1989_Siliconix_Low_Power_Discretes_Data_Book 1989 Siliconix Low Power Discretes Data Book

User Manual: 1989_Siliconix_Low_Power_Discretes_Data_Book

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General Information _
Cross Reference . . .
Selector Guide . .

JFETs . .
DMOSa
Low Power MOS _
Performance Curves _
Package Outlines . .
Applications . .
Worldwide Sales Offices and Distributors

Dill

1989
LOW POWER DISCRETES

DATA BOOK

g

Siliconix

inc[]rp[]rated

~Siliconix

~ incorporated

SlIIconix Incorporated reserves the right to make changes In the circuitry or
specifications at any time without notice and assumes no responsibility for the use of
any circuits described herein and makes no representations that they are free from
patent Infringement.

Warning Regarding Life Support Applications
SlIIconlx products are not sold for applications In any medical equipment Intended for use
as a component of any life support system unless a specific written agreement
pertaining to such Intended use Is executed between the manufacturer and SlIIconlx.
Such agreement will require the eqUipment manufacturer either to contract for additional
reliability testing of the SlIIconlx parts and/or to commit to undertake such testing as a
part of Its manufacturing process. In addition, such manufacturer must agree to
Indemnify and hold SlIIconlx harmless from any claims arising out of the use of the
Sillconlx parts in life support equipment.

Stresses listed under' Absolute Maximum Ratings' may be applied (one at a time) to
devices without resulting In permanent damage. This Is a stress rating only and not
subject to production testing. Exposure to absolute maximum rating conditions for
extended periods may effect device reliability.

@1989 SlIIconlx Incorporated
Printed In U.S.A.

.HSiliconix

incorporated

TABLE OF CONTENTS
Section 1.

General Information
Device Ordering Information ........................................... 1-1
Hi-Rei Process Capabilities ............................................ 1-2

Section 2.

Cross Reference .................................................... 2-1

Section 3.

Selector Guide
Introduction to Selector Guide ......................................... 3-1
JFET Selector Guide ................................................. 3-2
Low Power MOS Selector Guide ....................................... 3-35

Section 4.

JFETs
Introduction to JFETs ................................................. 4-1
2N3819 ............................................................ 4-2
2N3956 Series ...................................................... 4-4
2N4091 Series - JANTX. JANTXV ...................................... 4-6
2N4117 Series ...................................................... 4-8
2N4220 Series ..................................................... 4-11
2N4338 Series ..................................................... 4-14
2N4391 Series ..................................................... 4-17
2N4416 Series ..................................................... 4-19
2N4856 Series - JANTX. JANTXV ..................................... 4-21
2N4856A Series .................................................... 4-24
2N4867 Series ..................................................... 4-27
2N5114 Series ..................................................... 4-30
2N5114 Series - JANTX. JANTXV ..................................... 4-32
2N5196 Series ..................................................... 4-34
2N5432 Series ..................................................... 4-37
2N5460 Series ..................................................... 4-39
2N5484 Series ..................................................... 4-42
2N5564 Series ..................................................... 4-44
2N5638 Series ..................................................... 4-46
2N5911 Series ..................................................... 4-48
2N6905 Series ..................................................... 4-50
2N6908 Series ..................................................... 4-52
BF244 Series ...................................................... 4-54
BF245 Series ...................................................... 4-56
BSR56 Series ...................................................... 4-58
CR022 Series ...................................................... 4-60
CRR0240 Series .................................................... 4-62
DPAD1 Series ...................................................... 4-64

.r-Siliconix

~ incorporated

Section 4.

JFETs (Cont'd)

J105 Series ........................................................ 4-66
J 108 Series ........................................................ 4-68
J111 Series ........................................................ 4-71
J111A Series ...................................................... 4-73
J174 Series ........................................................ 4-75
J201Series ........................................................ 4-78
J210 Series ........................................................ 4-81
J230 Series ........................................................ 4-83
J270 Series ........................................................ 4-85
J304 Series ........................................................ 4-87
J308 Series ........................................................ 4-89
J500 Series ........................................................ 4-91
J552 .............................................................. 4-93
J553 Series ........................................................ 4-95
JPAD5 Series ...................................................... 4-97
JR135V Series ..................................................... 4-99
M440 Series ...................................................... 4-1 01
M5911 Series ..................................................... 4-1 03
P1086 Series ..................................................... 4-105
PAD1 Series ...................................................... 4-107
PN4091 Series .................................................... 4-1 09
PN4117 Series ......................................... : .......... 4-111
PN4302 Series .................................................... 4-114
PN4391 Series .................................................... 4-116
PN4416 Series .................................................... 4-118
SST1 08 Series .................................................... 4-120
SST111 Series .................................................... 4-122
SST174 Series .................................................... 4-124
SST201 Series ..................................................... 4-127
SST270 Series .................................................... 4-130
SST308 Series .................................................... 4-132
SST404 Series .................................................... 4-134
SST440 Series .................................................... 4-136
SST4091 Series ................................................... 4-138
SST4391 Series ................................................... 4-140
SST4416 ......................................................... 4-142
SST4859 Series ................................................... 4-144
SST5114 Series ................................................... 4-146
SST5912 ......................................................... 4-148
SST6908 Series ................................................... 4-150
SSTDPAD5 Series .................................................. 4-152
SSTPAD5 Series ................................................... 4-154

fCrSiliconix

~ incorporated

Section 4.

JFETs (Cont'd)
U290 Series ...................................................... 4-156
U308 Series ...................................................... 4-158
U350 ............................................................ 4-160
U401 Series ...................................................... 4-162
U421 Series ...................................................... 4-165
U430 Series ...................................................... 4-1 68
U440 Series ...................................................... 4-1 70
U443 Series ...................................................... 4-172
U1897 Series ..................................................... 4-174
VCR2N, VCR4N, VCR7N, VCR3P ..................................... 4-176

Section 5.

DMOS
Introduction to OMOS ................................................. 5-1
2N7104 Series ...................................................... 5-2
2N7105 Series ...................................................... 5-4
2N7116 Series ...................................................... 5-6
S02100E Series ..................................................... 5-8
802110E 8eries .................................................... 5-10
80/SST2100 Series ................................................. 5-12
805000 Series ..................................................... 5-14
805400 Series ..................................................... 5-16
8i8901 Series ...................................................... 5-18
8ST211 Series ..................................................... 5-20

Section 6.

Low Power MOS
Introduction to Low Power MOS ........................................ 6-1
2N6659 ............................................................ 6-2
2N6660 ............................................................ 6-4
2N6660 JANTX, JANTXV .............................................. 6-6
2N6661 ............................................................ 6-8
2N6661 JANTX, JANTXV ............................................. 6-10
2N7000 ........................................................... 6-1 2
2N7001 ........................................................... 6-14
2N7002 ........................................................... 6-16
2N7007 ........................................................... 6-18
2N7008 ........................................................... 6-20
3N163 Series ...................................................... 6-22
BS107 ............................................................ 6-24
BS170 ............................................................ 6-26
BS208 ............................................................ 6-28
BS250 ............................................................ 6-30
BSS89 ............................................................ 6-32
BSS92 ............................................................ 6-34

.:r-Siliconix

~ incorporated

Section 6.

Low Power MOS (Cont'd)
BSS129 ........................................................... 6-36
MFE823

.......................................................... 6-38

ND2012 Series ..................................................... 6-40
ND2020 Series ..................................................... 6-42
ND2406 Series ..................................................... 6-44
ND2410 Series ..................................................... 6-46
TP0610 Series ..................................................... 6-48
VN40AFD .......................................................... 6-51
VN46AFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53
VN66 Series ....................................................... 6-55
VN67 Series ....................................................... 6-57
VN88 Series ....................................................... 6-59
VN90AB ........................................................... 6-61
VN0300 Series ..................................................... 6-63
VN0603 Series ..................................................... 6-65
VN0605T .......................................................... 6-67
VN0610L, VN10KE, VN10KM .......................................... 6-69
VN0610LL, VN10LE, VN10LM ......................................... 6-71
VN0808 Series ..................................................... 6-73
VN1206B, VN1206D ..................................•.............. 6-75
VN1206L, VN1206M ...........................................•..... 6-77
VN1210 Series ..................................................... 6-79
VN1706B, VN1706D ................................................. 6-81
VN1706L, VN1706M ................................................. 6-83
VN1710 Series ..................................................... 6-85
VN2010 Series ..................................................... 6-87
VN2222KM, VN2222L ................................................ 6-89
VN2222LL. VN2222LM ............................................... 6-91
VN2406B. VN2406D ................................................. 6-93
VN2406L. VN2406M ................................................. 6-95
VN2410 Series ..................................................... 6-97
VN4012 Series ......................................•.............. 6-99
VN45350 Series .....................................•............. 6-101
VN50300 Series ................................................... 6-103
VP0300 Series .................................................... 6-1 05
VP061 0 Series .................................................... 6-107
VP0808 Series .................................................... 6-110
VP1008 Series ......................................•............. 6-112
VP2020 Series .................................................... 6-114
VP2410 Series .................................................•.. 6-116
VQ1000 Series .................................................... 6-118
VQ1001 Series .................................................... 6-120

~SilicDnix

~ incorporated

Section 6.

Low Power MOS (Cont' d)
VQ1004 Series .................................................... 6-122
VQ1006 Series .................................................... 6-124
VQ2000 Series .................................................... 6-126
VQ2001 Series .................................................... 6-128
VQ2004 Series .................................................... 6-130
VQ2006 Series .................................................... 6-132
VQ3001 Series .................................................... 6-134
VQ7254 Series .................................................... 6-136

Section 7.

Performance Curves
DMCA/B ........................................................... 7-1
DMCD ............................................................. 7-5
MRA ............................................................... 7-9
NBB .............................................................. 7-12
NCB .............................................................. 7-16
NCL .............................................................. 7-22
NH ............................................................... 7-25
NiP ............................................................... 7-30
NKL .............................................................. 7-35
NKM .............................................................. 7-38
NKO .............................................................. 7-41
NNR .............................................................. 7-44
NNT .............................................................. 7-48
NNZ .............................................................. 7-52
NPA .............................................................. 7-56
NQP .............................................................. 7-60
NRL .............................................................. 7-64
NT ............................................................... 7-69
NVA .............................................................. 7-73
NZB .............................................................. 7-77
NZF .............................................................. 7-82
PSCIA ............................................................ 7-87
PSCIB ............................................................ 7-91
VDDQ20

.......................................................... 7-95

VDDV24 ........................................................... 7-99

VNDB24 .......................................................... 7-103
VNDN24 .......................................................... 7-108
VND050 .......................................................... 7-113

VNDP06 .......................................................... 7-118
VNDQ03 .......................................................... 7-123
VNDQ06 .......................................................... 7-128
VNDQ09 .......................................................... 7-133

~SilicDnix
incorporated

..LII
Section 7.

Performance Curves (Cont'd)
VNDQ12 .......................................................... 7-138
VNDQ20 .................................••..•........ , ........... 7-143
VNDS06 •......................................................... 7-148
VNDV40 .......................................................... 7-153
VNMA06 ......................................................... 7-158
VNMA09 ......................................................... 7-163
VPDQ20 .......................................................... 7-168
VPDS06 .......................................................... 7-173
VPDV10 .......................................................... 7-178
VPDV24 .......................................................... 7-183
VPMH03 .......................................................... 7-188
VRMA ........................................................... 7-193

Section 8.

Package Outlines ................................................... 8-1

Section 9.

Applications
LPD-1:

An Introduction to FETs ...................................... 9-1

LPD-2

Understanding JFET Parameters . . . . . . . . . . . . . . . . . . . . . . . • . . . . . .. 9-9

LPD-3:

FET Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-17

LPD-4:

High JFET Gate Input Resistance Serves Well - If You Can Utilize It 9-29

LPD-5:

Audio-Frequency Noise Characteristics of Junction FETs ......... 9-33

LPD-6:

JFET~

LPD-7:

Designing Junction FET Input Op Amps ........................ 9-53

LPD-8:

Preventing Latch-Up in Monolithic Dual JFETs ................... 9-73

LPD-9:

Applications for the 2N6908 Series JFET Amplifier ............... 9-76

for Video Amplifiers .................................. 9-42

LPD-10: Analog Switching Using FETs ................................ 9-81
LPD-11: Subnanosecond Switching With DMOS FETs ................... 9-100
LPD-12: High-Speed Depletion-Mode DMOS FET for
Small-Signal Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-107
LPD-13: DMOS - Understanding the Body Effect ...................... 9-112
LPD-14: Designing FET Balanced Mixers for High Dynamic Range ........ 9-114
LPD-15: The FET Constant-Current Source ........................... 9-146
LPD-16: Low-Power MOSFETs for "Smart" Telephones ................. 9-149
LPD-17: P-Channel MOSFETs The Best Choice For High-Side Switching ... 9-154
LPD-18: Depletion-Mode MOSFETs Expand Circuit Opportunities .......... 9-157
LPD-19: Applying MOSFETs in Low Voltage Circuits ...... . . . . . . . . . . . . .. 9-163
LPD-20: An Ultra-Broadband Analog Switch ........................... 9-167
LPD-21: A High Quality Audio Crosspoint Switch ....................... 9-170
Section 10.

Worldwide Sales Offices and Distributors .............................. 10-1

.HSiliconix

incorporated

ALPHA-NUMERIC INDEX
2N3819

4-2

2N4861 .... . . ..

4-21

2N5566 .... . . ..

4-44

BF244B

4-54

2N3956

4-4

2N4861 A ......

4-24

2N5638 .... . . ..

4-46

BF244C

4-54

2N3957

4-4

2N4867 . . . . . . ..

4-27

2N5639 .... . . ..

4-46

BF245A

4-56

2N3958

4-4

4-46

BF245B

4-56

2N5911 ........

4-48

BF245C

4-56

2N4867A ......
2N4868 . . . . . . ..

4-27

2N4091

4-6

2N4092

4-6

2N4868A ......

4-27

2N5912 ........

4-48

B8107

6-24

2N4093

4-6

2N4869 . . . . . . ..

4-27

2N6660 . . . . . . . ..

6-2

B8170

6-26

2N4117

4-8

2N4869A ......

4-27

2N6660 .. . . . . . ..

6-4

B8208

6-28

6-6

B8250

6-30

B8R56

4-58

B8R57

4-58

B8R58

4-58

B8889 .........

6-32

2N4117 A ........ 4-8

2N5114 . . . . . . ..

4-27

2N5640 .... . . ..

4-30

2N6660 JAN . . . ..

2N4118 ......... 4-8

2N5114JAN ....

4-32

2N6660 JANTX . ..

6-6

2N411 8A ........ 4-8

2N5114JANTX ..

4-32

2N6660 JANTXV "

6-6

2N4119 ......... 4-8

2N5114JANTXV.

4-32

2N6661 .........

6-8

2N4119A ........ 4-8

2N5115 ........

4-30

2N6661 JAN....

6-10

2N4220 ........ 4-11

2N5115JAN ....

4-32

2N6661 JANTX ..

6-10

2N4220A ....... 4-11

2N5115JANTX .,

4-32

2N6661 JANTXV.

6-10

2N4221 ........ 4-11

2N5115JANTXV.

4-32

2N6905 . . . . . . ..

4-50

2N4221A ....... 4-11

2N5116 ....... ,

4-30

2N6906 . . . . . . ..

4-50

2N4222 ........ 4-11

2N5116JAN ....

4-32

2N6907 .. . . . . ..

4-50

2N4222A ....... 4-11

2N5116JANTX .,

4-32

2N6908 .. . . . . ..

4-52

2N4338 ........ 4-14

2N5116JANTXV.

4-32

2N6909 .. . . . . ..

4-52

2N4339

4-14

2N5196 ........

4-34

2N6910 .. . . . . ..

4-52

2N4340

4-14

2N5197 . . . . . . ..

4-34

2N7000 .. . . . . ..

6-12

2N4341

4-14

2N5198 . . . . . . ..

4-34

2N7001 ........

6-14

2N4391

4-17

2N5199 ........

4-34

2N7002 ........

6-16

B8892 ......... 6-34
B88129 ........

6-36

CR022

4-60

CR024

4-60

CR027

4-60

CR030

4-60

CR033

4-60

CR039

4-60

CR043

4-60

CR047

4-60

CR056

4-60

CR062

4-60

2N4392

4-17

2N5432 . . . . . . ..

4-37

2N7007 . . . . . . ..

6-18

CR068

4-60

2N4393

4-17

2N5433 . . . . . . ..

4-37

2N7008 . . . . . . ..

6-20

CR075

4-60

2N4416

4-19

2N5434 . . . . . . ..

4-37

2N7104 . . . . . . . ..

5-2

CR082

4-60

2N4416A ....... 4-19

2N5460 . . . . . . ..

4-39

2N7105 .........

5-4

CR091

4-60

2N4856 ........ 4-21

2N5461 .. . . . . ..

4-39

2N7106 ....... "

5-2

CR100

4-60

2N4856A ....... 4-24

2N5462 . . . . . . ..

4-39

2N7107 . .... ....

5-4

CR110

4-60

2N4857 ........ 4-21

2N5463 . . . . . . ..

4-39

2N7108 ....... "

5-2

CR120

4-60

2N4857A ....... 4-24

2N5464 . . . . . . ..

4-39

2N7109 ....... "

5-4

CR130

4-60

2N4858 ........ 4-21

2N5465 ....... ,

4-39

2N7116 ....... "

5-6

CR140

4-60

2N4858A ....... 4-24

2N5484 ....... ,

4-42

2N7117 ....... "

5-6

CR150

4-60

2N4859 ........ 4-21

2N5485 . . . . . . ..

4-42

2N7118 ....... "

5-6

CR160

4-60

2N4859A ....... 4-24

2N5486 ....... ,

4-42

3N163 .... . . . ..

6-22

CR180

4-60

2N4860 ........ 4-21

2N5564 . . . . . . ..

4-44

3N164 .... . . . ..

6-22

CR200

4-60

2N4860A ....... 4-24

2N5565 ....... ,

4-44

BF244A . . . . . . ..

4-54

CR220

4-60

~Siliconix

..1;;11 incorporated

CR240

4-60

J202 ..... . . . ..

4-78

JR170V ........

4-99

CR270

4-60

J203 ..........

4-78

JR200V ...... ..

4-99

S0211 ......... 5-10

CR300

4-60

J204 .. . . . . . . ..

4-78

JR220V ... . . . ..

4-99

S0212 .......... 5-8

CR330

4-60

J210 ..... . . . ..

4-81

JR240V ...... ..

4-99

S0213 ......... 5-10

CR360

4-60

J211 ..........

4-81

M440 .........

4-101

S0214 .......... 5-8

CR390

4-60

J212 ..........

4-81

M441 .........

4-101

S0215

5-10

CR430

4-60

J230 ..........

4-83

M5911 ........

4-103

S02100

5-12

CR470 ......... 4-60

J231 ..........

4-83

M5912 ........

4-103

S05000

5-14

6-38

S05001

5-14

6-40

S05002

5-14

6-40

S05400

5-16

CR530 ......... 4-60
CRR0240 ....... 4-62

J232 " . . . . . . ..
J270 ..... . . . ..

4-83
4-85

MFE823 . . . . . . ..
N02012E . . . . . ..

S0210 .......... 5-8

CRR0360

4-62

J271 ..........

CRR0560

4-62

J304 .. . . . . . . ..

4-87

N02020E . . . . . ..

6-42

S05401

5-16

CRR0800

4-62

J305 ....... . ..

4-87

N02020L . . . . . ..

6-42

S05402

5-16

Si8901 ......... 5-18

4-85

N02012L . . . . . ..

CRR1250 ....... 4-62

J308 ..... . . . ..

4-89

N02406B . . . . . ..

6-44

CRR1950

J309 ....... . ..

4-89

N02406L . . . . . ..

6-44

4-62

CRR2900 ....... 4-62

J310 " . . . . . . ..

4-89

N02410B . . . . . ..

CRR4300 ....... 4-62

J500 ..........

4-91

N02410L . . . . . ..

OPAOl ......... 4-64

J501 ..........

4-91

Pl086 ........

OPA02 ......... 4-64
OPA05 ......... 4-64
OPA010 ........ 4-64
OPA020 ........ 4-64

J502 ..........
J503 " . . . . . . ..
J504 .. . . . . . . ..

4-91
4-91
4-91

6-46
6-46
4-105

Pl087 ........

4-105

PAOl . . . . . . . ..

4-107

PAOlO. . . . . . ..

4-107

SST108

4-120

SST109

4-120

SSTll0

4-120

SSTlll

4-122

SSTl12

4-122

SSTl13

4-122

SST174

4-124

SST175

4-124

SST176

4-124

SSTl77

4-124

SST201

4-127

SST202

4-127

SST203

4-127

SST204

4-127

SST211

5-20

J505 ....... . ..

4-91

PA0100 .......

4-107

OPA050 . . . . . . .. 4-64

J506 .. . . . . . . ..

4-91

PA02 . . . . . . . ..

4-107

OPA0100 . . . . . .. 4-64

J507 ..... . . . ..

4-91

PA020 ........

4-107

Jl05 ........... 4-66

J508 ... . . . . . ..

4-91

PA05 . . . . . . . ..

4-107

Jl06 ........... 4-66

J509 ..........

4-91

PA050 . . . . . . ..

4-107

Jl07 ........... 4-66

J510 .. . . . . . . ..

4-91

PN4091 .......

4-109

Jl08 ........... 4-68

J511 ..........

4-91

PN4092 .......

4-109

Jl09 . . . . . . . . . .. 4-68

J552 .. . . . . . . ..

4-93

PN4093 " . . . ..

4-1 09

Jll0 ........... 4-68

J553 ..........

4-95

PN4117 .......

4-111

Jll0A ......... 4-68

J554 ....... . ..

4-95

PN4117A . . . . ..

4-111

SST270

4-130

Jlll ........... 4-71

J555 ...... . . ..

4-95

PN4118 .. . . . ..

4-111

SST271

4-130

JlllA ......... 4-73

J556 ..........

4-95

PN4118A . . . . ..

4-111

SST308

4-132

Jl12 ......... "

4-71

J557. . . . . . . . ..

4-95

PN4119 .. . . . ..

4-111

SST309

4-132

Jl12A ......... 4-73

JPA05 ........

4-97

PN4119A . . . . ..

4-111

SST31 0

4-132

Jl13 ........... 4-71

JPA010

4-97

PN4302 ..... ..

4-114

SST404

4-134

Jl13A ......... 4-73

JPA020 .......

4-97

PN4303 .......

4-114

SST405

4-134

J174 ........... 4-75

JPA050.......

4-97

PN4304 .. . . . ..

4-114

SST406

4-134

J175 . . . . . . . . . .. 4-75

JPA0100

4-97

PN4391 .......

4-116

SST440

4-136

J176 . . . . . . . . . .. 4-75

JPA0200. . . . ..

4-97

PN4392 .. . . . ..

4-116

SST441

4-136

J177 ........... 4-75

JPA0500 ......

4-97

PN4393 .. . . . ..

4-116

SST2100 ....... 5-12

J201 . . . . . . . . . .. 4-78

JR135V . . . . . . ..

4-99

PN441 6 . . . . . ..

4-118

SST4091 ...... 4-138

SST213 ........ 5-20
SST215 ........ 5-20

ICrSiliconix

~ incorporated

88T4092

4-138

U403 .. . ......

4-162

VN1206M......

6-77

VP0300B

88T4093

4-138

U404.........

4-162

VN1210l .......

6-79

VP0300l

6-105

88T4391

4-140

U405 .........

4-162

VN1210M ......

6-79

VP0300M . . . . ..

6-105

88T4392

4-140

U406 . . . . . . . ..

4-162

VN1706B . . . . . ..

6-81

88T4393

4-140

U421.........

4-165

VN1706D.......

6-81

6-105

VP0610E

6-107

VP0610l

6-107

VP0610T

6-107

88T4416

4-142

U422 . . . . . . . ..

4-165

VN1706l . . . . . ..

6-83

88T4859

4-144

U423 . . . . . . . ..

4-165

VN 1706M ......

6-83

88T4860

4-144

U424 . . . . . . . ..

4-165

VN 171 Ol . . . . . ..

6-85

VP0808B

6-110

88T4861

4-144

U425 .........

4-165

VN1710M ......

6-85

VP0808l

6-110

88T5114

4-146

U426 . . . . . . . ..

4-165

VN2010ll. . . . ..

6-87

VP0808M. . . . ..

6-110

88T5115

4-146

U430 . . . . . . . ..

4-168

VN2020l . . . . . ..

6-87

VP1008B

6-112

VP1008l

6-112

88T5116

4-146

U431 .........

4-168

VN2222KM .....

6-89

88T5912

4-148

U440 ....... ..

4-170

VN2222l . . . . . ..

6-89

88T6908

4-150

U441. . . . . . . ..

4-170

VN2222ll. . . . ..

6-91

88T6909

4-150

U443 . . . . . . . ..

4-172

VN2222lM. . . ..

6-91

88T6910

4-150

U444 . . . . . . . ..

4-172

VN2406B . . . . . ..

6-93

88TDPAD5 .... 4-152

U1897 . . . . . . ..

4-174

VN2406D . . . . . ..

6-93

VP1008M ...... 6-112
VP2020l

6-114

VP2410B

6-116

VP2410l

6-116
6-118

VN2406l . . . . . ..

6-95

VQ1000J

4-174

VN2406M ......

6-95

VQ1000P ...... 6-118

4-176

VN2410l . . . . . ..

6-97

VQ1001J ...... 6-120

VCR3P

4-176

VN2410M ......

6-97

VQ1001P ......

4-154

VCR4N

4-176

VN3515l . . . . . ..

6-99

VQ1004J ...... 6-122

88TPAD10 ..... 4-154

VCR7N

4-176

VN4012B . . . . . ..

6-99

88TPAD20 . . . .. 4-154

VN0300B

6-63

VN4012l . . . . . ..

6-99

88TPAD50 . . . .. 4-154

VN0300l

6-63

VN40AFD ......

6-51

88TPAD100 .... 4-154

VN0300M

6-63

VN45350l . . . ..

6-101

88TPAD200 . . .. 4-154

VN0603l

6-65

VN45350T .....

6-101

88TPAD500 . . .. 4-154

VN0603T

6-65

VN46AFD ......

88TDPAD10

4-152

U1898 . . . . . . ..

4-174

88TDPAD20 ... 4-152

U1899 ........

88TDPAD50 ... 4-152

VCR2N

88TDPAD100 .. 4-152
88TPAD5 . . . . ..

Tl0610l . . . . . . ..

6-53

6-120

VQ1004P ...... 6-122
VQ1006J ...... 6-124
VQ1006P ......

6-124

VQ2000J ...... 6-126
VQ2000P . . . . ..

6-126

6-48

VN0605T

6-67

VN50300l . . . ..

6-1 03

VQ2001J ...... 6-128

TP061 DE ....... 6-48

VN0610l

6-69

VN50300T . . . ..

6-103

VQ2001 P . . . . ..

TP0610T ....... 6-48

VN0808l

6-73

VN610ll . . . . . ..

6-71

U290 ......... 4-156

VN0808M

6-73

VN66AD .......

6-55

U0291 ........ 4-156

VN10KE ...... .

6-69

VN66AFD ......

6-55

U308

VN10KM .......

6-69

VN67AB .......

6-57

4-158

U309

4-158

VN10lE .......

6-71

VN67 AD .......

6-57

U310

4-158

VN10lM .......

6-71

VN67 AFD ......

6-57

6-128

VQ2004J ......

6-130

VQ2004P .. . . ..

6-130

VQ2006J ...... 6-132
VQ2006P ...... 6-132
VQ3001 J ......

6-134

U350

4-160

VN1206B

6-75

VN88AD .......

6-59

VQ3001 P . . . . ..

6-134

U401

4-162

VN1206D

6-75

VN88AFD ......

6-59

VQ7254J ......

6-136

U402

4-162

VN1206l

6-77

VN90AB .......

6-61

VQ7254P . . . . ..

6-136

.HSiliconix

incorporated

NUMERIC-ALPHA INDEX
DPAD ........... 4-64
PAD1

........ .

4-107

........ .

... .

4-154

J111A

SSTDPAD50 ...

4-152

SST111

SSTPAD50

...... .
. .........

DPAD2 •.... , ... 4-64

BSR56

. .......

4-58

J112

........ .

4-1'07

CR056

....... .

4-60

J112A

VCR2N ........ 4-176

BSR57

....... .

4-58

SST112 .......

PAD2

VCR3P ........ 4-176

BSR58

VCR4N ........ 4-176

CR062

DPAD5 ......... 4-64

VN66AD

........ ,

JPAD5
PAD5

........ .

4-97
4-107

SSTPAD5 ...... 4-154
SSTDPAD5

....

4-152

....... .
. .......

4-58

J113

.........
......... .
. ........

4-60

J113A

.. , ....

6-55

SST113 .......

..... .

6-55
6-57

VN66AFD

...... .
VN67AD ...... .
VN67AFD ... , ..

VN67AB

4-73

BS208

4-122

SD210

4-71

J210 ........... 4-81

4-73

J211 ........... 4-81

4-122

4-73
4-122

SD212

. .........

5-8

CR120 .........

4-60

SD213

..... , ...

5-10

BS8129 ........

6-36

SST213

........

5-20

4-60

SD214

6-57

CR130 .........

6-57

JR135V

. ...... ,

4-99

4-60

CR140 .........

4-60

....... .

CR075

....... .

4-60

CR150 .........

4-60

4-60

CR160 .........

4-60

6-59

3N163

.........

6-22

6,-59

3N164 .........

6-22

........

6-32

BS170 .........

6-26

.......

6-61

JR170V

. .......

4-99

6-69

.......
CR082
VN88AD .......
VN88AFD ......

VN10KM ........

6-69

BSS89

...... , .

6-71

VN90AB

VN10LM ........

6-71

CR091

..... , ..

4-60

J174

SSTPAD10 •.... 4-154

BSS92

........

6-34

8ST174 .......

CR100

........

4-60

J175

4-64

SST175 .......

4-97

J176

JPAD10
VN10KE

VN10LE

....... ,
....... .

S8TDPAD10

.. .

4-97

4-152

DPAD20 ........ 4-64
JPAD20
PAD20

....... , 4-97
........ 4-107

SSTPAD20 ..... 4-154
SSTDPAD20
CR022

...

........ .

4-152

,

DPAD100
JPAD100
PAD100

......
. .....

. .........
. .........

. .........

4-107

SST176 .......

...

4-154

J177

SSTDPAD100 ..

4-152

SST177 .......

S8TPAD100

4-66

4-60

J106

..........
. .........

4-60

BS107 .........

4-60
4-60

4-124
4-75
4-124
4-75
4-124
4-75
4-124

J230 ........... 4-83
J231 ........... 4-83
J232 •.......... 4-83

.........
.......
JR240V ..... ,. ,
BF244A ........

CR240

4·60

CRR0240

4-62

........

4-56

BF245C

........

4-56

.........

6-30

BS250

CR200 .........

4-60

CR270

4-97

J107 ..........

4-66

JR200V

J108 ..........

4-68

. .......
. ..

SST270

SSTPAD200

4-154

4-60

SST108 .......

4-120

VN40AFD .......

6-51

J109

.........

4-60

SST109 .......

CR039

CR043

.........

.........
.........

..........

4-68
4-120

. ......... 4-78
SST201 . ...... 4-127

J201

J202

. .........

VN46AFD .......

6-53

CR110

........

4-60

SST202 .......

.........

4-60

J110 ..........

4-68

J203

DPAD50 ........ 4-64

J110A .........

4-68

SST203 .......

SST110 .......

4-120

CR047

JPAD50
PAD50

........ 4-97
........ 4-107

J111

. .........

4-71

4-99

J204

. .........

. .........

SST204 .......

4-78
4-127
4-78
4-127
4-78
4-127

4-54

BF245A

JPAD200 .......

CR033

4-54

BF245B

6-24

CR030

4-99

........
........

BF244C

4-66

.........
.........

........

BF244B

4-60

CR027

J105

. .........

4-75

. ......... 5-8
SD215 ......... 5-10
SST215 . ....... 5-20
CR220 ......... 4-60
JR220V ........ 4-99

CR180 .........

CR024

4-60

5-20

J212 ........... 4-81

....... .

4-107

5-10

4-71

CR068

DPAD10 ........ 4-64

.......

........

SD211 .,
SST211

VCR7N ........ 4-176
PAD10

......... 6-28,
.......... 5-8

4-54
4-56

J270 ........... 4-85

. ........

4-60

. ......

4-130

J271 ........... 4-85

. ......

SST271
U290
U291

. ........
. ........

VN0300B
VP0300B
CR300

4-130
4-156
4-156

. ...... 6-63
. ..... 6-105

. ........

4-60

......

6-63

VN0300LO

VN0300M ....... 6-63
VP0300L

. .....

6-105

.:rSiliconix

~ incorporated

VP0300M . . .... 6-105

J500.. .. .. ....

4-91

VQ1001J ......

6-120

VP2020E

6-114

J304 . . . . . . . . . .. 4-87

JPAD500. . . . ..

4-97

VQ1001P ......

6-120

VP2020L

6-114

J305 ........... 4-87

SSTPAD500. ..

4-154

VQ1004J ......

6-122

SD2100 ........ 5-12

J308 . . . . . . . . . .. 4-89

J501. . . . . . . . ..

4-91

VQ1004P......

6-122

SST2100 ....... 5-12

SST308 ....... 4-132

J502.. .. .. ....

4-91

VQ1006J . . . . ..

6-124

VN2222KM . . . . .. 6-89

U308 ......... 4-158

J503.. .. .. ....

4-91

J504. . . . . . . . ..

4-91

6-124
6-112

VN2222L ....... 6-89

J309 . . . . . . . . . .. 4-89

VQ1006P......
VP1008B ......

VN2222LL ...... 6-91

SST309 ....... 4-132

J505. . . . . . . . ..

4-91

VP1008L ......

6-112

VN2222LM ...... 6-91

U309 ......... 4-158

J506. . . . . . . . ..

4-91

VP1008M .....

6-112

ND2406B

4-105'

ND2406L ....... 6-44

6-44

J310 ........... 4-89

J507.. ........

4-91

Pl086 ........

SST310 ....... 4-132

J508.. .. .. ....

4-91

P1087 ........

4-105

VN2406B ....... 6-93

6-75

VN2406D. . . . . .. 6-93
VN2406L ....... 6-95

U310 ......... 4-158

J509..........

4-91

VN1206B . . . . . ..

CR330 ......... 4-60

J510 . . . . . . . . ..

4-91

VN1206D .......

6-75

U350 ......... 4-160

J511 ..........

4-91

VN1206L .......

6-77

CRR0360 ....... 4-62

CR530 ........

4-60

VN1206M ......

6-77

CR390 ......... 4-60

J552 ..........

4-93

VN1210L .......

6-79

U401 ......... 4-162

J553 ..........

4-95

VN1210M ......

6-79

U402 ......... 4-162

J554 .. ........

4-95

CRR1250 . . . . . ..

4-62

U403 ......... 4-162

J555 ..........

4-95

VN1706B . . . . . ..

6-81

VP2410L ...... 6-116

SST404 ....... 4-134

J556 ..........

4-95

VN1706D . . . . . ..

6-81

CRR2900 ....... 4-62

U404 ......... 4-162

J557 .. . . . . . . ..

4-95

VN1706L . . . . . ..

6-83

VQ3001J ...... 6-134

SST405 ....... 4-134

CRR0560

4-62

VN1706M ......

6-83

VQ3001P ...... 6-134

U405 ......... 4-162

VN0603L

6-65

VN1710L . . . . . ..

6-85

VN3515L ....... 6-99

SST406 ....... 4-134

VN0603T

6-65

VN1710M ......

6-85

2N3819 ......... 4-2

U406 ......... 4-162

VN0605T

6-67

U1897 ........

4-174

2N3956 ......... 4-4

U421

TP0610E . . . . . ..

6-48

U1898 ........

4-174

2N3957

4-174

2N3958

U422

4-165
4-165

TP0610L . . . . . ..

6-48

U1899 ........

U423

4-165

TP0610T . . . . . ..

6-48

CRR1950 . . . . . ..

4-62

U424

4-165

VN0610L ......

6-69

VQ2000J . . . . ..

6-126

U425 ......... 4-165

VN0610LL......

6-71

VQ2000P......

6-126

VN2406M . . . . . .. 6-95
ND2410B ....... 6-46
ND2410L ....... 6-46
VN2410L ....... 6-97
VN241 OM . . . . . .. 6-97
VP241 OB ...... 6-116

VN4012B

4-4
4-4
6-99

VN4012L ....... 6-99
2N4091 ......... 4-6
PN4091 ....... 4-109

U426 ......... 4-165

VP0610E .....

6-107

VQ2001J ......

6-128

CR430 ......... 4-60

VP0610L . . . . . .

6-107

VQ2001P......

6-128

U430 •..•..... 4-168

VP0610T ......

6-107

VQ2004J . . . . ..

6-130

U431 ......... 4-168

CRR0800

4-62

VQ2004P . . . . ..

6-130

M440 ......... 4-101

VP0808B

6-110

VQ2006J. . . . ..

6-132

SST440 ....... 4-136

VN0808L

6-73

VQ2006P......

6-132

PN4093 ....... 4-1 09
SST4093 ...... 4-138
PN4116 ....... 4-118

M441 ......... 4-101

VN0808M

6-73

VN2010L . . . . . ..

6-87

SST441 ....... 4-136

VP0808L......

6-110

ND2012E .......

6-40

U441

VP0808M .....

6-110

ND2012L . . . . . ..

6-40

MFE823. . . . . ..

6-38

ND2020E . . . . . ..

6-42

4-170

U443 ......... 4-172

SST4091 ...... 4-138
2N4092 ......... 4-6
PN4092 ....... 4-109
SST4092 ...... 4-138
2N4093 ......... 4-6

2N4117 ......... 4-8
2N4117 A ........ 4-8

U444 ......... 4-172

VQ 1OOOJ

6-118

ND2020L . . . . . ..

6-42

PN4117. . . . . .. 4-111

CR470 ......... 4-60

VQ1000P .....

6-118

VN2020L .......

6-87

PN4117A ...... 4-111

H'Siliconix
incorporated
2N4118
2N4118A
PN4118
PN4118A

........ . 4-8
....... . 4-8
...... . 4-111
..... . 4-111

2N4857 ........

4-21

SST5116 ......

..... .

4-24

2N5196

2N4858 ........

4-21

2N5197

..... .

4-24

2N5198

2N4859 ........

4-21

2N5199

4-24

805400 ........

5-16

........

5-16
5-16

2N4857A
2N4858A

........ . 4-8
2N4119A ....... . 4-8
PN4119 ...... . 4-111
PN4119A ...... 4-111
2N4220 ....... . 4-11
2N4220A ...... . 4-11
2N4221 ....... . 4-11
2N4221A ...... . 4-11
2N4222 ....... . 4-11

S8T4861 ......

2N4222A

4-11

2N4867 ........

4-27

4-62

2N4867A

..... .

4-27

2N4119

CRR4300

...... .

2N4859A

......

S8T4859 ......

4-144

2N4860 ........

4-21

805402 ........

..... .

4-24

4-148

4-32

88T5115 ......

4-146

6-6

VN45350L

6-6

VN45350T

6-101
6-103
6-103

2N4869 ........

4-27

..... .

4-27

4-14

2N4869A

4-14

805000

4-14

805001

2N4856A

...... .

5-14
5-14

4-14

S05002

...... .
...... .

4-17

2N5114 ........

4-30

4-116

... .
2N5114JANTX · .

4-32

....... . 4-21
4-24

2N6905

2N5115JANTXV

4-114

2N4856

. ....... 4-50
2N6906 ........ 4-50
2N6907 ........ 4-50
2N6908 ........ 4-52
88T6908 ...... 4-150
2N6909 ........ 4-52
88T6909 ...... 4-150
2N6910 ........ 4-52
88T6910 . ..... 4-150
2N7000 . ....... 6-12
2N7001 . ....... 6-14
2N7002 . ....... 6-16
2N7007 ........ 6-18
2N7008 ........ 6-20
2N7104 ......... 5-2
2N7105 ......... 5-4
2N7106 ......... 5-2
2N7107 . ........ 5-4
2N7108 ......... 5-2
2N7109 . ........ 5-4
2N7116 . ........ 5-6
2N7117 . ........ 5-6
2N7118 . ........ 5-6
VQ7254J ...... 6-136

4-34

4-103

4-27

PN4304

...... 4-140
2N4392 ....... . 4-17
PN4392 ....... 4-116
88T4392 ...... 4-140
2N4393 ....... . 4-17
PN4393 ...... . 4-116
SST4393 ...... 4-140
2N4416 ........ 4-19
2N4416A ...... . 4-19
88T4416 ...... 4-142

4-34

6-10

88T5912 ......

4-27

PN4391

2N6661 JANTXV . 6-10

M5912 ........

4-144

..... .

88T4391

4-34

4-32

4-24

2N4868A

2N4391

6-10

4-30

4-21

4-114

2N4341

.
..

4-32

4-144

PN4303

2N4340

'"

2N6661 JANTX

....
2N5115JANTX · .

....... .
2N4861A ..... .
2N4861

2N4868 ........

2N4339

2N6661 JAN

4-34

2N5115 ........

88T4860 ......

4-114

....... .
....... .
....... .
....... .
....... .

4-146

........ 4-37
2N5433 ....... . 4-37
2N5434 ....... . 4-37
2N5460 ....... . 4-39
2N5461 ........ 4-39
2N5464 ........ 4-39
2N5462 ........ 4-39
2N5465 ........ 4-39
2N5484 ........ 4-42
2N5485 ........ 4-42
2N5486 ........ 4-42
2N5564 ........ 4-44
2N5565 . ....... 4-44
2N5566 ....... . 4-44
2N5638 ....... . 4-46
2N5639 ....... . 4-46
2N5640 . ....... 4-46
2N5911 ........ 4-48
M5911 . ....... 4-103
2N5912 ........ 4-48

2N4860A

PN4302

2N4338

805401

........
........
........
........

2N5114JAN

5-14

4-32

2N5114JANTXV

4-32

88T5114 ......

4-146

2N5115JAN

2N5432

VQ7254P ...... 6-136

2N5116 ........

4-30

. ........
2N6660 . ........
2N6660 JAN . ....

. ...
2N5116JANTX · .

~-32

2N6660 JANTX ...

4-32

2N6660 JANTXV ..

6-6

VN50300L

2N5116JANTXV

4-32

2N6661

.........

6-8

VN50300T

2N5116JAN

2N6659

6-2
6-4

8i8901

.........

5-18
6-101

General Information . .
Cross Reference
Selector Guide

JFETs
DMOS
Low Power MOS
Performance Curves
Package Outlines
Applications
Worldwide Sales Offices and Distributors

fCrSiliconix

~ incorporatec

LOW POWER DISCRETES
DEVICE ORDERING INFORMATION

TECHNOLOGY/DESIGN PREFIX-DEVICE FAMILY

PROCESS OPTION

SF

-European Transistor Standard Diode TO-92
Cased FET

-1 Contact Factory - 7S08 Visual, Mil-STO-7S0 Processing
(JANTXV)

CR

-SI Standard N-Channel Current Regulator

CRR

-SI Standard N-Channel Current Regulator

OM

-SI Special OM OS FET

DN

-SI Dual N-ChanneIJFET

FN

-SI N-ChanneIJFET

OPAO -SI Standard Dual JFET Diode
J

-SI Standard TO-92 Cased FET

JR

-SI Standard Current limiter

JPAO -SI Standard JFET Diode

-2 Contact Factory - 7S08 Visual, MIL-STD-7S0 Processing
(JANTX)
3 Contact Factory - 7S08 Visual, MIL-STD-7S0,
Group 8 and C

PACKAGE

-os Std TO-92

-18 Std TO-92 with Center Lead Formed Toward Flat
In TO-18 Pin Circle
- TR Tape and Reel Available on TO-92 FETs

MU

-SI Special MOSFET

-TA Tape and Ammo Pack Available on TO-92 FETs

NO

-SI Standard Low Power MOS

-T1, T2 Tape and Reel Available on SOT-23, SOT-143
and SOIC Products

PAD

-SI Standard JFET Diode

PN

-SI Standard TO-92 Cased FET

SO

-SI Standard DMOS FET

SST

-Surface Mount Device

U

-SI Standard FET

V

-SI Standard or Special Low Power MOS

VCR

-SI Standard N- and P-Channel Voltage
Controlled Resistors

2N

-JEDEC-Reglstered Device

3N

-JEDEC-Reglstered Device

-

Lead Formed to TO-S Pin Circle

1-1

.r-Siliconix

~ incorporated

Hi-Rei Process Capabilities
INTRODUCTION
For over twenty years Siliconix has actively participated in the Military/Hi-Rei marketplace. The company has
been a preferred source supplier on numerous major military programs with Low Power Discrete (LPD) devices
designed into land. air. sea and space systems.
LPD products are logical choices in Military/Hi Rei applications for several reasons. There are performance
benefits to be gained using LPD devices which cannot be matched with any other existing technology. LPD
devices are inherently radiation-hardened. as high as 6 X 105 RAD (Si). They perform reliably at cryogenic
temperatures proving they can operate as a "Focal Plane Preamp" at a liquid helium temperature of 3soK.
The LPD business unit is dedicated to serving the Military/Hi-Rei market and does so in five basic ways: QPL
(Qualified Parts List) devices. CECC devices. Standard Hi-Rei Process Flows. Hi-Rei "Specials". and Lockheed
Monitored Line devices.

QPL Devices (See Figure 1)
For ease of delivery and in keeping with the government trend towards standardized devices. the LPD product
line offers 16 QPL devices (with more QPL quais in progress). These are products qualified under Military
Specification Mil-S-19S00. the General Specification for Semiconductor Devices. Parts are purchased by specifying the appropriate Government Designation on the purchase order. The LPD business unit is continuously
evaluating the devices within its product line for candidates as additional QPL devices. Wherever a significant
need is demonstrated. the LPD Business Unit is committed to addressing that need by seeking QPL approval
from DESC.

CECC Devices (See Figure 2)
CECC SO 000 is the European system of electronic component approval in which product is released to internationally agreed detail specifications conforming to CECC rules. QPL listed products are built on an approved line
by a manufacturer who must comply with defined standards relating to organization. facilities and quality assurance procedures.
Throughout Europe CECC approved components are preferred items for all military and aerospace
programmes.

Standard Hi-ReI Processes (See Figure 3)
Where a QPL device does not exist. LPD offers the next best thing with its -1. -2 and LP3 process flows. The
-1 process flow provides many of the 100% screening steps for a JANTXV-Ievel device as called out in
Mil-S-19S00. U.S. Build is included. The -2 provides many of the 100% screening steps for a JANTX-Ievel device
as called out in MiI-S-19S00.
The LP3 process flow provides 100% processing similar to Mil-S-19S00 for a JANTX-Ievel device using Mil-S-7S0
test methods. Group A. B. and C testing is included. Portions of the 100% screening and/or the Quality Conformance Inspection testing may be performed at any of Siliconix' worldwide facilities.
Use of these standard processes can eliminate the need for a costly source control drawing. The processes can
be performed on any hermetic packaged LPD device. Devices are ordered by adding the -1. -2. -LPD3 as a
suffix to the standard part type (i.e. 2NS432-1. 2NS432-2. 2NS432-LP3).

1-2

.:rSiliconix

~ incorporated

Hi-ReI "Specials"
Where QPL, CECC, -1, -2 and LP3 won't do, LPD can provide processing based upon a customer source
control drawing or detail specification. Siliconix has built a reputation in the industry for its skill in manufacturing
such devices commonly referred to as "Specials". All MiI-S-19500/Mil-Std-750 requirements through JANTXVlevel processing can be provided. Baseline control, a "must" in many Military/Hi-Rei applications, is offered.
Our dedicated Program Management group can provide the coordination necessary to commandeer the more
complex specials through the factory.

Lockheed Monitored Line
Siliconix also offers Lockheed-monitored line parts. This means on-line process monitoring by a resident team of
quality & reliability engineers. With approval from the U.S. Air Force, this service can be used by any aerospace
company or government agency.

Conclusion
Since 1964 Siliconix has been regarded as a steady, reliable supplier to the Military/Hi-Rei market. We intend to
carry this reputation into the future by providing Military/Hi-Rei service you can rely on for many years to come .

..

1-3

.r-Siliconix

~ incorporated

Figure 1

LOW POWER DISCRETE
QUALIFIED PARTS LIST (QPL)
Products Qualified as Standard Devices under Military Specification
MiI-S-19500: Semiconductor Devices, General Specification For
GOVERNMENT
DESIGNATION
2N4091

2N4092

2N4093

2N4856

2N4857

2N4858

2N4859

2N4860

2N4861

2N5114

2N5115

2N5116

2N6661

2N6660

t
t
t
1-4

(JAN)
JANTX
JANTXV
(JAN)
JANTX
JANTXV
(JAN)
JANTX
JANTXV
(JAN)
JANTX
JANTXV
(JAN)
JANTX
JANTXV
(JAN)
JANTX
JANTXV
(JAN)
JANTX
JANTXV
(JAN)
JANTX
JANTXV
(JAN)
JANTX
JANTXV
(JAN)
JANTX
JANTXV
(JAN)
JANTX
JANTXV
(JAN)
JANTX
JANTXV
(JAN)
JANTX
JANTXV
(JAN)
JANTX
JANTXV

(CAGE)
SILICONIX
DESIGNATION (CODE)
TYPE NUMBER
CDSN
17856 (FSCM)

DETAIL SPECIFICATION
(SLASH SHEET)
MiI-S-19500/431

CDSN
17856 (FSCM)
CDSN
17856 (FSCM)
CDSN
17856 (FSCM)

MiI-S-19500/385

CDSN
17856 (FSCM)
CDSN
17856 (FSCM)
CDSN
17856 (FSCM)
CDSN
17856 (FSCM)
CDSN
17856 (FSCM)
CDSN
17856 (FSCM)

MiI-S-19500/476

CDSN
17856 (FSCM)
CDSN
17856 (FSCM)
CDSN
17856 (FSCM)

MiI-S-19500/547 A

CDSN
17856 (FSCM)

JANS:

JANTXV plus wafer lot acceptance and additional 1000/0 processing requirements. Includes Group 0 testing

JANTXV:

JANTX plus 1000/0 Internal visual Inspection

JANTX:

JAN plus 100% processing to MII-8-19500 Including Group AI 8, C testing

JAN:

Controlled lot with sample environmental and life testing

~SilicDnix

~ incorporated

Figure 2

LOW POWER DISCRETE
CECC 50 000 . QUALIFIED DEVICES
Additional Product Options for European Customers

At this time, member countries of the CECC (Cenelec Electronic Components Committee) are Belgium, Denmark, Germany, France, Ireland, Italy, the Netherlands, Norway, Sweden, Switzerland and the United Kingdom.
Specific device types are individually qualified against a fixed detail specification which has been approved by
the British Standards Institute (BSI) acting as the national supervising agency on behalf of CECCo
The CECC 50 000 scheme is administered in the UK by the BSI. The UK-generated specifications are prefixed
with the letters BS.
A number of industry preferred standard device types are now qualified and the following detail specifications
are available:

Type Number

BS Specification

Type Number

BS Specification

2N3824
2N4391 12/3
2N4856A/7 AlBA
2N4220/1/2
2N6659/60/61
2N5564/65/66

BS
BS
BS
BS
BS
BS

U430/U431
2N5432/3/4
VQ1001
CR022 through CR062
CR06B through CR150
CR160 through CR530

BS
BS
BS
BS
BS
BS

CECC
CECC
CECC
CECC
CECC
CECC

50
50
50
50
50
50

012-008
012-004
012-006
012-009
012-016
012-024

CECC
CECC
CECC
CECC
CECC
CECC

50
50
50
50
50
50

012-025
012-026
012-040
013-001
013-002
013-003

Each of the approved types is now available with additional screening options, including high temperature reverse bias burn-in, of either 48, 72 or 168 hours duration. Screening details are appended to the detail specification and conform to appendix VI of the European Standard CECC 50 000 ISSUE 3.
Product is released with a BS CECC certificate of conformity and will have been submitted to:
1. Group A sample inspection (lot by lot)-quality assessment tests, assuring product conforms
to electrical specification.
2. Group B sample inspection (lot by lot)-reliability tests, including package related tests and
168 hours electrical endurance. to identify potential early failures.
3. Group C sample inspection (periodic - 3 monthly)-Iong term reliability tests including 1000
hours of high temperature storage and electrical endurance.
Data from the inspection tests is available to the customer in the form of CTRs (certified test records).
Manufacturing of BS CECC product is carried out in the Siliconix UK facility located in Morriston, Swansea SA6
6NE, South Wales.
In addition to BS CECC approved product, the Siliconix UK facility can provide internationally recognized high-reliability screening options on standard products. These include Mil-750 and custom screening options.
JAN, JANTX or JANTXV processing for certain JEDEC-registered FETs can also be supplied.
For additional information and details of new/pending approvals, inquiries may be directed to the nearest sales
office.

1-5

•

~Siliconix

~ incorporated

Figure 3

LPD PROCESS OPTIONS
HI·REL PROCESS FLOWS
-1*'-2** Process
Internal Visual
(Pre Cap Inspection)
Method 2072 (JFET) /
2069 (MOSPOWER)

I
High Temp. Llle
(Stabilization Bake)
Method 1032

-LP3 Process*

I
High Temp. Llle
(Stabilization Bake)
Method 1032

I

I

Thermal Shock (Temp. Cycling)
Method 1051

Thermal Shock
(Temp. Cycling)

Condition C or F

I
Constant Acceleration
Method 2006
VI Axis at 20,000 G min.

*.

I
Method 1071

Condition G or H

Condition G or H

I

HTGB Burn-In
(MOSPOWER Only)
Method 1042 Condition B
48 Hour. @ 150°C

Interim Electrical
Parameters
Tested 100% to 25°C

I
Interim Electrical
Parameters

(MOSPOWER Only) Go-No Go
100% to 25 °c
Static Parameters
HTGB Burn-ln

(MOSPOWER Only)
Method 1042, Condition B
48 hours @ 150°C

Interim Electrical
Parameters

100% to 25°C

HTRB Burn-In
Method 1039, Condition A
(JFET), "'Current Regulators
Condition B/Method 1042
Condition A (MOSPOWER)
160 hours min. @ 150°C

HTRB Burn-In
Method 1039, Condition A
(JFET); Method 1042Condition A (MOSPOWER)

Final Electrical Test
Static Parameters
Read, Record & Deltas

(MOSPOWER Only)
Go - No Go - (JFETS)

Quality Conformance
Per MIL-S-I9500 JANTX
Sampling Plan for Group A
Inspectloni On selected
parameters QRAP 1030

1-6

Gr~~~~I;w~;.

0I'MIL-S-I9500

I

Static Parameters
Read and Record

Tested 100% to 25°C

II

Hermetic Seal: Gross Leak
Method 1071. Condition C

Static Parameters
Read and Record:
(MOSPOWER)
Go - No Go: (JFETS)

I

I
Quality Conformance

Method 2006
VI Axis at 20,000 G min.

Hermetic Seal: Fine Leak

Interim Electrical
Parameters
(MOSPOWER Only) Go-No Go
Tested 100% to 25°C
Static Parameters

I

I

I

I

Method 1071
Condition C

I
Qua~~~ucogf~lJ!I!!nCe
per fable IVb
01 MIL-S-19500

I

I

Constant Acceleration

Method 1071

Hermetic Seal: Gross Leak

External Visual LTPO = 5
Method 2071

Method 1051, Condition C or F

Hermetic Seal: Fine Leak

I

I

Internal Visual
(Pre-Cap Inspection)
Method 2072 (JFET)
2069 (MOSPOWER)

I

Method 1039, Condition B
(Current Regulators)

160 hours min. @ 150°C
Final Electrical
Parameters

100% to 25°C
Static Parameters
Read and Record

I

• -1: U. S. Build. U. S. Test

•• -2: ~

.: ~:'.

.

30
30
10
10
10
10
10
10

38
38
35
35
16
16
35
35

0.85
0.85
0.46
0.46
0.23
0.23
0.40
0.40

2
2
2
2
2
2
2
2

3.0
3.0
2.5
2.5
4.5
4.5

15
20
20
30
25
20

16
16
16
15
5
5

0.22
0.18
0.12
0.05
0.02
0.02

0.36
0.36
0.2
0.2
0.35
0.35

2.5
2.0
2.0
2.0
2.5
2.0
2.0
2.0
2.0
2.0
2.0
1.8

30
10
10
10
15
10
10
10
16
16
16
40

38
38
30
38
35
30
35
35
35
105
110
80

1.51
1.40
0.99
1.10
0.79
0.86
0.90
0.67
0.22
0.63
0.63
0.42

5
6.25
6.25
6.25
5
6.25
6.25
5
5
6.25
6.25
0.8

2.5
2.5

10
10

16
38

0.38
0.17

1.5
0.3

~
60
60
60
240
450
500

4
5
8
45
350
300

TO-205AD (TO-39)
VN0300B
2N6659
2N6660JANTX
2N6660
VN67AB
2N6661JANTX
2N6661
VN90AB
VN1206B
VN1706B
VN2406B
VN4012B

30
35
60
60
60
90
90
90
120
170
240
400

TO-206AC (TO-52)
VN10LE
VN10KE

3-42

60
60

1.2
1.8
3
3
3.5
4
4
5
6
6
6
12

#Y
5
5

.HSiliconix

incorporated

N·CHANNEL (Cont'd)
PART #

V(BR)DS
(V)

rDS(ON)
(n)

VGS(th)
(V)

tON

Ciss

(ns)

(pF)

ID
(rnA)

PD

TO·220ITO·220SD
VN46AFD
VN40AFD
VN66AD
VN66AFD
VN67AD
VN67AFD
VN88AD
VN88AFD
VN1206D
VN1706D
VN2406D

TO·237
VN0300M
VN10KM
VN10LM
VN2222LM
VN2222KM
VN0808M
VN1206M
VN1210M
VN1706M
VN1710M
VN2406M
VN2410M

TO·92
VN0300L
VN0603L
2N7000
VN0610L
88170
VN0610LL
VN2222LL
2N7008
VN2222L
VN0808L

40
40
60
60
60
60
80
80
120
170
240

3
5
3
3
3.5
3.5
4
4
6
6
6

2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.0
2.0
2.0

15
15
15
15
15
15
15
15
16
16
16

35
35
35
35
35
35
35
35
35
105
110

1.46
1.14
1.70
1.46
1.58
1.37
1.49
1.29
0.33
1.12
1.12

1.2
5
5
7.5
7.5
4
6
10
6
10
6
10

2.5
2.5
2.5
2.5
2.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0

30
10
10
10
10
10
16
16
16
16
16
16

38
38
16
16
38
35
35
35
105
110
110
110

0.67
0.31
0.32
0.26
0.25
0.33
0.26
0.20
0.25
0.19
0.25
0.19

1.2
3.5
5
5
5
5
7.5
7.5
7.5
4

2.5
3.0
3.0
2.5
3.0
2.5
2.5
2.5
2.5
2.0

30
15
10
10
10
10
10
20
10
10

38
16
16
38
16
16
16
16
38
35

0.64
0.30
0.20
0.27
0.50
0.28
0.23
0.15
0.23
0.30

15
15
20
15
20
15
20
15
20
20
20

~
30
60
60
60
60
80
120
120
170
170
240
240

..

~
30
60
60
60
60
60
60
60
60
80

0.8
0.8
0.4
0.8
0.83
0.8
0.8
0.4
0.8
0.8
3·43

.HSiliconix
incorporated

N-CHANNEL (Cont'd)
PART #

V(BR)OS
(V)

(.!1)

VGS(th)
(V)

tON
(ns)

Ciss
(pF)

(mA)

35
35
105
110
105
35
35
35
110
110
15
80
80
5
5

0.23
0.18
0.22
0.17
0.30
0.19
0.08
0.12
0.22
0.17
0.07
0.15
0.16
0.03
0.03

10

PD

~

TO-92 (Cont'd)
VN1206L
VN1210L
VN1706L
VN1710L
B8889
VN2010L
VN2020L
B8107
VN2406L
VN2410L
2N7007
VN3515L
VN4012L
VN45350L
VN50300L

rOS(ON)

120
120
170
170
200
200
200
200
240
240
240
350
400
450
500

6
10
6
10
6
10
20
28
6
10
45
15
12
350
300

2.0
2.0
2.0
2.0
2.8
1.8
2.0
3.0
2.0
2.0
2.5
1.8
1.8
4.5
4.5

16
16
16
16
80
20
20
16
16
30
40
40
25
20

0.8
0.8
0.8
0.8
1
0.8
0.8
0.5
0.8
0.8
0.4
0.8
5
0.8
0.8

P-CHANNEL

VQ2001J
VQ2001P
VQ2000J
VQ2000P
VQ2004P
VQ2004J
VQ2006P
VQ2006J

SOT-23
TP0610T
VP0610T

3-44

-3~
-3~

-60
-60
-60
-60
-90
-90

~ ~
'.

14-PIN CERAMIC (P) & PLASTIC (J)

'Y

2
2
10
10
5
5
5
5

-4.5
-4.5
-3.0
-3.0
-4.5
-4.5
-4.5
-4.5

10
10

-2.4
-3.5

••

<.

30
3D
35
35
55
55
55
55

130
130
15
15
75
75
75
75

-0.60
-0.60
-0.24
-0.24
-0.41
-0.41
-0.41
-0.41

2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00

25
25

15
15

-0.12
-0.12

0.36
0.36

~
-60
-60

.HSiliconix

incorporated

P-CHANNEL (Cont'd)
PART #

V(BR)DS
(V)

PO

VGS(th)
(V)

tON

Ciss

(il)

(ns)

(pF)

ID
(rnA)

2.5
5
5
10

-4.5
-4.5
-4.5
-2.5

30
55
55
45

130
75
75
65

-1.25
-O.SS
-0.79
-0.17

6.25
6.25
6.25
0.73

-2.4
-3.5
-2.5

25
25
25

15
15
30

-0.25
-0.25
-0.17

1.50
1.50
1.50

2.5
5
5

-4.5
-4.5
-4.5

30
55
55

130
75
75

-0.50
-0.31
-0.31

1.00
1.00
1.00

2.5
14
10
10
5
5
20
20
14
10

-4.5
-3.5
-3.5
-2.4
-4.5
-4.5
-2.S
-2.5

30
10
25
25
55
55
14
25
14
45

130
15
15
15
75
75
30
30
70
65

-0.32
-0.1S
-0.1S
-0.1S
-0.2S
-0.2S
-0.15
-0.12
-0.20
-0.1S

O.SO
0.S3
O.SO
O.SO
O.SO
O.SO
1.00
O.SO
0.S3
O.SO

-0.03

0.375

-0.05
-0.05

0.375
0.375

rDS(ON)

TO-205AD (TO-39)
VP0300B
VPOSOSB
VP100SB
VP2410B

-30
-SO
-100
-240

TO-206AC (TO-52)
TP0610E
VP0610E
VP2020E

TO-237
VP0300M
VPOSOSM
VP100SM

TO-92
VP0300L
B8250
VP0610L
TP0610L
VPOSOSL
VP100SL
B8892
VP2020L
B820S
VP2410L

-60
-60
-200

~
10
20

~
-30
-SO
-100

~
-30
-45
-60
-60
-SO
-100
-200
-200
-200
-240

-2.5

TO-18
MFES23

-25

1S0

-6

-30
-40

300
250

-5
-5

2.4

TO-72
3N164
3N163

36
36

2.4
2.4

3-45

..

.HSiliconix

incorporated

N· & P·CHANNEL QUADS
PART #

V(BR)OS
(V)

rOS(ON)
(.0)

VGS(th)
(V)

tON
(ns)

2%.

4-3

..

2N3956 SERIES

.:r-Siliconix

~ incorporated

N-Channel JFET Pairs

The 2N3956 Series are monolithic JFET pairs
for
high
performance differential
designed
amplification. This series features tight matching,
low gate leakage for accuracy, and wide dynamic
range as IG is guaranteed atVos = 20 V. Its TO-71
package is hermetically sealed and is available with
full military processing. (See Section 1.)

PART
NUMBER

IG IVGS,- VGS21
MAX
MAX
(pA)
(mV)

2N3956

-50

1

-50

15

2N3957

-50

1

-50

20

2N3958

-50

1

-50

25

For additional design information please see
performance curves NQP, which are located in
Section 7.

TO-71

SIMILAR PRODUCTS
•
•
•
•

V(BR)GSS gls
MIN
MIN
(V)
(mS)

BOTTOM VIEW

1
2
3
4
5
6

Low Noise, See U401 Series
Low Leakage, See U421 Series
High Gain, See 2N5911 Series
Chips. Order 2N395XCHP

SOURCE 1
DRAIN 1
GATE 1
SOURCE 2
DRAIN 2
GATE 2

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

VGO

-50

Gate-Source Voltage

VGS

-50

Forward Gate Current

IG

50

UNITS

V

Power Dissipation
Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-4

Per Side
Total
Per Side
Total

Po

250
500
2.86
4.3

TJ

-55 to 150

T stg

-65 to 200

TL

300

mA
mW
mW/DC

DC

2N3956 SERIES

fCrSiliconix
.LII incorporated
ELECTRICAL CHARACTERISTICS 1

LIMITS
2N3956

2N3957

2N3958

TYp2

MIN

I G = -1 .l1A, V DS = 0 V

-57

-50

VGS(OFF)

V DS = 20 V, I D = 1 nA

-2

-1

-4.5

-1

-4.5

-1

-4.5

Saturation Drain
Current

IDSS

V DS = 20 V, V GS = 0 V

3

0.5

5

0.5

5

0.5

5

mA

Gate Reverse
Current

IGSS

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)GSS

Gate-Source
Cutoff Voltage

PARAMETER

MAX

MIN

MAX

MIN

MAX UNIT

STATIC

Gate Operating
Current

Gate-Source Voltage

Gate-Source
Forward Voltage

-50

-50
V

IG

V GS = -30 V
V DS = 0 V

-10

-100

-100

-100

pA

-20

-500

-500

-500

nA

-5

-so

-SO

-SO

pA

I T A =125°C

-0.8

-250

-250

-250

nA

V DS = 20 V, ID = 50.l1A

-1.7

-4.2

-4.2

-4.2

V DS = 20 V, I D = 200 .l1A

-1.5

V DS = 20 V
ID = 200 .l1A

I T A =150°C

V GS

VGS(F)

I G = 1 mA, V DS = 0 V

-0.5

0.7

-4

-0.5

2

-4

-0.5

2

-4

V

2

DYNAMIC
V DS = 20 V, V GS = 0 V
f = 1 kHz

2.5

1

V DS = 20 V, V GS = 0 V
f = 200 MHz

2

1

gos

V DS = 20 V, V GS = 0 V
f = 1 kHz

7

35

35

35

Drain-Gate
Capacitance

Cdgo

V DG = 10 V, Is = 0 mA
f = 1 MHz

1

1.5

1.5

1.5

Common-Source
Input Capacitance

C lss

3

4

4

4

Common-Source
Reverse Transfer
Capacitance

Crss

V DS = 20 V, V GS = 0 V
f = 1 MHz

1

1.2

1.2

1.2

en

V DG =10V,I D =200.l1A
f = 1 kHz

Common-Source
Forward
Transconductance
Common-Source
Output Conductance

Equivalent Input
Noise Voltage
Noise Figure

gfs

NF

V DS = 20 V, V GS = 0 V
f = 100 Hz, RG = 10 M.n.

3

1

3

1

3
mS

1

1

.l1S

pF

%
"Hz

10
<0.1

0.5

0.5

0.5

dB

V DS = 20 V, I D = 200 .l1A

10

15

20

25

mV

~°C

MATCHING
Differential
Gate-Source Voltage

I VGS1-VGS21

Gate-Source Voltage
Differential Change
with Temperature

III VGS1-VGS21

V DS = 20 V IT = -55 to 25°C

25

50

75

100

liT

ID = 200 .l1AIT = 25 to 125°C

25

50

75

100

V DS = 20 V, V GS = 0 V

0.97

0.95

1

0.9

1

0.85

1

~
gls2

V DS = 20 V, I D = 200 .l1A
f = 1 kHz

0.97

0.95

1

0.9

1

0.85

1

1'G1-I G2 1

V DS = 20 V, I D = 200 .l1A
T A =125°C

0.2

Saturation
Drain Current Ratio
Transconductance
Ratio
Differential
Gate Current
NOTES:

I DSS1
I DSS2

10

10

10

nA

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300.l1s , duty cycle :s 3%.

4-5

--

.r'Siliconix

2N4091 SERIES - JANTX, JANTXV

~ im::orporated

N-Channel JFET

The 2N4091 Series is an all-purpose JFET analog
switch which offers low on-resistance, good
isolation and very fast switching. Its JAN, JANTX,
and JANTXV certification make this device a perfect
choice for military designs, as qualified devices can
be purchased without cumbersome source-L)ontrol
documentation.

PART
NUMBER

Vas (OFF)
MAX
(V)

rds(ON) IC(OFF)

MAX
(0)

MAX
(pA)

tON

MAX
(n8)

2N4091

-10

30

200

25

2N4092

-7

50

200

35

2N4093

-5

80

200

60

For further design information please consult the
typical performance curves NCB which are located
in Section 7.
BOTTOM VIEW

TO-18

SIMILAR PRODUCTS
•
•
•
•

TO-92, See PN4091 Series
SOT-23, See SST4091 Series
Duals, See 2N5564 Series
Chips, Order 2N409XCHP

1 SOURCE
2 DRAIN

3 GATE

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

Vac

-40

Gate-Source Voltage

Vas

-40

la

10

rnA

Po

1800

mW

10

mW/cC

V

Gate Current
Power Dissipation

(Case 25 cC)

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-6

TJ

-55 to 200

T stg

-65 to 200

TL

300

cC

2N4091 SERIES - JANTX, JANTXV

flCrSiliconix
.L:II incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N4091

SYMBOL

TEST CONDITIONS

TYP2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

I G = -1 .uA. V DS = 0 V

-55

-40

Gate-Source
Cutoff Voltage

VGS(OFF)

V DS = 20 V. ID = 1 nA

-5

Saturation Drain
Current 3

I Dss

V DS = 20 V. V GS = 0 V

30

Drain Reverse
Current

I DGO

PARAMETER

MAX

2N4092
MIN

MAX

2N4093
MIN

MAX UNIT

STATIC

Gate Operating
Current4

-40
V

IG

V DG = 20 V
Is = 0 V

T A =150'C

V DG =15V.I D = 10 mA

V DS = 20 V
Drain Cutoff Current

-40

ID(OFF)
V DS = 20 V
T A =150'C

-10

-2

-7

15

VDS(ON)

-5

-200

-200

-200

pA

-400

-400

-400

nA

200

pA

-5

V GS = -6 V

5
5

V GS = -12 V

5

V GS = -6 V

10

V GS = -8 V

10

V GS = -12 V

10

ID = 4 mA

200
200
400
400

rDS(ON)

VGs=OV.ID = 1 mA

Gate-Source
Forward Voltage 4

VGS(F)

I G = 1 mAo V DS = 0 V

nA

400
0.2

0.15

ID = 6.6 mA 0.15
Drain-Source
On-Resistance

mA

-10

V GS = -8 V

V GS = 0 V

-5

8

ID = 2.5 mA 0.15
Drain-Source
On-Voltage

-1

0.2

V

0.2
30

50

80

n

0.7

V

6

mS

25

.uS

DYNAMIC
Common-Source
Forward
Transconductance 4
Common-Source
Output Conductance4
Drain-Source
On-Resistance

gls

V DG = 20 V. I D = 1 mA
1=1 kHz

gos

V GS = 0 V. ID = 0 V
1=1 kHz

rds(ON)

30

50

80

Common-Source
Input Capacitance

C iss

V DS = 20 V. V GS = 0 V
1= 1 MHz

13

16

16

16

Common-Source
Reverse Transler
Capacitance

Crss

V DS = 0 V. V GS = -20 V
1=1 MHz

3.5

5

5

5

Equivalent Input
Noise Voltage4

en

n

pF

~
VHz'

V DG = 10 V. I D = 10 mA
1=1 kHz

3

VDD = 3 V. VGS(ON) = 0 V

2

15

15

20

2

10

20

40

20

40

60

80

SWITCHING
Turn-on Time

td(ON)
tr

Turn-off Time
NOTES:

1.
2.
3.
4.

tOFF

PIN
2N4091
2N4092
2N4093

RL
ID(ON) VGS(OFF)
6.6 mA -12 V
425 n
-8 V
4mA
700 n
-6 V 1120n
2.5 mA

ns

T A = 25 'c unless otherwise noted.
For design aid only. not subject to production testing.
Pulse test; PW =300.uS. duty cycle5 3%.
This parameter not registered with JEDEC.

4-7

-

.r-SilicDnix

2N4117 SERIES

~ inclJrplJrated

N-Channel JFET

The 2N4117 and 2N4117 A Series are n-channel
JFETs designed to provide ultra-high input
impedance. The 2N4117 features I GSS of 10 pA
maximum while the 2N4117 A Series is specified
with a 1 pA limit and typically operates at 0.2 pA.
These devices, therefore, make perfect choices for
use as sensitive front-end amplifiers in applications
such as microphones, smoke detectors, and
precision test equipment.
Additionally, its
hermetically sealed TO-72 package allows full
military processing per MIL-S-19500.
(See
Section 1.)

PART
NUMBER

VGS(OFF) V(BR)GSS
MAX
MIN
(V)
(V)

MIN
( fLS)

loss
MAX
(mA)

9fs

2N4117

-1.8

-40

70

0.09

2N4118

-3

-40

80

0.24

2N4119

-6

-40

100

0.60

2N4117A

-1.8

-40

70

0.09

2N4118A

-3

-40

80

0.24

2N4119A

-6

-40

100

0.60

BOTTOM VIEW

TO-72

For additional design information please consult
performance curves NT which are located in
Section 7.

SIMILAR PRODUCTS
•
•
•
•

1 SOURCE
2 DRAIN
3 GATE
4 CASE

TO-92, See PN4117 Series
SOT-23, See SST4117 Series
Dual, See U421 Series
Chips, Order 2N411 XCHP

ABSOLUTE MAXIMUM RATINGS (T A = 25 DC unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

VGD

-40

Gate-Source Voltage

VGS

-40

Gate Current

IG

50

mA

Power Dissipation

PD

300

mW

2

mW/DC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds 1

4-8

TJ

-55 to 175

T stg

-65 to 175

h

255

DC

2N4117 SERIES

..... Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N4117

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

-70

-40

MAX

2N4118
MIN

MAX

2N4119
MIN

MAX UNIT

STATIC
Gate-Source
Breakdown Voltage

V(BR)GSS

IG=-l~A.VDS=OV

Gate-Source
Cutoff Voltage

VGS(OFF)

V DS = 10 V. I D = 1 nA

-0.6

-1.8

-1

-3

-2

-6

Saturation Drain
Current 3

IDSS

VDS = 10 V. V GS = 0 V

0.03

0.09

0.08

0.24

0.2

0.6

mA

Gate Reverse Current

IGSS

V GS = -20 V
VDS = 0 V

Gate Operating
Current

-40

-40
V

IG

ITA =150°C

V DG = 15 V. ID =

30~A

-0.2

-10

-10

-10

pA

-0.4

-25

-25

-25

nA

-0.2
pA

Drain Cutoff Current

ID(OFF)

V DS = 10 V. VGS = -6 V

0.2

Gate-Source
Forward Voltage

VGS(F)

IG = 1 mA. V DS = 0 V

0.7

V

DYNAMIC
Common-Source
Forward
Transconductance

gfs

Common-Source
Output Conductance

gas

Common-Source
Input Capacitance

C lss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

en

70

VDS = 10 V. VGS = 0 V
f = 1 kHz

V DS = 10 V. VGS = 0 V
f = 1 MHz
V DS = 10 V. VGS = 0 V
f = 1 kHz

210

60

250

100

330
J,LS

3

5

10

1.2

3

3

3

0.3

1.5

1.5

1.5

pF

15

'2:
VHZ

-

NOTES: 1. T A = 25 0 C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW = 300J,LS. duty cycle S3%.

\

4-9

2N4117 SERIES

~SiliCDnix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N4117A

2N4118A

2N4119A

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

IG=-1.11A.Vos=OV

-70

-40

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 10 V. 10 = 1 nA

-0.6

-1.8

-1

-3

-2

-6

Saturation Drain
Current 3

loss

Vos = 10 V. VGS = 0 V

0.015

0.09

0.08

0.24

0.2

0.6

rnA

Gate Reverse Current

IGSS

VGS = -20 V
Vos = 0 V

PARAMETER

MAX

MIN

MAX

MIN

MAX UNIT

STATIC

Gate Operating
Current

-40

-40
V

IG

ITA =150·C

VpG = 15 V. 10 = 30jlA

-0.2

-1

-1

-1

pA

-0.4

-2.5

-2.5

-2.5

nA

-0.2
pA

Drain Cutoff Current

10(OFF)

Vos = 10 V. VGS = -8 V

0.2

Gate-Source
Forward Voltage

VGS(F)

IG = 1 inA. VOS = 0 V

0.7

gfs

VOS = 10 V. VGS = 0 V
f = 1 kHz

V

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Capacitance
Equivalent Input
Noise Voltage

gos
Clss
Crss

en

Vos = 10 V. VGS = 0 V
f = 1 MHz
Vos = 10 V. VGS = 0 V
f = 1 kHz

NOTES: 1. T A = 25 ·C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW =300,ll.S. duty cycle S3%.

4-10

70

210

80

250

100

330
.I1S

3

5

10

1.2

3

3

3

0.3

1.5

1.5

1.5

pF

15

~
VHz

~SilicDnix

~ incorporated

2N4220 SERIES
N-Channel JFETs

The 2N4220 Series of mUlti-purpose JFETs is
designed for a wide range of applications.
It
features
extremely low gate leakage and
capacitance, and when coupled with its high gain,
the 2N4220 Series will make a perfect broad band
amplifier.
The 2N4220A Series features a
guaranteed noise figure of 2.5 dB. For military
designs, this series is available with full high-rei
processing. (See Section 1.)

PART
NUMBER

For further design information please consult the
typical performance curves NRL which are located
in Section 7.

VGS(OFF) V(BR)GSS
MAX
MIN
(V)
(V)

9fs
MIN
(mS)

loss
MAX
(mA)
3

2N4220

-4

-30

1

2N4221

-6

-30

2

6

2N4222

-8

-30

2.5

15

2N4220A

-4

-30

1

3

2N4221A

-6

-30

2

6

2N4222A

-8

-30

2.5

15

TO-72

BOTTOM VIEW

SIMILAR PRODUCTS
•
•
•

1
2
3
4

TO-92, See J201 Series
SOT-23, See SST201 Series
Chips. Order 2N422XCHP

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

DRAIN
SOURCE
GATE
CASE

= 25°C unless otherwise

noted)

SYMBOL

LIMIT

Gate-Drain Voltage

VGO

-30

Gate-Source Voltage

VGS

-30

Gate Current

IG

10

Drain Current

10

15

Power Dissipation

PD

300

mW

2

mW/oC

UNITS

V

mA

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 175

Tstg

-65 to 200

TL

300

°C

4-11

.rSiliconix

2N4220 SERIES

~ incorpora.ted

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N4220

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source,
Breakdown Voltage

V(BR)GSS

I G =-10JlA, Vos =OV

-57

-30

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 15 V, 10 = 0.1 nA

Saturation Drain
Current 3

loss

Vos = 15 V. VGS = 0 V

Gate Reverse Current

IGSS

VGS = -15 V
VOS = 0 V

PARAMETER

MAX

2N4221
MIN

MAX

2N4222
MIN

MAX UNIT

STATIC

Gate Operating
Current 4

-30

-30
V

TA=150·C

-4
0.5

3

-8

-6
2

6

5

15

rnA

-2

-100

-lOa

-lOa

pA

-4

-100

-100

-lOa

nA

IG

V oG =15V,l o = 0.1 rnA

-2

Drain Cutoff Current 4

10(OFF)

Vos =,10 V, VGS = -10 V

2

Gate-Source Voltage

VGS

pA

10 = 50 J.lA
Vos = 15 V

-0.8

-0.5

-2.5

10 = 200 JlA -1.5

-1

-5

10 = 500J.lA -3.5
Gate-Source
Forward Voltage 4

VGS(F)

IG=lmA,Vos=OV

-2

-6

2.5

6

V

0.7

DYNAMIC
Common-Source
Forward
Transconductance

gls

Common-Source
Output Conductance
Common-Source
Forward
Transmittance

90s

Common-Source
Input Capacitance

C lss

Common-Source
~~6';[~~,ance
Transfer
Equivalent Input
Noise Voltage4

gls

Vos = 15 V, VGS =
f = 1 MHz

aV

Vos = 10 V, VGS =
f = 1 kHz

aV

)

NOTES:

4-12

1.
2.
3.
4.

4

2

10

T A = 25·C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW =300Jls. duty cycle S3%.
This parameter not registered with JEDEC.

5
20

mS

40
J,lS

VOS = 15 V, VGS = 0 V
f = 100 MHz

c;.ss

en

1

Vos = 15 V, VGS = 0 V
f = 1 kHz

750

750

750

5

6

6

6

1.5

2

2

2

pF

6

%
-./Hz

2N4220 SERIES

fCrSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N4220A

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -10,IJ.A, Vos = 0 V

-57

-30

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos=15V,lo=0.1nA

Saturation Drain
Current 3

loss

Vos = 15 V, V GS = 0 V

Gate Reverse Current

IGSS

V GS = -15 V
Vos = 0 V

PARAMETER

MAX

2N4221A
MIN

MAX

2N4222A
MIN

MAX UNIT

STATIC

Gate Operating
Current 4

-30

-30
V

T A =150°C

-4
0.5

3

-6

-6
2

6

5

15

mA

-2

-100

-100

-100

pA

-4

-100

-100

-100

nA

IG

VOG = 15 V, 10 = 0.1 mA

-2

Drain Cutoff Current 4

10(OFF)

Vos = 10 V, VGS = -10 V

2

Gate-Source Voltage

VGS

pA

10 = 50,IJ.A
Vos = 15 V

-0.6

-0.5

-2.5

10 = 200,IJ.A -1.5

-1

-5

10 = 500,IJ.A -3.5
Gate-Source
Forward Voltage 4

VGS(F)

IG = 1 mA, Vos = 0 V

-2

-6

V

2.5

6

mS

0.7

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Common-Source
Forward
Transmittance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Caoacltance
Equivalent Input
Noise Voltage4
Noise Figure

NOTES:

1.
2.
3.
4.

gfs
gos
gfs

4

2

10

VOS = 15 V, VGS = 0 V
f = 1 MHz

en

Vos = 10 V, VGS = 0 V
f = 1 kHz

NF

Vos = 15 V, VGS - 0 V
f = 100 Hz, RG= 1 M.o.
BW = 6 Hz

5
20

40
.uS

Vos = 15 V, VGS = 0 V
f= 100 MHz

C 1SS
Crss

1

Vos = 15 V, VGS = 0 V
f = 1 kHz

750

750

750

5

6

6

6

1.5

2

2

2

pF

~
"Hz

6
2.5

2.5

2.5

dB

T A = 25 a C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW =300,IJ.s, duty cycle :>3%.
This parameter not registered with JEDEC.

4-13

l1li

~Siliconix

2N4338 SERIES

~ incorporatec

N·Channel JFETs

The 2N4338 Series of n-channel JFETs is designed
for sensitive amplifier stages at low to mid
frequencies. It features low cut-off voltages to
accommodate low-level power supplies and low
leakage for improved system accuracy.
The
2N4338 and 2N4339 are ideal for low current. low
battery operation. With their 1 dB max. noise figure
at 1 kHz. system sensitivity will be excellent.
Finally. the 2N4338 Series' TO-18 package is
hermetically sealed and suitable for military
processing. (See Section 1.)

PART
NUMBER

loss
MAX
(mA)
0.6

gfs

-1

-50

0.6

2N4339

-1.8

-50

0.8

1.5

2N4340

-3

-50

1.3

3.6

2N4341

-6

-50

2

9

BOTTOM VIEW

TO·18

SIMILAR PRODUCTS

1 SOURCE
2 DRAIN
3 GATE & CASE

e TO-92. See J201 Series
e 1. SOT-23. See SST201 Series
eo' Chips. Order 2N433XCHP

PARAMETERS/TEST CONDITIONS

MIN
(mS)

2N4338

For further design information please consult the
typical performance curves NPA which are located
in Section 7.

ABSOLUTE MAXIMUM RATINGS (T A

Vas (OFF) V(BR)aSS
MIN
MAX
(V)
(V)

= 25°C unless otherwise noted)
SYMBOL

LIMIT

Gate-Drain Voltage

Vao

-50

Gate-Source Voltage

Vas

-50

Gate Current

la

50

mA

Power Dissipation

Po

300

mW

2

mW/oC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-14

TJ

-55 to 175

T stg

-65 to 200

TL

300

°C

2N4338 SERIES

~Siliconix
.z.
incorporated
ELECTRICAL CHARACTERISTICS 1

LIMITS
2N4338

PARAMETER

TYp2

MIN

MAX

2N4339

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -1,l.LA. V DS = 0 V

Gate-Source
Cutoff Voltage

VGS(OFF)

V DS = 15 V. ID = 0.1,l.LA

-0.3

-1

-0.6

-1.8

Saturation Drain
Current 3

IDSS

VDS = 15 V. VGS = 0 V

0.2

0.6

0.5

1.5

rnA

Gate Reverse Current

IGSS

STATIC

Gate Operating
Current4

-57

-50

-50
V

VGS = -30 V
V DS = 0 V

I TA =150·C

-2

-100

-100

pA

-4

-100

-100

nA

50

50

IG

V DG =15V.I D =0.1mA

-2

Drain Cutoff Current

ID(OFF)

VDS = 15 V. VGS = -5 V

2

Gate-Source
Forward Voltage 4

VGS(!)

IG = 1 rnA. V DS = 0 V

0.7

pA

V

DYNAMIC
Common-Source
Forward
Transconductance

g!s

Common-Source
Output Conductance

gos

Drain-Source
On-Resistance

rDS(ON)

Common-Source
Input Capacitance

C1SS

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage 55 V), high gain (typically

PART
NUMBER

> 9 mS), and less than 5 mV ')ffset between the
two die.
Additionally, its TO-71 package is
hermetically sealed and can be processed per
MIL-S-19500. (See Section 1.)

IG IVGS1- Vas21
MAX
MAX
(mV)
(pA)

2N5564

-40

7.5

-100

2N5565

-40

7.5

-100

10

2N5566

-40

7.5

-100

20

1
2
3
4
5
6

SIMILAR PRODUCTS
Low Noise, See U401 Series
Low Leakage, See U421 Series
Chips, Order 2N556XCHP

5

BOTTOM VIEW

TO-71

For additional design information please see
performance curves NCB, which are located in
Section 7.

•
•
•

V(BR)GSS 9fs
MIN
MIN
(V)
(mS)

SOURCE 1
DRAIN 1
GATE 1
SOURCE 2
DRAIN 2
GATE 2

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

VGD

-40

Gate-Source Voltage

VGS

-40

Gate-Gate Voltage

VGG

± 80

IG

Forward Gate Current
Power Dissipation
Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-44

Per Side
Total
Per Side
Total

PD

50
325
650
2.2
3.3

TJ

-55 to 150

T stg

-65 to 200

h

300

UNITS

V

mA
mW
mW/oC

°C

2N5564 SERIES

~Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N5564

2N5565

2N5566

Typ2

MIN

I G = -1.IJ.A, V DS = 0 V

-55

-40

VGS(OFF)

V Ds =15V,I D =1nA

-2

-0.5

-3

-0.5

-3

-0.5

-3

Saturation Drain
Current

I DSS

V DS = 15 V, V GS = 0 V

20

5

30

5

30

5

30

mA

Gate Reverse
Current 3

IGSS

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(SR)GSS

Gate-Source
Cutoff Voltage

PARAMETER

MAX

MIN

MAX

MIN

MAX UNIT

STATIC

Gate Operating
Current
Drain-Source
On-Resistance
Gate-Source Voltage
Gate-Source
Forward Voltage

-40

-40
V

IG
rDS(ON)

V GS = -20 V
V DS = 0 V
V DG =15V
ID = 2 mA

I T A =150°C

I T A =125°C

-5

-100

-100

-100

pA

-10

-200

-200

-200

nA

-3

pA

-1

nA

V GS = 0 V, ID = 1 mA

50

V GS

V DS = 15 V, ID = 2 mA

-1.2

VGS(F)

I G = 2 mA, V DS = 0 V

0.7

100

100

100

1

1

1

n

V

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Common-Source
Forward
Transconductance
Common-Source
Input Capacitance
Common-Source

Reverse Transfer
Capacitance

gts
gas
gts

C iss

Crss

V DG = 15 V, ID = 2 mA
f = 1 kHz
V DG = 15 V, ID = 2 mA
f = 100 MHz
V DG = 15 V, I D = 2 mA
f = 1 MHz

9

7.5

7.5

45

35
8.5

12.5

7

12.5

7.5

45
7

12.5

mS

45

jJ.S

7

mS

10

12

12

12

2.5

3

3

3

pF

Equivalent Input
Noise Voltage

en

V DG = 15 V, ID = 2 mA
f = 10 Hz

12

50

50

50

~
'-1Hz

Noise Figure

NF

V DG =15V,I D =2mA
f = 10 Hz , RG = 1 Mn

0.1

1

1

1

dB

5

10

20

mV

10

25

50

10

25

50

~°C

MATCHING
Differential
! VGS1-VGS2!
Gate-Source Voltage

V DS = 15 V , I D = 2 mA

vi

Gate-Source Voltage
T = -55 to 25°C
bo!VGS1-VGS2! V DS = 15
Differential Change
ID
=
2
mA
IT
= 25 to 125°C
with Temperature
boT
Saturation
Drain Current Ratio

I DSS1
I DSS2

V DS = 15 V, V GS = 0 V

0.98

0.95

1

0.95

1

0.95

1

Transconductance
Ratio

~
gts2

V DS = 15 V, ID = 2 mA
f = 1 kHz

0.98

0.95

1

0.90

1

0.90

1

CMRR

V DD = 10 to 20 V, ID = 2 mA

76

Common Mode
Rejection Ratio
NOTES:

dB

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3, Pulse test; PW = 300.IJ.s , duty cycle :S 3%.

4-45

..

fCrSiliconix

2N5638 SERIES

~ incorporated

N-Channel JFET

The 2N5638 Series is a mUlti-purpose n-channel
JFET designed to economically enhance circuit
performance. These devices are especially well
suited for analog switching applications and feature
very fast switching speeds. but function efficiently
as high-gain amplifiers. particularly at high-frequency.
Our low-cost TO-92 packaging offers
affordable performance with flexibility for designers.
as these devices can be ordered with a variety of
lead forms or tape and reel for automated
insertion. (See Section 8.)

PART
NUMBER

rds(ON) ID(OFF)
MAX
MAX
(n)
(nA)

tON
MAX
(ns)

2N5638

-30

30

1

9

2N5639

-30

60

1

14

2N5640

-30

100

1

18

For additional design information please consult the
typical performance curves NCB which are located
in Section 7.

TO-92

BOTTOM VIEW

1 DRAIN
2 SOURCE
3 GATE

SIMILAR PRODUCTS
•
•
•
•

V(BR)DSS
MAX
(V)

TO-18. See 2N4391 Series
SOT-23. See SST4391 Series
Duals. See 2N5564 Series
Chips. Order 2N563XCHP

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise

noted)

SYMBOL

LIMIT

Gate-Drain Voltage

VGD

-30

Gate-Source Voltage

VGS

-30

Gate Current

IG

10

mA

Power Dissipation

PD

625

mW

5.68

mW/oC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-46

TJ

-65 to 135

T stg

-65 to 150

TL

300

°C

g

2N5638 SERIES

Siliconix

incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N5638

2N5639

2N5640

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)GSS

IG = -10J.l.A, Vos = 0 V

-55

-30

-30

-30

V

Saturation Drain
Current 3

loss

Vos = 20 V, V GS = 0 V

50

25

5

rnA

Gate Reverse Current

IGSS

PARAMETER

MAX

MIN

MAX

MIN

MAX UNIT

STATIC
Gate-Source
Breakdown Voltage

Gate Operating
Current 4

IG

V GS = -15 V
Vos = 0 V

V oG =15V,1 0 = 10 rnA

Vos = 15 V
Drain Cutoff Current

TA =100·C

-0.005

-1

-1

-1

nA

-0.01

-1

-1

-1

J.I.A

-5

V GS = -6 V

0.005

V GS = -8 V

0.005

V GS = -12 V 0.005

10(OFF)
Vos = 15 V
TA =100·C

V GS = -6 V

0.01

V GS = -8 V

0.01

V GS = -12 V 0.01
Drain-Source
On-Voltage

VOS(ON)

Drain-Source
On-Resistance
Gate-Source
Forward Voltage

4

V GS = 0 V

10 = 3 rnA
10 = 6 rnA

0.25

10 = 12 rnA

0.35

rOS(ON)

VGs=OV,l o = 1 rnA

VGS(F)

I G = 1 rnA, Vos = 0 V

pA
1
1

nA

1
1
1

J.I.A

1
0.5

0.30

0.5

V

0.5
30

60

100

.n

0.7

V

6

mS

25

JJ.S

DYNAMIC
Common-Source
Forward
Transconductance

gls
4

Common-Source
Output Conductance 4
Drain-Source
On-Resistance

f = 1 kHz

gos

V GS = 0 V, 10 = 0 rnA
f = 1 kHz

rds(ON)

Common-Source
Input Capacitance

C lss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage 4

\

V oG =20V, 10=1 rnA

en

Vos = 0 V, V GS = -12 V
1=1 MHz
VOG = 10 V, 10 = 10 rnA
1= 1 kHz

30

60

100

7

10

10

10

3

4

4

4

.n

pF

%
VHZ

3.0

SWITCHING
Turn-on Time
Turn-olf Time

td(ON)
tr
td(OFF)
tf

NOTES: 1.
2.
3.
4.

VOO - 10 V, VGS(ON) - 0 V
PIN
2N5638
2N5639
2N5640

RL
10(ON) VGS(OFF)
-10 V
800.n
12 rnA
6mA
-10 V 1600.n
-10 V 3200.n
3 rnA

2

4

6

8

2

5

8

10

6

5

10

15

13

10

20

30

ns

T A = 25·C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW =300JJ.S, duty cycle S3%.
This parameter not registered with JEDEC.

4-47

..

.:r-SilicDnix

2N5911 SERIES

~ incorporated

N-Channel JFET Pairs

The 2N5911 Series are JFET matched pairs
mounted in a single TO-78 package. This two chip
design reduces parasitic performance at high
frequency while ensuring extremely tight matching.
The 2N5911 features high speed amplification (slew
rate). high gain (typically> 6 mS). and low gate
leakage (typically < 1 pA).
This performance
makes these devices perfect for use as wideband
differential amplifiers in demanding test and
measurement applications.
Finally. its TO-78
hermetically sealed package is available with
military screening per MIL-S-19500.
(See
Section 1.)

PART
NUMBER

V(BR)GSS 91s
MIN
MIN
(V)
(mS)

IG IVGS1- VGS21
MAX
MAX
(pA)
(mV)

2N5911

-25

5

-100

10

2N5912

-25

5

-100

15

TO-78

BOTTOM VIEW

For additional design information please see
performance curves NZF. which are located in
Section 7.
1
2
3
4
5
6
7

SIMILAR PRODUCTS
•
•
•
•
•

SO-8. See SST5912
Monolithic. See M5911 Series
Low Noise. See U401 Series
Low Leakage. See U421 Series
Chips. Order 2N591XCHP

SOURCE 1
DRAIN 1
GATE 1
CASE
SOURCE 2
DRAIN 2
GATE 2

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted).
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

VGD

-25

Gate-Source Voltage

VGS

-25

Gate-Gate Voltage

VGG

± 80

IG

50

Forward Gate Current
Power Dissipation
Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1 /16~' from case for 10 seconds)
4-48

Per Side
Total
Per Side
Total

PD

367
500
3
4

TJ

-55 to 150

T stg

-65 to 200

TL

300

UNITS

V

mA
mW
mW/oC

DC

2N5911 SERIES

~Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N5911

2N5912

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

I G =-lj..lA,V os =OV

-35

-25

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 10 V, 10 = 1 nA

-3.5

-1

-5

-1

-5

15

7

40

7

40

mA
pA

PARAMETER

MAX

MIN

MAX

UNIT

STATIC
-25
V

Saturation Drain
Current 3

loss

Gate Reverse
Current

IGSS

Gate Operating
Current
Gate-Source Voltage

IG

VOS = 10 V, VGS = 0 V
VGS = -15 V
Vos = 0 V
V oG =10V
10 = 5 mA

IT
IT

A

A

=150°C

=125°C

-1

-100

-100

-2

-250

-250

nA

-1

-100

-100

pA

-0.3

-100

-100

nA

VGS

VOG = 10 V, 10 = 5 mA

-1.5

VGS(F)

I G = 1 mA, Vos = 0 V

0.7

V OG = 10 V, I 0 = 5 mA
f = 1 kHz

6

-0.3

-4

-0.3

-4
V

Gate-Source
Forward Voltage

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Common-Source

Forward
Transconductance
Common-Source
Output Conductance

gls
gas
gls
gas

5

70
V OG = 10 V, I 0 = 5 mA
f = 100 MHz

5.8

10

5

100
5

10

5

10

mS

100

J,lS

10

mS
J,lS

90

150

150

3

5

5

1

1.2

1.2

VOG = 10 V, 10 = 5 mA
f = 10 kHz

4

20

20

%
VHz

NF

VOG = 10 V, 10 = 5 mA
f = 10kHz, R G = 100 k.(1

0.1

1

1

dB

Differential
Gate-Source Voltage

I VGS1-VGs21

V OG =10V, 10 =5mA

4

10

15

mV

Gate-Source Voltage
Differential Change
with Temperature

'" IVGs1-VGs21

15

20

40

15

20

40

~°C

Common-Source
Input Capacitance

C 1ss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

en

Noise Figure

VOG = 10 V, 10 = 5 mA
f = 1 MHz

pF

MATCHING

Saturation
Drain Current Ratio
Transconductance
Ratio
Differential
Gate Current
Common Mode
Rejection Ratio
NOTES:

"'T

V oG =10vl
10 =5mA

T = -55 to 25°C

I T = 25 to 125°C

loss1
IOSS2

Vos = 10 V, VGS = 0 V

0.98

0.95

1

0.95

1

gls1
gls2

VOG = 10 V, 10 = 5 mA
f = 1 kHz

0.98

0.95

1

0.95

1

II G1- I G21

VOG=10V,10=5mA
T A = 125°C

0.005

CMRR

V 00 = 5 to 10 V, I 0 = 5 mA

85

20

20

nA
dB

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300)J.s , duty cycle $ 3%.

4-49

.r'Siliconix

2N6905 SERIES

~ incorporated

N-Channel JFET Pairs

The 2N6905 Series of high-performance monolithic
dual JFETs features extremely low noise, tight
offset voltage and drift over temperature
specifications. It is targeted for use in a wide range
of precision instrumentation applications.
The
2N6905 Series has a wide selection of both offset
and drift ranges with the prime device, the 2N6905,
featuring 5 mV offset and 10 /J.V/oC drift. The three
devices allow designers to make important
cost/benefit decisions. This series is available in a
TO-71 hermetically sealed package and is available
with military screening. (See Section 1.)

PART
NUMBER

V(BR)GSS 9fs
MIN
MIN
(V)
(mS)

IG !VGS1-VGS2!
MAX
MAX
(mV)
(pA)

2N6905

-35

2

-5

5

2N6906

-35

2

-5

10

2N6907

-35

2

-5

25

BOTTOM VIEW

TO-71

For additional design information please see
performance curves NNR, which are located in
Section 7.
1
2
3
4
5
6

SIMILAR PRODUCTS
•
•
•

High-Gain, See 2N5911 Series
SO-8, See SST404 Series
Chips, Order 2N690XCHP

ABSOLUTE MAXIMUM RATINGS {T A
PARAMETERS/TEST CONDITIONS

= 25 DC unless

SOURCE 1
DRAIN 1
GATE 1
SOURCE 2
DRAIN 2
GATE 2

otherwise noted}

SYMBOL

LIMIT

Gate-Drain Voltage

VGD

-35

Gate-Source Voltage

VGS

-35

Forward Gate Current

IG

10

UNITS

V

Power Dissipation
Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-50

Per Side
Total
Per Side
Total

Po

300
500
2.6
5

TJ

-55 to 150

Tst9

-65 to 200

h

300

mA
mW
mW/oC

°C

2N6905 SERIES

~Siliconix
incorporated

~.

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N6905

2N6906

2N6907

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -lp.A, VOS = 0 V

-55

-35

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 15 V, 10 = 1 nA

-1.5

-0.2

-3

-0.2

-3

-0.2

-3

Saturation Drain 3
Current

loss

Vos = 10 V, V GS = 0 V

3.5

0.5

10

0.5

10

0.5

10

rnA

Gate Reverse
Current

IGSS

PARAMETER

MAX

MIN

MAX

MIN

MAX UNIT

STATIC

Gate Operating
Current
Drain-Source
On-Resistance 4
Gate-Source Voltage
Gate-Source
Forward Voltage 4

-35

-35
V

IG
rOS(ON)

V GS = -15 V
Vos = 0 V
VOG = 15 V
10= 200 j.LA

-2

IT
IT

A

A

=125°C

=125°C

-15

-15

-15

pA

-2

-5

-5

-5

pA

-0.8

-5

-5

-5

nA

-1

V GS = 0 V, 10 = 0.1 rnA

250

V GS

VOG = 15 V, 10 = 200 j.LA

-1

VGS(F)

I G =lmA,V os =OV

0.7

nA

.0.
-2.3

-2.3

-2.3
V

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Capacitance
Equivalent Input
Noise Voltage

gls
gos

Vos = 10 V, V GS = 0 V
f = 1 kHz

C 1SS
Crss

VOG = 15 V, 10 = 200 j.LA
f = 1 MHz

en

V DS = 10 V, V GS = 0 V
f = 10 Hz

1VGS1-VGS21

V OG = 10 V, I 0 = 200 j.LA

4

2

7

2

7

2

7

mS

.us

4

20

20

20

4

8

8

8

1.5

3

3

3

10

15

15

15

%
'-1Hz

5

10

25

mV

10

25

25

10

25

50

~°C

pF

MATCHING
Differential
Gate-Source Voltage

vi

Gate-Source Voltage t>.IVGS1-VGS21 VOG = 10
T = -55 to 25°C
Differential Change
10 = 200 j.LA1 T = 25 to 125°C
with Temperature
t>.T
Saturation
Drain Current Ratio 4

10SSl
IOSS2

Transconductance
Rati04

glsl
gls2

Differential
Output Conductance4

1gosl - gos21

Vos = 10 V, V GS = 0 V

0.97
0.97

VOG = 10 V, 10= 0.2 rnA
f = 1 kHz

0.1

.uS
pA

Differential
Gate Current 4

11 Gl- I G21

VOG = 15 V, 10= 0.2 rnA
T A = 25°C

1

Common Mode
Rejection Ratio

CMRR

V OG = 10 to 20 V, 10 = 200 j.LA

102

NOTES:

95

95

95

dB

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300p.s, duty cycle S3%.
4. This parameter not registered with JEDEC.

4-51

l1li

g

2N6908 SERIES

Sificonix

incorporated

N-Channel JFET Circuits

The 2N690B Series is much more than a JFET. The
addition of back-to-back diodes effectively clamps
input "over-voltage" while a high-performance
JFET provides an effective amplification stage.
With the addition of a source resistor, a complete
common-source amplifier is created which provides
This
both low leakage ,and very low noise.
performance is especially effective as a small
signal pre-amplifier as well as impedance matching
between low and high impedance sources. Finally,
its TO-72 package is hermetically sealed and is
per
available
with
full
military
screening
MIL-S-19500. (See Section 1.)

PART
NUMBER

VGS(OFF) V(BR)GSS
MIN
MAX
(V)
(V)

9fs

MIN
(J.l.S)

loss
MAX
(mA)

2N690B

-1.B

-30

100

2

2N6909

-2.3

-30

400

3.5

2N6910

-3.5

-30

1200

5

TO-72

For additional design information please see
performance curves NBB. which are located in
Section 7.

BOTTOM VIEW

1
2
3
4

SOURCE
DRAIN
GATE
DIODES

SIMILAR PRODUCTS
•
•

SOT-143. See SST690B Series
Chips. Order 2N69XXCHP

S

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise

noted)

SYMBOL

LIMIT

Gate-Drain Voltage

VGD

-30

Gate-Source Voltage

VGS

-30

Forward Gate Current

IG

10

mA

Power Dissipation

Po

300

mW

2.4

mWloC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-52

TJ

-55 to 150

T stg

-55 to 200

h

300

°C

2N6908 SERIES

.r'Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N6908

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

-50

-30

MAX

2N6909
MIN

MAX

2N6910
MIN

MAX UNIT

STATIC

av

Gate-Source
Breakdown Voltage

V(BR)aSS

la = -lJJ.A, Ves =
V a4 = a V

Gate-Source
Cutoff Voltage

VaS(OFF)

Ves = 10 V, Ie = 1 nA
V a4 = a V

Saturation Drain
Current 3

less

Gate Reverse Current

lass

Ves = 10 V, Vas = a V
V a4 = a V
V as =-15V
Ves = a V
ITA =125°C
Va4 = a V

-30

-30

V
-0.3

-l.B

-0.6

-2.3

-0.9

-3.5

0.05

2

0.2

3.5

0.6

5

rnA

-25

pA

-2

-25

-25

-1

nA

Gate Operating
Current

la

Vea = 15 V, Ie = 50M

-2

Forward Gate Diode
Current 4

la4

V a4 = ± 100 mV

±1

±10

± 10

±10

± 0.7

± 1.2

± 1.2

± 1.2

V

4

mS
jJ.S

Gate-Source
Forward Voltage

pA

VaS(F)

la=±0.5 rnA, Ves =
V a4 = a V

gls

Ves = 15 V, Vas =

aV

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Caoacltance
Equivalent Input
Noise Voltage
Noise Figure
NOTES:

1.
2.
3.
4.

gas

V a4 =

a V,

C 1SS

Ves = 10 V, Vas =
Crss

en
NF

VG4 =

a V,

aV

0.1

3

0.4

3.5

1.2

f = 1 kHz

aV

f = 1 MHz

Ves = 10 V, Vas =
f = 100 Hz

aV

Ves = 15 V, Vas = a V, f = 1 kHz
Ra=lMn.

50

75

100

3.2

5

5

5

1.5

2

2

2

12

25

25

25

%
"HZ

0.1

1

1

1

dB

pF

l1li

T A = 25°C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 300 JJ.s , duty cycle :s 3 %.
Forward diode current when a voltage Is applied between gate and fourth lead.

4-53

.rSiliconix

BF244 SERIES

~ incorporated

N-Channel JFETs

The BF244 Series of n-channel JFETs is selected
into narrow current ranges to simplify design and
biasing requirements of high performance JFET
amplifier stages.
The BF244A, BF244B, and
BF244C have been selected into loss ranges of
2 to 6.5 mA, 6 to 15 mA, and 12 to 25 mA
respectively. Additionally, this series features high
gain (>3 mS) and low capacitance. Finally, its
TO-92 package offers the designer low cost and
compatibility with automated assembly.
(See
Section 8.)

PART
NUMBER
BF244A
BF244B
BF244C

For additional design information please see
performance curves NH, which are located in
Section 7.

MIN
(mS)

loss
MAX
(mA)

-30

3

6.5

-30

3

15

-30

3

25

VGS(OFF) V(BR)GSS
MIN
MAX
(V)
(V)

-8
-8
-8

Qfs

BOTTOM VIEW

TO-92

1 SOURCE
2 GATE
3 DRAIN

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

Vao

-30

Gate-Source Voltage

Vas

-30

Gate Current

la

10

mA

Power Dissipation

Po

360

mW

3.27

mW/oC

V

Power Derating
Operating Junction Temperature

TJ

-55 to 135

Storage Temperature

T stg

-55 to 150

Lead Temperature
(1/16" from case for 10 seconds)

lL

300

4-54

°C

BF244 SERIES

.r'Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
BF244A

TYp2

MIN

-35

-30

MIN

MAX

BF244C

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -lJ1A, V DS = 0 V

Gate-Source
Cutoff Voltage

VGS(OFF)

V DS = 15 V, ID = 10J,1A

-0,5

-8

-0.5

-8

-0.5

-8

Saturation Drain
Current 3

IDss

V DS = 15 V, VGS = 0 V

2

6.5

6

15

12

25

Gate Reverse Current

IGSS

PARAMETER

MAX

BF244B

MIN

MAX UNIT

STATIC

Gate Operating
Current
Gate-Source Voltage
Gate-Source
Forward Voltage

-30

-30
V

IG

VGS = -20 V
VOS = 0 V

-5

-0.002
ITA =125°C

VOG = 10 V, I D = 1 mA

VGS

VOS = 15 V, 10 = 200 J,1A

VGS(F)

I G =1mA,Vos =OV

gfs

Vos = 15 V, vGS = 0 V
f = 1 kHz

-5

mA

-5
nA

-1
-20

pA
-0.4

-2.2

-1.6

-3.8

-3.2

-7.5
V

0.7

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Capacitance
Common-Source
Output Capacitance
Equivalent Input
Noise Voltage
NOTES:

C lss
Crss

6.5

3

6.5

3

6.5

mS

2
Vos = 20 V, VGS = -1 V
f = 1 MHz

0.8

pF

1

Coss

en

3

Vos = 10 V, VGS = 0 V
f=100Hz

10

%
VRZ

1. T A = 25 °C unless otherwise noted.
2, For design aid only, not subject to production testing.
3. Pulse test; PW = 300J1s, duty cycle S3%.

l1li

4-55

crSiliconix

BF245 SERIES

~ incorporated

N-Channel JFETs

The BF245 Series of n-channel JFETs is selected
into narrow current ranges to simplify design and
biasing requirements of high performance JFET
amplifier stages.
The BF245A, BF245B, and
BF245C have been selected into loss ranges of
2 to 6.5 mA, 6 to 15 mA, and 12 to 25 mA
respectively. Additionally, this series features high
gain (>3 mS) and low capacitance. Finally, its
TO-92 package offers the designer low cost and
compatibility with automated assembly.
(See
Section 8.)

PART
NUMBER
BF245A
BF245B
BF245C

For additional design information please see
performance curves NH, which are located in
Section 7.

VGS(OFF) V(BR)GSS
MIN
MAX
(V)
(V)

-8
-8
-8

Sis
MIN
(mS)

loss
MAX
(mA)

-30

3

6.5

-30

3

15

-30

3

25

BOTTOM VIEW

TO-92

1 GATE
2 SOURCE
3 DRAIN

ABSOLUTE MAXIMUM RATINGS (T A = 25 DC unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

VGO

-30

Gate-Source Voltage

VGS

-30

Gate Current

IG

10

mA

Power Dissipation

Po

360

mW

3.27

mW/oC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-56

TJ

-55 to 135

T stg

-55 to 150

TL

300

°C

BF245 SERIES

~Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
BF24SA

BF24SB

BF24SC

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)aSS

la = -lJ1A, V DS = 0 V

-35

-30

Gate-Source
Cutoff Voltage

VaS(OFF)

V DS = 15 V, ID = 10.JJA

-O.S

-8

-0.5

-8

-0.5

-8

Saturation Drain
Current 3

I DSS

V DS = 15 V, Vas = 0 V

2

6.5

6

15

12

25

Gate Reverse Current

lass

PARAMETER

MAX

MIN

MAX

MIN

MAX UNIT

STATIC

Gate Operating
Current
Gate-Source Voltage
Gate-Source
Forward Voltage

-30

-30
V

la

Vas = -20 V
V DS = 0 V

-0.002

i TA=125°C

V Da =10V,I D =lmA

Vas

V Da = 15 V, ID= 200)1A

VaS(F)

I a = 1 mA, V DS = 0 V

gfs

VDS = 15 V, Vas = 0 V
f = 1 kHz

-S

-5

mA

-5
nA

-1
-20

pA
-0.4

-2.2

-1.6

-3.8

-3.2

-7.5
V

0.7

DYNAMIC
Common-Source

Forward
Transconductance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Caoacltance
Common-Source
Output Capacitance
Equivalent Input
Noise Voltage
NOTES:

C lss
erss

6.5

3

6.5

3

6.5

mS

2
V DS = 20 V, Vas = -1 V
f = 1 MHz

0.8

pF

1

Coss

en

3

V DS = 10 V, Vas = 0 V
f = 100 Hz

10

%
VHz

1. T A = 25 °C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test: PW =300J1s, duty cycle S3o/c.

4-57

..

.r'Siliconix

BSR56 SERIES

~ incorporated

N-Channel JFETs

The BSR56 Series is an-channel JFET mounted in
our popular SOT-23 package. Its low cost and
rOS(ON) make it a good choice for an all-purpose
analog switch, while its high gfs and good
high-frequency response also make this product
useful in a high-gain amplifier mode.
Like all
SOT-23 products available from Siliconix, 'tape and
reel capabilities exist for automated assembly.
(See Section 8.)

rds(ON) IO(OFF)
MAX
TYP
(pA)
(.0)

VGS(OFF)
MAX
(V)

BSR56

-10

25

5

4

BSR57

-6

40

5

4

BSR58

-4

60

5

4

SOT-23
For further design information please consult the
typical performance curves NCB which are located
in Section 7.

TOP VIEW

~

~

SIMILAR PRODUCTS
'.
•
•

tON
TYP
(n9)

PART
NUMBER

1 GATE
2 SOURCE
3 DRAIN

TO-18, See 2N4856 Series
TO-92, See PN4391 Series
Duals, See 2N5564 Series

PRODUCT MARKING
BSR56

M4

BSR57

M5

BSR58

M6

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL.

LIMIT

UNITS

Gate-Drain, Drain-Source Voltage

VGO

-40

Gate-Source Voltage

VGS

-40

IG

50

mA

Po

350

mW

2.8

mW/oC

V

Gate Current
Power Dissipation (TA

= 65°C)

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-58

TJ

-55 to 175

Tstg

-55 to 175

TL

300

°C

BSR56 SERIES

.:F'Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
BSR56

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

I G =-l,IJ.A,V os =OV

-55

-40

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 15 V, 10 = 0.5 nA

-4

aV

50

PARAMETER

MAX

BSR57
MIN

MAX

BSR58
MIN

MAX UNIT

STATIC

V

Saturation Drain
Current 3

loss

Gate Reverse Current

IGSS

Vos = 15 V, V GS =
V GS = -20 V
VOS = 0 V
Vos = 15

Drain Cutoff Current

Drain-Source
On-Voltage

-40

-40

10(OFF)

VOS(ON)

V.

-0.005
TA =125°C
V GS = -10 V

VOS = 15 V. V GS = -10 V
TA =125°C
V GS = 0 V

-10

-2

-6

-0.8

-4

20

100

6

60

-1

-1

-1

1

1

1

rnA

-3
0.005

nA

3

10 = 20 rnA

500

10 = 10 rnA

350

10 = 5 rnA

250

750
500

mV
400

rOS(ON)

V GS = 0 V, 10 = 1 rnA

25

40

60

.n.

rds(ON)

VGs=OV,lo =OmA
f = 1 kHz

25

40

60

.n.

Common-Source
Input Capacitance

Ciss

Vos = 20 V, VGS = 0 V
f = 1 MHz

13

Common-Source
Reverse Transfer
Capacitance

Crss

Vos = 0 V, V GS = -10 V
f = 1 MHz

3.5

5

5

5

25

50

100

Drain-Source
On-Resistance

DYNAMIC
Drain-Source
On-Resistance

pF

SWITCHING
Turn-on Time

tON

Turn-off Time

tOFF

NOTES:

Voo = 10 V, VGS(ON) = 0 V
PIN
10(oN)
VGS(OFF)
BSR56
20 rnA
-10 V
-6 V
BSR57
lOrnA
-4 V
SmA
BSR56

4
ns
19

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =100 ms, duty cycle 53%.

4-59

.r'Siliconix

CR022 SERIES

~ incorporated

Current Regulator Diodes

The CR022 Series is a family of precision current
regulators designed for demanding appli.cations in
test equipment and instrumentation.
These
devices combine the proven performance of a JFET
with an integrated resistor to produce a single
two-leaded device which is extremely simple to
operate.
With nominal current ranges from
0.22 mA to 5.30 mA, the CR022 Series will meet a
wide array of design requirements. In addition to its
two-lead construction, this series features 10%
current ranges, improved current control over wide
temperature ranges,
and Simple "floating"
operation as no power supplies are required for
biasing.
Finally, its TO-18 hermetically sealed
package is available with military processing per
MIL-S-19500. (See Section 1.)

PART

IF
(mA)

PART

IF
(mA)

PART

IF
(mA)

CR022
CR024
CR027
CR030
CR033
CR039
CR043
CR047
CR056
CR062
CR068

0.22
0.24
0.27
0.30
0.33
0.39
0.43
0.47
0.56
0.62
0.68

CR075
CR082
CR091
CR100
CRll0
CR120
CR130
CR140
CR150
CR160
CR180

0.75
0.82
0.91
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.80

CR200
CR220
CR240
CR270
CR300
CR330
CR360
CR390
CR430
CR470
CR530

2.00
2.20
2.40
2.70
3.00
3.30
3.60
3.90
4.30
4.70
5.30

For additional design information please see typical
performance curves (Section 7) as follows:
CR022 - CR062
CR068 - CR150
CR160 - CR530

TO-18 2 LEADS

NKL
NKM
NKO

~

SIMILAR PRODUCTS
•
•
•

BOTTOM VIEW

1 ANODE
2 CATHODE

TO-92 , See J500 Series
20% Ranges, See CRR0240 Series
Chips, Order CRXXXCHP

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Pov

100

V

IR

50

mA

RthJC

100

DC/W

Power Dissipation at T C = 25DC

PD

1.25

W

Operating Junction Temperature

TJ

-55 to 150

T stg

-55 to 200

Peak Operating Voltage
Reverse Current
Thermal Resistance

DC
Storage Temperature

4-60

ELECTRICAL CHARACTERISTICS (T A = 25 °C unless otherwise noted)
SYMBOL

IF

Zd

Zk

VL

POV

PARAMETER

REGULATOR
CURRENT

DYNAMIC
IMPEDANCE

KNEE
IMPEDANCE

LIMITING
VOLTAGE

PEAK
OPERATING
VOLTAGE

TEST
CONDITIONS

VF =25 V
(Note 1)

V F =25 V
(Note 2)
M!1

mA

UNITS
NOM

MIN

VF = 6 V

IF

V

TYP

TYP

2.2
(All)

2200
1800
1450
1100
800
500
250
0
-200
-600

4.2
(All)

-350
-450
-550
-650
-750
-875
-1000
-1100
-1200
-1300

6
(All)

1000
650
300
100
0
-200
-400
-550
-730
-820
-1000
-1125
-1250

TYP

MIN

9000
8.000
7.000
6.000
5000
4 100
3.300
2.700
1.900
1 550

18.00
15.50
13.00
11.50
10.00
9.00
8.00
7.00
6.00
450

2.750
2.350
1.950
1.600
1.350
1.000
0.870
0.750
0.560
0.470

3.50
3.00
2.50
2.00
1.80
1.50
1.30
1.20
090
0.70

1.00
1.00
1.00
1.00
1.00
1.05
1.05
1.10
1.20
1.30

0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.82
0.90

CR068
CR075
CR082
CR091
CR100
CR110
CR120
CR130
CR140
CR150

0.68
0.75
0.82
0.91
1.00
1.10
1.20
1.30
1.40
1.50

0.612
0.675
0.738
0.819
0.900
0.990
1.080
1.170
1.260
1.350

0.748
0.825
0.902
1.001
1.100
1.210
1.320
1.430
1.540
1.650

1 350
1 150
1.000
0880
0.800
0.700
0640
0.580
0.540
0.510

10.00
9.00
7.80
660
5.50
4.80
4 10
3.50
3.10
2.70

0.400
0.335
0.290
0.240
0.205
0.180
0.155
0.135
0.115
0.105

1.80
1.60
1.40
1.20
. 1.00
0.90
0.80
0.80
0.70
0.60

1.15
1.20
1.25
1.29
1.35
1.40
1.45
1.50
1.55
1.60

0.85
0.90
0.95
1.00
1.06
1.12
1.18
1.25
1.32
1.40

CR160
CR180
CR200
CR220
CR240
CR270
CR300
CR330
CR360
CR390
CR430
CR470
CR530

1.60
1.80
2.00
2.20
2.40
2.70
3.00
330
3.60
3.90
4.30
4.70
530

1.440
1.620
1.800
1.980
2.160
2.430
2.700
2.970
3.240
3.510
3.870
4.230
4770

1.760
1.980
2.200
2.420
2.640
2.970
3.300
3.630
3.960
4.290
4730
5 170
5.830

0.475
0420
0395
0.370
0345
0.320
0300
0.280
0265
0255
0245
0235
0.220

1.10
1 00
0.90
0.83
0.76
070
065
0.60
0.54
0.47
0.40
035
0.30

0092
0.074
0.061
0.052
0.044
0.035
0.029
0.024
0.020
0.017
0.014
0.012
0.010

0.40
0.34
0.28
0.25
0.22
0.19
0.16
014
0.13
0.12
0.10
0.09
0.07

1.65
1.75
1.85
1.95
2.00
2.15
2.25
2.35
2.50
2.60
2.75
2.90
3.10

0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1 17
1.25
1.32
1.40

f"

MAX

TYP

MIN

0242
0.264
0.297
0.330
0.363
0429
0.473
0.517
0.616
0.682

-

~~.

ppm/DC

0.198
0.216
0.243
0.270
0.297
0.351
0.387
0.423
0.504
0.558

Pulse test - steady state currents may vary.
Pulse test - steady state Impedances may vary.
Min VF required to insure IF> 0.8 IF(MIN)'
Max VF where IF < 1.1 i F(MAX) is guaranteed.

VF = 25 V
ODCS TAS 100 DC

pF

IF

=1.1I F(MAX)

MIN

100
(All)

100
(All)

100
(All)

TYP

180
(All)

180
(All)

175
(All)

0_,

0-

V

0.22
0.24
0.27
0.30
0.33
0.39
0.43
0.47
0.56
0.62

NOTES' 1
2.
3.
4.

-tin'

(Note 4)

M!1
TYP

CAPACITANCE

TEMPERATURE
COEFFICIENT

(Note 3)

CR022
CR024
CR027
CR030
CR033
CR039
CR043
CR047
CR056
CR062

MAX

9,

VF =25 V
f =1 MHz

=0.8 I F(MIN)

~
5'0)

CF

DO

o..>C

o

:II

o

I\)
I\)

en

m

:II

m

en

~

II

~Siliconix

CRR0240 SERIES

~ incorporatec

Current Regulator Diodes

The CRR0240 Series is a family of precision current
regulators designed for demanding applications in
test equipment and instrumentation.
These
devices combine the proven performance of a JFET
with an integrated resistor to produce a single
two-leaded device which is extremely simple to
operate.
With nominal current ranges from
0.24 rnA to 4.3 rnA, the CRR0240 Series will meet
a wide array of design requirements. In addition to
its two-lead construction, this series features ±25%
current ranges, current control over wide
temperature ranges,
and simple "floating"
operation as no power supplies are required for
biasing.
Finally, its TO-1B hermetically sealed
package is available with military processing per
MIL-S-19500. (See Section 1.)
For additional design information please see typical
performance curves as follows (Section 7):

PART

IF
(rnA)

CRR0240
CRR0360
CRR0560
CRROBOO
CRR1250
CRR1950
CRR2900
CRR4300

0.24
0.36
0.56
O.BO
1.25
1.95
2.90
4.30

TO-1B 2 LEADS

BOTTOM VIEW

CRR0240-CRR0560 .. NKL
CRROBOO-CRR1250 .. NKM
CRR1950-CRR4300 .. NKO

SIMILAR PRODUCTS
•
•
•

1 ANODE
2 CATHODE

TO-92 , See J500 Series
10% Ranges, See CR022 Series
Chips, Order CRRXXXXCHP

ABSOLUTE MAXIMUM RATINGS (T A = 25 DC unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Pav

100

V

IR

50

rnA

Thermal Resistance

eJC

100

°C/W

Power Dissipation at T C = 25°C

PD

1.25

W

Operating Junction Temperature

TJ

-55 to 150

T stg

-55 to 200

Peak Operating Voltage
Reverse Current

°C
Storage Temperature

4-62

~
:i'm
n_.

ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)
SYMBOL

IF

Zd

Zk

VL

POV

CF

9,

PARAMETER

REGULATOR
CURRENT

DYNAMIC
IMPEDANCE

KNEE
IMPEDANCE

LIMITING
VOLTAGE

PEAK
OPERATING
VOLTAGE

CAPACITANCE

TEMPERATURE
COEFFICIENT
(TYPICALS)

TEST
CONDITIONS

V F = 25 V
(Nole 1)

VF = 25 V
(Note 2)

VF = 6 V

IF = 0.8 I FIMINI
(Nole 3)

IF = 1.1 IFIMAXI
(Nole 4)

V F = 25 V
f = 1 MHz

V F = 25 V
O°C'; T A" 100°C

mA

Mfi

Mfi

V

V

pF

ppm/oC

UNITS
NOM

MIN

MAX

MIN

TYP

TYP

MAX

TYP

MIN

TYP

TYP

TYP

CRR0240
CRR0360
CRR0560

0.24
0.36
0.56

0.180
0.270
0.420

0300
0.450
0.700

5.00
2.50
1.20

15.50
9.50
6.00

3.00
1.70
090

1.00
1 05
1.30

045
0.65
0.82

100
100
100

180
180
180

2.2
2.2
2.2

1800
650
-200

CRR0800
CRR1250

080
1.25

0600
0.937

1.000
1.560

080
0.50

7.80
3.70

1.40
0.80

1 35
1.60

0.95
1.20

100
100

180
180

42
4.2

-550
-1050

CRR1950
CRR2900
CRR4300

1 95
290
4.30

1 460
2.160
3.240

2440
3.600
5.400

0.37
0.28
0.22

090
0.65
040

0.28
0.16
0.10

1 95
2.35
3.00

080
1.00
1.25

100
100
100

175
175
175

60
60
6.0

300
-400
-1125

c=

-riO

DO

~::J
m-'
c.>C

i

-

NOTES: 1.
2.
3
4.

Pulse lesl - sleady slale currenls may very.
Pulse lest - sleady state Impedances may vary.
Min VF required to Insure IF> 0.8 I FIMIN) .
MaxVF where IF> 1 1 IFIMAXI Is guaranteed.

o

:II
:II
o
I\)

8
en
m

:II

m

./>0

m

en

w

II

.r-Siliconix

DPAD1 SERIES

~ inccrpcrater:!

Dual Low-Leakage Pica-Amp Diodes

The DPADl Series of extremely low-leakage diodes
provides a superior alternative to conventional
diode technology when reverse current (leakage)
must be minimized. These devices feature leakage
currents ranging from -1 pA (DPAD1) to -100 pA
(DPAD100) to support a wide range of applications.
With two diodes per package, the DPADl Series is
well suited for use in applications such as input
protection for operational amplifiers. Its hermetically sealed metal can is available with full military
processing per MIL-S-19500. (See Section 1.)

IR
(pA)

PART NO.
DPADl

-1

DPAD2

-2

DPAD5

-5

DPAD10

-10

DPAD20

-20

DPAD50

-50

DPAD100

-100

SIMILAR PRODUCTS
•
•
•
•

TO-92, See JPAD5 Series
SOT-23, See SSTPAD5 Series
TO-18, See PADl Series
Chips, Order DPADXXCHP

TO-78 (MODIFIED)

1
2
3
4
5

BOTTOM VIEW

1:0-71 (MODIFIED)

CATHODE 1
ANODE 1
CASE
CATHODE 2
ANODE 2

1
2
3
4

PARAMETERS/TEST CONDITIONS

CATHODE 1
ANODE 1
CATHODE 2
ANODE 2

(DPAD2, 5, 10, 20, 50, 100)

(DPAD1)

ABSOLUTE MAXIMUM RATINGS (T A

BOTTOM VIEW

= 25 DC unless otherwise

noted)

SYMBOL

LIMIT

UNITS

Forward Current

IF

50

mA

Total Device Dissipation

PD

400

mW

Tstg

-55 to 125

h

300

Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-64

°C

DPAD1 SERIES

.:y-Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

MAX

UNIT

STATIC
DPADl
DPAD2
Reverse Current

Reverse Breakdown Voltage

Forward Voltage Drop

IR

BVR

VF

VR = -20 V

IR = -1 J.LA

-0.2

-1
-2

DPAD5

-1
-2

DPAD10

-3

-10

DPAD20

-5

-20

DPAD50

-10

-50

DPAD100

-15

-100

DPAD1, 2, 5

-60

-45

DPAD10, 20
DPAD50, 100

-55

-35

IF = 1 rnA

-5
pA

-120
V

0.7

1.5

0.6

O.B

1

2

0.07

0.2

DYNAMIC

Reverse Capacitance

Differential Capacitance

NOTES:

CR

i C R1- C R2 i

VR = -5 V
f = 1 MHz

DPAD1,2,5
DPAD10, 20
DPAD50, 100

VRI =VR2 = -5 V, f = 1 MHz

pF

1. T A = 25·C unless otherwise noted.
2. For design aid only, not subject to production testing.

III

4-65

J105 SERIES

.rSiliconix

~ incorporated

N-Channel JFET

The Jl05 Series is a high-performance JFET analog
switch designed to offer low on-resistance and fast
switching. rOS(ON) <3 !l is guaranteed with the
Jl05 which makes this device the lowest of any
commercially available JFET. This device is housed
in a low-cost TO-92 package and offers a wide
range of lead-forms and lor tape and reel options.
(See Section 8.)

PART
NUMBER

Vas (OFF)
MAX
(V)

rds(ON) IO(OFF)
TYP
MAX
(!l)
(pA)

tON
TYP
(n5)

Jl05

-10

3

10

14

Jl06

-6

6

10

14

Jl07

-4.5

8

10

14

For further design information please consult the
typical performance curves NVA which are located
in Section 7.
BOTTOM VIEW

TO-92

SIMILAR PRODUCTS
•
•

TO-52, See U290 Series
Chips, Order Jl0XCHP
1 DRAIN
2 SOURCE
3 GATE

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

= 25 DC unless otherwise

noted)

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

Vao

-25

Gate-Source Voltage

Vas

-25

Gate Current

IG

50

mA

Power Dissipation

Po

360

mW

3.27

mW/DC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-66

TJ

-55 to 135

T stg

-55 to 150

h

300

DC

J105 SERIES

~Siliconix
incorporated

..LII

ELECTRICAL CHARACTERISTICS 1

LIMITS

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

IG=-l)J.A.VDS =OV

-35

-25

Gate-Source
Cutoff Voltage

VGS(OFF)

V DS = 5 V. ID = l)J.A

-4.5

Saturation Drain
Current 3

IDSS

VDS = 15 V. VGS = 0 V

500

Gate Reverse Current

IGSS

PARAMETER

J107

J106

J105
MAX

MIN

MAX

MIN

MAX UNIT

STATIC

Gate Operating
Current

Drain Cutoff Current

-25

-25
V

IG

V GS = -15 V
V DS = 0 V

-0.02
ITA =125°C

-10

-2

-6

200

-0.5

-4.5

100

mA

-3

-3

-3

3

3

3

3

6

8

-10

V DG = 10 V. ID = 25 mA

-0.01

V DS = 5 V. V GS = -10 V

0.01

V DS = 5 V, V GS = -10 V
T A =125°C

5

nA
ID(OFF)

Drain-Source
On-Resistance

rDS(ON)

V GS = 0 V. V DS S 0.1 V

Gate-Source
Forward Voltage

VGS(F)

I G = 1 mAo VDS = 0 V

.n.

0.7

V

55

mS

5

)J.S

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Drain-Source
On-Resistance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Caoacitance
Equivalent Input
Noise Voltage

gt.
gas
rdS(ON)

V DG = 10 V. I D = 25 mA
f = 1 kHz
V GS = 0 V. ID = 0 mA
f = 1 kHz

3

6

8

C lss

V DS = 0 V. V GS = 0 V
f = 1 MHz

120

160

160

160

Crss

V DS = 0 V. V GS = -10 V
f = 1 MHz

20

35

35

35

en

VOG = 10 V. 10 = 25 mA
f = 1 kHz

3

.n.

pF

%
"Hz

SWITCHING
Turn-on Time

td(ON)
tr

Turn-off Time

td(OFF)
tt

NOTES:

VDD = 1.5 V. VGS(ON) =
PIN
ID(ON) VGS(OFF)
-12 V
Jl05
28 mA
-7 V
J106
27 mA
J107
-5 V
26 mA

0V
RL
50.n.
50.n.
50.n.

6
8
5

ns

9

1. T A = 25 • C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW =300)J.S. duty cycle S3%.

4-67

..

.r-Siliconix

J108 SERIES

~ incorporated

N-Channel JFET

The J1 08 Series is designed with high-performance
analog switching applications in mind. It features
low on-resistance. good off-isolation. and fast
switching. The TO-92 package affords low-cost and
a wide range of lead-forms and tape and reel
options. (See Section 8.)

PART
NUMBER

For further design information please consult the
typical performance curves NIP which are located in
Section 7.

VGS(OFF)
MAX
(V)

rds(ON) IO(OFF)
MAX
TYP
(0)
(pA)

tON
TYP
(ns)

J108

-10

8

20

4

J109

-6

12

20

4

J110

-4

18

20

4

J110A

-4

25

20

4

SIMILAR PRODUCTS
TO-92
•
•
•

BOTTOM VIEW

SOT-23. See SST108 Series
TO-52. See 2N5432 Series
Chips. Order J1XXCHP

1 DRAIN
2 SOURCE
3 GATE

ABSOLUTE MAXIMUM RATINGS (T A = 25 DC unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

VGO

-25

Gate-Source Voltage

VGS

-25

Gate Current

IG

50

mA

Power Dissipation

Po

360

mW

3.27

mW/DC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-68

TJ

-55 to 135

T stg

-55 to 150

lL

300

DC

J108 SERIES

~Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
Jl08

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

I G =-lJ.lA,VDS =OV

-32

-25

Gate-Source
Cutoff Voltage

VGS(OFF)

V DS = 5 V, I D = 1 J.lA

-3

Saturation Drain
Current 3

IDSS

V DS = 15 V, VGS = 0 V

80

Gate Reverse Current

IGSS

PARAMETER

Jl09

MAX

MIN

MAX

UNIT

STATIC

Gate Operating
Current

Drain Cutoff Current

-25
V

VGS = -15 V
V DS = a V

IG

-0.01

I

T A =125°C

-10

-2

-6

40

rnA

-3

-3

3

3

8

12

-5

V DG = 10 V, ID = 10 rnA

-0.01

V DS = 5 V, VGS = -10 V

0.02

V DS = 5 V. VGS = -10 V
TA =125°C

10

nA
ID(OFF)

Drain-Source
On-Resistance

rDS(ON)

Gate-Source
Forward Voltage

VGS(F)

VGS = 0 V, V DS = :!5 0.1 V
I G = 1 rnA, V DS = 0 V

.n

0.7

V

17

mS

600

J.lS

DYNAMIC
Common-Source
Forward
Transcontluctance
Common-Source
Output Conductance
Drain-Source
On-Resistance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Caoacitance
Equivalent Input
Noise Voltage

gfs

V DG =5V,I D =10mA
f = 1 kHz

gas

VGS = 0 V, ID = 0 rnA
f = 1 kHz

rdS(ON)
C 1SS

V DS = 0 V, VGS =
f = 1 MHz

Crss

V DS =

en

aV

8

12

60

85

85

11

15

15

.n
pF

a V,

VGS = -10 V
f = 1 MHz

V DG = 5 V, ID = 10 rnA
f = 1 kHz

3.5

%
"Hz'

SWITCHING
Turn-on Time
Turn-off Time

d(ON)

PIN

ID(ON)

VGS(OFF)

td(OFF)

Jl08
Jl09

lOrnA
lOrnA

-12 V
-7 V

tf
NOTES:

VDD = 1.5 V, VGS(ON) = 0 V

t,

3

1

RL
150
150

.n.
.n.

4

ns

18

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 JJ.S, duty cycle :!5 3%.

4-69

..

J108 SERIES

~SilicDnix

~ incorporated

El.ECTRICAl. CHARACTERISTICS 1

LIMITS
J110

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -1.11A, VOS = 0 V

-32

-25

Gate-Source
Cutoff Voltage

VGS(OFF)

VOS = 5 V, 10 = 1 .I1A

-0.5

Saturation Drain
Current 3

loss

Vos = 15 V, V GS = 0 V

10

Gate Reverse Current

IGSS

PARAMETER

J110A

MAX

MIN

MAX

UNIT

STATIC

Gate Operating
Current

Drain Cutoff Current

-25
V

V GS = -15 V
VOS = 0 V

IG

-0.01

I

T A =125°C

-4

-0.5

-4

10

rnA

-3

-3

3

3

18

25

-5

VOG = 10 V, 10 = 10 rnA

-0.01

Vos = 5 V, V GS = -10 V

0.02

nA
iO(OFF)

v:

Vos = 5
V GS = -10 V
TA=125°C

Drain-Source
On-Resistance

rOS(ON)

Gate-Source
Forward Voitage

VGS(F)

10

V GS = 0 V, Vos = S 0.1 V
I G =.1 rnA, Vos = 0 V

.0.

0.7

V

17

mS

600

jJ.S

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Drain-Source
On-Resistance
Common-Source
Input Capacitance
Common-Source

~~~~~~a~~:nsfer
Equivalent input
Noise Voltage

gts

V OG =5V,1 0 =10mA
f = 1 kHz

gos
rds(ON)

V GS = 0 V, io = 0
f = 1 kHz

C iss

Vos = 0 V, VGS = 0 V
f = 1 MHz

erss

en

18

25

60

85

85

Vos '7 0 V, VGS = -10 V
f = 1 MHz

11

15

15

VOG = 5 V, 10 = 10 rnA
f = 1 kHz

3.5

.0.

pF

%
VHz

SWITCHING
Turn-on Time
Turn-off Time

d(ON)
t,
td(OFF)
tf

VOO = 1.5 V, VGS(ON) = 0 V
PIN

10(ON)

VGS(OFF)

J110
J110A

10 rnA
10mA

-5 V
-5 V

NOTES: 1. T A = 25 ° C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300jJ.S, duty cycle S30/0.

4-70

RL
150 .0.
150 .0.

3
1
4
20

ns

fCrSiliconix

~ incorporated

J111 SERIES
N-Channel JFET

The Jlll Series is a low-cost, all-purpose analog
switch designed to support a wide range of
applications.
It features low on-resistance,
capacitance and good off-isolation. Additionally,
our TO-92 package allows a variety of lead-forms or
tape and reel combinations. (See Section 8.)

PART
NUMBER

For further design information please consult the
typical performance curves NCB which are located
in Section 7.

VGS(OFF)
MAX
(V)

rds(ON) IO(OFF)
MAX
TYP
(D)
(pA)

tON
TYP
(ns)

Jlll

-10

30

5

4

J112

-5

50

5

4

Jl13

-3

100

5

4

SIMILAR PRODUCTS
•
•
•
•

TO-92

SOT-23, See SSTlll Series
TO-18, See 2N4391 Series
Duals, See 2N5564 Series
Chips, Order JllXCHP

BOTTOM VIEW

1 DRAIN
2 SOURCE
3 GATE

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

= 25°C unless

otherwise noted)

SYMBOL

LIMIT

Gate-Drain Voltage

VGO

-35

Gate-Source Voltage

VGS

-35

Gate Current

IG

50

mA

Power Dissipation

Po

360

mW

3.27

mW/oC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 135

T stg

-55 to 200

TL

300

°C

4-71

III

~Siliconix
incorporated

J111 SERIES

.LII
LIMITS

ELECTRICAL CHARACTERISTICS 1
Jlll

TYp2

MIN

-55

-35

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)GSS

I G =-lJ,LA.Vos =OV

Gate-Source
Cutoff Voltage

VGS(OFF)

VOS = 5 V. 10 = 1 J,LA

-3

Saturation Drain
Current 3

'loss

Vos = 15 V. V GS = 0 V

20

Gate Reverse Current

IGSS

PARAMETER

Jl13

Jl12

MAX

MIN

MAX

MIN

MAX UNIT

STATIC

Gate Operating
Current

Drain Cutoff Current

-35

-35
V

VGS = -15 V
Vos = 0 V

IG

IO(OFF)

-0.005
IT A =125°C

-10

-1

-5

5
-1

-3
2

-1

rnA
-1

nA

-3

VOG = 15 V. 10 = 10 rnA

-5

Vos = 5 V, VGS = -10 V

0.005

Vos = 5 V, V GS = -10 V
TA =125°C

3

pA
1

1

1
nA

Drain-Source
On-Resistance

rOS(ON)

V GS = 0 V. VOS = 0.1 V

Gate-Source
Forward Voltage

VGS(F)

I G = 1 rnA. Vos = 0 V

0.7

V

V oG =20V, 10= 1 rnA
f = 1 kHz

6

mS

25

J,LS

30

50

100

.0.

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Drain-Source
On-Resistance
Common-Source
Input Capacitance
Common-Source

~~~~~~a~~~nsfer
Equivalent Input
Noise Voltage

gts
gos

V GS = 0 V. 10 = 0 V
f = 1 kHz

rdS(ON)
C lss

Vos = 0 V. VGS = -10 V
f = 1 MHz

Crss

30

50

100

7

12

12

12

3

5

5

5

.0.

pF

en

VOG=10V.lo=lmA
f = 1 kHz

4

td(ON)

Voo = 10 V. VGS(ON) = a V
RL
IO(ON) VGS(OFF)
-12 V
600 .0.
J111
12 rnA
-7 V 1600.0.
J112
6mA
J113
3mA
-5 V 3200.0.

2

%
"Hz

SWITCHING
Turn-on Time
Turn-off Time

t,
td(OFF)

tt

PIN

NOTES: 1. T A = 25 ° C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW = 300 J,LS, duty cycle S 3%.

4-72

2
6
15

ns

J111 A SERIES

.:rSiliconix

~ incorporated

N-Channel JFET

The J 111 A Series is a low-cost. all-purpose analog
switch designed to support a wide range of
applications. In addition to low on-resistance and
capacitance.
this series guarantees higher
breakdown voltage and significantly lower leakage
than its counterpart. the Jlll Series. Finally. its
TO-92 package allows a variety of lead-forms or
tape and reel combinations. (See Section B.)

PART
NUMBER

VGS(OFF)
MAX
(V)

rds(ON) IO(OFF)
MAX
MAX
(!l)
(pA)

tON
TYP
(ns)

JlllA

-10

30

200

Jl12A

-7

50

200

4

Jl13A

-5

BO

200

4

4

For further design information please consult the
typical performance curves NCB which are located
in Section 7.
TO-92

BOTTOM VIEW

SIMILAR PRODUCTS
•
•
•
•

SOT-23. See SSTlll Series
TO-lB. See 2N4391 Series
Duals. See 2N5564 Series
Chips. Order Jll XACHP

1 DRAIN
2 SOURCE
3 GATE

ABSOLUTE MAXIMUM RATINGS (T A = 25 °C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

VGO

-40

Gate-Source Voltage

VGS

-40

Gate Current

IG

50

mA

Power Dissipation

Po

360

mW

3.27

mW/oC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 135

Tstg

-55 to 150

TL

300

°C

4-73

g

J111A SERIES
ELECTRICAL CHARACTERISTICS 1

incorporated

LIMITS
JlllA

PARAMETER

Siliconix

TYp2

MIN

-55

-40

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)GSS

I G =-l.JJ.A,Vos =OV

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 5 V, 10 = 1 .JJ.A

-5

Saturation Drain
Current3

loss

Vos = 15 V, V GS = 0 V

30

Gate Reverse Current

IGSS

MAX

Jl12A
MIN

Jl13A

MAX

MIN

MAX UNIT

STATIC

Gate Operating
Current

-40

-40

V

IG

V GS = -15 V
VOS = 0 V

-5
ITA =125°C

-10

-2

-7

15
-200

-1

":5
rnA

8
-200

-200

-3

V OG=15V, 10 =10mA

-5

Vos = 5 V, VGS = -10 V

5

Vos = 5 V, V GS = -10 V
TA=125°C

3

pA
nA

pA
Drain Cutoff Current

10(OFF)

200

200

200
nA

Drain-Source
On-Resistance

rOS(ON)

VGS = 0 V, VOS = 0.1 V

Gate-Source
Forward Voltage

VGS(F)

IG = 1 rnA, VOS = 0 V

0.7

V

V OG=20V, 10= 1 rnA
f = 1 kHz

6

mS

25

.JJ.5

30

50

80

.n

DYNAMIC
Common-Source
Forward
Transconductance

g,s

Common-Source
Output Conductance

gas

Drain-Source
On-Resistance

rds(ON)

Common-Source
Input Capacitance

C iss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

en

V GS = 0 V, 10 = 0 V
f = 1 kHz
VOS = 0 V, VGS = -10 V
f = 1 MHz
VOG = 10 V, 10 = 1 rnA
f = 1 kHz

30

50

80

7

12

12

12

3

5

5

5

.n

pF

4

"J:,
VHz'

SWITCHING
Turn-on Time
Turn-off Time

td(ON)
tr
td(OFF)
t,

Voo = 10 V, VGS(ON) =
PIN
10(ON) VGS(OFF)
-12 V
JlllA 12 rnA
Jl12A
-7 V
6mA
-5 V
Jl13A
3mA

0V
RL
800.n
1600.n
3200.n

NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300.JJ.5 , duty cycle :$3%.

4-74

2
2
6
15

ns

ICrSiliconix

.LJI

incorporated

J174 SERIES
P-Channel JFET

The J 174 Series is a low-cost p-channel analog
switch designed to provide low on-resistance and
fast switching. It also works well in conjunction with
Siliconix' Jlll Series for complimentary switching
applications. It features a TO-92 package which is
available with various lead-forms andlor tape and
reel options. (See Section 8.)

PART
NUMBER

VGS(OFF)
MAX
(V)

For further design information please consult the
typical performance curves PSCIA which are
located in Section 7.

rds(ON) IO(OFF)
MAX
MAX
(!l)
(nA)

tON
TYP
(ns)

J174

10

85

-1

25

J175

6

125

-1

25

J176

4

250

-1

25

Jl77

2.25

300

-1

25

SIMILAR PRODUCTS
•
•
•

BOTTOM VIEW

TO-92

TO-18. See 2N5114 Series
SOT-23. See SST174 Series
Chips. Order J17XCHP

1 DRAIN
2 GATE
3 SOURCE

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

VGD

30

Gate-Source Voltage

VGS

30

Gate Current

IG

-50

mA

Power Dissipation

PD

360

mW

3.27

mW/oC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 135

T stg

-55 to 150

TL

300

°C

4-75

g

J174 SERIES
ELECTRICAL CHARACTERISTICS 1

Siliconix

incorporated

LIMITS
J174

J175

SYMBOL

TEST CONDITIONS

TYp2

Gate-Source
Breakdown Voltage

V(BR)GSS

I a = 1 J.lA, Vos = 0 V

45

Gate-Source
Cutoff Voltage

Vas (OFF)

Vos = -15 V, 10 = -10 nA

5

10

3

6

SaturatIon DraIn
Current 3

loss

Vos = -15 V, Vas = 0 V

-20

-135

-7

-70

Gate Reverse Current

lass

PARAMETER

MIN

30

MAX

MIN

MAX

UNIT

STATIC

Gate OperatIng
Current

Drain Cutoff Current

30
V

Vas = 20 V
Vos = 0 V

la

0.01

I

TA =125°C

1

1

-1

-1

85

125

rnA

5

Voa = -15 V, 10 = -1 rnA

0.01

Vos = -15 V, Vas = 10 V

-0.01

Vos = -15 V, Vas = 10 V
TA=125°C

-5

nA
10(OFF)

DraIn-Source
On-ResIstance

rOS(ON)

Vas = 0 V, Vos = -0.1 V

Gate-Source
Forward Voltage

Vas (F)

la=-lmA,Vos=OV

.0.

-0.7

V

4.5

mS

20

JJ,S

DYNAMIC
Common-Source
Forward
Transconductance

gls

Common-Source
Output Conductance

gos

DraIn-Source
On-ResIstance
Common-Source
Input CapacItance
Common-Source
Reverse Transfer
Caoacltance
Equivalent Input
Noise Voltage

Vos=-15V,lo =-lmA
f = 1 kHz

rds(ON)

Vas=OV,lo=O rnA
f = 1 kHz

C lss

Vos = 0 V, Vas = 0 V
f = 1 MHz

20

erss

Vos = 0 V, Vas = 10 V
f = 1 MHz

5

en

Vos = -10 V, 10 = -1 rnA
f = 1 kHz

20

85

125

.0.

pF

~
\1Hz

SWITCHING
Turn-on Time
Turn-off Time

td(ON)

PIN

Voo

Vas (OFF)

RL

15

td(OFF)

J174
J175

-10 V
-6 V

12 V
8V

560.n.
1200 .n.

10

tl

NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testIng.
3. Pulse test; PW =300J.lS, duty cycle S3%.

4-76

10

Vas (ON) = 0 V

tr

20

ns

J174 SERIES

~Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
J176

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)GSS

I G ; 1 ).lA, Vos ;

Gate-Source
Cutoff Voltage

VGS(OFF)

PARAMETER

TYp2

MIN

45

30

J177

MAX

MIN

MAX

UNIT

STATIC

loss

Gate Reverse Current

IGSS

Drain Cutoff Current

30
V

Saturation Drain
Current 3

Gate Operating
Current

av

VOS; -15 V, 10 ; -10 nA
Vos ; -15 V, V GS ;

0.01

V GS ; 20 V
Vos ; a V

IG

aV

I

T A ;125°C

1

4

O.B

2.25

-2

-35

-1.5

-20

1

1

-1

-1

250

300

mA

5

V OG ;-15V, 10 ;-1 mA

0.01

Vos ; -15 V, V GS ; 10 V

-0.01

VOS ; -15 V, V GS ; 10 V
T A ;125°C

-5

nA
10(OFF)

Drain-Source
On-Resistance

rOS(ON)

Gate-Source
Forward Voltage

VGS(F)

V GS ;

a V,

Vos ;

-0.1 V

I G; -1 mA, V DS ;

aV

n

-0.7

V

4.5

mS

20

).lS

DYNAMIC
Common-Source
Forward
Transconductance

gfs

Common-Source
Output Conductance

gas

Vos ; -15 V, 10 ; -1 mA
f ; 1 kHz

rds(ON)

V GS ;

a V, 10 ;
f ; 1 kHz

Common-Source
Input Capacitance

C iss

Vos ;

a v,

Common-Source
Reverse Transfer
Caoacitance

C rss

VOS ; 0 V, V GS ; 10 V
f ; 1 MHz

5

en

V DS ;-10V, 10 ;-1 mA
f ; 1 kHz

20

Drain-Source
On-Resistance

Equivalent Input
Noise Voltage

a

V GS ;
f ; 1 MHz

mA

250

aV

300

n

20
pF

~
"Hz

SWITCHING
Turn-on Time
Turn-off Time

td(ON)
PIN

td(OFF)

J176
J177

tf
NOTES:

VGS(ON) ; 0 V

t,

Voo
-6 V
-6 V

VGS(OFF)
6V
3V

10
15

RL
5600
10000

n
n

10

ns

20

1. T A; 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW ; 300).lS, duty cycle ~ 3%.

4-77

III

tcrSiliconix

J201 SERIES

~ incorporated

N-Channel JFETs

The J201 Series of popular, low-cost JFETs offers
high performance in a wide range of applications.
With features such as 100 pA gate leakage, -40 V
breakdown voltage, and 5 nVI-.JHZ noise, these
devices are especially characterized for sensitive
amplifier stages. The J201 and J204 with low cut
off voltages, are ideal for battery operated
equipment and low current amplifiers. The J201
Serie!! in the TO-92 package offers both value and
compatibility with automated assembly.

PART
NUMBER

VGS(OFF) V(BR)GSS
MIN
MAX
(V)
(V)

Qfs

MIN
(mS)

loss
MAX
(mA)

J201

-1.5

-40

0.5

1

J202

-4

-40

1

4.5

J203

-10

-40

1.5

20

J204

-2

-25

0.5

3

For further design information please consult the
typical performance curves NPA which are located
in Section 7.
TO-92

~N

SIMILAR PRODUCTS
•
•
•

BOTTOM VIEW

2 SOURCE
3 GATE

TO-1B, See 2N433B Series
SOT-23, See SST201 Series
Chips, Order J20XCHP

ABSOLUTE MAXIMUM RATINGS (T A = 25 DC unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT
J201-3

J204

Gate-Drain Voltage

Vao

-40

-25

Gate-Source Voltage

Vas

-40

-25

UNITS

V

Gate Current

la

50

mA

Power Dissipation

Po

360

mW

3.27

mW/oC

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-7B

TJ

-55 to 135

T stg

-55 to 150

TL

300

°C

J201 SERIES

.:rSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
J201

J202

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -U.lA. Vos = 0 V

-57

-40

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos=20V.lo=10nA

-0.3

-1.5

-0.8

-4

Saturation Drain
Current 3

loss

Vos = 20 V. VGS = 0 V

0.2

1

0.9

4.5

rnA

Gate Reverse Current

IGSS

-100

pA

PARAMETER

MAX

MIN

MAX

UNIT

STATIC

Gate Operating
Current

-40
V

Vas = -20 V
Vos = 0 V

-2

I

T A =125°C

-100

nA

-1

la

Voa = 15 V. 10 = 0.1 rnA

-2

Drain Cutoff Current

lo(oFF)

Vos = 15 V. Vas = -10 V

2

Gate-Source
Forward Voltage

VaS(F)

I a = 1 rnA. VOS = 0 V

0.7

gfs

Vos = 20 V. Vas = 0 V
f = 1 kHz

pA

V

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Capacitance
Equivalent Input
Noise Voltage

NOTES:

C lss

VOS = 20 V. Vas = 0 V
f = 1 MHz

erss

en

0.5

1

mS

4.5
pF
1.3

Vos = 10 V. Vas = 0 V
f = 1 kHz

6

%
\1Hz

1. T A = 25°C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW =300.l.ls. duty cycle S3%.

4-79

J201 SERIES

.:rSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
J203

J204

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

I G =-l.11A,Vos =OV

-57

-40

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos=20V,lo=10nA

-2

-10

-0.3

-2

Saturation Drain
Current 3

loss

Vos = 20 V, V GS = 0 V

4

20

0.2

3

rnA

Gate Reverse Current

IGSS

-100

pA

PARAMETER

MAX

MIN

MAX

UNIT

STATIC

Gate Operating
Current

-25
V

V GS = -20 V
VOS = 0 V

-2

I

TA=125·C

-100

-1

IG

V oG =15V,l o =O.lmA

-2

Drain Cutoff Current

IO(OFF)

Vos = 15 V, V GS = -10 V

2

Gate-Source
Forward Voltage

VGS(F)

IG = 1 rnA, VOS = 0 V

0.7

g,.

Vos = 20 V, V GS = 0 V
f = 1 kHz

nA

pA

V

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Capacitance
Equivalent Input
Noise Voltage

CI••

Cr••

en

VOS = 20 V, VGS = 0 V
f = 1 MHz

0.5

mS

4.5
pF
1.3

Vos = 10 V, VGS = 0 V
f = 1 kHz

NOTES: 1. T A = 25·C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300.l1s , duty cycle S 3 % .

4-80

1.5

6

'2.:"Hz

g

J210 SERIES

Siliconix

incorporated

N-Channel JFETs

The J210 Series of n-channel JFETs provides good
general purpose amplifiers for a wide range of test
and instrumentation applications.
This series
features low-leakage (I GSS < 100 pA), high gain
(gfs> 7 mS for J212), and low noise. Additionally,
its low cost TO-92 package ensures value as well as
compatibility with automated assembly techniques.
(See Section 8.)

PART
NUMBER

VGS(OFF) V(BR)GSS
MAX
MIN
(V)
(V)

Qfs
MIN
(mS)

loss
MAX
(mA)

J210

-3

-25

4

15

J211

-4.5

-25

6

20

J212

-6

-25

7

40

For additional design information please see
performance curves NZF, which are located in
Section 7.

BOTTOM VIEW

TO-92

SIMILAR PRODUCTS
•
•

Duals, See 2N5911 Series
Chips, Order J21XCHP

1 DRAIN

2 SOURCE
3 GATE

ABSOLUTE MAXIMUM RATINGS (T A = 25 DC unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

VGD

-25

Gate-Source Voltage

VGS

-25

Gate Current

IG

10

mA

Power Dissipation

PD

360

mW

3.27

mW/oC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 135

Tstg

-55 to 150

h

300

°C

4-81

J210 SERIES

ICrSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
J210

J211

J212

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

IG=-1JJ.A.Vos=OV

-35

-25

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 15V.lo = 1 nA

-1

-3

-2.5

-4.5

-4

-6

Saturation Drain
Current 3

loss

VOS = 15 V. V GS = 0 V

2

15

7

20

15

40

mA

Gate Reverse Current

IGSS

VGS = -15 V
VOS = 0 V

-100

pA

PARAMETER

MAX

MIN

MAX

MIN

MAX UNIT

STATIC

Gate Operating
Current

-25

-25
V

-100

-1
IT A =125°C

-100

-0.5

IG

VOG = 10 V. 10 = 1 mA

-1

Drain Cutoff Current

10(OFF)

VOS = 10 V. VGS = -8 V

1

Gate-Source
Forward Voltage

VGS(F)

IG=lmA.Vos=OV

0.7

nA

pA

V

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Common-Source
Input Capacitance
Common-Source

~~~er~'~a~~ansfer

Equivalent Input
Noise Voltage

g,s
gas
Clss

c,.••

en

12
150

Vos = 15 V. VGS = 0 V
f = 1 MHz

6

12
200

7

12

mS

200

JJ.S

4
pF
1.5

Vos = 15 V. VGS = 0 V
f = 1 kHz

NOTES: 1. T A = 25 °C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW=300JJ.s. duty cycle S3%.

4-82

4

Vos = 15 V. VGS = 0 V
f = 1 kHz

5

~
"HZ

~SilicDnix

~ incorporated

J230 SERIES
N-Channel JFETs

The J230 Series of popular, low-cost JFETs offers
high performance in a wide range of applications. It
features low leakage, noise and cutoff voltage for
use with low level power supplies.
Its TO-92
package offers both value and compatibility with
automated assembly.

PART
NUMBER

For further design information please consult the
typical performance curves NPA which are located
in Section 7.

II

gfs

loss

MIN
(mS)

MAX
(mA)
3

J230

-3

-40

1

J231

-5

-40

1.5

6

J232

-6

-40

2.5

10

TO-92

SIMILAR PRODUCTS
•
a

VGS(OFF) V(BR)GSS
MIN
MAX
(V)
(V)

BOTTOM VIEW

TO-18, See 2N4338 Series
SOT-23, See SST201 Series
Chips, Order J23XCHP
1 DRAIN
2 SOURCE
3 GATE

ABSOLUTE MAXIMUM RATINGS (T A = 25 DC unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

VGO

-40

Gate-Source Voltage

VGS

-40

Gate Current

IG

50

mA

Power Dissipation

Po

360

mW

3.27

mW/oC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 135

T stg

-55 to 150

TL

300

°C

4-83

J230 SERIES

fCrSi6conix

~ incorporatec

ELECTRICAL CHARACTERISTICS 1

LIMITS
J230

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR) ass

la=-ljl.A,Vos=OV

-57

-40

Gate-Source
Cutoff Voltage

Vas (OFF)

Vos = 20 V,

PARAMETER

J231

MAX

MIN

J232

MAX

MIN

MAX UNIT

STATIC
-40
V
10

= 1 jl.A

-0.5

-3

-1.5

-5

-3

-6

0.7

3

2

6

5

10

rnA

-250

pA

Saturation Drain
Current 3

loss

Vos = 20 V, Vas = 0 V

Gate Reverse Current

lass

Vas = -30 V
Vos = 0 V

Gate Operating
Current

-40

la

Voa = 10 V,

10

-2
ITA =125°C

-1

= 0.5 rnA

-1

-250

-250

nA

pA
Drain Cutoff Current

10(oFF)

Vos = 15 V, Vas = -10 V

2

Gate-Source
Forward Voltage

Vas (F)

la = 1 rnA, Vos = 0 V

0.7

gf.

Vos = 20 V, Vas = 0 V
f = 1 kHz

V

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Caoacltance
Equivalent Input
Noise Voltage

Cis.

Vos = 20 V, Vas = 0 V
f = 1 MHz

Cr••

en

3.5

1.5

4

2.5

5

mS

4.5
pF
1.3

Vos = 10 V, Vas = 0 V
f = 10 Hz

NOTES: 1. T A = 25 °c unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300jl.s, duty cycle S3%.

4-84

1

14

30

30

30

~
VHZ

~Siliconix

~ incorporatec

J270 SERIES
P-Channel JFET

The J270 Series is an all-purpose amplifier for
designs requiring p-channel operation.
These
devices feature high gain. low noise and tight

PART
NUMBER

VGS(OFF) limits for simple circuit design. They are
available in low-cost TO-92 packages and are fully
compatible with automatic insertion techniques.
(See Section 8 for details.)

MIN
(mS)

loss
MAX
(mA)

9fs

J270

2.0

30

6

-15

J271

4.5

30

8

-50

For further design information please consult the
typical performance curves PSCIA which are
located in Section 7.

TO-92

SIMILAR PRODUCTS
•
•

VGS(OFF) V(BR)GSS
MIN
MAX
(V)
(V)

BOTTOM VIEW

1 DRAIN
2 GATE
3 SOURCE

SOT-23. See SST270 Series
Chips. Order J27XCHP

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS
Gate-Drain Voltage

SYMBOL

LIMIT

VGO

30

UNITS

V
Gate-Source Voltage

Vas

30

Gate Current

IG

-50

mA

Power Dissipation

Po

360

mW

3.27

mW/oC

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 135

T stg

-55 to 150

TL

300

°C

4-85

•

g

J270 SERIES
ELECTRICAL CHARACTERISTICS 1

Siliconix

incorporated

LIMITS
J270

TYp2

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)GSS

I G = 1 .I1A, Vos = 0 V

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = -15 V, 10 =-1 nA

0.5

2.0

1.5

4.5

Vos = -15 V, VGS = 0 V

-2

-15

-6

-50

mA

200

pA

PARAMETER

MIN

J271

MAX

MIN

MAX

UNIT

STATIC
30

30
V

Saturation Drain
Current 3

loss

Gate Reverse Current

IGSS

Gate Operating
Current

45

VGS = 20 V
Vos = 0 V

10

I

TA =125°C

200

5

IG

VOG = -15 V, 10 = -1 mA

10

Drain Cutoff Current

10(oFF)

Vos = -15 V, VGS = 10 V

-10

Gate-Source
Forward Voltage

VGS(F)

IG = -1 mA, Vos = 0 V

-0.7

nA

pA

V

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Common-Source
Input Capacitance
Common-Source

~~~~g,fa~~~nsfer

Equivalent Input
Noise Voltage

g,s
gos
C iss
Crss

en

VOS = -15 V, VGS = 0 V
f = 1 MHz
VOS = -10 V. VGS = 0 V
f = 1 kHz

NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300,l1S , duty cycle :53%.

4-86

6

Vos = -15 V, VGS = 0 V
f = 1 kHz

15
200

8

18

mS

500

.I1S

20
pF
4
20

%
"Hz

J304 SERIES

tcrSiliconix

~ incorporated

N-Channel JFETs

The J304 Series of n-channel JFETs is designed to
provide high-performance amplification. especially
at high-frequency. These parts feature low noise.
high gain and provide wide bandwidth.

PART
NUMBER

For additional design information please see
performance curves NH. which are located in
Section 7.

VGS(OFF) V(BR)GSS
MIN
MAX
(V)
(V)

MIN
(mS)

loss
MAX
(mA)

9fs

J304

-6

-30

4.5

15

J305

-3

-30

3

8

SIMILAR PRODUCTS
•
•
•

TO-92

SOT-23. See SST5484 Series
TO-72. See PN4416 Series
Chips. Order J30XCHP

BOTTOM VIEW

1 DRAIN
2 SOURCE
3 GATE

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS
Gate-Drain Voltage

SYMBOL

LIMIT

VGD

-30

UNITS

V
Gate-Source Voltage

VGS

-30

Gate Current

IG

10

mA

Power Dissipation

PD

360

mW

3.27

mW/OC

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 135

Tstg

-55 to 150

TL

300

°C

4-87

-

J304 SERIES

~SilicDnix

~ incorporated
LIMITS

ELECTRICAL CHARACTERISTICS 1
J304

TYp2

MIN

J305

MAX

MIN

MAX

UNIT

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)GSS

I G =-1jJ.A,Vos =OV

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 15 V, 10 = 1 nA

-2

-6

-0.5

-3

Saturation Drain
Current 3

loss

Vos = 15 V, V GS = 0 V

5

15

1

8

rnA

Gate Reverse Current

IGSS

V GS = -20 V
VOS = 0 V

-100

pA

PARAMETER

STATIC

Gate Operating
Current

-35

-30
V

-2

I TA=100·C

-100

-0.2

IG

VOG = 10 V, 10 = 1 rnA

-20

Drain Cutoff Current

10(OFF)

Vos = 10 V, V GS = -6 V

2

Drain-Source
On-Resistance

rOS(ON)

Gate-Source
Forward Voltage

-30

nA

pA

VGS(t)

V GS = 1

V. 10 = 1 rnA

IG=lmA,Vos=OV

200

.n

0.7

V

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance

gts
gos

Common-Source
Input Capacitance

C 1SS

Common-Source
Reverse Transfer
Caoacltance

Crss

Common-Source
Output Capacitance

Coss

Equivalent Input
Noise Voltage

en

4.5

Vos = 15 V, V GS = 0 V
f = 1 kHz

50

SYMBOL

mS
50

jJ.S

2.2
Vos = 15 V, V GS = 0 V
f = 1 MHz

0.7

pF

1
Vos = 10 V, V GS = 0 V
f=100Hz

"X,
VHZ

10
LIMITS (Typical)

ELECTRICAL CHARACTERISTICS 1
PARAMETER

3

7.5

TEST CONDITIONS

J304
J305
I
I
100 MHz 400 MHz 100 MHz 400 MHzl UNIT

HIGH-FREQUENCY
Common-Source
Input Conductance

g Iss

80

800

80

J.LS

Common-Source
Input Susceptance

b,ss

2

7.5

2

mS

Common-Source
Output Conductance

gOS5

60

80

60

J.LS

Common-Source
Output Susceptance

boss

0.8

3.6

0.8

Common-Source Forward
Transconductance

gts

4.2

3

Common-Source
Power Gain

G ps

Vos = 15 V, 10 = 5 rnA

20

11

NF

Vos = 15 V, 10 = 5 rnA
RG = 1 k.Cl.

1.7

3.8

VOS = 15 V, V GS = 0 V

mS

Noise Figure
NOTES:

4-88

1. T A = 25·C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 jJ.S , duty cycle :S 2 %.

dB

.-:rSiliconix

~ incorporated

J308 SERIES
N-Channel JFETs

The J308 Series is a popular. low-cost device which
offers superb amplification characteristics.
It
features high-gain. low noise (typically < 6 nVVHz)
and low gate leakage (typically < 2 pA). Of special
interest. however. is performance at high
frequency. Even at 450 MHz the J308 Series offers
high power gain and low noise. Like all TO-92
packages offered by Siliconix. tape and reel options
are available to support automated assembly.
(See Section 8.)

PART
NUMBER

For additional design information and a closer look
at high-frequency characteristics. please consult
performance curves NZB which are located in
Section 7.

9fs

MIN
(mS)

loss
MAX
(mA)

J308

-6.5

-25

8

60

J309

-4.0

-25

10

30

J310

-6.5

-25

8

60

BOTTOM VIEW

TO-92

1 DRAIN
2 SOURCE
3 GATE

SIMILAR PRODUCTS
•
•
•
•

VGS(OFF) V(BR)GSS
MAX
MIN
(V)
(V)

TO-52. See U308 Series
SOT-23. See SST308 Series
Dual. See U430 Series
Chips. Order J30XCHP

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise

noted)

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

Vao

-25

Gate-Source Voltage

Vas

-25

Gate Current

la

10

mA

Power Dissipation

Po

360

mW

3.27

mW/oC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 135

T stg

-55 to 150

lL

300

°C

4-89

J308 SERIES

.:r-Siliconix
..z::.
incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
J308

J309

J310

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

I G = -1 ,lJ.A, VOS = 0 V

-35

-25

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 10 V, 10 = 1 nA

-1

-6.5

-1

-4

-2

-6.5

Saturation Drain
Current 3

loss

VOS = 10 V, VGS = 0 V

12

60

12

30

24

60

Gate Reverse Current

IGSS

VGS = -15 V
VOS = 0 V

PARAMETER

MAX

MIN

MAX

MIN

MAX UNIT

STATIC
-25

-25
V

T A =125°C

mA

-0.002

-1

-1

-1

nA

-0.008

-1

-1

-1

JJ.A

Gate Operating
Current

IG

V oG =9V,l o =10mA

-15

pA

Drain-Source
On-Resistance

rOS(ON)

VGs=OV,lo =1 mA

35

.n.

VGS(F)

I G = 1 mA, Vos = 0 V

0.7

Vos = 10 V, 10 = 10 mA
f = 1 kHz

14

Gate-Source
Forward Voltage

1

1

1

V

DYNAMIC
Common-Source
Forward
Transconductance

gls

Common-Source
Output Conductance

gos

Common-Source
Input Capacitance

C lss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

en

VGS = -10 V, VOS = 10 V
f = 1 MHz
VOS = 10 V, 10 = 10 mA
f=100Hz

8

10

8

mS

110

250

250

250

4

5

5

5

1.9

2.5

2.5

2.5

,IJ.S

pF

6

~
"Hz'

HIGH FREQUENCY
Common-Gate Foward
Transconductance
Common-Gate Output
Conductance
Common-Gate Power
Galn4
Noise Figure

NOTES:

4-90

1.
2.
3.
4.

f = 105 MHz

gIg

gog

G pg

NF

Vos = 10 V
10 = 10 mA

15

f = 450 MHz

13

f = 105 MHz

0.16

f = 450 MHz

0.55

f = 105 MHz

16

f = 450 MHz

11.5

f = 105 MHz

1.5

f = 450 MHz

2.7

T A = 25 ° C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 300,IJ.s, duty cycle "3%.
Gain (Gpgl measured at optimum Input noise match.

mS

dB

J500 SERIES

..:r-Siliconix

~ incorporated

Current Regulator Diodes

The J500 Series is a family of current regulators
designed for demanding applications in test
equipment and instrumentation.
These devices
utilize the JFET techniques to produce a single
two-leaded device which is extremely simple to
operate. With nominal current ranges from 0.24
mA to 4.7 mA, the J500 Series will meet a wide
array of design requirements. In addition to its
two-lead construction, this series features 20%
current ranges, improved current control over wide
temperature ranges,
and simple "floating"
operation as no power supplies are required for
biasing. Several of the devices provide effective
current control operating down to even 1 volt.
Finally, its low-cost TO-92 package ensures a cost
effective design solution.

PART
J500
J501
J502
J503
J504
J505

IF
(mA)

PART

0.24
0.33
0.43
0.56
0.75
1.00

J506
J507
J50B
J509
J510
J511

TO-92

For additional design information please see
performance curves NCL, which are located in
Section 7.

IF
(mA)
1.40
LBO
2.40
3.00
3.60
4.70

BOTTOM VIEW

1 ANODE
2 CATHODE

SIMILAR PRODUCTS
•
•

TO-1B, See CR022 Series
Chips, Order J5XXCHP

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

= 25 DC unless otherwise noted)
SYMBOL

LIMIT

UNITS

Pov

50

V

Forward Current

IF

20

Reverse Current

IR

50

Power Dissipation

PD

360

mW

3.27

mW/oC

Peak Operating Voltage

mA

Power Derating
Operating Junction Temperature

TJ

-55 to 150

T stg

-55 to 200

DC
Storage Temperature

4-91

..

c..

t-

(0
I\)

CJ'1

ELECTRICAL CHARACTERISTICS (T A = 25 °C unless otherwise noted)
SYMBOL

IF

Zd

Z.

VL

PARAMETER

REGULATOR
CURRENT

DYNAMIC
IMPEDANCE

KNEE
IMPEDANCE

LIMITING
VOLTAGE

TEST
CONDITIONS

VF =25 V
(Note 1)

VF =25 V
(Note 2)

V F =6 V

mA

Mil

Mil

UNITS
NOM
J500
J501
J502
J503
J504
J505
J506
J507
J508
J509
J510
J511

NOTES: 1
2.
3.
4.

0.24
0.33
0.43
0.56
0.75
1.00
1.40
1.80
2.40
3.00
3.60
4.70

MIN
0.192
0.264
0.344
0.448
0.600
0800
1.120
1.440
1.900
2.400
2.900
3.800

MAX
0.288
0396
0.516
0.672
0.900
1.200
1.680
2.160
2.900
3.600
4.300
5.600

MIN
4.00
2.20
1.50
1.20
0.80
0.50
0.33
0.20
0.20
0.15
0.15
0.12

TYP
400
25 0
15.0
12.0
70
5.0
30
20
1 5
1.0
0.8
06

IF

=0.8 I FCMINI
(Note 3)

POV

CF

6,

PEAK
OPERATING
VOLTAGE

CAPACITANCE

TEMPERATURE
COEFFICIENT
(TYPICALS)

VF =25 V
f =1 MHz

VF =25 V
O·CS TAS 100·C

pF

ppm/·C

TYP

TYP

2.2
2.2
2.2
22
2.2
2.2
2.2
2.2
22
2.2
22

1300
600
0
-400
-1000
-1300
-1900
-2200
-2600
-2800
-3000
-3000

IF

=1.1

I FCMAXI
(Note 4)

V

TYP

MAX

2.50
1.60
1.10
0.80
055
0.40
0.25
0.19
0.13
0.09
0.07
0.05

1.20
1.30
1.50
1.70
1.90
2.10
2.50
2.80
3.10
3.50
3.90
4.20

V
TYP
0.4
0.5
0.6
0.7
0.8
0.9
1.1
1.3
15
1.7
1.9
2.1

MIN
50
50
50
50
50
50
50
50
50
50
50
50

TYP
100
100
100
100
100
100
100
100
100
100
100
100

22

o
o

en

m

:IJ

m
en

Pulse test - steady state currents may very.
Pulse test - steady state Impedances may vary.
Min VF required to ,nsure IF> 0.8 IFCMINI'
MaxV F where IF> 1.1 I FCMAXl's guaranteed

~

:i'rn
[l_.

0=

.:a 0

cO

~~.

1:1.)(

J552

.-rSiliconix

~ incorpora.ted

Current Regulator Diode

The J552 is a current regulator designed for
applications in test equipment and instrumentation.
With forward current between 0.2 and 0.7 mA, the
J552 will meet a wide array of design requirements.
In addition to its two-lead construction, it features
current control over wide temperature ranges and
simple "floating" operation as no power supplies
are required for biasing. Finally, the low-cost TO-92
package ensures a cost effective design solution.
For additional design information please see
performance curves NKL, which are located in
Section 7.

PART

IF
(mA)

J552

0.77

TO-92

BOTTOM VIEW

SIMILAR PRODUCTS
1 ANODE
2 CATHODE
•
•

TO-1B, See CR022 Series
Chips, Order J5XXCHP

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise

noted)

SYMBOL

LIMIT

UNITS

Pav

100

V

Forward Current

IF

20

Reverse Current

IR

50

Power Dissipation

PD

350

mW

3.27

mW/oC

Peak Operating Voltage

mA

Power Derating
Operating Junction Temperature

TJ

-55 to 135

Storage Temperature

T stg

-55 to 135

Lead Temperature
(1/16" from case for 10 seconds)

lL

300

°C

4-93

..

J552

.....Siliconix

~ incorporatec

ELECTRICAL CHARACTERISTICS 1

LIMITS
J552

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

MAX

UNIT

STATIC

Forward Current 3

Peak Operating Voltage 3, 4

VF=100V

400

VF = 25 V

400

250

VF = 1 V

390

200

Pov

IF = 100 V IF1(MAX)

160

100

VL

IF = 0.9 IF1(MIN)

1

IF1

770
700

p..A

V
Limiting Voltage 5

1.5

DYNAMIC
Smail-Signal Dynamic
Impedance 3

ZF1

VF = 25 V, f = 1 kHz

6

Anode-Cathode
Capacitance

CF

V F = 25 V, f = 1 MHz

2

NOTES: 1.
2.
3.
4.
5.

4-94

T A = 25·C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW =300jJ.s, duty cycle :S3%.
Maximum V F < 1.1 I F1 (MAX) Is guaranteed.
Maximum VF required to Insure IF> 0.9IF1(MIN)'

1

M.o.
pF

J553 SERIES

~Siliconix

~ incorporated

Current Regulator Diodes

The J553 Series is a low cost family of current
regulators designed for demanding applications in
test equipment and instrumentation.
These
devices utilize the proven JFET techniques to
produce a single two-leaded device which is
extremely simple to operate. With nominal current
ranges from 0.5 mA to 4.5 mA, the J553 Series will
meet a wide array of design requirements.
In
addition to its two-lead construction, this series
feature improved current control over wide
temperature
ranges
and
simple
"floating"
operation as no power supplies are required for
biasing. Several of the devices provide effective
current control operating down to even 2 volts.
Finally, its low-cost TO-92 package ensures a cost
effective design solution.

IF
(mA)

PART
J553
J554
J555
J556
J557

0.50
1.00
2.00
3.00
4.50

BOTTOM VIEW

TO-92

For additional design information please see
performance curves NCL, which are located in
Section 7.

1 ANODE
2 CATHODE

SIMILAR PRODUCTS
•
•

TO-18, See CR022 Series
Chips, Order J5XXCHP

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Pov

50

V

Forward Current

IF

20

Reverse Current

IR

50

Power Dissipation

Po

360

mW

3.27

mW/DC

Peak Operating Voltage

mA

Power Derating
Operating Junction Temperature

TJ

-55 to 150

T stg

-55 to 200

DC
Storage Temperature

4-95

-

f'

COl

CD

(j)

ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)
Zd

IF

SYMBOL

VL

POV

KNEE
IMPEDANCE

LIMITING
VOLTAGE

PEAK
OPERATING
VOLTAGE

IF = 0.8 I F(MIN)
(Note 3)

IF = 1.1I F(MAX)
(Note 4)

Zk

PARAMETER

REGULATOR
CURRENT

DYNAMIC
IMPEDANCE

TEST
CONDITIONS

V F = 25 V
(Note 1)

V F = 25 V
(Note 2)

VF = 5 V

9,

CAPACITANCE

TEMPERATURE
COEFFICIENT
(TYPICALS)

V F = 25 V

VF = 25 V

f = 1 MHz

QOC:S:T A S100°C

MJ1

MJ1

pF

ppm/oC

NOM

MIN

MAX

TYP

TYP

MAX

TYP

MIN

TYP

TYP

TYP

0.50
1.00
2.00
3.00
4.50

0.180
0.600
1.400
2.400
3.600

0.750
1.500
2.600
3800
5.300

13.0
5.0
1.8
1.0
0.5

1.00
0.40
0.17
009
0.06

1.30
1.75
2.15
2.60
3.00

07
09
1.4
1.7
2.1

50
50
50
50
50

100
100
100
100
100

2.2
2.2
2.2
2.2

-200
-1300
-2300
-2800
-3100

mA

V

CF

V

UNITS

J553
J554
J555
J556
J557

----

NOTES: 1.
2.
3.
4.

2.2

01
eN

en

m

:IJ

m

en

--

Pulse test - steady state currents may very.
Pulse test - steady state impedances may vary.
Min VF required to insure IF> 0.8 IF(MIN)'
MaxVF where IF> 1.1 I F(MAX) is guaranteed.

~

0_,

o=:

-dO

CO
~:J

[X'

JPAD5 SERIES

.rSiliconix

~ incorporated

Low-Leakage Pico-Amp Diodes

The JPAD5 Series of low-leakage diodes provides a
superior
alternative
to
conventional
diode
technology when reverse current (leakage) must
be minimized.
These devices feature leakage
currents ranging from -5 pA (JPAD5) to -500 pA
(JPAD500) to support varying system requirements.
Its TO-92 package allows designers to
maximize circuit performance while maintaining the
objectives of low cost and compact packaging.
Tape and reel is available for use with automated
assembly techniques. (See Section B.)

IR
(pA)

PART NO.
JPAD5

-5

JPAD10

-10

JPAD20

-20

JPAD50

-50

JPAD100

-100

JPAD200

-200

JPAD500

-500

TO-92

~g

SIMILAR PRODUCTS
•
•
•
•

1 CATHODE
2 ANODE

SOT-23. See SSTPAD5 Series
TO-lB. See PADl Series
Duals. See DPADl Series
Chips. Order JPADXXCHP

ABSOLUTe MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

BOTTOM VIEW

..
= 25 DC unless otherwise noted)
SYMBOL

LIMIT

UNITS

Forward Current

IF

10

mA

Total Device Dissipation

Po

360

mW

T 9 tg

-55 to 135

h

300

Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

°C

4-97

JPAD5 SERIES

.:r-Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

MAX

UNIT

STATIC
JPAD5
JPAD10
JPAD20
Reverse Current

Reverse Breakdown Voltage

IR

VR= -20 V

-1
-2

-5
-10
-20

-2

JPAD50

-5

-50

JPAD100

-5

-100

JPAD200

-20

-200

JPAD500

-20

pA

-500

BVR

IR=-l)lA

-60

VF

IF = 5 rnA

0.8

1.5

CR

VR = -5 V, f = 1 MHz

1.5

2

-35
V

Forward Voltage Drop

OYNAMIC
Reverse Capacitance
NOTES:

4-98

1. T A = 25·C unless otherwise noted.
2. For design aid only, not subject to production testing.

pF

JR135V SERIES

.:Y"Siliconix

~ incorporated

High-Voltage Current Limiting Diodes

The JR135V Series of high-voltage diodes utilizes a
MOS process to provide active current limiting over
a voltage range from 1 V up to 240 V. These
devices feature two-terminal construction and
require no additional circuitry or power supplies.
Additionally, it is housed in a low-cost TO-92
package and is available with tape and reel to
support automated assembly.
For additional design information please see
performance curves VRMA, which are located in
Section 7.

PART NO.

Pav
(V)

JR135V

135

JR170V

170

JR200V

200

JR220V

220

JR240V

240
BOTTOM VIEW

TO-92

~~

~1 ANODE ~
2 CATHODE

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

Peak Anode-Cathode Voltage

= 25°C unless otherwise noted)
SYMBOL

LIMIT

JR135V

135

JR170V

170

JR200V

Pav

200

JR220V

220

JR240V

240

UNITS

V

Reverse Current

IR

50

mA

Power Dissipation

PD

360

mW

3.27

mW/oC

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 135

T stg

-55 to 150

h

300

°C

4-99

~SilicDnix

JR135V SERIES

~ incorporated

ELECTRICAL CHARACTERISTICS 1
LIMITS
PARAMETER

SYMBOL

TYp2

MIN

JR135V

165

135

JR170V

190

170

JR200V

215

200

JR220V

230

220

TEST CONDITIONS

MAX

UNIT

STATIC

Peak Operating Voltage

Pov

IF = 1 mA

V

260

240

VF = 2 V

440

200

VF=100V

450

200

VL

I F =0.8I F @2Vmln

0.7

Dynamic Impedance

Zo

VF = 25 V

2

M.D.

Temperature Coefficient

AIF
AT

VF = 2 to 100 V
T A = -20 to 85· C

0.6

%,·C

JR240V
Forward Current

IF

Limiting Voltage

770
0.9

J.lA
V

DYNAMIC

NOTES: 1. T A = 25·C unless otherwise noted.
2. For design aid only. not subject to production testing.

4-100

M440 SERIES

~Siliconix

~ incorporated

N-Channel JFET Pairs

The M440 Series are monolithic pairs of JFETs
mounted in a single TO-71 package. The M440
features high speed amplification (slew rate), high
gain (typically > 6 mS), and low gate leakage
(typically < 1 pA). This performance makes these
devices perfect for use as wide band differential
amplifiers in demanding test and measurement
applications. Finally, its TO-71 hermetically sealed
package is available with military screening per
MIL-S-19500. (See Section 1.)

PART
NUMBER

V(BR)OSS 9fs
MIN
MIN
(V)
(mS)

10 IVos 1 - Vos 2 1
TYP
MAX
(pA)
(mV)

M440

-25

5

-1

10

M441

-25

5

-1

20

BOTTOM VIEW

TO-71
For additional design information please see
performance curves NNZ, which are located in
Section 7.

1
2
3
4
5
6

SIMILAR PRODUCTS
•
•
•
•
•

TO-78, See U443 Series
SO-8, See SST440 Series
Low Noise, See U401 Series
Low Leakage, See U421 Series
Chips, Order M44XCHP

SOURCE 1
DRAIN 1
GATE 1
SOURCE 2
DRAIN 2
GATE 2

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

VOD

-25

Gate-Source Voltage

Vos

-25

Forward Gate Current

10

50

UNITS

V

Power Dissipation
Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

Per Side
Total
Per Side
Total

PD

325
650
2.2
3.3

TJ

-55 to 150

Tstg

-65 to 200

h

300

mA
mW

mW/oC

°C

4-101

..

.:F'Siliconix

M440 SERIES

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
M440

M441

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -l.1lA, V DS = 0 V

-35

-25

Gate-Source
Cutoff Voltage

VGS(OFF)

V DS = 10 V, ID = 1 nA

-3.5

-1

-6

-1

-6

Saturation Drain
Current 3

IDSS

V DS = 10 V, VGS = 0 V

15

6

30

6

30

rnA

Gate Reverse
Current

IGSS

-500

-500

pA

-500

-500

pA

PARAMETER

MAX

MIN

MAX

UNIT

STATIC
-25
V

Gate Operating
Current

IG

Gate-Source
Forward Voltage

VGS(F)

VGS = -15 V
V DS = 0 V
V DG = 10 V
ID = 5 rnA

-1

I TA =125°C

-0.2

nA

-1

I TA =125°C

-0.2

nA

IG = 1 rnA, V DS = 0 V

0.7

V

V DG = 10 V, ID = 5 rnA
f = 1 kHz

6

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance

gls
gos

20

Common-Source
Input Capacitance

C ISS

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

en

V DG =10V,ID=5mA
f = 10 kHz

4

Differential
Gate-Source Voltage

I VGS1-VGS21

V DG = 10 V, ID = 5 rnA

7

Gate-Source Voltage
Differential Change
with Temperature

I!.IVGS1-VGS21
I!.T

V DG = 10 V, ID = 5 rnA
f = 1 MHz

4.5

9
200

4.5

9

mS

200

j!.S

3.5
pF
1

%
-1HZ

MATCHING

V DG = 10 V
ID = 5 rnA

I

T = -55 to 25°C

I T = 25 to 125°C

10
10

Saturation
Drain Current Ratio

IDSS1
IDSS2

V DS = 10 V, VGS = 0 V

0.98

Transconductance
Ratio

glsl
gls2

V DG = 10 V, I D = 5 rnA
f = 1 kHz

0.98

CMRR

V DD = 5to 10 \/'ID= 5 rnA

90

Common Mode
Rejection Ratio
NOTES:

4-102

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300.lls, duty cycle S3%.

10

20

mV

~°c

dB

M5911 SERIES

.:rSiliconix

~ incorporated

N-Channel JFET Pairs

The M5911 Series are monolithic pairs of JFETs
mounted in a single TO-78 package. The M5911
features high speed amplification (slew rate), high
gain (typically > 6 mS), and low gate leakage
(typically < 1 pA). This performance makes these
devices perfect for use as wideband differential
amplifiers in demanding test and measurement
applications. Finally, its TO-78 hermetically sealed
package is available with military screening per
MIL-S-19500. (See Section 1.)

PART
NUMBER

V(BR)GSS 9fs
MIN
MIN
(V)
(mS)

IG IVGS1- VGS21
MAX
MAX
(pA)
(mV)

M5911

-25

5

-100

10

M5912

-25

5

-100

15

For additional design information please see
performance curves NNZ, which are located in
Section 7.

BOTTOM VIEW

TO-7B

SIMILAR PRODUCTS
•
•
•
•
•

SO-8, See SST5912
Two-Chip, See 2N5911 Series
Low Noise, See U401 Series
Low Leakage, See U421 Series
Chips, Order M591XCHP

1
2
3
4
5
6
7

SOURCE 1
DRAIN 1
GATE 1
CASE
SOURCE 2
DRAIN 2
GATE 2

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

VGD

-25

Gate-Source Voltage

VGS

-25

UNITS

V

IG

Forward Gate Current
Power Dissipation
Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

Per Side
Total
Per Side
Total

PD

50
367
500
3
4

TJ

-55 to 150

Tstg

-65 to 200

TL

300

mA
mW
mW/oC

°C

4-103

-

.r-Siliconix

M5911 SERIES

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
M5911

M5912

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -lP.A, V DS = 0 V

-35

-25

Gate-Source
Cutoll Voltage

VGS(OFF)

V DS =10V,I D =lnA

-3.5

-1

-5

-1

-5

15

7

40

7

40

rnA

PARAMETER

MAX

MIN

MAX

UNIT

STATIC

V

Saturation Drain
Current

IDSS

Gate Reverse
Current

IGSS

Gate Operating
Current
Gate-Source Voltage

-25

IG

V DS = 10 V, VGS = 0 V
VGS = -15 V
V DS = 0 V
V DG =10V
ID = 5 rnA

-1

-100

-100

pA

IT

A

=150°C

-2

-250

-250

nA

-1

-100

-100

pA

IT

A

=125°C

-0.3

-100

-100

nA

-4

-4

VGS

V DG = 10 V, ID = 5 rnA

-1.5

VGS(F)

IG = 1 rnA, V DS = 0 V

0.7

V DG = 10 V, ID = 5 rnA
1= 1 kHz

6

-0.3

-0.3

V
Gate-Source
Forward Voltage

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Common-Source

Forward
Transconductance
Common-Source
Output Conductance

gls
gos
gls

5

6

5

100

20
V DG = 10 V, I D = 5 rnA

10

5

10

5

10

mS

100

P.S

10

mS
P.S

1= 100 MHz

gos

30

150

150

3.5

5

5

1

1.2

1.2

Common-Source
Input Capacitance

C iss

Common-Source
Reverse Transler
Capacitance

Crss

Equivalent Input
Noise Voltage

en

V DG = 10 V, I D = 5 rnA
1= 10 kHz

4

20

20

%

NF

V DG = 10 V, I D = 5 rnA
I = 10kHz, R G = 100 k.n.

0.1

1

1

dB

Differential
Gate-Source Voltage

I VGS1-VGS21

V DG = 10 V, ID = 5 rnA

7

10

15

mV

Gate-Source Voltage
Differential Change
with Temperature

'" I VGS1-VGS2 I

V DG = 10 V

10

20

40

6T

ID = 5 rnA

10

20

40

~°C

Noise Figure

V DG = 10 V, I D = 5 rnA
1=1 MHz

pF

~

MATCHING

I T = -55 to 25°C

I T = 25 to 125°C

Saturation
Drain Current Ratio

IDSS1
IDSS2

V DS = 10 V, VGS = 0 V

0.98

0.95

1

0.95

1

Transconductance
Ratio

glsl
gls2

V DG = 10 V, ID = 5 rnA
1=1 kHz

0.98

0.95

1

0.95

1

II G1- I G21

V DG = 10 V, ID = 5 rnA
T A = 125°C

0.005

CMRR

V DD = 5 to 10 V, ID = 5 rnA

90

Differential
Gate Current
Common Mode
Rejection Ratio
NOTES:

4-104

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300p.s, duty cycle ;!;3%.

20

20

nA
dB

tcrSiliconix

~ incorporated

P1086 SERIES
P-Channel JFETs

The P1086 Series of low-cost p-channel analog
switches is designed to provide low on-resistance
and fast switching. It also works well in conjunction
with Siliconix' J111 Series for complementary
switching applications. The P1086 Series features a
TO-92 package which is available with various
(See
lead-forms and/or tape and reel options.
Section 8.)

rds(ON) IO(OFF)
MAX
TYP
(a)
(pA)

tON
TYP
(ns)

PART
NUMBER

VOS(OFF)
MAX
(V)

P10B6

10

75

-10

25

P10B7

5

150

-10

25

For further design information please consult the
typical performance curves PSCIA which are
located in Section 7.
BOTTOM VIEW

TO-92

SIMILAR PRODUCTS
•
CI

•

TO-1B. See 2N5114 Series
SOT-23. See SST174 Series
Chips. Order P10BXCHP

ABSOLUTE MAXIMUM RATINGS (T A

1 SOURCE
2 DRAIN
3 GATE

= 25°C unless otherwise noted)
SYMBOL

LIMIT

Gate-Drain Voltage

Voo

30

Gate-Source Voltage

VGS

30

Gate Current

IG

-50

mA

Power Dissipation

Po

360

mW

3.27

mW/oC

PARAMETERS/TEST CONDITIONS

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 135

T stg

-55 to 150

TL

300

°C

4-105

~Siliconix
incorporatec

P1086 SERIES

~

ELECTRICAL CHARACTERISTICS 1

LIMITS
Pl0S6

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)aSS

I a = l)1A, V DS = 0 V

45

30

Gate-Source
Cutoff Voltage

Vas (OFF)

PARAMETER

Pl0S7

MAX

MIN

MAX

UNIT

STATIC

V

Saturation Drain
Current 3

IDSS

Gate Reverse Current

lass

Gate Operating
Current

Drain Cutoff Current

30
10

V DS = -15 V, ID = -1J.IA
-10

V DS = -20 V, Vas = 0 V
Vas = 15 V
VDS = 0 V

la

0.01

I

TA = 85°C

5
-5

rnA

2

2

0.6

VDa=-15V,I D =-1 rnA

0.01

VDS = -15 V, Vas = 10 V

-0.01

-10

-10

VDS = -15 V, Vas = 10 V
T A = 85°C

-0.001

-0.5

-0.5

J.IA

75

150

.n

nA
ID(OFF)

Drain-Source
On-Resistance

rDS(ON)

la = -1 rnA, Vas = 0 V

Gate-Source
Forward Voltage

Vas (F)

la=-lmA,VDS=OV

-0.7

V

4.5

mS

20

JJ,S

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Drain-Source
On-Resistance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Ca
Equivalent Input
Noise Voltage

gfs
V Ds =-15V,I D =-lmA
f = 1 kHz

gas
rds(ON)

Vas = 0 V, I D = 0 rnA
f = 1 kHz

Cis.

V DS = -15 V, Vas = 0 V
f = 1 MHz

Crss

en

75

150

20

45

45

V DS = 0 V, Vas = 10 V
f - 1 MHz

5

10

10

V DS = -10 V, ID = -1 rnA
f = 1 kHz

20

.n
pF

~
VHz

SWITCHING
Turn-on Time
Turn-off Time

td(ON)
t,
~(OFF)

tf

10

15

15

PIN

V DD

Vas (OFF)

RL

15

20

75

Pl086
Pl087

-6 V
-6 V

12 V
7V

910.n
1800.n

10

15
50

25

Vas (ON) = 0 V

NOTES: 1. T A = 25 ° C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300)1s, duty cycle S3%.

4-106

20

100

ns

.HSiliconix

PAD1 SERIES

incorporated

Low-Leakage Pico-Amp Diodes

The PADl Series of extremely low-leakage diodes
provides a superior alternative to conventional
diode technology when reverse current (leakage)
must be minimized. These devices feature leakage
currents ranging from -1 pA (PAD1) to -100 pA
(PAD100) to support a wide range of applications.
The PADl Series is well suited for use in
applications such as input protection for operational
amplifiers. Its hermetically sealed metal can is
available with full military processing per
MIL-S-19500. (See Section 1.)

IR
(pA)

PART NO.
PADl

-1

PAD2

-2

PAD5

-5

PAD10

-10

PAD20

-20

PAD50

-50

PAD100

-100

SIMILAR PRODUCTS
"
•
•
•

TO-92, See JPAD5 Series
SOT-23, See SSTPAD5 Series
Duals, See DPADl Series
Chips, Order PADXXCHP

TO-1S (MODIFIED)

BOTTOM VIEW

TO-1S

1 CATHODE
2 ANODE

BOTTOM VIEW

-

1 CATHODE
2 ANODE
3 CASE

(PAD10, 20, 50 100)

(PAD1, 2, 5)

ABSOLUTE MAXIMUM RATINGS (T A = 25 DC unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Forward Current

IF

50

mA

Total Device Dissipation

PD

300

mW

Tstg

-55 to 125

TL

300

Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

°C

4-107

PAD1 SERIES

~Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

TYp2

MIN

MAX

UNIT

STATIC

Reverse Current

Reverse Breakdown Voltage

Forward Voltage Drop

IR

BVR

VR

IR

=-20 V

= -1 JJ,A
IF

VF

PADl

-0.3

-1

PAD2
PADS

-0.7
-1

-S

PAD10

-2

-10

PAD20

-2

-20

PADSO

-S

-50

PAD100

-S

-100

PAD1, 2, 5

-60

-45

PAD10, 20
PADSO, 100

-so

-3S

= S rnA

-2
pA

-120
V

0.8

1.5

PAD1, 2, 5

O.S

0.8

PAD10,20
PAD50, 100

1.5

2

DYNAMIC

Reverse Capacitance

=

CR

=
=

VR -S V
f 1 MHz

NOTES: 1. T A 25·C unless otherwise noted.
2. For design aid only, not subject to production testing.

4-108

pF

PN4091 SERIES

~SilicDnix
incorporated

.LII

N-Channel JFET

The PN4091 Series is the plastic equivalent of our
popular 2N4091 Series.
These devices are
especially well suited for analog switching
applications but function effiCiently as high-gain
amplifiers, particularly at high-frequency.
Our
low-cost TO-92 packaging offers affordable
performance with flexibility for designers, as these
devices can be ordered with a variety of lead forms
or tape and reel for automated insertion. (See
Section B.)

PART
NUMBER

rds(ON) iO(OFF)
MAX
MAX
(0)
(pA)

tON
MAX
(ns)

PN4091

-10

30

200

25

PN4092

-7

50

200

35

PN4093

-5

BO

200

60

For additional design information please consult the
typical performance curves NCB which are located
in Section 7.

TO-92

BOTTOM VIEW

1 DRAIN
2 SOURCE
3 GATE

SIMILAR PRODUCTS
•
•
•
•

Vas (OFF)
MAX
(V)

SOT-23, See SST4091 Series
TO-1B, See 2N4091 Series
Duals, See 2N5564 Series
Chips, Order PN409XCHP

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

Vao

-40

Gate-Source Voltage

Vas

-40

Gate Current

la

10

mA

Power Dissipation

Po

360

mW

3.27

mW/DC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 135

Tstg

-55 to 150

TL

300

DC

4-109

..

PN4091 SERIES

.:r-Siliconix

~ incorporated
LIMITS

ELECTRICAL CHARACTERISTICS 1
/~

PARAMETER

TEST CONDITIONS

SYMBOL

PN4091

TYp2

MIN

MAX

PN4092
MIN

MAX

PN4093
MIN

.

STATIC
Gate-Source
Breakdown Voltage

V(BR)GSS

I G =-lJJ.A.Vos =OV

Gate-Source
Cutoff Voltage

VGS(OFF)

VOS = 20 V. 10 = 1 nA

-5

Saturation Drain
Current 3

loss

VOS = 20 V. VGS = 0 V

30

Gate Reverse Current

IGSS

Gate Operating
Current

-55

-40

-40

-40
V

IG

V GS = -15 V
VOS = 0 V

TA =125°C

VOG=15V.10 = 10 mA

Vos = 20 V
Drain Cutoff Current

10(OFF)
Vos = 20 V
TA =125°C

-10

-2

-7

15

VGS = 0 V

VOS(ON)

200

200

200

pA

100

100

100

nA

200

pA

-5
5
5

V GS = -12 V

5

V GS = -6 V

3

V GS = -8 V

3

V GS = -12 V

3

200
200
100
100

VGs=OV.lo = 1 mA

Gate-Source
Forward Voltage

VGS(F)

IG= 1 mAo Vos = OV

nA

100
0.2

0.15

10 = 6.6 mA 0.15
rOS(ON)

mA

-3

V GS = -8 V

Drain-Source
On-Resistance

-5

-5

V GS = -6 V

10 = 4 mA

-1
8

10=2.5mA 0.15
Drain-Source
On-Voltage

MAX UNIT

0.2

V

0.2
30

50

80

.n

0.7

V

6

mS

25

JJ,S

DYNAMIC
Common-Source
Forward
Transconductance

gfs

Common-Source
Output Conductance

gos

Drain-Source
On-Resistance

VOG=20V.10=lmA
f = 1 kHz
VGs=OV.lo=OmA
f = 1 kHz

rds(ON)

30

50

80

Common-Source
Input Capacitance

C lss

VOS = 20 V. VGS = 0 V
f = 1 MHz

13

16

16

16

Common-Source
Reverse Transfer
Capacitance

Crss

Vos = 0 V. V GS = -20 V
f = 1 MHz

3.5

5

5

5

en

VOG=10V.10=lmA
f = 1 kHz

4

Voo = 3 V. VGS(ON) = 0 V

2

15

15

20

2

10

20

40

20

40

60

80

Equivalent Input
Noise Vcltage

.n

pF

%
"Hz

SWITCHING
Turn-on Time

td(ON)
tr

Turn-off Time

tOFF

PIN
PN4091
PN4092
PN4093

10(ON) VGS(OFF) RL
6.6 mA -12 V 425.0.
-8 V 700.0.
4mA
-6 V 1120.n
2.5 mA

NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW =300JJ,S. duty cycle S3%.

4-110

ns

PN4117 SERIES

~Siliconix

~ incorporated

N-Channel JFETs

The PN4117 and PN4117 A Series are n-channel
JFETs designed to provide ultra-high input
impedance. The PN4117 Series features I GSS of
10 pA maximum. The PN4117A is specified with a
1 pA limit and typically operates at 0.2 pA. These
devices, therefore, make perfect choices for use
as sensitive front-end amplifiers in applications
such as microphones, smoke detectors, and
precision test equipment. Additionally, its TO-92
plastic package provides a low-cost device
compatible with today's automated assembly
techniques. (See Section 8.)

PART
NUMBER

gls
MIN
(J.lS)

loss

70

0.09

MAX
(mA)

PN4117

-1.8

-40

PN4118

-3

-40

80

0.24

PN4119

-6

-40

100

0.60

PN4117A

-1.8

-40

70

0.09

PN4118A

-3

-40

80

0.24

PN4119A

-6

-40

100

0.60

For additional design information please consult
performance curves NT which are located in
Section 7.

TO-92

SIMILAR PRODUCTS
o
o
•
o

VGS(OFF) V(BR)GSS
MIN
MAX
(V)
(V)

BOTTOM VIEW

1 DRAIN
2 SOURCE
3 GATE

TO-72 , See 2N4117 Series
SOT-23, See SST4117 Series
Dual, See U421 Series
Chips, Order PN411XCHP

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

VGO

-40

Gate-Source Voltage

VGS

-40

Gate Current

IG

10

mA

Power Dissipation

PD

360

mW

3.27

mW/oC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1116" from case for 10 seconds)

TJ

-55 to 135

T stg

-65 to 150

TL

300

°C

4-111

.HSiliconix

PN4117 SERIES

incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
PN4117

PN4118

PN4119

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -1 J.lA. Vos = 0 V

-70

-40

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 10 V. 10 = 1 nA

-0.6

-1.6

-1

-3

-2

-6

0.03

0.09

0.08

0.24

0.2

0.6

rnA

PARAMETER

MAX

MIN

MAX

MIN

MAX UNIT

STATIC
-40
V

Saturation Drain
Current 3

loss

Vos = 10 V. VGS = 0 V

Gate Reverse Current

IGSS

VGS = -10 V
Ves = 0 V

Gate Operating
Current

-40

IG

ITA =100·C

VeG = 15 V. 10 = 30J.lA

-0.2

-10

-10

-10

pA

-0.03

-25

-25

-25

nA

-0.2
pA

Drain Cutoff Current

10(OFF)

VOS = 10 V. VGS = -6 V

0.2

Gate-Source
Forward Voltage

VGS(F)

IG = 1 rnA. Ves = 0 V

0.7

V

DYNAMLC
Common-Source
Forward
Transconductance

grs

Common-Source
Output Conductance

gas

Common-Source
Input Capacitance

Clss

Common-Source
Reverse Transfer
C@l>acitance
Equivalent Input
Noise Voltage

Crss

en

210

60

250

100

330
J.l$

3

5

10

1.3

3

3

3

Vos = 10 V. VGS = 0 V
f = 1 MHz

0.4

1.5

1.5

1.5

=0 V

15

Vos = 10 V. VGS
f = 1 kHz

NOTES: 1. T A = 25·C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; pw =300 J.lS • duty cycle :s 3 % .

4-112

70

Ves = 10 V. VGS = 0 V
f = 1 kHz

pF

"J.:,
"Hz'

.HSiliconix

PN4117 SERIES

incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
PN4117A

PN4118A

PN4119A

SYMBOL

TEST CONDITIONS

TYp2

Gate-Source
Breakdown Voltage

V(BR)GSS

I G =-l.J.1A.Vo s =OV

-70

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 10 V. 10 = 1 nA

-0.6

-1.8

-1

-3

-2

-6

Saturation Drain
Current 3

loss

Vos = 10 V. V GS = 0 V

0.03

0.09

0.08

0.24

0.2

0.6

rnA

Gate Reverse Current

IGSS

V GS = -10 V
Vos = 0 V

PARAMETER

MIN

-40

MAX

MIN

MAX

MIN

MAX UNIT

STATIC

Gate Operating
Current

-40

-40
V

IG

ITA =100·C

VOG = 15 V. 10 = 30.J.1A

-0.2

-1

-1

-1

pA

-0.03

-2.5

-2.5

-2.5

nA

-0.2
pA

Drain Cutoff Current

10(OFF)

VOS = 10 V. VGS = -8 V

0.2

Gate-Source
Forward Voltage

VGS(F)

IG = 1 rnA. Vos = 0 V

0.7

Common-Source
Forward
Transconductance

gt.

Common-Source
Output Conductance

VOS = 10 V. V GS = 0 V
f = 1 kHz

go.

Common-Source
Input Capacitance

CI••

Common-Source
Reverse Transfer
Capacitance

Cr••

V

DYNAMIC

Equivalent Input
Noise Voltage
NOTES:

en

Vos = 10 V. VGS = 0 V
f = 1 MHz
VOS = 10 V. V GS = 0 V
f = 1 kHz

70

210

80

250

100

330

.J.1S
3

5

10

1.3

3

3

3

0.4

1.5

1.5

1.5

pF

15

%
'-'Hz

1. T A = 25·C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW =300.J.1s. duty cycle :53%.

4-113

PN4302 SERIES

~Siliconix

~ incorporated

N-Channel JFETs

The PN4302 Series of mUlti-purpose JFETs is
designed for a wide range of low cost applications.
It features low gate leakage and capacitance, which
makes these devices ideal for high-frequency
amplifiers. This series is packaged in TO-92 for low
cost and compatibility with automated assembly.

PART
NUMBER

For further design information please consult the
typical performance curves NPA which are located
in Section 7.

9fs

MIN
(mS)

loss
MAX
(mA)

PN4302

-4

-30

1

5

PN4303

-6

-30

2

10

PN4304

-10

-30

1

15

BOTTOM VIEW

TO-92

SIMILAR PRODUCTS
•
•
•

VGS(OFF) V(BR)GSS
MIN
MAX
(V)
(V)

TO-18, See 2N4338 Series
SOT-23, See SST201 Series
Chips, Order PN430XCHP
1 DRAIN
2 SOURCE
3 GATE

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

VGO

-30

Gate-Source Voltage

Vas

-30

Gate Current

la

50

mA

Power Dissipation

Po

360

mW

3.27

mW/oC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
j1/16" from case for 10 seconds)

4-114

TJ

-55 to 135

T stg

-55 to 150

TL

300

°C

PN4302 SERIES

.:r-Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
PN4302

PARAMETER

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -l.lJ.A. Vos = 0 V

Gate-Source
Cutoff Voltage

VGS(OFF)

VOS = 20 V. 10 = 10 nA

TYp2

MIN

-57

-30

MAX

PN4303
MIN

MAX

PN4304
MIN

MAX UNIT

STATIC

V

Saturation Drain
Current 3

loss

Vos = 20 V. VGS =

aV

Gate Reverse Current

IGSS

VGS = -10 V
Vos = a V

= 65°C

Gate-Source
Forward Voltage

-30

-30

VGS(F)

IT

A

IG = 1 mAo Vos =

aV

Vos = 20 V. VGS =
f = 1 kHz

aV

-4
0.5

5

-10

-6
4

10

0.5

15

-0.001

-1

-1

-1

-0.03

-100

-100

-100

0.7

mA
nA
V

DYNAMIC
Common-Source
Forward
Transconductance

gts

Common-Source
Output Conductance

gas

Common-Source
Input Capacitance

C iss

Common-Source
Reverse Transfer
Capacitance

Crss

Vos = 20 V. VGS =
f = 1 MHz

aV
aV

Equivalent Input
Noise Voltage

en

Vos = 10 V. VGS =
f = 1 kHz

Noise Figure

NF

Vos = 10 V. Vas = a V
f = 1 kHz. Ra= 1 M.o.

NOTES:

1

2

1

mS

50

50

50

4.5

6

6

6

1.3

3

3

3

.us
pF

%
-.1HZ

6
<0.1

2

2

3

dB

1. T A = 25 ° C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW =300.lJ.s. duty cycle S3%.

111

4-115

PN4391 SERIES

~SilicDnix

~ incorporated

N-Channel JFET

The PN4391 Series is the plastic equivalent of our
popular 2N4391 Series.
These devices are
especially well suited for analog switching
applications but function efficiently as high-gain
amplifiers. particularly at high-frequency.
Our
low-cost TO-92 packaging offers affordable
performance with flexibility for designers. as these
devices can be ordered with a variety of lead forms
or tape and reel for automated insertion. (See
Section 8.)

PART
NUMBER

rds(ON) IO(OFF)
MAX
MAX
(n)
(nA)

tON
MAX
(ns)

PN4391

-10

30

1

20

PN4392

-5

60

1

20

PN4393

-3

100

1

20

For additional design information please consult the
typical performance curves NCB which are located
in Section 7.

BOTTOM VIEW

TO-92

1 DRAIN
2 SOURCE
3 GATE

SIMILAR PRODUCTS
•
•
•
•

VaS(OFF)
MAX
(V)

SOT-23. See SST4391 Series
TO-18. See 2N4391 Series
Duals. See 2N5564 Series
Chips. Order PN439XCHP

ABSOLUTE MAXIMUM RATINGS (T A = 25 DC unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

VaD

-40

Gate-Source Voltage

Vas

-40

Gate Current

la

50

mA

Power Dissipation

PD

360

mW

3.27

mW/DC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-116

TJ

-55 to 135

T stg

-55 to 150

TL

300

DC

PN4391 SERIES

fCrSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
PN4391

PN4392

PN4393

SYMBOL

TEST CONDITIONS

TYp2

Gate-Source
Breakdown Voltage

V(BR)aSS

la=-1)1.A.Vos=OV

-55

Gate-Source
Cut 011 Voltage

VaSIOFF)

Vos = 20 V. 10 = 1 nA

-4

-10

-2

-5

-0.5

-3

Saturation Drain
Current 3

loss

Vos = 20 V. Vas = 0 V

50

150

25

100

5

60

Gate Reverse Current

lass

PARAMETER

MIN

-40

MAX

MIN

MAX

MIN

MAX UNIT

STATIC

Gate Operating
Current

la

Vas = -20 V
Vos = 0 V

-0.005

-1

-1

-1

-1.0

-200

-200

-200

-5

Vas = -5 V

0.005

Vas = -7 V

0.005

Vas = -12 V 0.005

10(OFF)

VOSION)

T A =100oC

Voa=15V.lo = lOrnA

Vos = 20 V
TA =100°C

Drain-Source
On-Voltage

-40
V

Vos = 20 V
Drain Cut 011 Current

-40

Vas = 0 V

Vas = -5 V

1

Vas = -7 V

1

Vas = -12 V

1

10 = 3 rnA

0.25

10 = 6 rnA

0.30

10 = 12 rnA

0.35

Drain-Source
On-Resistance

rOS(ON)

Vas=OV.lo = 1 rnA

Gate-Source
Forward Voltage

VaS(F)

I a = 1 rnA. Vos = 0 V

rnA

nA
pA

1
1
1
200

nA

200
200
0.4
0.4

V

0.4
30

60

100

.n

0.7

V

6

mS

25

)lS

DYNAMIC
Common-Source
Forward

gfs

Transconductance

Common-Source
Output Conductance

gos

Voa=20V.lo= 1 rnA
I = 1 kHz

rds(ON)

Vas = 0 V. 10 =0
1= 1 kHz

Common-Source
Input Capacitance

C lss

Vos = 20 V. Vas = 0 V
1=1 MHz

Common-Source
Reverse Transler
Capacitance

Crss

Vos = 0 V
1= 1 MHz

Drain-Source
On-Resistance

Equivalent Input
Noise Voltage

en

12

Vas = -5 V

3.5

Vas = -7 V

3.5

Vas = -12 V

3.5

Voa = 10 V. 10 = 10 rnA
1=1 kHz

30

60

100

16

16

16
5

.n

pF

5
5

%
"Hz'

3.0

SWITCHING
Turn-on Time

td(ON)
tr

Turn-oIl Time
NOTES:

tdIOFF)
tf

Voo = 10 V. VaSION) = 0 V
PIN
PN4391
PN4392
PN4393

101ON) Vas (OFF) RL
BOO .n
12 rnA -12 V
6 rnA
-7 V 1600.n
-5 V 3200.n
3 rnA

2

15

15

2

5

5

15
5

6

20

35

50

13

15

20

30

ns

1. T A = 25°C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW = 300)1.S. duty cycle :S3%.

4-117

~Siliconix

PN4416

~ incorporated

N-Channel JFET

The PN4416 is an-channel JFET designed to
provide high-performance amplification. especially
at high-frequency. These parts feature low noise
(4 dB max @ 400 MHz). high gain (10 dB min @
400 MHz) and provide a wide bandwidth. Its low
cost TO-92 package is available with a wide range
of lead form and tape and reel opitons. (See
Section 8.)

PART
NUMBER
PN4416

For additional design information please see
performance curves NH. which are located in
Section 7.

-6

-30

TO-92

MIN
(mS)

loss
MAX
(mA)

4.5

15

9fs

BOTTOM VIEW

1 SOURCE
2 DRAIN
3 GATE

SIMILAR PRODUCTS
•
•
•

VGS(OFF) V(BR)GSS
MIN
MAX
(V)
(V)

TO-72. See 2N4416
SOT-23. See SST4416
Chips. Order PN4416CHP

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

Vao

-30

Gate-Source Voltage

Vas

-30

Gate Current

la

10

mA

Power Dissipation

Po

360

mW

3.27

mW/oC

V

Power Derating
"',

Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-118

TJ

-55 to 135

T stg

-55 to 150

h

300

°C

PN4416

.-rSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
PN4416

TYp2

MIN

I G =-1.uA,V os =OV

-36

-30

VGS(OFF)

VOS = 15 V, 10 = 1 nA

-3

Saturation Drain
Current 3

loss

Vos = 15 V, VGS = 0 V

10

Gate Reverse Current

IGSS

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)GSS

Gate-Source
Cutoff Voltage

PARAMETER

UNIT

MAX

STATIC

V

Gate Operating
Current

V GS = -15 V
Vos = 0 V

-6
15

5

-1

-0.002

I T A =125°C

mA
nA

-0.6

IG

VOG = 10 V, 10 = 1 mA

-20

Drain Cutoff Current

10(OFF)

VOS = 10 V, VGS = -6 V

5

Drain-Source
On-Resistance

rOS(ON)

VGS = 0 V, 10 = 1 mA

150

.n

VGS(f)

IG=1mA,Vos=OV

0.7

V

pA

Gate-Source
Forward Voltage

DYNAMIC
Common-Source
Forward
Transconductance

gfs

Common-Source
Output Conductance

gas

Common-Source
Input Capacitance

C lss

Common-Source
Reverse Transfer
Capacitance

c;.ss

Common-Source
Output Capacitance

Coss

Equivalent Input
Noise Voltage

en

4.5

7.5

mS

15

50

.uS

2.2

4

0.7

0.8

1

2

6

Vos = 15 V, V GS = 0 V
f = 1 kHz

Vos = 15 V, VGs = 0 V
f = 1 MHz

Vos = 10 V, V GS = 0 V
f:, 100 Hz

~
"HZ'

9
LIMITS

ELECTRICAL CHARACTERISTICS 1
PARAMETER

SYMBOL

pF

TEST CONDITIONS

TYp2

I

100 MHz
MIN
MAX

I

400 MHz
MIN
MAX

I
UNIT

HIGH-FREQUENCY
Common-Source
Input Conductance

g Iss

100

1000

Common-Source
Input Susceptance

blss

2500

10000

Common-Source
Output Conductance

g05S

75

100

Common-Source
Output Susceptance

boss

1000

4000

Common-Source Forward
Transconductance

gfs

Common-Source
Power Gain

G ps

V os =15V,1 0 =5mA

Noise Figure

NF

V os =15V,1 0 =5mA
RG = 1 f<,(1

NOTES:

Vos = 15 V, V GS =

aV

.uS

4000
18

10
dB
2

4

1. T A = 25 °C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300.us , duty cycle :5: 2 % .

4-119

.-r'Siliconix

SST108 SERIES

.LII

incorporated

N-Channel JFET

The SST10a Series is the surface mount equivalent
of our Jl0a device types. It features the lowest
rOS(ON) of any SOT-23 JFET device, which makes it
especially well suited for analog switching
applications. Siliconix' surface mount commitment
features low cost performance for a wide range of
commercial applications as well as tape and reel
options for automatic insertion and high-volume
assembly. (See Section a.)

PART
NUMBER

VGS(OFF)
MAX
(V)

rds(ON) IO(OFF)
TYP
MAX
(0)
(pA)

tON
TYP
(ns)

SST10a

-10

a

20

4

SST109

-6

12

20

4

SSTll0

-4

la

20

4

TOP VIEW

SOT-23

For further design information please consult the
typical performance curves NIP which are located in
Section 7.

2

3
1 GATE
2 DRAIN
3 SOURCE

SIMILAR PRODUCTS
PRODUCT MARKING
•
•
•

TO-92, See Jl0a Series
TO-52, See 2N5432 Series
Chips, Order J1XXCHP

SSTloa

loa

SST109

109

SST110

110

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

VGO

-25

Gate-Source Voltage

VGS

-25

Gate Current

IG

50

mA

Power Dissipation

Po

350

mW

2.a

mW/oC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-120

TJ

-55 to 150

T stg

-55 to 150

TL

300

°C

SST108 SERIES

ICrSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST108

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

I G = -l)J.A, V DS = 0 V

-32

-25

Gate-Source
Cutoff Voltage

VGS(OFF)

V DS = 5 V, I D = 1 )J.A

-3

Saturation Drain
Current 3

IDSS

V DS = 15 V, V GS = 0 V

80

Gate Reverse Current

IGSS

PARAMETER

MAX

SST109
MIN

MAX

SSTll0
MIN

MAX UNIT

STATIC

Gate Operating
Current

Drain Cutoff Current

-25

-25
V

V GS = -15 V
V DS = 0 V

IG

-0.01
ITA =125°C

-10

-2

-6

40

-0.5

-4

10

rnA

-3

-3

-3

3

3

3

8

12

18

-5

V DG = 10 V, I D = 10 rnA

-0.01

V DS = 5 V, V GS = -10 V

0.02

V DS = 5 V, V GS = -10 V
T A =125°C

1.0

nA
ID(OFF)

Drain-Source
On-Resistance

rDS(ON)

VGS = 0 V, V DS S 0.1 V

Gate-Source
Forward Voltage

VGS(F)

I G = 1 rnA, VDS = 0 V

.0.

0.7

V

17

mS

600

)J.S

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Drain-Source
On-Resistance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Caoacltance
Equivalent Input
Noise Voltage

gfs

V DG =5V,I D =10mA
f = 1 kHz

gos
rds(ON)

V GS = 0 V, ID = 0 V
f = 1 kHz

C lss

V DS = 0 V, V GS = 0 V
f = 1 MHz

Crss

en

8

12

18

60

85

85

85

V DS = 0 V, V GS = -10 V
f = 1 MHz

11

15

15

15

V DG = 5 V, ID = 10 rnA
f = 1 kHz

3.5

.0.

pF

~
VRZ

SWITCHING
Turn-on Time

td(ON)
tr

Turn-off Time

~(OFF)

tf

VDD = 1.5 V, VGS(ON) =
I D(ON) V GS(OFF)
SST108 lOrnA -12 V
SST109 lOrnA
-7 V
-5 V
SSTll0 lOrnA
PIN

0V
RL
150
150
150

3

.n.
.n.
.n.

1
4

ns

18

NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300)J.S, duty cycle S 3%.

4-121

III

SST111 SERIES

.-FSiliconix

~ incorporated

N-Channel JFET

The SST111 Series is the surface mount equivalent
of our J111 device types. Its low cost and rOS(on)

PART
NUMBER

make it a good choice for an all-purpose analog
switch, while its high gf8 and good high-frequency
response also make this product useful in a
high-gain amplifier mode. Like all SOT-23 products
available from Siliconix, tape and reel capabilities
exist for automated assembly. (See Section 8.)

VaS(OFF)
MAX
(V)

rds(ON) IO(OFF)
MAX
TYP
(pA)
(n)

tON
TYP
(ns)

SST111

-10

30

5

4

SST112

-5

50

5

4

SST113

-3

100

5

4

SOT-23

TOP VIEW

For further design information please consult the
typical performance curves NCB which are located
in Section 7.

2

3
1 GATE
2 DRAIN
3 SOURCE

SIMILAR PRODUCTS

PRODUCT MARKING
•
•
•
•

TO-92, See J111 Series
TO-18, See 2N4391 Series
Duals, See 2N5564 Series
Chips, Order J11XCHP

SST111

C11

SST112

C12

SST113

C13

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

Vao

-35

Gate-Source Voltage

Vas

-35

Gate Current

la

50

mA

Power Dissipation

Po

350

mW

2.8

mW/oC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-122

TJ

-55 to 150

Tstg

-55 to 150

TL

300

°C

SST111 SERIES

~SilicDnix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST111

TYp2

MIN

-55

-35

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -1.11A, VDS = 0 V

Gate-Source
Cutoff Voltage

VGS(OFF)

V DS = 5 V, I D = 1 .I1A

-3

Saturation Drain
Current 3

loss

Vos = 15 V, V GS = 0 V

20

Gate Reverse Current

IGSS

PARAMETER

MAX

SST112
MIN

MAX

SST113
MIN

MAX UNIT

STATIC

Gate Operating
Current

Drain Cutoff Current

-35

-35
V

VGS = -15 V
V DS = 0 V

-5

V DS = 10 V. V GS = -12 V

0.005

V DS = 10 V. V GS = -12 V
T A =125°C

3

Drain-Source
On-Resistance

rDS(ON)

V GS = 0 V, VDS = 0.1 V

Gate-Source
Forward Voltage

VGS(F)

I G = 1 mA, V DS = 0 V

-1
5

-1

-3

-5
2
-1

mA
-1

-3

V DG =15V,I D =10mA

IG

ID(OFF)

0.005
ITA =125°C

-10

nA
pA

1

1

1
nA

30

50

100

.0.

0.7

V

6

mS

25

JJ.S

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Drain-Source
On-Resistance

gt.

f = 1 kHz

go.

V GS = 0 V, ID = 0 V
f = 1 kHz

rd. (ON)

Common-Source
Input Capacitance

CI••

Common-Source
Reverse Transfer
Capacitance

Cr••

Equivalent Input
Noise Voltage

V DG =20V,I D = 1 mA

V DS = 0 V, V GS = -10 V
f = 1 MHz

en

V DG = 10 V, ID = 1 mA
f = 1 kHz

td(ON)

VDO = 10 V, VGS(ON) = 0 V
I D(ON) VGS(OFF) RL
SST111 12.5 mA -12 V 800.0.
SST112 6.25 mA -7V 1600.0.
SST113
3.1 mA -5 V 3200.0.

30

50

100

7

12

12

12

3

5

5

5

.0.

pF

4

~
"HZ

SWITCHING
Turn-on Time
Turn-off Time

t,
td(OFF)
tt

PIN

2
2
6

ns

15

NOTES: 1. T A = 25 °C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW =300.l1S, duty cycle :$3%.

4-123

~Siliconix

SST174 SERIES

~ incorporated

P-Channel JFET

The SST174 Series is a low-cost p-channel analog
switch designed to provide low on-resistance and
fast switching. It works well in conjunction with
Siliconix' Jl11 Series for complimentary switching
applications. It features a SOT-23 package and is
available tape and reeled to support automated
assembly.
(See Section 8.)

PART
NUMBER

For further design information please consult the
typical performance curves PSCIA which are
located in Section 7.

VGS(OFF)
MAX
(V)

rds(ON)
MAX
(.0)

IGSS
MAX
(nA)

tON
TYP
(ns)

SST174

10

85

1

25

SST175

6

125

1

25

SST176

4

250

1

25

SSTl77

2.25

300

1

25

SOT-23

TOP VIEW

SIMILAR PRODUCTS
•
•
•

TO-18, See 2N5114 Series
TO-92, See J174 Series
Chips, Order J17XCHP

1 GATE
2 DRAIN
3 SOURCE
PRODUCT MARKING
SST174

S74

SST175

S75

SST176

S76

SSTl77

S77

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

VGD

30

Gate-Source Voltage

VGS

30

Gate Current

IG

-50

mA

Power Dissipation

PD

350

mW

2.8

mW/oC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-124

TJ

-55 to 150

T stg

-55 to 150

lL

300

°C

SST174 SERIES

~SilicDnix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST174

SST175

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

VIBR)GSS

I G = 1 JJ.A. Vos = 0 V

45

30

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = -15 V. 10 = -10 nA

5

10

3

6

Saturation Drain
Current 3

loss

VOS = -15 V. VGS = 0 V

-20

-135

-7

-70

Gate Reverse Current

IGSS

PARAMETER

MAX

MIN

MAX

UNIT

STATIC

Gate Operating
Current

30
V

V GS = 20 V
VOS = 0 V

IG

0.01

I

T A =125°C

1

1

5

VOG=-15V.10 =-1 mA

10

VOS = -15 V. V GS = 10 V

-10

Vos = -15 V. V GS = 10 V
T A =125°C

-5

mA
nA

pA
Drain Cutoff Current

10(OFF)

Drain-Source
On-Resistance

rOSION)

V GS = 0 V. Vos = -0.1 V

Gate-Source
Forward Voltage

VGS(F)

IG=-lmA.Vos=OV

nA
85

125

.0.

-0.7

V

4.5

mS

20

p.S

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Drain-Source
On-Resistance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Caoacltance
Equivalent Input
Noise Voltage

gf.

Vos = -15 V. 10 = -1 mA
f = 1 kHz

gas

V GS = 0 V. 10 = 0 mA
f = 1 kHz

rds(ON)

85

Ciss

Vos = 0 V. VGS = 0 V
f = 1 MHz

20

Crss

Vos = 0 V. V GS = 10 V
f = 1 MHz

5

en

Vos = -10 V. 10 = -1 mA
f = 1 kHz

20

125

.0.

pF

~
VRZ

SWITCHING
Turn-on Time
Turn-off Time

tdlON)
tr
~IOFF)

tf
NOTES:

10

VGSION) - 0 V
PIN
SST174
SST175

Voo
-10 V
-6 V

VGS(OFF)

RL

15

12 V
8V

560.n.
1200.n.

10

ns

20

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300p.S, duty cycle ~3%.

4-125

~Siliconix

SST174 SERIES

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST176

TYp2

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)GSS

IG=lJ.lA.Vos=OV

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = -15 V. 10 = -10 nA

1

4

0.8

2.25

loss

Vos = -15 V. VGS = 0 V

-2

-35

-1.5

-20

PARAMETER

MIN

SSTl77

MAX

MIN

MAX

UNIT

STATIC

Saturation Drain
Current 3
. Gate Reverse Current
Gate Operating
Current

45

30

30

V

IGSS

VGS = 20 V
Vos = 0 V

IG

0.01

I

TA=125°C

1

1

5

V oG =-15V.l o =-1 rnA

10

Vos = -15 V. Vas = 10 V

-10

VOS = -15 V. Vgs = 10 V
TA =125°C

-5

rnA
nA

pA
Drain Cutoff Current

10(OFF)

Drain-Source
On-Resistance

rOS(ON)

VGS = 0 V. VOS = -0.1 V

Gate-Source
Forward Voltage

VGS(F)

IG = -1 rnA. VOS = 0 V

nA
250

300.

n

-0.7

V

4.5

mS

20

J.lS

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Drain-Source
On-Resistance
Common-Source
Input Capacitance
Common-Source
~~~~~,ftance
Transfer
Equivalent Input
Noise Voltage

grs
Vos = -15 V. 10 = -1 rnA
1= 1 kHz

gas

VGs=OV.lo=OmA
1= 1 kHz

rdS(ON)

250

C lss

Vos = 0 V. VGS = 0 V
1=1 MHz

20

Crss

Vos = 0 V. VGS = 10 V
1=1 MHz

5

en

Vos = -10 V. 10 = -1 rnA
1=1 kHz

20

td(ON)

VGS(ON) = 0 V

10

300

n
pF

~
VHz

SWITCHING
Turn-on Time
Turn-ofl Time

tr
td(OFF)
tr

PIN

Voo

SST176
SST177

-6 V
-6 V

VGS(OFF)
6V
3V

NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW =300).1.8. duty cycle ;5;3%.

4-126

RL

15

5600.n
10000.n

10
20

ns

g

SST201 SERIES

Siliconix

incorporated

N-Channel JFETs

The SST201 Series is the SOT-23 equivalent of our
popular J201 Series. It features low leakage, very
low noise, and low cutoff voltage for use with low
level power supplies. The SST201 and SST204 are
excellent for battery operated equipment and low
current amplifiers. The SST201 Series' SOT-23
package affords low cost and compatibility with
automated assembly techniques. (See Section 8.)

PART
NUMBER

loss
MAX
(rnA)

9fs

MIN
(mS)

SST201

-1.5

-40

0.5

1

SST202

-4

-40

1

4.5

SST203

-10

-40

1.5

20

SST204

-2

-25

0.5

3

For further design information please consult the
typical performance curves NPA which are located
in Section 7.

SOT-23

TOP VIEW

~

SIMILAR PRODUCTS
•
•
•

VaS(OFF) V(BR)aSS
MAX
MIN
(V)
(V)

2

.'

TO-18, See 2N4338 Series
TO-92 , See J201 Series
Chips, Order J20XCHP

3
1 GATE
2 SOURCE
3 DRAIN

PRODUCT MARKING

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

SST201

P01

SST202

P02

SST203

P03

SST204

P04

III

= 25 DC unless otherwise noted)
SYMBOL

LIMIT

Gate-Drain Voltage

Vao

-40

Gate-Source Voltage

Vas

-40

Gate Current

la

50

rnA

Power Dissipation

Po

350

mW

2.8

mW/oC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 150

Tstg

-55 to 150

TL

300

°C

4-127

SST201 SERIES

~SilicDnix

~ incorpora.ted

EL.ECTRICAL. CHARACTERISTICS 1

LIMITS
SST201

SST202

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

I G =-lJ,lA.Vos =OV

-57

-40

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 20 V. 10 = 10 nA

-0.3

-1.5

-O.B

-4

Saturation Drain
Current 3

loss

Vos = 20 V. V GS = 0 V

0.2

1.0

0.9

4.5

mA

Gate Reverse Current

IGSS

-100

pA

PARAMETER

MAX

MIN

MAX

UNIT

STATIC

Gate Operating
Current

-40
V

IG

V GS = -20 V
Vos = 0 V

-2

I

T A =125°C

-100

nA

-1

VOG=15V.10 =O.lmA

-2

Drain Cutoff Current

10(OFF)

Vos = 15 V. V GS = -10 V

2

Gate-Source
Forward Voltage

VGS(F)

I G = 1 mA. Vos = 0 V

0.7

gfs

Vos = 20 V. V GS = 0 V
f = 1 kHz

pA

V

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Capacitance
Equivalent Input
Noise Voltage
NOTES:

4-128

C lss

Vos = 20 V. VGS = 0 V
f = 1 MHz

erss

en

0.5

1

mS

4.5
pF
1.3

Vos = 10 V. VGS = 0 V
f = 1 kHz

1. T A = 25°C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW = 300J,ls. duty cycle :!>3%.

6

%
"HZ

SST201 SERIES

W'rSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST203

SST204

SYMBOL

TEST CONDITIONS

TYp2

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -lJJ.A. VOS = 0 V

-57

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 20 V. 10 = 10 nA

-2

-10

-0.3

-2

Saturation Drain
Current 3

loss

Vos = 20 V. V GS = 0 V

4

20

0.2

3

rnA

Gate Reverse Current

IGSS

-100

pA

PARAMETER

MIN

-40

MAX

MIN

MAX

UNIT

STATIC

Gate Operating
Current

-25
V

V GS = -20 V
VOS = 0 V

-2

I

TA =125·C

-100

nA

-1

IG

VOG = 15 V. 10 = 0.1 rnA

-2

Drain Cutoff Current

10(OFF)

Vos = 15 V. V GS = -10 V

2

Gate-Source
Forward Voltage

VGS(F)

I G = 1 rnA. Vos = 0 V

0.7

pA

V

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Capacitance
Equivalent Input
Noise Voltage

gls

Vos = 20 V. V GS = 0 V
f = 1 kHz

C 1SS
Crss

en

Vos = 20 V. VGS = 0 V
f = 1 MHz

1.5

0.5

mS

4.5
pF
1.3

Vos = 10 V. VGS = 0 V
f = 1 kHz

6

'%
VHZ

NOTES: 1. T A = 25·C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test: PW =300JJ.s. duty cycle S3%.

4-129

SST270 SERIES

~SilicDnix

~ incorporated

P·Channel JFET

The SST270 Series is an all-purpose amplifier for
designs requiring p-channel operation.
These
devices feature high gain, low noise and tight
VaS(OFF) limits for simple circuit design. They are
available In low-cost SOT-23 packages and are fully
compatible with automatic insertion techniques.
(See Section 8 for details.)

gfs
MIN
(mS)

loss
MAX
(mA)

30

6

-15

30

8

-50

VGS(OFF)
MAX
(V)

V(BR)GSS
MIN
(V)

SST270

2.0

SST271

4.5

PART
NUMBER

TOP VIEW

SOT·23

For further deSign information please consult the
typical performance curves PSCIA which are
located in Section 7.

SIMILAR PRODUCTS
•
•

1 GATE
2 DRAIN
3 SOURCE

TO-92 , See J270 Series
Chips, Order J27XCHP

PRODUCT MARKING

I
I

SST270
88T271

S70
871

ABSOLUTE MAXIMUM RATINGS (T A = 25 DC unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

Vao

30

Gate-Source Voltage

Vas

30

Gate Current

la

-50

mA

Power Dissipation

Po

350

mW

2.8

mW/oC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-130

TJ

-55 to 150

Tstg

-55 to 150

TL

300

°C

g

SST270 SERIES

Siliconix

incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST270

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

I G = 1 Jl.A, VOS = 0 V

45

30

Gate-Source
Cutoff Voltage

VGS(OFF)

PARAMETER

MAX

SST271
MIN

MAX

UNIT

STATIC

V

Saturation Drain
Current 3

loss

Gate Reverse Current

IGSS

Gate Operating
Current

30

V os =-15V,

10

=-1 nA

Vos = -15 V, V GS = 0 V
V GS = 20 V
Vos = 0 V

0.5

2.0

1.5

4.5

-2

-15

-6

-50

mA

200

pA

10

I

T A =125·C

200

5

IG

V oG =-15V, 10 =-1 mA

10

Drain Cutoff Current

I o (OFF)

VOS = -15 V, V GS = 10 V

-10

Gate-Source
Forward Voltage

VGS(F)

IG = -1 mA, VOS = 0 V

-0.7

nA

pA

V

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance

gfs
gas'

Common-Source
Input Capacitance

C lss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

en

6

V os =-15V,V Gs =OV
f = 1 kHz

Vos = -15 V, V GS = 0 V
f = 1 MHz

15
200

8

18

mS

500

jJ.S

20
pF
4

Vos = -10 V, VGs = 0 V
f = 1 kHz

20

%
"Hz'

NOTES: 1. T A = 25·C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300jJ.S, duty cycle S3%.

4-131

..

..:rSiliconix

SST308 SERIES

~ incorpora.ted

N-Channel JFETs

The SST30B Series is the surface mount equivalent
of our popular J30B Series. It features high-gain
(> BOOO J.lS). low noise (typically < 6 nV.J'Hz) and
low gate leakage (typically < 2 pA). Of special
interest. however. is performance at high
frequency. Even at 450 MHz. the SST30B Series
offers high power gain and low noise. Tape and
reel options are available to support automated
assembly. (See Section B.)

PART
NUMBER

VGS(OFF) V(BR)GSS
MIN
MAX
(V)
(V)

9fs

MIN
(mS)

loss
MAX
(mA)

SST30B

-6.5

-25

B

60

SST309

-4

-25

10

30

SST31 0

-6.5

-25

B

60

SOT-23

TOP VIEW

For additional design information and a closer look
at high-frequency characteristics. please consult
performance curves NZB which are located in
Section 7.
1 GATE
2 DRAIN
3 SOURCE
PRODUCT MARKING

SIMILAR PRODUCTS
•
•
•
•

ZOB

SST30B

TO-92. See J30B Series
TO-52. See U30B Series
Dual. See U430 Series
Chips. Order J30XCHP

SST309

Z09

SST31 0

Z10

ABSOLUTE MAXIMUM RATINGS (T A = 25 DC unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

VGO

-25

Gate-Source Voltage

VGS

-25

Gate Current

IG

10

mA

Power Dissipation

Po

350

mW

2.B

mW/DC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-132

TJ

-55 to 150

T stg

-55 to 150

TL

300

DC

SST308 SERIES

~Siliconix

~ incorporatec

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST308

SST309

SST310

SYMBOL

TEST CONDITIONS

TYp2

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -lJ.LA. V DS = 0 V

-35

Gate-Source
Cutoff Voltage

VGS(OFF)

VDs=10V.ID=lnA

-1

-6.5

-1

-4

-2

-6.5

Saturation Drain
Current 3

IDSS

V DS = 10 V. VGS = a V

12

60

12

30

24

60

Gate Reverse Current

IGSS

V GS = -15 V
V DS = 0 V

PARAMETER

MIN

-25

MAX

MIN

MAX

MIN

MAX UNIT

STATIC
-25

-25
V

TA =125°C

mA

-0.002

-1

-1

-1

nA

-0.008

-1

-1

-1

J.LA

Gate Operating
Current

IG

V DG = 9 V. I D = lamA

-15

pA

Drain-Source
On-Resistance

rDS(ON)

V GS = 0 V. ID = 1 mA

35

.n.

VGS(F)

I G = 10 mAo V DS = 0 V

0.7

V

V DS = 10 V. I D = 10 mA
f = 1 kHz

14

Gate-Source
Forward Voltage

DYNAMIC
Common-Source
Forward
Transconductance

gfs

Common-Source
Output Conductance

90S

Common-Source
Input Capacitance

Clss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

en

V GS = -10 V. V DS = 10 V
f = 1 MHz
V DS = 10 V. ID = 10 mA
f = 100 Hz

10

8

8

mS

110

250

250

250

4

5

5

5

1.9

2.5

2.5

2.5

J.LS

pF

6

~
VHZ

HIGH FRI:QUENCY
Common-Gate Foward
Transconductance
Common-Gate Output
Conductance
Common-Gate Power
Gain4
Noise Figure

NOTES:

1.
2.
3.
4.

f = 105 MHz

gfg

9 0g

G pg

NF

V DS = 10 V
ID = 10 mA

15

f = 450 MHz

13

f = 105 MHz

0.16

f = 450 MHz

0.55

f = 105 MHz

16

f = 450 MHz

11.5

f = 105 MHz

1.5

f = 450 MHz

2.7

mS

dB

T A = 25 0 C unless otherwise noted.
For design aid only. not subject to production testing.
Pulse test; PW =300J.Ls. duty cycle S3%.
Gain (Gpgl measured at optimum Input noise match.

4-133

..rSiliconix

SST404 SERIES

~ incorporate!:!

N-Channel JFET Pairs

The 8ST404 Series is the surface mount equivalent
of our U401 Series.
It is available in a SO-8
package with three ranges of offset and drift
specifications. It features extremely low noise and
gate leakage and is intended for use in a wide
range of precision instrumentation. For ease of
manufacturing, the symmetrical pinout prevents
improper orientation. Finally, tape and reel options
are available to make this product compatible with
automatic assembly methods. (See Section 8.)

PART
NUMBER

V(BR)GSS g,s
MIN
MIN
(V)
(mS)
2

-15

-50

2

-15

20

-50

2

-15

40

SST404

-50

SST405
SST406

For additional design information please see
performance curves NNR, which are located in
Section 7.

IG IVGS1- VGS21
MAX
MAX
(pA)
(mV)
15

TOP VIEW

SO-8

SIMILAR PRODUCTS
•
•

TO-71 , See U401 Series
Chips, Order U40XCHP

ABSOLUTE MAXIMUM RATINGS (T A

= 25°C unless otherwise
SYMBOL

LIMIT

Gate-Drain Voltage

VGO

-50

Gate-Source Voltage

Vas

-50

Forward Gate Current

la

10

PARAMETERS/TEST CONDITIONS

noted)
UNITS

V

Power Dissipation
Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-134

Per Side
Total
Per Side
Total

Po

300
500
2.4
4

TJ

-55 to 150

T stg

-55 to 200

TL

300

mA
mW
mW/DC

DC

.HSiliconix
incorporated

SST404 SERIES

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST404

SST405

SST406

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

I G =-l.11A,V os =OV

-58

-50

-50

-50

Gate-Gate
Breakdown Voltage

V(BR)Gl - G2

I G = ± 1 .I1A, Vos = 0 V
V GS = 0 V

-58

±50

±50

±50

VGS(OFF)

Vos = 15 V, 10 = 1 nA

-1.5

-0.5

-2.5

-0.5

-2.5

-0.5

-2.5

Saturation Drain 3
Current

loss

Vos = 15 V, V GS = 0 V

3.5

0.5

10

0.5

10

0.5

10

mA

Gate Reverse
Current

IGSS

-25

pA

PARAMETER

MAX

MIN

MAX

MIN

MAX UNIT

STATIC

Gate-Source
Cutoff Voltage

Gate Operating
Current
Drain-Source
On-Resistance
Gate-Source Voltage
Gate-Source
Forward Voltage

IG
rOS(ON)

V GS = -30 V
Vos = 0 V
VOG = 15 V
10= 200 J.lA

V

-2

IT

A =125°C

IT

A

=125°C

-25

-25

-1

nA

-2

-15

-15

-15

pA

-0.8

-10

-10

-10

nA

V Gs =OV,l o =O.l mA

250

V GS

VOG = 15 V, 10= 200J.lA

-1

VGS(F)

IG = 1 mA, Vos = 0 V

0.7

.0.
-2.3

-2.3

-2.3
V

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance

gls
gos

Common-Source
Forward
Transconductance
Common-Source
Output Conductance

gos

Common-Source
Input Capacitance

C lss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

VOG = 15 V, 10 = 200 J.lA
f = 1 kHz

gls

en

Vos = 10 V, V GS = 0 V
f = 1 kHz

VOG = 15 V, 10 = 200 J.lA
f = 1 MHz
VOG = 15 V, 10 = 200 J.lA
f = 10 Hz

1.5

1

1.3
1.5

2

1

2
2

10

7

2

1

2
2

7

2

2

mS

2

.us

7

mS

.us

20

20

20

8

8

8

1.5

3

3

3

10

20

20

20

%
VHz

15

20

40

mV

25

40

80

25

40

80

~°C

pF

MATCHING
Differential
I VGS1-VGS21
Gate-Source Voltage

VOG = 10 V, 10 = 200.l1A

vi

Gate-Source Voltage "IVGS1-VGS21 VOG = 10
T = -55 to 25°C
Differential Change
with Temperature
10= 200 J.lA1 T = 25 to 1250C
"T
Common Mode
Rejection Ratio

CMRR

VOG = 10 to 20 V, 10= 200 J.lA

102

95

90

dB

NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300.l1s, duty cycle :$3%.

4-135

tcrSiliconix

SST440 SERIES

~ incorporated

N-Channel JFET Pairs

The SST440 Series are monolithic pairs of JFETs
mounted in a single SO-8 package. The SST440
Series features high speed amplification (slew
rate), high gain (typically> 6 mS), and low gate
leakage (typically < 1 pAl .
This performance
makes these devices perfect for use as wideband
differential amplifiers in demanding test and
Finally, its SO-8
measurement applications.
package is available in tape and reel to support
automated assembly. (See Section 8.)

PART
NUMBER
SST440
SST441

For additional design information please see
performance curves NNZ, which are located in
Section 7.

V(BR)GSS 91s
MIN
MIN
(mS)
(V)
-25
-25

IG IVGS1- VGS21
MAX
MAX
(pA)
(mV)

4.5

-500

10

4.5

-500

20

TOP VIEW

SO-8

SIMILAR PRODUCTS
•
•
•
•

TO-71 , See U440 Series
TO-78 , See U443 Series
Low Noise, See SST404 Series
Chips, Order U44XCHP

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

VGD

-25

Gate-Source Voltage

VGS

-25

Forward Gate Current

IG

50

UNITS

V

Power Dissipation
Power Derati\lg
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-136

Per Side
Total
Per Side
Total

PD

300
500
2.4
4

TJ

-55 to 150

T stg

-55 to 150

TL

300

mA
mW

mWloC

°C

.HSiliconix

SST440 SERIES

incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST440

SST441

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -1.I1A, Vos = 0 V

-35

-25

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 10 V, 10 = 1 nA

-3.5

-1

-6

-1

-6

15

6

30

6

30

rnA

-500

pA

PARAMETER

MAX

MIN

MAX

UNIT

STATIC
-25
V

Saturation Drain
Current 3

loss

Gate Reverse
Current

IGSS

Gate Operating
Current

IG

Gate-Source
Forward Voltage

VGS(F)

Vos = 10 V, VGS =
VGS = -15 V
Vos = 0 V

aV

-500

-1

I TA =125°C

-0.2

I TA =125°C

-0.2

nA

IG = 1 rnA, Vos = 0 V

0.7

V

VOG = 10 V, 10 = 5 rnA
f = 1 kHz

6

VOG = 10 V
10 = 5 rnA

nA

-1

-500

-500

pA

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance

gls
gos

Common-Source
Forward
Transconductance
Common-Source
Output Conductance

20

gls

VOG = 10 V, 10 = 5 rnA
f = 100 MHz

gos

9
200

4.5

9

mS

200

J,lS

5.5

mS

30

J,lS

Common-Source
Input Capacitance

C lss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

en

VOG = 10 V, 10 = 5 rnA
f=10kHz

4

I VGsrVGs21

VOG = 10 V, 10 = 5 rnA

7

VOG = 10 V, 10 = 5 rnA
f = 1 MHz

4.5

3.5
pF

1

%
VHz

MATCHING
Differential
Gate-Source Voltage
Gate-Source Voltage
Differential Change
with Temperature

I

A VGSrVGS2
AT

I

VOG = 10 V
10 = 5 rnA

I

T = -55 to 25°C

I T = 25 to 125°C

10
10

Saturation
Drain Current Ratio

10SS1
loss2

VOS = 10 V, VGS = 0 V

0.96

Transconductance
Ratio

glsl
gls2

VOG = 10 V, 10 = 5 rnA
f = 1 kHz

0.98

CMRR

Voo =5tol0V,l o =5mA

90

Common Mode
Rejection Ratio

10

20

mV

~°c

dB

NOTES: 1. T A = 25 ° C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300)1s, duty cycle S3'Yo.

4-137

..

~SilicDnix

SST4091 SERIES

~ incorporated

N-Channel JFET

The SST4091 Series is the surface mount
equivalent of our popular 2N4091 device types. Its
low cost and rOS(on) make it a good choice for an

PART
NUMBER

all-purpose analog switch, while its high gfs and
good high-frequency response also make this
product useful in a high-gain amplifier mode. Like
all SOT-23 products available from Siliconix, tape
and reel capabilities exist for automated assembly.
(See Section 8.)

VaS(OFF)
MAX
(V)

rds(ON) IO(OFF)
TYP
MAX
(il)
(pA)

tON
TYP
(ns)

SST4091

-10

30

5

4

SST4092

-7

50

5

4

SST4093

-5

80

5

4

TOP VIEW

SOT-23

For further design information please consult the
typical performance curves NCB which are located
in Section 7.

1 GATE
2 DRAIN
3 SOURCE

SIMILAR PRODUCTS
•
•
•
•

TO-18,
TO-92,
Duals,
Chips,

PRODUCT MARKING

See 2N4091 Series
See PN4091 Series
See 2N5564 Series
Order 2N409XCHP

SST4091

C41

SST4092

C42

SST4093

C43

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

Vao

-35

Gate-Source Voltage

Vas

-35

Gate Current

la

10

mA

Power Dissipation

Po

350

mW

2.8

mW/oC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-138

TJ

-55 to 150

Tstg

-55 to 150

TL

300

°C

SST4091 SERIES

.-r-Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST4091

PARAMETER

TYp2

MIN

-55

-35

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -1 JJ.A, V DS = 0 V

Gate-Source
Cutoll Voltage

VGS(OFF)

V Ds =20V,I D =10nA

-5

Saturation Drain
Current 3

IDss

V DS = 20 V, VGS = 0 V

30

Gate Reverse Current

IGSS

MAX

SST4092
MIN

MAX

SST4093
MIN

MAX UNIT

STATIC

Gate Operating
Current

Drain Cutoff Current

-35
V

VGS = -15 V
V DS = 0 V

IG

ID(OFF)

0.005
T A =125°C

-5

V DS = 10 V, VGS = -10 V

0.005

VDS = 10 V, VGS = -10 V

ID = 4 rnA

-2

-7

15
-1

-1

-5

8
-1

rnA
-1

nA
pA

1

1

1
nA

3

I D =6.6mA 0.15
VGS = 0 V

VDS(ON)

-10

-3

V DG =15V,I D = 10 rnA

TA =125°C
Drain-Source
On-Voltage

-35

0.2

0.15

0.2

ID = 2.5 rnA 0.15

V

0.2

Drain-Source
On-Resistance

rDS(ON)

VGs=OV,I D = 1 rnA

Gate-Source
Forward Voltage

VGS(F)

I G = 1 rnA, V DS = 0 V

0.7

V

V DG = 10 V, ID = 1 rnA

6

mS

25

jJ.S

30

50

80

.n

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Drain-Source
On-Resistance
Common-Source
Input Capacitance
Common-Source
Reverse Transler
Caoacltance
Equivalent Input
Noise Voltage

gfs

1= 1 kHz

gas
rds(ON)

Vas = 0 V, ID = 0 V

C lss

V DS = 20 V, VGS = 0 V

Crss

VDS = 0 V, VGS = -20 V

en

V DG = 10 V, ID = 10 rnA

30

50

80

12

16

16

16

3.5

5

5

5

1= 1 kHz
1=1 MHz
f = 1 MHz
f = 1 kHz

.n

pF

3.0

%
'-'HZ

SWITCHING
Turn-on Time

td(ON)
tr

Turn-off Time

td(OFF)
tf

NOTES:

V DD = 5 V, VGS(ON) = 0 V

PIN
SST4091
SST4092
SST4093

ID(ON) VGS(OFF) RL
6.6 rnA -12 V 425.n
4mA -8 V 700.n
2.5 rnA -6 V 1120.n

2
2
6

ns

13

1. T A = 25 ° C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300JJ.S, duty cycle ~3%.

4-139

III

.-r-Siliconix

SST4391 SERIES

~ incorporated

N-Channel JFET

The SST4391 Series is the surface mount
equivalent of our popular 2N4391 device types. Its
low cost and rOS(on) make it a good choice for an

PART
NUMBER

ali-purpose analog switch, while its high g Is and
good high-frequency response also make this
product useful in a high-gain amplifier mode. Like
ali SOT-23 products available from Siliconix, tape
and reel capabilities exist for automated assembly.
(See Section 8.)

VaS(OFF)
MAX
(V)

tON
TYP
(ns)

rds(ON) IO(OFF)
TYP
MAX
(11)
(pA)

SST4391

-10

30

5

4

SST4392

-5

60

5

4

SST4393

-3

100

5

4

SOT-23

TOP VIEW

For further design information please consult the
typical performance curves NCB which are located
in Section 7.

2

3
1 GATE
2 DRAIN
3 SOURCE

SIMILAR PRODUCTS
•
•
•
•

PRODUCT MARKING

TO-18, See 2N4391 Series
TO-92 , See PN4391 Series
Duals, See 2N5564 Series
Chips, Order 2N439XCHP

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

SST4391

C91

SST4392

C92

SST4393

C93

= 25°C unless otherwise

noted)

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

Vao

-35

Gate-Source Voltage

Vas

-35

Gate Current

la

50

mA

Power Dissipation

Po

350

mW

2.8

mW/oC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-140

TJ

-55 to 150

T stg

-55 to 150

h

300

°C

SST4391 SERIES

.-r-Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST4391

TYp2

MIN

-55

-35

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)aSS

la = -1 ,lJ.A, V DS = 0 V

Gate-Source
Cutoff Voltage

VaS(OFF)

V DS = 15 V, ID = 10 nA

-4

Saturation Drain
Current 3

IDSS

V DS = 20 V, Vas = 0 V

50

Gate Reverse Current

lass

PARAMETER

MAX

SST4392
MIN

MAX

SST4393
MIN

MAX UNIT

STATIC

Gate Operating
Current

-35

-35

V

la

Vas = -5 V
V DS = 0 V

T A =125°C

V Da =15V,I D = 10 rnA

-10

-2

-5

25

-0.5

-3

5

rnA

-5

-100

-100

-100

pA

-3

-200

-200

-200

nA

5

100

100

100

3

200

200

200

0.3

0.4

-5
pA

V DS = 10
Drain Cutoff Current

ID(OFF)

V.

Vas = -10 V

V DS = 10 V. Vas = -10 V
T A =125°C
ID = 12 rnA

Drain-Source
On-Voltage

VDS(ON)

Vas = 0 V

ID = 6 rnA

0.3

ID = 3 rnA

0.25

0.4

nA

V
0.4

Drain-Source
On-Resistance

rDS(ON)

VGS=OV,I D = 1 rnA

Gate-Source
Forward Voltage

Vas (F)

I a = 1 rnA, V DS = 0 V

0.7

V

V Da =10V,I D =lmA
f = 1 kHz

6

mS

25

)J.S

30

60

100

.n

DYNAMIC
Common-Source
Forward
Transconductance

gls

Common-Source
Output Conductance

gas

Drain-Source
On-Resistance

rdS(ON)

Common-Source
Input Capacitance

C lss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

VGS = 0 V, I D = 0 rnA
f = 1 kHz

30

60

100

13

16

16

16

Vas = -12 V

3.5

5

Vas = -7 V

3.B

Vas = -5 V

4

V DS = 20 V, Vas = 0 V
f = 1 MHz

V DS = 0 V
f = 1 MHz

en

V Da = 10 V, ID = 10 rnA
f = 1 kHz

3.0

td(ON)

VDD = 10 V, VGS(ON) = 0 V
PIN
ID(ON) VGS(OFF) RL
SST4391 12 rnA -12 V BOO .n
SST4392
6mA
-7 V 1600.n
SST4393
-5 V 3200.n
3 rnA

2

.n

pF
5
5

~
VHz

SWITCHING
Turn-on Time
Turn-off Time

t,
td(OFF)
tl

2
6

ns

13

NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300,IJ.s, duty cycle ~3%.

4-141

..

.:r-Siliconix

SST4416

~ incorporated

N-Channel JFET

The SST4416 is the SOT-23 equivalent of our
popular PN4416 Series, designed to provide
high-performance amplification,
especially at
high-frequency. These parts feature low noise,
high gain, and provide a wide bandwidth.
To
support the needs of automated assembly
techniques these low cost devices are available
with tape and reel options. (See Section 8.)

VGS(OFF) V(BR)GSS
MIN
MAX
(V)
(V)

PART
NUMBER

-6

SST4416

For additional design information please see
performance curves NH, which are located in
Section 7.

4.5

15

TOP VIEW

X'

"':;:.:,,"
~
'~'.:.

•
•
•

loss
MAX
(mA)

9fs

-30

SOT-23

,

SIMILAR PRODUCTS

MIN
(mS)

3

'

2

TO-72 , See 2N4416
TO-92, See PN4416
Chips, Order PN4416CHP

1 SOURCE
2 DRAIN
3 GATE

PRODUCT MARKING

I

SST4416

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise

H16

noted)

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

VGD

-30

Gate-Source Voltage

VGS

-30

Gate Current

IG

10

mA

Power Dissipation

PD

350

mW

3.18

mW/DC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-142

TJ

-55 to 135

T stg

-65 to 150

TL

300

DC

SST4416

~Siliconix
incorporated

.LII

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST4416

TYp2

MIN

la = -1 J.lA, Vos = 0 V

-36

-30

Vas (OFF)

Vos = 15 V, 10 = 1 nA

-3

Saturation Drain
Current 3

loss

Vos = 15 V, Vas = 0 V

10

Gate Reverse Current

lass

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)aSS

Gate-Source
Cutoff Voltage

PARAMETER

MAX

UNIT

STATIC

Gate Operating
Current

V

IG

-6
5

-1

-0.002

VGS = -15 V
Vos = 0 V

I T A =125·C

Voa = 10 V, 10

= 1 rnA

15

-0.6

rnA
nA

-20
pA

Drain Cutoff Current

10(OFF)

Vos

= 10 V,

Drain-Source
On-Resistance

rOS(ON)

Vas

=0 V

Gate-Source
Forward Voltage

Vas (I)

Vas = -6 V

2

, 10 = 1 rnA

150

.n.

IG = 1 rnA, Vos = 0 V

0.7

V

DYNAMIC
Common-Source
Forward
Transconductance 3
Common-Source
Output Conductance 3

grs
gos

Common-Source
Input Capacitance

C 1ss

Common-Source
Reverse Transfer
Caoacltance

Crss

Common-Source
Output Capacitance

Coss

Equivalent Input
Noise Voltage
NOTES:

en

Vos=15V,Vas=OV
f = 1 kHz

Vos = 15 V, Vas = 0 V
f = 1 MHz

Vos

= 10 V,

VGS = 0 V
f = 100 Hz

7.5

mS

15

50

JJ,S

2.2

4

0.7

O.B

1

2

6

9

4.5

pF

%
VHz'

1. T A = 25·C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 JJ,S, duty cycle S 2 %.

4-143

..

.r-Siliconix

SST4859 SERIES

~ incorporated

N-Channel JFET

The SST4859 Series is the surface mount
equivalent of our 2N4859 device types. Its low cost
and

rOS(on)

make

it

a

good

choice

PART
NUMBER

for an

all-purpose analog switch, while its high gfs and
good frequency response also make this product
Like all
useful in a high-gain amplifier mode.
SOT-23 products available from Siliconix, tape and
reel capabilities exist for automated assembly.
(See Section 8.)

Vas (OFF)
MAX
(V)

rds(ON) IO(OFF)
MAX
TYP
(,0,)
(pA)

tON
TYP
(ns)

SST4859

-10

25

5

2

SST4860

-6

40

5

3

SST4861

-4

60

5

4

SOT-23

TOP VIEW

For further design information please consult the
typical performance curves NCB which are located

2

in Section 7.

3
1 GATE
2 DRAIN
3 SOURCE

SIMILAR PRODUCTS
•
•
•
•

TO-18,
TO-92,
Duals,
Chips,

PRODUCT MARKING

See 2N4859 Series
See PN4091 Series
See 2N5564 Series
Order 2N485XCHP Series

SST4859

C59

SST4860

C60

SST4861

C61

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

Vao

-30

Gate-Source Voltage

VGS

-30

Gate Current

IG

50

mA

Power Dissipation

Po

350

mW

2.8

mW/oC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-144

TJ

-55 to 150

T stg

-55 to 150

TL

300

°C

SST4859 SERIES

.rSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST4859

TYp2

MIN

-55

-30

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)GSS

I a = -1 .I.I.A, Vos = 0 V

Gate-Source
Cutoff Voltage

Vas (OFF)

Vos = 15 V, 10 = 10 nA

-4

Saturation Drain
Current 3

loss

Vos = 15 V. Vas = 0 V

50

Gate Reverse Current

lass

PARAMETER

MAX

SST4860
MIN

MAX

SST4861
MIN

MAX UNIT

STATIC

Gate Operating
Current

-30
V

la

V as =-15V
Vos = 0 V

10(OFF)

-0.005
ITA =125°C

Voa = 15 V. 10 = 10 rnA
Vos = 15

Drain Cutoff Current

-30

V.

Vas = -10 V

Vos = 15 V. Vas = -10 V
TA =125°C

Drain-Source
On-Resistance

rOS(ON)

Vas=OV, 10 = 1 rnA

Gate-Source
Forward Voltage

Vas (F)

I a = 1 rnA. Vos = 0 V

-10

-1

-2

-6

-0.6

-4

20

100

6

80

-1

-1

-3
-5
0.005

rnA
nA
pA

1

1

1
nA

3
25

40

60

.a

0.7

V

6

mS

25

JJ.S

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Drain-Source
On-Resistance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Caoacltance
Equivalent Input
Noise Voltage

gfs
gas
rds(ON)

VOG=20V.10=lmA
f = 1 kHz
Vas=OV,lo=OV
f = 1 kHz

C iss
Crss

en

25

40

60

.a

7
Vos = 0 V. Vas = -10 V
f = 1 MHz
Voa = 10 V, 10 = 10 rnA
f = 1 kHz

pF

3

~
-./Hz

3

SWITCHING
Turn-on Time
Turn-off Time

td(ON)
t,
td(OFF)
tf

NOTES:

Voo - 10 V, VaS(ON) = 0 V
PIN
10(oN) VGS(OFF) RL
SST4659 20 rnA -10 V 464.a
SST4860 lOrnA -6 V 953.a
SST4861
5mA -4 V 1910.a

2
2
ns

8
5

1. T A = 25°C unless otherwise noted.
2. For design aid only, not sublect to production testing.
3. Pulse test; PW =300.l.l.S. duty cycle :S3%.

4-145

..

.-r-Siliconix

SST5114 SERIES

~ incorporated

P-Channel JFETs

The SST5114 Series is a p-channel JFET analog
switch designed to complement our n-channel
SST4391 Series. They feature low on-resistance
and good off-isolation as well as the fast switching
associated with JFETs. They are housed in SOT-23
packages and are available tape and reeled to
support automated assembly. (See Section 8.)

PART
NUMBER

VaS(OFF)
MAX
(V)

rds(ON) IO(OFF)
MAX
MAX
(n)
(pA)

tON
MAX
(ns)

SST5114

10

75

-500

16

SST5115

6

100

-500

30

SST5116

4

150

-500

60

For additional design information please see
performance curves PSCIA, which are located in
Section 7.

SOT-23

TOP VIEW

,0

~
....

../."..-:

2
3

1 GATE
2 DRAIN
3 SOURCE

SIMILAR PRODUCTS
•
•
•

PRODUCT MARKING

TO-18, See 2N5114 Series
TO-92, See J 174 Series
Chips, Order 2N511XCHP

SST5114

S14

SST5115

S15

SST5116

S16

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

Vao

30

Gate-Source Voltage

Vas

30

Gate Current

la

50

mA

Power Dissipation

Po

350

mW

2.8

mW/DC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1116" from case for 10 seconds)

4-146

TJ

-55 to 150

T stg

-55 to 150

h

300

DC

SST5114 SERIES

wrSiliconix

~ incorporatE!d

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST5114

SYMBOL

TEST CONDITIONS

TYp2

Gate-Source
Breakdown Voltage

V(BR)GSS

I G = 1 JJ.A. VOS = 0 V

45

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = -15 V. 10= -1 nA

PARAMETER

MIN MAX

SST5115

SST5116

MIN MAX MIN

MAX UNIT

STATIC

loss

Gate Reverse
Current

lass

IG

Vos = -16 V
VGS = 0 V
VGS = 20 V
Vos = 0 V

10IOFF)
V os =-15V
T A =150 o C

5

10

-30

-90

VOS = -15 V
5
TA =150°C

VOG=-15V.10=-lmA

Vos = -15 V
Drain Cutoff
Current

30

30
V

Saturation Drain
Current 3

Gate Operating
Current

30

VGS = 7 V

-10

VGS = 5 V

-10

Vas = 12 V

-0.02

VGS = 7 V

-0.02

VGS = 5 V

-0.02

VGS = 0 V. 10 = -1 rnA

Gate-Source
Forward Voltage

VGS(F)

la=-lmA.Vos=OV

1

4

-15

-60

-5

-25

500

500

rnA
pA

.llA

5
-10

rOS(ON)

6

0.01

VGS = 12 V

Drain-Source
On-Resistance

500

3

-0.7

-500

pA
-500
-500

nA

75

100

150

.n.

-1

-1

-1

V

DYNAMIC
Common-Source
Forward
Transconductance

gts

Common-Source
Output Conductance

gas

Drain-Source
On-Resistance

rds(ON)

Common-Source
Input Capacitance

C lss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

VOG=-15V.lo=-1 rnA
f = 1 kHz

4.5

mS

20

JJ.S

VGS = 0 V. 10 = 0
f = 1 kHz

75

Vos = -15 V. Vas = 0 V
f = 1 MHz
VGS = 12 V
Vos = 0 V
f = 1 MHz

VGS
VGS

=7 V
=5 V

en

VOG = -10 V. 10 = -1 rnA
f = 1 kHz

td(ON)

VGS(ON) = 0 V
PIN
VOO 1010N) VGSIOFF) RL
SST5114 -10 V -15 rnA
20 V 130.0.
SST5115 -6 V -7 rnA
12 V 900.0.
SST5116 -6 V -3 rnA
BV 2000.0.

100

150

.n.

20
5

pF

6
6

'%
'11Hz'

20

SWITCHING
Turn-on Time
Turn-off Time

tr
tdIOFF)
tt

NOTES:

6

10

25

10

20

35

6

6

20

15

30

60

ns

1. T A = 25 °C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW = 300 JJ,S • duty cycle;!; 20/0 .

4-147

ICrSiliconix

SST5912

~ incorporated

N-Channel JFET Pair

The SST5912 is a monolithic pair of JFETs mounted
in a single SO-8 package. The SST5912 features
high speed amplification (slew rate). high gain

PART
NUMBER

(typically> 6 mS). and low gate leakage (typically
This performance makes these devices
perfect for use as wide band differential amplifiers in
demanding test and measurement applications.

SST5912

< 1 pA).

V(BR)GSS 9fs
MIN
MIN
(V)
(mS)
-25

5

IG IVGS1- VGS21
MAX
MAX
(mV)
(pA)
-100

15

Finally. its SO-8 package is available in tape and
reel to support automated assembly.
(See
Section 8.)
TOP VIEW

SO-8
For additional design information please see
performance curves NNZ. which are located in
Section 7.

SIMILAR PRODUCTS
•
•

TO-78. See M5911 Series
Low Noise. See SST404 Series

•

Chips. Order M5912CHP

ABSOLUTE MAXIMUM RATINGS (T A

= 25°C unless otherwise
SYMBOL

LIMIT

Gate-Drain Voltage

VGD

-25

Gate-Source Voltage

VGS

-25

Forward Gate Current

IG

50

PARAMETERS/TEST CONDITIONS

noted)
UNITS

V

Power Dissipation
Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-148

Per Side
Total
Per Side
Total

PD

300
500
2.4
4

TJ

-55 to 150

Tstg

-65 to 150

h

300

mA
mW
mW/oC

°C

g

SST5912

Siliconix

incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST5912
TYp2

MIN

IG = -1,1.lA, Vos = 0 V

-35

-25

VGS(OFF)

VOS = 10 V, 10 = 1 nA

-3.5

-1

-5

Saturation Drain
Current 3

loss

Vos = 10 V, V GS = 0 V

15

7

40

mA

Gate Reverse
Current

IGSS

-100

pA

-100

pA

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(8R)GSS

Gate-Source
Cutoff Voltage

PARAMETER

MAX

UNIT

STATIC

Gate Operating
Current
Gate-Source Voltage
Gate-Source
Forward Voltage

V

IG

V GS = -15 V
VOS = 0 V

-1

I

TA =125°C

-0.2

nA

-1

VOG = 10 V
10 = 5 mA

I

TA =125°C

-0.2

V GS

VOG = 10 V, 10 = 5 mA

-1.5

VGS(F)

IG = 1 mA, Vos = 0 V

0.7

VOG = 10 V, 10 = 5 mA
f = 1 kHz

6

nA
-0.3

-4
V

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Common-Source
Forward
Transconductance
Common-Source
Output Conductance

gls

gas

10

mS

100

JJ.S

10

mS

30

150

J.lS

3.5

5

1

1.2

20

gls

gas

5

VOG = 10 V, 10 = 5 mA
f = 100 MHz

6

5

Common-Source
Input Capacitance

C lss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

en

VOG=10V,10=5mA
f = 10 kHz

4

20

%
-1Hz

NF

V oG =10V,1 0 =5mA
f = 10 kHz, RG = 100 k.n

0.1

1

dB

Differential
Gate-Source Voltage

I VGS1-VGS21

V OG =10V, 10 =5mA

7

15

mV

Gate-Source Voltage
Differential Change
with Temperature

t.IVGS1-VGS21

T = -55 to 25°C

10

40

T = 25 to 125°C

10

40

~°C

Noise Figure

VOG = 10 V, 10 = 5 mA
f = 1 MHz

pF

MATCHING

t.T

Saturation
Drain Current Ratio

loss1
IOSS2

Transconductance
Ratio

gls1

Differential
Gate Current
Common Mode
Relection Ratio
NOTES:

VOG = 10 V
10 = 5 mA

I
I

Vos = 10 V, V GS = 0 V

0.98

0.95

1

V OG =10V,1 0 =5mA
f = 1 kHz

0.98

0.95

1

I' G1- I G21

VOG = 10 V, 10 = 5 mA
TA = 125°C

0.01

CMRR

Voo = 5 to 10 V, 10 = 5 mA

90

gls2

20

nA
dB

1. T A = 25 ° C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300J.ls, duty cycle :S3%.

4-149

~SilicDnix

SST6908 SERIES

~ incorporated

N-Channel JFET Circuits

The SST6908 Series is much more than a JFET.
The addition of back-to-back diodes effectively
clamps input "over-voltage" while a highperformance JFET provides an effective amplification stage. With the addition of a source resistor, a
complete common-source amplifier is created
which provides both low leakage and very low
noise. This performance is especially effective as a
small signal pre-amplifier as weU as impedance
matching between low and high impedance
sources. Finally, its SOT-143 package provides a
cost effective design solution and is available tape
and reeled to support automated assembly. (See
Section 8.)

PART
NUMBER

VGS(OFF) V(BR)GSS
MIN
MAX
(V)
(V)

loss
MAX
(mA)

100

2

9fs

-1.8

-30

SST6909

-2.3

-30

400

3.5

SST6910

-3.5

-30

1200

5

SST6908

TOP VIEW

SOT-143

~

2

~

For additional design information please see
performance curves NBB, which are located in
Section 7.

4
1
2
3
4

SIMILAR PRODUCTS
•
•

MIN
(J.LS)

TO-72 , See 2N6908 Series
Chips, Order 2N69XXCHP

3

GATE
DRAIN
SOURCE
DIODES (4TH)

PRODUCT MARKING
SST6908

B08

SST6909

B09

SST6910

B10

s

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

VGO

-30

Gate-Source Voltage

VGS

-30

Forward Gate Current

IG

10

mA

Power Dissipation

Po

350

mW

2.8

mW/oC

UNITS

V

Power Derating
Operating Junction Temperature

TJ

-55 to 150

Storage Temperature

Tstg

-55 to 150

Lead Temperature
(1/16" from case for 10 seconds)

h

300

4-150

°C

.HSiliconix
incorporated

SST6908 SERIES

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST690B

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -lJ.LA, Vos = 0 V
V G4 = 0 V

-50

-30

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 10 V, 10 = 1 nA
V G4 = 0 V

PARAMETER

MAX

SST6909
MIN

MAX

SST6910
MIN

MAX UNIT

STATIC

Saturation Drain
Current 3

loss

Gate Reverse Current

IGSS

Vos = 10 V, VGS = 0 V
V G4 = 0 V
VGS = -15 V
Vos = 0 V
ITA =125·C
VG4 = 0 V

-30

-30
V

-0.3

-l.B

-0.6

-2.3

-0.9

-3.5

0.05

2

0.2

3.5

0.6

5

rnA

-25

pA

-2

-25

-25

-1

nA

Gate Operating
Current

IG

VOG = 15 V, 10 = 50J.LA

-2

Forward Gate Diode
Current 4

IG4

V G4 = ± 100 mV

±1

±10

±10

± 10

VGS(F)

I G = ± 0.5 rnA , Vos = 0 V
V G4 = 0 V

± 0.7

± 1.2

± 1.2

± 1.2

V

4

mS
J,LS

Gate-Source
Forward Voltage

pA

DYNAMIC
Common-Source
Forward
Transconductance

gls

Common-Source
Output Conductance

gos

Common-Source
Input Capacitance

C lss

Common-Source
Reverse Transfer
Caoacltance
Equivalent Input
Noise Voltage
Noise Figure

Crss

en
NF

Vos = 15 V, VGS =
VG4 =

a V,

aV

0.1

3

0.4

3.5

1.2

f = 1 kHz

Vos = 10 V, VGS =

aV

VG4 = 0 V, f = 1 MHz
Vos = 10 V, VGS =
f = 10 Hz

aV

Vos = 15 V, VGS = 0 V, f = 1 kHz
RG=lM.n

50

75

100

3.2

5

5

5

1.5

2

2

2

12

25

25

25

%
VHz

0.1

1

1

1

dB

pF

NOTES: 1. T A = 25·C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300J.Ls, duty cycle :53%.
4. Forward diode current when a voltage Is applied between gate and fourth lead.

4-151

..

~Siliconix

SSTDPAD5 SERIES

~ incorporated

Dual Low-Leakage Pica-Amp Diodes

The SSTDPAD5 Series of extremely low-leakage
diodes provides
a superior alternative to
conventional diode technology when reverse
current (leakage) must be minimized. These
devices feature leakage currents ranging from
-5 pA (SSTDPAD5) to -100 pA (SSTDPAD100) to
support a wide range of applications. With two
diodes per package, the SSTDPAD5 Series is well
suited for use in applications such as input
Its SO-8
protection for operational amplifiers.
package allows designers to maximize circuit
performance while maintaining the objectives of low
cost and compact packaging. Tape and reel is
available for use with automated assembly
techniques. (See Section 8.)

TO-71/TO-78, See DPAD1 Series

•
•
•
•

TO-92 , See JPAD5 Series
SOT-23, See SSTPAD5 Series
TO-18, See PAD1 Series
Chips, Order DPADXXCHP

SSTDPAD5

-5

SSTDPAD10

-10

SSTDPAD20

-20

SSTDPAD50

-50

SSTDPAD100

-100

SO-8

TOP VIEW

1
2
3
4
5
6
7
8

SIMILAR PRODUCTS
•

IR
(pAl

PART NO.

CATHODE
CATHODE
ANODE 1
N/C
CATHODE
CATHODE
ANODE 2
N/C

1
1
2
2

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
SYMBOL

LIMIT

UNITS

Forward Current

IF

50

mA

Total Device Dissipation

PD

400

mW

Tstg

-55 to 125

h

300

PARAME1;ERS/TEST CONDITIONS

Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-152

°C

SSTDPAD5 SERIES

~Siliconix

,L;II im::crpcrated
ELECTRICAL CHARACTERISTICS 1

LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

MAX

UNIT

STATIC
-2

-5

-2

-10

SSTDPAD20

-5

-20

SSTDPAD50

-10

-50

SSTDPAD100

-10

SSTDPAD5
SSTDPAD10
Reverse Current

Reverse Breakdown Voltage

IR

V R = -20 V

pA

-100

BVR

IR=-l.uA

-50

VF

IF = 1 rnA

0.8

1.5

-30
V

Forward Voltage Drop
DYNAMIC
Reverse Capacitance

CR

V R = -5 V, f = 1 MHz

2

4

IC R1 - C R2 1

VRl =VR2 = -5 V, f = 1 MHz

0.1

0.5

pF
Differential Capacitance

NOTES: 1. T A = 25·C unless otherwise noted.
2. For design aid only, not subject to production testing.

..

.HSilicanix

SSTPAD5 SERIES

incorporated

Low-Leakage Pico-Amp Diodes

The SSTPAD5 Series of low-leakage diodes
provides a superior alternative to conventional
diode technology when reverse current (leakage)
must be minimized. These devices feature leakage
currents ranging from -5 pA (SSTPAD5) to -500 pA
(SSTPAD500) to support varying system requirements. Its SOT-23 package allows designers to
maximize circuit performance while maintaining the
objectives of low cost and compact packaging.
Tape and reel is available for use with automated
assembly techniques. (See Section 8.)

IR
(pA)

PART NO.
SSTPAD5

-5

SSTPAD10

-10

SSTPAD20

-20

SSTPAD50

-50

SSTPAD100

-100

SSTPAD200

-200

SSTPAD500

-500

SIMILAR PRODUCTS
•
•
•
•

TO-92, See JPAD5 Series
TO-18, See PAD1 Series
Duals, See SSTDPAD5 Series
Chips, Order PADXXCHP

TOP VIEW

SOT-23

PRODUCT MARKING
SSTPAD5

005

SSTPAD10

010

SSTPAD20

020

SSTPAD50

050

SSTPAD100

100

SSTPAD200

200

SSTPAD500

500

1 ANODE
2 CATHODE
3 CATHODE

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Forward Current

IF

10

mA

Total Device Dissipation

Po

350

mW

T stg

-55 to 150

TL

300

Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-154

°C

SSTPAD5 SERIES

.r-Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

MAX

UNIT

STATIC

Reverse Current

Reverse Breakdown Voltage

IR

V R = -20 V

SSTPADS

-1

-S

SSTPAD10

-2

-10

SSTPAD20

-4

-20

SSTPADSO

-S

-SO

SSTPAD100

-10

-100

SSTPAD200

-1S

-200

SSTPADSOO

-2S

pA

-SOO

BVR

IR = -1 Jl.A

-60

VF

IF = S rnA

0.8

1.S

CR

VR = -S V, f = 1 MHz

1.S

2

-3S
V

Forward Voltage Drop

DYNAMIC
Reverse Capacitance

pF

NOTES: 1. T A = 2S 0 C unless otherwise noted.
2. For design aid only, not subject to production testing.

4-155

~Siliconix

U290 SERIES

~ incorporated

N-Channel JFET

The U290 Series is a high-performance JFET analog
switch which offers ultra low on-resistance and fast
It features the lowest available
switching.
on-resistance of any JFET available in the industry
It is packaged in a hermetically sealed
today.
TO-52 can which makes it suitable for military
applications. (See Section 1 for details.)

PART
NUMBER

VGS(OFF)
MAX
(V)

rds(ON) IO(OFF)
MAX
MAX
(a)
(nA)

tON
MAX
(ns)

U290

-10

3

1

35

U291

-4.5

7

1

35

For further design information please consult the
typical performance curves NVA which are located
in Section 7.

TO-206AC (TO-52)

BOTTOM VIEW

SIMILAR PRODUCTS
•
•

TO-92, See J 105 Series
Chips, Order U29XCHP

1 SOURCE
2 DRAIN
3 GATE

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
SYMBOL

LIMIT

Gate-Drain Voltage

VGO

-30

Gate-Source Voltage

VGS

-30

Gate Current

IG

100

mA

Power Dissipation

Po

500

mW

4.0

mW/oC

PARAMETERS/TEST CONDITIONS

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-156

TJ

-55 to 150

T stg

-65 to 200

TL

300

°C

.HSiliconix

U290 SERIES

incorporated

LIMITS

ELECTRICAL CHARACTERISTICS I

U291

U290
PARAMETER

TEST CONDITIONS

SYMBOL

TYp2

MIN

-35

-30

MAX

MIN

MAX

UNIT

STATIC
Gate-Source
Breakdown Voltage

V(BR)aSS

la

Gate-Source
Cutoff Voltage

Vas (OFF)

V DS

~

15 V, ID

Saturation Drain
Current 3

IDSS

V DS

~

10 V, Vas

Gate Reverse Current

lass

Gate Operating
Current

-I J.l.A, V DS

~

~

0V

-30
V

Vas
V DS

~

-15 V
0V

~

I

-4

3 nA
~

0V

-10

500

TA~150°C

~25mA

V Da =10V, ID

la

~

-1.5

-4.5

200

mA

-0.02

-I

-I

nA

-0.04

-I

-I

J.l.A

0.01

I

I

0.02

1

I

J.l.A

30

70

mV

3

7

.0.

-0.01
nA

Drain Cutoff Current

V DS

~

V DS

~

ID(OFF)

5 V, Vas

~

-10 V

5 V. Vas

~

-10 V

TA~150°C

Drain-Source
On-Voltage

VDS(ON)

Drain-Source
On-Resistance

rDS(ON)

Gate-Source
Forward Voltage

VaS(F)

~

Vas

la~

0 V, ID

~

10 mA

I mA, V DS

~

OV

0.7

V

55

mS

5

J.LS

DYNAMIC
Common-Source
Forward
Transconductance

gl.

Common-Source
Output Conductance

gas

Drain-Source
On-Resistance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Caoacltance
Equivalent Input
Noise Voltage

V Da

~

Vas

rds(ON)

10 V, ID ~ 25 mA
f ~ I kHz
~

f

0 V, I D
I kHz

~

0 mA

~

3

7

Cis.

V DS

~

0 V, Vas ~ 0 V
f ~ I MHz

120

160

160

Crss

V DS

~

0 V, Vas ~ -15 V
f ~ I MHz

20

30

30

pF

VDa~10V, ID~25mA
f ~ I kHz

en

.0.

~
"HZ

3

SWITCHING
td(ON)
Turn-on Time
Turn-off Time

VDD ~ 1.5 V, Vas (ON) ~ 0 V

t,

PIN

ID(ON)

Vas (OFF)

td(OFF)

U290
U291

30 mA
30 mA

-12 V
-7 V

tf

RL
50n
50n

6

15

15

8
5

20

20

15

15

9

20

20

ns

NOTES: 1. T A ~ 25 °C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW ~ 300J.l.s, duty cycle $3%.

4-157

..

~Siliconix

U30S SERIES

~ incorporated

N-Channel JFETs

The U308 Series offers superb amplification
characteristics. High-gain (> 10,000 J..I.S), low noise
(typically < 6 nVVR'Z) and low gate leakage
(typically < 2 pAl are features of this series. Of
special interest, however, is performance at high
frequency. Even at 450 MHz, the U308 Series
offers high power gain and low noise. Finally, with
its TO-52 hermetically sealed package, full military
processing is available. (See Section 1.)

PART
NUMBER

VGS(OFF) V(BR)GSS
MIN
MAX
(V)
(V)

loss
MAX
(mA)

U308

-6

-25

10

60

U30S

-4

-25

10

30

U310

-6

-25

10

60

BOTTOM VIEW

TO-206AC (TO-52)

For additional design information and a closer look
at high-frequency characteristics, please consult
performance curves NZB which are located in
Section 7.

9fs

MIN
(mS)

SIMILAR PRODUCTS
•
•
•
•

1 SOURCE
2 DRAIN
3 GATE

TO-S2, See J308 Series
SOT-23, See SST308 Series
Dual, See U430 Series
Chips, Order U30XCHP

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

VGO

-25

Gate-Source Voltage

VGS

-25

Gate Current

IG

20

mA

Power Dissipation

PD

500

mW

4

mWloC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-158

TJ

-55 to 150

T stg

-65 to 175

TL

300

°C

U308 SERIES

.-:r-Siliconix

.L1'

inr:orporatE,d

ELECTRICAL CHARACTERISTICS 1

LIMITS
U309

U30B

U310

SYMBOL

TEST CONDITIONS

TYp2

Gate-Source
Breakdown Voltage

V(SR)GSS

I G = -1 JlA, VDS = 0 V

-35

Gate-Source
Cutoff Voltage

VGS(OFF)

VDS = 10 V, ID = 1 nA

-1

-6

-1

-4

-2.5

-6

Saturation Drain
Current 3

IDSS

VDS = 10 V, V GS = 0 V

12

60

12

30

24

60

mA

Gate Reverse Current

IGSS

V Gs =-15V
VDS = 0 V

PARAMETER

MIN

-25

MAX

MIN

MAX

MIN

MAX UNIT

STATIC
-25

-25
V

T A =125°C

-2

-150

-150

-150

pA

-0.8

-150

-150

-150

nA

Gate Operating
Current

IG

V DG = 9 V, ID = 10 mA

-15

pA

Drain-Source
On-Resistance

rDS(ON)

V GS = 0 V, I D = 1 mA

35

.n

VGS(F)

I G = 10 mA, VDS = 0 V

0.7

VDS = 10 V, ID = 10 mA

14

Gate-Source
Forward Voltage

1

1

1

V

DYNAMIC
Common-Source

Forward
Transconductance

gls

Common-Source
Output Conductance

gas

Common-Source
Input Capacitance

C 1ss

Common-Source
Reverse Transfer
Capacitance

erss

Equivalent Input
Noise Voltage

en

10

10

10

mS

f = 1 kHz

V GS = -10 V, VDS = 10 V
f = 1 MHz
V DS =10V, ID =10mA

110

250

250

250

4

5

5

5

1.9

2.5

2.5

2.5

JlS

pF

%
VHz

6

f - 100 Hz

HIGH FREQUENCY
Common-Gate Foward
Transconductance

f = 105 MHz

gIg

15

f = 450 MHz

13

f = 105 MHz

0.16

f = 450 MHz

0.55

mS
Common-Gate Output
Conductance
Common-Gate Power
Gain4

gog

G pg

VDS = 10 V
I D =10mA

f= 105 MHz

16

14

14

f = 450 MHz

11.5

10

10

14

f = 105 MHz

1.5

2

2

2

f = 450 MHz

2.7

3.5

3.5

3.5

10
dB

Noise Figure

NOTES:

1.
2.
3.
4.

NF

T A = 25°C
For design
Pulse test;
Gain (G pg)

unless otherwise noted.
aid only, not subject to production testing.
PW =300Jls, duty cycle :53%.
measured at optimum input noise match.

4-159

H

U350

Silicanix

incorporated

N-Channel JFET Ring Demodulator

The U350 is a set of four matched n-channel JFETs
connected as a ring demodulator. The matched
set of JFETs has low rOS(ON), high g fs, and square
law operation which gives high conversion gain and
a very high intermodulation intercept point. Best
device performance is in the HF-VHF frequency
range. The hermetic TO-99 package shields the die
set as well as lending itself to military processing.

PART
NUMBER
U350

V(BR)GSS gfs
MIN
MIN
(V)
(mS)
-25

10

IGSS
MAX
(nA)

NF
TYP
(dB)

-1

7

BOTTOM VIEW

TO-99 (TO-78)

1 GATE 1, GATE 3
2 DRAIN 1, DRAIN 4
3 SOURCE 1, SOURCE 2
4 GND & CASE
5 SOURCE 3, SOURCE 4
6 DRAIN 2, DRAIN 3
7 GATE 2, GATE 4

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise noted)
SYMBOL

LIMIT

Gate-Drain Voltage

VGO

-25

Gate-Source Voltage

VGS

-25

Forward Gate Current

IG

25

mA

Power Dissipation

Po

1

W

8

mW/DC

UNITS

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-160

TJ

-55 to 150

T stg

-65 to 150

TL

300

DC

.rSiliconix

U350

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
U350

PARAMETER

TYp2

SYMBOL

TEST CONDITIONS

MIN

MAX

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -1.I1A, V DS = 0 V

-35

-25

Gate-Source
Cutoff Voltage 4

VGS(OFF)

V DS = 10 V, ID = 1 nA

-3

-2

-6

Saturation Drain
Current3, 4

I DSS

V DS = 15 V, V GS = 0 V

45

24

60

Gate Reverse
Current 4

IGSS

UNIT

STATIC

Gate-Source
Forward Vo(tage 4

V

VGS(F)

V GS = -15 V
V DS = 0 V

I TA =125·C

IG = 1 rnA, V DS = 0 V

rnA

-0.002

-1

nA

-0.001

-1

.I1A

0.7

1

V

18

mS

DYNAMIC
Common-Source
Forward
Transconductance 4
Common-Source
Output Conductance 4

gls

15

10

gos

V DS = 10 V, ID = 10 rnA
f = 1 kHz

100

150

.us

rDS(ON)

V GS = 0 V, ID = 0 rnA, f = 1kHz

33

90

.n

Common-Source
Input Capacitance

Cgs

V GS = -10 V, ID = 0 rnA
f = 1 MHz

4

5

Common-Source
Reverse Transfer
Capacitance

Cgd

V GD =-10V, Is =OmA
f = 1 MHz

2

2.5

Conversion Gain

Go

Noise Figure

NF

VDS = 20 V, VGS = "2 VGS(OFF)
f = 100 MHz, R L = 1700 .n
See Figure 1

Drain-Source
On-Resistance

Intercept Point

pF

4
dB
7
33

dBm

MATCHING
Saturation Drain
Current Ratl0 3

IDSS
IDSS

Transconductance
Ratio

.!!k

Output Conductance Ratio
Gate-Source Cutoff
Voltage Ratio

gls

Jl=

gos
VGS(OFF)
VGS(OFF)

V DS = 15 V, V GS = 0 V

V DS = 15 V, ID = 10 rnA
f = 1 kHz

V DS = 15 V, ID = 1 nA

0.95

0.9

1

0.95

0.9

1

0.95

0.9

1

0.95

0.9

1

NOTES:
1. T A = 25 ·C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300)J.s, duty cycle S 3%.
4. Other gate terminal clamped to -8 V.

;4ii~IF
1111

~+-~~~~--~

Figure 1

[1C:~~~ LOCAL OSC
4-161

III

~SilicDnix

U401 SERIES

~ incorporated

N-Channel JFETs

The U401 Series of high-performance monolithic
dual JFETs features extremely low noise, tight
offset voltage and drift over temperature
specifications. It is targeted for use in a wide range
of precision instrumentation applications. The U401
Series has a wide selection of both offset and drift
specifications with the prime device, the U401,
featuring 5 mV offset and 10 fJ.V/oC drift. The six
devices allow designers to make important
cost/benefit decisions. This series is available in a
TO-?1 hermetically sealed package and is available
with military screening. (See Section 1.)

PART
NUMBER
U401

-50

2

-15

5

-50

2

-15

10

U403

-50

2

-15

10

U404

-50

2

-15

15

U405

-50

2

-15

20

U406

-50

2

-15

40

BOTTOM VIEW

TO-?1

SIMILAR PRODUCTS

1
2
3
4
5
6

High-Gain, See 2N5911 Series
SO-8, See SST404 Series
Chips, Order U40XCHP

ABSOLUTE MAXIMUM RATINGS (T A

SOURCE 1
DRAIN 1
GATE 1
SOURCE 2
DRAIN 2
GATE 2

= 25 DC unless otherwise noted)
SYMBOL

LIMIT

Gate-Drain Voltage

VGD

-50

Gate-Source Voltage

VGS

-50

Forward Gate Current

IG

10

PARAMETERS/TEST CONDITIONS

IG IVGS,- VGS21
MAX
MAX
(pA)
(mV)

U402

For additional design information please see
performance curves NNR, which are located in
Section ?

•
•
•

V(BR)GSS 9fs
MIN
MIN
(V)
(mS)

UNITS

V

Power Dissipation
Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/1 6" from case for 10 seconds)

4-162

Per Side
Total
Per Side
Total

PD

300
500
2.4
4

TJ

-55 to 150

Tstg

-65 to 200

lL

300

mA
mW
mW/oC

°c

U401 SERIES

.rSiliconix

.L;II incorporated
ELECTRICAL CHARACTERISTICS 1

LIMITS
U401

U403

U402

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

I G =-lJJ.A,VDS =OV

-56

-50

-50

-50

Gate-Gate
Breakdown Voltage

V(BR)G1 - G2

I G = ± 1 JJ.A, V DS = 0 V
V GS = 0 V

-56

±50

±50

±50

VGS(OFF)

V DS = 15 V, ID = 1 nA

-1.5

-0.5

-2.5

-0.5

-2.5

-0.5

-2.5

Saturation Drain 3
Current

loss

Vos = 10 V, V GS = 0 V

3.5

0.5

10

0.5

10

0.5

10

mA

Gate Reverse
Current

IGSS

-25

-25

pA

pA
nA

PARAMETER

MAX

MIN

MAX

MIN

MAX UNIT

STATIC

Gate-Source
Cutoff Voltage

Gate Operating
Current
Drain-Source
On-Resistance
Gate-Source Voltage

IG
rDS(ON)
V GS

V GS = -30 V
V DS = 0 V
V DG = 15 V
I D = 200 M

-2
I T A =125°C

IT

A

=125°C

-25

V

-1

nA

-2

-15

-15

-15

-0.6

-10

-10

-10

VGs=OV, 10 =0.1 mA

250

V DG = 15 V, I D = 200 M

-1

.0.
-2.3

-2.3

-2.3
V

Gate-Source
Forward Voltage

VGS(F)

I G =lmA,VDS =OV

0.7

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Common-Source
Forward
Transconductance
Common-Source
Output Conductance

gts
gas
gts

V DS = 10 V, V GS = 0 V
f = 1 kHz

1.5

1

1.3
4

2

1

2
2

7

2

1

2
2

7

2

2

mS

2

jJ.S

7

mS
jJ.S

5

20

20

20

4

6

6

6

1.5

3

3

3

10

20

20

20

%
"Hz

5

10

10

mV

vi T = -55 to 25°C

10

10

25

"'T

10= 200 MI T = 25 to 1250C

10

10

25

7.c

CMRR

VOG = 10 to 20 V, ID= 200M

gas

Common-Source
Input Capacitance

C 1ss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

VOG = 15 V, 10= 200M
f = 1 kHz

V DG = 15 V, ID= 200M
f = 1 MHz

en

V DG = 15 V, ID = 200 M
f = 10 Hz

Differential
Gate-Source Voltage

I VGS1-VGS21

V DG = 10 V, ID = 200 M

Gate-Source Voltage
Differential Change
with Temperature

'" IVGS1-VGS2 I

pF

MATCHING

Common Mode
Rejection Ratio
NOTES:

V DG = 10

102

95

95

95

dB

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300JJ.s, duty cycle :S3%.

4-163

-

U401 SERIES

~SilicDnix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
U404

U405

U406

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -lP,A, VOS = 0 V

-58

-50

-50

-50

Gate-Gate
Breakdown Voltage

V(BR)G1 - G2

I G = ± 1 P,A, Vos = 0 V
V GS = 0 V

-58

±50

±50

±50

VGS(OFF)

Vos = 15 V, 10 = 1 nA

-1.5

-0.5

-2.5

-0.5

-2.5

-0.5

-2.5

Saturation Drain 3
Current

loss

Vos = 10 V, VGS = 0 V

3.5

0.5

10

0.5

10

0.5

10

rnA

Gate Reverse
Current

IGSS

-25

pA

PARAMETER

MAX

MIN

MAX

MIN

MAX UNIT

STATIC

Gate-Source
Cutoff Voltage

Gate Operating
Current
Drain-Source
On-Resistance
Gate-Source Voltage
Gate-Source
Forward Voltage

IG
rOS(ON)
V GS

V GS = -30 V
Vos = 0 V
VOG = 15 V
10= 200 M

-2

-25

-25

V

I TA =125°C

-1
-2

-15

-15

-15

pA

I T A =125°C

-0.8

-10

-10

-10

nA

V Gs =OV,l o =O.l rnA

250

VOG = 15 V, 10 = 200 M

-1

nA

.0.
-2.3

-2.3

-2.3
V

VGS(F)

I G = 1 rnA, Vos = 0 V

0.7

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance

gls
gas

Common-Source
Forward
Transconductance
Common-Source
Output Conductance

gas

Common-Source
Input Capacitance

C lss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

VOG = 15 V, 10= 200M
f = 1 kHz

gfs

en

Vos = 10 V, V GS = 0 V
f = 1 kHz

VOG = 15 V, 10 = 200 M
f = 1 MHz
VOG = 15 V, 10= 200M
f = 10 Hz

1.5

1

1.3
4

2

1

2
2

7

2

1

2
2

7

2

2

mS

2

.lIS

7

mS

.lIS

5

20

20

20

4

8

8

8

1.5

3

3

3

10

20

20

20

%
"HZ

15

20

40

mV

25

40

80

25

40

80

7ac

pF

MATCHING
Differential
I VGS1-VGS21
Gate-Source Voltage

VOG = 10 V, 10 = 200 M

vi

Gate-Source Voltage "'IVGS1-VGS21 VOG = 10
T = -55 to 25°C
Differential Change
with Temperature
10 = 200 MLT = 25 to 125°C
"'T
Common Mode
VOG = 10 to 20 V, 10= 200M
CMRR
Rejection Ratio
NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to' production testing.
3. Pulse test; PW = 300p,s, duty cycle :53%.

4-1,64

102

95

90

dB

U421 SERIES

~Siliconix
incorporated

.LII

N-Channel JFET Pairs

The U421 Series are monolithic pairs of n-channel
JFETs designed to provide very high input
impedance for differential amplification and
impedance matching.
Among its many unique
features, this series offers operating gate current
specified at -250 fA (U421-3), high gain at low
operating currents, and tight matching (10 mV for
U421 and U424). Additionally, its TO-78 package is
hermetically sealed and may be screened per
MIL-S-19500. (See Section 1.)

PART
NUMBER

For additional design information please see
performance curves NNT, which are located in
Section 7.

V(BR)GSS 9fs
MIN
MIN
(mS)
(V)

IG IVGS1- VGS21
MAX
MAX
(pA)
(mV)

U421

-40

0.3

-0.25

U422

-40

0.3

-0.25

15

U423

-40

0.3

-0.25

25

U424

-40

0.3

-0.5

10

U425

-40

0.3

-0.5

15

U426

-40

0.3

-0.5

25

TO-78

10

BOTTOM VIEW

SIMILAR PRODUCTS
o
o
"

Low-Noise, See U401 Series
High-Gain, See 2N5911 Series
Chips, Order U42XCHP

1
2
3
4
5
6
7

SOURCE 1
DRAIN 1
GATE 1
CASE
SOURCE 2
DRAIN 2
GATE 2

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

VGO

-40

Gate-Source Voltage

VGS

-40

Gate-Gate Voltage

VGG

± 40

IG

Forward Gate Current
Power Dissipation
Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

Per Side
Total
Per Side
Total

Po

10
400
750
3.2
6

TJ

-55 to 150

T stg

-65 to 150

h

300

UNITS

V

mA
mW
mW/oC

°C

4-165

a':r'Siliconix

U421 SERIES

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
U422

U421

U423

SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -1JlA, Vos = 0 V

-60

-40

-40

-40

Gate-Gate
Breakdown Voltage

VGG

IG = -tJ.lA, 10 = 0, Is = 0

±55

±40

±40

±40

Vos = 10 V, 10 = 1 nA

-1.2

-0.4

-2

-0.4

-2

-0.4

-2

Vos = 10 V, VGS = 0 V

400

60

1000

60

1000

60

1000

JJ,A

PARAMETER

MAX

MIN

MAX

MIN

MAX UNIT

STATIC

Gate-Source
Cutoff Voltage

VGS(OFF)

Saturation Drain
Current 3

loss

Gate Reverse
Current

IGSS

V GS = -20 V
VOS = 0 V

I TA =125°C

-0.6

-1

-1

-1

pA

-0.3

-1

-1

-1

nA

-0.2

-0.25

-0.25

-0.25

-150

-250

-250

-250

Gate Operating
Current

IG

Drain-Source
On-Resistance

rOS(ON)

VGs=OV,l o = 10JJ,A

2000

V GS

VOG = 10 V, 10 = 30JJ,A

-O.B

VGS(F)

IG = 1 mA, VOS = 0 V

0.7

Gate-Source Voltage

VOG = 10 V
10 = 30jIA

I TA =125°C

V

pA

.0.
-1.B

-1.B

-1.B
V

Gate-Source
Forward Voltage

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Common-Source
Forward
Transconductance
Common-Source
Output Conductance

gls
gas
gls

VOS = 10 V, VGS = 0 V
f = 1 kHz

VOG = 10 V, 10 = 30jIA
f = 1 kHz

gas

0.6

0.3

4
0.2

1.5

0.3

0.35

0.3

10

10
0.12

1.5

0.12

0.35

0.12

1.5

mS

10

Jl,S

0.35

mS
Jl,S

004

3

3

3

1.4

3

3

3

0.7

1.5

1.5

1.5

30

70

70

70

%
VHz

Common-Source
Input Capacitance

C lss

Common-Source
Reverse Transfer
Capacitance

Crss

Vos = 10 V, V GS = 0 V
f = 1 MHz

en

VOG = 10 V, 10 = 30JJ,A
f = 10 Hz

NF

VOG = 10 V, 10 = 30jIA
f = 10 Hz , RG = 10 M.o.

1

1

1

dB

VOG = 10 V, 10 = 30JJ,A

10

15

25

mV

10

25

40

10

25

40

1.:

Equivalent Input
Noise Voltage
Noise Figure

pF

MATCHING
Differential
I VGS1-VGS21
Gate-Source Voltage

vi

Gate-Source Voltage
VOG = 10
T = -55 to 25°C
Differential Change f'IVGS1-VGS21
10= 30jlAi T = 25 to 1250C
with Temperature
liT
Common Mode
Rejection Ratio

CMRR

V oG =10t020V,1 0 =30jIA

NOTES: 1. T A = 25 ° C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300jls, duty cycle S3%.

4-166

102

90

80

80

°C

dB

U421 SERIES

.:r-Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
U424

PARAMETER

SYMBOL

U426

U425

TYp2

MIN

I G = -1 J.lA, Vos = 0 V

-60

-40

-40

-40

I G =-lJ.lA, 10 =0, Is=O

±55

±40

±40

±40

Vos = 10 V, 10 = 1 nA

-2

-0.4

-3

-0.4

-3

-0.4

-3

VOS = 10 V, VGS = 0 V

800

60

1800

60

1800

60

1800

TEST CONDITIONS

MAX

MIN

MAX

MIN

MAX UNIT

STATIC
Gate-Source
Breakdown Voltage

V(BR)GSS

Gate-Gate
Breakdown Voltage

VGG

Gate-Source
Cutoff Voltage

VGS(OFF)

Saturation Drain
Current 3

loss

Gate Reverse
Current

IGSS

VGS = -20 V
Vos = 0 V
V OG =10V
10 = 30M

IT

A

=125°C

-3

-3

-3

pA

-0.4

-3

-3

-3

nA

-0.3

-0.5

-0.5

-0.5

-200

-500

-500

-500

IG

Drain-Source
On-Resistance

rOS(ON)

VGS = 0 V, 10 = 10M

2000

VGS

V OG =10V,10=30M

-1.5

VGS(F)

IG = 1 mA, Vos = 0 V

0.7

Gate-Source Voltage

M

-0.8

Gate Operating
Current

I T A =125°C

V

pA

.n
-2.9

-2.9

-2.9
V

Gate-Source
Forward Voltage

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance

gls
gas

Vos = 10 V, VGS = 0 V
f = 1 kHz

Common-Source
Forward
Transconductance
Common-Source
Output Conductance

gas

Common-Source
Input Capacitance

C lss

Common-Source
Reverse Transfer
Capacitance

Crss

Vos = 10 V, VGS = 0 V
f = 1 MHz

en

VOG = 10 V, 10 = 30M
f = 10 Hz

NF

Equivalent Input
Noise Voltage
Noise Figure

gls

V oG =10V,1 0 =30M
f = 1 kHz

0.6

0.3

4
0.2

1.5

0.3

10
0.12

0.35

1.5

0.3

10
0.12

0.35

0.12

1.5

mS

10

JiS

0.35

mS
JiS

0.4

3

3

3

1.4

3

3

3

0.7

1.5

1.5

1.5

30

70

70

70

%
VHz

VOG = 10 V, 10 = 30 M
f = 10Hz, R G = 10 M.n

1

1

1

dB

V OG =10V,1 0 =30M

10

15

25

mV

T = -55 to 25°C

10

25

40

loT

10= 30 MI T = 25 to 1250C

10

25

40

~°C

CMRR

VOG = 10 to 20 V, 10 = 30M

pF

MATCHING
Differential
I VGS1-VGS21
Gate-Source Voltage
Gate-Source Voltage
Differential Change
with Temperature
Common Mode
Rejection Ratio
NOTES:

fA IVGS1-V GS21

VOG = 10

vi

100

90

80

80

dB

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 J.lS , duty cycle S 3 %.

4-167

~Siliconix

U430 SERIES

~ incorporated

N-Channel JFET Pairs

The U430 Series are pairs of matched JFETs
assembled in one TO-78 package. They feature
high gain, low noise and low gate leakage and are
intended for high performance, high slew rate,
mixing and differential amplification. Additionally,
these devices offer good power gain even as
frequencies are increased beyond 250 MHz. The
TO-78 package may be processed for military
applications. (See Section 1.)

PART
NUMBER

V(BR) ass 9fs
MIN
MIN
(V)
(mS)

la IVasl-Vas21
TYP
TYP
(pA)
(mV)

U430

-25

10

-15

25

U431

-25

10

-15

25

BOTTOM VIEW

TO-78

For additional design information please consult
performance curves NZB which are located in
Section 7.

1
2
3
4
5
6
7

SIMILAR PRODUCTS
•
•
•
•

Low-Noise, See U401 Series
High-Gain, See 2N5911 Series
Low-Leakage, See U421 Series
Chips, Order U43XCHP

ABSOLUTE MAXIMUM RATINGS (TA

SOURCE 1
GATE 1
DRAIN 1
CASE
DRAIN 2
GATE 2
SOURCE 2

= 25°C unless otherwise
SYMBOL

LIMIT

Gate-Drain Voltage

Vao

-25

Gate-Source Voltage

Vas

-25

la

10

PARAMETERS/TEST CONDITIONS

noted)
UNITS

V

Forward Current
Power Dissipation
Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-168

Per Side
Total
Per Side
Total

Po

300
500
2.4
4

TJ

-55 to 150

T stg

-65 to 200

h

300

mA
mW
mW/oC

°C

U430 SERIES

fCrSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
U430

U431

SYMBOL

TEST CONDITIONS

Typ2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

I G =-l.1lA,VDS =OV

-35

-25

Gate-Source
Cutoff Voltage

VGS(OFF)

V DS = 10 V, ID = 1 nA

-1

-4

-2

-6

Saturation Drain
Current 3

IDSS

V DS = 10 V, V GS = 0 V

12

30

24

60

rnA

Gate Reverse
Current

IGSS

PARAMETER

MAX

MIN

MAX

UNIT

STATIC

Gate Operating
Current
Gate-Source
Forward Voltage

-25
V

IG

VGS(F)

V GS = -15 V
V DS = 0 V
V DG = 10 V
ID = 5 rnA

I TA =150·C
I TA =150·C

IG = 10 rnA, V DS = 0 V

-5

-150

-150

pA

-10

-150

-150

nA

-15

pA

-10

nA

0,8

1

1

V

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance

g,s

15

10

10

mS

V DS = 10 V, ID = 10 rnA
gos

Common-Source
Input Capacitance

C iss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

en

f = 1 kHz

V GS = -10 V, V DS = 0 V
f = 1 MHz

VDS = 10 V, ID = 10 rnA
f = 100 Hz

100

250

250

4,5

5

5

2

2.5

2.5

.IlS
pF

~
"Hz

6

HIGH FREQUENCY
Common-Source Forward
Transconductance

g,s

Common-Source Output
Conductance

gos

Power-Match Source
Admittance

g,g

14
VDS = 10 V, ID = 10 rnA
f = 100 MHz

0.13

mS

12

MATCHING
Differential
Gate-Source Voltage
Saturation Drain 4
Current Ratio

I VGS1-VGS21

VDG = 10 V, ID = 10 rnA

25

IDSS1
IDSS2

V DS = 10 V, V GS = 0 V

0.95

0.9

1

0.9

1

Transconductance 4
Ratio

g'sl
g's2

V DS = 10 V, ID = 10 rnA
f = 1 kHz

0.95

0.9

1

0.9

1

Gate-Source Cutoff
Voltage Ratio

VGS (OFF)l
VGS (OFF)2

V DS = 10 V, ID = 1 nA

0.95

0.9

1

0.9

1

Differential
Gate Current

I'G1- 1G21

VDG=10V,I D =5mA

-2

pA

CMRR

V DD = 5 to 10 V, I D = lOrnA

75

dB

Common Mode
Rejection Ratio
NOTES:

1.
2.
3.
4.

mV

T A = 25· C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 300.lls, duty cycle S3%.
Assumes smaller value In the numerator.

4-169

III

.:r-Siliconix

U440 SERIES

~ incorporated

N-Channel JFET Pairs

The U440 Series are matched pairs of JFETs
mounted in a single TO-71 package'. This two chip
design reduces parasitic performance at high
frequency while ensuring extremely tight matching.
The U440 features high speed amplification (slew
rate), high gain (typically> 6 mS), and low gate
leakage (typically < 1 pA).
This performance
makes these devices perfect for use as wideband
differential amplifiers in demanding test and
measurement applications.
Finally, its TO-71
hermetically sealed package is available with
military screening per MIL-S-19500.
(See
Section 1.)

PART
NUMBER

V(BR)GSS 9fs
MIN
MIN
(mS)
(V)

IG IVGS1- VGS21
MAX
MAX
(pA)
(mV)

U440

-25

4.5

-500

10

U441

-25

4.5

-500

20

BOTTOM VIEW

TO-71

For additional design information please see
performance curves NZF, which are located in
Section 7.
1
2
3
4
5
6

SIMILAR PRODUCTS
•
•
•
•
•

TO-78, See U443 Series
SO-8, See SST440 Series
Low Noise, See U401 Series
Low Leakage, See U421 Series
Chips, Order U44XCHP

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

SOURCE 1
DRAIN 1
GATE 1
SOURCE 2
DRAIN 2
GATE 2

= 25°C unless otherwise
SYMBOL

LIMIT

Gate-Drain Voltage

VGD

-25

Gate-Source Voltage

VGS

-25

Gate-Gate Voltage

VGG

± 50

IG

50

Gate Current
Power Dissipation
Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/1 6" from case for 10 seconds)
4-170

Per Side
Total
Per Side
Total

PD

250
350
2
2.8

TJ

-55 to 150

Tstg

-65 to 150

h

300

noted)
UNITS

V

mA
mW
mWloC

°C

U440 SERIES

ttCrSiliconix

~ incorporatE!d

ELECTRICAL CHARACTERISTICS 1

LIMITS
U440
TYp2

MAX

MIN

MAX

UNIT

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -l.1lA, Vas = 0 V

-35

-25

Gate-Source
Cutoff Voltage

VGS(OFF)

Vas = 10 V, 10 = 1 nA

-3.5

-1

-6

-1

-6

Saturation Drain
Current 3

loss

Vas = 10 V, VGS = 0 V

15

6

30

6

30

rnA

Gate Reverse
Current

IGSS

-500

-500

pA

-500

-500

pA

PARAMETER

MIN

U441

STATIC
-25
V

Gate Operating
Current

IG

Gate-Source
Forward Voltage

VGS(F)

V Gs =-15V
Vas = 0 V
VaG = 10 V
10 = 5 rnA

-1

IT

A

=150·C

-2

nA

-1

IT

-0.3

nA

IG = 1 rnA, Vas = 0 V

0.7

V

VaG = 10 V, 10 = 5 rnA
f = 1 kHz

6

A

=125·C

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance

gl.
gos

70

Common-Source
Input Capacitance

C lss

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

en

VaG=10V,la=5mA
f = 10 kHz

4

Differential
Gate-Source Voltage

! VGS1-VGS2!

VaG = 10 V, I a = 5 rnA

6

Gate-Source Voltage
Differential Change
with Temperature

A!VGS1-VGS2!

VaG = 10 V, 10 = 5 rnA
f = 1 MHz

4.5

9
200

4.5

9

mS

200

.IlS

3
pF
1

%
-1Hz

MATCHING

AT

VaG = 10 V
10 =5mA

I

T = -55 to 25·C

I T = 25 to 125·C

20
20

Saturation
Drain Current Ratio

lassl
lass2

Vas = 10 V, VGS = 0 V

0.97

Transconductance
Ratio

glsl
gls2

VaG = 10 V, 10 = 5 rnA
f = 1 kHz

0.97

CMRR

V aa =5tol0V,l a =5mA

85

Common Mode
Rejection Ratio
NOTES:

10

20

mV

~·C

dB

1. T A = 25·C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300.lls, duty cycle S3%.

4-171

..:rSiliconix
...z:.
incorporated

U443 SERIES
N-Channel JFET Pairs

The U443 Series are matched pairs of JFETs
mounted in a single TO-78 package. This two chip
design reduces parasitic performance at high
frequency while ensuring extremely tight matching.
The U443 features high speed amplification (slew
rate), high gain (typically> 6 mS), and low gate
leakage (typically < 1 pA).
This performance
makes these devices perfect for use as wideband
differential amplifiers in demanding test and
Finally, its TO-78
measurement applications.
hermetically sealed package is available with
military screening per MIL-S-19500.
(See
Section 1.)

PART
NUMBER

V(BR)GSS 9fs
MIN
MIN
(V)
(mS)

IG IVGS1- VGS21
MAX
MAX
(pA)
(mV)

U443

-25

4.5

-500

10

U444

-25

4.5

-500

20

BOTTOM VIEW

TO-78

For additional design information please see
performance curves NZF, which are located in
Section 7.
1
2
3
4
5
6
7

SIMILAR PRODUCTS
•
•
•
•
•

TO-71 , See U440 Series
SO-8, See SST440 Series
Low Noise, See U401 Series
Low Leakage, See U421 Series
Chips, Order U44XCHP

SOURCE 1
DRAIN 1
GATE 1
CASE
SOURCE 2
DRAIN 2
GATE 2

ABSOLUTE MAXIMUM RATINGS (T A = 25 DC unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

Gate-Drain Voltage

VGD

-25

Gate-Source Voltage

VGS

-25

Gate-Gate Voltage

VGG

± 50

Forward Gate Current
Power Dissipation
Power Derating
Operating Junction Temperature

IG
Per Side
Total
Per Side
Total

PD

50
367
500
3
4

TJ

-55 to 150

Storage Temperature

T stg

-65 to 150

Lead Temperature
(1/16" from case for 10 seconds)

h

300

4-172

UNITS

V

mA
mW

mW/oC

°C

.HSiliconix

U443 SERIES

incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
U443

TYp2

MAX

MIN

MAX

SYMBOL

TEST CONDITIONS

Gate-Source
Breakdown Voltage

V(BR)GSS

IG = -lJ.lA, Vos = 0 V

-35

-25

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos=10V,10=lnA

-3.5

-1

-6

-1

-6

15

6

30

6

30

mA

-500

pA

PARAMETER

MIN

U444
UNIT

STATIC
-25
V

Saturation Drain
Current 3

loss

Gate Reverse
Current

IGSS

Gate Operating
Current

IG

Gate-Source
Forward Voltage

VGS(F)

Vos = 10 V, V GS = 0 V
V GS = -15 V
Vos = 0 V
VOG = 10 V
10 = 5 mA

-1
! T A =150°C

-500

-2

nA

-1

-500

-500

pA

-0.3

nA

I G = 1 mA, Vos = 0 V

0.7

V

V OG = 10 V, I 0 = 5 mA

6

! T A =125°C

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance

gls
gos

Common-Source
Input Capacitance

4.5

9

4.5

9

mS

200

jJ.S

f = 1 kHz
70

C 1SS

V DG = 10 V, I 0 = 5 mA

3
pF

Common-Source
Reverse Transfer
Capacitance

Crss

Equivalent Input
Noise Voltage

en

V DG = 10 V, 10 = 5 mA
f = 10 kHz

4

I VGS1-VGS21

VOG = 10 V, 10 = 5 mA

6

f = 1 MHz

200

1

%
..[Hz

MATCHING
Differential
Gate-Source Voltage
Gate-Source Voltage
Differential Change
with Temperature

I

A VGS1-VGS2
AT

I DSS1

I

I T = -55 to 25°C

20

10=5mA! T = 25 to 125°C

20

VOG = 10 V

Saturation
Drain Current Ratio

IOSS2

Vos = 10 V, V GS = 0 V

0.97

Transconductance
Ratio

gls1
gl52

VOG = 10 V, 10 = 5 mA
f = 1 kHz

0.97

CMRR

Voo = 5 to 10 V, 10 = 5 mA

85

Common Mode
Rejection Ratio
NOTES:

10

20

mV

~°c

dB

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300J.ls, duty cycle :53%.

4-173

III

wrSiliconix

U1897 SERIES

~ incorporatec

N-Channel JFET

The U1897 Series is a mUlti-purpose n-channel JFET
designed
to
economically
enhance
circuit
performance. These devices are especially well
suited for analog switching applications but function
efficiently as high-gain amplifiers, particularly at
high-frequency.
Our low-cost TO-92 packaging
offers affordable performance with flexibility for
designers, as these devices can be ordered with a
variety of lead forms or tape and reel for automated
insertion. (See Section 8.)

PART
NUMBER

Vas (OFF)
MAX
(V)

rds(ON) IO(OFF)
MAX
MAX
(n)
(pA)

tON
MAX
(ns)

U1897

-10

30

200

25

U1898

-7

50

200

35

U1899

-5

80

200

60

TO-92

For additional design information please consult the
typical performance curves NCB which are located
in Section 7.

BOTTOM VIEW

1 DRAIN

2 SOURCE

SIMILAR PRODUCTS
•
•
•
•

3 GATE

TO-18, See 2N4091 Series
SOT-23, See SST4091 Series
Duals, See 2N5564Series
Chips, Order U189XCHP

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise noted)
SYMBOL

LIMIT

UNITS

Gate-Drain Voltage

Vao

-40

Gate-Source Voltage

Vas

-40

Gate Current

IG

10

mA

Power Dissipation

Po

360

mW

3.27

mW/oC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-174

TJ

-55 to 135

T stg

-55 to 150

TL

300

°C

U1897 SERIES

~Siliconix

~ incorporated

LIMITS

ELECTRICAL CHARACTERISTICS 1
U1897
SYMBOL

TEST CONDITIONS

TVP2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

I G =-ljJ.A.Vos=OV

-55

-40

Gate-Source
Cutoff Voltage

VGS(OFF)

Vos = 20 V. 10 = 1 nA

-5

Saturation Drain
Current 3

loss

Vos = 20 V. VGS = 0 V

30

Gate Reverse Current

IGSS

PARAMETER

MAX

U1898
MIN

MAX

U1899
MIN

MAX UNIT

STATIC

Gate Operating
Current

-40
V

IG

VGS = -20 V
Vos = 0 V

-5
T A = 65°C

VOG=15V.10 = 10 mA

Vos = 20 V

Drain Cutoff Current

-40

10(OFF)
Vos = 20 V
T A = 65°C

-10

-2

-7

15
-400

VOS(ON)

VGS = 0 V

-400

5
5

VGS = -12 V

5

VGS = -6 V

0.2

VGS = -6 V

0.2

VGS = -12 V

0.2

VGS = 0 V. 10 = 1 mA

Gate-Source
Forward Voltage

VGS(F)

I G = 1 mAo V DS = 0 V

pA
nA

200

pA

200
200
10
10

nA

10
0.2

0.15

10 = 6.6 mA 0.15
rOS(ON)

-400

-5

VGS = -6 V

Drain-Source
On-Resistance

mA

-0.2

VGS = -6 V

10 = 4 mA

-5

6

10 = 2.5 mA 0.15
Drain-Source
On-Voltage

-1

0.2

V

0.2
30

50

60

.0.

0.7

V

6

mS

25

jJ.S

DYNAMIC
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
Drain-Source
On-Resistance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer
Caoacltance
Equivalent Input
Noise Voltage

gfs
gos
rds(ON)

VOG=20V.10=lmA
f = 1 kHz
VGS = 0 V. 10 = 0 mA
f = 1 kHz

C lss
Crss

V DS = 20 V. VGS = 0 V
f = 1 MHz

30

50

60

14

16

16

16

3

3.5

3.5

3.5

.0.

pF

~
VHZ

en

VOG = 10 V. 10 = 10 mA
f = 1 kHz

3

td(ON)

Voo = 3 V. VGS(ON) = 0 V
PIN
10(oN) VGS(OFF) RL
U1697
6.6 mA -12 V
430.0.
-6 V
U1696
4mA
700.0.
U1699
2.5 mA
-6 V 1100.0.

2

15

15

20

2

10

20

40

19

40

60

60

SWITCHING
Turn-on Time

tr
Turn-off Time
NOTES:

t OFF

ns

1. T A = 25 ° C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW =300jJ.s. duty cycle S3%.

4-175

•

VCR2N, VCR4N, VCR7N, VCR3P

~Siliconix

~ incorporated

JFET Voltage Controlled Resistors

The VCR2N, VCR4N, VCR7N, and VCR3P line of
JFET voltage controlled resistors utilize the JFET's
linear output characteristics in the resistive region.
This area of operation is around VDS = 0 V and
extends for a range up to several hundred
millivolts - up to the point I D begins to saturate.
Key to device performance is the predictable rDS
change versus VGS bias where:

PART
NUMBER

MIN
(il)

MAX
(il)

VCR2N

-3.5

-15

20

60

VCR4N

-7

-15

200

600

VCR7N

-5

-15

4000

8000

VCR3P

5

15

70

200

rDS (@ VGs= 0)
.
VGS
r DS bias "" 1 _
VGS(OFF)

I

rds(ON)

VGS(OFF) V (BR)GSS
MIN
MAX
(il)
(V)

I

TO-18

BOTTOM VIEW

~SOURCE

This series features three n-channel devices with
rDS(ON) ranging from 20 - 8000 il. Also featured is
a p-channel device with rDS(ON) specified between
70 and 200 il.
All packages are hermetically
sealed and may be processed per MIL-S-19500.
(See Section 1.)

2 DRAIN
3 GATE

BOTTOM VIEW

TO-72
For additional design information please consult
typical performance curves (Section 7) as follows:
VCR2N
VCR4N
VCR7N
VCR3P

......
......
......
. . . . ..

NCB
NPA
NT
PSCIA

1 SOURCE
2 DRAIN
3 GATE
4 SUBSTRATE

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT
VCR2N-7N

VCR3P

Gate-Drain Voltage

VGD

-15

15

Gate-Source Voltage

VGS

-15

15

IG

10

-10

UNITS

V

Gate Current
Power Dissipation

(Case 25°C)

PD

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

4-176

mA

300

mW

2

mW/oC

TJ

-55 to 175

Tstg

-55 to 175

h

300

°C

VCR2N,VCR4N,VCR7N,VCR3P

..rSiliconix
..z:.
incorporatE!d
N-CHANNEL

LIMITS

ELECTRICAL CHARACTERISTICS 1
VCR2N
SYMBOL

TEST CONDITIONS

TYp2

MIN

Gate-Source
Breakdown Voltage

V(BR)GSS

IG=-1J.LA.Vos=OV

-55

-15

Gate-Source
Cutoff Voltage

VGS(OFF)

VOS = 10 V. 10 = 1J.LA

PARAMETER

VCR4N

MAX

MIN

VCR7N

MAX

MIN

MAX UNIT

STATIC

Gate Reverse Current

-15

-15

V

IGSS

VGS = -15 V. Vos = 0 V

Drain-Source
On-Resistance

rOS(ON)

VGS = 0 V. 10 = 1 mA

Gate-Source
Forward Voltage

VGS(F)

I G = 1 mAo Vos = 0 V

rd.(ON)

VGS = 0 V. 10 = 0 A
f = 1 kHz

-1

-3.5

-3.5

-5
20

-7

-2.5

-0.2

60

200

600

4000

-5
-0.1

nA

8000

.0.

0.7

V

DYNAMIC
Drain-Source
On-Resistance
Drain-Gate
Capacitance

C dg

V GO = -10 V. Is =
f = 1 MHz

aA

Source-Gate
Capacitance

COg

VGS = -10 V. 10 =
f = 1 MHz

aA

20

60

200

600

4000

8000

7.5

3

1.5

7.5

3

1.5

.0.

pF

P-CHANNEL
ELECTRICAL CHARACTERISTICS 1

LIMITS
VCR3P

PARAMETER

SYMBOL

TEST CONDITIONS

V(BR)GSS

IG = 1 J.LA. Vos =

Typ2

MIN

50

15

MAX

UNIT

STATIC
Gate-Source
Breakdown Voltage
Gate-Source
Cutoff Voltage
Gate Reverse Current

aV

V
VGS(OFF)
IGSS

Vos = -10 V. 10 = -1J.LA
VGS = 15 V. Vos =

aV

2.5

1

0.005

Drain-Source
On-Resistance

rOS(ON)

VGS = 0 V. 10 = -1 mA

100

Gate-Source
Forward Voltage

VGS(F)

IG=-1mA.Vos=OV

-0.7

rd. (ON)

VGS =

a v. 10 =
f = 1 kHz

aA

100

C dg

V GO = 10 V. Is =
f = 1 MHz

aA

C.g

VGS = 10 V. 10 = 0 A
f = 1 MHz

70

5
20

nA

200

.0.
V

DYNAMIC
Drain-Source
On-Resistance
Drain-Gate
Capacitance
Source-Gate
Capacitance

NOTES:

70

200

6

25

6

15

.0.

pF

1. T A = 25·C unless otherwise noted.
2. For design aid only. not subject to production testing.

4-177

III

General Information
Cross Reference
Selector Guide
JFETs
OMOS
Low Power MOS

iii
..

Performance Curves
Package Outlines
Applications
Worldwide Sales Offices and Distributors

:,',

'::;

.r-Siliconix

~ incorporated

DMOS
INTRODUCTION

DMOS products from Silica nix utilize a lateral double-diffused MOS process to offer the ultimate
low-cost yet highly reliable switches. It's unique lateral construction affords all the benefits
critical to small-signal switching applications. Ultra fast switching speed, exceptionally low
capacitance, good off-isolation, and high operating frequency are all available to design engineers todayl
Key applications which benefit from this technology include video switching and precIsion
sample and hold applications. In fact, any high performance application which benefits from
< 1 ns turn-on time, < 0.5 pF capacitance, and operating frequencies up to 1 GHz, should utilize
Siliconix' lateral DMOS as an optimal design solution.
Packaging options are diversified and range from surface mount to hermetically sealed metal
cans and both single and quad array switches may be purchased. With our high reliability silicon
gate process, full military processing is available per MIL-S-19500 on all hermetically sealed
packages.
For additional technical information please see "Switching DMOS Fast" (LPD-11), "An Ultra
Broadband Analog Switch" (LPD-20), and "High speed Depletion-mode DMOS FETs" (LPD-12).
These application notes are located in section nine and provide useful insight into device
operation.

5-1

tcrSiliconix

2N71 04 SERIES

~ incorporated

N-Channel Lateral DMOS FETs

The 2N7104 Series of lateral DMOS FETs is
designed for high speed switching in audio. video.
and high-frequency applications. These devices
are designed on the Siliconix DMOS process and
utilize lateral construction to achieve low
capacitance and ultra-fast switching speeds. For
long term reliablitly this series features a polysilicon gate. making Siliconix 2N7104 devices the
perfect choice for high-performance military
applications.

V(BR)OS
MAX
(V)

rds(ON)
MAX
(n)

C rss
MAX
(pF)

tON
MAX
(ns)

2N7104

20

70

0.5

2

2N7106

10

70

0.5

2

2N7108

15

70

0.5

2

PART
NUMBER

BOTTOM VIEW

TO-72

For additional design information please see
performance curves DMCB. which are located in
Section 7.

SIMILAR PRODUCTS
•
•
•
•
•

Quad Array. See 2N7116 Series
SO-14 Array. See SD5400 Series
Zener Protection. See 2N7105 Series
SOT-143. See SST211 Series
Chips. Order 2N710XCHP

1
2
3
4

SOURCE
DRAIN
GATE
SUBSTRATE, CASE

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

2N7104

2N7106

2N710S

VGS,VGD.VGB

±40

±40

±40

Drain-Source Voltage

Vos

30

10

20

Source-Drain Voltage

VSO

10

10

20

Drain-Substrate Voltage

VOB

30

15

25

Source-Substrate Voltage

VSB

15

15

25

ID

50

50

50

mA

Po

300

300

300

mW

2.4

2.4

2.4

mW/oC

Gate-Source, Gate-Drain
Gate-Substrate Voltage

Drain Current
Power Dissipation

(TJ = 25°C)

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

5-2

TJ

-55 to 150

T stg

-65 to 200

TL

300

V

°C

2N7104 SERIES

.-r-Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N7104

PARAMETER

SYMBOL

2N7106

2N7108

TEST CONDITIONS

Typ2

MIN

V GS =VBS = 0 V, 10 = 10.llA

35

30

V GS =VBS = -5 V, Is = 10 nA

30

10

10

20

MAX

MIN

MAX

MIN

MAX UNIT

STATIC
Drain-Source
Breakdown Voltage3

VIBR)OS

Source-Drain
Breakdown Voltage3

VIBR)SO

V GO =VBO = -5 V, 10 = 10 nA

22

10

10

20

Drain-Substrate
Breakdown Voltage3

VIBR)OB

V GB = 0 V
10=10nA

Source OPEN

35

15

15

25

Source-Substrate
Breakdown Voltage3

VIBR)SB

V GB = 0 V
Is = 10.llA

Drain OPEN

35

15

15

25

Drain-Source
Leakage

10SIOFF)

Source-Drain
Leakage

V GS =VBS = -5 V

Vos=10V
Vos = 20 V

0,4
0,9

10

V GS =VBS = -5 V
T A = 125 DC

Vos = 10 V
Vos - 20 V

0.4
0,9

5

Vso = 10 V

0,5

10

10

V"O = 20 V
VSO = 10 V
Vso = 20 V

1
5

5

VGO=V BO = -5 V
I SOlOFF)

V Go =-5V
T A = 125 DC

Gate Leakage

IGSS

Vos =VSB = 0 V
VGs= 12 V

Zero Gate Voltage
Drain Current

loss

Vos = 30 V, VGS = VBS =

Threshold Voltage

VGs(th)

Drain-Source
On-Resistance

rOSION)

5
5
10

0.5
1

aV

V GS = 5 V, 10 = 1 mA

10
10

T A = 125 DC

Vos = VGS = VGSlth), Is = l.1lA
V SB = a V

V

100

100

5
100

1

1

1

58

0.5

2.0
70

.IlA
nA
.IlA
nA
.IlA

10
0.7

nA

0.1

2.0
70

0.1

2.0

V

70

.n.

DYNAMIC

~~~~:~~nductance 3

gts

g~~~~tance3

gos

Gate Node
Capacitance

Ciss

Reverse Transfer
Capacitance

C rss

VOS = 10 V, V SB = a V
10 = 20 mA, f = 1 kHz

V os =10V,f=1 MHz
V GS =V BS = -15 V

11
mS
0.9
2.5

3.5

3.5

3.5

0.2

0.5

0.5

0.5

0.5

1

1

1

0.6

1

1

1

pF

SWITCHING
Turn-ON Time
Turn-OFF Time 3
NOTES:

tdlON)
tr
tdIOFF)

VOO = 5 V, R L = 680 .n.
VIN = 5 V, RG = 50 .n.

tt

2

ns

6

1. T A = 25 DC unless otherwise noted.
2. For design aid only, not subject to production testing.
3. This parameter not registered with JEDEC.

5-3

.-:F'Siliconix

2N7105 SERIES

~ incorporated

N-Channel Lateral DMOS FETs

The 2N7105 Series of single-pole, single-throw
analog switches is designed for high speed
switching in audio, video, and high-frequency
applications. These devices are designed on the
Siliconix DMOS process and utilize lateral
construction to achieve low capacitance and
ultra-fast switching speeds. This series also feature
an integrated Zener diode designed to protect the
gate from electrical .. spikes" or overstress ..

V(BR)DS
MAX
(V)

rds(ON)
MAX
(0)

2N7105

10

2N7107

10
20

PART
NUMBER

2N7109

For additional design information please see
performance curves DMCB, which are located in
Section 7.

C rss
MAX
(pF)

tON
MAX
(ns)

70

0.5

2

70

0.5

2

70

0.5

2

BOTTOM VIEW

TO-72

SIMILAR PRODUCTS
•
•
•
•

Quad Array, See 2N7116 Series
SO-14 Array, See SD5400 Series
SOT-143, See SST211 Series
Chips, Order 2N710XCHP

1 SOURCE
2 DRAIN
3 GATE
4 SUBSTRATE, CASE

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise noted)

SYMBOL

LIMIT

UNITS

2N7105

2N7107

2N7109

VGS,VGD

-30/25

-15/25

-25/30

Gate-Substrate Voltage 1

VGB

-0.3/25

-0.3/25

-0.3/30

Drain-Source Voltage

VDS

30

10

20

Source-Drain Voltage

VSD

10

10

20

Drain-Substrate Voltage

VOB

30

15

25

Source-Substrate Voltage

VSB

15

15

25

10

50

50

50

mA

Po

300

300

300

mW

2.4

2.4

2.4

mW/oC

Gate-Source, Gate-Drain Voltage

Drain Current
Power Dissipation (TJ

= 25°C)

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 150

T stg

-65 to 200

h

300

lThese devices feature an internal Zener protected gate.
5-4

V

°C

2N7105 SERIES

~Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N7105

PARAMETER

SYMBOL

2N7107

2N7109

TEST CONDITIONS

TYp2

MIN

VGS =VBS = 0 V. 10 = 10,IJ.A

35

30

VGS =V BS = -5 V. Is = 10 nA

30

10

10

20

MAX

MIN

MAX

MIN

MAX UNIT

STATIC
DraIn-Source
Breakdown Voltage 3

V(BR)OS

Source-DraIn
Breakdown Voltage3

V(BR)SO

VGO=VBO = -5 V. 10= 10 nA

22

10

10

20

DraIn-Substrate
Breakdown Voltage3

V(BR)OB

V GB = 0 V
10 = 10 nA

Source OPEN

35

15

15

25

Source-Substrate
Breakdown Voltage 3

V(BR)SB

V GB = 0 V
Is = 10,IJ.A

DraIn OPEN

35

15

DraIn-Source
Leakage

Source-DraIn
Leakage

VGS =V BS = -5 V

0.4
0.9

10

10

Vas =VBS = -5 V
T A = 125°C

VOS = 10 V
Vos = 20 V

0.4
0.9

5

5

Vso = 10 V
Vso= 20 V
Vso = 10 V

0.5

10

I OS (OFF)

Vao=VBo = -5 V
I so (OFF)
VGo= -5 V
T A = 125°C

lass

25

Vos = 10 V
Vos = 20 V

VOS =VSB = 0 V
Gate Leakage

15

VOS=VSB=OV
T A = 125°C

Vso= 20 V
Vas = 25 V
Vas = 30 V

10
5

1
0.5

10
10

5

5

1

1

100

100

1

1

VGs= 30 V

loss

Vos = 30 V. VGS = V BS = 0 V

Threshold Voltage

VGS(th)

Vos=VGs= VGS(th). Is= I,IJ.A
V SB = 0 V

Drain-Source
On-ResIstance

rOS(ON)

VGS = 5 V. 10 = 1 mA

nA
,lJ.A
nA

5

VGs= 25 V

Zero Gate Voltage
DraIn Current

V

,lJ.A

100
10
0.7
58

0.5

2
70

0.1

2
70

0.1

2

V

70

.n.

DYNAMIC

~~~~;~~nductance 3

gfs

g~~~~tance3

gos

Gate Node
Capacitance

C 1SS

Reverse Transfer
Capacitance

C rss

VOS = 10 V. V SB = 0 V
10 = 20 mAo f = 1 kHz

Vos= 10V. f= 1 MHz
VGS =VBS = -15 V

11
mS
0.9
2.5

3.5

3.5

3.5

0.2

0.5

0.5

0.5

0.5

1

1

1

0.6

1

1

1

pF

SWITCHING
Turn-ON Time
Turn-OFF Time 3
NOTES:

td(ON)
t,
td(OFF)

VOO= 5 V. R L = 680.n.
VIN = 5 V. RG= 50.n.

tf

2

ns

6

1. T A = 25 ° C unless otherwise noted.
2. For desIgn aid only. not subject to production testing.
3. ThIs parameter not registered with JEDEC.

5-5

.-r-Siliconix

2N7116 SERIES

~ inc:crpcrated

N-Channel Lateral DMOS Quad FETs
The Siliconix 2N7116 series is a monolithic array of
single-pole, single-throw analog switches designed
for high speed switching in audio, video' and high
frequency applications in communications, instrumentation, and process control. Designed on the
Siliconix OM OS process, the 2N7116 is rated for
analog signals of ±10 V, while the 2N7117 and

PART
NUMBER

V(SR)DS
MIN
(V)

VGS(th)
MAX
(V)

rds(ON)
MAX
(il)

tON
MAX
(ns)

2N7116

20

2.0

70

2

2N7117

10

2.0

70

2

2N7118

15

2.0

70

2

2N7118 are rated for ±5 V and ±7.5 V respectively.
These bidirectional switches feature very low
interelectrode capacitance and on-resistance to
achieve low insertion loss,
crosstalk, and
feedthrough performance. The threshold voltage
for all switches is 2 V maximum, simplifying driver
requirements for low level signal applications.

16-PIN DIP
SIDE BRAZE QUAD

TOP VIEW

For additional design information please see
performance curves DMCA-1 B, which are located in
Section 7.

SIMILAR PRODUCTS
•
•
•
•

SOT-143, See SST211 Series
TO-18, See SD211DE Series
SO-14, See SD5400 Series
Chips, Order 2N711XCHP

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT
2N7116

2N7117

2N7118

Gate-Source, Gate-Drain Voltage

VGS,VGO

25/-25

25/-15

30/-22.5

Drain-Substrate, Source-Substrate
Voltage

Vos,Vss

25

15

22.5

Drain-Source, Source-Drain Voltage

Vos,Vso

20

10

15

VGS

30/-0.3

25/-0.3

30/-0.3

UNITS

V
Gate-Substrate Voltage 1
Drain Current
Power Dissipation

I
I

PackaQe
Each Device

10

50

mA

Po

640
300

mW

5

mW/oC

Power Derating (Package)
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 125

Tstg

-55 to 150

TL

300

1These devices feature an internal Zener procted gate.
5-6

°C

2N7116 SERIES

~Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N7116

PARAMETER

SYMBOL

2N7117

2N7118

TEST CONDITIONS

TYp2

MIN

V Gs =VBs =OV,ID=10J.lA

35

30

VGS =V BS = -5 V, Is = 10 nA

30

10

10

20

MAX

MIN

MAX

MIN

MAX UNIT

STATIC
Drain-Source
Breakdown Voltage 3

V(BR)OS

Source-Drain
Breakdown Voltage3

V(BR)SO

V GO = V BO = -5 V, 10 = 10 nA

22

10

10

20

Drain-Substrate
Breakdown Voltage3

V(BR)OB

V GB = 0 V
10=10nA

Source OPEN

35

15

15

25

Source-Substrate
Breakdown Voltage 3

V(BR)SB

V GB = 0 V
Is=10J.lA

Drain OPEN

35

15

15

25

VGS=VBS = -5 V

Drain-Source
Leakage

I OS (OFF)
VGS =VBS = -5 V
T A = 125°C

V Go =VBo =-5V

Source-Drain
Leakage

I so (OFF)

VOS=VSB=OV

IGSS

0.4
0.7

VOS = 20 V
Vos = 10 V

0.9
0.4

Vos=15V

0.7

Vos = 20 V

0.9
0.5

Vso = 10 V
V SD = 15 V
VSO = 20 V
Vso=10V

VGO=VBO = -5 V
T A = 125°C

Gate Leakage

Vos=10V
Vos=15V

VDS=VSB=OV
T A = 125°C

Vso=15V
Vso = 20 V

10

Threshold Voltage

VGS(th)

Vos = VGS = VGS(th) ' 10= lJ.lA
V SB = 0 V

Drain-Source
On-Resistance

rOS(ON)

VGS = 5 V, ID = 1 mA
VBS = 0 V

5

J.lA

10

nA

5
10

0.7
1
0.5
0.7

10

1

5

5
5
1
1

1

J.lA

10

VGS = 30 V

VOS= 30 V, VGS=VBS=OV

nA

5

VGs= 25 V

loss

10
10

VGs= 25 V
V Gs =30V

Zero Gate Voltage
Drain Current

V

10

10
10
0.7
58

0.1

2
70

0.1

2
70

0.1

2

V

70

.0.

DYNAMIC

~~~~:6~nductance 3

gls

g~~~~tance3

90S

Gate Node
Capacitance

Ciss

Reverse Transfer
Capacitance

erss

VOS = 10 V, V SB = 0 V
I D = 20 mA, f = 1 kHz

Vos=10V,f=1MHz
VGS =VBS = -15 V

11
mS
0.9
2.5

3.5

3.5

3.5

0.2

0.5

0.5

0.5

0.5

1

1

1

0.6

1

1

1

pF

SWITCHING
Turn-ON Time
Turn-OFF Time 3

td(ON)
t,
td(OFF)

VOO= 5 V, R L = 680.0.
V IN = 5 V, RG= 50.0.

tl
NOTES. 1. T A = 25 ° C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. This parameter not registered with JEDEC.

2

ns

6

5-7

fCrSiliconix
.z.
incorporated

SD210DE SERIES
N-Channel Lateral DMOS FETs

The SD210DE Series of single-pole, single-throw
analog switches is designed for high speed
switching in audio, video, and high-frequency
applications. These devices are designed on the
Siliconix DMOS process and utilize lateral
construction to achieve low capacitance and
ultra-fast switching speeds.
For long term
reliability, this series also features a poly-silicon
gate.

V(BR)DS
MAX
(V)

rds(ON)
MAX
(0,)

C rss
MAX
(pF)

tON
MAX
(ns)

SD210DE

20

45

0.5

2

SD212DE

10

45

0.5

2

SD214DE

15

45

0.5

2

PART
NUMBER

For additional design information please see
performance curves DMCB, which are located in
Section 7.

TO-72

BOTTOM VIEW

SIMILAR PRODUCTS
•
•
•
•
•

Quad Array, See SD5000 Series
SO-14 Array, See SD5400 Series
Zener Protection, See SD211 DE Series
SOT-143, See SST211 Series
Chips, Order SD21XCHP

1
2
3
4

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

SOURCE
DRAIN
GATE
SUBSTRATE, CASE

= 25°C unless otherwise noted)

SYMBOL

LIMIT

UNITS

SD210DE

SD212DE

SD214DE

VGS,VGO,VGB

±40

±40

±40

Drain-Source Voltage

Vos

30

10

20

Source-Drain Voltage

Vso

10

10

20

Drain-Substrate Voltage

VOB

30

15

25

Source-Substrate Voltage

VSB

15

15

25

Drain Current

10

50

50

50

mA

Power Dissipation (25°C Case)

Po

1200

1200

1200

mW

9.6

9.6

9.6

mWloC

Gate-Source, Gate-Drain
Gate-Substrate Voltage

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

5-8

TJ

-55 to 150

T 5t9

-65 to 200

TL

300

V

DC

SD210DE SERIES

.rSiliconix

~ incorporated

LIMITS

ELECTRICAL CHARACTERISTICS 1
SD210DE
PARAMETER

SYMBOL

SD212DE

SD214DE

TEST CONDITIONS

TYp2

MIN

Vas =VBS = 0 V, 10 = 10P.A

35

30

Vas =V BS = -5 V, Is = 10 nA

30

10

10

20

MAX

MIN

MAX

MIN

MAX UNIT

STATIC
Drain-Source
Breakdown Voltage

V(BR)OS

Source-Drain
Breakdown Voltage

V(BR)SO

Vao =VBo = -5 V, 10 = 10 nA

22

10

10

20

Drain-Substrate
Breakdown Voltage

V(BR)OB

V aB = 0 V
10=10nA

Source OPEN

35

15

15

25

Source-Substrate
Breakdown Voltage

V(BR)SB

V aB = 0 V
Is = 10p.A

Drain OPEN

35

15

15

25

Drain-Source
Leakage

10S(OFF)

Vas =VBS = -5 V

Vos=10V
VOS = 20 V

0.4
0.9

10

10

VSO = 10 V
Vso = 20 V

0.5

10

10

Source-Drain
Leakage

ISOIOFF)

Gate Leakage

laBs

VOB =V SB = 0 V, VaB = :!:40 V

0.001

VaS(th)

VOS - Vas - VaS(th), Is - lP.A
V SB = 0 V

0.7

Threshold Voltage

Drain-Source
On-Resistance

rOS(ON)

Vao=V Bo =-5V

10= 1 rnA
V SB = 0 V

V

10
10

1
0.1

0.1
0.5

2

0.1

2

nA

0.1
0.1

2

Vas = 5 V

58

70

70

70

Vas=10V

38

45

45

45

Vas = 15 V

30

Vas = 20 V

26

Vas = 25 V

24

V

.n.

DYNAMIC
Forward
Transconductance

gls

Output
Conductance

gos

Gate Node
Capacitance

C (as+ao+aB)

Drain Node
Capacitance

C (ao+oB)

Source Node
Capacitance

C (as+SB)

Reverse Transfer
Capacitance

Vos = 10 V, V SB = 0 V
10 = 20 rnA, f = 1 kHz

VOS = 10 V, f = 1 MHz
Vas=VBs = -15 V

C rss

11

10

10

10
mS

0.9
2.5

3.5

3.5

3.5

1.1

1.5

1.5

1.5

3.7

5.5

5.5

5.5

0.2

0.5

0.5

0.5

0.5
0.6

1

1

1

1

1

1

pF

SWITCHING
Turn-ON Time
Turn-OFF Time
NOTES:

td(ON)
tr
td(OFF)

Voo = 5 V, R L = 680
VIN = 0 to 5 V

.n.

tf

2

ns

6

1. T A = 25·C unless otherwise noted.
2. For design aid only, not subject to production testing.

5-9

SD211 DE SERIES

~SilicDnix

~ incorporated

N-Channel Lateral DMOS FETs

The SD211 DE Series of single-pole, single-throw
analog switches is designed for high speed
switching in audio, video, and high-frequency
applications. These devices are designed on the
Sillconix DMOS process and utilize lateral
construction to achieve low capacitance and
ultra-fast switching speeds.
This series also
features an integrated zener diode designed to
protect the gate from electrical " Spikes" or
overstress.

V(BR)DS
MAX
(V)

rds(ON)
MAX
(.0)

C rss
MAX
(pF)

tON
MAX
(ns)

SD211DE

10

45

0.5

2

SD213DE

10

45

0.5

2

SD215DE

20

45

0.5

2

PART
NUMBER

BOTTOM VIEW

TO-72

For additional design information please see
performance curves DMCB, which are located in
Section 7.

SIMILAR PRODUCTS
•
•
•
•

Quad Array, See SD5000 Series
SO-14 Array, See SD5400 Series
SOT-143, See SST211 Series
Chips Order, SD21XCHP

1
2
3
4

SOURCE
DRAIN
GATE
SUBSTRATE, CASE

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS
Gate-Source, Gate-Drain Voltage

SYMBOL
VGS,VGO

LIMIT
SD211DE

SD213DE

SD215DE

-30/25

-15/25

-25/30

UNITS

Gate-Substrate Voltage

VGB1

-0.3/25

-0.3/25

-0.3/30

Drain-Source Voltage

Vos

30

10

20

Source-Drain Voltage

Vso

10

10

20

Drain-Substrate Voltage

VOB

30

15

25

Source-Substrate Voltage

VSB

15

15

25

Drain Current

10

50

50

50

mA

Power Dissipation (25°C Case)

Po

1200

1200

1200

mW

9.6

9.6

9.6

mW/oC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 150

T stg

-65 to 200

TL

300

1This series features an internal zener diode for gate protection
5-10

°C

S02110E SERIES

~Siliconix

~ inclJrplJrated

ELECTRICAL CHARACTERISTICS 1

LIMITS
SD211DE

PARAMETER

SYMBOL

SD213DE

SD215DE

TEST CONDITIONS

TYp2

MIN

vas =V BS = 0 V. ID = 10.l1A

35

30

Vas =V BS = -5 V. Is = 10 nA

30

10

10

20

MAX

MIN

MAX

MIN

MAX UNIT

STATIC
Drain-Source
Breakdown Voltage

V(BR)DS

Source-Drain
Breakdown Voltage

V(BR)SD

VaD=VBD = -5 V. ID = 10 nA

22

10

10

20

Drain-Substrate
Breakdown Voltage

V(BR)DB

V aB = 0 V
ID=10nA

Source OPEN

35

15

15

25

Source-Substrate
Breakdown Voltage

V(BR)SB

V aB = 0 V
Is = 10.l1A

Drain OPEN

35

15

15

25

Drain-Source
Leakage Current

I DS(OFF)

Source-Drain
Leakage Current
Gate Leakage
Current
Threshold Voltage

Drain-Source
On-Resistance

ISD(OFF)
laBs
VaS(th)

rDS(ON)

Vas =VBS = -5 V
VaD=V BD = -5 V

V DS = 10 V
V DS = 20 V

0.4
0.9

10

10

V SD = 10 V
V SD = 20 V

0.5

10

10

V

10

1

V DB = V SB = 0 V. V aB = 30 V

10-5

VDS = Vas = VaS(th)' Is = 1.11A
V SB = 0 V
Vas - 5 V

0.7
58

70

70

70

Vas=10V

38

45

45

45

Vas = 15 V

30

Vas = 20 V

26

Vas = 25 V

24

ID= 1 rnA
V SB = 0 V

nA

10
10

10
0.5

2

0.1

2

0.1

10

.I1A

2

V

.0.

DYNAMIC
Forward
Transconductance

gfs

Output
Conductance

gos

Gate Node
Capacitance

C (as+aD+aB)

Drain Node
Capacitance

C (aD+DB)

Source Node
Capacitance

C(as+sB)

Reverse Transfer
Capacitance

V DS = 10 V. V SB = 0 V
I D = 20 rnA. f = 1 kHz

V DS = 10 V. f = 1 MHz
Vas =VBS = -15 V

C rss

11

10

10

10
mS

0.9
2.5

3.5

3.5

3.5

1.1

1.5

1.5

1.5

3.7

5.5

5.5

5.5

0.2

0.5

0.5

0.5

0.5

1

1

1

0.6

1

1

1

pF

SWITCHING
Turn-ON Time
Turn-OFF Time
NOTES:

td(ON)
tr
td(OFF)

V DD = 5 V. R L = 680 .0.
VIN =Ot05V

tf

2

ns

6

1. T A = 25 ·C unless otherwise noted.
2. For design aid only. not subject to production testing.

5-11

.HSiliconix
incorporated

SO/SST2100 SERIES
N-Channel Depletion-Mode Lateral DMOS FETs
The SD/SST2100 Series is a depletion-mode
MOSFET which utilizes our lateral DMOS process to
provide low capacitance, fast switching, and high
operating frequency.
This DMOS process
effectively bridges the operating frequency gap
between JFETs and costly gallium-arsenide
devices. Additionally, this series is available in both
a TO-72 hermetically sealed can as well as the
SOT-143 package for commercial applications.

V(BR)DS
MAX
(V)

rds(ON)
MAX
(.0.)

e rss
MAX
(pF)

tON
TYP
(ns)

SD2100

15

50

2

1.1

SST2100

15

50

2

1.1

PART
NUMBER

BOTTOM VIEW

TO-72

For additional design information please see
performance curves DMCD, which are located in
Section 7. Application hints can be found in LPD-12
(See Section 9).

1
2
3
4

SOURCE
DRAIN
GATE
SUBSTRATE

SIMILAR PRODUCTS
•

Chips, Order SD2100CHP

SOT-143

TOP VIEW

~

~
1
2
3
4

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

GATE
DRAIN
SOURCE
SUBSTRATE

= 25°C unless otherwise

SYMBOL

noted)

LIMIT
SD2100

SST2100

UNITS

Gate-Source Voltage

VGS

± 25

± 25

Drain-Source Voltage

VDS

25

25

Drain Current

ID

50

50

mA

Power Dissipation (TA= 25°C)

PD

350

350

mW

2.8

2.8

mW/oC

V

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

5-12

TJ

-55 to 150

T stg

-55 to 150

h

300

°C

SO/SST2100 SERIES

.:rSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
SDISST2100

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)DS

V Gs =V Bs =-5V,ID=1 J.l.A

25

15

Gate Reverse
Current

IGSS

V GS = ±25 V, V DS = V BS = 0 V

± 0.05

Saturation Drain
Current

IDSS

V DS = 10 V, VGS=V BS = 0 V

7

VGS(OFF)

V Ds -10V,I D =1J.1.A
V BS = 0 V

-1.5

PARAMETER

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage

Gate-Source Cutoff
Gate-Source
Voltage
Drain-Source
On-Resistance

V GS

V DG = 10 V
V BS = 0 V

rDS(ON)

ID - 100 J.l.A
V BS = 0 V

0.5

V

± 1

nA

10

rnA

-2

ID - 5 rnA

-0.3

-1

ID - 10 rnA
V GS - 0 V

0.4

0

120

200

V GS = 5 V

40

50

1

V

1.5
.n

DYNAMIC
Forward
Transconductance

gts

Output
Conductance

gas

Forward
Transconductance

Qts

Output
Conductance

gas

Common-Source
Input Capacitance

C lss

Reverse Transfer
Capacitance

C rss

V DS = 10 V, VGS=V BS = 0 V
f = 1 kHz

8000

1000

250

500
,lJ.S

VOG= 10 V, V BS = 0 V
I D =10mA,f=1kHz

Vos= 10V, f= 1 MHz
V GS = V BS = -5 V

10000

7000

350

500

5

6

1

2

pF

SWITCHING
Turn-ON Time
Turn-OFF Time

td(ON)
tr
tOFF

0.7
V OD = 5 V. R L = 680.n
VIN = -4 V to -2 V

0.4

ns

5

NOTES: 1. T A = 25·C unless otherwise noted.
2. For design aid only, not subject to production testing.

5-13

..

.:rSificanix

S05000 SERIES

~ incorporated

N-Channel Lateral DMOS Quad FETs
The Siliconix SD5000 Series is a monolithic array of
single-pole, single-throw analog switches designed
for high speed switching in audio, video and
high-frequency applications in communications,
instrumentation, and process control. Designed on
the Siliconix DMOS process, the SD5000 is rated for
analog signals of ±10 V, while the SD5001 and
SD5002 are rated for±5 V and ±7.5 V respectively.

PART
NUMBER

These bidirectional switches feature very low
interelectrode capacitance and on-resistance to
achieve low insertion loss, crosstalk, and
feedthrough performance. The threshold voltage
for all switches is 2 V maximum, simplifying driver
requirements for low level signal applications.

Vas (TH)
MAX
(V)
PACKAGE

rds(ON)
MAX
(il)

tON
MAX
(ns)

SD5000N

PLASTIC

2.0

70

2

SD5001N

PLASTIC

2.0

70

2

SD5002N

PLASTIC

2.0

70

2

SD50001

CERAMIC

2.0

70

2

SD50011

CERAMIC

2.0

70

2

SD50021

CERAMIC

2.0

70

2

16-PIN DIP
QUAD PLASTIC
TOP VIEW

For additional design information please see
performance curves DMCA-1 B, which are located in
Section 7.

SIMILAR PRODUCTS
•
•
•
•

16-PIN DIP
SIDE BRAZE QUAD

SO-14, See SD5400 Series
TO-18, See SD211DE Series
SOT-143, See SST211 Series
Chips, Order SD500XCHP

~

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

= 25 DC unless otherwise noted)

SYMBOL

LIMIT
SD5000

SD5001

SD5002

Gate-Source, Gate-Drain Voltage

VGS,VGO

30/-25

25/-15

30/-22.5

Drain-Substrate, Source-Substrate
Voltage

VOB,VSB

25

15

22.5

Drain-Source, Source-Drain Voltage

Vos,Vso

20

10

15

VGB

30/-0.3

25/-0.3

30/-0.3

UNITS

V
Gate-Substrate Voltage 1
Drain Current
Power Dissipation

I
I

Package
Each Device

10

50

mA

Po

640
300

mW

5.12

mW/DC

Power Derating (Package)
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 125

T stg

-65 to 150

TL

300

lThese devices feature an internal zener protected gate.
5-14

DC

S05000 SERIES

.rSiliconix

~ incorporated

LIMITS

ELECTRICAL CHARACTERISTICS 1
SD5000

SD5001

SD5002

SYMBOL

TEST CONDITIONS

TYp2

MIN

Drain-Source
Breakdown Voltage

V(BR)OS

VGS=V BS = -5 V, 10 = 10 nA

30

20

10

15

Source-Drain
Breakdown Voltage

V(BR)so

V GO =VBO = -5 V, Is = 10 nA

22

20

10

15

Drain-Substrate
Breakdown Voltage

V(BR)DB

V GS = 0 V
10=10nA

Source OPEN

35

25

15

22.5

Source-Substrate
Breakdown Voltage

V(BR)SB

V GB = 0 V
Is = 10J.lA

Drain OPEN

35

25

15

22.5

PARAMETER

MAX

MIN

MAX

MIN

MAX UNIT

STATIC

Drain-Source
Leakage

Source-Drain
Leakage

Gate Leakage
Threshold Voltage

Drain-Source
On-Resistance

I OS (OFF)

I SO (OFF)

V

VGS =VBS = -5 V

V Go =VBo =-5V

Vos = 20 V

0.9

VOS = 10 V

0.4

V Ds =15V

0.7

VS D - 20 V

1

VSO = 10 V

0.5

Vso = 15 V

0.8

I GBS

VOS=VSB=OV, V GB =30V

10-5

VGs(th)

VDS = VGS = VGS(th)' ) S = 1J.lA
V SB = 0 V

0.7

rDS(ON)

Resistance Match

ID= 1 mA
V SB = 0 V

Vas = 5 V

58

VGS = 10 V

38

VGS = 15 V

30

VGS = 20 V

26

10 = 1 mA, V SB = 0 V
VGS = 5 V

1

Vos = 10 V, V SB = 0 V
I D = 20 mA, f = 1 kHz

11

10
10
10
10

nA

10
10
1
0.1

2.0

1
0.1

2.0

0.1

70

70

1

J.lA

2.0

V

70

.0..

5

5

5

DYNAMIC
Forward
Transconductance

gf.

Gate Node
Capacitance

C (GS+GD+GB)

Drain Node
Capacitance

C (GD+DB)

Source Node
Capacitance

C (GS+SB)

Reverse Transfer
Capacitance

VOS = 10 V, f = 1 MHz
Vas =VBS = -15 V

C rss

Crosstalk

10

10

10

mS

2.5

3.5

3.5

3.5

1.1

1.6

1.6

1.6

3.7

5

5

5

0.2

0.5

0.5

0.5

pF

f = 3 kHz, See Test Circuits
In DMCA Performance Curves

-107

0.5

1

1

1

Voo= 5 V, R L = 680.0..
V rN = 5 V

0.6

1

1

1

dB

SWITCHING
Turn-ON Time
Turn-OFF Time
NOTES:

td(ON)
t,
td(OFF)
tf

2

ns

6

1. T A = 25 • C unless otherwise noted.
2. For design aid only, not subject to production testing.

5-15

-

S05400 SERIES

.-r'Siliconix

~ incorporated

N-Channel Lateral OM05 Quad FETs
The Siliconix SD5400 series is a monolithic array of
single-pole, single-throw analog switches designed
for high-speed switching in audio, video and high
frequency applications in communications, instrumentation, and process control. Designed with the
Siliconix DMOS process, the SD5400 is rated for
analog signals of ±10 V, while the SD5401 and
SD5402 are rated for ±5 V and ±7.5 V respectively.
These bidirectional switches feature very low
-interelectrode capacitance and on-resistance to
achieve low insertion loss, crosstalk, and
feedthrough performance. The threshold voltage
for all switches is 2 V maximum, simplifying driver
requirements for low level signal applications.

(V)

rds(ON)
MAX
(!l)

tON
MAX
(ns)

20

2.0

70

2

10

2.0

70

2

15

2.0

70

2

V(BR)DS

VGS(TH)

PART
NUMBER

MIN

MAX

(V)

SD5400CY
SD5401CY
SD5402CY

50-14

TOP VIEW

For additional design information please see
performance curves DMCA, which are located in
Section 7.

52

51
N/C

BOOY

G1

G2
O2

SIMILAR PRODUCTS
•
•
•
•

TO-1S, See SD211DE Series
16-Pin DIP, See SD5000 Series
SOT-143, See SST211 Series
Chips, Order SD540XCHP

01

03

04

G3

G4

53

54

ABSOLUTE MAXIMUM RATINGS (T A = 25 DC unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT
505400

505401

505402

Gate-Source, Gate-Drain Voltage

VG5,VGO

301-25

25/-15

301-22.5

Drain-Substrate, Source-Substrate
Voltage

VOB,V5B

25

15

22.5

Drain-Source, Source-Drain Voltage

V05,V50

20

10

15

VGB

301-0.3

25/-0.3

301-0.3

UNIT5

V
Gate-Substrate Voltage 1
Drain Current
Power Dissipation

I
I

Package
Each Device

10

50

rnA

Po

500
300

mW

5

mW/oC

Power Derating (Package)
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 125

T stg

-55 to 125

TL

300

1These devices feature an internal Zener protected gate.
5-16

°C

S05400 SERIES

.r-Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
SD5400CY

SD5401CY
MIN

SD5402CY

SYMBOL

TEST CONDITIONS

TYp2

MIN

Drain-Source
Breakdown Voltage

V(BR)DS

V GS =V BS = -5 V. ID = 10 nA

30

20

10

15

Source-Drain
Breakdown Voltage

V(BR)SD

V. Is = 10 nA

22

20

10

15

PARAMETER

MAX

MAX

MIN

MAX UNIT

STATIC

VGD=VBD = -5

V

Drain-Substrate
Breakdown Voltage

V(BR)DB

V GB = 0 V
ID= 10 nA

Source-Substrate
Breakdown Voltage

V(BR)SB

V GB = 0 V
Is = 10Jl.A

Drain-Source
Leakage

IDS(OFF)

VGS =VBS = -5 V

Source-Drain
Leakage

Gate Leakage
Threshold Voltage

Drain-Source
On-Resistance

ISD(OFF)

Source OPEN

35

25

15

22.5

Drain OPEN

35

25

15

22.5

VGD=VBD = -5 V

V DS = 20 V

0.9

VDS = 10 V

0.4

V Ds =15V
V SD - 20 V

0.7

V sD =10V

0.5

V SD = 15 V

0.8

I GBS

VDB=VSB=OV. V GB = 30V

VGS(th)

VDS = VGS = VGS(th)' Is = 1)J.A
V SB = 0 V
V GS = 5 V

0.7

V Gs =10V
V Gs =15V

38

V GS = 20 V

26

rDS(ON)

Resistance Match

10
10

1

10-5

ID= 1 mA
V SB = 0 V

10

10
10
10
1
0.1

58

2

1
0.1

70

2

0.1

70

1

Jl.A

2

V

70

30

ID = 1 mAo V SB = 0 V
V GS = 5 V

1

V DS = 10 V. V SB = 0 V
I D = 20 mA. f = 1 kHz

11

nA

n
5

5

5

DYNAMIC
Forward
Transc,onductance

gt.

Gate Node
Capacitance

C (GS+GD+GB)

Drain Node
Capacitance

C (GD+DB)

Source Node
Capacitance

C (GS+SB)

Reverse Transfer
Capacitance

V DS = 10 V. f = 1 MHz
V GS =V BS = -15 V

C rss

f = 3 kHz. See Test Circuits
in DMCA Performance Curves

Crosstalk

10

10

10

mS

2.5

3.5

3.5

3.5

1.1

2

2

2

3.7

6

6

6

0.2

0.5

0.5

0.5

pF

-107

dB

SWITCHING
Turn-ON Time
Turn-OFF Time
NOTES:

td(ON)
t,
td(OFF)

V DD = 5 V. RL = 680
VIN = 5 V

n

tt

0.5

1

1

1

0.6

1

1

1

2
6

ns

1. T A = 25·C unless otherwise noted.
2. For design aid only. not subject to production testing.

5-17

.:r-Siliconix

Si8901 SERIES

~ incorporated

DMOS Double-Balanced Mixers
The Si8901 Ring Demodulator/Balanced Mixer offers
significant improvements for RF mixer application
where low third order harmonic distortion has been
Combining matching with very low
a problem.
junction capacitance, « 3 pF), low on-resistance
(30 0) and very high off-resistance (> 109 0), the
Si8901 accepts an RF and a local oscillator (LO)
input and provides a high fidelity IF output with
typical conversion loss of -8 dB at frequencies up
to 200 MHz. Available in an 8-pin TO-78 and SO-14
package, this device is specified over -55 to 125°C
temperature range.

V(BR)DS Vas(th)
MAX
MIN
PACKAGE
(V)
(V)

PART
NUMBER

rds(ON)
MAX
(0)

Si8901A

TO-78

15

2.0

70

Si8901CY

SO-14

15

2.0

70

TOP VIEW

SO-14
LO 1
SUB

RF2

L02

RF1

SUB

SUB

SUB

IF2

•

SUB

SUB

N/C

-,'_ _"r- N/C

BOTTOM VIEW

TO-78

SIMILAR PRODUCTS

IF1

Chips, order Si8901CHP

IF,
2 RF,
3 RF2
4 SUB

ABSOLUTE MAXIMUM RATINGS (T A = 25 DC unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT
Si8901A

Si8901CY

Gate-Source, Gate-Drain Voltage

Vas,Vao

30/-22.5

30/-22.5

Drain-Substrate, Source-Substrate
Voltage

VOB,VSB

22.5

22.5

Drain-Source Voltage

Vos

15

15

Gate-Substrate Voltage 1

VaB

30/-0.3

30/-0.3

UNITS

V

Drain Current
Power Dissipation

(Package)

10

50

mA

Po

500

mW

5

mW/oC

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ

-55 to 125

T stg

-65 to 150

TL

300

'These devices feature an internal Zener protected gate.
5-18

°C

g

Si8901 SERIES

Siliconix

incorporated

EL.ECTRICAL. CHARACTERISTICS 1

LIMITS
SI8901A

SI8901CY

SYMBOL

TEST CONDITIONS

TYP 2

MIN

Drain-Source
Breakdown Voltage

V(BR)OS

V GS = V BS = -5 V, 10= 10 nA

30

15

15

Source-Drain
Breakdown Voltage

V(BR)SO

VGO=VBO = -5 V, Is = 10 nA

22

15

15

Drain-Substrate
Breakdown Voltage

V(BR)OB

V GB = 0 V
lo=10nA

Source OPEN

35

22.5

22.5

Source-Substrate
Breakdown Voltage

V(BR)SB

V GB = 0 V
Is=10nA

Drain OPEN

35

22.5

22.5

Drain-Source
Leakage

I OS (OFF)

V GS =V BS = -5 V, VOS = 15 V

0.7

Source-Drain
Leakage

I SO (OFF)

VGO=VBO = -5 V, VSO = 15 V

0.8

Gate Leakage

I GBS

V OB =VSB = 0 V, V GB = 30 V

0.01

VGs(th)

Vos = VGS = VGS(th)' Is = 1JJ.A
V SB = 0 V

0.7

PARAMETER

MAX

MIN

MAX

UNIT

STATIC

Threshold Voltage

Drain-Source
On-Resistance

V

nA

rOS(ON)

lo=10mA
V SB = 0 V

V GS = 5 V

60

VGs =10V
VGs=15V

40

VGs= 20 V

29

10= 10 mA, V SB = 0 V
V GS = 5 V

Resistance Match

2
0.1

0.1

2
75

2

JJ.A

2

V

75

33

n.

1

7

7

DYNAMIC
L01- L02
Capacitance
Conversion Loss

C gg

Vos - 0 V, VBS - -5.5 V
V GS = 4 V

4.4

pF

8

Lc
See Figure 1, P LO = +17 dBm

dB

Third Order
Intercept

IMDa

35

Maximum Operation
Frequency

fMAX

250

NOTES:

MHz

1. T A = 25·C unless otherwise noted.
2. For design aid only, not subject to production testing.

LOW-PASS
IMAGE TERMINATING
FILTER
(OPTIONAL)

I

680

-

T4-1

Figure 1

pF

t

u

~-vu

'J

680

pF

5-19

--

.-r-Siliconix

SST211 SERIES

~ incorporated

N-Channel Lateral DMOS FETs

The SST211 Series is a single-pole, single-throw
analog switch designed for high speed switching in
audio, video, and high-frequency applications.
These devices are designed on the Siliconix DMOS
process and utilize lateral construction to achieve
low capacitance and ultra-fast switching speeds.
These devices also feature an integrated Zener
diode designed to protect the gate from electrical
" spikes" or overstress.

V(BR)OS
MAX
(V)

rds(ON)
MAX
(il)

C rss
MAX
(pF)

tON
MAX
(ns)

SST211

10

50

0.5

2

SST213

10

50

0.5

2

SST215

20

50

0.5

2

PART
NUMBER

For additional design information please see
performance curves DMCB, which are located in
Section 7.

1
2
3
4

SIMILAR PRODUCTS
•
•
•
•

TOP VIEW

SOT-143

:8:

SOURCE
DRAIN
GATE
SUBSTRATE

PRODUCT MARKING

TO-18, See SD211DE Series
Quad Array, See SD5000 Series
SO-14 Array, See SD5400 Series
Chips, Order SD21XCHP

SST211

Dll

SST213

D13

SST215

D15

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

LIMIT

UNITS

SST211

SST213

SST215

VGS,VGO

-30/25

-15/25

-25/30

Gate-Substrate Voltage 1

VGB

-0.3/25

-0.3/25

-0.3/30

Drain-Source Voltage

Vos

30

10

20

Source-Drain Voltage

VSO

10

10

20

Drain-Substrate Voltage

VOB

30

15

25

Source-Substrate Voltage

VSB

15

15

25

Drain Current

10

50

50

50

mA

Power Dissipation

Po

350

350

350

mW

2.8

2.8

2.8

mW/oC

Gate-Source, Gate-Drain Voltage

Power Derating
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)
1These devices feature an internal Zener diode
5-20

TJ

-55 to 150

T stg

-65 to 150

lL

300

V

°C

SST211 SERIES

.:rSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
SST211

PARAMETER

SYMBOL

SST213

SST215

TYp2

MIN

ID = 10.IJ.A

35

30

VGS =V ss = -5 V. Is = 10 nA

30

10

10

20

TEST CONDITIONS

MAX

MIN

MAX

MIN

MAX UNIT

STATIC
VGS =VBS =

a v.

Drain-Source
Breakdown Voltage

V(BR)DS

Source-Drain
Breakdown Voltage

V(SR)SD

VGD=V SD = -5 V. ID = 10 nA

22

10

10

20

Drain-Substrate
Breakdown Voltage

V(SR)DS

V GS = a V
I D =10nA

Source OPEN

35

15

15

25

Source-Substrate
Breakdown Voltage

V(SR)SS

V GS = a V
Is = 10.IJ.A

Drain OPEN

35

15

Drain-Source
Leakage

I DS(OFF)

VGS =VSS = -5 V

0.4
0.9

10

10

V SD = 10 V
V sD -20V

0.5

10

10

ISD(OFF)

Gate Leakage

IGSS

V DS =Vss = 0 V. V GS = ±25 V

10-5

VGs(th)

VDS = VGS = VGS(th)' Is = 1.IJ.A
Vss = a V

0.7

Threshold Voltage

Drain-Source
On-Resistance

rDS(ON)

ID= 1 mA
Vss =

aV

25

V Ds =10V
V DS = 20 V

Source-Drain
Leakage

V GD =VSD =-5V

15

V

10
10

1
10
0.5

2

10
0.1

2

0.1

nA

10

.lJ.A

2

V

VGs= 5 V

56

75

75

75

V Gs =10V

36

50

50

50

VGS = 15 V

30

VGS= 20 V

26

V Gs =25V

24

.n

DYNAMIC
Forward
Transconductance

gfs

Output
Conductance

gos

Gate Node
Capacitance

C (GS+GD+GB)

Drain Node
Capacitance

C(GD+DB)

Source Node
Capacitance

C(GS+SB)

Reverse Transfer
Capacitance

V DS = 10 V. Vss = a v
I D = 20 mAo f = 1 kHz

V DS = 10 V. f = 1 MHz
VGS =Vss = -15 V

C rss

11

9

9

9
mS

0.9
2.5

3.5

3.5

3.5

1.1

1.5

1.5

1.5

3.7

6

6

6

0.2

0.5

0.5

0.5

0.5
0.6

1

1

1

1

1
1

pF

SWITCHING
Turn-ON Time
Turn-OFF Time
NOTES:

td(ON)
tr
td(OFF)

V DD = 5 V. RL = 660
VIN =Oto5V

.n

tf

2

ns

6

1. T A = 25 0 C unless otherwise noted.
2. For design aid only. not subject to production testing.

5-21

General Information
Cross Reference
Selector Guide

JFETs
DMOS
low Power MOS
Performance Curves
Package Outlines
Applications
Worldwide Sales Offices and Distributors '::.;.

~Siliconix

~ incorporated

LOW POWER MOS
INTRODUCTION

Low Power MOS products from Siliconix utilize a vertical DMOS process to offer a wide range of
both n- and p-channel Enhancement-mode and n-channel Depletion-mode devices. The vertical
structure allows high breakdown voltage, low on-resistance, low capacitance, and fast switching. Inherent in its MOS process, these devices also feature a high-impedance gate and
freedom from the thermal runaway typically associated with bipolar devices.
To meet a wide range of applications Siliconix' Low Power MOS product line features n-channel
Enhancement-mode devices with breakdown voltages ranging from 30 - SOO volts, onresistance as low as 1.2 .0, and many devices with threshold voltages less than 2.S volts. Pchannel devices designed to complement n-channel products are offered with breakdown
voltage ranging from 30 - 240 volts, on-resistance as low as 1.8.0, and a family of low threshold
devices again with threshold voltages less than 2.S volts.
A recent unique addition to this product line was a family of high voltage n-channel Depletionmode products. This series features normally "on" operation, breakdown voltage up to 240
volts, and on-resistance as low as 6 .0. Depletion-mode performance is perfect for use in telecommunications and industrial process control applications.
Packaging options are diverse and include SOT-23, TO-92, TO-237, and 14-pin DIPs for commercial applications and TO-39, TO-S2, and 14-pin ceramic packages for demanding industrial
or military applications. Full military processing is available per MIL-S-19S00 on all hermetically
sealed packages.
For additional technical information please see "High-Side Switching" (LPD-17), "Depletionmode Applications" (LPD-18), "Logic compatable MOS" (LPD-19), and "FETs in Telecom"
(LPD-16). These application notes are located in section nine and provide useful design tips and
device information.

6-1

.:r-Siliconix

2N6659

~ incorporated

N-Channel Enhancement-Mode MOS Transistor

PRODUCT SUMMARY
BOTTOM VIEW

TO-205AD (TO-39)
V(BR)OSS
(V)

rOS(ON)
(.0)

10
(A)

PACKAGE

35

1.8

1.4

TO-205AD
1 SOURCE
2 GATE
3 DRAIN & CASE

Performance Curves: VNDQ06 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TC
PARAMETERS/TEST CONDITIONS

= 25°C unless
SYMBOL

otherwise noted)
2N6659

Drain-Source Voltage

Vos

35

Gate-Source Voltage

VGS

±20

UNITS

V

1.4

Tc= 25°C
Continuous Drain Current 1

10

1

Tc = 100°C
Pulsed Drain Current 1

10M

Tc= 25°C
Power Dissipation

3
6.25

Po
2.5

Tc = 100°C
Tj

-55 to 150

Tstg

-55 to 150

TL

300

SYMBOL

2N6659

Junction-to-Ambient 2

RthJA

170

Junction-to-Case

RthJC

20

Operating Junction Temperature
Storage Temperature 2
Lead Temperature
(1/16" from case for 10 seconds)

A

W

°C

THERMAL RESISTANCE
THERMAL RESISTANCE

UNITS

°C/W

1Pulse width limited by maximum junction temperature
2This parameter not registered with JEDEC

6-2

2N6659

.-r-Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N6659

PARAMETER

TYp2

MIN

SYMBOL

TEST CONDITIONS

V(BR)OSS

V Gs =OV,l o =10JJ.A

70

35

Vos = VGS, 10 = 1 mA

1.5

0.6

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current

V
VGS(th)
IGSS

loss

On-State Drain
Current 3

10(ON)

Drain-Source
On-Reslstance 3

rOS(ON)

Vos = a V
V Gs =±lSV
VGS =

aV

I

To = 125°C

IVOS = 35 V
I VOS = 26 V,

To = 125°C

Vos = 10 V, VGS = 10 V
4V GS = 5 V, 10 = 0.3 A
VGS = 10 V
10 = 1 A

1

4T o=12SoC

4VGS = 5 V, 10 = 0.3 A
Drain-Source
On-Voltage 3

VOS(ON)

VGS = 10 V
10 = 1 A

I

4To= 125°C

2

±1

+100

+5

+500

0.05

10

0.3

500

1.6

1.5

nA

JJ.A
A

1.6

5

1.3

1.6

2.6

3.6

0.54

1.5

1.3

1.6

2.6

3.6

~~~;~~nduotance3

gFS

Vos = 10 V, 10 = 0.5 A

350

Common Source
Output Conductance 3,4

gos

Vos = 10 V, 10 = 0.1 A

1100

rdS(ON)

VGs=10V,lo=lA
1 = 1 kHz

1.3

1.6

Drain-Source
Capacitance

Cds

V os =24V,V Gs =OV
f = 1 MHz

30

40

Input Capacitance

C 1SS

36

50

26

40

6

10

Voo = 25 V, R L = 23.0.
10 = 1 A, V GEN = 10 V, RG = 25.0.

6

10

(Switching time Is essentially Independent
01 operating temperature)

9

10

170

.0.

V

mS
JJ.S

DYNAMIC
Small Signal DralnSource On-Resistance

pF

Vos = 24 V
Output Capacitance 4

Coss

Reverse Transfer
Capacitance

C rss

VGS =

aV

.0.

f = 1 MHz

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES:

1.
2.
3.
4.

ns

To = 25 ° C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 60 JJ.S, duty cycle ~ 1 % .
This parameter not registered with JEDEC.

6-3

.rSiliconix

2N6660

~ incorporated

N-Channel Enhancement-Mode MOS Transistor

PRODUCT SUMMARY
BOTTOM VIEW

TO-20SAD (TO-39)
V(BR)eSS
(V)

restoN)
(0)

Ie
(A)

PACKAGE

60

3

1.1

TO-205AD
1 SOURCE
2 GATE
3 DRAIN & CASE

Performance Curves: VNDQ06 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (Tc

= 25°C unless otherwise noted)
SYMBOL

PARAMETERS/TEST CONDITIONS

2N6660

Drain-Source Voltage

Ves

60

Gate-Source Voltage

VGS

±20

UNITS

V
Tc= 25DC

1.1

Continuous Drain Current

Ie
0.8

Tc = 100DC
Pulsed Drain Current 1

10M

Tc= 25DC
Power Dissipation

A

3
6.25

Po

Tc = 100DC

2.5

Operating Junction Temperature 2

TJ

-55 to 150

T stg

-55 to 150

lL

300

SYMBOL

2N6660

Junction-to-Ambient 2

RthJA

170

Junction-to-Case

RthJC

20

Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

W

DC

THERMAL RESISTANCE
THERMAL RESISTANCE

UNITS

DC/W

1Pulse width limited by maximum junction temperature
2This parameter not registered with JEDEC

6-4

2N6660

.-r'Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N6660

PARAMETER

TEST CONDITIONS

SYMBOL

TYp2

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3

V(BR)OSS

V GS ; 0 V, 10 ; 10 JlA

70

60

Vos; VGS' 10 ; 1 mA

1.5

0.8

V
VGS(th)

Vos ; 0 V
V GS ; ±15 V

IGSS

loss
10(ON)

vGS

; 0V

1Vos ;

I

T c ;125°C

60 V

IVos; 48 V, Tc; 125°C

Vos ; 10 V, V GS ; 10 V
4 V GS ; 5 V, 10 ; 0.3 A

Drain-Source
On-Reslstance 3

rOS(ON)

V GS ; 10 V
10 ; 1 A

I

4T c ;125°C

4VGS ; 5 V, 10 ; 0.3 A
Drain-Source
On-Voltage 3

VOS(ON)

V GS ; 10 V
10 ; 1 A

I

4T c ;125°C

2

±1

±100

+5

+500

0.05

10

0.3

500

1.8

1.5

1.8

nA

JlA
A

5

1.3

3

2.6

4.2

0.54

1.5

1.3

3

2.6

4.2

~~~~:~~nductance 3

gFS

Vos ; 10 V, 10; 0.5 A

350

Common Source
Output Conductance 3 ,4

gos

Vos; 10 V, 10 ; 0.1 A

1100

rds(ON)

V Gs ;10V,1 0 ;1A
1- 1 kHz

1.3

3

Drain-Source
Capacitance

Cds

Vos ; 24 V, V GS ; 0 V
I ; 1 MHz

30

40

Input Capacitance

Ciss

38

50

28

40

8

10

8

10

9

10

170

,n

V

mS
JlS

DYNAMIC
Small Signal DrainSource On-Resistance

pF

VOS ; 24 V
Output Capacltance 4

Coss

Reverse Transfer
Capacitance

erss

V GS ; 0 V

,n

I ; 1 MHz

SWITCHING
Turn-On Time

tON

Turn-all Time

t OFF

NOTES:

1.
2.
3.
4.

VOO ; 25 V, R L ; 23 ,n
10;1A,VGEN ; 10 V, R G ; 25,n
(Switching time Is essentially Independent
01 operating temperature)

ns

T c; 25°C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW ; 80 JlS, duty cycle!> 1 % .
This parameter not registered with JEDEC.

6-5

crSiliconix

2N6660 JANTX, JANTXV

~ incorporated

N-Channel Enhancement-Mode MOS Transistor

PRODUCT SUMMARY
BOTTOM VIEW

TO-205AD (TO-39)
V(BR)OSS
(V)

rOS(ON)
(0)

(A)

PACKAGE

60

3

0.99

TO-205AD

10

1 SOURCE
2 GATE
3 DRAIN & CASE

Performance Curves: VNMA06 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TC

= 25°C unless otherwise noted)
SYMBOL

2N6660

Drain-Source Voltage

Vos

60

Gate-Source Voltage

VGS

±20

PARAMETERS/TEST CONDITIONS

UNITS

V
0.99

Tc= 25°C
Continuous Drain Current

10

0.62

Tc = 100°C
Pulsed Drain Current 1

10M

Tc= 25°C
Power Dissipation

3
6.25

Po
0.725

TA= 25°C
Operating Junction Temperature

TJ

-65 to 150

T stg

-65 to 175

TL

300

SYMBOL

2N6660

Junction-to-Ambient

RthJA

170

Junction-to-Case

RthJC

20

Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

A

W

°C

THERMAL RESISTANCE
THERMAL RESISTANCE

UNITS

°C/W

1 Pulse width limited by maximum junction temperature

6-6

2N6660 JANTX, JANTXV

tcrSiliconix
.LII incorporated
ELECTRICAL CHARACTERISTICS 1

LIMITS
2N6660

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BA)OSS

VGS = 0 V, 10 = 10JlA

90

60

1.5

0.8

MAX

UNIT

2

V

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3, 4
Drain-Source
On-Reslstance3, 5

VGS(th)

Vos = VGS
10 = 1 mA

IGSS

Vos = 0 V
VGS =±20 V

loss
10(ON)

rOS(ON)

VGS = 0 V

I
I
I

To = -55°C
To=125°C
To = 125°C

IVos = 48 V

IVos = 48 V, To = 125°C

VOS(ON)

1

+100
+100

0.0004

1

2

100

2
3.5

I

Tc=125°C

VGS = 10 V
10 = 1 A

I

To = 125°C

0.3

±5

V Gs =5V,l o =0.3A
VGS = 10 V
10 = 1 A

2.5

±1

Vos = 7.5 V, VGS = 10 V

VGS = 5 V, 10 = 0.3 A
Drain-Source
On-Voltage 3

1.9

A

3

4

5.6

1.05

1.5

2.25

3

4

5.6

~~~~~~nductance 3

VOS = 7.5 V, 10 = 0.525 A

275

Common Source
Output Conductance3 ,4

gos

Vos = 7.5 V, 10 = 0.1 A

900

JlA

5

2.25

gFS

nA

170

.n

V

mS
JlS

DYNAMIC
Input Capacitance

Ciss

30

50

30

40

5

10

7

10

6

10

Vos = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

VGS = 0 V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

t OFF

VOO = 25 V, R L = 23 .n
10 = 1 A, V GEN = 10 V
RG=50.n
(Switching time Is essentially independent of
operating temperature)

SOURCE-DRAIN DIODE RATINGS & CHARACTERISTICS 1

ns

LIMITS
2N6660

PARAMETER
Forward Voltage
NOTES:

1.
2.
3.
4.
5.

SYMBOL

TEST CONDITIONS

TYp2

Vso

Is=0.99A

0.8

MIN

MAX

UNIT

0.7

1.6

V

To = 25 ° C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 80 JlS, duty cycle ~ 1% .
This parameter not registered with MIL-S-19500/547A.
Not a measured value rOS(ON) =VOS(ON) " 0 ,

6-7

.:r-Siliconix

2N6661

~ incorporated

N-Channel Enhancement-Mode MOS Transistor

PRODUCT SUMMARY
TO-20SAD (TO-3S)
V(BR)OSS
(V)

rOS(ON)
(0)

(A)

PACKAGE

SO

4

O.S

TO-205AD

BOTTOM VIEW

10

1 SOURCE
2 GATE
3 DRAIN & CASE

Performance Curves: VNDC09 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

2N6661

Drain-Source Voltage

Vos

SO

Gate-Source Voltage

VGS

±20

UNITS

V
0.9

Tc= 25°C
Continuous Drain Current

10

0.7

Tc = 100°C
Pulsed Drain Current 1

10M

Tc= 25°C

A

3
6.25

Power Dissipation

Po
2.5

Tc = 100°C
Operating Junction Temperature 2

TJ

-55 to 150

T stg

-55 to 150

TL

300

SYMBOL

2N6661

Junction-to-Ambient 2

RthJA

170

Junction-to-Case

RthJC

20

Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

W

°C

THERMAL RESISTANCE
THERMAL RESISTANCE

UNITS

.oC/W

1Pulse width limited by maximum junction temperature
2This parameter not registered with JEDEC

6-8

7

.:r-Siliconix

2N6661

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N6661

PARAMETER

TYp2

SYMBOL

TEST CONDITIONS

MIN

V(BR)DSS

VGS =OV,I D =10J.lA

120

90

VGS(th)

V DS = V GS , ID = 1 mA

1.6

0.8

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Resistance 3

V

IGSS

IDSS
ID(ON)

rDS(ON)

V DS = 0 V
VGS = ±15 V
V GS = 0 V

I

Tc=125°C

IVDS = 90 V
IVDS = 72 V, Tc = 125°C

VDS(ON)

+1

±100

+5

±500

0.03

10

0.3

500

V DS = 15 V, V GS = 10 V

1.8

4VGs =5V,I D =0.3A

4.2

5.3

3.6

4

6.8

9

1.26

1.6

3.6

4

6.8

9

V GS = 10 V
ID = 1 A

I

4Tc = 125°C

4V Gs =5V,I D =0.3A
Drain-Source
On-Voltage 3

2

V GS = 10 V
ID = 1 A

I

4Tc = 125°C

1.5

nA

J.lA
A

~~~~:~~nductance 3, 4

gFS

V DS = 10 V, ID = 0.5 A

350

Common Source
Output Conductance3,4

gos

VOS = 10 V, 10 = 0.1 A

225

rdS(ON)

V GS = 10 V, ID = 1 A
1 = 1 kHz

3.6

4

Drain-Source
Capacitance

Cds

V os =24V,V Gs =OV
1 = 1 MHz

30

40

Input Capacitance

C iss

35

50

15

40

2

10

6

10

8

10

170

.0.

V

mS
J.lS

DYNAMIC
Small Signal DralnSource On-Resistance

Output Capacitance 4

Coss

Reverse Transfer
Capacitance

C rss

Vos = 24 V
V GS = 0 V

.0.

pF

1 = 1 MHz

SWITCHING
Turn-On Time

tON

Turn-Off Time

t OFF

NOTES:

1.
2.
3.
4.

V OD = 25 V, R L = 23 .0.
10 = 1 A, V GEN = 10 V, RG = 25.0.
(Switching time Is essentially Independent
01 operating temperature)

ns

T c = 25°C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 80 J,lS, duty cycle S 1%.
This parameter not registered with JEDEC.

6-9

.r'Siliconix

2N6661 JANTX, JANTXV

~ incorpora.ted

N-Channel Enhancement-Mode MOS Transistor

PRODUCT SUMMARY
TO-205AD (TO-39)
V(BR)OSS
(V)

rOS(ON)
(0 )

(A)

PACKAGE

90

4

0.86

TO-205AD

BOTTOM VIEW

10

1 SOURCE
2 GATE
3 DRAIN & CASE

Performance Curves: VNMA09 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TC
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise noted)
SYMBOL

2N6661

Drain-Source Voltage

VOS

90

Gate-Source Voltage

VGS

±20

UNITS

V

0.86

Tc= 25°C
Continuous Drain Current

10

0.54

Tc = 100°C
Pulsed Drain Current 1

10M

Tc= 25°C

A

3
6.25

Power Dissipation

Po
0.725

TA= 25°C
Operating Junction Temperature

TJ

-65 to 150

Storage Temperature

Tstg

-65 to 175

Lead Temperature
(1/16" from case for 10 seconds)

lL

300

SYMBOL

2N6661

Junction-to-Ambient

RthJA

170

Junction-to-Case

RthJC

20

W

°C

THERMAL RESISTANCE
THERMAL RESISTANCE

UNITS

°C/W

1Pulse width limited by maximum junction temperature
6-10

2N6661 JANTX, JANTXV

wrSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N6661

PARAMETER

TEST CONDITIONS

SYMBOL

TYp2

MIN

MAX

UNIT

2

V

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3,4

V(BR)OSS

Vas=OV,10=10Jl.A

VaS(th)

Vos = Vas
10 = 1 mA

lass

Vos = 0 V
Vas = ±20 V

loss
10(ON)

Vas = 0 V

I

rOS(ON)

VOS(ON)

To=125°C

0.8
+1

r

To = 125°C

±5
0.01

±100

30

100

VOS = 10 V, Vas = 10 V

Vas = 10 V
10 = 1 A

0.8

I

I

To = 125°C

Vas=5V,10=0.3A
Drain-Source
On-Voltage 3

1.3
1.7

IVos = 72 V
IVos = 72 V, To = 125°C

Vas = 10 V
10 = 1 A

90

To = -55°C

Vas = 5 V, 10 = 0.3 A
Drain-Source
On-Reslstance3, 5

130

r

To=125°C

2.5
0.3
±100
1

1.7
4.3

5.3
4

5

7.5

1.3

1.6

2.75

4

5

7.5

gFS

Vos = 7.5 V, 10 = 0.475 A

250

Common Source
Output Conduotance3,4

gos

Vos =7.5V,1 0 =0.1 A

425

Jl.A
A

2.75

~~~:6~nduotance 3

nA

170

.0.

V

mS
Jl.S

DYNAMIC
Input Capacitance

Clss

Output Capaoltanoe

Coss

Reverse Transfer
Capacitance

C rss

30

50

30

40

5

10

8.5

10

9.6

10

Vos = 25 V
Vas = 0 V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

VOO = 25 V, R L - 23.0.
10 = 1 A, V aEN = 10 V
Ra = 50.0.
(Switching time Is essentially Independent of
operating temperature)

SOURCE.DRAIN DIODE RATINGS & CHARACTERISTICS 1

ns

LIMITS
2N6661

PARAMETER
Forward Voltage
NOTES; 1.
2.
3.
4.
5.

SYMBOL

TEST CONDITIONS

TYp2

VSO

Is = 0.86 A

0.9

MIN
0.7

MAX

UNIT

1.4

V

To = 25 ° C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 80 Jl.S, duty cycle S 1%.
This parameter not registered with MIL-S-19500/547A.
Not a measured value rOS(ON) =VOS(ON)"O'

6-11

wrSiliconix

2N7000

~ incorporated

N-Channel Enhancement-Mode MOS Transistor

TO-92

PRODUCT SUMMARY
V(BR)OSS
(V)

rOS(ON)
(n)

10
(A)

PACKAGE

60

5

0.2

TO-92

BOTTOM VIEW

1 SOURCE
2 GATE
3 DRAIN
Performance Curves: VNDS06 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TC

= 25°C unless otherwise noted)

PARAMETERS/TEST CONDITIONS

SYMBOL

2N7000

Drain-Source Voltage

Vos

60

Gate-Source Voltage

VGS

±40

UNITS

V
±0.2

Tc= 25°C
Continuous Drain Current

10

0.13

Tc = 100°C
Pulsed Drain Current 1

10M

Pulsed Power Dissipation 2

A

0.5
3.1

Tc= 25°C
Power Dissipation

0.4

W

Po
0.16

Tc = 100°C
Tj

-55 to 150

Tstg

-55 to 150

TL

300

SYMBOL

2N7000

Junction-to-Ambient

RthJA

312.5

Junction-to-Case

RthJC

40

Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

°C

THERMAL RESISTANCE
THERMAL RESISTANCE

UNITS

°C/W

1Pulse width limited by maximum junction temperature
20ne second single, power pulse

6-12

2N7000

~Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N7000

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

VIBR)OSS

V Gs =OV,l o =10J.lA

70

60

Vos = VGS, 10 = 1 mA

2.3

0.8

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current

V
VGSlth)
IGSS

loss

On-State Drain
Current 3

1010N)

Drain-Source
On-Resistance 3

rOSION)

Vos = 0 V
VGS = :tIS V
VGS = 0 V

+ 1

I

4To = 125°C

IVOS = 48 V

IVos = 48 V, To = 125°C

VOSION)

~~~~:~~nductance 3

gls

Common Source
Output Conductance 3,4

gos

+10

0.001

1

0.02

1000

210

4VGS = 4.5 V, 10 = 75 mA

4.8

5.3

2.5

5

4.4

9

VGS = 10 V
lo=0.5A

I

To=125°C

VGS = 10 V
10 = 0.5 A

I

4To = 125°C

VOS = 10 V, 10= 0.2 A
f = 1 kHz
VOS = 5 V, 10 = 50 mA

nA

+ 5

VOS = 10 V, VGS = 4.5 V

4V GS = 4.5 V, 10 = 75 mA
Drain-Source
On-Voltage 3

3

75

mA

0.36

0.4

1.25

2.5

2.2

4.5

170

J.lA

100

.n.

V

mS

500

J.lS

DYNAMIC
Input Capacitance

C lss

16

60

11

25

2

5

7

10

7

10

Vos = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

erss

VGS = 0 V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

t OFF

NOTES:

1.
2.
3.
4.

Voo= 15 V, RL= 25.n.
10 = 0.5 A, VGEN = 10 V
RG = 25.n.
(Switching time Is essentially independent of
operating temperature)

ns

T A = 25°C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW =300J.ls, duty cycle S3%.
This parameter not registered with JEDEC.

6-13

.r'Siliconix

2N7001

~ incDrpDrated

N-Channel Enhancement-Mode MOS Transistor

SOT-23

PRODUCT SUMMARY
V(BR)OSS
(V)

rOS(ON)
(0)

(A)

PACKAGE

240

45

0.045

SOT-23

TOP VIEW

10

1 GATE
2 SOURCE
3 DRAIN
Performance Curves: VNDN24 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (T c
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise noted)
SYMBOL

2N7001

Drain-Source Voltage

Vos

240

Gate-Source Voltage

VGS

±40

UNITS

V
0.045

Tc= 25°C
Continuous Drain Current

10

0.029

Tc = 100°C
Pulsed Drain Current 1

10M

Tc= 25°C

A

0.21
200

Power Dissipation

mW

Po
80

Tc = 100°C
Tj

-55 to 150

Tstg

-55 to 150

TL

300

SYMBOL

2N7001

UNITS

RthJA

625

°C/W

Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

°C

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient
1Pulse width limited by maximum junction temperature

6-14

2N7001

fCrSiliconix

~ incorporated
ELECTRICAL CHARACTERISTICS 1

LIMITS
2N7001

PARAMETER

TEST CONDITIONS

SYMBOL

TYp2

MIN

270

240

1.85

1

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current

Vas =

V(BR)OSS

a V,

10 = 100.l1A

V
Vos = Vas, 10 = 0.25 mA

VaS(th)
lass

loss

On-State Drain
Current 3

10(ON)

Drain-Source
On-Reslstance 3

rOS(ON)

Vos = 0 V
Vas = ±20 V
Vas =

aV

4TO = 125°C

IVos = 120 V
IVos = 120 V, To = 125°C

VOS(ON)

~~~:~~nductance 3

gFs

Common Source
Output Conductance 3 ,4

gos

0.001

0.1

0.5

1

750

Vas = 10 V, 10 = 50 mA

35

85

40

45

80

85

1.75

2.25

0.8

0.9

1.6

1.7

4Vas = 4.5 V
10 = 20 mA

I

To=125°C

4Vas = 4.5 V
10 = 20 mA

I

To= 125°C

nA

±5

Vos = 10 V, Vas = 10 V

Vas = 10 V, 10 = 50 mA
Drain-Source
On-Voltage 3

+10

±1

I

2.5

80

100

.I1A
mA

30

.0.

V

mS

Vos = 10 V, 10 = 50 mA
10

.I1S

DYNAMIC
Input Capacitance

C lss

15

30

4

15

1

10

7

30

18

20

Vos = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

Vas = 0 V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES:

1.
2.
3.
4.

Voo=60V, RL=1.2k.n
10 = 50 mA, VGEN = 10 V
Ra = 25.0.
(Switching time Is essentially Independent of
operating temperature)

ns

To = 25°C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 80 .I1s, duty cycle;!; 1% .
This parameter not registered with JEDEC.

6-15

g

2N7002

Siliconix

incorporated

N-Channel Enhancement-Mode MOS Transistor

SOT-23

PRODUCT SUMMARY
V(BR)OSS
(V)

rOS(ON)
(.n )

(A)

PACKAGE

60

7.5

0.115

SOT-23

TOP VIEW

~
~

10

1 GATE
2 DRAIN
3 SOURCE
Performance Curves: VNDS06

(See Section 7)

ABSOLUTE MAXIMUM RATINGS (TC
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise noted)
SYMBOL

2N7002

Drain-Source Voltage

Vos

60

Gate-Source Voltage

VGS

±40

UNITS

V
± 0.115

Tc= 25°C
Continuous Drain Current

10

± 0.073

Tc = 100°C
Pulsed Drain Current 1

10M

Tc= 25°C

A

0.8
200

Po

Power Dissipation
Tc = 100°C
Operating Junction Temperature

mW
80

TJ

-55 to 150

T stg

-55 to 150

TL

300

SYMBOL

2N7002

UNITS

RthJA

625

°C/W

Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

°C

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient
1Pulse width limited by maximum junction temperature

6-16

~Siliconix

2N7002

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N7002

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

V(BR)OSS

V GS = 0 V, 10 = 10JlA

70

60

2.15

1

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3

Drain-Source
On-Reslstance 3

V
VGS(th)
IGSS

loss
10(ON)

Vos = V GS , 10 = 0.25 mA
Vos = 0 V
VGs =±20V
V GS = 0 V
Vos = 60 V

To = 125°C

I

To= 125°C

Vos 2: 2 VOS(ON) , VGS = 10 V
V GS = 5 V
10=50mA

rOS(ON)
V Gs =10V
10 = 0.5 A

r
I

To=125°C

To=125°C

V GS = 5 V, 10 = 50 mA
Drain-Source
On-Voltage 3

VOS(ON)

V GS = 10 V
10 = 0.5 A

+100

+ 1

I

1 4T o =125°C

2.5
nA

± 5
0.02

1

1

500

1000

500

mA

5

7.5

9

13.5

2.5

7.5

4.4

13.5

0.25

0.375

1.25

3.75

2.2

6.75

~~~~:~~nduotance 3

gfs

VOS = 10 V, 10 = 0.2 A
f = 1 kHz

170

Common Source
Output Conductance3 ,4

gos

Vos =5V, 10=50mA

500

JlA

80

.n

V

mS
JlS

DYNAMIC
Input Capacitance

Ciss

16

50

11

25

2

5

7

20

7

20

Vos = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

V GS = 0 V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES:

1.
2.
3.
4.

VOO = 30 V, RL= 150.010 = 0.2 A, V GEN = 10 V
RG=25.n
(Switching time Is essentially Independent of
operating temperature)

ns

To = 25 ° C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 80 JlS , duty cycle !$ 1% .
This parameter not registered with JEDEC.

6-17

~Siliconix

2N7007

~ incorporated

N-Channel Enhancement-Mode MOS Transistor

BOTTOM VIEW

TO-92

PRODUCT SUMMARY
V(BR)OSS
(V)

rOS(ON)
(.n )

10
(A)

PACKAGE

240

45

0.065

TO-92
1 SOURCE
2 GATE
3 DRAIN

Performance Curves: VNDN24 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TC
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise noted)
SYMBOL

2N7007

Drain-Source Voltage

Vos

240

Gate-Source Voltage

VGS

±40

UNITS

V
0.065

Tc= 25°C
Continuous Drain Current

10

0.041

Tc = 100°C
Pulsed Drain Current 1

10M

Tc= 25°C

A

0.260
0.4

Power Dissipation

W

Po
0.16

Tc = 100°C
Tj

-55 to 150

T stg

-55 to 150

TL

300

SYMBOL

2N7007

UNITS

RthJA

312.5

°C/W

Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

°C

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient
1 Pulse width limited by maximum junction temperature

6-18

2N7007

.-rSiliconix

~ incorporatec

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N7007

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

V(BR)OSS

Vas=OV.10=100JJ,A

270

240

Vos = Vas. 10 = 0.25 mA

1.85

1

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3

Drain-Source
On-Reslstance 3

V
VaS(th)
lass

Vos = 0 V
Vas =±20 V

I

Vos = 120 V
loss

Vas = 0 V

10(ON)

Vos = 20 V

0.001

0.1

0.6

1

Vas = 4.5 V

100

50

Vas = 10 V

170

150

Vas = 4.5 V
10=20mA
rOS(ON)

I
I

Tc = 125°C

Tc=125°C

Vas = 4.5 V. 10 = 20 mA
VOS(ON)

Vas = 10 V
10 = 50 mA

I

4TC = 125°C

nA

±5

Vos = 120 V. Tc = 125°C

Vas = 10 V
10 = 50 mA

Drain-Source
On-Voltage 3

+10

±1
Tc = 125°C

2.5

mA

40

45

80

85

35

45

75

85

0.8

0.9

1.75

2.25

3.75

4.25

~~~;~~nductance 3

gfs

Vos=10V.10=50mA
f = 1 kHz

50

Common Source
Output Conductance3 ,4

gos

Vos=10V.10=50mA

10

JJ,A

30

.n

V

mS
JJ,S

OYNAMIC
Input Capacitance

C lss

15

30

4

15

1

10

7

30

18

20

Vos = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

Vas = 0 V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES:

1.
2.
3.
4.

VOO= 60 V. RL= 1.2 k.n
10 = 50 mAo VaEN = 10 V
Ra= 25.n
(Switching time Is essentially Independent of
operating temperature)

ns

T c = 25·C unless otherwise noted.
For design aid only. not subject to production testing.
Pulse test: PW = 80 JJ,s. duty cycle S 1%.
This parameter not registered with JEDEC.

6-19

iii

~SilicDnix

2N7008

~ incorporated

N-Channel Enhancement-Mode MOS Transistor

TO-92

PRODUCT SUMMARY
V(BR)OSS
(V)

rOS(ON)
(.0)

(A)

PACKAGE

60

7.5

0.15

TO-92

BOTTOM VIEW

10

1 SOURCE
2 GATE
3 DRAIN
Performance Curves: VNDS06 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TC

= 25°C unless otherwise

PARAMETERS/TEST CONDITIONS

SYMBOL

2N7008

Drain-Source Voltage

Vos

60

Gate-Source Voltage

VGS

±40

noted)
UNITS

V
0.15

Tc= 25°C
Continuous Drain Current

10

0.1

Tc = 100°C
Pulsed Drain Current 1

10M

Tc= 25°C
Power Dissipation

1
400
mW

Po
160

Tc = 100°C
Operating Junction Temperature
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

A

Tj

-55 to 150

T stg

-55 to 150

TL

300

SYMBOL

2N7008

UNITS

RthJA

312.5

°C/W

°C

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient
1Pulse width limited by maximum junction temperature

6-20

~Siliconix
.L;II incorporated

2N7008

ELECTRICAL CHARACTERISTICS 1

LIMITS
2N7008

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

V(BR)DSS

Vas = 0 V, ID = 10)J.A

70

60

2.15

1

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3

Drain-Source
On-Resistance 3

V
VaS(th)
lass

IDSS
ID(ON)

VDS = Vas, ID = 0,25 mA
VDS = 0 V
Vas = ±30 V
Vas = 0 V

I

±1
4To = 125°C

IVDS = 50 V
IVDS = 50 V, To = 125°C

V DS 2: 2 VDS(ON), Vas = 10 V
Vas = 5 V
I D =50mA

rDS(ON)
Vas = 10 V
ID = 0.5 A

I

I

To=125°C

To= 125°C

Vas = 5 V, ID = 50 mA
Drain-Source
On-Voltage 3

VDS(ON)

Vas = 10 V
I D =0.5A

I

4TO = 125°C

2.5
+100

nA

+ 5
0.02

1

1

500

1000

500

mA

5

7.5

9

13.5

2.5

7.5

4.4

13.5

0.25

0.375

1.25

3.75

2.2

6.75

~~~:6~nductance3

gfs

V Ds =10V,I D =0.2A
f = 1 kHz

170

Common Source
Output Conductance 3,4

gos

V DS = 5 V, I D = 50 mA

500

)J.A

80

.0.

V

mS
.uS

DYNAMIC
Input Capacitance

C lss

16

50

11

25

2

5

7

20

7

20

V DS = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

erss

Vas = 0 V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

t OFF

NOTES:

VDD = 30 V, RL= 150 .0.
ID = 0.2 A, VaEN = 10 V
Ra = 25.0.
(Switching time Is essentially Independent of
operating temperature I

ns

1. To = 25 ° C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 80 .us, duty cycle S 1% .
4. This parameter not registered with JEDEC.

6-21

.:rSiliconix

3N163 SERIES

..z;;JI incorporated

P·Channel Enhancement·Mode MOS Transistors

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSS rOS(ON)
(fi)
(V)

10
(mA)

PACKAGE

3N163

-40

250

-50

TO·72

3N164

-3~

300

-50

TO-72

TO·72

Performance Curves: MRA (See Section 7)

BOTTOM VIEW

1
2
3
4

DRAIN
GATE
SUBSTRATE, CASE
SOURCE

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

3N163

3N164

Drain-Source Voltage

Vos

-40

-3~

Gate-Source Voltage

VGS

±4o

±3o

±125

±125

Transient Gate-Source Voltage
Continuous Drain Current

ID

-50

-50

Power Dissipation

PD

375

375

3

3

UNITS

V

mA

mW
Power Derating
TJ

-55 to 150

Storage Temperature

T stg

-65 to 200

Lead Temperature
(1/16" from case for 10 seconds)

TL

300

Operating Junction

6-22

DC

3N163 SERIES

.... Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
3N163

3N164

SYMBOL

TEST CONDITIONS

TYp2

MIN

Drain-Source
Breakdown Voltage

V(BR)OSS

V GS = 0 V, 10 = -10J.LA

-70

-40

-30

Source-Drain
Breakdown Voltage

V(BR)SOS

-70

-40

-30

V GS =Vos , 10 = -10J.LA

-2.5

-2

-5

-2

-5

Vos = -15 V, 10 = -0.5 mA

-3.5

-3

-6.5

-2.5

-6.5

PARAMETER

MAX

MIN

MAX UNIT

STATIC

Gate Threshold
Voltage
Gate-Source
Voltage

VGo =VBO = 0 V, Is = -10J.LA

V
VGS(lh)
V GS

VOS = 0 V
V GS = -40 V

Gate-Body Leakage

IGSS
Vos = 0 V
V GS = -30 V

Zero Gate Voltage
Drain Current
Zero-Gate Voltage
Source Current

loss

Vos = -15 V
VGS = 0 V

Isos

Vso = -20 V
V GO =VOB = 0 V

On-State Drain
Current 3

101ON)

Drain-Source
On-Reslstance 3

rOSION)

I

TA = 125°C

-10

-1

-25

<-1

-10

I

T A = 125°C

-1

-25

I

TA = 125°C

-20

TA = 125°C

-10
-25

-8

r

Vos = -15 V, V GS = -10 V
V GS = -20 V
10 = -100J.LA

<-1

-10

TA = 125°C

-200

-400

-400

-800

pA
nA

-30

mA

nA

-5

180

I

pA

-30

-3

250

300
.0.

270

DYNAMlC

~~~~:6~nductance 3

gf.

Common Source
Output Conductance3

gas

Input Capacitance

C lss

Output Capacitance

Cess

Reverse Transfer
Capacitance

C rss

2.7
Vos = -15 V, 10 = -10 mA
f = 1 kHz

2

4

1

4

mS

J.LS

150

250

250

2.4

2.5

2.5

2.5

3

3

0.5

0.7

0.7

Voo = -15 V, RL= 1500.0.
10 = -10 mA , V GEN = 12 V

5

12

12

tr

RG=50.o.

13

24

24

tOFF

(Switching time Is essentially
Independent of operating
temperature)

25

50

50

Vos = -15 V, 10 = -10 mA
f = 1 MHz

pF

SWITCHlNG
tdlON)
Turn-On Time

Turn-Off Time

ns

NOTES: 1. T A = 25 ° C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 J.Ls , duty cycle S 2 % .

6-23

-

H

BS107

Siliconix

incorporated

N-Channel Enhancement-Mode MOS Transistor

PRODUCT SUMMARY
TO-92-18

BOTTOM VIEW

10

V(BR)OSS
(V)

rOS(ON)
(0,)

(A)

PACKAGE

200

28

0.12

TO-92

1 SOURCE
2 GATE
3 DRAIN
Performance Curves: VNDQ20 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TC
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise noted)
SYMBOL

BS107

UNITS

Drain-Source Voltage

VOS

200

Gate-Source Voltage

VGS

±25

Continuous Drain Current (T A = 25°C)'

10

0.12

A

Power Dissipation (fA = 25°C)

Po

0.5

W

Tj. T stg

-55 to 150

V

Operating Junction and Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

°C

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

6-24

SYMBOL

BS107

UNITS

RthJA

250

°C/W

8S107

~Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS1

LIMITS
BS107

TYp2

MIN

VGS = 0 V, 10 = 100.IJ.A

225

200

VGS(th)

Vos= V GS , 10 =1 mA

1.45

0.8

Gate-Body Leakage

IGSS

Vos = a V, V GS = ±15 V

±1

Drain Leakage Current

losx

Vos = 70 V, V GS = 0.2 V

Zero Gate Voltage
Drain Current

loss

Vos = 130 V, Vas = 0 V

rOS(ON)
gFS

PARAMETER

SYMBOL

TEST CONDITIONS

V(BR)OSS

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

Drain-Source
On-Reslstance 3

~~~;~~nductance 3

V
3
±10

nA

1

.lJ.A

0.001

30

nA

Vas = 2.8 V, 10 = 20 mA

6

28

.0.

Vos=10V,lo=0.1A

180

mS

DYNAMIC
Input Capacitance

CISS

Output Capacitance

Coss

Reverse Transfer
Capacitance

erss

35
Vos = 20 V, Vas = 0 V
f = 1 MHz

9

pF

1

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

V o o-25V, R L =125.n
10 = 0.2 A, V GEN = 10 V
RG= 25.0.
(Switching time Is essentially independent
of operating temperature)

5
ns
14

NOTES: 1. T c = 25·C unless otherwise noted.
2. For deSign aid only, not subject to production testing.
3. Pulse test; PW = 80.IJ.s, duty cycle;!; 1%.

6-25

g

BS170

Siliconix

im::crpcrated

N-Channel Enhancement-Mode MOS Transistor

PRODUCT SUMMARY
BOTTOM VIEW

TO-92-18
V(BR)OSS
(V)

rOS(ON)
(n)

(A)

PACKAGE

60

5

0.5

TO-92

10

1 DRAIN
2 GATE
3 SOURCE
Performance Curves: VNDS06 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (Tc

= 25°C unless otherwise noted)
SYMBOL

BS170

Drain-Source Voltage

Vos

60

Gate-Source Voltage

VGS

±25

PARAMETERS/TEST CONDITIONS

UNITS

V
0.5

TA= 25°C
Continuous Drain Current
TA = 1QQoC
Power Dissipation (T A = 25°C)
Operating Junction and Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

A

10

0.175
Po

0.83

TJ. T stg

-55 to 150

TL

300

SYMBOL

BS170

UNITS

RthJA

156

°C/W

W
°C

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

6-26

88170

~Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS1

LIMITS
BS170

TYp2

SYMBOL

TEST CONDITIONS

V(BR)OSS

V GS = 0 V, 10 = 100.uA

70

60

VGS(th)

Vos = VGs, 10 = 1 mA

2.3

0.8

Gate-Body Leakage

IGSS

Vos = 0 V, V GS = ±15 V

±1

±10

nA

Zero Gate Voltage
Drain Current

loss

Vos = 25 V, V GS = 0 V

0.02

0.5

.uA

V GS = 10 V, 10 = 0.2 A

2.5

5

.0.

gFS

Vos = 10 V, 10 = 0.2 A

230

C lss

Vos = 10 V, V GS = 0 V
f = 1 MHz

16

60

7

10

7

10

PARAMETER

MIN

MAX

UNIT

STATIC
Drain-Souroe
Breakdown Voltage
Gate Threshold
Voltage

Drain-Source
On-Reslstance 3

~~~:~gnductance 3

V

rOS(ON)

3

mS

100

DYNAMIC
Input Capacitance

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES:

VOO - 25 V, R L - 125 .0.
10=0.2A,VGEN =10V
RG= 25.0.
(Switching time Is essentially Independent
of operating temperature)

ns

1. T c = 25 °C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 80 .us, duty cycle S 1% .

6-27

~SilicDnix

BS208

~ incorporated

P-Channel Enhancement-Mode MOS Transistor

PRODUCT SUMMARY
BOTTOM VIEW

TO-92

V(BR)OSS
(V)

rOS(ON)
(!l)

(A)

PACKAGE

-200

14

-0.2

TO-92 RM

10

1 DRAIN
2 GATE
3 SOURCE

RM = Reverse Mold
Performance Curves: VPDV24 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
SYMBOL

BS208

Drain-Source Voltage

Vos

-200

Gate-Source Voltage

VGS

±20

Continuous Drain Current

10

-0.2

Pulsed Drain Current 1

10M

-0.8

Power Dissipation

Po

0.83

Tj. Tstg

-55 to 150

PARAMETERS/TEST CONDITIONS

UNITS

V

Operating Junction and Storage Temperature

A

W
DC

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE

SYMBOL

BS208

UNITS

RthJA

156

DC/W

Junction-to-Ambient
1Pulse width limited by maximum junction temperature

6-28

8S208

fCrSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
BS208

SYMBOL

TEST CONDITIONS

TYp2

V(BR)OSS

V GS = 0 V, 10 = -100p.A

-230

VGS(th)

VOS = VGS ' 10 = -1 mA

-1.9

IGSS

Vos = 0 V, V GS = ±15 V

± 1

±10

loss

Vos = -130 V, V GS = 0 V

-0.002

-1

losx

Vos = -70 V, V GS = -0.2 V

-8

-25

On-State Drain
Current S

101ON)

Vos = -10 V, VGS = -4.5 V

-300

Drain-Source
On-ResistanceS

rOS(ON)

V GS = -10 V, 10 = -100 mA

10

PARAMETER

MIN

-200

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage

Zero Gate Voltage
Drain Current

V

nA

P.A

mA
14

.0.

DYNAMIC
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance

70

C 1ss
Coss

C rss

VOS = -20 V
V GS = 0 V

25

pF

f = 1 MHz
11

SWITCHING
td(ON)
Turn-On Time
tr
t dIOFF)
Turn-Off Time

V OD = -25 V, R L = 125.0.
ID = -200 mA, V GEN = -10 V
RG = 25.0.
(Switching time Is essentially
independent of operating
temperature)

tf
NOTES:

6
8
ns
18
17

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300p.s, duty cycle S2%.

6-29

.HSiliconix

8S250

incorporated

P-Channel Enhancement-Mode MOS Transistor

PRODUCT SUMMARY
rOS(ON)
(n)

10
(A)

PACKAGE

-45

14

-0.18

TO-92RM

RM

= Reverse

BOTTOM VIEW

TO-92-1B

V(BR)OSS
(V)

~
~'
1 SOURCE
2 GATE
3 DRAIN

Mold

Performance Curves: VPDS06 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
SYMBOL

BS250

Drain-Source Voltage

Vos

-45

Gate-Source Voltage

VGS

±25

Continuous Drain Current (T A = 25 DC)

10

-0.18

A

Power Dissipation

Po

0.83

W

Tj. T stg

-55 to 150

TL

300

SYMBOL

BS250

UNITS

RthJA

150

°C/W

PARAMETERS/TEST CONDITIONS

UNITS

V

Operating Junction and Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

DC

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

6-30

g

8S250

Siliconix

incorporated

ELECTRICAL CHARACTERISTICS1

LIMITS
BS250

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage

V(BR)OSS

V Gs =OV,1 0 =-100jJ.A

-70

-45

VGS(th)

Vos = V GS , 10 = -1 mA

-2

-1

Gate-Body Leakage

IGSS

Vos = 0 V, V GS =±15 V

± 1

±20

Zero Gate Voltage
Drain Current

loss

Vos = -25 V, V GS = 0 V

-0.20

-500

rOS(ON)

V GS = -10 V, 10 = -0.2 A

6

14

gFS

VOS = -10 V, 10 = -0.2 A

125

mS

C lss

VOS = -10 V, V GS - 0 V
f = 1 MHz

15

pF

Gate Threshold
Voltage

Drain-Source
On-Reslstance 3

~~~~;6~nductance 3

V
-3.5

nA

.n.

DYNAMIC
Input Capacitance

SWITCHING
Turn-On Time

tON

8

10

8

10

lo=-0.2A
Turn-Off Time

tOFF

ns

SOURCE-DRAIN DIODE RATINGS & CHARACTERISTICS 1

LIMITS·
BS250

PARAMETER

SYMBOL

Continuous Current

Is

Forward Voltage 3

Vso

TEST CONDITIONS

IF=ls= -0.18V,V Gs =OV

TYp2

0.85

MIN

MAX

UNIT

-0.18

A
V

NOTES: 1. T A = 25·C unless otherwise noted.
2. For design aid only, not sublect to production testing.
3. Pulse test; PW =300jJ.s, duty cycle S2%.

6-31

tcrSiliconix

BSS89

~ incorporated

N-Channel Enhancement-Mode MOS Transistor

PRODUCT SUMMARY

TO-92-18

V(BR)OSS
(V)

rOS(ON)
(.n )

10
(A)

PACKAGE

200

6

0.3

TO-92 CD

BOTTOM VIEW

1 GATE
2 DRAIN
3 SOURCE

CD = Center Drain

Performance Curves: VNDB24 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TA

= 25°C unless otherwise noted)

PARAMETERS/TEST CONDITIONS

SYMBOL

BSS89

Drain-Source Voltage

Vos

200

Gate-Source Voltage

VGS

±20

10

0.3

10M

1.2

UNITS

V

Continuous Drain Current

I

T A= 25°C

Pulsed Drain Current 1
Power Dissipation

I

TA= 25°C

Operating Junction and Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

A

W

Po

1

Tj. T stg

-55 to 150

TL

300

SYMBOL

BSS89

UNITS

RthJA

125

°C/W

°C

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient
1 Pulse width limited by maximum junction temperature

6-32

BSS89

.-r-Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
BSSB9

TYp2

MIN

10 = 250 j.LA

270

200

VGS(lh)

Vos = VGS, 10 = 1 rnA

1.4

0.8

Gate-Body Leakage

IGSS

Vos = 0 V, VGS = 20 V

1

Zero Gate Voltage
Drain Current

loss

PARAMETER

SYMBOL

TEST CONDITIONS

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage

V(BR)OSS

VGS =

a v,

V
Gate Threshold Voltage

Drain-Source
On-Resistance
Forward
Transconductance

2.8
100

nA

0.01

60

1

200

VOS = 60 V, VGS = 0 V

5

200

nA

rOS(ON)

VGS = 10 V, 10 = 0.4 A

5

6

n.

gFs

Vos = 25 V, 10 = 0.4 A

0.4

Vos = 200 V
VGS = 0 V

I TJ = 125°C

0.14

j.LA

S

DYNAMIC
Input Capacitance

105

C lss
VOS = 25 V

Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

VGS = 0 V
f = 1 MHz

25

pF

5

SWITCHING
td(ON)

3

20

t,

Voo = 30 V, RL= lOOn.
10 = 0.28 A, V GEN = 10 V
RG=25n.

2

60

t d(OFF)

(Switching time Is essentially Independent of
operating temperature)

15

90

34

55

Turn-On Time

Turn-Off Time
tf

ns

SOURCE-DRAIN DIODE RATINGS & CHARACTERISTICS 1

LIMITS
BSS89

PARAMETER
Forward Voltage 3

NOTES:

SYMBOL

TEST CONDITIONS

TYp2

Vso

IF =Is= -0.6 A, VGS = 0 V

0.9

MIN

MAX

UNIT

1.4

V

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300j.Ls, duty cycle S2%.

6-33

BSS92

tcrSiliconix

~ incorporated

P·Channel Enhancement·Mode MOS Transistor

PRODUCT SUMMARY

BOTTOM VIEW

TO·92·18

~

10

V(BR)OSS
(V)

rOS(ON)
(Il)

(A)

PACKAGE

-200

20

-0.15

TO-S2 CORM

~

CD = Center Drain, RM = Reverse Mold. TO-1S Lead Form

1 SOURCE
2 DRAIN
3 GATE

Performance Curves: VPDQ20 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
SYMBOL

BSS92

Drain-Source Voltage

Vos

-200

Gate-Source Voltage

VGS

±20

10

-0.15

PARAMETERS/TEST CONDITIONS

,
UNITS

V

TA= 25°C
Continuous Drain Current

-O.OS

T A = 100°C
Pulsed Drain Current 1

IDM

TA= 25°C

A

-0.60
1.0

Power Dissipation

Po
T A = 100°C

Operating Junction and Storage Temperature

DAD

W

TJ. Tstg

-55 to 150

TL

300

SYMBOL

BSS92

UNITS

RthJA

125

°CfW

°C

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient
1Pulse width limited by maximum junction temperature

6·34

.HSiliconix
incorporated

BSS92

ELECTRICAL CHARACTERISTICS 1

LIMITS
BSS92

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

V(BR)OSS

VGS = 0 V. 10 = -250.lJ.A

-220

-200

VGS(th)

Vos = VGs. 10 = -1 mA

-1.9

-0.6

IGSS

Vos = 0 V. VGS = -20 V

±1

±100

-0.01

-0.2

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage

V

Vos = -60 V. VGS = 0 V
Zero Gate Voltage
Drain Current
Drain-Source
On-Reslstance 3

~~~;~~nductance3

loss

rOS(ON)
gFS

VOS = -200 V
VGS = 0 V

I

TJ = 125°C

VGS = -10 V. 10 = -100 mA
VOS = -25 V. 10 = -100 mA

-2.6

-0.02

-60

-3

-200

11.4

20

150

60

nA

.lJ.A

.0.
mS

DYNAMIC
Input Capacitance

30

Clss
Vos = -25 V

Output Capacitance

Coss

Reverse Transfer
Capacitance

erss

VGS = 0 V
f = 1 MHz

10

pF

2

SWITCHING
td(ON)
Turn-On Time
t,
t d(OFF)
Turn-Off Time

Voo = -30 V. R L = 120.0.
10 = -0.25 A. V GEN = -10 V
RG = 25.0.
(Switching time Is essentially
Independent of operating
temperature)

tf

6
6
ns
16
17

SOURCE-DRAIN DIODE RATINGS & CHARACTERISTICS 1

LIMITS
BSS92

PARAMETER
Forward Voltage 3

SYMBOL

TEST CONDITIONS

TYp2

Vso

IF =Is= -0.3 A. VGS = 0 V

-0.9

MIN

MAX

UNIT

-1.2

V

NOTES: 1. T A = 25 0 C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW =300.lJ.s. duty cycle S2%.

6-35

.HSiliconix
incorporated

888129
N-Channel Depletion-Mode MOS Transistor

PRODUCT SUMMARY

TO-92-18

V(BR)OSV
(V)

rOS(ON)
(.n )

10
(A)

PACKAGE

230

20

0.15.

TO-92 CORM

BOTTOM VIEW

1 GATE
2 DRAIN
3 SOURCE

CD = Center Drain. RM = Reverse Mold

Performance Curves: VDDV24 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TA
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise noted)
SYMBOL

BSS129

Drain-Source Voltage

Vos

230

Gate-Source Voltage

VGS

±20

10

0.15

Pulsed Drain Current 1

10M

0.60

Power Dissipation

Po

1

TJ. T stg

-55 to 150

TL

300

SYMBOL

BSS129

UNITS

RthJA

125

DC/W

UNITS

V
Continuous Drain Current

I

TA= 35DC

A

Operating Junction and Storage Temperature

W
DC

Lead Temperature
(1/16" from case for fa seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient
1Pulse width limited by maximum junction temperature

6-36

BSS129

tcrSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
855129

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage

V(BR)DSV

VGS = -3 V, ID = 250 mA

260

230

Gate-Source
Cutoff Voltage

VGS(OFF)

V Ds =3V,I D =1mA

-2.3

-0.7

Gate-Body Leakage

IGSS

V DS = 0 V, VGS = 20 V

±1

Drain Cutoff Current

ID(OFF)

Drain-Source
On-Resistance
Forward
Transconductance

V

V DS = 230 V
VGS = -3 V

I TJ

= 125°C

± 100

0.04

0.1

7.5

200
20

rDS(ON)

VGS = 0 V, ID = 14 mA

4

gFS

VDS = 25 V, I D = 250 mA

175

140

nA
Jl.A

.0.
mS

DYNAMIC
Input Capacitance

70

C tSS
V DS = 25 V

Output Capacitance
Reverse Transfer
Capacitance

Coss

VGS = -5 V

20

pF

f = 1 MHz
C rss

10

SWITCHING
td(ON)
Turn-On Time

15

tr

VDD = 25 V, R L = 830.0.
I D =30mA, VGEN=-5V
RG = 25.0.

75

td(OFF)

(Switching time Is essentially independent of
operating temperature)

40

Turn-Off Time
t,

NOTES:

ns

100

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 Jl.S , duty cycle S 2 % .

6-37

~Siliconix

MFE823

~ incorporated

P-Channel Enhancement-Mode MOS Transistor

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSS
(V)

9fs

10

(mS)

(rnA)

PACKAGE

-25

1

-30

TQ-18

TO-18
MFE823

Performance Curves: MRA (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TA

BOTTOM VIEW

1 DRAIN
2 GATE
3 SOURCE, SUBSTRATE
CASE

= 25°C unless otherwise noted)
SYMBOL

MFE823

Drain-Source Voltage

Vos

-25

Gate-Source Voltage

VGS

±10

PARAMETERS/TEST CONDITIONS

UNITS

V
Continuous Drain Current

TA= 25°C

10

-30

mA

Power Dissipation

TA= 25°C

Po

375

mW

3

mW/oC

Power Derating
Operating Junction

TJ

-55 to 150

Storage Temperature

T stg

-65 to 200

Lead Temperature
(1/16" from case for 10 seconds)

TL

300

6-38

°C

MFE823

.rSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
MFE823

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

V(BR)DSS

V GS = 0 V, ID = -10,IJ.A

-70

-25

VGS(th)

VDS = -10 V, ID = -10,IJ.A

-2.5

-2

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

V

Gate-Body Leakage

IGSS

Zero Gate Voltage
Drain Current

IDSS

On-State Drain
Current 3

ID(ON)

Drain-Source
On-Reslstance 3

rDS(ON)

VDS = 0 V
V GS = -10 V
V DS = -10 V
VGS = 0 V
VDS

-1

<-1

I

TA

= 125°C

I

TA

= 125°C

-1
-0.01

= -10 V,

-6

-20

-20

V GS = -10 V

-10

V GS = -20 V, ID = -100,IJ.A

180

-3

pA

nA
mA

.0.

DYNAMIC

~~~~:~gnductance 3

gls

Common Source
Output Conductance 3

gos

Input Capacltanoe

Clss

Reverse Transfer
Capacitance

C rss

V DS = -10 V, ID = -2 mA
f = 1 kHz

V DS = -10 V, V GS = -10 V
f = 1 MHz

1.5

1

mS

35

,IJ.S

2.4

6

0.5

1.5

pF

NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300,IJ.s, duty cycle S2%.

6-39

tcrSiliconix

ND2012 SERIES

~ incorporatE!d

N-Channel Depletion-Mode MOS Transistors
BOTTOM VIEW

TO-92

~r::::::4

~1 SOURCE ~

PRODUCT SUMMARY

. 2 GATE
3 DRAIN

PART
V(BR)OSV rOS(ON)
NUMBER
(V)
(n.)

10
(A)

PACKAGE
TO-206AC (TO-52)

ND2012L

200

12

0.16

TO-92

ND2012E

200

12

0.22

TO-206AC

Performance Curves: VDDQ20 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

BOTTOM VIEW

1 SOURCE
2 GATE
3 DRAIN & CASE

= 25°C unless otherwise

noted)

ND2012E 2

SYMBOL

ND2012L

Drain-Source Voltage

Vos

200

200

Gate-Source Voltage

VGS

±30

±20

0.16

0.22

0.10

0.14

0.8

0.8

0.80

1.5

0.32

0.60

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA = 100°C
Pulsed Drain Current 1

10M

T A= 25°C
Power Dissipation

Po
TA= 100°C

Operating Junction and Storage Temperature

Tj. T stg

-55 to 150

TL

300

A

W

°C

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

ND2012L

ND2012E

UNITS

RthJA

156

400

°C/W

1Pulse width limited by maximum junction temperature
2Reference case for all temperature testing
6-40

ND2012 SERIES

.r-Siliconix
.LII incorporated
ELECTRICAL CHARACTERISTICS 1

LIMITS
ND2012

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage

V(BR)OSV

VGS = -8 V, 10 = 10jJ.A

Gate-Source
Cutoff Voltage

VGS(OFF)

V os =5V,1 0 =10jJ.A

Gate-Body Leakage

Drain Cutoff Current

220

200

-3

-1.5

V

IGSS

10(OFF)

Drain Saturation
Current 3

loss

Drain-Source
On-Resistance 3

rOS(ON)

Forward
Transconductance

gFs

Common Source Output
Conductance 3

gos

Vos = 0 V
VGS = ±20 V

I TJ = 125°C

Vos=160V
VGS = -8 V

I TJ = 125°C

±0.1

+10

±5

+50

0.2

1

5

200

Vos = 10 V, VGS = 0 V

400

VGS = 2 V, 10 = 20 mA

7

VGS = 0 V
10 = 20 mA

I TJ = 125°C

-4

30

nA

jJ.A
mA

8

12

15

30

.0.

55

mS

75

jJ.S

V os =7.5V,I D =20mA

DYNAMIC
Input Capacitance

CISS

35

100

10

20

2

5

Vos = 25 V

Output Capacitance

Coss

Reverse Transfer
Capacitance

erss

VGS = -5 V
f = 1 MHz

pF

SWITCHING
td(ON)
Turn-On Time
tr
td(OFF)
Turn-Off Time
tf

NOTES:

V DO = 25 V, R L = 1250.0.
10 = 20 mA, V GEN = -5 V
RG = 25.0.
(Switching time is essentially
Independent of operating
temperature)

20
20
ns
10
10

1. T A = 25°C unless otherwise noted, T c = 25°C for ND2012E.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300jJ.s. duty cycle ;5;2%.

6-41

a'Y"Siliconix

ND2020 SERIES

~ incorporated

N-Channel Depletion-Mode MOS Transistors
BOTTOM VIEW

TO-92

~§
1 SOURCE
2 GATE
3 DRAIN

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSV rOS(ON)
(il)
(V)

10

(A)

PACKAGE
BOTTOM VIEW

TO-206AC (TO-52)
ND2020L

200

20

0.132

TO-92

ND2020E

200

20

0.18

TO-206AC

Performance Curves: VDDQ20 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TA

1 SOURCE
2 GATE
3 DRAIN & CASE

= 25°C unless otherwise noted)
ND2020E 2

SYMBOL

ND2020L

Drain-Source Voltage

Vos

200

200

Gate-Source Voltage

VGS

±30

±20

0.132

0.18

0.083

0.11

0.8

0.8

0.80

1.5

0.32

0.60

PARAMETERS/TEST CONDITIONS

UNITS

V

T A= 25°C
Continuous Drain Current

10

T A = 100°C
Pulsed Drain Current 1

10M

TA= 25°C
Power Dissipation

Po
TA = 100°C

Operating Junction and Storage Temperature

A

W
-55 to 150

TJ. Tstg

DC

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

ND2020L

ND2020E

UNITS

RthJA

156

400

DC/W

1Pulse width limited by maximum junction temperature
2Reference case for all temperature testing
6-42

ND2020 SERIES

ttCrSiliconix

~ incorporater::l

ELECTRICAL CHARACTERISTICS 1

LIMITS
ND2020L

SYMBOL

TEST CONDITIONS

TYp2

MIN

Drain-Source
Breakdown Voltage

V{BR)OSV

VGS = -5 V, 10 = l.11A

220

200

Gate-Source
Cutoff Voltage

VGS{OFF)

Vos = 5 V, 10 = 10.l1A

-1.8

-0.5

PARAMETER

MAX

ND2020E
MIN

MAX UNIT

STATIC

Gate-Body Leakage

Drain Cutoff Current
Drain Saturation
Current 3
Drain-Source
On-Reslstance 3

200
V

IGSS

10{OFF)
loss

rOS{ON)

~~~:~~nductance 3

gFS

Common Source Output
Conductance 3

gos

Vos = 0 V
VGS = ±20 V
VOS = 160 V
VGS = -5 V

I TJ = 125 DC
I TJ

= 125 DC

+10

+10

±50

±50

0.2

1

1

5

200

200

110
10

I

-2.5

±5

V GS = 2 V, 10 = 20 mA

TJ = 125 DC

-0.5

±0.1

Vos = 10 V, VGS = 0 V

VGS = 0 V
10 = 20 mA

-2.5

30

30

nA

,I.lA
mA

11

20

20

20

50

30

.0,

55

mS

75

,I.lS

Vos=7.5V,10=20mA

DYNAMIC
Input Capacitance

C lss

35

100

100

10

20

20

2

5

5

Vos = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

VGS = -5 V
f = 1 MHz

pF

SWITCHING
td{ON)
Turn-On Time
tr
t d{OFF)
Turn-Off Time

Voo = 25 V. RL = 1250.0,
10 = 20 mA, VGEN = -5 V
RG = 25.0,
(Switching time Is essentially
Independent of operating
temperature)

tf

20
20
ns
10
10

NOTES: 1. T A = 25 DC unless otherwise noted, Tc = 25 DC for ND2020E.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300.l1s, duty cycle S 2%.

6-43

~Siliconix

ND2406 SERIES

~ incorporated

N-Channel Depletion-Mode MOS Transistors

TO-92

BOTTOM VIEW

~~

~1

PART
NUMBER

~

SOURCE
2 GATE
3 DRAIN

PRODUCT SUMMARY
10

V(BR)OSV rOS(ON)
(0)
(V)

(A)

PACKAGE

ND2406L

240

6

0.23

TO-92

ND2406B

240

6

0.57

TO-205AF

BOTTOM VIEW

TO-205AF

1 SOURCE
2 GATE
3 DRAIN & CASE

Performance Curves: VDDV24 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless.otherwise noted)
PARAMETERS/TEST CONDITIONS

ND2406B 2

SYMBOL

ND2406L

Drain-Source Voltage

Vos

240

240

Gate-Source Voltage

VGS

±30

±20

0.23

0.57

0.14

0.36

0.90

1

0.80

5

0.32

2

UNITS

V
TA= 25DC
Continuous Drain Current

10

TA = 100DC
Pulsed Drain Current 1

10M

T A= 25DC
Power Dissipation

Po

T A = 100DC

Operating Junction and Storage Temperature

A

W

-55 to 150

TJ. T5t9

DC

Lead Temperature
(1/1 6" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE

Junction-to-Ambient

SYMBOL

ND2406L

ND2406B

UNITS

RthJA

156

125

DC/W

1Pulse width limited by maximum junction temperature
2Reference case for all temperature testing
6-44

ND240S SlER~ES

.rSiliconix

.LJII

incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
ND2406L

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

MAX

ND2406B
MIN

MAX UNIT

STATIC
Drain-Source
Breakdown Voltage

V(BR)OSV

V GS = -9 V, ID = 10Jl.A

260

240

Gate-Source
Cutoff Voltage

VGS(OFF)

V os =5V,I D =10Jl.A

-2.8

-1.5

Gate-Body Leakage

Drain Cutoff Current
Drain Saturation
Current 3
Drain-Source
On-Resistance 3

240
V

IGSS

10(OFF)
loss

rOS(ON)

~~~~;~~nductance 3

gFS

Common Source Output
Conductance 3

gos

+1

Vos = 0 V
V GS =±20 V

I TJ = 125°C

Vos = 180 V
V GS = -9 V

I TJ = 125°C

±5

-4.5

±10

±10

+50

+50

1

1

15

200

200

640

V GS = 2 V, I D = 30 mA

3

I TJ = 125°C

-1.5

0.04

V DS = 10 V, V GS = 0 V

V GS = 0 V
10 = 30 mA

-4.5

40

40

nA

Jl.A
mA

3.5

6

6

7

15

15

.0.

110

mS

70

J.lS

V os =10V,1 0 =30mA

DYNAMIC
Input Capacitance

C lss

70

120

120

20

30

30

10

15

15

V DS = 25 V
Output Capacitance

Coss

V GS = -5 V

pF

f = 1 MHz
Reverse Transfer
Capacitance

C rss

SWITCHING
td(ON)
Turn-On Time
tr
t d(OFF)
Turn-Off Time

V DO = 25 V, R L = 830.0.
10 = 30 mA, V GEN = -5 V
RG = 25.0.
(Switching time Is essentially
Independent of operating
temperature)

tf

15
75
ns
40
100

NOTES: 1. T A = 25°C unless otherwise noted, T c = 25°C for ND2406B.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300J.ls, duty cycle ;5;2%.

6-45

ND2410 SERIES

.rY"Siliconix

~ incorporated

N-Channel Depletion-Mode MOS Transistors
BOTTOM VIEW

TO-92

~(§)
1 SOURCE
2 GATE
3 DRAIN

PRODUCT SUMMARY
PART
V(BR)OSV reStON)
NUMBER
(V)
(0)

10

(A)

PACKAGE

ND2410L

240

10

0.18

TO-92

ND2410B

240

10

0.46

TO-205AF

TO-205AF

1 SOURCE
2 GATE
3 DRAIN & CASE

Performance Curves: VDDV24 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TA

BOTTOM VIEW

25°C unless otherwise noted)

=

ND2410B 2

SYMBOL

ND2410L

Drain-Source Voltage

Vos

240

240

Gate-Source Voltage

VGS

±30

±20

0.18

0.46

0.12

0.29

0.90

1

0.80

5

0.32

2

PARAMETERS/TEST CONDITIONS

UNITS

V
TA= 25DC
Continuous Drain Current

10

T A = 100DC
Pulsed Drain Current 1

10M

TA= 25DC
Power Dissipation

PD

TA = 100DC

Operating Junction and Storage Temperature

TJ. Tstg

-55 to 150

TL

300

A

W

DC

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

ND2410L

ND2410B

UNITS

RthJA

156

125

DC/W

1Pulse width limited by maximum junction temperature
2Reference case for all temperature testing

6-46

ND2410 SERIES

~Siliconix
inccrpcrated

..LII

ELECTRICAL CHARACTERISTICS 1

LIMITS
ND2410L

SYMBOL

TEST CONDITIONS

TYp2

MIN

Drain-Source
Breakdown Voltage

V(BR)OSV

VGS = -5 V, 10 = 1 jJ.A

260

240

Gate-Source
Cutoff Voltage

VGS(OFF)

V os =5V,1 0 =10jJ.A

-1.7

-0.5

PARAMETER

MAX

ND2410B
MIN

MAX UNIT

STATIC

Gate-Body Leakage

Drain Cutoff Current
Drain Saturation
Current3

V

IGSS

10(OFF)
IDSS

V DS = 0 V
VGS =±20 V
V DS = 180 V
VGS = -5 V

J TJ = 125°C
I TJ = 125°C

Vos = 10 V, VGS = 0 V

I

VGS = 2 V, I D = 30 mA
Drain-Source
On-Reslstance 3

240

rOS(ON)

~~~~:b~nductance 3

gFS

Common Source Output
Conductance 3

90S

VGS = 0 V
10 = 30 mA

I TJ = 125°C

-2.5

-0.5

-2.5

±0.1

±10

±10

+5

+50

±50

0.04

1

1

7.5

200

200

120

40

40

nA

.uA
mA

4.5
5

10

20

10

25

25

.0.

110

mS

70

.uS

V os =10V,1 0 =30mA

DYNAMIC
Input Capacitance

C lss

Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

70

120

120

20

30

30

10

15

15

V DS = 25 V
VGS = -5 V
f = 1 MHz

pF

SWITCHING
td(ON)
Turn-On Time
tr
td(OFF)
Turn-Off Time

V DO = 25 V, R L = 830.0.
I D =30mA, V GEN =-5V
RG= 25.0.
(Switching time Is essentially
Independent of operating
temperature)

tf

15
75
ns
40
100

NOTES: 1. T A = 25°C unless otherwise noted, To = 25 °C for ND2410B.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300jJ.s, duty cycle ~2%.

6-47

.-r-Siliconix

TP0610 SERIES

~ incorporated

P-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
PART
NUMBER

TO-92
10
(A)

PACKAGE

-0.25

TO-206AC

V(BR)OSS rOS(ON)
(.n )
(V)

~~

~1 SOURCE ~

,

TP061DE

-60

10

BOTTOM VIEW

2 GATE
3 DRAIN
TP0610L

-60

10

-0.18

TO-92

TP0610T

-60

10

-0.12

80T-23

TO-206AC (TO-52)

BOTTOM VIEW

Performance Curves: VPOS06 (See Section 7)
TOP VIEW

SOT-23

SOURCE
1 SOURCE
2 GATE
3 DRAIN & CASE

DRAIN
GATE

ABSOLUTE MAXIMUM RATINGS (T A

= 25°C unless otherwise

noted)

SYMBOL

TP0610E 2

TP0610L

TP0610T

Drain-Source Voltage

Vos

-60

-60

-60

Gate-Source Voltage

VGS

±20

±30

±30

-0.25

-0.18

-0.12

-0.15

-0.11

-0.07

-1

-0.8

-0.4

1.5

0.80

0.36

0.60

0.32

0.14

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA = 100°C
Pulsed Drain Current 1

10M

T A= 25°C
Power Dissipation

Po
TA= 100°C

Operating Junction and Storage Temperature

A

W

Tj. Tstg

-55 to 150
°C

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

TP0610E

TP0610L

TP0610T

UNITS

RthJA

400

156

350

°C/W

~Pulse width limited by maximum junction temperature
Reference T c for all temperature testing
6-48

TP0610 SERIES

~Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
TP0610E

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)OSS

VGS = 0 V, 10 = -10.llA

-70

-60

VGS(th)

Vos = VGS, 10 = -1 mA

-1.7

-1

MAX

TP0610L
MIN

MAX UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

-60
V

IGSS

loss
10(ON)

rOS(ON)

Vos = 0 V
Vas = ±20 V
VDS = -48 V
VGS = 0 V

I

TJ = 125°C

I

TJ = 12S·C

Vos = -10 V, VGS = -4.5 V

-2.4

-1

-2.4

± 1

±10

±10

±S

±SO

+50

-0.02

-1

-1

-0.2

-200

-200

-80

-50

-50

11

VGS = -10 V
lo=-O.SA

8

10

10

15

20

20

I

TJ = 12S·C

~~~~:6~nductance 3

gFS

VOS = -10 V, 10 = -0.5 A

135

Common Source
Output Conductance 3

gas

VOS = -10 V, 10 = -0.1 A

400

80

.llA
mA

VGS = -4.5 V, 10 = -25 mA

25

nA

25

80

n
mS
,llS

DYNAMIC
Input Capacitance

Ciss

Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

15

60

60

10

25

25

3

5

5

6

10

10

10

15

15

7

15

15

8

20

20

Vos = -25 V
VGS = 0 V
f = 1 MHz

pF

SWITCHING
td(ON)
Turn-On Time
t,

n

Voo = -25 V, R L = 133
10 = -0.18 A, V GEN = -10 V
RG = 25

t d(OFF)
Turn-Off Time
tf

n

(Switching time Is essentially
Independent of operating
temperature)

ns

NOTES: 1. T A = 25·C unless otherwise noted, T c = 25·C for TP0610E.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300.lls , duty cycle !f 2 %.

6-49

.:rSiliconix

TP0610 SERIES

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
TP0610T

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

V(BR)OSS

VGS = 0 V, 10 = -10,ll.A

-70

-60

VGS(th)

Vos = VGS' 10 = -1 mA

-1.7

-1

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V

IGSS

loss
ID(ON)

rOS(ON)

~~~~:~~nductance 3

gFS

Common Source
Output Conductance3

gos

Vos = 0 V
V Gs =±20V
V DS = -48 V
VGS = 0 V

I

TJ = 125°C

I

TJ = 125°C

Vos = -10 V, VGS = -4.5 V

-2.4

+1

±10

±5

±50

-0.02

-1

-0.2

-200

-80

-50

11

VGS = -10 V
10 = -0.2 A

6

10

12

20

TJ = 125°C

90

,Il.A
mA

VGS = -4.5 V, 10 = -25 mA

I

nA

25

60

.n

mS

Vos = -10 V, 10 = -0.1 A
400

.uS

DYNAMIC
Input Capacitance

Cis.

Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

15

60

10

25

3

5

6

10

10

15

7

15

6

20

VOS = -25 V
VGS = 0 V
f = 1 MHz

pF

SWITCHING
td(ON)
Turn-On Delay Time
t,

Voo = -25 V, R L = 133.n
10 = -0.16 A, V GEN = -10 V
RG = 25.n

t d(OFF)
Turn-Off Delay Time
tf
NOTES:

6-50

(Switching time Is essentially
independent of operating
temperature)

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300,ll.s, duty cycle ;!;2%.

ns

VN40AFD

~Siliconix

.L;II incorporated

N-Channel Enhancement-Mode MOS Transistor

TO-220SD

TOP VIEW

o

PRODUCT SUMMARY
10

V(BR)OSS
(V)

rOS(ON)
(!l)

(A)

PACKAGE

40

5

1.14

TO-22080

1 SOURCE
2 GATE
3 & TAB - DRAIN

80 = Side Drain

1 2 3

Performance Curves: VNDQ06 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (T c
PARAMETERS/TEST CONDITIONS

= 25°C unless

otherwise noted)

SYMBOL

VN40AFD

Drain-Source Voltage

Vos

40

Gate-Source Voltage

VGS

±30

UNITS

V

1.14

Tc= 25°C
Continuous Drain Current

ID
0.72

Tc = 100°C
Pulsed Drain Current 1

10M

Tc= 25°C

A

3
15

Power Dissipation

Po

W
6

Tc = 100°C
Operating Junction and Storage Temperature

Tj. Tstg

-55 to 150
°C

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE

SYMBOL

VN40AFD

UNITS

RthJC

8.3

°C/W

Junction-to-Case
1Pulse width limited by maximum junction temperature.

6-51

VN40AFD

~Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS1

LIMITS
VN40AFD

TYp2

SYMBOL

TEST CONDITIONS

V(BR)OSS

Vas=OV,1 0 =10)lA

70

40

VaS(th)

Vos= Vas, 10 =1 mA

1.5

0.8

Gate-Body Leakage

lass

Vos=OV,Vas=±15V

±1

Zero Gate Voltage
Drain Current

loss

PARAMETER

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V

10(ON)

rOS(ON)

2.5
±100

Vos = 40 V, Vas = 0 V

0.05

10

Vos = 32 V, Vas = 0 V, To = 125°C

0.3

500

Vos = 15 V, Vas = 10 V

1.8

Vas=5V,10=0.3A

1.8

Vas = 10 V

1.3

5

2.6

10

10 = 1 A

I To= 125°C

~~~:~gnductance 3

gFS

Vos = 10 V, 10 = 0.5 A

350

Common Source
Output Conductance3

gos

Vos=10V,10=0.1 A

1100

1

nA
)lA
A

5
.0.

mS

170

)lS

DYNAMIC
Input Capacitance

C lss

35

50

25

65

5

10

8

15

9.5

15

Vos = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

Vas = 0 V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

VOO - 25 V, R L - 23.0.
10=lA,VaEN =10V
Ra= 25.0.
(Switching time Is essentially Independent
of operating temperature)

NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300)ls, duty cycle :52%.

6-52

ns

VN46AFD

.:r'Siliconix

~ incorporated

N-Channel Enhancement-Mode MOS Transistor

TOP VIEW

TO-220SD

o

PRODUCT SUMMARY
V(BR)eSS
(V)

res (ON)
(il)

Ie
(A)

PACKAGE

40

3

1.46

TO-220SD

1 SOURCE
2 GATE
3 & TAB - DRAIN

Performance Curves: VNOQ06 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TC

1 23

= 25°C unless otherwise noted)
SYMBOL

VN46AFD

Drain-Source Voltage

Ves

40

Gate-Source Voltage

VGS

±30

PARAMETERS/TEST CONDITIONS

UNITS

V
1.46

Tc= 25°C
Continuous Drain Current

Ie
0.92

Tc = 100°C
Pulsed Drain Current 1

leM
Tc= 25°C

Power Dissipation

3
15

Po
6

Tc = 100°C
Operating Junction and Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

A

TJ. T stg

W

-55 to 150
°C

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Case

SYMBOL

VN46AFD

UNITS

RthJC

8.3

°C/W

1Pulse width limited by maximum junction temperature

6-53

.:rSilicanix

VN46AFD

~ incorporated

ELECTRICAL CHARACTERISTICS1

LIMITS
VN46AFD

TYp2

MIN

SYMBOL

TEST CONDITIONS

V(BR)DSS

V Gs=OV.I D =10jJ.A

70

40

VGS(th)

V DS = V Gs • I D = 1 mA

1.5

0.8

Gate-Body Leakage

IGSS

VDS = 0 V. VGS = ±15 V

± 1

Zero Gate Voltage
Drain Current

IDSS

VDS = 40 V. VGS = 0 V

0.05

10

VDS = 32 V. V GS = 0 V. Tc = 125°C

0.3

500

PARAMETER

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V

ID(ON)

rDS(ON)

2.5
±100

V DS = 10 V. V GS = 10 V

1.8

V GS = 5 V. I D = 0.3 A

1.8

V GS = 10 V
ID = 1 A

1.3

3

2.6

6

I Tc = 125°C

~~~~:6~nductance 3

gFS

V DS =10V.I D =0.5A

350

Common Source
Output Conductance 3

gos

V Ds =10V.I D =0.lA

1100

1

nA
JJ.A
A

5
.0.

mS

170

JJ.S

DYNAMIC
Input Capacitance

C lss

Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

V DS = 25 V
V GS = 0 V
f = 1 MHz

35

50

25

65

5

10

8

15

9.5

15

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

V DD = 25 V. R L = 23.0.
ID = 1 A. V GEN = 10 V
RG= 25.0.
(Swltchln~ time Is essentially Independent
of operat ng temperature)

NOTES: 1. T c = 25°C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW = 300 jJ.s • duty cycle ~ 2 % .

6-54

ns

VN66 SERIES

fCTSiliconix

.LJ!I

incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSS rOS(ON)
(il)
(V)

TOP VIEW

TO-220/TO-220SD

10
(A)

PACKAGE

VN66AD

60

3

1.7

TO-220

VN66AFD

60

3

1.46

TO-220SD

o

1 2 3

TO-220

Performance Curves: VNDQ06 (See Section 7)

1 GATE

2 & TAB - DRAIN
3 SOURCE
TO-220SD
1 SOURCE

2 GATE
3 & TAB - DRAIN

ABSOLUTE MAXIMUM RATINGS (Tc = 25°C unless otherwise noted) 2
PARAMETERS/TEST CONDITIONS

SYMBOL

VN66AD

VN66AFD

Drain-Source Voltage

Vos

60

60

Gate-Source Voltage

VGS

±30

±30

1.7

1.46

1

0.92

3

3

20

15

8

6

UNITS

V

Tc= 25°C
Continuous Drain Current

ID

Tc = 100°C
Pulsed Drain Current 1

IDM

Tc= 25°C
Power Dissipation

Po
Tc = 100°C

Operating Junction and Storage Temperature

A

W
-55 to 150

TJ. Tstg

°C

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE

Junction-to-Case

SYMBOL

VN66AD

VN66AFD

UNITS

RthJC

6.25

8.3

°C/W

~pulse width limited by maximum junction temperature.
Absolute maximum ratings have been revised.
6-55

ICrSiliconix

VN66 SERIES

~ incorporated

ELECTRICAL CHARACTERISTJ,CS 1

LIMITS

VN66 4
PARAMETER

SYMBOL

TYp2

MIN

V GS = 0 V, I D = 10 JlA

70

60

V DS = V GS , ID = 1 mA

1.5

0.8

TEST CONDITIONS 4

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V(BR)DSS

V

VGS(th)
IGSS

IDSS
ID(ON)

rDS(ON)

V DS = 0 V
V GS = ±30 V
V GS = a V
V DS = 48 V

I

Tc= 125°C

I

Tc= 125°C

2.5

± 1

±100

± 5

+ 500

0.05

1

0.3

10

V DS = 10 V, V GS = 10 V

1.8

V GS = 5 V, ID = 0.3 A

1.B

5

1.3

3

2.6

6

V GS = 10 V

ID = 1 A

I

Tc= 125°C

~~~~:6~nductance 3

gFS

V DS = 10 V, ID = 0.5 A

350

Common Source
Output Conductance 3

gas

V Ds =7.5V,I D =0.1 A

1100

nA

J.LA
A

1.5

170

.n.

mS

J.LS

DYNAMIC
Input Capacitance

C 1SS

Output Capacitance

Coss

Reverse Transfer
Capacitance

V DS = 25 V

VGS = 0 V

35

50

25

40

5

10

8

15

9.5

15

f = 1 MHz

C rss

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES: 1.
2.
3.
4.

6-56

V DD = 25 V, R L = 23 .n.

I D =lA,VGEN =10V
RG= 25.n.
(Switching time Is essentially Independent of
operating temperature)

T c = 25°C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 300 JlS, duty cycle S 2 % .
Data sheet limits and/or test conditions have been revised.

ns

VN67

fCrSiliconix

.LB

incorporated

SER~ES

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
BOTTOM VIEW

TO-205AD (TO-39)
PART
NUMBER

V(BR)OSS rOS(ON)
(.0. )
(V)

10
(A)

PACKAGE

VN67AB

60

3.5

0.79

TO-205AD

VN67AD

60

3.5

1.58

TO-220

VN67AFD

60

1.37

3.5

1 SOURCE
2 GATE
3 DRAIN & CASE

TO-220SD

Performance Curves: VNDQ06 (See Section 7)

TO-220/TO-220SD

TOP VIEW

o
TO-220

TO-220SD

1 GATE
2 & TAB - DRAIN
3 SOURCE

1 SOURCE
2 GATE
3 & TAB - DRAIN

1 2 3

ABSOLUTE MAXIMUM RATINGS (Tc = 25°C unless otherwise noted) 2
PARAMETERS/TEST CONDITIONS

SYMBOL

VN67AB

VN67AD

VN67AFD

Drain-Source Voltage

Vos

60

60

60

Gate-Source Voltage

VGS

±20

±30

±30

0.79

1.58

1.37

0.5

1

0.87

3

3

3

5

20

15

2

8

6

UNITS

V

Te= 25DC
Continuous Drain Current

10

Te = 100DC
Pulsed Drain Current 1

10M

Te= 25DC
Power Dissipation
Te=100 DC
Operating Junction and Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

Po

A

W

Tj. T stg

-55 to 150

TL

300

DC

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Case

SYMBOL

VN67AB

VN67AD

VN67AFD

UNITS

RthJe

25

6.25

8.3

DC/W

1 Pulse width limited by maximum junction temperature
2 Absolute maximum ratings have been revised from previous data sheet
6-57

VN67 SERIES

~SilicDnix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VN67 4

PARAMETER

TEST CONDITIONS 4

SYMBOL

TYp2

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V(BR)OSS

VGS = 0 V, 10 = 10.lJ.A

70

60

VGS(th)

Vos = VGS, 10 = 1 mA

1.5

0.8

V

IGSS

less
10

rOS(ON)

Vos = 0 V
VGS =±15 V
VGS = 0 V

I

To=125°C

2.5

+ 1

±100

+ 5

+500

IVos = 60 V

0.05

10

I Vos = 48 V, To = 125°C

0.3

500

VOS = 10 V, VGS = 10 V

1.8

VGS = 5 V, 10 = 0.3 A

1.B

5

1.3

3.5

2.6

7

VGS = 10 V
Ie = 1 A

I

To = 125°C

~~~:6~nductance 3

gFS

Ves=10V,lo=0.5A

350

Common Source
Output Conductance3

gos

Vos =7.5V,lo=0.1 A

1100

1.5

nA
.lJ.A
A

170

.n.

mS
,lJ.S

DYNAMIC
Input Capacitance

C lss

Output Capacitance

Coss

Reverse Transfer
Capacitance

erss

Ves = 25 V
VGS = 0 V
f = 1 MHz

35

50

25

40

5

10

8

15

9.5

15

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES: 1.
2.
3.
4.

6-58

Veo = 25 V, R L = 23.n.
Ie = 1 A, V GEN = 10V, RG=25.n.
(Swltchlnr, time Is essentially Independent
of operat ng temperature)

To = 25°C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW =300.lJ.s, duty cycle :$2%.
Data sheet limits and/or test conditions have been revised.

ns

VN88 SERIES

.r'Siliconix

.LII

incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
PART
V(BR)OSS rOS(ON)
(V)
NUMBER
(n)

TOP VIEW

TO-220/TO-220SD

10

(A)

PACKAGE

VNBBAD

BO

4

1.49

TO-220

VNBBAFD

BO

4

1.29

TO-220SD

o

1 23

TO-220

Performance Curves: VNDQ09 (See Section 7)

1 GATE
2 & TAB - DRAIN
3 SOURCE
TO-220SD
1 SOURCE
2 GATE
3 & TAB - DRAIN

ABSOLUTE MAXIMUM RATINGS (TC
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise noted) 2
SYMBOL

VN88AD

VN88AFD

Drain-Source Voltage

Vos

BO

BO

Gate-Source Voltage

VGS

±30

±30

1.49

1.29

0.94

0.B1

3

3

20

15

B

6

UNITS

V

Tc= 25 D C
Continuous Drain Current

10

Tc = 100D C
Pulsed Drain Current 1

10M

Tc= 25°C
Power Dissipation

Po
Tc = 100°C

Operating Junction and Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

TJ. Tstg

-55 to 150

TL

300

A

W

°C

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Case

SYMBOL

VN88AD

VN88AFD

UNITS

RthJC

6.25

B.3

°C/W

1Pulse width limited by maximum junction temperature
2Absolute maximum ratings have been revised from previous data sheet
6-59

.-rSiliconix
...z:.
incorporated

VN88 SERIES
ELECTRICAL CHARACTERISTICS 1

LIMITS
VN88 4

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)DSS

Vas = 0 V, ID = 10 JJ.A

120

80

VaS(th)

V DS = Vas, ID = 1 mA

1.6

0.8

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance3

V

lass

I DSS
ID(ON)

rDS(ON)

VDS = 0 V
Vas =±15 V
Vas = 0 V

I

Tc=125°C

I V DS = 80 V

IV DS = 64 V,

Tc = 125°C

2.5

± 1

+ 100

± 5

±500

0.03

10

0.3

500

V DS = 10 V, Vas = 10 V

1.8

Vas = 5 V, I D = 0.3 A

4.2

5.6

3.6

4

6.8

8

Vas = 10 V
ID = 1 A

I

Tc=125°C

~~~~~~nductance 3

gFS

V DS = 10 V, ID = 0.5 A

350

Common Source
Output Conductance3

gos

V DS = 7.5 V, ID = 0.1 A

225

1.5

nA

JJ.A
A

170

.n.

mS
JJ.S

DYNAMIC
Input Capacitance

C iss

Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

V DS = 25 V
Vas = 0 V
f = 1 MHz

35

50

15

40

2

10

6

15

6

15

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES:

6-60

1.
2.
3.
4.

VDD - 25 V, R L - 23 .n.
I D = 1 A, VaEN = 10 V
Ra= 25.n.
(Switching time Is essentially Independent of
operating temperature)

T c = 25 ° C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 300 JJ.s , duty cycle S 2 %.
Data sheet limits have been revised.

ns

VN90AB

~Siliconix

.LII

incorporated

N-Channel Enhancement-Mode MOS Transistor

BOTTOM VIEW

TO-205AD (TO-39)

PRODUCT SUMMARY
V(BR)OSS
(V)

rOS(ON)
(.0)

10
(A)

PACKAGE

90

5

0.67

TO-205AD
1 SOURCE
2 GATE
3 DRAIN

Performance Curves: VNDQ09 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TC
PARAMETERS/TEST CONDITIONS

= 25°C unless

otherwise noted)2

SYMBOL

VN90AB

Drain-Source Voltage

VDS

90

Gate-Source Voltage

VGS

±20

UNITS

V

0.67

Te= 25°C
Continuous Drain Current

10
0.42

Te = 100°C
Pulsed Drain Current 1

IDM
Te= 25°C

Power Dissipation

Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

2
5
W

Po
2

Te = 100°C
Operating Junction Temperature

A

Tj

-55 to 150

T stg

-55 to 150

TL

300

SYMBOL

VN90AB

UNITS

RthJe

25

°C/W

°C

THERMAL RESISTANCE2
THERMAL RESISTANCE
Junction-to-Ambient

1 Pulse width limited by maximum junction temperature
2 Absolute maximum ratings have been revised from previous datasheet

6-61

~Siliconix

VN90AB

~ incorpora.ted

ELECTRICAL CHARACTERISTICS 1

LIMITS
VN90AB

PARAMETER

TYp2

SYMBOL

TEST CONDITIONS

MIN

V(BR)OSS

V Gs =OV,l o =10jJ.A

120

90

Vos = VGS, 10 = 1 mA

1.6

0.8

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V
VGS(th)
IGSS

loss
10(ON)

rOS(ON)

~~~;6~nductance 3

gFS

Common Source
Output Conductance3

gos

Vos = 0 V
VGS = ±15
VGS = 0 V

I

To = 125°C

IVos = 90 V
IVos = 72 V,

To = 125°C

±1

±100

±5

+500

0.03

10

0.30

500

Vos = 10 V, VGS = 10 V

1.8

VGS = 5 V, 10 = 0.3A

4.2

VGS = 10 V
10 = 1 A

I

4To = 125°C

2

1.5

jJ.A
A

5.3

3.6

5

6.8

10

350

nA

170

.0.

mS

VOS = 10 V, 10 = 0.5 A
300

jJ.S

DYNAMIC
Input Capacitance

C lss

35

50

15

40

2

10

6

10

8

10

Vos = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

VGS = a V
f = 1 MHz

pF

SWITCHING
Turn-On Delay Time

tON

Turn-Off Delay Time

t OFF

Voo = 25 V, R L = 23 .0.
10 = 1 A, VGEN= 0 to 10 V
RG= 25.0.
(Switching time Is essentially Independent of
operating temperature)

NOTES: 1. To = 25 ° C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300jJ.s, duty cycle :!:2%.
4. This parameter has been revised from previous datasheet.

6-62

ns

VN0300 SERIES

.... Siliconix

~ incorporated

N-Channel Enhancement-Mode MOS Transistors

TO-20SAD (TO·39)

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSS rOS(ON)
(V)
(n)

10

(A)

PACKAGE

VN0300B

30

1.2

1.51

TO-205AD

VN0300L

30

1.2

0.64

TO-92

VN0300M

30

1.2

0.67

TO-237

Performance Curves: VNDQ03

,.
TO-237

BOTTOM VIEW

1 SOURCE
2 GATE
3 DRAIN & CASE

BOTTOM VIEW
1 SOURCE
2 GATE
3 DRAIN

ABSOLUTE MAXIMUM RATINGS (TA

BOTTOM VIEW

TO·92

(See Section 7)

~

1 SOURCE
2 GATE
3 DRAIN

= 25°C unless otherwise noted)3
SYMBOL

VN0300B 2

VN0300L

VN0300M

Drain-Source Voltage

Vos

30

30

30

Gate-Source Voltage

Vas

±20

±30

±30

1.51

0.64

0.67

0.95

0.38

0.43

3

3

3

5

0.8

1

2

0.32

0.4

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA = 100°C
Pulsed Drain Current 1

10M

TA= 25°C
Power Dissipation

Po
TA = 100°C

Operating Junction and Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

Tj. T stg

-55 to 150

lL

300

A

W

°C

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN0300B

VN0300L

VN0300M

UNITS

RthJA

170

156

125

°C/W

1Pulse width limited by maximum junction temperature
2Reference case temperature for all testing
3Absolute maximum ratings have been revised from previous datasheet
6-63

ICrSiliconix

VN0300 SERIES

~ incorporated

ELECTRICAL CHARACTERISTICS1

LIMITS
VN0300 4

TYp2

MIN

SYMBOL

TEST CONDITIONS

V(BR)OSS

V GS = 0 V. 10 = 10,ILA

65

30

VGS(th)

Vos = VGs • 10 = 1 mA

1.5

0.8

Gate-Body Leakage

IGSS

Vos = 0 V. V GS =±30 V

± 1

Zero Gate Voltage
Drain Current

loss

Vos = 30 V. V GS = 0 V

0.0001

10

0.2

500

PARAMETER

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V

10(ON)

rOS(ON)

I Tc= 125°C

2.5
±100

Vos = 10 V. V GS = 10 V

3

VGS = 5 V. 10 = 0.3 A

1.4

3.3

0.85

1.2

V Gs =10V
10 = 1 A

I Tc = 125°C

1

1.8

~~~:6~nductance3

gFS

VOS = 10 V. 10 = 0.5 A

500

Common Source
Output Conductance 3

gos

Vos=10V.10=0.lA

1500

nA

,lLA
A

.0-

1.65
mS

200

jJ.S

DYNAMIC
Input Capacitance

Clss

38

100

28

95

8

25

9

30

13

30

VOS = 15 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

VGS = 0 V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES: 1.
2.
3.
4.

6-64

VOO - 25 V. R L - 24.010 = 1 A. V GEN = 10 V
RG= 25.0(Swltchin~ time is essentially Independent
of operat ng temperature)

T A = 25°C unless otherwise noted.
For design aid only. not subject to production testing.
Pulse test; PW = 300,ILs. duty cycle ~ 2%
Reference case temperature for VN0300B.

ns

VN0603 SERIES

fCrSiliconix

~ incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
PART
NUMBER
VN0603L

VN0603T

V(BR)OSS rOS(ON)
(,(1)
(V)
60

60

3.5

3.5

TO-92

BOTTOM VIEW

10

(A)

PACKAGE

0.30

TO-92

0.22

1 SOURCE
2 GATE
3 DRAIN

SOT-23

TOP VIEW

SOT-23

Performance Curves: VNDS06 (See Section 7)

1 DRAIN
2 SOURCE
3 GATE

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

VN0603L

VN0603T

Drain-Source Voltage

Vos

60

60

Gate-Source Voltage

VGS

±30

±30

0.30

0.22

0.21

0.14

1

0.8

0.8

0.36

0.32

0.14

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA= 100°C
Pulsed Drain Current 1

10M

TA= 25°C
Power Dissipation

PD
TA=100°C

Operating Junction and Storage Temperature

A

W

Tj. Tstg

-55 to 150

It

300

°C

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN0603L

VN0603T

UNITS

RthJA

156

350

°C/W

1Pulse width limited by maximum junction temperature

6-65

VN0603 SERIES

trrSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS1

LIMITS
VN0603L

PARAMETER

TYp2

SYMBOL

TEST CONDITIONS

MIN

V(BR)OSS

Vas = 0 V, 10 = 10 llA

70

60

VaS(th)

Vos = Vas, 10 = 1 mA

2,3

0.8

v

± 1

MAX

VN0603T
MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

60
V

Gate-Body Leakage

lass

Zero Gate Voltage
Drain Current

loss

On-State Drain
Current 3

10(ON)

Drain-Source
On-Reslstance 3

rOS(ON)

Vos = 0 V, Vas =±20
Vos = 48 V
Vas = 0 V

l T = 125°C

Vos = 10 V, Vas = 10 V
Vas = 4.5 V, 10 = 50 mA

~~~~~nductance 3

gFS

Common Source
Output Conductance 3

gos

Vas = 10 V
10 = 0.2 A

J

T J = 125°C

3

0.8

±100

3
±100

0.02

1

1

1

500

500

1000

750

500

4.5

7.5

7.5

3.5

3.5

4.5

7

7

230

100

100

Vos=10V,lo=0.5A
VN0603T

230

100

100

Vos = 10 V, 10 = 50 mA

500

J.1A
mA

2.5

Vos = 10 V, 10 = 0.5 A
VN0603L

nA

.n

mS

J.1S

DYNAMIC
Input Capacitance

Clss

16

60

60

11

40

40

2

10

10

10

15

15

10

15

15

Vos = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

Vas = 0 V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

V OO - 15 V, RL- 23.0.
10 = 0.2 A, V aEN = 10 V
Ra=25.n
(Swltchln?, time Is essentially Independent
of ope rat ng temperature)

NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =30011s, duty cycle S2%.

6-66

ns

VN0605T

.:rSiliconix

~ incorporated

N-Channel Enhancement-Mode MOS Transistor

PRODUCT SUMMARY
SOT-23
V(BR)OSS
(V)

rOS(ON)

10

(0)

(A)

TOP VIEW

PACKAGE

2
60

5

0.18

SOT-23

3
1 DRAIN
2 SOURCE
3 GATE

Performance Curves: VNDS06 (See Section 7)

PRODUCT MARKING

I

VN0605T

ABSOLUTE MAXIMUM RATINGS (TA

V02

= 25°C unless otherwise noted)

PARAMETERS/TEST CONDITIONS

SYMBOL

VN0605T

Drain-Source Voltage

Vos

60

Gate-Source Voltage

VGS

±30

UNITS

V
0.18

TA= 25 D C
Continuous Drain Current

10

0.11

T A = 100D C
Pulsed Drain Current 1

IDM
TA= 25D C

A

0.72
0.36

Power Dissipation

W

PD
0.14

T A = 100D C
Operating Junction Temperature

TJ

-55 to 150

Tstg

-55 to 150

TL

300

SYMBOL

VN0605T

UNITS

RthJA

350

DC/W

Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

II

DC

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient
1Pulse width limited by maximum junction temperature

6-67

f1CrSiliconix

VN0605T

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VN0605T

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)oSS

V Gs =OV,1 0 =10JJ.A

70

60

Vos = VGS, 10 = 1 mA

2.3

0.8

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Thresho)d
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current

V
VGS(th)
IGSS

loss

On-State Drain
Current 3

10(ON)

Drain-Source
On-Reslstance 3

roS(ON)

Vos = 0 V
VGS =±20 V
Vos = 50 V
VGS = 0 V

I

TJ = 125°C

I

TJ = 125°C

3.0

+ 1

±100

± 5

+500

0.02

1

1

500

Vos = 10 V, VGS = 10 V

700

VGS = 4.5 V, 10 = 50 mA

4.5

7.5

3

5

5.5

10

VGS = 10 V
10=0.5A

I

T J = 125°C

~~~:~gnductance 3

gFS

Vos=10V,lo=0.2A

180

Common Source
Output Conductance 3

gos

V os =10V,10=50mA

500

500

nA

JJ.A
mA

80

.0.

mS
JJ.S

DYNAMIC
Input Capacitance

C lss

16

60

11

25

2

5

7

20

11

20

Vos = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

VGS = 0 V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

Voo = 30 V, RL=150 n.
10 = 0.2 A, VGEN= 10 V
RG= 25.0.
(Switching time Is essentially Independent of
operating temperature)

NOTES: 1. T A = 25 ° C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 80 JJ.S, duty cycle :S 1%.

6-68

ns

VN0610L, VN10KE, VN10KM

~Siliconix

.,1;11 incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
BOTTOM VIEW

TO-206AC (TO-52)
PART
NUMBER

V(BR)OSS rOS(ON)
(il)
(V)

10

(A)

PACKAGE

VN0610L

60

5

0.27

TO-92

VN10KE

60

5

0.17

TO-206AC

VN10KM

60

5

0.31

TO-237

Performance Curves: VNDP06
TO-237

1 SOURCE
2 GATE
3 DRAIN

(See Section 7)
BOTTOM VIEW

TO-92

BOTTOM VIEW

1 SOURCE
2 GATE
3 DRAIN

1 SOURCE
2 GATE
3 DRAIN & TAB

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

= 25°C unless

otherwise noted)

SYMBOL

VN0610L

VN10KE

VN10KM

Drain-Source Voltage

Vos

60

60

60

Gate-Source Voltage 2

Vas

15/-0.3

15/-0.3

15/-0.3

0.27

0.17

0.31

0.17

0.11

0.20

1

1

1

O.B

0.3

1

0.32

0.12

0.4

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA = 100°C
Pulsed Drain Current 1

10M

TA= 25°C
Power Dissipation

Po
T A = 100°C

Operating Junction and Storage Temperature

TJ. T stg

-55 to 150

TL

300

A

W

°C

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN0610L

VN10KE

VN10KM

UNITS

RthJA

156

400

125

°C/W

1Pulse width limited by maximum junction temperature
2 Features internal gate-source Zener diode
6-69

.-r'Silicanix

VN0610L, VN10KE, VN10KM

~ incorporated

ELECTRICAL CHARACTERISTICS1

LIMITS
All

PARAMETER

TYp2

SYMBOL.

TEST CONDITIONS

V(BR)OSS

VGs=OV,10=100.l1A

120

60

VGS(th)

Vos = VGS, 10 = 1 mA

1.4

0.8

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

V

Gate-Body Leakage

IGSS

Zero Gate Voltage
Drain Current

loss

On-State Drain
Current 3
Drain-Source
On-Reslstance 3

10(ON)

rOS(ON)

Vos = 0 V, VGS = 15 V
VOS = 48 V
VGS = 0 V

I

T = 125°C

1

10

3

500

1000

Vas = 5 V, 10 = 0.2 A

4

I TJ = 125°C

100

0.7

VOS = 10 V, VGS = 10 V

VGS = 10 V
10=0.5A

2.5

750

mA

3

5

9

gFS

Vos=10V,10=0.5A

300

Common Source
Output Conductance 3

gos

Vos = 7.5 V, 10 = 50 mA

200

.I1A

7.5

5.6

~~~~:6~nductance 3

nA

.0.

mS

100

,I1S

DYNAMIC
Input Capacitance

Clss

Output Capacitance

Coss

Reverse Transfer
Capacitance

CrsB

Vos = 25 V
VGS = 0 V
f = 1 MHz

38

60

16

25

2

5

7

10

9

10

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

VOO= 15 V, RL= 23.0.
10 = 0.6 A, VGEN = 10 V
RG= 25.0.
(Switching time Is essentially Independent
of operating temperature)

NOTES: 1. T A = 25 ° C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300.l1s, duty cycle ~20/0.

6-70

ns

VN0610LL, VN10LE, VN10LM

.:rSiliconix

.LII

incorpora.ted

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
TO-206AC (TO-52)
PART
V(BR)OSS rOS(ON)
(n)
(V)
NUMBER

(A)

PACKAGE

VN0610LL

60

5

0.28

TO-92

VN10LE

60

5

0.38

TO-206AC

VN10LM

60

5

0.32

TO-237

1 SOURCE
2 GATE
3 DRAIN & CASE

Performance Curves: VNDS06 (See Section 7)
TO-92

BOTTOM VIEW

TO-237

BOTTOM VIEW

10

1 SOURCE
2 GATE
3 & TAB - DRAIN

BOTTOM VIEW

1 SOURCE
2 GATE
3 DRAIN

ABSOLUTE MAXIMUM RATINGS (TA

= 25°C unless otherwise noted)
SYMBOL

VN0610LL

VN10LE 2

VN10LM

Drain-Source Voltage

Vos

60

60

60

Gate-Source Voltage

Vas

±30

±20

±30

0.28

0.38

0.32

0.17

0.24

0.2

1.3

1

1.4

0.8

1.5

1.0

0.32

0.6

0.4

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA = 100°C
Pulsed Drain Current 1

10M

TA= 25°C
Power Dissipation

Po
TA = 100°C

Operating Junction and Storage Temperature

Tj. T stg

-55 to 150

TL

300

Lead Temperature
(1/16" from case for 10 seconds)

A

W

°C

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN0610LL

VN10LE

VN10LM

UNITS

RthJA

156

400

125

°C/W

1 Pulse width limited by maximum junction temperature
2 Reference case for all temperature testing

6-71

VN0610LL, VN10LE, VN10LM

ICrSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS1

LIMITS
ALL

PARAMETER

TYp2

SYMBOL

TEST CONDITIONS

MIN

V(BR)OSS

V GS = 0 V, 10 = 100JJ.A

70

60

VGS(th)

Vos = VGs, 10 = 1 mA

2.3

0.6

Vos = 0 V, VGS = ±30 V 5

±1

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

V

Gate-Body Leakage

IGSS

Zero Gate Voltage
Drain Current

loss

On-State Drain
Current 4
Drain-Source
On-Reslstance 3

10(ON)

rOS(ON)

2.5
±100

VOS = 50 V, V GS = 0 V

0.02

10

Vos = 50 V, V GS = 0 V, TJ = 125·C

1

500

VOS = 10 V, V GS = 10 V

1000

V GS = 5 V, ID = 0.2 A

5

7.5

2.5

5

4.4

9

V GS = 10 V

10 = 0.5 A

I TJ = 125·C

~~~~;6~nductance 3

gFS

Vos=10V,10=0.5A

230

Common Source
Output Conductance 3

gos

Vos = 5 V, 10 = 50 mA

500

750

nA
J.lA
mA

.0.

mS

100

J.lS

DYNAMIC
Input Capacitance

C 1SS

16

60

11

25

2

5

7

10

7

10

VOS = 25 V

Output Capacitance

Coss

Reverse Transfer
Capacitance

erss

VGS = 0 V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

Voo-15 V, R L - 23.0.
10=0.6A,VGEN =10V
RG= 25.0.
(Switching time Is essentially Independent
of operating temperature)

NOTES: 1. T A = 25·C unless otherwise noted, Tc = 25·C for VN10LE.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 J.ls, duty cycle ~ 2 0/0.
4. Pulse width limited by maximum Junction temperature.
5. Vas =±20 V for VN10LE.

6-72

ns

VN0808 SERIES

flr]l""Siliconix

~ incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
BOTTOM VIEW

TO-92
PART
NUMBER

V(BR)OSS rOS(ON)
(.(1 )
(V)

10
(A)

PACKAGE

VNOSOSL

SO

4

0.30

TO-92

VNOSOSM

SO

4

0.33

TO-237

1 SOURCE
2 GATE
3 DRAIN

Performance Curves: VNDQ09 (See Section 7)

BOTTOM VIEW

TO-237

1 SOURCE
2 GATE
3 DRAIN

ABSOLUTE MAXIMUM RATINGS (TA
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise noted)
SYMBOL

VN0808L

VN0808M

Drain-Source Voltage

VOS

SO

SO

Gate-Source Voltage

VGS

±30

±30

0.30

0.33

0.19

0.21

1.9

1.9

O.S

1

0.32

0.4

UNITS

V

TA= 25°C
Continuous Drain Current 2

10

TA = 100°C
Pulsed Drain Current 1. 2

10M

TA= 25°C
Power Dissipation

Operating Junction and Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

W

Po
TA = 100°C

A

-55 to 150

TJ. Tstg

°C

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN0808L

VN0808M

UNITS

RthJA

156

125

°C/W

1Pulse width limited by maximum junction temperature
2This parameter has been revised from previous datasheet
6-73

H

VN0808 SERIES
ELECTRICAL CHARACTERISTICS1

Siliconix

incorporated

LIMITS
VN0808

PARAMETER

TYp2

SYMBOL

TEST CONDITIONS

MIN

V(BR)DSS

VGs =OV,I D =10.l1A

120

80

VGS(th)

VDS = VGS, ID = 1 mA

1.6

0.8

IGSS

VDS = 0 V, V GS = ±15 V

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V

IDSS
ID(ON)

rDS(ON)

V DS = 80 V
VGS = 0 V

I

T = 125°C

2

±1

±100

0.03

10

0.3

500

V DS = 10 V, VGS = 10 V

1.8

V GS = 5 V, I D = 0.3 A

4.2

V Gs =10V

3.6

4

6.8

8

ID = 1 A

14TJ = 125°C

~~~:~~nductance3

gFs

V DS = 10 V, ID = 0.5 A

350

Common Source
Output Conductance3

gos

V DS = 10 V, ID = 0.1 A

225

1.5

nA
.l1A
A

.0.

mS

170

jJ.S

DYNAMIC
Input Capacitance

C lss

35

50

15

40

2

10

6

10

8

10

V DS = 25 V
Output Capacitance
Reverse Transfer
Capacitance

Coss

V GS = 0 V

pF

f = 1 MHz
C rss

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES: 1.
2.
3.
4.

6-74

V DD = 25 V, R L = 23.0.
ID=lA,VGEN =10V
RG=25.n
(Switching time Is essentially Independent
of operating temperature)

T A = 25°C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 300.l1s, duty cycle S 2%.
This parameter has been revised from previous datasheet.

ns

VN1206B, VN1206D

tlCrSiliconix

~ incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSS rOS(ON)
(V)
(n)

TO-20SAO (TO-39)

BOTTOM VIEW

10

(A)

PACKAGE

VN12068

120

6

0.59

TO-205AD

VN1206D

120

6

1.19

TO-220

1 SOURCE
2 GATE
3 DRAIN & CASE
TOP VIEW

TO-220

o

Performance Curves: VNDQ12 (See Section 7)

1 GATE
2 & TAB - DRAIN
3 SOURCE

ABSOLUTE MAXIMUM RATINGS (TC
PARAMETERS/TEST CONDITIONS

1 2 3

= 25°C unless otherwise noted) 2
SYMBOL

VN1206B

VN1206D

Drain-Source Voltage

Vos

120

120

Gate-Source Voltage

VGS

±20

±30

0.59

1.19

0.37

0.75

2.5

2.S

5

20

2

8

UNITS

V

Tc= 25°C
Continuous Drain Current

10

Tc = 100°C
Pulsed Drain Current 1

10M

Tc= 2SoC
Power Dissipation

Po
Tc = 100°C

Operating Junction and Storage Temperature
Lead Temperature
(1116" from case for 10 seconds)

A

W

TJ. T stg

-55 to 150

TL

300

°C

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Case

SYMBOL

VN1206B

VN1206D

UNITS

RthJC

25

6.25

°C/W

1Pulse width limited by maximum junction temperature
2Absolute maximum ratings have been revised from previous data sheet
6-75

fCrSilicanix

VN1206B, VN1206D

~ incorporatec

ELECTRICAL CHARACTERISTICS 1

LIMITS
VN1206

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)OSS

VGS = 0 V, 10 = 100 Jl.A

145

120

VGS(th)

Vos = VGS, 10 = 1 mA

1,4

0,8

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V

IGSS

loss
10CON)

rOSCON)

Vos = 0 V
V Gs =±15V
Vos = 120 V
VGS = 0 V

I

T o =125°C

I

To = 125°C

±1

+100

+5

+500

0.001

10

0.5

500

Vos = 10 V, VGS = 10 V

1,6

VGs=2.5V, 10 =0.1 A

6

VGS = 10 V
10=0.5V

I

To = 125°C

2

1

A

6

7

14.8

gFS

VOS = 10 V, 10 = 0.5 A

425

Common Source
Output Conductance3

gos

V os =7.5V,10=0.lA

400

Jl.A

10

3.4

~~~~:6~nductance 3

nA

300

.0.

mS
.uS

DYNAMIC
Input Capacitance

C lss

Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

Vos = 25 V
VGS = 0 V
f = 1 MHz

35

125

15

50

2

20

3

8

2.5

8

7

18

2.5

12

pF

SWITCHING
tdCON)
Turn-On Time
tr
tdCOFF)
Turn-Off Time

Voo = 60 V, RL= 150.0.
10 = 0.4 A, V GEN = 10 V
RG = 25.0.
(Switching time Is essentially
Independent of operating
temperature)

tf
NOTES: 1. To = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300.us, duty cycle :$ 2 % .

6-76

ns

VN1206L, VN1206M

.rSiliconix
..z:.
incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
TO-92
PART
NUMBER

V(BR)OSS rOS(ON)
(V)
(n)

BOTTOM VIEW

10

(A)

PACKAGE

VN1206L

120

6

0.23

TO-92

VN1206M

120

6

0.26

TO-237

1 SOURCE
2 GATE
3 DRAIN

Performance Curves: VNDQ12 (See Section 7)

TO-237

BOTTOM VIEW

1 SOURCE
2 GATE
3 & TAB - DRAIN

ABSOLUTE MAXIMUM RATINGS (TA
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise noted)
SYMBOL

VN1206L

VN1206M

Drain-Source Voltage

Vos

120

120

Gate-Source Voltage

VGS

±30

±30

0.23

0.26

0.15

0.16

2

2

0.8

1

0.32

0.40

UNITS

V

TA= 25°C
Continuous Drain Current

10

T A = 100°C
Pulsed Drain Current 1

10M

TA= 25°C
Power Dissipation

Po
T A = 100°C

Operating Junction and Storage Temperature

A

W
-55 to 150

Tj. T stg

°C

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN1206L

VN1206M

UNITS

RthJA

156

125

°C/W

1Pulse width limited by maximum junction temperature

6-77

III

.:rSiliconix

VN1206L, VN1206M

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VN1206

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)OSS

VGS = 0 V, 10 = 100.l1A

145

120

VGS(th)

Vos = VGS, 10 = 1 mA

1.4

0.8

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V

IGSS

loss
10(ON)

rOS(ON)

Vos = 0 V
VGS =±15 V
Vos = 120 V
VGS = 0 V

I

TJ = 125°C

I

TJ = 125°C

± 1

+ 100

± 5

±500

0.001

10

0.5

500

VOS = 10 V, VGS = 10 V

1.6

VGS = 2.5 V, 10 = 0.1 A

6

VGS = 10 V
10=0.5A

I

TJ = 125°C

2

1

A

6

7

14.8

~~~~:~~nductance3

Vos=10V,lo=0.5A

425

Common Source
Output Conductance3

gos

Vos=7.5V,lo=0.lA

400

.I1A

10

3.4

gFS

nA

300

.0.

mS
,II.S

DYNAMIC
Input Capacitance

Clss

Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

td(ON)
Turn-On Time
t,
t d(OFF)
Turn-Off Time

VOS = 25 V
VGS = 0 V
f = 1 MHz

Voo = 60 V, RL = 150.0.
10 = 0.4 A, V GEN = 10 V
RG= 25.0.
(Switching time Is essentially
Independent of operating
temperature)

tf
NOTES: 1. T A = 25 ° C. unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300.l1s, duty cycle S2%.

6-78

35

125

15

50

2

20

3

8

2.5

8

7

18

2.5

12

pF

ns

VN1210 SERIES

fCrSiliconix

~ incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
TO-92
PART
NUMBER

V(BR)OSS rOS(ON)
(il)
(V)

10
(A)

PACKAGE

VN1210L

120

10

0.18

TO-92

VN1210M

120

10

0.20

TO-237

BOTTOM VIEW

1 SOURCE
2 GATE
3 DRAIN

Performance Curves: VNDQ12 (See Section 7)

TO-237

BOTTOM VIEW

~

~

1 SOURCE
2 GATE
3 DRAIN & TAB

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERSITEST CONDITIONS

= 25°C unless otherwise

noted)

SYMBOL

VN1210L

VN1210M

Drain-Source Voltage

VOS

120

120

Gate-Source Voltage

VGS

±30

±30

0.18

0.20

0.11

0.13

2

2

0.8

1

0.32

0.40

UNITS

V

T A= 25°C
Continuous Drain Current

10

T A = 100°C
Pulsed Drain Current 1

10M

TA= 25°C
Power Dissipation

Po
T A = 100°C

Operating Junction and Storage Temperature

A

W

TJ. Tstg

-55 to 150

TL

300

°C

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN1210L

VN1210M

UNITS

RthJA

156

125

°C/W

1Pulse width limited by maximum junction temperature
6-79

VN1210 SERIES

.:F'Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VN1210

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)DSS

V GS = 0 V. ID = 100)J.A

145

120

VGS(th)

V DS = V GS , ID = 1 mA

1.4

0.8

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3

V

IGSS

I Dss
ID(ON)

V DS = 0 V
V Gs =±15V
V DS = 120 V
V GS = 0 V

I

I

TJ = 125°C
T J = 125°C

VDS = 10 V. V GS = 10 V
VGs=2.5V, I D =O.l A

Drain-Source
On-Reslstance 3

rDS(ON)

V GS = 10 V
ID = 0.5 A

I

TJ = 125°C

2.0

+ 1

+100

+ 5

+500

0.001

10

0.5

500

1.6

1

6

10
10

7

24.7

gFS

VDS=10V,ID=0.5A

425

Common Source
Output Conductance 3

gos

V DS = 7.5 V. ID = 0.1 A

400

)J.A
A

3.4

~~~;~~nductance 3

nA

300

.n.

mS
)J.S

DYNAMIC
Input Capacitance

C 1SS

Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

V DS = 25 V
VGS = 0 V
f = 1 MHz

35

125

15

50

2

20

3

8

2.5

8

7

18

2.5

12

pF

SWITCHING
td(ON)
Turn-On Time
tr
t d(OFF)
Turn-Off Time

V DD = 60 V. R L = 150.n.
I D =0.4A.VGEN =10V
RG = 25.n.
(Switching time Is essentially
Independent of operating
temperature)

tf
NOTES:

6-80

1. T A = 25°C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW = 300)J.s , duty cycle S 2 %.

ns

VN1706B, VN1706D

tlCTSiliconix

.LII

incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
PART
NUMBER

V(BR)DSS rDS(ON)
(il)
(V)

BOTTOM VIEW

TO-20SAD (TO-39)
ID
(A)

PACKAGE

VN1706B

170

6

0.63

TO-205AD

VN1706D

170

6

1.12

TO-220

1 SOURCE
2 GATE
3 DRAIN & CASE
TOP VIEW

TO-220

o

Performance Curves: VNDB24 (See Section 7)

1 GATE
2 & TAB - DRAIN
3 SOURCE

ABSOLUTE MAXIMUM RATINGS (TC

= 25°C unless otherwise noted)
SYMBOL

VN1706B

VN1706D

Drain-Source Voltage

VDS

170

170

Gate-Source Voltage

VGS

±20

±30

0.63

1.12

0.4

0.7

3

3

6.25

20

2.5

S

PARAMETERS/TEST CONDITIONS

1 23

UNITS

V

Tc= 25°C
Continuous Drain Current

ID
Tc = 100°C

Pulsed Drain Current 1

IDM
Tc= 25°C

Power Dissipation

PD
Tc = 100°C

Operating Junction and Storage Temperature

Tjo T stg

A

W

-55 to 150
°C

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN1706B

VN1706D

UNITS

RthJA

170

SO

°C/W

1Pulse width limited by maximum junction temperature

6-S1

ICrSiliconix

VN1706B, VN1706D

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VN1706

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)OSS

VGs=OV,10=100,ll.A

230

170

VGS(lh)

Vos = VGS, 10 = 1 mA

1.4

O.B

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V

IGSS
loss
10(ON)

rOS(ON)

VOS = 0 V
VGs=±15V
Vos = 120 V
VGS = 0 V

I

To = 125°C

I

Tc = 125°C

2.0

+1

+100

+5

+500

0.01

10

1

500

VOS = 10 V, VGS = 10 V

1.5

VGS = 2.5 V, 10 = 0.1 A

7.5

10

5

6

10.8

14.8

VGS = 10 V
10=0.5V

I

To = 125°C

~~~:~~ndu~tance3

gFS

V os =10V,1 0 =0.5A

530

Common Source
Output Conductance3

gos

Vos = 7.5 V, 10 = 0.5 A

475

1

nA
JJ.A
A

300

.0.

mS

JJ.S

DYNAMIC
Input Capacitance

C lss

Output Capacitance

Coss

Reverse Transfer
Capacitance

Crss

VOS = 25 V
VGS = 0 V
f = 1 MHz

105

125

25

50

5

20

3

8

2

8

13

18

9

12

pF

SWITCHING
td(ON)
Turn-On Time
t,
t d(OFF)
Turn-Off Time

Voo = 60 V, R L = 150 .0.
10 = 0.4 A, V GEN = 10 V
RG=25.o.
(Switching time Is essentially
Independent of operating
temperature)

tl
NOTES: 1. To = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300,ll.s, duty cycle :$2%.

6-82

ns

VN1706L, VN1706M

wrSiliconix
.LII inccrpcratec

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
BOTTOM VIEW

TO-92
PART
V(BR)OSS rOS(ON)
(!l )
(V)
NUMBER

10

(A)

PACKAGE

VN1706L

170

6

0.22

TO-92

VN1706M

170

6

0.25

TO-237

1 SOURCE
2 GATE
3 DRAIN

Performance Curves: VNDB24 (See Section 7)

BOTTOM VIEW

TO-237

1 SOURCE
2 GATE
3 DRAIN

ABSOLUTE MAXIMUM RATINGS (TA

= 25°C unless otherwise noted)
SYMBOL

VN1706L

VN1706M

Drain-Source Voltage

Vos

170

170

Gate-Source Voltage

VGS

±30

±30

0.22

0.25

0.14

0.16

2.3

2.5

0.8

1.0

0.32

0.4

PARAMETERS/TEST CONDITIONS

UNITS

V
TA= 25 DC
Continuous Drain Current

10

TA = 100DC
Pulsed Drain Current 1

10M

TA= 25DC
Power Dissipation

Po

TA = 100DC

Operating Junction and Storage Temperature

A

W

Tj. T stg

-55 to 150

TL

300

DC

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN1706L

VN1706M

UNITS

RthJA

156

125

DC/W

1Pulse width limited by maximum junction temperature

6-83

fCrSiliconix

VN1706L, VN1706M

.LJI incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VN1706

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)DSS

V GS =OV.I D =100J.lA

230

170

VGS(th)

V DS = VGs. 10 = 1 mA

1.4

0.8

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V

IGSS

IDSS
10(ON)

rDS(ON)

V DS = 0 V
VGS =±15 V
V DS = 120 V
VGS = 0 V

I

TJ = 125°C

I

TJ = 125°C

2.0

+ 1

+100

+ 5

+500

0.01

10

1

500

VDS = 10 V. VGS = 10 V

1.2

VGS = 2.5 V. I D = 0.1 A

7.5

10

5

6

10.8

14.8

VGS = 10 V
I D =0.5V

I

T J = 125°C

~~~:6~nductance 3

gFS

V Ds =10V.I D =0.5A

530

Common Source
Output Conductance 3

gos

VDS = 7.5 V. ID = 0.5 A

475

1

nA

J.lA
A

300

.n.

mS

J.lS

DYNAMIC
Input Capacitance

C lss

Output Capacitance

Coss

Reverse Transfer
Capacitance

V DS = 25 V
VGS = 0 V

105

125

25

50

5

20

3

8

2

8

13

18

9

12

pF

f = 1 MHz

C rss

SWITCHING
td(ON)
Turn-On Time
tr
t d(OFF)
Turn-Off Time

VDD = 60 V. R L = 150.n.
I D =0.1A.V GEN =10V

RG= 25.n.
(Switching time Is essentially
Independent of operating
temperature)

tf
NOTES:

6-84

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 J.ls • duty cycle :s 2 %.

ns

VN1710 SERIES

~Siliconix

~ incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
BOTTOM VIEW

TO-92
PART
NUMBER

V(BR)OSS rOS(ON)
(.0. )
(V)

10
(A)

PACKAGE

VN1710L

170

10

0.17

TO-92

VN171 OM

170

10

0.19

TO-237

1 SOURCE
2 GATE
3 DRAIN

Performance Curves: VNDB24 (See Section 7)

BOTTOM VIEW

TO-237

1 SOURCE
2 GATE
3 DRAIN

ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

= 25°C unless

otherwise noted)

SYMBOL

VN1710L

VN1710M

Drain-Source Voltage

VOS

170

170

Gate-Source Voltage

VGS

±30

±30

0.17

0.19

0.11

0.12

0.47

0.54

0.8

1.0

0.32

0.4

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA = 100°C
Pulsed Drain Current 1

10M

TA= 25°C
Power Dissipation

Po
T A = 100°C

Operating Junction and Storage Temperature

A

W

Tjo T 5 tg

-55 to 150

TL

300

°C

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN1710L

VN1710M

UNITS

RthJA

156

125

°C/W

1Pulse width limited by maximum junction temperature
6-85

.r"Siliccnix

VN1710 SERIES

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VN1710

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)OSS

Vas = 0 V, 10 = 100.l1A

230

170

VaS(th)

Vos = Vas, 10 = 1 rnA

1.4

0.8

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V

lass

loss
10(ON)

rOS(ON)

Vos = 0 V
Vas =±15 V
Vos = 120 V
Vas = 0 V

+1

2.0
±100

I

TJ = 125°C

±5
0.01

10

I

TJ = 125°C

1

500

Vos = 10 V, Vas = 10 V

1.2

V as =2.5V,lo=0.1 A

8.5

10

6.5

10

14

24.7

Vas = 10 V
10=0.5A

I

T J = 125°C

~~~:6~nductance 3

gFS

V os =10V,1 0 =0.5A

530

Common Source
Output Conductance3

gos

Vos=7.5V,10=0.5A

475

1

nA
.I1A
A

300

.n.
mS
.I1S

DYNAMIC
Input Capacitance

C lss

Output Capacitance

Coss

Reverse Transfer
Capacitance

Crss

Vos = 25 V
Vas = 0 V
f = 1 MHz

110

125

30

50

5

20

3

8

2

8

13

23

9

34

pF

SWITCHING
td(ON)
Turn-On Time

t,
t d(OFF)
Turn-Off Time

Voo = 60 V, R L = 150 .0.
10 = 0.4 A, V aEN = 10 V
Ra = 25.0.
(Switching time Is essentially
Independent of operating
temperature)

t,

NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =300.119, duty cycle :52%.

6-86

ns

VN2010 SERIES

.r'Siliconix

~ incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSS rOS(ON)
(Il)
(V)

BOTTOM VIEW

TO-92
10

(A)

PACKAGE

VN2010L

200

10

0.19

TO-92

VN2020L

200

20

0.08

TO-92

1 SOURCE
2 GATE
3 DRAIN

Performance Curves: VNDQ20 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS

SYMBOL

VN2010L

VN2020L

Drain-Source Voltage

Vos

200

200

Gate-Source Voltage

VGS

±30

±30

0.19

0.08

0.12

0.055

0.8

0.5

0.8

0.8

0.32

0.32

UNITS

V

T A= 25°C
Continuous Drain Current

10

T A = 100°C
Pulsed Drain Current 1

10M

TA= 25°C
Power Dissipation

Po
T A = 100°C

Operating Junction and Storage Temperature

A

W

Tj. Tstg

-55 to 150
°C

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN2010L

VN2020L

UNITS

RthJA

156

156

°C/W

1Pulse width limited by maximum junction temperature

6-87

III

fCrSiliconix

VN2010 SERIES

.LII

ELECTRICAL CHARACTERISTICS 1
VN2010L
PARAMETER

incorporated

LIMITS

SYMBOL

TEST CONDITIONS

TYp2

V(BR)OSS

V GS = 0 V, 10 = 100jJ.A

220

200

VGS(th)

Vos = V GS , 10 = 1 mA

1.3

O.B

MIN

MAX

VN2020L
MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current

200
V

IGSS

loss

On-State Drain
Current 3

10(ON)

Drain-Source
On-Reslstance 3

rOS(ON)

Vos = 0 V
V GS =±20 V
VOS = 160 V
V GS = 0 V

ITJ = 125°C

O.B

+10

± 1
ITJ = 125°C

I.B

2
+10

0.001

1

1

1

100

100

Vos = 10 V, V GS = 10 V

700

V GS = 4.5 V
10 = 50 mA

7

10

20

12.5

20

40

ITJ = 125°C

nA

± 5

~~~~;6~nductance3

9FS

Vos = 15 V, 10 = 100 mA

lBO

Common Source
Output ConductanceS

gos

Vos=15V,10=50mA

150

100

100

125

J.lA

mA

125

.0.

mS
J.lS

DYNAMIC
Input Capacitance
Output Capacitance

Clss
Coss

Vos = 25 V
V GS = 0 V

35

60

60

9

30

30

1

15

15

5

20

20

21

30

'30

pF

f = 1 MHz
Reverse Transfer
Capacitance

erss

SWITCHING 4
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES:

6-88

1.
2.
3.
4.

VOO = 25 V, R L = 250.0.
10 = 100 mA, V GEN = 10 V
RG= 25.0.

ns

T A = 25°C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW =300jJ.s, duty cycle S2%
Switching time Is essentially Independent of operating temperature.

VN2222KM, VN2222L

flCrSiliconix

~ incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
TO-92
PART
NUMBER

V(BR)OSS rOS(ON)
(V)
(.n )

BOTTOM VIEW

10

(A)

PACKAGE

VN2222KM

60

7.5

0.25

TO-237

VN2222L

60

7.5

0.23

TO-92

1 SOURCE
2 GATE
3 DRAIN

TO-237

Performance Curves: VNDP06 (See Section 7)

BOTTOM VIEW

1 SOURCE
2 GATE
3 DRAIN

ABSOLUTE MAXIMUM RATINGS (TA

= 25°C unless otherwise noted)
SYMBOL

VN2222KM

VN2222L

Drain-Source Voltage

Vos

60

60

Gate-Source Voltage 2

VGS

+15, -0.3

+15, -0.3

0.25

0.23

0.16

0.14

1

1

1

0.8

0.4

0.32

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

10

T A = 100°C
Pulsed Drain Current 1

10M

T A= 25°C
Power Dissipation

Po
TA = 100°C

Operating Junction and Storage Temperature

A

W
-55 to 150

TJ' T stg

°C

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN2222KM

VN2222L

UNITS

RthJA

125

156

°C/W

1 Pulse width limited by maximum junction temperature
2 Features internal gate-source zener diode

6-89

.-rSiliconix

VN2222KM, VN2222L

~ incorporatec

ELECTRICAL CHARACTERISTICS1

LIMITS
VN2222

PARAMETER

TYp2

SYMBOL

TEST CONDITIONS

MIN

V(BR)OSS

V as =OV,10=100jJ.A

120

60

VaS(th)

Vos = Vas, 10 = 1 mA

1.3

0.6

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

V

Gate-Body Leakage

lass

Zero Gate Voltage
Drain Current

loss

On-State Drain
Current 3

10(ON)

Drain-Source
On-Reslstance3

rOS(ON)

Vos = 0 V, Vas = 15 V
VOS = 48 V
Vas = 0 V

I

TJ = 125°C

1

2.5
100

0.7

10

3

500

Vos = 10 V, Vas = 10 V

1000

Vas = 5 V, 10 = 0.2 A

4

Vas = 10 V
10 = 0.5 A

3

7.5

5.6

13.5

I TJ = 125°C

~~~:6~nductance 3

gFS

V os =10V,1 0 =0.5A

300

Common Source
Output Conductance 3

gos

Vos=7.5V,10=50mA

200

750

nA
jJ.A
mA

7.5
.0.

mS

100

jJ.S

DYNAMIC
Input Capacitance

C lss

38

60

16

25

2

5

7

10

9

10

Vos = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

Vas = 0 V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

VOO - 15 V, RL= 23.0.
10 = 0.6 A, V aEN = 10 V
Ra= 25.0.
(Switching time Is essentially Independent
of operating temperature I

NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 jJ.s , duty cycle :s 2 %

6-90

ns

VN2222LL, VN2222LM

~Siliconix
incorporated

.LII

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
PART
NUMBER
VN2222LL

VN2222LM

V(BR)OSS rOS(ON)
(V)
(!l )
60

60

7.5

7.5

BOTTOM VIEW

TO-92
10

(A)

PACKAGE

0.23

TO-92

0.26

1 SOURCE
2 GATE
3 DRAIN

TO-237

BOTTOM VIEW

TO-237
Performance Curves: VNDS06 (See Section 7)

1 SOURCE
2 GATE
3 DRAIN

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
SYMBOL.

VN2222L.L

VN2222LM

Drain-Source Voltage

Vos

60

60

Gate-Source Voltage

VGS

±30

±30

0.23

0.26

0.14

0.16

1

1

0.8

1

0.32

0.4

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA = 100°C
Pulsed Drain Current 1

10M

T A= 25°C
Power Dissipation

Po
T A = 100°C

Operating Junction and Storage Temperature

A

W

TJ. Tstg

-55 to 150

TL

300

°C

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN2222LL

VN2222LM

UNITS

RthJA

156

125

°C/W

1 Pulse width limited by maximum junction temperature

6-91

VN2222LL,VN2222LM

.:rSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS1

LIMITS
VN2222

TYp2

SYMBOL

TEST CONDITIONS

V(BR)OSS

VGS = 0 V, 10 = 100J-lA

70

60

VGS(th)

Vos = VGS' 10 = 1 rnA

2.3

0.6

Gate-Body Leakage

IGSS

Vos = 0 V, VGS = ±20 V

±1

Zero Gate Voltage
Drain Current

loss

PARAMETER

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V

10(ON)

rOS(ON)

Vos = 48 V
VGS = 0 V

I TJ = 125°C

10

1

500

1000

VGS = 5 V, 10 = 0.2 A

5

I TJ = 125°C

±100

0.02

VOS = 10 V, VGS = 10 V

VGS = 10 V
10=0.5A

2.5

750

rnA

2.5

7.5
13.5

gFS

Vos=10V,10=0.5A

230

Common Source
Output Conductance 3

gos

Vos = 10 V, 10 = 0.2 A

1200

JJ.A

7.5

4.4

~~~~;6~nductance 3

nA

!l.

rnS

100

JJ.S

DYNAMIC
Input Capacitance

C lss

16

60

11

25

2

5

7

10

7

10

Vos = 25 V
Output Capacitance

Coss

Reverse Transler
Capacitance

C rss

VGS = 0 V
1=1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-OIl Time

tOFF

Voo - 15 V, R L = 23!l.
10 = 0.6 A, V GEN = 10 V
RG = 25!l.
(Switchlnp, time Is essentially Independent
of operat ng temperature)

NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 J-lS , duty cycle :s 20/0 .

6-92

ns

VN2406B, VN2406D

.:r-Siliconix

~ incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSS rOS(ON)

BOTTOM VIEW

TO-20SAD (TO-39)
10

(V)

(.n )

(A)

PACKAGE

VN2406B

240

6

0.63

TO-205AD

VN2406D

240

6

1.12

TO-220

1 SOURCE
2 GATE
3 DRAIN & CASE
FRONT VIEW

TO-220

o

Performance Curves: VNDB24 (See Section 7)

1 GATE
2 & TAB - DRAIN
3 SOURCE

1 2 3

ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
PARAMETERS/TEST CONDITIONS .':'

SYMBOL

VN2406B

VN2406D

Drain-Source Voltage

Vos

240

240

Voltag~

VGS

±20

±30

0.63

1.12

0.4

0.7

3

3

6.25

20

UNITS

V
Gate-Source

Tc= 25DC
Continuous Drain Current

10

Tc = 100DC
Pulsed Drain Current 1

10M

Tc= 25DC
Power Dissipation

Po

Tc = 100DC

Operating Junction and Storage Temperature

W

2.5
T,. Tstg

A

8
-55 to 150
DC

Lead Temperature
(J1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE

Junction-to-Case

SYMBOL

VN2406B

VN2406D

UNITS

RthJC

20

6.25

DC/W

1Pulse width limited by maximum junction temperature

6-93

II

.:rSiliconix

VN2406B, VN2406D

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VN2406

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

V(BR)OSS

Vas = 0 V, 10 = 100 jJ.A

270

240

VaS(th)

Vos = Vas, 10 = 1 mA

1,4

0.8

MIN

MAX

,UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current

V

lass

loss

On-State Drain
Current 3

10(ON)

Drain-Source
On-Reslstance 3

rOS(ON)

Vos = 0 V
Vas =±15 V
VOS = 120 V
Vas = 0 V

I

To = 125°C

I

To=125°C

±1

±100

+5

+500

0.01

10

1

500

Vos = 10 V, Vas = 10 V

1.5

Vas = 2.5 V, 10 = 0.1 A

7.5

Vas = 10 V
10=0.5V

I

To=125°C

2.0

1
10
6

10.8

14.8

~~:n':6~nductance 3

Vos = 10 V, 10 = 0.5 A

530

Common Source
Output Conductance3

gas

Vos = 7.5 V, 10 = 0.5 A

475

C'ss

Vos = 25 V

Output Capacitance

Coss

Vas = 0 V
f = 1 MHz

Reverse Transfer
Capacitance

C rss

jJ.A
A

5

gFS

nA

300

.0.

mS
jJ.S

DYNAMIC
Input Capacitance

110

125

30

50

5

20

3

6

2

6

13

17

9

12

pF

SWITCHING
td(ON)
Turn-On Time
tr
t d(OFF)
Turn-Off Time

VOO= 60 V, R L =150.o.
10= 0.4 A, V aEN = 10 V
Ra= 25.0.
(Switching time Is essentially
Independent of operating
temperature)

tf
NOTES: 1. To = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW =.300jJ.s, duty cycle S2%

6-94

ns

VN2406L, VN2406M

ICrSiliconix

~ incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
BOTTOM VIEW

TO-92
PART
NUMBER

V(BR)OSS rOS(ON)
(fl)
(V)

10

(A)

PACKAGE

VN2406L

240

6

0.22

TO-92

VN2406M

240

6

0.25

TO-237

1 SOURCE
2 GATE
3 DRAIN

Performance Curves: VNDB24 (See Section 7)

BOTTOM VIEW

TO-237

1 SOURCE
2 GATE
3 DRAIN

ABSOLUTE MAXIMUM RATINGS (TA
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise noted)
SYMBOL

VN2406L

VN2406M

Drain-Source Voltage

Vos

240

240

Gate-Source Voltage

VGS

±30

±30

0.17

0.19

0.11

0.12

1.7

2

0.8

1

0.32

0.4

UNITS

V
TA= 25DC
Continuous Drain Current

10

T A = 100DC
Pulsed Drain Current 1

10M

TA= 25DC
Power Dissipation

Po

TA = 100DC

Operating Junction and Storage Temperature

A

W

Tj. T stg

-55 to 150
DC

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN2406L

VN2406M

UNITS

RthJA

156

125

DC/W

1 Pulse width limited by maximum junction temperature

6-95

iii

crSiliconix

VN2406L, VN2406M

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VN2406

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

V(BR)OS:'l

Vas=OV.10=100Jl.A

270

240

VaS(th)

Vos = Vas. 10 = 1 mA

1.4

0.6

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current

V

lass

loss

On-State Drain
Current 3

10(ON)

Drain-Source
On-Reslstance 3

rOS(ON)

Vos = 0 V
Vas =±15 V
Vos = 120 V
Vas = 0 V

I

TJ = 125°C

J

TJ = 125°C

+1

+100

+5

+500

0.01

10

1

500

Vos = 15 V. Vas = 10 V

1.5

Vas =2.5V. 10 '= 0.1 A

7.S

Vas = 10 V
10=0.5A

I

TJ = 125°C

2

1
10
10

10.6

24.7

~~~~:~gnductance 3

VOS = 10 V. 10 = 0.5 A

530

Common Source
Output Conductance3

gos

Vos = 7.5 V. '0 = 0.5 A

475

JJ.A
A

S

gFS

nA

300

.0.

mS
)J.S

DYNAMIC
Input Capacitance

C 'SS

Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

Vos = 25 V
,vas = 0 V
f = 1 MHz

110

125

30

SO

5

20

3

6

2

6

13

23

9

34

pF

SWITCHING
td(ON)
Turn-On Time
t,
td(OFF)
Turn-Off Time

Voo = 60 V. R L = 150 .0.
10 = 0.4 A. V aEN = 10 V
Ra=25.o.
(Switching time Is essentially
Independent of operating
temperature)

tf
NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW =300JJ.s. duty cycle S2%.

6-96

,

ns

.HSiliconix

VN2410 SERIES

incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
TO-92
PART
NUMBER

V(BR)DSS rDS(ON)
(!l)
(V)

ID
(A)

PACKAGE

VN2410L

240

10

0.17

TO-92

VN2410M

240

10

0.19

TO-237

BOTTOM VIEW

1 SOURCE
2 GATE
3 DRAIN
TO-237

Performance Curves: VNDB24 (See Section 7)

BOTTOM VIEW

1 SOURCE
2 GATE
3 DRAIN

ABSOLUTE MAXIMUM RATINGS (TA
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise noted)
SYMBOL

VN2410L

VN2410M

Drain-Source Voltage

VDS

240

240

Gate-Source Voltage

VGS

±30

±30

0.17

0.19

0.11

0.12

1.7

2

0.8

1

0.32

0.4

UNITS

V

TA= 25°C
Continuous Drain Current

ID
TA = 100°C

Pulsed Drain Current 1

IDM
TA= 25°C

Power Dissipation

PD
T A = 100°C

Operating Junction and Storage Temperature

A

W

TJ. Tstg

-55 to 150

TL

300

°C

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN2410L

VN2410M

UNITS

RthJA

156

125

°C/W

1Pulse width limited by maximum junction temperature

6-97

.:r-Siliconix

VN2410 SERIES

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VN2410

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

V(BR)OSS

V Gs=OV,10=100jJ.A

270

240

VGS(th)

Vos = VGS' 10 = 1 mA

1.4

0.8

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current

V

lass

loss

On-State Drain
Current 3

10(ON)

Drain-Source
On-Reslstance 3

rOS(ON)

Vos = a V
VGS =±15 V
Vos = 120 V
VGS = 0 V

+1

I

T J = 125°C

I

TJ = 125°C

0.01

10

1

500

1.2

VGs=2.5V,lo=0.lA

8.5

I

TJ = 125°C

±100

nA

±5

Vos = 15 V, VGS = 10 V

VGS = 10 V
10=0.5A

2

1

A
10

6.5

10

14

24.7

~~~:~~nductance 3

gFS

V os =10V,1 0 =0.5A

530

Common Source
Output Conductance 3

gos

V os =7.5V,1 0 =0.5A

475

C'SS

Vos = 25 V

JJ.A

300

.0.

mS

JJ.S

DYNAMIC
Input Capacitance
Output Capacitance

Coss

Reverse Transfer
Capacitance

erss

VGS = a V
f = 1 MHz

110

125

30

50

5

20

3

8

2

8

13

23

9

34

pF

SWITCHING
td(ON)
Turn-On Time
t,
t d(OFF)
Turn-Off Time
t
NOTES:

6-98

Voo = 60 V, R L = 150.0.
10=0.4A, V GEN = 10V
RG = 25.0.
(Switching time Is essentially
Independent of operating
temperature)

f

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 JJ.s , duty cycle S 2 %.

ns

VN4012 SERIES

fCTSiliconix

~ incorporated

N-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSS rOS(ON)
(.n )
(V)

BOTTOM VIEW

TO-92

-'§

10

(A)

PACKAGE

VN4012L

400

12

0.16

TO-92

VN4012B

400

12

0.42

TO-205AF

VN3515L

350

15

0.15

TO-92

1 SOURCE
2 GATE
3 DRAIN

TO-205AF

BOTTOM VIEW

Performance Curves: VNDV40 (See Section 7)

1 SOURCE
2 GATE
3 DRAIN & CASE

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
VN4012B 2

SYMBOL

VN4012L

Drain-Source Voltage

Vos

400

400

350

Gate-Source Voltage

VGS

±30

±20

±30

0.16

0.42

0.15

0.10

0.27

0.09

0.65

1.3

0.60

0.80

5

0.80

0.32

2

0.32

PARAMETERS/TEST CONDITIONS

VN3515L

UNITS

V

TA= 25°C
Continuous Drain Current

10

T A = 100°C
Pulsed Drain Current 1

10M

T A= 25°C
Power Dissipation

Po
TA=100°C

Operating Junction and Storage Temperature

A

W

-f55

TI. T 5 tg

to 150
°C

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN4012L

VN4012B

VN3515L

UNITS

RthJA

156

125

156

°C/W

1Pulse width limited by maximum junction temperature
2Reference case for all temperature tests

6-99

II

WTSiliconix

VN4012 SERIES

~ incorpora.tec

ELECTRICAL CHARACTERISTICS 1

LIMITS
VN4012

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)OSS

VGS = 0 V, 10 = 100 J.l.A

420

400

VGS(th)

Vos = VGS, 10 = 1 mA

1.3

0.6

VN3515

MAX

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current

350
V

IGSS

loss

On-State Drain
Current 3

10(ON)

Drain-Source
On-Reslstance 3

rOS(ON)

Vos = 0 V
VGS =±20 V

gFS

Common Source
Output Conductanca3

gos

1.8
±10

Vos = 0.8 XV(BR)OSS
VGS = 0 V
ITJ = 125°C

0.002

1

1

0.8

100

100

VOS = 10 V, VGS = 4.5 V

300

VGS = 4.5 V
10 = 100 mA

ITJ = 125° C

nA

+5

VGS = 10 V, 10 = 100 mA

~~~~:~~nductance 3

0.6

+10

±1
ITJ = 125°C

1.8

150

150

J.l.A

mA

9
9.5

12

15

17

30

35

350

125

125

.0.

mS

Vos = 15 V, 10 = 100 mA
17

J.l.S

DYNAMIC
Input Capacitance

Clss

80

90

90

10

20

20

2

5

5

3.5

20

20

2

20

20

25

65

65

15

65

65

Vos = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

VGS = 0 V
f = 1 MHz

pF

SWITCHING
td(ON)
Turn-On Time
t,

Voo= 25 V, R L = 250.0.
10=0.lA,VGEN=10V
RG=25.o.

td(OFF)
Turn-Off Time
tf

(Switching time Is essentially
independent of operating
temperature)

ns

NOTES: 1. T A = 25°C unless otherwise noted, T c =25°C for VN4012B.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 J.l.s, duty cycle S 2%.

6-100

VN45350 SERIES

.r'Siliconix

.L;II incorporated

N-Channel Enhancement-Mode MOS Transistors

PART
NUMBER

BOTTOM VIEW

TO-92

PRODUCT SUMMARY
V(BR)OSS rOS(ON)
(V)
(.n )

~~

10

(A)

PACKAGE

VN45350L

450

350

0.030

TO-92

VN45350T

450

350

0.020

SOT-23

~1 SOURCE ~
2 GATE
3 DRAIN

SOT-23

TOP VIEW

Performance Curves: VND050 (See Section 7)

2

3
PRODUCT MARKING
VN45350T

I

V04

1 DRAIN
2 SOURCE
3 GATE

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
SYMBOL

VN45350L

VN45350T

Drain-Source Voltage

Vos

450

450

Gate-Source Voltage

Vas

±30

±30

0.030

0.020

0.019

0.013

0.12

0.08

0.80

0.35

0.32

0.14

PARAMETERS/TEST CONDITIONS

UNITS

V

T A= 25°C
Continuous Drain Current

10

TA = 100°C
Pulsed Drain Current 1

10M

TA= 25°C
Power Dissipation

Po
T A = 100°C

Operating Junction and Storage Temperature

A

W

TJ. Tstg

-55 to 150

TL

300

°C

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN45350L

VN45350T

UNITS

RthJA

156

350

°C/W

1Pulse width limited by maximum junction temperature
6-101

II

~Siliconix

VN45350 SERIES

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VN45350

SYMBOL

TEST CONDITIONS

TYp2

MIN

Drain-Source
Breakdown Voltage

VIBR)DSS

VGS = 0 V, ID = 10.uA

490

450

Gate-Source
Threshold Voltage

VGSlth)

VDS = VGS, ID = 10.uA

3.5

1.0

PARAMETER

MAX

UNIT

STATIC

Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Resistance 3

V

IGSS

'DSS
IDION)

rDSION)

VDS = 0 V
VGS =±20 V

I TJ

= 125°C

VDS = 250 V
VGS = 0 V

I TJ

= 125°C

±1

± 100

±5

± 500

0.003

0.050

2

5

VDS = 15 V, Vas = 10 V

30

VGS = 10 V, I D = 10 mA

320

VGS = 10 V
'D = 5 mA

4.5

15

mA

.n

650

~?~:~~nductance 3

gFS

VDS = 15 V, ID = 10 mA

14

Common Source
Output Conductance 3

gos

VDS = 10 V, ID = 1 mA

4.5

.uA

350

300

I TJ = 125°C

nA

820
5

mS
JJ,S

DYNAMIC
Input Capacitance

C 1SS

5

20

1.8

10

0.5

5

4.5

10

8

15

15

30

60

100

VDS = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

VGS = 0 V
f = 1 MHz

pF

SWITCHING
tdlON)
Turn-On Time
tr
t dIOFF)
Turn-Off Time

V DD = 25 V, R L = 2500 .n
ID = 10 mA, V GEN = 10 V
RG=25.n
(Switching time Is essentially
Independent of operating
temperature)

tf
NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 .us, duty cycle ~ 2 % .

6-102

ns

VN50300 SERIES

6t'lI"" Siliconix

~ incorporated

N-Channel Enhancement-Mode MOS Transistors

PART
NUMBER

BOTTOM VIEW

TO-92

PRODUCT SUMMARY
V(BR)OSS rOS(ON)
(il)
(V)

~§

10

(A)

PACKAGE

VN50300L

500

300

0.033

TO-92

VN50300T

500

300

0.022

SOT-23

1 SOURCE
2 GATE
3 DRAIN

SOT-23

TOP VIEW

Performance Curves: VND050 (See Section 7)

2
3

PRODUCT MARKING
VN50300T

I

1 DRAIN
2 SOURCE
3 GATE

V01

ABSOLUTE MAXIMUM RATINGS (T A

= 25°C unless otherwise

noted)

SYMBOL

VN50300L

VN50300T

Drain-Source Voltage

Vos

500

500

Gate-Source Voltage

VGS

±30

±30

0.033

0.022

0.021

0.013

0.130

O.OBO

O.BO

0.35

0.32

0.14

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

ID
TA = 100°C

Pulsed Drain Current 1

10M

TA= 25°C
Power Dissipation

PD
T A = 100°C

Operating Junction and Storage Temperature

TJ. Tstg

-55 to 150

TL

300

A

W

°C

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VN50300L

VN50300T

UNITS

RthJA

156

350

°C/W

1Pulse width limited by maximum junction temperature
6-103

iii

.rSiliconix

VN50300 SERIES

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VN50300

SYMBOL

TEST CONDITIONS

TYp2

Drain-Source
Breakdown Voltage

V(BR)OSS

VGS = 0 V, 10 = 10P.A

520

500

Gate-Souroe
Threshold Voltage

VGS(th)

Vos = VGS, 10 = 10P.A

3,5

1.0

PARAMETER

MIN

MAX

UNIT

STATIC

Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Draln-Souroe
On-Resistance 3

V

IGSS

loss
10(ON)

rOS(ON)

~~~;6~nductance 3

gFS

Common Source
Output Conductance3

gos

Vos = 0 V
VGS = ±20 V
Vos = 250 V
VGS = 0 V

I TJ

= 125°C

I TJ = 125°C

±1

± 100

+5

± 500

3

50

2

Vos = 10 V, VGS = 10 V

30

VGS = 10 V, 10 = 10 rnA

250

VGS = 10 V
10 = 5 mA

4,5

5
15

mA

.0.

525
14

J.lA

300

240

I TJ = 125°C

nA

700
5

mS

Vos = 15 V, 10 = 10 mA
4.5

J.lS

DYNAMIC
Input Capacitance

Cis.

5

20

1.8

10

0.5

5

4.5

8

8

12

15

20

60

90

Vos = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

VGS = 0 V
f = 1 MHz

pF

SWITCHING
td(ON)
Turn-On Time
t,
t d(OFF)
Turn-Off Time

Voo= 25 V, R L = 2500.0.
10 = 10 mA, VGEN = 10 V
RG= 25.0.
(Switching time Is essentially
independent of operating
temperature)

tf
NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 p.s , duty cycle S 2 % .

6-104

ns

VP0300 SERIES

ICrSiliconix

~ incorporated

P-Channel Enhancement-Mode MOS Transistors

PART
NUMBER

V(BR)OSS rOS(ON)
(il)
(V)

10

(A)

PACKAGE

VP0300B

-30

2.5

-1.25

TO-205AD

VP0300L

-30

2.5

-0.32

TO-92

VP0300M

-30

2.5

-0.5

TO-237

1 SOURCE
2 GATE
3 DRAIN & CASE

TO-92

Performance Curves: VPMH03 (See Section 7)
TO-237

BOTTOM VIEW

TO-205AD (TO-39)

PRODUCT SUMMARY

BOTTOM VIEW
1 SOURCE
2 GATE
3 & TAB - DRAIN

ABSOLUTE MAXIMUM RATINGS (TA

BOTTOM VIEW

~8
1 SOURCE
2 GATE
3 DRAIN

= 25°C unless otherwise noted)
SYMBOL

VP0300B 2

VP0300L

VP0300M

Drain-Source Voltage

VDS

-30

-30

-30

Gate-Source Voltage

VGS

±20

±30

±30

-1.25

-0.32

-0.5

-0.79

-0.2

-0.32

-3

-2.4

-3

6.25

0.8

1

2.5

0.32

0.4

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA = 100°C
Pulsed Drain Current 1

10M

T A= 25°C
Power Dissipation

PD
TA= 100°C

Operating Junction and Storage Temperature

Tj. T slg

A

W

-55 to 150
°C

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VP0300B

VP0300L

VP0300M

UNITS

RthJA

170

156

125

°C/W

1Pulse width limited by maximum junction temperature
2Reference case temperature for all tests,
6-105

VP0300 SERIES

~Siliconix

~ incorpora.ted

ELECTRICAL CHARACTERISTICS1

LIMITS
VP0300 4

TYp2

MIN

VGS = 0 V. 10'; -10 JJ.A

-55

-30

VGS(th)

VOS = VGs • 10 = -1 mA

-3.6

-2

Gate-Body Leakage

IGSS

Vos = 0 V. VGS = ±30 V

±1

Zero Gate Voltage
Drain Current

loss

PARAMETER

SYMBOL

TEST CONDITIONS

V(BR)OSS

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

V

On-State Drain
Current

10(ON)

Drain-Source
On-Reslstance3

rOS(ON)

VOS = -25 V. VGS = 0 V

I TJ = 125°C

Vos = -10 V. V GS = -12 V
VGS = -12 V
10 = -1 A

I TJ = 125°C

-4.5
± 100

-0.0001

-10

-0.3

-500

-1.6

-1.5

1.8

2.5
3.63

gFS

VOS = -10 V. 10 = -0.5 A

290

Common Source
Output Conductance3

gos

Vos = -7.5 V. 10 = -0.05 A

800

JJ.A
A

3.1

~~~~:~~nductance 3

nA

.0.

mS

200

JJ.5

DYNAMIC
Input Capacitance

C lss

130

150

75

100

20

60

16

30

13

30

Vos = -15 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

VGS = 0 V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES: 1.
2.
3.
4.

6-106

VOO = -25 V. R L = 23.0.
10 = -1 A. V GEN = -10 V
RG= 25.0.
(Swltchln~ time Is essentially Independent
of operat ng temperature)

T A = 25°C unless otherwise noted.
For design aid only. not subject to production testing.
Pulse test; PW =300JJ.s. duty cycle :S2%.
Reference case temperature for VP0300B.

ns

VP0610 SERIES

ICrSiliconix

.L:II

incorporated

P-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSS rOS(ON)
(V)
(il)
-60

VP0610E

10

BOTTOM VIEW

TO-92

10

(A)

PACKAGE

-0.25

TO-206AC

VP0610L

-60

10

-0.18

TO-92

VP0610T

-60

10

-0.12

SOT-23

~8
1 SOURCE
2 GATE
3 DRAIN

TO-206AC (TO-52)

BOTTOM VIEW

Performance Curves: VPDS06 (See Section 7)
SOT-23

TOP VIEW
SOURCE
DRAIN { ]
GATE
1 SOURCE
2 GATE
3 DRAIN & CASE

PRODUCT MARKING
VP0610T

I

V50

ABSOLUTE MAXIMUM RATINGS (TA

= 25°C unless otherwise

noted)

SYMBOL

VP0610E 2

VP0610L

VP0610T

Drain-Source Voltage

Vos

-60

-60

-60

Gate-Source Voltage

VGS

±20

±30

±30

-0.25

-0.18

-0.12

-0.15

-0.11

-0.07

-1

-0.8

-0.4

1.5

0.80

0.36

0.6

0.32

0.14

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA = 100°C
Pulsed Drain Current 1

10M

TA= 25°C
Power Dissipation

Po
T A = 100°C

Operating Junction and Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)

A

W

Tj. T stg

-55 to 150
°C

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VP0610E

VP0610L

VP0610T

UNITS

RthJA

400

156

350

°C/W

6-107

g

V'P0610 SERIES
ELECTRICAL CHARACTERISTICS 1

incorporated

LIMITS
VP0610E

PARAMETER

Siliconix

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)OSS

V GS = 0 V, 10 = -10J,lA

-70

-60

VGS(th)

Vos = VGS , 10 =-1 mA

-2

-1

MAX

VP0610L
MIN

MAX UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
DraIn Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

-60
V

IGSS

loss
10(ON)
rOS(ON)

Vos = 0 V
V GS = ±20 V
Vos = -48 V
V GS = 0 V

TJ = 125°C

I

TJ = 125°C

VOS = -10 V, V GS = -10 V
V GS = -10 V
10 = -0.5 A

I

T J = 125°C

-1

+10

± 1

I

-3.5

-3.5
+10

nA

±5
-0.02

-1

-1

-0.2

-200

-200

-700

-600

-600

mA

8

10

10

15

20

20

~~~;~~nductance3

gFS

VOS = -10 V, 10 = -0.5 A

135

Common Source
Output Conductance3

gos

Vos = -10 V, 10 = -0.2 A

400

80

.uA

80

,n.

mS
J,lS

DYNAMIC
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance

C 1SS
Coss

Vos = -25 V
V GS = 0 V

15

60

60

10

25

25

3

5

5

6

10

10

10

15

15

7

15

15

8

20

20

pF

f = 1 MHz

C rss

SWITCHING
td(ON)
Turn-On Time
tr
t d(OFF)
Turn-Off Time

Voo = -25 V, R L = 133,n.
10 = -0.18 A, VGEN = -10 V
RG = 25,n.
(Switching time Is essentially
Independent of operating
temperature)

tf
NOTES:

6-108

1. T A = 25°C unless otherwise noted, T c = 25°C for VP0610E.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 J,lS, duty cycle ~ 2 %.

ns

g

VP0610 SERIES

Siliconix

incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VP0610T

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

V(BR)OSS

V GS = 0 V, 10 = -10J.lA

-70

-60

VGS(th)

Vos = VGS , 10 = -1 mA

-2

-1

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current

V

IGSS

loss

On-State Drain
Current 3

10(ON)

Drain-Source
On-Reslstance 3

rOS(ON)

Vos = 0 V
V GS = ±20 V
Vos = -48 V
V GS = 0 V

I

TJ = 125°C

I

TJ = 125°C

Vos = -10 V, V GS = -10 V
V GS = -10 V
10 = -0.2 A

I

T J = 125°C

+
+

-3.5

+

1

10

nA

5

-0.02

-1

-0.2

-200

-300

-220

mA

6

10

12

20

~~~;~~nductance 3

gFS

VOS = -10 V, 10 = -0.1 A

90

Common Source
Output Conductance 3

gos

VOS = -10 V, 10 = -0.2 A

400

J.lA

70

.0.

mS
p.S

DYNAMIC
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance

C lss
Coss

15

60

10

25

3

5

6

10

10

15

7

15

8

20

VOS = -25 V
V GS = 0 V

pF

f = 1 MHz

C rss

SWITCHING
td(ON)
Turn-On Time
tr
td(OFF)
Turn-Off Time

Voo = -25 V, R L = 133.0.
10=-0.18A, V GEN =-10V
RG = 25.0.
(Switching time is essentially
independent of operating
temperature)

tf

ns

NOTES: 1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 J.ls , duty cycle S 2 %.

6-109

g

VP0808 SERIES

Siraconix

incorporated

P-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
TO-20SAD
PART
V(BR)OSS rOS(ON)
NUMBER
(V)
(.n )

BOTTOM VIEW

10

(A)

PACKAGE

VP0808B

-80

5

-0.88

TO-205AD

VP0808L

-80

5

-0.28

TO-92

VP0808M

-80

5

-0.31

TO-237

1 SOURCE
2 GATE
3 DRAIN & CASE

TO-237

Performance Curves: VPDV10 (See Section 7)
TO-92

BOTTOM VIEW

£Y
~

BOTTOM VIEW

1 SOURCE
2 GATE
3 DRAIN

1 SOURCE
2 GATE
3 DRAIN & TAB

ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted) 3
SYMBOL

VPOS08B 2

VPOSOSL

VPOSOSM

Drain-Source Voltage

Vos

-80

-80

-80

Gate-Source Voltage

VGS

±20

±30

±30

-0.88

-0.28

-0.31

-0.53

-0.17

-0.20

-3

-3

-3

6.25

0.8

1

2.5

0.32

0.4

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA = 100°C
Pulsed Drain Current 1

10M

TA= 25°C
Power Dissipation

Po
T A = 100°C

Operating Junction and Storage Temperature

TJ. T stg

-55 to 150

TL

300

A

W

°C

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VPOSOSB

VPOSOSL

VP0808M

UNITS

RthJA

170

156

125

°C/W

1Pulse width limited by maximum junction temperature
2Reference case temperature for all testing
3Absolute maximum ratings have been revised
6-110

VP0808 SERIES

~Siliconix

.L;II incorporated
ELECTRICAL CHARACTERISTICS 1

LIMITS
VP0808 4

PARAMETER

SYMBOL

TEST CONDITIONS 4

TYp2

MIN

V(BR)DSS

VGS = 0 V, ID = -10jJ.A

-110

-80

VGS(th)

VDS = VGS' ID = -1 mA

-3.4

-2

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V

IGSS

I DSS
ID(ON)
rDS(ON)

V DS = 0 V
VGS = ±20 V
V DS = -80 V
VGS = 0 V

I

TJ = 125°C

I

T J = 125°C

V DS = -15 V, VGS = -10 V
VGS = -10 V
ID = -1 A

I

TJ = 125°C

-4.5
+100

± 1
+5

+500

-0.0005

-10

-0.1

-500

-2

-1.1
5

4.3

8

gFS

VDS = -10 V, ID = -0.5 A

325

Common Source
Output Conductance3

gas

V DS = -7.5 V, ID = -0.1 A

450

jJ.A

A

2.5

~~~~;6~nductance 3

nA

200

.0.
mS
jJ.S

DYNAMIC
Input Capacitance

C lss

Output Capacitance

Coss

Reverse Transfer
Capacitance

erss

75

150

40

60

18

25

11

15

30

40

20

30

20

30

V DS = -25 V
VGS = 0 V
f = 1 MHz

pF

SWITCHING
td(ON)
Turn-On Time
tr
t d(OFF)
Turn-Off Time
t
NOTES:

1.
2.
3.
4.

V DD = -25 V, R L = 47.0.
ID = -0.5 A, V GEN = -10 V
RG= 25.0.
(Switching time Is essentially
Independent of operating
temperature)

f

ns

T A = 25°C unless otherwise noted, T c = 25°C for VP080BB.
For design aid only, not subject to production testing.
Pulse test; PW = 300 jJ.s , duty cycle S 3 % .
Data sheet limits and/or test conditions have been revised.

6-111

.-:r-Siliconix
...z::.
incorporated

VP1008 SERIES
P-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY

TO-20SAD

PART
V(BR)OSS rOS(ON)
(!l)
(V)
NUMBER

BOTTOM VIEW

10

(A)

PACKAGE

VP100BB

-100

5

-0.79

TO-205AD

VP100BL

-100

5

-0.2B

TO-92

VP100BM

-100

5

-0.31

TO-237

1 SOURCE
2 GATE
3 DRAIN & CASE

BOTTOM VIEW

TO-237
Performance Curves: VPDV10 (See Section 7)
BOTTOM VIEW

TO-92

1 SOURCE
2 GATE
3 DRAIN & TAB

1 SOURCE
2 GATE
3 DRAIN

ABSOLUTE MAXIMUM RATINGS (TA

= 25°C unless

otherwise noted)3

SYMBOL

VP10088 2

VP1008L

VP1008M

Drain-Source Voltage

Vos

-100

-100

-100

Gate-Source Voltage

VGS

±20

±30

±30

-0.79

-0.28

-0.31

-0.53

-0.17

-0.20

-3

-3

-3

6.25

0.8

1

2.5

0.32

0.4

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA = 100°C
Pulsed Drain Current 1

10M

TA= 25°C
Power Dissipation

Po
TA = 100°C

Operating Junction and Storage Temperature

Tj. T 5 tg

A

W

-55 to 150
°C

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VP1008B

VP1008L

VP1008M

UNITS

RthJA

170

156

125

°C/W

~pulse width limited by maximum junction temperature
Reference case temperature for ali testing
3Absolute maximum ratings have been revised
6-112

VP1008 SERIES

.:rSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VP1008 4

PARAMETER

TYp2

SYMBOL

TEST CONDITIONS 4

V(BR)OSS

V GS = 0 V, 10 = -10J.lA

-110

-100

VGS(th)

Vos = VGS , 10 = -1 mA

-3.4

-2

MIN

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Resistance 3

V

IGSS

loss
10(ON)
rOS(ON)

Vos = 0 V
V GS = ±20 V
Vos = -100 V
V GS = 0 V

I

TJ = 125°C

I

TJ = 125°C

Vos = -15 V, V GS = -10 V
V GS = -10 V
10 = -1 A

I

T J = 125°C

-4.5

+ 1

+100

± 5

+500

-0.0005

-10

-0.1

-500

-2

-1.1
5

4.3

6

gFS

VOS = -10 V, 10 = -0.5 A

325

Common Source
Output Conductance3

gos

Vos = -7.5 V, 10 = -0.1 A

450

.I1A
A

2.5

~~~~;~~nductance 3

nA

200

.n
mS
.I1S

DYNAMIC
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance

C 1ss
Coss

Vos = -25 V
V GS = 0 V

75

150

40

60

16

25

11

15

30

40

20

30

20

30

pF

f = 1 MHz

C rss

SWITCHING
td(ON)
Turn-On Time
tr
t d(OFF)
Turn-Off Time

Voo = -25 V, R L = 47.n
10=-0.5A, V GEN =-10V
RG=25.n
(Switching time Is essentially
Independent of operating
temperature)

tf
NOTES:

1.
2.
3.
4.

ns

•

T A = 25°C unless otherwise noted, T c = 25°C for VP1008B.
For design aid only, not subject to production testing.
Pulse test; PW = 300.l1s , duty cycle S 3%.
Data sheet limits and/or test conditions have been revised.

6-113

.HSiliconix

VP2020 SERIES

in c crpcrated

P-Channel Enhancement-Mode MOS Transistors
BOTTOM VIEW

TO-92

~~

~1 SOURCE ~

PRODUCT SUMMARY
PART
NUMBER

2 GATE
3 DRAIN
10

V(BR)OSS rOS(ON)
(V)
(.0)

(A)

PACKAGE
TO-206AC (TO-52)

VP2020L

-200

20

-0.12

TO-92

VP2020E

-200

20

-0.17

TO-206AC

BOTTOM VIEW

Performance Curves: VPDQ20 (See Section 7)
1 SOURCE
2 GATE
3 DRAIN & CASE

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
PARAMETERSITEST CONDITIONS

VP2020E 2

SYMBOL

VP2020L

Drain-Source Voltage

VOS

-200

-200

Gate-Source Voltage

VGS

±30

±20

-0.12

-0.17

-0.08

-0.10

-0.48

-0.60

0.80

1.50

0.32

0.60

UNITS

V
TA= 25DC
Continuous Drain Current

10

T A = 100DC
Pulsed Drain Current 1

10M

TA= 25DC
Power Dissipation

PD

T A = 100DC

Operating Junction and Storage Temperature

A

W

-55 to 150

TJ. Tstg

DC

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VP2020L

VP2020E

UNITS

RthJA

156

400

DC/W

1Pulse width limited by maximum junction temperature
2Reference case for all temperature testing

6-114

VP2020 SERIES

tcrSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VP2020

PARAMETER

TYP 2

MIN

V GS = 0 V, 10 = -10jJ.A

-220

-200

Vos = VGS ' 10 = -1 mA

-1.9

-0.8

SYMBOL

TEST CONDITIONS

V(BR)OSS
VGS(lh)

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

V

Gate-Body Leakage

IGSS

Zero Gate Voltage
Drain Current

loss

On-State Drain
Current 3

10(ON)

Drain-Source
On-Reslstance 3

rOS(ON)

~~~~:6~nductance 3

gFS

Common Source
Output Conductance3

gos

Vos = 0 V
V GS =±20 V
Vos = -160
V GS = 0 V

+ 1

±10

I

T J = 125·C

±5
-0.02

+50

I

TJ = 125·C

-3

-100

Vos = -10 V, V GS = -4.5 V
V GS = -4.5 V
10 = -100 mA

-2.5

I

TJ = 125·C

-270

-1

-100

J.lA
mA

15

20

27

40

150

nA

100

.n
mS

Vos = -10 V, 10 = -100 mA
300

J.lS

DYNAMIC
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance

C lss
Coss

Vos = -25 V
V GS = 0 V

30

70

10

20

2

10

6

10

8

15

18

30

17

25

pF

f = 1 MHz
erss

SWITCHING
td(ON)
Turn-On Time
tr
t d(OFF)
Turn-Off Time

Voo = -25 V, R L = 250.n
10 = -100 mA, V GEN = -10 V
RG = 25.n
(Switching time Is essentially
Independent of operating
temperature)

tf

ns

-

NOTES: 1. T A = 25·C unless otherwise noted, T c = 25·C for VP2020E.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300J.ls, duty cycle S2%.

6-115

VP2410 SERIES

I!CrSiliconix

~ incorporated

P-Channel Enhancement-Mode MOS Transistors

PRODUCT SUMMARY
PART
NUMBER

TO-92

V(BR)OSS rOS(ON)
(.0)
(V)

~~

10

~1

PACKAGE

(A)

VP2410L

-240

10

-0.18

TO-92

VP2410B

-240

10

-0.17

TO-205AF

BOTTOM VIEW

SOURCE
2 GATE
3 DRAIN

TO-205AF

~

BOTTOM VIEW

Performance Curves: VPDV24 (See Section 7)

1 SOURCE
2 GATE

3 DRAIN & CASE

ABSOLUTE MAXIMUM RATINGS (T A

= 25°C unless otherwise

noted)

SYMBOL

VP2410L

VP2410B

Drain-Source Voltage

Vos

-240

-240

Gate-Source Voltage

VGS

±30

±20

-0.18

-0.17

-0.11

-0.10

-0.72

-0.70

0.80

0.73

0.32

0.22

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA = 100°C
Pulsed Drain Current 1

10M

TA= 25°C
Power Dissipation

PD
TA = 100°C

Operating Junction and Storage Temperature

A

W

-55 to 150

TJ. Tstg

°C

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE
Junction-to-Ambient

SYMBOL

VP2410L

VP2410B

UNITS

RthJA

156

170

°C/W

1Pulse width limited by maximum junction temperature

6-116

VP2410 SERIES

.r-Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VP2410

PARAMETER

TYP 2

SYMBOL

TEST CONDITIONS

MIN

V(BR)OSS

V GS = 0 V, 10 = -5,lJ.A

-255

-240

Vos = VGS ' 10 = -2.5 mA

-2.25

-0.8

MAX

UNIT

STATIC
Draln-Souroe
Breakdown Voltage
Gate Threshold
Voltage

V
VGS(th)

Gate-Body Leakage

IGSS

Zero Gate Voltage
Drain Current

loss

On-State Drain
Current 3

10(oN)

Draln-Souroe
On-Reslstance 3

rOS(ON)

Vos = 0 V
V Gs =±20V
Vos = -180 V
V GS = 0 V

I

TJ = 125°C

I

TJ = 125°C

Vos = -10 V, V GS = -4.5 V
V GS = -10 V, 10 = -100 mA
V GS = -4.5 V
10 = -100 mA

I

T J = 125°C

-2.5

±1

±10

+5

+50

-0.001

-1.0

-0.40

-100

-300

-150

nA

,lJ.A
mA

7
8.5

10

15.5

20

~~~~~nductance 3

gFS

VOS = -10 V, 10 = -100 mA

175

Common Source
Output Conductance 3

gos

Vos = -10 V, 10 = -50 mA

125

125

,n

mS

DYNAMIC
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance

Ciss

Coss

Vos = -25 V
V GS = 0 V

65

95

20

30

8

15

7

15

18

30

45

70

45

60

pF

f = 1 MHz
erss

SWITCHING
td(ON)
Turn-On Time
tr
t d(OFF)
Turn-Off Time
t
NOTES:

VOO = -25 V, R L = 250 ,n
10=-100mA, V GEN =-10V
R G =25,n
(Switching time Is essentially
Independent of operating
temperature)

f

ns

1. T A = 25·C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 ,lJ.S, duty cycle S 2 %.

6-117

.:r-Siliconix

VQ1000 SERIES

~ incorporated

N-Channel Enhancement-Mode MOS Transistor
Arrays

PRODUCT SUMMARY
PART
V(BR)OSS rOS(ON)
(V)
NUMBER
(.n )

14-PIN DIP
SIDE BRAZE

10

(A)

TOP VIEW

PACKAGE

Oual-In-Llne Package

VQ1000J

60

5.5

0.225

Plastic

VQ1000P

60

5.5

0.225

Side Braze
14-PIN PLASTIC

~
¥VD

Performance Curves: VNDS06 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TA
PARAMETERS/TEST CONDITIONS

= 25°C unless

otherwise noted)

SYMBOL

VQ1000J

VQ1000P

Drain-Source Voltage

Vos

60

60

Gate-Source Voltage

VGS

±30

±20

0.225

0.225

0.14

0.14

±1

±1

1.3

1.3

0.52

0.52

2

2

0.8

0.8

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA= 100°C
Pulsed Drain Current 1

10M

TA= 25°C

A

Power Dissipation - Single
T A= 100°C
Po
TA= 25°C

W

Power Dissipation - Quad
TA= 100°C
Operating Junction and Storage Temperature

Tj. Tstg

-55 to 150

TL

300

°C

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE

SYMBOL

Junction-to-Ambient - Single

VQ1000J

VQ1000P

96.2

96.2

62.5

62.5

°C/W

RthJA
Junction-to-Ambient - Quad
1Pulse width limited by maximum junction temperature.

6-118

UNITS

VQ1000 SERIES

.r'Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VQ1000

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)OSS

V GS = 0 V, 10 = 100 j.lA

70

60

VGS(th)

Vos = VGS , 10 = 1 rnA

2.3

0.8

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Resistance 3

V

IGSS
loss
10(ON)

rOS(ON)

Vos = 0 V
V GS =±10 V
Vos = 60 V
V GS = 0 V

I

Ivos = 48 V, TJ = 125°C

±5
0.02

10

1

500

Vos = 10 V, V GS = 10 V

1000

V GS = 5 V, 10 = 0.2 A

5

V GS = 10 V
10=0.3A

+ 100
+ 500

± 1
T J = 125°C

I

TJ = 125°C

2.5

500

rnA

2.5

5.5
7.6

gFS

VOS = 10 V, 10 = 0.5 A

230

Common Source
Output Conductance3

gos

Vos = 7.5 V, 10 = 50 rnA

500

.I1A

7.5

4.4

~~~~;~~nductance 3

nA

100

.0.

mS

.I1S

DYNAMIC
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance

C rss
Coss

Vos = 25 V
V GS = 0 V

16

60

11

25

2

5

7

10

7

10

pF

f = 1 MHz
C rss

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES:

Voo = 15 V, R L = 23.0.
10= 0.6A,VGEN =10V
RG= 25.0.
(Switching time Is essentially Independent
of operating temperature)

ns

1. T A = 25 ° C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300 j.lS , duty cycle ~ 2%.

6-119

.:r'Siliconix

VQ1001 SERIES

~ incorporated

N-Channel Enhancement-Mode MOS Transistor
Arrays

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSS rOS(ON)
(V)
(n)

14-PIN DIP
SIDE BRAZE

10

(A)

TOP VIEW

PACKAGE

Oual-In-Une Package

VQ1001J

30

1

0.85

Plastic

VQ1001P

30

1

0.85

Side Braze
14-PIN PLASTIC

.,;.,,,

~

Performance Curves: VNDQ03 (See Section 7)

.

.

.

,

ABSOLUTE MAXIMUM RATINGS (T A = 25°C unless otherwise noted)
SYMBOL

VQ1001J

VQ1001P

Drain-Source Voltage

Vos

30

30

Gate-Source Voltage

VGS

±30

±20

0.85

0.85

0.53

0.53

±3

±3

1.3

1.3

0.52

0.52

2

2

0.80

0.80

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA= 100°C
Pulsed Drain Curren} 1

10M

TA= 25°C

A

Power Dissipation - Single
TA= 100°C
Po
TA = 25°C

W

Power Dissipation - Quad
TA= 100°C
Operating Junction and Storage Temperature

-55 to 150

TJ. Tstg

°C

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE

SYMBOL

Junction to Ambient - Single

VQ1001J

VQ1001P

96.2

96.2

62.5

62.5

RthJA
Junction to Ambient - Quad
1Pulse width limited by maximum junction temperature

6-120

UNITS

°C/W

~Siliconix
incorporated

VQ1001 SERIES

.LII

ELECTRICAL CHARACTERISTICS 1

LIMITS
VQ100l

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)DSS

V GS =OV,I D =10.l1A

65

30

VGS(th)

V DS = V GS , ID = 1 mA

1.5

0.8

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

V

Gate-Body Leakage

IGSS

Zero Gate Voltage
Drain Current

IDSS

V DS = 0 V
V Gs =±15V
V DS = 30 V
V GS = 0 V

On-State Drain
Current 3

ID(ON)

Drain-Source
On-Reslstance 3

rDS(ON)

TJ = 125°C

I V DS = 24 V, T J

= 125°C

V DS = 10 V, V GS = 12 V
V GS = 5 V, I D = 0.2 A
V GS = 12 V
ID = 1 A

± 100
± 500

± 1

I

I

4TJ = 125°C

2.5

±5
0.0001

10

0.2

500

3

2

1.4

1.75
1

1.65

2

gFS

V DS = 10 V, ID = 0.5 A

500

Common Source
Output Conductance 3

gos

V DS = 10 V, ID = 0.1 A

1500

.I1A
A

0.85

~~~~:~~nductance 3

nA

200

.n.

mS
.uS

DYNAMIC
Input Capacitance

C lss

38

110

28

110

8

35

9

30

13

30

V DS = 15 V
Output Capacitance
Reverse Transfer
Capacitance

Coss

V GS =

aV

pF

f = 1 MHz
erss

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES:

1.
2.
3.
4.

V DD = 15 V, R L = 23.n.
ID= 0.6A,V GEN =10V
RG= 25.n.
(Switching time Is essentially Independent
of operating temperature)

ns

T A = 25°C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 300.l1s , duty cycle S 2 %.
This parameter has been revised from previous data sheet.

iii

6-121

VQ1004 SERIES

......Siliconix

~ incorporatec

N·Channel Enhancement·Mode MOS Transistor
Arrays

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSS rOS(ON)
(V)
(.0)

14·PIN DIP
SIDE BRAZE

10

(A)

PACKAGE

TOP VIEW

~
.:.;.~;.
....... -: ..

Oual-In-Llne Package

.. ~ ..". « .

VQ1004J

60

3.5

0.46

Plastic

VQ1004P

60

3.5

0.46

Side Braze
14·PIN PLASTIC

Performance Curves: VNDQ06 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TA

= 25°C unless otherwise

noted)

SYMBOL

VQ1004J

VQ1004P

Drain-Source Voltage

Vos

60

60

Gate-Source Voltage

VGS

±30

±20

0.46

0.46

0.26

0.26

±2

±2

1.3

1.3

0.52

0.52

2

2

0.8

0.8

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA= 100°C
Pulsed Drain Current 1

IDM
TA= 25°C

A

Power Dissipation - Single
TA= 100°C
PD
TA= 25°C

W

Power Dissipation - Quad
TA= 100°C
Operating Junction and Storage Temperature

-55 to 150

TJ. Tstg

°C

Lead Temperature
(1 /1 6" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE

SYMBOL

Junction to Ambient - Single

VQ1004J

VQ1004P

96.2

96.2

62.5

62.5

°CfW

RthJA
Junction to Ambient - Quad
1Pulse width limited by maximum junction temperature.

6-122

UNITS

VQ1004 SERIES

fCrSiliconix
.z.
incorporated
ELECTRICAL CHARACTERISTICS 1

LIMITS
VQ1004

PARAMETER

SYMBOL

TYp2

MIN

ID = 10 jJ.A

70

60

VDS = VGS, ID = 1 rnA

1.5

0.8

TEST CONDITIONS

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

V(BR)DSS

VGS =

a v,

V
VGS(th)

Gate-Body Leakage

IGSS

V DS = a V
V Gs =±15V

Zero Gate Voltage
Drain Current

I DSS

V DS = 60 V
VGS =

On-State Drain
Current 3

ID(ON)

Drain-Source
On-Resistance 3

rDS(ON)

I

TJ = 125°C

a V IvDS = 48 V,

TJ = 125°C

±1

± 100

±5

+500

0.05

1

0.3

500

VDS = 10 V, VGS = 10 V

1.8

VGS = 5 V, ID = 0.3 A

1.8

5

1.3

3.5

2.6

4.9

VGS = 10 V
ID = 1 A

I

TJ = 125°C

~~~~;~~nductance 3

gFS

V DS = 10 V, ID = 0.5 A

350

Common Source

gos

VDS = 10 V, ID = 0.1 A

1100

Output Conductance 3

2.5

1.5

nA
jJ.A
A

170

.0.

mS
jJ.$

DYNAMIC
Input Capacitance

C lss

35

60

25

50

5

10

8

10

9

10

V DS = 25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

VGS = a V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES:

V DD = 25 V, R L = 23.0.
I D = 1 A, V GEN = 10 V
RG=25.o.
(Switching time Is essentially Independent
of operating temperature)

ns

1. T A = 25°C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test: PW = 300jJ.s, duty cycle :>2%

6-123

VQ1006 SERIES

~Siliconix

~ incorporated

N-Channel Enhancement-Mode MOS Transistor
Arrays

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSS rOS(ON)
(11)
(V)

14-PIN DIP
SIDE BRAZE
10

"."
~
.)

90

4.5

0.40

Plastic

VQ1006P

90

4.5

0.40

Side Braze

Oual-In-Line Package

..... :.

""

VQ1006J

TOP VIEW

.

PACKAGE

(A)

"

14-PIN PLASTIC

Performance Curves: VNDQ09 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TA

= 25°C unless otherwise noted)
SYMBOL

VQ1006J

VQ1006P

Drain-Source Voltage

VDS

90

90

Gate-Source Voltage

VGS

±30

±20

0.40

0.40

0.23

0.23

±2

±2

1.3

1.3

0.52

0.52

2

2

O.B

O.B

PARAMETERS/TEST CONDITIONS

UNITS

V
T A= 25DC
ID

Continuous Drain Current.
TA= 100DC
Pulsed Drain Current 1

IDM
T A= 25DC

A

Power Dissipation - Single
TA= 100DC
PD

T A= 25DC
Power Dissipation - Quad

TA=100 DC

Operating Junction and Storage Temperature

W

-55 to 150

TJ. Tstg

DC

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE

SYMBOL

Junction-to-Ambient - Single

VQ1006J

VQ1006P

96.2

96.2

62.5

62.5

DC/W

RthJA
Junction-to-Ambient - Quad
1Pulse width limited by maximum junction temperature.

6-124

UNITS

VQ1006 SERIES

.-rSiliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
Val00S

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)OSS

V Gs =OV,1 0 =10.ll.A

120

90

VGS(th)

Vos = VGS , ID = 1 mA

1.S

O.B

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V

IGSS

loss
10(ON)

rOS(ON)

VOS = 0 V
V Gs =±15V
V DS = 90 V
V GS = 0 V

gFS

Common Source
Output Conductance 3

gos

IVos = 72 V, TJ = 12SoC

±1

±100

±S

±SOO

0.03

1

0.3

SOO

Vos = 10 V, V GS = 10 V

1.B

V GS = S V, 10 = 0.3 A

4.7

5

4.1

4.5

7.7

B.S

V GS = 10 V
ID = 1 A

~~~~~~nductance 3

I

TJ = 12SoC

2.5

I

4T J = 125°C

V DS = 10 V, 10 = 0.5 A
Vos=10V,10=0.lA

350

1.5

nA

.Il.A
A

170

.0.

mS

225

.Il.S

DYNAMIC
Input Capacitance

C lss

35

60

15

SO

2

10

6

10

B

10

V DS = 25 V
Output Capacitance
Reverse Transfer
Capacitance

Coss

V GS = 0 V

pF

f = 1 MHz
erss

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES:

1.
2.
3.
4.

VOO - 25 V, R L = 23 .0.
I D = 1 A, VGEN = 10 V
RG = 25.0.
(Switching time Is essentially Independent of
operating temperature)

ns

T A = 25°C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 300).J,s , duty cycle S 2 % .
This parameter has been revised from previous data sheet.

6-125

~Siliconix

VQ2000 SERIES

~ incorporated

P-Channel Enchancement-Mode MOS Transistor
Arrays

PRODUCT SUMMARY
PART
NUMBER

14-PIN DIP
SIDE BRAZE

V(BR)OSS rOS(ON)
(V)
(n)

10

PACKAGE

(A)

TOP VIEW

.<

~

Oual-In-Line Package

..... :,: .......

VQ2000J

-60

10

-0.24

Plastic

VQ2000P

-60

10

-0.24

Side Braze

..

.

'

14-PIN PLASTIC

~

Performance Curves: VPDS06 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (T A

"'Y.
'

.'

,

= 25°C unless otherwise

noted)

SYMBOL

VQ2000J

VQ2000P

Drain-Source Voltage

Vos

-60

-60

Gate-Source Voltage

VGS

±30

±20

-0.24

-0.24

-0.15

-0.15

±O.B

±O.B

1.3

1.3

0.52

0.52

2

2

O.B

O.B

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA= 100°C
Pulsed Drain Current 1

10M

TA= 25°C

A

Power Dissipation - Single
TA= 100°C
Po
T A= 25°C

W

Power Dissipation - Quad
T A= 100°C
Operating Junction and Storage Temperature

-55 to 150

TJ. Tstg

°C

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE

SYMBOL

Junction-to-Ambient - Single

VQ2000J

VQ2000P

96.2

96.2

62.5

62.5

°C/W

RthJA
Junction-to-Ambient - Quad
1Pulse width limited by maximum junction temperature

6-126

UNITS

VQ2000 SERIES

fiCTSiliconix
.LII incorporated
ELECTRICAL CHARACTERISTICS 1

LIMITS
VQ2000

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)DSS

VGS = 0 V. ID = -10.uA

-70

-60

VGS(th)

VDS = VGs. ID = -1 mA

-1.7

-1

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

V

Gate-Body Leakage

IGSS

V DS = 0 V
VGS = ±20 V

Zero Gate Voltage
Drain Current

I DSS

VDS = -48 V

On-State Drain
Current 3

ID(ON)

Drain-Source
On-Reslstance 3

rDS(ON)

VGS = 0 V

I

TJ = 125°C

I

T J =125°C

+1

+10

±5

+50

-0.02

-1

-0.2

-200

V DS = -10 V. VGS = -4.5 V

-80

VGS = -4.5 V. ID = -25 mA

15

VGS = -10 V
I D = -0.25 A

I

TJ = 125°C

-3

-40
25
10

15

20

gFS

VDS = -10 V. ID = -0.1 A

90

Common Source
Output Conductance 3

gos

V DS = -10 V. ID = -0.1 A

400

.uA
mA

8

~~~~;~~nductance3

nA

60

.a

mS

.us

DYNAMIC
Input Capacitance

C ISS

15

60

10

25

3

5

6

15

10

20

7

15

8

20

V DS = -25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

VGS = 0 V
f = 1 MHz

pF

SWITCHING
td(ON)
Turn-On Time
tr
td(OFF)
Turn-Off Time

V DD = -25 V. R L = 133.a
ID = -0.18 A. V GEN = -10 V
RG=25.a
(Switching time Is essentially
Independent of operating
temperature)

tf
NOTES:

ns

1. T A = 25 ° C unless otherwise noted.
2. For design aid only. not subject to production testing.
3. Pulse test; PW = 300.us • duty cycle S 2%.

6-127

VQ2001 SERIES

.rSiliconix

~ incorporated

P-Channel Enhancement-Mode MOS Transistor
Arrays

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSS rOS(ON)
(V)
(n)

14-PIN DIP
SIDE BRAZE

10
(A)

PACKAGE

VQ2001J

-30

2

-0.6

Plastic

VQ2001P

-30

2

-0.6

Side Braze

TOP VIEW

~

Oual-In-Une Package

~~D

14-PIN PLASTIC
Performance Curves: VPMH03 (See Section 7)

ABSOLUTE MAXIMUM RATINGS (TA

= 25°C unless otherwise

noted)

SYMBOL

VQ2001J

VQ2001P

Drain-Source Voltage

Vos

-30

-30

Gate-Source Voltage

VGS

±30

±20

-0.6

-0.6

-0.12

-0.12

±2

±2

1.3

1.3

0.52

0.52

2

2

0.8

0.8

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA= 100°C
Pulsed Drain Current 1

10M

TA= 25°C

A

Power Dissipation - Single
TA= 100°C
Po
TA= 25°C

W

Power Dissipation - Quad
TA = 100°C
Operating Junction and Storage Temperature

Tj. Tstg

-55 to 150
°C

Lead Temperature
(1/16" from case for 10 seconds)

h

300

THERMAL RESISTANCE
THERMAL RESISTANCE

SYMBOL

Junction-to-Ambient - Single

VQ2001J

VQ2001P

96.2

96.2

62.5

62.5

°C/W

RthJA
Junction-to-Ambient - Quad
1Pulse width limited by maximum junction temperature.

6-128

UNITS

g

VQ2001 SERIES

Siliconix

inccrpcr.ated

LIMITS

ELECTRICAL CHARACTERISTICS 1

VQ2001
PARAMETER

SYMBOL

TYp2

MIN

VGS = 0 V, ID = -10.uA

-55

-30

VDS = VGS, ID = -1 mA

-3.6

-2

TEST CONDITIONS

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

V(BR)DSS

V
VGS(th)
lass
I DSS
ID(ON)
rDS(ON)

V DS = 0 V
VGS =±16 V
VDS = -30 V
VGS = 0 V

I

TJ = 125°C

I

TJ = 125°C

V DS = -10 V, VGS = -12 V
Vas = -12 V
ID = -1 A

I

T J = 125°C

-4.5

+1

±100

±5

±500

-0.0001

-10

-0.3

-500

-1.6

-1.5
2

3.1

3.6

gFS

VDS = -10 V, ID = -0.5 A

290

Common Source
Output Conductance 3

gos

V DS = -7.5 V, ID = -0.05 A

800

J.lA
A

1.8

~~~~;~~nductance 3

nA

200

.0.

mS

J.lS

DYNAMIC
Input Capacitance

Clss

130

150

75

100

20

60

18

30

13

30

V DS = -15 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

erss

Vas = 0 V
f = 1 MHz

pF

SWITCHING
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES:

V DD = -15 V, RL= 23.0.
ID = -0.6 A, VGEN = -10 V
RG= 25.0.
(Switching time Is essentially Independent of
operating temperature)

ns

1. T A = 25 ° C unless otherwise noted.
2. For design aid only, not subject to production testing.
3. Pulse test; PW = 300.us , duty cycle S 2 % .

-6-129

.-r-Siliconix

VQ2004 SERIES

~ incorporated

P-Channel Enhancement-Mode MOS Transistor
Arrays

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSS rOS(ON)
(V)
(0)

14-PIN DIP
SIDE BRAZE

10

(A)

PACKAGE

VQ2004J

-60

5

-0.41

Plastic

VQ2004P

-60

5

-0.41

Side Braze

TOP VIEW

~
.~..

Oual-In-Llne Package

.. ' ., .' .. ..
.

,

~

14-PIN PLASTIC

~

Performance Curves: VPDV10 (See Section 7)

~YU
ABSOLUTE MAXIMUM RATINGS (T A
PARAMETERS/TEST CONDITIONS

= 25°C unless otherwise noted)
SYMBOL

VQ2004J

VQ2004P

Drain-Source Voltage

Vos

-60

-60

Gate-Source Voltage

VGS

±30

±20

-0.41

-0.41

-0.23

-0.23

±3

±3

1.3

1.3

0.52

0.52

2

2

0.8

0.8

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA = 100°C
Pulsed Drain Current 1

10M

TA= 25°C

A

Power Dissipation - Single
TA= 100°C
Po
TA= 25°C

W

Power Dissipation - Quad
TA= 100°C
Operating Junction and Storage Temperature

TJ. Tstg

-55 to 150

TL

300

°C

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE
THERMAL RESISTANCE

SYMBOL

Junction-to-Ambient - Single

VQ2004J

VQ2004P

96.2

96.2

62.5

62.5

°C/W

RthJA
Junction-to-Ambient - Quad
1Pulse width limited by maximum junction temperature.

6-130

UNITS

g

VQ2004 SERIES

Siliconix

incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
VQ2004 4

PARAMETER

SYMBOL

TEST CONDITIONS

TYp2

MIN

V(BR)OSS

V GS = 0 V, 10 = -10 J1A

-110

-60

VGS(th)

VOS = V GS , 10 = -1 mA

-3.4

-2

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current

V

IGSS
loss

On-State Drain
Current 3

10(ON)

Drain-Source
On-Reslstance 3

rOS(ON)

Vos = 0 V
V Gs =±30V
Vos = -60 V
V GS = 0 V

gFS

Common Source
Output Conductance 3

gos

TJ = 125°C

I

TJ = 125°C

Vos = -10 V, V GS = -10 V
V GS = -10 V

10 = -1 A

~~~~:~~nductance 3

I

I

TJ = 125°C

VOS = -10 V, 10 = -0.5 A
VOS

=-7.5 V,

10 = -0.1 A

-4.5

+ 1

+100

+5

±500

-0.0005

-10

-0.1

-500

-2

-1

JJ.A
A

2.5

5

4.3

8

325

nA

200

.0.

mS

450

JJ,S

DYNAMIC
Input Capacitance

C lss

75

150

40

60

18

25

11

15

30

40

20

30

20

30

Vos = -25 V

Output Capacitance
Reverse Transfer
Capacitance

Coss

V GS = 0 V

pF

f = 1 MHz
erss

SWITCHING
td(ON)
Turn-On Time
tr
td(OFF)
Turn-Off Time

Voo = -25 V, R L = 47.0.
10 = -0.5 A, VGEN= -10 V
RG=25.o.
(Switching time Is essentially
Independent of operating
temperature)

tf
NOTES: 1.
2.
3.
4.

ns

III

T A = 25°C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 300 J1s, duty cycle S 2%.
Data sheet limits have been revised.

6-131

.r'Siliconix

VQ2006 SERIES

~ incorporated

P·Channel Enhancement·Mode MOS Transistor
Arrays

PRODUCT SUMMARY
PART
NUMBER

V(BR)OSS rOS(ON)
(V)
(.n )

14·PIN DIP
SIDE BRAZE
10

PACKAGE

(A)

TOP VIEW

.. :.: .... "

~

Oual-In-Llne Package

~ .... :'. ~17'

VQ2006J

-90

5

-0.41

VQ2006P

-90

5

-0.41

Plastic

,

Side Braze
14·PIN PLASTIC

~

Performance Curves: VPDV10 (See Section 7)

~VD
ABSOLUTE MAXIMUM RATINGS (T A

= 25°C unless otherwise

noted)

SYMBOL

VQ2006J

VQ2006P

Drain-Source Voltage

Vos

-90

-90

Gate-Source Voltage

VGS

±30

±20

-0.41

-0.41

-0.23

-0.23

±3

±3

1.3

1.3

0.52

0.52

2

2

0.8

0.8

PARAMETERS/TEST CONDITIONS

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA= 100°C
Pulsed Drain Current 1

10M

TA= 25°C

A

Power Dissipation - Single
TA= 100°C
Po
TA= 25°C

W

Power Dissipation - Quad
TA= 100°C
Operating Junction and Storage Temperature

TJ. T s1g

-55 to 150

lL

300

°C

Lead Temperature
(1/16" from case for 10 seconds)

THERMAL RESISTANCE '
THERMAL RESISTANCE

SYMBOL

Junction-to-Ambient - Single

VQ2006J

VQ2006P

96.2

96.2

62.5

62.5

°C/W

RlhJA
Junction-to-Ambient - Quad
1Pulse width limited by maximum junction temperature
~
6-132

UNITS

VQ2006 SERIES

fCrSiliconix

~ incDrpDratE!d

ELECTRICAL CHARACTERISTICS 1

LIMITS
VQ200S 4

PARAMETER

SYMBOL

TEST CONDITIONS

Typ2

MIN

V(BR)DSS

V GS =OV,I D =-10JJ.A

-110

-90

VGS(th)

VDS = VGS' ID = -1 mA

-3.4

-2

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage

V
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current

IGSS
I DSS

On-State Drain
Current 3

ID(ON)

Drain-Source
On-Resistance3

rDS(ON)

V DS = 0 V
VGS =±30 V
V DS = -90 V
VGS = 0 V

+ 1

+100

I

TJ = 125°C

±5
-0.0005

±500
-10

r

TJ = 125°C

-0.1

-500

V DS = -10 V, VGS = -10 V
VGS = -10 V
ID = -1 A

-4.5

I

TJ = 125°C

-2

-1
5

4.3

8

9FS

V DS = -10 V, ID = -0.5 A

325

Common Source
Output Conductance 3

gos

V DS = -7.5 V, ID = -0.1 A

450

JJ.A
A

2.5

~~~~:~~nductance 3

nA

200

.0.

mS
JJ.S

DYNAMIC
Input Capacitance

Ciss

75

150

40

60

18

25

11

15

30

40

20

30

20

30

V DS = -25 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

erss

VGS = 0 V
f = 1 MHz

pF

SWITCHING
td(ON)
Turn-On Time
tr
td(OFF)
Turn-Off Time

V DD = -25 V, R L = 47.0.
ID = -0.5 A, V GEN = -10 V
RG= 25.0.
(Switching time is essentially
independent of operating
temperature)

tf
NOTES:

1.
2.
3.
4.

ns

T A = 25°C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW =300JJ.s, duty cycle :52%.
Data sheet limits have been revised.

6-133

~SilicDnix

VQ3001 SERIES

~ incorporated

N- and P-Channel Enhancement-Mode MOS
Transistor Arrays

PRODUCT SUMMARY

14-PIN DIP
SIDE BRAZE

PART V(BR)OSS rOS(ON)
(Il)
(V)
NUMBER

10

(A)

TOP VIEW

PACKAGE

Oual-In-Llne Package

VQ3001J

3~/-3~

N= 1
P=2

N = 0.85
P = 0.6

VQ3001P

3~/-3~

N= 1
P=2

N = 0.85
Side Braze
P = 0.6

Plastic

14-PIN PLASTIC

~
.~.:.,;
. ... .. , ...

..

,,;

ABSOLUTE MAXIMUM RATINGS (TA
PARAMETERS/TEST CONDITIONS

SYMBOL

.

= 25°C unless otherwise noted)
VQ3001J
N-Channel P-Channel

VQ3001P
N-Channel P-Channel

Drain-Source Voltage

Vos

30

-30

30

-30

Gate-Source Voltage

VGS

±30

±30

±20

±20

± 0.85

± 0.6

± 0.85

± 0.6

± 0.52

± 0.37

± 0.52

± 0.37

±3

±2

±3

±2

UNITS

V

TA= 25°C
Continuous Drain Current

10

TA = 100°C
Pulsed Drain Current 1

10M

TA= 25°C

1.3

1.3

0.52

0.52

2

2

0.8

0.8

A

Power Dissipation - Single
TA = 100°C
Po

TA= 25°C

W

Power Dissipation - Quad
T A = 100°C
Operating Junction and
Storage Tem~erature
Lead Temperature
(1/16" from case for 10 seconds)

TJ. Tstg

-55 to 150

h

300

°C

THERMAL RESISTANCE
THERMAL RESISTANCE

SYMBOL

Junction-to-Ambient - Single

VQ3001J

VQ3001P

96.2

96.2

62.5

62.5

°C/W

RthJA
Junction-to-Ambient - Quad
1Pulse width limited by maximum junction temperature
6-134

UNITS

VQ3001 SERIES

.-:r-Siliconix

~ incorporated

ELECTRICAL CHARACTERISTICS 1

LIMITS
N-Channel

PARAMETER

SYMBOL

TEST CONDITIONS5

TYp2

MIN

V(BR)OSS

Vas = 0 V, 10 = 10 mA

55

30

VaS(th)

Vos = Vas, 10 = 1 mA

2

0.8

P-Channel

TYp2

MIN

-55

-30

2.5

-3.5

-2

+ 0.1

+ 100

+ 0.1

± 100

±5

+ 500

±5

+ 500

0.005

10

-0.005

-10

0.5

500

-0.5

-500

MAX

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage
Drain Current
On-State Drain
Current 3
Drain-Source
On-Reslstance 3

~~~:~~nductance 3

V

lass

loss
10(ON)
rOS(ON)

gFS

Vos = 0 V
V as =±16V

I TJ

= 125°C

Vos = 24 V
Vas = 0 V

I TJ

= 125°C

Vos = 10 V, Vas = 12 V
Vas = 12 V
10 = 1 A

ITJ = 125°C

Vos=10V,10=0.5A

3

-2

2

-4.5

-1.5

1

1.8

2

1.4

1.75

3.1

3.5

250

280

JJ.A
A

0.8

360

nA

200

.0.

mS

DYNAMIC
Input Capacitance

C iss

85

110

130

150

83

110

75

100

20

35

20

60

10

30

18

30

13.5

30

26

30

Vos = 15 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

C rss

Vas = 0 V
f = 1 MHz

pF

SWITCHING 4
Turn-On Time

tON

Turn-Off Time

tOFF

NOTES:

1.
2.
3.
4.
5.

Voo = 15 V, R L = 23.0.
10 = 0.65 A, V aEN = 10 V
Ra = 25.0.

ns

T A = 25 ° C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse Test: Pulse Width S 300 .usec, Duty CycleS 2%.
Switching time Is essentially independent of operating temperature.
Test conditions are at 1-) polarities.

6-135

~Siliconix

VQ7254 SERIES

~ incorporated

N· and P·Channel Enhancement·Mode MOS
Transistor Arrays
, 14·PIN DIP
SIDE BRAZE

PRODUCT SUMMARY
PART
NUMBER

rOS(ON)
01 + 02
V(BR)OSS
or
03 + 04
(V)

TOP VIEW
Dual-ln-L1ne Package

10
(A)

r'o

PACKAGE

VQ7254J

201-20

3!l

2

Plastic

VQ7254P

201-20

3!l

2

Side Braze

ABSOLUTE MAXIMUM RATINGS (TA
PARAMETERS/TEST CONDITIONS

14·PIN PLASTIC

= 25°C unless otherwise

VQ7254J
SYMBOL
N-Channel P-Channel

noted)

V07254P
N-Channel P-Channel

Drain-Source Voltage

VDS

20

-20

20

-20

Gate-Source Voltage

VGS

±30

±30

±20

±20

ID

2

-2

2

-2

IDM

±3

±3

±3

±3

1.75

1.75

1.75

1.75

1.05

1.05

1.05

1.05

UNITS

V

Continuous Drain Current (T A = 25°C)

A
Pulsed Drain Current 1
TA= 25°C
Power Dissipation - Single

PD

TA= BO°C
Operating Junction
Storage Temperature
Lead Temperature
(1/16" from case for 10 seconds)
Thermal Coupling Factor - Single
(K)-Q1-Q4 or Q2-Q3
Thermal Coupling Factor - Single
(~-Q1-Q2-Q3-Q4. Q1-Q30r Q2-Q4

W

TJ

-40 to 100

T stg

-40 to 150

h

300

°C

60
%

50

THERMAL RESISTANCE
THERMAL RESISTANCE

SYMBOL

Junction-to-Ambient - Single

V07254J

V07254P

96.2

96.2

62.5

62.5

°C/W

RthJA
Junction-to-Ambient - Quad
1Pulse width limited by maximum junction temperature
6·136

UNITS

VQ7254 SERIES

fCrSiliconix

.L;II incorporated
ELECTRICAL CHARACTERISTICS 1

LIMITS
VQ7254

PARAMETER

SYMBOL

TEST CONDITIONS'

TYp2

MIN

MAX

UNIT

2.5

2

3

V

2.5

2

3

.0.

STATIC 4
Drain-Source On
Voltage

VDS(ON)

Drain-Source
On-Reslstance 3

rDS(ON)

Vas=ll.4V,ID=lA
(01 + O 2 ) or (Q3 + 04 )

P-Channel

N-Channel
PARAMETER

SYMBOL

TEST CONDITIONS'

TYp2

MIN

TYp2

MIN

V(BR)DSS

Vas=OV,I D =10J.l.A

-40

20

-55

-20

VDS = Vas
ID = 1 mA

1.5

0.8

-3.6

-0.8

1.2

0.65

-3.3

-0.65

MAX

MAX

UNIT

STATIC
Drain-Source
Breakdown Voltage
Gate Threshold
Voltage

VaS(th)

IT

J = 85°C

V

Gate-Body Leakage

lass

VDS = 0 V, Vas =±12 V

±1

±100

±1

±100

nA

Zero-Gate Voltage
Drain Current

IDSS

VDS = 20 V, Vas = 0 V

0.1

500

-0.1

-500

J.l.A

ID(ON)

VDS = 10 V, Vas = 10 V

1.8

gFS

VDS = 10 V, ID = 0.5 A

500

On-State Drain
Current 3

~~~~;~~nductance3

-1.6
200

290

A
200

mS

DYNAMIC
Input Capacitance

Ciss

85

175

130

190

80

95

75

100

18

25

20

60

12

20

20

30

14

20

20

30

VDS = 12 V
Output Capacitance

Coss

Reverse Transfer
Capacitance

erss

Vas = 0 V
f = 1 MHz

pF

SWITCHING 5
Turn-On Time

tON

Turn-Off Time

tOFF

VDD = 17 V, R L = 15.0.
ID = 1 .1 A, V aEN = 10 V
Ra= 25.0.

ns

DYNAMIC
Continuous Source
Current
(Body Diode)
Source Current
(Body Diode)
Diode Forward Voltage
NOTES:

Is

~~~~'ri~ t~~~~~~~f~_~~~~'t'on
rectlfle~D
:!D

ISM
N-Ch:nnel

V SD

s

Vas = 0 V
Tc=25°C

p-c~annel

lis = 1 A

-2

3

-3

A

S

lis = 50 mA

2

0.6

0.75

-0.6

-0.75

1

1.2

-1

-1.2

V

1.
2.
3.
4.

T A = 25°C unless otherwise noted.
For design aid only, not subject to production testing.
Pulse test; PW = 300J.l.s, duty cycle :52%.
rDS(ON) and VDS(ON) limits are not specified for Individual transistors but are measured as the sum
of a n- and p-channel pair.
5. Switching time is essentially independent of operating temperature.
6. Reverse polarity for p-channel devices.

6-137

III

General Information
Cross Reference
Selector Guide
JFETs

DMOS
low Power MOS
Performance Curves _
Package Outlines
Applications
Worldwide Sales Offices and Distributors

.HSiliconix

DMCAIB

incorporated

N·Channel Enhancement·Mode DMOS FET
DESIGNED FOR:
•
•

Ultra-High Speed Switching
High Gain Amplifiers

TYPE

PACKAGE

DEVICE

Single

TO-72

• SD210DE, SD211DE,
SD212DE, SD213DE,
SD214DE, SD215DE

FEATURES
•

< 1 ns Switching tON

•

Ultra-Low Capacitance CG < 3.5 pF
g fs (gain) > 10000 j.lmhos

Quads

SOT-143

• SST211, SST213,
SST215

Dual-In-Line
16-Pin Side
Braze

• SD5000l, SD50011,
SD50021

Dual-In-Line
16-Pin
Plastic

• SD5000N, SD5001 N,
SD5002N

Surface
Mount

Chipl
Wafer

• SD5400CY,
SD5401CY,
SD5402CY
• Available as above
specifications

GEOMETRY DIAGRAMS

DMCB Single
0.004--1

(0.102)1

r---~

o

DMCA Quad

L
I

r---~

..

--~-

0.019

~________~~__~____~("::::'I~I
0.019 -------~.I
~~_ _ _ _ (0.483)

Note: For Switching Circuit
See LPD-10 (Section 9)

0.004
(0.102)

0.004
0.004
(0.102)
(0.102)
0.035 _ _ _ _ _+I
(0.864)

7-1

DMCAIB

~Silicanix

~ incorporated

TYPICAL CHARACTERISTICS
Leakage Current VS. Applied Voltage

Drain Current vs. Gate-Source Voltage
100
101@JoS

!

15

..

10 6 ..."'T"....,~"T"'....,.-T""'...,..-r-"'T"....,......,

~

Vse= 0 V

80

0.5 V

40

A

20

o

~ ~V
I~~ V
~ ~
~~ ;/"10 V

,

5V

10
(rnA)

~

I ~~

1V
60

~~~~
o

10

5

o

10

10

VGs(V)

Common-Source Forward
Transconductance VS. Drain Current

On-Resistance VS.
Gate-Source Voltage
100

60
ros
(.0.)

40
20

o

20

\ \

I- Vos = 15 V

\

80

Ves = 0 V

rl0V
16

.\ r- 5V
Ai\ ~

1V

TA = -55°C~

Vse= 0 V

~

I

r--r--

gfs
(mS)

.....

10= 5 rnA

r--r-- TAt 25(C I

o

10

V'" .... , / ,.

"'"

'/125°C

4 i"'"

~ 25°C

l-

II
II

o

20

--

,/
8

-

I

..,....,

,.

12

r--b.5Y~~
I.!,
~

r--

20

APPLIED VOLTAGE (V)

10

VGs(V)

100

10 (rnA)

Output Characteristics

Output Conductance vs. Drain Current

50

1.0
Ves= 0 V
T A = 25°C

/

Ves = 0 V
f = 1 kHz

40

//

0.8
Vos= 5 V

30
10
(rnA)

~

/"
V ,,-

20

10

o

VGs= 5 V

-

41 V

I. V

3V

II. ~

2V

~

0.2

~~

~

~ "/

//V

J ~Z
~V

"

Vos= 15 V

::;. " .
0
10
Vos(V)

7-2

Vos= 10 V
0.4

7'

o

I

0.6
gas
(mS)

~ ~/

20

o

10
10 (rnA)

20

g

DMCAIB

Siliconix

incorporatec

TYPICAL CHARACTERISTICS
Threshold Voltage

On-Resistance vs. Temperature
100

1 .1

1

1 .1

1-1 D = 5 mA, VBS = 0

,I

./

60

V
1/"'"

40

V

/

~~

20

I::::::

o

-60

3

a.

~~

VBS = -10 V

VaS(th)

15 V
1 _ f-'C....~

i-"'": I---

4

V
10 V

.- f.-

(V)

::5

2

;::::;;-i"'"
-20

J

~1)-

J--

-0.5V

60

20

1°V;--

o

140

100

-60

-20

60

20

140

100

Leakage Currents vs. Temperature

Threshold Voltage vs. Substrate-Source Voltage
100

5

ID (OFF)@ Vas = VBS = -5 V, VDS = 10 V
IS(OFF) @ VaD = V --5V,Von-l0V

_ Vas = VDS = VTH
ID = 1J.l.A
4 - TA = 25°C

lass@ Vas = 10 V

3
VaS(th)

(V)

~

-

L

-

I

1/ ./
o

las~

ISBO@ VSB = 10 V f- DIODE
f- (
). Is (OFF)
DRAIN OPEN

L

2

o

Temperature

Vas = V DS = V TH
ID = 1J.l.A

I.

Vas=V ~ I--

80

rDS
(n.)

vs.

5

I
(nA)

1/ ;;

I I

10

f= 1= ID(OFF)
f--

",",

/

/'
-10

-20

25

/

'/

7

)SBO

V

17' . /

tx"

/ ./V./V
50

100

125

VBS (V)

Capacitance vs. Gate-Source Voltage

Body Leakage Current vs. Drain-Body Voltage

10 9

10
VDs =10V,f=1MHz
Vas= VBS

ID = 13 mA'S:

/. ?'"

'/

6
C
(pF)
4

r"- I--.

C(GS+SB)
I
I-tC(as+aD+aB)-

~

2

o

t;;;

r:;....

8

.....

-

r--..

C\aD+DB)

~

o

1:=

10

rrT

10 3

h

I/j..

10

~mA

I""':: ....

C Da)

Vas (V)

/)

IB
(pA)

0.1
20

I-- f-

I

o

4

8

12

16

20

V DB (V)

7-3

..

DMCAIB

.:r-Siliconix

.LII incorporated

TYPICAL CHARACTERISTICS

Forward Admittance

Input Admittance

100

100
Vos = 10 V
10 - 10 mA
TA - 25°C

Vos-l0V
ID - 10 mA
TA 25°C

..... ~

10

9,s

10

~biS

mS

mS

... ----

"""9 Is r-

V

./bls

./

./

./

0.1

./

0.1
1K

100

1K

100

FREQUENCY (MHz)

FREQUENCY (MHz)

Reverse Admittance

Output Admittance

100
VOS-l0V
10 - 10 mA
TA 25°C

0.1
mS

----

~s

1/

10

+9rg

mS

I

r-,b..:........ f-" "'"""""

If

-9rg

0.01

Vos 10 V
10 10mA
TA 25°C

~

fo-"i"""

90g

V

0.001

0.1

100

1K

100

1K

FREQUENCY (MHz)

FREQUENCY (MHz)

Switching Characteristics

700
600
500

RL
(.0,)

L

400

/

200

/

100

/

/

~

/
a

2

3

4

5

FALL TIME, t, (ns)

7-4

. . 1/'

L~

300

o

V

V

6

7

DMCD

~Siliconix
..,1;11 incorporatE!d

N-Channel Depletion-Mode MOSFET
DESIGNED FOR:
•
•

High Gain Amplification
Analog Switching

TYPE

PACKAGE

Single

To-72
Chip

DEVICE

• S02100
• Available as above
specification

FEATURES
•

High g fs > 10 mS (Typically)

GEOMETRY DIAGRAM

0.004

(0.102)

--l

r-

..

C)

0.019

:1
( .102)

I·

0.019
(0.483)

·1

7-5

DMCD

~Siliconix

~ incorporated

TYPICAL CHARACTERISTICS (DEPLETION-MODE)
Depletion Mode - Drain Current & On-Resistance
vs. Gate-Source Cutoff Voltage
10

II

....
~

L

ros

I'
losS
(rnA)

10 5
10 4

........ ./

ros@
~ Vas =VGs= 0 V
5 r- 10= 100.lJ.A

...... :---...

j

100 ros
(.0. )

/

L

10 3
10 2

VBS =VGS = 0 V
Vos=15V

10
IGSS@VOB=VSB=OV

I I I I

l'
o

IG
(pA)

1/loss@

loss/

o

Leakage Currents vs. Applied Voltage
200

-2

-1

o

o

10

Drain Current vs. Gate-Source Voltage
10

Drain Current vs. Drain-Source Voltage
10

\

VGS(OFF) = -1.5 V
VBS = 0 V

Vos = 15 V _
VBS = 0 V
8

\.

VGs = 0 V

\.MAX
10
(rnA)

20

(V)

VGS(OFF) (V)

\.

5

6

V

10
(rnA)

~

10.21V

Iv

4

10.41V

',MIN

o

~0.6Iv

"

'-

~

-,.......

o

-1

I

2

-- ---

0.8 V
1.0 V

I

0

-2

0

2.5

V GS (V)

Output Characteristics (V GS (OFF) = -1 .5 V)

Equivalent Input Noise Voltage vs. Frequency
200

V GS = 0 V

1

I_

VSB=OV -

I-en
(nV/v.:iZ) 100

2V ( - - ' - -

I

"

~/

o

~V
15 V

5

i'\
r-....

I--- ' - -

16v I---

Vos (V)

7-6

VOS = 10 V
VGS=VBS = 0 V

/

5

o

5

Vos (V)

10

10
(rnA)

( - - I--

10

o

0.001

0.01

0.1
f (kHz)

10

DMCD

dfY"Siliconix

~ incorporated

TYPICAL CHARACTERISTICS (ENHANCEMENT-MODE)
Common-Source Forward
Transconductance vs. Drain Current

Drain-Source On-Resistance
vs. Gate-Source Voltage
20

100
10 = 5 mA

VGS(OFF) = -1.5 V
VOS= 10 V
V SB = 0 V
f = 1 kHz

80
i-VSB=OV

60

l\i

ros
(.0. )

~,

40

O.~ V

K

,,'-'

gts
(mS) 10

.!.

/~

10V

o

0
10

0

20

",. 1--1

V",.

d

r

11

125°C

'"

'-'

... ~~

"'~~~==-

20

,

'-'

V

1V
5V

~ ~~

15510

I25°C
II

'/

o

20

V GS (V)

On-Resistance vs. Temperature

Leakage Current vs. Temperature
100

100

V BS = 0 V
10=5mA-

10(oFF) @VGs

80

ISBO @V SB

........ 1--

-

i--

'/
V GS = 5 'f/
"'

40

'/
",.

20

V

:::;::::::.

o

-60

~
~

-20

-

10 V

IL

(nA)

60

I I I
10(OFF)

\

---

100

V

/

-V- '7r- P" '-

140

25

50

I

V BS = 0 V

I

ILk:

r- ,....,

C (GS + SB)

4

j

t--...

I I

C (GS + GO + GB)-

"r--,

,./ ::::::

C (GO + OB)
COG

o

I

101=11~

8 r f = 1 MHz

o

125

Body-Channel Leakage Current vs.
Drain-Source Voltage

VOS = 10 V

2

-,-

~GSS

100

f- VGS=VBS

......

I SBO....-

",.

10

6

-'

. / I~

Capacitance vs. Gate-Source Voltage

C
(pF)

-_

DRAIN OPEN

10

-20

= 10 V

Vos

IS(,,...I.-

p.~~ I-

~ t:::-

t::;:: :::::: ~V

=VBS = -5 V,

IGSs@VGS= 10 V

V

60

= 10 V
= 10 V

IS(OFF) @VGo = V BO = -5 V, Vso

r-

10

0.1
20

o

II

-

4

//1 1
1110=1 mA
'/

Vj

8

12

16

20

V GS (V)

7-7

W'rSiliconix
..z:.
incorporated

DMCD
TYPICAL CHARACTERISTICS (ENHANCEMENT-MODE)

Input Admittance
100
TA = 2SOC

=

=:

=

i--"

==b,

--

=T

Ves = 10 V
le=10mA
COMMON SOURCE -

10
mS

Forward Admittance
100

.... :.-

A

=2SoC

mS

s

~

b,y

,/
/

/'

./

0.1
100

1K

1K

f (MHz)

f (MHz)

Output Admittance

Reverse Admittance
100
T

TA - 2SOC

-_ b r .
0.1
mS

..............-

.......

= 2SOC

I/g rg

F

Ves = 10 V

10
mS

I-b~

I

....... ....-

r:==gog

0.001
100

0.1
100

1K

f (MHz)

Switching Characteristics
1000
_

.I.
I
.'.
Vee =
10V
RG= SO.n

V
V"
.....
.....
I;"'"

V
o I'
o 1

2

3

4

S

t, (ns)

6

7

-

~

io-"

1K

f (MHz)

7-8

=

- - Ie = 10 mA

COMMON SOURCE

COMMON SOURCE

-grg

0.01

A

1/

====
- 10 V
==== Ves
Ie 10 mA
-

Ves=10V
le=10mA
COMMON SOURCE

gt.

10

-g~

0.1
100

=

8

9

10

MRA

~Siliconix

~ incorporated

P-Channel Enhancement-Mode MOSFET
DESIGNED FOR:
•
•
•

Analog and Digital Switching
General Purpose Amplifiers
Smoke Detectors

TYPE

PACKAGE

Single

TO-18

• MFE823

TO-72

• 3N163, 3N164

Chipl
Wafer

• Available as above
specifications

FEATURES
•

•
•

High Gate Transient Voltage Breakdown
Eliminates need for Gate Protective
Diode
Ultra-High Input Imedance
Normally Off

DEVICE

GEOMETRY DIAGRAM

B

G

I

T
I

-

0,022

l l
5

I.

"

D

-+ 0,003 I+0,016 {,_O_'o_7..:.6) _ _--11

(.451)

•

7-9

.HSiliconix
incorporated

MRA
TYPICAL CHARACTERISTICS
Output Characteristics
-50

v

.,.~ I-"-"

/
./

-30

il.

ID
(mA)

.,.. .,......
..-

'(lj

-20

o

~

./

I--"'

--

£ V I-"""

-14 V
-12 V

-30

-20

-20

-30

-40

o

-50

,

v.~~
-6V~

-7

-.,..

~~

V ~

~~

-15 V
0V
r-f=lkHz

~ k':rv

V-5V

25°C

k:::j:::ft
TA - 125°C

gfs

LuS)

I::::~

Ves = 0 V

0.2

0

-0.2

10
-0.01

-0.4

-0.1

V DS (V)

-1.0

-10

10 (mA)

Common-Source Output Conductance
vs Drain Voltage

Common-Source Output Conductance
vs Drain Current
1000

10 K

1= Vos

15 V
OV
r-f=lkHz

Ves - 0 V::
f = 1 kHz -

\

1= Ves

\

1K

......

..........

\

1--

gas
()1S)

10(ON) = -10 mA
I

r-::.:::L

-5

-10

I'
10

I O(ON)- lmA=

I
o

I'

100

gas
()1S)

-15
VOS (V)

7-10

TA

1K

1'/
0.4

f:: V DS -

1= Ves

100

./ th W
... ~V

1000

10

-20

Common-Source Forward Transconductance
vs Drain Current

-400

100

-16

Low-Level Output Characteristics

-600

800

-12

VGS (V)

-800

600

lL

V DS (V)

10 K

400

~ I/'
-4
-8

o

VGS = -10 ".,
/
-9 v.~
-8 V
~ V'....

200

V

-6V--:

I

IL

V

-10

8 V -:

-10

0

/

10
(mA)

-lb V

~V

-200

L
1

.-1! V

y.,..""
o

.l

,I

~ VOs=VGS
-40 c- Ves = 0 v.

-lh

~

V

-1000

ID
(J,LA)

I

V S - -20 V

S= 0 V

-40

-10

Transfer Characteristics
-50

-20

-25

-30

1.0

-0.1

-1.0

-10
10 (mA)

-100

MRA

W'rSiliconix

~ incorporated

TYPICAL CHARACTERISTICS
Drain Source On-Resistance vs.
Gate-Source Voltage

Low-Level ON Drain-Source
Voltage vs. Gate-Source Voltage
2.5

100 K

I

ID - 100.uA
Ves - 0 V

~D
2.0

I
I
I
I D = 10 mA---

1.5

\...

V DS
IV)

rDS(ON)

\'

\r\.

1K

1.0
TA - 125°C=

I D =1.0mA

0.5

"'

TA=2~
100

.j

o

I

o

-20

~

:-.....

' ....

I

o

I

-10

-20

VGS IV)

VGS (V)

Capacitance vs. Gate-Source
Voltage

Drain-Source Leakage Current vs.
Temperature

J

J

Ciss

V
1.5

I

-10

3.0

C
IpF)

I

~

10 K

(.0. )

I

I' 0·1 m~

.,,'"

f-- V

--

-

100

10

I

I

I

I

Coss

Is OFF)

V DS = -15 V
Ves = 0 V
f = 1 MHz

C rss

/.V

I D(OFF)
I SCOFF)
InA)

_.......

~r

1.0

I D(OFF)

I

IV

0.1

I
o

o

-4

-12
VGS IV)

-16

-20

I

~

0.01
-8

10

30

50

70

90

110

I I
130

150

TA (OC)

..
7-11

NBB

ICrSilicanix

~ incorporated

N·Channel JFET Circuit
DESIGNED FOR:
•
•

Pre-Amplifiers
Infrared Detectors

TVDC
I
I ....

DI\,...VI\r>C
• __ .'r"\W"

Single

SOT-143

FEATURES
•
•

TO-72

Low Leakage < 2 pA Typically
Low Noise < 10 nV/VHZ, at 10 Hz

GEOMETRY DIAGRAM

....--,!""I.

~g::~J

,-. . . .,11
~.>-----

0.019 - - - -....1

(0.483)

Gate Is backside contact

7-12

I

_ ... v v ..

• SST6908. SST6909.
SST6910
• 2N6908. 2N6909.
2N6910

NBB

tcrSiliconix

~ incorporated

TYPICAL CHARACTERISTICS
Drain Current & Transconductance
vs. Gate-Source Cutoff Voltage

Operatln9 Gate Current

5

2.5
gls

4

V
V

3

II

loss

1.5
gls
(mS)

V

I

2

2

V

/

1/

IDSS
(mA)

I-

V

/

10

./

o

0.5

gls@Vos = 10 V, VGs= 0 V
f = 1 kHz
loss @ Vos = 10 V, V GS = 0 V

V
o

IG
(pA)

-1

-3

-2

-4

-5

o

VGS(OFF) (V)

VOG (V)

Common-Source Forward
Transconductance VS. Drain Current

On-Resistance & Output Conductance
vs. Gate-Source Cutoff Voltage
40

2

J

I

~

ro

/

//

...... :"-i---....

._

ros@ 10= 100).LA, V GS = 0 V
gas @Vos = 10 V, VGs= 0 V f = 1 kHz

./

-2

-1

~

gls
(mS)
1.0

'" ./
/

o

90S
20 (.U.s)

-4

-3

-5

0.5

o

o

~~

J5'-6 1

/
I

1.5

,

o

2.0

VGS(OFF)= -2 V
VOG= 15 V
f = 1 kHz

go;

1\

rOS
(1<.0. )

2.5

f

d
-I

25 0

125 0 C

I

~

~
0.1

VGS(OFF) (V)

10
10 (mA)

Equivalent Input NOise Voltage vs. Frequency
50

..

Output Conductance vs. Drain Current
40

Vos=10V

VGS(OFF)= -2 V
V oG =15V
f = 1 kHz

40

/
30
en
(nVI -.1HZ)
20

~

1/

90S
(.lJ.S ) 20

10= 0.1 mA

I

1/
f:::::~

10
V GS

o

0.01

OV

1111111
0.1

10
f (kHz)

100

o

0.1

10
10 (mA)

7-13

tcrSiliconix

NBB

~ incorporated

TYPICAL CHARACTERISTICS

Output Characteristics ( Vas (OFF) = -2 V)

Output Characteristics ( Vas (OFF) = -1 V)
2.5

1

)

VG =OV

I

/
10
(mA)

2.0

-0.2 V
0.5

I

I

/

10
(mA)

,

(

<

1.0

10.4IV

~0.6Iv

I
-c.~v- i--

V-

.. "

•

If

1

I

-O.B V

V'

0.5

_1. 12 v l - I--1.6 V '--- I--

-O.B V

o

0

o

20

10

o

10

Vos (V)

JOS=1 15

Transfer Characteristics (VaS(OFF) = -2 V)
4

~-

Vos = 15 V_

'-WC

\.

'\ \

10
(mA)

0.5

~~

"'"

25°C

o

10
(mA)

~

125°C ~

"'-

~ ~55"C
2

'\

~ ~........

~

o

~
~

" -- <,

.... 25°C

.......

... ~

~

125°C

~~

-0.5

o

-1

i"""'-O ~ =::....

o

Transconductance vs. Gate-Source Voltage
Vas (OFF) = -1 V
Vos= 15 V
f = 1 kHz

-

-

,

"'WC
25°C

-

1.5

"""-"

Qt.
(mS)

~

1.0

~
~~

o

-0.5
Vas (V)

7-14

0
-1

o

-

~25°C

I......... ~

""-

0.5

Vas (OFF) = -2 V
Vos=15V
f = 1 kHz

"

"""t:

125°C-

~~

o

~1-551c

2.0

I

........

-2

Transconductance vs. Gate-Source Voltage
2.5

r-j$ ~

-

Vas (V)

2

~~

i"""oo

-1

Vas (V)

Qt.
(mS)

20

Vos (V)

Transfer Characteristics (Vas (OFF) = -1 V)

\

s=lo V '--- I--

r-..... ........ ~
r-o
-1
Vas (V)

'"

""II1II ~

~

~
-2

NBB

.:rSiliconix

~ incorporated

TYPICAL CHARACTERISTICS

Input Current vs. Input Voltage

10

Signal Distortion vs. Signal Voltage

10

I

II
II

f = 1 kHz

f - 1 kHz

/

V

%
Signal
Distortion

~

o

"

,/
0.1

-10
-1

o

0.2

0.4

± PEAK
Common-Source Input Capacitance
vs. Gate-Source Voltage

Common-Source Reverse Feedback
Capacitance vs. Gate-Source Voltage

10

10
f

Ciss

IpF)

5

\

~

Vos

f

= 1 MHz

5

=0 V

Vos

o

=1 MHz

C rss
IpF)

........ r-..,"""Ioo.
o

0.8

0.6

SIGNAL VOLTAGE IV)

'"

.....

= 10 V
-10
Vas IV)

-20

o

o

Vos

=0 V

Vos

= 10 V
-10

-20

Vas IV)

•
7-15

NCB

.rY"Siliconix

~ incorporated

N·Channel JFET
DESIGNED FOR:
TYPE

e

Ana!og SV'/itches

•
•
•
•

Commutators
Choppers
Voltage Controlled Resistors
Integrator Reset 8witch

8ingle

I

PACKAGE

• 2N5638, 2N5639,
2N5640
J111, J12, J113
J111A, J112A,
J113A
PN4091, PN4092,
PN4093
PN4391, PN4392,
PN4393
U1897, U1898,
U1899

80T-23

• 88T111, 88T112,
88T113
88T4091, 88T4092,
88T4093
88T4391, 88T4392,
88T4393
88T4856, 88T4857,
88T4858, 88T4859,
88T4860, 88T4861

TO-18

• 2N4091, 2N4092,
2N4093
2N4391, 2N4392,
2N4393
2N4856, 2N4857,
2N4858, 2N4859,
2N4860, 2N4861
2N4856A, 2N4857A,
2N4858A, 2N4859A,
2N4860A, 2N4861A
VCR2N

Dual

TO-71

• 2N5564, 2N5565,
2N5566

8ingle

Chip

• All of the above
specifications are
available

Dual

Chip

• 2N5566 specification
available

High 8peed tON < 20 ns
High Off-Isolation ID(OFF) < 100 pA
No Offset or Error Voltages Generated
by Closed 8witch. Purely Resistive.
High Isolation Resistance from Driver

GEOMETRY DIAGRAM

...J

0.004 ' -

·1 (0.102) I·

T

~(~

u'

0.021

Ti:W.

.0085

(0.089)

...L .

·0: ,

.., .. .

f~
.
.-.~

1(0.533)

~[b
I

0.021
(0.533)----+1>
Gate also backside contact

7-16

DEVICE

TO-92

FEATURES
•
•
•

I

~SilicDnix

NCB

~ incorporated

SWITCHING CIRCUITS

OUT

2N4091 through 2N4093
2N4856 through 2N4861

2N4391 through 2N4393

IfI

7-17

~Siliconix

NCB

~ incorporated

TYPICAL CHARACTERISTICS
On-Resistance & Drain Current
vs. Gate-Source Cutoff Voltage

rOS
(.0.)

On-Resistance

'"l~111111
nr
,
"

o

.... V

./

J

........
1

10

50

~
I

g,.

100

10 (rnA)

Forward Transconductance & Output
Conductance vs. Gate-Source Cutoff Voltage

"..

T A = 25°C

I I I II

a

-10

-5

,,'

VGS(OFF) = -8 V

o

VGS(OFF) (V)

On-Resistance vs. Temperature
200

500

-10= 1 rnA
ros changes - 0.7%/OC

--:?""

-

./ /"gos

g,s

",.

I

rOS@ 10 = 1 rnA, V GS = 0
loss@ VOS = 20 V. V GS = 0

o

./

VGS(OFF) = -4 V

/1'
........

/

'/

ros
(.0.) 50

/

~

I
I

VGS(OFF) = -2 V

I

loss
100 (rnA)

./

50

-

Drain Current

VS •.

100

V :/

V :/

25

250

/ 1/

(mS)

90S

(.lIS)

VGS(OFFI~ ~

ros 100
(.0.)

'/

b

IT

o

a

g,s & gos@
VOS = 20 V. VGS=
f = 1 kHz

-5

..,.

..,.V

- I--

".."

a _ I-o

o

i"""
-55

-10

-15

i--"

""

~~
.1.
VGS(OFF) -

85

25

_

8V
125

TA (OC)

VGS(OFF) (V)

Operating Gate Current

Output Characteristics (VGS(OFF)= -4 V)
100

V GS = 0 V
10 5
(rnA) a

a

I/. V'

-1.0

&- i""
~ / ....

-1.5
2.0
2.5

o II~
15
VOG (V)

7-18

-0.5

V

30

o

5
VOS (V)

10

.HSiliconix

NCB

incorporated

TYPICAL CHARACTERISTICS

Transfer Characteristics

Output Characteristics (VGS(OFF) = -2 V)

40

20

V~S=120 ~

\

~ \A=-55

VGS=~

ID
(mA)

vP

10

,,/
. / .............. ...........
-....,.....

~~

~~~-

o

.--

~r;:::;;;.-

o

...... V

-

.--I--"

.t!

ID
(mA)

20

~
1.0

C

25°C\

"-

I\,

o
1.0

~

~

125°C-

-

1.2

0.5

0

" "'-'" '"r---:"

0.8

I
o

Transfer Characteristics

Output Characteristics (VGS(OFF) = -4 V)
100

k'y

Vv :1!

./

v:V

-

~

?- t:::-- ~ ~ ~

r-~ ~ ~ ~I o

ID
(mA)

0.5

50

r-....

...-

........ t--....

-2~

'\
i'... I'\.

-2.5

-

o

1.0

+

VGS(OFF) = -4 V

~oC ~

-1.5

3.0

o ~~

V~S=120J

\
\,
- KA = -55°C

VGS=O~
20

-2.0

V GS (V)

40

ID

~ :::::"...

-1.0

V DS (V)

(mA)

+

VGS(OFF) = -2 V

- -

125°C

I

o

r--... r\..
~ c--.:: ~

~

-2.5

V DS (V)

-5.0

V GS (V)

Output Characteristics (VGS(OFF) = -8 V)

Transfer Characteristics

400

+

V~S=120 J

VGS(OFF) = -8 V

ID

(mA)

25

1-+-/-+-t-+-7f,--:;~+:;;o

ID

(rnA)

200

~

TA = -55°C

""-

25°~

~

~,......,." .........
125°C

o

o

o
0.5
V DS (V)

1.0

o

"-r-....
-5

-10

V GS (V)

7-19

.HSiliconix
incorporated

NCB
TYPICAL CHARACTERISTICS

Turn-Off Switching

Turn-On Switching

5

30

tr approx. Independent of 10
t

4

3

r

I

(ns)

2

t d (OFF) independent of
device Vas (OFF)
Vas = -2 V _ Voo = 5 V
VIN = -10 V
I
I

16

r-

V astt@
=-6V' "

Ti'--...

t

(ns)

td(OFF

12

10=12mA

/~ t-.....

......

/

td(ON) @
10 = 3 mA

I

24

Itd(ON)I @I

\\
I" '\.

t

I tt ~ I-

I-

I
I
I
Voo = 5 V
Ra= 50 .n.
VIN = -10 V
I

6

...... r-..,

I

:-.....

r".

"

-10

-5

0

f"'..

......... ......

r--.....

........

r---.... r5

0

......

-

10

10 (mA)

Vas (OFF) (V)

Transconductance vs. Drain Current

Capacitance vs. Gate-Source Voltage
100

30
f = 1 MHz

Vas (OFF) -2 V
Voa 10 V
f = 1 kHz

24

\

C
(pF)

I

\

gt.
(mS)

r\.

12

I'..
6

!'-.....

i'....

0

0

16

.......

.......

i'...

10

125°C

Ciss@ Vos = 0 V_
.1
II
I

I""--..........

r-.

/:

~~

C rss @ Vos = 0 V

~

1

o

-10

TA = -55°C

~5OC\. ~e::::tH

-20

""

0.1

1.0

10

10 (mA)

Vas (V)

Output Conductance vs. Drain Current

Noise Voltage vs. Frequency
100

1000

=
-

:=

~

Vas (OFF) -2 V
Voa 10 V
f = 1 kHz

II--

Voa=10V
ew = 6 Hz @ f = 10 Hz, 100 Hz
= 0.2 f @ f 2: 1 kHz

II 111111

I-

TA = -55°C
gos
().lS)

en
(nV I '11Hz' )

100
25°C . /
..If'
/\;0' . /
12tii
.........

10

I

11 \I~~

10

= 10 mA

;'

10
0.1

II

-:::~
1.0
10 (mA)

7-20

......
I.......

/

r--.
10

0.01

0.1

10
f (kHz)

100

.rSiliconix
.z.
incorporated

NCB

TYPICAL CHARACTERISTICS

Common-Gate Input Admittance

Common-Gate Forward Admittance

100

100

--

I-glg

10
(mS)

--gIg

b 1_-

..:.a.--

10

-

(mS)

lI-- big
VDG = 10 V ~
ID =10 mA
TA = 25°C

~

\

VDG = 10 V
ID = 10 mA
TA =25°C

gIg

I

0.1

0.1
100

200

500

100

1000

FREQUENCY (MHz)

200

500

Common-Gate Reverse Admittance

Common-Gate Output Admittance

100

10
VDG 10 V
ID - 10 mA
TA 25°C

VDG 10 V
ID 10mA
TA - 25°C
-br~

1.0

/'

/

bog

10

+grg=
(mS)

1000

FREQUENCY (MHz)

-g;;-"

0.1

..,..

(mS)

I-.

......

I

V

0.01

--gog

0.1
100

200

500

FREQUENCY (MHz)

1000

100

200

500

1000

FREQUENCY (MHz)

..
7-21

~Siliconix

NCL

~ incorporated

N·Channel JFET Current Regulator Diode
DESIGNED FOR:
•
•
•

Current Reguiation
Current Limiting
Biasing

. -_.,,..,,...:;-

TVDC
•
11_

"'",.. ..... "n.c

Single

TO-92

FEATURES
•
•
•
•

Simple Two Lead Current Source
1 to 100 V Operation
0 Temperature Coefficient
Simplifies Floating Current Sources
No power supplies required

Chip

GEOMETRY DIAGRAM

T
0.023

~_------,.I

I. .I-----(g:g~~) ----~.I
0.004

(.102)

Gate is backside contact

7-22

I

__VI __

nC\lII"C

• J501.
J505.
J50B.
J511
J553.
J556.

J502. J503.
J506. J507.
J509. J510.
J554. J555.
J557

• Available as above
specifications

NCL

~Siliconix
..r;;;JI incorporated
TYPICAL CHARACTERISTICS

Output Current vs. Forward Voltage

Output Current vs. Forward Voltage

5

5

I

I

I

J5\0

J510

I

",.
IF
(mA)

)f'
2.5

o

J08

'/

/

I

IF
(mA)

./

I

fo""'

I

'/

J505

h~

J!02

o

J5~8

2.5

2

J505
J500

o

4

3

5

o

50

V F (V)

IF
(mA)

r-....

V F = 25 V
Steady State

VF

J510

"-

~ --... r--....
........

--... r- rI--

~

I"- _J508

2.5

Knee Impedance vs. Regulator Current
10

"- .........
......

100

V F (V)

Limiting Current vs. Temperature

5

J500

J502

~

~

J505

-

6V

....

t--

r-

-

"-

"

0.1

J562

o

0.01

-55 -35 -15

5

25

45

65

85 105 125

0.1

10

TJ (OC)

Limiting Voltage @ 0.8 IF
vs. Regulator Current

Dynamic Impedance vs. Regulator Current
100

10

VF - 25 V::

""

10

'"

VF

,

./

-

25 V

V~

..;

0.1

0.1
0.1

10

0.1

10

7-23

~Si6cDnix

NCL

~ incorporated

TYPICAL CHARACTERISTICS

On-Resistance vs. Regulator Current

Temperature Coefficient vs. Regulator Current

0.5
V F = 25 V

To
(%/oC)

~
0

~

rOS(ON)

(k.n)

I'

\.

~

f-

TJ: ~5 to 125:cJ2 :::;:: too..

1- f5 Itol ~51

~I

r-o

I I "I

-0.5

~

o

0.1

10

o

......... ......

-

2.5
IF (mA)

Capacitance vs. Forward Voltage

10

CT
(pF)

5

;= lIMH~_

,

1\

"
o

o

10

......
20

30

VF IV)

7-24

40

50

5

NH

.:r-Siliconix

~ incorporated

N·Channel JFET
DESIGNED FOR:
•
•
•
•

VHF/UFF Amplifiers
Oscillators
Mixers
Low Input Capacitance High Speed Switch

TYPE

PACKAGE

Single

TO-92

FEATURES
•
•

Low Noise
nF = 3 dB Typical at 400 MHz
Wideband High 9fs/CIss Ratio

SOT-23

DEVICE

• 2N3819
2N5484. 2N5485.
2N5486
BF244A. BF244B.
BF244C
BF245A. BF245B.
BF245C
J304. J305
PN4416
• SST4416

TO-72

• 2N4416. 2N4416A

Chip

• Available as above
specifications

GEOMETRY DIAGRAM

T
Gate also backside contact

7-25

.-rSiliconix

NH

~ incorporated

TYPICAL CHARACTERISTICS
Drain Current & Transconductance
vs. Gate-Source Cutoff Voltage

Leakage Current vs. Drain Voltage
10

20
loss

V

'"

-

/

~~

lOSS
(mA)

"V

gfs

10

1,

gts
(mS)

IG
(pAl

1/

/

gfS@ Vos = 10 V, VGS = 0 V
f = 1 kHz
IfSS~ Vps =1 10 '1" V1S = V

1/

,
o

5

V I

f

o

-5

-10

o

VGS(OFF) (V)

VOG (V)

On-Resistance & Output Conductance
vs. Gate-Source Cutoff Voltage

Common-Source Forward
Transconductance vs. Drain Current

500

50

10

r- VOG =10V

rOS@ 10= 1 mA, VGS = 0 V
gas @ VOS = 10 V,vGS = 0 V
f = 1 kHz

.1

f - ro

\
\

f = 1 kHz

r- VGS(OFF) = -3 V
TA = -55°C

Vgos

/

V

gas
25 (.I1S)

gts
(mS)

25°~

5

!/ ~

V
"/ I ' ......

0

V
a

o

a

-5

-10

--

....... "

o~
0.1

~

..

10

VGS(OFF) (V)

10 (mA)

Equivalent Input Noise Voltage vs. Frequency
20

Output Conductance

VS.

Drain Current

20
V

= 10 V

VGS(OFF) = -3 V

I- VOG =10V
f = 1 kHz

l\

..... i" ....

\

\
gas 10
(.I1S)

en 10
(nV/VHz')

'roo.
i'.
r- Vos = 10 V,

o 11111111
0.1
0.01

r--

~~

TA = -55°C
1
25°C

1-44

r---/~

/. ~

10 = 5 mA

125°C

lM'

N
i-J..

V

VGS = 0 V
111111111 I

10
f (kHz)

7-26

~ ........125°C

100

o

0.1

10
10 (mA)

NH

.-:rSiliconix

.LII

incorporated

TYPICAL CHARACTERISTICS

Output Characteristics (VaS(OFF) = -2 V)

Output Characteristics (VaS(OFF) =-2 V)

5

~~-T~~~-r~--T-~~~

10

~+-~-+~--~+--IVal=Olv
.J.,...-'

I I
I I

4.2V

~v

1/

10
(mA)

~

///

o

~

-

-0.2 v l 0.4V I-

0~6 v l -0.8 V ' 1.0V=
1.2 V
- .4 V

rl~

~::::""I--"

-1.2 v
-1.4 V

,.-

o

o

.".

5

"'-asl = 0 IV

0.5

~.....
o

5

VOS (V)

10

Vos (V)

Output Characteristics (Vas (OFF) = -3 V)

Output Characteristics (Vas (OFF) = -3 V)
15

Vas = 0 V

o.~ V
10
(mA)

2.5 I-~__+--+~~~~~~~~~

/

10
(mA) 7.5

-0.6 V

1//

-0.9 V

~

-1.2 V

~

o

o

o

0.5
Vos (V)

Transfer Characteristics
10

.I.

.1 1 I
-VaS(OFF) = -2 V -

T

5

-

I

V~S = \ 0 ) -

5

10

Vos (V)

VS.

Gate-Source Voltage

Jos~10~

.1 I I .1.
!-VaS(OFF) = -2 V

II

~.....

gf.
(mS)

" ...

I

f = 1 kHz

I

5

~5ocl

----~r---. ,
-l:' ~

125°C

~~

.........

I~

""Il

o

o

i-- T A = -55°C

i'...

o

10

25°C

12~ ~
~

"
Transconductance

~t:

-.....:
10
(mA)

--I

-1.5 V
- .8 V

-1
Vas (V)

~~

I~ ~

~~
-2

o

~~

o

-1

-2

Vas (V)

7-27

H

NH

Siliconix

incorporated

TYPICAL CHARACTERISTICS

Transconductance vs. Gate-Source Voltage

Transfer Characteristics
10

10

i\. i\. TA = -55°C
'\ \
y125O~
I'\.

"

.1
II.!
-Vis (Or) = 3 V

Vas (OFF) = -3 V
Vos = 10 V

-T~ = ~ssob

['.., \.

10
(mA)

"\
i\.."- ~

125°C' ....

5

~

o

o

gfs

(mS)

~

~'..,J 25°C
-.c..: l'-

5

~

.........

......

~

~~

o

-3

-1.5

" "i'...
......... l'

" ~ ~~

o

-1.5

'"

Vas (V)

Vas (V)

On-Resistance vs. Drain Current

Circuit Voltage Gain vs. Drain Current

300

_

Vos = 10 V
f = 1 kHz

1-

TAI=

2~ob

II

-3

AV=~

1

J

Vas (OFF) = -2 V ...",
ros
(.0.)

II III

150

Vas (OFF) =

-3

V

-

J

5V

~
".

Av

o

50

OL-~~~~~--~~~~~

0.1

10

0.1

10

10(mA)

10(mA)

Common-Source Input Capacitance
vs. Gate-Source Voltage

Common-Source Reverse Feedback
Capacitance VB. Gate-Source Voltage

5

3
t'= 1IMHZ:_

t'=

r-

1IMH~_

\VOS = 0 V
Clss

(pF)

\

2.5

~

C rss
(pF)

"-

1.5

\

'\

~

Vols =

a

o

-10
Vas (V)

7-28

...............

Vos = 0 V

r

1° V I -20

iosi 1

a

o

-10
Vas (V)

-20

NH

.-r-Siliconix

~ incorporated

TYPICAL CHARACTERISTICS

Forward Admittance

Input Admittance
100

100
V DS

25°C
15 V

V GS -

aV

TA

=
=

:::: T A

b,s

COMMON SOURCE

i---"

10

rf

25°C
15 V

V GS -

aV

-

COMMON SOURCE

10

9,s

9,s

mS

V DS

mS

~

b,s

- ~

/'
."

0.1
100

./

0.1
100

1K

1K

f (MHz)

f (MHz)

Output Admittance

Reverse Admittance
10

10

TA
V DS

25°C
15 V

V GS - 0 V

COMMON SOURC~

-

-- -- -

b,'-p

bes ~;;;i

....-

io-'"

mS

mS
9rslo"'i-'
0.1

. . . . . C'=

0.1

25°C

90

.:1=

I

V DS = 15 V

.--- ,......

VGS=

aV

COMMON SOURCE

0.01
100

0.01
1K
f (MHz)

100

1K
f (MHz)

•
7-29

~Siliconix

NIP

~ incorporated

N·Channel JFET
DESIGNED FOR:
•
•
•
•
•

Low ON Resistance Analog 8witches
Commutators
Choppers
Integrator Reset Capacitors
Low Noise Audio Amplifiers

TYPE

PAI,,;KAI.:iE

8ingle

TO-92

• J108, J109, J110,
J110A

80T-23

• 88T108, 88T109,
88T110

TO-52

• 2N5432, 2N5433,
2N5434

FEATURES
•
•
•
e

Chip

Low Insertion Loss
8mall Error in Measurement 8ystems
VOS(on) < 50 mV (2N5432)
High Off-Isolation IO(OFF) < 200 pA
High 8peed td(on) < 4 ns
Low Noise Audio-Frequency Amplification
en < 2 nV/VHZ at 1 kHz

GEOMETRY DIAGRAM

1
0.030

(0.762)

"'1.-----

----~

0.030
(0.762)
Gate also backside contact

7-30

DEVICE

• Available as above
specifications

~Siliconix

NIP

~ incorporated

TYPICAL CHARACTERISTICS

,

On-Resistance & Drain Current
Gate-Source Cutoff Voltage

On-Resistance VS. Drain Current

VS.

20

50

1000
rDS @ ID= 10 mA, VGS = a IDSS@VDS=5.VGs=0 _

I- TA =25°C

I
\
rDS
(.n. )

rDS

/

10

I'\.

'-..
a --a

I--

VGS(OFF) = -2 V

V

\

..,. "

V

/';DSS

500 I DSS
(mA)

1

rDS
(.n.) 25

-

~

p< r--..

VGS(OFF) = -4 V

VGS(OFF) - -8 VI

a

a

-10

10

VGS(OFF) (V)

200

gfs /

...... :--

V

VGS(OFF)

I

24
90S

/

/

25 (mS)

-

."

-5

. / V'

V

8

V
a

a

-

I-- I--

-55

-10

=;2~

/

rDS

(.n.)

16

./
~

a

32

I

IL
go:;

/

I

vs. Temperature

ID = 10 mA
rDschanges - 0.7%/OC

a

I

a

On-Resistance

40

50

100

100

ID (mA)

Forward Transconductance & Output
Conductance vs. Gate-Source Cutoff Voltage

gfs
(mS)

I

III
-5

gfs&gos@
V DS = 5 V, VGS=
f=lkHZ

/

l......VGS(OFF) = -4 V

........r::r:

,.-

I
VGS(OFF) -

-15

I.8V

85

125

VGS(OFF) (V)

Operating Gate Current

Output Characteristics (VGS(OFF) = -2 V)
100

IG
(pA)

VG~ =

ID
(mA) 50

a

"

lib .....
a 1:::=

10

10
V DG (V)

20

-

L~

V
V

a

aV

-0.2 V
-0.4 V
0.6 V
0.8 V

I
5

I
10

VDS (V)

7-31

•

ICrSiliconix

NIP

~ incorporated

TYPICAL CHARACTERISTICS

Transfer Characteristics

Output Characteristics (VaS(OFF) = -2 V)

40

VGS~
10
(mA)

20

.., ,

V ...... "

~
~

o

~ .-" ~

o

l/'

-

.-"

-o.~

10
(mA)

"llJ·~
IIIIII1
,
50

1\ '\.

,~

......-r:o.d V

~

~

0.25

"

12~~

0.8 V

o

0.5

T

,

25°C

"-

........ .
~

I

i"o.

~

o

-2

-1

VOS (V)

Vas (V)

Transfer Characteristics

Output Characteristics (VaS(OFF)= -4 V)

400

100

VOS = 5 V
VaS ( FF) = -4 V

I-TA = -55°C
Vas=Oy
10
(mA)

50

-0.5 V

./

...... .-:::: ~

V"

10

/
;>

-

(mA)

Y

200

-1.0 V

o

-

0.25

i\..
I'I.......

...- r-:"1.5 V

"

......

....... ~ ....... I'.....

f-~k;:::~"'-~~-~v
o l.-..

I'\.

r-

125°C

o

0.5

L

o

25°C

"

~

-2

Vos (V)

-4

Vas (V)

Transfer Characteristics

Output Characteristics (V as(OFF) = -6 V)
100 r--r---r--r--r---,r--r-.....,..-r-"7r"""'"1

1000
VOS = 5 V
V aS ( FF) = -8 V

, A = -55°f
10

10
(mA)

(mA)

500

'-

~ --\

"-

25°C

I\.

" "
"
~

1250-1'-0.

o

o
VOS (V)

7-32

I

o

.........

t'-....
~

~

-5
Vas (V)

-10

g

NIP

Silicanix

incorporated

TYPICAL CHARACTERISTICS

Turn-Off Switching

Turn-On Switching
30

5
tr approximately Independent of ID
V DD = 1.5 V. RG= 50.0.. VIN = -10 V

4

....

3

~

-

tdlON) @I

= 25 mA

t-- ...... I"--l
1--1-.... ........

t

td( N) @ ID = 10 mA

'\..

i'..

t

(ns)

"r-- I-

12 f--tf @ V GS

-, '1

tr

-5

o

-10

o

5

10

a

gts
(mS)

C rss @ V D!! =

I-TA = -55°C

~~

10

I
V DG = 5 V
f = 1 kHz

",

VGf(OjF)
-20

100

ID (rnA)

Noise Voltage vs. Frequency
V DG 5 V
100~~=BW - 6 Hz @ f
10 Hz. 100 Hz

V DG - 5 V
f = 1 kHz
VGS(OFF) - -4 V

- 0.2 f @ f l!: 1 kHz
1111111 I III

TA = -55°C
2rs.-

gas
(mS)

t I-~ I~ I

10

Output Conductance vs. Drain Current

111111

~

II

en
(nV/IIHz )

125°C

1

Drain Current

./,/,/

;'"

10

0.1

25

~/~5OC

V GS (V)

"/

VS.

aV

-10

?; /'

20

;' ./

........ ~s~ vD,=O,V
"- i--

a

./

15

Transconductance

50 ~

~

r-=-

100

~ 1 ~HZ

l\.
\ i'..

-

........

ID (mA)

C
(pF)

.......

r-'-

Capacitance vs. Gate-Source Voltage

I-f

~

r---...

I-- r- Id(OiF)

VGS(OFF) (V)

100

'-tf@VGs=-2V

I'
= -8 V

"'"",

6

a

'- I\..

\

18

! - r--

a

1\

24

........

(ns)

2

td(OFF) independent of device VGS(OFF)
,VDD = 1.5 V. VIN = -10 V

'"
10
ID (mA)

100

0.01

0.1

1

10

100

f (kHz)

7-33

.:rSiliconix

NIP

~ incorporated

TYPICAL CHARACTERISTICS

Common Gate Forward Admittance

Common Gate Input Admittance

"1'

I II

10

III
bi~=

(mS)

(mS)

'~r "I

~
1 ----

./
0.1

..,./
10

I

1-----1----1--1- VOG - 20 V -

50

100

10

TA

25°C -

10 = 20 mA

50

100

FREQUENCY (MHz)

Common Gate Reverse Admittance

Common Gate Output Admittance

100
TA 25°C
V OG - 20 V
10 20 mA

TA - 25°C
V OG - 20 V
10 20 mA

==

10

g,g

---

(mS)

- -

(mS)

bog~=

~

-=b,g

0.01

.... I--i-'
gog

0.1
10

50
FREQUENCY (MHz)

7-34

I

=

10

0.1

-

big

TA 25°C VOG - 20 V
10 = 20 mA

FREQUENCY (MHz)

1.0

I 1111 I!

100

10

50
FREQUENCY (MHz)

100

.HSiliconix

NKL

incorporated

N-Channel JFET Current Regulator Diode
DESIGNED FOR:
•
e

Current Regulation
Current Limiting

•
•

Baising
Low Voltage References

TYPE

PACKAGE

Single

TO-18

Chip

DEVICE

• CR022 through
CR062
CRR0240 through
CRR0560
• Available as above
specifications

FEATURES
o
III

o
..

Simple Two Leaded Current Source
Current Insensitive to Temperature
Changes
Tempurature Coefficient Better than
0.15 %/° on all Devices
Simplifies Floating Current Sources
No Power Supply Required

GEOMETRY DIAGRAM

Cathode is backside contact

7-35

NKL

fCrSiliconix

~ incorporated

TYPICAL CHARACTERISTICS

Output Current

VS.

Output Current vs. Forward Voltage

Forward Voltage

11111111111
IF
(mA)

0.5

II
V

'"

I

,

J.V'

o

CR062

r

CR043

CR043

CR030

CR030

CR022

CR022

I
I

'I
o

2

3

4

5

o

o

50

V F (V)

Limiting Current vs. Temperature

Knee Impedance vs. Regulator Current

!

I VF
25 ~
Steady State-

CR062
IF
(mA)

100

V F (V)

10
VF- 6 V

-

0.5
CR043
CR030
CR022

0.1

I--

o

0.01

-55 -35 -15

5

25

45

TJ

(OC)

65

85 105 125

0.1

Limiting Voltage @ 0.8 IF
vs. Regulator Current

Dynamic Impedance vs. Regulator Current
100~

10
VF - 25 V ::

VF - 25 V

"

10

0.1

0.1
0.1

7-36

10

10

0.1

10

NKL

.:r-Siliconix

~ incorporated

TYPICAL CHARACTERISTICS

Temperature Coefficient vs. Regulator Current
0.25
V = 25 V

\

On-Resistance vs. Regulator Current

2

F1

1=0.1I F @25V

\

\ \

r\ TJ = -55 to 25°C

1\ N III
i\ r III

o

rDS(ON)

(k.n)

'" ..... ,

1.5

......

T J = 25 to 125°C

~
-0.25
0.1

o

10

0.5

IF (rnA)

IF (rnA)

Capacitance vs. Forward Voltage

Thermal Resistance vs. Power Dissipation

20

1000
f = 1 MHz

C
(pF)

e JA -

(OC/W)

=

- -

eJCI~ (Tc)

10

(T A )

100

\.

"\

RANGE-

...... 1-0...
o

o

I

10
10

20

I

T A = 25°C still air, current regulator
.25 In. above circuit board
T c = 25°C infinite heat sink

........ 1-0..
30
V F (V)

40

50

o

100

200

300

400

500

PD (mW)

•
7-37

W'rSiliconix

NKM

~ incorporated

N·Channel JFET Current Regulator Diode
DESIGNED FOR:
I T

•
•
•
•

Current Regulation
Current Limiting
Baising
Low Voltage References

C

nA,",VA"cl

rM\"oo.,"-.;i ...

Single

TO-1B

Chip

FEATURES
•
•
•
•

Simple Two Leaded Current Source
Current Insensitive to Temperature
Changes
Tempurature Coefficient Better than
0.15 %/oC on all Devices
Simplifies Floating Current Sources
No Power Supply Required

GEOMETRY DIAGRAM

0.0035
(0.0890)

0.030

~--------~~--------~~
Cathode Is backside contact

7-3B

-- ....

~-

• CR06B through
CR150
CRROBOO through
CRR1250
• Available as above
specifications

NKM

.r-Siliconix

~ incorporated

TYPICAL CHARACTERISTICS

Output Current VS. Forward Voltage

Output Current vs. Forward Voltage

2

2

.I CR1'50
/""

CR120

/ / r-

IF
(mAl

bRllo
CR120

"CRO~l

D

IF
(mAl

bROJl

CROBB

11/

CROSB

if/'
/I

o I(
o

o
2

5

4

3

o

50

V F (VI

100

V F (VI

Limiting Current VS. Junction Temperature

Knee Impedance VS. Regulator Current
10

2

SV

VF
CIR150'

-r--

-r-.J.
CR120

C~0911

IF
(mAl

CROBB
0.1

V F = 25 V
Steady State

o

0.01

-55

-15

B5

125

0.1

10
IF (mAl

100

..

Limiting Voltage @
O.B IF VS. Regulator Current

Dynamic Impedance vs. Regulator Current
10
VF

25 V

VF

-

25 V

10

".

"
0.1

0.1
0.1

10
IF (mAl

0.1

10
IF (mAl

7-39

.HSiliconix

NKM

incorporated

TYPICAL CHARACTERISTICS

Temperature Coefficient vs. Regulator Current
0.25
V F =25 V

On-Resistance vs. Regulator Current

2

1~0.1IF~2L \.

Tc
(%/OC)

o

o
T

= 25 to

rOS(ON)

,

-55 to 25°C

--r-

'-

,

125°C'\..'

II II
II II

-0.25

....

(k.t1)

o

0.1

10

Capacitance vs. Forward Voltage
20

; =

o

2

Thermal Resistance vs. Power Dissipation

1000

lIMH~_

6JA - (TA )

10

\.

6JR

~

100

RANGE f-t-I
I
TA =25° C stili air. current regulator
.25 In. above circuit board
T c =25°C Infinite heat sink

........
o

10

10

20

30
VF (V)

7-40

I-

(OC/W)

'I..
.....

o

--

6JC - (Tc)

f=

40

50

o

100

200

300

Po (mW)

400

500

NKO

~SilicDnix

~ incorporated

N-Channel JFET Current Regulator Diode
DESIGNED FOR:
•
•
•
•

Current Regulation
Current Limiting
Baising
Low Voltage References

TYPE

PACKAGE

Single

TO-18

Chip

DEVICE

• CR160 through
CR530
CRR1950 through
CRR4300
• Available as above
specifications

FEATURES
•
•
•
•

Simple Two Leaded Current Source
Current Insensitive to Temperature
Changes
Tempurature Coefficient Better than
0.15 %/0 C on all Devices
Simplifies Floating Current Sources
No Power Supply Required

GEOMETRY DIAGRAM

..
Cathode Is backside contact

7-41

wrSiliconix

NKO

~ incorporated

TYPICAL CHARACTERISTICS

Output Current

vs.

Forward Voltage

OutF?ut Current

vs.

Forward Voltage

10

10

5

/'

L

-

5

h V'
o

'CRJ60

bR3!0

If/

o IT

CR530

CR530

CR240

CR~40

CR160

CR160

2

3

4

5

o

o

50

V F (V)

100

VF (V)

Limiting Current VS. Temperature

Knee Impedance VS. Regulator Current

10

10
VF = 25 V
Steady State-

-

CR530

5

CR~60

VF= 6 V

.....

I--

~

0.1

CR240
CR160

o

0.01

-55

-15

85

25

125

0.1

10

TJ (OC)

Dynamic Impedance

vs.

Limiting Voltage @
O.B IF VB. Regulator Current

Regulator Current

100

10
VF

V F = 25 V

25 V

10
~

......

0.1

0.1
0.1

7-42

10

0.1

10

~Siliconix

NKO

~ incorporated

TYPICAL CHARACTERISTICS

Temperature Coefficient vs. Regulator Current
0.25
V F = 25 V

On-Resistance vs. Regulator Current
500

I

I

I

I

I

1=0.1 IF@ 25 V -

\

.\
\

Te
(%/oC)

\
rDSION)
(k!l)

\\

o

~

/V
I - TJ: 25 to 125:C/
I

-I

-~5It~ Frl

F

' .....

.......

1'\

"

II "I

-0.25

~
250

o

0.1

10

o

-

5

IF (rnA)

10

IF (rnA)

Capacitance vs. Forward Voltage
20

I

,I,

Thermal Resistance vs. Power Dissipation
1000

I

f = 1 MHz_

--

1\
\

(OC/W)

.........
..........

.......

----

9Je - (Te)

9JR

r--...

10

9JA - (TA ) I-I--

100

RANGE

t--.

-

TA = 25°C stili air, current regulator
.25 In. above circuit board
T c = 25°C Infinite heat sink

o

o

10
10

20

30
V F (V)

40

50

o

100

200

300

400

500

PD (mW)

..
7-43

NNR

.:rSiliconix

~ incorporated

N·Channel JFET Dual Monolithic
DESIGNED FOR:
•
•
•
•
•

FET Input Amplifiers
Low and Medium Frequency Amplifiers
Impedance Converters
Precision Instrumentation Amplifiers
Comparators

FEATURES
•

•
•
•

Minimum System Error and Calibration
5 mV Offset (U401)
95 dB Minimum CMRR
Low Drift with Temperature
10 jJ.V/oC (U401)
Simplifies Amplifier Design
Output Conductance < 2 IJ-S
Low Noise
en = 6 nV/VHz at 10 Hz Typical

GEOMETRY DIAGRAM

0.004
(0.102)

7-44

I

TVPF
... -

PACKAGE
_.. - ..

Dual

SOIC-8

• SST404, SST405,
SST406

TO-71

• 2N6905, 2N6906,
2N6907
U401, U402, U403,
U404, U405, U406

Chip

• Available as above
specifications for
U404, U405, &
U406 only

DEVICE

NNR

fCrSiliconix
.LJJI incorporated
TYPICAL CHARACTERISTICS
Drain Current & Transconductance
vs. Gate-Source Cutoff Voltage
10

g Is @ VOG = 15 V, V GS = a V, I - 1 kHz
loss@ Vos= 15 V, V GS = a V

8

/~

6
gls/

loss
(mA)

,/
4

;I'

X

I'

6.4

~

4.8

/

gls
(mS)
3.2

/

~Ioss

/~

2

a

Operating Gate Current

8.0

1.6

/V

.;"

a

-0.5

-1.0

IG
(pA) 10 2

-1.5

a

-2.0

0.1

-2.5

Y OG (V)

VGS(OFF) (V)

Common-Source Forward
Transconductance vs. Drain Current

On-Resistance & Output Conductance
vs. Gate-Source Cut 011 Voltage

500

10

I\,
ros

VOG= 15 V
1= 1 kHz

I\.
"\
gasI"

./' ~

,,/

".

V

......
gas
(.uS)

gls
(mS)
1.6

.......
~

f-ros@ 10= 100 .uA, V GS = a V
gos@ VOG= 15 V, V GS = a V, 1=1 kHz

-0.5

-1.0

-1.5

-2.0

TA = -sso~.l
II
~
25°C ---, ~"/

2.4
5

,. /
a

VGS(OFF) = -1.5 V

3.2

"'-

a

4.0

~

I.-:

0.8

~ t:::::~

-

-2.5

a

........125°C

~r"""

a

0.01

0.1

VGS(OFF) (V)

10 (mA)

Equivalent Input Noise Yoltage vs. Frequency

..

Output Conductance vs. Drain Current

20

5
V oG =15Y

V oG =15V
1= 1 kHz

VGS(OFF) = -1.5 V

4
:,\O@ 200 .uA

3
en
10
(nV/Vi=iZ)

i'\

I
0.01

TA = -55°C

(,US)

'\

2

-Y

a

gas

f'.
-~

FFI~II

25°~

I

t10

I (kHz)

~~

P125°C
I-

111111
0.1

~

100

a

0.01

I
0.1
10 (mA)

7-45

NNR

.:r-Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Output Characteristics (VaS(OFF) = -1.5 V)

Output Characteristics ( Vas (OFF) = -1.5 V)

10
(rnA)

'1I1111n
./

1.5

/
/

V

.I~ V
V
~

o

I'.

o

--

./

-

'"

---

./

V

",

I

I

~

~

1.2 V

10
(rnA)

1.6

-0.6 V

I

o.d V

-

~

-0.4 V

If

-0.6 V

I

~0.8IV

'/

0.8

-1.0 V

-1.2 V

o

0.5

I

o

-1.0 V

10

VOS (V)

20

Vos (V)

Output Characteristics (Vas(OFF) = -2 V)

Output Characteristics (Vas (OFF) = -2 V)
10

Vas = 0 V
10
(rnA)

2

l-+-I-+~~~~"--b..-r:;

10
(rnA)

-0.2 V

5

0.4 V

io"'"

-0.6 V
0.8 V
-1.0 V
-1.2 V

o

o

20

Vos (V)

Transfer Characteristics

Gate-Source Differential
Voltage vs. Drain Current
100

Vas (OFF) = -1.5 V _
Vos = 15 V

~1 =~sso~
I

TA - 25°C
V oa -15V

I

'\4- 25°C
2.5

10

VOS (V)

5

10
(rnA)

-.l

o

~

\ I\.
I' 1\.\

~~

--

125°C~

o

'"
o

Prime

i'IIIo..
""III

~Iooo.

-1
Vas (V)

7-46

-2

1
0.01

0.1
10(mA)

NNR

ICrSiliconix

~ incorporated

TYPICAL CHARACTERISTICS
Common Mode Rejection Ratio
vs. Drain Current

Voltage Differential with Temperature
vs. Drain Current
100

130

!=VOG- 15 V
~TA 25 to 125°C
-55 to 25°C

I-TA

120

1-

"-

AIVGS1 -VGS21
--'--A""t.----' 10
(JJ.VIOC)

1

110
CMRR
(dB)

AI V GS1 - VGS21

I I I 111111
r- Lo~J 110 1_IJJlv

ir:"1~ I

90

III

80

0.1

--- --

- :'--'"

100

0.01

-:.--

On-Resistance
TA = 25°C

VS.

I J 1111
111111
0.01

0.1
10(mA)

Drain Current

Circuit Voltage Gain

III

1.1 I.
VGS(OFF)=Y

Jv
Jo')

Drain Current

Ay

r-.

VGS(OFF) = -1.5 V

~

90

~

-2.0 V"",,

\.

~
60 Ay =
~
1 + RL gos
30 Assume Voo = 15 V, Vos = 5 V
RL= 10 V
,
,
10

IIII

""~

o
0.01

:::::

120

51

250

VS.

150

~ .1 I I

rOS
(.0. )

I-

5 - 10 V

lo(mA)

500

AV OG

CMRR = 20 log

o

0.1

0.01

0.1
10(mA)

lo(mA)

Common-Source Input Capacitance
VS. Gate-Source Voltage
10

If

Common-Source Reverse Feedback
Capacitance vs. Gate-Source Voltage

10

=~ MJz-

L lIMH!_

\)s='o)
Clss
(pF)

5

\
1\ ,
~\ I\..

erss
(pF)

5V

5
\ Vqs = 0 V

\~ ~...J.
"""- ~

\

...... r'+4r-r- I- 15 V

15 1V

o

o

5V

-10
VGS (V)

-20

o

I

o

-10

-20

VGs(V)

7-47

~SilicDnix

NNT

~ incorporated

N·Channel JFET Dual Monolithic
DESIGNED FOR:
•
•
•

Ultra Low Leakage FET Input Op Amps
pH Meters
Electrometers

I Tr-C

I""A'-'''AUC.

Dual

TO-78

• U421. U422. U423.
U424. U425. U426

Chip

• Available as above
specifications for
U423. U424. U425.
U426

FEATURES
•
•
•

Ultra-High Input Impedance
Good Voltage Gain
Low Noise

GEOMETRY DIAGRAM

T
0.024

!----_~I

I(4.----

7-48

I

0.024
(0.610)-----1>

UCVI,"",C

NNT

.:r-Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Drain Current & Transconductance
vs. Gate-Source Cutolf Voltage

Operating Gate Current

2

V

gf.

/

/

loss
(mA)

V

L

/

J
/,

V

/

IL
loss f--

-

V

0.5 9t.
(mS)

/
'./

o

5

ros
(kn) 2.S

9t.@ Voa=10 V, Vas= 0 V
1= 1 kHz
loss @ Vos = 10 V, Vas = 0 V

o

o

Vas (OFF) (V)

Voa (V)

On-Resistance & Output Conductance
vs. Gate-Source Cut all Voltage

Common-Source Forward
Transconductance vs. Drain Current

~

W
-

-

ros @ 10 = 10 JJ.A, Vas = 0 V
go.@ Voa = 10 V, Vas = 0 V

I

-~=1kHZ

\:~s

TAII= -S5°C

V

/
./

Vas (OFF) = -1 V

-

90.

" ./r.......

,/

o

-S

-2.S

;'

o

90.
10 (JJ.S)

-

2~!~

9t.
(mS)O.S

. /~

,?9

/ . t::;;~

~~

-2.S

-S

o

12SoC

Voa= 10 V
I = 1 kHz
I I 11 II

LI

o

0.01

0.1

Vas (OFF) (V)

10 (mA)

Equivalent Input Noise Voltage vs. Frequency

Output Conductance VS. Drain Current

SO
V

I-

= 10 V

_Voa=10V
f = 1 kHz

I III

*

HIJ-H1111--1-+
1 -++++++1
TA = -SSOC /

en
2S
(nV/Vi=iZ)

~

'"
....

9 os O.S
(JJ.S)

10 = 30JJ.A

l---if--H::;;I.oo1%IoI'::>':~A-/-+-t-t+if-ttl
__
/'
~

-~ ..... ~
i"-o.

10

o

0.01

125°C

'11

-t--+-+++t+H

J.

100JJ.A

I-VaS(OFF)= -1 V -1++---1--+-++-1-1-++1

o~_~i~(~II.I~I~~~~~

111111
0.1

10

I (kHz)

100

0.01

0.1
10 (mA)

7-49

IfII

.-rSiliconix

NNT

~ incorporated

TYPICAL CHARACTERISTICS
Output Characteristics (VaS(OFF) =-1 V)

Output Characteristics (VaS(OFF) =-1 V)
0.5

I I

J

I

Vas = 0 V

10
(mAl

10
(mA)

0.25

0.1

"

-0.1 V

~

:'0.2 V

I~

-0.3 V

~

0.4 V
0.5 V

Z"

0.5

0.6 V

f/

o

0
0

0.5

~ -0.7 V

o

10

Vos (V)

20

Vos (V)

Output Characteristics (VaS(OFF) = -1.5 V)
0.5

Output Characteristics (VaS(OFF) = -1.5 V)

I I
I

J

Val~
10
(mA)

~

::% ~
~ ::::... i-"'

o

.......-r:.o 2' V

~

V

0.25

IJ!. ~

o

/' ~ "

",

-0.4 V

Vas = 0 V
10
(mA)

0.5

~

-0.2 V

I. I'"

-~o.jv

V

-0.6 V

'/

-1.0 V

o

0.5

o

-0.4 V
-1.0 V-

_

-0.6 V
10

20

Vos (V)

VOS (V)

Transfer Characteristics

Gate-Source Differential
Voltage vs. Drain Current
100

0.5

Vas (OFF) = -1 V
1

1

VDa- 10 V
TA - 25°C

1

~A = ;SSOC
25°C

~10
(mA)

0.25

~~

"

~aS1 - Vas21
~

125°C ~

I

o

I

~

'"

~

-0.5
Vas (V)

7-50

10

(mV)

1
I
VOS = 10 V

o

-0.6 V

...

~

P,RIM,E

~
-1

1

0.01

0.1
10(mA)

NNT

ICrSiliconix

~

incorporated

TYPICAL CHARACTERISTICS
Common Mode Rejection Ratio
VS. Drain Current

Voltage Differential with Temperature
VS. Drain Current
130

100
V OG -l0V
TA - 25 to 125°C
= -55 to 25°C

\VGS1 - VGS2\

....:...._l!.~t_.:...l0

r--

(,Uv/oC)

r--T"'""'T""",.....,..~I'TI'"-...,.....,..-.-.,...,...,.,.,.,

I- CMRR = 20 log ""T"-':'l!.~V~O~GL..=r-HHiti

-

I-

CMRR
(dB)
100

...

1---+1--l~I+~_..j..,....~~~
1- .....

90~-+-~4-~+H+--4--+~~++~

prEI
0.1

0.1

10(mA)

lo(mA)

0.01

Circuit Voltage Gain vs. Drain Current

On-Resistance VS. Drain Current
100

5

-

a

I

I- RL = 10 V

/ " I

-1.5 V

10

I-

Av

-"

I

1 + RLgoS

f.- Assume Voo = 15 V, Vos = 5V

I

2.5 _ VGS(OFF) = -1 V

AV=~

I-

I

rOS
(k.O. )

\ VGS1 - VGS2\1-+-I--I4++I

120 I-

.::~ .....

50

I

·n·illll~ ~

0.1

Tr m

0.01

0.1
lo(mA)

10(mA)

Common-Source Input Capacitance
vs. Gate-Source Voltage

2

I

I

Common-Source Reverse Feedback
Capacitance vs. Gate-Source Voltage
I

:\. Vos =

aV

~

~ ~

51V

"'-

f = 1 MHz_

-

~ r--...: 1'/........

"'r.-

C lss
(pF)

I-- 10 V

a

a

.......

C rss
(pF)

-10
VGS (V)

I "I

l\..

o
0.01

I I III
VGS(OFF) = -1 V

-20

1
,
,
f = 1 MHz-

,I

I. . 1
V S =,0 V,

........

r-....

"

5

V'-I-

........ ...... i--

0.5 I-- 10 V"""

o

a

-10

-20

VGS (V)

7-51

•

NNZ

.:rSiliconix

~ incorporated

N·Channel JFET
DESIGNED FOR:
•
•
•
•

TVOE:'
I

High Frequency Amplifiers
Mixers
Oscillators
Hybrid Op Amps

II

....

Dual

11'""'\_I,r-\ _ _

SOIC-8

• SST440, SST441
SST5912

TO-71

• U440, U441

TO-78

• 2N5911, 2N5912
U443, U444

FEATURES
•
•

High Gain
Low Input Capacitance

Chip

GEOMETRY DIAGRAM

iBJl

0.024

(0.610)

I.

7-52

-_ .. _-

nl=\Ill"l=

• Available as above
specifications for
2N5912, U440,
U441 , U443, U444

NNZ

~Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Drain Current & Transconductance
vs. Gate-Source Cutoff Voltage
25

9ts@ VOG = 10 V, V GS = a V
f = 1 kHz
loss@ Vos = 10 V, V GS = a V

20

/

15
loss
(rnA)

-

10

II
~

~
I-

I-

I-::l ~

10 gts
(mS)

V

~

5

a

/

~

9ts

I--

Operating Gate Current
15

V

VI'

loss

5

a

-5

-2.5
VGS(OFF) (V)

VOG (V)

Common-Source Forward
Transconductance vs. Drain Current

On-Resistance & Output Conduotance
vs. Gate-Source Cutoff Voltage

,

250

,-gas

ros \

200

\

150

"-

100

V
./

-

50

><.

".../

II

V OG =10V
f = 1 kHz
l .1.1
VGS(OFF) = -3 V

I-

-I'

V

-- -

90S
50 (JlS)

9ts
(mS)

f I

,

-2.5

5

25°C
125°C

..... k

~
5

a

/. ;....,

TA = -55°C-

r-

ros @ 10 = 1 rnA, V GS = a V 90s@ VOG = 10 V, VGS = a V f = 1 kHz

a

10

V

~

rOs
(.0. )

a

100

a

~~

-

~

""\

;...-:;S

;;;...-

0.1

10

VGS(OFF) (V)

10(mA)

Equivalent Input Noise Voltage vs. Frequency
20

Output Conductance vs. Drain Current
50

V

= 10 V

II

VOG= 10 V
f = 1 kHz
_I I
VGS(OFF) = -3 V

.I.

,

T " ,,
I

\
en 10
(nVI '"t--,-10

(.lLV/OC)

I> V DG

=20 log

IVGS1 -VGS21

-

CMRR
IdB)

100

prime I

-

- -'

I> V DG
I> VDG

II

50

1

10

0.1

On-Resistance

VS.

10
IDlmA)

Drain Current

Circuit Voltage Gain

=25°C

,~'iIT:;.a
.'.1111

100

VGS(OFF)

I

1 + RLg as
Assume VDD = 15 V
VDS = 5 V

1-+1'-*'+iH-t+t

I

Av

=-4 V_

= -3 V -1-1 ,.. .......

VGS(OFF) = -4 V

0.1

10

0.1

10
IDlmA)

Common-Source Input Capacitance
VS. Gate-Source Voltage
10
f

o

r-/-,--j--t--'1"""t-l--W±I
tl--'

OL-............--o................u...__-L.---I....J....J...I..L.JOU

IDlmA)

5

RL = 10 V
ID

,1\

50~+-~~~~+H+---r-~~~~

VGS(OFF)

C iss
IpF)

Drain Current
________~

Av=~

\

1\ 1\

I-'\+,"\+++-I-+-I-t

o

VS.

100~~~~~~~----

TA

rDS
1.0.)

I

0.1

IDlmA)

200

= 5 - 10 V
= 10 - 20 V

5

= 1 MHz

,
~ ~.......
o

Common-Source Reverse Feedback
Capacitance vs. Gate-Source Voltage
f = 1 MHz

LI-I- VDS = 0

V

C rss
IpF)

=5 V
~lJf't=VDS =15 V
VDS

~,

--

2.5

V GS IV)

~
::::: ~'Y_:"'~

_ - / F VDS

...

-10

t,'--I-VDS = 0 V
VDS = 5 V

-20

o

o

= 15 V

-10

-20

V GS IV)

7-55

NPA

~Siliconix

~ incorporated

N·Channel JFET
DESIGNED FOR:

I

.,

Srnaii Signai ArTlpiifie(s

TYPE
-- -

PACKAGE
---

•
•

Voltage Controlled Resistors
Choppers

DEVICE

Single

TO-92

• J201, J202, J203,
J204
PN4302, PN4303,
PN4304

SOT-23

• SST201, SST202,
SST203, SST204

TO-18

• 2N4338, 2N4339,
2N4340, 2N4341
VCR4N

TO-72

• 2N4867, 2N4868,
2N4869, 2N4867A,
2N4868A, 2N4869A

Chip

• Available as above
specifications

FEATURES
•
•
•
•

Low Noise NF < 1 dB at 1 KHz
Operation from Low Power Supply Voltages
VGS(off) < 1 V (2N4338)
High Off-Isolation as a Switch
I D(OFF) < 50 pA
High Input Impedance

GEOMETRY DIAGRAM

0.017
(0.432)

Gate also backside contact

7-56

NPA

~Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Drain Current & Transconductance
VS. Gate-Source Cutoff Voltage
10

gls/

S

/'

I-I-- 4

104

~

-

10 3

3
gls
(mS)

IG
2
(PA)10

2

./

1/
a

..- /

l-

/

/

a

10 5

J

~.I
~
.'
I
I
i - gls @ Vos= 10 V, V GS = a v
f = 1 kHz
i-loss@Vos= 10 V, V GS = a v

I
loss
(mA)

Operating Gate Current
S

10

./ViOSS

./

V

-1

-3

-2

-4

a

-S

0.1

VGS(OFF) (V)

VOG (V)

Common-Source Forward
Transconductance vs. Drain Current

On-Resistance & Output Conductance
VS. Gate-Source Cutoff Voltage
lS00
9
1200

rOS

~ro

(.n. )

600

300

o

2

)<

II

V oG =10V
f = 1 kHz
I L1.1.
-VGS(OFF) = -l.S V

o~

V

1\
900 I -

10

I ./ V'

II

/

V

/

gos

S (Jl.S)

r-

(mS)

~/

-

~2SoC
~

f = 1 kHz

-1

-2

-3

-4

-S

o

o

~~

F"
0.01

VGS(OFF) (V)

0.1
10 (mA)

Equivalent Input Noise Voltage vs. Frequency
20 r-rTnmrr-~~mr-r~T-------m
V oG =10V

111111

~

'-'I
~f'

~!oc
\

915

ros @ 10= 100 Jl.A. V
=0V
- ~ gos@ VOS= 10 V. V GSGS= 0 V -

o

TA = -SsoC

I

I

Output Conductance vs. Drain Current

3

I I I)!!!

VOG= 10 V
f = 1 kHz

I
i'

en 10
(nV/VHz)

-

0
0.01

fA

gos
(Jl.S) l.S

r.....
V GS = 0 V

I"r-.
i'"

0.1

10
f (kHz)

d

-

III

VGS(OFF)= -1.S V
I
I I I II

2s o

l\.

II

1Jsq~
/1.

~~

~oc100

o

II I

0.01

0.1
10 (mAj

7-57

NPA

~Siliconix
incorporated

.LII

TYPICAL CHARACTERISTICS
Output Characteristics (VGS(OFF)= -0.7 V)

10

"'lllllll8iB

(J.LA) 150

V

~V
~~ i.-"

o •
o

/

~
,...

v ,... ..... ~I
.....

-

-0.2 V

~

!-'

Output Characteristics (VGS (OFF) = -0.7 V)
400

I.

r

I I
10 . 1

(J.LA) 200

JO•2 ~-0.3 V

0.4 V
0.5 V-

o

0.5

o

10

VGS= 0

(rnA)

0.5

/
I
//

./

,...r-

I I

V GS = 0 V

-0.3 V

~ r-

--

h y"
!-'

IR.. ~
o
o

I I

/

I

/'

V

Output Characteristics (VGS(OFF)= -1.5 V)

2

VA

V

/

-0.6 V _

(rnA)

I I

I

0.6 V
J9J-

r

-1.2 V

o

0.5

-6.9

Transfer Characteristics

o

10

Transconductance vs. Gate-Source Voltage

1.2

~

~~C

0.9

'"

i'
i-TA = -sso~
I

I

I

......

I"-

.......
..........

-0.25
V GS (V)

l'......

r-.....:

-

-0.5

VGS(OFF) = -0.7 V
Vos = 10 V
1kHZ -

fl

TA = -55°C

25°C

.......... I""': ~
125°C......

...;:::: ~
I~

0.3

0

-

.......... .......

0.6

..........

o

.........

........ ......

gls
(mS)

25°C

'~ ........ i'

7-58

20

1.5
VGS(OFF) = -0.7 V _
Vo = 10 V

o

J

- .2 V

Vos (V)

500

10

I

-LJ-

10

VOS (V)

(J.LA) 250

20

Vos (V)

Output Characteristics (VGS(OFF)= -1.5 V)

10

-0.4 V

-0.5 V

Vos (V)

/'

~-

10

~~Lt-

0.25

!

I

VGS 1= 01

o

-0.25
V GS (V)

~

"- ~

~
-0.5

NPA

~Siliconix
..c;;II incorporated
TYPICAL CHARACTERISTICS

Transconductance vs. Gate-Source Voltage

Transfer Characteristics

2

I

NA

=

~ \

~

4

.1,

25!C
~

gfs
(mS)

.\
" ..'\r\

125°C......

~

\I:::

o

~A
2

= -55°C

~" ........

N~

-

I-

o

-2

-1

"

.........

......

-1;;~ ~
I

I

o

........ ~

-1

-2

VGS (V)

VGS (V)

On-Resistance vs. Drain Current

Circuit Voltage Gain vs. Drain Current

2000

I
II

T A =25°C

I I I

AV=~

1 + RLg es
Assume Voo = 15 V. Vos = 5 V

VGS(OFF) = -0.7

RL = 10 V

./

10

rOS
(.o.) 1000

AV

0.01

100

P..l--+-t-+f-l++I---t--f-l--I-f-H+I

i""

VGS(OFF) - -1.5 V

o

VOS = 10 V _
f = 1 kHz

.-r--

K

"
o

I

VGS(OFF) = -1.5 V_
Vos=10V

~550:C- -

i\

r\
10
(mA)

I

0.1

0.1

10(mA)

10(mA)

Common-Source Input Capacitance
vs. Gate-Source Voltage

Common-Source Reverse Feedback
Capacitance vs. Gate-Source Voltage

10

I

I

5

.1

fl =

f = 1 MHz-

lIMH~-

4

C lss
(pF)

5

3

1\

C rss
(pF)

r\..\VOs-OV

.........

I

o

l""k
-L

-

l - i- rOS,- 10 V
l

IVoSI= 1~ V

o

\ VOS = 0 V

2

~
I - 1-1.

\

-10
VGS (V)

-20

o

o

-10

-20

VGS (V)

7-59

.:r-Siliconix

NQP

~ incorporated

N·Channel JFET
DESIGNED FOR:
•

TYPE

GenerClI Purpose Amplifiers

Dual

I

PACKAGE

TO-71

FEATURES
•

High Input Impedance
Chip

GEOMETRY DIAGRAM

T
0.023

L-f----+-----::-=::-:-------l

I14"---7-60

0.004---J
(0.102)
0.024
(0.610)

II

I

DEVICE

• 2N3956. 2N3957.
2N3958
2N5196. 2N5197.
2N5198. 2N5199
• Available as above
specifications for
2N3956 through
2N3958. 2N5198 &
2N5199

NQP

~Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Drain Current & Transconductance
YS. Gate-Source Cutoff Voltage

5

Operating Gate Current

3

/ VI
IDSS
/

4

J

V

gf5/

1/ I
J

IDSS
(mA)

2

V /

2

J

gf5
(mS)

)

/ IIgf5@ V DG

I

o

~ 15 V, V GS ~ 0 V
I Dss @ VDS~ 15 V. V GS = 0 V
f ~ 1 kHz

L
,

o

-1

1

-4

-3

-2

-5
V DG (V)

VGS(OFF) (V)

Common-Source Forward
Transconductance YS. Drain Current

On-Resistance & Output Conductance
YS. Gate-Source Cutoff Voltage
10

/l

I

\
\

2.5

gas
2.0

I
I\.

rDS
(k.Q)

5

'"

/
o

1.5

'J

0.5

o

gas

(.u.s)

gf5
(mS)

I

0.5

ID~ 100).lA. VGS~ 0 V
gas @ VDG~ 15 V. VGS~ 0 V
f ~ 1 kHz

-2

TA

1.0

'~DS

V
VrDS @

-1

VGS(OFF) ~ -2 V
V DG =15V
f ~ 1 kHz

-4

-3

o~

o

V G ~ 10 V
2.0

'\
II

ID~l~fl~~

mr-ttttt
VGS~ 0 V

III
10

o
0.01

0.1

f (kHz)

I

f = 1 kHz
VGS(OFF) ~ -2 V

- T AI

1.5

I

II

I
VDG~15V

\

:-

I
0.1

Output Conductance YS. Drain Current
2.5

~

I

ID (mA)

Equivalent Input Noise Voltage vs. Frequency

I'-..

25O~'{~

/ V1:.~ "'125°C

0.01

-5

20

en
(nV/VHz") 10

-55°C

~ ::::~
~

VGS(OFF) (V)

\

~

III

I
~ _155!J

25°C

gas
(.u.S)

b(fI

I/V
/ l0
Vh

1.0

0.5

!7"125°C

III
100

o

0.01

~~
0.1
ID (mA)

7-61

crSiliconix

NQP

~ incorporated

TYPICAL CHARACTERISTICS
Output Characteristics (VGS(OFF) =-2 V)

Output Characteristics (VGS (OFF) = -2 V)

U

"1111111 U
10
(mA)

10
(mA)

-0~2 V

2.5

-0.4 V
-0.6 V
-0,8 V

1,0 V
-1,2 V

o

o

o

0.5

o

10

Output Characteristics (VGS(OFF) = -3V)

Output Characteristics (VGS(OFF) = -3V)

......-.....-....,....-,

5

2.5 .......,.....--r-~..,...~r--...,...

v

1---+--t-+--I--I7"''-bA:~:-u

S

OV

/

2. 0 1---+--t-+--I--I--I---\-7"l-7"~

1 .5

20

Vos (V)

Vos (V)

-o.J v

J /'

I

1/

.•,
10
(mA)

10

(mA)

-D,6 V

I'

2.5

v
dv
-dv

-D,d

,..-

1.0 1---+--t--t7~"""1--:::;...t""'-::l;"""""'--1

0.5

1,h
2,1

o

o

0.5

o

10
Vos (V)

Transfer Characteristics

Gate-Source Differential
Voltage VS. Drain Current

.I

......-r--...,...-,
I

I

!

100
TA - 25°C
V oG -15V

VGS(OFF) = -2 V -

10
(mA) 2.5

,\

TA=-55°C

~

""

~5°C'

25°~

IVGS1 -VGS2110
(mV)

~'\

"- ~

~~

o

o

-0.5

-1.0

Prime

~ 10..
-1.5

V GS (V)

7-62

20

Vos (V)

5.0 ........,.......,.--r-..,...~r--...,...

-2.0

-2.5

1

v

-2,4 V

I III
0.01

0.1
10(mA)

NQP

.:r-Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Common Mode Rejection Ratio
VS. Drain Current

Voltage Differential with Temperature
vs. Drain Current
100

130
V DG 15 V
TA 25 to 125·C
= -55 to 25·C

CMRR = 20 log
120

I III II
I III II

110
CMRR
(dB)

AV DG = 10 - 20 V

100

5 - 10 V

Prime
I III

90

11

1
0.01

II
I I

80
0.01

0.1

0.1

ID(mA)

ID(mA)

On-Resistance vs. Drain Current

Circuit Voltage Gain vs. Drain Current

100

~VGS(OFF) = -2 V
-3 V

rDS
(k.n.)

AV

VGS(OFF) - -2 V

0.5

i'\1\

50

~,

-3 V

Av=~

o

~

1 + RLg as
AssumeVDD =15V,VDS= 5v
RL = 10 V
ID

o

0.1

0.01

0.01

Common-Source Input Capacitance
VS. Gate-Source Voltage

Common-Source Reverse Feedback
Capacitance VS. Gate-Source Voltage

10

5.0

~ = 1IMH~-

fl= 1IMHZI_

5

V DS = 0 V

C rss
(pF)

~ ,-

\V is = 0 V
2.5

'"

~

.'\

~" ,.....

5J

~

"""--1........
15 V

~;....

I

15 V

o

o

i'

0.1
ID(mA)

ID(mA)

C lsS
(pF)

AVDG
AlvGS1 - VGS21

1

-10
VGs(V)

-20

o

o

-10

-20

V GS (V)

7-63

..

NRL

.:rSiliconix

~ incorporated

N·Channel JFET
DESIGNED FOR:

=
•
•
•
•

Small Signal Amplifiers
VHF Amplifiers
Oscillators
Mixers
Switches

•
•

Single

TO-72

• 2N4220, 2N4221,
2N4222
2N4220A, 2N4221A,
2N4222A

Chip

• Available as above
specification

Wide Input Dynamic Range
High I G Breakpoint voltage
High Gain
Low Insertion Loss Switches

GEOMETRY DIAGRAM

0.018

----L..--f-'---_--L---J.~
I"'.f------

I

0.018
(0.457) ----~.

Gate also backside contact

7-64

DEVICE

PACKAGE

FEATURES
•

I

TYPE

"I'"

NRL

~Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Drain Current & Transconductance
VS. Gate-Source Cutoff Voltage
20

"...,.. ~

loss
(rnA)

I

10

V

_..,........,-...,.--r-T"""-r-r-""""",,_

/
J

loss

I

10 5

V

g,y i-"""

V

Operating Gate Current
5

2.5 g,s
(mS)

17

/

IG 10 2 h--+--;--j
(pA)
10

/
g,s @ Vos = 10 V. V GS = a V
f = 1 kHz
loss@ Vos = 10 V, V GS = 0 V

L
o

a

-5

-10

a

15

VGS(OFF) (V)

Common-Source Forward
Transconductance VS. Drain Current

On-Resistance & Output Conductance
vs. Gate-Source Cutoff Voltage
500

50

2~~--~~~~--~~~~~

II

VOG= 10 V
f=lkHz 1J1!~!~!--~-+4-~~~~
VGS(OFF) = -3.5 V.+t--I-+-tilNFttI

V

r- ~O

/

i IIII

Irgas

/

rOs
(n) 250

"

30

VOG (V)

gas
25 (JJ.S)

I

g,s
(mS)

P'.

/
o

~

/

i"-I--I-

ros @ 10 = 0.1 rnA, V GS = a V
gos@V os = 10 V, VGs= a V
f = 1 kHz

a

-5

a

O~~--~~~~--~~~~~

0.01

-10

0.1

VGS(OFF) (V)

Equivalent Input Noise Voltage

10(mA)

VS.

Frequency

30

Output Conductance

V p' = 10 V

en
15
(nV/Vi=iZ)

II
\.

;--

~

'I 1111I
II I

-10 ~,,~ rnA

10

gas 2.5
(JJ.S)

-10 = 10 rnA

25°C

I

1K
f (Hz)

10 K

100 K

--,

.J- -W.J.

125°C

I",

100

-

V.

TA = -55°C

.......

o

Drain Current

VoG = l O V I I I
f = 1 kHz
VGS(OFF) = -3.5 V

\

\

VS.

5

a r--

0.01

--

~~

I/Y

j ~
~

/y. /
W

,I

1

I
0.1
10 (rnA)

7-65

NRL

~Siliconix

~ incorporated

TYPICAL CHARACTERISTICS

Output Characteristics (VGS(OFF) = -1 V )

Output Characteristics (VGS(OFF) = -1 V)

-

l-

V

VGS = 0 V----.!..
-0.1 V

",IT V

VY
/ V /"
.IV:V
//. V V

10
(rnA) 0.5

J. ~

I

I

-0.2 V-

I

I

-0.3 VI
I
0.4

"-=

-U. I

10
(rnA)

,

-0.7 V-=

Ie- io""

I

o

0.4V- I--

f/,

-0.6 V-

I

o

0.5

-0.5 V- I-0.6 V

o

5

Vos (V)

10

VOS (V)

Output Characteristics (VGS(OFF) = -3.5 V )

5

.-

-0.2 V
0.3V- r-

'I

-0.5 V-

~~
J~

o

..H-

Output Characteristics (VGS(OFF) = -3.5 V )

r-~~--~~~~~~-r~~

15

1 1
1 J
IV GS = 0 V

10
(rnA) 2.5

10
(rnA)

.I

7.5

V"
Z~

I

j

-1.0 V
-1.5 V-=

'L

o

o

0.5

....o

-2.5 V

I

Transconductance vs. Gate-Source Voltage

3

I
I
I .!
VGS(OFF) = -1 V
Vos=10V

L r-- T A = -55°C

"

["-0..,

~
LS~ f=:. 125°C

1.5

~~

o

o

-...

""" ~ ~

-0.5

VGS (V)

7-66

'" "

-1

o

~~

o

VGS(OFF) = -1 V
Vos=10V
.r-t--

1"\ V.
~

gfs

(mS)

' (~

~

...
I........

r-- 25°C

~

10

Vos (V)

Transfer Characteristics

10
(rnA)

I

5

Vos (V)

2

'==

-2.0 V

UJ.

o

'==

~0.5IV- t--

.L

X<;-

"

TA = -55°C
250C - , 125°C -

t-

~

~

~~

'"
1\

-0.5
VGS (V)

I'.
~ .......
-1

NRL

~Siliconix

~ incorporated

TYPICAL CHARACTERISTICS

Transconductance vs. Gate-Source Voltage

Transfer Characteristics
10

10

1\

\ \
ID
(mAl

,r-< I,'

T A ;-55°C
\ \ 1\ r-y---- ,----- 25°C

'\1):'-

gfs

(mSI

125°C

5

r-.,. ~

o

~~
~~

o

I

I

I.

'---

1\'

5

I

e-- VGS(OFF); -3.5 V
V Ds ;10V
e-- f ; 1 kHZ

VGS(OFF); -3.5 V
V Ds ;10V

o

-5

-2.5

'"

-

L
.....
.........
"'vI
...... -....(j

-

On-Resistance
TA

VS.

25°C

~=

"""-.e ~ ~

........;

o

125°C

~

...... ~

-2.5

V GS (VI

1000

T A ; -55°C

-5.0

V GS (VI

Drain Current

Circuit Voltage Gain

VS.

Drain Current

200

~ 25~CI

Av;

~

1 + RLgos

Assume V DD ; 15 V, V DS ;

11
rDS
(.0. I

Av

500

100

""'................
" r--.

...... r-.

VGS(OFF) ; -1 V

11I11

I

~

I

I III

VGS(OFF) ; -1 V

VGS(OFF) ; -3.5
I I I II
I I

o

f---Y....

V GS (OFF) ; -3.5 V ----"

v_
I
10

..;:: ......
l"-

I I I IIIII1

o

0.1

0.01

0.1

ID(mAI

IDlmAI

Common-Source Input Capacitance
VS. Gate-Source Voltage

Common-Source Reverse Feedback
Capacitance vs. Gate-Source Voltage

5

10
f ; 1 MHz

f ; 1 MHz

\
C rss
(pFI

5

~~£
~

f-- V DS ; 0 V

r-/'F I=-

~
o

5V

RL; 10 V
ID

o

C rss
(pFI

V DS ; 5 V

\

2.5

f-- V DS ; 10 V

'\
~

-10
V GS (VI

I- V DS ; 0 V
I- V DS ; 5 V

-20

o

o

""'"

I[~
I1~r-

- _

V DS ; 10 V -

"'-

-10

-

-

-

-20

V GS (VI

7-67

NRL

.:r-Siliconix

~ incorporated

TYPICAL CHARACTERISTICS

Forward Admittance

Input Admittance
100

10

TA 25°C
V DS 15 V
V GS - 0 V
COMMON SOURCE

TA 25°C
V DS 15 V
V GS - 0 V
COMMON SOURCE

-

.DIS:::: p

.......

10

mS

mS
9,s

0.1

1===91s

I-'

---

I - - b ls

"

./

0.01
10

0.1
100

..............10

f (MHz)

Reverse Admittance

TA - 25°C
V DS 15 V
I
V GS - 0 V I
COMMON SOURCE..........
0.1

Output Admittance

--

mS

·1

b r;:;:;: .... ~

-I--- -~

TA

VDS

25°C
15 V

---

V GS = 0 V
0.1

-

mS

grs

0.01

100

f (MHz)

bas

-~

90S

0.01

;

COMMON SOURCE
0.001

0.001
10

100
f (MHz)

7-68

10

100

f (MHz)

NT

ICrSiliconix

,;zJfI incorporated

N-Channel JFET
DESIGNED FOR:
o

Ultra-High Input Impedance Amplifier
Electrometers:
Infrared Detectors
Smoke Detectors
pH Meters

PACKAGE

Single

TO-92

• PN4117. PN4118.
PN4119
PN4117A. PN4118A.
PN4119A

TO-72

• 2N4117. 2N4118.
2N4119
2N4117A.2N4118A.
2N4119A

Chip

• Available as above
specification

FEATURES
o

o

DEVICE

TYPE

Low Power
IDSS < 90 J.lA (2N4117)
High Input Impedance
IG < 1 pA (2N4117A)

GEOMETRY DIAGRAM

2T

•

cf~I
0.016~&.m1~

11+.---- (0.432)

•

1

Gate also backside contact

7-69

NT

.rSiliconix

~ incorporated

TYPICAL CHARACTERISTICS
Drain Current & Transconductance
VS. Gate-Source Cutoff Voltage

Operating Gate Current

1.0

300
gls@ VDS = 10 V, V GS = 0 V
f = 1 kHz
IDSS@VDS = 10 V, V GS = 0 V

V

.",.

/

I

o

./

V'
o

V

V

-"

~O J1IA ,

'

II GS~ @ 2SOC ,

§

100 J1A-

-3

-4

o

12

9

Common-Source Forward
Transconductance vs. Drain Current

( k.O. )
6

..,

3

0

o

J

200

S

4

V

~

3
gas
(JJ.S )

/
"- i;><- ......

gfs 100
(JJ.S )

2

/b

-2

-4

-3

-S

~

~"'L-TA = -SSoC
;--1 2SIoCI
I I
12SoC

~~

r

,/
!;,rDS@ ID = 10 J1A, VGS = 0"
gos@ VDS = 10 V. V GS = 0 V
f = 1 kHz

-1

~I II I
h¥ III

VDG=10V
f = 1 kHz

gos/

I'

rDS

30

VDG(V)

I

\ r D"-

(~

lS

-S

On-Resistance & Output Conductance
vs. Gate-Source Cutoff Voltage

,

ZY-

~ ~ ~\ §

TA = 2SoC

VGS(OFF) (V)

lS

I I ~
I i ' .....

T A =125°C

E

10

VGS(OFF) = -2.S V

o

o

0.1

0.01

VGS(OFF) (V)

ID(mA)

Equivalent Input Noise Voltage vs. Frequency

Output Conductance vs. Drain Current

200

2
V[)' = 10 V

/;1'

I- VDG =10V
f = 1 kHz

-0
\(

2~
en
100
(nV/VRZ)

o

0.01

lo=10J1A

~~
~V

gas
(JJ.S )

/A

W

r...VGS = 0

....

rtttH....
JlIll
0.1

10
f (kHz)

7-70

~TA = -SSoC

I

~

"

~

I Gss @ 12S0C'"\I'I:1

~

IG
2
lS0 gfs
(JJ.S ) (PA)10

/.I DSS- -

100 J1A --,

E
-2

-1

V'

E

10 3

"

~

E

10 4

'.-- rI
IDSS O.S l - I- gls
(mA)

10 5

100

o

0.01

~

2SoC
12SoC

"
VGS(OFF) = -2.S V
0.1
ID(mA)

NT

~SilicDnix
incorporated

.LII

TYPICAL CHARACTERISTICS

Output Characteristics (VaS(OFF)= -0.7 V)

Output Characteristics (VaS(OFF) = -0.7 V)

so
I Va 1= olv

......}-:t"""

-0~1 V~

~.""

/

/
10

(.llA)

/

L

// .....

2S

J.~

-

o

--

/'
/

=

..-!""

V aEL 0 V

II

-0.2 V..:;::;:

10

(.llA)

1
-0 .3 v'-=

I

_I""""

IJ/ . /

j ~/
o ~~

V-

100

~

-0.4 V

roo-

-O.S V

~
SO

IJ'

I

IJ'".

I I

o.S

-0.1 V

o V"

~~

-0.2 V

-

-0.3 V
-0.4 V

O.S V

o

10

Vos (V)

20

Vos (V)

Output Characteristics (VaS(OFF)= -2.S V)
200

Output Characteristics (VaS(OFF) = -2.S V)

SOO

I I

I I
Vas = 0 V

.Y':
10

(.llA)

100

./

/'. V

L& '/ I-"'"

o

'/

V

.I!!!

....-

o

..;

~

. /1/"-1.0 V

_H'l

V

-..,..." I---'

~

-l.S

10

(.llA)

2S0

~

-~.S

V

12.01v

o

O.S

o

10

Transconductance vs. Gate-Source Voltage
200

Vas (OFF) = -0.7 V
VOS = 10 V

Vas (OFF) = -0.7 V
Vos=10V
~lkHZ

........

....... ......
~

\.: "- L

o

"

o

~.

r - TA = -SSOC - f~I
I

gf.
(.I1S)

12SoC

~ ~bo...
........~
-o.S
Vas (V)

-1

o

Jr-'- TA = -SsoC

~ Llrl 2SOC
j'... ~ ) - 12S o C
~
"- .......
.......
~~
~
~

-

100

~2S0C

r-

20

Vos (V)

Transfer Characteristics

so ~

t-

2.0 V-

100

(.llA)

t-

-1.0 V

VOS (V)

10

-~.S

I

I.
Y

::£...

Vas - 0 V

..; ..--

o

\\'
-O.S

-1

Vas (V)

7-71

NT

ICrSiliconix

~ incorporated

TYPICAL CHARACTERISTICS

Transconductance vs. Gate-Source Voltage

Transfer Characteristics
300

500

VOS = 10 V
f = 1 kHz

VGS(OFF) = -2.5 V
Vos=10V

10
(JJA)

250

I ITA = -55°C

\

~

:.t

I

r....

I

ri- 25°C

gfs
(JI,S)

~;-1250C

,;:r= T A = -55°C

"' "";;.'k-:

'C\;:--,25°C

150

.......

........

~

'C ~

""lI

o

125 °C

.\

~

\..

"-~~

o

-2.5

o

-5

\~ r\

o

-2.5

On-Resistance vs. Drain Current
20

-5

V GS (V)

VGs(V)

~VGS(OFF)

Circuit Voltage Gain vs. Drain Current
100
Ay=~

= -0.7 V

-

1 + RLgos

AssumeVoo = 15V, VOS= 5V-

rOS
(Kn. )

-

V-

10

o

R L = 10 V

1I
Ay

L"

T A =25°C
0.01

I/

50

~

~VGS(OFF)

......

IflVGS(OFF) = -2.5 V
I I I IIII
III

III

= -0.7 V

I"

I
I

'"

VGS(OFF) = -2.5 V

~JIIII

o

0.1

0.01

0.1
10(mA)

10(mA)

Common-Source Input Capacitance
vs. Gate-Source Voltage

Common-Source Reverse Feedback
Capacitance vs. Gate-Source Voltage

2

0.5
f = 1 MHz

f = 1 MHz

"

t=

"- ~ 1-t...L

Clss

(pF)

o

o

\

Vos = 0 V
I

C rss
(pF) 0.25

1~IVosl= lL

-10
V GS (V)

7-72

I

1101 111111

.......

,-

~
\.
-

-

-20

o

o

"-

c--Vos = 0 V

:'1 I

::r
II....
_

I

.1-

Vo = 10V

-10
V GS (V)

-20

.-rSiliconix

~ im::crpcrated

NVA

N·Channel JFET
DESIGNED FOR:
•
•
•

Analog Swiches
Commutators
Choppers

PACKAGE

Single

TO-92

• J105, J106, J107

TO-52

• U290, U291

Chip

FEATURES
•
•

DEVICE

TYPE

Very Low Insertion Loss
rDS(on) < 3.0 .n (U290)
High Off-Isolation

• Available as above
specifications

GEOMETRY DIAGRAM

T

•

0.045

~I
I·
·1

Gate Is backside contact

7-73

NVA

.-r'Siliconix

.LII

incorporated

TYPICAL CHARACTERISTICS
On-Resistance & Drain Current
vs. Gate-Source Cutoff Voltage

On-Resistance vs. Drain Current

f--

less
"

.)\

J

'DS ' \

5

"-f'
i--'

o

......-~

o

I

TA = 25°C

res @ le= 10 rnA, V GS = 0 _
less@ Ves= 10 V, V GS = 0

\

res
(n.)

20

2K

10

~

I

IL

I ess
1 K (rnA)

/

res
(.0.) 10

-

'.,

J

o

o

-10

10

Forward Transconductance & Output
Conductance vs. Gate-Source Cutoff Voltage

On-Resistance vs. Temperature
30

/'

,

.",

g(/

/'

10

~

/ .gos
.'

15

gos
(mS)

res
(.0.)

VGS(OFF) = -5 V

')V

5

/"

./

V
-5

I J

I

/'
0

./

VGSiOFF) = -3;:"-

~

100

./

Ie = 10 rnA
res changes - 0.7%/oC

k-'"

./~

iI""

1000

100
Ie (rnA)

300

gfs 200
(mS)

.... ~

VGS(OFF) = -8 V

VGS(OFF) (V)

..",-

1/

/

-5

J

I ! .1.1

I I
J I

./

l/

,

V,..t!',,,,,r::.r::.\ = -3 V
....... '.....

. /1""-0.

gfs&gos@
Ves= 10 V, VGs= 0
f = 1 kHz ,

I

VGS(OFF) = -5 V

0
-10

o

,

.......

/
".,."..

V
./

,

V

.",

I

-15

i"'"

~

".,."..

ki';;'S(OFF) = -8 V

V

-55

,

~V

/

I'

I
85

r-125

VGS(OFF) (V)

Operating Gate Current

Output Characteristics (VGS(OFF) = -5 V)
500

r-"'T'"--r-T"""""T'......,r---r-....,...-""'''''''''...,

10 5
10 4
IG
(pA)

Ie
(rnA) 250 t-+-t~9---::I;;""'"1F-+-+-=p..."'F=--J

10 3
10 2
10

o
10
VeG (V)

7-74

20

o

5
Ves (V)

10

NVA

~Siliconix
incorporated

.LII

TYPICAL CHARACTERISTICS

Turn-On Switching
20

I--

Turn-Off Switching
20

I
I
I
.1
I
I
I
I
r- tr approximately Independent of 10

,

V oo =1.5V
RG= so.o.
VIN = -10 V
tr
t
(ns)

10

--

j"... to...

..... ......... r---..
I--

o

~

I

.......

td(ON) @
I-Ip = 0

1 rrt

o

td(ON) @
10 = 30 rnA

--

t

(ns)

10

~

,
-

o

-10

tf

~

"-

~ .........

td(OFF)

"

NGs= -3 V

I'.

........

-tGr-r

o

f@1

r--.J."""i-I
II

25

Capacitance vs. Gate-Source Voltage

Transconductance vs. Drain Current
=VoG -l0V
- f - 1 kHz

120

~

-TA = -SsoC

..... ~

f\c lss

60

I\,

C
(pF)

o

gfs
(mS)

'I'-..

/. ~

10

r-....

--

Vi

c,!ss

o

-10

10 (

-20

Output Conductance vs. Drain Current

,. ,.
25°C
en
(nV/VHz)

0.1

1

10
10 (mA)

=

=
-

~

VOG=10V
f = 1 kHz
VG,S(OrF)1= ,-~

..

Noise Voltage vs. Frequency
100

./ :::; ~25OC

100

10 (rnA)

10

r-T A = -SSx

= -5 V

~f(OfF)1 I I II

V GS (V)

gas
(mS)

2SoC

~ ~5°C

.........

~
30

SO

100

I.
I
I.
VOS = 0 V_
f = 1 MHz

90

1_ -

10 (rnA)

VGS(OFF) (V)

150

I I
I I

..... ~

I

-5

t d(OFF) Independent of
device VGS(OFF)
Voo = 1.S V
YIN = -10 V

~
100

10

V oG =10V
BW = 6 Hz @ f = 10 Hz, 100 Hz
= 0.2 f @ f l!: 1 kHz

I

-10 mA

1
0.01

0.1

10

100

f (kHz)

7-75

NVA

tcrSiliconix

.LII incorporated

TYPICAL CHARACTERISTICS

Transfer Characteristics

Output Characteristics (VGS(OFF) = -3 V)
100

SOO

I

I
VG

J

=y

\

. / '-~
10

(rnA)

/'

50

". "'-:-OJ..-

./'1/ '-O.~

"" .........
./ c,....' :,...-

10

(rnA)

2S0

~~~I:::--~

-1.2

j\'A = -SsoC

"I

"

12S~ ......

-1.4
1.6

o
0.25

,

'\
2S0~ '\

.2.-

~ --1 .

~ ~ ~ ...... ...- ~

o :.~--o

-

VOS=10V
,_
VGS(OFF) = -3 V

0.5

l"
.........

I""'---

o

Transfer Characteristics

0/

V

/
/
/ ./

50

/"

--

I.::;;..o

".

./'

/ C/ V
/~ V' k'
~/
I-

o

1000

JGS=I~ r/

10

....... ~

,.....

VOS = 10 V
VGS(OFF) = -S V-

~

-1.~

~.

-j;....

10

(rnA)

SOO

~ ~ = -55°C
ro.....

" r-...."

~C

-

-2!0

12S°C'

2!S

o

0.2S

O.S

~

r--.... ~

r--....

r- r-- ~ 110.

o

-2.5

Vos (V)

Output Characteristics (VGS(OFF) = -8 V)

Transfer Characteristics
2000

I

Vos=10V
._
VGS(OFF) = -8 V

VGs=OV'/

/V
10

./ ~ V

100

./ / '

l/':V "../'
~ """. ~ ....... ...:;...-

-- -

~~

o

7-76

Lit!.

o

~
-2.0

Vos (V)

~

10

.....-:r:
...:;-

-

(rnA) 1000

0.5

~ TA = -S5°C
\.
'\. \
25O~ I'\.
'-.1

)0

I
0.2S

-S.O

VGS (V)

200

(rnA)

-3

V GS (V)

Output Characteristics (VGS(OFF) = -S V)

(rnA)

I"

-l.S

Vos (V)

100

-~

o

~

,

c-~ ......... I'...
L I
~ !l!I...

o

"

-S
VGS (V)

-10

NZB

crSiliconix

~ incorporated

N·Channel JFET
DESIGNED FOR:
•
•
•
•

VHF/UHF Amplifers
Front End High Sensitivity Amplifiers
Oscillators
Mixers

PACKAGE

Single

TO-S2

• J30a, J30S, J310

SOT-23

• SST30a, SST30S,
SST31 0

TO-52

• U30a, U30S, U310

TO-7a

• U430, U431

FEATURES
•
•

DEVICE

TYPE

16 dB at 100 MHz, Common Gate
11 dB at 450 MHz, Common Gate

Dual

Chip

• Available as above
specifications

GEOMETRY DIAGRAM

•

.Q.,Qlll
(0.483)

0.019 - - - - + I
~.---- (0.483)
Gate also backside contact

7-77

.HSiliconix

NZB

incorporated

TYPICAL CHARACTERISTICS
Drain Current & Transconductance
vs. Gate-Source Cutoff Voltage

Operating Gate Current

100

50
gts @ Vos= 10 V. VGS = 0 V
-f=1kHz
_'oss@Vo s = 10 V. VGS = 0 V

1 0 5 _"'T""""T-T""""'T"--r-'T"""""""""-'T""""!!!!I

L

/

L

loss
(mA)

50

.......

~

gts

1-

~

:;...--

k--"
25

./

9ts
(mS)

./

10

./

loss

./

o

I

o

-2.5

o

-5

VGS(OFF) (V)

,

Common-Source Forward
Transconductance vs. Drain Current

On-Resistance & Output Conductance
vs. Gate-Source Cutoff Voltage
100

\

9 0s

....r
o

,.,1/

"-...... ~ "

-- -

o

150 9 s
(JJ,S )

9ts
(mS) 10

-

V'125°C

,...

..0- ~

o

-5

0.1

10
10 (mA)

Output Conductance

VB.

IIIII
rl~ I=I\"~A

V G= 10 V

r·,vOG=10V
f = 1 kHz
f-VGS(OFF)= -3 V

~

\

TA = -55°C

,

~

I'~

r-Io= 10 mA
11111111
I

II 11111
0.1

25 0

f (kHz)

7-78

I

90S 75
(JJ,S )

i'

0.01

Drain Current

150

II

o

'"

""""

;"/
o

Equivalent Input Noise Voltage vs. Frequency

en
10
(nVIVHi)

L.;

...-:: ,

VGS(OFF) (V)

20

,.....

~ V'

25~T...,...i'

-

ros

-2.5

'~A= _55°Y V

./

0

./

~

VGS(OFF) = -3 V

_VOG=10V
f = 1 kHz

-

"-

rOS
(.(1) 50

20

300

ros @ 10= 1 mA, V GS = 0 V _
90s@ Vos = 10 V, VGS= 0 V
f = 1 kHz

d

~

~

V L> y
:,....1010

100

o

~

~lfuoc
r-' I I I

0.1

10
io(mA)

H

NZB

Siliconix

incorporated

TYPICAL CHARACTERISTICS
Output Characteristics (VGS(OFF)= -1.5 V)

Output Characteristics (VGS(OFF)= -1.5 V)
15

V~S=~
./

/
10
(mA)

/

7.5

/

1/V
L V L .......
/. 0 V'
r-

~ ::...a

20

---

a

. . . . l~
'-oL
"~
'-a L

/
II
10
(mA)

1£

10

V
'1/

V

fjr,.--

J
1.0 V

10.2l

--

10-

1
1
-0.4 V

lO.6 ~

I-

I-O.~ V

, o.~

1

V S- 0 V
~~

o

0.5

~0.8

V

-1.0 V

L

~

o

1

5

10

Vos (V)

VOS (V)

Output Characteristics (V GS(OFF)= -3 V)

Output Characteristics (VGS(OFF) = -3 V)
50

V GS = 0 V

,

;"

/
10
(mA)

I

25

If.
'/

OV

..-

,

'0.4

a
0.5

11 . 2

..-

-2.0 V
-2.4 V

o

5

Transfer Characteristics

Transconductance

1

1

15

1 _I

'"

r-

, A = -~50CI

I'... ~

gfs
(mS)

"- "f <-~'\

25°C

15

~
-1
VGS(V)

-2

a

TA = -55°C

i'-.. K

125°C ......

"

o

VOS = 10 V
f = 1 kHz
VGS(OFF) = -1.5 V

I

I

. . . r--..., ~ ,,25°C

_125°~ ~
I I ~~
a

Gate-Source Voltage

VS.

30

VGS(OFF) = -1.5 V
VOs= 10 V _

~

10

Vos (V)

30

10
(mA)

V

16~-

Vos (V)

\

1

-0.8 V

~j.;""

a

~-=

a

~

"\.

~
~~

.'\ ~

-1

-2

VGS(V)

7-79

..

NZB

.rY"Siliconix

.LII incorporated

TYPICAL CHARACTERISTICS

Transconduotanoe

Transfer Characteristics
100

10
(mA)

so

I
I
I.
Vas (OFF) = -3 V
VOl = 10 V

so

~
gts
(mS)

2S

12soc

.......... ~~ ........

::::-;
- -12~ ~ ===Iii::

--

J J

o

,

'f

I I

"'1-2~
"'

~

o

-3

...... ~

"" t--...
....... ~
........

rOs
(.0.)

"~~
-3

-l.S

Circuit Voltage Gain
Av

--

V

VS.

Drain Current

=

gts RL
1 +RLgos

- ' - - AssumeVoo = lSV. Vos= SV

I
I

~- RL = 10V

""~

Av

---

I'-..

Vas (V)

I
L

so

!

I

~~

o

On-Resistance vs. Drain Current

I
I I
' - - Vas (OFF) = -l.S

.!

Vos=10V_
f = 1 kHz

TA = -SsoC

Vas (V)

TA = 2SoC

Gate-Souroe Voltage

.........

-l.S

100

VS.

,!

~

~

"N-I

o

,

r- Vas (OFF) = -3 V

-

~TA = -SsoC

,"

"

.i

SO

10

1--+-'pf::::k:J'
..... ~+---+J--41--4J-+II-I4I++1
1
1---I----l-f-l--H''IoI::F......:VaS(OFF) = -l.S V

~I

Vas (OFF) = -3 V

Vas (OFF) = -3 V

11I111

o
1

10

100

0.1

10

'o(mA)

'O{mA)

Common-Souroe Input Capacitance
vs. Gate-Source Voltage
lS
If =

~

Common-Sou roe Reverse Feedback
Capacitance vs. Gate-Source Voltage
10

MHlz-

,

f =11 MIHZ

\ Vos= 0 V
C's.
(pF)

7.S

I'I"-'

...:: r-

C rss
(pF)

- ....

S \,os = 0 V

"-

"" ........

IDS I S '

o

o

-10
Vas (V)

7-80

--

~

Vos = S V

-20

o

o

-10
Vas (V)

-20

NZB

.-rSiliconix

~ incorporated

TYPICAL CHARACTERISTICS

Forward Admittance

Input Admittance
100

100

I--

9ig

----

(mS)

--9Ig

........

10

10
(mS)

big

~

r=

TA 25°C
VOG 10 V
10 = 10 mA
Common-Gate

bIg

-----

TA - 25°C
:: VOG 10 V
10=10mA
'- Common-Gate

0.1

0.1

1K

100

100

FREQUENCY (MHz)

1K
FREQUENCY (MHz)

Reverse Admittance

Output Admittance

10

100

:: TA -25°C
-VOG-l0V
- 10 = 10 mA
- Common-Gate

TA - 25°C
VOG - 10 V
10 - 10 mA
Common-Gate

.... f-"

10
b rg
(mS)

0.1

~

...[+9r

-9rg

\
0.01

,

I

100

0.1
1K

FREQUENCY (MHz)

bog

...- ....-

(mS)

--

:,....f-"
90g=

......

100

1K
FREQUENCY (MHz)

7-81

NZF

ICrSiliconix

~ incorporatec

N·Channel JFET
DESIGNED FOR:
•
•
•

High Frequency Amplifiers
Mixers
Oscillators

TYPE

PACKAGE

Single

TO-92

• J210, J211, J212

TO-71

• U440, U441

TO-78

• 2N5911, 2N5912
U443, U444

Dual

FEATURES
•
•

High Power Gain
Low Noise

Chip

GEOMETRY DIAGRAM

0.019
(0.483)

,0.004
(0.102)

""1.----

0.019
(0.483)

----+1.1

Gate also backside contact

7-82

DEViCE

• Available as above
specifications for
J210, J211, J212,
U440, U441 , U443,
U444, and 2N5912

NZF

fCrSiliconix

~ incorporated

TYPICAL CHARACTERISTICS
Drain Current & Transconductance
vs. Gate-Source Cutoff Voltage

Operating Gate Current

50

20
VOS = 10 V. V GS = 0 V
f = 1 kHz
10ss@Vos = 10 V. V GS = 0 V

,

loss
(mA)

II
i.V

25

t--

gfs

./

10 gfs
(mS)

. /~

/

IG
(pA) 10

2E-~~~;t;;~tt;;t;~~~~~

106-+--+-

l-llosV

,

o

o

-10

-5

o

0.1 L-..I-..J.--JI..-...I-...J.....;.,:..:.....................J.--I
o
10
20

VGS(OFF) (V)

VOG (V)

Common-Source Forward
Transconductance vs. Drain Current

On-Resistance & Output Conductance
vs. Gate-Source Cutoff Voltage
200

\

10

I/'

rOS
(.0.) 100

J-'-I

V oG =10V
f = 1 kHz
VGS(OFF) = -5 V

/gos

\

II I I

/
\

IA
j

.......... ~

o

\.... ~ ~
0

25°C-

ros

125°C -

r-

rOS@ 10 = 1 mAo V GS = 0 V
gos@ Vos = 10 V. V GS = 0 V
f = 1 kHz

I

......:: ~~

TA = -55°C

gfs
(mS) 5

I
o

200

V

-5

~

o
-10

~

.......
:;::;....

~

o '?'
0.1

10

VGS(OFF) (V)

10 (mA)

Equivalent Input Noise Voltage vs. Frequency
50

Output Conductance vs. Drain Current
150

VOG= 10 V

•

II

VOG =10V
f=lkHz
II
VGS(OFF)= -5 V

Y 'I II
en

25

(nV/VHz)

\ 1\

I

I

II

10= 1 mA

gos 75
(JJ.S)

I

25°C
125°C -

;.-10=10mA
1/

o

0.01

-

~ j::::r;.

r--i(l I'
I
0.1

10
f (kHz)

100

lI.

TA = -55°C

o~
0.1

1\';

h

/. ~!;'

~

~~

rr

10
10(mAI

7-83

NZF

..rSiliconix

~ incorporated

TYPICAL CHARACTERISTICS

Output Characteristics (VGS(OFF) = -2 V )

s

10

VV

'/
v: ~ .,..

2.S

~

/1
/-04::'.",.

......-r

I~ ~ .....

~~k""'-~
""': ....o

I

-o.~

"1111111
!vGS-:..10
(rnA)

5

-r

~ ~ ' / -~ I-"

o

q1

V~S~
I
I

V

(rnA)

Output Characteristics (VGS(OFF) = -2 V )

-O.B V

V

-0.2 V-

V

-0.4 V

i.-"""

-0.6 V
O.B V

-1.0 V

1.0 V

IJ

-1.2 V

I

I

o

O.S

1.2 V

o

5

10

Vos (V)

VOS (V)

Output Characteristics (VGS(OFF) = -S V )

Output Characteristics (V GS (OFF) = -5 V )
30

-

10

(rnA)

10

7.5

(rnA)

I

VGS= 0 V -

,V

/~

I

Z~

-2.0

~

o

o

'I

~

Transfer Characteristics

I

~
10
(rnA)

5

I I
5

H T A = -5S0C

~

9fs

(mS)

~

5

7

r.- - 25°C
........ ~ 6.. Ie 125°C
........
'<- ~
I"": ~
~

VGS (V)

7-84

Transconductance vs. Gate-Source Voltage

,L-j-- 25°C

-1

10

10

I

~K: r1-125°C

o

-3.5 V

o

--+--r~--+--r~

I

-3.0 V

Vos (V)

r----......
----,..-..,.........,..-,......,.....,
VGS(OFF) = -2 V
Vos=10V

-2.5 V

;..-

VOS (V)

10

~'-

t'~ I-"

1. ~

I

-1.0 V-.::::=.
I
I
-l.SV-

/ / .-1',/

15

I

-O.S V-

-2

o

Vos=10V
f = 1 kHz
VGS(OFF) = -2 V

o

""

-1
V GS (V)

"" 1\""
~~

~
-2

g

NZF

Siliconix

im::orporated

TYPICAL CHARACTERISTICS

Transfer Characteristics

Transconductance vs. Gate-Source Voltage

30 ~

"

\

rt-

.rJ-T A = -SSOC

T A = -55°C

,,r,-r-10
(mA)

I'\t<\
......"c'IoC\..---i-I-l-+-+-I

15 1--+-~...r"

gl.
(mS)

~~

_~aS(OFF) = -5 V -l--I-~-I""""+--I---I

Vos= 10V
"IIiI~
0L-..J-.....J._l.-..J-.....J._L..-..J.-...J.:I1IiIW-.J
-2.5
-5
o

o

-VaS(OFF) = -5 V
_Vos=10V
f = 1 kHz

o

Circuit Voltage Gain vs. Drain Current

/I

Vas (OFF) = -2 V

I"-

.......... ~.....

-

100

Av

II

II HI
II III

Av=~

T A =25°C

o
100

RL = 10V
10

I I

c--.,

~

1'""

III

II II
10
10(mA)

Common-Source Input Capacitance
vs. Gate-Source Voltage

Common-Source Reverse Feedback
Capacitance vs. Gate-Source Voltage

10

5
f = 1 MHz

~

f = 1 MHz

t: r-- -

Vos = 0 V

~ ~W
.r-

- Vos = 5 V

C rss
(pF)

-Vos= 10V

2.5

o

-10
Vas (V)

~

'"
r--

I".

o

~

0.1

10(mA)

5

Vas (OFF) = -2 V

............
1 +RLg o•
Assume Voo = 15 V. Vos = 5 V

10

C jss
(pF)

"

VGS(OFF) = -5 V

<.;/
~

25

Vas (OFF) -5 V
I I 111I1I

o

-5

50

JIll III

ros

\ \

Vas (V)

XIIIIIII

(.0. )

~"

-2.5

On-Resistance vs. Drain Current

~

1,,\

--11-+-I-+-W,,-l

L--'-.....J.__~~~__~~~L..-UL~

Vas (V)

200

25°C

-20

o

o

i--Vos= 0 V
r= r--

tty
t--(f6

r--- Vos = 5 V
~

-

-Vos= 10V

'--

-10

-20

Vas IV)

7-85

NZF

ICrSiliconix

~ incorporated

TYPICAL. CHARACTERISTICS

Forward Admittance

Input Admittance
100

100

TA = 25°C
V DS = 10 V
ID=10mA

TA - 25°C
V DS - 10 V
I D - 10 mA
10

bls

~

"!:

10

-

-

......

mS

......

E gig

.,

mS

.".

f=

-bfs ...

f--'"

bfg _

~

-

~fs 1~1
-gfg

/.

J.,

gls
.".

0.1

0.1

1K

100

100

1K

f (MHz)

f (MHz)

Output Admittance

Reverse Admittance
10

100

TA - 25°C

TA - 25°C

V DS - 10 V
ID=10mA
-brs

...

......

-

-~ "'~grs

t

0.01

mS

.'

==

rg, \ I

I

0.1

1K
f (MHz)

bOg,bo

~

grg

......

Z

-

/

100

7-86

I

:;:;~
10

mS
0.1

V Ds -l0V
I D = 10 mA

--

gog, gos

~I
100

i-"

f (MHz)

1K

PSCIA

~SilicDnix

~ incorporated

P-Channel JFET
DESIGNED FOR:
•
•
•
•

Analog Switches
Commutators
Choppers
Integrator Reset Switch

TYPE

PACKAGE

Single

TO-92

• J174, J175, J176,
Jl77
J270, J27l
Pl086, Pl087

SOT-23

• SST174, SST175,
SST176, S8T177
88T270, 88T27l

TO-18

• 2N5ll4, 2N5ll5,
2N5ll6 (TX, TXV)

Chip

• Available as above
specifications

FEATURES
o

o
"

Low Insertion Loss in Switching Systems
rDS(on) < 75 .n (2N5ll4)
Short Sample and Hold Aperture Time
C rss < 7 pF
High Off-Isolation I D(OFF) < 500 pA

SWITCHING CIRCUIT

DEVICE

GEOMETRY DIAGRAM

T

0.004
(0.102)

~

:·S···

~

~

_
_
1
0.02
(0.53 3)

G·
.'.

OUT

:.~··i

~1·

1•

____

T

0.004

(Or 2 )

.I]
0.021
(0.533)

----.,.1

Gate backside contact

7-87

PSCIA

fCrSiliconix

~ incorporated

TYPICAL CHARACTERISTICS
On-Resistance & Drain Current
vs. Gate-Source Cutoff Voltage

rOS
(.0. )

On-Resistance VS. Drain Current

'" Ikill II ttl
\..

100

"-

/

o

-50 loss
(mA)

--

><

V
/

r'oo

,

I'

rnJili
tti

-1

15

/'

/

12
gt.
(mS)

6

3

I

On-Resistance VS. Temperature

/

10=-1 mA
ros changes - 0.7%/oC

'"

200

.!

./

150
gas
(JJS)

V

I .1,

..,..V

ros 150
(.0.)

./'

100

./
gf.&go.@
Vos= -15 V. VGS= 0

f = 1,kHZ,

I

f-- c-- VGS(OFF) = 1.5 V

/
I

II V
o

-

-100

300

90.

/

/

9

....

T A =25°C
-10
10 (mA)

Forward Transconductance & Output
Conductance VS. Gate-Source Cutoff Voltage
18
250

,,-

~

i--""

I I III

o

o

VGS(OFF) (V)

tgf.

-

I I I II

VGS(OFF) = 5.0 V

10

~

V

VGS(OFF) - 3.0 V

50

5

1111111111

~IIII

ros
(.0.)
100

ros@ 10= -1 mAo V GS = 0
loss@ Vos= -15 V. VGS = 0

o

::

, , ,

5

-

50

o

10

I,...-

o
-55

."

........ ........

---

. /~

VGS(OFF) = 3.0 V

-- ,- - ,--.- ~

~

~

~VGS(OFF) = 5.0 V
(

"

-15

85

125

VGS(OFF) (V)

Operating Gate Current

Output Characteristics (VGS(OFF) = 3 V)
-25

.I.

I .!

yGSIO~-

,,,- ,,-

-20

-15
10
(mA)
-10

IG
(pA)

I .,.-

'//

o
-25
VOG (V)

7-88

-50

I I

~

.o

J

,I.

I

V GS

= 2.0 V

yGSI1.~ V

'1

-5

o

I

V GS = 1.0 V

10

0.1

I I I
VGs =0.5V

J J J
-10
Vos (V)

-20

.r-Siliconix

PSCIA

~ incorporated

TYPICAL CHARACTERISTICS

Transfer Characteristics

Output Characteristics (VGS(OFF) = 1.5 V)

,,

-2

-10
/I/'VGs=OV

V-

['

1/

'/
r- Vas = 0.4 V--I-

III /
ID

(mA)

-1

,
/)

o

l

I

~A = -55°C

I

VG,s=ri-

V

IJ /
II V / '

'1l , /

V",p, = 0.6 V

--

r

"./

V

o

ID

(mA)

-5

~

r-

250C

1~

Vas = 0.6 V

o

-0.5

'\

~

j,.-

-1.0

""'- .""""
, .........
......

V Ds =-15V
Vas (OFF) = 1.5 V

o

II

Transfer Characteristics

ID

(mA)

II I
f/I /

Vas = 0.5 V

/

Vas=1.0V
t \ TA =-55,C

V

III

-1

V Ds =-15V
VGS(OFF) = 3 V I-

..tI' I I

LL

I /
II 1/

.......

VV as =1.5V

Y--r

ArL 0' I
i
J'. '/....... '"
'las

o~
o

~~

ID

(mA)

-20

"~1250C

\.

J

~

.......

I

2 .O V

1'0..

125°C

o

-0.25

-0.5

o

~

i'.: ~

I

,

L

/

Vas

ID

-1

"I /

JI}
/) /
~/
o

Vas

/I I /
Vas = 3 V
'/I

I

1V

'\

,,/"

........-

ID

(mA)

"- .........

-40

""25°C

"'125':?- ......

4 V

K

/'

J

;..'

o

-0.25
V DS (V)

VDS = -15
VaS(OFF) = 5 V l -

I I

TA = -55°C

2V

Y
....... VVas=

vJ

OV

Vas

/,

(mA)

Transfer Characteristics
-60

I'

5.0

Vas (V)

Output Characteristics (V GS (OFF) = 5 V)

L

~~
2.5

V DS (V)

-2

1.0

-40

A

V

II'

~

Vas (V)

Output Characteristics (VaS(OFF) = 3 V)
Vas = 0 V

~

........ ""~~
..... ~

0.5

V DS (V)

-2

.....

........

-0.5

o

o

"- i'..
...... r---.,:

-r-

tro.....

....... ~
~

2.5

~~
5.0

Vas (V)

7-89

•

~SilicDnix

PSCIA

~ incorporated

TYPICAL CHARACTERISTICS

Turn-On Switching
50
_

I t I @I
ON
10 = 10 mA

- r-

_""l
10 = 5 mA

t

(ns)

25

...

.........

....

L

1-'

......

~

:-...... ..............

(ns)

f'

.........

.............. ...... .........

~'"

10

-i"""--

voo~-ldv

o

5.0

I-

~IN _~ 0 t110~

o

-3

~

......

~I"

- - :--

Vas- 5.0 V

.......

2.5

~

td(OFF) @

Vaf=\~

I l-l

......I--

o

t~

@ '"
V as =1.5V-

t

"-

t.....

t, @
10 = 5 mA
t, approximate
10 Independent

Independent of
L~ I'\..td(OFF)
device Vas (OFF)

LVas= 5.0V- ~

") t...... ~

o

-

Voo= -10 V
Ra = 220.0.
V,N = 10 to 0 V-

......

tnl\l@

-"

Turn-Off Switching
20

-6

-9

-12

-15

10 (mA)

Vas (OFF) (V)

Capacitance vs. Gate-Source Voltage

Transconductance VB. Drain Current

30
f = 1 MHz
100

1 1 .' '.

~l~~r]I~~~~~11
Voa= -15 V
f = 1 kHz

tc1sS@vos=ov

\
C
(pF)

I\.

15

...... r-.,

gfs
(mS)

"

.........

1"'--0.
-

o

--

I-

c'ss@ Vos = 0 V

I

I

T

o

I

10

-1

-0.1

20

Vas (V)

Output Conductance vs. Drain Current
100

Voa= -15 V
f - 1 kHz

-10

10 (mA)

Noise Voltage vs. Frequency

100
TA -

55°C

Ip

0.1 mA

i"o..

V

90S

,,- ~ i-"~
"

10

(;1.5)

1"-

.....-:0

V ./
~25°C

25°C

-Ip = -1

!"
mA
...... 1--

en

10

(nV/VHz)

.....
Voa= -10 V
V

1
-0.1

1S (OtF)1 -3V
-I I I I

-1
10 (mA)

7-90

-10

_ BW = 6 Hz @ f = 10 Hz, 100 Hz
= 0.2 f @ f :i!: 1 kHz

111111111
0.01

0.1

111111111
1
f (kHz)

1111111111
10

100

PSCIB

~Siliconix

~ incorporated

P-Channel JFET
DESIGNED FOR:
•
•
•
•

Amplifers
Sample and Hold
Choppers
Analog Switches

TYPE

PACKAGE

Single

TO-92

Chip

FEATURES
•
•

DEVICE

• 2N5460, 2N5461,
2N5462, 2N5463,
2N5464, 2N5465
• Available as above
specifications

Lowen < 15 nVNHz at 10 kHz
Low Leakage < 10 pA at 30 V

GEOMETRY DIAGRAM

T

0.004
(0.102)

1

s·

~l?

•

0.021
(0.533)

I
: D·:

0.004
(0.102)

0.021 ----~.I
~4---- (0.533)
Gate backside contact

7-91

H

PSCIB

Siliconix

incorporated

TYPICAL CHARACTERISTICS
Drain Current & Transconductance
vs. Gate-Source Cutoff Voltage

Operating Gate Current
10 5 .........,......,,................_.,........,.._,.......,......,....,,,

5

-20
gls@ V DS = -15 V, VGS = 0 V, f = 1 kHz
IDSS@VDS= -15 V
j
VGS = 0 V

V

V

2.5

gls
(mS)

1/
/

o

/

/

g~s

6-+--1,--+-+-+--+-1-+-1-..1

/

I'

I DSS -10
(mA)

10 4

/~ 17

10

I DSS

V
o

5

10

10-1~~~_~~_~~_~~~~

o

o

-25

Common-Source Forward
Transconductance vs. Drain Current

On-Resistance & Output Conductance
vs. Gate-Source Cutoff Voltage

,

1000

J

100

I

I\..

,..

"-.i

V

"

/
..........

I

I I

--

gos
50 gos
()J.5 )

-

-:;::;

gos@ V DS = -15 V
VGS = 0 V
f = 1 kHz

5

o

0.1

10

25°C

-10

ID(mA)

Output Conductance vs. Drain Current
20

-15 V

JJ

VGS(OFF) = 3 V
V DG = -15 V
f= 1 kHi
I D ,:',,-O.l

...

"

,,~

-1

-0.1

Equivalent Input Noise Voltage vs. Frequency

~5~o C
I

gos 10
(.uS)

1 mA

ID

I 'III
/V

LJJ

t - - -T~!

mA

II 11111

en 10
(nV/ViiZ)

A'

125°C

100

t--..

/

""I)
i-'

~

gls 1
(mS)

VGS(OFF) (V)

VDG

./

t - - - TA = -55°C

I

\

o

VGS(OFF) = 3 V
VDG -15 V
f - 1 kHz

II
J

rDS\

o

10

rDS @ ID = -100.llA, VGS = 0 V

/

-50

V DG (V)

VGS(OFF) (V)

/

/J

//)

//

25°C

~

V ...... ~k
~

1
0.01

10

0.1
f (kHz)

7-92

100

o

-0.1

"

mlOC
-1
ID(mA)

-10

PSCIB

fllJIrSiliconix

JLE) incorporated
TYPICAL CHARACTERISTICS

Output Characteristics (V GS (OFF) = 1 .5 V)

Output Characteristics (VGS(OFF) = 1.5 V)
-0.5
VGS =

0.2 V

av / V

V

/ lL i-'
/
'
[/
/lJ
V
VJ.:

j}, ~

l...-

a P

. /n
O'SI V

-

--

--

a

/

1/

0.8 V

I---

/,V

V GS

/04V

I /
V
'If 'If V
1// / )~

rl

'0
(mA)-O.25

-2

-0.5

'/

-1

/'

'J

1.0 V_

I

OV

~.2 t-

",.,

-

-

'0.4

hsv
. '0.8

,,-

1.21 V

a

-1

I I

~

a

-10

-20

Vos (V)

Output Characteristics (VGS(OFF) = 3 V)

Output Characteristics (V GS(OFF) = 3 V)

r-..,---r-,---,.......,--r---r-Y--......,...,

-10

V GS =

-5

-1

..... 10"

'I'
~

[...--

l
III
".V
a

-0.5

a

-1

1.0 V
1.5 V
2.0 V

Y

a

-10

-20

Vos (V)

Transfer Characteristics
I- V~s =1_15 I V

aV

o.~ V

-

Vos (V)

-5

~-

1.0 V-

Vos (V)

-2

~-

Transconductance VS. Gate-Souroe Voltage

5
VOS = -15 V
VGS(OFF)= 1.5 V
f = 1 kHz

I

VGS(OFF)= 1.5 V

IfII

TA = -55°C

10

(mA) -2.5

r

gts
(mS)

TA = -55°C

I\.

2.5

125°C

i'.. i'..
i"'-....

"" "

~~

I-i--...
I-

~

25°C

125~ ~ ~

a

a

.......

I

a
2

a

r----.

,

r-..... .....r--...

...... f'
.......

I\.

1'...'\
~

~
2

7-93

PSCIB

~Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Transconductance vs. Gate-Source Voltage

Transfer Characteristics

5

-10
Vo s =-15V
r-YGS(OFF)= 3 V

4

10
(mA)

N
,

I

I

3

I

gf.
(mS)

r\A = _550,

-5

I, ~

125°C:,

2

25°C

'\:

o

"

-

1\

....

VOS = -15 V
VGS(OFF)= 3 V
f = 1 kHz

~=-55jC

" I~

i"" i'oo"

25°C

'\
r-..... I, I'\.

125°C

f'.. 1\.'
i\.. ~

&..

..... ~ lilt..

o

2.5

o

5

~

o

2

VGs(V)

i

VGS(OFF) = 1.5 V
rOS
(.0.)

/

!;:' t-...

J

t-

3V

./

AV

1/

50

VGS(OFF) = 1.5 Y

3.0 V

I

I I

~
~

IS:

1 + RLgos

RL = 10V
-1

Io

o

-10

-0.01

JllJlJ
l1lll

Common-Source Input Capacitance
vs. Gate-Source Voltage

Common-Source Reverse Feedback
Capacitance VS. Gate-Source Voltage

-1

5
f = 1 MHz

\-5 V

C rss
(pF)

5

2.5

~5V

"~ i'o..

"

15 V

I
o

-15 V
10
V GS (V)

7-94

r-

-0.1
10(mA)

f = 1 MHz

o

1 1

10(mA)

10

Clss
(pF)

~

Assume Voo = 15 V, Vos = 5 \":
V ~r-

4V

-0.1

II III

Av=~

..... 1/
o

5

I'.

I

V

500

4

Circuit Voltage Gain vs. Drain Current
100

II
V

j

TA = 25°C

3
VGs(V)

On-Resistance vs. Drain Current
1000

I I I,

-

20

o

ro

1 J
10
V GS (V)

20

VDDQ20

~Siliconix

~ im::orporated

N-Channel Depletion-Mode MOSFET
DESIGNED FOR:
o
•

Switching
Amplification

FEATURES
•
•

High Breakdown Voltage> 200 V
Low rOS(on) < 3 n

TYPE

PACKAGE

DEVICE

Single

TO-206AC

• ND2012E, ND2020E

TO-92

• ND2012L, ND2020L

Chip

• Available as above
specifications

GEOMETRY DIAGRAM

Gate Pad

0.010
(0.254)
0.0087
(0.2209)

Source Pad
0.0070
(0.1778)
0.010
(0.254)

T
1

•

0.038
(0.965)

7-95

.-r-Siliconix

VDDQ20

~ incorporated

TYPICAL CHARACTERISTICS
On-Resistance & Drain Current
vs. Gate-Source Cutoff Voltage

On-Resistance vs. Drain Current

25 r---~-----r----~----r----,1000

::I~~tfIIIIIIV II ~IIIII

ros @ 10 = 20 rnA, V GS = 0 V
20 I----If\o loss @ Vos =7.5 V, V GS =0 V 800

ros
(.0. )

15

600 10
(rnA)

15

(.0.)

10 ~---4----~~~~----~--~400

10

200

5

5

ND2020

rOS

10

100

Body-Drain Leakage Current

On-Resistance vs. Junction Temperature
2.25

,

10 V
25°C
l

ND2020

losv
(nA) 10

V GS = 0 V
10 = 20 rnA

2.00

,

1.75
ros

,ND2012

,,/

.--V

0.75

10-2
0

-1

-2
-3
V GS (V)

-4

0.50

-5

-50

Output Characteristics (ND2020)

-10

70

110

V S

j

I
I
II

120

60
10
(rnA)

40

1.
/I

80
TJ

20

40

0

o

0.4

0.8
1.2
Vos (V)

1.6

150

r

=10 V

160

80

7-96

30

Transfer Characteristics (ND2020)
200

100

0

./

/

(Norm.) 1.25

10-1

V

/

1.50

1.00

10
(rnA)

1K

10(mA)

VGS(OFF) (V)

TJ

ND2012

o

0 ~--~~--~~~----------~o
-5
-2
-3
-4
0
-1

I: Vos -

111

YI

2

-4.5

= 125°C r-- VII
25°C~'(

~

-3.5

WC

-2.5
-1.5
V GS (V)

-

-0.5

I--

0.5

.HSiliconix

VDDQ20

incorporated

TYPICAL CHARACTERISTICS

Transfer Characteristics (ND2012)

Output Characteristics (ND2012)

500~--~----~----------~~~

VOS = 10 V
BO-r----~~~~--~Y-----~----;

400r-----r_----r_----r_--~~~__i

60r----;~~~-----+----~~--;

300r----;-----+-----+--~Yr----;

ID
(rnA)

40r--.~~--~~~-+-----r----;

10
(rnA)

200~----r_----r_----~~--+_--__i

100r-----r_----r_~~r_----+_--__i

OL-__

O.B

0.4

1.2

1.6

-4.5

2

~~~~

-3.5

V DS (V)

Effects cf Drive Resistance
100

Voo - 25 V
V GS = 0 to -5 V
RL - 1250n

=== Ftdlon)

~~

10

~

tdloll)

"'~ I<

t

(ns)

1
20

50

10

1

100

1

Capacitance
V GS = -5 V
f = 1 MHz

V S

,=

300

40
20

o

100

=

5V

400

BO
60

tl'

Equivalent Input Noise Voltage vs. Frequency
500

100

C
(pF)

0.5

tr

10
10 (rnA)

RG (n)

120

~

I

tdloll)

10

__

Voo - 25 V
VGs= 0 to -5 V
RG= 25 n

"

t,
t

~

-0.5

Effects on Load Conditions

100

(ns)

___L____

-2.5
-1.5
V GS (V)

~

en
(nV/VHz)
200

\
100

Coss

C rss

o

10

lOrnA

20
30
V DS (V)

40

50

o

4t

10

100

1K

10 K

f (Hz)

7-97

.-:r'Siliconix

VDDQ20

~ incorporated

TYPICAL CHARACTERISTICS
Output Conductance vs. Drain Current

Forward Transconductance vs. Drain Current
700

350
VOS = 7.5 V
T J = 25°C
Pulse Test
80).Ls, 1 % Duty Cycle

300

600

j

250
gFS
(mS)

7

I

gos 400
().LS)
300

150
100

I

500

II

200

VOS = 7.5 V
T J = 25°C
Pulse Test
80 ).LS, 1% Duty Cycle

200

)~

50

100

o 1,....--1-"

~

0
100

10

1

1K

10

100

1K

10 (mA)

10 (mA)

Normalized Effective Transient Thermal Impedance, Junctlon-to-Amblent (TO-92)

Duty Cycle - 0.5

0.2
R thJA
(Norm.)

....

0.1
0.1

-0.05

~

Notes:

-0.0

tt~

..r.
::/\

\

1. Duty Factor, D

0.01

r

= ~~

2. Per Unit Base = R thJA = 156 ° C/W
3. TJM - TA =POMZthJA(t)

Single Pulse
0.01

~

I I I

10
100
Square Wave Pulse Duration (sec)

0.1

1K

10 K

Transient Thermal Response (TO-20SAC)
D - 0.5

0.2
RthJC
(Norm.)

0.1

0.1

--Sji;
I-

,..-

iii"

......, :ijjII

~i"'"

~~

Notes:

0.05

tt~

0.02_
~I,..oo

1. Duty Factor, D

~IO.Ol

0.1

10

100

t, (ms)

7-98

= ~~

2. Per Unit Base = RthJC = 83°C/W
3. TJM - Tc =POMZthJC(t)

Slngr Pt,11
0.01

~

1K

10 K

VDDV24

..rSiliconix

~ incorporated

N-Channel Depletion-Mode MOSFET
DESIGNED FOR:
•
•

Switching
Amplification

TYPE

PACKAGE

Single

TO-205AD

• ND2406B, ND2410B

TO-92

• ND2406L, ND2410L

Chip

• Available as above
specifications

FEATURES
•
•

High Breakdown> 240 V
LowrOS(on)<10n

DEVICE

GEOMETRY DIAGRAM

Gate Pad
~
(0.127) 0.007
(0.178)

•••••
i....
.......
••••••••••••••••••••
....................
....................
••••••••••••••••••••
.....................
....
................
....................
.............
......
.•••••••
......
••••••

..

•••••
•••••

....... 1
i •••••••••••••••••••

. . . . . . . . . . . . . . . . 11 •••

Source Pad
0.006
(0.152)
0.007
(0.178)

0.058
(1.47)

•••• 'u ............ u

"1111"

•••••••

1~.~~~0~.05~3~~~.1
(1.35)

7-99

~Siliconix

VDDV24

~ incorporatec

TYPICAL CHARACTERISTICS
On-Resistance & Drain Current
vs. Gate-Source Cutoff Voltage

On-Resistance VS. Drain Current
1000

rOS
(.0. )

B~4r-+----~---4----~---1

BOO

6 1----'\-1--1'-+

600

4 ~---+~::--+

::I~;~trllllllllllllll~1
10
(mA)

ros
(.0. )

-1

__

~

____

-2

~

____

-3

~

____

-4

~

__

-5

~

J

5

o

0

-6

10

100
10 (mA)

1K

On-Resistance vs. Junction Temperature

Bcdy-Drain Leakage Current
10 4

2.25
EVoS -l0V
TJ - 25°C

V GS = 0 V
10 = 30 mA

2.00
1.75

10 2
losv
(nA) 10

ND2406

l/

VGS(OFF) (V)

10 3

II
II

ND2410
10

400

2~--~----+---~----~---1 200

O~

10

rOS

i===1

ND2410

./

1.50

(Norm.) 1.25

1·

, ND2406

=I
1.00

"

10"

-1

-2

"
-3

0.75

-4

0.50

-5

--

-50

./
.,/
~

-10

30

70

110

150

V GS (V)

Output Characteristics (ND2410)

Transfer Characteristics (ND2410)
500

VOS

=10 V

VI

400

160

I
I
I

300
10
(mA)

10
(mA)

~

200
TJ

= 125°CJj

25°C-401-~~~~~-+--+-+-

100

o

-4.5
VOS (V)

7-100

'f/I -SSOC

A, If
~
-3.5

-2.5
-1.5
VGS (V)

-0.5

0.5

VDDV24

ICrSiliconix

~ im::crpcrated

TYPICAL CHARACTERISTICS

Output Characteristics (ND2406)

Transfer Characteristics (ND2406)
500r---~-----r----~--~r----'

VOS=10V
400r-----r_----r_----r_-.~r_--~

10
(mA)

10
(mA)

200r---~r---~----_.----_r----4
100r---~r---~--~~----_r----4

O~--~--~~--~----~

0.8

0.4

1.2
Vos (V)

1.6

-4.5

2

-3.5

Effects of Drive Resistance

l~

300
tr

............

(ns)

100

td l ott~-

tr

j"'-......,

10

~

0.5

Voo = 25 V
Vas = a to -5 V
Ra= 25.n.

it
td(ott

tf

t

__

-0.5

Effects on Load Conditions

100

.............td(On)

-2.5
-1.5
Vas (V)

"

t

"--

(ns)

10

-

_ td(on)

1

2

"

I'\.
i'~

Voo = 25 V
Vas = 0 to -5 V
10 = 30 mA

1
10

20

50

3

100

Capacitance
100

Vas = -5 V
f = 1 MHz

80
40

o

is

80

~

10

~

120

60
en
(nV/VHz)

~CISS

40

~OSS
10

100

40

50

a

~ ~IJ"II

I IIIII

! 110 I~A' I

\

1"--'
1 m'Alll.

20

20
30
Vos (V)

50

~

r-....

I'--r-.

C rss

o

I

V

200

C
(pF)

10
20
10 (mA)

Equivalent Input Noise Voltage vs. Frequency

240

160

5

10

100

-~
1K

10 K

f (Hz)

7-101

.-rSiliconix
.z:.
incorporated

VDDV24
TYPICAL CHARACTERISTICS

Output Conductance vs. Drain Current

Transconductance
350

2

250

rp50 0 C

II

250
gFS
(mS)

HrFII

VOS = 10 V
Pulse Test
80)Ls, 1% Duty Cycle

300

300

-55°C
gos
()LS)

.I.~
~~

100
50

150
100
SO

o -.-

0
10

1

I

200

200
150

I

Vos = 10 V, TJ =25°C
Pulse Test
80)Ls, 1% Duty Cycle

100

1K

-

,.,
10

10 (mA)

100

1K

'o(mA)

Normalized Effective Transient Thermal Impedance, Junctlon-to-Amblent (TO-92)

Duty Cycle

0.5

0.2
0.1
RthJA
1(i.05
(Norm.) 0.1
-0.0

"...

Notes:

-tt~

,L'JI'

r;.."\

2. Per Unit Base = R thJA = 156°C/W
3. TJM - TA = POMZthJA(t)

Sinr'e jUliel
0.01

0.1

!~

1. Duty Factor, D =

0.01

}

3nSL

O.S

S
10
SO
100
Square Wave Pulse Duration (sec)

SOO

SK

1K

10 K

Transient Thermal Response (TO-205AD)

D - O.S

--

0.2
R thJC
(Norm.) 0.1

....,

~~

~ f- -~

-

~O.OS

Notes:

Single Pulse

3nSL
-tt~

0.02

I - - 0.01

1. Duty Factor, D =

-r;
t

2. Per Unit Base = R thJC = 2soC/W
3. TJM - Tc = POMZthJC(t)
0.01

7-102

0.1

O.S

S
10
SO
100
Square Wave Pulse Duration (sec)

SOO

1K

SK

10 K

g

VNDB24

Siliconix

incorporated

N·Channel Enhancement·Mode MOSFET
DESIGNED FOR:
o
.,

Switching
Amplification

FEATURES
o
•

High Breakdown> 240 V
Low rDS(on) < 6 n

TYPE

PACKAGE

Single

TO-205AD

DEVICE

• VN1706B, VN2406B

TO-220

GI

VN1706D, VN2406D

TO-92

101

VN1706L, VN2406L

TO-237

Chip

• VN1706M, VN1710M,
VN2406M
o Available as above
specifications

GEOMETRY DIAGRAM

0.008
(0.203)

t
7-103

VNDB24

..rSiliconix

~ incorporated

TYPICAL CHARACTERISTICS
Ohmic Region Characteristics

Output Characteristics

2.0

1.6

f

~

I

5V

I

0.8

0.8

,/
4V

L

0.6

o

20

40
60
Vos (V)

80

r-

~
o

~

160

VGS - 3 V j

I

TJ=25°C

/V

120

II. ~ ""

80

VI

40

2

o

~J

0.4

11/

0.3
(A)

2.2 V
-'2.0

J

0.2

~

I~
V

0.1

I

I

0.8
1.2
Vos (V)

o
1.6

2.0

o

~

2

---

V

10.0
VGS
(V)

V S = 120 V
7.5
5.0
2.5

7-104

o
0.1

0.2

0.3
10 (A)

0.4

0.5

1"

12.5

2

o

5

Gate Charge

10=0.5A

3

o

4

15.0

I
VGs =10V

4

rOS

3

VGS (V)

5

(.0. )

b

10

On-Resistance

6

5

250C
125 0

Vos=15V

I I
I I

11.8t"

0.4

4

t1l

= -55!C

I

./'2.4 V

IF'

3

Transfer Characteristics

0.5

-I J-

.4 V

2.L

VOS (V)

/2.6 V

Vj 1/
I. ~
Vh J.-

10
(mA)

0

V

I

2.5 V

~

Output Characteristics for Low Gate Drive

200

J

~

o

100

3.0 V

~ ~~

3V

2'V

I

L. ~

0.4

0.2

~

,

~~

L

/ ~V

10
(A)

0.4

o

VGs= 10J-

TJ = 25°C

V'VGs =10V

r

1.2
10
(mA)

~

1.0

0.6

A

V
lL:

o

400

-;I

V

/

~192V

800

1200

Og (pC)

1600

2000

.HSiliconix

VNDB24

incorporated

TYPICAL CHARACTERISTICS
Capacitance

Transconductance
0.75 r--"""'T'--..,.---r---r----,

200

I

Vas = 0 V
f = 1 MHz
0.60

160

0.45

120

C
(pF)

gFs
(S)
0.30

ao

0.15

40

1\

I

C iss

'- J

~

---

I

~rssl

0.10

0.05

0.15

20

10

30

Source-Drain Diode Forward Voltage

I,o,o,~

1.75
1.50

(Norm.) 1.25
1.00

V
-50

/'
-10

V

~

I

,/

II I

0.1 A

Is
(A)

f--I-

TJ

25°C

I

30
70
T J (OC)

110

0.01 0

150

I

II
0.5

1.0

1.5

2.0

Safe Operating Area

10~mrIa.

5V

~otel

lS0°C

II

/

I

/

'-

-~

10jJ.S
100 jJ.S

10

10
(rnA)

I

V

0.1

0.01
0.3

(rnA)

I
250C

I

I

II

I
0.7

2.5

Vso (V)

Threshold Region

TJ

TJ = 150·C

0.1

I

10
Vo

50

40

On-Resistance vs. Junction Temperature
Vas= 10V

0.50

o

Vos (V)

2.00

0.75

o

0.25

10 (A)

2.25

ros

0.20

1.1
Vas (V)

./

I

II
55°C

t-

100

1.5

1K

Vos(V)
10peratlon in this area may be limited by rOS(ON)

7-105

..

.HSiliconix
incorporated

VNDB24
TYPICAL CHARACTERISTICS

Normalized Effective Transient Thermal Impedance, Junctlon-to-Amblent (TO-92)

Duty Cycle

0.5

0.2
R thJA
(Norm.)

--

0.1

~.05

0.1

~

Notes:

0.0

HlSL
~t~

"~

:/'\

\

1. Duty Factor, D =

0.01

2. Per Unit Base = R'hJA = 156°C/W

Slnrle rUlje l
0.01

t,
t2

3. TJM - TA = POMZthJA(t)
1K

10
100
Square Wave Pulse Duration (sec)

0.1

On-Resistance vs. Gate to Source Voltage

10 K

Off State Current

14
VGS -

T J = 25°C

aV

12
10
rOs
(.('). )

8

\\ I,

6

1.0A

\; N.:!A

Vos i 190 V
11 L

loss
(nA)

L

10

Vos

10V -

4 1- 10 =0.1 A

T I I

2

o

o

L

I

,

10-

4

8

12

16

-60

20

Drive Resistance Effects on Switching

60
100
TJ (OC)

100
Vos - 60 V
R G -25.(').

VOO 60 V
R L -150.n
10=0.4A

I

IiiI'"

I I

t - - ' td(OFF)

t

20

td(OFF),-

""'~

if

10

t

(ns)

10

tlr

r--" td(ON)

1

7-106

td(ON)
t

I

1
2

5

10
RG (.(').)

20

50

140

Load Condition Effects on Switching

100

(ns)

-20

100

1

0.01

Jill

0.1
10(A)

~

180

tcrSiliconix

VNDB24

~ incorporated

TYPICAL CHARACTERISTICS
Equivalent Input Noise Voltage vs. Frequency

Body Drain Leakage Current

100

80

60
en
(nVNRZ)

TJ

25°C
I

\

~R

40

10= 1 mA
10
(nA)

10=10m~ :::~

20

o

VOS = 5 V
TJ = 25°C

~

.,

10

......;;;
10

Vos-190 V ~

100

10 V

:::::~

1K

10 K

0.2

0.4

0.6

0.8

1.0

V GS (V)

f (Hz)

Output Conductance vs. Drain Current
700
600

80 JJ,S, 1% Duty Cycle
Pulse Test
TJ = 25°C

500
gos
(mS)

400

Vos=7.5V

300

I

200

/

100

.... hov

a

10

1K

100
10 (mA)

Transient Thermal Response (TO-205AD)
1.0
D

-....

0.2
R thJO
(Norm.)

0.1

0.1
0.05
~

19'"

I

~

....

~

~

Notes:

Single Pulse

0.02

V-

-

0.5

tt~

0.01

t
1. Duty Factor, D = ~

a
0.01

3LrL

2. Per Unit Base = RthJO = 20 ° C/W
3. TJM - To = POMZthJO(t)
0.1

10

100

1K

10 K

t1 (sec)

7-107

~Siliconix

VNDN24

~ incorporated

N·Channel Enhancement·Mode MOSFET
DESIGNED FOR:
•
•

Switching
Amplification

TYPE

PACKAGE

Single

To-92

• 2N7007

SOT-23

• 2N7001

Chip

FEATURES
•
•

High Breakdown > 240 V
Available in Surface Mount SOT-23

GEOMETRY DIAGRAM

T

Gate Pad

0.0038
(0.0965)

0.0063
(0.1600)

0.027

(0.686)

Source Pad

0.0049
(0.124)

0.0049
(0.124)

liiiiiiiiiiiiiiiiiiill

1 - 0 - - - 0.027 _ _~'I
(0.686)

7-108

DEVICE

• Available as above
specifications

VNDN24

fCTSiliconix

~ incorporated

TYPICAL CHARACTERISTICS

Ohmic Region Characteristics

Output Characteristics
200

f
V

160

I

/5V

. /V

I

./
)t"/ V
/,/

80

V/
IY

3V
40

40
2V
0
25

50
75
VOS (V)

100

125

3V-

"

2V
4

0

Output Characteristics for Low Gate Drive
50

40
V GS = 3 V

./

30
10
(mA)

h ~

10

o

~

o

~
,...-

~V

--

0.4

40

k& :::;.--

2.Jv
20

2.2 V
2.0 V

0
0.8
1.2
Vos (V)

1.6

2.0

2
3
V GS (V)

0

Gate Charge
R L = 6.2

v

75

o

V GS
(V)

7.5
Vos = 100 V--;;

~

5.0
2.5
0

50

100
150
10(mA)

/~

10.0

V S=10J/

o

..!.
k.o.

12.5

100

--

5

10
(mA)

15.0

25

4

60

2.8 V

On-Resistance

50

20

80

125

rOS
(.0.)

16

Transfer Characteristics

.",.

2.6 V

~

8
12
VOS (V)

100

T J = 25°C

20

4V_

~

V

120

3.5 V
10
(mA)

o

-

160
4V

80

o

Vos-10 V / ,

T J = 25°C

;--V Gs =10V

r

120
10
(mA)

200

200

250

/~
~

~ r--

192 V

V
o

50

100

150

I
200

250

300

Og (pC)

7-109

VNDN24

fC'rSiliconix

~ incorporatec

TYPICAL CHARACTERISTICS
Capacitance

Transconductance
0.150

20
VGS=IOV

0.125

16

12
gFS 0.075
(S)

Coss

8

~ """'-

0.050

4

50

o

150

100

lss

"

·C
(pF)

0.025

C

"""\

0.100

I\.::=s
o

10

20

10 (rnA)

On-Resistance vs. Junction Temperature
2.25
2.00

VGS= 4.5 V
10 = 50 rnA

1.75
ros
(Norm.)

1.50
1.25

/

1.00
0.75
0.50

L

-50

/

30

50

V

V

/

Source-Drain Diode Forward Voltage

/

TJ - 150·C

I

I I
Is
(rnA)

I

0.1

TJ = 25·C

/
-10

110

I

0.01 0

150

0.5

1.0

1.5

Vso (V)

Threshold Region
10

E VOS -

5V

r - - TJ

150·C

75~C
10
(rnA)

II

I

I

I
0.75

/

1// /

/ I

J

0.01

7

/

I

r- 25·C
0.1

7-110

40

VOS (V)

1.25

-55·C
1.5 1.75
V GS (V)

2

2.25

2.5

2.0

2.5

H

VNDN24

Siliconix

incorporated

TYPICAL CHARACTERISTICS
Normalized Effective Transient Thermal Impedance, Junctlon-to-Amblent (TO-92)

Duty Cycle

0.5

0.2
R thJA
(Norm.)

_

,,-

...

0.1

Notes:

~05
0.1

HlSL

0.0

tt~

Ji'/
;/\

\

1. Duty Factor, D =

0.01
slnrle 'lulie,

0.01

10
100
Square Wave Pulse Duration (sec)

0.1

1K

On-Resistance vs. Gate to Source Voltage

10 K

Off State Current
10 3

100

Vas

TJ = 25'C
90

OV

10 2

80
ros
(.0. )

!~

2. Per Unit Base = RthJA = 156'C/W
3. TJM - TA = POMZthJA(t)

Vos - 190 V

10'

1\

70

"

""-

60

loss
(nA)

10 = 100 mA

20 V
10-'

50
40
30

o

\~

50 mA

i'-

10 mA

10-2
10-3

8

4

12

16

20

-60

Drive Resistance Effects on Switching

30
TJ (OC)

60

90

120

100
VOO - 25 V
RL - 500.0.
Vas = 0 to 10 V
10=50mA

50

Voo 25 V
Ra- 25
Vas - 0 to 10 V

.n

50

..........

20

t

0

Load Condition Effects on Switching

100

(ns)

-30

20
tf
td(OFF)-~

10

5

t

(ns)

~

..........

10

I

~
td(OFF)-

5
tr

I
r-.

tr

I

t~(O~) 1-

td(ON)

2

2

I
10

20

50

100

10

20

50

100

10 (mA)

7-111

VNDN24

tcrSiliconix

~ incorporated

TYPICAL CHARACTERISTICS
Body Drain Leakage Current

Equivalent Input Noise Voltage vs. Frequency
10 3

200 r-"""'T'TTTnrTT'""....,...-r-rTTmr-r-T"TTTTTn
V DS = 5 V
TJ = 25°C
160

120
en
(nV/VRZ)
80

TJ

\

"

40 - I -

25°C

10 2
10

ID = 1 rnA

ID
(nA)

~ ....

I

/

10-2

'r-

10 V

OL-..I-.L..L..u.J.UJ......J....L..u..LWJ.._L....L..L..I.1.LW
10
100
1K
10 K

10-3
-0.5

o

0.5

f (Hz)

Output Conductance vs. Drain Current

I: 80 J,ls, 1% Duty Cycle
Pulse Test
TJ = 25°C

VD
gos
(J,LS)

7.5 V

10 2

~

10

20 V

V
10

100
ID(rnA)

7-112

I

10-1

10 rnA.....oo:I---ti'---f'!oW:ttt--+-++-H1-tHI

1111111

~ V DS ~90 V

1K

1.0

1.5

2.0

VND050

.rSiliconix

.LJI

incorporated

N·Channel Enhancement·Mode MOSFET
DESIGNED FOR:
•
o

Switching
Spike Protection

FEATURES
•
•

High Breakdown 450 V
Available in Surface Mount Package
SOT-23

TYPE

PACKAGE

Single

TO-92

• VN45350L
VN50300L

SOT-23

• VN45350T
VN50300T

Chip

DEVICE

• Available as above
specifications

GEOMETRY DIAGRAM

VND050

T

•

0.026

(0.660)

Source Pad

0.0041

0.0034

(0.1041)

(0.0863)

0.0043

0.0043

(0.1092)
Gate Pad

(0.1092)

I-

0.028
(0.711)

7-113

VND050

.-r'Siliconix

~ incorporated

TYPICAL CHARACTERISTICS

Output Characteristics

Ohmic Region Characteristics

100
VGS - 20 V ""
~

~

BO

60
10
(rnA)

40

20
VGS= 10V
10 V..!!...

~

,

16

l

,

7V

10
(rnA)

B

~

6V

4

5V
4V

o

40

BO
120
Vos (V)

160

o

200

~

V GIl = 7 V

I
4

I

I

TJ = 25°C

3
10
(rnA)

/)

L
If/ /
n rL
V/
/

o

I~

o

2

4

5

6

7

40

30
10
(rnA)
20

4V

"

10
3.5'V
0

0.4

O.B
1.2
Vos (V)

1.6

2.0

2

3

On-Resistance

4
5
V GS (V)

Gate Charge
30

TJ = 25°C
V Gs =10V

300

275
rOS
(.0. )

250

~
225

7-114

3

5V........t-"

325

200

I
41V
3.5 V

Transfer Characteristics

V4.5V

I'

o

I
4.51V

50

II V

J. V

.... ~ J..ooo'"
~ 10'

Vos (V)

/A

2

51V

~

Output Characteristics for Low Gate Drive

5

6V

1~
~

12

V

Y

VA

I
I
T J = 25°C

BV

20

o

I

9V

o

--

5

10= 10 rnA
25

~

V
:,/'

20

250~

15
10

./

d

I"'"

5

10
15
10(mA)

20

25

~

o ~
o
25

50

100

Og (pC)

;;;"

400 V

I

150

200

VND050

crSiliconix

~ incorporated

TYPICAL. CHARACTERISTICS
Capacitance

Transconductance
25
20

~--~----~---'-----r--~

12

80.l1s, 1% Duty Cycle
Pulse Test
Vos=7.5V

VGS = 0 V
f = 1 MHz

10
8

15 I---j.---j---:!.-'''''--{
gFS
(mS)

C
(pF)

10

6

I---j.--::;~-+::.,...=:'-j---

4

51-+.A"c..--j---j---j---I

2

OL..__......I..____.....__- - '____- ' -__- - '
4
6
8
10
o
2

"-

'-

o

'-E.,oss

C rss

40

Source-Drain Diode Forward Voltage

lo=10mA

10

r--

On-Resistance vs. Junction Temperature
VGS= 10 V

50

i#

./.! ~

5mA_

1.75

/

1.50

/

1.00

/'
-50

TJ = 125°C
Is

/

(Norm.) 1.25

0.50

C'ss

20
30
VOS (V)

2.00

0.75

\'

10 (mA)

2.25

rOS

o

~

(A)

/

0.1

fT J =25°C=

I

V

I

-10

30
70
TJ (OC)

110

0.01

150

I

'/

o

0.25

Threshold Region

0.50
0.75
Vso (V)

1.00

1.25

Safe Operating Area

10
Vn ,

5V
TJ

150°

10
(mA)

0.1

/L II

If/

125!C

II

I

1/

I
I

0.01

o

25°C

3

VGS (V)

See Note 1
100

" " "

..r-.. ... ...

0.01

I
4

0.1
10
(mA)

Tc 25°C
Single Pulse
RthJA - 156°C/W
Part: VN50300L

-55°C -

/J III.
2

§

I
5

6

0.001
7

10

100
VOS (V)

1 ms
IIIII

10 ms
100 m s

IdFI

H

1000

10peratlon In this area may be limited by rOS{ON)

7-115

VND050

.:r'Siliconix
.LII incorporated

TYPICAL CHARACTERISTICS

Normalized Effective Transient Thermal Impedance. Junction-to-Amblent (TO-92)

Duty Cycle

0.5

-

0.2
R thJA
(Norm.)

0.1
0.1

~ ~

F-

i-

1(i.05

Noles:

P?M

0.0

r

2. Per Unit Base = R thJA = 156 0 C/W
3. TJM - TA = POMZthJA(t)

I I I

0.1

0.5

5
10
50
100
Square Wave Pulse Duration (sec)

500

On-Resistance vs. Gate to Source Voltage

1K

5 K

10 K

Off State Current
10 2

700

VGS

TJ = 25°C
IIJmA

600

I

500
ros
(.(1)

~~

1. Duty Factor. D =

0.01
Single Pulse

0.01

L

tt~

--r....

[/\

1\

I U

OV

10 1

I

Vos

r.--l0 mA

400

loss
()J.A)

300

,~

400 V,; ~
L

./

Hy1
./

10-2

10V_

/

200
10-3

100

o

o

10-4

4

8
12
VGS (V)

16

20

-60

Drive Resistance Effects on Switching

-20

20

100

"-

'"

1'\

I'
td(OFF)

10

t

(ns)

t,
td(ON)

20

7-116

t~l~iF)

t,

"

f',~

I'

50
RG (.(1)

10

I

t;

td(ON)

VOO = 25 V
RL = 2.5 k.(1
V Gs =Otol0V
10=10mA
10

180

VOO 25 V
RG 25.(1
.... VGS = 0 to 10 V

t1

t

140

Load Condition Effects on Switching

100

(ns)

60
100
TJ (DC)

100

10
10 (mA)

100

VND050

fCJrSiliconix

.LJJ incorporated
TYPICAL CHARACTERISTICS
Equivalent Input Noise Voltage vs. Frequency
1000

Body Drain Leakage Current
10 6

=
=

r=

Vos 5 V
TJ
25°C
800

600
en
(nV/IiHZ)
400

10 5

r\~

10 4

\

10
(nA)

10

0

1/

I
I

10 3
100 V

Vos

= 1 mA :-.....1"'-

t:===.

1111
10

-U

10 2

' " 10.uA

200

TJ = 25°C

I

100

...

10 V
10 K

1K

2

f (Hz)

3

4

5

VGS (V)

Output Conductance vs. Drain Current
28
24

80.us, 1% Duty Cycle
Pulse Test
25°C
TJ

=

II
Vo

= 10 V

20

gos
(.us)

16
50 V'-

12
8

~

4

o

V~

'"

0.1

10

100

10 (mA)

..
7-117

VNDP06

tcrSiliconix

~ incorporated

N·Channel Enhancement·Mode MOSFET
DESIGNED FOR:

=
•

S'vVitching
Amplification

FEATURES
•
•

Protection Diode
Low rDS(on) < 10

n

TYPE

PACKAGE
-

Single

TO-206AC

0.0063
(0.16)

TO-237

• VN10KM, VN2222KM

T
0.038

(0.965)

Source Pad

0.0081
(0.206)

0.0059
(0.15)

7-118

• VN10KE
• VN0610L, VN2222L

GEOMETRY DIAGRAM

~
(0.224)

--

DEVICF
-

TO-92

Chip

Gate Pad

I

1

• Available as above
specifications

VNDP06

~SilicDnix
.z.
incorporated
TYPICAL CHARACTERISTICS

Output Characteristics

Ohmic Region Characteristics

1.25

1.0

T J = 25°C

7V
6V

1.00

Vas = 10 V/

/

0.8

L

5V

0.75
10

(A)

10
(A)

'/ '"
v..
~
/,
~ / '~

0.4

~V

3V
0.25

0.2
2V

/' ~

1'.....

0.6

4V

0.50

6Y,
V5V

,

1

1

4V

1

1

13 ) -

Vi. V

A~

_12)-

0

4
6
Vos (V)

2

8

10

0

2
3
Vos (V)

Output Characteristics for Low Gate Drive
50

/ Sf!-v

30

II

10
(rnA)

o

'/~

,
Ij

o

4

5

0.4

0.3

1.8 V

10
(AI

Z "1".6 J

20

10

Transfer Characteristics

Vas - 2.0 V

V

40

5

0.5

I

T J - 25°C

4

0.2

1.5 V
1.4 V

0.1

1.2 V
0
0.4

0.8
1.2
Vos (V)

1.6

2.0

0

2
3
Vas (V)

On-Resistance

...

Gate Charge

5

15.0

4

- --

3
ros
(.0. )

2

Vas= 10 V

-

~

--

12.5
10.0
Vas
(V)

7.5
5.0
2.5

o

a

0.2

0.4

0.6
10 (A)

0.8

1.0

100

200

300
400
Og (pC)

500

600

7-119

VNDP06

fCrSiliconix

~ incorporated

TYPICAL CHARACTERISTICS
Capacitance

Transconductance
100

I

V GS = 0 V
f = 1 MHz

80

60
gFS
(S)

125·C

C

""

C lss

(pF)

0.2

40

0.1

20

Coss

0.4

0.2

0.6

0.8

~

I,
o
o

1.0

C rss

10

20

30

40

50

10 (A)

Vos (V)

On-Resistance vs. Junction Temperature

Source-Drain Diode Forward Voltage

2.25
V Gs =10V

/

2.00
1.75
ros
(Norm.)

~

1.25
1.00
0.75
0.50

-50

~.lA

Is
(A)

I

I I

0.1

/'

/

V

I

I

/'

10=0.5A ~

1.50

- TJ -150·C

//

-10

30

==

TJ - 25·C

70

110

0.01 0

150

0.25

0.75

0.5

1.0

1.25

100.IJ.S

==

Vso (V)

Threshold Region

Safe Operating Area

10

5

/

I

/

seel
Note 1

/ VI /J
I=TJ

10
(mA)

150·C

10

II

I

100·C -

0.1

f---tj

I

/ I 1/

25·C

,..

II

0.01

/,
o

0.25

J
0.5

I I

0.75 1.0
VGs(V)

0.1
O·C=

-

5T C 0.01

1.25

1.5

1.75

--

..

'/

(A)

I

I

~

1 ms

.

Tc - 25·C
Single Pulse
R thJC = 83·C/W
Part: VN10KE
10

=

10 ms
100 msdc

--t-

11111
100

300

VOS (V)
10peratlon In this area may be limited by rOS(ON)

7-120

VNDP06

.-r-Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Normalized Effective Transient Thermal Impedance, Junction-to-Amblent (TO-92)

Duty Cycle - 0.5

0.2
R thJA
(Norm.)

-

0.1
0.1

~05

;.-'

Notes:

0.0

HLJL
~t~

I/\.

\

1. Duty Factor, D =

0.01
Sint lUlie,

0.01

0.1

0.5

5
10
50
100
Square Wave Pulse Duration (sec)

ros
(.0. )

TJ = 25°C

Vas

\ ~ i- 250 rnAI

4

~~ ~6mA

Vos

loss
(nA)

"

10-1 I

8

12
Vas (V)

4

16

-60

20

Drive Resistance Effects on Switching

20

60
100
TJ (DC)

..

Load Condition Effects on Switching

~ Voo 15 V
50 ~ RL = 25.0.
I- Vas = 0 to 10 V

Voo 25 V
50.0.
RL
Vas o to 10 V
10=0.5A

20

20

t

10

2

-20

100

50

5

'1

10-2

o

100

t

180

'/

u10V
I

(ns)

48 V

101

2

o

140

//

10 2

3 i-Io = 50 rnA

10 K

OV~

10 3

\\

5

5 K

Off State Current
10 4

1\ \

1K

500

On-Resistance vs. Gate to Source Voltage

7
6

!;

2. Per Unit Base = R thJA = 156 ° C/W
3. TJM - TA = POMZthJA(t)

(ns)

-

10

td(OFF)

5

tf
tr
td(ON)

2

'"

td(OFF)=
tr

r-

'::tt

~
tf

10

20

50

R a (.0.)

100

0.1

0.2

0.5

1.0

10 (A)

7-121

VNDP06

tcrSiliconix

~ incorporated

TYPICAL CHARACTERISTICS
Body-Drain Leakage Current

Equivalent Input Noise Voltage vs. Frequency
250

200

150

~

Vos = 5 V
TJ = 25°C

I~~
1\

en
(nV/'IiHz)
100

10
(nA)

1F~~:~,
....

50

o

~1mA

10-'~~~~~~~

10-2~~~
TJ - 25°C

10-3
100

10

-0.3

10 K

1K

0

0.3

O.S

0.9

1.2

Vas (V)

f (Hz)

Output Conductance vs. Drain Current
10 K
80J,Ls, 1% Duty Cycle
Pulse Test
TJ - 25°C

gos
(J,LS)

1K

VD~'~

100

"'~01~11I

7.5 V

~

10

10

100

1K

10 (mA)

Transient Thermal Response (TO-20SAC)
1.0
D = 0.5

0.2
RthJO
(Norm.) 0.1

-

~

-==="

~

0.1

~

0.05

Notes:

=--

tt~

O.O~
~

::.,.....-r

.....

0.1

1. Duty Factor, D = ~~
2. Per Unit Base = R,hJC = 83°C/W
3. TJM - To =PoMZthJO(t)

0.01

Slnglj put
0.01

I II
10

100
t, (sec)

7-122

~

1K

10 K

VNDQ03

~SilicDnix

~ incorporated

N·Channel Enhancement·Mode MOSFET
DESIGNED FOR:
•
•

Switching
Amplification

TYPE

PACKAGE

Single

TO-20SAD

• VN0300B

TO-92

• VN0300L

TO-237

• YN0300M

14-Pin
Plastic

• YQ1001J

FEATURES
•

Low rDS(on) < 3

.n
Quad

14-Pin
Dual-InLine
Chip

DEVICE

II

YQ1001P

• Available as above
specifications

GEOMETRY DIAGRAM

Gate Pad
0.010
(0.254)
0.0087
(0.2209)

Souroe Pad
0.007
(0.1778)

.lLQ..1.Q..
(0.254)

T
1

•

0.038
(0.965)

7-123

~SilicDnix

VNDQ03

~ incorporated

TYPICAL CHARACTERISTICS
. Ohmic Region Characteristics

Output Characteristics

2.0

v

s= 10 V
6V

/

1.S

1.2

SV

VI

1.2

-,Vi

10
(A)

4V -

O.B

0.4

3V

0

12
Vos (V)

8

4

16

20

160

vas-I
3.S VI
I
II
'I
I V
I fl

120
10
(rnA)

80

J

1.S
(.0. )

1.0

2V

2

4

S

200 ~--~-----r--~~----r----;

..1

1.7 V

0.8
1.2
Vos (V)

1.6

1001----+

o ~--~~~~--~~--~--~
o
2
3
4
S

2.0

Vas (V)

Gate Charge

S

I

10= 1 A

T J = 2SoC

lts=6J

L
V
-----

S

Vos=lls~

4

Vas
(V)

o!!!.

~V

3

/. ~V

2

Vas=10V

/
o

2

10 (A)

7-124

3

r----r--""T""---r--rr~r----,

O.S

o

3V

2.3 V

tilas=4.L

ros

J

I/J

On-Resistance

2.0

4'V

(rnA)

1

~

2.S

1

10

..1

1.00"""

2.1 V

0.4

LI--

300 ~--~-----r----~----r----;

2.S I V

~

o

slV

2.7 1V

.......

fJJ

/

Transfer Characteristics

SOO

T J - 2SoC

-

~

1

/'r'

Vos (V)

rJI/'r'

40

o

-2.9V

L

SIV

100-""

J'Ib I--"'"

Output Characteristics for Low Gate Drive

200

/7V

'{flY

o~
o

2V

0

I

II V/'

'F
0.4

,I

1V

TJ = 2SoC

"

O.B

TJ = 2SoC
Va1l= 10 V

1.6

/

10
(A)

2.0

3

4

S

o

/

o

80

160
240
Og (pC)

320

400

VNDQ03

trr'Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Transconductance

Capacitance

--.,.....--=_--,

500 .......---r.r--......

120

Ia v _

Vas=
f = 1 MHz

100

400

BO

1\

60

1\\

300
gFS
(mS)

C
(pF)

""

200
40
100

1H--+---+-----1 Pulse

Test
V Ds =7.5V
BO)J,s
1% Duty Cycle

20

400

200
300
ID (mA)

100

On-Resistance

VS.

...........::::

C lss

I--- Coss

~

o

0
0

1\

500

o

Junction Temperature

C rss

10

20
30
V DS (V)

40

50

Source-Drain Diode Forward Voltage

2.25
Vas=10V
TJ

2.00

1.50

1.00

/

. /V

",...

0.1 A

Is
(A)

0.50
-50

-10

30
70
TJ (OC)

110

I

150

o

0.25

Threshold Region

=='TJ - 150 0 C-o-/

=

ID
(mAJ'

I

/
I

0.6

See
Notey

O.B

f

~:25°C

r--SSOC
0.1
1.0

I

I

TJ = -55°C
I

0.5
0.75
VSD (V)

1.0

1.25

•

1.2
1.4
Vas (V)

1.6

1.B

2.0

10)J,S

--I'

I II
"
V '" .. , rrl

......

ID
(A)

/

/

I

I

~

I /

I

I

0.01

/

/ /

100°C

0.1

I

I

10

10 V

I

I

Safe Operating Area

10
V DS

I

I

25 0 C/

0.1

0.01

I

II

/

#

L

(Norm.) 1.25

0.75

I

I

I D - 0.5 A/

1.75
rDS

150°7

_I

To = 25°C
Single Pulse
R thJO = 25°C/W
par\ V~0310~BI I I

,..

10
V DS (V)

"

10 ms

~OOI ~s
dc

II

I I II
100

10peratlon in this area may be limited by rDS(ON)

7-125

~Siliconix

VNDQ03

~ incorporated

TYPICAL CHARACTERISTICS
Normalized Effective Transient Thermal Impedance, Junctlon-to-Amblent (TO-92)

Duty Cycle - 0.5

0.2
0.1
R1hJA
(Norm.)

0.1

Notes:

"0.05
\).0

\

1. Duty Factor, D =

0.01

2. Per Unit Base = R thJA = 15soC/W
3. TJM - TA = POMZthJA(I)

Single Pulse
0.01

f I II

0.1

t,
t2

50
100
5
10
Square Wave Pulse Duration (sec)

0.5

On-Resistance vs. Gate to Source Voltage

500

1K

10 K

5 K

Off-State Current
10 3
~ VGS - 0 V

TJ = 25°C

3

rOs
(.0. )

I\-,

10=0.2A
f I I

Vos - 24 V
1£

10

;-10=0.5A
.11
10 = 1.0 A

2

/L

10 2

~OS -1~ V

loss
(nA)

\ 1\\

~~

"

10-'

v,

10-2

a

10-3

o

4

12

8

16

-SO

20

Drive Resistance Effects on Switching

-20

20

SO
100
TJ (OC)

,=

VOO 25 V
RG - 25.0.
V GS - 0 to 10 V

-

I I
10

t

tJJ)

(ns)

I- t,

10

10

tL1)

td(Q.N)

td(ON)

r-t,_

t

t/

t,

50

100

1
0.1

1
10 (A)

7-126

180

100
VOO - 25 V
'::
RL -24.o.
VGs 0 to 10 V _
10 = 1 A
_

t

140

Load Condition Effects on Switching

100

(ns)

=J

10

VNDQ03

tcTSiliconix

~ incorporated

TYPICAL CHARACTERISTICS
Body-Drain Leakage Current

Equivalent Input Noise Voltage vs. Frequency
1000

BOO

10 3

~!ll

V DS = 5 V
T J =2S o C

III

10 2

II

10 '

en

600

\

(nV/IiRZ)
400

200

ID
(nA) 1.0

"

24 V I

ler'

~I'--

'D -1 mA

o

- VDS

VDs-l0V~
I

I I III

10

10-3
100

1K

-0.5

10 K

o

0.5

1.0

1.5

2.0

f (Hz)

Output Conductance vs. Drain Current
80Jj.s, 1% Duty Cycle
Pulse Test
T J = 2S o C
V Ds =10V

3

gos 2
(mS)

o

V

--

""

/

10

100

1K

'D(mA)

Transient Thermal Response (TO-20SAD)
1.0
D

~:;1111

0.2
R thJO
(Norm.)

-

i-"I-

0.1

--

0.5

~ I- 1--'1~ngle

~ ".

~0.05

Notes:

tt~

Pulse

1-\'+-'\'
0.01

r-

~

I
0.02

1. Duty Factor, D =

I I

:~

2. Per Unit Base = RthJO = 2s o C/W
3. TJM - To = PDMZthJO(t)

0.01
0.1

1.0

10

100

1K

10 K

t, (sec)

7-127

.:rSiliconix

VNDQ06

~ incorporated

N·Channel Enhancement·Mode MOSFET
DESIGNED FOR:
•
•

Switching
Amplification

DEVICE

TYPE

PACKAGE

Single

TO-205AD

• 2N6659, 2N6660
VN67AB

TO-220SD

• VN40AFD, VN46AFD,
VN66AFD, VN67AFD

FEATURES
•

Low rOS(on) < 3.5

n

Quad

TO-220

• VN66AD, VN67AD

14-Pin
Plastic

• VQ1004J

14-Pin
Dual-InLine

• VQ1004P

Chip

GEOMETRY DIAGRAM

Gate Pad

0.010
(0.251)

0.0087
(0.2209)

T
1
0.038

(0.965)

Source Pad

0.0070
(0.1778)

0.010
(0.254)

7-128

• Available as above
specifications

VNDQ06

~SilicDnix

~ incorporated

TYPICAL CHARACTERISTICS
Output Characteristics

Ohmic Region Characteristics

2.0

2.0
TJ=25°C

Vas = 10 V
1.6

Vas = 10 V

7V
1.6

f

TJ =

6V
1.2
10
(A)

1.2

'/

0.8

10
(A)

5V

rr

0.8

o

0
0

20
30
Vos (V)

10

40

50

I

I

80

I /
II I
/ ./

60
10
(mA)

I II
/I / ,.
rIJ /

40

20

o

Vas = 3 V

".

V

./ '

I

5V
4'V
3 1V

e;

2V

o

2

3

4

5

T J -25°C

2.8V

1.0

.-----r---,--"'T'"rr-l,......-,......--,

0.8

t----t---t--I-H9---t---I

0.6 I----II----f--H-I--+--+---I
10

(A)
2.4 V

0.4

2.2 V

1---4---1/----+---1---1

0.2 I - - - - I I - - - I - f - - - - + - - + - - - I

2.0 V
.8 V

0.4

0.8
1.2
Vos (V)

1.6

2.0

o~--~--~----~--~--~
o
2
4
6
8
10
Vas (V)

On-Resistance
2.5

I

6V

Transfer Characteristics

.......

-

7V

t/'

Vos (V)

2.6 V

rb

o

I

/

/ ~
/ // /~
liD /

Output Characteristics for Lcw Gate Drive
100

J

fA ~/. / '

0.4
3V

I

V'svJ

/;"

~V
A~

4V

0.4

2~OC

V

/

Gate Charge
15.0

I
TJ=25°C

10=1.0A
12.5 t---+---t----t--t---+-~~

2.0

1 0.0
1.5

,......-..,....--,----r--.---..,....-...,

Vas = 10 V

ros

I---t---f---+---I---.~~--I

~

7.5 1---t---f----r--7I'-"-k---II----I

(.0. )

1.0

0.5

o

o

0.4

0.8

1.2
10 (A)

1.6

2.0

5.0

t---j---+~,?!"--t---t---f

2.5

t---:±:%*---t--t---j---f

100

200

300

400

500

600

Q g (pC)

7-129

VNDQ06

tcrSiliconix
.z.
incorpora.ted

TYPICAL CHARACTERISTICS
Capacitance

Transconductance
500

",---""'--"""'---r---r---.....,

120

80 J,ls, 1 % Duty Cycle
Pulse Test
Vos =7.5V

400

I

Vas = 0 V
,... f = 1 MHz

100

I

25°C
80

~

300 1---t-7'~01-"'==--t---t 125°C
gFS
(mS)

C
(pF)
200

60

I---Mf-::;~-+---+---I----I

40
100

I-H--f---f---+---+--~

20

OL..._...I._ _..L..._--'_ _-'-_--J

o

100

200

300

400

o

500

1\"
1\
.........

o

~

Coss

--.

erss

20

10

-

C lss

r-""-...:r-30

40

10 (rnA)

Vos (V)

On-Resistance vs. Junction Temperature

Source-Drain Diode Forward Voltage

50

2.25
VGS = 10 V

/

2.00
10= 1.0 A
1.75
ros

~

(Norm.) 1.25

It
IS

(A)

fc-

V
-50

I

30
70
T J (OC)

110

0.01 0

150

I

- TJ = 25°C
0.5

1.0

1.5

2.0

2.5

Vso (V)

Threshold Region

Safe Operating Area

10

10
:: Vos

5V

I
TJ = 150°C
10
(rnA)

I

I I

0.01
0.5

,

I

~

I II
1.0

See Note 1

1.5
Vas (V)

~I;'-

10

,

"

.

25°C
f - Tc = 25°C
,- Single Pulse
RthJC = 20°CIW
Part: 2N6660

-rCI0.1
2.0

,11~fS

-='"

(A)

'(c-+

If-~/

125°C -

"I

~/X

/
0.1

TJ = 150°C

I

/'
-10

-

0.1

V

1.00

0.50

I I

~ Va.2 A

1.50

0.75

,

,

W

imr

s

1 ms

".

10

-

=

10 ms
100 ms
dc
100

Vos (V)
IOperation In this area may be limited by rOS(ON)

7-130

VNDQ06

~Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Normalized Effective Transient Thermal Impedance, Junctlon-to-Amblent (TO-92)

Duty Cycle - 0.5

0.2

-

0.1
RlhJA
(Norm.)

0.1

"0,05

Notes:

HLJL

0.0

~t~

.L"L

/\.

2. Per Unit Base = R lhJA = 156°C/W
3. TJM - TA = POMZlhJA(I)

Slnrle 'Iuliel
0.01

0.1

5
10
50
100
Square Wave Pulse Duration (sec)

0.5

500

On-Resistance vs. Gate to Source Voltage
2.8

ros
(.0. )

'\

1.6
10

10 K

Off State Current

TJ = 25°C
10 2

r-

OV

VG

1\\\

2.0

5K

1K

10 3

\1\ \

2.4

!~

1. Duty Factor, D =

0.01

\

=0.1 A '\:::

1.2

~

,

101

\ \ 1.0A

i=

loss
(nA)

0.5 A

V ns = 48 V

,

/

10-1

,

i/

I

10 V

0.8

o

/

10-2

0.4

10-3

o

4

12
V GS (V)

8

16

-60

20

Drive Resistance Effects on SWitching

-

90

120

•

~ Voo - 25 V
50 f- RG 25.0.
i- V GS = 0 to 10 V

Voo - 25 V
RL - 23.0.
V GS = 0 to 10 V
10 = 1.0 A

'-

20
10

60

100

50

t

o

Load Condition Effects on Switching

100

(ns)

-30

20

==

5 _

t

t\
tr

(ns)

td(OFF)
td(ON)

~
td(OFF)

5

" - i-"

2

2

10

5

10
20
R G (.0.)

2

50

100

tr

i---

I

1

0.1

tt,d(Oi),·

1
10 (A)

10

7-131

VNDQ06

1Cr5iliconix

~ incorporated

TYPICAL CHARACTERISTICS
Body-Drain Leakage Current

Equivalent Input Noise Voltage vs. Frequency

:::
120

lli'ili~;1111111111111111111

80

\
\. \II~ U~lllA

40

.....

en
(nV/VHz)

a

'i'o

48 V

V DS

1111UII

\

ID
(nA)

30V.-t 1 0 V -

/

.....

nij~I""~
10

1 K

100

10 K

0.4

0.2

0.6

0.8

V GS (V)

f (Hz)

Output Conductance vs. Drain Current
1400

B~ ~sl. 111~!~ I ~utyl C~~I~

r

1200

Pulse Test
TJ=25°C

1000
BOO

gas
(jlS)

600
VDS = 20 V

400

V

.......

200

a

1 7 .5
.L
/

0.1

10

100

ID(mA)

Transient Thermal Response (TO-205AD)
1.0
D - 0.5
0.2

.......:::: ~ II"""

~0.1

R thJC
(Norm.)

O~~_ ~

0.1

-

..-

::::t --~

Notes:

Single Pulse

~t~

~0.02
0.01

1. Duty Factor. D =

I

0.1

7-132

!~

2. Per Unit Base = R thJC = 20°C/W
3. TJM - Tc = PDMZthJC(t)

I

0.01

~

II
0.5

5

10

50
tl (sec)

100

I

I I 111111
500

1 K

I

I I I III
5 K

10 K

VNDQ09

~SilicDnix

~ incorporated

N·Channel Enhancement·Mode MOSFET
DESIGNED FOR:
GI

•

Switching
Amplification

DEVICE

TYPE

PACKAGE

Single

TO-20SAD

• VN90AB
2N6661

TO-92

• VNOBOBL

TO-237

• VNOBOBM

TO-220SD

• VNBBAFD

TO-220

• VNBBAD

14-Pin
Plastic

• VQ1006J

14-Pin
Dual-InLine

e VQ1004P

FEATURES
II

Low rDS(on) < 4

.n

Quad

GEOMETRY DIAGRAM

Gate Pad
0.010
(0.254)

MQl!L

(0.2209)

Source Pad
0.0070
(0.1778)
~

(0.254)

T

III

0.038
(0.965)

1
7-133

~SiliCDnix

VNDQ09

~ incorporated

TYPICAL. CHARACTERISTICS

Output Characteristics

1.25

Ohmic Region Characteristics

1.0

I V~s =10 ~

1.00

TJ

=25°C

VGs= 10~

SV

/

O.B

{

/

5V

0.75
10

(A)

(A)

0.50

rt

3V _

0.25

2V

o

a

10

20

30

40

~~~

0.4

0.2

50

V

V

10

4V

a

/

O.S

= 3 vI ~2.JV

III

80

AI
r/

"
'II

so

II!.

10
(rnA)

40

20

a

J

V

r/

I~

I

~

a

3V

2V

1.0

2.0

I

I
= 25°C -

0.4
0.3

0.2

b~
I

)
~~

0.1

1.2

1.S

2.0

a

2

I

= 25°C

I
VGS
(V)

~

7-134

0.5

1.0
1.5
10 (A)

~

7.5

2.5

a

./

2.0

2.5

a

~

~
Vos=45V~

5.0

2

a

I
10= 1.0 A

10.0

VGS= 1 0 ; /

~

10

12.5

s
4

8

Gate Charge

15.0

8

rOS

Vos = 15 V

4
S
V GS (V)

On-Resistance

(n. )

25+

V

(A)

VOS (V)

TJ

5.0

'f.- 125 b

1.BV

10

4.0

J

10

I I

O.B

3.0

0

2.0 V

0.4

U't/-

TJ = -55°C

I
f-- TJ

a

a

4V

i""""'"

Transfer Characteristics

2.4 V

IY

5V

Vos (V)

I I

I

/

~

0.5

f'sy-

V

~

~

~
i""'"

Output Characteristics for Low Gate Drive
VG

L""

j~ ",

VOS (V)

100

4=J._

~

A

V

a

100

~2V
I

200

300

Q g (pC)

400

500

VNDQ09

IClTSiliconix

jI;N) incorporated
TYPICAL CHARACTERISTICS
Transconductance

Capacitance

0.75

125

0.60

100

0.45
gFS
(mS)

/
P ..,.,..-

0.30

0.15

o

/"

-------

TJ = -)55°C
75

,-

C
(pF)

k5°C

I

50

125°C
25

If"
o

0.2

0.4

On-Resistance

VS.

I
VGs= 0 V
f = 1 MHz

0.6
10(A)

o

1.0

0.8

\

\'

C rss
Coss

"

o

~
C
rss

10

Junction Temperature

r-- ---. t----.

20

30

40

50

VOS (V)

Source-Drain Diode Forward Voltage

2.25
V GS = 10 V
2.00
1.75
ros

1.50

/

(Norm.) 1.25
1.00
0.75
0.50

/'
-50

/

V

V

V

/

/

T

150°C
I

I

I

I

I

Is

(A)

0.1

TJ = 25°C

I

-10

30
70
TJ (0C)

110

0.01 0

150

I I
0.4

Threshold Region

0.8
1.2
Vso (V)

1.6

2.0

Safe Operating Area

10

•

10
5V

VG

,

//

~/
PJ

10
(mA)

I

I

See Notel ~

/ /

150°

125°C
0.1

10

-I

I
~/

(A)

I

f. I,-!-

25°C
55°C

I

II

/ /

0.01
0.5

1.0

1.5
V GS (V)

,
..

==

0.1 ETC = 25°C
~ Single Pulse
I- RthJC = 20°C/W
0.01

2.0

~

?T

12N1f111

"'-

1OJ,LS '100d

1 "Is

-

r

~i

10
I I
100 ms
dc

I

10

100

1K

VOS (V)
10peratlon In this area may be limited by rCS(ON)

7-135

tcrSiliconix

VNDQ09

.,1;;11 incorporated

TYPICAL CHARACTERISTICS
Normalized Effective Transient Thermal Impedance, Junction-to-Ambient (TO-92)

Duty Cycle - 0.5

0.2
0.1
RthJA
(Norm.)

0.1

~

100-

~.05

Notes:

0.0

3nSL
tt~

~

:/\

i\

2. Per Unit Base = RthJA = 156°C/W
3. TJM - TA = POMZthJA(t)

Slnrle rUlje l
0.01

0.1

10
50
100
Square Wave Pulse Duration (sec)

500

5

0.5

On-Resistance vs. Gate to Source Voltage

7

,

5
rOs

(.0. )

TJ = 25°C

I

4

lo=0.1};

3

10 K

F

VGS - 0 V

10 3 I

\

'l\ f\

5K

1K

Off State Current
10 4

I

6

!~

1. Duty Factor, D =

0.01

10 2 I

~ :a~

..

loss
(nA)

1 ..q ~

V/

72 V
ILL.

10

10 V

2
/~

10-t

o

o

10-2

4

8
12
VGS(V)

16

-60

20

Drive Resistance Effects on Switching

t
(ns)

100r~~~~DI
23.0.

Voo - 25 V
RL VGS = 0 to 10 V H---+-Hf-++++H
lo=1.0A

50

20 I---I--+-+-Hf-H+f---+-i-H-H+H

20

td(OFF)
10~_~m

5

o

t

(ns)

120

160

VOO - 25 V
RG-25.o.
VGS = 0 to 10 V

10
td(OFF)

5
~

2
1
0.1

tr

~ rr;

i'
0.2

0.5

1.0

t

.1

1(01)

_tf

lo(A)

7-136

80

40
T J (OC)

Load Condition Effects on Switching
100

50

-40

2

5

10

.HSiliconix

VNDQ09

incorporated

TYPICAL CHARACTERISTICS
Body Drain Leakage Current

Equivalent Input Noise Voltage vs. Frequency
10 3

100
Vas = 5 V
T J = 25°C
80

60
en
(nV/VRZ)

~1\
\

40

TJ 10 2

7
II

10
la
(nA)

la = 1 mA

1\)

10m~

/I

t: Vas
10-1

~~

20

~45V
10 V

10-3
10

72 V

10-2

::::f:::
o

2r C

100

10 K

1K

a

0.2

0.4

0.6

0.8

1.0

f (Hz)

Output Conductance vs. Drain Current
350
80 JlS, 1%
Pulse Test
T J =2SoC

300

D~ty

Cycle

~

2S0

gas
(.J,J.S)

VV",

200

=7.SV

lS0
100

~

SO

20 V

/'

a

10

" II

100

1000

la(mA)

Transient Thermal Response (TO-20SAD)
1.0
D

-

O.S

:.,...,

0.2

~~

1-1--1-'

R thJO
(Norm.)

0.1

-

~ I- ,...

r-- 0.01

S

~O.OS

Notes:

ingle Pulse

BLfL
tt~

0.02

1. Duty Factor, D =

t
t}

2. Per Unit Base = R thJO = 20°C/W
3. TJM - To = PaMZthJO(t)
0.01
0.1

0.5

1.0

S

10

SO
t1 (sec)

100

sao

1K

SK

10 K

7-137

.rY"Siliconix

VNDQ12

~ incorporated

N·Channel Enhancement·Mode MOSFET
DESIGNED FOR:
•
•

Switching
Amplification

FEATURES
•

Low rOSlon) < 4.5

n

TYPE

PACKAGE

Single

TO-205AD

• VN1206B

TO-220

• VN1206D

TO-237

• VN1206M, VN1210M

TO-S2

• VN1206L, VN1210L

Chip

• Available as above
specifications

GEOMETRY DIAGRAM

Gate Pad
0.010
(0.254)
0.0087
(0.2209)

T
1
0.038

(0.965)

Source Pad
0.0070
(0.1778)

.-JW..Q.

(0.254)

7-138

DEVICE

~SilicDnix

VNDQ12

~ incorporated

TYPICAL CHARACTERISTICS
Output Characteristics
2.0

~

7V

1.2

VGS= 10V./
V
6V

6V

rr

1.6

10
(A)

VGS - 10 V

Ohmic Region Characteristics
1000

BOO

/ ./
/ / ...... .......
/ /'.: ' /
....

5V
600

V

10
(mA)

O.B

4V

0.4

3V

~

b

200

~

20

40
60
Vos (V)

BO

0

100

2
3
Vos (V)

Output Characteristics for Low Gate Drive
200

VGS= 3.0
2.8V~

160

~/

120

/I. V./ "

BO

2.2 V

....

2.0 V

Jj r V

~

40

500

125°C
300
10
(mA)
200

I I

100

j ~

1.B V
1.6 V

I&--

o

0
0.4

O.B
1.2
Vos (V)

1.6

0

2.0

2
3
V GS (V)

On-Resistance
5.0

I

ros
(.0. )
3.5

-l--'
o

0.2

5

I.
10= 0.5 A

11.1

10

4.0

3.0

4

Gate Charge
12

V Gs=10V
TJ = 25°C

4.5

5

400

L~
I I

~

4

Transfer Characteristics

-

VI V 2.6V_
if .A'I

h /

10
(mA)

2.5

L

0
0

o

3V

,"V

2V
0

4;:"

/ [.?

400

V

V
~

/

B

~

6

VOS=h~

~96V_

4

"./

........",

2

0.4

0.6
10 (A)

O.B

1.0

a

./

a

120

240

360

4BO

600

Og (pC)

7-139

.HSiliconix

VNDQ12

incorporated

TYPICAL CHARACTERISTRICS
Capacitance

Transconductance
600

120

1

T J = -55°C

VGS = 0 V
f = 1 MHz -

100

500

60

400
C
(pF)

9FS
(mS)

60

300
40
200

20

o
100

200
300
10 (mA)

400

500

~

"1\\"

2.00

10= 0.5

f- V GS = 10 V

1.75
ros
(Norm.)

#

1.50
1.25
1.00
0.75
0.50

/'

V
-50

-10

V

I
Coss

\..'

o

C rss

10

20
30
VOs(V)

V/

I

/

V"0.1 A
Is

"

(A)

TJ = 125°C /

I

l II

25oc

0.1
I

t---

-55°C I -

0.01

30
70
T J (OC)

110

150

o

I
0.2

Threshold Region

I

I

0.4
0.6
Vso (V)

0.6

1.0

Safe Operating Area
10

TJ

150°C

Vos = 15 V

I

I

1/

See Note 1

.

10
(A)

I

0.1

I

I

o

0.5

II

/
0.1

25°C -

I

r

-

'- -55°C
0.01
2.5

3

1 ms

.

10 lmls

~ Tc 25°C
I- Single Pulse
I- R thJC = 25°C/W

1 --

1.5
2
VGs(V)

~ot~
I I I

1'--,

100.u.s

10
(mA)

r-

100
dc

prY 11~ln~6B I

3.5

10

+tt

I I III
100

1K

VOS (V)
10peratlon

7-140

50

~

10

0.01

40

Source-Drain Diode Forward Voltage

On-Resistance vs. Junction Temperature
2.25

C 1SS

In

this area may be limited by rOS(ON)

VNDQ12

crSiliconix

~ incorporated

TYPICAL CHARACTERISTICS

Normalized Effective Transient Thermal Impedance, Junctlon-to-Ambient (TO-92)

Duty Cycle

0.5

0.2
0.1
RthJA
(Norm.)

0.1

r"";...-'"

~

-

~

Notes:

0.05

~

tt~

/'\.

\

2. Per Unit Base = RthJA = 156°C/W
3. TJM - TA = PDMZthJA(t)

sinrle lUlie,
0.01

On-Resistance

VS.

Gate to Source Voltage

6.0

1K
VDS

5.0

l\

4.5

I -rO.5

'.\\:

4.0
3.5
3.0
2.5

Off State Current

TJ=25°C-

~ -d.25 ~

IDSS
(nA)

~
~ ~ ........

V

10
l/

0.1

10
VGS (V)

20

-60

-20

20

140

180

..

Load Condition Effects on Switching
V DD 25 V
RG 25.0.
VGS o to 10 V

V DD - 25 V

tf

,

(ns)

100

100

I- R L -50.o.
I- VGS o to 10 V
I- ID = 0.5 A

t

10V-

/

0.01

o

r1=

96YL

100

A

Drive Resistance Effects on Switching
100

10 K

10 K

I I I

- I D =O.l A

rDS
(.0.)

1K

10
100
Square Wave Pulse Duration (sec)

0.1

5.5

~~

1. Duty Factor, D =

0.01

10

i--'

td(oL)

t

(ns)

td(OFF)

10

r-

"-

t,

"""-

td(ON)

T
10

~

-ltd(FNI

~t;""_

I
100

RG (.0.)

1
10

~

/

t',
100
ID (mA)

1000

7-141

.:r-Siliconix

VNDQ12

~ incorporated

TYPICAL CHARACTERISTICS
Body Drain Leakage Current

Equivalent Input Noise Voltage vs. Frequency

sao

10 4
"V O; = IslJ I

,

~ TJ - 25°C

TJ = 2SoC

400

10 3
96 V I

Vos

1\

300
en
(nV/\IHz)

10 2
10
(nA)

\'10mA

,

200

,

10

, 10 V : = = !

,

No=1 mA
100

a

10

I1tI

10-1

......... r-.

J-,.

10-2

100

1K

10 K

-1.0

-O.S

o

0.5

1.0

1.S

V GS (V)

f (Hz)

Output Conductance vs. Drain Current
600
500

80,l.ls, 1% 'Duty Cycle
Pulse Test
T J = 2SOC

400
gas
(J!S)

V

V
Vos=7.SV

300
200

II

100
0

V
10

1K

100
10(mA)

Transient Thermal Response (TO-20SAD)

D - 0.5
0.2
R1hJC
(Norm.)

0.1

..2J...

-

--

~~

fo-"

~O.OS

Notes:

BLJL
tt~

0.02
3;0.01
sing/e

P~IS~

1. Duty Factor, D =

!~

2. Per Unit Base = R1hJc = 2S °C/W
3. TJM - Tc = POMZlhJC(t)
0.01
0.1

10

100
tl (sec)

7-142

1K

10 K

VNDQ20

.:r-Siliconix

~ incorporated

N·Channel Enhancement·Mode MOSFET
DESIGNED FOR:
•
•

Switching
Amplification

TYPE

PACKAGE

DEVICE

Single

TO-92

• BS107
VN2010L, VN2020L

Chip

• Available as above
specifications

FEATURES
•
•

High Breakdown> 200 V
Low rDSlon) < 10 n

GEOMETRY DIAGRAM

Gate Pad
0.010
(0.254)
0.0087
(0.2209)
Source Pad
0.0070
(0.1778)

-lL..1Q.

(0.254)

T
1
0.038
(0.965)

7-143

~Siliconix

VNDQ20

~ incorporated

TYPICAL CHARACTERISTICS

Output Characteristics

1.0

~

O.B

SV

3.S V

"L:V

h

10
(A)

r'-

0.2

0.2

3V
12 . S

"

V

0.1

2V

o

40
60
VOS (V)

20

BO

o

100

~
~~

,

TJ

;

2SoC

/

I.
III. V
r/ L.o--

10
(rnA)

20

10

o

~V

•

o

l

11.6

~

.1 1 . 4

~

2
3
Vos (V)

7-144

S

4

S

100

0
0.4

---

O.B
1.2
Vos (V)

1.6

2.0

2

0

V GS ; 10

Gate Charge

lS.0

V

1

10; 0.1 A
12.S

V./ V

10.0

~

VGS
(V)

V

7.S
S.O

0.4

0.6
10(A)

O.B

1.0

V

VOS; 1 0 0 V 7

o
0.2

3

V GS (V)

2.S

o

4

200

2.S

o

2V

(rnA)

/

S.O

3V

300

1.2 V
1.0 V_ I-- 0.6 V f--

10.0

ros

..,... r-

~

On-Resistance

(.0. )

I

10

12.S

7.S

rsv

~~
~

400

1;!V
1 .B

4V

Transfer Characteristics

~2.~V

11/ I'J

30

~

SOO

V) I

40

~

~

o

Output Characteristics for Low Gate Drive

so

VGS - 10 V ~/

~~ ~

0.3

Y

0.4

TJ ; 2SoC

0.4

4V

[

10

o

I

:--V GS ; 10 V

l

0.6
(A)

Ohmic Region Characteristics

O.S

L

o

/
2S0

-160V

SOO
7S0
Og (pC)

1000

12S0

~Siliconix

VNDQ20

~ incorporated

TYPICAL CHARACTERISTICS
Capacitance

Transconductance
500

60
Pulse Test
80.u.s 1 %
Duty Cycle

400

50
40

300
gFs
(mS)

C
(pF)

125°C

200

30

I

c-

VG !! = 0 V
f = 1 MHz

~,\oss

20
100

0

a

100

200

300

400

~

10

20

30

40

50

On-Resistance vs. Junction Temperature

Source-Drain Diode Forward Voltage

I

VGS= 4.5 V

10=50~

1.75

,

TJ = 150°C

I

~ v,-o rnA

1.50

(Norm.) 1.25
1.00

0.50

a

Vos (V)

2.00

0.75

o

500

10 (rnA)

2.25

ros

\ r-...

10

V
-50

/'
-10

V

~

Is
(A)

I I

0.1

I

I

30

I

70

110

0.01

150

V

)'

a

0.2

0.4

TJ

0.6

=r
0.8

c
1.0

Vso (V)

..

Threshold Region
10
5V

Vos

II

TJ = 150°C'

I

10
(rnA)

1/

I
0.1

O°C

0.01

I

I

I

55°C

o

0.4

I II
0.8

1.2
1.6
VGS (V)

2.0

2.4

2.8

7-145

ICTSiliconix

VNDQ20

.LJ# incorporated

TYPICAL CHARACTERISTICS
Normalized Effective Transient Thermal Impedance. Junctlon-to-Amblent (TO-92)

HthJA
(Norm.)

\

1. Duty Factor. D =

0.01

t
t}

2. Per Unit Base = R thJA = 156°C/W
3. TJM - TA = POMZthJA(t)
0.01

0.1

10
100
Square Wave Pulse Duration (sec)

1K

On-Resistance vs. Gate to Source Voltage

Off State Current
10 4

28

VGS - 0 V

TJ = 25°C
24

'fus..

110 =

10 2

koo mA

16

loss
(nA)

J50t

12

10 V
//

'1"10-1 I

50 mA

l I

4

o

8
12
VGS (V)

4

16

-60

20

Drive Resistance Effects on Switching

I

-20

20

100

180

Load Condition Effects on Switching

VOO - 25 V
RL - 250.0.
V GS - 0 to 10 V
10=100mA

50
I""

20

20

"-

10

tf
td(OFF)

t

(ns)

r-- ......

10

VOO - 25 V
RG-25.o.
VGS - 0 to 10 V

I""td(OFF)

5

5

~

~

tr

I

2

'2
tTT
10

20

50
RG (.0.)

7-146

140

100

50

(ns)

//

10-2

o

100

t

160 V
L

10

,\K~l

8

-'

LL

10 3

I

20
rOS
(.0.)

10 K

100

1
0.01

0.1
10(A)

.,.j._tl~l±i

iJ(~~r
Itt'
1.0

VNDQ20

.:r-Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Equivalent Input Noise Voltage vs. Frequency

Body Drain Leakage Current
105

100

=
=

VDS 5 V
TJ
25°C
80

60
en

(nVNRZ)

\

10m~

20

o

,

TJ

25°C

I

10 3

'\ ,~N = 1 mA

40

~

10 4

ID
(nA)

I"-~

i'-

Vos

/y
100 V

10 2
//

10
///

~ :::
10-1

10

100

-0.4

10 K

1K

160 V _

-0.2

o

)OV

0.2

0.4

0.6

f (Hz)

Output Conductance vs. Drain Current
10 K
80 .lJ.s. 1% Duty Cycle
Pulse Test
25°C
T"
1K
Vos

J...H1

90S

(.lJ.S)

100

10

20 V

12 V

..-t"

10

100

1K

10 (mA)

7-147

ICrSiliconix

VNDS06

~ incorporated

N·Channel Enhancement·Mode MOSFET
DESIGNED FOR:
•
•

Switching
Amplification

TYPE

PACKAGE

Single

TO-206AC

FEATURES
•
•
•

Low rDS(on} < 10 n
Low Cost
Surface Mount Package SOT-23

Quad

TO-237

• VN2222LM

SOT-23

• VN0603T, VN0605T
2N7002

14-Pin
Plastic

• VQ1000J

14-Pin
Dual-InLine

• VQ1000P

T
1
0.027

(0.686)

7-148

• VN10LE
• 2N7000, 2N7008
VN0603L, VN0610LL
VN2222LL

GEOMETRY DIAGRAM

Source Pad
0.0041
(0.104)
0.0049
(0.124)

DEVICE

TO-92

Chip

Gate Pad
0.0041
(0.104)
0.0049
(0.124)

I

• Available as above
specifications

VNDS06

~Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Ohmic Region Characteristics

Output Characteristics

1.0

II- VG

10
(A)

= 10 V

I

/'"

0.8

1.0

7V

s~ _

O.S

I
II.,.
V-

0.4

'I

I

(A)

J
4V

0.2

/
0

1S

8
12
Vos (V)

4

0.4

o

0
20

./

80

/

so

/

10
(mA)

fb

31V

'o

2

o

,
o

..- /

-r

I

TJ = -55°C

5

~

1

0.2

I I

J
l/

0.1

o
0.8
1.2
Vos (V)

1.S

2.0

125°C

~

10
(A)

3.0 V

25°C

A

0.3

v'

f/Ij

v-

0.4

I

3.12

4

Transfer Characteristics

2!4)
0.4

3

VOS (V)

~ls~- -

/,'/./ " ,

lV
11//

I

3.4 V

~

1//

40

20

I'

5V

~ yo

0.5

TJ = 25°C

I

/

4 1V

Output Characteristics for Low Gate Drive

100

J
slv

~V
J l j.....

0.2

3~ -

.- -

h V.

10

5V

/ / V
'/. /

25°C

TJ

7V

...... ..-

/ V

0.8

O.s

VaJ

VGS =10Vj

o

2

Vos= 10 V

4

S

8

10

V GS (V)

On-Resistance

Typical Gate Charge

s

5

10=0.5A
5

4

--

3

VGS =10V

rOS
(.0. )

2

o

o

0.25

0.50

0.75
10 (A)

....- .

1.00

/.

4
V GS
(V)

VOS= 30 V'y
3

2

1.25

1.50

o

V
o

V
30

/

SO
90
Og (pC)

//

~
)
48 V

120

150

7-149

..

VNDS06

.:r"Siliconix

..L;II incorporated

TYPICAL CHARACTERISTICS
Typical Transconductance

Capacitance

r---~-----r----------~~~

50

200 ~--~----~~~~----r----i

40

250

Vas = 0 V
f = 1 MHz

150

30

gFS
(mS)

C
(pF)
20

100

50 H f - - i - - - i - voS = 7.5 V-I------f
80 jJ.s. 1 % Duty Cycle
Pulse Test
0
100
200
300
400
500
0

~

o

~

-

10

r-:::

!.-C lss

20

30

40

On-Resistance vs. Junction Temperature

Source-Drain Diode Forward Voltage

I

Vas=10V

1.50

V

ros
1.25
(Norm.)
1.00

V
-50

/

/

50

T J - 125°C

/

I

I I

I I

Is
(rnA)

V

V

-

i' Coss

Vos (V)

1.75 1--10 = 0.5 A

0.50

o

~....

10 (rnA)

2.00

0.75

10

\

II

0.1

TJ - 25°C

J

-10

30

70

110

II

0.01 0

150

0.5

1.0

1.5

2.0

2.5

Vso (V)

VN10LE - Safe Operating Area

Threshold Region
10

5
VO~-10V

T J = 150°C/

I I
se~ I

I

/I -55°C

Note 1

10

10

(rnA)

I
0.01

I
o

0.5

1.0

(A)

I
L25°C

J

0.1

V
0.1

..
.
"- .

Tc - 25°C
Single Pulse
R thJC 83°C/W

,
I
1.5
2.0
Vas (V)

=
=

--

10jJ.S
100.l1S =

0.01
2.5

3.0

3.5

- TtilTIWl1

1 ms

c:

111b ms

IWO m~ =
dc

I

III

10

100

200

Vos (V)
10peratlon In this area may be limited by rOS(ON)

7-150

fCTSiliconix

VNDS06

~ incorporated

TYPICAL CHARACTERISTICS
Normalized Effective Transient Thermal Impedance. Junction-to-Amblent (TO-92)

Duty Cycle

0.5

0.2
0.1
RthJA
(Norm.)

~

1-1-

Notes:

0.05

0.1

~-

~
tt:-:J

/\.

\
0.01

-',

1- Duty Factor. D =

0.01
Sint e IUI,e l

0.1

0.5

5
10
50
100
Square Wave Pulse Duration (sec)

500

On-Resistance vs. Gate to Source Voltage

I-- + oJ

5
4

1\\

3

10 = 0.1 A

\ 1.0

.\ \..

2

10K

,,

OV

VGS
10 2

A

48 V

Vos

~
loss
(nA)

~

~~ ~

I
I

V

10

Vps - 10 V ;;;;;;
10-1

"

11'/

10-2

10-3

o

8

12
VGS (V)

4

16

-60

20

Drive Resistance Effects on Switching

-20

20

60
100
TJ (OC)

140

180

..

Load Condition Effects on Switching

100

100
Voo 15 V
RL 23.0.
VGS o to 10 V
10=0.5A

50

Voo 15 V
RG = 25.0.
VGS - 0 to 10 V

50

20
t
(ns)

5 K

Off State Current

TJ = 25°C
6

o

1K

10 3

7

ros
(.0. )

!~

2. Per Unit Base = R thJA = 156 ° C/W
3. TJM - TA = POMZthJA(t)

20

t

10

(ns)

10
td(OFF)

5

I~N)
tr

II
1

2

5

10
R G (.0.)

5
td(ON)

~t)

2
1

td(OFF)

20

Ii

50

k"tr

2

100

1
0.1

I~

.(l'

T ii'l

0.2

0.5

1.0
10(A)

2

5

10

7-151

.HSiliconix

VNDS06

incorporated

TYPICAL CHARACTERISTICS
Equivalent Input Noise Voltage vs. Frequency
250

\10~111~~1

200

1S0

Vos = S V
TJ = 2S o C

TJ

1\

\

I

10 1

~

~

30 V

10
(nA)

'I'

10 V
I

10-1

....

II

10

I

~Vos-48V

10mA

so

2S o C

I

10 2

\

100

a

Body Drain Leakage Current
10 3

....... r-.

. " JT

10-2

:"'"-1100

10-3
-O.S

10 K

1K

I

a

O.S

1.0

1.S

2.0

V GS (V)

f (Hz)

Output Conductance vs. Drain Current
10 K

1K

gas
().lS)

80 ).ls, 1% Duty Cycle
Pulse Test
TJ - 2S o C

~

~~IIIIIII

V s

~

I

20 V

SV

..... 1--

100

10

1

1

10

1K

100
10(mA)

Transient Thermal Response (TO-206AC)
D - 0.5

---

0.2
R thJO
0.1
(Norm.)

~ ~ ;;;iii

0.1

-~

"'~""
Notes:

0.05

~t~

0.02~

~".

~

1. Duty Factor, D

1 0 . 01

Singie PI's,

~

II

=

0.01
0.1

7-152

!;

2. Per Unit Base = R thJC = 83°C/W
3. TJM - To = POMZlhJO(I)
1.0

10

100

1K

10 K

VNDV40

.:rSiliconix

~ incorporated

N·Channel Enhancement·Mode MOSFET
DESIGNED FOR:
•
•

Switching
Amplification

TYPE

PACKAGE

Single

TO-205AD

FEATURES
•
•

High Breakdown> 400 V
Low rDS(on) < 12 n

DEVICE

• VN4012B

TO-92

• VN3515L, VN4012L

Chip

• Available as above
specifications

GEOMETRY DIAGRAM

Gate Pad
0.005
(0.127) 0.007
(0.178)

..

0.058
(1.47)

Source Pad
0.006
(0.152)
0.007
(0.178)

~1
0.053
(1.35)

•

I

7-153

.-r-Siliconix

VNDV40

~ incorporatec

TYPICAL CHARACTERISTICS
Ohmic Region Characteristics

Output Characteristics

:J

500

3.0 V

~~

10

~ P': ~

200

100

0.2

-

2.0 V
T J = 25°C

o

o

100

200
300
Vos (V)

400

500

/

~~

o

T~ = ~5°CI

VGS

80

(rnA)

/

40

v

160

10
80

Ih

1.6 V
40

,l~~

1.4 V f-

Ir'

0

o

0.4

0.8
1.2
Vos (V)

1.6

0

2.0

2
3
V GS (V)

On-Resistance

Gate Charge

13

12
rOS

/

(.0.)

11

10

/'"

o

/'

V

/

/
V

JI7'

200:V
326 V

2

L
I

0.4
10 (A)

/

-'-

.j

/
/

/

/

0.2

5

4

3
VGS = 4.5 V
T J = 25°C

7-154

I

VOS = 15 V

J

(rnA)

..,.~

14

9

5

4

120

1.8 V

'/

20

o

---

V

V

10

3

Transfer Characteristics

200

V

60

2.dv

VOS (V)

=2.0 V......

V

~ fo""""
2.5 V

~V
F'

2

Output Characteristics for Low Gate Drive

100

~

-1.......... ~ ~

~ ~ V"

300

2.5 V

o

1

3.0V~

VGS = 10 V

(rnA)

0.4

14.0 1V _

400

I I I I::: I

10
(A)

T~ = ~5ocl

0.6

o

I
o

V

/
10= 0.1 A
200

400

600

Og (pC)

800

1000

VNDV40

~SilicDnix
..z::.
incorporated
TYPICAL CHARACTERISTICS

Capacitance

Transconductance
500

120
Vas = 0 V
f = 1 MHz
100

400

80

~

C 1ss

300

C
(pF)

gFS
(mS)

60

200
40
100 1ff--+---4- 80p.s, 1% Duty Cycle
Pulse Test
Vos = 7.5 V
0
20
30
40
50
0
10
10 (mA)

20

o

1\

I\~OSS

,\,.'
C
rs

o

10

Vas = 4.5 V

110 = 0.1 A-7J

2.00
10=0.02A1.75
ros
(Norm.)

1.50

./

1.25

0.50

V
-50

TJ

125°C,

'#'

I

I IT

Is
(A)

II I

0C
J = 25

0.1

V

I

-10

30
70
TJ (OC)

110

0.01

150

I I
o

1.0

0.5

Threshold Region

1.5
Vso (V)

2.0

2.5

Safe Operating Area

10

10
Vos

==
1.0

10 V
=TJ - 150°C
125°C'

10
(mA)

,

I

I II

I II
o

0.5

~ Note 1

e-

10
(A)
0.1

I
1.0
Vas (V)

. ,

/

10

1 ms

~

0.01

1.5

100p.S

.

To 25°C
Single Pulse
R thJO = 25°C/W
Part: VN40128

55°C -

I

10JJS

§' See

/<- ~ 25°C_

/

0.1

I

-f.I

I

0.01

50

/'

1.00
0.75

/
,/

40

Source-Drain Diode Forward Voltage

On-Resistance vs. Junction Temperature
2.25

20
30
Vos (V)

100

10 ms

~~~Ims
1000

Vos (V)
'Operation In this area may be limited by rDS(ON)

7-155

..

VNDV40

~Siliconix

~ incorporated

TYPICAL CHARACTERISTICS

Normalized Effective Transient Thermal Impedance. Junctlon-to-Amblent (TO-92)

0.5

0.2
RthJA
(Norm.)

0.1

~jtilill 11_111111111111111
U L
I

"u,~~.

ro.05

~
P OM

-0.0

tt~

0.05

f/\.

0.02

1\

0.01
Sin fie

0.01

= ~~
=
= 156°C/W

1. Duty Factor. D

2. Per Unit Base R thJA
3. TJM - TA POMZthJA(t)

~jj

0.1

=

0.5

1.0

5

10
50
100
Square Wave Pulse Duration (sec)

500

On-Resistance vs. Gate to Source Voltage

1 K

10 K

5 K

Off State Current

12

~ ~Io = 100 mA

1= Vr;"

T J = 25°C

OV

11

10
rOS
(.n)

') ~

9

Vos - 320
~

loss
1
(,UA) 10-

20 ;'"A

8
7

o

t

(ns)

I

10-4

4

8

12
V GS (V)

16

-60

20

Drive Resistance Effects on Switching
100

==

V~Il-10V
y

10-3

6
5

")'f,===I

VOO 25 V
RL - 250.n
V GS o to 10 V
10 - 100 mA

10

-20

20

60
100
TJ (OC)

140

180

Load Condition Effects on Switching
100

--

VOO 25 V
RG 25.n
V GS 0 to 10 V

......

=

I'

,Ltd(OFF)

J

.1 1 1

~~~o:r

tf I

t

(ns)

10

tf

i--td(ON)
td(ON)

/(,

t,ll

I
10

20

50

1
100

10

100
10 (mA)

7-156

1000

..:F'Siliconix

VNDV40

~ incorporated

TYPICAL CHARACTERISTICS
Equivalent Input Noise Voltage vs. Frequency

"1

200

160

120

0

=

1~,\I.

Vos = 5 V
TJ = 25°C

1\

1\

Body-Drain Leakage Current
10 4

10 2
10

1'1

80

(nA)

10 mA

40

o

I

I

10 V

1\

"

en
(nV/VHz)

320 V

Vos

I

10 3

~~,...

10
1

J

10-1

t-...

TJ

10-2

100

10

1K

-0.5

10 K

I

o

0.5

1.0

25°C

=t

1.5

2.0

VGS (V)

f (Hz)

Output Conductance vs. Drain Current
18
80 p,s. 1% Duty Cycle
Pulse Test
TJ 25°C

16

= 50 V

VOS

I I

7.S V

=

14
gas
(p,S)

12

10
8
6
4

./
10

0.1

100

lo(mA)

..

Transient Thermal Response (TO-20SAF)
1.0
0.5

D

--

[;,..,

0.2

RthJO
(Norm.)

0.1

~
~

~~

-"'"
~

-

~

~0.05

Notes:

~1-0.02
-0.01

tt:-=J

I I

1. Duty Factor. D =

Single Pulse

0.01

0.1

~

"

1.0

!~

2. Per Unit Base = R thJO = 25 0 C/W
3. TJM - To = POMZthJO(t)

10

100

1K

10 K

tl (sec)

7-157

VNMA06

tcrSiliconix

~ incorporated

N·Channel Enhancement·Mode MOSFET
DESIGNED FOR:
•

TYPE

Switching

Single

FEATURES
•

High Speed for Military Applications
(see VNDQ06 for Industrial Applications)

GEOMETRY DIAGRAM

0.012
(0.304)

0.010

T
0.077

(1.956)
(0.254)
Source Pad -I+--+---HIII+
Gate Pad ---1f+--l---HIII0.0094
(0.24)
0.0095
(0.241)

9 mil

7-158

I

PACKAGE

I

DEVICE

TO-205AD. JANTX2N6660

~Siliconix

VNMA06

~ incorporated

TYPICAL CHARACTERISTICS
Output Characteristics

I

2.0

1.6

Ohmic Region Characteristics

2. 0

9V

Vas = 10 V

'/

8V

r;'"

7V

1.6 1--t--t-+---1--/-+--f-~",","

1 .2

1.2
10
(A)

r;'"

6V

0.8

rr

1--t--t-+---1--/n..r:~~1-

10
(A)

5V

0.4

r--...,.....-r-~"T"--r-"T"""...,.......,r-...,.....-,

4V

0.4
3V

0

a

10

20
30
Vos (V)

40

2

50

Output Characteristics for Low Gate Drive
100

/
//

80

'/

60

20

""'I I

Transfer Characteristics

I

I

I

T J = 25°C

-r

400

1---+--+---/

300

1---t----1---+---8+

200

1---t----1---+-:;..--II-'---I

100

1---/---t--9'#----1----I

10
(rnA)

Lt

, ,.. '1/

2.2 V

j

o ~
o

tot
1.8 V

0 ......0.4

0.8
1.2
Vos (V)

1.6

o

2

.........:::;;,"""'-""""-......- - - ' - - - - - '
2
3
4
5
Vas (V)

On-Resistance
4.0
TJ =

~5°C

10= 0.5 A

3.0
ros
(.0.)

Vas=

/
lOV

I

20 I - - - - t - - - + - - - t - - - - i - - - I
16

1---t----1---+---/--1

12

1---t----1--

./

2.5

1.5

Gate Charge
24 r----r--"T"---r----r---,

3.5

2.0

5

t6t

U /'
1/1 ,

10
(rnA)

40

./

4

500 r-----r---r--...,..--'"T""""TTT.,

2.8 V

Vas = 3 V ' /

3

Vos (V)

--

o

0.4

-

~

0.8

./

1.2
10 (A)

1.6

2

8

I---f---+-~~~-~-__I

4

I--~~-+--_+---t--__I

160

320

480

640

800

Og (pC)

7-159

~Si6conix

VNMA06

~ incorporatec

TYPICAL CHARACTERISTRICS
Capacitance

Transconductance
500 ......-....,.--...,----,---r----,

200

VOS= 10 V
Pulse Test 60.us
Duty Cycle 1 %

400

-..,..==J

160

300 I---+--:;."..~---:::!__
gFS

(mS)

C
(pF)

120
60

100 HLF--f---+---\---II---J

600
400
10 (mA)

200

600

40

o

1000

~

Coss

~
o

C rss

10

20
30
Vos (V)

2.00
10= 11
1.75
~

1.50
1.25
1.00
0.75
0.50

/'

V

V
-50

V'

,

A~

~A

(A)

J /

2S·C
_I-

I

I

I

I

'I

-10

30
70
T J (·C)

I

I

If

J

0.1

I

I

-TJ = 12S·C
Is

110

0.01

150

o

II

II

1/-:5·1

i
0.2

Threshold Region

0.4
0.6
Vso (V)

0.6

1.0

Safe Operating Area

10

10
lS0·C

= TJ

,

J..

II
10
(mA)

I

I

I

0.1

I

,

I
o

I'
0.1

0.6

1.2
1.6
VGS (V)

0.01
2.0

2.4

2.6

Part: I

I%O~s

1111
dc

T c =2S·C
T J = lS0·C
Single Pulse
R thJC = 20·C/W

I
0.4

11\1 msl
10 ms

10
(A)

I-wc

111~0.us

,

See
Note 1

2S·C_

I
0.01

50

I

VGs= 10V

ros
(Norm.)

40

Source-Drain Diode Forward Voltage

On-Resistance vs. Junction Temperature
2.25

I
VGS = 0 V
f = 1 MHz

160 _

~~~~I~PJA~T~
100

10

1 K

VOS (V)
10peratlon in this area may be limited by rOS(ON)

7-160

VNMA06

~Siliconix

.L;II incorporated
TYPICAL CHARACTERISTICS
On-Resistance vs. Gate to Source Voltage

Off State Current
10 4

7
T J = 25°C

6

5

4

//

//

10 V
IDSS
(nA)

\' .\

3

48 V

10 2

1A

\

VOS

10 3

j+"-:-0t A

~~

10=0.2A
2

//

10
//

::::!I!o

10-1

o

//

10-2

o

4

12
V GS (V)

16

8

-60

20

Drive Resistance Effects on Switching

140

160

Load Condition Effects on Switching

100

100

~

Voo

Voo - 25 V
RG= 25.n.
VGS = 0 to 10 V

25 V

23.n.
I- RL
I- V GS = 0 to 10 V
I- 10=lA

t
(ns)

-20

Ktf

t
(ns)

10

'\
10

tdloFF

t,

--

~

tf

I
10

-

tdlON'7'

tdlON) t1 IO jF)I-

...........

1
50

0.1

100

1
10(A)

R G (.n.)

Equivalent Input Noise Voltage vs. Frequency

Body-Drain Leakage Current
10 4

500

~IO = 10 mA
400

300
en
(nV/VRZ)

10

Vos = 5 V
TJ = 25°C

:: T J

I~~

200

r/

Vos - 48
10 2

~

1

25°C

10 3

10
(nA)

mA~

v-g::.

10 V

:=

/,

10
/,

~

100

10-1

,..,

t-0

10

100

1K
f (Hz)

10 K

o

1.5

V GS (V)

7-161

..

H

VNMA06

Siliconix

incorporated

TYPICAL CHARACTERISTICS
Output Conductance vs. Drain Current
80J,ls. 1% Duty Cycle
Pulse Test
T J = 25°C

2

I
II

gos
(mS)

L
o

....
0.1

10

100

10 (mA)

Transient Thermal Response (TO-39)

D - 0.5

-

0.2
0.1
0.1

0.05~ j;:Ot;

~

.-?

10Notes:

~~

3nSL
~t~

"'If. 02 ;00"~
0.01

~n~le PUI~e I
I I I I
0.01

0.1

1

1. Duty Factor. D =

III
10

100
tl (sec)

7-162

!~

2. Per Unit Base = RthJO = 20°C/W
3. TJM - To = PoMZthJO(t)

_L

I I IIIIII
1K

I

I I II
10 K

VNMA09

crSiliconix

~ incorporated

N-Channel Enhancement-Mode MOSFET
DESIGNED FOR:
•

Switching

TYPE

PACKAGE

DEVICE

Single

TO-205AD

• JANTX2N6661

FEATURES
•

High Speed for Military Applications
(see VNDQ09 for Industrial Applications)

GEOMETRY DIAGRAM

T

0.012
(0.304)
0.077
0.010
(1.956)
(0.254)
Source Pad -+t--+--+
Gate Pad -H--I---\0.0094
(0.24)
0.0095
(0.241)

9mil-ll-

'-----

1-

III
0.041
(1.041)

--.J
-I

7-163

a'r'Siliconix

VNMA09

~ incorporated

TYPICAL CHARACTERISTICS
Ohmic Region Characteristics

Output Characteristics

2
!VGS = 10V

rr

1.S

81V -

0.8

I

r

0.8

10

5V-

(A)

0.4

4V
0.4

o

0.2

3V
2V

o

20

40
SO
Vos (V)

o

80

100

~

VCS = 3 V

L

80

(rnA)

20

o

A

3~
2

2

3

r-

-= r-

t- r4

5

4

5

1

2.4 V
0.3

1

1

10
(A)

2.2 V

0.2
12.01v

I'

0.1

1.8 V

11/
I.

1.S V
0

o

0.4

0.8
1.2
Vos (V)

1.S

2

0

2
3
V GS (V)

Gate Charge

S

)

4

3

7-164

4t -

0.4

1

VGS=110V
TJ = 25°C

o

""""

~

On-Resistance

2

./

I=-

Transfer Characteristics

5

rOS
(.0. )

.~

~

~ !--

12.S IV
..L

2.8

'"

40

1
5V

0.5

I/L
rt 1--1'"'
II'"
MI ,,- r-

10

V

Vos (V)

"I / ' i"""

so

VA
I. 1:7/
~ V-

o

Output Characteristics for Low Gate Drive
100

/

' j VL

I

sv

SV_ l-

/

V..... ~

TJ = 25°C ' /

O.S

10

(A)

1/

71V

1.2

7V/ ~I

VG = 10 V

g'V

...-

o

-0.4

~

0.8

./

10= 1 A

5

V

/

4

VGS
(V)

Vos= 45 V /
3

L

2

1.2
10 (A)

1.S

2.0

o

/

o

/
50

11'"/

.....

72V

V

100
150
Og (pC)

200

250

VNMA09

~Siliconix

~ incorporated

TYPICAL CHARACTERISTRICS
Capacitance

Transconductance
500 r---~----~---.r----r----'
VOS= 10 V
Pulse Test BOJ,ls
Duty Cycle 1%
400

200
VGS= 0 V
f = 1 MHz
180
160

300 ~---4----~----+-~~~~~
C
(pF)

gFS
(mS)

120 \- C 'SS
BO

100 ~~~~--~----+-----r----;

200
300
10 (mA)

100

400

40

o

500

~c=
.~

~

~

1.50

~~

1.25

0.75
0.50

,/
-50

20
30
Vos (V)

l/

~A

f--TJ

Is
(A)

=

0

0.1

150°C

0.01

150

o

I

I

I

II

'I
J

7 I

0.2

0.4
0.6
Vso (V)

O.B

1.0

..

Safe Operating Area

25°C

I

/ I

I

I

Threshold Region

- - 125°C

0

I

110

7

125 c1i5 Cj FT-SSOC-

I

10

10
(mA)

50

7

I

I

/'

-10

::TJ

40

Source-Drain Diode Forward Voltage

10=~

1.75

1.00

10

I

VGS= 10V
2.00

ros
(Norm.)

C rss

o

On-Resistance vs. Junction Temperature
2.25

;-....,

10

==

./

See Note 1

",

55°C ~

100J,ls

lLI=

10

0.1

I

I

/ V-

I

0.01

10 ms

O.S

do

Tc 25°C
TJ - 150°C
Single Pulse

I
0.4

lOti ~s

0.1

I

I-

If
o

(A)

RtJF 1=1
0.01
1.2
1.6
V GS (V)

2.0

2.4

Tg~~/wl
10

2.B

100

1K

VOS (V)
10peratlon

In

this area may be limited by rOS(ON)

7-165

H

VNMA09

Siliconix

incorporated

TYPICAL CHARACTERISTICS
On-Resistance vs. Gate to Source Voltage

7
1

6

5
ros
(.0. )

3

l-

;-~

TJ = 25°C
d.5

~

1\\ \
r-llJ.n~ ::::::: b-.Ioo.

loss
(nA)

"

2

o

~

o

8

12
V GS (V)

4

Off State Current

16

10

o

20

Drive Resistance Effects on Switching
100

F

Vos 25 V
R L -25.o.
V GS -10V

t

1=
t-

t

10

(ns)

10

td(OFF)
I

I

50

."

td(OFF)
td(ON)
t,

I

J

1

100

1

0.1

R G (.0.)

400

300

r\1~/11'

200

Body Drain Leakage Current

F TJ =150C~ .L

Vos = 5 V
TJ=25°C

I,\~

~'72V

"

en
(nV/VRZ)

10~1 rnA

100

10

10(A)

Equivalent Input Noise Voltage vs. Frequency
500

120

tf

t
20

70

Vos - 25 V
RG 25.0.
VGS = 10 V

td.'ON)
t,
I
tf

10

60

Load Condition Effects on Switching

100

(ns)

30
To (OC)

10
(nA)

~

/I

10
I/,

'-

-

10 V

JL

i"""

0

10

100

1K
f (Hz)

7-166

10 K

10-2 -2

-1

o
V GS (V)

2

3

VNMA09

ICrSiliconix

~ incorporated

TYPICAL CHARACTERISTICS
Output Conductance vs. Drain Current
1400
80 J.lS, 1% Duty Cycle
Pulse Test
TJ=25°C
V DS =7.5V

1200
1000

gos

800

/

(p,S)

600

1/

400
200

o

l-~
10

1

100

1K

ID(mA)

Transient Thermal Response (TO-39)

0-0.5
~

0.2
R1hJC
(Norm.) 0.1

0.1
0.05

J,..o

~

~I'

Notes:

~
~t~

0j.2

~iS~.0.1

1. Duty Factor, 0 =

Slng:e PilSj

~~

2. Per Unit Base = R1hJC = 20°C/W
3. TJM - Tc = PDMZlhJC(I)
0.01

II
0.1

10

100

I

II 111111
1K

I

I I I III
10 K

t, (sec)

..
7-167

.:rSilicanix

VPDQ20

~ incorporated

P-Channel Enhancement-Mode MOSFET
DESIGNED FOR:
@

•

Switching
Amplification

FEATURES
•
•

High Breakdown> 200 V
Low rDSlon) < 20 n

Single

TO-206AC

• VP2020E

TO-92

• VP2020L
BSS92

GEOMETRY DIAGRAM

T
1
0.038

(0.965)

Source Pad
0.0070
(0.1778)

....lh1Q.

(0.254)

7-168

DEVICE
--

PACKAGE

Chip

Gate Pad
0.010
(0.254)
0.0087
(0.2209)

I

TYPE

• Available as above
specifications

~Siliconix

VPDQ20

~ incorporated

TYPICAL CHARACTERISTICS
Output Characteristics

Ohmic Region Characteristics

-sao

-1.0
V s=-10Y

/

-0.8

t

-0.6
10
(A)

-0.4

-8 V

",--

~

I

;-6

-SV

-300
6V

i;"""

Y

if
o

-3 V
-10

-20
-30
VOS (V)

-40

/~ :::;;.:: ...- ~

rI--:;

o

-so

~

o

V

-60

V

10
(mA)

V
V V

~

-20

~

I..---"

~ .....

o~
o

10
(mA)
-3.0 V

-40

.1_2 . dV

-20

o
-0.8
-1.2
Vos (V)

-1.6

fJJ

-2.0

~
o

-1

-12

V

20

----

lS
(.0.)

l

l,/

-8
-10

::!...

VGS
(V)

-160

S

-2

-so

0
-100
-lS0
10(mA)

-200

-2S0

v:-f_)'

-6
-4

o

-5

VL
I /

I

10= -0.1 A

10

o

-4

Vos = -100 V
-10

rOS

~

-2
-3
VGS (V)

Gate Charge

I.
~
VGS= - 4 ' S 7

TJ = 2SoC

125°C

I

25°C

On-Resistance

2S

V

VOS = -15 V

;.....
-0.4

-5

-60

/

...-

'L

I
TJ = -55°C

-80

/'

~V
V
~

-40

-4

-2
-3
VOS (V)

Transfer Characteristics

VG =-4VY
-3.6V

-80

-4 V

_31V

-1

-100

I
I
I
TJ = 2SoC

",

:,...0

~

Output Characteristics for Low Gate Drive

-100

I

~ ~ ~4.SV

~

-100

y

. / ~ I----"

10
(mA) -200

-S V
-4 V

o

JGS LldviL

-400

-7 V

,

-0.2

I
I
I
I- TJ = 25°C

I

/

/

I

/

/

o

0.5

1.0
1.5
Og (nC)

2.0

2.5

7-169

..

VPDQ20

.:r-Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Capacitance

Transconductance
250 r--------'T"""--~-....,
80 j1S, 1% Duty Cycle
Pulse Test
Vos = -7.5 V
200 I-;;;.:;..-r---;----t---i-==;=i

120
Vas = 0 V
f = 1 MHz
100
80

150 I---t--~"'---t-__::=I---'"'I
gFS
(mS)

C
(pF)

,

60

100 1--7"f~~+-_=::!---I"""'==i

i\

40
50

t+N~--_t_---t---t----I

20

OL-_........._ _......._--'_ _-'-_--'

o

-40
-60
10 (mA)

-20

-80

o

-100

~

C~
o

-1

1.75
ros
(Norm.)

1.50

/

1.25

0.50

/

-20
-30
VOS (V)

-40

-50

TJ - 125°C

,

L
Is
(A)

25°C
-0.1

. . .V

1.00
0.75

V

I
Coss

Source-Drain Diode Forward Voltage

On-Resistance vs. Junction Temperature
2.25
Vas,: -4.5 V
2.00 :- 10= -0.1 A

-

-10

C lss

V

V
-50

-10

30
70
TJ (OC)

110

-0.01

150

,
o

Threshold Region

-0.5

-1.0
-1.5
VSO (V)

-2.0

-2.5

Safe Operating Area

-10.0

-10 _ _
=Vos - -5 V

-~J = l~O°C
f

-1.0

-

10
(mA)

-

'/

1/" rl

125°C -

10

(mA)

I

/I II

-0.1

-0.01

II
o

-1.0

25°C

/--SSOC
-2.0
Vas (V)

-3.0

-3.5

-1

-100

-10

-1 K

VOS (V)
toperatlon In this area may ba limited by rOS(ON)

7-170

VPDQ20

fCrSiliconix

~ incorporated

TYPICAL. CHARACTERISTICS

Normalized Effective Transient Thermal Impedance. Junctlon-to-Amblent (TO-92)

Duty Cycle

0.5

0.5
0.2
0.2
, R thJA
(Norm.)

0.1

1"'";...-'

0.1

Notes:

HLfL

0'.05
0.0

~t~

0.05

/\.
0.02

1. Duty Factor. D =

0.01

\

0.01

0.5

0.1

!~

2. Per Unit Base = RthJA = 156°C/W
3. TJM - TA = POMZthJA(t)

Sint e 'lulie,

5

1.0

10
50
100
Square Wave Pulse Duration (sec)

500

On-Resistance vs. Gate to Source Voltage

1K

5 K

10 K

Off State Current

20
VGS - 0 V

TJ = 25°C
18

V s--160V~
16
rOS
(.0. )

~

14

10=-0.1A

~~
""'"""" r::2'

12
10

10 =

o

-n t-

loss
-1
(.lJ.A) -10

5

/1

_1'~-2

"

I

I~ = 162' A

8
6

10 V""

-1

F
'_10-3

I

_10-4

-4

-8

-12
VGS(V)

-16

-20

-60

-20

Drive Resistance Effects on Switching
100
VOO -25 V
R L -125.o.
V Gs -Oto-10V
10 = -200 mA

t

td(OFF)
td(OT)
t,
tf

t
(ns)

10

td(ON)

10

20

50
RG (.0.)

=

140

180

..

VOO - -25 V
RG - 25.0.
VGS - 0 to -10 V

tf

-

10

60
100
TJ (OC)

Load Condition Effects on Switching

100

(ns)

20

I",,~

~~ ~

=
c::::

t,

td(ON)

100

1

-10

-50

-100
10 (mA)

-500 -1000

7-171

H

VPDQ20

Siliconix

incorporated

TYPICAL CHARACTERISTICS
Body Drain Leakage Current

Equivalent Input Noise Voltage vs. Frequency
100

IU

111011111~mA

80

_10 7

=
=

Vos -5 V
T J 25°C

-10mA~\

60

10
4
(nA) _10

\

40

a

10

100

"

1K

I,

_10 2 ~ T - 25°C
J

~ :::::t-

-10

10 K

h

-10 V- r.--P

_10 3

1\
20

160 V

100 V

_105

\\

en
(nV/VHz')

Vos-

_10 6

o

2

-1

-2

-3

V GS (V)

f (Hz)

Output Conductance vs. Drain Current
700
80 )J.S, 1% Duty Cycle
Pulse Test
TJ = 25°C

600

gos
LuS)

500

1111

I II

400

IIII

II

'liDS = -7.5 V
300
200
100

o

-

~OS i-}? I~
~

-I-

-1.0

I

-10

III

-100

-1000

10 (mA)

Transient Thermal Response (TO-206AC)
1.0
D - 0.5
0.5

0.2

--

R thJO
(Norm.)

0.05

Notes:

0.05

K,::1

Slngt

HLSL
tt~

0.02 _
~

0.02

A~

~

~ ~ ;;ii~

0.1
0.1

J--

~

0.2

.....

t1
=t;
Per Unit Base = R thJC =83°C/W
TJM - To =POMZthJC(t)

1. Duty Factor, D

1 0 . 01

TSil1

2.
3.

0.01
0.1

0.5

1.0

5

10

50
tl (sec)

7-172

100

500

1K

5 K

10 K

VPDS06

~SilicDnix
incorporated

.LII

P-Channel Enhancement-Mode MOSFET "FETlington"
DESIGNED FOR:
•

Switching (P-Channel Complement
to 2N7000)

FEATURES
•
•

Low rDS(on) < 10 n
Available in Surface Mount

DEVICE

TYPE

PACKAGE

Single

TO-206AC

• VP0610E, TP0610E

TO-92

• VP0610L, TP0610L

SOT-23

• VP0610T, TP0610T

14-Pin
Plastic

• VQ2000J

14-Pin
Dual-Inline

o VQ2000P

Chip

• Available as above
specifications

GEOMETRY DIAGRAM

Gate Pad
0.0041
(0.104)
0.0049
(0.124)

Source Pad
0.0041
(0.104)
0.0049
(0.124)

T
1

•

0.027
(0.686)

7-173

VPDS06

.r'Siliconix

~ incorporated

TYPICAL CHARACTERISTICS

Output Characteristics

: : I/if"V I
-200

v

-100

V'

-300
10

(rnA)

I

o

-3
-10

-20
-30
Vos (V)

I
-300

111m
1. ~ b--'" I-""""
......
~

(mA) -200

~ l,...---'

-100

o

-50

-6 V
......,...
;.,.1-5 V1

~~

/

10

~

-40

I

-400

-J
-J

~

o

J

-500

Ohmic Region Characteristics

iV
I~ i"""

-

14)'3V'-

~

o

-1

Output Characteristics for Low Gate Drive

-2
-3
Ves (V)

-4

-5

-4

-5

Transfer Characteristics

-100
Ves = -15 V
-80

-60
10

10

(rnA)

(rnA)
-40

-20

0
-0.4

-0.8
-1.2
Vos (V)

-1.6

-2.0

-2
-3
Vas (V)

-1

0

On-Resistance

Gate Charge

25

-1

I

I

~
L~

-12.5, t-- l e=-0.5A

20

0

-10.0
15
res
(.0. )

10

---

5

o

7-174

o

V s

10 V

V

-2.5

o
-0.30
-0.45
Ie (A)

-0.60

-0.75

I

V

o

48 V

L

/

-5.0

~

-0.15

Ves = -30;

Vas
(V) -7.5

1-

100

200

300
Q g (pC)

400

500

600

VPDS06

.:rSiliconix

~ incorporated

TYPICAL CHARACTERISTICS
Capacitance

Transconductance
0.150

.--......,..-----r---.,.---,---.,

50

I
VGS = 0 V
f = 1 MHz

40

0.125

30

0.100
gFS

C
(pF)

(S)

0.075

20

0.050 I-B<------if---/---+---+---/

10

l\

,
'\
I~

C rs" ;

o

o ~o---~o....1~--~0.~2---0~.~3---~0....4~--~0.5

o

-10

Coss
I

-20

-30

-40

-50

VOS (V)

On-Resistance vs. Junction Temperature

Source-Drain Diode Forward Voltage

2.25

-1

VGS =1- 10 V
10=-0.5A

2.00

/'

V
-50

-10

150°C

,

/

1.50
ros
(Norm.) 1.25
1.00

I=TJ

/

1.75

0.50

~

:'--

10(A)

0.75

C 1SS

/

V

/

/

/

IS
(A)

1/
-0.1

TJ

30

70

110

-0.01 0

150

-1

-0.5

25°C

-2

-1.5

-2.5

Vso (V)

Threshold Region

Safe Operating Area

-1

-5

/

-0.1

,

I

-1

'L 1/11

T J = 150°C

1110lJ ,lJ.s

F See Note 1

.

100°C
10
(mA)

-

10

50°C

-0.01

(A)

I

I II

OloC

I

-0.1

V '"

55°C

I
-0.001

j
o

/

To 25°C
Single Pulse
R thJO = 83°C/W
Part: VP0610E

I

I II I

-0.3 -0.6 -0.9 -1.2 -1.5 -1.8
V GS (V)

-0.01
-2.1

~

-1
'Operatlon

-10
VOS (V)
In

1~

r...

..

10 ms
100 ms

d~,

IIII
-100

this area may be limited by rOS(ON)

7-175

VPDS06

.-:F'Siliconix
..LII incorporated

TYPICAL CHARACTERISTICS
Normalized Effective Transient Thermal Impedance. Junctlon-to-Amblent (TO-92)

Duty Cycle

0.5

0.2
n

,

0.1

;,.---

_I-'

u. ,

RthJA
(Norm.)

Notes:

0.0

tt~

:L'~

1/'\

\

1. Duty Factor. D =

0.01

100
10
Square Wave Pulse Duration (sec)

0.1

1K

On-Resistance vs. Gate to Source Voltage
20

JI

II

110 =1_25 ImA I

VGS

Vos -

loss
(nA)

1\

T1J = ~5°~
2.5

o

'"F:::

-4

f

-10

: - -0.5 A

\ l\l~

~ t-.

_10-3

-8

-12
VGS (V)

-16

-20

-60

-20

20

60
100
Tc (OC)

140

180

Load Condition Effects on Switching
100

25 V
VOO
45.0.
RL
VGS o to -10 V
10 = -0.5 A

1= t f

50

I....

25 V
Voo
RG-25.o.
VGS - 0 to -10 V

20 I- td(OFF)
t,
td(OFF1=
tf
td(ON) -

10

5

t

(ns)

r--.... I""-

10

r.....

r-o'"

F t,
5 i- td(ON)

2

2

10

20

50
RG (.0.)

7-176

_I

L

_10-2 l"'"

20
(ns)

-10V-

./

Drive Resistance Effects on Switching

t

48 V
I

LL

-1
_10- 1

100
50

OV

_10 2

~-0.2A

5

10 K

Off State Current

15

10

\

_10 3

II

rOs
(.0. )

tl
"12

2. Per Unit Base = R thJA = 156°C/W
3. TJM - TA = POMZthJA(t)

Sin~le jUliel
0.01

uL

P~M I

1Q.'05

100

1

-10

-100
10 (mA)

-1 K

VPDS06

.:rSiliconix

~ incorporated

TYPICAL CHARACTERISTICS
Body Drain Leakage Current

Equivalent Input Noise Voltage vs. Frequency
_10 4
TJ

25°C

-I
Vos

_10 3

-40 V
./

_10 2

~
r...r

-20V~

10

en
(nV/VHZ)

-10 V
./

-1

100

1--H-+++++fI~~k+++++H+--+-+-If++If!l

_10- 1

":0::

o UUll1llUJJJ:ttffE::l::!::E~
10

~

I;r-"'

10 K

1K

100

'l

./

(nA) -10

-0.8

-0.4

-1.2

-2

-l.B

VGS (V)

f (Hz)

Output Conductance VS. Drain Current
700 r-~~~~--~~~~-r~~rm
80 )J.S. 1% Duty Cycle
BOO
Pulse Test

II

500 I-T_J.j-=+25j-°HC+I+II--++++HH+l-v-j)4-+l-H+I+I
400 I--+-+HH+I+I--++++H~--~~H+~
90S

()J.S)

VOS = -10 V

300

1-I-H-H-H+l-IH++ffltlll~l+H+H

200 I--+-+HH+I+I--+~~~--~~~~

~ IT?I~I

10:

-+++++Hb~111rlII++--lli++-I+l-H.Jl

I----t_
-1

-10

-1 K

-100
10 (mA)

Transient Thermal Response (TO-20BAC)
1.0

III

D - 0.5

.....

-

0.2
RthJC
(Norm.)

0.1
0.1

0.05

k:= ti,

.....l;1li'

~
Notes:

~t~

0.02
~l,..o

I=-d

BLrL

1. Duty Factor. D =

1 0 . 01

~~

2. Per Unit Base = R thJC = 83°C/W
3. TJM - Tc = POMZthJC(t)

Singie Ts,11
0.01
0.1

100

10

1K

10 K

t1 (sec)

7-177

.HSiliconix

VPDV10

incorporatec

P-Channel Enhancement-Mode MOSFET
DESIGNED FOR:
C .. ,i ....... hir"'ln

..... ,' '~\J' '" 'bI

•

Amplification

PACKAGE

Single

TO-205AD

• VP08088, VP10088

TO-92

• VP0808L, VP1008L

TO-237

• VP0808M, VP1008M

14-Pin
Plastic

• VQ2004J, VQ2006J

14-Pin
Dual-InLine

• VQ2004P, VQ2006P

Chip

• Available as above
specifications

FEATURES
•

Low rDS(on) < 5

n
Quad

GEOMETRY DIAGRAM

Gate Pad
0.005
(0.127) 0.007
(0.178)

0.058
(1.47)
Source Pad
0.006
(0.152)
0.007
(0.178)

~1

I~

7-178

0.053
(1.35)

I

TYPE

DEVICE

VPDV10

~SilicDnix

~ im::orporated

TYPICAL CHARACTERISTICS
Ohmic Region Characteristics

Output Characteristics

-2.5

t

-1.5

-0.5

o

-9 V

-1.6

-8 V

-1.2
10
(A)

-7 V

V

/'

~ "/

~ /'" i"""
~ ~ -'~

-0.8

-0.4

~
o

-5 V
-10

-20
-30
Vos (V)

-40

o

-50

I
!/

-12

-8

I

-4 V

-0.4

o

Ves = -10 V

j

-0.1
_ I - 3.2 V

-0.8
-1.2
Vos (V)

-1.6

-2.0

AW
o

-2

-4

On-Resistance

-10.0

-V

V GS = -10 V

2

o

o

-0.5

-1.0

-1.5
10(A)

-10

.~V

1
le= -0.5 A

-12.5

8

4

-8

Gate Charge

-15.0

rOS
(.0. )

-6

V GS (V)

10

6

,

2slc

'/

-0.3
10
(A)

o
-0.4

-5

'"-- 125°(

-3.6 V

~3.4IV

-4

'I-

I

-0.2

'/
o

\J-

-2
-3
Vos (V)

'/

-4

-7 V

-5 V

TJ = -55°C

I

-3.8 V

rl

~

Transfer Characteristics

TJ = 25°C

I
I 1,/

10
(rnA)

I

1

V

-0.5

VvG~ = ~4.0 ~

I

GS = -10 V

~V

-1

Output Characteristics for Low Gate Drive

-20

-16

.1.v

1

-6 V

II
o

1
I ......
-9 V ><1"__

II

."

~

-1.0

I

- T J =25°C

I~

-2.0

10
(A)

-10 V

VG = -12 V

/

-2.0

-50

II

VGS
(V) -7.5

1. ~-80V
I

-5.0

/

-2.5

-2.0

-2.5

-3.0

v-;t;; //

II
o
o

100

200

300

400

500

Og (pC)

7-179

~Siliconix

VPDV10

~ incorporatec

TYPICAL CHARACTERISTICS
Capacitance

Transccnductance

: : r---+--±----t
300

C
(pF)

125°C
200

I I I

I

--+--::;,.j£---J--c::::;;oo-F--I

1-.

gFS
(mS)

1---.o"II-~:....t-__:::ooI-~=--+--_f

100 ~~~~-+--+---r----;

-100

-200

-300

-400

o ~0----~~----2~0~----3~0~----4~0~--~-50

-500

10 (mA)

Vos (V)

Source-Drain Diode Forward Voltage

On-Resistance vs. Junction Temperature
2.00
1.75

r-

-1

VGS ~ -10 V
10=-0.5A

V
./

1.50

1.00

0.50

I

/
-50

Is
(A)

III

-0.1

T J - 25°C

I

I

-10

30
70
TJ (OC)

110

II

-0.01 0

lS0

-O.S

-1.0

-l.S

-2.0

-2.5

Vso (V)

Threshold Region

Safe Operating Area
-10

-10
VOS

SV

-1

10

I

I I

V

/

150°C

I I

/

rOS
1.25
(Norm.)

0.75

TJ

/

I

I=TJ

150 0

(mA)
125°C -

I
-0.01
-1.0

II

I

I

/
See Note 1 ' /

-1

q
II I

-0.1

I

/1/

r.t I-.=-- 25°C

,

V

-0.1
-55°C:
I

-l.S -2.0 -2.S -3.0 -3.S -4.0
VGS (V)

-0.02
-4.S

l°rl
1 ms

10
(A)

I

10J,LS

'"

~C=
25°C
~
F
Single Pulse
1= RthJC = 20°C/W =
r-1

PtT

101m~

I I
=!::J:

100 ms
dc

1171~f8B I
-10

-100

-1 K

Vos (V)
1Operation in this area may be limited by rDS(ON)

7-180

VPDV10

.r'Siliconix

.LII

incorporatE!d

TYPICAL CHARACTERISTICS
Normalized Effective Transient Thermal Impedance, Junctlon-to-Amblent (TO-92)

Duty Cycle

0.5

0.2

--- -

0.1
RthJA
(Norm.)

~05
0.1

~

::;;..-

-

HLJL

Notes:

tt~

A''''-

/\.

1. Duty Factor, D =

0.01

\

sint jUlie,
0.01

0.1

50
100
10
Square Wave Pulse Duration (sec)

500

5

0.5

On-Resistance vs. Gate to Source Voltage

7

:: VGS

\ 110 =

rOS
(.0. )

\

4

0.5 A

3

b.1 }..

Vos

~ \

loss
(nA)

1.0 A

~ :::::..: :::::--...

-

-1
_10- 1

-4

-8

-12
VGS (V)

tr

~
10

Vos

10 V

-16

-20

-60

-20

20

60
100
TJ (OC)

140

180

Load Condition Effects on Switching
100

50

t

./ /

_10-3

o

Drive Resistance Effects on Switching

(ns)

80 V

-10

i\

100

20

10 K

OV

_10 2

2

o

5 K

Off State Current

,

5

1K

_10 3

TJ = 25°C

6

~~

2. Per Unit Base = R thJA = 156 °C/W
3. TJM - TA = POMZthJA(t)

-:-

-

.....

50

-

.... i-'"

~

I td(Of F)
td(ON)

.... 1-"

20

t

(ns)

5

10

--..

tr
.... f-1""i

-

tf
td(Om
'd(ON)

5
Voo = -25 V
R L =50.o.
VGS = 0 to -10 V
10 = -500 MA

2

10

20

-

2 -

50
R G (.0.)

100

1

-0.1

Voo = -25 V
RG= 25.0.
VGS = 0 to -10 V (Pulse)
-0.2

-0.5

-1.0

10 (A)

7-181

..

VPDV10

a:rSiliconix

~ inccrpcrated

TYPICAL CHARACTERISTICS
Body Drain Leakage Current

Equivalent Input Noise Voltage vs. Frequency
250

200

\

150

Vos = -5 V
TJ = 25°C

\
10 = -1 mA

\.

f\

en
(nV/VHz)

10

100

"

-10~~~

50

o

(nA) _10 4

1\.

t-......

I 11111

_10 1

100

10

3
_10
_10 2

1K

ilililil
o

10 K

-0.6

-1.2

-1.8

-2.4

-3.0

V GS (V)

f (Hz)

Output Conductance vs. Drain Current
700
80,lJ.s. 1% Duty Cycle
Pulse Test
TJ = 25°C

600
500
gos
()..lS)

400
-7.5 V
300
200

I~

Vos = -20 V
100

o -1

~
-10

-100

-1 K

ID(mA)

Transient Thermal Response (TO-20SAD)
1.0
D - 0.5

0.2
0.1

R thJC
0.1
(Norm.)

I"'O":'Ofi

_

%

::~

"

:::;;.--

~

Notes:

~.0.02
,0.01

jjUL
tt~

Single Pulse

1. Duty Factor, D =

=

!~

2. Per Unit Base R thJO = 20°C/W
3. TJM - To POMZthJO(t)

=

0.01
0.1

7-182

0.5

5

10

50
tl (sec)

100

500

1K

5 K

10 K

g

VPDV24

Siliconix

incorporated

P-Channel Enhancement-Mode MOSFET
DESIGNED FOR:
•
•

Switching
Amplification

PACKAGE

Single

TO-205AD

• VP2410B

TO-92

VP2410L
• BS208

FEATURES
•
•

DEVICE

TYPE

High Breakdown > 240 V
LowrOS(on)<10n

Chip

Available as above
• specifications

GEOMETRY DIAGRAM

Gate Pad
0.005
(0.127)
0.007
(0.178)

•••••
•••••
•••• •

.....
........
....................
....
...............
....................
••••••••••••••••••••
....................
....................
....
................
....................
....................
....................
..............
...... .......
......
.......
~1.~~~0.~05~3~~~.I
• • • • • 11 . . . . . . . . . . . . . .

Source Pad
0.006
(0.152)
0.007
(0.178)

"'111 ••••••••••••••

"1' •

• • 111

.11

(1.35)

l1li •

••••

..

0.058
(1.47)

1
7-183

VPDV24

~Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Ohmic Region Characteristics

Output Characteristics
-1.0

~VIGS=-10V

-S V

7V

-0.8

,

-0.6
10
(A)

-500

-0.2

V

/

-300
-5 V

/ /

10
(mA) -200

-4 V

h

-100

~"

-10
-15
Vos (V)

-20

o

-25

~ V,
~

10
(mA)
-40

-20

V

/ V
r/ V

II V

~V
~~

~

3V

o

-1

I,.....;' ~

-

I

~3.2Iv

i

~

-300

-200

~3.0IV

100-

-2.8 V

-100

2.6 V

I
-0.4

-0.8
-1.2
Vos (V)

0

-1.6

-2.0

0

-1

-2
-3
VGS (V)

-4

-5

400

500

Gate Charge
-12
10=-100mA

VGS = -4.5 V
TJ = 25°C

-10

14

12
rOS
(.0. )

10

7-184

-5

10
(mA)

On-Resistance

6

-4

-2
-3
Vos (V)

Vos=-15V

16

8

-4 V

3.4~

....

o

.......!-":'

-400

1-'1

1M::

o

.,.

Transfer Characteristics

1/"

V

/

~

-4.~ V

~

L- I -

-3.S V

VG = -4 V

-60

6:

-500

I

TJ = 25°C

L

-

LrL L

-3 V

-5

-80

-5 V

L

Output Characteristics for Low Gate Drive
-100

V
./ ;r

11/
o
o

Ves= -10

-400

~ .,.

-0.4

TJ = 25°C

./

~

;I'"

o

-

/

....-'"

-8

V

VGS
(V)

-6

-4
-2
0

-100

-200
-300
10(mA)

-400

-500

0

100

200
300
Q g (pC)

r-

VPDV24

~Siliconix
.z.
incorporated
TYPICAL CHARACTERISTICS

Capacitance

Transconductance
250 r---....,...--"T"""-~--:::::OI\'""----,

150
VGS = 0 V
f = 1 MHz

125

200

\

100

~" ...............~
\\

150
C
(pF)

gFs
(mS)

75

100
50

VOS = -10 V

1-1>"""-+---+--- ~~11:s Test

50

\

25

1% Duty Cycle
0
-100
-150
10 (mA)

-50

-200

-250

""'--

-10

0

,

10= -0.2 A

1.75

//

1.50

/

1.00

Is
(mA)

-0.1

I

0.50
-50

-10

30
70
TJ (OC)

110

-0.01

150

o

-0.25

150°C

=

25

-0,5
-0.75
Vso (V)

"

-1.0

,

I
I

-0.01

-1.2

..

..

100p.S

1 ms

(A)

I 25

f [,
I

-0.1

55°C

-1.6 -2.0 -2.4
VGS (V)

'.

V
To - 25°C
Single Pulse
R thJO = 20°C/W
Part: VP2410B

II I I
o

-1.25

1b~1

se~ JoU 111

-1

10

I
-0.1

7-

Safe Operating Area

h II

~ F 125

10
(mA)

J

-5

5V

VOS

Ji

I

Threshold Region
-10

~TJ

I

~

V

f--'

-50

II

- TJ = 125°7'

-4.5 V
~ VvGS=
10= -0.1 A

1.25

-40

-1

L-"'0

2.00

-1

C rss

-20
-30
VOS (V)

Source-Drain Diode Forward Voltage

On-Resistance vs. Junction Temperature
2.25

0.75

Coss

0
0

ros
(Norm.)

~

-2.6 -3.2

-3.6

dc\-ttlt

I I "I

till

-0.01
-1

-10

1~ ~~
100 ms

-100

-1000

Vos (V)
10peratlon

In

this area may be limited by rOS(ON)

7-185

VPDV24

W'rSiliconix

~ incorporated

TYPICAL CHARACTERISTICS
Normalized Effective Transient Thermal Impedance, Junctlon-to-Ambient (TO-92)

O.S

Duty Cycle

0.2
0.1
RthJA
(Norm.)

0.1

.-

-,-,-,
IL
~U

Notes:

I(i.OS
0.0

-tt~

r/\

\

2. Per Unit Base = R thJA = lS6°C/W
3. TJM - TA = PDMZthJA(t)

Slnrle jUliel
0.01

O.S

0.1

sao

S
10
SO
100
Square Wave Pulse Duration (sec)

On-Resistance vs. Gate to Source Voltage

~

VGS - 0 V

TJ = 2SoC
_10 1

10

-1

l\

8

lo=-O.]A-

I~ ~

6

10 =

-O.O~

_I

A

Vos=

_10-3 I

10 V

//

_10-4

o

-4

-8

-12

-16

-20

-60

-20

20

VGS (V)

Drive Resistance Effects on Switching

60
100
T J (OC)

140

180

Load Condition Effects on Switching
100

100

I

td(OFF)

td(OFF)

t

10

td(ON)

1=

(ns)

--

10

td(ON)

~

J_

I I
Voo = -25 V
RG=2S.o.
VGS = 0 to -10 V

so
R G (.0.)

=

-

Voo = -2S V
R L = 2S0.o.
VGS = 0 to -10 V
I D =-O.l A
20

tf

lJ
V. .

..... tr

10

~

_L!

!--tf

7-186

JfL

LLi

_10-2

2

-192 V

Vos

loss
_10- 1 I
(J.lA)

t

4

t
(ns)

10 K

Off State Current

12

o

SK

1 K

_10 2

14

ros
(.0. )

~~

1. Duty Factor, D =

0.01

100

1

-10

-100
10 (mA)

-1000

VPDV24

.:rSiliconix

.L;II incorporated
TYPICAL CHARACTERISTICS

Body Drain Leakage Current

Equivalent Input Noise Voltage vs. Frequency
200 . -..............,...,.,.,.,........,I"""T.,...,..,.,.,.,....-.............,.,.,I'!'I'I
VOS = -s V
T J = 2SoC
160

10 5

~ T J - 2SoC
f1

10 4

~=-1 mA

I

10 3

en
(nV/VHZ)
80

-192 V

Vos

120

r\

1\

10
(nA)

1\

I""

I

10 2

I

I

10

VOS - -10 V

40 ~~~~~~~4+~~~+4~~

10=-10mA~1:::::

o

LU
IllJjllllllL
1111 --DJ!iWC:EEEJ:OOI
10

100

10-'

10 K

1K

O.S

o

-o.S

-1.0

-1.S

-2.0

VGS (V)

f (Hz)

Output Conductance vs. Drain Current
700
80 J.LS, 1% Duty Cycle
Pulse Test
Vos = -7.5 V

600
500

gos
(J.lS)

400

/

300

if

200

-

100

o

-1

.... '"

-10

-100

-1000

10 (mA)

..

Transient Thermal Response (TO-205AD)

D - 0.5

-

10--'" ...-!;II

0.2

R thJO
(Norm.)

0.1

P

C'S

~~

...

I -~~

~0.05

Notes:

tt~

0.02
0.01

J I

1. Duty Factor, D =

Single Pulse

0.1

0.5

!~

2. Per Unit Base = R thJC = 20 ° C/W
3. TJM - To = POMZthJO(t)

I

0.01

~

5

10

50
t, (sec)

100

500

1K

5K

10 K

7-187

~Siliconix

VPMH03

~ incorporated

P-Channel Enhancement-Mode MOSFET
DESIGNED FOR:
e
•

SV/itching
Amplification

High Speed
Low rOS(on) < 2.5

n

Single

TO-205AD

• VP0300B

TO-92

• VP0300L

TO-237

• VP0300M

14-Pin
Plastic

• VQ2001J

14-Pin
Dual-InLine

• VQ2001P

Quad

Chip

GEOMETRY DIAGRAM

0.008
(0.203)
0.0085
(0.216)
Gate Pad

7-188

DEVICE

PACKAGE

FEATURES
•
•

I

TYPE

• Available as above
specifications

VPMH03

tcrSiliconix

~ incorporated

TYPICAL CHARACTERISTICS

Output Characteristics

-2.0

/v

GS

= -12 V

TJ = 25°C

J

-1.6

-0.8

'IJ

(AI

-0.4

-0.2

-6 V
-5 V
-4

-8
-12
Vos (V)

-16

Output Characteristics for Low Gate Drive

-50

VGS - -6.0 V

r+

-40

II-

-30

T~ = ~socl-

V

I---j.---I----H~-I---I

(A)

-0.4 I - - - j . - - - I - - - I , - - - I - - - I

-0.2

I---j.---I----.j~+---I---I

-4.0 V
-3.5 V

0
-0.4

-0.8
-1.2
VOS (V)

-1.6

0L..-_-J.._~c;..._.....I

-1

-2.0

-5

-3

_ _...I.._--I

-7

On-Resistance

Gate Charge

-12

lst§

10= 1.0 A

~ ~V
//

3.0
-8
2.5

/

V GS

ros
(n. )

(V)
2.0

-4

V
/

1.5

-0.4

-0.8

-1.2

10 (A)

-11

-9

Vas (V)

3.5

o

-5

ID

~

IL
0

-4

-2
-3
VOS (V)

-0.8 I---j.---I----t--I.fl-I---I

-4.5 V

~

I
-1

Transfer Characteristics

-0.6

-20

slv

-1.0 r----,r-----,----.....,.......- - . . ,

-5.0 V

'l

10
(mA)

-10

i- -5.5 V

_6 1v

,;I-"'"

o

-20

)V

AV

o t--

0

I

"..

~ ",

-7 V

-0.4

I

-8 V

h 1/
/1/.

10

-8 V

vi

T J = 25°C

/ V /'

-0.6

-9 V-

-1 OJ.. ...... -9

/

II /

-10 V

Y

0

VGS = -12 V

-0.8

/~ ...~

-1.2
10
(A)

Ohmic Region Characteristics

-1.0

-1.6

-2.0

o

V

o

SOO

/
1000

lS00

2000

2S00

Q g (pC)

7-189

..

VPMH03

.:r"Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Transconductance

Capacitance

r--"""I"--.,.----r---r----,

500

180

V os =-7.5V
,
80 Jl.s, 1 % Duty Cycle
'
Pulse Test

400

150
120

1\

V GS = 0 V
f = 1 MHz

I\--~

\

300 ~----~----~----~~~+---~
gls
(mS)

C
(pF)

90

~ ......

60
100 I-fi~=--_f---+--+---I

-100

-200
-300
10 (mA)

-400

30

o

-500

C lss

r-..
o

Coss

---

-10

On-Resistance vs. Junction Temperature

-

erss

-20
-30
VOS (V)

-40

-50

Source-Drain Diode Forward Voltage

2.25

-1
VGS= -11.4 V

2.00
1.75
ros
(Norm.)

1.25
1.00
0.75

/

lo=-~

1.50

/'

,.,.,..V'

~0.2A

Is
(A)

125°C
30
70
T J (OC)

110

I

I

II

l

/ /

-0.1

-0.01

-10

I

I

,

0.50
-50

"

150

25°C/

/TJ = -55°C

-0.4
-0.6
Vso (V)

-0.2

Threshold Region

I

I
-0.8

-1.0

Safe Operating Area
-10
10JJ,S

:==TJ - 150°C - /

1

See Note 1

/ / 1/

1/ If/J

I

F='100°C

10
(Jl.A)

50°C

I

rh r- 25°C

I

-1.5 -2.0

rI

-3.0
V GS (V)

SSOC
I
-4.0

dC ,-0.1

E

r=:
:=:

Single Pulse
Tc= 25°C
R thJA = 20°C/W
Part: VP0300B
I

I

I IIIIII

II III

-0.01
-5.0

b

100 ms

10

I

I I I

10 ms

(A)

LI LL

I /I

-10

........

~

-1.0

m

1 ms

-1

-10
Vos (V)

-100

10peratlon In this area may be limited by rOS(ON)

7-190

VPMH03

tcrSiliconix

~ incorporated

TYPICAL CHARACTERISTICS

Normalized Effective Transient Thermal Impedance, Junctlon-to-Amblent (TO-92)

Duty Cycle - 0.5
0.5
0.2
0.2
RthJA
(Norm.)

0.1

....

0.1
0.05

~

~

Notes:

0.0
0.05

tt~

..r.A

/'\ I

\

0.02

.
1. Duty Factor, D

0.01

0.5

0.1

tl
=t2
Per Unit Base = RthJA = 156°C/W
TJM - TA =POMZthJAlt)

2.
3.

Sinrle iUljel
0.01

5

1.0

10
50
100
Square Wave Pulse Duration (sec)

500

On-Resistance vs. Gate to Source Voltage

~ VGS

1

3.0

f-

,

1.5

I
loss
(nA)

V os - -10 V=

-10
-1

!'I:o!.

TJ = 25°C

o

-10

II

-1Irl

-

I

_1Ir2

-20

-60

-20

20

VGS (V)

Drive Resistance Effects on Switching
100
25 V
Voo
RL 25.{1
VGS - 0 to 10 V
10 = -1 A

(ns)

~
r-: tdlON)
I-tl-

10

140

180

..

100

-

Voo - -25 V
RG 25.{1
Vas-Oto 10 V

- tl

K""

t d,o
t

(ns)

10

1
100

....

=tr
-

r- tdIOFF)

30 40 50
RG (.{1)

60
100
T J (OC)

Load Condition Effects on Switching

~

20

24 V
//

_10 2

-0.5 A

~\
"' ~ ~......;:

2.0

y"

Vos

-1.0 A

2.5

10

10K

OV

_10 3

10 = -0.2 A
C I I

3.5

t

5 K

Off-State Current

4.0

1.0

1K

_10 4

4.5

ros
(.{1)

~

-0.1

.......

tdlON)

-1

-10

10(A)

7-191

VPMH03

.rSi6conix

~ incorporated

TYPICAL CHARACTERISTICS
Body Drain Leakage Current

Equivalent Input Noise Voltage vs. Frequency
1000

800

en

t

ll)l l~

\

=

1\

Vos = 5 V
TJ = 25°C

600

400
-1
200

o

10
. (nA) -10

\ 1\

(nV/VRZ)

WI

====1

/1

~t"-

100

1K

o

10 K

Output Conductance vs. Drain Current
2800

80IJl~, I/~I~~ty byb'~
=
=

2400

Pulse Test
TJ
25°C
Vos -7.5 V

2000

gas
(JJ,S)

-1

-2

Vas (V)

f (Hz)

11II

1600
1200

II

800
400

o

~~
-1

-10

-100
10 (mA)

7-192

-10 V

•

-1

o~~

I IIIII
10

I

-1000

-3

-4

VRMA

crSiliconix
.z.
incorporated

N·Channel Enhancement·Mode MOSFET Protection Diode
DESIGNED FOR:
•
•
•

Limiting Current
Voltage Protection
Voltage Decoupling

TYPE

PACKAGE

Single

TO-92

FEATURES
•
•
•
•

Chip

Series Element
Two Terminals
High Breakdown> 240 V (JR240V)
Low Cost, Simple to Use

DEVICE

• JR135V, JR170V
JR200V, JR220V,
JR240V
• Available as above
specifications

GEOMETRY DIAGRAM

VRMA

T
or(_o._o_r_1)~ ' '
"I

L -_________
A____

1_____
r"

0.023
(0.584)

..

M

)

------II
•

Cathode Is backside contact

7-193

VRMA

.rY"'Siliconix

~ incorporated

TYPICAL CHARACTERISTICS
Dynamic Impedance VS. Forward
,
Voltage a~ Temperature

Output Characteristics

5

1500

1200

900

600

L

~

--...... ~~

~

~

--

I--

",

300

o

,"" . /

./

4

L

50

./

2

..,.V

Current

800

VB,

200

\

o

250

I\,

-

-

-

o

Forward Voltage

.........

~ 25°C \

1"'- ............
-125°;-~ ~
I
I
~ I".......,;

50

-=

200

250

Dissipation Derating Curve

500

~A = ~5od

I-

..... \. T~ = ~55O~

3

I

",

o

-

..,..,.

640

400

480

300

JR240V

I

IF

4, JR220V
II - JR200V

Po
(mW)

(JJ.A)

320

II

200
gos(S) = A IF IAV F

160

JR170V
JR135V

.'"

1#

y~

" ",

100

ZF(.o.) = AVF/AIF

I I I I I

0
0

25

IF VS. Temperature

1000

r-J

200

1 .1

-...- - - -- ...... I-

I--

~

I-"::

I-- -::::: f:=-

;......

o
25

45

1

65

85

105

125

400

1--1--1--1--1--1--1--1--1--1

300

1--1--1--1--1--1--1--1--1--1

POV
(V)

200 I--I---i--t-+-II-+-t--I---I

100 1--+--I--t--!--II---I--+--I----1
0'"-.......- - 1 _..........1._-'---'-_.1.-...1---1
-55 -35 -15 5 25 45 65 85 105 125
TA(OC)

7-194

150

1-1 f' = 1 mA -+-II-+-t--I---I

I-

,......

125

Peak Operating Voltage VS. Temperature

F =120J

600

~

50

500 r-"'"T"-r-"'"T"-r-"'"T"-r-"'"T"-r-...,

800

400

~

o

10

General Information
Cross Reference
Selector Guide
JFETs

DMOS
Low Power MOS
Performance Curves
Package Outlines _
Applications
Worldwide Sales Offices and Distributors ;;';',:.

~Silico~:~

~ inccrpcr

PACKAGE OUTLINES

:~;g E(i;~~O)l
-I (::~
[ -fHlt-II
(.76)

~

-===---~
2 LEADS

.021T
016

~
(.41)

.046 """" /
" /
I'/
,

036
li.!.!.L
(.91)

"

45°
BOTTOM VIEW

TO-18
(2-PIN)

iii
BOTTOM VIEW

TO-206AA
(TO-18)

IN INCHES
ALL DIMENSIONSS IN MILLIMETERS)
(ALL DIMENSION

8-1

PAC KAGE OUTLINES

r

150t~l

:115

~
(2.93)

-l

(12.70)

~

(.76)

I
~.

~======:J~

11-======----::-021
:016T
3 LEADS

...f.:EL
(.41)

BOTTOM VIEW
TO-206AC
(TO-52)

r: l

.130
...!§Q.
~
(3.30)

-l

500

(i2.70)

030
(.76)

r=_===== -.l
:016
6 LEADS

021T

~
(.41)

BOTTOM VIEW

TO-71
NINCHES
ALL
IN MILLIMETERS)
DIMENS/O
(ALL DIMENSION~i

8-2

.-rSilicD':.'J~

~ inccrpcr

PACKAGE OUTLINES

:~ig

[

~
(4.32)

:t

-I

(i~~~o)

030

(.'t6)

-,----;

l

~
lh::=======T
4 LEADS

.021
.016
~
(.41)

BOTTOM VIEW

TO-206AF
(TO-72)

[
-----

III

370
'335

~
1

.335
.305

(8: 51) .J§..:§QL
(7',5)

:m J:(i~~~O)l

.1i:!2J...
(4.19)

-1

040

71:D2r

.1

l __~" I Ib~~~~~~ T

~

.021

.

7 LEADS

.016

~

iii

(.41)

BOTTOM VIEW

MO-002AG
(TO-7S)

ALL DIMENSIONS
(ALL DIMENSION

i

NINCHES
IN MILLIMETERS)

8-3

IC:rSiliconix
..z::.
incorporated
PACKAGE OUTLINES

I
I
iJ~1 ~~ ~I;;;~=======;;;('~~;:;=J)::::~
' 1 7 5 , .600
.550
.185
(15.24)
(13.97)
(4.70)

~

l}

3 LEADS

....Q2§..

(2~:~)
(2.16)

-1

.145
.135
iM§l.
(3.43)

BOTTOM VIEW
TO-226AA
(TO-92)

1·

.185
175

JllQL

1I

II·

.080
(2.03)

500
,(i2.70)

I

021

:016
~
(.41)

(4.45)

.047
.052

C=~~~~~~==~

T,I I

~-

L~
(.53)

3LEADS

:#8=
~
(1. 14)

(1.206)

(1.334)

~

--$-)~
.145
.135

iM§l.
(3.43)

TO-226AA
(TO-92 LEAD FORM)
-18

8-4

BOTTOM VIEW

.105
.095

.11.:i!.1.
(2.16)

.-r'Siliconix

~ incorporated

PACKAGE OUTLINES

~~ ~
r~-1
(3.05)

I

.021

.016

f:~~1

3 LEADS

('~I ~===========::::J: 4= fl1J!:
~

.450
.400
~

~

(5.08)

·1

(10.16)

TO-226AA
TO-92 DEVICE to TO-5 PIN CIRCLE

[ J: l
:~~~

~

-J

I T(
.335
.305

(9.39)

(8.50)

(8.51)

(7.75)

1 ~l

.1i:.QEL
(3.56)

.040

-I

.370
.335

.160
.120

(12.70)
.500

(4.19)

(1.02)

-

.M.Q..-1~
.010

.1.1.:!!.1.L

1.

lT

.02
B LEADS .016
~
(.41)

(.25)

BOTTOM VIEW

MO-002AK
(TO-99)
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)

8-5

wrSiliconix

~ incorporatec

PACKAGE OUTLINES

f

3

t
.055
.047

~~
(1.20)

2

.098
.083

.R§QL
(2.10)

I

!

~+

.004
.001
~
(.02)

.005
.003

--I.:.m.
(.085)

SOT-23

:071
079

..f..?.:QQL
(1.80)

120
:105

ffl

f
!

.055
.047
~
(1.20)

.018
.015

~

(.37)
.

fl.:.QEL
(2.67)

~~'----~
-I I=='f.005
.003

...LE.L

(.085)

SOT-143

ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)

8-6

.010
.005

..1d§.L
(.13)

.rSiliconix

~ incorporated

PACKAGE OUTLINES

8

7

6

5

f .160
.140

.
2

.050
(1.27)

-J

3

(4.0S)

~S}

4

r- -I r--

~

.018

.014

-

..L.ill
(.3S)

-----'-t
1
.069 11..1.§.1.
.. 053 (1.3S)

~

t

.248 (6.30)

.224 (S.70)

~(

.008 ..L.2Ql.
.004

~

.031 .LMJ...

(.10)

.L

I :::::
.024

(.60)

--I

I-~

.009

.007

7'~~j
•

a-LEAD SOIC

~
14

13

.352~~
-:329
(B.3S)

12

11

10

9

T

8

.160
.140
(4. OS}

(3.SS)

2

.050
(1.27)

3

4

I

I

-1

5

r-

6

II

-1

~

7

r-

.018...1.:.i§L

.014

.069
~053

f

.008
.004

r

(.35)

..1dQL
(.10)

.1.J2fl.
(1.3S)

f

-.L Jj

T
.009 ~
.007

.248~
(S.70)

T24

l

('-_--I) ~
.031
.024

~ -I
(.60)

I--

(.19)

14-LEAD (NARROW) SOIC

ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)

8-7

fCrSiliconix

..,1;;11 incorpora.ted
PACKAGE OUTLINES

f
.325 ...@:.g§l
.300 (7.62)

.280
.220

* I
I""0----

.840
.745
(21.33)
(18.93)

f.1l..:.11L
(5.59)

*

-----t

P
'310

I

(l~~) --I

'- /
i

(7.37)

\\._

-"\\

(.20)

15° MAX

16-LEAD DUAL IN LINE PACKAGE
(PLASTIC)

t

5

4

3

t

2

.325~

.310 .Jl..:.§!J..
.280 (7.11)

.290 (7.37)

+

9

10

11

12

13

~
.770
(21.08)

0

1

14

+

15

-----t-I

(19.56)
.055
.025

(.64)1

.1..!...:.£!1..

WW:
.021 ...1..:..§§L
.015 (.38)

-11'-

.060~

.038

~~ -I

I-

--:-::::T:
.175~

"",".67)

f~~
.125+ (3.18)
.100

(2.54)

8-8

.QQL

.300

(7.62)

16-LEAD DUAL IN LINE PACKAGE
(SIDE BRAZE)
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)

Pi
.,QRt
.008

(.20)

(.97)

.012

i~30~

~

H

Siliconix

incorporated

PACKAGE OUTLINES

P
ExtractIon force

STYLES
A,B,C,D,P
(see below)

12.7 ± 1.0

F

5 +0.8
-0.2

Min. 300 gl.

Po

12.7 ± 0.2

Fl - F2

-II--' h

P1

3.85 ± 0.5

Do

P2

6.35 ± 0.5

± 0.3
4 ± 0.2
1.4

o ±. 1

6.35

'h

18 +0.5
-0.5

d

Wo

6 ±. 3

R

W1

9 ± 0.5

W2

MAX. 0.5

L

MIN. 11

Wa

MIN. 4.5

' c

o ± 0.5

Pa
W

H

OPTION 1

18.5

0.50 ~ g:~

dla.

0.8
45°- 60·

:!: g:?s

OPTION 3

STYLE IS A PREFER ED STYLE

STYLE A IS PREFERED

~

ROUNDEDSIDE
ROUND OUT
DRAIN OFF FIRST

FEED~
STANDARD TAPE & REEL FLAT OUT GATE OFF FIRST

o

0

0

0

0

CARRIER STRIP

ROUNDED SIDE TRANSISTER AND ADHESIVE TAPE NOT VISIBLE

OPTION 2

OPTION 4

CARRIER STRIP
FLAT SIDE
FLAT OUT
DRAIN OFF FIRST

~
0000

FEED~

FLAT SIDE OF TRANSISTER AND ADHESIVE TAPE VISIBLE

CARRIER

STRIP

ROUNDED SIDE
ROUND OUT
GATE OFF FIRST

ROUNDED SIDE TRANSISTER AND ADHESIVE TAPE NOT VISIBLE

TO-92 TAPING SPECIFICATIONS
AND WINDING STYLES

(ALL DIMENSIONS IN MILLIMETERS)

8-9

~Siliconix
incorporated

..z::II
PACKAGE OUTLINES

UNIT: mm

START

I

'----7"'--1-----,,0
No Components
SEALED
MIN 40 mm

SOT-23
Option 1 (Tl)

~~

0

JI

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Option 2 (T2)

A
SOT-23/S0T-143
SOIC-8
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8.0

± 0.3 MIN

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B

C

178 MIN

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330
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± 0.3
330
± 0.3
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__________________
~

SOT-23/143/S01C TAPE AND REEL

8-10

0

~

General Information
Cross Reference
Selector Guide

JFETs
DMOS
Low Power MOS
Performance Curves
Package Outlines
Applications
Worldwide Sales Offices and Distributors

> '"

-

~SilicDnix

LPD·1

~ incorporated

AN INTRODUCTION TO FETS
INTRODUCTION
Current Limiters

The basic principle of the field-effect transistor (FET)
has been known since J. E. Lilenfeld's patent of
1925. The theoretical description of a FET made by
Schockley in 1952 paved the way for development of
a classic electronic device which provides the designer the means to accomplish nearly every circuit
function. At one time, the field-effect transistor was
known as a "unipolar" transistor. The term refers to
the fact that current is transported by carriers of one
polarity (majority), whereas in the conventional bipolar transistor carriers of both polarities (majority and
minority) are involved.
This Application Note provides an insight into the nature of the FET, and touches briefly on its basic characteristics, terminology, parameters, and typical applications.
The following list of FET applications indicates the
versatility of the FET family:
Amplifiers
Small Signal
Low Distortion
High Gain
Low Noise
Selective
D.C.
High-Frequency

Voltage-Controlled Resistors
Mixers
Oscillators
This very wide range of FET applications by no means
implies that the device will replace the more widelyknown bipolar transistor in every case. The simple
fact is that FET characteristics - which are very different from those of bipolar devices - can often
make possible the design of technically superior (and
sometimes cheaper) circuits.
The family tree of FET devices (Figure 1) may be divided into two main branches, Junction FETs (JFETs)
and Insulated Gate FETs (or MOSFETs, metal-oxidesilicon field-effect transistors). Junction FETs are inherently depletion-mode devices, and are available in
both n- and p-channel configurations. MOSFETs are
available in both enhancement and depletion modes,
and also exist as both n- and p-channel devices. The
two main FET groups depend on different phenomena for their operation, and will be discussed separately.

Switches
Chopper-type
Analog Gate
Commutator
Protection Diodes
Low-Leakage

FETS

iii
Figure 1.

FET Family Tree

9-1

crSiliconix

LPD·1
Junction FETs
In its most elementary form, this transistor consists
of a piece of high-resistivity semiconductor material
(usually silicon) which constitutes a channel for the
majority carrier flow. The magnitude of this current is
controlled by a voltage applied to a gate, which is a
reverse-biased pn junction formed along the channel. Implicit in this description is the fundamental difference betwee JFET and bipolar devices: when the
JFET junction is reverse-biased the gate current is
practically zero, whereas the base current of the bipolar transistor is always some value greater than
zero. The JFET' is a high-input resistance device,
while the input resistance of the bipolar transistor is
comparatively low. If the channel is doped with a donor impurity, n-type material is formed and the channel current will consist of electrons. If the channel is
doped with an acceptor impurity, p-type material will
be formed and the channel current will consist of
holes. N-channel devices have greater conductivity
than p-channel types, since electrons have higher
mobility than do holes; thus n-channel JFETs tend to
be more efficient conductors than their p-channel
counterparts.
Junction FETs are particularly suited to manufacture
by modern planar epitaxial processes. Figure 2
shows this process in an idealized manner. First, ntype silicon is deposited epitaxially (single-crystal
condensation surface) onto monocrystalline p-type
silicon, so that crystal integrity is maintained. Then, a
layer of silicon dioxide is grown on the surface of the
n-type layer, and the surface is etched so that an
acceptor-type impurity can be diffused through into
the silicon. The resulting cross-section is shown in
Figure 2C, and demonstrates how a p-type annulus
has been formed in the layer on n-type silicon. Figure
2D shows how a further sequence of oxide growth,
etching, and diffusion can produce a channel of ntype material within the substrate.
In addition to the channel material, a JFET contains
two ohmic (non-rectifying) contacts: the source and
the drain. These are shown in Figure 2E. Since a
symmetrical geometry is shown in the idealized JFET
chip, it is immaterial which contact is called the
source and which is called the drain; the JFET will
conduct current equally well in either direction and
the source and drain leads are usually interchangeable.
(For certain JFET applications, such as amplifiers, an
asymmetrical geometry is preferred for lower capaci-

9-2

~ incorporated

tance and improved frequency response. In these
cases, the source and drain leads should not be interchanged) .

(A) P-type silicon substrate

(B) N-type silicon layer
deposited epltaxlally

(C) Impurity diffused In to
start Isolation region

(D) More Impurity diffused
In to complete Isolation and form N-type
channel

(E) Final form taken by
FET: with N-type
channel embedded In
P-type substrate

Figure 2.

Idealized Manufacture of an N-Channel
Junction FET

Figure 2E also shows how the n-channel is embedded in the p-type silicon substrate, so that the gate
above the channel becomes part of this substrate.
Figure 3 shows how the JFET functions. If the gate is
connected to the source, then the applied voltage
('IDS) will appear between the gate and the drain.
Since the pn junction is reverse-biased, little current
will flow in the gate connection. The potential gradient established will form a depletion layer, where almost all the electrons present in the n-type channel
will be swept away. The most depleted portion is in

.:r-Siliconix

LPD-1

~ incorporated

the high field between the gate and the drain, and the
least-depleted area is between the gate and the
source. Because the flow of current along the channel from the (positive) drain to the (negative) source
is really a flow of free electrons from source to drain
in the n-type silicon, the magnitude of this current will
fall as more silicon becomes depleted of free electrons. There is a limit to the drain current (I D) which
increased VDS can drive through the channel. This
limiting current is known as I DSS (Drain-to-Source
current with the gate shorted to the source). Figure
3B shows the almost complete depletion of the channel under these conditions.
Figure 3C shows the output characteristics of an nchannel JFET with the gate short-circuited to the
source. The initial rise in I D is related to the buildup
of the depletion layer as VDS increases. The curve
approaches the level of the limiting current I DSS
when I D begins to be pinched off. The physical
meaning of this term leads to one definition of pinchoff voltage, Vp, which is the value of VDS at which the
maximum I DSS flows.
In Figure 4, consider the case where VDS = a and
where a negative voltage VGS is applied to the gate.
Again, a depletion layer has built up. If a small value
of VDS were now applied, this depletion layer would
limit the resultant channel current to a value lower
than would be the case forVGs = O. In fact, at a value
of VGS > Vp the channel current would be almost
entirely cut off. This cutoff voltage is referred to as
the gate cutoff voltage, and may be expressed by
the symbol Vp or by VGS(off). Vp has been widely
used in the past, but VGS(oll) is now more commonly
accepted since it eliminates the ambiguity between
gate cut-off and drain pinch-off. VGS(off) and Vp ,
strictly speaking are generally equal in magnitude but
opposite in polarity.
The mechanisms of Figures 3 and 4 react together to
provide the family of output characteristics shown in
Figure SA. The area below the pinch-off voltage locus
is known as the triode or "below pinch-off" region:
the area above pinch-off is often referred to as the
pentode or saturation region. JFET behavior in these
regions is comparable to that of a power-grid vacuum tube, and for this reason JFETs operating in the
saturation region make excellent amplifiers. Note that
in the "below pinchoff" region bothVGS andVDS control the channel current, while in the saturation region
VDS has little effect and VGS essentially controls ID.

V OS < V p

Iii

D

S

I -----)
P

N

I

[\

-------

/

DEPLETION
LAYER

P

IG
(A) N-channel FET working below saturation
(VGS = 0 ). (Depletion shown only In
channel region).

VOS > Vp

r-----lll

:1------,

S

D

P

IG

'----------'

(B) N-channel FET working In saturation region
(V Gs = 0 ).

loss

SATURATION REGION

t

10

BELOW
PINCH-OFF
REGION

III

(C) Idealized output characteristic lorVGs = O.

Figure 3.

9-3

~Siliconix
incorporated

LPD·1

.LII

J..-IVDSI = Ivpl- IVGsl

I

DEPLETI ON
LAYER
S

D

,['I
P
r\ I
\N , _______ 1 i
-..=-

-----------'

P

I

o

G

Figure 4.

N-Channel FET Showing Depletion Due To
Gate-Source Voltage (V = 0).

DS

VDS--

vp

(A) Family of output characteristics for
n-channel FET

ID

Figure 58 relates the curves in Figure 5A to the actual circuit arrangement, and shows the number of
meters which may be conn~cted to display the conditions relevant to any combination of VDS and VGs.
Note that the direction of the arrow at the gate gives
the direction of current flow for the forward-bias condition of the junction. In practice, however, it is always reverse-biased.

The p-channel JFET works in precisely the same way
as does the n-channel JFET. In manufacture, the planar process is essentially reversed, with the acceptor
impurity diffused first onto n-type silicon, and the donor impurity diffused later to form a second n-type
region and leave a p-type channel. In the p-channel
JFET, the channel current is due to hole movement,
rather than to electron mobility. Consequently, all the
applied polarities are reversed, along with their directions and the direction of current flow. Figure 5A
shows the circuit arrangement for a p-channel JFET,
and Figure 58 shows the output characteristics of the
device. Note that the curves are shown in anotherquadrant than those of the n-channel JFET, in order
to stress the current directions and polarities involved.

9-4

+

~:
(8) Circuit arrangement for n-channel FET
Figure 5.
In summary, a junction FET consists essentially of a
channel of semiconductor material along which a
current may flow whose magnitude is a function of
two voltages, VDS and VGs. When VDS is greater than
Vp, the channel current is controlled largely by VGS
alone, because VGS is applied to a reverse-biased
junction. The resulting gate current is extremely
small.

g

Siliconix

LPD-1

incorporated

tate that free electrons will accumulate in the interface, inverting the p-type material and spontaneously
forming an n-type channel. Thus, a conduction path
exists between the diffused n-type channel source
and drain regions.
There are, however, some fundamental performance
differences between MOSFETs and JFETS. JFETs, by
nature, operate only in the depletion mode. That is, a
reverse gate bias depletes, or pinches off the flow of
channel current. A MOSFET, by virtue of its electrically-insulated gate, can be fabricated to perform as
either a depletion-mode or enhancement-mode FET.
Quite unlike the JFET, a depletion-mode MOSFET will
also perform as an enhancement-mode FET.

+

(A) Circuit Arrangement for p-channel JFET

G

V GS-

o

S

Vos-

.;=======~Vp======~~o

INSULATING

f=~!;~~~~~~~~~~~~LAYER

VGS(OFF)

t

p

10

SUBSTRATE

loss

I
I

(A) Idealized cross-section through an n-channel
depletion-type MOSFET
10

l-iVosi = iVPi-iVGsi
(B) Family of output characteristics for
p-channel JFET
Figure 6.

+

MOSFETS
The metal-oxide-silcon FET (MOSFET) depends on
the fact that it is not actually necessary to form a
semiconductor junction on the channel of a FET in
order to achieve gate control of the channel current.
Unlike the junction FET (JFET) a metallic or
polysilicon gate may be simply isolated from the
channel by a thin layer of silicon dioxide, as shown in
Figure 7A. Although the bottom of the insulating layer
is in contact with the p-type silicon substrate, the
physical processes which occur at this interface dic-

(B) Circuit arrangement for n-channel depletion
MOSFET.

Figure 7.

9-5

~Siliconix

LPD-1

~ inccrpcrated
Output Characteristics

200

Vos= 0.2 V /

160

/
~

120
10
(mA)

b

BO

40

o

./

J."/
I~ ' /
~~

-

o

..-

V,
/ /
'/

,

V

OV

I,

L-+*-

(A) p-type substrate

J ~O.4

...... ~

O.B

.".

~

~0.6 ~ _

OXIDE

~O.B V-

(B) Grow SI02

p-SILICON

-1 V_

1
0.4

hances a channel by attracting electrons beneath the
gate oxide will current begin to flow.

1.2

1.6

1
OXIDE

2.0

VDS (V)

(C) Grow polysilicon
n-type

p-SILICON

(C) Family of output characteristics for
an N-channel depletion MOSFET
Figure 7.

r====~~==iOXIDE
(D)

Where the greater majority of JFETs are fabricated
similar to that shown in Figure 2, and operate in a
fashion described in Figures 3 and 4, the MOSFET
can assume several forms and operate in either the
depletion/enhancement-mode
or
enhancementmode only.
There are, today, three popular styles of small-signal
::MOSFETs. First, we have the planar, lateral MOSFET,
similar to that shown in Figure 7A. By virtue of the
n-doped channel spanning from source to drain, it
performs as an n-channel depletion-mode MOSFET in
a fashion not unlike that of the depletion-mode JFET
when a voltage of the correct polarity is appliled to
the gate, as in Figure 7B. However, if we forwardbias the gate (that is, place a gate voltage whose
polarity equals the drain voltage polarity) additional
electrons will be attracted to the region beneath the
gate, further enhancing - and inverting (from p to n)
the region. As the channel region thickens, the channel resistance will further decrease, allowing greater
channel current to flow beyond that identified as
loss, as we see in the family of output characteristics
in Figure 7e.
This MOSFET also can be constructed for enhancement-mode-only performance, as shown in Figure 8.
Unlike the depletion-mode device, the enhancementmode MOSFET offers no channel between the source
and drain. Not until a forward bias on the gate en-

9-6

p-SILICON

Mask to leave
gate opening

(E) lon-Implant with poly
gate acting as mask

n

rC. . . -----'n~--l

(F) Etch contact areas
through oxide, metallze
and attach Source,
Drain and Gate

BODY
Figure 8.

Fabrication of Planar
Enhancement-Mode MOS

A newer MOSFET offering superior performance is
the lateral double-diffused or DMOS FET. Because of
the limitations of photo-lithographic masking, the earIier, older-style MOSFET was severely limited in performance. Some of these former limitations involved
switching speeds, channel conductivity (too high an
rDS). and current handling in general. The lateral
DMOS FET removed these limitations, offering a viable alternative betwean the JFET and the GaAs FET
for video and high-speed switching applications.

fCrSiliconix
.LII incorporated

LPD·1
MASK
(A) p-type substrate

(G) Replace mask,
Implant whole
with n+

CHANNEL

OXIDE

p-SILICON

(B) GrowSi0 2
n+

(H) Remove nitride

p,-{::::::==::OXIDE

p-SILICON

(C) Grow Silicon
nitride overlay
OXIDE

p

n+

J)

n+

(I) Poly over wafer

n;-

(J) Mask and etch poly

n+

(K) lon-Implant with
light n-

n+

(L) Metallze cpmtacts
contacts for
source, gate &
drain

p-SILICON
OXIDE

(0) Mask for gate

MASK

p-SILICON

OXIDE

p

n+

/NITRIOE

J)
p-SILICON

OXIDE

p-SILICON

(E) Etch nitride,
leaving gate
OXIDE

p

n+

, .... n

')

p-SILICON
(F) Mask drain area,
overlap gate.
Implant p-doped
channel

GATE

Pl-----I=====~

p-SILICON
SUBSTRATE

Figure 9. Fabrication of Planar Enhancement-mode OMOS

The lateral DMOS FET differs radically in its channel
construction when compared with the older planar
MOSFET. A self-explanatory series of construction
views of an n-channel, enhancement-mode device is
offered in Figure 9. Note the double-diffused source
implant into the implanted p-doped channel region,
shown in Figures 9 (f) and (g). The novelty that
improves the performance of DMOS is both the precisely-defined short channel that results and the
"drift region" resulting from the remaining p-doped

silicon body and light n-doped ion implant, shown if
Figures 9 (k) and (1).
Although Figures 8 and 9 illustrate the fabrication sequences for n-channel enhancement-mode DMOS
FETs, by reversing the doping sequences, p-channel
DMOS FETs could easily be fabricated. Furthermore,
by lightly doping across the short channel and drift
region, depletion-mode DMOS FETs could be constructed.

9-7

lCrSiliconix

LPD·1

~ incorporated

The combination of the short channel and the drift
region allows the MOSFET to operate in "velocity
saturation" (as a result of the short channel) and to
offer higher operating drain voltages (as a result of
the drift region). Together, both offer low on-resistance and low interlectrode capacitances, expecially
gate-to-drain, VGD.

Velocity saturation coupled with low interelectrode
capacitance offers us high-speed and high-frequency
performance.

The novelty of the short-channel DMOS FET led to the
evolution of a yet more advanced, higher-voltage,
higher-current MOSFET: the Vertical Double-Diffused
MOSFET, shown in Figure 10. Where this vertical
MOSFET offers improved power-handling capabilities,
its fundamental shortcoming is that, because of its
construction and to a lesser extent because of its
size, it fails to challenge the high-speed performance
of the latera! DMOS FET. Consequently, the vertical
and lateral DMOS FETs complement each other in a
wide selection of applications.

F

1000

(A) n-type substrate

"&'
(I) Gate oxide

n-

I.--__n_+_ _-,]

L

(9) Grow epitaxy
(J) Poly deposition &

I

gate mask

_=_=_=-=n--~=-=....>;t=f-'
SI0 GrowSI0
_
(e)
2

t=
I-

2

n+

(K) Etch oxide

E::J

(D) Mask & etch
(L) Diffuse p body

~~SI02

I

GJn-gLJ+
n+

L...-_ _ _ _- /

(E) Implant deep p+
and oxidation

~SENIC
n-

(F) Deposit photoresist
mask & remove
photoresist

LQ±5dJ

+
n+

~

I.----------------~

(M) n (arsenic)
Implant

(G) Etch photoresist

~
-

+

~==:;~~~~~~~~;::
METAL
n(H) Strip photoresist

n+

Figure 10.

9-8

Vertical n-channel, enhancement-mode DMOS FET

(0) Etch for source
contracts and
lay source metal

fCCSiliconix

LPD·2

~ incorporated

UNDERSTANDING JFET PARAMETERS
Bob Landon

JFET Characteristics
The JFET enjoys certain inherent advantages over bipolar transistors because of the unique construction
and method of operation of the field-effect device.
These characteristics include:
•
•
•
•
•
•
•
•

Low noise
"Zero offset" On-resistance
No thermal runaway
Low distortion and negligible intermodulation
products
High input impedance at low frequencies
Very high dynamic range (>100 dB)
Zero temperature coefficient Q point
Junction capacitance independent of 'device
current

The transfer function of a JFET approximates to a
square-law response. and the second and higherorder derivatives of gls are near zero; thus. strong
second and negligible higher-order harmonics are
produced. Intermodulation products are extremely
low.

frequency (VHF through L-band) oscillators to be
built which are far more stable than oscillators using
low-frequency crystals and multiplier stages.

JFET Terminology and Parameters
Any introduction to the nature. behavior. and applications of field-effect transistors requires that certain
questions be answered on JFET electrical quantities
and parameters. in particular the most important parameters. and the means by which they can be
measured. The following discussion will define specific JFET parameters and their associated subscript
notations. and present basic test circuits and results.
Major parameters include:
•
III

•
o
o

The input impedance of a JFET is simply the impedance of a reverse-biased pn junction. which is on the
order of 10 10 to 10 13 ! l . In practice. the input
impedance is limited by the value of the shunt gate
resistor used in a self-bias common-source circuit
configuration. At RF frequencies. the input impedance drop is proportional to the square of the
frequency. In a 2N4416 JFET. for example. the input
impedance would be 22 k!l at 100 MHz. Also. the
input susceptance increases linearly with frequency.
since it is a simple parasitic capacitance.
The JFET has a very high dynamic range in excess of
100 dB. Thus it can amplify very small signals because it produces very little noise. or it can amplify
very large signals because it has negligible intermodulation distortion products. It also has a zero
temperature coefficient bias point (zero TC point) at
which changes in temperature do not change the quiescent operating point.
Junction FET capacitances are more constant over
wide current variation than are the same parameters
in a bipolar device. This inherent stability allows high-

•
o

loss - Drain current with the gate shorted to
the source
VGS(off) - Gate-source cutoff voltage
I GSS - Gate-to-source current with the drain
shorted to the source
V (BR)GSS - Gate-to-source breakdown
voltage with the drain shorted to the source
g Is - Common-source forward transconductance
C gs - Gate-source capacitance
Cgd - Gate-drain capacitance

Special attention should be given to the subscript" s"
because it has two different meanings and three possible uses. In JFET notations. an "s" for the first or
second subscript identifies the source terminal as a
node point for voltage reference or current flow.
However. when using triple subscript notation. an "s"
for the third subscript is an abbreviation for
"shorted". and signifies that all terminals not designated by the first two subscripts must be tied together and shorted to the common terminal. which is
always the second subscript. Therefore. the term
I GSS refers to the gate-source current with the drain
tied to the source.
Because of the typical low input and output admittance of the JFET. four-pole admittance equations
are commonly used to describe electrical characteristics of the JFET:
(1)

9-9

.:r'Siliconix

LPD·2

~ incorporated

When Y11, Y21, Y12 and Y22 are defined as the input, reverse transfer, forward transconductance, and
output admittance respectively, Equation 1 reduces
to

(2)
i2 = Yf v11

+ Yov22

For a three-lead JFET, 11 usually corresponds to the
gate-source terminal and 22 corresponds to the
drain-source terminal (i.e., the device is connected
in the common-source mode). Thus

(3)

io

= YfsVgs + Yosvds

Here, the second subscript for the Y parameters designates the source lead as the common or ground
terminal.

loSS - Drain Current at Zero Gate Voltage
(10 at VGS = 0)
By itself, I DSS merely refers to the drain current that
will flow for any applied VDS with the gate shorted to
the source. However, when a particular value forVDs
is given, equal to or greater than Vp (see Figure 1),
I DSS indicates the drain saturation current at zero
gate voltage. Some JFET data sheets label I DSS for
VDS greater thanVp as ID(ONI'

VGS(off)

- Gate-Source Cutoff Voltage

The resistance of a semiconductor channel is related
to its physical dimensions by R = pLlA, where

=

p reSistivity
L = length of the channel
A = W x T =: cross-sectional area of channel
In the usual JFET structure, Land Ware fixed by device geometry, while channel thickness T is the distance between the depletion layers. The position of
the depletion layer can be varied either by the gatesource bias voltage or by the drain-source voltage.
When T is reduced to zero by any combination ofVGS
andVDs, the depletion layers from the opposite sides
come into contact, and the a-c or incremental channel resistance rDS, approaches infinity. As earlier
noted, this condition is referred to as "pinch-off" or
"cutoff" because the channel current has been reduced to a very thin sheet, and current will no longer
be conducted. Further increases in VDS (up to the
junction reverse-bias breakdown) will cause little
change in I D. Accordingly, the pinch-off region is
also referred to as the pentode or "constant-current"
region.

1.4

VGS - 0.2 V
1.2

I

1.0

I
0.2 V

O.B

loss

I
I
I
I
I
I
I
I
I - - SATURATION REGION---I
I
I
I
I
I
I
I
I
I
I
I
I

10

Vp
Vos
Figure 1.

9-10

JFET Characteristic at VGS

V(BR)GSS

=0 V

I
I

I

T

lo/Ioss
(Norm.) 0.6

I

O.B V

I

fI"'"

0.4

I

1.0 V

I

-I

/'

0.2

1.4 V

:

1

0
0

-5

-10

-15

-20

-25

Vos (V)

-30

V(BR)GSS

Figure 2. JFET Output Characteristics
In Figure 1, pinch-off occurs when VGS = O. In Figure
2, VGS controls the magnitude of the saturated I D,
with increases in VGS resulting in lower values of constant I D and smaller values of VDS necessary to
reach the "knee" of the curve. The current scale in
Figure 2 has been normalized to a specific value of
IDSS.

~Siliconix

LPD·2

~ incorporated

The knee of the curve is important to the circuit designer because he must know what minimum VDS is
needed to reach the pinch-off region with VGS 0 V.
When appropriate bias voltage is applied to the gate,
it will pinch off the channel so that no drain current
can flow; VDS has no effect until breakdown occurs.
the specific amount ofVGS that produces pinch-off is
known as the gate-source cutoff voltage, VGS(off) .

=

VGS(Off) Test Procedure
Although the magnitude of VGS(off) is equal to the
pinch-off voltage, Vp , defined by the pinch-off knee
in Figure 1, rapid curvature in the area makes it
difficult to define any precise point as Vp. Taking a
second derivative of VDs/1 D would yield a peak corresponding to the inflection point at the knee which
However, this is not a simple
approximates Vp.
measurement for production quantities of devices. A
better measure is to approach the cutoff point of the
I D versus VGS characteristic. This is easier than
trying to specify the location of the knee of the I D
versus VDS output characteristic.
A typical transfer characteristic I D versus VGS is
shown in Figure 3. The curve can be closely approximated by

ID = IDSS

(

1 -

V

Equation 4 and Figure 3 indicate that at VGS =
VGS(off) , I D =O. In a practical device, this cannot be
true because of leakage currents. If I D is reduced to
less than 1 percent of I DSS , VGS will be within 10
percent of the VGS(off) value indicated by Equation 4.
If I D is reduced to 0.1 percent of I DSS the indicated
VGS(off) error will be reduced to about 3 percent.
For a true indication of VGS(off), and a realistic picture of the parameters of Figure 3, care must be
taken that leakage currents do not result in an error
in the VGS(off) reading. Typically, at room temperature, 1 percent of I DSS is still well above leakage currents but is low enough to give a fairly accurate value
of VGS(off) .
A typical circuit for measuring VGS(off) is shown in
Figure 4. At VGS = 0 V, the value of IDSS can be
measured. Then by increasing VGS until ID is 0.01
percent of I D at some fixed value (such as 1 nA),
rather than as a certain percentage of I DSS. Thus a
pinch-off voltage specification may be given as indicated in Table I.

2

VGS

)

(4)

GS(off)

1.4

SLOPE = _"'_I_D_ = gfs
1.2 I - \ - - f - - f - -

'" VGS

Figure 4. Circuit for Measuring VGS(off)

V DS = -5 V

1.0
0.8
IDIIDss

(Norm.) 0.6
0.4
0.2
0
0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

VGs(V)

Another method which provides an indirect indication
of the maximum value ofVGS(off) is shown in Table II.
The characteristic specified is I D(off), where the parameter of interest is VGS = 8 volts. The specification
does say that the maximum VGS(off) is approximately
8 V, but no provision is made for stating a minimum
VGS(off) , as was done in Table I. Therefore, another

Figure 3.

Typical I D VS VGS Transfer Characteristic

test must be made if VGS(off) (min) is to be specified.

9-11

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Table I. Typical Plch-Off Voltage Specification.
Characteristics

Test Conditions
VDS = -5

Gate-Source pinch-off voltage

VGS(off)

Min

Max

Unit

1

4

Min

Max

Unit

-10

nA

v.

V

ID = -1 JJ.A

Table II. Indication of MaxlmumVaS(off)
Test Conditions

Characteristics

VDS
ID(OFF)

Pinch-off drain current
Vas

IGSS -

Gate-Source Cutoff Current

The input gate of a p-channel JFET appears as a simple pn junction; thus the dc input characteristic is
analogous to a diode V-I curve, as shown in Figure 5.
2

=-12 v.
=8 V

than 1000 M.a. The gate current is both voltage and
temperature sensitive. Figure 6 shows this relationship for IGSS versus temperature and VGs.
If the gate-source junction becomes forward-biased,
(negative voltage in a p-channel device) or if VGS exceeds the reverse-bias breakdown of the junction,
the input resistance will then become very low.

la
(JJ.A)

o

-10

10

20

30

40

V(BR)aSS
Vas (V)
-1

10

lass

Figure 5. P-Channel JFET Input Gate Characteristic
10-3 ..........._ ......_ ......_ ......_ ........_ ......._ ............
-50

In the normal operating mode, with VGS positive for a
p-channel device, the gate is reverse-biased to a
voltage between zero and VGS(off). This results in a
dc gate-source resistance which is typically more

9-12

-25

0

25

50

75

100 125 150

TA(OC)
Figure 6. I ass vs. Temperature

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The JFET is normally operated with a slight reverse
bias applied to the gate-source; hence, a good
measure of the dc input characteristic is to check the
gate current at a value of gate-channel voltage that is
below the junction breakdown rating.
In device
evaluation, there are the common measurements of
gate current: I GDO, I GSO, and the combined measurement I GSS.
These measurement circuits are
shown in Figure 7.

o
1?Ef~
~ I~GSS
D

~

VG

vG

S

Figure 7.

IGSO
S
~~

D

VG

S

~

Three Common Measurements of Gate
Current

The question is, should IGDO and IGSO be measured
separately, or will one measurement of I GSS suffice?
One thing is certain: I GSO + I GDO > I GSS, because the
drain and the source are not completely isolated.
They are, in fact, electrically connected via channel
resistance. For most JFETs, if VG is greater than
VGS(off), the difference between (lGSO + IGDO and
I GSS is small; therefore, the measurement of I GSS is
a realistic means of controlling both I GDO and I GSO.
In a circuit, VGD may be biased between zero and
V(BR)GSS, while VGS will be between zero and
VGS(off): therefore, I G is not necessarily the same
as IGss.

gate-drain voltage is greater than the gate-source
voltage; thus, the gate-drain breakdown rating is
most important. However, it is also possible to consider the gate-source junction breakdown and the apparent drain-source breakdown (i.e., in Figure 8,
when a high negative voltage is applied from drain to
source, CR1 will break down while CR n becomes forward-biased) .
Some device manufacturers use a BVGDO rating,
which means they are only checking diode CR1. A
better method is to use a ",BR)GSS rating (gatesource breakdown with the drain shorted to the
source), because it checks both CR1 and CR n, in
addition to exposing the weakest breakdown path
along the entire gate-channel junction. The ",BR)GSS
test also allows the user to interchange source and
drain lead connections without worry about device
breakdown ratings.
Admittedly, a "'BR)GSS test will reject some units
which might pass a BVGDO test; the number rejected, however, will be insignificant compared to the
advantage of providing symmetrical operation.
GATE o-----t---i+-..,.----o DRAIN

CR n_1

SOURCE

V(BR)GSS - Gate-Source Breakdown Voltage
JFET input terminals have been previously described
as having np or pn junctions, depending on the channel material. As such, the junction breakdown voltage is a necessary parameter.
A useful equivalent circuit for a JFET is the distributed
constant network shown in Figure 8, for a p-channel
JFET. If an n-channel device is being evaluated, the
diodes would be reversed. In most applications, the

Figure 8. A Useful JFET Equivalent Circuit

Test Procedures for V(BR)GSS
Junctions may break down softly or sharply; junctions
with soft knee breakdown are undesirable. Without
examining each individual unit on a curve tracer, devices with a soft knee may be eliminated by selecting
a low current level for breakdown measurement (see
Figure 9).

9-13

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-

....... g's/g's

.......

"

r\.

I D/IDSS
ID/IDSS
SOFT KNEE (FAILING)
Figure 9.

9 fs

SHARP BREAKDOWN

g's/g,s

\

\

iNonro.) 10-2

Example of Soft Knee and Sharp Knee
Breakdown

5 V f - 1 kHz
FOR g,s MEASUREMENTS

Vas -

- Transconductance
10-3

Transconductance, g fs, is a measure of the effect of
gate voltage upon drain current:
6.ID
gfs = 6.VGS ; VDS =

constant

0.2

IDSS
= - --'==---

0.6

0.8

\
1.0

The drain current of a JFET operating in the triode
(below pinch-off) region can be accurately predicted
by using Equation 8, where

(6)

I

VDS
VGS(off)

)1/2

(8)

(7)

VGS(off)

Specifications for g fs are shown in Tables III and IV.
Note that there is a difference in the test conditions
specified for the n-channel and the p-channel
devices. The gate voltage for the n-channel is established as zero. This means that g fs is measured at
ID = IDSS, as in Table III.

where g fso is the value of g fs at VGS = 0 V and I DSS is
the value of ID atVGS = 0 V. With these equations,
the value of g fs can be calculated with a fair degree
of accuracy (20 percent) if I DSS and VGS(off) are
known.
Figure 10 shows normalized curves for I D and g fs as
functions of VGS in a P-Channel JFET. These curves
were obtained from actual measurements on typical
diffused channel JFETs. The curves agree very well
with Equation 4 and 6 until VGS(off) is approached.
For these curves, VGS(off) was assumed to be the
value of VGS where I D/I DSS = 0.001.

The test conditions shown in Table IV specify a certain value for I D (-200 1lA). This means that for
each unit tested, VGS is adjusted until I D equals the
specified value. The conditions specified in Table II
simplify testing of the g fs parameter by eliminating
the necessity of adjusting VGS. Figures 11 and 12
show typical test systems for the two methods.

Table III.
Characteristics

Test Conditions

Min

Max

Unit

4,500

7,500

,I.lS

V DS = 15 V.

g,s

9-14

1.2

Figure 10. Normalized Curves for I D and g,s as Functions of Vas

(5)

I D triode = I DSS (
g fso

0.4

VaslVaS(ofl)

The interrelation of g fs to the parameters I DSS and
VGS(off) should be noted. Equations 4, 6, and 7 describe the value of I D and g fs in a JFET for any value
of VGS between zero and VGS(off) .
VGS)
gfs= gfso ( 1 - -V--GS(off)

o

Smail-signal common-source
forward transconductance

Vas= 0,

f = 1 kHz

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incorporated
Table IV.
Characteristics

Test Conditions
Va's

gls

Common-source

forward transconductance

10

f

=
=

20 V,
200J.lA

Min

Max

Unit

700

1,600

J.lS

= 1 kHz

V

Figure 11. Test Circuit for g Is with VGS = OV

Junction FET Capacitances
Associated with the junction between the gate and
the channel of a JFET is a capacitance whose value
and geometric distribution are functions of the applied voltages VGS and VDS. Because of the complexity of dealing with such a distributed capacitance.
a simplification is made so that two lumped capacitances. C gs and Cgd. exist between the gate and the
source and drain. respectively. (A much smaller capacitance. Cds. also exists between the drain and the
source. stemming mainly from the device package;
this header capacitance is small enough so that it
can be ignored for most purposes.)

Data sheets quote C gs and Cgd (or other capacitances from which they may be derived) for specified
operating conditions. Occasionally. graphs are included which show the variations of C gs and Cgd as
the result of changing conditions of VDS. VGS and
temperature. If this data is not presented. an estimate of interelectrode capacitance values may be
made by assuming that these values vary inversely
with the square root of the bias voltage. The temperature variations will be very small. because they

V

Figure 12. Test Circuit for gls with

10

Specified

depend on the -2.2 mVo C change in junction potential difference.
Assuming that the JFET is properly biased - that is
the dc conditions are met by the external circuitry - it
is possible to construct an incremental equivalent circuit from which the small-signal or ac performance
may be predicted. Such an equivalent circuit is
shown in Figure 13.

G 0---...,...--+-"""1 I---+-~r---'----- 2 VGS(oll) + Rs I DQB.

An alternate method, that selects RD to provide a
specified voltage gain, follows Steps 1 and 2 above
and then proceeds as follows:
Step 3

Determine required stage gain,AV, and set
RD =AV/glsQ'

Step 4.

Calculate VDSQ to ensure that the criteria of
Step 2 are not violated:

VDSQ = VDD - (RD + Rs) I DQ
Step 5.

(6)

If necessary, change I DQ ,VDD, Av andlor
RD to obtain an optimum compromise.

9-23

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FET SOURCE-FOLLOWER CIRCUITS
The common-drain amplifier, or source follower, is a
particularly valuable configuration; its high input impedance and low output impedance make it very
useful for impedance transformations between FETs
and bipolar transistors. By considering ten circuits
(Figure 10), which represent virtually every sourcefollowsi cOiifiguiatioii, the designer can obtain consistent circuit performance despite wide device variations.
There are two basic connections for source followers: with and without gate feedback. Each connection comes in several variations (Figure 10). Circuits
10(a) through 10(e) have no gate feedback; their input impedances, therefore, are equal to RG. Circuits
10 (f) through 10 (k) employ feedback to their gates
to increase the input impedance above RG.
Before getting into the details of bias-circuit design,
note several general observations that can be made
about the circuits of Figure 10:
Voo

•

Circuits a, c, d, f, h, and j can accept only positive and small negative signals, because these
circuits have their source resistors connected to
ground. The other circuits can handle large
positive and negative signals limited only by the
available supply voltages and device breakdown
voltage.

•

Circuits c, d, e, h, j, ~lnd k employ current
sources to improve drain-current Q0) stability
and increase gain.

•

Circuits d, e, and k employ FETs as current
sources. In circuit d, 02 must have a lower cutoff voltage, VGS(off), and a lower zero gate-voltage drain current, loss, than 01.

•

Circuits e, g, and k employ a source resistor,
R s, which may be selected to set the quiescent
output voltage equal to zero.

•

Circuits e and k use matched FETs. Rs is selected to set I D near the specified low-drift operating current. The input-output offset is zero.

Voo

Voo

Voo

Voo
01
RSI

B

RG

Rs

RG

Rs

02
RS2

0

-=-

-=-

-Vss

-::-

a

b

Voo

-Vss

c

Voo

d

Voo

e

Voo

Voo

01

RG

RSI
RS
02
RS2

-=-

-Vss

g

h

-Vss
k

Figure 10. Virtually every practical source-follower configuration Is represented In this collection of ten
circuits. The configurations in the top row do not employ gate feedback; the corresponding
ones In the bottom row do.

9-24

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Biasing Without Feedback Is Simple

...--------------r 1.5
Vos = 15 V

The no-feedback circuits of Figure 10 (circuits 10(a)
through 10(e) use simple biasing techniques (see
the earlier article). Circuit 10(a) is a self-bias configuration; the voltage drop across Rs biases the
gate (which draws essentially zero current) through
resistor RG. Since no gate-to-source voltage, VGS,
can be developed when I D = 0, the self-bias load line
passes through the origin (Figure 11). The quiescent
drain current is seen to lie between about 0.25 and
0.55 mA when a 1 k!1 source resistor is used. The
quiescent output voltage lies between 0.25 and
0.55 V.

1.2

0.8

10
(mA)

0.4

I-....,..-"F---..,r--..,...-;;-~-"T'"~f-

-1.6

-1.2

0

o

-0.4

-0.8
VGS (V)

Figure 11.

Self biasing (Figure lOa) uses the
voltage dropped across the source
resistor, R S to bias the gate. The
load line passes through the origin
and has a slope of -1IR s .

1.5
VOS = 15 V
1.2

0.8

10
(mA)

Rs = 50 k!l. Vss = -15 V

0.4

RS = 10 k.o. Vss = -1.6 V

-1.6

-1.2

-0.8

o

-0.4

0.4

0.8

1.2

1.6

VGS (V)

Figure 12. Adding aVss supply to the self-bias circuit (Figure lOb) allows It to handle large
negative signals. The load line's intercept with theV Gs axis Is at VGS =Vss .
Bias lines are shown for Vss = -15 V and Vss = -1.6 V.

Circuit 10(b) is another example of source-resistor
biasing with a -Vss supply added. The advantage
over circuit 10 (a) is that the signal voltage can swing
negative to approximately -Vss, Two bias lines are
shown in Figure 12, one for Vss = -15 V and the
otherVss -1.6 V. For the first case, the quiescent

=

output voltage lies between 0.18 and 0.74 V. For the
second, it lies between 0.3 and 0,82 V.
The bias load line for circuit 10(c) is just a horizontal
line QD = constant), The quiescent output voltage is
between 0.15 and 0.7 forlD = 0,3 mA,

9-25

..

g

LPD-3
Circuit 10(d) is similar to 10(c) except that theVGS =
o output characteristic of FET Q2 is used as a current

Siliconix

incorporated
1.5

Ves=15V

source. As seen in Figure 13. Q2 does not supply
constant current when its Vos gets very small. This
technique should therefore be used only to bias FETs
whose VGS(Off) is significantly higher than the equivalent VGS(off) of the current-source FET diode.

1.2

0.8

Ie
(mA)

RS2=;'5 k..'l

.--------------~

~

1.5

Ves = 15 V
1.2

0.4

~~--~--~~~~~--~~~ 0
-O.B
-0.4
-1.2
o

-1.6
O.B

Ie
(mA)

VGS (V)
Figure 14. This load line Is set byR s2 and Q 2
which acts as a current source (Figure
1De). This source follower, therefore.
exhibits zero or near-zero offset. If the
FETs are temperature-matched at the
operating I e, the source follower will
exhibit zero or near-zero temperature
drift.

0.4

-1.6

-1.2

-0.8

o

-0.4

A pair of matched FETs is used in the circuit of Figure
10(e). one as a source follower and the other as a
current source. The operating drain current (I OQ) is
set by RS2. as indicated by the load line of Figure 14.
The drain current may be anywhere from 0.2 to 0.42
mAo as shown by the limiting transfer characteristic

VGS (V)
Figure 13. FET Q2 doesn't behave like an Ideal
current source when Its Ves gets
very small (Figure 1Od). Therefore,
Q, should have a significantly larger
V GS (off) than the Q 2 does.

intercepts; however. VGSl
are matched.

r--------------,-

=VGS2

because the FETs

1.5

Ves=15V
1.2

O.B

Ie
(mA)
Rs+Rl=10k!'l.

0.4
Rs+ Rl = 10 k!'l.

-1.6

-1.2

-O.B

-0.4

0
VGS (V)

0.4

O.B

1.2

1.6

Figure 15. The bias load line Is set byRs but the output load line Is determined by Rs + R, when gate feedback Is
-"Jmployed (Figure 10f). The feedback VFB is determined by the Intercept of the Rs + R, load line and
the VGS axis.

9-26

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. . . - - - - - - - - - - - - - - , - 1.5
VDS = 15 V

ID
(mA)

Rs+Rl=50J<,O. ;Vss =-15V

-1.6

-1.2

-O.B

o

-0.4

0.4

O.B

1.2

1.6

VGS (V)

Figure 16.

Rs can be trimmed to provide zero offset at some point between 670.0. and 2.5 J<,O. (Figure
109). The source load line Intercepts the VGSaxis atV ss =V GG = -15 V. Note that this
load line Is not perfectly flat. It has a slope of -1 150 J<,O. • because the current source Is not
perfect; It has a finite Impedance.

Biasing With Feedback Increases

Z IN

Each of the feedback-type source followers (Figure
10(f) through 10(k) is biased by a method similar to
that used with the nonfeedback circuit above it. However, in each case, RG is returned to a point in the
source circuit that provides almost unity feedback to
the lower end of RG. If Rs is chosen so that RG is
returned to zero dc volts (except in circuit 10 (f), then
the input/output offset is zero. R 1 is usually much
larger than R s .

Circuit 10(f) is useful principally for ac-coupled circuits. Rs is usually much less than R 1 to provide
near-unity feedback. The bias load line is set by Rs
(Figure 15). The output load line, however is determined by the sum of R s + R 1 • The feedback voltage
VFB, measured at the junction of R sand R 1 , is determined by the intercept of the R s + R 1 load line with

the VGS axis. The quiescent output voltage is VFB VGs.
In the circuit of Figure 10 (g), Rs can be trimmed to
provide zero offset. As the curves show (Figure 16),
Rs will be between 670 il and 2.5 kil. Rs is much
less than R 1 . The source load line intercepts the VGS
axis at Vss = -VGG = -15 V.
Circuit 10(h) is almost the same as 10(g); the difference is that resistor R 1 is replaced by a current
source. Since an ideal current source has infinite impedance, the bias curve of circuit 1 (h) differs from
that of Figure 10 (g) (Figure 16) in that the load line is
perfectly flat. In Figure 16 the load line is almost, but
not quite, flat; it has a slope of -1/50 kil.
Circuit 10(j) is similar to 10(h) except that the output
is taken from the top of Rs to reduce the output impedance. Rs must be trimmed if the circuit is to work
properly.

9-27

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.HSiliconix

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incorporated

1.5
V Ds =15V

ID
(mA)

Is = 0.3 mA

-1.6

-1.2

-0.8

o

-0.4

I

I

I

I

0.4

0.8

1.2

1.6

V GS (V)

Figure 17.

If R s Is not trimmed so that the load line passes through the origin, a voltage will appear at the
gate causing a reduction in dc input Impedance. The incremental input impedance will not be
affected.

In Figure 17, the constant-current load line represents a 0.3 mA current source, and the effect of a
1 kil source resistor is shown. The offset voltage is
seen to lie between 0.2 and 0.75 V. The intercept of
the Rs load line and the VGS axis sets the voltage at
the junction of Rs and the current source (VFB). For
Rs = 1 kil, VFB wiii be between -0.1 V and 0.45 V.
Since VFB appears at the gate. it must be zero if the
dc input impedance of the circuit is to be preserved.

9-28

This can be done by trimming R s. as shown dashed
in Figure 17. The biasing then becomes the same as
for circuit 10 (h).
Biasing for circuit 10 (k) is identical to that for circuit
10(e) (Figure 14) except that feedback is added to
raises the input impedance.

~Siliconix

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HIGH JFET GATE INPUT RESISTANCE SERVES WELL IF YOU CAN UTILIZE IT
Ed Oxner

Reprinted from EON, February 20, 1979
©1988 CAHNERS PUBLISHING COMPANY

a Division of Reed Publishing USA

Many designers try to take advantage of high JFET
input resistance, only to be disappointed with the results. Understanding the reasons for this characteristic can help you make the most of a useful JFET
property.
One of the most widely known characteristics of
JFETs - their high gate input resistance - is rarely
specified on these devices' data sheets. But deriving this important parameter correctly from the information provided, and then applying it properly, are
the keys to good JFET circuit design.
The sampling-probe circuit shown in Figure 1 is an
example of a common JFET application. It utilizes as
a source follower a 2N4868A n-channel device with a
drain voltage of 30 V and a 1-mA drain current. Because this probe must sample 10 V-rms signals on a
high-impedance line and must not load the circuit under test, it must also exhibit a very high input resistance. Assuming the data sheet for the JFET used in
the probe lists a 40-V minimum breakdown voltage
and a 250-pA maximum I GSS, the probe circuit design does not provide the required high input resistance.

If you design a circuit with at least 10 Mil input resistance - such as the circuit in Figure 1 - and the JFET
data sheet lacks an input-resistance specification,
you can extract an indication of this important parameter from another specification: gate current,
which is inversely proportional to gate input resistance. Thus, JFETs with a 1-mA gate current provide
an input resistance orders of magnitude lower than
those with a l-nA gate current.

~O.OI.11F

A MASTERY OF JFET CIRCUIT DESIGN BEGINS WITH THE DATA SHEET
To understand what's wrong with the circuit depicted
in Figure 1 (and it isn't the JFET that's at fault), consider the roots of the problem. The JFET is used incorrectly here because of any or all of the following
faults:
•
•
•

An improperly characterized data sheet
An improper interpretation of the data sheet
A misunderstanding of why a JFET exhibits a high
gate input resistance

You can't do much about the first fault except to
make sure you know enough about these devices to
recognize misleading data when you see it. For the
most part, though, the latter two faults are the ones
primarily responsible for incorrect JFET use.

Figure 1.

This JFET-input probe is designed for
failure.

However, unwary designers can also fall into the trap
of using I GSS - gate current with the drain terminal
shorted to the source - as an indicator of input resistance. But I GSS does not characterize the operating
gate current - clearly, the JFET's high input res istance is not utilized with the drain shorted to the
source. Some years ago, the commonly accepted
design procedure specified gate current at about 1/2
IGSS for the desired drain-gate voltage. But this is a
reasonable approximation only so long as the draingate voltage remains below the "IG breakpoint."

9-29

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~

LPD·4

~Siliconix

~ incorporated

The way out of this dilemma is to recognize that I GSS
represents nothing more than a measurement of
reverse-bias diode current.
10-8

With source shorted to drain, the channel becomes a
cathode and the gate becomes an anode, and their
interaction can be considered to constitute a simple
aioae. in tnis aloae moael, tne reverse current typIcally stays small until it increases abruptly at some
finite voltage - termed the reverse (avalanche)
breakdown voltage - because of a process called
avalanche multiplication.

Reverse current itself originates principally from the
thermal generation of electron/hole pairs within the
JFET's junction space-charge region.
Avalanche
multiplication then occurs when an electron within
this space-charge region develops so much energy,
through increasing acceleration and subsequent collisions, that other electron/hole pairs are created, resulting in rapidly increasing reverse current and rapidly decreasing gate input resistance.

10-9

IG
(A)
10-10

10 (A)
Figure 2.

Gate current Is a linear function of drain
current In the 2N4666 JFET.

10-6

JFETs Act Differently In A Circuit
10-7

An operating JFET differs from the preceding diode
model because its drain is not shorted to the source
and some finite drain current passes through the
channel. Designers, furthermore, often overlook this
drain current's effects upon gate current.

10-8

10-9

IG(A)

Illustrating the drain-current effect, Figure 2 shows
that gate current (I G) increases linearly with drain
current when the drain-gate voltage exceeds the I G
breakpoint; it also indicates that I G increases exponentially with the drain-gate voltage (VOG). (RaiSing
the VOG level increases impact ionization, thus increasing gate current.)

Replotting Figure 2 as Figure 3, this time using draingate voltage as the primary variable, exposes the
critical relationship between these two parameters.
The tremendous difference between the I G curves
and the superimposed I GSS characteristic reveals the
folly of using I GSS values above the I G breakpoint to
determine gate input resistance.

9-30

10-10

10-11

10-12

10-13

10-14
0

15

30

45

60

VOG (V)
Figure 3.

A plot of gate current versus drain gate
voltage for the 2N4666 JFET shows why
you can't use IGSS values above the
breakpoint to determine gate Input resistance.

g

Siliconix

LPD-4

incorporated

Yet another plot of the same JFET data yields additional information. Figure 4 shows a comparison of
two ratios: gate current to drain current (I GIlD) versus drain-gate voltage to drain-gate breakdown
voltage (VOG IBVoGo). Figure 2 provides data for
the current ratio and Figure 3 furnishes voltage figures, with the drain-gate breakdown voltage established at the 57 V IGSS breakpoint.)

7

If you have an application requiring high input resistance, you are thus confronted with something of a
problem. If you don't care to tediously characterize
selected JFETs yourself, you can only hope that the
vendor has overridden the JEDEC format in its catalog and has included operating-gate-current figures.
Alternatively, the vendor might offer a graphical presentation of gate-current data as in Figure 3. How
ever this information is presented, be aware that the
operating gate-current characteristic for a particular
JFET type can vary among manufacturers. Thus, if
you change vendors - watch out.

V--CHANNEL
10-4

/V

10-5

~
10

10-6

/

10-7

I

10-8

10-9

o

0.2

'7
I1cHANNEL_

0.4

0.6

I I

0.6

1.0

1.2

VOG

~GO
Figure 4.

The Data Sheet's To Blame
Although high gate input resistance is important in
many applications including differential and operational amplifiers (as well as in the probe example
here), the spec sheets for many JFETs offer no hint
of operating gate current.

10-2

10-3

similar to that of the n-channel device, but because
of this device's lower mobility and the resulting lower
impact ionization, the p-channel curve is pushed out
to a higher voltage and, therefore, presents less of a
problem.

Normalized gate-current (leakage) variations depend upon drain-gate voltage.
plotted here for n- and p-channel JFETs.

While Figure 4 illustrates the dependence of currentratio (leakage) characteristics on drain-gate voltage,
it also simultaneously shows this parameter's independence from the type of n-channel JFET - fabrication technique employed. Curve A represents ratios
from both a short-channel JFET and a long-channel,
high-frequency JFET.
The problem of gate-leakage dependence on draingate voltage, however, is a characteristic principally
of n-channel devices. The p-channel JFET (represented by curve B in Figure 4) exhibits a response

Referring back to the example presented at the beginning of this article, you should understand by now
why the probe doesn't perform as expected. The
drain-gate voltage is a combination of the +30-V bias
supply and the peak negative potential of the
10-VRMS signal appearing at the gate. The gate current, therefore, peaks to nearly 1 f,LA, and the input
resistance falls short of the levels it could attain.
If you want to remedy this problem, one solution is to
lower the bias voltage from +30 V to +20 V, thereby
increasing the probe's input resistance to an
acceptable level. You could, however, choose a
better solution that permits high drain voltages and
appreciable gate potentials without losing the JFET's
unique high gate input resistance by using a cascade
circuit similar to the one shown in Figure 5b. In this
arrangement, the input JFET's drain potential remains low because of its interaction with the piggyback JFET. Figure 6 compares the gate currents
(and thus the input-resistance performance) of the
two circuits depicted in Figure 5 and demonstrates
the advantage of the dual-JFET configuration.

9-31

II

LPD-4
(A)

.:rSiliconix

~ incorporated
30 V

(8)

10 V

-30 V

-30 V

Figure 5.

A slngle-JFET circuit la) offers simplicity, but It might not provide the high Input resistance you
want. A cascode dual-JFET alternative Ib) selves the Input-resistance problem.

10-6

10-7

\

r\

10-8

\t,

10-9
'olA)

10-10

10-11

1\

10-12

\ r-....

(8)

10-13
-30

-20

-10

o

10

20

30

Veo IV)

Figure 6.

9-32

A plot of gate current for both circuits In Figure 5 reveals that the dual-JFET one maintains Its
low gate current over a much wider operating-voltage range.

ICrSiliconix

LPD-5

~ incorporated

AUDIO-FREQUENCY NOISE CHARACTERISTICS
OF JUNCTION FETS
Bruce Watson

INTRODUCTION

Total available output noise power

F

The purpose of this application note is to identify and
characterize audio frequency noise in junction fieldeffect transistors (JFETs). Emphasis is placed on
basic device characteristics rather than on end
applications, since it is important for the circuit
designer to know the salient noise behavior of the
JFET and how those characteristics may be specified
by production-oriented test parameters.

Noise power at output due to thermal noise of

Rc>

or
Noise power output due to Ra+ noise power
output due to FET

F

Noise power output due to Ra
or

F = 1+

Noise power output due to FET
Noise power output due to Ra

or

Defining the FET Noise Figure

F = 1+

For analysis, it is convenient to represent noise in a
FET by assuming that an ideal noise-free device has
two external noise sources, en and Tn. These noise
sources are chosen to have the same output as an
actually noisy FET. An equivalent circuit is shown in
Figure 1.

Gain X noise power of FET referred to Input
Gain X noise power due to Ra

or
F = 1+

Noise power of FET referred to Input
Noise power due to Ra

The thermal noise voltage across RG is
(1 )

,
L. _ _

I
I
I
.J

where k = 1.380 x 10-23 Joules/oK (Boltzmann's
Constant), T = temperature in oK , and B = bandwidth in Hz. Therefore, noise power due to RG is
ST 2

_

RG

-

4kTRGB
RG

= 4kTB

(2)

The noise power of the FET referred to the input is
- 2

+ i n · RG

Figure 1.

Representing Noise in an Ideal FET

A noise factor (F) is a Figure of Merit of a device with
respect to the resistance of a generator. To calculate
a noise factor, a source resistor, RG , with a thermal
noise voltage, ST , is added to the circuit.
A noise factor (F) may be defined as

(3)

When expressions for the noise power of both the
FET and RG are substituted, the noise factor becomes

F

=

Sn 2 + In 2 RG2
1 + -=":'~':"""":',!!-...:..:.l,;!4kTRGB

(4)

A noise figure (NF) expressed in dB indicates the
presence of added noise power from the FET or another active device. The noise figure is always given
with reference to a standard, specifically the generator resistance RG:

9-33

LPD-5

.r-Siliconix

~ incorporated

where n varies between 1 and 2 and is device- and
lot-oriented.

(5)

NF = 10 10910 [F]
The noise figure of the FET is
NF

= 10 10g10 [ 1 + -en 2

2J
RG
dB
4kTRGB

+

.,. 2

The characteristic bulge in en in the 1If n region has
been observed to some extent in all junction FETs
submitted for testing. The breakpOint or corner frequency shown as fl in Figure 2 is lot- and device
design-oriented, and varies from about 100 Hz to
1 kHz.

(6)

In

When junction FET noise is expressed in terms of the
noise figure (NF), an inherent disadvantage arises
because the noise figure value is dependent upon
the value of the generator resistance, RG . Therefore, the en , Tn method remains as the best way to
quantitatively express the noise characteristics of the
FET.

As indicated in Equations (7) and (8), en is inversely
proportional to the square root of the transconductance of the FET

(en

C\!

1 IVQ;s).

en

can be lowered

by a factor of 1/VN if N devices with matched
electrical characteristics are connected in parallel.
For example, when

Describing Junction FET Noise Characteristics
Junction FET en and Tn characteristics are frequency-dependent within the audio noise spectrum
and take the form as shown in Figure 2.

N = 2

(9)

let

en '

the equivalent short circuit input noise voltage
(with the exception of the 1If n region), is defined as

(10)
and let

(7)

(11)

where RN = 0.67/91s , the equivalent resistance for
noise. The en, except in the 1If n region, closely
approximates the equivalent thermal noise voltage of
the channel resistance.
In the so-called 1If n region,

en

Thus,

From equation (7)

is expressed as

e nl =..j 4kT

(8)

10-13

=
i==
f--

f-100
EQUIVALENT
SHORT -CIRCUIT
INPUT NOISE
VOLTAGE
(NV/VHz)

(13)

(0.671 glsl) B

1K

en-

n

1If OR FLICKER
EXCESS NOISE
REGION

I

I I I

III

10-14

BREAK
POINTS

~ ,en

I

~

10

=i
=

-I

GENERATOR
RECOMBINATION
OR SHOT NOISE
REGION

JOHNSON OR
NYQUIST THERMAL
NOISE REGION

J

I

III

i nI

SLOPES
1/1 n
n - 1 to 2

~ I-'--

In

10-15

II

11111

10

100

II
1K

~ITI
10 K

I - FREQUENCY (Hz)
Figure 2.

9-34

(12)

gls TOTAL = 2 glsl or 2 gls2

Characteristics 01 Junction FET Noise

10-16
100 K

EQUIVALENT
OPEN-CIRCUIT
INPUT NOISE
CURRENT
(AMP/VHz)

ICrSiliconix

LPD·5

~ incorporated

was originated in the hearing aid industry because of
noise or level shifts which are present in input
stages, and which resemble the sound of corn popping.

and
en TOTAL = Y4kT (0.671 2g ls1 ) B

(14)

Thus,
en TOTAL

=

fi

en1

(15)

Popcorn noise is a form of random burst input noise
current which remains at the same amplitude and
which is confined to frequencies of 10Hz or lower.
The suitability of a FET device is dependent on the
amplitude of the burst, its duration, and its repetition
rate. The origins of popcorn noise are not completely
identified, but are believed to be caused by intermittent contact in aluminum-silicon interfaces and by
contamination in the oxidatin processes.

A second way to achieve low en is to use a device
with a large gate area. Empirically, en is inversely
proportional to the square of the gate area (en (Ii
1/AG 2 ), independent of gfs . This large gate area
philosophy has been followed in the design of the
Siliconix 2N4867 A FET, and noise performance of the
device is discussed later in this application note. A
major advnatage of this design is that en is significantly lowered and Tn also remains at a low value.

A test circuit to measure popcorn noise in differential
junction FET amplifiers is shown in Figure 3. In practice, popcorn noise is evaluated on an engineering
basis, not on a production-line basis. No correlation
between 1If n noise at 10Hz and popcorn noise has
yet been found in junction FETs. However, if the amplitude of the burst is large and occurs frequently,
then 1/f n noise voltage (en) is masked and difficult
to evaluate at 10Hz.

The equivalent open-circuit input noise current, Tn,
with the exception of the shot noise region shown in
Figure 2, is due to thermally-generated reverse current in the gate channel junction. It is defined as

(16)

where q = 1.602 x 10- 19 coulomb (the magnitude of
the electron charge), I G is the measured dc operating gate current in amperes, and B is bandwidth in
Hz. The expression is accurate only when the measured gate current is the result of bulk device conductance. It is possible for the measured gate current to
be due to conductance stemming from contamination across the leads of the semiconductor package.
At higher frequencies, as in the shot noise region
shown in Figure 2, Tn can be approximated as being
equal to the Nyquist thermal noise current generated
by a resistor:

I
1

1

1
1

1

1

1

1

1

(17)

where Rp is the real part of the gate-to-source input
impedance. The breakpoint or corner frequency f2 in
Figure 2 is lot- and device design-oriented and can
vary from 5 kHz to 50 kHz.
Another form of noise found in junction FETs is known
as "popcorn" or burst noise; the term popcorn noise

------1
+9 V

1

L

~\

f.
~

50

n

1 ..

~LbTTER

-=-1 -=-

CONSTRUCTION IS
SHIELDED ENCLOSURE WITH 1
SELF-CONTAINED BATTERIES
-9V
_ _ _ _ _ .J

Figure 3.'

)

Test Circuit to Measure Popcorn Noise

The graph in Figure 4 shows "moderate" burst noise
observed in a group of junction FET differential amplifiers which were measured in the test circuit.

9-35

Ell

LPD·5

~Siliconix

~ incorporated

~

f- x-Y LOTTEJ TIME
_

30 SEC

04--

TA=1250C

0.4 JlV REFERRED TO INPUT

n

NOISE
BURST

f

NOISE
BURST

I

STABL~

DC("'VGs/"'T)
DRIFT ONLY

,...

I

I

J 1..! ~.-.~

+l/f n en
I

NOISE
BURSTS~

I

Figure 4.

NOISE
BURST
AND l/f en

I
Popcorn Noise In Differential Amplifiers

Operating Point Considerations
Unlike bipolar transistors, where en and Tn characteristics vary directly with changes in the collector
current (I c), similar characteristics in junction FETs
will vary only slightly as drain current (I D) is varied.
This is true as long as the FET is biased so that the
drain-source voltage is greater than the pinch-off
voltage (VDS > Vp or VaS(off) ).
The en in junction FETs will be lowest when the devices are operated at Vas = 0 (I D = I DSS), where
transconductance (gfs) is at its highest value. This
will be true only if device dissipation is maintained
very low in relation to the total dissipation capability
of the FET.
The curves shown in Figure 5 illustrate changes in en
as the operating drain current (l D) is varied. Note
that the lowest en did not occur at Vas = 0 because
of high power dissipation and a resultant rise in junction temperature at the operating point.

ing point is changed, provided that the drain-gate
voltage is maintained below the gate current (Ia)
breakpoint and power dissipation is kept at a low
level. The curves shown in Figure 6 illustrate Tn characteristics as a function of drain-gate voltage at
points below, on, and above the la breakpoint voltage.

loss = 35 mA
T A = 25°C

100
en
(nV/VHz)

en @ 10 = 0.01 loss _H-ttHtti

1 0 - ,_ _

f - FREQUENCY (Hz)

The optimum (lowest) Tn in depletion-mode junction
FETs should occur at Vas = 0 (I D =I DSS). In practice,
very little change will be seen in I D when the operat-

9-36

Figure 5.

en Changes vs. 10 Variations

~Siliconix

LPD-5

~ incorporated

-10

10-13

2N3822
(NRL GEOMETRY)

-

10 -14

-

In
(A/-JHz)

t::
2N3822
~
1=
(NRL GEOMETRY)
I- HIGH Jl. TYPE

VDG - 40 V

mlr"i

1I~0

-1

v'

I

20 V

IIII

I

I G "BREAKPOINT" ::
~

10 V
-

10-16

//

IG -0.1
(nA)

"i'5 V

10-15
I D - O. 1 I DSS
T A = 25°C
"'"
10
100

-0.01

I

IIII I
10 K

-0.001

ID - 1 m,!..-

~./;'~ - 100 l M
10
15
20
25
VDG - DRAIN-GATE VOLTAGE (V)

o

100 K

Figure 7.

L Characteristics as Function of

-100

en

=

112 2N5911
~ ~ T A = 25°C~
(NZF GEOMETRY)
HIGH
gm/C,ss
TYPE
I
-10
-1

===

IG
(nA)
-0.1

IG @ ID= 5 mAHI G @ ID= 1 mA=

IG
.. BREAKPOINT" II
~0,

\.j rrlG~

-0.01

-0.001

o

10

5

15

20

25

VDG(V)
Figure 8.

30 V.

Characteristics of
perature

30

Gate Operating Current vs.
Drain-Gate Voltage

Drain-Gate Voltage
In circuit design, particular attention must be paid to
drain-gate voltage (VDG) to minimize gate current
(I G) under operating conditions. The critical draingate voltage (I G breakpoint voltage) can be anywhere from 8 to 40 V. depending on device design.
Gate operating current (I G) should not be considered
equal to gate reverse current (I GSS) in linear amplifier applications. I GSS is only an indication of reversebiased junction leakage under non-operating conditions. The curves shown in Figures 7 and 8 reveal
how the I G breakpoint is related to basic device
design. Device designs with a high gfs /Ciss ratio
have low breakpoint voltages. typically at VDSG =
10V; whereas. high J.l devices (J.l=rds·gfs) have
much higher I G breakpoints. typically VDG = 20-

=

5

f - FREQUENCY (Hz)
Figure 6.

'IE=-

~

1111

1K

T A = 25°C

Gate Current vs. Drain-Gate
Voltage

and in at Low Tem8 K

ent. en and Tn are proportional to VT. and both will
be reduced if the temperature is lowered. In Equation
(16). Tn is proportional to ~ ; I G will halve for
each temperature drop of 10 to 11°C. en is also
proportional to VR N • where R N """ 0.67/ g fs . Thus
when g fs is increased. which is typical of junction
FETs operating at low temperature. en will also become lower.
In Figure 9. g fs has been plotted vs. temperature for
silicon junction FETs. and the low temperature limitation caused by a drop-off in g fs is clearly shown.

ID= 3 mA

2N4416

Three equations presented earlier [ (7). (16) and
(17) 1 show that en and Tn are temperature depend-

h
6 K

~

/,co" ">:- "-

gfs (Jl.mhos)

r-...

4K

2 K

o

o

100

200

'" Ell

300

(OK)

Figure 9.

gfs vs. Temperture

9-37

LPD·5

tcrSiliconix

.,1;;11 incorporated

In connection with the plot of gfs vs. temperature,
note that the relationship can vary from approximately 0.2% to 1% per °C. The gfs slope depends
upon the basic design of the FET and upon the proximity of the drain current operating point to I DZ, the
zero temperature coefficient point.
The major application of junction FETs at low temperature is in charge-sensitive amplifiers. For best
performance in this type of appiication, a high
gfslClss ratio is required. Recommended Siliconix
FET types for such applications are the 2N4416 and
the U310.

Test Measurements
By definition, en and Tn are referred to the input of
the device under test. To measure en , the test circuit shown in Figure 10 will prove useful.
The following procedure should be used to make the
en test:
1.

2.

Set the tunable filter to the required f low and
f high . Adjust the oscillator to the mean center
frequency [ f mean = ( flow e f high ) 1/2 1.
Set VOSC to 100 mV with Switch 1 in position

CD.
ComputerVln1 =10- 1 X

3.

2

~
16 6

=1O-5 V=10 /1V.

MeasureVOUT1. Compute overall gain as
Av = VOUT1
Vln1

VOUT1.
10 /1 V

4.

®

Set Switch 1 to position
and measure VOUT2 .
Compute Vln2 , the equivalent short-circuit input
noise voltage (en), using Av from Step 3.
Vi
VOUT2
In2 =
Av

= en in volts over band-

band f low to f high .
An alternate method of performing the above test
uses a Quan-Tech Transistor Noise Analyzer consisting of a Model 2173 Control Unit and a Model 2181
Filter. The analyzer has provision for measuring en
and determining NF with various values of R G in FET
and bipolar devices with selectable test conditions.
The measuring system has a constant gain of
10,000. The analyzer records output noise at selected frequencies between 10Hz and 100 kHz in the
device under test, with the scale shown as the actual
output divided by 10,000. This is then the output
noise referred to the input. The equivalent bandwidth
for testing is 1 Hz.

There are certain instances where the test circuit or
the Transistor Noise Analyzer are not adequate to
measure en at certain frequencies over certain
bandwidths in the 1ff n region. The RMS noise over a
bandwidth from f low to f high, where there is a 1ff n
characteristic over the entire range, can be computed as

f hi h )] 1/2n
en = [ en known ] • [ fknown -In ( _g_
(18)
flow

+VOD

1 M.o.

MOUNT D.U.T. AND INPUT CIRCUITRY
IN SHIELDED ENCLOSURE
Figure 10.

9-38

Test Circuit to Measure en

.:r-Siliconix

LPD·5

~ incorporated

independently. Equation (21) implies that Tn2 can be
calculated if e T2 and total noise e nl 2 are known. The
difficulty here is that in MOS or junction FETs, the RG
must be very large to detect the anticipated small
value of Tn. However, when RG is very large, eT 2 is
much greater than Tn2 • RG2 . For example, over a
l-Hz bandwidth at 25°C, if RG is equal to 100 Mil,
then

--,
I
I

I
I
I

en
KNOWN

I I
--n-----I I
I I
I I
f row

eT 2 = 4kTRG
= 4 xl. 38 x 10 -23 x 2.95 x 10 2 x 10 8
f known

Figure 11.

= 1.63 x 10 -12 V1.,fHi.

Computing rms Noise Over
a Bandwidth

(22)

Anticipated Tn is
in"'" 10- 15 Amperes/.,fHi

Figure 11 represents this equation graphically. For
example, en known = 70 x 10- 9 VI"fHz at 10 Hz.
How much noise is in the band from 4.5 to 5.5 Hz?
The noise has a llfl characteristic over the entire
range. Thus
en=[70 x

10-9 ]. [10 .1n ( !. ~ )(\Olts
v/.,fHi

@4.975 Hz,

and

Tn 2 = 10- 30

Amperes/.,fHi.

(24)

Thus
Tn 2 • RG2 = 10- 30 .10 16

= 10- 14

(19)

v/.,fHi.

(25)

e/,

or
en= 99.16 xl0- 9

(23)

(20)

4.975 Hz is the mean center frequency where f mean
= (flow 0 fhlgh) 1/2.
Tn measurements are difficult to implement at best.
At frequencies below f2 in Figure 2, Tn is assumed to
have a constant level or "white" noise characteristic
which may be correlated to gate current, I G. From
Equation (16) I G is established as the measured bulk
gate current. Because measured gate current (I G) is
the result of all conductances at the gate, the resulting gate current and the computed Tn due to bulk
material can be assumed to be this value or less.
The total equivalent input noise of the FET can be
approximated by
(21)
where e / is the thermal noise of the generator resistance R G and e ni 2 is the total noise referred to the
input. This approximation assumes that the equivalent noise voltage and the current generators vary

Therefore, Tn2 • R d is much less than
which
renders this method of finding Tn impractical for most
common MOSFETs or junction FETs.
An improved method of measuring Tn2 is to substitute a low-loss mica capacitor for resistor RG . The
mica capacitor by definition does not have equivalent
thermal noise voltage and, thus, Equation (21) becomes
(26)
(where Xc

= capacitive

reactance)

or
in

=

(_

eni

2

-

- en
Xc

2) 1 12

(27)

When a 10-pF mica capacitor was used in the
evauluation circuit (up to a frequency of 100 Hz), a
correlation of from 80 to 90% was obtained when
compared to Tn2 computed from measured gate
current readings. At frequencies above 100 Hz,
direct computation of Tn via the capacitor method
becomes unwieldy because of the rapid decrease in
capacitor reactance at these frequencies.

9-39

~
~

LPD-5

.:F'Siliconix
.LII incorporated
250A Rx meter or equivalent. The 250A Rx meter can
measure Rp accurately up to 200 kil. As is shown in
Figure 12. this establishes the low-frequency limit of
20 MHz for 1n computed via direct measurement of
Rp for the Siliconix FETs 2N4117A. For frequencies
between 100 Hz and 20 MHz, In must be extrapolated, as shown in Figure 12 and 13. For FET types
with lower Rp (such as the Siliconix 2N4393) Tn can
be computed down to 2 MHz, and, hence, extrapolating 1n between 100 Hz and 100 kHz is more accurate.

1000 K
2N4117A
(NT GEOMETRY)

100 K

Vos-10V
Vas = 0 V
TA -25°C

=

1.1

in

Rp

\

10 K

'-

1K

in

in

E~J,~APOLA ~~,D

CAL,?,~LATED

100

10

0.1

10-15
1K

f - FREQUENCY (MHz)

Figure 12.

Low-Frequency Limit for
Calculated in

The curves shown in Figure 14 are representative
curves for Siliconix JFET products. Of particular importance is the geometry which by its design governs the basic noise characteristics of
product types derived from it.

en, In

CONCLUSION

2N4117A
(NT GEOMETRY)

Vas

10 V

10 - loss
T A -25°C

: i~

Contemporary junction FETs have noise voltages
(en) equal to those found in low-noise bipolar transistors. Each type of device has a different operating
mechanism: the FET is voltage-actuated. while the
bipolar transistor is current-actuated. Hence, FETs
have an inherently lower noise current (T n) and are
preferred over bipolar devices in most audio-frequency applications where low-noise performance is
a design requirement.
When bias points are properly selected. as described
in this application note, the excellent low-noise characteristics of high gfs junction FETS can be realized.

0.1 K

1K

10 K

100 K

10-16
1000 K

f - FREQUENCY (Hz)

Figure 13.

Extrapolated i nvs . Frequency

In calculating In at higher frequencies, an alternate
method is to measure (Rp) the real part of the gatesource impedance of the FET. When Rp is measured
at various frequencies, the equivalent short-circuit input noise current (I n) can be computed as a function
of frequency (see Equation (17). A convenient instrument to measure Rp is the Hewlett-Packard Type

9-40

The process geometry of the basic FET design of the
FET governs the noise characteristics of product
types derived from it. Readers are invited to refer to
the Siliconix FET catalog for full geometry performance data and for specific part numbers stemming
from the generic process geometries.
The measurement section of this application note
showed that direct en measurements can readily be
made. Tn can be guaranteed at frequencies below
100 Hz by measuring the dc operating gate current
(I G). When I G is known, 1n can be extrapolated from
frequencies below 100 Hz to predict noise performance at frequencies to 100 kHz.

.rSiliconix

.LII

LPD·5

incorporated

NIP

NCB
1

1K
2N4393
(NCB GEOMETRY)

§

1=

lilll

1111111

100

t:::

en
(nV/VHz)

I II'U

11111111

en @Io= 0.1 lOSS

en

100
en
(nV/VHz)

11\ .::::

100

1K

10

@ 10:::: 0,01 ID~

EIiJ.llll
10

II

0.01 lOSS

10

10-13

Vos= 10 V
10SS= 16 rnA
TA=2SoC

In @ 10= 0.110SS~

Tn @ 10

K .-------,E"'E"'...- __":":"-"III

JJIIiI

10 K

10- 16
100 K
I - FREQUENCY (Hz)

I - FREQUENCY (Hz)

NPA

NRL

-,""'=_....._ ...........'I!I

==......""'1-............'111 10-13

1 K .-.,...,..,.,.,....................

1 K ...._ _ _..........

10-13

10-14

in

en
(nV/VHz)

(A/VHz)

10~1I10-1S
10-16
100 K

~.u..WJ~..J..J.J.LJ.I!'L~..u.~~:-l-u.L~
10 K

I - FREQUENCY (Hz)

10-16
100 K

I - FREQUENCY (Hz)

NT

PSA

en
(nV/VHz)

10

_1....L.......................u,wll-..I..IU-L1WI 10 -16

100

1K

10 K

100 K

I - FREQUENCY (Hz)

Figure 14.

I - FREQUENCY (Hz)

iii

Noise Characteristics by Geometry

9-41

LPD·6

fCrSiliconix

~ incorporated

JFETS FOR VIDEO AMPLIFIERS
INTRODUCTION
The field-effect transistor lends itself well to video
amplifier applications. Gain bandwidth products in excess of 250 MHz may be easily achieved using simple one- or two-transistor circuits. DC input resistances in the tens of MO range may also be easily
achieved while input capacitances may be significantly reduced to less than 1 pF by well-known circuit
techniques. Video amplifiers have applications in
communications and pulse amplifying circuits and
normally operate up to 100 MHz.

For this analysis the gate source leakage resistance
has been ignored due to its high value. Redrawing
the input equivalent circuit as a simple parallel resistance-capacitance combination results in

Behavior of JFET Input Resistance
A prime JFET parameter. input impedance. has a
large effect in determining the frequency response of
a JFET video amplifier. It is not a simple RC network,
but one in which the real and imaginary parts are a
function of frequency.
The voltage generator source resistance RG and the
JFET input impedance Z IN form a frequency sensitive
attenuation network. The larger the RG. the worse will
be the frequency response and vice versa. Examining this in greater detail. consider the input equivalent circuit of a JFET connected in the common
source configuration.

Figure 2.

where

002[T,C,(1 +oo2T22) +T2C2 (1 + oo2T,2)]
1 _(oo 2 T,T2)2+ oo2(T,2+ T22)
and
8,

where

= 1m IVlnl
oo[C, (1 +oo2T22)+C2(1 +oo 2 T,2)]

Rgs and Rgd
C gs andCgd
goss

= bulk series gate resistance
= bulk series gate capacitance
= output conductance

1 _(oo 2 T,T2)2+ oo2(T,2+ T22)

T,

Figure ,.

9-42

(2)

where
T,

goss

(1)

= CgdRgd
= CgsRgs

(3)

The input resistance varies inversely with the square
of the frequency (see Figures 3 and 4). while the input reactance is inversely proportional to the frequency (see Figure 3).
in common-source circuits. I/G, will typical fall
to < 2 kO at 100 MHz while C, remains substantially
constant at least up to 1000 MHz. Figures 3 and 4
exhibit these relationships.

H

Siliconix

LPD-6

incorporated

To maintain low input capacitance and, thus, a high
input impedance over a wide frequency range, feedback may be applied to most circuits. Such techniques are explored in "JFET and Bipolar Cascade"
section of this application note. The effect of RG on
the frequency response is shown in Figures 6, 9, 11,
and 13 where various amplifier configurations are investigated .

100

-

I-

10

-

Ylss

i = b lss

(mU)

....

./

./
Circuits to Consider

f----- gls,:/"

/"

0.1
100

The following five video amplifier circuits are considered.

YlSj = gliss I" J~ly
1000

FREQUENCY (MHz)
Figure 3

1\
15

-\
\

C IN

(pF) 10

80

60

~

C1N

r\.

,

5

RIN

(K.(1)

Shunt-Peaked Common-Source Configuration

3.

Source Follower

4
5.

Cascode Amplifier

RD

.....

-

~ "'1-

a
10

FREQUENCY (MHz)

JFET and Bipolar Cascade

The circuit shown in Figure 5 features high input impedance and high voltage gain. The drain resistor is
set at 560 n to maintain good bandwidth which, with
50-n generator impedance, is determined primarily
by the drain load components. These are:

40

~N
1

Common-Source Configuration

Common-Source Circuit

100

20

1.
2

= 560n

(4)

20

(5)

a
100

Cgd = 2.0 pF, CD the VTVM probe, 2.0 pF,
and Cs is circuit stray capacitance of 3 pF.

a.

CT

15 V

= 2

+2+3

= 7 pF

(6)

The 3-dB frequency W3 is given by

J300

W3 - - - -

CTRD

0---.,.---'01--, (1/22N5911112)

(7)

100 K .(1

7 x 1.0- 12 X 560

(8)

(9)
b.
Figure 4

f3

= 39

MHz

(10)

9-43

~Siliconix

LPD·6

~ incorporated

Measured Performance

15 V

Figure 6 shows the frequency response of the circuit.
The low-frequency gain was measured at 4.5 and the
3-d8 bandwidth at 44 MHz giving a gain bandwidth
product of 197 MHz. This compares with a calculated
gain bandwidth of 191 MHz.

RD
560.n.

f

I
I
I
-.L
"T' 2.5 of

Rs

!

47.n.

I

Effect of Increasing Generator Impedance
If the generator resistance RG is increased to 1 k n,
the input time constant of the JFET is increased. The
bandwidth of the amplifier is now determined primarily by the input time constant which consists of generator impedance (RG = 1 k 0) shunted by Cln (see
Figure 7).

-.L

Figure 5

The low frequency voltage gain for this configuration
is given by:
gfsRO
1 + gfsRs

AV

AV

(11 )

= 4.9

L

(12)

where
gfs = 15 mU
10

= 12 mA,

when

Figure 7

the quiescent current
where

RO

560n

(13)

RO

47 n

(14)

14

IlIlIi"'ol
111111 I

-

.......

'\

Rg = 1 K.n.

ilill

1111

IIIII

111111

Rg =50 .n.

8

1\

4

o

~

(16)

Cgd

3.5 pF

(17)

C gs

10 pF

(18)

o

10

The corresponding 3-d8 frequency is given by:

\

1\

2

100

(19)
109

= 30

1000

FREQUENCY (MHz)

9-44

=

x 10_12 x 10 3

30

(20)

(21)
5.3 MHz
which agrees closely with the measured bandwidth
shown in Figure 6.

f3
Figure 6

(15)

where

(dB)

6

(5.9 x 3.5) + (0.6 x 10) + 3.
30 pF

111111 I

12
10

=

~Siliconix
incorporated

LPD·6

.LII

Shunt-Peaked Common-Source Circuit

fo

=

1
2

(22)

-rrV LCin

RD2 C

L

The frequency response of the resistance-loaded
common-source circuit may be significantly extended
by shunt peaking at the gate and/or drain. First, consider the gate circuit. Here an inductor may be
connected in shunt with the gate and set to such a
value that it forms a tuned circuit with the JFET input
capacitance. The frequency of resonance is determined by

and for the cicuit in Figure 8.

(24)

2
(25)

0.78 J.1H
where
RD

= 560n

C

= Cgd +

C

= 1.2 + 1.3 + 2.5 = 5 PF

(26)
CStray

+

(27)

CYTYM PROBE

(28)

where
Cln = Ciss

(23)

+ CStray + CMiller

The response of an input signal of frequency f 0 will
then be boosted to an extent depending on the
loaded Q of the tuned circuit; the loaded Q, in turn is
dependent on the unloaded Q of inductor L, RG, and
the JFET input resistance.
Next, consider shunt peaking in the drain circuit. In
Figure 8 the inductor L is set to such a value that a
low Q tuned circuit is formed; the resonating capacitance C is the parallel combination of C gd plus stray
and load capacitances. For a flat response, the LC
circuit is tuned to the 3-dB frequency of the resistance loaded circuit of Figure 5. (See Appendix.)

Due to the low circuit Q (about 5), the value of L is
not critical.
The 3-dB bandwidth shown in Figure 9 now extends to
67 MHz, giving a gain bandwidth product of
67 X 4.2

(29)

When Rs is bypassed by a 0.1 J.1F capacitor, the lowfrequency voltage gain is given simply by
Ay = gfsRD

L
0.78JlHy

(30)

15 x 10 -3 x 560

(31)

8.4 (18.5 dB)

(32)

28

I
I
I

--.L
"1"'
I

I
I
--..L
Figure 8

MHz

The gain bandwidth product tends to remain constant
whether Rs is bypassed or not, and this effect is
shown in Figure 9.

15 Y

Rs
47!1

= 281

24

11111111
s6J~blkll

20

RESISTOR
BYPASSED

16

SOURCE """'"
RESISTOR
UNBYPASSED

(dB)

12

llllllll

2.5 pF

8

1111 II I
I~g= 156

ii

1·1111111

o

III11111

o

J

..

V;<

Rg = 1 k!1

4

-,I
I'
10

100

1000

FREQUENCY (MHz)
Figure 9

The required value of L is

9-45

LPD-6

~SilicDnix

~ incDrpDrated

Source-Follower Circuit
A J300 is used in the JFET source-follower circuit Figure 10, because of its low input capacitance and high
gfs, which remains high at the frequency range of
interest. A source follower exhibits a high input impedance and low output impedance. The real part of
the output impedance is the reciprocal of gfs which is
independent of frequency UP to about 600 MHz. The
input capacitance is C gd + C gs (1 - Av) which, in this
case, is approximately 1.5 pF maximum. The input
capacitance is also independent of frequency and independent of load when the load is larger than the
output resistance Ro.

12 V

Thus, Av is almost independent of Rs when Rs is
large. Using typical values for the J300 (or 1/2
2N5912) in Figure 10, the drain current is 3 mA, gfs
is 5 mS and Rs is 4700 .0.
Av = 0.96
which is near the measured value of 0.94. Measured
performance is shown in Figure 11 . The output resistance of this source follower is given by

1
Ro= - gfs

200 .0

and in this circuit, Ro was measured at 165 .0. The
source follower is a useful versatile circuit which may
be used as an impedance converter, level shifter,
buffer stage, or as an input circuit to an op amp or
feedback amplifier.
14

I
I

12

Rs
*2.5PF
4700
I

10

Voltage
Gain
(dB)

I

-

-L
_ 12 V

-

IIII U

Rg = 1 k!l.

\

6

I-

2 I-0

The frequency response is dependent mainly on the
generator internal impedance. For example, when
Rg is Increased to 1kn the bandwidth falls to 80
MHz. In this particular circuit, the low-frequency voltage gain is 0.94.
The input resistance is proportional to llf 2 (as explained in the section, "Behavior of JFET Input Resistance) and at some high frequency will go negative,
particularly if the source resistor is large. For example, with the circuit shown in Figure 10, the input resistance is high at 10 MHz but in the negative resistance region at 100 MHz. However, when Rs is
1000 .0, the input resistance .is real at this frequency.
The voltage gain of a source follower is given by
_

9-46

3 dB FREQUENCY
Rg = 1 k.o. 3 dB FREQUENCY
R = 50.0.
111111 gl I 1111111

o

I

11111111

10

100

1000

FREQUENCY (MHz)

Figure 11

Cascode Circuit
The casco de circuit has applications as a buffer amplifier for use with high-stability oscillators or in lowlevel power amplifiers 2 mainly due to its low reverse
transfer characteristics .. The advantages and considerations of this configuration (Figure 12) are similar
to those listed for the common-source circuit. An extra advantage exists in the cascode circuit, namely
the low input capacitance:
Cln

(33)

I II

Rg = 50.0.

6

4

= 1_+g..."f.::.sR....;S,,-gfsRS

1111111

......

Figure 10

Av

(34)

= C gs +

(1 - AV) Cdg

(35)
(36)

~Siliconix
.L;II incorporated

LPD-6

where Av is the voltage gain from Q 1 gate to Q 1
drain,which is essentially unity. Clss for the 2N5912
dual JFET is 5 pF, and Cgd is 1 pF; therefore,
Cln= 5 + 1 = 6 pF, excluding strays of 4 pF
Thus, Miller effect is minimized, and a good gain
bandwidth product is achieved.

10 k.n.

Figure 13 shows cascode frequency response. The
voltage gain at low frequency is 15 dB (x 5.6), and
the bandwidth is 24.5 MHz with a generator impedance of 50 n. The gain bandwidth product is
137 MHz.

JFET and Bipolar Cascade
The JFET and bipolar transistor combination shown in
Figure 14 makes a good video amplifier because the
JFET input provides the voltage gain, thus obtaining
a superior gain bandwidth product. The feedback
capacitor ac couples the emitter to the drain. The
acvoltage at the gate is nearly equal to that at the
source. This source voltage is dc coupled to the
base. This produces an A/C voltage at the emitter,
whose amplitude is almost equal to that at the base.
Thus, at the JFET, V g ~ V s ~ V d , and all three signals are in phase. In this way, Miller effect capacitance is largely eliminated.
The frequency response of this circuit is controlled
by the output time constant if f t of the transistor is
much greater than the amplifier bandwidth. In the circuit shown the A/C load is 2.5 pF.

0.1
12 V

1k.n.
Figure 12

28
24

20
Voltage
Gain 16
(dB)
12

SOURCE
RESISTOR
BYPASSED
RESISTOR
UNBYPASSED

4 I-

~ llll!l~ k.n.1
I 111111

IzI

K

SOIU~CIEI III

8

aa

R g = 50.n.

~

~~
\

I
100

FREQUENCY (MHz)

Figure 13

1000

LPD·6

~SilicDnix

~ incorporated

CONCLUSION

14

The input resistance of a JFET is inversely proportional to the frequency squared, while the input
capacitance remains constant to at least 1000 MHz.

I~I= l.UJ
1'1

12

.......,.".1

10
Voltage
Gain
(dB)

Several video amplifier configurations are considered. The common-source circuit is considered first.
In the example, the low frequency gain is 4.5
and the 30-dB bandwidth is 44 MHz (gain bandwidth
= 197 MHz). By shunt peaking in the drain circuit,
gain bandwidth is increased to 260 MHz. The simple
source-follower circuit gives a gain near unity with
gain bandwidth almost 300 MHz and an output resistance of 1/Q f8' The cascode circuit features a low
input capacitance and gain bandwidth of 137 MHz.
The circuit featuring the best gain bandwidth is the
JFET and bipolar combination, where gain of 11 dB
and bandwidth of 90 MHz is achieved.

LI=~

8
6
4
2
00

100

1000

FREQUENCY (MHz)

Figure 15

APPENDIX
Selection of Video Amplifier Designs with Performance Summary
Note: All output voltages measured with Boonton 91C VTVM.

Table 1

COMMON SOURCE STAGE
DEVICE
2N4393

(~) Byp~~8ed (~) (~)GAIN

dB

C 1n
BW GBW
( pF) (MHz) (MHz)

50
50
1k
1k

44
40
5.0
3.5

197
300
22
26

50
1/2
50
2N5912 1 k
1k

X
X

J300

2N4416

9-48

50
50
1k
1k

X
X
X
X

47
47
47
47

560
560
560
560

4.5
7.5
4.5
7.5

13.0
17.5
13.0
17.5

91
91
91
91

1
1
1
1

K
K
K
K

3.8
6.3
3.8
6.3

11.6
16.0
11.6
16.0

11.0
14.5
11.0
14.5

27.5
30.0
9.5
6.5

103
189
36
41

120
120
120
120

1.5
1.5
1.5
1.5

K

3.9
6.2
3.9
6.2

11.8
15.8
11.8
15.8

11.5
13
11.5
13

25
19
8
7

98
118
31
44

K
K
K

15 V

Ro

Rs

I

2 . 5PF

.-r'Siliconix

LPD-6

~ incorporated

COMMON-SOURCE CIRCUIT
CASCODE

1 k.O.

U257
OR
2N5912

1

2.5 pF

180.0.

-15 V

Rg
Rs
Gain
(.0.) Bypassed

dB

C 1n
BW GBW
(pF) (MHz) (MHz)

(~)

50
50
1k
1k

8.5
15
8.5
15

9
11.5
9
11.5

50
1k
50
1k

2.7
5.6
2.7
5.6

X
X

27
27
9.5
9.0

R

73
151
73
51

L
GBW
Cln
BW
(p.H) Gain dB (pF) (MHz) (MHz)
0
0
8
15

3.5
3.5
3.5
3.5

11
11
11
11

2
2
2
2

20
11
37
17

70
38.5
130
60

SHUNT-PEAKED COMMON-SOURCE STAGE
J300

2N4393

(1/22N5911/12)

l)J.Hy

2.8)J.Hy

560.0.

1 k.o.

I

47.0.

2. 5PF

91.0.

-

Rg
Rs
Gain
(.0.) Bypassed
50
50
1k
1k

X
X

4.2
7.5
4.2
7.5

I''''

BW
GBW
dB
(MHz) (MHz)
12.5
17.5
12.5
17.5

66
54
6.0
3.5

277
405
25
26

Rg
(.0.)
50
50

Rs
Bypassed
X

Gain

dB

BW
(MHz)

GBW
(MHz)

3.9
6.3

11.8
16.0

67
67

262
421

9-49

III

LPD-6

~Siliconix

~ incorporated
SHUNT-PEAKED COMMON-SOURCES STAGE (Cont'd.)

2N4416

L

Rg
L
Rs
(.0.) (jIH) Bypassed

Gain

BW GBW
dB (MHz) (MHz)

50

4

3.9

11.8

45

175

50

4

X

6.2

15.8

40

248

50

5

X

6.2

15.8

45

279

1500.0.

1

!

2.5 pF

120.0.

COMMON-DRAIN COMMON-EMITTER STAGE

15 V

1 k.O.

1 k.O.

0.01
MPS

MPS

6543

RE
180.0.

R
9

(.0.)
50
50
1k
1k

9-50

6543

1'"

180.0.

-

Rs
Bypassed Gain
(0.1 J1F)
X
X

3
25
3
25

dB
9.5
28
9.5
28

C 1n BW
(pF) (MHz)
2.0
2.0
2.0
2.0

39
21
13
11

-

-

GBW
(MHz)
117
525
39
275

1'"

~g

G I
an

dB

50

5.6
5.6

15
15

(.{},)

1k

C 1n
BW
GBW
(pF) (MHz) (MHz)
1.0
1.0

32
15

179
84

..:r'Siliconix

LPD·6

~ incorporated
SOURCE-FOLLOWER CIRCUIT

15 V
15 V

180 .{1

r - - -....----,

J300

1

2.5 pF

180 .{1

-15 V

Rg

Total Ro
(.{1) Gain (Stray pF) (pF) (.{1)

BW
GBW
(MHz) (MHz)

Cln

50

0.92

2.2

2.7

165

350

326

1k

0.92

2.2

2.7

165

55

50

Dual
FET

Derivation of Input Admittance Terms

Cl = C gs

S = jw

BW GBW
(MHz) (MHz)

(mV)

U257
2N5912

50
1k

100
100

0.98
0.98

70
15

69
14.7

U232

50
1k

10
10

0.98
0.98

85
13

8.3
12.7

Yin IRl

T Cl

RL2+w 2 L2

z=[
(1 _

SCl
Yin = R1 C 1 S + 1 +

Gain

( .{1)

The equivalent circuit of the drain load is shown in the
Figure below. The total impedance seen by the drain
is given by:

(1)

R2= Rgd C2= Cgd (2)

Offset (Max)
(Input to Output)

Derivation of Shunt Peaking Formula

where
Rl = Rgs

Rg

SC2
R2 C 2 S + 1

_w 2 Cl C2 (Rl+ R2) + S (Cl +C2)

]112

(5)

w2 LC) 2 + w 2 C 2 RL2

(3)

(4)

C

(1 -w2R1R2C1C2) +S(C1Rl+C2R2)

9-51

ICrSiliconix

LPD-6

~ incorporated

The response below shows the .. normal" 3-dB frequency without peaking -f1. It is now required to raise
the response at f1 by 3-dB to achieve a maximally flat
response. Therefore, under these conditions the total impedance seen by the drain at f1 must equal the
impedance seen by the drain at fo. Also, at f1 , Xc =
RL. Substituting for Xc in Equation 5:

(7)
(8)

=2 w L

RL

(9)

RL

L=-4'IT f1

(10)

and

(6)

f1

= __1_
2'IT RLe

9-52

, therefore,

(11 )

~Siliconix

LPD-7

~ incorporatec

DESIGNING JUNCTION FET
INPUT OP AMPS
INTRODUCTION
Junction FET input operational amplifiers generally
consist of a discrete FET differential preamplifier followed by a monolithic bipolar operational amplifier.
FET input op amps have a number of advantages
over op amps with bipolar transistor input stages.
Most of these advantages are attributable to the low
input and offset current characteristics of JFET pairs,
which are typically three to five orders of magnitude
lower than those of bipolar op amps. This is presented graphically in Figure 1.

1000 K
100 K

r--.

J,1A7l10Rk70J-

r--

LM201

circuits are a common-drain or differential source
follower (Figure 2) and a common-source or long
tailed pair differential amplifier (Figure 3).

VccO-~--------,

+

10 K
1 K

Voo

voo

.;t'

(pA)
100

V

LM2&a

10
U,401-4

Y

0.1
-50 -25

0

./

V

Figure 2.

V

. / U421-423_

V
25

Common-Drain or Differential Source
Follower

Vcco---~-------.

50

75

100

125

Ro

T(OC)

Figure 1.

Comparison of Input Bias Currents In
Dual FET and Bipolar Op Amps

In integrator circuits, the low offset current of junction
FET input op amps permit the integrator charge to be
held more than 1000 times longer at 25°C than is
possible with a typical bipolar input op amp. FET input op amps also payoff in high impedance amplifier
circuits where their low offset current results in low
(loffsetl x (Rgeneratorl error voltage.

+

..

Behavior of JFET Preamplifiers
FET input op amps usually include a preamplifier
constructed of a matched FET pair and a monolithic
bipolar op amp. Two configurations of the preamplifier circuit are shown in Figures 2 and 3. These

Voo

Figure 3.

Common-Source Differential Amplifier

9-53

LPD·7

wrSiliconix
.LII incorporated

The differential common drain (or "source follower")
circuit has a differential voltage gain
Adlff

=

RS

(1 )

1 + RS (9fs+ gOS)

Adlff never exceeds unity for the common drain circuit. and only approaches unity for high values of Rs
and light loading.

The differential output impedance is twice that of the
single-ended output impedance. or

Zout(dlff)

=

Rs + gosRs2

2 [

]

(2)

1 + Rs (gfs+gos)

Neglecting the output conductance. g os. and assuming Rs is very large. one can arrive at the useful approximation that
Zout(dlff)

2

R$

(3)

gfs

The common-source (or "long-tailed pair") differential amplifier has a differential voltage gain of.

Adlff

=

- gfsRD

(4)

1 + gos (RD+ Rs) + gfs Rs

A useful approximation for the case where Rs =a can
be arrived at if. again. g os is neglected. In that instance.
Adiff

R$

-

(5)

gfsRD

Note that there is a phase inversion between the gate
and the drain. and that the value of the commonmode resistor. ReM. does not affect the gain.
The differential output impedance is

2 RD
goS(RD+RS)

Zout(dlff)

(6)

-----"-----"-+ 1
1 + gfsRs

If RD«

Zout(dlff)

9-54

1
- - and if Rs
gos

R$

2 RD

= O.

then

(7)

In the common-source differential amplifier. the addition of Rs lowers the gain and raises the output
impedance. Lower gain and higher output impedance will tend to degrade the offset. drift and noise
of the FET input amplifier. For this reason it not
generally advisable to use source resistors in
common-source FET preamplifiers. The use of a
source resistor does tend to stabilize the gain of a
FET pre-amplifier over the temperature range of the
device. but stable open loop gain is not generally of
great importance in an op amp.
At low frequencies. input impedance is not a very
useful concept for a FET amplifier. It is far more realistic to consider that there is a very small current
source. typically ranging from 0.01 to 1000 pA in the
gate lead. The value of this current source is
dependent on a number of factors. This aspect of op
amp applications will be covered in a subsequent
section of this Application Note. In general neither
the common-drain circuit or the common-source
circuit enjoys any particular advantage over the other
in terms of input current.
As general rule. a common-source FET preamplifier
will produce better results in a FET input op amp than
will a common-drain preamplifier. There are three
reasons for this superior performance. A common
source preamplifier tends to mask the drift and offset
of the second stage because of its voltage gain. By
the same mechanism. the noise of the second stage
is diminished. The third advantage of the commonsource preamplifier is that is removes commonmode variations from the input of the second stage.
These points will all be considered in more detail in
later sections of this Application Note.

Offset and Drift
The offset of a FET pair is the difference in gate-tosource voltage between the two devices when measured at the operating current. Drift is the change of
offset with temperature. As is the case with any dc
amplifier. the offset and drift of the input devices are
indistinguishable from the input signal. Thus offset
and drift are erroneous signals. and must be minimized until their magnitude is small in comparison to
the input signal.
In a FET input op amp the input FET pair and the second stage both contribute to offset and drift. Figure
4 shows an equivalent circuit for a common-drain
FET input op amp. including the sources of offset.

.rSiliconix

LPD-7

~ incorporated
VccO-~---------------,

S,

RS

Rs

Voo
Figure 4.

Voo

Offset Equivalent Circuit for FET Input Op Amp with Common-Drain Preamplifier

If

Eosl Al A2 + 10sRT A2 + Eos2 A2
Z OUT of the FET preamp in parallel with
Z IN of the second stage,

Eosl

Voltage offset of the FET pair,

Eos2

Voltage offset of the second stage,

lOS

Current offset of the second stage.

(9)

A1A2
or
(10)

Allowing the simplifications ZIN » ZOUT, gos = 0,
Al, = 1, and Z OUT = 2/9 fs, one can obtain an equation for the total offset referred to the input of a FET
op amp, using a common-drain preamplifier:

Voltage gain of the FET preamplfier,
Open-loop voltage gain of the second
stage,

2 los
ETin"" Eosl + - + Eos2
gfs

Total offset error at output of second
stage,
Total offset from all sources referred to
the input, and
gfs

(11)

If both sides of Equation (11) are divided by aT, and
equation is derived for total drift referred to the input:

Forward transconductance of the FET at
the operating current,

then
(8)

and

Thus the total drift referred to the input of a FET input
op amp with a common drain preamp is approximately the sum of the voltage drift of the FET pair
plus the voltage drift of the second stage.

9-55

.HSiliconix
incorporated

LPD-7
VCCO-~---------------,

0,

~

__________- - J

S,

RCM
Voo

Figure 5.

Offset Equivalent Circuit for FET Input Op Amp with Common-Source Preamplifier

Figure 5 shows the offset equivalent circuit for a FET
input op amp with a common-source FET
preamplfier.
As is the case of the common-drain preamplifier.
Equation (10) applies. If it is assumed that Z IN »
ZOUT. ZOUT = 2 RD. gos = O. and Al =gfsRO. where
Ro is the drain resistance and Rs is the source resistance. then one can derive an equation for the total
offset referred to the input for an op amp with a common source FET preamp.
Eos2
2 los
ETln ,..,. Eosl + - - + - - gfs
gfsRo

g fs

~ TJ

g fsR 0

~T )

~T.

then

(14)

Thus a FET input op amp with a common-source preamplifier has a total drift referred to the input of the
drift of the FET pair. plus the current-related voltage
drift and the voltage drift of the second stage divided
by the gain of the preamplifier. Note that for lowest
offset and drift. the gain of the preamplifier should
be as large as possible. For high gain. the drain resistors should be as large as possible. consistent

9-56

Methods of nulling offset in the FET input op amp will
depend on the configuration of the FET preamplifier
in the circuit. Two common methods of nulling offset
in common-drain FET preamplifiers are shown in Figure 6A and 6B.
VccO-~--------~

ETln,..,.(Eos~+2(IOS'+_1_(E~S2'

t ~ TJ

Offset Nulling

(13)

If both sides of equation (13) are divided by

~T

with other design criteria (See FET biasing. a later
section of this Application Note). When equations
(12)-(14) and (11)-(13) are compared. it is apparent
that the common-source FET preamplifier always will
produce lower overall offset and drift.

1

Voo

Figure SA. Nulling a Common-Drain Preamp with
Source Resistor Biasing

~Siliconix

LPD·7

~ incorporated

By changing the drain current in the FET, one can
change the gate-to-source voltage and thus change
the offset. In a junction FET

used in Equation (20). Also, there will inevitably be
small differences in the values of the the two source
resistors due to their tolerance; the value of R N must
be increased to correct for these differences.

(15)

In the circuit in Figure 6B, the offset is nulled by varying the difference between el and e2. The value of
the fixed resistor, R, is

In a source-follower configuration where VGG - VDD »
VGS(off),
I D~ VGG- VDD
Rs

(16)

If Equation (16) is substituted into Equation (15):

ETln
R=-IBIAS

(21)

The value of the potentiometer then is 2R. The value
of ETin in Equation (21) is the value found in Equation (11),
VccO-~----,

VGS

~VGS(off) - [VGS(Off)2

1/2

(VGG- VDD) Rs- 1 ]
IDSS

(17)

If VGS is differentiated with respect to Rs, one can
derive a value of IlVGsl IlR S for small changes in RS :
dVGS
dRs

~ IlVGS ~[VGS(Off)2
IlRs

(VGG- VDD)]
41 DSS RS3

112

(18)

Thus in a single-source follower, to correct for an offset ETln , the value of Il R S should be

ISlAS

ISlAS

Voo

Voo

(19)
Figure 68.

In the circuit in Figure 6A, where the resistor is a potentiometer in both legs of the differential source follower, the effect of any resistance change is double
that of Equation (19). Hence the value of the null
potentiometer R N to correct for an expected maximum offset of ETln is
ETln

RN~--~

Nulling a Common-Drain Preamp with
Constant Current Biasing

plus any offset caused by unbalance in the current
sources. The voltage offset caused by current unbalance in the current sources can be calculated
from Equation (15).
In a common-source FET preamplifier, offset can be
nulled by either of two techniques. One method is to
insert a potentiometer in the source Circuit, as is
shown in Figure 7A.

(20)

IlVGS
IlRs
For any type of junction FET, there will be a range of
VGS (off) and I DSS values. For a conservative value of
RN, minimum values ofVGS(off) and IDSS should be

In the circuit in Figure 7A, the offset is nulled by the
difference in ICM R1/2 -ICM R2/2. The value of the
potentiometer should be
(22)

9-57

LPD-7

~Siliconix
incorpora.ted

.LII

where ETln is the worst-case value calculated in
Equation (13). Before the source nulling method is
used, the value of RN calculated in Equation (22)
should be checked against Equations (4) and (6) to
confirm that it has no significant effect on gain and
output impedance.

The second method of accomplishing offset null is a
common-source FET differential amplifier is know as
drain nulling, and an equivalent circuit is shown in
Figure 7B. The basic principle of drain nulling is the
same as that employed in source nulling except that
the offset which is to be nulled is multiplied by the
gain of the stage. Hence, for drain nulling:

VeeO~~--------,

(23)

RD

RD

+

Figure 7A. Source Nulling In Common-Source
FET Differential Amplifier

Noise
During design of a FET input operational amplifier, it
is useful to be able to predict the total noise of the
amplifier referred to the input. The total noise output
is then equal to the total noise referred to the input,
multiplied by the voltage gain of the amplifier. In a
FET amplifier, the total noise can be broken down to
three specific sources, for ease of mathematical
analysis.

Vee

!
RD

Offset nulling is a relatively simple technique which
consists of adjusting an offset potentiometer for zero
output with zero input. The technique to compensate
for drift, however, is more complex and time consuming. The method is based upon the fact that the
temperature coefficient ofVGS is dependent on drain
current. Thus by varying the ratio of the drain current in the two FETs, the drift can be compensated.
The technique is of limited practical value, however,
because of the lengthy oven testing required. For
this reason, drift compensation will not be discussed
in depth in this Application Note.

RD

+

The first noise source is the thermal noise of the generator, which is caused by random electron movement in the generator resistance. Thermal noise is
often referred to as "white" noise, since its spectral
density is constant for all frequencies. The power
spectral density of thermal noise is
St

VDD
Figure 78.

9-58

Drain Nulling In Common-Source
FET Differential Amplifier

= 4kTRG

(24)

where St is the power spectral density of the thermal
noise in the generator resistance in V2 /Hz, T is the
temperature in degrees Kelvin, RG is the generator
resistance, in ohms, and k is Boltzmann's constant
to 1.38 x 10-23 Joules/oKelvin.

g

Siliconix

LPD·7

incorporated

The total noise over a bandwidth f b - f a is
(25)

where let! is the magnitude of the thermal noise
stemming from the generator resistance is rms volts.
and f b - f a is the bandwidth in Hz.
The second significant source of noise is the equivalent short circuit input noise voltage of the FET. This
noise voltage. referred to as en • is caused by a
number of phenomena within the channel of the FET.
and is not constant with frequency; it is made up of
two noise components. One of these is white noise.
with a spectral density that is constant with frequency. The second is "1 over f" noise. so termed
because its power spectral density varies inversely
with frequency. 1/f noise usually becomes dominant
below a frequency between 100 and 1000 Hz. The
power spectral density of en is the sum of the power
spectral densities of the white noise and the 1/f noise
components. thus

10

100

1K

10 K

100 K

FREQUENCY (Hz)
Figure 8.

Equivalent Short Circuit Input Noise
Power Spectral Density vs. Frequency

Then

(27)

(26)

and
where 8 e is the total power spectral density of en in
V2 /Hz. 8w is the power spectral density of the white
noise generated in the FET channel in V2/Hz. and 8f
is the power spectral density of the 1/f noise in the
FET channel in V2/Hz.

To find the total rms noise voltage over a given
bandwidth. 8 e (f) must be integrated over the frequency range of
interest. and its square root
obtained. To accomplish this. it is necessary to
define an analytical expression for 8 e (f). This can be
done if two values of 8 e (f) are known. Usually 8 e (f)
is not given on FET data sheets. however en is
usually given and en is the square root of 8 e (f) .
One value of 8 e (f) must lie in the 1/f region. and is
referred to as 18 ell at fl. and the other (which must
lie out of the 1/f region). and is referred to as 18 e21.
A typical graph carrying these values is shown in
Figure 8. Note that Figure 8 is a graph of power
spectral density. not en.

where lenTI is the total rms noise voltage attributable
to the short circuit input noise of the FET.
Then.
lenTI

It should be noted that if fa is chosen to be zero Hz in
Equation (29). the total noise. lenTI. will be infinite.
In reality. as the period of the noise becomes greater
than several seconds. it begins to resemble drift
rather than noise. With this rationale in mind. it is
wise to choose a non-zero frequency for fa. such as
0.1 Hz. Such a frequency selection will provide reasonably accurate data. and will allow comparison
between various device types and amplifier circuits.

9-59

.r-Siliconix

LPD·7

~ incorporated

The third source of noise is current noise, usually
referred to as Tn. Noise current has a flat spectral
density up to the region of 10 to 100 kHz. Beyond
this point, the spectralrdensity increases because of
noise which feeds through the drain-gate capacitance to the gate. Feed through noise above
100 kHz is known as "shot noise", and will not be
dealt with in this Application Note.
The power spectral density of noise current is expressed in the white noise region as
Isd

= 2qlG

(30)

where I en I is the magnitude of the total op amp
noise from all sources referred to the input in rms
volts, IT n21 is the magnitude of the input noise current of the second stage in rms amperes, and l"en21
is the magnitude of the input voltage noise of the
second stage in rms volts.
Since the spectra! densities of i n2 'and en2 are functions of frequency, the ITn21 and l"e n2 1 must be determined in a manner similar to that of Equation (29).
That is

where I SII is the power spectral density of the current noise in A 2 /Hz, q is the charge of an electron,
1.6 x 10- 19 coulombs, and I G is the gate current in
amperes. Thus the total input current-caused noise
referred to the input of the amplifier is

where Is e1 1. ISe21, f1 ,fa and fb are as previously
defined, except that they now refer to the noise voltage of the second stage. Also,

(31)

When using Equation (30) it is important to choose a
value for I G which corresponds to the actual operating conditions of the FET. I G will vary over several
decades, depending on temperature, VDG and I D.
The total input FET noise of a single-ended amplifier
is the vector sum of the three components

I
-V-2 2 _2
IeT =
et + enT + eiT

(32)

Since the differential amplifier contains two devices,
the noise from both FETs must be accounted for:

where IS i1 I is a point on the curve of input current
power spectral density vs frequency in the 1 If region,
and Is i2 I is a point totally out of the 1If region.
In the case of a FET input op amp with a commonsource FET preamplifier, the total op amp noise referred to the input is

lenl""

V/

1 -eTdiff

12

n21)2(37)
~2ITn21)2+ t2Ie
---

+ --gls

9fsRD

(33)

The foregoing analysis covers only the noise in the
FET pre-amplifier. It does not include the noise contribution of the second stage. As in the case of offset and drift, the noise contribution of the second
stage can be referred back to the input of the op
amp. For a common-drain preamplifier, the total
noise referred to the input of the op amp is
12
V eTdil1 12 + ~2ITnl)2
- - - + 1e n2
gls

lenl"" ./

9-60

1

_

(34)

As was the case for offset and drift, the common
source FET preamplifier will always product lower
equivalent input noise for the total op amp than will
the FET common-drain preamplifier.
In any discussion of noise the term "noise figure" is
bound to arise. Noise figure is the ratio of added
noise power to the thermal noise power of the generator resistance. In a FET preamplifier

(38)

g

Siliconix

LPD-7

incorporated

For any device there is one value of generator impedance for which the noise figure is optimum
lenl
Ropt

(39)

= IT nl

Noise figure is a useful concept in RF circuits where,
by various matching techniques, the generator resistance can be adjusted for Ropt so that the required
noise figure is achieved. Most FET input op amps,
however, are used in dc-coupled applications, and
there is seldom any choice for the designer concerning generator resistance. For this reason, noise
figure is not a very useful concept in FET input op
amps. A much more useful figure of merit is simply

-V 1 e n21+ 1 in21 RG2 ,

which is added noise voltage
referred to the input of the device.

The I G breakpoint results from carriers in the channel
being accelerated by the applied field to such a degree that they are capable of generating hole-electron pairs upon collision with a silicon atom. This
phenomenon is similar to normal junction breakdown,
but occurs at a lower voltage than BVGSS. This is
because, under operating conditions, there are more
carriers available in the channel for collisions.
Operation at higher drain current will result in lower I G
breakpoints for the same reasons.
At low drain-to-gate voltages the leakage current
doubles for approximately every 1DoC increase in
temperature. However, I G breakpoints occur at a
higher voltage for increasing temperature. This is
consistent with normal breakdown voltage behavior
for diodes above 6 V, where the avalanche effect
dominates.

Input and Offset Current
The gate of a JFET forms a reverse-biased junction
with the channel. For this reason, the input current of
a junction FET is the leakage current through the reverse-biased gate-to-source and gate to drain junctions. In normal operation the drain-to-gate voltage
is much higher than the source-to-gate voltage; thus
it is the drain-to-gate junction which is responsible for
most of the leakage current.
N-Channel junction FETs experience an I G "breakpoint" where the gate current rises rapidly with
increasing drain-to-gate voltage. This is shown in the
plot of gate current vs drain-to-gate voltage in
Figure (9).

Figure 10 shows that for some voltages, IG at 125°C
is actually lower than IG at room temperature!

100 K

10

I

K

FIGAT 10 -1 rnA
f=TA 125°C
IG(pA)

.... 1--

1K

100

I
I

r-IGAT 10

10

I

100

VGO(V)

Figure 10.

II

IG
10-10
IGss(A)

I

UJ.H1"

10

IG ATl o-lrnA

I

~IGAT 10 -1 rnA
=T
25°C
-IAI IIII

Gate Current vs Draln-to-Gate Voltage
at 25°C and 125°C.

100.llA ~

17
",

~

"'"

IGss==

==--

10

20

30

40

50

In a dual FET, the difference between the I G of each
device is known as I G offset. A good rule of thumb
for design analysis is

VOG (V)
Figure 9.

Gate Current vs. Drain-to-Gate Voltage

I G offset "'" 0.1 I G

(40)

9-61

iii

~SilicDnix

LPD·7

~ incorporated

mode error 80 dB more than the common-mode error(assuming its CMRR is 80 dB), the differential
mode error is by far the more important of the two.

Common Mode Errors
Common mode errors are output errors caused by
common-mode input signals. A common-mode input
signal is any signal which equally affect both sides of
a differential amplifier. Common-mode inputs often
take the form of either 60 Hz signal pickup or dc bias
signals. It is interesting to note that ambient temperature is also a common-mode signal since it affects both devices equally.

Differential mode error is the result of unequal gain
between the two sides of the differential amplifier.
This can be caused by imprecise transconductance
matching of the dual FETs, unbalanced drain resistances, unbalanced source resistances, imprecise
output conductance matching of the FETs, or any
combination of these factors. Thus, if the drain or
source resistances are adjusted for drift or offset
nulling, the differential output error will be increased
and CMRR degraded.

Common-mode input signals cause two types of output errors in differential amplifiers. One type of error
is a differential output signal caused by the commonmode input; the other is a common-mode output signal where both outputs change equally and in the
same direction. Since the op amp which follows the
FET input stage will typically amplify the differential

Consider the case where the differential amplifier has
slightly unbalanced gain. An equivalent circuit is
shown in Figure 11.

Ycc
Ro + IIRO
2

Ro _ IIRO
2
ECMDIFF
OUT

O2

0,

gos+ II gos
2

G2

G,

gl. + II gls YGs,
2

~
S,

gls- 119ISYGS2
2

~
Rs + IIRs
2

-

Rs _ IIRS
2

S2

Yoo

Figure 11.

9-62

Differential Output Equivalent Circuit

IIgos
gos--2

fCrSiliconix

.L:II

LPD-7

incorporated

A Figure of Merit CMRR can be derived for differential
out errors:
CMRR(dlff) =

Adlff
ACM(dlff)

(41)

The differential mode gain, assuming both halves of
the differential amplifier are nearly equal, can be approximated as:

Adlff

R$

9fsRD
(
1
)
+ 9fsRs
1 + gosRD .

(42)

A more general equation, resulting from the combination of all the above factors, is:

r

2gfs RCM
]
CMRR(db)=20 log l.6.RS+1/.6.9fs ± .6.RD± .6.Ro
RS+1/9fs
RD
Ro

The other type of error, common-mode output voltage, is important when only one of the outputs of the
differential stage is used, or when the following stage
has a poor CMRR. Figure 12 shows how commonmode output error can be measured. If commonmode gain for common-mode output errors is defined as

1
for - - »Rs
gos

(SO)

ForRS » 1/9f8 and RD« 1/9 os, this simplifies to the
familiar expression:
Adlff

R$

vcc,o------,t-----------,

(43)

g fsR D

If the circuit is balanced except for the drain resistors, the differential mode error resulting from a
common-mode input signal becomes:

ACM(dlff)

R$

(49)

~

~2

~CM(ln)

(44)

2RcM

so

1

2RCM
CMRR(db) = 20 log [ R;;- 9fsRDJ

(4S)

voo
Figure 12.

Similarly, the error introduced by unbalanced
transconductance is taken into account:
CMRR(db) = 20 log 2.6.gfs RCM

(46)

Circuit

then an expression may be found by noting that
(S1)

When unequal output conductances are taken into
account:
CMRR(db) = 20 log

2gfs RCM Ro
.6.Ro

Common-Mode Output Equivalent

However,
(47)

(S2)

and with unbalanced source resistors,
and
CMRR(db) = 20 log

2RCM

(48)

.6.Rs
assuming 1/9 fs

» Rs.

Vs=

-2 VD RCM

(S3)

RD

9-63

g

LPD-7
Thus,
Vo= -9fsVGRo -9fs2 RCM Vo

(54)

Siliconix

incorporated

A two-stage amplifier is shown in Figure 13. Calculations of CMRR in this circuit is made as follows:
CMRR = Adlff
ACM

and
Vo
AcM(em)= VG

-gfsRo

(55)

1+ 2gfsRcM

It is common practice to assign a Figure of Merit to a
differential amplifier. This Figure of Merit is "common mode rejection ratio," usually abbreviated as
CMRR. CMRR is defined as

CMRR =

Adiff

(56)

ACM

When equations (5) and (55) are substituted into
equation (56), it is apparent that the common-mode
rejection ratio for common-mode output errors is

CMRR(em) "'"

(58)

-gfsRo
---.!::....-9fsRo

=1+ 29fsRcM

(57)

1+ 2gfsRcM

Most op amps have single-ended outputs. In such
cases, there can be only one' result of a commonmode input signal; and error in the output. In a FET
input op amp the total CMRR will be a function of the
common-mode and differential output errors of the
preamplifier as well as the CMRR of the second
stage. To calculate the combined CMRR of both
stages of the FET input op amp, refer to Equation
(56), which is the definition of CMRR.

Substituting Equation (56) into Equation (58) we
have,

CMRRtotal = - - - - - - - ' - - - - - - - 1
(59)
[ CMRR( em) 1][ CMRR2 1+[ CMRR( dlft) 11

where CMRR(em)l is the CMRR referred to in Equation (57) for the FET preamplifier, CMRR 2 is the
CMRR specification of the second stage, and
CMRR(ditf)l is the CMRR referred to in Equation (49)
for the FET preamplifier.
In a common drain stage, the common-mode gain
with respect to common-mode output error
[ACM(em) 1 is unity (when Adlff = 1). Hence, the
entire output common-mode signal is passed along
to the second stage. All of the equations in this section, except for (50)-(55) and (57) apply equally to
common drain preamplifiers.

Frequency Response
The frequency response of a FET differential amplifier is determined by two time constants, one for the
input and one for the output.
The input time constant is formed by the generator
impedance and the effective input capacitance, Cln ,
where

(9fsRo )
Cin=\)+9tsRs

r.

9tsRS)

COG+~-1+9tsRs CGS+Cstray
(60)

ECMjln)

and

Figure 13.

9-64

Two-Stage Op Amp CMRR Model

(61)

~Siliconix
incorporated

LPD·7

.LII

The output time constant is formed by the drain resistance and the output capacitance, Cout, where

= ---=---1T

fout

2

(62)

C out RD

and
Cout

= Cgd + Cload

+ Cstray

(63)

Equations (60) and (61) apply to common drain preamplifiers as well as to common source preamplifiers, if RD = O.
For the case of the output time constant for the common drain preamplifier.
fout

=

Cout

= C gs

gfs
21TC out

(64)

+ Csd + Cload + Cstray

quency at which the gain is unity or greater. Since
the feedback around an op amp is in the inverting
input there is an intrinsic 180 0 phase shift. This dictates that the additional phase shift in the amplifier
plus the phase shifty of the feedback network must
be less than 180 0 for all frequencies where gain is
unity or greater.
Most commercially-available operational amplifiers
are compensated so that they have only 90 0 of
phase shift where gain is unity or greater. This is
demonstrated in Figure 15. When a FET preamplifier
is added ahead of an op amp, the total gain and
phase response will be the sum of the response of
the preamplifier and the second stage. Often, this
results in a phase shift of 180 0 or greater over much
of the frequency range. An intolerable situation is
thus created in that the total FET input op amp will
oscillate if the gain is set to a value where the phase
shift is greater than 180 0 •

(65)

Typically, the Bode plot of a FET preamplifier will resemble that shown in figure 14.

140
120
100

20db~::::::::~----------------------'

60

o

60

Gain
(dB)

-20 db
-40 db
I

40

-40 db/DECADE

20

-60db~------~------~~~----------~

0
O°l-----~

-20

-45 0

-40

_90 0
-135 0

-60
0

-160 0

-90

I

10
-2700~

__

~

__

~

__

~

__

~

fOUT

____

~

__

~

__

~

FREQUENCY
Figure 14.

Phase and Gain Bode Plots for Typical
FET Preamplifier

Phase
(degree)

-160

-

-270
-360
-450
.01

.........
- - -

... ....
~

,

SAFE OPERATING
AREA INCLUDING 45 0
MARGIN

~AFETY

-

'~t....;:

'"

_\ -

~

100
10 k
1M
FREQUENCY (Hz)

100 M

Stability and Phase Compensation
The stability criterion for any closed loop system, including an operation amplifier, is that the phase shift
around the loop must never reach 360 0 for any fre-

Figure 15.

Compensated Phase Shift In Op Amps

9-65

LPD·7

Cl'Siliconix

~ incorporated

As a rule of thumb, an op amp will not oscillate if the
closed loop gain is such that the slope of the roll-off
is no greater than 20 dB/decade. This point corresponds to a worst-case phase shift of 135° .

design requirement. High-frequency FETs are usually of hybrid (two chip) construction rather than of a
monolithic design, because of the significantly lower
capacitances between the two chips.

There are a number of techniques for stabilizing the
amplifier; this Application Note will not attempt to
treat them.

General-purpose dual devices are often the best
choice for FET input op amp applications, exhibiting
good gfs and breakdown voltage and moderately low
g os, leakage current, and capacitance. Generalpurpose dual FETs also tend to have low en and good
CMRR and drift characteristics.

Selecting the Proper FET Pair
FeT differential pairs can be broken down into four
general types, according to their intended application. These types include low leakage, low noise,
high frequency and general purpose FET duals.
Low-leakage FETs generally have leakage currents in
the range of 0.1 to 1.0 pA at 25°C. To achieve this
low leakage, the active area of the device is made as
small as possible. This small active area produces
low gfs and low capacitance. Although low leakage
FETs are preferred whenever low circuit leakage is is
the primary design criterion, the designer should
consider using a general-purpose FET if slightly
higher leakage can be tolerated. General purpose
devices offer better g fs, offset, drift and en than do
low-leakage devices. One feature of the low-leakage
FET which is not often specified in data sheets, but
which is important to actual circuit performance, is
thelG breakpoint; that is, the drain-to-gate voltage at
which the gate current rises rapidly. In practical circuits, the drain-to-gate voltage can reach 15 or 20
volts causing excessive leakage for FETs with low I G
breakpoints.
Low-noise FETs are designed primarily for low en.
They also have moderate g fs, low g os, and moderate
leakage and breakdown voltage. Low-noise devices
tend to have better drift and CMRR characteristics
than do other types of dual FETs. A low-noise FET
can product the lowest noise operation of any FET
when the generator impedance is below 1 to 10 MO.
For higher generator impedances, low-leakage FETs
may well provide lower overall noise performance because of their lower noise current.
High frequency dual FETs have very high gfs and low
capacitance. To achieve these characteristic
leakage currents, breakdown voltage and the IG
breakpoint must be sacrificed. Because of these
performance tradeoffs, high-frequency FETs should
be used only when their high-gain bandwidth is a

9-66

Representative geometries of the four types of FETs
described preceding are shown in Figure 16, and
provide a good insight into the relationship of device
active area and performance characteristics.
When selecting any dual FET, two factors which
affect the overall performance of the devices should
be considered.
One is the maximum value of
VGS(off); a low maximum value of VGS(Off) simplifies
bias design and improves common-mode range,
CMRR, offset and drift. The other factor is the offset
of the device. Although any value of offset can be
nulled out of a circuit, the nulling process itself
degrades CMRR and the drift performance of the
circuit.

Selecting the Op Amp Integrated Circuit
The monolithic IC op amp portion of a FET input op
amp circuit either contributes to or solely determines
five parameters of the complete circuit. For three of
the parameters - offset, drift and noise - the contributions are diminished in the complete op amp
circuit by the gain of the FET differential amplifier. In
many circuits, however, these parameters are still
significant and should not be ignored. Whenever
possible, an IC op amp device should be chosen
which specifies maximum values forVos, los, Vdrlft,
en and in. Many IC op amp data sheets will provide
only typical values for these parameters. Typical values can be in error by an order of magnitude, and
almost inevitably vary from lot to lot.
One parameter which is usually ignored on IC op amp
data sheets is so-called "popcorn noise". Even
though this parameter is missing from the data sheet
it is usually present in the op amp IC and can be quite
troublesome in low noise designs. If low noise is a
prime design criterion an op amp specified for low
"popcorn noise" should be selected.

g

Siliconix

LPD-7

incorporated
1/2 DUAL FET LOW NOISE
NNR GEOMETRY

1/2 DUAL FET LOW LEAKAGE
NT GEOMETRY

£]T

I

6~1'

.1-,0.00tM
'"",_ _ _ _ 0.016 'iD.i021
(0.432)

,

I

0.004
(0.1021

1+-_ __

Gate also backside contact

1/2 DUAL FET HIGH FREQUENCY
NZB GEOMETRY

1/2 DUAL FET GENERAL PURPOSE
NPA GEOMETRY

~l

0.021

Q&.J1

'---_---'1'
\.1,--- (0.533)
~ ----1,1

(0'432)

~

QJlQ1

(0. 02)

~---~~-r~

.1

Gate also backside contact
Gate also backside contact

Figure 16.

All dimensions In Inches
(All dimensions In millimeters)

Four FET Geometries

Two other circuit parameters, output impedance and
slew rate, are determined entirely by the IC op amp
portion of the circuit.

The upper limit is the minimum value of loss for the
type of FET selected, that is
10 operating :::; 10SS(mln)

Biasing the FET preamplifier
After the proper FET has been selected and the op
amp IC chosen for the second stage, the next consideration is the bias design of the FET preamplifier.
The first objective in biasing a FET preamplifier is the
determination of the correct FET operating current.
Usually, this will be the manufacturer-recommended
operating current of the FET, which can range from
30 IJ.A for the low-leakage devices to 200 IJ.A for general purpose or low-noise devices. If some other
value of operating current is desired. two limiting factors exist and should be kept in mind.

(66)

If a value of operating current greater than minimum
loss is selected, the FETs will operate with forwardbiased gate-source junctions, and thus negate the
low I G characteristics of the circuit.
The lower limit for lois determined by the fact that
g fs is related to 10 through the following equation

9fs "'" 9fso

~

10

loss

(67)

9-67

II

LPD-7

.rr-Siliconix

~ incorporated

where g fs is the forward transconductance at VGS =
o and I DSS, I D is the operating current, I D is the
operating current, and I DSS is the drain current with
VGS = O.
For very small values of drain current, the transconductance and thus the gain become very small.

Since the voltage drop across the drain resistors is
I CM RD/2, the voltage on the drains of the FETs is
VDO where
VDO = VCC-

ICMRD

(68)

2

It is important to insure that the voltage drop across

The next step in bias design is selection of the current source. The simplest means of establishing a
current source is via a resistor. This method, however, has an inherent drawback in that the current will
change as the common-mode voltage changes on
the gates; offset, drift and CMRR are unfavorably
affected.

the FET drain to the FET source is always greater
thanVGS(Off)' This is necessary for the FET to operate in the "pentode" or saturation region, where the
drain current is relatively independent of the drain-tosource voltage. In this condition, the device g os will
be low, and in turn will assure good offset and CMRR.

A better approach to selection of a current source is

The maximum common mode bias voltage which can
be applied to the gates without operating the FETs in
the triode region is

to use an active device, such as a juction FET current
limiter diode. These devices have very low g os and
temperature coefficient; recommended types are the
CR100 series of diodes.
In the case of the common-drain preamplifier, selection the the current sources completes the bias
design. For the common-source preamplifier, however, the value of the drain resistor remains to be
established. The value of these resistors affects
offset, drift, noise, open-loop gain, current leakage,
common-mode range, and bandwidth in the circuit.
With the exception of the last two, these parameters
will be improved if the resistors are as large as possible; the factor which ultimately limits resistor size is
the voltage drop across them. Figure (17) shows a
typical circuit employing this form of biasing.

VGG

Ic~RD

--{

VGG

~ VGS"'VGS(Off)~-(~fJ
{

2

~

ICM

~CM
2

V CM
V DD

Figure 17.

9-68

(69)

+ VGS(off)max+ VGS(on)max

Where VGS(off) and VGS(on) are negative voltages
and

~

J

1/2]

VGS(on)max "'" VGS (off) max 1 _(I

10

~OSs(max)

(70)

However in most cases VGS(on)max is approximately
VGS(off)maX so
ICMRO

2

+ VGS(off)max

(71)

The minimum common mode voltage which can be
applied to the gate is

}VDS

IC~

ICMRD
Vcc - - - 2

VGG(max) "'" Vcc -

VCC'O---~--------------------

}--

VGG(max)

Op Amp Circuit Blasing

VGG(mln)= Voo+ VCM(max) + VGS(mln)

(72)

when Voo and VGS(mln) are negatives voltages and
VGS(mln)= VGS(off)mln

J
~DSS(maX)

~ -(
~

1/2 ]

10

(73)

But in most casesVGS(mln) "'" 0 so
VGG(min)"'" Voo+ VCM(max)

(74)

.rSilicanix

..LII

LPD-7

incorporated

Drain resistors should be of good quality, such as
metal film, and should be mounted in close physical
proximity to minimize temperature differentials.
Temperature-induced resistance differentials of only
hundredths of a percent can cause offsets of many
millivolts.

PElrmissible, then the value of the drain resistors can
be found by applying Ohm's Law, as in

APPENDIX A - DESIGN EXAMPLE

Gain of the preamplifier will be as established in

This Appendix deals with a typical FET input op amp
design example, using a SlIiconix U401 N-Channel
junction FET. The U401 is designed to be operated
with an I 0 of 200 J.L A per device, or with an I CM of
400 J.LA. A general-purpose operational amplifier
should have a large common-mode range and good
CMRR. These two requirements dictate that an active current source be used, such as the Siliconix
CR043 current regulator diode. The CR043 is ideal
for this purpose, with a nominal current value of
430 J.LA :!:10% and a low temperature coefficient of
less than 0.05%I O C typically, or 0.2 J.LA/oC.
15 V

15

K.n.

..2L =
200 J.LA

15 kD.

(1)

Adlff ~ - gfsRO

(2)

From the U401 data sheet, gfs at 200 J.LA operating
current varies from a minimum of 1000 J.L'U' to a maximum of 1600 J.L'U'. For a worst-case design, the
minimum value should be used:
Adiff(mln) ~ (1 x 10

-3

4

). (1.5 x 10 ) = 15.0

(3)

The maximum positive common-mode excursion can
be calculated if the voltage drop across the drain resistors is subtracted and the device VGS(off) and the
device VGS(on) are added to the positive power supply voltage
ICMRO
VGG(max) = Vcc - - - -

15 K.n.
1%

1%

RO=

2

(4)

+ VGS(off)max+ VGS(on)max

I

,

I'

,

,

+

ICM can be up to 430 J.lA + 10% = 473 J.lA. VGS(off)
max from the data sheet is given as 2.5V, and
VGS(on) may be obtained from Equation (64) , preceding

"
VGS(on)max

-15 V

General Purpose Design
Example Circuit

Selection of drain resistor value involves a trade-off
between preamplifier gain and common-mode range.
Common-mode range decreases and gain increases
proportionally to increased value of the drain resistor.
If a voltage drop of 3 V across the drain resistors is

t

~ VGS(off)maX 1 _(I

J

1/2 ]

ID

~OSs(max)

(5)

Maximum values ofVGS(off) and loss will provide the
maximum value of VGs(on)

VGS(on)max

~ -2.5 [r-t1~·.~)1I2J ~ -2.2 V

(6)

if ±15 V supplied are used.
VGG(max)= 15 - 3.6 - 2.5 - 2.2 = +6.7 V

(7)

9-69

III

LPD-7

trr'Siliconix

~ incorporated

In Equation (14) p'receding, drift was established as

and

(8)

VC3G(mln)= Voo+ VCM(max) + VGS(mln)

Erin

where Voo and VGS are negative numbers.

~T

F>S

Eos1

~T

+~ (

lost +_1_ ( Eos2 \
9fsRo ~T)

(15)

2(6 Xl0- 10 )
1 xl0- 5
9 x 10-4 + 15.0

(16)

gfs

~T]

t

The CR043 data sheet indicates that a minimum knee
impedance of 0.75 mn occurs at VeM = 6V. Thus

(9)

VGG(mln) = -15 + 6 + VGS(mln)

Erin

~T F>S10X10

-6

+

but
VGS(mln)

F>S

~ ~

10
VGS(off)mln 1 - I
.
OSS(mln)

)1/2J

(10)

or
VGS(mln)

F>S

[1 -

-(0.5)

or

-Erin F>S 12 J.l VI 0 C worst case
~T

1/2J

(17)

(0.4)

Equation (17) assumes that the drain resistors are
perfectly balanced.

= -(0.5) • (1 - 0.6)
(11)

= -(0.5) • (0.4) = -0.20
then
VGG(mln) = -15 + 6.0 - 0.2 = -8.8 V

For drain nulling, the value of the null potentiometer
should be
2 ETln(max) gfs(max)Ro

(12)

(18)

ICM(mln)
If the U401 FET is used a J.lA741 bipolar op amp, the
offset will be as established in Equation (13), preceding:

ETln

F>S

2 los
Eos2
Eo 1 + - - + - - s
gfs
gfsRo

or

3.87 x 10-4

(13)
or

From the U401 data sheet, Eos1 = 5 mY, and gfs(mlnl
at 10 = 200 J.lA is 1000 J.lU. From the op amp data
sheet, ISO(max) is given as 200 nA. Therefore

ETln(max) = 5 x 10

+

-3

5 x 10-3
15.0

9-70

+

2 (2 x 10-7 )
3

1 x 10-

(14)

RN = 720 n

However, to this approximation for RN must be
added the maximum drain resistor unbalance, which
is 2% Ro for 1% tolerance resistors or 300 n. Thus
RN F>S 1 kn.

F>S 5.73 mV
Equation (29) established total rms noise voltage attributable to the short circuit input noise voltage of
the FET as

fCrSiliconix

LPD·7

~ incorporated

from the data sheet,
-

-15

Sel =5 x10

2

-

-16

V IHz,S~2=4 xlO

2

V 1Hz,

fl = 10 Hz and f2 = 10 kHz. Therefore,
From typical values given in the U401 data sheet,
-

Sel = 36 x 10

-18

2

-

V IHz;Se2 = 6.25 x 10

-18

;

fl= 10 Hz;f2= 10 kHz; and iffa= 1 Hz and
fb = 1 kHz, then,
or
(21)
I en21 R> 8.47 x 10 -7 V rms = 847 nV rms.

(29)

or
lenTI R>"" 2.07 x 10 15 + 6.25 x 10 15

(22)

In Equation (33) preceding it was established that

and
leTdiffl =-{2leTI= 1.4 (91 nV) = 129 nV

(30)

and from Equation (37) preceding, en was defined
In Equation (36), Tn was established as

as

R>~I-eTdlff 12l21Tni
1)2
+ - - )2lle
+ -n2gfs
9fsRD
and from the op amp data sheet, values are given
-23 -25
so that S 11 = 5 x 10
, S 12 = 3 x 10
,
fl = 10 Hz and f2 = 10 kHz. Therefore,

(31)

or

ITnlR>

~5

x 10-23 (10) (6.9) +(3 XlO- 25 ) (1 X10 3 )

(25)
(

1.5x10 1

or
ITnl=
6.2 x 10- 11 amps rms = 62 femtoamps rms.

8.47 x 10 _7)2 }1/2
(32)

or

II

(26)

Equation (35) preceding established that

R> 1.88 x 10 -7 R>188 nV rms

(33)

9-71

LPD-7

~Siliconix

~ incorporated

Frequency Response

numerous forms of op amp compensation must be
used.

As defined in Equation (57) preceding, the output
frequency of the preamplifier will be
f out

= --'---

(34)

2'ITC out RD

= Cgd + Cload

(35)

+ Cstray

or
C out

r-------------------------------~
- - - - - - 741 OP AMP
- - - - - - - PREAMP
OVERALL
RESPONSE

120 dB

where
Cout

150 dB

- .... ,

,,

90 d B '

60 dB
P:S

5 pF + 2 pF + 5 pF

P:S

(36)

12 pF

-20 dB/DECADE

,

,

,,

,

30 dB

and thus
f out =

o
1

(6.28) (1.5x10 4 ) (1.2x10- 11 )

=880

kHz (37)

-30 dB

L--J_...I-_..I-_I-.-L_....L.--1"'-_L.....;~

1

9-72

10 K

1M

FREQUENCY (Hz)

The combined Bode plot of the preamplifier and the
second stage is shown in Figure 18.
The Bode plot indicates that the op amp will be stable
for any closed-loop gain of greater than 35 dB. For
closed-loop gains of less than this value, one of the

100

Figure 18.

Bode Plot of Preamplifier and
Second Stage

100 M

wrSiliconix

LPD·8

~ incorporated

PREVENTING LATCH·UP IN MONOLITHIC DUAL JFETS
Ed Oxner
Central Applications

Monolithic JFETs offer the designer unmatched performance for a wide range of applications. While their
monolithic structure offers tight matching and good
drift characteristics it can also lead to a regenerative
current flow known as latch-up. Fortunately, it is
completely preventable, but only with some understanding of the mechanism by which it occurs.

o

G

S

exceed unity. If the base of the npn is more positive
than its emitter, the npn turns on. Likewise, if the
base of the pnp is more negative than its emitter, it
turns on. Consequently, a positive potential applied
to the npn's base will turn it on. Conduction through
the npn pulls the pnp's base below its emitter potential (base-negative with respect to the emitter) and
the pnp turns on, while conduction through the pnp
pulls the npn base high (positive), resulting in the regenerative latch-up effect. Physically interrupting
conduction is the only way to stop this effect.
GATE

1
P

P

("BACK" GATE)

("BACK" GATE)

n
EPITAXY

I

Figure 1.

P

~ODE

PNPL__p~L-n__~__-J~

n SUBSTRATE

Cross-Sectional View of a Junction-Isolated
Monolithic Dual JFET

Like CMOS, a monolithic JFET consists of multiple
layers of both p- and n-doped silicon. Figure 1 offers
a greatly simplified view. This construction technique
is commonly called "junction isolation," so named
for the fact that each junction in the monolithic structure is reverse biased. Ideally, junction isolation
means a p-n junction will not conduct when a positive
potential is applied to the n-doped region and a negative voltage is applied to the p-doped region. In practice, of course, there will be leakage currents.
Latch-up results when, as an unexpected result of
normal functioning, conduction current flows that
cannot be halted. This flow will stop only when the
device burns out or power to the device is physically
interrupted.
The potential for latch-up exists when a combination
of p-n junctions forms an SCR - a silicon-controlled
rectifier. An SCR consists of a pnp transistor and an
npn transistor in a cascode arrangement as shown in
Figure 2. SCR action occurs when the product of the
individual current gains (Beta) of the npn and pnp

GATE

Figure 2.

The Silicon-Controlled Rectifier, represented
Symbolically and Electrically

In Figure 1's simplified cross-sectional view, both
JFETs are junction-isolated from each other. The Figure shows a pair of n-channel JFETs with a p-doped
region - representing the "back" gate - surrounded
by an n-doped epi that forms an effective junctionisolated buffer between each JFET. This combination
of p-n junctions, however, forms a potential SCR.
This is more clearly shown in Figure 3.
The path in Figure 3 shows that SCR action will occur
if either "back" gate is biased more positively than
the opposing source (n-doped region) when the
substrate is left floating.

9-73

..

.HSiliconix

LPD·8

incorporated

many popular JFET applications, SeR action is entirely possible. Typical applications are shown in Figure 4.
As Figure 5 shows, preventing latch-up is simple.
Bias the substrate at a positive potential equal to or
greater than the positive potential of the uppermost
gate. This prevents the parasitic pnp from conducting, and in turn halts any SeR action.
In the special case of a differential amplifier, substitute a current regulator for the source resistor. This
not only ensures against latch-up but also improves
the amplifier's common-mode rejection performance.

SUBSTRATE

Figure 3.

Cross-Sectional View of a Junction-Isolated
Monolithic Dual JFET Showing SCR Effect

In some cases, such a combination of biases does
not exist and latch-up will not be a worry. However, in

For monolithic dual JFETs available in the TO-78
case, pin 4 is the substrate. For the TO-71 , the substrate is the can, and there is no pin connection. In
this case, a bond to the can may be imprpvised with
a spring clip; this is generally preferred to soldering a
lead to the can.

+V

+V

-V
CASCODE AMPLIFIER

Figure 4.

9-74

CASCO DE CONSTANT-CURRENT
SOURCE FOLLOWER

Typical Circuits Where Latch-Up Is Possible

ICrSiliconix

LPD·8

~ im::crpcrated

+v
+v

\
\

I

I
I
I CAN
I
/

-v

CASCODE AMPLIFIER
SUBSTRATE CONNECTION
TO-76 Pin 4
TO-71 Can

CASCODE CONSTANT -CURRENT
SOURCE FOLLOWER

Substitute Current Regulator
for Source Resistor

DIFFERENTIAL AMPLIFIER

Figure 5.

Procedures to Prevent SCR Latch-Up

9-75

.:rSiliconix

LPD-9

~ incorpora.ted

APPLICATIONS FOR THE 2N6908 SERIES
JFET AMPLIFIER
Doyle Slack

INTRODUCTION
The Siliconix 2N6908 series is much more than a
JFET; it is a complete monolithic amplifier circuit featuring a low-noise, low-leakage JFET and two parallel
diodes from the gate of the device to the substrate.
This application note will discuss the operation of the
2N6908 series and its uses and advantages. Also,
several example circuits are included to show the
2N6908 series' versatility as an impedance matching
circuit and/or small-signal amplifier.

DEVICE OPERATION AND SPECIFICATIONS
The 2N6908 series (2N6908, 2N6909, 2N6910) incorporates the features of two of our more popular JFET
products, producing a unique combination of low
noise and low leakage. Two parallel diodes are con-

nected between the JFET gate and the substrate
(which is tied to the fourth lead of the package).
These diodes clip transient spikes and overvoltages,
protecting the output of the circuit from sudden voltage fluctuations.
Figure 1 shows the two circuits and their connections
to the leads of a TO-72 can. It also shows the pad
layout and dimensions of the 2N6908 die for use in
hybrid circuit applications. Added f1exibillity can be
achieved with the 2N6908 series when they are used
as source-follower amplifiers. By varying the source
resistor, a wide range of amplifiers can be designed
- all featuring input protection. Table 1 shows some
of the more important typical values for the 2N6908
series. A transfer characteristic graph is included in
Figure 2 to give an idea of the operating range of the
2N6908 series.

NBB-A

TO-72

D

r------I --,--~..-G o-i-

BOTTOM VIEW

I

S

I
I
I
I
I
I

1.--------..1
COMMON

2N690B Series

1
2
3
4

SOURCE
DRAIN
GATE
COMMON

~.----

0.019
(0.483)

----"'i

Gate Is backside contact

Figure 1.

9-76

Schematic Diagrams. Lead Connections. and Die Layout for the 2N6908 Series.

LPD·9

~Siliconix

~ incorporated

Table 1. Typical Values for discussed parameters of the 2N6908 series

2N6908 Family

Parameter

Test Conditions

± 100

mV

Diode Leakage

< 2 pA

VG4 =

JFET Leakage

< 1 pA

VGS = OV,VDs=10V
VG4 = OV
VDS = 10V,VGS=OV

10 nV/.JHz

Noise

f = 10 Hz

2.
300r------------,-------r----------,
250
200

The diodes provide overvoltage protection for
later stages. If voltage sensitive circuits follow
the 2N6908 series part, the maximum output
swing of the 2N6908 source follower amplifier will
be less than a diode forward voltage drop above
or below ground potential if the fourth lead of the
device is grounded.

ID

(J1A) 150
100
50

-0.5

Figure 1.

-1.0

-1.5

-2.0

-2.5 -3.0

-3.5

Graph of the Transfer Characteristics
of the 2N6908 series

ADVANTAGES AND APPLICATIONS
Several advantages of the 2N6908 series - such as
low noise, low leakage, and small size - have already
been mentioned. These and other advantages over
discrete amplifiers, including improvements in both
circuit operation and ease of implementation, make
this series very attractive:
1.

A low-noise and low-leakage combination is effective in providing an extremely high input impedance and low loading. These characteristics
allow connection to the outputs of high-impedance transducers with minimal signal loss and
signal noise injection.

3. Monolithic design reduces space requirements to
a minimum, allowing circuit placement in locations that are often impossible for discrete amplifiers. It also reduces the possibility of noise insertion from nearby sources because the case of
the part is normally grounded to provide an effective RF shield. Also, the 2N6908 series' small
die size makes it very attractive for use in hybrid
circuits, such as those designed for hearing aids
where minimizing space is an essential design
factor.

4. Low-currentllow-voltage capability

makes the
2N6908 series amplifier ideal for battery operation. This is important for low-cost field operation
and for portable equipment.

The most universal application of the 2N6908 series
is in impedance matching for high-impedance
sources (such as transducers) to low-impedance
loads (such as transmission lines). Figure 3 demonstrates how simply the 2N6908 can solve the impedance problem. The input impedance of JFETs is typically in the range of 1000 G !1 (10 12 ) while the output
impedance of the amplifier is set by the source resistor. In Figure 4, the 2N6908 is shown in a more specific application - as a preamplifier for an electret
microphone.

9-77

__
__

crSilicDnix

LPD·9

~ incorporated

Vs
TRANSDUCER

r----.,

r-----12N6908

l-f-!
Figure 3.

2N6908 Devices Connected As
Impedance Transformers

Vs

ELECTRET
MICROPHONE

I
I
I
I
I
IL

Figure 4.

TO
8 ohm
LOAD

2.7!l.

_ _ _ _ _ ..1

I. 100 nF
Schematic Diagram of An Audio Amplifier Using the 2N6908 As
A Microphone Preamplifier

But what if an even lower load impedance, such as
50 n, from a transmission line is to be used? Figure 5
shows how the output impedance of the source follower circuit can be lowered even more with the help
of a bipolar transistor. The reflected resistance
through the base of the bipolar is paralleled with the
effective output resistance of the 2N6908 circuit to
produce an output resistance of less than 60 n and a
voltage gain of better than 0.95 VIV. This allows both
the source and load to be optimally matched with virtually no Signal loss.
The bipolar-assisted source follower gives great flexibility by allowing interface between any ultra high-impedance source and a 50 n load with virtually no signal loss or noise insertion. Some examples of ultra
high-impedance transducers are electret microphones, input preamplifiers for hearing aids, accelerometers for military and industrial sensing, infrared
sensors, and ion chambers such as those used for
industrial radiation exposure monitors.

9-78

+5 V to +10 V

Figure 5.

Schematic Diagram of the Bipolar
Assisted Low Output Impedance SourceFollower Amplifier

LPD·9

fCrSiliconix

~ incorporated

30 K

+5 V
ELECTRIC FIELD
DETECTOR PLATE

62 K

r-----12N690B

TTL
OUT

L _ _ _ _ _ ..1

10 K

Figure 6.

I

0.15JJ.F Mylar

Schematic Diagram of the 2N690B Series Proximity Sensor

Another example of how the 2N690B family could be
used is given in Figure 6. Here. the 2N690B series
circuit input is connected to a capacitive field sensor
(as simple as a piece of double sided circuit board) .
Any induced voltage change on the plates is fed to
the input of the peak detector section of the op-amp
circuit. The Schmitt trigger monitors the voltage
across the capacitor and changes its output state
when the capacitor voltage crossed the 2.5 V trigger
point. The output from the Schmitt trigger switches
between 0 and 5 V and is microprocessor-compatible
for sensor applications. such as computer-controlled
intruder alarms.
Another transducer interface problem occurs when
high impedance measurement networks are connected to operational amplifiers for differential measurement. This can be solved by the circuit shown in
Figure 7. Here a pair of 2N690B series parts has been
used to monitor a high-impedance bridge for an instrumentation amplifier. This circuit allows precision

measurement at low input signal levels and easy zeroing of the amplifier output.
+12 V

390 K

100 nF

o-1l--f--.----~...--..

Figure 7.

Schematic Diagram of the Low Signal
2N690B High Impedance Instrumentation Amplifier

9-79

..

.HSiliconix

LPD·9

incorporated

+6 V

+6 V

,.--------.,

I

2N690B

I
I
I

-12 V

1M

Figure 8.

Schematic Diagram of the 2N690B Series Low Power Common Source Amplifier

Another use for the 2N6908 is in the common-source
amplifier mode where low power or battery operation
is important. Figure 8 shows a circuit that will operate
in the 10- to 20- j.LA range at a 12 V supply. voltage.
The diode protection is still available in this configuration, but the circuit voltage gain will be between 10
and 20 V, with extremely low power consumption
(approximately 250 j.LW). This is very desirable for
remote or battery operation where minimum maintenance is important.

CONCLUSION
With its low noise and low leakage combination, the
2N6908 series amplifier is an ideal circuit for impedance matching. Although this series has been de-

9-80

signed for source follower applications, it is flexible
enough to be converted to any suitable amplifier design and still provide diode protection. There are
many good reasons to include these devices in your
designs, such as small size, outstanding performance, and reasonable cost, lower parts count, and
higher reliability. These advantages make the 2N6908
series preferable for numerous small signal applications.

.HSiliconix
incorporated

LPD·10
ANALOG SWITCHING USING FETS

SECTION 1: FETS AS ANALOG
SWITCHES
INTRODUCTION
The past few years have seen a pronounced growth
of analog/digital systems which employ integrated
circuits. One of the interface elements in such a system is the digitally-controlled analog switch. As more
and more applications arise for the analog switch,
especially in the areas of industrial processing and
control, the question is often asked: "Which is the
best switch for my application?"

(A)

The sheer variety of applications precludes any pat
answer to this question; however, the user of analog
switches can gain valuable insight on the subject
through an understanding of the nature of solid-state
switches. Areas which require exploration include:

BODY

T

T

1. Base factors affecting switch performance.
2.

G

Details of switch-driver circuit design.

MOS-FET

3.

Total switching characteristics of driver circuits
and switches.

N-CHANNEL DEPLETED WITH
APPLICATION OF NEGATIVE GATE
VOLTAGE. NEGATIVE BODY VOLTAGE
ALSO DEPLETES THE CHANNEL.

(B)

4. Characterization of the analog switch at high frequencies.
The intent of this section is to consider (1) above, in
detail, with minor attention to the other areas.

METAL

BODY

Field-Effect Transistor Operation
The field-effect transistor (FET) is in effect a conductor whose cross-sectional area may be varied by the
application of appropriate voltages. When the conducting area (the channel) is maximum, conductance is also maximum (minimum resistance). When
the conducting area is minimum, conductance is
minimum (maximum resistance). This phenomenon
makes possible the use of FETs as analog switches.
When conductance is maximum, the switch is in the
ON state; when conductance is minimum, the switch
is in the OFF state. In the ON state, an n-type channel
contains n-type carriers; similarly, p-channel FETs
contain p-type carriers. Cross-sections for three
types of n-channel FETs are shown in Figure 1.

~fr

T
G

IC)

Figure 1.

N-Channel FET Cross-Sections

9-81

LPD·10

ICrSiliconix

~ incorpora.tec

P-channel FET cross-sections are quite similar, except that the channel contains p-type carriers and
the voltage polarities are reversed. Depletion-mode
devices are shown in Figures 1A and 1B; these FET
types have high channel conductance (are ON) with
zero gate-channel voltage, and are characterized as
"normally-ON" switches. An enhancement-mode
FET is shown in Figure 1C. This device requires that
voltage be applied to the control gate to create a
conducting channel - the ON state. Enhancementmode FETs are said to be normally-OFF.
For enhancement-mode devices, channel conductance (g DS) is a function of length (L), width (W),
thickness (T), carrier mobility (J.l.), and mobile carrier
concentration (Nc):
N-CHANNEL

gos

gDS

WT
= K'-LJ.l.Nc

Effective channel thickness and carrier concentration
are functions of the electric field in the channel. Voltage on the control gate changes the field, and hence
the channel conductance, g DS.
Tne gate vOltage is applied with respect to the channel (source or drain). In most devices, the function
of the source and drain can be interchanged, because of symmetrical FET geometry. By convention,
however, voltage is specified between gate and
source, VGS. Figure 2 shows the variation of g DS with
VGS for both n- and p-channel devices. In all cases,
gDS = 1/rDS.
P-CHANNEL

=-'ros

gos
D

o~

D

J-FET

S

~G
S

o

o

(A)

(D)

Vp

V p Ves

gos

90S

D

MOS-FET
(DEPLETION
TYPE)

Vp

'~~G
S
(Ves = 0)

o

o

(8)

(E)
D

gos

D

J
Go1M-- (VGl - VGS(off)).
VGS(off) is a negative voltage for an n-channel FET;

thus the negative analog signal is limited by the
of Ql and the negative supply (VGl ""

VGS(off)

-20 V).
The ON condition is also shown in Figure 7. g DS is
constant because with VGl = VSIG imposed by the
switch control circuit. VGS "" O.

9-85

LPD·10

~SilicDnix

~ incorporated

1

\; _________

~O~ =-rE.s £~ _V~1~~I~

\

\
I

~B

VS1G > (VG1 - Vp )

v,p \
-20

Figure 8 also indicates that at any given pOint along
the g DS vs VSIG curve. a unique value of g DS will be
obtained. Assume that a battery is inserted between
the source and the gate. with the source clamped to
the body as shown in Figure 9.

FOR DEVICE TO
i

-15

S

REMAIN OFF

I

I

-10

-5

I

o

5

i
10

V S1G (V)

Figure 7.

t

-=- 10 V
VS1G

D

fG

1

RL

Switch ON Condition

The MOS FET as a Switch

Figure 9.

The p-channel enhancement-mode MaS FET is currently used in more applications than its n-channel
counterpart. The consideration of MaS FET switch
performance will thus center on p-channel devices.
The ON and OFF conditions of the MaS FET are analyzed in Figure 8. When the device is in the ON stage.
note that the FET begins to turn ON when VSIG (Vs or
VD) becomes VGS(th) volts more positive than VG
(= -20 V).

• Floating" Battery and
Clamped Source

A constant voltage between source and gate will produce a constant value of g DS vs VSIG. provided that
the bOdy-to-source voltage is also constant. In a
MaS FET. variation of the body-to-source voltage will
also cause a modulation of g DS. To further complicate the picture. several MaS FETs will have a
common body when they are integrated on a single
chip. Finally. the construction of a "floating battery"
circuit is difficult. Thus MaS FET switch designers
currently cope with the problem of .6.rDS by specifying rDS for a given switch at several points over the
entire analog voltage range.
Referring to the switch in the OFF condition fVG

=

+10 V). it is apparent that no problem will exist until
G

the source-to-body or drain-body diode becomes
forward-biased.

I
I CHANNEL-TOI BODY DIODE
I BECOMES

(ON) VG = -20 V
(OFF) VG = 10 V
gos

(-10 V)

-20

-10

Figure 8.

9-86

o

I ~3.~~~RD1/
10

PMOS Channel Conductance
( ros ) vs Signal Voltage

The CMOS Switch
As noted previously. the typical PMOS switch circuit
will exhibit a variation in ON conductance as the analog voltage is varied. This undesirable characteristic
can be overcome by paralleling p- and n-channel
FETs. as shown in Figure 10A. For the ON state. the
n-channel gate is forced positive and the p-channel
gate is forced negative. Figure 10B shows the
combined conductance of the two FET switches. The
integrated combination of n-channel and p-channel
devices on a common substrate is referred to as
complementary MaS (CMOS).

crSiliconix

LPD·10

~ incorporated

"--1 '
V S1G

-15 - - -

-

'----T"---oD

0---1------1

The OFF condition for the CMOS device will be maintained so long as the channel-to-body diodes do not
become forward-biased, as shown in Figure 10C.
The major advantages the CMOS construction technique makes to analog switching are:

i
B

oN

15V

-

15--I

-15 - -

0>-------11

-

(A)

90S =

1
ros

•

Lower rDS variation with analog signal characteristics, similar to the performance of a junction
FET.

•

Analog Signal range extends to + and - supply
voltages. For instance, using the same ±15 V
supplies typical of operational amplifiers, the
signal-handling capability of the system is limited
by the op amp, not by the switch.

Summary of FET Switch Performance and
Tradeoffs

90S

Figure 11 compares the performance of two switch
types with respect to rDS(on) vs VSIG.

120

-10

-15

o

-5

10

5

90

15

\

PMOS

V S1G

I VG
I VG

p-MOS

n-MOS

-15 V

+15 V

+15 V

-15 V

rOS

(.0. )

\

60

ON I
OFFI

"

I-""
30

-16

~

I""- r0- t-

(JFET)

(B)

o

CMOS

I I
-8

o

8

16

PARALLEL P-MOS AND N-MOS (CMOS)
OFF CONDITION:
VG (n-TYPE) = -15 V
VG (p-TYPE) = 15 V

90S =

Figure 11. Performance of Three FET Switches

CHANNEL-TO-BODY
DIODE OF N-TYPE
DEVICE FORWARD
BIASED
-15

-10

1
ros

CHANNEL-TO-BODY
DIODE OF P-TYPE
DEVICE FORWARD
BIASED
-5

o

5

10

(C)

Figure 10. Characteristics of CMOS
Devices

15

The curves in Figure 12 define the maximum rDS (or
tl.rDS) which can exist for a given allowable error percentage with a fixed value of RL. Recall that in the
circuit in Figure 3, a resistive load of 200 kn was assumed. If it is also assumed that an error level of
0.1 % is tolerable, then rDS = 200 n is the maximum
allowable switch resistance. On the other hand, if
settling time is not critical, then an RL of 1 Mn, yielding rDS = 1 kn is permissible.

9-87

LPD-10

~Siliconix

~ incorporated

1000

1= RL -

1 MEG

f: RL - 200 K =f- RL = 100

KK

.....
'\

./V

/.~

100
ros
OR
6ros
( .0.)

I.....

V
10

./ V

V

0.001%

RL

......

1/1/

V

/

~

50K

RL1110~

/
0.01%

OPEN SWITCH CAPACITANCE

0.1%

D

S
1%

ALLOWABLE ERROR IN V L

SW

Cs

ros
Co

Figure 12. Tolerable Level of 6ros and ros
CLOSED SWITCH CAPACITANCE

In situations where settling time is indeed a design
consideration, the circuits in Figure 13 will provide an
overview of the exact nature of settling time forV2 (=
VLl at turn-OFF and turn-ON. For a turn-ON signal, CL
charges through rDS. During turn-OFF, CL discharges through RL. For a system error level of
0.1%, RL = 1000 rDS; therefore, the maximum settling time for V 2 occurs during turn-OFF.

Consider a switch with Cs =CD = 3 pF, for an application requiring 0.1 % accuracy with 5)J.s settling
time. A typical stray capacitance (CIN for an op amp)
may be 6 to 7 pF. Therefore, CL
3 pF + 7 pF
10 pF. Resistance loads, RL, of 100 kn, 50 kn, and
25 kn are considered for the switch. The time required for an RC system to settle to within 0.1% of its
final value is 6.9 time constants (6.9 RC). Table 1
shows the RL and rDS values necessary to satisfy a
number of settling time specifications. From Table 1,
it is apparent that so long as RL::;;; 72 kn, the desired
settling time of 5 )J.s will be achieved.

=

9-88

OPEN SWITCH CONTAINING
STRAY CAPACITANCE
CL=C o+ CSTRAY

=
CLOSED SWITCH CONTAINING
STRAY CAPACITANCE

Figure 13. Switch Settling Time Equivalent Circuits

~Siliconix

LPD·10

~ im::crpcrated

while the active PMOS area is almost three times
greater than that of the JFET. Yet the ratio of PMOSto-JFET capacitance is almost 2:1.

Table 1
tOFF (V2)"
tON (V2)"
CL (0.1 % settling time) (0.1 % settling time)
(ns)
(Kn) (.0) (pF)
(lJ.s)
RL

rOS

25

25

10

1.72

1.72

50

50

10

3.45

3.45

72

10

5.00

5.00

100 100

10

6.90

6.90

• 72

• Maximum RL for tset

MOS-FET (PMOS)

= 5 IJ.S

34.0

OG181
JFET

MILS

• Does not include delay times

If cost is a design constraint. it is wise to make a
close analysis of actual system switch requirements.
Too often. designers buy unnecessary performance
capability. In Table 1. the switch with ros = 25 .0
costs nearly twice as much as does the switch with
ros = 50 .0. yet either switch will meet the 5 IJ.S settling time specification.

Switch Capacitance
In general. the lower the switch capacitance the better the switching time and high-frequency isolation
performance.
The simplified representation of switch capacitance
shown in Figure 13 can be used to provide a very
good estimate of what problems (if any) will be
caused by switch capacitance in a given application.
In general. capacitance is proportional to the active
area in a FET chip. prior to bonding onto a header.
Additional stray capacitances are introduced when
the leads are brought out through the device package. Thus. as lower ros (higher g os) is required. the
active area is generally increased to obtain that
parameter. The increase in area leads to an increase
in capacitance.
The foregoing statements are true so long as one is
dealing with a given device type. However. in transition from a JFET to a PMOS device. a significant difference will be observed in the active areas required
for a given ros. Figure 14 compares the area of a
JFET (from the hybrid DG181 circuit) and the monolithic PMOS circuit. Note that the ros for the JFET is
approximately one-third that of the PMOS device.

1
1
12.9
MILS

~
ros = 42.0.
AREA = 489.6 MIL 2
Co = 10 pF

13.7 MILS--l

ros = 15.0.
AREA = 176.7 MIL 2
Co = 6 pF

Figure 14. Active Area Comparison of PMOS
and JFET Switches

Switch Comparison
A comparison between the characteristics of the
three types of JFET switches is made in Table 2.
Table 2
Switch
Type

Analog Signal
Range

rOS ll.ros

Leakage
10 or
Is

PMOS

(V_ -VGS(th)) 50 ns RISE & FALL TIMES

nR~L__

p_u_L_SE_R_---'f---;·~1 ~"C" ~"u

D_R_IV_E_R_----,1

·1...__

OMOS

1 ns RISE & FALL TIMES

Figure 14.

Block Diagram of the High-Speed Switch

2.5
SD210DE DMOS FET

I I

l - t-

..1I

(V)

°

I

IINPtl

~

I

1\

I,

1

I

r&0.sns

I'- V

I

~UTPUTI
I-

'\

-2.5
1 ns/div
Figure 15.

Conclusions

I

1.09 ns-'fi

.~

Figure 14 is a block diagram of the complete highspeed switch capable of 1-ns turn-on and turn-off
speeds. The transition time (between the initiating
pulse that triggers the pulser and the resulting switch
action) is 30 ns.

r--

Figure 15 shows that fast switching action is possible.
Note the positive gating pulse from the step-recovery
diode pulser and the resulting switching of the DMOS
FET. For a 150-!l DMOS load resistor, the turn-off
time 3 nearly matches that derived earlier (see Figure 9): 1 ns.

3 To observe these rise and fall times requires an oscilloscope with a bandwidth of at least 500 MHz.

9-106

.r-Siliconix

LPD·12

~ incorporated

HIGH·SPEED DEPLETION·MODE DMOS FET
FOR SMALL·SIGNAL APPLICATIONS
Alan Pritchard
July 1988

The 802100 is an ultra high-speed n-channel
depletion-mode lateral OM08 transistor geared for
small-signal applications. This device boasts highperformance characteristics, produced by the
8iliconix OM08 construction, which include:

structures are similar, the device characteristics are
also similar. In fact, the depletion-mode device may
be thought of as an enhancement-mode device with
a negative threshold voltage.

•
o

Unlike the enhancement-mode devices, such as the
802100E whose drain current falls to zero when the
gate-to-source voltage equals zero, the 802100 has
appreciable current at zero gate signal. In fact, the
drain-to-source resistance is typically 100.n when
VGS = 0 V. As shown in Figure 3, the on-resistance
( rDS(on)) versus analog signal range is an almost flat
response. This characteristic coupled with the low
capacitance values of the device make the 802100
particularly suitable as an analog switch for audio and
video switching applications.

o
o
•

turn-on speeds of less than 1 ns
low reverse-transfer capacitance of less than
2.5 pF
high-frequency transconductance greater than
10 m8
wide dynamic range
low distortion

Figures 1 and 2 show idealized cross sections of the
normally on depletion-mode and the normally off enhancement-mode devices. Because these device

'

.1

•• : .......

• .............. "

••

Figure 1.

.

. . . . : ..... ,

..

'

...

,
••••

.........1 .

iii

Depletion-Mode Device Cross Section

9-107

g

LPD-12

Siliconix

incorporated

.. " ........................ ..................................... ,,'
~"~

. "" ....... " ........................... ,........... " ................. , ............................... ".. ........

Figure 2.

.

..................... :..... :, ..... " .. ; ........................ ..

Enhancement-Mode Device Cross Section

200

(2)

A = 92 .0.
B = 100 .0.

rOS(ON)
(.0. )

where

A

100

G gs

B

G dg

a
-500

0

500

ANALOG SIGNAL RANGE (mV)
Figure 3.

= __-:-.=.g....fS'--_ _
2 'IT

( Gin

+

(1)

Goud

For a common-source configured amplifier, Gin is the
short-circuit input (Miller) capacitance

9-108

It is evident that the gain-bandwidth product is largely
dependent on the device gain and the feedback
capacitance. If typical values for the 8D2100 are
substituted in Equation 1, including the low feedback
capacitance of 2.5 pF, the gain bandwidth product is
found to be greater than 400 MHz, a useful value in
VHF and UHF operation.

SD2100 On-Resistance vs. Analog Signal Range

The high-frequency gain of the device, along with its
low capacitance values, produce a high figure of
merit. An importan't factor in VHF and UHF amplification, figure of merit defines the gain bandwidth product (GBW) of the device, which may be expressed
as
GBW

= gate-source capacitance
= feedback capacitance

The high figure of merit is also reflected in the
nanosecond turn-on times which allow the 8D2100 to
be used in applications which are normally monopolized by gallium arsenide devices. Turn-on times are
important in applications such as sync-pulse generation for high-definition video systems, Signal routing
for high-speed digital video recording where data
rates of greater than 100M bits/s are possible, and
outside broadcasting systems where signal switching
is required during blanking periods. Figure 4 shows a
high-performance video dc restorer. In these applications, the low distortion characteristics are
important.

ICrSiliconix

LPD·12

~ incorporated

R

INPUT

o-Jf---.------~----,r-----1

~--~~o

OUTPUT

R
+V

Figure 4.

High-Performance Video dc Restorer

Additionally, the 802100 is useful in applications
which require both low charge injection and high
switching speeds. For example, a deglitch circuit for
the output of a high-speed digital-to-analog (01 A)
converter, such as those found in video waveform
generators, can take advantage of the 8021 ~O's high
speed, low capacitance, and low distortion.
Glitches at the O/A converter output, as shown in Figure 5, are generated during the switching transition
times when time skews allow incoming and previous
data to overlap. The worst-case occurrence is at

DAC Output With Time Skewed Glitches

-V

M8B (most significant bit) switching (e.g., from
01111111 to 10000000).

A deglitch circuit effectively forms a sample-and-hold
function which samples the output sometime after it
has settled. As O/A converter performance improves, settling times approaching 10 ns have
become possible; therefore, fast switching, low
capacitance sample-and-hold circuits, such as the
one shown in Figure 6 using the 802100, are
required.

Ideal DAC Output

III
Figure 5.

The Effect of Time Skew Glitches at the D/A Converter Output

9-109

.:rSiliconix

LPD·12

~ incorpora.ted

33 pF

R1

SI7545/8045

n-~'''J'~--fVREF

Q = +5 V Sample
Q = -5 V Hold
Charge Injection Is reduced by complementary drive to Q1 and to Q2 which acts as a "dummy" capacitor.
Figure 6.

Deglltched DI A Converter Using 2

x SD2100

Another advantage of the depletion-mode or normally on characteristic of this device makes the
8D2100 useful for single-device current regulators.
This type of circuit. usually associated with junction
FETs. is shown in Figure 7. The value for Rscan. be
calculated from

RS

=

Vas (offl

[1 - (ID/lDSS)

1/2]

"';"::~.:!!.L..-!...~~::..:....-"'-"~---"-

ID

(3)

Where lois the required value of regulated current.
The major advantage of depletion-mode M08FETs in
current-source circuits is their low drain capacitance.
which makes them suitable for biasing applications in
low-input-Ieakage. medium-speed (>50 VlJ.l.s) circuits,
In general. each side of the M440 (high speed dual
JFET) will be biased at ID = 500 J.l.A. Thus. the current available for charge compensation and stray capacitances is limited to 2 x I D or. in this case.
1.0 mAo The M440 matching characteristics are production tested and guaranteed on the data sheet.
C s represents output capacitance of the input stage
"tail" current source. This capacitance is important
in non-inverting amplifiers because the input stage
undergoes considerable signal excursions in this connection. and the charging currents in C s may be
large. When using standard current sources. this tail
capacitance may be responsible for marked slewrate degradation in non-inverting applications as opposed to inverting applications where the charging
currents in Cs are very small.

9-110

C s reduces the maximum current swing available to charge
Ce • thus reducing the slew rate.
Figure 7.

Low Bias Current Differential Front-End

The slew-rate reduction may be shown as

+ (Cst Cel

(4)

As long as C s is small compared to C c (the compensation capacitor). little change in slew rate occurs.
Using an 8D2100. Cs is on the order of 2 pF. This
approach yields a significant slew rate improvement.

~Siliconix

LPD·12

~ incorporated

Further applications result when currents greater
than I DSS (1 to 5 mAl are required. The 802100 may
be biased into the enhancement mode to produce up
to 20 mA for a VGS of +2.5 V maximum. Low output
capacitance remains a major feature. Figure 8 shows
a suitable enhancement-mode current source.

B

V~5V

-5 V

Figure 9.

Normally On Analog Switch

V BE

10 = - -

Rs

Rs

the enhancement-mode region as well as in the depletion-mode region. This effect is shown in
Figure 10.
6

{
Figure 8.

r

Enhancement-Mode Current Source

The low negative threshold voltage of the device
gives simple drive requirements and allows low voltage operation. Figure 9 shows the typical bias
conditions for a depletion-mode 802100.
To turn the device off, a negative voltage is required
on the gate. However, the on-resistance can be reduced if the device is further enhanced with a positive gate potential, allowing the 802100 to be used in

.3 V

.2

v

.1 V

10

A final advantage of a normally on analog switch is
that it may be constructed for applications where a
default condition is required at supply failure, such as
for automatic ranging of test equipment or for guaranteeing correct initialization of logic circuits at start
up.

VGS= .4 V

(mA)
OV
-.1 V
-.2 V
-.3 V

o

o

15

Figure 10. SD2100 Current vs. Drain-to-Source Voltage
The 802100 is an easy-to-use, cost-effective device
that is suitable for a wide range of high-speed applications. To improve the flexibility and high-frequency
performance, 8iliconix now offers the 88T2100 which
is housed in a 80T-143 surface-mount package.

9-111

LPD·13

~Siliconix

~ im::crpcratec

DMOS - UNDERSTANDING THE BODY EFFECT
Ed Oxner

The body effect is a common problem with many
DMOS components. To avoid the unexpected performance degradation it can,cause, designers should
be aware of this effect and its consequences.
DMOS, like all MOS products, and quite unlike the
JFET, is a four-terminal structure. The terminals are
the source, drain, gate, and the body or structure.
Many MOSFETs, FETlingtons in particular, have the
body electrically bridged to the source. In smallsignal DMOS components. however. the body is
frequently available as a separate connection.

Examine the cross-sectional view of a DMOS FET offered in Figure 1. The substrate/body of this enhancement-mode, n-channel DMOS is p-doped silicon. but a positive gate voltage inverts the p-region
beneath the gate. The resulting channel, spanning
the n-doped source and the n-doped drain. is
bounded by oxide above and p-doped silicon below.
During conduction, this n-enhanced channel bounded
by the p-doped substrate resembles that of an nchannel JFET. Figure 2 offers an idealized comparison.

DMOS

Often, the body is simply tied to the source. While
this is a perfectly acceptable solution for many applications, there are exceptions. For example. consider
a Zener-gate protected DMOS, such as the
SD211 DE, used as an analog switch. Under no circumstances may the Zener be forward-biased; consequently, the gate must never be more negative
than the body/substrate. Yet. to ensure an off condition, the gate-to-source potential must be less than
the threshold voltage. If the analog signal being
switched swings negative, the gate must be more
negative to maintain proper control. The body must,
in turn, be more negative than the gate to prevent
forward-biasing of the Zener.

P
SUBSTRATE/BODY

BODY

JFET
SOURCE

I
SOURCE

GATE

DRAIN
OXIDE

I

BODY
Figure 1.

9-112

Cross-Sectional View of
Enhancement-mode DMOS

DRAIN

I

.: n .

I
CHANNEL

Figure 2.
SUBSTRATE p-

GATE

Comparing the DMOS Channel
to the JFET Channel

Together, the n-enhanced channel and the p-doped
substrate/body form a diode; the p-substrate is the
anode and the inverted region is the cathode. Diode
conduction occurs whenever the forward bias exceeds the barrier potential, which for a silicon p-n
junction is nominally 0.55 V.

.rSiliconix
.z.
incorporated

LPD-13
an abrupt increase in body current results: the body
effect.

SD210DE
10 9

......

10 7

~

10 5

'fI

10 3

~
Jj)

10
0.1

--

1///

IB
(pA)

,..A

P'

~
o

iIIIII'"
10

20

Returning to the analog switch scenario: If the body is
biased negatively to where the drain-body voltage
approaches 10 V (as per Figure 3), substantial channel-body current flow. Among other observable problems, this will strongly offset the analog voltage being
switched (I Body R Load) .
This problem is not limited to the analog switch scenario. Any application (with or without a Zener gate
diode) where the drain-to-substrate potential exceeds 10 V may result in undue drain-substrate current flow.

VDB (V)

Figure 3.

Leakage current vs. voltage

This channel-substrate diode is the key to the body
effect. Figure 3 identifies its reverse leakage. As with
any diode, some nominal leakage occurs until reverse breakdown is reached and the current rises
dramatically. Especially dramatic, though, is the apparent low breakdown voltage evident in Figure 3.
When the nominal drain/body potential passes 10 V,

In addition to this current flow effect, there are other
body-related phenomena to be considered. Threshold voltage and on resistance both rise quite dramatically as the source-body voltage increases. For more
information on these effects, see Application Note
LPD-10.
In conclusion, generally a good rule of thumb is to tie
the substrate/body terminal to the most negative
voltage that the DMOS will experience (including the
gate potential). Under no circumstances should the
substrate float as carrier-induced charges will lead to
threshold and on-state instabilities.

9-113

LPD-14

~Siliconix

~ incorporated

DESIGNING FET BALANCED MIXERS FOR
HIGH DYNAMIC RANGE
Ed Oxner
Central Applications

SECTION 1: FETS IN SINGLE
BALANCED MiXERS
INTRODUCTION
When high-performance, high-frequency junction
field-effect transistors (JFETs) are used in the design
of active balanced mixers, the resulting FET mixer
circuit demonstrates clearly superior characteristics
when compared to its popular passive counterpart
employing hot-carrier diodes. Comparison of several
types of mixers is made in Table I. The advantages
and disadvantages of semiconductor devices currently used in various mixer circuits are shown in
Table II.

Initial evaluation of the active FET mixer will imply a
disadvantage because of local oscillator drive
requirements; bipolar devices in low-level mixers require very little drive power. However, in high-level
mixing this disadvantage is overcome in that drive
requirements at such mixing levels are generally the
same, no matter whether bipolar or FET devices are
used.
Table 2
DEVICE
Bipolar
Transistor

Diode

Table 1
JFET

MIXER TYPE
Double
Balanced
Decade

Characteristic

Single-Ended

Single
Balanced

Bandwidth

Several
decades
possible

Decade

Relative 1M
Density

1.0

0.5

0.25

Interport
Isolation

Little

10-20 dB

>30 dB

Relative

o dB

+3 dB

+6 dB

ADVANTAGES

DISADVANTAGES

Low Noi sa Figure

High 1M

High Gain
Low D.C. Power

Easy Overload
Subject to Burnout

Low NOI sa Figure
High Power Handling

High L. O. Drive
Interface to I. F.

High 8urn-out Level

Conversion Loss

Low Noise Figure
ConversIon Gain
Excellent 1M products

Gain Not Possible at
Optimum Square
Law Response

Square Law Characteristic
Excellent Overload

Optimum Conversion

High Lo Power

High Burn-out Level

Dual-Gate

MOS FET

Low 1M DistortIon

AGO

High NoIse FIgure
Poor Burnout Level

Squre Law CharacterIstIc

Why FETs for Balanced Mixers?

L. O. Power

Why an Active Mixer?
Active mixing suggests high-level mixing capability.
High level mixing in turn infers that active mixers outperform passive mixer circuits in terms of wide
dynamic range and large-signal handling capability.
Additionally, the active mixer offers improved conversion efficiency over the passive mixer, permitting
relaxation of the IF amplifier gain requirements and
even possible elimination of the customary RF
amplifier front end.

9-114

The performance priorities of modern communication
systems have stringent requirements for wide dynamic range, suppression of intermodulation products, and the effects of cross-modulation. All of the
foregoing parameters must be considered before
noise figure and gain are taken into account.
Since FETs have inherent transfer characteristics
approximating a square-law response, their thirdorder intermodulation distortion products are generally much smaller than those of bipolar transistors.
Harmonic distortion and cross-modulation effects are
third-order-dependent, and thus are greatly reduced
when FETs are used in active balanced mixers.
A secondary advantage derives from available
conversion gain, so that the FET mixer becomes simultaneously equivalent to both a demodulator and a
preamplifier.

.:r-Siliconix
.LII incorporated

LPD-14

First Order Balanced Mixer Theory
Essential details of balanced mixer operation,
including signal conversion and local oscillator noise
rejection, are best illustrated by signal flow vector
diagrams (Figure 1).

both the local oscillator vector and the noise
component, FET "A" is OFF and FET "6" is ON.
Moving ahead an additional one-half of the IF cycle,
FET "A" is again ON, but the noise component has
advanced 180 0 (Witt) through the coupling structure,
and is now" out of phase". The process continually
repeats itself.
The end result of this averaging (detection) is the
cancellation of the noise which originated in the local
oscillator, providing that the mixer balance is
precise 1.

H----'-t .. L L U - - - - - t - - - I : F
FETs

SIGNAL
CONVERSION

A

The analysis of the conversion of the signal to the IF
pass-band is similar, but the signal is injected into the
coupling structure at the equipotential tap. Thus at
time t2, the signal vector (e s) is "out of phase" with
the local oscillator vector, el o . The resulting envelope develops a cyclic progression at the IF rate,
since the signal is" demodulated" by the mixing
action of the FETs.
A schematic of a prototype balanced mixer is shown
in Figure 2. Design criteria, in order of priority,
include the following:

B

1. Intermodulation and Cross-Modulation
NOISE
REJECTION

A

2.

Conversion Gain

3.

Noise Figure

4.

Selecting the Proper FET

5.

Local Oscillator Injection

6.

Designing the Input Transformer

7.

DeSigning the IF Network

B

Figure 1.

Signal and Noise Vectors

Intermodulation and Cross-Modulation
Energy conversion into the intermediate frequency
(IF) pass-band is the major concern in mixer operation. In the following analysis, both the signal and
noise vectors are shown progressing (rotating) at the
IF rate (Witt); the resulting wave occurs through
vector addition.
The analysis of local oscillator noise rejection (Figure
1) assumes, for simplicity of explanation, that noise
is coherent. Thus at some point in time (t 1) the noise
component (en) is "in phase" with the local oscillator
vector (elo ) and FET "A" (the rectifying element) is
ON; the JFET mixer acts as a switch, with the local
oscillator acting as the switch drive signal. One-half
cycle later, at time t2, the signal flow is reversed for

A basic aim in mixer design is to avoid the effects of
intermodulation product distortion and cross-modulation. Part of the problem may be resolved by using a
balanced mixer circuit.
The active transfer function of the FET is represented
by a voltage-controlled current source. For both
cross-modulation and intermodulation, the amount of
distortion is proportional to the amplitude of the gatesource voltage. Since input power is proportional to
input voltage, and inversely proportional to input
impedance, the best FET 1M and cross-modulation
performance is obtained in the common-gate
configuration where the impedance is lowest 2 .

9-115

~

..

LPD·14

.-rSiliconix

.LII

incorporated

",T, '" ~ '1o"f"T

III
III
III

Cs
E-!LO

T_ ClO

III
III
III

'

-=C,. C s
C 2 • C4
C3
CS. C a
C 7• C g
C lO

-

01.ufd

- 1 - 10 pF

- 1000 pF

- 30 pF
- 66 pF

- O.l.uF

L,. L2 - 1.3.uHy
0,. O2 - U310 (2) or U430
T,
- RELCOM BT-9

Figure 2.

Prototype Active Balanced Mixer

When JFETs are used as active mixer elements. it is
important that the devices be operated in their
square-law region. Operation in the FET square-law
region will occur with the device in the depletion
mode. Considerable distortion will result if the FET is
operated in the enhancement mode (positive. for an
n-channel FET); by analogy. the problems encountered are similar to those which arise when positive
drive is placed on the grid of a vacuum tube.
Square-law region operation emphasizes the importance of establishing proper drive levels for both quiescent bias and the local oscillator. The maximum
conversion transconductance. gc. is achieved at
about 80% of the FET gate cutoff voltage. VGS(off).
and amounts to about 25% of the forward transconductance. gfs. of the FET when used as an amplifier.
Since conversion gain (or loss) must be considered.
it is common to equate voltage gain Av. as:
(1)

where g c is the conversion transconductance and RL
is the FET drain load.
An attempt to achieve maximum conversion gain by
indiscriminately increasing the drain load resistance
will adversely affect any design priority concerning
distortion
particularly intermodulation. product
distortion.
Distortion takes different forms in mixers. Most obvious is that distortion which will occur if the FET is
driven into the enhancement mode. as noted earlier.

9-116

A more pernicious form is drain load distortion. And
finally. there is the so-called "varactor effect. "
The most frequent cause of poor mixer performance
stems from Signal overloading in the drain circuit.
Excessive drain load impedance degrades the intermodulation characteristics and produces unwanted
cross-modulation signals 3 . A characteristic of the
FET balanced mixer is that the correct drain load impedance is inversely proportional to the value of the
conversion transconductance. Figure 3 shows the
improvement in the 1M characteristics obtained in the
prototype mixer with the drain load impedance
reduced to 1700 n from 5000 n. Specifically. the
dynamic load line must be plotted so that the signal
peaks of the instantaneous peak-to-peak output
voltage are not permitted to enter into the non-saturated ("triode") region of the FET. Suitable and
unsuitable drain load lines are shown in Figure 4.
Load impedance selection is quantified in Equations
21 through 23.
Distortion from the "varactor effect" is of secondary
importance. and arises from an excessive peak
voltage signal swing. where the changing drain-tosource voltage can cause a change in parasitic
capacitance. C rss • and give rise to harmonics 4 . A
FET tends to be voltage-dependent when the drain
voltage falls appreciable below 6 volts. If the source
voltage (from the power supply) is also low and the
drain load impedance in high. then distortion will
develop. However. if proper steps are taken to
prevent drain load distortion. the varactor effect will
also be inhibited.

~Siliconix

LPD-14

~ incorporated

,
15

\

14

\
\
\

13

=

\

12

Intercept, ...

\

Point

+36

n" ....

= the

The effects of time-varying local oscillator voltage.
V2. and the much smaller signal voltage. Vl. must be
considered:

+40

+32

~

\

11

where wi
the intermediate frequency and wr
signal frequency.

t44

Source Injected Mixer (L.O, & Signal)
Freq LO = 120 MHzj Power LO: +17 dBm
Freq S'9 = 150 MHz
Drain Impedance: 1700 ohms'" - - .....
5000 o h m s - -

(4)

• +2B

\

S.S.B.
NOISE 10
FIGURE
(dB)

+24
(dBm)

For square law operation

+20

(5)

+15
7

+12

6

+B

5

t4

Drain current is approximately defined by

o

L---~----~----~----~--~o
2

3

ID

5

= IDSS

VGS

~

J
2

VGS
- VGS(off)

(6)

or
Figure 3.

Comparison of Mixer 1M Characteristics

~
VGS(off)

J
2

(7)

or
gfso
[
J2
ID =--:::7';":":"':'--- VGS(off)- Vgs
2 VGS(off)

(8)

then
ID

gfso
2V
(complex Taylor expansion)
GS(off)

(9)

which can be reduced

Vas

Figure 4.

=

ID(IF)

Plotting Drain Load Lines

=

gfso
2V
Vl V2 COS(Wl-W2)t
GS(off)

(10)

and the conversion transductance is

(11)

Conversion Gain
In a FET. forward transconductance is defined
as
(2)

Equation 11 suggests that gc increases without limit
as V2 increases without limit. However. to avoid operation of the FET in the "triode" region. the peak-to-

__

peak swing of V2 should not exceed VGS(off).

~

Thus

and conversion transconductance is defined as

2 V2 peak
dlD(wi)
dVgs(wr)

S

VGS(off)

(12)

or
(3)

V peak < VGS(off)
2
2

(13)

9-117

LPD-14

~Siliconix

.L;II incorporated

28.0 ,........,..-.,.-r-...,....-.,.-r---:'"Lo-c-u-s-Of0:--.,
---VLO=VGO
24.0 1--I--+All--Hrl"'-l,--"1""'==t--i=-t
VLO = 0.8 VGS(off)
20 . 0
ge/gfs 16.0
x 100%

I--I-+-I--'\t-~r-:±'V LO=
I-+-I=IF::P\-l-\-+~V

LO =

VGS(off)
-2VGS(off)
3

I

, 2.0 i--H'==f=-I==~~~-+\-+-t-+--l

4.0

o

0.2 0.4 0.60.8 1.01.2 1.4 1.6 1.8 2.0
VGOIVGs(off)

power-match source admittance, gigs, which closely
matches the output admittance of the coupling transformer. In the common-gate configuration, match
points for optimum power gain and noise do not occur at the same value of generator resistance (Figure
6). Optimum noise match can only be achieved at
the sacrifice of bandwidth.
!-In
.., tn
1."",,,11'
......

~elel"t
_ _ • _ _ • •the
•• -

Prnner
I=I=T
• • _1""' __
• _.

Conversion efficiency is determined by conversion
transconductance, gc, which in turn is directly
related to such FET parameters are zero-bias saturation current, I DSS, and the gate cutoff voltage,
VGS(off)) :
(14)

Figure 5.

Normalized gelgf vs.VGSIVGS(offl
(from "FET RF Mixer Design Technique",
S.P. Kwok, WESCON Convention Record
(1970) 8/1, p.2.) Used with Permission

Figure 5 shows plots of normalized conversion
transconductance, gc/9 fs versus normalized quiescent bias, VGS IVGS(off), for different oscillator
injections.

Noise Figure
Like the common-gate FET amplifier, the commongate FET balanced mixer is sensitive to generator
resistance, Rg 5. A change of a decade in Rg can
produce a noise figure variation of as much as 3 dB.

3 dB

Power Gain

(15)

Equation 14 appears to indicate that FETs with high
IDSS are to be preferred. However,lDsS andVGS(off)
are related, and Figures 7a and 7b show that devices
from a family selected for high I DSS do not provide
high conversion transconductance, but actually
produce a lower value of gc.
5

v

a.
VGS(off)
(V)

,/
2

Noise

./

,;

io' ....

5
Power Gain
and
Noise Match
(dB)

b.

40

5

3

.........

[VGS(Off)12 2

i ' .....

i'..........

Generator Resistance (0.)
Power Gain and Noise Matching

1

3

In the design of the prototype FET active balanced
mixer, the generator resistance of the FETs is
established by the hybrid coupling transformer. Two
important criteria for the FETs in the circuit are high
forward transconductance,
and a value of

9-118

10
20
loss (rnA)

4
loss

Figure 6.

/"

5

10

20

30 40

loss (rnA)

Figure 7.

Relationship of loss and VGS(off)

H

Siliconix

LPD-14

incorporated

Best mixer performance is achieved with "matched
pairs" of JFETs. Basic considerations in selecting
FETs for this application are gate cutoff voltage,
VGS(off), for good conversion transconductance, and
zero-bias saturation current, I DSS, for dynamic
range. A match to 10% is generally adequate.
Among currently available devices, the Siliconix U31 0
and the dual U431 offer excellent performance in
both categories; common-gate forward transconductance is 14,000 mmhos typical at VDS = 10 V,
I D = 10 mA, and f = 1 kHz.

Criteria for FET Selection
In balanced mixers using FETs, conversion efficiency
of the devices is determined by conversion transconductance, gc, which in turn is directly related to such
FET operating parameters as zero-bias drain current,
I DSS, and gate cutoff voltage, VGS(off).

increased dynamic range. Since balanced mixer
design involves many tradeoffs for best performance, this I DSS vs. VGS(off) problem is generally
inconsequential.
There is, of course, the possibility that FET cost is a
major consideration in evaluating the active balanged
mixer approach - the familiar price/performance
tradeoff. If this is the case, there are a number of
other Siliconix FETs which will provide suitable alternatives to the U310 (Table 3). Remember, however,
that conversion transconductance, go, can never be
more than 25% of forward transconductance. Thus
as tradeoff considerations begin, the first sacrifice to
be made will be the degree of achievable conversion
gain. Intermodulation performance will follow with the
third tradeoff being available noise figure.

It can be shown that
I DSS

2 VGS(off)2

Table 3

1 1 """
g fso
1V21
V2
2 VGS(off)

(16)

where V2 is the time-varying local oscillator voltage.
To maintain operation in the square-law region, we
repeat Equation 13,
V2 (peak)

::;

VGS~Off)

(17)

where now, under optimum performance conditions,
we merge Equation 11 with Equation 13 to find
gfso
go """

2 VGS(Off)

VGS(Off) __ gfso
2

(18)

4

which agrees with Equation 15.
For the highest level of conversion transconductance, it would appear initially that for any given FET
geometry, units with high I DSS are to be preferred.
But as we saw in Figure 7, since I DSS and VGS(off)
are related, a performance tradeoff is necessary;
however, an increased value of I DSS provides

DEVICE TYPE

Typical
Characteristics

U310'

2N5912

2N4416'

9m

15 K

6K

5K

3.5 K

15mA

10 m

10 mA

IDss

40 mA

2N3823

'Similiar products are available In TO-92:
U310 (J310)
2N4416 (2N5486)

Local Oscillator Injection
Low 1M distortion products and noise figure, plus best
conversion gain, will be achieved if the voltage swing
of the local oscillator across the gate-to-source junction is held to the values presented in Figure 5. VLO is
expressed in terms of peak-to-peak voltage, while
VGS(off) is a d.c~ voltage.
Local oscillator injection can be made either through
a brute-force drive into the JFET source through the
hybrid input transformer, or through a direct-coupled
circuit to the JFET gates where less drive will be required for the desired voltage swing. Two circuits to
obtain direct gate coupling are suggested in Figure 8.

9-119

iii

LPD-14

.-:r'Siliconix

~ incorporated

2.

+-----t-----IE----o

ZRFo--1

Z 10

Offer a match between either input to a symmetrical balanced load

3. Provide as much isolation as possible between
the signal and local oscillator ports (Figure 9)
4.

Gates Tied In Parallel
L2 Resonates withe 9
a.

Maintain a differential phase of 180 0 across the
symmetrical balanced loads

5. Introduce the least possible amount of loss

L-

r

Gates Driven Push-Pull
Sources Tied Together
b.

Figure 9.
Figure 8.

4-Port Hybrid with Phase and Isolation

Alternate Forms of L.O. Injection

The source-injection method is used in the design of
the present mixer to maintain the inherent stability of
a common-gate circuit. A minor disadvantage with
the direct-drive method is that the required gate-tosource voltage swing requires considerable local
oscillator input power. For source injection through
the transformer, best mixer performance is obtained
with a local oscillator drive level of +12 to +17 dBm
across a 50-.0 load.
Conversely, direct coupling to the FET gates occurs
at a higher impedance level and less local oscillator
drive power is required. The functional tradeoff
resulting when the gates are tied together is that
shunt susceptance requires some form of conjugate
matching, and thus brings about an undesirable
reduction of instantaneous mixer bandwidth.

Designing the Input Transformer

A transformer using ferrite cores and meeting these
five requirements is derived from elementary transmission-line theory (Figure 10). Transmission line
transformers have a low-frequency cutoff determined
by the falloff of primary reactance as frequency is
decreased. This reactance is determined by the series inductance of the transmission line conductors.
On the other hand, high-frequency performance is
enhanced by minimizing the physical length of the
transmission line. Minimizing overall line length while
maintaining suitable reactance can be accomplished
by using a high-permeability core material such as a
ferrite. The transformer constructed for the balanced
FET mixer closely resembles the balanced 4-port
unsymmetrical 180 0 hybrid device described by
Ruthroff 6.
Although Ruthroff does not discuss the method of determining the winding length of bifilar wire, a solution
is offered by Pitzalis 7 • The Pitzalis definitions for wire
length are as follows (Figure 11):

Five criteria are important to the design of the hybrid
input coupling transformer for best mixer performance. The impedance transformer must

max length

= -f7200n
-upper

Consist of four single-ended terminals, for the local oscillator, the input signal and FETs A and B

min length

= (1

1.

9-120

.
(Inches)

+ J.L I J.Lo) f lower

(19)

(inches)

(20)

g

Siliconix

LPD·14

incorporated

2R

..1.
4

R

2R

2R

Figure 10.

Hybrid Input Coupling Transformer

where RL = the load impedance. ).1./).1.0 = the relative
permeability of the ferrite at the lower frequency. and
n = a fractional wavelength determined by the
amount of allowable phase error.
Selection of the ferrite core material is determined
mainly by performance requirements. A prime consideration for wideband performance is the temperature coefficient of the ferrite. which must have a low
loss tangent over the required temperature range.
i.e .• high Q.
In addition. an important design factor involves the
relative permeability of the core. since inductance of
a conductor is proportional to the permeability of the
surrounding medium. A high permeability material
placed close to the transmission line conductors acts
upon the external fringe field present. appreciably
magnifying the inductance and providing a lower
cutoff frequency. Power transferred from input to

output is coupled directly through the dielectric medium separating the transmission line conductors;
thus a relatively small cross-section of ferrite material
can operate in an unsaturated state at impressively
high power levels. For the FET balanced mixer. ferrite core material with a permeability of 40 provides
satisfactory operation from 50 to 250 MHz. Figure 11
also demonstrates that a lower transmission line impedance. Zoo is to be preferred over a higher Zoo
Both 50-n and 100-n transmission lines are required
for the mixer transformer; twisted pairs will provide
satisfactory results. A characteristic impedance of 45
n is obtained from 3 turns-per-inch of Belden No. 24
AWG enamel wire. while 3 1 / 2 turns-per-inch of No. 24
(7X32) Belden plastic covered wire provide
Z a = 100 n. Each core is wound with 2 inches of
proper twisted pair. with min/max lengths calculated
from Pitzalis' data (Formulae 19.20).

A

Z a = 2 Z a Optimum

+40

2R

+20
~

~zoOPtimum
~ =+z a Optimum

oJ-..~~--20

2R':"
a.

-40L-~~_~~~~~~~~___
0.02

B

0.06
0.10
0.14
Length of Wire A In)
b.

0.18

Figure 11. Toroid Coil Winding Data

9-121

LPD-14

a'r'Siliconix

~ incorporated

As with all broadband transformers, the coil has an
inherent parasitic inductance which must be capacitor-compensated (C 2, C 4, Figure 2). A trim capacitor is required at the two input terminals, and is
adjusted only once to optimize the differential phase
shift across the symmetrical balanced FETs. Phase
match of the hybrid structure may be tracked to
within ±2 degrees (about 180°) to 250 MHz. Effective
resistance transformation IS useful from 50 to
550 MHz (Figure 12) - but phase track beyond
250 MHz may show too much deterioration.

output, serving three useful functions. First, it serves
to achieve the proper drain load match between the
FETs and the IF structure. Second, it provides the
very necessary isolation of the intermediate frequency signal. And third, it serves as a simple filter
to provide a monotonic decrease in impedance as
frequency departs from the IF center frequency,
f 0 8 . This third function, shown in Figure 13, prevents the drain ioad impedance from skyrocketing
out of control and giving rise to distortion products.

+

Olstortlon Region

)50

Uncontrollable

______________ I-F

~

________

~

~

121

Figure 13. PI (TI) Match Filter Function

Figure 12. 50.n - 200 .n Balun

Designing the IF Network for
Single-Balanced Mixers
The IF network performs two important functions in
the FET balanced mixer circuit. It provides for optimum match between the FETs and the IF amplifier,
and it effectively bypasses the circuit RF components
(signal and local oscillator).
In network deSign, it is essential that the RF and local
oscillator signals be sufficiently isolated from the
intermediate frequency signal to maintain rejection
levels of at least 20 dB. If this isolation is not maintained, conversion gain and noise figure are
degraded.
The simplest technique for design of the IF network is
to use the well-known pi (TI) match structure from
each FET drain to a common balanced output transformer network. This pi match technique is especially
suitable for a narrow-band intermediate frequency

9-122

Selection of the dynamic drain impedance value in
the IF network is a critical point in design of the structure. Intermodulation product distortion and crossmodulation will be both affected by the instantaneous
peak-to-peak output voltage of the FETs, if the value
of the dynamic drain impedance allows these signal
peaks to enter either the pinch-off voltage or breakdown voltage regions of the transistors. If the impedance is too high, the dynamic range of the mixer will
be severely limited; if the impedance is too low, useful conversion gain will be sacrificed.
A first-order approximation to establish the proper
load impedance may be obtained when

RL = Voo- ~ VGS(Off)
Id

(21)

where

id = loss

~

~]

2

(22)

VGS(Off)

and
Vgs

= VGS

+ V1 sin w1 t

(23)

.rSiliconix

LPD·14

~ incorporated

For the U310 FET. the optimum drainload impedance
is established at slightly less than 2000 n. with sufficient local oscillator drive and gate bias determined
from the conversion transconductance curve in
Figure 5.

300 kHz apart. the balanced mixer suppressed thirdorder products -89 dB with both signals at -10 dB.
representing an intercept point of +32 dBm.

The output IF coupling structure is an 800-n CT to
50-n trifilar-wound transformer (Relcom BT-9 or
equivalent). The pi (1T) match into this transformer
provided a dynamic drain load impedance of 1700 n
on each FET; excellent 1M performance was obtained. Value of operating Q was established at 10 as
the best compromise to insure that the tolerance of
the pi match components would permit the IF output
to peak within the allowable bandwidth at the associated IF amplifier. A Q of more than 10 would result in
a greatly restricted bandwidth. while a Q of less than
10 would result in excessively high capacitance. excessively low inductance. and unsatisfactory filter
performance.

50-150 MHz Mixer Performance Comparison

Table 4

Characteristic
Intermoduiation Intercept
Point
Dynamic Range

JFET
+32 dB

Conversion Gain

Bipolar

+28 dBm +12 dBmt
100 dB

80 dBt

+3 dBm

+1 dBmt

+2.5 dB"

-6 dB

+18 dB

7.2 dB

6.5 dB

6.0 dB

100 dB

Desensitization Level
+8.5 dBm
(the level for an unwanted
signal when the desired
signal first experiences
compression)

Single-sideband Noise
Figure @ 50 MHz

Schottky

Single-Balanced Mixer Performance
* Conservative minimum

Tests of the operational prototype FET singlebalanced mixer demonstrated that the active mixer
has several characteristics superior to those of passive mixer counterparts. These comparisons are
made in Table 4 (measurements of all three mixers
were made under laboratory conditions).

tEstlmated

Figure 14 shows a comparison of third-order 1M products emanating from both the JFET balanced mixer
and a typical low-level double-balanced diode mixer.
under similar operating conditions. Noise figure and
intercept point are shown at various bias and local
oscillator drive levels in Figure 15.

Insertion loss measurements on the IF network
amounted to 3 dB in the center of the passband.
while insertion loss on the hybrid assembly measured
1.2 dB. The network exhibited a Q of 10. Gain and
noise figures were measured over the full
50-250 MHz bandwidth. with a single-sideband noise
figure ranging from 7.2 dB at 50 MHz to 8.6 dB at
250 MHz. Conversion gain was a flat +2.5 dB.

The performance of the active mixer is clearly
superior to that of the diode mixers. contributing
overall system gain in areas critical to telecommunications practice. and reducing associated amplifier
requirements.

Two-tone third-order intermodulation is expressed in
terms of the intercept point 9 . With two signals

The reason for using the three-core bifilar transformer (Figure 11 A) In this tutorial article stemmed

CONCLUSION

30

(dB)

40

o

co

Figure 14. Comparison of 3rd Order 1M Products

9-123

iii

g

LPD-14

Siliconix

incorporated

Measured Performance Source-Injected Mixer
L.O. Power +17 dBm AND +22 dBm
1700 0 -----Drain Load Impedance:

50000--

S.S.B.
Noise Figure
(dB)

:ira
24 Order Intercept
(dBm)

10
9

20

6

16

7

12

6

6

5

4

L-__

0

~

____

~

__

2

~

____

3

~

4

__

~

5

__

~~

6

__

~

7

__

~O

6

VGS

Figure 15. Noise Figure and Intercept Point Performance
Single-Balanced Mixer

SECTION 2: JUNCTION FETS IN
DOUBLE-BALANCED MIXERS

cillator drive requirements. Thus the active balanced
mixer which employs field-effect transistors is a welcome innovation: conversion gain and improved intermodulation distortion characteristics alone place
the FET double-balanced mixer far ahead of its passive counterparts. The high saturation levels possible
with modest local oscillator power make such a mixer
useful for mixing both small and large Signals.

INTRODUCTION

First Order Double-Balanced Mixer Theory

Dynamic range is probably the most important consideration in modern receiver design. Table 1
provides a comparison between the harmonic distortion characteristics of a simple mixer, a single-balanced mixer, and a double-balanced mixer. The
comparison clearly shows those performance characteristics of the double-balanced mixer which have
made it one of the most popular of all mixer types.
Among these attributes are greatly improved
interport isolation and a significant degree of
rejection of local oscillator carrier amplitude
modulation.

In either single or double-balanced mixer design, the
prime requirement is that when the mixer is excited
by the local oscillator carrier, the circuit must be capable of rejecting the amplitude-modulated wave
which exists about the L.O. Also, the mixer must reject any AM signal entering from the local oscillator
port. (This signal rejection is usually known as AM
local oscillator noise cancellation).

from the relative analytical simplicity of such a
design. An alternative transformer is the single-core
trifilar-wound design. The definitions for wire lengths
(Equations 19 and 20) are equally applicable to trifilar
as they are for bifilar.

When used in double-balanced mixers, however,
passive devices such as Schottky-barrier (hot
carrier) diodes have certain fundamental shortcomings, such as high conversion loss and high local os-

A second requirement for balanced mixers is the
establishment of interport isolation between the
signal, local oscillator, and IF ports. A third desirable
characteristic is the reduction of intermodulation
distortion products.
Careful attention to design of double-balanced mixers
will satisfy the foregoing criteria.

~Siliconix

LPD-14

~ incorporatec

L1

SIG C1

~

T4 - RELCOM

BT-9

T2

T1

II
II

II

II

II

L1, L2 - 1.3.uHy
C1 - 0.01.uF
C2, C7 - 0.10.uF
C3, C4 - 30 pF
C5, C6 - 68 pF

II

+VDD

' - - - - - { O J Local

Figure 16.

OSC

Double-Balanced Mixer

The schematic of a prototype double-balanced mixer
(Figure 16) employs four high-performance junction
FETs chosen for closely matched characteristics.
(The significance of the quad-FET configuration will
be dealt with later).

If the schematic in Figure 16 is reduced to show only
the local oscillator circuit (Figure 17a), the rejection
mechanism of AM signals, either on the L.O. carrier
on entering through the local oscillator port, is readily
understood.

II

L.a.

1F

II
II

II

~ IIII

SIG

II

~ IIII

II
II
II
II

II

e~

~ 1F

ON

a.

b.

SIG

c.
Figure 17.

9-125

LPD·14

~Siliconix

~ incorporated

Likewise, the equivalent circuit in Figure 17b demonstrates how the signal is enhanced at the IF output.
Both local oscillator AM cancellation, as well as signal
enhancement, are dependent upon the precise balance of the IF transformer, as well as on the match
of the four FETs which make up the quad network. In
Figure 17c, the schematic has been rearranged to
show both the local oscillator and the signal input
transformers; the mechanics of Interport isolation
may be easily visualized. Signal excitation provides
an equipotential at the junctions of the local oscillator
transformer and FET pairs AB and CD; in the same
manner, excitation of the local oscillator produced an
equipotential balance at the junctions of the signal
transformer and FET pairs AC and BD.
Harmonic distortion products are reduced by the balance between the signal and local oscillator (inputs)
and the IF (output), where even-integer harmonics of
the signal and local oscillator frequencies are effectively canceled. A sixth-order summary of such products in both single- and double-balanced mixers is
shown in Table 5. Note how the relative densities
agree with Table 1. The effects of harmonic distortion
can be reduced by a judicious selection of the IF
passband response 10. Third-order IMD (Intermodulation Distortion) products are reduced by virtue of the
characteristics of junction FETs, which approximate a
square-law response. Care must be taken in FET
operation, however, to avoid driving the device into
forward conduction by the application of too much
local oscillator power.
Table 5
Comparison of Modulation Products In Single
and Dougle Balanced Mixers to 6th Order
Single-Balanced

Double-Balanced

fs
3 fs
5 fs
f o ± fs

f o ± fs

f o ± 3 fs

f o ± 3 fs

±
2 fo ±
2 fo ±
3 fo ±
fo

±
4 fo ±
S fo ±

3 fo

9-126

5 fs

f o ± 5 fs

fs
3 fs
fs

3 fo
3 fo

±
±

fs

3 fs

5 fo

±

fs

3 fs

fs
fs

Harmonic Distortion, Intermodulation
Products, and Cross-Modulation
Spurious output signals in mixers fall into three categories:
1. Spurious mixer products derived from harmonic
mixing of the signal and local oscillator frequencies;
2.

Two-tone, odd-order intermodulation products;

3.

"Chirping" which arises from undesired mixing
frequencies falling in the IF passband.

The harmonics of a single-signal frequency, when
mixed with the harmonics of the local oscillator, produce spurious outputs which are level-dependent on
the signal amplitude. These products are greatly reduced by the double-balanced mixer, where the even
harmonics are effectively canceled; when FETs are
used, the Taylor-series power expansion falls quickly
to zero above the second order.
However, modulation products of a similar nature will
arise if the broadband down~converting mixer is not
preceded by signal preselection, because of the mixer's equal response to the "image" frequency.
Here, perfectly valid signals will mix with the local oscillator producing interfering i-f signals whose only
difference, when compared to the desired i-f signal,
is that it moves counter to the desired i-f signal when
the local oscillator is shifted.
Two-tone, odd-order 1M products differ markedly
from other spurious signals. This form of harmonic
distortion consists of interactions between two or
more input signals and their respective harmonics. In
turn, these products are mixed with the fundamental
and harmonics of the local oscillator, generating
spurious products which may fall within the IF
passband, on or very near to the desired signal.
Cross-modulation in the active JFET balanced mixer
does not pose a serious problem, provided the signal
input is maintained at a high conductance, which will
occur with source injection. Cross-modulation is very
dependent on and directly related to the impedance
across which the signal is impressed. In the active
JFET double-balanced mixer this impedance is very
low, typical 35 !l. Consequently, the effects of
cross-modulation may be disregarded.

~Siliconix

LPD-14

~, incorporated

In the mixing process of any active device, the value
of the FET drain current may be derived from a
knowledge of the transconductance of the device,
and the impressed signal voltage, ego This is
obtained from the Taylor-series power expansion:
id

= gmeg

+ _1_ Sgm e g2 +
2 I

_1_ S2gm e 3 .
g
31
SVG 2

SVG

_1_
n!

Sn-l gm
egn
SVG n- 1

(24)

which can be reduced to the terms in Table 6.

Table 6
Term
gmeg
_1_

21

Sgm
e g2
SVG

Output

Transfer
Characteristic

Fl, F2

Linear

2 Fl, 2 F2
Fl ± F2

Second-order
Square-law

3 Fl, 3 F2
1

-3-'

Sgm
eg3
8VG 2

2 Fl ± F2
2 F2 ± Fl

Third order

In FET theory, the second and higher-order derivatives of gm are absent, and the device thus offers a
considerable reduction of both intermodulation products and higher-order harmonics. In the double-balanced mixer, where F1 = F2 is the desired result, it is
well to manipulate mixer design and bias conditions
Sgm
to render 8 VG as large as possible, simultaneously
reducing all other terms.

Criteria for FET Selection
For best perfo'rmance in the single-balanced mixer,
matched FET pairs were used. A 10% match in gate
cutoff voltage, VGS(off), saturated drain current,

I DSS, and forward transconductance was sufficient; a
wide selection of junction FET pairs is available for
single-balanced mixer applications. However, in a
double-balanced mixer using a ring-style (quad)
demodulator, the match must be extended to four
discrete devices. Although high forward transconductance remains desirable, the selection of FETs
becomes sharply limited for most users.
Early in the development of the prototype double-balanced mixer, evaluation was made of the potential
effect of physical FET packaging on mixer performance. Four selected discrete JFETs were arranged in
a matrix which was electrically and schematically
identical to the circuit shown in Figure 16. At the
same time, four FET chips were mounted in a TO-116
dual in-line package, with the lead bonds arranged to
form the ring demodulator. Comparison of the two
quad-FET configurations at operating frequencies
through 100 MHz indicated that the single-package
arrangement had definitely superior characteristics.
Physical assembly into the mixer circuit is easier, and
less PC board space is required. Improved
performance was noted on the following parameters:
•

Lower lead inductance

•

Lower distributed capacitance

•

Better isolation

•

Better rejection of AM noise

All of the mixer performance achievements discussed in this presentation have been made with the
single-package quad-FET matrix; it behooves the user to follow this design philosophy, and to limit JFET
candidates for selection to those high-performance
(high transconductance, low capacitance) devices
which are available packaged as matched ring-quad
demodulators.
The FET chips used in the single-package configuration were Siliconix U310s, which offer saturated drain
current, I DSS, of 20 to 60 mA, and a typical forward
transconductance of 14 mmho at VGS = O. Parasitic
chip capacitance averages about 4 pF (C Iss), which
allows for operation well into the UHF region. Taqle 7
shows the performance match achieved when
adjacent chips were selected from the same wafer.

9-127

III

LPD·14

ICrSiliconix

~ incorporated

Table 7

quad JFET source, the local oscillator excitation may
be applied directly at the gates of the FET array.

Quad-FET Chip Matching

A balanced' trifilar-wound toroidal-coil broadband
transformer, exhibiting high even-mode rejection,
provides the balanced drive for the local oscillator excitation of the quad FET gates. The gates of the quad
array have very low conductance; hence there will be
some degree of mismatch to the local oscillator,
which normally could not be tolerated for the signal
port. The high gate impedance, however, allows a
moderate level of local oscillator power to bring
about the necessary gate voltage swing.

VGS(o!!)

IDSS

(V)

(ma)

gfs
(mU)

04720

3.39
3.54
3.53
3.43

29.2
31.0
30.8

13.1
12.8
13.0

29.4

13.1

04724

3.78
3.74
3.84
3.83

35.6
35.3
35.7
37.2

12.6
12.6
12.7
12.6

04728

5.23
5.14
5.03
5.19

53.4
53.3
51.1
53.3

11.6
11.7
11.5
11.8

Quad SIN

All of the quad arrays shown were tested in the mixer
assembly, and all provided a maximum dynamic unbalance of only 0.17 dB, ample proof that the practice of adjacent chip selection is valid for close
matching.
The pin assignments of four JFETs in the 14-pin
TO-116 dual in-line carrier were arranged to avoid
crossovers and maintain sufficient separation between the signal and local oscillator ports to keep
stray coupling leakage to a minimum. Siliconix offers
the U350, a quad-ring demodulator consisting of
matched U310 JFETs.

Local Oscillator Injection
Local oscillator drive for active FET mixers, either
balanced or unbalanced, differs from the drive characteristics of passive diode mixers. For best IMD
performance, the gate of the FET must never be
driven positive with respect to the source - - a case
equivalent to the hard ON condition of the diode.
Consequently, local oscillator drive for the balanced
mixer is less than that required for a passive
balanced mixer with comparable performance
characteristics.
The double-balanced mixer relies on balanced drive
from both the local oscillator and the signal source.
Since conversion efficiency, optimum noise figure,
and good cross-modulation effects can best be
served with the signal entering through the common

9-128

Transformer Design
The design problems encountered in a singlebalanced mixer are compounded in the doublebalanced mixer: the full-wave JFET quad differs
markedly from the half-wave single-balance JFET
pair, in that the quad is represented as a 4-terminal
input structure, while the JFET pair is represented as
a 2-terminal structure. Consequently, the doublebalanced mixer transformer design requires two
separate solutions, each offering entirely different
structures. While each transformer design will be
treated separately, it is important to note the design
goals which are common to both.
The transformers must:
1. Consist of three single-ended terminal pairs, an
input and a balanced output;
2.

Offer a broadband match between the unbalanced input and a symmetrical balanced load;

3.

Maintain (over a wide bandwidth) a differential
phase of 180 0 across the symmetrical balanced
loads; and

4.

Introduce a minimum of insertion loss.

Signal Input Transformer Design
In general, design and fabrication of broadband
transformers has been limited to the popular
ferrite-core varieties derived from transmission-line
theory 11, where exceptional bandwidths are possible.
The more popular transformer designs frequently
result in a 4:1 impedance transformation, as in the
single-balanced mixer or in most trifilar designs.
Other popular transformers offer either simple
constant-impedance phase inversion or unbalancedto-balanced configurations.

terSiliconix

.LII

LPD-14

incorporated

~~

~~
T1
Figure 18. Signal Input Transformer

The JFET quad signal input terminals consists of
shunt pairs of JFET source terminals which offer a
combined load impedance of about 35 n as
contrasted to a 100 n impedance value which would
have suited a 4: 1 transformer. It was thus necessary
to design a broadband unbalanced-to-split-balance
transformer which produced, in effect, a 50 n
asymmetrical input to a 25-0-25 n output.
Such a transformer would require an unbalanced
50 n
input and a symmetrically-balanced output
having near-perfect 180 0 phase differential and an
equipotential, (even-mode) center tap.
Consequetly, a two-step design procedure was indicated.
The first step was to design a transformer which
would provide the unbalanced-to-balanced transition
while maintaining a constant impedance of 50 nand
a 180 0 phase differential across the balanced output,
over a 50-250 MHz band. The design was straightforward, and is shown schematically in Figure 18. The
extra winding was required to complete the
necessary magnetization current path.
Design of the core windings required selection of the
proper ferrite, and establishment of the actual winding length. The latter was resolved to a first-order

approximation by the formulas of Pitzalis (Equations
19 and 20).
Having established the approximate length limits, the
final solution came by experiment. A Hewlett-Packard
8405A vector voltmeter was invaluable during this
phase of the work.
According to Ruthroff the simple balun, to which the
signal input transformer can be most readily compared, is equivalent to "an ideal reversing transformer plus a length of transmission line. If the characteristic impedance of the line is equal to the terminating impedance, the transformer is inherently
broadband." The true equivalent of the Simple
Ruthroff balun is shown in Figure 19, where the
"length of transmission line" is in effect a shunt eleIf
ment
of
characteristic
admittance,
Ys.
Yo = Yin =YA, then it can be shown that Ys = YA,
thus providing a flat admittance transfer through the
transformer 12 . Construction of the "ideal reversing
transformer" required three turns-per-inch of Belden
#24 enamel wire for a characteristic admittance of
0.22 tl'.
Core permeability was established by selection from
three possible choices of -Indiana General ferrite (Q1
for a permeability, I!/I!o of 125; Q2 forl!/I!o = 40;
and Q3 for I! / I!o = 16). Figure 20a provides a performance comparis'on between identically-wound
transformers with different core permeabilities;
Figure 20b shows the effects of winding length on the
selected core, Q2. (Core material Q3 might have offered a better permeability, but its cost was prohibitive). A winding length of 1.5 inches was used for this
first-stage transformer design. An identical length of
single conductor was wound about the core in the

f--l

III

Figure 19. Equivalence of Simple Balun

9-129

LPD·14

.-r-Siliconix

.L;II incorporated

f - 2

183 0

182 0

182 0
181
6[1

........
181

~

0

"'- r--..

180 0

I"""

~

.....

....

........

...... ~2

!'

Illlm

:::1

50

70

100
200 250
Frequency (MHz)

6[1

"""""~

o~ ~
I"~
~

180 0

or--.

177 0
50

~

......

...........
'

0

178

..........

11-I-H-11I--t-I-t--lD

1 - + - + 1

50

70

100
200 250
Frequency (MHz)

-1

"'"
....... 2'
I""".

~X
70

Figure 22. Completed Signal Input Transformer

100
200 250
Frequency (MHz)

b.
Figure 20. Differences In Core Permeability

same winding direction for the magnetization requirements.
The second phase of the signal input transformer design is to provide a circuit that maintains the precise
impedance and phase balance of the reversing transformer, while offering in combination a center-tapped
junction with high even-mode rejection. The transformer was wound after the fashion of Ruthroff's 4:1
ratio impedance design, with 2 inches of twisted pair
wire on a 02 core. The resulting transformer, in combination with the reversing transformer discussed
earlier, provided the degree of phase balance shown
in Figure 21.
The center tap is typically decoupled in excess of
50 dB. The completed signal input transformer is
shown in Figure 22. If the design offers the assurance

9-130

~

179 0

.........,; ~-1.5

179 0
178

..........

180 0

:-....

183 0
182 0

0

Figure 21. Input Transformer Phase Balance

a.

181

183 0

that the center tap will be grounded, then the
magnetization winding may be omitted.

Local Oscillator Input Transformer
Design of the local oscillator transformer is somewhat simpler than that of the signal input transformer, because two design rules may be relaxed.
First, the gates operate at a higher impedance than
that imposed on the sources; thus it is only
necessary to insure that the peak-to-peak voltage
swing at the gates is sufficient for proper FET operation. Second, close impedance match is not so critical as in the signal input transformer, since the local
oscillator excitation is generally derived directly from
a nearby source.
In those situations where the existence of a mismatched load is bothersome (as in high-frequency
operation, where a long coaxial feed will tend to exhibit a "long lines effect" and produce erratic mixer
performance) a simple precaution will avoid the
problem. If the FET gates are clamped with fixed noninductive resistors (value approximately 200 il) to
ground, such loading of the LO transformer secondary will insure a reasonable input match.

~Siliconix

LPD-14

~ incorporated

In the design shown in Figure 23, a simple trifilarwound toroidal-core transformer produced excellent
results. The transformer was constructed from three
strands of Belden #24 enamel wire, twisted to 3 turns
per inch. The trifilar winding, 2 inches long, was
wrapped around an Indiana General F625-9 (CF102)
02 toroidal core. Care must be taken when winding
multifilar transformers with heavy wire, to insure that
the wire is wrapped tightly around the ferrite for good
even-mode isolation and balance.
Simplicity of design of the combined transformers
made detailed analysis of performance unnecessary;
indicators such as isolation and dynamic unbalance
are sufficient to show symmetry for both
transformers and the FET quad.

IN:J::O
II

'---1----'+---0 CT

Figure 23. Local Oscillator Input Transformer

Gaussian Distribution
Noise Envelope
L.a. powerl

I-F
Bandwidth

dB01!-~~~~~11F~:~:~~-LIF~~t!~~
I I
I :
I I

AM Local Oscillator Noise Rejection
Originally, balanced mixers were used for the specific
purpose of canceling spurious AM signals existing on
or about the local oscillator carrier (the function of
the mixer in establishing good inter-port isolation was
a side-effect). These signals could be either spurious
AM signals generated on or about the carrier
(Figure 24) or actual signals existing at the signal
frequency. In the latter case, the signals enter the
mixer through the local oscillator, having found their
way in through some leakage coupling phenomenon.
Regardless of the type or source of AM signals entering through the local oscillator port, the balanced
mixer should effectively reject these signals so that

I I
I I
I I

Pseudo Image

__

Pseudo Signal

Figure 24. Generation of Spurious AM Signals

their products do not occur at the intermediate
frequency. In the early days of balanced mixers, a
20 dB rejection of AM noise was considered good;
today's sophisticated techniques for selection of
dynamically-matched semiconductors can provide
ultimate AM rejection in excess of 30 dB. Figure 25
provides an insight into the degree of AM noise rejection available in the double-balanced mixer.

60
50

(For the prototype mixer feasibility study, relatively
large ferrite cores were used, as a matter of winding
convenience. The practice of using large cores, however, can lead to excessive transformer losses,
resulting in degraded mixer efficiency, high noise
figures, high LO drive requirements and reduced
gain. For best results, cores no larger than those
commonly used in the CATV industry should be
chosen).

I-F
Bandwidth

V DD = -20V
VGSO= 1/2 V p
P LO = -15 dBm

- .....

AM
40
Noise Rejection
(dB)
30

i"'-o I'"

-

./

-'

r-..

\

20
10

o

50

70

100
Frequency (MHz)

200 250

Figure 25. AM Noise Rejection In Double-Balance
Mixer

(Insofar as FM noise is concerned, it should be noted
that no mixer is capable of rejecting frequencymodulated signals entering through the local oscillator).
An interesting point not generally considered in discussions of balanced mixers is that the dynamic
range of the mixer can be limited by the conversion
of local oscillator noise into the intermediate
frequency, which tends to blank out a weak signal
and place a bottom on sensitivity.

9-131

~

..

g

LPD·14

Siliconix

incorporated

Interport Isolation

\

50

Like AM noise rejection and dynamic unbalance, interport isolation is very dependent on mixer balance
(symmetry). Matching aspects of the JFET quad array and the phase/amplitude balance of the signal
input and local oscillator input transformers play im-

Interport
Isolation
(dB)

portant roles in Bchieving interport isolation. Capaci-

~

r-.... ......
ioo,;..

1:111111111
o

0.2
0.4
0.6
0.6
Dynamic Unbalance (dB)

fl

Figure 26. AM Noise Rejection In Double-Balance
Mixer

Interport isolation was also enhanced in the prototype
mixer through careful parts layout. As a measure of
the overall effects of unbalance, a quantitative measurement of interport isolation vs dynamic unbalance
is made in Figure 26.
In Figure 27, the interport isolation between the local
oscillator and signal input ports is shown to be 35 dB
typically.

f'

30
20

tive and magnetic coupling between the transformers
add to problems of interport isolation in balanced
mixers.
(In the prototype mixer, the JFET quad was packaged
in a 14-pin dual in-line housing, as a matter of construction convenience.) The U350 is recommended
for double-balanced mixer designs.

\

40

60
50

V DD =-20V
Vaso = 1/2Vp
P LO = -15 dBm

40
Isolation
(dB)

........

30

.......-. ~

20

Dynamic Unbalance

10

o
Dynamic unbalance may be regarded as another expression for AM noise rejection, except that the latter
does not provide a ready insight into the effects of
symmetry, balance, and quad matching.
Dynamic unbalance also affects the intermodulation
distortion performance of the mixer. As the unbalance approaches a degree of true balance, the IMD
tends to optimize; conversely, when unbalance is excessive the IMD approaches an asymptotic state.
This effect is shown in Figure 28.

Designing the IF Network

50

70

Figure 27. Interport Isolation

-

o

;-...

Incremental Decay
(dB)
In 3rd Order -1.0
IMD Intercept

r-....~

I"- r--....

-2.0

"

"-

-3.0

The IF network performs three important functions in
the FET double-balanced mixer. As with the singlebalanced mixer, it provides for best match between
the quad FETs and the intermediate frequency
amplifier; it effectively bypasses the RF components
(signal and local oscillator); and unique to the
double-balanced mixer, it provides a reduction of
simple harmonic distortion, by virtue of its balance.

100
200 250
Frequency (MHz)

o

0.2
0.4
0.6
0.6
Dynamic Unbalance (dB)

~
1.0

Figure 2B. Dynamic Unbalance vs. Incremental
Decay

\~--------------------------------------------------------------------------9-132

fCrSiliconix

LPD-14

~ incorporated

Selection of the dynamic drain impedance value in
the IF network is a critical point in the design of the
structure. Both 1M product distortion and crossmodulation will be affected by the instantaneous
peak-to-peak voltage of the FETs If the dynamic drain
impedance allows the signal peaks to enter either the
pinchoff or breakdown voltage regions of the transistors. Here another design tradeoff must be considered. If the impedance is too high, the dynamic
range of the mixer will be limited; if the impedance is
too low, useful conversion gain will be sacrificed, as
shown in Figure 29.

2 Tone
40
3rd Order IMD
Intercept Point
30 H-+-I-:::;looo1'S1--1'-::'E:-lrl;..-I;i:
(dB)

HBHill

~.~, ] I
6

Figure 29.

8

10

12 14 16
PLD(dBm)

18

20

Gain and IMD vs. Local Oscillator Drive

Mixer Performance
Quad FET arrays with both high and low pinchoff voltage levels were used in evaluation of the active double-balanced mixer; the prototype mixer exhibited
clearly superior characteristics, compared to equivalent small-signal passive double-balanced mixers.
The low- to medium-level pinchoff voltage quad FET
array performed slightly better than the high-level
pinchoff devices (5.5 V), solely because of a limitation in available local oscillator power. Performance
of several types of mixers is made in Table 8.

Conclusion
It may be concluded that performance of the active
double-balanced mixer contributes overall system
gain in areas critical to telecommunications practice,
and reduces associated amplifier requirements.

SECTION 3: A COMMUTATION DOU·
BLE·BALANCED MOSFET MIXER OF
HIGH DYNAMIC RANGE
INTRODUCTION
Heretofore, most mixers sporting a high dynamic
range have been either the passive diode-ring variety
- available from numerous vendors - or the active
FET mixer. The latter is often implemented, using
either the Siliconix U31 0 or the Siliconix U350, as described in Sections 1 and 2.
Common to both the diode and FET is their squarelaw characteristic so important in maintaining low distortion during mixing. However, equally important for
high dynamic range is the ability to withstand overload that has been identified as a principle cause of
distortion in mixing 13. Some passive diode-ring mixer
designs have resorted to paralleling of diodes to
effect greater current handling, yet the penalty for
this apparent improvement is the need for a massive
increase in local-oscillator power.
Here we examine a new FET mixer where communication achieves high dynamic range without exacting
the anticipated penalty of increased local-oscillator
drive. Using the Siliconix Si8901 monolithic quad-ring
small-signal double-diffused MOSFET, third-order intercept points upward of +39 dBm (input) have been
achieved with only +17 dBm of local-oscillator drive.
A comparison between the Si8901 double-balanced
mixer and the conventional diode ring doublebalanced mixer is offered in Figure 30 where we see
an order-of-magnitude improvement in performance
at local-oscillator power levels substantially lower
than heretofore possible with the conventional mixer.

Conversion Efficiency Of The Commutation
Mixer
Unlike either the conventional diode-ring mixer or the
active FET mixer, the commutation mixer relies on
the switching action of the quad-FET elements to
effect mixing action. Consequently, the commutation
mixer is, in effect, no more than a pair of switches
reversing the phase of the signal carrier at a rate determined by the local-oscillator frequency. Ideally,
we would anticipate little noise contribution, and

9-133

LPD-14

.-:rSiliconix

~ incorporated

Table 8
Comparison Between Active, Passive, and MOSFET Double-Balanced Mixers
Active
FET

Characteristic
Frequency Range (MHz)

Passive
Low-Level

Passive
High-Level

MOSFET
Switch

50-250

0.5-500

0.5-500

0.2-100

45

Unknown

Unknown

Unknown

AM Local Oscillator Noise Rejection (dB)

0.15

Unknown

Unknown

Unknown

Isolation RF-Local Oscillator (dB)

35

35

40

30

Isolation Local Oscillator - RF (dB)

60

25

30

25

Overall Noise Figure (SSB) (dB)

8.0

8.5

8.5

9.0

Local Oscillator Drive Level (dBm)

+15

+7

+17

+30

Two-Tone IMD Intercept Point- (dBm)

+34

+15

+28

35

Conversion Gain (db)

+4

-8

-8

-8

1 dB Compression (dBm)

+13

+1

+8

+29

Desensitization Level- - (dBm)

+13

+1

+8

+29

Dynamic Unbalance (dB)

- Output - measured at recommended LO drive level.
The level for a nearby unwanted signal (separated 200 kHz) to compress a desired signal of -15 dBm by 1 dB.

since the switching mixer - consisting of four MOSFET
"switches" - has finite ON-state resistance, performance is similar to that of a switching attenuator, As a
result, the conversion efficiency of the commutation
mixer may be expressed as a loss.

40
3rd Order
Input
30
Intercept Point
(+dBm)
20

_ISI890~ DB~

/

, ..,....,

10

o

J..

~ ::::J!350 D~ ... ...

o

5

-

..... ~de~lngDBM

10
15
20
25
30
Power Local Osc. (+dBm)

are, however, ways to reduce the effects of
undesired frequency generation by filtering.
The effect of rDS of the MOSFETs may be determined
from the analysis of the equivalent circuit shown in
Figure 31, assuming that our local oscillator wave
form is an idealized square wave. It is not, but if we
assume that it is, our analysis is greatly simplified;
and for a commutation mixer, a high local-oscillator
voltage begins to approach the ideal waveform of a
square wave.
rOFF

35

~

Figure 30. Performance Comparison of Double
Balanced Mixers

This loss results from two related factors. First, is the
rDS of the MOSFET relative to the signal impedance
(Rg) and intermediate frequency (IF) impedance
(RL); second - and a more common and expected
factor - is the loss attributed to signal conversion to
undesired frequencies. The latter signal conversion
involves the image and harmonic frequencies. There

9-134

I rYY"n
I
I V L Sin wct I

rOFF
Figure 31.

Equivalent Circuit of Communication
Mixer

~SilicDnix

LPD-14

~ incorporated

Figure 31, showing switches rather than MOSFETs,
also identifies the ON-state resistance, rDS, as well
as the OFF-state resistance, rOFF . The latter can be
disregarded in this analysis as it is generally extremely high (2 • 109 .0.). On the other hand, the ONstate resistance, rDS, together with the source and
load impedances (i.e. signal and intermediate-frequence impedances) directly affects the conversion
efficiency.
If we assume that our local-oscillator excitation is an
idealized square wave, the switching action may be
represented by the Fourier series as,
00

=

f(x)

1

2

+-1.

L:

'IT

n

=1

_ VIN2

P av

(26)

4R g

or, in terms shown in Figure 33

(27)

the output power, deliverable to the intermediatefrequency port, is
(28)

Pout

sin(2n - 1) wt

(25)

(2n - 1)

The switching function, E(t), shown in the derivative
equivalent circuit of Figure 32, is derived from the
magnitude of this Fourier series expansion as a
power function by squaring the first term, i.e.

rDS
9---~~-----~~--~Vo

(21 'IT )2 •

A

+1

0

2'IT

'IT

wt

0

Figure 33. The Power-Loop Circuit with All Elements
Equivalent Based on the Transfer
Function. E(t) = ...1.
'lT2

'--

-1

To arrive at V o , we first need to obtain the loop current, i L, which from Figure 33 offers

r-------..,
E(t)

,-----<1>---.., v0

iL

=

~(Rg+ rDS) + RL + rDS

(29)

4
then

Vo

= ___V--!!.!ln....;R..:.!L~_ _ __
~(Rg+ rDS)

L. _ _ _ _ _ _ _ .J

Figure 32. Derivative Equivalent Circuit

The available power that can be delivered from a
generator of RMS open-circuit terminal voltage, VIN,
and internal resistance, Rg , is

(30)

4

Combining Equations 28 and 30,

(31)

9-135

LPD·14

crSiliconix

~ incorporated

Conversion efficiency - in the case for the commutation mixer. a loss - may be calculated from the ratio
of Pav and Pout
4~l~--~~~~~~~~--t-~

Lc= 10 Log

~ dB

(32)

Lc(d8)

Pout

~~~

;111

o
Substituting Equation 27 for P avo and Equation 31 for

2

4

6

8

10

12

14

16

18

Rg/rDS

Pout. we obtain
Figure 34. Insertion Loss As A Function of rDS. RL& Rg

The conversion loss represented by Equation 33 is
for a broadband double-balanced mixer with the image and sum frequency (RF + La) ports shorted and
the signal frequency (RF) matched to the characteristic line impedance. The ideal commutating mixer
operating with resistive source and load impedances
will result in having the image and all harmonic
frequencies dissipated. For this case. the optimum
conversion loss reduces to

Lc = 10 Log

£4

dB

(34)

or -3.92 dB

However. a truly optimum mixer also demands that
the MOSFETs exhibit an ON-state resistance of zero
ohms and. of course. an ideal square-wave excitation. Neither is possible in a practical sense.
Equation 33 can be examined for various values of
source and load impedances as well as ros by
graphical representation. as shown in Figure 34. remembering that a nominal 3.92 dB must be added to
the values obtained from the graph.

9-136

To illustrate how seriously the ON-state resistance of
the MOSFETs affects performance. we need only to
consider· the
Si8901
with
a
nominal ros
(at VGS = 15V) of 23 il. With a 1:1 signal transformer
(50 to 25-0-25 il). Rg Iros = 1.1. Allowing a 4: 1 IF
output transformer to a 50-il preamplifier. the ratio
RL/rOS approximates 4. From Figure 34 we read a
conversion loss. Le. of approximately 3.7 dB. to
which we add 3.92 dB for a total loss of 7.62 dB.
Additionally. we must also include the losses incurred
by both the signal and IF transformers. The result
compares favorably with measured data.
A careful study of Figure 34 reveals what appears as
an anomalous characteristic. If we were to raise
Rg/ros from 1.1 to 4.3 (by replacing 1: 1 transformer
with a 1:4 to effect a Signal-source impedance of
100-0-100 il) • we would see a dramatic improvement
in conversion efficiency. The anomaly is that this
suggests that a mismatched signal-input port improves performance.
Caruthers 14 first suggested that reactively terminating all harmonic and parasitic frequencies would reduce the conversion loss of a ring demodulator to
zero. This. of course. would also require that the active mixing elements (MOSFETs in this case) have
zero ros. in keeping with the data of Figure 34.
A double-balanced mixer is a 4-port - consisting of a
signal. image. IF. and a local-oscillator port. Of
these. the most difficult to terminate is the image frequency port simply because. in theory. it exists as a
separate port. but in practice it shares the signal
port. Any reactive termination would. therefore. be
narrow-band irrespective of its proximity to the active
mixing elements.

~Siliconix

LPD·14

~ incorporated

The performance of an image-termination filter offering a true reactance to the image frequency (100%
reflective) may be deduced to a reasonable degree
from Figure 34, if we first presume that the conversion loss between signal and IF compares with that
between signal and image. The relationship is
displayed in Figure 35 where we see the expected
variation in amplitude proportional to conversion
efficiency (inversely proportional to conversion loss).
Image-frequency filtering affects more than conversion efficiency. As the phase of the detuned-short
position of the image-frequency filter is varied, we
are able to witness a cyclical variation in the intermodulation distortion as has been confirmed by
measurement, shown in Figure 36. By comparing
Figure 35 with Figure 36, we see that any improvement in conversion loss appears to offer a corresponding degradation in intermodulation distortion I
0.6
0.4
0.2

+
"La
(dB)

0.2

62

,,-,

,

Measured Data
Point

,/-V

\

I

\

56

I

\
\

I

\

-•

(35)

\

60
56

The most damaging intermodulation distortion (IMO)
products in receiver design are generally those attributed to odd-order and, in particular, those identified as the third-order IMO.

There are both fixed-level IMO products and leveldependent IMO products. The former are produced
by the interaction between a fixed-level signal, such
as the local oscillator and the variable-amplitude signal. The resulting frequencies may be identified by

Figure 35. Effect of Image Termination on
Conversion Loss

"

Identifying Intermodulation Distortion
Products

The second-order term is the desired intermediate
frequency we seek, all other higher-orders are undesirable but, unfortunately, are present to a varying
degree.

0.6

IMD
(dB)

In the ideal mixer, the input signal is translated to an
intermediate frequency without distortion, that is
without imparing any of the contained information.
Regrettably, the ideal mixer does not occur in practice. Because of certain non-linearities within the
switching elements (MOSFETs in this case) as well as
imperfect switching resulting in phase modulation,
distortion results.

Earlier, in Equation 24, we saw that any non-linear
device may be represented as a power series which
can be reduced to the terms shown in Table 6.

0

0.4

64

Unbalanced, single-balanced, and double-balanced
mixers are distinguished by their ability to selectively
reject spurious frequency components, as defined in
Table 5. The double-balanced mixer, by virtue of its
symmetry, suppresses twice the number of spurious
frequencies as the single-balanced mixer suppresses.

\

,

wt

I

\
\

-'

where, n is an integer greater than 1.
Level-dependent IMD products result from the interaction of the harmonics of the local oscillator and
those of the signal. The resulting frequencies may be
identified by

Figure 36. Effect of Image Termination on 3rd-Order
Distortion

Intermodulation Distortion

(36)
where, m and n are integers greater than 1.

9-137

iii

.:r-Siliccnix

LPD·14
For a mixer to generate IMD products at the intermediate frequency, we must account for at least a twostep process. First, the generation of the harmonics
of the signal and local oscillator; and second, the
mixing or conversion of these frequencies to the intermediate frequency. Consequently, the mixer may
be modeled as a series connection of two non-linear
impedances, the first to generate the harmonic products and the second to mix or convert to the intermediate frequency. Although many harmonically-related
products are possible, we will focus principally on the
odd-order IMD products.
If we allow two interfering signals, fl and f2, to impinge upon the first non-linear element of our mixer
model, the result will be 2fl - f2 and 2f2 - fl. These
are identified as third-order intermodulation products
(IMD3)' Other products are also generated taking the
form 3fl - 2f2 and 3f2 - 2fl, called fifth-order IMD
products (IMD5)' Unlike the even-order products,
odd order products lie close the the fundamental
signals and, as a consequence, are most susceptible
to falling within the passband of the intermediate
frequency and thus degrading the performance of
the mixer.
A qualitative definition of linearity based upon intermodulation distortion performance is called the intercept point. Convergence occurs when
•

the fundamental output (IF) response is directly
proportional to the signal input level;

•

the second-order output response is proportional
to the square of the signal input level; and,

•

the third-order o,utput response is proportional to
the cube of the signal input level.

The point of convergence is termed the intercept
point. The higher the value of this intercept point, the
better the dynamic range.

~ incorporated

on a varying non-linear, voltage-dependent capacitance (not shown in Figure 37). Although the effects
of this sinusoidal transition are not easily derived,
Ward 17 and Rafuse 18 have concluded that lowering
Rg will provide improved intermodulation performancel This conflicts with low conversion loss, as we
saw in Figure 34, but agrees with Equation 37.

(37)

where,
Vc is the peak-to-peak local-oscillator voltage,
Vs is the peak signal voltage,
tr

is the rise and fall time of Vc,

WLO

is the local-oscillator frequency.

Further examination of Figure 37 reveals that the
sinusoidal local-oscillator excitation results in phase
modulation. That is, as the sinusoidal wave goes
through a complete cycle, the resulting gate voltage,
acting upon the MOSFET's tranfer characteristic,
produces a resulting non-linear waveform. Since all
FETs have some offset - a JFET has cut-off voltage,
and a MOSFET has threshold voltage - it is important,
Transform
Function

Resultant I-F
Waveform

otLI.----.....:-wt

Intermodulation Distortion in the Commutation Mixer
Although the double-balanced mixer outperforms the
single-balanced mixer as we saw in Table 5, a more
serious source of intermodulation products results
when the local-oscillator excitation departs from the
idealized square wave 15 , 16. This phenomena is easily recognized by a careful examination of Figure 37,
where a sinusoidal local-oscillator voltage reacts not
only upon a varying transfer characteristic but also

9-138

Figure 37. Effect of Sinusoidal LO. Waveform on
I-F linearity

.:r-Siliconix

LPD·14

~ incorporated

both for symmetry as well as for balance, to offer
some dc offset voltage to the gates. Optimum IMD
performance demands that the switches operate in a
50% duty cycle; that is, the switches must be fully ON
and fully OFF for equal time. Without some form of
offset bias, this would be extremely difficult unless
we were to implement an idealized square-wave
drive.
Walker 19 has derived an expression showing the predicted improvement in the relative level of two-tone
third-order intermodulation products (IMD3) as a
function of the rise and fall times of the local-oscillator waveform.
Equation 37 offers us several interesting aspects on
performance. Since any reduction in the magnitude
of Ys improves the IMD, we again discover that by
lowering Rg (which, in turn, decreases the magnitude
ofYs) appears to benefit performance. Second, the
higher the local-oscillator voltage, the better the IMD
performance. Third, if we can provide the idealized
square-wave drive, we achieve an infinite improvement in IMD performance I
An additional fault of sinusoidal local-oscilaltor excitation results whenever the wave approaches the zerocrossing at half-period intervals. As the voltage
decays, we find that any signal voltage may overload
the
MOSFETs
causing
intermodulation
and
crossmodulation distortion 20 . This can be easily visualized from Figure 38 where we see the classic i-e
characteristics of the MOSFET at varying gate
voltages. Only at substantial gate voltage do we witness reasonable linearity and, consequently, good
dynamic range.
10 (mA)

16 V ,

50

III
fI

_J !L

4V

IV
V
V

-50
-5

In any receiver, performance can be quantified by
the term dynamic range. Dynamic range can be extended by improving the sensitivity to low-level signals and by increasing the power handling ability without being overcome by interfering intermodulation
products or the effects caused from desensitization.
There are rules to follow if we are to improve the lowlevel signal sensitivity. Ideally we would like a mixer to
be transparent, acting only to manipulate the incoming signals for easy processing by subsequent equipment. The perfect mixer would have no conversion
loss and a low noise figure. However, in the preceding analysis we discovered that optimum intermodulation performance occurred when the signal input port is mismatched to the quad MOSFETs
(Figure 34). It now becomes clear that a performance trade-off appears necessary. Either we seek
low conversion loss and with it a higher noise figure,
or we aim for the highest two-tone third-order intercept point. Fortunately, as we seek the latter, our
dynamic range will actually improve since a mismatched signal port has less effect upon the signalto-noise performance of the mixer than does a
matched signal port have upon intermodulation
distortion.
Convention has identified minimum sensitivity to be
the weaker signal which will produce an output signal
that is 10 dB over that of the noise in a prescribed
bandwidth (usually 1kHz), or

OV

A

Sens.

/1/1
VI rJ/

/

As the two-tone intercept point increases in magnitude, we generally expect a like improvement in dynamic range results. Yet, as we have concluded
from earlier study, the intermodulation products appear to be a function of both the generator or source
impedance as well as ratio Rg/ros and RL/rOS
(Figure 34).

12 V_" 8V
,/

/1
a

Dynamic Range Of The Commutation Mixer

= 20

Log Ys + YN + dB
YN

(38)

III

/ Ifil
/

1/

Vas

a

1.dlv

5
(V)

Figure 38. First & Third Quadrant I-E
Characteristics Showing Effect of Gate
Voltage Leading to Large-Signal Overload
Olstortion

Desensitization occurs whenever a nearby unwanted
signal causes the compression of the desired signal.
The effect appears as an increase in the mixer's
conversion loss.

9-139

.HSiliconix

LPD·14

incorporated

The Si8901 As A Commutation Mixer

importance, is to properly terminate the parasitic and
harmonic frequencies developed by the mixer.

Because of package and parasitic constraints, the
Si8901 is best suited for performance in the HF to low
VHF region. A surface-mount version may extend
performance to somewhat higher frequencies.

Establishing the Gating Voltage

In our review of intermodulation distortion, we recognized that to achieve a high intercept point the localoscillator drive must
•

approach the ideal square-wave,

•

ensure a 50% duty cycle,

•

offer sufficient amplitude to ensure a full ON and
OFF switching condition, as well as to offer reduced rDS when ON.

Furthermore, to maintain superior overall performance - both in conversion loss, dynamic range (noise
figure) and intercept point - some form of image-frequency termination would be highly desirable even
though, understandably, the mixer's bandwidth
would be restricted.
Consequently, the principal effort in the design of a
high dynamic range commutation mixer is two-fold.
First, and most crucial, is to achieve a gating or control voltage sufficient to ensure a positive and hard
turn-ON as well as a complete turn-OFF of the mixing
elements (MOSFETs). Second, and of lesser

Local oscillator injection to the conventional diode
ring, FET, or MOSFET double-balanced mixer is by
the use of the broadband, transmission-line transformer, as shown in Figure 39. For the diode-ring
mixer where swiiching is a funclion of ioop currem,
or for active FET mixers that operate on the principle
of transconductance and thus need little gate voltage, the broadband transformer is adequate. If this
approach is used for the commutation mixer, we
would need extraordinarily high local-oscillator drive
to ensure positive turn-ON. Rafuse and Ward used a
minimum of 2 W to ensure mixing action; Lewis and
Palmer achieved high dynamic range using 5 Watts!
The MOSFETs used in these early designs were pchannel, enhancement-mode (2N4268 devices with
moderately high threshold (6 V maximum) and high
input capacity (6 pF maximum). All of these early
MOSFET double-balanced mixers relied on the conventional 50 to 100-0-100 .n transformer for local-oscillator injection to the gates.
A major goal is the conservation of power. This goal
cannot be achieved using the conventional design.
Simply increasing the turns ratio of the coupling
transformer is thwarted by the reactive load presented by the gates.

Signal

~
I.F.

'-------{I:JJI. F .

Figure 39.

9-140

Local Oscillator Drive Using Conventional Broadband Transformers

fCrSiliconix

LPD·14

~ incorporated

The obvious solution is to use a resonant gate drive.
The voltage appearing across the resonant task - and
thus on the gates - may easily be calculated.

v

= (P • Q • X) 1/2

(39)

Where, P is the power delivered to the resonant tank
circuit,
Q is the loaded Q of the tank circuit, and

Figure 41.

Resonant - Gate Drive. T2 is Tuned to
Resonate with C g5 of Si8901

X is the reactance of the gate capacity.
Since the gate capacitance of the MOSFET is voltage
dependent, the reactance of the gate becomes dependent upon the impressed excitation voltage. To
allow this would severely degrade the IMO performance of the mixer. However, we can minimize the
change in gate capacitance and remove its detrimental influence using a combination of substrate and
gate bias, as shown in Figure 40. Not only does this
show itself beneficial in this regard, but as we saw in
Figure 37, a gate bias is necessary to ensure the
required 50% duty cycle. Furthermore, a negative
substrate voltage ensures that each MOSFET on the
monolithic substrate is electrically isolated and that
each source-/drain-to-body diode is sufficiently reverse biased to prevent half-wave conduction.

~G

--=:J"!'"L

vGG

v BS

Xc

V

0

~

-

I--

o

-1

-2

-

t--

-3

-4

-5

-

-6

To ensure symmetrical gate voltage in 180-degree
anti-phase, if the local-oscillator drive is asymmetrical, i.e., fed by unbalanced coax, an unbalanced-tobalanced balun must be used (T1 in Figure 41);
otherwise, capacitive unbalance results with an
attendant loss in mixer performance.
Table 9 offers an interesting comparison between a
resonant-gate drive with a loaded tank Q of 14 and a
conventional gate drive using a 50 to 100-0-100 n
transformer. The importance of a high tank Q is
graphically portrayed in Figure 42. The full impact of
a high gate voltage swing can be appreciated by using Equation 37. Here, as Vc (gate voltage) increases the intermodulation performance (IMO) also
improves, as we might intuitively expect. Calculated
and measured results are shown in Figure 43 and
demonstrate reasonable agreement. The difference
may reflect problems encountered in measuring Vc
as any probe will inadvertently load, or detune, the
resonant tank even with the special care that was
taken to compensate.

~

Table 9

4V
6 V

-7

-8

Power
in
(mW)

NR Gate
Voltage
(V)

Res Gate
Voltage
(V)

10
20
30
60

0.20
0.29
0.33
0.44

5.4

VBS(V)

Figure 40.

Effect of Bias on Gate Reactance

Implementing the resonant gate drive may take any
of several forms. The resonant tank circuit may be
merged with the oscillator, or it can be varactortuned Class B stage, or as in the present design, an
independent resonant tank, shown in Figure 41.

7.7
9.4
13.3

Comparison of a-c gate voltage versus localoscillator drive between a non-resonant (NR)
and resonant (Res) tank with a loaded Q of 14
(Freq. 150 MHz)

9-141

LPD-14

.:r-Siliconix

~ incorporated

If we have the option to choose "high side" or "low
side" injection - Le., having the local-oscillator frequency above (high) or below (low) the signal
frequency - a closer inspection of Equation 37 should
convince us to choose low-side injection.
25

g=5PF
fLO = 150 MHz
~

__ I~--~II---+----I----:7"'f-

20

does affect performance - for high-side local-oscillator injection, an elliptic-function low-pass filter, or for
low-side injection, a high-pass filter might offer
worthwhile improvement. In either case, the filter offers a short-circuit reactance to the image frequency
forcing the image to return once again for demodulation. The results of using a low-pass filter with the
prototype commutation mixer are known from our
eariier examination of Figures 35 ana 36.

Gate
Voltage
(V)

30
40
Power L. O. (mW)

20

10

Figure 42.

50

60

Influence of Loaded Q on Gate Voltage
L.O. Power

VS.

40

\\

50

IMD
60
Referred
to Signal
(dB)
70

Calculated (Eq. 14)
Measured
...• fLO
= 150 MHz
PSIG

'\

o

Figure 43.

= 0 dBm

~

80

90

Figure 44. Mask Layout PCM Prototype
Commutation Mixer

5

The resonant-gate drive consisting of a high-Q tank
offers adequate bypassing of the intermediate
frequency and image frequency.

~

'~

~

10
15
Gate Voltage (V)

20

If the IF port is narrow band, filtering may be possible
by simply using a resonant L-C network across the
primary of the transformer.

~
25

Effect of Gate Voltage on IMD
Performance

Terminating Unwanted Frequencies
If our mixer is to be operated over a restricted frequency range where the local oscillator and signal
frequencies can be manipulated, image-frequency
filtering may be possible. Image-frequency filtering

9-142

Design Techniques in Building the Mixer
The mixer was fabricated on a high-quality doublecopper clad board shown in Figure 44. An improvised
socket held the Si8901.
The Signal and IF ports used Mini-Circuits, Inc., plastic T-case RF transformers. For the intermediate
frequency, the Mini-Circuits T4-1 (1 :4) was used; for
the Signal, the Mini-Circuits Tl-H (1 :1) was used.
The resonant tank was wound on a one-quarterinch-diameter ceramic form with no slug. The
unbalanced-ta-balanced resonant tank drive used a
T4-1. The schematic diagram, Figure 45, is for a
commutation mixer, operating with an IF of 60 MHz.

.:rSiliconix

LPD·14

~ incorporated

The principle effort involved the design of the resonant-gate drive. This necessitated an accurate
knowledge of the gate's total capacitive loading effect. To accomplish this, a precision fixed capacitor
(5 pF) was substituted for the Si89al, and at resonance, it was a simple matter to calculate the inductance of the resonant tank. Substituting the Si89al
made it again a simple task to determine the
capacitive effects of the Si89al. Once known, a
high-Q resonant tank can be quickly designed and
implemented. To ensure good interport isolation,
symmetry is important, so care is necessary in
assembly to maintain mechanical symmetry, especially with the primary winding.

Performance of the Si8901 Prototype
Commutation Mixer
The primary goal in developing a commutation double-balanced mixer is to achieve a wide dynamic
range. If this task can be accomplished with an attendant savings in power consumption, then the resulting mixer design should find wide application in HF
receiver design.

•

desensitization level

•

noise figure

Conversion loss and the intercept point are directly
dependent upon the magnitude of the local-oscillator
power. The prototype mixer's performance is offered
in Figure 46, where the input intercept and conversion loss are plotted.
Both the compression and desensitization levels may
appear to contradict reason. Heretofore, conventional diode-ring demodulators exhibited compression and desensitization levels an order of magnitude
below the local-oscillator power level. However, with
a commutation MOSFET mixer, switching is not accomplished by the injection of loop current but by the
application of gate voltage. At a local-oscillator
power level of + 17 dBm (50 mW), the 2-dB compression level and desensitization level were
+30 dBm!
The single-sideband HF noise figure of 7.95 dB was
measured at a local oscillator power level of
+17dBm.

The following tests were performed.
•

conversion efficiency (loss)

•

two-tone, 3rd order intercept point

•

compression level

SI8901

,----,

COOllq
T4 - 1

L-------r-----~

L----r--~~--o+vGG

I680

pF

b

to Vu ':"
.----uL.U~T-4-_-1

HI''';;
Figure 45. Prototype Commutation Double-Salanced Mixer

9-143

LPD·14

..:rSiliconix

~ incorporatec

technology the tuning can be accomplished by
numerous methods. not the least of which might be
electronically using varactors. The resonant tank also
may take several forms. It can be part of the oscillator. it can be varactor-tuned driver electronically
tracking the local oscillator21 •

CONCLUSION
Achieving a high gate voltage to effect high-level
switching by means of a resonant tank is not a handicap. Although one might. at first. label the mixer as
narrow-band. in truth the mixer is wide-band. For the
majority of applications. the intermediate frequency
is fixed. that is. narrow band. Consequently. to receive a wide range of signal frequencies. the local
oscillator is tuned across a similar band. In modern

If the local-oscillator drive was processed to offer a
more rectangular waveform. approaching the idealized square wave. we might then anticipate even
greater dynamic range as predicted by Equation 37.

39

/

38

V

37
36
35
2 Tone.
3rd Order
Intercept Point
(dBm) (Input) 34

/

33

-10

-8

"""'Ii

J

32

-6

/

31

o
o

10
+10

Conversion
Loss
(dB)

-4

/

30
29

/

I

V

.-

-2

20
+13

30
+15

40
+16

50
+17

60
+18

0
mW
dBm

Figure 46. Intercept Point & Conversion Loss

References
1.

Pound. R. V .• Microwave Mixers (1948) MIT Rad. Lab. Series. Vol. 16. Fig. 6.14.

2.

Compton. J. B.• "High Frequency JFET Characterization and Applications." Design Electron/cs.
March. 1970.

3.

Sabin. Wm .• "The Solid State Receiver." QST. July 1970.

4.

Penfield. P. and R. Rafuse. Varactor Applications (1962) MIT Press. pp. 73ff.

5.

Vogel. J. S .• "Non-Linear Distortion and Mixing Processes in FETs." Proc. IEEE. Vol. 55.
No. 12 (1967).

9-144

tlCrSiliconix

~ incorporated

6.

Ruthroff, C. L., "Some Broadband Transformers," Proc. IRE, Vol. 47, No.8 (1969).

7.

"UHF FET Mixer of High Dynamic Range," ECOM-0503-P005-G821 (1969).

8.

Will, Peter, "Reactive Loads - The Big Mixer Menace," Microwaves, April 1971.

9.

McVay, F. C., "Don't Guess the Spurious Level," Electronic Design, Feb. 1, 1967.

LPD·14

10. Hoigaard, J. C., "Spurious Frequency Generation in Frequency Converters," Microwave Journal,
Julyl August 1967.
11. Pitzalis, O. and T. Couse, "Broadband Transformer Design for RF Power Transistor Amplifiers,"
Proceedings Electronic Components Conference, 1968.
12. Mattaei, G. L., Young, L., and E. M. T. Jones, Microwave Filters, Impedance Matching Networks
and Coupling Structures (1964) McGraw-Hili.
13. Walker, H. P., "Sources of Intermodulation in Diode-Ring Mixers," The Radio and Electronic Engineer,
Vol. 46, No. 5 (1967).
14. Caruthers, R. S., "Copper Oxide Modulators in Carrier Telephone Repeaters," Bell System Technical
Journal, Vol. 18, No.2 (1939).
15. Lewis, H. D. and F. I. Palmer, "A High Performance HF Receiver," R.C.A. Missiles & Surface Radar
Dlv. Report (Nov. 1968).
16. Walker, H. P., op. cit.
17. Ward, Michael John, "A Wide Dynamic Range Single-Sideband Receiver,' MIT"MS Thesis (Dec. 1968).
18. Rafuse, R. P., "Symmetric MOSFET Mixers of High Dynamic Range," Digest of Technical Papers,
1968 Int'I. Solid-State Circuits Conference.
19. Walker, H. P. op. cit.
20. Gardiner, John G., "The Relationship Between Cross-Modulation and Intermodulation Distortions in the
Double-Balanced Modulator," Proc. IEEE Letters (Nov. 1968).
21. "Electronically Controlled High Dynamic Range Tuner," Final Report (June 1971) ECOM-0104-4 R&D
Tech. Report, AD887063L.

iii

9-145

.-rSiliconix

~ incorporated

THE FET CONSTANT·CURRENT SOURCE
INTRODUCTION
The combination of low associated operating voltage
and high output impedance make the FET attractive
as a constant-current source. An adjustable-current
source (Figure 1) may be built with a FET, a variable
resistor and a small battery. For good thermal stability, the FET should be biased near the zero temperature coefficient point.

RS

A change in supply voltage or a change in load impedance, will change I D by only a small factor because of the low output conductance g oss.
.6.ID

= (.6.VDS)

(goss)

(3)

The value of g oss is an important consideration in the
accuracy of a constant-current source. As goss may
range from less than 1 ).LS to more than 50 ).LS according to the FET type, the dynamic impedance can
be greater than 1 M n to less than 20 kn. This corresponds to a current stability range of 1 ).LA to 50 ).LA
per. volt. The value of g oss depends also on the operating pOint. Output conductance g oss decrease approximately linearly with I D, becoming less as the FET
is biased toward cut-off. The relationship is
ID

+

'------+----1111------'

goss
g'oss

IDSS

(4)

where
Figure 1.

Field-Effect Transistor Current Source

Whenever the FET is operated in the 'saturated region, its output conductance is very low. This occurs
whenever the drain-source voltage VDS is significantly
greater than the cut-off voltage VGS(off). The FET
may be biased to operate as a constant-current
source at any current below its saturation current
IDSS.

goss

= g' oss

(5)

VGS

=0

(6)

when

So as VGS VGS(off), goss Zero. For best
regulation, I D must be considerably less than I DSS.
It is possible to achieve much lower g oss per unit I D
by cascading two FETs, as shown in Figure 2.

For a given device where IDSS and VGS(off) are
known, the approximate VGS required for a given I D is

VGS

= VGS(off) [

1 - (I

~~S) 11k]

(1 )

where k can vary from 1.7 to 2.0, depending upon
device geometry. The series resistor R S required between source and gate is

RS

9-146

(2)

+

Figure 2.

Cascade FET Current Source

.-r'Siliconix

.LII

LPD·15

incorporated

=

Now, I D is regulated by Q 1 and V DS1
-V GS2 . The de
value of I D is controlled by R sand Q 1. However, Q 1
and Q2 both affect current stability. The circuit output
conductance is derived as follows:

_i_o_
g0551

Vo

= Vd51 + Vds2 = Vds2 +

Vo

gossl + gos52 + 9 t52
= vds2--~~--~=~~~--

(9)

(10)

gos51 + gts2

Figure 2 is redrawn in Figure 3 for the condition VGS1

= O.

io
Vo

go=--

If gossl

go =

gossl goss2
g05s1 + gos52 + gts2

= goss2

(11)

(12)

goss

(13)

---::---:='-:---2 + gtsl goss

when Rs # 0 as in Figure 2

(A)

goss2

r-----------~--------------04-- 10

~-----:.;~------

(15)

gfs (1 + Rs gts)
go•• 2

go••l

In either case (Rs = 0 or Rs ~ 0), the circuit output
conductance is considerably less than the g oss of a
single FET.

+
Vd.1 = -Vg .2
= 10/go••1

In designing any cascaded FET current source, both
FETs must be operated with adequate drain-gate
voltage VDG . That is,

(8)

VDG > VGS(off), preferably VDG > 2 VGS(off)

(16)

Figure 3.

If VDG < 2 VGS(off), the goss will be significantly increased, and circuit go will deteriorate. For example:
A JFET may have a typical g oss =4 IlS at VDS =-20 V
and VGS
O. At VDS ~ -VGS(offl
2 V, gOS5 ~
100 IlS.

=

=

(7)

io =

vd52 g0552 g0551
g0551 + gt52

--=-:.;~~=----­

(8)

The best FETs for current sources are those having
long gates and consequently very low g oss. The
Siliconix 2N4869 exhibits typical g oss = 1 j.lS at VDS =
20 V. A single 2N4869 in th circuit of Figure 4 will
yield a current source adjustable from 5 j.lA to 1 mA
with internal impedance greater than 2 MO.

9-147

.-:r'Siliconix

LPD·15

~ incorporated

.---------1111-1- - - 0

Rs = 1Mn., 2W

Figure 4.

Adjustable Current Source
Rs
1 Mn.. 2 W

=

.-----ll 11-1- - - 0

Rs>--"

Q, = 2N4340

Q2 = 2N4341
Rs = 1Mn., 2W

Figure 5.

9-148

Cascade FET Current Source

The cascade circuit of Figure 5 provides a current
adjustable from 2 )J.A to 1 mA with internal resistance
greater than 10 MO.
Siliconix also offers a line of JFETs with a resistor fabricated on the device. thus creating a 10% current
range. The series is called the CR022 (0.22 mA
range) through the CR530 (5.3 mA range). See the
data sheet section fOi spsa:fic pact types. TI-Ie
devices allow precision designs using a single device
versus the typical approach using several components.

.:rSiliconix

~ incorporated

LPD-16

LOW-POWER MOSFETS FOR "SMART" TELEPHONES
Deregulation of the telephone industry has brought
fierce competition among electronic telephone
manufacturers. "Smart" phones now provide special
services, such as automatic re-dial, elapsed time indicators, repertory dialing, visual display, and many
other attractive consumer aids. One circuit described
in this article uses low-power MOSFETs to provide all
the basic high-voltage switching functions needed in
an electronic telephone set.
This article also describes a basic remote-isolation
device or RID' circuit implemented using low-power
MOSFETs. RIDs are used to identify telephone link
problems that result from faults in customer's equipment rather than faults in the phone company
system. A RID is placed on the telephone line at the
interface between the telephone line and the customer-owned wiring. When the telephone company
tests the line, a standard test signal activates the
RID, momentarily disconnecting the customer-owned
equipment and leaving a standard termination connected. If the problem is isolated to the customerowned equipment, the telephone company can save
from $50 to $BO for an unnecessary service call. This
savings easily justifies the modest cost of the RID,
and recent legislation encourages their installation on
all new central office lines in the U.S.

Electronic Telephone Handset
Figure 1 shows a block diagram of the essential functions of a telephone set. On the left side, the telephone lines (known as tip and ring in the U.S. or as A
and B in Europe) enter the handset (known as a station set in the U.S.). In Europe, there may also be a
third line which allows one to signal the operator by
momentarily connecting this line to the B conductor.
On the right side of the diagram, separate pairs of
wires go to the microphone and earpiece. These
transmit and receive functions are separated by circuitry known as a hybrid. On the two-wire (left) side
of the hybrid, tip and ring carry both incoming and
outgoing signals. However, on the four-wire (right)
side, incoming and outgoing signals are separated.
This prevents speech Signals generated by the microphone from being repeated with deafening force
into the ear of the person speaking. Traditionally, the

hybrid function was provided with a transformer circuit; however, in recent times, electronic circuits
have been contrived to perform the same function.
A pair of buttons on the top of most handsets operate a simple closure switch known as the hookswitch.
(Named from early telephones that switched when
the earpiece was hung on a hook.) The hookswitch
can also be used for pulse dialing. In pulse dialing,
the loop is repeatedly opened and closed to signal
dialing instructions to the exchange. Traditionally, this
is done at a rate of 10 pulses per second. In tone
dialing, special oscillators (known as dual-tone multifrequency generators) generate tones representing
the dialing instructions. These tones are normally applied across the loop without interruption.
The bridge circuit shown in Figure 1 is a polarity
guard that protects the telephone circuitry against
accidental polarity inversion of the linefeed voltage or
accidental crossing and substitution of the telephone
lines. Since this is normally done with pn diodes, the
1.5 V dropped across these diodes can limit telephone circuits designed to operate on long loops
where only a few volts are available at the end of the
loop to run the handset.
The surge protection block prevents the telephone
circuitry from being damaged by high-voltage
surges. Telephone lines are typically routed in bundles with a metallic grounded shield around the bundle. If the metallic shield is struck by lightning, a highvoltage surge is produced on all of the lines in the
bundle. This surge may run to tens of thousands of
volts. The most important feature of the protector
circuit is a carbon block spark gap, which arcs over
at about 400 V to BOO V. When electronic components are used in the telephone set, this surge needs
to be further reduced by a circuit comprising resistors and a metal oxide varistor which breaks over at
200 V.
The ring detection circuit is designed to recognize
the 20-Hz waveform of an incoming ring signal and
thus produce a ringing tone or a logical output which
operates a separate ringing-tone generator. In an
electronic phone, it is often desirable to disable the

'This device has other common names, such as maintenance termination unit and remote disconnect unit.
9-149

.rSiliconix

LPD-16

~ incorporated

MICROPROCESSOR CONTROLLER
FROM HV
CIRCUIT

5V

J1P

r-

RECALL PULSED FORCED HOOK
DIAL
OFF SWITCH
INPUTS
HOOK INPUT

POWER
SUPPLY

TIP
(LINE A)

DROP

~GE

RING
(LINE B)

~

DTMF
GENERATOR
HOOK SWITCH CONTROL

HOOK SWITCH

k

~
(A)

~

I

t t t t

I~~'~
SURGE
~
PROTECTION
(B)

TO HV
CIRCUIT

I

r---l

KEYPAD

RECALL
RECALL
SWITCH

I
I
I
I
I
I
I
I
I
I

SPEECH
+ OUT

GROUND
OUT

HYBRID

~".~
MICROPHONE

RINGER
DISCONNECT

RING DETECTION CIRCUIT

Figure 1.

Electronic Telephone with Solid-State
High-Voltage Switching Elements

ring detection circuit when the handset is picked up,
thus preventing accidental triggering of the ring
detection circuit. If the station set is used in a handsfree telephone application, an off-hook condition
must be generated to draw current from the line
while the handpiece is resting on the hookswitch.
This function, the "forced off hook" capability, along
with the generation of dial pulse or dial tone signals,
is initiated by the microprocessor controller, the hallmark of a smart phone.
In Figure 1, a number of telephone handset functions
associated with high-voltage switching are illustrated.
These switching functions are ideally provided using
low-power MOSFETs, regardless of how the controller, DTMF generator, hybrid, and other components
are implemented. Inside this box, a 5-V power supply
draws a small amount of power from the telephone
line and generates the 5 V of power needed to run
the low-power CMOS logic in the handset. The polarity-guard diode bridge is synthesized from low-cost
power MOSFETs which provide the same protection

9-150

as the diode bridge without interposing a fixed 1.5-V
drop into the telephone loop. A switch provides the
hookswitch function, and when pulsed on and off, it
can also be used for dial pulse signaling. A ring disconnect switch disconnects the ring detector when
the handpiece is picked up, and a recall switch momentarily connects the recall line to the more negative of the two telephone conductors when a 5-V signal is applied to the recall input. Logic signals tell the
microprocessor when its power supply has reached
full voltage so the microprocessor functions can begin.

Figure 2 shows the detailed implementation of the
handset switching circuit. At all times, the intrinsic
diodes of the MOSFET bridge, consisting of transistors Q1 through Q4, bleed through small amounts of
current of the correct polarity. This current passes
through the 10-M!1 resistor, R1, to the 10-V zener
diode, Z1, connected by a 100-k!1 resistor to the
gate of Q9. Thus the 10-M!1 resistor is permanently

ICrSiliconix

LPD-16

~ incorporated

,lIP START

SVPOWER

TIP

(Al

RING
(61
QS

Q6

RECALL

L.."'-"'--.-----1~V\I\rI300 V Breakdown

Remote Isolation Device Circuit

The circuit will respond to a 1-s, +100-V or greater
potential on tip or ring by turning off both switches for
approximately 10 s. It is not triggered by transient
pulses above 100 V, nor by sharp pulses or noise on
the line, and it is not affected by the normal negative
voltages used in telephone service. When the +135-V
signal is applied, the disconnect does not occur until
the voltage is reduced below the original level. Once
triggered, the disconnect cannot be negated by the
application of other potentials, even if they are
greater than 130 V. The functioning is not affected if
tip and ring are interchanged.

Conventionally, telephone companies place a recognizable impedance across the line in front of the remote isolation device. This is frequently a diode in
series with a 400-krl resistor, so the variation of impedance with polarity can be observed when the customer has been disconnected.

Those who plan to build a remote isolation device
should consult the detailed network requirements of
the telephone companies involved to make sure that
all applicable regulatory requirements, such as those
imposed by the FCC, are met. The circuit shown
here requires a resistor and varistor protector to protect it against overvoltages in excess of 240 V, such
as those associated with a power cross where a
power line touches the telephone line.
The low-power MOSFETs that provide all the basic
high-voltage switching functions for the telephone set
and the RID circuits presented in this article are available from Siliconix. In addition to standard enhancement-mode MOSFETs, we also offer depletion-mode
options that provide a convenient interface with the
economical gate-drive circuits used in many telephone systems. Siliconix has a well-established history as a supplier of rugged, high-voltage MOSFETs
for the worldwide telecommunications industry.

9-153

~
~

~SilicDnix

LPD-17

~ incorporated

P-CHANNEL MOSFETS
THE BEST CHOICE FOR HIGH·SIDE SWITCHING
Ed Oxner
Central Applications

Historically, p-channel FETs were not considered as
usefui as their n-channei counterparts. The higher
resistivity of p-type silicon resulting from its lower
carrier mobility put it at a disadvantage compared to
n-type silicon.

nel in both on-resistance and capacitance simultaneousiy, such combinations as the iow-threshoid pchannel TP0610 and the n-channel 2N7000 together
offer outstanding performance as a complementary
pair.

Getting n-type performance out of p-type FETs has
meant larger area geometries with correspondingly
higher inter-electrode capacitances. Consequently, a
truly complementary pair - a p-channel and an
n-channel device that match in all parameters - is
impossible.

CIRCUIT APPLICATIONS

Another obvious shortcoming is that, despite the
availability of low-threshold devices, no p-channel
MOSFET is "logic compatible."
Yet, despite its shortcomings, the p-channel MOSFET
performs a vital "high-side" switch task that the nchannel simply cannot equal.

To drive the FET properly, the gate voltage must be
referenced to its source. For enhancement-mode
MOSFETs, this gate potential is of the same polarity
as the MOSFET's drain voltage. To turn on, the nchannel MOSFET requires a positive gate-source
voltage, whereas the p-channel MOSFET requires a
negative gate-source potential.

Used as a high-side switch, a p-channel MOSFET in a
totem-pole arrangement with an n-channel MOSFET
will simulate a high-current, high-power CMOS
(complementary MOS) arrangement. Although the
p-channel MOSFET cannot complement the n-chan-

During switching, a MOSFET's source voltage must
remain fixed, as any variation will modulate the gate
and thus adversely affect performance. Figure 1
shows this degradation by comparing n-channel and
p-channel MOSFET high-side switching.

Figure 1.

9-154

Switching Ground-Return Loads
The principal application of the p-channel, enhancement-mode MOSPOWER FET is in switching power
(or voltage) to grounded (ground return) loads.

N-Channel

P-Channel

(a)

(b)

Comparing the Performance Between N-Channel and P-Channel Grounded-Load Switching

..:rSiliconix

LPD-17

~ incorporated

If an n-channel, enhancement-mode MOSFET were
switching a positive-polarity voltage to a grounded
load, the output would be limited to VGG - Vth.

and rail ensures that V(BR)GSS will not be exceeded.
Again, both MOSFETs must withstand the full rail voltage.

The equations describing performance of the n-channel ground-switching MOSFET with a ground-reference gate drive are based on the relationship between VDD and VGG :
IfVDD ~VGG, thenVo =VGG-Vth;
If VDD < VGG , then Vo = VDD - I LrDS(on).
Sustaining a more acceptable gain with an output in
direct relation to VDD would require an isolated gate
drive referenced to the source, as shown in Figure 2.

TTl.:-"----'

Figure 3.

Bootstrapping for N-Channel
Ground-Loaded Switching

A

- - r - r - - - , - - DD

B

TTL

Figure 2.

Floating Gate Drive

Bootstrapping the n-channel MOSFET (see Figure 3)
is quite satisfactory for short turn-on times of a few
milliseconds. In this arrangement, both MOSFETs
must have breakdown voltage specifications that
match or exceed the rail voltage.
Using a p-channel MOSFET in the configuration
shown in Figure 1 (b) may place some severe restraints upon the gate drive, since the gate must be
close to VDD. To return gate control to a more acceptable logic format, add an n-channel MOSFET as
shown in Figure 4.
Using an n-channel MOSFET in this way simplifies the
gate drive for a high-voltage, high-side, p-channel
MOSFET. Placing a Zener diode between the gate

J1:
Figure 4.

Using an N-Channel Level-Shifter
Simplifies Driving from Logic

Half-Bridge (Totem Pole)
The high-side p-channel MOSFET coupled to a lowside n-channel MOSFET with common drains (shown
in Figure 5) makes a superb high-current "CMOS
equivalent" switch. One fault common to such
circuits has been the excessive crossover current
during switching that may occur if the gate drive
allows both MOSFETs to be on simultaneously.

9-155

.-r-Siliconix
.z.
incorporated

LPD·17
T+

15V

lid """om"

1-v

."v_n_~
-15V~

=

I~
~9

L

crossover current, as Figure 6 shows. When the output stage uses high-power MOSFETs, a resistivelycoupled lower-power complementary pair offers extremely low crossover current. The Zener, Z1, and
resistors, R1 and R3, act as a level shifter, properly
driving the low-power MOSFETs. The Zener may be
selected according to the equation

VZENER
N-Channel

where

~-15V
Figure 5.

Low-Voltage Complementary
MOSPOWER Array

At high rail voltages (both +VDD and -VDD), properly
driving the MOSFET gates can minimize unwanted

+VDD

= 2 VDD
= -VDD

-I

Vthl

Whatever crossover current that might occur in the
low-power drivers is dramatically reduced by the series resistor, R4. Additionally, driving the high-power
complementary pair using this resistor divider
scheme all but eliminates crossover current in this
critical output driver. This increases both the driver's
efficiency and its reliability.

~----...--------....,..-+

voo

R2

TTTI

N-Channel

11

Figure 6.

9-156

- - 4 - - - - l_ _ _ _ _ _ _ _

--<~_

-Voo

High-Voltage Complementary Pair Driven by Logic-Compatible MOSFET

tcrSiliconix

LPD-18

~ incorporated

DEPLETION·MODE MOSFETS EXPAND
CIRCUIT OPPORTUNITIES
Ed Oxner & Richard Bonkowski

INTRODUCTION
A principal advantage of the depletion-mode MOSFET
is its ability to perform at higher operating voltages
than its JFET counterpart. As a depletion-mode
structure, the MOSFET permits the added flexibility of
allowing the gate potential not only to be higher but to
be of either polarity. Earlier, small-signal MOSFETs
were classed as being quite sensitive to ESD. With
the introduction of the ND2020 and ND2410 series,
sensitivity to ESD has been greatly reduced.
Perhaps the only short coming for the depletionmode MOSFET is its higher-than-JFET noise performance. Where the JFET has been perceived as a
.. noiseless" transistor, the MOSFET does not share
that renown.

Depletion-Mode VS. Enhancement-Mode
Three Classes of FETs

There are three classes of FETs, both n- and p-channel, that are identified by the mnemo A, Band C.
Class A encompasses the whole field of junction
FETs (JFETs). Class B includes those that are identified as depletion-mode MOSFETs, and Class C includes those recognized as enhancement-mode
MOSFETs. Figure 1 illustrates the basic differences
that distinguish the various classes and also demonstrates how these classes differ with respect to biasIng.
In the symbols used in Figure 1, the solid bar identifies a depletion-mode FET (current conduction at
zero bias); the broken bar identifies an enhancement-mode MOSFET (zero conduction at zero bias) .

Note that although Class A and B are both classified
as depletion-mode, Class B radically differs in that
depletion-mode MOSFETs are also capable of
performance in the enhancement-mode region. This
distinction is only achievable for Class B. Although
neither Class A (JFETs) nor Class C (MOSFETs) can
perform beyond their respective mode, Class B - the

depletion-mode MOSFET - is capable of operation in
both modes I
Perhaps the simplest definition of depletion-mode
operation is shown by the transfer characteristic (biasing) curves offered in Figure 1 (b). Drain current is
reduced to zero when the gate voltage reaches a
critical cutoff voltage, opposite in polarity to that of
the drain voltage. The n-channel JFET (or Class B
MOSFET) has a positive-polarity drain voltage and is
controlled by a negative-polarity gate voltage. Why
the Class B MOSFET may also perform in the
enhancement-mode is made clear by study of the
structure.

The Structure of MOSFETs
All MOSFETs are classified as either depletion-mode
or enhancement-mode. Although they can be fabricated as n- or p-channel, generally we find n-channel
MOSFETs in either mode and p-channel MOSFETs
available only as enhancement-mode devices.
There are, however, three fundamental styles of
MOSFETs regardless of mode. The classic planar
MOSFET, shown in cross-section in Figure 2, the
short-channel double-diffused MOSFET (DMOS FET) ,
shown in Figure 3, and the vertical power MOSFET,
shown in Figure 4. The features of each style are distinguished by performance.
When viewing the cross section, the distinguishing
feature that quickly identifies the mode is whether a
diffused channel spans the gap from source to drain.
No visible channel (Figure 2a, 3a, and 4a) identifies
the enhancement-mode MOSFET.

The Performance
MOSFET

of

a Depletion-Mode

Regardless if the MOSFET is n- or p-channel, the fundam ental difference in performance focuses on
whether the MOSFET is a depletion-mode or an enhancement-mode device. An important, but secondary difference lies in the style of MOSFET: planar,
DMOS, or vertical. The principal differences are clarified as we study the transfer characteristics (biasing), shown in Figure 1.

9-157

--

~

LPD·18
N-CHANNEL

HSiliconix
incorporated

G~:

o~:

CLASS A
(DEPLETION-MODE)

0

IOS/11 0

I

LJ

-VGS

V GS

7

J~::'

(a)

0

GJ~:"

P-CHANNEL

GJ~:"

CLASS B
(DEPLETION-MODE)

-VGS

0

V GS

(b)

-VGS

0

V GS

CLASS C
(ENHANCEMENT MODE)

lOll
loss-

o

V th

(e)

VGS

Figure 1.

Classification of FETs

The transfer characteristics of the n-channel, depletion- mode MOSFET are shown in Figure 1 (b). Because the gate is isolated (see Figure 2b), VGS can
be reversed without creating a gate current. The gate
may be made either positive or negative with respect
to the source. By allowing the gate-to-source poten-

9-158

tial to go positive and increasing the magnitude of
gate voltage, additional free electrons will be attracted beneath the gate oxide further enhancing the
diffused channel and allowing 10 to become greater
than IDssl

~Siliconix
incorporated

LPD·18

.LI#

GATE

p
SUBSTRATE p(a)

Enhancement-mode

Enhancement-mode

(a)

GATE

p
SUBSTRATE
(b)

Figure 2.

(b)

Depletion-mode

Figure 3.

Classic Planar MOSFETs

SUBSTRATE

n+

Depletion-mode

Short-Channel Double-Diffused MOSFET

SUBSTRATE n+

DRAIN
(a)

p-

DRAIN

Enhancement-mode

(b) Depletion-mode

Figure 4.

Vertical Power MOSFET

This mode of operation results in a unique series of
output characteristics where, for the n-channel depletion-mode MOSFET, we see near-linear performance in what appears as the enhancement region.
This performance is shown in Figure 5. The foregoing

establishes that the depletion-mode MOSFET is a
"normally on" device; that is, when VGS = D, ID =
I DSS . When a normally off device is needed, the enhancement-mode MOSFET is selected.

9-159

~SilicDnix

LPD·18

~ incorporated

Applications For Depletion-Mode MOSFETs
As a Current Regulator

VGS = 1 V
VGS = 0

(3)

dVOS gos

diD

The ideal current source supplies a fixed current to a
load independent of the impressed voltage. Such a
source would exhibit zero output conductance. Aside
from the fact that depletion-mode ~,,~OSFETs can han~
die higher voltages and greater currents than most
JFETs, they exhibit two characteristics which provide
near-ideal performance as a current regulator. First,
when the impressed voltage exceeds pinchoff, Vp ,
the saturation characteristics exhibit near-constant
current (low output conductance) over a wide voltage range (see Figure 5). Second, performance as a
depletion-mode transistor allows for simplified biasing to achieve the desired results.

loss

magnitude of the output conductance of the MOSFET.

Rs
I
~_..
~- VGS~
Q1

+V O f - - - - , ~JIv-.-1-----r-o

I

~

I

~

I

I

LOAD

_vo~-----------~l-o
Figure 6.

Baslo Regulator Clroult

A typical constant-current regulator circuit that em-

ploys a depletion-mode MOSFET is shown in Figure
6. As with any depletion-mode FET, the lower the ratio between 10 and loss the better the regulation, as
shown in Figure 7 and Table 1 .

v
100

VGS= -1 V
10
VGS= -2 V

I

VGS= -3 V

10
(rnA)

50
Vp

Figure S.

VOS

/'
,;

Output Charaoterlstlos N-Channel
Depletion-Mode MOSFET
0

Basic Regulator Circuit

VGS = VGS(off)

~1 -

10
-loss

10

0

For a given device where loss and VGS(off) are both
known, the value of bias required to establish the
regulating current may be approximated by

)1/2

20

Vos (V)
Figure 7.

(1)

Output Charaoterlstlos of
a depletion-mode MOSFET

Table 1
10

The biasing resistor, R s, required in the source of
the MOSFET is

RS=~
10

(2)

A change in either supply voltage or load impedance
will change the regulating current in proportion to the

9-160

lOSS

0/0 Regulation

0.02
0.05
0.10
0.20
0.30

0.5
1.0
1.5
2.5
3.5

~Siliconix

LPD·18

~ incorporated

Extending Power Level Using MOSPOWER
The n-channel, depletion-mode MOSFET can be used
in conjunction with an enhancement-mode power
device to give an appreciable boost to the power
handling capability of a current regulator. Such a
power regulator circuit is shown in Figure 8, where
both the operating voltage and regulating current are
set by the selection of the MOSPOWER FET, 02.
Regulation may suffer somewhat when using large
MOSPOWER FETs due to the higher g os typical of
large power FETs. 02, operating in the linear mode,
will, in all likelihood, require a heatsink. The basic
regulator circuit, 01 and Rs, is used to establish a
small bias current that, in conjunction with R1 , sets
level
for the enhancement-mode
the
bias
MOSPOWER FET.

+vo

-vo

Q2

~

Figure 8.

0

much power. In most systems, current drain in excess of 10 to 15 IlA will alert the central office to an
"off hook" condition and the subscriber's phone is
presumed "busy." A simple depletion-mode regulator using the ND2410 can satisfy these requirements
very economically. As shown in Figure 9, the depletion-mode MOSFET is used in a current-regulator
mode to supply 10 IlA to a 500-kn load. This establishes a voltage of 5-V to power the memory circuit.
If the memory requires 2 microamperes, only 8 IlA
will flow through the resistor, and the voltage drops
to 4 V, which is sufficient to sustain the memory.
Should the telecom line rise to 60 volts, the current
regulator continues to supply a fixed 10 IlA to the
load; the surplus voltage is dropped by the MOSFET.
The regulation is not precise, but more than sufficient
to provide a simple and reliable solution. Alternatives
such as 3-terminal bipplar regulators require high
bias currents (over 1 mAl and are not readily available to sustain the high voltages necessary for use
on telephone lines.

1

LOAD

0

1

Extended-Range Current Limiter

Figure 9.

Telecom Voltage Regulator for
Memory - Resident Redlallng

A Simple Regulator for Telecom
Modern telephone handsets are steadily increasing
their electronic content. Useful features, such as a
memory to retain the last number dialed, require
constant voltage to retain the information in memory.
Typically, small memory les require only a few
microamperes at 3 to 4 V to perform. This sustaining
voltage must be available at all times, even when the
phone is inactive or "on hook." Some handsets use
a small battery cell to fill this need, while other designs use the -48 V which is available from the telephone line.
To utilize the incoming line, one needs to reduce the
voltage and loosely regulate it, without consuming

As a Switch
When considering a switch, we usually select one
whose natural, quiescent state is either normally-on
or normally-off. With no applied power (or voltage),
the depletion-mode MOSFET is normally-on.

Improving the dV/dt of Thyristors
The ND2410 can be used very effectively in power
SeR circuits to improve the critical dV/dt rating. Spurious turn-ON of an SeR caused by dV/dt can result
in permanent damage to an SeR or an out-of-sequence turn-ON that can have disastrous effects in
high-powered phase-control equipment.

9-161

Ell
•

LPD-18

~Siliconix

~ incorporated

r--

r-IC
_ .L_

I

_.L _

la= C dV /dt

'T'

'T'

I

I

-

I
·0

0

b

II

II

Va

Ras

Va

Figure 11. Depletion Mode Active Shunt

PULSE
Xfmr

Figure 10. dV/dt Triggering of SCRs

Traditionally, SCRs fired by pulse transformers have
used a resistor from gate to cathode to shunt false
gate Signals caused by dV/dt as shown in Figure 10.
This method requires a large wattage resistor, since
the normal gate trigger signal is also applied across
the resistor. The resistor, therefore, shunts part of
the normal gate current, thus reducing the signal
available for adequate turn-on of the SCR. The ideal
solution would be a shunting resistor that seems to
disappear when a normal gate signal is applied.
Just such an effect can be achieved using the normally on feature of the ND2410 as shown in Figure
11. With no gate pulse applied, the depletion-mode
transistor is "on" with an equivalent resistance of
about 10 .0.. When the gate current is applied, the
voltage drop across R GS turns the transistor off,
allowing all of the gate current to flow through the
SCR gate.

9-162

Since the MOSFET turns off in a few nanoseconds, it
has very little effect on normal SCR operation. In an
actual experiment, the dV/dt of a 25-A SCR (similar
to a 2N692) was improved from 300 V/JJ.s (with no
gate shunt network) to 2000 V/JJ.s with the depletionmode shunt.

Some suggestions for effective operation:
1. Use a fast-rising gate pulse: I G > 3 x I gt
2.

The shunt should be located as physically close
to the SCR gate terminal as possible to reduce
the winding inductance and noise pick-up from
long gate wires.

3. RGS ~ VGS(off)
IG

4. Do not use with non-isolated gate drive circuits;
a pulse transformer should be used.

.HSiliconix

LPD-19

incorporated

APPLYING ,MOSFETS IN LOW VOLTAGE CIRCUITS
Richard L. Bonkowski

INTRODUCTION
The application possibilities for low-power MOSFETs
are so numerous that they often are suitable for use
in low-voltage circuits (5 to 15 V) as replacements
for bipolars or as switches driven by digital integrated
circuits. Lamp and relay drivers, small motor controls, and stand-by power-transfer switches are just a
few of these popular low-voltage circuits. These
applications deserve special consideration as they
highlight one of the important differences between
MOS and bipolar technology: MOS is voltage controlled, while bipolar devices are current controlled.
Applying MOSFETs in these low-voltage circuits is
greatly simplified by the availability of low-threshold
MOSFETs from Siliconix.

"high" state output of a TTL gate (3 to 4.5 V), this
transistor could be completely "off" or, at best, conducting only 10 or 20% of rated current. A curve for a
Siliconix low-threshold transistor, the 2N7000 FETlington, is shown in Figure 2.

2.0

1.6

l

1.2

IIJ
r

10
(A)

0.8

-

0.4

Transfer Characteristics
To better understand the performance of MOSFETs in
low gate voltage applications, one can examine the
transfer characteristics of a typical device shown in
Figure 1.

,

1.0

III

Tc=-55°C
0.8

10

0,4

0.2
25°C----...,

I

0

o

2

~

4

6

8

10

Vas (V)
Figure 1.

I
o

Figure 2.

/
2

4

I

IBIPOLAR

12N7000

6

10

B

Normalized Transfer Characteristics
2N7000

At TTL drive levels, this device can conduct 40 to
100% of its rated current. It should be noted that TTL
is normally considered to be "5-V logic," but practical available gate drive is generally to 4.5 V. If the
transfer characteristic of a small bipolar transistor
was shown on the same scale as the 2N7000, one
could see the relative independence of collector current once a base voltage level greater than 0.7 V is
applied.

J
A'

(A)

o

I

125°C

I

0.6

J

rt!+-TJ = ~SSOC
d..l- 25°C'
~1250t-

Normalized Transfer Characteristics
2N6786

To realize the full rated I D current, a gate drive of
approximately 7 volts is required. At the typical

Benefits of Low VT
Siliconix low-threshold MOSFETs offer the user a real
advantage in applying the benefits of low losses and
high switching speed to low-voltage circuits. At low
switching frequencies, the gate drive power required
by MOSFETs is virtually nil, compared to the 1 mW or
more required by comparable bipolars. Because
MOSFETs are essentially resistive in the "on" state,
conduction losses can be significantly less for MOS
than for bipolar devices.

9-163

LPD-19

.rSiliconix

~ incorporated

allowing the designer to achiever even greater turnon of Siliconix low VT MOSFETs or use of our normal
threshold MOSFETs.

Logic-Level Applications
TTL Gate Drives
While TTL gates operate from 5 v, the typical voltage
available at a gate output is 3.5 V. This is clearly insufficient to drive a normal MOSFET whose threshold
voltage can be 4.0 V. Low VT MOSFETs can sometimes be used in such applications, if only a small
fraction of their rated current is needed or a higher
rOSlon) can be tolerated. A a better solution is to use
open-collector TTL and a pull-up resistor to the 5-V
bus, as shown in Figure 3a.
5V

The designer should also bear In mind that the
switching speed of the MOSFET is dependent on the
gate driver's ability to source and sink peak current
to charge and discharge the input capacitance of the
FET. Typical TTL can source about 1.0 mA per gate
and sink about 10 mAo For very high-speed applications or to drive large MOSFETs, an intermediate
buffer may be needed. For a more complete discussion of gate drive requirements, see the Siliconix
MOSPOWER Data Book (1988), page 9-18.

CMOS Gate-Drives
Because CMOS logic can operate from 10- or 15-V
supplies, it seems more naturally compatible with
MOSFET transistors. While this solves the VGS problem, speed can still be an issue as CMOS gates
usually switch slower than TTL. CMOS gates are also
limited in source and sink current, but may be paralleled if additional drive is needed. External buffers
may be used with CMOS, as previously suggested for
bipolar TTL.

OPEN-COLLECTOR
TTL GATE

Low-Voltage Circuits

la)
5V

10 TO 15 V

V+

]w~

OPEN-COLLECTOR
TTL GATE

Circuits powered by batteries are of particular interest for MOSFET applications. Because MOSFETs can
be more power efficient than bipolars, they can be
used to great advantage in battery powered applications.
In 12-V circuits, conventional MOSFETs are readily
applicable. At lower voltages (eg. a 6-V Ni-Cad
source) or at low temperatures in automobiles (coldcranking can drop the battery voltage to 5 V), the
deSigner must be aware of gate drive conditions. For
the 12-V "cold cranking" situation or a 6-V Ni-Cad
near discharge (5 V), the I OION) and rOSlon) data at
4.5 V is particularly important.

Ib)

Figure 3.

Open Collector TTL Gats Drive

This technique will provide a greater drive voltage,
and the designer can use the data from Siliconix data
sheets showing the rOSlon) for 4.5-V gate drive. Of
course, open collector TTL, connected to a 10- or
15-V supply (Figure 3b) is an even better solution,

9-164

Figure 4 shows a typical automotive application for a
"high-side switch" or solid-state relay. The gate voltage for the high current MOSPOWER switch is supplied from a voltage doubler IC (Si7661). To prevent
activation of a load under low battery conditions, Q2,
a low-threshold 2N7000 prevents Q1 from turning on,
even if only 4.5 V of gate control is available from a
cold battery. If Q1 could not be held off, control of a
non-essential load (lights, radio, etc.) might be lost,
further burdening the battery during starting.

.:r'Siliconix

LPD·19

~ incorporated

Q1
SMM70N05

LOAD

12Vo-------~--------------,

I

I

'--M-...I

6

SI7661

Q2
2N7000

2
3

5

GNDo-------~~-----------4----------~---------4----------~

Figure 4.

Automotive High-Side Switch

Low-Threshold P-Channel MOSFETs

Design Considerations

Most of this discussion has focussed on n-channel
transistors because of their wide selection, low cost,
and better availability. High-side switches, as shown
in Figure 5, can be easily implemented with p-channel MOSFETs and open-collector or open-drain logic
at low-voltage levels.

When using low-threshold MOSFETs, one should be
aware of the changes in VT due to environmental
conditions. At high temperatures, VT decreases. A
device with a 1.0-V threshold at 25 DC might drop to
0.5 or 0.6 Vat 150 DC. Under these conditions, the
MOSFET could gate-on due to electrical noise or fail
to switch off if the pull-down circuit cannot drop Vg5
to a low enough value. Operation in an environment
susceptible to radiation (e.g., x-rays) can permanently depress VT, resulting in false turn-on due to
noise or depletion-mode operation, that is, a normally-on state requiring a negative gate voltage for
turn-off .

Figure 5 High-Side P-Channel Switch
The threshold of the p-channel is not usually critical
unless the supply voltage is very low. With a 12-V
supply and a 4-V threshold, 8 V are available to enhance conduction of the FET. If The supply were only
5 V, the enhancement would be minimal and rDSlon)
would be very high. A low-VT transistor, such as
TP0610, should be used in this case.

v 0----.-----... . .

LOAD

When comparing MOSFETs, be aware that some
manufacturers achieve low VT through the use of
thinner gate oxides. This lowers the maximum gate
voltage rating of the transistor (Siliconix parts are all
rated for at least ±20 V and makes them more susceptible to ESD (electrostatic discharge) damage.
Transistors rated at ±15 V maximum gate voltage
should be used and handled with proper caution.

CONCLUSIONS

Figure 5.

High-Side p-Channel Switch

Understanding and attention to proper gate drive is
essential for successful application of MOSFETs. In
many instances, low VT Siliconix MOSFETs are a
ready solution to achieve economical circuit design
where limited gate drive is available. The following
table shows some of the more popular Siliconix lowthreshold parts and their performance with gate signals of 5 V or less.

9-165

LPD·19

.rSiliconix

~ incorporated
Table 1

Part Number·

VN0300
VN0610
VN10
VN2222
VN66
VN67
VN80
2N6661
VN1206
VN1210
VN1706
VN2406

"Note:

9-166

SlIIconlx Low Threshold MOSFETs

VT (MAX)
\kBR)OSS

30
60
60
60
60
60
80
90
120
120
170
240

(V)
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.0
2.0
2.0
2.0
2.0

Only the first few significant digits are given
for some part numbers. Each family consists of a variety of package options indicated by suffix letters. Package style deter-

Low Vas Performance
rOS(ON)

Vas

( .0.)

(V)

3.3
7.5
7.5
7.5
5
5
5
5.3
10
10
10
10

5
5
5
5
5
5
5
5
2.5
2.5
2.5
2.5

mines the thermal performance of the product which,
in turn, determines current and power capabilities.
See the individual data sheets for complete performance data.

~Siliconix

-LI'

LPD·20

incorporated

AN ULTRA·BROADBAND ANALOG SWITCH
Ed Oxner

Many TTL and
commercially
into the UHF
scribe how to

CMOS-compatible analog switches are
available, but none operate usefully
region. The following instructions demake one that does.

The heart of the ultra-wideband analog switch is the
Siliconix S02100E series of small-signal enhancement-mode double-diffused MOS (OMOS) FETs. This
series features low on-resistance and low interelectrode capacitances--an unusual combination. In
either a 50- or a 72-n system, the S02100E OMOS
FET provides reasonably low insertion loss when on
and excellent off-isolation when off.
In this design, the "T" configuration (see Figure 1)
was chosen for its optimum off-state performance
over a wide dynamic and frequency range. The configuration uses a pair of OMOS transistors tied backto-back; that is, with sources in common and the
drains acting as the input and output. The shunting
OMOS transistor contributes to the high off-isolation
when the switch is off. The body terminal of each
S02100E is electrically tied to its respective source.
As with any OMOS FET, tying the body to the source
forms a body-drain diode across the MOSFET. In the
S02100E, body-drain diode conduction occurs at
close to 0.5 V.

would be sufficient to cause forward conduction
through the body-drain diode irrespective of gate
control, resulting in an off-isolation loss. Using a pair
of OMOS FETs in the "T" configuration places one of
the two diodes in opposition (i.e., in reverse conduction). As a consequence, the off-isolation remains
unaffected. However, because of the body-drain
diode's low forward conduction (approximately
350 n), in a 50- or 72-n system, the shunt arm of
the "T" requires only one OMOS FET. This 350 {l
shunt has little effect on insertion loss.
Other options for limited dynamic range switching
(besides the "T" configuration) include the popular
"L" configuration and possibly a single OMOS transistor with the body terminal clamped to a negative supply.
Varying the gate voltage makes the OMOS transistor
act as a wideband variable attenuator as well as an
analog switch.
The switch's layout and assembly begins by selecting
for the substrate a low-loss double copper-clad PCB
(RT/Ouroid 5870). Next, a 50-{l (or 72-{l) transmission line is etched onto this substrate, as Figure 2
shows. This line is suitably configured to accept the
S02100E .

• -14,

[

-

l~
-

'-------1---0 x

iii

'-----------------------------+---0)(
Figure 1.

Electrical Schematic of
Broadband Switch

A high dynamic signal (in this case, +10 dBm) across
50 n results in an rms signal voltage of 0.707 V. This

Figure 2.

Circuit Board Mask (Top View)
Showing Placement of SD210DE

9-167

LPD-20

.:r-Siliconix

..,,6;;lI incorporated

Finally, each DMOS gate is bypassed and isolated using a combination of shunt capacitors and series
RFCs (radio-frequency chokes). The shunting capacitors
are
chip
capacitors
(Varadyne
3BX050S393K -- 3.9 nF) and the RFCs are 10 selfsupporting turns of #26AWG enamel magnet wire,
each turn measuring 4.7 mm in diameter.

To drive the analog switch, simultaneously apply a
logic HIGH (for turn-on) to the series DMOS gates
and a logic LOW to the shunt DMOS gate. As the
logic HIGH increases in potential, the rDS of the
DMOS transistor improves, resulting in a progressively improved insertion loss. Consequently, performance improves with 15-V logic as compared with
5-V logic, as Figures 3 through 6 show.

Insertion Loss
0

"Off" Isolation
100

V~~ALOG

IIII

= 5V

-2

80

........
-4
dB

-6

II

11'';=

"

I VANALOG = 5 V

I I I a dBm
' I I -10 dBm
I I 10 dBm

II

~-30dBm

60

-30 dBm, -10 dBm
o dBm
I- 10 dBm

dB

40

,~~

~

....... fIII

-8

-10

20

10

100

o

1K

10

Frequency (MHz)
Figure 3.

100

Insertion Loss for a SD210DE "T"
Switch with a 50-.0. Input/Output
and 5-V Logic

Figure 4.

Off-Isolation for a SD210DE "T"
Switch with a 50-.0. Input/Output
and 5-V Logic

Insertion Loss
0

-2

"1/

-4

II
I

r~

"Off" Isolation

KiNiLOi

=1

100

YIII

1-0.

I
~::

~/

~1'

VANALOG = 15 V

o dBm
-10 dBm
-30 dBm

{"!Io

dB

40

"'r--

20

10

100

1K

o

Frequency (MHz)

9-168

II

60

-8

Figure 5.

IIII

~10dBm

10 dBm

-6

-10

80

-30 dBm, -10 dBm

~

dB

1 I<

Frequency (MHz)

Insertion Loss for a SD210DE "T"
Switch with a 50-.0. Input/Output
and +15-V Logic

10

100

Frequency (MHz)
Figure 6.

Off-Isolation for a SD21 ODE "T"
Switch with a 50-.0. Input/Output
and +15-V Logic

1K

.::r-Siliconix
.z::.
incorporated

LPD-20

Because of the high gate impedance, the switch will
remain in either state (on or off) when the logic is
removed, provided that the gate-driving impedance
is also extremely high. Performance decays with
time, of course, depending upon cleanliness of the
circuit board, and humidity.

The performance of this analog switch was measured
using the Hewlett-Packard vector voltmeter, Model
HP8405A, with its accompanying 50-.0 accessory kit,
the HP11570A. The off-isolation tests were limited by
the HP11570A's dynamiC range and interchannel
isolation. At signal levels of 0 dBm an +10 dBm,

measurements to 70 dB were possible, but at lower
signal levels the dynamic range was less. As a result
of this dynamic range limit, the measured off-isolation was limited to -52 dB at a signal level of
-30 dBm.
The apparent lack of off-isolation at high signal levels
may partly be due to the layout. No shielding was
attempted, even between the DMOS transistor's
source and drain.
The performance curves in Figures 3 to 6 are, with
these explanations, self-evident. The analog switch
rolls off -3 dB at about 500 MHz.

\

9-169

LPD-21

~Siliconix

~ incorporated

A HIGH QUALITY AUDIO CROSSPOINT SWITCH
Bob Zavrel
Revised January 1988

9. Freedom from switch "popping"
1O. Small size
11. Usa of DC coupling only

INTRODUCTION
Recent advances in analog switch integrated circuits
have made superior audio switch specifications possible. A crosspoint switch for the most demanding
audio applications is described here. Although this
switch may be used in recording studio and radio
broadcast mixers where little compromise is acceptable. the low cost and small size makes this switch
ideal for a diverse range of applications. Such appli~ations can include audio crosspoint switches found
in video systems. audio synthesizers. high quality
multiplexers. and home entertainment systems.
A high quality audio frequency switch should have the
following features:
1.
2.
3.
4.
5.
6.
7.
8.

Reasonable cost
Unity or variable gain
Very low harmonic distortion « 0.01 %)
Flat response (DC to > 1 MHz)
Low crosstalk
High OFF Isolation
Excellent phase linearity
High speed switching

75

RL

Rs

41s

k.o.

I

011
SUMMING AMP
RA

I

3jc;L.J

± 15 v

CHANNEL 1

0--[ j

_

1

6 G

RIGHT INPUT BUS

Siliconix SD5002s were chosen because of low ON
resistance. low switch capacitance. and very fast
switching times. The LF347 quad op amp was chosen
for its excellent audio characteristics in a quad package. Two LF347s are used in this switch providing a
sum~ing and output amplifier for each of four channels. Since the SD5002s switch into virtual grounds.
they are held "normally open" by applying
SUMMING
NODE FROM
6 OTHER LEFT SWITCHES

r----.,
LEFT INPUT BUS

The size of a complex audio switching array can be
greatly reduced by using IC analog switches. The
prototype array is an 8x2 stereo crosspoint switch
mounted on a 4x7 inch board. Other switch configurations may be fabricated with little effect on the
switch characteristics. This single board can replace
a score of rotary switches and the bundles of audio
cable often found in audio mixers. Furthermore.
ground loop problems are reduced by eliminating the
cable bundles.

i

600.0.
RO

Rs
75

k.O.

CHANNEL A
LEFT OUTPUT
RO 600.0.

S05002
LEFT INPUo-T_B...,U....
S_ _ _....R,y.S;:,...J.>......t......r.
75

RL

± 15V

CHANNEL 2

k.O. 141G

0--[1-

J

600.0.
RO

l11G"i
I
----W.....,,
::r.
k.o. I

RIGHT INPUT BUS

Rs

o--......

75

_
12 S,...... ......-"""""+:;---0 SUMMING NODE FROM
6 OTHER RIGHT SWITCHES

I

L. _ _ _ _

I

SUBSTRATEO v-

J2

Figure 1.

9-170

CHANNEL A
RIGHT OUTPUT
RO 600.0.

ICrSiliconix

LPD·21

.r;;II incorporated
-15 V to the switch gates. To turn them on it is sufficient to apply a V+ level to the gates. For any switch
configuration, the appropriate switch(es) are closed
by biasing the appropriate gate(s) to the positive
voltage supply. In this circuit, pairs of switches are
controlled together to affect the left and right channels of a stereo input simultaneously. This is accomplished simply by tying the applicable switch gates
together and using a common bias.

Figure 1 shows how a single 8D5002 is configured as
a 2x1 stereo switch. Figure 2 shows how the circuit
can be expanded into a switch matrix. Eight 8D5002s
are required to construct the 8x2 stereo matrix array.
One RL is required for each channel input for termination while four R S 's are employed to feed the signal from the swiitches to the amplifiers. Input buses
are consequently formed in front of these resistors.

75 k.O.

RS
600n
>---'V\f\r--Q L

75kn

CHA

OUTPUT

600n
>---'VVIr--Q R

B

STEREO
INPUTS
R

O--r--..,--t--+-t--<,..... ...._ - t - - ;

2

STEREO
OUTPUTS

75 kfi

75kn

CH B

OUTPUT

600n
>---'VVIr--Q R

..
Figure 2.

A High Quality 8 x 2 Stereo Crosspoint Switch

9-171

LPD-21

~SilicDnix

~ incorporated

The SD5002 drains are connected to these input
buses. A larger array will cause reduced system performance due to longer lead lengths and increased
circuit capacitance. Nevertheless, large matrices can
be configured with little performance compromise
because of the low initial switch capacitance. RL'S
value should reflect the value of the source impedance. Deletion of RL will seriously degrade crosstalk
and off isolation performance while lower values of I'l L
will improve these specifications. Rc may be adjusted
for a wide range of system gain while a value of
about 150 kn will set the circuit to unity gain. RD sets
the value of the output impedance and if the switch is
to feed a high impedance load, Ro should be included to maintain system performance.
Electrolytic and mica capacitors are used on the cir-

cuit board for bypassing the two power supply voltages. Supply voltage bypassing will reduce both high
and low frequency noise and help stabilize the system. The entire circuit should be well shielded particularly if it will be exposed to strong rf or power line
fields. Conductors carrying high current should be
kept away from the circuit. Double sided PC board
should be used creating a ground plane on the componer'Jt side as an additional precautionary measure.
Table 1 shows the switch performance of the 8x2
crosspoint configuration. RL was set to 10 k .0, reflecting the high impedance of the test oscillator's
output. Regulated power supply voltages of plus and
minus 9 to 15 volts may be used. The signal voltages
should be kept under about 3.5 Vp_p to maintain
switch performance.

TABLE 1
Frequency
(Hz)

50
100
200
500
1
2
5
10
20
50
100
Signal voltages: 3 Vp-p
Supply voltages: ±12 volts

9-172

Crosstalk
(dB)
-74
-74
-74
-74
-74
-73
-70
-67
-62
-55
-50

"Off" Isolation

THO

(dB)

-75
-75
-75
-75
-75
-74
-71
-68
-62
-55
-49

0.006
0.005
0.004
0.003
0.003
0.003
0.003
0.004
0.006
0.020
0.045

General Information
Cross Reference
Selector Guide

JFETs
DMOS
Low Power MOS
Performance Curves
Package Outlines
Applications
Worldwide Sales Offices and Distributors

III

u.s. Sales Representatives
ALABAMA

ILLINOIS (SQuthern)

NORTH CAROLINA

Huntsville (35815)

See Kansas

Charlotte (28212)
Rep, Inc.

~~& J~gx 4889

~4d8n~I~~f3 ~~~J~ Ct,::.k425

ILLINOIS (Northern)

11535 Gilleland Road

~~ 1ggJ:~g£3;692

V~1 57sg;-~S:_7507

~f!~r:~~n~~rk~~?~~borp.

3158 Des Plaines Avenue
Suite 109

~

~~1 m:~~?o650

See Washington

ARIZONA

illQJMIA

Tempe (85282)

indlanaRQiis (46268)
Wilson Technical Sales, Inc.
P.O. Box 681038
8752 Robbins Rd.

Quatra Associates, tnc.
4645 S. Lakeshore Drlvo
Suite 1

~~~! ~5~:~~g97a54

~~1 ~r?j~J~0664

ARKANSAS

MONTANA
See Washington

NEBRASKA

Morrisville (27560)
Rep. Inc.
2500 Gatewa~ Centre Blvd. ,Ste. 400

W~~1 ~~3j~1187g

See Missouri

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NEVADA (Northern)

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NEVADA (Clark County)
See Arizona

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NEW HAMPSHIRE

CALIFORNIA (Southern)

See Massachusetts

Irvine (92714)
SlIlconlx, Jnc,
17500 RedhlJl Avo.
Sulta 270

NEW JERSEY (Northern)

V~~ ~~~:}g~:a987

~

CALIFORNIA (Northern)

~~rc~~\~~ \~~~14)
21710 Stevens Creek Blvd,

I

~~1 ~5gj~~?7682

#100

Lenexa (66219)
Midwest Technical Sales
15301 W. 87th Pkwy.
Suite 200

~~18~tf-1~L103
~~~~:t ~~g~~lcai Sales

21901 La Vista

COLORADO

(316) 794-8565

~rl?~~~I~~n~.al11 )

KENTUCKY

6355 S. Pontiac Ct.

See Indiana

~~i ~6d:~~~~6887

CONNECTICUT
Cheshire (06410)
Connecdcut Applied Technology
399 Beacon Hili Drive

~>"?~1 ~6tm~670

LOUISIANA
See Texas

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See New Jersey (Southern)

FAX: 407-831-2844
Ft. Lauderdale (33309)

Semtronlc Associates, Inc.

3471 Northwest 55th Street

~~1 ~3J:m~1019

Clearwater (34616)
Semtronic Associates, Inc.
1467 S. Missouri Avenue

~';,,~1 ~~J:m:2234
GEORGIA

Suite 1

~~1 ~3:~g~194

.I:::I8YlAJ..l

NEW JERSEY (Soythern)

~

Marlton (08053)
B.G.R. Associates
Evesham Commons
525 Route 73
Suite 100

Portland (97224)
Crown Electronic Sales
17020 S. W. Upper Boones Ferry Rd.

t~~: ?~g:J~5?1358
~~:lln~69~~~~:1~~g
NEW MEXICO
Albuquerque (87111)
Quatra Associates, Inc.
9704 Admiral Dewey NE

~~~? 6~~~~~:~054

~607)

F~:II~~~~f8~~~~
~~r-~~~hll~~e~1~g~i~s,

MASSACHUSETTS
Tewksbury (01876)
Pro Comp Associates, Inc.
1049 East Street

FAX: 315-446-3047

~5f~1 ggg~g?0110
MICHIGAN

~~I~~t~~s~~!~:~

810 E. Grand River

f3&!
~~~1f~~APAIUR)
FAX: 313-229-9356

See Texas (Grand Prairie)

~~1 ~ijg~~~023

PENNSYLVANIA (Eastern)
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PENNSYLVANIA (Western)
Sea Ohio

PUERTO RICO

~~~t~~Yc (~~~~~lates,

fV.,~: ":160"::111-0604

~~1 ~gg:~~?£gf~1

RHODE ISLAND
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SOUTH CAROLINA
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Fishkill (12524)
Tri-Tech Electronics, inc.
14 Westview Drive

SOUTH DAKOTA

F~: 914-897-5611 (Manual Receive)
E. Rochester (14445)
Trl-Tech Electronics, Inc.
300 Main Street

TENNESSEE

~~~4~i~~(~~b1505

~716)

385-6500

See Minnesota

Jefferson City (37760)
Rep. Inc.
P. a. Box 728
113 So. Branner Avenue

F:s<:lig~~~8~~~~~

~~1 ~rgjn~40

NEW YORK (Metro/L,I,)

Eden Prairie (553441
High Technol~~ Sa as Associates

~

Babylon (11702)

FAX: 612-944-3229

t~! illiigg oo

Austin (78750)
Ion Associates l Inc.
9811 Anderson Mill Rd.
Suite 200 A

MINNESOTA

lJiJf ~~%74 ew Road

Astrorep incorporated
103 Cooper Street

FAX: 516-422-2504

See California (Northern)

Inc.

Mercantl! Plaza Bldg.
Suite 816

754-1094

Inc.
6836 E. Genesee Street

Tucker (30084)

~3.f4 ~grthlake Parkway

OKLAHOMA

~~1 gg~:gg~9616

Endwell (13760)
Trl-Tech ElectroniCS, Inc.
3215 E. Main Street

.E.!.Q.BJQA

t~~: g~J:~~~~321

Fairfield Commons
271 Route 46, Suite 210A

NEW YORK (Upstate)

DELAWARE

Altamonte Springs (32701)
Semtronlc ASSOCiates, inc.
657 Maitland Avenue

~~~7~~~~ ~g~g~~rated

~~1 m::m~7254

MISSISSIPPI

.lMJ:iQ

See Alabama

See Washington

10-1

u.s. Sales Representatives (Cont'dl
TEXAS (Conl'd)

!.!IAI::l

WISCONSIN

Salt Lak. City (64115)

1504 109th Street
(214) 647-11225

~: ~:~r~ Main Street
~~1W;~t7~

Houston (77014-1696)

VERMONT
See Massachusetts

Grand Pralrl. (75050)

Ion Associates, Inc.

~~:"n~i4~~J9

Wauwatosa (53226)

Larsen Associates, Inc.

10655 West Potter Road

~~1 r,:~~655
WEST ViRGINIA
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WYOMING
See Colorado

Ion Associates, Inc,

lmr-~t~W't7 Chas. Blvd.

ViRGINIA

WEST WISCONSIN

PISTRICT OF COLUMBIA

t-AX:

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See Maryland

713e0637-5612

Canadian Sales Representatives
North Gower, Ontario (M9B6E3)

Pipe Thompson, Ltd.
(613) 258-4067

Chip Distributor
E1.QB.lQA
Orlando (32810)
Chip Supply, Inc.
7725 N. orange Blossom Trail
(4071 298-71 0
TWX: 810-85(H)1D3
FAX: 407-290-0164

u.S. Distributors
ALABAMA

CALIFORNIA
~ura

Hills (91301)

~l8g,=trr'~

~~1 Bfg:ggg~464
Calabazas (91302)

~Ie Laboratories

2B 77 W. A~oura
~818) 880-9 DO
AX: 818-880-6510

Irvine (92718)
Marshall Industries
1 Morgan

V14) 859-6050

AX: 714-681-6255
Irvine (92714/

mle

Marshall Industries
9710 DeSoto Avenue

ARIZONA

FAX: 714-863-0473

~':.~~~f
10105 Car

nRoad

W19) 578

AX: 619
San DI~ (92123)

~

~~:l.~1 ~~~~)Ies

336 Los Coches

~~14ra~~':~224

La:

ratcrleS-EMG

ru,'l1 c~~~:~e Drive

: 910-335-1590
FAX: 619-565-9171, X274

W18) 407-0101

San Jose 95131)
Zeus
ts

AX: 818-709-6334

1580

~~~~f M:frJ~I~~26J51

~~1

Suite

350 McCormick Avenue

V~17~~~~007

COsta Mesa (92826)

Marshall Industries

3~g) K~~~b'" #140

V~1 nJ:t.l~~I22
~~~~o~l~o~=~~

\NYle Dlstrlbutlan Group
Sacramento Division
11151 Sun Center Drive

l~~gp ~~~sgton Blvd.
AX: 213-658-2076

~:S~':IT 6~~~~te

~AX: 916-635-6D44
Rancho Cordova (95870)

~~19~~~~491
~X~eg~v\~~)

9674 Telstar Avenue

~C~S~11~\j'lI.

~:r~"ra~
'l1:1~J Sales, #01
1361 "8' W. 190th Street

Bell Industries

~~1 :f~-6231
~~12~1~fr~22

Road

Rancho Cordova (95670)

Hamilton Electro Sales, 1129

3170 Pullman Street

10-2

~02

Avenue

ru,~: g~~7140

9650

~1Jl:

AX: 916-925-3478

Labora orles-EMG
17 72 Cowan Avenue

Chatsworth (91311)
~sr~t~Electro Sales,

FAX:
Chatsworth (91311)

~:~"~~~A~nC:F~

tJ~i) Ngr~!,~o Blvd.

109
: 910-997-1130
FAX: 818-708-7436
Rocklin (95677)

4311

Anth~

Ct., #100

~~1 ~~-sJ~D3

~~~n:~1A~'!;4~~6.b

1175 Bordeaux Avenue

~~14b~~679

Yorba Linda (92686)
Zeus Compoflents

RL~ ~~o~anch

Pkwy.
: 910-691-1696
FAX: 714 -921-2715

U.S. Distributors (Continued)
~!~ff:g~~~v~~~Ja

12400 Whltowaler Dr.

W~16~~~~~613

29

~~fffo~1A~~~~7~~A

6947 U

Thornton (80221)
Marshall Industries

tw~:81

12351 N. Grant St.

FAX: 407

1W~: ~n=-1657

FAX:

Plymouth (55441)

Marshall Industries

Blvd.

7g~~) ~~~~~

Lane
FAX: 612.£59-8321

~
1878

MISSOURI
GEORGIA

303~7-2899

Brldgoton (83043)
Marshall Industries

Norcross (30092)
Hamliton/Avnet, 1115
5825 Peachtree Corners E-O

Thornton (80241)

~~IT:.D~~~~~U~~~n~~OUP

1W~: 4~lci~~-0770

12774 Boonkor

~~1 ~fJj~~391
R~~7It~~YA~e"aecr,sJ05

~~1 4~~~~~9526

FAX: 303-457-4831

Norcross (30071)
Future Electronics
3000 Northwoods Parkway

~?le~~~~~~B<:OO33)
12421 W. 49th Avenue

Suite 295

FAX: 303-424-0932

Norcross (30093)
Marshall Industries

1W~: ~~g:~~93

13743 Shoreline Court

~~1 m:.1~~~8889

~~1 :gJ:m~7580

5300

CONNECTICUT

-\W~:
FAX:

~~~lj'nJ~~~!~! #21

Commerce Drive
Commerce Park

NEW HAMPSHIRE

~:~TI~~~}Xv~~~1 C:is

Pkwy .• Slo.140

444 E. Industrla~ Park Drive

W~:~g~~~~

FAX: 603-624-2402

Norcross (30071)
Pioneer Tach.
3100 F Northwoods Place

~~12~~~~050

NEW JERSEY

~~1 :~:JlJ1270

Lexington (02173)
Zeus
429 Marrett Road

~~1 g~j~~807
~~ln}~~~:P) #18

10 D Centennlar Drive

~~1 ggJ~~9802

f,~~:~~r~~u~~~!~3)

50 E. Commerce Or .• Ste. 1

-Rl.,~: ~~g~g~036

.El.Q.BJ.QA
A

FAX: 312-490-0569

onte Springs (32701)
e Electronics
Northlake Blvd.,

~

048

~:::mI~~~1~~~;t

~~llg~:M.l~318

Plnobrook (07058)
Pioneer Std.

#28

485 Gradle Drive

MICHIGAN

FAX: 317-844-5921
Indlanapoll. (46278)

22

M~:m:~~966

(32701)
Ivd. , 8t8. 1024

45 Route 46

Marshall Industries

19~?) ~~f%t~ Drive
FAX: 317-297-2787

~~

Ra l~~e\~9:3/)
Street S.E. A-5

Wk: 616j~028

49508)
rAve. SE

)

n1l:
~rgjgl~82
FAX: 201-575-3454
NEW MEXICO

~~~r~~eJ~~re~87123)
11728 Linn N. e.
~~1 ~~:~~~2819

Clearwater (34620)
Future Electronics
4900 N. Creekside Drive

W~1 m::g~~~7600

Livonia (48150)
Pioneer Std.
13485 Stamford

-Rl.,~: ~~:~:~~71

Fort Lauderdale (33309)
Marshall Industries

FAX: 313-427-3720

~~~~ ~ioiypress Creek Bivel.

MINNESOTA

~~1 g6~99~887

Eden Prairie (55344)
Pioneer Std.

Ovelda (32765)
Zeus
1750

~~1

Ig~) ~~~langIO Dr.
I

8te. 114

FAX: 612-944-3794

10-3

)

U.S. Distributors (Continued)
~(';W YOB~

(CODI'dl

~f~~~7 £~d:50)

QJ:iI.Q

~ENNSYb v

Cleveland (44105)

Horsham (19044)
Pioneer Tech.
261 Gibraltar Road

Pioneer Std.

840 Fairport Rd.

4800 E. 131st Street

-IZJJli:
g~J:£~~7001
FAX: 716-381-5955

~~12~~~i~~906

~~~ft~~~~J~~r.B~~O

933 Motor Parkway

~~15~~~~~~7426

954 Senate Drive

-\-V,,~: ~g::~g~2531
FAX: 513-439-6711

~~~~~~~tl9~dVe\~~J

~~~"Oa11 9~~uJir?~~O)

Dayton (45424)
Pioneer Std,

516 273-2053
AX: 516-434-4775

129 Brown Street

~~~1 m:~gj~7031
Port Chester (10523)
Zeus Components
100 Midland Avenule

-\-v"'
li: ?n:~~~~1248
FAX: 914-937-2553

~~ft~~JA~n~~3J61

2060 Town Line Road

V~~~ A~~~~:g119

WX: 810-459-1622
FAX: 513-236-8133

IMA§.

Dayton (45414)
Zeus Components
3500 Park Center Drive

Quall~

l~rX) ~~~~drcle

~513)

454-1225
AX: 513-454-0494

AX: 214-250-0216

Solon (44139)
Hamiiton/Avnet, N62

19f~f ~~~~.l'e Rd., Bldg. A

X: 810-427-2701
FAX: 216-248-2312

~ffg ~~7tRf;~~t~ve.

~~r~~~~~v~~~8ij9

Westbury (11590)
Hamilton/Avnet, N39
12fg Olg9~~~~'l Road

OKbeHOMA

~~*1 mj5?~520

516-997-6375

W~:

Addison (75001)
Components

mgr

Ronkonkoma (11779)

~Ax1

WX: 710-795-3122
FAX: 412-963-8255

Solon (44139)
Marshall Industries
~~~.?1~~~e Rd, Unit A

f16) 235
WX: 510
FAX: 716

W.

510-221-2184
FAX: 516-921-2143

NORTH CAROLINe
Charlotte (28209)
Future Electronics
1515 MOCkl'Slbblrd Lane, Ste, 801

V04)
529-5 0
AX: 704-627-2222

Charlotte (28210)
Pioneer Tech,
9801-A Southern Pine Blvd.

f-Z'): ~~b:g~8~66
FAX: 704-522-8564

~~~IR~n{Tl~':i,

#24
3510 Spring Forrest Road

¥Ut9)X: 510-928-1836
878-0819. X210
FAX: 919-872-4435

~~I~~~~II(f~3u~~ies

5221 N. Blvd,

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Suite 120

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rAX: 216-349-1694

Rochester (14623)
Marshall industries
1250 Scot

Plttsburgh(15222)
Hamllton/Avnet, #43
2800 Liberty Avenue, Bldg. E.

Pittsburgh (15238)
Pioneer Std.

ft~5) in~r;r_~~60BIVd.

AX: 614-882-8650

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Ste # 274

OBEGON
Beaverton (97005)
Marshall Industries
8333 S. W. Cirrus Dr.
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644-5050
AX: 503-646-8256

~S~ ~~rrl~~e?~~~;Parkway
Suite 600
~503)

640-6000
AX: 503-640-5846

Lake Oswego (97034)
Hamliton/Avnet, N27
6024 S. W, Jean Road

1W~ C6:ls~~~610

: 910-455-8179
FAX: 503-636-1327

FAX: 919-872-2431

8504 Cross Park Dr,

~~~15~~~~~81O

W12)
835-4000
AX: 512-835-9829

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~~~1 ~~:g5§~9252
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21~O-F

W. Braker Lane

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Tulsa (74146)

Hillsboro (97124)

~~? 5~~~~J232
C,~~~~air?~JjJtrles

Austin (78758)

Tulsa (74146)
Hamilton
12121 E. 51st St., Suite 102

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~~1 g~~:g~J~8515

Austin (78758)
Hamliton/Avnet, N26
l807A W, Braker

Austin (78758)
Pioneer Std,
18260 Kramer Lane

l~~4~rgg~:7~g2e Boulevard

~~12l~~~~064

Richardson (75081)

FAX: 412-281-8662

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g~8j~g~1735
FAX: 513-898-9636

Richardson (75083)
Wyte DistrIbution
1810 N. Greenville Avenua

FAX: 215-674-3107

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3520 Park Center Dr.

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Dayton (45459)
Hamllton/Avnet, #64

275 Oser Avenue
~516J 273-2424 and

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Carrollton (75006)
Marshall Industries
2045 Chenault St.

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Dallas (75244)
Pioneer Std,

p

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AX: 214-490-6419

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~~~12~~:2~~~385

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4~fg ~~~~j~oad 190

~AX1713-240-0582

Sugarland (77478)
Quality Components
1005 Industrial Rd.

~~~1 ng:~~~988

1!IAt:i
Salt Lake City (84119)

Hamllton/Avnet, N09
1585 West 2100 South

~~l g6~:~~~~9266

Salt Lake City (84115)

Marshall IndustrIes
466 Lawndale Dr., Ste. NC

~~~ :g~:J~¥~936

West Valley City (84119)

~~~ ~~~~W~~S-EMG
Ste. E

~~~1 ~bt2~~2524

WeSHINGTON

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11715 N, Creek Pkwy, South
Suite 112

~~* 118t~~~?6964

~:~rnf~~/A~~~~~)#07
17761 N. E. 78th PI.

~~1 ~gJ:g~~?0159
Redmond (98052)

~~~5
~~1

~~n s~~~~r

f?1567

WISCONSIN
Milwaukee (53214)
Marsh ElectroniCS, Inc,
1563 South 101st Street

~~~~h~~1 \~~~:~lles
lm)
L8aS"l~~00

~'li: ~~5j~~:>:'321

Houston (77036)
Pioneer Std,
5853 Point West Drive

Waukesha (53186)
Beli
W227N913 W. Mound Dr,

AX: 713-462-6714

V~17~~~~7t~732
tt9~~t~~s~~~~~rJn
11~01

~713)

S, Wilicrest, Ste,100

879-9953
AX: 713-879-6540

~~9It
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