1989_TI_First Generation_TMS320_Users_Guide 1989 TI First Generation TMS320 Users Guide

User Manual: 1989_TI_First-Generation_TMS320_Users_Guide

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"TEXAS

INSTRUMENTS

First-Generation
TAfS32 0

1989

Digital Signal Processor Products

First-Generation
TAfS320
User's Guide

TEXAS

INSTRUMENTS

1M PO RTAI\IT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to discontinue
any semiconductor product or service identified in this publication without
notice. TI advises its customers to obtain the latest version of the relevant information to verify. before placing orders, that the information being relied
upon is current.
TI warrants performance of its semiconductor products to current specifications in accordance with Tl's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to supportthis
warranty. Unless mandated by government requirements. specific testing of
all parameters of each device is not necessarily performed.
TI assumes no liability for TI applications assistance. customer product design,
software performance. or infringement of patents or services described herein.
Nor does TI warrant or represent that license. either express or implied. is
granted under any patent right, copyright. mask work right. or other intellectual property right of TI covering or relating to any combination, machine, or
process in which such semiconductor products or services might be or are
used.

iii

Contents
Section

Page

1
1.1
1 .2
1.3
1.4
1.5

Introduction
General Description
Key Features
Typical Applications
How To Use This Manual
References
...... .

1-1
1-4
1-6
1-8
1-9
1 -11

2
2.1
2.2
2.3

Pinouts and Signal Descriptions
TMS320C1 x Pinouts . . . . . . . . . . . . .
TMS3201 0/C1 0/C15/E15 Signal Descriptions
TMS320C17/E17 Signal Descriptions

2-1

3
Architecture
3.1
Architectural Overview
Functional Block Diagrams
3.2
3.3
Internal Hardware Summary
3.4
Memory Organization
3.4.1
Data Memory
3.4.2
Program Memory
3.4.3
Data Movement
3.4.4
Memory Maps
Auxiliary Registers
3.4.5
3.4.6
Memory Addressing Modes
Central Arithmetic Logic Unit (CALU)
3.5
3.5.1
Shifters. . . . . . . . . . .
3.5.2
ALU and Accumulator
3.5.3
Multiplier, T and P Registers
3.6
System Control . . . . . . . .
3.6.1
Program Counter and Slack
3.6.2
Reset
...... .
Status Register
3.6.3
3.7
Input/Output Functions
Input/Output Operation
3.7.1
3.7.2
Table Read/Table Write Operation ..
3.7.3
General-Purpose I/O Pins (BIO and XF)
Interrupts . . . . . . . . . . .
3.8
Serial Port (TMS320C17/E17)
3.9
3.9.1
Receive Registers . . . . . . . . . . . .
.......... .
3.9.2
Transmit RE';gisters
3.9.3
Timing and Framing Control . . . . . .
3.10 Companding Hardware (TMS320C17/E17)
IJ-Law/A-Law Encoder . . . . . . . . .
3.10.1
3.10.2
IJ-Law/A-Law Decoder . . . . . . . . .
3.11 Coprocessor Port (TMS320C17/E17)
3.12 System Control Register (TMS320C17/E17)

2-2
2-3
2-5

3-1
3-3
3-5
3-7
3-10
3-10
3-11
3-13
3-13
3-14
3-16
3-17
3-18
3-19
3-21
3-22
3-22
3-24
3-25
3-27
3-28
3-30
3-31
3-32
3-36
3-36
3-39
3-41
3-43
3-44
3-45
3-46
3-51
v

Assembly language Instructions
4.1
Memory Addressing Modes
4.1.1
Direct Addressing Mode
4.1.2
Indirect Addressing Mode
4.1.3
Immediate Addressing Mode
4.2
Instruction Set . . . . . . . .
4.2.1
Symbols and Abbreviations
4.2.2
Instruction Set Summary
4.3
Individual Instruction Descriptions

4-1

5-1

5.1
5.1.1
5.1.2
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.4
5.4.1
5.4.2
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.5.7
5.5.8
6.6
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6

Software Applications
Processor Initialization
........ .
TMS3201 0/C1 0/C15/E15 Initialization
... .
TMS320C17E1V Initialization
Interrupt Managem~nt
" ....... .
TMS3201 0/C1 0/C15/E15 Interrupt Service Routines
TMS320C17/E17 Interrupt Service Routines
BIO Polling
Context Switching
Program Control.
Software Stack Expansion
Subroutine Calls
Addressing and Loop Control with Auxiliary Registers
Computed GOTOs
Memory Management
........ .
Moving Data
. . . . . . . . .
Moving Constants into Data Memory
Logical and Arithmetic Operations
Bit Manipulation
Overflow Management
Scaling
....... .
Convolution Operations
Multiplication
Division . . . . . . . .
Addition . . . . . . . .
Floating-Point Arithmetic
Application-Oriented Operations
Companding
FIRIIIR Filtering
..... .
Adaptive Filtering . . . . . .
Fast Fourier Transforms (FFT)
PID Control .,
Selftest Routines . . . . . .

4-2
4-2
4-4
4-6
4-7
4-7
4-8
4-11

5-3
5-3
5-4
5-7
5-7
5-10
5-12
5-13
5-16
5-16
5-17
5-19
5-22
5-23
5-23
5-25
5-29
5-29
5-30
5-31
5-32
5-33
5-36
5-39
5-40
5-42
5-42
5-46
5-47
5-50
5-55
5-56

6
6.1
6.1.1
6.1.2
6.2
6.3
6.4

Hardware Applications
Expansion Memory Interface
Program ROM Expansion
Data RAM Expansion
Codec Interface . . . .
A/D and 0/ A Interface
I/O Ports
..... .
6.5
Coprocessor Interface
6.6 System Applications
6.6.1
2400 bps Modem . . .
Speech Synthesis System
6.6.2
Voice Store-and-Forward Message Center
6.6.3

8
C

D
E
F
G

First-Generation TMS320 Data Sheet
SMJ32010/C10 Data Sheets
ROM Codes
Quality and Reliability
Development Support/Part Order Information
Memories, Analog Converters, Sockets, and Crystals
Programming the TMS320E15/E17 EPROM Cell

6-1

6-2
6-2

6-4
6-6
6-8
6-10

6-11
6-13
6-13
6-13
6-15
A-1
8-1
C-1
D-1
E-1
F-1
G-1

vii

Illustrations

Figure
1-1
2-1
3-1
3-2

3-3
3-4
3-5
3-6
3-7
'3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-.26
3-27
3-28
3-29
3c30
3-31
4-1
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
C-1
E-1

viii

Page

TMS320 Device Evolution
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. 1 -2
TMS320C1 x Pin Assignments
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-2
TMS3201 0/C1 0/C15/E15 Block Diagram
. . . . . . . . . . . . .. . . . . . . . . . .. 3-5
TMS320C17/E17 Block Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ,3-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-11
On-Chip Data Memory
External Program Memory Expansion Example ., ................... , 3-12
Memory Maps for the TMS3201 0/C1 0 ............................ , 3-13
Memory Maps for the TMS320C15/E15 and TMS320C1 7 /E17.
. ....... '3-14
Auxiliary Register Counter ...................................... 3-15
Indirect Addressing Autoincrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-15
Indirect Addressing Autodecrement
. . . . . . . . . . . . . . . . . . . . . . . . . .. . .. 3-16
Methods of Instruction Operand Addressing
........' . . . . . . . . . . . . . .. 3-16
Central Arithmetic Logic Unit (CALU)
........................... , 3-17
Instruction Pipeline Operation ...'................................ 3-23
Status Register Organization ............. . . . . . . . . . . . . . . . . . . . . . .. 3~26
TMS320C1 x External Device Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-28
Input Instruction Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-29
Output Instru.ction Timing ...................................... 3-29
TBLR Instruction Timing ................... . . . . . . . . . . . . . . . . . . .. 3-30
TBLW Instruction Timing
........•............................ , 3-30
TMS320C1 x Simplified Interrupt Logic Diagram
. . . . . . . . . . . . . . . . . . .. 3-33
Interrupt Timing
. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-34
Interrupt Latch and Multiplexer .................................. 3-35
Serial Port and Companding Hardware ............................ 3-37
Receive Timing for External Framing .............................. 3-37
Fixed-Data Rate for Internal Framing
............................ , 3-38
Variable- Data Rate for Internal Framing
. . . . . . . . . . . . . . . . . . . . . .. . . .. 3-39
Transmit Timing for External Framing
. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-40
Serial:Port Timing and Framing Control
. . . . . . . . . . . . . . . . . . . . . . . . . .. 3-41
TMS320C17/E17 Simplified Coprocessor Port Logic Diagram
........ , 3-46
External Write Timing to the CoprocessOi Port .. . . . . . . . . . . . . . . . . . . .. 3-50
External Read Timing from the Coprocessor Port
.. . . . . . . . . . . . . . . . . .. 3-50
System Control Regist~r
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-51
Direct Addressing Block Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
Long Division and SUBC Division
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-37.
Minimum Program ROM Expansion
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
EPROM Interface to the TMS320C1 0-14 .. . . . . . . . . . . . . . . . . . . . . . . .. 6-4
Data RAM Expansion
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. 6-5
Codec Interface for Standalone Serial Operation
. . . . . . . . . . . . . . . . . . .. 6-7
AID Converter to TMS320C1 0/C15/E15/C17 /E17 Interface ........... 6-8
D/A Converter to TMS320C1 0/C15/E15/C17 /E17 Interface ........... 6-9
I/O Port Interface Circuit ....................................... 6-10
TMS320C17 /E17 to TMS70C42 Interface
. . . . . . . . . . . . . . . . . . . . . . . .. 6-11
TMS320C17/E17 to TMS320C25 Interface
. . . . . . . . . . . . . . . . . . . . . . .. 6-12
2400 bps Modem
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-13
Speech Synthesis System
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-14
Answering Machine
. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-15
TMS320 ROM Code Flowchart
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. C-2
TMS320C1 x Development Tools
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. E-2

E-2
E-3
E-4
E-5
E~6

E-7
F-1
G-1

G-2
G-3
G-4
G-5
G-6
G-7

TMS320C1 x Development Tools
............................... .
TMS320C1 x EVM/Single-User System
.......................... .
TMS320C1 x XDS/22 System Configuration
...................... .
TMS320 AlB System Configuration
............................. .
TMS320 Device Nomenclature
................................. .
TMS320 Development Tool Nomenclature ........................ .
.......................................... .
Crystal Connection
EPROM Adaptor Socket
...................................... .
EPROM Programming Data Format
............................. .
TMS320E15/E17 EPROM Conversion to TMS27C64 EPROM Pinout
.................................. .
Fast Programming Flowchart
..................................... .
Fast Programming Timing
EPROM Protection Flowchart .................................. .
EPROM Protection Timing
.................................... .

E-2
E-5
E-7
E-9
E-17
E-18
F-144
G-1

G-2
G-3
G-6
G-7
G-9
G-10

Tables

Table
1 -1

1-2
2-1

2-2
3-1
3-2
3-3
3-4
3-5
3-6
4-1
4-2
5-1
5-2
0-1
0-2
E-1
E-2
E-3
F-1
G-1

G-2

Page
TMS320C1 x Processors Overview
.............................. .
....................... .
Typical Applications of the TMS320 Family
TMS3201 0/C1 0/C15/E15 Signal Descriptions
.................... .
TMS320C17/E17 Signal Descriptions
........................... .
TMS320C1 x Internal Hardware ................................. .
....................... .
Accumulator Results of a Logical Operation
Status Register Field Definitions ................................ .
........ .
Serial Clock (SCLK) Divide Ratios (X2/CLKIN = 20.48 MHz)
...................... .
Serial- and Parallel-Mode Bit Configurations
................................ .
Control Register Bit Definitions
......................................... .
Instruction Symbols
Instruction Set Summary ...................................... .
................................ .
Control Register Bit Definitions
Program Space and Time Requirements for IJ-/A-Law Companding
........................ .
Microprocessor and Microcontroller Tests
TMS320C1 x Transistors
...................................... .
TMS320C1 x Digital Signal Processor Part Numbers
................ .
TMS320C1 x Support Tool Part Numbers
......................... .
................. .
Development Tool Connections to a Target System
............................ .
Commonly Used Crystal Frequencies
TMS320E15/E17 Programming Mode Levels ...................... .
TMS320E15/E17 EPROM Protect and Protect Verify Mode Levels

1-4
1-8
2-3
2-5
3-8
3-20
3-25
3-42
3-44
3-52
4-7
4-9
5-5
5-42
0-5
0-5
E-13
E-14
E-15
F-144
G-4
G-8

Section 1

Introduction

The TMS320 family of 16/32-bit single-chip digital signal processors ,combines the flexibility of a high-speed controller with the numerical capability of
an array processor, offering an inexpensive alternative to custom VLSI and
multichip bit-slice processors.

The TMS3201 0, the first digital signal processor in the TMS320 family, was
introduced in 1983. During that year, the TMS32010 was named "Product
of the Year" by the magazine, Electronic Products. Its powerful instruction set,
inherent flexibility, high-speed number-crunching capabilities, and innovative
architecture have made this high-performance, cost-effective processor the
ideal solution to many telecommunications, computer, commercial, industrial,
and military applications.

The TMS320 family has now expanded into three generations of processors:
TMS320C1 x, TMS320C2x, and TMS320C3x (see Figure 1-1). Many features
are common among these generations. Some specific features are added in
each processor to provide different cost/performance tradeoffs. Software
compatibility is maintained throughout the family to protect the user's investment in architecture. Each processor has software and hardware tools to facilitate rapid design.

1-1

Introduction

32OC3O

TMS320C2x

32OE2&

.2T1.....
• DMA

.II44W_RAM
.4KW ROM/EPROM

.---

IL
• 128KWtoteI_
• 18 • 18 - 32-b1t ............

._portond_

TMS320C1x

.,---

• 32-b1t ftt-pt cJiU

.1_toteI_
·32.32- _ _
.2 _ _

• 18132-l1li
·80
... _CPU
_

320C2&

32010
320CiO
320C14
320E14
320Cll
3ZOEli
320C17
320E17

._1_-

• ZKWRAM
·4KW'ROM
• 84W _ _

32020

TMS320C3x

• _ _ UF

• 18J32-bIt CPU

• _ _ RAM

.--

.4KWROM/EPROM
• 4kW ext prog l1*li

• 18 • 18 - 32-b1t_

·TImon

....

TIME

Figure 1-1. TMS320 Device Evolution

Throughout this document, the first-generation device group within the
, TMS320 family will be referred to as TMS320C1 x. The specific 'members of
the first-generation TMS320 include:
•

TMS32010, the first 20- M Hz digital signal processor

•

TMS320C10, a CMOS 20-MHz version of the TMS3201 0

•

TMS320C1 0-14, a 14- M Hz version of the TMS320C1 0

•

TMS320C10-25, a 25- M Hz version of the TMS320C1 0

•

TMS320C14, aI TMS320C15 designed for a control system

•

TMS320E14, an EPROM version of the TMS320C14

•

TMS320C15, a TMS320C1 0 with expand~d ROM and RAM

•

TMS320C15-25, a 25-MHz version of the TMS320C15

•

TMS320E15, an EPROM version of the TMS320C15

•

TMS320E15-25, a 25- M Hz version of the TMS320E15

•

TMS320C17, a TMS320C15 with serial and coprocessor ports

•

TMS320E17, an EPROM version of the TMS32QC17

1-2

Introduction

This document describes the core CPU, memory, and basic I/O port architecture of the first-generation devices (TMS320C1 x) in the TMS320 family. The
peripherals for the TMS320C17/E17 devices are also described. For descriptions of the TMS320C14/E14 as well as software and hardware
applications/examples, refer to the TMS320C14/TMS320E14 User's Guide
(literature number SPRU032).
The TMS320 family combines the high performance and specialized features
necessary in digital signal processing (DSP) applications with an extensive
program of development support, including hardware and software development tools, product documentation, textbooks, newsletters, DSP design
workshops, and a variety of application reports. See Appendix E for a discussion of the wide range of development tools available.
Plans for expansion of the TMS320 family include more spinoffs of the existing generations as well as more powerful future generations of digital signal
processors.

1-3

Introduction - General Description

1.1 General Description
The combination of the TMS320's Harvard-type architecture (separate program and data buses) and its special digital signal processing (DSP) instruction set provides speed and flexibility to pr6duce a microprocessor family
,capable of executing 6.25 MIPS (million instructions per second). While
other. processors implement functions through software or microcode, the
TMS320 family optimizes performance by implementing functions within the
hardwarEl. This hardware-intensive approach provides the design engineer
with power previously unavailable on a single chip.
Table 1-1 provides an overview of the TMS320C1 x group of processors with
comparisons of technology, memory, I/O, cycle timing, package type, and
military support.

Table 1-1. TMS320C1x Processors Overview
MEMORY
I/O»
ON-CHIP
OFF-CHIP
RAM ROM EPROM
PROG
SER PAR
4K
NMOS 144 1.SK
8li16

DEVICE

TECH

TMS32010:t
TMS320C10:t
TMS320C10-14
TMS320C10-25
TMS320C14§
TMS320E14§

CMOS
CMOS
CMOS

144
144
144

1.5K
1.5K
1.5K

CMOS 256
CMOS 256

TMS320C1S§
TMS320C1S-25
TMS320E15§
TMS320E15-25

CMOS ,256
CMOS 256
CMOS 256
CMOS 256

4K
4K

4K
4K
4K

4K
4K

1
1

4K
4K
4K
4K

CYCLE
PACKAGE
TYPEt
TIME
(ns)
DIP PLCC CER
200

8x16
8)(16 .
8x16
7x16'!T
7x16'!T

200
280
160
160
160

40
40
40

44
44
44

8x16
8x16
8x16
8x16
6x16.r
6x16.r

200
160
200
160
200
200

40
40
40
40

44
44

-68

44
44

TMS320C17
CMOS 256
4K
2
44
40
TMS320E17
CMOS 256
4K
2
40
44
»SER = serial; PAR = parallel.
tOIP = dual in-line pin; PLCC = plastic leaded chip carrier; CER = surface mount ceramic leaded chip
carrier (CER-QUAO).
:tMilitary version available.
§Military versions planned; contact nearest TI Field Sales Office for availability.
'!Ton-chip 16-bit I/O, four capture inputs, and six compare outputs are available .
.rOn-chip 16-bit coprocessor interface is optional by pin selection ..

The first generation of the TMS320 family includes both NMOS and CMOS
products. The TMS32010 microprocessor is the only NMOS device. The
other members are processed in CMOS technology:
TMS320C10,
TMS320C10-14, TMS320C10-25, TMS320C14/E14, TMS320C15/E15,
TMS320C15-25/E15-25, and TMS320C17 /E17.
The TMS3201 0, the first TMS320 family member, is a microprocessor capable
of achieving a 16 x 16-bit multiply in a single 200-ns cycle. On-chip data
memory of 144 words is available. Up to 4K words of off-chip program
memory can be executed at full speed. The TMS3201 0 is also available in a
microcomputer version, with 1.5K words of on-chip program ROM and up to
2.5K words of off-chip program memory for a total of 4K words. This ROM1-4

Introduction - General Description

code version can also operate entirely from off-chip ROM for ease of prototyping, code update, and field upgradeability.
The TMS320C10 has a 200-ns instruction cycle time and is object-code and
pin-for-pin compatible with the TMS3201 o. The TMS320C1 0 is processed in
CMOS technology, achieving a power dissipation less than one-sixth that of
the NMOS device. Because of its low-power dissipation (165 mW), the
TMS320C10 is ideal for power-sensitive applications such as digital telephony and portable consumer products. A masked ROM option is available for
the TMS320C1 O.
The TMS320C10-14, a 14-MHz version of the TMS320C10, provides a
low-cost alternative for DSP applications not requiring the maximum operating frequency of the TMS320C10. The device can execute 3.5 million instructions per second and has a 280-ns instruction cycle time.
The TMS320C10-25, a 25-MHz version of the TMS320C10, has a 160-ns
instruction cycle time. Its lower power and higher speed make it well suited
for high-performance DSP applications.
The TMS320C14 and TMS320E14 are microcontrollers with an instruction
cycle time of less than 160-ns, 256 words of on-chip RAM, and 4K words of
on-chip program ROM (TMS320C14) or EPROM (TMS320E14). The
TMS320C14/E14 feature an event manager with four capture inputs and six
compare outputs, a bit-selectable I/O port, a serial port with programmable
protocols and timer, a watchdog timer, and two general-purpose timers. These
devices are object-code compatible with the TMS32010 and processed in
CMOS technology.
The TMS320C15 and TMS320E15 are fully object-code and pin-for-pin
compatible with the TMS32010. Each offers an expanded on-chip RAM of
256 words and an on-chip program ROM (TMS320C15) or EPROM
(TMS320E15) of 4K words. The devices are processed in CMOS technology.
Both are also available in the 160-ns versions, the TMS320C15-25 and
TMS320E15-25.
The TMS320C17 and TMS320E17 are dedicated microcomputers. Each offers 256 words of on-chip RAM and 4K words of on-chip program ROM
(TMS320C17) or EPROM (TMS320E17). The TMS320C17/E17 features a
dual-channel serial interface, on-chip companding hardware (Il-Iaw/A-Iaw),
a serial port timer, and a latched 16-bit coprocessor port for direct microprocessor I/O interface. The devices are object-code compatible with the
TMS32010 and processed in CMOS technology.

1-5

Introduction - Key Features

1.2 Key Features
Some of the key features of the TMS320C1 x devices are listed below and on
the following page. Specific devices for a particular feature are enclosed in
parentheses.

•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
1-6

Instruction cycle timing:
160 ns (TMS320C10-25/C14/E14/C15-25/E15-25)
200 ns (TMS3201 0/C,1 0'/C15/E15/C17 /E17)
.
280 n$ (TMS320C10-14)
144-/256-word on-chip data RAM
1.5K-/4K-word on-chip program ROM
4K-wOid on-chip program EPROM
(TMS320E14/E15/E15-25/E17)
EPROM code protection for copyright security
4K-word total external memory at full speed
(TMS32010/C1 0/C1 0-14/C1 0-25/C14/
E14/C15/C15-25/E15/E15-25)
16-bit bidirectional data bus at 50-Mbps transfer rate
32-bit ALU/accumulator

16~ x 16-bit parallel multiplier with a 32~bit prodUct
O~

to 16-bit barrel shifter

On-chip clock generator
Eight input and eight output channels
Dual-channel seria,l port with timer
(TMS320C17/E17)
Direct interface to combo-codecs
(TMS320C17/E17)
On-chip IJ-Iaw/A-Iaw companding hardware
(TMS320C17/E17)
16 c bit coprocessor interfac~
(TMS320C17/E17)
16-pin bit-selectable I/O ports
.
(TMS320C14/E14)
Serial. port with programmable protocols
(TMS320C14/Ef 4)
Event manager with capture inputs and compare outputs
(TMS320C14/E14)

Introduction - Key Features

•

Four independent timers (TMS320C14/E14)
General-purpose (2)
Serial port
Watchdog

•

15 external/internal interrupts
(TMS320C14/E14)

•

Single 5-V supply

•

Device packaging:
40-pin DIP (TMS3201 O/C1 O/C1 0-14/C1 0-25/C15/
C15~25/E15/E15-25/C17/E17)
,
44-lead PLCC (TMS320C1 O/C1 0-14/C1 0-25/C15/
C15-25/C17)
68-lead PLCC (TMS320C14)
'44-lead CER-QUAD (TMS320E15/E15-25/E17)
68-lead CER-QUAD (TMS320E14)

•

Technology:
NMOS (TMS32010)
CMOS (TMS320C1 O/C1 0-14/C1 0-25/C14/E14/C15/
C15-25/E15/E15-25/C17/E17)

•

Commercial and military versions available.

1-7

Introduction - Typical Applications

1.3 Typical Applications
The TMS320 family~s unique versatility and realtime performance offer flexible
design approaches in a variety of applications. In addition, TMS320 devices
can simultaneously provide the multiple functions often required in those
complex applications. Table 1-2 lists typical TMS320 family applications.

Table 1-2. Typical Applications of the ,TMS320 Family
GENERAL-PURPOSE DSP
Digital Filtering
Convolution
Correlation
Hilbert Transforms
Fast Fourier Transforms
Adaptive Filtering
Windowing
Waveform Generation

GRAPHICS/IMAGING
3- D Rotation
Robot Vision
Image Transmission/
Compression
Pattern Recognition
Image Enhancement
Homomorphic Processing
Workstations
Animation/Digital Map

VOICE/SPEECH
Voice Mail
Speech Vocoding
Speech Recognition
Speaker Verification
Speech Enhancement
Speech Synthesis
Text-to-Speech

CONTROL
Disk Control
Servo Control
Robot Control
Laser Printer Control
Engine Control
Motor Control

TELECOMMUNICATIONS
Echo Cancellation
ADPCM Transcoders
Digital PBXs
Line Repeaters
Channel Multiplexing
1200 to 19200-bps Modems
Adaptive Equalizers
DTMF Encoding/Decoding
Data Encryption

FAX
Cellular Telephones
Speaker Phones
Digital Speech
Interpolation (DSI)
X.25 Packet Switching
Video Conferencing
Spread Spectrum
Communications

CONSUMER
Radar Detectors
Power Tools
Digital Audio/TV
Music Synthesizer
Educational Toys

INDUSTRIAL
Robotics
Numeric Control
Security Access
Power Line Monitors
I

1-8

INSTRUMENTATION
Spectrum Analysis
Function Generation
Pattern Matching
Seismic Processing
Transient Analysis
[)igital Filtering
Phase-Locked Loops

MILITARY
Secure Communications
Radar Processing
Sonar Processing
Image Processing
Navigation
Missile Guidance
Radio Frequency Modems

AUTOMOTIVE
Engine Control
Vibration Analysis
Antiskid Brakes
Adaptive Ride Control
Global Positioning
Navigation
Voice Commands
Digital Radio
Cellular Telephones

MEDICAL
Hearing Aids
Patient Monitoring
Ultrasound Equipment
Diagnostic Tools
Prosthetics
Fetal Monitors

Introduction - How To Use This Manual

1.4 How To Use This Manual
The purpose of this user's guide is to serve as a reference book for the firstgeneration TMS320 digital signal processors. Sections 2 through 6 provide
specific information on architecture and operation of these devices. Appendix
A furnishes electrical specifications and mechanical data information.
The following table lists each section and briefly describes the section contents.

Section 2.

Pinouts anq Signal Descriptions. Drawings of the DIP and
PLCC packages for TMS320C1 x devices. Functional listings of the signals, their pin locations, and descriptions.

Section 3.

Architecture. TMS320C1 x design description, hardware
components, and device operation. Functional block diagrams and internal hardware summary table.

Section 4.

Assembly Language Instructions. Addressing modes and
format descriptions. Instruction set summary listed according to function. Alphabetized individual instruction
descriptions with examples.

Section 5.

Software Applications. Software application examples for
the use of various TMS320C1 x instruction set features.

Section 6.

Hardware Applications. Hardware design techniques and
application examples for interfacing to codecs, external
memory, or common 4-/8-/16-/32-bit microcomputers
and microprocessors.

Seven appendices are included to provide additional information.

Appendix A.

First-Generation TMS320 Data Sheets. Electrical specifications, timing, and mechanical data for all TMS320C1 x
devices.

Appendix B.

SMJ3201 O/C1 0 Data Sheets.
Electrical specifications,
timing, and mechanical data for these military devices.

Appendix C.

ROM Codes. Discussion of ROM codes (mask options)
and the procedure for implementation.

Appendix D.

Quality anq Reliability. Discussion of Texas Instruments
quality and reliability criteria for evaluating performance.

Appendix E.

Development Support/Part Order Information. Listings of
the hardware and software available to support the
TMS320C1 x devices.

1-9

Introduction - How To Use This Manual

)

1-10

Appendix F.

Memories; Analog Converters. Sockets. and Crystals.
Listings of the TI memories, analog conversion devices,
and sockets available to support the TMS320C1 x devices
in DSP applications. Crystal specifications and vendors.

Appendix G.

Programming the TMS320E15/E17 EPROM Cell. Procedure for programming and verifying the EPROM cell using
the 28-pin TMS27C64.

Introduction - References

1.5 References
The following reference list contains useful information regarding functions,
operations, and applications of digital signal processing. These books also
provide other references to many useful technical papers. The reference list is
organized into categories of general DSP, speech, image processing, and
digital control theory; if known, each category is alphabetized by the author's
last name.

General Digital Signal Processing:
Antoniou, Andreas, Digital Filters: Analysis and Design. New York, NY:
McGraw-Hili Company, Inc., 1979.
Brigham, E. Oran, The Fast Fourier Transform.
Prentice- Hall, Inc., 1974.

Englewood Cliffs, NJ:

Burrus. C.S. and Parks, T.W., DFT/FFT and Convolution Algorithms.
New York, NY: John Wiley and Sons, Inc., 1984.
Digital Signal Processing Applications with the TMS320 Family, Texas
Instruments, 1986; Prentice-Hall, Inc., 1987.
Gold, Bernard and Rader, C.M., Digital Processing of Signals.
York, NY: McGraw-Hili Company, Inc., 1969.
Hamming, R.W., Digital Filters.
Inc., 1977.

Englewood Cliffs, NJ:

New

Prentice-Hall,

IEEE ASSP DSP Committee (Editor), Programs for Digital Signal Processing. New York, NY: IEEE Press, 1979.
Jackson, Leland B., Digital Filters and Signal Processing. Hingham, MA:
Kluwer Academic Publishers, 1986.
Jones, D.L. and Parks, T.W., A Digital Signal Processing Laboratory
Using the TMS32010. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987.
Lim,Jae and Oppenheim, Alan V., Advanced Topics in
Processing: Englewood Cliffs, NJ: Prentice-Hall, Inc., 1988.

Signal

Morris, l. Robert, Digital Signal Processing Software. Ottawa, Canada:
Carleton University, 1983.
Oppenheim, Alan V. (Editor), Applications of Digital Signal Processing.
Englewood Cliffs, NJ: Prentice- Hall, Inc., 1978.
Oppenheim, Alan V. and Schafer, R.W., Digital Signal Processing. Englewood Cliffs, NJ: Prentice- Hall, Inc., 1975.
Oppenheim, Alan V. andWillsky, A.N. with Young, LT., Signals and
Systems. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1983.
Parks, T.W. and Burrus, C.S., Digital Filter Design. New York, NY: John
Wiley and Sons, Inc., 1987.

1-11

Introduction - References

Rabiner, Lawrence R. and Gold, Bernard, Theory and Application of Digital Signal Processing. Englewood Cliffs, NJ: Prentice- Hall, Inc., 1975.
Treichler, 'J.R., Johnson, Jr., C.R., and Larimore, M.G., Theory and Design of Adaptive Filters. New York, NY: John Wiley and Sons, Inc.,
, 1987.

Speech:
Gray, A.H. and Markel, J.D., Linear Prediction of Speech.
NY: Springer-Verlag, 1976.

New York,

Jayant, N.S. and Noll, Peter, Digital Coding of Waveforms. Englewood
Cliffs, NJ: Prentice- Hall, Inc., 1984.
.
Papamichalis, Panos, Practical Approaches to Speech Coding.
wood Cliffs, NJ: Prentice-Hall, Inc., 1987.

Engle-

Rabiner, Lawrence R. and Schafer, R.W., Digital Processing of Speech
Signals. Englewood Cliffs, NJ: Prentice-Hall, Inc.,
, 1978.

Image Processing:
Andrews, H.C. and Hunt, B.R., Digital Image Restoration. Englewood
Cliffs, NJ: Prentice-Hall, Inc., 1977.
Gonzales, Rafael C. and Wintz, Paul, Digital Image Processing. Reading,
MA: Addison-Wesley Publishing Company, Inc., 1977.
Pratt, William K., Digital Image Processing. New York, NY: John Wiley
and Sons, 1978.

Digital Control Theory:
Astrom, K. and Witten mark, B., Computer Controlled Systems.
wood Cliffs, NJ: Prentice-Hall, Inc., 1984.
Iserman, R., Digital Control Systems.
1981.

Engle-

New York, NY: Springer-Verlag,

Jacquot, R., Modern Digital Control Systems. New York, NY: Marcel
Dekker, Inc., 1981.
Katz, P., Digital Control Using Microprocessors. Englewood Cliffs, NJ:
Prentice- Hall, Inc., 1981.
Kuo, B.C., Digital Control Systems. New York, NY: Holt, Reinholt and
Winston, Inc., 1980.
Moroney, P., Issues in the Implementation of Digital Feedback Compensators. Cambridge, MA: The MIT Press, 1983.
Phillips, C. and Nagle, H., Digital Control System Analysis and Design.
Englewood Cliffs, NJ: Prentice- Hall, Inc., 1984.

1-12

Section 2

Pinouts and Signal Descriptions

The TMS320C1 x (first-generation TMS320) digital signal processors, except
TMS320C14 and TMS320E14, are available in a 40-pin dual-in-line (DIP)
package. The TMS320C14 is only available in the 68-pin plastic-leaded chip
carrier (PLCC) and the TMS320E14 is only available in a 68-pin CER-QUAD
package. The TMS320C10 and TMS320C15/C17 are also packaged in a
44-pin plastic-leaded chip carrier (PLCC). The TMS320E15 and TMS320E17
are available in 44-pin CER-QUAD packages, too.
This section provides the pinouts and signal definitions in the following
subsections:
•

TMS320C1 x Pinouts (Section 2.1 on page 2-2)

•

TMS3201 O/C1 O/C15/E15 Signal Descriptions (Section 2.2
on page 2-3)

•

TMS320C17/E17 Signal Descriptions (Section 2.3 on page 2-5)

Electrical specifications and mechanical data are given in Appendix A which
contains the First-Generation TMS320 and the TMS320C14/E14 data sheets.
For pinouts used in programming the TMS320E14/E15/E17 EPROMs, refer
to Appendix G.

2-1

Pinouts - TMS320C1x

2.1 TMS320C1x Pinouts
Figure 2-1 shows pinouts of the 0.1 P packages for the TMS320C1 x devices
and the PLCC packages for the TMS320C10/C15/C17. 'For pinouts of the
TMS320C14/E14, see Appendix A or refer to the TMS320C14/TMS320E14
\
User's Guide (literature number SPRU032).
TMS32010. TMS320Cl0
TMS320C1S. TMS320E1S
N/JD PACKAGE
ITOPVIEWI
Al/PAl
AO/PAO
MC/MP
RS
INT
CLKOUT
Xl
X2/CLKIN
BID

TMS320C17. TMS320E17
N/JD PACKAGE
ITOP VIEWI
PA1/RBLE
PAO/HI/LO

A2/PA2
A3
A4
A5
A6
A7
A8
MEN
DEN
WE

Vss
08
09
010
011
012
013
01'4
015
07
06

PA2/TBLF
FSR
FSX
FR
OXl

DXO
Xl
X2/CLKIN
BIO

,SCLK
ORl
OEN/RO
WE/WR

VSS
08/L08
09/LD9
010/L010
011/LOll
012/L012
013/L013
014/L014
015/L015
07/L07
06/L06

VCC
A9
Al0
All
DO
01
02
03
04
05'

VCC
ORO
XF
MC/PM
OO/LOO
01/LOl
02/L02
03/L03
04/L04
05/L05
TMS320C17
FN PACKAGE

TMS320Cl0.TMS320C1S
FN PACKAGE
ITOPVIEWI

In..~

0.....

~ ~ (/)~

fU (3;:
'~a;;:;

ITO~VIEWI

Igl~
::::1]]

cnN

M..:t Ln.--CO

« « >« « « «'«

8
9
10
11

;;:

O.-(I)Na:X"-

wa::..::Q.Q.

39! A7
38! A8
37[ MEN
DEN
35! WE

36!

VSS 12
08 13
09 14
010 15
011 16
012 17

34! VCC

33
32!
31!
30
29

1819202122232425262728
VlMq-U'lr--.(OLOoq-MN(J)

(/)---000000(/)
>000
>

A9
Al0
,All
DO
01

CLKOUT
Xl
X2 CLKIN
BID
NC
VSS
08/LOB
09/L09
010/L010
011/LOll
012/L012

7
0
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 2021 22 23 24 25 26 2728
V,)M'¢Il)r--.CDU')~MNN

(/)---0000000

>CCO...J...J...J...J...J...J...J

_ _ _ f'COtn,¢MC\I_
....J...J...J------M~"'OOOOOOO
000

Figure 2-1. TMS320C1x Pin Assignments

2-2

a;;

a..LLLLLL ......

6 5 4 3 2 1 4443424140

6 5 4 3 2 1 44 43 42 41 40

CLKOUT
X)
X2/CLKIN
BID
NC

I~al

I I(/) !;I, « « >(/) t:« I(/) I(/)
f~
X

OXO
SCLK
ORl
OEN/RO
WE/WR
VCC
ORO
XF
MC/PM
OO/LOO
VSS

Signal Descriptions - TMS3201 OlC1 O/C15/E15

2.2 TMS3201 O/C1 O/C15/E15 Signal Descriptions
The signal descriptions for the TMS3201 O/C1 0 and TMS320C15/E15 devices
are proyided in this section. Table 2-1 lists each signal, its pin location
(DIP/PLCC), function, and operating mode(s). i.e., input, output, or highimpedance state as indicated by I, 0, or Z. The signals in Table 2-1 are
grouped according to function and alphabetized within that grouping.

Table 2-1. TMS32010/C10/C15/E15 Signal Descriptions
SIGNAL

PIN
(DIP/PLCC)

I/O/Zt

DESCRIPTION

ADDRESS/DATA BUSES
A11 MSB
A10
A9
A8
A7
A6
A5
A4
A3
A2/PA2
A1/PA1
AO/PAO
D15 MSB
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
DO LSB

27/31
28/32
29/33
34/38
35/39
36/40
37/41
38/42
39/43
40/44
1/2
2/3
18/21
17/20
16/19
15/17
14/16
13/15
12/14
11/13
19/22
20/23
21/24
22/25
23/26
24/27
25/29
26/30

Program memory address bus A11 (MSB) through AO (LSB)
and port addresses PA2 (MSB) through PAO (LSB).
Addresses A11 through AO are always active and never
go to high impedance. During execution of the I Nand
OUT instructions. pins A2 through AO carry the port
addresses. (Address pins A11 through A3 are always
driven low on IN and OUT instruction)

I/O/Z

Parallel data bus D15 (MSB) through DO (LSB). The data
bus is always in the high-impedance state except when
WE is active (low).

INTERRUPT AND MISCELLANEOUS SIGNALS

Bi'O

9/10

External polling input. Polled by BIOZ instrllction. If low.
the device branches to the address specified by the instruction.

DEN

32/36

Data enable for device input data. When active low. 'i5EN'
indicates that the device will accept data from the data bus.
DEN is onl." active during the first c~ of the IN instruction. When DEN is active. 'MEN and E will always be inactive (high).

t Input/Output/High-impedance state

2-3

Signal Descriptions - TMS32010/C10/C15/E15

Table 2-1. TMS32010/C10/C15/E15 Signal Descriptions (Concluded)
SIGNAL

DESCRIPTION

PIN
(DIP/PLCC)

I/O/zt

iNi'

5/6

External interrupt input. The interrupt S~I is generated by
applying a negative-going edge to the I T pin. The edge is
used to latch the interrupt flag register (I NTF) until an interrupt is gral)ted by the device. An active low level will also
be sensed.

MC/-;;;W

3/4

Memory mode select pin. High selects the microcomputer
mode, in which 1.5K words (4K on the TMS320C15/E15)
of on-chip program memory are available. This mode also
allows an additional 2.5K words of program memor~ reside off-chip on the TMS3201 0/C1 O. A low on MC/ P pin
enables the microprocessor mode. In this mode, the entire
memory space is external, i.e., addresses 0 through 4095.

Memory enable. iiifEii1 will be active low on every machine
cycle except when WE and DElii are active. iiifEii1 is a control
signal generated by the device to enable instruction fetches
from program memory. iiifEii1 will be active on instructions
fetched from both internal and external memory.

Reset input for initializing the device. When held at an active low for a minimum of five clock cycles, DElii, WE, and
MEN are forced high; and, the data bus (015 through DO)
is not driven. The program counter (PC) and the address
bus (A11 through AO) are then synchronously cleared after
the next complete clock cycle from the falling edge of itS.
Reset also disllbles the interrupt, clears the interrupt· flag
register, and leaves the overflow mode·register unchanged.
The device can be. held in the reset state indefinitely.

Write enable for device output data. When active low, WE
indicates that data will be output from the device on the
data bus. WE is only active during the first cycle of the OUT
instruction and the second cycle of the TBlW instruction.
When WE is active, MEN and DElii wifl always be inactive
(high).

itS

33/37

4/5

31/35

SUPPLY/OSCilLATOR SIGNALS
6/7

Vee

30/34

5-V supply pin.

VSS
X1

10/12

Ground pin.

7/8

Crystal output pin for internal oscillator. If the internal oscillator is not used, this pin should be left unconnected.

8/9

Input pin to thl3 internal oscillator (X2) from the crystal. Alternatively, an input pin for an external oscillator (ClKIN).

ClKOUT

X2/ClKIN

t Input/Output/High-impedance state

2-4

System clock output (one-fourth crystal/ClKIN frequency).
Duty cycle is fifty percent.

Signal Descriptions - TMS320C17/E17

2.3 TMS320C17/E17 Signal Descriptions
Table 2-2 lists each signal provided on the TMS320C17 IE17, its pin location,
function, and operating mode(s), i.e., input, output, or high-impedance state
as indicated by I, 0, or Z. The signals in Table 2-2 are grouped according to
function and alphabetized within that grouping. Note that the first signal and
the signal following the slash are both used on the TMS320C17 IE17.

Table 2-2. TMS320C17/E17 Signal Descriptions
SIGNAL

PIN
(DIP/PLCC)

I/O/zt

DESCRIPTION

BIDIRECTIONAL DATA BUS
D15/LD15
D14/LD14
D13/LD13
D12/LD12
D11/LD11
D10/LD10
D9/LD9
D8/LD8
D7/LD7
C6/LD6
D5/LD5
D4/LD4
D3/LD3
D2/LD2
D1/LD1
DO/LDO

18/21
17/20
16/19
15/17
14/16
13/15
12/14
11/13
19/22
20/23
21/24
22/25
23/26
24/27
25/28
26/30

I/O/Z

During the microcomputer mode. this represents a 16-bit
parallel data bus (015 through DO). The data bus is
always in the high-impedance state. except when WE is
active (low) or when an IN instruction is being executed
from either port 0 or port 1.
During the coprocessor mode. the 16-bit data lines (LD15
through LDO) is used for a coprocessor latch. The data
bus is always held in a high-impedance state. except
when RD is active (low).

PORT ADDRESS BUS
PA2/'i1rrF
PA1/RBLE
PAO/HI/U5

40/44
1/2
2/3

0
0
I/O/Z

I/O port address output/transmit buffer latch full flag.
I/O port address output/receive buffer latch empty flag.
I/O port address output/latch byte select pin.
During the microcomputer mode. these pins carry the port
address when using the IN and OUT instructions. When
using other instruction cycles. these pins carry the three
LSBs of the program counter.

D~ring the coprocessor mode. these pins signal the status
of the receive and the transmit buffer latches.
INTERRUPT AND MISCELLANEOUS SIGNALS

9/10

External polling input. Polled by BIOZ instruction. If low.
the device branches to the address specified by the instruction. When in the coprocessor mode. the BiO line is reserved for coprocessor interface and .cannot be driven
externally.

t Input/Output/High-impedance state

2-5

Signal Descriptions - TMS320C17/E17

Table 2-2. TMS320C17/E17 Signal Descriptions (Continued)
SIGNAL

15m/lID

PIN
(DIP/PLCC)

I/O/zt

32/36

I/O/Z

DESCRIPTION
Data enable for device input data/external read for the output latch. When active low. 15m indicates that the device
will accept data from the data bus. DEN is only active durjng
the first cycle of the IN instruction. WE will always be inactive (high) when
is active. In the coprocessor mode.
the external processor reads from the coprocessor latch by
driving the RI5 line active (low). thus enabling the output
latch to drive the latched data. When the data has been
read. the external device will bring the RI5 line high.

E5 = phase of internal clock.
NOTE: The TMS3201 0 requires external synchronizing flip-flops. '

Figure 3-19. TMS320C1x Simplified Interrupt Logic Diagram

3-33

Architecture - Interrupts

Figure 3-20 shows the instruction sequence that occurs once an interrupt
becomes active. The dummy fetch is an instruction that is fetched but not executed. This instruction will be refetched and executed after the interrupt
routine is completed.
The TMS320C17 IE17 has four maskable interrupts: EXINT, FSR, FSX, and FR.
On these devices, the TMS3201 0/C1 0/C15 interrupt function has been ex- i
panded to fully support the serial-port interface. An interrupt latch and multiplexer is used to generate the master interrupt signal, which functions
identically to the INT interrupt on the TMS32010. Thus, all the maskable interrupts have the same priority and require the use of interrupt polling techniques when multiple interrupts are enabled.
Two steps must be taken to enable an active interrupt to the device. First, the
individual interrupt must be enabled by writing a logic 1 to the appropriate
system control register bit (CR7-CR4). Then, the master interrupt circuitry is
enabled via the EINT instruction. An interrupt flag represents a valid interrupt
condition to the processor if interrupts have been enabled. Thus, prior to enabling interrupts, the flag bits of all undesired interrupts should be cleared. In
the coprocessor port mode, the external interrupt (EXINT) flag cannot be
cleared until four cycles after the data from the coprocessor port has been
read. In a reset initialization routine, the interrupt flag bits (CR3-CRO) should
be cleared before the EINT instruction to insure that a false interrupt does not
occur (see Section 3.12 for detailed interrupt bit descriptions);

CLKOUT

INT

1. . _-.-.. .

~ CLOCK CYCLE MINI
FETCH
INSTRUC1l0N N

DUMMY FETCH
INSTRUC1l0N N + 1

FETCH
INSTRUCTION 002

EXECUTE N

DI,lMMY CYCLE

Figure 3-20. Interrupt Timing

3-34

EXECUTE 002

Architecture - Interrupts

The interrupt latch synchronizes all interrupts to the device output clock
(CLKOUT). A block diagram of the interrupt latch and multiplexer is shown
in Figure 3-21.
The external interrupt flag (EXINT) is set by one of two conditions: (1) an
asynchronous input to the device for external control, or (2) a master processor interrupt signal when the TMS320C17/E17 is being operated in coprocessor mode. The EXINT flag cannot be cleared while an interrupt condition is
presented.
The other three interrupts are normally associated with the serial port framing
signals. A bit in the system control register (CR9) designates whether FR is
to be used for framing or alternatively, FSX and FSR. When FSX and FSR control
the serial port framing, FR can function as an independent timer interrupt with
the timer clocked by the SCLK ,source. When the serial port is controlled by
the internal framing pulse (FR), the FSX and FSR inputs are available as independent edge-triggered interrupts.
Due to the asynchronous operation of the interrupts, the time between the
occurrence of an active interrupt signal and the device actually vectoring to
ROM location 2 is four CLKOUT cycles; see Appendix A for further timing
information.

FSR FSX EXINT FR CR7-CRO

CLKOUT--~

MASTER
INTERRUPT
SIGNAL (MIS)

'--...0001---

FR MUX
OUTPUT

INTERRUPT
FLAG BITS
CR3-CRO

Figure 3-21. Interrupt Latch and Multiplexer

3-35

Architecture - Serial Port

3.9 Serial Port (TMS320C17/E17)
Two of the I/O ports on the TMS320C17/E17 are dedicated to the serial port
and companding hardware. I/O port 0 is dedicated to control register 0, which
controls the serial port, interrupts, and companding hardware. I/O port 1 accesses control register 1, as well as both serial port channels, and the companding hardware. The six remaining I/O ports are available for external
parallel interfaces.
The on-chip dual-channel serial port, provided on the TMS320C17/E17, is
capable of full-duplex serial communications and direct interface to combocodec PCM systems, serial A/D converters, and other serial systems. The interface signals are directly compatible with codecs and many other serial
devices, and require a minimum of external hardware. An example of a codec
interface is provided in Section 6.2. For additional information on combocodecs, refer to the TCM29C13/C14/C16/C17 Combined Single-Chip PCM
Codec and Filter Data Sheet.
Two receive and two transmit registers are mapped into I/O port 1, and operate with 8-bit data samples. Either internal or external framing signals for serial
data transfers (MSB first) are selected via the system control register. The
serial port clock, SCLK, provides the bit timing for transfers with theserial port,
and may be either an input or output. A framing pulse signal provides framing
pulses for combo-codec circuits, a sample clock for voice-band systems, or a
timer for control applications. The serial port is accessed through IN and OUT
instructions. A block diagram of the serial port and companding hardware is
shown in Figure 3-22.

3.9.1 Receive Registers
Two receive registers are mapped into I/O port 1 via the port decode logic.
Data is clocked into the shift registers on the next eight negative serial clock
(SCLK) transitions after an active framing pulse is detected. SCLK controls
the bit-level timing for all serial-port data transfers. Note that the MSB is always shifted first.
On an active framing pulse, serial data is clocked into the receive registers from
the DR pins. 'Channel 0 data is received in shift register RSO from pin ORO,
and channel 1 data is received in shift register RS1 from pin DR1. To read the
data from the registers, an IN instruction is executed from port 1. On the first
IN instruction after a framing pulse, channel 0 data is output onto the external
data bus where it is read by the CPU. On the second IN instruction, channel
1 data is output onto the external data bus.
An active framing pulse initiates the receive operation, as shown in Figure
3-23. External framing pulses (FSR) are active low, and the internal framing
(FR) signal is active high. With external framing (FSR), the falling edge of the
framing pulse gates the serial-port clock to the receive shift registers, and the
data is clocked into the shift registers on the next eight consecutive negative
transitions of the clock.
3-36

Architecture - Serial Port

EXTERNAL
DATA BUS
(D15-DO)
PAO
PA1
PA2

WE
t5EfiI

14
I/O
CONTROL
jJ.-LAW/A-LAW
ENCODER

CR14

CRa
CR13

jJ.-LAW/A-LAW
DECODER

;:
0:: 10::
CD

RECEIVE
READ
SELECT

CR14

a
a a a

RECEIVE
REGISTER
RRO

DRO

DXO
CR11

RECEIVE
REGISTER
RR1

DR1

DX1

Figure 3-22. Serial Port and Companding Hardware

SCLK

~R~~____________~r~.______~~
DR1, DRO

DR1, ORO ':"'.--~----<

Data In

TRO, TR1

RSO, RS1

transferred

TSO, TS1·

transferred

RRO, RR1

Figure 3-24. Fixed-Data Rate for Internal Framing

3-38

Interrupt
flag set

Architecture - Serial Port

In the variable data-rate mode shown in Figure 3-25, the FR pulse is eight
SCLK cycles wide, .and appears in the same SCLK cycle as the first data bit.
The rising edge of the pulse initiates the transmit and receive operations. The
falling edge of the pulse transfers data from the receive shift registers to the
receive registers and sets the FR flag bit (CR3) in the system control register,
causing an interrupt to occur if enabled.
SCLK

OX1.0XO

~------------------~"~--------~

'---

---<'-_..JX

X,-_3~~~

OR1. ORO

Data in

TRO. TR1

RSO. RS1

transferred

to TSO. TS1

interrupt
flag set

transferred

to RRO. RR1

Figure 3-25. Variable-Data Rate for Internal Framing

3.9.2 Transmit Registers
Two transmit registers are mapped into I/O port 1 via the port decode logic.
The transmit registers are connected to the port 1 data bus in a FIFO (first in,
first out) configuration. On the first OUT instruction to port 1 after a framing
pulse, the data to be transmitted is put into transmit register TRO. On the next
framing pulse, the TRO contents are latched into transmit shift register TSO and
the data is transmitted on channel 0 (pin DXO) on the next eight positive
transitions of the serial-port clock (SCLK), as shown in Figure 3-26. External
framing pulses (FSX) are active low, and the internal framing (FR) signal is
active high. Data sent to port 1 is always put into the transmit registers. Only'
when control register bit 11 (CR11) is high will the data be enabled onto the
transmit pins. The transmit pins are in the high-impedance state when not
transmitting. External framing pulses are sensed during the high portion of the
SCLK cycle and latched internally with the falling edge of SCLK. Only one FSX
state can be detected per SCLK period.

3-39

Architecture - Serial Port

J8\-/\-

SCLK

FSX

~~------------~~~t------~~

DX1,DXO~

Data in
TRO, TR1
transferred
to TSO, TS1

FSX
interrupt
flag set

Figure 3-26. Transmit Timing for External Framing

Internal framing (FR) pulses can be selected in either fixed data-rate or variable data-rate modes for combo-codec interface. With the fixed data-rate
mode, the FR pulse is one SClK cycle wide, and appears in the cycle preceding the first data bit. The falling edge of the pulse initiates both the
transmit and receive operations, as shown in Figure 3-24. Data is transferred
from the transmit registers to the transmit shift registers. Transmitted data is
clocked into the transmit shift registers on the next eight -consecutive negative
transitions from the clock. After data bit 8 has been transmitted, an interrupt
is generated when the FR flag bit (CR3) is set in the system control register,
thus causing an interrupt to occur if enabled.
In the variable data-rate mode shown in Figure 3-25, the FR pulse is eight
SClK cycles wide, and appears in the same SClK cycle as the first data bit.
The rising edge of the pulse initiates the transmit and receive operations. The
falling edge of the pulse sets the FR flag bit (CR3) in the system control register, causing an interrupt to occur if enabled.
When two OUT instructions to port 1 are executed between framing pulses,
both transmit registers are loaded with data for transmission. The first OUT
instruction loads data into transmit register TRO. The second OUT pushes the
data from TRO into TR1 and puts the new data into TRO. On an active framinj;J
pulse edge, the transmit register contents are latched into the transmit shift
registers and the data clocked out on the next eight consecutive positive
transitions of SClK. Thus, for single-channel operation, only one OUT instruction to port 1 should be executed between framing pulses to insure data
transmission on channel O. Only TRO may be read back to the serial-port data
bus by an IN instruction. This feature is used for the parallel companding
mode.
Both transmit channels always output data on an active framing pulse when
CR11 is high. During single-channel operation (using channel 0), channel 1
still transmits the data from transmit register TR1. Transmit channel 1 cannot
be disabled during single-channel operation.
3-40

Architecture - Serial Port

3.9.3 Timing and Framing Control
The serial-port timing and framing control is shown in Figure 3-27. The serial-port clock (SCLK) provides the timing control for data transfers with the
serial port. SCLK may be configured as either an input or output through the
control register. As an input, SCLK is an external serial system clock that
provides the framing synchronization and timing for the serial port. As an
output, SCLK provides the system clock for standalone serial applications and
is derived from the microcomputer system clock (X2/CLKIN).

CR27-CR24

CR15

FSR FSX CR23-CR16

X2/CLKIN

TIMER
PRESCALE
.;.10/12/14/16/20/24/28/32

CR28

SERIAL-PORT
SCLK----*-.... TIMING CONTROL

tSXLD =
:t:RCLK =

SXLDt
RCLK:j:

Load transmit shift registers (TSO,TS1) from transmit registers (TRO,TR1)
Load receive registers (RRO,RR1) from receive shift registers (RSO,RS1)

Figure 3-27. Serial-Port Timing and Framing Control

3-41

Architecture - Serial Port

The serial-port clock prescaler determines the divide .ratio for SClK when
configured as an output. The TMS320C17 /E17 system clock (X2/ClKIN) is
input to the prescaler, along with control register bits CR27-CR24. Table 3-4
shows the prescale divide ratios selectable as divide by 10, 12, 14, 16, 20, 24,
28, and 32 through system control register bits CR27-CR24. These divide
ratios are available only for SClK when it is configured as an output from the
device (see Section 3.12 for control register bit configurations).
The frame multiplexer determines which framing pulses cause serial-port data
transfers to occur and configures the internal framing pulse (FR) frequency.
The inputs to the multiplexer are SClK, control register bit 9 (CR9), control
register bits CR23-CR16, external transmit framing (FSX) pulse, and external
receive framing (FSR) pulse. The outputs of the multiplexer go to the serialport control for receive and transmit timing generation for the serial-port registers and to the FR multiplexer for determining which FR framing pulse will
be generated.
The outputs of the frame counter are input to the FR multiplexer for selection
of long or short FR pulses. The short FR pulse provides fixed data-rate framing pulses for standalone serial interface to the Texas Instruments TCM29Cxx
family of combo-codec circuits. The long FR framing pulse provides variable
data-rate framing pulses to the combo-codec.
The FR frequency is determined at the beginning of the framing pulse cycle.
The FR frequency is equal to SClK/(CNT +2) where CNT is the binary value
of CR23-CR16. When reconfiguring the frequency, the upper control register
bits determine the new divide ratio. However, the new frequency is not implemented until the next FR framing pulse.

Table 3-4. Serial Cloc~ (SClK) Divide Ratios (X2/elKIN

= 20.48 MHz)

CR27

CR26

CR25

CR24

DIVIDE RATIO

SCLK FREQUENCY

UNIT

0
0

0
1

32
28

0.640

0.853

0
0

0
1

20
16

1.280

MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz

1
1
1

3-42

0
1

0.731
1.024

14
12

1.463

0
0

2.048

1.706

Architecture - Companding Hardware

3.10 Companding Hardware (TMS320017/E17)
The on-chip companding hardware enables the TMS320C17 /E17 to compand
(COMpress and exPAND) data in either JJ-Iaw or A-law format with either
sign-magnitude or two's-complement numbers. The standard employed in the
United States and Japan is JJ-Iaw companding. The Eur,opean standard is referred to as A-law companding. Configuration and connections of the encoder and decoder (see Figure 3-22)' are controlled through the system
control register.
When sign magnitude is selected, the JJ-Iaw encoding and decoding require a
bias adjustment in the sample value. For JJ-Iaw encoding, a bias of 33 must
be added to the sign magnitude before encoding; likewise, after JJ-Iaw decoding, the bias of 33 must be subtracted from the sign-magnitude value. No
additional bias adjustment is required for JJ-Iaw encoding and decoding when
the selected conversion uses two's-complement notation. Note that A-law
encoding and decoding do not require a bias adjustment in either case.
Upon reset, the TMS320C17/E17 is programmed to operate in sign-magnitude mode. This mode can be changed by modifying control register bit 29
(CR29). Refer to the TCM29C13/TCM29C14/TCM29C16/TCM29C17 Combined Single-Chip PCM Codec and Filter Data Sheet for further information
on companding. If software companding is desired without the use of companding hardware, descriptive algorithms are given in the book, Digital Signal
Processing Applications with the TMS320 Family (literature number
SPRA012A); refer to the application report, "Companding Routines for the
TMS32010/TMS32020."
The specification for JJ-Iaw and A-law log PCM is part of the CCITI G.711
recommendation. Part of the coding format specifies certain bits to be inverted
prior to transmission or upon receipt of transmitted data. The companding
hardware in the TMS320C17 IE17 implements the bit inversion as well as the
logarithmic compression and decompression.
Data may be companded via four modes: serial-port encode, serial-port decode, parallel encode, and parallel decode. In the serial mode, transmitted data
is encoded according to the specified companding law, and received data is
decoded to either sign-magnitude or two's-complement format. In the parallel
modes, encoding or decoding is performed on data from the RAM for computations within the device. Note that in parallel mode when two'scomplement notation is selected, at least ,one instruction must be inserted
between successive OUT and IN instructions to I/O port 1.
Table 3-5 shows the control register bit combinations that determine the serial
or parallel modes of the companding hardware operation. Note that the serial
and parallel companding modes require separate control register settings.
When using the serial mode, parallel companding is not available unless the
control register is reconfigured.

3-43

Architecture - Companding Hardware

Table 3-5. Serial- and Parallel-Mode Bit Configurations
,

CR BIT #
13 12 11

MODE OF OPERATION

Parallel mode. Encoder and decoder are disabled.
performed on data written to or read from port 1.

Serial mode. Encoder and decoder are disabled. The transmit registers are enabled for data transmission on an active framing pulse. The
8-bit value written to port.1 is transmitted and the 8-bit value in the
receive register is read with an IN instruction from port 1.

P<;Iraliel encode. Encoder is enabled. A linear sample written to port
1 'with an OUT instruction is compressed to 8-bit log PCM. The 8-bit
value is then read from port 1 with an I N instruction.

Serial encode. Encoder is enabled. A linear sample written to port 1
is compressed to 8-bit log PCM and put into the transmit register for
transmission on an active framing pulse.

Parallel decode. Decoder is enabled. An 8-bit log PCM data written
to port 1 is decoded to linear notation with an IN instruction from
port 1.

Serial decode. Decoder is enabled. An 8-bit log PCM sample from
one of the receive registers is expanded to linear notation with an IN
instruction from port 1.

Parallel encode and decode. Encoder and decoder enabled. In this
state, data is compressed on an OUT instruction to port 1 and then
expanded with the IN instruction from the port.

Serial encode and decode. Encoder and decoder enabled. Linear
data written to port 1 is encoded and put into one of the transmit
registers for serial transmission. The 8-bit log PCM data from one of
the receive registers is decoded with an IN instruction from port 1.

No operation

3.10.1 J.I-Law/A-Law Encoder
The encoder compresses linear PCM (14 bits of dynamic range for J.I-Iaw format or 13 bits of dynamic range for A-law format) to 8-bit logarithmic PCM.
Selection between J.I-Iaw or A-law conversion is determined by the system
control register bit 14 (CR14). This bit is input directly to the encoder to de~
termine the conversion· law to be used. The J.I-255 law conversion is performed if CR14 is logic 0, and A-law conversion if CR14 is logic 1. Data is
input to the encoder from the data bus with an OUT instruction to port 1. The
converted 8-bit log PCM sample is then presented to the multiplexer (MUX2
. shown in Figure 3-22). The multiplexer controls whether the encoder output
or the eight low-order data bus bits are input to transmit register TRO of the
serial port. Note that the transmit registers are connected to the port 1 data
bus in a FIFO (first in, first out) configuration. The encoder compresses data
written to port 1 at all times, but the output will be enabled to the TRO only
when CR12 is logic 1.
3-44

Architecture - Companding Hardware

In the serial-encode mode, data written to port 1 is encoded, and the value
put into transmit register TRO. The transmit register is then loaded with the
8-bit value on an active framing pulse, and the 8 bits are clocked out on the
positive edge of SCLK.
For the parallel-encode mode, the linear-PCM value is written to port 1 with
an OUT instruction. The encoded 8-bit value is then stored in TRO. An IN
instruction from port 1 reads TRO to the data bus for storage in RAM. Care
should be taken to have only one OUT and one IN instruction to port 1 for
each data sample in the parallel-encode mode. If there are two OUT instructions to port 1, the first sample will be pushed into transmit register TR1 ,
which cannot be read back to the data bus. Note that when two'scomplement notation is selected, there must be at least one instruction executed after the OUT instruction to ,port 1 and before the IN instruction from
port 1.

3.10.2 IJ-Law/A-Law Decoder
The IJ-Iaw/A-Iaw decoder converts 8-bit log-PCM samples to linear PCM.
The conversion-law selection is governed by control register bit 14 (CR14).
The IJ-Iaw conversion is performed if CR14 is logic 0, and A-law conversion
if CR14 is logic 1. Data input to the decoder may come from either the serial-port receive registers or transmit register TRO. The multiplexer (MUX1
shown in Figure 3-22) sends data to the data bus either through the decoder
or directly to the bus. This multiplexer is controlled in part by control register
bit 13 (CR13). If this bit is logic 0, the multiplexer output is sent to the data
bus directly. If the bit is logic 1, the multiplexer output is sent to the data bus
through the decoder.
In the serial-decode mode, received data from the serial-port receive registers
is input to the decoder from the mUltiplexer, and the received data is decoded
according to either IJ-Iaw or A-law format.
For the parallel-decode mode, the 8-bit PCM sample to be decoded is written
to port 1 with an OUT instruction. This stores the sample in transmit register
TRO. The sample is then decoded by reading the value from port 1 with an IN
instruction. The IN instruction brings the sample from TRO through the mUltiplexer (MUX1) to the decoder, which performs the expansion on the 8-bit
sample. Again, there should be only one OUT and one IN instruction to port
1 for each sample to be decoded in order to avoid losing a sample in transn;lit
register TR1. Note that when two's-complement notation is selected, there
must be at least one instruction executed after the OUT instruction to port 1
and before the IN instruction from port 1.

3-45

Architecture - Coprocessor Port

3.11" Coprocessor Port (TMS320C17/E17)

The coprocessor port on the TMS320C17/E17 provides a direct interface to
most 4/8-bit microcomputers and 16/32-bit microprocessors. The port is
accessed through I/O port 5 using IN and OUT instructions. The coprocessor
interface allows the device to act as a peripheral (slave) microcomputer to a
microprocessor, or as a master to a peripheral microcomputer such as the
TMS7042. The coprocessor port is enabled by setting MC/PM and MC low.
The microcomputer mode is enabled by setting these two pins high. (Note
that the MC/PM and MC pins must belin the same state.) In the microcomputer mode, the 16 data lines are used for the 6 parallel 16-bit I/O ports.
Interprocessor communication through the coprocessor interface (see Figure
3-28) is accomplished asvnchronously as in memory-mapped I/O operations.
In coprocessor mode, the 16-bit data bus is reconfigured to operate as a
16-bit latched bus interface. Control bit 30 (CR30) in control register 1 is
used to configure the coprocessor port to either an 8-bit or a 16-bit length for
data transfers. Use of the H I/lO pin allQws the full 16-bit data latches to be
used even when the 8-bit mode is selected.

WR -+....--+--tt--A

RI-+-+-.....-<\--.....
RD -+-+--e--cL.~

PRE

~-+-+--+-----+--~Q
fij[f

-+-+--+-----1

D
4 - 4 t - ' - - 4 I " - - - I N FROM PAS

4-4t--4..---+--'-+--OUT TO PAS

LD1S·
LDO

-+---....----+-+----1-,.<;
,--_.'6+-1 Q

'.;.;;6+-_-----......--D1S.DO

D ...

Figure 3-28. TMS320C17/E17 Simplified Coprocessor Port Logic
Diagram

3-46

Architecture - Coprocessor Port

Several key characteristics of the coprocessor interface are worth noting and
listed below.
•

The BIO and EXINT signals are internal to the processor. No inputs should
be made on the BIO and EXINT pins.

•

Only transfers made when HI/LO is in a low state can activate the internal BIO and EXINT signals.

•

The interrupt condition is kept internally until it is cleared by the
TMS320C17/E17 reading the data in the coprocessor port latch. The
interrupt flag cannot be cleared until the port is read. Four instruction
cycles must take place between the read (IN instruction) from the coprocessor port (PA5) and the write to control register CRO to clear the
interrupt flag.

•

When the TMS320C17 /E17 reads the coprocessor port, it clears the data
in the latch.

•

The 16 data lines (LD15-LDO) remain in a high-impedance state unless
a logic low is asserted on RD. When RD is asserted, the TMS320C17 /E17
drives the data bus with the data in the coprocessor port latch.

The following sequences of events occur depending upon the configuration
and use of the coprocessor porto:
•

16-bit data interface (CR30

= 1):

All 16 bits of the data port are available for 16-bit transfers to
16/32-bit microprocessors.
The HI/LO pin is maintained at a logic low level for all transfers.
Transfers to the TMS320C17 /E17 (see Figure 3-29):
1)
The WR signal is driven low by the microprocessor.
2)

The RBLE (receive buffer latch empty) signal transitions to a
logic high level in response to WR.

Data is written from LD15-LDO to the receive buffer latch
when the WR signal is driven high by the microprocessor.

The internal EXINT signal is generated, causing the interrupt
flag to be set in the TMS320C17 /E17.

The TMS320C17/E17 responds to the interrupt condition
and reads port 5 using an IN instruction.
The receive buffer is cleared. (Subsequent reads by the
TMS320C17 /E17 will be zero value.)

The RBLE signal transitions to a logic low level, signaling the
microprocessor that the receive buffer is empty.

The internal EXINT signal is removed, allowing the interrupt
flag to be cleared.

The interrupt flag is cleared by writing .to control register O.

3-47

Architecture - Coprocessor Port

Transfers from the TMS320C17 /E17 (see Figure 3-30):

•

The RD signal is driven low by the microprocessor.

The TBLF (transmit buffer latch full) signal transitions to a
logic high level in response to RD.

Data is driven from the transmit buffer latch to LD15-LDO
until the RD signal is driven high by the microprocessor.

The internal BIO signal transitions to a logic low level, indicating to the TMS320C17/E17 that the transmit buffer is
empty.

The TMS320C17/E17 responds to the BIO condition and
writes to port 5 using an OUT instruction.

The TBLF signal transitions to a logic low level, signaling the
microprocessor that the transmit buffer is full.

The internal BiO signal transitions back to a logic high state.

8-bit data interface (CR30 = 0):
Only the least-significant eight bits of the ,data port are available
for 8-bit transfers to 4/8-bit microcomputers.
Eight-bit microcomputers may complete full 16-bit transfers by
first transferring data with the HI/LO signal in a logic high state
(steps 1 through 4 below), and then with HI/LO in a logic low
state. Composing 16-bit data in this manner requires two external
bus cycles but only one internal port access. The HI/LO pin may
be maintained at a logic low level if only 8-bit transfers are desired.
Transfers to the TMS320C17 /E17 (see Figure 3-29):
1)
The HI/LO signal is driven high by the microcomputer to allow transfers to the upper eight bits of the internal latch.

3-48

2}
3)

The WR signal is driven low by the

The HllLO signal is driven low by the microcomputer to allow
transfers to the lower eight bits of the internal latch.

The WR signal is driven low by the microcomputer.

The RBLE (receive buffer latch empty) signal transitions to a
logic high level.

Data is written from lD7-lDO to the receive buffer latch
(D7-DO) when the WR signal is driven high by the microcomputer.

The internal EXINT signal is generated, causing the interrupt
flag to be set in the TMS320C17 /E17.

The TMS320C17/E17 responds to the interrupt condition
. and reads port 5 using an IN instruction.

microcompu~er.

Data is written from LD7-lDO to the receive buffer latch
(D15-D8) when the WR signal is driven high by the microcomputer.

Architecture - Coprocessor Port

10}

The receive buffer is cleared. (Subsequent reads· by the
TMS320C17 /E17 will be zero value.)

11}

The RBLE signal transitions to a logic low level, signaling the
microcomputer that the receive buffer is empty.

12)

The internal EXINT signal is removed, allowing the interrupt
flag to be cleared.

13)

The interrupt flag is cleared by writing to control register O.

Transfers from the TMS320C17 /E17 (see Figure 3-30):
1)

The HI/LO signal is driven high by the microcomputer to allow transfers from the upper eight bits of the internal latch.

The RD signal is driven low by the microcomputer.

Data is driven from the transmit buffer latch (D15-D8) to
LD7-LDO until the RD signal is driven high by the microcomputer.

The HI/LO signal is driven low by the microcomputer to allow
transfers from the lower eight bits of the internal latch.

The RD signal is driven low by the microcomputer.

The TBLF (transmit buffer latch full) signal transitions to a
logic high level.

Data is driven from the transmit buffer latch (D7 -DO) to
LD7-LDO until the RD signal is driven high by the microcomputer.

The internal BIO signal transitions to a logic low level, indicating to the TMS320C17/E17 that the transmit buffer is
empty.

The TMS320C17/E17 responds to the BIO condition and
writes to port 5 using an OUT instruction.

10)

The 'i'BtF signal transitions to a logic low level, signaling the
microcomputer that the transmit buffer is full.

11)

The internal BIO signal transitions back to a logic high state.

Examples of the use of a coprocessor interface are provided in Section 6.5 and
the data sheet of Appendix A.

3-49

Architecture - Coprocessor Port

Hi/LOW

DATA-{

~\-(I

VALID
~--------~~~--~--

VALID

RBLE

u
II

EXINTt

I
\ '-----tll-l----II
\~

DENtL
(PA5)
Only necessary for
operation of a-bit mode
constructing 1 6-bit data
t Internal signals

Figure 3-29. External Write Timing to the Coprocessor Port

HlfrnW'

DATA

TBLF

----«

VALID

~I~S-----«

/
------------~\Ir\------J

BlOt

WEtL

(PA5)

VALID

)>---iSrS- - - - -

'-\'------ill~
/\~

. Only necessary for
operation of a-bit mode
constructing 1 6-bit data

t Internal signals

Figure 3-30. External Read Timing from the Coprocessor Port

3-50

Architecture - System Control Register

3.12 System Control Register (TMS320C17/E17)
The TMS320C17/E17 provides additional hardware for interfacing ease in
serial applications. This hardware is interfaced to the microcomputer portion
of the device via the external data bus (015-00). The additional hardware is
controlled by a 32-bit system control register (see Figure 3-31), thereby
eliminating any additions to the TMS320 instruction set.
CR(10)

DATA BUS (015-00)
18

CR(15 -0) __-~<.::18=-t LOWER CONTROL
REGISTER

RESET

INTERRUPT
FLAG BITS

CR(31-18) __- - - - ; UPPER CONTROL
REGISTER

Figure 3-31. System Control Register

The lower 16 register bits (CR15-CRO) are accessed through port O. These
bits control interrupts, serial-port configuration, the external logic output flag,
internal and external framing pulses, and the J.I-Iaw/A-Iaw encoder and decoder. The interrupt inputs (EXtNT, FSX, FSR, and FR) are synchronized to
CLKOUT and control the interrupt flag bits (CR3-CRO). The interrupts are
maskable via the interrupt enable bits (CR7-CR4). Bit S (CRS) controls I/O
port 1 configuration.
The upper 16 bits (CR31-CR16) are accessed through port 1. These bits
control the internal framing pulse (FR) output frequency, serial-clock divide
ratios, pulse-width control for the FR framing pulse, and companding conversions. The bit width of the coprocessor mode is controlled by CR30.
The external data bus provides on-chip communication with the system control register, serial port, companding hardware, and coprocessor port. With a
write to port 0, the lower control register is addressed and data latched into
the register by the rising edge of the write enable (WE) signal. To write to the
upper control register bits, bit 8 of the lower control register must be set to
logic 1. If CRS is logic 0, a write to port 1 accesses the serial port and compan~ing hardware.
Table 3-6 gives a detailed description of the control register bits and their
operation. The control register bits are configured through OUT instructions
to port 0 and port 1. WE goes low during the first cycle of the OUT instruction,
enabling the port data onto the external data bus. The control register bits are
latched on the rising edge of WE. There is a propagation delay time for these
bits to access the appropriate hardware (see Appendix A for timing informa'tion). An allowance for this write delay should be made when reconfiguring
(writing to) the control register. The most critical factor is receiving an ex3-51

Architecture - System Control Register

ternal framing pulse while reconfiguring the control register. If an external
framing pulse is received at that time, it may not be detected and the serialport registers will contain random data (see Section 3.9 for further details).

Table 3-6. Control Register Bit Definitions
CR BIT
3-0

DESCRIPTION
Interrupt flags. When an interrupt occurs on any of the four maskable interrupts, the
appropriate flag is set to logic 1 whether the interrupt is enabled or disabled. To clear
the flag, a logic 1 is written to the appropriate bit by an OUT instruction to port O.
The bits may be read by an IN instruction to determine interrupt sources when multiple
interrupts are enabled.
Bit

EXINT
FSR
FSX
FR

0
1

2
3

7-4

Interrupt enable bits. When one of these bits is set to logic 1, an interrupt occurring
on that input sets the appropriate flag and activates the microcomputer interrupt circuitry. When disabled, the interrupt flag is still set, but the device is not interrupted.
Bit

4
5
6

3-52

Flag

Flag
EXINT
FSR
FSX
FR

Port 1 control bit. When set to logic 0, I/O port 1 isconnected to either the serial-port
registers or the companding hardware, depending on the state of CR11. When set to
logic 1, I/O port 1 is connected to the upper control register. This bit must be set with
an OUT instr\.lction to port 0 before port 1 may access the upper control register bits
CR31-CR16.

External framing enable. This bit controls which framing pulses cause serial port data
transmission to occur. When set to logic 0, serial port transmit and receive operations
occur simultaneously and are controlled by the internal framing (FR) pulse. When set
to logic 1, transmit operations are controlled by the external transmit framing (FSX)
pulse, and receive operations are controlled by the external receive framing (FSR)
pulse.

XF output latch. This bit controls the logic level of the external logic output flag (XF)
pin. A write delay time occurs when reconfiguring this latch (see Appendix A for
timing information).

Serial port enable. When set to logic 0, the transmit and receive registers are disabled
in order to use the parallel companding mode. When set to logic 1, the serial port
registers are enabled and data transfers with ,the serial port are via OUT and IN instructions to port 1. A reset sets this bit to zero.

Architecture - System Control Register

Table 3-6. Control Register Bit Definitions (Concluded)
CR BIT#

DESCRIPTION

IJ-Iaw/A-Iaw encoder enable. When set to logic 0, the encoder is disabled. When set
to logic 1, the encoder is enabled, and data written to port 1 is IJ-Iaw or A-law encoded. The encoder must be enabled for compression of linear data in both the serial
and parallel modes of operation.

IJ-Iaw/A-Iaw decoder enable. When set to logic 0, the decoder is disabled. When set
to logic 1, the decoder is enabled, and data read from port 1 is IJ-Iaw or A-law decoded to linear format. The decoder must be enabled for expansion of log PCM data
in both the serial and parallel modes of operation.

IJ-Iaw or A-law encode/decode select. When set to logic 0, the companding hardware
performs 1J-255-law conversion. When set to logic 1, the companding hardware performs A-law conversion.

Serial clock control. When set to logic 0, the serial port clock (SCLK) is an output,
and its frequency is derived from the microcomputer system clock, X2/CLKIN. When
set to logic 1, SCLK is an input that provides the clock for all data transfers with the
serial port and the frame counter in timing logic. A reset sets this bit to one.

23-16

Frame counter modulus. The value of these bits determines the divide ratio for the
FR output frequency. The FR frequency is given as SCLK/(CNT + 2) where CNT is a
binary value of CR23-CR16. The following should be noted when configuring the
divide ratio:
1. CNT must be in the range given by 7 :S CNT :S 254.
2. Bits are operational whether SCLK is an input or an output.

27-24

SCLK prescale control bits. As an output, SCLK is derived from the microcomputer
system clock, X2/CLKIN. Prescale divide ratios are selectable through these control
bits (see Section 3.9.3 for the available divide ratios).

FR pulse-width control. This bit controls the pulse width of the FR output to select
data-transfer rates with combo-codec circuits. When set to logic 0, the FR output
framing pulse is one SCLK cycle wide for the fixed data-rate mode and appears in the
serial-clock cycle preceding the first serial-bit transmission. When set to logic 1, the
FR output framing pulse is eight SCLK cycles wide for the variable data-rate mode.
In this mode. the framing pulse is active high for the duration of the eight bits transmitted and received.

Two's-complement IJ-Iaw/A-Iaw conversion enable. When set to logic 0, sign-magnitude companding is enabled. When set to logic 1, two's-complement companding
is enabled. When two's-complement companding has been selected along with the
parallel companding mode of operation, one instruction must be inserted between
successive OUT and I N instructions to port 1. A reset sets this bit to zero.

8/16-bit length coprocessor mode select. When set to logic 0, the 8-bit byte length
is used. When set to logic 1, the 16-bit word length is selected.

Reserved for future expansion. This bit should be set to zero.

3-53

Architecture - System Control Register .

3-54

Section 4

Assembly Language Instructions

The instruction set of the TMS320C1 x (first-generation TMS320) processors
supports numeric-intensive signal processing operations and general-purpose
applications, such as high-speed control. The instruction set shown in Table
4-2 consists primarily of single-cycle, single-word instructions, permitting
execution rates of up to 6.25 million instructions per second. Only infrequently
used branch and 1/0 instructions are multi-cycle.
For operations involving multiplication, the TMS320C1 x instruction set offers
a single-cycle instruction (MPY). For ease of use in a Harvard architecture,
table read (TBLR) and table write (TBLW) instructions are provided, which
allow information transfer between data and program memory. The IN and
OUT instructions permit a data word to be read into the on-chip RAM in only
two cycles. The SUBC (conditional subtract) instruction performs the shifting
and conditional branching necessary to implement a divide efficiently and
quickly.
This section describes the TMS320C1 x assembly language instructions. Included in this section are the following major topics:
•

Memory Addressing Modes (Section 4.1 on page 4-2)
Direct addressing
Indirect addressing (using two auxiliary registers)
Immediate addressing

•

Instruction Set (Section 4.2 on page 4-7)
Symbols and abbreviations used in the instructions
Instruction set summary (listed according to function)

•

Individual Instruction Descriptions (Section 4.3 on page 4-11 )
Presented in alphabetical order and provirfing the following:
- Assembler syntax
- Operands
- Execution
- Encoding
. - Description
- Words,
- Cycles
- Example(s}

4-1

Assembly Language Instructions - Memory Addressing Modes

4.1 Memory Addressing Modes
The TMS320C1 x instruction set provides three memory addressing modes:
•
•
•

Direct 'addressing mode
Indirect addressing mode
Immediate addressing mode.

Both direct and indirect addressing can be used to access data memory. Direct
addressing concatenates seven bits of the instruction word with the 1 -bit data
memory page pointer to form the 8-bit data memory address. Indirect addressing accesses data memory through the two auxiliary registers. In immediate addressing, the data is based on a portion of the instruction word(s).
The foilowing sections describe each addressing mode and give the opcode
formats and some examples for each mod~.

4.1.1 Direct Addressing Mode

In the direct memory addressing mode, the instruction word contains the
lower seven bits of the data memory address (dma). This field is concatenated
with the one-bit data memory page pointer (DP) register to form the full 8-bit
data memory address. This implements a paging scheme in which the first
page contains 128 words and the second page contains 16/128 words. In a
typical application, infrequently accessed system variables, such as those used
when performing an interrupt routine, are stored on the second page. The
7 -bit address in the instruction points to the specific location within that data
memory page. The DP register is loaded through the LOP (load data memory
page pointer~, LDPK (load data memory page pointer immediate). or LST
(load statuI! bits from data memory) instructions. The data page pointer is part
of the status register and thus can be stored in data memory.

Note:
The data page pointer is not initialized by reset and is therefore undefined
after powerup. The TMS320C1 x development tools, however, utilize de-'
fault values for many parameters, including the data page pointer. Because
of this, programs that do not explicitly initialize the data page pointer may
execute improperly depending on whether they are executed on a
TMS320C1 x device or using a development tool. Thus, it is critical that
all programs initialize the data page pointer in software.

Figure 4-1 illustrates how the 8-bit data address is formed.

4-2

Assembly Language Instructions - Memory Addressing Modes

7 LSBS FROM
INSTRUCTION
REGISTER (JR)

8-BIT DATA ADDRESS

Figure 4-1. Direct Addressing Block Diagram

Direct addressing can be used with all instructions except CALL, the branch
instructions, immediate operand instructions, and instructions with no operands. The direct addressing format is as follows:
15 14

Opcode'

dma

Bits 15 through 8 contain the opcode. Bit 7 = 0 defines the addressing mode
as direct. Bits 6 through 0 contain the data memory address (dma),which can
directly address up to 128 words (1 page) of data memory. Use of the data
memory page pointer is required to address the full data memory space.
Example of Direct Addressing Format:

ADD 9,5

15 14

Add to accumulator the contents of data memory location
9 left-shifted 5 bits.
13

00000

0000

The opcode of the ADD 9,5 instruction is 05h and appears in bits 15 through
8. The notation nnh indicates nn is a hexadecimal number. The shift count
of 5h appears in bits 11 through 8 of the opcode. The data memory address
09h appears in bits 6 through O.

4-3

Assembly Language Instructions- Memory Addressing Modes

4.1.2 Indirect Addressing Mode
Indirect addressing forms the data memory address from the least significant
eight bits of one of the two auxiliary registers, ARO and AR1 . This is sufficient
to address all the data memory; no paging is necessary with indirect addressing. The Auxiliary Register Pointer (ARP) selects the current auxiliary register.
The auxiliary registers can be automatically incremented, or decremented in
parallel with the execution of any indirect instruction to permit single-cycle
manipulation of data tables. The increment/decrement occurs AFTER the current instruction has completed executing.
In indirect addressing, the 8-bit addresses contained in the auxiliary registers
may be loaded ,by the instructions LAR (load auxiliary register) and LARK
(load auxiliary register immediate). The auxiliary registers may be modified
by the MAR (modify auxiliary register) instruction or, equivalently, by the indirect addressing field of any instruction supporting indirect addressing.
AR(ARP} denotes the auxiliary register selected by ARP.
The following symbols are used in indirect addressing:

..
..

Contents of AR(ARP} are used for data memory address.
Contents of AR(ARP} are used for adc:tress, then decremented after data
memory access.

Contents of AR(ARP} are used for address, then incremented after data
memory access.

The indirect addressing format is as follows:
15

I
NOTE: NAR

8765432

Opcode
I 1 I 0 IINC I DEC I NAR I 0
new auxiliary register control bit.

Bits 15 through 8 contain the opcode, and bit 7 = 1 defines the addressing
mode as indirect. Bits 6 through 0 contain the indirect addressing control bits.
Bit 3 and bit 0 control the Auxiliary Register Pointer (ARP). If bit 3 = 0, the
contents of bit 0 are loaded into the ARP after execution of the current in~truction. If bit 3 = 1, the contents of the ARP remain unchanged. ARP = 0
defines the contents of ARO as a memory address. ARP = 1 defines the contents of AR1 as a memory address. Note that NAR denotes the new auxiliary
register control bit.
Bit 5 and bit 4 control the auxiliary registers. If bit 5 = 1, the current auxiliary
register is incremented by 1 after execution. If bit 4 = 1. the current auxiliary
register is decremented by 1 .after execution. If bit 5 and bit 4 are 0, then
neither auxiliary register is incremented nor decremented. Bits 6, 2, and 1 are
reserved and should always be programmed to O.
The auxiliary registers may also be used for temporary storage via the load and
store auxiliary register instructions. LAR and SAR, respectively.
The examples that follow illustrate the Indirect addressing format. Indirect
addressing is indicated by an asterisk (*) in these examples and in the
TMS320C1 x assembler.
4-4

Assembly Language Instructions - Memory Addressing Modes

Example 1:

ADD *+,8

Add to the accumulator the contents of the data memory
address defined by the contents of the current auxiliary
register. This data is left-shifted 8 bits before being added.
The current auxiliary register is auto incremented by one.
The opcode is OSASh, as shown below.
12

0000100010

o
o

Example 2:

ADD *,8

As in Example 1, but with no autoincrement; the opcode
is 088Sh.

Example 3:

ADD *-,8

As in Example 1, except that the current auxiliary register
is decremented by 1; the opcode is 089Sh.

Example 4:

ADD *+,8,1

As in Example 1, except that the auxiliary register pointer
is loaded with the value 1 after execution; the opcode is
OSA1h.

Example 5:

ADD "+,8,(\

As in Example 4, except that the auxiliary register pointer
is loaded with the value 0 after execution; the opcode is
08AOh.

4-5

Assembly Language Instructions - Memory. Addressing Modes

4.1.3 Immediate Addressing Mode
Included in the TMS320Clx instruction set are five immediate operand instructions, in which the immediate operand is contained within the instruction
word. These instructions execute within a single instruction cycle. The length
of the constant operand is instruction-dependent. The immediate instructions
are:
Load accumulator immediate short (S-bit constant)
Load auxiliary register immediate short (S-bit constant)
Load auxiliary register pointer (1 -bit constant)
Load data memory page pointer immediate (1-bit constan1)
Multiply immediate (13-bit constant)

LACK

LARK
LARP

LDPK

MPYK

The following examples illustrate immediate addressing format:
Example 1:
MPYK 2781
15 14

Multiply the value 27S1 with the contents of the T register.
The result is loaded into the P register.

13-bit constant

Example 2:
LACK 221

15 14

oI1

4-6

Load the constant 221 in the lower eight bits of the accumulator right-justified. The upper 24 bits of the accumulator
are zero.
12

I1 I1 I1 I1

8- bit constant

Assembly Language Instructions - Instruction Set

4.2 Instruction Set
The following sections list the symbols and abbreviations used in the
TMS320C1 x instruction set summary and in the instruction descriptions. The
complete instruction set summary is organized according to function. A detailed description of each instruction is listed in the instruction set summary.

4.2.1 Symbols and Abbreviations
Table 4-1 lists symbols and abbreviations used in the instruction set summary
(Table 4-2) and the individual instruction descriptions.
Table 4-1. Instruction Symbols
SYMBOL

MEANING

A
ACC
ARn

Port address
Accumulator
Auxiliary Register n (ARO and AR1) are predefined assembler symbols
equal to 0 and 1, respectively.)
Auxiliary register pointer
Branch address
Data memory address field
Label assigned to data memory location n
Data memory address
Data page pointer
Addressing mode bit
Interrupt mode bit
Immediate operand field
Indicates nn is a hexadecimal number. (All others are assumed to be
decimal values.)
Overflow (saturation) mode flag bit
Product register
Port address (PAO through PA7 are predefined assembler symbols equal
to 0 through 7, respectively.)
Program counter
Program memory address
Label assigned to program memory location n
1-bit operand field specifying auxiliary register
4-bit left-shift code
Temporary register
Top of stack
3-bit accumulator left-shift field
Is assigned to
An absolute value
User-defined items
Optional items
"Contents of"
Alternative items, one of which must be entered
Angle brackets back-to-back indicate "not equal".
Blanks or spac.!ls must be entered where shown.

ARP
B

o
DATn
dma
DP
I
INTM
K
nnh
OVM

P
PA
PC
pma
PRGn
R

S
T
TOS

....

I I

<>
[ ]
()
{}
<>

4-7

Assembly Language Instructions -- .Instruction Set

4.2.2 Instruction Set Summary _
Table 4-2 provides the TMS320C1 x instruction set summary, arranged according to function and alphabetized1within each functional grouping. Additional information is presented in the .individual instruction descriptions in the
following section.
The instruction set summary consists primarily of single-cycle, single-word
instructions. Only infrequently used branch and I/O instructions are multicycle.

4-8

Assembly Language Instructions - Instruction Set

Table 4-2. Instruction Set Summary
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS
Mnemonic and Description
Cycles Words
16-Bit Opcode
MSB
LSB
Absolute value of accumulator
1
1
0111 1111 1000 1000
ABS
ADD
Add to accumulator with shift
1
1
0000 ·SSSS I DOD DODD
ADDH
Add to high accumulator
1
1
0110 0000 I DOD DODD
ADDS
Add to low accumulator with
1
1
0110 0001 I DOD DODD
sign-extension suppressed
AND
AND with accumulator
1
0111 1001 I DOD DODD
1
LAC
Load accumulator with shift
1
0010 SSSS I DOD DODD
1
LACK
Load accumulator immediate short
1
0111 1110 KKKK KKKK
1
OR
OR with accumulator
1
0111 1010 I DOD DODD
1
SACH
Store high accumulator with shift
1
1
0101 1XXX I DOD DODD
SACL
Store low accumulator
1
1
0101 0000 I DOD DODD
SUB
Subtract from accumulator with shift
1
1
0001 SSSS I DOD DODD
SUBC
Conditional subtract
1
1
0110 0100 I DOD DODD
SUBH
Subtract from high accumulator
1
1
0110 0010 I DOD DODD
SUBS
Subtract from low accumulator
1
1
0110 0011 I DOD DODD
with sign-extension suppressed
XOR,
Exclusive-OR with low accumulator
1
1
0111 1000 I DOD DODD
ZAC
0111 1111 1000 1001
1
Zero accum,ulator
1
ZALH
Zero low accumulator and load high
1
0110 0101 I DOD DODD
1
accumulator
ZALS
Zero accumulator and load low
1
1
0110 0110 I DOD DODD
accumulator with sign-extension
suppressed
AUXILIARY REGISTER AND DATA PAGE POINTER INSTRUCTIONS
Mnemonic and Description
Cycles Words
16-Bit Opcode
MSB
LAR
LARK
LARP
LOP
LDPK
MAR
SAR

Load auxiliary register
Load auxiliary register immediate short
Load auxiliary register pointer
immediate
Load data memory page pointer
Load data memory page pointer
immediate
Modify auxiliary register
Store auxiliary register

LSB

1
1
1

0011 100R I DOD DODD
0111 OOOR KKKK KKKK
0110 1000 1000 OOOK

1
1

0110 1111 I DOD DODD
0110 1110 0000 OOOK

1
1

0110 1000 I DOD DODD
0011 OOOR I DOD DODD

T REGISTER. P REGISTER. AND MULTIPLY INSTRUCTIONS
Mnemonic and Description
Cycles Words
16-Bit Opcode
MSB
APAC
LT
LTA
LTD
MPY

,
MPYK
PAC
SPAC

Add P register to accumulator
Load T register
Load T register and accumulate
previous product
Load T register. accumulate previous
product. and move data
Multiply (with T register. store product
in P register)
lII!ultiply immediate
Load accumulator with P register
Subtract P register from acoumulator

1
1
1

LSB
0111 1111 1000 1111
0110 1010 I DOD DODD
0110 1100 I DOD DODD

0110 1011

I DOD DODD

0110 1101

I DOD DODD

1
1
1

100K KKKK KKKK KKKK
0111 1111 1000 1110
0111 1111 1001 0000

1
1
1

4-9

Assembly Language Instructions.., Instruction Set

Table 4-2. Instruction Set Summary (Concluded)
,/

BRANCH/CALL INSTRUCTIONS
Cycles Words
Mnemonic and Description

16-Bit Opcode
MSB

Branch unconditionally

BANZ

Branch on auxiliary register not zero

BGEZ

,,'

Branch if accumulator

;

BGZ

Branch if accumulator> 0

BIOZ

Branch on I/O status = 0

BLEZ

Branch if accumulator

s: 0

BLZ

Branch if accumulator < 0

BNZ

Branch if accumulator ¢ 0

Branch on overflow

Branch if accumulator = 0

CALA
CALL

Call subroutine indirect
Call subroutine

2
2

1
2

RET

Return from subroutine

LSB

1111 1001 0000 0000
0000 BBBB BBBB BBBB
1111 0100 0000 0000

OQOO BBBB BBBB BBBB

1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
0111
1111
0000
0111

CONTROL INSTRUCTIONS
Mnemonic and Description
Cycles Words

1101 0000 0000
BBBB BBBB BBBB

1100 0000 0000
BBBB BBBB BBBB

0110 0000 0000
BBBB BBBB BBBB

1011 0000 0000
BBBB BBBB BBBB

1010 0000 '0000
BBBB BBBB BBBB

1110 0000 0000
BBBB BBBB BBBB

0101 0000 0000
fBBB BBBB BBBB

111 0000 0000

BBBB BBBB BBBB

1111 1000 1100
1000 0000 0000
BBBB BBBB BBBB

1111 1000 1101
)

16-Bit Opcode
MSB

DINT
EINT
LsT
NOP
POP
PUSH
ROVM
sOVM
SST

Dis!lble interrupt
Enable interrupt
Load status register from data memory
No operation
Pop top of stack to low accumulator
Push low accumulator onto stack
Reset overflow mode
Set overflow mode
Store status register

I/O AND

1
1
1
1
2
2
1
1
1

1
1
1
1
1
1
1
1
1

0111
0111
0111
0111
0111
,0111
0111
0111
0111

LSB

1111
1111
1011
1111
1111
1111
1111
1111
1100

1000 0001
1000 0010
I ODD DODD

1000
1001
1001
1000
1000

0000
1101
1100
10.10
1011

I DOD DODD

DATA MEMORY OPERATIONS
Mnemonic and Description
16-Bit Opcode
Cyc,es Words
MSB
LSB
DMOV Data move in data memory
1
1
0110 1001 I DOD DODD
IN
Input data from port
2
1
0100 OAAA I DOD DODD
OUT
Output data to port
0100 1AAA I DOD DODD
2
1
TBLR
Table read
3
1
0110 0111 I DOD DODD
TBLW
1
0111 1101 I DOD DODD
Table write
3

4-10

Assembly Language Instructions - Individual Descriptions

4.3 Individual Instruction Descriptions
Each instruction in the instruction set summary is described in the following
pages. Instructions are listed in alphabetical order. Information, such as assembler syntax, operands, execution, encoding, description, words, cycles,
and examples, is provided for each instruction. An example instruction is
provided on the next two pages to familiarize the user with the special format
used and explain its content. Refer to Section 4.1 for further information on
memory addressing. Code examples using many of the instructions are given
in Section 5 on Software Applications.

4-11

Example Instruction

EXAMPLE
Syntax

Direct: [] EXAMpLE [,]
Indirect: [] EXAMPLE {*I*+I*-}[, [,]]
Immediate: [] EXAMPL!= []
Each instruction begins with an assembler syntax expression. The optional
comment field that concludes the syntax is not included in the'syntax expression. Space(s) are required between each field (label, command, operand, and comment fields) as shown in the syntax. The syntax example
illustrates both direct and indirect addressing, as well as immediate addressing in which the operand field includes .

Operands

Os dma S 127
ARP = 0 or 1

o ;:;

constant ~ 255

Operands may be constants or assembly-time expressions which refer to
memory, I/O and register addresses, pointers, shift counts, and a variety of
constants. The operand values used in the example syntax are shown.

Execution

(PC) + 1 -+ PC
(ACC) + (dma) x 2shift

ACC

1 -+ interrupt mode (INTM) status bit
Affects INTM.
This section provides an example of the instruction operation sequence,
describing the processing that takes pl~ce when the instruction is executed.
Conditional effects of status register specified modes are also given. In addition, those bits in the status registers that are affected by the instruction
are listed.

-Encoding

15 14

Indirect:

0 01

Shift

1 01

Shift

I 11

Direct: 1

Immediate: 11

Data Memory Address

See Section 4.1

1 3 - Bit Constant

Opcode examples are shown of both direct and indirect addressing or of the
use of an immediate operand.

4-12

EXAMPLE

Example Instruction
Description

This section decribes the instruction execution and its effect on the rest of
the processor or memory contents. Any constraints on the operands imposed by the processor or the assembler are also described here. The description parallels and supplements the information given by the execution
block.

Words

The digit specifies the number of memory words required to store the instruction and its extension words.

Cycles

1
The digit specifies the number of cycles required to execute the instruction.

Example

ADD
or
ADD

DATl,3

; (DP

* ,3

;If current auxiliary register contains 1.

Before Instruction

After Instruction

Data
Memory
1

ACC

17h

The sample code presented in the above format shows the effect of the
code on memory and/or registers.

4-13

Absolute Value of Accumulator

ASS
Syntax

[] ABS

Operands

None

Execution

(PC) + 1

If (ACC) < 0:
Then -(ACC)

Encoding

15 14 13

ACC

10
Description

0 0

If the contents of the accumulator are greater than or equal to zero, the accumulator is unchanged by the execution of ABS. If the contents of the
accumulator are less than zero, the accumulator is replaced by its two'scomplement value.
Note that 80000000h is a special case. When the overflow mode is not set,
the ABS of 80000000h is 80000000h. When in the overflow mode, the
ABS of 80000000h
is 7FFFFFFFh.
,
'

Words
Cycles

Example

ABS

Before Instruction

4-14

After Instruction

ACC

1234h

ACC

1234h

ACC

I OFFFFFFFFh

ACC

Add to Accumulator with Shift

ADD

Syntax
Direct: [] ADD [,]
Indirect: [] ADD {*I*+I*-}[, [,]]

o ~ dma

Operands

ARP

127

= 0 or 1

(PC) + 1 .... PC
(ACC) + (dma) )( 2shift .... ACC

Execution
Encoding

15 14 13

12 11

Direct:

Indirect:

876

54321

I0I

Data Memory Address

Shift
Shift

See Section 4.1

Description

Contents of the addressed data memory location are left-shifted and added
to the accumulator. During shifting, low-order bits are zero-filled, and
high-order bits are sign-extended. The result is stored in the accumulator.

Words

Cycles

Example

ADD
or
ADD

DAT1,3

; (DP = 0)

*,3

;If current auxiliary register contains 1After Instruction

Before Instruction

Example

ADD
or
ADD

Data
Memory
1

ACC

17h

DAT2,4

; (DP = 0)

*,4

;If current auxiliary register contains 2.
Before Instruction

Data
Memory
2
ACC

8BOEh .

After Instruction
Data
Memory
2
ACC

8BOEh

I OFFF8BOEOh
4-15

Add to High Accumulator

ADDH
Syntax

Direct: [] ADDH
Indirect: [] ADDH {*I*+I*-}[,]

Operands

0 S dma S 127
ARP = 0 or 1

Execution

(PC) + 1 ..... PC
(ACC) + (dma) x 2 16 ;.,. ACC

Encoding
Direct:

15 14

I0 I
o 11 I

Data Memory Address

Indirect:

Description

See Section

4.1

Contents of the addressed data memory location are added to the upper
half of the accumulator (bits 31 through 16). Low-order bits are unaffected
by ADDH.
The ADDH instruction may be used in performing 32-bit arithmetic ..

Words

)

Cycles
Example

ADDH
or
ADDH

DAT5

dDP = 0)

iIf current auxiliary register contains 5.

Before InstructIon

4-16

After Instruction

Data
Memory
5

ACC

13h

ACC

40013h

Add to Accumulator
.with Sign-Extension Suppressed

ADDS

Syntax
Direct: [] ADDS
Indirect: [] ADDS {*I*+I*-H,]

Operands

o :s dma :s 127
ARP

Execution

Encoding
Direct:

= 0 or 1

(PC) + 1 ... PC
(ACC) + (dma) ... ACC
(dma) is a 16-bit unsigned number.
Affects OV; affected by OVM.
15 14

I°

12
0

11
0

10
0

I° I

Data Memory Address

Indirect: 1.. 1_o_____o__o__o
__o__.LI_'-..&.I_ _ _ _s_ee_s.;..e.....ct.;..io.;..n_4_._' _ _---l

Description

Contents of the specified data memory location are added with sign-extension suppressed. The data is treated as a 16-bit unsigned number rather
than a two's-complement number. Therefore, there is no sign-extension as
with the ADD instruction.
The ADDS instruction can be used in implementing 32-bit arithmetic.

Words

Cycles

Example

ADDS

DATll

; (DP = 0)

;If current auxiliary register contains 1l.

or
ADDS

Before Instruction
Data
Memory
11
ACC

OFOO6h

After Instruction
Data
Memory
11

OFOO6h

ACC

OFOO9h

4-17

AND

AN D with Low-Order Bits of Accumulator

Syntax
Direct: [] AND
Indirect: [] AND {*I*+I*-}[,]

Operands

0 ::; dma ::; 127
ARP = 0 or 1

Execution

(PC) + 1 -+ PC
(ACC(15-0».AND.(dma)
-+ ACC(31-16)

o
Encoding

15 14 13

Direct:

Indirect:

ACC(15~O)

10 I
11

Data Memory Address

See Section 4.1

Description

The lower half of the accumulator is ANDed with the contents of the addressed data memory location. The upper half of the accumulator is ANDed
with all zeroes. Therefore, the upper half of the accumulator is always zeroed by the AND instruction.

Words

Cycles

Example

AND

DAT16

i (DP =

iIf current auxiliary register contains 16.

or
AND

Before Instruction
Data
Memory
16
ACC

4-18

OFFh

12345678h

After Instruction
Data
Memory
16
ACC

OFFh

78h

Add P Register to Accumulator

Syntax

[] APAC

Operands

None

Execution

(PC) + 1 ... PC
(ACC) + (P register) ... ACC
Affects DV; affected by DVM.

Encoding

Description

15 14 13

APAC

The contents of the P register, the result of a multiply, are added to the
contents of the accumulator. The result is stored in the accumulator.
The APAC instruction is a subset of the LTA and LTD instructions.

Words
Cycles

Example

APAC

Before Instruction

After Instruction

40h

ACC

20h

ACC

,60h

4-19

Branch Unconditionally

Syntax

[] B

Operands

Execution

pma

Encoding

pma
-+

4095

15 14

13 12 11

6
0

5
0

4
0

o
o

Program Memory Address

Description

Control passes to the designated program memory address (pma). Pma can
be either a symbolic or a numeric address.

Words

Cycles

Example

4-20

PRG191

191 is loaded into the program counter,
and the program continues running from
that location.

Branch on Auxiliary Register Not Zero

Syntax

[] BANZ

Operands

o :s

Execution

If (AR bits 8-0) ¢ 0:
Then pma .... PC;
Else (PC) + 2 ~ PC
(AR) - 1 .... AR. I.

Encoding

15 14 13

BANZ

pma :s 4095

9
8
7
6
5
4
3
2
o
0000000000

Program Memory Address

Description

If the lower nine bits of the current auxiliary register are not equal to zero,
then the address contained in the following word is loaded into the program counter. If these bits are equal to zero, the current program counter is
incremented by two. In either case, the auxiliary register is decremented.
Note that the test for zero is performed before decrementing the auxiliary
register. The branch to a location in program is specified by the program
memory address (pma). Pma can be either a symbolic or numeric address.

Words

Cycles

Example

BANZ

PRG35

Before Instruction

After Instruction

46h

35h

OFFFFh

46h

48h

Note:
BANZ is designed for loop control using the auxiliary registers as loop
counters. The auxiliary register is decremented after testing for zero~
The .auxiliary registers also behave as modulo 512 counters.

4-21

Branch if Accumulator
Greater Than or Equal to lero

BGEl
Syntax

[] BGEZ

Operands

Execution

If (ACC) ~ 0:
Then pma -+ PC;
Else (PC) + 2 -+ PC.

Encoding

pma

15 14

BGEl

4095

7
6
5
4
3
2
1 0
00000000

Program Memory Address
/

Description

If the contents of the accumulator are greater than or equal to zero, then
branch to the specified program memory location. The branch to a location
in program is specified by the program memory address (pma). Pma can
be either a symbolic or numeric address.

Words

Cycles

Example

BGEZ

4-22

. PRG2l7

217 is loaded into the program counter
if the accumulator is greater than or
equal to zero.

Branch if Accumulator Greater Than Zero

Syntax

[] BGZ

Operands

o :s

Execution

If (ACC) > 0:
Then pma -+ PC;
Else (PC) + 2 -+ PC.

Encoding

15 14 13

pma

BGZ

4095

12 11

0000000000
Program Memory Address

Description

If the contents of the accumulator are greater than zero, then branch to the
specified program memory location. The branch to a location in program
is specified by the program memory address (pma). Pma can be either a
symbolic or numeric address.

Words

Cycles

Example

BGZ

PRG342

;342 is loaded into the program counter
;if the accumulator is greater than zero.

4-23

BIOZ

Branch on I/O Status Equal to Zero

Syntax

[] SIOl

Operands

o :S pma

Execution

If BIO = 0:
Then pma .... PC;
Else (PC) + 2 .... PC.

Encoding

15 14

:S' 4095

8
7
6
5
4
3
2
1 0
000000000

Program Memory Address

Description

If the BIO pin is active low, then branch to the specified program memory
location. Otherwise, the program counter is incremented to the next instruction. The branch to a location in program is specified by the program
memory address (pm~). Pma can be either a symbolic or numeric address.
The SIOl instruction in conjunction with the BIO pin can be used to test if
a peripheral is ready to send or receive data. Polling the BIO pin using SIOl
may be preferable to an interrupt when executing time-critical loops. .

Words

Cycles

Example

BIOZ

4-24

PRG64

If the ~ pin is active (low), then
a branch to location 64 occurs. Otherwise,
the program counter is incremented.

Branch if Accumulator
Less Than or Equal to Zero

BLEZ
Syntax

[] BLEZ

Operands

o :s pma :s 4095

Execution

If (ACC) :s 0:
Then pma -+ PC;
Else (PC) + 2 -+ PC.

Encoding

15 14

BLEZ

Program Memory Address

Description

If the contents of the accumulator are less than or equal to zero, then
branch to the specified program memory location. The branch to a location
in program is specified by the program memory address (pma). Pma can
be either a symbolic or numeric address.

Words

Cycles

Example

BLEZ

PRG63

63 is loaded into the program counter if
the accumulator is less than or equal to
zero.

4-25

Branch if Accumulator less Than Zero

BlZ
Syntax

[ ] BLl

Operands

Execution

If (ACC) < 0:
Then pma -+ PC;
Else (PC) + 2 -+ PC.

Encoding

15 14 13 12 11

pma

4095

000000000

Program Memory Address

Description

If the contents of the accumulator are less than zero, then branch to the
specified program memory location. The branch to a location in program
is specified by the program memory address (pma). Pma can be either a
symbolic or numeric address .

. Words

Cycles

Example

BLZ

~-26

PRG481

;481 is loaded into the program counter
;if the accumulator is less than zero.

Branch if Accumulator Not Equal to Zero
Syntax

[] BNZ

Operands

o ~ pma

Execution

If (ACC) '¢ 0:
Then pma ..... PC;
Else (PC) + 2 ..... PC.

Encoding

15 14 13

BNZ

~ 4095

8
7
6
5
4
3
2
o
000000000

Program Memory Address

Description

If the contents of the accumulator are not equal to zero, then branch to the
specified program memory location. The branch to a location in program
is specified by the program memory address (pma). Pma can be either a
symbolic or numeric address.

Words

Cycles

Example

BNZ

PRG320

i320 is loaded into the program counter
i i f the accumulator does not equal zero.

4-27

Branch on Overflow

Syntax

[] BV

Operands

o :s pma :s 4095

Execution

If overflow (OV) status bit = 1:
Then pma -+ PC and 0 -+ OV;
Else (PC) + 2 -+' PC.
Affects OV; affected by OV.

Encoding

15 14

12 11 "10

'7
6
5
4
32
00000000

Prot;Jram Memory Address

Description

If the overflow (OV) flag has been set, then a branch to the specified program memory location occurs and the overflow flag is cleared. Otherwise,
the program counter is incremented to the next instruction: The branch to
a location in program is specified by the program memory address (pma).
Pma can be either a symbolic or numeric address.

Words

Cycles

Example

4-28

PRG6l0

If an overflow has occurred since the
overflow flag was last cleared, then 610
is loaded into the program counter and
OV is cleared. Otherwise, the program
counter is incremented.

Branch if Accumulator Equals Zero

Syntax

[] BZ

Operands

O:s; pma :s; 4095

Execution

If (ACC) = 0:
Then pma -+ PC;
Else (PC) + 2 -+ PC.

Encoding

15 14

00000000
Program Memory Address

Description

If the contents of the accumulator are equal to zero, then branch to the
specified program memory location. The branch to a location in program
is specified by the program memory address (pma). Pma can be either a
symbolic or numeric address.

Words

Cycles

Example

PRG102

;102 is loaded into the program counter
;if the accumulator is equal to zero.

4-29

CALA

Call Subroutine Indirect

Syntax

[] CALA

Operands

None

Execution

(PC) + 1 .... TOS
(ACC(11 -0» .... PC

Encoding

15 14 13

10
Description

0
0

The current program counter is incremented and pushed onto the top of the
stack. Then, the contents of the 12 least significant bits of the accumulator
are loaded into the PC.
The CALA instruction is used to perform computed subroutine calls.

Words

Cycles

Example

CALA

Before Instruction

After Instruction

25h

83h

ACC

83h

ACC

83h

Stack

4-30

32h
75h
84h
49h

Stack

26h
32h
75h
84h

Call Subroutine

CALL

Syntax

[] CALL

Operands

Execution

(PC) + 2 ~ TOS
pma ~ PC

Encoding

pma

4095

15 14 13 12 11

43210

Program Memory Address

Description

The current program counter is incremented by two and pushed onto the
top of the stack. The specified program memory address (pma) is then
loaded into the PC. Pma can be either a symbolic or a numeric address.

Words

Cycles

Example

CALL

PRGI09
Before Instruction
PC

After Instruction
PC

6Dh

Stack

16h

35h
71h
48h

80h

16h

33h

71h
Stack

48h

4-31

Disable Interrupt

DINT
Syntax

[] DINT·

Operands

None

Execution

(PC) + 1

1 ~ interrupt mode (INTM) status bit
Affects INTM.
Encoding

Description

15 14
10

6
0

5
0

4
0

3
0

2
0

o
o

The interrupt mode (INTM) status bit is set to logic 1. Maskable interrupts
are disabled immediately after the DINT instruction executes. Interrupts are
also disabled by a reset. Note that the LST instruction does not affect
INTM_
"
The unmaskable interrupt, RS, is not disabled by this instruction. Interrupts
are also disabled by a reset.

Words
Cycles

Example

DINT

4-32

;Maskable interrupts are disabled, and INTM
;is set to one.

DMOV

Data Move in Data Memory

Syntax
Direct: [] DMOV
Indirect: [] DMOV {*I*+I*-}[,]

Operands
Execution

0 S dma S 127
ARP = 0 or 1

(PC) + 1
(dma)

Encoding

15 14

I0
Indirect: I 0

dma + 1
13

Direct:

Description

10 1

11 1

Data Memory Address

See Section

4.1

The contents of the specified data memory address are copied into the
contents of the next higher address. When data is copied from the addressed location to the next higher location, the contents of the addressed
location remain unaltered.
The data move function is useful in implementing the z-1 delay encountered
in digital signal processing. The DMOV function is included in the LTD instruction (see LTD for more information).

Words
Cycles

Example

DMOV
or
DMOV

OATS

;If current auxiliary register contains S.
Before Instruction

After Instruction

Data
Memory

43h

Data
Memory

43h

Data
Memory

43h

4-33

EINT

Enable Interrupt

Syntax

[ ] EINT

Operands

None

Execution

(PC) + 1

o -+ interrupt mode (INTM) status bit
Affects INTM.

Encoding

Description

15 14
10

8
1

6
0

5
0

4
0

3
0

2
0

0
01

The interrupt mode (INTM) status bit is cleared to logic O. Maskable interrupts are enabled after the instruction following EINT executes. This allows an interrupt service routine tore-enable interrupts and execute a RET
instruction before any other pending interrupts are processed. Note that the
EINT instruction should not be used immediately preceding a branch instruction.
The LST instruct!on does not affect INTM. (See the DINT instruction for
further information.)

Words

Cycles

Example

EINT

4-34

;Maskable interrupts are enabled, and INTM
lis set to zero.

Input Data from Port

Syntax
Direct: [] IN ,
Indirect: [] IN {*I*+I*-},[,]

Operands

0 s dma :s 127
ARP = 0 or 1
o :s port address PA :S 7

Execution

(PC) + 1 -+ PC
Port address -+ address lines A2/PA2-AO/PAO
o -+ address bus A11-A3
Data bus D15- DO -+ dma

Encoding

15 14

Direct: 1

° ° ° 1 Port Address 1 ° 1

Data Memory Address

Indirect: 1
...._o____o--o--o...I'--Po-rt-A-dd-r-es-s--'-I-,....IIL.----S-8-e-S_8_ct_io_n_4_._1_ _ _...

Description

The IN instruction reads data from a peripheral and places it in data memory. This is a two-cycle instruction. During the first cycle, the port address
is sent to address lines A2/PA2-AO/PAO. DEN goes low during the same
cycle, strobing in the data that the addressed peripheral places on the data
bus D15- DO. On the TMS3201 0/C1 0/C15/E15, MEN will remain high
when DEN is active. On the TMS320C17 /E17, the MEN signal is not available.
'

Words

Cycles

Example

STAT,PA5

Read in word from peripheral on port
address 5. Store in data memory
location STAT.

or
LARK
LARP
IN

1,20
1

*-,PA1,0

Load AR1 with decimal 20.
Load ARP with decimal 1.
Read in word from peripheral on port
address 1. Store in data memory
location 20. Decrement AR1 to 19.
Load the ARP with o.

4-35

LAC

Load Accumulator with Shift

Syntax
Direct: [] LAC [,]
Indirect:, [] LAC {*I*+I*-}[, [,J]

Operands

0 ~ dma ~ 127
ARP = 0 or 1
o ~ shift :s 15 (defaults to 0)

Execution

(PC) + 1 -+ PC
(dma) x 2 shift -+ ACC

Encoding

1 5 14

Direct:
Indirect:

° °

°I

Shift

1 01

Data Msmory Address

1'--0__0____0. .1_____S_hi_ft_ _--'-_-'--_
I 1 I _ _S_ee_S_s_c_tio_n_4_._1_ _----'

Description

Contents of the specified data memory address are left-shifted .and loaded
into the accumulator.' During shifting, low-order bits, are zero-filled.
High-order bits are sign-extended.

Words

Cycles

Example

LAC
or
LAC

DAT6,4

i(DP =

*,4

iIf current auxiliary register contains 6.

After Instruction

Before Instruction
Data
Memory

6
ACC

4-36

Data
Memory

ACC

10h

Load Accumulator Immediate

LACK

Syntax

[] LACK

Operands

o :S

Execution

(PC) + 1 -+ PC
8-bit positive constant

Encoding

constant :S 255

15 14

ACC

Description

8-Bit Constant

The 8-bit constant is loaded into the accumulator right-justified. The upper
24 bits of the accumulator are zeroed (i.e., sign extension is suppressed).

Words
Cycles
Example

LACK

ISh
Before Instruction
ACC

31 h

After Instruction
ACC

15h

4-37

toad Auxiliary .Register

LAR

Syntax
Direct: [] LAR ,
Indirect: [] LAR ,{*I*+I*-}[,]

Operands

o :s dma :s 1 27

auxiliary register AR
ARP = 0 or 1

Execution

(PC) + 1

= 0 or 1

(dma) -+ auxiliary register AR

Encoding
15 14 13
0
Direct: 0

I
Indirect: I 0

Description

o IAR

I 1I

4
2
3
Data Memory Address
See Section 4.1

0
I

The contents of the specified data memory address are loaded into the designated auxiliary register. The LAR and SAR (store auxiliary register) instructions can be used to load and store the auxiliary registers during
subroutine calls and interrupts. If an auxiliary register is not being used for
indirect addressing, LAR and SAR enable the register to be used as an additional storage register, especially for swapping values between data
memory locations without affecting the contents of the accumulator.
If indirect addressing is used to load the current auxiliary register (Le., if the
AR specified in the LAR instruction is the AR pointed to by the ARP), then
the new value will be loaded into the auxiliary register from data memory
and any decrement or increment specified will not be performed.

Words

Cycles
Example

LAR

ARO,DAT19
Before Instruction
Data
Memory

ARO

also,

LARP
LAR

18h

ARO

18h

32h

Data
Memory

32h

ARO

32h

ARO,*Data
Memory

ARO

4-38

After Instruction
Data
Memory

Load Auxiliary Register Immediate

LARK

Syntax

[] LARK ,

Operands

o :S

Execution

constant :S 255
auxiliary register AR

(PC) + 1

--+

8-bit constant
Encoding

15 14

I0
Description

= 0 or 1

--+

auxiliary register AR

12 11
0

10
0

987

o IAR

543

8- Bit Constant

The 8-bit positive constant is loaded into the designated auxiliary register
right-justified and zero-filled (i.e., sign-extension suppressed).
LARK is useful for loading an initial loop counter value into an auxiliary
register for use with the BANZ instruction.

Words

Cycles
Example

LARK

ARO,21h

Before Instruction
ARO

After Instruction
ARO

21 h

4-39

LARP

Load Auxiliary Register Pointer

Syntax

[] LARP

Operands

Execution

(PC) + 1 ... PC
Constant ... ARP
Affects ARP

Encoding

Description

cohstant S 1

15 14

12
0

I
\,

6
0

5
0

o ~R~

The auxiliary register pointer is loaded with the one-bit constant identifying
the desired auxiliary register. ARP can also be modified by the LST and
MAR instructions, as well as any instruction that is used in the indirect addressing mode.
The LARP instruction is a subset of MAR; i.e., the opcode is the same as
MAR in the indirect addressing mode. The instruction MAR *,
has the same effect as LARP.

Words
.Cycles
Example

4-40

LARP

Any succeeding instructions will use
auxiliary register ARl for indirect
addressing.

Load Data Memory Page Pointer

LDP

Syntax
Direct: [] LDP
Indirect: [] LDP {*I*+I*-}[,]

Operands

o :s dma :s 127
ARP

Execution

Encoding

= 0 or 1

(PC) + 1 ~ PC
LSB of (dma) ~ data memory page pointer (DP
Affects DP.
15 14

Direct:' 0

or 1)

Data Memory Address'

Indirect: 1L._O_ _ _ _ _O_ _ _ _ _ _ _--L._-'-_ _ _s_e_e_s_e_ct_iO_"_4_.1_ _ _--"

Description

The least significant bit of the contents of the specified data memory address is loaded into the DP (data memory page pointer) register. All higher-order bits are ignored in the data word. DP = 0 defines page 0 that
contains words 0-127. DP = 1 defines page 1 that contains words
128-143/255. The DP may also be loaded by the LST and LDPK instructions.

Words

Cycles
Example

LDP
or
LDP

DATI

;LSB of location DATI is loaded into DP.

*,1

;LSB of location currently addressed by
;auxiliary register is loaded into DP.
;ARP is set to 1.

After Instruction

Before Instruction
Data
Memory
1
DP

OFEDCh

Data
Memory
1
DP

OFEDCh

Load Data Memory Page Pointer Immediate

LDPK
Syntax

[] LDPK

Operands

Execution

(PC) + 1 -+ PC
Constant -+ data memory page pointer (DP)
Affects DP.

Encoding

constant

15 14

IDP I

Description

The DP (data memory page pointer) register is loaded with a 1-bit constant.
D P= 0 defines page 0 that contains words 0-127. D P = 1 defines page 1
that contains words 128-143/255. The DP may also be loaded by the LST
and LDP instructions.

Words

Cycles
Example

4-42

LDPK

;The data page pointer is set to O.

Load Status Register from Data Memory

LST

Syntax
Direct: [] LST
Indirect: [] LST {*I*+I*-}[,]

Operands

Os dma S 127
ARP

Execution

= 0 or 1

(PC) + 1

(dma) -> status register bits
Affects ARP, OV, OVM, and DP.
Does not affect INTM.

Encoding
Direct:

15 14

Data Memory Address

Indirect: 1
...._0_ _ _ _ _ _ _ _ _0_ _ _ _..L..-----'_ _ _ _S_e_e_S_e_ct_io_"_4_.1_ _ _---'

Description

The status register is loaded with the addressed data memory value. Note
that the INTM (interrupt mode) bit is unaffected by LST.
The LST instruction is used to load the status register after interrupts and
subroutine calls. The status register contains the status bits: OV (overflow
flag) bit, OVM (overflow mode) bit, ARP (auxiliary register pointer), and
DP (data memory page pointer). These bits were stored (by the SST instruction) in the data memory word as follows:
15

1OV IOVMIINTM 1

11 10

987

jARP 11

IDP I

Words
Cycles

Example

LARP
or

LST

o
*,1

iThe data memory word addressed by the
icontents of auxiliary register ARO
ireplaces the status bits. ARP becomes 1.

Note:
When using direct addressing, the SST instruction always saves status
on page 1. The LST instruction will not automatically restore status
from page 1. Therefore, the user must specify the correct data page
pointer.

4-43

Load T R$gister

Syntax

Direct: []' LT
Indirect: [] LT {*I*+I*-}[,]

Operands

o :s dma :s 127 .
ARP = 0 or 1

Execution
Encoding

(PC) + 1 -> PC
(dma) -> T register
10

01 0

Data Memory Address

Indirect:

o 11

See Section 4.1

Description

15 14 ·13

Direct:

The T register is loaded with the contents of the specified data memory location. The LT instruction may be I.Jse~ to load the T register in preparation
for multiplication (see the LTA, LTD,'MPV, and MPVK instructions).

Words
Cycles
Example

LT
or
LT

DAT24

(DP

iIf current au~iliary register contains 24.

Before Instruction
Data
Memory
24
T

4-44

62h

After Instruction
Data
Memory
24

62h

Load T Register and Accumulate Previous Product

LTA

Syntax
Direct: [] LTA
Indirect: [] LTA {*I*+I*-}[,]

Operands

0 :S dma :S 1 27
ARP = 0 or 1

Execution

(PC) + 1 -> PC
(dma) -> T register
(ACC) + (P register) -> ACC
Affects OV; affected by OVM.

Encoding

15 14

Direct:

Indirect:

Description

01 0

Data Memory Address

o 11

See Section 4.1

0
1

The T register is loaded with the contents of the specified data memory
address. The P register, containing the previous product of the multiply
operation, is added to the accumulator, and the result is stored in the accumulator.
The function of the LTA instruction is included in the LTD instruction.

Words

Cycles

Example

LTA
or
LTA

DAT24

; (DP = 0)

;If current auxiliary

registe~

Before Instruction
Data
Memory
24

62h

contains 24.

After Instruction
Data
Memory
24

62h

OFh

ACC

14h

ACC

4-45

Load T Register, Accumulate
Previous Product. and' Move Data

LTD

Syntax
Direct: [] LTD
Indirect: [] LTD {*I*+I*-}[,]

Operands

0 :s dma :s 127
ARP = 0 or 1

Execution

(PC) + 1 -+ PC
(dma) -+ T register
(dma) -+ dma + 1
(ACC) + (P register) -+ ACC
Affects OV; affected by OVM.

Encoding

15 14

Direct:

Indirect:

Description

I I
I1 I

Data Memory Address

See Section 4.1

The T register is loaded with the contents of the specified data memory
address. The contents of the P register are added to the accumulator, and
the result is placed in the accumulator. The contents of the specified data
memory address are also copied to the next higher data memory address.
This function is described under the instruction DMOV.

Words
Cycles
Example

LTD
or
LTD

DAT24

; (DP

;If

curren~

auxiliary register contains 24.

Before Instruction
Data
Memory
24

After Instruction

62h

Data
. Memory
24

62h

Data
Memory
25

62h

OFh

ACC

14h

ACC

4-46

Modify Auxiliary Register

MAR

Syntax
Direct: [] MAR
Indirect: [] MAR {*'*+'*-}[,]

s dma s 127
ARP = 0 or 1

Operands

Execution

(PC) + 1 -+ PC
Modifies AR(ARP). ARP as specified by the indirect addressing field
(acts as a NOP in direct addressing).

Encoding

15 14

I0
Indirect: I 0
Direct:

Description

Data Memory Address

See Section 4.1

In the indirect addressing mode, the auxiliary registers are either incremented or decremented and the ARP is modified; however, no use is made
of the memory being referenced. MAR is used only to modify the auxiliary
registers or the ARP. ARP may also be loaded by an LST instruction.
MAR acts as a no-operation (NOP) instruction in the direct addressing
mode. Also, the LARP instruction is a subset of MAR (i.e., MAR *,0 performs the same function as LARP 0).

Words
Cycles

4-47

MAR

Example 1

Modify Auxiliary Register

MAR

*,1

;Load the ARP with 1.
Before Instruction

ARP

. Example 2

MAR

After Instruction
ARP

;Decrement current auxiliary register (in this
;case, ARl)
Before Instruction

AR1

Example 3

MAR

*+,0

I .

35h

After Instruction
AR1

34h

;Increment current auxiliary register (AR1)
;and load ARP with o.
Before Instruction

4-48

After Instruction

AR1

34h

AR1

35h

ARP

Multiply

MPY

Syntax
Direct: [] MPY
Indirect: [] MPY {*I*+I*-}[,]

Operands

o :s dma :s 127
ARP = 0 or 1

Execution
Encoding
Direct:

(PC) + 1 -+ PC
(T register) x (dma)
15 14

P register
10

Data Memory Address

Indirect:L,.I_o_ _ _ _ _O
______
o_ _.l..---I_ _ _ _s_e_e_s_e_ct_io_n_4_.1_ _ _.....1

Description

The contents of the T register are multiplied by the contents of the addressed data memory location. The result is placed in the P register.
During an interrupt, all registers except the P register can be saved and restored directly. However, the first-generation TMS320 devices have hardware protection against servicing an interrupt between an MPY or MPYK
instruction and the following instruction. For this reason, it is advisable to .
follow MPY and MPYK with LTA, LTD, PAC, APAC, or SPAC.
Note that no provisions are made for the condition of 8000h x 8000h. If
this condition arises, the product will be OCOOOOOOOh.

Words·

Cycles
Example

MPY
or
MPY

DAT13

;(DP

;If current auxiliary register contains 13.

Before Instruction

After Instruction

Data
Memory
13

36h

2Ah

4-49

MPYK

Multiply Immediate

Syntax

[] MPYK

Operands

-2 12 S constant < 212

Execution

(PC) + 1 -+ PC
(T register) x constant

Encoding

Description

15 14

-:+ P register
10

13-Bit Constant

The contents of the T register are multiplied by the signed 13-bit constant.
The result is loaded into the P register.
During an interrupt, all registers except the P register can be saved and restored directly. Since no provision is made to save the contents of the P
register during an interrupt, the MPYK instruction should be followed by
one of the following instructions: PAC, APAC, SPAC, LTA, or LTD. Provision is made in hardware to inhibit interrupt during MPYK until the next
instruction is executed.

Words

Cycles

Example

MPYK

-9
Before Instruction
T

4-50

After Instruction

2Ah

IOFFFFFFC1 h

NOP

No Operation

Syntax

[] NOP

Operands

None

Execution

(PC) + 1

Encoding

15 14 13
10

Description

12 11

o
o

No operation is performed. NOP affects only the PC.
NOP is useful as a pad or temporary instruction during program development.

Words
Cycles
Example

NOP

4-51

OR with Accumulator

. Syntax
Direct: [] OR
Indirect: [] OR {*I*+I*-}[,]
Operands

0 s dma s 127
ARP = 0 or 1

Execution

(PC) + 1 -+ PC
(ACC(15-0» .OR.dma -> ACC(15-0)
(ACC(31 -16» -+ ACC(31 -16)

Encoding

15 14

Direct: 10

01 0

Indirect:
Description

Data Memory Address

See Section 4.1

The low-order bits of the accumulator are ORed with the contents of the
addressed data memory location. The high-order bits of the accumulator
are ORed with all zeroes. Therefore, the upper half of the accumulator is
unaffected by this instruction. The result is stored in the accumulator.
The OR instruction is useful for comparing. selecte.Q bits of a data word.

Words
Cycles
Example

OR
or
OR

DAT88

; (DP

;Where current auxiliary register contains 88.

After Instruction

Before Instruction
Data
Memoy,.'

8E'
ACC

4-52

OFOOOh

Data
Memory

100002h

ACC

OFOOOh

88
10F002h

Output Data to Port

OUT

Syntax
Direct: [] OUT ,
Indirect: [] OUT {*I*+I*-},[,]
Operands

0 :s dma :s 1 27
ARP = 0 or 1
o :s port address PA :S 7

Execution

(PC) + 1 -+ PC
Port address PA -+ address bus A2/PA2-AO/PAO
o -+ address bus A11-A3
(dma) -+ data bus 015-00

Encoding

15 14 13

Direct:

Port Address

Data Memory Address

Indirect: ~1_o____o
__o__~I_p_o_rt_A_d_d_r_es_s---L_1~1_ _ _ _s_e_e_S_ec_t_io_n_4_.1_ _ _........1
Description

The OUT instruction transfers data from data memory to an external peripheral. The first cycle of this instruction places the port address onto address lines A2/PA2-AO/PAO. During the same cycle, WE goes low and the
data word is placed on the data bus 015- DO. On the
TMS32010/C1 0/C15/E15, MEN remains high during the first cycle. On the
TMS320C17 /E17, the MEN signal is not available.

Words

Cycles

Example

OUT

120,7

Output data word stored in data memory
location 120 to peripheral on port
address 7.

or
OUT

*,5

Output data word referenced by current
auxiliary register to peripheral on port
address 5.

4-53

PAC

Load Accumulator with P Register

Syntax

[] PAC

Operands

None

Execution

(PC) + 1 -+ PC
(P register) -+ ACC

Encoding

15 14 13

0
01

Description

The contents of the P register resulting from a multiply are loaded into the
accumulator.

Words

Cycles
Example

PAC

Before Instruction

4-54

144h

ACC

23h

After Instruction
P

144h

ACC

144h

Pop Top of Stack to Low Accumulator

Syntax

[] POP

Operands

None

Execution

(PC) + 1 -+ PC
(TOS) .... ACC(11 -0)
o .... ACC(31-12)
Pop stack one level.

Encoding

Description

15 14 13

POP

The contents of the top of the stack (TOS) are copied to the low accumulator, and the stack popped after the contents are copied. The next ele-·
ment on the stack becomes the top of the stack.. The upper bits (31 -12)
of the accumulator are zeroed. The hardware stack is a last-in, first-out
stack with four locations. Any time a pop occurs, every stack value is copied to the next higher stack location, and the top value is removed from
the stack. After a pop, the bottom two stack words will have the same
value. Because each stack value is copied, if more than three pops (due to
POP or RET instructions) occur before any pushes occur, all levels of the
stack contain the same value.

Words
Cycles

Example

POP

Before Instruction
ACC

Stack

a2h
45h
16h
7h
33h

After Instruction
ACC

Stack

t!·5h
16h
7h
33h
33h

4-55

PUSH

Push Low Accumulator onto Stack

Syntax

[] PUSH

Operands

None

Execution

(PC) + 1 -+ PC
Push all stack locations down one level.
(ACC(11 -O)} -+ TOS

Encoding

Description

15 14

The contents of the lower 12 bits (11-0) of the accumulator are copiE!d
onto the top of the hardware stack. The stack is pushed down before the
accumulator value is copied. The hardware stack is a last-in, first-out stack
with four locations. If more than four pushes (due to CAlA, CAll, PUSH,
TBlR, or TBLW instructions or interrupts) occur before a pop, the first data
values written will be lost with each succeeding push.

Words
Cycles

Example

POSH

Before Instruction
ACC

Stack

DJ
h
5h
3h

4-56

After Instruction
ACC

Stack

7hl
h
2h
5h
3h

RET

Return from Subroutine

Syntax

[] RET

Operands

None

Execution

(TOS) -+ PC
Pop stack one level.

Encoding

15 14 13

Description

12 11

6
0

0
0

The contents of the top of stack are copied into the program counter. The
stack is then popped one level. RET is used in conjunction with CALA and
CALL for subroutines and interrupts.

Words
Cycles

Example

RET

Before Instruction
PC

Stack

96h
37h
45h
75h
75h

After Instruction
PC

Stack

37h
4511
75h
75h
75h

4-57

ROVM

Reset Overflow Mode

Syntax
Operands
Execution

[] ROVM
~

None

(PC) + 1 .... PC

o ....

OVM status bit
Affects OVM.

Encoding

15 U

13 12 11

9
1

6543210

Description

The OVM status bit is reset to logic zero. This disables the ove.rflow mode,
in which the device was placed by the SOVM instruction. If an overflow
occurs with OVM reset, the OV (overflow flag) is set, and the overflowed
result is placed in the accumulator. OVM may also be loaded by the LST
and SOVM instructions (see the SOVM instruction).

Words

Cycles

Example

ROVM

4-58

The overflow mode bit OVM is reset,
disabling the overflow mode on any
subsequent arithmetic operations.

Store High Accumulator with Shift

SACH

Syntax
Direct: [] SACH [,]
Indirect: [] SACH {*'*+'*-}[, [,]]

Operands

o :s dma :s 127
ARP
shift

Execution
Encoding
Di.rect:

= 0 or 1
= 0, 1, or 4

(PC) + 1 ... PC
16 MSBs of (ACC) x 2shift ... dma
1 5 14

I°

Shift

I °I

Data Memory Address

Indirect: L..1_O_ _ _ _
O_ _ _....J..__S_h_if_t_....J..I_,. &.1____
S_ee_s_e_c_tio_n_4_._1_ _---'

Description

The SACH instruction copies the entire accumulator into a shifter. It then
left-shifts this entire 32-bit number 0, 1, or 4 bits, and copies the upper 16
bits of the shifted value into data memory. The accumulator itself remains
unaffected.

Words

Cycles

Example

SACH
or
SACH

DAT70,1

i(DP =

*,1

iIf current auxiliary register contains 70.
After Instruction

Before Instruction
ACC
Data
Memory
70

4208001h

ACC
Data
Memory
70

4208001h

841h

4-59

SAel

Store low Accumulator

Syntax
Direct: []. SACl
Indirect: [f SACl {*I*+I*-}[,[,]]

Operands

0 :s dma :s 1 27
ARP = 0 or 1
shift = 0

Execution

(PC) + 1 ~ PC
(ACC(15-0» ~ dma

Encoding

15 14

I0
Indirect: I 0

Direct:

01 0

Data Memory Address

0
1

See Section 4.1

Description

The low-order bits of the accumulator are stored in data memory. There is
no shift associated with this instruction, although a shift code of zero
MUST be specified if the ARP is to be changed.

Words

Cycles

Example

SACL
or
SACL

(DP = O)

DAT71

iIf current auxiliary register contains 71.

Before Instruction
Data
Memory
71
ACC

7C638421h

'4-60

AttAr Instruction
Data
Memory
71
ACC

8421h

7C638421h

Store Auxiliary Register

SAR

Syntax
Direct: [] SAR ,
Indirect: [] SAR ,{*I*+I*-}[,]

Operands

Execution

0 :s; dma :s; 127
auxiliary register AR
ARP = 0 or 1

= 0 or 1

(PC) + 1 -+ PC
(auxiliary register AR)

Encoding

1 5 14

Direct: /

dma

10
0

o /AR

I °I

Data Memory Address

Indirect: I...._o__o_____o__o
__O.....I....A_R-'-I_1--&.1_ _ _ _s_ee_s_e_c_tio_n_4_,_1_ _----'

Description

The contents of the designated auxiliary register are stored in the addressed
data memory location. For more information, see the LAR instruction.

Words
Cycles

4-61

SAR
Example

,Store Auxiliary Register
1

BAR
or
BAR

ARO,DAT30 ;(DP

;If current auxiliary register contains 30.

ARO,*

(

Before Instruction

Example

ARO

37h

Data
Memory
30

18h

LARP
BAR

After Instruction

ARO

37h

Data
Memory
30

37h

ARO
ARO,*+

ARO

Data
Memory
5

Warning:
Special problems arise when SAR is used to store the current
auxiliary register with indirect addressing if autoincrement/decrement is ~sed.
LARP
LARK
BAR

ARO
ARO,IO
ARO,*+

BAR

ARO,*-

In this case, SAR ARO,*+ will cause the value 11 to be stored
in location 10. SAR ARO,*- will cause the value 9 to be stored
in location 10.

4-62

Set Overflow Mode

SOVM

Syntax

[] SOVM

Operands

None

Execution

(PC) + 1 -+ PC
1 -+ overflow mode (OVM) status bit
Affects OVM.

Encoding

15 14
10

Description

2
0

o
1 1

The OVM status bit is set to logic 1, which enables the overflow (saturation) mode. If an overflow occurs with OVM set, the overflow flag OV is
set, and the accumulator is set to the largest representable 32-bit positive
(7FFFFFFFh) or negative (80000000h) number according to the direction
of overflow. OVM may also be loaded by the LST and ROVM instructions.
(See the ROVM instruction for further information.)

Words
Cycles

Example

SOVM

The overflow mqde bit OVM is set, enabling
the overflow mode on any subsequent
arithmetic operations.

4-63

Subtract P Register from Accumulator

SPAC
Syntax

[] SPAC

Operands

None

Execution

(PC) + 1 ..... PC
(ACC) - (P register) ..... ACC
Affects OV; affected by OVM.

Encoding

15 14 13

I 01

o
o

Description

The contents of the ,P register are subtracted from the contents of the accumulator. The result is stored in the accumulator. Note that the P register
is always sign-extended.

Words

Cycles

Example

SPAC

Before Instruction

4-64

After Instruction

24h

ACC

3Ch

ACC

18h

Store Status Register

SST

Syntax
Direct: [] SST
Indirect: [] SST {*I*+I*-}[,]

Operands

:s dma :s 15 (TMS3201 0/C1 0/11 )

o :s dma :s 127 (TMS320C15/C17)

ARP

or 1

Execution

(PC) + 1 ..... PC
(status register) ..... specified dma (page 1 only in direct addressing)

Encoding

15 14

Direct:

I°

° °I °

54321
Data Memory Address

Indirect: 1'--0_ _ _ _ _ _ _ _ _ _ _
0 __0-L.,1_-'-_ _ _s_e_e_s_ec_t_io_n_4_.1_ _ _--'

Description

The status bits are saved into the specified data memory address (page 1
only if direct memory addressing is used).
In the direct addressing mode, the status register is always stored in page

1 regardless of the value of the DP register. The processor automatically
forces the page to be 1 i and the specific location within that page is defined
in the instruction. Note that the DP register is not physically modified. This
allows storage of the DP register in the data memory on interrupts, etc., in
the direct addressing mode with~ut having to change the DP. In the indirect addressing mode, the data memory address is obtained from the auxiliary register selected. (See the LST instruction for more information.)
The SST instruction can be used to store the status bits after interrupts and
subroutine calls. These status bits include the OV (overflow flag) bit, OVM
(overflow mode) bit, INTM (interrupt mode) bit, ARP (auxiliary register
pointer) bit, and DP (data memory page pointer) bit. The status bits are
stored in the data memory word as follows:
15 14
13
12 11 10
I OVIOVMIINTM I

987

x1 lop° I

reserved

Words
Cycles
Example

SST
or
SST

(OP' = don't care)

OATl

* ,1

iIf current auxiliary register contains l .

Before Instruction

After Instruction

Status
Register

5EFEh

Status
Register

5EFEh,

Data
Memory
1

OAh

Data'
Memory

5EFEh

4-65

Subtract from Accumulator with Shift

SUB
Syntax

Direct: [] SUB [,]
Indirect: [] SUB {*I*+I*-}[,[,]]

Operands

0 S dma S 1 27
ARP = 0 or 1
o S shift S 15 (defaults to O)

Execution

(PC) + 1 -+ PC
(ACC) - [(dma) x 2shift] -+ ACC
Affects OV; affected by OVM.

Encoding

15 14

12
1

Direct:

Indirect:

Shift
Shift

I oI
I 1I

Data Me1l'ory Address

See Section 4.1

Description

The contents of the addressed data memory location are left-shifted and
subtracted from the accumulator. During shifting, the low-order bits are
zero-filled. The high-order bit is sign-extended. The result is stored in the
accumulator.

Words

Cycles

Example

SUB

DAT59

i(DP = 0)

iIf current auxiliary register contains 59.

or
SUB

Before Instruction

4-66

After Instruction

ACC

24h

ACC

13h

Data
Memory
59

11 h

Data
Memory
59

11 h

Conditional Subtract

SUBC

Syntax
Direct [] SUBC
Indirect: [] SUBC {*I*+I*-}[,]

Operands

Os dma S 127
ARP

Execution

Encoding

= 0 or 1

(PC) + 1 -+ PC
(ACC) - [(dma) x 2 15] -+ ALU output
If ALU output ~ 0:
Then (ALU output) x 2 + 1 -+ ACC;
Else (ACC) x 2 -+ ACC.
Affects OV but NOT affected by OVM (no saturation).
15 14

Direct I 0 0

9
0

010

54321
Data Memory Address

Indirect 1L....;.o_ _ _ _ _o~.-;.0_ _ _..;..0_...;0....L.I_ _'__ _ _s;...e__e...;.s_e__
ct_io_n_4_.1_ _ _--I

Description

The SUBC instruction performs conditional subtraction, which may be used
for division. The 16-bit dividend is placed in the low accumulator, and the
high accumulator is zeroed. The divisor is in data memory. SUBC is executed 16 times for 16-bit division. After completion of the last SUBC, the
quotient of the division is in the lower-order 16-bit field of the accumulator,
and the remainder is in the high-order 16 bits of the accumulator. SUBC
assumes the divisor and the dividend are both positive.
If the 16-bit dividend contains less than 16 significant bits, the dividend
may be placed in the accumulator left-shifted by the number of leading
non-significant zeroes. The number of executions of SUBC is reduced from
16 by that number. However, at least one leading zero must always be
present since both operands of the SUBC instruction must be positive.
Note that the next instruction after SUBC cannot use the accumulator.
The SUBC instruction affects OV but is not affected by OVM. Therefore, the
accumulator does not saturate upon positive or negative overflows when
executing this instruction.
The above description is for 16-bit integer division. SUBC can also be used
in fixed-point division.

Words
Cycles

4-67

Conditional Subtract

SUBC
Example
DIV

LARP
LARK
SUBC
BANZ

ARO
ARO,15
DAT2
DIV

; (DP

Before Instruction

Alter Instruction

Data
Memory
2

Data
Memory

ACC

41h

ACC

20009h

The results above show the execution of all the instructions in the code
example.

4-68

SUBH

Subtract from High Accumulator

Syntax
Direct: [] SUBH
Indirect: [] SUBH {*I*+I*-}[,]

Operands

Os dma S 127
ARP = 0 or 1

Execution

(PC) + 1 ..... PC
(ACC) - [(dma) x 2 16] ..... ACC
Affects OV; affected by OVM.

Encoding
Direct:

15 14

Indirect L._0_ _ _ _ _0__0__0_ _ _ _"'-----'-_ _ _ _ _ _ _ _ _ _- - '

Description

The contents of the addressed data memory location are subtracted from the
upper 16 bits of the accumulator. The 16 low-order bits of the accumulator
are unaffected. The result is stored in the accumulator.
The SUBH instruction can be used for performing 32-bit arithmetic.

Words
Cycles
Example

SUBH

DAT33

iIf current auxiliary register contains 33.

or
SUBH

(DP = 0)

After Instruction

Before Instruction
Data
Memory
33
ACC

OA0013h

Data
Memory
33
ACC

60013h

4-69

Subtract from Low Accumulator
with Sign-Extension Suppressed

SUBS

Syntax
Direct: «label>] SUBS
Indirect: '«label>] SUBS {*I*+I*r}(,]

Operands

o :s dma :s 127
ARR = 0 or 1

Exacution

Encoding
Direct:

(PC) + 1 ~ PC
(ACC) - (dma) -+ ACC
Affects OV; affected by OVM.
1 5 14

I°

543

Data Memory Address

Indirect: 1_o
... _____o
____o__o____-'-----'____S_e_e_S_e_ct_io_n_4_.1_ _ _--'

Dascription

The contents of the addressed data memory location are subtracted from the
accumulator with sign-extension suppressed. The data is treated as a 16bit unsigned number, rather than a two's-complement number. The accumulator behaves as a signed number.

Words
Cyclas

Example

SUBS

DAT2

; (DP = 0)

;If current auxiliary register contains 2.

or
SUBS

Before Instruction
Data
Memory
2

OFOO3h

After Instruction
Data
Memory

Before Instruction
ACe

4-70

OF105h

OFOO3h

After Instruction
Ace

102h

Table Read

TBLR

Syntax
Direct: [] TBLR
Indirect: [] TBLR {*I*+I*-}[,]

Operands

o S dma S 127
ARP = 0 or 1

Execution

(PC) + 1 .... TOS
(ACC(11-0» .... PC
(pma) .... dma
Modify AR(ARP) and ARP as specified
(TOS) .... PC

Encoding

15 14

I0
0
0
0
Data Memory Address
I
Indirect: I 0
o 0
See Section 4.1
~------------------------~--~--------------------~
Direct:

Description

The TBLR instruction transfers a word from a location in program memory
to a data memory location specified by the instruction. The program memory address is defined by the low-order 12 bits of the accumulator. For this
operation, a read from program memory is performed, followed by a write
to data memory. The contents of the lowest stack location are lost when
using TBLW.
The TBLR instruction is useful for reading coefficients that have have beer
stored in program ROM, or time-dependent data stored in RAM.

Words

Cycles

Example

TBLR
or
TBLR

DAT6

iIf

(DP = 0)
current auxiliary register contains 6.

Before Instruction
ACC

After Instruction
ACC

Program
Memory
9

306h

Program
Memory
9

306h

Data
Memory
6

75h

Data
Memory
6

306h

Stack
')

71h
4sh
16h
SOh

Stack

71 h
4sh
16h
16h

4-71

TBLW

Table Write

Syntax
~

Direct: [] TBLW
Indirect: [] TBLW {*I*+I*-}[,]

Operands

o :s dma :s 127
ARP = 0 or 1

Execution

(PC) + 1 -+ TOS
(ACC(11-0» -+ PC
(dma) -+ pma
Modify AR(ARP) and ARP as specified
(TOS) -+ PC

Encoding
15 14 13
Direct:

I°

Data Memory Address

Indirect: 1
...._O_ _ _ _ _ _ _ _ _ _ _O_ _.L1_1---'_ _ _ _s;...e_e...;s_e;...ct_io-:'n_4_.1_ _ _--'
,

Description

The TBLW instruction transfers a word in data memory to program memory.
The data memory address is specified by the instruction, and the program
memory address is specified by the lower 12 bits of the accumulator. A read
from data memory is followed by a write to program memory to complete
the instruction. The contents of the lowest stack location are lost when
using TBLW.
Note that the TBLW and OUT instructions use the same external signals and
thus cannot be distinguished when writing to program memory addresses
o through 7.

Words

Cycles

Example

TBLW
or
TBLW

DAT5

; (DP = 0)

;If current auxiliary register contains 5.
Before Instruction

Data
Memory
5

4339h

Data
Memory
5

4339h

Program
Memory
8

306h

Program
'Memory
8

4339h

ACC

Stack

4-72

After Instruction

8h
.34h
23h
11h
97h

ACC

Stack

8h
34h
23h
11 h
11 h

Exclusive-OR with Low Accumulator

XOR

Syntax
Direct: [] XOR
Indirect: [] XOR {*I*+I*-}[,]

Operands

o :S dma :S 127
ARP = 0 or 1

Execution

(PC) + 1 ~ PC
(ACC(15-0».XOR.dma ~ ACC(15-0)
(ACC(31-16» ~ ACC(31-16)

Encoding

1 5 14

543

Data Memory Address
I0
0
0
oI0 I
I
Indirect: 1_o
.... ________o
__0_ _0.....l...1_1--1.1_ _ _ _s_ee_s_e_c_tio_n_4_._1_ _---'

Direct:

Description

The low half of the accumulator is exclusive-ORed with the contents of the
addressed data memory location. The upper half of the accumulator is not
affected by this instruction.
The XOR instruction is useful for toggling or setting bits of a word for
high-speed control. In addition, the one's complement of a word can be
found by exclusive-ORing it with all ones.

Words
Cycles
Example

XOR
or
XOR

DAT127

; (DP = 0)

iIf

current auxiliary register contains 127.

Before Instruction
Data
Memory
127
ACC

OFOFOh

12345678h

After Instruction
Data
Memory
127
ACC

OFOFOh

1234A688h

4-73

ZAC

Zero Accumulator

Syntax

[] ZAC

Operands

None

Execution

(PC) + 1 -+ PC
0-+ ACC

Encoding

15 14 13 12

10
Description

000

The contents of the accumulator are replaced with zero.

Words
Cycles
Example

ZAC

Before Instruction
ACC

4-74

IOA5A5A5A5h

After Instruction
ACC

0011

Zero Low Accumulator
and Load High Accumulator

ZALH

Syntax
Direct: [
Indirect: [] ZALH {*I*+I*-}[,]
Operands
Execution

Os dma S 127
ARP = 0 or 1
(PC) + 1 .... PC

o .... ACC(15-0)
(dma) .... ACC(31-16)

Encoding

15 14

Direct:!

876

!° !

543

Data Memory Address

Indirect: L..!_O_ _ _ _ _
O__O_ _ _ _
O_ _.....
!_'--L____
s_ee_s_e_ct_io_n_4_._' _ _---oJ
Description

. ZALH loads a data memory value into the high-order half of the accumulator. The low-order bits of the accumulator are zeroed.
ZALH is useful for 32-bit arithmetic operations.

Words
Cycles

Example

ZALH
or
ZALH

DAT3

; (DP = 0)

;If current auxiliary register contains 3.

Before Instruction
Data
Memory

ACC

3F01h

77FFFFh

After Instruction
Data
Memory

ACC

3F01h

3F010000h

4-75

Zero Accumulator, Load Low Accumulator
with.Sign-Extension Suppressed

ZALS

Syntax
Direct: [] ZALS
Indirect: [] ZALS {*I*+I*-}[,J

Operands
Execution

0 :s dma S 127
ARP = 0 or 1

(PC) + 1
(dma)

Encoding

ACC(15-0)

15 14 13

Direct:

Indirect:

Description

o -+ ACC(31-16)
12
,

01 0

Data Memory Address

See Section 4.1

The contents of the addressed d~ta· memory location are loaded into the 16
low-order bits of the accumulator. The upper half of the accumulator is
zeroed. The data is t(eated as a 16-bit unsigned number rather than a
two's-complement number. Therefore, there is no sign-extension with this
instruction.
ZALS is useful for 32-bit arithmetic operations.

Words

Cycles
Example

ZALS
or
ZALS

DATl

; (DP

;If current auxiliary

0)
r~gister

Before Instruction
Data
Memory
1
ACC

4-76

OF7FFh

7FF00033h

contains 1.

After Instruction
Data
Memory
1

OF7FFh

Ace

OF7FFh

Section 5

Software Applications

The use of various key software-related processor and instruction set features
along with assembly language coding examples is explained in this section.
TMS320C1 x (first-generation TMS320) instructions are tailored to digital
signal processing tasks, providing a single-cycle multiply, scaling, convolution, overflow management, and many other features. There is also instruction set support for logical and arithmetic operations.
More information about specific applications can be found in the book, Digital
Signal Processing Applications with the TMS320 Family (literature number
SPRA012A). The DSP Software Library contains the major DSP routines and
application algorithms presented in the applications book. The TMS320 DSP
Bulletin Board Service provides access to code updates and new application
reports as they become available. See Appendix E for information about the
software library and bulletin board.
Major topics discussed in this section are listed below and on the next page.
•

Processor Initialization (Section 5.1 on page 5-3)

•

Interrupt Management (Section 5.2 on page 5-7)
Interrupt service routines
810 polling
Context switching

•

Program Control (Section 5.3 on page 5-16)
Software stack expansion
Subroutine calls
Addressing and loop control with auxiliary registers
Computed GOTOs

•

Memory Management (Section 5.4 on page 5-23)
Moving data
Moving constants into data memory

•

Logical and Arithmetic Operations (Section 5.5 on page 5-29)
Bit manipulation
Overflow management
Scaling
Convolution operations
Multiplication; division, and addition
Floating-point arithmetic

5-1

Software Applications

•

5-2

Application-Oriented Operations (Section 5.6 on page 5-42)
Companding
FIR/IIR filtering
Adaptive filtering
Fast Fourier Transforms (FFT)
PIO control
Selftest routines.

Software Applications - Processor Initialization

5.1 Processor Initialization
Prior to the execution of a digital signal processing algorithm, it is necessary
to initialize the processor. Generally, initialization takes place anytime the
processor is reset.
When reset is activated by applying a low level to the RS (reset) input for a
minimum of five cycles, the TMS320C1 x terminates program execution and
forces the program counter (PC) to zero. Program memory location 0 normally contains a B (branch) instruction in order to direct program execution
to the system initialization routine following the reset. The hardware reset also
initializes various registers and status bits.
After reset, the processor should be initialized through software. The initialization routine should set up operational modes, memory pointers, interrupts,
and the remaining functions necessary to meet system requirements. This
section describes how to configure the TMS320C1 x devices after reset and
provides code for processor initialization.

5.1.1 TMS3201 O/C1 O/C15/E15 Initialization
To configure the TMS3201 O/C1 O/C15/E15 processor after reset, the following internal functions should be initialized:
•
•
•
•

Interrupt structure
Overflow mode control (OVM)
Auxiliary registers and auxiliary register pointer (ARP)
Data memory page pointer (OP).

Note that the OVM (overflow mode) bit, INTM (interrupt mode) bit, auxiliary
register pointer (ARP), and data memory page pointer {OP} are not initialized
by reset.
Example 5-1 shows coding for initializing the TMS3201 O/C1 O/C15/E15 to
the following machine state, in addition to the initialization performed during
the hardware reset:
•
•
•
•
•

Interrupt enabled
Overflow mode {OVM} disabled
Data memory page pointer (OP) set to zero
Auxiliary register pointer (ARP) set to zero
Internal memory filled with zeros.

5-3

Software Applications - Processor Initialization

Example 5-1. TMS32010/C10/C15/E15 Prpcessor Initialitati.on
.title
.deif

.ref

...

*
*

'PROC~SSOR

INI'rIALIZATION'

RESET,INT
ISR

PROCESSOR INITIALIZATION.
RESET AND INTERRUPT VECTOR SPECIFI<:;ATION,

.text
RESET· B
INIT
INT
B
ISR

**
*
*
*
**

THE BRANCH INSTRUCTION AT PRQGRAM MEMORY LOCATION 0 DIRECTS
EXECUTION TO BEGIN HERE FOR RESET PROCESSING THAT INITIALIZES THE PROCESSOR. WHEN RESET IS APPLIED, THE FOLLOWING
CONDITIONS AR~ ESTABLISHED FOR THE STATUS REGISTE~:

* ST:
*INIT

LOOP

5~1.2

OVOVM INTM 12 11 10 9 ARP 7 6 5 4 3 2 DP
Q X
1
1 1 1 1 X 1 1 1 1 1 1 X
ROVM
LDPK 0
LARK 0,255

DISABLE OVERFLOW MODE
POINT DP TO DATA PAGE 0
SET LOOP COUNT FOR DATA MEM INIT TO
143 FOR 32010 AND 255 FOR 320C15/17

INTERNAL DATA MEMORY INITIALIZATION.

**
*

; RS BEGINS PROCESSING HERE
; INT BEGINS PROCESSING HERE

ZAC
LARP 0
SACL *
BANZ LOOP

CLEAR THE ACCUMULATOR
USE AROFOR POINTER AND LOOP CONTROL
CLEAR DATA MEMORY
CHECK IF DONE AND DECREMENTARO

THE PROCESSOR IS INITIALIZED. THE REMAINING APPLICATIONDEPENDENT PART OF THE SYSTEM SHOULD NOW BE INITIALIZED.
EINT

; ENABLE ALL INTERRUPTS

TMS320C17E17 Initialization
To configure the TMS320C17lE17 after reset, the following internal functions
must be initialized:
•
•
•
•
•
•
•
•

Interrupt structure
Serial-port framing-pulse generation selection
Serial-port connection
Companding hardware
Serial-port clock
Auxiliary register pointer
Data memory page pointer
Overflow mode.

Two of the I/O ports are dedicated to the serial port and companding hardware, the operation of which is determined by the 32 bits of the system control
register. Table 5-1. lists the control register bits with brief definitions.
5-4

Software Applications - Processor Initialization

Table 5-1. Control Register Bit Definitions
CR BIT#

DEFINITION
PORTO

CR3 - CRO
CR7 - CR4
CRS
CR9
CR10
CR11
CR13 - CR12
CR14
CR15

Interrupt flags
Interrupt mask bits
Port 1 configuration control
External framing enable for serial port transfers
XF external logic output flag latch
Serial port companding mode select
Companding hardware enable
A-Iaw/IJ-Iaw conversion select
Serial clock (SCLK) control

CR23 - CR16
CR27 - CR24
CR2S
CR30 - CR29
CR31

Frame counter modulus
Serial clock (SCLK) prescale control (divide ratios)
FR pulse-width control
I/O control
Reserved for future expansion (set to 0)

PORT 1

Example 5-2 shows coding for initializing the TMS320C17/E17 serial-port
and companding hardware for interface to a codec. The following machine
state is loaded:
•

Set the lower control register bit 8 (CR8) to enable port 1 to access the
upper control register. To insure safe system operation, SCLK should
be left as an input to the device (CR15 set to logic 1). This prevents any
invalid serial-port timing during the initialization routine. The value
loaded into the lower control register to accomplish this is OB988h.

•

The upper control register is set as follows:
Long FR pulse (variable data-rate selected)
SCLK divide ratio of 10
FR frequency at SCLK/256 for an 8-kHz framing pulse
The value 7CFEh loaded into the upper control register.
Note that the data operand of the upper control register is set at 7CFEh.
This selects two's-complement companding for the serial port and 16-bit
length coprocessor mode (Le., for interface to 16-bit processors). When
two's-complement companding is used, there must be at least one instruction between an OUT instruction to the serial port transmit register
and an IN instruction from the serial port receive register.

•

The lower control register is then configured as follows:
Interrupt flags cleared
Active FR inteRVPt enabled. (The FR interrupt flag will be generated independent of the enable condition to the serial port.)
Port transfers enabled by active FR
Serial companding mode selected (see Section 5.6.1)
Companding hardware enabled
IJ-Iaw conversion selected
SCLK selected as an output
The value 3888h now loaded into the lower control register.
5-5

Software Applications - Processor Initialization

Note that the interrupt flags are flip-flops. Writing a one to an interrupt
flag clears it and sets the corresponding flag to zero; Le., a write to the
flags affects the clear or reset input of the flip":flops.

Example 5-2. TMS320C17/E17 Processor Initialization

*
*
*
*
*
*
*
*

A BRANCH INSTRUCTION AT PROGRAM MEMORY LOCATION 0 DIRECTS
PROCESSOR EXECUTION HERE.
THE CONTROL REGISTER VALUES ARE
STORED IN ROM STARTING AT LOCATION 4. THESE VALUES ARE
THEN READ INTO RAM FOR THE OUT INSTRUCTIONS TO THE CONTROL
REGISTER. MEMORY LOCATIONS SET1-SET3 AND ONE ARE LOCATED
ON RAM PAGE 1. THE PROGRAM MEMORY LOCATION HAS A BRANCH TO
THE INTERRUPT SERVICE ROUTINE.

ONE
SET1
SET2
SET3

**
*
*

INIT

**
*
*
*

5-6

RESET,INT,INIT
ISR

.set
.set
. S'et
.set

1
2
3
4

CONSTANT ONE
LOWER CONTROL REGISTER
UPPER CONTROL REGISTER
LOWER CONTROL REGISTER

PROCESSOR INITIALIZATION.
RESET AND INTERRUPT VECTOR SPECIFICATION.

RESET
INT
TABLE

.def
.ref

.text
B
B
.word
.word
.word
DINT
SOVM
LARP
LDPK
LACK
SACL
LACK
TBLR
ADD
TBLR
ADD
TBLR
OUT
OUT
OUT
LDPK

INIT
ISR
OB988h
7CFEh
3888h

0
1
1
ONE
TABLE
SET1
ONE,O
SET2
ONE,O
SET3
SET1,O
SET2,1
SET3,O
0

RS BEGINS PROCESSING HERE
INT BEGINS PROCESSING HERE
CONTROL REGISTER DATA

DISABLE INTERRUPTS
SET OVERFLOW MODE
USE AUXILIARY REGISTER 0
WORK IN RAM PAGE 1
ACC = 1
STORE 1 IN MEMORY LOCATION ONE
START AT LOCATION 4
READ VALUE OB988h TO RAM
INCREMENT ADDRESS
READ VALUE 1CFEh TO RAM
INCREMENT ADDRESS
READ VALUE 3888h TO RAM
CONFIGURE LOWER CONTROL REGISTER
CONFIGURE UPPER CONTROL REGISTER
CONFIGURE LOWER CONTROL REGISTER
RESET RAM 'PAGE TO

THE PROCESSOR IS INITIALIZED. THE REST OF THE SYSTEM THAT
IS APPLICATION-DEPENDENT SHOULD BE INITIALIZED BEFORE THE
EINT INSTRUCTION.
EINT

; ENABLE INTERRUPTS.

Software Applications - Interrupt Management

5.2 Interrupt Management
The interrupt function allows thtt current process to be suspended in order to
perform a more critical function. On the TMS3201 O/C1 O/C15/E15, processor
execution may be suspended on a high-priority basis by using the INT pin.
Otherwise, a lower priority interrupt can be serviced by using a software
(BiO) polling technique.
The TMS320C17 IE17 has four interrupts maskable via the system control register. These interrupts are synchronized and multiplexed into the master interrupt circuitry and have the same priority. Software polling techniques are
used to determine which input caused the interrupt when multiple interrupts
are enabled.
Processing in the interrupt service routine (ISR) must assure that the processor context is saved before and during execution and restored when the routine is finished. Descriptions and examples of how to implement interrupt
service routines, 810 polling, and context switching are provided in this section.

5.2.1 TMS32010/C10/C15/E15 Interrupt Service

R~utines

The TMS3201 O/C1 0 and TMS320C15/E15 devices provide one maskable
interrupt (INT). By using the INT pin, the processor's execution can be suspended at any point in the program except after a mUltiply instruction. The
instruction following the MPY and MPYK instructions is always executed.
Interrupt processing on the TMS3201 O/C1 O/C15/E15 begins as follows:
1)
2)

The EINT (enable interrupt) instruction is executed, which sets the
INTM (interrupt mode) bit to 0 so that an interrupt can be received.
When an interrupt occurs, the INTF (interrupt flag) bit is set to 1.

As interrupt servicing begins, the following sequence occurs automatically:
1)
2)
3)
4)

The interrupt is acknowledged, which clears the INTF (interrupt flag)
bit to O.
The INTM (interrupt mode) bit is set to.1 to disable further interrupts.
The current PC is pushed onto TOS (top of stack).
The new PC is set to 2.

During servicing of the interrupt, the following operations are commonly performed by the user in software:
1)
2)

3)
4)

Program memory address 2 will either have a service routine to save the
context of the machine or a branch to the interrupt service routine.
The interrupt service routine is executed. The context of the machine
can be saved and the source of the interrupt serviced. Then, the context
is restored and the interrupts enabled prior to returning from the interrupt
routine.
The EINT (enable interrupt) instruction is executed, which sets the
INTM (interrupt mode) bit to O.
The RET inljtruction is executed.

The hardware interrupt can be masked at critical points in the program with
the DINT instruction. This sets the INTM (disable interrupt mode) bit to logic
\

5-7

Software Applications - Interrupt Management

one. If an interrupt occurs while INTM equals one, the interrupt will not be
serviced until the interrupts are enabled again. However, the INTF (interrupt
flag) is set to one, and the interrupt is held pe)lding. The interrupt will be
serviced when the INTM bit is set to zero by executing the EINT instruction.
If an interrupt is pending when an enable interrupt operation occurs, the interrupt is serviced after the execution of the instruction following the EINT
instruction. This allows for a return instruction to be executed before an interrupt is acknowledged.
An interrupt-driven analog input channel can be implemented using the technique described and shown in Example 5-3. However, multiple-level data
buffering will impact system 1/0 overhead. Analog systems supported by
first-generation TMS320 devices usually have information bandwidths of less
than 20 kHz. The desired sample rate can be generated by dividing the
CLKOUT signal from the TMS320. It 'is advisable to provide at least a onelevel data buffer to ensure the integrity of the data read by the processor. If
an 8-kHz sample rate is used (for example), the system must then respond to
an analog interrupt every 125 IlS. The percentage of 1/0 overhead incurred
by this arrangement can be computed by determining the number of clock
cycles that the TMS320 will spend in the interrupt rou!tine seniicing each
sample and dividing by the number of clock cycles available between each
sample. Example 5-3 shows a typical interrupt service routine. Note that the
memory location flag (FLAG) contains a 1-bit flag to indicate that the required
number of samples have been received.

5-8

Software Applications - Interrupt Management

Example 5-3. TMS32010/C10/C15/E15 Interrupt Service Routine

* THIS ROUTINE SERVICES AN EXTERNAL INTERRUPT. IT MAY BE
* LOCATED AT PROGRAM MEMORY LOCATION 2, OR A BRANCH AT

*
*
*
*
*
*

*
*

LOCATION 2 DIRECTS PROGRAM EXECUTION HERE. THE ROUTINE
READS DATA FROM AN EXTERNAL DEVICE (A/D CONVERTER). THE
NUMBER OF SAMPLES OBTAINED ARE STORED IN MEMORY LOCATION
COUNT. LIMIT IS THE NUMBER OF SAMPLES NEEDED. MEMORY
LOCATION ONE CONTAINS THE CONSTANT 1. STATUS IS ALWAYS
STORED ON DATA PAGE 1 WHEN USING DIRECT MEMORY ADDRESSING.
ASSUME ARO POINTS TO THE NEXT EMPTY LOCATION IN THE SAMPLE
BUFFER.

ADC
STATUS
ACCL
ACCH
SAMP
COUNT
FLAG
LIMIT·

*
ISR

DONE
OK

.set
.set
.set
.set
.set
.set
.set
.set

0
0
1
2
3
4
5
32

.text
SST STATUS
LDPK 1
SACL ACCL
SACH ACCH
LARP 0
IN
*- ,ADC
LAC
COUNT
ADD ONE
SACL COUNT
LACK LIMIT
SUB
COUNT
BGZ
OK
LACK 1
SACL FLAG
ZALH ACCH
ADDS ACCL
LST STATUS
EINT
RET

ASSIGN PAO TO A/D CONVERTER
STATUS REGISTER STORAGE ON PAGE 1
ASSIGN MEM LOCATION TO SAVE STATUS/ACC
STORE INPUT DATA HERE
COUNT # OF SAMPLES HERE
ASSIGN MEM LOCATION TO FLAG
ASSIGN TOTAL # OF SAMPLES REQUIRED
SAVE STATUS
USE DATA PAGE 1
SAVE ACCUMULATOR LOW
SAVE ACCUMULATOR HIGH
USE ARO
READ FROM ADC
LOAD SAMPLE COUNTER
INCREMENT
STORE UPDATED COUNT
CHECK IF LIMIT EXCEEDED
YES --> SET FLAG
RESTORE ACCUMULATOR HIGH
RESTORE ACCUMULATOR LOW
RESTORE STATUS
ENABLE SUBSEQUENT INTERRUPTS

If the processor is using a 20-MHz clock, the number of available cycles between each sample is 625. The overhead required to service this system is
18/625 = 2.9 percent. This overhead burden can be reduced by using a FIFO
{first in, first out} to buffer the data. In this case, the TMS320 need only be
interrupted when the buffer has filled. If a 16-level FI FO is used in the example
above, this interrupt will occur every 2 ms, and the overhead burden will be
reduced to about 0.5 percent.
If two different kinds of devices are being serviced by the same interrupt routine, the 810 pin can be used to determin'e which device needs to be serviced
(see Section 5.2.3 for 810 poning).

5-9

Software Applications -Interrupt Management

5.2.2 TMS320C17/E17 Interrupt Service Routines
The TMS320C17/E17 has four maskable interrupts: EXINT, FSR, FSX, and FR.
The interrupts are maskable via the system control register bits CR7-CR4. Bits
CR3-CRO serve as the interrupt flags for the four interrupts. An active signal
on any of these pins sets the corresponding interrupt flag to one. Since all four
interrupts activate a single master interrupt flag, the interrupt service routine
(ISR) should poll all four interrupt flags and check for the corresponding interrupt source. The ISR may also need to poll the individual mask bits
(CR7-CR4) before recognizing the interrupt flag.
Interrupt processing on the TMS320C17 /E17 begins as follows:
1)
2)

As interrupt servicing begins, the following sequence occurs automatically:

2)
3)
4)

The interrupt is acknowledged, which clears the INTF (interrupt flag)
bit to O.
The INTM (interrupt mode) bit is set to 1 to disable further interrupts.
The current PC is pushed onto TOS (top of stack).
The new PC is set to 2.

During servicing of the interrupt, the following operations are comn;lonly performed by the user in software:
1)
2)

Program memory address 2 will either have a service routine to save the
context of the machine or a branch to the interrupt service routine.
The interrupt service routine is executed. The context of the machine
may be saved and restored later if required. The following can be used
to select which interrupt to service:
a)
Use software polling >techniques to determine which one of the
four flags has been set in the control register.
b)
Check for corresponding mask bits before proceeding (optional).
c)
Clear that flag (reset by writing a 1) and service the source of that
flag. There must be an interval of at least four clock cycles after the
flag has been set before clearing it. On the EXINT flag, the interrupt
source must have been taken away for four cycles before the interrupt flag can be cleared.

All interrupts are synchronized and multiplexed into the master interrupt circuitry and have the same priority. However, interrupt priorities in polling the
interrupt flags can be established by the user. The ISR should clear the interrupt flag before executing an EINT instruction or enabling the interrupts. Note
that writing a one to an interrupt flag will clear it, i.e., set the corresponding
flag to zero. If the interrupt condition persists when an attempt is made to clear
the flag, that interropt flag will remain set. This condition is only applicable to
EXINT or its equivalent in coprocessor port mode. In the coprocessor mode
on the TMS320C17 /E17, the 810 and EXINT lines cannot be driven externally,
but are reserved for transfers to/from the coprocessor port. An example interrupt service routine for a system with three active interrupts enabled is given
in Example 5-4. Polling is also included in the code example.
5-10

Software Applications - Interrupt Management

Example 5-4. TMS320C17/E17 Interrupt Service Routine

THIS ROUTINE MAY BE LOCATED AT PROGRAM MEMORY LOCATION 2,

*
*

EXECUTION HERE. MEMORY LOCATION ONE CONTAINS THE
CONSTANT 1. STATUS IS ALWAYS STORED ON DATA PAGE 1 WHEN
DIRECT MEMORY ADDRESSING IS USED.

* OR A BRANCH INSTRUCTION AT LOCATION 2 DIRECTS PROGRAM

*
**
*
*

RECV IS THE SERVICE ROUTINE FOR THE RECEIVE INTERRUPT.
XINT IS THE SERVICE ROUTINE FOR THE EXTERNAL INTERRUPT.
TRANS IS THE SERVICE ROUTINE FOR THE TRANSMIT INTERRUPT.

.def ISR,RECV,XINT
.ref TRANS

STATUS
ACCL
ACCH
RBUF
CREG

*
ISR

.set
.set
.set
.set
.set

o
1

2
3
4

.text
SST STATUS
LDPK 1
SACL ACCL
SACH ACCH

ASSIGN MEM LOCATION TO SAVE STATUS/ACC
STORE RECEIVE DATA HERE
TEMP LOCATION TO STORE CONTROL REG
SAVE STATUS
USE DATA PAGE 1
SAVE LOW ACCUMULATOR
SAVE HIGH ACCUMULATOR

THIS ROUTINE CHECKS FOR THREE ACTIVE INTERRUPTS OCCURRING

* AND SERVICES THEM ACCORDINGLY. IT IS ASSUMED THAT ONE OF
* THREE IS THE SOURCE OF THE INTERRUPT. AFTER AN INTERRUPT
* FLAG IS SET, IT MUST BE RESET BY THE INTERRUPT SERVICE

*
*
*

ROUTINE TO AVOID BEING INTERRUPTED AGAIN ON THE RETURN
FROM THE SUBROUTINE.
IN
LAC
AND
BNZ
LAC
AND
BNZ

READ LOWER CONTROL REGISTER
LOAD INT INTERRUPT MASK
INT FLAG SET?
GO TO INT SERVICE ROUTINE
LOAD FSX INTERRUPT MASK
FSX FLAG SET?
GO TO TRANSMIT SERVICE ROUTINE

INTERRUPT MUST BE FSR.

*
RECV

CREG,PAO
ONE,O .
CREG
XINT
ONE,2
CREG
TRANS

LACK
OR
SACL
LACK
XOR
SACL
IN

OFh
CREG
CREG
OBh
CREG
CREG
RBUF,PA1

SET ALL INTERRUPT FLAGS IN CREG
ZERO ALL INTERRUPT FLAGS EXCEPT FSR
READ REC DATA FROM PORT 1

RESTORE STATUS.

*
RESTOR

OUT
ZALH
ADDS
LST
EINT
RET

CREG,PAO
ACCH
ACCL
STATUS

RESTORE CNTL REG ~ CLEAR INTERRUl:"rs
RESTORE HIGH ACCUMULATOR
RESTORE LOW ACCUMULATOR
RESTORE STATUS
ENABLE INTERRUPTS

5-11

Software Applications - Interrupt Management

* INTERRUPT MUST BE COPROCESSOR EXINT.

XINT IN
LACK
OR
SACL
LACK
XOR
SACL
B

CPBUF,PA5
OFh
CREG
CREG
OEh
CREG
CREG
RESTOR

READ LATCH DATA FROM PORT 5
SET ALL INTERRUPT FLAGS. IN CREG
ZERO ALL INTERRUPT FLAGS EXCEPT EXINT
BRANCH TO RESTORE STATUS

5.2.3 810 Polling
A low priority interrupt can be serviced by usjng BiD polling. The BIOZ instruction can be used to poll (or test) the BiD pin to see if a device needs to
be serviced. This method allows a critical loop or set of instructions to be
executed without a variation in execution time. Because the test for the BIO
pin occurs at defined points in the program, context saves are minimal.
The BIO pin can be used to monitor the status of a peripheral. If the FIFO (first
in, first out) full status line is connected to the BIO pin, the FIFO is serviced
only when the FIFO is full. In the following code segment,. the FIFO contains
16 data words. The BIO pin is tested after each time-critical function has been
I
r
executed.

SKIP

BIOZ
CALL

SKIP
SERVE

The subroutine does not have to save the registers or the status, because a
new procedure will be executed after the device iS'serviced, as shown below.
SERVE
LOOP

LARK
LARK
LARP
IN
BANZ
RET

ARO,15
AR1,TABLE
1

*+,PAO,ARO
LOOP

The FIFO must be serviced before another word is input or data may be lost.
This fact determines the frequency at which the polling must take place.

5-12

Software Applications - Interrupt Management

5.2.4 Context Switching
Context switching, commonly required when processing a subroutine call or
interrupt, may be quite extensive or simple, depending on system requirements
such as the use made of the stack or auxiliary registers. Unless the interrupt
service routine (ISR) is a simple I/O handler, the processing in the ISR generally must assure that the processor context is preserved during execution.
The context must be saved before executing the routine itself and restored
when the routine is finished. A common routine may be used to secure the
context of the processor during interrupt processing.
The TMS320C1 x program counter is stored automatically on the hardware
stack. If there is any important information in the other TMS320C1 x registers,
such as the status or auxiliary registers, these must be saved by user software.
A stack in data memory, identified by an auxiliary register, is useful for storing
the machine state when processing interrupts.
During an interrupt, all registers except the P register can be saved and restored directly. However, the TMS320C1 x devices have hardware protection
against servicing an interrupt between an MPY or MPYK instruction and the
following instruction. For this reason, it is advisable to follow the MPY and
MPYK instructions with LTA, LTD, PAC, APAC, or SPAC instructions that
transfer data from the P register to the accumulator.
Examples of saving and restoring the state of the TMS320C1 x processor are
given in Example 5-5 and Example 5-6. Auxiliary register 1 (AR1) is used in
both examples as the stack pointer. As the stack grows, it expands into lower
memory addresses. The registers saved are the ST status register, accumulator
(ACC), P register, T register, all four levels of the hardware stack, and auxiliary
registers AROand AR1.
The routines in Example 5-5 and Example 5-6 are protected against interrupts,
allowing context switches to be nested. This is accomplished by the use of
the MAR *- and MAR *+ instructions at the beginning of the context save
and context restore routines, respectively. Note that the last instruction of the
context save decrements AR1 while the context restore is completed with an
additional increment of AR1. This prevents the loss of data if a context save
or restore routine is interrupted.

5-13

Software Applications - Interrupt Management

Example 5-5. Context Save
. title
.def·

'CONTEXT SAVE'
SAVE

.text
*
* CONTEXT SAVE ON SUBROUTINE CALL OR INTERRUPT. ASSUME THAT
* AR1 IS THE STACK POINTER AND AR1 = 128.
*
SAVE LARP AR1
AR1
128
; CHANGE POINTER TO AR1
AR1
MAR *127
*
* SAVE THE STATUS REGISTER.
*
SST *AR1
126
; ST
--> (127) ,
*
* SAVE THE ACCUMULATOR.
*
; ACCH --> (126),
AR1
125
SACH *SACL *; ACCL --> (125) ,
AR1
124
*
* SAVE THE P REGISTER.
*
* THE P REGISTER CANNOT BE EASILY RESTORED FROM~EMORY. ON
* TMS320C1X DEVICES, IT IS ASSUMED THAT THE MPY AND MPYK
* INSTRUCTIONS HAVE BEEN FOLLOWED BY AN APAC, PAC, SPAC,
* LTA, OR LTD INSTRUCTION. HENCE, SAVING THE ACCUMULATOR
* HAS ALSO SAVEtlTHE P REGISTER.
*
* SAVE THE T.REGISTER.
*
MPYK 1
T --> P
PAC
T --> ACC
SACL *T --> (124),
AR1 = 123
*
* SAVE ALL FOUR LEVELS OF THE HARDWARE STACK.
*
POP
TOS
--> ACC,
TOS (4) --> (123) ,
AR1
122
SACL *POP
STACK(3) --> ACC,
STACK(3) --> (122) ,
SACL *AR1
121
POP
STACK(2) --> ACC,
STACK(2) --> (121) ,
AR1
SACL *120
BOS ( 1) --> ACC,
POP
SACL *BOS (1) --> (120) ,
AR1 =; 119
*
* SAVE AUXILIARY REGISTERS.
*
AR1
SAR ARO,*- ; ARO --> (119),
118
SAR AR1,*- ; AR1 --> (118) ,
AR1
117
*
* SAVE IS COMPLETE.

5-14

Software Applications - Interrupt Management

Example 5-6. Context Restore
.title
.def
.text

'CONTEXT RESTORE'
RESTOR

* CONTEXT RESTORE AT THE END OF A SUBROUTINE OR INTERRUPT.
* ASSUME THAT AR1 IS THE STACK POINTER AND AR1 = 117.

RESTOR LARP AR1
MAR
*+

*
*

; CHANGE POINTER TO AR1, AR1
117
AR1 = 118

* RESTORE AUXILIARY REGISTERS.
LAR
LAR

AR1,*+
ARO,*+

; (118) --> AR1,
; (119) --> ARO,

AR1
ARO

119
120

* RESTORE ALL FOUR LEVELS OF THE HARDWARE STACK.

ZALS
PUSH
ZALS
PUSH
ZALS
PUSH
ZALS
PUSH

*+
*+
*+
*+

(120)
(120)
( 121)
( 121)
(122)
(122)
(123)
(123)

-->
-->
-->
-->
-->
-->
-->
-->

ACC,
(1) ,
BOS
ACC,
STACK(2) ,
ACC,
STACK(3),
ACC,
(4) ,
TOS

AR1

121

AR1

122

AR1

123

AR1

124

*
* RESTORE THE T REGISTER.
*
*+
; (124) --> T,
AR1
LT
*
* RESTORE THE ACCUMULATOR.
*
ZALS *+
AR1
; (125) --> ACCL,
ADDH *+
AR1
; (126) --> ACCH,
*
* RESTORE THE STATUS REGISTER.
*
*+
LST
AR1
; (127) -> ST,
*
* RESTORE IS COMPLETE.
*
EINT
; ENABLE INTERRUPTS
RET
; RETURN TO CALLING ROUTINE

125

126
127

128

5-15

Software Applications - Program Control

5.3 Program Control
To facilitate the use of the:TMS320C1 x in general-purpose high-speed processing, a variety of instructions are provided for softw~re stack expansion,
implementation of subroutine calls, addressing and loop control with auxiliary
registers, and external branch control. Descriptions and examples of how to
use these features are given in this section.

5.3.1 Software Stack Expansion
The TMS320C1 x has a 12-bit Program Counter (PC) and a four-level hardware stack for PC storage. Provisions have been made on the TMS320C1 x
for extending the hardware stack into data memory. This is useful for deep
subroutine nesting or stack overflow protection.
The hard~are stack is accessible via the accum'ulator using the PUSH and
POP instructions. The PUSH instruction pushes the 12 lSBs of the accumulator onto the top of stack (TOS). The POP instruction pops the TOS into \
the 12 lSBs of the accumulator. Following the POP instruction, the TOS can
be moved into data memory by storing the low-order accumulator word
(SACl instruction). This allows expansion of the stack into the d.ata RAM.
From data RAM, it can easily be copied into off-chip program RAM using the
TBlW instruction. In this way, the stack can be expanded to very large levels.'
When the stack has four values stored on it and one or more values are to be
put on the stack before any other values are popped off, a subroutine can be
used to perform software stack expansion. Such a routine is illustrated in Example 5-7. In this example, the main program stores the stack starting location in memory in the auxiliary register and indicates to the subroutine
whether to push data from memory onto the stack or pop data from the stack
to memory. If a zero is loaded, into the ,accumulator before calling the subroutine, the subroutine pushes data from memory to the stack. If a one is
loaded into the accumulator, the subroutine pops data from the stack to
memory.
A CAll instruction should be used to initiate execution of the software stack
expansion routine. Since the CAll instruction uses the stack to save thle
program counter, the subroutine pops this value into the accumulator and
saves it in a memory location. Then at the end of the subroutine, this value is
reloaded into the accumulator, and the main program is reentered using the
RET instruction. This prevents the calling routine program counter from being
stored into a memory location. The subroutine in Example 5- 7 uses the BANZ
(branch on auxiliary register not zero) instruction to control all of its loops.

5-16

Software Applications - Program Control

Example 5-7. Software Stack Expansion
* THIS ROUTINE EXPANDS THE STACK WHILE LETTING THE MAIN
* PROGRAM DETERMINE WHERE TO STORE THE STACK CONTENTS OR
* FROM WHERE TO RECOVER THEM.

LOCl

*
STACK

. set

.tex-e
LARK
LDPK
BNZ
POP
SACL

ARl,3
1
PO
LOCl

LOAD COUNTER
USE PAGE 1
IF POPD IS NEEDED, GOTO PO
LOAD PC INTO ACCUMULATOR
STORE PC AT MEM LOCATION LOCl

*
LARP
LAC *+,ARl
PUSH
BANZ P
LAC LOCl
PUSH
RET

USE ARO
LOAD ACCUMULATOR INTO MEMORY
PUT MEMORY ON STACK
BRANCH TO P UNTIL STACK IS FULL
LOAD PC INTO ACCUMULATOR
PUT RETURN ADDRESS ON STACK
RETURN TO MAIN PROGRAM

POP
SACL LOCl
LARP ARO
MAR *-

LOAD PC INTO ACCUMULATOR
SAVE PC INTO MEMORY
USE ARO
ALIGN STACK POINTER

LARP
POP
SACL
BANZ
MAR
LAC
PUSH
RET

USE ARO
PUT STACK IN ACCUMULATOR
STORE STACK IN MEMORY
BRANCH TO POl UNTIL SAVED
REALIGN STACK POINTER
LOAD ACCUMULATOR WITH PC
PUT RETURN ADDRESS ON STACK
RETURN TO MAIN PROGRAM

*
PO

POl

°*-,O,ARl
POl
*+
LOCl

5.3.2 Subroutine Calls
I

When a subroutine call is made using the CAll or CAlA instruction, the current contents of the program counter are stored on the top of the stack. At the
end of the subroutine, a RET (return from subroutine) instruction pops the top
of the stack to the program counter. The program then resumes execution at
.
the instruction following the subroutine call.
In two circumstances, a level of stack must be reserved for the machine's use.
First, the TBlR and TBlW instructions use one level of stack. Second, when
interrupts are enabled, the PC is saved on the stack during the interrupt routine. If a system is designed to use both interrupts and a TBlR or TBlW in~,/'uction, only two levels of stack are available for nesting subroutine calls.
Subroutine calls can be nested deeper than two levels if the return address is
removed from the stack and saved in data memory. The POP instruction
moves the top of stack (TOS) into the accumulator and pops the stack up one
level. The return address can then be stored in data memory until the end of
the subroutine when it is put back into the accumulator. The PUSH instruction
pushes the stack down one level and then moves the accumulator onto the
TOS. Therefore, when the RET instruction is executed, the PC is updated with
5-17

Software Applications - Program Control

the return address. This procedure allows a second subroutine to be called
inside the first subroutine without using another level of stack.
The POP and PUSH instructions can also be used to pass arguments to a
subroutine. The .word directives following the subroutine call can be used to
create a list of constants and/or variables to be passed to the subroutine. After
the subroutine is called, the TOS points to the list of arguments following the
CALL instruction. By moving the argument pointer from the TOS to the accumulator, the list of arguments can be read into data memory using the TBlR
instruction. Between each TBlR instruction, the accumulator must be incremented by one to point to the next argument in the list. To create the return
address, the argument pointer is incremented past the last element in the argument list. The PUSH instruction moves the return address onto the TOS,
and the RET instruction updates the PC. Example 5-8 illustrates a call that
passes two arguments to a subroutine.

Example 5-8. Two Arguments Passed to a Subroutine

*
**
*
*
*
*
*

CLEAR BITS
THIS ROUTINE CLEARS THE BITS OF A DATA WORD DESIGNATED BY
A MASK. THE BITS SET TO ONE IN THE MASK INDICATE THE' BITS
IN THE DATA WORD TO BE CLEARED. ALL OTHER BITS REMAIN
UNCHANGED. LOCATION ONE CONTAINS THE CONSTANT 1. MINUS
CONTAINS A MASK INVERTER, -lOR OFFFFh. TWO ARGUMENTS ARE
PASSED TO THIS SUBROUTINE. THE CALLING SEQUENCE IS AS
FOLLOWS:
'

*
*
*
*
*

1ST ARGUMENT = ADDRESS OF DATA WORD
2ND ARGUMENT = MASK

STATUS • set
XRO
. set
XR1
.set

0
126
127

STORE STATUS REGISTER HERE
TEMPORARY LOCATIONS

STATUS

SAVE STATUS
USE DATA PAGE 0
SAVE ARO IN TEMPORARY LOCATION

POP
TBLR
LAR
ADD
TBLR
ADD
PUSH

XR1
ARO,XR1
ONE
XR1
ONE

GET ADDRESS OF 1ST ARGUMENT IN ACC
STORE 1ST ARGUMENT IN TEMP LOCATION
PUT 1ST ARGUMENT INTO ARO
POINT TO 2ND ARGUMENT
2ND ARGUMENT = MASK
POINT TO RETURN ADDRESS
PUT RETURN ADDRESS ON TOS

LARP
LAC
XOR
AND
SACL

XR1
MINUS

CBITS

5-18

CALL CBITS
.word VALUE
.word 0081h

SST
LDPK
SAR

LAR
LDPK
LST
RET

ARO,XRO

ARO,XRO
1

STATUS

LOAD MASK INTO ACCUMULATOR
INVERT MASK
CLEAR BITS
STORE MODIFIED VALUE
RESTORE ARO
USE DATA PAGE 1
RESTORE STATUS REGISTER
RETURN TO MAIN PROGRAM

Software Applications - Program Control

Hardware stack allocation involves allocating the usage of the various stack
levels for interrupts, subroutine calls, pipelined instructions, and the emulator
(XDS). The TMS320C1 x disables all interrupts when taking an interrupt trap.
If interrupts are enabled more than one instruction before the return of the
interrupt service routine, the routine can also be interrupted; thus using another level of the hardware stack. This should be taken into consideration
when managing the use of the stack.
When nesting subroutine calls, each call uses a level of the stack. The number
of levels used by interrupts must be considered as well as the depth of the
nesting of subroutines. Two possible allocations of the hardware stack levels
are:
- 1 level reserved for interrupt service routines (ISR)
- 3 levels available for subroutine calls.
or: .
- 1 level reserved for interrupt service routines (ISR)
- 2 levels available for subroutine calls
- 1 level available for TBLR/TBLW instructions.

5.3.3 Addressing and Loop Control with Auxiliary Registers
The two auxiliary registers on the TMS320C1 x can be used either as pointers
for indirect addressing or as loop counters. In the indirect addressing mode,
the auxiliary register pointer (ARP) is used to determine which auxiliary register is selected. The LARP instruction sets the ARP equal to the value of the
immediate operand. The value of the ARP can also be changed in the indirect
addressing mode; the ARP is updated after the instruction has been executed.
The contents of the auxiliary register are interpreted as a data memory address
when the indirect addressing mode is used. A sequential list of data can easily
be accessed in the indirect mode by using the autoincrement/decrement feature of the auxiliary registers. The auxiliary register can also be used as a 9-bit
counter (see Section 3.4.5). The MAR (modify auxiliary register and pointer)
instruction allows the auxiliary register selected by the ARP to be incremented
or decremented without implementing any other operation in parallel.
Three instructions (LARK, LAR, and SAR) either load or store a value into an
auxiliary register, independent of the value of the ARP. The first operand in
each of these instructions determines which auxiliary register is to be either
loaded or stored. This operand does not affect the value of the ARP for subsequent instructions.
Example 5-9 illustrates using an auxiliary register in the indirect addressing
mode to input data into a block of memory.

5-19

Software Applications - Program Control

El!:ample 5-9. Auxiliary Register Indirect Addressing
* THIS ROUTINE USES AN AUXILIARY REGISTER 'IN THE INDIRECT
* ADDRESSING MODE TO INPUT DATA INTO A BLOCK OF MEMORY.
*
INIT ARO AS A POINTER TO DATBLK,
LARK ARO,DATBLK
(AREA OF 8 WORDS, IN DATA MEMORY)
*
SELECT ARO
LARP 0
LACK 8
INIT ACCUMULATOR AS A COUNTER
*
LOOP
IN
*+,PAO
INPUT DATA
SUB ONE
DECREMENT COUNTER (ONE
VALUE 1)
LOOP
REPEAT UNTIL'COUNT
0
B~Z

An auxiliary register can also be used as a loop counter. The BANZ instruction
tests and then decrements the auxiliary register selected by ARP. Because the
test for zero occurs before the auxiliary register is decremented, the value
loaded into the auxiliary register must be one less than the number of times the
loop should be executed. The maximum number of loops that can be counted
is 512, because only 9 bits of each auxiliary register are implemented as
counters. A routine that inputs data and calculates a sum while the auxiliary
register is used to count the number of loops is shown in EXample 5-10. The
'
accumulator contains the result.

Example 5-10. Auxiliary Register Loop Counting
* THIS ROUTINE USES AN AUXILIARY REGISTER TO COUNT THE.
* NUMBER OF LOOPS.

*
*
LOOP

5-20

LARK ARO,3
LARP 0
ZAC

INITIALIZE ~RO AS A COUNTER
SELECT ARO
CLEAR ACCUMULATOR

IN
I?ATA1,PA2
ADD DATAl
BANZ LOOP

INPUT DATA VALUE
ADD DATA TO ACCUMULATOR
REPEAT LOOP FOUR TIMES

Software Applications - Program Control

Both indirect addressing and loop counting can be performed at the same time
to implement loops efficiently. If the data block is defined to start at location
in data memory, the same auxiliary register that is counting the number of
loops can also be the pointer for indirect addressing, as shown below. Note
that data locations 0 through 7 are loaded with input data.

LOOP

LARK ARO,7
IN
*,PA2
BANZ LOOP

ARO POINTS TO END OF DATA BLOCK
INPUT DATA VALUE
REPEAT LOOP 8 TIMES

The data block does not have to start at zero if one auxiliary register is used
for counting and the other register is used as a pointer. Example 5-11 illustrates how both auxiliary registers can be used at once.
I

Example 5-11. Auxiliary Register Pointing and Loop Counting
* THIS ROUTINE USES ONE AUXILIARY REGISTER FOR POINTING AND
* THE OTHER REGISTER FOR LOOP COUNTING.

LARK ARO,7
LARK ARl,DATBLK

*
ZAC
*
LOOP

LARP 1
ADD *+,ARO

*
BANZ LOOP

INITIALIZE ARO AS A COUNTER
ARO POINTS TO START OF DATBLK
(DATA MEMORY AREA)
CLEAR ACCUMULATOR
POINT TO ARI
CALCULATE SUM OF DATA IN BLOCK
POINT TO ARO
REPEAT LOOP 8 TIMES

5-21

Software Applications - Program Control

5.3.4 Computed GOTOs
Processing may be executed in a time-dependent (interrupt-driven) or process-dependent (user-selected) way. Selecting the processing mode may
depend on the result of a particular computation. A simple computed GOTO
can be programmed in the TMS320C1 x by using the CALA instruction. This
instruction uses the contents of the accumulator as the direct address of the
call. The address of the subroutine can be computed from a data value to determine which one of several routines will be executed. The return at the end
of each of these routines causes program execution to resume with the instruction following the CALA command. Note that the CALA instruction uses
a level of stack, because it is an indirect subroutine call, not just an indirect
branch.
Example 5-12 illustrates how to compute a call to one of several routines. The
subroutines are defined first, and then'a table of branches to each subroutine
is created. The main part of the program inputs a data value of 0, 1, or 2. The
appropriate address in the table is calculated in the accumulator. An indirect
subroutine call causes the proper branch in the table to be executed.
Example 5-12. Computed GOTO

* THIS ROUTINE COMPUTES AND EXECUTES A SUBROUTINE CALL.
*
STORE CONSTANT 1

ONE
VALUE

SUB1

SUB2

SUB3

TBL1

START

5-22

.set
.set

126
127

VALUE READ FROM PORT 4

IN
RET

DAT1,PAO

INPUT DATA VALUE FROM PORT 0

IN
.RET

DAT1,PA1

INPUT DATA VALUE FROM PORT 1

IN
RET

DAT1,PA2

INPUT DATA VALUE FROM PORT 2

B
B
B

SUB1
SUB2
SUB3

CREATE TABLE OF BRANCHES TO EACH
SUBROUTINE DEFINED

LDPK
LACK
SACL
LT
MPYK
PAC
IN
LT
MPYK
APAC
CALA
LAC

USE PAGE 0
ACC = 1
STORE 1 IN LOCATION ONE
LOAD T REGISTER WITH VALUE OF 1
GET ADDRESS OF TABLE

ONE
ONE
TBL1

INPUT DATA VALUE OF 0, 1, OR 2
LOAD T REG WITH VALUE FROM PA4
CALCULATE OFFSET

DATI

GO TO DESIGNATED SUBROUTINE
RETURN HERE AFTER SUBROUTINE

VALUE,PA4
VALUE

Software Applications - Memory Management

5.4 Memory Management
The TMS320C1 x has a modified Harvard architecture in which the program
and data memories reside in two separate spaces. Therefore. the next instruction fetch can occur while the current instruction is fetching data and
executing the operation. The concept of the Harvard architecture increases the
speed of the device. but it requires the use of instructions to transfer a word
between data memory and program memory.
Data memory consists of 144/256 words of 16-bit on-chip RAM with all
non immediate data operands residing within this RAM. Program memory
consists of 1.5K/4K words of 16-bit on-chip ROM with 1524/4000 words
reserved for program use. Only those devices with EPROM capability can
access all 4096 words. Since there is no microprocessor mode of operation
on the TMS320C17 /E17. all program memory resides within the on-chip
ROM.
The TMS320C1 x uses three forms of data memory addressing: direct. indirect.
and immediate. Direct addressing uses the seven bits of the instruction word
concatenated with the data page pointer to form the data memory address.
Indirect addressing uses the lower eight bits of the auxiliary registers as the
data memory address. Immediate addressing uses part of the instruction word
for data rather than data RAM.
The structure of the TMS320C1 x memory map can vary for each application
(see Section 3.4.4 for memory maps). Instructions are provided for moving
data and for moving constants into data memory. Explanations and examples
are provided in this section~

5.4.1 Moving Data
The DMOV (data move) instruction allows a data word to be written into the
next higher memory location in a single cycle without affecting the accumulator. If variables are placed in consecutive locations. a DMOV instruction
can be used to move each of the variables before the next calculation is performed. For example. when implementing a digital filter. the variables in the
equation rep~esent the inputs and outputs at discrete times. This type of data
structure is typically implemented as a shift register when the data at time t is
shifted to the position previously occupied by the data at time t-1. If consecutive addresses in data memory correspond to consecutive time increments.
then shifts can be accomplished simply by using the DMOV instruction to
move the data item at location d to that corresponding to d+1,

The LTD instruction combines the data move operation with the LTA (load T
register and accumulate previous product) instruction operations, performing
the three operations in parallel. The operand of the instruction is loaded into
the T register; the operand is also written into the next higher memory location; and the P register is added to the accumulator. When using the LTD
instruction. the order of the multiply and accumulate operations becomes important because the data is being moved while the calculation is being performed. The oldest input variable must be mUltiplied by its constant and
loaded into the accumulator first. Then the input. which is one time-unit delay
less. is multiplied and accumulated. This process is repeated until the entire
equation has been computed.
5-23

Software Applications - Memory Management

Example 5-13 illustrates the use of the LTD instruction to move input variables·
in memory as the results are calculated.

Example 5-13. Moving Data Using the LTD Instruction
* THE FOLLOWING EQUATION WILL BE IMPLEMENTED TO DEMONSTRATE
* THE USE OF THE LTD INSTRUCTION. AT THE END OF THE SUB* ROUTINE, LOCATION Xl IS AVAILABLE TO INPUT THE NEW SAMPLE.

Y = A*X3 + B*X2 + C*Xl'

* WHERE A, B, C, Xl, X2, AND X3 ARE VALUES STORED AT THESE
* ADDRESSES.

Xl
X2
X3
Y
A
B
C
*
START

.set
.set
.set
.set
.set
.set
.set
ZAC
LDPK
LT
MPY
LTD
MPY
LTD'
MPY
'APAC
SACH

0
1
2
3
127
126
125

; USE THESE MEMORY LOCATIONS

CLEAR ACCUMULATOR
USE PAGE 0

0
X3
A
X2
B
Xl
C

Y,l

P =1
T
P
T
P
ACC
Y =

A*X3
X2, X2 --> X3, ACC
A*X3
B*X2
Xl, Xl --> X2, ACC
A*X3 + B*X2
C*Xl
= A*X3 + B*X2 + C*Xl
ACCH

The table below illustrates the effect on data memory after execution of the
code in Example 5-13.
Data
Memory

Before Code
Execution

After Code
Execution

Oh
1h
2h

X1
X2
X3

X1
X1
X2

The DMOV feature is useful in implementing filters and convolution algorithms.

5-24

Software Applications - Memory Management

5.4.2 Moving Constants into Data Memory
Most signal processors have a separate memory space for storing constants.
By allowing communication betWeen data and program memory, the
TMS320C1 x is able to incorporate a constant memory capability with its program memory, thus allowing an efficient use of memory space. The portion of
memory not used for storing constants is available for use as program space.
Five immediate instructions provide an efficient way to execute operations
using constants. The LARP instruction changes the auxiliary register pointer,
and the LDPK instruction changes the data page pointer. The LACK, LARK,
and MPYK instructions allow constants to be used in calculations. LACK and
LARK both require an unsigned operand with a magnitude no greater than
eight bits. The MPYK instruction allows a 13-bit signed number as an operand.
A 16-bit value can be moved from program memory to data memory using the
TBLR instruction. TBLR requires that the program memory address (the
source) be in the accumulator, while the data memory address (the destination) is obtained from the operand of the instruction. This instruction is commonly used to look up values in a table in program memory. The address of
the value in the table is computed in the accumulator before executing the
instruction. TBLR then moves the value into data memory. TBLR is a threecycle instruction and, therefore, takes longer than an immediate instruction.
However, it has more flexibility since it operates on 16-bit constants.
Sometimes it is convenient to store data operands in program ROM or external
memory, and then read them into the on-chip RAM as they are needed. Two
means are available for doing this. First, the TBLR (table read) instruction can
be used to transfer data from on-chip program ROM to on-chip data RAM.
Second, off-chip data RAM can be addressed via the IN and OUT instructions.
With some extra hardware, the IN and OUT instructions can be used to read
and writ~ from data RAM to large amounts of external storage addressed as a
peripheral.
Data may also be transferred from data memory to program memory by means
of the TBLW instruction. The IN and OUT instructions can be used to transfer
data between the on-chip data memory and the I/O space (see Section 6.1).
Note that the TBLW (table write) instruction should not be used on the
TMS320C17/E17 since this instruction transfers data from on-chip data RAM
to external memory. The TMS320C17 /E17 does not directly interface to external memory since the port address bits (PA2-PAO) are the only address
lines external to the device.
Example 5-14 illustrates bringing the cosine value of a variable into data
memory using the TBLR instruction. Note that if the address of COSINE is
greater than 255, the address can be loaded . into the accumulator by loading
the T register with a one, multiplying by the constant COSINE, and transferring it from the P register into the accumulator.

5-25

Software Applications - Memory Management

Example 5-14. Moving a Constant into Data Memory Using the TBLR Instruction

* THIS ROUTINE USES THE TBLR ,INSTRUCTION TO BRING THE COSINE
* VALUE OF A VARIABLE INTO DATA MEMORY. A TABLE CONTAINI~G
* THE COSINE VALUES IS FIRST CREATED IN PROGRAM MEMORY.
*
COSINE
DATA
START

IN
LACK
ADD
TBLR

X, PAO
COSINE
X
COSX

LOAD TABLE ADDRESS
CALCULATE PROGRAM MEMORY ADDRESS
MOVE VALUE INTO DATA MEMORY

The following table shows the effect on data memory after the TBlR instruction has been executed in Example 5-14.
Program
Memory

Before TBlR
Execution

After TBlR
Execution

COSINE +X

02FFh

71F2h

02FFh

Data
Memory
COSX

Another method for transferring data from program memory into data memory
uses the TBlR Instruction. By using the TBlR instruction, a calculated, rather
than predetermined, location of data in program memory may be specified for
transfer.· A routine using this approach is shown in Example 5-15.

Example 5-15. Moving Program Memory to Data Memory with TBLR

*
*
*
*

*
*

THIS ROUTINE USES THE TBLR INSTRUCTION TO MOVE DATA VALUES
FROM PROGRAM MEMORY INTO DATA MEMORY. BY USING THIS ROUTINE,
THE PROGRAM MEMORY LOCATION IN THE ACCUMULATOR FROM WHICH
DATA IS TO BE MOVED TO A SPECIFIC DATA MEMORY LOCATION CAN
BE SPECIFIED. ASSUME THAT THE ACCUMULATOR CONTAINS THE
'
ADDRESS IN PROGRAM MEMORY FROM WHICH TO TRANSFER THE DATA.

TABLE

LOOP

LARP 1
LARK AR1,63

USE ARl
START FROM ADDRESS 63

TBLR *
BANZ LOOP
RET

MOVE DATA INTO DATA RAM
TRANSFER 64 VALUES
RETURN TO CALLING PROGRAM

In cases where systems require that temporary storage be allocated in the
program memory, TBlW can be used to transfer data from internal data
memory to external program memory. The code in Example 5-16 demonstrates how this may be accomplished.

5-26

Software Applications - Memory Management

Example 5-16. Moving Internal Data Memory to Program Memory with TBLW
* THIS ROUTINE USES THE TBLW INSTRUCTION TO MOVE DATA VALUES
* FROM INTERNAL DATA MEMORY TO EXTERNAL PROGRAM MEMORY. THE
* CALLING ROUTINE MUST SPECIFY THE DESTINATION PROGRAM MEMORY
* ADDRESS IN THE ACCUMULATOR. ASSUME THAT THE ACCUMULATOR
* CONTAINS THE ADDRESS IN PROGRAM MEMORY INTO WHICH THE DATA
* IS TRANSFERRED.
*
TABLE LARK ARi,63
; LOAD LOOP COUNT OF 64
LARK ARO,DATi; LOAD STARTING ADDRESS
*
LOOP
LARP ARO
USE ARO
MOVE DATA TO EXTERNAL PROGRAM RAM
TBLW *+,ARi
DECREMENT AND CHECK IF DONE
BANZ LOOP
RET
RETURN TO CALLING PROGRAM

After the execution of the TBLW instruction, the following effect has occurred
on program memory:
Program
Memory

Before TBLW
Execution

After TBLW
Execution

PROG1

OFF10h

1234h

Data
Memory
DAT1

The IN and OUT instructions are used to transfer data between the data memory and the I/O space, as shown in Example 5·17 and Example 5-18.

Example 5-17. Moving Data from I/O Space into Data Memory with IN
* THIS ROUTINE USES THE IN INSTRUCTION TO MOVE DATA VALUES
* FROM THE I/O SPACE INTO DATA MEMORY. DATA ACCESSED FROM
* I/O PORT 7 IS TRANSFERRED TO SUCCESSIVE MEMORY LOCATIONS
* ON DATA PAGE O.
*
INPUT LARK ARO,32
SET UP LOOP COUNT
SET UP DESTINATION ADDRESS
LARK ARi,DATi
*
USE ARi
LOOP
LARP ARi
IN
*+,PA7,ARO
MOVE DATA INTO DATA RAM
BANZ LOOP
DECREMENT AND CHECK IF DONE
RET
RETURN TO CALLING PROGRAM

5-27

Software Applications - Memory Management

Example 5-18. Moving Data from Data Memory to I/O Space with OUT
*
*
*
*

TaIS ROUTINE USES THE OUT INSTRUCTION TO MOVE DATA VALUES
FROM THE DATA MEMORY TP THE I/O SPACE .• DATA IS TRANSFERRED
TO I/O PORT 7 FROM SUCCESSIVE MEMORY LOCATIONS ON DATA
PAGE O.

OUTPUT LARK ARO,32
LARKARl.,DATl

LOOP

5-28

LARP
OUT
BANZ
RET

ARI
*+,PA7,ARO
LOOP

SET UP LOOP COUNT
SET UP STARTING ADDRESS
USE ARI
MOVE DATA INTO I/O SPACE
DECREMENT AND CHECK IF DONE
RETURN TO CALLING PROGRAM

Software Applications - Logical and Arithmetic Operations

5.5 logical and Arithmetic Operations
Although the TMS320C1 x instruction set is oriented toward digital signal
processing, the same fundamental operations of a general-purpose processor,
such as bit manipulation, logical and arithmetic operations, logical and arithmetic shifts, and overflow management, are included. Explanations and examples of how to use instructions for scaling, convolution operations,
fixed-point multiplication/division/addition, and floating-point arithmetic are
also included in this section.
The contents of the accumulator may be stored in data memory using the
SACH and SACL instructions or stored in the stack by using the PUSH instruction. The accumulator may be loaded from data memory using the ZALH,
ZALS, and LAC instructions, which zero the accumulator before loading the
data value. The ZAC instruction zeroes the accumulator. POP can be used to
restore the accumulator contents from the stack. The accumulator is also affected by the execution of the ABS instruction, which replaces the contents
of the accumulator with its absolute value.

5.5.1

Bit Manipulation
A specified bit of a word from data memory can either be set, cleared, or
tested. Such bit manipulations are accomplished by using the hardware shifter
and the logic instructions, AND, OR, and XOR. In Example 5-19, operations
on single bits are performed on the data word VALUE. In this and the following example, data memory location ONE contains the value 1 and MINUS
contains the value -1 (all bits set).

Example 5-19. Single-Bit Manipulation

*
* CLEAR BITS OF DATA MEMORY LOCATION VALUE. MEMORY LOCATION

*
*
*

**
*
*

*
*

ONE CONTAINS CONSTANT 1. MEMORY LOCATION MINUS CONTAINS -1
OR OFFFFh.
LAC
XOR
AND
SACL

ONE,S
MINUS
VALUE
VALUE

ACC = 00000020h
INVERT ACCUMULATOR; ACC = OOOOFFDFh
BIT S OF VALUE IS ZEROED

SET BIT 12 OF VALUE.
LAC ONE,12
OR
VALUE
SACL VALUE

; ACC = 00001000h
; BIT 12 OF VALUE

TEST BIT 3 OF VALUE.
LAC
AND
BZ

ONE,3
VALUE
BIT3Z

ACC = 00000008h
TEST BIT 3 OF VALUE
BRANCH TO BIT3Z IF BIT IS CLEAR

More than one bit can be set, cleared, or tested at one time if the necessary
mask exists in data memory. In Example 5-20, the six low-order bits in the
word VALUE are cleared if MASK contains the value 63.
5-29

Software Applications -Logical and Arithmetic Operations

Example 5-20. Multiple-Bit Manipulation

**
*
*
*

CLEAR LOWER SIX BITS OF VALUE. MEMORY LOCATION MASK
CONTAINS THE MASK TO CLEAR THE BITS. MEMORY LOCATION
MINUS CONTAINS -lOR OFFFFh.
LAC
XOR
AND
SACL

MASK
MINUS
VALUE
VALUE

ACC = 0000003Fh
INVERT ACCUMULATOR; ACC
CLEAR LOWER SIX BITS

OOOOFFCOh

5.5.2 Overflow Management
The TMS320C1 x has two features that can be used to handle overflow management. These include the branch on overflow conditions and accumulator
saturation (overflow mode). These features provide several 'options for overflow protection within an algorithm.
A program can branch to an error handler routine on an overflow of the accumulator by using the BV (branch on overflow) instruction. This instruction
can be performed after any ALU operation that may cause an accumulator
overflow.
The overflow mode is a feature useful for DSP applications. This mode simulates the saJuration effect characteristic of analog systems. When enabled,
any overflow in the accumulator results in the accumulator contents being
replaced with the largest positive value (7FFFFFFFh) if. the overflowed num~
ber is positive, or the largest negative value (80000000h) if negative. The
overflow mode is controlled by the OVM bit of the status register and can be
changed by the SOVM (set overflow mode). ROVM (reset overflow mode),
or LST (load status register) instructions. Overflows can be detected in software by testing the OV (overflow) bit in the status register. When a branch is
used to test the overflow bit, OV is automatically reset. Note that the OV bit
does not function as a carry bit. It is set only when the absolute value of a
number is too large to be represented in the accumulator, and it is not reset
except by specific instructions. The overflow mode feature affects all arithmetic operations in the ALU.
\

In Example 5-21, the accumulator saturates to 7FFFFFFFh or the largest positive value. The BV instruction also clears the OV bit.

Example 5-21. Overflow Management

*
*
*
*
*

*
5-30

THE ACCUMULATOR WILL SATURATE TO THE HIGHEST POSITIVE VALUE
WHEN OVERFLOW OCCURS. THE ACCUMULATOR CONTAINS 7FFFF423h.
MEMORY LOCATION A CONTAINS 74EDh. MEMORY LOCATION B
CONTAINS 67AFh.
SOVM
LT
MPY
.jU'AC
BV

A
B

OVRFLW

SET OVERFLOW MODE
T = 74EDh
P = 2FSB4903h
ACC = 7FFFFFFFh
CHECK OV BIT'
BRANCH TO OVERFLOW HANDLING ROUTINE

Software Applications - Logical and Arithmetic Operations

The effect on the accumulator before and after the code execution is shown
as follows:

ACC

Before Code
Execution

After Code
Execution

7FFFF423h

7FFFFFFFh

5.5.3 Scaling
Scaling the data coming into the accumulator or already in the accumulator is
useful in signal processing algorithms. This is frequently necessary in adaptation or other algorithms that must compute and apply correction factors or
normalize intermediate results. Scaling and normalizing are implemented on
the TMS320C1 x via shifts of data on the incoming path to the accumulator.
There are two types of shifts: logical and arithmetic. A logical shift is implemented by filling the empty bits to the left of the MSB with zeros, regardless
of the value of the MSB. An arithmetic shift fills the empty bits to the left of
the MSB with ones if the MSB is one, or with zeros if the 'MBS is zero. The
second type of bit padding is referred to as sign extension.
Data can be left-shifted 0 to 16 bits when the accumulator is loaded, and
left-shifted 0, 1, or 4 bits when storing from the accumulator using the SACH
instruction. These shifts can be used for loading numbers into the high 16
bits of the accumulator and renormalizing the result of a mUltiply. The incoming left shift of 0 to 16 bits is supplied in the instruction itself. Left shifts
of data fetched from data memory are available for loading the accumulator
(LAC), adding to the accumulator (ADD), and subtracting from the accumulator (SUB). When data is left-shifted 16 bits, the ZALH, ADDH, and
SUBH instructions are used. The left-shift of 0, 1, or 4, available with the
SACH instruction, is used to shift out the extra sign bits when fractional multiplication is used (see Section 5.5.5).
The hardware shift, which is built into the ADD, SUB, and LAC instructions,
performs an arithmetic left-shift on a 16-bit word. Thisleature can also be
used to perform right-shifts. A right-shift of n is implemented by performing
a left-shift of 16-n and saving the upper word of the accumulator. Example
5-22 performs an arithmetic right-shift of 7 on a 16-bit number in the accumulator.

Example 5-22. Arithmetic Right-Shift
SACL
LAC
SACH
LAC

TEMP
TEMP,9
TEMP
TEMP

MOVE NUMBER TO MEMORY
; SHIFT LEFT (16-7)
SAVE HIGH WORD IN MEMORY
RETURN NUMBER BACK TO ACCUMULATOR

The effect on the accumul::ttor before and after the code execution is shown
as follows:

ACC

Before Code
Execution

After Code
Execution

OFFFFA452h

OFFFFFF48h

A logical right-shift of 4 on a 32-bit number stored in the accumulator is
shown in Example 5-23. The 32-bit results of the shift are then stored in data
5-31

Software Applications - Logical and Arithmetic Operation~

memory. In this example, the accumulator initially contains the hexadecimal
number, 9D84C1 B2h. The variables, SHIFTH and SHIFTL, will receive the
high word (09D8h) and low word (4C1 Bh) of the shifted results.

Example 5-23. Logical Right-Shift

*
*

SHIFT THE LOWER WORD. MEMORY LOCATION MINUS CONTAINS -1

* OR OFFFFh.

**
*

SACH
SACL
LAC
SACH
LAC
XOR
AND

SHIFTH
SHIFTL
SHIFTL,12
SHIFTL
MINUS, 12
MINUS
SHIFTL

INITIAL VALUES
SHIFTH = 9D84h
SHIFTL = OC1B2h
ACC = OFC1B2000h
SHIFTL = OFC1Bh
ACC
OFFFFFOOOh
ACC
OFFFFOFFFh
ACC
OOOOOC1Bh

SHIFT THE UPPER WORD.
ADD
SACL
SACH
LAC
XOR
AND
SACL

SHIFTH,12
SHIFTL
SHIFTH
MINUS, 12
MINUS
SHIFTH
SHIFTH

ACC = OF9D84C1Bh
SHIFTL = 4C1Bh
FINAL LOW VALUE
SHIFTH = OF9D8h
ACC = OFFFFFOOOh
ACC = OFFFFOFFFh
ACC = 000009D8h
·SHIFTH = 09D8h
FINAL HIGH VALUE

The accumulator is affected before and after the code execution as follows:

ACC

Before Code
Execution

After Code
Execution

9D84C1B2h

09D84C1 Bh

An arithmetic right-shift of 4 can be implemented using the same routine as
shown above, except with the last four lines omitted.

5.5.4 Convolution Operations
Many DSP applications must perform convolution operations or other operations similar in form. These operations require data to be shifted or delayed.
The DMOV and LTD instructions can perform the needed data moves for
convolution. .
!
The data move function is used for on-chip data memory. It allows a word to
be copied from the currently addressed data memory location in on-chip RAM
to the next higher location while the data from the addressed location is being
operated upon (e.g., by the CALW). The data move and the CALU operation
are performed in the same cycle. The data move function is useful in implementing algorithms, such as convolutions and d,igital filtering, where data is
being passed through a time window. It models the z-1 delay operation encountered in those applications.

5-32

Software Applications - Logical and Arithmetic Operations

5.5.5 Multiplication
The TMS320C1 x hardware multiplier normally performs two's-complement
16-bit by 16-bit multiplies and produces a 32-bit result in a single processor
cycle. To multiply two operands, one operand must be loaded into the T
register. The second operand is moved by the multiply instruction to the
multiplier, which then produces the product in the P register. Before another
multiply can be performed, the contents of the P register must be moved to the
accumulator. By pipelining multiplies and P-register moves, most multiply
operations can be performed with a single instruction.
Computation on the TMS320C1 x is based on a fixed-point two's-complement
representation of numbers. Each 16-bit number is evaluated with a sign bit, i
integer bits, and 15-i fractional bits. Thus, the number

o 0000010

10100000

~ binary point

has a value of 2.625. This particular number is said to be represented in a 08
format (8 fractional bits). Its range is between -128 (1000000000000000)
and 127.996 (0111111111111111). The fractional accuracy of a 08 number
is about 0.004 (one part in 28 or 256).
Although particular situations (e.g., a combination of dynamic range and accuracy requirements) must use mixed notations, it is more common to work
entirely with fractions represented in a 015 format or integers in a 00 format.
This is especially true for signal processing algorithms where multiply and accumulate operations are dominant. The result of a fraction times a fraction remains a fraction, and the result of an integer times an integer remains an
integer. No overflows are possible.

o format is a number representation commonly used when performing operations on noninteger numbers. In 0 format, the 0 number (15 in 015) denotes
how many bits are located to the right of the binary point. A 16-bit number in
015 format, therefore, has an assumed binary point immediately to the right
of the most significant bit. Since the most significant bit constitutes the sign
of the number, then numbers represented in 015 may take on values from + 1
(represented by +0.99997 ... ) to -1.
A wide variety of situations may be encountered when multiplying two numbers. Three of these situations are provided in Example 5-24, Example 5-25,
and Example 5-26.

5-33

Software Applications - Logical and Arithmetic Operations

Example 5-24. Fraction x Fraction (015 x 015
x

= 030)

0100000000000000
0100000000000000

= 0.5 in 015
= 0.5 in 015

0000000000000000

= 0.25 in 030

00 01000000000000

I-

binary point

Two sign bits remain after the multiply. Generally, a single-precision (16-bit)
result is saved, rather than maintaining the full intermediate precision. The
upper half of the result does not contain a full 15 bits of fractional precision
since the mUltiply operation actually creates a second sign bit. In order to recover that precision, the product must he shifted left by one bit, as shown in
the following code excerpt:
LT
MPY
PAC
SACH

OP1
OP2

4000h ,CO.5 in Q15)
4000h (0.5 in Q15)

ANS,l

ANS

2000h (0.25 in Q15)

The MPYK instruction provides a multiply by a 13-bit signed constant. In
fractional notation, this means that a 015 number can be multiplied by a 012
number. The resulting number must be left-shifted by four bits to maintain full
precision.
LT
MPYK
PAC
SACH

OP1
2048

OP1
OP2

4000h (0.5
0800h (0.5

ANS,4

ANS

2000h (0.25 in Q15)

Example 5-25. Integer x Integer (00 x 00
x
1111111111111111

in Q15)
in Q12)

= 00)

0000000000010001
1111111111111011

17 in 00
-5 in 00

1111111110101011

-85 in 00

I-

binary point

In this case, the extra sign bits do not change the result, and the desired product is entirely in the lower half of the product, as shown in the following
program:
LT
MPY
PAC
SACH

5-34

OP1
OP2

OOllh ( 17 in QO)
OFFFBh ( -5 in QO)

ANS

OFFABh (-85 in QO)

Software Applications - Logical and Arithmetic Operations

Example 5-26. Mixed Notation (014 x 014 = 028)
x

0001

001000000000

0110000000000000
0011000000000000

= 1.50 in 014

=
=

0000000000000000

0.75 in 014
1 .125 in 028

~ binary point
The maximum magnitude of a 014 number is just under two. Thus, the maximum magnitude of the product of two 014 numbers is four. Two integer bits
are required to allow for this possibility, leaving a maximum precision for the
product of 13 bits. In general, the following rule applies: The product of a
number with i integer bits and f fractional bits and a second number with j
integer bits and g fractional bits will be a number with (i+j) integer bits and
(f+g) fractional bits. The highest precision possible for a 16-bit representation
of this number will have (i+j) integer bits and (15-i-j) fractional bits.
If the physical system being modelled is well understood, the precision with
which the number is modelled can be increased. For example, if it is known
that the above product can be no more than 1.8, the product can be represented as a 014 number rather than the theoretical worst case of 013, shown
in the following program:
LT
MPY
PAC
SACH

OP1
OP2

6000h (1.5
3000h (0.75

in Q14)
in Q14)

ANS , 1

ANS

2400h (1.125 in Q13)

The techniques illustrated in the previous three examples all truncate the result
of the multiplication to the desired precision. The error generated as a result
can be as much as minus one full LSB. This is true whether the truncated
number is positive or negative. It is possible to implement a simple rounding
technique to reduce this potential error by a factor of two, as shown in the
code sequence of Example 5-27. The maximum error generated in this example is plus one-half LSB whether ANS is positive or negative.

Example 5-27. Rounding Technique for Multiplication
LT
MPY
PAC
ADD
SACH

OP1
OP2

OP1

ONE,lL'

ROUND UP

OP2

ANS , 1

A common operation in DSP algorithms is the summation of products. The
contents of the P register are added to the accumulator, and two values simultaneously read and multiplied. A data memory value is multiplied by a
program memory value. Example 5-28 shows an implementation of multiplies
and accumulates using the LTA-MPY instruction pair.

5-35

Software Applications -' Logical and Arithmetic Operations

Example 5-28. Multiply and Accumulate Using the lTA-MPY Instruction Pair

*
*
*

CLOCK
CYCLES
ZAC
LT
MPY
LTA
MPY

01
C1
02
C2

TOTAL CLOCK
CYCLES

1
1
1
1
1

PROGRAM
MEMORY
1
1
1
1
1

2N
LTA ON
MPY CN
APAC

5.5.6

1
1
1

TOTAL PROGRAM
MEMORY

2 + 2N

1
1
1

2 + 2N

Division
Binary division is the inverse of multiplication. Multiplication consists 9f a
series of shift and add operations, while division can be broken into a series
of subtracts and shifts. Although the first-generation TMS320 does not have
an explicit divide instruction, it is possible to implement an efficient flexible
divide capability using the conditional subtract instruction, SUBC. SUBC
implements binary division in the same manner as is commonly done in long
division. Given a 16-bit positive dividend and divisor, the repetition of the
SUBC command 16 times produces a 16-bit q~otient in the low accumulator
and a 16-bit remainder in the high accumulator. With each SUBC, the divisor
is left-shifted 15 bits and subtracted from the accumulator. For each subtract
not producing a negative answer, a one is put in the lSB of the quotient and
then shifted. For each subtract producing a negative answer, the accumulator
is simply left-shifted.' The shifting of the remainder and quotient after each
subtract produces the separation of the quotient and remainder in the low and
high halves of the accumulator. The similarities between long division and the
SUBC method of division are shown in Figure 5-1 where 33 is dividec;l by 5.

5-36

Software Applications - Logical and Arithmetic Operations

LONG DIVISION:
Quotient

0000000000000110
0000000000000101 )0000000000100001
-101

110

-101
-11

Remainder

SUBC METHOD:
132

HIGH ACC

1 1

LOW ACC

COMMENT

0000000000000000
-10
-10

0000000000100001
1000000000000000
0111111111011111

1
1
0000000001000010 (2) 2nd subtract produces negative
1000000000000000
answer, so discard result and shift
0111111110111110
ACC (dividend) left.

1
0000000000000000
-10
-10
o
o

0000000000000100
-10
0000000000000001

Dividend Is loaded Into ACC. The
divisor Is left-shifted 15 and subtracted from ACC. The subtraction
Is negative, so discard the result
and shift left the ACC one bit.

··•

0010000000000000 (14) 14th SUBC command. The result
1000000000000000
IS positive. Shift result left and
1010000000000000
replace LSB with '1'.

I
0000000000000011
-10

(1)

0100000000000001 (15) Result Is again positive. Shift
1000000000000000
result left and replace LSB with '1'.

0000000000000000 1100000000000001

I I

0000000000000001
-10

1000000000000011 (16) Last subtract. Negative answer, so
1000000000000000
discard result and shift ACC left.
- 1111111111111101

0000000000000011

0000000000000110

REMAINDER

QUOTIENT

Answer reached after 16 SUBC
Instructions.

Figure 5-1, Long Division and SUBC Division

The condition of the divisor, less than the shifted dividend, is determined by
the sign of the result. The only restriction for the use of the SUBC instruction
is that both the dividend and divisor MUST be positive. Thus, the sign of the
quotient must be determined and the quotient computed using the absolute
value of the dividend and divisor. In addition, when implementing a divide
algorithm, it is important to know if the quotient can be represented as a
fraction and the degree of accuracy to which the quotient is to be computed.
Each of these considerations can affect how the SUBC instruction is used (see
Example 5-29 and Example 5-30). Note that the next instruction after SUBC
cannot use the accumulator.

5-37

Software Applications - Logical and Arithmetic Operations

Example 5-29. Using SUBC Where Numerator < Denominator

*
*
*
*
*
*
*
*
*
*
*
*

THIS ROUTINE DIVIDES TWO BINARY, TWO'S-COMPLEMENT NUMBERS
OF ANY SIGN WHERE THE NUMERATOR IS LESS THAN THE
DENOMINATOR.
BEFORE
INSTRUCTION
NUMERA
DENOM
QUOT

DIV

**
*

LARP
LT
MPY
PAC
SACH
LAC
ABS
SACL
ZALH
ABS
LARK

21 1
42
0.5
(0.1 0 0)

21
42
0
0
NUMERA
DENOM

GET SIGN OF QUOTIENT

TEMSGN
DENOM

SAVE SIGN OF QUOTIENT

DENOM
NUMERA

MAKE DENOMINATOR POSITIVE
ALIGN NUMERATOR
MAKE NUMERATOR POSITIVE

0,14

IF DIVISOR AND DIVIDEND ARE ALIGNED, DIVISION CAN START
HERE.

KPDVNG SUBC
BANZ

DONE

5-38 "

AFTER
INSTRUCTION

SAGL
LAC
BGEZ
ZAC
SUB
SACL
RET

DENOM
KPDVNG
QUOT
TEMSGN
DONE
QUOT
QUO,]"

; lS-CYCLE DIVIDE LOOP

(

DONE .IF SIGN IS POSITIVE
NEGATE QUOTIENT IF NEGATIVE
RETURN TO MAIN PROGRAM

Software Applications - Logical and Arithmetic Operations

Example 5-30. Using SUBC Where Accuracy of Quotient Specified

* THIS ROUTINE DIVIDES TWO BINARY, TWO'S-COMPLEMENT NUMBERS

OF ANY SIGN, SPECIFYING THE FRACTIONAL ACCURACY OF THE
.

* QUOTIENT (FRAC).

*
*
*
* NUMERA
* DENOM
*
* FRAC
* QUOT
*
*
DNI
LT
MPY
PAC
SACH
LAC
ABS
SACL
LACK
ADD
SACL
LAC
ABS
LAR

* IF DIVISOR
** HERE.
*
KPDVNG SUBC
BANZ

DONE

SACL
LAC
BGEZ
ZAC
SUB
SACL
RET

BEFORE
INSTRUCTION

AFTER
INSTRUCTION

11
8
3
17

11
8
3
1. 375
(1.0 1 1)

NUMERA
DENOM

GET SIGN OF QUOTIENT

TEMSGN
DENOM

SAVE SIGN OF QUOTIENT

DENOM

MAKE DENOMINATOR POSITIVE

FRAC
FRAC
NUMERA

COMPUTE LOOP COUNT
ALIGN NUMERATOR
MAKE NUMERATOR POSITIVE

O,FRAC
AND DIVIDEND ARE ALIGNED, DIVISION CAN START
DENOM
KPDVNG
QUOT
TEMSGN
DONE
QUOT
QUOT

;

16 + FRAC CYCLE DIVIDE LOOP
I

DONE IF SIGN IS POSITIVE
NEGATE QUOTIENT IF NEGATIVE
RETURN TO MAIN PROGRAM

5.5.7 Addition
Both operands in division must be represented in the same Q format. Enough
room must be allowed in the result to accommodate bit growth or there must
be some preparation to handle overflows. If the operands are only 16 bits
long, the result may have to be represented as a double-precision number.
Example 5-31 and Example 5-32 illustrate two approaches to adding 16-bit
numbers.

Example 5-31. Maintaining 32-Bit Results
LAC
ADD
SACH
SACL

OPI
OP2
ANSHI
ANSLO

Q15
Q15

HIGH-ORDER 16 BITS OF RESULT
LOW-ORDER 16 BITS OF RESULT
5-39

Software Applications - Logical and Arithmetic Operations

Example 5-32. Adjusted Binary Point to Maintain 16-Bit Results
LAC
ADD
SACH

OP1,15
OP2,15
ANS

Q14 NUMBER IN ACCH
Q14 NUMBER IN ACCH
Q14

Double-precision operands present a more complex problem since actual
arithmetic overflows or underflows may occur. The BV (branch on overflow)
instruction can be used to check for the occurrence of these conditions. A
second technique is the use of saturation mode operations, which will saturate
the result of overflowing'accumulations to the most positive or most negative
number. Both techniques, however, result in a loss of precision. The best
technique involves a thorough understanding of the underlying physical
process and care in selecting number representations.

5.5.8 Floating-Point Arithmetic
Although the TMS320C1 x devices are fixed-point 16/32-bit microprocessors,
they can also perform floating-point computations. Using the floating-point
single-precision standard proposed by the IEEE, the TMS320C1 x can perform
a floating-point multiplication in 8.4 I.IS and a floating-point addition in 17.2
I.IS. For a detailed discussion of floating-point arithmetic and TMS320 source
code, refer to "Floating-Point Arithmetic with the TMS32010," an application
report in the book, Digital Signal Processing Applications with the TMS320
Family (literature number SPRA012A).
Floating-point numbers are often represented on microprocessors in a twoword format of mantissa and exponent. The mantissa is stored in one word.
The exponent, the second word, indicates how many bit positions from the left
the binary point is located. If the mantissa is 16 bits, a 4-bit exponent is sufficient to express the location of the binary point. Because of its 16-bit word
size, the 16/4-bit floating-point format functions most efficiently on the
TMS320C1x.
Operations in the TMS320C1 x central ALU are performed in two'scomplement fixed-point nOlation. To implement floating-point arithmetic,
operands must be converted to fixed point for arithmetic operations, and then
converted back to floating point. Conversion to floating-point notation is
performed by normalizing the input data (Le .• shifting the MSB of the data
word into the MSB of the internal memory word). The exponent word then
indicates how many shifts are required. To mUltiply two floating-point numbers, the mantissas are multiplied and the exponents added. The resulting
mantissa must be renormalized. (Since the input operands are normalized, no
more then one left shift is required to normalize the result.)
Floating-point addition or subtraction requires shifting the mantissa so that
the exponents of the two operands match. The difference between the exponents is used to left-shift the lower power operand before adding. Then, the
Qutput of the add must be renormalized.
Instructions useful in floating-point operations are the LAC, LACK. ADD, and
SUB instructions. The mantissas are often used in 015 format. 0 format is a
number representation commonly used when performing operations on noninteger numbers. If! 0 format, the 0 number (15 in 015) denotes how many
5-40

Software Applications - Logical and Arithmetic Operations

digits are located to the right of the binary point. A 16-bit number in Q15
format, therefore, has an assumed binary point immediately to the right of the
most significant bit. Since the most significant bit constitutes the sign of the
number, then numbers represented in Q15 may take on values from +1 (represented by +0.99997 ... ) to -1.

5-41

Software Applications - Application-Oriented Operations
>

,5.6 Application-Oriented Operations
The TMS320C1 x has been designed to provide efficient implementations of
many common digital signal processing algorithms. Its features provide solutions to numerically intensive problems usually characterized by multiply and
accumulate operations. Some device-specific features that aid in the implementation of specific algorithms on the TMS320C1 x include companding, filtering, Fast Fourier Transforms (FFT), and PID control. These applications
reqLJirel/O performed either in para"el or serial.

5.6.1 Companding
In the area of telecommunications,one of the. primary concerns is the I/O
bandwidth in the communications channel. One way to minimize this bandwidth is by companding (COMpress/exPAND). Companding is defined by
two international standards, A-law and fJ-law, both based on the compression
of the equivalent of 13 bits of dynamic range into an 8-bit code. The standard
employed in the United States and Japan is fJ-law companding. The European
standard is referred to as A-law companding. Detailed descriptions and code
examples of fJ-law and A-law companding are presented in "Companding
Routines for the TMS3201 0/TMS32020," an application report included in
the book, Digital Signal Processing Applications with the TMS320 Family
(literature number SPRA012A).
The technique of companding allows the digital sample information corresponding to a 13-bit dynamic range to be transmitted as 8-bit data. For
processing in the TMS320C1 x, it is necessary to convert the 8-bit logarithmic
data to a 16-bit linear format. Prior to output, the linear result must be converted to the compressed or companded format. On the TMS3201 0/C1 0/C15,
companding must be performed in software using conversion routines. Onchip companding hardware on the TMS320C17 /E17 implements these functions.
Software routines for fJ-law and A-law companding, flowcharts, companding
algorithms, and detailed descriptions are provided in the application report on
companding routines in the book, Digital Signal Processing Applications with
the TMS320 Family (literature number SPRA012A). The algorithm space and
time requirements for fJ-law and A-law companding on the TMS32010/
C1 0/C15/E15 are given in Table 5-2.

Table 5-2. Program Space and Time Requirements for fJ-/A-Law
Companding
FUNCTION
fJ-Law:
Compression
Expansion

WORDS OF MEMORY
PROGRAM CYCLES
. Initialization Loop*
Program
Data
105
46

A-Law:
Compression
97
48
Expansion
tAssuming initialization
+Worst case

5-42

TIME REQDt
fJS

13
8

17
6

40
23

8.0
4.6

11
7

14
4

36
25

7.2
5.0

Software Applications - Application-Oriented Operations

Four modes are available for the on-chip companding hardware operation on
the TMS320C17 I E17: serial encode, serial decode, parallel encode, and parallel decode. The companding hardware converts between two's-complement
or sign-magnitude format and the companded format.
In the serial encode mode, transmitted data is encoded according to either
IJ-Iaw or A-law format. In the serial decode mode, received data is decoded
to a linear format according to the specified companding law.
\

In the parallel modes, either the encoder or decoder is enabled, and then data
written to port 1 is compressed or expanded. To convert sign-magnitude or
two's-complement linear PCM to 8-bit log PCM, the encoder is enabled for
parallel operation, and the sample is written to port 1. An IN instruction from
port 1 returns the linear PCM value. To convert an 8-bit log PCM to a signmagnitude or two's-complement linear PCM, the decoder is enabled for parallel operation, and the 8-bit sample is written to port 1. The expanded linear
value is returned on the IN instruction from port 1. Note that when the conversion mode selected converts' a two's-complement value, there must be one
instruction cycle between the OUTand IN instructions. Care should be taken
to have one OUT-IN instruction sequence ,to port 1 for each data sample, because the execution of two OUT instructions to port 1 in succession pushes
the first sample into the transmit register TR1, preventing access for read purposes. OUT instructions to port addresses 2 through 7 will not affect serialport operations.
When the companding hardware converts to sign-magnitude data, it must be
converted to two's-complement notation for computation in the microcomputer. Sign-magnitude notation consists of a sign bit in the MSB: a zero indicating a positive value, and a one indicating a negative number. All bits
between the sign bit and the MSB of the data value are set to zero. For conversions between IJ-Iaw and sign-magnitude linear PCM, the hexadecimal
value 1 FFFh represents the most positive value of 8191 and the value 9FFFh
represents the most negative value of-8191. For conversions between A-law
and sign-magnitude linear PCM, the hexadecimal value OFFFh represents the
10st positive value of 4095 and the value 8FFFh represents the most negative
alue' of -4095.
Conversion between sign-magnitude and two's-complement data for ,..-Iaw
encoding and decoding is implemented with the code shown in Example 5-33
and Example 5-34, respectively. Conversion between two's-complement and
sign-magnitude data for A-law encoding and decoding is implemented with
the code shown in Example 5-35 and Example 5-36, respectively. Note that
both TMS320C17/E17 devices feature hardware companding logic that can
operate in either ,..-Iaw or A-law format with either sign-magnitude or two'scomplement numbers.

. 5-43

Software Applications - Application-Oriented Operations

Example 5-33. Two's-Complement to Sign-Magnitude for IJ-Law Encoding

* THIS ROUTINE CONVERTS A TWO'S-COMPLEMENT NUMBER TO 14-BIT
* SIGN-MAGNITUDE FORMAT AND ADDS THE BIAS OF 33 FOR MU-LAW
* ENCODING. MEMORY LOCATION 1 CONTAINS THE VALUE 1 AND
* MEMORY LOCATION 2 (BIAS) CONTAINS +33.
*
OUTPUT
LAC SAMPLE
GET THE LINEAR DATA FOR OUTPUT
BGEZ POSOUT
IF POSITIVE, CHECK POS MAX VALUE
ABS
IF NEGATIVE, CHECK ABSOLUTE VALUE
ADD BIAS
ADD IN THE BIAS OF 2lh
ADD ONE,15
SET THE SIGN BIT NEGATIVE
SACL SAMPLE
HOLD FOR LATER
SUB NEGMAX
COMPARE TO NEGATIVE MAX = 9FFFh
BLEZ DONE
IF WITHIN MAX, THEN SEND IT
ELSE, LOAD THE VALUE WITH THE
LAC NEGMAX
SACL SAMPLE
LARGEST NEGATIVE IN RANGE
AND SEND IT
B
DONE
POSOUT ADD BIAS
ADD IN THE BIAS OF 2lh
SACL SAMPLE
AND SAVE IT
SUB POSMAX
COMPARE TO POSITIVE MAX = lFFFh
BLEZ DONE
IF WITHIN MAX, THEN SEND IT
ELSE, LOAD THE VALUE WITH THE
LAC POSMAX
SACL SAMPLE
LARGEST POSITIVE VALUE IN RANGE
DONE
OUT SAMPLE,PAl ; AND SEND IT TO ENCODER
CONTINUE CODE HERE
*
I

Example 5-34. Sign-Magnitude to Two's-Complement for IJ-Law Decoding

*
*
*
*
*

THIS ROUTINE CONVERTS A l4-BIT SIGN-MAGNITUDE NUMBER TO
TWO'S-COMPLEMENT NOTATION AND REMOVES THE BIAS OF 33 FOR
MU-LAW DECODING. MEMORY LOCATION 1 CONTAINS THE VALUE 1
AND MEMORY LOCATION 2 (BIAS) CONTAINS 33.

INPUT

POS

IN
SAMPLE,PAl
READ INPUT FROM SERIAL PORT; DECODE,
LAC SAMPLE
MOVE INPUT TO ACCUMULATOR
REMOVE BIAS VALUE
SUB BIAS
BGEZ POS
IF POSITIVE, THEN SAVE IT
ELSE, DELETE SIGN BIT BY CARRY
ADD ONE,15
SACL SAMPLE
SAVE MAGNITUDE VALUE
NEGATE THE INPUT BY
ZAC
SUBTRACTING FROM ZERO AND SAVE
SUB SAMPLE
SACL SAMPLE
; FULLY EXPANDED LINEAR DATA
CONTINUE CODE HERE

Software Applications - Application-Oriented Operations

Example 5-35. Two's-Complement to Sign-Magnitude for A-Law Encoding

*
*

THIS ROUTINE CONVERTS A TWO'S-COMPLEMENT NUMBER TO l3-BIT
SIGN-MAGNITUDE NOTATION FOR A-LAW ENCODING. MEMORY
* LOCATION 1 CONTAINS THE VALUE 1.

OUTPUT
LAC SAMPLE
GET THE LINEAR DATA FOR OUTPUT
BGEZ POSOUT
IF POSITIVE, CHECK POS MAX VALUE
ABS
IF NEGATIVE, CHECK NEG MAX VALUE
ADD ONE,15
SET THE SIGN BIT NEGATIVE
SACL SAMPLE
HOLD FOR LATER
SUB NEGMAX
COMPARE TO NEGATIVE MAX = 8FFFh
BLEZ DONE
IF WITHIN MAX, THEN SEND IT
LAC NEGMAX
ELSE, LOAD THE VALUE WITH THE
SACL SAMPLE
LARGEST NEGATIVE IN RANGE
B
DONE
AND SEND IT
POSOUT SACL SAMPLE
SAVE IT
SUB POSMAX
COMPARE TO POSITIVE MAX = OFFFh
BLEZ DONE
IF WITHIN MAX, THEN SEND IT
LAC POSMAX
ELSE, LOAD THE VALUE WITH THE
SACL SAMPLE
LARGEST POSITIVE VALUE IN RANGE
DONE
OUT SAMPLE,PA1; AND SEND IT TO ENCODER
*
CONTINUE CODE HERE

Example 5-36. Sign-Magnitude to Two's-Complement for A-Law Decoding

* THIS ROUTINE CONVERTS A l3-BIT SIGN-MAGNITUDE
* TWO'S-COMPLEMENT NOTATION FOR A-LAW ENCODING.
* LOCATION 1 CONTAINS THE VALUE 1.
*
INPUT

POS

NUMBER TO
MEMORY

IN
SAMPLE,PAl
READ INPUT FROM SERIAL PORT; DECODE
LAC SAMPLE
MOVE INPUT TO ACCUMULATOR
BGEZ POS
IF POSITIVE, THEN SAVE IT
ADD ONE,15
ELSE, DELETE SIGN BIT BY CARRY
SACL SAMPLE
SAVE MAGNITUDE VALUE
ZAC
NEGATE THE INPUT BY
SUB SAMPLE
SUBTRACTING FROM ZERO AND SAVE
SACL SAMPLE
; FULLY EXPANDED LINEAR DATA
CONTINUE CODE HERE

5-45

Software Applications - Application-Oriented Operations

5.6.2 FIR/IIR Filtering
Digital filters are a common requirement for digital signal processing systems.
The filters fall into two basic categories: Finite Impulse Response (FIR) and
Infinite Impulse Response (IIR) filters. For either category of filter, the coefficients of the filter (weighting factors) may be fixed or adapted during the
course of the signal processing. The theory and implementation of digital filters has been presented and discussed in an application report, "Implementation of FIR/IIR Filters with the TMS3201 O/TMS32020," included in the book,
Digital Signal Processing Applications with the TMS320 Family (literature
number SPRA012A).
,
IIR filters benefit from the fast instruction cycle time of the TMS320C1 x. IIR
filters typically require fewer multiply/accumulates. Correspondingly, the
amount of data memory for samples and coefficients is not usually the limiting
factor. Because of sensitivity to quantization of the coefficients themselves,
IIR filters are usually implemented in cascaded second-order sections. This
translates to code consisting of LTD-MPY instruction pairs. Example 5-37
provides an implementation of a second-order IIR filter.

Example 5-37. Implementing an IIR Filter

* THE FOLLOWING EQUATIONS ARE USED TO IMPLEMENT
*
*
x(n)
+ d(n-l)al + d(n-2)a2
den)
*
yen) = d(n)bO + d(n-l)bl + d(n-2)b2
*
*
START IN
XN,PAO ; INPUT NEW VALUE XN
*
*
*
*
*

LAC

XN,15

LT
MPY

DNMl
Al

LTD
MPY

DNM2
A2

APAC
SACH DN,l
ZAC
MPY B2
LTD
MPY

DNMl
Bl

LTD

DN
BO

~PY

APAC
SACH YN,l
OUT YN,PAl

AN IIR FILTER:

; LOAD ACCUMULATOR WITH XN

den)

x(n) + d(n-l)al + d(n-2)a2

yen) = d(n)bO + _,d(n-l)bl + d(n-2)b2
YN IS THE OUTPUT OF THE FILTER

FIR filters also benefit from the fast instruction cycle time. In addition, an FIR
filter requires many more multiply/accumulates than does the IIR filter with
equivalent sharpness at the cutoff frequencies and with distortion and attenuation in the passbands and stopbands. The TMS320C1 x devices help solve
The
this problem by making longer filters feasible to implement.
TMS320C15/E15/C17/E17 has expanded data memory of 256 words, thus
allowing additional coefficients and samples to be stored for longer-length
5-46

Software Applications - Application-Oriented Operations

filters. Example 5-34 provides an implementation of a fourth-order (4 taps)
FIR filter. Each tap consists of a LTD-MPY instruction pair, uses two date
memory locations, and takes two instruction cycles to execute.

Example 5-34. Implementing an FIR Filter

* THE FOLLOWING EQUATION IS USED TO IMPLEMENT AN FIR FILTER:

y(n)=[Ax(n-l)+Cx(n-~)+Dx(n-4)1* 2**-16
*
*
Xl,PAO
INPUT SAMPLE
START IN
ZAC
*
X4
x(n-4)
LT
MPY D
*
LTC X3
ACC=Dx4; x(n-4»=x(n-3)
MPY
C
*
LTD X2
ACC=Dx4+Cx3j x(n-3»=x(n-2)
MPY B
*
LTD Xl
ACC=Dx4+Cx3+Bx2j x(n-2»=x(n-l)
MPY A
*
APAC
ACC=Dx4+Cx3+Bx2+Axl
SACH Y,J.
OUT Y,PA~
OUTPUT RESULTS
STAR'!
B

The implementation of the FIR filter using straightline code was shown in
Example 5-34. For longer-length FIR filters, straightline code may require
larger program memory size. Depenqing on system constraints, the designer
may choose to reduce program memory size by using looped code. However,
straightline code will run much faster than looped versions. The design tradeoff should be carefully considered by the des in /1 engineer.

5.6.3 Adaptive Filtering
With FIR or IIR filtering, the filter coefficients may be fixed or adapted. If the
coefficients are adapted or updated with time, then another factor impacts the
computational capacity. This factor is the requirement to adapt each of the
coeffi.cients, usually with each sample. A means of adapting the coefficient
is the Least-Mean-Square (LMS) algorithm given by the following equation:
bk(i+1) = bk(i) + 28 em x(l-k)
where em = x(j) - y(/)
N-1

and y(j) =

bk xO-k)

k=O

5-47

Software Applications - Application-Oriented Operations

Quantizafion errors in the updated coefficients can be minimized if the result
is obtained by rounding rather than truncating. For each coefficient in the filter
at a given point in time, the factor 2B e(i) is a constant. This factor can then
be computed once and stored in the T register for each of the updates. Thus,
the computational requirement has become one multiply/accumulate plus
rounding. The adaptation of each coefficient is five instructions corresponding to five clock cycles. This is shown in the instruction sequence as follows:
LARK
LARK
LARP
LT

ARO,LASTAP
AR1,COEFFD
ARO
ERRF

POINT TO DATA SAMPLE
POINT TO COEFFICIENTS

MPY
ZALH
APAC
ADD
SACH

*-,AR1

ONE, 15
*+;O,ARO

bO(i+1) = bO (1) + P
ROUND
STORE bO(i+l)

errf

2B*e(i)

2B*e(i)*X(i-O)

Example 5-39 shows a routine to filter a signal and update the coefficients.
The total execution time of the routine is 30 + 7n where n is the filter length.
Data and program memory requirements are 5 + 2n words and 28 + 7n words,
respectively. The filter length for adaptive filters is restricted both by execution
time and memory. There is obviously more processing to be completed per
sample due to the adaptation, and the size of the on-chip data RAM limits the
number of coefficients and data samples that can be stored.
Another routine on adaptive filtering is discussed in the book, Digital Signal
Processing A'pplications with the TMS320 Family (literature number
SPRA012A); see application report, "Digital Voice Echo Canceller with a
TMS32020."

5-48

Software Applications - Application-Oriented Operations

Example 5-39. 32-Tap Adaptive Filter
.title
.def
.def

'ADAPTIVE FILTER'
ADPFIR
X, Y

* THIS 32-TAP ADAPTIVE FILTER USES PAGE 0 FOR COEFFICIENTS
* AND DATA SAMPLES. THE NEWEST INPUT SHOULD BE IN MEMORY
* LOCATION X WHEN CALLED. THE OUTPUT WILL BE IN MEMORY
* LOCATION Y WHEN RETURNED.
*
CONSTANT ONE
ONE
.set 120
BETA
ADAPTATION CONSTANT * 2
.set 121
SIGNAL ERROR
ERR
.set 122
ERRF
ERROR FUNCTION
.set 123
FILTER OUTPUT
Y
.set 124
NEWEST DATA SAMPLE
X
.set 125
FRS TAP .set
32
NEXT NEWEST DATA SAMPLE
OLDEST DATA SAMPLE
LAS TAP .set 63
START OF COEFFICIENT TABLE
COEFFD .set
0
*
* FINITE IMPULSE RESPONSE (FIR) FILTER.

*
ADPFIR

.text
LDPK 0
LARK AR1, COEFFD
LARK ARO, LAS TAP
MPYK 0
LAC ONE,14
LARP ARO

*
* DO 32 TAPS.
*
FIR
LT
MPY
*
LTD
MPY
*
LTD
MPY

LTD
MPY

USE DATA PAGE 0
LOAD POINTER FOR COEFF TABLE
LOAD POINTER FOR DATA SAMPLES
CLEAR THE P REGISTER
LOAD OUTPUT ROUNDING BIT

*-,AR1
*+,ARO

LOAD T- REG WITH OLDEST SAMPLE
MULTIPLY WITH LAST COEFFICIENT

*-,AR1
*+,ARO

LOAD NEXT SAMPLE
MULTIPLY WITH NEXT COEFFICIENT

*-,AR1
*+,ARO

LOAD NEXT SAMPLE
MULTIPLY WITH NEXT COEFFICIENT

*-,AR1
*+,ARO

LOAD LAST SAMPLE
MULTIPLY WITH LAST COEFFICIENT

Y,l

STORE FILTER OUTPUT

Y
X
ERR

ACC = -y(i)
ADD THE NEWEST INPUT
err(i) = x(i) - y(i)

*
APAC
SACH
ZAC
SUB
ADD
SACL

*
*

* LMS ADAPTATION OF FILTER COEFFICIENTS.
LT
MPY
PAC
ADD
SACH
LAC
SACL

ERR
BETA
ONE, 14
ERRF,l

errf(i) = 2*beta*err(i)
ROUND THE RESULT

FRS TAP

INCLUDE NEWEST SAMPLE
5-49

Software Applications - Application-Oriented Operations

*
LARK ARO,LASTAP
LARK ARI,COEFFD

POINT TO DATA SAMPLE
POINT TO COEFFICIENTS

ERRF

KEEP ERRF IN T REGISTER

MPY
ZALH
APAC
ADD
SACH

*-,ARI
*

= 2*beta*err(i)*x(i-31)
b3I(i+l) = b3l(i) + P

*
*
ADAPT

MPY
ZALH
APAC
ADD
SACH
MPY
ZALH
APAC
ADD
SACH

MPY
ZALH
APAC
ADD
SACH
*

ONE,IS
*+,O,ARO
*-,ARI
*
ONE,IS
*+,O,ARO
*-,ARI
*
ONE,IS
*+,O,ARO

*-,ARI
*
ONE,IS
*+,O,ARO

RET

ROUND
STORE b31(i+l)

= 2*beta*err(i)*x(i-30)

b30(i+l) = b30(i) + P
ROUND
STOREb30 (i+l)

= 2*beta*err(i)*x(i-29)
b29(i+l) = b29(i) + P
P

ROUND
STORE b29 (i+l)

= 2*beta*err(i)*x(i-O)
bO(i+l) = bO(i) + P
P

ROUND
STORE bO(i+l)

RETURN TO MAIN PROGRAM

5.6.4 Fast Fourier Transforms (FFT)
Fourier transforms are another important tool often used in digital signal
processing systems. The purpose of the transform is to convert information
from the time domain to the frequency domain. The inverse Fourier transform
converts information back to the time domain from the frequency domain.
Implementations of Fourier transforms that are computationally efficient are
known as Fast Fourier Transforms (FFTs). The theory and implementation of
FFTs has been discussed in the book, DFT/FFT and Convolution Algorithms,
by Burrus and Parks, published by John Wiley and Sons. The book also contains a large number of sample TMS32010 and FORTRAN programs to implement OFT /FFT algorithms, The TMS320C1 x reduces the execution time
of all FFTs by virtue of its single-cycle instruction time.
Example 5-36 consists of some of the macros used in the implementation of
FFTs. Example 5-37 provides the code for an 8-point OIT (decimation in
time) FFT. The code has been structured into a number of macro calls, including a macro for bit reversal.

5-50

Software Applications - Application-Oriented Operations

Example 5-40. FFT Macros
COMBO

*
*

$MACRO R1,I1,R2,I2,R3,I3,R4,I4

CALCULATE PARTIAL TERMS FOR R3, R4, 13, AND 14_

LAC
ADD
SACH
SUB
SACH
LAC
ADD
SACH
SUB
SACH

:R3:,14
:R4:,14
:R3:,1
:R4:,15
:R4:,1
:13:,14
: 14: ,14
: 13: ,1
: 14: ,15
: 14: ,1

;ACC
;ACC
;R3
;ACC
;R4
;ACC
;ACC
;13
;ACC
;14

:=
:=

:=
:=
:=

:=
:=

(1/4) (R3)
(1/4)(R3+R4)
(1/2) (R3+R4) ,
(1/4) (R3+R4)-(1/2) (R4)
(1/2)(R3-R4)
(1/4) (13)
(1/4) (13+I4)
(1/2) (13+I4)
(1/4) (13+I4)-(1/2) (14)
(1/2) (13-14)

* CALCULATE PARTIAL TERMS FOR R2, R4, 12, AND 14_

LAC
ADD
SACH
SUB
ADD
SACH
SUBH
DMOV
SACH
LAC
ADD
SACH
SUB
SUB
SACH
ADDH
SACH

:R1:,14
:R2:,14
:R1:,1
: 13: ,15
: 14: ,15
:R2:
: 14:
:R4:
:R4:
: 11: ,14
: 12: ,14
: 11: ,1
: 12: ,15
: 14: ,15
:12:
:14:
:14:

;ACC
;ACC
;R1
;ACC
;ACC
;R2
;ACC
;14
;R4
;ACC
;ACC
;11
;ACC
;ACC
;12
;ACC
;14

-= (1/4)(Rl)
:=

(1/4) (R1+R2)

:=
:=

(1/4)
(1/4)
(1/4)
(1/4)
R4 =
(1/4)
(1/4)
(1/4)
(1/2)
(1/4)
(1/4)
(1/4)
(1/4)
(1/4)

-= (1/2) (R1+R2)
-=

:=
:=

-=
-=

:=
:=
:=

(R1+R2)-(1/2) (R2)
[(R1-R2)+(13-I4)]
[(R1-R2)+(I3-I4)]
[(R1-R2)-(13-I4)]
(1/2) (R3-R4)
[(R1-R2)-(13-I4)]
(Il)
(Il+I2)
(Il+I2)
(Il+I2)-(1/2) (I2j
[(Il-I2)-(13-I4)]
[(Il-I2)-(I3-I4)]
[(Il-I2)+(I3-I4)]
[(Il-I2)+(13-I4)]

* CALCULATE PARTIAL TERMS FOR R1, R3, 11, AND

*
*
BITREV

LAC
ADD
SACH
SUBH
SACH
LAC
ADD
SACH
SUBH
SACH
$END

:R1:,15
: R3: ,15
:R1:
:R3:
:R3:
: 11:., 15
:13:,15
:11:
: 13:'
: 13:

;ACC
;ACC
;R1
;ACC
;R3
;ACC
;ACC
;11
;ACC
;13

:= (1/4) (R1+R2)

(1/4)
(1/4)
:= (1/4)
:= (1/4)
.= (1/4)
.= (1/4)
:= (1/4)
-= (1/4)
:= (1/4)
:=

[(R1+R2)+(R3+R4)]
[(R1+R2)+(R3+R4)]
[(R1+R2)-(R3+R4)]
[(R1+R2)-(R3+R4)]
(Il+I2)
[(Il+I2)+(I3+I4)]
[(I1+I2)+(13+I4)]
[(I1+I2)-(13+I4)]
[(Il+I2)-(I3+I4)]

*~MACRO FOR INPUT BIT REVERSAL_

$MACRO PR,PI,QR,QI
ZALH
:PR:
ADDS
:QR:
SACL
PR
SACH
QR
ZALH
PI
ADDS
QI
SACL
PI
SACH
QI
$END
5-51

Software Applications - Application-Oriented Operations

*
ZERO
$MACRO PR,PI,QR,QI
*
* CALCULATE Re(P+Q) AND Re(P-Q)
*
:=
LAC
:PR:,15
;ACC
:=
ADD
:QR:. ,15
;ACC
SACH
:PR:
;PR
:=
SUBH
;ACC
:=
:QR:
SACH
-=
:QR:
;QR
*
* CALCULATE Im(P+Q) AND Im(P-Q)
*
:PI:,15
;ACC
-=
LAC
:=
ADD
:QI:,15
;ACC
:=
SACH
:PI:
;PR
:=
SUBH
:QI:
;ACC
:=
SACH
:QI:
;QR
$END
*
PIBY4
$MACRO PR,PI,QR,QI,W
*
;T REG:=
LT
:W:
:=
LAC
:QI: ,14
;ACC
:=
SUB
:QR:,14
;ACC
:=
SACH
:QI:,l
;QI
:=
ADD
:QR: ,15
;ACC
:=
SACH
:QR:,l
iQR
:PR: ,14
;ACC
-=
LAC
;P REG:=
MPY
:QR:
;ACC
:=
APAC
:=
SACH
:PR:,l
;PR
:=
SPAC
;ACC
:=
SPAC
;ACC
:=
SACH
:QR: ,1
;QR
LAC
:PI:,14
;ACC
-=
.MPY
;P REG:=
:QI:
;ACC
:=
APAC
:PI:,l
;PI
:=
SACH
;ACC
-=
SPAC
;ACC
:=
SPAC
:=
SACH
:QI:,l
;QI
$END
*
PIBY2
$MACRO PR,PI,QR,QI
*
* CALCULATE Re(P+jQ) AND Re(P-jQ)
*
:PI: ,15
;ACC
-=
LAC
:=
SUB
:QR:,15
;ACC
:=
SACH
:PI:
;PI
:=
ADDH
;ACC
:QR:
:=
SACH
:QR:
;QR
*
* CALCULATE Im(P+jQ) AND Im(P-jQ)
*

5-52

(1/2)
(1/2)
(1/2)
(1/2)
(1/2)

(PR)
(PR+QR)
(PR+QR)
(PR+QR)-(QR)
(PR-QR)

(1/2)
(1/2)
(1/2)
(1/2)
(1/2)

(PI)
(PI+QI)
(PI+QI)
(PI+QI)-(QI)
(PI-QI)

W=COS(PI/4)=SIN(PI/4)
(1/4)CQI)
(1/4) (QI-QR)
(1/2) (QI-QR)
(1/4) (QI+QR)
(1/2) (QI+QR)
(1/4) (PR)
(1/4) (QI+QR)*W
(1/4) [PR+(QI+QR)*W]
(1/2) [PR+(QI+QR)*W]
(1/4) (PR)
(1/4) [PR-(QI+QR)*W]
(1/2) [PR-(QI+QR)*W]
(1/4) (PI)
(1/4) (QI-QR)*W
(1/4) [PI+(QI-QR)*W]
(1/2) [PI+(QI-QR)*W]
(1/4) (PI)
(1/4) [PI-(QI-QR)*W]
(1/2) [PI-(QI-QR)*W]

(1/2)
(i/2)
(1/2)
(1/2)
(1/2)

(PI)
(PI-QR)
(PI-QR)
(PI-QR)+(QR)
(PI+QR)

Software Applications - Application-Oriented Operations

LAC
:PR:,15
ADD
:QI:,15
SACH
:PR:
SUBH , :QI:
DMOV
:QR:
SACH
:QR:
$END
*
PI3BY4
*

;ACC
;ACC
;PR
;ACC
;QR
;QR

:= (1/2) (PR)

-= (1/2)
(1/2)
-= (1/2)
--> QI
-= (1/2)
:=

(PR+QI)
(PR+QI)
(PR+QI)-(QI)
(PR-QI)

$MACRO PR,PI,QR,QI,W
LT
LAC
SUB
SACH
ADD
SACH
LAC
MPY
APAC
SACH
SPAC
SPAC
MPY
SACH
LAC
SPAC
SACH
APAC
APAC
SACH
$END

:W:
:QI:,14
:QR: ,14
:QI: ,1
:QR: ,15
:QR: ,1
:PR:,14
:QI:
:PR:,1
:QR:
:QR:,1
:.PI: ,14
:PI:,1
:QI:,1

;T REG:=
;ACC
:=
;ACC
:=
:=
;QI
;ACC
:=
:=
;QR
;ACC
-=
;P REG:=
;ACC
-=
;PR
:=
:=
;ACC
;ACC
-=
;P REG:=
-=
;QR
:=
;ACC
;ACC
:=
;PI
-=
:=
;ACC
-=
;ACC
:=
;QI

W=COS(PI/4)=SIN(PI/4)
(1/4)(QI)
(1/4) (QI-QR)
(1/2) (QI-QR)
(1/4) (QI+QR)
(1/2) (QI+QR)
(1/4) (PR)
(1/4) (QI-QR)*W
(1/4) [PR+(QI-QR)*W]
(1/2) [PR+(QI-QR)*W]
(1/4) (PR)
(1/4) [PR-(QI-QR)*W]
(1/4) (QI+QR) *W
(1/2) [PR-(QI-QR)*W]
(1/4) (PI)
(1/4) [PI-(QI+QR)*W]
(1/2) [PI-(QI+QR)*W]
(1/4) (PI)
(1/4) [PI+(QI+QR)*W]
(1/2) [PI+(QI+QR)!Wl

5-53

Software Applications -Application-Oriented Operations

Example 5-41. An 8-Point DIT FFT

* THIS ROUTINE IMPLEMENTS AN'9":POINT D1T FFT. ASSUME THAT

TWIDDLE FACTOR = W VALUE STORED IN MEMORY LOCATION W.

XOR
XOI
X1R
XlI
X2R
X2I
X3R
X3I
X4R
X4I
XSR
XSI
X6R
X6I
X7R
X7I
W
WVALUE

.set
.set
.set
.set
.set
.set
.set
.set
.set
.set
.set
.set
.set
.set
.set
.set
.set
.set

00
01
02
03
04
05
06
07
08
09
10
11

12
13
14
15
16
SA82h

;

VALUE FOR SIN(4S) OR COS(4S)

*
* INITIALIZE FFT PROCESSING. ASSUME TWIDDLE FACTOR
* W VALUE STORED IN MEMORY LOCATION W.

*
FFT

*
*

.text
ROVM
LDPK

; RESET OVERFLOW MODE
; SET DATA PAGE POINTER TO 0

BIT-REVERSED INPUT SAMPLES.
BITREV
BITREV

X1R,X1I,X4R,X4I
X3R,X3I,X6R,X6I

*
* FIRST AND SECOND STAGES COMBINED WITH DIVIDE-BY-4

*
*
*

*
*

5-54

INTERSTAGE SCALING.
COMBO
COMBO

XOR,XOI,XIR,X1I,X2R,X2I,X3R,X3I,
X4R,X4I,XSR,XSI,X6R,X6I,X7R,X7I.

THIRD STAGE WITH DIVIDE-BY-2 INTERSTAGE SCALING.
ZERO
PIBY4
PIBY2
PI3BY4

XOR,XOI,X4R,X4I
X1R,X1I,XSR,XSI,W
X2R,X2I,X6R,X6I
X3R,X3I,X7R,X7I,W

Software Applications - Application-Oriented Operations

5.6.5 PIO Control
Control systems are concerned with regulating a process and achieving a desired behaviour or output from the process. A control system consists of three
main components: sensors, actuators, and a controller. Sensors measure the
behavior of the system. Actuators supply the driving force to ensure the de,ired behaviour. The controller generates actuator commands corresponding
to the error conditions observed by the sensors and the control algorithms
programmed in the controller. The controller typically consists of an analog
or digital processor.
Analog control systems are usually based on fixed components and are not
programmable. They are also limited to using single-purpose characteristics
of the error signal, such as P (proportional), I (integral), and D (derivative)
or their combination. These limitations, along with other disadvantages o.
analog systems such as component aging and temperature drift, are causing
digital control systems to increasingly replace analog systems in most control
applications.
Digital control systems that use a microprocessor/microcontroller are able to
implement more sophisticated algorithms of modern control theory, such as
state models, deadbeat control, state estimation, optimal control, and adaptive
control. Digital control algorithms deal with the processing of digital signals
and are similar to DSP algorithms. The TMS320C1 x instruction set can
therefore be used very effectively in digital control systems.
The most commonly used algorithm in both analog and digital control systems
is the PID (Proportional, Integral, and Derivative) algorithm. The classical PID
algorithm is given by
u(t)

= Kp e(t) +

J edt + Kd de/dt

The PID algorithm must be converted into a digital form for implementation
on a microprocessor. Using a rectangular approximation for the integral, the
PI D algorithm can be approximated as
u(n)

= u(n-1) + K1

e(n) + K2 e(n-1) + K 3 e(n-2)

This algorithm is implemented in Example 5-42.

5-55

Software Applications - AppJication.;.Oriented Operations

Example 5-38. PIO Control
.title
.def

'PID CONTROL'
PID

*
* THIS ROUTINE IMPLEMENTS A PID ALGORITHM.
*
UN
.set 0
OUTPUT OF CONTROLLER
EO
.set 1
LATEST ERROR SAMPLE
El
.set 2
PREVIOUS ERROR SAMPLE
OLDEST ERROR SAMPLE
E2
.set 3
GAIN CONSTANT
Kl
.set 4
GAIN CONSTANT
K2
.set 5
K3
.set 6
GAIN CONSTANT
*
* ASSUME DATA PAGE 0 IS SELECTED.

*
PID

.text
IN
EO,PAO
LAC UN
LT
E2
MPY K2
LTD El
MPY Kl
LTD EO
MPY
KO
APAC
SACH UN,l
OUT UN,PAl

READ NEW ERROR SAMPLE
ACC '" u(n-l)
LOAD T REG WITH OLDEST SAMPLE
P '" K2*e(n-2)
ACC = u(n-l)+K2*e(n-2)
P -= Kl*e (n-,l)
,
ACC = u(n-l)+Kl*e(n-l)+K2*e(n-2)
P = KO*e(n)
ACC = u(n-l)+KO*e(n)+kl*e(n-l)
+K2*e(n-2)
STORE OU'rPUT
SEND IT

The PID loop takes 13 cycles to execute or 2.6 lAS at a 20-MHz clock rate. The'
TMS320 can also be used to implement more sophisticated algorithms such
as state modeling, adaptive control, state estimation, Kalman filtering, and
optimal control. Other functions that can be implemented are noise filtering,
stability analysis, and additional control loops.

5.6.6 Selftest Routines
A selftest program can effectively perform incoming quality verification or be
used as a powerup device verification tool. Texas Instruments has developed
a selftest program to check out the functionality of a TMS320C1 x device before branching to the user code. This program is not intended to provide a
means of logic debug but rather to indicate device pass/fail from which it can
be determined whether or not the TMS320C1 x is still functional.
When designing a DSP device, Texas Instruments runs very thorough patterns
through the logic to test all the stages. In these patterns, worst-case conditions and transitions are forced in order to verify logic design prior to manufacturing. Likewise, the speed and electrical specifications are thoroughly
tested. In production manufacturing, every TMS320C1 x is tested to meet the
functionality, speed, and power specifications of the device before it is
shipped. The drive levels and loading of lines are checked at full speed and
over varying temperature.

5-56

Software Applications - Application-Oriented Operations

The 4.60-word selftest program for the TMS320C1 x exercises most of the
on-chip resources of the device with a minimal amount of external circuitry.
Note that this code is intended for testing on-chip resources and will not exercise the external interface lines.
Example 5-43 contains a small portion of this selftest program, which checks
out the ALU section. The ALU test is designed to validate the basic operation
of the circuit. It consists of a series of subtests to verify addition and subtraction operations of both halves of the 32-bit operation as well as carry and
overflow calculations, absolute value, and SUBC operation. A failure in any
of these tests will set the error code in the accumulator to 100Xh where X is
the number of the subtest that has failed.
Other sections of this selftest check the auxiliary registers, on-chip data RAM,
on-chip program ROM (longitudinal redundancy test), status register and
branches, pre- and post-scaling shifters, multiplier, and the instruction set.
An applications brief is available which discusses the code segments that
comprise the TMS320C1 x selftest program as well as how to link and execute
this code. The applications brief and selftest code are available via the
TMS320 DSP Bulletin Board Service (see Appendix E).

5-57

Software Applications - Application-Oriented Operations
(

Example 5-43. Selftest Routine

*
*
*

THIS PROGRAM EXECUTES AN INTERNAL SELFTEST OF THE TMS320C1X
MICROCOMPUTER ALU. A FAILURE IN ANY OF THESE TESTS WILL SET
THE ERROR CODE IN THE ACCUMULATOR TO 100Xh WHERE X IS THE
NUMBER OF THE SELFTEST THAT HAS FAILED.

*
**

RESET AND INTERRUPT VECTORS.

BEGIN

B
B

START
INTRPT

; RESET SOFT VECTOR
; INTERRUPT SOFT VECTOR

**
*

REQUIRED DATA VALUES FOR TEST PROGRAMS.

PROGRAM INITIALIZATION DP

. word
.word
.word
.word

OFFFFh
OAAAAh
5555h
Oh

RAM
RAM
RAM
RAM

TEST
TEST
TEST
TEST

PATTERN
PATTERN
PATTERN
PATTERN

1
2
3
4

0 AND DISABLE INTERRUPTS.

.text

START
LDPK
DINT

START INITIALIZATION ROUT.INE
START IN ZERO DATA PAGE
DISABLE EXTERNAL INTERRUPTS

*
* ARITHMETIC LOGIC UNIT TEST.
*

ALU

LACK
SACL
LACK
TBLR
ADD
TBLR
ADD
TBLR
ADD
TBLR
LACK
SACL

ALU1

*
*
ALU2

5-58

ZAC
ADDS
AND
OR
SUBS
BZ
LACK
ADD
B
ZALH
ADDH
SACH
ZALH
ABS
SUBH
,
BZ

1
a
4
4
a
5
a
6
a
7
10h
2
5
5

6
4
ALU2
1

i,a

ERROR

5
6
0
0
a
ALU3

GET INCREMENT VALUE
STORE IT IN REGa
POINT ACC TO PATTERNS TABLE
PUT TABLE VALUE IN REG4
INCREMENT TABLE ADDRESS
PUT TABLE VALUE IN REG5
INCREMENT TABLE ADDRESS
PUT TABLE VALUE IN REG6
INCREMENT TABLE ADDRESS
PUT TABLE VALUE IN REG7
SET ERROR,CODE VALUE
STORE CODE IN REG2
CLEAR OUT ACCUMULATOR
ADD IN OAAAAh PATTERN
AND WITH OAAAAh PATTERN
OR WITH 5555h PATTERN
SUBTRACT -1 FROM PATTERN
IF ACC CLEARED, GO TO NEXT TEST
IF NOT, THEN SET TEST 1 CODE
ADD IN ERROR CODE
EXIT TO ERROR ROUTINE
ADD HIGH THE OAAAAh PATTERN
SUBTRACT HIGH THE 5555h PATTERN
SAVE THE VALUE
RESTORE THE VALUE
TAKE ABSOLUTE VALUE
SUBTRACT HIGH 10000h
IF ACC CLEARED, GO TO NEXT TEST

Software Applications - Application-Oriented Operations

*
*

ALU3

*
*
ALU4
*
*

ALU5

*
*

ALU6

LACK
ADD
B

2
2,8
ERROR

IF NOT, THEN SET TEST 2 CODE
ADD IN ERROR CODE
EXIT TO ERROR ROUTINE

LAC
ADD
BZ

4,12
8,12
ALU4

LOAD ACC WITH OFFFFFOOOh PATTERN
ADD 00001000h TO IT
IF ACC CLEARED, GO TO NEXT TEST

LACK
ADD
B

3
2,~

IF NOT, THEN SET TEST 3 CODE
ADD IN ERROR CODE
EXIT TO ERROR ROUTINE

ERROR

ADD
ABS
SUB
BZ

4
8
ALU5

LOAD ACC WITH OFFFFFFFFh PATTERN
TAKE ABSOLUTE VALUE
SUBTRACT 0000000lh
IF ACC CLEARED, GO TO NEXT TEST

LACK
ADD
B

4
2,8
ERROR

IF NOT, THEN SET TEST 4 CODE
ADD IN ERROR CODE
EXIT TO ERROR ROUTINE

LACK
SACL
LACK
SUBC
NOP
SUBC
NOP

40h
0
OFFh
0

GET DIVISOR = 64
SAVE IN REGO
GET DIVIDEND = 255
1ST STAGE OF DIVIDE
REQUIRED NOP
2ND STAGE OF DIVIDE
REQUIRED NOP

SUBC
NOP
SACH
SACL
LACK
XOR
BZ

1
2
3
2
ALU6

16TH STAGE OF DIVIDE
REQUIRED NOP
SAVE REMAINDER
SAVE QUOTIENT
GET QUOTIENT COMPARISON MASK
COMPARE WITH CALCULATED ANSWER
IF ACC CLEARED, GO TO NEXT TEST

LACK
ADD
B

5
2,8
ERROR

IF NOT, THEN SET TEST 5 CODE
ADD IN ERROR CODE
EXIT TO ERROR ROUTINE

LACK
XOR
BZ

3Fh
1
STATUS

GET REMAINDER COMPARISON MASK
COMPARE WITH ANSWER
IF ACC CLEARED, GO TO NEXT TEST

LACK
ADD
B

6
2,8
ERROR

IF NOT, THEN SET TEST 6 CODE
ADD IN ERROR CODE
EXIT TO ERROR ROUTINE

5-59

Software Applications - Application-Oriented

5-60

perations

Section 6

Hardware Applications

Information and examples on interfacing a TMS320C1 x (first-generation
TMS320) digital signal processor with external devices are presented in this
section. The examples given are general enough in nature that they may be
easily adapted to fit a particuiar system requirement.
The following buses, ports, and control signals provide system interface to the
TMS320C1 x processor:
•
•
•
•

12-bit address bus (A11 -AO)
16-bit data bus (D15- DO)
3-bit port address bus
Memory control signals (MC/MP or MC/PM)

•
•
•
•
•
•
•
•
•

Reset (RS)
Interrupt (INT) and branch control (BIO)
Enable signals (DEN, MEN, and WE)
External flag (X F) )
Serial port clock (SCLK)
Serial port receive/transmit channel inputs/outputs (DR/DX)
Serial port framing inputs and output (FSR, FSX, and FR)
Coprocessor port read/write signals (RD/WR)
Coprocessor latch signals (TBLF/RBLE).

Major hardware applications discussed in this section are listed below.
•

Expansion Memory Interface (Section 6.1 on page 6-2)
Program ROM expansion
Data RAM expansion

•

Codec Interface (Section 6.2 on page 6-6)

•

A/D and D/A Interface (Section 6.3 on page 6-8)

•

I/O Ports (Section 6.4 on page 6-10)

•

Coprocessor Interface (Section 6.5 on page 6-11)

•

System Applications (Section 6.6 on page 6-13)
2400 bps modem
Speech synthesis system
Voice store-and-forward message system.

6-1

Hardware Applications - Expansion Memory Interface

6.1 Expansion Memory Interface

•

,
The TMS320C1 x can be interfaced to a wide variety of memory and I/O devices. The TMS3201 O/C1 0 and TMS320C15/E15 devices can be interfaced
to up to 4K words of external program memory. Expansion of program memory is accomplished directly through the use of the MEN (memory enable) and
WE (write enable) control lines, with memory accesses occurring in a single
cycle.
'

6.1.1 Program ROM Expansion
Twelve TMS3201 0 output pins (A11-AO) are available for addressing external
memory. They contain either the buffered outputs of the program counter or
the I/O port address.
Read operations are performed on external memory either during opcode or
operand fetches or during the execution of a TBLR (table read) instruction.
Write operations have no effect on the circuit. When a read operation occurs,
an address is placed on the address bus, and the MEN (memory enable) strobe
is generated by driving MEN low to enable external memory. The instruction
word is then transferred to the TMS3201 0 via the 16-bit data bus.
A memory address being placed on the bus becomes valid following a maximum delay (td1) from the falling edge of CLKOUT. The combined delay of:
td1 + ta(A) + tsu(O)

= minimum cycle time t c(C)

where ta(A) = memory access time of EPROM from address valid
tsu(O) = setup time form data bus valid prior to CLKOUT!
serves as the timing constraint used when calculating tc(C).
When only external program ROM is required, a minimum system can consist
of a TMS320C10/C15 and up to 4K words of external program memory
(TMS27C292), as shown in Figure 6-1~. The MEN signal and the address
(A11-AO) and data (015-00) lines on the TMS320C1 0/C15/E15 are connected directly to the TMS27C292 memories, and no address decoding is required. These memories are a pair of TMS27C292 4K x 8 ROMs by Texas
Instruments, configured in parallel for a direct 16-bit interface to the
TMS320C10/C15/E15.

6-2

Hardware Applications - Expansion Memory Interface

12
TMS320C10/C15
A11-AO

TMS27C292
A10-AO

A10-AO
07-00

MEN

D15-D8'
D7-DO

TMS27C292

<31

r--

07-00

r--

r--< <31

8
8

Figure 6-1. Minimum Program ROM Expansion

An inexpensive system 'with minimal chip-count is possible when using the
TMS320C10-14. The usage of an EPROM, interfaced to a TMS320C1 0-14,
in external program memory allows the implementation of 4K words of nonvolatile program memory along with the added flexibility in reprogramming,
thus, providing for system development, future program expansion, and/or
upgrade modification. Single-cycle memory access using a direct memory interface requires no additional external interface logic.
On the TMS320C1 0-14, td1 with a maximum value of 50 ns and tsu(O) with
a minimum value of 50 ns are both constants; therefore, ta(A) is the only remaining variable used in determining the minimum clock cycle time of the
system. For the circuit shown in Figure 6-2 (with ta(A) = 170 ns), inserting
these values into the equation yields tc(C) min = 270 ns.
In Figure 6-2, a pair of Texas Instruments TMS2732A-17 4K x 8 EPROM
memories are configured in parallel for a direct 16-bit interfacing with
TMS320C10-14. These EPROMs display a 170-ns access time. However,
other EPROMs may be used with access times best suited to a particular application as long as the TMS320C1 0-14 clock frequency has been selected to
allow for the access time of the EPROMs chosen.

6-3

Hardware Applications - Expansion Memory Interface

12
-14

TMS2732A

A11-AO

MEN

E
~
GNpp

A11-AO

,
08-01

015-08
07-00

.,. ., .......... ,
r--

08-01

E
- r---< GNpp

Figure 6-2. EPROM Interface to the TMS320C10-14

Contention for the data bus is not a concern in this memory configuration.
Therefore, the E (chip enable) pin for the EPROM pair has been tied to ground
to avoid unnecessary switching transients that could be induced if the chip
enables were toggled upon memory access.

6.1.2 Data RAM Expansion
No direct memory expansion is provided on 'the TMS320C1 x. However, if
RAM is used for external program memory, this memory can be used to store
data information, accessed using the TBLR and TBLW instructions~ These instructions, however, take three cycles to execute.
If larger memory or faster memory accesses are required, an alternative memory
expansion scheme using I/O ports can be implemented for a TMS320C1 x
device. In this case, additional RAM can be used to supplement internal data
memory, and can be accessed in only two cycles using the IN and OUT instructions. If RAM is to be used for program memory, additional logic must
be included to distinguish between an I/O write (OUT) and a program memory write (TBLW).
Figure \:)-3 provides an example of external data memory expansion: The design consists of up to 16K words of static RAM (IMS1420)., addressed by the
lower 14 bits of a 16-bit counter (74ALS193). In the case of the I MS1420s,
the address of the data to be accessed is loaded into the counter by implementing an OUT instruction to port O. This loads the data bus into the
counters. Memory can then be read from or written to sequentially by doing
an IN or OUT instruction to port 1. The MSB in the counters determines,
whether the memory address is incremented (MSB = 0) or decremented
(MSB = 1) after a read or write of data memory. Memory continues to be
addressed sequentially until new data is, loaded into the counters.

6-4

Hardware Applications - Expansion Memory Interface

16K X 16 DATA RAM
(iMS1420)
(16 UNITS)
(4K
1 70-NS SRAM)

.-----------------------------~LOAD

ADDRESS
COUNTER
(74ALS193)
(4 UNITS)

A13-AO

A15(MSB) fU

~ ~~~

WRITE RAM

):~~~~~~~~;I'III::===================~_----'

+--_R_EA_D_+R1A_M_;;
___

r--p.7~-{-i-~:
. . :-). . .,

f,ii~
3

It
I

WE
DEN 015-00
TMS320C1x

COUNT DOWN

: : ~:~:~:~ ~:~: :

:::::::::::::::::::::II!ii!

PA2-PAO 1-----'

Figure 6-3. Data RAM Expansion

Dynamic memories may also be used; however, these devices may impose
additional constraints on the system designer. For example, some memory
cycle times may not allow consecutive IN/OUT/IN instruction sequences.
Memory refresh must also be considered. Since the TMS320C1 x does not
implement "wait" states, memory refresh must be generated transparent to the
processor.
For additional information regarding interfacing to TMS320C1 x devices, refer
to Digital Signal Processing Applications with the TMS320 Family (literature
number SPRA012A).

6-5

Hardware Applications - Codec Interface

6.2 Codec Interface
In areas of telecommunications, speech processing, and other applications that
require low-cost analog I/O devices, a combo-codec may be useful. A combo-codec consists of nonlinear A/D and D/A converters'with antialiasing and
smoothing filters and data storage registers. For additional information on
combo-codecs, refer to TCM29C13/C14/C16/C17 Combined Single-Chip
PCM Codec and Filter Data Sheet.
The TMS320C17/E17 is capable of direct interface to serial devices such as
combo-codecs, thus reducing chip count and Improving system throughput.
These TMS320 devices can also compand (COMpress and exPAND) a PCM
(Pulse Code Modulation) data stream, acquired by the codec, through the use
of on-chip companding hardware.
Figure 6-4 shows the TMS320C17/E17 interfaced to a TCM29C13 combocodec to demonstrate direct serial-port interface capability. A standalone
full-duplex serial interface is shown, in which the TMS320C17 /E17 provides
the serial clock for bit transmission. The codec is sampled every 125 liS (8-kHz
frequency), at which time an 8-bit PCM byte is exchanged between the two
devices. A second codec can also be interfaced to the TMS320C17 /E17 with
no additional logic or' interconnections since these devices implement two independent serial ports.
Timing for the serial interface system is controlled by the serial-port clock
(SCLK). iSCLK is configured as an output from the TMS320C17/E17, and its
frequency is set to 2.048 MHz (see Section 3.9). A 20.48-MHz crystal is input
to the TMS320 as its system clock. The SCLK frequency is derived from this
system clock by a divide-by-1 0 in the SCLK prescale control logic, initialized
through control register 1. SCLK is connected to CLKR/CLKX on the
TCM29C13 to provide the transmit and receive master clock. CLKSEL on the
codec is tied to Vee to select the 2.048-MHz master clock mode.
Framing pulses are generated by the TMS320C17 /E17 on the FR output pin.
The frequency of these pulses is set to 8 kHz by dividing the serial clock
(SCLK) by 256. This value is also initialized through control register 1. The
short FR framing pulses provide the codec with framing pulses for the fixed
data-rate mode. FR is input to both the FSX and FSR inputs on the codec.
The FR output causes simultaneous transmit and receive operations from the
serial port. The FSX input on the codec causes the device to transmit PCM
data on the next eight consecutive positive transitions of the serial-port clock
(SCLK). The FSR input on the codec causes the device to receive PCM data
on the next eight consecutive negative transitions of the serial-port clock
(SCLK). With this timing, the codec transmits and receives one 8-bit PCM
sample every 125 liS.

6-6

Hardware Applications - Codec Interface

+5 V

VCC"sS

+5 V

MC
MC/PM
2_------'<.<.7--1 FR
FSX .....,1....
FSR

PCM IN

DXO

PCM OUT

DRO

SIGX/ASEL
DCLKR

~
020.48 MHz

CLKR/CLKX ....1'-!-1_ _ _ _ _---'''''--I SCLK

CLKSEL

X2/CLKIN

9
X1

6 V (2.048 MHz)
cc
15 Vcc(f..L-LAW)
7 V BB (FIXED RATE)

TCM29C13

TMS320C171E17

Figure 6-4. Codec Interface for Standalone Serial Operation

The TMS320C17 /E17 transmits its PCM sample via the DXO pin. The sample
is received by the TCM29C13 on the PCM IN pin. The TMS320 receives PCM
samples on its ORO pin, which is the output of the PCM OUT pin of the
TCM29C13. With this setup, single-channel operation is realized with the
TMS320C17/E17. All data transmission occurs on channel 0, requiring one
IN instruction from port 1 to receive the PCM sample and one OUT instruction
to port 1 to send a sample to the codec ..
In the serial interface configuration, 1.1-255 law companding is selected by
setting system control register bit 14 (CR14) to logic O. The TCM29C13 is
put into the Il-Iaw companding mode by connecting the SIGX/ASEL pin to

Vee·
Linear A/D and D/A converters may also be interfaced to the
TMS320C17/E17 through its parallel ports instead of using the serial port.

6-7

Hardware Applications - AID and DIA Interface

6.3 AID and DIA Interface
The TMS320C10/C15/E15/C17/E17 can' be interfaced to AID (analog-todigital) and D/A (digital-to-analog) converters to perform the necessary conversions. A minimum of external circuitry is required.
,Figure 6-5 shows an interface of the TLC0820 8-bit AID converter to the
TMS320C10/C15/E15/C17/E17. Since the control circuitry of the TLC0820
operates much more slowly than the TMS320C10/C15/E15/C17/E17, it
cannot be directly interfaced. All of the logic functions are implemented with
one each of the following devices from the 74ALS family of Advanced Lowpower Schottky Logic:
12-bit address comparator
Dual positive edge-triggered D-type flip-flops
Octal buffer with three-state output
Quad two-input OR-gate.

74ALS679
74LS74
74ALS465
74LS32

TMS320C10/C15/C17

rei
.A.11-AO

'+5 V

74ALS679

P3 ----<
P2 f----<
P1 f----<
PO r---

A12-A1
74ALS465

TLC0620
MODE

G1
G2
YB

DEN
07
06
05
04
03
02
01
DO

Y6
Y5
Y4
Y3
Y2

VIN

AB
A7
A6
A5
A4

A3
A2
A1

07
De
D5

04
03
D2

01
00

,
I

1}>-

74LS74

=- Vref .JL . where D = digital Input
256

Figure 6-6. D/A Converter to TMS320C10/C15/E15/C17/E17 Interface

For further information about the A/D and D/A converters shown in the figures, refer to Linear Circuits Data Book (literature number SL YD001 ).

6-9

Hardware Applications - I/O Ports

6.4 1/0 Ports
The TMS320C1 x devices interface to input/output (I/O) devices through the
eight 16-bit parallel ports (see Section 3.7 for I/O functions). The I/O space
is selected by the DEN signal for reads and the WE signal for writes. Each of the
eight I/O ports is addressed by the three LSBs of the address bus vyith all other
address lines held low. The I/O ports share the 16 data lines.
The I/O ports may be used for interfacing external circuitry such as data
memory expansion devices (see Section 6.1), A/D and D/A converters, synchronization latches, or memory-mapped peripheral devices. Figure 6-7
shows a circuit that can be used to generate device select lines for each of the
individual port writes. A similar circuit may be used to enable I/O port reads.

TMS320Cl0
WE

PAO
PAl
PA2

~7{;04
2
1
40

74AS137
4

1
?

A
B

3 C
Vcc-iL .G1
5 G2

YO
Y1

.15
.14

.13
.12
Y4 11
Y5 10
YB 9
Y7 7
Y2

1/0

DEVICE

Figure 6-7. I/O Port Interface Circuit

When interfacing the TMS320C1 x to slower devices, a handshake interface
used in conjunction with the I/O port interface may be desirable. Data to be
transferred may be stored in latches to be read by the TMS320C1 x at a later
time. Handshaking may then be established using the interrupt, BIO, and XF
(TMS320C17/E17) signals.

6-10

Hardware Applications - Coprocessor Interfa;e

6.5 Coprocessor Interface
The TMS320C17 /E17 includes an option to use the parallel I/O interface exclusively as a coprocessor interface. This option includes both the buffer logic
to communicate between two processors asynchronously, and the protocol
logic to protect against poor communication. This port allows the
TMS320C17/E17 to act as either a master processor or a slave processor in a
multiprocessing system. The circuit also allows data to be transferred as either
8 or 16-bit values.
As a master processor, the TMS320C17 /E17 writes to and reads from the coprocessor interface at will. This requires that the slave processor keep the receive buffer full and the transmit buffer empty. Figure 6-8 shows the
TMS320C17 as a master processor to a TMS70C42 (8-bit microcomputer).
As the internal CPU writes to the coprocessor interface, the TBLF (transmit
buffer latch full) signal is driven active low. This signals the TMS70C42 that
there is data to be read and that the 8-bit microcomputer must read that data
before the next write by the internal CPU. In Figure 6-8, the TBLF signal is tied
to an I/O bit on the 8-bit microcomputer so that the microcomputer can poll
the signal and act accordingly. This signal could also be tied to an interrupt
on the 8-bit microcomputer if this better suited system requirements. When the
internal CPU reads its buffer, it signals the 8-bit microcomputer that the read
buffer is empty by generating the RBLE (read buffer latch empty) signal. This
signals the microcomputer that it must reload the receive latch before the next
internal CPU access.

TMS320C17/E17
Me
MC/PM
HI/LO
CLKOUT

3
27
2
6

TMS70C42

1
I

.J,.

XTAL2

WR
RBLE

31
1

7
6

A1
AO

32
40

A3
A2

TBLF
LD7
LOS
L05
LD4
L03
L02
L01
LOO

J9_

20
21
22
23
24
25
26

19_ 07

20
21
22
23
24
26
27

06
05
04
03
02
01
DO

Figure 6-8. TMS320C17/E17 to TMS70C42 Interface

6-11

Hardware Applications - Coprocessor Interface

When the TMS320C17/E17 serves as a slave pr()cessor, transfer of data is
controlled by a master processor. Figure 6-9 shows how TMS320C17/E17
(slave) interfaces with the 16-bit microprocessor TMS320C25 (master).
When TMS320C25 writes to TMS320C17/E17, an interrupt signal is sent
from the master to the internal CPU of the slave. The CPU must then read the
information stored· in the coprocessor interface before the next write from the
TMS320C25. When the TMS320C25 reads the transfer latch of the coprocessor port, the internal CPU of, the slve receives an active low 810 signal.
When transferring info(mation to the master processor, the internal CPU
monitors the 810 line (using the BlaZ instruction) to determine when it can
reload the transmit latch. Note that a wait state may be required when interfacing to the TMS320C25.
To support mixed 8/16-bit operation, the read buffer latch is cleared to 0 when
read by the internal CPU.

TMS320C17/E17

TMS320C25

MSC
READY
RtW

~
-L
~

-J

INT1
INT2

DO
01
02

TBLF
RBLE
MC
MC/PM
HI/LO
DO

01
02

04
05

04
05
06
07
08

07
08
09
010
011
012
013
014
015

010
011
012
013
014
015

Figure 6-9. TMS320C17/E17 to TMS320C25 Interface

6-12

Hardware Applications - System Applications

6.6 System Applications
The TMS320C1 x devices are commonly used in many system applications.
Several of these system applications are presented in this section, in a general
form, to illustrate basic approaches to system design using the TMS320C1 x.
These applications include a 2400 bps modem, a speech synthesis system, and
a voice store-and-forward message center.

6.6.1 2400 bps Modem
The impl~mentation of a 2400 bps modem is shown in Figure 6-10. This system implements the functions of a V.22 bis modem using a TMS320A2400
and a TMS70A2400, which are masked ROM versions of the TMS320C17 and
TMS7042, respectively. The TMS320A2400 performs all of the signal processing functions, and the TMS70A2400 performs all of the interface protocol
and control functions. The remaining system components perform the necessary analog-to-digital (A/D) and digital-to-analog (D/A) conversions as well
as the PC bus interfacing, telephone line interfacing, and filtering functions.

PCM OUT

HOST VF
8250 UART
"::I!!S:~liW8::.

SERIAL
I/O

SN74ALS245
AND
SN74ALS30

T
M
S
7
0
A
2
4
0
0

N
T
R

0
L
L
E
R

::::W./.'j:r:f.i::~:::·

T
M
S
3
2
0
A
2

PCM IN

TCM29C13
CODEC

0
S
P

0
"I

..-

S35212A
BANDPASS
FILTER

SN74AS169
RS-232
I/F
(OPTIONAL)

04--------

ANALOG
I/O
CONTROL

TELEPHONE
LINE VF
(OM)

f-- TELCO

Figure 6-10. 2400 bps Modem

6-13

Hardware Applications - System Applications

6~6.2 Speech Synthesis System
The system design for speech applications consists of a cOdec, a digital signal
processor supported vvith program and data memory, a speech data memory,
and an optional host processor. A block diagram of this system, shown in
Figur~ 6-11, consists of the following components:
.
•
•
•
•

Codec (TCM29C18)
Digital signal processor (TMS320C17)
Speech data ROM (TSP60C20) or EPROM (TMS27C56)
Microcomputer host (TMS70C42).

The actual speech system is composed of the digital signal processor and the
codec. The microcomputer host is used to perform an end-product application
that calls upon the speech subsystem when needed, such as in the case of a
minicomputer and array processor system. The speech system can be used to
perform speech synthesis, vocoding, speech recognition, speaker verification,
and DTMF decoding/encoding as well as many other algorithmically intensive
applications.

DISPLAY
HOST I~
CPU I~

TMS320C17"-----r-

CODEC
TCM29C18

KEYBOARD

I
INTERFACE

SPEECH
DATA ROMS
TSP60C20
OR
EPROMS
TMS27C56

. Figure 6-11. Speech Synthesis System

6-14

_ANALOG
"---INPUT/OUTPur

Hardware Applications - System Applications

6.6.3 Voice Store-and-Forward Message Center
The voice store-and-forward message center consists of a TMS320C17 -based
system interfaced to a phone line and a large storage area either on DRAMs
or computer disks depending on the application. Some applications of the
message center are: voice mail for a computer network, answering machines
for home use (see Figure 6-12), and a hand-held battery-operated voice
message pad for personal use. Typical algorithms required to perform the task
are: half-duplex ADPCM or sub-band coder, LPC synthesis, and DTMF
encoder/decoder. A combination of these algorithms will fit into the 4K onchip program ROM of the TMS320C17, requiring no external data memory.
Because the CPU utilization is less than 100 percent when performing any of
these tasks, other operations can also be done by the TMS320C17, such as
digital volume control, noise filtering, etc. A masked ROM version of the
TMS320C17 can provide a cost-effective solution.
CONTROL
SWITCHES

•

TMS320C17

TCM29C18
CODEC

28-PIN
ASIC

LED
DISPLAY

TELEP HONE
LI NE

DRAM

x TMS4256
Figure 6-12. Answering Machine

6-15

Hardware Applications - System Applications

"
6-16

TMS320 FIRST·GENERATION
DIGITAL SIGNAL PROCESSORS
JANUARY 1987-REVISED MAY 1989

TMS32010. TMS320C10

•

160-ns Instruction Cycle

•

144/256-Word On-Chip Data RAM

N PACKAGE
(TOPVIEWI

•

1.5K/4K-Word On-Chip Program ROM

•

4K-Word On-chip Program EPROM
(TMS320E15/E17)

•

EPROM Code Protection for Copyright
Security

•

4K-Word Total External Memory at Full
Speed

•

32-Bit ALU/Accumulator

•

16" 16-Bit Multiplier with a 32-Bit Product

•

0 to 16-Bit Barrel Shifter

•

Eight Input and Eight Output Channels

•

Dual-Channel Serial Port (TMS320C17/E17)

•

16-Bit Bidirectional Data Bus with 50-Mbps
Transfer Rate

•

Single 5-V Supply

•

Packaging: 40-Pin DIP. 44-Lead PLCC. and
44-Lead CER-QUAD

•

Commercial and Military Versions Available

A11PA1
AOIPAO
MC/MP
RS
INT
ClKOUT
X1
X2/ClKIN
BIO
VSS
08
09
010
011
012
013
014
015
07
06

A21PA2
A3
A4
A5
A6
A7
A8
MEN
DEN
WE
VCC
A9
A10
A11
DO
01
02
03
04
05

• 'NMOS Technology:
- TMS32010 ......... 200-ns cycle time
•

CMOS Technology:
- TMS320C10 ..........• 2oo-ns cycle
- TMS320C10-14 ......... 280-ns cycle
- TMS320C10-25 .......•. 160-ns cycle
- TMS320C15 ........... 200-ns cycle
- TMS320C15-25 ......... 160-ns cycle
- TMS320E15 (EPROM) .... 200-ns cycle
- TMS320E15-25 (EPROM) .. 160-ns cycle
- TMS320C17 ........... 200-ns cycle
- TMS320E17 (EPROM) .... 200-ns cycle

time
time
time
time
time
time
time
time
time

This data sheet provides complete design documentation for all the first-generation devices of the TMS320
family. This facilitates the selection of the devices best suited for user applications by providing all
specifications and special features for each TMS320 member. This data sheet is divided into four major
sections: architecture; electrical specifications (NMOS and CMOS). timing diagrams. and mechanical data.
In each of these sections. generic information is presented first. followed by specific device information.
An index is provided for quick reference to specific information about a device.

PROIWCTIOI DATA _ _ collllin inIunnotI..
••mlt II of p.bliCltion
III opocIIICItiIao par Ibo _

Pndlcll conte...
If T_lan_

_""'" ......nty. P~.ctiDn . . - .•• " - nul

.-rI1, IjIChuIe Inti...,

In PI''-.

TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

A-1

TMS32.0 FIRST·GENERATION
DEVICES

description
The TMS320 family of 16/32-bit single-chip digital signal processors combines the flexibility of a highspeed controller with the numerical capability of an array processor, thereby offering an inexpensive
alternative to multichip bit-slice processors. The highly paralleled architecture and efficient instruction set
provide speed and flexibility to produce a MOS microprocessor family capable of executing 6.4 MIPS (million
instructions per second). The TMS320 family optimizes speed by implementing functions in hardware that
other processors implement through microcode or software. This hardware-intensive approach provides
the design engineer with processing power previously unavailable on a single chip.
The TMS320 family consists af two generations of digital signal processors. The first generation contains
the TMS32010 and its spinoffs, as described in this data sheet. The TMS32020 and TMS320C25 are
the second-generation processors, designed for higher performance. Many features are common among
Ithe TMS320 processors. Specific features are added in each processor to provide different cost/performance
tradeoffs. Software compatibility is maintained throughout the family to protect the user's investment
in architecture. Each processor has software and hardware tools to facilitate rapid design.

introduction
The TMS32010, the first NMOS digital signal processor in the TMS320 family, was introduced in 1983.
Its pbwerful instruction set, inherent flexibility, high-speed number-crunching capabilities, and innovative
architecture have made this high-performance, cost-effective processor the ideal. solution to many
telecommunications, computer, commercial, industrial, and military applications. Since that time, the
TMS320C10, a low-power CMOS version of the industry-standard TMS3201 0, and other spinoff devices
have been added to the first generation of the TMS320 family.
The TMS32010 microprocessor executes at 20 MHz or 5 MIPS. It is capable of executing a 16 x 16-bit
multiply with a 32-bit result in a single instruction cycle. On-chip data RAM of 144 words and on-chip
progtam ROM of 1.5K words are available. Fun-speed execution of 4K words of off-chip program memory
is also possible.
The TMS32OC10 is object-code and pin-for-pin compatible with the TMS32010. It is processed in CMOS
technology; achieving a power dissipjltion less than one-sixth that of the NMOS device. The lower power
dissipation makes the TMS320C1 01deal for power-sensitive applications such as digital telephony and
ponable products. The TMS320C1 0-25, a 25-MHz version of the TMS320C1 0, has a 160-ns instruction
cycle time and is well suited for high-performance DSP applications. The TMS320C10 is also available
in a 280-ns version, the TMS320C1 0-14. This device provides a low-cost alternative for DSP applications
not requiring the maximum operating frequency of the TMS320C10.
The TMS320C15 and TMS320E15 CMOS devices are object-code and pin-for-pin compatible with the
TMS32010 and offer expanded on-chip RAM of 256 words and on-chip program ROM or EPROM of 4K
words. These devices allow the capability of upgrading performance and reducing power, board space,
and system cost without hardware redesign. The TMS320C15/E15 are available in 160-ns versions, the
TMS320C 15-25 and TMS320E 15-25.

A-2

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TMS320 FIRST·GEIERATIOI
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introduction (continued)
The TMS320C17 and TMS320E17 also offer expanded on-chip RAM of 256 words and on-chip program
ROM or EPROM of 4K words. These devices provide a dual-channel serial interface, on-chip ,.-Iaw/A-Iaw
companding hardware, and a serial port timer. In addition, a l6-bit coprocessor interface provides a direct
communication channel to common 4/8-bit microcomputers (no glue logic required), and minimal logic
interface to most common l6/32-bit microprocessors. The devices are object-code compatible with the
TMS32010 and processed in CMOS technology.
'
Table 1 provides an overview of the first generation of TMS320 processors with comparisons of memory,
I/O, cycle timing, power, package type, technology, and military support. For specific availability, contact
the nearest TI Field Sales Office.
TABLE 1. TMS320 FIRST-GENERATION DEVICE OVERVIEW
MEMORY
ON-CHIP
OFF-CHIP
RAM ROM EPROM EXPANSION SER

DEVICE
TMS32010§

(NMOS)

144

1.5K

TMS32OC10§
TMS320Cl0-14
TMS32OC10-25

(CMOS)
(CMOS)
(CMOS)

144
144
144

1.5K
1.5K
1.5K

TMS32OC14'
TMS320E14'

(CMOS)
(CMOS)

256
256

TMS32OC15'
TMS32OC15-25

(CMOS)
(CMOS).
(CMOS)
(CMOS)
(CMOS)
(CMOS)

256
256
256
256
256
256

4K
4K

TMS320E15'
TMS320E15-25
TMS32OC17
TMS320E17

lIot
PAR

8 x 16

8 x 16
8 x 16
8 x 16

4K
4K

1
1

7 x 16
7 x 16

4K
4K
4K
4K

2
2

8
8
8
8
6
6

4K
4K
4K
4K

x
x
x
x
x
x

CYCLE
TYP
PACKAGE
TIME POWER
TYPE*
(ns)
(mW) DIP PLCC CER-QUAD
CPX

16
16 16 16 16 YES
16 YES

200

900

200
280
160

165
140
200

40
40
40

44
44
44

160
160

200
160
200
160
200
200

225
250
275
325
250
275

40
40
40
40
40
40

44
44

t SER = serial; PAR = paraliel; CPX = coprocessor interface.

*DIP
= dual in-line pin; PLCC = plastic-leaded chip carrier;
CER-QUAD = surface mount ceramic-leaded chip carrier.

§ Militarv version available.
, Mifitarv version planned; contact nearest TI Field Sales Office for availability.

A-3
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TMS320 FIRST·GENERATION
DEVICES

Key Features: TMS32010/C10
•

Instruction Cycle Timing:
- 160 ns ITMS320C10·25)
- 200 ns ITMS32010/C10)
. - 280 ns ITMS320C10·14)

+.5V

GND

•

144 Words of On·Chip Data RAM

•

1.5K Words of On·Chlp Program ROM

•

Extemal Memory Expansion up to 4K Words at
Full Speed

•

16 x 16-Blt Multiplier with 32·Blt Product

•

0 to 16·Blt Barral Shifter

INTERRUPT

•

On·Chip Clock Oscillator

•

Single 5·V Supply

•

Device Packaging:
- 4O·Pln DIP lall devices)
- 44·Lead PlCC ICMOS only)

•

Technology
- NMOS: TMS32010
- CMOS: TMS320C10/C10·14/C10·25

144-WORD RAM

DATA (16)

)
1.5K·WORD ROM

cr"L

32·BIT ALU/ACC
ADDRESS (12)
MULTIPLIER

)
SHIFTERS

Key Features: TMS320C15/E15

A·4

•

Instruction Cycle Timing:
- 160 ns ITMS320C15·25/E15·25)
- 200 ns ITMS320C15/E15)

•

256 Words of On·Chip Data RAM

•

4K Words of On·Chlp Program ROM
ITMS320C15/C15·25)

•

4K Words of On·Chlp Program EPROM
ITMS320E15/E15·25)

•

EPROM Code Protection for Copyright Security

•

Extemal Memory up to 4K Words at Full Speed

•

Object·Code and Pln·For·Pln Compatible with
TMS32010

+5 V

INTERRUPT

•

16 x 16·BIt Multiplier with 32·BIt Product

•

0 to 16·Blt Barrel Shifter

GND

•

On·Chip Clock Oscillator

•

Single 5·V Supply

•

Device Packaging:
- 4O·Pln DIP lall devices)
- 44·Lead PLCC ITMS320C15/C15·25)
- 44-Leed CER·QUAD ITMS320E15/E15·25)

•

CMOS Technology

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256·WORD RAM

DATA (16)

4K·WORD
ROM/EPROM
32·BIT ALU/ACC
MULTIPLIER

ADDRESS (12)

)
SHIFTERS

TMS320 FIRST·GENERATION
DEVICES

Key Features: TMS320C17/E17
... 5 V

•

Instruction Cycle Timing:
- 200 ns (TMS320C17/E17)

•

256 Words of On-Chip Data RAM

•

4K Words of On-Chip Program ROM
ITMS320C17)

GND

t
INTERRUPT

•

4K Words of On-Chip Program EPROM
ITMS320E17)

•

EPROM Code Protection for Copyright Security

•

Object-Code Compatible with TMS32010

•

Dual-Channel Serial Port for Full-Duplex Serial
Communication

•

Serial Port TImer for Standalone Serial
Communications

•

On-Chip Companding Hardware for ,.-Iaw/A-law
PCM Conversions

•

16-Bit Coprocessor Interface for Common
.4/B/16/32-Bit Microcomputers/Microprocessors

•

Davlca Packaging:
- 4O-Pln DIP lall devices)
- 44-Lead PLCC ITMS320C17)
- 44-Lead CER-QUAD ITMS320E17)

•

CMOS Technoiogy

~
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OR
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DATA 116)

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SERIAL
INTERFACE

COPROCESSOR
INTERFACE
..LAW/A-LAW
HARDWARE

ADDRESS (3)

)

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DUALCHANNEL
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TMS320 FIRST-GENERATION
DEVICES

archhecture
I

The TMS320 family utilizes a modified Harvard architecture for speed and flexibility. In a strict Harvard
architecture, program and data memory lie in two separate spaces, permitting a full overlap of instruction
fetch and execution. The TMS320 family's modification of the Harvard architecture allows transfers
between program and data spaces, thereby increasing the flexibility of the device. This modification permits
coefficients stored in program memory to be read into the RAM, eliminating the need for a separate
coefficient ROM. It also makes available immediate instructions and subroutines based on computed values.
32-bIt ALU/accumulator
The TMS320 first-generation devices contain a 32-bit ALU and accumulator for support of double-precision,
two's-complement arithmetic. The ALU is a general-purpose arithmetic unit that operates on 16-bit words
taken from the data RAM or derived from immediate instructions. In addition to the usual arithmetic
instructions, the ALU can perform Boolean operations, providing .the bit manipulation ability required of
a high-speed controller. The accumulator stores the output from the ALU and is often an input to the ALU.
It operates with a 32-bit wordlength. The accumulator is divided into a high-order word (bits 31 through
16) and a low-order word (bits 15 through 0). Instructions are provided for storing the high- and low-order
accumulator words in memory.
I
shifters
Two shifters are available for manipulating data. The ALU barrel shifter performs a left-shift of 0 to 16
places on data memory words loaded into the ALU. This shifter extends the high-order bit of the data word
and zero-fills the low-order bits for two's-complement arithmetic. The accumulator parallel shifter performs
a left-shift of 0, 1, or 4 places on the entire accumulator and places the resulting high-order accumulator
bits into data RAM. Both shifters are useful for scaling and bit extraction.

16 x 16-blt parallel multiplier
The multiplier performs a 16 x 16-bit two's-complement multiplication with a 32-bit result in a single
instruction cycle. The multiplier consists of three units: the T Register, P Register, and multiplier array.
The 16-bit T Register temporarily stores the multiplicand; the P Register stores the 32-bit product. Multiplier
values either come from the data memory or are derived immediately from the MPYK (multiply immediate)
instruction word. The fast on-chip multiplier allows the device to perform fundamental operations such
as convolution, correlation, and filtering.
data and program memory
Since the TMS320 devices use a Harvard architecture, data and program memory reside in two separate
spaces. The first-generation devices have 144 or 256 words of on-chip data RAM and 1.5K or 4K words
of on-chip program ROM. On-chip program EPROM of 4K words is provided on the TMS320E15/E17. The
EPROM cell utilizes standard PROM programmers and is programmed identically to a 64K CMOS EPROM
(TMS27C64).
'
program memory expension
The first-generation devices are capable of executing up to 4K words of external memory at full speed
for those applications requiring external program memory space. This allows for external RAM-based
systems to provide multiple functionality. The TMS320C 17/E 17 provides no memory expansion capability.

A-6

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microcomputer/microprocessor operating modes (TMS3201 O/C1 O/C15/E15)
The TMS3201 O/C 10 and TMS320C 1 5/E 1 5 devices offer two modes of operation defined by the state
of the MC/MP pin: the microcomputer mode (MC/MP = 1) or the microprocessor mode (MC/MP = 0).
In the microcomputer mode, on-chip ROM is mapped into the memory space with up to 4K words of external
memory available. In the microprocessor mode, all 4K words of memory are external.
interrupts and subroutines
The TMS320 first-generation devices contain a four-level hardware stack for saving the contents of the
program counter during interrupts and subroutine calls. Instructions are available for saving the device's
complete context. PUSH and POP instructions permit a level of nesting restricted only by the amount of
available RAM. The interrupts used in these devices are maskable.
input/output
The 16-bit parallel data bus can be utilized to perform I/O functions in two cycles. The I/O ports are addressed
by the three LSBs on the address lines. In addition, a polling input for bit test and jump operations (BIO)
and an interrupt pin (lNT) have been incorporated for· multitasking.
serial port (TMS320C17/E17)
Two of the I/O ports on the TMS320C17/E17 are dedicated to the serial port and companding hardware.
I/O port 0 is dedicated to control register 0, which controls the serial port, interrupts, and companding
.hardware. I/O port 1 accesses control register 1, as well as both serial port channels, and the companding
hardware. The six remaining I/O ports are available for external parallel interfaces.
The dual-channel serial port is capable of full-duplex serial communication and offers direct interface to
combo-codecs. Receive and transmit registers that operate with 8-bit data samples are I/O-mapped. Either
internal or external framing signals for serial data transfers are selected through the system control register.
The serial port clock provides the bit timing for transfers with the serial port, and may be either an input
or output. A framing pulse signal provides framing pulses for combo-codec circuits, an 8-kHz sample clock
for voice-band systems, or a timer for control applications.
companding hardware (TMS320C17/E17)
On-chip hardware enables the TMS320C17/E17 to compand (COMpress/exPAND) data in either wlaw
or A-law format. The companding logic operation is configured via the system control register. Data may
be companded in either a serial mode for operation on serial port data (converting between linear and
logarithmic PCM) or a parallel mode for computation inside the device. The TMS320C17/E17 allows the
hardware companding logic to operate with either sign-magnitude or two's-complement numbers.
coprocessor port (TMS320C17/E17)
The coprocessor port on the TMS320C17/E17 provides a direct connection to most 4/8-bit microcomputers
and 16/32-bit microprocessors. The port is accessed through I/O port 5 using IN and OUT instructions.
The coprocessor interface allows the device to act as a peripheral (slave) microcomputer to a microprocessor,
or as a master to a peripheral microcomputer. In the microcomputer mode, the 16 data lines are used for
the 6 parallel 16-bit I/O ports. In the coprocessor mode, the 16-bit parallel port is reconfigured to operate
as a 16-bit latched bus interface. For peripheral transfer, an 8-bit or 16-bit length of the coprocessor port
can be selected.

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A-7

1MS320 FIRST·GENERATIOI
DEVICES

instruction 88t
A comprehensive instruction set supports both numeric-intensive op~rations, such as signal processing,
and general-purpose operations, such as high-speed control. All of the first-generation devices are objectcode compatible and use the same 60 instructions. The instruction set consists primarily of single-cycle
single-word instructions, permitting execution rates of more than six million instructions per second. Only
infrequently used branch and 1/0' instruction~ are multicycle. Instruction$ that shift data as part of an
arithmetic operation execute in,a single cyCle and are useful for scaling data in parallel wi~h other operations.
Three main addressing modes are available with the instruction set: direct, indirect, and immediate
addressing.
direct addressing
In direct addressing, seven bits of the instruction word conpatenated with the 1-bit data page pointer form
the data memory address. This implements a paging scheme in which the first page contains 128 words,
'
and the second page contains up to 128 words.
indirect addressing
Indirect addressing forms the data memory address from the least-significant eight bits of one of the two
auxiliary registers,ARO and AR1. The Auxiliary Register Pointer (ARP) selects the current auxiliary register.
The auxiliary registers can be automatically incremented or decremented and the ARP changed in parallel
with the execution of any indirect instruction to permit single-cycle manipulation of data tables. Indirect
addressing can be used with all instructic;ms requiring data operands, except for the immedi.ate operand
instructions.
Immediate addressing
Immediate instructions derive data from part of the instruction word rather than from the data RAM. Some
useful immediate instructions are multiply immediate (MPVK), load accumulator immediate (LACK), and
load auxiliary regi~ter immediate (LARK).
lnatruction set summary
Table 2lists'the symbols and abbreviations used in Table 3, the instruction set summary. Table 3 contains
a short description and the opcode for each TMS320 first-generation instruction. The summary is arranged
according to function and alphabetized Within each functional group.
TABLE 2. INSTRUCTION SYMBOLS
SYMBOL

MEANING
Accumulator
,
Data memory address field
AddresSing mode bit
Immediate operand field
3-bit port eddress field
'·bit operand field specifying auxiliary regiater
4-bit left-shift code
3-bit accumulator left-shift field

ACC
0
I
K
PA

R
5
X

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TABLE 3. TMS320 FIRST·GENERATION INSTRUCTION SET SUMMARY
ACCUMULATOR INSTRUCTIONS

ADD

Add to accumulator with shift

AOOH
ADDS

Add to high-order accumulator bits

Add to accumulator with no sign

LAC

Load accumulator with shift
accumulato~

LACK

Load

OR
SACH

OR with accumulator

CYCLES

WORDS

,
,,
,
,
,
,
,
,
,,
,,

immediate

Store high-order accumulator bits with
shift

SACL

Store low-order accumulator bits

SUB

Subtract from accumulator with shift

SUBC

Conditional subtract (for divide)

SUBH
SUBS

Subtract from high-order accumulator bits
Subtract from accumulator with no sign

OPCODE
INSTRUCTION REGISTER

,,,,,, ,

1
1
1
1
1
1

0
1
0 0 1
0
1
0
1
0
0

,
,
1
1

,
,,

, ,
, , ,
,, , , ,

XOR

Exclusive OR with accumulator
Zero accumulator

ZALH

Zero accumulator and load high-order bits

ZALS

Zero accumulator and load

low~order

bits

1
1
1
1

1
1
1

1
0 c· ; i
0 +-S+ I
1
1
0
1
0 I
0
1 +X+ I

4--0--'
4--0--'
K~

+-0--.
4--0~

0
0
0
0
0

1 0
0 0 0 0
0 0
+-S+
1
0 0
0 0
1
0 0 0
0
0 0 0

0
0
0
0

,,,,
,,, , ,, o , ,
,,
, , , +--0--+
,

extension
ZAC

1514131211109 8 7 6 5 4 3 2 1 0
1
0 0 0
0
0 o 0
0 0 0 0 ~S. I 4--0~
1 0 0 0 0 0 I 4--0~
0
0
0 0 0 0 1 I 4--0~

,
,
,

,
,
,,

,, ,

0 0 0
1
0 0 1 0
1 0 0
0

+-0--+
+--0--'
I +-0--'
I +--0--+
I
I

4--0~

I
I

____

Absolute value of accumulator

extension
AND with accumulator

NO.

ABS

AND

NO.

DESCRIPTION

MNEMONIC

0 0

4---0~

I
I

with no sign extension

AUXILIARY REGISTER AND DATA PAGE POINTER INSTRUCTIONS
MNEMONIC

DESCRIPTION

LAR

Load .auxiliary register

LARK
LARP

Load auxiliary register immediate

LOP

Load data memory page pointer

LOPK

Load data memory page pointer immediate

MAR

Modify auxiliary register and pointer

SAR

Store auxiliary register

Load auxiliary register pointer immediate

NO.

CYCLES

WORDS

,
,
,
,
,
1

,
,
,
,
,

OPCODE
INSTRUCTION REGISTER

,,,
,,,
,, ,
,. o
, , , , , , 4---0----..
,, , ,
o9
,, ,
+--0--+
,,
+--0--.

1514131211109
0 0
0 0
0
0 0 0
0
0
0 0
0
0
1
0
0
0
0
0 0
0 0
0 0 0

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8 7 6 5 4 3 2 1 0
R

4---0~

K--.

0 0 0 0 K

0 0 0
0 I

0 0 0 K

A-9

TMS320 FIRST·GENERATION
DEVICES

TABLE 3. TMS320 FIRST·GENERATION INSTRUCTION SET SUMMARY (CONTINUED)
/

BRANCH INSTRUCTIONS
MNEMONIC

NO.

DESCRIPTION

CYCLES

NO.
WORDS

Branch unconditionally

BANZ

Branch on auxiliary register not zero

BGEZ

Branch if accumulator

OPCODE
INSTRUCTION REGISTER

+--

BGZ

Branch if accumulator

BIOZ

Branch on

BlEZ

Branch if accumulator s 0

iiiO = 0

BLZ

Branch if accumulator < 0

BNZ

Branch if accumulator

BV
BZ

Branch on overflow

Branch if accumulator = 0

CALA
CAll

Call subroutine from accumulator
Call subroutine immediately

2
2

1
2

RET

Return from subroutine or interrupt routine

1514131211109 8 7 6 5 4 3
1 1 1 1 1 0 0 1 0 0 0 0 0
0 0 0 0 +-- BRANCH ADDRESS
1 1 1 1 0 1 0 0 0 o 0 0 0
0 0 0 0 +-- BRANCH ADDRESS
1 1 1 1 1 1 0 1 0 0 0 o 0
0 0 0 0
BRANCH
1 1 1 1 1 1 0 0 0 0
0 0 0 0 +-- BRANCH
1 1 1 1 0 1 1 0 0 0
0 0 0 0 +-- BRANCH
1 1 .1 1
0 1 1 0 0

0
1
0
1
0
1
0
1
0
0
1
0
0

2 1 0
o 0 0
--+
0 0 0
--+

000
ADDRESS - - +
0 0 0 0 o 0
ADDRESS--+
0 0 0 0 0 0
ADDRESS - - +

0 0 0 0 o 0
0 0 0 +-- BRANCH ADDRESS--+
1
1 1 0 1 0 0 o 0 0 0 0 o 0
0 0 0
BRANCH ADDRESS--+
1 1 1 1 1 0 0 0 0 0 0 0 0 0
0 0 0 +-- BRANCH ADDRESS
1 1
0 1 0 1 0 0 0 0 000 0
0 0 0 +--- BRANCH ADDRESS--+

+--

1 1 1 1 1 1 1 0 0
+--- BRANCH
1 1 1 1 1 0
1 0 0 0 0 0
0 0 0 +-- BRANCH
1 1 1 1 1
1 1 0

0 0 0
1 1
1

, ,

0 0 0 o 0 0
ADDRESS--+
0 0 1
0 0
0 0 000 0
ADDRESS--+

0 0

1 1 0 1

T REGISTER. P REGISTER. AND MUl TIPL Y INSTRUCTIONS
MNEMONIC

DESCRIPTION

APAC

Add P register to accumulator

lT
lTA

Load T register

lTA combines lT and APAC into one

OPCODE
INSTRUCTION REGISTER
151413121110 9 8 7 6 5 4 3 2 1 0
0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1
0 1 1 0 1 0 1 0 I +--0---+
0 1 1 0 1 1 0 0 I +--0---+

NO.
CYCLES

NO.
WORDS

1
1
1

1 1 0

1 0

1 1 0

1 0 0

1
1

instruction

lTD
MPY

lTD combines IT. APAC, and DMOV into
one instruction
Multiply 'with T register, store product in
P register

MPYK

Multiply T register with immediate
operand; store product in P register

A-10

PAC

Load accumulator from P register

SPAC

Subtract P register from accumulator

+--0---+

+--0---+
K

1 1 1 1 1 1 1 1 0 0 0 1 1 1 0
1 1 1 1 1 1 1 1 0 0 1 0 0 0 0

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TMS320 FIRST·GENERATION
DEVICES

TABLE 3. TMS320 FIRST-GENERATION INSTRUCTION. SET SUMMARY (CONCLUDED)

CONTROL INSTRUCTIONS

MNEMONIC

DESCRIPTION

NO.

CYCLES

WORDS

DINT

Disable interrupt

EINT
lST

Enable interrupt

Load status register

NOP

No operation

POP

POP stack to accumulator

PUSH

PUSH stack from accumulator

ROVM

Reset overflow mode

SOVM

Set overflow mode

SST

Store status register

OPCODE
INSTRUCTION REGISTER

1514131211109
0 1 1 1 1 1 1
0 1 1 1 1 1 1
0 1 1 1 1 0 1
0 1 1 1 1 1 1
0 1 1 1 1 1 1
0 1 1 1 1 1 1
0 1 1 1 1 1 1
0 1 1 1 1 1 1
0 1 1 1 1 1 0

8 7 6 5 4 3 2 1 0
1 1 0 o 0 0 0 0 1
1 1 0 0 0 0 0 1 0
1
1
1

1
1
1

I +-0--+
1 0 0 0 0 0 0 0
1 0 0 1 1 1 0 1
1 0 0 1 1 1 0 0
1 0 0 0 1 0 1 0
1 0 o 0 1 0 1 1
I +--0---+

1/0 AND DATA MEMORY OPERATIONS

MNEMONIC

DESCRIPTION

NO.

CYCLES

WORDS

OPCODE
INSTRUCTION REGISTER

1514131211109 8 7 6 5 4 3 2 1 0
0 1 1 0 1 0 0 1 I +---0---+

OMOV

Copy contents of data memory location
into next higher location

Input data from port

Output data to port

2
3

1
1

0
0
0

1 0

OUT
TalR

Tabl~

read from program memory to data

0 0

4PA.

1 0 0 1
1 1 0 0

4PA.
1 1 1

I
I

+---0--+
+---0--+
+--0--+

+--0--+

RAM
TBlW

Table write from data RAM to program

1 0

memory

oevelopmen, support products
Together, Texas Instruments and its authorized third-party suppliers offer an extensive line of development
support products to assist the user in all aspects of TMS320 first-generation-based design and development.
These products range from development and application software to complete hardware development and
evaluation systems. Table 4 lists the development support products for the first-generation TMS320 devices.
System development may begin with the use of the simulator, evaluation module (EVM), or emulator (XDS),
along with an assemblerllinker. These tools give the TMS320 user various means of evaluation, from
software simulation of the first-generation TMS320s (simulator) to full-speed in-circuit emulation with
hardware and software break point tracing and timing capabilities (XDS).
Software·and hardware can be developed simultaneously by using the macro assembler/linker or simulator
for software development, the XDS for hardware development, and the evaluation module for both software
development and limited hardware development.
Many third-party vendors offer additional development support for the first-generation TMS320s, including
as,sembler/linkers, simulators, high-level languages, applications software, algorithm development tools,
application boards, software development boards, and in-circuit emulators. Refer to the TMS320 Family
Development Support Reference Guide (SPRUO 11 A) for further information about TMS320 development
support products offered by both Texas Instruments and its third-party suppliers.
Additional support for the TMS320 products consists of an extensive library of product and applications
documentation. Three-day DSP design workshops are offered by the TI Regional Technology Centers (ATCs).
These workshops provide insight into the architecture and the instruction set of the first-generation
TMS320s as well as hands-on training with the TMS320 development tools. When technical questions
arise in regard to a TMS320 member, contact Texas Instruments TMS320 Hotline at (713) 274-2320.
Or, keep informed on the latest TI and third-party development support tools by accessing the libraries
of application source code via the DSP Bulletin Board Service (BBS) at (713) 274-2323. The BaS provides
access for the 2400-/1200-/300-bps modems.

TEXAS . "

INSTRUMENTS
POST OFFice BOX 1443 •

HOUSTON, TEXAS ,17001

A-11

TMS320 FIRST·GENERATION
DEVICES

TABLE 4. TMS320 FIRST·GENERATION SOFTWARE AND HARDWARE SUPPORT
SOFTWARE TOOLS
Macro Assembler/Unker
PC/MS-DOS
VAXNMS
VAX ULTRIX
SUN-3 UNIX

PART NUMBER

Simulator
PC/MS-DOS
VAXNMS

TMDS3240811-02
TMDS3240211-08

Digital Filter Design Package (DFDP)
IBM PC PC-DOS

DFDPII8MOO2

DSP Software Library
PC/MS-DOS
VAXNMS

TMDC3240812-12
TMDC3240212-18

TMS320 Bell 212A Modem Software
PC/MS-DOS

TMDX3240813-12

Data Encryption Standard Software
PC/MS-DOS
HARDWARE TOOLS
Evaluation Tools
Evaluation Module (EVM)
Analog Interface Board 1 (AlB 1)
Analog Interface Board 2 (AI82)
EPROM DSP Starter Kit (TMS320E15)

XDS/22 Emulators
TMS320Cl0/C15
TMS320C14
TMS320C17

TMDX3240814-12
PART NUMBER
RTC/EVM320A-03
RTC/EVM320C-06
RTC/AIB320A-06
RTC/EVM320E-15
TMDS3262211
TMDX3262214
TMDX3262217

XDS/22 Upgrade Kits
TMS32010 - TMS320Cl0/C15
TMS320Cl0/C15 - TMS320C14

TMDS3282215
TMDX3285010 and
TMDX3285018
TMDX3285014 and
TMDX3285018

TMS32OC10/C16 - TMS320C17
EPROM Programming Adaptor Sockets
40- to 28-pin (TMS320E15/E17)
I 44- to 28-pin (TMS320E15lE17)
68- to 28-pin (TMS320E14)

RTC/PGM320A-

V
\

A·14

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •

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TMS32010, TMS320C10
TMS320C10-14, TMS320C10-25
TMS320C15, TMS320C15-25, TMS320E15, TMS320E15-25
description

TMS32010. TMS320Cl0
TMS320C1S. TMS320E1S
N/JD PACKAGE
(TOPVIEWI

Since the TMS3201 0 was the first digital signal
processor in the TMS320 family. its architecture
has served as the basis from which firstgeneration spinoff devices have evolved. The
TMS320C10 is a low·power CMOS version of
the TMS32010 and identical to it. The
TMS320C15/E15 is object-code and pin-for-pin
compatible with the TMS32010 and offers
expanded on-chip RAM and ROM or EPROM.

A lIPA 1
AO/PAO
MC/MP
AS

INT
ClKOUT
Xl
X2/ClKIN
BIO

TM832OC10. TMS32OC15. TM8320E15
FN AND FZ PACKAGES
(TOPVIEWI

VSS

e..
I~~~cn~
0

08
09
010
011
012
013
014
015
07
06

I I-zlcn~o;:: cnNM~It)«««««

ClKOUT ~7
Xl ~8
X2/ClKIN
BIO ~10
NC ~11

65432

1 4443424140

08
0.9
010
011
012

A7
AS
37~ MEN
36! DEN
35~ WE
38

VSS

~12

34[ VCC

~13

A2/PA2
A3
A4
A5
A6
A7
AS
MEN
DEN
WE
VCC
A9
Al0
All
DO
01
02
03
04
05

33~ A9

14
15

32
31

Al0
All

30
29

1819202122232425262728
cnM~It)""'000

PIN NOMENCLATURE (TMS32010. TMS320C10. TMS320C15. TMS320E15 t )
NAME
All -AO/PA2-PAO

CLKOUT
D15-DO

15m
INT
MC/ms

QEIiI
NC

1m
VCC
VSS
~
Xl
X2/CLKIN

1/0*
0
I

0
I/O

0
I
I

0
0
I
I
I

0
0
I

DEFINITION
External address bus. I/O port address multiplexed over PA2-PAO.
External pOlling input
System clock output. \4 crystel/ClKIN frequency
16-bit parallel data bus
Data enable for device input deta on D 1 6-DO
External interlupt input
Memory mode select pin. High selects microcomputer mode. Low selects microprocessor mode.
Memory enable indicetes that D15-DO will accept external memory instruction.
No connection
Reset for initializing the device
+5 V supply
Ground
Write enable for device output data on D 1 6-00
Crystel output for internal oscilletor
Crystal input for internal oscillator or external system clock input

tSee EPROM programming section.
*lnputlOutputlHigh-impedance stete.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

A-15

TMS32010. TMS320C10
TMS320C10·14. T.,S320C10·25
TMS320C.15. TMS320C15·25. TMS320E15. TMS320E15·25
functional block diagram (TMS32010, TMS320C10" TMS320C1S, TMS320E1S)
X1
CLKOUT

X2/CLKIN

,---------------------~~----~

m
16

DEN
iAEN
iiO

INSTRUCTION

MC/Wi

ifiIT

.--+---....- ....~~

PROGRAM
ROM/EPROM
(1.5K/4K
WORDS)

......f-+- D15-DO

16
T(16)
16
MULTIPLIER

8
P(32)

ADDRESS

LEGEND:
Ace= Accumulator

DATA RAM
(144/256
WORDS)
DATA

ARP= Auxiliary register pointer
ARO= Auxiliary register 0
AR1 = Auxiliary register 1

A-16

Data page pOinter

PC
P

Program counter

T register

P register

.. TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

TMS320C17. TMS320E17

description
The TMS320C17, like the TMS320C15, has 256 words of on-chip data RAM and 4K words of on-chip
program ROM. The TMS320C17 is object-code compatible with the TMS3201 O. The TMS320C17 provides
a dual-channel serial port and is designed specifically to interface to two combo-codecs. A 16-bit coprocessor
interface is also provided for interfacing to common 4/8/16/32-bit microcomputers/microprocessors.
TMS320C17.TMS320E17
FN AND FZ PACKAGES
ITOPVIEWI

TMS320C17. TMS320E17
N/JD PACKAGE
ITOPVlEWI
PAt/RBLE
PAO/HI/W
MC

XI
X2CLKIN

BiO
NC

vss
DB/LOB
09/l09
D1O/L01Q
Oll/lOll
O12/l012

EXINT
CLKOUT
XI
X2/CLKIN

1 44 4342 41 40

ClKOUT

OXO
SClK
37 ORI

•
"

3'
33
32

DEN/AD
35 WEIWR

VSS
DBILDB
D91LD9
DlDlLOIO

VCC
ORO
XF
3' MCIPM
30 DO/LOO
2. VSS

,.'3
15

01'/LD11

D1 21LD1 2
D131LD13
D141LD14
D15/LD15
D7/LD7
D6/LD6

17
1819202122232425262728

'7
'8
'9
20

PA2/TBLF
FSR
FSX
FR
DXI
DXO
SCLK
DRI
DENIAD
WEIWR
VCC
DRO
XF
MCIPM
DOILDO
D11LD1
D21LD2
D3/LD3
D41LD4
D5/LDS

PIN NOMENCLATURE (TMS320C17, TMS320E17 t )
NAME

am
ClKOUT
DI5/lDI5-DO/LDO

UERiRIl
OR1, ORO
OX1.0XO

mRT
FR

ffi(

MC
MC/PM
PAO/HI/m
PAI/iil!ii:E
PA21fiilJ!

im
SCLK
VCC
VSS

1/0*
I

0
110
110
I
0
I
0
I
I
I
I
110
0
0
I
110
I
I

WE!WR

Xl
X2JCLKIN
XF

0
I

DEFINITION
External polling input
System clock output. % crystallClKIN frequency
16-bit parallel data bus/data lines for coprocessor latch
Data enable for device input data/external read for output latch
Serial-pon receive-channel inputs
Serial-pon transmit-channel outputs
External interrupt input
Internal serial-pon framing output
External serial-pon receive framing input
External serial-pon transmit framing input '
Microcomputer select (must be same state as MC/PM)
Microcomputer/peripheral coprocessor select (must be same state as MC)
110 pon address output/latch byte select pin
110 pon address output/receive buffer latch empty flag
I/O pon address output/transmit buffer latch full flag
Reset for initializing the device
Serial-pon clock
+5 V Supply
Ground
Write enable for device output data/external write for input latch
Crystal output for internal oscillator
Crystal input for internal oscillator or external oscillator system clock input
External-flag output pin

tSee EPROM programming section.
*Input/Output/High-impedance state.

TEXAS •

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

A-17

TMS320C17
TMS320E17

functional block diagram (TMS320C17, TMS320E17)

r'I

MC/iIQ
WR/~

INSTRUCTION

AD/liM
iiiO
lIS

HI/i]!

PROGRAM
ROM/EPROM
I4KWORDSI

RiLE
TliLF_~"L-_ _...J
PA2-PAO

PROGRAM BUS

I
DATA BUS
I
I
I
I
16
I
16
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DATA
I
1256 WORDSI
I
I
DATA
I
I
I
16
I
I
I
16
I
I
DATA BUS
I
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
LEGEND:
ACC - ACCUMULATOR
ARP - AUXILIARY REGISTER POINTER
ARO - AUXILIARY REGISTER 0
AR1 - AUXILIARY REGISTER 1
DP - DATA PAGE POINTER

A-18

PC
P
T
TR
RR

PROGRAM COUNTER
P REGISTER
T REGISTER
TRANSMIT REGISTER
RECEIVE REGISTER

r--;'~~~l===~-'--DRO
L.!!!!.!~!....-r----DR1

TEXAS

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

TMS320C11
TMS320El1

architecture
The TMS320C17 consists of five major functional units: the TMS320C15 microcomputer. a system control
register. a full-duplex dual-channel serial port. companding hardware. and a coprocessor port.
Three of the I/O ports are used by the serial port. companding hardware. and the coprocessor port. Their
operation is determined by the 32 bits of the system control register (see Table 5 for the TMS320C17/E17
control register bit definitions). Control register O. accessed through port O. consists of the lower 16 register
bits (CR15-CRO bit). and is used to control the interrupts. serial port connections. and companding hardware
operation. Port 1 accesses control register 1. consisting of the upper 16 control bits (CR31-CR16). as
well as both serial port channels. the companding hardware. and the coprocessor port channels.
Communication with the control register is via IN and OUT instructions to ports 0 and 1.
Interrupts fully support the TMS320C 17/E 17 serial port interface. Four maskable interrupts (EXINT. FR.
FSX. and FSR) are mapped into I/O port 0 via control register O. When disabled. these interrupts may be
used as single-bit logic inputs polled by software.
serial port
The dual-channel serial port is capable of full-duplex serial communication and offers direct interface to
two combo-codecs. Two receive and two transmit registers are mapped into I/O port 1. and operate with
8-bit data samples. Internal and external framing signals for serial port transfers (MS8 first) are selected
via the system control register. The serial port clock. SCLK. provides the bit timing for transfers with the
serial port. and may be either an input or output. As an input. an external clock provides the timing for
data transfers and framing pulse synchronization. As an output. SClK provides the timing for standalone
serial communication and is derived from the TMS320C17/E17 system clock. X2/ClKIN and system control
register bits CR27-CR24 (see Table 6 for the available divide ratios). The internal framing (FR) pulse
frequency is derived from the serial port clock (SCLK) and system control register bits CR23-CR16. This
framing pulse signal provides framing pulses for combo-codecs. for a sample clock for voice-band systems.
or for a timer used in control applications.
,,-law/A-law companding hardware .
The TMS320C17/E17 features hardware companding logic that can operate in either I'-Iaw or A-law format
with either sign-magnitude or two's-complement numbers. Data may be companded in either a serial mode
for operation on serial port data or a parallel mode for computation inside the device. The companding
logic operation is selected through CR14. No bias is required when operating in two·s-complement. A bias
of 33 is required for sign-magnitude in Wlaw companding. Upon reset. the device is programmed to operate
in sign-magnitude mode. This mode can be changed by modifying control bit 29 (CR29) in control register
1. For further information on companding. see the TCM29C13flCM29C14/TCM29C16flCM29C17
Combined Single-Chip PCM Codec and Filter Data Sheet. and the application report. "Companding Routines
for the TMS32010flMS32020." in the book. Digital Signal Processing Applications with the TMS320
Family (SPRA012A). both documents published by Texas Instruments.
In the serial mode. sign-magnitude linear PCM (13 magnitude bits plus 1 sign bit for I'-Iaw format or 12
magnitude bits plus 1 sign bit for A-law format) is compressed to 8-bit sign-magnitude logarithmic PCM
by the encoder and sent to the transmit register for transmission on an active framing pulse. The decoder
converts 8-bit sign-magnitude log PCM from the serial port receive registers to sign-magnitude linear PCM.
In the parallel mode. the serial port registers are disabled to allow parallel data from internal memory to
be encoded or decoded for computation inside the device. In the parallel encode mode. the encoder is
enabled and a 14-bit sign-magnitude value written to port 1. The encoded value is returned with an IN
instruction from port 1. In the parallel decode mode. the decoder is enabled and an 8-bit sign-magnitude
log PCM value written to port 1. On the successive IN instruction from port 1. the decoded value is returned.
A~ least one instruction should be inserted between an OUT and the successive IN when companding is
performed with two's-complement values.

TEXAS

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 71001

A-19

TMS320C17
TMS320E17

TABLE 5. CONTROL REGISTER CONFIGURATION

- P O R T 1 PORT

FRAME COUNTER MOOULUS

"
y
SERIAL-PORT CONFIGURATION
COMPANOING HAROWARE CONTROL

DESCRIPTION AND CONFIGURATION

BIT

EXINT interrupt flag t

m
m

FR interrupt flag t

INTERRUPT FLAGS

Interrupt flag t
interrupt flag t

EXINT interrupt enable mask. When set to logic I, an interrupt on ~ activates device interrupt circuitry.

Fmi interrupt enable

F§X interrupt enable mask. Same as EXINT control.

interrupt enable mask. Same as EXINT control.
o = port 1 conneqts to either serial-port registers or companding hardware.
1 = port 1 accesses CR31-CR 16.
o = serial-port data transfers controlled by active FR.
External framing enable:
1 = serial-port dat~ transfers controlled by active ~i

TMS3201Q

+5 V
CLKOUT

RESET _ _ _---,
BIO INPUT SIGNAL
IACTIVE LOWI

P
Q

SN74ALS74
TMS32010

L-_--.:..;::...:._ _ _- I

CLKOUT

FIGURE 3. ASYNCHRONOUS INPUT SYNCHRONIZATION CIRCUITS

A-24

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 7700.1

TMS32010

CLOCK CHARACTERISTICS AND TIMING
T~e

TMS32010 can use either its internal oscillator or an external frequency source for a clock.

Intema' clock option
The internal oscillator is enabled by connecting a crystal across X 1 and X2/CLKIN (see Figure 11. The
frequency of CLKOUT is one-fourth the crystal fundamental frequency. The'crystal should be fundamental
mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW,
and be specified at a load capacitance of 20 pF.
PARAMETER

TEST CONDInONS

MIN
6.7

ODC to 70 DC
ODC to 70 DC

Crystal frequency, fx
C1, C2

TMS32010
NOM MAX
20.5
10

UNIT
MHz
pF

extema' clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X 1 left
unconnected. The external frequency injected must conform to the specifications listed in the table below.

switching characteristics over recommended operating conditions
PARAMETER

TEST CONDITIONS

CLKOUT cycle time t

!e(C)
tr(CI
tf(C)
tw(CLI
twlCHI

CLKOUT rise time
CLKOUT fall time
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high

!d(MCCI

Delay time CLKINt to CLKOUT~

TMS32010
NOM MAX
MIN

UNIT

200
10
6
92
90

ns
ns
ns
ns
ns

\95.12
RL = 6250,
CL = 100 pF,
See Figure 2

60*

25*

ttc(C) Is the cycle time of CLKOUT, i.e., 4*!e(MC) (4 times CLKIN cycle time if an external oscillator is used).
*Values derived from characterization data and not tasted.

timing requirements over recommended operating conditions
MIN
48.78

TMS32010
NOM
50

MAX
150

UNIT

tclMC)

Master clock cycle time

tr(MC)

Rise time mastar clock input

, lOt

tf(MC)

Fall time master clock input

lOt

tw(MCP)

Pulse duration master clock

tw(MCL)

Pulse duration mastar clock high, tc(MC) = 50 ns

20t

tw(MCH)

Pulse duration master clock high, !e(MC) = 50 ns

20t

0.525tc (MC) t

0.475tc (MC) t

tValuas derived from characterization data and not tasted.

TEXAS " ,
INSTRUMENTS
POST OFFice BOX 1443 •

HOUSTON. TEXAS 77001

A-25

TMS32010

MEMORY AND PERIPHERAL INTERFACE .TIMING
switching characteristics over recommended operating conditions
TEST
CONDmONS

PARAMETER
Delay time CLKOUn to
address bus valid

tel1

J;;eiij

tel2

Delay time CLKOUn to

tel3

Deley time CLKOUn to J;;eiij

tel4

Delay time CLKOUn to ~~

tel5

Delay time CLKOUn to

tel6

Delay time CLKOUn to WE~

tel7

Delay time CLKOUT~ to WEt
Delay time CLKOUT~ to
data bus OUT valid
Time after CLKOUn that
data bus starts to be driven
Time after CLKOUn that
data bus stops being driven
Data bus OUT valid
after CLKOUn
Address hold time after

tel8
tel9
tel 10
tv

th(A-WMDI

WEt, J;;eiijt

MIN

TMS32010
TYP
MAX

10t

14tc(C)-st

14tc(C)HS

-1O t

14tc(C) -st

timt

14tc(C) + 16

-10t

Y..tc(C)-5 t

Y.. t c(CI+15

-10t
RL = 8250,
CL = 100 pF,
See Figure 2

15
14tc(C) +65

ns
ns
ns
ns
ns
ns
ns
ns

14tc(CI-5t
14tc(C)+30t

ns
ns

14tc(C)-10

or Dmt

UNrr

(see Note 1)
lauIA-MD)

Address bus satup time
prior to J;;eiij~ or DEN~

14tc(CI-45

tValues derived from characterization data and not tfl8t8d.
NOTE 1: Address bus will be valid upon WEt, timt, or gmt.

timing requirements over recommended operating conditions

taulD)
fhlDI
NOTE 2:

A-26
,
.

TEST
CONDITIONS
Setup time data bus valid prior to CLKOUn
Hold time data bus held valid after
(see Note 2)

MIN
RL = 8250,
CL = 100 pF,
See Figure 2

c"'i:i----------

A-43

TMS320 FIRST·GENERATION
DEVICES

TBlR Instruction timing

LEGEND:
1.
2.
3.
4.
6.
6.

TBLR INSTRUCTION PREFETCH
DUMMY PREFETCH
.
DATA FETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VAUD
ADDRESS BUS VAUD

7.
B.
9.
10.
11.
12.

ADDRESS BUS VALID
ADDRESS BUS VALID
INSTRUCTION VALID
INSTRUCTION VALID
DATA INPUT VAUD
INSTRUCTION VALID

TBlW instruction timing
CLKOUT

I
II

A11·AO

'------7
1
I
I
4_)@(.---S----'-)@(_----,-)@(_ _

)@C

.=:::>@(_____

l--'d6--j
~1"-'d7
----------------~~--td-8~~-.v----------le-'d9"1
D15·DO
LEGEND:
1.
2.
3.
4.
6.
6.

A-44

TBLW INSTRUCTION PREFETCH
DUMMY PREFETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
ADDRESS BUS VALID
ADDRESS BUS VALID

7.
8.
9.
10.
11.

ADDRESS BUS VALID
INSTRUCTION VALID
INSTRUCTION VALID
DATA OUTPUT VALID
INSTRUCTION VALID

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TeXAS 77001

~'d10~

TMS320 FIRST·GENERATION
DEVICES

IN instruction timing

CLKOUT

/
\._____ _ _ . . . . J

\_~I

\_~I
I

I
I
A1'-AO

-...II+"

I
I

',"'A-MO)

1~__-1~~::~~~'~'"~10~1
4 8 < ' - -_ _

_ _.....-----1....,1

~ '04

----------------~i

'05--'

I+"-

v~---------------------

I ~
~>-----<~>-----C{J:--_}>------<~~/4-'hIO)

015-DO

LEGEND:

1_
2.
3.
4.

IN INSTRUCTION PREFETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
PERIPHERAL ADDRESS VALID

5.
6.
7.
8.

ADDRESS BUS VALID
INSTRUCTION VALID
DATA INPUT VALID
INSTRUCTION VALID

OUT instruction timing

CLKOUT

~\ ._\ -_

/
-J

\I'--~I
I

\"'--~!
I

I
I

Al1-AO

015·00

LEGEND:

1.
2.
3.
4.

OUT INSTRUCTION PREFETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
PERIPHERAL ADDRESS VALID

5.
6.
7.
8.

ADDRESS BUS VALID
INSTRUCTION VALID
DATA OUTPUT VALID
INSTRUCTION VALID

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

A-45

TMS32010, TMS320C1.
TMS320C10·14, TMS320C10·25, TMS320C15
TMS320E15, TMS320C15·25, TMS320E15·25
reset timing

CLKOUT~
KtSUIRI

,..-f--tsUfRI

------<,S/

\_1
. Ie

! ~~J--------------------------------NOTE EX-!li
-4Jf ~td11

WE
MEN

'dl.'RI~~

OATA SHOWN

~c..C_______________"~D~A~T3A~'N~F~R~D~RDM

015-00

==x

ADDR:~~
NOTES: A.

'wiRI

'PCADORO~PC+1

ADDRESS SU;.S________

AS = PC + 1

D2'--______

A_S_=·_PC_-_O_ _ _ _ _ _

1m foress 15m, ~, and'flm high and places data bus DO through 015 in a high-impedance state. AB outputs (and program
counter) are synchronously cleared to zero after the next complete CLK cycle from Iml.

B. RS must be maintained for a minimum of five clock cycles.
C. Resumption of normal program will commence atter one complete ClK cycle from Imt.
D. Due to the synchronizing action on 1m, time to execute the function can vary dependent upon when
the CLK cycle.
E. Diagram shown is for definition purpose only. ~, ~,and MEN are mutually exclusive.
F. During a write cycle, 1m may produce an Invalid write address.

interrupt timing

CLKOUT

-.J

!-----*tsullNTl

iNf

"UNTI--t

I==--

twllNTl

810 timing
CLKOUT

~
iiiO

I
I

j4-

\ ---_-'I

tsullOI

~
tlllOl--l

A-46

·1

tw(lOI

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

Imt or Iml occur in

TMS320C17
TMS320E17

reset timing

CLKOUT

r-+
--I
~ --""""1\1"-1----~III
'sulRI

\--'suIRI

I. w I R I - - - -..
-t,
Iz-----------~~I----------------------I

I.-

--...j
'diSIRI~""

td11

015·00

SCLK

DX1,DXO

==x:

PC3 ~ 3 LSB OF PC

PA - PORT ADDRESS

PA2-PAO

VALID

K:1!-;______

PC - 0

PC" 1

~"o1

PA_,_P_C_3_,O_ _ _ _

Interrupt timing

CLKOUT

r------'-

IsullNTI

i l i f j ' -......

---

I I
-----.; j+- t d(OX1-CL)

NOTES: G. Data valid on transmit outputs until SCLK rises.
H. The most significant bit is shifted first.

external framing: receive timing

SCLK

tsu(FS)~

~tSU(FS)

'i!

. I
j4-tsu(OR)

OR1. ORO

-./!OIII-Ih(OR)

NOTE H: The most significant bIt is st)ifted first.

TEXAS . "

INSTRUMENTS
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A-49

TMS320C17
TMS320E17

internal framing: variable-data rate

SCLK

Lj. i
I"" ~

I tcI(CH-FRI

-------

TMS320C17
TMS320E17

coprocessor timing: external write to coprocessor port

HI/LOW:I

Jlx

~~
i~~I

I--twlWRLI----.lL _:
:_
_I
r--rtsulHLl
r--rtt.IHLl

1oI1oo1----'tau lWRI - - -..-tl

l4-tw/WRLl -..I
I'
tsulHLI-t---!
!+-i--tt.IHLI

)

1 tt.IWRI

DATA~j-i-----V-A-U-D------.j}---;~

1 taulwRI--r----itt.IWRI

VALID

I
tclIW-AI...j....-..l

~r_--------------~\I~s------~I

""1.-----

--J

Onlv necessarv for
operation of a-bit mode
constructing l6-bit data

coprocessor timing: external read from coprocessor port

ftU~------------------~\I~\--------JJ'

---.I

..
I . _ - - - - o n l v necessary for
operation of a-bit mode
conatructing l6-bit data

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 7100')..

A-51

A-52

TEXAS " ,
INSTRUMENTS
I?OST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

TMS320E15/E15·25
TMS320E17

EPROM PROGRAMMING
absolute maximum ratings over specified temperature range (unless otherwise noted)t
Supply voltage range, Vpp (see Note 1) .................................. - 0.6 V to 14 V
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum·rated conditions for extended periods may affect
device reliability.
NOTE, 1. All voltage values are with respect to GND.

recommended operating conditions
MIN
Vpp

Supply voltage (see Note 2)

NOTE 2:

NOM MAX
12.5 12.75

Vpp can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC + Ipp.
During programming, Vpp must be maintained at 12.5 V (±0.25 V).

electrical characteristics over specified temperature range (unless otherwise noted)
PARAMETER
Vpp supply current
Vpp supply current
Ipp2
(during program pulse)
IpPl

TEST CONDITIONS
Vpp = VCC = 5.5 V
Vpp =

~2.5

MIN Typt

MAX
100

UNIT
p.A
mA

tAli typical values except for ICC are at VCC = 5 V, TA = 25°C.

recommended timing requirements for programming. T A
(see Note 3)
twllPGM)
twlFPGMl
tsu(A)

Initial program pulse duration
Final pulse duration
Address setup time

tsulEl
taulG)

E setup time
G" setup time

!<;Iis(Gl

Output disable time from

IenIG)
tau(D)
tau(VPP)
taulVCCI
Ih(A)
Ih(D)

12.5 V

6 V. Vpp
MIN NOM MAX
1 1.05
0.95
3.B
63
2
2
2

G"
Output enable time from G"

Deta setup time

2
2
2
0
2

Vpp setup time
VCC setup time
Address hold time
Data hold time

UNIT
ms
ms
p.S

,..
p.S

130 t

150 t

ns
p.S
p.S
p.S
p.S
p.S

tValues derived from characterization data and not tested.
NOTES: 3. For all switching characteristics and timing measurements, input pulse levels are 0.40 V to 2.4 V and Vpp = 12.5 V ± 0.25
V during programming.
4. Common test conditions apply for tdis(G) except during programming.

TEXAS

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A-53

TMS320E15/E15·25
TMS320E17

PROGRAMMING THE TMS320E15/E17 EPROM CELL
Each TMS320E 1 5/E 17 d,!vice includes a 4K x l6-bit industry-standard EPROM cell for prototyping. early
field testing. and low-volume production. In conjunction with this EPROM. the TMS320C15/C17 with a
4K-word masked ROM. then. provides more migration paths for cost-effective production.
EPROM adaptor sockets are available that provide pin-to-pin conversions for programming any
TMS320E15/E17 device. One adaptor socket (part number-RTC/PGM320A-06). shown in Figure 7. converts
a 40-pin DIP device into an equivalent 2S-pin device. Another socket (part number RTC/PGM320C-06).
not shown. permits 44- to 2S-pin conversion.

FIGURE 7. EPROM ADAPTOR SOCKET
(40-pln to 2S·pln DIP Conversion)

Key features of the EPROM cell include the normal programming operation as well as verification. The
EPROM cell also includes a code protection feature that allows code to be protected against copyright
violations.
The TMS320E15/E17 EPROM cell is programmed using the same family and device codes as the TMS27C64
SK x S-bit EPROM. The TMS27C64 EPROM series are ultraviolet-light erasable. electrically progral'1mable.
read-only memories. fabricated using HVCMOS technology. They are pin-compatible with existing 2S-pin
ROMs and EPROMs. These EPROMs operate from a single 5-V supply in the read mode; however. a 12.5-V
supply is needed for programming. All programming signals are TTL level. For programming outside the
system. existing EPROM programmers can be used. Locatior;Js may be programmed singly. in blocks. or
at random.
Figure S shows the wiring conversion to program the TMS320E15/E17 using the 2S-pin pinout of the
TMS27C64. The table of pin nomenclature provides a description of the TMS27C64 pins. The code to
be programmed into the device should be in serial mode. The TMS320E15/E17 uses 13 address lines to
address the 4K-word memory in byte format.

A-54

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

TMS320E151E15·25
TMS320E17

-;-;-

Vp
A1 2
A7
A6
A5
A4
A3
A2
A1
Ao
1
2
o3
GN o

o
o

2
3[
4[
5[
6[
7[
8[
9[
10[
11[
12 [
13 [
14

-oJ
-oJ
-oJ
-oJ

§-: --

TMSFc64
PINOUT

1
2
3
4
5
6
[ 7
8
[ 9
10
11
12
13
14
15
16
17
18
19
[ 20

~
~
~

A1
AOllSBI
Vpp
RS
EPT

40
39
38
37
36
35
34
elKIN
33
32
GND
31
01llSBI
30
Vee
02
A9 29
03
A10 28
04
A11 27
05
IMS81A12 26
06
E 25
07
G 24
aslMSBI
PGM 23
22
21
TMS320E15/E17
A2
A3
A4
A5
A6
A7
A8

;=:
;=:
;=:
~
~

""2sV
27 ~~
3.9kO

p--.-

P
P

26
25
24
23
22
21
20
.---:1 19
,..-:1 18
.---:117
,..-:1 16
.---:115

EPT
A8

!.11
G
A 10

E
as
07
06
05
04

TMs27c-6 4
PINOUT

CAUTION
Although acc:eptable by some EPROM programmers. the signature mode cannot be used on any TMS320E1x
device. The slgnagure mode will input a high-level voltage 112.5 Vdc) onto pin AS. Since this pin Is not designed
for high voltage. the cell will be damaged. To prevent an accidental application of voltage. Texas Instruments
has inserted a 3.S kO resistor between pin AS of the TI programmer socket and the programmer Itself.

PIN NOMENCLATURE (TMS320E15/TMS320E17)
NAME
AO-A12
elKIN

E
EPT

G
GND

J5lm
01-08

RS
Vec
Vpp

I/O
I
I
I
I
I
I
I
I/O
I
I
I

DEFINITION
On-chip EPROM programming address lines
Clock oscillator input
EPROM chip select
EPROM test mode select
EPROM read/verify select
Ground
EPROM write/program select
Data lines for byte-wide programming of on-chip 8K bytes of EPROM
Reset for initializing the device
5-V power supply
12.5-V power supply

FIGURE 8. TMS320E15/E17 EPROM PROGRAMMING CONVERSION TO
TMS27C64 EPROM PINOUT

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A·55

TMS320E15/E15·25
TMS320E17

Table 8 shows the programming levels required for programming, verifying, reading, and protecting
the EPROM cell.
TABLE 8. TMS320E15/E17 PROGRAMMING MODELEVELS
SIGNAL NAME

TMS320E16 PIN

TMS27C84 PIN

(PROGRAM

VERIFY

READ

PROTECT VERIFY.

EPROM
PROTECT

VIL

VIH

PULSE

"PUCSE

VIL

VIH

"Pim'

23
3
30
10
8

27
1
28
14
14

PULSE
Vpp

VIH
Vpp
Vee
Vss
vss

VIH
Vee + 1
vee + 1

VIH
Vpp

Vee
Vss
Vss

VIH
Vee
Vee
Vss
Vss

vee + 1

Vss
vss

EPT

4
5

14
26

vss
Vss

Vss
Vss

vss
Vpp

Vss
Vpp

01-08
AO-A3
A4
A5
A6
A7-A9
A10-A12

11-18
2,1,40,39
38
37
36
35,34,29
28-26

11-13,15-19
10-7
6
5
4
3,25,24
21,23,2

DIN
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR

°OUT
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR

GoUT
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR

08 = RBIT
X
X

08 = PULSE
X

X
X
X
X

Vpp
Vee
Vss
eLK",j

JiS

VIL
X

VIH

LEGEND:
VIH = TTL high level; VIL = TTL low level; ADDR = byte address bit
Vpp = 12.5 V ± 0.25 V; Vee = 5 V ± 0.25 v; X = don't care
PULSE = low-going TTL level pulse; DIN = byte to be programmed at ADDR
GoUT = byte stored at ADOR; RBIT = ROM protect bit.

programming..
Since every memory bit in the cell is a logic 1, the programming operation reprograms certain bits to O. Once
programmed, these bits can only be erased using ultraviolet light. The correct bYte is placed on the data bus
with Vpp set to the 12.5-V level. The PGM pin is then pulsed low to program in the zeroes.
erasure
Before programming, the device must be erased by exposing itto ultraviolet light. The recommended minimum
exposure dose (UV-intensity X exposure-time I is 15 watt-seconds per square centimeter. A typical 12 milliwattseconds per square centimeter, filterless UV lamp will erase the device in 21 minutes. The lamp should be located
about 2.5 centimeters above the chip during erasure. After exposure, all bits are in the high state.
verify/read
To verify correct programming, the EPROM cell can be read using either the verify or read line definitions shown
in Table 8, assuming the inhibit bit has not been programmed.
program inhibit
Programming may be inhibited by maintaining a high level input on the E pin or PGM pin.

read
The EPROM contents may be read independent of the programming cycle, provided the RBIT (ROM protect
bit) has not been programmed. The read is accomplished by setting Eto zero and pulsing Glow. The contents
of the EPROM location selected by the value on the address inputs appear on Q8-Q 1.

A-56

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001 '

TMS320E151E15-25
TMS320E17

output disable
During the'EPROM programming process. the EPROM data outputs may be disabled. if desired. by establishing
the output disable state. This state is selected by setting Gand Epins high. While output disable is selected.
OS-01 are placed in the high-impedance state.
EPROM protection
To protect the proprietary algorithms existing in the code programmed on-chip. the ability to read or verify code
from external accesses can be completely disabled. Programming the RBIT disables external access of the
EPROM cell. making it impossible to access the code resident in the EPROM cell. The only way to remove this
protection is to erase the entire EPROM cell. thus removing'the proprietary information. The signal requirements
for programming this bit are shown in Table S. The cell can be determined as protected by verifying the
programming of the RBIT shown in the table.
standard programming procedure
Before programming. the device must first be completely erased. Then the device can be programmed with
the correct code. It is advisable to program unused sections with zeroes as a further security measure. After
the programming is complete. the code programmed into the cell should be verified.lfthe cell passes verification.
the next step is to program the ROM protect bit (RBIT). Once the RBIT programming is verified. an opaque label
should be placed overthe window to protectthe EPROM cell from inadvertent erasure by ambient light. At this
point. the programming is complete. and the device is ready to be placed into its destination circuit.

program cycle timing

,,,

PAOGRAM--;'-VERIFY---1

I
A12-AO

-V
-A

ADDRESS STABLE

:
I

!--t.UIAI--!

08-01

--.f

I -{

DATA IN STA8lE

~!'=----------"Irt--t,u'D'~

HIII-z

"k.tADDRESS N+1 V,H

.f\

~th'AI--j

DA::,l~UT

*1-_____

~td'.'GI

V,l

V,HiVDH
V'liVOl

I
:
7f~---------~--~--~----------vpp

Vpp

-.-I j..t.u,vPP'~
~
t--

Vee

----I--------~--~----------VCC+1

Vee

tSU(VCCI--i

Vee

I
E

~'-___-:-:_____...:..._____-:-_-:-________ ::~

PGM

I
KthlOI

tsufEI----t

V,..-....:i-.

--.I--:L-u-,G-,--:----------- :',:

I.. .,
tw'FPGM'~
twllPGMI

~_.J..I I"
"I len'G'1

I I...

}]"I_ _ _ _ _ _ _ _ :::

T~XAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

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A-57

TMS320C10
TMS320C10·25

TYPICAL POWER VS. FREQUENCY GRAPHS
52

46
<[

E 40
I

:; 34

[ill
§]
~

Vee - 5.5 V
Vee

5.0 V

Vee - 4.5 V

......

~ 28

u
!:} 22

16~--~~~---,dS~~----~~~----+--------r------~------~

10~.-

____

1.2

______

______- L - _ _ _ _ _ _

______

fx-crystal Frequency-MHz
(a)-400e TO 85°e TEMPERATURE RANGE

~J~
'/'1,,,\\.,,.

E
I

~
::I

...

::I

til

u 12

~
1.2

'/'I\\\\O>Sl

!:}

..".

12
fx-erystal

Frequency-MH~

(b) VOLTAGE - 5 V; TEMPERATlJRE = 25°e

FIGURE 9. TYPICAL CMOS ICC VS. FREQUENCY

A-58

TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •

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TMS320 FIRST·GENERATION
DEVICES

PACKAGE TYPES
PACKAGE TYPE

SUFFIX
NMOS:

4O-pin plastic DIP (1 OO-mil pin spacing)

CMOS:

FAMILY MEMBERS
TMS32010
TMS320Cl0, TMS320Cl0-14, TMS320C10-2S,
TMS320C1S, TMS320C1S-2S, TMS320C17

4O-pin windowed ceramic DIP
(100-mil pin spacing)

CMOS:

TMS320E1S, TMS320E1S-2S, TMS320E17

44-lead PLCC (SO-mil pin spacing)

CMOS:

TMS320Cl0, TMS320Cl0-2S,
TMS320C1S, TMS320C1S-2S, TMS320C17

44-leed windowed CER-QUAD
(SO-mil pin spacing)

CMOS:

TMS320E1S, TMS320E1S-2S, TMS320E17

THERMAL DATA
thermal resistance characteristics
IIfJA
°CIW)
Sl.6
84

PACKAGE
40-pin plastic dual-in-line package (NMOS)
40-pin plastic dual-in-line package (CMOS)
4O-pin windowed ceramic dual-in-line package (CMOS)
44-IBed plastic chip carrier package (CMOS)
44-leed CER-QUAD chip carrier package (CMOS)

40
60
63.8

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IIfJc
(OCIW)
16.6
26
8
17
7.8

A-59

TMS320 FIRST-GENERATION
DEVICES

MECHANICAL DATA
40-pin plastic dual-in-line package

} 4 - - - - - - - - 53,1 (2.0901 MAX - - - - - - - - ,

EITHER OR BOTH
INDEX MARKS

o
It

15,24 ± 0,25

~.600±0.010~

tw.o

0,51~~N0201

5,08 (0.2001 MAX

~ ~"-~"4-~J
~
MIN~ ~J'lliL.-. "" <0.""

0,28±0,08-\r(0.011 ± 0.0031

0.457±0,076 --II, 2 , 9 2 (0.1151 MIN
(0.018 ± 0.0031
0,84 (0.0331
PIN SPACING 2,54 (0.1001 T.P.
1 40 (0.0551
(SEE NOTE AI
1,52 (0.0601 NOM
'

=:i

ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0,254 (0.010) of its true longitudinal position.

40-pin windowed ceramic dual-in-line package
14------51,3112.0201 MAX

·,,,,,,~~:~~~IQl:::~:::tI~'

15.24 ± 0.25
10.600 ± 0.0101

----~·RXD/DATA

~~---------~~5

DP-Oate Page Pointer
ACe-Accumulator
ACT -Action Register
ALU-Arithmetic logic Unit
ARP-Auxiliary Register Point
ARO-Auxlliary Register 0
AR1-Auxitiat'Y Register 1 '
85R-Bank Select Register

CAP-Capture
CMPR-Compllre Register

architecture

IOP-lnput!OutpJt Port
(Bit Selectable,

PC-Program Counter
p-p Register
RBR-Recelve Buffer Regist...

RSR - Receiv. Shift Register
T - T Register
TBR- Transmit Buffer Register
TSR- Trenamtt Shift Register

The TMS320 family utilizes a modified Harvard architecture for speed and flexibility. In a strict Hl\lrvard
architecture, program and data memory lie in two separate spaces, permitting a full overlap of instruction
fetch and execution. The TMS320 family's modification of the Harvard architecture allows transfers
between program and data spaces, thereby increasing the flexibility of the device. This modification permits
coefficients stored in program memory to be read into the RAM, eliminating the need for a separate
coefficient ROM. It also makes available immediate instructions and subroutines based on computed values.
32-blt ALU/accumulator
The TMS320C14/E14 devices contain a 32-bit ALU and accumulator for support of double-precision, two'scomplement arithmetic. The ALU is a general-purpose arithmetic unit that operates on 16-bit words taken
from the data RAM or derived from immediate instructions. In addition to the usual arithmetic instructions,
the ALU can perform Boolean operations, providing the bit manipulation ability required of a high-speed
controller. The accumulator stores the output from the ALU and is often an input to the ALU. It operates
with a 32-bit wordlength. The accumulator is divided into a high-order word (bits 31 through 161 and a
low-order word (bits 15 through 01. Instructions are provided for storing the high- and low-order accumulator
'
words in memory.

A-68

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TMS320C14/TMS320E 14
DIGITAL SIGNAL PROCESSOR

shifters
Two shifters are available for manipulating data. The ALU barrel shifter performs a left-shift of 0 to 16
places on data memory words loaded into the ALU. This shifter extends the high-order bit of the data word
and zero-fills the low-order bits for two's-complement arithmetic. The accumulator parallel shifter performs
a left-shift of 0, 1, or 4 places on the entire accumulator and places the resulting high-order accumulator
bits into data RAM. Both shifters are useful for scaling and bit extraction.
16 x 16-blt parallel multiplier
The multiplier performs a 16 x 16-bit two's-complement multiplication with a 32-bit result in a single
instruction cycle. The multiplier consists of three units: the T Register, P Register, and multiplier array.
The 16-bit T Register temporarily stores the multiplicand; the P Register stores the 32-bit product. Multiplier
values either come from the data memory or are derived immediately from the MPYK (multiply immediate)
instruction word. The fast on-chip multiplier allows the device to perform fundamental operations such
as convolution, correlation, and filtering.
data and program memory
Since the TMS320C14/E14 devices use a Harvard architecture, data and program memory reside in two
separate spaces. These devices have 256 words of on-chip data RAM and 4K words of on-chip program
ROM (TMS320C 14) or EPROM (TMS320E 14). The EPROM cell utilizes standard PROM programmers and
is programed identically to a 64K CMOS EPROM (TMS27C64).
program memory expension
The first-generation devices are capable of executing up to 4K words of external memory at full speed
for those applications requiring external program memory space. This allows for external RAM-based
systems to provide multiple functionality.
microcomputer/microprocessor operating modes
The TMS320C 14/E 14 devices offer two modes of operation defined by the state of the NMI/MC/MP pin
during reset: the microcomputer mode (NMIIMC/MP = 1) or the microprocessor mode (NMIIMC/MP = 0).
In the microcomputer mode, on-chip ROM is mapped into the memory space with up to 4K words of intemal
memory available. In the microprocessor mode, all 4K words of memory are external.
Interrupts end subroutines
The TMS320C 14/E 14 devices contain a four-level hardware sta,ck for saving the contents of the program
counter during interrupts and subroutine calls. Instructions are available for saving the complete context
of the device. PUSH and POP instructions permit a level of nesting restricted only by the amount of available
RAM. The TMS320C14/E14 has a total of 16 internal/external interrupts. Fifteen of these are maskable;
NMI is the sixteenth.
input/output
The 16-bit parallel data bus can be utilized to access external peripherals. Only the lower three address
lines are active, however. The upper nine address lines are driven high.

bit I/O
The TMS320C14/E14 has 16 pins of bit 110 that can be individually configured as inputs or outputs. Each
of the pins can be set or cleared without affecting the others. The input pins can also detect and match
p"ff'lrnS and generate a maskable interrupt signal to the CPU.

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A-69

TMS320C14/TMS320E14
DIGITAL SIGNAL PROCESSOR

serial port
The TMS320C14/E14 includes an I/O mapped serial port that can operate in one of three modes:
asynchronous, synchronous, and codec. Two types of inter-processor communication protocols are
supported in all modes. An associated timer provides baud rate/clock generation if required. Depending
on the mode, internal/external clock (master/slave) options are available. All communication parameters
are software-controlled through a serial control register.
event manager
An event manager is included that provides up to four capture inputs and up to six compare outputs. This
peripheral operates with the timers to provide a form of programmable event logging/detection. The six
compare outputs can also be configured to produce six channels of high precision PWM.
timers 1 and 2
Two identical 16-bit timers are provided for general purpose applications. Both timers include a 16-bit period
register and buffer latch, and can generate a maskable interrupt.
serial port timer
The serial port timer is a 16-bit timer primarily intended for baud rate generation for the serial port. Its
architecture is the same as timers 1 and 2, therefore it can serve as a general purpose timer if not needed
for serial communication.
watchdog timer
The TMS32OC14/E14 contains a 16-bit watchdog timer that can produce a timeoutlWDT) signal for various
applications such as software development and event monitoring. The watchdog timer also generates,
at the point of the timeout, a maskable interrupt signal to the CPU.

A-70

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INSTRUMENTS
POST OFFICE BOX 1443 •

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TMS320C14/TMS320E14
DIGITAL SIGNAL PROCESSOR

instruction set
A comprehensive instruction set supports both numeric-intensive operations. such as signal processing.
and general-purpose operations. such as high-speed control. All of the first-generation devices are objectcode compatible and use the same 60 instructions. The instruction set consists primarily of single-cycle
single-word instructions. permitting execution rates of more than six million instructions per second. Only
infrequently used branch and 1/0 instructions are multicycle. Instructions that shift data as part of an
arithmetic operation execute in a single cycle and are useful for scaling data in parallel with other operations.
NOTE
The BIO pin on other TMS320C1x devices are not available for use in the TMS320C14/E14. An
attempt to execute the BIOZ (Branch on BIO low) instruction will result in a two cycle NOP action.
Three main addressing modes are available with the instruction set: direct. indirect. and immediate
addressing.
direct addressing
In direct addressing. seven bits of the instruction word concatenated with the 1-bit data page pointer form
the data memory address. This implements a paging scheme in which each page contains 128 words.
indirect addressing
Indirect addressing forms the data memory address from the least-significant eight bits of one of the two
auxiliary registers. ARO and ARI. The Auxiliary Register Pointer (ARP) selects the current auxiliary register.
The auxiliary registers can be automatically incremented or decremented and the ARP changed in parallel
with the execution of any indirect instruction to permit single-cycle manipulation of data tables. Indirect
addressing can be used with all instructions requiring data operands. except for the immediate operand
instructions.
immediate addressing
Immediate instructions derive data from part of the instruction word rather than from the data RAM. Some
useful immediate instructions are multiply immediate (MPVK). load accumulator immediate (LACK). and
load auxiliary register immediate (LARK).
instruction set summary
Table 1 lists the symbols and abbreviations used in Table 2. the instruction set summary. Table 2 contains
a short description and the opcode for each TMS320 first-generation instruction. The summary is arranged
according to function and alphabetized within each functional group.

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DIGITAL SIGNAL PROCESSOR

TABLE 1. INSTRUCTION SYMBOLS
SYMBOL
ACC

MEANING
Accumulator

D
I
K,

Data memory address field
Addressing mode bit

Immediate operand field
3-bit port address field

R
S
X

1-bit operand field specifying auxiliary register
4-bit left-shift code
3-bit accumulator left-shift field

TABLE 2. TMS320 FIRST-GENERATION INSTRUCTION SET SUMMARY
ACCUMULATOR INSTRUCTIONS
NO.
CYCLES

DESCRIPTION

MNEMONIC

NO.
WORDS

ABS

Absolute value of accumulator

ADD
ADDH
ADDS

Add to accumulator with shift

,
,
,
,
,
,
,

,
,
,
,
,

Add to high-order accumulator bits
Add to accumulator with no sign
extension

AND

AND with accumulator

lAC

Load accumulator with shift

lACK
OR
SACH

OR with accumulator

(

Load accumulator immediate
Store high-order accumulator bits with

OPCODE
INSTRUCTION REGISTER
1514131211109 8 7 6 5 4 3 2 1 0
0 1 1 1 1
0 0 0
0 0 0
0 0 0 0 +-S. I +--D----+

,,,,

0
0

,,
,
,
,

0 0 0 0 0 I
0 0 0 0 T I

,,, ,
,
,,,,,

0
0 0
0 0
0 4--5+
0
0
1 1 0 1 0
0
0 1 0
1 +X.

+--D----+
+--D----+

+--D~

+---D~

K----+

+--o~

+--0----+

+--D----+

+-5.

4--o~

0 1 0 0 I
1 1 0 0 0 1 0 I
1 1 0 0 0 1 1 I

4--D----.
+--D----+

shift
SACl

Store lovy-order accumulator bits

SUB

Subtract from accumulator with shift

SUBC

Conditional subtract (for divide)

SUBH
SUBS

Subtract from high-order accumulator bits

1
1

XOR

Exclusive OR with acc.umulator

ZAC

Zero accumulator

Subtract from accumulator with no sign

extension

ZAlH
, ZAlS

Zero accumulator and load high-order bits

Zero accumulator and load low-order bits

1
1

0
0
0
0
0
0
0

1 0
0 0
1

1 0 0 0
1

1 0

,
,,
1

0 0 0

1 1 0 0
0, 1 1 0 0
()

1 0 1
1 1 0

4--0--+

I +---0----+
1 0 0 0 1 0 0 1
I

+--0----+
+--D----+

with· no sign extension

AUXILIARY REGISTER AND DATA PAGE POINTER INSTRUCTIONS
MNEMONIC

A-72

DESCRIPTION

NO.

CYCLES

WORDS

lAR
lARK
lARP

Load auxiliary register
Load auxiliary register pointer immediate

1
1

lOP
loPK

Load data memory page pOinter

Load data memory page pointer immediate

MAR
SAR

Modify auxiliary register and pointer

Store auxiliary register

Load auxiliary register immediate

1
1

,
1

OPCOoE
INSTRUCTION REGISTER
1514131211109
0 0 1 1 1 0 0
1 1 0 0 0
0
0 1 1 0 1 0 0
0 1 1 0 1 1

,
,

1
1 0 1 1 1 0
0
0 1 1 0 1 0 0 0
0 0 1 1 0 0 0 R

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R I +--0----+
R
K--+
0 1 0 0 0 00 0 K

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+--0--+

0 0 0 0 0 0 K

4--0----'

~o--+

TMS320C14/TMS320E14
DIGITAL SIGNAL PROCESSOR

TABLE 2. TMS320 FIRST-GENERATION INSTRUCTION SET SUMMARY (continuedl
BRANCH INSTRUCTIONS
MNEMONIC

DESCRIPTION

NO.

CYCLES

WORDS

Branch unconditionally

BANl

Branch on auxiliary register not zero

BGEZ

Branch if accumulator 2: 0

BGZ

Branch if accumulator > 0

BLEZ

Branch ;1 accumulator ::s: 0

OPCODE
INSTRUCTION REGISTER
1514131211109 B 7
1

0 0 0 0
1

0 0 0 0
Bll

Branch If accumulator < 0

0 0 0 0
BNZ

Branch If accumulator

" 0

0 0 0 0
BV

Branch on overflow

0 0 0 0
BZ

Branch if accumulator - 0

CALA
CALL

Call subroutine from accumulator

Call subroutine immediately

2
2

0 0 0 0
0 1 1 1

RET

Return from subroutine or interrupt routme

0 0 0 0
0 1 1 1

6
0 0
BRANCH
0 1 0 0 0 0
BRANCH
1 1 0 1 0 0
+-- BRANCH
1 1 0 0 0 0
BRANCH
1 0 1 1 0 0
+-- BRANCH
1 0 1 0 0 0
+-- BRANCH
1 1 1 0 0 0
BRANCH
0 1 0 1 0 0
+-- BRANCH
1 1 1 1 0 0
+-- BRANCH
1 1 1 1 1 0
1 0 0 0 0 0
BRANCH
1 1 1 1 1 0
1

0 0

+--

0 0 0
AODRESS
0 0 0
ADDRESS
0 0 0
ADDRESS
0 0 0
ADDRESS

1 0

0 0 0
-----+
0 0 0
-----+
0 0 0

-----+
0 0 0
-----+

0 0 0 0 0 0
ADDRESS -----+

0 0 0 0 0 0
ADDRESS-----+

0 0 0 0 0 0
ADDRESS - - +

0 0 0 0 0 0
ADDRESS-----+

0 0 0 0 0 0
ADDRESS--+

0 0 1 1 0 0
0 0 0 0 0 0
ADDRESS-----+

0 0

1 0

T REGISTER, P REGISTER, AND MUL TlPL Y INSTRUCTIONS
. MNEMONIC

DESCRIPTION

NO .

NO.

CYCLES

WORDS

OPCODE
INSTRUCTION REGISTER
1514131211109 B 7

APAC

Add P register to accumulator

LT
lTA

Load T register

LTA combines LT and APAC into one

6 5 4 3 2 1 0
0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1
0' 1 1 0 1 0 1 0 I 4---D~
0 1 1 0 1 1 0 0 I 4---D----+

1 0

0 0

0
0

1 0

instruction

LTD

LTD combines l T, APAC, and DMOV Into

4---D~

1 0

4---D~

one instruction

MPY

Multiply

wit~

T register, store product in

P register
MPYK

Multiply T register with immediate

operand; store product in P register

PAC

Load accumulator from P register

SPAC

Subtract P register from accumulator

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0 0 1 1 1 0
0 0 1 0 0 0 0

A-73

TMS320C141TMS320E14
DIGITAL SIGNAL PROCESSOR

TABLE 2. TMS320 FIRST-GENERATION INSTRUCTION SET SUMMARY (concluded)
CONTROL INSTRUCTIONS
MNEMONIC

DESCRIPTION

NO.

CYCLES

WORDS

OINT

Disable interrupt

EINT

Enable interrupt

lST

load status register

NOP

No operation

POP

POP stack to accumulator

PUSH

PUSH stack from accumulator

ROVM

Reset overflow r.1ode

SOVM

Set overflow mode

SST

Store status register

OPCOOE
INSTRUCTION REGISTER

7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 l
1 1 0 0 0 b 0 1 0

1514131211109
0 1 1 1 1 1 1
0 1 1 1 1 1 1
0 1 1 1 1 0 1
0 1 1 1 1 1 1
0 1 1 1 1 1 1
0 1 1 1 1 1 1
0 1 1 1 1 1 1

0
0

0 0

4-0~

0 0 0 0 0 0
0 I 1 1 0 1
0 1 1 1 0 0
0 0 1 0 1 0
0 0 1 0 1 1
4-0---.

0
0
0
0
0

1/0 AND DATA MEMORY OPERATIONS

MNEMONIC

DESCRIPTION

NO.

CYCLES

WORDS

OMOV

Copy contents of data memory location

Input data from port

OUT
TBlR

Output data to port

Table read from program memory to data

3
3

DPCODE
INSTRUCTION REGISTER

._---_

1514131211109 8 7 .. 6 5 4 3 2 1 0
0 1 1 0 1 0 0 1 I 4---0~

into next higher .Iocation
1

4PA+

4PA+
1 1 1

4---0-+
4---0-+

0
0
0

.4-0~

4-0~

0 0 0
0 0 1
1 1 0 0

RAM
TBlW

A-74

Table write from data RAM to program
memory

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development support products
Texas Instruments offers an extensive line of development support products to assist the user in all
aspects of TMS320 first-generation-based design and development. These products range from
development and application software to complete hardware development and evaluation systems such
as the XDS/22. Table 3 lists the software and hardware support products for the first-generation TMS320
devices.
TABLE 3. TMS320C14 SOFTWARE AND HARDWARE SUPPORT
SOFTWARE T90LS
Macro Assembler/Unker
VAX VMSt
IBM PC MS-DOSU
VAX ULTRIXt
SUN-3 UNIX"

PART NUMBER
TMDS3242250-0B
TMDS3242B50-02
TMDS32422BO-OB
TMDS3242550-0B

CPU Simulator
VAX VMSt
IBM PC MS-DOS* §

TMDS3240211-0B
TMDS3240Bll-02

Digital Filter Design Package (DFDP)
IBM PC MS-DOSU

DFDP-IBMOO2

DSP Software Library
VAX VMSt
IBM PC MS-DOSU

TMDC3240212-1B
TMDC3240B12-12

HARDWARE TOOLS
Analog Interface Board (AIB2)

PART NUMBER
RTC/EVM320C-06

AIB2 Adapter Board

RTC/ADPC14A-OB

XDS/22 Emulator

TMDS3262214

EPROM Programmer Adapter Socket

TMDX3270110

TMS320 Design Kit

TMS320DDK

tVAX. VMS, and ULTRIX are trademarks of Digital Equipment Corporation.
*MS-DOS is a trademark of Microsoft, Incorporated.
§IBM PC is a trademark of IBM Corporation.
'UNIX is a trademark of AT&T Bell Laboratories.
'SUN is a trademark of Sun Microsystems, Incorporated.

System development begins with the use of the Emulator (XDSI. This hardware tool allows the designer
to evaluate the processor's performance, benchmark time-critical code, and determine the feasibility of
using a TMS320 device to implement a specific algorithm.
Software and hardware can be developed in parallel by using the macro assemblerllinker and simulator
for software development and the XDS for hardware development. The assemblerllinker translates the
system's assembly source program into an object module that can be executed by the CPU simulator
or XDS. The XDS provides realtime in-circuit emulation and is a powerful tool for debugging and integrating
software and hardware modules.
Additional support for the TMS320 products consists of extensive documentation and three-day DSP
design workshops offered by the TI Regional Technology Centers (RTCsl. The workshops provide handson experience with the TMS320 development tools. Refer to the TMS320 Family Development Support
Reference Guide (SPRU011 I for further information about TMS320 development support products and
DSP workshops. When technical questions arise regarding the TMS320, contact the Texas Instruments
TMS320 DSP Hotline, (7131 274-2320.

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documentation support
Extensive documentation supports the first-generation TMS320 devices from product announcementthrough
applications development. The types of documentation include data sheets with design specifications, complete
user's guides, and 750 pages of application reports published in the book Digital SignalProcessing Applications
with the TMS320 Family (SPRA012A).
.
A series of DSP textbooks is being published by both Prentice Hall and John Wiley and So~s to support
digital signal processing research and education. Prentice Hall (201) 767-5937 offers among others: Practical
Approaches to Speech Coding, and A DSP Laboratory Using the TMS32010. John Wiley and Sons (800)
526-5368 has published such books as Digital Filter Design, DFTIFFT and Convolution Algorithms, and
A Practical Guide to Adaptive Filter Design. The TMS320 newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 customers on product information. The TMS320
DSP bulletin board service provides access to large amounts of information pertaining to the TMS320 family.
Refer to the TMS320 Family Development Support Reference Guide for further information about TMS320
documentation. To receive copies of first-generation TMS320 literature, call the Customer Response Center
at 1-800-232-3200.

~
~
2

electrical specifications
This section contains all the electrical specifications for the TMS320C 14/E 14 devices, including test parameter
measurement information. Parameters with PP subscript apply only to TMS320E 14 in EPROM programming mode.

absolute maximum ratings over specified temperature range (unless otherwise noted) t

n
m

Supply voltage range, VCC* ............................................. -0.3 V to 7 V
Supply voltage range, vppt ............................................ -0.6 Vto 14 V
Input voltage range ........................................ : .......... - 0.3 V to 14 V
Outputvoltagerange ................................................... -0.3Vt07V
Continuous power dissipation .................................................. 0.5 W
Air temperature range above operating device: L version .......................... 0 DC to 70 DC
Storage temperature range .......................................... - 55 DC to + 150 °C

o":zJ

~
6
2

t Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only,
and tunctional operation ofthe device at these or any other conditions beyond those indicated in the' "Recommended Operating Conditions"
section ofthis specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to vss.

recommended operating conditions
EPROM devices
EPROM devices while Fast programming
VCC Supply voltage
EPROM devices while SNAPI programming
All other devices
Vpp Supply voltage for Fast programming (see Note 1)
Vpp Supply voltage for SNAPI programming (see Note 1)

MIN
4.75
5.75
6.25
4.5
12.25
12.75

VSS Supply voltage

I
VIH High-level input voltage

ClKIN

A-76

UNIT

v
V

ClKIN, CAPO, CAP1, CMP4/CAP2/FSR, CMP5/CAP3/FSX, RS

I All remaining inputs

4
2

Vil

Low-level input voltage, all inputs except as noted

Vil
IOH
IOl
TA

CAPO, CAP1, ,CMP4/CAP2/FSR, CMP5/CAP3/FSX, ~
High-level output current, all outputs
Low-level output current, all outputs
Operating free-air temperature, l version

NOTE 1:

NOM MAX
5.25
5
6.0
6.25
6.5
6.75
5
5.5
12.5 12.75
13.0 13.25
0

Vpp can be connected directly (except in the program

0.8
1
-300
0
~de).

VCC supply current in this case would be ICC + Ipp.

..If

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V
V
p.A
mA
DC

TMS320C14/TMS320E14
DIGITAL SIGNAL PROCESSOR

electrical characteristics over specifled temperature range (unless otherwise noted)
PARAMETER

TEST CONDITIONS

VOH High-level output voltage
VOL low-level output voltage
IOZ
II

Off-state output current
Input current

Input capacitance

f = 25.6 MHz, Vec
TA = O·C to 70·C

= 5.25 V,

ROM

f = 25.6 MHz, Vec
TA = ooC to 70°C

= 5.25 V,

Vpp

Data bus

MAX

Vee- 0.4 *
0.3

0.5
20
-20
±20
±50

= Vec = 5.5 V
= 13V

V
V
,.A
,.A

rnA

100

,.A

rnA

25*
f

UNIT
V

rnA

Data bus
All others

Output capacitance

= VSS to Vee

Vpp

TYpt

All inputs except elKIN
ClKIN

EPROM

IpPl VPP supply current
Vpp supply current
IpP2
(during program pulse)
Ci

= 20,.A (see Note 2)
= MAX
Vo - 2.4 V
Vee = MAX
Vo = 0.4 V
IOH

IOl

ICC § Supply current

MIN
2.4

IOH - MAX

z
o

15*

= 1 MHz, All other pins 0 V

25*

All others

10*

tAli typical values are at VCC = 5 V, TA = 25°C, except ICC at 70°C.
*Velues derived from characterization, date and not tested.
flCC characteristics are inversely proportional to temperature.
NOTE 2: This voltage specification is included for interface to HC logic. However, note that all of the other timing parameters defined
in this data sheet are specified for TTL logic levels and will differ for HC logiC levels.

::E
a:

oLa.
Z

--------------------------------------------------------------------------..
-W
PARAMETER MEASUREMENT INFORMATION

2.15 V

FROM OUTPUT
UNDER TEST

'
C

~
z

n
m
Z

MIN
39.06·

Master clock cycle time

tc(MC)

NOM
40

MAX
150

UNIT
ns

tr(MC)

Rise time master clock input

10t

tf(MC)

Fall time master clock input

10t

tw(MCP)

Pulse duration master clock

t"'1(MCL)

Pulse duration master clock low

15 t

tw(MCH)

Pulse duration master clock high

15 t

0.45tcIMC) t

0.55tcIMC) t

tValues derivl!d from characterization date and not testl!d.

MEMORY READ AND INSTRUCTION TIMING
switching characteristics over recommended operating conditions

"TI

o::Il

TEST
CONDInONS

PARAMETER
Delay time CLKOUT I to address bus valid

Delay time CLKOUTI to RENI (memory access)

td4

Delay time CLKOUT I to J!iEN I 11/0 access)

Delay time CLKOUT I to RENI 11/0 access)

Delay time CLKOUTI to WEI

RL = 8250,

Delay time CLKOUTI to WEI

Delay time CLKOUT I to date bus OUT valid

CL = 100pF.
See Figure 1.

Time after CLKOUT I that data bus starts to be driven

~10
tv

Time after CLKOUTI that data bus stops being driven
Data bus OUT valid after CLKOUT I

thIA-WR)

Address hold time after WEI, RENI

~
oz

TYP

MAX

10t

:s::

MIN

UNIT

0.25tcIC) - 5 t

0.25tc(C) + 12

-lOt
0.25tc IC) - 5 t

0.25tcIC) + 12

-10 t

0.5tc IC)-5 t

ns
ns

12
0.25tc IC) + 52

0.26tc IC) - 5 f

ns
ns

0.25tcIC) + 30 t
0. 25tcIC)-10
ot

tsuIA-REN) Address bus setup time prior to "AEiii1

ns
ns

0.5tc IC) + 12,

-10t

ns
ns

ns
ns
ns

0.25tc IC) - 35

tValues derivl!d from characterization date and not testl!d.

timing requirements over recQmmended operating conditions
TEST CONDITIONS
tsulD)
thlD)
NOTE 3:

A-78

Setup time date bus l'alid prior to CLKOUT I
Hold time date bus held valid after CLKOUT I

RL - 8250,
CL = 100pF,
See Figure 1 .

Isee Note 3)

Date may be removed from the data bus upon "AEiii I precl!ding CLKOUT I.

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MIN

40
0

NOM

MAX

UNIT
ns
ns

TMS320C14/TMS320E14
DIGITAL SIGNAL PROCESSOR

RESET IRS) TIMING

switching characteristics over recommended operating conditions
PARAMETER
tdll

TEST CONDITIONS

Delay time ~I, and 'AENI from ~

tdislR} Data bus disable time after RS

tdis(A} Address bus disable time after ~ low
tenIA} Address bus enable time after ~ high

MIN

TVP

MAX

0.5tc (C}+ 50 t

= 825O,
= 100 pF,

See Figure 1.

UNIT
ns

0.25tc1CI + 50 t

0.25tc (C} + 50 t

tThese values were derived from characterization data and not tested.

timing requirements over recommended operating conditions
MIN
tsu(R}

Reset (~) setup time prior to CLKOUT (see Note 4)

twIRl

~ pulse duration

NOTE 4:

NOM

MAX

UNIT

5tc(C}

~ can occur anytima during a clock cycle. Time given is minimum to ensure synchronous operation.

z
o

MICROCOMPUTER/MICROPROCESSOR MODE INMI/MC/MP)

timing requirements over recommended operating conditions

~--------------------------------~----------~~<
MIN
NOM
MAX
:E
th(MC/MP} ~ Hold time after RS high

a::

1.25tc

~HOld time to put device in microprocessor mode.

;u,.

-w

INTERRUPT (lNT)/NON-MASKABLE INTERRUPT INMI)

timing requirements over recommended operating conditions Isee Note 5)
MIN
tf(lNT}

Fall timeiiiii'

tf(NMI}

Fall time JiiQJ

tw(lNT}

Pulse duration

NOM

MAX

UNIT

15 t

TFn'

tc(C}

ris

twlNMIl Pulse duration JiiQJ

tc(C}

tsullNTI Setup time iiiii' before CLKOUT low

tsu(NMI} Setup time NMI before CLKOUT low

CJ
Z

<
>
o

tThese values were derived from characterization deta and not tested.
NOTE 5: TFn' and JiiQJ are synchronous inputs and can occur at any time during the cycle. NMI and INT are edge triggered only.

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TMS320C14/TMS320E14
DIGITAL SIGNAL PROCESSOR

BIT I/O TIMING
switching characteristics over f'ecommended operating conditions
PARAMETER

trfp

Rise and fall time' outputs

!d(lOP)

CLKOUT low to data v~lid outputs

TEST CONDITIONS
RL - 825 n,
CL = 100 pF,
See Figure 1.

MIN

TVP

MAX

UNIT

20t

.25tcU:) + 20

timing requirements over recommended operating conditions
TEST CONDITIONS

MIN

= 825 n,
= 100 pF,

trfUlOP)

Rise and fall time inputs

tst.!l!OP)
twl(lOP)

Data setup time before CLKOUT time
Input pulse duration

CL
See Figure 1.

TVP

MAX
20t

20t

UNIT
n's
ns
ns

tc(C) +20

tTlllise values were derived from characterization data and not tested.

GENERAL PURPOSE TIMERS

timing requirements over recommended operating conditions
TEST CONDITIONS

~
2

n
m

tr(TIM)

TCLK I, TCLK2 rise time

tf(TIM)
thL(TIM)
thH(TIM)

TCLK I, TCLK2 fall time
Hold time TCLK I, TCLK2 low
Hold time TCLK1, TCLK2 high

RL = 825

MAX

UNIT

20t

ns
ns
ns

MAX

UNIT

20t

tcIC)+20
tc(C) +20

tThese values were derived from characterization data and not tested.

WATCHDOG TIMER TIMING
switching characteristics over recomm!tnded operating conditions

:IJ

PARAMETER

TEST CONDITIONS

WDi'
CLKOUT to WI5'I' valid
WDi' output pulse duration
Fall time,

tflWDTl

TVP

CL = 100 pF,
See Figure 1.

MIN

!d'WDTI
tw(WDT)

RL
CL

= 825 II,
= 100 pF,

MIN

TYP

0.25tc (C) + 20

See Figure 1.

8tc (C)-20 8tc+ 2O

tThese values were derived from characterization data and not tested.

EVENT MANAGER TIMING
switching characteristics over recommended operating conditions
PARAMETER
tf(CMP)

Fall time, CMPO-CMP5

tr(CMP)

Rise time, CMPO-CMP5

TEST CONDITIONS
RL = 82511,
CL = lOOpF,'
See Figure 1.

MIN

TVP

MAX

UNIT

20t

MAX

UNIT

tThese values were derived from characterization data and not tested.

timing requirements over recommended operating conditions

,
tw(CAP)

CAPO-CAP3 input pulsa duration

tsu(CAP)

Capture input setup time before CLKOUT low

TEST CONDITIONS

MIN

RL - 82511,
CL = 100 pF,
See Figure 1.

tc(C) +20

20t

tThesa values were derived from characterization data and not tested.

A-SO

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TYP

TMS320C14/TMS320E14
DIGITAL SIGNAL PROCESSOR

SERIAL PORT-SYNCHRONOUS MODE TIMING

switching characteristics over recommended operating conditions
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tc(C)

65,536tc 1C)

tc(ClK-S)

Serial port clock cycle time t

tflClK-S)

TXO/ClK fall time t

tr(ClK-S)

TXO/ClK rise tima t

twl(ClK-S) TXO/ClK low time t

td(TX-S)

RXO/OATA output valid before TXO/ClK low t

th(TX-S)

RXO/OATA hold after TXO/ClK (intemal) low t

ld(TX-S)

RSO/DATA output valid before TXO/ClK IOw*

th(TX-S)

RXO/OATA hold after after TXO/ClK low*

= 8250,

0.5tc(ClK-S)- 20 0.5tc (ClK-S) + 20

Cl = 100pF,

0.5tc(ClK-S)- 20 0.5tc(ClK-S) + 20

twH(ClK-S)- 20

twH(ClK-S) TXO/ClK high time t

See Figure 1 .

ld(Tx-s) + 20

ns
ns

twH -1. 75tc(C) + 20
twl + 1. 75tc(C) + 20

t Internal clock
* External clock

timing requirements over recommended operating conditions
MIN

TEST CONDITIONS

MAX

UNIT

twl(ClK-Si TXO/ClK low time (external) *

2tc(C)

twH(ClK-S) TXO/ClK high time (external) *

2tc(C)

tau(RX-S)
th(RX-S)
tau(RX-S)
th(RX-S)

RXO/OATA input setup before TXO/ClK low*
RXO/OATA input hold after TXO/ClK low*
RXO/OATA input setup before
TXO/ClK external low t
RXO/OAT A input hold after
TXO/ClK external low t

Rl = 82511,
Cl = 100pF,
See' Figure 1 .

0
2tc (C)-20

ns
ns

0.25tc (C) + 20

::E
a::

ou.

-Zw

t Internal clock
*External clock

11('

SERIAL PORT-CO DEC MODE TIMING

switching characteristics over recommended operating conditions
PARAMETER
ld(TXO-C)

TXO output valid before ClKX low

th(TXO-C)

TXO output hold after ClKX low

TEST CONDITIONS
Rl - 8250,

MIN

MAX

0.5tc(C)- 20

Cl = 100pF,
See Figure 1 .

UNIT

>
C
II(

ns
twl +1.75tc (C)-20

timing requirements over recommended operating conditions
TEST CONDITIONS
tc(ClK-C)

ClKR, ClKX cycle time

MIN

MAX

UNIT
ns

3tc (C)§

tf(ClK-C) , ClKR, CLKX fall time

20§

ClKR/ClKX rise time

20§

tr(ClK-C)

twl(ClK-C) ClKR, CLKX high time
twH(CLK-C) ClKR, ClKX low time
FSX valid before ClKX low
tsu(FSX)
FSR valid before ClKR fow
tou(FSR)

Rl = 8250,

1.5tc(C)- 20'

Cl = 100pF,
See Figure 1 .

1.5tcIC)- 20'
0.5tc (C)-20
0.5tc (C)- 20
0

ns
ns
ns
ns
ns

tsu(RXO-C) RXO input setup time before ClKR low
th(TXO-C) RXO input hold time after ClKR low

tc(C) +20

§These values were derived from characterization data and not tested.
'lrhis cycle time is only possible when ClK(R) and ClK(X) are synchronized with CLKOUT.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

A-81

TMS320C14/TMS320E14
DIGITAL SIGNAL PROCESSOR

timing diagrams
This section contains all the timing diagrams for the TMS320C14/E14 devices.
Timing me'asurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts,
unless otherwise noted.

clock timing
~ ~ ',IMel
~ 'wiMeHI
·1 ~'cIMel ~

~---.+- twlMCPI t

1
X2/eLk'N

. I

l,'IIMel__! 1.:----.1'wiMeLi
•
L..

I-

CLKOUT

z
o

__________________-,lfr-----------------~~

~ I.- 'llel

: 1.._ - - - -

....! ~

',Iel

. w l e L I - - - - -...
"

'wleHI

........-.r'dIMeel'

-I

'clel

ttcl(MCC) and tw(MCPI are referenced to an intermediate level of 1.5 volts on the ClKIN waveform.

"oXI

memory read timing

!'eLkDUT

-r
--~I/·
'd3

o
z

I.-

015-00

A-82

~~I____________~r_

/
'd2

---I
I

j.-- 'd, ----=:j

A11-AO

"lei

~~~~~~:~~~~=>RW<

V!------.\'---

1...1 \.~

14'""'..,IA-RENI

ADORESS

aus

VALIa

I---{

____-J)

'suID)

'~=========

----1...-....4)>-.---------

INSTRUCTION INPUT VALID

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

'hiD)

TMS320C14/TMS320E14
DIGITAL SIGNAL PROCESSOR

TBLR instruction timing
CLKOUT

LEGEND:
1.
2.
3.
4.
5.
6.

TBlR INSTRUCTION PREFETCH
DUMMY PREFETCH
DATA FETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
ADDRESS BUS VALID

7.
8.
9.
10.
11.
12.

ADDRESS BUS VALID
ADDRESS BUS VALID
INSTRUCTION INPUT VALID
INSTRUCTION INPUT VALID
DATA INPUT VALID
INSTRUCTION INPUT VALID

TBLW instruction timing

z
o

::E
a::

ou.

Z
w

LEGEND:
1.
2.
3.
4.
5.
6.

TBlW INSTRUCTION PREFETCH
DUMMY PREFETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
ADDRESS BUS VALID
ADDRESS BUS VALID

7.
8.
9.
10.
11.

ADDRESS BUS VALID
INSTRUCTION INPUT VALID
INSTRUCTION INPUT VALID
DATA OUTPUT VALID
INSTRUCTION INPUT VALID

TEXAS

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TeXAS 77001

A-S3

TMS320C14/TMS320E14
DIGITAL SIGNAL PROCESSOR

IN instruction timing
CLKOUT

\Io...-_....JI

A11-AO

015·00

LEGEND:

»
c
~

1.
2.
3.
4.

IN INSTRUCTION PREFETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
PERIPHERAL ADDRESS VALID

OUT instruction timing

-m

CLKOUT

n
2

5.
6.
7.
B.

ADDRESS BUS VALID
INSTRUCTION INPUT VALID
DATA INPUT VALID
INSTRUCTION INPUT VALID

\I'-----JI

3l:

A11-AO

6
2

015·00

LEGEND:
1.
2.
3.
4.

A-84

OUT INSTRUCTION PREFETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
PERIPHERAL ADDRESS VALID

5.
6.
7.
8.

ADDRESS BUS VALID
INSTRUCTION INPUT VALID
DATA OUTPUT VALID
INSTRUCTION INPUT VALID

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

TMS320C14/TMS320E14
DIGITAL SIGNAL PROCESSOR

reset timing
ClKOUT

.....

.......

,...touiRI

g----..\l

•

I
,....tou(RI

~,----------~--~
I..

DII
WE

,--------+----r-----~

I
I

SEE
NOTE10

twiRl

telll......

'--

-.4 -tcn.IRI
~

DATA SHOWN I

RELATIVE TO WE I

Dl&-DO~""'------I'----Ij-------~(D~A~~:g~~~Ml

ADD~ -----v

AB:

---./\

NOTES:

8.
9.
10.

r_t-dl-.(-A-I--.....,.t----i-.--~.J
~

....(AI AB = PC = 0

AB = ADDRESS BUS

AS forces REN and ~ high and places data bus 00-015 and address bus AO-A 11

+
~
PC

in a high-impedance state. AB outputs
land program counterl are synchronously cleared to zero after the next complete elK cycle from AS 1.
AS must be maintained for a minimum of five clock cycles.
Resumption of nonnal program will commence after one complete elK cycle from RSr.
Due to the synchronizing action on AS, time to execute the function can vary dependent upon when ifSr or mil occur in
the elK cycle.
Diagram sh~wn is for definition purpose only. WE and REN are mutually exclusive.

z
o

:E
a:

oLL.

-o
Z

microcomputer/microprocessor mode timing diagram

CLKOUT

~\.._'_--JI:
,.-...--TnIMC/MPI----;
__________~/r-----mli'/MC/MP ~'--~
\.~
.
iii

TEXAS
INSTRUMENTS
POST OFFtCE BOX 1443 •

HOUSTON. TEXAS 77001

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEX,AS 77001

TMS320E14
DIGITAL SIGNAL PROCESSOR

EPROM programming
The TMS320E 14 includes a 4K x 16-bit industry-standard EPROM cell for prototyping and low-volume
production. The TMS320C 14 with a 4K-word masked ROM then provides a migration path for cost-effective
production. An EPROM adapter socket (part #TMDX327011 0). shown in Figure 2. is available to provide 68-pin
to 28-pin conversion for programming the TMS320E14.
Key features of the EPROM cell include the normal programming operation as well as verification. The EPROM
cell also includes a code protection feature that allows code to be protected against copyright violations.
The TMS320E14 EPROM cell is programmed using the same family and device codes as the TMS27C64 8K
x 8-bit EPROM. The TMS27C64 EPROM series are ultraviolet-light erasable. electrically programmable. readonly memories. fabricated using HVCMOS technology. They are pin-compatible with existing 28-pin ROMs
and EPROMs. These EPROMs operate from a single 5-V supply in the read mode; however. a 12.5-V supply
is needed for programming. All programming signals are TTL level. For programming outside the system. existing
EPROM programmers can be used. Locations may be programmed Singly. in blocks. or at random.

z
o

a::

oLL.

-ow
Z

~
cs:

Q
FIGURE 2. EPROM ADAPTER SOCKET

TEXAS . "
INSTRUMENTS
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A-89

TMS320E14
DIGITAL SIGNAL PROCESSOR

The TMS320E14 uses 12 address lines plus WE to a.ddress the 4K-word memory in byte format (8K=byte
memory). In word format. the most-significant byte of each word is assigned an even address and the leastsignificant byte an odd address in the byte format. Programming information should be downloaded to EPROM
programmer memory in a high-byte to low-byte order for proper programming of the devices (see Figure 3.)
TMS320C14 On-Chlp
Program Memory
(Word Format)

O(OOOOh)
1(0001 h)
2(0002h)
3(OO03h)

»
c

1234h
5678h
SABCh
DEFOh

4095(OFFh)

TMS320E14 On-Chip
Program Memory
(Byte Format)

O(OOOOh)
1(0001 h)
2(0002h)
3(0003h)
4(0004h)
5(0005h)
6(0006h)
7(0007h)

34h
12h
78h
56h
BCh
9Ah
FOh
DEh

EPROM
Programmer
Mamory
Byte Format with
Adapter Socket
O(OOOOh)
1(0001 h)
2(OOO2h)
3(0003h)
4(0004h)
5(0005h)
6(0006h)
7(0007h)

12h
34h
56h
78h
9Ah
BCh
DEh
FOh

z
om

B191(lFFFh)

o::u
3:

o
z

FIGURE 3. EPROM PROGRAMMING DATA FORMAT
Figure 4 shows the wiring conversion to program the TMS320E 14 using the 28-pin pinout ofthe TMS27C64.
The table of pin nomenclature provides a description of the TMS27C64 pins.

CAUTION
I

The TMS320E14 does not support the signature mode available with some EPROM programmers.
The signature mode puts a high voltage 112.5 V DC) on pin A9. The TMS320E14 EPROM cell is not
designed for this feature and will be damaged if subjected to it. A, 3.9 IdI res.lstor Is standard on the
TI programmer socket between pin A9 and the programmer. This protects the device from unintentional
use of the signature mode.

A-90

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TeXAS 77001

TMS320E14
DIGITAL SIGNAL PROCESSOR

4vpp

3 A12
A7
4
A8
5
A5
6
A4
7
A3
8
A2
S
A1

VCC

'lm
EPT

28
27
26

A10

'---A1i"

III ..

5 4 3 2

10
11

::i ::!

16867666564636261
80

59
58
57
56
55 ~
54
53
52
51

20
21

as ; a - - '

9 8 7

.....
~1°

> > ~I~ e e

"'III
ee

25
A8
24
3.SKU
AS
23 yvv
A11
22
~
21
A10
20
E
19

~
Pml

;t-----

11
as
a1
12
a5 ~
Q2
13
a4 ~
Q3
14 GND
TMS27C64

EPT

;s---'

VPP

PINOUT

G
ClKIN

13
14
15

17
18

TMS320E14

SO
48
47
48
45
44

22
23
24
25
26

n~~~~U~M~~~~~~~~~

~ ~~~~~

z
o

:E
a:

ou.

-ow
Z

FIGURE 4. TMS320E14 EPROM PROGRAMMING CONVERSION TO
.
TMS27C64 EPROM PINOUT
PIN NOMENCLATURE (TMS320E14)
NAME
A 12(MSB)·AO(lSB)
ClKIN

E
EPT
G
GND

PGM
OS(MSB)-O 1(lSB)

~
VCC
Vpp

1/0
I
I
I
I
I
I
I
I/O
I
I
I

DEFlNmON
On-chip EPROM programming address lines
Clock oscillator input

EPROM ,chip enable
EPROM test mode select
EPROM output enable
Ground
EPROM writelprogram select
Data lines for byte-wide programming of on-chip BK bytes of EPROM
Reset for initializing the device
5-V to a.5-V power supply
12.5-Vto 13-V power supply

TEXAS

INSTRUMENTS
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A-91

TMS320E14
DIGITAL SIGNAL PROCESSOR

Table 4 shows the programming levels required for programming. verifying. reading. aRd protecting the EPROM
cell.

TABLE 4. TMS320E14 PROGRAMMING MODE LEVELS
SIGNAL
NAMEt

TMS320E14
PIN

i!t
(5

READ

VIL

VIH

rom:

PGM

16
18

27
1
28
14
14
26

PULSE
Vpp

v'H
Vpp

Veep

Vss
Vss
Vss

Vss
Vss
vss

v'H
Vee
Vee
Vss
Vss
Vss

19-15,13-11

D'N

OoUT

ADDR

ADDR
ADDR
ADDR
ADDR

01-08

(')

PROGRAM
VERIFY

G
Vpp

~
z

PROGRAM

Vee
Vss
eLK'N
EPT

»c

TMS27C84
PIN

A12-A7
A6
A5
A4
A3-AO

4.33
3.34
24
17
42,41,38,37,
32-29
15,11,10.
8,7,2
1
68
67
66,65,56,55

25,24.23,
21,3,2
4
5
6
7-10

vlL

EPROM
PROTECT
VIH

PROTECT
VERIFY
vlL

V'H

V'L

v'H
Vpp
Veep

V'H
Veep
Veep

Vss
Vss
Vpp

Vss
Vss
vpp

OsPULSE

08RB'T

ADDR

ADDR
ADDR
ADDR
ADDR

v'L

V'H

tSigna' names shown for TMS320E14 EPROM programming mode on'Y.
LEGEND:
V'H = TTL high 'eve'; V'L = TTL low 'eve'; ADDR = byte address bit; Vpp
Vee = 5 V ± 0.25 V; X = don't care; PULSe = 'ow-going TTL pu'se.
D'N = byte to be progremmed 8t ADDR; OoUT = byte stored at ADDR.
Veep = 6.0V ± 0.25 v (FAST) or 6.5 V ± 0.25 V (SNAP!)

= 12.5 V ±

0.25V (FAST) or 13.0V ±0.25 V (SNAP!) .

programming
Since every memory bit in the cell is a logi!! 1. the programming operation reprograms certain bits to O. Once
programmed. these bits can only be erased using ultraviolet light. The correct byte is placed on the data bus
with Vpp set to the 12.5-V level. The PGM pin is then pulsed low to program in the zeroes.
erasure
Before programming. the device must be erased by exposing it to ultraviolet light. The recommended minimum
exposure dose (UV-intensity X exposure-tinie) is 15 watt-seconds per square centimeter. A typical 12 milliwattseconds per SQuare centimeter. filterless UV lamp will erase the device in 21 minutes. The lamp should be located
about 2.5 centimeters above the chip during erasure. After exposure. all bits are in the high state.
verifyfread
To verify correct programming. the EPROM cell can be read using either the verify or read line definitions shown
in Table 4. assuming the inhibit bit has not been programmed.

A-92

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TMS320E14
DIGITAL SIGNAL PROCESSOR

program inhibit
Programming may be inhibited by maintaining a high level input on the Epin or PGM pin.
standard programming procedure
Before programming, the device must first be completely erased. Then the device can be programmed with
the correct code. It is advisable to program unused sections with zeroes as a further security measure. After
the programming is complete, the code programmed into the cell should be verified. If the cell passes verification,
the next step is tel) program the ROM protect bit (RBIT). Once the RBIT programming is verified, an opaque label
should be placed overthe window to protect the EPROM cell from inadvertent erasure by ambient light. At this
point, the programming is complete, and the device is ready to be placed into its destination circuit.
Refer to Appendix F of the TMS320C 14/E 14 User's Guide for additional information on EPROM programming.

recommended timing requirements for programming: Vee = 6 V and Vpp = 12.5 V (Fast) or
Vee = 6.5 V and Vpp = 13.0 V (SNAP! Pulse), TA = 25°C (see Note 6)
MIN NOM MAX

I Fast programming algorithm
J SNAPI Pulse programming algorithm
I Fast programming only

0.95
95
2.85
2

1
100

1.05
105
78.75

UNIT
ms

twUPGMI

Initial program pulse duration

tw{FPGM)
tsulAI

Final pulse duration
Address setup time

tsu{E)

E setup time

p.s

tsu{G)
tsuCDI
tsu{VPP)
tsu{vee)

Gsetuptime
Data setup time

2
2
2
2
0
2

thlAI
lh{D)
NOTE:

•

VPP setup time
Vee setup time
Address hold time
Data hold time

6. For all switching characteristics and timing measurements, input pulse levels are 0.40 V to 2.4 V and VPP
during programming.

z
o

ps
ms

:i
a::
ou.

p.s

ps
"s

= 12.5 V

p.s
± 0.5 V

W
(J

cs:

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

A-93

TMS320E14
DIGITAL SIGNAL PROCESSOR
program cycle timing

==x

---PROGRAM-....J-"-VERIFV-----:

i"j
__

A12·AO

ADDRESS STA+

!----rl tsulAI
I

08.Q1----1
V~

DATA IN STABLE

X A~D:E~

'-thIAI"':

::~
VIHIVOH

}--H~.Z----{ DA:~~UT }~-----VILIVOL

I
I
I
I
'
I
t
~taulDI
I
I
t----rtcliSIGI
r-~I~------4---rI--41--~I----------V~
I
I
I

--./1.if

~tsulVppl

Vee

: : :
r--~I~-----~---rl--~I--rl---------Veep

vee~

Vee

I---i--taulVeel
I

E~
I

~
Z

tsulEI ,.

:
I

..:

....
; -• .;..1 thlDI

(")

~~---~--~-~i~-~---------VIH

I
VIL
I
----:-tenlGI
I
'
twIFPGMI~
;---:- t~UIGI
:
---"';';;--=~----""'\l
;i:------VIH

I
I
twlIPGMI"'--

"TI

VIL

-z~
o

ttdislGI and tan(G( are characteriatics of the device but must be accommodated by the programmer.

A-94

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INSTRUMENTS
POST OFFICE BOX 1443 •

H9USTON, TEXAS 77001

TMS320C14/TMS320E14
DIGITAL SIGNAL PROCESSOR

68-lead plastic chip carrier package (FN suffix)

~0.25

(0.0101 R MAX

IN 3 PLACES

1.27 (0.050) T.P.
(SEE NOTE B)

23.62 (0.9301
23.11 (0.9101
(AT SEATING PLANE I

25.27 (0.995)
25.02 (0.985)
24.33 (0.9561
24.13 (0.9501
(SEE NOTE AI

0.94 (0.0371 R
0.69 (0.027)

I
I

SEATING PLANE

THERMAL RESISTANCE
CHARACTERISTICS (SEE NOTE CI
RIJA

·c/W

~0.9561

24.33
(SEE NOTE AI
24.13 (0.9501

ou.

1.22 (0.048) x 450
1.07 (0.0421

25.27 (0.9951
25.02 (0.985)

0.81 (0.0321
0.66 10.026)

~:1l52 (0.0601 MIN

0.51 (0.020)
0.36 (0.0141

:E
a::

L-

RlJc

·C/W

z
o

JL~0.64

Z
w

(0.0251 MIN

LEAD DETAIL

NOTES:

A.' Centerline of center pin each side is within 0.10 (0.0041 of package centerline as determined by this dimensioo
B. Location of each pin is within 0.27 (0.0051 of true position with respect to center pin on each side.
C. Thermal resistance calculations based on ICC = 65 mA TYP at T A = 70 ·C.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.

TEXAS . .
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POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

A-95

TMS320C14/E14
DIGITAL SIGNAL PROCESSORS

68-lead cerquad chip carrier package (FZ suffix)
....._ _..... 4.57(0.180)
3.94 (0.155)
0.64, (0.26) R MAX

3.55 (0.140)

(SEE NOTE C)

IN 3 PLACES

3.05 (0.120)

,27 (0.050) T.P.
(SEE NOTE 8)

26.27 (0.965)
25.02 (0.985)

24.28 (0.955)
23,62 (0.930)
(SEE NOTE A)

l>
C

o:D

2.29 (0.090)

1.018 (0.40) MIN

SEATING PLANE
(SEE NOTE D)

ilr-

-t

~ =~4~ ~ ~:~ ~ ~:5~ ~
23,62 (0.930)

0.81 (0.032)
0.86 (0.026)

__________

1.02 (.040) x 45°

25,27 (0.995)
25.02 (0.985)

-JI-

~
o
z

0.51 (0.020)
0.36 (0.014)
LEAD DETAIL
ALL LINEAR DIMENSIONS ARE IN MILLIMEteRS AND PARENTHETICALLY IN INCHES.
NOTES:

A-96

A.
B.
C.
D.

Centerline of center pin each side is within 0,10 (0.004) of package centerline as determined by this dimension.
Location of each pin is within 0,27 (0.005) of true position with respect to center pin on each side.
Glass is optional.
The lead contact points are planar within 0,' 5 (0.006).

TEXAS . "
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POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

TMS320C14/TMS320E14
DIGITAL SIGNAL PROCESSORS

INDEX
accumulator ....................... 4

memory .......................... 5

addressing ........................ 7

microcomputer/miccoprocessor mode .... 5

ALU ............................. 4

multiplier ......................... 5

architecture ....................... 4

non-maskable interrupt (NMI) ....... 2,5,15

bit I/O .......................... 3,5

operating conditions ................ 12

block diagram ...................... 4

package types ................ 1,31,32

capture inputs ...................... 3

parallel I/O channels ................. 4

clock timing ...................... 14

parallel multiplier .................... 5

compare outputs .................... 3

parameter measurement ............. 13

data and program memory ............. 5

pinout/nomenclature ................ 27

development support products ......... 11

pin descriptions ................... 2,3

::E

documentation support .............. 12

program cycle timing ................ 29

electrical specifications .............. 12

program inhibit .................... 29

ou.

EPROM adapter socket .............. 25

program memory expansion ............ 5

EPROM programming ............... 25

programming procedure ........... 28,29

EPROM programming data format ....... 26

reset ........................... 21

event manager ..................... 6

serial port ....................... 3,6

external clock requirements : .......... 13

serial port timer .............. 3,6,23,24

functional block diagram .............. 4

shifters .......................... 5

input/output . . . . . . . . . . ............. 5

subroutines ....................... 5

instruction set ................... 7-10

temperature ratings .................. 1

interrupts ...................... 5,22

thermal data ...................... 1 2

introduction ....................... 1

timers 1 and 2 ................... 6,22

key features ....................... 1

. timing diagrams .............. 18-24,30

mechanical data ................. 30,31

timing specifications ............. 14-17

z
o

Z
w

BI02

Branch on

BLEZ

Branch if accumulator :::; 0

BLl

Branch If accumulator < 0

BNZ

Branch if accumulator

Branch on overflow

Branch If accumulator = 0

CALA

Call subroutine from accumulator

CALL

Call subroutine Immediately

RET

Return from subroutine or mterrupt routine

BiO

=1=

OPCODE
INSTRUCTION REGISTER

1514131211109 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 0 o 0 0 0 0 0 0
0 0 0 0 +-- BRANCH ADDRESS ----+
1 1 1 1 0 1 0 0 0 o 0 0 0 0 0 0
0 0 0 0 +-- BRANCH ADDRESS ----+
1 1 1 1 1 1 0 1 0 o 0 0 0 0 0 0
0 0 0 0 +--- BRANCH ADDRESS ----+
1 1 1 1 1 1 0 0 0 o 0 0 0 0 0 0
0 0 0 0 +-- BRANCH ADDRESS ----+
1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0
0 0 0 0 +-- BRANCH ADDRESS ----+
1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0
0 0 0 0 +-- BRANCH ADDRESS ~
1 1 1 1 1 0 1 \0 0 o 0 0 0 0 0 0
0 0 0 0 +--- BRANCH ADDRESS----+
1 1 1 1 1 1 1 0 0 o 0 0 0 0 0 0
0 0 0 0 +-- BRANCH ADDRESS ----+
1 1 1 1 0 1 0 1 0 o 0 0 0 0 0 0
0 0 0 0 +-- BRANCH ADDRESS ~
1 1 1 1 1 1 1 1 0 o 0 0 0 0 0 0
0 0 0 0 +-- BRANCH ADDRESS ----+
0 1 1 1 1 1 1 1 1 o 0 0 1 1 0 0
1 1 1 1 1 0 0 0 0 o 0 0 0 0 0 0
0 0 0 0 +-- BRANCH ADDRESS----+
0 1 1 1 1 1 1 1 1 0 0 0 1 1 0 1

T REGISTER. P REGISTER. AND MUL TIPL Y INSTRUCTIONS
DESCRIPTION

MNEMONIC

NO.

OPCODE
INSTRUCTION REGISTER

CYCLES

WORDS

APAC

Add P register to accumulator

Load T register

151413121110 9 8 7 6 5 4 3 2 1 0
0 1 1 1 1 1 1 1 1 o 0 0 1 1 1 1
0 1 1 0 1 0 1 0 I ~D----+

0 0

~D--+

~D----+

0 0

0
0

LTA
LTD
MPY
MPYK

LTA combines LT and APAC Into one
Instruction
LTD combp1es LT. APAC. and DMOV into
one instruction
Multiply with T register, store product in

'p register
Multiply T register with Immediate
operand; store product In P register

PAC

Load accumulator from P register

SPAC

Subtract P register from accumulator

TEXAS . .
INSTRUMENTS
f.'(JST OFFICE 60; 1443

•

H()USHJrJ. TEXAS 77fJr)l

0 0
0 0

0
1

1 1 1 0
0 0 0 0

B-7

SMJ32010
DIGITAL SIGNAL PROCESSOR

TABLE 2. TMS320 FIRST-GENERATION INSTRUCTION SET SUMMARY (CONCLUDED)
CONTROL INSTRUCTIONS
DESCRIPTION

MNEMONIC
DINT
EINT
LST
NOP

pop
PUSH
ROVM
SOVM
SST

Disable interrupt
Enable interrupt ,
Load status register
No operation
pop stack to accumulator
PUSH stack from accumulator
Reset overflow mode
Set overflow mode
Store status register

NO.
CYQ.ES

NO.
WORDS

1
1
1
1

1
1
1
1
1
1
1
1
1

2
2
1
1
1

15
0
0
0
0
0
0
0
0
0

14
1
1
1
1
1
1
1
1
1

13
1
1
1
1
1
1
1
1
1

OPCODE
INSTRUCTION REGISTER
12 " 10 9 876543
1 1 1 1 1 1 0000
1 1 1 1 1 1 0000
1 1 0 1 1 I +--0
1 1 1 1 1 1 0000
1 1 1 1 1 1 001 1
1 1 1 1 1 1 001 1
1 1 1 1 1 1 000 1
1 1 1 1 1 1 000 1
1 1 1 0 01 + - - 0

210
001
o10

--+
000
1 0 1
100
o10
o1 1

--+

I/O AND DATA MEMORY OPERATIONS
DESCRIPTION

MNEMONIC

OMOV
IN
OUT
TBLR
TBLW

Copy contents of data memory location
into next higher location

Input data from port
Output data to port
Table read from program memory to deta
RAM
Table write from data RAM to program
memory

OPCODE
INSTRUCTION REGISTER
15 14 13 12 11 10 9 8 76543210

NO.
CYQ.ES

NO.
WORDS

2
2

1
1

0
0

1
1

0
0

o 4-PA .... 1 + - - 0 _

1 I+--O

1 14--0_

1 1..-1-0_

1 4 - PA--.I 4 - - 0 _

---+

development support
Together, Texas Instruments and its authorized third-party suppliers offer an extensive line of development
support products to assist the user in all aspects of TMS320 first-generation-based design and development.
These products range from development and application software to complete hardware development and
evaluation systems. Table 3 lists the development supPort products for the first-generation TMS320 devices.
System development may begin with the use of the simulator, evaluation module (EVM), or emulator (XDS),
along with an assembler/linker. These tools give the TMS320 user various means of evaluation, from
software simulation of the first-generation TMS320s (simulator) to full-speed in-circuit emulation with
hardware and software break point trace and timing capabilities (XDS).
Software and hardware can be developed simultaneously by using the macro assembler/linker or simulator
for software development, the XDS for hardware development, and the EVM for botl:1 software development
and limited hardware development.
Many third-party vendors offer additional development support for the first-generation TMS320s, including
assembler/linkers, simulators, high-level languages, applications software, algorithm development tools,
application boards, software development boards, and in-circuit emulators. Refer to the TMS320 Family
Development Support Reference Guide (SPRU011 A) for further information about TMS320 development
support products offered by both Texas Instruments and its third-party suppliers.

8-8

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

SMJ32010
DIGITAL SIGNAL PROCESSOR
Additional support for the TMS320 products consists of an extensive library of product and applic~tions
documentation. Three-day DSP design workshops are offered by the TI Regional Technology Centers (RTCs).
These workshops provide insight into the architecture and the instruction set of the first-generation
TMS320s as well as hands-on training with the TMS320 development tools. When technical questions
arise in regard to a TMS320 Family member, contact Texas Instruments TMS320 Hotline via (713)
274-2320. Or, keep informed on the latest TI and third-party development support tools by accessing the
DSP Bulletin Board Service (BBS) via (713) 274-2323. Application source code may also be accessed
through the BBS via a 2400-, 1-200-, or 300-bps modem.
TABLE 3. TMS320 FIRST·GENERATION SOFTWARE AND HARDWARE SUPPORT
SOFTWARE TOOLS

PART NUMBER

Macro Assembler/Linker
PC/MS-DOS

TMDS3242850-02

VAXNMS
VAX ULTRIX
SUN-3 UNIX

TMDS3242250-08
TMDS3242260-08
TMDS3242550-08

Simulator
PC/MS-DOS

TMDS32408ll-02

VAXNMS

TMDS32402ll-08

Digital Filter Design Package (DFDP)
IBM PC PC-DOS

DFDP/IBMOO2

DSP Software Library
PC/MS-DOS

TMDC32408l2-l2

VAXNMS

TMDC32402l2-l8

TMS320 Bell 2l2A Modem'Software
TMDX32408l3-l2

PC/MS-DOS
Data Encryption Standard Software

TMDX32408l4-l2

PC/MS-DOS
HARDWARE TOOLS
Evaluation Tools
Evaluation Module (EVM)
Analog Interface 80ard 1 (AIB1)

PART NUMBER
RTC/EVM320A-03
RTC/EVM320C-06

Analog Interface Board 2 (AIB2)
EPROM DSP Sta"er Kit (TMS320E15)

XDSl22 Emulators
TMS320Cl0/C15
TMS320C14
TMS320C17

RTC/AIB320A-06
RTC/EVM320E-15
TMDS32622ll
TMDX3262214
TMDX3262217

XDSl22 Upgrade Kits
TMS32010 - TMS320Cl0/C15
TMS320Cl0/C15 - TMS32OC14

TMDS3282215
TMDX3285010 and
TMDX3285018
TMDX3285014 and
TMDX3285018

TMS320Cl0/C15 - TMS32OC17
EPROM Programming Adaptor Sockets
40- to 28-pin (TMS320E15/E17)

RTC/PGM320A-06

44- to 28-pin (TMS320E15/E17)

RTC/PGM32OC-06

68- to 28-pin (TMS320E14)

TMDX3270ll0

Additional Target Connector
44-pin PLCC ~TMS320Cl0)

TMDX3288810

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

B-9

SMJ32010
DIGITAL SIGNAL PROCESSOR

documentation support
Extensive documentation supports the first-generation TMS320 devices from product announcement
through applications development. The types of documentation include data sheets with design
specifications. complete user's guides. and 750 pages of application reports published'in the book. Digital
Signal Processing Applications with the TMS320 Family (SPRA012AI.
A series of DSP textbooks is being published by Prentice-Hall and John Wiley & Sons to support digital
signal processing research and education. The TMS320 newsletter. Details on Signal Processing, is published
quarterly and distributed to update TMS320 customers on product information. The TMS320 DSP bulletin
board service provides access to large amounts of information pertaining to the TMS320 family.
Refer to the TMS320 Family Development Support Reference Guide (SPRU011 AI for further information
about TMS320 documentation. To receive copies of first-generation TMS320 literature. call the Customer
Response Center at 1-800-232-3200.

absolute maximum ratings over specified temperature range (unless otherwise noted)t
Supply voltage range. VCC* ....................................... , ... -0.3 V to 7 V
'Input voltage range .................................................. -0;3 V to 7 V
Output voltage range .................. '............................... -0.3 V to 7 V
Continuous power dissipation ................................................. 1.5 W
Maximum operating case temperature ........................................... 100 DC
Minimum operating free-air temperature ......................................... - 55 DC
Storage temperature range .............. " ........................... - 65 DC to 150 DC
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only. and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum·rated conditions for extended periods may affect
device reliability.
*AII voltage values are with respect to VSS.

recommended operating conditions
VCC Supply voltage
VSS Supply voltage
VIH

H~gh~evel

input voltage

NOM

MAX

4.5

5.5

0
All inputs except ClKIN

2
2.8

ClKIN

0.8

em. INT. MC/MiS. AS

0.7

low·level i,nput voltage

IOH
IOL
TC
TA

High·level output current lall outputs)
low·level output current lall outputs)
Maximum operating case temperature

300
2

100

-55

Minimum free-air temperature

TEXAS . "
INSTRUMENTS
I,().,T f)FFI(E Br)./ 144', •

H(JIJ .... rr)tJ: HIM. Ilr)()l

UNIT
V
V
V

X2/ClKIN and data

vil

8-10

MIN

p.A
mA
·C
·C

SMJ32010
DIGITAL SIGNAL PROCESSOR

electrical characteristics over specified temperature range (unless otherwise noted)
PARAMETER
VOH High-level output voltage
VOL Low-level output voltage

TEST CONDmONS
IOH = MAX
'IOL - MAX

I Vo = 2.4 V

IOZ

Off-state output current

VCC

II
ICC

Input current
Supply current

VI = VSS to VCC
VCC = MAX,

Input capacitance

Output capacitance

Data bus
All others
Data bus
All others

MAX

Vo - 0.4 V
fx - MAX,

1 MHz, AU other pins 0 V

MIN TYpt MAX
2.4
3
0.3
0.5
20
-20
±50
180 275
25
15
25
10

UNIT
V
V

,.P,.PrnA

tAli typical values are at Vee = 5 V, TA = 25°C.

CLOCK CHARACTERISTICS AND TIMING
The SMJ32010 can use either its internal oscillator or an extemal frequency source for a clock.
Internal clock option
The internal oscillator is enabled by connecting a crystal across X 1 and X2/ClKIN (see Figure 1). The
frequency of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental
mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW,
and be specified at a load capacitance of 20 pF,
PARAMETER

TEST CONDITIONS

Crystal frequency, f x t
Cl, C2

-55°C to l00"C

MIN

NOM

6.7*
10

MAX

UNIT

20*

MHz
pF

tAn 8 MHz crystal was used in the test.

*Value derived from characterization data. The value is guaranteed bu'" not tested.

Xl
CRYSTAL

...----IDt----.

FIGURE 1. INTERNAL CLOCK OPTION

TEXAS

INSTRUMENTS
PUST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

8-11

SMJ32010
DIGITAL SIGNAL PROCESSOR

external clock option
An external frequency source can be used by injecting the frequency directly into X2/elKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the following table.

timing requirements over recommended operating conditions
PARAMETER
tc(MC)

Master clock cycle time

trlMGI

Rise time master clock input

tllMGt
tw(MCL)

Fall time master clock input

MIN

NOM

Pulse duration master clock low. tc(MC) = 50 ns
Pulse duration master clock high. tc(MC) - 50 ns

tw(MCH)

MAX

UNIT

150

10§

ns
ns

§CLKIN rise and fall times must be less than 10 ns.

switching characteristics over recommended operating conditions
PARAMETER
CLKOUT cycle time

tc(C)

TEST CONDITIONS

tr(C)

CLKOUT rise time

tt(C)

tw(CL)

CLKOUT tan time
Pulse duration, CLKOUT low

tw(CH)

Pulse duration, CLKOUT high

Mill
200

MAX

NOM

UNIT
ns

RL = 82511,

CL = 100 pF,
See Figure 2

8
92

ns
ns

PARAMETER MEASUREMENT INFORMATION
ALL OTHER OUTPUTS
V=2.16V

FROM OUTPUT
UNDER TEST

825!l

0----.
..._--0 TEST POINT
CL

100 pF

FIGURE 2. TEST lOAD CIRCUIT

' '-1 ~ "'-±-- r-- Im'OH
---~-

1.88V-

-----

~::~~:::

---

---- -----

------

VIH (MIN)

2.0V0.8V-

VIL(MAX)

0.5 V -

---__

(b) OUTPUTS

FIGURE 3. VOLTAGE REFERENCE lEVELS

TEXAS.
INSTRUMENTS
I'(J<,T rJFFlr.E fir).! 144"j

•

H()IJ~~r()fJ.

If.lNJ Ilfhl

(MIN) .

VOL (MAX)

(a) INPUT

8-12

--____

SMJ32010
DIGITAL SIGNAL PROCESSOR

input synchronization requirements
For systems using asynchronous inputs to the INT and BIO pins on the SMJ3201 O. the external hardware
shown in the Figure 4 is recommended to ensure proper execution of interrupts and the BIOZ instruction.
This hardware synchronizes the INT and BIO input signals with the rising edge of CLKOUT on the
SMJ3201 O. The pulse width required for these input signals is tc(C). which is one SMJ3201 0 clock cycle.
plus sufficient setup time for the flip-flop (dependent upon the flip-flop used). Note that these input
synchronization requirements apply only to NMOS versions of the SMJ32010 and not to other members
of the SMJ320 family.

o
r-

P
O·TYPE

a r--- iNT

~LlP-FLOP

SMJ32010

+lv

CLKOUT

O-TYPE
FLIP-FLOP

SMJ32010

~------------~ClKOUT

FIGURE 4_ ASYNCHRONOUS INPUT SYNCHRONIZATION CIRCUITS

clock timing
~

14~--I1i- tw(MCHI

,.tr(MCI

l~tc(MCI~
1
~--~
I
1

X2/CLKIN

tw(MCLI

,..

tf(MCI...I

1
CLKOUT

~
-.I !.1
1
1111

NOTE 1:

I..

-+I

tf(CI

tw(CLI

j4- t,(CI

tc(CI

tw(CHI

~
,
I
I

Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts. unless

otherwise noted.

TExAs

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

B-13

SMJ32010

DIGITAL 'SIGNAL PROCESSOR

MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions
TEST

PARAMETER

Delay time CLKOUT. to address
bus valid (see Note 2)

tdl

MIN

CONDITIONS

td2

Delay time CLKOUn to MEN.

td3

Delay time CLKOUT. to MEN!

-15 t

Delay time CLKOUT! to DEN.

td5

Delay time CLKOUT. to DENt

td6

Delay time CLKOUT. to WE.

MAX

lOt
'%tc(C)-10 t

td4

TYP

Delay time CLKOUn to WEt
Delay time CLKOUT. OUT valid to data bus
td8
Time after CLKOUT. that data bus
tdS
starts to be driven
Time after CLKOUT. that data bus
tdl0
stops baing driven
Data bus OUT valid after CLKOUT.
tv
Address bus hold time after
th(A-WMD) WEt, MEN.t, or 'D'E'N!

td7

UNIT

%tc(C) + 15

%tcICI-l0 t
-15 t

%tcICI+15

RL = 825O,

ll.tcICI-l0 t

ll.tcICI+15

CL = 100 pF,
See Figure 2

-lOt

ns
n.

%tc(CI+65
%tcIC)-10 t

ns
%tcIC)+30 t

Address bus setup prior to
tsu(A-MDI MEN. and 'D'E'N.

%tcICI-l0

%tc(CI-45 t

NOTE 2: Address bus will be valid upon WEt, 15mt, or liilEiiIt, and address bus will be valid upon liilEiiI. or
tThese values were derived from characterization data. The values are guaranteed but not tested.

om•.

timing requirements over recommended operating conditions
TEST CONDITIONS
tsulDI
thlDI
\

NOTE 3:

B-14

Setup time data bus valid prior to CLKOUT.
Hold time data bus held valid after CLKOUn
(see Note 31

RL = 825O,
CL = 100 pF,
See Figure 2

Data may be ramoved from the data bus upon MENt or 'D'E'Nt preceding CLKoun.

TEXAS.
INSTRUMENTS

MIN

NOM

MAX

UNIT

SMJ32010
DIGITAL SIGNAL PROCESSOR

memory read

1""..o - - - - - - - - - - t c I C I - - - - - - - - - - -......
..,1
I
I

CLKOUT

~:\.~_ _ _ _ _ _ _ _ _ _

...J

I..

~r-

.ill. . . . _ _ _ _ _ _ _ _

td2.,j

I
mrn ~
'{~:________________~~
\'---+---+--11
I!----t--1
1__
I
---"~
~'~~ ~

thIA-WMDI

tsuiA-MDI

td1

A11-AO _ _ _ _

...

ADDRESS BUS VALID

_ _ _ __

t.--tsuIDI---..l

"",""1---"'1-1- thlDI

D15-DO~~---------------1~----------NOTE 1:

Timing measurements are referenced to and from a low voltage of O.S volts a'nd a high voltage of 2.0 volts, unless otherwise noted.

TEXAS
INSTRUMENTS
1'051 OFFICE BOX 1443

•

HOUSTON. TEXAS 77001

8-15

CUI'

r:II

5!c..
-tW

CII:I

..:i"
..
..3"
en

MEN

;0;;;1

~~
z

td3-r~----!

z
!'T'lUl

Al lAO

~4r

)@(

=:J

-..\

F""\.I

j+-

td3
4

')@(____
10-'''-"1
6 _*~7~)@(--

(")

(

DI5·DO

10)

~""'~ >r-'"'"'

{

)@C

LEGEND:
1.
2.
3.
4.
5.
6.

TBlR INSTRUCTION PREFETCH
DUMMY PREFETCH
DATA FETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
ADDRESS BUS VALID

NOTE 1:

7.
8.
9.
10.
11.
12.

ADDRESS BUS VALID
ADDRESS BUS VALID
INSTRUCTION VALID
INSTRUCTION VALID
DATA INPUT VALID
INSTRUCTION VALID

Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

)~-

-=
CO)

Jio

:i"
CO

JioN
r-

en-

2C)

::::I

CLKOUT

-11:

r""a

=
Q

n
m
en
en
Q

g:::II

CLKOUT \

'---~

,...------...,

\ ~I

MEN

zoo

A11-AO

~~
c::~
~oo

-fiU\.

I
I
I

-v:JNI

--'

d11
I
5 ,1~~6------L:
j

)@(

015-00

==>

--II

rd7
-t-__________________
___
~,

\LJ

t dS----',

r-~9..-1

. .

3
IC

Ij4----

)@(7)@C

~..t

\
3

,t---td6~I

ct_

l--~10--.l

. . tv

("--9~'-~'
~
~I
.

G).--c::II

LEGEND:

1.
2.
3.
4.
5.
6.

TBLW INSTRUCTION PREFETCH
DUMMY PREFETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
ADDRESS BUS VALID
ADDRESS BUS VALID

7.
8.
9.
10.
11.

ADDRESS BUS VALID
INSTRUCTION VALID
INSTRUCTION VALID
DATA OUTPUT VALID
INSTRUCTION VALID

as
;!
,...
fn
as
:.
:a,...

"cn
nc,.
mw

......

fnN

cnc

NOTE 1:

Timing measurements are referenced to and from a low voltage of O.B volts and a high voltage of 2.0 volts. unless otherwise noted .

==-c

rp
.....

..,.

S·

a.
0

::s

ClKOUT

"-.~

I
I

zoo

-.I

t-- td4 --I
____________________________
I

DEN

~oo

I
I

4~ 5 )@C

'-tsu(A-MDI

~'---3----!..~:

A11-AO

I
--I t-1ct5

~I---------------------

--A
i4-lsu (DI ....

015-00

)

r-th(DI

G>--,.---

LEGEND:
1.
2.
3.
4.

IN INSTRUCTION PREFETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
PERIPHERAL BUS VALID

NOTE 1:

5.
6.
7.
8.

lCun

ec..

-IW
:'N
P'"o

tn_0
In
Z

::::!".

:.
-P'"

"ne::a

i \

'-1ct1....-1

I
I

All

MEN

ADDRESS BUS VALID
INSTRUCTION VALID
DATA INPUT VALID
INSTRUCTION VALID

Timing mtiasuremems are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts. unless otherwise noted.

tn
tn

::a

i3.
CLKO~T~
MEN

I
I
I

All-AO

)@(

1\2rL

I
I

>@?l
r-- i

-l

----------------------+I----~

~~
z

:)@(

td6

~r;;i

~9 -I-----!

015-00

)~------«

~_~
6

I:=

a:::I

)@C

I4-td7

I ~!- - - - - - - - - - - - - - - - - - - - - - -

~tdl0---.l

L.--.tdS---t

Cil4r

:/
j4- t dl--t

z
~

I
I
I

I
I

---I tv 14-

~_--__
~

LEGEND:
1.
2.
3.
4.

I"'"

OUT INSTRUCTION PREFETCH
NEXT INSTRUCTION PREFETCH
ADDRESS SUS VALID
PERIPHERAL ADDRESS VALID

5.
6.
7.
S.

ADDRESS BUS VALID
INSTRUCTION VALID
DATA OUTPUT VALID
INSTRUCTION VALID

a;
2

:aI"'"
"'CI

I
.
nc..
I"I'Iw

enN
enCl

....

NOTE 1:

Timing measurements are referenced to and from a low voltage of O.S volts and a high voltage of 2.0 volts, unless otherwise noted.

:::a CI

SMJ32010
DIGITAL SIGNAL PROCESSOR

RESET (RS) TIMING

timing requirements over recommended operating conditions

MIN

tsu(RI

Reset (RSI setup time prior to CLKOUT (see Note 41

tw(RI

RS pulse duration

NOM

MAX

UNIT

5te(C)

switching characteristics over recommended operating conditions
TEST

PARAMETER
ldll

MIN

CONDITIONS
RL = 825

Delay time DENt, WEt, and MENt from RS

CL = 100 pF,
See Rgure 2

ldis(RI Data bus disable time after RS

TYP

MAX

UNIT

%tc(CI+50 t

14 te(CI + 50 t

-RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.

NOTE 4:
tThese values were derived from characterization data. The values are guaranteed but not tested.

reset timing

CLKOUT

-------4,S

'lti<--.-

~IsuIRI

1+----- t w I R I - - - - - - -..!

r-------------~~-----------------------------I I

Noto 9

tclls(Rl--.j

J+-tclll

14-

.>------------...,~(r_--------~(

D15-00

DATA SHOWN RELATIVE TO

DATA (N FROM)-{ DATA IN FROM
PCADDRO.
.PCADDRPC+l

AB = ADDRESS BUS

ADDRESS
BUS

NOTES:

B-20

AB - PC

;>cr-A-B---PC--.-'~~?~______A_B__P_C__O______-J) time iiiiit before CLKOUn

50 t

twllOl Pulse duration HlO
lsullOUSeIup time

BIO~

Hold time BlOt or

tt.1101

8fO~

after CLKOUT~

tValue deriwd from characterization data and not tested.

810 timing
..
~.--.....t- fsullOHl

I
I
I

CLKOUT

I -....OOU.....

iiiii
ISEE NOTE 141

i\
I
--

NOTES:

~IJ
I

I-tfllOl
I
'--twtlOl-

1. Timing measurements are referenced to and from alowvoltageof 0.8vo1tsandahighvoltageof2.0volts, unless otherwise noted.
13. 810 fall time must be less than 15 ns.
,
14. The branch control signal, iiiii, must not transition within ± 50 ns from CLKOUn.

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8-21

SMJ32010
DIGITALSIGIAL PROCESSOR

4O-pin JD ceramic dual-in-line package

NOTE A: Each pin cent....ine is located within 0,2541 (0.010) of its true longitudinal position.
ALL OIMENSIONS ARE IN MILUMETERS AND PARENTHETICALLY IN INCHES

8-22

"'is

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SMJ32010
DIGITAL SIGNAL PROCESSOR

44-pad ceramic chip carrier package

~--------------~:,~~:g:~~:------------~~

·n
I-

15,04 (0.5921 MAX

-----------j

20_'9_'8_1

16.82 (0.6621
16,33 (0.6431

33
15,04 10.592\
MAX

R,JA
R,JC

44.7°C/WATT
l3.3°C/WATT

INDEX CORNER

43.

0.6410,02511

'~10

---c.

0,64 (0,025)
0,38 (0.0151

nmnflonm
·Urd

LJQutJ

r[] Q8 0 EH]

[]

Qfl["lonnn
pjbjlJ
LJkJlJ

DGLJOD8D

0,635 X 1,27

(0.025 X 0.050)
TV'
35 PLACES

D~BGHJEl[]

~I
~1.65

3,05(0.1201
(0.0651

The checkerboard pattern is aligned vertically and is symmetrical horizontally as shown.
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
Texas Instruments reseNas the right to make changes at any time in order to improve design and to supply the best product possible.

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8-23

8-24

SMJ320C10
DIGITAL SIGNAL PROCESSOR
MAY 1987 - REVISED MAY 1989

•
•
•
•
•
•
•

•
•
•
•
•

•
•
•

200-ns Instruction Cycle

SMJ320C10 .•. JD PACKAGE
(TOP VIEW)

144-Word On-Chip Data RAM

1_5K-Word On-Chip Program
ROM - SMJ320M10
External Memory Expansion to a Total
of 4K Words at Full Speed
16-Bit Instruction/Data Word
32-Bit ALU/Accumulator
16 )( 16-BIt Multiply in One Instruction
Cycle

o to

A2/PA2
A3
A4
A5
A6
A7
AS
MEN
DEN
WE
VCC
A9
A10
A11
DO
01
02
03
04
05

A1/PA1
AO/PAO
MC/MP
RS
INT
CLKOUT
X1
X2/CLKIN
BiO
VSS
08
09
010
011
012
013
014
015
07
06

ROMless Yersion - SMJ320C10

16-Bit Barrel Shiftar

Eight Input and Eight Output Channels
16-BIt Bidirectional Data Bus with
40-Megablts-per-Second Transfer Rate
Interrupt with Full Context Save
Signed Two's-Complement Fixed-Point
Arithmetic
CMOS Technology
Single 5-Y Supply

SMJ320C10 ... FD PACKAGE
(TOP VIEW)

description
The SMJ320C10 is the first low-power CMOS
member of the Texas Instruments SMJ320
family of Digital Signal Processors. This device
is a CMOS pin-for-pin compatible version of the
industry-standard TMS32010 Digital Signal
Processor. The 165-mW typical power
diSSipation of the SMJ320C 10 enables powersensitive applications to take advantage of the
SMJ320C 10's high performance. The 16/32-bit
microcomputer was designed to support a wide
range of high-speed and numeric-intensive
applications. The SMJ320C10 combines the
flexibility of a high-speed controller with the
numerical capability of an array processor.
thereby offering an inexpensive alternative to
multi chip bit-slice processors. The highly
pipelined architecture and efficient instruction
set of the SMJ320C 10 provide the capability of
executing more than five million instructions per
second. The instruction set is easily programmed
and contains general-purpose as well as digital
signal processing instructions.

PRDDUCllDI DATA dDouJnontI _ I I InflnnotlIn
..mot • " pnHcatloI .... P. . . . cnIann to
II*ifiAtIeu III'" 110..... " lna Inttnll_
.-..n wtrrtllly. PradlCll. . . . . . . . . . . not
- . I I , I.... ttotI•• " til plnII. . . ..

::!;:::: ::

10..

Il-zltJ)~O;::UNPl"'''''CQ
a::",,«z««<
6 5 4 3 2 1 44 43424140
0
39
38
37
36
35
34
33
32
31
30
29
18,1912021 22 232425~~~

CLKOUT 7
X1 8
X2/CLKIN 9
BiO 10
NC 11
VSS 12
08 13
09 14
010 15
011 16
012 17

A7
A8
MEN
DEN
WE
VCC
A9
A10
A11
DO
01

UPl ............ CQ ....... PlNU
zCiCiCiccccccz

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8-25

SMJ320C10
DIGITAL SIGNAL PROCESSOR

functional block diagram
Xl
CLKOUT

X2tCLKIN

,-----------------------------,

WE
DEN

MEN
iiO

,...--"""--..., ')

r----~___.
INSTRUCTION

MCt~

INT

iiS

PROGRAM
ROMt
11.6K WORDS)

All-AOt
PA2-PAO
.......~-D15-DO

16
8

ADDRESS
DATA RAM
1144 '" 18)

LEGEND:

DATA

ACC= Accumulator
ARF' = Auxiliary register pOinter
ARO = Auxiliary register 0
AR1 = Auxiliary register 1

DP
PC
P
T

Data page pOinter
Program counter
P register

T register

tThe Program ROM is available in SMJ320M 10 onlv.

8-26

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SMJ320C10
DIGITAL SIGIAL PROCESSOR

PIN NO~ENCLATURE
NAME
A ll-AO/PA2-PAO

I/O

iiiO

ClKOUT
015-00

0
I/O

DEN

iN'i'
MciMP
MEN

I
I

AS
VCC
VSS
WE
Xl
X2/CLKIN

0
0
I
I
I

0
0
I

DEFINITION
External address bus. I/O port address multiplexed over PA2-PAO.
External polling inpu1
SyS1am clock outpUt. 14 crystal/ClKIN frequency
16:bit parallel date bus
Data enable for device input data on 01 5-00
External interrupt input

Memory mode select pin. High selects microcomputer mode. low selects microprocessor mode.
Memory eneble indicates that 015-00 will accept external memory instruction.
No connaction
Resat for initializing the device
+5 V supply
Ground
Writa enable for device output data on 01 5-00
Crystal output for intarnal oscillator
CryS1a1 inpu1 for intamal oscillator or external syatem clock input

architecture
The SMJ320 family utilizes a modified Harvard architecture for speed and flexibilitv. In a strict Harvard
architecture, program and data memory lie in two separate spaces, permitting a full overlap of instruction
fetch and execution. The SMJ320 family's modification of the Harvard architecture allows transfers between
program and data spaces. thereby increasing the flexibility of the device. This modification permits
coefficients stored in program memory to be read into the RAM,. eliminating the need for a separate
coefficient ROM. It also makes available immediate instructions and subroutines based on computed values.
32-blt ALU/accumulator
The SMJ320 first-generation devices contain a 32-bit ALU and accumulator for support of double-precision,
two's-complement arithmetic. The ALU is a general-purpose arithmetic unit that operates on 16-bit words
taken from the data RAM or derived from immediate instructions. In addition to the usual arithmetic
instructions, the ALU can perform Boolean operations, providing the bit manipulation ability required of
a high-speed controller. The accumulator stores the output from the ALU and is often an input to the ALU.
It operates with a 32-bit wordlength. The accumulator is divided into a high-order word (bits 31 through
16) and a low-order word (bits 15 through 0). Instructions are provided for storing the high- and low-order
accumulator words in memory.
shifters
Two shifters are available for manipulating data. The ALU barrel shifter performs a left-shift of 0 to 16
places on data memory words loaded into the ALU. This shifter extends the high-order bit of the data word
and zero-fills the low-order bits for two's-complement arithmetic. The accumulator parallel shifter performs
a left-shift of 0, 1, or 4 places on the entire accumulator and places the resulting high-order accumulator
bits into data RAM. Both shifters are useful for scaling and bit extraction.

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8-27

SMJ320C10
DIGITAL SIGNAL PROCESSOR

16 x 16-blt parallel multiplier
The multiplier performs a 16 x 16-bit two's-complement multiplication with a 32-bit result in a single
instruction cycle. The multiplier consists of three units: the T Register, P Register, and multiplier array.
The 16-bit T Register temporarily stores the multiplicand; the P Regi$ter stores the 32-bit product. Multiplier
values either come from the data memory or are derived immediately from the MPYK (multiply immediate)
instruction word. The fast on-chip multiplier allows the device to perform fundamental operations such
as convolution, correlation, and filtering.
data and program memory
Since the SMJ320 devices use a Harvard architecture, data and program memory reside in two separate
spaces. The SMJ320C 10 device has 144 words of on-chip data RAM and 1.5K words of on-chip program
ROM. The SMJ320C1 0 is capable of executing up to 4K words of external memory at full speed for those
applications requiring external program memory space. This allows for external RAM-based systems to
provide multiple functionality.
microcomputer/microprocessor operating modes
The SMJ320C1 0 offers two modes of operation defined by the state of the MC/MP pin: the microcomputer
mode (MC/MP = 1) or the microprocessor mode (MC/MP = 0). In the microcomputer mode, the on-chip
ROM is mapped into the memory space with up to 1.5K words of internal memory and 2.5K words of
external memory. In the microprocessor mode, 4K words of memory are external.
interrupts and subroutines
I

The SMJ320 first-generation devices contain a four-level hardware stack for saving the contents of the
program counter during interrupts and subroutine calls. Instructions are available for saving the device's
complete context. PUSH and POP instructions permit a level of nesting restricted only by the amount of
available RAM. The interrupts used in these devices are maskable.
Input/output
The 16-bit parallel data bus can be utilized to perform 1/0 functions in two cycles. The I/O ports are addressed
by the three LSBs on the address lines. In addition, a polling input for bit test and jump operations (BIO)
and, an interrupt pin (lNT) have been incorporated for multitasking.

8-28,

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SMJ320C10
DIGITAL SIGNAL PROCESSOR

instruction set
A comprehensive instruction set supports both numeric-intensive operations, such as signal processing,
and general-purpose operations, such as high-speed control. All of the first-generation devices are objectcode compatible and use the same 60 instructions. The instruction set consists primarily of single-cycle
single-word instructions, permitting execution rates of more than six million instructions per second. Only
infrequently used branch and 110 instructions are multicycle. Instructions that shift data as part of an
arithmetic operation execute in a single cycle and are useful for scaling data in parallel with other operations.
Three main addressing modes are available with the instruction set: direct, indirect, and immediate
addressing.
direct addressing
In direct addressing, seven bits of the instruction word concatenated with the 1-bit data page pointer form
the data memory address. This implements a paging scheme in which the first page contains 128 words,
and the second page 'contains up to 16 words.
indirect addressing
Indirect addressing forms the data memory address from the least-significant eight bits of one of the two
auxiliary registers, ARO and AR 1. The Auxiliary Register Pointer (ARP) selects the current auxiliary register.
The auxiliary registers can be automatically incremented or decremented and the ARP changed in parallel
with the execution of any indirect instruction to permit single-cycle manipulation of data tables. Indirect
addressing can be used with all instructions requiring data operands, except for the immediate operand
instructions.
Immediate addressing
Immediate instructions derive data from part of the instruction word rather than from the data RAM. Some
useful immediate instructions are multiply immediate (MPVK), load accumulator immediate (LACK), and
load auxiliary register immediate (LARK).
instruction sat summary
Table 1 lists the symbols and abbreviations used in Table 2, the instruction set summary. Table 2 contains
a short description and the opcode for each SMJ320 first-generation instruction. The summary is arranged
according to function and alphabetized within each functional group.
TABLE 1. INSTRUCTION SYMBOLS
SYMBOL

ACC
0
I

K
PA
R

S
X

MEANING
Accumulator
Data memory address field
Addressing mode bit
Immediate operand fiald
3-bit port ~ddress field
l-bit operand field specifying auxiliary register
4-bit left-shift code
3-bit accumulator left-shift field

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8-29

SMJ32DC10
DIGITAL SIGNAL PROCESSOR

TABLE 2. SMJ320 FIRST-GENERATION INSTRUCTION SET SUMMARY
ACCUMULATOR INSTRUCTIONS
MNEMONIC

DESCRIPTION

ABS

Absolute value of accumulator

ADD

Add to accumulator with shift

AOOH
ADDS

Add to accumulator with no sign

Add to high-order accumulator bits

OPCODE

NO.

CYCLES

WORDS

1
1
1
1

1514131211109 8 7
0 1 1 1 1 1 1 1,1
0 0 0 0 +-S. I
0 1 1 0 0 0 0 0 I
0 1 1 0 0 0 0 1 I

1
1
1
1
1

0 1 1 1 1 0 0 1
0 0" 0 +-S+
0 1 1 1 1 1 1 0
0 1 1 1 1 0 1 0
0 1 0 1 1 .X.

1
1
1
1
1

0
0
0
0
0

1
0
1
1
1

0
0
1
1
1

1
1
0
0
0

1
1
1
1

0
0
0
0

1
1
1
1

1 1 0 0 0 I + - - 0......-----+
1 i 1 1 1 1 0 0 0 1 ·0 0 1
0 0 1 0 1 I +---0----+
0 0 1 1 0 I 4-----0----+

INSTRUCTION REGISTER

6 5 4 3 2 1 0
0 0 0 1 0 0 0
+---0----+
+---0----+
+---0----+

extension

AND

AND with accumulator

LAC

Load accumulator with shift

LACK

Load accumulator immediate

OR
SACH

OR with accumulator
Store high-order accumulator bits with

+---0----+

+--0----+
K----+

4
I
I

+--0----+
+--0----+

+---0--;+

+--0----+

shift
SACL

Store low-'order accumulator bits

SUB

Subtract from accumulator with shift

SUBC

Conditional subtract Ifor divide}

SUBH
SUBS

Subtract from high-order accumulator bits
Subtract from accumulator with no sign

0 0 0 0
+-S.
0 1 0 0
0 0 1 0
0 0 1 1

+---0----+

I
I

+--0----+
+--0----+

extension

XOR

Exclusive OR with accumulator

ZAC

Zero accumulator

ZALH

Zero accumulator and load high-order bits

ZALS

Zero accumulator and load low-order bits
with no sign extension

AUXILIARY REGISTER AND DATA PAGE POINTER INSTRUCTIONS
MNEMONIC

DESCRIPTION

LAR

Load auxiliary register

LARK
LARP

Load auxiliary register immediate

LOP

Load data memory page pointer

LOPK

Load data memory page pointer immediate

MAR

Modify auxiliary register and pointer

SAR

Store auxiliary 'register

8-30

Load auxiliary register pointer immediate

NO.

CYCLES

WORDS

1
1
1
1
1
1
1

OPCOOE
INSTRUCTION REGISTER

1514131211109
0 0 1 1 1 0 0
0 1 1 1 0 0 0
0 1 1 0 1 0 0
0 1 1 0 1 1 1
0 1 1 0 1 1 1
0 1 1 0 1 0 0
0 0 1 1 0 0 0

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8 7 6 5 4 3 2 1 0
R I
R

0
1
0
0
R

+---0----+

K----+
1 0 0 0 0 o 0 K
I +--0----*
0 0 0 0 0 0 0 K
I

+-'--- 0 ----+

04-- 0----+

SMJ320C10
DIGITAL SIGNAL PROCESSOR

TABLE 2. SMJ320 FIRST-GENERATION INSTRUCTION SET SUMMARY (CONTINUED)
BRANCH INSTRUCTIONS
MNEMONIC

DESCRIPTION

NO.

CYCLES

WORDS

Branch unconditionally

BANZ

Branch on auxiliary register not zero

BGEZ

Branch if accumulator ;;:: 0

BGZ

Branch if accumulator > 0

BIOZ

Branch on

BiO ""

BLEZ

Branch If accumulator s 0

BLZ

Branch if accumulator

< 0

BNZ

Branch If accumulator

Branch on overflow

Branch If accumulator

CALA
CALL

Call subroutine from accumulator
Call subroutine immediately

2
2

RET

Return from subroutine or interrupt routine

- a

OPCODE
INSTRUCTION REGISTER
1514131211109 B 7
1

a a

a a a a a a a a

a a a a +-- BRANCH ADDRESS - - +
1 1 1 1 a 1 a a a a a a a a a a
a a a a +-- BRANCH ADDRESS - - +
1 1 1 1 1 1 a 1 a a 0 a a 0 a a
0 a a a +-- BRANCH ADDRESS - - +
1 1 1 1 1 1 a a a a 0 a a a a a
0 a a 0 +-- BRANCH ADDRESS - - +
1 1 1 1 a 1 1 a a a 0 a a a a a
a a a a +-- BRANCH ADDRESS - - +
1 1 1 1 1 a 1 1 0 a 0 a a a a a
a a a a +-- BRANCH ADDRESS - - +
1 1 1 1 1 a 1 a 0 a o 0 0 a 0 a
a a a a +-- BRANCH ADDRESS--+
1 1 1 1 1 1 1 a a a 0 a a a a a
a a a a +-- BRANCH ADDRESS ~
1 1 1 1 a 1 a 1 0 a 0 a 0 a 0 a
a a a a ~ BRANCH ADDRESS--+
1 1 1 1 1 1 1 1 a a a a a a a a
a a a a ~ BRANCH ADDRESS ~
a 1 1 1 1 1 1 1 1 a a a 1 1 a a
1 1 1 1 1 a a a a a 0 a a a a a
0 a a 0 +-- BRANCH ADDRESS--+
0 1 1 1 1 1 1 1 1 a 0 a 1 1 a 1

T REGISTER. P REGISTER. AND MUL TIPL Y INSTRUCTIONS
MNEMONIC

DESCRIPTION

NO.

CYCLES

WORDS

APAC

Add P register to accumulator

LT
LTA

Load T register

LTA combines LT and APAC into one

LTD

LTD combines LT. APAC. and DMOV into

OPCODE
INSTRUCTION REGISTER
1

a
a

1 0

a a

7 6 5 4 3 2 1 0
1 a 0 a 1 1 1 1
I +--D~
I +--0--+

+--D~

a a

a
a

1514131211109 8
1

instruction
one instruction

MPY

Multiply with T register, store product in

P register

MPYK

Multiply T register with immediate

•

operand; store product in P register

PAC

Load accumulator from P register

SPAC

Subtract P register from accumulator

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a
a

0
0

1 0

a
a a a
1

B-31

SMJ32OC10
DIGITAL SIGNAL PROCESSOR

TABLE 2. SMJ320 FIRST-GENERATION .INSTRUCTION SET SUMMARY (CONCLUDED)
CONTROL INSTRUCTIONS
MNEMONIC

DESCRIPTION

NO.

CYCLES

WORDS

1
1

DINT

Disable interrupt

EINT

Enable interrupt

LST

Load status register

NOP

No operation

POP

POP stack to accumulator

PUSH

PUSH stack from accumulator

2
2

ROVM

Reset overflow mode

SOVM

Set overflow mode

SST

Store status regist~r

OPCODE
INSTRUCTION REGISTER

1514131211109 8 7 6 5 4 3 2 1 0
0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1
0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0
0 1 1 1 1 0 1 1 I 4---0----+
0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1
0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0
0 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0
0 1 1 1 1 1 1 1 1 '0 0 0 1 0 1 1
0 1 1 1 1 1 0 0 1 4---0--+

110 AND DATA MEMORY OPERATIONS
MNEMONIC

DESCRIPTION

OMOV

Copy contents of data memory location

Input data from port

OUT
TBLR

Output data to port

OPCODE

NO.

CYCLES

WORDS

2
2
3

1 0

0
0 1
1 1 0 0

INSTRUCTION REGISTER

1514131211109 8 7 6 5 4 3 2 1 0
0 1 1 0 1 0 0 1 1 +---0----+

into next higher location

Table read from program memory to data

4PA.

4PA+
1 1 1

+---0----+
+---0----+
+---0----+

+---0----+

RAM
TBLW

Table write from data RAM to program
memory

development support products
Together. Texas Instruments and its authorized third-party suppliers offer an extensive line of development
support products to assist the user in all aspects of TMS320 first-generation-based design and development.
These products range from development and application software to complete hardware development and
evaluation systems. Table 4 lists the development support products for the first-generation TMS320 devices.
System development may begin with the use of the simulator. evaluation module (EVM). or emulator (XDS).
along with an assembler/linker. These tools give the TMS320 user various means of evaluation. from
software simulation of the first-generation TMS320s (simulator) to full-speed in-circuit emulation with
hardware and software break point tracing and timing capabilities (XDS).
Software and hardware can be developed simultaneously by using the macro assembler/linker or simulator
for software development. the XDS for hardware development. and the evaluation module for both software
development and limited hardware development.
Many third-party vendors offer additional development support for the first-generation TMS320s. including
assembler/linkers. simulators. high-level languages. applications software. algorithm development tools.
application boards. software development boards. and in-circuit emulators. Refer to the TMS320 Family
Development Support Reference Guide (SPRU011 A) for further information about TMS320 development
support products offered by both Texas Instruments and its third-party suppliers.

8-32

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SMJ320C10
DIGITAL SIGNAL PROCESSOR

Additional support for the TMS320 products consists of an extensive library of product and applications
documentation. Three-day DSP design workshops are offered by the TI Regional Technology Centers (RTCs).
These workshops provide insight into the architecture and the instruction set of the first-generation
TMS320s as well as hands-on training with the TMS320 development tools. When technical questions
arise in regard to a TMS320 member, contact Texas Instruments TMS320 Hotline at (713) 274-2320.
Or, keep informed on the latest TI and third-party development support tools by accessing the libraries
of application source code via the DSP Bulletin Board Service (BBS) at (713) 274-2323. The BBS provides
access for the 2400-/1200-/300-bps modems.

documentation support
Extensive documentation supports the first-generation TMS320 devices from product announcement
through applications development. The types of documentation include data sheets with design
specifications, complete user's guides, and 750 pages of application reports published in the book Digital
Signal Processing Applications with the TMS320 Family.
A series of DSP textbooks is being published to support digital signal processing research and education.
The first book, DFT/FFT and Convolution Algorithms, is now available. The TMS320 newsletter, Details
on Signal Processing, is being published quarterly and distributed to update TMS320 customers on product
information. The TMS320 DSP bulletin board service provides access to large amounts of information
pertaining to the TMS320 family.
Refer to the TMS320 Family Development Support Reference Guide for further information about TMS320
documentation. To receive copies of first-generation SMJ320 literature, call the Customer Response Center
at 1-800-232-3200.

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8-33

SMJ320C10
DIGITAL SIGIALPROCESSOR

TABLE 3. TMS320 FIRST-GENERATION SOFTWARE AND HARDWARE SUPPORT
SOFTWARE TOOLS
Macro Assembler/Unker
PC/MS-DOS
VAXIVMS
VAX ULTRIX
SUN-3 UNIX

PART NUMBER
TMDS324285Q-02 ,
TMDS3242250-08
TMDS3242260-08
TMDS3242550-08

Simulator
PC/MS-DOS
VAXIVMS

TMDS3240811-02
TMDS3240211-08

Digital Filter Design Package (DFDP)
IBM PC PC·DOS

DFDP/lBMOO2

DSP Software Library
PC/MS-DOS
VAXIVMS

TMDC3240B 12-12
TMDC3240212-18

TMS320 Ben 212A Modem Software
PC/MS-DOS

TMDX3240813-12

Date Encryption Standard Software
PC/MS-DOS
HARDWARE TOOLS
Evaluation Tools
Evaluation Module IEVM)
Analog Interface Board 1 IAIB1)
Analog Interface Board 2 (AIB2)
EPROM DSP Starter Kit ITMS320E15)

TMDX3240814-12
PART NUMBER
RTC/EVM320A-03
RTC/EVM320C-06
RTC/AIB320A.:o6
RTC/EVM320E·15

XDS/22 Emulators
TMS320Cl0/C15
TMS320C14
TMS320C17

TMDS3262211
TMDX3282214
TMDX3262217

)(DS/22 Upgrade Kits
TMS32010 - TMS320Cl0/C15
TMS320Cl0/C16 - TMS320C14

TMDS3282215
TMDX3286010 and
TMDX3285018
TMDX3285014 and
TMDX3285018

TMS320Cl0/C15 - TMS320C17

8-34

EPROM Programming Adaptor Soc.kets
40- to 28-pin (TMS320E15/E17)
44- to 28-pin (TMS320E15/E17)
68· to 28-pin (TMS320E14)

RTC/PGM320A-06
RTC/PGM320C-06
TMDX3270110

Additional Targat Connector
44'pin PLCC ITMS320Cl0)

TMDX3288Bl0

TEXAS

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

SMJ320C10
DIGITAL SIGNAL PROCESSOR

absolute maximum ratings over specified temperature range (unless otherwise notedl t
Supply voltage range, VCC* ........................................... -0.3 V to 7 V
Input voltage range .................................................. -0.3 V to 7 V
Output voltage range ................................................. - 0.3 V to 7 V
Continuous power dissipation: ................................................ 0.33 W
Maximum operating case temperature ........................................... 125 °C
Minimum operating free-air temperature ......................................... - 55 °C
Storage temperature range ......................................... - 65 °C to + 150 °C
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
*AII voltage values are with respect to VSS.

recommended operating conditions
MIN
4.5

VCC Supply voltage
VSS Supply voltage
VIH

.1 All inputs except ClKIN
High-level input voltage I ClKIN

Vil
IOH
IOl
TA
TC

low-level input voltage (All inputs)
High-level output current (All outputs)
Low-level output current (All outputs)
Operating free-air temperature
Operating case temperature

NOM MAX
5
5.5
0

2
3

UNIT
V
V
V

125

V
p.A
mA
·C
·C

MAX

UNIT

0.8
-300
2
-55

electrical characteristics over specified temperature range (unless otherwise noted I
PARAMlTER

TEST CONDmoNS

VOH High-level output voltage
VOL low-level output voltage
IOZ

Off-state output current

Input current

ICC' Supply current
Ci
Co

VCC

1 SMJ320Cl0
1 SMJ320C10-14

Input capacitance

= MAX ~

Data bus

MIN TYpi
2.4

VCC-CAY'
0.3

Vo - 2.4 V
Vo = 0.4 V

VI = VSS, VCC = MAX
VCC - 5.5 V, fx - MAX
VCC - 5.5 V, fx - MAX

V
0.5
20
-20
±50
60
50

p.A
p.A
mA

25#

Data bus
All others

Output capacitance

= MAX
IOH = 20 p.A (see Note
IOl = MAX
IOH

= 1 MHz, All other pins 0 V

15#
25#

10#

All others

fAil typical values except for ICC are at VCC = 5 V, TA = 25·C.
, ICC characteristics are inversely proportional to temperature; i.e., ICC decreases approximately linearly with temperature.
#Value derived from characterization data and is guaranteed to limit but not tested. NOTE 1: This voltage specification is included for interface to HC logiC. However, note that all other timing paramaters defined in this
data sheet are specified for TTL logic levels and will differ for HC logic levels.

TEXAS ."

INSTRUMENlS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

8-35

SMJ320C10
DIGITAL SIGNAL PROCESSOR

CLOCK CHARACTERISTICS AND TIMING
The SMJ320C10 can use e.ither its internal oscillator or an external frequency source for a clock.

Internal clock option

\
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The
frequency of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental
mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW,
and be specified at a load capacitance of 20pF.
PARAMETER

Crystal frequency, f x'

TEST CONDITIONS

I SMJ320Cl0
I SMJ320Cl0-14

MIN NOM
6.7#

-55°C to 125°C

MAX
20.5#

6.7#

20.6#

Cl,C2

UNIT
MHz
pF

'An 8 MHz crystal was used in the test.
'value derived from characterization data and is guaranteed but not tested.

FIGURE 1, INTERNAL CLOCK OPTION

extemal clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the table below.

timing requirements over recommended operating conditions

tc(MCI
tr(MCI
tflMCI
tw(MCPI
tw(MCLI
tw(MCHI

MIN
48.78
69.44

SMJ32OC10
I SMJ32OC10-14
Rise time master clock input (see Note 21
Fall tima master clock input ·(see Nota 21
Master clock cycle time

NOM

UNIT
ns
ns
ns,

5
6

Pulse duration master clock#

0.476tc (MCI

Pulse duration master clock low, tc(MCI
Pulse duration master clock high, tc(MCI

MAX
150
150

= 50 ns
= 50 ns

0.625tc(MCI
20
20

ns
ns
ns

\
switching characteristics over recommended operating conditions
PARAMETER
tc(CI

*
CLKOUT cycle time

TEST CONDITIONS

I SMJ320Cl0
I

SMJ320C10-14

CLKOUT rise time
tr(CI
CLKOUT fall time
tf(CI
twlCLI Pulse duration, CLKOUT low
twlCHI Pulse duration, CLKOUT high
td(MCCI Delay time CLKINt to CLKOUn

RL = 8250,
CL = 100 pF,
See Figure 2

MIN NOM
195.12
278.78
10
8
92
90
20

*tc(CI i. the cycle time of CLKOUT, i.e., 4*tc(MCI (4 times CLKIN cycle time if an external oscillator is usedl.
IValue derived from characterization data and is guaranteed but not tasted.
NOT~_2: CLKIN rise and fall times must be less than IOns.

8-36

TEXAS .."

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

MAX
600
600

UNIT
ns
ns
ns
ns
ns

SMJ320C10
DIGITAL SIGNAL PROCESSOR

MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions
TEST
CONDITIONS

PARAMETER
tdl

Delay time CLKOUT! to address bus valid (see Note 3)

!d2

Delay time CLKOUT! to tlEN!

td3

Delay time CLKOUn to ~t

!d4

Delay time CLKOUn to ~!

td5

Delay time CLKOUn to 15mT

!de

Delay time CLKOUT! to WEl

td7

MIN

TVP

MAX

lOt

%tc (CI-5 t

%tc(CI+15

-lOt

%tc (C)-5 t
RL

825

-lOt

!d8
!d9

Time after CLKOUn that data bus starts to be driven

!dl0
tv

Time after CLKOUT! that data bus stops being driven
Data bus OUT valid after CLKOUn

%tc (C)-5 t

CL = 100 pF,

Delay time CLKOUn to WET
Delay time CLKOUT! OUT valid to data bus

%tc(C) + 15
%tc(C) + 15

-lOt

See Figure 2

15
%tc(C) +65

%tc(C)-5 t

ns
ns
ns
ns
ns
ns
ns
ns
ns

%tc(C)+40 t
%tc(CI-l0

!au(A-MD) Address bus satup time prior to tlEN! or DEN!

UNIT

ns
ns

%tc (C)-45

th(A-WMD) Address hold time after WET, tlENT, or 15mT
NOTE 3: Address bus will be valid upon WEt, DENt, or mJilT.
tValue derived from characterization d.,. and is guaranteed but not tested.

timing requirements over recommended operating conditions
tsu(D)
th(D)
NOTE 4:

TEST CONDITIONS
RL = 825 n,
CL = 100 pF,
See Figure 2

Setup time data bus valid prior to CLKOUT l
Hold time data bus held valid after CLKOUn
(see Note 4)

MIN NOM
50
0

MAX

UNIT
ns
ns

Data may be removed from the data bus upon !\lENt or ~T preceding CLKOUn.

TEXAS ",

8-37

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

SMJ320C10
DIGITAL SIGNAL PROCESSOR

RESET (RSI TIMING
switching chatacteristics Over recommended operating conditions
TEST CONDmONS

PARAMETER

telll

Delay time DENt. WEt. and ~t from

tdis(R)

Data bus disable time after 1m

MIN

MAX

UNIT

Y, tc(C) + 50 t

%tc(C)+50 t

TYP

RL - 825 D.
CL = 100 pF.
See Figure 2

tValue derived from characterization data and is guaranteed but not tested.

timing requirements over recommended operating conditions
MIN

(1m)

tau(R)

Reset

tWIRl

1m pulse duration

NOTE 5:

im can

setup time prior to CLKOUT (see Note 5)

NOM

MAX

UNIT

5tc(C)

occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.

INTERRUPT (INTI TIMING
timing requirements over recommended operating conditions \
MIN
tf(lNT)

Fall time INT (see Note 6)

tw(lNT)

Pulse duration l1ii'i'

MAX

tsu(lNT) Setup time l1ii'i'~ before CLKOUn
NOTE 6:

NOM

UNIT
ns

tc(C)

INT fall time must be less than 15 ns.

810 TIMING
timing requirements over recommended operating conditions
MIN

NOM, MAX

UNIT

am (see Note 7)
Pulse duration am

tc(C)

fau(lO) Setup time am~ before CLKOUn

,ns

tfnol
tw(lO)

NOTE 7:

8-38

Fall time

BIO fall time must be less than 15 ns.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

SMJ320C10
DIGITAL SIGNAL PROCESSOR

PARAMETER MEASUREMENT INFORMATION
V-2.15V

Rl = 8260
FROM OUTPUT O - - t . . _ - o
UNDER TEST
TEST
POINT

Tel

= 100 pF

-=
FIGURE 2. TEST LOAD CIRCUIT

.oV-1 ~
---~-

1.88V'"

-----

---

0.92 V_
0.80 v....

---

VIH (MIN)

Vil (MAX)

o
(a)

INPUT

"Vd-- :;E--t--2.0V0.8 V
~V""

-----__
_ ___

VOH(MIN)

~~~

(b) OUTPUTS

FIGURE 3. VOLTAGE REFERENCE LEVELS

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

8-39

SMJ320C10
DIGITAL SIGNAL PROCESSOR

TIMING DIAGRAMS
This section contains all the timing diagrams for the SMJ320 first-generation devices. Refer to the top corner
for the specific device.
Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts,
unless otherwise noted.

clock timing
~ ,... trlMCI

X2/ClKIN

1--* twlMCHI

.....

1 ~ tclMCI
1
I,
1

----t

...--~ twlMCPl t

~--~

I
I
: ttlMCI...! ....

l1li

~IcIIMcclt
ClKOUT

~,,"I_ _ _ _ _ _ _ _ _ _ _ _ __

-1"-

114

trici

I
I

twICll------ti

1111

If
I

~
I

...,' !.- tfici

twlCHI

tcici

t tdlMCCI and twlMCPI are referenced to an intermediate level of 1.5 volts on the ClKIN waveform.

memory read timing

CLKOUT

'd3

r
\l
-i I-

_~II
L

'.,CI

I
'd2

-----I
I

td1

----,

Vi
I..;I

tsulA-MDI

\'--_

,..,- 'hIA-WMDI

----------~~;--------AD-D-RE-S-S-.U-S-V-A-LlD----------~~~_ _ ___

~tsu'D'~th'D)
015-00

8-40

______-J)

(

INSTRUCTION IN

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

V~LlD

)>-----------

SMJ320C10
DIGITAL SIGNAL PROCESSOR

TBLR instruction timing

I-td1~
A11-AO

~_ _ _ __

)@(

)@(
;;:j ~thlol

I4-t.u lOI
015-00

~>-----<

Ci0

G=>

{

;

Ci0

LEGEND:
1.
2.
3.
4.
5.
6.

TBLR INSTRUCTION PREFETCH
DUMMY PREFETCH
DATA FETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
ADDRESS BUS VALID

7.
8.
9.
10.
11.
12.

ADDRESS BUS VALID
ADDRESS BUS VALID
INSTRUCTION VALID
INSTRUCTION VALID
DATA INPUT VALID
INSTRUCTION VALID

TBLW Instruction timing

CLKOUT

I
I

'------":'1
I

A"-AO

=::>®<_____4_)@(-----.,;....)@(_---:-'>®<_ _>®C
-.j~td7
------~--------~~--td~8~~~t.-----------

I--

t d6---j

i--td"--j

Iot-td10~

015·00

LEGEND:
1.
2.
3.
4.
5.
6.

TBLW INSTRUCTION PREFETCH
DUMMY PREFETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
ADDRESS BUS VALID
ADDRESS BUS VALID

7.
8.
9.
10.
11.

ADDRESS BUS VALID
INSTRUCTION VALID
INSTRUCTION VALID
DATA OUTPUT VALID
INSTRUCTION VALID

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

8-41

SMJ320C10
DIGITAL SIGNAL PROCESSOR

IN Instruction timing
CLKDUT

MEN~

\
I
If

"'-------J

I
A"·AO

'su'OI

'dS--.I

J4--

14""-

'd4

--------------~i

V~---------------~'h'OI

=:>>----------C]('-_________A_B__-_P_C__-_O________~~ 1

AS forces DEN. WE. and MEN high and places data bus DO through 015 in a high-impedance state_ AS outputs land program

counter) are synchronously cleared to zero after the next complete elK cycle from RS!.
B. AS must be maintained for a minimum of five clock cycles.
C. Resumption of normal program will commence after one complete elK cycle from RSr.
D. Due to the synchronizing action on AS, time to execute the function can vary dependent upon when
the eLK cycle_
E. Diagram shown is for definition purpose only. DEN. WE, and MEN are mutually exclusive.
F. During a write cycle, RS !iT1ay produce an invalid write address.

RSt

AS!

occur in

interrupt timing

CLKOUT

---.I

I------'*tsuUNTI

~I==------

iNT

'fIlNTI-..j

twUNTI

BIOtlmlng
CLKOUT

~
iili

tsuliOI

~
tfflOI-ti

14j4

\ '---~/

t~nol

TEXAS ."

INSTRUMENTS
POST OFFICE

sox

1443 •

HOUSTON, TEXAS 77001

8-43

SMJ320C10
DIGITAL SIGNAL PROCESSOR

MECHANICAL DATA
4O-pin JD ceramic dual-in-line package

L
r.

~1~~~~~~I:::]~~~~·~·~]~:~~~
0)

15.24±0.264
10.800 ±0.0101 ~

51.3112.0201 MAX

F9
"M~,._j~'Tj~l~~~"~..~.~~H~M~.~,~~"~. ~ ~ ~ .~ ~ ~ml l ~~ ~jE"~,:':~;'"
0.60810.0201 MIN

•

1~4.7010.185IMAX

0.457±0.076
10.018±0.0031

ISoeNo•• AI

1.27.0.254
10.060±0.0101

J l= [

NOTE A: Each pin centerline is located within 0.254 10.010) of its true longitudinal position.
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

8-44

TEXAS ~

INSJRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

+0015]

0.050 -0:020

SMJ320C10
DIGITAL SIGNAL PROCESSOR

MECHANICAL DATA
44-pad ceramic chip carrier package

~--------------~:.:~:~:~::------------~~
1----------16.0410.5921 MAX----~.otl
26

188210.::,
1••3310.
I

IIfJA - 44.7°CIWATT
13.3°CIWATT

IIfJC -

INDEX CORNER

IIIIIII
f l l iU1111
11111111

IIIII1I
11111111
~I
I---I-m-m:ml
3.0510.1201

The checkerboard pattern is aligned vertically and is symmetrical horizontally as shown.

ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
Texas Instruments reserves the right to make changee at any time in order to improve design and to supply the best product ponible.

TEXAS

INSTRUMENTS
POST OFFICE BOX 1443 •

8-45

HOUSTON. TEXAS 77001

8-46

SMJ320C15. SMJ320C15·25
DIGITAL SIGNAL PROCESSORS
MAY 1989

•

JD PACKAGE

Instruction Cycle Timing:
- 160 ns (SMJ320C15·25)
- 200 ns (SMJ320C15)

(TOPVIEWI

•

256 Words of On·Chip Data RAM

•

4K Words of On·Chip Program ROM

•

External Memory Expansion up to 4K Words
at Full Speed

•

16·Bit Instruction/Data Word

•

Object·Code and Pin· For· Pin Compatible
with SMJ32010 and SMJ320C10

•

16 x 16·Bit Multiplier with 32·Bit Product

•

0 to 16·Bit Barrel Shifter
Eight Input and Eight Output Channels
On·Chip Clock Oscillator

•

Single 5·V

•

Device Packaging: '
- 4O·Pin DIP
- 44·Pad LCCC

DEN
WE
VCC
A9
A10
A11
DO
01
02
03
04
05

VSS
08
09
010
011
012
013
014
015
07
06

32·Bit ALU/Accumulator

•

MEN

•

A2/PA2
A3
A4
A5
A6
A7
A8

AlIPA1
AO/PAO
MC/MP
RS
INT
CLKOUT
X1
X2/CLKIN

10% Supply

FD PACKAGE

(TOPVIEWI
I~ 0 ~" N

.' CMOS Technology

::!;~~

The SMJ320 family of 16/32-bit single-chip
digital signal processors combines the flexibility
of a high-speed controller with the numerical
capability of an array processor, thereby offering
an inexpensive alternative to multichip bit-slice
processors. The highly paralieled architecture
and efficient instruction set provide speed and
flexibility to produce a MOS microprocessor
family capable of executing 6.4 MIPS (million
instructions per second). The SMJ320 family
optimizes speed by implementing functions in
hardware that other processors implement
through microcode or software. This hardwareintensive approach provides the design engineer
with processing power previously unavailable on
a single chip.

l!zlln
UN "",t It) CD
_a: g15;:::
««Z«««««

description

6 5 4

CLKOUT 7
X1 8
X2/CLKIN 9
1m)

NC
VSS
08
09
010
011
012

3 2 1 44 43424140
0
39
38
37

10
11
12
13
14
15
16

36
35
34
33
32
31
30

17
.291
1819202122232425262728

A7
A8
MEN
DEN
WE
VCC
A9
A10
All
DO
01

UM'OtIt)I'CDIt)'OtMNU

ZCiCiCiCCCCCCZ

The SMJ320 family consists of two generations of digital signal processors. The first generation contains
the SMJ32010, SMJ320C10, and the SMJ320C15. The SMJ32020 and SMJ320C25 are the secondgeneration processors, designed for higher performance. Many features are common among the SMJ320
processors. Specific features are added in each processor to provide different cost/performance tradeoffs.
Each processor has software and hardware tools to facilitate rapid design.

PRODUCTIO. DATA doo•••1b .lIIIIIi. i.for.lli..
••rnnt H of ,.blicoti•• doto. Protluctl 00Il10111 t.
.....liCllia•• por t.. I11III of Toa 1.1In...1I
motion! Wlmnty. P.....ctian ........i•• d. . .ot
i..... tecti•• of

._ril,

.11 p.n_.

\ TEXAS . "
INSTRUMENTS
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8-47

SMJ320C15. SMJ320C15·25
, DIGITAL SIGNAL PROCESSORS

PIN NOMENCLATURE
NAME
A ll-AO/PA2-PAO

iiiO

ClKOUT
016-00

0
I/O

DEFlNmON
External address bus. I/O port address multiplexed over PA2-PAO.
External polling input

DEN

iNT

MCiMP
MEN
NC

System clock output, % crystal/ClKIN frequency
16-bit parallel data bus
,
Date enable for device input data on 01 5-00
External interrupt input
Memory mode select pin. High selects microcomputer mode. Low selects microprocessor mode.

0
0

Memory enable indicates that 015-00 will accept external memory instruction.
No connection

I
I
I

Resat for initializing the device
+5 V supply

RS
VCC
VSS
WE
Xl
X2/ClKIN

0
0

Ground
Write enable for device output data on 015-00
Crystel output for internal oscillator

Crystal input for internal oscillator or external system clock input

description (continued)
The SMJ320C15 CMOS device is object-code and pin-for-pin compatible with the SMJ32010lC10 and
offers expanded on-chip RAM of 256 words and on-chip program ROM of 4K words, This device allows
the capability of upgrading performance and reducing power, board space, 'and system cost without
hardware redesign. The SMJ320C15 is also available in a 160-ns version, the SMJ320C15-25.

architecture
The SMJ320 family utilizes a modified Harvard architectur4;l for speed and flexibility. In a strict Harvard
architecture, program and data memory lie in two separate spaces, permitting a full overlap of instruction
fetch and execution, The SMJ320 family's modification of the Harvard architecture allows transfers between
program' and data spaces, thereby increasing the flexibility of the device. This modification permits
coefficients stored in program memory to be read into the RAM, eliminating the need for a separate
coefficient ROM. It also makes available immediate instructions and subroutines based on computed values.
32-blt ALU/accumulator
The SMJ320 first-generation devices contain a 32-bit ALU and accumulator for support of double-precision,
two's-complement arithmetic. The ALU is a general-purpose arithmetic unit that operates on 16-bit words
taken from the data RAM or derived from immediate instructions. In addition to the usual arithmetic
instructions, the ALU can perform Boolean operations, providing the bit manipulation ability required of,
a high-speed controller. The accumulator stores the output from the ALU and is often an input to the ALU.
It operates with a 32-bit wordlength. The accumulator is divided into a high-order word (bits 31 through
16) and a low-order word (bits 15 through 0). Instructions are provided for storing the high- and low-order
accumulator words. in memory.
shifters
Two shifters are available for manipulating data. The ALU barrel shifter performs a left-shift of 0 to 16
places on data memory words loaded into the ALU. This shifter extends the high-order bit of the data word
and ,zerO-fills the low-order bits for two's-complement arithmetic. The accumulator parallel shifter performs
a left-shift of 0, 1, or 4 places on the entire accumulator and places the resulting high-order accumulator
bits into data RAM. Both shifters are useful for scaling lind bit extraction.

8-48

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

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SMJ320C15, SMJ320C15·25
DIGITAL SIGNAL PROCESSORS

functional block diagram
XI
CLKOUT

X2/CLKIN

,-----------------------------~

WE
16

DEN
MEN
BIO

INSTRUCTION

MC/MP
INT

PROGRAM
ROM
(4K WORDS)

A"-AO/
PA2-PAO

..........-015-00

ADDRESS
DATA RAM

(258 x 18)
LEGEND:
ACC~

Accumulator

ARP~

Auxiliary register pointer

ARO~

Auxiliary register 0

AR1~

Auxiliary register 1

OP
PC

Data page pointer
Program counter
P register
T register

P
T

DATA

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B-49

SMJ320C15.' SMJ320C15·25
DIGITAL SIGNAL PROCESSOR~

16 x 16-bIt parallel multiplier
The multiplier performs a 16 x 16-bit two's-complement multiplication with a 32-bit result in a single
instruction cycle. The multiplier consists of three units: the T Register, P Register, and multiplier array.
The 16-bit T Register temporarily stores the multiplicand; the P Register stores the 32-bit product. Multiplier
values either come from the data memory or are derived immediately from the MPYK (multiply immediate)
instruction word. The fast on-chip multiplier allows the device to perform fundamental operations such
as convolution, correlation, and filtering.
data and program memory
Since the SMJ320 devices use a Harvard architecturli!, data and program memory reside in two separate
spaces. The first-generation devices have 144 or 256 words of on-chip data RAM and 1. 5K or 4K words
of on-chip program ROM. The SMJ32OC15 is capable of executing up to 4K words of external memory
at full speed for those applications requiring external program memory space. This allows for external RAMbased systems to provide multiple functionality.
microcomputer/microprocessor operating modes
The SMJ320C15 offers two modes of operation defined by the state of the MC/MP pin: the microcomputer
mode (MC/MP = 1) or the microprocessor mode (MC/MP = 0). In the microcomputer mode, on-chip
ROM is mapped into the memory space' with up to 4i< words of internal memory available. In the
microprocessor mode, all 4K words of memory are external.
Interrupts and subroutines
The SMJ320 first-generation devices contain a four-level hardware stack for saving the contents of the
program counter during interrupts and subroutine calls. Instructions are available for saving the device's
complete context. PUSH and POP instructions permit a level of nesting restricted only by the amount of
available RAM. The interrupts used in these devices are'maskable.
Input/output
The 16-bit parallel data bus can be utilized to perform I/O functions in two cycles. The I/O ports are addressed
by the three LSBs on the address lines. In addition, a polling input for bit test and jump operations (BIO)
and an interrupt pin (lNT) have been incorporated for multitasking.

8-50

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SMJ320C15, SMJ320C15·25
DIGITAL SIGNAL PROCESSORS
instruction set
A comprehensive instruction set supports both numeric-intensive operations. such as signal processing.
and general-purpose operetions. such as high-speed control. All of the first-generation devices are objectcode compatible and use the same 60 instructions. The instruction set consists primarily of single-cycle
single-word instructions. permitting execution rates of more than six million instructions per second. Only
infrequently used branch and I/O instructions are multicycle. Instructions that shift data as part of an
arithmetic operation execute in a single cycle and are useful for scaling data in parallel with other operations.
Three main addressing modes are available with the instruction set: direct. indirect. and immediate
addressing.
direct addressing
In direct addressing. seven bits of the instruction word concatenated with the 1-bit data page pOinter form
the data memory address. This implements a paging scheme in which the first page contains 128 words.
and the second page contains up to 128 words.
Indirect addressing
Indirect addressing forms the data memory address from the least-significant eight bits of one of the two
auxiliary registers. ARO and AR1. The Auxiliary Register Pointer (ARP) selects the current auxiliary register.
The auxiliary registers can be automatically incremented or decremented and the ARP changed in parallel
with the execution of any indirect instruction to permit single-cycle manipulation of data tables. Indirect
addressing can be used with all instructions requiring data operands. except for the immediate operand
instructions.
Imrnadlata addressing
Immediate instructions derive data from part ofthe instruction WOld rather than from the data RAM. Some
useful immediate instructipns are multiply immediate (MPYK). load accumulator immediate (LACK). and
load auxiliary register immediate (LARK).
Instruction 88t summary
Table 1 lists the symbols and abbrevi/iltions used in Table 2. the instruction set summary. Table 2 contains
a short description and the opcode for each SMJ320 first-generation instruction. The summary is arranged
according to function and alphabetized within each functional group.
TABLE 1. INSTRUCTION SYMBOLS
SYMBOL
ACC
D
I
K
PA
R

S
X

MEANING
Accumulator
Data memory address field
Addressing mode bit
Immadiate operand field
. ,3-blt port address field
l-bit operand field specifying auxiliary regiater
4-bit left-shift code
3-blt accumulator left-shift field

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8-51

SMJ320C15, SMJ320C15·25
DIGITAL SIGNAL PROCESSORS

TABLE 2. SMJ320 FIRST-GENERATION INSTRUCTION SET SUMMARY
ACCUMULATOR INSTRUCTIONS
MNEMONIC

OESCRIPTION

NO.
CYCLES

NO.
WORDS
1

ABS

Absolute value of accumulator

ADD
ADOH
ADDS

Add to accumulator with shift

Add to high-order accumulator bits
Add to accumulator with no sign

1
1

OPCOOE
INSTRUCTION REGISTER
1~1413121110 9 8 7 6 5 4 3 2 1 0
0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0
0 0 0 0 +-S. I +--D--+
0 1 1 0 0 0 0 0 I +--0--+
0 1 1 0 0 0 0 1 I +--0--+

extension

AND

AND with accumulator

LAC
LACK

Load accumulator with shift

OR
SACH

OR with accumulator

Load accumulator immediate
Store high-order accumulator bits with

1
1
1

1
1

0
0
0
0
0

1 1 1 1 0 0 1
0 1 0 4-S+
1 1 1 1 1 1 0
1 1 1 1 0 1 0
1 0 1 1 +X.

0
0
0
0
0

1 0 1
0 0 1
1 1 0
1 1 0
1 1 0

+--0--+

I
'

+--0----+
K--+

I
I

+--0--+
+--0--+

I
+--S. I
0 1 0 0 I
0 0 1 0 I
0 0 1 1 I

+--0--+
...-L-O--+

shift
SACL

Store low-order accumulator bits

SUB
SUBC

Subtract from accumulator with shift

Conditional subtract Ifor dividel

Subtract from high-order accumulator bits

1
1

extension
Exclusive OR with accumulator

Zero accumulator

Zero accumulator and load high-order bits

Zero accumulator and load low-order bits

1
1

SUBH
SUBS

Subtract from accumulator with no sign

XOR
ZAC
ZALH
ZALS

0
0
0
0

0 0 0 0

0 0 0

1 1

1 1 1
1 1
1 1 0 0
1 1 0 0

1 1

1 0 1 I
1 1 0 I

+--0--+
+--0--+
+--0-----+
+--0--+
0 0 1 0 0 1

+--.O~
+--0--+

with no sign extension
AUXILIARY REGISTER AND DATA PAGE POINTER INSTRUCTIONS
MNEMONIC

DESCRIPTION

WORDS

LAR
LARK
LARP

Load auxiliary register

Load auxiliary register immediate

Load auxiliary register pOinter immediate

LOP
LOPK

Load data memory page pointer

Load data memory page pointer immediate

MAR

Modify auxiliary register and pointer

SAR

Store a'uxiliary register

B-52

OPCOOE
INSTRUCTION REGISTER

NO.

NO.
CYCLES

TEXAS

1514131211109 8 7 8 5 4 3 2 1 0
0 0 1 1 1 0 0 R I +--0--+
0 1 1 1 0 0 0 R
K--+
0 ,1 1 0 1 0 0 0 1
0 0 0 0 0 K

.. o

0
0
0
0

1 1 1
1 1 0
1 1 0 1 0 0 0
0 1 1 0 0 0 R
1 1 0
1 1 0

..If

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+--0--+
+-0--+

+--0--+
0 0 0 0 0 K

SMJ320C15. SMJ320C15·25
DIGITAL SIGNAL PROCESSORS

TABLE 2. SMJ320 FIRST·GENERATION INSTRUCTION SET SUMMARY (CONTINUED)
BRANCH INSTRUCTIONS
DESCRIPTION

MNEMONIC

NO.

CYCLES

WORDS

Branch unconditionally

BANZ

Branch on auxiliary register not zero

BGEZ

Branch if accumulator 2: 0

OPCODE
INSTRUCTION REGISTER

1514131211109 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 0 0 o 0 0 0 0 0
0 0 0 0 ~ BRANCH ADDRESS ---+
1 1 1 1 0 1 0 0 0 0 o 0 0 0 0 0
0 0 0 0 ~ BRANCH ADDRESS ---+

1 0 1 0 0 o 0 0 0 0 0
+-- BRANCH ADDRESS ---+
1 1 0 0 0 0 o 0 0 0 0 0

0 0 0
BGZ

Branch if accumulator

iiiO

BIOZ

Branch on

BlEZ

Branch if accumulator

> 0

= 0

0
1 1

0 0 0 0 ~ BRANCH ADDRESS - - - +
1 1 1 1 0 1 1 0 0 0 o 0 0 0 0 0
0 0 0 0 ~ BRANCH ADDRESS ---+

BlZ

Branch if accumulator < 0

0 0 0
1 1 1 1

BNZ

Branch if accumulator -:/! 0

0 0 0 0
1 1 1 1

1 1 0 0 o 0 0 0 0 0
+-- BRANCH ADDRESS - - - +
1 0 1 0 0 0 o 0 0 0 0 0
+-- BRANCH ADDRESS---+
1 1 1 0 0 0 o 0 0 0 0 0

0 0 0 0

Branch on overflow

1 0

Branch if accumulator = 0

1 0

BRANCH ADDRESS ~

1 0 0

0 0 0

0 0 0 0

+-- BRANCH ADDRESS---+

0 0 0 0
0 1 1 1
1 1 1 1

CAlA
CALL

Call subroutine immediately

2
2

RET

Return from subroutine or interrupt routine

Call subroutine from accumulator

1 0

1 0 0 0 0 0

0 0 0

1 0 0

0 0

+-- BRANCH ADDRESS ---+

o
o

0 0

1 0 0
0 0 0

BRANCH ADDRESS---+

1 0

T REGISTER. P REGISTER. AND MULTIPL Y INSTRUCTIONS
MNEMONIC

DESCRIPTION

NO.

CYCLES

WORDS

8 7 6 5 4 3 2 1 0
1

1 0

1
1

1514131211109
0 1 1 1 1 1 1
0 1 1 0 1 0 1
0 1 1 0 1 1 0

0
0

+---0--+

+---D~

1 0

+---0--+

1 0

+---0--+

1 0 0

APAC

Add P register to accumulator

IT
lTA

Load T register

1
1

LT A combines LT and APAC into one

OPCODE
INSTRUCTION REGISTER

instruction

lTD

lTD combines LT. APAC. and DMDV into
one instruction

MPY

Multiply with T register. store product in

P register
MPYK

Multiply T register with immediate

•

operand; store product in P register

PAC

Load accumulator from P register

1 0 0 0

SPAC

Subtract P register from accumulator

1 0 0

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1 0

1 0 0 0 0

8·53

SMJ3Z0C15, SMJ320C15·25
DIGITAL SIGNAL PROCESSORS

TABLE 2. SMJ320 FIRST-GENERATION INSTRUCTION SET SUMMARY (CONCLUDED)
CONTROL INSTRUCTIONS
MNEMONIC

DESCRIPTION

NO.

CYCLES

WORDS
1

DINT

Disable interrupt

EINT

Enable i~terrupt

lST

Load status register

NOP

No operation

POP

POP stack to accumulator

PUSH

PUSH stack from accumulator

ROVM

Reset overflow mode

SOVM

Set overflow mode

SST

Store status register

OPCODE
INSTRUCTION REGISTER

1514131211109
0 1 1 1 1 1 ,1
0 1 1 1 1 1 1
0 1 1 1 1 0 1
0 1 1 1 1 1 1
0 1 1 1 1 1 1
0 1 1 1 1 1 1
0 1 1 1 1 1 1
0 1 1 1 1 1 1
0 1 1 1 1 1 0

8 7 6 5 4 3 2 1 0
1 1 0 0 0 0 0 0 1
1 1 0 0 0 0 0 1 0
.1 I + - - 0 - - - +
1 1 0 0 0 0 0 0 0
1 1 0 0 1 1 1 0 1
1 1 0 0 1 1 1 0 0
'1 1 0 0 0 1 0 1 0
1 1 0 0 0 1 0 1 1
0 I +--O~

1/0 AND DATA MEMORY OPERATIONS

MNEMONIC

DESCRIPTION

NO.

CYCLES

WORDS

OMOV

Copy contents of data memory location

Input data from port

OUT
TBlR

Output data to port

Table read from program memory to data

OPCODE
INSTRUCTION REGISTER

15141312111098 7 6 5 4 3 2 1 0
0 1 1 0 1 0 0 1 I 4--0--+

into next higher location

0
0
0

4PA.

4--0--+

1 0 0
1 1 0

4PA.

I
I

4--0--+
+--0---+

1 0

+--0---+

1 0

0 0

RAM
TBlW

Table write from data RAM to program
memory

development support products
Together, Texas Instruments and its authorized third-party suppliers offer an extensive line of development
support products to assist the user in all aspects of TMS320 first-generation-based design and development.
These products range from development and application software to complete hardware development and
evaluation systems. Table 4 lists the development support products for the first-generation TMS320 devices.
System development may begin with the use of the simulator, evaluation module (EVM), or emulator (XDS),
along with an assembler/linker. These tools give the TMS320 user various means of evaluation, from
software simulation of the first-generation TMS320s (simulator) to full-speed in-circuit emulation with
hardware and software break point tracing and timing capabilities (XDS).
Software and hardware Jan be developed simultaneously by using the macro assembler/linker or simulator
for software development, the XDS for hardware development, and the evaluation module for both software
development and limited hardware development.
Many thi~d-party vendors offer additional development support for the first~generation TMS320s, including
assembler/linkers, simulators, high-level languages, applications software, algorithm development tools,
application boards, software development boards, and in-circuit emulators. Refer to the TMS320 Family
Development Support Reference Guide (SPRU011 A) for further information about TMS320 development
support products offered by both Texas Instruments and its third-party suppliers.

8-54

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SMJ320C16. SMJ320C16·26
DIGITAL SIGNAL PROCESSORS

Additional support for the TMS320 products consists of an extensive library of product and applications
documentation. Threa-c:lay DSP design workshops are offered by the TI Ragional Technology Centers (RTCsl.
These workshops provide insight into the architecture and the instruction set of the first-generation
TMS320s as well as hands-on training with the TMS320 development tools. When technical questions
arise in regard to a TMS320 membar, contact Texas Instruments TMS320 Hotline at (7131274-2320.
Or, keep informed on the latest TI and third-party devalopment support tools by accessing the libraries
of application source code via the DSP Bulletin Board Service (BBSI at (7131 274-2323. The BBS provides
access for the 2400-/1200-/3OO-bps modems.

documentation support
Extensive documentation supports the first-generation TMS320 devices from product announcement
through applications development. The types of documentation include data sheets with design
specifications, complete user's guides, and 750 pages of application reports published in the book Digital
Signal Processing Applications with the TMS320 Family.
A series of qsP textbooks is being published to support digital signal processing research and education.
The first book, DFT/FFT and Convolution Algorithms, is now available. The TMS320 newsletter, Details
on Signal Processing, is published quarterly and distributed to update TMS320 customers on product
information. The TMS320 DSP bulletin board service provides access to large amounts of information
pertaining to the TMS320 family.
Refer to the TMS320 Family Development Support Reference Guide for further information about TMS320
documentation. To receive copies of first-generation SMJ320 literature, call the Customer Response Center
at 1-800-232-3200.

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SMJ320C15, SMJ320C15·25
DIGITAL SIGIAL PROCESSORS

TABLE 3. TMS320 FIRST-GENERATION SOFTWARE AND HARDWARE SUPPORT
SOFTWARE TOOlS
Macro Assembler/Unker
PC/MS-DOS
VAXNMS
VAX ULTRIX
SUN-3 UNIX

PART NUMBER
TMDS3242850-02
TMDS3242250-08
TMDS3242280-08
TMDS3242550-08

Simulator
PC/MS-DOS
VAXNMS

TMDS3240811-02
TMDS3240211-08

Digital Filter Design Package (DFDP)
IBM PC PC-DOS

DFDP/IBMOO2

DSP Software Ubrary
PC/MS-DOS
VAXNMS

TMDC3240812-12
TMDC3240212-18

TMS320 Ball 212A Modem Suftwara
PC/MS-DOS

TMDX3240813-12

Da1a Encryption Standard Software
PC/MS-DOS
HARDWARE TOOLS
Evaluation Tools
Evaluation Module (EVM)
Analog Intarface Board 1 (AIBlI
Analog Interface Board 2 (AIB2)
EPROM DSP Staner Kit (TMS320E15)
XDS/22 Emulators
TMS32OC10/C15
1
TMS32OC14
TMS320C17

RTC/EVM320A-03
RTC/EVM32OC-06
RTC/AIB320A-08
RTC/EVM320E-15
TMDS3282211
TMDX3282214
TMDX3282217

XDS/22 Upgrade Kits
TMS32010 - TMS320C10/C15
TMS32OC10/C15 - TMS32OC14

TMDS3282215
TMDX3285010 and
TMDX3285018
TMOX3285014 and
TMDX3285018

TMS320C10/C15 - TMS32OC17
EPROM Programming Adaptor Sockets
to 28-pin (TMS320E15/E17)
44- to 28-pln (TMS320E 15/E 17)
58- to 28-pin (TMS320E14)

RTC/PGM320A-08
RTC/PGM32OC-05
TMDX3270110

Additional Target Connector
44-pin PLCC (TMS320C10)

TMDX3288810

8-56

TMDX3240814-12
PART NUMBER

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SMJ320C15, SMJ320C15·25
DIGITAL SIGNAL PROCESSORS

absolute maximum ratings over specified temperature range (unless otherwise noted) t
Supply voltage range, VCC:!: ........................................... -0.3 V to 7 V
Input voltage range .................................................. -0.3 V to 7 V
Output voltage range ................................................. -0.3 V to 7 V
Continuous power dissipation: SMJ320C15 ..................................... 275 mW
SMJ320C15-25 .................................. 330 mW
Maximum operating case temperature ........................................... 125 DC
Minimum operating free-air temperature ......................................... - 55 DC
Storage temperature range ......................................... - 65 DC to + 150 DC
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only. and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute·maximum-rated conditions for extended periods may affect
device reliability.
*A" voltage velues are with respect to VSS.

recommended operating conditions
MIN NOM MAX
4.5
5
5.5

VCC Supply voltage
VSS Supply voltage

VIH

High-level input voltage

Vil

low-level input voltage

IOH
IOL
TA
TC

A" inputs except CLKIN
ClKIN

2
3

V
V
V

A" inputs except MC/gp

0.8

MC/gp
High·level output current (a" outputs)
low-level output current (a" outputs)
Operating free·air temperature
Operating case temperature

UNIT

0.6
-300

('A
mA

125

°C
°C

MAX

UNIT

-55

electrical characteristics over specified temperature range (unless otherwise noted)
PARAMETER

'VOL Low·level output voltage
IOZ

Off·atate output current

Input current

ICC' Supply current
Ci

I
I

= 20 ('A (see Note 1)
IOl = MAX
Ycc =>, MAX 1 Vo = 2.4 V
IOH

Data bus

VCC-OAV#
0.3

Vo - 0.4 V

VI = VSS. VCC = MAX
VCC = 5.5 V. f - 20.5 MHz
VCC = 5.5 V. f - 25.6 MHz

V
0.5
20
-20

V
('A

±50

('A

56
65

26#

Data bus
A" others

Output capecitance

2.4

IOH - MAX

SMJ32OC15
SMJ320C15-25

Input capacitance

MIN TYPi

TEST CONDITIONS

VOH High·level output voltage

= 1 MHz. A" other pins 0

15#

25#
10#

A"others

iA" typical values except for ICC are at Vee = 5 V. TA = 25°C.
, ICC characteristics are inversely proportional to temperature; i.e .. ICC decreases approximately linearly with temperature.
'value derived from characterization data and is guaranteed to limit but not tested.
NOTE 1: This voltage speci.fication is included for interface to HC logic. However, note that a" other timing parameters defined in this
data sheet are specified for TTL logiC levels and will differ for HC logic levels.

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SMJ320C15. S.MJ320C15·25
DIGITAL SIGNAL PROCESSORS

CLOCK CHARACTERISTICS AND TIMING
The SMJ320C15 can use either its internal oscillator or an external frequency source for a clock.
Internal clock optlo.,
The internal oscillator is enabled by connecting a crystal across X 1 and X2/ClKIN (see Figure 11. The frequency
of ClKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and
parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and be specified
at a load capacitance of 20 pF.
PARAMETER

Crystal frequency, fx

TEST CONDmONS

I SMJ320C15
I SMJ320C1S·25

- 55·C to 125·C with B MHz crystal

Cl C2

MIN NOM

MAX

6.7 t

20.St

6.7 t

25.6 t
10

UNIT

MHz
pF

tValue derived from charactarization data and is guaranteed to limit but not tasted.

Xl
CRYSTAL

"'----101----'

FIGURE 1. INTERNAL CLOCK OPTION

external· clock option
An external frequency source can be used by injecting the frequency directly into X2/ClKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the timinp
requirements table.

8-58

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SMJ320C15, SMJ320C16·26
DIGITAL SIGNAL PROCESSORS

swhchlng characteristics over recommended operating condhlons

tc(C) *
trlC)
tf(C)
tw(CL)
tw(CH)

CLKOUT cycle time
CLKOUT rise time
CLKOUT faU time
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high

195.12
RL
CL

SMJ320Cl &-26
MIN NOM MAX

SMJ3ZOC1&
MIN NOM MAX

TEST
CONDmONS

PARAMETER

200
10
8
92
90

= 8250,
= 100 pF

~(MCC)t De)ay time CLKINt to CLKOUn

600

156.25

160
10
8
72
70

600

ns
na
ns
na
ns

UNIT

tValue derived from characterization date and ia guarantaad to limit but not taated.
*tc(C) is the cycle time of CLKOUT i.e., 4tc(MC) (4 times CLKIN cycle time if an external osclUator is used).

timing requlrell\ents over recommended operating condhions

tcIMC)
trlMCI
tf(MC)

SMJ320C1&-2&
MIN NOM MAX
40
150
39.06
5
5

SMJ32OC15
MIN NOM MAX
150
48.78
50
5
6

Master clock cycle time
Rise time maater clock input
FaU time master clock Input

twIMCP) t Pulse duration, master clock.
tw(MCL) Pulse duration, master clock low
tw(MCH) Pulse duratlon, maater clock high

0.4tc1MCI

0.6tcIMC)

0.45tcIMC)

20
20

0.55tc1MCI
15
15

UNIT
ns
na

ns
ns
ns
na

tValue derived from characterization date and is guaranteed to limit but not tested.
NOTE 2: CLKIN rise and faU times must be less than 10 na.

MEMORY AND PERIPHERAL INTERFACE TIMING
switching, characteristics over recommended operating condhlons
SMJ32OC15

PARAMETER
~1

Delay time, CLKOUT ~ to address
bus valid lsee Note 3)

MIN

~2
~3

Delay time, CLKOUn to MENt

Delay tiine, CLKOUn to DEN~

td5

Delay time, CLKOUT ~ to DENt

Delay time, CLKOUT~ to WE!

1d7

Delay time, CLKOUT~ to WEt
Delay tima, CLKOUT~ to data bus OUT valid
Time after CLKOUn that date
bua startll to be driven
Time after CLKOl(n that date
bus atops being driven
Date bus OUT valid after CLKOUn

~9
~10

tsu(A-MD)

0.25tcIC) - 5 §

0.25tcIC) + 15

-lOS

0.26tc(C)- 6 §

0.25tc(C) + 16

-10§

0.5Otc(C) - 6§

Address hold time after
1h(A-WMD) WEt, Maiit, or DENt (see Note 3)
Address bus setup time
Drior to Maii~ or DEN~

MAX

lOS

Delay time, CLKOUT~ to MEN!

TYP

-10§

0.5Otc(C) + 15
15
0.25tc (C) + 65

0.25tc(C)- 6 §

SMJ320Cl&-2&
MIN
TVP
MAX
lOS

UNIT

ns
na

0.25tc(C)- 5 S 0.25tc (C) + 12
-10§
12

0.25tcIC) - 6 §

-10§
O.5Otc(C) - 5 §
-10§

0.25tc(C) + 12
12
O. 5Otc (C) + 12
12
0.26tc(C) + 52

ns
ns
ns
na

0.26tc(C)- 5 §
0. 26tc(C)+40§

0.25tc(C) +40§

0.25tc(C) -1 0

0.25tc;lC)-10

O§

0.25tc(C)-46

0.25tc(C) - 35

§Value derived from characterization data and is guaranteed to limit but not teated.
NOTE 3: Address bus will be valid upon ~t,lmiIt or IiimiIt.

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8-59

SMJ320C15, SMJ320C15·25
DIGITAL SIGNAL PROCESSORS

timing requirements over recommended operating conditions

,
taulD)
th(D)
NOTE 4:

TEST CONDITIONS
RL = 8250,
CL = 100 pF,
See Figure 2

Setup time date bus valid prior to CLKOUT!
Hold time data bus held valid after CLKOUT!
(see Note 4)

MIN NOM
50

MAX

UNIT
ns
ns

Data may be removed from the data bus upon MENt or DEiiit preceding CLKOUT!.

RESET (RS) TIMING

switching characteristics over recommended operating conditions
TEST
CONDITIONS
RL = 8250,
CL = 100 pF,
See Figure 5

PARAMETER

Delay time Dmt, WEt, and ~t from ~

~is(R)

Date bus disable time after ~

MIN

MAX

TVP

UNIT

%te(C)+50 t

14 te(e) + 50 t

tValue derived from characterization data and is guaranteed to limit but not tested.

timing requirements over recommended operating conditions
MIN
tsu(R)

Reset (1m) setup time prior to CLKOUT (see Note 5)

twIRl

~ pulse duration

NOTE 5:

SMJ320Cl&
NOM
MAX

50
6te(C)

SMJ320Cl&-26
MIN
NOM
MAX

5te1C)

UNIT
ns

~ can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.

INTERRUPT (INT) TIMING

timing requirements over recommended operating conditions
MIN
tf(lNT)

Fall time iNi' (sae Note 6)

twllNT)

Pulse duration iNT

SMJ320C15-2&
NOM
MAX
MIN

tsuUNTl Satup time iNT! before CLKOUT!
NOTE 6:

SMJ32OC1&
NOM
MAX

UNIT
ns

te(C)

telC)

iiii'f fall time must be less than 15 ns.
BIOTIMING

timing requirements over recommended operating conditions
MIN
tf(lOi

Fall time ~ (see Nota 7)

SMJ320C15-2&
MIN
NOM
MAX

twllO) Pulse duration ~

tc;tC)
50

tau(lO) Setup time ~! before CLKOUn
NOTE 7:

SMJ320Cl&
NOM
MAX

iiO fall time must be less than 15 ns.

TEXAS .."

8-60

INSTRUMENTS
POST

OF~ICE

BOX 1443 •

HOUSTON. TEXAS 77001

UNIT
ns

te(C)

SMJ320C15, SMJ320C15·25
DIGITAL SIGNAL PROCESSORS

PARAMETER MEASUREMENT INFORMATION

2.16V

FROM OUTPUT
UNDER TEST

L_8260
TEST
POINT

ct.

= 100 pF

-=FIGURE 2. TEST LOAD CIRCUIT

=-==== -==- .:---

1.B8V'"
2.0V ...

0.92 V...

VIH(MINI

0.80 V ... ~==~:':::=:"::===~=VIL (MAXI

(aIINPUT

wd-- :;L--I--2.0V'"

O.BV
0.5 V'"

----

---

'OH(MINI
VOL (MAXI

(bl OUTPUTS I

FIGURE 3. VOLTAGE REFERENCE LEVELS

TEXAS

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

8·61

SMJ320C15, SMJ320C15·25
DIGITAL SIGIAl PROCESSORS

TIMING DIAGRAMS
This section contains all the timing diagrams for the SMJ320 first-generation devices. Refer to the top corner for
the specific device.
Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless
otherwise noted.

clock timing
~ ,.. ',IMCI

X2/CLKIN

~ 'wIMCHI

I ~ telMCI
I
)I
I
•

----t

, . . . -......1-1 'wIMCPI I
I

_I ~

l'fIMCI_ ~

'wIMCLI

..........,.. 'dIMCCI'

'wICHI

-----til'!

--:X~--------~-------JI:~----------------~~
....! !.....! rtiI
11oiI1.f-----'fiCI

·,ICI

.WICLI------tl.!

ttd(MCCI and tw(MCPI are referenced to an intermediate level of 1.5 volts on the ClKIN waveform.

memory read timing

ClKOUT

'd3

---I- !.-

-.,...-~II

/
'd2

---!
I

---!i
r--- td1.~

telCI

I~I '----r-- 'hiA-WMDI

tsuiA-MOI

\~_

A"-AO

----------~~;--------A-D-DR-E-SS-.-U~S-V-AU-D------------~~~_________

015-00

__________)

t'---tSUIDI

8·62

{

TEXAS

~ 'hID)

INSTRUCTION IN VALID

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TeXAS 77001

)>--------------

SMJ320C15, SMJ320C15·25
DIGITAL SIGNAL PROCESSORS

TBLR Instruction timing

I-'d'~
Al'-AO

D'S-DO

)@(

==>@(

GO)

)@(
;;;:j ~'hCDI

"'suCDI
{

)@C

GO)

LEGEND:
1.
2.
3.
4.
5.
6.

TBLR INSTRUCTION PREFETCH
DUMMY PREFETCH
DATA FETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
ADDRESS BUS VALID

7.
B.
9.
10.
11.
12.

ADDRESS BUS VALID
ADDRESS BUS VALID
INSTRUCTION VALID
INSTRUCTION VALID
DATA INPUT VALID
INSTRUCTION VALID

7.
B.
9.
10.
11.

ADDRESS BUS VALID
INSTRUCTION VALID
INSTRUCTION VALID
DATA OUTPUT VALID
INSTRUCTION VALID

TBLW Instruction timing
J

LEGEND:
1.
2.
3.
4.
6.
6.

'TBLW INSTRUCTION PREFETCH
DUMMY PREFETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
ADDRESS BUS VALID
ADDRESS BUS VALID

TEXAS

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

8-63

SMJ320C15, SMJ320C15·25
DIGITAL SIGNAL PROCESSORS

IN instruction timing
CLKOUT

\'--._-J
/

\F------J!

\F---J!
I

A1'·AO

I ......., 14~~~..L.,I~I

------------~~1

taufDI

4B<'---_~*==
14-

I "'5-.J

I V-----------------

I --.I ~hlOI
=:>~-~G=>~-~{~_)~~G=>>----

LEGEND:
1.
2.
3.
4.

IN INSTRUCTION PREFETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
PERIPHERAL ADDRESS VALID

5.
6.
7.
8.

ADDRESS BUS VALID
INSTRUCTION VALID
DATA INPUT VALID
INSTRUCTION VALID

OUT instruction timing
CLKOUT

\_----J!

\'--._-J
/

LEGEND:
1.
2.
3.
4.

OUT INSTRUCTION PREFETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
PERIPHERAL ADDRESS VALID

8·64

',.IA·MDI

1+O-'d4

015·00

5.
6.
7.
8.

ADDRESS BUS VALID
INSTRUCTION VALID
DATA OUTPUT VALID
INSTRUCTION VALID

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

SMJ320C15, I SMJ320C15·25
DIGITAL SIGNAL PROCESSORS

reset timing

CLKOUT~
KtsulRI

\1......------',S/
I~

-I

'wlRI

1 ~c~J------------------

_______________

WE NonE\.....Yi
MEN
--t .....dll
'dlsIRI--tJol-

DATA SHOWN

-J'ii'AiA\

RELATIVE TO WE

D15'DO~

ADDRESS
BUS

= ADDRESS

BUS;-_ _ ___

AB = PC

AI = PC + 1

>C?(~

________

A_B_=__
PC__
=_O_________

NOTES: A. RS forces DEN. WE. and MEN high and places data bus DO through 015 in a high-impedance state. AB outputs land program
counter) are synchronously cleared to zero after the next complete ClK cycle from ~I.
B. RS must be maintained for a minimum of five clock cycles.
C. Resumption of normal program will commence after one complete ClK cycle from RSt.
D. Due to the synchronizing action on ~. time to execute the function can vary dependent upon when liSt or ~I occur in
the ClK cycle.
E. Diagram shown is for definition purpose only. DEN. WE. and MEN are mutually exclusive.
F. During a write cycle, AS may produce an invalid write address.

interruPt timing

CLKOUT

-.-I

t-------ft'UIINTI

~!:=--

iNT

I
tl

'IIINTI~

twUNTI

810 timing
CLKOUT

I-

iilj

\
~

'IIIDI~

tsuliOI

'wIlO)

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TeXAS 77001

8-65

SMJ320C15. SMJ320C15·25
DIGITAL SIGNAL PROCESSORS

MECHANICAL DATA
4O·pin JD'ceramic dual·in-line package

51,31 12.0201 MAX

~1~~~~~~I:::]~~~~~.~]~:~=~
CD

L
rr

~-~~~NGf~ ~ ~ ~ ~ ~ ~ ~,~ ~ ~ ~ ~ ~ ~ ~J
~ m~1~ ~jE',!.,u ..,y...-.l' ~g:~

16,24±0,254
I0 .800 ±0.0101 ~

0,508 10.0201 MIN

•

1.~4'7010'186IMAX

0,26410,0101 NOMJL,
JlWPlN SPACING 2,5410,1001 T,P,
0,467±0,078
(s. . Note AI
(0.018±0.0031

1,27±0,264
10,060±0.0101

1,27
[+0016]
0.060 ..,0:020

NOTE A: Each pin centerlina is located within 0,254 (0.0101 of its true longitudinal position.
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

8-66

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

SMJ320C15, SMJ320C15·25
DIGITAL SIGIAL PROCESSORS

44-pad FD ceramic chip carrier package

~-------------~:.:I~:=~:------------~

' - - - - - - - - 1 S . 0 4 10.6921 MAX-----------l"1

~ ~

2.
30
31

'8 82 (~':1I1
1'.33
.

33
16.0410.5921
MAX

RfJA = 44,'·CIWATT
RfJC = 13,3·CIWATT

.
3•

INDEX CORNER

3.
40

~1Li-

l
O.•3~~.0261-f===---""

...

---c 0," ~.g2.'

0,38 f . 1&1

I1IIIII

fllllill

IIIUIIHJI
11111111

0,836 X 1,27
(0.025 X 0.0501

TY.
36 PlACES

IIIIII

f---II
i------t-~

3,0& '0.120'

The checkerboard pattern is aligned vertically and is symmetrical horizontally as shown,
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
Taxas Instruments reserves the right to make changes at any time in order to improve design and to supply the best product possible.

TEXAS

INSfRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

8-67

Appendix C

ROM Codes

Size of a printed circuit board must be considered in many DSP applications.
To fully utilize the board space, Texas Instruments offers two options which
will reduce the chip count and provide a single-chip solution to its customers.
These options incorporate 4K words of on-chip program from either a mask
programmable ROM or an EPROM. This allows the customer to use a codecustomized processor for a specific application while taking advantage of the
following:
•
•
•
•

Greater memory expansion
Lower system cost
Less hardware and wiring
Smaller PCB

If used otten, the routine or entire algorithm can be programmed into the onchip ROM of a TMS320 DSP. TMS320 programs can also be expanded by
using external memory; this reduces chip count and allows for a more flexible
program memory. Multiple functions are easily implemented by a single device, thus enhancing system capabilities.
TMS320 Development Tools are used to develop, test, refine, and finalize the
algorithms. The microcomputer/microprocessor (MC/MP) mode is available
on all ROM-coded TMS320 DSP devices when accessing either on-chip or
off-chip memory is required. The microprocessor mode is used to develop,
test, and refine a system application. In this mode of operation, the TMS320
acts as a standard microprocessor by using external program memory. When
the algorithm has been finalized, the designer may submit the code to Texas
Instruments for masking into the on-chip program ROM. At that time, the
TMS320 becomes a microcomputer which executes customized programs out
of the on-chip ROM. Should the code need changing or upgrading, the
TMS320 may once again be use in the microprocessor mode. This shortens
the field upgrade time and avoids the possibility of inventory obsolescence.
Figure C-1 illustrates the procedural flow for TMS320 masked parts. When
ordering, there is a one-time/non-refundable charge for mask-tooling. A
minimum production order per year is required for any masked-ROM device.
ROM codes will be deleted from the TI system after one year from the last
delivery.
A digital signal processor with the EPROM option is the solution for lowvolume production orders. The EPROM option allows for form-factor emulation. Field upgrades and changes are possible with the EPROM option.

C-1

Appendix C - ROM Codes

CUSTOMER TMS320C1x DESIGN

CUSTOMER SUBMITS:
TMS320C1x NEW CODE RELEASE FORM
- PRINT EVALUATION AND ACCEPTANCE FORM (PEA F)
- PURCHASE ORDER FOR MASK CHARGE/25 PROTOTYPES
- TMS320C1x CODE

TEXAS INSTRUMENTS RESPONDS:
- CUSTOMER CODE INPUT INTO TI SYSTEM
- CODE SENT BACK TO CUSTOMER FOR VERIFICATION

TI PRODUCES 25 PROTOTYPES

TMS320C1 x PRODUCTION

Figure C-1. TMS320 ROM Code Flowchart

C-2

Appendix C - ROM Codes

A TMS320 ROM code may be submitted in one of the following formats (the
preferred media is 5 1/4" floppies):
FLOPPY:
EPROM (others):
PROM:
MODEM (8BS):

TI Cross-Assembler Format
TMS2764, TMS2508, TMS2516, TMS2532, TMS2564
TBP28S166, TBP28S86
TI Cross-Assembler Format

When a code is submitted to Texas Instruments for masking, the code is reformatted to accommodate the TI mask generation system. System level verification by the customer is therefore necessary. Although the code has been
reformatted, it is important that the changes remain transparent to the user and
do not affect the execution of the algorithm. The formatting changes involve
the removal of address re-Iocation information (the code address begins at the
base address of the ROM in the TMS320 device and progresses without gaps
to the last address of the ROM on the TMS320 device) and the addition of
data in the reserved locations of the ROM for device ROM test. Note that
because these changes have been made, a 'checksum' comparison is not a
valid means of verification.
With each masked device order, the customer must sign a disclaimer stating:
"The units to be shipped against this order were assembled, for
expediency purposes, on a prototype (i.e., non-production qualified)
manufacturing line, the reliability of which is not fully characterized.
Therefore, the anticipated inherent reliability of these prototype units
cannot be expressly defined."
and a release stating:
"Any masked ROM device may be resymbolized as TI standard product and resold as though it were an unprogrammed version of the
device at the convenience of Texas Instruments."
Contact the nearest TI Field Sales Office for more information on procedures,
leadtimes, and cost.

C-3

Appendix C - ROM Codes

C-4

Appendix 0

Quality and Reliability

The quality and reliability performance of Texas Instruments Microprocessor
and Microcontroller Products, which includes the three generations of
TMS320 digital signal processors, relies on feedback from:
•

Our customers

•

Our total manufacturing operation from front-end wafer fabrication trfinal shipping inspection

•

Product quality and reliability monitoring.

lJur customer's perception of quality must be the governing criterion for
judging performance. This concept is the basis for Texas Instruments Corporate Quality Policy, which is as follows:
"For every product or service we offer, we shall define the requirements that solve the customer's problems, and we shall conform to
those requirements without exception."
Texas Instruments offers a leadership reliability qualification system, based on
years of experience with leading-edge memory technology as well as years of
research into customer requirements. Quality and reliability programs at TI are
therefore based on customer input and internal information to achieve constant imorovement in quality and reliability.
TI Quallticatlon test updates are available upon request at no charge. TI will
consider performing any additional reliability test(s), if requested. For more
information on TI quality and reliability programs, contact the nearest TI Field
Sales Office.

Note:
Texas Instruments reserves the right to make changes in MaS Semiconductor test limits, procedures, or processing without notice. Unless prior
arrangements for notification have been made, TI advises all customers to
reverify current test and manufacturing conditions prior to relying on
published data.

0-1

Appendix 0 - Quality and Reliability

0.1

Reliability Stress Tests
Accelerated stress tests are performed on new semiconductor products and
process changes to ensure product reliability excellence. The typical test environments used to qualify new products or major changes in processing are:
•
•
•
•
•
•
•
•
•

High-tempera~ure operating life
Storage life
Temperature cycling
Biased humidity
Autoclave
Electrostatic discharge
Package integrity
Electromigration
Channel-hot electrons (performed on geometries 'less than 2.0 IJm).

Typical events 'or changes that require internal requalification of product incl\Jde:
•
•
•
•
•

New die design, shrink, or layout
Wafer process (baseline/control ,systems. flow. mask. chemicals. gases.
dopants. passivation. or metal systems)
Packaging assembly (baseline control systems or critical assembly
equipment)
Piece parts (such as lead frame. mold compound. mount material. bond
wire. or lead finish)
Manufacturing site.

TI reliability control systems extend beyond qualification. Total reliability
controls and management include. a product reliability monitor and final product release controls. MOS memories. utilizing high-dens~ty active elements.
serve as leading' indicators in wafer-process integrity at TI MOS fabrication
sites. enhancing all MOS logic device yields and reliability. Thousands of
MOS devices per month are randomly tested to ensure product reliability and
excellence.
Table 0-1 lists the microprocessor and microcontroller reliability tests. the
duration of the test. and sample size. The following defines and describes
those tests in the table.

AOQ (Average Outgoing Quality) Amount of defective product in a population. usually expressed in terms of
parts per million (PPM).
FIT (Failure In Time)

0-2

Estimated field failure lrate in number
of failures per billion power-on device
hours; 1000 FITS equals 0.1 percent
fail per 1000 device hours.

Appendix D - Quality and Reliability

\ Operating lifetest

Device dynamically exercised at a high
ambient temperature (usually 125·C)
to simulate field usage that would expose the device to a much lower ambient temperature (such as 55·C).
Using a derived high temperature, a
55·C ambient failure rate can be calculated.

High-temperature storage

Device exposed to 150·C unbiased
condition. Bond integrity is stressed in
this environment.

Biased humidity

Moisture and bias used to accelerate
corrosion-type failures in plastic
packages. Conditions include 85·C
ambient temperature with 85-percent
relative humidity (RH). Typical bias
voltage is +5 V and ground on alternating pins.

Autoclave (pressure cooker)

Plastic-packaged devices exposed to
moisture at 121·C using a pressure of
one atmosphere above normal pressure. The pressure forces moisture
permeation of the package and accelerates corrosion mechanisms· (if present) on the device. External package
contaminates can also be activated
and caused to generate inter-pin current leakage paths.

Temperature cycle

Device exposed to severe temperature
extremes in an alternating fashion
(-65·C for 15 minutes and 150·C for
15 minutes per cycle) for at least 1000
cycles. Package strength, bond quality, and consistency of assembly process are stressed in this environment.

Thermal shock

Test similar to the temperature cycle
test, but involving a liquid-to-liquid
transfer, per MIL-STD-883C, Method
1011.

PIND

Particle Impact Noise Detection test.
A non-destructive test to detect loose
particles inside a device cavity.

0-3

Appendix 0 - Quality and Reliab,ility·

Mechanical Sequence:
Fine and gross leak
Mechanical shock
PIND (optional)
Vibration, variable frequency
Constant acceleration
Fine and gross leak
Electrical test

Thermal Sequence:
Fine and gross leak
Solder heat (optional)
Temperature cycle
(10 cycles minimum)
Thermal shock
(10 cycles minimum)
Moisture resistance
Fine and gross leak
Electrical test
Thermal/Mechanical Sequence:
Fine and gross leak
Temperature cycle
(10 cycles minimum)
Constant acceleration
Fine and gross leak
Electrical test
Electrostatic discharge
Solderability
Solder heat
Salt atmosphere
Lead pull
Lead intAoritv
Electromigration

Resistance to solvents

0-4

Per MIL-STD-883C, Method 1014.5
Per MIL-STD-883C, Method 2002.3,
1500 g, 0.5 ms, Condition 8
Per MIL-STD-883C, Method 2020.4
Per MIL-STD-883C, Method 2007.1,
20 g, Condition A
Per MIL-STD-883C, Method 2001.2,
20 kg, Condition D, Y1 Plane min
Per MIL-STD-883C, Method 1014.5
To data sheet limits

Per M I L- STD-883C, Method
Per MIL-STD-750C, Method
Per MiL-STD-883C, Method
-65 to +150·C, Condition C
Per MIL-STD-883C, Method
-55 to +125·C, Condition 8
Per MIL-STD-883C, Method
Per MIL-STD-883C, Method
To data sheet limits

1014.5
1014.5
1010.5,

Per MIL-STD-883C, Method
Per MIL-STD-883C, Method
-65 to +150·C, Condition C
Per MIL-STD-883C, Method
30 kg, Y1 Plane
Per MIL-STD-883C, Method
To data sheet limits

1014.5
1010.5,

1011.4,
1004.4
1014.5

2001.2,
1014.5

Per MIL-STD-883C, Method 3015
Per MIL-STD-883C, Method 2003.3
Per MIL-STD-750C, Method 2031,
10 sec
Per MIL-STD-883C, Method 1009.4,
Condition A, 24 hrs min
Per MIL-STD-883C, Method 2004.4,
Condition A
Per MIL-STD-883C, Method 2004.4,
Condition 81
Accelerated stress testing of conductor patterns to ensure acceptable
lifetime of power-on operation
Per MIL-STD-883C, Method 2015.4

Appendix 0 - Quality and Reliability

Table 0-1. Microprocessor and Microcontroller Tests
TEST

DURATION

Operating life, 125'C, 5.0 V
Operating life, 150'C, 5.0 V
Storage life, 150'C
Biased 85'C/85 percent RH, 5.0 V
Autoclave, 121'C, 1 ATM
Temperature cycle, -65 to 150'C
Temperature cycle; 0 to 125'C
Thermal shock, -65 to 150'C
Electrostatic discharge, ±2 kV
Latch-up (CMOS devices only)
Mechanical sequence
Thermal sequence
Thertnal/mechanical sequence
PINO
Internal water vapor
Solderability
Solder heat
Resistance to solvents
Lead integrity
Lead pull
Lead finish adhesion
Salt atmosphere
Flammability (UL94-VO)
Thermal impedance

1000
1000
1000
1000
240
1000
3000
200

SAMPLE SIZE
PLASTIC CERAMIC

hrs
hrs
hrs
hrs
hrs
cyc
cyc
cyc

129

77'
77

77
77

129

77
129
129
129
12
5
-

129
129
129
12
5
38
38
38
45
3
22
22
15
15
15
15
5

22
22
15
15
22
15
15
3
5

. .

'If junction temperature does not exceed plasticity of package .

Table D-2 provides a list of the TMS320C1 x devices, the approximate number
of transistors, and the equivalent gates. The numbers have been determined
from design verification runs.

Table 0-2. TMS320C1x Transistors
DEVICE
NMOS:
TMS32010 (all speeds)
CMOS:
TMS320C10
TMS320C14
TMS320E14
TMS320C15
TMS320E15
TMS320C17
TMS320E17

(all
(all
(all
(all
(all
(all
(all

speeds)
speeds)
speeds)
speeds)
speeds)
speeds)
speeds)

# TRANSISTORS

# GATES

50K

17K

58K
122K
125K
110K
113K
115K
118K

15K
25K
26K
20K
21 K
22K
23K

0-5

Appendix 0 - Quality and Reliability

0-6

Appendix E

Development Support/Part Order Information

This section provides development support Information, device part numbers,
and support tool ordering information for all TMS320C1 x (first-generation
TMS320) products. Extensive documentation, including application reports,
user's guides, and textbooks, is available to support DSP design, research, and
education. To order TMS320 literature, contact the TI Customer Response
Center (CRC) hotline number via 1-800-232-3200. For more information
about support products and documentation, refer to the TMS320 Family Development Support Reference Guide (literature number SPRU011 A).
The nearest TI Field Sales Office can be contacted for support tool availability
or further details (see list of offices and distributors at end of book). For
technical support, contact the TMS320 DSP hotline via (713) 274-2320.
The major topics discussed in this section are listed below.
•

Development Support (Section E.1 on page E-3)
TMS320C1 x/TMS320C2x Assembly Language Tools
TMS320C1 x Simulator
TMS320C1 x Evaluation Module (EVM)
TMS320C1)( Emulator (XDS/22)
TMS320C1 x XDS/22 Upgrade Kit
TMS320 Third-party Support
TMS320 Analog Interface Board
TMS320E15 EPROM DSP Starter Kit
Digital Filter Design Package (DFDP)
OS P Software Library
TMS320 Bell 212A Modem Software
TMS320 DSP Hotline/Bulletin Board Service

•

Part Order Information (Section E.2 on page E-12)
Device part numbers
Software and hardware support tools part numbers
Device and support tool prefix designators
Device and support tool nomenclature

Appendix E - Development Support/Part Order Information

Macro
SourcE;
FileI'

Figure E-2. TMS320C1x Development Tools

E-2

Appendix E - First-Generation TMS320 Development Support

E.1

First-Generation TMS320 Development Support
Texas Instruments offers extensive development support and complete documentation with the first-generation TMS320 digital signal processors. Tools
are provided to evaluate the performance of the processors, develop algorithm
implementations, and fully integrate the design's software and hardware
modules. Developmental operations are performed with the TMS320C1 x/
TMS320C2x Assembly Language Tools, Simulator, Evaluation Module
(EVM), Emulator (XDS). and other support products.
A description and key features for each TMS320C1 x development support
tool is provided in the following subsections. For more information about
support products, refer to the TMS320 Family Development Support Reference Guide (literature number SPRU011 A). For ordering information, see
Section E.2.

E.1.1 TMS320C1xjTMS320C2x Assembly Language Tools
The TMS320C1 x/TMS320C2x Assembly language Tools generate the program code for the first- and second-generation TMS320 devices. This assembly language package consists of the following:
•
•
•
•

An Assembler which translates assembly language source files into
machine language object code in a common object file format (COFF).
An Archiver which allows the programmer to collect a group of files
into a single file or to produce a "library" of macros.
A Linker which combines the object files into a single module for execution.
A Format Conversion Utility which converts the files into a
TI-tagged, Intel, or Tektronix object format.

Figure E-2 shows the developmental flowchart for the assembly language
tools. The shaded area represents the basic routine for a software development. All devices which lie outside of this shaded portion are optional items.
The TMS320C1 x/TMS320C2x Assembly Lanuguage Tools create and use the
object files which are in the common object file format (COFF). This format
is an improvement over those object codes which were developed by earlier
macro assemblers. The COFF files provide more efficient programming for any
TMS320C1 x/E1 x device since the programmer is allowed to divide and subdivide the program code into sections for modular manipulation/relocation.

Note:
The COFF files which are generated by the assembly language tools are
not compatible with the TI-tagged, Intel, or Tektronix object files. The
code conversion utility will convert COFF files into the standard format
when using most EPROM programmers.
The assembly language tools are currently available for the IBM PC/MS- DOS
and VAXNMS operating systems.

E-3

Appendix E - First-Generation TMS320-0evelopment Support

E.1.2 TMS320C1x Simulator
The TMS320C1 x CPU Simulator is a software program that simulates operation of the TMS320C1 x CPU to aUow program verification. The debug mode
enables the user to monitor the state of the simulated TMS320C1 x while the
program is executing. The simulator uses the object code produced by the
TMS320C1 x Assembly Language Tool. During program execution, the internal
registers and memory of the simulated device are modified as each instruction
is interpreted by the host computer. Once program execution is suspended,
the internal registers and both program and data. memories can be inspected
and/or modified. In addition, files can be associated with the I/O ports.
The following features highlight simulator capability for effective TMS320C1 x
software development:
Program debug/verification
Single-step option
Trace/breakpoint capabilities
Full access to simulated registers and memories
I/O device simulation.

•
•
•
•
•

The simulator is currently available for the VAX/VMS and IBM PC/PC-DOS
operating systems.

Note:
The TMS320C1 x CPU Simulator. only simulates the ODAration of the CPU,
not the peripherals. .
I

E.1.3 TMS320C1x Evaluation Module (EVM)
The TMS320C1 x Evaluation Module (EVM) is a low-cost development board
for TMS3201 O/C1 O/C15/E15 devices, used for full-speed in-circuit emulation
and hardware debugging. (Note that the EVM does not support the
T/VIS320C17 /E17 devices.) It consists of a single board that enables a designer to evaluate certain characteristics of the processor to determine if it
meets the requirements of an application.
The powerful' firmware package of the TMS320C1 x EVM contains a debug
monitor, assembler/reverse assembler, and software communication via three
EIA ports. The EVM can communicate to a host computer and several peripherals. The three EIA ports allow the EVM to communicate with a designer's
terminal, a host computer, a printing device, or audio cassette. In addition, the
EVM also supports an onboard PROM utility for programming TMS2764 EPROMs, used for mass program storage.
The EVM assembles source code created on a host computer or on the EVM's
text editor, a line-numbered editor with character-editing capabilities. The
EVM has a one-pass assembler, which resolves both forward and reverse labels and converts the incoming text into executable code. Object code produced by the EVMassembler is stored in memory. The reverse assembler
E-4

Appendix E - First-Generation TMS320 Development Support

converts object code back to assembly language mnemonics, and the patch
assembler allows modification of the code.
Some key features of the TMS320C1 x EVM are:
•
•
•

On-board TMS3201 0
20-MHz operation
Event counter for one breakpoint

•
•
•
•
•
•
•
•
•
•
•

Text editor
On-board EPROM programmer
Audio cassette interface
4K words of on-board program RAM
Target connector for full-speed in-circuit emulation from EVM memory
Debug monitor including commands with full prompting
Line-by-line assembler/reverse assembler
Transparency mode for host CPU upload/download
Eight instruction breakpoints available
Single-step execution with software tracli
Standalone or host CPU configurable.

The TMS320C1 x EVM functions in two modes: host computer mode or PC
mode (single-user system). In the host computer mode, object and source
code can be uploaded/downloacfed between the host computer and EVM. In
the PC mode, the EVM can support host uploads/downloads over a single
port to allow a single-user system, such as an IBM PC, to function as both a
terminal and a host (see Figure E-3). Commercially available terminal emulation software for the single-user system is required in this configuration.

SINGLE-USER
SYSTEM
(PC)

~ ~
TMS320
EVM

POWER
SUPPLY

TARGET
SYSTEM

Figure E-3. TMS320C1x EVM/Single-User System

E-5

Appendix E - First-Generation TMS320Deveiopment Support

E.1.4 TMS320C1x Emulator (XDS)
The TMS320C1 x Emulator (XDS/22) is a user-friendly system that has all the
features necessary for realtime in-circuit emulation. This allows integration of
hardware and software modules in the debug mode. By setting breakpoints
based on internal conditions or external events, execution of the program can
be suspended and control be given to the debug mode. In the debug mode,
all registers and memory locations can be inspected and modified. Single-step
execution is available. Full-trace capabilities at full speed and a reverse assembler that translates machine code back into assembly instructions also increase debugging productivity. Using a standard RS-232-C port,. the object
file is first produced by the TMS320C1 x Assembly Language Tools, downloaded into the emulator, and finally controlled through a terminal.
The XDS/22 provides 4K x 16 words of high-speed static RAM (zero wait
states) for program memory. It also has the capability of executing out of
target memory to utilize the full TMS320C1 x program/data address range. FOI
multiprocessing configurations, up to nine emulators can be daisy-chained
together.
The XDS/22 emulator is a completely self-contained system with power supply. With three RS-232-C ports, the XDS/22 Emulator can be interfaced to a
terminal, host computer for source or object downloading/uploading capabilities,and printer or PROM programmer.
The TMS320C1 x emulator supports in-circuit emulation on all speed versions
of the TMS3201 O/C1 O/C15. Emulators are also available for supporting incircuit emulations of the TMS320C14 and TMS320C17.
The key features of the TMS320C1 x XDS/22 Emulator are as follows:
•
•
•
•
•
•
•
•
•
•
•

Full-speed in-circuit emulation
4K words of program memory for user code
Hardware breakpoint on program, data, or I/O conditions
2K words of full-speed hardware trace
Use of target system crystal or internal crystal
Up to ten software breakpoints
Single-step option
Assembler/reverse assembler
Host-independent upload/download capabilities to/from program or
data memory
Ability to inspect and modify registers and program/data memory
Multiprocessor system development.

Figure E-4 shows a block diagram of a typical system configuration using the
TMS320C1 x XDS/22 Emulator.

E-6

Appendix E - First-Generation TMS320 Development Support

USER'S
TERMINAL

PROM
PROGRAMMER
OR
LINE
PRINTER

HOST
COMPUTER
SYSTEM

•
I

I
I
I
I
I

XDS
TMS320
WORK
STATION

Figure E-4. TMS320C1x XDS/22 System Configuration

E.1.5 TMS320C1x XDS/22 Upgrade Kit
Texas Instruments offers a TMS320C1 x XDS upgrade kit, which extends the
functions and capabilities of existing development systems at a minimal cost
to the customer. The upgrade kit will enable a TMS3201 0 XDS/22 to emulate
operation of the TMS3201 O/C1 O/C15 devices. Note that early systems support TMS3201 0 and TMS320C1 0 performance. Upgrade kits allow upgrade
only within a generation, not from a first- to a second-generation XDS.

E.1.6 TMS320 Third-party Support
The TMS320 family of digital signal processors is supported and serviced by
many independent vendors and consultants, known as third parties. These
products range from hardware to software, simulator to DPS utility package,
or logic analyzer to emulator. The services range from simple speech-encoding or vector quantization to a more complex software/hardware design or
system analysis.
The TMS320 Family Development Support Reference Guide (literature nUl •. ber SPRU011 A) lists and describes a number of tools and services that augment the support that Texas Instruments provides; see Section 11. These
publications furnish TI customers with additional information on supportive
equipment and accessories.

E-7

Appendix E - First-Generation TMS320 Development Support

E.1.7 TMS320 Analog Interface Board
Two TMS320 Analog Interface Boards (AIB1 and AIB2) are presently available for the first-generation TMS320 family. Both boards are capable of converting analog-to-digital/digital-to-analog signals. Either board can function
as a preliminary target system with the TMS320C1 x EVM, XDS, or another
emulator. Figure E-5 shows the layout of a typical AlB system.
Each AlB board is an excellent educational tool which provides a simple, inexpensive method for learning the digital signal processing (DSP) techniques.
And, either board allows testing of application programs with analog 1/0 by
providing an interface to the TMS320C1 x , EVM or XDS/22. )
Key features of the AIB1 are as follows:
•
•
•
•
•
•
•
•
•

12-bit analog-to-digital converter with sample and hold
12-bit digital-to-analog converter
One 16-bit input port for additional AID or user application
One 16-bit output port for additional D/A or user application
Two low-pass filters
Audio amplifier
TBLW (TABLE WRITE) decoder
Extended 1/0 data memory
Prototyping area for user application

Key features of the AfB2 are as follows:
•
•
•
•
•
•
•

16-bit analog-to-digital converter with sample and hold
16-bit digital-to-analog converter
Supports TLC3204x Analog Interface chips and TCM2918 codec chips
Stand-alone operation (dual 27xxx EPROM sockets and socket-type
oscillator)
Oncboard noise and function generator
Sockets for TMS320C1 O/C15/C17/C25 devices
Socket for applicable second-generation TMS320 members

The sample rate clock for each AlB is derived from an on-board oscillator and
may be programmed to provide an periodic analog input, output, or both.
There are two analog lowpass filters on the board, too. One .filter minimizes
the aliasing effects by limiting the band-width of the AID input. The other
filter smooths the output of the D/A. The frequen~y response of the filters is
controlled by varying the external components in the filter stages. The cutoff
of these filters is set to 4.7 kHz, but may be (plug) programmed. An audio
amplifier that will drive an 8-ohm speaker is provided for applications with
audio output. Sockets for 8K words of expansion memory are also provided.
This memory is addressed through 1/0 and can support, direct or
autoincrementldecrement addressing. Up to 64K words of memory may be
addressed through the memory expansion connector via this 1/0 interface.

E-8

Appendix E - First-Generation TMS320 Development Support

USER'S
TERMINAL

_ _ ANALOG
OUT

POWER
SUPPLY
POWER CABLE

ANALOG
IN

EMULATION CABLE

Figure E-5, TMS320 AlB System Configuration

E.1.8 TMS320E15 EPROM DSP Starter Kit
To assist with developing, debugging, and testing programs, Texas Instruments offers the TMS320E15 EPROM DSP Starter Kit. The kit includes th~
following:
•
•

•

TMS320C1 x Evaluation Module (EVM) to provide a standalone development system for the TMS3201 O/C1 O/C15/E15,
Two TMS320E15JDL devices (TMS320EPROM/15 - EPROM DSP
Twin-Pack), each of which provides an on-chip 256-word RAM and
4K-word program EPROM for realtime code development and modification.
The device is object-code and pin compatible with the
TMS3201 O/C1 0 and features EPROM code protection for copyright security.
40-pin to 28-pin conversion EPROM programmer adaptor socket
(RTC/PGM320A-06) to facilitate the TMS320E15 with programming
when using an EVM or a standard PROM programmer which is capable
of programming the 28-pin 64K CMOS EPROMs.
Documentation.

Contact the nearest TI Field Sales Office or distributor for availability or further
information regarding the TMS320E15 EPROM DSP Starter Kit (part number
RTC/EVM320E-15).

E.1.9 Digital Filter Design Package (DFDP)
Available from Atlanta Signal Processors, Inc. (ASPI), the The Digital Filter
Design Package (DFDP) is a user-friendly, menu-driven software package.
This package shortens the design time of various filter structures which use
digital filters with floating-point accuracy or fixed-point economy. The package consists of four interactive filter design modules capable of performing the
following functions:
1)
2)
3)
4)

Designing FIR filters (Kaiser window)
Designing FIR filters (Parks-McClellan)
Designing IIR filters (Butterworth, Chebychev I and II, and elliptic)
Generating TMS320C1 x assembly code by converting the ASCII file
which contains the filter coefficients into a fully commented assembly
language code for TMS320C1 x devices.
E-9

Appendix E - First-Generation TMS320 Development Support

Cascade and parallel structures as well as higher-performance iattice, normali~ed lattice, and orthogonal forms are included in the modules.
The DFDP can design filters to meet any piecewise linear response specification, evaluate filter characteristics before and after coefficient quantization,
and design special-purpose FIR filters, i.e., multi-band filters, differentiators,
Hilbert transformers, and raised-cosine filters. The DFDP can also generate
coefficients for filter implementations on any general-purpose processor or
signal processing chip, as well as fully commented assembly language code
for a variety of DSP chips. Magnitude, log magnitude, and impulse responses
can be plotted for printer or screen display; in addition, the phase, group delay,
and pole-zero map can be plotted for II R filters. After the filter is designed,
the user can generate code associated with the filter using the CGEN design
module.
The DFDP runs on the IBM PS/2, IBM PC/XT/AT, and compatible systems.
Operating systems must have 192K bytes of memory available. For more information, contact the nearest TI Field Sales Office. For details, contact Atlanta Signal Processors, Inc. via (404) 892-7265.

E.1.10 DSP Software Library
The Digital Signal Processing Software Library contains the major DSP routines (FFT, FIR/IIR filtering, and floating-point operations) and application
algorithms (echo cancellation, ADPCM, and DTMF coding/decoding) as
presented in the book, Digital Signal Processing Applications with the
TMS320 Family (literature number SPRA012A). These routines and algorithms are written in TMS320C1 x source code as well as TMS320C2x source
code. In addition, macros for the TMS320C1 x are included in this library.
The software package consists of four diskettes for use with the IBM
PC/MS- DOS (version 1.1 or later) or a 1600 BPt magnetic tape for the
VAX/VMS version. All the directories on the PC/MS-DOS version are contained on the magnetic tape for the VMS version. Each directory contains a
README.L1S file briefly describing the contents of the files in the directory
and the reference to the code. The book, Digital Signal Processing Applications with the TMS320 Family (literature number SPRA012A), serves as the
major reference for theory an'd application of the algorithms; printed codes for
'
the application reports are given in the appendices.
The library can also be ordered separately through TI (see Table E-2 for ordering information). All of the software in the library is copyrighted by Texas
Instruments. The library is continually being updated; to obtain current information, contact TMS320 DSP Bulletin Board via (713) 274-2323.

E-1Q

Appendix E - First-Generation TMS320 Development Support

E.1.11 TMS320 Bell 212A Modem Software
Texas Instruments is offering a software package containing source code and
documentation for the design and implementation of a 1200-bps Bell 212A
modem with the TMS320C17 IE17 digital signal processor and the TMS7041
microcontroller.
The documentation included in the package consists of two reports. One report discusses in detail the theory behind the design of the modem, as well
as the functions implemented. The second report describes the hardware, algorithms, and coding techniques used in the implementation of a Bell 212A
modem demonstration unit. This implementation has been built and tested to
verify its operation. After reading this report, the user should be able to design
and build a similar unit as well as understand some tradeoffs involved in
making custom modifications.
The source code for the TMS320 Bell 212A Modem Software package is
provided on a 5 1/4" floppy for PC/MS-DOS or compatible operating sys'
tems. Contact the nearest TI Field Sales Office for further information.

E.1.12 TMS320 DSP Hotline/Bulletin Board Service
The TMS320 group at Texas Instruments provides a DSP Hotline to answer
TMS320 technical questions, i.e., device problems, development tools, documentation, upgrades, and new TMS320 products. The hotline operates five
days a week from 8:00 AM to 6:00 PM Central Time. The commercial telephone number is (713) 274-2320. To order literature, call the Customer Response Center (CRC) at 1-800-232~3200. Additionally, the TMS320 DSP
maintains a facsimile (FAX) hotline which may be used for technical questions and other information; the FAX hotline number is (713) 274-2324. For
details and availability of TMS320 devices or development tools, contact the
nearest TI Field Sales Office.
The TMS320 DSP Bulletin Board Service is a telephone-line computer bulletin
board that provides access to information pertaining to TMS320 devices.
Specification updates for current or new TMS320 devices and development
tools are communicated via the bulletin board as the information becomes
available. The Bulletin Board Service can be accessed by dialing (713) 2742323 with a 2400-, 1200-, or 300-bps modem.
The bulletin board contains TMS320 source code from the application reports
included in the book, Digital Signal Processing Applications with the TMS320
Family (literature number SPRA012A). The bulletin board also provides new
DSP applications software as it becomes available. See the TMS320 Family
Development Support Reference Guide (literature number SPRU011A) for
information on how to access the bulletin board.

E-11

Appendix E - Part Order Information

E.~

Part Order Information
This section provides the device and support tool part numbers. Table E-1
lists the part numbers for all the first-generation members of the TMS320
family. Table E-2 gives ordering information for TMS320C1 x hardware and
software support tools. Table E-3 provides a list and description of the development tool connections to a target system. A discussion of the TMS320
family device and development support tool prefix and suffix designators is
included to assist in understanding the TMS320 product numbering system.

E-12

Appendix E - Part Order Information

Table E-1. TMS320C1x Digital Signal Processor Part Numbers

TMS32010NL

2.4-~m

NMOS

OPERATING
FREQUENCY
20 MHzt

TMS320C10FNL
TMS320C10FNL25

2.0-~m
2.0-~m

CMOS
CMOS

20 MHz
25 MHz

Plastic
44-lead PLCC

TMS320C10NA

2.0-~m

CMOS

20 MHz

Plastic
40-pin DIP

TMS320C10NL
TMS320C1 ON L14
TMS320C10NL25
TMS320C14FNL

2.0-~m
2.0-~m
2.0-~m

CMOS
CMOS
CMOS

Plastic
40-pin DIP

1.6-~m

CMOS

20
14
25
25

TMS320E14FZL

1.6-~m

CMOS

25 MHz:!:

TMS320C15FNL
TMS320C15FNL25

1.8-~m
1.8-~m

TMS320C15NL
TMS320C15NL25

1.8-~m
1.8-~m

CMOS
CMOS
CMOS
CMOS

20
25
20
25

TMS320E15FZL
TMS320E15FZL25

2.0-~m
2.0-~m

CMOS
CMOS

TMS320E15J DA

2.0-~m

TMS320E15JDL
TMS320E15JDL25

DEVICE NAME

TECHNOLOGY

MHzt
MHz
MHz
MHz:!:

PACKAGE
TYPE

TYPICAL
POWER

Plastic
40-pin DIP

900mW
165mW
200mW
165 mW

Plastic
68-lead PLCC

165 mW
140 mW
200mW
275mW

Plastic
68-lead CER1QUAD

325mW

Plastic
44-lead PLCC

165mW
200mW

Plastic
40-pin DIP

165mW
200mW

20 MHz
25 MHz

Ceramic
44-lead CER-QUAD

275mW
325mW

CMOS

20 MHz

Ceramic
44-pin DIP

275mW

2.0-~m
2.0-~m

CMOS
CMOS

20 MHz
25 MHz

Ceramic
40-pin DIP

275mW
325mW

TMS320C17FNL

1.8-~m

CMOS

20 MHz

Plastic
44-lead,PLCC

250mW

TMS320C17NL

1.8-~m

CMOS

20 MHz:!:

Plastic
40-pin DIP

250mW

TMS320E17FZL

2.0-lJm CMOS

20 MHz

Ceramic
44-lead CER-QUAD

275mW

TMS320E17JDA

2.0-fJm CMOS

20 MHz

Ceramic
40-pin DIP

275mW

TMS320E17JDL

2.0-fJm CMOS

20 MHz

Ceramic
40-pin DIP

275mW

MHz
MHz
MHz:!:
MHz

tMilitary version available,
:!:Military versions planned; contact TI Field Sales Office for availability.

E-13

Appendix E - Part Order Information

Table E-2. TMS320C1x Support Tool Part Numbers
TOOL DESCRIPTION

OPERATING SYSTEM

PART NUMBER

SOFTWARE
Macro Assembler/Linker

Simulator
~

PC/MS-DOS
VAXNMS
VAX ULTRIX
SUN-3 UNIX

TM DS3242850-02
TMDS3242250-08
TM DS3242260-08
TMDS3242550-08

PC/MS-DOS
VAXNMS

TMDS3240811-02
TMDS3240211-08

Digital Filter Design Package

IBM PC-DOS

DFDP/IBM002

DSP Software Library

PC/MS-DOS
VAXNMS

TMDC3240812-12
TMDC3240212-18

TMS320 Bell 212A Modem Software

PC/MS-DOS

TM DX3240813-12

Data Encryption Standard
Software

PC/MS-DOS

TMDX3240814-12

HARDWARE
Evaluation Module (EVM)

RTC/EVM320A-03

XDS/22 Emulator
TMS320C10/C15
TMS320C14
TMS320C17

TMDS3262211
TM DX3262214
TMDX3262217

XDS/22 Upgrade Kit
TMS32010 to TMS320C1 0/C15
TMS320C1 0/C15 to TMS320C14
TMS320C1 0{C15 to TMS320C17
Analog Interface Board 1 (AIB1)
Analog Interface Board 2 (AIB2)

RTC/EVM320C-06
RTC/ AI B320A-06

EPROM DSP Starter Kit (TMS320E15)

RTC/EVM320E-15

EPROM Programmer Adaptor,Socket
40- to 28-pin (TMS320E15/E17)
44- to 28-pin (TMS320E15/E17)
68- to 28-pin (TMS320E14)
Additional Target Connector
44-lead PLCC (TMS320C10)

E-14

TMDS3282215
TMDX3285010 and
TMDX3285018
TM DX3285014 and
TM DX3285018

RTC/PGM320A-06
RTC/PGM320C-06
TM DX327011 0
TM DX328881 0

Appendix E - Part Order Information

Table E-3. Development Tool Connections to a Target System
TOOL

TARGET CONN.

INCL.

TMS320C10 XDS/22

40-pin DIP
44-lead PLCC

TMS320C10 XDS/22
(Upgrade Kit)

40-pin DIP
44-Iead PLCC

TMS320C14 XDS/22

68-lead PLCC

TMS320C17 XDS/22

40-pin DIP
44-lead PLCC

TMS32010 EVM

40-pin DIP

OPT.

PART NUMBER

TMDS3288810

TMDS3288810
TM DX3262214

TMDS3288810
RTC/EVM320A-03

E-15

Appendix E - Part Order

E.2.1

Inform~tion

Device and Development Support Tool Prefix Designators
To assist the user in understanding the stages in the product development
cycle, Texas Instruments assigns prefix designators to the part numbers of all
TMS320 devices and support tools. Each TMS320 member will have one of
~hree prefix designators: TMX, TMP, and TMS. TI recommends two of three/
possible prefix designators for its support tools: TMDX and TMDS. These
prefixes represent one of the evolutionary stages of product development from
engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS). This development flow is defined below.
,

Device Development Evolutionary Flow:
TMX

Experimental device that is not necessarily representative of the final
device's electrical specifications.
.

TMP

Final silicon die that conforms to the device's electrical specifications
but has not completed quality and reliability verification.

TMS

Fully qualified production device.

S~pport

Tool Development Evolutionary Flow:

TMDX

Development support product that has not yet completed Texas Instruments internal qualification testing.

TM DS

Fully qualified development support product.

TMX and TMP devices and TMDX development support tools are shipped
against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TM DS development support tools have been fully characterized and the quality and reliability of the device has been fully demonstrated. Texas Instruments standard warranty applies.

Note:
Predictions show that prototype devices (TMX or TMP) will have a greater
failure rate than the standard production devices. Texas Instruments recommends that these.devices not be used in any production system since
their expected end-use failure rate is still undefined. Only qualified production devices are to be used.

E-16

Appendix E - Part Order Information

E.2.2 Device and Development Support Tool Nomenclature
In addition to the prefix, the device nomenclature includes a suffix that follows
the device family name. This suffix indicates the package type (e.g., N, FN,
or GB) and temperature range (e.g., L). Figure E-6 provides a legend for
reading the complete device name for any TMS320 family member.

TMS 320

PREFIX _ _ _ _ _ _....JI
TMX
TM P
TMS
SMJ

=
=
=
=

experimehtal device
prototype device
qualified device
MIL-STD-883C

DEVICE FAMILY
320 = TMS320 family
TECHNOLOGY-------~

C = CMOS
E = CMOS EPROM
No letter = NMOS

15 JD

TEMPERATURE RANGE
L = 0 to 70'C
S = -55 to 100'C
M= -55 to 125'C
A = -40 to 85'C
PACKAGE TYPE
N = plastic DIP
JD= ceramic DIP
side- brazed
J = ceramic CER-DIP
GB= ceramic PGA
FZ = ceramic CER-QUAD
FN= plastic leaded CC
FD= ceramic leadless CC
DEVICE
1 st-gen. DSP.
10

14
15

17
2nd-gen. DSP:
20
25
3rd-gen. DSP:
30

Figure E-6. TMS320 Device Nomenclature

E-17

Appendix E - Part Order Information

Figure E-7 provides a legend for reading the, part number for any TMS320
hardware or software development tool.

TMDS 32 40810-02
QUALIFICATION STATUS
TMDX = prototype
TMDS = qualified

MEDIUMt
2 = 5 1/4" floppy disk
8 = 1600 BPI magnetic tape

DEVICE FAMilY _ _ _ _---I
32 = TMS320 famil"

PRODUCT TYPE - - - - - - - '
4 = software
6 = hardware
8 = upgrade

-----------i

S/W FORMAn
o = object code
1 = source code

L...-_ _

SEQUENCE NUMBER!:

MODEL:!:
11 = XDS/11
22 = XDS/22
88 = upgrade kits

t - - - - GENERATION.:!:

OPERATING SYSTEMt ------1
02 = 1st-gen. VAXjVMS
08 = 1st-gen. IBM PC/MS-DOS
22 = 2nd-gen. VAXjVMS
28 = 2nd-gen. IBM PC/MS-DOS
32 = 3rd-gen. VAXjVMS
38 = 3rd-gen. IBM PC/MS-DOS

L--_ _ _

1 = 1st-gen.
2 = 2nd-gen.
3 = 3rd-gen.
FORMAn
1 = TI-tagged
5 = COFF

t Software only.
:!: Hardware only.

Figure E-7. TMS320 Development Tool Nomenclature

E-18

Appendix F

Memories, Analog Converters, Sockets, and
Crystals

This appendix provides product information regarding memories, analog converters, and sockets, which are manufactured by Texas Instruments and compatible with the TMS320C1 x. Information is also given regarding crystal
frequencies, specifications, and vendors.
The contents of the major areas in this appendix are listed below.
•

TI Memories and Analog Converters (Section F.1 on page F-2)
EPROM memories
Codecs and filters
Analog interface circuits
A/D and D/A converters.

•

TI Sockets for DIP and PLCC Packages (Section F.2 on page F-139)
Production sockets
Burn-in/test sockets.

•

Crystals (Section F.3 on page /--144)
Commonly used crystal frequencies
Crystal specification requirements
Vendors of suitable crystals.

Appendix F - TI Memories and Analog Converters

F.1 TI Memories and Analog Converters
This section provides pages of product information taken from data sheets for
EPROM memories, codecs, analog interface circuits, and D/A and D/A converters.
All of these devices can be interfaced with TMS320C1 x processors (see Section 6 for hardware interface designs). Refer to Digital Signal Processing Applications with the TMS320 Family (literature number SPRA012A) for
additional information on interfaces using memories and analog conversion
devices.
The following paragraphs give the name of each device and where the data
sheet for tha~ device is located in order to obtain further specification information if desired.
Data sheets for EPROM memories are located in the MOS Memory Data Book
(SMYD006). The name of the device and the page number in the book on
which the device is introduced are listed.
TMS27C64
TMS27C128
TMS27C256
TMX27C512

(page
(page
(page
(page

6-55)
6-79)
6-91 )
6-105)

Another EPROM memory, TMS27C291/292, is described in. a data sheet
(SMLS291A).
The TCM29C13/14/16/17 codecs and filters are described in the data sheet
beginning on page 2-111 of the Telecommunications Circuits Data Book
(SCT001). An analog interface for the DSP using a codec and filter is provided by the TCM29C18/19 (data sheet number SCT021).
The data sheet for the TLC32040 analog interface circuit is provided in the
Interface Circuits Data Book (SLYD002); see page 2-271.
In the same book, data sheets for A/D and 0/ A converters can be found. The
name of the device and the introductory pages are as follows:
TLC0820
TLC1205/1225
TLC7524

F-2

(page 2-113)
(page 2-181)
(page 2-243)

TMS27C64 65,536·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC64 65,536·BIT PROGRAMMABLE READ·ONLY MEMORY
I

NOVEMBER 1985-REVISED APRIL 1988

This Data Sheet is Applicable to All
TMS27C64s and TMS27PC64s Symbolized
with Code "A" as Described on Page 12.
•

Organization ... 8K )( 8

•

Single 5·V Power Supply

•

Pin Compatible with Existing 64K MOS
ROMs, PROMs, and EPROMs

•

All Inputs/Outputs Fully TTL Compatible

•

Max Access/Mln Cycle TImes
VCC ±5%
'27C64-100
'27C/PC64-120
'27C/PC64-1
'27C/PC64-2
'27CIPC64

•

N PACKAGE
(TOPVIEWI

Vcc
PGM
NC

AS
A9
All

G
Al0

E
Q8

VCC ±10%
100
120
150
200
250

'27CIPC64-12
'27C/PC64·15
'27C/PC64-20
'27C/PC64-25

ns
ns
ns
ns
ns

Q2
Q6
Q3
Q5
GND --.. _ _. r - Q4

Power Saving CMOS Technology

•
• 3-State Output Buffers
mV Guaranteed DC Noise Immunity
• 400
with Standard TTL Loads
Latchup Immunity of 250 mA on All Input
• and
Output Lines
Power Dissipation (VCC
5.25 VI
• Low
- Active ... 158 mW Worst Case

yery High-Speed SNAPI Pulse Programming
or Fast Programming Algorithms

- Standby . . . 1.4 mW Worst Case
(CMOS Input Levelsl

•

AO-A12
~

G
GND
NC
NU
j5GJ;il'

PIN NOMENCLATURE
Address Inputs
Chip Enable Power Down
Output Enable
Ground
No Connection

01·08

Make No External Connection
Program
Outputs

vcc

5N Power Supply

Vpp

12·13 V Progremmlng Power Supply

PEP4 Version Available with 168 Hour
Burn-In, and also Extended Guaranteed
Operating Temperature Ranges

description
The TMS27C64 series are 65,536-bit, ultraviolet-light erasable, electrically programmable read-only
memories.
The TMS27PC64 series are 65,536-bit, one-time, electrically programmable read-only memories.
These devices are fabricated using power saving CMOS technology for high-speed and simple interface
with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL
circuits without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without
external resistors.
The data outputs are three-state for connecting multiple devices to a common bus. The TMS27C64 and
the TMS27PC64 are pin compatible with '2a-pin 64K MOS ROMs, PROMs, and EPROMs.

PRODUCTIOI DATA . 1.._ _II h.fInIotiln
..,nIIlM If , ..11aIio1 Uto........ '"""- '"
.,.aticIti... pol" doe _
01 T_
III•••'" .....IIly. Pradnllo. p............ lot
._rlly IICI•• II1II•• 01 .11 , . . . - .

"1IrU_

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TeXAS 77001

F-3

TMS27C128131.072;BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC128131.072·BIT PROGRAMMABLE READ·ONLY MEMORY
OCTOBER 1984 - REVISED FEBRUARY 1989

J AND N PACKAGES

This Data Sheet is Applicable to All
TMS27C 128s and TMS27PC 128s Symbolized
with Code"A" as Described on Page ".

Organization... 16K x 8

•

Single 5· V Power Supply

•

Pin Compatible with Existing 128K MOS
ROMs, PROMs, and EPROMs

•

AlllnputslOutputs Fully TTL Compatible
VCC ±10%
'27C128-12
'27C/PC128-15
'27C/PC128-20
'27C/PC128-25

100ns
120ns
150ns
200ns
250ns

•

Power Saving CMOS Technology

•

Very High-Speed SNAPI Pulse Programming
or Fa8t Programming Algorithms

•

3-State Output Buffers

•

400 mV Guaranteed DC Noise Immunity with
Standard TTL Loads

•

Latchup Immunity of 250 mA on All Input and
Output Lines

•

Low Power Dissipation (VCC = 5.25 VI
- Active . . . 158 mW Worst Case
- Standby ..• 1.4 mW Worst Case
(CMOS Input Levelsl

PGM

PEP4 Version Available with 168 Hour Burnin, and also Guaranteed Operating
Temperature Ranges

•

128K EPROM Available with MIL-STD-883C
Class B High Reliability Processing
(SMJ27C1281

The TMS27C128 series are 131,072-bit,
ultraviolet-light
erasable,
electrically
programmable read-only memories.
The TMS27PC128 series are 131, 072-bit, onetime, electrically programmable read-only
memories.

Al0

E
08
07
06
05
04

FM PACKAGE
(TOP VIEW)

A6
A5
A4
A3
A2
Al
AO

1 323130
29
28

5
6

A8
AS'
All

7
8
9

27
26
25

10
11

24
23

22
21
14 15 16 17 18 1920

Al0
08
07

PIN NOMENCLATURE
AO-AI3 Address Inputs

description

GND

'43

•

A13
A8
AS
All

A5
A4
A3
A2
Al
AO
01
02
03

Max AccesslMin Cycle Times
VCC ±5%
'27C128-100
'27C128-120
'27C/PC128-1
'27C/PC128-2
'27C/PC128

VCC

A12

•

(TOPVIEWI

Vpp

Chip Enable/Power Down

Output Enable

GND

Ground

No Connection
Make No External Connection
Program

NU
PGM
01-a8
VCC
Vpp

Outputs
5-V Power Supply
12-13 V Programming Power Supply

These devices are fabricated using power-saving
CMOS technology for high speed and simple
interface with MOS and bipolar circuits. An inputs

F-4

PRODUcnol DATA dacl_ ..ltOi. inlarmatian
I.""nt II of plllllicatiDl ditto. ProtIUItI IInhrm t.
IPOCIllcati... (III' tho tonIl of T.... IIltruNntI
ntI"""nI
Pro••atI•• pre....i.. doII.at
.......rily 1.00odo _I•• of.1I pore_no

"""nty.

TEXAS •
INSTRUMENis
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

TMS27C256 262,144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC256 262,144-BI1 PROGRAMMABLE READ-ONLY MEMORY
SEPTEMBER 1984 - REVISED FEBRUARY 1989

This Data Sheet is Applicable to All
TMS27C256s and TMS27PC256s Symbolized
with Code "A" as Described on Page 12.
•

Single 5-V Power Supply

•

Pin Compatible with Existing 256K MOS
ROMs, PROMS, and EPROMs

•

All Inputs/Outputs Fully TTL Compatible

•

Max Access/Min Cycle Times
VCC ±5%

VCC ±10%

'27C256-120
'27C/PC256-150
'27C/PC256-1
'27C/PC256-2
'27C/PC256

'27C256-12
'27C/PC256-15
'27C/PC256-17
'27C/PC256-2Q
'27C/PC256-25

120
150
170
200
250

ns
ns
ns
ns
ns

•

Power Saving CMOS Technology

•

Very High Speed SNAP! Pulse Programming
or Fast Programming Algorithms

•

3-State Output Buffers

•

400 mV Guaranteed DC Noise Immunity
with Standard TTL Loads

•

Latchup Immunity of 250 mA on All Input
and Output Lines

•

Low Power Dissipation (VCC = 5.25 VI
- Active . . . 158 mW Worst Case
- Standby ... 1.4 mW Worst Case
(CMOS-Input Levels)

•

ITOPVIEWI

Organization ... 32K x 8

•

J AND N PACKAGES

Vpp

VCC

A12
A7
AS
A5
A4
A3
A2
AI
AO
01
02
03
GND

A14
A13
A8
A9
All

G
Al0

E
08
07

as
05
04

FM PACKAGE
ITOPVIEWI

4 3 2 1 323130
29
0
ASP5
A5 6
28
A4 7
27
A3 8
26
A2 9
25
AI 10
24j
AO 11
23!
22j
NC 12
01 13
21j
14151617181920

PEP4 Version Available with 168 Hour Burnin, and also Guaranteed Operating
Temperature Ranges

A8
A9
All
NC

G
Al0

E
08
07

<'IMC::J''««

Low-Power CMOS Technology

•

5.25 VI

1 282726
A4 5
0
25 Al0
A3 6
24 51 t
A2 7
23 S2t
Al 8
22 S3t
AD 9
21 NC
NC 10
20 Q8
Ql 11
19 Q7
12131415161718

oLl-

tThese pins have different pin assignments and
functions in the program mode (see page 3).

>
o

description
The TMS27C291 and TMS27C292 series are
16,384-bit, ultraviolet-light erasable, electrically
programmable read-only memories. The
TMS27PC291 series are 16,384-bit, one-time,
electrically programmable read-only memories.
These devices are fabricated using CMOS
technology for tligh speed and simple interface
with MaS and bipolar circuits. All inputs
(including program data inputsl can be driven by
Series 74 TTL circuits without the use of
external resistors. Each output can drive eight
Series 74 TTL circuits without external resistors.
The data outputs are three-state for connecting
multiple devices toa common bus. The J and N
dual-in-line packages are pin compatible with
existing 24-pin bipolar PROMs and high speed
EPROMs.

a::

U
Z

«
«

READ MODE
PIN NOMENCLATURE

AD-AI 0

Address Inputs

GND

Ground

No Connection
Outputs

01-08
~1. 52. 53
VCC

Chip Selects

5-V Power Supply

The TMS27C291 and TMS27C292 are offered in dual-in-line ceramic packages (J suffix). The TMS27C291
ceramic package is designed for insertion in mounting-hole rows on 7,62-mm (300-mill centers. The
TMS27C292 ceramic package is designed for insertion in mounting-hole rows on 15,24-mm (600-mill
centers.
ADVAICE IIFORMATIOI ....orn. now produell in
tho ..mpli.. or pnp..~.ctiDft p..... of ............,.
CbarlCllriIlic uta .... IIIhIIr .....fi..tio.. In
••bjact ta ....... without .oti...

TEXAS

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

F-7

TMS27C291. TMS27C29216.384·BIT UV
ERASABLE PROGRAMMABLE READ·OlLY MEMORIES
TMS27PC291 16.384·BIT PROGRAMMABLE READ·OlLY MEMORY
The TMS27PC291 PROM is offered in dual-in-line plastic package (N suffix) designed for insertion in
mounting-hole rows on 7,62-mm (300-mil) centers. This version of the device is still in development, and
the ADVANCE INFORMATION notices in this data sheet pertain to the N package devices. The
TMS27PC291 PROM is also offered in a 28-lead plastic-leaded chip carrier (FN suffix) for surface mountihg
applications on solder lands on 1,27-mm (50-mil) centers.
All devices are guaranteed for operation from O°C to 70°C.
operation
There are eight modes of operation for the TMS27C291, TMS27c292 and the TMS27PC291 as listed
in the following table. The read mode requires a single 5-V supply. All inputs are TTL or CMOS levels except
for Vpp during programming (13.5 V).
MODE
FUNCTION

Read

Output

Program
Disable' Disabla# Disable' Verify

Program
Inhlblt\

Fast
Program'

Blank Check

Ones

Zeros

Signature

Sl/Vppt

Vil

VIH

VPP

Vpp

Vll(P)'

Vll(P)

Vil

S2/VF'i't

VIH

Vil

Vll(P)

VIH(P)

Vll(P)

VIH(P)

VIH

S3/PGMt

VIH

Vil

VIH(P)

Vll(P)

VH§

Vee

Vpp

VPP

Vil

VIH

CODE

01-08

DOUT

HI-Z

DOUT

HI-Z

DIN

Ones

Zeros

MFG.l DEV
97

tPin assignment for program mode.

*X can be Vil or VIH.
§VH = ·12 V ± 0.5 V.
'(PI = Programming mode.
'Output can be disabled using any of these three methods.

read/output disable
I

When the outputs of two or more of these devices are connected in parallel on the same bus, the output
of any particular device in the circuit can be read with no interference from competing outputs of the other
devices. To read the output of a '27C291, '27PC291, or '27C292, a low-level signal is applied to 51 and
a nigh-level signal is applied to S2 and S3. Any other combination of logic states on these three inputs
will disable the outputs. Output data is accessed at pins 01 through 08.
latchup immunity
Latchup immunity is a minimum of 250 mA on all inputs and outputs. This feature provides latch up immunity
beyond any potential transients at the P.C. board level when the devices are interfaced to industry-standard
TTL or MOS logic devices. The input/output layout approach controls latchup without compromising
performance or packing density.

F-8

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

TCM129C13. TCM129C14. TCM129C16. TCM129C17.
TCM29C13. TCM29C14. TCM29C16. TCM29C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
REVISED JUNE 1988

•

Replaces Use of TCM2910A in Tandem
with TCM2912C

•

Reliable Silicon-Gate CMOS Technology

•

Low Power Consumption:
Operating Mode . . . 80 mW Typical
Power-Down Mode ... 5 mW Typical

FEATURE TABLE
129C13 129C14 129C16 129C17
29C13
29C14
29C16
29C17

FEATURE
Number of Pins:

•

24
20
16

Excellent Power Supply Rejection Ratio Over
Frequency Range of 0 to 50 kHz

wlaw/A-Iaw Coding:

wlaw
A-law

X
X

X
X
X

Data Timing Rates:

•

No External Components Needed for
Sample. Hold, and Auto-Zero Functions

•

Precision Internal Voltage References

•

Direct Replacement for Intel 2913, 2914,
2916. and 2917

•

X
X

Variable Mode

64 kHz to 2.048 MHz
Fixed Mode

1.536 MHz
1.544 MHz
2.048 MHz
Loopback Test Capability
8th· Bit Signaling

TCM29C13N-3 is Primarily Used for LowCost DSP Applications with TMS320CXX

description
TheTCM129C13, TCM129C14, TCM129C16, TCM129C17. TCM29C13. TCM29C14. TCM29C16, and
TCM29C17 are single-chip pulse-code-modulated encoders and decoders (PCM codecs) and PCM line filters.
These devices provide all the functions required to interface a full-duplex (4-wire) voice telephone circuit
with a time-division-multiplexed (TOM) system. These devices are intended to replace the TCM291 OA
in tandem with the TCM2912C. Primary applications of the devices include:
.
• Line Interface for Digital Transmission and Switching of Tl Carrier. PABX. and Central Office
Telephone Systems
• Subscriber Line Concentrators
• Digital Encryption Systems
• Digital Voice Band Data Storage Systems
• Digital Signal Processing
TCM129C13 ... OW. OV. J. OR N PACKAGE
TCM29C13 ... OW. OV. J. OR N PACKAGE
TCM29C13N·3 ... N PACKAGE

TCM129C16. TCM129C17 ... J OR N PACKAGE
TCM29C16. TCM29C17 .•• J OR N PACKAGE
(TOP VIEW)

(TOP VIEWI

VBB

VCC
GSX

PWRO+
PWRO -

CLKSEL
DCLKR
PCM IN
FSR/TSRE
DGTL GND

ANLG IN

9
11

ANLG IN+
ANLG GND
ASEL
TSXIDCLKX
PCM OUT
FSX/TSXE
CLKR/CLKX

TCM129C14 ... OW OR JW PACKAGE
TCM29C14 ..• OW OR JW PACKAGE
(TOP VIEW)

vcc

VBB
PWRQ+
PWRO·
GSR
PDN

SIGR
DCLKR
PCM IN
DGTL GND

PWAO+
PWRO-

GSX
ANLG IN
ANLG IN+
ANLG GND
NC
SIGX/ASEL
TSXIDCLKX
PCM OUT
FSX/TSXE
CLKX
CLKR

DCLKR
PCM IN
FSR/TSRE
DGTL GND

VCC
GSX
ANLG INANLG GND
TSX/DCLKX
PCM OUT
FSX/TSXE
CLKR/CLKX

Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PRODUCTION DATA do.umants .ontain informltion
currant IS of publicatioR dlta. Products confarm to

specifications per the terms of TIXI. Instruments

=~~i~I[::h:l.; =:~i:.n :'i~::!:t!s~ nDt

TEXAS

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

F-9

TCM129C13. TCM129C14. TCM129C16. TCM129C17
TCM29C13. TCM29C14. TCM29C16. TCM29C17

COMBINED SINGLE-CHIP PCM CODEC AND FILTER
description (continued)
These devices are designed to perform the transmit encoding (AID conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a pulse-code-modulated system. They
are intended to be used at the analog termination of a PCM line or trunk.
The TCM129C13, TCM129C14, TCM129C16, TCM129C17, TCM29C13, TCM29C14, TCM29C16, and
TCM29C 17 provide the bandpass filtering of the analog signals prior to encoding and after decoding, These
combination ,devices perform the encoding and decoding of voice and call progress tones as well as the
sig'naling and supervision information.
The TCM29C13N-3 is the same as the TCM29C13N except for certain parameters as indicated in the
specification section.
The TCM129C13, TCM129C14, TCM129C16, and TCM129C17 are characterized for operation from
-40°C to 85°C. The TCM29C13, TCM29C14, TCM29C16, and TCM29C17 are characterized for
operation from OOC to 70°C.

functional block diagram
TRANSMIT
SECTION

AUTO
ZERO
PCMOUT

ANLGIN+

COMPARA·
TOR

ANLGIN-

TSX/DCLKX
SIGX/ASEL

GSX-I-;=~~
ANALOG
T~~~~~~~_ _ _ _ _ _ _~~'-_~FsxrrSXE

LOGIC

CLKX

RECEIVE
S~CTION

,...----'L..o..L CLKSEL
PDN
ANLG ~oopt

GSR

PCMIN

DLCKR
PWRO-

SIGRt

VCC

VBB

DGTL ANLG
GND GND

FSRrrSRE
CLKRt

tTCM129C14 and TCM29C14 only
*TCM129C13. TCM129C16, TCM129C17, TCM29C13, TCM29C16, and TCM29C17 only.

F-l0

, TEXAS'"

INSTRUMENTS
POST OFFICE

Box 655012

• DALLAS. TEXAS 75265

TCM129C13. TCM129C14. TCM129C16. TCM129C17
TCM29C13. TCM29C14. TCM29C16. TCM29C17

COMBINED SINGLE·CHIP PCM CODEC AND FILTER
PIN
TCM129C16
TCM129C13

TCM129C14

TCM129C17

TCM29C13

TCM29C14

TCM29C16

NAME

DESCRIPTION

TCM29C17
Most negative supply voltage; input is - 5 V ± 5%.

Vss

PWRO+

Noninverting output of power amplifier. Can drive transformer hybrids or
high-impedance loads directly in either a differential or a single-ended

configuration.

PWRO-

Inverting output of power amplifier; functionally identical with and
complementary to PWRO + .

Input to the gain-setting network on the output power amplifier.

GSR

Transmission level can be adjusted over a 12-d8 range depending upon
the voltage at GSA.

Power-down select. The device is inactive with a TTL low-level input to
this pin and active with a TTL high-level input to the pin.

CLKSEL

Clock frequency selection. Input must be connected to Vss. VCC. or
ground to reflect the master clock frequency. When tied to VBB. eLK is
2.048 MHz. When tied to ground. CLK is 1.544 MHz. When tied to VCC.
CLK is 1.536 MHz.

ANLG LpOP

Provides loopback test capability. When this input is high. PWRO + is
internally connected to ANLG IN.

Signaling bit output. receive channel; in a fixed-data-rate mode, outputs

SIGR

the logical state of the 8th bit (LSSI of the PCM word in the most recent
signaling frame.

DCLKR

Selects fixed or variable data-rate operation. When this pin is connected
to Vss. th~ device operates in the fixed-data-rate mode. When DCLKR
is not connected to VBB, the device operates in the variable-data-rate
mode. and DCLKR becomes the receive data clock. which operates at
frequencies from 64 kHz to 2.048 MHz

PCM IN

Receive PCM input. PCM data is clocked in on this pin on eight consecutive
negative transitions of the receive data clock, which is ClKR in fixed-datarate timing and DCLKR in variable-data-rate timing.

FSR/TSRE

Frame synchronization clock input/time slot enable for receive channel.
In the fixed-data-rate mode, FSR distinguishes between signaling and nonsignaling frames by a double- or single-length pulse, respectively. In the
variable-data-rate mode, this signal must remain high for the duration of
the timeslot. The receive channel enters the standby state when FSR is
TTL low for 300 ms.

DGTL GND

Digital ground for all internal logic circuits. Not internally connected to
ANLG GND.

Receive master clock and data clock for the fixed-data-rate mode. Receive

CLKR

master clock only for variable-data-rate mode. CLKR and CLKX are
internally connected together for TCM 129C 13. TCM 1 29C 16.

TCM129C17. TCM29C13. TCM29C16. and TCM29C17.

T~.

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

F·11

TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17

COMBINED SINGLE·CHIP PCM CODfC AND FILTER
PIN
TCM129C16
TCM129C13

TCM129C14

TCM129C17

TCM29C13

TCM29C14

TCM29C16

DESCRIPTION

NAME

TCM29C17
9

CLKX

Transmit master clock and data clock for the

fixed~data-rate,

mode.

Transmit master clock only for variable dina rate mode. CLKR and CLKX
are internally connected for the TCM 129C13, TCM 129C16, TCM129C 17,
TCM29C13, TCM29C16, and TCM29C17.
12

FSX/TSXE

Frame synchronization clock input/time-slot enable for transmit channel.
Operates independently of, but in an analagous manner to, FSR/TSRE.
The transmit channel enters the standby state when FSX is low for 300 ms.

PCM OUT

Transmit PCM output. PCM data is clocked out on this output on eight
consecutive positive transitions of the transmit data clock. which is CLKX

in fixed-data-rate timing and DClKX in variable-data-rate timing.
14

TSX/OCLKX

Transmit channel time slot strobe (output) or data clock (input) for the
transmit channel. In the fixed-data-rate mode, this pin is an open-drain
output to be used as an enable signal for a three-state buffer. In the
variable-data rate mode, OCLKX becomes the transmit data clock, which
operates at TTL levels from 64 kHz to 2.049 MHz.

SIGX/ASEL

Used to select between A-law and wlaw operation. When connected to

Ves,

A-law is selected. When connected to

Vee

or ground, u-Iaw is

selected. When not connected to Vss, it is a TTL-level input that is
transmitted as the eighth bit (LSS) of the PCM word during signaling frames
on the PCM OUT pin (TCM129C14 and TCM29C14 only). SIGX/ASEL
is internally connected to provide wlaw operation for TeM 129C 16 and
TCM29C16 and A-law operation for TCM129C17 and TCM29C17.
16

ANLG GND

Analog ground re,turn for all internal voice circuits. Not internally connected
to OGTL GND.

ANLG IN+

Noninverting analog input to un.::ommitted transmit operational amplifier.
,Internally connected to ANLG GND on TCM129C16, TCM29C16,
TCM129C17, and TCM29C17.

ANLG IN-

GSX

VCC

Inverting analog input to uncommitted transmit operational amplifier.
Output terminal of internal uncommitted operational amplifier. Internally,
this is the voice signal input to the transmit filter.
Most positive supply voltage, input is 5 V ± 5%.

(

F-12

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TCM129C13. TCM129C14. TCM129C16. TCM129C17
TCM29C13. TCM29C14. TCM29C16. TCM29C17

COMBINED SINGLE·CHIP PCM COOEC AND FILTER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Output voltage, Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to 15 V
Digital ground voltage ................................... '....... ~ . .. -0.3 V to 15 V
Continuous total dissipation at (or below) 25°C free-air temperature ................ 1375 mW
Operating free-air temperature range: TCM 129C_ ........................ - 40°C to 85 °C
TCM29C_ ............................ ooc to 70°C
Storage temperature range ......................................... - 65°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: OW, DY, or N package ... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or JW package ....... 300 °C
NOTES:

1. Voltage values for maximum ratings are with respect to Vee.

recommended operating conditions (see Note 2)
VCC

Supply voltage (see Note 3)

Vee

Supply voltage

MIN

NOM

MAX

UNIT

4.75

5.25

-4.75

DGTL GND voltage with respect to ANLG GND
V,H

High-level input voltage. all inputs except CLKSEL

V,L

Low-level input voltage, all inputs except CLKSEL
Clock select
input voltage

Load resistance

Load capacitance

Operating free-air temperature

-5 -5.25
0

2.2

For 2.048 MHz

Ve8
0

For 1. 544 MHz
For 1. 536 MHz

VCC-0.5
10

At GSX
At PWRO + and/or PWRO -

O.B

Vaa+ 0.5
0.5

VCC

kll
11

300

At GSX

50
100

AT PWRO+ and/or PWROTCMI29C_
TCM29C

V
V

-40

pF
·C

NOTES: 2. To avoid any possible damage and reliability problems to these CMOS devices when applying power, the following sequence
should be followed:
(1) Connect ground
(2) Connect the most negative voltage
(3) Connect the most positive voltage
(4) Connect the input signals
When powering down the device, follow the above steps in reverse order. If the above procedure cannot be followed, connect
a diode between V88 and digital ground, cathode to DGND. anode to Ve8.
3. Voltages at analog inputs and outputs. VCC. and Vee terminals are with respect to the ANLG GND terminal. All other voltages
are referenced to the DGTL GND terminal unless otherwise noted.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

F-13

TCM129C13, TCM129C14, TCM129C16,.,TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17

COMBINED SINGLE-CHIP PCM CODEC AND FILTER
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
. supply current. fOCLK - 2.048 MHz. outputs not loeded
TCM129C_ _
TEST CONDITIONS

PARAMETER*
I
Supply current
CC from VCC
Supply current
ISS

from VSS

TYpf

Operating
Standby

FSX or FSR at VIL after 300 ms

Power-down

J5r5N VIL after

10 ~s

Operating
Standby

FSX or FSR at VIL after 300 ms

Power-down

I5rnii VIL after

10 ~s

Operating

Power
dissipation

Standby

FSX or FSR at VIL after 300 ms

Power down

J5I5IiI VIL after

10 ~

TCM29C_ _

MAX

TYpt

MAX
9

0.7

1.5

0.5

0.4

0.3

0.8

-8

1
-13

-7

-0.7

-1.5

-0.5

-9
-1

-0.4

-1

-0.3

-0.8

130

MAX

MIN

UNIT

digital interface
PARAMETER

TEST CONDITONS

I PCM

TCM29C __

TCM129C _ _
MIN

TVpf

IOH = -9.6 mA

2.4

IOH = -1.2 mA

2.4

VOL

jSIGR
Low-Ieliel output voltage at PCM out. TSX, SIGR

IIH

High-level input current, any digital input

VI =2.2 V to Vce
VI = 0 to 0.8 V

VOH High-level output voltage

out

IOL = 3.2 rnA

IlL

Low~level

Input capacitance

Output capacitance

input current, any digial input

TVPt

MAX

UNIT
V
V

0.5

0.4

12
10

transmit amplifier input
PARAMETER

TEST CONDITIONS

Input current at ANLG IN +, ANLG INInput offset voltage at ANLG IN +, ANLG IN-

VI = - 2. 17 V to 2.17 V
VI - -2.17 V to 2.17 V

Common-mode rejection at ANLG IN +, ANLG IN-

VI = -2.17 Vto 2.17 V

Open-loop voltage amplification a\ GSX

MIN

TVpt

MAX

±25

5000

Open-loop unity-gain bandwidth at GSX

Input resistance at ANLG IN +, ANLG IN-

MHz

receive filter output
PARAMETER

TEST CONDITIONS

Output offset voltage PWRO +, PWRO - Ising Ie-ended)

Relative to ANLG GND

Output resistance at PWRO +, PWRO
tAli typical values are at VSS = -5 V, VCC = 5 V, and TA = 25°C.

F-14

UNIT

±100

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 656012. DALLAS, TeXAS 75265

MIN

TYpt
80

MAX

TCM129C13, TCM129C14, TCM129C16, TCM129Cl1
TCM29C13, TCM29C14, TCM29C16, TCM29Cl1
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
gain and dynamic range. Vee
Isee Notes 4. 5. and 6)
PARAMETER
Encoder milliwatt response
(transmit gain tolerance)
Encoder milliwatt response
(nominal supplies and temperature)
Digitsl milliwatt response (receive

tolerance gain) relative to zerotransmission level point
Digital milliwatt response variation
with temperature and supplies
Zero-transmission-Ievel
point, transmit channel
(0 dBmOI
Zero-transmission-Ievel

point, receive channel
(0 dBmO)

w law
A-law
wlaw
A-law
!,-Iaw
A-law
!,-Iaw
A-law

5 V. VBB -

-5 V. TA - 25°e lunless otherwise noted)

TEST CONDITIONS
Signal input = 1.064 V rms for wlaw Standard version
Signal input = 1.06B V rms for A-law TCM29C13N-3
TA = O'C to 70'C,
Supplies = ± 5%

MIN

I
I

Signal input per cCln G.711,
Output signal = 1 kHz

TYP
±0.04
±0.2

MAX
±0.2
±0.5
±0.08

Standard version

±0.04

±0.2

±0.5

UNIT
dBmO
dB

dBmO

ITCM29C13N-3

TA - O'Cto 70'C,
Supplies = ± 5%

±0.08
2.76
2.79
1.00
1.03
5.76
5.79
4.00
4.03

RL = 60011
RL=90011
RL = 60011
RL = 90011

dBm

NOTES: 4. Unless otherwise noted, the analog input is a O-dBmO, 1020-Hz sine wave, where 0 dBmO is defined as the zero-reference
point of the channel under test. This corresponds to an analog signal input of 1.064 V rms, or an output of 1.503 V rms.
5. The input amplifier is set for unity gain, noninverting. The digital input is a PCM bit stream generated by passing a O-dBmO,
1020-Hz sine wave through an ideal encoder.
6. Receive output is measured single-ended in the maximum-gain configuration. To set the output amplifier for maximum gain,
GSR is connected to PWRO - and the output is taken at PWRO +. All output levels are (sin x)/x corrected.

gain tracking over recommended ranges of supply voltage and operating free-air temperature. reference
level - - 10 dBmO
PARAMETER
Transmit gain tracking error, .sinusoidal input

Receive gain tracking error, sinusoidal input

TEST CONDITIONS
3 to -40 dBmO
- 40 to - 50 dBmO
- 50 to - 55 dBmO
3 to -40 dBmO
·40 to - 50 dBmO
50 to . 55 dBmO

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265

MIN

MAX
±0.25
±0.5
± 1.2
±0.25
±0.5
± 1.2

UNIT
dB

F-15

TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17

COMBINED SINGLE-CHIP PCM CODEC AND FitTER
noise over recommended ranges of supply voltage and operating free-air-temperature
TEST CONDITIONS

PARAMETER

MAX

MIN

ANLG IN+ - ANLG GND,

Transmit noise, C-message w'!'ighted

ANLG IN-

Transmit noise, C-message weighted with eighth-bit
signaling (TCM129C14·and TCM29C14 only)

ANLG IN+
ANLG IN-

=
=
=

GSX

UNIT

dBrnCO

-75

dBmOp

dBrnCO

dBmCO

-79

dBmOp

ANLG GND,
GSX,

6th frame signaling
ANLG IN +

Transmit noise. psophometrically weighted

ANLG IN PCM IN

Receive noise. C-message weighted quiet code

PCM IN

=
=

ANLG GND,
GSX

11111111 (wlaw)
10101010 (A-law)

measured at PWRO +
Receive noise.

C-mes~age

weighted sign

Input to PCM IN is zero code with sign bit

bit toggled

toggled at 1-kHz rate

Receive noise. psophometrically weighted

PCM

lowest positive decode level

power supply rejection and crosstalk attenuation over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER
V CC supply voltage

0 to 30 kHz

30 to 50 kHz

rejection ratio,
transmit channel
VBB supply voltage
rejection ratio,
transmit -channel

VCC supply voltage
rejection ratio,

receive channel
(single-ended)
VBB supply voltage
rejection ratio,

receive channel
(single-ended)

TEST CONDITIONS

= 0 to 30 kHz
= 30 to 50 kHz

= 0 to 30 kHz

200 mV p-p,

-30
200 mV p-p,

dB
-55
-20

200 mV p-p,

narrow-band, f measured

30 to 50 kHz

Idle channel,

-20

= 200 mV p-p,

narrow-band. f measured

= 30 to 50 kHz

ANLG IN+
f

(single-ended)

dBmO,

= 1 .02 kHz, unity gain,

PCM IN

-45

at PWRO+

Crosstalk attenuation, transmit-ta-receive

-45

at PWRO+
supply signal

UNIT
dB

Idle channel,

MAX

-45

f measured at PCM OUT

supply signal

Typt
-30

Idle channel,

to 30 kHz

MIN

f measured at PCM OUT
supply signal

Idle channel,
supply signal

lowest decode level,

measured at PWRO +

PCM IN - 0 dBmO,

Crosstalk attenuation, receive-to~transmit

(single-ended)
tAli typical values are at VBB

F-16

= 1.02 kHz,

Measured at PCM OUT

-5 V, VCC

5 V, and TA

25°C.

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17

COMBINED SINGLE-CHIP PCM CODEC AND FILTER
distortion over recommended ranges of supply voltage and operating free-air temperature
PARAMETER

TEST CONDITIONS

Transmit signal to distortion ratio. sinusoidal

input ICCITT G.712 - Method 2)

Receive Signal to distortion ratio. sinusoidal
input (CCITT G..712 - Method 2)

ANLG IN+

= 0 to

ANLG IN+ ANLG )N+
ANLG IN+
ANLG IN+
ANLG IN+

MIN

-30 dBmO

TYpt

MAX

UNIT

-30 to -40 dBmO

= -40 to -45 dBmO
= 0 to -30 dBmO
= -30 to -40 dBmO
= -40 to -45 dBmO

36
30

Transmit single-frequency distortion products

AT&T Advisory #64 (3.8), Input signal - 0 dBmO

-46

dBmO

Receive single-frequency distortion products

AT&T Advisory #64 (3.8), Input Signal

= 0 dBmO

-46

dBmO

CCITT G.712 (7.1)

-35

Intermodulation distortion, end-ta-end

CCITT G.712 (7.2)

-49

Spurious out-of-band signals, end-to-end

CCITT G.712 (6.11

-25

CCITT G.712 (9)
Transmit absolute delay time to PCM OUT

Fixed data rate, fCLKX

245

Input to ANLG IN + 1.02 kHz at 0 dBmO
f

Transmit differential envelope delay time

relative to transmit absolute delay time

f
f

Receive absolute delay time to PWRO +

-40

= 2.048 MHz,

= 500 Hz to 600 Hz
= 6\10 Hz to 1000 Hz
= 1000 Hz to 2600 Hz
= 2600 Hz to 2800 Hz

190

600 Hz

f - 600 Hz to 1000 Hz

= 1000 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
= 5V,andTA = 25°C.

110

-5V,VCC

relative to transmit absolute delay time

45
105

Receive differential envelope delay time

tAli typical values are at VBB

Digital input is DMW codes

= 500 Hz to

dBmO

170

Fixed data rate, fCLKR - 2.048 MHz,
f

dBmO

transmit filter transfer over recommended ranges of supply voltage and operating free-air temperature
(see Figure 1)
PARAMETER

TEST CONDITIONS

MIN

MAX

16.67 Hz

-30

50 Hz

-25
-23

60 Hz
Input amplifier set for unity

200 Hz

Gain relative to gain

gain, Noninverting maximum gain

at 1.02 kHz

output, Input signal at ANLG IN +
is 0 dBmO

-1.8

-0.125

300 Hz to 3 kHz

-0.15

0.15

3.3 kHz

-0.35

0.03

3.4 kHz
4 kHz

-1

-0.1
-14

-1.4

-0.1

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

-32

4.6 kHz and above
3.4 kHz (TCM29CI3N-3 only)

UNIT

F-17

TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17

COMBINED SINGLE-CHIP PCM CODEC AND FILTER
receive filter transfer over recommended ranges of supply voltage and operating free-air temperature
(see Figure 2)
PARAMETER

MIN

TEST CONDITIONS

MAX

UNIT

0.15

Below 200 Hz
-0.5

0.15

300 Hz to 3 kHz

-0.15

0.15

200 Hz
Gain relative to gain

Input signal at PCM IN

3.3 kHz

-0.35

0.03

at 1.02 kHz

is 0 dBmO

3.4 kHz
4 kHz

-1

-0.1

-14
-30

4.6 kHz and above
3.4 kHz (TCM29CI3N-3 only)

-1.4

-0.1

clock timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see timing diagrams)
PARAMETER

MIN

Clock period for ClKX. ClKR (2.048-MHz systems)

Typt

MAx

488

tc(ClK)
t r • tf

Rise and fall times for ClKX and ClKR

tw(ClK)

Pulse duration for ClKX and ClKR (see Note 7)

220

twU)ClKI

Pulse duration for OClK (fOClK = 64 Hz to 2.048 MHz) (see Note 7)

220

Clock duty cycle (tw(ClK)/tc(ClK)l for ClKX and ClKR

UNIT

ns
ns
ns

t All typical values are at VBB = - 5 V. VCC = 5 V. and T A = 25°C.

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, f,xed-data-rate mode (see timing diagrams)
PARAMETER

MIN

MAX

UNIT

100

tc(ClKI- 100

~IFSXI

Frame sync delay time

tsu(SIGX)

Setup time before Bit 7 falling edge (TCM129C14 and TCM29C14 only)

th(SIGXI

Hold time after Bit 8 falling edge (TCMI29CI4 and TCM29C14 only)

propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode
(see timing diagrams)
PARAMETER

tpdl
tpd2
tpd3
tpd4
tpd5
tpd6

TEST CONDITIONS

From rising edge of transmit clock to Bit 1 data valid at

PCM OUT (data enable time on time slot entry) Isee Note 8)
From rising edge of transmit clock Bit n to Bit n + 1 data

valid at PCM OUT (data valid time)
From falling edge of transmit clock Bit 8 to Bit 8 Hi·Z at
PCM OUT (data float time on time slot exit) (see Note 8)
From rising edge of transmit clock Bit 1 to TSX active

(low) Itime slot enable time)
From falling edge of transmit clock 8it 8 to TSX inactive
(high) (timeslot disable time) 'I see Note 8)

= Oto

MIN

MAX

145

215

145

190

0 to 100 pF
100 pF

Cl = 0
Cl = 0 to 100 pF
Cl ;" 0

From rising edge of channel time slot to SIGR update
(TCMI29CI4 and TCM29C14 only)

NOTES: 7. FSX ClK must be phase locked with the ClKX. FSR ClK must be phase locked with CLKR.
B. Timing parameters tpdl. tpd3. and tpd5 are referenced to the high·impedance state.

F-18

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

UNIT

TCM129C13, TCM129C14, TCM129C16, TCM129Cl1
TCM29C13, TCM29C14, TCM29C16. TCM29Cl1
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
receive timing requirements over recommended ranges of supply voltage and operating free"air
temperature. fixed-data-rate mode (see timing diagrams)
PARAMETER
IdIFSRI

Frame sync delay time

tsulPCM IN}

Setup time before

thlPCM INI

Hold time after Bit 8 falling edge ITCM129C14 and TCM29C14 only}

7 falling edge ITCM129C14 and TCM29C14 only}

MIN

MAX

UNIT

100

te1CLKI-l00

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature. variable-data-rate mode (see timing diagrams)
MIN

PARAMETER

MAX

UNIT

tdITSDX}

Timeslot delay time from DCLKX Isee Note 9}

140

tdIOCLKXI-140

tdIFSX}

Frame sync delay time

100

tclDCLKXI

Clock period for DCLKX

488

teICLK} - 100
15620

ns
ns
kHz

propagation delay times over recommended ranges of operating conditions. variable-data-rate mode
(see Note 10 and timing diagrams)
MIN

MAX

t Dd7

Data delay time from DCLKX

PARAMETER

TEST CONDITIONS
CL = 0 to 100 pF

100

UNIT
ns

t Dd8

CL = 0 to 100 pF

t od9

Data delay from timeslot enable to PCM OUT
Data delay from time slot disable to PCM OUT

CL = 0 to 100 pF

ns
ns

t Ddl0

Data delay time from FSX

tdITSDX} = BO ns

140

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variabh,-data-rate mode (see timing diagrams)
MIN

PARAMETER

MAX

UNIT

IdITSDRI

Timeslot delay time from DCLKR Isea Note II}

140

tdlOCLKRI - 140 ,

tdlFSR)

Frame sync delay time

100

IeICLK) - 100

tsulPCM INI

Setup time before Bit 7 falling edge

thlPCM INI

Hold time alter Bit 8 falling edge

tcIDCLKR}
tISER}

Data clock frequency

4B8

Tlmeslot end r!'celve time

ns
ns
15620

ns
ns

64-kilobit operation timing requirements over recommended ranges of supply voltage and operating
free-air temperature, variable-data-rate mode
PARAMETER

TEST CONDITIONS

Transmit frame sync,minimulll down

tFSLR

Receive frame sync minimum down time

tDCLK

Pulse duration, data clock

NOTES:

FSX = TTL high for

tim~

tFSLX

remainder of frame
FSR - TTL high for
remainder of frame

MIN

MAX

UNIT
ns

488

1952
10

I's

9. tFSLX minimum requirement overrides the IdITSDX} maximum requirement for 64-kHz operation.
10. Timing parameters tpd8 and tpd9 are referenced to a high-impedance state.
11. tFSLR minimum requirement overrides the IdITSDR}-maximum requirement for 64-kHz operation.

TEXAS

INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS. TEXAS 75265

F-19

TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17

COMBINED SINGLE·CHIP PCM CO DEC AND FILTER
ClK, ClKR, and ClKX Selection Requirements for DSP Based Applications
1) It should be .noted that the ClKX, ClKR, ClK must be selected as foll9wS:
ClKSEl PIN

ClK. ClKR. ClKX
IBETWEEN 1.0 MHz to 3.0 MHz)

-5 vt

= (256) x IFrame Sync Frequency)

= (193) x (Frame Sync Frequency)

+5 V

= (19;!) x IFrame Sync Frequency)

DEVICE TYPE
TCM129C13/14/16/17
TCM29C13/14/16/17
TCM129C13/14
TCM29C13/14
TCM129C13/14
TCM29C13/14

E.G.: For Frame Sync Frequency = 9.6 kHz
CLKSEl PIN

ClK. ClKR. CLKX
IBETWEEN 1.0 MHz to 3.0 MHz)

-5 v t

=2.4576 MHz

= 1.8528 MHz

+5 V

= 1.8432 MHz

DEVICE TYPE
TCM129C13/14/16/17
TCM29C13/14/16/17
TCM129C13/14
TCM29C13/14
TCM129C13/14
TCM29C13/14

tCLKSEL is internally set to -5 V for TCM129C16/17 and TCM29C16/17.

2) Corner frequency at 8 kHz Frame Sync Frequency = 3kHz
Therefore. the corner frequency = (3/8) x (Frame Sync Frequency). (For nonstandard frame sync.)

F-20

TEXAS .."

INSTRUMENlS
POST OFFICE BOX 855012 • DALLAS. Tr;XAS 75265

TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17

COMBINED SINGLE·CHIP PCM CODEC AND FILTER
+0.15 dB
300 Hz

+0.03 dB
3300 Hz

'"I

..,

Ww
0-,
Ze(

-0.15 dB
300 Hz
-1

::&1
X
w

TYPICAL FILTER
-1

...~
le(

-10

"g
t:I

TYPICAL FILTER
TRANSFER FUNCTION

-50

FREQUENCY -,Hz

FIGURE 1. TRANSFER CHARACTERISTICS OF THE TRANSMIT FILTER

·TEXAS .."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

F-21

TCM129C13, TCM129C14,TCM129Cf6,' TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER

+1
+0.125 dB
200' Hz

+0.15dB
3000 Hz

EXPANDED
SCALE

+0.15db
+0.03 dB
300 Hz ~ 3300 Hz

o~===~=~~=~;;:;:;;~~~~~::=~~~ -0.10 dB
200 Hz

-0.15 dB
300 Hz

III

'i'

-1

...

:I:

~
Z

"e
w

~...

-10

-20

-30

....~~~-30

-40

II:
Z

FREQUENCY - Hz
'\IOTE: This is a typic,al transfer function of the receive filter component.

FIGURE 2. TRANSFER CHARACTERISTIC OF THE RECEIVE FILTER

F·22

TEXAS ."

INSTRUMENlS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75285

TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17

COMBINED SINGLE·CHIP PCM CO DEC AND FILTER

ClKX
FSX INPUT

IdfFSXI..! 14I I

fNONSIGNALING
FRAMESI

2 I

--tt ...-ldIFSXI

1f---tl"-lcfClKI
~~
I
--'I i
~~----~I--------------------------------------------

If.ldfFSXI

FSX INPUT - '
ISIGNAllNG

ILldfFSXI
r

\.!

~~----------------------------------------------

FRAMESI

FRAME SYNCHRONIZATION TIMING

ClKX

PCMOUT

I
Ipd4-t1

I
~.1pd5

If-

IIIIV~--

----:IL-

'~--------------------------------~------~------i{.
I .. fSIGX l-tt
...a
... Ih ISIGXI

TSXOUTPUT

SIGX INPUT ------------------O-O-N-.,.-C-A-R-E----------------""""'tJ......
V-A-Ll-O""""'X'00N.,. CARE
OUTPUT TIMING

FIGURE 3. TRANSMIT TIMING (FIXED·DATA·RATE)
TIMESlOT1~

ClKR.

I
'dfFSRI-.iI......
FSR
I
fNONSIGNALING
FRAMESI
I

-.1 .....1

--Iin---'\.!

FSR
fSIGNALING
FRAMES)

'"~

if-ldIFSR)

I
dfFSRI I
____ I

-tlI4-I,

If-tC.

k"'f~lKI
I

10.
t( "fClKI
__________________________________________
__

-tI ....ldIFSR)

\~.------------------FRAME SYNCHRONIZATION TIMING

ClKR

PCM IN

SIGROUTPUT ___________________________V_A_l_IO__________________________~~
INPUT TIMING

FIGURE 4. RECEIVE TIMING (FIXED·DATA-RATE)
NOTE: Inputs and driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low
level is indicated.
tBit 1 = MSB = SIGN BIT and is clocked in first on the PCM-IN pin or clocked out first on the PCM-OUT pin. BIT 8 = LSB = LEAST
SIGNIFICANT BIT and is clocked in last on the PCM-IN pin or is clocked out last on the PCM-OUT pin.

TEXAS ."

INSTRUMENlS
POST OFFICE BOX 855012 • DALLAS. TexAS 75285

F-23

TCM129C13. TCM129C14. TCM129C16. TCM129C17
TCM29C13. TCM29C14. TCM29C16. TCM29C17
COMBINED SINGLE·CHIP PCM CO DEC AND FILTER

FIGURE 5. TRANSMIT TIMING (VARIABLE·DATA·RATEI

FSR
,

-I"

~td(TSDR)
~

., : 1---1
DCLKR
I , T' -r

1""""'1..

,2,

'---oJ

\..!....I

I
~

-.I ,..
td(FSR)
I

CLKR

r-:\ :
,4
i

I
J;......J

,
I
,I
I\......J

,...-,

r::-\

I 6 I

\......J

,-,
I

\...J

r-"\' ,-,'u',,.....,U'n "
,-,"

r-"\

\...J,

tsu(PSM

t-',

IN)~ ~

\...J

I roo-

,.....,

IS, I I
~

\.....J

'---oJ

,.......,

\...J

I.- t(SER)

\...JI

3 •

\....J

\...J

...i k- th(PCM IN)

~DON"T'''A'-·"'\.!77~r~.P7.J'~~.'"''~.w;,..~r-'.~
PCM IN

~CARE%t,_,r~~:".-J~\........I"&\..._f((/4'\.....J~t_/(I'd;\.....J~\.....J~
~T

BIT
3

BIT
5

BIT
7

BIT

NOTE: All timing parameters referenced to VIH and VIL except tpd8 and tpd9. which reference a high-impedance state.

FIGURE 6. RECEIVE TIMING (VARIABLE-DATA-RATEI
NOTE: All timing parameters. referenced to VIH and VIL except tpd8 and tpd9. which reference a high-impedance state.
tBit 1 ~ MS8 ~ SIGN BIT and is clocked in first on the PCM-IN pin or clocked out first on the PCM-OUT pin. BIT 8 ~ LSB ~ LEAST
SIGNIFICANT BIT and is clocked in last on the PCM-IN pin or is clocked out last on the PCM-OUT pin.

TEXAS

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17

COMBINED SINGLE-CHIP PCM CODEC AND FILTER
GENERAL OPERATION

system reliability features
The TCM129C13, TCM129C14, TCM129C16, TCM129C17, TCM29C13, TCM29C14, TCM29C16, and
TCM29C17 are powered up in four steps:
VCC and VBB supply voltages are applied.
All clocks are connected.
TTL high is applied to PDN.
FSX and/or FSR synchronization pulses are applied.
On the transmit channel, digital outputs PCM OUT and TSX are held in high-impedance state for
approximately four frames (500 ,.s) after power up or application of VBB or VCC. After this delay, PCM
OUT, TSX, and signaling are functional and will occur in the proper timeslot. The analog circuits on the
transmit side require approximately 60 ms to reach their equilibrium value due to the autozero circuit settling
time. Thus valid digital information, such as for on/off hook detection, is available almost immediately,
while analog information is available after some delay.
On the receive channel, the digital output SIGR is also held low for a maximum of four frames after power
up or application of VBB or VCC. SIGR will remain low until it is updated by a signalling frame.
To further enhance system reliability, PCM OUT and TSX will be placed in a high-impedance state
approximately 20 ,.s after an interruption of CLKX. SIGR will be held low approximately 20 ,.s after an
interruption of CLKR. These interruptions could possible occur with some kind of fault condition.

power-down and standby operations
To minimize power consumption, a power-down mode and three standby modes are provided.
For power down, an external low signal is applied to the PDN pin. It is not sufficient to remove the high
voltage to PDN. In the absence of a signal, the PDN pin floats to high and the device remains active. In
the power-down mode, the average power consumption is reduced to an average of 5 mW.
The standby modes give the user the option of putting the entire device on standby, putting only the transmit
channel on standby, or putting only the receive channel on standby. To place the entire device on standby,
both FSX and FSR are held at low. For transmit-only operation, FSX is high and FSR is held low. For receiveonly operation, FSR is high and FSX is held low. See Table 1 for power down and standby. procedures.
TABLE 1. POWER DOWN AND STANDBY PROCEDURES
DEVICE
STATUS

PROCEDURE

TYPICAL POWER

Power down

PDN low

3mW

Entire device on standby

FSX and FSR
are low

3mW

Only transmit on standby

FSX is low

Only receive on standby

FSR is high
FSR is low
FSX is high

DIGITAL OUTPUT STATUS

CONSUMPTION

40mW
30mW

~ and PCM OUT are in a high-impedance state;

SIGR goes to low within lOpS.
PCM OUT are in a high-impedance state;

TID< and

SIGR goes to low within 300 ms.
PCM OUT are placed in a high-impedance

TID< and

state within 300 ms.
SIGR is placed in a high-impedance state
within 300 ms.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

F-25

TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM.29C14, TCM29C16, TCM29C17

COMBINED SINGLE-CHIP PCM CODEC AND FILTER
fixed-data-rate timing (see Figure 7)
Fixed-data-rate timing is selected by connecting DCLKR to VBB. It uses master clocks CLKX and CLKR,
frame synchronizer clocks FSX. and FSR, and output TSX. FSX and FSR are 8-kHz inputs that set the
sampling· frequency and distinguish between signaling and nonsignaling frames by their pulse durations.
A frame synchronizati·on pulse one master clock period long designlltes a nonsignaling frame, while a doublelength sync pulse enables the signaling function (TCM 129C 14 and TCM29C 14 only). Data is transmitted
on the PCU OUT pin on the first eight positive transitions of CLKX following the rising edge of FSX. Data
is received on the PCM IN pin on the first eight falling edges of CLKR following FSX. A digital-to-analog
(D/A) conversion is performed on the received digital word and the resulting analog sample is held on an
internal sample-and-hold capacitor until transferred to the receive filter.
The clock selection pin (CLKSEL) is used to select the frequency of CLKX and CLKR (TCM129C13,
TCM129C14, TCM29C13, and TCM29C14 only). The TCM129C13, TCM129C14, TCM29C13, and
TCM29C14 fixed-data"rate mode can operate with frequencies of 1.536 MHz, 1.544 MHz, or 2.048 MHz.
The TCM 129C16, TCM 129C17, TCM29C16, and TCM29C17 fixed data rate mode operates at 2.048 MHz
only.
192/193/256
OTHER

~TSIX
"I j+--TIMESLOTS~
CLKX~~
12345678
1921193/256
FSX

J'"'l

I'.

TS1X----.I

12345
XMIT SIGNAL FRAME

II--r---,'-----------

8788 SIGX
PCMOUT -~-- - - - - - - - - - - - - ::x:::::>DCCx:X::x~5<=:::::=
8, 82838485
87 88 - - - - - - - - - - - - - 8, 82838485 86

TSX~~_________~~Ir--------fr--~
SIGX - - . - - - - - ' - . - -

I DON.~CARE
------f~--- ------- --1.f-X - - - =::::_::.::.::x:..6..::L:>C=~

- - - - - - - - - - - - - --11.... - - DoN".T" ~RE-- ,
j+------TSIR

-if-

192/193/256

- --

VALID

OTHER
192/193/256
j----TIMESLOTS ----.j
\ 114-·- - -

CLKR~~
123456789
..
FSR.II

__~__~~----

1
45
REC. SIGNAL FRAME

_ _ _ _ _ _ _ _ _ __

~"==-----------:---~--8,8283.84 85 as 87 88
- - - - - - - - - - - - - - - ~;--SIGR

..
PREVIOUS VALUE

FIGURE 7. SIGNALING TIMING (FIXED-DATA-RATE ONLY)

F-26

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265

{
NEW VALUE

TCM129C13. TCM129C14. TCM129C16. TCM129C17
TCM29C13. TCM29C14. TCM29C16. TCM29C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
variable, data rate timing
Variable-data-rate timing is selected by connecting DClKR to the bit clock for the receive PCM highway
rather than to VBB. It uses master clocks ClKX and ClKR, bit clocks DClKX and DClKR, and frame
synchronization clocks FSX and FSR.
Variable-data-rate timing allows for a flexible data frequency. The frequency of the bit clocks can be varied
from 64 kHz to 2.048 MHz. The bit clocks can be asynchronous in the TCM129C14 and TCM29C14,
but must be synchronous in the TCM129C13, TCM129C16, TCM129C17, TCM2~C13, TCM29C16, and
TCM29C 17. Master clocks in types TCM 129C 13, TCM 129C 14, TCM29C 13, and TCM29C 14 are restricted
to frequencies of operation of 1.536 MHz, 1.544 MHz, or 2.048 MHz as in the fixed-data-rate timing mode.
The master clock for the TCM129C16, TCM129C17, TCM29C16, and TCM29C17 is restricted to
2.048 MHz.
While FSX/TSXE input is high, PCM data is transmitted from PCM OUT onto the highway on the next
eight consecutive positive transitions of DClKX. Similarly, while the FSR/TSRE input is high, the PCM
word is received from the highway by PCM IN on the next eight consecutive negative transitions of DClKR.
The transmitted PCM word will be repeated in all remaining tim.eslots in the 125 p's frame as long as DClKX
is pulsed and FSX is held high. This feature, which allows the PCM word to be transmitted to the PCM
highway more than once per frame, if desired, is available only with variable-data-rate timing. Signaling
is allowed only in the fixed-data-rate mode because the variable-data-rate mode provides no means with
which to specify a signaling frame.

signaling
The TCM29C14 (only) provides 8th-bit signaling in the fixed-data-rate timing mode. Transmit and receive
signaling frames are independent of each other and are selected by a double-width frame sync pulse on
the appropriate channel. During a transmit signaling frame, the signal present on SIGX is substituted for
the least significant bit (lSB) of the encoded PCM word. In a receive signaling frame, the codec will decode
, the seven most significant bits in accordance with CCITT G. 733 recommendations, and output the logical
state of the lSB on the SIGR pin until it is updated in the next signaling frame. Timing relationships for
signaling operations are shown n Figure 9. The signaling path is used to transmit digital signaling information
such as ring control, rotary dial pulses, and off-hook and disconnect sUpervision. The voice path is used
to transmit prerecorded messages as well as the call progress tones; dial tone, ring-back tone, busy tone,
and re-order tone.

asynchronous operation
The TCM 129C 14 and TCM29C 14 can be operated with asynchronous clocks in either the fixed- or variabledata-rate modes. In order to avoid crosstalk problems associated with special interrupt circuits, the design
of the TCM129C13, TCM129C14, TCM29C13, and TCM29C14 includes separate digital-to-analog
converters and voltage references on the transmit and receive sides to allow completely independent
operation of the two channels.
.
In either timing mode, the master clock, data clock, and timeslot strobe must be synchronized at the
beginning of each frame. Specifically, in the variable-data-rate mode the rising edge of ClK~ must occur
within td(FSX) ns before the rise of FSX, while the leading Jdge of DClKX must occur within tTSDX ns
of the rise of FSX. ClKX and DClKX are synchronized once per frame but may be of different frequencies.
The receive channel operates in a similar manner and is completely independent of the transmit timing
(see variable data rate timing diagrams). This approach requires the provision of two separate master clocks
but avoids the use of a synchronizer, which can cause intermittp.nt data conversion errors.

TEXAS

-II

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

F-27

TCM129C13. TCM129C14. TCM129C16. TCM129C17
TCM29C13. TCM29C14. TCM29C16. TCM29C17

COMBINED SINGLE·CHIP PCM CODEC AND FILTER
analog loopback
A distinctive feature of the TCM129C14 and TCM29C14 is their analog loopback capability. With this
feature, the user can test the line circuit remotely by comparing the signals sent into the receive channel
(PCM IN) with those generated on the transmit channel (PCM OUT). The test is accomplished by sending
a control signal that internally connects the analog input and output ports. WhenANLG LOOP is TTL high,
the receive output (PWRO + ) is internally connected to ANLG IN +, GSR is internally connected to PWRO -,
and ANLG IN - is internally connected to GSX (see Figure 8).

,---------

..:... - ANLGI
Loopt

I
I
I pCM
TRANSMIT ....;..!~_~_
VOICE

AID

OUT
DIGITIZED

PCM
LOOPBACK
RESPONSE

I
IN
IPCM
I DIGITIZED
PCM
I - TEST TONE
I
I
____ .J

PWRO+~~--~------------__~~

PWRO- ; - - - -....- - - - - - - -. .----.::100,..

I
I
IL _ _ _ _ _

FIGURE 8. TCM129C14 AND TCM29C14 ANALOG LOOPBACK CONFIGURATION
Due to the difference in the transmit and receive transmission levels, a 0 dBmO code into PCM IN will
emerge from PCM OUT as a 3-dBmO code, an implicit gain of 3 dB. Because of this, the maximum signal
that can be tested by Bnalog loopback is 0 dBmO.

precision voltage references
No external components are required with the devices to provide the voltage references. Voltage references
that determine the gain and dynamic range characteristics of the device are generated internally. A difference
in subsurface charge density between two suitably implanted MOS devices is used to derive a temperatureand bias-stable reference voltage. These references are calibrated during the manufacturing
process.Separate references are supplied to the transmit and receive sections, and each is calibrated
independently. ,Each reference value is then further trimmed in the gain setting operational amplifiers to
a final precision value. Manufacturing tolerances can be achieved of typically ±O.04 dB in absolute gain
for each half channel, providing the user a significant margin to compensate for error .in other board
components.

F-28

TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

lCM129C13, lCM129C14, lCM129C16, lCM129C17
lCM29C13, lCM29C14, lCM29C16, lCM29C17
COMBINED SINGLE·CHIP PCM CO DEC AND FILTER
conversion laws
The TCM129C13. TCM129C14. TCM29C13. and TCM29C14 provide pin-selectable ,,-law operation as
specified by CCITT G. 711 recommendation. A-law operation is selected when the ASEL pin is connected
to VBB. Signaling is not allowed during A-law operation. The TCM129C16 and TCM29C16 are ,,-law only.
The TCM129C17 and TCM29C17 are A-law only.
The wlaw operation is effectively selected by not selecting A-law operation. If the ASEL pin is connected
to vce or GNO. the device is in Wlaw operation. If Wlaw operation is selected. SIGX is a TTL-level input
that can be used in the fixed data rate timing mode to modify the LSB of the PCM output is signaling frames ..
transmit operation
transmit filter
The input section provides gain adjustment in the passband by means of an on-chip uncommitted operational
amplifier. the,load impedance to ground (ANLG GNOI at the amplifier output (GSXI must be greater than
10 kG in parallel with less than 50 pF. The input signal on the ANLG IN + pin can be either ac or dc coupled.
The input operational amplifier can also be used in the invening mode or differential amplifier mode.
A low-pass antialiasing section is included on the device. This section provides 35-dB attenuation at the
sampling frequency. No external components are required to provide the necessary antialiasing function
for the switched capacitor section of the transmit filter.
The passband section provides flatness and stopband attenuation that fulfills the AT&T 03/04 channel
bank transmission specification and CCITT recommendation G.712. The device specifications meet or
exceed digital class 5 central office switching systems requirements.
A high-pass section configuration was chosen to reject low-frequency noise from 50.. and 6o..Hz power
lines, 17-Hz European electric railroads, ringing frequencies and their harmonics, and other low-frequency
noise. Even with the high rejection at these frequencies, the sharpness of the band edge gives low
attenuation at 200 Hz. This feature allows the use of low-cost transformer hybrids without external
. components.
encoding
The encoder internally samples the output of the transmit filter and holds each sample on an intemal sample
and hold capacitor. The encoder performs an analog-to-digital conversion on a switched capacitor array.
Oigital data representing the sample is transmitted on the first eight data clocks bi~ of the next frame.
The autozero circuit corrects for de offset on the input signal to the encoder. The autozero circuit uses
the sign bit averaging technique. The sign bit from the encoder output is long-term averaged and subtracted
from the input to the encoder. All dc offset is removed from the encoder input waveform.
receive operation
decoding
The serial PCM word is received at the PCM IN pin on the first ight data clock bits of the frame. Oigital-toanalog conversion is .performed and the corresponding analog sample is held on an intemal sample-andhold capacitor. This sample is transferred to the receive filter.
receive filter
The receive section of the filter provides passband flatness and stopband rejection that fulfills both the
AT&T 03/04 specification and CCITT recommendation G. 712. The filter contains the required compensation
for the (sin xlix response of such decoders.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DAUAS. TEXAS 75265

F-29

lCM129C13, lCM129C14, lCM129C16, lCM129C17
lCM29C13, lCM29C14, lCM29C16, lCM29C17
COMBINED SINGLE·CHIP PCM CODEC AND FILlER
receive output power amplifiers
A balanced output amplifier is provided to allow maximu(Tl flexibility in output configuration. Either of the
two outputs can be used single-ended (i.e., referenced to ANLG GND) to drive single-ended loads.
Alternatively, the differential output will directly drive a bridged load. The output stage is capable of driving
loads as low as 300 oh~s single-ended to a level of 12 dBm or 600 ohms differentially to a level of 15 dBm.
The receive channel transmission level may be adjusted between specified limits by'manipulation of the
GSR input. GSR is internally connected to an analog gain-setting network. When GSR is connected to
PWRO -, the receive level is at maximum. When GSR is connected to PWRO +, the level is minimum.
The output transmission level is adjusted between 0 and - 12 dB as GSR is adjusted (with an adjustable
resistor) between PWRO + anI;! PWRO - .
Transmission levels are specified relative to the receive channel output under digital milliwatt conditions'
(i.e., when the digital input at PCM IN is the eight-code sequence specified in CCITT recommendation
G.711).

TYPICAL APPLICATION DATA
output gain set design considerations (see Figure 9)
PWRO + and PWRO - are low-impedance complementary outputs. The voltages at the nodes are:
VO+ at PWRO+
VO- at PWROVOD = Vo + - VO- (total differential response)
,

R1 and R2 are a gain-setting resistor network with the center tap connected to the GSR input,
A value greater than 10 kll and less than 100 kll for R1 + R2 is recommended because of the following:
The parallel combination of R1 + R2 and RL sets the total loading.
The total capacitance at the GSR input and the parallel combination of R1 and R2 define a time constant
that has to be minimized to avoid inaccuracies.
VA represents the maximum available digital milliwatt output response (VA = 3.06 V rms).
VOD = A.VA
+ (R1IR2)
4 + (R1IR2)

Where A

PWRO+

Voo

I
.I

~ GSR
R2

TCM129C13
TCM129C14
TCM129C16
TCM129C17
TCM29C13
TCM29C14
TCM29C16 PCM IN
TCM29C17

PWRO-

vo_

OIGITAL~ ILLIWATT
SEauEN CE PER
CCITT G.711

FIGURE 9. GAIN-SETTING CONFIGURATION

F-30

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TCM129C18, TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR DSP
03036, AUGUST 1987 - REVISED JUNE 1988

•

Reliable Silicon-Gate CMOS Technology

•

low Power Consumption
Operating Mode ... 80 mW
Power-Down Mode ... 5 mW
p-Law Coding

N DUAL·IN·LlNE PACKAGE
(TOPVIEWI

•

Excellent Power Supply Rejection Ratio Over
Frequency Range of 0 to 50 kHz

•

No Extemal Components Needed for
Sample. Hold. and Auto-Zero Functions

•

Precision Internal Voltage References

•

Single Chip Contains AID. D/A. and
Associated Filters
I

VBB
PWRO+
PWROPDN
DClKR
PCM IN
FSR/TSRE
DGTl GND

VCC
GSX
ANlG IN
ANlG GND
TSX/DClKX
PCM OUT
FSX/TSXE
ClK

FEATURE TABLE
16 Pins

,,·Law Coding
Variable Mode:
64 kHz to 2.048 MHz

Flxad Mode:
2.048 MHz (TCM12SC18. TCM2SC181.
1.536 MHz (TCM12SC1S. TCM2SC1S1
B·BIt Ruolutlon
12-BIt Dynamic Range

description
The TCM129C18. TCM129C19. TCM29C18. and TCM29C19 are low-cost single-chip pulse-codemodulated encoders and decoders (PCM codecs) and PCM line filters. These devices incorporate both the
AID and DIA functions; an anti-aliasing filter (AID). and a smoothing filter (D/A). These devices are ideal
for use with the TMS320 family members. particularly those featuring a serial port such as the TMS32020.
TMS32011. and TMS320C25.
Primary applications of

t~ese

devices include:

Digital Encryption Systems
Digital Voice-Band Data Storage Systems
Digital Signal Processing
These devices are designed to perform encoding of analog input signals (AID conversion) and decoding
of digital PCM signals (D/A conversion). They are useful for implementation in the analog interface of a
digital-signal processing system. Both devices also provide band-pass filtering of the analog signals prior
to encoding and smoothing after decoding.
The analog input is encoded into an 8-bit digital representation by use of the ,.-Iaw encoding scheme
(CCITT G. 711) .which equates to 12 bits of resolution for low amplitude signals. Similarly. the decoding
section converts 8-bit PCM data into an analog signal with 12 bits of dynamic range. The filter characteristics
(bandpass) for the encoder and decoder are determined by a single clock input (ClK). The filter roll-off
( - 3 dB) is derived by:
fco = k· fCLK/256 for the TCM129C18 and TCM29C18 or fco
TCM 129C 19 and TCM29C 19

= k.

fCLK/192 for the

where k has a value of 0.44 for the high-frequency roll-off point. and a value of 0.019 for the low-frequency
roll-off point.
PRODUCTIDI DATA d... mantsc.ntli. iltarmati••
currelt II ., p••IiCltio. dat.. Products •••Iorm to
apacifiClti••1 par til. term••, TI••• 1.IU.m....

=rll;"{::I':.7i =:~i:: :.l.=~~ not

TEXAS . "

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

F-31

TCM129C18, TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR DSP
description (continued)
The sampling rate of the ADC is determined by the Frame Sync Clock, FSX; the sampling rate of the DAC
is determined by the Frame Sync Clock, FSR. Once a conversion is initiated by FSX or FSR, data is clocked
in or out on the next consecutive eight Clock pulses in the fixed data rate mode. Likewise, data may also
be transferred on the next eight consecutive clock pulses of the data clocks, DCLKX and DCLKR, in the
variable data rate mode. In the variable data rate mode, DCLKX and DCLKR are independent, but rnust
be in the range from fCLK/32 to fCLK.
TheTCM 129C 18 and TCM 129C 19 are characterized for operation over the temperature range of - 40 DC
to 85 DC. The TCM29C 18 and TCM29C 19 are characterized for operation over the temperature range of
ODC to 70 DC.
'

functional block diagram
TRANSMIT
SECTION

AUTO
ZERO

SAMPLE

ANLGIN

SUCCESSIVE
APPROXI·
MATION

COMPARA·
TOR

PCMOUT
OUTPUT
REGISTER

TlX/DCLKX

GSX-I-~=~~
ANALOG

T~~!6~LI-_ _ _ _ _--......L_""'--4-FSXITSXE
LOGIC

ClK

RECEIVE
SECTION

PCMIN
PWRO+

DCLKR

PWRO-

vcc

F-32

Vaa DGTL ANLG
GND GND

FSRITSRE

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POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TCM129C18, TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR DSP

NAME
ANlG IN
ANlG GND
ClK

PIN
14
13
9

DClKR

DGTL GND
FSR/TSRE

8
7

FSXITSXE

GSX

PCM IN
PCM OUT

6
11

PDN

PWRO+

PWRO-

T§X/DCLKX

Vas
VCC

DESCRIPTIDN
Inverting analog input to uncommitted transmit operational amplifier
Analog ground raturn for all voice circuits. Not internally connected to digital ground.
Master clock and data clock for the fixed data rate mode. Master (filter) clock only for variable data-rate mode.
This clock is used for both the transmit and receive sections.
When this pin is connected to Vaa. the device operates in the fixed-data-rata mode. When DCLKR is not connected
to Vaa. tha device operatas in the variable-data-rate mode and DCLKR becomes the receive data clock. which
operates at frequencies from 64 kHz to 2.048 MHz.
Digital ground for all internal logic circuita. Not intsrnally connected to analog ground.
Frame sync clock input/time-slot enable for the receive channel. In the variable-data-rate-mode. this signal must
ramain high for the duration of the time-slot. The receive channel enters the standby state when FSR is TTL low
for 30 ms.
Frame synchronization clock input/time-slot enable for transmit channel. Operates independently of. but in an
analogous manner to FSRITSRE. The transmit channel enters the atandby state when FSX is low for 300 ms.
Output terminal of internal uncommitted operational amplifier. Internally, this is the voice Signal input to the transmit
filter.
Receive PCM input. PCM data is clocked in on this pin on eight consecutive negative transitions of the receive
data clock. which is ClKR in fixed-data-rate timing and DClKR in variable-data-rate timing.
Transmit PCM output. PCM data is clocked out of this output on eight consecutive positive transitions of the
transmit data clock. which is ClKX in fixed-data-rate timing and DCLKX in variable-data-rate timing.
Power-Down Select. On the TCM129C18 and the TCM29C18. the device is inactive with a TTL low-level input
and active with a TTL high-level input to the pin. On the TCM129C19 and the TCM29C19. this pin must be
connected to a TTL high level.
Noninverting output of power amplifier can drive transformer hybrids or high-impedance loeds diractly in either
a differential or a single-ended configuration.
Inverting output of power amplifier. functionally identical to PWRO +
Transmit channel time slot strobe (output) or data clock (input). In the fixed-data-rate mode. this is an open-d,ain
output to be used a8 an enable signal for a three-state-buffer. In the variable-data-rate mode. DCLKX becomes
the transmit data clock. which operates at TTL levels from 64 kHz to 2.048 MHz.
Negative supply voltage. - 6 V ± 6%.
Positive supply voltage. 6 V ± 6%.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage. Vee (see Note 1) ....................................... -0.3 to 15 V
Output voltage. VO .................................................. -0.3 to 15 V
Input voltage. digital inputs. VI ......................................... - 0.3 to 15 V
Digital ground voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 to 15 V
Operating free-air temperature range .................... . . . . . . . . . . . . . .. - 10 °e to 80 0 e
Storage temperature range ......................................... - 65 °e to 150 DC
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds ...................... 260 D e
NOTE 1: Voltage values for maximum ratings are with raspect to Vaa.

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F-33

TCM129C18. TCM129C19. TCM29C18. TCM29C19
ANALOG INTERFACE FOR OSP
recommended operating conditions (see Note 2)
MIN

NOM

MAX

UNIT

VCC

Supply voltage Isee Note 3)

4.75

5.25

VBB

Supply voltage

4.75

-5 -5.25

DGTL GND voltage with respect to ANLG GND

VIH

High-level input voltage, all inputs except ANLG IN

VIL

Low-level input. voltage, all inputs except ANLG IN

0.8

VIPP

Peak-ta-peak analog input voltage

4.2

Load resistance

Load capacitance

Operating free-air temperature

2.2

GSX

PWRO + and/or PWRO-

k!l
!l

300

GSX

PWRO + and/or PWRO-

100

TCM129C18 or TCM129C19
TCM29C1B or TCM29C19

-40

pF
DC

NOTES: 2. To avoid any possible damage and reliability problems to these CMOS devices when applying power, the following sequence
should be followed:
II} Connect ground
12} Connect the most negative voltage
(3), Connect the most positive voltage
14} Connect the input signals.
When powering down the device, follow the above steps in reverse order. If the above procedure cannot be followed, connect
a diode between VBB and DGTL GND, cathode to DGTL GND, anode to VBB'
3. Voltages at analog inputs and outputs, VCC and VBB terminals are with respect to the ANLG GND terminal. All other voltages
are referenced to the DGTL GND terminal unless otherwise noted.
'
4. Analog input signals that exceed 4.2 V peak-ta-peak may contribute to clipping and preclude correct AID conversion. The
digital code representing values higher than 4.200 V is 10000000. For values more negative than 4.200 V, the code is 0000000.

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
supply current. fdclk - 2,048 MHz. outputs not loaded
PARAMETER
Supply current
ICC

from VCC
Supply current

IBB

from VaB

TCM129CXX

TEST CONDITIONS

MIN

operating

TCM29CXX

MAX

MIN

MAX

standby

FSX or FSR at VIL after 300 nis

1.5

1.2

power down

PDN at VIL after 10 P.s

1.2

-14

-10

standby

FSX or FSR at VIL after 300 ms

-1.5

-1.2

power down

PDN at VIL after 10 p.s

-1.2

-1

operating

UNIT

rnA

digital interface
PARAMETER

IOH

= -9.6 mA
= -0.1 rnA
= 3.2 mA

VOH
VOL

Low-level output voltage, TSX

IOL

IIH

High~level

VI - 2.2 V to VCC

IOH
input current, any digital input

= b to

MIN

TYpt

MAX

2.4

UNIT
V

3.5
0.5

p.A

IlL

Low-level input current, any digital input

p.A

Input capacitance

Output capacitance

t All typical values are at VBB

F-34

TEST CONDITIONS

High-level output voltage, PCM OUT

-5 V, VCC

5 V, and TA

0.8 V

25 DC.

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TCM129C18, TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR DSP
transmit side (AID) characteristics
PARAMETER

TEST CONDITIONS

Input offset current at ANLG IN

Input offset voltage at ANLG IN

Input bias current

=
=
=

MIN

-2.17 V to 2.17 V
-2.17 Vto 2.17 V
-2.17 V to 2.17 V

Unity-gain bandwidth at GSX

Isee Notes 5, 6, and 71

- 40 dBmO to - 50 dBmO,

REF level

Transmit gain tolerance

Vi = 1.06 V,
Ref max output level:

(single-endedl

±100

1
REF level -

Crosstalk attenuation, transmit-to-receive

±25

MHz

10
3 dBmO to -40 dBmO,

Supply voltage rejection ratio, VCC or VBB

UNIT

5000

Input resistance at ANLG IN

Noise

MAX

Open-loop voltage amplification at GSX

Gain tracking error with sinusoidal input

TVpt

= -

±2.5
0.95

200 Hz to 3 kHz

idle channel, Supply signal
PCM IN

±0.5

10 dBmO

1.02 kHz

to 30 kHz, (measured at PCM OUT)

ANLG IN

- 10 dBmO

200 mV pop

= 0 dBm, f = 1 kHz unity
= lowest decode level,

1.19

Vrms

-70

-20

gain,

measured at PWRO +

Signal-ta-distortion ratio, with
sinusoidal input (see Note 8).

Absolute delay time to PCM OUT

ANLG IN

ANLG IN ANLG IN,

to - 30 dBmO

-30 to -40 dBmO

= - 40 to

- 45 dBmO

Fixed data rate, FCLKX
input to ANLG IN

2.048 MHz,

245

1 kHz at 0 dB

I'S

receive side (D/A) characteristics (see Note 9)
TEST CONDITIONS

PARAMETER

Output offset voltage PWRO + and PWRO(single-ended I

MIN

Relative to ANLG GND

Output resistance at PWRO + and PWROGain tracking error with sinusoidal input

1
3 dBmO to -40 dBmO,

REF ievel ~ - 10 dBmO

(see Notes 5, 6, and 7)

- 40 dBmO to - 50 dBmO, REF level -

Receive gain tolerance

Noise

Supply voltage rejection ratio, VCC or VBB
(single-ended)
Crosstalk attenuation, receive-to-transmit

(single-ended)
Signal-ta-distortion ratio, sinusoidal input

(see Note 8)
Absolute delay time to PWRO +

TVpt

1.06 V,

Ref max output level:
f

UNIT

±200

2
±0.5

- 10 dBmO

1.02 kHz

MAX

±2.5
1.34

200 Hz to 3 kHz

!l
dB

1.69

Vrms

-70

to 30 kHz, idle channel,

Supply signal

200 mV poP,

-20

narrow band, frequency at PWRO +

= 0 d8,
= 1 kHz at PCM OUT
ANLG IN = 0 dBmO to ,.. 30 dBmO
ANLG IN = -30 dBmO to -40 dBmO
ANLG IN = -40 dBmO to -45 dBmO
Fixed data rate, FCLKX = 2.04B MHz
PCM IN

Frequency

33
27

22
190

I's

tAli typical values are atVBB = -5 V, VCC = 5 V, and TA = 25°C.
NOTES: 5. Unless otherwise noted, the analog input is a O-dBmO, 1020-Hz sine wave, where 0 dBmO is defined as the zero-reference
pOint of the channel under test. This corresponds to an analog signal input of 1.064 V rms, or an output of 1.503 V rms.
6. The input amplifier is set for unity gain. The digital input is a PCM bit stream generated by passing a O-dBmO. 1020-Hz sine
wave through an ideal encoder.
7. The TCM129C1B, TCM129C19, TCM29C18, and TCM29C19 are internally connected to set PWRO + and PWRO - to OdBm.
All output levels are (sin x)/x corrected.
8. CCITT G.712 - Method 2.
9. The receive side (D/A) characteristics are referenced to a 600-U termination.

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F-35

TCM129C18, TCM129C19, TCM29C18, TCM29~19
ANALOG INTERFACE FOR DSP
.
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode (see
timing diagrams)

tpdl
tpd2
tpd3
tpd4
tpd5

PARAMETER
From rising edge of transmit clo~k to bit 1 data valid at
PCM OUT (data enable time on time slot entry)
From rising edge of transmit clock bit n to bit n + 1
dlita valid at PCM OUT (data valid time)
From falling edge of tran~mit clock bit 8 to bit 8 Hi-Z at
PCM OUT (data float time on time slot exit)
From rising edge of transmit clock bit 1 to TSX active (low)
(time slot enable time)
From falling edge of transmit clock bit 8 to TSX inactive (high)
(timeslot disable time)

TEST CONOITIONS

MIN

MAX

UNIT

Cl = 0 to 100pF

145

Cl =,0 to 100 pF

145

Cl = 0

215

Cl = Oto lOOpF

145

Cl = 0

190

propagation delay times over recommended ranges of operating conditions. variable-data-rate mode
todS
t Dd7
tDdS
t Dd9

From
From
From
From

TEST CONDITIONS
Cl - Oto 100 pF
Cl = Oto 100 pF
Cl = 0 to 100 pF

PARAMETER
DClKX
time slot enable to PCM OUT
time slot disable to PCM OUT
FSX

td(TSDX) - 140 ns

MIN
0
0
0
0

MAX
100
50
80
140

UNIT
ns
ns
ns
ns

clock timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see timing diagrams)
tc(ClKI
t r• tf
tw(ClK)
tw(DClKI

PARAMETER
Clock period for ClK. (2.048-MHz systems)
Rise and fall times for ClK
Pulse duretion for ClK
Pulse duration for DClK (fDClK = 64 Hz to 2.048 MHz)

MIN
488
5
220
·220
~5

Clock duty cycle [tw(ClK)'tc(ClK)1 for ClK

TYpt

MAX
30

UNIT
ns
ns
ns
ns

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature. fixed-data-rate mode (see timing diagrams)
PARAMETER
Frame sync delay time

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature. fixed-data-ratemode (see timing diagrams)
PARAMETER
Frame sync delay time

F-36

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TCM129C18. TCM129C19. TCM29C18. TCM29C19
ANALOG INTERFACE FOR DSP
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature. variable-data-rate mode
MIN

MAX

UNIT

tdITSDX)

Delay time. timeslot from DCLKX Isee Note 10)

PARAMETER

140

twIDCLKX) - 140

tdIFSX)

Delay time, frame sync

100

twIDCLKX)

Pulse duration. DCLKX

488

tcICLKI- 100
15620

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature. variable-data-rate mode
MIN

MAX

UNIT

tdITSDR)

Delay time. timeslot from DCLKR (see Note 11)

PARAMETER

140

tdIFSR)

Delay time. frame sync T C_(CLK)
Setup time. before bit 7 falling edge

100

twIDCLKR) - 140
tc(CLK) - 100

tsulPCM IN)
thlPCM IN)
twIDCLKR)
tISER)

Hold time after bit 8 falling edge

Pulse duration. DCLKR

488

Time slot end receive time

ns
15620

ns
ns

64-kbit operation timing requirements over recommended ranges of supply voltage and operating free-air
temperature. variable-data-rate mode
PARAMETER
Transmit frame sync
tFSLX

minimum down time
Receive frame sync

tFSLR
twCLK

minimum down time

TEST CONDITIONS

MIN

FSX

= TTL high for

remainder of frame

488

FSR

= TTL high for remainder of frame

1952

Pulse duration. data clock

MAX

UNIT
ns
ns

I'S

NOTeS: 10. tFSLX min requirement overrides the td(TSCDX) max requirement for 64·kHz operation.
11. tFSLR min requirement overrides the tc(TSDR) max requirement for 64-kHz operation.

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F-37

TCM129C18. TCM129C19~ TCM29C18.TCM29C19
ANALOG INTERFACE FOR DSP

0.5 dB
300 Hz

0.5 dB

0.2 dB
3300 Hz

-0.5 dB
300 Hz

III

...
I

f&l
><
W

TYPICAL FILTER
TRANSFER FUNCTION'

-1

...:r:
...
c(

Z -10

-10

-10 dB
4000 Hz

~
>

...~

-20

TYPICAL FILTER
TRANSFER FUNCTION

II:

-51!

-50

100

FREQUENCY - Hz
NOTE: This is a typical transfer function of the receiver filter component.

FIGURE 1. TRANSFER CHARACTERISTICS OF THE TRANSMIT FILTER

F-38

e
Ww
eZc(
...

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TCM129C18, TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR DSP

+1
0.5 dB
200 Hz

0.5 dB
300 Hz

0
-0.8 dB
200 Hz
ID

.
:r

EXPANDED
SCALE

0.5 dB
0.2 dB
3000 Hz , ; ' 3300 Hz

-0.5 dB
300 Hz
-2 dB
3300 Hz

-1

...

-1

-3.5 dB
3400 Hz

1:1

>
~

..J

-10

-20

w
II:

1:1

-30

-40

100

1k
FREQUENCY - Hz

NOTE: This is a typical transfer function of the receiver filter component.

FIGURE 2. TRANSFER CHARACTERISTIC OF THE RECEIVE FILTER

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F-39

TCM129C1B. TCM129C19. TCM29C1B. TCM29C19
ANALOG INTERFACE FOR DSP

CLK
'dIFSXI....!1
FSXINPUT

I
14I

2
I

-'"
~I

l.-

'dIFSXI I

~______~I___________________~~_-_-_-_~
__~_-_'C_I_C_LK_I_________________
FRAME SYNCHRONIZATION TIMING

CLK

PCMOUT

I
tpd4-t1

~ ~tpd5

It-

TSXOUTPUT ~ ____________________________________________________
'~

y,....-.-

-J~

OUTPUT TIMING

FIGURE 3. TRANSMIT TIMING (FIXED-DATA-RATEI
TlMESLOT1~

CLK

I
'dIFSRI-+j
FSR INPUT

14-

-.I

1f-'00

description

zzz
(!l(!l

(!l(!l
The TLC32040, TLC32041, and TLC32042 are
...J ...J
complete analog-to-digital and digital-to-analog
zz
««
input/output systems, each on a single
monolithic CMOS chip. This device integrates a
NU - Nonusable; no external connection should be made to these
bandpass switched-capacitor antialiasing input
pins.
filter, a 14-bit-resolution A/D converter, four
microprocessor-compatible serial port modes, a
14-bit-resolution D/A converter, and a low-pass
switched-capacitor output-reconstruction filter. The device offers numerous combinations of Master Clock
input frequencies and conversion/sampling rates, which can be changed via digital processor control.

Typical applications for this IC include modems (7.2-,8" 9.6-, 14.4-, and 19.2-kHz sampling ratel, analog
interface for digital signal processors (DSPsl, speech recognition/storage systems, industrial process control,
biomedical instrumentation, acoustical signal processing, spectral analysis, data acquisition, and
instrumentation recorders. Four serial modes, which allow direct interface to the TMS32011, TMS320C17,
TMS32020, and TMS320C25 digital signal processors, are provided. Also, when, the transmit and receive
sections of the Analog Interface Circuit (AICI are operating synchronously, it will interface to two SN74299

Advanced LinCMOS'M is a trademark of Texas Instruments Incorporated.

,ie.

PRODUCTIOI DATA d.cum••11 canllin info,...
••" ••, •• of ,llIIi.llion doll. ProdlClJ ca.form 111
.....ifi••Ii••• per 1"lIrll. of T.... 1.11......11

=~~.{,::.1i ~::\:'i:; 1I=::~:~~ nD!

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F-45

TLC320401, TLC32040C, TLC320411, TLC32041C,
TLC320421, TLC32042C

ANALOG INTERFACE CIRCUITS
description (continued)
serial-to-parallel shift registers. These serial-to-parallel shift registers can then interface in parallel to the
TMS32010, TMS320C15, other digital signal processors, or external FIFO circuitry. Output data pulses'
are emitted to inform the processor that data transmission is complete or to allow the DSP to differentiate
between two transmitted bytes. A flexible control scheme is provided so that the functions of the IC can
be selected and adjusted coincidentally with signal processing via software control.
The antialiasing input filter comprises seventh-order and fourth-order CC-type (Chebyshev/elliptic
transitional) low-pass and high-pass filters, respectively, 'and a fourth-order equalizer. The input filter is
implemented in switched-capacitor technology and is preceded by a continuous time filter to eliminate
any possibility of aliasing caused by sampled data filtering. When no filtering is desired, the entire composite
filter can be switched out of the signal path. A selectable, auxiliary, differential analog input is provided
for applications where more than one analog input 'is required.
The A/D and D/A converters each have 14 bits of resolution. The A/D and D/A architectures en!lure no
missing codes and monotonic operation. An internal voltage reference is provided on the TLC32040 and
TLC32042 to ease the design task and to provide complete control over, the performance of the IC. The
internal voltage reference i's brought out to a pin and is available to the designer. Separate analog and
digital voltag!l supplies and grounds are provided to minimize noise and ensure a wide dynamic range.
Also, the analog circuit path contains only differential circuitry to keep noise to an absolute minimum.
The only exception is the DAC sample-and-hold, which utilizes pseudo-differential circuitry.
The output-reconstruction filter is a seventh-order CC-type (Chebyshev/elliptic transitional low-pass filter
with a fourth-order equalizer) and is implemented in switched-capacitor technology. This filter is followed
by a continuous-time filter to eliminate images of the digitally encoded signal.
The TLC32040l, TLC32041I, and TLC320421 are characterized for operation from -40°C to 85°C, and
the TLC32040C, TLC32041 C, and TLC32042C are characterized for operation from OOC to 70°C.

functional block diagram
BANDPASS FILTER
IN+
INAUX IN+

I,....",~~...

AUX IN-

R::EI~ s'::TI~ _ _ _ _

J
I

IL.L.-,;~~
_
LOW·PASS FILTER
OUT + +--I-----l
OUT -

+-1-----1
TRANSMIT SECTION

vee + Vee _ ANLG DTGL
GND GND

F-46

VDD
IDIG)

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TLC320401. TLC32040C. TLC320411. TLC32041C.
TLC320421. TLC32042C

ANALOG INTERFACE CIRCUITS
PRINCIPLES OF OPERATION
analog input
Two sets of analog inputs are provided. Normally, the IN + and IN - input set is used; however, the auxiliary
input set, AUX IN + and AUX IN - , can be used if a second input is required. Each input set can be operated
in either differential or single-ended modes, since sufficient common-mode range and rejection are provided.
The gain for the IN +, IN -, AUX IN +, and AUX IN - inputs can be programmed to be either 1, 2, or 4
(see Table 2). Either input circuit can be selected via software control. It is important to note that a wide
dynamic range is assured by the differential internal analog architecture and by the separate analog and
digital voltage supplies and grounds.

AID bandpass filter. AID bandpass filter clocking. and AID conversion timing
The AID bandpass filter can be selected or bypassed via software control. The frequency response of this
filter is presented in the following pages. This response results when the switched-capacitor filter clock
frequency is 288 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter
clock. When the filter clock frequency is not 288 kHz, the filter transfer function is frequency-scaled by
the ratio of the actual clock frequency to 288 kHz. The low-frequency roll-off of the high-pass section
is 300 Hz. However, the high-pass section low-frequency roll-off is less steep for the TLC32042 than for
the TLC32040 and TLC32041.
The Internal Timing Configuration and AIC OX Data Word Format sections of this data sheet indicate the
many options for attaining a 288-kHz bandpass switched-capacitor filter clock. These sections indicate
that the RX Counter A can be programmed to give a 288-kHz bandpass switched-capacitor filter clock,
for several Master Clock input frequencies.
The AID conversion rate is then attained by frequency-dividing the 288-kHz bandpass switched-capacitor
filter clock with the RX Counter B. Thus, unwanted aliasing is prevented because the AID conversion rate
is an integral submUltiple of the bandpass switched-capacitor filter sampling rate, and the two rates are
synchronously locked.

AID converter performance specifications
Fundamental performance specifications for the AID converter circuitry are presented in the AID converter
operating characteristics section of this data sheet. The realization of the AID converter circuitry with
switched-capacitor techniques provides an inherent sample-and-hold.

analog output
The analog output circuitry is an analog output power amplifier. Both noninverting and inverting amplifier
outputs are brought out of the IC. This amplifier can drive transformer hybrids or low-impedance loads
directly in either a differential or single-ended configuration.

D/A low-pass filter. DIA low-pass filter clocking. and D/A conversion timing
The frequency response of this filter is presented in the following pages. This response results when the
low-pass switched-capacitor filter clock frequency is 288 kHz. Like the AID filter, the transfer function
of this filter is frequency-scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided
on the output of the DIA low-pass filter to greatly attenuate any switched-capacitor clock feedthrough.
The DIA conversion rate is then attained by frequency-dividing the 288-kHz switched-capacitor filter clock
with TX Counter B. Thus, unwanted aliasing is prevented because the DIA conversion rate is an integral
submultiple of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously
locked.

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F-47

TLC320401. TLC32040C. TLC320411. TLC32041C.
TLC320421. TLC32042C
ANALOG INTERFACE CIRCUITS
PRINCIPLES OF OPERATION (continued)
asynchronous versus synchronous operation
If the'transmit section of the AIC (low-pass filter and DAC) and receive section (bandpass filter and ADC)
are operated asynchronously, the low-pass and band-pass filter clocks are independently generated from
the Master Clock signal. Also, the D/A and A/D conversion rates are independently determined. If the
transmit and receive sections are operated synchronously, the low-pass filter clock drives both low-pass
and bandpass filters. In synchronous operation, the A/D conversion timing is derived from, and is equal
to, the D/A conversion timing. (See description of the WORD/BYTE pin in the Pin Functional Description
Section.)
,

D/A converter performance specifications
Fundamental performance specifications for the D/A converter circuitry are presented in the D/A converter
operating characteristics section of the data sheet. The D/A converter has a sample-and-hold that is realized
with a switched-capacitor ladder.

system frequency response correction
Sin x/x correction circuitry is performed in digital signal processor software. The system frequency response
can be corrected via DSP software to ± O. 1 dB accuracy to a band-edge of 3000 Hz for all sampling rates.
This correction is accomplished with a first-order digital correction filter, which requires only seven TMS320
instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of
only 1.1 % and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the sin x/x Correction Section
for more details).

serial port
The serial port has four possible modes that are described in detail in the Functional Pin Description Section.
These modes are briefly described below and in the Functional Description for Pin 13, WORD/BYTE.
1. The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS32011 and TMS320C17.
\
2. The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS32020 and the TMS320C25.
3. The transmit and receive sections are operated synchronously, and the serial port interfaces directly
with the TMS32011 and TMS320C17.
'
4. The transmit and receive sections are operated synchronously, and the serial port interfaces directly
with the TMS32020, TMS320C25, or two SN74299 serial-to-parallel shift registers, which can
then interface in parallel to the TMS32010, TMS320C15, to any other digital signal processor,
or to, external FIFO circuitry.

testing
An addendum accompanying this data sheet fully describes the test capabilities of the IC, provided by
the design.

operation of TLC32040 or TLC32042 with intemal voltage reference
The internal reference of the TLC32040 and TLC32042 eliminates the need for an external voltage reference
and provides overall circuit cost reduction. Thus, the internal reference eases the design task and provides
complete control over the performance of the IC. The internal reference is brought out to a pin and is available
to the ~esigner. To keep the amount of noise on the reference signal to a minimum, an external capacitor
may be connected between REF and ANLG GND.

F-48

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TLC320401, TLC32040C, TLC320411, TLC32041C,
TLC320421, TLC32042C

ANALOG INTERFACE CIRCUITS
PRINCIPLES OF OPERATION (continued)
operation of TLC32040. TLC32041. or TLC32042 with external voltage reference
The REF pin may be driven from an external reference circuit if so desired. This external circuit must be
capable of supplying 250,.A and must be adequately protected from noise such as crosstalk from the
analog input.

reset
A reset function is provided to initiate serial communications between the Ale and OSP and to allow fast.
cost-effective testing during manufacturing. The reset function will initialize all Ale registers. including
the control register. After a negative-going pulse on the RESET pin, the Ale will be initialized. This
initialization allows normal serial port communications activity to occur between Ale and OSP (see Ale ox
Data Word Format section).

loopback
This feature allows the user to test the cir,cuit remotely. In loopback, the OUT + and OUT - pins are internally
connected to the IN + and IN - pins. Thus, the OAe bits (d15 to d2), which are transmitted to the OX
pin, can be compared with the AOe bits (d15 to d2). which are received from the DR pin. An ideal comparison
would be that the bits on the DR pin equal the bits on the OX pin. However, in practice there will be some
difference in these bits due to the AOe and OAe output offsets.
In loopback, if the IN + and IN - pins are enabled, the external signals on the IN + and IN - pins are ignored.
If the AUX IN + and AUX IN - pins are enabled, the external signals on these pins are added to the OUT +
and OUT - signals in loopback operation.
The loop back feature is implemented with digital signal processor control by transmitting the appropriate
serial port bit to the control register (see Ale Data Word Format section).

PIN
NAME

NO.

ANlG GND

17.18

AUX IN+

I/O

DESCRIPTION
'Analog ground return for all intarnal analog circuits. Not internally connected to DGTl GND.
Noninvarting auxiliary analog input stage. This input can be switched into the bandpass filter and AID converter

path via software control. If tha appropriate bit in the Control register is a 1. tha auxiliary inputs will replace
the IN + and IN - inputs. If the bit is a O. the IN + and IN:" inputs will be used (see the Ale DX Data Word
Format section).
AUX IN-

DGTl GND

9
5

Inverting auxiliary analog input (see the above AUX IN + pin description).
Digital ground for all internal logiC circuits. Not internally connected to ANOO GND.
This pin is used to transmit the ADC output bits from the AIC to the TMS320 serial port. This transmission
of bits from the AIC to the TMS320 serial port is synchronized with the SHIFT ClK signal.

This pin is used to recaiva the DAC input bits and timing and control information from the TMS320. This serial
transmission from the TMS320 sarial port to the AIC is synchronized with the SHIFT ClK signal.

mtili

(Sae the WORD/BY'fE pin description a"d the Serial Port Timing Diagram.) During the word-mode
timing. this signal is a low-9oinllPulse that occurs immediately aftar tha 16 bits of AID information have been
transmitted from the AIC to the TMS320 serial port. This signal can be used to intarrupt a microprocassor
upon completion of serial communications. Also, this signal can be used to strobe and enable external serialto-parallel shift registers. latches. or external FIFO RAM. and to facilitate parallel data bus communications
between the AIC and the serial-ta-parallal shift ragisters. During the byte-mode timing. this signal goas low
after the first byte has been transmitted from the AIC to tha TMS320 serial port and is kept low until the
second byte has been transmitted. The TMS32011 or TMS32OC17 can use this low-going signal to differentiata
between the two bytes as to which is first and which is second.

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TLC320401, TLC32040C, TLC320411, TLC32041 C,
TLC320421, TLC32042C
ANALOG INTERFACE CIRCUITS
PIN
NAME
EODX

NO.
11

1/0

DESCRIPTION

ISee the WORD/BV'fE pin description and the Serial Port Timing Diagram.) DuriAg the word-mode
timing, this signal is a low-going pulse that occurs immediately after the 16 bits of DIA converter and control
or register information have been transmitted frOm the TMS320 serial port to the AIC. This signal can be used
to interrupt a microprocessor upon the completion of serial communications. Also, this signal can" be used

to strobe and enable external serial-to-parallel shift registers, latches, or an external FIFO RAM, and to facilitate
parallel data-bus communications between the AIC and the serial-to-parallel shift registers. During the bytemode timing, this signal goes low after the first byte has been transmitted from the TMS320 serial port to
the AIC and is kept low until the second byte has been transmitted. The TMS32011 or TMS320C17 can use
this low-going signal to differentiate between the two bytes as to which is first and which is second.

In the serial transmission modes, which are described in the WORD/BV'fE pin description; the FSR pin is held
low during bit transmission. When the
pin goes low, the TMS320 serial port will begin receiving bits from

the AIC via the DR pin of the AIC. The most significant DR bit will be present on the DR pin before
low. ISee Serial Port Timing and Internal Timing Configuration Diagrams.)
14

goes,

When this pin goes low, the TMS320 serial port will begin transmitting bits to the AIC via the
.oX pin of the AIC. In all serial transmission modes, which are described in the WORD/B'i"FE pin description,

rnx

the
pin is held low during bit transmission Isee Serial Port Timing and Internal Timing Configuration
Diagrams).
IN+
INMSTR ClK

26
25

I
I
I

Noninverting input to analog input amplifier stage
Inverting input to analog input amplifier stage
The Master Clock signal is used to. derive all the key logic signals of the AIC, such as the Shift Clock, the
switched·capacitor filter clocks, and the AID and DIA timing Signals. The Internal Timing Configuration diagram
shows how these key signals are derived. The frequencies of these key signals are synchronous submultiples
of the Master Clock frequency to eliminate unwanted aliasing when the sampled analog signals are transferred

OUT+

OUT-

RESET

o
o

between the switched-capacitor filters and the AID and 01 A converters Isee the Internal Timing Configuration).
Noninverting output of analog output power amplifier. Can drive transformer hybrids or high-impedance loads
directly in either a differential or a single-ended configuration.
Inverting output of analog output power amplifier. Functionally identical with and complementary to OUT + .

I/O For the TlC32040 and TlC32042, the internal voltage reference is brought out on this pin. For the TlC32040,
TLC32041, and TlC32042, an external voltage reference can be applied to this pin.
I

A reset function is provided to initialize the TA, TA', TB, RA, RA', RB, and control registers. This
reset function initiates serial communications between the Ale ~nd bsp. The reset function will initialize all
AIC registers including the control register. After a negative-going pulse on the l\'ESrr
pin, the AIC registers will' be initialized to provide an 8-kHz data conversion rate for a 5.184-MHz master clock

input signal. The conversion rate adjust registers, TA' and RA', will be reset to 1. The CONTROL register bits
will be reset as follows Isee AIC OX Data Word Format section).
d7

I, d6

I, d5

l,d4

= 0,

This initialization allows normal serial-port communication to occur between Ale and DSP.

F-50

SHIFT ClK

VDD
VCC+
VCC-

7
20
19

The Shift Clock signal is obtained by dividing the Master Clock signal frequency by four. This Signal is used
to clock the serial data transfers of the AIC, described in the WORD/BYTE pin description
beloW {see the Serial Port Timing and Internal Timing Configuration diagrami.
Digital supply voltage, 5 V ± 5%
Positive analog supply voltage, 5 V ± 5%
Negative analog supply voltage - 5 V ± 5 %

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TLC320401, TLC32040C, TLC320411, TLC32041C,
TLC320421, TLC32042C

ANALOG INTERFACE CIRCUITS
PIN
NAME

NO.

WORD/B'i"rr 13

1/0

DESCRIPTION

This pin. in conjunction with a bit in the CONTROL register, is used to establish one of four serial
modes. These four serial modes are described below.

Ale transmit and receive sections are operated asynchronously.
The following description applies when the AIC is configured to have asynchronous transmit and receive sections.
If the appropriate data bit in the Control register is a 0 (see the AIC OX Data Word Formatl, the transmit and
receive sections will be asynchronous.

Serial port directly interfaces with the serial port of the TMS320 11 or TMS320C 17 and communicates
in two a-bit bytes. The operation sequence is as follows (see Serial Port Timing diagrams).

rnx m

1.
2.
3.
4.

The
or
pin is brought low.
One 8-bit byte is transmitted or one 8-bit byte is received.
The E!5l5X or rni5Ii pin is brought low.
The FSX or ~ pin emits a positive frame-sync pulse that is
four Shift Clock cycles wide.
5. One 8-bit byte is transmitted or one 8-bit byte is received.
6. The eoox or eOOR pin is brought high.
7. The FSX or ~ pin is brought high.
Serial port directly interfaces with the serial port of the TMS32020, TMS320C25, or TMS320C30'
and communicates in one l6-bit word. The operation sequence is as follows (see Serial Port Timing

diagramsl:
or ~ pin is brought low.
1. The
2. One 16-bit word is transmitted or one l6-bit word is received.
3. The FSX or ~ pin is brought high.
4. The ~ or rn!rn pin emits a low-going pulse.

rnx

Ale transmit and receive sections are operated synchronously.
If the appropriate data bit in the Control register is a 1, the transmit and receive sections will be configured
to be synchronous. In this case, the bandpass switched-capacitor fiiter and the AID conversion timing will

be derived from the TX Counter A, TX Counter 8, and TA, TA', and T8 registers, rather than the RX Counter
A, RX Counter 8, and RA, RA', and R8 registers. In this case, the Ale FSX and ~ timing will be identical
during primary data communication; however, Fm=i will not be asserted during secondary data communication
since there is no new AID conversion result. The synchronous operation sequences are as follows (see Serial

Port Timing diagrams).
L
Serial port directly interfaces with the serial port of the TMS320 11 or TMS320C 17 and communicates
in two 8-bit bytes. The operation sequence is as follows (see Serial Port Timing diagramsl:
1. The FSX and ~ pins are brought low.
.
2. One 8-bit byte is transmitted and one 8-bit byte is received.

3. The EODX and rni5Ii pins are brought low.
4. The
end rnA pins emit positive frame-sync pulses that are
four Shift Clock cycles wide.
5. One 8-bit byte is transmitted and one 8-bit byte is received.
6. The eo OX and eOOR pins are brought high.
7. The FSX and rnA pins are brought high.
Serial port directly interfaces with the .erial port of the TMS32020, TMS320C25, or TMS320C30

rnx

and communicates in one 16-bit word. The operation sequence is as follows (see Serial Port Timing

diagrams):
1. The

FSX

and

pins are brought low.

2. One 16-bit word is transmitted and one 16-bit word is received.

3. The FSX and ~ pins are brought high.
4. The ~ or rn!rn pins emit low-going pulses.
Since the transmit and receive sections of the Ale are now synchronous, the Ale serial port, with additional
NOR and AND gates, will interface to two SN74299 serial-to-parallel shift register•. Interfacing the AIC to
the SN74299 shift register .IIows the AIC to interface to an external FIFO RAM and facilitates parallel, data
bus communications between the Ale and the digital signal processor. The operation sequence is the same
as the above sequence (see Serial Port Timing diagrams).

TEXAS ."

F-51

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS,

TE~!,S

75265

TLC320401, TLC32040C, TLC320411, TLC32041 C,
TLC320421, TLC32042C

ANALOG INTERFACE CIRCUITS
INTERNAL TIMING CONFIGURATION

r-r~~-=_-~~-~-~~-~-~~-::"':-~-=-~-~'=t
DIVIDE 8Y 4

MASTER CLOCK
5.184 MHz I1t
10.368 MHz 121

_ _ _ _ _ _ _ _ _ _ _ _ _ ..I

--+SHIFT CLOCK
1.296 MHz 111
2.592 MHz 121

------,
OPTIONAL EXTERNAL CIRCUITRY
FOR clULL- DUPLEX MODEMS
-'53.6kHz- - - - - ,
CLOCK 111

COMMERCIAL
EXTERNAL
FRONT-END

DIVIDE BY 2

LOW-PASS
SWITCHED
CAP FILTER
CLK - 2B8 kHz
SQUARE WAVE

TX COUNTER B
TB-4O: 7.2 kHz
TB - 36: B.O kHz
fB-30: 9.6kHz
TB - 20: 14.4 kHz
TB-15; 19.2 kHz

DIA
CONVERSION
FREQUENCY

DIVIDE BY 2

BANDPASS
SWITCHED
CAP FILTER
CLK - 288 kHz
SQUARE WAVE

RX COUNTER B
RB-40: 7.2 kHz
RB - 36: 8.0 kHz
RB-30: 9.6 kHz
RB-20: 14.4 kHz
RB-15: 19.2 kHz

AID
CONVERSION
FREQUENCY

I
I

F~;Cr~~=~~ I

FILTERS!
I
L __________
:.J

L ____ _
SCF Clock Frequency =

____ J

Master Clock Frequency
2 x Contents of Counter A

NOTE: Frequency I, 20.736 MHz, is used to show how 153.6 kHz Ifor a commercially available modem split-band filter clockl. popular

speech and modem sampling signal frequencies, and an internal 288-kHz swi.tched'capacitor filter clock can be derived synchronously
and as submultiples of the crystal oscillator frequency. Since these derived frequencies are synchronous submultiples of the crystal
frequency. aliasing dO,8S not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter
stages. Frequency 2, 41 .4 72 MHz, is used to show that the AIC can work with high-frequency signals, which are used by highspeed digital signal processors.
tSplit-band filtering can alternatively be performed after the analog input function via software in the TMS320.
*These control bits are desCribed in the AIC OX Data Word Format section.

F-52

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TLC320401, TLC32040C, TLC320411, TLC32041C,
.
TLC320421, TLC32042C

, ANALOG INTERFACE CIRCUITS
explanation of internal timing configuration
All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the Master
Clock input pin. The Shift Clock signal, which strobes the serial port data between the AIC and DSP, is
derived by dividing the Master Clock input signal frequency by four.
SCF Clock Frequency

Conversion Frequency

Shift Clock Frequency

Master Clock Frequency
2 x Contents of Counter A
SCF Clock Frequency
Contents of Counter B
Master Clock Frequency

TX Counter A and TX Counter B, which are driven by the Master Clock signal, determine the D/A conversion
timing. Similarly, RX Counter A and RX Counter B determine the AID conversion timing. In order for the
switched-capacitor low-pass and bandpass filters to meet their transfer function specifications, the
frequency of the clock inputs of the switched-capacitor filters must be 288 kHz. If the frequencies of the
clock inputs are not 288 kHz, the filter transfer function frequencies are scaled by the ratios of the clock
frequencies to 288 kHz. Thus, to obtain the specified filter responses, the combination of Master Clock
frequency and TX Counter A and RX Counter A values must yield 288-kHz switched-capacitor clock signals.
These 288-kHz clock signals can then be divided by the TX Counter Band RX Counter B to establish the
D/A and AID conversion timings.
TX Counter A and TX Counter B are reloaded every D/A conversion period, while RX Counter A and RX
Counter B are reloaded every AID conversion period. The TX Counter Band RX Counter B are loaded with
the values in the TB and RB Registers, respectively. Via software control, the TX Counter A can be loaded
with either the TA Register, the TA Register less the TA' Register, or the TA Register plus the TA' Register.
By selecting the TA Register less the TA' Register option, the upcoming conversion timing will occur earlier
by an amount of time that equals TA' tjmes the signal period of the Master Clock. By selecting the T A
Register plus the T A' Register option, the upcoming conversion timing will occur later by an amount of
time that equals TA' times the Signal period of the Master Clock. Thus, the D/A conversion timing can
be advanced or retarded. An identical ability to alter the AID conversion timing is provided. In this case,
however, the RX Counter A can be programmed via software control with the RA Register, the RA Register
less the RA' Register, or the RA Register plus the RA' Register ..
The ability to advance or retard conversion timing is particularly useful for modem applications. This feature
allows controlled changes in the AID and D/A conversion timing. This feature'can be used to enhance
signal-to-noise performance, to perform frequency-tracking functions, and to generate nonstandard modem
frequencies.
If the transmit and receive sections are configured to be synchronous (see WORD/BYTE pin description).
then both the low-pass and bandpass switched-capacitor filter clocks are derived from TX Counter A. Also,
both the D/A and AID conversion timing are derived from the TX Counter A and TX Counter B. When the
transmit and receive sections are configured to be synchronous, the RX Counter A. RX Counter B, RA
Register, RA' Register, and RB Registers are not used.

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TLC320401, TLC32040C, TLC320411, TLC32041C,
TLC320421, TLC32042C

ANALOG INTERFACE CIRCUITS
AIC DR or OX word bit pattern
AID or D/A MSB,

1st bit sent

1 st bit sent of 2nd byte

AID or D/A LSB

AIC OX data word format section
COMMENTS

d151d141d131d121d111dl0ld91dSld71dSldSld41d21d11dO
primary OX serial communication protocol

.... d15 (MSBI through d2 go to the D/A

-1 0

The TX and RX Count.er A's are loaded witlilthe TA and RA register
values. The TX and RX Counter B's are loaded with TB and RB

converter register

d15 fMSBI through d2 go to the D/A

-1 0

The TX and RX Counter A's are loaded with the TA+TA' and
RA + RA' register values. The TX and RX Counter B's are loaded

converter register

with the TB and RB register values. NOTE: dl =0, dO= 1 will cause
the next D/A and AID conversion periods to be changed by the
addition of T A' and RA' Master Clock cycles, in which TA' and
RA' can be positive . or negative or zero. Please refer to
Table 1. AIC Responses to Improper Conditions.
.... d15 fMSBI through d2 go to the D/A

-I

The TX and RX Counter A's are loaded with the TA-TA' and
RA - RA' register values. The TX and RX Cllunter B's are loaded

converter register

with the TB and RB register values. NOTE: dl = 1, dO=O will cause
the next D/A and AID conversion periods to be changed by the
subtraction of TA' and RA' Master Clock cycles, in which TA' and
RA' can be positive or negative or zero. Please refer to
+-

d 15 fMSBI through d2 go to the 01 A
converter register

-11

Table 1. AIC Responses to Improper Conditions.
The TX and RX Counter A's are loaded with the TA and RA register
values. The TX and RX Counter B's are loaded with the TB and
RB register values. After a delay of four Shift Clock cycles, a
secondary transmission will immediately follow to program the Ale
to operate in the desired configuration.

NOTE: Setting the two least significant bits to 1 in the normal transmission of OAC information (Primary Communications) to the Ale
~iII initiate Secondary Communications upon completion of the Primary Communications.

Upon completion of the Primary Communication, FSX will remain high for four SHIFT f:=LOCK cycles and will then go low and initiate
the Secondary Communication. The timing specifications for the Primary and Secondary Communications are identical. In this manner.
the Secondary Communication. if initiated. is interleaved between successive Primary Communications. This inter,leaving prevents
the Secondary Communication from interfering with the Primary Communications and DAe timing. thus p~eventing the AIC from
skipping a OAC output. It is important to note that in the, synchronous mode; FSR will not be asserted during Secondary
Communications.

F-54

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TLC320401, TLC32040C, TLC320411, TLC32041 C,
TLC320421, TLC32042C

ANALOG INTERFACE CIRCUITS
secondary OX serial communication protocol
x x I .... to TA register .... , x
x, .... tp TA' register "'1 x
x, .... to TB register ... , x
x x x x x x x x

I ....

x, .... to RA register'"
...
to RA' register
...
to RB register

,I
,

d7 d6 d5 d4 d3 d2

0 0
0 1
1 0
1 1

I +-- CONTROL --+ I

d 13 and d6 are MSBs (unsigned binary)
d14 and d7 are 2's complement sign bits
d14 and d7 are MSBs (unsigned binary)
d2 = 011 deletes/inserts the bandpass filter

d3 = 0/1 disables/enables the loopback function
d4 = 011 disables/enables the AUX IN + and AUX IN - pins
d5 = 011 asynchronous/synchronous transmit and receive sections

d6 = 011 gain control bits (see Gain Control Section)
d7 = 011 gain control bits (see Gain Control Section)

reset function
A reset function is provided to initiate serial communications between the AIC and OSP. The reset function
will initialize all AIC registers, including the control register. After power has been applied to the AIC, a
negative-going pulse on the RESET pin will initialize the AIC registers to provide an 8-kHz AID and
01 A conversion rate for a 5.184 MHz master cloc~ input signal. The AIC, excepting the CONTROL register,
will be initialized as follows (see AIC OX Data Word Format section):
INITIALIZED
REGISTER
VALUE (HEX)
9
1
24
9

1
24

The CONTROL register bits will be reset as follows (see AIC OX Data Word Format section):
d7

= 1,

= 1, d4 = 0,

d3~ 0, d2

This initialization allows normal serial port communications to occur between AIC and OSP. If the transmit
and receive sections are configured to operate synchronously and the user wishes to program different
conversion rates, only the TA, TA', and TB register need to be programmed, since both transmit and receive
timing are synchronously derived from these registers (see the Pin Descriptions and AIC OX Word Format
sections).
The circuit shown below will provide a reset on power-up when power is applied in the sequence given
under Power-Up Sequence. The circuit depends on the power supplies' reaching their recommended values
a minimum of 800 ns before the capacitor charges to 0.8 V above OGTL GNO.
TLC32040/
TLC32041/
TLC32042

vcc+t--....--+5 v
200 kll

0.5,.F

vcc-

TEXAS

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F-55

TLC320401; TLC32040C. TtC320411. TLC32041C.
TLC320421. TLC32042C

ANALOG INTERFACE CIRCUITS
power-up sequence
To ensure proper operation of the AIC, and as a safeguard ,against latch-up, it is recommmended that a
Schottky diode with a forward voltage less than Or equal to 0.4 V be, connected from VCC- to ANLG
GND (see Figure 17). In the absence of such a diode, power should be applied in the following sequence:
ANLG GND and DGTL GND, VCC _, then VCC + and VDD. Also, no input signal should be applied until
after power-up.

AIC responses to improper conditions
The AIC has provisions for responding to improper conditions. These improper conditions and the response
of the AIC to these conditions are presented in Table 1 below.

AIC register constraints
The following constraints are placed on the contents of the AIC registers:
1. TA register must be > 1.
2. TA' register can be either positive, negative, or zero.
3, RA register must be > 1.
4. RA' register can be either positive, negative, or zero.
5. (TA register ± TA' register) must be > 1.
6. (RA register ± RA' register) must be > 1.
7. TB register must be > 1.
TABLE 1. AIC RESPONSES TO ,IMPROPER CONDITIONS
IMPROPER CONDITION
T A register - T A' register

=0
=0

TA register + TA' register

< 0

RA register + RA' register

=0
=0
=0

T A register + T A' register

AIC RESPONSE
or 1

Reprogram TX Counter A with TA register value

or 1
MODULO 64 arithmetic is used to ensure that a positive value is loaded into the TX Counter A.
i.e., TA register + TA' register + 40 HEX is loaded into TX Counter A

RA reg'ister - RA' register
RA register + RA' register

or 1

Reprogram RX Counter A with RA register value

or 1
or 1

MODULO 64 arithmetic is used to ensure that a positive value is loaded into RX Counter A.

i.e" RA register + RA' register + 40 HEX is loaded into RX Counter A
T A register
RA register

=0
=0

or 1

AIC is shut down

or 1

TB register - 0 or 1
RB register

Reprogram TB register with 24 HEX

or 1

Reprogram RB register with 24 HEX

AIC and DSP cannot communicate

Hold last DAC output

improper operation due to conversion times being too close together
If the difference between two successive D/A conversion frame syncs is less that 1/19.2 kHz, the AIC
operates improperly. In this situation, the second D/A conversion frame sync occurs too quicklY,and there
is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B
registers are improperly programmed or if the A + A' register or A - A' register result is too small. When
- incrementally adjusting the conversion period via the A + A' register options, the designer should be very
careful not to violate this requirement (see diagram below).

~~~E!~~
FSX

i4-0NGOING

CONVERSION~

t2 - tl '" 1/19.2 kHz

F-56

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POST OFFICE BOX 655012 • DALLAS. TEXAS 15265

TLC320401, TLC32040C, TLC320411, TLC32041C,
TLC320421, TLC32042C

ANALOG INTERFACE CIRCUITS
asynchronous operation - more than one receive frame sync occurring between two transmit frame
syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the
AIC during a FSX frame sync. The ongoing conversion period is then adjusted. However, either Receive
Conversion Period A or B may be adjusted. For both transmit and receive conversion periods, the incremental
conversion period adjustment is performed near the end of the conversion period. Therefore, if there is
sufficient time between t1 and t2, the receive conversion period adjustment will be performed during Receive
Conversion Period A. Otherwise, the adjustment will be performed during Receive Conversion Period B.
The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a subsequent FSX frame (see figure below).

M14I------TRANSMIT CONVERSION PERIOD-----..,~~I

I
~ RECEIVE CONV.
PERIOD A

---*- RECEIVE CON V .---t
PERIOD B

asynchronous operation - more than one transmit frame sync occurring between two receive frame
syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. For both transmit and receive conversion periods, the incremental conversion period
adjustment is performed near the end of the conversion period. The command to use the incremental
conversion period adjust options is sent to the AIC during a FSX frame sync. The ongoing transmit conversion
period is then adjusted. However, three possibilities exist for the receive conversion period adjustment
in the diagram as shown in the figure below. If the adjustment command is. issued during Transmit
Conversion Period A, Receive Conversion Period A will be adjusted if there is sufficient time between t1
and t2. Or, if there is not sufficient time between t1 and t2, Receive Conversion Period B will be adjusted.
Or, the receive portion of an adjustment command may be ignored if the adjustment command is sent
during a receive conversion period, which is already being or will be adjusted due to a prior adjustment
command. For example, if adjustment commands are issued during Transmit Conversion Periods A, B,
and C, the first two commands may cause Receive Conversion Periods A and B to be adjusted, while the
third receive adjustment command is ignored. The third adjustment command is ignored since it was issued
during Receive Conversion Period B, which already will be adjusted via the Transmit Conversion Period B
adjustment command.

i+-TRANSMIT CONV .......... TRANSMIT CONV . . . . TRANSMIT CONV ....
·PERIOD A
PERIOD B
PERIOD C

FSRU
I

!4---RECEIVE CONVERSION PERIOD A

U-

I
RECEIVE CONVERSION PERIOD B----i~~t

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TLC320401, TLC32040C, TLC320411, TLC32041C,
TLC320421, TLC32042C
ANALOG INTERFACE CIRCUITS
asynchronous operation - more than one set of primary and secondary DX serial communication
occurring between two receive frame sync (see Ale DX Data Word Format section)
The T A, T A', TB, and control register information that is transmitted in the secondary communications
is always accepted and is applied during the ongoing transmit conversion period. If there is sufficient time
between tl and t2, the TA, RA', and RB regist~r information, which is sent during Transmit Conversion
Period A, will be applied to Receive Conversion Period A. Otherwise, this information will be applied during
Receive Conversion Period B. If RA, RA', and RB register information has already been received and is
being applied during an ongoing conversion period, any subsequent RA, RA', or RB information that is
received during this receive conversion period will be disregarded (see diagram below).
'1

PRIMARY

SECONDARY

PRIMARY

SECONDARY

PRIMARY

,....----,

..---~

SECONDARY

..---""

TRANSMIT
TRAIIISMIT
TRANSMIT
If----CONVERSION------.Itf-----CONVERSION----I,..----CONVERSION---.....
PERIOD A
PERI,OD B
PERIOD C

I
I

+-RECEIVE CONVERSION_.......If-_ _ _ _ _ _ RECEIVE CONVERSION PERIOD B------~~
PERIOD A

"'1'"

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to 15 V
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Output voltage, Vo ...................................... '" ....... -0.3 V to 15 V
Input voltage, VI ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Digital ground voltage .........................................'..... - 0.3 V to 15 V
Operating free-air temperature range: TLC32040l, TLC32041I, TLC320421 ...... -40°C to 85°C
.
TLC32040C, TLC32041C, TLC32042C ....... O°C to 70°C
Storage temperature range ................................ :........ - 65°C to 150°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package .... '" ..... 260°C
NOTE 1: Voltage values for maximum ratings are with respect to

F-58

vee - .

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POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

TLC320401, TLC32040C, TLC320411, TLC32041C,
TLC320421, TLC32042C

ANALOG INTERFACE CIRCUITS
recommended operating conditions
MIN

NOM

MAX

UNIT

Supply voltage. Vcc + (see Note 21

PARAMETER

4.75

5.25

Supply voltage. Vcc _ (see Note 2)

-4.75

5
-5

-5.25

4.75

5.25

VOO+0.3
0.8

100

Digital supply voltage. VDD (see Note 2)
Digital ground voltage with respect to ANLG GND. DGTL GND
Reference input voltage. V ref(ext) (see Note 2)
High-level input voltage. VIH
Low-level input voltage. VIL (see Note 3)

-0.3

Load resistance at OUT + andlor OUT -. RL

Load capacitance at OUT + andlor OUT -. CL
MSTR CLK frequency (see Note 4)

0.075

300
5

10.368

MHz

Analog input amplifier common mode input voltage (see Note 5)

± 1.5

AID or 01 A conversion rate

19.2

kHz
kHz

Conversion rate
Operating free-air temperature. T A

I TLC320401. TLC32041I. TLC320421
I

TLC32040C. TLC32041C. TLC32042C

-40

NOTES: 2. Voltages at analog inputs and outputs. REF. VCC+. and VCC-. are with respect to the ANLG GND terminal. Voltages at
digital inputs and outputs and VDD are with respect to the DGTL GND terminal.
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet
for logic voltage levels and temperature only.

4. The bandpass and low-pass switched-capacitor filter response specifications apply only when the switched-capacitor clock
frequency is 288 kHz. For switched-capacitor filter clocks at frequencies other than 288 kHz. the filter response is shifted
by the ratio of switched-capacitor filter clock frequency to 288 kHz.
5. This'range applies when (IN + .- IN-) or (AUX IN+ - AUX IN-) equals ±6 V . •

TEXAS .."

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F-59

TLC320401,. TLC32040C, TLC320411, TLC32041C,
TLC320421, TLC32042C

ANALOG INTERFACE CIRCUITS
electrical characteristics over recommended operating free-air temperature range.
VCC- - -5 V. VOO - 5 V (unless otherwise noted)

Vcc+ - 5 V.

total device. MSTR elK frequency - 5.1a4 MHz. outputs not IQaded
VOH
Val

PARAMETER
High·level output voltage
low-level output voltage

ICC+

Supply current from VCC +

ICC-

Supply current from V CC _

100

Supply current from VOO
Internal reference output voltage
Temperature coefficient of imernal

Vref
"Vref
ro

TEST CONDITIONS
VDO
VOO

= 4.75
= 4.75

V. IOH
V. IOl

= -300 ~A
= 2 mA

MIN
2.4

Typt

MAX
0.4

TlC3204-C

35
40
-35
-40

TLC3204-1
TLC3204-C
TLC3204_1
fMSTR ClK

7
3.3

5.184 MHz
3

reference voltage
Output resistance at REF

UNIT
V
V
mA
mA
mA
V

100

ppml·C

100

receive amplifier input
PARAMETER

TEST CONDITIONS

MIN

AID converter offset error (filters bypassed I
AID converter offset error (filters inl
Common-mode rejection ratio at IN +. IN - •
CMRR
or AUX IN+. AUX IN-

See Note 6

Input resistance at IN +. IN-

or AUX IN+. AUX IN-. REF

TYpt

MAX

UNIT
mV

100

transmit filter output
PARAMETER

TEST CONDITIONS

VOO

Output offset voltage at OUT + or OUT(single-ended relative to ANlG GNOI

YOM

Maximum peak output vottage swing across
Rl at OUT + or OUT - (single-endedl

YOM

Maximum peak output voltage swing between
OUT + and OUT - (differential outputl

TYpt

MAX

UNIT
mV

Rl'" 300 O.
Offset voltage = 0

±3

RL'" 6000

±6

t All typical values are at TA = 25 ·C.
NOTE 6: The test condition is a O-dBm. l-kHz input signal with an 8-kHz conversion rate.

F-60

MIN

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TLC320401. TLC32040C. TLC320411. TLC32041 C.
TLC320421. TLC32042C
ANALOG INTERFACE CIRCUITS
electrical characteristics over recommended operating free-air temperature range. VCC+ - 5 V.
VCC- - -5 V. VOO - 5 V (unless otherwise noted)
system distortion specifications. SCF clock frequency - 288 kHz
PARAMETER

MIN

TEST CONDITIONS

Attenuation of second harmonic of

single-ended

AID input signal

differential

Vin = - 0.1 dB to - 24 dB referred to V ref.
See Note 7

Typt

MAX

70
62

Attenuation of third and higher

single-ended

Vin -

harmonics of AID input signal

differential

See Note 7

Attenuation of second harmonic of

single-ended

01 A input signal

differential

Vin = - 0 dB to - 24 dB referred to V ref.
See Note 7

Attenuation of third and higher

single-ended

harmonics of DIA input signal

differential

Vin = - 0 dB to - 24 dB referred to V ref.
See Note 7

- O. 1 dB to - 24 dB referred to V ref.

UNIT
dB

AID channel signal-to-distortlon ratio
TEST CONDITIONS

PARAMETER

(s. . Note

Vin
Vin
Vin

=
=
=

Vin AID channel signal-to-distortion ratio

Vin
Vin

=
=

Vin Vin

Vin

=
=

Av - 1*
MIN MAX

Av - 2*
MIN MAX

Av - 4*
MIN MAX

-6 dB to -0.1 dB

>58§

-12 dB to -6 dB

>58§

-18 dB to -12 dB

- 24 dB to - 1 B dB

-30 dB to -24 dB

-36 dB to -30 dB

-42 dB to -36 dB

-48 dB to -42 dB

-54 dB to -48 dB

UNIT

DIA channel signal-to-distortlon ratio
TEST CONDITIONS

PARAMETER

(s. . Note

D/A channel signal·to-distortion ratio

MIN

Vin = -6 dB to -0.1 dB
Vin = -12dBto -6dB

Vin - -18 dB to -12 dB

Vin = -24 dB to - f8 dB
Vin = -30 dB to -24 dB
Vin = -36 dB to -30 dB

50
44

UNIT

-42 dB to -36 dB

Vin = -48 dB to -42 dB
Vin = -54 dB to -48 dB

Vin

MAX

gain and dynamic range
PARAMETER

TEST CONDITIONS

Absolute transmit gain tracking error while transmitting

- 48 dB to 0 dB signal range.

into 600 0

See Note 8
- 48 dB to 0 dB signal range.

Absolute receive gain tracking error

See Note 8

MIN

TYpt

MAX

UNIT

±0.05 ±0.15

±0.O5 ±0.15

t Ail typical values are at T A = 25 ·C.
t Av is the programmable gain of the input

amplifier.
§A value > 58 is overrange and signal clipping occurs.
NOTES: 7. The test condition is a 1-kHz input signal with an 8-kHz conversion rate (0 dB,relative to Vref). The load impedance for the
DAC is 600 D.
8. Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 db relative to Vref).

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F-61

TLC320401. TLC32040C. TLC320411. TLC32041 C.
TLC320421. TLC32042C

ANALOG INTERFACE CIRCUITS
power supply rejection and crosstalk attenuation
PARAMETER

TEST CONDlnONS
Idle channel .. supply signal

Vee + or Vce _ supply voltage

f = 0 to 30 kHz

rejection ratio. receive channel

I = 30 kHz to 50 kHz

at 200 mV p-p measured
at DR (ADC output)

Vec + or V CC _ supply voltage

I = Oto 30 kHz

Idle channel. supply signal
at 200 mV p-p measured

rejection:ratio. transmit channel

(single-ended)

I = 30 kHz to 50 kHz

MIN ' TYpt

MAX

dB
45
30
dB
45

at OUT+

Crosstalk attenuation, transmit-to-receive (single-ended)

delay distortion. SCF clock frequency - 288 kHz ± 2%. input (IN +

UNIT

..... IN -) is ± 3-V sinewave

Please refer to filter response graphs for delay distortion specifications.

TLC32040 and TLC32041 bandpass filter transfer function (see curves). SCF clock
frequency - 288 kHz ± 2%. input (IN + - IN -) is a ± 3-V sinewave (see Note 9)
PARAMETER

Filter Gain
(see Note 10)

TEST CONDlnONS

MIN

MAX
-42

f = 100 Hz
f = 170 Hz
Input signal relerence is 0 dB

300 Hz s I s 3.4 kHz
f = 4 kHz

UNIT

-25
-0.5

0.5
-16

-58

I '" 4.6 kHz

TLC32042 bandpass filter transfer function (see curves). SCF clock frequency - 288 kHz ± 2%.
input (IN + - IN -) is a ± 3-V sinewave (see Note 9)
PARAMETER

Filter Gain
(see Note 10)

TEST CONDITIONS

Input signal reference is 0 dB

MIN

MAX
-27

-0.5

1'74 kHz

0.5
-16

I '" 4.6 kHz,

-58

I = 100 Hz
f-170Hz
300 Hz's I s 3.4 kHz

UNIT

-2
dB

low-pass filter transfer function. SCF clock frequency - 288 kHz ± 2% (see Note 9)
.PARAMETER
Filter Gain
(see Note 10)

TEST CONDlnONS
I s 3.4 kHz
I = 3.6 kHz
Output signal relerence is 0 dB
I = 4 kHz

MAX

MIN
-0.5

0.5
-4
-30
-58

f '" 4.4 kHz

UNIT

serial port
VOH

PARAMETER
High-level output voltage

VOL
(I

Input current

Low-level output voltage

TEST CONDlnONS
IOH -

-300

MIN
2.4

TYpt

IOL=2mA

MAX

UNIT
V

0.4

±10

Input capacitance

~
pF

Output capacitance

t All typical values are at T A = 25 ·C.
NOTES: 9. The above Iilter specifications are lor a switched-capacitor lilter clock range 01 288 kHz ±2%. For switched-capacitor lilter
clocks at Irequencies other than 288 kHz ± 2%. the Iilter response is shifted by the ratio 01 switched-capacitor filter clock
frequency to 288 kHz.
10. The lilter gain outside 01 the passband is measured with respect to the gain at 1 kHz. The lilter gain within the passband
is measured with respect to the average gain within the passband. The passbands are 300 to 3400 Hz 'and 0 to 3400 Hz
for the bandpass and lowpass lilters respectively.
.

F-62

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POST OFFICE BOX 855012 • DALLAS. TEXAS 75265

TLC320401, TLC32040C, TLC320411, TLC32041C,
TLC320421, TLC32042C
ANALOG INTERFACE CIRCUITS
operating characteristics over recommended operating free-air temperature range.

VCC- -

Vcc+ - 5 V.

-5V. VDO - 5V

noise (measurement includes low-pass and bandpass switched-capacitor filters)
PARAMETER

Typt

TEST CONDITIONS

I single-ended

Transmit noise

DX input = 00000000000000, constant input code

differential

MAX

200
300

500

Receive noise (see Note 11)

Inputs grounded, gain

300

UNIT

/l-V rms

475

p.V rms
dBrncO
ltV rms
dBrncO

timing requirements
serial port recommended input signals
PARAMETER

MIN

tf(MCLK)

Master clock fall time
Master clock duty cycle

42%

~ pulse duration (see Note 12)

tsulDXI
th(DX)

MAX

tc(MCLKI Master clock cycle time
trlMCLKI Master clock rise time

DX setup time before SCLKI
DX hold time after SCLKI

UNIT

ns
10

58%

800

ns
ns

tclSCLKI/4

t All typical values are at T A = 25°C.
NOTES: 11. This noise is referred to the input with a buffer gain of one. If the buffer gain is two or four, the noise figure will be
correspondingly reduced. The noise is computed by statistically evaluating the digital output of the AID converter.
12. ~ pulse duration is the amount of time that the reset pin is held below 0.8 V after the power supplies have reached
their recommended values.

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F-63

TLC320401, TLC32040C, TLC320411, TLC32041C,
TLC320421, TLC32042C

ANALOG INTERFACE CIRCUITS
operating characteristics over recommended operating free-air tertJperature range. Vee +
Vee- - -5 V. VOO - 5 V (continued)

5 V.

serial port - AIC output signals
PARAMETER
Shift clock ISCLK) cycle time

tcISCLK)
tfISCLK)

MIN
\

Shift clock ISCLK) fall time
Shift clock ISCLK) rise time
Shift clock ISCLK) duty cycle

trfSCLKI

MAX

380

UNIT
ns

50
55

ns
%

tdICH-FL)

Delay from SCLKT to FSR/FSXI

tdICH-FHj
tdICH-DR)

Delay from SCLKT to FSR7FSXT
DR valid after SCLKT

90
90

tdwICH-EL)

Delay from SCLKT to Wl5XiernlRI in word mode

IdwICH-EH)

Delay from SCLK T to rnJ5XieODRT in word mode

tf(EODX)

EODX fall time

tffEODRI

EODR fall time

tdbfCH-ELI

Delay from SCLKT to EODX/EODRI in byte mode

tdbfCH-EHI

Delay from SCLKT to EODX/EODRT in byte mode

100

TABLE 2. GAIN CONTROL TABLE
(ANALOG INPUT SIGNAL REQUIRED FOR FULL-SCALE AID CONVERSIONI
CONTROL REGISTER BI1;S
d7
d6

INPUT CONFIGURATIONS

AID CONVERSION

ANALOG INPUTt

RESULT

Differential configuration

±& V

full-scale

Analog input = IN + - IN= AUX IN+ - AUX IN-

0
1

±3 V
±1.5 V

full-scale
full-scale

Single-ended configuration

0
1

0
0
1
1

±3 V

half-scale

Analog input = IN +. - ANLG GND
= AUX IN + - ANLG GND

0
1

0
0
1

±3 V
±1.5 V

full-scale
full-scale

t In this example, Vref is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input

not exceed O. 1 dB below full scale.

Rfb

R
IN + ---'VVI....-I

_~TOMUX

h-....

R
IN--VVl....-I

R
AUX IN + -VVl....-I

1. d7 O. d7 - 1. d7
- O. d7

Rfb - Rford& - l.d7 d6 - O. d7 Rfb - 2Rford& - 1.d7
Rfb - 4R for d& - O. d7

1
0
- 0
- 1

FIGURE 1. IN + AND IN - GAIN
CONTROL CIRCUITRY

F-64

I-;:-....

Rfb

Rfb
R,b - R for d6 d6 R,b - 2R for d6
Rfb - 4R for d6

_~TOMUX

R
AUX IN - -VVl....-I

1
0
- 0
- 1

FIGURE 2. AUX IN + AND AUX INGAIN CONTROL CIRCUITRY

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7~26S

TLC320401, TLC32040C, TLC320411, TLC32041 C,
TLC320421, TLC32042C

ANALOG INTERFACE CIRCUITS
sin xIx correction section
The AIC does not have sin x/x correction circuitry after the digital-to-analog converter. Sin x/x correction
can be accomplished easily and efficiently in digital signal processor (DSP) software. Excellent correction
accuracy can be achieved to a band edge of 3000 Hz by using a first-order digital correction filter. The
results, which are shown below, are typical of the numerical correction accuracy that can be achieved
for sample rates of interest. The filter requires only seven instruction cycles per sample on the
TMS320 DSPs. With a 200-ns instruction cycle, nine instructions per sample represents an overhead factor
of 1.4% and 1.7% for sampling rates of 8000 Hz and 9600 Hz, respectively. This correction will add a
slight amount of group delay at the upper edge of the 300-3000-Hz band.

sin xIx roll-off for a zero-order hold function
The sin x/x roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for
the various sampling rates is shown in the table 'below.
TABLE 3. sin x/x ROLL-OFF

fs 1Hz)

20 log sin .. f/fs
.. flfs
If - 3000 Hz)
IdB)

-2.64
-2.11
-1.44
-0.63
-0.35

7200
8000
9600
14400
19200

Note that the actual AIC sin x/x roll-off will be slightly less than the above figures, because the AIC has
less man a 100-% duty cycle hold .interval.

correction filter
To compensate for the sin x/x roll-off of the AIC, a first-order correction filter shown below, is recommended.

UIi+1)

} - - - - - - - - - -.....--+YIi+ 1)

The difference equation for this correction filter is:
Yi+1 = p2(1-p1) (Ui+1)+p1 Yi
where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
IH(f)12

p22 (1 -p1)2
1 - 2p1 cos(2 1r f/fs) + p1 2

TEXAS ."

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F-65

TLC320401. TLC32040C. TLC320411. TLC32041C.
TLC320421. TLC32042C

ANALOG INTERFACE CIRCUITS
correction results
Table 4 below shows the optimum p values and the corresponding correction resi.!lts for 8000-Hz and
9600-Hz sampling rates.
TABLE 4

f 1Hz)

300
600
900
1200
1500
1800
2100
2400
2700
3000

ERROR CdB)
fs - BOOO Hz
p1 - -0.14813
p2 - 0.9888
-0.099
-0.089
-0.054
-0.002
0.041
0.079
0.100
0.091
-0.043
-0.102

ERROR CdB)
f. - 9800 Hz

p1 - -0.1307
p2 - 0.9951
-0.043
-0.043
0
0
0
0.043
0.043
0.043
0
-0.043

TMS320 software requirements
The digital correction filter equation can be written in state variable form as follows:
Y = k1Y +k2U
where k1 equals p1 (from the preceding page), k2 equals (1-p1)p2 (from the preceding page), Y is the
filter state, and U is the next 110 sample. The coefficients k 1 and k2 must be represented as 16-bit integers.
The SACH instruction (with the proper shift) will yield the correct result. With the assumption that the
TMS320 processor page pointer and memory configuration are properly initialized. the equation can be
executed in seven instructions or seven cycles with the following program:
ZAC
LT K2
MPY U
LTA K1
MPYY
APAC
SACH (dma), (shift)

F-66

TEXAS ",

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POST OFFICE BOX 855012 • DALLAS. TEXAS 75285

TLC320401, TLC32040C, TLC320411, TLC32041C,
TLC320421,. TLC32042C

ANALOG INTERFACE CIRCUITS
byte-mode timing

. I

I 0.8 V
tclICH-Fl~

~tc(SClKI

~ro-t'ISClKI

'''''''If-tflSClKI
SHIFT ClK

Ie-

I
I

I·

0.8

--t

-4Ilt- tdICH-FHI
II

It-tdICH-Fll
I

I
tdICH-FH.-..t

It--

ttr.2:":v:--------'"\\1
I~
~i-(-----'If
0.8 v+"-_ _-J!.I-'_ _ _ _ _-!'F

BR.m ~08V

I
I
I ...., ~ ~dICH-ORI
DR

I
I

_--,0,,-1;.;;5_--,Y~~

,[§IT!lJ-ou

tsulOXI.... ItOX

I
I

DO:

I
I

~:1[~:x~~I}-_-200~N~.~T~C~A~R~E
_ _C!~XJ~~
~,J 09
DB I
07
06~
.;......~

I.-- thlOXI

~ It- tdblCH Ell

~.~---------~:~:----~i~~O~.8~V_ _-_ _ _ _ _ _ _ _ _-f:_~._____td_bl_C_H-_EH_~-J~
word-mode timing
Io---*-tclSClKI
I

SHIFT elK

O.8V~2V

FIGURE 3. SERIAL PORT TIMING

(

TEXAS'"

INSTRUMENTS

POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

F-67

TLC320401. TLC32040C. TLC320411. TLC32041C.
TLC320421. TLC32042C
ANALOG INTERFACE CIRCUITS
r
ffi(

TMS32010

SN74lS299
~ S1

AO/PAO

Al/PAl
A2/PA2

8
C

YO -

SO
Gl

08-015

A-H

I.-

'---

00-015

ClK OUT

TLC320401
TLC32041 I
TlC32042

rO=-

SN74lS299

PD
WE

ClK<

[

SN74lS138

00-015

QH'

DEN

00-07

"""

S1
62
SO
61

QH
ClK

A-H

U-cr-

SHIFT ClK

.r-

r-Ll

•

/
MSTR ClK

rnl>X

INT

FIGURE 4. TMS32010-TLC32040/TLC32041/TLC32042 INTERFACE CIRCUIT

in instruction timing
ClK OUT

_ _oJ

I ~I------------------------------....---+I~·
I

SO.G1
00-015

I
I

___________~c:~~~I>-----------------(

VALID

)

out instruction timing
ClK OUT _ _ _--'

----~:~I~----------------------i
I

SN74lS138 Y1

SN74lS299 ClK

I
00-015

;

--7"""-----...;.---«=V~A~l~IOt:».,..---------------FIGURE 5. TMS3201 O-TLC32040ITLC32041 ITLC32042 INTERFACE TIMING

F-6S

TEXAS

..If

INSIRUMENlS
POST OFFICE BOX 665012 • DALLAS. TeXAS 75285

TLC320401. TLC32040C. TLC320411. TLC32041C.
TLC320421. TLC32042C

ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
AIC TRANSMIT CHANNEL FILTER
10

0.3

~ag~itud~

-10
III

.1::

:i!

Group Delay

-30

-50

-70

V-

-80
-90

Kf'

\~ .1

\.. /

0.1

\
\

See Note B ,

-40

-60

0.2
0.15

-20

"..I
""c

0.25

0.05
0

I
>
Ii

"~
C!J

0.05 .~
CD

"ii

r-I"-See Note A

I--+-S~e N~te

0.1

0.15
0.2

.
SCF clock frequency
Normalized FrslJuency-kHz x
288 kHz
NOTES: A.
B.
C.
O.

Maximum relative delay (0 H~ to 600 Hz) = 125 ~s.
Maximum relative delay (600 Hz to 3000 Hz) = ± 50 ~s.
Absolute delay (600 Hz to 3000 Hz) = 700 ~s.
Test conditions are VCC+. VCC--. and VOO within recommended operating conditions. SCF clock f
input = ±3-Vsinewave.andTA = 25°C.

= 2B8

kHz ±2%.

FIGURE 6

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265

F-69

TlC320401, TlC32040C, TlC320411i TlC32041C,
TlC320421, TLC32042C

ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
TLC32040 and TLC32041
RECEIVE CHANNEL FILTER
10

0.35

Magnit~de

See Note A

0.3
0.25

-10

-20
III
'0

-30

.Ec

~40

4>
'0

-50

-70

U/'JI. V

>.!!

4>
Q

0.1

e"
Cl

>
;::
.!!
CD

0.05

0.1

See Note C-

-90

III

0.15

0.05

\
\y......

LSee Note 8

-80

Group Delay

-60

0.2

0.15
4

SCF clock frequency
288 kHz
Normalized Frequency-kHz x
NOTES: A.
B.
C.
D.

Maximum relative delay (200 Hz to 600 Hz) = 3350 ~s.
Maximum relative delay (600 Hz to 3000 Hz) = ± 50 ~s.
Absolute delay (600 Hz to 3000 Hz) = 1230 ~s
Test conditions are VCC +, VCC _, and VDD within recommended oDer.ting conditions, SCF clock f
input = ± 3-V sinewave, and T A = 25 ·C.

FIGURE 7

F-70

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265

2B8 kHz ± 2%,

TLC320401, TLC32040C, TLC320411, TLC32041C,
TLC320421, TLC32042C
ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
TLC32042
RECEIVE CHANNEL FILTER
10
0
-10

..,
..,.I

0.3

Ma~nitu~e
Se~ No~e A
...

0.25
0.2

-20

III

'"..

-30
-40
-50

0.15

Group Delay

-60 r-:see1 e f
-70

0.05

0.1

''-/

0.05

"\ 0.1

III

E
I

>to
Gi
0
Q.
~

..,:>
to

See Note C

0.15

-80
-90
0

Normalized Frequency-kHz x
NOTES: A.
B.
C.
D.

0.2

SCF clock frequency
288 kHz

Maximum relative delay (200 Hz to 600 Hzl = 3350 ~s.
Maximum relative delay (600 Hz to 3000 Hzl = ± 50 ~s.
Absolute delay (600 Hz to 3000 Hzl = 10BO I's.
Test conditions are VCC +. VCC _. and VDD within recommended operating conditions. SCF clock f
input = ± 3-V sinewave, and T A

288 kHz ± 2%.

25°C.

FIGURE 8

TEXAS

INSIRUMENlS
POST OFFICE

aox 655012

• DALLAS. TEXAS 75265

F-71

TLC320401, TLC32040C, TLC320411, TLC32041 C,
TLC320421, TLC32042C

ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
AID GAIN TRACKING
(GAIN RELATIVE TO GAIN
AT 0 dB INPUT SIGNAL)

AID SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL
80
70

GAIN 1.4X

~
I

0.5

1-kHz Input signal with an
8-kHz conversion rate

"V V
V

1-kHz input signal
0.4 8-kHz conversion rate

r--.

0.3

GAIN - 1X-

...

0.2

i..c

0.1

-0.1

'ii
CI -0.2

-0.3

o-50

...

-0.4
-40
-30
-20
-10
o
Input Signal Relative to Vref-d8

-0.5
-50

-40

FIGURE 9

1-kHz Input signel into 600 11
90 8-kHz conversion rete
80

a:
c 60

'f
0

~
S

1ic

0.4

0.2

...I

:.u
~

·1

0
-0.2

CI -0.4

en 20

-0.6

-50

0.6

V r--

.S!'

1.0
1-kHz input signal into 600 11
0.8 8-kHz conversion rate

. . ,X

-10

D/A GAIN TRACKING
vs
(GAIN RELATIVE TO GAIN
AT 0 dB INPUT SIGNAL)

10Cl

-20

FIGURE 10

D/A CONVERTER SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL

...I

-30

Input Signal Relative to Vref-d8

-0.8
-30
-20
-10
0
Input Signal Relative to Vref-d8

-40

-1

'-50

-40

-30

-20

-10

Input Signal Relative to Vref-dB

FIGURE 11

FIGURE 12
NOTE: Test conditions are Vcc+, VCC _. and VOO within recommenaed operating conditions set clock f

F-72

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265

= 288 kHz' ±2%, and TA = 25°C.

TLC320401, TLC32040C, TLC320411, TLC32041C,
TLC320421, TLC32042C
ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
ATTENUATION OF SECOND HARMONIC OF AID INPUT
vs
INPUT SIGNAL
100
ID

I
u
"2

:I:

"t:I

:;;

"t:I
C

100

".--

/
/

ATTENUATION OF THIRD HARMONIC OF AID INPUT
vs
INPUT SIGNAL
1 -kHz input signal
90 8-kHz conversion rate

ID
"t:I

"-"'- ./"

I
"S!
c

:I:

(""-.,...

:;;

-...J

"t:I

lf-

'0 40

"c
!

II>

1 -kHz input signal
8-kHz conversion rate

-50

-40

-30

-20

-10

-50

Input Signal Relative to V ref - dB

-40
-30
-20
-10
o
Input Signal Relative to V ref - dB

FIGURE 13

FIGURE 14

ATTENUATION OF SECOND HARMONIC OF DIA INPUT
vs
INPUT SIGNAL

ATTENUATION OF THIRD HARMONIC OF D/A INPUT
vs
INPUT SIGNAL

100
ID

1 -kHz input signal into 600
90 8-kHz conversion rate

"t:I

c
.~

...-

100
[l
ID

"
!

1 -kHz input signal into 600
90 8-kHz conversion rate

"0 40
c

.."

.g
c

-~z
~oo

II:

a
3:

l?l?
l?l?
-' -'

1.
2. TA' register can be either positive, negative, or zero.
3. RA register must be > 1.
4. RA' register can be either positive, negative, or zero.
5. (TA register ± TA' register) must be > 1.
6. (RA register ± RA' register) must be > 1.
7. TB register must be > 1.
TABLE 1. AIC RESPONSES TO IMPROPER CONDITIONS
IMPROPER CONDITION

AIC RESPONSE

T A register + TA' register = 0 or 1

Reprogram TX Counter A with TA register value

TA register - TA' register = 0 or 1
TA register + TA' register

< 0

MODULO 64 arithmetic is used to ensure that a positive value is loaded into the TX Counter A,
i.e., TA register + TA'register + 40 HEX is loaded into TX COUllter A

RA register + RA' register - 0 or 1

Reprogram RX Counter A with RA register value

RA register - RA' register = 0 or 1
RA register + RA' register
T A register

or 1

MODULO 64 arithmetic is used to ensure that a positive value is loaded into RX Counter A,
Le .. RA register + RA' register + 40 HEX is loaded into RX Counter A
AIC is shut down

or 1

RA register = 0 or 1
TB register
RB register

=
=

0 or 1

Reprogram TB register with 24 HEX

0 or 1

Reprogram RB register with 24 HEX

AIC and DSP cannot communicate

Hold last DAC output

improper operation due to conversion times being too close together
If the difference between two successive D/A conversion frame syncs is less that 1/19.2 kHz, the Ale
operates improperly. In this situation, the second D/A conversion frame sync occurs too quickly. and there
is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B
registers are improperly programmed or if the A + A' register or A - A' register result is too small. When
incrementally adjusting the conversion period via the A + A' register options, the designer should be very
careful not to violate this requirement (see diagram below).

~:~E~~
FSX

~:R

i4--0NGOING CONVERSION-.!

12 - 11 '" 1119.2 kHz

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

F·87

TLC320441, TLC32044C

YOICE·BAND ANALOG INTERFACE CIRCUITS
asynchronous operation - more than one r~ceive frame sync occurring between two transmit frame
syncs
When incrementally adjusting the conversion period via the A + A' or A ~ A' register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the
AIC during a FSX frame sync. The ongoing conversion period is then adjusted. However, either Receive
Conversion Period A or B may be adjusted. For both transmit and receive conversion periods, the incremental
conversion period adjustment is performed near the end of the conversion period. Therefore, if there is
sufficient time between t1 and t2, the receive conversion period adjustment will be performed during Receive
Conversion Period A. Otherwise. the adjustment will be performed during Receive Conversion Period B.
The adjustment command only adjusts one transmit conversion period and one receive co!,version period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a subsequent FSX frame (see figure below).

M"I------TRANSMIT CONVERSION PERIOD-----~.~I

~RECEIVE CONV. ____ RECEIVE CONV.~

PERIOD A

PERIOD B

asynchronous operation - more than one transmit frame sync occurring between two receive frame
'syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. For both transmit and receive conversion periods, the incremental conversion period
adjustment is performed near the end of the conversion period. The command to use the incremental
conversion period adjust options is sent to the Ale during a FSX frame sync. The ongoi~g transmit conversion
period is then adjusted. However. three possibilities exist for the receive conversion period adjustment
in the diagram as shown in the figure below. If the adjustment command is issued during Transmit
Conversion Period A. Receive Conversion Period A will be adjusted if there is sufficient time between t1
and t2. Or, if there is not sufficient time between t1 and t2, Receive Conversion Period B will be adjusted.
Or, the receive portion of an adjustment command may Qe ignored if the adjustment command is sent
during /l'receive conversion period, which is already being or will be adjusted due to a prior adjustment
command. For example. if adjustment commands are issued during Transmit Conversion Periods A, B,
and C, the first two commands may cause Receive Conversion Periods A and B to be adjusted, while the
third receive adjustment command is ignored. The third adjustment command is ignored since it was issued
during Receive Conversion Period B, which already will be adjusted via the Transmit Conversion Period B
adjustment command.

I
I
I
I
j4-TRANSMIT CONV ......... TRANSMIT CONV . . . . TRANSMIT CONV.~
PERIOD A
PERIOD B
PERIOD C

FSRU
I

!4---RECEIVE CONVERSION PERIOD

F·SS

U
I

TEXAS

I
RECEIVE CONVERSION PERIOD B---~."I

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

TLC320441, TLC32044C
VOICE·BAND ANALOG INTERFACE CIRCUITS
asynchronous operation - more than one set of primary and secondary DX serial communication
occurring between two receive frame sync (see Ale DX Data Word Format section)
The T A, T A', TB, and control register information that is transmitted in the secondary communications
is always accepted and is applied during the ongoing transmit conversion period. If there is sufficient time
between t1 and t2, the TA, RA', and RB register information, which is sent during Transmit Conversion
Period A, will be applied to Receive Conversion Period A. Otherwise, this information will be applied during
Receive Conversion Period B. If RA, RA', and RB register information has already been received and is
being applied during an ongoing conversion period, any subsequent RA, RA', or RB information that is
received during this receive conversion period will be disregarded (see diagram below).

t,
PRIMARY

SECONDARY

PRIMARY

TRANSMIT

r---.......,

SECONDARY

PRIMARY

SECONDARY

TRANSMIT

,..---'"1

r-----CONVERSION---~"'----CONVERSION---"",,~,,----CONVERSION---~

PERIOD A

PERIOD B

PERIOD C

+-- RECEIVE CONVERSION_....*r--_ _ _ _ _ _ RECEIVE CONVERSION PERIOD B - - - - - -..
~
PERIOD A

...,.

TEXAS . "

INSTRUMENlS
POST OFfiCE BOX 655012 • DALLAS. TEXAS 75265

F·S9

TLC320441, TLC32044C
VOICE·BANO ANALOG .INTERFACE CIRCUITS
test modest
The following paragraph provides information that allows the TLC32044 to be operated in special test
modes. These test modes are used 'by Texas Instruments to facilitate testing 6f the device during
manufacturing. They are not 'intended to be used in real applications, however, they allow the filters in
the AID and DIA paths to be used'without using the AID and DIA converters.
In normal operation, the nonusable (NU) pins are left unconnected. These NU pins, are used by the factory
to speed up testing of the TLC32044 Analog Interface Circuit (AIC). When the device is used in normal
(non-test-mode) operation, the NU pin (pin 1) h~s an internal pull-down to - 5 V. Externally connecting
o V or 5 V to pin 1 puts the device in ,test-mode operation. Selecting one of the possible test modes is
accomplished by placing a particular voltage on certain pins. A description of these modes is provided
in Table 2 and Figures 1 and 2.
TABLE 2. LIST OF TEST MODES
TEST
PINS
5

DIA PATH TEST (PIN I to 5 V)
TEST FUNCTION
The low-pass switched-capacitor filter clock is brought

out to pin 5. This clock signal is normally internal.
No change from normal operation. The ~ signal is
brought out to pin 11.

The pulse that initiates the 01 A conversion is brought

The bandpass switched-capacitor filter clock is brought
out to pin 5. This clock signal is normally internal.
The pulse that initiates the AID conversion is brought
out here. This Signal is normally internal.
No change from normal operation. The EOOR signal is
brought out.

out here.
27 and 28

,
AID PA'tH TEST IPIN I to 0)
TEST FUNcnON

There are no test output signals provided on these pins.

The outputs of the AID path low-pass or bandpass filter
(depending upon control bit d2 - see AIC OX Data
Word Format section) are brou,ght out to these pins. If
the high-pass section is inserted, the output will have a
(sinx)/x droop. The slope of the droop will be determined
by the AOC sampling frequency, which is the high-pass
section clock frequency (see diagram of bandpass or
low-pass filter test for receive sectionl. These outputs
will drive small (30-pF) loads.

OIA PATH LOW-PASS FILTER TEST; PIN 13 (WORD/IiYT!) to - 5 V
15 and 16

TEST FUNCTION
The inputs of the OIA path low-pass filter are brought out to pins 15 and 16. The OIA input to this filter is removed.
If the (sin x)/x correction filter is inserted, the OUT + and OUT - Signals will have a flat response (see Figure 2). The
common-mode range of these inputs must not exceed ± O. 5 V.

t In the test mode, the AIC responds to the setting of Pin 13 to - 5 V, as if Pin 13 were set to 0 V. Thus, the byte mode is selected
for communicating between OSP and AIC. Either of the path tests (O/A or AIOI can be performed Simultaneously with the OIA low-pass
filter test. In this situation, Pin 13 must be connected to - 5 V, which initiates byte-mode communications.

F-90

TEXAS ""
INSTRUMENlS
POST OFFICE BOX 855012 •

DAl~AS"

TEXAS 75265

TLC320441. TLC32044C
VOICE·BAND ANALOG INTERFACE CIRCUITS

PIN 27 (POSITIVEI.
PIN 28 (NEGATIVElt

TEST CONTROL
(PIN 1 AT 0 VI
FILTER

M
U
X

AID

FIGURE 1. BANDPASS OR LOW-PASS FILTER TEST FOR RECEIVER SECTION
FILTER

M
U
X

(Sin xl/x
CORRECTION

..........-+1 u
X

........_

TEST CONTROL
(PIN 13 at -5 VI

PIN 16 (POSITIVEI.
PIN 15 (NEGATlvElt

FIGURE 2. LOW-PASS FILTER TEST FOR TRANSMIT SECTION
t All analog signal paths have differential architecture and hence have positive and negative components.

TEXAS •

INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS, TEXAS 75266

F-91

TLC320441. TLC32044C
VOICE·BAND ANALOG INTERFACE CIRCUITS
absolut~

maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage. VCC + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... - 0.3 V to 15 V
Supply voltage. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Output voltage. Vo .... , ........................................... -0.3 V to 15 V
Input voltage. V, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0 ..3 V to 15 V
Digital ground voltage .......................... . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Operating free-air temperature range: TLC320441 ......................... - 40°C to 85 °C
TLC32044C .................•......... O°C to 70°C
Storage temperature range ......................................... - 40°C to 125°C
Case temperature for 10 seconds: FN package ................................... 260°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds: N packal;le ............ 260°C
NOTE 1: Voltage values for maximum ratings are with respect to VCC - .

recommended operating conditions
PARAMETER

MIN

MAX

4.75
-4.75

NOM
5
-5

5.25
-5.25

Digital supply voltege. VDD (see Note 21
Digital ground voltage with respect to ANLG GND. DGTL GND

4.75

5.25

Reference input voltage. Vreflextl (see Note 21
High-level input voltage. VIH
Low-level input voltage. VIL (see Note 31

2
2
-0.3

Supply voltage. VCC + (see Note 21
Supply voltage. VCC _ (see Note 21

Load resistance at OUT + andlor OUT -. RL

VOO+0.3
0.8

300

Load capacitance at OUT + andlor OUT -. CL
MSTR CLK frequency (see Note 41

0.075

Analog input amplifier common mode input voltage (see Note 51

100
10.368
±1.5
19.2

AID or 01 A conversion rate

Conversion rate
Operating free-air temperature. T A

TLC320441
TLC32044C

-40
0

20
85
70

UNIT
V
V
V
V
V
V
V
!l
pF
MHz
V
kHz
kHz
·C

NOTES: 2. Voltages at analog inputs and outputs. REF. VCC +. and VCC _. are with respect to the ANLG GNO terminal. Voltages at
digital inputs and outputs and VDD are with respect to the DGTL GND terminal.
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet

• for logic voltage levels and temperature only.
4. The bandpass switched-capacitor filter (SCFI specifications apply only when the low-pass section SCF clock is 288 kHz and
the high-pass section SCF clock is 8 kHz. " the low-pass SCF clock is shifted from 288 kHz. the low-pass roll-off frequency
will shift by the ratio of the low-pass SCF clock to 288 kHz. If the high-pass SCF clock is shifted from 8 kHz. the high-pass
roll-off frequency will shift by the ratio of the high-pass SCF clock to 8 kHz. Similarly, the low-pass switched-capacitor filter
(SCFI specifications apply only when the SCF clock is 288 kHz. " the SCF clock is shifted from 288 kHz, the low-pass roll-off
frequency will shift by the ratio of the SCF clock to 288 kHz.
5. This range applies when (IN + - IN - I or iAUX IN + - AUX IN - I equals ± 6 V.

F-92

TEXAS .."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 15265

TLC320441, TLC32044C

VOICE·BAND ANALOG INTERFACE CIRCUITS
electrical characteristics over recommended operating free·air temperature range. VCC+ - 5 V.
VCC- - -5 V. VOO - 5 V (unless otherwise noted)
total device. MSTR elK frequency - 5.184 MHz. outputs not loaded
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

VDD ; 4_75 V. IOH ;

VOL

Low-level output voltage

VDD ; 4_75 V. IOL

ICC+ Supply current from VCC +
ICC- Supply current from VCC-

-300 p.A

MIN

Typt

0.4
40

TLC32044C

35
-40

TLC320441

-35

TLC32044C

Supply current from VDD

Vref

Internal reference output voltage

fMSTR ClK

= 5_ 1S4 MHz

7
3_3

Temperature coefficient of

UNIT
V

= 2 mA

TLC320441

IDD

MAX

2.4

V
mA
mA
mA
V

"'Vref internal reference voltage

250

ppm/·C

Output resistance at REF

100

receive amplifier input
PARAMETER

TEST CONDITIONS

MIN

A/D converter offset error (filters inl
CMRR

Common· mode rejection ratio at IN +, IN - ,

See Note S

or AUX IN+. AUX INInput resistance at IN +. IN-

or AUX IN+. AUX IN-. REF

Typt

MAX

UNIT
mV

100

transmit filter output
PARAMETER

TEST CONDITIONS

MIN

Output offset voltage at OUT + or OUT VOO

(single-ended relative to ANLG GND)
Maximum peak output voltage swing across

VOM

RL at OUT + or OUT - (Single-ended)
Maximum peak output voltage swing between

VOM

OUT + and OUT - (differential output)

RL 2: 300 G.
Offset voltage ; 0
RL 2: SOO

Typt

MAX

UNIT
mV

±3

±S

t All typical values are at T A = 25 ·C_
NOTE S: The test condition is a O-dSm. 1-kHz input signal with an S-kHz conversion rate.

TEXAS .".
INSTRUMENlS
POST OFFICE BOX 655012. DALLAS. TEXAS. 75265

F·93

TLC320441, TLC32044C

VOICE·BANDANALOG ,INTERFACE CIRCUITS
electrical characteristics over recommended operatingfree·air temper"ture range. VCC+ - 5 V.
VCC- - -5 V. VOO - 5 V (unless otherwise noted)
system distortion specifications. SCF clock frequency PARAMETER

28~

kHz
MIN

TEST CONDITIONS

Attenuation of second harmonic:; of
\
AID input signal

differential

Vin = - O. 1 dB to - 24 dB referred to V ref,
See Note 7

Attenuation of third and higher

single-ended

Vin

harmonics of AID input signal

differential

See Note 7

single-ended

= - O. 1 dB to
=

single-ended

Vin

DIA input signal
Attenuation of third and higher
harmonics of DIA input signal

differential

See Note 7

single-ended

Vin = - 0 dB to - 24 dB referred to V ref,
See Note 7

differential

MAX

70
62

- 24 dB referred to V ref,

Attenuation of second harmonic of

TYpt

70
65

70
'70

-0 dB to - 24 dB referred to Vref,

dB
dB

65
57

UNIT

AID channel signal-to-distortion ratio
TEST CONDITIONS

PARAMETER
Vin

Ay - 4'
MIN MAX

-6 dB to -0.1 dB

>58§

- 12 dB to - 6 dB

>58§

Vin = -24dBto-18dB
Vin - -30 dB to -24 dB
Vin = -36 dB to -30 dB
Vin = -42 dB to -36!1B
Vin - -48 dB to -42 dB
Vin = -54 dB to -48 dB

58
58'

Vin

=
=
=

Ay - 2'
MIN MAX

-18 d8 to -12 dB

Vin

AID channel signal-to-distortion ratio

Ay - l '
MIN MAX

(see Note 7)

UNIT

t All typical values are at ,.A = 25 DC.
t Av is the programmable gain of the input amplifier.
§ A value > 60 is over range and signal clipping occurs.

DIA channel signal-to-distortion ratio
PARAMETER

TEST CONDITIONS
IS88 Note 7)
Vin -

DIA channel signal-to-distortion ratio

-6 dB to -0.1 dB

Vi~ = - 12
Vin ~ -18
Vin = - 24
Vin = -30

MIN

MAX,

UNIT

dB to - 6 dB

dB to -12 dB

dB to - 18 dB

dB to -24 dB

Vin = -36 dB to -30 dB
Vin = -42 dB to -36 dB

38
32

Vin = -48 dB to -42 dB
Vin = -54 dB -48 dB

NOTE 7: The test condition is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to Vref). The load impedance for the DAC
is 600 Il.

,F·94

TEXAS

INSTRUMENTS
POST OFFICE BOX 655012 ··CALLAS. TEXAS 75265

TLC320441. TLC32044C
VOICE-BAND ANALOG INTERFACE CIRCUITS
electrical characteristics over recommended operating free-air temperature range, Vcc+ - 5 V,
Vcc- - -5 V, Voo - 5 V (unless otherwise noted) (Continued)
gain and dynamic range
PARAMETER

TEST CONDITIONS

Absolute transmit. gain tracking error while transmitting

- 48 dB to 0 dB signal range.

into 600

MIN

See Note 8
- 48 dB to 0 dB signal range.

Absolute receive gain tracking error

See Note 8

Typt

MAX

UNIT

±0.05 ±0.15

power supply rejection and crosstalk attenuation
PARAMETER

TEST CONDITIONS
Idle channel. supply signal

Vee + or Vee _ supply voltage

f=Ot030kHz

rejection ratio. receive channel

f = 30 kHz to 50 kHz

Vee + or Vee _ supply voltage

f=Ot030kHz

Typt

at DR (ADe output)
Idle channel. supply signal
at OUT+

Crosstalk attenuation, transmit-ta-receive (single-ended)

UNIT
dB

45
30

at 200 mV POp measured
f = 30 kHz to 50 kHz

MAX

at 200 mV POp measured

rejection ratio, transmit channel

(single-ended)

MIN

dB
45
80

t All typical values are at T A = 25 ·e.
NOTE 8: Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 dB relative to Vref).

TEXAS

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

F-95

nC32044•• nC32044C
VOICE·BAID AIALOG IITERFACE CIRCUITS
delay distortion
bandpass filter transfer function. SCF fclock - 288 kHz. input (IN +
lsee Note 9)
PARAMETER

TEST CONDITION

FREQUENCY

ADJUSTMENT ADDEND*

RANGE
1".50 Hz

Input signal

Filter gain

reference is 0 dB

- IN -) is a ± 3·V sinewave t

Kl x 0 dB

MIN

TYP§

MAX

-33

-29

-25

I = 100 Hz

Kl x - 0.26 dB

-4

-2

-1

I - 150 Hz to 3100 Hz
I = 3100 Hz to 3300 Hz

Kl x 0 dB

-0.25

0.25

Kl x 0 dB

-0.3

0.3

I = 3300 Hz to 3650 Hz

Kl x OdB

-0.5

0.5

I = 3800 Hz

Kl x 2.3 dB

-5

-3

-1

1= 4000 Hz

Kl x 2.7 dB

-20

-17

I l!: 4400 Hz

Kl x 3.2 dB

-40

I l!: 5000 Hz

Kl x 0 dB

-65

UNIT

-16

Iow'pass filter transfer function. SCF fclock - 288 kHz Isee Note 9)
PARAMETER

Filter gain

TEST CONDITION

Input signal
relerence is 0 dB

FREQUENCY

MIN

TYP§

MAX

I = 0 Hz to 3100 Hz

Kl x 0 dB

-0.25

0.25

I = 3100 Hz to 3300 Hz

Kl x 0 dB

0.3

Kl x 0 dB

-0.3
-0.5

I = 3300 Hz to 3650 Hz

0.5

1= 3800 Hz

Kl x 2.3 dB

-5

0
-3

1= 4000 Hz

Kl x 2.7 dB

-20

-17

-16

ADJUSTMENT ADDEND*

RANGE

-1

I l!: 4400 Hz

Kl x 3.2 dB

-40

I l!: 5000 Hz

Kl x 0 dB

-65

UNIT

serial port
PARAMETER

TEST CONDITIONS

MIN

TYP§

UNIT

High-lilvel output voltage

IOH -

VOL
II
Cj

low-leval output voltage

IOL=2mA

Input current

Input capacitance

Output capacitance

- 300 p.A

MAX

2.4

VOH

0.4
±10

V
p.A
pF
pF

t See lilter curves in typical characteristic•.
* Th8 MIN. TYP. and MAX specifications are given lor a 288-kHz SCF clock Irequency. A slight error in the 288-kHz SCF may result Irom
inaccuracies in the MSTR CLK frequency. resulting Irom crystal Irequency tolerances. If this Irequency error is less than 0.25%. the
ADJUSTMENT ADDEND should be added to the MIN. TYP. and MAX specilications. where Kl = 100. ((SCF Irequency - 288 kHzl/
288 kHz). For errors greater than 0.25%. see Note 10.
'
§ AU typical values are at T A = 25 ·C.
NOTES: 9. The lilter gain outside 01 the passbend is measured with respect to the gain at 1 kHz. The lilter gain within the passband
is measured with respect to the average gain within the passband. The passbands are 150 to 3600 Hz and 0 to 3600 Hz
101 the bandpass and low-pass lilters respectively.
10. For switched-capacitor filter clocks at Irequencies other than 288 kHz. the lilter response is shilted by the ratio 01 switchedcapacitor lilter clock frequency to 288 kHz.

,
\
fo96

, TEXAS'"
INSTRUMENlS
POST OFACE

sox 855012

• DAllAS, TEXAS 75265

TLC320441, TLC32044C
VOICE-BAND ANALOG INTERFACE CIRCUITS
operating characteristics over recommended operating free-air temperature range.

VCC- -

Vcc+ - 5 V.

-5 V. VDD - 5 V

noise (measurement includes low-pass and bandpass switched-capacitor filters)
PARAMETER

Tvpt

TEST CONDITIONS

I with Isin xlix

Transmit noise

OX input = 00000000000000, constant input code

without Isin xlix

325

MAX

UNIT

550

"V rms

425

"V rms
dBrncO

500

"V rms
dBrncO

MAX

UNIT

Receive noise Isee Note 111

300
18

Inputs grounded, gain = 1

timing requirements
serial port recommended input signals
MIN

PARAMETER
t~IMClKJ

Master clock cycle time

trlMClKI

Master -clock rise time

tflMClKI

Master clock fall time

Master clock duty cycle

25%

~ pulsa duration Isee Note 121

tsulOX)
thlOX)

OX setup time before SClKl
OX hold time after SClKl

75%

800

tc1SClKl/4

t All typical values are at TA = 25 DC.
NOTES: 11. The noise is computed by statistically evaluating the digital output of the AID converter.
12. ~ pulse duration is the amount of time that the reset pin is held below 0.8 V after the power supplies have reached
their recommended values.

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265

F-97

TLC320441, TLC32044C
VOICE-BAND ANALOG INTERFACE CIRCUITS
operating characteristics over recommended operating free-air temperature range. V cc + - 5 V.
vcc- - -5 V. VOO - 5 V (continued)
serial port - AIC output signals
PARAMETER
tclSCLKI

Shift clock (SCLK) cycle time

tf(SCLK)

Shift clock (SCLK) fall time

trlSCLKI

Shift

cloc~

MIN

MAX

UNIT
ns

380

(SCLK) rise time

Shift clock (SCLK) duty cycle

Delay from SCLKt to FSR/FSXI

tdICH-FHI

Delay from SCLK t to FSR/FSX t

td(CH-DR)

DR valid after SCLK t

tdw(CH-EL)

Delay from SCLKT to EODX/EODRI in word mode

tdw(CH-EH)

Delay from SCLKT to EODX/EODRT in word mode

t, EO OX

EODX fall

time

tflEODRI

EOPR fall time

tdbICH-ELI

Delay from SCLKT to EODX/EODRI in byte mode

100

tdbICH-EHI

Delay from SCLK T to eODX/EODRT in byte mode

100

tdICH-FLI

TABLE 2. GAIN CONTROL TABLE
(ANALOG INPUT SIGNAL REQUIRED FOR FULL-SCALE AID CONVERSION)
CONTROL REGISTER BITS

INPUT CONFIGURATIONS

Differential configuration
Analog input = IN + - IN-

·1

ANALOG INPUTt
±S V

AID CONVERSION
RESULT
full-scale

0
1

±3 V
±1.5 V

full-scale

0
Single-ended configuration

±3 V

half-scale

Analog input = IN + - ANLG GND

0
1

0
0

±3 V

full-scale

±1.5 V

full-scale

AUX IN+ - AUX IN-

AUX IN + - ANLG GND

full-scale

t In this example, Vref is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input
• not exceed 0.1 dB below full scale.

IN+-"""'~"''''

I-;-+--

IN - -'VV<..... . ,

AUX IN + -""',.".....-i
TO MUX.

R,b

TO MUX

Rfb

Rfb - R for dB - 1. d7 - 1
dB - O. d7 - 0
Rfb - 2Rfo.dS - 1. d7 - 0
Rfb - 4R for dB - O. d7 - 1

R,b - R for dB - 1. d7 dB - O. d7 Rfb - 2R for dB - 1. d7
Rfb - 4R lor d6 - O. d7

FIGURE 3. IN + AND IN - GAIN
CONTROL CIRCUITRY

F-9B

R
AUX IN - -""',..,....-1

1
01
- 0
- 1

FIGURE 4. AUX IN + AND AUX INGAIN CONTROL CIRCUITRY

. TEXAS'"

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

TLC320441, TLC32044C
VOICE· BAND ANALOG INTERFACE CIRCUITS
(sin xlix correction section
If the designer does not wish to use the on-board second-order (sin xlix correction filter. correction can
be accomplished in digital signal processor (DSPI software. (Sin xlix correction can be accomplished easily
and efficiently in digital signal processor (DSPI software. Excellent cqrrection accuracy can be achieved
to a band edge of 3000 Hz by using a first-order digital correction filter. The results. which are shown
below. are typical of the numerical correction accuracy that can be achieved for sample rates of interest.
The filter requires only seven instruction cycles per sample on the TMS320 DSPs. With a 200-ns instruction
cycle. nine instructions per sample represents an overhead factor of 1.4% and 1.7% for sampling rates
of 8000 Hz and 9600 Hz. respectively. This correction will add a slight amount of group delay at the upper
edge of the 300-3000-Hz band.

(sin xlix roll-off for a zero-order hold function
The (sin xlix roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for
the various sampling rates is shown in the table below.
TABLE 3. (sin xlIx ROLL-OFF
sin 11'" fIts
20109 - - f. (Hz)

" fIf.
(f - 3000 Hz)
(dB)

-2.64
-2.11
-1.44
-0.63
-0.35

7200

BOOO
9600
14400
19200

Note that the actual AIC (sin xlix roll-off will be slightly less than the above figures, because the AIC has
less than a 100% duty cycle hold interval.

correction filter
To compensate for the (sin xlix roll-off of the AIC. a first-order correction filter shown below. is
recommended.
U(i+ 1)

l - - - - - - - - - - - e - - + V ( i + 11

The difference equation for this correction filter is:
Yi+1 = p2(1-p11 (ui+11+p1 Yi
where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
IH(fll 2 =

p22 (1-p1)2
1 - 2p1 cos(2 ". flfsl + p1 2

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

F-99

TLC320441. TLC32044C
VOICE-BAND ANALOG INTERFACE CIRCUITS
correction results
Table 4 below shows the optimum p values and the corresponding .correction results for 8000-Hz and
9600-Hz sampling rates.
TABLE 4
ERROR (dBI
f. - BOOO Hz
pl - -0.14813
p2 - 0.9888
-0.099
-0.089
-0.054
-0.002
0.041
0.079
0.100
0.091
-0.043
-0.102

f (Hzl

300
600
900
1200
1500
1800
2100
2400
2700
3000

ERROR (dBI
f. - 9600 Hz

pl - -0.1307
p2 - 0.9951
-0.043
-0.043
0
0
0
0.043
0.043
0.043
0
-0.043

TMS320 software requirements
The digital correction filter equation can be written in state variable form as follows:
Y = klY +k2U
where k 1 equals p 1 (from the preceding page). k2 equals (1 - p 1)p2 (from the preceding page). Y is the
filter state, and U is the next 1/0 sample. The Coefficients k 1 and k2 must be represented as 16-bit integers.
The SACH instruction (with the proper shift) will yield the correct result. With the assumption that the
TMS320 processor page pointer and memory configuration are properly initialized, the equation can be
executed in seven instructions or seven cycles with the following program:
ZAC
LT K2
MPY U

LTA Kl
MPY Y
APAC
SACH (dma). (shift)

F-l00

TEXAS

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75285

TLC32D441, TLC32D44C
VOICE-BAND ANALOG INTERFACE CIRCUITS
byte-mode timing
~~trISClK)

--.!O-tflSClKI
SHIFT ClK

I
I

0_8 V

tdICH-FLI~ ~

)

I
~~tdICH-FHI

08 V

I
~ ~tdICH-Fl)

I
tdICH-FH~

10-

= _______
I'
~~,----~12V
08V~~I____~f~!------~I~
,

I;.,'

I
I
I ~ ~~dICH-ORI

DR ___

~0~1~5____~~--~---0~8~------~~~0-1----0-0~:~--~
1
I
tsuIOX).....

~,1(~~~~I}-_~O~O~N!.!T~C~A~R~E~_-(~~~~~
~~ 09
08
07
06~
1

~
EQDR,

I
I

tdbICH-EH~

---Jr-

I.-thIO,..X_I_ _ _--t--,!"-tdbICH-Ell

jo-

t"'~O"'8'_V'___ _ _ _ _ _ _ _ _ _~, ~,_ _ _ _ _ _

roox----------fJP

word-mode timing
to-----*- tclSClK I

,
,

SHIFT ClK

2 V

08 VI

08 V

_ _ _~
____r - :
FSX. FSR

tdICH-FH~ ~

I
1~2V
+--+,
- - - - 1 ~ _ _ _ _ _ _ _.lJr - I
I i

---

08 V\-'"---_ _ _ _

08 V

(l-

--+\

DO:

r-td(CH-ORI

OR _ _...;0:..1.:...5~_..J~iDD 01

tsulOXI~ 10-

OX----(~0~1~5JG~~'~~(£~)J0~1~1~
,

jo-thlOXI

tdw(CH-ELr--i ~

----------------~fl-I--~~--

____'

---+I

io-tdw(CH-EHI

08 v'L-.J'2 V

FIGURE 5_ SERIAL PORT TIMING

TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012. DALLAS, TeXAS 75265

F-101

TLC320441, TLC32044C
YOICE·BAND ANALOG INTERFACE CIRCUITS

FSX

TMS32010
SN74LS299

....

OEN

....

AO/PAO

Al/PAl

A2/PA2

f--

YO f0-

~ 1.5

(!l

-60

SCF clock f - 288 kHz
TA = 25°C
Input = ± 3-V sinew ave

-70
-80

0.5

1.5

2.5

0.5
r.

3.5

4.5

0.5

1.5

I"r-3.5

4.5

FIGURE 9

FIGURE 8
AIC RECEIVE·CHANNEL BANDPASS FILTER

AIC RECEIVE-CHANNEL HIGH-PASS FILTER
20

20
10

SCF clock f - 8 kHz
TA = 25°C
Input -. ± 3-V sinewave

-10

!g ~10

" -20
cD

g' -40
:!!

]

Low-pass SCF clock f ~ 288 kHz
High-pass SCF clock f - 8 kHz
TA - 25°C
Input - ± 3-V sinewave

-60
-70

0.5

1.5 2 2.5 3 3.5
Frequency - kHz

-20

·2

~ -30

-50

l\
\

-30

-80

2.5

Normalized Frequency-kHz x SCF Clock Frequency
288 kHz

"·2a

/
-'

-40
r-

4.5

-50
-60

50 100 150 200 250 300 350 400 450 500

No~malized Frequency-kHz x AID Conversion Rate
8 k samplesls

FIGURE 10
FIGURE 11

. TEXAS ~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

F-103

TlC320441, TlC32044C
VOICE·BAND ANALOG INTERF~CE CIRCUITS
TYPICAL CHARACTERISTICS
AIC RECEIVE CHANNEL BANDPASS FILTER

2.5

.. 2.0
E
I
>

..'"

::ii

1.5

I':r-

0.5

0.0
0.5

2.5

I':

a.
::s
2 1.0

1°

SCF clock f - 288 kHz
4.5 f-TA _ 25°C
4 f-Input a ± 3-V sinew ave
I
3.5

..,m
..,::sI

~ 1.5

0.5

AIC (SIN X)/X CORRECTION FILTER
5

Low-pass SCF clock f - 288 kHz
High-pass SCF clock f - 8 kHz
f-..TA - 25°C
Input - ± 3-V sinewave

1.5 2 2.5 3 3.5
Frequency - kHz

4.5

0.5

/
1.5

2.5

3.5

4.5 5

Normalized Frequency-kHz" SCF Clock Frequency
288 kHz

FIGURE 12

FIGURE 13
(SIN X)/X CORRECTION FILTER
6

I I

..,m
..,::sI

L-

.......-

t-.

.'"

::ii -2

-6

~Ttorn rr
o

0.5

1 1.5

100
90

..,m

error

rerter 3

3.5

$
iii
c

4.5

iii
5

V /

20
10

Normalized Frequency-kHz" SCF Clock Frequency
288 kHz

': 50

FIGURE 14

-40 -30 -20 -10
o
Input Signal Relative to Vref-dB

FIGURE 15

F-104

-- -

GAIN - 1X-

GAIN - 4X

f'.. ~

r r "'-

oil
cr:

-1\

i'-- t-......

2 2.5

1-kHz input signal
8-kHz converton rete

I
I
D/A converter (sin x)/x

-4

i.-

fVi

(sin xl/x
correcti/

AID SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL

TEXAS . "

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TLC320441, TLC32044C
VOICE·BAND ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
AID GAIN TRACKING
(GAIN RELATIVE TO GAIN AT 0 dB INPUT SIGNAL)
0.5 , . . - - - , - - , - - - - r - - , - - - - r - - - - - ,
1-kHz input signal
0.4 8-kHz conversion rate--+----+-----i

0.31---+---+--1--+---+-----1
0.2 f - - + - - t - - + - - t - - + - - - - - i

CD
."

0.1 f----+--t--+--t--+-----i

:;;

Of---:::P-=r---t---t--+-----i

t!:
I:

·iii

0.1 f - - + - - t - - + - - t - - + - - - - - i

~ -0.2f---+---1--+---+--1-~

-0.31--+--t---+--t---+-----1
- 0.4 1 - - + - - t - - - + - - t - - - + - - - - - 1
_0.5L---L-~--i---L--L--~

-50

-40

-30

-20

-10

Input Signal Relative to V ref - dB

FIGURE 16
DIA CONVERTER SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL LEVEL
100 r-----"-.,----~____,__
1-kHz input signal into 600 !l
-90 8-kHz Iconversion rate

r--

CD
."

..,0

--/

""\

lii

0 40

$
"iii 30

c
Ol
iii 20

- 50 - 40

- 30

- 20

- 10

Input Signal Relative to V ref - dB

FIGURE 17

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TeXAS 75265

F-105

TLC320441. TLC32044C

VOICE·BAND ANALOG INTERFACE· CIRCUITS
TYPICAL CHARACTERISTICS
DIA GAIN TRACKING
(GAIN RELATIVE TO GAIN
AT 0 dB INPUT SIGNAL LEVEL)
0.5
0.4

AID SECOND HARMONIC DISTORTION
vs
INPUT SIGNAL
- 100

1-kHz input signal into 600 {)
8-kHz conversion rate

1-kHz input signal

..,
i"c
CD

:g
~c

0.3

0.2

.S! -70
t:

-80

0.1

~-60

J..-/

r---

'2
~

......... V

-0.1

'iii

-50
-40

Cl -0.2

-0.3

---

-90 8-kHz conversion rate

.., -30
c
o

"'"

-20

-0.4
-0.5
-50

-10
-40
-30
-20
-10
o
Input Signal Relative to V ref - dB

- 50

o
- 40
- 30 - 20
- 10
Input Signal Relative to V ref - dB

FIGURE 18

FIGURE 19
DIA SECOND HARMONIC DISTORTION
vs
INPUT SIGNAL

-100
1-kHz input signal into 600 II

-90 8-kHz conversion rate
CD

-80

o -70

'2
..~

-60

t----

........

-50
-40

.., -30
c

-20
-10

-50

-40
-30
-20
-10
o
Input Signal Relative to Vref - dB

FIGURE 20

F-106

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265

TLC320441. TLC32044C
VOICE·BAND ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
AID THIRD HARMONIC DISTORTION
vs

INPUT SIGNAL
-100,----,----,-----,----,----,---,
11.kHz input signal

- 90 B-kHz conversion rate

! -B0r-

°E

V "-

1--

of - 7
~ -60
i5
o~ 50 I

---+- -+-----1

r-"'"

r--

-40 1--

::r: -30
'E

-_.

.- -

1: -20 r----- .-

-10

-50

___ -'-__---'____ -'-__---'____....J

-40

-30

-20

-10

Input Signal Relative to V ref - dB

FIGURE 21
DiA THIRD HARMONIC DISTORTION
vs

INPUT SIGNAL
-100
1-kHz input signal into 600 0

-90 B-kHz conversion rate
!!l-BO
I

6 -70

'§.. -60 f - - -

i5
u

V"\.

100-

I--

------

-50 r---- - .

§ -40

::r: -30
'E
~ -20
-10

- 50

- 40

- 30

- 20

- 10

Input Signal Relative to V ref - dB

FIGURE 22

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265

F-107

TLC320441. TLC32044C
VOICE·BAND ANALOG INTERFACE CIRCUITS
TYPICAL APPLICATION INFORMATION
TlC32044

TMS32020/C25
ClKOUT I-_f---I MSTR ClK
FSX

FSX

1----------......- + 5 V

REF
ANlG GND I-.-~.....-

DX~_--IDX

FSR ~_f---I FSR
DR
DR
ClKR

VCC+

......- - -..

VCC-~~4_----~-

SHIFT ClK

ClKX

C - 0.2

~F.

CERAMIC

FIGURE 23. AIC INTERFACE TO THE TMS32020/C25 SHOWING DECOUPLING CAPACITORS AND
SCHOTTKY DIODEt
VCC

R
.....-

.....- -.....- - - - - 3 - V OUTPUT

Tl431~-"""

FOR:

VCC - 12 V. R - 7200 II
VCC - 10 V. R - 5600 II
VCC - 5 V. R - 1600 II

FIGURE 24. EXTERNAL REFERENCE CIRCUIT FOR TLC32044
tThomson Semiconductors

F·108

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265

TLC0820A, TLC0820B, ADC0820B, ADC0820C
Advanced Lin CMOS" HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
D2873. SEPTEM8ER 1986-REVISED FEBRUARY 1989

•

ALL TYPES ... OW OR N PACKAGE
TLC0820_M ... J PACKAGE
ITOP VIEWI

Advanced LinCMOS" Silicon-Gate
Technology

•

8-Bit Resolution

•

Differential Reference Inputs

•

Parallel Microprocessor Interface

•

Conversion and Access TIme Over
Temperature Range
Write-Read Mode . . . 1.18 p.s and 1.92 p's
Read Mode ... 2.5,.s Max

•

No External Clock or Oscillator Components
Required

•

On-Chip Track-and-Hoid

•

Low Power Consumption ... 50 mW Typ

•

Single 5-V Supply

•

TLC0820B is Direct Replacement for
National Semiconductor ADC0820B/BC and
Analog Devices AD7820UC/U;
TLC0820A is Direct Replacement foJ'
National Semiconductor ADC0820C/CC and
Analog Devices AD7820K/BIT

ANLGIN
(LSB) DO
01
02
03
WR/ROY
MODE
RO
INT
GNO

Vee
Ne
OFLW
07 (MSB)
06
05
04
es
REF+
REF-

TLC0820_M ... FK PACKAGE
TLC0820_1. TLC0820_C ... FN PACKAGE
AOC0820_CI. AOC0820_C ... FN PACKAGE
ITOP VIEWI
iil~

~C)

-...JU
0 2 UU

00«>2
3

description

1 2019

The TLC0820A. TLC0820B. ADC0820B. and
ADC0820C are Advanced LinCMOS" B-bit
analog-to-digital converters each consisting of
two 4-bit "flash" converters. a 4-bit digital-toanalog converter. a summing (errorl amplifier.
control logic. and a result latch circuit. The
modified "flash" technique allows low-power
integrated circuitry to complete an B-bit
conversion in 1.18 p.S over temperature. The onchip track-and-hold circuit has a 100 ns sample
window and allows these devices to convert
continuous analog signals having slew rates of
up to 100 mV/p.s without external sampling
components. TTL-compatible three-state output
drivers and two modes of operation allow
interfacing to a variety of microprocessors.
Detailed information on interfacing to most
popular microprocessors is readily available from
the factory.

07 (MSB)
06
05

8
9

II-~i3:t:tU
+ It/)
0

cr:cr:

NC - No internal connection

The M-suffix devices are characterized for operation over the full military temperature range of - 55°C
to 125°C. The I-suffix devices are characterized for operation from - 40°C to 85 DC. The C-suffix devices
are characterized for operation from O°C to 70°C. See Available Options.

Advanced LinCMOS is a trademark of Texas Instruments Incorporated.

PRODucnOI DATA dec..._ CftIIiIo illfamotiln
e.rntII "' of ..... iclli•• doto. PnoIIctI CMfmI to
.,ocifledi....... tho tlrlll If T_ ' - _
.to.d... w.mnty. P.....otian ~ .... lit
_.ril, inclado toIIi•• of .u ...........

TEXAS .",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

F-l09

TLC0820A. TLC0820B. ADC0820B. ADC0820C
Advanced LinCMOS™ HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
AVAILABLE OPTIONS
SYMBOLIZATIONt
PACKAGE
SUFFIX

DEVICE
TLC0820AC
TLC0820AI
TLC0820AM

OW, FN, N
OW, FN, N
OW, FK, J, N

TLC0820BC
TLC0820BI
TLC0820BM

OW, FN, N
OW, FN, N
OW, FK, J, N

AOC0820BC

OW, FN, N
OW, FN, N

AOC0820BCI
AOC0820CC
AOC0820CCI

OPERATING
TEMPERATURE

TOTAL
UNADJUSTED

RANGE
OOC to 70°C

ERROR
± 1 LSB

-40°C to 85°C
-55°C to 125°C

± 1 LSB
± 1 LSB

OOC to 70°C
-40°C to 85°C

±O.5 LSB
±O.5 LSB

-55°C to 125°C
OOC to 70°C

±O.5 LS8
±O.5 LSB

-40°C to 85°C

±O.5 LSB
± 1 LSB

OW, FN, N

O°C to 70°C
-40°C to 85°C

OW, FN, N

± 1 LSB

t In many instances, these ICs may have both TLC0820 and AOC0820 labeling
on the package.

functional block diagram
REF+
REF-

4-BIT FLASH
ANALQG-TODIGITAL
CONVERTER
(4 MSBs)

(121
(11)

4
~

4-BIT
DIGITALTO-ANALOG
CONVERTER

~ OFLW
--E.!. DO (LSB)

f--

~ 01
OUTPUT
LATCH
AND
3-STATE
BUFFERS

~ 02
~ 03

~ 04

~ 05
i....-

i....-

ANLG IN

MOOE
WR/ROY
CS
RO

F-110

(1)

-1
+1

'---

4-BIT FLASH
ANALOG-TODIGITAL
CONVERTER
(4 LSBs)

~ 06
~ 07 (MSB)

(7)
(6)

TIMING
ANO
CONTROL

(13)
(8)

TEXAS . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

---..!!L

DIGITAL
OUTPUTS

TLC0820A, TLC0820B, ADC0820B, ADC0820C
Advanced LinCMOSTM HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
PIN
NAME

ANLG IN

DESCRIPTION

NUMBER

Analog input

Three·state data output. bit 1 ILSB)

Three-state data output. bit 2

Three·state data output. bit 3

Three·state data output. bit 4

Three·state data output. bit 5

Three-state data output. bit 6

Three·state data output. bit 7

Three-state data output. bit 8 IMSB)

GND

Ground

fiiiT

This input must be low in order for RD or WR to be recognized by the ADe.

In the WRITE·READ mode. the interrupt output. INT. going low indicates that the internal count·down delay time.
tdlint). is complete and the data result is in the output latch. tdlint) is typically 800 ns starting after the rising
edge of the

Wfi input Isee operating characteristics and Figure 3). If RD goes low prim to the end of tdlint).

INT goes low at the end of tdRIL and the conversion results are available sooner Isee Figure 2). INT is reset by the
rising edge of either RD or es.
MODE

Mode~selection

input. It is internally tied to GND through a SO-"A current source, which acts like a pull-down

resistor.

READ mode: Occurs when this input is low.
WRITE-READ mode: Occurs when this input is high.
Ne

No internal connection

OFLW

Normally the OFLW output is a logical high. However. if the analog input is higher than the VREF +. OFLW
will be low at the &nd of conversion. It can be used to cascade 2 or more devices to improve resolution (9
or 10·bits).

In the WRITE-READ mode with es low. the 3·state data outputs DO through D7 are activated when RD goes
low. RD can also be used to increase the conversion speed by reading data prior to the end of the internal

count·down delay time. As a result. the data transferred to the output latch is latched after the falling edge of RD.
In the READ mode with es low. the conversion starts with RD going low. RD also enables the three-state
data outputs upon completion of the conversion. The ROY output going into the high-impedance state and
.tNT gOing low indicates completion of the conversion.

REF-

This input voltage is placed on the bottom of the resistor ladder.

REF+

This input voltage is placed on the top of the resistor ladder.

Vee

WR/RDY

Power supply voltage
In the WRITE-READ mode with es low. the conversion is started on the falling edge of the WR input signal.
The result of the conversion is strobed into the output latch after the internal count-down delay time, td(intl,

provided that the RD input does not go low prior to this time. tdlint) is approximately 800 ns.
In the READ mode. RDY Ian open-drain outputl will go low after the falling edge of CS. and will go into the
high-impedance state when the conversion is strobed into the output latch. It is used to simplify the interface
to a microprocessor system.

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

F-111

TLC0820A. TLC0820B. AI;JC0820B.· ADC0820C
Advanced linCMOS'" HIGH·SPEEDS·Bll ANALOG·lO·DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
TLC0820~

Supply voltage, VCC (see Note 1 t
Input voltage range, all inputs (see Note 1 t
Output voltage range, all outputs (see Note 1 t
Operating free-air temperature range

Storage temperature range

TLC0820_1
TLC0820_C
ADC0820_CI ADC0820_C
10

UNIT

10
-0.2 to

-0.2 to

VCC+O.2
-0.2 to

VCC+0.2
-0.2 to

VCC+ 0 .2
-55 to 125
-65 to 150

VCC+ 0 .2
-40 to 85
-66 to 150

VCC+0.2
to 70
-65 to 150

260

Case temperature for 60 seconds: FK package

260

Case temperature for 10 seconds: FN package
Lead temperature 1,6 mm (1/16 inch) from case

DC
DC

300

for 60 seconds: J package
Lead temperature 1,6 mm (1/16 inch) from case
for 10 seconds: OW or N package

260

NOTE 1: All voltages are with respect to network ground terminal, pin 10.

recommended operating conditions
TLC0820_1
ADC0820_CI

TLC0820_M

MIN
4.5
-0.1

Supply voltage, VCC
Analog input voltage
Positive reference voltage, VREF +

VREFGND

Negative reference voltage, VREF-

High-level inpu VCC '= 4.75 V ~,Wf!IRDY,
to 5.25 V
MODE
voltage, VIH

AD in

write-read mode,

tdWR (see Figure 2)
Write-pulse duration in write-read mode,

(see Figures 2, .3, and 4)
Operating free-air temperature, T A

F-112

tww

MIN
4.5
-0.1

NOM
5

Vee

VREFVREF+ GND

Vee +0.1.
Vce

Vee

MAX
8

VREFVREF+ GND

3.5

3 ..5

3.5

Low-level input VCC = 4.75 V ~, iiiiR/RDY, RD
to 5.25 V
MODE

Delay time from Wf! to

MAX
8
Vee+ O.1

voltage, VIL

Delay to next conversion, td(NC)
(see Figures I, 2, 3, and 4)

NOM
5

TLC0820_C
ADC0820 C
MIN NOM MAX
4.5
5
8
-0.1
Vee+ O.1
VREF+

UNIT
V
V
V
V
V

0.8

1.5

500

.ns

0.4

,..

0.5
-55

0.5

,.s

125

-40

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TLC0820A, TLC0820B, ADC0820B, ADC0820C
Advanced LinCMOS™ HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
electrical characteristics at specified operating free·air temperature,
PARAMETER
~

Vee
VOH

VOL

High-level output voltage

LOW-level output voltage

Any D, INT, or OFLW

4.75 V,
-360

10H

Vce

4.75 V,

Any D, OFLW, INT,

10H ~ -10 ~A
Vec ~ 5.25 V,

or WR/RDY

10L

High-level input current

IlL

Off-state (high-impedance

10Z

state) output current

VIH

or MODE

VIL

5 V

Any D, OFLW, INT,

Supply current

I nput capacitance

Output capacitance

Typt

0.4
0.34

25°C
0.005
0.1

-1

0.1

0.3

-0.1

-0.3

5 V

Full range

-3

Full range

-6

25°C

-7.2

Full range

-4.5

25°C

-5.3

Full range

1.25

Full range

and RD at 0 V

25°C

Any digital

Full range

ANLG IN
Any digital

Full range

7
8.4

es, WR/RDY,

-0.3

25°C

3
0.3

25°C

Any D or OFLW
~

170

-3

25°C
Full range
Full range

Full range

0.3

25°C

at 5 V,

-0.005

Full range

200

Full range

UNIT

25°C

MAX

Full range

25°C

INT

ICC

4.6

5 V

Rref

4.5

25°C

Any D or WR/RDY

Analog input current

Reference resistance

Full range

25°C

or WR/RDY
lOS

2.4

Full range

es, WR/RDY, RD,

Short-circuit output current

MIN

Full range

'C'S at 5 V,
II

V (unless otherwise notedl

Full range

WR/RDY
MODE

Low-level input current

= 5

Full range

1.6 rnA

es or RD
IIH

Vee

TEST CONDITONS

1.4

14
rnA

-12

-9
6
2.3

5.3

7.5

15
5

kG
rnA
pF

45
5

t All typical values are at TA ~ 25°C.

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

F-113

TLCOB20A, TLC0820B, ADC0820B,ADC0820C
Advanced LinCMOSTM HIGH·SPEED 8·BITANALOG·TO·DIGITAl
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
operating characteristics, Vee - 5 V, VREF +
(unless otherwise noted)
PARAMETER

TEST CONDITIONS
MIN

Supply' voltage
kSVS

VCC

sensitivity
1'otal unadjusted error t

Aead mode
tconvR

tdlint)
taA

5 V ± 5%. TA

MODE pin at 0 V. TA

MIN to MAX

Internal count-

MODE pin at 5 V.

down delay time

See Figures 3 and 4

Access time from ADI

MODE pin at 0 V. See Figure 1

50 pF.

20 ns, TA

TLC0820B

TLC0820A

ADC0820B

ADC0820C

TYP

MAX

±1/16

±1/4

MIN to MAX

MODE pin at 0 V. See Figure 1

conversion time

0, tr

5 V, VREF-

MIN

UNIT

TYP

MAX

±1/16

±1/4

LSB

1/2
1.6

2.5

1.6

2.5

,..

800

1300

800

1300

tconvR tconvR

+20

+50

MODE pin at 5 V.

15 pF

190

280

190

'280

210

320

210

320

taAl

Access time from ADI

tdWA < td/int).
See Figure 2

100 pF

MOD"e pin at 5 V.

15 pF

120

taA2

Access time from RDl

tdWA > td/int)
See Figure 3

100 pF

150

taiNT

Access time from

MODE pin at 5 V. See Figure 4

tdis

Disable time from ADt

CL = 10 pF.
AL = 1 kO.
See Figures 1. 2. 3. and 5

Delay time from

MODE pin at 0 V.

tdADY

~I to ADYI

See Figure 1

100

Delay time from
ADt to INn

CL = 50 pF.
See Figures 1. 2. and 3

125

2'25

125

225

Delay time from

MODE pin at 5 V.

200

290

200

290

175

270

175

270

tdAIH
tdAIL
tdWIH

ADI to

iiiiTI

tdWA

50 pF.

< tdlint).

See Figure 2

Delay time from

MODE pin at 5 V.

WAt to 'iN'i't

See Figure 4

50 pF.

Slew rate tracking

0.1

t Total unadjusted error includes offset, full-scale, and linearity errors.

F-114

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 66501.2 • DALLAS. TEXAS 76265

0.1

V/~s

TLC0820A, TLC0820B, ADC0820B, ADC0820C
Advanced LinCMOSTM HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
PARAMETER MEASUREMENT INFORMATION

-'!
'---___I

" \ __

cs } ' -_ _ _ _ _ _
I

~----

j.-IdINCI---!

WR/ROY

WITH

--t
INT

r,:

tdRIH

III - - - - - - .

-,;:

j4--tconVR~

00-07

~XTERNAL PULL-UP

I
I

------r-------{!I;..._-:-I.....,.}-------~taR____+!

-.I,

"j.-Idi.

FIGURE 1. READ MODE WAVEFORMS (MODE PIN LOW)

cs~
WR/ROY

1.. ____ _

tww~
~------.\r:"
tdWR

~
I

.1"

INT
tdUntl

00:07

1
It

tww:-\.--.I

__-.J-,'7',-

WR/ROY

~-----------

tdlNCI.....j

"L.....fr---

I tdRIL -.I t+I
I I

I _______\~__C

cs ::\

1
I

'---if
-.j I--

1.1

--------:- td(int)l

CS LOW - - - - - - - - - - - - -

WR/ROY

INT

00-07

---~.

_ _ _ _ _ _J

......-~

}--

'-~~

FIGURE 4. WRITE·READ MODE WAVEFORMS
(STAND·ALONE OPERATION. MODE PIN HIGH. AND RD LOW)

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012

~ DALLAS, TeXAS 75265

F-115

TLC0820A. TLC0820B. ADC0820B. ADC0820C
Advanced LinCMOS'" HIGH·SPEED 8·BIT ANALOG·TO,DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
PARAMETER MEASUREMENT INFORMATION
VCC

TLC0820
OR

-+Jtr !4=

ADC0820

INPUT
Dnt-.....-

. . .-

DATA
OUTPUT

VCC GND

Z~~%
110%

-+I

GND
CL

VOH

1 kll
DATA
OUTPUTS

tdis 14-I

~O%
""-

GND------------~

t,-20ns
VCC

CL - 10 pF

-+ltrj4-

TLC0820
OR
ADC0820
INPUT

1 kll
RD

DATA
Dnt-......- . - - OUTPUT
GND

VCC~-...I...1
/
90%
/50%
GND

/10%

VCC

-..tdlsl4I

DATA

OUTPUTS VOL - - 1 1 0 %

t,-20ns
On - DO ... D7
VOLTAGE WAVEFORMS

TEST CIRCUIT

FIGURE 5. TEST CIRCUIT AND VOLTAGE WAVEFORMS

TEXAS . "

F·116

INSTRUMENTS
PO~T

OFFICE BOX 6~50'2 • DALLAS. TeXAS 75265

•

TLC0820A, TLC0820B, ADC0820B,ADC0820C
Advanced LinCMOSTM HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
PRINCIPLES OF OPERATION
The TLC0820A, TLC0820B, ADC0820B and ADC0820C each employ a combination of "sampled-data"
comparator techniques and "flash" techniques common to many high-speed converters. Two 4-bit "flash"
analog-to-digital conversions are used to give a full 8-bit output.
The recommended analog input voltage range for conversion is -0.1 V to VCC +0.1 V. Analog input signals
that are less than VREF _ + Yo LSB or greater than VREF + - Yo LSB convert to 00000000 or 11111111
respectively. The reference inputs are fully differential with common-mode limits defined by the supply rails.
The reference input values define the full-scale range of the analog input. This allows the gain of the ADC to
be varied for ratiometric conversion by changing the VREF + and VREF..., voltages.
The device operates in two modes, read (only) and write-read, which are selected by the MODE pin (pin 7).
The converter is set to the read (only) mode when pin 7 is low. In the read mode, the WR/RDY pin is used
as an output and is referred to as the "ready" pin. In this mode, a low on the "ready" pin while CS is low
indicates that the device is busy. Conversion starts on the falling edge of RD and is completed no more than
2.5 ,.s later when INT falls and the "ready" pin returns to a high-impedance state. Data outputs
also change from high-impedance to active states at this time. After the data is read, RD is taken high, INT
returns high, and the data outputs return to their high-impedance states.
The converter is set to the write-read mode when pin 7 is high and WR/RDY is referred to as the "write" pin.
Taking CS and the "write" pin low selects the converter and initiates measurement of the input signal.
Approximately 600 ns after the "write" pin returns high, the conversion is completed. Conversion starts on
the rising edge of WR/RDY in the write-read mode.
The high-order 4-bit "flash" ADC measures the input by means of 16 comparators operating simultaneously.
A high precision 4-bit DAC then generates a discrete analog voltage from the result of that conversion. After
a time delay, a second bank of comparators does a low-order c'onversion on the analog difference between
the input level and the high-order DAC output. The results from each of these conversions enter an 8-bit latch
and are output to the three-state buffers on the falling edge of RD.

TEXAS •

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

F-117

TLC0820A, TLC0820B, ADC0820B, ADC0820C
Advanced LinCMOSTM HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING' MODIFIED "FLASH" TECHNIQUES
TYPICAL APPLICATION DATA

~cs

(131

WI(

(61

rt>
"p

f""»!!L

(21

(31

(41

BUS 03

(51

(141

(151

(161

(171

(201
Vee f---5V
111
Wii/ROY ANLG
IN
es

ANLGIN

RD
DO

MODE

REf+

~5V
1121

02
03

fO'

04
05

REF-

(111

fo.

06
07

08
OFL

(101

(181

r.-.-.rth

r.-

I~~I

r.-.t-td(READY)

I.I ,II - - - - - . . .

ld(READYI-M+I,
READY

~I__-JI

~>-------------<{

!........ldIREADYI

'--I

\11..___________

~tdi.
I
OUT

}>----------

COMMAND TO
INITIATE CONVERSION

(REQUIRES 105 CLOCK CYCLES'

FIGURE 3. TIMING DIAGRAM

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

F-125

TLC122SA, TLC1225B
.SELF-CALIBRATING 12-BIT~PLUS-SIGN UNIPOLAR OR BIPOLAR
ANALOG-TO-CONVERTERS
PARAMETER MEASUREMENT INFORMATION
DGTl

'
,VCC
f u ' DATA
RD
OUTPUT

"':"

-=-

DGTl
VCC

VOH _ _ _

""!!I1ga~i.

:s::.

DATA OUTPUT
GND---

,....--1'1--.. RL

RD,

, ':' J

DATA
OUTPUT

GND

Vcc--DATA OUT
VOL---""!

FIGURE 4. LOAD CIRCUITS AND WAVEFORMS
/'

PRINCIPLES OF OPERATION

power-up calibration sequence
Power-Up calibration is not automatic and calibration IS initiated by writing control words to the six least
significant bits of the data bus. If addressed or initiated, conversion can begin after the first clock cycle.
However, full AID conversion accuracy is not established until after internal capacitor calibration.

conversion start sequence
The writing of the conversion command word to the six least significant bits of the data bus, when .either CS or
WR goes high, initiates the conversion sequence.

analog sampling sequence
Sampling of the input signal occurs during clock cycles 3thru 10 of the conversion sequence.

completed AID conversion
When INT goes low, conversion is complete and the ND result can be read. A new conversion can begin
immediately. The AID conversion is complete at the end of clock cycle 27 of the conversion sequence.

aborting a conversion In process and beginning a new conversion
If a conversion is initiated while a conversion sequence Is in process, the ongoing conversion will be aborted
and a new conversion sequence will begin.

reading the conversion result
When both CS and RD go low, all 13 bits of conversion data are output to the 1/0 bus. The format of the output
is extended sign with 2's complement, right justified data. For both unipolar and bipolar cases, the sign bit
D12 is low if VI+ - VI_ is positive and high ifVI+ - VI_ is negative.

F-126

TEXAS

,41

INSTRUMENTS,
POST OFFICE BOX 855012 -,DALLAS. TEXAS 75265

TLC1225A, TLC1225B
SELF·CALIBRATING 12·BIT·PLUS·SIGN UNIPOLAR OR BIPOLAR
ANALOG· TO·DIGITAL CONVERTERS
general
reset INT
When reading the conversion data, the falling edge of the first low-going combination of CS and RD will reset
INT. The falling edge of the low-going combination of CS and WR will also reset INT.
ready out
For high-speed microprocessors, READY OUT allows the TLC1225 to insert a wait state in the
microprocessor's read or write cycle.
reference voltage (Vref)
This voltage defines the range for 1VI+ - VI- I. When 1VI+ - VI_ 1equals Vref, the highest conversion data
value results. When 1 VI+ - VI_ 1 equals 0, the conversion data value is zero. Thus, for a given input, the
conversion data changes ratiometrically with changes in Vref.
TIE HIGH
This pin is a digital input and should be tied high.

calibration and conversion considerations
Calibration of the internal capacitor and NO conversion are two separate actions. Each action is
independently initiated. A calibration command that calibrates all seven internal capacitors is normally issued
before conversion. A conversion command then initiates the NO conversion. Subsequent conversions can be
performed by issuing additional conversion commands. The calibration and conversion commands are totally
independent from one another and can be initiated in any order. Calibration and conversion commands
require 105 and 27 clock cycles, respectively.
The calibrate and conversion commands are initiated by writing control words on the six least significant bits
of the data bus. These control words are written into the IC when either CS or WR goes high. The initiation of
these commands is illustrated in the Timing Diagram. The bit patterns for the commands are shown in
Table 1.
TABLE 1. CONVERSION COMMANDS
COMMAND

~+WFi

Conversion

t
t

Calibratet

REQUIRED NUMBER

1/0 BUS

015
H
L

014
L

013
X
L

012
X
L

011
X
L

010
L
L

OF CLOCK CYCLES

105

tCalibration is lost when clock is stopped.

analog Inputs
differential Inputs provide common-mode rejection
The differential inputs reduce common-mode noise. Common-mode noise is noise common to both IN + and
IN- inputs, such as 6O-Hz noise. There is no time interval between the sampling of the IN+ and IN':" so these
inputs are truly differential. Thus, no conversion errors result from a time interval between the sampling of the
IN+ and IN- inputs.
Input bypass capaCitors
Input bypass capaCitors may be used for noise filtering. However, the charge on these bypass capaCitors will
be depleted during the input sampling sequence when the internal sampling capacitors are charged. Note
that the charging of the bypass capaditors through the differential source resistances must keep pace with the
charge depletion of the bypass capaCitors during the input sampling sequence. Higher source resistances
reduce the amount of charging current for the bypass capaCitors. Also, note that fast, successive conversion
I

TEXAS . "

F-127

INSTRUMENlS
POST OFFICE BOX 655012 eo DALLAS,

TII:'VACl:

75285

TLC1225A, TLC1225B
SELF-CALIBRATING 12-BIT-PLUS-SIGN UNIPOLAR OR BIPOLAR
ANALOG~ TO-DIGITAL CONVERTERS
will have the greatest charge depletion effect on the bypass capacitors. Therefore, the above phenomenon
becomes more significant as source resistances and the converssion rate (i.e., higher clock frequency and
conversion initiation rate) increase.
In addition, if the above phenomenon prevents the bypass capacitors from fully charging between
conversions, voltage drops across the source resistances will result due to the ongoing bypass capacitor
charging currents. The voltage drops will cause a conversion error. Also, the voltage drops increase with
higher I VI + - VI_ Ivalues, higher source resistances, and lower charge on the bypass capacitors (i.e., faster
conversion rate).
For low-source-resistance applications (Rsource < 100 [1), a O.OOl-f..IF bypass capacitor at the inputs will
prevent pickup due to the series lead inductance of a long wire. A 100-[1 resistor can be placed between, the
capacitor and the output of an operational amplifier to isolate the capacitor from the operational amplifier.
input leads
The input leads should be kept as short as possible, since the coupling of noise and digital clock signals to the
inputs can cause errors.
power supply considerations
Noise spikes on the VCC lines can cause conversion error. Low-inductance tantalum capacitors (> 1 f..IF) with
short leads should be used to bypass ANLG VCC and DGTL Vcc. A separate regulator for the TLC1225A or
TLC1225B and other analog circuitry will greatly reduce digital noise on the supply line.

positive and negative full-scale adjustment
unipolar Inputs
Apply a differential input voltage that is 0.5 LSB below the desired analog full-scale voltage (VFS) and adjust
the magnitude of the REF input so that the output code is just changing from 0 11111111 1110 to
o 1111 1111 1111. If this transition is desired for a different input voltage, the reference voltage can be
adjusted accordingly.
bipolar inputs
First, follow the procedure for the unipolar case.
Second, apply a differential input voltage so that the digital output code is just changing from
1 0000 OQOO 0001 to 1 0000 0000 0000. Call this actual differential voltage Vx. The ideal differential voltage
~
for this transition is:
-VFS

VFS

+--

(1)

8192

The difference between the actual and ideal differenti~al VOltage:i;~)
Delta

= Vx

-(2)

- -VFS + - 8192

Then apply a differential input voltage of:
Delta
Vx

(3)

and adjust Vref so the digital output code is just changing froni1 0000 0000 0001 to 1 0000 0000 0000. This
procedure produces positive and negative full-scale transitions with symmetrical minimum error.

F-128

TEXAS .."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TLC1225A, TLC1225B
SELF-CALIBRATING 12-BIT-PLUS-SIGN UNIPOLAR OR BIPOLAR
ANALOG-TO-DIGITAL CONVERTERS
TYPICAL APPLICATIONS
(4095) 0 1 1 1 1 1111 11 1 1
(4094) 0111111111110

7::/----

§
!5

I!:;:)

OSITIVE

FULL-SCALE
TRANSITION

LSB

1 1111 1111 1111 1-1)
1 1111 1111 11101-2)

-Vr.f

,.,,"

+Vref

,. , , "

~TlVE

10000000000011-4095)
10000000000001-4096)

FULL-SCALE TRANSITION

ANALOG INPUT VOLTAGE [VIN(+) - VINI-)]

FIGURE 5. TRANSFER CHARACTERISTIC

.----~IN( +)

TIE HIGH
DGTLVCC~~----~~----'

.....----1INI-)
~

SEE NOTE A":

ANLG VCC

1-+----.--__

V-

~"".; ';I~

~
,......-----~-IVref

~0.1"F

•

.....------4....-iANLG GND
SIGNAL GND
,......---4-1DGTL GND

-=- POWER GND ' -_ _ _ _ _ _

NOTES: A. The analog input must have some current return path to ANALOG GND.
B. Bypass capacitor leads must be as short as possible.

FIGURE 6. ANALOG CONSIDERATIONS

TEXAS

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

F-129

TLC1225A, TLC1225B
,
SELF-CALIBRATING 12-BIT-PLUS-SIGN UNIPOLAR OR BIPOLAR
ANALOG-TO-DIGITAL CONVERTERS
TYPICAL APPLICATIONS (Continued)
5V
IN914

~---'''''''-__''--I(N(+I

ANLG VCC+

TLC1225A'
TLC12258

/tF

IN(-I

FIGURE 7. INPUT PROTECTION
5V

4 kll
VXDR

t:S:=EE=-N~O::::T=E-=8-+---1IN( + 1
500 Il
ZERO
ADJ

ANLG VCC + 1--.....- -..
0.1/tF
+10/IF

IN( -I SEE NOTE A

DGTL VCC H~--'>--~-'
500 Il

TLC1225A
TLC12258

0.1 /IF

'""=

10 /IF

""""=_

..L..L-

3.9 kll

TIE HIGH

V'eft--.......-<

1 kll
r--~FS

ADJ
8.2 kll

NOTES: A. VI_ = 0.15 x ANLG Vee+.
B. 15% of ANALOG Vee s VXDR s 85% of ANALOG Vee.

FIGURE B. OPERATING WITH RATIOMETRIC TRANSDUCERS

F-130

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

TLC7524
Advanced LinCMOSTM 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
03008. SEPTEMBER 1986-REVISEO OCTOBER 1988

•

Advanced linCMOS'" Silicon-Gate
Technology

•

Easily Interfaced to Microprocessors

o OR N PACKAGE
(TOP VIEW)

oun

•

On-Chip Data Latches

•

Monotonic over the Entire AID Conversion
Range

•

Segmented High-Order Bits Ensure LowGlitch Output

•

Designed to be Interchangeable with Analog
Devices AD7524. PMI PM-7524. and Micro
Power Systems MP7524

•

RFB
REF
VDD
WR

OUT2
GND
DB7
DB6
DB5
DB4
DB3

CS
DBO
DB1
DB2
FN PACKAGE
(TOP VIEW)

Fast Control Signaling for Digital Signal
Processor Applications Including Interface
with TMS320

~~u lett

OOza:a:
3

GND
DB7

KEY PERFORMANCE SPECIFICATIONS
Resolution

B Bits

Linearity error

Y, LSB Max

Power dissipation

100 ns Max

Propagation delay

BO ns Max

1 20 19
18

17
16

DB6
DB5

5 mW Max

at VOO = 5 V
Settling time

DBO

9 1011 1213

NC- No internal connection

description
The TLC7524 is an Advanced LinCMOS" 8-bit digital-to-analog converter (DAC) designed for easy interface
to most popular microprocessors.
The TLC7524 is an 8-bit multiplying DAC with input latches and with a load cycle similar to the "write"
cycle of a random access memory. Segmenting the high-order bits minimizes glitches during changes in
the most-significant bits. which pfoduce the highest glitch impulse. The TLC7524 provides accuracy to
Va LSB without the need for thin-film resistors or laser trimming. while dissipating less than 5 milliwatts
typically.
Featuring operation from a 5-V to 15-V single supply. the TLC7524 interfaces easily to most microprocessor
buses or output ports. Excellent multiplying (2 or 4 quadrant) makes the TLC7524 an ideal choice for many
microprocessor-controlled gain-setting and signal-control applications.
The TLC75241 is characterized for operation from - 25 DC to 85 DC. and the TLC7524C is characterized
for operation from ODC to 70 DC.

Advanced LinCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTIDI DATA d.....uts ••l1li10 lof.rmlti••
••rnat I. of p.bll.III•• dlle. P"dum •••flrm to
spooill.III.I. ,.. thl tamo. of TI... loltTamlnll

:':'~=~I~";'.':I~i =:~~r 1I1~::~lt::'· ••,

TEXAS

INSTRUMENTS
POST OFFICE BOX 655012 • DALl.AS, TEXAS 75265

F-131

TLC7524
Advanced LinCMOSTM 8·BIY MULYIPL YING
DlGITAL·YO·ANALOG CONVERTER
functional block diagram
VOD
1141

2R
1161 RFB
R
111
121

1121

131

1131

DB6

DB7
IMSBI

DB5

OUT1
OUl2

GND

DBO
ILSBI

'~--------~v~--------~
DAlAINPUlS
operating sequence

,
~

t.ulCSI

I
I

Jf---twIWR)
I

F-132

thlCS)

~I
I

~t.uID)--.I

DBO-DB7

~thID)

-------,,<____t)- - - -

TEXAS •
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TeXAS 75265

TLC7524
Advanced LinCMOSTM 8·BIT MULTIPLVING
DIGITAL·TO·ANALOG CONVERTER
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, VOO .............................................. -0.3 V to 16.5 V
Oigital input voltage, VI ....................................... -0.3 V to VOO+0.3 V
Reference voltage, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 V
Peak digital input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 /LA
Operating free·air temperature range: TLC75241 .......................... - 25°C to 85 °C
TLC7524C ............................ O°C to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1'16 inch) from case for 10 seconds: 0 or N package ........ 260°C

recommended operating conditions
Voo - 5 V
MAX
MIN NOM
4.75

Supply voltage. VOO

5.25

voo - 15V
MIN NOM MAX
14.5

2.4

High·level input voltage. VIH

ns
ns
ns

Data bus input hold time. thlD)

Pulse duration. WR low. twlWR)

-25

TEST CONDITIONS

IIH

High-level input current

IlL

Low-level input current

Output leakage
Ilkg

oun

current
OUT2

100

Supply current

Ci
Co
Co

OBO-OB7 at 0 V or VDD

10
-10

±400

±200

±400

±200

AVDD = ±10%

0.01

0.04

%FSR/%

0.16

0.005

120

OBO-DB7 at VDD.

120

OUT2

wrl

DBO-DB7 at 0 V.

at 0 V

Reference input impedance

TEXAS .."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2
500

WRandCSatOV

IPin 15 to GNO)

~
OUT2
oun

500

and

UNIT

VI = 0

OBO-OB7. WR. CS

Output capacitance

10
-10

Vref = ±10 V
OBO-OB7 at VIHmin or VILmax

Output capacitance

Voo - 15V
MIN
TYP MAX

Vref = ±10 V
DBO-OB7 at VOO. WR. CS at 0 V.

Quiescent

Again/AVoo
Input capacitance,

Voo - 5 V
MIN
TYP MAX

WR. CS at 0 V.

Standby

Supply voltage sensitivity.
kSVS

VI - VOO
VI = 0
OBO-OB7 at 0 V.

°C

± 10 V,

electrical characteristics over recommended operating free-air temperature range, Vref OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER

CS hold time. thlCS)

ITLC75241
Operating free-air temperature. TAl TLC7524C

V
V

1.5

0.8
40

Data bus input setup time. tsulD)

UNIT

13.5

Low-level input voltage. VIL
CS setup time. tsulCS)

15.5

±10

Reference voltage, V ref

1'5

pF
pF
pF
kll

F-133

TlC7524
Advanced LinCMOSTMS;BITMULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
operating characteristics over recommended operating free·air temperature range. Vref OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER

TEST CONDITIONS

(

VDD - 5 V
MIN TYP
MAX

Linearity error

± 10 V.

VDD - 15 V
MIN TYpt
MAX

UNIT

±0.5

LSB

Gain error

See Note 1

±2.5

LSB

Settling time (to Yo LSB)

See Note 2

100

See Note 2

0.5

%FSR

Propagation delay from
digital input to 90% of
final analog output current

Feedthrough at

oun

or OUT2

Temperature coefficient of gain
NOTES:

Vref

WR and

± 10 V (100-kHz sinewave)

at 0 V.

DBO-DB7 at 0 V

±O.OOI

±O.OO4

TA = 25°C 10 MAX

%FSRIOC

1. Gain error is measured using the internal feedback resistor. Nominal Full Scale Range (FSR) = V ref - 1 LSB.
2. OUT1'load = 100 n. Cext = 13 pF. WR at 0 V. CS at 0 V. D80-0B7 at 0 V to VDD or VOO to 0 v.

principles of operation
The TLC7524 is an a·bit multiplying D/A converter consisting of an inverted R-2R ladder. analog switches.
and OUT2 bus lines.
and data input latches. Binary weighted currents are switched between the
thus maintaining a constant current in each ladder leg independent of the switch state. The high-order
bits are decoded and these decoded bits, through a modification in the R-2R ladder, control three equally
weighted current sources. Most applications only require the addition of an external operational amplifier
and a voltage reference.

oun

The equivalent circuit for all digital inputs low is seen in Figure 1. With all digital inputs low, the entire
reference current, Iref, is switched to OUT2. The current source 1/256 represents the constant current
flowing through the termination resistor of the R-2R ladder, while the current source Ilkg represents leakage
currents to the substrate. The capacitances appearing at
and OUT2 are dependent upon the digital
input code. With all digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2
and the on-state switch capacitance (120 pF maximum) appears at OUT1. With all digital inputs low, the
situation is reversed as shown in Figure 1. Analysis of the circuit for all digital inputs high is similar to
Figure 1; however, in this case, Iref would be switched to OUT1.

oun

Interfacing the TLC7524 D/A converter to a microprocessor is accomplished via the data bus and the CS
and WR control signals. When CS and WR are both low, the TLC7524 analog output responds to the data
activity on the OBO-DB7 data bus inputs. In this mode, the input latches are transparent and input data
directly affects the analog output. When either the CS signal or WR signal goes high, the data on the
.OBO-OB7 inputs are latched until the CS and WR signals go low again. When CS is high, the data inputs
are disabled regardless of the state of the WR signal.
The TLC7524 is capable of performing 2-quadrant or full4-quadrant multiplication. Circuit configurations
for 2-quadrant or 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and
bipolar operation are summarized in Tables 1 and 2, respectively.

F-134

TEXAS

INSTRUMENTS
POST OFFICE BOX 655012· DALLAS. TeXAS 75265

TLC7524
Advanced LinCMOS™ 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
principles of operation (continued)
} , - - R - - - - - RFB

r------1~...11------ OUT1

r""

••'~t
I,el

--+

~"'25-6-~-_._-~--II-kg-~-4,::"~i-----f-4,::"~1-20-PF---- OUT2

REF

FIGURE 1. TLC7524 EQUIVALENT CIRCUIT WITH ALL DIGITAL INPUTS LOW
V,.I

VDD

RA - 2kll
(See Note 3)

r--_"""-~_--------'

DBO-DB7
>---_'--OUTPUT

CS----I
WR---;

GND

=
FIGURE 2. UNIPOLAR OPERATION (2·QUADRANT MULTIPLICATION)
V,ef

VDD
20 kll

RA - 2 kll
(Se. Note 3)

20 kll

...............-OUTPUT
10 kll

DBO-DB7

CS---I

WR---;

FIGURE 3. BIPOLAR Ol>ERATION (4·QUADRANT OPERATION)
NOTES:

3. RA and RB used only if gain adjustment is ,equi,ed.
4. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

F-135

TLC7524
Advanced LinCMOS IM 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
principles of operation (continued)
TABLE 2. BIPOLAR (OFFSET BINARY) CODE

TABLE 1. UNIPOLAR BINARY CODE
DIGITAL INPUT
(SEE NOTE 5)
MSB
LSB
11111111
10000001
10000000
01111111
00000001
00000000
NOTES:

5. LSB
6. LSB

=
=

DIGITAL INPUT
(SEE NOTE 6)

ANALOG OUTPUT

LSB
MSB
11111111

- V,e! (255/256)
-V,e! (129/256)
-V,e! (128/256) = -V,e!/2
- V,e! (127/256)
- V,e! (1/256)
0

ANALOG OUTPUT
V,et (127/128)

10000001
10000000
01111111
00000001

V,e! (1/128)
0

00000000

-V,e!

-V,e! (1/128)
-V,e! (127/128)

1/256 (V,e!)'
11128 (V,e!)'

microprocessor interfaces

00·07

DATA BUS

~------------------------~

Z·80A
WRI---~~'

>--------~WR

lORa I-~I--+--t

AO-A15

FIGURE 4. TLC7524-Z·80A INTERFACE

00-07

~_ _ _ _ _ _ _ _ _ _
DA_T_A_B.:.US-=-'_ _ _..,

6800

VMAI--.......-~

AO-A15~

_ _ _ _ _ _ _ _~~~~~~_ _ _ _ _ _ _~~

FIGURE 5. TLC7524-6800 INTERFACE

F·136

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INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265

TLC7524
Advanced LinCMOSTM 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
microprocessor interfaces (continued)

A8-A15

r--------------r~

8051

r------iWR
ALE r---+-+--"'~---"

ADO-AD7

r---+-+------'
I--_____A:.,::D:,:D:;,;.R;:E:::;,SS:;,;.':,:DA:.;.T:..::A:,;B:,:U:.,::S:..-_ _ _ _ _ _ _-r
FIGURE 6_ TLC7524-8051 INTERFACE

TEXAS .."

INSTRUMENTS
POST OFFICE BOX 665012 • DAllAS. TEXAS 75265

F-137

TlC7524
Advanced LinCMOSTII 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
TYPICAL APPLICATION DATA

(

voltage·mode operation
It is possible to ope~ate the TLC7524 current multiplying O/A converter in a voltage mode. In the voltage
mode, fixed voltage is placed on the current output pin. The analog output voltage is then available at
the reference voltage pin. Figure 7 is an example of a current multiplying O/A; which is operated in voltage
mode.
.

4---'lH·.,... . . . .~..--"\...,... . . . .~"--\\--M-""-""

REF (ANALOG OUTPUT VOLTAGEI ..

L--+----+---t-...- - o u n (FIXED INPUT VOLTAGEI
L---_~-----t_---4~~---OUT2

FIGURE 7. VOLTAGE MODE OPERATION

The relationship between the fixed input voltage and the analog output voltage is given by the following
equation:
Vo = VI (0/266)
_ where
Vo = analog output voltage
VI = fixed input voltage
o = digital input code converted to decimal
In voltage-mode operation, the TLC7524 will meet the following specification:
PARAMETER
linearity error at REF

F·138

TEST CONDITIONS
VDD = 5 V. Qun = 2.5 V. QUT2 at GND. TA =

TEXAS'"

INSTRUMENTS
POST OFF:ICE BOX 665012 • DALLAS. TeXAS 75285

o·e to 70·e

Appendix F - TI Sockets

F.2 TI Sockets
The sockets produced by Texas Instruments are designed for high-densitv
packaging needs. The production sockets and burn-in/test sockets for DIP
and PLCC packages, described in the following pages, are compatible with
TMS320C1 x devices.
For additional information about TI sockets, contact the nearest TI sales office
or contact:
Texas Instruments Incorporated
Connector Systems Dept, MS 14-3
Attleboro, MA 02703
(617) 699-5242/5269
Telex: 92-7708

F-139

Appendix F - TI Sockets

IC SOCKETS

DUAL·IN·L1NE
PERFORMANCE SPECIFICATIONS

C7X SERIES - SCREW MACHINE
WIDE-TAPERED
ENTRY

Mechanical
Accommodates IC leads 0.011 ± 0.003 in by
0.018 ± 0.003
Recommended PCB thickness range: 0.062 in to 0.092 in
Recommendeq PCB hole size range: 0.032 in to 0.042 in
Recommended hole grid pattern: 0.100 in ± 0.003 in each
direction
Vibration: 1 5 G, 10-2000 Hz per MIL-STD 1344A,
Method 2005.1 Test Condition III.
Shock: 100 G, sawtooth waveform, 2 shocks each direction
per MIL-STD 202, Method 213, Test Condition I
Durability: 5 cycles, 10 mO max contact resistance change
per MIL-STD 1344, Method 2016
Solderability: per MIL-STD 202, Method 208
Insertion force (C7X and C86): 16 oz (454 g) per pin max
Insertion force (C50): 12 oz per pin max
Withdrawal force: (40 g) per pin min

C7X SERIES
PART NUMBER SYSTEM

Electrical

C7X

(X)

Contact rating: 1.0 A per contact
Contact resistance: 20 mO max initial
Insulation resistance: 1000 MO at 500 V dc per
MIL-STD 1344, Method 3003
Dielectric withstanding voltage: 1000 V ac rms per
MIL-STD 1344, Method 3001.1
Capacitance: 1.0 pF max per MIL-STD 202, Method 305

i
XX

-LX

Number of

Environmental
Operating temperature: -55°C to 125°C, gold; -40°C
to 100°C, tin
Corrosive atmosphere: 10 mO max contact resistance
change when exposed to 22% ammonium sulfide for
4 hours
Gas tight: 10 mO max contact resistance change when
exposed to nitric acid vapor for 1 hour
Temperature soak: 10 mO max contact resistance change
when exposed to 105°C temperature for 48 hours
Shelf life: 12 months min

PRECISION
MACHINED
SLEEVE

PRECISION
FOUR-FINGERED
CONTACT

Variations
Solder Tail
9 - Pin length 0.105/0.150
Wire Wrap
3 - Pin length 0.510

Plating (Sleeve/Clip)
o - Gold/Gold
5 - Tin/Gold

Positions

S -

Single-in-line package (where applicable)

Screw Machine Socket
1 - wire wrap
2 - solder tail

C86 SERIES - STAMPED AND FORMED

Materials (C7X, C50, and C86)
Body - PBT polyeSter U/L 94 VO rating
C7X & C50 Contacts - Outer sleeve: brass
Clip: BECU or PHBR
Contact finish - clip 30 I'in gold over 50l'in nickel or
50 I'in tin/lead over 50 I'in nickel
Specified by
Part Number - sleeve 10 I'in gold over 50 I'in nickel
or 50 I'in tin/lead over 50 I'in nickel
C86 Contacts - Phosphor bronze base metal
CB6 Contact-finish - Tin plate 200 I'in over copper flash

C86 SERIES
PART NUMBER SYSTEM

l
c

l86 lXX-

Variation
01 -

Standard product

Number of positions
Tin Dual Face Wipe Single Beam

TI Socket Series

F-140

Appendix F - TI Sockets

IC SOCKETS
BURN·IN/TEST DIP

PERFORMANCE SPECIFICATIONS

PART NUMBER SYSTEM

Mechanical

Accommodates IC leads 0.011 in by 0.018 in NOM
Recommended PCB thickness range: 0.062 in to 0.092 in
Recommended PCB hold size range: 0.032 in to 0.042 in
Durability: 10K cycles -CM Series, 5K cycles - CP/CO
Solderability: per MIL-STD 202, Method 208

Contact rating: 1.0 A per contact
Contact resistance: 20 m{) max initial
Insulation resistance: 1000 M{) at 500 V dc
Dielectric withstanding voltage: 1000 V ac rms
Capacitance: 1.0 pF max per MIL-STD 202, Method 305

Environmental

Copper nickel alloy
Soldertail
Number of positions

Overall gold plate
Series Features
Q- Auto unloadable

P - High density mounting
M - Shrink 0.070 centers
TI Socket Series

MATERIALS
Body - PPS (polyphenylen sulfide) glass filled U/L 94 VO
Contacts - Higher performance copper nickel alloy
Plating: t 4 ·I'in of gold min over 100 I'in of nickel min

BURN-IN/TEST DIP SOCKETS

111

C037 SERIES
A
±0.01
Length

Number of
Positions

t For additional plating options consult the factory

2,54

3.30.~

10 1301-L

TJ-II

:..It----

2.54
(0.100)

Contact
7,62
10.3001

24
28
40
42

32,51
37,59
52,83
55,37

(1,2801
(1.480) 19,05
22,86
(2.0801 10.7501 (0.9001
(2.1801

15,24
(0.6001

SOLDER TAIL

CP37 SERIES
CP37 SERIES
Number of
Positions

B
±0.O2

A
max
Length

C
max
Width

8
14
16
18
20

11,68
17,78
20,32
22,86
25,40

(0.4601
(0.700)
(0.8001
(0.9001
(10001

7,62
(0.3001

12,70
10.500)

24
28
40

30,48 (1.2001
35,56 (1.4001
50,80 (2.0001

15,24
(0.6001

20,32
10.800)

CM37 SERIES

'''''' JI.~'.'
6.50¥

~!::::!::rJn
A

B
±0.01

(0.8001
15,24
(0.8801 12,70
(0.980) (0.500) (0.6001
(1.0801

CM37 SERIES

C
±0.01
Width

20,32
22,35
24,89
27,43

..-

C037 SERIES

0
±0.02

14
16
18
20

(O.100)~

Pin to pin
A-0.l00 centers
8-0.070 centers

PPS high temperature
body material

Electrical

Operating temperature: - 65°C to 170°C - CP/CM Series,.
- 65°C to 150°C - CO Series
Humidity: 10 m{) max contact resistance
Temperature Soak: 10 m{) max contact resistance change

051

!lIIR'·"

Ju=?~_.J
0.53--1i(0.0211

1,78----J

(O.070)

Number of
Positions

A
±0.016
Length

3.48

(0.137\

0,50
10,0201

C
±O.O16
Width

27,1811.0701

10,67
(0.4201

17,20
(0.677)

40
42
54

37,8511.4901
39,62 11.5601
50,29 (1.9801

16,51
(0.6501

23,11
(0.910)

59,18 (2.3301

20,32
(0.800)

26,92
(1.0601

10.4121

B
±O.O2

Dimensions in parentheses are inches
Contact factory for detailed information

F-141

Appendix F - TI Sockets

IC SOCKETS
PLASTIC LEADED CHIP CARRIER
PERFORMANCE SPECIFICATIONS

DEVICE GUIDE
BARRIERS

Mechanical
Recommended PCB thickness range: 0.062 in to 0.092 in
Recommended PCB hole size range: 0.032 in to 0.042 in
Vibration: 15 G
Shock: 100 G
Solderability: Per MIL-STD 202, Method 208
Insertion force: 0.59 Ibs per position
Withdrawal force: 0.25 Ibs per position
Normal force: 200 g min, 450 g typ
Wipe: 0.075 in min
Durability: 5 cycles min
Contact retention: 1.5 Ibs min

Electrical
Current carrying capacity: 1 A
,
Insulation resistance: 5000 MI1 min
Dielectric withstanding voltage: 1000 V ac rms min
Capacitance: 1.0 pF max

Environmental
Operating temperature:
Operating: - 40°C to 85°C
Storage: -40°C to 95°C
Temperature cycling with humidity: will conform to final EIA
specifications
Shelf life: 1 year min

MATERIALS
Body - Ryton R-4 140% glass) U/L 94-VO rating
Contacts - CDA 510 spring temper
Contact finish - 90/10 tin 1200 I'in -400 I'in) over 40 I'in
copper
Contact factory for detailed information

PART NUMBER SYSTEM

XXX

C1PR

IPH

-IX- t:o:tact surface 1 -tin lead

plating
Contact spacing 1 - 0.050 in
Number of pos 1044, 052, 068, 084)
Plated thru hole, solder tail
TI socket Series
Plastic leaded chip carrier

PLASTIC LEADER CHIP CARRIER CPR SERIES

2.54
10.1001 TVP

Pos

Device guide barriers not shown

----,

8,13
10.3201

44
52
68

2.54 10.1001
I---.:..TV,-,-P_ _ C

A
21,43
10.844
23,98
10.944)
29,06
11.144)
34,14
11.344)

17,78
10.700)
20,32
10.800)
25,40
11.000)
30,48
11.200)

C
12;70
10.500)
15,24
10.600)
20.32
10.800)
25,40
11.000)

Extraction tool available, consult

F-142

f~ctory.

Appendix F - TI Sockets

IC SOCKETS
PLCC BURN·IN/TEST
PRODUCT FEATURES
Can be loaded by top actuated insertion or press-in
insertion, either manually or automatically
High reliability due to high pressure contact point
Open body and high stand-off design provide high efficiency
in heat dissipation
High durability up to 10,000 cycles
Compact design

PERFORMANCE SPECIFICATIONS
Mechanical
Durability: 10,000 cycles
Operating Temperature: 180°C max

Electrical
Contact rating: 1.0 A per contact
Contact resistance: 30 mO max
Insulation resistance: 1000 MO min
Dielectric withstanding voltage: 500 V ac rms min

MATERIALS
Body - ultem glass filled (U/l 94 VOl
Contact - copper alloy
Plating - overall gold plate

PART NUMBER SYSTEM

1_-- 1
CPJ 'AA33A -

xxx

B
Number of PO:itions

TI series socket

PlCC BURN-IN/TEST SOCKETS CPJ SERIES
2.54
10.1001

2.54
101001

J='!
$

+-.

(02i~rill

101001
2.54

1.27

I~ 0501

5.08 (0 2001

18.08 (0 7121---1

SIZES: 18 PIN
22 PIN

1.27 (0.0501

5.08 (0.2001

12.9010.5071--1

Dimensions in parentheses are inches
Contact factory for detailed information

F-143

Appendix F - Crystals

F.3 Crystals
This section lists the commonly used crystal frequencies, crystal specification
requirements, and the names of suitable vendors.
Table F-1lists the commonly used crystal frequencies and the devices with
which they can be used.

Table F-1. Commonly Used Crystal Frequencies
FREQUENCY
14 MHz

DEVICE
TMS3201 0-14, TMS320C10-14

18.432 MHz

TMS3201 0/C1 0, TMS320C15/E15, TMS320C17/E17

20 MHz

TMS3201 0/C1 0, TMS320C15/E15, TMS320C17/E17

20.48 MHz
25.6 MHz

TMS3201 0/C1 0, TMS320C15/E15, TMS320C17/E17
TMS3201 0/C1 0, TMS320C15/E15, TMS320C17/E17

A crystal connected across X1 and X2/ClKIN on the TMS320 processor enables the internal oscillator, as shown in Figure F-1. The frequency of ClKOUT
is one-fourth the crystal fundamental frequency. Crystal specification requirements are listed below.
load capacitance = 20 pF
Series resistance = 30 ohm
Power dissipation = 1 mW
Parallel resonant
14- M Hz and 20- M Hz crystals use fundamental mode.
25-MHz operation may require third-overtone crystal.

X2/CLKIN
CRYSTAL

.----lOf---.....

Figure F-1. Crystal Connection

F-144

Appendix F - Crystals

Vendors of crystals suitable for use with TMS320 devices are listed below.
RXD, Inc.
Norfolk, NB
(SOO) 22S-S10S

N.E.L. Frequency Controls, Inc.
Burlington, WI
(414) 763-3591

CTS Knight, Inc.
Contact the local distributor

F-145

Appendix F - Crystals

F-146

Appendix G

Programming the TMS320E15/E17 EPROM Cell

This appendix presents the TMS320E15/E17 EPROM cells which are featured
in the First-Generation Digital Signal Processors data sheet. Both devices.
TMS320E15/E17. include one 4K x 16-bit EPROM which is implemented
from a standard EPROM cell. This expands their capabilities in the areas of
prototyping. early field testing. and production. When used with either
4K-word masked-ROM TMS320C15/C17. the appropriate TMS320E15/E17
yields a more cost-effective production as a result of more migration paths for
data.
EPROM adaptor sockets are available which provide pin-to-pin conversion for
One adaptor socket (part number
programming the TMS320Ei 5/E17.
RTC/PGM320A-06) is shown in Figure G-1 and is capable of converting a
40-pin DIP device into an equivalent 28-pin device. Another socket (part
number RTC/PGM320C-06). not shown. permits a 44- to 28-pin conversion.

Figure G-1. EPROM Adaptor Socket
Key features of the EPROM cell include standard programming and verification. The EPROM cell also includes a code protection feature that allows code
to be protected against copyright violations. The protection feature can be
used to protect reading the EPROM contents. This appendix describes erasure.
FAST programming and verification. and EPROM protection and verification.
G-1

Appendix G - Programming the TMS320E15/E17 EPROM Cell

G.1 FAST Programming and Verification
Both TMS320E15/E17 EPROM cells are similar to the TMS27C64 SK x S-bit
EPROM. Their memories can be erased by using an ultraviolet light source
and electrically programmed by using the same family and device codes. The
TMS320E15/E17, like the TMS27C64, devices operate from a 5-V supply for
reading and a 12.5-V supply for programming. All programming signals are
TTL level. For programming outside the system, existing EPROM programmers can be used. Locations'may be systematically or randomly programmed
as a singular or blocked address. When programmed in a block format, each
byte of data is separately loaded into the EPROM cell with the high byte preceding the low byte. The manufacturing process is largely responsible for their
dissimilarity. Due to HVCMOS technology, the TMS27C64 has a read-only
memory; the memories of TMS320E15/E17 have both reading and writing
capabilities. The TMS27C64 is pin-to-pin compatible with all 2S-pin ROMs
and EPROMs.
The TMS320E15/E17 uses 13 address lines to address the 4K-word memory
in byte format (SK-byte memory). In word format, the most-significant byte
of each word is assigned an even address while the least-significant byte is
assigned an odd address in the- byte format. Programming information must
be downloaded into' the EPROM programmer memory in a high-byte to lowbyte order for proper programming (see Figure G-2).

TMS320E15/E17 On-Chip
Program Memory
(Word Format)
O(OOOOh)
1 (0001 h)
2(0002h)
3(0003h)

4095(OFFFh)

1234h
5678h
9ABCh
ODEFOh

EPROM
Programmer Memory
(Byte Format)
O(OOOOh)
1 (0001 h)
2(0002h)
3(0003h)
4(0004h)
5(0005h)
6(0006h)
7(0007h)

12h
34h
56h
78h
9Ah
OBCh
ODEh
OFOh

8191 (1 FFFh)

Figure G-2. EPROM Programming Data Format

G-2

Appendix G - Programming the TMS320E15/E17 EPROM Cell

Figure G-3 shows the wiring diagram for programming the TMS320E15/E17
by using the TMS27C64 in its 28-pin output form. The illustration furnishes
a table for each pin nomenclature on the TMS27C64 with a description of that
pin. Programming the code into either EPROM device should be done in the
serial mode.
.

Caution:
Although acceptable by some EPROM programmers, the signature mode cannot be used on any TMS320E1x device. The signature mode will input a high-level voltage (12.5 Vdc) onto pin
A9. Since the TMS320E1x EPROM cell is not designed for high
voltage, the cell will be damaged. To prevent an accidental
application of voltage, Texas Instruments has inserted a 3.9 kn
resistor between pin A9 of the TI programmer socket and the
programmer itself.

G-3

Appendix G - Programming the TMS320E15/E17 EPRQM 'Cell

Vpp
A12
A7
A6
A5
A4
A3
A2
A1
AO
01
02
03
GND

1
2
3
4
5
6
7
S
9
10
11
12
13
14
15
16

1
2
3
4
5
6
7
S

A1
AO(lSB)
Vpp
RS
EPT

A2
A3
A4
A5
A6
A7
AS

ClKIN

GND
01(lSS)
Vcc
02
A9
03
A10
04
A11
05
(MSB)A12
06
l
17 07
G
1S OS(MSB)
PGM
19
20
TMS320E15/E17

9
10
11
12
13
14

rMS27C64
PINOUT

40
39
3S
37
36
35
34
33
32
31
30
29
2S
27
26
25
24
23
22
21

Vcc

Pim
EPT
AS
A9

a11
G
A10

l
OS
07
06
05
04
TMS27C64
PINOUT

PIN NOMENCLATURE
NAME
A 12(MSB)-AO(lSB)

I/O
I

DEFINITION
On-chip EPROM programming address lines

ClKIN

Clock oscillator input

EPROM chip select

EPT

I
I

EPROM test mode select

IT
GND

EPROM read/verify select
Ground

EPROM write/program select

PGM
QS(MSB)-Q 1(lSBI
RS
VCC
Vpp

I/O
I
I
I

Data lines for byte-wide programming of on-chip SK bytes of EPROM
Reset for initializing the device
5- V power supply
1 2,5-V power supply

Figure G-3. TMS320E15/E17 EPROM Conversion to TMS27C64
EPROM Pinout

G-4

Appendix G - Programming the TMS320E15/E17 EPROM Cell

Table G-1 shows the programming levels required for programming, verifying,
and reading the EPROM cell. Following the table, individual paragraphs describe the function of each programming level.

Table G-1. TMS320E15/E17 Programming Mode Levels
SIGNAL TMS320E15/ TMS27C64 PROGRAM PROGRAM PROGRAM
NAMEt E17 DIP PIN
DIP PIN
VERIFY
INHIBIT

READ

OUTPUT
DISABLE

VIL

VIH

V IL

VIL

VIH

150m

VIH

PUm

VIH

Vpp

Vee

Vee+ 1

Vee

Vss
elKIN

Vss

V ss

Vss

V ss

Vss

EPT

\ 26

Vss

08-01

18-11

19-15,13-11

DIN

Vss
HI-Z

A12-A10

26-28

2,23,21

ADDR

°OUT
ADDR

Vss
HI-Z

. A9-A7

29,34,35

24,25,3

ADDR

A3-AO

39,40,1,2

7-10

°OUT
ADDR

ADDR

lEGEND:
t = in accordance with TMS27C64.
VIH = TTL high level; VIL = TTL low level; ADDR = byte address bit
Vpp = 12.5 ± 0.25 V; Vee = 5 ± 0.25 V; X = don't care
PULSE = low-going TTL level pulse; DIN = byte to be programmed at ADDR
00UT = byte stored at ADDR.

Erasure
Before programming, the memory must be erased by exposing high-intensity
ultraviolet through its transparent lid. Note that normal ambient light contains
the correct wavelength for erasure. Therefore, the window should be covered
with an opaque label after programming either the TMS320E15/E17. The recommended minimum exposure dose (UV-intensity x exposure-time) is 15
watt-seconds per square centimeter. If located about 2.5 centimeters above
the transparent lid, a typical 12 milliwatt per square centimeter, filterless UV
lamp will erase the device in 21 minutes. After erasing the memory, all bits
are in a high state.
G-5

Appendix G - Programming the TMS320E15/E17 EPROM Cell .

FAST Programming
After erasing, all memory bits in the cell are a logic one. Logic zeroes must
be programmed into their desired locations. The FAST Programming algorithm, shown in Figure G-4, is normally used to program the entire EPROM
contents, although individual locations may be programmed separately. A
programmed logic zero can only be erased by ultraviolet light. Data is presented in parallel (eight bits) on pins as-a1. Once addresses and data are
stable; PGM is pulsed. The programming mode is achieved when Vpp = 12.5
V, PGM = VIL, Vee = 6.0 V, G = VIH, and E = VIL.
More than one
TMS320E15/E17 can be programmed when the devices are connected in
parallel. Locations can be programmed in any order.
FAST Programming uses two types of programming purses: prime and final.
The length of the prime pulse is 1 ms. After each prime pulse, the byte being
programmed is verified. If correct data is read, the final programming pulse is
applied; if correct data is not read, an additional 1 -ms prime pulse is applied
up to a maximum of 15 times. The final programming pulse is 4 ms times the
number of prime programming pulses applied. This sequence of programming
and verification is performed at Vee = 6.0 V, and Vpp = 12.5 V. When the full
FAST Programming routine is complete, all bits are verified with Vee = Vpp
= 5V.
I

Program Verify
Programmed bits may be verified with Vpp = 12.5 V when G = VIL, E = VIL,
and PGM = VIH. Figure G-5 shows the timing for the program and verify operation for the FAST programs.

Program Inhibit
Programming may be inhibited by maintaining a high level input on the E pin
or PGM pin.

Read
The EPROM contents may be read independent of the programming cycle,
provided the RBIT (ROM protect bit) has not been programmed. The read is
accomplished by setting E to zero and pulsing G low. The contents of the
EPROM location selected by the value on the address inputs appear on
as-a1.

Output Disable
During the EPROM programming process, the EPROM data outputs may be
disabled, if desired, by establishing the output disable state .. This state is selected by setting the G and E pins high. While output disable is selected,
as-a1 are placed in the high-impedance state.
G-6

Appendix G - Programming the TMS320E15/E17 EPROM Cell

INCREMENT
ADDRESS

-----DEVICE
FAILED

)

Figure G-4. FAST Programming Flowchart

G-7

Appendix G - Programming the TMS320E15/E17 EPROM Cell

••

PROGRAM

A12-AO

==>¢

ADOAr

DATA IN
STABLE

1
1

>-HI-~-<

DATA OUT
VALID

'LI

1
1
1
1
1
1
I
1
1
I.
1
1
1
I

VIL
VIHNOH
VILNOL

. Vcc
VCCP
VCC
VIH
VIL
VIH
VIL

Figure G-5. Fast Programming Timing

G-B

VIH

Vpp

VCCJ

XA~D:E~S

1
1
1
1
1
1
1
1

VPPJ

PGM

STABLE

1
OS-01 - - {

-I

Ioe---..:VERIFY~

VIH
VIL

Appendix G - Programming the TMS320E15/E17 EPROM Cell

G.2 EPROM Protection and Verification
This'section describes the code protection feature included in the EPROM cell,
which protects code against copyright violations. Table G-2 shows the programming levels required for protecting the EPROM and verifying the protection. Following the table, individual paragraphs describe the protect and
verify functions.

Table G-2. TMS320E15/E17 EPROM Protect and Protect Verify Mode Levels
SIGNAL
NAMEt

TMS320E15/E17
DIP PIN

TMS27C64
DIP PIN

EPROM
PROTECT

PROTECT
VERIFY

VIH

VIL

VIH

VIL

"j5"G""M"

Vpp

VIH
Vpp

Vee+ 1

Vee

Vee+ 1

Vss
ClKIN

Vss

Vss
Vpp

VIH

EPT

Vss
Vpp

08-01

18-11

19-15,13-11

08=~

08=RBIT

A12-A10

26-28

2,23,21

A9-A7

29,34,35

24,25,3

VIL
X

A3-AO

39,40,1,2

7-10

VIH
X

X
X

lEGEND:
t = in accordance with TMS27C64.
VIH = TTL high level; VIL = low-level TTL, Vee = 5 ± 0.25 V
~rr = 12.5 ± 0.25 V; X = don't care
lSE = low-going TTL level pulse; RBIT = ROM protect bit

EPROM Protection
The EPROM protection facility is used to completely disable reading of the
EPROM contents to guarantee security of proprietary algorithms. This facility
is implemented through a unique EPROM cell called the RBIT (ROM protect
bit) cell. Once the contents to be protected are programmed into the EPROM,
the RBIT is programmed, disabling access to the EPROM contents and disabling the microprocessor mode on the device. Once programmed, the RBIT
can only be cleared by erasing the entire EPROM array with ultraviolet light,
thereby maintaining security of the proprietary algorithm. Programming the
RBIT is accomplished using the EPROM protection cycle, which consists of
setting the E, (3, PGM, and A4 pins high, Vpp and EPT to 12.5 ± 0.25 V, and
pulsing 08 low. The complete sequence Of operations involved in programming the RBIT is shown in the flowchart of Figure G-6. The required setups
in the figure are detailed in Table G-2.
G-9

Appendix G - Programming the TMS320E15/E17 EPROM Cell

DEVICE
PASSED

)

Figure G-6. EPROM Protection Flowchart

G-10

Appendix G - Programming the TMS320E15/E17 EPROM Cell

Protect Verify
Protect verify is used following the EPROM protection to verify correct programming of the RBIT (see Figure G-6). When using protect verify, 08 outputs the state of the RBIT. When RBIT = 1, the EPROM is unprotected; when
RBIT = 0, the EPROM is protected. The EPROM protection and verify timings
are shown in Figure G-7.
'4

'4.---...
PROTECT·---_-.il
!

VERIFY

A4~,
~~,
,

A,k'------------~~I!\

,
Vee
---------'if,
!
,,
,
!,
,,
Vpp

VIH

VIL

Vw t

Veep
,,
1\1...
, ___________ :eeee:

---------',

I ,...___________

::~

,
I
,
,
,
I
-----------4,~---------------4,-------------~,r_-------------VIH
,

as - - HI-z---+I.....\

,
-JA,
,

EPT _________

,,
,
\ll::-'
,,________ /
,

VIL

VIH

-J

VIL

r-H~Z~'---____- J
I

,
!,
I

II,

HI-Z

,
I
I

VIH/VOH
VIL/VOL
Vpp
Vss
VIH

VIL

tvpp

= 12.5 V and Vee

= 6.0 V for Fast Programming.

Figure G-7. EPROM Protection Timing

G-11

Appendix G - Programming the TMS320E15/E17 EPROM Cell

G-12

Index

A
AID and D/A interface 6-8
AID converters (TI) F-2
accumulator 3-19
adaptive filters 5-47
addition 5-39
addressing modes 4-2
ADDS
Add to Accumulator with Sign-Extension Suppressed 4-17
A-Iaw/ll-law companding 3-43,5-42
analog converters (TI) F-2
analog interface~rd (AlB) E-8
analog interface board 1 (AIB1) E-8
analog interface board 2 (AIB2) E-8
analog interface circuits (TI) F-2
answering machine 6-15
applications 1 -8
architecture 3-1
arithmetic logic unit (ALU) 3-19
assembly language E-3
assembly language instructions 4-1
instruction set summary 4-7
assembly language tools E-3
auxiliary register pointer (ARP) 3-15,
3-16,3-25
auxiliary registers (ARO,AR1) 3-14,4-4,
5-19

B
barrel shifter 3-18
BGEZ
Branch if Accumulator Greater Than or
_
Equal to Zero 4-22
BIO 3-31
BiO polling 5-12
bit manipulation 5-29
BLEZ

Branch if Accumulator Less Than or
Equal to Zero 4-25
block diagrams 3-5
bulletin board E-11
BV 5-30

c
CALA 5-17
CALL 5-17
central arithmetic logic unit (CALU) 3-17
CMOS devices
TMS320C10 1-5
TMS320C10-14 1-5
TMS320C10-25 1 -5
TMS320C15/E15 1 -5
TMS320C15-25 1 -5
TMS320C17/E17 1 -5
codec interface 6-6
codecs (TI) F-2
coefficients 3-3, 5-47
companding 5-42
companding hardware 3-43
A-Iaw/ll-law 5-42
A-Iaw/ll-law selection 3-43
decoding 3-43
encoding 3-43
mode bit configurations 3-43
parallel modes 3-43, 5-43
serial modes 3-43, 5-43
sign-magnitude data 3-43, 5-43
software routines 5-42
two's-complement data 3-43, 5-43
computed GOTO 5-22
context switching 5-13
control register bits 5-4
convolution operations 6-32
coprocessor interface 6-11
coprocessor port
(TMS320C17 lEn) 3-46
crystals F-144

Index-1

D/A converters (TI) F-2
data memory 3-10
data memory page pointer (DP) 3-16,
3-25
data moves 3-13
data RAM expansion 6-4
data shift 5-31
development support E-1
analog interface board 2 (AI B2) E-8
assembly language tools E-3
DFDP (digital filter design
package) E-9
DSP Software Library E-10
emulator (XDS) E-6
evaluation module (EVM) E-4
simulator E-4
third-party support E-7
TMS320 Bell 212A modem
software E-11
TMS320 DSP bulletin board
service E-.11
TMS320 DSP hotline E-11
TMS320E15 EPROM DSP Starter
Kit E-9
XDS/22 upgrade kit E-7
digital filter design package (DFDP) E-9
digital filters 5-46
direct addressing mode 3-16, 4-2
divide ratios (SCLK) 3-42
division 4-67, 5-36
DMOV 5-23, 5-32
DSP Software Library E-"1O

Fast Fourier Transforms (FFT) 5-50
filtering 5-46
FIR filters 5-46
fixed-point arithmetic 5-33
floating-point arithmetic 5-40
framing (FR) pulses 3-36,3-41
framing control 3-41

E
emulator (XDS) E-6
EPROM (TMS320E15/E17) 3-11
EPROM memories (rl) F-2
EPROM programming
(TMS320E15/E17) G-1
EPROM protection/verification
(TMS320E15/E17) G-8
evaluation module (EVM) E-4
EXINT (TMS320C17/E17) 3-34
expansion memory interface 6-2
external flag (XF) 3-31

Index-2

G
gates

0-5

H
hardware applications 6-1
A/D and D/A interface 6-8
codec interface 6-6
coprocessor interface 6-11
expansion memory interface 6-2
I/O ports 6-10
system applications 6-13
hardware stack 5-13,5-16,5-19
Harvard architecture 1 -4, 3-22
hotline E-11

I/O functions 3-27
I/O port addressing 3-27
I/O ports 6-10
IIR filters 5-46
immediate addressing mode 3-16,4-6
IN 3-28,3-44,3-45,5-25
indirect addressing 5-19
indirect addressing mode 3-16,4-4
initialization 5-3
instruction set summary 4-7
instructions (assembly language) 4-1
internal hardware summary 3-7
interrupt flag (INTF) 5-8
interrupt mode (INTM) 3-25,5-8
interruFr 3-32, 5-7
BI polling 5-12
~t switching
5-13
EXINT
3-34

FR 3-34, 5-10
FSR
3-34, 5-10
FSX
3-34,5-10
INT
3-32, 5-7
interrupt flag (I NTF) 5-7, 5-10
interrupt mode (INTM) 5-7,5-10
RS
3-24
service routines 5-7

L
logical and arithmetic operations 5-29
addition 5-39
bit manipulation 5-29
division 5-36
floating-point arithmetic 5-40
multiplication 5-33
overflow management 5-30
scaling 5-31
loop control 5-19
LTA 5-35
LTD 5-23, 5-46
Load T Register, Accumulate Previous
Product. and Move Data 4-46
/

M
.JT'1ask options C-1
memory 3-10,5-23
addressing modes 3-16
auxiliary registers (ARO.AR1) 3-14
data moves 3-13
data RAM 3-10
moving constants into data
memory 5-25
moving data 5-23
program EPROM
(TMS320E15/E17) 3-11
program memory expansion 3-12
program ROM 3-11
memory addressing modes 3-16
direct addressing 3-16,4-2
immediate addressing 3-16,4-6
indirect addressing 3-16, 4-4
memory management 5-23
addressing 5-23
memory maps 3-13
memory products (TI) F-2
microcomputer mode 3-11
microprocessor mode 3-11
modem application 6-13

modem software (TMS320 Bell
212A) E-11
moving constants into data memory
moving data 5-23
MPY 5-35, 5-46
mUltiplication 5-33
multiplier 3-21, 5-33

5-25

N
nomenclature
normalization

E-17
5-40

o
ordering information E-12, E-14
OUT 3-28, 3-44, 3-45, 5-25
overflow flag (OV) 3-25,5-30
overflow management 5-30
.
overflow mode (OVM) 3-20, 3-25, 5-30
overflow saturation mode 3-20

p
P register 3-21, 5-33
parallel shifter 3-18
part numbers E-12, E-14
PC stack 5-16,5-17
PC/MS-DOS E-10
PID control 5-55
pinouts 2-2
POP 3-24, 5-16
prescale divide ratios 3-42
product quality/reliability D-1
product register (P) 3-21, 5-33
program control 5-16
.
auxiliary register addressing 5-19
computed GOTOs 5-22
loop control 5-19
software stack expansion 5-16
subroutine calls 5-17
program counter (PC) 3-22
program EPROM
(TMS320E15/E17) 3-11
program memory 3-11
program memory expansion 3 -12
program ROM expansion 6-2
programming EPROM cell
(TMS320E15/E17) G-1
Ihdex-3

prototype devices C-1
PUSH 3-24,5-16

Q
Q format

SUBS
Subtract from Low Accumulator with
Sign - Extension Suppressed 4-70
system applications 6-13
system control register
(TMS320C17/E17) 3-51

5-33, 5-39, 5-41

T
R
RAM 3-10
receive registers 3-36
reliabil& tests 0-2
reset (R1)
3-24, 5-3
RET 5-17
ROM 3-11
ROM codes C-1
ROVM 3-20, 5-30

s
scaling 5-31
SCLK 3-36
selftest routines 5-56
serial p,ort 3-36, 6-6
fixed data-rate mode 3-39, 3-40
framing control 3-41
framing pulses 3-36
receiye registers 3-36
serial-port clock (SCLK) 3-36
timing control 3-41
transmit registers 3-39
variable data-rate mode ) 3-39, 3-40
shifters 3-18
signal descriptions 2-1
TMS3201 0/C1 0/C15/E15 2-3
sign-magnitude data 5-43
simulator E-4
sockets (TI) F-139
softWrare applications 5-1
software library E-10
software stack 5-16
software stack expansion 5-16
SOVM 3-20, 5-30
speech synthesis system 6-13
stack ,3-22,3-23
status register 3-25
SUBC 5-36
subroutine calls 5-17

Index-4

T register 3-21, 5-33
TBLR 3-30, 5-25
TBLW 3-30, 5-25
. temporary register (T) 3-21, 5-33
third-party support E-7
TMS320 Bell 212A modem
software E-11
TMS32P development tool
nomenclature E-18
TMS320 device nomenclature E-17
TMS320 OSP bulletin board service E-11
TMS320 OSP hotline E-11
TMs320C10 1-5
TMS320C10-14 1-5
TMS320C10-25 1-5
TMS320C15/E15 1-5
TMS320C15-25 1-5
TMS320C17/E17 1 -5, 2-5
TMS320E15 EPROM OSP Starter Kit E-9
TMS32010 1-4
tools E-3
transistors 0-5
transmit registers 3-39
two's-complement data 5-43

v
VAXNMS E-10
voice store-and-forward message
center 6-15

x
XOS emulator E-6
XOS/22 upgrade kit
XF 3-31

E-7

z
ZALH
Zero Low Accumulator and Load High
Accumulator 4-75
ZALS
Zero Accumulator, Load Low Accumulator with Sign-Extension Sup
pressed 4-76

Index-5

OREGON: ........: 8700 SW 105th St., Suite 110,
a..venon. OR 97005, 16031 643-87&8.

TI Worldwide
Sales Offices

PUERTO RICO: HMo Hey: Merc.ntil PI.z. Btdg .•
Suite 605. Heto Rev, PA 00918, (809) 753-8700.

ALABAMA: .........: 500 Wynn Drive, Suit. 514,
Huntsvl.... AL 36805, 12051 837·1&30.

TENNESSEE: ~ City: Erwin Hwy,
P.O. Of.wer 1255. Johnson City. TN 37605
(616)461-2192.

ARIZONA: PhoenIx: 8825 N. 23rd Ave., Phoenix,
AZ 86021. (8021 996-1007;TUCSON: 818 W. Miracle
Mlle. Suite 43, Tuc.an. AZ 85705. 18021 292·2640.
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Plaza, RoMYiIIe. CA 95878, (918) 78e-9208;
. . . DIego: 4333 View Ridge Ave., Suite 100,

=.
San

~ CA

92123.18191278-9801;

I~~=g.=; ~~:s:;;,·K~~~·St~.A

TonlnC8. CA 90602. (2131 217·7010;

Wooct.nd .-.: 21220 Erwin St., Woodland Hills,
CA 91387, (8181 704-7769.
COLORADO: AuronI: 1400 S. Potomac Ave.,

Suite 101. Aurora. CO 80012. 13031 368-8000.
CONNECTICUT: W........: 9 Berne. Industria' Perk
Rd .• Barne. Industrial Park, Wamngford,

CT 080t92, 12031 289-0074.

R.OAIDA: AItIImonte~: 370 S. North Lake Blvd.

~~=":"~9~LN~~7 6i'::~~!. 260-2116;

PENNSYlVANIA: . . Bel: 670 Sentry Pkwy.
Blue Bell. PA 19422, (215)826-9600.

TEXAS: AuItIn: 12501 Re..arch Blvd., Austin, TX
78769. 1512) 250-7855; RIchMI ...... : 1001 E.
C.mpbell Rd .• Rich.rdson, TX 75081,
(214) 880-5082; tto.ton: 9100 Southwest Frwy .•
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UTAH: Murray: 6201 South Green St., Suite 200.
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....o...w:

WISCONSIN:
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{4161 884-9181; St. lauNnt: ViNe St. Laurent
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GA 30092. 1404) 882-7900
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Ft. W.yne. IN 48815, (2191424-5174:
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1317) 573-8400.
IOWA: c...... .......: 373 Collin. Rd. NE, Suite 201.
Cedar Rapida. IA 62402. (3191 395-9650.

==.~~~ j:~o~f~~ :'5t4~,g,~n

ARGENnNA: Tex.. Instrumenta Argentin. Vi.monte
1119, 1053 e.pltal Feder.I, Buenos Aire., Argentina,
5411748-3699
AUSTRAUA fa NEW ZEALANDI: T.x.s Instruments
Austr.li. Ltd.: 8-10 TaI.v.,. Rd., North Ryde
(Sydneyl. New South W .... , Au.'r.li. 2113,
2 + 887-1122; 5th Floor. 418 St. Klid. Road.
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AUSTRIA: Texas In.truments Ges.m.b.H.:
~~=2~~ Bl16. A-2346 Brunn/Gebirge.

8815 Centre P.rk Dr .•

IIELOIUM: T.x.slnstrum.nts N.V. Belgium S.A.: 11,
Avenu. Jul•• Bondetl••n 11. 1140 Brussel., Be~um,
102) 242-3080.

MASSAC*JSETTS: W....... : 950 Winter St .•
Wafthem. MA 02154. (6171895·9100.

IlllAZIL: Tex•• In.truments Electronicos do Br.sil
Ltd•. : Ru. P... Lem., 524-7 And.., P;nhelro., 05424
Sao Paulo. Br.zil, 0815-6166.

MARYLAND:~:

Columbia MD 21046. 13011 964-2003.

..aIIGAN: F. . . . . . H.: 33737 W. 12 Mile Rd .•

DENMARK: Texas In.truments AlS, Mairelundvej 46E,
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FINLAND: T.x.. Instruments Finland OV:
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0-481-422.

:=...~:·;or~ =~ ~i~! 5~~S~:~9.

_NESOTA: Eden ........: 11000 W. 78th St .•
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MISSOURI: St.~: 11818 Barmen Drive.
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NEW JERSEY: .....: 485E U.S. Route 1 South,
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NEW YORK: bit."....: 8386 Collamer Dr.,

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FRANCE: Tex•• Instruments Fr.nce: Paris Offic•• BP
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GERMANY fFed. RapubIc of Genneny): Texas
Instrument. Deutschl.nd GmbH: Haggertystr.sse "

~~~:~iS~oto8:Ji:~~1~~~~8~~I~·.r';en

43/Kibbalstra..... 19, 4300 Essen, 201-24250;
Kltchhof'lteratr.... 2, 3000 H.nnover 51.
611 +648021; Maybachstr.ba 11. 7302 Ostfildern
2-N.llngen, 711 + 34030.

(7181385-8770;

:Vf;801.191!~~~~~.'

Poughkeepsie.

NORTH CAIIouM: CIwIcme: 8 Woodlawn Green,
Wood'-wn Rd .• Charlotte. He 28210. 17041
=~~~~~, ~:f:) ~I,~~;, IUvd .• Suite 100,
OHIO: 1Mchwood: 23776 Commerce P.rk Rd .•
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1MwrcrMk: 4200 Colonel Gtenn Hwy.,

Beavercreek, OH 45431,1&131427-8200.

~
TEXAS

INSTRUMENTS

HONG kONG: Tex•• In.trumant. Hong Kong Ltd., 8th
=~ :::~ 1~~~:;2~3:anton Rd., Kowtoon.
IRElAND: T.xas lnatrum.nt. (Ireland) Limited:
7/8 Harcourt Street, StllkJrgan. County Dublin. Eire,
1 781677.
ITALY: Tex •• In.truman•• 1••li. S.p.A. Divisione
Semiconduttori: Viele Europa. 40. 20093 Cologne
Monz... IMII.nol, (02) 253001; Vi. C....11o dell.
Magll.na, 38, 00148 Rom •• IOSI 5222661;
VI. Am.ndola. 17. 40100 Bologn., 10511 664004.
JAPAN: Toltyo M8fketinglSale. (Headquarters):
Texa. In.trument. J.p.n ltd., MS Shibaur. Btdg .• 9F,
4-13-23 Shib.w•• Minato-ku. Tokyo 108, J.p.n.
03-769-8700. Tex.. In.trum.nt. Japan Ltd.: NI••holwei Bldg. 5F, 30 ImatMllhi 3-chome. Htgalhl-ku.
0 . . . 541, J.pan, 06-294-1881: Deini Toyot. West
Btdg. 7F. 10-27 Mei.ki ....chome. Nak.mur.-ku.
Nagoy. 460. 052-583-8691; D.lichi Selmai Btdg. 6F.
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0762-23-5471: Daiichi Olympic Tec:hikawa Bldg. 6F.
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0425-27-6426; Matsumoto Show. Bldg. 6F, 2-11
Fukashi l-chome. M.tsumoto 390~ N~ken,

~~:~-:~~~=.i:t!~:':h~::~:~~:I~~O,6F.

045-322-6741; Nlhon Seimai Kyoto Vas.k. Bldg. 5F.
843-2 Hig••hi Shiokohjidori. Ni.hlnotCJh.in Hlg.shi-iru,
Shioltouji, Shimogyo-ku. Kyoto 600, 075-341-7713;
2597-1. Az. Harudai. O.z. V.uk., Kitsuki 873. Oi••ken. 09788-3-321 1; Miho PI.nt, 2350 Kih.r. Mihomur•• In.shiki-gun 300-04. Ib.ragi-k.n.
0298-85-2541 .
KOREA: Tex.a Instrument. Korea Ltd .• 28th Fl .• Trade
Tower. "59, S.msung-Dong, K.ngnarn-ku. Seoul.
Kor •• 2+551-2810.
MEXICO: Texas Instruments de Mexico S.A.: Alfonso
Reyes-115. Col. Hipodromo Condes., Mexico. D.F.,
Mexico 06120.625/525-3860.
MIDDLE EAST: Tex.s Instruments: No. 13, 1st Ftoor
M.nnai Bldg., Diplom.tic Are•• P.O. Box 26335.
Manam. Bahrain. Arabi.n Gulf, 973+274681.
NETHERLANDS: T.x.s Instruments Holland B.V.,
19 Hogehilweg, 1100 AZ Amsterdam-Zuidoost,
HoIl.nd 20 + 560291 1.
NORWAY: Texa. Instrumenta Norw.y A/S: PB106,
Refstad 0585, 0.10 5. Norw.y, 121 165090.
PEOPLES REPUBLIC OF CHINA: T.x•• Instruments
China Inc .• Beijing R.presentativ. Office. 7-05 Cltic
~tiW2'2~:,J~~~~3~~W8i D'ue, Beijing. China. (861)

PHIUPPINES: Texas Instruments Asi. Ltd.: 14th Floor.
S. Lepanto Bldg., Paseo de Roxas, M.kati, Metro
M.nll., Philippines, 817-60-31.
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Electronlco (Portugall, Ld•• : Ru. Eng. Frederico Ulrich,
2650 Moreir. Oa M.i., 4470 M.i., Portug-',
2-948-1003.
SINGAPORE I + INDIA. INDONESIA. MALAYSIA.
THAILAND): Tex•• Instruments Singapor. (PTE) Ltd.,
Asi. Pacific Division, 101 Thompson Rd. #23-01,
United Squ.re. Singapore 1130. 350-8100.
SPAIN: Tex.s Instruments Esp.n•• S.A.: C/Jose
laz.ro Galdi.no No.6. M.drid 28036. 1/468.14.58.
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Corpor.tion ISvarigefilialenl: 5--164-93, Stockholm.
Sweden, 8 - 752-6800.
SWITZERLAND: Tex•• Instrumants, Inc .• Reidstrasse
6, CH-8953 Dietikon (Zuerich) Switzerl.nd,
1·740 2220.
TAIWAN: Texas Instruments Supply Co., 9th Floor
B.nk Tower, 205 Tun Hw. N. Rd., Taipei. T.iwan,
Republic of China, 2 + 713-9311.
UNITED KINGDOM: TexIS Instruments Limited:
M.nton Lane, Bedford, MK41 7PA. Engl.nd, 0234
270111.

A·18B

TI Sales Offices TI Distributors

MAIIYLAND: Arrow/K.....'" (301) llH002;

. .:.=-

:.:~:tioz'i"=2~.1~2) 115-1007;

TI AUTHORIZED DISTRIBUTORS
Arrow/Klerulff Electro.nlc. Group
Arr_ (Canada)
FuturB Electronic. (Canada)
GRS Electronic. Co., Inc.
Hall·Mark Electronics
MarshBl1 Industries
N_ark ElectroniC.
Schweber Electronics
Time Electronics
Wyle Laboratories
Zeus Components
-OBSOLETE PRODUCT ONLYRochester Electronics, Inc.
N_buryport, Massachusetts
(508) 462·9332
.

~.:.o,,:~~~~ '~,:,-.m~) 810-1200;

SO. D'ar.: ('1~) 271-t101;

ro=n~(;,\1:lm~;

W_Io'" HI" (818) 704-7758.
COLDRADO: A..... (303) 388-8000.
CONNECTICUT: W.III.gford (203) 289-0074.

""-monte 8prlng. (305) 280-2118;

r...~='l:~f"~~~r~502;

GEORGIA: Norcross (404) 662·7900.

IWHO,,: Arlington Heights (312)

~2925.

INDIANA: C.rrMl (317) 573-8400;
Fl. W.yn. (21') 424-517••
IOWA: Cedar Rapids (319) 395-9550.

MICHIGAN: DoIrOn; Arrow/KI....fI (313) 482·2210;
HIII-M.rk \31\462.,205; M....h.1I ~313) 525-5850:

:=~:':J.. =:~r:;8~ ~~~lOO;

:!::.,:~r.~~)~=:'~I, fsl'21':.l.2211;

Schweber (812) N1·5280. '

~!:3f.~:Hn~t ~W50";":::':rJ:,~'~~~888:

Schweber (314) 739-0528.
I

IIIASSACHUSETTS: Wa"Mm (817) 895-9100.

::~:J~~:id:(6'r~)f:7~~: (313)

553-1569;

MINNESOTA: Eden ""alrle (612) 828-1300.
MISSOURI: Sl Loul. (314) 5.e.7~.
NEW JERSEY: 1..11. (201) 750-1050.

~~~~:~20'r.;;~~t;'OO~,f.~:~S:~~~~i81.9235;

Schweber (205) 895-0480.

ARIZONA: Arrow/KleNlff

CO2) 437.0750;

~::-w~~r:r \:lJ) ~~~'~~i v!;.~:Jr:~=90;

CAUFORNIA: Los Ana."S/Or0:'1'.".Cou.1Y:
Arrow/Kleruttf (818:U0l.7500. (7~~838·Sd2;

NEW MEXICO: Albuqu.rq. . (505) 3015-2555.

::~::;r(~~~f)4~;-o1~~'(~1r)4~~SS::;

~=I~~~5~~}e::=u•• (31S) 463-9291;

(714) 458·5395: Schweber (818) 88O-H88;
14) 883-0200, (213) 320-8090; Wylo (81818....9000'
14) 863-9153; Zeus (714) 921 ..9000; (818 aag..3838;

PlI1slord (718) 385-8770;
PoughkMp.1e (114) 47~21OO.
NORTH CAROUNA: Chorion. (704) 527...33;
R.lolgh (119) 87802725.
OHIO: a.achwood (216) 4M081OO;

a...... C.... (513) 4270f200.

OREGON: B......... (503) 843-8758.
PENNSYLVANIA: Blu. Boll (215) 825-9500.
PUERTO RICO: Hoto lIoy (809) 753-8700.

ecremento: Halt·Mark (918) 824-9781;

;;:'(;~6\9~~~:;8:?OO: Schweber (B18) 364w0222:
San DIego: Arrow/Klerulff (619) 565-4800:
Hall·Mark (619) 26..1201; Marshall '61~ 578-9600':

t:'r'::I=~4~~~~~{~1~~.

Hall-Mlrk (408) :72..0900; Marshall (408) 942-4600;
Schwebor (408) 4~2·7171; Wylo (408) 727-2500;
Zau. (408) 998-Sf!.21.
COLORADO: Arrow/Klarulff (303) 790-4444:

TENNESSEE: Johnson CIty (815) 461-2182.

~~:::r \~~~) ~gj,~~; =h(~M~J7~:J5~83:

TEXAS: Austin (512) 250-7855;

CONNETICUT: ArroW/Klerulff (203) 28$.7741;

:~~;:.".~ ~~l~~'i:.a:6a2;

Sen Antonio (512) 416-1779. ,

UTAH: Munay (801) 2. . . .72.
WASHINGTON: Redmond (208) 881.J08O.

WISCONSIN:

(414i 7a..2899.

CANADA: Nron, Ontario (813) 728-'970:

::~u~':t,HlJ~=r::'~1':d:=~81i

TI Regional
Technology Centers
CALIFORNIA: 1M.' (714) 810-8105;
Senta QIIr. (408) 7.8-2220;
IIEORGIA: No,oro" (404) ""·7845.
iWNOIS Arlington Heights (312) 840.2901,
IiIASSACHUSETTS: W.nham (817) 895-9196.

NEW HAMPSHIRE: Arrow/Klo.. '" (803) ......968;
Schweber (603) 625-2250.

,=~::::~:~~:~=tcF.(~~60;
~all.MOrk \':1 575-4415,~1)
882.8773,

!:g:1 ~al'O: ~~'::'l (2~~tr.:o.

NEW MEXICO: Arrow/Klo..'" (505) 243-45".

:~~in'i:r~ ~~~; H"~Mork (51~37.CJ800;

KANSAS: Overland 'ark (913) 451-4511.
MARYLAND: Columbia (301) 9&402003.

85800900;

~
~'!A ~:a:=;~h(~~~ 5:&=10;
Wyl. (817) 273-7300; Zeus (817) _ .

ALABAMA: H.....,. . (205) 837-7530.

FLORIDA:

=-=~V)=;=h(:.lf~~:;r.e';

MASSACHUSETTS Arrow/KIoru'"

Hal~Mark

(203) 271-2844; Morsha" (203) 285-3822;
Schwaber (203) 264-4?OO.
FLORIDA: Fl. Lauderdale:
Arrow/Kleru'" (305) 42N200; HII~Mork ~305) 971·11280;
~~::: (~0:1!~i!~~: {~~w:::~~::2? 977.7511:
Hall·Mark (407) 830-5855: Marshall (40~NI585:

~:~';~H~:~a=::1:'5355~l~;J:~7) 3

ODD:
Schwaber (813) 541-5100.

M....hall (813) 578-13~;
GEORGIA: Arrow/Klerutff (404) 44&-8252:
Han-Mark (404) 447·8000: Marshall (404) 923-5750;
Schweber (404) 449-9170.
ILUNOIS: Arrow/Kleru'" (312) 25..0500;

=::::73\~1 ~,A.e:;~~~::::::1(~~~~) 3~a..O-:7':o~;

INDIANA: Ind..na~I': Arrowlklet'ulff ~317} 243-9353:
~~:~ \~\'9) ~~~. Mar.hall {31 } 297-0483;

,fl

IOWA: Arrow/K'o.. (319) 395-7230;
Schwebo, (319) 373-1417.

~I~t~~ (~r:)'::~'~l~,:!~(~~r~~~~~2~~2;

Schwaber (913) 4'2·2922.

~::';~4\5~;~?¥~~24; Schweber (516)

7474:

=::i."=:~,':)~:::~~J~!:l:ln;~=~35-7620;

Schwab., (718) 42..2222;
SyrRUH: Marshall (607) 798-1611.

;~:)':2~~~~:'':~~1)~~~~~;878-3132.
Marshall (91t) 878-9882; Schweber (919) 876-0000.
OHIO: Cleveland: Arrow/KIerutff (21&) 248-3190:
Han.Mark (218) 34.....32: Marshall (218) 248-1788:
(218) 464-2970:
Columbus: Hall·Mark (614) 888-3313;

Schweber

:~~:i, ~5~;):~~~':0~5~:1!t~~:3) 439-1800.

OKLAHOMA: Arrow/Klo.. '" (918) 252·7537;
Schwebel' (918) 622-8003.

3:~~~~(5=~~':o~~:)(r~~.
PENNSYLVANIA: Arrow/K.....'" S121858-7000,

~~:lh~~~l~~~~~-;C::~~ber'(~,:ft1f~,

(412) 963-8804.

TEXAS: Austin: Arrow/KlerulH (512) 835-4180:

Hall·M.rk
Schwabe,
081..s:

258-8848: Marthall (512) 837.1811;
Wylo (512) 834-1157;
380-8484·

~::;:r:, ~~~) ~~~.5010; ~,~~U~t~~:s~~;

Zeus (214) 783-7010,

~~~::~:M=%<~!:lJr:1-gr=h..700;

~::,a-w'!b:r.<&\~) ~~=; =h~aI~~:e~~oo;
~!~~aZ(:~::~~V:3;'~:~~:1(~;01) 485-1551;

Wylo(801) 97....53.

::'~:!:1~r~::~~I~:' (~:,) ::,s::::o~;
WISCONSIN: Arrow/Klerulff (414) 782·0150:

::~::.~ \~\~} ~~~~. Marshall (414) 797.&400;

~::::I!~:C~'=:::(~)~~::A::3S-5325;
Mont....I: Arrow Clinada (514)'735-5511;
Future (514) 694-7710:
Arrow Canada (613) 228-6903;

~awa:

~=~6~~~2::!!~enada (418) 871.7500:
T""",Io: Arraw Conada (418) 872.7789;
Future (418) 838-4771: Marshall (418) 674·2181;
Vancower: Arrow Canada (604) 211.2988;
Future (604) 2.... 1186.

TEXAS: Rlcherdson (214) 1580-5068.
CANADA: He...n, Ontarto (813) 728-1970.

TEXAS
INSTRUMENTS

Customer
Response Center
TOLL FREE: (800) 232..200
DUTSIDE USA:

\~~~ ~~;,,!1 ~:OO p.m. C~T)
A·IS9

-'!}
TEXAS

INSTRUMENTS
Printed in U.S.A., March 1989
1604933·9702

SPRU0138

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1989_TI_First Generation_TMS320_Users_Guide 1989 TI First Generation TMS320 Users Guide

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