1989_TI_High Speed_CMOS_Logic_Data_Book 1989 TI High Speed CMOS Logic Data Book
User Manual: 1989_TI_High-Speed_CMOS_Logic_Data_Book
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•
TEXAS
INSTRUMENTS
High·Speed CMOS Logic
:t
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1989
1989
General Information
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High-Speed CMOS Logic
Data Book
~
TEXAS
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments (Til reserves the right to make changes to or to
discontinue any semiconductor product or service identified in this
publication without notice. TI advises its customers to obtain the latest
version of the relevant information to verify, before placing orders,
that the information being relied upon is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with Tl's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. Unless mandated by government
requirements, specific testing of all parameters of each device is not
necessarily performed.
TI assumes no liability for TI applications assistance, customer product
design, software performance, or infringement of patents or services
described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or
relating to any combination, machine, or process in which such
semiconductor products or services might be or are used.
Information contained in this data book supersedes all data for this
technology published by TI in the United States of America before
June 1989.
Copyright © 1987. 1989 Texas Instruments Incorporated
Printed in the U.S.A.
Revised June 1989
SCLD001C
INTRODUCTION
The high-speed silicon-gate CMOS (HCMOS) logic family from Texas Instruments offers a broad range of functions
from basic gates and flip-flops to bus-compatible complex devices. The devices in this family are pin-for-pin
and functionally compatible with the corresponding devices in the popular LSTTL family while offering a significant
power savings. Both CMOS voltage-compatible functions, SN54174HC', and TTL voltage-compatible functions,
SN54/74HCr are included in Tl's HCMOS logic family.
The HCMOS logic devices included in this book offer speed and drive capability comparable to LS but with lower
power dissipation for applications where power must be minimized. The availability of these devices in surface
mount packaging, both SO and LCC, also makes them especially attractive for use in systems where board
space is critical.
High-speeds and low power consumption have been made possible by the 3-",m self-aligned poly-silicon-gate
CMOS process. This self-aligning process permits smaller channel lengths, hence an increase in switching speeds
and less gate capacitance.
Through the successful execution of an aggressive design-in reliability program, Texas Instruments is able to
offer a HCMOS logic family with reliability consistent with that of more mature technologies. Reliability
improvement programs are ongoing. Further, a quality watch program to continually monitor the quality and
reliability of production devices is in place and guarantees a consistent product of the highest quality.
This book contains pertinent technical information on available HCMOS devices. The general information section
includes a functional and numerical index, and parameter measurement information. The mechanical section
provides packaging information on all devices included in this book. A detailed discussion of interchangeability,
electrostatic discharge (ESD) protection, latch-up circuitry, design considerations, interfacing, and other pertinent
subjects regarding this family can be found in the designer's information section.
Complete technical data for any Texas Instruments semiconductor/component product is available from your
nearest TI field sales office, local authorized TI distributor, or by writing direct to:
Texas Instruments Incorporated
P.O. Box 809066
Dallas, TX 75244-9066
We sincerely hope that you will find the new HCMOS Logic Data Book a meaningful addition to your technical
library.
v
ATTENTION
These devices contain circuits to protect the inputs and outputs
against damage due to high static voltages or electrostatic fields.
however. it is advised that precautions be taken to avoid application
of any voltage higher than maximum-rated voltages to these highimpedance circuits.
Unused inputs must always be connected to an appropriate logic
voltage level. preferably either Vee or ground.
vi
General Information
Numerical Index
Functional Index
D Flip-Flop and Latch Signal Conventions
Explanation of Function Tables
Glossary
Parameter Measurement Information
Ordering Instructions
Mechanical Data
Tape and Reel Information
IC Sockets
1-1
II
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CD
:::l
CD
...
at
....
:::l
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3
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....
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:::l
1-2
NUMERICAL INDEX
NUMERICAL INDEX
SN54HCOO
SN54HCTOO
SN54HC01
SN54HC02
SN54HCT02
SN54HC03
SN54HC04
SN54HCT04
SN54HCU04
SN54HC05
SN54HC08
SN54HCT08
SN54HC09
SN54HC10
SN54HC11
SN54HC14
SN54HC20
SN54HC21
SN54HC27
SN54HC30
SN54HC32
SN54HCT32
SN54HC36
SN54HC42
SN54HC51
SN54HC73
SN54HC74
SN54HCT74
SN54HC75
SN54HC76
SN54HC77
SN54HC78
SN54HC85A
SN54HC86
SN54HC107
SN54HC109
SN54HC112
SN54HC113
SN54HC114
SN54HC125
SN54HC126
SN54HC132
SN54HC133
SN54HC137
SN54HCT137
SN54HC138
SN54HCT138
SN54HC139
SN54HCT139
SN54HC147
SN54HC148
SN54HC151
SN54HC152
SN54HC153
SN54HC154
SN54HC157
SN54HC158
SN54HC160
SN54HC161
SN54HC162
SN54HC163
SN54HC164
SN74HCOO - .... , ..........
SN74HCTOO .. ' " .... ," ...
SN74HC01 ............ , ...
SN74HC02 ................
SN74HCT02 ...............
SN74HC03 ............. , ..
SN74HC04 ...............
SN74HCT04 .. ...... ... ....
SN74HCU04 ...............
SN74HC05 ................
SN74HC08 ................
SN74HCT08 ...... , ........
SN74HC09 ............ , ...
SN74HC10 ................
SN74HC11 ......
SN74HC14 ................
SN74HC20
SN74HC21 ....... , ........
SN74HC27 ..... " , ........
SN74HC30 ................
SN74HC32 ................
SN74HCT32 ...............
SN74HC36 ................
SN74HC42
.... .......
SN74HC51 ................
SN74HC73 ................
SN74HC74 ................
SN74HCT74 ...............
SN74HC75 .... ....... .....
SN74HC76
...........
SN74HC77 ..... ....... ....
SN74HC78 ................
SN74HC85A ...............
SN74HC86 ................
SN74HC107 ...............
SN74HC109 ........... ....
SN74HC112 ...............
SN74HC113 ..... .... ......
SN74HC114 ...............
SN74HC125 ...............
SN74HC126 ...............
SN74HC132 .. ... ..........
SN74HC133 ............ ...
SN74HC137 ............ ...
SN74HCT137 ...... ........
SN74HC138 .. .............
SN74HCT138 . ... ..........
SN74HC139 ...............
SN74HCT139 . ... ....... ...
SN74HC147 .. .... .........
SN74HC148 ....... ........
SN74HC151 ............ ...
SN74HC152 ...... .........
SN74HC153 ....... ...
SN74HC154 ....... ........
SN74HC157 ....... ... .....
SN74HC158
........
SN74HC160 .. .... .........
SN74HC161 ....... ... .....
SN74HC162 ....... ... .....
SN74HC163 .. .... .........
SN74HC164 ... ....... .....
'
"
2-3
2-7
2-9
2-13
2-17
2-19
2-23
2-27
2-29
2-33
2-37
2-41
2-45
2-49
2-53
2-57
2-61
2-65
2-69
2-73
2-77
2-81
2-85
2-89
2-93
2-97
2-101
2-105
2-109
2-113
2-117
2-121
2-125
2-129
2-133
2-137
2-141
2-145
2-149
2-153
2-153
2-159
2-163
2-167
2-171
2-175
2-179
2-183
2-187
2-191
2-191
2-197
2-201
2-205
2-209
2-213
2-213
2-217
2-217
2-217
2-217
2-231
SN54HC165
SN54HC166
SN54HC173
SN54HC174
SN54HC175
SN54HC180
SN54HC190
SN54HC191
SN54HC192
SN54HC193
SN54HC194
SN54HC195
SN54HC237
SN54HCT237
SN54HC238
SN54HCT238
SN54HC239
SN54HC240
SN54HCT240
SN54HC241
SN54HCT241
SN54HC242
SN54HC243
SN54HC244
SN54HCT244
SN54HC245
SN54HCT245
SN54HC251
SN54HC253
SN54HC257
SN54HC258
SN54HC259
SN54HC266
SN54HC273
SN54HC280
SN54HC283
SN54HC298
SN54HC299
SN54HC354
SN54HC365
SN54HC366
SN54HC367
SN54HC368
SN54HC373
SN54HCT373
SN54HC374
SN54HCT374
SN54HC375
SN54HC377
SN54HC378
SN54HC379
SN54HC386
SN54HC390
SN54HC393
SN54HC490
SN54HC533
SN54HCT533
SN54HC534
SN54HCT534
SN54HC540
SN54HCT540
SN54HC541
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74HC165 . ..............
SN74HC166 . ..............
SN74HC173 · ............. ,
SN74HC174 · ...... , .......
SN74HC175 .., ...........
SN74HC180 ...... , ... ' , ...
SN74HC190 ...............
SN74HC191 ...............
SN74HC192 · , ........ ....
SN74HC193 . ..............
SN74HC194 . ..............
SN74HC195 . ..............
SN74HC237 . ..............
SN74HCT237 . .............
SN74HC238 .......
SN74HCT238 . .............
SN74HC239 .. , .. , ' , ......
SN74HC240 ..............
SN74HCT240 . .......
SN74HC241 . ..............
SN74HCT241 . .............
SN74HC242 . ..............
SN74HC243 . ..............
SN74HC244 ...............
SN74HCT244 . .............
SN74HC245 . ..............
SN74HCT245 . .............
SN74HC251 . ..............
SN74HC253
.........
SN74HC257 . ..............
SN74HC258 · ..............
SN74HC259 . ..............
SN7.4HC266 ...............
SN74HC273 · ..............
SN74HC280 . ..............
SN74HC283 ...............
SN74HC298 . ..............
SN74HC299 ...............
SN74HC354 · ..............
SN74HC365 . ..............
SN74HC366 . ..............
SN74HC367 · ..............
SN74HC368 ...............
SN74HC373 ...............
SN74HCT373 ..............
SN74HC374 ...............
SN74HCT374 ..............
SN74HC375 . ..............
SN74HC377 ...............
SN74HC378 · ..............
SN74HC379 ...............
SN74HC386 ...............
SN74HC390 ...............
SN74HC393 ...............
SN74HC490 ...............
SN74HC533 ...............
SN74HCT533 ..............
SN74HC534 ...............
SN74HCT534 ..............
SN74HC540 ...............
SN74HCT540 ..............
SN74HC541 ..........
'
'
'
'
'"
2-235
2-241
2-247
2-253
2-253
2-259
2-263
2-263
2-271
2-271
2-279
2-285
2-291
2-295
2-299
2-303
2-307
2-311
2-317
2-311
2-317
2-321
2-321
2-327
2-331
2-335
2-339
2-343
2-349
2-355
2-355
2-361
2-367
2-371
2-375
2-379
2-385
2-389
2-395
2-401
2-401
2-401
2-401
2-407
2-413
2-417
2-423
2-427
2-431
2-431
2-431
2-437
2-439
2-439
2-447
2-451
2-457
2-461
2-467
2-471
2-477
2-471
II
C
0
+i
CO
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...
0
.5
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...
Q)
C
Q)
~
1-3
NUMERICAL INDEX
NUMERICAL INDEX
C)
CD
::::I
CD
"'"
et
-....
::::I
0
3"'"
D)
....
O·
::::I
1-4
SN54HCT541
SN54HC563
SN54HCT563
SN54HC564
SN54HCT564
SN54HC573
SN54HCT573
SN54HC574
SN54HCT574
SN54HC590A
SN54HC594
SN54HC595
SN54HC620
SN54HCT620
SN54HC623
SN54HCT623
SN54HC640
SN54HCT640
SN54HC643
SN54HCT643
SN54HC645
SN54HCT645
SN54HC646
SN54HCT646
SN54HC648
SN54HCT648
SN54HC651
SN74HCT541 ..............
SN74HC563 ...............
SN74HCT563 ..............
SN74HC564 ...............
SN74HCT564 ..............
SN74HC573 ...............
SN74HCT573 ..............
SN74HC574 ...............
SN74HCT574 ..............
SN74HC590A ..............
SN74HC594 ...............
SN74HC595 ...............
SN74HC620 ...............
SN74HCT620 ..............
SN74HC623 ...............
SN74HCT623 ...... " " . ' "
SN74HC640 ...............
SN74HCT640 ..............
SN74HC643 ..............
SN74HCT643 ..............
SN74HC645 ...............
SN74HCT645 ..............
SN74HC646 ...............
SN74HCT646 ..............
SN74HC648 ...... , " , .....
SN74HCT648 .. ," , .. , .. " .
SN74HC651 ...............
'
2-477
2-483
2-487
2-491
2-497
2-501
2-507
2-511
2-517
2-521
2-527
2-533
2-539
2-543
2-539
2-543
2-547
2-553
2-547
2-553
2-547
2-553
2-559
2-567
2-559
2-567
2-573
SN54HCT651
SN54HC652
SN54HCT652
SN54HC679
SN54HC682
SN54HC688
SN54HC805
SN54HC808
SN54HC832
SN54HC4002
SN54HC4016
SN54HC4017
SN54HC4020
SN54HC4024
SN54HC4040
SN54HC4060
SN54HC4061
SN54HC4066
SN54HC4075
SN54HC4078A
SN54HC4514
SN54HC7001
SN54HC7002
SN54HC7032
SN54HC7074
SN54HC7266
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
.
SN74HCT651 · . . . . . . . . . . . .
SN74HC652 . ..............
SN74HCT652 . .............
SN74HC679 ...............
SN74HC682 . . . . . . . . . . . . . . .
SN74HC688 . ..............
SN74HC805 ...............
SN74HC808 . ..............
SN74HC832 . ..............
SN74HC4002 · . . . . . . . . . . . . .
TLC40161 .................
SN74HC4017 ..............
SN74HC4020 . .............
SN74HC4024 ..............
SN74HC4040 . ... , .........
SN74HC4060 ..............
SN74HC4061 ..............
TLC40661 .................
SN74HC4075 ..............
SN74HC4078A .............
SN74HC4514 ..............
SN74HC7001 . .............
SN74HC7002 . .............
SN74HC7032 . .............
SN74HC7074 · . . . . . . . . . . . .
SN74HC7266 . ...... , ' .....
.
2-581
2-573
2-581
2-587
2-593
2-597
2-601
2-605
2-609
2-613
2-617
2-625
2-631
2-635
2-639
2-643
2-647
2-651
2-659
2-663
2-667
2-677
2-681
2-685
2-689
2-695
FUNCTIONAL INDEX/SELECTION GUIDE
AND. NAND GATES. BUFFERS. AND INVERTERS
DESCRIPTION
OUTPUT
DEVICE
DESCRIPTIVE
TYPE
TYPE
INFORMATION
2-23
'HCT04
2-27
'HC05
2-33
'HCU04
2-29
'HC4061
2-647
'HCOO
2-3
'HCTOO
2-7
'HC01
2-9
...
'HC03
2-19
C
Totem-pole
'HC08
'HCT08
2-37
2-41
~
Open-drain
'HC09
2-45
2-605
Open-drain
Totem-pole
Hex Unbuffered Inverters
Hex Buffer.
Totem-pole
Quad 2-lnput NANO Gate.
Open-drain
Quad 2-lnput AND Gate.
Hex 2-lnput AND Driver.
'HC808
Triple 3-lnput NAND Gates
'HC10
2-49
Triple 3-lnput AND Gate.
'HC11
2-53
'HC20
'HC21
2-61
Dual 4-lnput AND Gate.
8-lnput NAND Gates
'HC30
2-73
13-lnput AND Gates
'HC133
2-163
Dual 4-lnput NAND Gates
o
+i
'HC04
Totem-pole
Hex Inverters
c
Totem-pole
ca
...E
....o
.5
16
Q)
Q)
2-65
OR. NOR. EXCLUSIVE-OR. AND AND-OR-INVERT GATES
DESCRIPTION
OUTPUT
DEVICE
DESCRIPTIVE
TYPE
TYPE
INFORMATION
Quad 2-lnput NOR Gates
Totem-Pole
Quad 2-lnput OR Gates
Quad 2-lnput Exclusive-NOR Gates
Open-drain
Quad 2-lnput Exclusive-OR Gates
'HC02
2-13
'HCT02
2-17
'HC36
2-85
'HC32
2-77
'HCT32
'HC7266
2-81
'HC266
2-367
2-695
'HC86
2-129
'HC386
2-437
Hex 2-lnput Exclusive NOR Drivers
'HC805
2-601
Hex 2-lnput OR Driver.
'HC832
'HC51
2-609
Triple 3-lnput NOR Gates
'HC27
2-69
Triple 3-lnput OR Gate.
'HC4075
2-659
Dual 4-lnput NOR Gates
'HC4002
2-613
8-lnput ORINOR Gates
'HC4078A
2-663
Dual 2-Wide 2-lnput AND-DR-Invert Gates
Totem-pole
2-93
GATE BUFFER/DRIVERS
DEVICE
DESCRIPTIVE
TYPE
INFORMATION
Hex 2-lnput AND Driver.
'HC808
2-605
Hex 2-lnput NOR Drivers
'HC805
2-601
Hex 2-lnput OR Drivers
'HC832
2-609
DESCRIPTION
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
1-5
FUNCTIONAL INDEX/SELECTION GUIDE
SCHMITT-TRIGGER GATES AND INVERTERS
G)
CD
:::s
...
CD
!!.
....5"o
...
DESCRIPTION
Hex Inverters
DEVICE
DESCRIPTIVE
TYPE
TYPE
INFORMATION
Totem-pole
Quad 2-lnput NAND Gates
Quad 2-lnput AND Gates
Quad 2-lnput NOR Gates
Totem-pole
Quad 2-lnput OR Gates
'HCI4
2-57
'HC132
2-159
'HC7001
'HC7002
2-677
2-681
'HC7032
2-685
MULTI-FUNCTION CIRCUITS
3
D)
r+
o·:::s
OUTPUT
DESCRIPTION
Dual D-Type Flip-Flop, Inverter 2-lnput NAND/NOR Combination
DEVICE
DESCRIPTIVE
TYPE
'HC7074
INFORMATION
2-689
SHIFT REGISTERS
DESCRIPTION
INPUTS
OUTPUTS
DEVICE
DESCRIPTIVE
TYPE
INFORMATION
4-Bit Shift Registers with Clear
J-K/Parallel
Parallel
'HC195
2-285
4-Bit Bidirectional Shift Registers with Clear
SerialiParaliel
Parallel
'HC194
2-279
2 Serial
'HC165
2-235
Parallel
'HC164
2-231
Serial
'HC166
2-241
Parallel
'HC594
2-527
3-State Parallel
'HC595
2-533
'HC299
2-389
Serial/Parallel,
Clear, Clock Inhibit,
Shift/Load
8-Bit Shift Registers
2 Serial, Clear
Serial/Parallel,
Clear, Clock Inhibit,
Shift/Load
Serial
8-Bit Shift Registers with Output Registers
3-State Parallel
Serial/Parallel
(Multiplexed I/O)
LATCHES AND REGISTERS
DESCRIPTION
OUTPUT
DEVICE
DESCRIPTIVE
CONFIGURATION
TYPE
INFORMATION
'HC75
2-109
'HC375
2-427
Q only
'HC77
2-117
Q only, 3-State
'HC173
2-247
'HC373
2-407
'HC573
2-501
'HC533
2-451
'HC563
'HCT373
2-483
2-413
'HCT573
2-507
'HCT533
2-457
'HCT563
2-487
'HC259
2-361
Complementary
Quad D-type Latches
auad D-type Registers
a only, 3-State
Octal D-type Latches
0: only,
3-State
a only, 3-State
Octal D-type Latches with TTL-Compatible Inputs
0: only,
8-Bit Addressable Latches
1-6
3-State
a only
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
FUNCTIONAL INDEX/SELECTION GUIDE
-------11
D-TYPE FLIP-FLOPS
OESCRIPTION
Dual D-type Flip-Flops with
OUTPUT
OTHER
CONFIGURATION
FEATURES
Complementary
Preset and Clear
Dual D-type Flip-Flops with
Complementary
2-lnput NAND/NOR Gates
Quad D-type Flip-Flops with
Complementary
Common Clocks
Hex D-type Flip-Flops with
Q only
Common Clocks
Q only
Octal D-type Flip-Flops with
Common Clocks
Independent clocks,
Preset, and Clear
'HCT74
2-105
'HC7074
2-689
Common Clear
'HC175
2-253
Output Enable
'HC379
2-431
Common Clear
'HC174
2-253
Output Enable
'HC378
2-431
Common Clear
'HC273
2-371
Output Enable
'HC377
2-431
'HC374
2-417
'HC574
2-511
'HC534
2-461
'HC564
2-491
'HCT374
2-423
'HCT574
'HCT534
2-517
2-467
'HC564
2-491
'HCT564
2-497
Independent clocks,
Preset, and Clear
Output control
3-State, Q only
Output control
Output control
with Common Clocks and
3-State, Q only
TTL-Compatible Inputs
OESCRIPTIVE
INFORMATION
TYPE
'HC74
3-State, Q only
3-State, Q only
Octal D-type Flip-Flops
DEVICE
Output control
2-101
c
o
'';:;
CO
...E
o
.E
DUAL J-K FLIP-FLOPS
DESCRIPTION
Dual J-K Flip-Flops with Clear
Dual J-K Flip-Flops with Preset
Dual J-K Flip-Flops with Preset, Common Clock, and Common Clear
Dual J-K Flip-Flops with Preset and Clear
Dual J-K Flip-Flops with Preset and Clear
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
DEVICE
DESCRIPTIVE
TYPE
INFORMATION
'HC73
2-97
'HC107
2-133
'HCl13
2-145
'HC78
2-121
'HCl14
2-149
'HC76
2-113
'HCl12
2-141
'HC109
2-137
1-7
FUNCTIONAL INDEX/SELECTION GUIDE
m- - - - - - BUS DRIVERS AND TRANSCEIVERS WITH 3-STATE OUTPUTS
DESCRIPTION
Quad Bus Drivers/Receivers
Quad Bus Transceivers
OUTPUT
CONTROL
DEVICE
DESCRIPTIVE
DATA
INPUTS
TYPE
INFORMAnON
'HC125
'HC126
'HC242
'HC243
'HC365
2-153
2-153
True
Inverting
True
True
Hex Bus Drivers/Receivers
Inverting
True
Inverting
Inverting
Octal Bus Drivers/Receivers
True
Inverting
Octal Bus Transceivers
True
Inverting
True and
Inverting
Individual Enables
Independent Enables
for A or B Buses
Common Enables
Symmetrical Enables
Symmetrical Enablas
2 Enables
Complementary Enables
Symmetrical· Enables
2 Enables
True
Inverting
Inverting
True
'-8
'HC368
'HC240
'HC540
'HC241
'HC244
2-401
2-401
2-401
2-401
2-311
2-471
2-311
'HC541
'HC620
2-327
2-471
2-539
'HC623
'HC640
2-539
2-547
Enable and
Direction Control
'HC643
2-547
'HC645
'HC245
Enable and
Direction Control
Independent Enables
for A or B Buses
'HC646
'HC648
'HC651
2-547
2-335
2-559
Independent Enables
for A or B Buses
True
Octal Bus Transceivers with Registers
'HC366
'HC367
2-321
2-321-
TEXAS ~
INSTRUMENTS
POST OffiCE BOX 655012 • OAUAS. TEXAS 75265
'HC652
2-559
2-573
2-573
FUNCTIONAL INDEX/SELECTION GUIDE
-------11
BUS DRIVERS AND TRANSCEIVERS WITH 3-STATE OUTPUTS AND TTL-COMPATIBLE INPUTS
DESCRIPTION
OUTPUT
CONTROL
DEVICE
DESCRIPTIVE
DATA
INPUTS
TYPE
INFORMATION
Symmetrical Enables
'HCT240
2-317
Inverting
2 Enables
'HCT540
2-477
Complementary Enables
'HCT241
2-317
Symmetrical Enables
'HCT244
'HCT541
2-331
2 Enables
Inverting
Independent Enables
'HCT620
2-543
True
for A and B Buses
'HCT623
2-543
'HCT640
2-553
Octal Bus Drivers/Receivers
True
Inverting
True and
Octal Bus Transceivers
Inverting
o
'';:;
CIS
...oE
....c
-ca
...
Q)
C
Enable and
Direction Control
True
Octal Bus Transceivers with Registers
2-477
c
'HCT643
2-553
'HCT645
2-553
'HCT245
2-339
True
Enable and
'HCT646
2-567
Inverting
Direction Control
'HCT648
2-567
Inverting
Independent Enables
'HCT651
2-581
True
for A and B Buses
'HCT652
2-581
Q)
Cl
ASYNCHRONOUS (RIPPLE-CLOCK) COUNTERS
DEVICE
DESCRIPTIVE
TYPE
INFORMATION
7-Bit Binary Counters
'HC4024
2-635
12-Bit Binary Counters
'HC404O
2-639
'HC4020
2-631
DESCRIPTION
14-Bit Binary Counters
Dual Decade Counters
FEATURES
On-Chip Oscillator
'HC4060
2-643
Biquinary or BCD
'HC390
2-439
Set-to-9 input
'HC490
2-447
'HC393
2-439
Dual 4-Bit Binary Counters
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1-9
FUNCTIONAL INDEX/SELECTION GUIDE
SYNCHRONOUS COUNTERS
G)
DESCRIPTION
CD
FEATURES
::::s
CD
iS"
....
o
..3
....
CI)
o·
::::s
Async Clear
Sync Clear
Decade
Synchronous Load
Clock Inhibit
Async Clear
Async Clear
Async Clear
Decade Up/Down
Divide-by-l0 Johnson Counter
4-Bit Binary
Asynchronous Load
Synchronous Load
Sync Clear
Clock Inhibit
4-Bit Binary Up/Down
Asynchronous Load
Async Clear
Sync Clear
8-Bit Binary with Output Registers
3-State Outputs
DEVICE
TYPE
'HC160
'HC162
'HC190
'HC192
'HC4017
'HC161
'HC163
'HC191
'HC193
'HC590A
DESCRIPTIVE
INFORMATION
2-217
2-217
2-263
2-271
2-625
2-217
2-217
2-263
2-271
2-521
MAGNITUDE COMPARATORS. PARITY GENERATORS/CHECKERS. AND PARITY ENCODERS
DESCRIPTION
FEATURES
4-Bit Magnitude Comparators
8-Bit Magnitude Comparators
P - Q, P > Q Outputs
P = Q Outputs
9-Bit Odd/Even Parity
Even, Odd Inputs
L Enable Inputs
Generators/Checkers
8-Line to 3-Line Priority Encoders
10-Line Decimal to 4-Line
Enable Inputs and Outputs
BCD Priority Encoders
DEVICE
TYPE
'HC85A
'HC682
'HC688
'HC180
'HC280
'HC148
DESCRIPTIVE
INFORMATION
2-125
2-593
2-597
2-259
2-375
2-191
'HC147
2-191
ADDRESS COMPARATORS
DESCRIPTION
12-Bit to 4-Bit Address Comparators
1-10
FEATURES
Output Enable
TEXAS ."
INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
DEVICE
TYPE
'HC679
DESCRIPTIVE
INFORMATION
2-587
FUNCTIONAL INDEXISELECTION GUIDE
------------------------A--RI-T-H-M-E-T-IC-C-I-R-C-UI-T-S------------------------~
DEVICE
TYPE
'HC2B3
DESCRIPTIDN
4-Bit Adders
DESCRIPTIVE
INFORMATION
2-379
INPUTS
TYPE
DESCRIPTIVE
INFORMATION
'HC152
'HC151
'HC251
2-201
2-197
2-343
3-State
'HC354
2-395
True,3-State
True
'HC253
'HC153
'HC157
2-349
2-205
2-213
'HC158
'HC257
2-213
2-355
'HC258
'HC298
2-366
2-385
OUTPUTS
Inverting
Complementary
Enable
8-Line to I-Line
Transparent Latches,
Enable
Dual 4-Line to l-Lina
Independent Enables
Quad 2-Line to I-Line
Common Enable
Complementary
True
Inverting
True, 3-State
Inverting, 3-State
Quad 2-Line to I-Line with Storage
True
"';::;
ca
..
.2
E
DATA SELECTORS/MULTIPLEXERS
DESCRIPTION
c
o
DEVICE
.5
"i
.
CD
C
CD
~
DECODERS/DEMULTIPLEXERS
DESCRIPTION
FEATURES
OUTPUTS
2 Enables
4-Line to 16-Line
Inverting
Input Latches,
Output Enable
True
4-Line to 1O-Line BCD-to-Decimal
True
3 Enables
Inverting
3-Line to 8-Line
True
3 Enables,
Address Latches
Dual 2-Line to 4-Line
Inverting
Independent Enables
Inverting
True
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
DEVICE
DESCRIPTIVE
TYPE
INFORMATION
2-209
'HC154
'HC4514
2-667
'HC42
'HC238
'HCT238
2-89
2-299
2-303
'HC13S
'HCT138
'HC237
'HCT237
2-175
2-179
2-291
2-295
'HC137
2-167
'HCT137
'HC139
'HCT139
'HC239
2-171
2-183
2-187
2-307
1-11
D FLlp·FlOP AND LATCH SIGNAL CONVENTIONS
D flip·flop and latch signal conventions
-:::::I
....
..
It is normal TI practice to name the outputs and other inputs of a O-type flip-flop or latch and to draw
its logic symbol based on the assumption of true data (0) inputs. Outputs that produce data in phase with
the data inputs are called 0 and those producing complementary data are called O. An input that causes
a 0 output to go high or a 0 output to go low is called Preset (PRE). An input that causes a 0 output to
go high or a 0 output to go low is called Clear (CLR). Bars are used over these pin names (PRE and CLR)
if they are active-low.
o
3
The devices on several data sheets are second-source designs, and the pin-name conventions used by
the original manufacturers have been retained. That makes it necessary to designate the inputs and outputs
of the inverting circuits 0 and O.
r+
In some applications, it may be advantageous to redesignate the data input from 0 to 0 or vice versa.
In that case, all the other inputs and outputs should be renamed as shown below. Also shown are
corresponding changes in the graphical symbols. Arbitrary pin numbers are shown in parentheses.
I»
o·:::::I
(5) Q
(6)
R
a
ClR
R
C1
jj
10
PRE
PRE
(5) Q
ClR
ClK
(6)
a
(5)
C1
jj
(6)
PRE
ClR
a
Q
LATCH
C1
0
(6)
5
lATCH
ClK
(5)
C
a
Q
FLlp·FLOP
FLIp· FLOP
The figures show that when 0 and 0 exchange names, the Preset and Clear pins also exchange names.
The polarity indicators (t::..) on PRE and CLR remain, as these inputs are still active-low, but the presence
or absence of the polarity indicator changes at 0 (or 0). 0, and O. Pin 5 (0 or 0) is still in phase with
the data input (0 or 0); their active levels change together.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
EXPLANATION OF FUNCTION TABLES
The following symbols are used in function tables on TI data sheets:
H
high level (steady state)
L
low level (steady state)
t
c
transition from low to high level
transition from high to low level
value/level or resulting value/level is routed to indicated destination
value/level is re·entered
x
z
off (high·impedance) state of a 3-state-output
a .. h
the level of steady-state inputs at inputs A through H respectively
irrelevant (any input, including transitions)
00
level of 0 before the indicated steady-state input conditions were established
complement of 00 or level of CI before the indicated steady-state input conditions were established
o
c
ca
...
C
CI)
CJ
level of 0 before the most recent active transition indicated by tort
JL
one high·level pulse
Lr
one low-level pulse
TOGGLE
E
...
CI)
ClO
On
o
ca
'';::;
each output changes to the complement of its previous level on each active transition indicated by
~ or t.
If, in the input columns, a row contains only the symbols H, L, and/or X, this means the indicated output is valid whenever the input configuration is achieved and regardless of the sequence in which it is achieved. The output persists so
long as the input configuration is maintained.
If, in the input columns, a row contains H, L, and/or X together with t and/or t this means the output is valid whenever the input configuration is achieved but the transition(s) must occur following the achievement of the steady-state
levels. If the output is shown as a level (H, L, 00, or 00), it persists so long as the steady-state input levels and the
levels that terminate indicated transitions are maintained. Unless otherwise indicated, input transitions in the opposite
direction to those shown have no effect at the output. (If the output is shown as a pulse,rLor LS,the pulse
follows the indicated input transition and persists for an interval dependent on the circuit.)
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1-13
EXPLANATION OF FUNCTION TABLES
C)
CD
j
CD
..
-....
o..
3
Among the most complex function tables in this book are those of the shift registers. These embody most of the
symbols used in any of the function tables, plus more. Below is the function table of a 4·bit bidirectional universal
shift register, e.g., type SN74194.
FUNCTION TABLE
INPUTS
!!.
CLEAR
0"
j
rS1- -SO-
CLOCK
SERIAL
OUTPUTS
PARALLEL
A
B
C
D
°A
aB
ac
aD
L
X
X
X
X
X
X
X
X
X
L
L
L
L
H
X
X
L
X
X
X
X
X
X
aBO
H
H
H
I
X
X
a
b
c
d
oAO
a
H
L
H
1
X
H
X
X
X
X
H
aAn aBn aCn
H
L
H
I
X
L
X
X
X
X
L
oAn
oBn
oCn
H
H
L
I
H
X
X
X
X
X
oBn
oCn
oDn
H
H
H
L
I
L
X
X
X
X
X
oBn
oCn
oDn
L
H
L
L
X
X
X
X
X
X
X
oAO
aBO
Oco
aDO
j
m
~
MODE
LEFT RIGHT
b
oCO aDO
c
d
The first line of the table represents a synchronous clearing of the register and says that if clear is low, all four outputs
will be reset low regardless of the other inputs. In the following lines, clear is inactive (high) and so has no effect.
The second line shows that so long as the clock input remains low (while clear is high), no other input has any effect
and the outputs maintain the levels they assumed before the steady·state combination of clear high and clock low was
established. Since on other lines of the table only the rising transition of the clock is shown to be active, the second line
implicitly shows that no further change in the outputs will occur while the clock remains high or on the high·to·low
transition of the clock.
The third line of the table represents synchronous parallel loading of the register and says that if Sl and SO are both
high then, without regard to the serial input, the data entered at A will be at output 0A, data entered at B will be at
0B, and so forth, following a low·to·high clock transition.
The fourth and fifth lines represent the loading of high· and low·level data, respectively, from the shift·right serial input
and the shifting of previously entered data one bit; data previously at 0A is now at OB, the previous I.evels of 0B and
Oc are now at Oc and OD respectively, and the data previously at OD is no longer in the register. This entry of serial
data and shift takes place on the low·to·high transition of the clock when Sl is low and SO is high and the levels at
inputs A through D have no effect.
The sixth and seventh lines represent the loading of high· and low·level data, respectively, from the shift·left serial input
and the shifting of previously entered data one bit; data previously at OB is now at OA, the previous levels of Oc and
OD are now at OB and OC, respectively, and the data previously at OA is no longer in the register. This entry of serial
data and shift takes place on the low·to·high transition of the clock when Sl is high and SO is low and the levels at
inputs A through D have no effect.
The last line shows that as long as both mode inputs are low, no other input has any effect and, as in the second line,
the outputs maintain the levels they assumed before the steady-state combination of clear high and both mode inputs
low was established.
The function table functional tests do not reflect all possible combinations or sequential modes.
1-14
. TEXAS""
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
-------11
INTRODUCTION
These symbols, terms, and definitions are in accordance with those currently agreed upon by the JEOEC Council of
the Electronic Industries Association (EIA) for use in the USA and by the International Electrotechnical Commission
(lEC) for international use.
OPERATING CONDITIONS AND CHARACTERISTICS liN SEQUENCE BY LETTER SYMBOLS)
Ci
Input capacitance
The internal capacitance at an input of the device.
Cpd
Power dissipation capacitance
Used to determine the n9-load dynamic power dissipation per logic function (see individual circuit pages):
Po = Cpd Vce 2 f+lee Vee·
f max
Maximum clock frequency
The highest rate at which the clock input of a bistable circuit can be driven through its required sequence
while maintaining stable transitions of logic level at the output with input conditions established that should
cause changes of output logic level in accordance with the specification.
ICC
Supply current
The current into' the Vce supply terminal of an integrated circuit.
IIH
High-level input current
The current into' an input when a high-level voltage is applied to that input.
IlL
Low-level input current
The current into' an input when a low-level voltage is applied to that input.
IOH
High-level output current
The current into' an output with input conditions applied that, according to the product specification, will
establish a high level at the output.
IOL
Low-level output current
The current into' an output with input conditions applied that, according to the product specification, will
establish a low level at the output.
IOZ
Off-state (high-impedance-state) output current (of a three-state output)
The current flowing into' an output having three-state capability with input conditions established that,
according to the production specification, will establish the high-impedance state at the output.
ta
Access time
The time interval between the application of a specified input pulse and the availability of valid signals at
an output.
tdis
Disable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms, with
the three-state output changing from either of the defined active levels (high or low) to a high-impedance
(off) state. (tdis = tpHZ or tpLZ)·
c
o
',i::
as
..E
o
.5
'!
G)
cG)
e"
·Current out of a terminal is given as a negative value.
TEXAS . "
INSTRUMENTS
POST OFFICE 80X 655012 • DALLAS. TEXAS 75265
1-15
GLOSSARY
SYMBOLS. TERMS. AND DEFINITIONS
ten
Enable time (of a three-state outputl
The time interval between the specified reference points on the input and output voltage waveforms, with
the three-state output changing from a high-impedance (off) state to either of the defined active levels (high
or low). (ten = tpZH or tpZL.)
Fall time
The time interval between two reference points (90% and 10% unless otherwise specified) on a waveform
that is changing from the defined high level to the defined low level.
Hold time
The time interval during which a signal is retained at a specified input terminal after an active transition occurs
at another specified input terminal.
NOTES: 1. The hold time is the actual time interval between two signal events and is determined by the
system in which the digital circuit operates. A minimum value is specified that is the shortest
interval for which correct operation of the digital circuit is guaranteed.
2.
The hold time may have a negative value in which case the minimum limit defines the longest
interval (between the release of the signal and the active transition) for which correct operation
of the digital circuit is guaranteed.
tpd
Propagation delay time
The time between the specified reference points on the input and output voltage waveforms with the output
changing from one defined level (high or low) to the other defined level. (tpd = tpHL or tPLH).
tPHL
Propagation delay time, high-to-Iow level output
The time between the specified reference points on the input and output voltage waveforms with the output
changing from the defined high level to the defined low level.
tpHZ
Disable time (of a three-state output) from high level
The time interval between the specified reference points on the input and the output voltage waveforms with
the three-state output changing from the defined high level to a high-impedance (off) state.
tpLH
Propagation delay time, low-to-high-Ievel output
The time between the specified reference points on the input and output voltage waveforms with the output
changing from the defined low level to the defined high level.
tpLZ
Disable time (of a three-state outputl from low level
The time interval between the specified reference points on the input and output voltage waveforms with
the three-state output changing from the defined low level to a high-impedance (off) state.
tpZH
Enable time (of a threa-stata output) to high level
The time interval between the specified reference points on the input and output voltage waveforms with
the three-state output changing from a high-impedance (off) state to the defined high level.
tPZL
Enable time (of a three-state output) to low level
The time interval between the specified reference points on the input and output voltage waveforms with
the three-state output changing from a high-impedance (off) state to the defined low level.
tr
Rise time
The time interval between two reference points (10% and 90% unless otherwise specified) on a waveform
that is changing from the defined low level to the defined high level.
1-16
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
GLOSSARY
SYMBOLS. TERMS. AND DEFINITIONS
tau
Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent active
transition at another specified input terminal.
NOTES: 1. The setup time is the actual time interval between two signal events and is determined by the
system in which the digital circuit operates. A minimum value is specified that is the shortest
interval for which correct operation of the digital circuit is guaranteed.
2.
The setup time may have a negative value in which case the minimum limit defines the longest
interval (between the active transition and the application of the other signal) for which correct
operation of the digital circuit is guaranteed.
Traanition time (general)
The time interval between two reference points (10% and 90% unless otherwise specified) on a waveform
that is changing from the defined low level to the defined high level (rise time) or from the defined high level
to the defined low level (fall time).
tw
Pulse duration (width)
The time interval between specified reference points on the leading and trailing edges of the pulse waveform.
VIH
High-level input voltage
An input voltage within the more positive (less negative) of the two ranges of values used to represent the
binary variables.
NOTE: A minimum is specified that is the least-positive value of high-level input voltage for which operation
of the logic element within specification limits is guaranteed.
VIL
Low-level input voltage
An input voltage level within the less positive (more negative) of the two ranges of values used to represent
the binary variables.
NOTE: A maximum is specified that is the most-positive value of low-level input voltage for which operation
of the logic element within specification limits is guaranteed.
VOH
High-level output voltage
The voltage at an output terminal with input conditions applied that, according to product specification, will
establish a high level at the output.
VOL
Low-level output voltage
The voltage at an output terminal with input conditions applied that, according to product specification, will
establish a low level at the output.
VT +
Positive-going threshold level
The voltage level at a transition-operated input that causes operation of the logic element according to
specification as the input voltage rises from a level below the negative-going threshold voltage, VT _.
VT _
Negative-going threshold level
The voltage level at a transition-operated input that causes operation of the logic element according to
specification as the input voltage falls from a level above the positive-going threshold voltage, VT + .
TEXAS
~
INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
c
o
ca
.~
E
o
:s
.
'ii
CD
C
CD
~
1-17
-....
:::J
o
3
~
I»
r+
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:::J
1-18
PARAMETER MEASUREMENT INFORMATION
--------FROM OUTPUT _ _ _4 .... TEST
UNDER TEST
tOINT
. .
c
---+--VCC
lCL
o
"';:::
C\'J
PARAMETER
or
tpd
I
Standard outputs
tt
I
High-current outputs ~
50 pFt
50 pF or 150 pF
.5
"!CD
LOAD CIRCUIT
c
t CL includes probe and test fixture capacitance.
FIGURE 2. OPEN-DRAIN OUTPUTS
FIGURE 1. TOTEM-POLE OUTPUTS
PARAMETER
TEST
.e
rCL -
CL t
50 pF
t CL includes probe and test fixture capacitance.
tHigh-current outputs are indicated by the C> in the logic symbol.
FROMOUTPUT _ _ _P~O.IN_T_~RL~_--.
UNDER TEST
E
...
TEST
FROM OUTPUT
UNDER TEST - - - . POINT
LOAD CIRCUIT
ten
-
RL
tpZH
1 kll
tpZL
tdis
tpHZ
~
CL t
81
82
50 pF
OPEN
CLOSED
or
150 pF
1 kll
CD
CJ
50 pF
CLOSED
OPEN
OPEN
CLOSED
CLOSED
OPEN
OPEN
OPEN
50 pF
tpd or tt
-
or
150 pF
LOAD CIRCUIT
t CL
includes probe and test fixture capacitance.
FIGURE 3. 3-STATE OUTPUTS
TEXAS
~
INSTRUMENTS
POST OFFICE BOK 655012 • DALLAS, TeXAS 75265
1-19
PARAMETER MEASUREMENT INFORMATION
.------~::UE:ENeE
______
Q
!
CD
!.
\,,_ _-_-_ ::e
!4--tsu---+l
I
I
I
DATA~90%
:r
0'
3
...s·
/50%
..J t t ' - - - - - - t h - - - - - - - . ! . I
INPUT
50%
10%
I
90%7\:1
-- -
I
I
I
I
I
~tr
-
-
Vee
50%
10%
OV
\.-.l-tf
I»
VOLTAGE WAVEFORMS
~
NOTE 1: Phase relationships betwaen waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR s 1 MHz. Zout =- SO n. tr = 6 ns, tf = 6 ns.
FIGURE 4. HC AND HCU - SETUP AND HOLD TIMES. AND INPUT RISE AND FALL TIMES
HIGH-LEVEL
PULSE
---- ::e
1:
\-_______1:.0~ ____
50
~O:-
%
14
tw, - - -...1
14
tw
~
I
LOW-LEVEL
PULSE
Vee
ov
VOLTAGE WAVEFORMS
NOTES:
1. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR :s 1 MHz, Zout = 50 n, tr = 6 ns, tf = 6 ns.
2. For clock inputs, f max is measured when the input duty cycle is 50%.
FIGURE 5. HC AND HCU - PULSE DURATIONS
1-20
TEXAS
~
INSTRUMENTS
POST OfFICE BOX 655012 • DALLAS, TeXAS 75265
PARAMETER MEASUREMENT INFORMATION
-------11
INPUTJ,.5-0%-------------"""'\:-0%- - - -
-
-
---
:~e
c
1
I
I
:
1
I
{:190%
50%1
10%
1
1
I
90%~1
1
-- 150%
10%
I
I
,
~'rt
14---- 'PH L ----..r
I
,
ttl
1
50%
I
'f
VOL
14----'PLH---.t
------""""::9:::0%~!\;'
OOW~
VOH
~~~'-f--
,
,
OUT -OF-PHASE
'';::
CO
14--'PH L~
I4----'PLH ----+I
IN-PHASE
OUWUT
o
I
50%
10%
.I!:~9:::0%::--- VOH
I
f- - - -
10%
VOL
~'rt
--+r--f4-
......Eo
.5
~
Q)
C
Q)
o
VOLTAGE WAVEFORMS
Itr is not applicable to SN54/74HCu' devices.
NOTE1: Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR :s; 1 MHz, Zout :::: 50 0, tr = 6 n5, tf = 6 ns.
FIGURE 6. HC AND HCU -
~I
OUTPUT CONTROL
(low-level enabling)
PROPAGATION DELAY TIMES AND OUTPUT TRANSITION TIMES
f
50%
Vee
50%
1-------------:- -
----.r
1-:-__
I4--'PZL
OUTPUT
WAVEFORM 1
(See No,e 2)
-
-
-
-
-
-
--- 0 V
j4--'PLZ---.t
I
"'Vee
!/
\.._____--;.____~-f1O~ _ _ -
"'vee
\50%
I,
I
-
VOL
1Ir----------r-------,
14-- 'PZH---+I
OUTPUT
WAVEFORM 2
(See No,e 2) _ _ _ _ _ _ _ _J
50
~-----VOH
%
I4---tpHZ~
'" 0 V
VOL TAGE WAVEFORMS
NOTES:
1. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR .s: MHz, lout :::: 50 0, t f = 6 n5, tf = 6 n5.
2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
FIGURE 7, HC AND HCU -
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
1-21
PARAMETER MEASUREMENT INFORMATION
.------~====~~~::~:ENCE
vi
\ . .____ v
3
1.3
Ci)
CD
::J
CD
.
MI4-----th-----~~1
I4-- t su--+l
I
0V
!.
I~~--------------------~~
I 7\:,'----DATA~2.7V
2.7V
5'
INPUT
a-..
...0'3
1.3V
O.3V
I
I
f.-.I-
I
I
1.3V
O.3V
:..I-
tr
3V
OV
tf
S»
VOLTAGE WAVEFORMS
::J
NOTE 1: Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR '" 1 MHz. Zout ~ 50 D, tr = 6 ns, tf = 6 ns.
FIGURE 8. HCT - SETUP AND HOLD TIMES, AND INPUT RISE AND FALL TIMES
HI~~~:~EL
Jluv
_____
);,~
----::
1414----tw---+l~1
\..
~14----tw----~~
LOW·LEVEL
PULSE
VOLTAGE WAVEFORMS
'-'~
__ n::
NOTES: 1. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR '" 1 MHz. Zout = 50 D. tr = 6 ns, tf = 6 ns.
2. For clock inputs, f max is measured when the input duty cycle is 50%.
FIGURE 9. HCT - PULSE DURATIONS
1-22
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
PARAMETER MEASUREMENT INFORMATION
\~3-:- - - -
INPUT-.iI.3V
IN-PHASE
OUTPUT
-
I
i+---tPLH~
I
tf--tPHL~
I
I
I
I
/i90%
1.3V
10%_ I
~tr
I
I
------~9::;:0%~T\;
I 1.3 V
CO
-
VOH
~tf
c
VOL
i'
I
13V
10%
JIO..'.;.;.;.----------=....
-tt--l+I
10%
I
tf
..oE
..
I
i+---tpLH~
I4---tPHL--.I
OUT ·OF·PHASE
OUTPUT
c
...o
9o%KI - - I 1.3V
:
10%
i
I
I
I
-- - - - : :
"ii
.Ir::-::90:::%::--- VOH
Q)
C
I
f- - - -
Q)
VOL
~tr
~
VOLTAGE WAVEFORMS
NOTE 1: Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR :s 1 MHz, Zout ::: 50 0, tr = 6 n5, tf = 6 ns.
FIGURE 10. HCT - PROPAGATION DELAY TIMES, OUTPUT RISE AND FALL TIMES
f r----------
~I1'3 V
1.3 V
'-----------.J-i- - - - - - - - - --
OUTPUT CONTROL
I Low·level enabling I
I
I
II
I
I
I
~1.3V
!/
' \.....______T-_ _ _ _..-fl~ _ _ -
1
"'Vee
-
K-----
I+--tPZH---"
I
OUTPUT
WAVEFORM 2_ _ _ _ _ _ _ _ _..J
(See Not. 21
•
0V
~tpLZ--+I
I4---tPZL--+I
OUTPUT
WAVEFORM 1
(See Not. 21
3V
1.3 V
I*--- tpHZ~
VOL
VOH
'" 0 V
VOLTAGE WAVEFORMS
NOTES:
1. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR '" 1 MHz, Zout '" 50 0, tr ~ 6 ns, tf ~ 6 ns.
2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
FIGURE 11, HCT - ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1-23
G)
CD
:::l
...
CD
Q)
-...
:::l
o
3Q)
r+
o·
:::l
1-24
Numerical Index
Functional Index
D Flip-Flop and Latch Signal Conventions
Explanation of Function Tables
Glossary
Parameter Measurement Information
HCMOS Devices
Ordering Instructions
Mechanical Data
Tape and Reel Information
IC Sockets
2-1
::J:
o
s::
otn
o
CD
<
5'
CD
(I)
2-2
SN54HCDD, SN74HCDD
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
02684, DECEMBER 1982-REVISED MARCH 1984
•
•
SN54HCOO .. , J PACKAGE
SN74HCOO , .. 0 OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
Dependable Texas Instruments Quality and
Reliability
description
These devices contain four independent 2-input
NAND gates, They perform the Boolean
functions Y = A·B or Y =A + B in positive logic,
GND
SN54HCOO .. , FK PACKAGE
The SN54HCOO is characterized for operation
over the full military temperature range of
-55°C to 125°C, The SN74HCOO is
characterized for operation from - 40°C to
85°C,
(TOP VIEW)
18
2A
28
3A
38
4A
48
(1)
CD
1 20 19
4A
1Y
4
18
5
17
NC
2A
6
16
4Y
15
NC
8
14
3B
OUTPUT
NC
B
Y
2B
H
L
L
H
X
H
X
L
H
9 1011 12 13
o
C/)
o
~
o
l:
>-OU>- Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 mA
eontinuous current through Vee or GND pins ........ , . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6mm (1/16 in) from case for 60 s: FK or J package ............... 300 0 e
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ............... 260 0 e
Storage temperature range ......................................... - 65 °e to 150 0 e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(")
s:o
recommended operating conditions
SN54HCOO
MIN NOM MAX
2
5
6
tJ)
cCD
Vee Supply voltage
(;'
VIH High-level input voltage
Vee = 2 V
Vee = 4.5 V
Vil low-level input voltage
Vee = 6 V
Vee = 2 V
Vee = 4.5 V
<
CD
en
1.5
3.15
4.2
0
Input voltage
Vo
Output voltage
tt
Input transition (rise and fall) times
Vee = 2 V
Vee = 4.5 V
Vee
Vee
1000
500
0
0
-55
Vee = 6 V
Operating free-air temperature
TA
1.2
0
0
0
0
Vee = 6 V
VI
0.3
0.9
0
400
125
SN74HCOO
MIN
2
1.5
NOM
5
3.15
4.2
0
MAX
6
UNIT
V
V
0.3
0
0.9
1.2
V
0
0
0
0
Vee
Vee
1000
V
V
0
0
500
400
ns
-40
85
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
vCC
2V
2-4
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.48
5.80
0.002
0.001
1.9
4.4
1.9
4.4
5.9
3.7
5.2
5.9
3.84
5.34
10H = -20 p.A
VI = VIH or Vil.
VI = VIH or Vil.
10H = -4 mA
10H = -5.2 mA
VI = VIH or Vil.
10l = 20 p.A
6V
2V
4.5 V
VI = VIH or Vil.
VI = VIH or Vil.
VI = Vee or 0
10l = 4 mA
IOl = 5.2 rnA
6V
4.5 V
6V
0.001
0.17
0.15
0.26
0.26
6V
±0.1
3
VOL
lee
ei
SN54HCOO
MIN MAX
VI = VIH or Vil.
VOH
II
TA - 25°C
MIN
TYP MAX
VI = Vee or O. 10 - 0
4.5 V
6V
4.5 V
6V
2 to 6 V
SN74HCOO
MIN MAX
V
0.1
0.1
0.1
0.1
0.1
0.1
0.33
0.33
±100
0.4
0.4
±1000
2
10
40
10
0.1
0.1
0.1
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • QALLAS. TeXAS 75265
UNIT
±1000
20
10
V
nA
~A
pF
SN54HCOO, SN74HCOO
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
TO
(INPUT)
(OUTPUT)
A or B
Y
Y
vCC
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25·C
MIN
TYP MAX
45
9
8
38
8
6
Power dissipation capacitance per gate
90
18
15
75
15
13
No load, TA
SN54HCOO
SN74HCOO
MIN
MIN
MAX
135
27
23
110
22
19
= 25°C
MAX
115
23
20
95
19
16
UNIT
ns
ns
II
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-5
J:
(')
s:
oen
cCD
<
5'
CD
til
2-6
SN54HCTOO. SN74HCTOO
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
D3243, NOVEMBER 1988
SN54HCTOO ... J PACKAGE
SN74HCTOO ... 0 OR N PACKAGE
•
Inputs are TTL-Voltage Compatible
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
1A
VCC
1B
4B
1Y
4A
Dependable Texas Instruments Quality and
Reliability
2A
4Y
•
(TOP VIEW)
description
These devices contain four independent 2-input
NAND gates. They perform the Boolean
functions Y = A-B or Y = A + B in positive logic.
B
H
H
L
L
X
H
L
2B
3A
3B
4A
4B
U)
Q)
(.)
Q)
c
1 20 19
UJ
1Y
18
4A
NC
17
NC
2A
16
4Y
NC
15
NC
(.)
14
3B
::I:
8
o
:!E
1011 12 13
Y
A
2
•
-:;
U
U (]]
z>'- OU >-<1:
N
zz
t:J
"''''
NC - No internal connection
H
logic diagram (each gate) (positive logic)
logic symbol t
2A
3Y
OUTPUT
INPUTS
(1 )
GND
(]] <1: U
(each gate)
1B
3A
(TOP VIEW)
FUNCTION TABLE
1A
3B
2Y
SN54HCTOO ... FK PACKAGE
The SN54HCTOO is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCTOO is
characterized for operation from - 40°C to
85°C.
X
2B
&
(2)
1Y
(4)
15)
2Y
19)
(101
3Y
(121
(131
4Y
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
PRODUCTION DATA documonts contain information
currant as of publication date. PrlHluets conform to
specifications per the terms of Taxas Instruments
=~~~~:~~i~a{::1~1i ~!:~:~ti:; !i~O:=:::':~~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © 1988, Texas Instruments Incorporated
2-7
SN54HCTOO, SN74HCTOO
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
absolute maximum ratings over operating free-air temperature range t
-0.5 V to 7 V
± 20 mA
Supply voltage, Vec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0 or VI > Vce.·. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Output clamp current, 10K (VO < 0 or Vo > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Input clamp current, 11K (VI
<
± 20 mA
± 25 mA
± 50 mA
Continuous current through Vce or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 105: 0 or N package . . . . . . . . . . . . . . .
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 De to
::J:
(")
s:
o
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absoluteMrnaximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HCTOO
MIN
4.5
en
vee
Supply voltage
<
VIH
VIL
VI
High-level input voltage
low-level input voltage
Vo
Output voltage
tt
TA
Input transition (rise and fall) times
c
(1)
ri"
(1)
(I)
300 De
260 DC
150 DC
I Vee
I Vee
~ 4.5 V to 5.5 V
2
~ 4.5 V to 5.5 V
0
NOM
5
0
0
Input voltage
MIN
4.5
2
0.8
0
0
0
Vec
Vee
500
0
-55
Operating free-air temperature
SN74HCTOO
MAX
5.5
125
NOM
5
MAX
5.5
UNIT
V
Vee
V
v
v
vee
500
v
ns
85
°e
0.8
0
-40
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
VOL
II
lee
~Iee;
TEST CONDITIONS
VI
~
VIH or VIL.
VI ~ VIH or VIL.
VI - VIH or VIL.
VI ~ VIH or VIL.
VI ~ Vee or 0
IOH
IOH
~
IOL
IOL
~
-20 ~A
-4 mA
~
~
vCC
20 ~A
4 mA
4.5 V
4.5 V
4.5 V
4.5 V
5.5 V
10 ~ 0
VI - Vee or O.
One input at 0.5 V or 2.4 V.
TA - 25°C
MIN
TYP MAX
4.4 4.499
3.98
4.3
Other inputs at 0 V or Vee
0.001
0.17
±0.1
SN74HCTOO
MIN
4.4
MAX
UNIT
V
3.84
0.1
0.26
±100
0.1
0.4
±1000
0.33
±1000
2
40
20
~A
1.4
2.4
3
2.9
mA
3
10
10
10
pF
4.5 to
ei
4.4
3.7
5.5 V
5.5 V
SN54HCTOO
MIN MAX
5.5 V
0.1
:t:This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or
V
nA
Vee.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(INPUT)
AorB
TO
(OUTPUT)
vCC
Y
4.5 V
5.5 V
Y
4.5 V
5.5 V
TA - 25°C
TYP MAX
MIN
11
20
10
9
8
Power dissipation capacitance per gate
SN54HCTOO
MIN
18
15
14
No load. TA
MAX
30
27
22
SN74HCTOO
MIN MAX
25
20
~
25°e
NOTE 1: Load circuit and voltage waveforms are shown in Section 1 of the High-Speed CMOS Logic Data Book. 1988.
2-8
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
22
19
17
UNIT
ns
ns
SN54HC01. SN14HC01
QUADRUPLE 2·INPUT POSITIVE·NAND GATES
WITH OPEN·DRAIN OUTPUTS
02864. SEPTEMBER 1984-REVISEO SEPTEMBER 1987
•
•
SN54HCOI •.. J PACKAGE
SN74HCOI ..• D OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
(TOPVIEWI
1Y
1A
18
2Y
2A
28
Dependable Texas Instruments Quality and
Reliability
description
These devices contain four independent 2-input
NAND gates. They perform the Boolean
functions Y = A· B or Y = Ii. + B in positive logic.
The open-drain outputs require pull-up resistors
to perform correctly. They may be connected to
other open-drain outputs to implement activelow wired-OR or active-high wired-AND
functions.
VCC
4Y
48
4A
3Y
38
3A
SN54HCOI •.. FK PACKAGE
II
(TOP VIEW)
G)
GND
«
>- U U>--Z>"Ct
3
The SN54HC01 is characterized for operation
over the full military temperature range. of
-55 DC to 125 DC. The SN74HC01 is
characterized for operation from - 40 DC to
85 D C.
2
"S;
G)
c
I 2019
18
4
5
18
17
48
NC
2Y
6
16
4A
NC
NC
15
NC
2A
14
3Y
8
9 10 II 1213
FUNCTION TABLE (each gate)
INPUTS
B
Y
H
H
L
L
X
H
x
L
H
en
o
::E
(,)
J:
CDOU«CD
"'22(')(')
I.!)
OUTPUT
A
en
CJ
U
NC-No internal connection
logic diagram (positive logic)
logic symbol t
lA
lB
2A
2B
3A
3B
4A
4B
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 .~d
lEe Publication 617·12.
Pin numbers shown are for D. J. and N packages.
PRODUCTION DATA ........IIIS ..nlli. iof.rlAlliio.
carrettl " of pu/lliCltien dote. P..ducts _famr to
.pooifiollli... po, the to.....f T.... I._IllS
lII.dard wamlllY. P..d.ati•• (lfGCllling .....at
......rily incl.do tolling of III porllllllrs.
~opyright @
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • QALLAS. TEXAS 75265
1984. Texas Instruments Incorporated
2-9
SN54HC01, SN74HC01
QUADRUPLE 2·INPUT POSITIVE·NAND GATES
WITH OPEN·DRAIN OUTPUTS
absolute maximum ratings over operating free-air temperature range t
•
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 rnA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Continuous output current, 10 (Vo = 0 to Vcc) . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. ± 25 rnA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ...... ;.................................. - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum·rated conditions for extended periods may affect device reliability.
%
(")
s:
o
recommended operating conditions
tn
MIN
C
Vee Supply voltage
CD
<
n'
CD
Vee
Vec
VIH High-level input voltage
Vee
en
Vee
Vee
Low-level input voltage
VIL
Vee
VI
Va
Input voltage
Output voltage
tt
Input transition Irise and fall) times
Vee
Vee
Vee
2
1.5
3.15
4.2
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
5
6
MIN
SN74HC01
NOM MAX
2
1.5
3.15
4.2
5
6
UNIT
V
V
0
0.3
0
0.3
0
0
0.9
1.2
0
0
0.9
1.2
V
0
0
0
0
Vee
Vee
1000
0
0
0
Vee
Vee
1000
V
V
0
500
400
ns
85
·e
500
400
0
-55
Operating free-air temperature
TA
SN64HC01
NOM MAX
125
0
-40
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
10H
TEST CONDITIONS
lee
ei
2-10
TA = 25°C
TYP MAX
MIN
0.Q1
0.5
0.1
0.1
0.1
VI
=
VIH or VIL.
Va
=
Vee
6V
2V
0.002
VI
=
VIH or VIL.
IOL
= 20 ~A
4.5 V
6V
VI
VI
VI
VI
= VIH or VIL. 10L = 4 mA
= VIH or VIL. 10L = 5.2 mA
= 0 or Vee
= Vee or 0.10 = 0
0.001
0.001
0.17
VOL
II
VCC
4.5 V
6V
6V
6V
2 to 6 V
TEXAS
0.15
±0.1
3
0.26
0.26
±100
2
10
-1!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC01
MIN MAX
SN74HC01
MAX
MIN
10
5
0.1
0.1
0.1
0.1
0.4
0.1
0.1
0.4
0.33
0.33
±1000
40
10
±1000
20
10
UNIT
pA
V
nA
~A
pF
SN54HC01, SN74HC01
QUADRUPLE 2·INPUT POSITIVE·NAND GATES
WITH OPEN·DRAIN OUTPUTS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), RL = 1 kO, CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
!
TO
(OUTPUT)
tpLH
A or B
Y
tpHL
tf
y
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
TYP MAX
60
105
13
25
10
23
50
100
20
10
8
38
8
75
15
17
6
13
No load, TA
Power dissipation capacitance per gate
SN54HC01
MIN MAX
155
36
31
150
30
25
110
22
19
SN74HC01
MIN MAX
131
31
27
125
25
21
95
19
16
UNIT
ns
ns
= 25°C
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
'Ii1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-11
E
:J:
(')
s:o
tn
C
CD
<
r;"
CD
(Il
2-12
SN54HC02, SN74HC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
02684, DECEMBER 1982-REVISED SEPTEMBER 1987
•
•
SN54HC02 ... J PACKAGE
SN74HC02 ... 0 OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
ITOP VIEW)
1Y
1A
18
2Y
2A
28
Dependable Texas Instruments Quality and
Reliability
description
These devices contain four independent 2-input
NOR gates. They perform the Boolean functions
y = A + B or Y = Aoi3 in positive logic,
GND
Vee
4Y
48
4A
3Y
38
3A
SN54HC02 ... FK PACKAGE
ITOP VIEW)
The SN54HC02 is characterized for operation
over the full military temperature range of
- 55°C to 125°C, The SN74HC02 is
characterized for operation from - 40°C to
85°C.
II)
Q)
CJ
oS;
Q)
c
en
o
1 20 19
18
17
FUNCTION TABLE leach gate)
~
16
INPUTS
OUTPUT
A
B
V
H
X
L
X
H
L
L
L
H
lA
2A
28
3A
38
4A
48
121
(J
~
9 10 11 12 13
logic symbol t
18
15
14
NC-No internal connection
logic diagram (positive logic)
;>1
131
:=I>-V
151
161
181
191
1111
1121
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
Pin numbers shown are for D, J, and N packages.
PRODUCTION DATA do.umanls .ontain information
currant II of publicatian data. Products conform to
specifications par the tarms of Taxas Instruments
;:~~:~i;;ai~:I~'~ ~~~:i:: !ir:::~~:.~ Rot
Copyright @ 1982, Texas Instruments Incorporated
TEXAS . "
INsrRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-13
SN54HC02, SN74HC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
absolute maximum ratings over operating free-air temperature range t
•
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee .......................... ". .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
::I:
(")
:s:
recommended operating conditions
otJ)
SN54HC02
o
Vee Supply voltage
<
V,H High-level input voltage
CD
Vee
n'
CD
Vee
Vee
Vee
C/)
Low-level input voltage
V,l
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
SN74HC02
MIN
NOM
MAX
2
5
6
4.2
V
0.3
0
0.3
0.9
0
0.9
0
1.2
0
1.2
0
0
Vee
V
Vee
1000
V
ns
Vee
1000
0
Operating free-air temperature
V
0
Vee
TA
UNIT
0
0
Vee
6
3.15
0
Vee
5
4.2
Output voltage
Input transition (rise and fall) times
2
3.15
Input voltage
tt
MAX
1.5
Vo
=2V
= 4.5 V
=6V
NOM
1.5
V,
Vee
MIN
0
0
500
0
500
0
400
400
-55
125
0
-40
85
V
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
notedl
PARAMETER
TEST CONDITIONS
VCC
V,
=
V,H or V,l.
=
10H
-20
~A
V,
V,
V,
=
=
=
V,H or V,l.
10H
V,H or V,l.
10H
V,H or V'l,
10l
=
=
=
-4 rnA
-5.2 rnA
20 p.A
VOL
V,
V,
= V,H
= V,H
or V'l,
or V,l.
10L
10l
= 4 rnA
= 5.2 rnA
V, - 0 or Vee
"
lee
ej
2·14
V,
=
Vee or O. 10
=0
SN54HC02
SN74HC02
MIN
MIN
MAX
1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
5.9 5.999
5.9
5.9
3.7
3.84
2V
VOH
TA = 25°C
MIN
TYP MAX
1.9
4.5 V
3.98
6V
5.48
4.30
5.80
MAX
UNIT
V
5.34
5.2
2V
0.002
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
V
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
± 1000
nA
2
40
20
~A
10
10
10
pF
6V
2 to 6 V
3
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SN54HCD2, SN74HCD2
QUADRUPLE 2·INPUT POSITIVE·NOR GATES
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
UNPUT)
TO
IOUTPUT)
A or 8
Y
Y
Vee
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°e
TYP MAX
MIN
45
90
9
18
8
15
38
75
8
15
6
13
Power dissipation capacitance per gate
No load. TA
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
SN54HC02
MIN MAX
135
27
23
110
22
19
= 25°C
SN74HC02
MIN MAX
115
23
20
95
19
16
UNIT
ns
ns
II)
CD
U
'S;
CD
c
en
o
:E
(,)
:z::
TEXAS •
INSTRUMENTS
POST OfFICE BOX 656012 • DALLAS, TEXAS 75265
2-15
E
2-16
SN54HCT02, SN74HCT02
QUADRUPLE 2·INPUT POSITIVE·NOR GATES
03244. NOVEMBER 198B
SN54HCT02 .•. J PACKAGE
SN74HCT02 ... 0 OR N PACKAGE
•
Inputs are TTL·Voltage Compatible
•
Package Options Include Plastic "Smell
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
(TOPVIEWI
Vee
4Y
48
•
Dependable Texas Instruments Quality and
Reliability
4A
3Y
2A
38
28
GND.,.1_ _...r-
description
These devices contain four independent 2-input
NOR gates. They perform the Boolean functions
Y = A.S or Y = A+B in positive logic.
SN54HCT02 .•. FK PACKAGE
18
2A
28
3A
38
4A
48
'S;
3
C
2
Q)
1 20 19
4
18
5
17
6
16
1
15
(each gatel
8
14
(J)
o
~
(.)
::r:
9 10 11 12 13
OUTPUT
V
B
H
X
L
X
H
L
L
L
H
NC-No internal connection
logic diagram (each gate) (positive logic)
logic symbol t
12)
<>u
u>
~~Z>q-
FUNCTION TABLE
INPUTS
lA
Q)
(,)
u
The SN54HCT02 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HCT02 is
characterized for operation from - 40°C to
85°C.
A
tn
(TOPVIEWI
:=D-V
;;'1
13)
IS)
16)
(8)
19)
111)
(12)
t This symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEe Publication 617-12.
Pin numbers shown are for D, J, and N packages.
PRODUCTION DATA do••_II •••IIII. i.!arllilil.
••rrant .. of publication dote. Products ....,.... III
specifiClliono por til, IIIrlll of T_ I.strulllllll
=i;;"I~:I':!1i =:~·lIlO;::::':~~ not
Copyright @ 198.8, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-17
SN54HCT02, SN74HCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
absolute maximum ratings over operating free-air temperature range t
E
::r:
(")
3:
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC) ............................. ±20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1.6 mm (1 '1 6 in) from case for 60 s: FK or J package. . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1'16 in) from case for 10 s: 0 or N package ............... 260°C
Storage temperature range ............•............................ - 65°C to 150 °C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
otn
SN54HCT02
MIN NOM MAX
5.5
4.5
5
Supply voltage
C
Vee
VIH
<
VIL
VI
High-level input voltage
Low-level input voltage
Input voltage
en
Va
tt
TA
Output voltage
Input transition (rise and fall) times
Operating free~air temperature
CD
n"
CD
1 Vee
I Vee
2
':' 4.5 V to 5.5 V
= 4.5 V to 5.5 V
0
0
SN74HCT02
MIN NOM MAX
4.5
2
0.8
Vee
Vee
500
125
0
0
-55
5
UNIT
5.5
V
0.8
V
V
V
0
0
Vee
0
0
-40
Vee
500
85
V
ns
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
VOL
II
lee
Lllee*
TEST CONDITIONS
VCC
VI = VIH or VIL. 10H = - 20 ~A
VI - VIH or VIL. 10H - -4 rnA
4.5 V
4.5V
VI = VIH or VIL. 10L
VI = VIH or VIL. 10L
VI - Vee or 0
4.5 V
4.5 V
5.5 V
= 20 ~A
= 4 rnA
VI = Vee or O. 10 = 0
One input at 0.5 V or 2.4 V.
Other inputs at 0 V or Vee
ei
TA - 25°C
MIN
TYP MAX
SN54HCT02
MIN MAX
4.4
SN74HCT02
MIN MAX
4.4
UNIT
4.4 4.499
3.98
4.3
0.001
0.17
0.1
0.26
0.1
0.4
0.1
0.33
±0.1
±100
±1000
20
nA
2
±1000
40
5.5 V
;.4
2.4
3
2.9
rnA
4.5 to
5.5 V
3
10
10
10
pF
3.7
5.5 V
V
3.84
V
~
*This is the increase in supply current for each input that is at one of the specified TIL voltage levels rather than 0 V or Vee.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). Cl - 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
Y
VCC
4.5 V
5.5 V
4.5 V
5.5 V
TA - 25°C
TYP MAX
MIN
11
20
10
Power dissipation capacitance per gate
9
8
SN54HCT02
MIN MAX
SN74HCT02
MIN MAX
30
27
25
22
19
18
15
14
22
20
No load. TA = 25°e
NOTE 1: . Load circuit and voltage waveforms are shown in Section 1 of the High-Speed CMOS Logic Data Book. 1988.
2-1a
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
17
UNIT
ns
ns
SN54HC03, SN74HC03
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
WITH OPEN-DRAIN OUTPUTS
02804, MARCH 1984-REVISED SEPTEMBER 19B7
•
•
SN54HC03 ... J PACKAGE
SN74HC03 ... D OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
(TOP VIEWI
lA
18
Dependable Texas Instruments Quality and
Reliability
VCC
48
4A
4Y
38
3A
3Y
1Y
2A
28
2Y
description
These devices contain four independent 2-input
NAND gates, They perform the Boolean
functions Y = A· B or Y = Po: +B in positive logic.
The open-drain outputs require pull-up resistors
to perform correctly, They may be connected to
other open-drain outputs to implement activelow wired-OR or active-high wired-AND
functions.
GND
SN54HC03 . , . FK PACKAGE
(TOP VIEWI
....
1 20 19
18
The SN54HC03 is characterized for operation
over the full military temperature range of
-55°C to 125°C, The SN74HC03 is
characterized for operation from - 40°C to
85°C.
17
NC
16
15
14
38
9 1011 12 13
FUNCTION TABLE (each gatel
INPUTS
A
B
OUTPUT
Y
H
H
L
L
X
L
H
X
NC-No internal connection
logic diagram (positive logic)
H
logic symbol t
t This symbol is in accordance with ANSIIIEEE SId 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for D, J, and N packages.
PRODUCTION DATA documents contain information
currant as of publication date. Products conform to
specifications per the terms of Taxas Instruments
:::~:~i~·{::1~1i
!JIQ:;::::~~I not
::::i:;
Copyright @ 1984, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-19
SN54HC03, SN74HC03
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
WITH OPEN-DRAIN OUTPUTS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Veel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
::t:
(")
~
recommended operating conditions
o(I)
MIN
c
vee Supply voltage
<
VIH High-level input voltage
Vee
Vee
Low-level input voltage
Vee
Vee
Vee
CD
Cr
CD
(I)
VIL
Vee
2
1.5
3.15
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Vee
=
Vee
Vee
1000
500
400
0
0
-55
Operating free·air temperature
TA
1.2
0
0
0
0
6 V
6
0.3
0.9
0
Vee - 2 V
Vee = 4.5 V
Input transition (rise and falll times
tt
5
4.2
0
Input voltage
Output voltage
VI
Vo
SN54HC03
NOM MAX
125
SN74HC03
MIN
2
1.5
3.15
4.2
NOM
5
MAX
6
UNIT
v
V
0
0.3
0
0
0.9
1.2
V
0
0
0
0
Vee
Vee
1000
500
V
ns
0
-40
400
85
·e
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
IOH
TEST CONDITIONS
VI
=
VIH or VIL,
Vo
=
Vee
VI
=
VIH or VIL,
IOL
=
20 p.A
VOL
VI - VIH or VIL,
II
lee
ei
2-20
IOL - 4 mA
10L = 5.2 mA
VI = VIH or VIL,
VI = Vee or 0
VI - Vee or 0, 10 - 0
VCC
TA = 25·C
MIN
TVP MAX
SN54HC03
MIN MAX
SN74HC03
MIN MAX
6V
0.01
0.5
10
5
2V
4.5 V
6V
0.002
0.001
0.1
0.1
0.1
0.1
0.1
0.001
0.17
0.15
0.1
0.26
0.26
±0.1
±100
2
10
4.5 V
6V
6V
6V
2 to 6 V
3
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
0.1
0.1
0.4
0.4
±1000
40
10
0.1
0.33
0.33
±1000
20
10
UNIT
p.A
V
nA
p.A
pF
SN54HC03, SN74HC03
QUADRUPLE 2·INPUT POSITIVE·NAND GATES
WITH OPEN·DRAIN OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), RL = 1 kO, CL = 50 pF (see Note 1)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
vcc
2V
tPLH
A or B
tf
Cod
Y
SN54HC03
MIN
MAX
SN74HC03
MIN
MAX
60
105
155
131
4.5 V
13
25
36
31
6V
2V
10
31
50
23
100
150
27
125
4.5 V
10
20
30
25
y
tPHL
TA = 25°C
MIN
TYP MAX
6V
8
17
25
21
2V
38
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance per gate
No load, TA
=
25°C
UNIT
ns
ns
20 pF typ
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-21
:::t:
(")
:s:
oen
c
CD
<
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CD
en
2-22
SN54HC04, SN74HC04
HEX INVERTERS
02684. DECEMBER 1982-REVISED SEPTEM8ER 1987
•
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
SN54HC04 ... J PACKAGE
SN74HC04 ... D DR N PACKAGE
(TOP VIEW)
Vee
lA
lY
2A
2Y
3A
3Y
Dependable Texas Instruments Quality and
Reliability
description
These devices contain six independent inverters.
They perform the Boolean function Y =A.
6A
6Y
5A
5Y
4A
4Y
GND
The SN54HC04 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC04 is
characterized for operation from - 40°C to
85°C.
oS
U
>- «UU«
~z>co
2
CU
o
1 2019
FUNCTION TABLE
4
18
(each inverter)
5
17
6
16
OUTPUT
A
V
H
L
L
H
CI)
CU
CJ
(TOP VIEW)
3
INPUT
fI
SN54HC04 ... FK PACKAGE
8
en
o
:!
15
(.)
14
::I:
9 1011 12 13
>-OU>-«
C'lzz-V
(13)
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
IEC Publication 617·12.
Pin numbers shown are for 0, J, and N packages.
PRODUCTION DATA documents contain information
currant as of publication date. Products conform to
specifications par the terms of Texas Instruments
:~~!~:~~i~a{::I~'i ~::i~~ti:; :1~O:=:::::t::s~S not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1982, Texas Instruments Incorporated
2-23
SN54HC04, SN74HC04
HEX INVERTERS
absolute maximum ratings over operating free-air temperature range t
•
::r:
(')
3:
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Va < 0 or Va > Vcc .............................. ±20 mA
Continuous output current, 10 (Va = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package. . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ............... 260°C
Storage temperature range ......................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
ot/)
MIN
c
Vee Supply voltage
<
VIH High-level input voltage
CD
C:;'
Vee
Vee
=2V
= 4.5 V
=6V
2
1.5
3.15
4.2
0
= 4.5 V
=6V
0
0
Vee
Vee - 2 V
CD
(II
Low-level input voltage
VIL
Vee
Vee
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
S
Vee
Vee
=2V
= 4.5 V
=6V
1.2
0
Vee
Vee
1000
500
400
-55
125
0
0
Operating free-air temperature
6
0.3
0.9
0
0
Vee
TA
SNS4HC04
NOM MAX
MIN
SN74HC04
NOM MAX
UNIT
5
V
2
1.5
3.15
4.2
0
6
V
0.3
0
0
0.9
1.2
V
0
0
0
Vee
Vee
1000
0
0
-40
500
400
ns
85
·e
V
v
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
=
VIH or VIL.
IOH
=
-20 p.A
VI
VI
=
=
VIH or VIL.
VIH or VIL.
IOH
IOH
=
=
-4 mA
-5.2 mA
VOH
VI
=
VIH or VIL.
10L
=
20 p.A
VOL
II
lee
ei
2-24
VI = VIH or VIL. IOL = 4 mA
VI - VIH or VIL. IOL - 5.2 mA
VI = 0 or Vee
VI = Vee or 0.10 = 0
2V
4.5 V
TA = 2SoC
TYP MAX
MIN
1.9 1.998
4.4 4.499
6V
4.5 V
5.9 5.999
3.98
4.30
6V
2V
4.5 V
5.48
VCC
6V
4.5 V
6V
6V
SN74HC04
MAX
MIN
1.9
4.4
5.9
3.84
5.34
5.2
0.1
0.1
0.1
0.1
0.1
0.1
0.001
0.17
0.15
±0.1
0.1
0.26
0.26
±100
0.1
0.33
0.33
±1000
20
3
2
10
0.1
0.4
0.4
±1000
40
10
10
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
UNIT
V
5.80
0.002
0.001
6V
2 to 6 V
TEXAS
SN54HC04
MAX
MIN
1.9
4.4
5.9
3.7
V
nA
p.A
pF
SN54HC04. SN74HC04
HEX INVERTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(INPUT)
TO
(OUTPUT)
A
Y
Y
vcc
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
TYP MAX
45
95
9
19
B
16
3B
75
15
B
6
13
Power dissipation capacitance per inverter
No load, TA
SN54HC04
MIN MAX
145
29
25
110
22
19
=
25°C
SN74HC04
MIN MAX
120
24
20
95
19
16
UNIT
ns
n.
II
tn
CD
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
()
':;
CD
C
(/)
o
:E
()
::I:
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-25
:I:
(")
s:
oen
cCD
<
c:r
CD
CIl
2-26
SN54HCT04, SN74HCT04
HEX INVERTERS
02953. JULY 1986-REVISED JUNE 1989
SN54HCT04 ... J PACKAGE
SN74HCT04 ... 0 OR N PACKAGE
•
Inputs are TTL-Voltage Compatible
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
(TOP VIEW)
lA
Dependable Texas Instruments Quality and
Reliability
description
These devices contain six independent inverters.
They perform the Boolean function Y = A.
OUTPUT
Y
L
H
H
L
2A
3A
4A
SA
6A
6Y
2Y
5A
3A
5Y
3Y
4A
GND
4Y
Ell
U)
Q)
(.)
U
>- -OU>- VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (VO < 0 or Vo > VCC) ............................. ±20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GND pins ................................. .' ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60: FK or J package ................ 300 °C
Lead temperature 1,6 mm (1/16 in) from case for 10: D or N package ................. 260°C
Storage temperature range ......................................... - 65°C to 1 50°C
:::t:
o
s:o
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation oftha device at these or any other condition. beyond those Indicated under "recommended operating conditions"
is not implied. Exposure to ab.olut....maximum-rated condition. for extended period. may affect device reliability.
recommended operating conditions
SN54HCT04
(I)
Vee
Supply voltage
VIH
High-level input voltage
<
5"
VIL
VI
Low-level input voltage
rn
Vo
tt
Input transition (rise and falll times
TA
Operating fre....air temperature
cCD
CD
I Vee = 4.5 V to 5.5 V
I Vee = 4.5 V to 5.5 V
SN74HCT04
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
V
2
2
V
0
0.8
0
0.8
V
Input voltage
0
Vee
0
Vee
V
Output voltage
0
Vee
500
0
0
Vee
500
ns
125
-40
85
°e
0
-55
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
VI
VI
VI
VI
= VIH or VIL. 10H = - 20 p.A
= VIH or VIL, 10H = -4 mA
= VIH or VIL' 10L - 20 p.A
= VIH or VIL, 10L = 4 mA
= Vee or 0
= Vee or 0, 10 = 0
II
VI
lee
VI
One input at 0.5 V or 2.4 V,
.1lee*
Other inputs at 0 V or Vee
4.5 V
TA - 25°C
TVP MAX
MIN
4.4 4.499
4.5 V
3.98
VCC
MIN
MAX
SN74HCT04
MIN
4.4
4.4
3.7
3.84
MAX
UNIT
V
4.5 V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
5.5 V
±0.1
±100
±1000
±1000
nA
2
40
20
p.A
1.4
2.4
3
2.9
mA
3
10
10
10
pF
5.5 V
5.5 V
4.5 to
ei
4.30
SN54HCT04
5.5 V
V
*This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or Vee.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note .1)
PARAMETER
tpd
tt
FROM
(lNPUn
(OUTPUn
TO
A
Y
V
VCC
TA - 25°C
TVP MAX
MIN
MIN
MAX
SN74HCT04
MIN
MAX
4.5 V
14
20
30
25
5.5 V
13
18
27
23
4.5 V
9
15
22
19
5:5 V
8
14
20
17
Power dissipation capacitance per inverter
No load, TA = 25°e
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-28
SN54HCT04
TEXAS .. "
INSTRUMENlS
POST OFFICE BOX 856012 • DALLAS,'TEXAS 75265
UNIT
ns
ns
SN54HCU04, SN74HCU04
HEX INVERTERS
02804, MARCH 1984-REVISEO JUNE 1989
•
SN54HCU04 .. , J PACKAGE
SN74HCU04 ... D OR N PACKAGE
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Unbuffered Outputs
•
Dependable Texas Instruments Quality and
Reliability
(TOPVIEWI
lA
1Y
2A
2Y
3A
3Y
description
GND
These devices contain six independent inverters,
They perform the Boolean function Y = A.
SN54HCU04 ... FK PACKAGE
The SN54HCU04 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCU04 is
characterized for operation from - 40°C to
85°C.
(TOP VIEW)
U
~ ~ ~ ~~
3
2A
NC
2Y
NC
3A
FUNCTION TABLE
(each inverter)
INPUT
OUTPUT
A
Y
2A
3A
4A
SA
6A
2
1 2019
4
18
5
17
6
16
7
15
8
14
H
L
9 1011 12 13
L
H
)-ou)-<
6Y
NC
5A
NC
5Y
MZZ'-V
(91
(111
(131
t This symbol is in accordance with ANSI/IEEE Std 91-1 984 and
lEG Publication 617-12.
Pin numbers are for D, J, and N packages.
PRODUCTION DATA documents cont.i. i.formation
currant as of publication data. Products conform tD
spacifications par the terms of Taxas Instrumants
~~~~:~~i~at::1~1i ~~::i:; :1~O=:~~es
not
..If
INSTRUMENTS
TEXAS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
Copyright @ 1989, Texas Instruments Incorporated
2-29
SN54HCUD4, SN74HCUD4
HEX INVERTERS
absolute maximum ratings over operating free-air temperature range t
•
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 rnA
Output clamp current, 10K (Va < 0 or Va > Vce . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Continuous output current, 10 (Va = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 rnA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Lead temperature 1,6 mm (1/16 in.) from case for 60 s: FK or J package .............. 300°C
Lead temperature 1,6 mm (1/16 in.) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent de,mage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
::I:
(")
s:o
recommended operating conditions
SN54HCU04
MIN NOM MAX
2
5
6
(/)
cCD
Vee Supply voltage
<
Vee
Vee
VIH High-level input voltage
C;"
Vee
CD
(II
Vee
Vee
VIL Low-level input voltage
Vee
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
vee
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
=
=
=
1.7
3.6
4.B
0.3
O.B
0
0
0
1.1
Vee
Vee
1000
0
0
0
0
-55
6 V
Operating free-air temperature
TA
1.7
3.6
0
2 V
4.5 V
SN74HCU04
MIN NOM MAX
5
2
6
500
400
125
UNIT
V
V
4.B
0
0.3
O.B
0
0
V
1.1
0
0
0
0
0
-40
Vee
Vee
1000
V
V
500
400
B5
ns
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
VI
=
VIH or VIL,
10H
=
-20
VI
VI
=
=
VIH or VIL,
VIH or VIL,
10H
-4 rnA
10H
=
=
VI
=
VIH or VIL,
10L
=
VI
= VIH or VIL, 10L = 4 rnA
= VIH or VIL. 10L = 5.2 rnA
= Vee or 0
= Vee or O. 10 = 0
~A
VOH
-5.2 rnA
20 ~A
VOL
II
lee
ei
2-30
VI
VI
VI
TA = 25°C
MIN
TYP MAX
SN54HCU04
MIN MAX
SN74HCU04
MIN MAX
2V
4.5 V
1.B
4
loB
4
loB
4
6V
4.5 V
5.5
3.9B
5.4B
5.5
3.7
5.2
5.5
3.84
5.34
6V
2V
0.2
0.2
0.5
V
0.2
0.5
0.5
4.5 V
6V
0.5
0.5
4.5 V
6V
6V
0.26
0.26
±100
0.5
0.4
0.4
±1000
0.33
0.33
±1000
2
10
40
10
20
10
6V
2 to 6 V
3
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
UNIT
V
nA
~
pF
SN54HCU04. SN74HCU04
HEX INVERTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
t"d
tt
FROM
IINPUT)
TO
(OUTPUT)
A
V
V
vCC
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
TVP MAX
40
80
8
16
7
14
38
75
8
15
6
13
Power dissipation capacitance per inverter
No load,
SN54HCU04
MIN MAX
120
24
20
110
22
19
TA
=
25°C
SN74HCU04
MIN MAX
100
20
17
95
19
16
UNIT
ns
ns
•
fI)
Q)
U
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
'S:Q)
o
en
o
:a
(.)
J:
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-31
J:
("')
s:
oen
o
(1)
~.
('")
(1)
en
2-32
SN54HC05. SN74HC05
HEX INVERTERS WITH OPEN-DRAIN OUTPUTS
02804. MARCH 1984-REVISEO SEPTEMBER 1987
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC05 ... J PACKAGE
SN74HC05 •.. D OR N PACKAGE
(TOP VIEW}
lA
lY
2A
2Y
3A
3Y
description
These devices contain six independent inverters.
They perform the Boolean function Y = A. The
open-drain outputs require pull-up resistors to
perform correctly. They may be connected to
other open-drain outputs to implement activelow wired-OR or active-high wired-AND
functions.
GND
(TOP VIEW)
u
>«uu«
~~z>CD
3
2A
NC
2Y
NC
3A
OUTPUT
V
H
L
L
H
2
1 20 19
18
4
5
17
6
16
8
14
15
9 10 11 12 13
FUNCTION TABLE (each inverter)
A
II
SN54HC05 ... FK PACKAGE
The SN54HC05 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC05 is
characterized for operation from - 40°C to
85°C.
INPUT
VCC
6A
6Y
5A
5Y
4A
4Y
>ou>«
MZZ-V
lA
2A
3A
4A
5A
6A
t This symbol is in accordance with ANSI/IEEE Std-91-1984 and
lEe Publication 617-12.
Pin numbers shown are for D. J. and N packages.
PRODUCTION DATA .....m.....olllli. i.formatio.
••"Iot II 01 publicatio. data. Prad.....onform to
lpooHicatio.1 p.r tho tarm. 01 T...I lostrume...
::':~ri~.i:''::li =:~i:: :.:o==~~~ .ot
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright @ 1984. Texas Instruments Incorporated
2-33
SN54HC05, SN74HC05
HEX INVERTERS WITH OPEN·DRAIN OUTPUTS
absolute maximum ratings over operating free·air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (V, < 0 or V, > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K (VO < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Continuous output current, 10 (VO = 0 to Vee) ................................. ± 25 rnA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings"
may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
:t
o
s::
o(I)
cCD
recommended operating conditions
MIN
Vee Supply voltage
<
5'
VIH High-level input voltage
Vee
Vee
low-level input voltage
Vee
Vee
Vee
CD
o
Vil
Vee
2
1.5
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
0.3
0
0
0
Vee
Vee
1000
500
0
0
0
0
400
125
0
-40
0
0
0
tt
Input transition (rise and fall) times
= 4.5 V
=6V
0
0
-55
Operating free-air temperature
TA
2
1.5
3.15
4.2
0.9
1.2
Input voltage
Vee
6
SN74HC05
NOM MAX
0
0
Output voltage
Vee - 2 V
5
MIN
3.15
4.2
0
VI
Vo
Vee
SN54HC05
NOM MAX
5
6
UNIT
V
V
0.3
0.9
V
1.2
Vee
Vee
1000
500
400
85
V
V
ns
De
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
10H
TEST CONDITIONS
=
VIH or Vil.
Vo
=
Vee
VI = VIH or Vil.
10l
=
20
VI = VIH or Vil.
10l
10l
= 4 rnA
= 5.2 rnA
VI
~A
VOL
II
lec
ei
2-34
VI = VIH or Vil.
VI = Vee or 0
VI - Vee or O. 10 - 0
VCC
TA = 25 DC
TYP MAX
MIN
6V
0.01
0.5
SN54HC05
MIN MAX
SN74HC05
MIN MAX
10
5
0.1
0.1
2V
0.002
0.1
0.1
4.5 V
6V
0.001
0.1
0.001
0.17
0.15
0.1
0.26
0.26
0.1
0.1
±O.l
±100
2
10
4.5 V
6V
6V
6V
2 to 6 V
3
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
0.4
0.4
±1000
40
10
0.1
0.33
0.33
± 1000
20
10
UNIT
~A
V
nA
~A
pF
SN54HC05. SN74HC05
HEX INVERTERS WITH OPEN-DRAIN OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
IpLH
A
Y
tpHL
A
Y
If
Y
Vce
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25"C
MIN
TYP MAX
115
60
13
23
10
20
45
85
17
9
8
14
38
75
8
15
13
6
SN54HC05
MIN MAX
175
35
30
130
26
22
110
22
19
No load, T A =
Power dissipation capacitance per inverter
SN74HC05
MIN MAX
145
29
25
105
21
18
95
19
16
UNIT
n'
n.
n.
II
25"C
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-35
E
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CD
en
2-36
SN54HC08, SN74HC08
QUADRUPLE 2·INPUT POSITIVE·AND GATES
02684, DECEMBER 1982 - REVISED SEPTEMBER 1987
•
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300·mil
DIPs
SN54HCOB .•. J PACKAGE
SN74HCOB .•. D OR N PACKAGE
(TOP VIEW)
lA
18
Dependable Texas Instruments Quality and
Reliability
2A
38
28
description
These devices contain four independent 2-input
AND gates. They p'erform the Boolean functions
Y = A,B or Y = A+B in positive logic.
......_ _J""
3A
3Y
fI
SN54HCOB ..• FK PACKAGE
The SN54HC08 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC08 is
characterized for operation from - 40°C to
85°C.
fI)
(TOP VIEW)
m CD
U
Um
-_z>~
3
2
c
1 20 19
en
18
o
17
FUNCTION TABLE
(each gate)
::!:
16
o
15
INPUTS
OUTPUT
A
B
H
H
V
H
L
X
L
X
L
L
14
:::t
9 10 II 12 13
NC-No internal connection
logic symbol t
lA
18
2A
28
3A
38
4A
48
logic diagram (positive logic)
(1)
131 1y
121
141
161 2y
151
191
181 3Y
(101
(121
(111 4y
1131
tThis symbol is in accordance with ANSI/IEEE Std 91- 1984 and
lEe Publication 617-12.
Pin numbers shown are for D, J, and N packages.
PRODUCTIOI DATA ....._
...1ailI illfema.....
...mot n of pu~ll..ti.n dote. Prod.1II ...IIm t.
_llicItIon. per t .. torll' of Ttu. IlIOIn_
='';''f.':I'i
=:r
lIr=~:.'·ot
Copyright @ 1982. Texas Instruments Incorporated
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-37
SN54HC08, SN74HC08
QUADRUPLE 2·INPUT POSITIVE·AND GATES
absolute maximum ratings over operating free-air temperature range t
•
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (VO < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package. . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
::J:
(")
s:o
recommended operating conditions
SN64HCOB
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0
0.9
0
1.2
0
0
Vee
0
Vee
1000
0
0
500
400
0
-55
125
en
c
<
n'
CD
Vee Supply voltage
CD
Vee - 2 V
Vee = 4.5 V
Vee = 6 V
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
VIH High-level input voltage
(I)
VIL Low-level input voltage
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
Vee
Vee
Vee
=2V
= 4.5 V
=6V
Operating free-air temperature
TA
SN74HCOB
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0
0.3
0
0.9
0
1.2
0
Vee
0
Vee
0
1000
0
500
0
400
-40
85
UNrr
V
V
V
V
V
ns
De
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
= VIH
or VIL.
IOH
=
-20 p.A
VOH
VI - VIH or VIL.
VI = VIH or VIL.
VI
= VIH
or VIL.
IOH - -4 mA
IOH = -5.2 mA
IOL
= 2Ol'A
VOL
II
lee
ei
2-38
VI = VIH or VIL. IOL = 4 mA
VI - VIH or VIL. 10L = 5.2 mA
VI = Vec orO
VI = Vee or O. 10 = 0
TA = 26°C
MIN
TYP MAX
2V
1.9 1.998
4.4 4.499
4.5 V
6V
5.9 5.999
3.98
4.30
4.5 V
6V
5.48
5.80
0.1
2V
0.002
4.5 V
0.001
0.1
6V
0.001
0.1
0.17
4.5 V
0.26
6V
0.15
0.26
6V
±0.1 ±100
6V
2
2 to 6 V
10
3
VCC
TEXAS
~
INSTRUMENlS
POsrOFF1CE BOX 655012 • DALLAS, TEXAS 75265
SN64HCOB
MIN MAX
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
40
10
SN74HCOB
MIN MAX
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
20
10
UNrr
V
V
nA
I'A
pF
SN54HCOB. SN74HCOB
QUADRUPLE 2-INPUT POSITIVE-AND GATES
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 IlF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
vcc
2V
tpd
tt
A or B
Y
Y
4.5 V
6V
2V
TA = 25°C
MIN
TYP MAX
50
10
100
20
8
38
8
6
4.5 V
6V
SN74HC08
MIN
MAX
MAX
17
75
150
30
25
110
125
25
21
95
15
13
22
19
19
16
No load, TA
Power dissipation capacitance per gate
SN54HC08
MIN
= 25°C
UNIT
ns
ns
II
fI)
CD
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
(,)
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CD
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TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-39
2-40
SN54HCT08, SN74HCT08
QUADRUPLE 2·INPUT POSITIVE·AND GATES
03245. NOVEMBER 1988
SN54HCT08 ••• J PACKAGE
SN74HCT08 .•. D OR N PACKAGE
•
Inputs are TTL-Voltage Compatible
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
(TOP VIEWI
Vee
1A
18
1Y
2A
28
2Y
Dependable Texas Instruments Quality and
Reliability
description
48
4A
3A
3Y
GND
These devices contain four independent 2-input
NAND gates. They perform the Boolean
functionsY = A-BorY = A+Bin positive logic.
SN54HCT08 ••• FK PACKAGE
U)
(TOPVIEWI
The SN54HCT08 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCT08 is
characterized for operation from - 40°C to
85°C.
CD
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-S
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2
1 20 19
C
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18
(J)
o
17
:E
16
FUNCTION TA8LE
15
(each gale)
H
L
X
9 1011 12 13
OUTPUT
INPUTS
A
V
8
H
X
L
H
L
NC-No ·internal connection
L
logic diagram (each gate) (positive logic)
logic symbol t
lA
18
2A
28
3A
38
4A
48
(1)
to)
l:
14
&
:=O-V
(3) IV
(21
(4)
(6)2V
(51
(91
(8) 3V
(10)
(121
(111 4V
(13)
t This symbol is in accordance wilh ANSI/IEEE SId 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for 0, J. and N packages.
PROOU&TIOI DATA ••••m.nto ...llin '.fannoti..
••, ..., II of p.blicati.. dill. p""'"eII oonfonn to
.....ilieoti••• per lhe linn. of Till. Inotru....11
:.=~i~·f.::.:,;
=:1:: ru:::::':~••
ot
Copyright @ 1988, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265
2-41
SN54HCT08, SN74HCT08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
absolute maximum ratings over operating free-air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC) ............................. ± 20 mA
Continuous output current, 10 (Va = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vce or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300 De
lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260 De
Storage temperature range ......................................... - 65 DC to 150 DC
::J:
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(') recommended operating conditions
s:o
SN54HCT08
tn
o
CD
<
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CD
U)
SN74HCT08
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
Vee
Supply voltage
VIH
High-level input voltage
VIL
VI
Low-level input voltage
0
0.8
0
O.B
Input voltage
0
Vee
0
Vee
V
Va
Output voltage
0
0
0
Vee
500
V
0
Vee
500
ns
-55
125
-40
85
°e
I Vee = 4.5 V to 5.5 V
I Vee = 4.5 V to 5.5 V
tt
Input transition (rise and fall) times
TA
Operating free-air temperature
2
V
V
2
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
TEST CONDITIONS
VI
VI
= VIH or VIL.
= VIH or VIL,
= VIH or VIL.
MIN
MAX
SN74HCT08
MIN
MAX
4.5 V
0.001
0.1
0.1
4.5 V
0.17
0.26
0.4
0.1
0.33
5.5 V
±0.1
±100
±1000
±1000
nA
2
40
20
pA
1.4
2.4
3
2.9
mA
3
10
10
10
pF
VI
lee
VI
or 0,
10 = 0
One input at 0.5 V or 2.4 V,
or 0
Other inputs at 0 V or Vee
4.5 V
4.4 4.499
3.98
4.3
5.5 V
5.5 V
4.5 to
5.5 V
4.4
4.4
3.7
3.84
V
*This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0
2-42
UNIT
10L - 4 mA
II
ei
SN54HCT08
4.5 V
VI
VI - VIH or VIL,
l!.lee*
TA - 25°C
MIN
TYP MAX
= -20pA
10H = -4 mA
IOL = 20 ~A
IOH
VOL
= Vee
= Vee
VCC
TEXAS
~
INSTRUMENTS
POST OFF:ICE BOX 655012 • DALLAS, TEXAS 75265
V or Vee.
V
SN54HCTOB, SN74HCTOB
QUADRUPLE 2·INPUT POSITIVE·AND GATES
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), Cl = 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(INPUT)
AorB
TO
(OUTPUT)
Y
Y
vCC
TA - 25°C
MIN
TYP MAX
SN54HCT08
MIN
MAX
SN74HCT08
MIN
MAX
4.5 V
15
24
35
30
5.5 V
13
22
32
27
4.5 V
9
8
15
22
14
20
19
17
5.5 V
Power dissipation capacitance per inverter
No load. TA
= 25°C
NOTE 1: Load circuit and voltage waveforms are shown in Section 1 of the High-Speed CMOS Logic Databook, 1988.
UNIT
ns
ns
fI
fI)
Q)
(,)
'S;
Q)
C
(/)
o
:?!
(.)
:t:
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS. TEXAS 75265
2-43
z
(")
s:
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C
CD
<
c:r
CD
en
2-44
SN54HC09, SN74HC09
QUADRUPLE 2·INPUT POSITIVE·AND GATES
WITH OPEN·DRAIN OUTPUTS
MARCH 1984 - REVISED SEPTEMBER 1987
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300·mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HCD9 .•. J PACKAGE
SN74HC09 ... 0 OR N PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
28
2Y
description
These devices contain four independent 2-input
AND gates. The't..mill'orm the Boolean functions
Y = A· B or Y = A + B in positive logic. The opendrain outputs require pull-up resistors to perform
correctly. They may be connected to other opendrain outputs to implement active-low wired-OR
or active-high wired-AND functions.
GND
U
~~li~~
•3
1Y
NC
2A
NC
28
X
H
L
X
L
L
1 2019
18
17
6
16
7
14
8
4A
NC
4Y
NC
38
>ou> Vee) ................................. ± 20 mA
Output clamp current, 10K(VO < 0 or Vo > Vee) .............................. ±20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins ................................. , ±50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ................ 260°C
Storage temperature range ...............................•......... - 65°C to 1 50°C
t Stresses beyond those listed under "absolute maximum ratings" may causa permanent damage to the devica. These are stress ratings
onlv. and functional operation of the devica at these or any other conditions beyond those indicated under "recommended operating
contitions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
en
MIN
c
Vee
Supply voltage
CD
<
c:r
CD
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-55
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
TA
Operating free-air temperature
(I)
Vee
Vee
Vee
SN64HC09
NOM MAX
=2 V
= 4.5 V
=6 V
5
6
0.3
0.9
1.2
Vee
Vee
1000
500
400
125
MIN
SN74HC09
NOM MAX
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-40
5
6
UNIT
V
V
0.3
0.9
1.2
Vee
Vee
1000
500
400
85
V
V
V
ns
De
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
10H
TEST CONOITIONS
VCC
VI
= VIH or VIL.
Vo
= Vee
VI
= VIH or VIL.
10L
= 20 I'A
VOL
II
lee
ei
2-46
VI - VIH or VIL. 10L - 4 mA
VI = VIH or VIL. 10L = 5.2 mA
VI - Vee or 0
VI = Vee or O. 10 - 0
TA - 25 DC
MIN TYP MAX
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 to 6 V
TEXAS
0.01
0.002
0.001
0.001
0.17
0.15
±0.1
3
0.5
0.1
0.1
0.1
0.26
0.26
±100
2
10
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC09
MIN MAX
SN74He09
MIN MAX
10
0.1
0.1
0.1
0.4
0.4
±1000
40
10
.5
0.1
0.1
0.1
0.33
0.33
±1000
20
10
UNIT
~A
V
nA
~
pF
SN54HCD9, SN74HCD9
QUADRUPLE 2·INPUT POSITIVE·AND GATES
WITH OPEN·DRAIN OUTPUTS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), RL - 1 kO, CL - 50 pF (see Note 1)
PARAMETER
FROM IINPUT)
tPLH
A or B
y
tpHL
A or B
Y
tf
TO (OUTPUT)
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
y
TA - 25°C
MIN
TYP
MAX
60
13
10
50
10
8
38
8
6
105
25
23
100
20
17
75
15
13
SN54HC09
SN74HC09
MIN
MIN
MAX
155
36
31
150
30
25
110
22
19
MAX
131
31
27
125
25
21
95
19
16
UNIT
ns
ns
ns
EJ
en
CD
(J
Cpd
Power dissipation capacitance per gate
No load, TA - 25°C
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
20 pF typ
'S;
CD
C
(J)
o
:!:
CJ
:J:
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·47
E
::E:
(')
s:o
en
c
CD
<
c:;'
CD
til
2-48
SN54HC10, SN74HC10
TRIPLE 3·INPUT POSITIVE·NAND GATES
02684, DECEMBER 1982-REVISED SEPTEMBER 1987
•
•
SN54HC10 ... J PACKAGE
SN74HC10 ... 0 OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
ITOP VIEW)
1A
1B
2A
2B
2C
Dependable Texas Instruments Quality and
Reliability
description
VCC
1C
1Y
3C
3B
2Y
These devices contain three independent 3-input
NAND gates. They perform the Boolean
functions Y = A.B.C or Y =A + B + C in positive
logic,
3A
GND ........_ _J"' 3Y
en
SN54HC10 .•. FK PACKAGE
ITOP VIEW)
The SN54HC10 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC10 is
characterized for operation from - 40°C to
85°C.
CD
__ Uz>_
m
Uu
.s:CJ
3
c
«
U
2
1 20 19
CD
18
en
lY
o
17
~
CJ
::J:
16
FUNCTION TABLE leach gate)
15
INPUTS
OUTPUT
A
B
C
Y
H
H
H
L
L
X
X
H
X
L
X
H
X
X
L
H
14
9 1011 12 13
NC - No internal co nnection
logic symbol t
lA
(1)
logic diagram (positive logic)
}>-v
&
18
lC
2A
28
2Y
2C
3A
3B
3C
3Y
Ill)
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for 0, J. and N packages.
.1
PROOUCTIO. DATA documan.......1. Inform.tion
of p.bli.ation d.... Prod.....onfor.. til
Ipocllication. por the term. of r •••• 1.lIr.......
.ottan!
=~~il;"i~:I~li =~; :.lo:=,:~••at
Copyright @ 1982, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-49
SN54HC1~SN74HC10
TRIPLE 3-INPUT POSITIVE-NAND GATES
absolut.e maximum ratings over operating free-air temperature range t
II
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
eontinuous current through Vee or GND pins ................... '. . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300 0 e
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260 0 e
Storage temperature range ......................................... - 65 °e to 150 0 e
t Stresses beyond'those listed under "absolute maximum ratings"
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any' other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
::::t
(')
s:o
recommended operating conditions
en
MIN
c
CD
Vee
(;'
VIH
<
Supply voltage
High-level input voltage
Vee = 6 V
fI)
0
0
Vee = 6 V
Input voltage
Output voltage
VI
'VO
Vee
Vee
1000
500
400
0
0
Vee = 2 V
Vee = 4.5 V
0
-55
Vee = 6 V
Operating free-air temperature
TA
1.2
0
0
Input transition (rise and fall) times
tt
6
0.3
0.9
0
Vee = 2 V
Vee = 4.5 V
Low-level input voltage
VIL
5
2
1.5
3.15
4.2
Vee = 2 V
Vee = 4.5 V
CD
SN54HC10
NOM MAX
125
MIN
SN74HC10
NOM MAX
UNIT
5
V
2
1.5
3.15
4.2
6
V
0
0.3
0.9
0
0
V
1.2
0
0
Vee
Vee
1000
500
400
0
0
0
-40
85
V
V
ns
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
VI
= VIH or VIL.
10H = - 20 p.A
4.5 V
6V
4.5 V
6V
VOH
VI
= VIH or VIL.
10H = -4 rnA
10H = -5.2 rnA
VI
= VIH or VIL.
10L = 20
VI = VIH or VIL.
~A
VOL
II
lee
ej
2-50
VI - VIH or VIL.
VI = VIH or VIL.
VI = Vee or 0
VI
= Vee or O. 10
10L - 4 rnA
10L
= 5.2 rnA
= 0
TA = 25°C
MIN
TYP MAX
1.9 1.998
4.4 4.499
5.9 5.999
3.98
5.48
2V
4.5 V
6V
4.5 V
6V
6V
4.30
5.80
0.002
0.001
TEXAS
SN74HC10
MIN
1.9
4.4
5.9
MIN
1.9
MAX
0.1
0.1
0.1
0.26
0.26
±100
3
2
10
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MAX
4.4
5.9
3.7
5.2
0.001
0.17
0.15
±0.1
6V
2 to 6 V
SN54HC10
UNIT
V
3.84
5.34
0.1
0.1
0.1
0.1
0.1
0.1
0.4
0.4
±1000
40
0.33
0.33
±1000
10
20
10
V
nA
~A.
pF
SN54HC10, SN74HC10
TRIPLE 3·INPUT POSITIVE· NAND GATES
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(INPUT)
A. B.
or
C
TO
(OUTPUT)
y
Y
vCC
2V
4.5 V
6V
2V
4.5 V
6V
TA ; 25°C
MIN
TYP MAX
35
95
10
19
16
9
23
75
15
6
13
5
No load. TA
Power dissipation capacitance per gate
SN54HC10
MIN MAX
145
29
25
110
22
19
= 25°C
SN74HC10
MIN MAX
120
24
20
95
19
16
UNIT
n.
n.
II
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-51
E
2-52
SN54HC11, SN74HC11
TRIPLE 3·INPUT POSITIVE·AND GATES
02684, DECEMBER 1982 - REVISED SEPTEMBER 1987
•
Package Options Include Plastic "Small
Outline" Packagas. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300·mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC11 ... J PACKAGE
SN74HC11 ... D OR N PACKAGE
(TOP VIEW)
1A
1B
2A
2B
2C
2Y
GND
description
These devices contain three independent 3-input
AND gates. They perform the Boolean functions
Y = A.B.C or Y = A+B+C in positive logic.
VCC
1C
1Y
3C
3B
3A
3Y
SN54HC11 ... FK PACKAGE
(TOP VIEW)
The SN54HC11 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC11 is
characterized for operation from - 40°C to
85°C.
!Xl <{ U
U
Uu
...-..-2>_
3
2
1 20 19
18
17
FUNCTION TABLE (eech gate)
16
INPUTS
OUTPUT
15
14
A
H
B
H
C
H
y
L
X
L
X
X
L
X
X
X
L
L
H
9 1011 1213
L
NC - No internal connection
logic symbol t
logic diagram (positive logic)
lA
18
lC
2A
28
2C
3A
38
3C
111
121
&
1121
lV
1131
131
141
(61
2V
(51
(91
1101
(81
3V
1111
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for D, J, and N packages.
PRODUCTION DATA d............ntoln inlormoti••
..mot I I 01 fIIIbUcotia. dote. P........ c..farnlto
-'fintiaao par tho lar... of T_ I_I""'"
=:=.~·I:,:i =:I:;": lrl':=~.11
Copyright @ 1982, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-53
SN54HC11, SN74HC11
TRIPLE 3·INPUT POSITIVE·AND GATES
absolute maximum ratings over operating free-air temperature range t
•
~
(")
3:
Supply voltage, VCC ................................................ -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K(VO < 0 or Vo > Vcc) .............................. ±20 mA
Continuous output current. 10 (VO = 0 to Vcc) ................................ ±25 mA
Continuous current through VCC or GND pins .................................. ±50 mA
Lead temperature 1.6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ................ 260°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
contitions" is not implied. Exposure to absolute·maximum·rated conditions for extended periods may affect device reliability.
recommended operating conditions
oen
MIN
cCD
Vee
(;'
VIH
<
Supply voltage
High·level input voltage
Vee
Vee
Low·level input voltage
Vee
Vee
Vee
CD
tn
VIL
Vee
VI
Vo
2
1.5
3.15
=2V
= 4.5 V
=6 V
=2V
= 4.5 V
=6 V
0
0
0
Vee
Vee
6
0
0
0
-55
= 4.5 V
=6V
Operating free-air temperature
MIN
SN74HC11
NOM MAX
2
1.5
3.16
6
6
UNIT
V
V
4.2
0
0
Input voltage
Output voltage
Input transition (rise and fall) times
TA
5
4.2
Vee - 2 V
tt
SN64HC11
NOM MAX
0.3
0.9
1.2
0
0
0
0.3
0.9
1.2
Vee
Vee
1000
0
Vee
Vee
1000
V
600
400
ns
85
·e
500
400
125
0
0
0
0
-40
V
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
VI
= VIH or VIL.
10H
=
-20 p.A
4.5 V
6V
VOH
VI = V,H or V,L. 10H = -4 mA
V, - V,H or V,L. 10H - -5.2 mA
VI
= V,H or V,L.
10L
= 20 p.A
4.5 V
6V
= 4 mA
= 5.2 mA
4.5 V
6V
VOL
'I
lee
ei
2-54
VI = VIH or VIL. 10L
VI = VIH or V,L. 10L
V, - Vee orO
V,
= Vee or O.
10
4.5 V
6V
2V
=0
TA - 26·C
MIN
TYP MAX
1.9 1.998
SN54HC11
MIN MAX
1.9
1.9
4.4 4.499
5.9 5.999
4.4
5.9
3.7
4.4
5.9
3.84
3.98
5.48
6V
6V
4.30
5.80
0.002
0.1
0.001
0.001
0.1
0.1
0.17 0.26
0.15 0.26
±0.1 ±100
2 to 6 V
TEXAS
5.2
3
~
INSTRUMENTS
POST OFFICE BO)( 655012 • DALLAS. TEXAS 75265
2
10
SN74HC.11
MIN MAX
UNIT
V
5.34
0.1
0.1
0.1
0.4
0.4
±1000
40
10
0.1
0.1
0.1
V
0.33
0.33
±1000
nA
20
10
p.A
pF
SN54HC11, SN74HC11
TRIPLE 3-INPUT POSITIVE-AND GATES
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted!. CL .. 50 pF (see Note 11
PARAMETER
tpd
tt
Cpd
FROM (INPUT)
A, B, or C
TO (OUTPUT)
Y
Y
VCC
TA - 25°C
SN54HC11
SN74HC11
MIN
MIN
2V
TYP
35
MAX
100
4.5 V
10
6V
8
20
17
30
25
25
21
95
MIN
MAX
150
MAX
125
2V
25
75
110
4.5 V
7
15
22
19
6V
5
13
19
16
No load, TA - 25°C
Power dissipation capacitance per gate
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
UNIT
ns
ns
25 pF typ
EJ
II)
Q)
CJ
'S;
Q)
c
en
o
~
(.)
:E:
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-55
E
::t
(')
s:o
t/)
c
CD
<
t;'
CD
en
2-56
8N54HC14, 8N74HC14
HEX SCHMITT-TRIGGER INVERTERS
02684. DECEMBER 1S82-REVISED SEPTEMBER 1987
•
•
SN54HC14 ... J PACKAGE
SN74HC14 ... 0 OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
(TOP VIEW)
1A
VCC
6A
1Y
Dependable Texas Instruments Quality and
Reliability
2A
2Y
description
These Schmitt-trigger devices contain six
independent inverters. They perform the Boolean
function Y = A.
6Y
5A
3A
5Y
3Y
4A
GND
4Y
SN54HC14 ... FK PACKAGE
(TOP VIEW)
The SN54HC14 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC14 is
characterized for operation from - 40°C to
B5°C.
u
«
>- « zu >u CD
2 1 20 19
2A
4
18
5
17
NC
FUNCTION TABLE
NC
2Y
6
16
5A
(each inverter,
NC
15
NC
8
14
5Y
3A
INPUT
OUTPUT
A
H
Y
L
L
H
I
9 1011 12 13
>-cu>-«
z Z oct .q
('I')
Cl
NC - No internal connection
logic symbol t
lA
2A
3A
4A
SA
6A
(1)
IT
(3)
(5)
(9)
(11)
(13)
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
logic diagram (positive logic)
PRDDucnDN DATA d..............in iofarmotiln
currant .s ., ,Ibli..lil. dots. Prod....
to
,"niar.
......1J..ti....... th' terms of TIJCII 1l1li........
:~i~':I":r.; =:~::
:.=.:':t.":.".ot
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75,265
Copyright © 1982. Texas Instruments Incorporated
2-57
SN54HC1' SN74HC14
HEX SCHMITT·TRIGGER INVERTERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vcc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package. . . . . . . . . . . . . .. 300 DC
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260 DC
Storage temperature range ......................................... - 65 DC to 1 50 DC
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
::r:
n
3:
o(I)
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute~maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
oCD
<
(;'
SN54HC14
NOM MAX
MIN
2
1.5
3.15
Vee Supply voltage
VIH High-level input voltage
Vee = 2 V
Vee = 4.5 V
Low-level input voltage
vee = 6 V
Vee = 2 V
Vee = 4.5 V
CD
en
VIL
4.2
0
0
0
Vee = 6 V
2-58
VI
Vo
Input voltage
Output voltage
TA
Operating free-air temperature
0
0
-55
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
5
6
0.3
0.9
SN74HC14
MIN
2
1.5
3.15
4.2
0
1.2
0
0
Vee
Vee
125
0
0
-40
NOM
5
MAX
6
UNIT
v
V
0.3
0.9
V
1.2
Vee
Vee
85
V
V
·e
SN54HC14. SN74HC14
HEX SCHMITT-TRIGGER INVERTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
MIN
TYP MAX
VCC
SN54HC14
SN74HC14
MIN
MIN
MAX
2V
1.9 1.998
1.9
1.9
VI = VIH or VIL.
10H = -20 p.A
4.5 V
4.4 4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
VI = VIH or VIL,
10H = -4 rnA
10H - -5.2 rnA
4.5 V
3.98
4.30
3.7
3.84
SV
5.48
itOH
VI - VIH or VIL,
5.80
5.2
MAX
V
5.34
2V
0.002
0.1
0.1
0.1
10L = 20 ~A
4.5 V
0.001
0.1
0.1
0.1
0.001
0.1
0.1
0.1
VI = VIH or VIL,
IOL=4rnA
SV
4.5 V
0.17
0.26
0.4
0.33
VI = VIH or VIL,
10L = 5.2 rnA
6V
0.15
0.26
0.4
0.33
1.2
1.50
VI = VIH or VIL,
VOL
2V
VT+
VT-
VT+ - VT-
0.70
VI = Vee or 0
VI = Vec or 0, 10 = 0
1.50
0.70
1.50
4.5 V
1.55
2.5
3.15
1.55
3.15
1.55
3.15
6V
2.10
3.3
4.20
2.10
4.20
2.10
4.20
2V
0.30
O.S
1.00
0.30
1.00
0.30
1.00
4.5 V
0.90
2.45
0.90
2.45
0.90
2.45
V
V
V
1.20
3.20
1.20
3.20
1.20
3.20
2V
0.20
O.S
1.20
0.20
1.20
0.20
1.20
4.5 V
0.40
0.9
2.10
0.40
2.10
0.40
2.10
SV
0.50
1.3
2.50
0.50
2.50
0.50
2.50
±0.1
±100
±1000
±1000
nA
2
40
10
20
10
~A
3
10
en
CD
U
6V
6V
2 to 6 V
I
'S:
1.6
2.0
6V
II
Ice
ej
0.70
UNIT
CD
Q
en
o
:E
V
o
:::t:
pF
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(INPUT)
A
TO
IOUTPUT)
Y
Y
VCC
TA = 25°C
MIN
TYP MAX
SN54HC14
MIN MAX
SN74HC14
MIN MAX
2V
55
125
190
155
4.5 V
12
25
38
31
6V
11
21
32
26
75
15
13
110
95
22
19
19
16
2V
38
4.5 V
8
6V
6
Power dissipation capacitance per inverter
No load, TA = 25°C
UNIT
n.
n.
20 pF typ
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-59
:x::
o
s:o
tn
C
CD
<
c;'
CD
VI
2-60
SN54HC20, SN74HC20
DUAL 4·INPUT POSITIVE·NAND GATES
02684, DECEMBER 19B2 - REVISED SEPTEMBER 1987
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300·mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC20 ... J PACKAGE
SN74HC20 .. , D OR N PACKAGE
(TOP VIEW)
1A
18
NC
1C
10
1Y
GNO
description
These devices contain two independent 4-input
NAND gates, They perform the Boolean
functiDnsY = A·B·C·DorY = A+B+C+Din
positive logic.
VCC
20
2C
NC
28
2A
2Y
II
SN54HC20 ... FK PACKAGE
(TOP VIEW)
The SN54HC20 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC20 is
characterized for operation from - 40°C to
85°C.
U
N
3 2 1 20 19
FUNCTION TABLE (each gate)
4
5
17
6
16
7
INPUTS
A
H
B
H
C
H
L
X
X
X
X
X
X
L
X
L
X
X
OUTPUT
D
H
X
X
X
L
8
Y
L
H
H
H
H
Nt-No internal connection
logic diagram (positive logic)
logic symbol t
&
1A
1B
lC
lD
2A
2B
2C
2D
14
9 1011 12 13
(21
(4)
lY
(51
(91
(101
1121
2Y
1131
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEe Publication 617-12.
Pin numbers shown are for 0, J. and N packages.
Copyright @ 1982, Texas Instruments Incorporated
TEXAS ."
INSlRUMENTS
POST OFfiCE 80X 855012 • DAllAS. TEXAS 7$265
2-61
SN54HC20, SN74HC20
DUAL 4·INPUT POSITIVE·NAND GATES
absolute maximum ratings over operating free· air temperature range t
Supply voltage, Vee ................................................ -0.5 V to 7 V
Input clamp current, IIK(VI < 0 or VI > Vee) ................................. ±20 mA
Output clamp current, 10K(VO < 0 or Vo > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) ................................ ± 25 mA
Continuous current through Vee or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ................ 260°C
Storage temperature range .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150 0 e
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
contitions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
vee
Supply voltage
Vee - 2 V
Vec = 4.5 V
Vee = 6 V
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
VIH
High-level input voltage
Vil
low-level input voltage
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and falll times
TA
Operating free-air temperature
Vee - 2 V
Vee = 4.5 V
Vee = 6 V
SN54HC20
NOM MAX
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-55
5
6
0.3
0.9
1.2
Vee
Vee
1000
500
400
125
MIN
SN74HC20
NOM MAX
UNIT
5
V
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-40
6
V
0.3
0.9
1.2
Vee
Vee
1000
500
400
85
V
V
V
ns
·e
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
VI
= VIH or Vll,
IOH
=
-20
~A
VOH
VI = VIH or Vll, IOH = -4mA
VI - VIH or Vll, IOH - -5.2 mA
VI
= VIH or Vll, IOl = 20 ~
VOL
II
ICC
CI
2·62
VI = VIH or Vll, IOl = 4 mA
VI - VIH or Vll, IOl = 5.2 mA
VI = Vee or 0
VI = Vee or 0, 10 = 0
4.5 V
6V
4.5V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 to 6 V
TA - 25·C
TYP MAX
MIN
1.9 1.998
4.4 4.499
5.9 5.999
3.98 4.30
5.80
5.48
0.1
0.002
0.001
0.1
0.001
0.1
0.17 0.26
0.15 0.26
±0.1 ±100
2
3
10
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 1;)55012 • DALLAS, TEXAS 75265
SN54HC20
MIN MAX
1.9
SN74HC20
MIN MAX
1.9
4.4
5.9
3.84
5.34
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
40
10
UNIT
V
0.1
0.1
0.1
0.33
0.33
±1000
20
10
V
nA
~
pF
SN54HC2D, SN74HC2D
TRIPLE 3-INPUT POSITIVE·NANO GATES
switching characteristics over recommended operating free· air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
tpd
tt
Cpd
FROM (INPUT)
A, B, C,
or
D
TO (OUTPUT)
vCC
2V
4.5 V
6V
2V
4.5 V
6V
Y
Y
TA - 25°C
M(N TYP MAX
45
110
14
22
19
11
75
27
15
9
13
7
SN54HC20
MIN MAX
165
33
2B
110
22
19
No load, TA - 25°C
Power dissipation capacitance per gate
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74HC20
MIN MAX
140
28
24
95
19
16
UN(T
ns
ns
25 pF typ
•
2-63
:c
(')
s:o
en
cCD
<
c;'
CD
til
2-64
SN54HC21. SN74HC21
DUAL 4·INPUT POSITIVE·AND GATES
02684, DECEM8ER 1982 - REVISED SEPTEM8ER 1987
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC21 , .. J PACKAGE
SN74HC21 ... 0 OR N PACKAGE
(TOP VIEW)
lA
18
NC
1C
10
1Y
GNO
description
These devices contain two independent 2-input
AND gates. They perform the Boolean functions
Y = A·B·C·D or Y = A+B+C+D in positive
logiC.
(TOP VIEW'
C
H
0
Y
H
H
L
X
X
X
L
X
L
X
X
L
X
X
L
X
L
X
X
X
L
L
lA
lC
10
2A
28
2C
20
111
«
U
3
2
1 2019
4
18
5
17
6
16
14
8
2C
NC
NC
NC
2B
9 10111213
;"CU;"«
-Z2NC'\I
(!)
NC - No internal connection
logic diagram (positive logic)
logic symbol t
18
til
7
OUTPUT
B
H
U
UC
~~Z>N
FUNCTION TABLE (each gate'
INPUTS
•
SN54HC21 ... FK PACKAGE
The SN54HC21 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC21 is
characterized for operation from - 40°C to
85°C.
A
H
VCC
20
2C
NC
2B
2A
2Y
&
121
}---lY
161
141
1Y
151
}---2Y
191
1101
181
1121
2Y
1131
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for Dr J, and N packages.
PROOUCTIOI DATA d••umBIII •••tli. i.'.rmlti••
currant .s of publicatioR date. Pradum canfarm to
.pacifications per thl terms at TillS Instruments
==~~i;·{::1~7i ~.=:~:r lI~a:::::.::~
nat
Copyright © 1982, Texas Instruments Incorporated
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-65
SN54HC21, SN74HC21
DUAL 4-INPUT POSITIVE-AND' GATES
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee ................................................ -0.5 V to 7 V
Input diode current, IIK(VI < 0 or VI > Vee) .................................. ±20 mA
Output diode current,IOK(VO < 0 or Va > Vee) .. , ..................... , ..... ±20 mA
Continuous output current, 10 (VA = 0 to Vee) ................................ ±25 mA
Continuous current through Vee or GND pins ................................. , ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300 °e
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ........ , ....... 260°C
Storage temperature range ......................................... - 65°C to 150°C
•
:::t:
(")
s:
o
tStresses beyond those listed under "'absolute maximum ratings'; may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "'recommended operating
contitions"' is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
tn
MIN
C
vee
Supply voltage
CD
<
rr
CD
VIH
High-level input voltage
VIL
Low-level input voltage
Vee
Vee
Vee
Vee
Vee
Vee
(II
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
TA
2
1.5
3.15
4.2
=2V
= 4.5 V
=6V
=2V
= 4.5 V
5
0
0
0
0
0
0
0
0
-55
=6V
Vee - 2 V
Vee = 4.5 V
Vee
SN54HC21
NOM MAX
=6V
Operating free-air temperature
6
0.3
0.9
1.2
Vee
Vee
1000
500
400
125
MIN
SN74HC21
NOM MAX
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-40
5
6
UNIT
V
V
0.3
0.9
1.2
Vee
Vee
1000
500
400
85
V
V
V
n.
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
VI
= VIH or VIL. 10H
= -20pA
VOH
VI = VIH or VIL. 10H
VI - VIH or VIL. 10H
=
=
VI = VIH or VIL. 10L
= 20 ~A
-4mA
-5.2 mA
VOL
II
lee
ei
2-66
VI - VIH or VIL. 10L - 4 mA
VI = VIH or VIL. 10L = 5.2 mA
VI - Vee or 0
VI - Vee or O. 10 - 0
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 to 6 V
TA - 26·C
TYP MAX
MIN
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.80
5.48
0.002
0.1
0.001
0.1
0.001
0.1
0.17 0.26
0.15 0.26
±0.1 ±100
2
10
3
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN64HC21
MIN MAX
1.9
4.4
5.9
3.7
5.2
SN74HC21
MIN MAX
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.4
0.4
±loo0
40
10
UNIT
V
0.1
0.1
0.1
0.33
0.33
±lOO0
20
10
V
nA
pA
pF
SN54HC21, SN74HC21
DUAL 4·INPUT POSITIVE·AND GATES
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL .. 50 pF (see Note 1)
PARAMETER
tpd
tt
Cpd
FROM (INPUT)
A, B, C, or 0
TO IOUTPUT)
vCC
2V
4.5 V
6V
2V
4.5 V
6V
Y
Y
TA - 25'C
MIN TYP MAX
44
110
14
22
11
19
29
75
10
15
8
13
SN54HC21
MIN MAX
165
No load, TA - 25'C
Power dissipation capacitance per gate
33
28
110
22
19
SN74HC21
MIN MAX
140
28
24
95
19
16
UNIT
ns
ns
25 pF typ
II
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·67
E
J:
(')
3:
oC/)
c
CD
<
(j"
CD
en
2-68
SN54HC27, SN74HC27
TRIPLE 3·INPUT POSITIVE·NOR GATES
02684. DECEMBER 1982-REVISED SEPTEMBER 1987
•
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
SN54HC27 ••• J PACKAGE
SN74HC27 ... 0 OR N PACKAGE
(TOP VIEW)
1A
1B
2A
2B
2C
2Y
GND
Dependable Texas Instruments Quality and
Reliability
description
These devices contain three independent 3-input
NOR gates. They perform the Boolean functions
Y=A+B+C or Y=A.i3;C in positive logic.
SN54HC27 .•. FK PACKAGE
CI)
(TOP VIEW)
CD
CJ
The SN54HC27 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC27 is
characterized for operation from - 40°C to
85°C.
'>CD
U
__ z>_
lDo(UUU
3
FUNCTION TABLE (each 9ata)
INPUTS
VCC
1C
1Y
3C
3B
3A
3Y
c
2 1 20 19
4
18
5
17
6
16
OUTPUT
7
15
A
B
C
Y
8
14
H
X
X
L
X
H
X
L
X
X
H
L
L
L
L
H
en
o
:!!:
o
J:
9 1011 12 13
NC- No internal connection
logic symbol t
lA
18
lC
2A
28
2C
3A
38
3C
(1)
logic diagram (positive logic)
;;'1
(2)
(13)
(3)
(4)
2Y
(5)
(9)
(10)
3Y
(11)
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617·12.
Pin numbers shown are for D. J. and N packages.
PRODUCTION DATA documlll" .ontain infannllion
CO""ot I. of p.bliclli•• dltl. P",ducts coofona t.
op..HicI1ionl PI' thl tarmo of TOIO Instrullim
:=~ri~"i:r.'li =::~. :.r'=:U~~ not
Copyright @ 1982. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DAl.LAS. TEXAS 75265
2-69
SN64HC27, SN74HC27
TRIPLE 3·INPUT POSITIVE·NOR GATES
absolute maximum ratings over operating free·air temperature range t
•
::J:
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > VCC) .. . . . . . . . . . . . . . . . . . . . . . . • . . . . . . •. ± 20 mA
Output clamp current, 10K NO < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ..........•.... 300 DC
Lead temperature 1,6 mm (1116 in) from case for 10 s: 0 or N package ............... 260 DC
Storage temperature range ......................................... - 65 DC to 150 DC
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device et these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
o
s:o
recommended operating conditions
en
cCD
SN54HC27
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0
0.9
0
1.2
0
Vee Supply voltage
<
(;'
Vee
Vee
Vee
Vee
Vee
Vee
VIH High-level input voltage
CD
til
VIL Low-level input voltage
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fam times
TA
Operating free-air temperature
Vee
Vee
Vec
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
0
0
0
0
0
-55
=2V
= 4.5 V
=6V
Vee
Vee
1000
500
400
125
SN74HC27
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0
0.3
0
0.9
1.2
0
0
Vee
0
Vee
0
1000
0
500
0
400
-40
85
UNIT
V
V
V
V
V
ns
·c
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
= VIH
or VIL.
10H
=
-20
VI
VI
= VIH
= VIH
or VIL.
or VIL.
10H
10H
=
=
-4mA
-5.2 mA
VI
= VIH
or VIL,
10L
= 20 ~A
VI
VI
VI
VI
= VIH or VIL, IOL=4mA
= VIH or VIL, 10L = 5.2 mA
= Vec or 0
= Vee or 0, 10 = 0
~A
VOH
VOL
II
lee
ei
2-70
TA = 25°C
TYP MAX
MIN
1.9 1.998
2V
4.5V
4.4 4.499
5.9 ·5.999
6V
4.5 V
3.98
4.30
6V
5.48
5.80
2V
0.002
0.1
4.5 V
0.001
0.1
0.001
0.1
6V
4.5 V
0.17
0.26
6V
0.15
0.26
6V
±0.1 ±100
6V
2
2 to 6 V
3
10
Vec
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC27
MIN MAX
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
40
10
SN74HC27
MIN MAX
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
20
10
UNIT
V
V
nA
~
pF
SN54HC21. SN14HC21
TRIPLE 3·INPUT POSITIVE·NOR GATES
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
Ipd
II
FROM
(INPUT)
A, B, or C
TO
IOUTPUT)
Y
Y
Vee
2V
4.5 V
6V
2V
4.5V
6V
=
TA
25°C
MIN
TYP MAX
35
90
10
18
9
15
27
75
7
15
6
13
Power dissipation capacitance per gate
SN54HC27
MIN MAX
135
27
23
110
22
19
SN74HC27
MIN MAX
115
23
20
95
19
16
UNIT
ns
n.
fI
No load, TA = 25°C
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-71
E
::I:
(")
3:
orJ)
c
CD
<
c:r
CD
til
2-72
SN54HC30, SN74HC30
8·INPUT POSITIVE·NAND GATES
02684. DECEMBER 1982-REVISED SEPTEMBER 1987
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC30 •.• J PACKAGE
SN74HC30 ... 0 OR N PACKAGE
(TOP VIEW)
A
VCC
NC
B
C
H
0
G
NC
NC
description
E
F
These devices contain a singie 8-input NAND
gate and perform the following Boolean
functions in positive logic:
GND
fI
Y
SN54HC30 ... FK PACKAGE
(TOP VIEW)
U
U UU
or
Z
3
The SN54HC30 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC30 is
characterized for operation from - 40°C to
85°C.
2
1 20 19
C
NC
5
17
0
6
16
8
14
18
4
NC
E
15
9 1011 1213
LLCU>U
FUNCTION TABLE
ZZ
Z
Cl
INPUTS A THRU H
OUTPUT
NC-No internal connection
y
All inputs H
L
One or more inputs L
H
logic diagram (positive logic)
A
logic symbol t
A
B
c
0
E
F
G
H
(1)
B
C
&
O - - - r - -...
(2)
E---,--_,
y
(3)
F
(4)
G
(5)
H
(6)
(11)
(12)
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for O. J. and N packages.
PRODUelIO. DATA dac....11 ..""'in Inflrmlltl••
c.....t II of publlllli•• dota. Plld_ .onflrm to
....Hi.IIi... JIIIr thalli"'. " l _ 1I11II'1I_
=i;;"f::t:Ti ~
==:..-
not
Copyright @ 1982. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALlAS, TEXAS 75265
2-73
SN54HC30, SN74HC30
8·INPUT POSITIVE·NAND GATES
absolute maximum ratings over operating free-air temperature range t
E
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300 DC
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260 De
Storage temperature range ....................•.................... - 65 DC to 150 DC
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute~maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC30
MIN
Vee Supply voltage
2
1.5
3.15
4.2
Vee = 2 V
Vee = 4.5 V
VIH High-Iavel input voltage
Vee = 6 V
Low-level input voltage
VIL
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
Vee = 2 V
Vee = 4.5 V
0
0
Vee = 6 V
0
0
0
0
Vee = 2 V
Vec = 4.5 V
Operating free-air temperature
SN74HC30
MAX
MIN
6
2
1.5
3.15
NOM
5
MAX
6
UNIT
V
V
4.2
0.3
0.9
1.2
Vee
Vce
1000
500
400
0
0
-55
Vee = 6 V
TA
NOM
5
125
0
0
0
0.3
0.9
1.2
V
0
0
Vee
VCC
1000
V
V
500
400
ns
85
°e
0
0
0
-40
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
Vce
VI = VIH or VIL.
10H = -20,.PI
VI = VIH or VIL.
VI = VIH or VIL.
10H = -4 mA
10H = -5.2 mA
VOH
VI = VIH or VIL.
10L = 20 ~A
VOL
II
lee
ei
2-74
VI
VI
VI
VI
=
=
=
=
VIH or VIL. IOL=4mA
VIH or VIL. 10L = 5.2 mA
Vee or 0
Vee or O. 10 = 0
2V
4.5 V
6V
4.5V
6V
2V
4.5 V
TA = 25°C
MIN
TYP MAX
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.48
5.80
0.002
6V
4.5 V
6V
6V
6V
2 to 6 V
TEXAS
0.001
0.001
SN54HC30
MIN MAX
1.9
4.4
5.9
3.7
SN74HC30
MIN MAX
1.9
4.4
5.9
3.84
5.2
V
5.34
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.17
0.15
0.26
0.26
0.1
0.4
0.4
0.33
0.33
±0.1
±100
2
10
±1000
40
10
±1000
20
10
3
-If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
0.1
V
nA
,.PI
pF
SN54HC30, SN74HC30
a-INPUT POSITIVE-NAND GATES
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(INPUT)
A thru H
TO
(OUTPUT)
Y
Y
Vee
TA ~ 25°C
MIN
SN54HC30
SN74HC30
MIN
MIN
TYP
MAX
MAX
2V
51
130
195
MAX
165
4.5 V
15
26
39
33
6V
12
22
28
2V
28
75
33
110
4.5 V
8
15
22
19
6V
6
13
19
16
No load, T A
Power dissipation capacitance per gate
~
25°C
UNIT
n.
95
n.
22 pF typ
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-75
E
::t
(")
s:o
en
o
(D
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,:SCD
(I)
2-76
SN54HC32, SN74HC32
QUADRUPLE 2·INPUT POSITIVE·OR GATES
02684, DECEMBER 1982-REVISED SEPTEMBER 1987
•
•
SN54HC32 , . , J PACKAGE
5N74HC32 , .. 0 OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
(TOPVIEWI
lA
18
Dependable Texas Instruments Quality and
Reliability
IV
2A
28
38
2Y
3A
GND '-1.._--,-r-3Y
description
These devices contain four independent 2-input
OR gates, They perform the Boolean functions
Y = A+B or Y = A:·S in positive logic,
fI
SN54HC32 . , • FK PACKAGE
The SN54HC32 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC32 is
characterized for operation from - 40°C to
85°C,
(TOPVIEWI
U
« Uz>-.:t
UIlI
__
III
J. 2
1 20 19
FUNCTION TABLE
(each gatel
INPUTS
OUTPUT
A
B
V
H
X
X
H
H
H
L
L
L
9 1011 12 lJ
NC-No internal connection
logic symbol t
logic diagram (positive logic)
lA
lB
2A
2B
(1)
;;>1
(2)
(3) lY
(4)
(5)
3A-1.9 )
(10)
38
(12)
4A
(13)
48
(6) 2Y
(8) 3Y
(111 4y
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for D. J. and N packages.
PRODUCTION DATA documa.t. co.tli. 1.IMlillio.
cur,..t a. 01 publlcllio. date, Producte co.form te
.pacIIIOltlo•• par the t.rml 01 T.u. IOltr••ante
.tand.rd warra.ty, Prod.ctio. p,.....I•• don lOt
n......rlly Includa tllti.g of all plrlll_no
Copyright © 1982, Texas Instruments Incorporated
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
2-77
SN54HC32. SN74HC32
QUADRUPLE 2·INPUT POSITIVE·OR GATES
absolute maximum ratings over operating free·alr temperature range t
II
Supply voltage, Vee .............................................. " -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) ............................... " ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300 0 e
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260 0 e
Storage temperature range ......................................... - 65 °e to 150 0 e
t Stresses beyond those listed under "absolute ma,ximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
::J:
n
s:o
recommended operating conditions
SN54HC32
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0
0.9
0
1.2
0
0
Vee
0
Vee
0
1000
0
500
400
0
-55
125
tn
C
Vee Supply voltage
CD
<
c:r
CD
Vee
Vee
Vee
Vee
Vee
Vee
vlH High-level input voltage
CII
VIL Low-level input voltage
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Input voltage
VI
Vo Output voltage
tt
Input transition Irise and fall) times
TA
Operating free-air temperature
Vee
Vee
Vee
=2V
= 4.5 V
=6V
SN74HC32
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0
0
0.9
0
1.2
0
Vee
0
Vee
0
1000
0
500
0
400
-40
85
UNIT
V
V
V
V
v
no
De
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
=
VI = VIH or VIL.
IOH
-20,.A
VI - VIH or VIL.
VI = VIH or VIL.
IOH - -4 mA
IOH = -5.2 mA
VI = VIH or VIL.
IOL = 20,.A
VOH
VOL
II
lee
ei
2-78
VI
VI
VI
VI
=
=
=
VIH or VIL. 10L = 4 mA
VIH or VIL. 10L - 5.2 mA
Vee orO
Vee or O. 10 = 0
TA = 2SoC
MIN
TVP MAX
2V
1.9 1.998
4.5V
4.4 4.499
6V
5.9 5.999
4.5V
3.98 4.30
6V
5.48
5.80
2V
0.1
0.002
4.5V
0.001
0.1
6V
0.001
0.1
4.5V
0.17 0.26
6V
0.15
0.26
6V
±0.1 ±100
6V
2
2 to 6 V
10
3
Vce
, TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265
SN54HC32
MIN MAX
1.9
4.4
6.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
40
10
SN74HC32
MIN MAX
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±IOO0
20
10
UNIT
V
V
nA
,.A
pF
SN54HC32. SN74HC32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
switching characteristics over recommended operating free-air temperature range lunless otherwise
noted). CL = 50 pF Isee Note 1)
PARAMETER
tpd
FROM
IINPUTI
A or B
TO
(OUTPUT)
VCC
2V
4.5 V
y
6V
tt
Y
2V
4.5 V
6V
TA = 2S·C
MIN TVP MAX
50
100
10
20
8
17
38
75
8
15
13
6
SNS4HC32
MIN MAX
150
30
25
110
22
19
SN74HC32
MIN MAX
125
25
21
95
19
16
UNIT
n.
n.
No load, T A = 25°C
Power dissipation capacitance per gate
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-79
J:
C')
:s:
oCJ)
c
CD
<
c;"
CD
til
2-80
S154HCT32, SI74HCT32
QUADRUPLE 2-INPUT POSITIVE-DR GATES
03246. NOVEMBER 1988
•
Inputs are TTL-Voltage Compatible
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DiPs
•
SN54HCT32 ..• J PACKAGE
SN74HCT32 ... D OR N PACKAGE
(TOP VIEW)
48
4A
Dependable Texas Instruments Quality and
Reliability
4Y
38
28
3A
2Y
GND '1-_ _;;r"
description
These devices contain four independent 2-input
OR gates. They perform the Boolean functions
y = 'Ao'B or Y = A + B in positive logic.
V
H
X
H
X
H
L
L
H
L
18
2A
2B
(11
3
2 1 20 19
U Um
....
4
18
5
17
6
16
7
15
8
14
NC - No internal connection
logic diagram (each gate) (positive logic)
logic symbol t
lA
«
9 1011 1213
OUTPUT
B
U
m
~~z>
FUNCTION TABLE
(each gate)
INPUTS
PI
SN54HCT32 •.. FK PACKAGE
(TOP VIEW)
The SN54HCT32 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HCT32 is
characterized for operation from - 40°C to
85°C.
A
Vee
lA
;;'1
121
:=D-V
131 IV
141
(51
3A....l91
(101
161 2y
181 3V
38
4A
4B
1121
1131
(111 4V
tThis symbol is in accordance with ANSI/lEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for D. J. and N packages.
NO/IUCTIOI DATA ....._ _ iltflrllatiH
••nut II If ........ UtI. PnoI......... 1O
If T_ InInmHtI
....nI .......
:
Pn••ctllII ~., .... not
-.IIy I
lalla, If .n ...._
...malllu .. tile _
Copyright @ 1988. Texas Instruments Incorporated.
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75265
2-81
SN54HCT32,SN14HCT32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
absolute maximum ratings over operating free-air temperature range t
E
::z:
(")
:s:
o
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (V, < 0 or V, > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Va < 0 or Va > vCC) ............................. ±20 mA
Continuous output current, 10 (VA = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vccor GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300 D C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260 D C
Storilge temperature range ......................................... - 65 DC to 150 DC
tStresses' beyond those listed under "abSolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure. to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
en
c
CD
<
C;CD
(I)
SN54HCT32
Vee
VIH
VIL
VI
Vo
tt
TA
2-82
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
I Vee
I
= 4.5 V to 5.5 V
Vee - 4.5 V to 5.5 V
Input transition (rise and fam times
Operating free-air temperature
SN74HCT32
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
2
0
0
0
0
-55
TEXAS .."
INSTRUMENTS
POST ·OFFICE BOX 655012 • DALLAS, TEXAS 75265
0.8
Vee
Vee
500
125
2
0
0
0
0
-40
0.8
Vee
Vee
500
85
UNIT
V
V
V
V
V
ns
De
SN54HCT32, SN74HCT32
QUADRUPLE 2·INPUT POSITIVE·OR GATES
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
TEST CONDITIONS
PARAMETER
VOH
VOL
II
ICC
41eet
VI
=
VIH or VIL,
VI - VIH or VIL,
VI = VIH or VIL,
VI = VIH or VIL,
VI - Vee or 0
VI = Vee or 0,
One input at 0.5 V
VCC
10H = -20~
10H - -4 mA
10L
10L
= 20 ~
= 4 mA
10 = 0
or 2.4 V,
Other inputs at 0 V or Vee
4.5 V
4.5 V
4.5 V
4.5V
5.5 V
5.5 V
TA - 2Soc
MIN
TYP MAX
4.4 4.499
3.98
4.30
0.001
0.1
0.17
±0.1
5.5 V
4.4
3.7
SN74HCT32
MIN MAX
UNIT
4.4
3.84
0.1
0.4
±1000
V
0.1
V
nA
40
0.33
±1000
20
~
1.4
2.4
3
2.9
mA
3
10
10
10
pF
4.5 to
ej
0.26
±100
2
SN54HCT32
MIN MAX
5.5 V
en
CI)
U
tThis is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or Vee.
'S;
switching characteristics over recommended operating free· air temperature range (unless otherwise
noted). CL -= 50 pF (see Note 1)
C
CI)
PARAMETER
tpd
tt
FROM
!INPUT)
A or B
TO
(OUTPUT)
Vcc
Y
4.5 V
5.5 V
15
13
Y
4.5 V
5.5 V
9
8
SN54HCT32
MIN MAX
SN74HCT32
MIN MAX
24
22
36
32
15
14
22
20
30
27
19
TA - 25°C
MIN
TYP MAX
17
UNIT
en
o
~
(.)
ns
::I:
ns
20 pF typ
Power dissipation capacitance per gate
NOTE 1: Load circuit and voltage waveforms are shown in Section 1 of the High·Speed CMOS Logic Data Book, 1988.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-83
::I:
o
s:
orJ)
c
CD
<
c:r
CD
(I)
2-84
SN54HC36, SN74HC36
QUADRUPLE 2·INPUT POSITIVE·NOR GATES
02684. DECEMBER 1982 - REVISED SEPTEMBER 1987
•
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300·mil
DIPs
SN54HC36 ... J PACKAGE
SN74HC36 ... 0 OR N PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
Dependable Texas Instruments Quality and
Reliability
description
These devices contain four independent 2·input
NOR gates. They perform the Boolean functions
Y = A+B or Y = 'A.S in positive logic.
Vee
4B
4A
4Y
3B
3A
3Y
GND
II
SN54HC36 ... FK PACKAGE
(TOP VIEW)
The SN54HC36 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC36 is
characterized for operation from - 40°C to
85°C.
II)
Q)
(,)
0>
U
cov
3
2
o
1 20 19
fJ)
18
o
17
FUNCTION TABLE (each gate)
:!:
16
INPUTS
OUTPUT
A
H
X
H
L
L
L
H
B
X
u
15
Y
J:
14
L
9 1011 12 13
>-OU>-1
121
'.1
(61
(91
(101
(121
(131
tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for D. J, and N packages.
PRDDUcnDI DATA ........IdI_ln inlanlilial
..met I. of~...... P'-- CD""",, to
~. por tIoo tw. . of Till. I............
-=~~=~III
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright @ 1982, Texas Instruments Incorporated
2·85
SN54HC36, SN74HC36
QUADRUPLE 2·INPUT POSITIVE· NOR GATES
absolute maximum ratings over operating free-air temperature range t
E
:::J:
(')
s:o
Supply voltage, VCC ................................................ -0.5 V to 7 V
Input clamp current, IIK(VI < 0 or VI > VCC) ................................. ±20 mA
Output clamp current, 10K(VO < 0 or Vo > Vcc) .............................. ±20 mA
Continuous output current, 10 (Vo = 0 to Vcc) ................................ ± 25 mA
Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300 DC
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ................ 260 DC
Storage temperature range ......................................... - 65 DC to 150 DC
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
contitions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
en
MIN
cCD
Vec
<
c;'
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Vo
Input voltage
Output voltage
tt
Input transition ,rise and falll times
Vee
VCC
VCC
VCC
Vee
VCC
CD
en
TA
=
=
=
=
2V
4.5 V
6V
2V
4.5 V
6V
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
Operating free-air temperature
SN64HC36
NOM MAX
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-55
5
6
0.3
0.9
1.2
Vec
VCC
1000
500
400
125
MIN
SN74HC36
NOM MAX
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-40
5
6
UNIT
V
V
0.3
0.9
1.2
VCC
VCC
1000
500
V
V
V
ns
400
85
·C
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
VI = VIH or VIL. IOH = -20 pA
VOH
VI = VIH or VIL. IOH - -4mA
VI - VIH or VIL. IOH = -5.2 mA
VI = VIH or VIL. IOL = 20 ~A
VOL
II
ICC
Ci
2-86
VI
VI
VI
VI
=
VIH or VIL. IOL = 4 mA
VIH or VIL. IOL - 5.2 mA
Vec orO
Vee or O. 10 = 0
4.5V
6V
4.5 V
6V
2V
4.5V
6V
4.5V
6V
6V
6V
2 to 6 V
TA - 25·C
TYP MAX
MIN
1.9 1.998
4.4 4.499
5.9 5.999
3.98 4.30
5.48
5.80
0.002
0.1
0.001
0.1
0.001
0.1
0.17 0.26
0.15 0.26
±0.1 ±loo
2
3
10
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TeXAS 75265
SN54HC38
MIN MAX
1.9
4.4
5.9
3.7
5.2
SN74HC38
MIN MAX
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.4
0.4
±1000
40
10
UNIT
V
0.1
0.1
0.1
0.33
0.33
±1000
20
10
V
nA
pA
pF
SN54HC36, SN74HC36
QUADRUPLE 2·INPUT POSITIVE·NOR GATES
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted). CL - 50 pF (see Note 11
PARAMETER
tpd
tt
Cpd
FROM (INPUT!
A or B
TO (OUTPUT!
vCC
TA - 25°C
MIN
2V
4.5 V
6V
2V
4.5 V
6V
Y
Y
TYP
MAX
50
10
110
20
8
17
38
75
15
13
8
6
SN54HC36
SN74HC36
MIN
MIN
No load, TA - 25°C
Power dissipation capacitance per gate
MAX
150
30
25
110
22
19
UNIT
MAX
125
25
21
95
19
16
ns
ns
20 pF typ
U)
CD
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
U
'S:
CD
Q
en
o
:;
o
l:
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·87
:x:
n
s:
oen
c
CD
<
,;,
CD
en
2-88
SN54HC42. SN14HC42
4·L1NE TO 10·L1NE DECODERS (1·of·10)
02684, DECEMBER 1982-REVISEO JUNE 1989
SN54HC42 ... J PACKAGE
SN74HC42, .. ot OR N PACKAGE
•
Full Decoding of Input Logic
•
All Outputs are High for Invalid BCD
Conditions
•
•
•
(TOP VIEW)
0
Also for Application as 3·Line to a·Line
Decoders
VCC
A
B
2
3
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300·mil
DIPs
Dependable Texas Instruments Quality and
Reliability
C
D
4
5
6
9
8
GND
7
SN54HC42 ... FK PACKAGE
(TOP VIEW)
description
C,)
These monolithic decimal decoders consist of
eight inverters and ten four-input NAND gates,
The inverters are connected in pairs to make
BCD input data available for decoding by the
NAND gates, Full decoding of valid input logic
ensures that all inputs remain off for all invalid
input conditions.
C,)
C,)
02>«
3
The SN54HC42 is characterized for operation
over the full military temperature range of
- 55 DC to 125 DC, The SN74HC42 is
characterized for operation from -40°C to
85°C,
2
1 2019
2
3
4
18
B
5
17
NC
6
16
15
C
NC
D
5
8
14
9
9 1011 12 13
eeoC,),....
~
H
INPUTS
0
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L L H
L H L
L H H
H L L
H L H
H H L
H H H
L L L
L L H
L H L
L H H
H L L
H L H
H H L
H H H
= high level,
L
=
logic symbol:!:
OUTPUTS
C B A
L L L
0
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1
2
H H
L H
H L
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
3
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
4
5 6
7 8
H H H H H
H H H H H
H H H H H
H H H H H
L H H H H
H L H H H
H H L H H
H H H L H
H H H H L
H H H H H
H H H H H
H H H H H
H H H H H
H H H H H
H H H H H
H H H H H
9
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
8CO/OEC
A
(151
B
(14)
C
(131
o
(12)
tThese symbols are in accordance with ANSI/IEEE SId 91-1984
and IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
low level
PRODUCTION DATA do.umenls .onlain information
currant as of publication datI. Products conform tD
.pecifications par the terms of Taxas Instruments
:'~='irv8{::1~1i ~:\::i:; :IID::~::::~:'~S not
Copyright © 1989, Texas Instruments Incorporated
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
2-89
SN54HC42, SN74HC42
4·LlNE TO 10·LlNE DECODERS (1·of·10)
logic diagram (positive logic)
INPUT A(15)
•
INPUT a(14)
::t:
n
s:o
en
c
CD
<
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CD
(I)
Pin numbers shown are for D. J. and N packages.
2-90
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SN54HC42, SN74HC42
4-LlNE TO 10-LlNE DECODERS (1-of-10)
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ± 20 mA
Continuous output current, 10 (Va = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
en
CD
U
recommended operating conditions
'S
MIN
Vee Supply voltage
2
1.5
3.15
4.2
Vee = 2 V
Vee = 4.5 V
VIH High-level input voltage
Vee = 6 V
VIL
Low-level input voltage
VI
Vo
Input voltage
Output voltage
0
0
0
0
Vee = 4.5 V
0
-55
Vee = 6 V
TA
Operating free-air temperature
6
0.3
0.9
1.2
0
0
Vee = 2 V
Input transition (rise and fall) times
5
0
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
tt
SN54HC42
NOM MAX
MIN
SN74HC42
NOM MAX
2
1.5
3.16
4.2
5
6
CD
UNIT
V
V
c
en
o
:E
(.)
0
0
::J:
0.3
0.9
1.2
V
Vee
0
0
Vee
V
Vee
1000
0
0
Vee
1000
V
500
400
125
0
0
-40
500
ns
400
85
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
VI = VIH or VIL.
10H = -20/LA
4.5 V
6V
VOH
4.5 V
VI = VIH or VIL.
10H = -4 mA
10H = -5.2 mA
VI = VIH or VIL.
10L = 20/LA
4.5 V
VI = VIH or VIL.
VI - VIH or VIL.
VI - Vee or 0
10L = 4 mA
10L = 5.2 mA
4.5 V
VI = VIH or VIL.
6V
2V
6V
VOL
II
lee
ej
VI = Vee or O. 10 = 0
6V
6V
TA = 25°C
MIN
TYP MAX
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.48
5.80
0.002
0.001
0.1
0.1
0.001
0.17
0.15
±0.1
0.1
0.26
0.26
±100
3
8
10
6V
2 to 6 V
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SN54HC42
SN74HC42
MIN
1.9
MIN
1.9
MAX
4.4
4.4
5.9
3.7
5.2
5.9
3.84
5.34
0.1
0.1
0.1
0.4
0.4
±1000
160
10
MAX
UNIT
V
0.1
0.1
0.1
0.33
0.33
±1000
80
10
V
nA
p,A
pF
2-91
SN54HC42. SN74HC42
4-lINE TO 10-UNE DECODERS (1-of-10)
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUTI
vCC
2V
tpd
•
::E:
(')
s:o
tt
A, B, C, or 0
o thru 9
4.5 V
6V
2V
4.5 V
6V
Any
TA = 25°C
TYP MAX
MIN
65
150
18
14
28
8
7
SN54HC42
MIN MAX
SN74HC42
MIN MAX
225
45
190
30
26
75
15
13
38
110
22
19
38
32
95
19
16
UNIT
ns
ns
.------.-------------------------.------------------.-----------~
No load, TA = 25°C
Power dissipation capacitance
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
(I)
c
CD
<
(;'
CD
(I)
2-92
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
39 pF typ
SN54HC51, SN74HC51
AND·OR·INVERT GATES
02684, DECEMBER 1982-REVISED SEPTEMBER 1987
•
•
SN54HC51 ... J PACKAGE
SN74HC51 ... 0 DR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
(TOP VIEW)
lA
Dependable Texas Instruments Quality and
Reliability
description
The 'HC51 provides 2-wide, 2-input, and 2-wide,
3-input AND-OR-INVERT gates. The device performs
the following Soolean functions:
lV
11A.1S·1C) + 11D.1E.1F)
2V
12A.2B) + 12C·2D)
2A
VCC
lC
28
18
2C
20
1F
2Y
10
GNO
lY
IE
en
(TOP VIEW)
Q)
(,)
.S;
3
The SN54HC51 is characterized for operation over the
full military temperature range of - 55°C to 125°C.
The SN74HC51 is characterized for operation from
-40°C to 85°C.
6
20
INPUTS
OUTPUT
lA lB lC lD IE IF
IV
Q)
2 1 2019
4
5
FUNCTION TABLES
18
18
17
NC
IF
16
15
14
8
L
L
NC-No internal connection
X
o
~
NC
IE
o
J:
--
X
X
H
tJ)
0
X X H H H
Any other combination
H
X
Q
9 1011 12 13
o u >
>
N
Z Z
t!l
H
II
SN54HC51 ... FK PACKAGE
H
logic diagram (positive logic)
INPUTS
OUTPUT
2A
2B
2C
20
H
H
X
X
2V
L
X
X
H
H
L
H
Any other combination
H = high level, L = low level, X = irrelevant
2A
2 8 - - ,_ _
logic symbol t
lA
18
lC
10
IE
IF
2A
28
2C
20
(1)
&
2V
;>1
(12)
2C _---Jr--....
(13)
20---'L-_'
(9)
&
(10)
(II)
(2)
&
;>1
(3)
(4)
&
(5)
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
PRODUCTION DATA documants contain information
currant I. of publication data. Products conform to
specifications par the terms at Taus Instrumants
:=~:~~1{::1~7~ ~!:~:~ti:; :'~D:::;;:r::.~s
not
Copyright © 1982, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-93
SN54HC51, SN74HC51
AND·DR·INVERT GATES
absolute maximum ratings over operating free·air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) ................................ , ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Continuous output current, 10 (VO = 0 to Vcc) ....•.......................... , ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300 DC
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ............... 260 DC
Storage temperature range ......................................... - 65 DC to 150 DC
::c
o
s:
otJ)
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum·rated conditions for extended periods may affect device reliability.
recommended operating conditions
cCD
<
c:r
CD
SN54HC51
MIN NOM MAX
2
5
6
1.5
3.15
4.2
Vee Supply voltage
Vee
Vee
VIH High-level input voltage
Vee
(I)
VIL
Vee
Vee
Low·level input voltage
Vee
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
Vee
Vee
Vee
TA
=2V
= 4.6 V
=6 V
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Operating free-air temperature
SN74HC51
MIN NOM MAX
2
1.5
3.15
5
0.3
0.9
0
0
0
0
1.2
Vee
Vee
1000
0
0
0
0
0
0
0
-55
500
400
125
0
0
-40
UNIT
V
V
4.2
0
0
0
6
0.3
0.9
V
1.2
Vee
Vee
1000
V
V
500
400
ns
85
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
TEST CONDITIONS
PARAMETER
VI
= VIH or VIL.
=
10H
VCC
-20pA
VOH
VI
= VIH or VIL.
10H - -4mA
10H = -5.2 mA
VI
= VIH or VIL.
10L
VI - VIH or VIL.
= 20 pA
VOL
II
lee
ei
2-94
VI = VIH or VIL.
VI - VIH or VIL.
VI = Vee orO
VI
10L = 4 mA
10L - 5.2 mA
= Vee or O. 10 = 0
2V
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 to 6 V
TA = 25·C
MIN
TVP MAX
1.9 1.998
SN54HC51
MIN MAX
1.9
4.4 4.499
5.9 6.999
4.30
3.98
4.4
5.9
3.7
5.2
5.48
5.80
0.002
0.001
0.001
0.17
0.15
±0.1
3
SN74HC61
MIN MAX
1.9
4.4
5.9
UNIT
V
3.84
5.34
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.26
0.26
0.4
0.4
±1000
0.33
0.33
±1000
nA
40
10
20
10
p.A
pF
±100
2
10
TEXAS .."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V
SN54HC51, SN74HC51
AND·OR·INVERT GATES
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
tpd
tt
Cod
FROM
(INPUT)
Any
TO
(OUTPUT)
VCC
2V
4.5V
y
Y
6V
2V
4.5 V
6V
Power dissipation capacitance per AOI gate
TA - 25°C
MIN
TVP MAX
54
15
12
28
9
8
140
28
24
75
15
SN54HC51
MIN MAX
210
42
13
No load, TA = 25°C
36
110
22
19
SN74HC51
MIN MAX
175
35
30
95
19
16
25 pF typ
UNIT
n.
n.
fI
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-95
::l:
o
s:o
en
c
CD
<
c;'
CD
en
2-96
SN54HC73, SN74HC73
DUAL J·K FLlp·FLOPS WITH CLEAR
02684. DECEM8ER 1982-REVISED SEPTEMBER 1987
•
Packaga Options Include Plastic "Small
Outline" Packages and Standard Plastic and
Ceramic 300-mil DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC73 ... J PACKAGE
SN74HC73 .•• D OR N PACKAGE
(TOP VIEW)
1CLK
1CLR
1K
VCC
2CLK
2CLR
2J
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the Clear input resets the outputs regardless of
the other inputs. When Clear is inactive (high),
data at the J and K inputs meeting the setup time
requirements are transferred to the outputs on
the negative-going edge of the clock pulse.
Following the hold time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. These flip-flops can also
perform as toggle flip-flops by tying J and K high.
The SN54HC73 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC73 is
characterized for operation from - 40°C to
85°C.
INPUTS
J
K
Q
L
X
I
I
I
I
H
X
L
H
L
H
X
X
L
L
H
H
X
H
L
00
H
00
L
H
H
H
1J
1Q
1CLK
1K
1Q
1CLR
2J
2CLK
2K
2CLR
Q
CLK
H
logic symbol t
OUTPUTS
CUI
H
For functionally and electrically identical
parts in chip carrier. see SN54HC107.
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
FUNCTION TABLE
(EACH FLIP-FLOP)
H
1J
10
10
GND
2K
20
20
L
TOGGLE
00
00
logic diagram. each flip-flop (positive logic)
K
o
_.a...-r--,
CLK~:
crR--------q
~o_--------------
PRDDucnOI DATA doc.manto call1li. i.lonnllioa
curnat II of ....llcatiD. dIlL Prodleto ca.!ann II
opocificatil.1 par t .. WIll of T.... lnotrullim
~~"r::I":li
=:::=.:~
not
__--------------------------------~
Copyright @ 1982, Texas Instruments Incorporated
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-97
SN54HC73. SN74HC73
DUAL J-K FLIP-FLOPS WITH CLEAR
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Va < 0 or Va > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
eontinuous output current, 10 (Va = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
eontinuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: J package ................... 300 0 e
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260 0 e
Storage temperature range ......................................... - 65 °e to 1 50 °e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating.
conditions" is not implied. Exposure to absolute~maximum-rated conditions for extended periods may affect device reliability.
::I:
(')
s:o
recommended operating conditions
SN54HC73
en
c
Vee Supply voltage
<
VIH High-level input voltage
CD
c:r
CD
Vee
Vee
Vee
Vee
til
Low-level input voltage
VIL
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
SN74HC73
MIN
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
1.5
1.5
3.15
4.2
3.15
UNIT
v
V
4.2
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
V
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
0
Vee
1000
0
0
Vee
1000
V
ns
Vee
Input transition (rise and fall) times
tt
Vee
Vee
=2V
= 4.5 V
=6V
Operating free-air temperature
TA
0
500
0
500
0
400
0
400
-55
125
-40
85
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
VI
=
VIH or VIL,
10H
=
-20
VI
=
=
VIH or VIL,
10H
-4 rnA
VIH or VIL,
10H
=
=
~A
VOH
VI
VI
=
VIH or VIL,
10L
=
20 ~A
VOL
VI
VI
2-98
II
VI
lee
ei
VI
=
=
=
=
VIH or VIL,
IOL
VIH or VIL,
IOL
= 4 rnA
= 5.2 rnA
Vee or 0
Vee or 0, 10
=0
SN54HC73
SN74HC73
MIN
MIN
MAX
1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
5.9 5.999
3.9B
4.30
5.9
3.7
5.9
3.84
4.5 V
-5.2 rnA
TA - 25°C
MIN
TYP MAX
6V
1.9
5.4B
5.BO
5.2
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.26
0.4
0.33
6V
0.17
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
4
80
40
~A
10
10
10
pF
6V
2 to 6 V
3
-Ii}
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V
SN54HC73, SN74HC73
DUAL J·K FLlp·FLOPS WITH CLEAR
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
ClK high or low
Pulse duration
tw
ClR low
Setup time, CLR inactive
tsu
or data before ClK I
Hold time, data after ClK I
th
TA - 25°C
MIN
MAX
SN54HC73
SN74HC73
MIN
MAX
MIN
MAX
4.2
0
5
2V
0
6
0
4.5 V
0
31
0
21
0
25
6V
0
36
0
25
0
29
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
100
150
125
4.5 V
25
35
30
6V
20
30
25
2V
0
0
0
4.5 V
0
0
0
6V
0
0
0
UNIT
MHz
ns
ns
CI)
Q)
ns
FROM
!INPUT)
TO
(OUTPUT)
VCC
2V
f max
tpHl
tpLH
tpd
tt
4.5 V
6V
ClR
ClR
CLK
Q
a
Q ora
Any
TA - 25°C
MIN
TYP MAX
6
31
36
SN74HC73
MIN
11
4.2
5
21
25
29
25
C
o
MIN
54
64
'S;
Ul
SN54HC73
MAX
o
Q)
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
II
MAX
:iE
u
J:
UNIT
MHz
2V
78
155
250
194
4.5 V
16
31
47
39
6V
13
26
40
32
194
2V
78
155
250
4.5 V
16
31
47
39
6V
13
26
32
160
2V
63
126
40
185
4.5 V
13
25
37
32
6V
11
21
32
27
95
2V
38
75
110
4.5 V
8
15
22
19
6V
6
13
19
16
ns
ns
ns
ns
Power dissipation capacitance per flip-flop
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-99
E
:J:
(")
s:o
(J)
c
<
n"
CD
CD
(I)
2-100
SN54HC74, SN74HC74
DUAL D·TYPE POSITIVE·EDGE·TRIGGERED
FLlP·FLOPS WITH CLEAR AND PRESET
02684. DECEMBER 1982-REVISED JUNE 1989
•
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
SN54HC74 ... J PACKAGE
SN74HC74 ... 0 OR N PACKAGE
(TOP VIEW)
lCLR
Dependable Texas Instruments Quality and
Reliability
vcc
10
description
These devices contain two independent Ootype
pDsitive-edge-triggered flip-flops. A low level at
the Preset or Clear inputs sets or resets the
outputs regardless of the levels of the other
inputs. When Preset and Clear are inactive
(high), data at the 0 input meeting the setup time
requirements are transferred to the outputs on
the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold time interval, data at the 0
input may be changed without affecting the
levels at the outputs.
2CLR
lCLK
20
lPRE
2CLK
lQ
2PRE
10
2Q
GNO
20
II
SN54HC74 ... FK PACKAGE
(TOP VIEW)
~I~
3
U
Z
Ia:
U..J
UU
N
>
2 1 20 19
lCLK
4
18
NC
lPRE
5
17
6
16
8
14
NC
lQ
The SN54HC74 is characterized for operation
over the full military temperature range - 55°C
to 125°C. The SN74HC74 is characterized for
operation from -40°C to 85°C.
NC
15
NC
9 1011 12 13
10
o u
z Z
10 0
N
N
(!)
NC - No internal connection
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
CLK
0
Q
L
H
X
X
X
H
L
L
X
X
X
i
i
H
H
L
Hi
H
Hi
H
L
L
L
X
L
Qo
00
L
L
H
H
H
H
H
H
logic symbol*
li
PRE
10
lCLK
10
1CLR
2PRE
H
20
2CLK
20
2CLR
t This configuration is nonstable; that is, it will not persist
when Preset or Clear returns to its inactive (high) level.
logic diagram, each flip-flop (positive logic)
; This symbol is in accordance with ANSI/IEEE Std 91·1984 and
IEC Publication 617·12.
Pin numbers shown are for 0, J, and N packages.
PRE --------------------------~~-----.
CLK~:
D
o
-----------1
CLR ________________~~------------------------------J
PRODUCTION DATA doc.monts contain information
curreot as of publication date. Products conform to
spacificatioRs par the terms of Taxas Instrumeots
==~~i;8i~:I~'li
=::i:; ~~o=:~::.~s not
Copyright @ 1989. Texas Instruments Incorporated
.
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-101
SN54HC74, SN74HC74
DUAL D·TYPE POSITIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH CLEAR AND PRESET
absolute maximum ratings over operating free-air temperature range t
•
::t
Supply voltage, Vcc . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . • . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . • . • . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . • . . • . . . • . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . • . . . . . • . . . . . . . . . . . . .. ±25 mA
Continuous current through VCC or GND pins .........................•...•.•.. ±50 mA
Lead temperature 1,6 mm (1116 in) from case for 60 s: FK or J package . . . . . . . . • . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ..........•.... 260°C
Storage temperature range ..•.......................•......•.•....• - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute·maxlmum·rated conditions for extended periods may affect device reliability.
(')
s:o . recommended operating conditions
SN&4HC74
MIN NOM MAX
2
5
6
1.5
3.16
4.2
0.3
0
0
0.9
1.2
0
0
Vee
0
Vee
1000
0
0
500
400
0
-55
125
en
c
Vee Supply voltage
<
(;'
VIH High·level input voltage
GI
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
GI
«n
Vil low·level input voltage
VI Input voltage
Vo Output voltage
tt
Input transition (rise and fall) times
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
TA Operating free·air temperature
SN74HC74
MIN NOM MAX
2
6
6
1.6
3.15
4.2
0.3
0
0
0.9
1.2
0
0
Vee
0
V~e
0
1000
0
500
0
400
-40
85
UNIT
V
V
V
V
V
ns
"e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
= VIH or Vil.
10H
=
-20 ~A
VI - VIH or Vil.
VI = VIH or Vil.
10H
10H
=
=
-4mA
-5.2 mA
= VIH or Vil.
10l
= 20 ~A
VI
VOH
VI
VOL
II
lee
ei
2-102
VI = VIH or Vil. 10l = 4mA
VI - VIH or Vil. 10l = 5.2 mA
VI = o or Vee
VI - 0 or Vee. 10 - 0
TA - 25"C
TYP MAX
MIN
2V
1.9 1.998
4.5V
4.4 4.499
6V
6.9 6.999
4.5 V
3.98 4.30
6V
5.48
5.80
0.1
2V
0.002
4.5 V
0.001
0.1
6V
0.001
0.1
4.5V
0.17 0.26
6V
0.15 0.26
6V
±0.1 ±100
6V
4
2 to 6 V
10
3
VCC
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54HC74
MIN MAX
1.9
4.4
6.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
80
10
SN74HC.74
MIN MAX
1.9
4.4
5.9
3.84
6.34
0.1
0.1
0.1
0.33
0.33
±1000
40
10
UNIT
V
V
nA
~
pF
SN54HC74. SN74HC74
DUAL D·TYPE PDSITIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH CLEAR AND PRESET
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vcc
ClK high or low
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
Data
6V
2V
4.5 V
fclock Clock frequency
PREormlow
Pulse duration
tw
Setup time
before ClKt
tsu
J5Rr or m
inactive
Hold time data after ClKt
th
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 26°C
MIN
MAX
0
6
31
0
0
36
100
20
17
80
16
14
100
20
17
25
5
4
0
0
0
SN64HC74
MIN MAX
0
4.2
0
21
0
25
150
30
25
120
24
20
150
30
25
40
8
7
0
0
0
SN74HC74
MIN MAX
0
5
25
0
0
29
125
25
21
100
20
17
125
25
21
30
6
5
0
0
0
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
PRE or
CIA:
Q or
Ci
tpd
ClK
tt
Q or Q
Qora
Vcc
2V
4.5V
6V
2V
4.5 V
6V
2V
4.5V
6V
2V
4.5V
6V
TA - 26°C
MIN
TYP MAX
6
10
31
50
36
60
70
230
20
46
15
39
175
70
20
35
15
30
28
75
8
15
6
13
Power diSSipation capacitance per flip-flop
SN64HC74
MIN MAX
4.2
21
25
345
69
59
250
50
42
110
22
19
SN74HC74
MIN MAX
5
25
29
290
58
49
220
44
37
95
19
16
UNIT
MHz
ns
ns
No load, TA = 25°C
NOTE 1: load circuit and voltage waveforms are shown in Section 1.
TEXAS
..If
INSfRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
2-103
E
::I:
o
3:
otn
C
CD
<
5'
CD
o
2-104
SN54HCT74, SN74HCT74
DUAL D·TYPE POSITIVE·EDGE·TRIGGERED
FLlP·FLOPS WITH CLEAR AND PRESET
D26B4, DECEMBER 19B2-REVISED SEPTEMBER 19B7
•
Inputs are TTL·Voltage Compatible
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
SN54HCT74 ... J PACKAGE
SN74HCT74 ... 0 OR N PACKAGE
(TOP V1EW)
1CLR
10
1CLK
1PRE
10
10
GNO
Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent D-type
positive-edge-triggered flip-flops. A low level at
the Preset or Clear inputs sets or resets the
outputs regardless of the levels of the other
inputs. When Preset and Clear are inactive
(high). data at the D input meeting the setup time
requirements are transferred to the outputs on
the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold time interval. data at the D
input may be changed without affecting the
levels at the outputs.
The SN54HCT74 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCT74 is
characterized for operation from - 40°C to
85°C.
FUNCTION TABLE
INPUTS
CLR
CLK
H
H
L
X
X
X
t
L
L
H
H
H
I ulu13a:
013
a:
U
~~Z>N
3
1CLK
NC
1PRE
NC
1Q
2
1 2019
4
18
5
17
6
16
7
15
8
14
9 1011 12 13
IdOUldd
-ZZNN
(!)
NC - No internal connection
logic symbol*
lQ
'il
lCLK
0
X
X
X
Q
t
H
L
L
H
20
L
X
Qo
00
2CLR
H
L
L
lCLR
Ht
H
Ht
H
L
2CLK
t This configuration is nonstable; that is. it will not persist
when Preset or Clear returns to its inactive (high) level.
•
SN54HCT74 ... FK PACKAGE
(TOP VIEW)
OUTPUTS
PRE
L
H
H
H
VCC
2CLR
20
2CLK
2PRE
20
20
10
2PRE
2Q
*This symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEe Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
logic diagram. each flip-flop (positive logic)
PRE --------------------------~~-----.
CLK~:
0------1
ij
PRODUCTION DATA do.umonts .ontain informotio.
currant as of publication data. Products conform to
spacifications per the terms of TaXI. Instrumants
=::i;ai~:1~7i ~:~:~ti:r :'~O:::::::t:~~ not
Copyright @ 1982, Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
2-105
SN54HCT74, SN74HCT74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH CLEAR AND PRESET
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 5: FK .or J package . . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 5: D or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
~
s::
C')
These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under .. recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
otn
C
SN54HCT74
Vee Supply voltage
High-level input voltage
~
VIH
n'
Vil
VI
<
~
(I)
I Vee = 4.5 V to 5.5 V
I Vee = 4.5 V to 5.5 V
low-level input voltage
Input voltage
SN74HCT74
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
V
2
2
V
0
0.8
0
0.8
V
Vee
0
Vee
v
0
Vee
500
ns
85
°e
Vo
Output voltage
0
0
tt
Input transition (rise and fall) times
0
Vee
500
TA
Operating free-air temperature
55
125
0
-40
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
VI
VI
VI
VI
=
=
=
=
=
=
VIH or Vil. 10H
VIH or Vil. 10H
VIH or Vil. 10l
VIH or Vil. 10l
= -20 pA
= -4 mA
= 20 ~A
= 4 mA
II
VI
lee
VI
Vee or O. 10 = 0
One input at 0.5 V or 2.4 V •
.1lee*
ei
Vee or 0
Other inputs at 0 V or Vee
VCC
4.5 V
4.5 V
TA - 25°C
TYP MAX
MIN
4.4 4.499
3.98
4.30
4.5 V
4.5 V
0.001
0.1
0.17
5.5 V
±0.1
4.5 to
5.5 V
MIN
MAX
SN74HCT74
MIN
4.4
4.4
3.7
3.84
MAX
UNIT
V
0.26
0.1
0.4
0.33
±100
±1000
±1000
nA
4
80
40
pA
1.4
2.4
3
2.9
mA
3
10
10
10
pF
5.5 V
5.5 V
SN54HCT74
0.1
*This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or Vee.
2-106
TEXAS
~
INSTRUMENTS
POST OFFice BOX 656012 • DALLAS. TEXAS 76265
V
SN54HCT74, SN74HCT74
DUAL D·TYPE POSITIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH CLEAR AND PRESET
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
4.5 V
fclock Clock frequency
PRE or
a:R low
Pulse duration
tw
ClK high or low
Data
Setup time
tsu
before ClK!
PRE or
a:R inactive
Hold time data after ClK!
th
TA - 25°C
MIN
MAX
SN54HCT74
SN74HCT74
MIN
MAX
MIN
MAX
0
22
0
24
0
27
0
18
5.5 V
0
30
0
24
20
4.5 V
5.5 V
16
14
20
18
4.5 V
18
27
23
5.5 V
16
24
21
4.5 V
12
18
15
5.5 V
11
16
14
4.5 V
0
0
0
5.5 V
4.5 V
0
0
0
0
0
0
5.5 V
0
0
0
21
UNIT
MHz
,.
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 11
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
PRE or
a:R
OarO
tpd
ClK
tt
Oar 0
OarO
VCC
TA - 25°C
MIN
TVP MAX
SN54HCT74
MIN
MAX
SN74HCT74
MIN MAX
4.5 V
27
40
18
22
5.5 V
30
46
20
24
MHz
4.5 V
21
35
53
44
5.5 V
17
31
48
40
4.5 V
20
28
42
35
5.5 V
18
25
38
31
4.5 V
8
15
22
5.5 V
7
14
20
19
17
Power dissipation capacitance per flip-flop
No load, TA
~
UNIT
ns
ns
25°C
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS " ,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2·107
E
:::t:
(')
~
oen
c
<
n'
CD
CD
en
2-108
SN54HC75. SN74HC75
4·BIT BISTABLE LATCHES
02684, DECEM8ER 1982- REVISED SEPTEMBER 19B7
SN54HC75 . , . J PACKAGE
SN74HC75 ... 0 OR N PACKAGE
•
Complimentary Q and Q Outputs
•
Package Options Include Plastic "Small
Outline" Packages. Standard Plastic and
Ceramic 300·mil DIPs
•
(TOP VIEW)
10
10
20
Dependable Texas Instruments Quality and
Reliability
3C,4C
VCC
description
These latches are ideally suited for use as
temporary storage for binary information
between processing units and input/output or
indicator units. Information present at a data (D)
input is transferred to the Q output when the
enable (C) is high, and the Q output will follow
the data input as long as the enable remains high.
When the enable goes low, the information.
which was present at the data input at the time
the transition occurred. is retained at the Q
output until the enable is permitted to go high.
The SN54HC75 is characterized for operation
over the full military temperature range of
- 55
to 125
The SN74HC75 is
characterized for operation from -40°C to
85°C.
ac
ac.
10
20
20
1C,2C
GNO
II
3D
30
40
30
40 '-C:_~..... 40
logic symbol t
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
FUNCTION TABLE
(each lalchl
INPUTS
OUTPUT
0
L
H
C
H
Q
Q
L
H
H
H
L
X
L
00 00
logic diagram. each latch (positive logic)
D
Q
r----------I
C
1
~~II.4---4
I
COMMON TO ONE
I
IL
___________ J
OTHER LATCH
Copyright @ 1982. Texas Instruments Incorporated
PRDDUCTIDI DATA d..ullllIIa ...lli. ilfannotlaa
.ar...,1 I. of pIIbllClIiDft dill. Preducto ..lfol'll II
.p..Hleotio.. plr Ih. _
of Till. '"lIn/llllIIa
:~'!::~i~.i~:'':.'l~ =::~; ~Io=::,:~~ oot
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 865012 • DALLAS. TEXAS 76265
2·109
SN54HC75, SN14HC15
4-BIT BISTABLE LATCHES
absolute maximum ratings over operating free-air temperature range t
IJ
::J:
o
3:
Supply voltage. Vee ................................................ -0.5 V to 7 V
Input clamp current. IIK(VI < 0 or VI > Vee) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current. 10K(VO < 0 or Vo > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
eontinuous output current. 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
eontinuous current through Vee or GND pins .................................. ± 50 mA
Lead temperature 1.6 mm (1 '1 6 in) from case for 60 s: J package . . . . . . . . . . . . . . . . . . . . 300 0 e
Lead temperature 1.6 mm (1'16 in) from case for 10 s: 0 or N package ................ 260 0 e
Storage temperature range ............................... . . . . . . . . .. - 65 °e to 150 °e
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
contitions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
o(I)
cCD
<
(;'
CD
MIN
Vee
Supply voltage
Vee
Vee
Vee
Vee
Vee
Vee
VIH
High-level input voltage
Vil
low-level input voltage
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
TA
Operating
(I)
free~air
=
=
=
=
SN54HC75
NOM MAX
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-55
2 V
4.5 V
6 V
2 V
4.5 V
6 V
Vee - 2 V
Vee = 4.5 V
vee = 6 V
temperature
5
6
0.3
0.9
1.2
Vee
Vee
1000
500
400
125
MIN
SN74HC75
NOM MAX
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-40
5
6
UNIT
V
V
0.3
0.9
1.2
Vee
Vee
1000
500
400
85
V
V
V
ns
·e
electrical characteristics over recommended operating free-air temperature range lunless otherwise
noted)
PARAMETER
TEST CONDITIONS
Vcc
2V
VI = VIH or Vil. IOH = -20,.AVOH
vI = VIH or Vil. 10H = -4mA
-5.2 mA
VI
VIH or Vil. 10H
=
=
VI = VIH or Vil. IOl = 20,.AVOL
II
lee
Ci
2-110
VI = VIH or Vll, IOl = 4 rnA
VI = VIH or Vil. 10l = 5.2 rnA
VI = Vee orO
VI = VCC or 0, 10 = 0
4.5V
6V
4.5 V
6V
2V
4.5V
6V
4.5V
6V
6V
6V
2106 V
TA - 25"C
MIN
TYP MAX
1.9 1.998
4.4 4.499
5.9 5.999
3.98 4.30
5.48
6.80
0.1
0.002
0.001
0.1
0.001
0.1
0.17 0.26
0.15 0.26
:1:0.1 :1:100
4
3
10
TEXAS
~
INSTRUMENTS
POST OFFIC£ BOX 655012 • DALLAS. TEXAS 75265
SN54HC77
MIN MAX
1.9
4.4
5.9
3.7
SN74HC77
MIN MAX
1.9
4.4
5.9
3.84
5.34
5.2
0.1
0.1
0.1
0.4
0.4
:1:1000
80
10
UNIT
V
0.1
0.1
0.1
0.33
0.33
:1:1000
40
10
V
nA
,.ApF
SN54HC15. SN14HC15
4·BIT BISTABLE LATCHES
timing requirements over recommended operating free·air temperature range (unless otherwise
noted)
VCC
Pulse duration, C high
tw
Setup time, data before C I
tsu
Hold time, data after CI
th
TA - 25°C
MAX
SN54HC75
SN74HC75
MIN
120
MIN
100
MAX
2V
MIN
80
4.5 V
16
24
20
6V
2V
14
100
20
150
17
125
4.5 V
20
30
25
6V
17
26
21
2V
5
5
5
4.5 V
5
5
5
6V
5
5
5
UNIT
MAX
ns
PI
ns
ns
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
tpd
tpd
tt
FROM (INPUT)
D
C
TO (OUTPUT)
OorO
OorO
Any
VCC
TA - 25°C
MIN
SN54HC75
SN74HC75
MIN
MIN
MAX
180
2V
TVP
40
4.5 V
14
MAX
120
24
6V
11
20
36
31
MAX
150
30
ns
26
2V
44
130
195
165
4.5 V
15
26
39
33
6V
12
22
33
28
2V
4.5 V
38
75
15
110
8
22
95
19
6V
6
13
19
16
Power dissipation capacitance per latch
UNIT
ns
ns
No load, TA - 25°C
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
-II
INSTRUMENTS
POST OFFICE BOX 655012 • DAl.LAS. TEXAS 75265
2·111
::J:
(")
s:o
en
cCD
<
(;'
CD
en
2-112
SN54HC76. SN74HC76
DUAL J·K FLlp·FLOPS WITH CLEAR AND PRESET
02684, DECEMBER 1982-REVISED SEPTEMBER 1987
•
•
SN54HC76 , • , J PACKAGE
SN74HC76 ... 0 OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Standard Plastic and
Ceramic 300-mil DIPs
(TOP VIEW)
lElK
lPRE
lClR
lJ
VCC
2ClK
2PRE
2ClR
Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the Preset or Clear input sets or resets the
outputs regardless of the levels of the other
inputs, When Preset and Clear are inactive
(high), data at the J and K inputs meeting the
setup time requirements are transferred to the
outputs on the negative-going edge of the clock
pulse, Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse, Following the hold time interval,
data at the J and K inputs may be changed
without affecting the levels at the outputs,
These versatile flip-flops can also perform as
toggle flip-flops by tying J and K high,
FUNCTION TABLE
lK
10
10
GND
2K
20
20
2J
•
U)
For functionally and electrically identical
CD
parts in chip carrier packages, see
(,)
SN54HCl12.
'S;
CD
logic symbol t
Q
en
1PRE
1J
1CLK
1K
1ClR
1PRE
o
1Q
~
(,.)
1Q
J:
2J
(EACH FLIP-FLOP)
INPUTS
OUTPUTS
2CLK
2K
K
0
0
X
X
X
H
L
L
H
L
X
X
X
J
X
X
X
H~
H~
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
H
I
L
L
00
00
Pin numbers shown are for 0, J, and N packages.
H
H
I
H
L
H
L
H
H
I
L
H
L
H
H
H
I
H
H
TOGGLE
H
H
H
X
X
00
PRE
ClR
ClK
l
H
H
L
L
H
2CLR
00
:1:This configuration is nonstable; that is, it will not
persist when either Preset or elea r returns to its
inactive (high) level.
PRODUCTION DATA documlnts contlin inlormation
...._t IS 01 pvhlication data. Products ....form to
apacificatlons per thl tarms of Taxas Instruments
::==i;a{::I~.re ~:~:~i:r :.~o=::::.:~~
nDt
Copyright © 1982, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS. TeXAS 75265
2-113
SN54HC76,SN74HC76
DUAL J,K FLlp·FLOPS WITH CLEAR AND PRESET
logic diagram, each flip· flop (positive logic)
PRE----------------------------------.-----------,
:::c
o
3:
oen
cCD
CDR----------------------~~--------------------------~
absolute maximum ratings over operating free·air temperature range t
<
Supply voltage, Vee. . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: J package ................... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 1 50°C
C;'
CD
U)
t Stresses beyond those listed under "absolute maximum ratings" may calise permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recbmmended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
Vee Supply voltage
VIH High-level input voltage
Vee
Vee
Low-level input voltage
Vee
Vee
Vee
VIL
Vee
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
Vee
Vee
Vee
TA
2-114
Operating free-air temperature
=2 V
= 4.5 V
=6V
=2V
= 4.5 V
=6 V
=2V
= 4.5 V
=6V
SN54HC76
NOM MAX
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-55
TEXAS ~.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5
6
0.3
0.9
1.2
Vel;
Vee
1000
500
400
125
MIN
SN74HC76
NOM MAX
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-40
5
6
UNIT
V
V
0.3
0.9
1.2
V
Vee
Vee
V
V
1000
500
400
85
ns
°e
SN54HC76, SN74HC76
DUAL J·K FLlp·FLOPS WITH CLEAR AND PRESET
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
vCC
2V
1.9
1.9
1.9
4.4
6V
5.9
5.999
5.9
5.9
4.5 V
3.98
4.30
3.7
3.84
IOH
=
-20 p.A
4.5 V
V,
=
V,H or V,L.
10H
-4 mA
V, - V,H or V,L.
10H
=
=
6V
5.48
=
V,H or V,L.
10L
=
20 p.A
VOL
V,
V,
=
=
V,H or V,L.
V,H or V,L.
10L
10L
= 4 mA
= 5.2 mA
V, - VCC or 0
V,
=
VCC or O. 10
=0
MIN
MAX
4.4
VIH or VIL.
V,
SN74HC76
MIN
1.998
=
-5.2 mA
SN54HC76
4.4 4.499
VI
VOH
"
ICC
Ci
TA = 25°C
TYP MAX
MIN
5.2
5.80
MAX
UNIT
V
0.002
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
0.1
V
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
4
80
40
p.A
10
10
10
pF
6V
2 to 6 V
3
II
5.34
2V
timing requirements over recommended operating free-air temperature range (unless otherwise notedl
VCC
TA
MIN
2V
fclock
Clock frequency
PRE or CLR low
tw
Pulse duration
CLK high or low
Data
tsu
Setup time before CLK j
PRE or CLR
inactive
th
Hold time, after eLK!
=
25°C
MAX
SN54HC76
SN74HC76
MIN
MAX
MIN
MAX
4.2
0
5
0
6
0
4.5 V
0
31
0
21
0
25
6V
36
0
150
25
0
125
29
2V
0
100
4.5 V
20
30
6V
17
25
21
2V
80
120
100
4.5 V
16
24
20
14
20
17
2V
4.5 V
150
225
30
45
190
38
6V
25
2V
100
38
150
125
4.5 V
20
30
25
6V
17
0
0
0
25
21
6V
TEXAS
~
INSTRUMENTS
POST OFFICE Sox 655012 • DALLAS, TEXAS 75265
MHz
25
6V
2V
4.5 V
UNIT
32
0
0
0
0
0
0
ns
ns
ns
2-115
SN54HC76, SN74HC76
DUAL J·K FLlp·FLOPS WITH CLEAR AND PRESET
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL ... 50 pF (see Note 1)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
f max
tpd
tpd
::E:
PRE or ClR
ClK
QorQ
OorQ
o
3:
tt
oen
c
OorQ
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN
TYP MAX
n'
CD
5
41
21
25
50
25
29
9
31
36
155
250
190
31
47
39
15
26
40
33
70
145
220
180
19
29
44
36
16
25
37
31
38
75
110
95
8
15
22
19
6
13
19
16
No load, TA
tI)
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
= 25°C
UNIT
MHz
16
Power dissipation capacitance per flip-flop
TEXAS
MAX
65
NOTE 1: load circuit and voltage waveforms are shown in Section 1.
2-116
SN74HC76
MIN
MAX
4.2
6
CD
<
SN54HC76
MIN
ns
ns
ns
SN54HC77. SN74HC77
4·BIT BISTABLE LATCHES
02684, DECEMBER 1982 - REVISED SEPTEMBER 1987
•
Package Options Include Plastic "Small
Outline" Packages, Standard Plastic and
Ceramic 300-mil DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC71 ... J PACKAGE
SN74HC71 ... 0 OR N PACKAGE
(TOP VIEW)
description
These latches are ideally suited for use as
temporary storage for binary information
between processing units and input/output or
indicator units. Information present at a data (D)
input is transferred to the Q output when the
enable (C) is high, and the Q output will follow
the data input as long as the enable remains high.
When the enable goes low, the information,
which was present at the data input at the time
the transition occurred, is retained at the Q
output until the enable is permitted to go high.
Not available in chip carrier package
with JEDEC·Standard pinout. For chip
carrier information, contact the factory.
logic symbol f
10 (11
30
40
tThis symbol is in accordance with ANSI/IEEE Sid 91-19B4 and
IEC Publication 617-12.
OUTPUT
C
0
H
H
H
X
L
00
10
20
FUNCTION TABLE
(Each Latch)
0
L
H
fI
NC - No internal connection
The SN54HC77 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC77 is
characterized for operation from - 40°C to
85°C.
INPUTS
1Q
2Q
1C,2C
GNO
NC
3Q
4Q
10
20
3C,4C
VCC
30
40
NC
L
logic diagram, each latch (positive logic)
o
Q
r----------,
I
I
I
C
~~~--~
COMMON TO ONE
IL _________
OTHER LATCH
-'I
PRODUCTION DATA doca_ ....111. i.formation
..."a.t •• of publicltion data. Pradum ••nfor.. to
.,.clfocati••• por Iha II.....f T.... Inatrumlm
=~;a,~:,~li ~::I:~i:; :'la::~"'.:A:~~
nat
Copyright @ 1982. Texas Instruments Incorporated
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-117
SN54HC77, SN74HC77
4·BIT BISTABLE LATCHES
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee ........................... ; .................... -0.5 V to 7 V
Input clamp current, IIK(VI < 0 or VI > Vee) ................................. ± 20 mA
Output clamp current, 10K(VO < 0 or Vo > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: J package .......... '" ....... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ................ 260°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
•
::I:
o
3:
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommanded opersting
contitions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
oen
cCD
<
5'
MIN
Vee
Supply voltage
Vee - 2 v
Vee = 4.6 V
Vee = 6 V
Vee - 2 V
Vee = 4.5 V
Vee = 6 v
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and falll times
TA
Operating free-air temperature
CD
(I)
vee
Vee
Vee
=2V
= 4.5 V
=6 V
SN64HC77
NOM MAX
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-55
5
6
0.3
0.9
1.2
Vee
Vee
1000
600
400
125
MIN
SN74HC77
NOM MAX
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-40
5
6
UNIT
V
V
0.3
0.9
1.2
Vee
Vee
1000
500
400
85
V
V
V
ns
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONOITIONS
Vec
2V
VI
= VIH or VIL. 10H =
-20 "A
VOH
VI - VIH or VIL. 10H VI - VIH or VIL. 10H VI
= VIH or VIL.
10L
4mA
-5.2 mA
= 20,.A
VOL
II
ICC
Ci
2-118
VI = VIH or VIL. 10L = 4 rnA
VI = VIH or VIL. 10L = 5.2 rnA
VI - Vec or 0
VI - Vec or O. 10 = 0
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 to 6 V
TA - 26·C
TYP MAX
MIN
1.9 1.998
4.4 4.499
5.9 5.999
4.30
3.98
5.48
5.80
0.002
0.1
0.1
0.001
0.001
0.1
0.17 0.26
0.15 0.26
±0.1 ±100
4
10
3
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN64HC77
MIN MAX
1.9
4.4
5.9
3.7
5.2
SN74HC77
MIN MAX
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.4
0.4
±1000
80
10
UNIT
V
0.1
0.1
0.1
0.33
0.33
±1000
40
10
V
nA
,.A
pF
SN54HC77, SN74HC77
4-BI1 BISTABLE LATCHES
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
vcc
tw
Pulse duration, C high
tsu
Setup time, data before C I
th
Hold time, data after CI
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5V
6V
TA - 25"C
MAX
MIN
80
16
14
100
20
17
5
5
5
SN54HC77
SN74HC77
MIN
120
24
20
150
MIN MAX
100
20
17
125
25
21
5
5
5
MAX
30
26
5
5
5
UNIT
ns
fI
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 11
PARAMETER
FROM (lNPUTI
TO (OUTPUTI
tpd
0
Q
tpd
C
Q
tt
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5V
6V
TA - 25"C
MIN TVP MAX
40
120
12
24
10
20
45
130
14
26
11
22
75
28
15
8
13
6
SN54HC77
SN74HC77
MIN
MIN
MAX
180
36
31
195
39
33
110
22
19
MAX
150
30
26
165
33
28
95
19
16
UNIT
ns
ns
ns
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
Power dissipation capacitance per latch
No load,
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
TA=25"C
16 pF typ
2-119
::J:
o
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s.
CD
(')
CD
o
2-120
SN54HC78. SN74HC78
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH PRESET. COMMON CLEAR. AND COMMON CLOCK
02684, DECEMBER 1982-REVISED SEPTEMBER 19B7
•
SN54HC78 ... J PACKAGE
SN74HC78 ... D OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Standard Plastic and
Ceramic 300-mil DIPs
(TOP VIEW)
ClK
1PRE
1J
VCC
ClR
2PRE
2K
Dependable Texas Instruments Quality and
Reliability
•
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the Preset or Clear inputs sets or resets the
outputs regardless of the levels of the other
inputs. When the Preset and Clear are inactive
(high). data at the J and K inputs meeting the
setup time requirements are transferred to the
outputs on the negative-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold time interval.
data at the J and K inputs may be changed
without affecting the levels at the outputs.
These versatile flip-flops can perform as toggle
flip-flops by tying J and K high.
INPUTS
OUTPUTS
J
K
a
H
X
X
X
H
L
L
X
X
X
L
H
L
H
a
L
L
X
X
X
H~
H~
H
H
H
H
L
H
L
Go
00
L
H
L
H
H
I
I
I
I
H
L
H
L
H
H
H
H
H
U)
CD
CJ
logic symbol t
'S:
CD
Q
en
o
:E
10
o
iii
:t:
20
2ii
ClK
ClR
II
For functionally and electrically identical
parts in chip carrier packages, see
SN54HCl14.
FUNCTION TABLE
PRE
1K
10
10
GND
2J
20
20
H
H
TOGGLE
X
X
ao
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
00
iThis configuration is nonstable; that is, it will not
persist when either Preset or Clear returns to its
inactive (high) level.
logic diagram. each flip-flop (positive logic)
PRE----------------------------------.---------,
J ------Ir--.....
Q
K _-I--""r--.....
r----------,
I
ClK~C
~
I
I
I
CLR
.:
I
L:.--C
I
PRODUCTION DATA documonts ..ntain informltion
.urra.t as of publi.atio. data. Products .onform to
.,..,icltioRI par t118 tarlll af leus Instruments
=i~8i~:~'li ~r::::; :.;a:::::~:'.." not
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1982. Texas Instruments Incorporated
2-121
SN54HC78, SN74HC78
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLlp·FLOPS
WITH PRESET, COMMON CLEAR, AND COMMON CLOCK
absolute maximum ratings over operating free· air temperature range t
11
::t
Supply voltage. Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current. 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current. 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current. 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1.6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300°C
Lead temperature 1.6 mm (1/16 in) from case for 10 s: 0 or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
o
s:o
en
cCD
<
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recommended operating conditions
SN54HC78
NOM MAX
5
2
6
MIN
Vee Supply voltage
VIH High-level input voltage
Vee
Vee
Low-level input voltage
Vee
Vee
Vee
CD
en
VIL
Vee
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
Vee
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
=
=
=
1.5
3.15
4.2
0
0
0
0
0
2 V
4.5 V
Vee
Vee
1000
500
400
0
0
-55
6 V
Operating free-air temperature
TA
0.3
0.9
1.2
0
125
SN74HC78
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0
0
0
0
0
0
0
0
-40
UNIT
V
V
0.9
1.2
V
Vee
Vee
1000
500
400
V
V
85
n.
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
=
VI
VI
= VIH
= VIH
VI
=
VIH or VIL.
=
IOH
VCC
-20/LA
VOH
or VIL.
or VIL.
VIH or VIL.
IOH - -4 rnA
IOH = -5.2 rnA
4.5 V
6V
= 20/LA
2V
4.5 V
IOL
VOL
II
lee
ei
2-122
VI = VIH or VIL.
VI - VIH or VIL.
VI = Vee orO
VI
=
Vee or 0.10
2V
4.5 V
6V
10L = 4 rnA
IOL - 5.2 rnA
=0
TA = 25°C
MIN
TYP MAX
SN54HC78
MIN MAX
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.48
5.80
0.002
1.9
4.4
1.9
4.4
5.9
3.7
5.2
5.9
3.84
5.34
6V
4.5V
6V
6V
0.001
0.001
0.17
0.15
±0.1
6V
2 to 6 V
TEXAS
SN74HC78
MIN MAX
V
0.1
0.1
0.1
0.1
0.1
0.26
0.26
0.1
0.1
0.4
0.4
0.1
0.1
0.33
±100
4
±1000
80
0.33
±1000
40
10
10
10
3
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
UNIT
V
nA
/LA
pF
SN54HC78, SN74HC78
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH PRESET, COMMON CLEAR, AND COMMON CLOCK
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vee
fclock
Clock frequency
ClR or PRE low
Pulse duration
tw
ClK high or low
tsu
Setup time
ern or PRE
before ClKI
inactive or data
Hold time, data after ClKI
th
TA - 2SOC
MAX
MIN
SNS4HC78
SN74HC78
MIN
MAX
MIN
MAX
2V
0
6
0
4.2
0
5
4.5 V
0
31
0
21
0
25
6V
0
36
0
25
0
29
2V
80
119
101
4.5 V
16
24
20
6V
14
20
17
2V
80
119
101
4.5 V
16
24
20
6V
14
20
2V
4.5 V
100
150
25
35
6V
20
30
0
17
125
30
25
0
0
0
2V
0
4.5 V
0
0
6V
0
0
UNIT
MHz
ns
II
ns
n.
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
TA = 2SoC
FROM
TO
(INPUT)
(OUTPUT)
f max
tpd
tpd
tt
-PRE or -ClR
ClK
-
QorQ
-
Qor Q
Vee
MIN
TYP
2V
6
9
4.5 V
31
6V
36
MAX
SNS4HC78
SN74HC78
MIN
MIN
MAX
4.2
5
50
21
25
60
25
29
MAX
MHz
2V
78
155
250
4.5 V
16
31
47
39
6V
13
26
40
32
160
194
2V
63
126
185
4.5 V
13
25
37
32
6V
11
21
32
27
95
2V
38
75
110
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance per flip-flop
UNIT
ns
ns
ns
No load, TA = 25°C
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS .",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-123
::t:
("')
:s:o
en
o
(1)
<
0'
(1)
til
2-124
SN54HC85A, SN74HC85A
4·81T MAGNITUDE COMPARATORS
02684, DECEMBER 1982-REVISEO JUNE 1989
•
Package Options Include Ceramic Chip
Carriers. and Standard Plastic and Ceramic
300·mil DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC85A ••• J PACKAGE
SN74HC85A .•• N PACKAGE
(TOPVlEWI
Vce
03
P3
o
INPUTS r <
P=O
02
P2
Pl
P>O
description
These four-bit magnitude comparators perform
comparison of straight binary and straight BCD
(8-4-2-1) codes. Three fully decoded decisions
about two 4-bit words (P, Q) are made and are
externally available at three outputs. These
devices are fully expandable to any number of
bits without external gates. Words of greater
length may be compared by connecting
comparators in cascade. The P>Q. P Q.
P < Q, and P = inputs of the next stage handling
more significant bits. The stage handling the
least significant bits must have a high-level
voltage applied to the P = Q input. The cascading
path of the 'HC85A is implemented with only a
two-gate-Ievel delay to reduce overall
comparison times for long words.
The SN54HC85A is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC85A is
characterized for operation from - 40°C to
85°C.
O
OUTPUTS f >
P=O
01
PO
00
PO
4
5
17
NC
6
16
{P>O
OUTPUTS P=O
15
14
8
9 1011 1213
I-OOUOO
::JVZZOc.
!=c.(.!J
::J
o
NC-No internal connection
logic symbol:!:
PO
Pl
P2
P3
po
00
01
02
03
(10)
(12)
(13)
(15)
(2)
(3)
(4)
(9)
(11)
COMP
}
<
p
:}
p>o
(7)
(6)
(5)
po
*This symbol is in accordance with ANSI/IEEE SId 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for J and N packages.
PRODUCTION DATA documents contain information
current as at public~iDn date. Products conform to
specifications par the terms of Tua. Instruments
:'~:~i~ai:~1~ ~t;:~:r :uo:::~~~~ IIO!
Copyright @ 1989. Texas Instrumems Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-125
SN54HC85A, SN74HC85A
4·81T MAGNITUDE COMPARATORS
logic diagram (positive logic)
::::c
o
:s::
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o
CD
<
c:r
CD
(I)
pQJ(4~)
____________________L-~----~
Pin numbers shown are for J and N packages.
2-126
TEXAS •
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75265
SN54HC85A. SN74HC85A
4-81T MAGNITUDE COMPARATORS
FUNCTION TABLE
P3. Q3
P3>03
P3<03
P3=03
P3=03
P3=03
P3=03
P3=03
P3=03
P3=03
P3=03
P3=03
P3=03
P3=03
COMPARING
INPUTS
P2. Q2 PI. 01
X
X
X
X
P2>02
X
P2<02
X
P2=02 Pl>OI
P2=02 PlOO
PO <00
PO=OO
PO=OO
PO=OO
PO=OO
PO =00
CASCADING
INPUTS
P>O
PO
H
L
H
L
H
L
H
L
H
L
L
L
H
P Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ............................. ± 20 rnA
Continuous output current. 10 (Vo = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 rnA
Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: N package ................... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Vee SupplV voltage
VIH High-level input voltage
VIL Low-level input voltage
Vee
Vee
Vee
Vee
Vee
=
=
=
=
=
2V
4.5 V
6V
2V
4.5 V
Vee = 6 V
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
TA
Operating free-air temperature
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
SN54HCS5A
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0
0.9
0
1.2
0
0
Vee
0
Vee
1000
0
500
0
0
400
-55
125
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN74HC85A
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0
0.3
0
0.9
0
1.2
0
Vee
0
Vee
1000
0
0
500
400
0
-40
85
UNIT
V
V
V
V
V
ns
·e
2-127
SN54HC85A, SN74HC85A
4-81T MAGNITUDE COMPARATORS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
VI = VIH or Vll,
IOH = -20,..A
VI = VIH or Vll,
VI - VIH or Vll,
10H = -4 mA
10H = -5.2 mA
VI = VIH or Vll,
10l = 20 p.A,
VOH
•
::c
(')
3:
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o
~
C:;'
(I)
en
II
ICC
Ci
6V
4.5 V
6V
2V
4.4 4.499
5.9 5.999
3.98
4.30
5.48
4.5V
6V
4,5 V
VOL
VI = VIH or Vll,
VI = VIH or Vll,
VI = VCC or 0
2V
4.5 V
TA = 25°C
MIN
TYP MAX
1.9 1.998
10l = 4 mA
10l - 5.2 rnA
6V
6V
5.80
0.002
0.001
0.1
0.1
0.001
0.17
0.15
0.1
0.26
0.26
±0.1
±100
3
8
10
6V
2 to 6 V
VI = VCC or 0, 10 = 0
SN54HC85A
MIN MAX
SN74HC85A
MIN MAX
1.9
1.9
4.4
5.9
3.7
5.2
4.4
5.9
3.84
5.34
V
0.1
0.1
0,1
0.1
0.4
0.4
0.33
0.33
±1000
0.1
0.1
±1000
160
80
10
UNIT
10
V
nA
,..A
pF
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
tpd
tpd
FROM
(INPUT)
TO
(OUTPUT)
VCC
AnyPorQ
P>Q
or
2V
4.5 V
PQ
P>Q
or
P=Q
P Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current. 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current. 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1.6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1.6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range .....•................................... - 65°C to 150°C
tn
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute~maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC86
NOM
MAX
2
5
6
Vee Supply voltage
Vee
VIH High-level input voltage
Vee
Vee
Vee
VIL Low-level input voltage
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
SN74HC86
MIN
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
UNIT
V
V
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
V
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
Vee
1000
0
Vee
1000
V
0
500
0
500
ns
0
400
0
400
-55
125
-40
85
Vee
tt
Input transition (rise and fall) times
Vee
Vee
TA
2-130
=2V
= 4.5 V
=6V
0
Operating free-air temperature
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
0
°e
SN54HC86, SN74HC86
QUADRUPLE 2-INPUT EXCLUSIVE·OR GATES
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
(Tatem·pale
autputsl
TEST CONDITIONS
vCC
VI = VIH or VIL.
10H = -20 1'A
VI = VIH or VIL.
10H = -4 rnA
VI = VIH or VIL.
10H = -5.2 rnA
II
lee
ej
2V
4.5 V
BV
4.5V
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.48
VI = VIH or VIL.
10L = 20,.A
BV
2V
4.5 V
VI = VIH or VIL.
VI = VIH or VIL.
10L = 4 rnA
10L = 5.2 rnA
BV
4.5 V
6V
VOL
BV
BV
2 to B V
VI - Vee or 0
VI = Vee or O. 10 = 0
TA - 25°C
TYP MAX
MIN
SN54HC86
MIN MAX
1.9
4.4
5.9
3.7
SN74HC86
MIN MAX
1.9
4.4
5.9
3.84
5.2
UNIT
V
5.80
0.002
0.001
0.1
0.1
0.1
0.1
5.34
0.1
0.1
0.001
0.17
0.15
±0.1
0.1
0.2B
0.26
±100
0.1
0.4
0.4
±1000
0.1
0.33
0.33
±1000
nA
"S;
3
2
10
40
10
20
10
I'A
pF
C
V
II)
CD
U
CD
U)
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT!
TO
(OUTPUT!
vCC
2V
Ipd
II
A or B
Y
Y
4.5 V
BV
2V
4.5 V
TA - 25°C
MIN
TYP MAX
40
100
12
10
28
BV
8
B
20
17
75
15
13
SN54HC86
MIN
MAX
150
SN74HC86
MIN MAX
125
30
25
110
22
25
21
95
19
19
lB
No load. TA = 25°e
Power dissipation capacitance per gate
UNIT
0
:E
o
J:
no
no
35 pF typ
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALlA$,.TEXA5 75265
2-131
:I:
(")
s:
oen
o
(1)
<
C:;"
(1)
en
2-132
SN54HC107, SN74HC107
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLlP·FLOPS WITH CLEAR
02684. DECEM8ER 1982 - REVISED JUNE 1989
•
•
SN54HC107 ... J PACKAGE
SN74HC107 ... 0 OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
(TOP VIEWI
Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the CLR input resets the outputs regardless of
the levels of the other inputs. When CLR is
inactive (high!, data at the J and K inputs
meeting the setup time requirements are
transferred to the outputs on the negative-going
edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to
the rise time of the clock pulse. Following the
hold time interval, data at the J and K inputs may
be changed without affecting the levels at the
outputs. These versatile flip-flops can perform
as toggle flip-flops by tying J and K high.
1J
vcc
'-5
1CLR
1Q
1CLK
1K
2K
2Q
2CLR
i5
2CLK
GND
2J
SN54HC107 ... FK PACKAGE
CI)
(TOP VIEWI
Q)
CJ
Ulct:d
"S;
10 -, U U
~Z>~
3
2
Q)
c
en
1 2019
10
4
18
NC
5
17
1K
6
16
o
:E
15
NC
()
J:
14
8
9 1011 12 13
The SN54HC1 07 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC107 is
characterized for operation from - 40°C to
85°C.
10OU-''''
NZZN.....l
l?
U
N
NC-No internal connection
logic symbols t
FUNCTION TABLE
INPUTS
OUTPUT
ClR
ClK
J
K
Q
l
X
I
I
X
X
l
H
L
L
QO
00
H
L
H
L
I
L
L
H
I
H
X
H
H
X
H
H
H
H
H
H
Q
TOGGLE
QO
00
tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, 1Jnd N packages.
PRODUCTION DATA do.umenu .onuin informatiDn
current as of publication data. Products conform to
spacifications per the tarms af Taxas Instruments
:'~=~i~at::I:r.; =~:i:r fI~O:::::~::'~ nDt
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1989, Texas Instruments Incorporated
2-133
SN54HC107. SN74HC107
DUAL J-K NEGATIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH CLEAR
logic diagram, each flip-flop (positive logic)
Q
K-oHtr'-..
•
:t
CLK~:
s:o
crR-----------q
o
(I)
c
CD
absolute maximum ratings over operating free-air temperature range t
<
(;'
Supply voltage, VCC ............................................... , -0.5 V to 7 V
Input clamp current, IIK(VI < 0 or VI > VCC} ................................. ± 20 mA
Output clamp current, 10K(VO < 0 or Vo > Vcc} .............................. ±20 mA
Continuous output current, 10 (Vo = 0 to Vcc) ................................ ±25 mA
Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ..•............ 300 0 C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ................ 260 0 C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 DC to 150 DC
CD
U)
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
contitlons" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN&4HC107
MIN NOM MAX
vee
VIH
VIL
Supply voltage
High-level input voltage
Low-lavel input voltage
2
vee
vee
vee
Vee
Vee
=
=
=
2V
4.5 V
6V
2V
4.5 V
vee = 6 V
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fell) times
Vee = 2 V
vee = 4.5 V
Vee = 6 V
TA
2-134
Operating free-air temperature
TEXAS
5
6
1.6
3.15
4.2
0
0
0
0
0
0
0
0
-55
..If
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
0.3
0.9
1.2
Vee
Vee
1000
500
400
125
sN74HC107
MIN NOM MAX
2
1.5
3.16
4.2
0
0
0
0
0
0
0
0
-40
6
6
UNIT
V
V
0.3
0.9
1.2
V
Vee
Vee
V
V
1000
500
ns
400
86
·e
SN54HC107, SN74HC107
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLIp· FLOPS WITH CLEAR
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
=
VIH or VIL, 10H
=
vCC
-20
~A
VOH
VI
VI
VI
=
=
=
VIH or VIL. 10H
VIH or VIL, 10H
VIH or VIL. 10L
=
=
=
-4 rnA
- 5.2 rnA
20 ~A
VOL
VI - VIH or VIL, 10L - 4 rnA
VI - VIH or VIL. 10L - 5.2 rnA
=
II
VI
ICC
VI - VCC or 0, 10 - 0
VCC or 0
TA - 25°C
MIN
TYP MAX
SN74HC107
MIN MAX
2V
1.9 1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
4.5 V
5.9 5.999
5.9
3.98
5.9
3.84
6V
5.48
4.30
3.7
5.80
5.2
UNIT
V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1 ±100
±1000
±1000
nA
6V
4
80
40
pA
10
10
10
pF
3
II
5.34
2V
2 to 6 V
Cj
SN54HC107
MIN MAX
V
U)
CD
(,)
oS
CD
Q
f/)
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
tw
Pulse duration
CLK high or low
Data (J. KI
tsu
SN74HC107
MIN
MAX
MIN
MAX
6
0
4.2
0
5
0
4.5 V
0
31
0
21
0
25
6V
0
100
36
0
150
25
0
29
30
6V
17
25
21
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
100
150
125
25
20
30
6V
17
25
21
before eLKl
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
0
0
0
4.5 V
0
0
0
6V
0
0
0
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
:E
(J
:::a::
MHz
25
4.5 V
Hold time. data after CLK 1
UNIT
o
125
20
Setup time
CLR inactive
th
SN54HC107
2V
2V
4.5 V
CLR low
TA - 25°C
MIN
MAX
ns
ns
ns
2-135
SN54HC107, SN74HC107
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLlP·FLOPS WITH CLEAR
switching characteristics over recommended operating free· air temperature range (unless otherwise·
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
vCC
2V
4.5 V
6V
2V
4.5 v
6V
2V
4.5 V
6V
2V
4.5 V
6V
f max
::J:
Ipd
ClR
aorO
tpd
ClK
a orO
(')
3:
It
C
Cpd
oen
CD
<
c=r
a orO
TA - 25°C
MIN
TYP
6
31
36
9
45
53
126
25
21
100
20
17
38
8
6
MAX
155
31
26
125
25
21
75
15
13
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
CD
til
2·136
MIN
MAX
4.2
21
25
No load, TA
Power dissipation capacitance per flip-flop
SN54HC107
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74HC107
MIN
MAX
5
25
29
MHz
195
39
32
160
32
27
95
19
16
235
47
40
185
37
32
110
22
19
= 25°C
UNIT
I
ns
ns
ns
35 pF typ
SN54HC109, SN74HC109
DUAL J-j( POSITIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH CLEAR AND PRESET
02684. DECEMBER 1982-REVISED JUNE 1989
•
•
Package Options Include Plastic "Small
Outline" Packages, Ceremic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
SN54HC109 •.• J PACKAGE
SN74HC109 •.. D OR N PACKAGE
(TOP VIEW)
lClR
lJ
lK
lClK
lPRE
10
1'0
GND
Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent J-j(
negative-edge-triggered flip-flops. A low level at
the Preset or clear inputs sets or resets the
outputs regardless of the levels of the other
inputs. When Preset and Clear are inactive
(high), data at the J and j( inputs meeting the
setup time requirements are transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold time interval,
data at the J and K inputs may be changed
without affecting the levels at the outputs.
These versatile flip-flops can perform as toggle
flip-flops by grounding j( and tying J high. They
also can perform as D-type flip-flops if J and j(
are tied together.
The SN54HC 109 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC109 is
characterized for operation from - 40°C to
85°C.
2ClR
2J
2K
2ClK
2PRE
20
2'0
II
en
SN54HC109 ... FK PACKAGE
CD
U
ITOP VIEW)
':;
CD
C
3
2
CI)
1 20 19
o
4
:E
17
5
6
o
::E:
7
8
14
9 1011 12 13
100 UIO 0
_ZZNN
Cl
NC-No internal connection
logic symbol t
FUNCTION TABLE
OUTPUTS
INPUTS
11
PRE
ClR
ClK
J
K
0
L
H
X
X
X
H
L
H
L
X
X
X
X
L
Ht
H
Ht
H
L
L
X
X
H
H
t
L
L
L
H
H
H
L
TOGGLE
H
H
t
t
L
H
00
H
H
H
H
H
L
H
H
t
L
X
X
00
110
110
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEe Publication 617-12.
Pin numbers shown are for D. J. and N packages.
+This configuration is nonstable; that is. it will not
persist when Preset or Clear return to their inactive
(high) level.
PRODUCTION DATA documonts contain information
currant as of publication date. Products conform to
specifications par the terms of Texas Instruments
=~~ir,8{::I~t,Ta
=:\::i:; :.~o::;::::.::s nat
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
Copyright @ 1989. Texas Instruments Incorporated
2-137
SN54HC109, SN74HC109
DUAL J.j( POSITIVE·EDGE·TRIGGERED
FLlP·FLOPS WITH CLEAR AND PRESET
logic diagram. each flip·flop (positive logic)
~~~==========================~=======4----~
Q
i<--+--L.-I
•
::::t
(1
!:
CLR------------------------------__----------------------------------~
oC/) absolute
maximum ratings over operating free·air temperature range t
c
<
n'
Supply voltage. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for '0 s: 0 or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
(1)
(1)
(I)
t Stresses beyond those listed under "absolute maximum ratings"
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC109
MIN NOM MAX
Vee Supply voltage
VIH High-level input voltage
Vee
Vee
low-level input voltage
Vee
Vee
Vee
VIL
Vee
Input voltage
VI
Vo
Output voltage
tt
Input transition (rise and falll times
Vee
Vee
Vee
TA
2-138
=2V
= 4.5 V
= !i V
=2V
= 4.5 V
=6V
Operating free-air temperature
=2 V
= 4.5 V
=6V
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-55
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5
6
0.3
0.9
1.2
Vee
Vee
1000
500
400
125
SN74HC109
MIN NOM MAX
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-40
5
6
UNIT
V
V
0.3
0.9
1.2
V
Vee
Vee
V
V
1000
500
400
85
ns
°e
SN54HC109, SN74HC109
DUAL J-i( PDSITIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH CLEAR AND PRESET
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TA ; 25°C
TEST CONDITIONS
vCC
2V
VI ; VIH or Vll,
IOH = -20
~A
VI ; VIH or Vll,
VI
VI
=
=
VIH or Vll,
VIH or Vll,
10H; -4 mA
10H = -5.2 mA
10l
= 20 ~A
VOL
II
ICC
CI
4.5 V
6V
VOH
VI ; VIH or Vll,
10l ; 4 mA
VI ; VIH or Vll,
VI; VCC or 0
10l
VI
=
VCC or 0, 10
=
5.2 mA
=0
SN54HC109
TYP
1.9
1.998
1.9
1.9
4.4 4.499
4.4
4.4
5.999
5.9
3.7
5.9
3.84
4.5 V
5.9
3.98
6V
5.48
MAX
4.30
MIN
MAX
SN74HC109
MIN
5.2
5.80
MIN
MAX
UNIT
V
fI
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
en
6V
0.15
0.26
0.4
0.33
(J
6V
±0.1
±100
±1000
±1000
nA
4
80
40
~
10
10
10
pF
6V
2 to 6 V
3
V
G)
'S:
G)
c
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
!clock
Clock frequency
PRE or ClR low
tw
Pulse duration
ClK high or low
Data (J, K)
Setup time
tsu
before ClKI
PRE or ClR
inactive
th
Hold time, data after ClK!
TA - 25°C
MIN
MAX
SN54HC109
SN74HC109
MIN
MAX
MIN
MAX
2V
0
6
0
4.2
0
5
4.5 V
0
31
0
21
0
25
6V
0
36
0
25
0
29
2V
100
150
125
4.5 V
20
30
25
BV
17
25
21
2V
80
120
100
4.5 V
1B
24
20
BV
14
20
17
2V
4.5 V
100
150
125
20
30
25
BV
17
25
21
2V
25
40
30
4.5 V
5
4
0
0
0
8
B
BV
2V
4.5 V
BV
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
7
5
0
0
0
0
0
0
UNIT
en
:E
o
(J
J:
MHz
ns
ns
n.
2-139
SN54HC109, SN74HC109
DUAL J.i{ POSITIVE·EDGE·TRIGGERED
FLlP·FLOPS WITH CLEAR AND PRESET
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL .. 50 pF (see Note 1)
PARAMETER
FROM
IINPUT}
TO
(OUTPUT)
f max
tpd
PRE or ClR
Q or 0:
::z::
tpd
ClK
Qor Q
s:o
tt
o
ur
c
<
-
Qor Q
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN
TYP MAX
10
6
31
50
36
60
60
230
15
46
12
39
50
175
15
35
12
30
28
75
8
15
13
6
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
U)
2·140
TEXAS
SN54HC109
MIN MAX
4.2
21
25
345
69
59
250
50
42
110
22
19
No load, TA
Power dissipation capacitance per flip-flop
CD
Cr
CD
-
vCC
~
INsrRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 752&5
~
25°C
SN74HC109
MIN MAX
5
25
29
290
58
49
220
44
37
95
19
16
UNIT
MHz
no
no
no
SN54HC112. SN74HC112
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLlp·FLOPS
WITH CLEAR AND PRESET
02684, DECEMBER 1982-REVISED SEPTEMBER 1987
•
•
SN54HC112 .•. J PACKAGE
SN74HC112 ... 0 OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
(TOP VIEW)
VCC
1ClR
2ClR
2ClK
2K
2J
2PRE
20
1ClK
1K
1J
1PRE
10
10
20
Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the Preset or Clear inputs sets or resets the
outputs regard less of the levels of the other
inputs. When Preset and Clear are inactive
(high). data at the J and K inputs meeting the
setup time requirements are transferred to the
outputs on the negative-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold time interval.
data at the J and K inputs may be changed
without affecting the levels at the outputs.
These versatile flip-flops can perform as toggle
flip-flops by tying J and K high.
GND
SN54HC112 ... FK PACKAGE
(TOP VIEWI
3
1J
2
1 20 19
4
5
17
2ClR
2ClK
6
16
NC
8
14
2K
2J
9 1011 1213
The SN54HC112 is characterized for operation
over the full military temperature range of
-55°C to 125°C, The SN74HC112 is
characterized for operation from - 40°C to
85°C,
NC - No internal connection
logic symbol t
FUNCTION TABLE
INPUTS
OUTPUTS
ClK
J
K
Q
L
ClR
H
X
X
X
H
L
H
l
X
X
X
l
H
PRE
Q
L
L
X
X
X
H~
H~
H
H
l
00
H
H
L
L
00
H
I
I
H
L
H
H
I
L
H
L
H
H
H
I
H
H
TOGGLE
H
H
H
X
X
00
00
~This configuration is nonstable; that is, it will not
perSist when either Preset or elea r returns to its
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
inactive (high) level.
PRODUCTION DATA do.umlnts .ont.in I.farmllio.
currant .s 01 publi.otIon dlla. Preducts colli... 10
spo.ifi.ations por tho terms 01 TOlIIIs Instrumlllll
standard wlrranty. Production p;rDc••sinl dall lot
.......rlly in.lu'. tolling 01 .11 plomllon.
Copyright @) 1982. Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-141
SN54HC112, SN74HC112
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLIP· FLOPS
WITH CLEAR AND PRESET
logic diagram, each flip·flop (positive logic)
~-----------------------------.------~
Q
K
CLR--------------------~~------------------------~
2-142
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC112, SN74HC112
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLlp·FLOPS
WITH CLEAR AND PRESET
absolute maximum ratings over operating frea·air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... - 65 DC to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
CD
'S;
SN54HC112
MIN
2
Vee Supply voltage
VIH High-level input voltage
Vee
Vee
Vee
VIL Low-level input voltage
Vee
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
=2 V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
SN74HC112
MAX
6
0.3
0.9
0
0
0
NOM
MAX
5
6
CD
UNIT
Q
V
U)
o
V
::E
(J
0
0.3
0.9
1.2
V
Vee
0
0
0
Vee
Vee
1000
0
0
Vee
1000
V
V
500
400
125
0
0
-40
500
400
ns
85
·e
1.2
0
0
0
0
-55
=6 V
MIN
2
1.5
3.15
4.2
0
Operating free-air temperature
TA
NOM
5
1.5
3.15
4.2
Vee - 2 V
Vee = 4.5 V
Vee
(I)
U
racommended operating conditions
Vee
Vee
II
%
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONOITIONS
VCC
2V
VI
= VIH or VIL.
10H
= -20 ~A
VOH
VI = VIH or VIL.
VI - VIH or VIL.
VI
= VIH or VIL.
10H = -4 mA
10H - -5.2 mA
IOL
II
lee
ei
6V
2V
4.5 V
= 20 ~
VOL
VI
VI
VI
VI
4.5 V
6V
4.5 V
= VIH or VIL. IOL = 4 mA
= VIH or VIL. IOL = 5.2 rnA
= Vee orO
= Vee or 0.10 - 0
,
6V
4.5 V
6V
6V
6V
2 to 6 V
TA = 25·C
MIN
TYP MAX
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.48
5.80
SN54HCl12
MIN
1.9
MAX
4.4
5.9
3.7
SN74HCl12
MIN
1.9
4.4
MAX
5.9
3.84
5.2
V
5.34
0.1
0.1
0.1
o.i
0.1
0.1
0.1
0.1
0.33
0.33
0.002
0.001
0.001
0.17
0.15
±0.1
0.1
0.26
0.26
±100
3
4
10
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
UNIT
0.4
0.4
±1000
80
10
V
±1000
nA
40
~A
10
pF
2-143
SN54HC112, SN74HC112
DUAL·J·K NEGATIVE·EDGE·TRIGGERED FLlP·FLOPS
WITH CLEAR AND PRESET
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
VCC
fclock
2V
4.5 V
Clock frequency
6V
2V
PRE or em low
4.5 V
Pulse duration
tw
ClK high or low
:::t
(')
s:o
Data (J, K)
Setup time
before ClKI
tsu
en
c
~
n'
CD
en
PRE
or
CCR
inactive
0
0
0
100
SN54HC112
MIN MAX
5
25
29
0
0
0
150
20
17
100
4.5V
20
6V
2V
4.5 V
6V
17
100
20
17
100
25
150
30
20
17
30
25
0
0
0
0
0
2V
4.5 V
3.4
17
20
30
6V
2V
6V
2V
4.5 V
6V
Hold time, data after ClK I
th
TA - 25°C
MAX
MIN
SN74HC112
MIN MAX
0
0
0
125
4
20
ns
125
25
ns
21
125
25
21
25
150
0
MHz
24
25
21
25
150
30
UNIT
ns
125
25
21
ns
0
0
0
ns
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
vCC
2V
f max
tpd
-PRE or -ClR
Qor Q
tpd
ClK
tt
-
4.5 V
6V
2V
TA = 25°C
MIN
TYP MAX
5
25
29
10
50
60
54
17
165
33
28
125
Qor Q
-
16
13
56
16
-
6V
2V
4.5 V
13
29
9
25
21
75
15
6V
8
13
Power dissipation capacitance per flip-flop
No load, TA
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-144
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
205
49
42
41
35
155
31
110
22
19
25°C
UNIT
MHz
245
185
37
31
=
SN74HC112
MIN MAX
4
20
24
20
4.5 V
6V
2V
4.5 V
Qor Q
SN54HC112
MIN MAX
3.4
26
95
19
16
ns
ns
ns
SN54HC 113, SN7 4HC 113
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLIP· FLOPS WITH PRESET
02684, OECEM8ER 1982-REVISEO SEPTEMBER 1987
•
•
SN54HC113 ... J PACKAGE
SN74HC113 ... 0 OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300·mil
DIPs
ITOP VIEW)
lCLK
lK
Dependable Texas Instruments Quality and
Reliability
VCC
2CLK
2K
2J
2PRE
20
20
1J
lPRE
10
10
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the Preset input sets the outputs regardless of
the levels of the other inputs. When Preset (PRE)
is inactive (high), data at the J and K inputs
meeting the setup time requirements are
transferred to the outputs on the negative-going
edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to
the rise time of the clock pulse. Following the
hold time interval, data at the J and K inputs may
be changed without affecting the outputs. These
versatile flip-flops can perform as toggle flipflops by tying J and K high.
GND
SN54HC113 .•. FK PACKAGE
ITOP VIEW)
3
2
1 20 19
18
17
16
15
14
910111213
The SN54HC113 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC113 is
characterized for operation from - 40°C to
85°C.
lei 0 Uiel eI
-ZZNN
(!l
NC-No internal connection
logic symbol t
FUNCTION TABLE
INPUTS
1m
OUTPUTS
a
lJ
H
L
00
00
L
1CLK
1K
2m
H
2J
a
PRE
ClK
J
K
L
x
X
X
H
I
I
I
I
H
L
L
H
L
H
l
H
L
H
H
TOGGLE
X
X
00
2CLK
2K
H
H
H
H
00
(4)
s
(5)
1Q
1li
20
2li
tThis symbol is in accordance with ANSIIIEEE Std 91·1984 and
lEe Publication 617·12.
Pin numbers shown are for D. J. and N packages.
0'
PRODUCTION DATA dac.manta ..ntai. iofa""alio.
pobli••tio••ot•• Pr.'uoll ••nlonn ta
apICilicllio•• per Ill. tar... at T..... lnatru_
..mat ••
=i~a=':.7.;
=:': :.:.:."::t't:~~
not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © 1982. Texas Instruments Incorporated
2-145
SN54HC113, SN74HC113
DUALJ·K NEGATIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH PRESET
logic diagram, each flip-flop (positive logic)
PRE --------~---------------------------------.--------_,
Q
K
i>t?::;
ClK ----------.....
::r::
(")
3:
oen
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
C
CD
<
f)'
CD
en
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommel}ded operating conditions
SN54HC113
MIN NOM MAX
6
2
5
1.5
Vee Supply voltage
VIH High-level input voltage
Vee
Vee
Vee
Vil Low-level Input voltage
Vee
Vee
Vee
VI
Input voltage
Vo
Output voltage
tt
Input transition (rise and fall) times
Vee
Vee
Vee
TA
2-146
=2V
= 4.5 V
=6 V
=2V
= 4.5 V
=6V
3.15
4.2
0
0
0
0
0
=2V
= 4.5 V
=6 V
0
0
0
-55
Operating free-air temperature
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TeXAS 75266
SN74HC113
MIN NOM MAX
2
5
6
1.5
3.15
UNIT
V
V
4.2
0.3
0.9
1.2
Vee
Vee
1000
500
400
125
0
0
0
0
0
0
0
0
-40
0.3
0.9
V
1.2
Vee
V
Vee
1000
V
500
400
ns
85
·e
SN54HC113. SN74HC113
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH PRESET
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
=
VIH or VIL,
=
10H
-20
VCC
~A
VOH
VI - VIH or VIL,
VI = VIH or VIL,
VI = VIH or VIL,
10H - -4 mA
10H = -5.2 mA
10L
=
20~
II
ICC
Ci
VI = VCC or 0
VI = VCC or 0, 10
SV
2V
4.5 V
3.98
5.48
SV
4.5 V
SV
VOL
VI = VIH or VIL,
VI - VIH or VIL,
2V
4.5 V
6V
4.5 V
TA - 25°C
TYP MAX
MIN
1.9 1.998
4.4 4.499
5.9 5.999
10L = 4 mA
10L - 5.2 mA
SV
SV
2 to S V
=0
4.30
5.80
0.002
0.1
0.001
0.001
0.17
0.15
±0.1
0.1
0.1
0.2S
0.2S
±100
3
4
10
SN54HC113
MIN MAX
1.9
4.4
5.9
3.7
SN74HC113
MIN MAX
1.9
4.4
5.9
3.84
5.2
UNIT
V
II
5.34
0.1
0.1
0.1
0.1
0.1
0.4
0.4
0.1
0.33
0.33
±1000
±1000
80
10
40
10
V
en
G)
U
'S;
nA
G)
c
~
pF
en
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
2V
4.5 V
SV
2V
Clock frequency
PRE low
tw
Pulse duration
CLK high or low
Data (J, KI
tsu
Setup time
before CLKI
th
Hold time, data after CLKI
SN54HC113
MIN MAX
SN74HC113
MIN MAX
6
31
4.2
21
25
5
25
3S
150
125
20
17
30
25
120
24
25
21
100
80
1S
SV
14
2V
4.5 V
100
20
17
25
4.5 V
SV
2V
4.5 V
6V
125
25
25
40
21
30
5
4
8
7
S
5
0
0
0
0
0
0
0
0
TEXAS •
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265
::E
u
J:
MHz
ns
20
17
20
150
30
0
UNIT
29
100
4.5 V
SV
2V
4.5 V
6V
2V
PRE inactive
TA - 25°C
MIN
MAX
o
ns
ns
2-147
SN54HC113, SN74HC113
DUAL J-K NEGATIVE-EDGE-TRIGGERED
FliP-FLOPS WITH PRESET
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
PRE
OorO
::E:
tpd
ClK
OorO
s:o
tt
(')
en
C
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN
TYP MAX
10
6
31
50
36
60
60
165
18
33
15
28
140
85
19
28
16
24
28
75
15
8
6
13
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
CD
en
2-148
TEXAS
SN54HCl13
MIN MAX
4.2
21
25
250
50
43
211
42
36
110
22
19
No load, TA = 25°C
Power dissipation capacitance per flip· flop
CD
~.
Oor 0
vCC
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74HC113
MIN MAX
5
25
29
205
41
35
175
35
30
95
19
16
UNIT
MHz
ns
ns
ns
SN54HC114, SN74HC114
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLlp·FLOPS
WITH PRESET. COMMON CLEAR, AND COMMON CLOCK
02684. DECEM8ER 1982-REVISED SEPTEM8ER 1987
•
•
SN54HCl14 .•. J PACKAGE
SN74HCl14 ... 0 OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300·mil
DIPs
(TOP VIEW)
ClR
lK
lJ
Dependable Texas Instruments Quality and
Reliability
VCC
ClK
2K
2J
2PRE
20
20
1PRE
10
description
15
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the Preset or Clear inputs sets or resets the
outputs regardless of the levels of the other
inputs. When the Preset and Clear are inactive
(high). data at the J and K inputs meeting the
setup time requirements are transferred to the
outputs on the negative-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold time interval.
data at the J and K inputs may be changed
without affecting the levels at the outputs.
These versatile flip-flops can perform as toggle
flip-flops by tying J and K high.
GND
II
SN54HCl14 .•. FK PACKAGE
(TOP VIEW)
~
u~
15
U U U..J
~~z>u
3
lJ
NC
lPRE
NC
10
2
1 2019
4
18
5
17
6
16
8
14
15
2K
NC
2J
NC
2PRE
9 1011 12 13
The SN54HCl14 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC114 is
characterized for operation from - 40°C to
85°C.
IOOUIOO
...... Z Z N N
(!l
NC - No internal connection
logic symbol t
FUNCTION TABLE
CLR (I)
INPUTS
PRE
L
CLR
H
H
L
CLK
X
X
X
OUTPUTS
0
J
X
X
X
K
0
X
X
X
H
L
L
H
H'
H'
L
H
L
L
00
00
L
L
H
H
H
H
j
H
L
H
H
L
H
L
H
H
H
I
I
H
H
TOGGLE
H
H
H
X
X
00
j
00
.:t:This configuration is nonstable; that is, it will not
persist when either Preset or Clear returns to its
inactive (high) level.
PRODUCTION DATA documents contain information
currant .s of publication date. Products conform to
spacific.fians per tbe tarms of Taxas Instruments
:=~ir,.i~:1~1i ~~:~ti:r :'~D:.a;:~:.:::s not
CLK (131
lPRE (41
lJ (3)
(5)
lK (2)
lK
2PRE (101 ..... t------t
2J (111
lQ
lQ
2K (12)
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEG Publication 617·12 .
Pin numbers shown are for D, J, and N packages.
Copyright @ 1982, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-149
SI!i4HC114, SI74HC114
DUAL J·K IEGATlVE·EDGE·TRIGGERED FLlp·FLOPS
WITH PRESET, COMMOI CLEAR, AID COMMOI CLOCK
logic diagram, each flip-flop (positive logic)
'PRE-----------------_-----,
J----,
K - - 1 -___
Q
r----------,
CLK~C
•
I
I
-
.iI t-:.--C
I
I
CUi
I
I
COMMON TO
I
I
I
L!I!!.'!.':.L!.:':.L~'!._J
absolute maximum ratings over operating free-air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vce) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ............... 260°C
Storage temperature range ..........................•.............. - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended opereting
conditions" is not implied. Exposure to absolute·maximum-rated conditions for extended periods may affect device raliability.
recommended operating conditions
Vee Supply voltage
VIH High-level Input voltage
Vee = 2 V
Vee = 4.5 V
VIL Low-level Input voltage
Vee = 6 V
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
VI
Input voltage
Vo
Output voltage
tt
Input transition (rise and fall) times
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
TA
2-150
Operating free-air temperature
SN54HC114
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0
0.3
0
0.9
1.2
0
0
Vee
0
Vee
0
1000
0
500
0
400
-55
125
TEXAS ."
INSTRUMENlS
POST OFFICE 80)( 655012 • DALLAS, TEXAS 75265
SN74HC114
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0
0.9
0
0
1.2
0
Vee
0
Vee
0
1000
0
500
400
0
-40
85
UNIT
V
V
V
V
V
ns
·e
· SN54HC114, SN74HC114
DUAL J·K NEGATlVE·EDGE·TRIGGERED FLlp·FLOPS
WITH PRESET, COMMON CLEAR, AND COMMON CLOCK
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
~A
VI = VIH or Vil.
10H = -20
VI = VIH or Vil.
VI = VIH or Vil.
10H = -4 mA
10H= -5.2mA
VOH
VI = VIH or Vil.
10l = 20 pA
VOL
II
ICC
Ci
VI
VI
VI
VI
=
=
-
VIH or Vil. 10l - 4mA
VIH or Vil. 10l = 5.2 mA
VCC or 0
VCC or O. 10 - 0
TA - 25°C
TVP MAX
MIN
2V
4.5 V
6V
4.5 V
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
BV
2V
4.5 V
5.48
SN54HC114
MIN MAX
1.9
4.4
5.9
3.7
1.9
4.4
5.9
3.84
5.34
5.80
0.002
0.001
0.1
0.1
0.1
0.1
BV
4.5 V
6V
0.001
0.17
0.15
0.1
0.2B
0.26
0.1
0.4
0.4
BV
6V
±0.1
±100
4
3
10
±1000
80
10
2 to B V
SN74HC114
MIN MAX
5.2
UNIT
V
0.1
0.1
0.1
0.33
0.33
±1000
40
10
II
V
en
4)
(,)
nA
'S;
pA
pF
c
4)
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
TA - 25°C
MAX
MIN
2V
fclock
tw
tsu
Clock frequency
4.5 V
BV
2V
4.5 V
ClK high or low
BV
2V
4.5 V
20
17
100
20
Data (J. K)
6V
2V
4.5 V
100
20
mE or CUi
inactive
th
Hold time. data after ClKI
BV
2V
4.5 V
6V
2V
4.5 V
6V
5
25
29
100
PFiE or<:Di low
Pulse duration
Setup time
before ClKI
0
0
0
MIN
0
MAX
3.4
0
0
150
17
20
30
25
150
30
25
150
30
25
17
17
100
20
150
30
17
0
0
0
TEXAS
SN54HC114
25
0
0
0
~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TeXAS 75265
SN74HCl14
MIN MAX
0
0
0
125
25
21
125
25
21
125
25
21
125
4
20
UNIT
en
0
:E
(.)
l:
MHz
24
ns
ns
25
21
0
0
0
ns
2-151
SN54HC114, SN74HC114 .
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLlp·FLOPS
WITH PRESET, COMMON CLEAR, AND COMMON CLOCK
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(lNPUTI
TO
(OUTPUTI
f max
::I:
tpd
Pm' or ClR
QorQ
tpd
ClK
QorQ
(")
3:
tt
oen
C
<
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN
TYP MAX
5
9
25
45
29
50
75
175
20
35
17
30
63
175
19
35
16
30
28
75
15
8
13
6
Power dissipation capacitance per flip-flop
m
ri'
m
QorQ
VCC
No load, TA = 25°C
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
U)
2-152
SN54HC114
MIN MAX
3.4
17
20
250
50
42
250
50
42
110
22
19
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74HC114
MIN MAX
4
20
24
220
44
37
220
44
37
95
19
16
UNIT
MHz
no
no
no
SN54HC125. SN54HC126
SN74HC125. SN74HC126
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
02804, MARCH 1984-REVISED JUNE 1989
•
SN54HC125, SN54HC126 ... J PACKAGE
SN74HC125, SN74HC126 ... N PACKAGE
'High-Current 3-State Outputs Interface
Directly with System Bus or Can Drive Up
to 15 LSTTL Loads
•
Package Options Include Ceramic Chip
Carriers and Standard Plastic and Ceramic
300-mil DIPs
•
Dependable Texas Instruments Quality and
Reliability
ITOP VIEW)
1G, 1Gt
1A
1Y
2G, 213t
2A
2Y
GND
description
VCC
4G,4Gt
4A
4Y
3G, 3Gt
3A
3Y
II
SN54HC125, SN54HC126 ... FK PACKAGE
These bus buffers feature independent line
drivers with three-state outputs. Each 'HC125
output is disabled when the associated G is high,
and each 'HC 126 output is disabled when the
associated G is low.
The SN54HC125 and SN54HC126 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HC125 and SN74HC126 are characterized
for operation from -40°C to 85°C,
CI)
(TOP VIEW)
CD
Co)
'>CD
Q
3
1Y
NC
2G, 2Gt
NC
2
en
1 2019
4
18
5
17
6
16
15
14
8
o
4A
NC
4Y
NC
3G,313t
:::?!
(.)
:J:
9 1011 12 13
FUNCTION TABLES
>-ou>-«
NZZMM
'HC125
'HC126
(EACH BUFFER)
(EACH BUFFER)
INPUTS
OUTPUT
INPUTS
(!J
t(j on 'He125; G on 'He126
OUTPUT
G
A
Y
G
A
Y
L
H
H
H
H
H
L
L
L
H
L
L
H
X
Z
L
X
Z
H
=
high level, L
=
low level, X
NC -- No internal connection
= irrelevant
logic symbols t
'HC126
'HC125
EN
[>
(1)
'V
(31
(61
2A
3G
3A
(131
4(;
(12)
4A
(81
(11)
lG
1Y
lA
2G
2Y
2A
3G
3Y
3A
EN
(21
(4)
'V
(31
(61
(5)
(101
(81
(9)
(131
4G
(121
4A
4Y
[>
(111
1Y
2Y
3Y
4Y
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617·12.
Pin numbers shown are for J and N packages.
PRODUCTION DATA documonts contain information
current I. of publication data. Pradam conform to
spacifications par lh. terms of TaXI. Instruments
::~:=i;~~:1~7i ~=::i:r mD::;::::':~~ not
Copyright @ 1989, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-153
SN54HC125, SN54HC126, SN74HC125, SN74HC126
QUADRUPLE BUS BUFFER GATES WITH 3·STATE OUTPUTS
logic diagrams (positive logic)
'HC125
•
'HC126
1G
(1)
1A
(2)
1Y
:t:
(')
~
2G
0
rn
c
(1)
2Y
2A
<
Ci'
(1)
en
3G
3Y
3A------j
3Y
4G
4A------j
Pin numbers shown are for J and N packages.
2-154
TEXAS ."
INSTRUMENTS
POST OFFICE' BOX 655012· DALLAS, TEXAS 75265
4Y
SN54HC125, SN54HC126, SN74HC125, SN74HC126
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Va < 0 or Va > Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (Va = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±35 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: N package ................... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
fI
recommended operating conditions
SN54HC125
SN74HC125
SN54HC126
Vee Supply voltage
VIH High·level input voltage
VIL Low-level input voltage
Vee
~
2 V
Vee
~
4.5 V
SN74HC126
MIN
NOM
MAX
2
5
6
UNIT
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
3.15
Vee ~ 6 V
4.2
4.2
Vee - 2 V
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
Vee
~
4.5 V
Vee ~ 6 V
V
V
V
VI
Input voltage
0
Vee
0
Vee
V
Va
Output voltage
0
Vee
1000
0
Vee
1000
V
ns
tt
TA
Input transition (rise and fall) times
Vee
~
2 V
0
Vee
~
4.5 V
0
500
0
500
Vee
~
6 V
0
-55
400
0
400
125
-40
85
Operating free-air temperature
0
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
Vce
TA = 25°C
MIN
2V
VI ~ VIH or VIL.
10H ~ -20
~A
VI ~ VIH or VIL.
IOH ~ -6 rnA
IOH ~ -7.8 rnA
4.5 V
6V
VOH
VI ~ VIH or VIL,
VI ~ VIH or VIL.
10L ~ 20 ~A
VOL
VI ~ VIH or VIL.
IOL
~
6 rnA
VI ~ VIH or VIL.
VI ~ Vee or 0
10L
~
7.8 rnA
II
10Z
Va ~ Vee or 0
lee
ei
VI
~
Vee or 0, 10
~
0
TYP
MAX
1.9 1.998
4.4 4.499
3.98
6V
5.48
SN74HC125
SN54HC126
SN74HC126
MIN
MAX
4.30
5.80
MIN
UNIT
MAX
1.9
1.9
4.4
5.9 5.999
4.5 V
SN54HC125
4.4
5.9
5.9
3.7
3.84
V
5.34
5.2
2V
0.002
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
V
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
6V
±0.01
±0.5
±10
±5
pA
160
3
8
10
80
10
pA
pF
6V
2 to 6 V
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
10
2-155
S154HC125, SI74HC125
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL
50 pF (see Note 1)
=
PARAMETER
•
::t
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
-G
Y
!dis
-G
Y
(")
s:
tt
c
Cpd
oen
(1)
<
n'
(1)
(II
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
MIN
TA t 25°C
TYP MAX
48
120
14
24
11
20
53
120
14
24
11
20
30
120
15
24
20
14
28
60
8
12
6
10
No load. TA
Power dissipation capacitance per gate
SN54HC125
MIN MAX
150
36
25
180
36
31
180
36
31
90
18
15
=
25°C
SN74HC125
MIN MAX
150
30
26
150
30
26
150
30
26
75
15
13
UNIT
ns
ns
ns
ns
45 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
-G
Y
tt
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN
TYP MAX
67
150
19
30
15
25
100
135
20
27
17
23
45
210
17
42
13
36
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-156
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC125
MIN MAX
225
45
39
200
40
34
315
63
53
SN74HC125
MIN MAX
190
38
32
170
34
29
265
53
45
UNIT
ns
ns
ns
SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
G
y
tdis
G
y
PARAMETER
Any
tt
vcc
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Power dissipation capacitance per gate
TA - 25°C
MIN
TYP MAX
120
47
14
24
11
20
57
120
16
24
12
20
120
35
17
24
15
20
28
60
12
8
10
6
No load, TA
SN54HC126
MIN MAX
180
36
31
180
36
31
180
36
31
90
18
15
= 25°C
SN74HC126
MIN MAX
150
30
26
150
30
26
150
30
26
75
15
13
UNIT
ns
ns
ns
ns
45 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
G
Y
tt
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN
TYP MAX
67
150
19
30
15
25
100
135
20
27
17
23
45
210
17
42
13
36
SN54HC126
MIN MAX
225
45
39
202
40
36
315
63
53
SN74HC126
MIN MAX
188
38
33
169
36
30
265
53
45
UNIT
ns
ns
ns
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS. TEXAS 75265
2-157
:I:
(')
s:
otJ)
c
CD
<
r;"
CD
en
2-158
SN54HC132, SN74HC132
QUADRUPLE POSITIVE-NAND GATES WITH SCHMln-TRIGGER INPUTS
02684. DECEMBER 1982-REVISED SEPTEMBER 1987
•
Operation from Very Slow Input Transitions
•
Temperature-Compensated Threshold Levels
•
High Noise Immunity
•
Seme Pinouts as 'HCOO
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC132 ... J PACKAGE
SN74HC132 ... 0 DR N PACKAGE
(TOP VIEW)
Vee
1A
18
1V
2A
28
2Y
48
4A
4Y
38
3A
3Y
GND
SN54HC132 ... FK PACKAGE
U)
(TOP VIEW)
description
CD
U
U
m' Veel ........ , . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . .. . . . . . . .. ±20 mA
eontinuous output current, 10 (VO = 0 to Veel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
eontinuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300 0 e
Lead temperature 1,6 mm (1/16 in) from .case for 10 s: D or N package ............... 260 0 e
Storage temperature range ......................................... - 65 °e to 150 0 e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
:t
o
3:
otf)
o
CD
<
c;'
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC132
Vee
VIH
Supply voltage
High-level input voltage
Vee'" 2 V
Vee = 4.5 V
Vee = 6 V
CD
fII
Vee = 2 V
VIL
Low-level input voltage
Vee = 4.5 V
Vee = 6 V
VI
Input voltage
Vo
TA
Output voltage
Operating free-air temperature
2-160
TEXAS
SN74HC132
MIN
NOM
MAX
MIN
NOM
MAX
2
1.5
3.15
4.2
0
0
0
0
0
-55
5
6
2
5
6
0.3
0.9
1.2
1.5
3.15
4.2
0
0
0
0
0
-40
-IJJ
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Vee
Vee
125
UNIT
V
V
0.3
0.9
1.2
V
Vee
V
Vee
V
·e
85
SN54HC132, SN74HC132
QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONOITIONS
VCC
2V
VI ~ VIH or VIL.
IOH ~ -20
~A
4.5 V
VOH
VI
~
VIH or VIL.
VI ~ VIH or VIL.
VI ~ VIH or VIL.
~
10H
-4 rnA
10H ~ -5.2 rnA
10L ~ 20 ~A
VOL
VI ~ VIH or VIL.
VI ~ VIH or VIL.
10L
~
4 rnA
10L
~
5.2 rnA
VT+
VT-
VT+ - VT-
TA
~
SN54HC132
25°C
SN74HC132
MIN
TYP
1.9
1.998
1.9
1.9
4.4 4.499
4.4
4.4
6V
4.5 V
5.9
3.98
6V
5.48
MAX
MIN
MAX
MIN
5.999
5.9
5.9
4.30
3.7
3.84
5.80
MAX
UNIT
V
0.002
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.1
V
0.33
2V
0.70
1.2
1.50
0.70
1.50
0.70
1.50
4.5 V
1.55
2.5
3.15
1.55
3.15
1.55
3.15
6V
2.10
3.3
4.20
2.10
4.20
2.10
4.20
V
2V
0.30
0.6
1.00
0.30
1.00
0.30
1.00
4.5 V
0.90
1.6
2.45
0.90
2.45
0.90
2.45
6V
2V
1.20
0.20
2.0
0.6
3.20
1.20
1.20
0.20
3.20
1.20
1.20
0.20
3.20
1.20
4.5 V
0.40
0.9
2.10
0.40
2.10
0.40
2.10
6V
0.50
1.3
2.50
0.50
2.50
0.50
2.50
±0.1
±100
±1000
±1000
nA
2
40
20
~A
10
10
10
pF
II
VI ~ Vee or 0
6V
lee
ej
VI ~ Vee or O. 10 ~ 0
6V
2 to 6 V
3
fI
5.34
5.2
2V
V
V
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
Vec
2V
tpd
tt
A or B
Y
Any
TA ~ 25°e
TYP MAX
SN54HC132
MIN
MIN
MAX
SN74HC132
MIN
MAX
60
120
186
156
4.5 V
18
25
37
31
6V
14
21
32
27
2V
28
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance per gate
No load. TA
~
UNIT
ns
ns
25°e
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-161
E
:::J:
(')
s:o
t/)
c
CD
<
c;"
CD
(I)
2-162
SN54HC133, SN74HC133
13-INPUT POSITIVE-NAND GATES
1982-REVISED SEPTEMBER 1987
•
•
SN54HC133 ... J PACKAGE
SN74HC133 ... 0 OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
(TOP VIEW)
A
VCC
M
L
K
J
B
C
Dependable Texas Instruments Quality and
Reliability
0
description
E
F
G
GND
These devices contain a single 13-input NAND
gate. They perform the Boolean functions in
positive logic:
Y = A·B.C.D·E·F·G.H.I·J·K·L.M
•
H
Y
SN54HC133 ... FK PACKAGE
or
(TOP VIEW)
Y = A+B+C+D+E+F+G+H+I+J+K+L+M
U
al«~~:2
The SN54HC133 is characterized for operation
over the full military temperature range of - 55°C
to 125°C. The SN74HC133 is characterized for
operation from -40°C to 85°C.
J
C
1 20 19
18
o
17
NC
6
16
E
7
15
F
8
FUNCTION TABLE
INPUTS A THRU M
2
4
5
OUTPUT
14
9 1011 1213
y
<.:lOU>-I
ZZ
All inputs H
L
One or more inputs L
H
<.:l
NC - No internal connection
logic symbol t
A
B
C
0
E
F
G
H
I
(1)
logic diagram (positive logic)
8<
A
(2)
B
C
(3)
(4)
o
(5)
E
F---I-_
(6)
(7)
G
(9) y
I
(11)
J
(12)
K
L
M
):>---v
H---I--
(10)
K
(13)
L
(14)
M
(15)
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
Copyright © 1982. Texas Instruments Incorporated
PRODUCTION DATA documants contain informalion
current 8. of publication date. Products conform to
spacifications per the tarms of Taxas Instruments
=~::i;ai~:1~1i ~=~::i:; :lr=:::9t:S~1 not
TEXAS.
INsrRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-163
SN54HC133. SN74HCt33
13-INPUT POSITIVE-NAND GATES
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (VO < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
::J:
(')
3:
ot/)
c
CD
<
(;'
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is, not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC133
Vee Supply voltage
VIH
Vee
Vee
High-level input voltage
Vee
CD
Vee
(II
Vil
low-level input voltage
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
SN74HC133
MIN
NOM
MAX
2
5
6
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
4.2
3.15
UNIT
V
V
4.2
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
V
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
Vee
1000
0
Vee
1000
V
n.
Vee
tt
Input transition (rise and fall) times
Vee
Vee
TA
=2V
= 4.5 V
=6V
0
Operating free-air temperature
0
0
500
0
500
0
-55
400
0
400
125
-40
85
De
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MAX
SN74HC133
MIN
2V
1.9
1.998
1.9
1.9
VIH or Vll,
10H
=
-20/LA
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
VI
VI
=
=
VIH or Vil.
VIH or Vll,
10H
=
=
-4 rnA
4.5 V
3.98
4.30
5.9
3.84
6V
5.48
3.7
5.2
=
VIH or Vll,
10H
10l
=
-5.2 rnA
20 pA
VOL
=
=
VIH or Vil.
10l
VI
VIH or Vll,
VI - Vee or 0
10l
VI
2-164
MIN
=
VI
lee
ei
SN54HC133
VI
VOH
II
TA = 25°C
TYP MAX
MIN
VI
=
Vee or 0,10
= 4 rnA
= 5.2 rnA
=0
5.80
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
±0.1
0.26
±1oo
0.4
6V
±1000
0.33
±1000
nA
2
40
20
pA
10
10
10
pF
6V
2 to 6 V
3
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX. 655012 •
DALLA~,
TEXAS 75265
V
SN54HC133, SN74HC133
13-INPUT POSITIVE-NAND GATES
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(INPUT)
Any
TO
(OUTPUT)
vCC
2V
4.5 V
6V
2V
4.5 V
6V
Y
Y
TA = 25°C
MIN
TYP MAX
70
16
13
38
8
6
SN54HC133
MIN
150
30
26
75
15
13
No load, TA = 25°C
Power dissipation capacitance
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
MAX
225
45
38
110
22
19
SN74HC133
MIN
MAX
190
38
33
95
19
16
24 pF typ
UNIT
ns
ns
II
U)
CD
Co)
'$
CD
c
en
o
:;
CJ
J:
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-165
E
J:
("')
s:o
rJ)
cCD
<
,sCD
(II
2-166
SN54HC137, SN74HC137
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
D2684, DECEMBER 1982-REVISED JUNE 1989
•
Combines Decoder and 3·Bit Address Latch
•
Incorporates 2 Output Enables to Simplify
Cascading
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300·mil
DIPs
•
SN54HC137, .• J PACKAGE
SN74HC137 ..• ot OR N PACKAGE
(TOP VIEW)
Vee
A
B
YO
Yl
Y2
Y3
Y4
Y5
Y6
e
GL
G2
Gl
Y7
GND
Dependable Texas Instruments Quality and
Reliability
fI
description
The 'HC137 is a three-line tD eight-line
decoder/demultiplexer with latches Dn the three
address inputs. When the latch-enable input (GL)
is low, the 'HC137 acts as a decoder/
demultiplexer. When GL goes from low to high,
the address present at the select inputs (A, B,
and C) is stored in the latches. Further address
changes are ignored as long as GL remains high.
The output enable controls, G1 and (32, control
the outputs independently of the select or latchenable inputs, All of the outputs are forced high
if G1 is low or (32 is high. The 'HC 137 is ideally
suited for implementing glitch-free decoders in
strobed (stored-address) applications in busoriented systems,
The SN54HC 137 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC137 is
characterized for operation from -40°C to
85°C,
SN54HC137 , .. FK PACKAGE
(TOPVIEWI
U
U
Uo
IXl<{Z»
3
Gl
2
1 20 19
4
18
5
17
6
16
7
15
8
14
Yl
Y2
9 1011 12 13
..... OU"''''
>ZZ»
t!)
NC-No internal connection
t Contact the factory for D availability
logic symbols* (alternatives)
A
B
c
OMUX
x/V
GL
(11
80
(21
2
A
4
B
(31
c
Gl (61
G2 (51
vo
(11
JGt
(21
(31
VI
V2
V3
&
V4
EN
Gl
V5
G2
V6
V7
'These symbols are in accordance with ANSIIIEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
PRODUCTION DATA doc.monls contain inform.lion
currant .s of publicatiDn date. Preducts conform to
specifications per the terms of Taxas Instruments
::'~:~~i;a[::I~~ ~:~~:i:; ~~o=~9t~:~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DAllAS. TEXAS 75265
Copyright @ 1989, Texas Instruments Incorporated
2-167
SN54HC137, SN74HC137
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
FUNCTION TABLE
INPUTS
ENABLE
GL G1 G2
X
X
X
L
H
L
L
E
L
H
H
H
C
X
X
L
H
X
L
L
L
L
L
L
X
X
L
L
L
H
L
H
H
::J:
~
L
L
H
H
L
L
H
H
H
H
L
H
H
H
L
X
X
X
oen
C
CD
<
c=r
L
L
X
X
L
L
L
(')
H
H
L
H
H
SELECT
B
A
L
L
H
L
H
OUTPUTS
VO V1
H
H
H
L
H
H
H
H
H
L
H
H
H
V2 V3 V4 V5 V6 V7
H
H
H H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H H
H
H
L
H
L
H
H
L
H
H
H H
H
H
H
H
H H
H H
H
H
H
Output corresponding
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
H
H
to stored
address, L; all others, H
logic diagram (positive logic)
CD
(I)
(151
VO
~-,-,(1..;.:41_ V1
~_(:..:.13:;;.1_ V2
(121
~--V3
~--V4
p-_U....;OI_ V5
(91
V6
V7
Pin numbers shown are for 0, J, and N packages.
2-168
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC131, SN14HC131
3-UNE TO B-UNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vcc .............................................. "
-0.5 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ............................. ±
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±
Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ...............
Lead temperature 1,6 mm (1/16 in) from case for 10 s: Dar N package ...............
Storage temperature range ......................................... - 65°C to
to 7 V
20 mA
20 mA
25 mA
50 mA
300°C
260°C
1 50°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC137
MIN NOM MAX
Vee Supply voltage
VIH High-level input voltage
Vee
Vee
Low-level input voltage
Vee
Vee
Vee
Vil
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Output voltage
tt
Input transition (rise and fall) times
Vee
Vee
Vee
5
0.9
1.2
0
0
0
=2V
= 4.5 V
=6V
0
0
0
-55
Operating free-air temperature
6
0.3
0
0
Input voltage
VI
Vo
TA
2
1.5
3.15
4.2
SN74HC137
MIN NOM MAX
2
1.5
3.15
5
0.3
0.9
0
Vee
Vee
1000
500
400
125
0
0
-40
UNIT
V
V
4.2
0
0
0
0
0
6
V
1.2
Vee
Vee
1000
V
V
500
400
ns
85
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
VI
=
VIH or Vil.
IOH
=
-20 p.A
VI
VI
=
=
VIH or Vil.
VIH or Vll,
10H
10H
=
=
-4 rnA
-5.2 rnA
VOH
lee
ei
6V
2V
5.48
5.80
0.002
0.1
0.33
0.33
±1000
160
10
±1000
80
10
4.5 V
6V
0.001
0.001
VI
=
=
=
VIH or Vll,
10l
IOl
= 4 rnA
= 5.2 rnA
4.5 V
6V
0.17
0.15
0.26
0.26
6V
±0.1
±100
3
8
10
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
V
0.1
0.4
0.4
20 ~A
6V
2 to 6 V
5.9
3.84
5.34
0.1
=
=0
5.9
3.7
0.1
0.1
IOl
VI - Vee or 0, 10
1.9
4.4
0.1
0.1
VIH or Vll,
VIH or Vil.
Vee or 0
SN74HC137
MIN MAX
1.9
4.4
5.2
=
VI
VI
SN54HC137
MIN MAX
0.1
0.1
VI
VOL
II
2V
4.5 V
6V
4.5V
TA = 25°C
MIN
TYP MAX
1.9 1.998
4.4 4.499
5.9 5.999
4.30
3.98
V
nA
p.A
pF
2-169
SN54HC137. SN74HC137
3-LlNE TO B-LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
-
Pulse duration, GL low
tw
II
-
Setup time, A, B, and C before GLI
tsu
-
Hold time, A, B, and C after GLI
th
:r:
C')
s:o
SN54HC137
MIN
MAX
SN74HC137
MIN
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
75
115
95
4.5 V
15
23
19
6V
13
20
16
2V
5
5
5
4.5 V
5
5
5
6V
5
5
5
MAX
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
(I)
cCD
TA = 25°C
MIN
MAX
PARAMETER
<
tpd
(;'
CD
en
tpd
tpd
tpd
FROM
(INPUT)
A, B,C
-G2
Gl
-GL
TO
(OUTPUT)
VCC
Y
y
y
y
TA = 25°C
MIN
TYP MAX
285
SN74HC137
MIN
MAX
190
4.5 V
23
38
57
240
48
6V
19
32
48
41
2V
59
145
220
180
4.5 V
17
29
44
36
6V
14
25
37
31
2V
61
145
220
180
4.5 V
17
29
44
36
6V
14
25
37
2V
77
22
19
38
8
6
190
285
31
240
2V
4.5 V
6V
Power dissipation capacitance
38
57
48
32
48
41
75
110
95
15
22
19
13
19
16
No load, TA = 25°C
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-170
MAX
82
4.5 V
Y
MIN
2V
6V
tt
SN54HC137
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
85 pF typ
UNIT
ns
ns
ns
ns
ns
SN54HCT137. SN74HCT137
3-UNE TO B-UNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
02804. MARCH 1984-REVISEO JUNE 1989
•
•
Combines Decoder and 3-Bit Address Latch
•
Incorporates 2 Output Enables to Simplify
Cascading
•
•
SN54HCT137 ••. J PACKAGE
SN74HCT137 ••• N PACKAGE
(TOP VIEW)
Inputs are TTL-Voltage Compatible
A
Vee
B
YO
Yl
Y2
Y3
Y4
Y5
Y6
e
Package Options Include Ceramic Chip
Carriers and Standard Plastic and Ceramic
300-mil DIPs
GL
<32
Gl
Y7
GND
Dependable Texas Instruments Quality and
Reliability
fI
fI)
description
Q)
SN54HCT137 ... FK PACKAGE
(TOP VIEW)
The 'HCT137 is a three-line to eight-line
decoder/demultiplexer with latches on the three
address inputs. When the latch-enable input (GL)
is
low,
the
'HCT137
acts
as
a
decoder/demultiplexer. When GL goes from low
to high, the address present at the select inputs
(A, B, and C) is stored in the latches. Further
address changes are ignored as long as GL
remains high. The output enable controls, G1
and G2, control the outputs independently of the
select or latch-enable inputs. All of the outputs
are forced high if G 1 is low or G2 is high. The
'HCT137 is ideally suited for implementing
glitch-free decoders in strobed (stored-address)
applications in bus-oriented systems.
o
oS;
U
Q)
u uo
IIl«Z>>3
2
C
en
1 20 19
o
18
~
17
u
:x:
16
15
14
9 1011 12 13
.... au "''''
>-zz>->(!)
NC-No internal connection
The SN54HCT137 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCT137 is
characterized for operation from -40°C to
85°C.
FUNCTION TABLE
INPUTS
OUTPUTS
ENABLE
GI G1 G2
C
B
A
YO
Y1
Y2
X
X
H
X
X
X
H
H
H
H
H
H
H
H
X
L
X
X
X
X
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
H
H
H
H
H
H
H
L
H
L
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
L
L
H
L
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
SELECT
Y3 Y4 Y5 Y6
L
Y7
L
H
L
H
L
L
H
H
H
H
L
H
H
H
L
H
L
H
L
H
H
H
H
H
H
L
H
H
L
H
L
H
H
L
H
H
H
H
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
L
X
X
X
PRODUCTION DATA documents contain information
currenl 8S of publication data. Products conform fa
spacifications par the tarms of Taxa. Instruments
:!=~~i;Bi~:I~i ~:~::i:; :'~D:.e:::9t:~~s
not
Output corresponding to stored
address, l; all others. H
"!1
INSTRUMENlS
TEXAS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright @ 1989. Texas Instruments Incorporated
2-171
SN54HCT137, SN74HCT137
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
logic symbols (alternatives) t
X/Y
A
(1)
B (2)
c
•
(3)
8D
YO
2
A
4
B
Yl
Y2
C
G1 (6)
G2
(5)
EN
Gl
%
Y6
()
s::
o
t/)
C
CD
<
Y7
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
logic diagram (positive logic)
n'
CD
o
(15)
YO
»--:';(1...,;4);... Yl
»-...,;(:..:.;13:::,)_ Y2
1>-_(;,,;,1,;,,:11_ Y4
(10)
J)---'---'- Y5
(9)
Gl
(32
Pin number. shown are for J and N packages.
2-172
TEXAS.
INSTRUMENTS
POST OFFICE BOX. 655012. DALLAS, TEXAS 75265
Y6
SN54HCT137, SN74HCT137
3-UNE TO B-UNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
absolute maximum ratings over operating free-air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ............................. ± 20 rnA
Continuous output current, 10 (Vo = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 rnA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Lead temperature 1,6 mm (1116 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: N package ................... 260°C
Storage temperature range ......................................... - 65°C to 150°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximurn-rated conditions for extended periods may affect device reliability.
fI
recommended operating conditions
SN74HCT137
SN54HCT137
Vee Supply voltage
VIH High-level input voltage
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
V
0.8
V
V
Vee
V
I Vee = 4.5 V to 5.5 V
I Vee = 4.5 V to 5.5 V
VIL
VI
Low-level input voltage
Vo
tt
Input transition (rise and falll times
TA
Operating free-air temperature
UNIT
MIN
2
2
0
0.8
Input voltage
0
Vee
Output voltage
0
0
Vee
500
-55
125
0
0
0
0
-40
V
Vee
500
ns
De
85
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
VOL
II
lee
alee*
ei
TEST CONDITIONS
VI
VI
VI
= VIH
= VIH
= VIH
= VIH
or VIL.
10H
or VIL,
10H
or VIL,
10H
VI
or VIL,
VI - Vee or 0
10L
VCC
= -~O ~A
= -4 mA
= 20 ~A
= 4 mA
vI = Vee or 0, 10 = 0
One input at 0.5 V or 2.4 V.
Other inputs at 0 V or Vee
4.5 V
4.5 V
TA = 25 DC
TYP MAX
MIN
4.4 4.499
3.98
4.30
SN54HCT137 SN74HCT137
MIN
MAX
MIN
4.4
4.4
3.7
3.84
MAX
UNIT
V
4.5 V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
5.5 V
±0.1
±100
±1000
±1000
8
160
80
~A
1.4
2.4
3.0
2.9
mA
3
10
10
10
pF
5.5 V
5.5 V
4.5 to
5.5 V
:f:ThiS is the increase in supply current for each input that is at one of the specified TIL voltage levels rather than 0 V or
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
V
nA
Vee.
2-173
SN54HCT137. SN74HCT137
3·LlNE TO B·LlNE DECODERS/D.EMULTIPLEXERS
WITH ADDRESS LATCHES
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
tw
Pulse duration, GL low
tsu
Setup time, A, B, and C before GLt
th
Hold time, A, B, and C after GL I
4.5 V
5.5 V
-
4.5 V
5.5 V
4.5V
5.5 V
II . . . .
TA = 25°C
TYP MAX
MIN
26
23
15
14
5
5
23
21
5
5
ing .........ris... Oy" ......,m............... f •• _
~ noted), CL = 50 pF (see Note 1) .
.
3:
oen
PARAMETER
cCD
<
ri"
CD
FROM
(INPUT)
ns
ns
temp ••at........ ,••,... 0 ......' . .
4.5 V
5.5 V
25
20
38
34
57
51
48
43
4.5 V
5.5 V
4.5 V
20
17
20
17
29
25
29
25
42
44
40
44
40
36
32
36
32
36
15
63
57
22
52
47
ns
14
20
19
17
ns
Y
tpd
-G2
y
tpd
G1
Y
tpd
-GL
y
5.5
4.5
5.5
4.5
Any
TA = 25°C
MIN
TYP MAX
V
V
V
V
32
25
12
5.5 V
11
Power dissipation capacitance
SN54HCT137 SN74HCT137
MIN MAX
MIN MAX
No load, TA = 25°C
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-174
ns
VCC
A, B,C
tt
19
17
5
5
UNIT
TO
(OUTPUTI
tpd
en
SN54HCT137 SN74HCT137
MIN MAX
MIN MAX
39
33
35
30
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
85 pF typ
UNIT
ns
ns
ns
SN54HC13B, SN74HC13B
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
02684, DECEM8ER 1982-REVISED SEPTEMBER 1987
•
SN54HC138 .•. J PACKAGE
SN74HC138 •.. D OR N PACKAGE
Designed Specifically for High·Speed
Memory Decoders and Data Transmission
Systems
ITOPVIEWI
•
Incorporates 3 Enable Inputs to Simplify
Cascading and/or Data Reception
•
Package Options: Plastic and Ceramic DIPs,
Plastic Small·Outline Packages, and Ceramic
Chip Carriers
•
Dependable Texas Instruments Quality and
Reliability
description
The 'HC138 circuit is designed to be used in
high-performance memory-decoding or datarouting applications requiring very short
propagation delay times. In high-performance
memory systems this decoder can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of this
decoder and the enable time of the memory are
usually less than the typical access time of the
memory. This means that the effective system
delay introduced by the decoder is negligible.
The conditions at the binary select inputs at the
three enable inputs select one of eight input
lines. Two active-low and one active-high enable
inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can
be implemented without external inverters and
a 32-line decoder requires only one inverter. An
enable input can be used as a data input for
demultiplexing applications.
A
B
e
G2A
G2B
Gl
Y7
GND
Vee
YO
Yl
Y2
Y3
Y4
Y5
Y6
rn
SN54HC138 ... FK PACKAGE
Q)
ITOP VIEW)
CJ
Uo
':;Q)
1 2019
(I)
U
U
mZZ»
C1
NC - No internal connection
The SN54HC1 38 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC138 is
characterized for operation from -40°C to
85°C.
Copyright © 1982, Texas Instruments Incorporated
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-175
SN54HC138. SN74HC138
3·LlNE TO 8·LlNE DECODERS/DEMULTIPLEXERS
logic symbols (alternatives)t
DMUX
BIN/OCT
A (1)
A (1)
B (2)
C (3)
B (2)
2
C (3)
4
J't
IJ
&
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
logic diagram (positive logic)
Pin numbers shown are for D. J. and N packages.
2-176
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
SN54HC13B, SN74HC13B
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
FUNCTION TABLE
ENABLE
SELECT
INPUTS
G1 l;2A G2B
INPUTS
OUTPUTS
A
VO
V1
H
X
C
X
B
X
X
X
H
H
V2 V3 V4 V5
H
H
H
H
V6 V7
H
X
X
H
X
X
X
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
II
en
CD
(J
'S;
CD
C
absolute maximum ratings over operating free-air temperature range t
CJ)
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K (Va < 0 or Va > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Continuous output current, 10 (Va = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 rnA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300 De
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260 De
Storage temperature range ......................................... - 65 DC to 150 DC
o
:E
o
:I:
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN74HC138
SN54HC138
MIN
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
Vee Supply voltage
1.5
1.5
3.15
4.2
3.15
Vee = 6 V
Vee = 2 V
0
0.3
0
0.3
0.9
0
Vee = 4.5 V
0
0.9
Vee = 6 V
0
1.2
0
1.2
Vee = 2 V
VIH High-level input voltage
VIL
Low-level input voltage
Vee = 4.5 V
UNIT
V
V
4.2
V
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
Vee
1000
0
Vee
1000
V
500
400
ns
85
·e
0
Vee = 2 V
tt
Input transition (rise and fall) times
TA
0
500
0
0
-55
400
0
-40
Vee = 4.5 V
Vee = 6 V
Operating free-air temperature
TEXAS
0
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
125
2-177
SN54HC138, SN74HC138,
3-L1NE TO 8-L1NE DECODERS/DEMULTIPLEXERS
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
=
VI
VI
= VIH
= VIH
VI
=
IOH
=
-201'A
or VIL.
or VIL.
IOH
10H
=
=
-4 mA
VIH or VIL.
10L
=
VIH or VIL.
VOH
IJ
::c
3:
oen
c
CD
<
c;'
VI = VIH or VIL.
VI = VIH or VIL.
VI - VCC or 0
II
ICC
Ci
20 p.A
VI
=
VCC or O. 10
2V
4.5 V
6V
4.5 V
6V
2V
4.5 V
1.9 1.998
4.4 4.499
5.9
3.98
5.48
6V
4.5 V
6V
6V
IOL = 4 mA
10L = 5.2 mA
=0
6V
2 to 6 V
5.999
4.30
5.80
0.002
0.001
0.001
SN54HC138
MIN MAX
SN74HC138
1.9
4.4
MIN
1.9
4.4
5.9
3.7
5.2
5.9
3.84
5.34
0.1
0.1
0.1
0.1
0.17
0.15
±0.1
0.1
0.26
0.26
±100
0.1
0.4
0.4
±1000
3
8
10
160
10
MAX
UNIT
V
0.1
0.1
0.1
0.33
0.33
±1000
80
10
V
nA
p.A
pF
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
CD
(I)
-5.2 mA
VOL
(')
TA = 25 0 e
MIN
TYP MAX
Vee
PARAMETER
tpd
tpd
tt
FROM
(INPUT)
TO
(OUTPUT)
A. B. or C
Any Y
Enable
Vee
2V
4.5 V
Any Y
Any
TA = 25°C
TYP MAX
MIN
67
180
2-178
ns
ns
75
15
40
110
22
33
95
19
ns
13
19
16
6V
2V
15
66
31
155
4.5 V
6V
2V
18
15
38
31
4.5 V
6V
8
6
26
No load. TA = 25°C
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS. TeXAS 75265
UNIT
38
195
39
36
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
SN74HC138
MIN MAX
225
45
18
Power dissipation capacitance
SN54HC138
MIN MAX
270
54
46
235
47
85 pF typ
SN54HCT138, SN74HCT138
3·LlNE TO 8·LlNE DECODERS/DEMULTIPLEXERS
02804. MARCH 1984-REVISED JUNE 1989
•
Inputs are TTL·Voltage Compatible
•
Designed Specifically for High·Speed
Memory Decoders and Data Transmission
Systems
•
Incorporates 3 Enable Inputs to Simplify
Cascading and/or Data Reception
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HCT138 •.• J PACKAGE
SN74HCT138 ... ot OR N PACKAGE
ITOPVIEWI
Vee
A
B
YO
Yl
Y2
Y3
Y4
Y5
Y6
e
G2A
G2B
Gl
Y7
GND
II
II)
CD
CJ
SN54HCT138 .•. FK PACKAGE
(TOP VIEW)
description
·S
U
The' HCT138 circuit is designed to be used in
high-performance memory-decoding or datarouting applications requiring very short
propagation delay times. In high-performance
memory systems, this decoder can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of this
decoder and the enable time of the memory are
usually less than typical access time of the
memory. This means that the effective system
delay introduced by the decoder is negligible.
The conditions at the binary select inputs and the
three enable in puts select one of eight input
lines. Two active-low and one active-high enable
inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can
be implemented without external inverters and
a 32-line decoder requires only one inverter. An
enable input can be used as a data input for
demultiplexing applications.
CD
U uo
ca«z»
3
2
C
1 2019
(/)
o
e
4
18
G2A
5
17
Yl
Y2
Ne
6
16
Ne
(.)
15
Y3
Y4
J:
G2B
Gl
14
8
:::E
9 10 11 12 13
.....
ou"''''
>zz»
(!)
NC-No internal connection
t Contact the factory for 0 availability.
The SN54HCT138 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCT138 is
characterized for operation from - 40°C to
85°C.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
::~:~~i~ai~:1~1e ~~:~:~i:r ~~o::::::~:~~s
not
Copyright © 1989, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFfiCE BOX 655012· DALLAS, TeXAS 75265
2-179
SN54HCT13B, SN74HCT13B
3,L1NE TO B·L1NE DECODERS/DEMULTIPLEXERS
logic symbols (alternatives) t
BIN/OCT
A (11
AlII
B 121
C 131
B 121
2
C (31
4
Gl 161
DMUX
J'~
&
G2A (41
G2B (51
:::c
C')
s:o
f/)
cCD
Y7
tThese symbols are in accordance with ANSIIIEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for D. J. and N packages.
logic diagram (positive logic)
<
(;'
CD
(I)
Pin numbers shown are for D, J, and N packages.
2-180
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HCT13B, SN74HCT13B
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
FUNCTION TABLE
ENABLE
SELECT
G1
OUTPUTS
INPUTS
INPUTS
G2A G2B
C
B
A
YO
Y1
Y2
Y3 Y4 Y5
Y6 Y7
X
H
X
X
X
X
H
H
H
H
H
H
H
H
X
X
H
X
X
X
H
H
H
H
H
H
H
H
L
X
L
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
l
H
H
H
H
H
L
l
H
l
l
H
H
H
H
l
H
H
H
H
l
l
H
L
H
H
H
H
H
H
l
H
H
H
L
l
H
H
H
H
H
H
H
H
H
H
H
H
H
H
l
l
H
H
H
H
l
L
H
l
H
fI
en
CD
CJ
oS;
CD
C
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (VO < 0 or Vo > Vee) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 1 50°C
(IJ
0
:::!
(J
::J:
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HCT138
Vee Supply voltage
VIH High-level input voltage
I Vee
I Vee
SN74HCT138
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
2
UNIT
V
= 4.5 V to 5.5 V
2
4.5 V to 5.5 V
0
0.8
0
0.8
V
V
Vil
low-level input voltage
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
Input transition (rise and falll times
Vee
500
0
tt
0
0
Vee
500
ns
TA
Operating free-air temperature
-55
125
85
°e
=
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
0
-40
V
2-181
SN54HCT13B. SN74HCT13B
3-LlNE TO B-LlNE DECODERS/DEMULTIPLEXERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
•
x
o
3:
oen
cCD
<
(;'
VOL
"
ICC
dlee t
TEST CONDITIONS
V,
V,
V,
V,
V,
= V,H or V'l,
= V,H or V'l,
= V,H or V'l,
= V,H or V'l,
= Vee or 0
IOH
=
VCC
-20 p.A
10H = -4 rnA
10l - 20/LA
10l
=4
rnA
V, - Vee or 0,10 - 0
One input at 0.5 V or 2.4 V,
Other inputs at 0 V or Vee
4.5
4.5
4.5
4.5
5.5
5.5
V
V
V
V
V
V
5.5 V
4.5 to
ei
5.5 V
TA = 25°C
MIN
TYP MAX
4.4 4.499
3.98
4.30
0.001
0.17
±0.1
SN54HCT138 SN74HCT138
MIN
MAX
MIN
4.4
4.4
3.7
3.84
0.1
MAX
UNIT
V
0.26
0.1
0.4
0.1
0.33
±100
±1000
±1000
8
160
80
/LA
1.4
2.4
3.0
2.9
rnA
3
10
10
10
pF
V
nA
tThis is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or Vee.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
CD
en
tpd
tpd
tt
FROM
TO
IINPUT)
IOUTPUT)
A, B, or e
Enable
VCC
4.5
5.5
4.5
5.5
4.5
5.5
Any Y
Any Y
Any
V
V
V
V
V
V
Power dissipation capacitance
TA = 25°C
MIN
TYP MAX
MIN
MAX
MIN
MAX
23
36
54
45
17
32
49
34
22
33
50
42
18
30
45
38
12
11
15
14
22
19
17
No load, TA = 25°C
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-182
SN54HCT138 SN74HCT138
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
20
85 pF typ
UNIT
ns
ns
ns
SN54HC139, SN74HC139
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
D2684, DECEM8ER 1982- REVISED SEPTEM8ER 1987
•
•
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
SN54HC139 ..• J PACKAGE
SN74HC139 .•. ow OR N PACKAGE
(TOP VIEW)
Incorporates 2 Enable Inputs to Simplify
Cascading and/or Data Reception
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
Vee
1A
1B
1YO
1Y1
1Y2
1Y3
GND
2(3
2A
2B
2YO
2Y1
2Y2
2Y3
U)
SN54HC139 ... FK PACKAGE
(TOP VIEW)
description
The 'HC 139 circuit is designed to be used in
high-performance memory-decoding or datarouting applications requiring very short
propagation delay times. In high-performance
memory systems, this decoder can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of this
decoder and the enable time of the memory are
usually less than the typical access time of the
memory. This means that the effective system
delay introduced by the decoder is negligible.
The 'HC139 is comprised of two individual twoline to four-line decoders in a single package. The
active-low enable input can be used as a data
line in de multiplexing applications. These
decoders/demultiplexers feature fully buffered
inputs, each of which represents only one
normalized load to its driving circuit.
The SN54HC139 is characterized for operation
over the full military temperature range of
-55°C to 125 DC. The SN74HC139 is
characterized for operation from - 40 DC to
85°C.
PRODUCTlOIi DATA docum••ts •••,.i. i.formlli••
currant II of publication data. Products conform to
spacificationl per the tarms of r811. Instruments
:::=~~i~ai~:,~l~ ~=:~:; :'~D=::::t!~~
1G
nat
N
3
1Y1
2
C
1 20 19
4
18
5
6
17
7
15
(J)
o
:E
16
8
CJ
:I:
14
9 1011 1213
MQUMN
>-zz>->NN
..... <.9
NC - No internal connection
FUNCTION TABLE
INPUTS
(;
SELECT
A
B
H
X
L
ENABLE
OUTPUTS
YO
V1
V2
V3
X
H
H
H
H
L
L
L
H
H
H
L
L
H
H
L
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
L
Copyright © 1982, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-183
SN54HC139, SN74HC139
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
logic symbols (alternatives) t
XIV
lA (2)
lA (2)
(3)
•
lB
lVO
13)
2B
:::J:
(")
s:o
tThese symbols are in accordance with ANSI/lEEE Std 91-1984 and lEG Publication 617-12.
t/)
logic diagram (positive logic)
C
(II
<
c:r
ENABLE 10 (1)
(II
en
DATA
OUTPUTS
ENABLE
2G (15)
Pin numbers shown are for OW, J, and N packages.
2-184
TEXAS
.Jf
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54HC139, SN74HC139
DUAL 2-UNE TO 4-UNE DECODERS/DEMULTIPLEXERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . .. . . .. ± 20 rnA
Continuous output current, 10 (Vo = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 rnA
Continuous current through Vee or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC139
VIH High-level input voltage
Vee
Vee
Vee
VIL
Low-level input voltage
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
'>
Q)
SN74HC139
MIN
NOM
MAX
2
5
6
Vee Supply voltage
Vee
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
4.2
3.15
4.2
UNIT
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
0
Vee
0
Vee
V
0
Vee
1000
0
0
Vee
1000
V
tt
Input transition (rise and fall) times
ns
TA
Operating free-air temperature
0
500
0
500
0
400
400
-55
125
0
-40
85
::t:
V
Output voltage
Vee
~
o
Vo
0
fI)
o
V
Input voltage
=2V
= 4.5 V
=6V
Q
V
VI
Vee
Vee
en
Q)
U
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
Vec
2V
VI
=
VIH or VIL,
10H
=
-20
~A
VI
VI
VI
=
=
=
VIH or VIL.
VIH or VIL,
VIH or VIL,
10H
10H
10L
=
=
=
-4 mA
-5.2 mA
20 ~A
VOL
VI
II
lee
ej
4.5 V
6V
VOH
VI
iii
VI
= VIH or VIL, 10L = 4 mA
= VIH or VIL. 10L = 5.2 mA
= Vee or 0
= Vee or O. 10 = 0
TA = 25°C
TYP MAX
MIN
SN54HC139
MIN
MAX
SN74HC139
MIN
1.998
1.9
1.9
4.4 4.499
4.4
4.4
5.9
3.7
5.9
3.84
1.9
4.5 V
5.9
3.98
6V
5.48
5.999
4.30
5.2
5.80
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.4
0.4
0.33
0.33
V
6V
0.15
0.26
0.26
6V
±0.1
±100
±1000
± 1000
nA
8
160
80
10
10
10
p.A
pF
6V
2 to 6 V
TEXAS
3
'Ii1
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-185
SN54HC139, SN74HC139
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(lNPUTI
TO
(OUTPUTI
VCC
2V
tpd
tpd
tt
:t
n
o3:
tJ)
eCD
A or B
G
Y
TA = 25°C
MIN
TYP MAX
47
175
4.5V
6V
2V
y
4.5 V
6V
2V
Y
4.5 V
6V
Power dissipation capacitance per decoder
14
12
39
11
10
38
8
6
35
30
75
15
13
No load, TA = 25°C
<
c;'
CD
(I)
TEXAS
MIN
35
30
175
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-186
SN54HC139
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
MAX
SN74HC139
MIN
MAX
UNIT
255
51
44
255
51
44
220
44
ns
38
220
44
ns
110
22
95
19
16
19
38
25 pF typ
ns
SN54HCT139, SN74HCT139
DUAL 2-LlNE TO 4-LlNE DECODERS/DEMULTIPLEXERS
03274. MARCH 1989
SN54HCT139 ... J PACKAGE
SN74HCJ139 ... OW OR N PACKAGE
•
Inputs are TTL-Voltage Compatible
•
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
•
Incorporates 2 Enable Inputs to Simplify
Cascading andlor Data Reception
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
ITOP VIEW)
ITOPVIEW)
U
~I~ ~ ~)~
The 'HCT139 circuit is designed to be used in
high-performance memory-decoding or datarouting applications requiring very short
propagation delay times. In high-performance
memory systems, this decoder can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of this
decoder and the enable time of the memory are
usually less than the typical access time of the
memory. This means that the effective system
delay introduced by the decoder is negligible.
The 'HCT139 is comprised of two individual
two-line to four-line decoders in a single
package. The active-low enable input can be
used as a data line in demultiplexing applications.
These decoders/demultiplexers feature fully
buffered inputs, each of which represents only
one normalized load to its driving circuit.
3
2
1 20 19
9 1011 1213
MQUMN
>-22>->'1""""(,9
NN
NC - No internal connection
FUNCTION TABLE
INPUTS
ENABLE
The SN54HCT139 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HCT139 is
characterized for operation from -40°C to
85°C.
=-~~~r:'=-~:-·II-rilY
2<3
2A
2B
2YO
2Yl
2Y2
2Y3
SN54HCT139 ... FK PACKAGE
description
UNLESS OTHERWISE NOTED this ........t ••ntlli..
PRODUCTION DATA informotion c.rrant II 01
p.blir:oti•• dote. p _ confonn to IjIICificotiono
par tho tIr..1 01 Tu.. 1..........11 ItIIndlrd
Vee
1G
1A
1B
1YO
1Y1
1Y2
lY3
GND
G
H
L
L
L
L
SELECT
B
A
X
L
L
H
H
X
L
H
L
H
OUTPUT
YO
Yl
Y2
H
H
H
Y3
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
Copyright @ 1989, Texas Instruments Incorpora~ed
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-187
SN54HCT139. SN74HCT139
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
logic symbols (alternatives) t
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
logic diagram (positive logic)
lYO
ENABLE lG
~~l>it==;::~~:J
lYl
lY2
SELECT{1A
INPUTS
1 B =~Dc:>-"*<:n""",""--L...J
lY3
2YO
ENABLE 2G
2Yl
2Y2
'p
A
SELECT
INPUTS'l2B
...:..:.::.:....I>o-...CO-.....--l....J
2Y3
Pin numbers shown are for OW, J, and N packages.
2·188
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DATA
OUTPUTS
SN54HCT139, SN74HCT139
DUAL 2-LlNE TO 4-LlNE DECODERS/DEMULTIPLEXERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V
Input clamp current, 11K (V, < 0 or V, > Vee) ............................... "
±
Output clamp current, 10K (VO < 0 or Vo > Vee) ............................. ±
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package .. , .. , .........
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ...............
Storage temperature range ..................... " .................. -65°C to
to 7 V
20 mA
20 mA
25 mA
50 mA
300°C
260°C
150°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SN54HCT139
Supply voltage
VIH
High-level input voltage
Vil
VI
Low-level input voltage
Input voltage
Va
Output voltage
tt
Input transition (rise and fall) times
TA
Operating free-air temperature
II)
Q)
(,)
recommended operating conditions
Vee
II
I Vee = 4.5 V to
I Vee = 4.5 V to
MIN
NOM
4.5
5
SN74HCT139
MAX
.,5.5
MIN
NOM
MAX
4.5
5
5.5
0.8
0
0.8
V
0
Vee
0
Vee
V
0.::"
0
0
Vee
500
V
,J)'
Vee
500
ns
-55
125
-40
85
·e
5.5 V
2
5.5 V
0
.'
.::
':;Q)
c
en
o
UNIT
V
2
V
:E
CJ
::t
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
Val
TEST CONDITIONS
VI
VI
VI
VI
= VIH or Vil.
= VIH or Vil.
= VIH or Vil.
= VIH or Vil.
= Vee or 0
= vee or O.
10H
10H
10l
10l
VCC
=
= -4 rnA
= 20 ~A
= 4 rnA
-20
II
VI
lee
VI
10 = 0
One input at 0.5 V or 2.4 V.
Alee t
ei
Other inputs at 0 V or Vee
~A
4.5 V
4.5 V
4.5 V
TA - 25°C
MIN
TYP MAX
4.4 4.499
3.98
MIN
MAX
4.4
4.30
0.001
SN54HCT139
SN74HCT139
MIN
MAX
3.7
V
3.84
q..:1
0.1
0.1
4.5 V
0.17
0.26
,J).4
0.33
5.5 V
±0.1
±100
":4'000
±1000
1.4
2.4
3
10
5.5 V
5.5 V
4.5 to
5.5 V
8
<,
,;,>"
TEXAS . "
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
nA
160
80
pA
3.0
2.9
rnA
10
10
pF
tThis is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0
INSTRUMENTS
UNIT
4.4
V or Vee.
2-189
SN54HCT139, SN74HCT139
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
tpd
tpd
IE
tt
FROM
(INPUT)
A or B
G
TO
(OUTPUT)
Y
Y
Y
VCC
4.5 V
TA - 25°C
TVP MAX
MIN
14
34
5.5 V
12
30
4.5 V
5.5 V
11
34
10
30
4.5 V
8
15
5.5 V
6
14
Power dissipation capacitance per decoder
SN54HCT139 SN74HCT139
MIN
MA~
MIN
MAX
~
43
-*'50
A'" 51
50
~S'
40
S'
<{
No load, TA = 25°C
43
40
22
19
21
17
25 pF typ
NOTE 1: Load circuit and voltage waveforms are shown in Section 1 of the High-Speed CMOS Logic Data Book, 1988.
2-190
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
ns
ns
ns
SN54HC147, SN54HC148
SN74HC147, SN74HC148
10·LlNE TO 4·LlNE AND 8·LlNE TO 3·LlNE PRIORITY ENCODERS
02844. MARCH 1984-REVISEO
'HC147
•
Encodes 10·Line Decimal to 4·Line BCD
•
Applications Include:
Keyboard Encoding
Range Selection
4
VCC
5
NC
o
3
2
'HC148
•
•
•
•
1989
SN54HC147 ••. J PACKAGE
SN74HC147 ... N PACKAGE
(TOP VIEW)
Encodes B Data Lines to 3·Line Binary
(Octal)
B
fI
9
GNO~_-..:.....
Applications Include:
N-Bit Encoding
Code Converters and Generators
SN54HC147 ... FK PACKAGE
U)
(TOP VIEW)
U
CD
U
U
'S;
UU
w...,.z>z
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
3
CD
c
2 1 20 19
18
Dependable Texas Instruments Quality and
Reliability
en
o
16
15
7
8
14
t
:!
1
(,)
9 1011 1213
description
::J:
W
3
2 1 20 19
6
4
7
517
NC
EI
6
7
A2
8
18
16
15
NC
2
14
1
9 1011 1213
.... cuoo
«zz«
(!)
NC-No internal connection
PRODUCTION DATA .......1111 _in i.formlliaa
..rn.t .1 of p..llatlaa dolo. Prad.oII ...form to
I~.nl
.... 1iIa to.....f T.... Inotrunteftll
=.ri~~":.Ti =:~:; IIr=.:::.~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright @ 1989. Texas Instruments Incorporated
2-191
SN54HC147, SN54HC148
SN74HC147, SN74HC148
10·LlNE TO 4·LlNE AND 8·LlNE TO 3·LlNE PRIORITY ENCODERS
'HCl4B
FUNCTION TABLE
'HC147
FUNCTION TABLE
INPUTS
1
::r.:
n
S
oen
C
3
5
6
7
8
9
0
H
H
H
H
H
L
L
H
H
H
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
L
H
H
H
H
X
L
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
X
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
8
C
H
H
H
H
H
L
L
H
L
L
L
L
H
H
L
H
H
H
L
H
OUTPUTS
INPUTS
OUTPUTS
4
H
2
H
A
H
EI
0
1
2
3
4
5
6
7
H
X
X
X
X
X
X
X
X
L
H
L
H
L
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
H
H
H
L
H
H
L
H
L
H
L
L
X
X
X
X
X
L
L
L
X
X
X
X
L
X
X
X
L
H
L
H
H
X
X
L
X
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
A2 Al
H
H
H
H
L
L
L
L
L
AO GS EO
H
H
H
L
H H
L
H
L
H
L
H
H
H
L
H
H
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
L
L
L
H
H
H
L
L
H
H
-~
H = high logic level, L = low logic level, X = irrelevant
logic symbols t
CD
'HC147
<
'HCl48
(;'
HPRIIBCO
CD
en
HPRI/BIN
0
(10)
(11)
A
B
2
3
4
5
6
7
(12)
(13)
(1)
0/Z10
10
l/Z11
11
21Z12
12
3/Z13
13
4/Z14
14
5/Z15
15
(2)
(3)
(4)
6/Z16
16
7/Z17
17
V18
EI
(5)
EN"
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for OW, J, and N packages .
2-192
. TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
;;'1
18
(15) EO
SN54HC147, SN54HC14B
SN74HC147, SN74HC14B
10-LlNE TO 4-LlNE AND B-LlNE TO 3-LlNE PRIORITY ENCODERS
logic diagrams (positive logic)
'HC147
'HCl48
o (10)
(15) EO
FI
EI~---'=~D
Pin numbers shown are for OW, J, and N packages.
absolute maximum ratings over operating free-air temperature range t
Supply voltage, VCC ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package ........... , .. 260°C
Storage temperature range ......................................... - 65°C to 1 50°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-193
SN54HC147, SN54HC14B
SN74HC147, SN74HC14B
10·LlNE TO 4·LlNE AND B·LlNE TO 3·LlNE PRIORITY ENCODERS
recommended operating conditions
VIH High-level input voltage
II
Vee
=2V
= 4.5 V
=6V
Vee
Vee - 2 V
Vil low-level input voltage
Vee
Vee
SN74HC147
SN74HC148
MIN
NOM
MAX
2
5
6
Vee Supply voltage
Vee
SN54HC147
SN54HC148
NOM
MAX
2
5
6
1.5
1.5
3.15
4.2
3.15
4.2
= 4.5 V
=6V
UNIT
MIN
V
V
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
V
%
VI
Input voltage
0
Vee
0
Vee
V
s:o
Vo
Output voltage
0
Vee
1000
0
0
Vee
1000
V
ns
C')
Vee
Input transition (rise and fall! times
tt
en
cCD
<
ri"
CD
Vee
Vee
=2V
= 4.5 V
=6V
0
Operating free-air temperature
TA
0
500
0
500
0
400
0
400
-55
125
-40
85
°e
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
(I)
PARAMETER
TEST CONDITIONS
TA
VCC
2V
VI
=
VI
= VIH
= VIH
VI
1.9
1.998
1.9
1.9
4.4
5.9
4.4
3.7
3.84
4.5 V
or Vll,
IOH
-4 rnA
4.5 V
3.98
or Vll,
10H
=
=
6V
5.48
6V
-5.2 rnA
SN74HC147
SN74HC148
4.4 4.499
5.9 5.999
-20p.A
MAX
SN54HC147
SN54HC148
TYP
=
VOH
25°C
MIN
IOH
VIH or Vll,
=
4.30
5.80
MIN
MAX
MIN
5.9
5.2
V
5.34
2V
0.002
0.1
0.1
0.1
20 p.A
4.5 V
0.001
0.1
0.1
0.1
0.1
0.1
0.1
10l - 4 rnA
6V
4.5 V
0.001
VI - VIH or Vll,
0.17
0.26
0.4
0.33
VI = VIH or Vll,
VI - Vee or 0
10l
II
lee
VI
VI
=
VIH or Vll,
IOl
=
VOL
=
Vee or 0, 10
=
5.2 rnA
=0
V
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
160
80
p.A
3
8
10
10
10
pF
6V
2 to 6 V
ei
UNIT
MAX
'HC147 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL - 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(lNPUTI
(OUTPUTI
TO
Any
Any
Any
VCC
TA = 25°C
TYP MAX
MIN
MIN
MAX
SN74HC147
MIN
MAX
2V
75
190
285
4.5 V
38
57
240
48
6V
25
21
32
48
41
95
2V
28
75
110
4.5 V
8
15
22
19
6V
6
13
19
16
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-194
SN54HC147
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 65501 ~ • DALLAS, TEXAS 75265
UNIT
ns
ns
SN54HC147, SN54HC148
SN74HC147, SN74HC148
1a-LINE TO 4-LlNE AND 8-LlNE TO 3-LlNE PRIORITY ENCODERS
'HC148 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL - 50 pF (see Note 1)
FROM
UNPUT)
TO
(OUTPUT)
tpd
1-7
AO, A1, or A2
tpd
0-7
EO
tpd
0-7
GS
PARAMETER
tpd
EI
tpd
EI
GS
tpd
EI
EO
tt
AO, A1, or A2
Any
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
TYP MAX
69
180
23
36
21
31
150
60
20
30
17
26
75
190
25
38
21
32
78
195
26
39
22
33
57
145
19
29
16
25
66
165
22
33
28
19
28
75
15
8
6
13
SN54HC148
MIN MAX
270
54
46
225
45
38
285
57
48
295
59
50
220
44
38
250
50
43
110
22
19
SN74HC148
MIN MAX
225
45
38
190
38
33
240
48
41
245
49
42
180
36
31
205
41
35
95
19
16
UNIT
ns
ns
ns
II
en
CD
U
ns
"S
CD
c
ns
en
o
~
ns
U
::t
ns
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-195
SN54HC147, SN54HC14B
SN74HC147, SN74HC14B
1a-LINE TO 4-L1NEAND B-L1NE TO 3-L1NE PRIORITY ENCODERS
TYPICAL APPLICATION DATA
16-LINE DATA (ACTIVE LOW)
,~. . . . . . . . . . . . . . . .~A. . . . . . . . . . . . . . .~\
o
.1
2
3
4
5
6
7
8
8
9
10 11 12 13 14 15
•
ENABLE
(ACTIVE LOW)
'HC148
A1
A2
GS
J:
o
s:
-,
oen
C
I
'HCOB
_____ JI
(1)
<
n'
,---..
o
(1)
U)
2
3
PRIORITY FLAG
(ACTIVE LOW)
v~--~
ENCODED DATA (ACTIVE LOW)
______________.A................
16-LINE DATA (ACTIVE LOW)
~
~\
8
9
10 11 12 13 14 15
'HC148
ENABLE
(ACTIVE LOW)
'HC148
A1
A2
GS
--,
I
'HCOO
__ JI
'---..
o
2
3
PRIORITY FLAG
(ACTIVE HIGH)
v~--~
ENCODED DATA (ACTIVE HIGH)
PRIORITY ENCODER FOR 16 BITS
Since the 'HC147 and 'HC148 are combinational logic circuits, wrong addresses can appear during input
transients. Moreover, for the 'HC148, a change from high to low at input EI can cause a transient low
on the GS output when all inputs are high. This must be considered when strobing the outputs.
2-196
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54HC151, SN74HC151
8·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
DECEMBER 19B2-REVISED SEPTEMBER 19B7
•
•
•
SNS4HC1Sl ... J PACKAGE
SN74HC1Sl ... D OR N PACKAGE
8·Line to 1·Line Multiplexers Can
Perform as:
Boolean Function Generators
Parallel-to-Serial Converters
Data Source Selectors
(TOP VIEW)
Vee
03
02
01
00
Package Options Include Both Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-Mil
DIPs
04
05
06
07
y
W
A
B
G
Dependable Texas Instruments Quality and
Reliability
GNO
C
In
description
Q)
SN54HC1Sl ... FK PACKAGE
These monolithic data selectors/multiplexers
provide full binary decoding to select one of eight
data sources. The strobe input (G) must be at
a low logic level to enable the inputs. A high level
at the strobe terminal forces the W output high
and the Y output low.
'S;
U
NMU UCl
c
3
The SN54HC151 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC151 is
characterized for operation from - 40°C to
U
(TOP VIEW)
2
Q)
en
1 20 19
4
18
5
17
6
16
7
15
8
14
o
:!:
(.)
::x:
9 1011 12 13
85°C.
FUNCTION TABLE
NC - No internal connection
INPUTS
SELECT
OUTPUTS
STROBE
y
W
logic symbol t
C
8
A
G
X
X
X
H
L
H
L
L
L
L
DO
i'iO
G
MUX
L
L
H
L
01
151
A
L
H
L
L
02
02
8
L
H
H
L
03
53
C
H
L
L
L
04
04
DO
H
L
H
L
05
05
Dl
H
H
L
L
06
06
D2
H
H
H
L
07
07
D3
D4
H = high level, L = low level, X = irrelevant
D0, 01 ... 07
= the
D5
level of the 0 respective input
06
D7
(11)
(10)
(9)
:}G~
(4)
0
(3)
(2)
2
(1)
(15)
(14)
(13)
(12)
(5)
y
W
3
4
5
6
7
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
PROOUCTIOI DATA d..uml.ts .0.lIIi. infermotio.
••mIIIl .. of ,ubl(ellia. dIto. P,d.ets conform III
lpoeificotio•• , . dol III.... of TIlIII I.....m.ots
=i~i:'':.7i =~:; lIr;:!:':t::." nit
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright @ 1982. Texas Instruments Incorporated
2-197
SN54HC151, SN74HC151
B·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
logic diagram (positive logic)
G (7)
A
B
C
!!!!t>o-.-rD
v
v
(10)
(9)
et
1SJ
t
II
::c
0
s:
0
en
0
00
01
CD
<
(;'
02
CD
en
03
D4
05
D6
07
(4)
(3)
(1)
(15)
(14)
'"
~
-'"
'7
L
~
(13)
T~
~
(12)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
v
H>~ w
~
Pin numbers shown are for D, J, and N packages.
2-198
~ ~
T~
IT
'"v
(
16
~ ~ ~ ~
9
(2)
t ~ ~
[§J-
SN54HC151, SN74HC151
B-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±35 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300 DC
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ............... 260 DC
Storage temperature range ......................................... - 65 DC to 150 DC
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
fI
en
CD
U
oS
recommended operating conditions
SN54HC151
MIN NOM MAX
Vee Supply voltage
High-level input voltage
Vee
Vee
VIL
Low-level input voltage
Vee
Vee
Vee
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
VIH
Vee
Vee
Vee
Vee
2
1.5
3.15
4.2
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
0.3
0.9
1.2
0
0
Vee
Vee
1000
0
0
0
=2V
= 4.5 V
=6V
6
2
1.5
3.15
5
6
CD
UNIT
C
V
UJ
o
:E
V
(J
4.2
0
0
0
-55
Operating free-air temperature
TA
5
SN74HC151
MIN NOM MAX
0
0
0.3
0.9
0
0
1.2
0
0
500
0
400
125
0
-40
::t
V
Vee
Vee
1000
V
V
500
400
ns
85
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
0.1
0.1
0.26
0.26
=
VIH or VIL.
IOH
=
-20 pA
VI
VI
=
=
VIH or VIL,
VIH or VIL.
IOH
IOH
=
=
-6 rnA
-7.8 rnA
VI
=
VIH or VIL.
IOL
=
20 ~A
6V
2V
4.5 V
VI
VI
VI
VI
=
=
=
=
VIH or VIL.
VIH or VIL.
Vee or 0
Vee or 0,
IOL
IOL
=
=
6 rnA
7.8 rnA
6V
4.5 V
6V
0.001
0.17
0.15
=0
6V
6V
2 to 6 V
±0.1
10
VOL
lee
ej
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.48
5.80
0.002
0.001
VI
VOH
II
2V
4.5 V
6V
4.5 V
TA - 25°C
MIN
TYP MAX
TEXAS
3
SN54HC151
MIN MAX
1.9
4.4
5.9
3.7
5.2
0.1
±100
8
10
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74HC151
MIN MAX
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
UNIT
V
0.1
0.1
0.4
0.4
±1000
0.1
0.33
0.33
±1000
V
nA
160
10
80
10
pA
pF
2-199
SN54HC151, SN74HC151
8·UNE TO l·UNE DATA SELECTORS/MULTIPLEXERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
tpd
II
tpd
tpd
l:
FROM
IINPUT)
A, B, or C
Any 0
~
TO
(OUTPUT)
YorW
YorW
YorW
o
s:o
tt
t/)
cCD
<
(;'
CD
(I)
VCC
TA - 2SoC
MIN
TYP MAX
SN54HC1Sl
MIN
MAX
SN74HC1Sl
MIN
MAX
250
360
312
30
50
73
63
25
43
62
54
74
195
283
244
23
39
57
49
6V
20
33
48
41
2V
94
4.5 V
6V
2V
4.5 V
2V
49
127
185
159
4.5 V
15
25
37
32
BV
13
22
28
95
2V
22
75
32
110
4.5 V
9
15
22
19
6V
8
13
19
16
Power dissipation capacitance
No load, TA = 25°C
UNIT
no
no
no
no
70 pF typ
I
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 150 pF (see Note 1)
PARAMETER
tpd
tpd
tpd
tt
FROM
IINPUT)
A, B, or C
Any 0
~
TO
(OUTPUT)
YorW
YorW
YorW
VCC
TA - 25°C
MIN
TYP MAX
MIN
MAX
SN74HC151
MIN
MAX
440
70
525
105
59
89
76
2V
107
350
4.5 V
33
6V
30
88
2V
90
275
415
345
4.5 V
29
51
83
69
6V
25
47
72
310
62
53
315
63
53
59
2V
67
205
4.5 V
21
41
6V
18
35
2V
51
210
4.5 V
16
42
6V
14
36
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-200
SN54HC151
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
UNIT
no
no
255
51
no
43
265
53
45
no
SN54HC152. SN14HC152
B-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS
02684, DECEM8ER 1982-REVISEO SEPTEMBER 1987
SN54HC152 ... J PACKAGE
SN74HC152 ... 0 OR N PACKAGE
•
Selects One-ot-Eight Data Sources
•
Performs Parallel-to-Serial Conversion
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
ITOP VIEW)
04
03
02
01
00
Dependable Texas Instruments Quality and
Reliability
VCC
05
06
07
W
A
B
GNO
C
•
description
SN54HC1S2 ... FK PACKAGE
These monolithic data selectors/multiplexers
contain full on-chip binary decoding to select the
desired one-of-eight data sources.
M '
OOZ>O
The SN54HC152 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC152 is
characterized for operation from - 40°C to
SELECT
CI)
ITOPVIEW)
NC-No internal connection
=
low level
logic symbol t
A (101
8 (91
C 181
(51
00 (41
~~
(31
(21
03
(1)
04
(131
~:
2
161 W
3
1121
07 (111
t This
symbol is in accordance with ANSI/IEEE Std 91- 1984 and
lEe Publication 617-12.
Pin numbers shown are for D, J, and N packages.
Copyright @ 1982, Texas Instruments Incorporated
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 •
DAL~S.
TEXAS 7526S
2-201
SN54HC152, SN74HC15Z
B·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
logic diagram (positive logic)
A
B
C
•
(10)
(9)
(8)
::J:
00
0
'0"
CD
01
<
02
en
03
n'
CD
1
U
t t t
(')
s:
I
04
05
06
07
(5)
(4)
(3)
1
9
I
u
"
"
~ ~ ~ ~ ~ ~ ~
~
9
(2)
L:?
(1)
(13)
~w
9
9
(12)
L:?
(11)
Pin numbers shown are for D. J. and N packages.
2-202
""
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
§-
SN54HC152, SN74HC152
B·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K (Vo < 0 or Vo > Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) ............................... , ± 35 rnA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package. . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ............... 260°C
Storage temperature range ......................................... - 65 DC to 150 DC
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
fI
recommended operating conditions
SN54HC152
MIN NOM MAX
Vee Supply voltage
2
1.5
3.15
4.2
Vee - 2 V
Vee = 4.5 V
VIH High-level input voltage
Vee = 6 V
Vil
Vee = 2 V
Vee = 4.5 V
Low-level input voltage
Input voltage
Output voltage
tt
Input transition (rise and fall) times
Vee = 2V
Vee = 4.5 V
Vee = 6 V
TA
Operating free-air temperature
6
UNIT
V
V
4.2
0
0.3
0
0.9
1.2
0
0
0
Vee = 6 V
VI
Vo
5
SN74HC152
MIN NOM MAX
2
5
6
1.5
3.15
0
0
Vee
Vee
1000
500
0
-55
400
125
0.3
0
0
0
0
0
0
0
0
-40
0.9
1.2
V
Vee
Vee
1000
V
V
500
400
ns
85
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
VI = VIH or Vll,
10H = -20 p.A
VI = VIH or Vll,
VI = VIH or Vil.
10H = -6 rnA
10H = -7.8 rnA
2V
4.5 V
6V
4.5 V
6V
VI = VIH or Vil.
10l = 20 p.A
2V
4.5 V
VI = VIH or Vil.
VI = VIH or Vll,
10l = 6 rnA
10L = 7.8 rnA
6V
4.5 V
6V
VOH
VOL
II
lee
ei
VI = Vee or 0
VI ~ Vee or O. 10 - 0
TA = 25°C
TYP MAX
MIN
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.48
5.80
0.002
0.001
0.001
0.17
0.15
6V
6V
2 to 6 V
SN54HC152
MIN
1.9
MAX
4.4
5.9
3.7
5.2
0.1
0.1
SN74HC152
MIN
1.9
4.4
5.9
MAX
UNIT
V
3.84
5.34
0.1
0.1
0.1
0.1
0.1
0.1
V
0.4
0.4
0.33
0.33
±0.1
0.1
0.26
0.26
±100
±1000
±1000
nA
160
10
80
10
~A
3
8
10
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
pF
2-203
SN54HC162,SN74HC152
B·L1NE TO 1·L1NE DATA SELECTORS/MULTIPLEXERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
FROM
(INPUTI
TO
(OUTPUT)
tpd
A,B,orC
W
tpd
Any 0
W
PARAMETER
::t
Vcc
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
W
tt
n
s:o
tn
o
CD
<
(i.
CD
I
Cpd
Power dissipation capacitance
TA = 25°C
MIN
TYP MAX
170
50
1B
34
16
29
130
38
14
26
12
22
20
60
12
8
6
10
SN54HC152
MIN MAX
255
51
43
195
39
33
90
18
15
No load, T A = 25°C
SN74HC152
MIN MAX
213
43
36
163
33
28
75
15
13
UNIT
ns
ns
ns
70 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
(I)
tpd
A, B, or C
W
tpd
Any 0
W
tt
2V
4.5 V
6V
2V
4.5V
6V
2V
4.5 V.
6V
W
=
TA
25°C
TYP MAX
MIN
225
63
22
51
19
44
215
52
18
43
16
37
45
210
17
42
13
36
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-204
.
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC152
MIN MAX
385
77
66
325
65
55
315
63
53
SN74HC152
MIN MAX
318
64
55
268
54
47
265
53
45
UNIT
ns
ns
ns
SN54HC153. SN74HC153
DUAL 4-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS
02684, DECEMBER 1982-REVISED SEPTEMBER 1987
•
Permits Multiplexing from N Lines to 1 Line
•
Performs Parallel-to-Serial Conversion
•
Strobe (Enable) Line Provided for Cascading
(N lines to n lines)
SN54HC153 .•. J PACKAGE
SN74HC153 •.• D/DWt DR N PACKAGE
(TOP VIEW)
1(3
lC3
lC2
lCl
lCO
lY
GND
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
•
VCC
2<3
B
Dependable Texas Instruments Quality and
Reliability
A
2C3
2C2
2Cl
2CO
2Y
•
SN54HC153 ... FK PACKAGE
description
(TOP VIEW)
Each of these data selectors/multiplexers
contains inverters and drivers to supply full
binary decoding data selection to the AND-OR
gates. Separate strobe inputs (3) are provided
for each of the two four-line sections.
Ie.:> U
U
UIc.:>
CO ..... Z>N
3
lC2
The SN54HC153 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC153 is
characterized for operation from - 40°C to
85°C.
2
1 2019
4
18
A
5
17
6
16
2C3
NC
2C2
2Cl
7
15
8
14
9 1011 12 13
>- cu>-a
ZZNU
e.:>
N
FUNCTION TABLE
NC-No internal connection
SELECT
DATA INPUTS
INPUTS
STROBE
OUTPUT
tContact the factory for 0 or OW availability.
B
A
co
Cl
C2
C3
G
y
X
X
X
X
X
X
H
L
L
L
L
X
X
X
L
L
L
L
H
X
X
X
L
H
L
H
X
L
X
X
L
L
A
L
H
X
H
X
X
L
H
B
H
L
X
X
L
X
L
L
H
L
X
X
H
X
L
H
H
H
X
X
X
L
L
L
H
H
X
X
X
H
L
H
logic symbol*
(7)1Y
Select inputs A and B are common to both sections.
H = high level, L = low level, X = irrelevant
2CO
2Cl (11)
2C2 (12)
2C3 (13)
(9) 2Y
*This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for O/DW, J, and N packages.
PRODUCTION DATA doc.ments contain Information
currant as of publication data. Products conform to
spacifications par the tarms of T8X88 Instruments
~~~:~:~~i~ai~:I~~i =::i~n :,~a::;::::.::s not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DAL.LAS. TEXAS 75265
Copyright © 1982, Texas Instruments Incorporated
2-205
SN54HC153. SN74HC153
DUAL 4·L1NE TO 1·L1NE DATA SELECTORS/MULTIPLEXERS
logic diagram (positive logic)
A
a..::;.:----+----+---I
1G~----+_---+----~----+_-_,
•
::r:::
n
s::
ot/)
cCD
<
C:;'
CD
US
Pin numbers shown are for O/OWt. J. and N packages.
t Contact the factory for 0 or OW availability.
2-206
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC153. SN74HC153
DUAL 4-UNE TO 1-UNE DATA SELECTORS/MULTIPLEXERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (V, < 0 or V, > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (VO < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300 DC
lead temperature 1,6 mm (1/16 in) from case for 10 s: D/DW or N package . . . . . . . . . . .. 260 DC
Storage temperature range ......................................... - 65 DC to 150 DC
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
•
(I)
CD
(J
recommended operating conditions
'S
SN54HC153
MIN NOM MAX
Vee Supply voltage
vee
Vec
VIH High-level input voltage
VIL
Low-level input voltage
VI
Vo
Input voltage
Output voltage
tt
Input transition Irise and fall I times
Vee
Vec
Vee
5
6
3.15
4.2
Vee
Vee - 2 V
Vee = 4.5 V
Vee
TA
2
1.5
=2V
= 4.5 V
=6V
0
0
0
0
=6V
0
0
0
=2V
= 4.5 V
=6V
Operating free-air temperature
2
1.5
3.15
4.2
5
6
CD
C
UNIT
CI.)
V
o
::ii!
V
0.3
0.9
1.2
0
0
0
0.3
0.9
1.2
V
Vee
Vee
1000
0
0
Vec
Vee
1000
V
V
500
400
ns
85
·e
500
400
125
0
-55
SN74HC153
MIN NOM MAX
0
0
0
-40
o
:z::
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI = VIH or VIL.
VCC
IOH
=
-20
-6 mA
-7.8 mA
~A
VOH
VI
VI
= VIH
= VIH
or VIL.
or VIL.
10H
10H
=
=
VI
= VIH
or VIL.
10L
= 20~
VI
VI
VI
= VIH or VIL.
= VIH or VIL.
= Vee or 0
10L
10L
= 6 mA
= 7.8 mA
VOL
II
lee
ei
VI - Vee or O. 10 - 0
2V
4.5 V
6V
4.5 V
6V
2V
4.5 V
TA - 25°e
TYP MAX
MIN
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.80
5.48
6V
4.5 V
6V
6V
MIN
1.9
4.4
MAX
5.9
3.7
5.2
SN74HC153
MIN MAX
1.9
4.4
5.9
3.84
5.34
UNIT
V
0.002
0.001
0.1
0.1
0.1
0.1
0.1
0.1
0.001
0.17
0.15
0.1
0.26
0.26
±100
0.1
0.4
0.4
±1000
0.1
0.33
0.33
±1000
nA
8
160
80
~A
10
10
10
of
±0.1
6V
2 to 6 V
TEXAS
SN54HC153
3
-I.!}
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V
2-207
SN54HC153, SN74HC153
DUAL 4-UNE TO 1-UNE DATA SELECTORS/MULTIPLEXERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
tpd
tpd
tpd
FROM
(INPUT)
TO
(OUTPUT)
Vce
2V
90
150
225
A or B
Y
4.5 V
21
30
45
38
6V
26
126
38
189
32
2V
17
73
158
4.5 V
17
28
42
35
6V
14
23
35
29
Data
(Any C)
G
y
y
Y
tt
TA - 25 G e
MIN
TYP MAX
SN54HC153
MIN
MAX
SN74HC153
MIN
MAX
190
2V
38
95
150
125
4.5 V
11
19
28
24
6V
2V
9
20
16
60
24
90
20
75
4.5 V
8
12
18
15
6V
6
10
15
13
Power dissipation capacitance per multiplexer
UNIT
ns
ns
ns
ns
40 pF typ
No load, TA = 25°C
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 150 pF (see Note 1)
PARAMETER
tpd
tpo
tpd
tt
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
Data
(Any C)
y
G
Y
Y
Vee
TA - 25 G e
MIN
TYP MAX
MIN
MAX
SN74HC153
MIN
MAX
2V
105
235
355
295
4.5 V
6V
27
21
47
41
71
59
60
51
274
2V
93
220
335
4.5 V
23
44
67
55
6V
19
38
57
48
2V
60
185
280
230
4.5 V
17
37
56
6V
14
32
48
46
40
265
2V
45
210
315
4.5 V
17
42
63
53
6V
13
36
53
45
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-208
SN54HC153
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
SN54HC154, SN74HC154
4-LlNE TO 16-LlNE DECODERS/DEMULTIPLEXERS
02684, DECEM8ER 1982-REVISED SEPTEMBER 1987
SN54HC154 ... JT PACKAGE
SN74HC154 ... OW DR NT PACKAGE
•
Decodes 4 Binary-Coded Inputs into One of
16 Mutually Exclusive Outputs
•
Performs the Demultiplexing Function by
Distributing Data From One Input to Any
One of 16 Outputs
0
Vec
2
A
B
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
3
4
5
C
6
131
15
14
13
12
11
(TOP VIEW)
•
•
0
<32
7
8
9
Dependable Texas Instruments Quality and
Reliability
10
GND
description
Each of these monolithic. 4-line to 16-line
decoders decodes four binary-coded inputs into
one of sixteen mutually exclusive outputs when
both the strobe inputs. G 1 and G2. are low, The
demultiplexing function is performed by using
the 4 input lines to address the output line.
passing data from one of the strobe inputs with
the other strobe input low. When either strobe
input is high. all outputs are high. These
demultiplexers are ideally suited for
implementing high-performance memory
decoders.
The SN54HC154 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC154 is
characterized for operation from - 40°C to
85°C.
II
U)
Q)
(,)
"S
Q)
o
(fJ
o
SNS4HC1S4 ... FK PACKAGE
(TOP VIEW)
U
u u
:i
N_OZ> Vee) .................................. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) .............................. ± 20 mA
Continuous output current, 10 (Vo = 0 to Vee) ................................. ± 25 mA
Continuous current through Vee or GNO pins ................................... ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or JT package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or NT package .............. 260°C
Storage temperature range .......................................... - 65°C to 150°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute·maximum·rated conditions for extended periods may affect device reliability.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-211
SN54HC154, SN74HC154
4·LlNe TO 16·LlNE DECODERSIDEMULTIPLEXERS
recommended operating conditions
SN54HCl54
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0
0.3
0
0.9
1.2
0
0
Vee
0
Vee
0
1000
0
500
400
0
-55
125
Vee Supply voltage
•
:J:
(')
3:
oen
i<
C:)'
CD
Vee
Vee
Vee
Vee
Vee
Vee
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
TA
Operating free-air temperature
=2V
= 4.5 V
=6 V
=2 V
= 4.5 V
=6 V
Vee - 2 V
Vee = 4.5 V
Vee = 6 V
SN74HCl54
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0
0.3
0.9
0
1.2
0
0
Vee
0
Vee
0
1000
0
500
0
400
-40
85
UNIT
V
V
V
V
V
ns
°C
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
til
VI
= VIH or VIL,
10H
= - 20 ~A
VOH
VI = VIH or VIL, 10H = -4 mA
5.2 mA
VI - VIH or VIL, 10H VI
= VIH or VIL,
10L = 20 ~A
VOL
II
lee
ei
VI - VIH or VIL, 10L - 4 mA
VI = VIH or VIL, 10L = 5.2 mA
VI - Vee orO
VI - Vee or 0, 10 - 0
TA - 25°C
MIN
TVP MAX
1.9 1.998
2V
4.5 V
4.4 4.499
6V
5.9 5.999
4.5 V 3.98 4.30
6V 5.48 5.80
2V
0.002
0.1
4.5 V
0.001
0.1
0.001
6V
0.1
4.5 V
0.17 0.26
0.15 0.26
6V
6V
±0.1 ±100
6V
8
2 to 6 V
10
3
VCC
SN54HC164
MIN MAX
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
160
10
SN74HC1S4
MIN MAX
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
80
10
UNIT
V
V
nA
p.A
pF
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
tpd
A, S, e, or 0
Any
tpd
GlorG2
Any
tt
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN TVP MAX
180
72
24
38
20
31
180
72
24
36
31
20
28
75
15
8
13
6
Power dissipation capacitance
No load, TA = 25°e
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-212
TEXAS
SN54HCl54
MIN MAX
270
54
46
270
54
46
110
22
19
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN74HCl54
MIN MAX
225
45
38
225
45
38
95
19
16
96 pF typ
UNIT
ns
ns
ns
SN54HC157, SN54HC158, SN74HC157, SN74HC158
QUADRUPLE 2-UNE TO 1-UNE DATA SELECTORS/MULTIPLEXERS
D2684. DECEMBER 1982-REVISED JUNE 1989
•
SN54HC157, SN54HC158 ... J PACKAGE
SN74HC167, SN7~CI58 ... Dt OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
(TOP VIEW)
vee
AlB
description
These monolithic data selectors/multiplexers
contain inverters and drivers to supply full data
selection to the four output gates. A separate
strobe input (<3) is provided. A 4-bit word is
selected from one of two sources and is routed
to the four DutputS. The 'HC157 presents true
data whereas the 'HC 158 presents inverted
data.
G
1A
1B
1Y
2A
2B
2Y
Dependable Texas Instruments Quality and
Reliability
4A
4B
4Y
3A
3B
3Y
GND
SN54HC157, SN54HC158 ... FK PACKAGE
(TOP VIEW)
«~u
~I« z
3
The SN54HC157 and SN54HC158 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HC157 and SN74HC158 are characterized
for operation from - 40°C to 85 DC.
2
tl
>I(!)
1 20 19
18
5
17
6
16
15
14
FUNCTION TABLE
INPUTS
H
OUTPUT Y
STROBE
SELECT
G
AlB
A
B
H
X
X
L
L
L
L
L
H
X
X
X
H
L
L
H
L
L
H
L
H
X
X
H
H
L
=
high level, L
= low
DATA
level, X
=
'HC157
'HC158
L
H
NC-No internal connection
H
L
t Contact the factory for D availability
irrelevant
logic symbols:!:
'HC1S8
'HC157
(4) 1Y
(7) 2Y
(9) 3Y
(12) 4Y
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
PRODUCTION DATA documant. cantain infarmatian
.u,rent .1 of publlCltia. data. Products co.larm to
lIIacifiCltia.1 por th. t..... of T.1II1 1.II'.....ta
:.=~i~.r::I~~i ~::\:~i:: :.:":!~~9t:~ .at
Copyright @) 1989, Texas Instruments Incorporated
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 855012 • DALLAS, TEXAS 76265
2-213
SN54HC157, SN54HC158, SN74HC157, SN74HC158
QUADRUPLE 2·UNE TO 1·UNE DATA SELECTORS/MULTIPLEXERS
logic diagrams (positive logic)
'HC157
lA
lB
•
2A
2B
::E:
(")
3A
0
3B
s:
en
(2)
(3)
(5)
(6)
(11)
(10)
4A (14)
0
(1)
<
4B
5'
(1)
en
STROBEG
SELECT AlB
(13)
(15)
(1)
'HC15B
lA (2)
lB (3)
2A (5)
2B (6)
3A (11)
3B (10)
4A (14)
4B (13)
STROBE
or-,
G ...;.(1...;.5.;..)- - - 1.......
SELECT AlB "':"(l,",")-+--+---a
Pin numbers shown are for D, J, and N packages.
2-214
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC157, SN54HC158, SN74HC157, SN74HC158
QUADRUPLE 2·UNE TO 1·UNE DATA SELECTORS/MULTIPLEXERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
U
.S;
VIH
High-level input voltage
Vee
Vee
Vee
VIL
Low-level input voltage
VI
Vo
Input voltage
Output voltage
It
Input transition (rise and fall) times
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Vee
= 4.5 V
=6V
Operating free-air temperature
TA
SN74HC157
SN54HC158
SN74HC158
Q)
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
UNIT
C
V
o
(/)
1.5
1.5
3.15
3.15
4.2
4.2
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
0
Vee
0
Vee
0
0
0
Vee
1000
Vee
1000
0
500
0
500
0
-55
400
0
-40
400
125
:li:
V
0
Vee - 2 V
Vee
SN54HC157
MIN
Vee Supply voltage
Vee
Vee
en
Q)
recommended operating conditions
0
85
(.)
X
V
V
V
ns
'e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted I
PARAMETER
TEST CONDITIONS
TA - 25'C
VCC
MIN
VI = VIH or VIL. 10H
=
2V
4.5 V
~A
-20
6V
VOH
VI - VIH or VIL. 10H -
-6 mA
VI - VIH or VIL, 10H -
- 7.8 mA
VI = VIH or VIL. IOL
=
20 ~A
VOL
VI
=
VIH or VIL. IOL
VI = VIH or VIL. 10L
II
VI - Vee or 0
lee
ei
VI
=
=
=
6 rnA
7.8 rnA
Vee or O. 10 = 0
TYP
MAX
1.9 1.998
SN74HC158
MIN
MAX
MIN
5.9 5.999
5.9
5.9
3.7
3.84
4.5 V
3.98
6V
5.48
4.30
5.80
UNIT
MAX
1.9
1.9
4.4
4.4
5.2
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
6V
0.001
0.1
0.1
0.1
0.1
0.1
4.5 V
0.17
0.26
0.26
0.4
0.4 .
V
0.33
6V
0.15
6V
±0.1 ±100
±1000
±1000
nA
6V
8
160
80
~A
10
10
10
pE
TEXAS
3
~
INSTRUMENTS
O~FICE
SN74HC157
SN54HC158
4.4 4.499
2 to 6 V
POST
SN54HC157
BOX 655012 • DALLAS. TEXAS 75265
0.33
2-215
SN54HC157, SN54HC158, SN74HC157, SN74HC158
QUADRUPLE 2·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM !INPUT)
vcc
TO (OUTPUT)
TA - 25°C
MIN
Ipd
A or B
V
Ipd
A/8
y
n
tpd
G
y
oen
II
::z:::
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
3i:
Y
TVP
MAX
63
13
11
67
18
14
59
16
13
28
8
6
125
25
21
125
25
21
115
23
20
60
12
10
SN54HC157
SN54HC158
MIN
MAX
SN74HC157
SN74HC158
MIN
190
38
32
190
38
32
170
34
29
90
18
15
UNIT
MAX
160
32
27
160
31
27
145
29
25
75
15
13
ns
ns
ns
ns
C
CD
<
5"
CD
en
40 pF Iyp
No load, TA = 25°C
Power dissipation capacitance
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM !INPUT)
TO (OUTPUT)
VCC
TA - 25°C
MIN
Ipd
A or 8
y
Ipd
AlB
y
tpd
G
y
II
Y
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TVP
MAX
81
23
18
81
23
18
91
24
18
45
190
38
33
210
42
36
190
38
33
210
42
36
17
13
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2·216
TEXAS •
INSTRUMENTS
POST OFFICE BOX 855012 .. DALLAS, TeXAS 75265
SN54HC157
SN54HC158
MIN
MAX
290
58
49
320
64
54
290
58
49
315
63
53
SN74HC157
SN74HC158
MIN
UNIT
MAX
235
47
41
260
52
45
235
47
41
265
53
45
ns
ns
ns
ns
SN54HC160 THRU SN54HC163
SN74HC160 THRU SN74HC163
SYNCHRONOUS 4·BIT DECADE AND BINARY COUNTERS
02684. DECEMBER 1982 - REVISED SEPTEMBER 1987
•
Internal Look Ahead for Fast Counting
•
Carry Output for N·Bit Cascading
•
Synchronous Counting
•
Synchronously Programmable
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300·mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC' ... J PACKAGE
SN74HC' ... 0 OR N PACKAGE
(TOP VIEW)
CLR
eLK
A
B
C
D
ENP
GND
Vee
RCa
°A
OB
Oc
OD
ENT
LOAD
SN54HC' ... FK PACKAGE
(TOP VIEW)
description
"leI:
UO
...J....J U
uu
UU2>eI:
These synchronous. presettable counters feature
an internal carry look-ahead for application in
high-speed counting designs. The 'HC160 and
'HC162 are decade counters, and the 'HC16l
and 'HC163 are 4-bit binary counters.
Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the
outputs change coincident with each other when
so instructed by the count-enable inputs and
internal gating. This mode of operation
eliminates the output counting spikes that are
normally associated with synchronous (ripple
clock) counters. A buffered clock input triggers
the four flip-flops on the rising (positive-going)
edge of the clock input waveform.
3
2
1 20 19
A
4
18
B
NC
e
D
5
17
6
16
7
15
8
14
OA
OB
NC
Oe
OD
9 1011 12 13
o..oUI°f222--~--__,
ENT
ENP
CLK
-=-+---1 )o---:!r\J~~
A
(31
a
(41
C
(51
o
(61
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
*For the sake of simplicity, the routing of the complementary signals iJ5 and CK is not shown on this overall logic diagram. The uses
of these signals are shown on the logic diagram of the OfT flip-flops.
Pin numbers shown are for D. J, and N packages.
2-220
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC160 THRU SN54HC163
SN74HC160 THRU SN74HC163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
logic symbol, each OfT flip-flop (positive logic)
LD (LOAD)
M1
TE (TOGGLE ENABLE)
G2
CK (CLOCK)
L
;,2T/1C3
Q
(OUTPUT)
G4
o (INVERTED DATAl
3D
R (INVERTED RESETl
4R
II
logic diagram, each OfT flip-flop (positive logic)
CK---------------.---~------_.~-~
LD-------,
TE---~
....--+-~ >-.....-
Q
j])t
D -_ _..J
CRt
R-------r------------~
t The origins of the signals
ill and
CK are shown in the logic diagrams of the overall devices.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-221
SN54HC160, SN54HC162
SN74HC160, SN74HC162
SYNCHRONOUS 4·81T DECADE COUNTERS
'HC160 and 'HC162 output sequence
Illustrated below is the following sequence:
1. Clear outputs to zero (SN54HC160 and SN74HC160 are asynchronous; SN54HC162 and
SN74HC162 are synchronous)
2. Preset to BCD seven
3. Count to eight, nine, zero, one, two, and three
4. Inhibit
II
CIR~
s:0
en
C
U
i:OAD
::r:
(")
A-.J
DATA
INPUTS
CD
B-.J
c-.J
<
5'
CD
en
L=
c=
c=
-,
I--
D
ClK
ENP
,
..._______
ENT ____~--~--~:rl--~------------------~~--------_,
,
I
--
--,
-,
-.2 _,
-
--, -,
QA __
I
,
I
I
,
OUTPUTS
Qc
=
I
-/
,
,----,
,
QB_ -.2 _I~
I
'
,
I~_ _ _ _ _ _~
,
,
_'---.II,~------------------~---------------------
i
I
- -, -1
,
I
'f------.
QD_ - - I - I
I
I
:
I
RCO
r--1
I
I
I
I
I
----~I--~:~--:~7--~i8--~9
~O--~--~2~-=3+:--------------------I
I
II
I
I
14141----COUNT ---"~144t----INHIBIT
SYNC PRESET
ASYNCClEAR
CLEAR
2-222
TEXAS . .
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
-----+~
SN54HC161, SN54HC163
SN74HC160, SN74HC163
SYNCHRONOUS 4·BIT BINARY COUNTERS
'HC161 and 'HC163 output sequence
Illustrated below is the following sequence:
1. Clear outputs to zero (SN54HC161 and SN74HC161 are asynchronous; SN54HC163 and
SN74HC163 are synchronous)
2. Preset to binary twelve
3. Count to thirteen, fourteen, zero, one, and two
4. Inhibit
II
CLR~
I
I
r.oAi5
U
I
I
I
A
Q)
U
-I---
I
's:
I
Q)
1--
B
DATA
INPUTS
II)
1--
c.J
I
1_-
D.J
1_-
I
C
en
0
:E
-
(,)
J:
CLK
I
:I
ENP
I
I
I
ENT
I
II
I
,I
°A
°B -_
-, -,I
-.!
_I
--,
-2 - ,I'_ _
OUTPUTS
~,_
_ _~
I
I:
r-l~~
__~____________
1:. .
svL J::ET .. 3 _ _1_4_ _
15COUNOT _ _ _ _:.t1t.4____ INHIBIT - - -...
CLEAR
ASVNC
CLEAR
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·223
SN54HC160 THRU SN54HC163
SN74HC160 THRU SN74HC163
SYNCHRONOUS 4·BIT DECADE AND BINARY COUNTERS
absolute maximum ratings over operating free·air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 rnA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ±20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... - 65 °e to 150°C
t Stresses beyond those listed under "a.bsolute maximum ratings" may cause permanent damage to the device. These are stress ratings
:::J:
o
s:o
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
c
Vee Supply voltage
<
VIH
CD
C:r
SN74HC'
SN54HC'
en
Vee
High·level input voltage
Vee
Vee
CD
en
Vee
low-level input voltage
Vil
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
MIN
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
UNIT
V
V
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
V
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
Vee
1000
0
Vee
1000
V
0
500
0
400
0
500
400
ns
0
-55
125
-40
85
·e
0
vee - 2 V
Input transition {rise and lall) times
tt
Vee
Vee
= 4.5 V
=6V
Operating free-air temperature
TA
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
MAX
SN74HC'
MIN
1.998
1.9
1.9
4.4 4.499
4.4
4.4
1.9
10H
=
- 20 p.A
4.5 V
6V
5.9
5.999
5.9
5.9
= VIH or Vil.
= VIH or Vil.
10H
=
=
-4mA
4.5 V
3.98
4.30
3.7
3.84
6V
5.48
VI
VI
VI
=
VIH or Vil.
10H
-5.2 mA
VI = VIH or Vil.
VI - VIH or VIL.
II
VI
lee
VI
=
=
5.2
UNIT
V
5.34
0.002
0.1
0.1
0.1
10l = 20 p.A
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
10l = 4 mA
10l - 5.2 rnA
4.5 V
0.26
0.26
0.4
0.33
6V
0.17
0.15
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
8
160
80
~A
10
10
10
pF
Vee or 0
Vee or O.
5.80
MAX
2V
VOL
2-224
SN54HC'
MIN
VI = VIH or Vil.
VOH
ei
TA - 25·C
MIN
TYP MAX
10
=0
6V
2 to
6V
3
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V
SN54HC160 THRU SN54HC163
SN14HC160 THRU SN14HC163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
SN54HC160
PARAMETER
VCC
fclock Clock frequency
ClK high or low
tw
Pulse duration
CLRlow ('HC160, 'HC161)
A, B, C, or D
lOAD low
ENP, ENT
tsu
SN74HC160
THRU
THRU
SN54HCI63
SN74HC163
MIN
MAX
MIN
MAX
MIN
2V
0
0
4.2
0
5
4.5 V
0
6
31
0
21
0
25
6V
2V
0
80
36
0
120
25
0
29
4.5 V
16
24
6V
14
20
17
2V
80
120
100
4.5 V
16
24
20
6V
20
17
2V
14
150
225
190
4.5 V
30
45
38
6V
38
32
2V
26
135
205
170
4.5 V
27
41
34
6V
2V
23
170
35
255
29
215
43
34
51
6V
29
43
37
before ClKt
2V
125
190
155
4.5 V
25
38
31
6V
21
32
26
2V
160
240
200
4.5 V
32
48
40
6V
27
41
34
2V
160
240
200
4.5 V
32
48
40
6V
27
41
34
2V
0
0
0
4.5 V
0
0
0
6V
0
0
0
CLR inactive (,HC162, 'HC163)
Hold time, all synchronous inputs after ClKt
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MAX
MHz
20
4.5 V
CLR low (,HC162, 'HC163)
UNIT
100
Setup time,
CLR inactive ('HC160, 'HC161)
th
TA - 25°C
ns
•
ns
ns
2-225
SN54HC160. SN54HC161
SN74HC160. SN74HC161
SYNCHRONOUS 4·BIT DECADE AND BINARY COUNTERS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
f max
•"
::z::
tpd
ClK
tpd
ClK
tpd
ENT
RCO
Any
Q
3l:
otn
C
CD
<
tPHl
ClR
tpHl
ern
RCO
Any
Q
5'
CD
til
tt
RCO
Any
MIN
6
31
36
Power dissipation capacitance
TYP
14
40
44
83
24
20
80
25
21
62
MAX
6
215
43
37
205
41
35
195
39
33
210
42
36
220
44
37
75
15
13
No load,
TA
17
14
105
21
18
110
22
19
38
8
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-226
SN54HC160
SN54HC161
MIN MAX
4.2
21
25
325
65
55
310
62
53
295
59
50
315
63
54
330
66
56
110
22
19
TA - 25 GC
VCC
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
=
25°C
SN74HC160
SN74HC161
MIN MAX
5
25
29
270
54
46
255
51
43
245
49
42
265
53
45
275
55
47
95
19
16
60 pF typ
UNIT
MHz
ns
ns
ns
ns
ns
ns
SN54HC162, SN54HC163
SN74HC162, SN74HC163
SYNCHRONOUS 4·BIT DECADE AND BINARY COUNTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise·
noted). CL - 50 pF (see Note 1)
PARAMETER
FROM
UNPUT)
TO
(OUTPUT)
f max
tpd
ClK
tpd
ClK
tpd
ENT
tt
RCO
Any
Q
RCO
Any
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
SN54HC162
SN54HC163
MIN MAX
4.2
21
25
325
65
55
310
62
53
295
59
50
110
22
19
TA - 25°C
VCC
MIN
6
31
36
TYP
14
40
44
83
24
20
80
25
21
62
17
14
38
8
6
MAX
215
43
37
205
41
35
195
39
33
75
15
13
SN74HC162
SN74HC163
MIN MAX
5
25
29
270
54
46
255
51
43
245
49
42
95
19
16
UNIT
MHz
ns
ns
U)
CD
CJ
'S;
ns
ns
CD
c
en
o
:E
()
No load, TA
Power dissipation capacitance
=
25°C
60 pF typ
J:
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2·227
SN5.4HC160 THRU SN54HC163
SN74HC160 THRU SN74HC163
SYNCHRONOUS 4·BIT DECADE AND BINARY COUNTERS
TYPICAL APPLICATION DATA
N-BIT SYNCHRONOUS COUNTERS
This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit
counter. The 'HC160 and 'HC162 will count in BCD, and the 'HC161 and 'HC163 will count in binary. Virtually
any count mode (modulo-N, N1-to-N2, N1-to-maximum) can be used with this fast look-ahead circuit.
lSB
CUi ...
CLEAR III
ilIAii .......
COUNT IHI/
DISABLE III
ENT
EN.
ClK
::J:
C')
s:o
(I)
o
(1)
<
5'
(1)
en
LOAO ILl
COUNT IHI/
DISABLE Il
l-r--
CLOCK
--
M1
G3
3CToMAX
'i.
CS/2.3.4+
r
111
B-
121
-QB
C-
131
-Qc
D-
141
-QD
CUi ....
toA5 ...
ENT
EN.
-QA
CT=O CTR
M1
G3
3CToMAX
~
G4
CS/2.3.4+
A - 1.S0
111
f--QA
B-
121
f--QB
C-
131
f--Qc
D-
141
t--Qo
CUi ....
lOAO ......
ENT
EN.
ClK
CT=O
CTR
M1
G3
3CT~MAX
G4
~
.
CS/2.3.4+
A - 1.50
111
B-
121
C-
131
f--Qc
D-
141
t--QD
CUi ....
lOAD .......
ENT
EN.
ClK
t--QA
f--QB
CT=O CTR
M1
G3
3CT
MAX
~
G4
C6/2.3,4+
A _ 1.S0
111
B-
121
-QB
C-
131
-Qc
0-
141
-QD
v
TO MORE SIGNIFICANT STAGES
2~228
~
G4
A - 1.50
ClK
\
CT=O CTR
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
-QA
I
SN54HC160 THRU SN54HC163
SN74HC160 THRU SN74HC163
SYNCHRONOUS 4·BIT DECADE AND BINARY COUNTERS
The application circuit shown on the preceding page is not valid for clock frequencies above 18 MHz (at 25 °C
and 4.5 V VCC). The reason for this is that there is a "glitch" that is produced on the second stage's RCa
output and every succeeding stage's RCa output. This glitch is common to all HC vendors that Texas Instruments
has evaluated in addition to the bipolar equivalents ('lS, 'AlS, 'AS).
The glitch on RCa is caused because the propagation delay of the rising edge of OA of the second stage is
shorter than the propagation delay of the falling edge of ENT. The RCa output is the product of ENT, OA, OS,
OC, and OD (ENT.OA·OB·OC·OD). The resulting glitch is about 7-12 ns in duration. Figure 1 illustrates the
condition in which the glitch occurs. For the purposes of simplicity, only two stages are being considered, but
the results can be applied to other stages. OS, OC, and OD of the first and second stage are at logic one, and
OA of both stages are at logic zero (1110 1110) after the first clock pulse. On the rising edge of the second
clock pulse, OA and RCa of the first stage will go high. On the rising edge of the third clock pulse OA and
RCa of the first stage will return to a low level, and OA of the second stage will go to a high level. It is at
this time that the glitch on the RCa of the second stage will appear because of the "race condition" inside
the chip.
The glitch will cause a problem in the next stage (stage three) if the glitch is still present when the next riSing
clock edge appears (clock pulse 4). To ensure that this does not happen, the clock frequency must be less than
inverse of the sum of the clock-to-RCO propagation delay and the glitch duration (tg)' In other words,
f max = 1/(tpd ClK-to-RCO + tg)' For example, at 25°C at 4.5 V VCC, the clock-to-RCO propagation delay
is 43 ns and the maximum duration of the glitch is 12 ns. Therefore, the maximum clock frequency that the
cascaded counters can use is 18 MHz. The following table contains the fclock, t w , and f max specifications
for applications that use more than two 'HC160 family devices cascaded together.
II
U)
Q)
U
.S;
Q)
C
tn
o
::i
o
J:
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
SN54HC160
PARAMETER
fclock
tw
VCC
Clock frequency
Pulse duration, ClK high or low
SN74HC160
thru
thru
SN54HC163
SN74HC163
MIN
MAX
2.9
TA _ 25°C
MIN
MAX
MIN
MAX
2V
0
3.6
0
2.5
0
4.5 V
0
18
0
12
0
14
6V
0
21
0
14
0
17
2V
140
200
170
4.5 V
28
40
36
6V
24
36
30
UNIT
MHz
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
SN54HC160
PARAMETER
FROM
(INPUT)
TO
10UTPUll
VCC
MIN
f max
TYP
MAX
SN74HC160
thru
thru
SN54HC163
SN74HC163
MIN
MIN
TA - 25°C
MAX
2V
3.6
2.5
4.5 V
18
12
14
6V
21
14
17
UNIT
MAX
2.9
MHz
NOTE 1: These limits apply only to applications which use more than two 'HC 160 family devices cascaded together.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-229
SN54HC160 THRU SN54HC163
SN74HC160 THRU SN74HC163
SYNCHRONOUS 4·BIT DECADE AND BINARY COUNTERS
If the 'HC160 family is used as a single unit or only two cascaded together, then the maximum clock frequency
that the devices can use is not limited because of the glitch. In these situations, the devices can be operated
at the maximum specifications.
2
4
3
5
CLK
•
ENT1
::c
0
s:0
QB1. QC1. QD1
en
c
CD
<
C=;'
J
QA1l
CD
tn
RC01.ENT2
.In
RC02 _ _ _ _ _ _ _ _ _ _ _
GLITCH 17·12 no)
FIGURE 1
A glitch can appear on the RCO output of a single' HC 160 family device depending on the relationship of ENT
to the clock input. Any application that uses the RCO output to drive any input except an ENT of another cascaded
'HC160 family device must take this into consideration.
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TeXAS 75265
SN54HC164, SN74HC164
8·BIT PARALLEL·OUT SERIAL SHIFT REGISTERS
DECEMBER 1982-REVISED SEPTEMBER 1987
•
SN54HC164 ..• J PACKAGE
SN74HC164 •.. N PACKAGE
AND·Gated (Enable/Disable) Serial Inputs
•
Fully Buffered Clock and Serial Inputs
•
Direct Clear
•
Package Options Include Ceramic Chip
Carriers and Standard Plastic and Ceramic
300·mil DIPs
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEWI
A
S
QA
QS
QC
QD
GND
description
VCC
QH
QG
QF
QE
ClR
ClK
II
SN54HC164 .•• FK PACKAGE
ITOP VIEW)
These 8·bit shift registers feature AND·gated
serial inputs and an asynchronous Clear. The
gated serial inputs (A and B) permit complete
control over incoming data as a low at either
input inhibits entry of the new data and resets
the first flip·flop to the low level at the next clock
pulse. A high·level input enables the other input,
which will then determine the state of the first
flip-flop. Data at the serial inputs may be
changed while the clock is high or low, provided
the minimum setup time requirements are met.
Clocking occurs on the low-to-high-Ievel
transition of the clock input.
The SN54HC 164 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC164 is
characterized for operation from - 40°C to
85°C.
U
U
U:I:
OJ
«z>O
3
2 1 2019
18
17
16
15
14
4
5
6
7
8
9
0 0 U ~Ia:
OZZ-'-'
(!l
UU
NC - No internal connection
logic symbol t
CUi
CLK
FUNCTION TABLE
INPUTS
eLK
A
B
L
X
H
L
I
X
X
X
X
H
L
H
X
X
L
H
H
H
I
I
A
OUTPUTS
CUi
QA
L
Os ..
L
·QH
L
OAO
H
aBO
OHO
L
OAn
OAn
°Gn
OGn
L
OAn
OGn
H = high level (steady state). L = low level (steady
state)
X = irrelevant (any input, including transitions)
I = transition from low to high level
0AO. 0BO. 0HO = the level of 0A. 0B. or 0H.
respectively. before the indicated steady-state input
conditions were established.
0An. OGn = the level of OA or 0G before the most
recent t transition of the clock: indicates a one-bit
shift.
PRODUCTIOI DATA document. coltain information
ourrant a. of publication data. Products confor.. to
..ecifications per til. terms af Texas Instruments
ltanh'" warranty. Production proc"..;n. do.. not
n......rily inclada talting of all poralll8lerl.
OA
B
OB
Oc
aD
(11)
(12)
(13)
OE
OF
OG
OH
tThis symbol is in accordance with ANSIIIEEE Std 91-19B4 and
lEe Publication 617-12.
Pin numbers shown are for J and N packages.
Copyright @ 1982. Texas Instruments Incorporateo
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-231
SN54HC164, SN74HC164
8·BIT PARALLEL·OUT SERIAL SHIFT REGISTERS
logic diagram (positive logic)
IJ
:I:
Pin numbers are for J and N packages.
o
typical clear. shift. and clear sequences
s:
oen
c
CD
<
~
CLR~
I
I
I
SERIAL {
INPUTS
c;'
CD
en
~------------~:------------
A
B_-+,____...J
I
I
ClK
I
----l
~~------~-------
~------7_-------
Qc==-~l__________________~
~~~---------
QA ___ ~I_ _ _ _ _ _ _ _...J
---,
QB ___ ~I~_ _ _ _ _ _ _ _~
---,
---,
---,
QO ___ ______________________
.~I
OUTPUTS
~
~'---+---------
QE ___ ~I__________________________~
L n__________
I
I
QF ___ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - ,
~I
---,
QG ___
~I
---,
QH __
~I
I
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - ,
I
________________________
n'
~
~
_ _ _ _ _ _ _ __
I
CLEAR
2-232
CLEAR
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54HC164, SN74HC164
8·BIT PARALLEL·OUT SERIAL SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K (Va < 0 or Va > Vce . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Continuous output current, 10 (Va = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 rnA
Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Lead temperature 1.6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: N package ................... 260°C
Storage temperature range ......................................... - 65 °e to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
fI
U)
II)
U
recommended operating conditions
"S;
SN54HC164
MIN
NOM
MAX
2
5
6
Vee Supply voltage
Vee
Vee
VIH High-level input voltage
Vee
Vee
Low-level input voltage
VIL
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
II)
SN74HC164
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
0
Vee
0
Vee
V
0
0
Vee
1000
0
Vee
1000
V
0
500
400
0
500
ns
0
-40
400
Vee
0
-55
Operating free-air temperature
TA
125
0
85
:::r::
V
Output voltage
Input transition (rise and falll times
:IE
o
Vo
tt
o
V
Input voltage
=2V
= 4.5 V
=6V
(I)
V
VI
Vee
Vee
o
UNIT
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONOITIONS
Vce
2V
VI
=
VIH or VIL.
=
10H
~A
-20
VOH
VI - VIH or VIL,
VI
VI
=
=
VIH or VIL.
VIH or VIL.
=
=
10H
10H
10L
=
-4 mA
-5.2 mA
20 ~A
VOL
VI = VIH or VIL,
VI - VIH or VIL,
II
VI
lee
ej
VI
=
=
10L = 4 mA
10L - 5.2 mA
Vee or 0
Vee or O. 10
=0
TA = 25°C
MIN
TVP MAX
MIN
MAX
SN74HC164
MIN
1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
4.5 V
5.9 5.999
3.98
4.30
5.9
5.9
3.84
6V
1.9
SN54HC164
5.48
3.7
5.80
MAX
UNIT
V
5.34
5.2
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
V
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
8
160
80
10
10
10
p.A
pF
6V
2 to 6 V
TEXAS
3
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·233
SN54HC164, SN74HC164
8·BIT PARALLEL·DUT SERIAL SHIfT REGISTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vcc
fclock
•
2V
4.5 V
Clock frequency
6V
2V
4.5 V
6V
CCR low
Pulse duration
tw
CLK high or low
6V
2V
4.5V
6V
:t
(')
s:
o(I)
Data
Setup time
tou
before CLKI
CCR inactive
o
CD
<
(;'
Hold time, data after CLK I
th
2V
4.5V
CD
TA = 2SoC
MAX
MIN
0
6
31
0
0
100
20
36
17
80
17
100
20
6V
2V
4.5 V
6V
17
5
5
5
0
4.2
0
0
150
30
25
21
25
SN74HC164
MIN MAX
0
0
0
125
25
UNIT
5
25
28
MHz
21
100
120
24
20
16
14
100
20
2V
4.5V
SN54HCI64
MIN MAX
no
20
18
125
25
21
150
30
25
150
no
125
25
30
25
5
5
5
21
5
5
5
no
(I)
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
IOUTPUTI
VCC
2V
f max
4.5V
6V
2V
tpHL
-CLR
Any Q
tpd
CLK
Any Q
tt
TA = 25°C
TYP MAX
MIN
10
6
54
31
36
62
140
4.5 V
6V
28
24
2V
4.5 V
115
23
6V
2V
4.5 V
6V
20
38
Power dissipation capacitance
25
295
41
35
175
59
51
265
8
6
35
30
75
15
13
No load, TA = 25°C
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74HC164
MIN MAX
UNIT
5
25
MHz
28
205
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-234
SN54HC164
MIN MAX
4.2
21
53
45
110
22
19
255
51
46
220
44
38
95
19
16
135 pF typ
no
no
no
SN54HC165, SN74HC165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
02684. DECEMBER 1982-REVISED SEPTEMBER 1987
•
Complementary Outputs
•
Direct Overriding load (Data) Inputs
•
Gated Clock Inputs
•
Parallel-to-Serial Data Conversion
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
SN54HC165 ... J PACKAGE
SN74HC165 ... 0 OR N PACKAGE
(TOP VIEW)
SH/lD
ClK
E
VCC
ClKINH
D
C
F
G
H
QH
GND
Dependable Texas Instruments Quality and
Reliability
B
A
FI
SER
QH
SN54HC165 ... FK PACKAGE
description
(TOP VIEW)
J:
The 'HC165 is an 8-bit serial shift register that,
when clocked. shifts the data toward serial
output QH. Parallel-in access to each stage is
provided by eight individual direct data inputs
that are enabled by a low level at the SH/lD
input. The 'HC165 also features a clock inhibit
function and a complementary serial output QH.
Clocking is accomplished by a low-to-high
transition of the ClK input while SH/lD is held
high and ClK INH is held low. The functions of
the ClK and ClK INH (clock inhibit) inputs are
interchangeable. Since a low ClK input and a
low-to-high transition of ClK INH will also
accomplish clocking, ClK INH should be
changed to the high level only while the ClK
input is high. Parallel loading is inhibited when
SH/lD is held high. While SHllD is low, the
parallel inputs to the register are enabled
independently of the levels of ClK, ClK INH, or
SER inputs.
)~
~
U..:
..IJ:U U..I
UUlZ >U
3
2
1 20 19
E
4
18
F
5
17
NC
G
H
6
16
D
C
NC
7
15
B
8
14
A
9 1011 12 13
::cO U ::ca:
w
10 Z Z 0 Ul
(!)
NC-No internal connection
logic symbol t
ClK INH
The SN54HC165 is characterized for operation
over the full military temperature range' of
- 55°C to 125°C. The SN74HC165 is
characterized for operation from - 40°C to
85°C.
ClK
SER
A
B
C
FUNCTION TABLE
0
E
INPUTS
SH/LD
ClK
l
X
H
ClK
FUNCTION
G
INH
Parallel load
H
X
X
H
X
H
No change
H
l
I
Shift
H
I
l
Shift
H
No change
111)
(121
(131
10
10
(14)
(3)
(4)
(5)
(9)
(6)
10
(7)
~H
QH
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
Pin numbers shown are for D, J, and N packages.
Shift - content of each internal register
shifts toward serial output QH. Data at
serial input is shifted into first register.
PRODUCTION DATA documa.ts co.tai. i.'ormatio.
current as nt publication date. Products conform to
spacifications per the terms 01 Taxas Instruments
~~:~:~~i~8i~:I~~i ~=:~ti:; :.r::::~:~~ not
TEXAS
~
Copyright © 1982, by Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-235
SN54HC165. SN74HC165
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
logic diagram (positive logic)
A
o
C
B
(111
(131
(121
E
(141
(31
F
(41
G
(51
H
(61
•
:::t
(")
s:
oen
Pin numbers shown are for 0, J, and N packages.
o
typical shift. load. and inhibit sequences
~
CLK
5'
CD
en
CLKINH
SER
L
SH/LD~
I
I
A
B
--1['Hl
I L
I
c--f:Hl
D
IL
I
I
DATA
E--r;l
IL
F
I
G~
I
H-.JlHl
I
QH
QH
------
I
H
H
L
L
I
I
I
I
+
j4-INHIBIT ~14------ SERIAL SHIFT
LOAD
2-236
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
..
SN54HC165, SN74HC165
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) ................................. ±20 rnA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
± 25 rnA
Continuous output current, 10 (Vo = 0 to Vee) .............................. "
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 5: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 105: D or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
'S
SN54HC165
NOM
MAX
2
5
6
Low-level input voltage
VI
Input voltage
Vo
Output voltage
2
5
6
4.2
4.2
Vee = 2 V
a
a
a
a
a
a
a
a
Vee - 2 V
Vee = 4.5 V
Vee = 6 V
TA
MAX
Vee = 6 V
Vee = 4.5 V
Input transition (rise and fall) times
NOM
1.5
3.15
Vee = 6 V
tt
MIN
1.5
3.15
Vee = 2 V
Vee = 4.5 V
400
a
a
a
a
a
a
a
a
125
-40
0.3
0.9
1.2
Vee
Vee
1000
500
-55
Operating free-air temperature
Q)
SN74HC165
MIN
Vee Supply voltage
Vil
en
Q)
(,)
recommended operating conditions
VIH High·level input voltage
•
c
en
o
:!:
UNIT
V
V
(.)
J:
0.3
0.9
V
1.2
Vee
V
Vee
1000
V
500
ns
400
85
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
TA = 25°C
MIN
TYP MAX
1.9
4.4
5.9 5.999
5.9
5.9
3.7
3.84
IOH = -4 rnA
10H - -5.2 rnA
4.5 V
3.98
6V
5.~8
IOl = 20 ~A
VOL
VI = VIH or Vil.
VI = VIH or Vll,
IOl=4rnA
IOl = 5.2 rnA
a
II
VI = Vee or
lee
ei
VI - Vee or 0, 10 -
a
MIN
1.9
VI = VIH or Vll,
VI = VIH or Vll,
SN74HC165
4.4
4.5 V
VI - VIH or Vil.
MAX
1.998
1.9
IOH = -20 p.A
6V
MIN
4.4 4.499
VI = VIH or Vll,
VOH
SN54HC165
4.30
5.80
5.2
MAX
UNIT
V
5.34
0.1
2V
0.002
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
V
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
160
10
80
10
~A
3
8
10
6V
2 to 6 V
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
pF
2-237
SN54HC165, SN74HC165
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
vcc
•
fclock
Clock frequency
tw
Pulse duration
SHIm low
ClK high
or low
:I:
o
SHIm high
before ClKt
3:
o
(I)
SER before
ClKt
o
CD
<
(;'
CD
tsu
Setup time
tn
ClK INH low
before ClKt
ClK INH high
before ClKt
Data before
SH/m~
SER data
after ClKt
th
Hold time
PAR data
after SH/ml
2-238
2V
4.5V
6V
2V
4.5V
6V
2V
4.5V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
0
6
31
0
0
36
80
16
14
80
16
14
80
16
14
40
8
7
100
20
17
40
8
7
100
20
17
5
TEXAS
5
5
5
5
5
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54HC165
MIN MAX
0
4.2
21
0
0
25
120
24
20
120
24
20
120
24
20
60
12
10
150
30
25
60
12
10
150
30
26
5
5
5
5
5
5
SN74HC165
MIN MAX
0
5
0
25
0
29
100
20
17
100
20
17
100
20
17
50
10
9
125
25
21
50
10
9
125
25
21
5
5
UNIT
MHz
n•
ns
n.
ns
ns
ns
n.
n.
5
5
5
5
n.
SN54HC165. SN74HC165
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
FROM
TO
'INPUT)
'OUTPUT)
VCC
2V
4.5V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
f max
tpd
SHim
QH or n:H
tpd
elK
QH orn:H
tpd
tt
H
QH or n:H
Any
Power dissipation capaCitance
TA = 2SoC
MIN
TVP MAX
13
6
31
50
62
36
80
150
20
30
16
26
75
150
15
30
13
26
75
150
15
30
13
26
75
38
8
15
13
6
SN54HC1SS
MIN MAX
4.2
21
25
225
45
38
225
45
No load, TA = 25°C
38
225
45
38
110
22
19
SN74HC1SS
MIN MAX
5
25
29
190
38
32
190
38
32
190
38
32
95
19
16
UNIT
MHz
ns
ns
ns
ns
75 pF typ
NOTE 1: load circuit and voltage waveforms are shown in Section 1.
TEXAS ...,
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
2-239
E
J:
n
3:
o
en
c
o·
CD
CD
<
en
2-240
SN54HC166, SN74HC166
PARALLEL· LOAD B·BIT SHIFT REGISTERS
02684. DECEM8ER 1982-REVISED SEPTEMBER 1987
SN54HCI66 .•. J PACKAGE
SN74HC166 ... D OR N PACKAGE
•
Synchronous Load
•
Direct Overriding Clear
•
Parallel to Serial Conversion
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300·mil
DIPs
•
ITOP VIEW)
SER
VCC
SH/lD
H
A
B
C
D
ClK INH
ClK
GND
Dependable Texas Instruments Quality and
Reliability
description
OH
G
FJ
F
E
ClR
en
SN54HC166 ... FK PACKAGE
The 'HC166 parallel-in or serial-in, serial-out
registers feature gated clock inputs and an
overriding clear input. The parallel-in or serial-in
modes are established by the shift/load input.
When high, this input enables the serial data
input and couples the eight flip-flops for serial
shifting with each clock pulse. When low" the
parallel (broadside) data inputs are enabled, and
synchronous loading occurs on the next clock
pulse. During parallel loading, serial data flow is
inhibited. Clocking is accomplished on the lowto-high-Ievel edge of the clock pulse through a
two-input positive NOR gate permitting one input
to be used as a clock-enable or clock-inhibit
function. Holding either of the clock inputs high
inhibits clocking; holding either low enables the
other clock input. This, of course, allows the
system clock to be free-running, and the register
can be stopped on command with the other
clock input. The clock-inhibit input should be
changed to the high level only when the clock
input is high. A direct clear input overrides all
other inputs, including the clock, and resets all
flip-flops to zero.
CD
()
ITOP VIEWI
'S
ul~
a::
CD
wU U:I:
C
cn
3
2
U)
1 20 19
B
4
18
C
NC
D
ClK INH
5
17
6
16
7
15
8
14
o
:l!
(.)
:x:
F
9 1011 12 13
Ula::
-'zz-'
U(!)
U
:.! 0
w
NC - No internal connection
logic symbol t
m
SH/Li5
CLKINH
CLK
The SN54HC166 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC166 is
characterized for operation from -40°C to
85°C.
SER
A
B
C
0
(2)
(3)
(5)
(10)
E
111)
F
(12)
G
H
2.30
141
(14)
(13)
QH
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
PRODUCTION DATA d.........11 ...toi. inform.tio.
.........t "' 01 p..li..tio. dm. Prodacto .o.farm t.
spa.ificatio.. por tho farm. 01 T.... InstramonIJ
::~:~~i;·i:l:ri ~=::i:f IIr:=::9t:"~ nit
TEXAS
~
Copyright © 1982, by Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-241
SN54HC16L SN74HC166
PARALLEL·LOAD B·BIT SHIFT REGISTERS
FUNCTION TABLE
INPUTS
SHIFT!
CLOCK
LOAD
INHIBIT
X
X
X
X
L
L
L
H
L
H
H
H
H
H
X
H
t
t
t
t
CLEAR
L
H
H
::E:
X
X
X
H
L
X
PARALLEL
A ... H
X
X
a ... h
X
X
X
OUTPUT
OUTPUTS
flH
OA
L
OB
L
OAO
a
aBO
b
QHO
h
H
QAn
QGn
L
QAn
QGn
GAO
QBO
QHO
L
logic diagram (positive logic)
(')
s:o
L
INTERNAL
CLOCK SERIAL
c
B
A
(2)
SH/LD
F
E
(4)
(3)
(10)
H
G
(11 )
(12)
en
o
CD
<
ci"
CD
o
CLKINHtn~I')-~~__~~____-!~
ClK
----<._
____~+-____~~__-J~____~~____J
Pin numbers shown are for 0, J, and N packages.
2-242
. TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
(14)
SN54HC166, SN74HC166
PARALLEL·LOAO 8·BIT SHIFT REGISTERS
typical clear. shift. load, inhibit, and shift sequences
IU.
i
en
..J
«
ir
~
_________________________________ z
1
•
Tl-
i!!
:I:
Z
-
Q
r
Iu.
~
..J
«
ir
w
en
______ __ ____ __ ___ __ ___ ___ ___ __ ___1
-"0
(.)
.J
(.)
I-
i!!
:I:
~
"
g
.J
(.)
I~
I:l
a.
:!:
.J
«
ir
W
en
- ----
I~
I-
u.
ien
«
\
-- -- -- -- -'"
(.)
Q
W
u..
C)
:I:
(5
V,..------~I.J
Wen
.JI.J:l
«a.
o::z
Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO =0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package. . . . . . . . . . . . . .. 300°C
Lead temperature 1.6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(')
s:
recommended operating conditions
oen
c
<
n'
CD
SN54HC166
MIN
2
1.5
3.15
4.2
Vee Supply voltage
CD
Vee
Vee
Vee
VIH High-level input voltage
Vee
Vee
(I)
VIL Low-level input voltage
Vee
VI
Input voltage
Vo
Output voltage
tt
Input transition Irise and fall) times
=
5
0
Vee
Vee
1000
0
0
0
0
-55
6 V
Operating free-air temperature
MAX
6
0.3
0.9
1.2
0
0
0
Vee - 2 V
Vee = 4.5 V
Vee
TA
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
NOM
500
400
125
SN74HC166
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0
0
0.3
0.9
UNIT
V
V
V
0
0
1.2
Vee
V
0
0
Vee
1000
V
0
0
-40
500
400
ns
85
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
VI
=
VIH or VIL.
IOH
=
-20 p.A
VOH
VI = VIH or VIL.
VI - VIH or VIL.
10H = -4 rnA
10H - -5.2 rnA
VI
=
VI
VI
VI
VI
= VIH or VIL. IOL=4mA
= VIH or VIL. 10L = 5.2 rnA
= Vee or 0
= Vee or O. 10 = 0
VIH or VIL.
10L
=
20 p.A
VOL
II
lee
ej
2-244
4.5V
6V
4.5 V
6V
2V
4.5 V
TA = 25°C
MIN
TYP MAX
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.80
5.48
1.9
4.4
5.9
3.7
0.1
0.1
6V
4.5 V
6V
0.001
0.17
0.15
6V
6V
±0.1
0.1
0.26
0.26
±100
3
8
10
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74HC166
MIN MAX
1.9
4.4
5.9
3.84
5.34
5.2
0.002
0.001
2 to 6 V
SN54HC166
MIN MAX
UNIT
V
0.1
0.1
0.1
0.1
0.1
0.1
0.4
0.4
0.33
0.33
±10oo
nA
80
10
p.A
pF
±1Ooo
160
10
V
SN54HC166, SN74HC166
PARALLEL· LOAD 8·BIT SHIFT REGISTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
-eTIilow
tw
Pulse duration
ClK high
or low
SHiCD high
SER before
ClKi
tsu
Setup time
before ClKi
Data before
ClKi
before ClKi
SH/[l) high
after ClKi
SER after
ClKt
th
ClK INH high
after ClKi
Data after
ClKi
MIN
MAX
6
0
4.2
0
5
0
31
0
21
0
25
6V
0
36
0
25
0
29
2V
100
150
125
4.5 V
20
30
25
6V
17
80
16
14
145
29
25
80
16
14
100
20
17
80
16
14
40
8
7
0
0
0
5
5
5
0
0
0
5
5
5
26
21
120
100
24
20
2V
4.5 V
2V
4.5 V
6V
2V
4.5 V
2V
4.5 V
6V
2V
4.5 V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Hold time
MAX
4.5 V
6V
ClR inactive
SN74HC166
MIN
0
6V
ClK INH low
SN54HC166
2V
6V
before ClKi
TA - 25°C
MAX
MIN
2V
4.5 V
6V
2V
4.5 V
6V
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
20
17
220
44
180
UNIT
MHz
no
36
38
31
120
100
24
20
20
17
150
125
30
25
26
21
120
100
24
20
20
17
60
50
12
10
10
9
0
0
0
0
0
0
5
5
5
5
5
5
0
0
0
0
0
0
5
5
5
5
5
•
n.
no
5
2-245
SN54HC166, SN74HC166
PARALLEL· LOAD 8·BIT SHIFT REGISTERS
switching characteristics over recommended operating free-air temperature range lunless otherwise
noted), CL = 50 pF Isee Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
f max
::J:
tPHL
CLR
QH
tpd
CLK
QH
o
s::
tt
oen
cCD
<
n'
CD
Any
TA - 25"C
MIN
TYP MAX
11
6
31
36
36
45
62
120
18
24
13
20
75
150
15
30
13
26
38
75
15
8
6
13
Power dissipation capacitance
No load. TA
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
en
2-246
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC188
M(N MAX
4.2
21
25
180
36
31
225
45
38
110
22
19
= 25°C
SN74HC188
MIN MAX
5
25
29
150
30
26
190
38
32
95
19
16
50 pF typ
UNIT
MHz
ns
ns
ns
SN54HC173. SN74HC173
4-81T OoTYPE REGISTERS WITH 3-STATE OUTPUTS
02684. DECEMBER 1982 - REVISED SEPTEMBER 1987
•
•
High-Current 3-State Outputs Interface
Directly with System Bus or Can Drive Up
to 15 LSTTL Loads
SN54HC173 ... J PACKAGE
SN74HC173 ... D OR N PACKAGE
(TOP VIEW)
M
Gated Output-Control Lines for Enabling or
Disabling the Outputs
•
Fully Independent Clock Virtually Eliminates
Restrictions for Operating in One of Two
Modes
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
VCC
ClR
N
ClK
10
20
3D
40
<32
GNO
G1
10
20
30
40
II
U)
SN54HC173 ... FK PACKAGE
(TOP VIEW)
Dependable Texas Instruments Quality and
Reliability
Q)
(,)
oS;
U Ua:
Q)
z::iiz$'d
description
3
2 1 20 19
20
5
17
10
20
NC
6
16
NC
30
40
7
8
15
3D
40
18
The 'HC 173 4-bit registers include D-type flipflops featuring totem-pole 3-state outputs
capable of driving highly capacitive or relatively
low-impedance loads. The high-impedence third
state and increased drive provide these flip-flops
with the capability of being connected directly
to and driving the lines in a bus-organized system
without need for interface or pull-up
components.
Gated enable inputs are provided on these
devices for controlling the entry of data into the
flip-flops. When both data-enable inputs are low,
data at the D inputs are loaded into their
respective flip-flops on the next positive
transition of the clock input. Gate output-control
inputs are also provided. When both are low, the
normal logic states (high or low levels) of the four
outputs are available for driving the loads or bus
lines. The outputs are disabled independently
from the level of the clock by a high logic level
at either output-control input. The outputs then
present a high impedance and neither load nor
drive the bus line. Detailed operation is given in
the function table.
c
14
en
o
::E
:::r:
(.)
9 1011 1213
NC - No internal connection
FUNCTION TABLE
INPUTS
CLEAR
CLOCK
DATA ENABLE
DATA
G1
G2
D
OUTPUT
a
H
X
X
X
X
L
L
L
X
X
X
L
1
1
I
1
H
X
X
X
H
X
ao
ao
ao
L
L
L
L
L
L
H
H
L
L
L
When either M or N (or both) is (are) high. the output is
disabled to the high-impedence state; however. sequential
operation of the flip-flops is not affected.
The SN54HC173 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC173 is
characterized for operation from - 40°C to
85°C.
PRODUCTION DATA d.cumonto contain information
currant as of publication date. Products conform to
.pacifications par the tarms at Taxas Instruments
:=~i~ai~:1~7i ~:\::i:fn :.~O:=::::~::~S not
Copyright © 1982. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-247
SN54HC173, SN74HC173
4-81T O-TYPE REGISTERS WITH 3-STATE OUTPUTS
logic symbol t
10
2Q
3Q
4Q
:t:
"os:
tn
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
M(1)
C
OUTPUT {
CONTROL
CD
<
N (2)
0"
CD
o
DATA (13)
2D ~~--+----+----r~
CLOCK (7)
DATA (12)
3D ~'----t--+---l
DATA (~1~1~)_ _~_ _ _,-~
4D
CLEAR
(~1..:.5~1- t > o - - - - - - -......-..q
Pin numbers shown are for 0, J, and N packages.
2-248
TEXAS . "
, INSTRUMENTS
POST OFFICE BOX 655012 • DALl.AS. TEXAS 15266
SN54HC173. SN74HC173
4·81T O·TYPE REGISTERS WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature range t
Supply voltage, Vee ................................................ -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K(VO < 0 or Vo > Vee) .............................. ±20 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
eontinuous current through Vee or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ......... " .... 300 0 e
lead temperature 1,6 mm (1/16 inl from case for 10 s: D or N package . . . . . . . . . . . . . . . . 260 0 e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 °e to 150 0 e
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
contitions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
II
U)
Q)
U
recommended operating conditions
':;
SN54HC173
MIN NOM MAX
vee
VIH
VIL
Supply voltage
High-level input voltage
Vee
Vee
Low-level input voltage
Vee
Vee
Vee
Vee
VI
Vo
tt
=
1.2
Vee
Vee
1000
0
0
0
500
400
125
0
-55
6 V
Operating free-air temperature
6
0.3
0.9
0
0
0
Vee - 2 V
Vee = 4.5 V
Input transition (rise and fall I times
5
0
Input voltage
Output voltage
Vee
TA
2
1.5
3.15
4.2
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
SN74HC173
MIN NOM MAX
2
1.5
3.15
4.2
5
6
Q)
o
UNIT
V
CI)
o
:E
V
(.)
0
0.3
0.9
1.2
0
0
0
0
0
0
0
-40
::I:
V
V
Vee
Vee
1000
500
ns
400
85
De
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
=
VIH or VIL' IOH
=
VCC
-20,.A
VOH
VI - VIH or VIL. 10H - -6mA
VI - VIH or VIL, IOH - -7.8 mA
VI
=
VIH or VIL, IOL
=
20 p.A
VOL
VI = VIH or VIL, 10L = 6 mA
VI - VIH or VIL, IOL = 7.8 mA
II
10Z
lee
ei
VI - Vee or 0
Vo = Vee or 0
VI - Vee or 0, 10 - 0
TA - 25°C
MIN
TVP MAX
SN64HC173
MIN MAX
2V
1.9
1.998
1.9
4.5 V
6V
4.5V
4.4
4.499
4.4
5.9
3.98
5.48
5.999
4.30
5.80
0.002
0.001
5.9
3.7
6V
2V
4.5V
6V
4.5 V
6V
6V
6V
6V
2 to 6 V
SN74HC173
MIN MAX
1.9
4.4
5.9
3.84
5.34
5.2
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.26
0.26
±0.1 ±100
±0.01 ±0.5
8
10
3
0.4
0.4
0.33
0.33
±1000
±10
±1000
±5
160
10
80
10
0.001
0.17
0.15
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
UNIT
V
nA
p.A
p.A
pF
2·249
SN54HC173, SN74HC173
4·BIT O·TYPE REGISTERS WITH 3·STATE OUTPUTS
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
fclock
Input clock frequency
ClK high or low
tw
Pulse duration
ClR high
%
(")
s::
Gl and G2
oen
c
(1)
tsu
Setup time before ClK I
<
,;"
Data
CLR inactive
(1)
en
Gl and G2
th
Hold time after ClK I
Data
2-250
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN
MAX
0
0
0
80
16
14
80
16
14
100
20
6
31
36
17
100
20
17
90
18
15
0
0
0
0
0
0
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC173
SN74HC173
MIN
MAX
MIN
MAX
0
0
0
120
24
20
120
24
20
150
30
25
150
30
25
135
27
23
0
0
0
0
0
0
4.2
0
0
0
100
20
5
25
29
21
25
UNIT
MHz
ns
17
100
20
17
125
25
21
125
25
21
115
23
19
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
SN54HC173, SN74HC173
4·81T O·TYPE REGISTERS WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
f max
tpHl
tpd
ten
tdis
ClR
ClK
M or N
M or N
Any
Any
Any
Any
Any
tt
vcc
SN54HC173
TA - 25°C
MAX
MIN
4.2
MAX
SN74HC173
MIN
5
2V
MIN
6
TYP
8
4.5 V
31
46
21
25
6V
36
55
25
29
MAX
MHz
2V
78
150
225
190
4.5 V
21
30
45
38
6V
20
26
38
32
2V
78
150
225
190
4.5 V
21
30
45
38
6V
20
38
2V
78
26
150
32
190
225
4.5 V
20
30
45
38
6V
15
26
38
32
2V
40
150
225
190
4.5 V
18
30
45
38
6V
2V
16
26
38
32
20
60
90
75
4.5 V
8
12
18
15
6V
6
10
15
13
Power dissipation capacitance
UNIT
ns
ns
en
CD
U
'S;
ns
CD
C
(J)
ns
o
:iE
ns
(.)
:t
29 pF typ
No load, TA - 25°C
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted!. CL = 150 pF (see Note 1)
PARAMETER
tpHl
tpd
ten
tt
FROM (INPUT)
ClR
ClR
M or N
TO (OUTPUT)
Any
Any
Any
Any
VCC
SN54HC173
TA - 25°C
MIN
SN74HC173
2V
TYP
100
MAX
200
4.5 V
28
40
60
50
6V
21
34
51
43
250
MIN
MAX
300
MIN
MAX
250
2V
100
200
300
4.5 V
28
40
60
50
6V
21
34
51
43
250
2V
100
200
300
4.5 V
28
40
60
50
6V
21
34
51
43
265
2V
45
210
315
4.5 V
17
42
63
53
6V
13
36
53
45
UNIT
ns
ns
ns
ns
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFtCE BOX 655012 • DALLAS, TEXAS 75265
2-251
::r::
(')
s:o
t/)
c
CD
<
n'
CD
en
2-252
SN54HC174, SN54HC175
SN74HC174, SN74HC175
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
02684, DECEMBER 1982-REVISEO JUNE 1989
•
'HC174 Contains Six Flip-Flops with SingleRail Outputs
•
'HC175 Contains Four Flip-Flops with
Double-Rail Outputs
•
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
SN54HC174, ' . J PACKAGE
SN74HC174 ... D OR N PACKAGE
(TOP VIEW)
VCC
ClR
10
10
20
20
3D
30
60
60
50
50
40
40
GNO
II
ClK
en
SN54HC174 ... FK PACKAGE
(TOP VIEW)
Dependable Texas Instruments Quality and
Reliability
G)
CJ
015 u
tlo
~uz>co
'>
3
C
description
2
G)
I 20 19
en
18
These monolithic, positive-edge triggered D-type
flip-flops have a direct clear input, and the
'HC175 features complementary outputs from
each flip-flop,
14
J:
SN54HC175 ... J PACKAGE
SN74HC175 ... D OR N PACKAGE
(TOP VIEW)
ClR
VCC
10
"0
40
40
40
3D
30
30
10
20
20
20
GNO
ClK
SN54HC175 ... FK PACKAGE
(EACH FLlP·FlOP)
(TOP VIEW)
015 u
OUTPUTS
a
at
X
L
H
H
H
l
H
D
l
x
H
I
I
L
l
l
H
(..)
FUNCTION TABLE
ClK
H
IS
910111213
The SN54HC174 and SN54HC175 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HC174 and SN74HC175 are characterized
for operation from - 40°C to 85 DC.
INPUTS
X
:!:
16
Information at the D inputs meeting the setup
time requirements is transferred to the outputs
on the positive-going edge of the clock pulse.
Clock triggering occurs at a particular voltage
level and is not directly related to the transition
time of the positive-going edge of the clock
pulse. When the clock input is at either the high
or low level, the D input signal has no effect at
the output.
ClR
o
17
tlo
~uz>~
3
ao 50
2
1 20 19
10
10
4
18
5
17
NC
6
16
8
14
20
t'HC175 only
15
9 1011 12 13
NC-No internal connection
PRODUCTION DATA documenlS contain information
cumot as of publication date. Products conform to
specifications par the terms of
TIXIS
Instrum"ts
::~:~i;a{nr:I~"'i ~:~::i:; :.~o=:::lt!O:S
not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
Copyright © 1989. Texas Instruments Incorporated
2-253
SN54HC174, SN54HC175
SN74HC174, SN74HC175
HEX/QUADRUPLE D·TYPE FLlP·FLOPS WITH CLEAR
logic symbols t
'HC174
'HC175
CLR
ClR
ClK
10
20
3D
ClK
(2)
(4)
(5)
(6)
171
(11)
(10)
(13)
50
(14)
60
(12)
(15)
4D
10
10
10
lQ
20
30
20
2D
40
50
20
30
3Q
3D
60
::t
40
40
41i
C")
s:
otn
tThese symbols are in accordance with ANSIIIEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
C
logic diagrams (positive logic)
CD
'HC175
'HC174
<
(;'
CD
(I)
elK
10~~--++--I
20-":'':':'''--++--I
Pin numbers shown are for 0, J, and N packages.
2-254
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54HC174, SN54HC175
SN74HC174, SN74HC175
HEX/OUADRUPLE D·TYPE FLlp·FLOPS WITH CLEAR
absolute meximum ratings over operating free·air temperature range t
Supply voltage. Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current. 11K (VI < 0 or VI > Vec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current. 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current. 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1.6 mm (1/16 in) from case for 60 s: FK or J package. . . . . . . . . . . . . .. 300°C
Lead temperature 1.6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
I
recommended operating conditions
SN54HC174
SN54HC175
V CC Supply voltage
VIH High-level input voltage
VCC
Vee
Low-level input voltage
Vee
Vee
Vee
VIL
Vee
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
Vee
Vee
Vee
TA
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
MIN
NOM
MAX
2
1.5
3.15
4.2
5
6
Operating free-air temperature
2
5
6
1.5
3.15
0.3
0
0
=2V
= 4.5 V
=6V
SN74HC174
SN74HC175
MIN NOM MAX
0.9
1.2
0.3
0.9
0
Vee
Vee
1000
0
0
-55
500
0
0
0
0
0
400
125
0
-40
V
V
4.2
0
0
0
0
0
UNIT
V
1.2
Vee
Vee
1000
V
V
500
400
ns
85
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
Vce
TA
=
MIN
VI
=
VIH or VIL.
IOH
=
-20 p.A
2V
4.5 V
TVP
1.9 1.998
4.4 4.499
VI
VI
=
=
VIH or VIL.
VIH or VIL.
10H
10H
=
=
-4 mA
6V
4.5 V
5.9 5.999
3.98
4.30
6V
2V
4.5 V
6V
4.5 V
5.48
VOH
VI
=
VIH or VIL.
10L
=
-5.2 mA
20 p.A
VOL
II
lee
ej
VI - VIH or VIL.
VI = VIH or VIL.
VI = Vee or 0
10L - 4 mA
10L = 5.2 mA
VI - Vee or O. 10 - 0
6V
6V
SN54HC174
25°C
MAX
SN54HC175
MIN MAX
1.9
4.4
5.9
3.7
5.9
3.84
0.1
0.1
0.1
5.2
0.1
0.1
0.1
0.17
0.15
±0.1
0.26
0.26
±100
0.4
0.4
±1000
8
160
10
3
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
10
MIN
1.9
4.4
5.80
0.002
0.001
0.001
6V
2 to 6 V
SN74HC174
SN74HC175
UNIT
MAX
V
5.34
0.1
0.1
0.1
0.33
0.33
±1000
80
10
V
nA
I'A
pF
2-255
SN54HC174, SN74HC174
HEX O·TYPE FLIp· FLOPS WITH CLEAR
timing requirements over recommended operating free~air temperature range (unless otherwise noted)
vcc
fclock
Clock frequency
-ern low
Pulse duration
tw
ClK high or low
:::t
(')
s:
o
Data
Setup time
before ClKI
tsu
(I)
-ern inactive
c
CI)
<
(;'
Hold time, data after ClK I
th
CI)
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
0
6
0
31
0
36
80
16
14
80
16
14
100
20
17
100
20
17
0
0
0
SN54HC174
MIN MAX
0
4.2
0
21
0
25
120
24
20
120
24
20
150
30
25
150
30
25
0
0
0
SN74HC174
MIN MAX
0
5
0
25
0
29
100
20
17
100
20
17
125
25
21
125
25
21
0
0
0
UNIT
MHz
n.
ns
ns
(I)
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
f max
-ern
Any
tpd
ClK
tt
Any
Any
Power dissipation capacitance per
TA = 2Soc
MIN
TYP MAX
6
9
31
44
36
50
58
160
17
32
14
27
160
58
17
32
14
27
75
38
15
8
13
6
flip~flop
No load, TA = 25°C
NOTE 1: load circuit and voltage waveforms are shown in Section 1.
2-256
TEXAS
SNS4HC174
MIN MAX
4.2
21
25
240
48
41
240
48
41
110
22
19
~
INSTRUMENTS
POST OFFICE BOX 655012 " DALLAS, TEXAS 75265
SN74HC174
MIN MAX
5
25
29
200
40
34
200
40
34
90
19
16
27 pF typ
UNIT
MHz
n.
ns
SN54HC175, SN74HC175
QUADRUPLE D·TYPE FLlp·FLOPS WITH CLEAR
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
ern low
Pulse duration
tw
ClK high or low
SN54HC175
MAX
MIN
MAX
SN74HC175
MIN
MAX
2V
0
6
0
4.2
0
5
4.5 V
0
31
0
21
0
25
6V
0
36
0
25
0
29
2V
80
4.5 V
16
120
24
6V
14
20
17
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
100
150
125
20
30
17
25
21
before ClKI
2V
100
150
125
4.5 V
20
30
25
6V
17
0
0
0
25
21
0
0
0
0
0
Hold time, data after eLK t
4.5 V
6V
MHz
20
6V
ern inactive
UNIT
100
4.5 V
2V
th
= 25°C
Setup time
Data
tsu
TA
MIN
fI
ns
fI)
CD
(,)
25
'S
ns
CD
a
en
o
0
:!E
ns
CJ
J:
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
Vce
2V
f max
ern
Any
tpd
ClK
tt
Cpd
Any
Any
TA = 25°C
TYP MAX
MIN
6
SN54HCI75
MIN
MAX
SN74HC175
MIN
12
4.2
5
4.5 V
31
50
21
25
6V
36
60
25
29
MAX
MHz
2V
52
150
255
190
4.5 V
15
30
45
38
6V
13
26
38
32
2V
58
150
255
190
4.5 V
16
30
45
38
6V
13
26
38
32
2V
38
75
110
90
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance per flip-flop
No load, TA = 25°C
UNIT
ns
ns
30 pF typ
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-257
2-258
SN54HC180, SN74HC180
9·BIT ODD/EVEN PARITY GENERATORS/CHECKERS
02484. MARCH 1984-REVrSEO SEPTEMBER 1987
•
•
SN54HCI80 ..• J PACKAGE
SN74HCI80 ••• 0 OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300·mil
DIPs
ITOPVIEWI
G
H
EVEN
ODD
E EVEN
Dependable Texas Instruments Quality and
Reliability
description
E ODD
GND
These universal. monolithic, 9-bit (8 data bits
plus 1 parity bit) parity generators/checkers,
feature odd/even outputs and control inputs to
facilitate operation in either odd- or even-parity
applications, Depending on whether even or odd
parity is being generated or checked, the even
or odd inputs can be utilized as the parity or 9thbit input. The word-length capability is easily
expanded by cascading.
ITOPVIEWI
U
U
U
::r::elZ>u.
3
2 1 20 19
E
NC
4
18
5
17
6
16
D
7
15
NC
14
C
8
9 1011 12 13
OOU<{1Xl
OZZ
FUNCTION TA8LE
INPUTS
Oel
t..l
OUTPUTS
E
E
EVEN
ODD
EVEN
ODD
EVEN
H
L
H
L
ODD
H
L
L
H
EVEN
L
H
L
H
ODD
L
H
H
L
EVEN
X
X
H
H
L
L
ODD
L
L
H
H
ATHRU H
•
SN54HCI80 ••• FK PACKAGE
The SN54HC180 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC180 is
characterized for operation from -40°C to
85°C.
EOFH'sAT
VCC
F
E
D
C
B
A
NC-No internal connection
logic symbol t
A
H = high level. L = low level. X = irrelevant
B
c
0
E
F
G
H
181
4
191
(10)
15)
~
EVEN
3
111)
112)
(13)
11)
12)
3
4
16)
~
ODD
tThis symbol is in accordance with ANSI/lEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
PRODUCTION DATA do.uments.ontsin information
current 8S of publicatioR data. Products conform to
specifications par the tarms of Taxas Instruments
:'~~~:~~i~ai~:I~lJi ~:\:~ti~n ~~o::~::~:~~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 15265
Copyright @ 1982. Texas Instruments Incorporated
2-259
SN54HC180, SN74HC180
9·BIT ODD/EVEN PARITY GENERATORS/CHECKERS
logic diagram (positive logic)
EVEN _':.:3!-1- - - - - - - - - - - - - 1 . : > 0 - - - - - - - - - - - - ,
ODD~'4~1_____________________1~----------------------~
A
B
::E:
(')
3:
otJ)
c
F
CD
<
C:r
CD
(I)
Pin numbers shown are for 0, J, and N packages.
absolute maximum ratings over operating free-air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package. . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2-260
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC180, SN74HC180
9·81T ODD/EVEN PARITY GENERATORS/CHECKERS
recommended operating conditions
SN54HC180
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
Vee Supply voltage
Vee
VIH High-level input voltage
Vee
Vee
Vee
VIL
Low-level input voltage
Vee
Vee
=
=
=
=
=
=
2 V
SN74HC180
MIN
1.5
1.5
3.15
3.15
6 V
4.2
4.2
4.5 V
UNIT
V
V
2 V
0
0.3
0
0.3
4.5 V
0
0.9
0
0.9
6 V
0
1.2
0
1.2
VI
Input voltage
0
Vee
0
Vee
V
Va
Output voltage
0
Vee
1000
0
V
tt
Input transition (rise and fall) times
500
0
Vee
1000
500
TA
Operating free-air temperature
= 2V
= 4.5 V
Vee = 6 V
0
0
Vee
Vee
0
0
400
0
400
-55
125
-40
85
II
V
I/)
Q)
(.)
ns
'S;
Q)
°e
C
electrical characteristics over recommended operating free-air temperature range (unless otherwise
oo~1
PARAMETER
TEST CONDITIONS
VCC
~A
= VIH or VIL, 10H = -20
VOH
= VIH or VIL, 10H = -4 rnA
VI = VIH or VIL, 10H = -5.2 rnA
VI
VI
= VIH or VIL, 10L = 20 ~
VOL
=
VI =
VI =
VI =
VI
II
lee
ej
= 4 rnA
VIH or VIL, 10L = 5.2 rnA
VIH or VIL,
10L
VCC or 0
Vee or 0, 10
= 0
SN54HC180
MIN
MAX
SN74HC180
MIN
1.998
1.9
1.9
4.4 4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
4.5 V
6V
3.98
4.30
3.7
3.84
2V
VI
TA = 25°C
MIN
TYP MAX
4.5 V
1.9
5.48
5.2
5.80
MAX
UNIT
V
5.34
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
6V
0.15
0.26
±0.1
±100
0.4
±1000
±1000
nA
8
160
80
~A
10
10
10
pF
3
2 to 6 V
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
~
U
J:
2V
6V
en
0
V
0.33
2-261
SN54HC180, SN74HC180
9-81T ODD/EVEN PARITY GENERATORS/CHECKERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tpd
FROM
(INPUT)
Data
(odd
= 0)
Data
(odd
= 0)
Data
tpd
:::t
(even
= 0)
oen
tpd
c
CD
tpd
tt
2V
119
260
390
325
4.5 V
36
52
78
65
6V
2V
32
113
44
245
66
370
55
305
4.5 V
33
49
74
61
6V
13
42
63
52
325
Odd
Even
Data
(even = 0)
Odd
Even or Odd
Even or Odd
Any
VI
Cpd
MIN
MAX
MIN
MAX
2V
119
260
390
4.5 V
36
52
78
65
6V
32
66
370
55
305
2V
113
44
245
4.5 V
33
49
74
61
6V
24
42
63
52
2V
49
110
165
140
4.5 V
15
22
33
28
6V
12
19
28
2V
38
75
110
24
95
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance
No load, TA
NOTE 1: load circuit and voltage waveforms are shown in Section 1.
2-262
SN74HC180
Even
<
n"
CD
SN54HC180
Vce
(")
3:
TA = 25°C
MIN
TYP MAX
TO
(OUTPUT)
TEXAS
-1!1
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
= 25°C
60 pF typ
UNIT
n'
n.
n.
n.
n.
n.
SN54HC190, SN54HC191, SN74HC190, SN74HC191
SYNCHRONOUS 4·BIT UP/DOWN DECADE AND BINARY COUNTERS
02684, DECEMBER 1982 - REVISED JUNE 1989
•
Single Down/Up Count Control Line
•
Look-Ahead Circuitry Enhances Speed of
Cascaded Counters
SN54HC190, SN54HC191 ... J PACKAGE
SN74HC190, SN74HC191 ... ot OR N PACKAGE
(TOP VIEWI
B
•
Fully Synchronous in Count Modes
•
Asynchronously Presettable with Load
Control
•
Package Options: Plastic and Ceramic DIPs,
Plastic Small-Outline Packages, and Ceramic
Chip Carriers
•
VCC
A
QB
QA
CTEN
Dependable Texas Instruments Quality and
Reliability
ClK
RCO
MAXIMIN
lOAD
DiD
Qc
QD
GND
C
D
en
SN54HC190, SN54HC191 ... FK PACKAGE
(TOP VIEWI
description
CD
()
'S;
U
m U U
Omz>-LJ
1151
t :0
111
~
-
...LJ
,-V
C
....u
1101
'Q
,-V
1131
~
~
;-~
CI
~F}
A..
-
~ Da
~ ~1Jt?CLJ
'-<:s
r-<
CI
"""-
~
~
...LJ
L:o
~
r- 'O
"f'
Lc;- .....!!!.. Oc
~
r
::j::
~ r!.-l
f-<>CI
r'D
-
191
---...
kQ
I--
~s
1-----'"
WD~
~>CI
Pin numbers are for D. J. and N packages.
2-264
MAXIMIN
141
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
A..
....
~ DO
rL 1
SN54HC191, SN74HC191
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
logic symbol t
1121
MAX/MIN
131 aA
121 a
161 B
III
121
141
171
181
fI
0c
aD
fI)
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
Q)
u
"S:
logic diagram (positive logic)
Q)
Q
1121 MAXIMIN
CTEN
DIU
elK
LOAr
A
141
(I)
o
:E
o
:r:
151 ......
~
.....
~
1151
U
ID
111
TD
~
L-
e (101
a
D
U
~~--------------~
Pin numbers are for 0, J, and N packages.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-265
SN54HC190, SN74HC190
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS
typical load. count. and inhibit sequences
Illustrated below is the following sequence:
1 . Load (preset) to BCD seven
2. Count up to eight. nine (maximum), zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum), nine, eight, and seven·
I
'-
:::r:
(")
s:o
en
i
B.J
L..
DATA
INPUTS
i
'-
cCD
<
(;'
r
D
I
CD
(I)
CLOCK
I
- ----1--,1
I
'I
----1--71'
ffiiii ____,__ 11~'-----------I
DIU ____I___ ILI_ _ _ _ _ _ _ _ _ _ _ _- I
,
:
1
I
I:
QB
QC
.r----
----:--!l
I ~.--------..1
___ ...J
r----
I
I
,
~i---------~------~--------~
----;--11
___ ...J
-- --,
QD ____
I '
L-jJ
I I
MAXIMIN
===J ::
RCO - - - - ,
I
I I
___ ...I
:
II
7
I I
8
U--I.-
,
U
9
2
0
COUNT UP
2
• I-INHIBIT
I
11
U
--I I--2
LOAD
2-266
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS; TEXAS 75265
0
~
9
COUNT DOWN
8
7
SN54HC191, SN74HC191
SYNCHRONOUS 4·BIT UP/DOWN BINARY COUNTERS
typical load, count, and inhibit sequences
Illustrated below is the following sequence:
1.
2.
3.
4.
Load (preset) to binary thirteen
Count up to fourteen, fifteen (maximum), zero, one, and two
Inhibit
Count down to one, zero (minimum). fifteen, fourteen, and thirteen.
•
lOA0-U
1-A-.J
L_
B
r-
--I --
I
DATA
INPUTS
I
C-.J
L_
D.-J
L_
ClK
--- --,
Diu ___, __ ...
' _ _ _ _ _ _ _ _ _ _ _ _--'
I
I I
-----,
C'i'EN ___' __ IL-_ _ _ _ _ _ _ _ _-'
, I
I,
I
I
I:
0B
==l..lJi----:___. . .
I
MAXIMIN
I
=-= ~.._"'-:-_---'11..____-.,-____:--.,-_-.....111..______
I
U:
RCO::]
: 13
I
14
15
0
2
U
2
2
..
I·>----COUNT U P - - - . . I--INHIBIT--I
~
I----
o
15
14
13
I
COUNT D O W N - - - - ·..
lOAD
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
2-267
SN54HC19L SN54HC191. SN74HC19L SN74HC190
SYNCHRONOUS 4·BIT UP/DOWN DECADE AND BINARY COUNTERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee ................................................ -0.5 V to 7 V
Input clamp current, IIK(VI < 0 or VI > Vee) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K(VO < 0 or Vo > Vee) .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 rnA
eontinuous current through Vee or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ... : . . . . . . . . . . . 300 0 e
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ................ 260 0 e
Storage temperature range ......................................... - 65 °e to 150 0 e
::J:
(')
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
contitions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
3:
oen
c
CD
<
C;'
Vee
VIH
Supply voltage
High-level input voltage
Vee ~ 6 V
(I)
Vee - 2 V
Vee ~ 4.5 V
Low-level input voltage
Vee
VI
Input voltage
Vo
Output voltage
tt
Input transition (rise and fall) times
TA
SN74HC190
SN54HC191
MIN NOM MAX
SN74HC191
MIN NOM MAX
2
Vee - 2 V
Vee ~ 4.5 V
CD
VIL
SN54HC190
~
6 V
5
6
2
1.5
1.5
3.15
3.15
4.2
4.2
5
6
V
V
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
0
0
Vee
0
0
Vee
V
Vee
1000
v
ns
Vee
~
2 V
0
Vee
1000
Vee
~
4.5 V
0
500
0
500
Vee
~
6 V
0
-55
400
0
400
125
-40
85
Operating free-air temperature
UNIT
0
V
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
2V
VI ~ VIH or VIL, 10H ~ -20
4.5 V
~A
VOH
VI - VIH or VIL, 10H -
-4 rnA
VI ~ VIH or VIL, 10H ~ -5.2 rnA
VI
~
VIH or VIL, 10L
~
20 pA
VOL
VI ~ VIH or VIL, 10L ~ 4 rnA
2-268
TA - 25°C
VCC
MAX
SN54HC190
SN74HC190
SN54HC191
SN74HC191
MIN
TYP
MIN
MAX
MIN
1.9
1.998
1.9
1.9
4.4 4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
4.5 V
3.98
4.30
3.7
3.84
6V
5.48
5.80
5.2
UNIT
MAX
V
5.34
2V
0.002
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0..1
0.1
4.5 V
0.17
0.26
0.4
0.33
0.1
V
VI - VIH or VIL, 10L - 5.2 rnA
6V
0.15
0.26
0.4
0.33
II
VI - Vee orO
6V
±0.1 ±100
±1000
±1000
nA
lee
ej
VI
6V
8
10
160
80
~A
10
10
pF
~
Vee or 0, 10
~
0
2 to 6 V
TEXAS
3
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC19~ SN54HC191, SN74HC19~ SN74HC191
SYNCHRONOUS 4·BIT UP/DOWN DECADE AND BINARY COUNTERS
timing requirements over recommended operating free·air temperature range (unless otherwise
noted)
vCC
fclock
Clock frequency
lOAO low
tw
Pulse duration
elk high or low
Data before LOAD!
CTEN before elK I
tsu
Setup time
DIU before elK!
lOAD inactive before elK!
Data after lOAD I
th
Hold time
CTEN after elK!
DIU after elK I
2V
4.5 V
6V
2V
4.5V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
SN54HC190
SN54HC191
MIN
MAX
MIN
MAX
0
0
0
120
24
21
120
24
21
150
30
25
205
41
35
205
41
35
150
30
25
5
5
5
5
5
5
5
5
5
4.2
21
24
0
0
0
180
36
31
180
36
31
230
46
38
306
61
53
306
61
53
225
45
38
5
5
5
5
5
5
5
5
5
2.8
14
16
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
SN74HC190
SN74HC191
MIN MAX
0
0
0
150
30
26
150
30
26
188
38
32
255
51
44
255
51
44
190
38
32
5
5
5
5
5
5
5
5
5
3.3
17
19
UNIT
MHz
ns
fI
U)
CD
CJ
oS
CD
Q
fI)
o
ns
:iE
()
::E:
ns
2-269
SN54HC190, SN54HC191, SN74HC190, SN74HC191
SYNCHRONOUS 4·BIT UP/DOWN DECADE AND BINARY COUNTERS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted). CL ... 50 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
BV
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
'max
::t
o
tpd
lOAD
Any a
tpd
A, B,
C, or D
aA,aB
aC, or aD
tpd
ClK
RCO
tpd
ClK
Any a
tpd
ClK
MAXIMIN
tpd
Diu
RCO
tpd
Diu
MAXIMIN
tpd
CTEN
RCO
is:
otn
C
CD
<
n"
CD
rn
tt
Any
TA - 25°C
MIN TYP
4.2
8
21
42
24
48
130
40
33
135
36
30
58
17
14
107
31
26
123
39
32
102
29
24
86
24
20
50
15
13
38
8
6
MAX
264
53
45
240
48
41
120
24
21
192
38
32
252
50
43
228
46
38
192
38
32
132
26
23
75
15
13
Power dissipation capacitance
NOTE 1: Load circuit and voltage waveforms are shown in Section 1,
2·270
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SN54HC190
SN54HC191
MIN MAX
2.8
14
16
396
79
67
360
72
61
180
36
31
288
58
49
378
76
65
342
68
59
288
58
49
198
40
34
110
22
19
SN74HC190
SN74H.C191
MIN MAX
3.3
17
19
330
66
56
300
60
51
150
30
26
240
48
41
315
63
54
285
57
49
240
48
41
165
33
28
95
19
16
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
50 pF typ
SN54HC192, SN54HC193
SN74HC192, SN74HC193
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
02684. DECEMBER 1982 - REVISED JUNE 1989
•
SN64HC192, SN64HC193 .•. J PACKAGE
SN74HC192, SN74HC193 ... ot OR N PACKAGE
(TOPVIEWI
Look·Ahead Circuitry Enhances Cascaded
Counters
•
Fully Synchronous in Count Modes
•
Parallel Asynchronous Load for Modulo-N
Count Lengths
•
Asynchronous Clear
•
Package Options: Plastic and Ceramic DIPs,
Plastic Small-Outline Packages, and Ceramic
Chip Carriers
•
Dependable Texas Instruments Quality and
Reliability
B
QB
QA
DOWN
Vee
A
eLR
BO
eo
LOAD
e
D
UP
Qe
QD
GND
fI
SN54HC192. SN54HC193 ... FK PACKAGE
ITOPVIEWI
U
description
--
r: 10
~
...
.A-
~
9
(91
U
~
r--
~
~ ~7JL· l
f--c pCl
J
>-U
~
=tJ
r--
L.: s
-1!1.
~ ~ r.!Ll
f--c P.Cl
f--1D
....
>-U
=tJ
r--
...I
~'-ill
'--< ","_Cl
SiD
-U
Pin numbers shown are for D, J, and N packages.
2·272
1~r:J
~
L.:s
1101
'i7
r~
f-< PCl
II)
9
o
LU-
~
(151
t
C
~;!.
(51 ....
,.,[>-I
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
.A.~
rL l
SN54HC193. SN74HC193
SYNCHRONOUS 4·BI1 UP/DOWN BINARY COUNTERS (DUAL CLOCK WITH CLEAR)
logic symbol t
CTRDIV16
CLR 1141
UP 151
CT=O
2+
ICT=15
2CT=O
1121
CO
{131 jjQ
111
131 0A
121
121 Os
141
(81
161 Oc
171 0D
fI
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
II)
CI)
logic diagram (positive logic)
(J
(12)
(13)
CLR
(14)",
~f\.
15) .....
UP
DOWN
LOAD
(4)
LU
~
(15)
A
B
~ ;::u
=L.J
o
1_
(9)
>
~>
1
=l..}
::L)
~ :::u-
~-
-s
~>Cl
gR
(10)
en
:?!
u
J:
....
=L..)
~
»--
....,.-
I1l
BO
CI)
0
0
~
r:: 10
U
C
~
'S:
CO
....,-
°A
r~l
r--
l."s
~I>Cl
f---
~
10
r!-~
~;-'~
'-<>Cl
-10
r~l
r--
=l...J'
~~~~
~ ::u
OD
....,-
Pin numbars shown are for 0, J, and N packages.
TEXAS
~
INSTRUMENTS
POST OFfICE BOX 655012 • DALLAS. TEXAS 75265
2-273
SN54HC192, SN74HC192
SYNCHRONOUS 4-811 UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
typical clear. load. and count sequence:
Illustrated below is the following sequence:
1 . Clear outputs to zero
2. Load (preset) to' BCD seven
3. Count up to eight, nine, carry, zero, one. and two
4. Count down to one, zero, borrow, nine, eight, and seven .
•
--1l~
CLR
i:OAD
::I:
(')
s:
0
A
en
D
--1-'--'
-_
-_
-_
-_
-_
-_
-_
-_
-_
-_____
_ _ _ _ _ L....I._
,
I'
_ _ I_I_---l
1
<
1
CD
(I)
UP
DOWN
1
I 1
-----1-,-- - - - - - - -,......,-----------,
- _I_I _ _ I_I_..J
I
I
,......,1----,
'----~
I
QB
1
=:lL.._~
=:1
=:J'--_~-:------J
~----~~
I
I
OUTPUTS
Dc
_
I
I'
--1---1-1--
1
QA
I
_ _ I_I_---l
1 I
5'
U
1 1
I 1
- _
-1-1- "L- - . . _
_
_ _ ---l
C
DATA
CD
1 I
- ----,,L-.. _ _ _ _ _ _ _
-----,,L-.. _ _____________ _
B
C
________________________________
I
' - - -_ _ _ _ _ _ _ _ _ _
-:-_..J
~_ _ _ _ _ _ _ _ _ _ _ _ _ __..J~
'-I
QD
I
~
u
CO
iffi
SEQUENCE
'LLUSTRATED
1
10
'I
171
~~
CLEAR
I
1
I
r-8
PRESET
9
0
COUNT UP
~
1
U
1
0
I
9
B. When counting up, count-down input must be high; when counting down, count-up input must be high.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 .. DALLAS, TEXAS 75265
71
~COUNT DOWN---'
NOTES: A. Clear overrides load, data, and count inputs.
2-274
8
SN54HC193,SN74HC193
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
typical clear. load. and count sequences
Illustrated below is the following sequence:
1 . Clear outputs to zero
2. Load (preset) to binary thirteen
3. Count up to fourteen, fifteen, carry, zero, one, and two
4. Count down to one, zero, borrow, fifteen, fourteen, and thirteen.
CLR
~~----------------------________________________________________
I
,
~------'--~LJr-----------------------------------------------A
"
I
I'
I'
FI
I
-______
- , - ,....J
- "l....--
B -_ _
-_
, -_
, -_
-_
- ,L...J,__
DATA
I, I'
I, I'
-1-,--"--
____,_.....1
C -
- - , - - - "L
--
o -_ _ _ _ .....I
I
UP -
l....-
'I
-,-- -,-,-
- -,---1-1--
DOWN -
-
-
-
-
-
-
-,......-----------.....;.----,
_ _ '_I __ I_I __ J
I
.-'_1___--.
,
°B
OUTPUTS
,
=.J
~
"I~-"""",:,""';'--'-'
I
ac::J
,'-----'
00:-'
co
~~~------~'_
__________________
~
--------~---------,LJ
BO ------~-~,-~-------------~-~I-----,LJ
~ ~ ~ l~DUN~UP ~ ~C~UNT~~WN~
SEQUENCE
ILLUSTRATED
CLEAR
PRESET
NOTES: A. Clear overrides load, data. and count inputs.
B. When counting up, count~down input must be high; when counting down, count-up input must be high.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2·275
SN54HC192, SN54HC193
SN74HC192, SN74HC193
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee ................................................ -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K(VO < 0 or Vo > Vee) .............................. ±20 mA
Continuous output current, 10 (VO = 0 to Vee) ................................ ±25 mA
Continuous current through Vee or GND pins .................................. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ......... , ..... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ................ 260°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
::r:
s:::
oen
o
cCD
<
(;'
CD
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
contitions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC192
SN54HC193
MIN NOM MAX
Vee
VIH
Supply voltage
2
1.5
3.15
4.2
Vee = 2 V
Vee = 4.5 V
High-level input voltage
Vee =6 V
US
VIL
0
Vee = 2 V
Vee = 4.5 V
Low-level input voltage
Input voltage
Output voltage
tt
Input transition (rise and fall) times
Vee = 6 V
TA
1.2
Vee
Vee
1000
0
0
0
-55
Vee - 2 V
vee = 4.5 V
Operating free-air temperature
6
0.3
0.9
0
0
0
0
Vee = 6 V
VI
Vo
5
500
400
125
SN74HC192
SN74HC193
MIN NOM MAX
2
1.5
3.15
4.2
5
6
UNIT
V
V
0
0.3
0.9
0
0
0
0
V
1.2
Vee
Vee
1000
500
400
0
0
0
-40
85
V
V
ns
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
TA - 25°C
MIN
2V
4.5 V
4.4 4.499
4.4
4.4
-4mA
6V
4.5 V
5.9 5.999
4.30
3.98
5.9
3.7
5.2
5.9
3.84
5.34
VI = VIH or VIL. 10H = -5.2 mA
2-276
SV
2V
5.48
5.80
0.002
0.4
±loo0
0.33
±1000
nA
8
10
ISO
10
80
10
pA
pF
VI - VIH or VIL. 10L - 4 mA
VI - VIH or VIL. 10L = 5.2 mA
VI = Vee or 0
4.5 V
0.17
VI - Vee or O. 10 - 0
0.1
0.15
±0.1 ±100
0.001
0.001
2 to 6 V
0.1
0.1
0.1
V
0.1
0.1
0.1
0.33
4.5 V
6V
SV
6V
6V
1.9
UNIT
0.1
0.1
0.4
VI = VIH or VIL. 10L = 20 ~A
VOL
lee
ei
SN74HC193
MIN MAX
1.9
VI = VIH or VIL. 10H = -20 pA
VI - VIH or VIL. 10H -
II
SN74HC192
SN54HC193
MIN MAX
TVP
1.9 1.998
VOH
MAX
SN54HC192
0.2S
0.26
3
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
V
SN54HC192, SN54HC193
SN14HC192, SN14HC193
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
timing requirements over recommended operating free·air temperature range (unless otherwise
noted)
vcc
2V
fclock
Clock frequency
4.5 V
6V
Pulse duration
Setup time
MIN
MAX
MIN
MAX
MIN
MAX
0
0
4.2
0
2.8
0
3.3
21
0
14
0
17
24
0
16
0
19
180
150
24
36
30
6V
21
31
26
2V
120
180
150
a5AD low
4.5 V
6V
24
21
36
31
30
26
2V
120
180
150
UP or DOWN high or low
4.5 V
24
36
30
6V
21
31
26
2V
110
165
140
4.5 V
22
33
28
24
140
a5AD inactive
CLR inactive before
UPI or DOWNI
UPI or DOWNI
Hold time
SN74HC193
2V
LOAD inactive before
th
SN74HC192
SN54HC193
4.5 V
Data before
tsu
SN54HC192
0
120
CLR high
tw
TA - 25 G C
6V
19
28
2V
110
165
4.5 V
22
33
28
6V
19
28
24
2V
110
165
140
4.5 V
22
19
33
28
28
24
6V
2V
Data after LOAD inactive
5
5
5
4.5 V
5
5
5
6V
5
5
5
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAlL.AS. TeXAS 75265
UNIT
MHz
fI
n.
en
II)
()
"S
II)
C
CI)
o
:;
n.
CJ
J:
n.
2-277
SN54HC192, SN54HC193
SN74HC193
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
SN74HC19~
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
vcc
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
f max
tpd
UP
CO
o
tpd
DOWN
BD
oC/)
tpd
UP or
DOWN
Any Q
tpd
LOAD
Any Q
tpHL
CLR
ANY Q
l:
3:
c
CD
<
c:;-
CD
en
tt
Any
TA - 25°C
MIN TYP
4.2
8
21
55
24
60
75
24
20
75
24
20
190
40
35
190
40
35
170
36
31
38
8
6
MAX
165
33
28
165
33
28
250
50
43
260
52
44
240
4B
41
75
15
13
No load, TA
Power dissipation capacitance
NOTE 1: load circuit and voltage waveforms are shown in Section 1.
2-278
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54HC192
SN54HC193
MIN MAX
2.8
14
16
250
50
43
250
50
43
375
75
64
390
78
66
360
72
61
110
22
19
=
25°C
SN74HC192
SN74HC193
MIN MAX
3.3
17
19
205
41
35
205
41
35
315
63
54
325
65
55
300
60
51
95
19
16
UNIT
MHz
ns
ns
ns
ns
ns
ns
50 pF typ
SN54HC194. SN74HC194
4·BI1 BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
02684, DECEMBER 1982 - REVISED JUNE 1989
•
Parallel Inputs and Outputs
•
Four Operating Modes:
Synchronous Parallel Load
Right Shift
Left Shift
Do Nothing
SN54HC194, , ,J PACKAGE
SN74HC194 .. ,N PACKAGE
(TOP VIEW)
ClR
SR SER
A
VCC
OA
Os
Oc
QD
ClK
S1
SO
S
•
Positive Edge-Triggered Clocking
•
Direct Overriding Clear
•
Package Options: Plastic and Ceramic DIPs
and Ceramic Chip Carriers
•
Dependeble Texas Instruments Quality and
Reliability
C
D
Sl SER
GND
U)
SN54HC194, , , FK PACKAGE
(TOP VIEW)
Q)
CJ
'S;
II:
Q)
W
These bidirectional shift registers are designed
to incorporate virtually all of the features a
system designer may want in a shift register, The
circuit features parallel inputs, parallel outputs,
right-shift and left-shift inputs, operating-modecontrol inputs, and a direct overriding clear line,
The register has four distinct modes of operation,
namely:
3
Synchronous parallel loading is accomplished by
applying the 4 bits of data and taking both mode
control inputs, SO and S 1, high, The data are
loaded into the associated flip-flops and appear
at the outputs after the positive transition of the
clock input, During loading, serial data flow is
inhibited,
A
4
18
S
5
17
NC
C
D
6
16
15
14
8
:E
Os
Oc
NC
u
:t:
OD
ClK
II:OUO~
NC - No internal connection
logic symbol t
SR SER
(15)
A
B
C
Clocking of the shift register is inhibited when
both mode control inputs are low,
::,=~~l;"i:'':.'.1.; =:~:; :':":a":=~ not
(I)
o
1 20 19
wzzd
description
(14)
(13)
(12)
SL SER
OA
OB
Oc
OD
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12,
Pin numbers shown are for J and N packages.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
Copyright © '989, Texas Instruments Incorporated
2-279
SN54HC194, SN74HC194
4·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
logic diagram (positive logic)
CLR
CLK
so
S1
SR SER
:::t:
A
(")
(1)
(11)
(9)
.......
.J'.....
V
1>-
f'....
~r1> r------- --- ------ (2)
(3)
s:o
THIS DETAIL
IS TVPICAL
OF ALL4
MULTIPLEXERS
~
,~
$-
c
CD
<
~
5"
CD
(I)
L ________
---- ------~
R
3
1
(4j
~
f-<:
I
~;-~
o }MUX
0
1
G
a
1
2
o
SLSER
}MUX
G
1
1
(6)
3
0
(7)
2
Pin numbers shown are for J and N packages.
2~280
C1
~1
0
o
H:;-~
~ -C
3
-
C1
~l
2
(5)
:>-
J
0
C
10
-
...- i-<
3
~
-
C1
o }MUX
0
G-
1
B
~-(15)
~
H
en
,
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
J!.
3
.---( R
~
'--< I>C1
~1
SN54HC194, SN74HC194
4·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
FUNCTION TABLE
INPUTS
MODE
s,So
CLEAR
X
X
H
L
L
H
H
L
L
H
H
H
H
H
H
H
CLOCK
X
X
H
H
H
L
L
L
X
L
I
I
I
I
I
X
OUTPUTS
SERIAL
LEFT
RIGHT
X
X
X
X
X
H
L
X
X
X
X
H
L
X
X
X
PARALLEL
B
X
X
b
X
X
X
X
X
A
X
X
a
X
X
X
X
X
QA
QB
Oc
00
L
L
L
C
D
X
X
L
L
X
d
X
X
X
X
X
QAO
c
X
X
X
X
X
a
aBO Oco aDO
b
c
d
H
aAn
L
aAn
aSn
aSn
aAn
•
aSn aCn
aBn Ocn
H
Ocn aDn
L
aCn aDn
aSn aCn aDn
typical clear. load. right-shift. left-shift. inhibit. and clear sequences
CLOCK
MODE {so - CONTROL
-INPUTS
S1
J
I
:
::Tll,--~----------!
I
CLEAR
l.J:
I
I
Lr
I
I
I
I
!;--i-_+-,rl
SERIAL {
DATA
R __
INPUTS
L
I
I
I
---7:-~,--7---------~-~~
A ~~_ _ _ _ _ _ _ _ _ _~~_ _ _ _ _ _ _ _~_ _ _ _ _ _ _~__
PARALLEL
DATA
INPUTS
B__
•
,
I
I
-
~:~L~:_-T
_________
~_~
_______ ________
~
~_
C ~,_~_ _ _ _ _ _ _ _ _ _~~_ _ _ _ _ _ _~~_ _ _ _ _ _ _~___
,
,
I
I
-
D__ , , , _________ _______-T________
::Lt--Lr-1
, "'------~'--~-------~
~
~:~L~:_~
~_~
~_
QA
--,+-
0B __
OUTPUTS
r---,,-,
~I ' - -_ _ _ _ _ _ _-:-_
: _
! L---J
1'--_ _ _-'--'"_ _ _ _ _....1
L
I
Dc
:~~
aD
---!'_":'---I
I
I
-- I
'
I
CLEAR LOAD
I--
SHIFT RIGHT
I--
TEXAS
SHIFT LEFT
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
.1.
INHIBIT
--.I
CLEAR
2-281
SN54HC194, SN74HC194
4·BIT BIDIRECTIONAL UNIVERSAL. SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (VO < 0 or Vo > Vec . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vce or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300 0 e
Lead temperature 1,6 mm (1/16 in) from case for 10 s: N package ................... 260 0 e
Storage temperature range ......................................... - 65 °e to 1 50 0 e
:t:
o
:s::
ot/)
c
CD
<
C)"
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN74HC194
SN54HC194
Vee Supply voltage
Vee
Vee
VIH High·level input voltage
Vee
CD
rn
Vee
Low·level input voltage
VIL
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
MIN
NOM
MAX
2
5
6
4.2
Operating free-air temperature
UNIT
V
V
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
Vee
Vee
1000
0
Vee
V
0
Vee
1000
V
0
500
0
500
ns
0
-55
400
0
-40
400
0
0
TA
6
3.15
0
Vee
5
4.2
Input voltage
Input transition (rise and fall) times
2
3.15
Output voltage
tt
MAX
1.5
Vo
=2V
= 4.5 V
=6V
NOM
1.5
VI
Vee
Vee
MIN
125
0
85
V
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
=
VIH or VIL.
10H
=
VCC
-20,.A
VOH
VI - VIH or VIL.
VI
=
VIH or VIL.
10H 10H
=
=
VI
=
VI
= VIH or VIL. 10L =
= VIH or VIL. 10L = Vee or 0
= Vee or O. 10 = 0
VIH or VIL.
10L
-4 mA
VI
2-282
VI
lee
ei
VI
MIN
MAX
SN74HC194
MIN
1.9 1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
5.9 5.999
4.30
3.98
5.9
5.9
3.7
3.84
6V
5.48
5.80
5.2
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
20 ~A
4.5V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4 mA
5.2 mA
4.5 V
0.17
0.26
0.4
0.33
VOL
II
SN54HC194
2V
4.5 V
-5.2 mA
TA - 25°C
MIN
TYP MAX
V
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
8
160
80
~A
10
10
10
pF
6V
2 to 6 V
3
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN4HC194. SN74HC194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
Clock frequency
fclock
CLK high or low
Pulse duration
tw
CLR low
Setup time. any input before CLKT
tou
Hold time, data after CLKT
th
TA - 25°C
MAX
MIN
SN54HC194
MIN
MAX
SN74HC194
MIN
MAX
2V
0
6
0
4.2
0
5
4.5 V
0
31
0
21
0
25
6V
0
36
0
25
0
29
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
100
150
4.5 V
20
30
125
25
6V
17
26
21
2V
0
0
0
4.5 V
0
0
0
6V
0
0
0
UNIT
MHz
•
no
U)
CD
U
no
':;
CD
o
no
en
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
FROM
TO
IINPUT)
IOUTPUT)
VCC
f max
tpHL
tpd
tt
CLR
CLK
Any
Any
Any
TA - 25°C
MIN
TYP MAX
SN54HC194
MIN
MAX
SN74HC194
MIN
2V
6
4.2
5
4.5 V
31
21
25
6V
36
25
29
MAX
2V
67
150
225
190
17
45
38
6V
14
30
26
37
31
2V
67
145
220
180
4.5 V
17
29
44
36
6V
14
25
37
31
2V
28
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
No load, TA
= 25°C
:E
(.)
:r:
UNIT
MHz
4.5 V
Power dissipation capacitance
o
no
no
no
65 pF typ
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-283
IE
:J:
n
s:
oen
o
CD
<
(;'
CD
tn
2-284
SN54HC195, SN74HC195
4-81T PARALLEL-ACCESS SHIFT REGISTERS
D26B4. DECEMBER 19B2-REVISED JUNE 19B9
•
SN54HC195 ••• J PACKAGE
SN74HC195 .•. N PACKAGE
(TOP VIEW)
Synchronous Parallel Load
•
Positive-Edge-Triggered Clocking
•
J and K Inputs to First Stage
•
Complementary Outputs from Last Stage
•
Package Options: Plastic and Ceramic DIPs
and Ceramic Chip Carriers
•
Dependable Texas Instruments Quality and
Reliability
ClR
VCC
J
A
B
OA
OB
Oc
00
C
Qo
0
ClK
SH/lO
K
GNO
description
en
'S;
CD
tl «
5
u
2
1 20 19
C
1
..,uz>o
3
Parallel loading is accomplished by applying the
4-bits of data and taking the shift/load control
input low. The data is loaded into the associated
flip-flop and appears at the outputs after the
positive transition of the clock input. During
loading, serial data flow is inhibited.
Shifting is accomplished synchronously when
the shift/load control input is high. Serial data for
this mode is entered at the J-K inputs. These
inputs permit the first stage to perform as a
J-K-, 0-, or T-type flip-flop as shown in the
function table.
CD
CJ
SN54HC195 ... FK PACKAGE
(TOP VIEW)
These 4-bit registers feature parallel inputs,
parallel outputs, J-K serial inputs, shift/load
control input, and a direct overriding clear. The
registers have two modes of operation: parallel
(broadside) load, and shift (in the direction OA
and 00).
U)
K
4
18
A
5
17
NC 6
16
7
15
8
14
o
:!:
CJ
z
910111213
NC-No internal connection
logic symbol t
The SN54HC195 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC195 is
characterized for operation from - 40°C to
85°C.
J
K
A
S
OA
Os
Oc
OD
aD
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617·12.
Pin numbers shown are for J and N packages.
PRODUCTION DATA documents conllin infurmltion
current 8S of publication data. Products conform tG
specifications par the terms of T811. Instruments
:'~=:~i~at::1~7. =~:~:; :.~a::;:::£:~~ not
Copyright © 1989. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-285
SN54HC195, SN74HC195
4·81T PARALLEL·ACCESS SHIFT REGISTERS
logic diagram (positive logic)
ClR
ClK
SH/LD
(15)
E
°A
K
::r:
(1
s::0
en
c
CD
<
ri'
CD
(14)
en
Os
s
(13)
°c
(12)
00
(11)
Pin numbers shown are for J and N packages.
2-286
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
aD
SN54HC195, SN74HC195
4·BIT PARALLEL·ACCESS SHIFT REGISTERS
FUNCTION TABLE
INPUTS
OUTPUTS
SERIAL
PARAllEL
CUi
SH/LD
ClK
J
K
A
B
C
D
L
X
X
X
X
X
X
X
H
L
t
X
X
a
b
H
H
L
X
X
X
H
H
t
t
t
t
L
H
X
H
H
H
H
H
H
OD
OA
OB
Oc
OD
X
L
L
L
L
H
c
d
a
b
c
d
d
X
X
X
X
X
X
L
L
X
X
X
X
H
H
X
X
X
X
H
L
X
X
X
X
QAO QBO QCO QDO ODD
QAO QAO aBn QCn OCn
L
QAn QBn QCn aCn
H
QAn
QBn
QCn
QCn
QAn QAn
QBn
QCn
OCn
II
en
typical clear. shift. and load sequences
CD
U
'>CD
ClK
I
I
-~----,r--f"'L.-----------i!f---+---------
INPUTS SHIro
K :=:t==~rT"I_~:
~==========;tl-;=t:=========
~r-;'----------
SERIAL {
:
1
PARAllEL
{
DATA
INPUTS
B
l
C
D
J:
I
-~-----if----------~~L.-;'----------
II
I
__ ,
o ---,
~1
B --- 1
Oc
QD
:-.::'+----i----.J
.:::::.1
I
I
"--'!-i- - - - - - - I
,--,
A -- - I
{
:E
I
Q
OUTPUTS
(I)
o
(.)
~
A
C
I
~-------
...-----.
r----'
I
I
1----SERIAl SHIFT
1<1I1
..
---~
CLEAR
\ . - - SERIAL SHIFT
~
lOAO
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
2-287
SN54HC195, SN74HC195
4-BIT PARALLEL-ACCESS SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ±20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ........... , ... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: N package ................... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
::r:
o
3:
otn
C
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Vee Sup'ply voltage
CD
<
c:;'
SN54HC196
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0
0
0.9
1.2
0
0
Vee
0
Vee
1000
0
500
0
400
0
-55
125
Vee
Vee
Vee
Vee
Vee
V,H High·level input voltage
CD
en
V,l low-level input voltage
Vee
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
V,
Vee
Vee
Vee
TA
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Operating free-air temperature
SN74HC196
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0
0.3
0
0.9
0
1.2
0
Vee
0
Vee
0
1000
0
500
0
400
-40
85
UNIT
V
V
V
V
V
ns
·e
electrical characteristics over recommended operating free-air temperature range junless otherwise
noted)
PARAMETER
TEST CONDITIONS
V,
= V,H
or V'l,
10H
=
-20
V,
V,
= V,H
= V,H
or V'l,
or V'l,
10H
10H
=
=
-4mA
-5.2 mA
V,
= V,H
or V'l,
10l
= 20 ~A
~A
VOH
VOL
I,
ICC
ej
2-288
TA = 26°C
TYP MAX
MIN
2V
1.9 1.998
4.5V
4.4 4.499
6V
5.9 5.999
4.5 V
3.98
4.30
6V
5.48
5.80
2V
0.002
0.1
4.5 V
0.001
0.1
6V
0.001
0.1
4.5 V
0.17
0.26
6V
0.15
0.26
6V
±0.1 ±100
6V
8
2 to 6 V
3
10
vCC
V, - V,H or V'l, 10l = 4 mA
V, = V,H or V'l, 10l = 5.2 rnA
V, = Vee or 0
V, - Vee or 0, 10 = 0
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
SN64HC195
MIN MAX
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
160
10
SN74HC195
MIN MAX
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
80
10
UNIT
V
V
nA
~
pF
S14HC195, SI74HC195
4·BIT PARALLEL·ACCESS SHIFT REGISTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
ClK high or low
Pulse duration
tw
ClR low
SH/lO, or serial
Setup time,
tsu
and parallel data,
before ClKI
th
or CLR inactive
Hold time,
SHim or serial
after ClKI
and parallel data
TA = 2S GC
SNS4HC195
SN74HC195
MIN
MAX
MIN
MAX
MIN
MAX
2V
0
6
0
4.2
0
5
4.5 V
0
31
0
21
0
25
6V
0
36
0
25
0
29
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
100
150
125
4.5 V
20
30
25
6V
17
26
21
2V
0
0
0
4.5 V
0
0
0
6V
0
0
0
UNIT
MHz
•
ns
U)
Q)
Co)
ns
'S;
Q)
C
no
CI)
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
VCC
f max
tpd
tt
ClK
ern
SNS4HC195
MIN
MAX
SN74HC195
MIN
2V
6
12
4.2
5
4.5 V
31
50
21
25
6V
36
60
25
29
MAX
2V
67
145
220
180
4.5 V
17
29
44
36
AD
6V
14
25
37
31
2V
67
150
225
190
or
4.5 V
17
30
45
38
AD
6V
13
26
38
32
2V
28
75
110
95
Any
4.5 V
8
15
22
19
6V
6
13
19
16
QA thru QO
No load, TA
Power dissipation capacitance
= 25°C
CJ
:::t:
UNIT
MHz
or
QA thru QO
tpd
TA = 2S C
MIN
TYP MAX
G
o:E
no
no
no
65 pF typ
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-289
::c
(')
3:
ot/)
c
CD
<
c:r
CD
(I)
2-290
.
SN54HC237. SN74HC237
3-LlNE TO B-LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
02804, MARCH 1984- REVISED JUNE 1989
•
Combines Decoder and 3-Bit Address Latch
•
Incorporates 2 Output Enables to Simplify
Cascading
•
•
SN54HC237 , , , J PACKAGE
SN74HC237 ... ot OR N PACKAGE
(TOP VIEW)
A
B
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
VCC
YO
Yl
Y2
Y3
Y4
Y5
Y6
C
GL
G2
Gl
Y7
GND
Dependable Texas Instruments Quality and
Reliability
fI
description
II)
The SN54HC237 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC237 is
characterized for operation from -40°C to
85°C.
Q)
SN54HC237 ... FK PACKAGE
The 'HC237 is a three-line to eight-line decoder/
demultiplexer with latches on the three address
inputs. When the latch-enable (GL) is low, the
'HC237 acts as a decoder/demultiplexer. When
GL goes from low to high, the address present
at the select inputs (A, B, and C) is stored in the
latches. Further address changes are ignored as
long as GL remains high. The output enable
controls, G1 and G2, control the outputs
independently of the select or latch-enable
inputs. All of the outputs are forced low if G 1
is low or G2 is high. The 'HC237 is ideally suited
for implementing glitch-free decoders in strobed
(stored-address) applications in bus-oriented
systems.
U
">
(TOP VIEW)
Q)
U
aJ<~~~
3
2
C
(J)
1 20 19
C
4
18
GL
5
17
NC
G2
Gl
6
16
7
15
14
8
o
Yl
Y2
NC
Y3
Y4
:E
CJ
:I:
9 1011 12 13
I'OU-zz>->t?
NC - No internal connection
t Contact the factory for D availability.
logic symbols (alternativesl*
GL
x/v
C8
OMUX
(15)
A
B
c
(1)
0
80
(2)
(14)
2
2
(3)
4
3
Gl
G2
(6)
4
&
(13)
(12)
(11)
(10)
EN
5
(9)
6
(7)
7
VO
Vl
A
V2
B
V3
c
III
80
(2)
(3)
V5
V7
Gl
(14)
2
3
V4
V6
:},~
(15)
0
&
(6)
4
(13)
(12)
(10)
(9)
6
(1)
7
Vl
V2
V3
(11) V4
5
G2
vo
V5
V6
V7
*These symbols are in accordance with ANSI/lEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
=:~~:~i~lr::1~7e ~~:~~i:r :'.O::~:::::t:~~S not
Copyright © 1989, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-291
SN54HC237, SN74HC237
3·UNE TO B·UNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
logic diagram (positive logic)
(15) VO
•
(14) Vl.
(12)
(11)
(10)
(9)
Gl..!::!---~
(7)
Pin numbers shown are for 0, J, and N packages.
FUNCTION TABLE
INPUTS
ENABLE
2·292
OUTPUTS
SELECT
B
A
VO
Vl
V2
V3
V4
V5
V6
V7
X
X
X
X
L
L
L
L
L
L
L
L
X
C
X
X
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
L
L
L
L
L
L
H
L
H
H
L
L
L
H
L
L
L
L
GL
Gl
G2
X
X
X
H
IL
L
L
H
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
H
L
H
L
H
L
L
L
L
L
H
L
L
H
L
H
H
L
L
L
L
L
L
L
H
L
L
H
L
H
H
H
H
H
L
X
X
X
L
L
L
L
L
L
L
H
Outputs corresponding to stored address, L;
all others, H
TEXAs ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. teXAS 75265
V3
V4
V5
V6
V7
SN54HC237, SN74HC237
3-L1NE TO B-L1NE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee ................................................. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) .................................. ± 20 mA
Output clamp current, 10K (Va < 0 or Va > Vee) .............................. ± 20 mA
Continuous output current, 10 (Va = 0 to Vee) ................................. ± 25 mA
Continuous current through Vee or GND pins ................................... ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ................ 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ................. 260 o e
Storage temperature range .......................................... - 65°C to 150°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PI
II)
Q)
CJ
recommended operating conditions
SN54HC237
MIN
NOM
MAX
2
5
6
vee Supply voltage
V,H
High-level input voltage
Vee
Vee
Vee
V,L
Low-level input voltage
Vee
Vee
= 4.5 V
=6V
=2V
= 4.5 V
=6V
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
3.15
Vee - 2 V
'S
SN74HC237
4.2
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
0
Vee
0
Vee
V
0
Vee
1000
0
Vee
1000
V
0
500
0
500
ns
0
-55
400
0
-40
400
Vee
Vee
0
Operating free-air temperature
TA
125
0
85
:t:
V
Input voltage
Input transition (rise and fall) times
:e:(.)
4.2
0
Output voltage
tt
o
V
Vo
=2V
= 4.5 V
=6V
en
v
V,
Vee
Q)
o
UNIT
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
notedl
PARAMETER
TEST CONDITIONS
SN54HC237
MIN
MAX
SN74HC237
MIN
2V
1.9 1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
5.9
5.9
-4 rnA
6V
4.5 V
5.9 5.999
V, - V,H or V'L, 10H -
3.98
3.7
3.84
V, - V,H 0' V'L, 10H -
- 5.2 rnA
6V
5.48
=
V,H or V'L, 10H
=
VOH
V,
=
V,H or V'L, 10L
=
20 ~A
VOL
V,
lee
ej
TA - 25°C
TYP MAX
MIN
-20 pA
V,
I,
VCC
=
V,H or V'L, 10L
=4
rnA
V, - V,H or V'L, 10L - 5.2 rnA
V, - Vee or 0
V,
=
Vee or 0, 10
=0
4.30
5.80
5.2
MAX
UNIT
V
5.34
0.1
2V
0.002
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.26
6V
0.17
0.15
0.26
0.4
0.4
0.33
0.33
6V
±0.1 ±100
±1D00
±1D00
nA
6V
8
160
80
~A
10
10
10
pF
2 to 6 V
3
TEXAS •
INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
V
2-293
SN54HC237, SN74HC237
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
vcc
tw
tsu
th
Pulse duration,
2V
4.5 V
GL low
Setup time, A, B, or C before
Hold time, A, B, and C after
GLt
GLt
:t
n
s:
o
SN54HC237
MIN
120
6V
2V
4.5 V
6V
16
14
75
15
13
2V
4.5 V
5
5
20
5
5
6V
5
5
MAX
24
20
115
23
SN74HC237
MIN
100
MAX
UNIT
20
17
ns
95
19
16
ns
5
5
ns
5
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
(I)
C
TA - 25°C
TYP MAX
MIN
80
SN54HC237
2V
4.5 V
TA - 25°C
MIN TYP MAX
91
190
23
3B
6V
2V
4.5 V
17
66
18
32
145
29
48
220
44
6V
2V
4.5 V
6V
2V
4.5 V
13
68
18
14
92
24
25
145
29
25
190
37
220
44
37
285
57
6V
19
2V
4.5 V
6V
38
8
6
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC
tpd
A,B,C
Any
Any
CD
<
c;'
CD
(I)
tpd
<32
tpd
G1
Any
tpd
GL
Any
tt
Any
38
32
75
15
13
No load, TA = 25°C
Power dissipation capacitance
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-294
MIN
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MAX
285
57
48
110
22
19
SN74HC237
MIN
MAX
240
UNIT
48
41
181
ns
36
31
181
ns
36
31
240
ns
48
41
ns
95
19
16
85 pF typ
ns
SN54HCT237, SN74HCT237'
3-UNE TO B-UNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
02804, MARCH 1984-REVISEO JUNE 1989
•
SN54HCT237 , , , J PACKAGE
SN74HCT237 ••. N PACKAGE
Inputs are TTL-Voltage Compatible
•
Combines Decoder and 3-Bit Address Latch
•
Incorporates 2 Output Enables to Simplify
Cascading
•
Package Options Include Ceramic Chip
Carriers and Stendard Plastic and Ceramic
300-mil DIPs
•
(TOP VIEWI
Vee
A
B
YO
Yl
Y2
Y3
Y4
Y5
Y6
e
GL
<32
Gl
Y7
GND
Dependable Texas Instruments Quality and
Reliability
description
U)
The 'HCT237 is a three-line to eight-line
decoder/demultiplexer with latches on the three
address inputs. When the latch-enable input (GL)
is low, the 'HCT237 acts as a decoder/
demultiplexer. When GL goes from low to high,
the address present at the select inputs (A, B,
and C) is stored in the latches. Further address
changes are ignored as long as GL remains high.
The output enable controls, G1 and G2, control
the outputs independently of the select or latchenable inputs. All of the outputs are forced low
if G1 is low or G2 is high. The 'HCT237 is ideally
suited for implementing glitCh-free decoders in
strobed (stored-address) applications in busoriented systems.
Q)
SN54HCT237 , . , FK PACKAGE
(TOP VIEW)
.s:
CJ
U
Q)
uo
m>U
c
en
3 2 1 20 19
o
18
Gl
5
17
6
7
16
15
8
14
:::!:
(.)
l:
9 1011 12 13
...
ou"''''
>-zz>->(!)
NC - No internal connection
The SN54HCT237 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCT237 is
characterized for operation from -40°C to
85°C.
logic symbols (alternativesl t
x/v
A
B
C
tThese symbols are in accordance with ANSIIEEE Std 91·1984 and IEC Publication 617·12.
Pin numbers shown are for J and N packages.
PRODUCTION DATA dooume.boontai. i.lar.llion
curront IS of pu~licatio. data. Prod.eII ..ofarm to
..ecificatio.. par the IIrm. of Te.u Inltrument.
::.=~~ai~:I':.'Ji ~r::l:~:: fll"::;:::~:'~ not
I
TEXAS . "
INsrRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76266
Copyright @ 1989, Texas Instruments Incorporated
2-295
SN54HCT237. SN74HCT237
3·L1NE TO B·L1NE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES
logic diagram (positive logic)
(15)
•
vo
(14) Vl
::c
(13)
(")
s:o
(12)
t/)
V2
Y3
c
CD
(11)
<
C:;'
CD
(10)
(I)
(9)
Gl"!::':'----,
(7)
Pin numbers shown are for J and N packages.
FUNCTION TABLE
INPUTS
ENABLE
G2
C
B
A
YO
Yl
Y2
Y3
Y4
Y5
Y6
Y7
H
X
X
X
X
X
l
l
L
L
L
l
l
L
l
H
H
H
H
H
H
H
H
X
X
l
l
l
l
L
L
l
L
l
l
L
l
H
H
H
H
l
l
H
H
L
l
H
H
l
H
l
H
L
H
l
H
L
l
H
l
l
l
l
l
l
L
l
l
l
H
l
l
L
L
L
L
l
l
l
l
H
L
L
l
l
L
l
l
l
l
l
H
L
l
L
L
l
l
l
l
l
l
H
l
L
L
l
l
l
l
l
l
l
H
L
L
l
l
l
l
l
l
l
L
H
L
l
l
l
l
l
l
L
L
L
H
H
H
L
X
X
X
X
X
2-296
OUTPUTS
SELECT
Gl
X
GL
Output corresponding to stored address, l;
all others, H
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265
Y4
YS
Y6
Y7
SN54HCT237, SN74HCT237
3-LlNE TO B-LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ±
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±
Continuous current through Vee or GND pins ................................ "
±
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ...............
Lead temperature 1,6 mm (1/16 in) from case for 10 s: N package ...................
Storage temperature range ......................................... -65°C to
to 7 V
20 mA
20 mA
25 mA
50 mA
300°C
260°C
150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
II
(I)
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Q)
U
recommended operating conditions
'$
SN54HCT237
MIN NOM MAX
Vee
Supply voltage
VIH
High-level input voltage
4.5
I Vee = 4.5 V to 5.5 V
I Vee = 4.5 V to 5.5 V
5
5.5
2
SN74HCT237
MIN NOM MAX
4.5
5
en
V
5.5
2
o
:E
o
V
VIL
Low-level input voltage
0
0.8
0
0.8
V
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
0
tt
Input transition (rise and fall) times
Vee
500
0
Vee
500
ns
TA
Operating free-air temperature
125
-40
85
°e
0
-55
Q)
c
UNIT
::E:
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
VCC
SN54HCT237 SN74HCT237
TA - 25°C
MIN
TYP MAX
MIN MAX
MIN MAX
VI = VIH or VIL, 10H = -20 pA
4.5 V
4.4 4.499
TEST CONDITIONS
VI = VIH or VIL, 10H = -4 rnA
4.5 V
VI - VIH or VIL, 10L - 20 ~A
4.5 V
VI - VIH or VIL, 10L - 4 rnA
II
lee
VOL
l>lee*
ei
3.98
4.30
3.7
0.001
0.1
4.5 V
0.17
VI = Vee or 0
5.5 V
VI - Vee or 0, 10 - 0
One input at 0.5 V or 2.4 V,
5.5 V
Other inputs at 0 V or Vee
5.5 V
UNIT
4.4
4.4
V
3.84
0.26
0.1
0.4
0.1
0.33
±0.1 ±100
±1000
±1000
V
nA
8
160
80
~A
1.4
2.4
3.0
2.9
rnA
3
10
10
10
pF
4.5 to
5.5 V
*This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or Vee.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-297
SN54HCT237. SN74HCT237
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vcc
Pulse duration.
tsu
Setup time. A. B. and C before GL I
th
::J:
o
s::
ot/)
Gi: low
tw
Hold time. A, B. and C after
Gi:t
SN54HCT237 SN74HCT237
TA - 25°C
4.5 V
MIN
26
5.5 V
23
35
30
4.5 V
15
23
19
5.5 V
4.5 V
14
17
5
21
5
5.5 V
5
5
5
MAX
MIN
39
MAX
MIN
33
MAX
UNIT
ns
ns
5
ns
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
c
CD
<
(;'
TO (OUTPUT)
tpd
A, B. e
Any
tpd
G2
Any
tpd
G1
Any
tpd
GC
Any
CD
tn
FROM (INPUT)
tt
Any
VCC
SN54HCT237 SN74HCT237
TA = 25°C
4.5 V
TYP
24
MAX
38
5.5 V
20
34
51
43
4.5 V
19
29
44
36
5.5 V
16
26
40
32
4.5 V
29
44
36
5.5 V
19
16
26
40
32
4.5 V
29
42
63
52
5.5 V
25
36
57
47
4.5 V
12
11
15
22
19
14
20
17
5.5 V
MIN
No load. TA - 25°e
Power dissipation capacitance
NOTE 1~ Load circuit and voltage waveforms are shown in Section 1.
2-298
MIN
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MAX
57
MIN
MAX
48
UNIT
ns
ns
ns
ns
ns
85 pF typ
SN54HC238, SN74HC238
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
D2804, MARCH 1984-REVISED JUNE 1989
•
SN54HC238 , .• J PACKAGE
SN74HC238 ..• ot OR N PACKAGE
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
•
Incorporates 3 Enable Inputs to Simplify
Cascading and/or Data Reception
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
ITOP VIEW)
A
B
C
G2A
G2B
G1
Y7
GND
VCC
YO
Y1
Y2
Y3
Y4
Y5
Y6
II
SN54HC238 ... FK PACKAGE
(TOP VIEW)
description
U
U uo
co<{z>>-
The 'HC238 circuit is designed to be used in
high-performance memory-decoding or datarouting applications requiring very short
propagation delay times. In high-performance
memory systems, this decoder can be used to
minimize the effects of systems decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of this
decoder and the enable time of the memory are
usually less than the typical access time of the
memory. This means that the effective system
delay introduced by the decoder is negligible.
The conditions at the binary select inputs and the
three enable inputs select one of eight input
lines. Two active-low and one active-high enable
inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can
be implemented without external inverters and
a 32-line decoder requires only one inverter. An
enable input can be used as a data input for
demultiplexing applications.
3
C
G2A
NC
G2B
G1
2
1 2019
4
18
5
17
16
6
15
14
8
NC
Y3
Y4
9 1011 1213
..... autO'"
>-zz>->Cl
NC - No internal connection
tContact the factory for 0 availability.
The SN54HC238 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC238 is
characterized for operation from - 40°C to
85°C.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications par the terms of Texas Instruments
:~~~~:~~i~ai~:I~~~ ~::i~~ti:r :1~O::~:::::t:~~S not
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 15265
Copyright @ 1989, Texas Instruments Incorporated
2-299
SN54HC23B. SN74HC23B
3·UNE TO B·UNE DECODERS/DEMULTIPLEXERS
logic symbols (alternatives) t
BIN/OCT
A (11
(14) VI
B (21
2
(13) V2
C (31
3
(121 V3
4
5
EN
:x:
DMUX
(15) VO
0
6
7
}~
(111
0
2
(131 V2
3
(121 V3
4
(91 V6
6
5
V7
7
o
i:
o
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for D. J. and N packages.
c
logic diagram (positive logic)
en
CD
<
(;'
CD
en
VO
A (11
VI
V2
Y3
V4
V5
V6
V7
Pin numbers shown are D. J. and N packages.
2-300
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
vo
(141 VI
V4
(101 V5
(71
(151
(111
V4
(101 V5
(91 V6
171
V7
SN54HC238. SN14HC238
3-UNE TO 8-UNE DECODERS/DEMULTIPLEXERS
FUNCTION TABLE
INPUTS
ENABLE
Gl
OUTPUTS
SELECT
G2A G2B
C
B
A
VO
VI
V2
V3
V4
V5
V6
V7
X
H
X
X
X
X
L
L
L
L
L
L
L
L
X
L
X
X
H
X
L
L
L
L
L
L
L
X
X
X
L
X
X
X
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
H
L
L
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
L
H
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
H
L
L
H
L
H
L
L
L
L
L
H
L
L
L
L
H
H
L
L
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
L
L
L
L
L
H
FJ
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K (Va < 0 or Va > Vee) ............................. ± 20 rnA
eontinuous output current, 10 NO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 rnA
eontinuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Lead temperature 1,6 rnrn (1116 in) from case for 60 s: FK or J package ............... 300 0 e
Lead temperature 1,6 mrn (1/16 in) from case for lOs: D or N package ............... 260 0 e
Storage temperature range ......................................... - 65 °e to 150 0 e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under •• recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC238
vee
VIH
Supply voltage
High-level input voltage
Vee
Vee
Vee
Vee
VIL
Low-Iftvel input voltage
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
MIN
NOM
MAX
2
5
6
SN74HC238
MIN NOM MAX
2
1.5
1.5
3.15
3.15
4.2
4.2
5
6
UNIT
V
V
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
V
VI
Input voltage
0
Vee
0
Vee
V
Va
Output voltage
0
Vee
1000
0
Vee
1000
V
500
400
ns
85
De
0
Vee - 2 V
tt
Input transition (rise and fall) times
Vee
Vee
TA
= 4.5 V
=6V
0
0
-55
Operating free-air temperature
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
500
400
125
0
a
0
-40
2-301
SN54HC23B. SN74HC23B
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
C
CD
<
cr
CD
en
SN74HC238
MIN
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
5.9 5.999
5.9
5.9
VI - VIH or VIL. 10H -
4 mA
4.5 V
3.98
3.7
3.84
VI - VIH or VIL. 10H -
- 5.2 mA
6V
5.48
= VIH
or VIL. 10H
=
-20
6V
= VIH
or VIL. 10L
=
20
!LA
VOL
VI = VIH or VIL. 10L = 4 mA
VI - VIH or VIL. 10L - 5.2 mA
tn
MAX
!LA
VI
s:
o
MIN
1.9 1.998
VOH
o
SN54HC238
2V
VI
:x::
TA - 25°C
MIN
TYP MAX
II
VI - VCC or 0
ICC
Ci
VI
=
VCC or O. 10 - 0
4.30
5.80
MAX
UNIT
V
5.34
5.2
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1 ±100
±1000
±1000
nA
6V
8
160
80
!LA
10
10
10
pF
2 to 6 V
3
V
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tpd
tt
FROM (INPUT)
A. B. or C
Enable
TO (OUTPUT)
VCC
Any
Any
Any
TA - 25°C
MIN TYP MAX
2V
67
180
4.5 V
20
6V
2V
15
60
4.5V
17
6V
13
MIN
MAX
SN74HC238
MIN
MAX
270
225
36
54
45
31
155
46
235
38
195
31
47
39
26
40
33
2V
38
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
No load. TA
Power dissipation capacitance
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-302
SN54HC238
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
= 25°C
UNIT
85 pF typ
ns
ns
ns
SN54HCT238, SN74HCT238
3-L1NE TO B-L1NE DECODERS/DEMULTIPLEXERS
02804. MARCH 1984-REVISEO JUNE 1989
•
Inputs are TTL-Voltage Compatible
•
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
•
Incorporates 3 Enable Inputs to Simplify
Cascading and/or Data Reception
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HCT238 •.. J PACKAGE
SN74HCT238 ... ot OR N PACKAGE
ITOP VIEW}
A
B
e
G2A
G2B
Gl
Y7
GND
Vee
YO
Yl
Y2
Y3
Y4
Y5
Y6
fI
en
Q)
o
SN54HCT238 ... FK PACKAGE
ITOP VIEW}
description
U
':;
Q)
U
uo
CIlZZ»
(!)
NC - No internal connection
t Contact the factory for 0 availability.
The SN54HCT238 is characterized for operation
over the full military temperature range of
-55 DC to 125 DC. The SN74HCT238 is
characterized for operation from - 40 DC to
85 D C.
PRODUCTIOM DATA documllllla contain informltio.
c.rn.t I. of publiClti•• d_ Pr.ducll conform to
..,oclflCltio.. per tho tarms of Ta,," Inltrumanll
=ri~"i~:I':.'li =~~i:; :'I.::=~" not
Copyright © 1989, Texas Instruments Incorporated
TEXAS . "
INSTRUMENlS
POST OfFICE BOX 655012 • DALLAS, TEXAS 75265
2-303
SN54HCT23B. SN74HCT23B
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
logic symbols (alternatives)t
BIN/OCT
A (1)
B (2)
C (3)
0
(15)
DMUX
vo
A (1)
(14) Vl
B (2)
(13) V2
C (3)
2
2
4
3
4
&
5
EN
6
}~
(12) V3
V4
(10) V5
&
(13) V2
2
4
5
V6
6
V7
7
7
n
s::
orn
c
CD
t These symbols are in accordance with ANSI/IEEE Std 91·1984 and IEC Publication 617·12.
Pin numbers shown are for D, J, and N packages.
logic diagram (positive logic)
<
c;'
CD
vo
tn
A
(1)
B
(2)
V1
V2
c
(3)
V3
V4
V5
Gl (6)
V6
G2A ...;.(4';';)_-<1
V7
Pin numbers shown are for 0, J, and N packages.
2·304
(12) V3
(11)
V4
(10) V5
(9) V6
(7)
(7)
l:
vo
(14) Vl
3
(11)
(9)
(15)
0
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
V7
SN54HCT23B, SN74HCT23B
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
FUNCTION TABLE
INPUTS
ENABLE
G1
OUTPUTS
SELECT
C
B
A
VO
V1
V2
V3
V4
V5
V6
V7
X
G2A G2B
H
X
X
X
X
L
L
L
L
L
L
L
L
X
X
H
X
X
X
L
L
L
L
L
L
L
L
L
X
X
L
X
L
L
H
L
L
L
L
L
L
L
L
L
X
L
L
H
X
L
L
L
L
L
H
L
L
L
L
H
L
H
L
L
L
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
L
L
H
L
L
H
L
L
L
L
L
L
H
L
L
L
H
H
L
L
H
L
H
L
L
L
L
H
L
L
L
L
H
H
L
L
L
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
L
L
L
L
L
H
L
•
en
CD
U
':;
CD
C
absolute maximum ratings over operating free-air temperature ranget
Supply voltage, Vee ................................................. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vec) .................................. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vec) .............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) ................................. ± 25 mA
Continuous current through VCC or GND pins ................................... ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ................ 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ................. 260°C
Storage temperature range .......................................... - 65·C to 150°C
(/)
o
:E
(.)
::::t
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absoJute~maximum-rated conditions "for extended periods may affect device reliability.
recommended operating conditions
SN54HCT238
NOM MAX
MIN
Vee Supply voltage
VIH High-level input voltage
Low-level input voltage
VIL
VI
Input voltage
Vo
Output voltage
tt
Input transition (rise and fa'" times
TA
Operating tree-air temperature
I Vee
I Vee
4.5
2
0
0
0
0
-55
= 4.5 V to 5.5 V
= 4.5 v to 5.5 V
TEXAS
.Jf
INSTRUMENTS
POST OFFICE BOX 655012 ,. DALLAS, TEXAS 75265
5
5.5
0.8
Vee
Vee
500
125
SN74HCT238
MIN
NOM
MAX
4.5
2
0
0
0
5
5.5
0
-40
UNIT
V
v
0.8
v
Vee
v
vee
V
500
85
ns
°e
2-305
SN54HCT238, SN74HCT238
3·L1NE TO 8·L1NE DECODERS/DEMULTIPLEXERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
VOL
II
lee
<1lee t
TEST CONDITIONS
VI
VI
= VIH or VIL,
= VIH or VIL,
10H
10H
VCC
= - 20 pA
= -4 rnA
4.5 V
4.q V
VI - VIH or VIL, 10L - 20 pA
4.5 V
VI - VIH or VIL, 10L - 4 rnA
4.5 V
VI = Vee or 0
VI - Vee or 0, 10 - 0
One input at 0.5 V or 2.4 V,
5.5 V
TA - 25°C
MIN
TYP MAX
4.4 4.499
3.98
4.4
4.30
0.001
0.17
Other inputs at 0 V or Vee
4.5 to
ei
5.5 V
UNIT
4.4
3.7
V
3.84
0.1
0.1
0.1
0.26
0.4
0.33
±0.1 ±100
±1000
±1000
5.5 V
5.5 V
SN54HCT238 SN74HCT238
MIN MAX
MIN MAX
V
nA
8
160
80
pA
1.4
2.4
3
2.9
rnA
3
10
10
10
pF
tThis is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or Vee.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
tpd
A, B, or e
Any
tpd
Enable
Any
tt
Any
TA - 25°C
MIN TYP MAX
4.5 V
21
36
54
45
5.5 V
18
32
49
41
4.5 V
21
33
50
42
5.5 V
17
30
45
38
4.5 V
11
15
22
19
5.5 V
9
14
20
17
MIN
No load, TA = 25°C
Power dissipation capacitance
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-306
SN54HCT238 SN74HCT238
VCC
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MAX
MIN
MAX
UNIT
85 pF typ
ns
ns
ns
SN54HC239, SN74HC239
DUAL 2·UNE TO 4·UNE DECODERS/DEMULTIPLEXERS
02804. MARCH 1984-REVISEO JUNE 1989
•
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
•
Incorporates 2 Enable Inputs to Simplify
Cascading and/or Data Reception
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC239 ••. J PACKAGE
SN74HC239 .•. ot OR N PACKAGE
(TOP VIEW)
1<3
lA
lB
lYO
lYl
lY2
lY3
GND
VCC
2<3
2A
2B
2YO
2Yl
2Y2
2Y3
SN54HC239 ... FK PACKAGE
(TOP VIEW)
description
U
The 'HC239 circuit is designed to be used in
high-performance memory-decoding or datarouting applications requiring very short
propagation delay times. In high-performance
memory systems this decoder can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of this
decoder and the enable time of the memory are
usually less than the typical access time of the
memory. This means that the effective system
delay introduced by the decoder is negligible.
The 'HC239 is comprised of two individual twoline to four-line decoders in a single package. The
active-low enable input can be used as a data
line in demultiplexing applications. These
decoders/demultiplexers feature fully buffered
inputs, each of which represents only one
normalized load to its driving circuit.
~I~ ~ ~I~
3
lB
lYO
NC
lYl
lY2
1 2019
2
4
18
5
17
6
16
15
14
8
9 10 11 12 13
MOUMN
>-zz>->-C!)
C"IIN
NC-No internal connection
tContact the factory for 0 availability
The SN54HC239 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74HC239 is characterized for operation from -40°C to 85°C.
logic symbols (alternatives):!:
XIV
o
OMUX
(4) lYO
O} 0
lA (2)
(5) 1Yl
2
(6) lY2
3
(7) lY3
1
o
G-
(4)1Y0
(5)1Yl
3
(6)1Y2
3
(7) lY3
(12) 2YO
(12) 2YO
(11) 2Yl
(11) 2Yl
(10) 2Y2
(10) 2Y2
(9) 2Y3
(9) 2Y3
*These symbols are in accordance with ANSIIIEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
PRODUCTION DATA documents contain information
currant as of publication date. Products canform to
specifications par the tarms of T.xls Instruments
:~~~::~~i;ar::,~li ~!::i:~i:; :'1U::~::~::.s nat
Copyright © 1989, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-307
SN54HC239, SN74HC239
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
logic diagram (positive logic)
12)
SELECT
INPUTS
{
lA
lB (3)
DATA
OUTPUTS
::r::
n
3:
ENABLE 2(; 115)
otn
C
CD
<
5'
CD
(I)
Pin numbers shown are for D, J, and N packages.
FUNCTION TABLE
INPUTS
ENABLE
OUTPUTS
SELECT
G
B
A
H
X
X
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
H
L
L
L
L
H
H
L
L
L
L
H
L
L
L
H
H
VO V1
V2 V3
absolute maximum ratings over operating free·air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ± 20 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
eontinuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300 0 e
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260 0 e
Storage temperature range ......................................... - 65 °e to 150 0 e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2-308
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN54HC239. SN74HC239
DUAL 2-UNE TO 4-UNE DECODERS/DEMULTIPLEXERS
recommended operating conditions
SN54HC239
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
Vee Supply voltage
1.5
1.5
Vee = 4.5 V
3.15
3.15
=6V
=2V
= 4.5 V
4.2
4.2
Vee = 2 V
VIH
High-level input voltage
Vee
Vee
VIL
Low-level input voltage
SN74HC239
MIN
Vee
Vee = 6 V
UNIT
V
V
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
0
Vee
1000
V
It
Input transition (rise and fall) times
Vee
1000
500
500
ns
400
0
-40
0
0
Vee - 2 V
Vee
Vee
=
=
4.5 V
0
-55
6 V
Operating free-air temperature
TA
0
0
125
fI
V
CI)
CD
(,)
'S;
400
CD
De
85
C
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VIH or VIL. 10H
=
-20
VI - VIH or VIL. 10H
=
=
-4 rnA
VI
=
VCC
2V
4.5 V
~A
6V
VOH
VI
VI
=
=
VIH or VIL, 10H
VIH or VIL, 10L
=
4.5 V
6V
- 5.2 rnA
20 ~A
VOL
VI - VIH or VIL, 10L - 4 rnA
VI = VIH or VIL, 10L
VI = Vee or 0
II
lee
ej
=
TA - 25 DC
MIN
TYP MAX
VI - Vee or 0, 10 - 0
MIN
MAX
SN74HC239
MIN
1.9 1.998
1.9
1.9
4.4 4.499
4.4
4.4
5.9 5.999
5.9
5.9
3.7
3.84
3.98
5.48
4.30
5.80
5.2
MAX
l:
V
5.34
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15 0.26
±0.1 ±100
0.4
±1000
0.33
±1000
nA
6V
8
160
80
~
10
10
10
pF
2 to 6 V
3
::E
o
UNIT
2V
6V
5.2 rnA
SN54HC239
en
0
V
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
TA = 25 DC
MIN TYP MAX
SN54HC239
62
150
225
190
18
30
45
38
6V
14
26
38
32
2V
4.5 V
53
14
120
180
150
24
36
30
6V
11
20
31
26
2V
38
75
110
95
4.5 V
8
6
15
22
19
13
19
16
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC
2V
tpd
A or B
Y
4.5 V
tpd
Ipd
G
y
Y
6V
MIN
MAX
No load, TA = 25°e
Power dissipation capacitance per decoder
SN74HC239
MIN
MAX
UNIT
ns
ns
ns
25 pF typ
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-309
E
:::t:
(")
s:
oen
c
CD
<
C:;"
CD
en
2-310
SN54HC240, SN54HC241, SN74HC240, SN74HC241
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
02684, OECEM8ER 1982-REVISEO JUNE 1989
•
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
•
High-Current Outputs Drive Up to 15 LSTTL
Loads
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC'" ,JPACKAGE
SN74HC' ... ow OR N PACKAGE
(TOP VIEW)
Vee
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
iG/2G*
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
GND
description
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of three-state memory address drivers.
clock drivers, and bus-oriented receivers and
transmitters. The designer has a choice of
selected combinations of inverting and
noninverting outputs, symmetrical G (active-low
output control) inputs, and complementary G
and G inputs. These devices feature high fanout.
II
SN54HC' ... FK PACKAGE
(TOP VIEW)
3
1A2
2Y3
1A3
2Y2
1A4
The SN54HC' family is characterized for
operation over the full military temperature range
of - 55°C to 125°C. The SN74HC' family is
characterized for operation from - 40°C to
85°C.
2
1 20 19
4
18
5
17
6
16
7
14
8
1Y1
2A4
1Y2
2A3
1Y3
9 1011 12 13
-0-""'("11
>z-__+-~(1:.::6:....)
(14)
1Yl
1Y2
1Y3
>-___-:..(1:.=2:....)
1Y4
(11)
>-__+-_(:.:.9:....)
2Yl
(13)
>-__+-_(~7:....)
2Y2
(15)
> __+_..:;(5:.:,)_
2Y3
(17)
>-___--'("'3)'-
2Y4
(19)
Pin numbers shown are for OW, J, and N packages.
2-312
(18)
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54HC240. SN54HC241. SN74HC240. SN74HC241
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature ranget
Supply voltage, Vee ................................................. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) .................................. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) .............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) ................................. ±35 mA
Continuous current through Vee or GNO pins ................................... ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ................ 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package ............... 260°C
Storage temperature range .......................................... - 65°C to 150°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute~maximum-rated conditions for extended periods may affect device reliability.
fI
en
CD
U
recommended operating conditions
"S;
SN54HC240
SN54HC241
MIN
2
1.5
3.15
4.2
Vee Supply voltage
VIH
High-level input voltage
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
VIL
Low-level input voltage
Vee = 2 V
Vee = 4.5 V
0
0
Vee = 6 V
0
0
0
0
Input voltage
VI
Vo
Output voltage
tt
Input transition (rise and fall) times
Vee - 2 V
Vee = 4.5 V
0
0
-55
Vee = 6 V
TA
Operating free-air temperature
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
NOM
5
CD
SN74HC240
SN74HC241
MAX
6
MIN
2
1.5
NOM
5
UNIT
3.15
4.2
0.3
0.9
1.2
Vee
Vee
1000
500
400
125
0
0
0
0
0
0
0
0
-40
CI)
MAX
6
v
V
0.3
0.9
1.2
C
o
::E
o
::E:
V
Vee
Vee
1000
V
V
500
ns
400
85
·e
2-313
SN54HC240. SN54HC241. .SN74HC240. SN74HC241
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
VI = VIH or VIL, 10H
=
-20 pA
VOH
VI = VIH or VIL, 10H = -6 rnA
VI = VIH or VIL, 10H = -7.8 rnA
VI
= VIH
or VIL, 10L
= 20 pA
VOL
= VIH or VIL,
= VIH or VIL,
VI = Vee or 0
Vo = Vee or 0
VI
VI
II
10Z
ICC
ej
2-314
10L = 6 rnA
10L = 7.8 rnA
VI - Vee or 0, 10 - 0
TYP
2V
4.5 V
SV
4.5 V
6V
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.80
5.48
2V
4.5 V
0.002
0.001
6V
4.5 V
SV
0.001
0.17
SV
6V
SV
SN54HC240
SN54HC241
TA - 25°C
0.15
±0.1
±0.01
2 to S V
MAX
MIN
1.9
4.4
MAX
5.9
3.7
5.2
0.1
0.1
0.1
0.26
0.2S
±100
±0.5
8
3
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
10
SN74HC240
SN74HC241
MIN
1.9
4.4
5.9
UNIT
MAX
V
3.84
5.34
0.1
0.1
0.1
0.4
0.4
±1000
±10
lS0
10
0.1
0.1
0.1
0.33
V
0.33
±1000
nA
±5
80
pA
pA
10
pF
SN54HC240, SN74HC240
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
tpd
A
Y
ten
G
Y
tdis
G
Y
Y
tt
vcc
TA - 25°C
MIN TYP MAX
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
50
10
9
75
15
13
44
22
21
28
8
6
SN54HC240
MIN
MAX
100
20
17
150
30
26
150
30
26
60
12
10
SN74HC240
MIN
150
30
25
225
45
38
225
45
38
90
18
15
MAX
UNIT
125
25
21
190
38
32
190
38
32
75
15
13
ns
ns
en
ns
G)
Co)
'S
ns
G)
c
U)
o
35 pF typ
No load, TA = 25°C
Power dissipation capacitance per buffer
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 150 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
tpd
A
Y
ten
G
Y
tt
Y
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN TYP MAX
75
15
13
100
20
17
45
17
13
150
30
26
200
40
34
210
42
36
SN54HC240
MIN
MAX
225
45
38
300
60
51
315
63
53
SN74HC240
MIN
MAX
190
38
32
250
50
43
265
53
45
:!
(.)
::J:
UNIT
ns
ns
ns
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-315
SN54HC241, SN74HC241
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
::E:
FROM (INPUT)
TO (OUTPUT)
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
y
tpd
A
ten
G or
G
y
tdis
G or
G
y
o
3:
oen
cCD
<
(;'
CD
o
Y
tt
Vcc
iA - 25 e C
MIN TYP MAX
39
115
12
23
11
20
60
150
17
30
15
26
40
150
18
30
17
26
28
60
8
12
10
6
SN54HC241
MIN
MAX
170
34
29
225
45
38
225
45
38
90
18
15
No load, TA = 25°C
Power dissipation capacitance per buffer
SN/4HC24i
MIN MAX
145
29
25
190
38
32
190
38
32
75
15
13
UN)T
ns
ns
ns
ns
35 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 150 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
tpd
A
Y
ten
G orG
y
tt
Y
vcc
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN TYP MAX
50
165
16
33
14
28
100
200
20
40
17
34
45
210
17
42
13
36
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-316
TEXAS . "
INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS, TExAS 75265
SN54HC241
MIN MAX
245
49
42
300
60
51
315
63
53
SN74HC241
MIN MAX
210
42
35
250
50
43
265
53
45
UNIT
ns
ns
ns
SN54HCT240. SN54HCT241. SN74HCT240. SN74HCT241
OCTAL BUFFERS AND LINE DRIVERS CMOS LOGIC
WITH 3·STATE OUTPUTS
02804, MARCH 1984-REVISEO JUNE 1989
SN54HCT'" .JPACKAGE
SN74HCT' ... ow OR N PACKAGE
•
Inputs are TTL-Voltage Compatible
•
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
•
High-Current Outputs Drive Up to 15 LSTTL
Loads
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
(TOP VIEW)
Vee
1G
•
1A1
Dependable Texas Instruments Quality and
Reliability
description
2G/2G*
2Y4
1Y1
1A2
2A4
2Y3
1Y2
1A3
2A3
2Y2
1Y3
1A4
2A2
2Y1
1Y4
GND
2A1
FJ
SN54HCT' , , , FK PACKAGE
.
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of three-state memory address drivers,
clock drivers, and bus-oriented receivers and
transmitters, The designer has a choice of
selected combinations of inverting and
noninverting outputs, symmetrical G (activelow output control) inputs, and complementary
G and G inputs, These devices feature high
fan-out,
(TOP VIEW)
(!l
'¢ ..........
UN
~ ~ ~ ;;'(~
3
2 1 2019
4
5
18
1Y1
17
2A4
6
16
1Y2
7
15
2A3
14
1Y3
8
The SN54HCT' family is characterized for
operation over the full military temperature range
of - 55 °e to 125 °e. The SN74HCT' family is
characterized for operation from - 40°C to
85°C.
9 1011 12 13
*213 for 'HCT240, or 2G for 'HCT241
logic symbols t
'HCT241
'HCT240
1<3
lG
lAl
lAl
lA2
lA3
lA4
1Vl
1V2
1V3
(18)
lYl
(16)
1V2
(14)
lY3
(12)
1V4
lA2
1V4
lA3
lA4
2Al
2A2
2Yl
2Y2
2Al
2A2
(13)
(7)
2A3
2A4
2Y3
2Y4
(151
2A3
(17)
2A4
(3)
213
2G
(9)
(51
2Yl
2Y2
2Y3
2Y4
tThese symbols are in accordance with ANSI/IEEE Std 91·1984 and IEC Publication 617-12,
Pin numbers shown are for OW. J, and N packages.
PRODUCTION DATA d••uments.ontain information
current IS of publication datI. Praducts confarm to
specifications par the terms af TIXII Instruments
::::~~i;ai:I~'~ =~~~i:.n :.r:.,::~~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
Copyright © 1989, Texas Instruments Incorporated
2-317
SN54HCT240, SN54HCT241, SN74HCT240, SN74HCT241
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
FUNCTION TABLES
'HCT240
lEACH BUFFERI
E
INPUTS
A
G
H
L
L
L
X
H
OUTPUT
Y
L
H
Z
'HCT241
(EACH BUFFER !N FIRST S5T)
INPUTS
OUTPUT
lG
lA
1Y
H
L
H
L
L
L
Z
H
X
'HCT241
{EACH
BUff~;:;
INPUTS
2G
2A
H
H
H
L
L
X
It,; SECOND SEi;
OUTPUT
2Y
H
L
Z
logic diagram (positive logic)
'HCT241
'HCT240
::r::
(')
:s::
lG
lG ....;.;./l...
l_a
oen
c
<
c:r
CD
/11
lAl ...:.::(2L,.1- - - - t
/181
1Yl
lA 1 ...:.::(2...
1----t
(18)
1Yl
lA2 ..:.:(4L,.1- - - - t
(161
1Y2
lA2 ...;.;(4.:..1- - - - t
(16)
1Y2
lA3 ...;.;;(6....
1 _ _ _-1
(141
1Y3
1- - - - t
lA3 ...:.::(6L.
(14)
1Y3
lA4 -:.;;(8L,.1- - - - t
(121
1Y4
lA4 ...;,;;/8.:..1- - - - I
CD
(I»
1Y4
2G
(191
~>-_+_...:.(9;;.:1_ 2Yl
2Al
(111
> __-+_..;/;;.:9)_
2Yl
2A2 _(:.;.1;::31_ _ _-t
.x>-_-t-_/;.;.7...
1 2Y2
2A2
(131
> __-+-_;.;.(7...
)
2Y2
2A3
/151
><:>-_+-_(:,::5:...1 2Y3
2A3
(15)
> __+_:.::/5:...)
2Y3
2A4
/171
><>-_ _ _...:./3:;.:.1_ 2Y4
2A4
(17)
> ____...:./3:;.:.1_
2Y4
2G
(191
2Al
(111
Pin numbers shown are for OW, J, and N packages.
2-318
>-___.....:.:/1""21'-
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HCT240, SN54HCT241, SN74HCT240, SN74HCT241
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
eontinuous current through Vee or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1'16 in) from case for 60 s: FK or J package ............... 300 De
Lead temperature 1,6 mm (1116 in) from case for. 10 s: OW or N package. . . . . . . . . . . . .. 260 De
Storage temperature range ......................................... - 65 De to 1 50 De
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
-S;
SN54HCT240
SN54HCT241
MIN NOM MAX
Vo
tt
TA
Supply voltage
High-level input voltage
Low-level input voltage
I Vee
I Vee
en
Q)
U
recommended operating conditions
Vee
VIH
VIL
VI
II
4.5
2
0
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
Input voltage
Output voltage
5
0.8
0
0
0
-55
Input transition (rise and falll times
Operating free-air temperature
5.5
Vee
Vee
500
125
SN74HCT240
SN74HCT241
MIN NOM MAX
4.5
5
5.5
2
0
0
0
0
-40
Q)
Q
UNIT
0.8
Vee
Vee
500
en
o
V
V
V
:!
v
v
:x:
u
ns
De
85
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
VOL
II
10Z
ICC
.1lee*
ei
TEST CONDITIONS
VI - VIH or VIL.
VI = VIH or VIL,
VI = VIH or VIL,
VI - VIH or VIL,
TVP
MIN
4.4 4.499
4.30
3.98
0.001
0.17
MAX
5.5 V
5.5 V
5.5 V
±0.1
±0.01
±100
±0.5
5.5 V
4.5 to
5.5 V
10H - -20 ~A
10H = -6 mA
4.5 V
4.5 V
10L = 20 pA
10L - 6 mA
4.5 V
4.5 V
VI = Vee or 0
Vo = Vee or 0,
VI = VIH or VIL
VI - Vee or 0,
10 - 0
One input at 0.5 V or 2.4 V
Other inputs at 0 V or Vee
TA - 25°C
VCC
0.1
0.26
SN54HCT240 SN74HCT240
SN54HCT241 SN74HCT241
MIN MAX
MIN MAX
4.4
4.4
3.84
3.7
0.1
0.4
±1000
8
±10
160
1.4
2.4
3
10
UNIT
V
0:1
0.33
V
±1000
±5
nA
~A
80
~A
3.0
2.9
mA
10
10
pF
* This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or Vee.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-319
SN54HCT240. SN54HCT241. SN74HCT240. SN74HCT241
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL
50 pF (see Note 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
G orG
y
PARAMETER
tdis
%
G orG
y
Y
tt
(")
3:
oen
C
(1)
MIN
Sr-l54HCi240
Sn;i4HCI~40
SN54HCT241
SN74HCT241
M)N MAX
TYP
MAX
4.5 V
13
25
37
32
5.5 V
12
23
33
29
4.5 V
21
35
53
44
5.5 V
19
32
48
40
4.5 V
19
35
53
44
5.5 V
18
32
48
4.5 V
8
12
18
40
15
5.5 V
7
11
16
14
MIN
MAX
UNIT
ns
ns
ns
ns
40 pF typ
No load, TA = 25 DC
Power dissipation capacitance per buffer
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 150 pF (see Note 1)
<
5'
(1)
en
TA - 2S D C
vCC
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
G orG
y
PARAMETER
tt
Y
SN54HCT240 SN74HCT240
TA - 25 D C
VCC
MIN
SN54HCT241
MAX
4.5 V
20
42
63
53
5.5 V
19
38
56
48
4.5 V
25
52
79
65
5.5 V
4.5 V
22
17
47
42
71
59
63
53
5.5 V
14
38
57
48
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-320
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
MIN
MAX
SN74HCT241
TYP
MIN
UNIT
MAX
ns
ns
ns
SN54HC242, SN54HC243
SN74HC242, SN74HC243
QUADRUPLE BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
02684. DECEMBER 1982 - REV1SED JUNE 1989
•
2-Way Asynchronous Communication
Between Data Buses
•
High-Current Outputs Can Drive Up to 15
LSTTL Loads
•
Package Options Include Ceramic Chip
Carriers and Standard Plastic and Ceramic
300-mil DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC242. SN54HC243 ... J PACKAGE
SN74HC242. SN74HC243 ... N PACKAGE
(TOP VIEWI
G1
NC
A1
A2
A3
A4
GND
VCC
G2
NC
B1
82
B3
B4
fI
SN54HC242. SN54HC243 ... FK PACKAGE
description
These parts differ from their TTL counterparts
(LS, ALS, and AS) in that these CMOS parts do
not have a bus-latching mode in which both the
outputs are simultaneously enabled. Instead of
this latched mode, the buses are isolated, thus
preventing potential bus conflicts if both buses
are active. However, with the exception of the
fourth line of the function table, their functional
operation is identical to their TTL counterparts.
The two enables have been renamed G1 and G2
since they work together to determine the
direction of transmission rather than each enable
controlling one direction independently of the
other. Whenever G1 and G2 are at opposite logic
levels with respect to each other, isolation
between buses results.
In
(TOP VIEWI
These four-data line tranceivers are designed for
asynchronous two-way communications
between data buses. The SN74HC' devices can
be used to drive terminated lines down to 133 n.
CD
(J
U
'S;
U ~ U UN
Z(!)z>(!)
CD
3
A1
c
2 1 20,19
en
4
18
5
17
6
16
o
8
15
14
o
:::e:
:J:
9 1011 1213
NC- No internal connection
The SN54HC' family is characterized for
operation over the full military temperature range
of - 55°C to 125°C. The SN74HC' family is
characterized for operation from - 40°C to
85°C.
FUNCTION TABLE
INPUTS
'HC242
'HC243
A to B
§to A
A to B
H
H
L
Isolation
Isolation
L
H
Isolation
Isolation
G1
G2
L
H
L
PRDDuenDI DATA d......nts contain Information
••rrent as 01 publication doto. PradoCb .onform to
lpaclflcations par tho to.... 01 To,," Instrumonts
=~~~ai:I':.1i =:~:; :.\"=~~ not
B to A
Copyright @ 1989, Texas Instruments Incorporated
TEXAS "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-321
SN54HC242, SN54HC243
SN74HC242, SN74HC243
QUADRUPLE BUS·TRANSCEIVERS WITH 3-STATE OUTPUTS
logic symbols t
'HC242
Gl
G2
ill
(131
'HC243
Gl
Gl
G2
1,2EN3
G2
(11
Gl
(131
i,2EN4
(111
AI
(101
A2
(")
::E:
A3
s:
o
tn
A4
(91
(81
(31
81
AI
82
A2
83
(51
1~~~-------t~J(9~1 83
A3 ..;;:
B4
(61
A4 - (~~.-~--------~~~J(8~1 B4
(41
C
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12
~.
logic diagrams (positive logic)
~
:
'HC243
'HC242
G2
AI~---------------+
Pin numbers shown are for J and N packages.
2-322
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC242, SN54HC243
SN74HC242, SN74HC243
QUADRUPLE BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee ................................................ -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K (Va < 0 or Va > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Continuous output current, 10 (Va = 0 to Vee) .............................. " ± 35 rnA
Continuous current through Vee or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: N package ................... 260°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 1 50°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
contitions" is not implied. Exposure to absolute·maxirnum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC242
SN54HC243
Vee
Supply voltage
Vee - 2 V
VIH
VIL
High-level input voltage
Low-level input voltage
Input
Vo
Output voltage
TA
Input transition (rise and fal1) times
Operating free-air temperature
MIN
NOM
MAX
2
5
6
UNIT
MIN
NOM
MAX
2
5
6
1.5
1.5
V
3.15
3.15
Vee ~ 6 V
4.2
4.2
Vee - 2 V
0
0.3
0
0.3
Vee ~ 4.5 V
0
0.9
0
0.9
Vee ~ 6 V
0
1.2
0
1.2
0
Vee
0
Vee
V
0
Vee
1000
0
Vee
1000
V
ns
volt~ge
VI
tt
Vee ~ 4.5 V
SN74HC242
SN74HC243
V
Vee ~ 2 V
0
Vee ~ 4.5 V
0
500
0
500
Vee ~ 6 V
0
400
0
400
-55
125
-40
85
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
0
V
°e
2-323
SN54HC242, SN54HC243
SN74HC242, SN74HC243
QUADRUPLE BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
I
I
I
I
TEST CONDITIONS
PARAMETER
I
TA - 25°C
vCC
MIN
TYP
1.9 1.998
MAX
MiN
1.9
4.4 4.499
5.9 5.999
3.98 4.30
5.48
5.80
0.002
0.1
0.001
0.1
0.001
0.1
0.17 0.26
0.15 0.26
±0.1 ±100
4.4
5.9
3.7
5.2
2V
VI
II
VI - V,H or VIL. 10H = -6 rnA
VI - V,H or V,L. 10H - -7.8 rnA
VI
::J:
o
VOL
en
II
s:o
lozt
c
ICC
Ci+
(1)
<
C;'
(1)
en
= VIH or VIL. 10H = - 20 I'A
VOH
= VIH or V,L. 10L
VI = VIH or VIL. 10L
V, - VIH or VIL. 10L
VI - Vee or 0
= 20 I'A
= 6 rnA
= 7.8 rnA
Vo = Vec or O. VI = VIH or VIL
VI = Vec or O. 10 = 0
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
6V
2 to 6 V
±0.01
3
±0.5
8
10
tFor 110 ports. the parameter is included in the off-state output current.
tThis parameter Ci does not apply to 110 ports.
2-324
SN54HC242
SN54HC243
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MAX
I
SN74HC242
SN74HC243
MIN
1.9
I
I
UNIT
MAX
4.4
5.9
3.84
5.34
V
0.1
0.1
0.1
0.4
0.4
±1000
0.1
0.1
0.1
0.33
0.33
±1000
±10
160
10
±5
80
10
V
nA
I'A
/'A
pF
SN54HC242, SN54HC243
SN74HC242, SN74HC143
QUADRUPLE BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL ... 50 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC
TA - 25°C
MIN
tpd
A or B
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
B or A
ten
Gl or G2
A or B
tdis
Gl or G2
A or B
A or B
tt
I Power dissipation capacitance per transceiver I
TYP
MAX
45
12
10
75
21
17
48
23
20
28
8
6
100
20
SN54HC242
SN74HC242
SN54HC243
SN74HC243
MIN
MAX
MIN
150
30
26
225
45
38
225
45
38
90
18
15
17
150
30
26
150
30
26
60
12
10
125
25
21
190
38
32
190
38
32
75
15
13
No load, TA - 25°C
UN)T
MAX
ns
II
ns
ns
ns
34 pF typ
switching characteristics over recommended operating free-air' temperature range (unless otherwise
noted!. CL - 150 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC
TA
MIN
tpd
A or B
B or A
ten
Gl or G2
A or 8
tt
A or B
2V
4.5 V
6V
2 V
4.5 V
6V
2V
4.5 V
6V
= 25°C
SN54HC242
SN74HC242
SN54HC243
SN74HC243
TYP
MAX
MIN
MIN
63
17
14
100
26
21
45
150
30
26
200
40
34
210
42
36
17
13
MAX
225
45
38
300
60
51
315
63
53
UNIT
MAX
190
38
32
250
50
43
265
53
45
ns
ns
ns
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-325
E
::I:
(")
3:
otJ)
c
(1)
<
(i'
(1)
en
2-326
SN54HC244, SN74HC244
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
02684, DECEMBER 1982-REVISED SEPTEMBER 1987
•
3-State Output Drive Bus Lines or Buffer
Memory Address Registers
•
High-Current Outputs Can Drive Up to 15
LSTTL Loads
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC244 , .• J PACKAGE
SN74HC244 .•• OW OR N PACKAGE
ITOPVIEW)
lG
lAI
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
VCC
2G
1Y1
2A4
1Y2
2A3
1Y3
2A2
lY4
2A1
GND
description
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of the three-state memory address
drivers, clock drivers, and bus-oriented receivers
and transmitters. Taken together with the
'HC240 and 'HC241, these devices provide the
choice of selected combinations of inverting
outputs, symmetrical G (active-low input
contro/) inputs and complementary G and G
inputs.
The SN54HC244 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC244 is
characterized for operation from - 40°C to
85°C.
SN54HC244 ... FK PACKAGE
(TOP VIEW)
3
1A2
2Y3
1A3
2Y2
1A4
2
1 2019
18
4
5
17
6
16
7
15
8
14
9 1011 1213
_C_q-N
>z<><
NC!)N-N
logic symbol t
lG
(18)
lAl
(16)
lA2
(14)
lA3
112)
lA4
1Vl
lY2
lY3
1V4
2G
(9)
2Al
(7)
2A2
2A3
2A4
liS)
IS)
(171
(3)
2Yl
2Y2
2Y3
2Y4
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
PRODUCTION DATA docoma.,. contain informotion
cu ..a.t IS of publi.atio. d.ta. Products .onform to
_ilicalio.s pir 1'" tarms of T.... 1l1li......11
=~~·i:~'li =:~ti:r :.r:::::::.~ not
Copyright @ 1982, Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-327
SN54HC244, SN74HC244
OCTAL BUFFERS AND LINE DRIVERS
WITH 3·STATE OUTPUTS
logic diagram (positive logic)
.u
lAl
II
lA2
::J:
lA3
s:o
lA4
(I)
-""'-
(2)
(18)
(4)
(16)
(6)
(14)
(8)
(12)
lVl
2Al
lV2
2A2
lV3
2A3
1Y4
2A4
.........
~19)
2(;
(II)
(9)
(13)
(7)
(15)
(5)
(17)
(3)
2V2
(")
rn
2Vl
2V3
2V4
o
(1)
<
c;'
absolute maximum ratings over operating free-air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (V, < 0 or V, > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (VO < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package .............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
(1)
(I)
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC244
Vee
Supply voltage
Vee
VIH
High-level input voltage
Vee
Vee
=2V
= 4.5 V
=6v
Vee - 2 V
VIL
Low-level input voltage
Vee
Vee
= 4.5 V
=6V
SN74HC244
MIN
NOM
MAX
2
5
6
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
UNIT
V
V
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
V
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
Vee
1000
0
Vee
1000
V
ns
tt
Input transition (rise and fall) times
Vee
Vee
Vee
TA
2·328
Operating
free~air
temperature
=2V
= 4.5 V
=6V
0
0
0
500
0
500
0
400
0
400
-55
125
'-40
85
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
°e
SN54HC244, SN74HC244
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
TEST CONDITIONS
PARAMETER
VCC
VI
=
VIH or VIL.
=
10H
- 20 p.A
VI - VIH or VIL.
VI
VI
=
=
VIH or VIL.
VIH or VIL.
10H 10H
10L
=
-6 rnA
-7.8 rnA
= 20 ~A
VOL
VI
=
VIH or VIL.
VI - VIH or VIL.
=
10L = 6 rnA
10L - 7.8 rnA
VI
10Z
Vo = Vee or O.
Vee or 0
VI = VIH or VIL
lee
ej
VI - Vee or O.
10
=0
MAX
SN74HC244
MIN
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
5.9 5.999
5.9
5.9
3.7
3.84
1.9
4.5 V
3.98
6V
5.48
4.30
5.80
5.2
MAX
UNIT
V
0.002
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.15
0.26
0.26
0.4
0.33
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
6V
±0.01
±0.5
±10
±5
~A
8
10
160
80
~A
3
10
10
pF
6V
2 to 6 V
•
5.34
2V
6V
II
MIN
1.998
2V
VOH
SN54HC244
TA - 25°C
MIN
TYP MAX
0.1
V
U)
CD
U
">CD
c
en
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), Cl = 50 pF (see Note 1)
PARAMETER
tpd
ten
tdis
tt
FROM
(INPUT)
TO
(OUTPUT)
Vee
2V
A
V
4.5 V
IT
IT
V
V
Y
TA = 25°C
MIN
TVP MAX
SN54HC244
40
115
170
145
23
20
34
29
29
6V
13
11
190
MIN
MAX
SN74HC244
MIN
MAX
2V
75
150
225
15
30
45
38
6V
13
26
38
32
190
2V
75
150
225
4.5 V
15
30
45
38
6V
13
26
38
90
32
75
2V
28
60
4.5 V
8
12
18
15
6V
6
10
15
13
No load. TA
=
25°e
CJ
::I:
ns
25
4.5 V
Power dissipation capacitance per gate
UNIT
o:2!
ns
ns
ns
35 pF typ
NOTE 1: load circuit and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75266
2-329
SN54HC244, SN74HC244
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 150 pF (see Note 1)
I
I
II
:z::
s:
oen
FRUM
(INPUT)
tpd
A
Y
ten
13
Y
tt
(')
I
PARAMETER
TO
(OUTPUT)
Y
I
I
Vec
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
i
TA - 2SoC
TYP MAX
MIN
56
165
18
33
15
28
100
200
40
20
17
34
45
210
17
42
13
36
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
c
<
n'
CD
CD
tn
2·330
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
i
i
SN54HC244
MIN MAX
245
49
42
300
60
51
315
63
53
SN74HC244
MIN MAX
210
42
35
250
50
43
265
53
45
UNIT
ns
ns
ns
SN54HCT244. SN74HCT244
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
02804. MARCH 1984-REVISEO SEPTEMBER 1987
SN54HCT244 ... J PACKAGE
SN74HCT244 ... OW OR N PACKAGE
•
Inputs are TTL·Voltage Compatible
•
3·State Outputs Drive Bus Lines or Buffer
Memory Address Registers
•
High·Current Outputs Can Drive Up to 15
LSTTL Loads
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300·mil·
DIPs
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEW)
1(3'
vee
lAl
2Y4
lA2
2Y3
lA3
2Y2
lA4
2Yl
2<3
lYl
2A4
lY2
2A3
lY3
2A2
lY4
2Al
GND
description
•
SN74HCT244 ••• FK PACKAGE
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of three-state memory address drivers,
clock drivers, and bus-oriented receivers and
transmitters. Taken together with the 'HCT240
and 'HCT241, these devices provide the choice
of selected combinations of inverting outputs,
symetrical G (active-low input control) inputs,
and complementary G and G inputs.
The SN54HCT244 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HCT244 is
characterized for operation from -40°C to
85°C.
(TOP VIEW)
U
>- ('\I
3
lA2
2Y3
lA3
2Y2
lA4
2
1 20 19
4
18
5
17
6
16
8
14
15
lYl
2A4
lY2
2A3
lY3
9 1011 12 13
-O-vN
>-z-__-t_-,(,,"9)~
2Vl
lA2 ..:;:(4.:...)- - - i
(16)
1Y2
2A2 -.:.:(1.;;3)_ _ _-1
> __+---,(...7)~
2V2
lA3 ...::(6;:..)_ _ _-I
(14)
1Y3
2A3 -.:.:(1,;;5)'--_ _-1
> __+_.:.;:;(5.:..)
2V3
1Y4
2A4 -:.;(1~7:..)- - - i
> ____.!::(3;:..)
2V4
J:
(")
s:o
lA4 ...::(8;:..)_ _ _-I
> ____...(1;.:2.:..)
(I)
cCD
absolute maximum ratings over operating free·air temperature range t
<
C:f
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (V, < 0 or V, > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vce . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300 0 e
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package .............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
CD
rn
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HCT244
Vee Supply voltage
VIH High-level input voltage
Low-level input voltage
I Vce
I Vee
SN74HCT244
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
V
V
= 4.5 V to 5.5 V
2
= 4.5 V to 5.5 V
0
0.8
0
0.8
2
V
VIL
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
0
0
Vee
500
V
0
Vee
500
no
-55
125
-40
85
°e
tt
Input transition (rise and fall) times
TA
Operating free-air temperature
2-332
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
SN54HCT244, SN74HCT244
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
TA - 25°C
MIN
TYP MAX
MAX
MIN
MIN
V, = V,H or V,L. 10L = 20 pA
4.5 V
0.001
0.1
4.5 V
0.17
0.1
0.26
0.1
V, = V,H or V,L. IOL=6mA
0.4
0.33
V, = Vee or 0
5.5 V
±0.1
±100
±1000
±1000
nA
10Z
Vo = Vee orO. V, = V,H or V,L
5.5 V
±0.01
±0.5
±10
±5
ICC
V, = Vee or O. 10 = 0
One input at 0.5 V or 2.4 V
5.5 V
8
160
80
/LA
pA
1.4
2.4
3
2.9
mA
3
10
10
10
pF
VOL
"
alee t
Other inputs at 0 V or Vee
5.5 V
3.98
4.30
4.5 to 5.5 V
ei
4.4
3.7
3.84
UNIT
V, = V,H or V,L. 10H = -20 pA
V, = V,H or V,L. 10H = -6mA
4.5 V
4.4
MAX
4.5 V
VOH
4.4 4.499
SN54HCT244 SN74HCT244
V
tThis is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or
V
fI
en
CD
(,)
"S:
Vee-
CD
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
tdis
G
G
Y
Y
Y
tt
VCC
TA - 25°C
MIN
TYP MAX
SN54HCT244 SN74HCT244
MIN
MAX
MIN
MAX
4.5 V
15
28
42
5.5 V
13
25
38
35
32
4.5 V
21
35
53
44
5.5 V
19
32
48
40
4.5 V
19
35
53
48
44
18
15
16
14
5.5 V
18
4.5 V
8
32
12
5.5 V
7
11
Power dissipation capacitance per buffer
40
o
en
o
:::i!
UNIT
CJ
::J:
ns
ns
ns
ns
40 pF typ
No load. TA = 25°C
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
(OUTPUT)
tpd
A
Y
ten
tt
G
TO
Y
Y
VCC
TA - 25°C
MIN
TYP MAX
SN54HCT244 SN74HCT244
MIN
MAX
MIN
MAX
4.5 V
5.5 V
21
18
45
40
68
61
56
51
4.5 V
25
52
79
65
5.5 V
22
47
71
59
4.5 V
17
42
63
53
5.5 V
14
38
57
48
UNIT
ns
ns
ns
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
2-333
E
J:
(")
s:
otn
C
('I)
<
c:r
('I)
en
2-334
SN54HC245. SN14HC245
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
02684. DECEM8ER 1982-REVISED JUNE 1989
•
High-Current 3-Stete Outputs Drive Bus
Lines Directly or Up to 15 LSTTL Loads
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
SN54HC245 ... J PACKAGE
SN74HC245 •.. OW OR N PACKAGE
(TOPVIEWI
•
Dependable Texas Instruments Quality and
Reliability
description
These octal bus transceivers
asynchronous two-way
between data buses. The
implementation minimizes
requirements.
are designed for
communication
control function
external timing
OIR
Vee
A1
A2
A3
A4
A5
A6
A7
A8
G
B1
B2
B3
B4
B5
B6
B7
B8
GNO
U)
Q)
(,)
">
SN54HC245 ••• FK PACKAGE
Q)
(TOPVIEWI
The devices allow data transmission from the A
bus to the B bus or from the B bus to the A bus
depending upon the logic level at the direction
control (DIRI input. The enable input (Gl can be
used to disable the device so that the buses are
effectively isolated.
C
en
o
3
2
18
The SN54HC245 is characterized for operation
over the full military temperature range of
-55 D C to 125 D C. The SN74HC245 is
characterized for operation from - 40 DC to
A6
A7
~
1 2019
5
17
6
16
7
15
8
14
CJ
:J:
B1
B2
B3
B4
B5
9 1011 1213
coo co ..... co
85 D C.
«zalalal
CI
NC-No internal connection
FUNCTION TABLE
CONTROL
INPUTS
CI
DATA dac._ coltai. ialDrmeti••
.uPRODUCTION
..."1 II of p""lelliDR
dati. "DII_ conIorm 10
IpICilicotionl .... Iho _
of T.uI 101118....11
=~l;"i:,~ ~=:':: ~!:':t.~~ not
TEXAS
OPERATION
OIR
L
L
L
H
B data to A bus
A data to B bus
H
X
Isolation
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright @ 1989, Texas Instruments Incorporated
2-335
SN54HC245, SN74HC245
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
logic symbol t
logic diagram (positive logic)
'--_-::1-1-<
A2---+--l
I-~
__ Bl
>+-r.--.....,
'--_-::1-1-< 1--";';';'';'" B2
'----.1--1-< 1--"':';";;"- B3
:x:
A4----+--l
(')
3:
oen
C
;>+-~--~
L..._-::I~-<
tThis symbol is in accordance with ANSI/lEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for OW, J, and N packages.
A6---+--l
CD
"",-"':';'=.0 B4
>+-",=::",.........,
L..._-:l~-< "",_"";"'';'';'''B6
<
n'
CD
A7---+--l
>+-r.--.....,
'-----1-1-< 1--";';";;;:'" B7
(11
A S - -......-I..;>--t=-...,
Pin numbers are for OW, J, and N packages.
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee ................................................. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) .................................. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) .............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vce) ................................. ± 35 mA
Continuous current through Vee or GND pins ................................... ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ................ 300 De
Lead temperature 1,6 mm (1/16 in) from case for 105: DW or N package ............... 260 DC
Storage temperature range .......................................... - 65 De to 150 De
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute~maximum-rated conditions for extended periods may affect device reliability.
2-336
TEXAS •
INSTRUMENTS
,... POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54HC245, SN74HC245
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
recommended operating conditions
SN54HC245
NOM
MAX
2
5
6
Vee Supply voltage
Vee - 2 V
VIH High-level input voltage
Vee
= 4.5
V
Vee = 6 V
Vee - 2 V
SN74HC245
MIN
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
UNIT
V
V
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
0
fI
0
Vee
1000
V
0
Vee
1000
tt
Input transition (rise and fall) times
0
500
0
500
ns
(,)
0
-55
400
0
-40
400
VIL Low-level input voltage
Vee
Vee
Vee
Vee
Vee
TA
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Operating free-air temperature
125
85
V
en
CD
">CD
°e
Q
electrical characteristics over recommended operating free-air temperature range (unless otherwise
PARAMETER
TEST CONDITIONS
VI
= VIH or VIL.
10H
=
VCC
-20
~A
VOH
VI - VIH or VIL.
VI
VI
=
=
VIH or VIL.
VIH or VIL.
10H 10H
10L
=
=
-6 rnA
-7.8 rnA
20 ~A
VOL
VI
II
I
10Z
I A or 8
lee
ei
I
DIRor~
DIR or G
en
0
oo~
= VIH or VIL.
10L
=
6 rnA
= VIH or VIL. 10L = 7.8
= Vee or 0
Vo = Vee or 0
VI = Vee or O. 10 = 0
VI
VI
rnA
TA = 25°C
MIN .. TVP MAX
SN54HC245
MIN
MAX
SN74HC245
MIN
2V
1.9 1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
4.5 V
3.98
4.30
3.7
3.84
6V
5.48
5.80
MAX
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
6V
0.15
±0.1
0.26
±100
0.4
0.33
±1000
6V
±0.01
±0.5
±10
±1000
±5
8
160
80
10
10
10
TEXAS
3
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
J:
5.34
5.2
0.002
2 to 6 V
:E
(J
V
2V
6V
UNIT
V
nA
~
/LA
pF
2-337
SN54HC245, SN74HC245
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
I
I
I
I
,0
FROM
TA ~ 25°C
SN54HC245
SN74HC245
,
PARAMETER
(INPUT)
A or B
tpd
-G
ten
-G
tdis
::t
(OUTPUT)
B or A
A or B
A or B
("')
3l:
A or B
tt
oen
c
c:r
CD
en
MIN
TYP
MAX
40
15
105
21
160
32
12
125
27
340
4.5 V
6V
2V
23
20
74
18
230
46
26
22
290
ns
6V
2V
68
58
300
58
ns
49
250
4.5 V
6V
2V
4.5 V
6V
25
21
20
8
6
MIN
39
200
40
MIN
10
MAX
130
60
51
90
18
15
34
60
12
No load, TA
MAX
UNIT
2V
4.5 V
Power dissipation capacitance per transceiver
CD
<
~
Vcc
50
ns
43
75
15
ns
13
= 25°C
40 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL
150 pF (see Note 1)
=
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
ten
-G
A or B
PARAMETER
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
tt
A or B
4.5 V
6V
TA = 25°C
TYP MAX
MIN
54
135
18
27
15
23
270
150
31
54
25
45
17
13
46
210
42
36
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
2-338
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC245
MIN MAX
200
40
34
SN74HC245
405
81
335
67
69
315
56
265
63
53
53
45
MIN
MAX
170
34
29
UNIT
ns
ns
ns
SN54HCT245, SN74HCT245
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
02804, MARCH 1984- REVISED JUNE 1989
•
Inputs are TTL-Voltage Compatible
•
High-Current 3-State Outputs Drive Bus
Lines Directly or Up to 15 LSTTL Loads
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
SN54HCT245 , , . J PACKAGE
SN74HCT245 ... OW OR N PACKAGE
(TOP VIEW)
G
A1
Dependable Texas Instruments Quality and
Reliability
description
These octal bus transceivers
asynchronous two-way
between data buses, The
implementation minimizes
requirements.
vee
DIR
are designed for
communication
control function
external timing
A2
61
A3
62
A4
63
A5
64
A6
A7
65
A8
67
GND
68
II
66
SN54HCT245 ... FK PACKAGE
(TOP VIEW)
N~g;
The devices allow data transmission from the A
bus to the B bus or from the B bus to the A bus
depending upon the logic level at the direction
control (DIR) input. The enable input (<3) can be
used to disable the device so that the buses are
effectively isolated.
tl
««O>ICl
3 2 1 2019
The SN54HCT245 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCT245 is
characterized for operation from - 40°C to
85°C.
4
18
61
5
17
62
6
16
63
7
15
14
64
8
65
9 10111213
CXlOCXl .... CO
«ZaJaJaJ
Cl
logic symbol t
FUNCTION TABLE
CONTROL
INPUTS
OPERATION
G
OIR
L
L
H
L
B data to A bus
H
A data to B bus
X
Isolation
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
PRODUCTION DATA documents .o.toin inlo,motio.
currant .s of publicatian date. Products conform ta
spacifications par lb. tarms Df rexi. Instrumants
:'~~~:~i~.i:I~1i ~=::i:; :.~O::~:::::~~~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright @ 1989. Texas Instruments Incorporated
2-339
SN54HCT245, SN74HCT245
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
logic diagram (positive logic)
Al
(18)
A2
IJ
(17)
B2
A3
(16)
83
A4
(15)
::c
0
B4
A5
s::
0
(14)
B5
A6
(13)
(I)
B6
A7
C
(12)
CD
<
5"
CD
en
81
B7
A8
(11)
B8
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee ................................................. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . .. . .................... ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) .............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) ................................. ± 35 mA
Continuous current through Vee or GNO pins ..................... , ............. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ................ 300 De
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package ............... 260 De
Storage temperature range .......................................... - 65 DC to 150 DC
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute~maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
VCC
VIH
VIL
VI
Vo
tt
TA
2-340
SN54HCT245
MIN NOM MAX
4.5
5
5.5
Supply voltage
High.level input voltage
Low-level input voltage
Input voltaga
I VCC
I
= 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2
0
0
0
0
-55
Output voltage
Input transition (rise and fall) times
Operating free-air temperature
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
0.8
VCC
VCC
500
125
SN74HCT245
MIN NOM MAX
4.5
5
5.5
2
0
0
0.8
0
0
VCC
VCC
500
-40
85
UNIT
V
V
V
V
V
ns
·C
SN54HCT245, SN74HCT245
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
TEST CONDITIONS
PARAMETER
=
-20 p.A
4.5 V
VI - VIH or Vil. 10H -
-6 rnA
4.5 V
VI
VOH
=
VCC
VIH or Vil. 10l
VI - VIH or Vil. 10l - 20 p.A
VI = VIH or Vil. 10l = 6 rnA
Val
=
TA - 25 G C
MIN
TYP MAX
4.4
3.7
3.84
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
5.5 V
±0.1 ±100
Va ~ VCC orO
5.5 V
±O.OI
VI - VCC or O. 10 - 0
5.5 V
Ci DIR or
5.5 V
v
± 1000
±1000
±0.5
±10
±5
nA
p.A
8
160
80
p.A
1.4
2.4
3
2.9
mA
3
10
10
10
pF
•
en
Q)
(,)
4.5 to
Gi
UNIT
V
0.001
VI
Other inputs at 0 V or VCC
MAX
4.5 V
A or B
.1ICC t
MIN
4.4
DIR orCl"
One input at 0.5 V or 2.4 V
MAX
4.30
II
ICC
MIN
4.4 4.499
3.98
10Z
Vec orO
SN54HCT245 SN74HCT245
5.5 V
'S
Q)
tThis is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or
f.This parameter Cj does not apply to transceiver 110 ports.
c
Vee.
CI)
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
tpd
A or 8
B or A
ten
G
A or 8
tdis
G
A or B
A or 8
tt
SN54HCT245 SN74HCT245
VCC
TA - 25 C
MIN TYP MAX
4.5 V
16
22
33
5.5 V
14
20
30
25
4.5 V
25
22
69
62
58
5.5 V
46
41
4.5 V
26
40
60
50
5.5 V
23
36
54
45
4.5 V
9
12
18
15
5.5 V
8
11
16
14
G
Power dissipation capacitance per transceiver
MIN
MAX
MIN
MAX
:!
(,)
::I:
UNIT
28
o
ns
ns
52
n.
n.
40 pF typ
No load. TA = 25 G C
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 11
PARAMETER
FROM (INPUT)
TO (OUTPUT)
tpd
A or 8
8 or A
ten
tt
G
A or 8
A or B
SN54HCT245 SN74HCT245
VCC
TA - 25 GC
MIN TYP MAX
4.5 V
20
30
45
5.5 V
18
27
41
34
4.5 V
36
59
89
74
5.5 V
53
80
67
4.5 V
30
17
42
63
53
5.5 V
14
38
57
48
MIN
MAX
MIN
MAX
38
UNIT
n.
ns
n.
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-341
J:
(")
:s:
orJ)
c
CD
<
'C:;'
CD
en
2-342
SN54HC251, SN74HC251
DATA SELECTORS/MULTIPLEXERS WITH 3·STATE OUTPUTS
02684. OECEM8ER 1982-REVISED SEPTEM8ER 1987
SN54HC251 ... J PACKAGE
SN74HC251 ... 0 OR N PACKAGE
•
3·State Version of 'HC151
•
High-Current 3-State Outputs Interface
Directly with System Bus or Can Drive Up
to 15 LSTTL Loads
•
Performs Parallel-to-Serial Conversion
•
Complementary Outputs Provide True and
Inverted Data
•
•
ITOPVIEW)
Vee
03
02
01
00
04
05
06
07
y
W
A
B
G
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
e
GNO
U)
SN54HC251 ... FK PACKAGE
Dependable Texas Instruments Quality and
Reliability
Q)
(,)
ITOP VIEW)
'S
U
U o
'" <'l U
description
3
These data selectors/multiplexers contain full
binary decoding to select one-of-eight data
sources and feature strobe-controlled
complementary three-state outputs.
The three-state outputs can interface with and
drive data lines of bus-organized systems. With
all but one of the common outputs disabled (at
a high-impedance state). the low-impedance of
the single enabled output will drive the bus line
to a high or low logic level. Both outputs are
controlled by the strobe (<3). The outputs are
disabled when G is high.
y
B
A
G
X
X
X
H
Z
Z
L
L
L
L
00
00
L
L
H
L
01
lIT
L
H
L
L
02
02
L
H
H
L
03
53
L
L
L
04
04
H
L
H
L
05
05
H
H
L
L
06
06
H
H
H
L
07
07
~
6
16
B
14
U)
o
:E
(.)
J:
U
zz
U!Xl
NC - No internal connection
logic symbol t
G
A
B
C
DO
01
'V
02
'V
(51
(61
V
W
03
04
05
06
H
00.01 ... 07
17
t:)
W
C
18
5
It:) 0
OUTPUTS
STROBE
4
9 1011 1213
FUNCTION TABLE
INPUTS
Q)
C
1 20 19
15
The SN54HC251 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC251 is
characterized for operation from - 40°C to
85°C.
SELECT
2
07
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617·12.
Pin numbers shown are for 0, J, and N packages.
the level of the respective
o input.
PRODUCTION DATA do.umants ,ontain information
current 81 of publication date. Products conform to
specifications par the terms of Texas Instruments
::~=~~i~.[nr;I~1i ~!::i:~i:; :1~o::~::::9t:~~s not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright @ 1982, Texas Instruments Incorporated
2-343
SN54HC251, SN74HC251
DATA SELECTORS/MULTIPLEXERS WITH 3·STATE OUTPUTS
,
logic diagram (positive logic)
G
(7)
A
B
c
IJ
::x:
o
s:
ofA
00
C
":"';';"---1 )>----H
CD
01
CD
02 -"-'----I
<
(;'
(I)
~>----------H
y
03
~---1
~>--------------H
04 ~~--1 ~-----------------~H
w
05~---1 ~------------------------H
06 "':":":::~--1 ~>-----------------------H
07 - - ; ~>---------------------------+-I
Pin numbers shown are for D, J, and N packages.
2·344
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54HC251, SN74HC251
DATA SELECTORS/MULTIPLEXERS WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 rnA
Output clamp current, 10K (Va < 0 or Va > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 rnA
eontinuous output current, 10 (Va = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±35 rnA
eontinuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 rnA
Lead temperature 1.6 mm (1/16 inl from case for 60 s: FK or J package. . . . . . . . . . . . . .. 300 0 e
Lead temperature 1,6 mm (1/16 in) from case for 105: 0 or N package ............... 260 0 e
Storage temperature range ......................................... - 65 °e to 150 0 e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only I and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
fI
recommended operating conditions
SN54HC251
NOM MAX
2
5
6
1.5
3.15
4.2
0
0.3
0
0.9
0
1.2
0
Vee
0
Vee
0
1000
0
500
0
400
-55
125
MIN
Vee
VIH
VIL
Supply voltage
High-level input voltage
Low·level input voltage
Vee
vee - 2 V
Vee = 4.5 V
Vee
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
Vee
Vee
Vee
TA
=2 V
= 4.5 V
=6V
Vee
Vee
Operating free-air temperature
=6V
=2V
= 4.5 V
=6 V
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
SN74HC261
NOM MAX
2
5
6
1.5
3.15
4.2
0
0.3
0.9
0
1.2
0
0
Vee
0
Vee
0
1000
500
0
0
400
-40
85
MIN
UNIT
V
v
V
V
v
ns
°e
2-345
SN54HC251, SN74HC251
DATA SELECTORS/MULTIPLEXERS WITH 3·STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
Vee
TEST CONOITIONS
2V
IOH=-20~
4.5 V
1.9 1.998
4.4 4.499
VI - VIH or VIL,
10H -
6V
4.5 V
5.9 5.999
3.98
4.30
VI = VIH or VIL,
10H = -7.8 rnA
VI = VIH or VIL,
VOH
VI = VIH or VIL,
::t
oen
c
CD
-6 rnA
10L = 20 ~A
VOL
VI = VIH or VIL,
o
s:
TA - 25!:JC
TYP MAX
MIN
VI - VIH or VIL,
II
VI = Vee or 0
10Z
Vo = Vee or 0,
lee
ej
VI = Vee or 0,
10L = 6 rnA
10L - 7.8 rnA
VI = VIH or VIL
10 = 0
6V
5.48
MIN
MAX
MIN
1.9
1.9
4.4
4.4
5.9
3.7
5.9
3.84
5.2
5.80
SN/4HC2bi
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
6V
0.17
0.15
0.26
0.4
0.33
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
6V
±0.01
±0.5
±10
±5
~A
8
160
80
~A
10
10
10
pF
6V
2 to 6 V
3
<
,r
CD
U)
2-346
Si~54HC25'i
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
V
SN54HC251, SN74HC251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
tpd
tpd
FROM
(INPUT)
A,
e,
or C
Any D
G
ten
TO
IOUTPUT)
Vcc
WarY
2V
4.5 V
WarY
6V
2V
4.5 V
WarY
6V
2V
4.5 V
TA - 25°C
TVP MAX
MIN
205
58
G
tdis
WarY
2V
256
51
44
n.
17
39
15
33
145
57
48
210
29
25
195
42
36
283
36
31
244
n.
39
33
75
57
48
110
49
41
n.
15
13
22
95
19
19
16
6
244
49
fI
n.
41
181
n.
70 pF typ
No load, TA = 25°C
Power dissipation capacitance
UNIT
60
51
283
20
8
4.5 V
6V
tt
300
41
35
195
9
25
15
14
4.5 V
6V
SN74HC251
MIN MAX
21
19
44
30
10
6V
2V
SN54HC251
MIN MAX
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 150 pF (see Note 1)
PARAMETER
tpd
FROM
(INPUT)
A,
e,
or C
TO
IOUTPUT)
WarY
tpd
Any D
WarY
ten
G
WarY
VCC
TA - 25°C
MIN
TYP MAX
2V
72
4.5 V
6V
25
2V
4.5 V
6V
2V
4.5 V
6V
2V
tt
4.5 V
6V
22
59
21
18
50
17
15
45
17
13
300
60
52
300
SN54HC251
MIN MAX
450
SN74HC251
MIN MAX
375
90
77
450
75
65
375
n.
90
77
ns
60
52
230
46
340
68
75
65
285
57
40
210
58
315
50
265
42
36
63
53
53
45
UNIT
ns
n.
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DAL,LAS, TEXAS 75265
2-347
E
:J:
o
s:
oen
c
CD
<
(i'
CD
(I)
2-348
SN54HC253, SN74HC253
DUAL 4-LlNE TO '-LiNE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
DECEMBER 1982 - REVISED JUNE 1989
•
3-State Versions of 'HC153
•
High-Current Inverting Outputs Drive Up to
15 LSTTL Loads
•
Permits Multiplexing from N Lines to 1 Line
•
Performs Parallel-to-Serial Conversion
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC253 ••• J PACKAGE
SN74HC253 ••. ot OR N PACKAGE
(TOPVIEWI
1G
VCC
2G
B
lC3
1C2
lCl
lCO
IV
GND
A
2C3
2C2
2Cl
2CO
2V
SN54HC253 ... FK PACKAGE
(TOP VIEW)
description
U
1Il1~ ~ ~I~
Each of these data selectors/multiplexers
contains inverters and drivers to supply full
binary decoding data selection to the AND-OR
gates. Separate output control inputs are
provided for each of the two four-line sections.
The three-state outputs can interface with and
drive data lines of bus-organized systems. With
all but one of the common outputs disabled (at
a high-impedance state) the low-impedance of
the single enabled output will drive the bus line
to a high or low logic level. Each output has its
own strobe (G). The output is disabled when its
strobe is high.
The SN54HC253 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC253 is
characterized for operation from - 40°C to
85°C.
3
2
1 2019
18
A
5
17
6
16
7
15
2C3
NC
2C2
2Cl
14
8
9 1011 1213
>-OU>-O
~ZZC'\lU
(!)
N
NC-No internal connection
t Contact the factory for 0 availability.
logic symbol:!:
B
FUNCTION TABLE
SELECT
OUTPUT
OATAINPUTS
INPUTS
lCl
L
L
lC3
L
H
L
L
L
H
L
L
L
H
A
CO
Cl
C2
C3
G
X
X
L
L
L
L
H
L
H
L
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
L
L
L
H
L
H
H
L
H
H
H
H
H
X
X
X
X
L
H
X
X
Address inputs A and B are common to both sections.
PRODUCTION DATA do.um.nls contain inlormllion
cu".nt as 01 publicllion dot•. Products .onlor.. to
sp.clli..tio.. p.r tho tar... of T.... I••trum.nls
~':::'rI;.i~I':.'le ':!:t1:~i:; :.\"=::~~~~ not
lCO
V
Z
B
X
L
lG
OUTPUT
CONTROL
IV
lC2
2G (151
2CO (101
2Cl (III
(121
2C2
2C3 (131
(9)
2V
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
IEC Publication 617·12.
Pin numbers shown are for D, J, and N packages.
Copyright @ 1989, Texas Instruments Incorporated
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-349
SN54HC253, SN74HC253
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
logic diagram (positive logic)
A
B~------~r-----~r----i
:J:
(")
s:
oo
c
CD
<
C)'
CD
(I)
Pin numbers shown are for D, J, and N packages.
2-350
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
SN54HC253. SN74HC253
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
lI
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
II
recommended operating conditions
SN54HC253
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0
0.9
0
1.2
0
0
Vee
0
Vee
1000
0
500
0
400
0
-55
125
Vee Supply voltage
VIH
High·level input voltage
VIL
Low-level input voltage
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
Vee
Vee
Vee
Vee
Vee
Vee
Vee - 2 V
Vee = 4.5 V
Vee
TA
=2V
= 4.5 V
=6 V
=2 V
= 4.5 V
=6 V
=6 V
Operating free-air temperature
TEXAS
.Jf
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74HC253
MIN NOM MAX
2
6
5
1.5
3.15
4.2
0
0.3
0.9
0
0
1.2
0
Vee
0
Vee
1000
0
0
500
0
400
-40
85
UNIT
V
V
V
V
V
no
·C
2-351
SN54HC253, SN74HC253
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
= VIH
or VIL, 10H
= VIH
VI = VIH
or VIL, 10H
= VIH
or VIL, 10L
= VIH
VI = VIH
or VIL, 10L
VI
= - 20 p.A
VI
VI
= 20
~A
VOL
VI
n
s:
or
= -6 rnA
VIL, 10H = -7.8 rnA
or
= 6 mA
VIL, IOL = 7.8 mA
I .;lI1
~"""'!:"'I.I"''''r'''''
I
.. ..,....n""' ...
"A - ,.., ""
MIN
TYP
~
MAX
MIN
MAX
roo ..........................
~
.... / .... n"'''i,J.;)
MIN
2V
1.9 1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
VOH
:t
vcc
5.9
5.9
4.5 V
3.98
5.9 5.999
4.30
3.7
3.84
6V
5.48
5.80
5.2
5.34
MAX
I
UNIT
V
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
6V
0.15
0.26
0.4
0.4
0.33
0.33
V
oen
II
VI - Vee or 0
6V
±0.1 ±100
±1000
±1000
nA
10Z
Vo
= Vee
6V
±0.01
±0.5
±10
±5
~A
lee
VI - Vee or 0, 10
8
160
80
~A
c
CD
ej
3
10
10
10
pF
or 0
=0
6V
2 to 6 V
<
c;'
CD
en
2-352
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC253. SN74HC253
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
FROM liN PUT)
TO (OUTPUT)
tpd
A or B
Any Y
tpd
Data
(Any C)
Y
ten
G
Y
tdis
G
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Y
Y
tt
VCC
TA - 25°C
MIN TYP MAX
150
62
19
30
16
26
126
54
16
28
13
23
28
100
11
20
17
9
135
21
14
30
12
35
28
60
12
8
10
6
SN54HC253
MIN MAX
225
45
38
210
42
36
150
SN74HC253
MIN MAX
190
38
32
175
35
30
125
30
26
203
45
38
90
18
15
25
21
170
38
31
75
15
13
No load, TA
Power dissipation capacitance per multiplexer
~
25°C
UNIT
ns
•
ns
o
ns
CD
Co)
'S:
ns
CD
o
en
o
ns
~
45 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 150 pF (see Note 1)
PARAMETER
FROM IINPUT)
TO (OUTPUT)
tpd
A or B
Any Y
tpd
Data
(Any C)
Y
ten
G
Y
tt
Y
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN TYP MAX
76
235
23
47
41
20
68
220
44
20
38
17
44
185
16
37
14
32
45
210
17
42
13
36
SN54HC253
MIN MAX
355
71
60
335
67
57
280
56
48
315
63
53
SN74HC253
MIN MAX
295
59
51
275
55
51
230
46
40
265
53
45
":r::
UNIT
ns
ns
ns
ns
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
2-353
:c
o
s:
otn
C
CD
<
(:;'
CD
(I)
2-354
SN54HC257, SN54HC258, SN74HC257, SN74HC258
QUAD 2·UNE TO HINE DATA SELECTORSIMULTIPLEXERS
WITH 3·STATE OUTPUTS
02684, DECEMBER 1982-REVISED JUNE 1989
•
SN54HC257, SN54HC258 •.. J PACKAGE
SN74HC257, SN74HC258 , . , Dt OR N PACKAGE
High·Current 3-State Outputs Interface
Directly with System Bus or Can Drive Up
to 15 LSTTL Loads
•
Provides Bus Interface from Multiple
Sources in High Performance Systems
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
ITOPVIEWI
AlB
1A
1B
1Y
2A
2B
2Y
GND
4A
4B
4Y
3A
3B
3Y
FI
U)
Q)
(,)
SN54HC257, SN54HC258 ... FK PACKAGE
description
ITOPVIEWI
These devices are designed to multiplex signals
from four-bit data sources to four-output data
lines in bus-organized systems. The 3-state
outputs will not load the data lines when the
output control pin (G) is at a high-logic level.
3
The SN54HC257 and SN54HC258 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HC257 and SN74HC258 are characterized
for operation from - 40°C to 85 °C.
FUNCTION TABLE
OUTPUT
OUTPUT Y
'HC257
A
B
H
X
X
l
L
l
X
X
X
H
l
l
l
H
H
H
l
l
l
H
l
H
L
H
X
X
Z
Z
l
H
PRODUCTION DATA doc.men,. contein information
currant as af publication date. Products conform to
spacifications par the terms of Taxas Instruments
::~:~;8[nr:I~1~
17
6
16
7
15
18
14
:!
(.)
:c
3A
9 1011 1213
=::i:;:.r:::£::.s nat
factory for 0 availability
'HC25B
A/B
G
1 20 19
4
5
8
t Contact the
DATA
SELECT
2
Q)
c
en
o
NC-No internal connection
INPUTS
CONTROL
'S;
~ u tl
~I1<:1
Copyright © 1989, Texas Instruments Incorporated
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-355
SN54HC257, SN54HC258, SN74HC257, SN74HC258
QUAD 2·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
logic symbols t
'HC257
'HC258
Ali
AlB
1A
::E:
s:o
38
4A
C')
t/)
o
CD
<
n'
CD
1Y
18
2A
2Y
28
.3A
1A
1Y
18
2A
2Y
28
3A
3Y
4Y
48
3Y
3B
4A
4Y
48
tThese symbols are in accordance with ANSI/IEEE Std 91·1984 and lEe Publication 617·12.
logic diagrams (positive logic)
'HC258
'HC257
en
1A {21
1A .,::{2::..)- - - i - i H L ' )
(31
1B ...:;{3;;.;.)--HHHLJ
(5)
2A .;.;{5.. :;)- - H H H L . /
(S)
2B (S)
(11)
3A (11)
38 (10)
3B "0)
4A (141
4A (14)
(13)
48 (13)
18
2A
28
3A
48
Pin numbers shown are for D. J. and N packages.
2-356
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54HC257. SN54HC258. SN74HC257. SN74HC258
QUAD 2·UNE TO 1·UNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ±20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package. . . . . . . . . . . . . . .. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
fI
recommended operating conditions
SN54HC257
SN74HC257
SN54HC258
Vee Supply voltage
Vee
VIH
2 V
Vce ~ 4.5 V
High-level input voltage
Low-level input voltage
NOM
MAX
2
1.5
5
6
UNIT
MIN
NOM
MAX
2
5
6
3.15
3.15
4.2
4.2
Vce ~ 2 V
0
0.3
0
0.3
~
0
0.9
0
0.9
0
1.2
0
1.2
Vce
~
4.5 V
Vee ~ 6 V
V
VI
Input voltage
0
Vee
0
Vee
Vo
Output voltage
0
0
Vee
1000
tt
Input transition Irise and fall) times
Vee
~
2 V
0
Vee
1000
Vee
~
4.5 V
0
500
0
500
0
400
400
-55
125
0
-40
Vee ~ 6 V
Operating free-air temperature
TA
V
1.5
6 V
Vee
VIL
~
SN74HC258
MIN
0
85
V
V
V
n.
°e
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TA - 25°C
Vcc
MIN
~ -20~
VI ~ VIH or VIL,
10H
VI ~ VIH or VIL,
10H ~ -6 rnA
10H ~ -7.8 rnA
2V
4.5 V
6V
VOH
VI ~ VIH or VIL,
~
TYP
MAX
SN54HC257
SN74HC257
SN54HC258
SN74HC258
MIN
MAX
MIN
1.9 1.998
4.4 4.499
1.9
4.4
5.9 5.999
5.9
5.9
3.7
3.84
4.5 V
3.98
6V
5.48
4.30
1.9
4.4
5.2
5.80
V
5.34
2V
0.002
0.1
0.1
0.1
0.1
0.1
0.1
VI ~ VIH or VIL,
10L
20 p.A
4.5 V
0.001
6V
0.001
0.1
0.1
0.1
VI - VIH or VIL,
10L - 6 rnA
4.5 V
0.17
0.26
0.4
0.33
VI ~ VIH or VIL,
10L
VOL
II
VI = Vee or 0
10Z
Vo ~ Vee or 0,
Ice
ei
VI = Vee or 0,
~
7.8 rnA
VI ~ VIH or VIL
10 ~ 0
UNIT
MAX
V
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
6V
±0.01
±0.5
±10
±5
p.A
160
80
p.A
3
8
10
10
10
pF
6V
2 to 6 V
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·357
SN54HC257, SN74HC257
QUAD 2-LlNE TO '-LINE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
I
I
III
PARAMETER
FROM
(INPUT)
tpd
A or B
tpd
AlB
i
TO
(OUTPUT)
,
i
vcc
Any Y
2V
4.5 V
Any Y
6V
2V
4.5 V
6V
2 V.
ten
::I:
G
Any Y
(')
3!:
o
en
tdis
cCD
G
Any Y
Any
tt
9
75
17
150
4.5 V
6V
2V
4.5 V
6V
15
13
75
15
13
30
26
150
30
26
2V
4.5 V
28
60
12
10
6V
<
,;,
Power dissipation capacitance per multiplexer
CD
TA = 25°C
TYP MAX
MIN
50
100
10
20
17
9
50
100
20
10
8
6
No load, TA
=
SN54HC257
MIN MAX
SN74HC257
MIN MAX
150
30
125
25
21
125
25
150
30
25
225
45
38
225
45
38
90
18
15
UNIT
ns
25
21
190
ns
38
32
190
38
ns
ns
32
75
15
ns
13
40 pF typ
25°C
(I)
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Any Y
tpd
AlB
Any Y
ten
G
vCC
2V
tt
TA = 25°C
TYP MAX
MIN
75
150
SN74HC257
MIN MAX
190
38
32
190
ns
38
32
250
no
50
43
265
53
45
no
4.5 V
6V
2V
4.5 V
6V
15
13
75
15
13
30
26
150
30
26
45
38
245
45
38
Any Y
2V
4.5 V
6V
100
24
18
200
40
34
300
60
51
Any
2V
4.5 V
6V
45
17
13
210
42
36
315
63
53
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
2-358
SN54HC257
MIN MAX
245
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
no
SN54HC258, SN14HC258
QUAD 2·UNE TO 1·UNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(lNPUlI
TO
(OUTPUll
tpd
A or B
Any V
tpd
AlB
Any V
ten
G
Any V
tdis
G
Any V
Any
tt
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Power dissipation capacitance per multiplexer
TA = 25°C
MIN
TYP MAX
60
100
13
20
12
17
115
60
13
23
12
20
70
150
15
30
13
26
75
150
15
30
13
26
28
60
8
12
10
6
SN54HC258
MIN MAX
150
30
25
175
35
30
225
45
38
225
45
38
90
18
15
No load, TA = 25°C
SN74HC258
MIN MAX
125
25
21
145
29
25
190
38
32
190
38
32
75
15
13
UNIT
ns
II
ns
ns
en
Q)
U
'S;
ns
Q)
o
en
ns
o
:!
40 pF typ
(.)
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(IN PUll
TO
(OUTPUll
tpd
A or B
Any V
tpd
AlB
Any V
ten
G
Any V
tt
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
TYP MAX
150
95
23
30
21
26
165
95
23
33
21
28
100
200
24
40
18
34
45
210
17
42
13
36
SN54HC258
MIN MAX
245
45
38
240
48
41
300
60
51
315
63
53
SN74HC258
MIN MAX
190
38
32
210
42
36
250
50
43
265
53
45
:::r:::
UNIT
ns
ns
ns
ns
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·359
:::t
C')
3:
oC/)
c
<
n'
CD
CD
t/)
2-360
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
02684, OECEMBER 1982-REVISEO SEPTEMBER 1987
SN54HC259 ... J PACKAGE
SN74HC259 ... D OR N PACKAGE
•
a-Bit Parallel-Out Storage Register Performs
Serial-to-Parallel Conversion with Storage
•
Asynchronous Parallel Clear
so
•
Active-High Decoder
•
Enable Input Simplifies Expansion
•
Expandable for N-Bit Applications
•
Four Distinct Functional Modes
51
52
QO
Q1
Q2
Q3
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
(TOP VIEWI
•
en
Q)
CJ
"S;
..- 0 U Ula::
U...J
UlUlZ>U
3
Four distinct modes of operation are selectable
by controlling the clear (ClR) and enable (G)
inputs as enumerated in the function table. In the
addressable-latch mode, data at the data-in
terminal is written into the addressed latch. The
addressed latch will follow the data input with
all unaddressed latches remaining in their
previous states. In the memory mode, all latches
remain in their previous states and are
unaffected by the data or address inputs. To
eliminate the possibility of entering erroneous
data in the latches, enable G should be held high
(inactive) while the address lines are changing.
In the 1-of-8 decoding or demultiplexing mode,
the addressed output will follow the level of the
D input with all other outputs low. In the clear
mode, all outputs are low and unaffected by the
address and data inputs.
Q)
c
en
1 20 19
2
o
4
18
G
5
17
D
6
16
NC
(J
7
15
Q7
8
14
06
J:
:!:
9 1011 1213
MOU"''''
OzzOO
l'J
NC-No internal connection
FUNCTION TABLE
INPUTS
Ci:R
G
OUTPUT OF
EACH
ADDRESSED
OTHER
LATCH
OUTPUT
FUNCTION
H
L
D
aiO
Addressable Latch
H
H
aiO
L
Memory
L
L
L
aiO
D
L
H
L
The SN54HC259 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC259 is
characterized for operation from - 40°C to
85°C,
:'::!:~~i;at::I~'1i ~!::i~~ti:; :,~O:::::::':is~S not
II
04
(TOPVIEWI
These 8-bit addressable latches are designed for
general purpose storage applications in digital
systems. Specific uses include working
registers; serial-holding registers, and active-high
decoders or demultiplexers. They are
multifunctional devices capable of storing singleline data in eight addressable latches, and being
a 1-of-8 decoder or demultiplexer with activehigh outputs.
specifications per the terms of Taxas Instrumants
D
Q7
Q6
Q5
SN54HC259 ... FK PACKAGE
description
currant as of publication date. Products conform to
G
GND
Dependable Texas Instruments Quality and
Reliability
PRODUCTION DATA documents contain information
VCC
CLR
8-Line Demultiplexer
Clear
LATCH SELECTION TABLE
SELECT INPUTS
ADDRESSED
L
L
0
L
H
H
L
H
1
2
3
4
5
6
7
51
L
L
L
L
H
H
L
L
H
L
H
H
H
L
H
H
H
"!1
INSTRUMENlS
TEXAS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
LATCH
SO
52
Copyright © 1982, Texas Instruments Incorporated
2-361
SN54HC259, SN74HC259
8·BIT ADDRESSABLE LATCHES
logic symbol t
:::E:
()
s:0
9,00
10,OR
14)
9,10
10,lR
15)
9,20
10:2R
9,30
10;JR
6)
9,40
t/)
17)
19)
10,4R
C
9,50
aI
00
Q1
02
03
04
110) 05
10,5R
<
,;,
aI
(I)
9,60
10,6R
Ill) 06
9,70
10,7R
112)
Q7
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
logic diagrams (positive logic)
Pin numbers shown are for 0, J, and N packages.
2-3£2
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
logic symbol and logic diagram, each internal latch (positive logic)
c
0
"=!}<:
C1
R
1R
Q
c
c
C
Q
R
C
absolute maximum ratings over operating free-air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 rnA
Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ............... 260°C
Storage temperature range ......................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC259
MIN NOM MAX
Vee Supply voltage
Vee - 2 V
VIH
High-level input voltage
Vee = 4.5 V
Vee = 6 V
vee = 2 V
Vil
Low-level input voltage
Vee = 4.5 V
Vee = 6 V
V,
Input voltage
Vo
Output voltage
tt
Input transition (rise and fall) times
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
TA
Operating free-air temperature
TEXAS
2
1.5
3.15
4.2
0
0
0
5
6
0.3
0.9
1.2
0
Vee
0
0
0
0
-55
Vee
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1000
500
400
125
SN74HC259
MIN NOM MAX
2
1.5
3.15
4.2
0
0
0
0
0
~
0
0
-40
5
6
UNIT
V
V
0.3
0.9
1.2
V
Vec
v
Vee
V
1000
500
400
85
ns
°e
2-363
SN54HC259, SN14HC259
8·BIT ADDRESSABLE LATCHES
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
i
I
PARAMETER
TEST CONDITIONS
VI
VI - VIH or VIL.
VI
VI
10H
=
-20 p.A
=
=
VIH or VIL.
VIH or VIL.
-4 rnA
10H -
10H = -5.2 rnA
10L
=
20 p.A
VOL
%
o
VI
~
=
VIH or VIL.
VI - VIH or VIL.
o·
(I)
c
CD
<
VIH or VIL.
VOH
•
(;'
=
vCC
II
VI
ICC
Cj
VI
=
=
10L = 4 rnA
10L - 5.2 rnA
VCC or 0
VCC or O.
10
=0
TA - 25°C
MIN
TVP MAX
SN54HC259
MIN
MAX
SN74HC259
MIN
2V
1.9 1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
5.9 5.999
5.9
5.9
3.84
4.5V
3.98
6V
5.48
4.30
3.7
5.80
5.2
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5V
0.001
0.1
0.1
0.1
BV
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.33
V
6V
0.15
0.26
0.4
0.4
6V
±0.1
±100
±1000
±1000
nA
8
160
80
~A
10
10
10
pF
6V
2 to 6 V
3
0.33
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
CD
en
VCC
CLR low
tw
Glow
tsu
th
2-364
Setup time. data or address before Gt
Hold time. data or address after Gt
SN54HC259
MIN
MAX
SN74HC259
MIN
120
100
4.5 V
80
16
24
20
6V
14
20
17
2V
80
120
100
4.5 V
16
24
20
2V
Pulse duration
TA = 25°C
MIN
MAX
6V
14
20
17
2V
75
115
95
4.5 V
15
23
19
BV
13
20
16
2V
5
5
5
4.5 V
5
5
5
6V
5
5
5
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MAX
UNIT
ns
ns
ns
SN54HC259. SN74HC259
8·BIT ADDRESSABLE LATCHES
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT!
tPHL
ern
Any
Q
tpd
Data
Any
Q
tpd
Address
Any
Q
tpd
tt
G
TO
(OUTPUT!
Any
Q
Any
VCC
2V
4.5 V
6V
2V
4.5 V
BV
2V
4.5V
6V
2V
4.5 V
BV
2V
4.5 V
BV
TA = 2SoC
MIN
TVP MAX
60
150
18
30
14
26
56
130
17
26
13
22
74
200
40
21
17
34
66
170
20
34
16
29
28
75
15
8
13
6
Power dissipation capacitance per latch
SNS4HC2S9
MIN MAX
225
45
38
195
39
33
300
60
51
255
51
43
110
No load, TA - 25°C
Note 1: Load circuits and' voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75285
22
19
SN74HC2S9
MIN MAX
190
38
32
165
33
28
250
50
43
215
43
37
95
19
16
33 pF typ
UNIT
ns
ns
ns
fI)
CD
U
ns
'>CD
ns
(J)
C
o
~
o
:J:
2-365
IE
::::c
n
s:
oen
oCD
<
c:;'
CD
rn
2-366
SN54HC266, SN74HC266
QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES
WITH OPEN-DRAIN OUTPUTS
02684, DECEMBER 1982-REVISED SEPTEMBER 1987
SN54HC266 , , , J PACKAGE
SN74HC266 ... 0 DR N PACKAGE
ITOP VIEW)
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
1A
18
1Y
2Y
2A
28
description
lB
2A
2B
3A
38
4A
48
(2)
'S
Q)
Z>' VCc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
2
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
%
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
(')
s:o
recommended operating conditions
SN54HC266
NOM MAX
f/)
cCD
Vee Supply voltage
C;"
VIH
<
MIN
2
Vee
Vee
High-level input voltage
CD
Vee
Vee
Vee
Vee
(I)
Vil
Low-level input voltage
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
Vee
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=
6 V
=2V
= 4.5 V
=6V
Operating free-air temperature
TA
5
6
1.5
3.15
4.2
SN74HC266
MIN NOM MAX
2
1.5
3.15
4.2
0
0
0
0.3
0.9
0
0
1.2
0
0
0
Vee
Vec
1000
500
400
0
0
0
0
0
0
-40
0
0
-55
125
5
6
UNIT
V
V
0.3
0.9
1.2
V
Vee
Vee
1000
500
400
85
V
V
ns
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
10H
TEST CONDITIONS
Vce
VI - VIH or Vll,
Vo - Vee
VI = VIH or Vil.
10l = 20 pA
VOL
II
ICC
ej
2-368
VI = VIH or Vil. IOl = 4 mA
VI = VIH or Vll; IOl = 5.2 mA
VI - Vee or 0
VI = Vee or 0,
10 = 0
TA - 25°e
MIN
TYP MAX
SN64HC266
MIN MAX
SN74HC266
MIN MAX
UNIT
6V
2V
4.5 V
0.01
0.002
0.001
0.5
0.1
0.1
10
0.1
0.1
5
0.1
0.1
pA
6V
4.5 V
6V
0.001
0.17
0.15
0.1
0.26
0.26
0.1
0.4
0.4
0.1
0.33
0.33
V
6V
6V
2 to 6 V
±0.1
±100
2
10
±1000
40
10
±1000
20
10
3
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
nA
pA
pF
SN54HC266, SN74HC266
QUADRUPLE 2·INPUT EXCLUSIVE·NOR GATES
WITH OPEN·DRAIN OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(lNPUTI
TO
(OUTPUTI
tpLH
A or B
Y
tpHL
A or B
Y
tt
Y
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA ~ 25°C
MIN
TYP MAX
60
125
13
25
10
23
60
100
13
20
10
17
28
75
8
15
13
6
Power dissipation capacitance per gate
SN54HC266
MIN MAX
190
38
32
150
30
25
110
22
19
Nolo.d, TA = 25°C
SN74HC266
MIN MAX
155
31
26
125
25
21
95
19
16
UNIT
ns
ns
ns
35 pF typ
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-369
2-370
SN54HC273, SN74HC273
OCTAL O·TYPE FLlp·FLOPS WITH CLEAR
02684. DECEMBER 1982-REVISED JUNE 1989
•
Contains Eight Flip-Flops with Single-Rail
Outputs
•
Direct Clear Input
•
Individual Data Input to Each Flip-Flop
•
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
SN54HC273 ... J PACKAGE
SN74HC273 ... OW OR N PACKAGE
ITOP VIEWI
•
ClR
VCC
10
10
20
20
30
3D
40
40
GNO
80
80
70
70
60
60
50
50
II
en
Q)
ClK
u
oS;
SN54HC273 ... FK PACKAGE
Dependable Texas Instruments Quality and
Reliability
Q)
ITOP VIEWI
o
CIl
o
:!:
o
15
o~~u>a:>
a
tl a
description
These circuits are positive-edge-triggered D-type
flip-flops with a direct clear input.
3
Information at the 0 inputs meeting the setup
time requirements is transferred to the Q outputs
on the positive-going edge of the clock pulse.
Clock triggering occurs at a particular voltage
level and is not directly related to the transition
time of the positive-going pulse. When the clock
input is at either the high or low level, the D input
signal has no effect at the output.
The SN54HC273 is characterized for operation
over the full military temperature range of
- 55 DC to 125 DC. The SN74HC273 is
characterized for operation from - 40 DC to
85 D C.
18
5
17
6
16
7
15
l:
14
9 1011 1213
logic symbol t
ClK
121
10
FUNCTION TABLE
30
lEACH FLiP-FLOPSI
4D
INPUTS
OUTPUT
50
CLEAR CLOCK 0
Q
60
L
X
X
L
70
H
H
H
80
H
r
r
L
L
H
L
X
00
:~~':!:~~i~8t::1~1i ~:~:~t~; :.~O::::::~:~~ not
1 20 19
4
8
20
PRODUCTION DATA dooumen,. con,ain information
current as of publication date. Products conform to
spacifications per the terms of Texas Instruments
2
141
151
171
161
10
20
1131
30
191 4Q
(121
1141
1151
1171
1161
1181
1191
181
so
6Q
70
80
tThis symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
Copyright © 1989, Texas Instruments Incorporated
2-371
SN54HC273, SN74HC273
OCTAL O·TYPE FLlp·FLOPS WITH CLEAR
logic diagram, total device (positive logic)
40
30
'i7j
•
"81
50
"131
80
(18)
::x::
(19)
80
(")
o3:
en
logic diagram each flip·flop (positive logic)
c
c
C
CD
<
O----f
o
n'
CD
(I)
CLK(I)~:
R---------~ ~----------~~--------~
2-372
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54HC273. SN74HC273
OCTAL O·TYPE FLlP·FLOPS WITH CLEAR
absolute maximum ratings over operating free·air temperature range t
Supply voltage, VCC ................................................. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > VCC) ............ , ..................... ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC) .............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) ................................. ± 25 mA
Continuous current through VCC or GNO pins ................................... ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ................ 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package ............... 260 0 C
Storage temperature range .......................................... - 65 DC to 150 DC
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Vee Supply voltage
VIH
High·level input voltage
VIL
Low-level input voltage
Vee - 2 V
Vee = 4.5 V
Vee = 6 V
Vee - 2 V
Vee = 4.5 V
Vee
=
6 V
Input transition (rise and fall) times
tt
Vee
=2V
= 4.5 V
=6V
2
1.5
3.15
4.2
5
6
5
6
">
Go)
V
V
0
0.3
0.9
1.2
0
0
0.9
1.2
V
Vee
0
0
0
Vee
V
Vee
1000
V
0
0
-40
500
400
85
ns
400
125
en
Go)
u
a
UNIT
0.3
Vee
1000
500
0
0
-55
Operating free-air temperature
TA
2
1.5
3.15
4.2
0
0
0
0
Output voltage
Vee
Vee
SN74HC273
MIN NOM MAX
0
0
Input voltage
VI
Vo
SN54HC273
MIN NOM MAX
2
°e
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
VCC
2V
4.5V
= VIH or VIL. 10H = - 20 ~A
VOH
VI - VIH orVIL,lOH - -4rnA
VI = VIH or VIL, 10H = - 5.2 rnA
VI
=
VIH or VIL. 10L
= 20 p.A
VOL
II
lee
ei
VI - VIH or VIL. 10L - 4 rnA
VI - VIH or VIL. 10L - 5.2 mil
VI = Vee or 0
VI - Vee or O. 10 - 0
6V
4.5V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 to 6 V
TA - 25°C
TYP MAX
MIN
1.9 1.998
4.44.499
5.9 5.999
3.98 4.30
5.48 5.80
0.002
0.001
SN54HC273
MIN
1.9
4.4
TYP
MAX
5.9
3.7
SN74HC273
MIN TYP MAX
1.9
4.4
5.9
3.84
5.2
V
5.34
0.1
0.1
0.1
0.1
0.1
0.1
0.001
0.1
0.17 0.26
0.15 0.26
±0.1 ±100
0.1
0.4
0.4
±1000
160
0.1
0.33
0.33
3
8
10
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
10
±1000
80
10
V
nA
p.A
pF
2-373
SN54HC273, SN74HC273
OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
timing requirements over recommended operilting free-air temperature range (unless otherwise noted)
Vcc
fclock
2V
4.5 V
6V
2V
4.5 V
Clock frequency
ClR low
II
tw
6V
2V
Pulse duration
ClK high or low
x
o
Data
3:
oen
tsu
Setup time before ClKi
ClR inactive
c(1)
<
(5"
th
Hold time, data after ClK!
en
I
iViAX
0
0
5
27
0
80
16
14
32
4.5 V
6V
80
16
14
2V
4.5 V
6V
100
20
17
2V
4.5 V
100
6V
2V
4.5 V
6V
(1)
iYF
fvtlt..
20
17
0
0
0
SN54HC273
MiN
0
0
0
120
24
20
120
24
20
150
30
25
150
30
25
0
0
0
MAX
4
18
21
I
SN74HC273
MiN MAX
0
0
4
21
0
100
20
25
I
UNIT
MHz
ns
17
100
20
17
ns
125
25
21
ns
125
25
21
0
ns
0
0
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
Vec
2V
4,5 V
f max
6V
tpHl
tpd
tt
ClR
ClK
Any
Any
Any
2V
4,5 V
TA - 25°C
MIN TVP MAX
II
5
27
50
32
60
160
55
6V
2V
4.5 V
6V
2V
4.5 V
6V
15
12
56
15
13
38
8
6
32
27
160
32
27
75
15
13
NOTE 1: load circuit and voltage waveforms are shown in Section 1.
TEXAS
18
~
INSTRUMENTS
POST OFFICE BOX 655012 • CALLAS, TEXAS 75285
SN74HC273
MIN MAX
4
21
UNIT
MHz
25
21
240
200
48
41
240
48
41
40
34
200
40
110
22
34
95
19
19
16
No load, TA = 25°C
Power dissipation capacitance per flip-flop
2-374
SN54HC273
MIN MAX
4
35 pF typ
ns
ns
ns
SN54HC280, SN74HC280
9-81T ODD/EVEN PARITY GENERATORS/CHECKERS
02684. OECEM8ER 1982-REVISEO JUNE 1989
SN54HC280 ... J PACKAGE
SN74HC280 ... D OR N PACKAGE
•
Generates Either Odd or Even Parity for
Nine Data Lines
•
Cascadable for n-Bits
•
Can Be Used to Upgrade Existing Systems
Using MSI Parity Circuits
G
H
NC
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
E EVEN
E ODD
GND
ITOP VIEW)
•
Dependable Texas Instruments Quality and
Reliability
en
CI)
u
NC
NC
NC
E EVEN
The SN54HC280 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC280 is
characterized for operation from - 40°C to
85°C.
NUMBER OF INPUTS A
':;
3
1 2019
o
2
4
18
5
17
6
16
8
14
CI)
o
:!
15
(.)
:t:
oou«tD
OZZ
OLL
CI)
These universal. monolithic. nine-bit parity
generators/checkers feature odd and even
outputs to facilitate operation of either odd Dr
even parity application. The word-length
capability is easily expanded by cascading.
1,3,5,7,9
fI
SN54HC280 ... FK PACKAGE
ITOP VIEW)
description
0,2,4.6,8
VCC
F
E
D
C
B
A
logic symbol t
J
l: ODD
I
L
H
A
B
c
D
E
F
G
H
2k
18)
19)
110)
111)
112)
113)
11)
15)
~
EVEN
~
ODD
12)
14)
tThis symbol is in accordance with ANSI/IEEE Std 91-1984
and lEe Publication 617-12.
Pin numbers shown are for D. J, and N packages.
PRODUCTION DATA documo.ts c••toin information
current II 01 publication doto. Products .onform to
spacifications per til. tarms of Taxas Instruments
::-::ri~8i:I':1~ =:~:r :.r::~:::~::.~s not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright @ 1989, Texas Instruments Incorporated
2-375
SN54HC280, SN74HC280
9-81T ODD/EVEN PARITY GENERATORS/CHECKERS
logic diagram (positive logic)
IJ
1:
EVEN
::J:
0
3:
0
(I)
C
CD
<
5"
CD
(I)
1:
ODD
Pin numbers shown are for 0, J, and N packages.
absolute maximum ratings over operating free-air temperature range t
Supply voltage, VCC ................................................. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) .................................. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) .............................. ±20 mA
Continuous output current, 10 (VO = 0 to Vce) : ........... : .................... ±25 mA
Continuous current through VCC or GND pins ................................... ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ................ 300 0 e
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ................. 260 o e
Storage temperature range .......................................... - 65 °e to 150 0 e
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating'
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2-376
TEXAS
,If
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS. TEXAS 75265
SN54HC280, SN74HC280
9·81T ODD/EVEN PARITY GENERATORS/CHECKERS
recommended operating conditions
SN54HC280
MIN
Supply voltage
Vee
2
Vee - 2 V
High-level input voltage
VIH
MAX
6
5
6
5
UNIT
V
3.15
3.15
4.2
4.2
Vee = 2 V
0
0.3
0
0.3
Vee = 4.5 V
0
0.9
0
0.9
Vee = 6 V
1.2
0
1.2
Vee
0
Vee
V
0
Vee
1000
V
500
ns
0
-40
Input voltage
Vo
Output voltage
0
Vee = 2 V
Vee = 4.5 V
0
0
Vee
1000
500
Vee = 6 V
0
400
-55
125
Operating free-air temperature
TA
NOM
2
1.5
VI
Input transition (rise and fall) times
MIN
1.5
0
0
tt
SN74HC280
MAX
Vee = 6 V
Vee = 4.5 V
Low-level input voltage
VIL
NOM
V
0
0
•
V
en
CD
U
'S;
400
CD
De
85
C
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
vCC
TA - 25 DC
MIN TYP MAX
SN54HC280
MIN
TYP
SN74HC280
MAX
MIN
2V
1.9 1.998
1.9
1.9
VI =VIHorVIL,IOH = -20~
4.5V
4.44.499
4.4
4.4
5.9 5.999
5.9
5.9
VI - VIH OrVIL,lOH - -4 mA
4.5V
3.7
5.2
3.84
6V
VOH
6V
VI = VIH or VIL, 10H = - 5.2 mA
VI = VIH or VIL, 10L = 20 p.A
VOL
VI - VIH or VIL, 10L - 4 mA
3.98
5.48
4.30
5.80
TYP
MAX
l:
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
V
VI - VIH or VIL, 10L - 5.2 m~
6V
VI = Vee or 0
6V
0.15 0.26
:to.l :tl00
0.4
:tl000
:tl000
nA
lee
VI - Vee or 0, 10 - 0
6V
8
160
80
10
10
10
p.A
pF
2 to 6 V
3
:!
(J
UNIT
II
ei
U)
o
0.33
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
tpd
FROM (INPUT)
A thru I
SN54HC280
SN74HC280
Vcc
J: Even
2V
4.5 V
103
205
305
21
41
61
52
6V
17
35
52
44
2V
4.5 V
38
8
75
110
95
15
22
19
6V
6
13
19
16
or
J: Odd
tt
TA - 25 DC
MIN TYP MAX
TO (OUTPUT)
Any
MIN
No load, TA = 25 De
Power dissipation capacitance
MAX
MIN
MAX
UNIT
260
ns
ns
60 pF typ
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-377
E
l:
(")
:s::
oen
c
CD
,r<
CD
en
2-378
SN54HC283. SN74HC283
4·BIT BINARY FULL ADDERS WITH FAST CARRY
02804, MARCH 1984-REVISED SEPTEMBER 1987
•
Full·Carry Look·Ahead Across the Four Bits
•
Systems Achieve Partial Look·Ahead
Performance with the Economy of Ripple
Carry
•
Supply Voltage and Ground on Comer Pins
to Simplify p·c Board Layout
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300·mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC283 ... J PACKAGE
SN74HC283 ... D OR N PACKAGE
(TOP VIEW)
1:2
B2
A2
1:1
A1
B1
eo
GND
Vee
B3
A3
1:3
A4
B4
1:4
e4
fI
SN54HC283 ... FK PACKAGE
(TOP VIEW)
U
N N U U""
tXlt.:lZ>tXl
description
These improved full adders perform the addition
of two 4-bit binary words. The sum (E) outputs
are provided for each bit, and the resultant carry
(C4) is obtained from the fourth bit.
These adders feature full internal look-ahead
across all four bits generating the carry term.
This capability provides the system designer
with partial look-ahead performance at the
economy and reduced package count of a ripplecarry implementation,
3
1:1
2
1 2019
4
18
5
17
6
16
8
14
15
9 1011 1213
OOuq-qUZzUt.:I
Cl
NC-No internal connection
The adder logic, including the carry, is
implemented in its true form. End around carry
can be accomplished without the need for logic
or level inversion.
The SN54HC283 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC283 is
characterized for operation from -40°C to
85°C.
PRODUCTION DATA documants contain information
current as of publication date. Products conform to
specifications par the tarms of Texas Instruments
=~i~8ir::I~'~ ~:~~~ti:; :.r:=:::~:~s
not
Copyright © 1984, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
2-379
SN54HC283, SN74HC283
4·81T BINARY FULL ADDERS WITH FAST CARRY
II
H
L
L
L
L
H
H
:l:
L
L
H
H
L
L
L
H
L
L
H
L
L
H
L
L
H
H
H
L
H
H
H
L
H
L
(')
L
L
H
L
L
H
H
L
L
H
H
H
L
L
L
H
L
H
H
L
H
L
H
H
L
L
L
H
H
L
H
L
H
H
L
L
0
tn
H
H
H
L
L
L
L
H
L
H
C
H
L
L
H
H
H
H
L
H
H
H
H
L
H
L
L
s:
CD
<
H
L
H
H
L
(I)
H
L
H
H
H
L
H
H
H
H
H
H
H
H
ri"
CD
L
L
L
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H = high level. L = low level
NOTE: Input conditions at A 1. B1. A2. B2. and CO are used to determine outputs
Eland E2 and the value of the internal carry C2. The values at C2. A3.
B3. A4. and B4 are then used to determine outputs E3. E4. and C4.
logic symbol t
(5)
A1
~
} {
(3)
A2
A3
A4
(14)
(12)
(6)
Bl
B2
B3
B4
CO
(2)
(15)
(11)
(7)
}
(4)
(1)
(13)
(10)
CO
(9)
~1
~2
~3
~4
C4
CI
• tThis symbol is in,accordance with ANSI/IEEE Std 91·1984 and
IEC Publication 617·12.
Pin numbers shown are for D~ J, and N packages.
2·380
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS. TEXAS 75265
SN54HC283. SN74HC283
4·BIT BINARY FULL ADDERS WITH FAST CARRY
logic diagram (positive logic)
•
U)
Q)
u
'S
Q)
c
CI)
o
:E
u
J:
Pin numbers shown are for 0, J, and N packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-381
SN54HC283, SN74HC2&3
4-BIT BINARY FULL ADDERS WITH FAST CARRY
absolute maximum ratings over operating free-air temperature range t
11
Supply voltage. Vee. . . . . . . . . . .
. ....................... -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > VCC) .................................. ±20 mA
Output clamp current, 10K (Va < 0 or Va > VCC) .............................. ± 20 mA
Continuous output current, 10 (Va = 0 to VCC) ................................. ±25 mA
Continuous current through VCC or GND pins ................................... ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ................ 300 DC
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ................. 260 DC
Storage temperature range .......................................... - 65 DC to 1 50 DC
::J:
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3:
recommended operating conditions
(")
otn
SN54HC283
MIN NOM MAX
oCD
Vee Supply voltage
(;'
VIH
<
High-level input voltage
Vee - 2 V
Vee = 4.5 V
Low-level input voltage
Vee = 6 V
Vee - 2 V
Vee = 4.5 V
CD
tI)
VIL
Vee
=
2
1.5
3.15
6 V
Output voltage
Input transition (rise and fall) times
tt
Vee
Vee
Vee
=2V
= 4.5 V
=6V
0
0
0
0.3
0
0
0
0
Vee
0
-55
Operating free-air temperature
TA
6
4.2
Input voltage
VI
Vo
5
0.9
1.2
Vee
1000
500
400
125
SN74HC283
MIN NOM MAX
2
1.5
3.15
4.2
5
6
UNIT
V
V
0
0
0
0.3
0.9
1.2
V
0
0
Vee
Vee
1000
V
500
400
n.
85
·e
0
0
0
-40
v
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
VI
= VIH or VIL. 10H = - 20 p.A
VI
VI
= VIH or VIL, 10H = -4 mA
= VIH or VIL. 10H = - 5.2 mA
VI
=
VIH or VIL. 10L
VI
VI
VI
=
=
=
VIH or VIL. 10L - 4 mA
VIH or VIL. 10L - 5.2 mil
Vee orO
VOH
= 20 ~A
4.5 V
6V
VOL
II
ICC
ei
2-382
VI - Vee or O. 10 - 0
4.5V
6V
4.5V
6V
2V
4.5 V
6V
6V
6V
2 to 6 V
TA - 25·C
MIN
TYP MAX
1.9 1.998
4.4 4.499
5.9 5.999
3.98
5.48
4.30
5.80
0.002
0.1
0.001
0.001
0.1
0.1
SN54HC283
MIN TYP MAX
1.9
4.4
5.9
3
4.4
5.9
3.7
5.2
0.17 0.26
0.15 0.26
±0.1 ±100
8
10
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74HC283
MIN TYP MAX
1.9
UNIT
V
3.84
5.34
0.1
0.1
0.1
0.4
0.4
±1000
160
10
0.1
0.1
0.1
V
0.33
0.33
±1000
80
10
nA
p.A
pF
SN54HC283, SN74HC283
4-BIT BINARY FULL ADDERS WITH FAST CARRY
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
tpd
CO
Any 1:
tpd
Ai or Bi
1:i
tpd
CO
C4
tpd
tt
Ai or Bi
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
C4
Any
TA - 25°C
MIN TYP MAX
60
150
20
30
16
26
80
175
25
35
20
30
70
175
25
35
20
30
90
175
26
35
21
30
75
28
8
15
13
6
Power dissipation capacitance
No load, TA
SN54HC283
MIN MAX
225
45
38
262
52
45
262
52
45
262
52
45
110
22
19
= 25°C
SN74HC283
MIN MAX
188
37
32
218
44
37
218
44
37
218
44
37
95
19
16
UNIT
ns
ns
ns
•
en
CD
ns
CJ
oS;
CD
Q
ns
en
o
~
(,)
90 pF typ
J:
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-383
:J:
o
3:
oen
c
CD
<
c:;'
CD
en
2-384
SN54HC298. SN74HC298
QUADRUPLE 2-INPUT MULTIPLEXER WITH STORAGE
02804. MARCH 1984-REVISEO JUNE 1989
•
•
Dual Source for Operands and Constants in
Arithmetic Processor; Can Release
Processor Register Files for Acquiring New
Data
•
Implements Separate Registers Capable of
.Parallel Exchange of Contents, yet Retains
External Load Capability
•
Has Universal·Type Register for
Implementing Various Shift Patterns
•
Has Compound Left-Right Capability
•
Package Options Include Ceramic Chip
Carriers and Standard Plastic and Ceramic
300-mil DIPs
•
SN54HC298 ... J PACKAGE
SN74HC298 .•• N PACKAGE
Selects One of Two 4-81t Data Sources and
Stores Data Synchronously with System
Clock
ITOPVIEWI
B2
A2
AI
Bl
C2
02
01
GND
VCC
AA
QB
Qc
QD
CLK
II
WS
Cl
SN54HC298 ... FK PACKAGE
(TOP VIEW)
U
'" '" U U ~
~"'z>O
3
AI
Bl
NC
C2
02
Dependable Texas Instruments Quality and
Reliability
description
This quadruple two-input multiplexer with
storage provides essentiallv the equivalent
functional capabilities of two separate MSI
functions ('HC157 and 'HC175) in a single
16-pin package.
2
1 2019
4
18
5
17
6
16
15
14
8
9 1011 1213
~OU~(/)
O(§ZU$
NC - No internal connection
When the Word-Select (WS) input is low, word
one (A 1, B1, C1, 01) is applied to the flip-flops.
A high Word-Select input causes word two
(A2. B2, C2, 02) to be selected. The selected
word is clocked to the output terminals on the
negative-going edge of the clock pulse.
logic symbol t
The SN54HC298 is characterized for operation
over the full military temperature range of
- 55 DC to 125 DC. The SN74HC298 is
characterized for operation from - 40 DC to
85 D C.
A2 121
Al 131
Bl 141
1151 0A
1.20
(141 0B
B2111
C1 191
C2 151
01 171
(13) Oc
(121 00
02 161
tThese symbols are in accordance with ANSIIIEEE Std 91-1984
and IEC Publication 61 7·12.
Pin numbers shown are for J and N packages.
PRODUCTION DATA documonts contain informition
corretlt II .f pllllli.lti•• dlta. Products conform to
spacificotioos par the tarmo of Te..s Instrumonts
:~:i~ai~:I~li :'1:~ti:; :.~-=:::£::s not
TEXAS ..,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright @ 1989, Texas Instruments Incorporated
2-385
SN54HC298, SN14HC298
QUADRUPLE 2·INPUT MULTIPLEXER WITH STORAGE
logic diagram (positive logic)
w,,~
-
V-
"'V'
•
:::z::
n
s:o
(I)
c
CD
<
t:i'
CD
o
Pin numbers shown are for J and N packages.
2-386
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC298. SN74HC298
QUADRUPLE 2-INPUT MULTIPLEXER WITH STORAGE
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: N package .. . . . . . . . . . . . . . . . .. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Vee Supply voltage
High-level input voltage
V,H
Vee
=2V
= 4.5 V
NOM
MAX
2
1.5
5
6
MIN
NOM
MAX
2
5
6
3.15
3.15
4.2
0
0.3
0
0.3
0
0.9
0
0.9
Low-level input voltage
0
1.2
0
1.2
V,
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
Vee
1000
0
vee
1000
V
0
500
0
500
ns
0
-55
400
0
-40
400
Input transition (rise and fall) times
tt
Vee
=
0
6 V
Operating free-air temperature
TA
o
125
:i!:
(.)
V,L
Vee = 2 V
Vee = 4.5 V
en
V
V
4.2
= 4.5 V
=6V
o
UNIT
1.5
Vee = 2 V
Vee
Q)
(.)
Q)
SN74HC298
MIN
Vee = 6 V
Vee
II)
oS
SN54HC298
Vee
•
0
85
:c
V
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONOITIONS
VCC
2V
V,
= V,H or V,L.
10H = -20pA
6V
VOH
V, - V,H or V,L. 10H - -4 rnA
V, - V,H or V,L. 10H - - 5.2 rnA
V, = V,H or V,L. 10L = 20 ~A
VOL
V,
=
V,H or V'L, 10L
=4
rnA
V, - V,H or V'L, 10L - 5.2 rnA
I,
lee
Cj
4.5V
V, - Vee or 0
V, = Vec or 0, 10 = 0
TA - 25°C
MIN
TYP MAX
1.9
SN54HC298
MIN
MAX
SN74HC298
MIN
1.998
1.9
1.9
4.4 4.499
4.4
4.4
5.9 5.999
4.5V
3.98
6V
5.48
4.30
5.80
5.9
5.9
3.7
3.84
5.2
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
6V
0.17
0.15
0.26
0.26
0.4
0.4
0.33
0.33
6V
±0.1
±100
±1000
±1000
nA
8
160
80
pA
10
10
10
pF
6V
2 to 6 V
3
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
0.1
V
2-387
SN54HC298, SN74HC298
QUADRUPLE 2-INPUT MULTIPLEXER WITH STORAGE
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
Vee
~
MIN
25°C
MAX
2V
fclock Clock frequency
E
Data before ClK!
tsu
WS before elK!
Data after elK!
Hold time
th
75
15
13
80
16
14
80
16
14
0
0
0
0
0
0
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Setup time
WS after elK!
MIN
6.5
33
38
4.5 V
6V
2V
4.5 V
Pulse duration, elK high or low
tw
I SN54HC298I
MAX
SN74HC298
MIN
4.3
22
25
115
23
20
125
25
21
125
25
21
0
0
0
0
0
0
MAX
5.5
27
31
I
UNiT
MHz
95
19
16
105
21
18
105
21
18
0
0
0
0
0
0
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL =0 50 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
vCC
2V
f max
4.5 V
Ipd
6V
2V
4.5 V
ClK
Any
TA - 25°C
MIN TYP MAX
Any
2V
4.5 V
6V
46
15
12
38
8
6
125
25
21
75
15
13
No load, TA
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
MAX
4.3
22
25
Power dissipation capacitance per multiplexer
2-388
MIN
6.5
33
38
BV
II
SN54HC298
.Jqr
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74HC298
MIN
MAX
5.5
27
31
190
38
32
110
22
19
= 25°C
UNIT
MHz
155
31
26
95
19
16
33 pF Iyp
ns
ns
SN54HC299, SN14HC299
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH DIRECT CLEAR AND 3·STATE OUTPUTS
02684, DECEMBER 1982-REVISEO SEPTEMBER 1987
•
Multiplexed 1/0 Ports Provide Improved Bit
Density
•
Four Modes of Operation: Hold /Store), Shift
Right, Shift Left, and Load Data
•
High Current 3·State Outputs Drive Bus
Lines Directly or Up to 15 LSTTL Loads
•
Can Be Cascaded for N·Bit Word Lengths
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300·mil
DIPs
•
SN54HC299 .•. J PACKAGE
SN74HC299 ... ow OR N PACKAGE
(TOP VIEW)
50
131
VCC
51
5L
132
Qw
H/QH
F/QF
O/Qo
B/QB
G/QG
E/QE
C/QC
A/QA
QA'
CLK
5R
CLR
GNO
U)
CD
(,)
Dependable Texas Instruments Quality and
Reliability
'S;
SN54HC299 ... FK PACKAGE
(TOP VIEW)
description
Nor- 0
1c.!11c.!1
These eight-bit universal registers feature
multiplexed 1/0 ports to achieve full eight-bit
handling in a single 20-pin package. 'HC299
applications are as stacked or push-down
registers, buffer storage, and accumulator
registers.
3
G/QG
E/QE
C/Qc
A/QA
QA'
Two function-select inputs and two output
control inputs can be used to choose the modes
of operation listed in the function table.
Synchronous parallel loading is accomplished by
taking both function-select lines, SO and 51,
high, This places the three-state outputs in a
high-impedance state, which permits data that
is applied on the 110 ports to be clocked into the
register. Reading out of this register can be
accomplished while the outputs are enabled in
any mode. A direct overriding input is provided
to clear the register whether the outputs are
enabled or off. Taking either of the output
controls, G1 or G2, high disables the outputs but
does not affect the shifting or storage of data.
CD
Q
U
U....-
en
en > en
o
2 1 20 19
4
18
5L
5
6
17
7
15
QH'
H/QH
F/QF
O/Qo
16
8
14
:E
(.)
x:
9 1011 1213
logic symbol t
The SN54HC299 is characterized for operation
over the full military temperature range of
- 55 DC to 125 DC. The SN74HC299 is
characterized for operation from - 40 DC to
85 D C.
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
PRODUCTION DATA documents contain information
current 8S of publicatioR date. Products conform to
spacifications per the terms of Texas Instruments
:.~:~:~~a[::1~1i ~=:~ti:f :I~':~::::':~
not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1982, Texas Instruments Incorporated
2-389
SN54HC299, SN74HC299
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH DIRECT CLEAR AND 3·STATE OUTPUTS
logic diagram (positive logic)
CLR
-<:t :;»_.......,
..l:!9:..:.1_ _ _ _ _ _ _ _ _ _ _ _
~(2~1_ _ _~~~------~
G2 ..::(3::!..1_--++++--1f-----------.,f----,
::J:
o
3:
SR
(111
ot/)
cCD
<
< 1--+-+++-I-1>-4------t-t---+-----'
1_ _
A/OA ..::(70.:..
(;'
CD
tn
C I--+-+++-H>-t------t-+---+-----'
BlOB .:.:(1.::.:31...........
C/O
---------,
r----
C
~I
D
~I
E/O E
~II
D/O
5 CHANNELS IDENTICAL
I
I
I
I
TO CHANNEL B ABOVE
I
I
I
F/OF~
I
I
I
G/OG~L ____
_
I
----------"
'----+-dR
-+______t - - - - - - - - - - '
H/OH .:.;(1.:;,61..........<.1-_ _ _ _ _
Sl (181
2·390
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • "DALLAS, TEXAS 75265
SN54HC299, SN74HC299
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH DIRECT CLEAR AND 3·STATE OUTPUTS
FUNCTION TABLE
INPUTS
FUNCTION
MOOE
Clear
Hold
Shift Right
Shift Left
Load
CLEAR
INPUTSIOUTPUTS
OUTPUT
SELECT
CONTROL
S1
G1 t
SO
CLOCK
L
H
H
X
X
H
L
L
L
L
X
X
X
X
H
X
X
L
L
L
H
L
H
L
L
H
H
L
L
H
L
H
L
L
L
H
H
L
L
L
H
H
H
X
X
t
t
t
t
t
X
L
L
L
L
L
X
L
L
A/QA B/QB C/QC O/Qo
E/QE
OUTPUTS
F/OF G/Oc; H/QH
QA'
QH'
SL:SR
G2 t
L
SERIAL
X
X
X
X
X
X
X
H
L
X
L
L
X
X
L
L
X
X
X
X OAO QBO
X OAO QBO
X
X
X
X
X
X
L
L
OCO
000
QFO
OGO
QAO
QHO
OCO
OFO
Oc;o
QAn
OBn
OEn
QFn
QGn
°AO
H
OHO
H
000
QCn
OHO
QHO
H
OEO
QEO
QOn
L
L
QAn
OEn
OFn
QCn
QCn
QOn
c
QEn
d
QGn
QGn
f
QHn
QHn
g
OGn
H
QBn
a
QFn
QFn
e
QGn
H
L
QBn
OCn
QEn
OOn
X
X
X
OBn
QOn
b
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
OBn
OGn
L
OBn
a
h
•
h
tWhen one or both output controls are high the eight input/output terminals are disabled to the high-impedance state; however, sequential
operation or clearing of the register is not affected.
a , .. h .= the level of the steady-state input at inputs through H, respectively. These data are loaded into the flip-flops while the flip-flop
outputs are isolated from the input/output terminals.
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee, , ............................................... -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) .................................. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) .............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) ................................. ±35 mA
Continuous current through Vee or GNO pins ................................... ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ................ 300°C
Lead temperature 1,6 mm (1/16 in) from case for 1Os: OW or N package ............... 260°C
Storage temperature range .......................................... - 65°C to 150°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied, Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC299
Vec Supply voltage
VCC - 2 V
VIH
High-level input voltage
Low-level input voltage
NOM
MAX
MIN
NOM
MAX
2
1.5
5
6
2
1.5
5
6
4.5 V
3.15
3.15
6V
VeC - 2 V
VCC = 4.5 V
VCC = 6 V
4.2
4.2
Vee
VCC
VIL
=
=
0.3
0
0.3
0
0.9
0
0.9
1.2
0
0
1.2
VI
Input voltage
Va
Output voltage
0
tt
Input transition (rise and fall) times
Vee
VCC
Vee
=2V
= 4.5 V
=6V
Operating free-air temperature
TEXAS
VCC
V
V
0
500
ns
0
400
-40
85
0
0
500
0
-55
400
125
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V
VCC
0
~
V
Vce
1000
0
Vce
1000
INSTRUMENTS
UNIT
V
0
0
0
TA
SN74HC299
MIN
°e
2-391
SN54HC299. SN74HC299
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH DIRECT CLEAR AND 3·STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
.
I
I
PARAMETER
TEST CONDITIONS
VI ; VIH o. Vll, 10H ;
VCC
2V
4.5 V
- 20 p.A
6V
•
VOH
VI - VIH OA' and OH' IOH A/On thru H/On IOH
or Vil
VI - VIH 0A' and OH' 10H A/On thru H/On IOH
or Vil
::E:
-4 mA
; - 6 mA
- 5.2 mA
- - 7.8 mA
VI ; VIH or Vll, 10l ; 20 p.A
(")
s:o
<
cr
CD
SN74HC299
MIN MAX
1.9
4.4
1.9
4.4
5.9
5.9
4.5 V
3.98
4.30
3.7
3.84
6V
5.48
5.80
5.2
5.34
UNIT
V
2V
4.5 V
6V
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
V
VI; VIH OA' and OH' 10l ; 4 mA
A/On thru H/On IOl - 6 mA
or Vil
VI; VIH OA' and OH IOl - 5.2 mA
A/On thru H/OH IOl ; 7.8 mA
or Vil
6V
0.15
0.26
0.4
0.33
II
VI; VCC or 0
6V
±0.1 ±100
±1000
±1000
nA
lozt
Vo - VCC or 0, VI ; VIH or Vil
VI - VCC Or 0, 10 - 0
6V
6V
±O.Ol
±0.5
8
±10
160
±5
80
p.A
p.A
3
10
10
10
pF
ICC
en
1.9 1.998
4.4 4.499
5.9 5~999
SN54HC299
MIN MAX
VOL
en
o
CD
TA - 25°C
MIN
TYP MAX
2 to 6 V
Ci*
tFor I/O ports (OA through OHI, the parameter II is included in the off-state output current.
*This parameter, CI, does not apply to transceiver I/O ports.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
tw
Clock frequency
Pulse duration
ClK high, ClK low,
or CUi low
SO orS1
Setup time
tsu
before ClK!
Sl or SR
Data or
CUi inactive
th
2-392
Hold time
after ClK!
Select or
data
2V
4.5 V
6V
2V
TA - 25°C
MIN
MAX
0
0
6
31
36
6V
2V
0
80
16
14
175
4.5 V
35
6V
2V
30
100
20
17
4.5 V
4.5 V
6V
2V
4.5V
6V
2V
4.5 V
6V
65
13
11
0
0
0
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC299
MIN MAX
4.2
0
0
0
120
24
20
263
21
25
SN74HC299
MIN MAX
0
0
0
100
20
17
219
44
5
25
29
UNIT
MHz
ns
53
45
150
37
125
ns
30
26
98
25
21
81
ns
20
17
0
16
14
0
ns
0
0
0
0
ns
SN54HC299. SN74HC299
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH DIRECT CLEAR AND 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
f max
QA' or QH'
tpd
ClK
QA thru QH
GlorG2
QA thru QH
ten
50 or 51
Gl,orG2
QA thru QH
tdis
50 or 51
QA' or QH'
tPHl
VCC
ClR
QA thru QH
QA' or QH'
tt
QA thru QH
TA - 25°C
MIN TYP MAX
MIN
MAX
4.2
21
25
6
31
36
45
16
13
42
16
12
60
24
23
115
44
39
60
24
23
115
44
39
41
17
13
50
17
13
38
8
6
38
8
6
170
38
32
170
38
32
160
32
27
300
60
51
160
32
27
300
60
51
210
42
36
200
42
36
75
15
13
60
12
10
No load, TA
Power dissipation capacitance
SN54HC299
MIN
MAX
5
25
29
285
57
48
285
57"
48
240
48
41
450
90
77
240
48
41
450
90
77
315
63
54
315
63
54
110
22
19
90
18
15
= 25°C
SN74HC299
UNIT
MHz
210
48
40
210
48
40
200
40
34
375
75
64
200
40
34
375
75
64
250
53
45
250
53
45
95
19
16
75
15
13
ns
ns
•
ns
ns
ns
ns
ns
ns
ns
ns
100 pF typ
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-393
SN54HC299. SN74HC299
8-BIT .UNIVERSAL SHIFT/STORAGE REGISTERS
WITH DIRECT CLEAR AND 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 150 pF (see Note 1)
,
I
I
PARAMETER
FROM (INPUT)
TO (OUTPUT)
tpd
ClK
QA thru QH
III
GlorG2
QA thru QH
ten
50 or 51
::t
C')
s:o
tpHl
ClR
QA thru QH
en
o
tt
CD
<
5"
CD
QA thru QH
Vcc
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 2S0C
MIN TYP MAX
56
21
16
94
38
33
130
59
49
63
21
17
45
17
13
230
46
39
220
44
37
450
90
77
260
52
44
210
42
36
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
en
2-394
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
SNS4HC299
MIN
MAX
345
69
59
330
66
56
675
135
115
390
78
66
315
63
53
SN74HC299
MIN
MAX
288
58
49
275
55
47
563
113
96
325
65
55
265
53
45
UNIT
ns
ns
ns
ns
ns
SN54HC354, SN74HC354
B-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS/
TRANSPARENT REGISTERS WITH 3-STATE OUTPUTS
02684. DECEMBER 1982-REVISEO SEPTEMBER 1987
•
Transparent Latches on Data Select Inputs
•
Transparent Data Registers
•
High-Current 3-State Outputs Can Drive Up
to 15 LSTTL Loads
SN54HC354 •.• J PACKAGE
SN74HC354 ..• OW OR N PACKAGE
(TOP VIEW)
•
Complementary Outputs
•
Package Options: Plastic and Ceramic DIPs.
Plastic Small-Outline Packages. and Ceramic
Chip Carriers
•
Dependable Texas Instruments Quality and
Reliability
Vee
07
06
05
04
03
02
01
00
y
W
G3
132
131
SO
S1
S2
oe
se
GNO
CI)
CD
(,)
description
These monolithic data selectors/multiplexers
contain full on-chip binary decoding to select one
of eight data sources. The data-select is stored
in transparent latches that are enabled by a low
level on pin 11. SC. A similar enable for data is
obtained by a low level on pin 8. DC.
The SN54HC354 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC354 is
characterized for operation from - 40°C to
85°C.
'S;
SN54HC354 ... FK PACKAGE
CD
(TOP VIEW)
C
U
U
000>>-
"'''',...
3
04
03
01
2
C/)
o
1 2019
4
18
W
G3
132
131
SO
5
17
6
16
7
15
14
8
:i!:
(.)
J:
9 1011 12 13
IU
0IU N ~
oZ(J)(J)(J)
logic symbol t
(!)
MUX
Cil
(;2
G3
sc
SO
51
52
DC
DO
01
02
03
04
05
06
07
(2)
90
6
(1)
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Copyright © 1982, Texas Instruments Incorporated
PRODUCTION DATA documents contain i.lormltion
current as of publication date. Products conform to
specifications per the tarms of Texas Instruments
:~~~~:~~i~a{::1~18 ~!:~~~ti:r :,~O::::::':~~S not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-395
SN64HC364. SN74HC354
B·lINE TO '·lINE DATA SELECTORS/MULTIPLEXEIS/
TRANSPARENT REGISTERS WITH 3·STATE OUTPUTS
logic diagram (positive logic)
~ (15)
ii2 (16)
G3 (17)
•
::J:
51 (13)
n
s:
0
(I)
S2 (12)
C
Q)
<
5'
oc
(I)
DO
Q)
01
(7)
02 (6)
~-I-(:..:;19:.:..) y
03 (5)
04 (4)
"»----,(.;..:18;;.) W
05 (3)
D6 (2)
07 (1)
2-396
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC354, SN74HC354
B·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS/
TRANSPARENT REGISTERS WITH 3·STATE OUTPUTS
FUNCTION TABLE
INPUTS
DATA
CONTROL
SELECTt
OUTPUT
ENABLES
G1
G2
G3
H
X
X
X
X
H
X
X
L
H
L
L
S2
S1
X
X
SO
X
X
X
X
X
X
X
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
H
H
L
H
L
L
L
H
L
DC
X
X
X
L
H
L
L
H
L
L
H
L
H
L
L
L
H
H
OUTPUTS
W
V
Z
Z
Z
Z
Z
Z
fI
00
DO
DOn
01
DOn
D1
D1n
02
D1n
D2
D2n
D3
'S;
o
o
L
H
H
L
L
L
H
02n
03
L
H
H
H
L
L
H
03 n
en
CD
(,)
CD
H
L
L
L
L
L
H
D4
D3 n
D4
H
L
L
H
L
L
H
D4 n
D4 n
en
H
H
L
H
H
L
H
L
H
L
L
L
L
D5
D5 n
:E
H
H
L
L
L
L
H
H
05
D5 n
06
D6
H
H
L
H
L
L
H
D6 n
D6 n
H
H
H
L
L
L
H
07
D7
H
H
H
H
L
L
H
D7 n
D7 n
(.)
:x:
H = high level (steady statel
L = low level (steady statel
X = irrelevant (any input, including transitions)
Z = high-impedance state (off statel
t = transition from low to high level
DO ... D7 = the level of stead-state inputs at inputs DO through
D 7. respectively
DOn ... D7 n = the level of steady state inputs at inputs DO through
D7. respectively. before the most recent low-to-high
transition of data control
tThis column shows the input address setup with SC low.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-397
SN54HC354, SN74HC354
B-L1NE TO 1-L1NE DATA SELECTORS/MULTIPLEXERS/
TRANSPARENT REGISTERS WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range t
•
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
1nput clamp current, !iK (Vi < 0 Oi Vi > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K (VO < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Continuous output current, 10 (VO = 0 to Vcc) ......................... ',',' . . .. ±35 rnA
Continuous current through VCC or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package. . . . . . . . . . . . .. 260,oC
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC354
MIN
Vee
VIH
Supply voltage
High-level input voltage
~
2 V
Vee
~
4,5 V
Vee ~ 6 V
Vil
MAX
MIN
NOM
MAX
5
6
2
5
6
2
Vee
Low-level input voltage
SN74HC354
NOM
1.5
3,15
3.15
4.2
4.2
UNIT
V
1.5
V
Vee
~
2V
0
0.3
0
0.3
Vee
~
4.5 V
0
0.9
0
0.9
Vee
~
6 V
0
1.2
0
1.2
V
VI
Input voltage
0
Vee
0
Vee
V
Va
Output voltage
0
0
Vee
1000
0
Vee
1000
V
0
500
0
500
n.
0
-55
400
0
-40
400
Input transition (rise and fall) times
tt
Vee
~
2 V
Vee
~
4.5 V
Vee ~ 6 V
TA
Operating free-air temperature
125
0
85
De
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
VI ~ VIH or Vil.
10H ~
-20~
VI - VIH or Vll,
VI ~ VIH or Vil.
VI ~ VIH or Vil.
10H - -6 rnA
10H ~ -7.8 rnA
10l
~
20 p.A
Val
10l
VI - VIH or Vil.
VI ~ Vee or 0
10l - 7.8 rnA
II
10Z
It::e
ei
2-398
~
VI ~ VIH or Vil.
6 rnA
SN54HC354
SN74HC354
MIN
MIN
MAX
1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
4.5 V
5.9
3.98
5.9
3.7
3.84
6V
5.48
2V
VOH
TA - 25°C
MIN
TYP MAX
1.9
5.999
4.30
5.9
5.2
5.80
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
V
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
Va ~ Vee or 0
6V
±0.01
±0.5
±10
±5
~
VI - Vee or O. 10 - 0
6V
8
160
80
p.A
10
10
10
pF
2 to 6 V
3
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
nA
SN54HC354. SN74HC354
B·L1NE TO '·L1NE DATA SELECTORS/MULTIPLEXERS/
TRANSPARENT REGISTERS WITH 3·STATE OUTPUTS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
Vcc
SC low
tw
Pulse duration
DC low
Data before OCt
tsu Setup time
SO thru 52 before sct
Data after Oct
th
Hold time
SO thru 52 after SCt
TA - 25°C
MIN
MAX
SN54HC354
SN74HC354
MIN
MIN
MAX
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
4.5 V
6V
80
16
120
100
24
20
14
20
17
2V
75
110
95
4.5 V
6V
2V
15
22
19
13
19
16
75
110
95
4.5 V
15
22
19
6V
2V
4.5 V
6V
13
19
16
5
5
5
5
5
5
5
5
5
2V
5
5
5
4.5 V
6V
5
5
5
5
5
5
MAX
UNIT
ns
en
ns
Q)
(,)
'S
Q)
c
en
o
ns
~
o
:::I:
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL ... 50 pF (see Note 1)
PARAMETER
tpd
tpd
FROM
UNPUT}
Any 0
DC
50,51,
tpd
tpd
or 52
SC
G1. G2,
ten
or G3
Gl, G2,
tdis
tt
or G3
TO
(OUTPUTI
WorY
WorY
WorY
WorY
WorY
WorY
WorY
TA _25°C
Vcc
MIN
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TYP
MAX
SN54HC354
MIN MAX
SN74HC354
MIN MAX
90
235
352
295
29
47
71
59
25
40
60
50
115
270
405
337
40
32
54
81
46
69
68
58
120
285
427
355
42
57
86
71
34
48
72
60
120
300
450
375
45
60
90
75
36
50
51
77
64
125
188
155
38
31
15
25
21
32
26
68
165
248
205
24
33
50
41
20
28
43
35
18
2V
28
60
90
75
4.5 V
8
12
18
15
6V
6
10
15
13
Power dissipation capacitance
No load, TA
=
25°C
UNIT
ns
ns
ns
ns
ns
ns
ns
100 pF typ
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-399
SN54HC354. SN74HC354
B·L1NE TO 1·L1NE DATA SELECTORS/MULTIPLEXERS/
TRANSPARENT REGISTERS WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL .. 150 pF (see Note 1)
,
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
·Any D
WorY
Ipd
DC
WorY
:::t
Ipd
SO, S1,
or S2
WorY
s:o
Ipd
SC
WorY
cCD
ten
CD
It
o
t/)
<
(;'
(I)
<31, <32,
or G3
WorY
WorY
VCC
MIN
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA _25°C
TYP MAX
100
275
40
55
46
32
125
310
46
62
38
52
130
325
50
65
40
55
110
340
52
68
42
58
60
165
25
33
21
28
37
210
12
42
10
36
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
2-400
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC354
MIN MAX
412
83
69
465
93
78
488
98
82
510
102
87
248
50
42
315
63
53
SN74HC354
MIN MAX
344
69
59
387
78
66
405
81
69
425
85
UNIT
ns
ns
ns
ns
72
205
41
35
265
53
45
ns
ns
SN54HC365 THRU SN54HC368
SN14HC365 THRU SN14HC368
HEX BUS DRIVERS WITH 3·STATE OUTPUTS
02684. DECEMBER 1 982 - REVISED JUNE 1989
•
•
Choice of True or Inverting Outputs
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
SN54HC366. SN54HC366 ..• J PACKAGE
SN74HC365. SN74HC366 ••• Dt OR N PACKAGE
High·Current 3-Stete Outputs Drive Bus
Lines, Buffer Memory Address Registers, or
Up to 15 LSTTL Loads
ITOPVIEW)
G1
A1
Y1
A2
Y2
A6
Y6
A5
Y5
fI
A4
'-L:""""'::..J-'Y4
Dependable Texas Instruments Quality and
Reliability
'HC365, HC367
'HC366, HC368
Vee
G2
SN54HC365. SN54HC366 ... FK PACKAGE
True Outputs
Inverting Outputs
ITOPVIEW)
u
UN
IC)
........... U
description
3
These Hex·buffers and line drivers are designed
specifically to improve both the performance and
density of three-state memory address drivers,
clock drivers, and bus-oriented receivers and
transmitters. The designer has a choice of
selected combinations of inverting and
noninverting outputs, symmetrical G (active-low
control) inputs.
2 1 20 19
18
17
16
14
A5
Y5
9 10 11 12 13
The SN54HC' family is characterized for
operation over the full military temperature range
of - 55 DC to 125 DC. The SN74HC' family is
characterized for operation from -40 DC to
85 D C.
SN54HC367. SN54HC368 •.• J PACKAGE
SN74HC367. SN74HC368 ... ot OR N PACKAGE
ITOPVIEW)
1G
1A1
1Y1
1A2
1Y2
1A3
1Y3
GND
vee
2G
2A2
2Y2
2A1
2Y1
1A4
1Y4
SN54HC367. SN54HC368 ... FK PACKAGE
ITOP VIEW)
3
1Y1
1A2
2 1 2019
4
18
5
17
16
15
14
9 10111213
NC - No internal connection
t Contact the factory for 0 availability.
PRODUCTION DATA do.umants cantain information
currnt as at publication data. Products confarm to
spacifications per the tarms of raxi. Instrllments
='=i;li~:I~tzi
=::i:; :.~o:::::~:.~ not
Copyright @ 1989, Texas Instruments Incorporated
TEXAS
-Ii}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-401
SN54HC365 THRU SN54HC368
SN74HC365 THRU SN74HC368
HEX BUS DRIVERS WITH 3-STATE OUTPUTS
logic symbols t
'HC366
'HC365
Gl
112
Al
A2 14)
\l
15)
VI
V2
17)
A3 16)
A4 11O)
•
13)
V3
19)
V4
111)
V5
113)
V6
A5 112)
A6 114 )
Al 12)
VI
A2 14)
A3 16)
110)
A4 112)
A5
A6 114)
V2
V3
V4
V5
V6
::t:
(')
'HC368
'HC367
:s:
lG
en
lAl
0
lA2
1Yl
lV2
<
lA3
lA4
1Y4
0
(1)
c:;(1)
lG
lV3
lVl
lA2
lA3
lA4
lV2
1V3
lV4
20
2G
en
lAl
2Al
2Vl
2Vl
2A2
2V2
2V2
logic diagrams (positive logic)
'HC365
'HC367
'HC366
tThese symbols are in accordance with ANSI/IEEE Std 91-1984
and lEe Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
2-402
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
'HC368
SN54HC365 THRU SN54HC368
SN74HC365 THRU SN74HC368
HEX BUS DRIVERS WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee ................................................. -0.5 V to 7 V
Input clamp current, 11K (V, < 0 or V, > Vee) .................................. ± 20 rnA
Output clamp current, 10K (Vo < 0 or Vo > Vee) .............................. ± 20 rnA
Continuous output current, 10 (VO = 0 to Vee) ................................. ± 35 rnA
Continuous current through Vee or GND pins ................................... ± 70 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ................ 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ................. 260°C
Storage temperature range .......................................... - 65°C to 150°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SN54HC365
SN74HC365
thru
thru
SN54HC368
Vee Supply voltage
Vee - 2 V
VIL
High-level input voltage
Low-level input voltage
Vee ~ 4.5 V
CD
UNIT
NOM
MAX
2
5
6
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
3.15
Vee ~ 6 V
4.2
Vee - 2 V
0
0.3
V
:E
V
:J:
4.2
0
0.3
~
4.5 V
0
0.9
0
0.9
Vee
~
6 V
0
1.2
0
1.2
V
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
Vee
1000
0
Vee
V
0
1000
TA
Input transition (rise and fall' times
Operating
free~air
0
Vee
~
4.5 V
0
500
0
500
Vee
~
6 V
0
400
0
400
-55
125
-40
85
temperature
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
o
(.)
Vee
Vee ~ 2 V
o
CJ)
SN74HC368
MIN
VI
tt
tI)
CD
U
oS
recommended operating conditions
VIH
fI
n'
°e
5N54HC365 THRU 5N54HC368
5N74HC365 THRU SN74HC368
HEX BUS DRIVERS WITH 3·STATE OUTPUTS
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
I
I
i
i
TEST CONDITIONS
PARAMETER
VCC
TA - 25°C
MIN
•
~
3:
oen
= V,H or V,L.
V,
V,
= V,H or V,L. IOH =
= V,H or V,L. 10H =
IOH
= - 20 p.A
VOH
V,
-6 mA
-7.8 mA
= V,H or V,L. 10L = 20 p.A
VOL
= V,H or V,L. 10L -6 mA
= V,H or V,L. 10L = 7.8 mA
= VCC or 0
Vo = VCC orO
V, = VCC or O. 10 = 0
V,
V,
V,
c
"
10Z
<
(;'
ICC
Cj
CD
V,
2V
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6
6V
2 to 6 V
TYP
MAX
SN74HC365
thru
SN54HC368
MIN MAX
thru
SN74HC368
MIN MAX
1.9
4.4
1.9 1.998
4.4 4.499
1.9
4.4
5.9 5.999
5.9
3.7
3.98
5.48
4.30
5.80
0.002
0.1
0.001
0.001
0.17
0.1
0.1
0.26
5.9
0.15 0.26
±0.1 ±100
±O.Ol
±0.5
3
8
10
tn
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75265
UNIT
V
3.84
5.34
5.2
CD
2·404
SN54HC365
0.1
0.1
0.1
0.4
0.4
±1000
±10
160
10
0.1
0.1
0.1
0.33
V
0.33
±1000
nA
±5
~A
80
10
p.A
pF
SN54HC365 THRU SN54HC368
SN74HC365 THRU SN74HC368
HEX BUS DRIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
TA - 25°C
MIN TYP
MAX
SN54HC'
SN74HC'
PARAMETER
FROM (INPUT)
TO (OUTPUT)
vCC
2V
50
95
145
120
tpd
A
Y
4.5 V
12
19
29
24
6V
10
16
25
20
ten
tdis
G
G
Y
Y
Any
tt
MIN
MAX
MIN
MAX
2V
100
190
285
238
4.5 V
26
38
57
48
6V
21
32
48
41
2V
50
175
265
240
4.5 V
21
35
53
48
6V
19
30
45'
41
2V
28
60
90
75
4.5 V
8
12
18
15
6V
6
10
15
13
Power dissipation capacitance per driver
UNIT
ns
fI
ns
ns
U)
Q)
CJ
'S
ns
Q)
c
en
o
35 pF typ
No load. TA = 25 0 C
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 150 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC
TA - 25°C
MIN TYP MAX
2V
tpd
ten
tt
A
G
Y
y
SN54HC'
MIN
MAX
SN74HC'
MIN
MAX
70
120
180
150
4.5 V
17
24
36
30
6V
14
20
31
25
285
2V
140
230
345
4.5 V
30
46
69
57
6V
28
39
59
48
265
2V
45
210
315
4.5 V
17
42
63
53
6V
13
36
53
45
:iE
(J
~
UNIT
no
ns
ns
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-405
IE
::J:
(")
3l:
oen
c
CD
<
C:;'
CD
en
2-406
SN54HC373, SN74HC373
OCTAL D·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
02684, DECEMBER 1982-REVISEO JUNE 1989
•
8 High·Current Latches in a Single Package
•
High·Current 3·State True Outputs Can
Drive Up to 15 LSTTL Loads
•
Full Parallel Access for Loading
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300·mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC373 •.• J PACKAGE
SN74HC373 ... ow OR N PACKAGE
ITOP VIEW)
De
Vee
10
10
20
20
30
3D
40
40
80
80
70
70
60
60
50
50
CD
(J
o
u
~ ~Ig ~~
3
20
20
30
3D
40
2
en
o
1 20 19
4
18
17
16
8
14
nDt
::t:
15
9 1011 1213
"d"Z
1J')Lt)
(!)
logic symbol t
(2)
10
(4)
15)
3D
171
(6)
40
(8)
20
10
20
30
(9)
50 (13)
60 (14)
40
112)
(15)
(16)
70 (17)
118)
119)
80
50
60
7Q
80
tThis symbol is in accordance with ANSIIIEEE Std 91·1984 and
lEe Publication 617·12.
FUNCTION TABLE
lEACH LATCH)
H
=:;ti:r :.~a:::::Nt::.s
(,,)
5
6
OUTPUT
INPUTS
PROOUCTION DATA documants ..ntain info,mation
currant as of publication data. P,aducts conform to
spacificatial. per the tarms af TaxIS Instruments
:iE
aQUaQ
The output control (OC) does not affect the
internal operations of the latches. Old data can
be retained or new data can be entered while the
outputs are off.
The SN54HC373 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC373 is
characterized for operation from - 40°C to
85°C.
CD
ITOP VIEWI
The eight latches of the 'HC373 are transparent
O·type latches, While the enable (C) is high. the
Q outputs will follow the data (0) inputs, When
the enable is taken low. the Q outputs will be
latched at the levels that were set up at the 0
inputs,
An output·control input (OC) can be used to
place the eight outputs in either a normal logic
state (high or low logic levels) or a high·
impedance state, In the high·impedance state
the outputs neither load nor drive the bus lines
significantly, The high·impedance third state and
increased drive provide the capability to drive the
bus lines in a bus·organized system without need
for interface or pull·up components.
':;
SN54HC373 ... FK PACKAGE
These 8·bit latches feature three·state outputs
designed specifically for driving highly capacitive
or relatively low·impedance loads, They are
particularly suitable for implementing buffer
registers, 1/0 ports. bidirectional bus drivers. and
working registers,
::==i~·{:I':.7i
en
e
GNO
description
DC
ENABLE C
0
a
L
H
H
H
L
H
L
L
L
L
Qo
H
X
X
X
= high level,
Z
= low level,
Z
X
= irrelevant
Copyright @ 1989, Texas Instruments Incorporated
TEXAS
-1.!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2·407
SN54HC373. SN74HC373
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
logic diagram (positive logic)
10 (3)
11
20 (4)
::I:
0
3l:
0
(7)
30
40 (8)
40
30
en
0
CD
<
5"
CD
(I)
(13)
50
60 (14)
70
70
(17)
(18)
80
2-408
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC373, SN74HC373
OCTAL O-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range t
Supply voltage. Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current. 11K (V, < 0 or V, > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current. 10K (VO < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
eontinuous output current. 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±35 mA
eontinuous current through Vee or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
lead temperature 1.6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300 0 e
lead temperature 1.6 mm (1/16 in) from case for 10 s: OW or N package .............. 260 0 e
Storage temperature range ......................................... - 65 °e to 1 50 0 e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
fI
recommended operating conditions
SN54HC373
MIN NOM MAX
Vee Supply voltage
VIH
VIL
High-level input voltage
Vee
Vee
Low-level input voltage
Vee
Vee
Vee
Vee
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
Vee
Vee
Vee
2
1.5
3.15
4.2
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
=
=
=
0
0
0
0
2V
4.5 V
0
0
-55
6 V
6
0.3
0
0
Operating free-air temperature
TA
5
SN74HC373
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0
UNIT
V
V
0.9
1.2
0
0
0.9
1.2
V
Vee
Vee
1000
500
400
0
0
Vee
Vee
1000
500
400
V
V
125
0
0
0
-40
85
ns
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
VI
=
VIH or VIL.
IOH
=
-20,.A
4.5 V
6V
VI
VI
=
=
VIH or VIL.
VIH or VIL.
IOH
IOH
=
=
-6mA
4.5 V
6V
2V
4.5 V
VOH
VI
= VIH or VIL.
IOL
-7.B rnA
= 20,.A
VOL
II
IOZ
Ice
ei
VI - VIH or VIL.
VI = VIH or VIL.
VI = Vee orO
Vo = Vee or 0
VI
= Vee or O.
10L - 6 rnA
IOL = 7.B rnA
10
=0
6V
4.5 V
6V
6V
6V
6V
2 to 6 V
TA - 25°C
MIN
TYP MAX
1.9 1.998
4.4 4.499
5.9 5.999
3.98
5.4B
4.30
5.80
0.002
0.1
0.001
0.001
0.17
0.15
0.1
0.1
0.26
0.26
±0.1
±0.01
±100
±0.5
3
B
10
SN54HC373
MIN
1.9
4.4
5.9
3.7
MAX
5.2
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74HC373
MIN
1.9
4.4
5.9
3.84
5.34
MAX
V
0.1
0.1
0.1
0.1
0.1
0.4
0.4
0.1
0.33
0.33
±1000
±5
±1000
±10
160
10
UNIT
BO
10
V
nA
,.A
~A
pF
2-409
SN54HC373, SN74HC373
OCTAL OoTYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
Vcc
•
tw
Pulse duration, enable C high
tsu
Setup time, data before enable ct
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Hold time, data after enable CI
th
::z::
I SN54HC373 I SN74HC373 I
MIN
80
16
14
50
10
MAX
9
20
10
10
MIN
120
24
20
75
15
13
26
13
13
MAX
MIN
100
20
17
63
13
11
24
12
12
MAX
UNIT
ns
ns
ns
(')
3:
o
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
en
PARAMETER
C
FROM
(INPUT)
TO
(OUTPUT)
CD
<
n'
CD
tpd
0
Q
tpd
C
Any Q
ten
OC
Any Q
tdis
OC
Any Q
en
tt
Any Q
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Power dissipation capacitance per latch
TA = 25°C
MIN
TYP MAX
58
150
15
30
13
26
73
175
18
35
30
15
"65
150
30
17
14
26
150
50
30
15
13
26
60
28
12
8
6
10
No load, TA
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
2-410
TEXAS .".
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC373
MIN MAX
225
45
38
265
53
45
225
45
38
225
45
38
90
18
15
= 25°C
SN74HC373
MIN MAX
190
38
32
220
44
38
190
38
32
190
38
32
75
15
13
100pFtyp
UNIT
ns
ns
ns
ns
ns
SN54HC373, SN74HC373
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted!. CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
D
Q
tpd
C
Any Q
ten
DC
Any Q
tt
Any Q
vcc
TA = 25°C
TYP MAX
MIN
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
.2V
4.5 V
6V
82
22
19
100
24
20
90
23
19
45
17
13
200
40
34
225
45
38
200
40
34
210
42
36
SN54HC373
MIN
MAX
300
60
51
335
67
57
300
60
51
315
63
53
SN74HC373
MIN
MAX
250
50
43
285
57
48
250
50
43
265
53
45
UNIT
ns
ns
ns
II
ns
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-411
E
:::J:
(')
s:o
C/)
c
CD
<
(;'
CD
en
2-412
SN54HCT313. SN14HCT313
OCTAL OoTYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
02804, MARCH 1984-REVISEO SEPTEMBER 19B7
SN54HCT373 .•. J PACKAGE
SN74HCT373 ... OW OR N PACKAGE
•
Inputs are TTL-Voltage Compatible
•
8 High-Current Latches in a Single Package
•
High-Current 3-State True Outputs Can
Drive Up to 15 LSTTL Loads
•
Full Parallel Access for Loading
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments auality and
Reliability
(TOP VIEW)
oe
Vee
10
10
20
20
30
30
40
40
80
80
70
70
60
60
50
50
description
II
en
e
GNO
Q)
(.)
'>
SN54HCT373 ... FK PACKAGE
(TOP VIEW)
These 8-bit latches feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, 110 ports, bidirectional bus drivers, and
working registers.
Q)
c
U
en
Od\U Ud
~~O>oo
3
20
20
30
30
40
The eight latches of the 'HCT373 are
transparent D-type latches. While the enable (C)
is high the Q outputs will follow the data (D)
inputs. When the enable is taken low, the Q
outputs will be latched at the levels that were
set at the D inputs.
2
o
1 2019
4
18
5
17
6
16
7
15
~
CJ
::z::
14
8
9 10 11 12 13
dOUdO
o;tZ
",,,,
t:)
An output-control input (OC) can be used to
place the eight outputs in either a normal logic
state (high or low logic levels) or a highimpedance state. In the high-impedance state
the outputs neither load nor drive the bus lines
significantly. The high-impedance third state and
increased drive provide the capability to drive the
bus lines in a bus-organized system without need
for interface or pull-up components.
FUNCTION TABLE (EACH LATCH)
INPUTS
oc
ENABLE C
L
H
L
H
L
L
H
X
OUTPUT
0
H
L
X
X
Q
H
L
00
Z
The output control (DC) does not affect the
internal operations of the latches. Old data can
be retained or new data can be entered while the
outputs are off.
The SN54HCT373 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCT373 is
characterized for operation from -40°C to
85°C.
PRODUCTION DATA documents contain information
curnllt I. of ,.blicatial d.... Prod.cts canform ta
IpacHiclltiollS par
tn tarms of TillS Instruments
:=:'~::"i:r.7~
=::r:.:o:.o::.:~~
not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
Copyright © 1984, Texas Instruments Incorporated
2-413
SN54HCT373, SN74HCT373
OCTAL D·TYPE TRANSPARENT LATCHES WITH 3~STATE OUTPUTS
logic symbol t
logic diagram (positive logic)
~ III
10
20
3D
30
40
50 (13)
60 (14)
50
70 (17)
80 (18)
::I:
n
o3!:
10
20
~~..........~
10 (31
40
(15)
(16)
(19)
20 (4)
60
70
80
tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and
lEe Publication 617-12.
3D (7)
t/)
C
40 (8)
CD
<
(;'
CD
(I)
(13)
50 - - - -.....
+-1
60 ...;(.;.14.;,;.1.....~1--I
70 (17)
80 (18)
2-414
TEXAS
-1.!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
50
SN54HCT373, SN74HCT373
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature range t
Supply voltage, Vee ................................................. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) .................................. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) .............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) ................................. ± 35 mA
Continuous current through Vee or GNO pins ................................... ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ................ 300 DC
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package ............... 260 De
Storage temperature range .......................................... - 65 DC to 1 50 DC
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
fI
fI)
Q)
CJ
recommended operating conditions
VCC
VIIi
VIL
VI
Vo
tt
TA
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
Input transition (rise and fall) times
I VCC = 4.5 V to 5.5 V
I VCC = 4.5 V to 5.5 V
Operating free-air temperature
MIN
4.5
2
0
0
0
0
-55
2
0
0
0
0
-40
0.8
VCC
Vce
500
125
'S
SN74HCT373
SNS4HCT373
MIN NOM MAX
4.5
5.5
5
NOM MAX
5
5.5
Q)
UNIT
c
en
V
o
V
V
V
0.8
VCC
~
(,)
V
ns
·C
Vce
500
85
J:
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
TEST CONDITIONS
PARAMETER
VOH
VOL
II
IOZ
ICC
Alce*
Ci
VI
VI
= VIH or VIL.
= VIH or VIL.
10H = -20 f'A.
10H = -6 mA
VI - VIH or VIL. IOL - 20 f'A.
VI = VIH or VIL. 10L = 6 mA
VI = VCC or 0
Vo = Vec or 0
VI = Vee or O. 10 = 0
One input at 0.5 V or 2.4 V
Other inputs at 0 V or VCC
VCC
4.5V
4.5 V
4.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
TA - 2S·C
MIN
TVP MAX
4.4 4.499
3.98
4.30
0.001
0.1
0.17 0.26
±0.1 ±100
SN54HCT373 SN74HCT373
MIN
4.4
3.7
MAX
MIN
4.4
3.84
MAX
UNIT
V
±0.5
0.1
0.4
±1000
±10
±1000
±5
8
160
80
f'A.
f'A.
1.4
2.4
3
2.9
mA
3
10
10
10
pF
±O.Ol
4.5 V to
5.5 V
0.1
0.33
V
nA
*Thls is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or Vce.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-415
SN54HCT373, SN74HCT373
OCTAL O-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
Vcc
tw
tsu
th
•
::I:
o
3:
Pulse duration, enable C high
Setup time, data before enable C.
Hold time, data after enable C.
ISN54HCT373ISN74HCT373I
TA
.. - 25°C
UNIT
MIN MAX
MIN
TYP MAX
MIN MAX
4.5 V
20
30
25
5.5 V
17
27
23
4.5 V
10
15
13
5.5 V
4.5 V
9
14
12
10
10
10
5.5 V
10
10
10
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
o(I)
o
CD
<
(;'
FROM (INPUT)
TO (OUTPUT)
tpd
D
Q
tpd
C
Any Q
ten
OC
Any Q
tdis
OC
Any Q
CD
(I)
Any Q
tt
SN54HCT373
SN74HCT373
VCC
TA - 25°C
MIN TYP MAX
4.5 V
25
35
53
44
5.5 V
21
32
48
40
4.5V
28
35
53
44
5.5 V
25
32
48
40
4.5 V
26
35
53
44
5.5 V
23
32
48
40
4.5 V
23
35
53
44
5.5 V
22
32
48
40
4.5 V
10
12
18
15
5.5 V
9
11
16
14
Power dissipation capacitance per latch
MIN
MAX
MIN
No load, TA = 25°C
MAX
UNIT
ns
ns
ns
ns
ns
50 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
tpd
D
Q
tpd
C
Any Q
ten
OC
Any Q
tt
Any Q
TA - 25°C
MIN TYP MAX
4.5 V
32
52
79
65
5.5 V
27
47
71
59
4.5 V
38
52
79
65
5.5 V
36
47
71
59
4.5 V
33
28
52
79
5.5 V
47
71
4.5 V
18
42
63
5.5 V
16
38
57
65
69
53
48
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-416
SN54HCT373 SN74HCT373
VCC
TEXAS .."
INSfRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
MAX
MIN
MAX
UNIT
ns
ns
ns
ns
SN54HC374, SN74HC374
OCTAL D-TYPEEDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
DECEMBER
•
8 D-Type Flip-Flops in a Single Package
•
High-Current 3-State True Outputs Can
Drive Up to 15 LSTTL Loads
•
Full Parallel Access for Loading
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC374 ... J PACKAGE
SN74HC374 ... OW DR N PACKAGE
(TOP VIEW)
oe
Vee
10
10
20
20
30
30
40
40
GNO
description
fI
U)
eLK
Q)
(.)
'S;
SN54HC374 ... FK PACKAGE
These 8-bit flip-flops feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
Q)
(TOP VIEW)
o
en
o
U
~ ~Ig ~~
3
20
20
30
30
40
The eight flip-flops of the 'HC374 are edgetriggered D-type flip-flops. On the positive
transition of the clock, the Q outputs will be set
to the logic levels that were set up at the D
inputs.
2
1 20 19
::E
4
18
5
17
6
16
8
15
14
()
::a:::
9 1011 1213
An output-control input (OC) can be used to
place the eight outputs in either a normal logic
state (high or low logic levels) or a highimpedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines
significantly. The high-impedance third state and
increased drive provide the capability to drive the
bus lines in a bus-organized system without need
for interface or pull-up components.
The output control (OC) does not affect the
internal operation of the flip-flops. Old data can
be retained or new data can be entered while the
outputs are in the high-impedance state.
80
80
70
70
60
60
50
50
FUNCTION TABLE (EACH FLIP-FLOP)
INPUTS
oc
ClK
L
t
t
L
L
H
X
L
H
= high level,
L
=
OUTPUT
0
H
L
X
X
low level. X
Q
H
l
Qo
Z
= irrelevant.
The SN54HC374 is characterized for operation
over the full military temperature range of
- 55 DC to 125 DC. The SN74HC374 is
characterized for operation from - 40 DC to
85 D C.
PRODUCTIOI DATA d••umlnts contli. information
•• ,nnt al of publicllion data. Pradum confo,m to
:r:lCificatiol. per the tIIr. of rell. Inltnlmaats
n=ri~·:::I':.'l~ =:I:;U:; ~\,,~.:~~...ot
Copyright © 1982. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-417
SN54HC374, SN74HC374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
logic symbol t
10
(3)
10
(2)
(7)
(6)
40 (8)
(9)
50 (13)
3:
60
C")
<
\l
(5)
::I:
c
C'D
C>
20 (4)
3D
o(J)
logic diagram (positive logic)
70
80
(12)
10
-""-1
20 ;.;(4;.;)
20
30
30:...(7.:..)_-+~
40
50
(14)
(15) 60
(17)
(16)
(18)
(19)
40",(8;.;)_-+-1
70
80
50;';(1....:3)'---+-1
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
5'
C'D
en
70':":'1..:..7)'---+-1
(18)
80'-----1
2-418
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SN54HC374, SN74HC374
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS
WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee ................................................. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Veel .................................. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Veel .............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Veel ................................. ± 35 mA
Continuous current through Vee or GND pins ................................... ± 70 mA
Lead temperature 1,6 mm (1/16 inl from case for 60 s: FK or J package ................ 300 De
Lead temperature 1,6 mm (1/16 in) from case for 10 s: DW or N package ............... 260 DC
Storage temperature range .......................................... - 65°C to 150 DC
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated· under "recommended operating
conditions" is not implied. Exposure to absolute~maximum-rated conditions for extended periods may affect device reliability.
fI
U)
Q)
CJ
recommended operating conditions
os:
SN54HC374
Vee Supply voltage
VIH
High-level input voltage
Low-level input voltage
MIN
NOM
MAX
2
5
6
MIN
NOM
MAX
2
5
6
Vee - 2 v
1.5
1.5
= 4.5
3.15
3.15
Vee
V
Vee = 6 V
Vee - 2 V
VIL
SN74HC374
Vee
Vee
V
V
4.2
4.2
= 4.5 V
=6V
UNIT
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
V
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
Vee
1000
0
Vee
1000
V
0
500
0
500
n.
0
-55
400
0
-40
400
tt
Input transition (rise and fall) times
Vee
TA
=2V
= 4.5 V
=6V
0
Operating free-air temperature
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TeXAS 75265
125
0
en
o
::iE
(J
0
VI
vee
Vee
Q)
C
85
J:
·e
2-419
SN54HC374, SN74HC374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
i
i
i
PARAMETER
TEST CONDITIONS
VI
•
VOH
=
VIH or Vil. 10H
=
VI
=
VIH or Vll, 10H
=
=
VI
=
VIH or Vll, 10l
=
VI - VIH or Vll, 10H
-20
~A
-6 mA
-7.8mA
20 ~
J:
n
VOL
s:
oen
cCD
<
c)'
VI - VIH or Vll, 10l - 6 mA
VI - VIH or Vll, 10l - 7.8 mA
=
i
i
VCC
TA - 25°C
MIN
TYP MAX
SN54HC374
MIN
MAX
i
i
SN74HC374
MIN
2V
1.9 1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
5.9 5.999
5.9
5.9
4.5 V
3.98
4.30
3.7
3.84
6V
5.48
5.80
5.2
5.34
MAX
i
UNIT
V
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
V
II
VI
VCC or 0
6V
±0.1 ±100
±1000
±1000
nA
10Z
Vo - VCC or 0
6V
±0.01
±0.5
±10
±5
~A
ICC
VI
8
160
80
~A
3
10
10
10
pF
=
VCC or 0, 10
=0
6V
2 to 6 V
Ci
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
CD
(I)
VCC
fclock
tw
tsu
th
Clock frequency
Pulse duration
I ClK high or low
Setup time, data before ClK!
Hold time, data after ClK!
SN54HC374
SN74HC374
MIN
MAX
MIN
MAX
6
0
4
0
5
2V
0
4.5 V
0
30
0
20
0
24
6V
2V
0
35
0
24
28
80
120
0
100
4.5 V
16
24
20
6V
14
20
17
2V
100
150
125
4.5 V
20
30
25
6V
2V
17
10
25
21
13
12
4.5 V
5
5
5
5
5
5
6V
2-420
TA - 25°C
TYP MAX
MIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
MHz
ns
ns
ns
SN54HC374, SN74HC374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
f max
'pd
eLK
Any Q
ten
oe
Any Q
tdis
oe
Any Q
Any Q
tt
Vcc
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN TYP MAX
12
6
30
60
35
70
63
180
17
36
15
31
60
150
16
30
14
26
36
150
17
30
16
26
28
60
8
12
6
10
No load, TA
Power dissipation capacitance per flipRflop
SN54HC374
MIN MAX
4
20
24
270
54
46
225
45
38
225
45
38
90
18
15
= 25°C
SN74HC374
MIN MAX
5
24
28
225
45
38
190
38
32
190
38
32
75
15
13
UNIT
MHz
•
n.
n.
en
Q)
CJ
'S>
n.
Q)
c
en
n.
o
:!:
CJ
:J:
100 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
f max
tpd
CLK
Any
'en
oe
Any Q
t,
Q
Any Q
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN TYP MAX
12
6
30
60
35
70
80
230
22
46
19
39
70
200
40
25
22
34
45
210
17
42
13
36
SN54HC374
MIN MAX
4
20
24
345
69
58
300
60
51
315
63
53
SN74HC374
MIN MAX
5
24
28
290
58
49
250
50
43
265
53
45
UNIT
MHz
n.
n.
n.
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-421
II
~
(")
s:o
t/)
c(1)
<
5'
(1)
en
2-422
SN54HCT374. SN74HCT374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
02804. MARCH 1984-REVISEO SEPTEMBER 1987
•
Inputs are TTL-Voltage Compatible
•
8 D-Type Flip-Flops in a Single Package
•
High-Current 3-State True Outputs Can
Drive Up to 15 LSTTL Loads
SN54HCT374 ... J PACKAGE
SN74HCT374 ... OW OR N PACKAGE
•
Full Parallel Access for Loading
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
ITOP VIEW)
oe
Vce
1Q
10
20
2Q
3Q
3D
40
4Q
GNO
description
8Q
80
70
7Q
6Q
60
50
5Q
II
U)
CLK
CD
U
"S
SN54HCT374 ... FK PACKAGE
These 8-bit flip-flops feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
en
U
~ ~Ig ~~
3
20
2Q
3Q
3D
40
The eight flip-flops of the 'HCT374 are edgetriggered D-type flip-flops. On the positive
transition of the clock, the Q outputs will be set
to the logic levels that were set up at the D
inputs.
2
o
:IE
1 2019
4
18
5
17
6
16
7
15
8
14
CJ
:::J:
80
70
7Q
6Q
60
9 1011 1213
oc"'Oc
vZ-'Ll)Ln
An output-control input (OC) can be used to
place the eight outputs in either a normal logic
state (high or low logic levels) or a highimpedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines
significantly. The high-impedance third state and
increased drive provide the capability to drive the
bus lines in a bus-organized system without need
for interface or pull-up components.
The output control (OC) does not affect the
internal operation of the flip-flops. Old data can
be retained or new data can be entered while the
outputs are in the high-impedance state.
CD
c
ITOP VIEW)
ClU
FUNCTION TABLE lEACH FLIP-FLOP)
INPUTS
H
~
De
ClK
l
l
T
T
L
H
OUTPUT
0
H
Q
H
L
L
L
X
00
X
X
Z
high level, L
~
low level. X
~
irrelevant
The SN54HCT374 is characterized for operation
over the full military temperature range of
-55 DC to 125 DC. The SN74HCT374 is
characterized for operation from - 40 DC to
85 D C.
PRODUCTIOI DATA documants contain infarm.tion
....ent .s 01 publi••tion data. Produots .onform to
_ilioatio.. per thl tarms 01 Tlxl. Instrumlnts
::'~::~i:;ei~:I':.'l.i ~:~~~i:; :.r::;:::lt:~~ not
Copyright @ 1984, Texas Instruments Incorporated
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-423
SN54HCT374, SN74HCT374
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS
WITH 3·STATE OUTPUTS
logic symbol t
logic diagram (positive logic)
DC
ClK
eLK
..:...;.:.:..--t>
1Q
10
10
20
3D
40
::::t
(')
50
3:
60
en
70
C
80
0
I>
'V
(21
(41
(51
(71
(61
(81
(91
(131
(141
10
20
30
20
2Q
(41
40
(121
50
(151 60
(171
(161 70
(181
(191
3D ......;.;.(7.;..1- - I H
80
CD
<
(r
....;.;"---~--1
1Q
tThis symbol is in accordance with ANSI/IEEE Std 91-1984
and lEe Publication 617-12.
40
(81
50
(13)
4Q
CD
(I)
60 _(;.;.14.;.;.1_-IH
2-424
TEXAS
70
(17)
80
1181
~
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265
P--+ooooCl
~-- 7Q
SN54HCT374. SN74HCT374
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS
WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature range t
Supply voltage, Vee ................................................. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) .................................. ± 20 rnA
Output clamp current, 10K (Vo < 0 or Vo > Vee) .............................. ± 20 rnA
Continuous output current, 10 (VO = 0 to Vee) ................................. ±35 rnA
Continuous current through Vee or GNO pins ................................... ± 70 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ................ 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package ............... 260°C
Storage temperature range .......................................... - 65°C to 150°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HCT374
Vee Supply voltage
VIH High-level input voltage
tt
Low-level input voltage
Input voltage
Output voltage
Input transition Irise and fall) times
TA
Operating free-air temperature
VIL
VI
Vo
I Vee
I Vee
SN74HCT374
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
V
V
2
- 4.5 V to 5.5 V
2
= 4.5 V to 5.5 V
0
0.8
0
0.8
V
0
Vee
0
Vee
V
0
Vee
500
0
Vee
500
ns
85
·e
0
-55
125
0
-40
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
TA - 25·C
TYP MAX
MIN
MIN
MAX
MIN
VI = VIH or VIL, IOH = -6 mA
4.5 V
VI - VIH or VIL, IOL - 20 ~A
4.5 V
0.001
0.1
0.1
0.1
VI = VIH or VIL, IOL = 6 mA
4.5 V
0.17
0.26
0.4
0.33
VI = Vee or 0
5.5 V
±0.1 ±100
±1000
±1000
nA
IOZ
Vo = Vee or 0
5.5 V
±0.01
±0.5
±10
±5
~A
ICC
VI = Vee or 0, 10 = 0
One input at 0.5 V or 2.4 V
5.5 V
8
160
80
p.A
1.4
2.4
3
2.9
mA
3
10
10
10
pF
VOL
II
Alee~
ei
Other inputs at 0 V or Vee
5.5 V
4.30
4.5 V to
5.5 V
4.4
3.7
3.84
UNIT
4.5 V
3.98
4.4
MAX
VI = VIH or VIL, IOH = - 20 p.A
VOH
4.4 4.499
SN54HCT374 SN74HCT374
V
tThis is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or
TEXAS
~
INSTRUMENTS
POST OFF!CE BOX 655012 • DALLAS, TEXAS 75265
V
Vee.
2-425
SN54HCT374, SN74HCT374
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS
WITH 3·STATE OUTPUTS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
Vcc
fclock
Pulse duration, CLK high or low
tw
•
:r::
(')
s:
otn
Clock frequency
tsu
Setup time, data before CLKt
th
Hold time, data after CLKt
TA - 25°C
I SN54HCT374I SN74HCT374I
MIN
TYP MAX
MIN MAX
MIN MAX
4.5 V
0
31
0
21
0
25
5.5 V
0
36
0
23
0
28
4.5 V
16
24
5.5 V
14
22
18
4.5 V
20
30
25
5.5 V
17
27
23
4.5 V
10
10
10
5.5 V
10
10
10
UNiT
MHz
20
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
C
FROM (INPUT)
TO (OUTPUT)
f max
CD
<
ri'
tpd
CLK
ten
OC
Any Q
tdis
OC
Any Q
Any Q
tt
TA - 25°C
MIN TYP MAX
SN54HCT374 SN74HCT374
MIN
MAX
MIN
4.5 V
31
36
21
25
5.5 V
36
40
23
28
4.5 V
Any Q
CD
(I)
vcc
54
MAX
MHz
5.5 V
30
25
36
32
49
45
. 41
4.5 V
26
30
45
38
5.5 V
23
27
41
34
4.5 V
23
30
45
38
5.5 V
22
27
41
34
4.5 V
5.5 V
10
12
18
15
9
11
16
14
ns
ns
ns
ns
85 pF typ
No load, TA = 25°C
Power dissipation capacitance
UNIT
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
tpd
CLK
Any Q
ten
tt
.
OC
Any Q
Any Q
VCC
TA - 25°C
MIN TYP MAX
MIN
MAX
MIN
MAX
4.5 V
40
46
69
58
5.5 V
35
41
62
52
4.5 V
34
40
60
50
5.5 V
36
42
54
45
4.5 V
29
18
63
53
5.5 V
16
38
57
48
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-426
SN54HCT374 SN74HCT374
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
ns
ns
ns
SN54HC375, SN74HC375
4-BI1 BISTABLE LATCHES
02804, MARCH 1984- REVISED SEPTEMBER 1987
•
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
SN54HC375 ... J PACKAGE
SN74HC375 ... 0 OR N PACKAGE
(TOP VIEW)
10
VCC
40
10
Dependable Texas Instruments Quality and
Reliability
10
40
40
lC,2C
description
Th SN54HC375 and SN74HC375 bistable
latches are electrically and functionally identical
to the SN54HC75 and SN74HC75, respectively.
Only the arrangement of the terminals has been
changed in the SN54HC375 and SN74HC375.
20
3C, 4C
20
30
20
30
GNO
30
II)
'S:
U
CD
I~ ~ ~ ~~
3
2
c
en
1 20 19
o
4
18
5
17
6
7
16
15
3C,4C
8
14
30
:e(.)
9 1011 1213
NZZM(")
(!)
NC - No internal connection
logic symbol t
10 (1)
10
(31
20
INPUTS
OUTPUTS
0
C
Q
L
H
L
H
H
H
H
L
X
L
00
00
level, L
=
low level. X
10
10
(EACH LATCH)
= high
:J:
0 0 U Old
FUNCTION TABLE
H
CD
U
(TOP VIEWI
These latches are ideally suited for use as
temporary storage for binary information
between processing units and input/output or
indicator units. Information present at a data (0)
input is transferred to the Q output when the
enable (C) is high and the Q output will follow
the data input as long as the enable remains high,
When the enable goes low. the information (that
was present at the data input at the time the
transition occurred) is retained at the Q output
until the enable goes high.
The SN54HC375 is characterized for operation
over the full military temperature range of
-55 D C to 125 D C. The SN74HC375 is
characterized for operation from - 40 DC to
85 D C.
•
SN54HC375 ... FK PACKAGE
20
30
Q
=
30
40
40
irrelevant.
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
Pin numbers shown are for D. J and N packages.
PRODUCTION DATA documents contain information
currant as of publication date. Products conform to
specificatipns per the terms of Texas Instruments
:'~~~:~~i~ai~:I~~~ ~!:~~ti:r :,~O:::::i:~~S not
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright
© 1984, Texas Instruments Incorporated
2-427
SN54HC375. SN74HC375
4·BIT BISTABLE LATCHES
logic diagram (positive logic)
o
•
c
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee ................................................. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) .................................. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) .............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) ................................. ± 25 mA
Continuous current through Vee or GND pins ................................... ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ................ 300 De
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ................. 260 De
Storage temperature range .......................................... - 65 DC to 150 DC
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC375
MAX
MIN NOM
2
5
1.5
Vee Supply voltage
VIH
High·level input voltage
VIL
Low·level input voltage
Vee
Vee
vee
vee
Vee
Vee
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
VI
2-428
3.15
4.2
0
0
Vee - 2 V
Vee = 4.5 V
Vee
TA
=2v
= 4.5 v
=6v
=2V
= 4.5 v
=6V
=6
6
V
Operating free-air temperature
TEXAS
3.15
4.2
0.3
0.9
1.2
0
0
0
0
0
Vee
Vee
1000
500
0
-55
400
125
..If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74HC375
MIN NOM MAX
2
5
6
1.5
0
0
0
0
0
0
0
0
-40
UNIT
V
V
0.3
0.9
V
1.2
vee
Vee
1000
v
V
500
400
ns
85
·e
SN54HC375. SN74HC375
4-BI1 BISTABLE LATCHES
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TA - 2SOC
MIN
TYP MAX
vCC
SN54HC37S
MIN
MAX
SN74HC37S
MIN
MAX
UNIT
2V
1.9 1.998
1.9
1.9
VI
=
VIH or VIL. IOH
=
- 20 p.A
4.5 V
4.4 4.499
4.4
4.4
5.9
5.9
=
VIH or VIL. IOH
=
-4 mA
6V
4.5 V
5.9 5.999
VI
3.98
4.30
3.7
3.84
6V
5.48
2V
5.80
0.002
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1 ±100
±1000
±1000
nA
'S:
4
80
40
10
10
10
J.UO
co
3
2 1 20 19
18
17
16
15
14
9 1011 12 13
NC-No internal connection
PRODUCTION DATA documeats contain infor...tion
curr••t .1 of publication data. Products conlorm to
spacificatiDns per the terms of Taxas Instruments
=~i~ai:I~'li ~1::i:r
not
:.,0:::="
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
Copyright @ 1989. Texas Instruments Incorporated
2-431
SN54HC377. SN54HC379. SN74HC377. SN74HC379
OCTAL AND QUADD·TYPE FLlP·FLOPS WITH CLOCK ENABLE
SN54HC379 ... J PACKAGE
SN74HC379 ... O. J, OR N PACKAGE
(TOP VIEW)
III
::x::
(')
G
Vee
10
10
40
40
40
3D
30
30
20
20
20
SN54HC379 ... FK PACKAGE
(TOP VIEW)
3
18
5
17
16
elK
GNO
2 1 20 19
4
7
15
8
14
9 1011 12 13
'HC377 logic symbol t
:s:
NC - No internal connection
G
0
elK
CJ)
'HC377 logic diagram (positive logic)
(2)
10
20
C
CD
<
(5)
(6)
3D
C;'
(9)
40
CD
(12)
50
til
(15)
60
70
80
(16)
(18)
(19)
10
20
30
40
50
60
70
80
t This symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEe Publication 617·12.
Pin number. shown ara for OW, J, and N packages.
10 (3)
el
10
(2) 10
20'(4)
el
10
(5) 20
3D 171
el
10
(6) 30
40 (8)
Cl
10
(9) 40
50 (13)
el
10
(12) 50
60 (14)
Cl
10
(15) 60
70 (17)
10
(16) 70
80 (18)
el
10
(19) 80
FUNCTION TABLE
(EACH FLlP·FLOP)
INPUTS
G
OUTPUT
CLOCK DATA
a
H
x
X
00
l
l
t
H
H
t
l
L
X
L
X
00
H = high level, L = low level, X = irrelevant.
el
Pin numbers shown are for OW, J, and N packages.
2·432
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 .. DALLAS, TeXAS 75265
SN54HC378. SN54HC379. SN74HC378. SN74HC379
HEX AND QUAD D·TYPE FLlp·FLOPS WITH CLOCK ENABLE
'HC378 logic symbol t
'HC378 logic diagram (positive logic)
G
CLK
30
4D
50
60
(2)
20
10
20
(S)
10
20
(6)
(7)
(ll)
(10)
(l3)
(l2)
(l4)
(1S) 60
30
40
50
Cl
10 (3)
(EACH FLIP-FLOP)
INPUTS
20 (4)
(5) 20
II
X
00
H
H
L
L
L
X
L
X
00
30 (6)
10
40{lll
Cl
10
50 (l3)
Cl
10
Q)
(,)
'S
Q)
Cl
Q
X
t
t
L
Cl
10
OUTPUT
CLOCK OATA
H
(2) 10
U)
FUNCTION TABLE
G
10
(7) 30
C
(10) 40
0
(l2) 50
0
J:
CJ)
'HC379 logic symbol t
G
:E
Cl
60 (l4)
CLK
10
10
(lS) 60
'HC379 logic diagram (positive logic)
20
FUNCTION TABLE
(EACH FLIP-FLOP)
10 (4)
INPUTS
G
CLOCK OATA
Q
Q
X
00
00
H
H
L
L
L
L
H
X
L
X
00
00
L
(2) 10
(3) 10
OUTPUTS
X
t
t
H
Cl
10
Cl
20 (5)
10
Cl
3D (12)
tThese symbols are in accordance with ANSI/IEEE Std 91-1984
and lEe Publication 617-12.
40
(13)
10
Cl
10
(7) 20
(6) 20
(10) 30
~30
(lS) 40
(14) 40
Pin numbers are for 0, J, and N packages.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-433
SN54HC377, SN54HC378, SN54HC379
SN74HC377, SN74HC378, SN74HC379
OCTAL, HEX, AND QUAD D·TYPE FLlp·FLOPS WITH CLOCK ENABLE
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee .............. - . - ______ . . . . . . . . . . . . . . . . . .. ~ 0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 orVO > VCC .............................. ±20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuo.us current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D, DW, or N package ........... 260°C
Storage temperature range ......................................... - 65°C to 150°C
.w
_ _ _ t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
:t
C')
3:
otn
recommended operating conditions
C
SN74HC377
SN74HC378
SN54HC379
(1)
<
c;'
(1)
en
SN54HC377
SN54HC378
NOM
MAX
2
5
6
Vee Supply voltage
Vee
High·level input voltage
VIH
Vee
Vee
Vee
Vee
Low·level input voltage
VIL
vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
UNIT
SN74HC379
MIN
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
V
V
0
0.3
0
0.3
0
0.9
1.2
0.9
1.2
V
0
0
0
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
Vee
1000
0
Vee
1000
V
0
500
0
500
no
0
400
0
400
~55
125
~40
85
Vee
Input transition (rise and falll times
tt
Vee
Vee
=2V
= 4.5 V
=6V
0
Operating free-air temperature
TA
0
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
TA - 25°C
MIN
MAX
SN74HC377
SN74HC378
SN54HC379
SN74HC379
MIN
MAX
MIN
2V
1.9 1.998
1.9
1.9
VI
=
VIH or VIL,
10H
=
~20
p.A
4.5 V
4.4 4.499
4.4
4.4
VI
=
=
VIH or VIL,
10H
-4 mA
4.5 V
VIH or VIL,
10H
=
=
6V
VOH
VI
VI
=
VIH or VIL,
10L
~5.2
mA
= ·20 p.A
VOL
VI
VI
2-434
TYP
SN54HC377
SN54HC378
II
VI
lee
ei
VI
=
=
=
=
=4
VIH or VIL,
10L
VIH or VIL,
10L = 5.2 mA
Vee orO
Vee or 0, 10
=
0
mA
6V
5.9 5.999
5.9
5.9
4.30
3.7
3.84
3.98
5.48
5.80
5.2
UNIT
MAX
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
V
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
8
160
80
p.A
10
10
10
pF
6V
2 to 6 V
3
TEXAS ..,
INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54HC377, SN54HC378, SN74HC379
SN74HC377, SN74HC378, SN74HC379
OCTAL, HEX, AND QUAD D·TYPE FLlp·FLOPS WITH CLOCK ENABLE
timing requirements over recommended operating free· air temperature range (unless otherwise noted)
TA - 25 Q C
VCC
MIN
fclock
Clock frequency
Pulse duration, ClK high or low
tw
0
before ClKI
G high
or
low
th
Hold time
G inactive or
after ClKt
active, data
SN74HC371
SN54HC378
SN74HC378
SN54HC379
SN74HC379
MIN
MAX
MIN
2V
0
5
0
3
0
4
0
25
0
16
0
20
6V
0
29
0
19
0
23
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
100
150
125
4.5 V
30
25
25
6V
20
17
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
5
5
5
4.5 V
5
5
5
5
5
6V
UNIT
MAX
4.5 V
Set up time
tsu
MAX
SN54HC371
MHz
fI
ns
II)
G)
(.)
ns
21
'S:
G)
o
rn
o
ns
ns
:E
5
(J
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
TA - 2S Q C
VCC
(OUTPUT)
MIN
f max
tt
ClK
Any
Any
MAX
SN74HC371
SN54HC378
SN74HC378
SN54HC379
SN74HC379
MIN
MAX
MIN
2V
5
11
3
4
4.5 V
25
54
16
20
6V
29
64
19
23
2V
tpd
TYP
SN54HC371
MHz
56
15
160
240
32
48
200
40
6V
12
27
41
34
2V
38
75
110
95
4.5 V
8
15
22
19
6V
.6
13
19
16
No load, TA - 25°C
UNIT
MAX
4.5 V
Power dissipation capacitance
J:
ns
ns
30 pF typ
Note 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-435
E
J:
(")
s:
oCJ)
c
CD
~,
(')
CD
til
2-436
SN54HC386, SN74HC386
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
02684, DECEMBER 1982-REVISEO SEPTEMBER 1987
•
•
SN54HC386 ... J PACKAGE
SN74HC386 ... 0 OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
(TOP VIEW)
Vee
1A
18
1Y
2Y
2A
28
Dependable Texas Instruments Quality and
Reliability
description
These devices contain four independent 2-input
Exclusive-OR gates. They perform the Boolean
functions Y = A EB B = AB +
in positive
logic,
As
48
4A
4Y
3Y
38
3A
GND
(TOP VIEW)
A common application is as a true/complement
element, If one of the inputs is low. the other
input will be reproduced in true form at the
output. If one of the inputs is high. the signal on
the other input will be reproduced inverted at the
output.
U
al « U U a l
Z> VCC) , .......... , . . . . . . . . . . . . . . . . . . . .. ±20 rnA
Output clamp current. 10K (Va < 0 or Va > VCC ....... , , . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current. 10 (Va = 0 to VCC) ................ , ........ , ... , .. ± 25 mA
Continuous current through Vce or GND pins ......... , . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Lead temperature 1.6 mm (1/16 in) from case for 60 s: FK or J package ....... , ....... 300°C
Lead temperature 1.6 mm (1/16 in) from case for lOs: 0 or N package ............ ,.. 260°C
Storage temperature range , ............ , ....................... ,... - 65 °e to 1 50°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PRODUCTION DATA d.c.monu OGDtain information
current as of publication data. Products conform to
spaclficatiDns par the term. of Texa. Instruments
:':=i~ai:I':.'l.;
=:;11:; :'r;"':':~:'H not
Copyright © 1982, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-437
SN54HC386, SN74HC386
QUADRUPLE 2·INPUT EXCLUSIVE·OR GATE
recommended operating conditions
SN54HC386
"..~tN
2
Vee Supply voltage
Vee - 2 V
VIH
•
J:
n
s:
oen
c
CD
<
(;'
CD
High-level input voltage
Vee
=
4.5 V
Vee = 6 V
Vee - 2 V
VIL
Low-level input voltage
Vee
Vee
SN74HC386
I',:or.,
'V''''A
Mii,j
5
6
2
1.5
1.5
3.15
4.2
3.15
= 4.5 V
=6V
iliO;;;;
5
MAX
6
UNIT
V
V
4.2
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
V
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
Vee
1000
500
0
Vee
1000
V
0
500
ns
400
0
400
125
-40
85
Vee
Input transition (rise and fall) times
tt
Vee
Vee
=2V
= 4.5 V
=6V
0
0
0
Operating free-air temperature
TA
-55
0
°e
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
(II
2V
VI
=
VIH or VIL.
10H
=
-20
~A
VOH
VI
VI
VI
=
=
=
VIH or VIL.
10H
VIH or VIL.
10H
VIH or VIL.
10L
= -4 rnA
= -5.2 rnA
=
20 ~A
VOL
VI - VIH or VIL.
VI
II
lee
ei
=
VIH or VIL.
VI = Vee orO
VI - Vee or O.
10L
10L
= 4 rnA
= 5.2 rnA
TA - 25°C
TYP MAX
MIN
1.9
SN74HC386
MIN
1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
5.9 5.999
5.9
5.9
3.7
5.2
3.84
4.5 V
3.98
6V
5.48
4.30
5.80
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
6V
0.001
0.1
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
V
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1oo0
nA
2
40
20
~
10
10
10
pF
6V
10 - 0
SN54HC386
MIN MAX
2 to 6 V
3
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted!. CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
Vce
TA = 25°C
MIN
TYP MAX
2V
tpd
tt
A or B
Y
Y
SN74HC386
MIN MAX
40
100
150
125
4.5 V
12
20
30
25
6V
10
25
21
2V
28
110
95
4.5 V
6V
8
1775
15
13
22
19
19
Power dissipation capacitance per gate
6
No load. TA = 25°e
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2-438
SN54HC386
MIN MAX
TEXAS
"!I
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
16
35 pF typ
UNIT
ns
ns
SN54HC390, SN54HC393, SN74HC390, SN74HC393
DUAL 4·BIT DECADE AND BINARY COUNTERS
02684. DECEM8ER 1982 - REVISED JUNE 1989
•
'HC390 ... lndividual Clock for A and B FlipFlops Provide Dual + 2 and + 5 Counters
•
'HC393 ... Dual 4-Bit Binary Counter with
Individual Clocks
SN54HC390 .•• J PACKAGE
SN74HC390 ••• DI OR N PACKAGE
(TOPVIEW(
•
All Have Direct Clear for Each 4-Bit Counter
•
Dual 4-Bit Versions Can Significantly
Improve System Densities by Reducing
Counter Package Count by 50%
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
lCKA
lClR
lOA
lCKB
lOB
laC
10 0
VCC
2CKA
2ClR
20A
2CKB
20B
20C
20 0
GNO
SN54HC390 ... FK PACKAGE
(TOP VIEW}
a::«
...J ~
Dependable Texas Instruments Quality and
Reliability
description
Each of these monolithic circuits contains eight
flip-flops and additional gating to implement two
individual four-bit counters in a single package.
The 'HC390 incorporates dual divide-by-two and
divide-by-five counters, which can be used to
implement cycle lengths equal to any whole
and/or cumulative multiples of 2 and/or 5 up to
divide-by-100. When connected as a biquinary
counter, the separate divide-by-two circuit can
be used to provide symmetry (a square wave)
at the final output stage. The 'HC393 comprises
two independent four-bit binary counters each
having a clear and a clock input. N-bit binary
counters can be implemented with each package
providing the capability of divide-by-256. The
'HC390 and 'HC393 have parallel outputs from
each counter stage so that any submultiple of
the input count frequency is available for systemtiming signals.
The SN54HC390 and SN54HC393 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HC390 and SN74HC393 are characterized
for operation from - 40°C to 85 °C.
«
u~
u
u
u
Uu
3
2
1 2019
2>",
4
18
5
17
6
16
8
14
15
9 1011 12 13
00 U
0
U
02200
~t?
"''''
SN54HC393 ... J PACKAGE
SN74HC393 .•. N PACKAGE
(TOP VIEW}
lClK
lClR
lOA
lOB
lac
100
VCC
2ClK
2ClR
20A
20B
20C
20 0
GNO
SN54HC393 ... FK PACKAGE
(TOP VIEW}
3
2
1 20 19
18
t Contact the factory for 0 availability.
17
16
15
14
20B
9 10 11 12 13
00 U
0
U
02200
..... (,!)
NN
NC - No internal connection
PRODUCTION DATA do.uments .. ntai. information
currant .1 of publication dlta. Products conform to
spBCifioatio.. per the t.rms of T.... }nstrum.nts
=~~i~.{.;!~'1i =~~i:; :'l":.,,:::~:s not
Copyright @ 1989. Texas Instruments Incorporated
TEXAS . . ,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-439
SN54HC390, SN74HC390
DUAL 4·81T DECADE COUNTERS
logic diagram. each counter (positive logic)
logic symbol t
CLR----------~ J~------~--,
CKA-----------Q
(3)
(5)
OlV5 { o
CT
2
(6)
~--------~--~
lOA
laB
lac
CKB-------------e~~~
(7)
>-+---1>
lao
::::t
o
3:
ot/)
r---OC
(13)
cCD
{o
OlV5
<
c:r
CD
(11)
20A
20B
(10)
CT
20c
r--+-OO
(9)
2
en
20 0
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D. J, and N packages.
FUNCTION TABLES
BCD COUNT SEQUENCE
BIQUINARY (5-2)
(EACH COUNTER)
(EACH COUNTER)
(See Note AI
(See Note B)
COUNT
OUTPUT
QO
QC
QB
QA
a
L
L
L
L
1
2
3
4
5
6
7
8
9
L
L
L
H
L
L
L
H
L
L
H
L
L
H
H
L
H
L
H
L
H
H
L
COUNT
L
L
H
H
H
H
L
L
L
H
L
L
H
OUTPUT
QA
QO
QC
a
L
L
L
L
1
2
3
4
5
6
7
8
9
L
L
L
H
L
L
H
L
L
L
H
L
H
L
L
H
H
L
L
L
H
L
H
H
L
L
H'
H
L
H
H
H
H
L
L
Notes: A. Output QA is connected to input CKB for BCD count.
B. Output aD is connected to inpUt CKA for biquinary count.
H = high level, L = low level.
2·440
QB
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
L
SN54HC393, SN74HC393
DUAL 4·BIT BINARY COUNTERS
logic symbol t
logic diagram. each counter (positive logic)
,{
CTROIV16
lClR
lA
(Z)
(1)
CT=O
(3)
ClR
lOA
14)
las
ClK
(5)
lac
16)
100
fI
(11)
2ClR
112)
20A
(10)
ZOs
(9)
2A
en
Q)
20c
(8)
U
ZOo
'S;
Q)
t This
C
symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for J and N packages.
(I)
o
:!
1---°0
o
:r::
FUNCTION TASLE
COUNT SEQUENCE
(EACH COUNTER)
COUNT
OUTPUT
QD
Oc
Qa
0
l
L
L
L
1
L
L
L
H
2
L
L
H
l
3
L
L
H
H
4
L
H
L
L
5
L
H
H
l
H
QA
6
l
H
l
H
7
L
H
H
H
L
L
L
9
10
H
L
L
H
H
L
H
L
11
H
H
H
12
H
l
H
L
L
13
H
H
L
H
14
H
H
H
L
15
H
H
H
H
8
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·441
SN54HC39D, ·SN54HC393, SN74HC39D, SN74HC393
DUAL 4·BIT DECADE AND BINARY COUNTERS
absolute maximum ratings over operating free-air temperature range t
E
:r:
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package. . . . . . . . . . . . . . .. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(")
s:o
recommended operating conditions
SN54HC390
tn
C
(1)
<
Vee Supply voltage
(1)
VIH
Vee - 2 V
C::;'
en
SN74HC390
SN54HC393
High-level input voltage
Vee
Vee
Vee
VIL
Low-level input voltage
Vee
Vee
Vo
Input voltage
Output voltage
tt
Input transition (rise and falll times
VI
Vee
Vee
2·442
Operating free-air temperature
NOM
MAX
MIN
NOM
MAX
2
5
6
5
6
1.5
2
1.5
3.15
3.15
4.2
4.2
=2V
= 4.5 V
=6V
UNIT
V
V
0
0.3
0
0.3
0
0.9
0
0.9
0
0
1.2
0
1.2
V
Vee
0
Vee
V
0
Vee
1000
V
0
Vee
1000
0
500
0
500
ns
0
-55
400
0
-40
400
0
Vee
TA
= 4.5 V
=6V
=2V
= 4.5 V
=6V
SN74HC393
MIN
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 6550t2 • OAlLAS, TEXAS 75266
125
0
85
°e
SN54HC390. SN54HC393. SN74HC390. SN74HC393
DUAL 4·BIT DECADE AND BINARY COUNTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
TA - 25°C
MIN
~A
VI = VIH or VIL,
10H = -20
VI = VIH or VIL,
10H = -4 rnA
10H = -5.2 rnA
VOH
VI = VIH or VIL,
TYP
MAX
SN54HC390
SN74HC390
SN54HC393
SN74HC393
MIN
MAX
MIN
2V
1.9 1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
BV
5.9
5.999
5.9
5.9
4.5 V
3.98
4.30
3.7
3.84
6V
5.48
5.80
5.2
UNIT
MAX
V
5.34
2V
0.002
0.1
0.1
0.1
10L = 20 ~A
4.5 V
0.001
0.1
0.1
0.1
0.1
0.1
10L = 4 rnA
0.001
0.17
0.1
VI = VIH or VIL,
6V
4.5 V
0.26
0.4
0.33
VI = VIH or VIL,
10L = 5.2 rnA
6V
0.15
0.2B
0.4
0.33
±0.1
±100
±1000
±1000
nA
8
lBO
80
~A
10
10
10
pF
VI = VIH or VIL,
VOL
II
VI = VCC or 0
6V
ICC
VI = VCC or 0, 10 = 0
6V
2 to 6 V
Ci
3
U)
CD
V
CJ
'>CD
o
U)
o
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
CKA
fclock
Clock frequency
CK8
CKA high
or low
tw
Pulse duration
CKB high
or low
CLR high
tou
Setup time, CLR inactive
TA - 25°C
MIN
MAX
SN54HC390
SN74HC390
MIN
MAX
MIN
MAX
2V
0
6
0
4.2
0
5
4.5 V
0
31
0
20
0
25
6V
2V
0
36
0
28
6
0
25
4.2
0
0
0
5
4.5 V
0
31
0
20
0
25
BV
0
36
0
25
0
28
2V
80
120
100
4.5 V
16
24
20
6V
2V
14
80
20
18
120
100
4.5 V
16
24
20
BV
14
20
18
2V
80
120
100
4.5 V
16
24
20
6V
14
20
18
2V
4.5 V
25
25
25
5
5
5
BV
5
5
5
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
UNIT
:E
o
:J:
MHz
no
no
2-443
SN54HC390. SN74HC390
DUAL 4-BIT BINARY COUNTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(lNPUn
CKA
TO
(OUTPUn
QA
f max
::J:
CK8
Q8
tpd
CKA
QA
tpd
CKB
Q8
tpd
CK8
QC
tpd
CK8
QO
tPHL
CLR
Any
o
3:
o(I)
c
CD
<
n'
CD
(I)
tt
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25 DC
MIN
TVP MAX
10
6
31
50
36
60
6
10
31
50
36
60
50
120
16
24
13
20
58
130
18
26
15
22
83
185
26
37
21
32
60
130
18
26
14
22
45
165
17
33
14
28
28
75
15
8
13
6
No load, TA = 25°C
Power dissipation capacitance per counter
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2-444
TEXAS . "
INSTRUMENlS
POST OFFICE BOX. 655012 •
SN54HC390
MIN MAX
4.2
20
25
4.2
20
25
180
35
31
196
39
33
280
55
48
195
39
33
250
49
42
110
22
19
D~LLAS,
TeXAS 75265
SN74HC390
MIN MAX
5
25
28
5
25
28
150
35
26
165
33
28
230
46
40
160
33
28
205
41
35
95
19
16
40 pF typ
UNIT
MHz
ns
ns
ns
ns
ns
ns
SN54HC393, SN74HC393
DUAL 4-BIT BINARY COUNTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
ClK
ClK high
or low
Pulse duration
Iw
ClR high
Setup time, ClR inactive
Isu
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
0
6
0
31
0
36
80
16
14
80
16
14
25
5
5
SN54HC393
MIN MAX
0
4.2
0
21
0
25
120
24
20
120
24
20
25
5
5
SN74HC393
MIN MAX
0
5
0
25
0
28
100
20
18
100
20
18
25
5
5
UNIT
MHz
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
FROM
(lNPUTI
TO
(OUTPUTI
f max
ClK
OA
Ipd
ClK
QA
tpd
ClK
08
tpd
ClK
Oc
tpd
tpHl
II
ClK
ClR
OD
Any
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Power dissipation capacitance per counter
TA - 25°C
MIN
TYP MAX
10
6
31
50
36
60
50
120
15
24
13
20
190
72
22
38
18
32
240
91
28
48
22
41
100
290
32
58
24
50
45
165
17
33
14
28
28
75
15
8
13
6
No load. TA
=
SN54HC393
MIN MAX
4.2
21
25
180
36
31
285
57
48
360
72
61
430
87
74
250
49
42
110
22
19
25°C
SN74HC393
MIN MAX
5
25
28
150
30
26
240
47
40
300
60
51
360
72
62
205
41
35
95
19
16
UNIT
MHz
ns
ns
ns
ns
ns
ns
40 pF typ
Note 1: Load circuits and voltage waveforms are shown in Section 1.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-445
:x:
(')
s:
oen
c
CD
<
C:;'
CD
en
2-446
SN54HC490, SN74HC490
DUAL 4·81T DECADE COUNTERS
02684, DECEMBER 1982-REVISED JUNE 1989
SN54HC490 ... J PACKAGE
SN74HC490 ... N PACKAGE
•
Individual Clock. Direct Clear. and Set-to-9
Inputs for Each Decade Counter
•
Dual Counters Can Significantly Improve
System Densities as Package Count Can be
Reduced by 50%
(TOP VIEW)
•
Package Options Include Ceramic Chip
Carriers and Standard Plastic and Ceramic
300-mil DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
lClK
lClR
lOA
lSET9
lOB
10C
10 0
GNO
VCC
2ClK
2ClR
20A
2SET9
20B
20C
20 0
•
SN54HC490 ... FK PACKAGE
Each of these monolithic circuits contains eight
master-slave flip-flops and additional gating to
implement two individual 4-bit decade counters
in a single package, Each decade counter has
individual clock, clear. and set-to-9 inputs. BCD
count sequences of any length up to divideby- 100 may be implemented with a single
'HC490. The counters have parallel outputs from
each counter stage so that submUltiples of the
input count frequency are available for system
timing signals,
The SN54HC490 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC490 is
characterized for operation from - 40°C to
85°C.
(TOP VIEW)
U:-J
5:J
u u u Uu
~Z>N
3
lOA
lSET9
NC
lOB
10C
2
1 20 19
4
18
5
17
6
16
2ClR
20A
NC
2SET9
20B
15
14
8
9 1011 1213
00 U
0
U
OZZOO
~<.:l
"IN
NC-No internal connection
BCD COUNT SEQUENCE
(EACH COUNTER)
CLEAR/SET-TO-9
COUNT
FUNCTION TABLE
(EACH COUNTER)
INPUTS
CLEAR SET-TO-9
H
H
L
QA
L
QB
L
Qc
L
Qo
L
L
H
H
L
L
H
L
L
= high
level, L
0
1
2
3
4
5
6
7
8
OUTPUT
COUNT
= low level.
9
PRODUCTION DATA d.euments e....i. i.l.rmlti••
• urreot II .1 pubU..ti•• dlto. Preducts ••nform to
lpooifiolti... por tho terms 01 To..s 11III.. _ts
=:=i~8i~:,~li ~r:::~:i:r ~l"=;~:;:'•••t
OUTPUT
QO QC QB QA
L
L
L
L
H
L
L
L
L
L
H
L
L
L
H
L
L
H
L
H
H
H
H
H
l
H
L
L
L
H
L
L
H
L
L
L
H
L
H
H
Copyright @ 1989, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 '. DALLAS. TEXAS 75265
2-447
SN54HC490, SN74HC490
DUAL 4·81T DECADE COUNTERS
logic symbol t
CTROIV10
(3) 1QA
1ClR (2)
1SET9 (4)
CT=O
CT=9
0
CT{3
(5) 1QB
(6) 1QC
+
(7) 1Qo
(13) 2QA
2ClR (14)
(11)
2QB
(10) 2QC
2SETS (12)
%
o
3:
o
en
c
CD
<
5'
CD
en
(S) 2Qo
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for J and N packages.
logic diagram, each counter (positive logic)
SETS ---~
ClK
----<:»---+-+-----+-.,
>--+-+----+--~
I-H--Qo
2-448
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75265
SN54HC490, SN74HC490
DUAL 4·811 DECADE COUNTERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: N package . . . . . . . . . . . . . . . . . .. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not imptied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
I
recommended operating conditions
SN54HC490
MIN NOM MAX
5
6
2
1.5
Vee Supply voltage
VIH
Vll
High-level input voltage
Vee
Vee
Low-level input voltage
Vee
Vee
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
3.15
4.2
Input voltage
VI
Va
Output voltage
Vee
Vee
Input transition (rise and fall) times
tt
Vee
Operating free-air temperature
TA
NOM
MAX
5
6
3.15
4.2
0
0
0.3
0.9
0
0
1.2
0
0
Vee
Vee
1000
500
0
0
0
0
400
125
0
-40
0
0
0
0
-55
=2V
= 4.5 V
=6V
SN74HC490
MIN
2
1.5
UNIT
V
V
0
0.3
0.9
V
1.2
Vee
V
Vee
1000
500
400
V
85
ns
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDtnONS
VI
=
VIH or VIL,
10H
=
-20
VI
VI
=
=
VIH or VIL.
VIH or Vll,
IOH
IOH
=
=
-4 rnA
-5.2 rnA
VI
=
VIH or Vll,
10l
=
VI
VI
VI
=
=
=
VIH or VIL,
VIH or Vll,
Vee or 0
IOl
10l
= 4 rnA
= 5.2 rnA
~A
VOH
20 ~A
Val
II
lee
ej
VI - Vee or 0, 10
=0
SN54HC490
MIN MAX
SN74HC490
MIN MAX
VCC
TA - 25"C
MIN
TVP MAX
2V
4.5 V
1.9 1.998
4.4 4.499
1.9
4.4
1.9
4.4
6V
4.5V
6V
5.9 5.999
3.98
4.30
5.48
5.80
5.9
3.7
5.2
5.9
3.84
5.34
2V
4.5 V
6V
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5 V
BV
6V
0.17
0.15
±0.1
0.26
0.26
±100
0.4
0.4
±1000
0.33
0.33
±1000
3
8
10
160
10
80
10
6V
2 to 6 V
TEXAS •
INsrRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
V
V
nA
~A
pF
2-449
SN54HC490, SN74HC490
DUAL 4-81T DECADE COUNTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
•
fclock
Clock frequency
tw
Pulse duration, any input
Setup time. CLR or set-to-9 inactive
tsu
:::t
o3i:
o
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 2SOC
MIN
MAX
0
6
0
31
0
36
80
16
14
25
5
5
SNS4HC490
MIN MAX
0
4.2
0
21
0
25
120
24
20
25
5
5
SN74HC490
MIN MAX
0
5
0
25
0
28
100
20
UNIT
MHz
ns
17
25
5
5
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
tn
PARAMETER
o
<
n"
FROM
IINPUT)
TO
(OUTPUT)
(1)
f max
(1)
(n
tpd
tPLH
CLK
QA
CLK
Q8. QO
CLK
QC
Sel-Io-9
QA.QO
Sel-Io-9
QB. QC
Clear
Any
tpHL
tt
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
TYP MAX
6
31
36
Power dissipation capacitance per counter
50
15
12
80
23
18
100
30
23
60
19
16
54
18
16
50
17
15
28
8
6
125
25
21
185
37
31
235
47
40
185
37
31
140
28
24
130
26
22
75
15
13
No load. TA
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2-450
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC490
MIN MAX
4.2
21
25
190
38
32
280
56
48
355
71
60
280
56
48
210
42
36
195
39
33
110
22
19
= 25°C
SN74HC490
MIN MAX
5
25
28
155
31
26
230
46
39
295
59
50
230
46
39
175
35
30
165
33
28
95
19
16
'40 pF typ
UNIT
MHz
ns
ns
ns
SN54HC533, SN74HC533
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
02684, DECEMBER 1982-REVISEO SEPTEMBER 1987
SN54HC533 , , , J PACKAGE
SN74HC533 , .. DW OR N PACKAGE
•
8 Latches in e Single Package
•
High·Current 3-State Inverting Outputs Can
Drive Up to 15 LSTTL Loads
•
Full Parallel Access for Loading
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
ITOPVIEW,
Dependable Texas Instruments Quality and
Reliability
description
oe
Vee
10
10
20
20
30
3D
40
40
GNO
80
80
70
io
FI
60
60
50
50
U)
e
CD
()
SN54HC533 ... FK PACKAGE
These 8-bit latches feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads, They are
particularly suitable for implementing buffer
registers, 1/0 ports, bidirectional bus drivers, and
working registers.
CD
ITOPVIEW,
C
U
~1~lg ~Ig
3
The eight latches of the 'HC 533 are transparent
D-type latches. While the enable (C) is high, the
Q outputs will follow the complements of the D
inputs. When the enable is taken low, the Q
outputs will be latched at the inverses of the
levels that were set up at the 0 inputs. The
'HC533 is functionally equivalent to the 'HC373
except for having inverted outputs.
An output-control (OC) input can be used to
place the eight outputs in either a normal logic
state (high or low logic levels) or a highimpedance state, In the high-impedance state
the outputs neither load nor drive the bus lines
significantly. The high-impedance third state and
increased drive provide the capability to drive the
bus lines in a bus-organized system without need
for interface or pull-up components.
oS;
2
tJ)
o
1 2019
4
18
5
17
6
16
7
15
14
8
:E
80
70
70
60
60
(,J
:J:
9 1011 1213
IOoUIOO
q-z
(!)
"''''
FUNCTION TABLE lEACH LATCH,
INPUTS
OUTPUT
~
ENABLE C
D
Q
l
H
l
H
l
H
H
l
X
00
H
X
X
Z
l
l
The output control does not affect the internal
operation of the latches. Old data can be retained
or new data can be entered while the outputs
are off.
The SN54HC533 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC533 is
characterized for operation from - 40°C to
85°C,
PRODUCTION DATA documonts contain infarmation
current IS af publication data. Products conform to
.pacifications par the tarms of Taxas Instruments
:'~=~~~8i~~I~~i ~=::i:r :'~D=::9t:'~. not
Copyright © 1982, Texas Instruments Incorporated
TEXAS "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-451
SN54HC533, SN74HC533
OCTALD·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
logicsymbol t
10
20
3D
40
E
50
so
::c
g
::a
o(I)
logic diagram (positive logic)
10
20
30
40
50
70
60
70
80
so
10"';"'''';'''--+-i
141
20----I--t
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
c
CD
<
3D
171
181
40----I--t
Cr
CD
(/I
1131
50--'----I--t
1141
60----+--1
1171
70 ----+---t
1181
80-----t
2-452
TEXAS ."
INSTRUMENTS
POST OFfiCE BOX 655012 • DALLAS, TEXAS 75265
SN54HC533, SN74HC533
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current; 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package. . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package. . . . . . . . . . . . .. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability_
fI
recommended operating conditions
SN54HC533
MIN NOM MAX
vee Supply voltage
VIH
Vil
High-level input voltage
Vee
Vee
Low-level input voltage
Vee
Vee
Vee
Vee
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
Vee
Vee
Vee
TA
Operating free-air temperature
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
=
=
=
2 V
4.5 V
6 V
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-55
TEXAS . "
INSlRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
5
6
SN74HC533
MIN NOM MAX
2
5
6
1.5
3.15
4.2
UNIT
v
V
0.3
0
0.3
0.9
1.2
0
0.9
1.2
V
Vee
Vee
1000
500
400
V
V
Vee
Vee
1000
500
400
125
0
0
0
0
0
0
-40
85
n.
°e
2-453
SN54HC533, SN74HC533
OCTAL D·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
= -20 pA
VI
= VIH or VIL.
10H
VI
VI
= VIH or VIL.
= VIH or VIL.
10H - -6 mA
10H = -7.8 mA
VI
= VIH or VIL.
10L
VOH
:::t
s:
orn
c
CD
<
n'
CD
= 20 pA
VOL
o
II
10Z
lee
ej
TA - 25°C
MIN
TYP MAX
2V
1.9 1.998
4.5V
4.4 4.499
6V
5.9 5.999
4.30
4.5 V
3.98
6V
5.48
5.80
0.002
0.1
2V
0.001
0.1
4.5 V
6V
0.001
0.1
0.17
0.26
4.5 V
6V
0.15
0.26
±0.1 ±100
6V
6V
±0.01 ±0.5
6V
8
2 to 6 V
10
3
Vee
TEST CONDITIONS
VI = VIH or VIL. 10L = 6 mA
VI - VIH or VIL. 10L - 7.8 mA
VI = Vee or 0
Vo = Vee orO
VI = Vee or O. 10 = 0
tn
2-454
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC533
MIN MAX
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
±10
160
10
SN74HC533
MIN MAX
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
±5
80
10
UNIT
V
V
nA
~A
~A
pF
SN54HC533. SN74HC533
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
tw
Pulse duration, enable e high
tou
enable 0
th
Hold time, data after enable
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Setup time, data before
e~
TA
MIN
80
16
14
50
10
9
20
10
10
=
25°C
MAX
SN54HC533
MIN MAX
120
24
20
75
15
13
26
13
13
SN74HC533
MIN MAX
100
20
17
63
13
11
24
12
12
UNIT
ns
no
ns
•
rn
CD
CJ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
0
a
tpd
e
Any
a
ten
oe
Any
a
tdis
oe
Any
a
Any
a
tt
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5V
6V
2V
4.5V
6V
Power dissipation capacitance per latch
TA = 25°C
MIN
TYP MAX
77
150
26
30
23
26
87
175
27
35
23
30
150
68
24
30
21
26
47
150
23
30
21
26
28
60
12
8
6
10
No load, TA
=
SN54HC533
MIN MAX
225
45
38
265
53
45
225
45
38
225
45
38
90
18
15
25°e
SN74HC533
MIN MAX
185
38
32
220
44
38
190
38
32
190
38
32
75
15
13
UNIT
no
':;
CD
c
en
o
:E
o
l:
no
ns
ns
50 pF typ
Note 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-455
SN54HC533, SN14HC533
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
:::t:
FROM
(INPUT)
TO
(OUTPUT)
Ipd
D
0
tpd
C
Any
ten
OC
0
AnyO
n
s:o
It
en
c
AnyO
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25 G C
MIN
TYP MAX
95
200
40
33
21
34
103
225
45
33
29
38
85
200
29
40
28
34
60
210
17
42
14
38
Note 1: Load circuits and voltage waveforms are shown in Section 1.
CD
<
(i"
CD
(Il
2-456
TEXAS
l.!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC533
MIN MAX
300
60
51
335
67
57
300
60
51
315
63
53
SN74HC533
MIN MAX
250
50
43
280
56
48
250
50
43
265
53
45
UNIT
ns
ns
ns
ns
SN54HCT533. SN74HCT533
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
02804. MARCH 1984-REVISEO SEPTEMBER 1987
SN54HCT533 ... J PACKAGE
SN74HCT533 ... OW OR N PACKAGE
•
Inputs are TTL·Voltage Compatible
•
8 Latches in a Single Package
•
High·Current 3·State Inverting Outputs Can
Drive Up to 15 LSTTL Loads
(TOP VIEW)
•
Full Parallel Access for Loading
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
oe
Vee
10
10
20
20
30
30
40
40
80
80
70
70
60
60
50
50
U)
e
GNO
description
FI
CD
U
'>CD
SN54HCT533 ... FK PACKAGE
o
(TOP VIEW)
These 8-bit latches feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
CI)
U
o
OIOIU UIO
~~O>CXl
3
20
20
30
30
40
The eight latches of the 'HCT533 are
transparent Ootype latches. While the enable (C)
is high, the IT outputs will follow the
complements of the 0 inputs. When the enable
is taken low, the IT outputs will be latched at
the inverses of the levels that were set up at the
o inputs. The 'HCT533 is functionally equivalent
to the 'HCT373 except for having inverted
outputs.
2
:!:
1 2019
4
18
5
17
6
16
7
15
8
14
CJ
80
70
70
60
60
J:
9 1011 1213
IOOUIOO
' VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (VO < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC or GNO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ......... '.' . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package .............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HCT533
Vee Supply voltage
VIH High-level input voltage
Low-level input voltage
I Vee
"1 Vee
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
V
= 4.5 V to 5.5 V
2
v to 5.5 v
= 4.5
SN74HCT533
2
V
0.8
0
0.8
v
Vee
0
Vee
V
0
0
Vee
500
0
Vee
500
ns
-55
125
-40
85
°e
VIL
VI
Input voltage
0
0
Vo
Output voltage
0
tt
Input transition (rise and fall) times
TA
Operating free-air temperature
•
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
VOL
II
10Z
lee
.l.lee
TEST CONDITIONS
VCC
= VIH or VIL, 10H = -20 ~A
= VIH or VIL, 10H = -6 rnA
VI = VIH or VIL. 10H = 20 ~A
VI = VIH or VIL. 10L = 6 rnA
VI = Vee or 0
Vo = Vee or O. VI = VIH or VIL
VI = Vee or 0, 10 = 0
VI
4.5 V
VI
4.5V
4.5 V
One input at 0.5 V or 2.4 V
Other inputs at 0 V or Vee
TA - 25°C
MIN
TYP MAX
4.4 4.499
3.98
MIN
MAX
MIN
4.4
4.4
3.7
3.84
MAX
UNIT
V
4.30
0.001
0.1
0.1
0.1
4.5V
0.17
0.26
0.4
0.33
5.5 V
±0.1
±100
±1000
±1000
nA
5.5 V
±0.01
±0.5
±10
±5
~A
8
160
80
~A
1.4
2.4
3
2.9
rnA
3
10
10
10
pF
5.5 V
5.5 V
4.5 to
Ci
SN54HCT533 SN74HCT533
5.5 V
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V
2-459
SN54HCT533,. SN74HCT533
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
Vcc
•
::x::
n
3:
4.5 V
5.5 V
4.5 V .
tw
Pulse duration, enable C high
tsu
Setup time, data before
enable C~
th
Hold time, data after enable C+
5.5 V
4.5 V
5.5 V
TA = 25°C
MIN
MAX
20
17
10
SN54HCT533 SN74HCT533
MIN
30
27
MAX
5
MAX
UNIT
ns
23
13
12
5
15
14
5
5
9
5
MIN
25
ns
ns
5
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL
50 pF (see Note 1)
=
oC/)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
0
0
4.5 V
c
CD
tpd
C
Any
0
~.
ten
DC
Any
0
tdis
DC
Any
0
Any
0
<
(II
tt
VCC
TA = 25°C
TYP MAX
MIN
35
38
5.5 V
4.5 V
24
30
32
35
5.5 V
4.5 V
28
29
32
35
5.5 V
4.5 V
5.5 V
25
25
24
32
35
32
4.5 V
5.5 V
10
12
11
Power dissipation capacitance per latch
9
No load, TA
SN54HCT533 SN74HCT533
MIN
MAX
53
48
53
48
53
48
53
48
18
16
= 25°C
MIN
MAX
44
40
44
40
44
40
44
40
15
14
UNIT
ns
ns
ns
ns
ns
50 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
0
0
4.5 V
tpd
C
Any
0
ten
DC
Any
0
tt
Any
VCC
0
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
TA = 25°C
MIN
TYP MAX
52
36
47
32
40
38
35
29
18
16
52
47
52
47
42
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2-460
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
38
SN54HCT533 SN74HCT533
MIN MAX
MIN MAX
79
65
71
59
79
65
71
79
71
63
57
59
65
59
53
48
UNIT
ns
ns
ns
ns
SN54HC534, SN74HC534
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS
WITH 3·STATE OUTPUTS
DECEMBER 1982 - REVISED SEPTEMBER 1987
SN54HC534 ••• J PACKAGE
SN74HC534 •.. DW OR N PACKAGE
•
High-Current 3-State Inverting Outputs Can
Drive Up to 15 LSTTL Loads
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carrlars,
and Standard Plastic and Ceramic 300-Mil
DIPs
oc
Dependable Texas Instruments Quality and
Reliability
20
30
3D
40
40
GNO
(TOPVIEWI
•
Vee
BQ
BO
70
70
60
60
50
50
10
description
These 8-bit flip-flops feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly attractive for implementing buffer
registers, 1/0 ports, bidirectional bus drivers, and
working registers.
III
elK
SN54HC534 ••• FK PACKAGE
(TOPVIEWI
u
~~Ig ~Ifil
The eight flip-flops of the 'HC534 are edgetriggered D-type flip-flops. On the positive
transition of the clock, the Q outputs will be set
to the complement of the logic states that were
set up at the 0 inputs. The 'HC534 is
functionally equivalent to the 'HC374 except for
having inverted outputs.
3
2
1 20 19
4
18
5
17
6
16
7
15
8
14
9 1011 1213
An output-control (OC) input can be used to
place the eight outputs in either a normal logic
state (high or low logic levels) or a highimpedance state. In the high-impedance state
the outputs neither load nor drive the bus lines
significantly. The high-impedance third state and
increased drive provide the capability to drive the
bus lines in a bus-organized system without need
for interface or pull-up components.
FUNCTION TABLE (EACH FLiP-FlOPI
oc
L
L
The output control does not affect the internal
operation of the flip-flops. Old data can be
retained or new data can be entered while the
outputs are off.
OUTPUT
INPUTS
ClK
D
Q
t
t
H
L
H
L
L
L
X
00
H
X
X
Z
The SN54HC534 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC534 is
characterized for operation from - 40°C to
85°C.
PRODUCTION DATA docu ..o... contain Information
Clrrant as of publication d.... Predacts CDRfarm to
opacificatlons per tho ta,.,. of T.... Instrume...
standard warranty. Productian p'rDC8Sling daBS Rot
nle...arily includa tasting of all paramata,s..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright @ 1982, Texas Instruments Incorpor8te~
2-461
SN54HC534, SN74HC534
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS
WITH 3·STATE OUTPUTS
logic symbol t
10 (31
20 (41
30 171
40 (81
50 (131
::t
60 (141
3l:
8D (181
o
7D (171
o
f/)
C
~(i.
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
logic diagram (positive logic)
C
(I)
20 141
3D 171
40 181
50 1131
60 1141
70 1171
118)
80 -'--'----I
Pin numbers shown are for OW, J, and N packages.
2-462
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC534, SN74HC534
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS
WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature range t
Supply voltage, VCC " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±35 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package .............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
oS;
SN54HC534
MIN NOM MAX
Vee Supplv voltage
High-level input voltage
Vee
Vee
Vee
VIL
Low-level input voltage
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
Vee
Vee
Vee
Vee
Vee
Vee
TA
II)
CD
CJ
recommended operating conditions
VIH
•
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Operating free-air temperature
TEXAS
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-55
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
5
6
0.3
0.9
1.2
Vee
Vee
1000
500
400
125
SN74HC534
MIN NOM MAX
2
1.5
3.15
4.2
5
6
0.3
0
0
0
0.9
0
-40
V
V
0
0
0
0
UNIT
CD
C
CI)
o
:liE
o
V
:::E:
1.2
Vee
Vee
1000
500
400
85
V
V
ns
°e
2-463
SN54HC534, SN74HC534
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS
WITH 3·STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range {unless otherwise
noted)
PARAMETER
•
VOL
o(I)
II
IOZ
ICC
Ci
n
3:
c
CD
<
VCC
VI = VIH or VIL.
IOH = -20 p.A
VI = VIH or VIL.
VI - VIH or VIL.
IOH = -SmA
IOH - -7.8 rnA
VI = VIH or VIL.
IOL = 20 p.A
VI = VIH or VIL.
VI = VIH or VIL.
VI = VCC or 0
Vo = Vce or O.
VI = VCC orO.
IOL=SmA
10L = 7.8 rnA
VOH
:::t:
(;'
CD
TEST CONDITIONS
VI = VIH or VIL
10 = 0
2V
4.5 V
SV
4.5 V
SV
2V
4.5V
6V
4.5 V
6V
SV
SV
SV
2 to 6 V
TA - 2SoC
TYP MAX
MIN
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.48
5.80
0.002
0.1
0.001
0.1
0.001
0.1
0.17
0.2S
0.15
0.26
±0.1 ±loo
±0.01 ±0.5
8
10
3
SN54HCS34
MIN MAX
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±10oo
±10
ISO
10
SN74HCS34
MIN MAX
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±10oo
±5
80
10
UNIT
V
V
nA
p.A
~A
pF
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
(II
VCC
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time. data before CLKt
th
2-464
I
CLK high or low
Hold time. data after CLKt
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 2SoC
MAX
MIN
0
6
31
0
0
36
80
16
14
100
20
17
5
5
5
TEXAS
..II
'NSTRUMENlS
POST OFFICE BOX 666012 • DALLAS, TEXAS 76265
SN54HCS34
MIN MAX·
0
0
0
120
24
20
150
30
26
5
5
5
4.2
21
25
SN74HCS34
MIN MAX
0
5
0
25
29
0
100
20
17
125
25
21
5
5
5
UNIT
MHz
ns
ns
ns
SN54HC534. SN74HC534
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS
WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TA = 2SoC
TO
vCC
IOUTPUT)
MIN
TYP
6
11
2V
f max
tpd
ten
ClK
~
Any
Any
0
0
Any
0
5
36
21
25
40
25
29
UNIT
MAX
MHz
2V
88
180
270
4.5 V
28
36
54
45
6V
24
31
46
38
2V
77
26
23
51
25
23
28
8
6
150
225
190
30
45
38
26
38
32
150
225
190
30
45
38
26
38
32
60
90
75
12
18
15
10
15
13
::E
100 pF typ
::J:
4.5 V
4.5 V
0
MIN
4.2
31
2V
Any
SN74HCS34
36
BV
tt
MAX
6V
2V
OC
MIN
4.5 V
6V
tdis
SN54HC534
MAX
4.5 V
6V
225
fI
ns
ns
U)
CD
(,)
'S
ns
CD
o
CI)
o
ns
(.)
Power dissipation per flip-flop
No load, TA
= 25°C
NOTE 1: load circuit and voltage waveforms are shown in Section 1.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
tpd
ClK
ten
tt
QC
TO
IOUTPUT)
Any
Any
Any
0
0
a
VCC
TA - 2Soc
TYP MAX
MIN
SNS4HCS34
MIN
MAX
SN74HCS34
MIN
MAX
2V
105
230
345
4.5 V
35
46
69
58
6V
31
39
200
58
49
300
250
2V
95
4.5 V
32
6V
UNIT
290
60
50
29
40
34
51
43
265
2V
60
210
315
4.5 V
17
42
63
53
6V
14
36
53
45
ns
ns
ns
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265
2-465
E
:::J:
(')
3i:
ot/)
c
CD
<
0'
CD
rn
2-466
SN54HCT534. SN74HCT534
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS
WITH 3·STATE OUTPUTS
02804. MARCH 1984-REVISEO SEPTEMBER 1987
•
Inputs are TTL-Voltage Compatible
•
High-Current 3-State Inverting Outputs Can
Drive Up to 15 LSTTL Loads
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-Mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HCT534 ••• J PACKAGE
SN74HCT534 ... OW OR N PACKAGE
(TOP VIEW)
description
These 8-bit flip-flops feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly attractive for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the 'HCT534 are edgetriggered D-type flip-flops. On the positive
transition of the clock, the Q outputs will be set
to the complement of the logic states that were
set up at the D inputs. The 'HCT534 is
functionally equivalent to the 'HCT374 except
for having inverted outputs.
An output-control (DC) input can be used to
place the eight outputs in either a normal logic
state (high or low logic levels) or a highimpedance state. In the high-impedance state
the outputs neither load nor drive the bus lines
significantly.
DC
Vee
10
10
20
20
30
3D
40
40
80
80
70
70
60
60
50
50
•
ClK
GNO
SN54HCT534 •.. FK PACKAGE
(TOP VIEW)
U
~1~lg ~I~
3
20
3D
40
2
1 2019
4
18
5
17
6
16
7
15
8
14
FUNCTION TABLE (EACH FLIP-FLOP)
The output control does not affect the internal
operation of the flip-flops. Old data can be
retained or new data can be entered while the
outputs are off.
(j(!
INPUTS
ClK
0
OUTPUT
Q
t
t
H
l
H
l
l
X
00
H
X
X
Z
l
l
l
The SN54HCT534 is characterized for operation
over the full military temperature range of
- 55 DC to 125 DC. The SN74HCT534 is
characterized for operation from - 40 DC to
85 D C.
PRODUCTION DATA d.cum••ls c.ntain inlarmatio.
currant 81 of pllblication data. Products cDnform ta
specifications par the tums af Taxas Instruments
::=~~i;.[::r.'li ~=::i:; ~\o:::,.:~~~
not
Copyright @ 1984, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-467
SN54HCT534. SN74HCT534
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS
WITH 3·STATE OUTPUTS
logic symboJt
10 (31
20 (41
•
3D (71
40 (81
5D (131
60 (141
::r::
n
70 (171
s:
80 \181
o(f)
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
C
logic diagram (positive logic)
CD
<
(;'
CD
en
20..:(..:,;41_-+-1
3D 171
40 (81
50 (131
60 (141
70 (171
80...;1_18...;,1_--1
2-468
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HCT534, SN74HCT534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through Vee or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1.6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead Temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package ............. 260°C
Storage temperature range ......................................... - 65°C to 1 50°C
:C:Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
•
U)
Q)
CJ
"S:
recommended operating conditions
Q)
SN54HCT534
vee Supply voltage
VIH High-level input voltage
I Vee
I Vee
SN74HCT534
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
= 4.5 V to 5.5 V
2
= 4.5 V to 5.5 V
Low-level input voltage
0
0.8
0
0.8
V
Input voltage
0
Vee
0
Vee
V
0
Vee
500
0
0
Vee
500
ns
125
-40
85
°e
Output voltage
Input transition (rise and fall) times
TA
Operating free-air temperature
0
-55
o
V
VI
Vo
en
V
2
VIL
tt
Q
UNIT
:!!
o
~
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
TA - 25°C
MIN
TYP MAX
SN54HCT534 SN74HCT534
MIN
MAX
MIN
MAX
UNIT
VI = VIH or VIL, 10H = -20 ~A
4.5 V
VI - VIH or VIL. 10H - -6 rnA
VI - VIH or VIL, 10H - 20 ~A
VI = VIH or VIL, IOL=6rnA
4.5 V
4.5 V
0.17
0.26
0.4
0.33
II
VI - Vee orO
5.5 V
±0.1
±100
±1000
±1000
nA
10Z
Vo = Vee or O. VI = VIH or VIL
VI = Vee or 0, 10 = 0
One input at 0.5 V or 2.4 V
5.5 V
±0.01
±0.5
±10
±5
p.A
5.5 V
8
160
80
p.A
1.4
2.4
3
2.9
rnA
3
10
10
10
pF
VOH
VOL
lee
Alee t
ei
Other inputs at 0 V or Vee
4.5 V
4.4 4.499
3.98
5.5 V
4.4
4.30
0.001
4.5 to 5.5 V
4.4
3.7
0.1
V
3.84
0.1
0.1
V
t This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or Vee.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-469
SN54HCT534. SN74HCT534
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS
WITH 3·STATE OUTPUTS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
VCC
Clock frequency
fclock
•
l:
(')
3!:
I
tw
Pulse duration
CLK high or low
tsu
Setup time, data before CLKt
Hold time, data after CLKt
th
TA - 2SOC
MAX
MIN
SNS4HCTS34 SN74HCTS34
MIN
MAX
MIN
MAX
4.5 V
0
31
0
21
0
25
5.5 V
0
36
0
23
0
28
4.5 V
16
24
20
5.5 V
14
22
18
4.5 V
20
30
25
5.5 V
17
27
23
4.5 V
5
5
5
5
5
5.5 V
UNIT
MHz
ns
ns
ns
5
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
oen
PARAMETER
c
FROM
(INPUT)
TO
IOUTPUT)
f max
CD
<
r;"
tpd
CLK
AnyQ
ten
~
AnyQ
CD
en
tdis
~
tt
Any
0
Any
0
VCC
TA - 25°C
TYP MAX
MIN
SN54HCT534 SN74HCT534
MIN
4.5 V
31
36
21
5.5 V
36
40
23
4.5 V
28
5.5 V
MAX
MIN
MAX
25
MHz
28
48
45
26
36
32
43
41
4.5 V
24
30
45
37
5.5 V
20
27
41
33
4.5 V
22
30
45
37
5.5 V
20
27
41
33
4.5 V
10
5.5 V
9
12
11
18
16
15
14
Power dissipation capacitance per flip-flop
UNIT
ns
ns
ns
ns
93 pF typ
No load, TA = 25°C
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
CLK
AnyQ
ten
OC
AnyQ
tt
AnyQ
VCC
TA - 25°C
MIN
TYP MAX
MIN
MAX
MIN
MAX
4.5 V
38
46
69
57
5.5 V
36
41
62
51
4.5 V
30
40
60
50
5.5 V
4.5 V
27
18
36
42
54
45
63
53
5.5 V
16
38
57
48
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-470
SN54HCT534 SN74HCT534
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
ns
ns
ns
SN54HC540, SN54HC541
SN74HC540, SN74HC541
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
02804, MARCH 1984-REVISED JUNE 1989
•
High·Current 3-State Outputs Drive Bus
Lines Directly or Up to 15 LSTTL Loads
•
Data Flow-Thru Pinout (All Inputs on
Opposite Side from Outputs)
SN54HC540, SN54HC541 ... J PACKAGE
SN74HC540, SN74HC541 ... OW OR N PACKAGE
ITOP VIEWI
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
Vee
Gl
Al
A2
A3
A4
A5
A6
A7
A8
GND
description
These octal buffers and line drivers are designed
to have the performance of the popular
SN54HC240/SN74HC240 series and, at the
same time, offer a pinout with inputs and
outputs on opposite sides of the package, This
arrangement greatly enhances printed circuit
board layout.
G2
Yl
Y2
Y3
Y4
Y5
Y6
Y7
Y8
II
CI)
Q)
(.)
os
SN54HC540, SN54HC541 ... FK PACKAGE
The three-state control gate is a 2-input NOR.
If either G 1 or G2 is high, all eight outputs are
in the high-impedance state,
The 'HC540 provides inverted data and the
'HC541 provides true data at the outputs,
Q)
C
(TOP VIEWI
U
UN
tn
1 20 19
:2E
"1..-.-
o
1t9
3
A3
A4
A5
A6
A7
2
4
18
5
17
6
16
15
14
(,)
::I:
Y3
Y4
Y5
9 10 11 12 13
The SN54HC540 and SN54HC541 are
characterized for operation over the full military
temperature range of - 55°C to 125°C, The
SN74HC540 and SN74HC541 are characterized
for operation from - 40°C to 85°C.
'HC540
'HC541
FUNCTION TABLE
FUNCTION TABLE
INPUTS
OUTPUT
INPUTS
OUTPUT
Y
Gl
G2
A
Y
Gl
G2
A
L
L
L
H
L
L
L
L
L
L
H
L
L
L
H
H
H
X
Z
Z
X
H
X
X
H
X
X
H
X
X
Z
Z
z
~
.z
High Impedance
:=:~~i~a{::1~7~ ~::i:~ti:f :.~o;::::.::.~
not
High Impedance
Copyright © 1989, Texas Instruments Incorporated
PRODUCTION DATA documents contain information
currant as of publication dats. Products conform to
specifications par the terms of Taxas Instruments
~
.
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-471
SN54HC540, SN54HC541
SN74HC540, SN74HC541
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
logic symbols t
'HC540
•
II
'HC541
EN
Al (21
Al
A2 (31
A2
A3 141
A3
A4 15)
A4
AS (6)
::E:
A5
(')
A6 (7)
A6
3:
IBI
A7
A8 191
A8
oen
c
A7
11BI Yl
1171 Y2
(4)
1161 Y3
151
115) Y4
161
(14) Y5
171
1131 Y6
181
1121 Y7
191
1111 Y8
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
CD
<
5'
logic diagrams (positive logic)
CD
ih
OZ
(II
ih
liz
(I)
(191
(191
(ZI
Yl
Al
(2)
(1BI
(1BI
(171
Y2
A2 (3)
(171
A2 (31
(IBI
A3
(41
(IB)
A3 (41
A4 (51
(151
A4 (51
(151
A5 (BI
(141
A5 (61
(141
(131
AB (71
(131
AB 171
A7 (BI
(12)
(B)
(121
AB (91
(I I)
(91
(111
Al
2-472
'HC541
'HC540
(I)
Y3
Y4
Y5
Y6
Y7
A7
YB
AB
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DA1.LAS, TEXAS 75265
Yl
Y2
Y3
Y4
Y5
Y6
Y7
YB
SN54HC540. SN54HC541
SN74HC540. SN74HC541
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±35 mA
Continuous current through Vee or GNO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package .............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC540
SN74HC540
SN54HC541
Vee Supply voltage
VIH
Vee
Vee
High·level input voltage
Vee
Vee
Low·level input voltage
VIL
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
SN74HC541
MIN
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
0
1.2
V
Vee
1000
V
0
500
n.
0
400
-40
85
0
Vee
Output voltage
0
Vee
1000
0
0
500
0
-55
400
125
Input transition (rise and fall) times
tt
Vee
Vee
= 4.5 V
=6V
Operating free-sir temperature
TA
V
Vee
Input voltage
Vo
0
V
V
0
VI
Vee - 2 V
UNIT
0
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
Vee
TEST CONDITIONS
TA - 25°C
MIN
2V
VI
=
VIH or VIL.
=
IOH
-20
~A
4.5 V
VOH
VI
VI
=
=
VIH or VIL,
IOH
VIH or VIL.
IOH
=
=
-6 rnA
-7.8 rnA
TYP
1.998
MAX
1.9
4.4 4.499
MAX
4.4
MIN
1.9
5.9
5.9
4.5 V
3.98
4.30
3.7
3.84
6V
5.48
5.80
5.2
V
5.34
0.002
0.1
0.1
0.1
0.001
0.1
0.1
0.1
0.1
0.4
0.33
VIH or VIL.
IOL
=
20 ~A
4.~
V
6V
0.001
0.1
0.1
VI
=
=
VIH or VIL.
IOL
6 rnA
4.5 V
0.17
0.26
IOL
II
VI
VIH or VIL.
VI - Vee or 0
=
=
IOZ
Vo
lee
e·
VI
UNIT
MAX
4.4
5.999
=
= Vee or 0
= Vee or O. 10 = 0
SN74HC541
MIN
1.9
5.9
VI
7.8 rnA
SN74HC540
SN54HC541
6V
2V
VOL
SN54HC540
V
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
6V
±0.01
±0.5
±10
±5
160
80
3
8
10
10
10
pA
pA
pF
6V
2 to 6 V
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-473
SN54HC540. SN74HC540
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
'HC540 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted). CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA = 25°C
MIN
TYP MAX
SN54HC540
2V
tpd
•
ten
:r:
tdis
o
~
o
A
Y
G
Y
G
Y
Y
tt
en
C
<
(;'
CD
en
MAX
SN74HC540
MIN
MAX
149
125
4.5V
35
10
100
20
30
6V
2V
8
75
17
25
. 21
150
25
224
4.5V
15
30
45
38
6V
13
26
38
32
2V
40
150
224
188
18
30
45
38
6V
17
26
32
75
2V
28
60
38
90
4.5 V
8
12
18
15
6V
6
10
15
13
No load, TA
=
UNIT
ns
188
4.5 V
Power dissipation capacitance
CD
MIN
25°C
ns
ns
ns
35 pF typ
'HC540 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted). CL = 150 pF (see Note 1)
PARAMETER
tpd
ten
tt
FROM
(INPUT)
A
G
TO
(OUTPUT)
Y
Y
Y
VCC
TA = 25°C
MIN
TYP MAX
MIN
MAX
SN74HC540
MIN
MAX
2V
4.5 V
60
150
224
15
30
45
188
38
6V
13
26
32
250
2V
100
200
38
298
4.5 V
20
40
60
50
6V
17
34
51
43
2V
4.5 V
45
17
210
42
315
265
63
53
6V
13
36
53
45
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2-474
SN54HC540
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
ns
ns
ns
SN54HC541. SN74HC541
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
'HC541 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
G
y
tdis
G
y
Y
tt
vcc
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25"C
MIN
TYP MAX
115
40
12
23
10
20
80
150
17
30
15
26
40
150
18
30
17
26
28
60
8
12
6
10
No load. TA
Power dissipation capacitance
=
SN54HC541
MIN MAX
171
34
29
224
45
38
224
45
38
90
18
15
25"C
SN74HC541
MIN MAX
144
29
25
188
38
32
188
38
32
75
15
13
UNIT
ns
II
ns
o
ns
CD
(,)
.S;
ns
CD
c
en
35 pF typ
o
'HC541 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
G
y
tt
Y
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25"C
MIN
TYP MAX
65
165
16
33
14
28
100
200
20
40
34
17
45
210
42
17
13
36
SN54HC541
MIN MAX
246
49
42
298
60
51
315
63
53
SN74HC541
MIN MAX
206
41
35
250
50
43
265
53
45
::iE
(.)
::E:
UNIT
ns
ns
ns
Note 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-475
IE
J:
o
s:
oen
c
(1)
<
c;"
(1)
en
2-476
SN54HCT540, SN54HCT541
SN74HCT540, SN74HCT541
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
02804. MARCH 1984- REVISED JUNE 1989
SN54HCT540. SN54HCT541 ... J PACKAGE
SN74HCT540. SN74HCT541 ... ow OR N PACKAGE
•
Inputs are TTL-Voltage Compatible
•
High-Current 3·State Outputs Interface
Directly with System Bus or Can Drive Up
to 15 LSTTL Loads
•
Data Flow·Thru Pinout (All Inputs on
Opposite Side from Outputs)
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
(TOP VIEWI
Vee
(;1
Al
(;2
A2
A3
Yl
Y2
Y3
Y4
Y5
Y6
Y7
A7
AS
Dependable Texas Instruments Quality and
Reliability
II
II)
GND ......_ _J - " YS
G)
CJ
"S
SN54HCT540. SN54HCT541 ... FK PACKAGE
description
G)
c
en
(TOP VIEW)
These octal buffers and line drivers are designed
to have the performance of the popular
SN54HCT240/SN74HCT240 series and, at the
same time, offer a pinout with inputs and
outputs on opposite sides of the package. This
arrangement greatly enhances printed circuit
board layout.
The three-state control gate is a 2-input NOR.
If either G 1 or G2 is high, all eight outputs are
in the high-impedance state.
N . - .....
U
UN
o
« «ICl >ICl
3
A4
A5
A6
A7
2
~
1 20 19
5
17
6
16
7
8
14
CJ
J:
Y1
Y2
Y3
Y4
Y5
9 1011 1213
CXlCl CXl ..... co
«z>->->-
The 'HCT540 provides inverted data and the
'HCT541 provides true data at the outputs.
Cl
The SN54HCT540 and SN54HCT541 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HCT540
and
SN74HCT541
are
characterized for operation from -40°C to 85°C.
'HCT540
'HCT541
FUNCTION TABLE
FUNCTION TABLE
INPUTS
OUTPUT
INPUTS
OUTPUT
G1
G2
A
Y
01
G2
A
L
L
L
H
L
L
L
Y
L
L
L
H
L
L
L
H
H
H
X
X
H
X
X
X
H
X
Z
Z
X
H
X
Z
Z
Z = High Impedance
Z = High Impedance
PRODUCTION DATA documonllconlli. inlar.llion
currant 81 af publication date. Praductl confom to
spoclflcalionl per tho to....., TO'1l InllrUmonll
=~~r,"{,::::.r.; =i; :.r:."::::':"~ n.t
Copyright @ 1989, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-477
SN54HCT540. SN54HCT541. SN74HCT540. SN74HCT541
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
logic symbols t
'HCT541
'HCT540
&
EN
IJ
J:
A4
:s:
ot/)
AS
A3
15)
A4
16)
A5
17)
A6
18)
A7
A8 19)
A7
A8
14)
116) V3
15)
115) V4
16)
114) V5
17)
113) V6
18)
112) V7
19)
111) V8
<
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
CD
logic diagrams (positive logic)
S'
en
'HCT540
A1
2-478
'HCT541
(1 )
(19)
01
02
(2)
118) Vl
117) V2
A2
14)
A6
\l
Al
13)
A3
(")
cCD
12)
Al
A2
(1)
(19)
il1
02
(18)
A2 (3)
(17)
A3 (4)
(16)
A4 (5)
(1S)
A5 (6)
(14)
A6 (7)
(13)
A7 18)
(12)
AB (9)
(11)
(2)
(1B)
V1
A1
V2
A2
(3)
(17)
V3
A3
(4)
(16)
V4
A4
(5)
(15)
V5
A5 (8)
(14)
V8
A6
(7)
(13)
V7
(B)
A7
(12)
V8
(9)
AB
(11)
TEXAS .. "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V1
V2
V3
V4
V5
V8
V7
VB
SN54HCT540, SN54HCT541
SN74HCT540, SN74HCT541
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (Vo = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±35 mA
Continuous current through VCC or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300 DC
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package .............. 260 DC
Storage temperature range ......................................... - 65 DC to 150 DC
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
fI
U)
CD
U
recommended operating conditions
'S;
SN54HCT540
SN54HCT541
Vee Supply voltage
VIH High·level input voltage
Vil
VI
I Vee
I Vee
CD
UNIT
c
V
o
SN74HCT540
SN74HCT541
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
2
en
:!
= 4.5 V to 5.5 V
2
= 4.5 V to 5.5 V
0
0.8
0
0.8
V
(.)
Input voltage
0
Vee
0
V
l:
0
Vee
500
0
Vee
Vee
500
ns
85
°e
low-level input voltage
Vo
Output voltage
tt
Input transition (rise and fall) times
TA
Operating free-air temperature
0
-55
125
V
0
-40
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
VOH
VOL
II
10l
lee
~Iee
ei
-20 ~A
4.5 V
= VIH or Vil. 10H = -6 rnA
VI = VIH or Vil. 10l = 20 ~A
VI = VIH or Vil. 10l = 6 rnA
VI = Vee or 0
Vo = Vee or O. VI = VIH or Vil
VI = Vee or O. 10 = 0
4.5 V
VI - VIH or Vil.
10H -
VI
One input at 0.5 V or 2.4 V
Other inputs at 0 V or Vee
SN54HCT540 SN74HCT540
TA - 25°C
VCC
TYP
SN54HCT541
MAX
4.4 4.499
3.98
4.30
MIN
MAX
SN74HCT541
MIN
4.4
4.4
3.7
3.84
UNIT
MAX
V
4.5 V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
5.5 V
±0.1
±100
±1000
±1000
5.5 V
±0.01
±0.5
±10
±5
~A
8
160
80
p.A
1.4
2.4
3
2.9
rnA
3
10
10
10
pF
5.5 V
5.5 V
4.5 to
5.5 V
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V
nA
2-479
.SN54HCT540, SN74HCT540
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
'HCT540 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
len
~is
FROM
(INPUT)
A
~
~
Y
4.5V
5.5 V
20
18
4.5V
5.5 V
4.5V
19
18
5.5
TA = 25°C
TYP MAX
MIN
13
20
12
18
SN54HCT640 SN74HCT540
MIN MAX
MIN MAX
30
27
45
41
45
41
30
27
30
27
12
8
7
V
Power dissipation capacitance
3:
C
Y
4.5V
5.5 V
Y
n
otn
Vee
Y
tt
::t
TO
IOUTPUT)
18
16
11
UNIT
25
23
ns
38
34
ns
38
34
15
14
ns
ns
35 pF typ
No load, TA = 25°C
'HCT540 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 150 pF (see Note 1)
CD
<
(;'
CD
(I)
PARAMETER
FROM
(INPUT)
TO
IOUTPUT)
tpd
A
Y
ten
tt
~
Y
Y
Vee
4.5 V
TA = 25°C
TYP MAX
MIN
20
30
5.5 V
4.5 V
5.5 V
19
26
25
4.5 V
5.5 V
17
14
27
40
36
42
38
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2-480
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HCT540 SN74HCT540
MIN MAX
MIN MAX
45
38
41
34
60
54
63
57
50
45
53
48
UNIT
ns
ns
ns
SN54HCT541, SN74HCT541
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
'HCT541 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted). CL
50 pF (see Note 1)
=
PARAMETER
FROM
TO
IINPUTI
(OUTPUT!
tpd
A
Y
ten
(l"
Y
tdis
G
Y
Y
tt
VCC
TA = 25°C
TYP MAX
MIN
SN54HCT541
MIN
MAX
SN74HCT541
MIN
MAX
4.5 V
13
23
34
29
5.5 V
12
21
26
4.5 V
21
30
31
45
5.5 V
19
27
41
34
4.5 V
19
30
45
38
5.5 V
18
27
41
4.5 V
8
12
18
34
15
5.5 V
7
11
16
14
38
UNIT
ns
ns
fI
ns
ns
en
CI)
Power dissipation capacitance
u
35 pF typ
No load, TA = 25°C
">
CI)
'HCT541 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted). CL = 150 pF (see Note 11
PARAMETER
FROM
TO
IINPUT!
(OUTPUT!
tpd
A
Y
ten
(l"
Y
tt
Y
VCC
TA = 25°C
TYP MAX
MIN
SN54HCT541
MIN MAX
SN74HCT541
MIN
MAX
UNIT
20
33
49
42
5.5 V
19
30
45
38
4.5 V
26
40
5.5 V
25
36
60
54
50
45
ns
4.5V
17
14
42
63
57
53
48
ns
38
en
o
:E
(,)
4.5 V
5.5 V
c
ns
l:
Note 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-481
E
::J:
(")
3:
oen
c
CD
<
(i'
CD
U)
2-482
SN54HC563, SN74HC563
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
D2684. DECEMBER 1982-REVISED SEPTEMBER 1987
•
High·Current 3·State Output Drive Bus-Lines
Directly or Upto 15 LSTTL Loads
•
Bus-Structured Pinout
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
SN54HC563 ... J PACKAGE
SN74HC563 ... OW OR N PACKAGE
(TOP VIEW)
•
oe
Vee
,.0:
10
20
30
40
50
60
70
80
GNO
Dependable Texas Instruments Quality and
Reliability
description
These 8-bit latches feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
20
30
40
50
60
70
80
II)
e
CD
U
'S;
SN54HC563 ... FK PACKAGE
(TOP VIEW)
CD
Q
U
OOIU UIO
en
o
N~O>~
3
The eight latches are transparent D-type latches.
While the enable (C) is high the Q outputs will
follow the complements of data (0) inputs.
When the enable is taken low the outputs will
be latched at the inverses of the levels that were
set up at the 0 inputs.
2
~
1 2019
4
5
17
6
16
7
15
18
8
14
CJ
J:
20
30
40
50
60
9 1011 12 13
An output-control (DC) input can be used to
place the eight outputs in either a normal logic
state (high or low levels) or a high-impedance
state. In the high-impedance state the outputs
neither load nor drive the bus lines significantly.
The high-impedance state and increased highlogic level provide the capability to drive the bus
lines in a bus-organized system without need for
interface or pull-up components.
0 0 ulOIO
coz
001'0
(.:J
FUNCTION TABLE
(EACH LATCH)
INPUTS
OUTPUT
ENABLE
OC
C
L
H
L
L
H
L
H
X
The output control (DC) does not affect the
internal operation of the latches. Old data can
be retained or new data can be entered while the
outputs are in the high-impedance state.
0
H
L
X
X
Q
L
H
00
Z
The SN54HC563 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC563 is
characterized for operation from - 40°C to 85°C.
PRODUCTION DATA do.uments .ontain information
currant 8S of publication data. Products conform to
spacifications par the terms of Taxas InBtruments
=-:~~i;·[::I~'li ~::i:~i:; :.r::::9t:~~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1982, Texas Instruments Incorporated
2-483
SN54HC563, SN74HC563
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
logic symbol
logic diagram (positive logic)
c
10~._~~~~__~
20
E
40
50
60
70
:::c
n
s:o
tn
C
20 ..::3::.1_---4-i1il)J
30
3D 141
8
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for OW, J, and N packages.
40~15::.1_-+~
50 161
CD
<
C;"
CD
en
60 .:;17:..:.1_--+~1IU
70 (81
so 191
absolute maximum ratings over operating free-air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC or GNO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package. . . . . . . . . . . . .. 260°C
Storage temperature range ......................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2-484
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DA.LLAS, TeXAS 75265
SN54HC563. SN74HC563
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
, recommended operating conditions
SNS4HCS63
MIN
Vee
Supply voltage
VIH
High-level input voltage
Vee
Vee
Vee
Vee
Low-level input voltage
VIL
MAX
MIN
NOM
MAX
5
6
2
5
6
2
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
= SV
SN74HCS63
NOM
UNIT
V
1.5
1.5
3,15
3.15
4.2
4.2
V
0
0.3
0
0,3
0
0
0.9
0
0.9
1.2
0
1.2
V
VI
Input voltage
0
Vee
0
Vee
V
Va
Output voltage
0
Vee
1000
a
Vee
1000
V
fI)
ns
U
"S;
°e
c
Vee
Vee
Input transition (rise and fall I times
tt
Vee
=
=
=
2 V
4.5 V
0
0
500
0
500
6 V
0
400
0
400
-55
125
-40
85
Operating free-air temperature
TA
0
CD
CD
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
=
VIH or VIL,
=
10H
VCC
VI
VI
=
=
=
VIH or VIL,
10H
VIH or VIL,
10H
VIH or VIL,
=
=
=
10L
=
=
VIH or VIL,
II
VI
VIH or VIL,
VI - Vee or 0
10Z
Va
ICC
ei
VI
= Vee or 0
= Vee or 0,
=
10
MIN
MAX
MIN
1.9
-20~A
4.5 V
4.4 4.499
4.4
4.4
5.9
5.9
-S rnA
6V
4.5 V
3.98
5.9
3.84
6V
5.48
-7.8 mA
20~
7.8 mA
=0
MAX
SN74HC563
1.9
10L-SmA
10L
TYP
SNS4HC563
1.9 1.998
VOL
VI
MIN
= 2SoC
2V
VOH
VI
TA
5.999
4.30
3.7
5.80
5.2
MAX
5.34
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
SV
0.001
0.1
0.1
0.1
4.5 V
0.17
0.2S
0.4
0.33
SV
0.15
±0.1
0.2S
SV
0.4
±1000
±1000
nA
SV
±0.01
±10
±5
~A
8
ISO
80
~
10
10
10
pF
2 to 6 V
3
l:
V
0.002
SV
::iE
o
UNIT
2V
±100
±0,5
en
o
V
0.33
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
TA = 2SoC
Vec
tw
Pulse duration, enable e high
Setup time, data before
tou
th
enable 0
Hold time, data aler enable el
MIN
MAX
SNS4HCS63
MIN
MAX
SN74HCS63
MIN
2V
80
120
100
4.5 V
16
24
20
6V
14
17
63
2V
50
20
75
4.5 V
10
15
13
SV
9
13
11
2V
5
5
5
4.5 V
5
5
5
SV
5
5
5
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MAX
UNIT
no
no
no
2-485
SN54HC563; SN74HC563
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
•
53:
oo
cCD
<
n'
CD
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
0
a
tpd
C
Any
a
ten
DC
Any
a
tdis
DC
AnyQ
Any
tt
VCC
2V
4.5 v
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5V
6V
2V
4.5 V
6V
a
Power dissipation capacitance per latch
TA = 25°C
MIN
TYP MAX
77
175
26
35
23
30
90
175
27
35
23
30
70
150
24
30
21
26
47
150
23
30
21
26
28
60
8
12
6
10
SN54HC563
MIN MAX
265
53
45
265
53
45
225
45
38
225
45
38
90
18
15
. No load, TA = 25°C
SN74HC563
MIN MAX
220
44
37
220
44
37
190
38
32
190
38
32
75
15
13
UNIT
ns
ns
ns
ns
ns
50 pF typ
U)
Note 1: Load circuits and voltage waveforms are shown in Section 1.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUll
tpd
0
a
tpd
C
AnyQ
ten
DC
AnyQ
tt
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
AnyQ
TA = 25°C
MIN
TYP MAX
95
200
40
33
29
34
103
225
33
45
29
38
85
200
29
40
26
34
60
210
17
42
14
36
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2·486
.
TEXAS'"
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54HC563
MIN MAX
300
60
51
335
67
57
300
60
51
315
63
53
SN74HC563
MIN MAX
250
50
43
285
57
48
250
50
43
265
53
45
UNIT
ns
ns
ns
ns
SN54HCT563, SN74HCT563
OCTAL OoTYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
02804. MARCH 1984-REVISEO SEPTEMBER 19B7
SN54HCT563 ..• J PACKAGE
SN74HCT563 ... OW OR N PACKAGE
•
Inputs are TTL-Voltage Compatible
•
High-Current 3-State Output Drive Bus-Lines
Directly or Up to 15 LSTTL Loads
•
Bus-Structured Pinout
•
Package Options Include Plastic "Small
Outline" Packages, Caramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEW)
oe
Vee
10
20
30
40
50
60
70
80
10
20
30
40
50
60
70
80
II
U)
e
GNO
description
CD
CJ
These 8-bit latches feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches are transparent Ootype latches.
While the enable (C) is high the
outputs will
follow the complement of data (0) inputs. When
the enable is taken low the outputs will be
latched at the inverses pf the levels that were
set up at the 0 inputs.
a:
'S
SN54HCT563 ... FK PACKAGE
CD
(TOP VIEW)
c
U
OOIU Uld
en
N~O>~
3
30
40
50
60
70
2
4
18
5
17
6
16
7
15
14
8
The output control (OC) does not affect the
internal operation of the latches. Old data can
be retained or new data can be entered while the
outputs are in the high-impedance state.
:E
20
30
40
50
60
(..)
::t:
9 1011 12 13
0 0 Uldld
002
An output-control (OC) input can be used to
place the eight outputs in either a normal logic
state (high or low levels) or a high-impedance
state. In the high-impedance state the outputs
neither load nor drive the bus lines significantly.
The high-impedance state and increased highlogic level provide the capability to drive the bus
lines in a bus-organized system without need for
interface or pull-up components.
o
1 2019
001'
t!l
FUNCTION TABLE
INPUTS
OUTPUT
ENABLE
Q
OC
C
L
H
0
H
L
H
L
H
L
L
X
X
X
Qo
H
L
Z
The SN54HCT563 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCT563 is
characterized for operation from - 40°C to
85°C.
Copyright © 1984. Texas Instruments Incorporated
PRODUCTIOI DATA ........nll .onllin informllio.
cumnt I I af publication data. Pradllcts aanform ta
spacificatial. par the tarms of Til•• Iliitrumants
:':'=i;"iZ:l":.7i =:~i:r :'l"::~~ not
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-487
SN54HCT563, SN74HCT563
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
logic symbol t
logic diagram (positive logic)
c
10~~~~~~__~~tltl
20
II
40
50
60 C7I
70 C81
80 C91
::J:
(")
s:
ot/)
20 -",C3:,:. .1_-+-~ II
3D
3D C41
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
C
40..::C5::.1_-4--I
50 C61
CD
<
(IS'
60.:..:C7..:..1_-+-~lL' I
CD
(I)
70 (81
so
2-488
TEXAS
C91
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HCT563. SN74HCT563
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±35 mA
eontinuous current through Vee or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300 De
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package. . . . . . . . . . . . .. 260 De
Storage temperature range ......................................... - 65 De to 150 De
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute~maximum~rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HCT563
Vee Supply voltage
High·level input voltage
I
I
VIH
Low~level
Vll
input voltage
=
=
Vee
Vee
SN74HCT563
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
V
V
4.5 V to 5.5 V
2
2
4.5 V to 5.5 V
0
0.8
0
0.8
V
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
0
Input transition (rise and falll times
0
0
Vee
500
V
tt
Vee
500
ns
TA
Operating free-air temperature
-55
125
-40
85
°e
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
TEST CONDITIONS
PARAMETER
VOH
VOL
II
10Z
lee
VI
VI
=
=
VIH or VIL,
10H
VIH or VIL,
10H
=
=
vCC
-20 p.A
4.5 V
-6 rnA
4.5 V
MIN
MAX
MIN
4.4 4.499
4.4
4.4
4.30
3.7
3.84
3.98
UNIT
MAX
V
10L - 2Ol'A
4.5 V
0.001
0.1
0.1
0.1
VI - VIH or Vll,
10L
=6
4.5 V
0.17
0.26
0.4
0.33
5.5 V
±0.1
±100
±1000
±1000
5.5 V
±0.01
±0.5
±10
±5
p.A
8
160
80
I'A
1.4
2.4
3
2.9
rnA
3
10
10
10
pF
rnA
= Vee or 0
Vo = Vee or 0
VI = Vee or 0, 10 = 0
VI
5.5 V
Other inputs at 0 V or Vee
5.5 V
4.5 to
ei
SN54HCT563 SN74HCT563
VI - VIH or Vll,
One input at 0.5 V or 2.4 V
.1lee*
TA - 25°C
TYP MAX
MIN
5.5 V
V
nA
*This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to Vee.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2·489
SN54HCT563, SN74HCT563
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
vcc
1.1
:J:
tw
Pulse duration, enable C high
tsu
Setup time, data before enable CI
SN54HCT563 SN74HCT563
MIN
MAX
MIN
4.5 V
20
30
25
5.5 V
17
27
23
4.5 V
10
15
13
5.5 V
9
5
14
12
5
5
5
5
5
4.!\V
5.5 V
Hold time, data afer enable CI
th
TA = 25°C
MIN
MAX
MAX
UNIT
ns
ns
ns
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
(")
s:o
PARAMETER
tpd
tn
C
tpd
CD
<
c:;'
ten
FROM
(lNPUTI
D
C
OC
TO
(OUTPUT!
Q
AnyQ
AnyQ
CD
(I)
tdis
OC
AnyQ
AnyQ
tt
VCC
TA = 25°C
TVP MAX
MIN
4.5 V
SN54HCT563 SN74HCT563
MIN MAX
MIN MAX
28
35
53
44
5.5 V
24
32
48
40
4.5 V
30
35
53
44
5.5 V
28
32
48
40
4.5 V
28
35
53
44
5.5 V
25
32
48
40
4.5 V
25
35
53
44
5.5 V
24
32
48
40
4.5 V
10
12
18
15
5.5 V
9
11
16
14
UNIT
ns
ns
ns
ns
ns
50 pF typ
Power dissipation capacitance per latch
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER.
tpd
tpd
ten
tt
FROM
(INPUT!
D
C
OC
TO
(OUTPUT)
Q
AnyQ
AnyQ
AnyQ
VCC
TA = 25°C
MIN
TVP MAX
4.5 V
36
52
MIN
MAX
79
MIN
MAX
65
5.5 V
32
47
71
59
4.5 V
40
52
79
65
5.5 V
38
47
71
59
4.5 V
35
52
79
65
5.5 V
4.5 V
29
47
71
59
18
42
63
53
5.5 V
16
38
57
48
Note 1: load circuits and voltage waveforms are shown in Section 1.
2-490
SN54HCT563 SN74HCT563
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
SN54HC564, SN74HC564
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
02684, DECEMBER 1982-REVISED SEPTEMBER 1987
•
High-Current 3-State Output Drive Bus-Lines
Directly or Up to 15 LSTTL Loads
•
Bus-Structured Pinout
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
SN54HC564 ... J PACKAGE
SN74HC564 ... OW OR N PACKAGE
(TOP VIEW)
•
Vee
10
"0
20
30
40
50
60
70
80
20
30
40
50
60
70
80
GNO
Dependable Texas Instruments Quality and
Reliability
description
These B-bit latches feature three-state outputs
designed specifically for bus driving. They are
particularly suitable for implementing buffer
registers, 1/0 ports, bidirectional bus drivers, and
working registers.
o
elK
CD
(,)
'S;
SN54HC564 ... FK PACKAGE
CD
o
(TOP VIEW)
en
U
OOIU UIO
o
N~O>~
The eight-bit edge-triggered D-type flip-flops
enter data on the low-to-high transition of the
clock.
An output-control (OC) input can be used to
place the eight outputs in either a normal logic
state (high or low levels) or a high-impedance
state. In the high-impedance state the outputs
neither load nor drive the bus lines significantly.
The high-impedance state and increased highlogic level provide the capability to drive the bus
lines in a bus-organized system without need for
interface or pull-up components,
De
J
30
40
50
60
70
2
~
1 2019
18
4
5
17
6
16
15
14
8
(.)
20
30
40
50
60
::t
9 1011 12 13
00><:1010
CXli3dCXl .....
logic symbol t
An output control does not affect the internal
operation of the flip-flops. Old data can be
retained or new data can be entered while the
outputs are in the high-impedance state.
oc
elK
The SN54HC564 is characterized for operation
over the full military temperature range of
- 55 ac to 125 ac. The SN74HC564 is
characterized for operation from - 40°C to
B5°C,
10
2D
3D
4D
50
6D
FUNCTION TABLE
7D
(EACH FLIP-FLOP)
OUTPUT
INPUTS
OC
ClK
D
Q
l
f
H
L
L
f
L
H
L
L
X
00
H
X
X
Z
PRODUCTION DATA documonts contain information
current as of publication date. Products conform to
specifications per the tarms of Texas Instruments
::~~:~~i~a{::1~1e ~.:\~~i:; :1~o:==9t::a~
not
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1982. Texas Instruments Incorporated
2-491
SN54HC564, SN74HC564
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
logic diagram (positive logic)
OC" 111
ClK (111
1191 10
10 (21
%
0
2D (31
s:0
f/)
C
30 (41
G>
<
i;"
G>
en
40 (51
50 (61
...--«=>C1
...--ct:>C1
60 (71
(151
~_r(:.;.14~1 60
70 (81
8D (91
2-492
_
;o-+~5Q
10
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC564, SN74HC564
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through Vee or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300 De
Lead temperature 1,6 mm (1/16 in) from case for lOs: OW or N package. . . . . . . . . . . . .. 260 DC
Storage temperature range ......................................... - 65 DC to 150 DC
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
U)
G)
U
os:
recommended operating conditions
SN54HC564
NOM
MAX
2
5
6
Vee Supply voltage
VIH
Vee
Vee
High-level input voltage
Vee
=2V
= 4.5 V
=6V
=2V
Vee
Vee = 4.5 V
o
(J)
::E
V
0.3
0
0.9
0
1.2
0
1.2
0
Vee
0
Vee
V
Vee
1000
0
Vee
1000
V
0
500
0
500
n.
0
-55
400
0
400
125
-40
85
0
o
:::t:
0
0.9
0
Operating free-air temperature
V
0.3
Vee = 2 V
TA
C
0
0
6 V
UNIT
0
Output voltage
= 4.5 V
6
4.2
Vo
=
5
3.15
=6 V
Vee
2
4.2
Input voltage
Vee
MAX
3.15
VI
Input transition frise and fall) times
NOM
1.5
Low-level input voltage
tt
MIN
1.5
Vil
Vee
G)
SN74HC564
MIN
V
De
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
.
PARAMETER
TEST CONDITIONS
VCC
2V
VI
= VIH or Vll,
IOH = -20 p.A
VOH
VI - VIH or Vil.
VI
VI
=
=
VIH or Vil.
VIH or Vil.
IOH = -6mA
10H = -7.8 mA
IOl = 20 p.A
VOL
VI - VIH or Vil.
10l - 6 rnA
VI - VIH or Vil.
IOl - 7.8 rnA
= Vee or 0
II
VI
10Z
Vo
lee
ei
VI - Vee or O.
=
Vee or 0
10
=0
TA - 25 DC
MIN
TYP MAX
1.9
SN54HC564
MIN
MAX
SN74HC564
MIN
1.998
1.9
1.9
4.5 V
4.4 4.499
6V
5.9 5.999
4.4
5.9
4.4
5.9
3.7
3.84
4.5 V
3.98
6V
5.48
4.30
5.80
5.2
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
6V
0.17
0.15
0.26
0.4
0.33
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
6V
±0.01
±0.5
±10
±5
pA
8
160
80
pA
10
10
10
pF
6V
2 to 6 V
3
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V
2-493
SN54HC564, SN74HC564
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
vcc
fclock
•
2V
4.5 V
Clock frequency
tw
Pulse duration, ClK high or low
tsu
Setup time, data before ClK!
th
Hold time, data after elK!
6V
2V
4.5 V
6V
2V
4.5.v
6V
2V
4.5 V
6V
l:
(')
3:
ot/)
o
CD
TA = 25°C
MIN
MAX
0
6
31
36
0
0
80
16
14
SN54HC564
MIN MAX
0
0
0
120
24
20
100
20
17
150
30
26
5
5
5
5
5
5
4.2
21
25
SN74HC564
MIN MAX
0
0
0
100
5
25
UNIT
MHz
29
20
17
ns
125
25
21
5
5
ns
ns
5
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
<
c:;'
PARAMETER
CD
en
FROM
(INPUT)
TO
(OUTPUT)
2V
4.5V
6V
2V
)
f max
tpd
ClK
Any
a
ten
OC
Any
a
ldis
tt
Vce
OC
Any
a
Any
a
TA = 25°C
MIN
TYP MAX
11
6
31
36
4.5V
6V
2V
4.5 V
6V
2V
4.5V
6V
2V
4.5V
6V
Power dissipation capacitance per flip·flop
36
40
54
18
15
TEXAS
4.2
21
SN74HC564
MIN MAX
MHz
25
29
180
270
36
31
54
46
225
45
38
45
15
13
150
225
45
190
38
45
150
15
13
30
26
38
225
45
38
28
8
60
12
90
32
190
38
32
75
6
10
1.8
15
15
13
30
26
No load, TA = 25°C
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
5
25
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2-494
SN54HC564
MIN MAX
100 pF typ
ns
ns
ns
ns
SN54HC564, SN74HC564
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
UNPUT)
Ipd
D
len
OC
II
TO
(OUTPUT)
Any
0
AnyO
Any
0
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
TYP MAX
75
230
24
46
21
34
57
200
19
40
17
34
60
210
17
42
14
36
SN54HC564
MIN MAX
345
69
58
300
60
51
315
63
53
SN74HC564
MIN MAX
290
58
49
250
50
43
265
53
45
UNIT
ns
ns
ns
en
CD
CJ
Note 1: Load circuits and voltage waveforms are shown in Section 1.
"S:
CD
Q
CI)
o
:e
(J
::J:
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
2·495
•
z
(')
s:o
en
c
n'
CD
CD
<
(I)
2-496
SN54HCT564, SN74HCT564
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
D2804. MARCH 1984-REVISED SEPTEMBER 1987
•
Input8 are TTL·Voltage Compatible
•
High·Current 3·State Output Drive Bus-Lines
Directly or Up to 15 LSTTL Loads
•
Bus-Structured Pinout
•
Package Options Include Plastic "Small
Outline" Peckages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HCT564 ..• J PACKAGE
SN74HCT564 ... ow OR N PACKAGE
ITOP VIEW}
description
These B-bit registers feature three-state outputs
designed specifically for bus driving. They are
particularly suitable for implementing buffer
registers. 1/0 ports. bidirectional bus drivers. and
working registers.
0
l
3
l
H
l
00
H
X
X
X
en
:E
(.)
o
2
1 20 19
4
lB
5
6
7
17
B
14
:::r:
16
15
oc
ClK
10
20
121
(31
(4}
3D
(5}
40
50
60
BO
l
Q)
C
logic symbol t
0:
H
'S;
910111213
70
t
t
Q)
Co)
CJ
OUTPUT
l
l
U)
elK
N~O>-
FUNCTION TABLE
(EACH FLIP-FLOP}
ClK
II
o 0ICJ CJld
The SN54HCT564 is characterized for operation
over the full military temperature range of
- 55°C. to 125°C. The SN74HCT564 is
characterized for operation from - 40°C to
B5°C.
OC
10
20
30
40
50
60
70
80
(TOP VIEWI
An output-control (OC) input can be used to
place the eight outputs in either a normal logic
state (high or low levels) or a high-impedance
state. In the high-impedance state the outputs
neither load nor drive the bus lines significantly.
INPUTS
Vee
10
20
30
40
50
60
70
80
GNO
SN54HCT564 ... FK PACKAGE
The eight-bit edge-triggered Ootype flip-flops
enter data on the low-to-high transition of the
clock.
The output control does not affect the internal
operation of the flip-flops. Old data can be
retained or new data can be entered while the
outputs are in the high-impedance state.
oe
(6}
(7}
(S}
(9}
7<:1
1l2} 8<:1
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Z
PRODUCTION DATA documenls contsin information
currant as of publication dat•. Products confarm ta
specifications per the terms of rexls Instruments
::=~~ai~:1~1i ~!:\~~ti:; :IIO::;:::::-'~S nDt
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1984, Texas Instruments Incorporated
2-497
SN54HCT564. SN74HCT564
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
logic diagram (positive logic)
oc
(1)
ClK (11)
(19) 10:
10 (2)
lEI
:::t
0
(18)
20 (3)
_
20
s:
0
en
C1
30 (4)
10
C
CD
<
n'
CD
(I)
C1
40 (5)
(16)
40:
10
t--C1
50 (6)
10
.....-C1
60 (7)
10
.....-C1
70 (8)
_
(14) _
"»-+';"";"6Q
(13) _
")0--+-'-= 70
(12)
80 (9)
2-498
(15)
'»-+';"";"50
_
~--'--8Q
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SN54HCT564. SN74HCT564
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K (Va < 0 or Va > Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (Va = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package .............. 260°C
Storage temperature range ......................................... - 65°C to 1 50°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute·maximum-rated conditions for extended periods may affect device reliability.
II
fI)
Q)
U
recommended operating conditions
'S
SN54HCT564
Q)
SN74HCT564
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
vee
V,H
Supply voltage
High-level input voltage
I Vee
- 4.5 V to 5.5 V
2
V,L
V,
Low-level input voltage
L Vee
~ 4.5 V to 5.5 V
0.8
0
Vee
0
Vee
500
0
0
vee
500
125
-40
85
Output voltage
Input transition (rise and fall) times
TA
Operating free-air temperature
0
-55
o
V
0
Vo
en
V
2
Input voltage
tt
o
UNIT
0
0
:E
0.8
V
vee
V
(.)
V
J:
ns
De
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
VOL
4.5 V
10L ~ 20 ~A
4.5 V
4.5 V
10L = 6 mA
10H 10H
V, ~ V,H or V'L,
V, ~ V,H or V'L,
V, ~ Vee orO
10Z
Vo
lee
V,
ei
-20 pA
-6 mA
V, - VIH or V'L,
V, ~ V,H or V'L,
I,
alee t
Vce
TEST CONDITIONS
~
~
~
Vee or 0
Vee or 0, 10
~
0
4.4 4.499
3.98
SN54HCT564 SN74HCT564
MIN
MAX
MIN
4.4
4.4
3.7
3.84
MAX
UNIT
V
4.30
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
5.5 V
±0.1
±100
±1000
±1000
nA
5.5 V
±0.01
±0.5
±10
±5
pA
8
160
80
~A
1.4
2.4
3
2.9
mA
3
10
10
10
pF
5.5 V
One input at 0.5 V or 2.4 V
Other inputs at 0 V or Vee
TA - 25°C
MIN
TYP MAX
5.5 V
4.5 to
5.5 V
t This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
V
Vee.
2-499
SN54HCT564, SN74HCT564
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
Vce
fclock
%
s::
o(I)
Clock frequency
tw
Pulse duration, CLK high or low
tsu
Setup time, data before CLKt
Hold time, data after CLKt
th
(")
4.5 V
TA = 25°C
MIN
MAX
0
31
36
SN54HCT564 SN74HCT564
MIN
MAX
MIN
MAX
21
25
23
28
5.5 V
0
4.5 V
16
24
20
5.5 V
4.5 V
14
20
22
30
18
25
5.5 V
17
27
23
4.5 V
5
5
5
5.5 V
5
5
5
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
c
FROM
IINPUT)
TO
IOUTPUT)
f max
CD
<
ri"
CD
tpd
til
ten
tdis
CLK
ac
ac
Any
Any
Any
Any
tt
Vce
TA = 25°e
MIN
TYP MAX
SN54HCT564 SN74HCT564
MIN
MAX
MIN
4.5 V
31
36
21
25
5.5 V
36
40
23
28
MAX
MHz
54
45
48
41
38
27
45
41
38
a
4.5V
18
5.5 V
16
36
32
a
4.5 V
14
30
5.5 V
10
34
a
4.5 V
22
30
45
5.5 V
20
27
41
34
a
4.5 V
10
9
12
18
15
11
16
14
5.5 V
Power dissipation capacitance per flip-flop
UNIT
ns
ns
ns
ns
93 pF typ
No load, TA = 25°C
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
tpd
ten
tt
FROM
TO
IINPUT)
IOUTPUT)
CLK
ac
Any
Any
Any
a
a
a
Vce
TA = 25°C
MIN
TYP MAX
4.5 V
38
5.5 V
MIN
MAX
MIN
MAX
80
66
36
53
47
71
60
4.5 V
30
47
71
5.5 V
4.5 V
27
59
59
49
18
39
42
63
53
5.5 V
16
38
57
48
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2-500
SN54HCT564 SN74HCT564
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
ns
ns
ns
SN54HC573. SN74HC573A
OCTAL O-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
02684. DECEMBER 1982-REVISED JUNE 1989
•
High-Current 3-State Output Drive Bus-Lines
Directly or Up to 15 LSTTL Loads
•
Bus-Structured Pinout
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
SNS4HCS73 ... J PACKAGE
SN74HC573 ... OW OR N PACKAGE
(TOP VIEW)
•
oe
Vee
10
10
20
30
40
50
60
70
80
20
30
40
50
60
70
80
Dependable Texas Instruments Quality and
Reliability
description
II)
Q)
(J
"S
SN54HC573 ... FK PACKAGE
Q)
c
(TOP VIEW)
U
Ud
tJ)
1 2019
:!
° 0IU
o
N~d>~
The eight latches are transparent D-type latches.
While the enable (C) is high the (0) outputs will
respond to the data (D) inputs. When the enable
is taken low the outputs will be latched to retain
the data that was set up.
An output-control (OC) input can be used to
place the eight outputs in either a normal logic
state (high or low logic levels) or a highimpedance state. In the high-impedance state
the outputs neither load nor drive the bus lines
significantly. The high-impedance state and
increased drive provide the capability to drive the
bus lines in a bus-organized system without need
for interface or pull-up components.
•
e
GNO
These 8-bit latches feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers. I/O ports. bidirectional bus drivers. and
working registers.
3
2
()
18
J:
17
16
6
7
15
8
14
9 1011 12 13
OOUdd
ooz
00 ....
t?
logic symbol t
oc
C
The output control (OC) does not affect the
internal operation of the latches. Old data can
be retained or new data can be entered while the
outputs are in the high-impedance state.
10
20
10
(3)
(18) 20
(4)
3D
(5)
40
(6)
50
(7)
60
(8)
70
(9)
80
The SN54HC573 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC573 is
characterized for operation from - 40°C to
85°C.
(19)10
(17) 30
(16) 40
(15) 50
(14) 60
(13)
70
(12)
80
FUNCTION TABLE
tThis symbol is in accordance with ANSI/lEEE Std 91-1984 and
IEC Publication 617 1 2
(EACH LATCH)
INPUTS
OUTPUT
ENABLE
Q
OC
C
0
L
H
H
L
H
L
L
L
L
X
QO
H
X
X
Z
H
PRODUCTION DATA do.ume.ts .o.laln information
• urrent I I of publiCltio. dill. Prod.oII conform to
_ilicatiORl per the toms of TilliS Instru..ents
=ri~·i:I':.2;=:i:;~.not
Copyright @ 1989, Texas Instruments Incorporated
TEXAS •
; INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-501
SN54HC573, SN74HC573A
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
logic diagram (positive logic)
OC
(1 )
C
(19)
•
%
10
20
(2)
(18)
(3)
1a
2a
n
:s:
0
rJ)
C1
3D
(4)
(17)
10
3a
C
CD
<
n'
CD
(I)
40
(16)
(5)
(15)
50
60
(6)
(14)
(7)
(13)
(8)
4a
5a
6a
7a
70
(12)
80
2·502
(9)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
8a
SN54HC573. SN74HC573A
OCTAL D·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Va < 0 or Va > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (Va = 0 to Vce) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package. . . . . . . . . . . . .. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These arB stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SNS4HCS73
MIN NOM MAX
vee Supply voltage
VIH
High-level input voltage
Vil
Low-level input voltage
Vee
Vee
Vee
Vee
Vee
Vee
VI
Vo
Input voltage
Output voltage
tt
Input transition Irise and fall) times
Vee
Vee
Vee
2
1.5
3.15
4.2
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
=2V
= 4.S V
=6V
Operating free-air temperature
TA
5
6
0.3
0
0
0
0.9
1.2
0
0
0
Vee
Vee
1000
0
0
-S5
SOO
400
125
SN74HCS73
MIN
NOM
MAX
2
1.5
3.15
4.2
5
6
•
UNIT
V
V
0.3
0
0
0
0
0
0
0
0
-40
0.9
1.2
V
Vee
Vee
1000
500
400
V
V
85
ns
De
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
=
VIH or Vll,
10H
=
-20
VI
VI
=
=
VIH or Vil.
VIH or Vil.
10H
10H
=
=
-6 mA
-7.8 mA
~A
VOH
VI
=
VIH or Vil.
10l
=
20 p.A
VOL
VI - VIH or Vil.
II
10Z
ICC
ei
= VIH or Vil.
= Vee orO
Vo = Vee or 0
VI = Vee or O.
VI
VI
10l - 6 mA
10l = 7.8 mA
10
=0
VCC
TA - 2SoC
MIN
TYP MAX
2V
4.S V
6V
4.5 V
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
6V
2V
4.5 V
5.48
5.80
0.002
0.001
0.001
0.17
6V
4.5 V
6V
6V
6V
0.15
±0.1
SN54HC573
MIN MAX
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.26
SN74HC573
MIN MAX
1.9
4.4
5.9
3.84
V
5.34
0.1
0.1
0.1
0.4
0.4
0.1
0.1
0.1
0.33
±0.01
0.26
±100
±0.5
±1000
±10
0.33
±1000
±5
3
8
10
160
10
80
10
6V
2 to 6 V
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
V
nA
~A
p.A
pF
2-503
SN54HC573, SN74HC573A
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
VCC
2V
4.5 V
Pulse duration, C high
tw
6V
2V
4.5 V
6V
Setup time, data before enable Cl
tsu
2V
4.5V
6V
Hold time, data afer enable C I
th
:::r:
TA - 2S0C
MAX
MIN
SN54HCS73
MIN MAX
SN74HC573
MIN MAX
80
16
14
120
24
20
100
20
17
50
10
75
15
9
20
5
13
5
5
63
13
11
24
5
5
UNIT
ns
ns
5
5
ns
(")
s:o
(I)
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
c(1)
PARAMETER
FROM
(lNPUTI
TO
(OUTPUTI
<
(is'
tpd
(1)
0
Q
2V
4.5 V
Any Q
6V
2V
4.5 V
en
tpd
ten
tdis
tt
e
De
Ol::
Vcc
Any Q
Any Q
Any Q
TA - 2Soc
MIN
TVP MAX
77
175
26
35
23
30
175
87
27
6V
2V
4.5 V
6V
23
68
24
21
2V
4.5 V
47
23
6V
2Y-
21
28
8
4.5 V
6V
Power dissipation capacitance per latch
MIN
35
30
150
30
26
150
6
30
26
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MAX
265
53
45
SN74HC573
MIN
MAX
220
44
38
265
53
220
44
45
225
45
38
190
38
32
38
225
45
38
UNIT
ns
ns
ns
190
38
ns
ns
60
12
90
18
32
75
16
10
15
13
No load, TA - 25°e
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2-504
SN54HC573
50 pF typ
SN54HC573, SN74HC573A
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUll
tpd
0
0
tpd
C
Any 0
ten
OC
Any 0
tt
Any 0
VCC
TA = 25°C
MIN
TYP MAX
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
95
33
21
103
33
29
85
29
26
60
17
14
200
40
34
225
45
38
200
40
34
210
42
36
Note 1: Load circuits and voltage waveforms are shown in Section 1.
SN54HC573
MIN
MAX
300
60
51
335
67
57
300
60
51
315
63
53
SN74HC573
MIN
MAX
250
50
43
285
57
48
250
50
43
265
53
45
UNIT
ns
ns
ns
U)
CD
CJ
ns
">
CD
o
UJ
o
:E
(J
::J:
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-505
::J:
C')
s:
oen
o
(I)
<
o·
(I)
tn
2-506
SN54HCT573. SN74HCT573
OCTAL O-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
02804, MARCH 1984-REVISEO SEPTEMBER 1987
SN54HCT573 ... J PACKAGE
SN74HCT573 ... OW OR N PACKAGE
(TOP VIEW)
•
Inputs are TTL-Voltage Compatible
•
High-Current 3-State Output Drive Bus-Lines
Directly or Up to 15 LSTTL Loads
•
Bus-Structured Pinout
10
10
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
20
20
30
30
40
•
oc
Vee
40
Dependable Texas Instruments Quality and
Reliability
50
50
60
70
60
70
80
80
GNO
These 8-bit latches feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers. I/O ports. bidirectional bus drivers. and
working registers.
U)
C
description
CD
U
'S;
SN54HCT573 ... FK PACKAGE
The eight latches are transparent O-type latches.
While the enable (C) is high the outputs (Q) will
respond to the data (D) inputs. When the enable
is taken low the outputs will be latched to retain
the data that was set up.
50
70
CD
(TOP VIEW)
C
u
aN~O>~
alu ua
en
3
:!:
2
o
1 2019
4
5
18
20
17
30
6
16
40
7
15
50
8
14
60
o
::t
9 1011 1213
An output-control (OC) input can be used to
place the eight outputs in either a normal logic
state (high or low levels) or a high-impedance
state. In the high-impedance state the outputs
neither load nor drive the bus lines significantly.
The high-impedance state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pull-up components.
aauaa
ooz
co ......
(!)
FUNCTION TABLE
(EACH LATCH)
INPUTS
oc
An output control (OC) does not affect the
internal operation of the latches. Old data can
be retained or new data can be entered while the
outputs re in the high-impedance state.
OUTPUT
ENABLE
C
Q
L
H
L
H
0
H
L
L
H
L
X
00
X
X
Z
H
L
The SN54HCT573 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HCT573 is
characterized for operation from - 40°C to 85°C.
i. infallllllio.
PRODUCTION DATA ....._
.....
.urrent •• of pu~ll..ti•• d.... Products confor.. ..
,pICifico1i••• por 1Iut ...... of T.... I............
=i;;"i~'~
=::r :~:::.::"
nat
TEXAS
~
INSTRUMENTS
POST OFFICE BOX- 65501 2 • DALLAS. TEXAS 75265
Copyright © 1984, Texas Instruments Incorporated
2-507
SN54HCT573, SN74HCT573
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
logic symbol t
logic symbol (positive logic)
oc
c
C
10~~~~~~__~
20
•
(2)
C1
1Q
1D
3D
40
50~~~~--------~
6D
::J:
2D
(3)
C1
1D
2Q
70
80
(')
3:
o(I)
10
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
3D
3Q
(4)
C
CD
<
C1
n"
CD
40
(5)
1D
4Q
(I)
5D
(6)
5Q
(7)
6Q
(8)
7Q
(9)
8Q
6D
7D
8D
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee .............................. ±20 mA
Continuous output current, 10 (Vo = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±35 mA
Continuous current through Vee or GNO pins ................................ " ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package. . . . . . . . . . . . . .. 300 DC
Lead temperature 1.6 mm (1/16 in) from case for 10 s: OW or N package .............. 260 De
Storage temperature range ......................................... - 65 DC to 150 DC
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2-508
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 •. DALLAS, TexAs 75265
SN54HCT573, SN74HCT573
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
recommended operating conditions
SN54HCT573
Vee Supply voltage
High-level input voltage
I Vee = 4.5 V to
SN74HCT573
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
V
V
5.5 V
2
I Vee = 4.5Vt05.5V
0
0.8
0
0.8
V
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
0
tt
Input transition (rise and fall) times
0
Vee
500
0
Vee
500
TA
Operating free-air temperature
-55
125
-40
85
VIH
V,l
V,
Low-level input voltage
2
V
ns
·e
electrical characteristics over recommended operating free·air temperature range (unless otherwise
notedl
TEST CONDITIONS
PARAMETER
VOH
VOL
V,
V,
= VIH
= VIH
VCC
TA - 25°C
MIN
TYP MAX
SN54HCT573 SN74HCT573
MIN
MAX
MIN
4.4
4.4
3.7
3.84
or V'l,
10H = -20 ~A
4.5 V
or V'l,
10H
4.5 V
10l
= -6 mA
= 20 ~A
4.5 V
0.001
0.1
0.1
0.1
10l
= 6mA
4.5 V
0.17
0.26
0.4
0.33
V, - VIH or V'l,
VI
= VIH
= Vee or 0
or Vll,
4.4 4.499
3.98
4.30
UNIT
MAX
V
V
I,
V,
5.5 V
±0.1
±100
±1000
±1000
nA
10Z
Vo - Vee orO
5.5 V
±0.01
±0.5
±10
±5
~
lee
VI = Vee or 0, 10 = 0
One input at 0.5 V or 2.4 V
5.5 V
8
160
80
~A
1.4
2.4
3
2.9
mA
3
10
10
10
pF
Alee!
Other inputs at 0 V or Vee
5.5 V
4.5 to
ei
5.5 V
tThis is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or Vee.
timing requirements over recommended operating free-air temperature range (unless otherwise notedl
VCC
tw
Pulse duration, e high
tsu
Setup time, data before enable 0
th
Hold time, data afar enable C.J..
4.5 V
TA = 25°C
MIN
MAX
SN54HCT573 SN74HCT573
MIN
MAX
MIN
20
30
25
5.5 V
17
27
23
4.5 V
10
15
13
5.5 V
9
14
12
4.5 V
5
5
5.5 V
5
5
5
5
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MAX
UNIT
ns
ns
ns
2-509
SN54HCT573, SN74HCT573
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
II
FROM
(lNPUTI
TO
(OUTPUTI
Ipd
0
Q
tpd
C
Any Q
ten
OE
Any Q
Idis
DC
Any Q
::::s::
o
<
5'
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5V
5.5 V
TA = 25°C
MIN
TYP MAX
25
35
21
32
28
35
25
32
26
35
23
32
23
35
22
32
9
12
11
9
SN54HCT573 SN74HCT573
MIN MAX
MIN MAX
44
53
48
40
44
53
48
40
53
44
40
48
53
44
40
48
15
18
14
16
No load, TA = 25°C
Power dissipation capacitance per latch
rn
cCD
Any Q
II
s::
o
vcc
UNIT
ns
ns
ns
ns
ns
50 pF Iyp
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
CD
PARAMETER
(I)
FROM
(lNPUTI
TO
(OUTPUT)
tpd
0
Q
tpd
C
Any Q
ten
OE
Any Q
tt
Any Q
Vcc
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
V
V
V
V
V
V
V
TA = 25°C
MIN
TYP MAX
52
32
27
47
52
38
47
36
33
52
28
47
18
42
16
38
Power dissipation capacitance per latch
No load, TA = 25'C
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2-510
TEXAS
SN54HCT573 SN74HCT573
MIN MAX
MIN MAX
79
65
71
59
79
65
71
59
79
65
71
59
63
53
57
48
~
INSTRUMENTS
POST OFFIcE BOX 655012 • DALLAS. TeXAS 75265
50 pF typ
UNIT
ns
ns
ns
ns
SN54HC574, SN74HC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
02684, DECEMBER 1982-REVISED SEPTEMBER 1987
•
SN54HC574 .•• J PACKAGE
SN74HC574 ... ow OR N PACKAGE
High-Current 3-State Noninverting Outputs
Drive Bus-Lines Directly or Up to 15 LSTTL
Loads
(TOPVIEWI
Vee
•
Bus-Structured Pinout
•
Package Options Include Plastic "Small
Out6ne" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
10
20
30
40
50
60
70
80
10
20
30
40
50
60
70
80
These 8-bit registers feature three-state outputs
designed specifically for bus driving, They are
particularly suitable for implementing buffer
registers. I/O ports, bidirectional bus drivers, and
working registers.
3
l
t
t
H
H
l
l
L
l
L
00
H
X
X
X
18
(.)
17
:::r:::
logic symbol t
oc
ClK
10
20
3D
10
(3)
(4)
80
0
:E
1 20 19
15
(EACH FLIP-FLOP)
OUTPUT
2
14
FUNCTION TABLE
0
en
o
16
(5)
40
(6)
50
(7)
60
(8)
70
ClK
CI)
o
U
The SN54HC574 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC574 is
characterized for operation from - 40°C to
85°C.
INPUTS
"S;
°N-O>0IU Ud
The output control does not affect the internal
operation of the flip-flops. Old data can be
retained or new data can be entered while the
outputs are in the high-impedance state.
ire
CI)
(.)
SN54HC574 ... FK PACKAGE
(TOP VIEW)
The eight edge-triggered O-type flip-flops enter
data on the low-to-high transition of the clock.
An output-control (OC) input can be used to
place the eight outputs in either a normal logic
state (high or low logic levels) or a highimpedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines
significantly. The high-impedance state and
increased high-logic level provide the capability
to drive the bus lines in a bus-organized system
without need for interface or pull-up
components.
U)
elK
GNO
description
fI
(9)
\7
(19) 10
(18) 20
(17) 30
(16)
40
(15)
50
(14)
60
(13)
70
(12)
80
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Z
PRODUCTION DATA do•• monts .ontain informalion
current I. of publication dati. Products conform to
specificatiD.' par the terms af T8X.I Instruments
=:~~I;li~:I~Ji ~=~~:i:; :I~D::~::~:'~ nat
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
Copyright © 1982, Texas Instruments Incorporated
2-511
SN54HC574. SN74HC574
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
logic diagram (positive logic)
E
:::z::
20 13 }
30 14}
0
3:
0
40 15 }
tn
C
CD
<
50
16}
r;"
CD
til
60 17 }
70'S}
SO'9}
2·512
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DAl.lAS. TEXAS 75265
SN54HC574, SN74HC574
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range t
Supply voltage. Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current. 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current. 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current. 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1.6 mm (1/16 in) from case for 60 s: FK or J package. . . . . . . . . . . . . .. 300°C
Lead temperature 1.6 mm (1/ 16 in) from case for lOs: OW or N package . . . . . . . . . . . . .. 260°C
Storage temperature range ......................................... - 65°C to 1 50°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC574
Vee Supply voltage
Vee
VIH
High-level input voltage
Vee
vee
VIL
Vee
Vee
Low-level input voltage
Vee
VI
Input voltage
Vo
Output voltage
Vee
Input transition (rise and fall I times
tt
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Operating free-air temperature
TA
SN74HC574
MIN
NOM
MAX
MIN
NOM
MAX
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-55
5
6
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-40
5
6
0.3
0.9
1.2
Vee
Vee
1000
500
400
125
•
UNIT
V
V
0.3
0.9
V
1.2
Vee
V
Vee
1000
V
500
ns
400
85
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
=
VIH or VIL.
IOH
=
VCC
VI
VI
=
=
VIH or VIL.
VIH or VIL.
IOH IOH
10L
=
=
II
IOZ
lee
ej
VI - Vee or O.
MIN
-20 p.A
4.5 V
4.4 4.499
4.4
4.4
5.9 5.999
-6 rnA
6V
4.5 V
3.98
5.9
3.7
3.84
6V
5.48
10L = 6 rnA
10L - 7.8 rnA
10 - 0
SN74HC574
1.9
20l'A
= Vee or 0
Vo = Vee or 0
MAX
1.9
-7.8 rnA
VI
MIN
1.9 1.998
VOL
VI = VIH or VIL.
VI - VIH or VIL.
SN54HC574
2V
VOH
VI - VIH or VIL.
TA - 25°C
MIN
TVP MAX
4.30
5.9
5.2
5.80
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.33
0.33
V
6V
0.15
0.26
0.4
0.4
6V
±0.1
±100
±1000
±1000
6V
±0.01
±0.5
±10
±5
p.A
8
160
80
10
10
10
I'A
pF
6V
2 to 6 V
3
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76266
nA
2-513
SN54HC574, SN74HC574
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
Pulse dUration
tw
I
ClK high or low
Setup time, data before ClKt
tsu
:::r:
n
s::
o
en
o
Hold time, data after ClKt
th
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
SN54HC574
MAX
SN74HC574
MIN
MAX
0
6
0
4
0
5
0
30
0
20
0
24
0
38
0
120
24
0
28
80
16
MIN
UNIT
MHz
100
24
20
14
20
17
100
150
125
20
30
25
17
26
21
5
5
5
5
5
5
5
5
5
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
CD
<
PARAMETER-
r;'
FROM
(INPUT)
TO
IOUTPUTI
CD
Ul
f max
tpd
ten
tdis
tt
ClK
DC
OC
Any Q
Any Q
Any Q
Any Q
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Power dissipation capacitance
TA = 25°C
MIN
TYP MAX
MIN
MAX
SN74HC574
MIN
11
4
5
30
36
20
24
36
40
24
28
6
MAX
180
270
225
28
36
54
24
31
45
38
190
77
150
46
225
26
30
45
38
23
26
38
32
52
150
225
190
24
30
45
38
22
26
38
32
28
60
90
75
8
12
15
6
10
18
15
No load, TA = 25°C
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
MHz
90
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2-514
SN54HC574
13
100 pF typ
ns
ns
ns
ns
SN54HC574, SN74HC574
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
ClK
Any Q
ten
OC
Any Q
tt
Any Q
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
TYP MAX
SN54HC574
MIN
MIN
6
30
36
4
20
24
105
36
31
95
32
28
60
17
14
265
53
46
235
47
41
210
42
36
MAX
SN74HC574
MIN
MAX
5
24
28
400
80
68
355
71
60
315
63
53
UNIT
MHz
330
66
57
295
59
51
265
53
45
ns
ns
•
ns
Note 1: Load circuits and voltage waveforms are shown in Section 1 .
. TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-515
E
J:
("')
3:
ot/)
o
CD
<
5"
CD
en
2-516
SN54HCT574, SN74HCT574
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
02804. MARCH 1984-REVISEO SEPTEMBER 1987
•
Inputs are TTL· Voltage Compatible
•
High·Current 3·State Noninverting Outputs
Drive Bus-Lines Directly or Up to 15 LSTTL
Loads
SN54HCT574 ... J PACKAGE
SN74HCT574 ... ow OR N PACKAGE
•
Bus-Structured Pinout
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEWI
De
Vee
10
10
20
30
40
50
60
70
80
20
30
40
50
60
70
80
elK
GNO
description
SN54HCT574 ... FK PACKAGE
These 8-bit registers feature three-state outputs
designed specifically for bus driving. They are
particularly suitable for implementing buffer
registers. I/O ports. bidirectional bus drivers. and
working registers.
(TOP VIEW I
U
o
0IU UO
N~O>~
3
30
40
50
60
70
The eight edge-triggered Ootype flip-flops enter
data on the low-to-high transition of the clock.
An output-control (OC) input can be used to
place the eight outputs in either a normal logic
state (high or low logic levels) or a highimpedance state. In the high-impedance state.
the outputs neither load nor drive the bus lines
significantly. The high-impedance state and
increased high-logic level provide the capability
to drive the bus lines in a bus-organized system
without need for interface or pull-up
components.
The output control does not affect the internal
operation of the flip-flops. Old data can be
retained or new data can be entered while the
outputs are in the high-impedance state.
The SN54HCT574 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCT574 is
characterized for operation from - 40°C to
85°C.
(EACH FLiP-FlOPI
INPUTS
OUTPUT
OC
ClK
0
a
l
H
H
l
t
t
l
l
l
l
00
H
X
X
X
1 2019
18
5
17
6
16
8
14
15
20
30
40
50
60
9 1011 1213
00><:00
OO~dCX)1'
logic symbol t
Dc
ClK
10
20
10
(31
(41
30
(51
40
(61
50
60
70
80
FUNCTION TABLE
2
4
(7)
(81
(91
'"
(191 10
(181 20
(171
30
(161 40
(151 50
(141 60
(131
70
(121
80
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEe Publication 617·12.
Z
PRODUCTIOI DATA d..umants contsin information
....ant IS 0' publicotion dill. Products confarm to
.pacifications pili' th. tonns at T.x•• IRlllumants
=~i~"['::~li ~::\:~:: .l\l:;~~ not
Copyright © 1984, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-517
SN54HCT574, SN74HCT574
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
logic diagram (positive logic)
II
20 (3 )
l:
30 (4 )
()
s:
0
40 (5 )
tn
0
CD
<
C;'
50 (6 )
CD
en
60 (7 )
70 (8 )
80 (9 )
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through Vee or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1 '1 6 in) from case for 60 s: FK or J package. . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1'16 in) from case for 10 s: OW or N package .............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2-518
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HCT574. SN74HCT574
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
recommended operating conditions
Vee
V,H
V,l
V,
Va
tt
TA
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
Input transition Irise and falll times
Operating free-air temperature
I Vee = 4.5 V to 5.5 V
I
= 4.5 V to
Vee
5.5 V
SN54HCT574
MIN NOM MAX
4.5
5
5.5
2
0
O.B
0
Vee
0
Vee
0
500
-55
125
SN74HCT574
MIN NOM MAX
4.5
5
5.5
2
0
O.B
0
Vee
0
Vee
500
0
-40
B5
UNIT
V
V
V
V
V
ns
·e
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER
VOH
VOL
"
IOZ
lee
<1lee t
TEST CONDITIONS
=
=
Vcc
V, = V,H or V,l.
IOH
V, = V,H or V'l.
-6 mA
IOH
IOl = 20 p.A
IOl - 6 mA
-20 p.A
V, = V,H or V,l.
VI - VIH or V,l.
V, - Vee or 0
Vo = Vee or 0
V, - Vee or O. 10 - 0
One input at 0.5 V or 2.4 V
Other inputs at 0 V or Vee
ei
4.5 V
4.5
4.5
4.5
5.5
5.5
5.5
V
V
V
V
V
V
TA - 25°C
TYP MAX
MIN
4.4 4.499
3.98
4.30
0.001
0.17
±0.1
±0.01
SN54HCT574 SN74HCT574
MIN MAX
MIN MAX
4.4
4.4
3.7
fI
UNIT
V
3.84
0.1
0.26
±100
±0.5
8
0.1
0.4
±1000
±10
160
0.1
0.33
±1000
±5
80
nA
p.A
p.A
V
5.5 V
1.4
2.4
3
2.9
mA
4.5 to
5.5 V
3
10
10
10
pF
tThis is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or Vee.
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
Vcc
fclock
elock frequency
tw
Pulse duration
tsu
Setup time. data before elK!
th
Hold time. data after elKt
I
elK high or low
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
V
V
V
V
V
V
V
TA = 25°C
MAX
MIN
0
30
0
33
16
14
20
17
5
5
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HCT574 SN74HCT574
MIN MAX
MIN MAX
0
20
24
0
22
0
27
0
24
20
22
18
30
25
27
23
5
5
5
5
UNIT
MHz
ns
n.
ns
2-519
SN54HCT574, SN74HCT574
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT}
TO
(OUTPUT}
f max
•
tpd
CLK
Any Q
ten
DC
Any Q
tdis
::t:
("')
:=
c
<
5'
CD
en
Any Q
Any Q
tt
orn
CD
ac
vcc
TA = 25°C
TYP MAX
MIN
4.5 V
30
36
5.5 V
33
40
4.5 V
SN54HCT574 SN74HCT574
MIN
MAX
20
MIN
MAX
24
22
MHz
27
30
25
36
32
54
48
45
41
4.5 V
26
30
45
38
5.5 V
23
27
41
34
4.5 V
23
30
45
38
5.5 V
22
27
41
34
4.5 V
5.5 V
10
12
11
18
15
16
14
5.5 V
9
Power diSSipation capacitance per flip-flop
No load. TA
= 25°C
UNIT
ns
ns
ns
ns
93 pF typ
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT}
f max
tpd
eLK
Any Q
ten
DC
Any Q
tt
Any Q
VCC
TA = 25°C
MIN
TYP MAX
MIN
4.5 V
30
36
20
5.5 V
33
40
22
MAX
MIN
MAX
24
40
53
5.5 V
4.5 V
35
34
47
80
71
47
71
59
5.5 V
29
39
94
78
4.5 V
18
42
63
53
5.5 V
16
38
57
48
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • CALLAS. TeXAS 75265
UNIT
MHz
27
4.5 V
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2·520
SN54HCT574 SN74HCT574
66
60
ns
ns
ns
SN54HC590A, SN74HC590A
8-BIT BINARY COUNTERS
WITH 3-STATE OUTPUT REGISTERS
02684. DECEMBER 19B2-REVISED SEPTEMBER 1987
•
8-Bit Counter with Register
•
High-Current 3-State Parallel Register
Outputs Can Drive Up to 15 LSTTL Loads
•
Counter has Direct Clear
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
SN54HC590A ... J PACKAGE
SN74HC590A ... ow OR N PACKAGE
(TOPVIEWI
Os
Oc
VCC
OA
00
G
RCK
CCKEN
CCK
CCLR
RCO
OE
OF
°G
OH
GNO
Dependable Texas Instruments Quality and
Reliability
fI
SN54HC590A ... FK PACKAGE
(TOPVIEWI
description
u
These devices each contain an 8-bit binary
counter that feeds an 8-bit storage register. The
storage register has parallel outputs. Separate
clocks are provided for both the binary counter
and storage register. The binary counter features
a direct clear input CCLR and a count enable
input CCKEN. For cascading a ripple carry output
RCO is provided. Expansion is easily
accomplished for two stages by connecting RCO
of the first stage to CCKEN of the second stage.
Cascading for larger count chains can be
accomplished by connecting RCO of each stage
to CCK of the following stage.
Both the counter and register clocks are positiveedge triggered. If the user wishes to connect
both clocks together, the counter state will
always be one count ahead of the register.
Internal circuitry prevents clocking from the
clock enable.
uccuu«
ddz>d
3
2
1 2019
00
4
18
G
OE
NC
OF
QG
5
17
6
16
RCK
NC
CCKEN
CCK
7
15
B
14
9 10111213
1° r=
:r: Cl U
dzzud
(,!)
"'u
NC-No internal connection
logic symbol t
CTRB
The SN54HC590A is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC590A is
characterized for operation from - 40°C to
85°C.
(15) 0
(1)
A
(2)
(3)
(4)
(5)
(6)
(7)
Os
Dc
00
OE
OF
OG
OH
tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for OW, J, and N packages.
PRODUCTION DATA do.um.nts .ont.in Infarmation
Clrrent I' of publication data. Products conform to
_ilicatiens per the te,.,s .f T.... Instruments
standard warranty. ProductiDa ,roclSling dnal not
.......ril' indado teating of .11 por.maters.
Copyright @ 1982, Texas Instruments Incorporated
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-521
SN54HC590A, SN74HC590A
8·BIT BINARY COUNTERS
WITH 3·STATE OUTPUT REGISTERS
logic diagram (positive logic)
G 1'4)
•
CCK .:..;1'..;.';,.)....._ _ _ _ _ _~
:t
o
s:o
(I)
c
CD
-CC-L-R ,;.1';.;;0.:..)-~
;:.o--1__-~
<
(;'
CD
(II
Pin numbers shown are far OW, J, and N packages.
2-522
TEXAS •
INSTRUMENTS
POST OFFICE BOX 65501 ~ • DALLAS, TEXAS 75265
SN54HC590A. SN74HC590A
8·BIT BINARY CDUNTERS
WITH 3·STATE OUTPUT REGISTERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±35 mA
Continuous current through Vec or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 5: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 105: OW or N package .............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximurn-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN74HC590A
SN54HC590A
MIN
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
vee Supply voltage
VIH
High-level input voltage
Vee
Vee
Vee
Vee
VIL
Low-level input voltage
Vee
Vee
VI
Vo
tt
Input voltage
Output voltage
Input transition (rise and fall) times
Vee
Vee
Vee
TA
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Operating free-air temperature
TEXAS
1.5
3.15
1.5
3.15
4.2
4.2
UNIT
V
V
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
0
Vee
0
Vee
V
0
Vee
1000
0
Vee
1000
V
0
500
0
500
ns
0
400
0
400
-55
125
-40
85
0
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
0
V
°e
2-523
SN54HC590A. SN74HC590A
8·BIT BINARY COUNTERS
WITH 3·STATE OUTPUT REGISTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
VI
VOH
= VIH
VI = VIH
or Vil
VI - VIH
or Vil
VI
VOL
VI = VIH
or Vil
10Z
ICC
ei
= - 2O I'A
10H
4.5 V
6V
~.IOH = -4mA
OA-OH. 10H = -6 rnA
~.IOH = -5.2 rnA
OA-OH.IOH
= VIH or Vil.
VI = VIH
or Vil
II
or Vil.
= 20l'A
10l
~.IOl
= -7.8 rnA
= 4mA
OA-OH. 10l = 6 rnA
ReO. 10l = 5.2 rnA
OA-OH. 10l = 7.8 rnA
VI - Vee or 0
Vo = Vee or 0
VI = Vee or O.
10
TA - 25°C
MIN
TYP MAX
1.9 1.998
4.4 4.499
5.9 5.999
4.5 V
3.98
6V
5.48
3.7
5.80
5.2
V
5.34
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
UNIT
3.84
2V
4.5 V
6V
6V
6V
6V
2 to 6 V
=0
4.30
SN54HC590A SN74HC590A
MIN MAX
MIN MAX
1.9
1.9
4.4
4.4
5.9
5.9
V
0.15
0.26
0.4
0.33
±0.1
±0.01
±loo
±0.5
±1000
±5
nA
80
10
I'A
3
8
10
±1000
±10
160
10
I'A
pF
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
2V
4.5 V
Clock frequency. CCK or RCK
6V
2V
4.5 V
6V
CCK or RCK
high or low
tw
Pulse duration
cern low
~Iow
before CCKt
tsu
Setup time
cern high (inactive)
before CCKt
ClKt before RCKt
(see Note 1)
th
Hold time
caO
3
description
OE
NC
OF
OG
These devices each contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit Dtype storage register. Separate clocks and directoverriding clears are provided on both the shift
and storage registers. A serial output (QH') is
provided for cascading purposes.
Both the shift register and storage register clocks
are positive-edge triggered. If the user wishes to
connect both clocks together, the shift register
will always be one count pulse ahead of the
storage register.
The parallel outputs (QA thru 0H) have highcurrent capability; output 0H' is a standard
output.
2 1 2019
SER
RCLR
NC
RCK
SRCK
18
4
5
00
6
17
16
8
14
15
9 1011 1213
:c15
:I: Cl u
ozzOu
o
II:
If)
NC - No internal connection
tContact the factory for 0 availability.
logic symbol
*
The SN54HC594 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC594 is
characterized for operation from - 40°C to 85°C.
(151
(11
(21
(31
°A
Os
Oc
141 °D
Oe
(51
OF
(61
20 [>
3
(71 °G
(91
OH
°H'
~This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
PRODUCTION DATA documentl contein information
current a. 01 publication date. Products conform to
.peciflcati... per th. terms of Tex•• Instruments
=~;:i~li:I~7i ~~::i:r :.r::;:~:.:~~s not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
Copyright @ 1989, Texas Instruments Incorporated
2-527
SN54HC594, SN74HC594
8·BIT SHIFT REGISTERS WITH OUTPUT REGISTERS
logic diagram (positive logic)
II
:::t
(")
s:
o
rn
c
CD
<
c;'
CD
(I)
Pin numbers shown on logic notation are for D, J, and N packages.
2-528
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75266
SN54HC594, SN74HC594
8·BIT SHIFT REGISTERS WITH OUTPUT REGISTERS
absolute maximum ratings over operating free·air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ............................. ±20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±35 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1116 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ............... 260°C
Storage temperature range ........................... " ...... '" ... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute·maximum-rated conditions for extended periods may affect device reliability.
fI
tn
CI)
U
'>
recommended operating conditions
CI)
Vee Supply voltage
High-level input voltage
Vee
Vee
VIL
Low-level input voltage
Vee
Vee
Vee
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
VIH
Vee
Vee
Vee
Vee
TA
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Operating free-air temperature
TEXAS
SN54HC594
MIN NOM MAX
SN74HC594
MIN NOM MAX
2
1.5
3.15
4.2
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-55
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5
6
5
6
UNIT
o
V
o
:i!
:t:
0
0
0
0.3
0.9
1.2
V
Vee
Vee
1000
500
400
125
0
0
Vee
Vee
1000
500
400
V
V
85
CI)
V
0.3
0.9
1.2
0
0
0
-40
c
n.
°e
2-529
SN54HC594, SN74HC594
8~BIT SHIFT REGISTERS WITH OUTPUT REGISTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
VOH
II
o
VOL
(I)
2-530
=
II
ei
=
-20
~A
0H'; 10H = -4 rnA
OA-OH,IOH = -6 rnA
0H',IOH = -5.2 rnA
OA-OH,IOH
VIH or VIL,
VI = VIH
or VIL
VI = VIH
or VIL
IOZ
ICC
10H
2V
4.5 V
6V
VI = VIH
or VIL
VI
t/)
c
CD
<
n'
CD
VIH or VIL,
VI = VIH
or VIL
:J:
s:o
=
VCC
IOL
=
=
-7.8 rnA
= 4 rnA
OA-OH, 10L = 6 rnA
0H', 10L = 5.2 rnA
0A·OH, 10L = 7.8 rnA
VI = Vee orO
Vo = Vee or 0
VI = Vee or 0,
10
=0
SN54HC594
MIN
1.9 1.998
4.4 4.499
1.9
4.4
5.9 5.999
MAX
SN74HC594
MIN
MAX
5.9
5.9
3.98
4.30
3.7
3.84
6V
5.48
5.80
5.2
5.34
V
6V
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
6V
6V
6V
2 to 6 V
TEXAS
UNIT
1.9
4.4
4.5 V
2V
4.5 V
20 ~
0H', IOL
TA - 25°C
TYP MAX
MIN
V
0.15
0.26
0.4
0.33
±0.1
±100
±1000
nA
±0.01
±0.5
8
10
±10
160
±1000
±5
80
10
~A
3
"!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
10
~
pF
SN54HC594. SN74HC594
8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
Vee
fclock
SRCK or RCK
high or low
tw
Pulse duration
SRClR or RClR low
SER before SRCKt
SRCKt before
RCKt Isee Note 11
tsu
Setup time
SRClR low
before RCKt
SRClR high linactivel
before SRCKt
RClR high linactivel
before SRCK t
th
Hold time
6V
a
a
a
2V
4.5 V
Clock frequency, SRCK or RCK
SER after SRCKt
TA = 25°C
MIN
MAX
SN54HC594
SN74HC594
MIN
MAX
MIN
MAX
3.3
29
0
20
a
a
a
4
25
a
a
5
17
2V
100
20
150
. 30
125
4.5 V
6V
17
25
21
25
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
4.5 V
90
18
135
27
110
22
6V
15
23
19
2V
90
135
110
4.5 V
18
27
22
6V
15
23
19
2V
4.5 V
50
10
75
15
63
13
6V
9
13
11
2V
20
20
20
4.5 V
10
10
10
6V
10
10
10
2V
5
5
5
4.5 V
5
5
5
6V
5
5
5
2V
5
5
5
4.5 V
5
6V
5
5
5
5
5
20
UNIT
MHz
24
ns
PI
ns
ns
ns
ns
ns
ns
ns
Note 1: This setup time ensures the output register will see stable data from the shift-register outputs. The clocks may be tied together
in which case the output register will be one clock pulse behind the shift register.
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-531
SN54HC594, SN74HC594
B-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 2)
FROM
(INPUT)
SRCK
or
RCK
TO
(OUTPUT)
tpd
SRCK
QH'
tpd
RCK
QA
thru
QH
PARAMETER
f max
E
:t
o
oen
s::
tpHL
SRCLR
QH'
C
tpHL
iiCIR
QA
thru
QH
n"
CD
tt
QH'
tt
QA
thru
QH
~
en
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Power dissipation capacitance
TA = 25°C
MIN
TYP MAX
5
8
25
35
29
40
50
150
20
30
15
25
50
150
20
30
15
25
50
150
20
30
15
25
50
125
20
25
15
21
38
75
8
15
13
6
38
60
12
8
6
10
No load, TA
=
SN54HC594
MIN MAX
3.3
17
20
225
45
38
225
45
38
225
45
38
185
37
31
110
22
19
90
18
15
25°C
SN74HC594
MIN MAX
4
20
24
185
37
31
185
37
31
185
37
31
155
31
26
95
19
16
75
15
13
UNIT
MHz
ns
ns
ns
ns
ns
ns
395 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 2)
PARAMETER
tpd
tpHL
tt
FROM
(INPUT)
RCK
iiCIR
TO
(OUTPUT)
QA
thru
QH
QA
thru
QH
QA
thru
QH
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
TYP MAX
90
200
23
40
19
34
200
90
23
40
19
34
45
210
17
42
13
36
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
2·532
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN54HC594
MIN MAX
300
60
51
300
60
51
315
63
53
SN74HC594
MIN MAX
250
50
43
250
50
43
265
53
45
UNIT
ns
ns
ns
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
02684, DECEMBER 1982-REVISED JUNE 1989
•
8-Bit Serial-In. Parallel-Out Shift
•
High-Current 3-State Outputs Can Drive Up
to 15 LSTTL Loads
•
Shift Register has Direct Clear
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
SN54HC595 ... J PACKAGE
SN74HC595 ... ot OR N PACKAGE
(TOP VIEW)
OB
•
VCC
OA
SER
Oc
OD
OE
OF
G
RCK
SRCK
SRCLR
OG
OH
GND
Dependable Texas Instruments Quality and
Reliability
Ow
SN54HC595 ... FK PACKAGE
(TOP VIEW)
description
These devices each contain an a-bit serial-in.
parallel-out shift register that feeds an a-bit Dtype storage register. The storage register has
parallel 3-state outputs. Separate clocks are
provided for both the shift register and storage
register. The shift register has a direct-overriding
clear. serial input. and serial output pins for
cascading.
U
UtDU U «
OOZ>O
3
1 2019
18
6
16
SER
17
8
Both the shift register and storage register clocks
are positive-edge triggered. If the user wishes to
connect both clocks together. the shift register
state will always be one clock pulse ahead of the
storage register.
The SN54HC595 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC595 is
characterized for operation from - 40°C to a5°C.
2
4
5
15
NC
RCK
14
SRCK
9 1011 12 13
I O U :CIa:
ozzod
(!l
a:
(J)
NC - No internal connection
t Contact the factory for 0 availability.
logic symbol1'
115)
(1) QA
(2) QB
(3) Qc
(4) Qo
(5) QE
(6) QF
(7) QG
20[> 3'V
(9) QH
QH'
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
PROOUCTIOI DATA documlnts.ontoin informltion
cu"••t H 01 publi.ation date. Products .onllrm to
_illcali... par thl tor... 01 TI..I Instrumonts
:=~I~ai:'"::i =:~i:; :'l"::"':::~~~1 not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1989, Texas Instruments Incorporated
2-533
SN54HC595, SN74HC595
8·BIT SHIFT REGISTERS WITH 3·STATE OUTPUT REGISTERS
logic diagram (positive logic)
G (13)
RCK
5RCLR
SRCK
E
J:
(")
:s:
oen
c
CD
<
c;'
CD
tI)
SER
~
(12)
~
(11)
(14)
~+
.....--
3R
10
~p.C3
Cl
~
[S~
---~+
35
1
3R
2R
(1)
~>C3
C2
~
~~
35
~+
3R
~
C2
L-
--
1
2R
[S~
1
(2)
--35
~+
(3)
00
~I>C3
C2
L-
[S~
1
35
L..-
~+
3R
2R
(4)
~P.C3
C2
l!.-
[S~
35
I......-
I
~+
3R
2R
(S)
~P.C3
C2
~
~'2S
1
~2S
2R
C2
L!L-
(6)
~P.C3
C2
L!!...-
---~~
35
3R
2R
1
Oc
C3
3R
2R
3S
I......-
.---
(7)
3R
L-c I>C3
3S
L..-
(9)
-v
Pin numbers shown are for D, J, and N packages.
2·534
(1S)
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC59i SN74HC595
8·BIT SHIFT REGISTERS WITH 3·STATE OUTPUT REGISTERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum·rated conditions for extended periods may affect device reliability.
U)
CI)
U
'S;
recommended operating conditions
SN54HC595
Vee Supply voltage
VIH
VIL
High·level input voltage
Low·level input voltage
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and 'all) times
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
Operating free-air temperature
NOM
MAX
MIN
NOM
MAX
2
1.5
3.15
4.2
5
6
2
1.5
3.15
4.2
5
6
0
Vee = 6 V
0
0
0
0
Vee = 6 V
TA
MIN
Vee = 2 V
Vee = 4.5 V
Vee = 2 V
Vee = 4.5 V
CI)
SN74HC595
0
0
0
-55
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
C
V
o
V
CJ
0
0
0.3
0.9
1.2
0
1.2
Vee
Vee
1000
500
400
0
0
Vee
vee
1000
V
V
500
400
85
ns
125
:l:
:r::
0.3
0.9
0
0
0
-40
fJ)
V
°e
2·535
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
VOH
E
:::t
s:
VOL
oen
c
C\)
II
<
,;"
10Z
ICC
Ci
C\)
en
VIH or VIL,
=
10H
-20
~A
2V
4.5 V
6V
VI = VIH
or VIL
QH" IOH = -4 mA
QA-QH, IOH = -6 mA
VI = VIH
or VIL
QH',IOH = -5.2 mA
QA-QH, 10H = -7.8 mA
VI
(")
=
VCC
=
VIH or VIL,
VI - VIH
or VIL
10L
=
1.9 1.998
4.4 4.499
5.9 5.999
QA-QH, 10L = 6 mA
QH" 10L = 5.2 mA
VI = VIH
QA-QH, 10L - 7.8 mA
or VIL
VI = VCC or 0
SN74HC595
MIN MAX
1.9
4.4
5.9
1.9
4.4
5.9
3.98
4.30
3.7
3.84
6V
5.48
5.80
5.2
5.34
0.1
0.1
0.1
6V
0.1
0.1
0.1
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
6V
±0.1
±0.01
±100
±0.5
±1000
±5
3
8
10
±1000
±10
160
2 to 6 V
80
10
10
UNIT
V
0.002
0.001
0.001
6V
10 - 0
SN54HC595
MIN MAX
4.5 V
2V
4.5 V
20 ~A
QH" 10L - 4 mA
Vo = VCC or 0
VI = Vec or 0,
TA - 25°C
MIN
TYP MAX
V
nA
~A
~
pF
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
Vee
fclack
2V
4.5 V
Clock frequency, SRCK
6V
2V
SRCK or RCK
high or low
tw
4.5 V
6V
2V
4.5 V
Pulse duration
S'RC'[R low
6V
2V
SER before SRCK I
4.5 V
6V
2V
4.5 V
SRCK I before
RCK I Isee Note 11
tsu
6V
2V
Setup time
SRCi:R low
before RCKI
S'RC'[R high (inactive I
before SRCK I
th
Hold time
SER after SRCK I
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MAX
MIN
0
0
0
80
16
14
80
16
14
100
20
17
75
15
13
50
10
6
31
36
SN54HC595
MIN MAX
0
0
0
120
24
20
120
24
20
150
30
25
113
23
19
75
15
4.2
21
25
SN74HC595
MIN MAX
0
5
0
0
100
20
17
100
20
MHz
ns
ns
17
125
25
21
94
ns
19
ns
16
65
13
ns
9
50
13
75
10
9
0
15
13
11
60
12
11
0
0
0
0
0
0
0
0
25
29
UNIT
ns
ns
Note 1: This setup time ensures the output register will see stable data from the shift-register outputs. The clocks may be tied together
in which case the output register will be one clock pulse behind the shift register.
2-536
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC595. SN74HC595
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
SRCK
°H'
tpd
SRCK
°H'
tpd
RCK
OA
to
OH
tpHL
SRCLR
ten
G
tdis
G
°H'
OA
to
OH
°A
to
OH
OA
to
QH
tt
QH'
tt
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN
TYP MAX
26
6
31
38
36
42
50
160
17
32
14
27
50
150
17
30
14
26
51
175
18
35
15
30
40
150
15
30
13
26
42
200
40
23
20
34
28
60
8
12
6
10
28
75
8
15
13
6
No load, TA
Power disSipation capacitance
~
SN54HC595
MIN MAX
4.2
21
25
240
48
41
225
45
38
261
52
44
225
45
38
300
60
51
90
18
15
110
22
19
25°C
SN74HC595
MIN MAX
5
25
29
200
40
34
187
37
32
219
44
37
187
37
32
250
50
43
75
15
13
95
19
16
UNIT
MHz
EI
ns
ns
U)
Q)
U
'S;
ns
Q)
c
en
ns
o
:e
(..)
ns
:::c
ns
ns
400 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 150 pF (see Note 2)
PARAMETER
tpd
ten
tt
FROM
(INPUT)
RCK
G
TO
(OUTPUT)
OA
to
°H
OA
to
OH
OA
to
OH
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN
TYP MAX
60
200
22
40
19
34
70
200
23
40
19
34
45
210
17
42
13
36
SN54HC595
MIN MAX
300
60
51
298
60
51
315
63
53
SN74HC595
MIN MAX
250
50
43
250
50
43
265
53
45
UNIT
ns
ns
ns
NOTE 2: load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-537
:I:
(")
3:
oen
c
n'
CD
CD
<
CI)
2·538
SN54HC620, SN54HC623, SN74HC620, SN74HC623
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
02684. DECEMBER 1982-REVISED SEPTEMBER 1987
SN54HC' •.. J PACKAGE
SN74HC' ... OW or N PACKAGE
•
Lock Bus-Latch Capability
•
Choice of True or Inverting Logic
•
High·Current 3·State Outputs Can Drive Up
to 15 LSTTL Loads
(TOPVIEWI
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
I
I
DEVICE
Vee
GA6
A1
A2
A3
A4
A5
A6
A7
A8
GND
G6A
61
62
63
64
65
66
67
68
II
LOGIC
'HC620
Inverting
'HC623
True
SN54HC' .•. FK PACKAGE
(TOPVIEWI
~ ~ ~;;1
««(!»I(!)
description
N
These octal bus transceivers are designed for
asynchronous two-way communication
between data buses. The control function
implementation allows for maximum flexibility in
timing.
These devices allow data transmission from the
A bus to the B bus or from the B bus to the A
bus depending up'on the logic levels at the enable
inputs (GBA and GAB.)
3
A3
A4
A5
A6
2
1 2019
4
18
5
17
6
16
7
15
14
61
62
63
64
65
9 1011 12 13
00000 ... '"
«zoo"''''
(!)
The enable inputs can be used to disable the
device so that the buses are effectively isolated.
The dual-enable configuration gives these
devices the capability to store data by
simultaneous enabling of GBA and GAB; Each
output reinforces its input in this transceiver
configuration. Thus when both control inputs are
enabled and all other data sources to the two
sets of bus lines are at high impedance, both sets
of bus lines (16 in all) will remain at their last
states. The 8-bit codes appearing on the two
sets of buses will be identical for the 'HC623 or
complementary for the 'HC620.
The SN54HC620 and SN54HC623 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HC620 and SN74HC623 are characterized
for operation from -40°C to 85°C.
PRODUCTION DATA d••uments ••ntai. inf.....ti••
.urrant '" of publi••ti•• dill. Products eonform to
.p..iIi.ltions PII thl tor... of T.... Instruments
=":~~~·i~~~7.;
=::i: :.r:.:=~:~
nil
Copyright © 1982, Tex,as Instruments Incor~?rated
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-539
SN54HC620. SN54HC623. SN74HC620. SN74HC623
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
FUNCTION TABLE
ENABLE INPUTS
GSA
L
GAB
L
H
H
H
L
l
H
OPERATION
'HC620
A data to B bus
Isolation
Isolation
B data to A bus,
A data to B bus
IOgi~ symbols t
•
'HC623
B data to A bus
B data to A bus
A data to B bus
B data to A bus,
A data to B bus
'HC620
:r:
'HC623
n
3:
o
til
oCD
<
5"
CD
(II
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
logic diagrams (positive logic)
'HC620
'HC623
GBA---- Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Va < 0 or Va > Vcc) ............................. ± 20 mA
Continuous output current, 10 (Va = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package .............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under uabsolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
High-level input voltage
VIH
Vee
Vee
Vee
Low-level input voltage
VIL
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Vo
Vee
Input transition (rise and fall) times
tt
Vee
Vee
UNIT
MAX
MIN
NOM
MAX
2
5
6
2
1.5
5
6
1.5
3.15
3.15
4.2
4.2
=2V
= 4.5 V
=6V
V
V
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
0
0
Vee
0
0
Vee
V
Vee
1000
V
n.
Vee
1000
0
Operating free-air temperature
TA
SN74HC623
NOM
Input voltage
Output voltage
VI
SN74HC620
SN54HC623
MIN
Vee Supply voltage
Vee
Vee
SN54HC620
0
0
500
0
500
0
400
0
400
-55
125
-40
B5
V
De
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
TA - 25°C
TYP
MIN
VI
=
VIH or VIL.
10H
=
-20
VI
=
=
VIH or VIL,
10H
-6 rnA
VIH or VIL.
IOH
=
=
~A
6V
VOH
VI
VI ~ VIH or VIL.
10L
=
-7.B rnA
20 pA
VOL
= VIH or VIL, 10L =
VI = VIH or VIL. 10L =
VI = Vee or 0
Vo = Vee or 0
VI = Vee or O. 10 = 0
VI
II
IGAB arGBA
10ziA or B
lee
ei I GAB or GBA
2V
4.5 V
6 rnA
7.B rnA
MAX
1.9 1.99B
4.4 4.499
SN54HC620
SN74HC620
SN54HC623
SN74HC623
MIN
MAX
1.9
4.4
MIN
1.9
4.4
5.9 5.999
5.9
5.9
4.30
3.7
3.B4
4.5 V
3.98
6V
5.4B
5.BO
UNIT
MAX
5.2
V
5.34
2V
4.5 V
0.002
0.1
0.1
0.1
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
4.5 V
0.17
0.1
0.26
0.4
0.33
V
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
6V
±0.01
±0.5
±10
±5
pA
B
160
BO
~A
10
10
10
pF
6V
2 to 6 V
TEXAS
3
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-541
SN54HC620. SN54HC623. SN74HC620. SN74HC623
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
FROM
(lNPUTI
TO
(OUTPUT)
tpd
A or B
B or A
ten
GBA
A
~
tdis
GBA
A
t/)
ten
GAB
B
tdis
GAB
B
PARAMETER
s::
o
c
CD
<
C:;'
CD
en
A or B
tt
TA = 25°C
VCC
MIN
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V·
SV
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Power dissipation capacitance per transceiver
TYP
29
10
B
112
27
20
40
18
IS
112
27
20
40
18
16
20
8
6
MAX
105
21
18
210
42
36
150
30
26
210
42
36
150
30
26
60
12
10
SN54HC620
SN54HC623
M(N MAX
160
32
27
315
63
54
225
45
38
315
63
54
225
45
38
90
18
15
No load, TA = 25°C
SN74HC620
SN74HC623
MIN MAX
130
26
22
265
53
45
190
38
32
265
53
45
190
38
32
75
15
13
UNIT
ns
ns
ns
n.
n.
ns
40 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
ten
GBA
A
ten
GAB
B
PARAMETER
tt
A or B
TA = 25°C
VCC
MIN
2V
4.5 V
6'V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TYP
44
14
11
130
31
23
130
31
23
45
17
13
MAX
135
27
23
270
54
46
270
54
46
210
42
36
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
2-542
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TeXAS 75265
SN54HC620
SN54HC623
MIN MAX
200
40
34
405
81
69
405
81
69
315
63
53
SN74HC620
SN74HC623
MIN MAX
170
34
29
335
67
56
335
67
56
265
53
45
UNIT
ns
ns
n.
n.
SN54HCT620, SN54HCT623, SN74HCT620, SN74HCT623
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
02804, MARCH 1984-REVISED SEPTEMBER 1987
SN54HCT' ... J PACKAGE
SN74HCT' ... ow 0' N PACKAGE
•
Inputs are TTL-Voltage Compatible
•
Lock Bus-Latch Capability
•
Choice of True or Inverting Logic
•
High-Current 3-State Outputs Can Drive Up
to 15 LSTTL Loads
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEW)
Vee
GA6
A1
A2
A3
A4
A5
A6
A7
A8
GND
LOGIC
G6A
61
62
63
64
65
66
67
68
II
SN54HCT' ... FK PACKAGE
(TOP VIEW)
Inverting
True
OJ
N~I(!)
description
3
These octal bus transceivers are designed for
asynchronous two-way communication
between data buses, The control function
implementation allows for maximum flexibility in
timing.
A3
A4
A5
A6
A7
These devices allow data transmission from the
A bus to the B bus or from the B bus to the A
bus depending upon the logic levels at the enable
inputs (GBA and GAB.)
2
1 2019
4
18
5
17
6
16
7
15
8
14
61
62
63
64
65
9 10"1213
tooto"''''
Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through Vee or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1 ,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package .............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum·rated conditions for extended periods may affect device reliability.
I
U)
CD
U
os:
recommended operating conditions
CD
SN54HCT620
SN54HCT623
vee Supply voltage
V,H High-level input voltage
V,L Low-level input voltage
I Vee
I Vee
C
SN74HCT620
SN74HCT623
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
V
V
O.B
V
= 4.5 V to 5.5 V
2
= 4.5 V to 5.5 V
0
2
:E
(.)
0.8
0
Vee
V
Vee
500
ns
85
°e
V,
Input voltage
0
vee
0
0
Vo
Output voltage
0
tt
Input transition (rise and falll times
0
Vee
500
TA
Operating free-air temperature
-55
125
0
-40
CI)
o
%:
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
notedl
PARAMETER
VI = V,H or V'L,
VOH
VOL
"
10Z
V, = V,H or V'L,
VCC
10H = -20 ItA
10H = -6 mA
V, - V,H or V'L,
10l - 20 "A
V, = V,H or V'l, IOl=6mA
GA8 or l;SA V, = Vee or 0
A or B
V, - Vee or GND
V, = Vee or 0, 10 = 0
One input at 0.5 V or 2.4 V
Ice
.1lee*
ei
TEST CONDITIONS
Other inputs at 0 V or Vee
GAB orG8A
4.5 V
4.5 V
4.5 V
SN54HCT620 SN74HCT620
TA - 25°C
MIN
TYP
4.4 4.499
3.98
SN54HCT623 SN74HCT623 UNIT
MAX
MAX
4.4
0.1
MIN
MAX
4.4
3.7
4.30
0.001
MIN
V
3.84
0.1
0.1
V
4.5 V
0.17
0.26
0.4
0.33
5.5 V
±0.1
±100
±1000
±1000
nA
5.5 V
±0.01
±0.5
±10
±5
B
160
80
ItA
ItA
1.4
2.4
3.0
2.9
mA
3
10
10
10
pF
5.5 V
5.5 V
4.5 to
5.5 V
:tThis is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
Vee.
2-545
SN54HCT620, SN54HCT623, SN74HCT620, SN74HCT623
OCTAL BUS TRANSCEIVERS WITH3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
FROM
(INPUT)
TO'
(OUTPUT)
tpd
A or 8
B or A
ten
'GBA
A
PARAMETER
E
tdis
GBA
A
ten
GAB
B
tdis
GA8
B
A or 8
tt
VCC
SN54HCT620 SN74HCT620
TA = 25°C
MIN
4.5 V
5.5 V
4.5 V
TYP
15
MAX
22
20
42
13
30
23
18
5.5 V
4.5 V
5.5 V
4.5 V
28
42
30
23
18
5.5 V
4.5 V
5.5 V
38
30
16
9
28
12
11
8
Power dissipation capacitance per transceiver
33
30
63
57
45
38
30
16
5.5 V
4.5 V
SN54HCT623 SN74HCT623
MIN MAX
MIN MAX
28
25
53
48
38
35
42
63
57
45
53
48
38
42
18
35
15
16
14
No load, TA = 25°C
UNIT
ns
ns
ns
ns
ns
ns
40 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
ten
GBA
A
ten
GAB
B
tt
A or B
VCC
MIN
4.5V
5.5 V
4.5 V
5.5
4.5
5.5
4.5
V
V
V
V
5.5 V
SN54HCT620 SN74HCT620
TA = 25°C
TYP
18
11
MAX
38
34
36
30
36
59
53
59
30
17
14
53
42
38
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
2-546
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75266
SN54HCT623 SN74HCT623
MIN MAX
MIN MAX
58
47
52
42
89
74
80
89
80
63
57
67
74
67
53
48
UNIT
ns
ns
ns
ns
SN54HC640. SN54HC643. SN54HC645
SN74HC640. SN74HC643. SN74HC645
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
02684, DECEMBER 1982-REVISED JUNE 1989
SN54HC' , , . J PACKAGE
SN74HC' ... OW DR N PACKAGE
•
Choice of True or Inverting Logic
•
High·Current 3·State Outputs Can Drive Up
to 15 LSTTL Loads
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
(TDP VIEW)
Inverting
'HC643
True and Inverting
'HC645
True
G
A1
A2
A3
A4
A5
A6
A7
A8
Dependable Texas Instruments Quality and
Reliability
DEVICE
'HC640
Vee
DIR
LOGIC
B1
B2
B3
B4
B5
B6
B7
B8
GND
II
I/)
G)
(J
oS;
SN54HC' ... FK PACKAGE
G)
(TOP VIEW)
description
N
~ !!:
3
2
Q
en
tl
o
1<.:)
These octal bus transceivers are designed for
asynchronous two-way communication
between data buses. The devices transmit data
from the A bus to the B bus or from the B bus
to the A bus depending upon the level at the
direction control (DIR) input. The enable input (G)
can be used to disable the device so the buses
are effectively isolated.
A3
A4
A5
A6
A7
:iE
1 2019
18
4
5
17
6
16
8
14
15
CJ
::I:
81
B2
B3
B4
B5
9 1011 12 13
CDQCOr---CO
The
SN54HC640.
SN54HC643,
and
SN54HC645 are characterized for operation
over the full military temperature range of
- 55°C to 125°C, The SN74HC640,
SN74HC643,
and
SN74HC645
are
characterized for operation from - 40°C to
85°C.
Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package. . . . . . . . . . . . .. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxirnum-rated conditions for extended periods may affect device reliability.
fI
recommended operating conditions
SN54HC640
SN74HC640
SN54HC643
SN74HC643
SN54HC645
NOM
MAX
2
5
6
Vee Supply voltage
Vee
VIH High-level input voltage
Vee
Vee
Vee
Low-level input voltage
VIL
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
UNIT
SN74HC645
MIN
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
V
V
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
V
VI
Input voltage
0
Vee
0
vee
v
Vo
Output voltage
0
0
Vec
1000
V
0
Vee
1000
tt
Input transition (rise and fall} times
0
500
0
500
n.
0
400
0
400
-55
125
-40
85
Vee
Vee
Vee
=2V
= 4.5 V
=6V
Operating free-air temperature
TA
0
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TA - 25°C
VCC
MIN
2V
1.9 1.998
1.9
1.9
-20,.A
4.5 V
4.4 4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
VI
=
=
VIH or VIL,
IOH
-6 rnA
4.5 V
3.98
4.30
3.7
3.84
VIH or VIL,
IOH
=
=
6V
5.48
=
VIH or VIL,
10L
=
= VIH or VIL,
VI = VIH or VIL,
VI = Vee or 0
Vo = Vee or 0
10L
-7.8 rnA
20,.A
IOL
= 6 rnA
= 7.8 rnA
VI - Vee or 0, 10 - 0
DIRorG
MIN
=
VI
I
MAX
IOH
VOL
ICC
ei
SN74HC645
MIN
VIH or VIL,
VI
lozlAorB
SN74HC643
SN54HC645
=
VI
JDIRorG
MAX
SN74HC640
SN54HC643
VI
VOH
II
TYP
SN54HC640
5.80
5.2
UNIT
MAX
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
V
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
6V
±0.01
±0.5
±10
±5
!LA
8
160
80
3
10
10
10
p.A
pF
6V
2 to 6 V
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-549
SN54HC640, SN74HC640
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
::z::
FROM
(INPUT)
TO
COUTPUT)
tpd
Aor B
BorA
ten
G
A or B
tdis
G
Aor B
(')
!:
o(I)
c~
=
A or 8
tt
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Power dissipation capacitance per transceiver
TA - 25°C
MIN
TYP MAX
29
105
21
10
8
18
109
230
27
46
20
39
40
150
18
30
16
26
20
60
12
8
6
10
SN54HC640
MIN MAX
160
32
27
340
68
58
225
45
38
90
18
15
No load, TA = 25·C
SN74HC640
MIN MAX
130
26
22
290
58
49
190
38
32
75
15
13
UNIT
ns
ns
ns
ns
40 pF typ
C;" switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
IOUTPUT)
tpd
AorB
BorA
ten
G
A or B
tt
A or B
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN
TYP MAX
44
190
14
38
11
33
124
315
31
63
23
54
45
210
17
42
13
36
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-550
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
SN54HC640
MIN MAX
290
58
49
470
94
80
315
63
53
SN74HC640
MIN MAX
235
47
41
395
79
68
265
53
45
UNIT
ns
ns
ns
SN54HC643, SN74HC643
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
switching ch.r.cteristics over recommended oper.ting fr..·.ir temper.ture range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
IINPUT'
TO
IOUTPUTI
tpd
A or B
BorA
ten
<;
Aor 8
leIi.
<;
AorB
A or 8
tt
vCC
2V
4.5 V
6V
2V
4.5V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Power dissipation capacitance per transceiver
TA - 25°C
MIN
TVP MAX
29
110
10
22
8
19
109
230
46
27
20
39
40
150
18
30
16
26
20
60
12
8
10
6
SN54HC843
MIN MAX
165
33
2B
340
6B
58
225
45
38
90
18
15
No load, TA = 25°C
SN74HC643
MIN MAX
140
28
24
290
58
49
190
38
32
75
15
13
UNIT
ns
II
n.
ns
ns
40 pF typ
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL - 150 pF (see Note 1)
FROM
TO
(INPUT'
(OUTPUT'
tpd
Aor8
8 or A
ten
<;
A or B
PARAMETER
tt
Aor B
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN
TVP MAX
44
195
14
39
11
34
315
124
31
63
54
23
210
45
17
42
13
36
SN54HC643
MIN MAX
295
59
50
470
94
80
315
63
53
SN74HC643
MIN MAX
245
49
43
395
79
68
265
53
45
UNIT
ns
n.
ns
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OffiCE BOX 655012· DALLAS, TEXAS 75265
2-551
SN54HC645, SN74HC645
OCTAL BUS TRANSCEIVERS WITH 3-STATEOUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
•
::J:
FROM
(lNPUTI
TO
(OUTPUn
tpd
A or B
B or A
ten
G
A or B
tdi.
G
A or B
C')
s::
oen
c
CD
Cpd
<
c;"
CD
tn
Aor B
tt
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
SN64HC646
MIN MAX
160
32
27
340
68
58
300
60
51
90
18
15
TA - 26°C
TVP MAX
MIN
105
40
15
21
12
18
125
230
23
46
20
39
74
200
25
40
21
34
20
60
8
12
6
10
No load. TA
Power dissipation capacitance per transceiver
=
25°C
SN74HC646
MIN MAX
130
26
22
290
58
49
250
50
43
75
15
13
UNIT
ns
n.
n.
ns
40 pF tvp
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL -150 pF (see Note 1)
PARAMETER
FROM
(lNPUTI
TO
(OUTPUn
tpd
A or B
B or A
ten
G
A or B
tt
A or B
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN
TVP MAX
135
54
18
27
15
23
150
270
54
31
25
46
45
210
17
42
13
36
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
2-552
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN64HC645
MIN MAX
200
40
34
405
81
69
315
63
53
SN74HC645
MIN MAX
170
34
29
335
67
56
265
53
45
UNIT
ns
ns
ns
SN54HCT640, SN54HCT643, SN54HCT645
SN74HCT640, SN74HCT643, SN74HCT645
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
02804, MARCH 1984-REVISED SEPTEMBER 1987
•
SN64HCT' ••• J PACKAGE
SN74HCT' ... OW OR N PACKAGE
(TOPVIEWI
Inputs are TTL-Voltage Compatible
•
Choice of True or Inverting Logic
•
High-Current 3-State Outputs Can Drive Up
to 15 LSTTL Loads
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mll
DIPs
•
Dependable Texas Instruments Quality and
Reliability
DEVICE
'HCT640
'HCT643
'HCT645
Vce
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
LOGIC
Inverting
True and Inverting
True
G
B1
B2
B3
B4
B5
B6
B7
B8
•
SN54HCT' ... FK PACKAGE
(TOPVIEWI
l3
N ~ !!:
««O>IC!l
description
3
These octal bus transceivers are designed for
asynchronous two-way communication
between data buses. The devices transmit data
from the A bus to the B bus or from the B bus
to the A bus depending upon the level at the
direction control (DIR) input. The enable input (<3)
can be used to disable the device so the buses
are effectively isolated.
A3
A4
A5
A6
A7
2
1 2019
4
18
5
17
6
16
15
14
8
B1
B2
B3
B4
B5
9 1011 1213
00000 ..... '"
«zCIJCIJCIJ
C!l
The SN54HCT640, SN54HCT643, and
SN54HCT645 are characterized for operation
over the full military temperature range of
- 55 DC to 125 DC. The SN74HCT640,
SN74HCT643 and SN74HCT645 are
characterized for operation from - 40 DC to
85 D C.
FUNCTION TABlE
CONTROL
INPUTS
G DIR
L
L
L
H
X
H
OPERATION
'HCT640
'HCT643
'HCT645
B data to A bus
B data to A bus
A data to B bus
Isolation
B data to A bus
A data to B bus
Isolation
A data to B bus
Isolation
PRODUCTIO. DATA doc....... call1lin infarmlti••
carrant II of publlcotlDn dIlL Prodo_ calllm to
IIo.III.....f T.... I.ItrtIII_
~Dn,..
=,,:;~:ra =:~: ~ro:=:~ lOt
Copyright @ 1984, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-553
SN54HCT640, SN54HCT643, SN54HCT645
SN74HCT640, SN74HCT643, SN74HCT645
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
logic symbols t
'HCT645
'HCT643
'HCT640
CIR
CIR
DlR
A1
B1
A1
B1
A1
B1
A2
B2
A2
B2
A2
B2
A3
B3
:J:
B3
B3
B4
B4
(")
s:
B4
A5
B5
A5
B5
A5
B5
en
AS
B6
A6
B6
A6
B6
C
A7
B7
A7
B7
A7
B7
<
A8
B8
A8
B8
A8
88
0
CD
(=)'
CD
U)
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
logic diagrams (positive logic)
'HCT640
'HCT643
.,
'HCT645
G-----,
G-----,
G-----,
DIR-+----'
DIR4---.J
DIR-+---~
A1
B1
TO SEVEN OTHER TRANSCEIVERS
2-554
B1
A1
TO SEVEN OTHER TRANSCEIVERS
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
A1
B1
TO SEVEN OTHER TRANSCEIVERS
SN54HCT640, SN54HCT643, SN54HCT645
SN74HCT640, SN74HCT643, SN74HCT645
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K (Va < 0 or Va > Vee) ............................. ± 20 rnA
eontinuous output current, 10 (Va = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 rnA
eontinuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300 0 e
Lead temperature 1,6 mm (1116 in) from case for 10 s: DW or N package ...... " ...... 260 0 e
Storage temperature range ......................................... - 65 °e to 150 °e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
fI
recommended operating conditions
Vee Supply voltage
VIH High-level input voltage
I Vee
I Vee
VIL
Low-level input voltage
VI
Input voltage
Vo
Output voltage
tt
TA
Input transition (rise and fall) times
SN54HCT640
SN74HCT640
SN54HCT643
SN74HCT643
SN54HCT645
SN74HCT645
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
= 4.5 V to 5.5 V
Operating free-air temperature
V
2
2
0
0
0
0
-55
= 4.5 V to 5.5 V
UNIT
V
0.8
0
0.8
V
Vee
0
Vee
V
Vee
500
0
0
Vee
500
ns
125
-40
85
°e
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
SN54HCT640 SN74HCT640
PARAMETER
TEST CONDITIONS
vCC
= 25°C
TA
MIN
VI
VOH
VI
VI
VOL
II
10Z
I
I
DIR or G
A or B
Alee;
I
VI
VI
Vo - Vee or 0
10H
10H
10L
10L
= -201'A
= -6mA
= 20!lA
= 6 rnA
VI = Vee or 0, 10 = 0
One input at 0.5 V or 2.4 V
lee
ei
= VIH or VIL,
= VIH or VIL,
= VIH or VIL,
= VIH or VIL,
= Vee or 0
Other inputs at 0 V or Vee
DIRorG
4.5 V
4.5 V
TYP
SN54HCT643 SN74HCT643
UNIT
SN54HCT645 SN74HCT645
MAX
4.4 4.499
3.98
MIN
MAX
4.4
4.30
MIN
MAX
4.4
3.7
V
3.84
4.5 V
0.001
0.1
0.1
0.1
4.5V
0.17
0.26
0.4
0.33
5.5 V
±0.1
±100
±1000
±1000
nA
5.5 V
±0.01
±0.5
±10
±5
I'A
8
160
80
!lA
5.5 V
V
5.5 V
1.4
2.4
3
2.9
rnA
4.5 to
5.5 V
3
10
10
10
pF
.:tThis is the increase in supply current for each input that is at one of the specified TTL voltage Jevels rather than 0 V or
TEXAS . "
INSTRUMENlS
POST OFF1CE BOX 655012 • DALLAS, TEXAS 75265
Vee.
2-555
SN54HCT640, SN54HCT643
SN74HCT640, SN74HCT643
OCTAL BUS. TRANSCEIVERS WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
IINPUTI
TO
(OUTPUTI
tpd
Aor B
B or A
ten
l!
A or B
PARAMETER
E
tdis
:::t
3:
c
CD
<
l!
A or B
A or B
tt
(')
oen
FROM
vCC
SN54HCT640 SN74HCT640
TA = 25°C
MIN
TYP
MAX
5.5 V
4.5 V
14
12
27
5.5 V
4.5 V
24
20
21
18
35
32
30
5.5 V
4.5 V
5.5 V
18
9
4.5 V
26
12
11
8
Power dissipation capacitance per transceiver
SN54HCT643 SN74HCT643
MIN MAX
MIN MAX
32
27
53
47
25
23
44
39
45
41
38
34
15
14
18
16
UNIT
ns
ns
ns
ns
40 pF typ
No load. TA = 25°C
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 150 pF (see Note 1)
rr
CD
FROM
(lNPUTI
TO
(OUTPUTI
tpd
Aor B
8 or A
ten
l!
A or B
PARAMETER
en
tt
A or B
VCC
TA = 25°C
MIN
4.5V
5.5 V
4.5 V
5.5 V
4.5V
5.5 V
TYP
17
15
31
28
17
14
MAX
27
24
45
41
42
38
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
2-556
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • OAUAS, TEXAS 75265
SN54HCT640 SN74HCT640
SN54HCT643 SN74HCT643
MIN MAX
MIN MAX
41
34
37
68
61
63
57
30
56
51
53
48
UNIT
ns
ns
ns
SN54HCT645, SN74HCT645
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL
50 pF (see Note 1)
=
PARAMETER
Ipd
len
Idis
FROM
(INPUT)
A or 8
IT
IT
B or A
A or B
AcrB
A or B
II
TA = 2SoC
TO
(OUTPUT)
vCC
MIN
4.5 V
SNS4HCT645 SN74HCT645
TYP
MAX
16
22
33
28
MIN
MAX
MIN
MAX
5.5 V
14
25
25
20
46
30
4.5 V
69
58
5.5 V
22
41
62
52
4.5 V
26
40
60
50
5.5 V
23
36
54
45
4.5 V
9
12
1B
15
5.5 V
8
11
16
14
UNIT
,.
ns.
ns
ns
ns
U)
Q)
(,)
Power dissipation capacitance per transceiver
No load, TA = 25°C
-s
40 pF typ
Q)
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
Ipd
len
It
FROM
(INPUT)
A or B
IT
TO
(OUTPUT)
B or A
A or B
A or B
TA = 2SoC
Vcc
MIN
4.5 V
SNS4HCT64S SN74HCT64S
MIN MAX
MIN MAX
TYP
MAX
20
45
5.5 V
18
30
27
4.5 V
36
59
89
5.5 V
30
53
80
74
67
4.5 V
5.5 V
17
42
14
38
63
57
53
48
41
UNIT
C
en
o
:E
(.)
38
34
ns
ns
ns
l:
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
-If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-557
::J:
(')
s:
o
en
C
CD
<
(;'
CD
III
2-558
SN54HC646, SN54HC648, SN74HC646, SN74HC648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
02684, DECEMBER 19B2-REVISED SEPTEMBER 1987
•
Independent Registers for A and B Buses
SN54HC' , • , JT PACKAGE
SN74HC' .•. DW or NT PACKAGE
•
Multiplexed Real·Time and Stored Data
(TOP VIEW,
•
Choice of True or Inverting Data Paths
•
High-Current 3-State Outputs Can Drive Up
to 15 LSTIL Loads
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
CAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
description
These devices consist of bus transceiver circuits
with 3-state outputs, D-type flip-flops, and
control circuitry arranged for multiplexed
transmission of data directly from the input bus
or from the internal registers. Data on the A or
B bus will be clocked into the registers on the
low-to-high transition of the appropriate clock
pin (CAB or CSA). The examples on the following
page demonstrate the four fundamental busmanagement functions that can be performed
with the 'HC646 or 'HC648.
VCC
CBA
SBA
G
B1
B2
B3
B4
B5
B6
B7
B8
•
FK PACKAGE
(TOP VIEW)
g;~~uij~~
OCllUZ>UCll
4
A1
A2
A3
NC
A4
A5
A6
Enable (G) and direction (DIR) pins are provided
to control the transceiver functions. In the
transceiver mode, data present at the highimpedance port may be stored in either register
or in both. The select controls (SAB and SBA)
can multiplex stored and real-time (transparent
model data. The direction control determines
which bus will receive data when the enable G is
active (low). In the isolation mode (enable G
high), A data may be stored in one register and/or
B data may be stored in the other register.
3
2
1 282726
5
25
G
6
24
7
23
8
9
22
B1
B2
NC
B3
10
20
21
19
11
12 13 14 15 1617 18
NC- No internal connection
When an output function is disabled, the input
function is still enabled and may be used to store
and transmit data. Only one of the two buses,
A or B, may be driven at a time.
The SN54HC' family is characterized for
operation over the full military temperature range
of - 55°C to 125°C. The SN74HC' family is
characterized for operation from - 40°C to
85°C.
PRODUCTION DATA documents contain information
cumnt IS of publication dat8. Products canform to
specifications par the terms of Taxes Instruments
=~~8r::,~7i ~::::i:; :'iD=;::::r:~ nat
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1982, Texas Instruments Incorporated
2-559
SN54HC646, SN54HC648, SN74HC646, SN74HC648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
Ex
...........,...
(')
s:o
(21)
(3)
G
DIR
L
en
cCD
L
(1)
(23)
CAB CBA
X
(2)
(22)
(21)
(3)
SAB
SBA
IT
DIR
X
L
L
X
H
REAL·TIME TRANSFER
(1)
(23)
CAB CBA
X
X
(2)
(22)
SAB
SBA
X
L
REAL·TIME TRANSFER
BUS A TO BUS B
BUS B TO BUS A
<
(;'
CD
U)
~
(21)
(3)
(1)
G
DIR
X
X
H
X
t
X
X
X
X
t
(23)
CAB CBA
t
(2)
(22)
(21)
(3)
SAB
X
SBA
IT
X
X
X
L
DIR
L
X
X
L
H
(23)
(2)
H or L
X
H
TRANSFER STORED DATA
TOAORB
STORAGE FROM
A.B.ORAANDB
Pin numbers shown are for OW. JT. and NT packages.
2·560
(1)
CAB CBA SAB
X H or L X
TEXAS
.Jf
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
(22)
SBA
H
X
SN54HC646, SN54HC648, SN74HC646, SN74HC648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
FUNCTION TABLE
DATA IIOt
INPUTS
G
X
X
OPERATION OR FUNCTION
'HC646
'HC648
DIR
CAB
CBA
SAB
SBA
A1 THRU A8
B1 THRU B8
t
X
Store A, B unspecified
Store A, B unspecified
t
t
X
X
X
X
Not specified
X
Not specified
Input
Store B, A unspecified
Store B, A unspecified
Input
Input
Store A and B Data
Store A and B Data
Isolation, hold storage
Isolation, hold storage
l
l
l
l
l
H
X
X
X
X
X
X
X
X
X
Input
H
X
X
X
X
l
l
H
H or l
X
X
H
t
H or L H or l
X
H or l
X
X
H
l
H
Output
Input
Input
Output
Real-Time B Data to A Bus
Real-Time B Data to A Bus
Stored B Data to A Bus
Stored
Real-Time A Data to B Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Stored
li
Data to A Bus
Ii. Data to B Bus
tThe data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always
enabled. i.e., data at the bus pins will be stored on every low-ta-high transition on the clock inputs.
logic symbols
*
'HC648
'HC646
G
1211
DIR 13)
G3
3 ENI IBA)
3 EN2 [AB)
CBA
S8A
CAB
SAB
G5
123)
122)
11)
12)
14)
Al
PI
G
C4
C6
G7
G3
3 ENI [BA)
3 EN2 [A8)
C8A
SBA
CAB
SAB
G5
120)
>1
121)
DIR 13)
1231
122)
11)
12)
C4
C6
G7
14)
Bl
120)
;>1
81
Al
~1
IS)
7
119)
A2
IS)
82
16)
liS)
171
117)
IS)
116)
19)
liS)
110)
114)
(11)
113)
A4
117)
IS)
(16)
19)
liS)
110)
114)
Ill)
113)
83
84
B5
A6
87
AS
17)
AS
86
A7
(1S)
A4
B5
A6
82
161
A3
B4
AS
119)
A2
83
A3
7
86
87
A7
AS
8S
88
*These symbols are in accordance with ANS[/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for OW, JT, and NT packages.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·561
SN54HC646, SN54HC648, SN74HC646, SN74HC648
. OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
logic diagrams (positive logic}
'HC648
'HC646
G (211
DJ.
G
i;"!h'--D...-l'--LJ-t---------:-,
(21)
DJ.~3i'~~~~~§§~~f~l==c;=t
C~~I2~~~~~~~~~~~~{>~-~>-~
CBA (231
SBA (221
CAB (11
CAB (11
SAB (2)
SAB
SOA '221
A1 (4)
(21
A1 14)
:::E:
o
s:o
(201 81
(201 B1
t/)
cCD
<
n'
CD
(I)
A2~
---
-----
A3~
A4~
A5~
A6~
:;
~~~~
U
I
~------
~B2
A2~
~B3
A3~
~B4
7 CHANNELS IDENTICAL
~B5
~B6
TOCHANNEL1ABDVE
!:: g~: :;
------ ------ ---"
A4
---
7 CHANNELS IDENTICAL
~
A6~
A5
A7~
A8~
-----
~B2
~B3
~
TO CHANNEL 1 ABOVE
: ••
:~!:
84
~ 85
~B6
~B7
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~B8
Pin numbers shown are for OW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > VCC) . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or JT package .............. 300 DC
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or NT package . . . . . . . . . . . .. 260 DC
Storage temperature range ......................................... - 65 DC to 150 DC
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2-562
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC646, SN54HC648, SN74HC646, SN74HC648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
recommended operating conditions
SN54HC646
SN54HC648
MIN NOM MAX
Vee Supply voltage
VIH
VIL
High-level input voltage
Vee
Vee
Low-level input voltage
Vee
Vee
Vee
Vee
VI
Va
Input voltage
Output voltage
tt
Input transition (rise and fall) times
TA
Operating free-air temperature
2
1.5
3.15
4.2
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Vee - 2 V
Vee = 4.5 V
Vee
=
5
6
2
1.5
3.15
4.2
0
0
0
0.3
0.9
1.2
0
0
0
0
0
0
0
Vee
0
0
0
0
Vee
1000
500
400
0
-55
6 V
SN74HC646
SN74HC648
MIN NOM MAX
125
5
UNIT
V
6
V
0.3
0
-40
0.9
1.2
V
Vee
Vee
1000
500
400
V
tI)
V
G)
ns
'S
De
c
CJ
B5
G)
tJ)
electrical characteristics over recommended operating free-air temperature range (unless otherwise
oo~
PARAMETER
TEST CONDITIONS
VCC
TA - 25°C
MIN
2V
VI
=
VIH or VIL.
10H
=
-20
VI
VI
=
=
VIH or VIL.
VIH or VIL.
10H
10H
=
=
-6 rnA
VI
= VIH
or VIL.
10L
=
20 ~
= VIH or VIL.
VI = VIH or VIL.
VI = Vee or 0
Vo = Vee or 0
10L
10L
=
=
6 rnA
7.B rnA
~A
VOH
-7.8 rnA
VOL
VI
II
Ieontrol Inputs
10ziA or B
VI - Vee or O. 10 - 0
lee
e· I eontrol Inputs
TYP
MAX
SN54HC646
SN54HC648
MIN MAX
4.5 V
6V
4.5 V
6V
1.9 1.99B
4.4 4.499
5.9 5.999
3.9B
4.30
5.4B
5.BO
2V
4.5 V
0.002
0.001
0.1
0.1
0.1
0.1
0.1
0.1
6V
4.5 V
6V
6V
0.001
0.17
0.1
0.26
0.1
0.4
0.1
0.33
0.15
±0.1
±0.01
0.26
±100
±0.5
0.4
±1000
±10
0.33
±1000
±5
3
B
10
160
10
BO
10
6V
6V
2 to 6 V
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1.9
4.4
SN74HC646
SN74HC648 UNIT
MIN MAX
0
~
(.)
:::E:
1.9
4.4
5.9
3.B4
5.34
5.9
3.7
5.2
V
V
nA
~A
~A
pF
2-563
SN54HC646, SN5411C648, SN74HC646, SN74HC648
.oCTAL BUS. TRANSCEIVERS AND REGISTERS
WITH 3·STATE .oUTPUTS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
Vcc
fclock
•
::E:
n
3:
oen
tw
tsu
th
Clock frequency
Pulse duration, CSA or
CAB high or low
Setup time, A before CABt
or B before CBAt
Hold time, A after CASt
or S after CBAt
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 2SOC
MIN
MAX
0
0
0
80
16
14
100
20
17
6
31
36
5
5
5
c
a>
<
....n
a>
en
2-564
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN64HC646
SN54HC646
MIN MAX
0
0
0
115
23
20
150
30
26
4.3
22
25
SN74HC646
SN74HC646
MIN MAX
0
0
0
95
19
16
125
25
21
5
5
5
5
5
5
5.5
27
31
UNIT
MHz
ns
ns
ns
SN54HC646. SN54HC648. SN14HC646. SN14HC648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), Cl = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
IOUTPUT)
f max
tpd
CBA or CAB
AcrB
tpd
A or B
B or A
tpd
SBA or SABt
A or B
ten
G
A or B
tdis
G
AcrB
ten
DIR
A or B
tdis
DIR
A or B
tt
Any
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
6
31
36
TYP
11
54
64
65
18
14
50
14
11
70
20
16
85
25
20
85
25
20
80
25
20
80
25
20
28
8
6
MAX
180
36
31
135
27
23
190
38
32
245
49
42
245
49
42
245
49
42
245
49
42
60
12
10
SN54HC646
SN54HC648
MIN MAX
4.4
22
25
270
54
46
205
41
35
285
57
48
370
74
63
370
74
63
370
74
63
370
74
63
90
18
15
SN74HC646
SN74HC648
MIN MAX
5.5
27
31
225
45
38
170
34
29
240
48
41
305
61
52
305
61
52
305
61
52
305
61
52
75
15
13
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Power dissipation capacitance
No load. TA = 25°C
50 pf typ
]
~~--~----------------~----------~--------NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
tThese parameters are measured with the internal output state of the storage register OPPOSite to that of the bus input.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-565
SN54HC646, SN54HC648, SN74HC646, SN74HC648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
CBA or CAB
A or B
tpd
A or B
B or A
(")
tpd
SBA or SABt
A or B
oen
ten
IT
A or B
ten
DIR
A or B
PARAMETER
:J:
s:
c
(1)
<
c;"
(1)
til
tt
Any
Vee
TA = 25°C
MIN
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TVP
90
24
20
70
20
15
80
24
20
113
33
27
113
33
27
45
17
13
MAX
265
53
46
220
44
38
275
55
47
330
66
57
330
66
57
210
42
36
SN54HC646
SN54HC646
MIN MAX
400
80
68
335
67
57
415
83
70
500
100
85
500
100
85
315
63
53
SN74HC646
SN74HC648
MIN MAX
330
66
57
280
56
49
345
69
60
410
82
71
410
82
71
265
53
43
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
tThese parameters are measured with the internal output state of the storage register opposite to that of the bus input.
2-566
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
UNIT
ns
ns
ns
ns
ns
ns
SN54HCT646. SN54HCT648. SN74HCT646. SN74HCT648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
D2804. MARCH 1984-REVISED SEPTEMBER 19B7
SN64HCT' ... JT PACKAGE
SN74HCT' .•. DW OR NT PACKAGE
•
Inputs are TTL-Voltage Compatible
•
Independent Registers for A and B Buses
•
Multiplexed Real·Time and Stored Data
•
Choice of True or Inverting Data Paths
•
High-Current 3-State Outputs Can Drive Up
to 15 LSTTL Loads
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEWI
CAB
SAB
VCC
CBA
SBA
G
B1
B2
B3
B4
B5
B6
B7
B8
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
fII
en
CI)
CJ
">
CI)
description
o
SN54HCT' ... FK PACKAGE
These devices consist of bus transceiver circuits
with 3-state outputs, D-type flip-flops, and
control circuitry arranged for multiplexed
transmission of data directly from the input bus
or from the internal registers. Data on the A or
B bus will be clocked into the registers on the
low-to-high transition of the appropriate clock
pin (CAB or CBA). The examples on the following
page demonstrate the four fundamental busmanagement functions that can be performed
with the 'HCT646 or 'HCT648.
Enable {G) and direction (DIR) pins are provided
to control the transceiver functions. In the
transceiver mode, data present at the highimpedance port may be stored in either register
or in both. The select controls (SAB and S8A)
can multiplex stored and real-time (transparent
mode) data. The direction control determines
which bus will receive data when the enable G is
active (low). In the isolation mode (enable G
high), A data may be stored in one register andlor
B data may be stored in the other register.
en
(TOP VIEW)
o
~~~U tl;;!;;;!;
~
OUlUZ>UUl
4
A1
3 2
o
1 2827 26
5
25
6
24
7
23
8
22
:t:
21
10
20
19
11
12131415 161718
NC-No internal connection
When an output function is disabled, the input
function is still enabled and may be used to store
and transmit data. Only one of the two buses,
A or 8, may be driven at a time.
The SN54HCT' family is characterized for
operation over the full military temperature range
of - 55°C to 125°C. The SN74HCT' family is
characterized for operation from - 40°C to
85°C.
PRDDUenD.
DATA ""111II1II,...
toin
of pUlialiotI
.....
_ InI.matio.
co"or.. to
. _ OS
~_
I" tor....1T.... 1_._
:=1:;"1:!."I'.7i =",J:.'i=~ nat
~tiona
por
TEXAS ....,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
~opvright
© 1984, Texas Instruments Incorporated
2-567
SN54HCT646, SN54HCT648, SN74HCT646, SN74HCT648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
Ii
:::I:
n
(21)
(3)
G
OIR
o(I)
L
~
L
(1)
(23)
CAB CBA
X
(2)
(22)
(21)
(3)
SAB
SBA
IT
OIR
X
L
X
H
REAL-TIME TRANSFER
cCD
(1)
(23)
(2)
CAB CBA SAB
X
X
L
(22)
SBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B TO BUS A
<
ri'
CD
o
(21)
(3)
IT
OIR
X
X
X
X
X
H
(1)
(23)
(2)
(221
CAB CBA SAB SBA
t
X
t
X
t
X
X
X
X
X
X
(21)
(3)
IT
OIR
L
L
L
H
(23)
(2)
TRANSFER STORED DATA
STORAGE FROM
A.B.ORAANDB
TOAORB
Pin numbers shown are for OW. JT. and NT packages.
2-568
(11
CAB CBA SAB
X H or L X
H
H or L X
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TeXAS 75265
(22)
SBA
H
X
SN54HCT646. SN54HCT648. SN74HCT646. SN74HCT648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
FUNCTION TABLE
DATA I/Ot
INPUTS
Ii
DIR
CAB
CBA
SAB
SBA
A1 THRU AS
X
X
X
X
X
Input
X
t
t
H
X
X
X
t
X
t
X
X
X
L
L
L
L
l
H
X
X
X
X
X
X
X
X
l
l
H
H or L
H
H or L H or L
X
H or l
X
X
H
L
H
X
X
OPERATION OR FUNCTION
as
'HCT846
'HCT848
Not specified
Store A, B unspecified
Store A, B unspecified
·Not specified
Input
Store B, A unspecified
Store B, A unspecified
Input
Input
Output
Input
Input
Output
B1 THRU
Store A and B Data
Store A and B Data
Isolation, hold storage
Isolation, hold storage
Real-Time B Data to A Bus Real-Time B Data to A Bus
Stored B Data to A Bus
Stored
ii Data to
A Bus
Real-Time A Data to B Bus Real-Time A Data to B Bus
Stored A Data to B Bus
t The data output functions may be enabled or disabled by various signals at the
Stored
A Data to B Bus
Gand DIR inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
CD
DIR (3)
G3
3 ENI (BA]
3 EN2 (AB]
CBA
SBA
CAB
SAB
G5
JENl (BAI
3 EN2 (AB)
C6
(20)
Bl
AI
B2
(6)
(1S)
(7)
(1])
(S)
liS)
19)
115)
110)
(141
(111
113)
A3
B3
A4
B4
B5
AS
B6
A1
87
A8
B8
1231
(221
(1)
(2)
l:
C4
G5
C6
G7
(4)
(20)
Bl
AI
(19)
A2
A5
en
o
:E
o
G3
CBA
SBA
CAB
SAB
'i
o
'HCT648
C4
14)
(5)
CD
oS
'HCT646
(231
122)
(1)
(2)
o
()
logic symbols:l:
G (211
PI
(5)
(19)
(SI
liS)
171
117)
IS)
(IS)
(9)
115)
110)
(14)
(11)
(13)
A2
B2
B3
A3
B4
A4
A5
B5
AS
BS
B1
A1
AS
B8
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for OW, JT. and NT packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-569
SN54HCT646, SN54HCT648, SN74HCT646, SN74HCT648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
logic diagrams (positive logic)
'HCT646
'HCT648
G 1211
G (211
eBA 1231
SBA (221
g~*~~=C:ll
0'R,31
CAB
SA• ....!12~1_...!:.-I-I--c:»-t-'I>....,
(1)
A1 141
::J:
o
s:o
(201
1201 81
81
tn
C
CI)
<
5'
CI)
o
A2~
---
A.3~
A4~
AS
~,'.',
A6~
A7~
7 CHANNELS IDENTICAL
TO CHANNEL 1 ABove
-----
1.......,...m!LB2
A2~
~B3
A3~
~84
~ B5
~B6
~B7
A8~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~B8
A4
AS
---
-----
7 CHANNELS IDENTICAL
~
TO CHANNEL 1 ABOVE
A6~
A7
i1'1t'"'i
A8~
~B2
~B3
J!L....i
!~
:: ~~:~
B4
B5
I
_____________________
1141 B6
~ B7
~B8
Pin numbers shown are for OW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or JT package .............. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or NT package ............. 260°C
Storage temperature range ......................................... - 65°C to 150 DC
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2-570
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HCT646, SN54HCT648, SN74HCT646, SN74HCT648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
recommended operating conditions
Vee Supply voltage
VIH High·level input voltage
Va
Low-level input voltage
Input voltage
Output voltage
tt
Input transition (rise and fall) times
TA
Operating free-air temperature
VIL
VI
SN54HCT646
SN74HCT646
SN54HCT648
SN74HCT648
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
V
I Vee = 4.5 V to 5.5 V
2
I
0
O.B
0
O.B
V
0
Vee
0
Vee
V
0
Vee
500
0
Vee
500
ns
B5
'e
Vee
= 4.5Vt05.5V
2
0
-55
V
0
-40
125
II
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
=
TA
VCC
TYP
MIN
VOL
I
Control Inputs
II
10ziA or B
ICC
One input at 0.5 V or 2.4 V
Alee t
ei
= VIH or VIL. IOH = - 2O I'A
VI = VIH or VIL. IOH = -6 rnA
VI = VIH or VIL. IOL = 2Ol'A
VI = VIH or VIL. IOL = 6 rnA
VI = Vee or 0
Va = Vce or 0
VI = Vee or O. 10 = 0
VI
VOH
Other inputs at 0 V or Vee
IControl Inputs
4.5 V
4.5 V
SN54HCT646 SN74HCT646
25°C
SN54HCT648 SN74HCT648 UNIT
MAX
MIN
3.98
MAX
4.4
4.4 4.499
4.30
MIN
MAX
4.4
V
3.84
3.7
4.5 V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
5.5 V
±0.1
±100
± 1000
± 1000
nA
5.5 V
±0.01
±0.5
±10
±5
I'A
8
160
80
I'A
1.4
2.4
3
2.9
mA
3
10
10
10
pF
5.5 V
5.5 V
4.5 to
5.5 V
tThis is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or
V
Vee.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
MIN
fclock
tw
tsu
th
Clock frequency
Pulse duration, CSA or
SN54HCT646 SN74HCT646
TA = 25°C
Vcc
SN54HCT648 SN74HCT648
MAX
MIN
MAX
MIN
MAX
4.5 V
0
31
0
22
0
27
5.5 V
0
16
36
0
23
24
0
19
29
4.5 V
CAB high or low
5.5 V
14
21
17
Setup time. A before CABt
4.5 V
20
30
25
or B before CBA!
5.5 V
18
27
23
Hold time. A after CABt
4.5 V
5
5
5
or B after CBA t
5.5 V
5
5
5
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
UNIT
MHz
ns
ns
ns
2-571
SN54HCT646, SN54HCT648, SN74HCT646, SN74HCT648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL '" 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
IOUTPUTI
f max
tpd
C8A or CAB
A or B
tpd
A or B
B or A
tpd
SBA or SABt
A or B
ten
G
AorB
tdis
G
A or B
CD
ten
DIR
A or B
n'
CD
tdis
DIR
A or B
:J:
o
3:
o
tn
C
<
til
Any
tt
TA = 25°C
VCC
MIN
TYP
4.5 V
31
5.5 V
4.5 V
36
54
64
18
16
14
5.5
4.5
5.5
4.5
V
V
V
V
5.5
4.5
5.5
4.5
V
V
V
V
22
24
12
20
22
25
22
25
22
25
V
V
V
V
22
9
7
5.5 V
27
29
54
49
41
45
41
34
24
37
57
31
48
51
74
43
61
44
49
67
74
55
61
44
49
44
49
67
74
55
61
55
61
44
12
11
67
18
67
74
16
Power dissipation capacitance
UNIT
MHz
36
32
27
38
34
49
17
25
5.5 V
4.5 V
5.5
4.5
5.5
4.5
MAX
SN54HCT646 SN74HCT646
SN54HCT646 SN74HCT648
MIN MAX
MIN MAX
55
15
14
ns
ns
ns
ns
ns
ns
ns
ns
50 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 150 pF (see Note 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
VCC
CBA or CAB
A or B
4.5 V
5.5 V
tpd
A or B
B or A
tpd
SBA or SABt
A or B
ten
G
A or B
ten
DIR
A or B
tt
Any
TA = 25°C
MIN
4.5 V
5.5 V
4.5 V
5.5
4.5
5.5
4.5
V
V
V
V
5.5 V
4.5 V
5.5 V
TYP
24
22
22
20
26
24
33
22
33
22
17
14
MAX
53
47
44
39
SN54HCT646 SN74HCT646
SN54HCT648 SN74HCT648
MIN MAX
MIN MAX
80
52
67
60
66
60
55
50
83
74
100
55
49
66
59
66
90
100
69
62
87
74
87
59
42
90
63
74
53
38
57
48
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
tThese parameters are measured with the internal output state of the storage register opposite to that of the bus input.
2-572
TEXAS
.Jf
INSTRUMENTS
POST OFt;=ICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
ns
ns
SN54HC651, SN54HC652, SN74HC651, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
02684. DECEMBER 1982-REVISED JUNE 1989
SN54HC651. SN54HC652 ... JT PACKAGE
SN74HC651. SN74HC652 ... OW Dr NT PACKAGE
•
Bus Transceivers and Registers
•
Independent Registers and Enables for A
and B Buses
•
High-Current 3-State Outputs Can Drive Up
to 15 LSTTL Loads
•
Multiplexed Real-Time and Stored Data
•
Choice of True and Inverting Data Paths
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
ITOP VIEW)
CAB
SAB
GAB
Al
A2
A3
A4
A5
A6
A7
A8
GND
Dependable Texas Instruments Quality and
Reliability
VCC
CBA
SBA
GBA
B1
B2
B3
B4
B5
B6
B7
B8
FI
fI)
Q)
U
'>
Q)
c
SN54HC651. SN54HC652 ... FK PACKAGE
ITOP VIEW)
description
These devices consist of bus transceiver circuits,
D-type flip-flops. and control circuitry arranged
for multiplexed transmission of data directly from
the data bus or from the internal storage
registers. Enable GAB and GBA are provided to
control the transceiver functions. SAB and SBA
control pins are provided to select whether realtime or stored data is transferred. A low input
level selects real-time data, and a high selects
stored data. The examples on the following page
demonstrate the four fundamental busmanagement functions that can be performed
with the 'HC651 and 'HC652.
en
o
:i!!
4
A7
A8
GND
NC
B8
B7
B6
3
(,)
2 1 28 27 26
25
24
6
7
23
8
22
9
21
10
20
11
19
J:
GAB
SAB
CAB
NC
VCC
CBA
SBA
12 13 14 15 16 17 18
_NMU'l:tLnCO
«<2«<
Data on the A or B data bus, or both, can be
NC-No internal connection
stored in the internal D flip-flops by low-to-high
transitions at the appropriate clock pins (CAB or
CBA) regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode,
it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling GAB
and GBA. In this configuration each output reinforces its input. Thus, when all other data sources to the
two sets of bus lines are at high impedance, each set of bus lines will remain at its last state.
The SN54HC651 and SN54HC652 are characterized for operation over the full military temperature range
of -55°C to 125°C. The SN74HC651 and SN74HC652 are characterized for operation from -40°C
to 85°C.
PRODUCTION DATA do•• monts .ont.in inform.tion
••rront .s 01 publication data. Products ••nlorm to
spa.ili••tions par ilia tarms 01 Taxa. Instrumants
=i~8{.r:1~7i =:~ti:; :I~D:=~~:~ aot
Copyright © 1989. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
2-573
SN54HC651. SN54HC652. SN74HC651. SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
II
(3)
(21)
(1)
(23)
(2)
GAB GBA CAB CBA SAB
L
L
X
X
X
(3)
(22)
(21)
(1)
(23)
(2)
(22)
GAB GBA CAB CBA SAB SBA
SBA
H
L
H
X
X
L
REAL-TIME TRANSFER
REAL-TIME TRANSFER
BUS B TO BUS A
BUS A TO BUS B
X
~
(3)
(21)
(1)
(23)
GAB GBA CAB CBA
(2)
(22)
(3)
SAB SBA
X
H
t
X
X
X
L
X
X
t
X
X
L
H
t
X
X
(21)
(1)
GAB GBA CAB
H
L
H or L
(23)
H or L
TRANSFER
STORED DATA
TO A AND/OR B
STORAGE FROM
A ANO/OR B
Pin numbers shown are for OW, JT, and NT packages.
TEXAS . "
INSTRUMENTS
2-574
POST
OFFI~E
BOX 655012 • DALLAS. TEXAS 75285
(2)
(22)
CBA SAB SBA
H
H
SN54HC651, SN54HC652, SN74HC651, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
FUNCTION TABLE
DATA II0t
INPUTS
GAB ~BA
L
H
L
X
H
L
L
L
L
H
H
H
H
H
CAB
H
X
H or L
L
L
H
H
L
SAB
SBA
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
L
H
X
X
H or L H or L
t
t
t
L
CBA
t
t
H or L
t
t
t
X
X
X
H or L
X
X
H or L
X
H or L H or L
H
H
OPERATION OR FUNCTION
Al THRU A8 Bl THRU B8
Input
Input
Input
Not specified
Input
Not specified
Output
Input
Output
Input
Output
Input
Input
Output
Output
Output
'HCS51
'HCS52
Isolation
Isolation
Store A and B Data
Store A and B Data
Store A, Hold B
Store A, Hold B
Store A in both registers
Store A in both registers
Hold A, Store B
Hold A, Store B
Store B in both registers
Store B in both registers
Real-Time B Data to A Bus
Real-Time B Oata to A Bus
Stored
B Data to
A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and
Stored A Data to B Bus
Stored
B Data to
fI
Stored B Data to A Bus
Real-Time A Data to B Bus
II)
Stored A Data to B Bus and
A Bus
Stored B Data to A Bus
enabled, i.e., data at the bus pins will be stored on every low-ta-high transition on the clock inputs.
~
GBA
GAB
CBA
SBA
CAB
SAB
ENI [BA]
EN2 [AB]
C4
G5
CS
G7
(20)
Bl
Al
(5)
(.)
'HC652
'HCS51
(4)
c
en
o
logic symbols*
(21)
(3)
(23)
(22)
(1)
(2)
":;
Q)
tThe data output functions may be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions are always
GBA
GAB
CBA
SBA
CAB
SAB
Q)
(,)
(19)
A2
B2
(6)
(18)
(7)
(17)
(8)
(IS)
(9)
(15)
(10)
(14)
(11)
(13)
A4
B4
A5
B6
B7
A7
B8
A8
EN2 [AB]
C4
G5
C6
G7
A3
;;'1<]
(5)~
5
60
L.=....
.r
5
1
(7)L
7
1
40
1
;;'1C>2'V
(20)
Bl
[J
7
(19)
~(18)
~
L...:..
B3
(9)L
.......:J (16)
.......:J (15)
(lO)L
W(14)
(ll)L
W(13)
A5
A6
B2
(17)
A4
(8)
B5
A6
A2
::E:
..... ENI [BA]
(4)
Al
(6)
B3
A3
(21)
(31
(23)
(22)
(I)
(2)
B4
B5
B6
A7
B7
A8
L..:....
~
B8
*These symbols are in accordance with ANSIIIEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for OW, JT, and NT packages.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-575
SN54HC651, SN54HC652, SN74HC651, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
logic diagrams Ipositive logic)
'HC651
'HC652
GBA .:::12.::11--<(>.---,
GA8~13=1~{)--1-------------------__,
CM~12~3~1~~~~~~~~~~lI~~~l
~:
SBA
ftl
12
Al -,,14,,-11+-+-I-,.--<::'1--+--+
:I:
(')
3:
1201 Bl
(20) B1
otJ)
c
151
A2 161:: :
crCD<
A4
CD
tn
~m
iiiJ-++-I
A5 ~
--7 CHANNELS IDENTICAL
----
1191
: ::1181 B2
:~
: :: 1161 B4
A4
~~
TO CHANNEll ABove
(15) B5
:~ 1101:: :
: ::1141 :~
A8 ~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~ B8
:;::::
-w......,
AS ~
A6 1~9ril:: :
- - -
__ h
7 CHANNELS IDENTICAL
TO CHANNEL 1 ABOVE
I::::::
B2
t.....!!.Z1 ::
~
B5
::: :::: B"
~~--------------------~ ~
Pin numbers shown are for OW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) ............................ , . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through Vee or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or JT package .............. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or NT package ............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2-576
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC651, SN54HC652, SN74HC651, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
recommended operating conditions
SN64HC651
SN64HC662
MIN NOM MAX
Vee SupplV voltage
VIH
VIL
High-level input voltage
Vce = 2 V
VCC = 4.5 V
Low-level input voltage
Vce = 6 V
VCC = 2 V
Vce = 4.5 V
Vce
VI
Input voltage
Vo
Output voltage
tt
Input transition (rise and fall) times
TA
Operating free-air temperature
VCC
Vee
Vee
=
2
1.5
5
SN74HC651
SN74HC652
MIN NOM MAX
6
2
1.5
3.15
4.2
6 V
0
0
0
=2V
= 4.5 V
=6V
Vec
VCC
1000
0
0
0
0
500
400
125
0
0
-40
0
-55
6
3.15
4.2
0
0
0.3
0.9
1.2
0
0
0
0
5
UNIT
V
V
0.3
0.9
1.2
II
V
Vee
Vee
1000
V
V
500
400
ns
85
"e
t/)
Q)
U
.S;
Q)
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
VI = VIH or VIL.
10H = -20 ~A
VI = VIH or VIL.
VI = VIH or VIL.
IOH = -6 mA
IOH = -7.8 mA
VOH
VI = VIH or VIL.
IOL
=
20 ~A
VOL
VI = VIH or VIL. IOL=6mA
VI = VIH or VIL. IOL = 7.8 mA
II
Control Inputs VI = Vec orO
10ziA or B
Vo = Vce or GND
I
VI = Vee or O. 10
lee
el Control Inputs
I
=0
2V
4.5 V
TA - 25"C
TYP
MIN
1.9 1.998
4.4 4.499
6V
4.5 V
5.9
3.98
5.999
4.30
6V
2V
4.5 V
5.48
5.80
0.002
6V
4.5 V
6V
6V
6V
6V
0.001
0.001
0.17
0.15
±0.1
5.2
UNIT
::E:
V
5.34
0.1
0.1
0.1
0.26
0.26
±loo
0.4
0.4
0.1
0.1
0.33
0.33
±1Ooo
±10
160
10
±1000
±5
80
10
10
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
1.9
4.4
5.9
3.84
0.1
0.1
0.1
3
~
SN74HC652
MIN MAX
5.9
3.7
±0.5
8
INSTRUMENTS
SN74HC651
1.9
4.4
±0.01
2 to 6 V
TEXAS
MAX
SN54HC651
SN54HC652
MIN MAX
o
en
o
~
o
0.1
V
nA
~
~A
pF
2-577
SN54HC651, SN54HC652, SN74HC651, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
VCC
fclock
tw
Clock frequency
Pulse duration, CBA or
CAB high or low
Setup time, A before CABt
:::z::
tsu
or B before CBAt
(")
3:
otJ)
th
Hold time, A after CABt
or B after CBA t
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
0
0
0
6
31
36
BO
16
14
100
20
17
5
5
5
cCD
<
c:r
CD
tn
2-578
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS,
TEX~S
75265
SN54HC651
SN74HC651
SN54HC652
MIN MAX
SN74HC652
MIN MAX
0
0
0
115
23
20
150
30
26
5
5
5
4.3
22
25
0
0
0
95
19
16
125
25
21
5
5
5
5.5
27
31
UNIT
MHz
ns
ns
ns
SN54HC651. SN54HC652. SN74HC651. SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
FROM
IINPUT!
TO
(OUTPUT!
f max
tpd
CBA or CAB
A or B
tpd
AorB
BorA
tpd
SBA or SABt
A or B
ten
GBA or GAB
A or B
tdis
GBA or GAB
AorB
Any
tt
TA
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
= 25°C
TYP
10
40
45
65
1B
14
50
14
11
70
20
16
85
25
20
50
23
20
28
8
6
MIN
6
31
36
MAX
1BO
36
31
135
27
23
190
3B
32
245
49
42
245
49
42
60
12
10
SN54HC651
SN54HC652
MIN MAX
4.3
22
25
270
54
46
205
41
35
285
57
48
370
74
63
370
74
63
90
18
15
No load, TA = 25°C
Power dissipation capacitance
SN74HC651
SN74HC652
MIN MAX
5.5
27
31
225
45
38
170
34
29
240
48
41
305
61
52
305
61
52
75
15
13
UNIT
MHz
fI
ns
ns
ns
ns
ns
ns
50 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 150 pF (see Note 1)
FROM
IINPUT!
TO
(OUTPUT!
tpd
C8A or CAB
A or B
tpd
A or B
B or A
tpd
SBA or SABt
A or B
ten
GBA or GAB
A or B
PARAMETER
tt
Any
TA
VCC
MIN
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
=
25°C
TYP
90
24
18
70
20
15
80
24
20
100
33
27
45
17
13
MAX
265
53
46
220
44
38
275
55
47
330
66
57
210
42
36
SN54HC651
SN54HC652
MIN MAX
400
80
68
335
70
57
415
83
70
500
100
85
315
63
53
SN74HC651
SN74HC652
MIN MAX
330
66
57
275
55
48
345
69
60
410
B2
71
265
53
43
UNIT
n.
n.
n.
n.
n.
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
tThese parameters are measured with the internal output state of the storage register opposite to that of the bus input.
TEXAS
-II
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-579
J:
(')
s:
oen
cCD
<
c:;'
CD
III
2-580
SN54HCT651, SN54HCT652, SN74HCT651, SN74HCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
MARCH 1984-REVISED SEPTEMBER 1
•
SN54HCT651. SN54HCT652 •.. JT PACKAGE
SN74HCT651. SN74HCT652 •.. OW OR NT PACKAGE
Inputs are TTL-Voltage Compatible
•
Bus Transceivers and Registers
•
Independent Registers and Enables for A
and B Buses
•
High-Current 3-State Outputs Can Drive Up
to 15 LSTTL Loads
•
Multiplexed Real-Time and Stored Data
•
Choice of True and Inverting Data Paths
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
(TOPVIEWI
Dependable Texas Instruments Quality and
Reliability
CAB
SAB
GAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
CBA
SBA
GBA
B1
B2
B3
B4
B5
B6
B7
B8
FI
tn
CD
CJ
'>CD
Q
SN54HCT651. SN54HCT652 ... FK PACKAGE
en
(TOP VIEW)
description
o
~~~utl~~
These devices consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged
for multiplexed transmission of data directly from
the data bus or from the internal storage
registers. Enable GAB and GBA are provided to
control the transceiver functions. SAB and SBA
control pins are provided to select whether realtime or stored data is transferred. A low input
level selects real-time data, and a high selects
stored data. The examples on the following page
demonstrate the four fundamental busmanagement functions that can be performed
with the 'HCT651 and 'HCT652.
:E
OC/lUZ>UC/l
4
A1
A2
A3
NC
A4
A5
A6
3
2
o
J:
1 2827 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
GBA
B1
B2
NC
B3
B4
B5
12131415 161718
r-COOucor----,
12"'"'---<0__--,
GBA 0:
GAS~13~1~~
GAB~13=1~~
__
~~~~~~~~~~--.
__~~~~~~~~~~__,
CBA~12~3tl====~=======t;:~~~~>-_tl
SSA
CSAtI2~3~1~s:~~=====5;;~~~~>-~l
CAB
~: jl2Jl=::!2=1-+bo""?"-- Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ± 20 mA
Continuous output current, la (Va = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±35 mA
Continuous current through Vee or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or JT package .............. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or NT package ............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HCT651
SN74HCT651
SN74HCT652
SN54HCT652
Vee Supply voltage
High-level input voltage
VIH
I
Vee = 4.5 V to 5.5 V
I Vee
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
2
2
V
V
0
0.8
0
0.8
V
Input voltage
0
Vee
0
Vee
v
Vo
Output voltage
0
0
tt
Input transition (rise and fall) times
Vee
500
Vee
500
ns
TA
Operating free-air temperature
85
°e
VIL
VI
2-584
Low-level input voltage
= 4.5 V to 5.5 V
0
-55
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
125
0
-40
V
SN54HCT651. SN54HCT652. SN74HCT651. SN74HCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
V, - VIH or VIL.
VI = VIH or VIL.
VOH
IOH - -20~A
IOH = -6 mA
10L = 20 ~A
VI = VIH or VIL.
VOL
VI - VIH or VIL. 10l - 6 mA
Control Inputs VI = VCC or 0
II
Vo = VCC or O. VI = VIH or Vll
10ziA or B
Data = VCC or 0
I
VI = VCC or O. 10 = 0
One input at 0.5 V or 2.4 V
ICC
41CC t
Ci
4.5 V
4.5 V
4.5 V
4.5 V
5.5 V
SN54HCT651
TA - 25°C
VCC
TYP
4.4 4.499
3.98
4.30
0.001
0.17
5.5 V
MAX
0.1
±0.1
0.26
±100
±O.Ol
JControl Inputs
UNIT
V
V
nA
±1000
±1000
±0.5
±10
±5
8
160
80
~A
~A
(/)
5.5 V
Other inputs at 0 V or V CC
SN74HCT651
SN54HCT652 SN74HCT652
MIN MAX
·MIN MAX
4.4
4.4
3.7
3.84
0.1
0.1
0.4
0.33
5.5 V
1.4
2.4
3
2.9
mA
4.5 to
5.5 V
3
10
10
10
pF
CD
CJ
tThis is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
TA - 25°C
MIN
4.5 V
5.5 V
4.5 V
fclock Clock frequency
tw
lou
th
Pulse duration. CBA or CAB high or low
5.5 V
Setup time. A before CA81 or B before CBA t
Hold time. A after CABI or B after CBAt
4.5 V
5.5 V
4.5 V
0
0
20
18
MAX
25
15
14
5.5 V
5
5
TEXAS •
INSTRUMENTS
POST OFFICE BOX 65!?012 • DALLAS, TEXAS 75265
28
SN54HCT651
SN74HCT651
SN54HCT652 SN74HCT652
MIN MAX
MIN MAX
17
20
0
0
0
19
0
22
30
25
27
23
19
23
21
5
17
5
5
5
':;
CD
c
en
o
::!:
(.)
::c
UNIT
MHz
ns
ns
ns
2-585
SN54HCT651, SN54HCT652, SN74HCT651, SN74HCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
.
WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
TO
(INPUT!
(OUTPUT!
f max
E
tpd
tpd
::t
tpd
(")
3:
ten
ot/)
tdis
cCD
CBA or CAB
A or B
B or A
SBA or SABt
Ci'BA or GAB
Ci'BA or GAB
A or B
A or B
A or B
Any
tt
<
C;'
A or B
MIN
TYP
SN74HCT651
SN54HCT652 SN74HCT652
MAX
MIN
MAX
MIN
UNIT
MAX
4.5 V
25
35
17
5.5 V
28
19
4.5 V
40
18
36
54
45
5.5 V
16
32
49
41
4.5 V
14
27
41
34
20
MHz
22
5.5 V
12
24
37
31
4.5 V
20
38
57
48
5.5 V
17
34
51
4.5 V
25
49
74
43
61
5.5 V
22
44
67
55
4.5 V
25
49
74
61
5.5 V
22
44
67
55
4.5 V
9
12
18
15
5.5 V
7
11
16
14
Power dissipation capacitance
CD
SN54HCT651
TA = 25°C
vCC
ns
ns
ns
ns
ns
ns
50 pF typ
No load, TA = 25°C
til
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
tpd
tpd
tpd
ten
tt
FROM
TO
(INPUT)
(OUTPUT)
CBA or CAB
A or B
A or B
SBA or SABt
Ci'BA or GAB
B or A
A or B
A or B
Any
SN54HCT651
TA = 25°C
VCC
MIN
TYP
SN74HCT65.1
SN54HCT652 SN74HCT652
MAX
MIN
MAX
MIN
4.5 V
24
53
80
66
5.5 V
22
47
72
60
4.5 V
22
44
70
55
5.5 V
4.5 V
20
26
39
55
60
50
83
69
5.5 V
24
49
74
62
4.5 V
33
66
100
82
5.5 V
30
17
59
90
74
4.5 V
42
63
53
5.5 V
14
38
57
48
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
tThese parameters are measured with the internal output state of the storage register opposite to that of the bus input.
2-586·
TEXAS
~
INSTRUMENTS
PO'ST OFFICE BOX 655012 • DALLAS, TeXAS 75265
UNIT
MAX
ns
ns
ns
ns
ns
SN54HC679. SN74HC679
12·81T ADDRESS COMPARATORS
02833. MARCH 1984-REVISEO JUNE 1989
•
•
SN54HC679 ... J PACKAGE
SN74HC679 ... OW OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
(TOP VIEW)
AI
A2
A3
A4
AS
A6
A7
A8
AS
Dependable Texas Instruments Quality and
Reliability
description
The 'HC679 address comparator simplifies
addressing of memory boards and/or other
peripheral devices. The four P inputs are normally
hard wired with a preprogrammed address. An
internal decoder determines what input
information applied tothe 12-A inputs must be
low or high to cause a low state at the output
(Y). For example, a positive-logic bit combination
of 0111 (decimal 7) at the P input determines
that inputs A 1 through A 7 must be low and that
inputs AS through A 12 must be high to cause
the output to go low. Equality of the address
applied at the A inputs to the preprogrammed
address is indicated by the output being low.
VCC
G
Y
P3
P2
PI
PO
AI2
All
A10
GND
fI
SN54HC679 ... FK PACKAGE
(TOP VIEW)
u
(f)
N ..... U
« « « > lel
3
2 1 2019
18
17
16
7
15
8
I.
9 10"
Y
P3
P2
PI
PO
1213
O>OO ..... N
The 'HC679 features an enable input (G). When
«z~~~
el«««
G is low, the device is enabled. When G is high,
the device is disabled and the output is high
regardless of the A and P inputs.
The 'HC679 is functionally unilaterally interchangeable with its TTL ALS counterpart, 'ALS679 in all cases
of normal use as 12-bit address comparators. They differ in two respects. First, they may be programmed
to recognize all A inputs low either by connecting all P inputs high (1111 = decimal 15), or by combination
HHLL (1100 = 12), the latter option not being valid for the TTL ALS parts. Second, the combinations
HHLH and HHHL (1101 = 13 and 1110 = 14) cannot be used (but are not needed) in address-comparator
applications. These two combinations cause the outputs to be disabled (high).
The SN54HC679 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74HC679 is characterized for operation from -40°C to 85°C.
a'
UNLESS OTHERWISE NOTED this d•••moot conlllin.
PRODUCTION DATA in'olllation •••raot I.
publi.ation dato. P.oducts coa'orm to _ificlti•••
par tha tarms ., T.... 10",,0I11III11 IIIndlrd
~::~~:\::'g.~.:lr=~:- not .......rily
Copyright © 1989, Texas Instruments Incorporated
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TeXAS 75265
2-587
SN54HC679, SN74HC679
12·81T ADDRESS COMPARATORS
FUNCTION TABLE
~
L
L
L
L
L
L
L
L
L
L
•
::J:
o
L
3:
L
L
L
L
L
L
H
otn
C
CD
<
(;'
CD
P3
P2
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
Pl
L
PO
L
H
H
L
H
L
H
L
H
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
L
H
L
H
A2
Ai
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
A3
H
A4
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
L
INPUTS
AS AS
H
H
H
H
H
H
L
L
L
L
L
L
L
L
OUTPUT
A7
H
H
H
H
H
H
L
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
A8
H
H
H
H
H
H
H
H
L
L
L
A9
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
A11
A12
V
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
l-t
H
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
All other combinations
Any combination
(I)
logic symbol t
G
PO
PI
P2
P3
19
I.
15
16
17
AI
AZ
A3
A4
3
•
A6
6
A7
AS
Al0
A11
A12
3
22
23
24
25
26
27
28
29
A9
11
12
13
IADDRESS CDMPI
p> 1
-1
II<
r
EN
21
2
A5
-I
l
pP> 3
3
P>.
•
P> 5
5
p> 6
6
p> 7
7
P> 8
8
P> 9
9
P>10
10
P>11
-I
-I
-1
=1
=1
18
V
=1
=1
=1
=1
11
210 P>12
12
Z11
P= 13
Z12 P = 14
-1
>1
tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for OW. J, and N packages.
2-588
Al0
H
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC679. SN74HC679
12·BIT ADDRESS COMPARATORS
'logic diagram (positive logic)
G
14
P1
P2
16 ~
15
.~
P3 17~
v
A1
In order to understand the
implementation of this device. it
is essential that the function of
the
vertical
string
of
transmission
gates
be
understood. A schematic of one
of these gates is shown below.
If the input to the transmission
gate labeled "X1" is high. then
the transmission path between
the two ports labeled "1" is on.
If the "X1" input is low. then
the transmission path between
the two ports labeled" 1" is off.
Only one of the 16 transmission
gates can be off while the
device is operating; which one is
off is determined by inputs PO
through P3. The lines going from
the string of transmission gates
to the Exclusive-OR gates
located above the transmission
gate that is off will be high. The
lines going to the Exclusive-OR
gates located below that
transmission gate will be low.
19
PO
1
J'>.
ff
=
~
,,',
A2
2
H
A3
,
",
3
,
",
A4
4
,
H
AS
",
S
,
",
A6
6
r=l
A7
,
",
7
,
",
A8
A9
A10
A11
A12
fI
tn
Q)
CJ
"S
Q)
c
en
o
:2E
u
::I:
8
~r4xo:J
9
11
12
13
18
y
~
~
~
,
",
)( 1
=I
~
,
" ,
en
~.
-i>-
Pin numbers shown are for OW, J, and N packages.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-589
SN54HC679, SN74HC679
12-BIT ADDRESS COMPARATORS
absolute maximum ratings over operating free-air temperature range t
•
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Va < 0 or Va > Vee) ............................. ±20 mA
Continuous output current, 10 (Va = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: DW or N package .............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under" absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC679
Vee Supply voltage
Vee
Vee
VIH High·level input voltage
Vee
Vee
Vil
low·level input voltage
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
1.5
4.2
0
0.9
1.2
0
1.2
Vee
Vee
1000
0
0
Vee
Vec
1000
V
V
0
500
0
500
ns
0
400
0
400
-55
125
-40
85
0
Output voltage
0
tt
Input transition (rise and fall) times
TA
0
Operating free-air temperature
V
4.2
0.3
Input voltage
Vee
V
0
0
=2V
= 4.5 V
=6V
1.5
3.15
UNIT
0
0
Vo
Vee
l
If
j/
3.15
VI
Vee
SN74HC679
MIN
<>
"
0.3
0.9
0
V
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
6V
5.9
5.999
VI
=
=
VIH or Vll,
10H
-4 mA
4.5 V
3.98
4.30
VIH or VIL,
10H
=
=
6V
5.48
=
20 pA
VOL
VI - VIH or VIL,
2-590
1.9
4.5 V
10l
VI
VI
=
=
VIH or VIL.
Vee orO
10l - 4 mA
10l
=
VI - Vee or O. 10 - 0
5.2 mA
MIN
4.4
5.9
-20 pA
VIH or Vll,
SN74HC679
4.4
5.9
=
=
MAX
1.998
1.9
10H
VI
MIN
4.4 4.499
VIH or Vll,
-5.2 mA
SN54HC679
1.9
=
VI
lee
ei
TA - 25·
TVP MAX
VI
VOH
II
MIN
3.7
5.2
5.80
2V
0.002
0.1
4.5 V
0.001
0.1
6V
0.001
0.1
4.5 V
0.17
0.26
6V
0.15
0.26
6V
±0.1
±100
6V
2 to 6 V
3
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 65501.2 • DALLAS, TEXAS 75265
iff
"
UNIT
V
3.84
5.34
;>
if! 0.1
0.1
0.1
0.1
0.1
0.4
0.33
jj
S
MAX
0.1
V
0.4
0.33
±1000
±1000
nA
8
160
80
pA
10
10
10
pF
SN54HC679, SN74HC679
12-81T ADDRESS COMPARATORS
switching characteristics over recommended operating free-air temperature range junless otherwise
noted), CL - 50 pF
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
Any P
y
tpd
Any A
Y
tpd
tt
G
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
y
Y
Power dissipation capacitance
TA - 25 GC
MIN
TVP MAX
185
300
37
60
31
51
105
160
21
32
18
27
75
125
15
25
13
21
38
60
8
12
10
6
SN54HC679
MIN MAX
450
90
76
i:~
i,187
No load. TA = 25°C
41
37
31
90
18
15
SN74HC679
MIN MAX
375
75
64
200
40
34
156
31
26
75
15
13
40 pF typ
UNIT
no
no
no
•
U)
CD
no
U
oS
CD
c
en
o
:E
CJ
J:
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TeXAS 75265
2-591
SN54HC679, SN74HC679
12·BIT ADDRESS COMPARATORS
TYPICAL APPLICATION INFORMATION
The 'HC67S can be wired to recognize anyone of 212 addresses. The number of "lows" in the address
determines the input pattern for the P inputs. Then those system address lines that are low in the address to
be recognized are connected to the lowest numbered A inputs of the address comparator and the system address
lines that are high are connected to the highest numbered A inputs.
For example, assume the comparator is to enable a device when the 12-bit system address is:
•
J:
A 11 A 10 AS
H
H
L
c:;'
A5
A4
L
L
A3
H
A2
H
A1
H
AO
H
System address lines AS, A8, A5, and A4 to comparator inputs A 1 through A4 in any convenient order.
oen
<
A6
H
P3 to 0 V, P2 to Vcc, P1 to 0 V, and PO to 0 V.
3:
(1)
A7
H
L
Since the address contains 4 lows and 8 highs, the following connections are made.
o
o
A8
The remaining eight system address lines to comparator inputs A5 through A 12 in any convenient order.
The output provides an active-low enabling signal.
The following circuit is a register bank decoder that examines the 14 most significant bits lAO through A 13)
of a 20-bit address to select banks corresponding to the hex addresses 10000, 10040, 10080, and 100CO.
(1)
CI)
ADDRESS
MEMEN
SYSTEM
ADDRESS
LINES
AO(MSB)
TOA19
AO •.. A2
A4 •.. All
A3
A12
A13
0
COMP
'G ....
I
PO
VCC
Pl
P2
~
11
I
I
I
I
Al ••• All
= LLLH
= LLLH
= LLLH
= LLLH
1000016
1004016
1008016
100C016
EN
:}.
12
16
LLLL
LHLL
HLLL
HHLL
LLLL
LLLL
LLLL
LLLL
XIV
(P-ll]
0
A12
1
A
B
1
2
2
1000016
1004016
1008016
lOOC016
3
111----11'----------------------50-.-.-.S_5-+~
REGISTER BANK DECODER
2-592
LLLL
LLLL
LLLL
LLLL
1/2
'HC139
6
A14 ... A19
8
LLLL
LLLL
LLLL
LLLL
::::...-
~
.-
4
TEXAS . .
INSTRUMENTS
POST OFFICE BOX -655012 • DALLAS. TEXAS 75265
}
64X N·BIT
REGISTERS
SN54HC682. SN14HC682
8·BIT MAGNITUDE COMPARATORS
02804, MARCH 1984-REVISEO JUNE 1989
•
SN54HC6B2 ... J PACKAGE
SN74HC6B2 •.. OW OR N PACKAGE
Compares Two 8-Bit Words
•
100-kO Pullup Resistors are on the Q Inputs
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
(TOPVIEWI
Vee
P>O
PO
00
P1
01
P2
02
P3
03
Dependable Texas Instruments Quality and
Reliability
description
These magnitude comparators perform
comparisons of two eight-bit binary or BCD
words. The 'HC682 features 100-kO pullup
termination resistors on the Q inputs for analog
or switch data.
p=o
07
P7
06
P6
05
P5
04
P4
GND
II
en
CD
CJ
'S
SN54HC682 •.. FK PACKAGE
CD
c
(TOP VIEW)
The SN54HC682 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC682 is
characterized for operation from - 40°C to
85°C.
en
OO/\UII
10 UIO
o
Oa.a.>a.
3
P1
01
P2
02
P3
logic symbol t
2
:E
1 2019
4
18
5
17
6
16
8
14
15
u
07
P7
06
P6
05
:::t
9 1011 1213
MOo
po
(9)
(12)
(14)
(16)
(18)
0
7
tThis symbol is in accordance with ANSIIIEEE Std 91·1984 and
lEe Publication 617·12.
dacu....n
UNL£SS OTHERWISE IOTED Ihis
coatal..
PRODUCTIOM DATA informlli.. .urroot "' 01
puIIIicltlan dati. Pnduots ..nform to .....ifi..mplr thl _
01 T.... lnatru....ts lII.dlrd
...
:::t:u":~.J',:""---
lot--'ly
Copyright @ 1989. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 15265
2-593
SN54HC682. SN74HC682
8·BIT MAGNITUDE COMPARATORS
logic diagram (positive logic)
)o-_ _ _ _ _ _ _(:.:;19:.!.) P=Q
II
:::J:
(")
3:
oen
cCD
<
~r
CD
en
2-594
TEXAS •
INSTRUMENTS
POST OFFICE BOX 66.6012 • DAL.LAS. TEXAS 75265
SN54HC682, SN74HC682
8-BIT MAGNITUDE COMPARATORS
absolute maximum ratings over operating free-air temperature range t
Supply voltage range, Vee ........................................... - 0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (VO < 0 or Vo > Vee) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package .............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC682
MIN NOM MAX
Vee Supply voltage
VIH
High-level input voltage
2
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
VIL
Low-level input voltage
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
TA
Operating free-air temperature
1.5
3.15
4.2
Vee = 2 V
Vee = 4.5 V
0
0
Vee = 6 V
0
0
0
6
It
i::'
/5
0
-55
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2
5
6
1.5
3.15
<~:.
~¥
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
5
SN74HC682
MIN NOM MAX
•
UNIT
V
V
4.2
0.3
O.g
0
0
0.3
O.g
1.2
0
0
0
1.2
Vee
vee
1000
500
400
125
0
0
0
-40
V
Vee
Vee
1000
V
V
500
n.
400
85
·e
2-595
SN54HC682, SN74HC682
8·BIT MAGNITUDE COMPARATORS
electrical charactedstics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VI
= VIH or VIL,
10H
=
-20 p.A
VOH
•
VI = VIH or VIL,
VI - VIH or VIL,
VI
l:
s:
o
en
o
CD
<
c:)'
(I)
10H = -4 mA
10H- -5.2mA
10L
= 20 p.A
VOL
IIH
VI = VIH or VIL,
VI = VIH or VIL,
VI - VCC
IlL
VI
ICC
VI - VCC orO
10 = 0
(')
CD
= VIH or VIL,
10L
10L
= 4 mA
= 5.2 mA
Q Inputs, 'HC682
=0
TA - 25°C
TYP MAX
MIN
1.9 1.998
4.4 4.499
5.9 5.999
3.98 4.30
5.80
5.48
0.002
0.1
0.001
0.1
0.001
0.1
0.17
0.26
0.15
0.26
0.1
100
-50
-90
-0.1 -100
vcc
TEST CONOITIONS
All other inputs
2V
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
6V
6V
'HC682
0.1
0.4
0.4
()
1000
-160
-1000
SN74HC682
MIN MAX
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
1000
-140
-1000
,::;:'"
/fO.l
0.1
f""
2'
r:
de
UNIT
V
V
nA
p.A
nA
480
700
1300
1100
~A
3
10
10
10
pF
2 to 6 V
Ci
SN54HC682
MIN MAX
1.9
4.4
5.9
3.7
5.2 ~
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL "" 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
P or Q
Any
tt
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
TYP MAX
MIN
275
A,,130
55
47
75
•
3:
15
13
w~
Power dissipation capacitance
No load, TA - 25 De
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2-596
SN54HC682
MIN MAX
413
88
70
110
22
19
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74HC682
MIN MAX
344
69
58
95
19
16
40 pF typ
UNIT
ns
ns
SN54HC688. SN74HC688
8-BIT IDENTITY COMPARATORS
02684. DECEM8ER 1982-REVISED SEPTEM8ER 1987
SN54HC688 ... J PACKAGE
SN74HC688 ... OW OR N PACKAGE
•
Compares Two S-Sit Words
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
ITOP VIEWI
Dependable Texas Instruments Quality and
Reliability
description
These
identity
comparators
perform
comparisons of two eight-bit binary or BCD
words. An enable input (G) may be used to force
the output to the high level.
The SN54HC688 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC688 is
characterized for operation from - 40°C to
85°C.
(2)
PI
(4)
P2
(6)
P3
(8)
07
01
06
P2
P6
02
05
P3
P5
03
04
GND
P4
o
•
tn
II)
u
'S;
II)
c
u
ul
dII
en
d lrl\.? > a..
3
01
18
5
17
6
7
16
15
14
8
EN
o
2 1 20 19
4
:iE
CJ
J:
P6
05
9 1011 12 13
0
MOq-q-1t)
dza..da..
\.?
FUNCTION TABLE
P
P4.!!!L
P5 (13)
INPUTS
DATA
ENA8LE
P6 lIS)
P7 (17)
7
00
131
0
01
IS)
02
(7)
03
(9)
P=O
P=O
OUTPUT
P=Q
P.Q
p=o
G
L
L
p>o
H
p Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Va < 0 or Va > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 mA
Continuous current through Vee or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package .............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute~maximum-rated conditions for extended periods may affect device reliabilitv.
recommended operating conditions
Vee Supply voltage
Vee
VIH
VIL
High-level input voltage
Low-level input voltage
Vee
Vee
Vee - 2 V
Vee = 4.5 V
Vee
VI
Vo
Input voltage
tt
Input transition (rise and faU) times
TA
Operating free-air temperature
2-598
=2V
= 4.5 V
=6V
=
6 V
Output voltage
Vee
Vee
Vee
=2V
= 4.5 V
=6V
SN54HC688
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0.9
1.2
0
0
0
0
0
-55
Vee
Vee
1000
TEXAS . "
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
UNIT
V
V
4.2
0
0
0
INSTRUMENTS
SN74HC688
MIN NOM MAX
2
5
6
1.5
3.15
500
400
125
0
0
0
0
0
0
0
0
-40
0.3
0.9
1.2
Vee
Vee
1000
500
400
85
V
V
V
ns
·e
SN54HC688, SN74HC688
8-BIT IDENTITY COMPARATORS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
VI = VIH or VIL,
10H = -20
~A
VI = VIH or VIL,
VI - VIH or VIL,
VI = VIH or VIL,
10H = -4 rnA
10H - -5.2 rnA
10L = 20~
VOL
VI = VIH or VIL,
VI = VIH or VIL,
II
VI = VCC or 0
ICC
Cj
VI = VCC or 0,
10L = 4 rnA
10L = 5.2 rnA
SN54HC688
MIN
MAX
SN74HC688
MIN
1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
4.5V
5.9
5.999
5.9
5.9
3.98
4.30
3.7
3.84
6V
5.48
2V
VOH
TA = 25 D C
MIN
TYP MAX
1.9
5.2
5.80
MAX
UNIT
V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
4.5 V
0.001
0.1
0.1
0.1
0.17
0.26
0.4
6V
0.15
0.26
0.4
0.33
0.33
6V
±0.1
±100
±1000
±1000
nA
160
80
~A
3
8
10
10
10
pF
6V
10 = 0
2 to 6 V
II
5.34
2V
V
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL
50 pF (see Note 1)
=
PARAMETER
tpd
tpd
tt
FROM
(lNPUTI
P or Q
G
TO
(OUTPUTI
P=Q
P=Q
Any
VCC
TA = 25 DC
MIN
TVP MAX
SN54HC688
MIN
MAX
SN74HC688
MIN
MAX
2V
113
210
313
4.5 V
30
42
63
53
6V
2V
24
53
179
45
66
36
120
151
4.5 V
16
24
36
30
6V
14
20
30
26
2V
38
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance
No load, TA = 25 DC
UNIT
265
n.
n.
n'
40 pF typ
Note 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-599
E
J:
(")
~
o(f)
c
~
<
c:r
~
Cfj
2-600
SN54HC805, SN74HC805
HEX 2·INPUT NOR DRIVERS
02805, MARCH 1984-REVISEO SEPTEMBER 1987
•
High-Current Output8 Can Drive Up to 15
LSTTL Loads
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
SNS4HC80S ... J PACKAGE
SN74HC805 , .. OW OR N PACKAGE
ITOPVIEW)
•
Vee
1A
18
1Y
2A
28
2Y
3A
38
3Y
Dependable Texas Instruments Quality and
Reliability
description
These devices contain six independent 2-input
NOR drivers. They perform the Boolean functions
y = A+B or Y =
in positive logic.
68
6A
6Y
58
5A
5Y
48
4A
4Y
GND
"·S
•
(I)
CD
0>U
SN54HC805 .•. FK PACKAGE
The SN 54HC805 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC805 is
characterized for operation from - 40°C to
85°C.
CD
o
ITOPVIEW)
U
~ ~ ~ ~m
U)
3
::E
o
2
o
1 20 19
18
FUNCTION TABLE
16
OUTPUT
15
14
X
Y
L
H
L
INPUTS
A
B
H
X
l
l
H
9 1011 12 13
logic symbol t
lA
lB
2A
2B
3A
38
(I)
(2)
logic diagram (positive logic)
;'1[>
lY
l A = D - lY
lB
(4)
(S)
2Y
2 A = D - ZY
2B
(7)
(8)
I1Z)
(13)
4B
(15)
SA
(16)
SB
(18)
6A
(19)
6B
::E:
17
lEACH DRIVER)
3Y
3 A = D - 3Y
3B
4A
4Y
5Y
4 A = D - 4Y
4B
BY
SA~
5B~SY
t This symbol is in accordance with ANSIIIEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for OW. J, and N packages.
6 A = D - 6Y
6B
Copyright © 1984. Texas Instruments Incorporated
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-601
SN54HC805, SN74HC805
HEX 2·INPUT NOR DRIVERS
absolute maximum ratings over operating free·air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
eontinuous current through Vee or GND pins. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . .. 300 0 e
Lead temperature 1,6 mm (1/16 in) from case for 10 s: DW or N package. . . . . . . . . . . . .. 260 0 e
Storage temperature range ......................................... - 65 °e to 1 50 0 e
::c
o
~
orn
c
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HCB05
MIN NOM MAX
Vee Supply voltag'e
Vee
Vee
Vee
Vee
Vee
(I)
<
n"
VIH
High-level input voltage
VIL
Low-level input voltage
(I)
en
Vee
VI
Vo
Input voltage
tt
Input transition (rise and fall) times
2
1.5
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Vee
3.15
4.2
0.3
0
0
=2V
= 4.5 V
=6V
Operating free-air temperature
TA
6
3.15
4.2
Output voltage
Vee
Vee
5
0
0
0
0
0
0
-55
SN74HCB05
MIN NOM MAX
2
5
6
1.5
0.9
1.2
UNIT
V
V
0
0
0.3
0.9
1.2
V
Vee
0
0
Vee
Vee
1000
0
0
Vee
1000
V
V
500
400
125
0
0
-40
500
400
ns
85
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
Vce
2V
VI
=
VI
VI
= VIH
= VIH
VI
=
IOH
=
- 20 p.A
or VIL,
or VIL,
10H
10H
=
=
-6 mA
-7.8 mA
VIH or VIL.
10L
=
VIH or VIL.
VOH
20 p.A
VOL
II
lee
Ci
2-602
VI - VIH or VIL.
VI = VIH or VIL.
VI = Vce or 0
VI - Vee or O.
10L - 6 mA
10L = 7.8 mA
10 - 0
TA - 25°C
MIN
TVP MAX
1.9 1.998
4.5 V
6V
4.5 V
4.4 4.499
5.9 5.999
3.98
4.30
6V
2V
4.5 V
5.48
6V
4.5 V
6V
6V
5.80
0.002
0.001
0.001
0.17
0.15
±0.1
6V
2 to 6 V
3
SN54HC805
MIN MAX
1.9
4.4
5.9
3.7
5.2
SN74HC805
MIN MAX
1.9
4.4
5.9
3.84
5.34
V
0.1
0.1
0.1
0.1
0.1
0.1
0.26
0.26
0.4
0.4
0.1
0.33
0.33
±100
8
10
±1000
160
10
±1000
80
10
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
0.1
0.1
V
nA
p.A
pF
SN54HCB05, SN74HCB05
HEX 2-INPUT NOR DRIVERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
FROM
TO
(INPUT)
(OUTPUT)
A or B
Y
. . . . . - - - - - - - r_ _ _ _
TA = 25°C
MIN
SN54HC805
MIN
MAX
SN74HC805
TYP
MAX
MIN
MAX
2V
4.5 V
6V
2V
4.5 V
31
95
145
120
10
19
29
24
8
16
25
20
28
60
90
75
8
12
18
15
6V
6
10
15
13
UNIT
ns
------r-~......-----::-------,
Any
tt
Vcc
Power dissipation capacitance per gate
No load, T A = 25°C
ns
40 pF typ
•
en
CD
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
tpd
tt
FROM
TO
(INPUT)
(OUTPUT)
A or B
Y
Any
VCC
TA = 25°C
MIN
SN54HC805
TYP
MAX
2V
44
180
4.5 V
6V
2V
14
11
4.5 V
6V
MIN
MAX
SN74HC805
MIN
MAX
275
225
36
55
45
31
47
39
45
210
315
265
17
42
63
53
13
36
53
45
UNIT
ns
U
'S
CD
c
en
o
::iE
(J
ns
J:
Note 1; Load circuits and voltage waveforms are shown in Section 1.
TEXAS
"J1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-603
E
:t
o
s:
oen
oCD
<
ri"
CD
en
2-604
SN54HC808. SN74HC808
HEX 2·INPUT AND DRIVERS
02804, MARCH 1984-REVISED SEPTEMBER 1987
•
High-Current Outputs Can Drive Up to 15
LSTTL Loads
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
SN54HC808 •.. J PACKAGE
SN14HC808 ... OW OR N PACKAGE
(TOPVIEWI
•
Dependable Texas Instruments Quality and
Reliability
description
These devices contain six independent 2-input
AND drivers. They perform the Boolean
functions Y = A· B or Y = A + B in positive logic.
H
l
X
H
X
l
lB
2A
2B
3A
3B
4A
4B
SA
5B
6A
6B
111
Q)
c
en
U
>-IXI«UIXI
__ .... ><0
3
o
18
5
17
6
16
15
Y
H
::?!
o
2 1 2019
4
OUTPUT
8
6A
6Y
58
5A
5Y
::x:
L
l
logic diagram (positive logic)
lA~
&[>
(21
lB~lY
(41
2A~(41
(51
(61 2Y
(51
m
2B
3A~
(81
3B~3Y
(121
(131
4A~(121
(lSI
(131
(111 4Y
48
(161
(151
5A~
(141
(1BI
58 (161
(191
5Y
6A~
6B~-···6Y
tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and
lEe Publication 617-12.
PRODUCTION OATA d•••m......ntai. in'.rmation
.urra.t •••, publi.ation date. Pr.ducts _Iorll ta
spacilicati... par til. terms ., T.... 1........11
=rJ;"{,':'~7i
"$
(TOP VIEWI
2A
logic symbol t
lA
Q)
CJ
(EACH DRIVERI
INPUTS
U)
SN54HC808 ... FK PACKAGE
FUNCTION TABLE
B
68
6A
6Y
58
5A
5Y
48
4A
4Y
GND
The SN54HC808 is characterized for operation
over the full military temperature range of
- 55 DC to 125°C. The SN74HC808 is
characterized for operation from - 40 DC to
85°C.
A
Vee
1A
18
1Y
2A
28
2Y
3A
38
3Y
=::::.r:.,,::::"~
oot
TEXAS
"I}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
Copyright © 1984, Texas Instruments Incorporated
2-605
SN54HC808, SN74HC808
HEX 2·INPUT AND DRIVERS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through Vee or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package .............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
::J:
t'Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute·maximum·rated conditions for extended periods may affect device reliability.
(")
s:
of/)
c
recommended operating conditions
SN54HCSOS
MIN NOM MAX
Vee Supply voltage
(1)
<
Cr
(1)
VIH
High·level input voltage
Vee = 2 V
Vee = 4.5 V
Low·level input voltage
Vee = 6 V
Vee = 2 V
Vee = 4.5 V
(I)
VIL
2
1.5
3.15
4.2
Vee = 6 V
VI
Vo
Input voltage
tt
Input transition (rise and fall) times
Output voltage
Vee - 2 V
Vee = 4.5 V
2
1.5
3.15
4.2
5
6
UNIT
V
V
0
0.3
0
0.3
0.9
1.2
0
0
0
0
0
0
0.9
1.2
V
Vee
V
V
Vee
Vee
1000
500
400
0
0
-55
Operating free-air temperature
6
0
0
0
0
0
Vee = 6 V
TA
5
SN74HCSOS
MIN NOM MAX
125
Vee
1000
500
400
0
-40
85
ns
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
VI = VIH or VIL.
10H = -20 p.A
VI = VIH or VIL.
VI = VIH or VIL.
IOH = -6 mA
IOH = -7.8 mA
VI = VIH or VIL,
IOL = 20 p.A
4.5 V
6V
VI = VIH or Vil.
VI = VIH or VIL,
VI = Vee orO
IOL=6mA
IOL = 7.S mA
4.5 V
6V
6V
VI - Vee or O.
10 - 0
VOH
VOL
II
lee
ei
2-606
4.5 V
6V
4.5 V
6V
2V
TA - 25°C
MIN
TYP MAX
1.9 1.99S
4.4 4.499
5.9 5.999
3.9S
4.30
5.48
5.80
0.002
0.001
SN54HCSOS
MIN MAX
1.9
4.4
5.9
3.7
5.2
0.1
0.001
0.17
0.15
±0.1
0.1
0.1
0.1
0.1
0.1
0.26
0.26
±100
0.4
0.4
±1000
3
8
10
160
10
6V
2 to 6 V
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS. TEXAS 75265
SN74HCSOS
MIN MAX
1.9
4.4
5.9
3.S4
5.34
UNIT
V
0.1
0.1
0.1
0.33
0.33
±1oo0
SO
10
V
nA
~A
pF
SN54HC808. SN74HC808
HEX 2·INPUT AND DRIVERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
Ipd
It
FROM
(INPUT!
A or B
TO
(OUTPUT)
Y
y
vCC
2V
4.5 V
6V
2V
4.5 V
6V
Power dissipation capacitance per gate
TA = 25°C
MIN
TYP MAX
50
100
10
20
8
17
28
60
8
12
10
6
No load, TA
SN54HCBOB
MIN MAX
150
30
25
90
18
15
= 25°C
SN74HCBOB
MIN MAX
125
25
21
75
·15
13
20 pF typ
UNIT
ns
ns
fI
en
Q)
Note 1: Load circuits and voltage waveforms are shown in Section 1.
CJ
oS
Q)
c
en
o
:e:
(.)
::I:
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-607
J:
(")
s::
oen
c
CD
<
c:;"
CD
til
2-608
SN54HC832, SN74HC832
HEX 2-INPUT OR DRIVERS
02804, MARCH 1984-REVISED SEPTEMBER 1987
•
High-Current Outputs Can Drive Up to 15
LSTTL Loads
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic JOO-mil
DIPs
•
SN54HC832 ..• J PACKAGE
SN74HC832 ... DW OR N PACKAGE
(TOPVIEWI
Dependable Texas Instruments Quality and
Reliability
Vee
18
68
lY
6A
2A
6Y
28
58
2Y
5A
3A
5Y
38
3Y
48
GND
4Y
description
These devices contain six independent 2-input
OR drivers. They perform the Boolean functions
Y = A + B or Y = A·S in positive logic.
lA
SN54HC832 ... FK PACKAGE
The SN54HC832 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC832 is
characterized for operation from - 40°C to
85°C,
(TOP VIEWI
U
l>-ID<{ UID
~~~>CD
3
FUNCTION TABLE
(EACH DRIVERI
INPUTS
OUTPUT
A
B
Y
H
X
H
X
H
H
L
L
L
4B
5A
58
6A
68
17
6Y
2Y
6
16
58
3A
7
15
5A
8
14
5Y
t:J
;;'11>
(51
171
3A
4A
6A
5
""2'<1''<1''<1'
(4)
3B
18
28
l>-Ol>-<{ID
(2)
2B
1 2019
4
logic diagram (positive logic)
lA (11
2A
2
2A
9 1011 12 13
logic symbol t
lB
II
4A
111
(31 ,y
lA~
(61 2y
2A~
lB~lY
28~2Y
(91 3Y
(81
(7)
(121
3A~
(111 4y
(13)
3B~3Y
(151
(12)
4A~4Y
(14) 5Y
(16)
4B~
(18)
(17) 6Y
(19)
1151
5A~
58~5Y
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
IEC Publication 617-12.
(181
6A~171
(191
6Y
6B
PRODUCTION DATA documents ..ntain information
current a. of publication data, Products .onform to
opacification. per tbe term. of T.... Instruments
==~i;;-rn~I~"
=::i:; :.r:::~:~"
nat
Copyright
TEXAS .",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
© , 984, Texas Instruments Incorporated
2-609
SN54HC832, SN74HC832
HEX 2-INPUT OR DRIVERS
absolute maximum ratings over operating free-air temperature range t'
1&
Supply voltage, Vcc ..... :. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vce) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or N package . . . . . . . . . . . . .. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Vee Supply voltage
VIH
High-level input voltage
VIL
Low·level input voltage
Vee
Vee
Vee
Vee
Vee
Vee
VI
Vo
Input voltage
tt
Input transition (rise and fall) times
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Vee
Operating
TA
free~air
SN74HC832
MIN NOM MAX
3.15
4.2
3.15
4.2
0
0
Output voltage
Vee
Vee
SN54HC832
MIN NOM MAX
2
5
6
1.5
=2V
= 4.5V
=6V
temperature
0
0.3
0.9
1.2
0
0
0
Vee
Vee
1000
0
0
-55
500
400
125
2
1.5
5
6
UNIT
V
V
0
0.3
0.9
1.2
0
0
0
0
0
0
0
-40
V
V
V
Vee
Vee
1000
500
ns
400
85
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
2V
VI
= VIH
or VIL.
10H
=
-20
~A
VOH
VI - VIH or VIL.
VI = VIH or VIL.
VI
= VIH
or VIL.
10H
10H
10L
=
=
-6 mA
-7.8 mA
= 20 p.A
VOL
II
lee
ei
2-610
VI - VIH or VIL.
VI = VIH or VIL.
VI = Vee or 0
VI = Vee or O.
10L - 6 mA
10L = 7.8 mA
10
=0
TA - 25°C
MIN
TYP MAX
1.9 1.998
4.5 V
6V
4.5 V
4.4 4.499
5.9 5.999
3.98
4.30
6V
2V
4.5 V
5.48
6V
4.5 V
6V
6V
6V
2 to 6 V
5.80
0.002
0.001
0.001
0.17
0.15
±0.1
3
SN54HC832
MIN MAX
1.9
4.4
5.9
3.84
5.2
0.1
0.1
0.26
0.26
V
5.34
0.1
0.1
0.1
0.1
0.1
0.1
±100
0.4
0.4
±1000
0.33
0.33
±1000
8
10
160
10
80
10
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
4.4
5.9
3.7
0.1
SN74HC832
MIN MAX
1.9
V
nA
~A
pF
SN54HC832, SN74HC832
HEX 2-INPUT OR DRIVERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
IOUTPUT)
Ipd
A or B
Y
It
TO
Y
VCC
2V
4.5 V
6V
2V
4.5 V
6V
Power dissipation capacitance per gate
TA = 25°C
TYP MAX
MIN
SN54HC832
100
20
17
60
12
10
150
30
25
90
18
15
50
10
8
28
8
6
MIN
No load, TA = 25°C
Note 1: load circuits and voltage waveforms are shown in Section 1.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
MAX
SN74HC832
MIN
MAX
125
25
21
75
15
13
20 pF typ
UNIT
n.
n.
•
2-611
E
2-612
SN54HC4002, SN74HC4002
DUAL 4·INPUT POSITIVE·NOR GATES
D2684, DECEMBER 1982-REVISED SEPTEMBER 1987
•
•
SN54HC4002 ... J PACKAGE
SN74HC4002 ... 0 DR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
(TOP VIEW)
1Y
1A
1B
1C
10
NC
GNO
Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent 4-input
positive NOR gates. They perform the Boolean
functions..,:_---;:--,....-;,,-----,;::Y = A + B + C + DorY = ~.~.~.5
in positive logic.
VCC
2Y
20
2C
2B
2A
NC
SN54HC4002 ... FK PACKAGE
(TOP VIEW)
u
« ......
>-uu>Z>N
The SN54HC4002 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC4002 is
characterized for operation from - 40°C to
85°C.
2
1 2019
4
18
5
17
16
FUNCTION TABLE
)NPUTS
A
lC
10
2A
28
2C
20
14
OUTPUT
9 1011 1213
Y
uouu«
X
L
L
H
C
H
X
X
X
H
X
X
X
H
X
X
L
L
L
ZZZZN
t:l
L
NC-No internal connection
L
L
logic diagram (positive logic)
(2)
lA
lB
18
15
8
0
X
X
X
H
B
logic symbol t
lA
7
(2)
~~
.. 1
(3)
i=ji3i
(4)
(5)
2A -;.(9:::;);-:--.-_.....
2B (10)
(4)
2C (11)
(5)
20--'-"::!-......- -
(9)
(10)
(11)
(12)
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
PRODUCTION DATA do.umanu.ontain Information
.urrant as of publintion date. Products .onform to
spacifi.ations par tba tarm. of T.... Instrumonu
:=~':u';"[:~~t,Ti
=:i:l':Ilo=:.:':ta":."
oat
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © , 982. Texas Instruments Incorporated
2-613
SN54HC4002. SN74HC4002
DUAL 4·INPUT POSITIVE·NOR GATES
absolute maximum ratings over operating free·air temperature range t
II
::s::::
()
s:o
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300 0 e
Lead temperature 1,6 mm (1/16 in) from 'case for lOs: 0 or N package ............... 260 DC
Storage temperature range ......................................... - 65 DC to 1 50 DC
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute·maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC4002
en
c
Vee Supply voltage
<
VIH
CD
(;'
High-level input voltage
Vee - 2 V
Vee = 4.5 V
Low-level input voltage
Vee = 6 V
Vee = 2 V
Vee = 4.5 V
CD
en
VIL
Vee = 6 V
Input voltage
Output voltage
VI
Vo
Vee = 2 V
Vee = 4.5 V
Input transition (rise and fall) times
tt
Vee = 6 V
Operating free-air temperature
TA
MIN
2
1.5
3.15
4.2
NOM
MAX
5
6
0
0
0.3
0.9
1.2
0
0
0
0
0
0
-55
Vee
Vee
1000
500
400
125
SN74HC4002
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0.9
1.2
UNIT
V
V
0
0
0
0
0
0
0
Vee
Vee
1000
500
ns
0
-40
400
85
°e
V
V
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
~A
VI = VIH or VIL.
10H = -20
VI = VIH or VIL.
VI = VIH or VIL.
10H = -4 rnA
10H = -5.2 rnA
VI = VIH or VIL.
10L = 20
VOH
~A
VOL
II
lee
ei
2-614
VI
VI
VI
VI
=
=
=
=
VIH or VIL.
VIH or VIL.
Vee orO
Vee or O.
IOL=4mA
10L = 5.2 rnA
10 = 0
TA - 26°C
TYP MAX
MIN
2V
4.5 V
6V
4.5 V
6V
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.48
5.80
2V
4.5 V
6V
0.002
0.001
4.5 V
6V
6V
6V
2 to 6 V
0.001
0.17
0.15
±0.1
3
SN64HC4002 SN74HC4002
MIN MAX
MIN MAX
1.9
1.9
4.4
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.26
0.26
±100
2
10
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5.9
3.84
5.34
0.1
0.1
UNIT
V
0.1
0.1
0.1
0.1
0.4
0.4
±10oo
0.33
0.33
±1000
V
nA
40
10
20
10
~
pF
SN54HC4DD2, SN74HC4DD2
DUAL 4·INPUT POSITIVE·NOR GATES
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(lNPUTI
A thru 0
TO
(OUTPUT)
V
V
Vee
2V
4.5 V
6V
2V
4.5 V
6V
Power dissipation capacitance per gate
TA = 25°C
MIN
TVP MAX
44
110
12
22
11
19
75
38
15
8
13
6
SN54HC4002 SN74HC4002
MIN MAX
MIN MAX
165
140
33
28
28
24
110
95
22
19
19
16
No load, TA = 25°C
Note 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
25 pF typ
UNIT
n.
n.
•
2·615
J:
(')
3:
ot/)
o
CD
<
cr
CD
t/)
2-616
SN54HC4016. TLC40161
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
JANUARY 1986
•
SN54HC4016 •.. J OR N PACKAGE
TlC40161 ... 0 OR N PACKAGE
High Degree of Linearity
•
High On-Off Output Voltage Ratio
•
low Crosstalk Between Switches
•
low On-State Impedance of 50 Ohms Typ
at VCC - 9 V
•
Individual Switch Controls
•
Extremely low Input Current
ITOPVIEWI
1A
19
29
2A
2C
3C
GND
VCC
1C
4C
4A
49
39
3A
II
description
The TlC4016 is a silicon-gate CMOS quadruple
analog switch integrated circuit designed to
handle both analog and digital signals. Each
switch permits signals with amplitudes up to
12 volts peak to be transmitted in either
direction.
logic symbol t
lC
lA 111
2C
151
2A 141
0
n
Xl
1
1
4A
1111
n
121
n
n
131
n
n
191
n
n
1101
161
3C
3A 181
1121
4C
Each switch section has its own enable input
control. A high-level voltage applied to this
control terminal turns on the associated switch
section.
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and digital-toanalog conversion systems.
1131
CD
(J
1B
'S;
2B
C
3B
0
48
0
J:
CD
0
~
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 61 7 -12.
The SN54HC4016 is characterized for operation
from - 55°C to 125°C, and the TlC40161 is
characterized from - 40°C to 85 DC.
logic diagram (positive logic)
A
B
C
PRODUCTION DATA doc.mants contain information
current 8S of publication date. Products conform to
specifications per the terms of Texas Instruments
:~~~~:~~i~a{::I~~i ~!::i~~ti:; :.~o:::::.::-:s not
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-617
SN54HC4016, TLC40161
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
absolute maximum ratings over operating free-air temperature range (unless otherwise notedl
Supply voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5 V to 15 V
Control-input diode current (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
1/0 port diode current (VI < 0 or Vila < VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
On-state switch current (Vila = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
o package ......................................................... 950 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package ......................................................... 875 mW
Operating free-air temperature, T A: SN54HC4016 ....................... - 55°C to 125°C
TLC40161 ........................... -40°C to 85°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: 0 and N packages ....... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300°C
•
:x:
o
3:
o
til
NOTES:
C
1. All voltages are with respect to ground unless otherwise specified.
2. For operation above 25°C free-air temperature, see Dissipation Derating Table.
CD
<
5"
DISSIPATION DERATING TABLE
CD
Maximum Power Dissipation
Package
rn
25°C
85°C
125°C
494 mW
D
950 mW
J
1025 mW
533 mW
205 mW
N
875 mW
455 mW
175 mW
Derating
Factor
7.6 mW/oe
8.2 mW/oe
7.0 mW/oe
recommended operating conditions
Supply voltage, Vee
110 port voltage. VIIO
High-level input voltage, VIH
Low-level input voltage. VIL
Input rise time, tr
Input fall time. tf
Operating free-air temperature, T A
Vee - 2 V
vee ~ 4.5 V
MIN
NOM
MAX
2t
5
12
V
0
Vee
V
1.5
3.15
Vee
vee
Vee
~
9 V
6.3
Vee
Vee
~
12V
8.4
Vee ~ 2 V
0
Vee
0.3
Vee - 4.5 V
0
0.9
Vee - 9 V
Vee ~ 12 V
0
0
1.8
2.4
Vee
~
2 V
Vee
~
4.5 V
500
Vee
~
9 V
400
Vee
~
2 V
1000
UNIT
V
V
1000
Vee - 4.5 V
500
Vee ~ 9 v
400
SN54He4016
-55
125
TLe40161
-40
85
ns
ns
°e
tWith supply voltages at or near 2 volts, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital
signals be transmitted at these low supply voltages.
2-618
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC4016, TLC40161
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
IS
~
1 rnA,
VA ~ OtoVee,
See Figure 1
On-state switch
rSon
IS
resistance
VA
~
=
1 rnA,
o or Vee,
See Figure 1
VA
resistance matching
See Figure 1
VI
II
Control input current
lee
ei
On-state switch
VA ~ OorVee,
leakage current
See Figure 3
Input capacitance
capacitance
10
=
0
A or B
e
A to B
t All typical values are at TA
VI
=
0
100
220
100
200
105
9V
50
120
50
12 V
3D
100
30
85
2V
120
240
120
215
4.5 V
50
120
50
100
9V
35
BO
35
75
12 V
20
70
20
60
4.5 V
10
20
10
20
9V
5
15
5
15
12 V
5
15
5
15
±1
±1
±0.1
±0.1
to
UNIT
n
II
n
#A
5.5 V
±10
±600
±10
±600
9V
±15
±BOO
±15
±BOO
12 V
VI ~ 0 or Vee,
Supply current
TlC40161
Typt
MAX
MIN
4.5 V
6V
25°e
leakage current
Feedthrough
Cf
=
SN54HC4016
Typt
MAX
MIN
2 V
0 or Vee
Vs = ±Vce,
See Figure 2
Off-state switch
ISon
=
0 to Vee,
VI - 0 or Vee,
TA
ISoff
=
On-state switch
Vce
± 20 ± 1000
5.5 V
±10
± 150
±10
± 150
9V
±15
±200
±15
±200
12 V
±20
±300
±20
±300
5.5 V
2
40
2
20
9 V
B
160
B
BO
12 V
16
320
16
160
2 V to
15
12 V
5
2 V to
12 V
5
15
10
nA
± 20 ± 1000
5
5
10
nA
#A
pF
pF
25°e.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75266
2-619
SN54HC4016, TLC40161
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
switching characteristics over recommended operating free·air temperature range, CL
otherwise noted)
PARAMETER
TEST CONDITIONS
vCC
SN54HC4016
Typt
MAX
MIN
Propagation delay time,
ton
See Figure 4
A to B or B to A
RL
Switch turn-on time
~
1 kll,
See Figures 5 and 6
:x:
o
s:o
en
c
CD
<
toft
RL
Switch turn-off time
~
1 kll,
See Figures 5 and 6
75
4.5 V
5
15
5
13
9V
4
14
4
12
12 V
3
13
3
11
Ichannel loss
~
~.
tn
to any switch, peak to peak
2V
32
150
32
125
8
30
8
25
9V
6
18
6
15
12 V
5
15
5
13
2V
45
252
45
210
4.5 V
15
54
15
45
9V
10
48
10
40
45
8
38
8
100
100
9 V
120
120
See Figure 7
4.5 V
180
See Figure 8
4.5 V
1
UNIT
62
4.5 V
12 V
3 dB)
Control feedthrough voltage
VOCFIPP)
25
4.5 V
Switch cutoff frequency
fco
TLC40161
Typt
MAX
MIN
25
2V
tpd
= 50 pF (unless
ns
ns
ns
MHz
180
mV
Frequency at which crosstalk
attenuation between any two
1
switches equals 50 dB
t All typical values are at T A ~ 25°C.
PARAMETER MEASUREMENT INFORMATION
VCC
C
VI ~ VCC
X1
A 1
VA
TEST
SWITCH
1
B
'::'
+-IS
FIGURE 1. ON-STATE RESISTANCE TEST CIRCUIT
VCC
C X1
VI - 0
TEST
SWITCH
Vs
B
VB
= VA - VB
CONDITION 1: VA - 0, VB - VCC
CONDITION 2: VA - VCC. VB - 0
FIGURE 2. OFF-STATE SWITCH LEAKAGE CURRENT TEST CIRCUIT
2-620
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75266
MHz
SN54HC40 16, TLC40161
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
VCC
C X1
VI - VIH
A
B
TEST
SWITCH
1
VA
.".
FIGURE 3. ON-STATE SWITCH LEAKAGE CURRENT TEST CIRCUIT
•
U)
Q)
CJ
VCC
'S;
Q)
VI
TEST
t-=B;...:O;;.;.R.;..:A..-VO
SWITCH
A OR B 1.-_
1
_ _ _--1
~50PF
C
CI.)
o
:E
o
TEST CIRCUIT
J:
VI
frO-%-----~'1\I~~-----~~'
_____. J
A OR B
I
I
I
I
~tpd
B
~~
tpd
14
I
I
..J/~·
A_ _ _ _ _ _ _
~
I
I
~~~"
VOLTAGE WAVEFORMS
FIGURE 4. PROPAGATION DELAY TIME. SIGNAL INPUT TO SIGNAL OUTPUT
TEXAS ,.,
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
2-621
SN64HC4016, TLC40161
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
VCC
VI
C X1
A
":"
1 k!J
TEST
SWITCH
'1 OF 41
':"
B
Vo
-:r
5OPF
TEST CIRCUIT
:::t
o
;,.O%---------------k~
s:
o
en
c(1)
<
ri"
(1)
en
_ _ _- J
I
14
-------
-V"
I
,,,.
~I
ton - tpZL
tott - tPLZ
14
OV
I/"
~I
'V"
Vo
\\.,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _.:II}10.! _ _ --VOL
VOLTAGE WAVEFORMS
FIGURE 5, SWITCHING TIME (tPZL. tPLZI. CONTROL TO SIGNAL OUTPUT
2-622
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
SN54HC4016, TLC40161
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
VCC
VI
C Xl
A
1=-....--4..-.VO
50pF
lkO
TEST CIRCUIT
---"'"
-------VCC
\\,,0%_____ 0V
I
toff=tPHZ~
--1
I
9 0%---VOH
'-=OV
VOLTAGE WAVEFORMS
FIGURE 6. SWITCHING TIME (tPZH, tPHZ), CONTROL TO SIGNAL OUTPUT
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-623
SN54HC4016, TLC40161
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
VCC
Xl
VI
TEST
SWITCH
(1 OF 4)
Vo
600 n
150 PF
.".
.".
.".
TEST CIRCUIT
:::t
11
o
s:o
en
cCD
VI _ _ _ _ _
90%'1\-'- - - - - - - - - V
90 %
. ;,;10;.;,%~{ !
! \10%
I
J4-t1-tr
c------j
<
n'
CD
en
,1,..;..;;,.;;....-----0 V
........ tf
V o - - - - - - - t ___________
~
_______
VOLTAGE WAVEFORMS
FIGURE 7. CONTROL FEEDTHROUGH VOLTAGE
VCC
Xl
----+--i
V I -.....
X2
600 n
2
TEST
SWITCH
(1 OF 4)
TEST
SWITCH
(1 OF 4)
V01
600 Il
.".
2
V02
600 !l
150 PF
.".
NOTE: ADJUST f for aX _
V02
.".
- 50 dB.
VOl
FIGURE 8. CROSSTALK BETWEEN ANY TWO SWITCHES, TEST CIRCUIT
2-624
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 15265
~T"
SN54HC4017, SN74HC4017
DECADE COUNTERS/DIVIDERS
02684, DECEMBER 1982-REVISED JUNE 1989
SN54HC4017 ... J PACKAGE
SN74HC4017 ... N PACKAGE
•
Carry-Out Output for Cascading
•
Divide-by-N Counting
•
DC Clock Input Circuit Allows Slow Rise
Times
•
Package Options Include Ceramic Chip
Carriers and Standard Plastic and Ceramic
300-mil DIPs
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEW)
Y5
Y1
YO
Y2
Y6
Y7
Y3
VCC
ClR
ClK
ClKEN
CO
Y9
Y4
YB
GND
fI
description
U)
The 'HC40 17 is a 5-stage divide-by-1 0 Johnson
counter with ten decoded outputs and a carryout bit, High-speed operation and spike-free
outputs are obtained by use of the Johnson
decade counter configuration,
The ten decoded outputs are normally low and
go high only at their respective decimal time
periods. A high signal on CLR asynchronously
clears the decade counter and sets the carry
output and VO high. With CLKEN low, the count
is advanced on a low-to-high transition at CLK.
Alternatively, if CLK is high, the count is
advanced on a high-to-Iow transition at CLKEN.
Each decoded output remains high for one full
clock cycle. The carry output CO is high while
YO, V1, V2, V3, or V4 is high, then is low while
V5, V6, V7, VB, or V9 is high.
Q)
SN54HC4017 ... FK PACKAGE
(TOP VIEW)
ll> U
CJ
"S;
Ua:
Q)
U-J
o
(I)
o
>->-z>U
3
2
1 20 19
Y2
5
17
NC
6
16
Y6
Y7
7
15
ClK
ClKEN
NC
CO
8
14
Y9
18
:!:
u
J:
9 1011 12 13
MOUCX)q.
>-zz>->\.?
NC -No internal connection
logic symbol t
The SN54HC4017 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC4017 is
characterized for operation from -40°C to
85°C.
CTR DIV 101
DEC
(3)
0
(2)
Y2
2
+
CLK
3
4
5
(7)
(10)
(1)
(5)
6
(15)
CLR
CT'"II
Vl
(4)
&
CIi-- >C1
R
ClR
~
....--..
I
L~
--
R
L
I
>-- >C1
J:
n
-
s:o
en
-
c(1)
-e-
-<
~
<
-
>C1
L
R
-
(1)
U)
I--...-
L;-~
I
~ >C1
R
,.....,...
-
I
L;-
(4)
(7)
~
10
C;"
(2)
--
-r
(1)
(5)
(S)
(9)
(11)
VO
V1
V2
V3
V4
V5
VS
V7
VB
V9
' - - - >C1
R
-
(12)
Pin numbers shown are for J and N packages.
2-626
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
co
SN54HC4017, SN74HC4017
DECADE COUNTERS/DIVIDERS
typical clear, count, and inhibit sequences
ENABLE ____________________________________________~r--l~----YO~------,L
•
______________________________~r__1L~__~______
Yl:J~~
________________________
L-
__J
_____~r__1~______________________________~~
Y2--'
_I
U)
r
___________~r-l
-I
Y3--'
Q)
U
"S
Y4--' __________~r_l~______________~~_____
OUTPUTS
Q)
o
en
o
-I
YS--' ____________~r_l~____________~~~___
-I
Y6 - , ________________~r_lL__________~__~____
:E
-I
(.)
1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~r_1~________~~----Y7-'
-I
:c
Y8 --, ____________________~r_l~_____+__~---I
yg--'
_I
________________________
~r_l~
I
~~
______
, t1.-
CARRY - ,
OUTPUT ---l
CLEAR
___
INHIBIT
~
~-------COUNT-----------
COUNT
absolute maximum ratings over operating free-air temperature range t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) .... ,........................ ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: N package .................... 260°C
Storage temperature range ......................................... - 65°C to 1 50°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
TEXAS
-1!1
INSTRUMENlS
POST OFFICE BOX 655012· DALLAS, TeXAS 75265
2-627
SN54HC4017, SN14HC4017
DECADE COUNTERS/DIVIDERS
recommended operating conditions
Vee Supply voltage
•
V,H
High-level input voltage
V,L
Low-level input voltage
Vee
Vee
Vee
Vee
Vee
Vee
Vo
Input voltage
Output voltage
tt
Input transition (rise and falll times
TA
Operating free·air temperature
V,
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Vee - 2 V
Vee = 4.5 V
Vee = 6 V
SN54HC4017
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0
0
0.9
1.2
0
0
Vee
0
Vee
1000
0
500
0
400
0
-55
125
SN74HC4017
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0
0.3
0
0.9
1.2
0
0
Vee
0
Vee
0
1000
0
500
0
400
-40
85
UNIT
V
V
V
V
V
n.
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
V,
= V,H
or V,L.
10H
=
VCC
-20 p.A
VOH
V, = V,H or V,L.
V, - V,H or V,L.
V,H or V,L.
10L
=
20 ~A
V, = V,H or V,L.
V, = V,H or V,L.
V, - Vee or 0
V, = Vee or O.
10L
10L
=
=
4 rnA
5.2 rnA
'0
=0
V,
=
10H = -4 rnA
10H - -5.2 rnA
VOL
I,
lee
ei
2-628
2V
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 to 6 V
TA - 25°C
MIN
TYP MAX
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.48
5.80
0.002
0.1
0.1
0.001
0.001
0.1
0.17
0.26
0.15
0.26
±0.1 ±100
8
10
3
TEXAS ..,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC4017 SN74HC4017
MIN MAX
MIN MAX
1.9
1.9
4.4
4.4
5.9
5.9
3.7
3.84
5.2
5.34
0.1
0.1
0.1
0.1
0.1
0.1
0.4
0.33
0.4
0.33
±1000
±1000
160
80
10
10
UNIT
V
V
nA
p.A
pF
SN54HC4017. SN74HC4017
DECADE COUNTERS/DIVIDERS
timing requirements over recommended operating free-air temperature raflge (unless otherwise noted)
PARAMETER
fclock
Vcc
ClKt or ClKENi
Clock frequency
ClK hi9h or low t or
ClKEN high or low~
Pulse duration
tw
ClR high
TA
MIN
ClK!t or ClK high
before ClKEN.i
Setup time
tsu
CLR inactive before
ClK!t or ClKEN.i
ClKEN low after
ClK!t or ClK
Hold time
'h
high after ClKEN.i
SN54HC4017
MAX
MIN
MAX
SN74HC4017
MIN
MAX
2V
4,5 V
0
6
0
4,2
0
5
0
31
0
20
0
25
6V
0
36
0
25
0
29
2V
4,5 V
80
120
25
16
14
20
17
2V
80
120
100
4,5 V
16
14
24
20
20
17
75
15
63
13
2V
4,5 V
50
10
UNIT
MHz
100
20
6V
6V
ClKEN low before
= 25°C
6V
9
13
11
2V
4,5 V
50
75
63
10
15
6V
9
13
13
11
2V
4,5 V
5
5
5
5
6V
5
5
5
5
5
II
ns
U)
Q)
(J
'S;
ns
Q)
c
en
o
:!
ns
()
:::t:
tThese conditions apply if clocking is being performed via the elK input.
iThese conditions apply if clocking is being performed via the ClKEN input,
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
tpd
ClK
ClKEN
Any Y or CO
Any Y or CO
tplH
tt
ClR
ClR
Any Y
CO
Any output
MAX
SN74HC4017
MIN
MAX
6
10
50
20
25
36
55
90
25
29
230
343
4,5 V
23
46
69
58
6V
20
39
58
49
2V
125
250
373
315
4,5 V
25
21
50
75
63
43
54
2V
4,5 V
90
230
63
343
23
46
69
58
6V
20
39
58
49
290
6V
tpd
MIN
31
6V
2V
tpd
SN54HC4017
4,2
2V
4,5 V
f max
TA = 25°C
MIN
TYP MAX
5
MHz
290
2V
90
230
343
23
46
69
58
6V
20
39
58
49
2V
4,5 V
38
75
110
8
6
15
22
95
18
13
19
16
Power dissipation capacitance
No load, TA = 25°C
ns
ns
290
4,5 V
6V
UNIT
ns
ns
ns
60 pF typ
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
~
TEXAS
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-629
E
::I:
n
s:
oen
C
CD
<:
c;'
CD
(I)
2-630
SN54HC4020. SN74HC4020
ASYNCHRONOUS 14·BIT BINARY COUNTERS
02684. DECEMBER 1982-REVISED JUNE 1989
•
•
SN54HC4020 ... J PACKAGE
SN74HC4020 ... Dt OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
ITOP VIEWI
Dependable Texas Instruments Quality and
Reliability
Ql
VCC
QM
QN
QK
QJ
QH
QI
ClR
QF
QE
description
QG
QD
GND
These devices are 14-stage binary ripple-carry
counters that advance on the negative-going
edge of the clock pulse. The counters are reset
to zero (all outputs low) independently of the
clock when CLR goes high.
II
ClK
QA
en
SN54HC4020 ... FK PACKAGE
ITOPVIEW)
The SN54HC4020 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC4020 is
characterized for operation from -40°C to
85°C.
Q)
(.)
'S;
tl '"
:2; --'
u
3
1 20 19
Q)
o
OOZ>O
2
5
17
6
16
QJ
QH
NC
14
QI
ClR
4
logic symbol:!:
8
RCTR14
en
o
:E
(,)
J:
9 10 11 12 13
OA
QD
ClR (11)
CT=O
Oe
OF
NC - No internal connection
QG
ClK 110)
tContact the factory for D availability.
QH
CT
(14)
115)
111
12)
13)
13
QI
QJ
OK
Ql
Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only r and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
'S
SN54HC4020
Vee
Vee
Vee
Vee
VIL
low-level input voltage
Vee
Vee
VI
Vo
NOM
MAX
2
5
6
Vee
Vee
Operating
free~air
;j.i
MAX
2
5
6
o
:E
V
o
4.2
0
0.9
0
0.9
0
h
1.2
0
1.2
0
>i
Vee
0
Vee
V
Vee
1000
0
vee
1000
V
ns
<,
en
V
0.3
<~.
c
UN'T
0
o
temperature
NOM
0.3
0
=2V
= 4.5 V
=6V
MIN
1.5
3.15
;~'/
4.2
0
Vee
TA
1.5
3.15
'nput voltage
Output voltage
Input transition (rise and fall) times
tt
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Q)
SN74HC4020
MIN
Vee Supp'y voltage
VIH
en
Q)
U
recommended operating conditions
High-level input voltage
fI
0
0
500
0
500
0
400
0
400
-55
125
-40
85
::t
V
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
SN54HC4020 SN74HC4020
MIN
MAX
MIN
2V
1.9 1.998
1.9
1.9
V,
=
V'H or V'L.
'OH
=
-20 p.A
4.5 V
4.4 4.499
4.4
4.4
V,
=
V'H or VIL.
'OH
IOH
=
=
-4 rnA
4.5 V
3.98
6V
5.48
6V
VOH
VI - V'H or VIL.
V,
=
V'H or V'L.
'OL
=
-5.2 rnA
20 p.A
VOL
V,
'I
lee
ej
TA - 25°C
MIN
TYP MAX
=
=
V'H or V'L.
V,
V'H or V'L.
V, - Vee or 0
V,
=
Vee or O.
IOL
IOL
'0
=
=
4 rnA
5.2 rnA
=0
5.9 5.999
5.80
0.002
0.1
4.5 V
0.001
0.1
6V
0.001
0.1
4.5 V
0.17
0.26
6V
0.15
0.26
6V
±0.1
±100
TEXAS
'
..;>
::::
.<
..
UNIT
V
3.84
5.34
0.1
0.1
0.1
0.1
0.1
0.4
0.33
0.1
V
0.4
0.33
±1000
±1000
nA
8
160
80
10
10
10
p.A
pF
6V
3
5.9
3.7"
5.2 ,;:
2V
2 to 6 V
~>
5.9
4.30
MAX
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
%.
2-633
SN54HC4020, SN74HC4020
ASYNCHRONOUS 14·B11 BINARY COUNTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
CLK high
or low
Pulse duration
tw
CLR high
::J:
o
s::
o
tn
o
CD
Setup time. CLR inactive before CLK~
tou
TA = 2SOC
MIN
MAX
SNS4HC4020 SN74HC4020
MIN MAX
MIN MAX
5.5
0
3.7
0
4.3
0
28
0
22
33
0
J;
0
0
0
25
2V
0
4.5 V
6V
2V
4.5 V
90
18
6V
135.1
MHz
115
27
23
15
23
20
no
10~/
90
2V
70
4.5 V
14
6V
12
2V
60
12
'Ilo
4.5 V
18
75
15
6V
10
15
13
2$
~.
UNIT
18
no
25
no
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
<
n'
CD
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
tn
f max
tpd
tpHL
tt
CLK
CLR
QA
Any
Any
TA = 25°C
TYP MAX
MIN
5.5
10
4.5 V
28
45
19
6V
33
53
22
3.7
2V
62
150
4.5 V
16
6V
12
30
26
2V
63
140
4.5 V
17
28
6V
13
24
2V
28
75
4.5 V
8
6
15
6V
Power dissipation capacitance
No load.
TA = 25°C
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TeXAS 75265
22
,.f:
fi
if
UNIT
4.3
MHz
25
,§125
190
45
38
38
32
210
175
42
35
36
30
110
95
22
19
19
16
j!
13
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2-634
SNS4HC4020 SN74HC4020
MIN MAX
MIN MAX
88 pF typ
no
no
no
SN54HC4024, SN74HC4024
ASYNCHRONOUS 7-BIT BINARY COUNTERS
02804. MARCH 1984-REVISEO JUNE 1989
•
•
SN54HC4024 ..• J PACKAGE
SN74HC4024 ... D OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
(TOP VIEW)
CLK
VCC
NC
CLR
Dependable Texas Instruments Quality and
Reliability
description
°G
°A
OF
OE
NC
OB
00
The 'HC4024 is an asynchronous 7-stage binary
counter designed with an input pulse-shaping
circuit. The outputs of all stages are available
externally. A high clear signal asynchronously
clears the counter and resets all outputs low. The
count is advanced on the high-to-Iow transition
of the clock pulse. Applications include timedelay circuits, counter controls, and frequencydividing circuits.
FJ
Oc
NC
GNO
SN54HC4024 ... FK PACKAGE
(TOP VIEW)
5:::iutlu
uuz>z
3 2 1 20 19
The SN54HC4024 is characterized for operation
over the full military temperature range of
- 55°C to 125 °C. The SN74HC4024 is
characterized for operation from - 40°C to
85°C.
OG
NC
4
18
5
17
OA
NC
OF
6
NC
OE
8
16
OB
15
NC
14
NC
9
ClClUU U
ozzzo
(!)
logic symbol t
NC - No internal connection
tThis symbol is in accordance with ANSI/IEEE SId 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
PRODUCTION DATA documants contain information
currant as of publication date. Products conform to
specifications per the terms of Texas Instrumants
:::=~i~ai~:'~~i ~=:~ti:; :'lo:.a;::::9t:'~ nut
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1989, Texas Instruments Incorporated
2-635
\
SN54HC4024. SN74HC4024
ASYNCHRONOUS 7·B11 BINARY COUNTERS
logic diagram (positive logic)
:c
o
s:o
en
c
CD
<
rr
CD
Pin numbers shown are for D, J. and N packages.
typical clear and count sequence
ClR
126 1 2 7 !
(I)
2
3
4
5
6
I
7
ClK
I
I
I
I
I
~~~~~
QA _ _ _ _+--t
I
I
I
I
QB_--+-+-S-~_S--"L ~ ~~ ~
QC
--7-+---J......-------,~ ~ ~ ~ ~ ~
I
I
I
I
I
I
I
I
I
I
I
I
QD_~-+---------'~~~~ ~
----- Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current. 10K (Va < 0 or Va > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Continuous output current. 10 (Va = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1.6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1.6 mm (1/16 in) from case for 10 s: D or N package ............... 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
II
U)
CD
U
recommended operating conditions
'S:
SN74HC4024
SN54HC4024
Vee Supply voltage
High-level input voltage
low-level input voltage
5
6
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
0
Vee
0
Vee
V
0
Vee
1000
0
0
Vee
1000
V
0
500
0
400
0
500
400
n.
0
-55
125
-40
85
°e
4.5 V
= 4.5 V
=6V
Vee
=2V
= 4.5 V
=6V
0
Operating free-air temperature
CI)
V
o
1.5
0
Vee
TA
2
CD
C
UNIT
Vee - 2 V
Vee
Input transition (rise and fall) times
6
MAX
4.2
Vee
tt
5
NOM
3.15
Vee
Va
2
MIN
4.2
2V
Input voltage
Output voltage
VI
MAX
6 V
Vee
Vee
Vil
NOM
1.5
3.15
Vee
VIH
=
=
=
MIN
~
V
(,)
J:
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
.
PARAMETER
TEST CONDITIONS
VI
=
VIH or Vil.
IOH
=
VCC
-20,.A
VOH
VI - VIH or Vil.
VI
=
IOH
=
-5.2 rnA
SN54HC4024 SN74HC4024
MIN
MAX
MIN
2V
1.9 1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
5.9 5.999
5.9
5.9
3.7
3.84
4.5 V
3.98
6V
5.48
4.30
5.80
5.2
MAX
5.34
2V
0.002
0.1
0.1
0.1
0.1
0.1
0.1
IOl
=
20 ~A
4.5 V
0.001
0.1
0.1
0.1
IOL
=
4 rnA
6V
4.5 V
0.001
VI - VIH or Vll,
0.17
0.26
0.33
VI - VIH or Vil.
IOl - 5.2 rnA
VOL
II
VI
lee
ej
VI
= Vee
= Vee
orO
orO.
10
=0
UNIT
V
VIH or Vll,
VI
=
VIH or Vll,
-4 rnA
IOH -
TA - 25°C
MIN
TVP MAX
V
6V
0.15
0.26
0.4
0.4
6V
±0.1
±100
±1000
±1000
nA
160
80
~A
3
8
10
10
10
pF
6V
2 to 6 V
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
0.33
2-637
SN54HC4024. SN74HC4024
ASYNCHRONOUS 7-BIT BINARY COUNTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
Clock frequency
2V
4.5 V
0
0
5.5
28
0
90
18
15
33
Pulse
duration
6V
2V
4.5 V
6V
2V
fclock
ClK high or low
II
tw
ClR high
:t
o
s:
o
Setup time. ClR low
before ClKI
tsu
TA = 25°C
MIN
MAX
4.5 V
6V
80
16
14
2V
4.5 V
80
16
6V
14
SN54HC4024 SN74HC4024
MIN MAX
MIN MAX
0
3.7
0
4.3
0
19
0
22
0
135
27
22
23
120
0
115
23
20
100
24
20
120
24
20
20
17
100
20
17
UNIT
MHz
25
ns
ns
ns
C/)
o
CD
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
<
(;'
PARAMETER
CD
FROM
(INPUT)
TO
IOUTPUT)
o
QA
f m• x
VCC
2V
4.5 V
6V
tpd
IpHl
II
ClK
ClR
QA
Any
QA
TA - 25°C
MIN
TYP MAX
5.5
10
28
33
2V
4.5 V
6V
2V
4.5 V
6V
2V
50
60
56
16
12
61
17
Power dissipation capacitance
22
120
8
6
TEXAS
32
28
75
39
33
110
15
13
22
19
Nolo.d, TA = 25°C
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2-638
150
30
26
22
,If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
UNIT
MHz
26
180
36
31
195
24
20
130
13
28
4.5 V
6V
SN54HC4024 SN74HC4024
MIN MAX
MIN MAX
3.7
4.3
22
19
ns
26
165
95
19
16
40 pF typ
ns
ns
SN54HC4040, SN74HC4040
ASYNCHRONOUS 12-BIT BINARY COUNTERS
02684, DECEMBER 1982-REVISED JUNE 1989
•
•
SN54HC4040 , .. J PACKAGE
SN74HC4040, . , Dt OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
(TOP VIEW)
Ol
OF
OE
OG
Dependable Texas Instruments Quality and
Reliability
00
description
•
01
Oc
OB
GNO
This device is an asynchronous 12-stage binary
counter with the outputs of all stages available
externally, A high level at ClR asynchronously
clears the counter and resets all outputs low. The
count is advanced on a high-to-Iow transition at
ClK. Applications include time delay circuits,
counter controls, and frequency-dividing circuits,
ClR
ClK
OA
SN54HC4040 ... FK PACKAGE
(TOP VIEW)
U
LL...IUU,",
OOz>O
The SN54HC4040 is characterized for operation
over the full military temperature range of
-55°C to 125°C, The SN74HC4040 is
characterized for operation from - 40°C to
85°C,
3
2
1 20 19
4
18
5
17
6
16
15
14
8
logic symbol:!:
OJ
OH
NC
O(
ClR
9 1011 1213
RCTR12
alO U
OB
CT=O
oCt'"'
0t§ZOd
OA
CLR (11)
VCC
OK
OJ
OH
NC - No internal connection
Qc;
tContact the factory for 0 availability
00
OE
OF
CT
(13)
(12)
(14)
(15)
11
(1)
°G
OH
01
OJ
OK
OL
;This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617·12.
Pin numbers shown are for D. J. and N packages.
PRODUCTION DATA d••umants ...tai. ilfa,,,"lio.
of , ••IICltio. dill, p,otIueto comnn ta
1HCIfI.1tio1. PI' do••or... of TUI. Inlltrull.nts
aionUni
Praductio. p"_il. d•• nit
_,11y I....... taotJ•• of .11 pa_rs.
••,,,1It •
WI"""".
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright @ 1989, Texas Instruments Incorporated
2-639
SN54HC4040, SN74HC4040
ASYNCHRONOUS 12-BIT BINARY COUNTERS
logic diagram (positive logic)
%
(")
:s:
oen
c
CD
<
C)'
CD
(I)
Pin numbers shown are for Of J, and N packages.
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ± 20 rnA
Continuous output current, 10 (Vo = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 rnA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Lead temperature 1,6 mm (1116 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6. mm (1/16 in) from case for 10 s: D or N package ................ 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2-640
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC4040, SN74HC4040
ASYNCHRONOUS 12·BIT BINARY COUNTERS
recommended operating conditions
SN54HC4040
Vce Supply voltage
Vee
VIH
High-level input voltage
Vee
Vee
VIL
Vee
Vee
Low-level input voltage
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
SN74HC4040
MIN
NOM
MAX
2
1.5
5
6
MIN
NOM
MAX
2
5
6
UNIT
V
1.5
3.15
3.15
4.2
4.2
V
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
VI
Input voltage
0
Vee
0
Vee
V
Va
Output voltage
0
0
V
0
Vee
1000
0
Vee
1000
500
0
500
ns
0
400
0
400
-55
125
-40
85
tt
Input transition (rise and fall) times
TA
Operating free-air temperature
Vee
Vee
Vee
=2V
= 4.5 V
=6V
0
•
V
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
vCC
2V
VI
=
VIH or VIL.
=
10H
-20,.A
VOH
VI
=
VIH or VIL.
VI - VIH or VIL.
VI
=
VIH or VIL.
10H
=
-4 rnA
-5.2 rnA
10H 10L
=
20,.A
VOL
II
lee
ei
=
=
VIH or VIL.
10L
VI
VIH or VIL.
VI - Vee or 0
10L
VI
VI
=
Vee or O.
10
= 4 rnA
= 5.2 rnA
=0
TA - 25°C
MIN
TYP MAX
1.9
SN54HC4040 SN74HC4040
MIN
MAX
MIN
1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
5.9 5.999
5.9
5.9
3.7
3.84
4.5 V
3.98
6V
5.48
4.30
5.80
5.2
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
6V
0.15
0.26
0.4
0.33
±0.1
±100
±1000
±1000
nA
8
160
80
10
10
10
,.A
pF
6V
2 to 6 V
3
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V
2-641
SN54HC4040, SN74HC4040
ASYNCHRONOUS 12·BI1 BINARY COUNTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
Vec
fclock
Clock frequency
tw
Pulse duration
ClK high or low
ClR high
Setup time, ClR inactive before CLKt
tsu
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
5.5
0
0
28
0
33
90
18
15
70
14
12
60
12
10
SN54HC4040 SN74HC4040
MIN MAX
MIN MAX
0
3.7
0
4.3
0
19
0
22
0
22
0
25
135
115
27
23
23
20
105
90
21
18
18
15
90
75
18
15
15
13
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
ClK
QA
IpHl
ClR
Any
II
Any
Vce
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Power disSipation capacitance
SN54HC4040 SN74HC4040
TA = 25°C
MIN
TYP MAX
MIN MAX
MIN MAX
3.7
5.5
10
4.3
28
45
19
22
33
53
22
25
62
150
225
190
16
30
45
38
12
32
26
38
63
140
210
175
17
42
35
28
13
36
24
30
75
28
110
95
15
8
22
19
19
16
6
30
No load, TA
Note 1: Load circuits and voltage waveforms are showri in Section 1.
2-642
TEXAS . "
INsrRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
=
25°C
88 pF Iyp
UNIT
MHz
ns
ns
ns
SN54HC4060, SN74HC4060
ASYNCHRONOUS 14-STAGE BINARY COUNTERS
AND OSCILLATORS
02684, DECEM8ER 1982-REVISED JUNE 1989
•
Allows Design of Either RC or Crystal
Oscillator Circuits
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC4060 • , • J PACKAGE
SN74HC4060, , • Dt OR N PACKAGE
(TOP VIEW)
QL
QM
QN
QF
QE
QG
QO
GNO
description
The 'HC4060 consists of an oscillator section
and 14 ripple-carry binary counter stages. The
oscillator configuration allows design of either
RC or crystal oscillator circuits. A high-to-Iow
transition on the clock input increments the
counter. A high level at CLR disables the
oscillator (CKO goes high and CKO goes low) and
resets the counter to zero (all Q outputs low).
VCC
QJ
QH
QI
CLR
CKI
CKO
CKO
•
en
CD
SN54HC4060 •.• FK PACKAGE
U
(TOP VIEW)
:iE...JU
"S;
~...,
CD
c
002>0
3
The SN54HC4060 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC4060 is
characterized for operation from - 40°C to
85°C.
en
2 1 20 19
4
18
5
17
6
16
7
15
8
14
o
QH
QI
NC
CLR
CKI
:IE
CJ
:::t
9 1011 12 13
0 0 U 010
022'"''"'
Cl
logic symbol:!:
UU
NC - No internal connection
RCTR14
(7) 00
(51 0E
tContact the factory for 0 availability.
(4) OF
lJT+
(S) OG
(14) OH
CT
CLR ;..(1~2)__--iCT=O
(13) 01
9
11
(15) OJ
(1) OL
(2) OM
13
CKI.:..:(I~I):""--I
ZI
(3) ON
(9) CKO
*This symbol is in accordance with ANSI/IEEE Std 91·1984
and IEC Publication 617·12.
Pin numbers shown are for D, J, and N packages.
Copyright © 1989, Texas Instruments Incorporated
PRODUCTION DATA doc."olllloontoin infor".'io.
current II of publication data. Products CDnrnrm to
spacificatio.. per Itut larms of To... Inll.....1111
=~~~·i=:r~
==:i:;:.:,,::::::,::0
not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-643
SN54HC4060, SN74HC4060
ASYNCHRONOUS 14-STAGE BINARY COUNTERS
AND OSCILLATORS
logic diagram (positive logic)
::I:
(')
s::
oen
c
CD
<
c:;"
CD
Pin numbers are for D, J, and N packages.
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 rnA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ±20 rnA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 rnA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ................ 260°C
Storage temperature range ......................................... - 65°C to 150 0 e
U)
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Vee Supply voltage
Vee
VIH
High-level input voltage
Vee
Vee
Vee
VIL
Low-level input voltage
Vee
Vee
VI
Input voltage
Vo
Output voltage
Vee
tt
Input transition (rise and fall) times
Vee
Vee
TA
2-644
Operating free-air temperature
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
=
=
=
2V
4.5 V
6 V
SN54HC4060
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0
0.9
0
1.2
0
0
Vee
0
Vee
1000
0
0
0
-55
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
500
400
125
SN74HC4060
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0
0.3
0
0.9
0
1.2
0
Vee
0
Vee
0
1000
0
500
0
400
-40
85
UNIT
V
V
V
V
V
ns
·e
SN54HC4060, SN74HC4060
ASYNCHRONOUS 14·STAGE BINARY COUNTERS
AND OSCILLATORS
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER
VOH
VOL
TEST CONOITIONS
VCC
All
Output!
VI
VIH or VIL.
10H
=
-20 p.A
Q
VI - VIH or VIL.
10H
Output!
VI
=
=
-4 rnA
-5.2 rnA
All
Output!
Q
Outputs
II
ICC
Ci
VI
=
=
=
VIH or VIL.
VIH or VIL.
VI = VIH or VIL.
VI - VIH or VIL.
VI = VCC or 0
VI
=
VCC or O.
10H
10L = 20 p.A
IOL=4mA
10L - 5.2 mA
2V
4.5 V
6V
4.5 V
6V
TA - 25°C
MIN
TYP MAX
1.9 1.998
4.4 4.499
5.48
4.5V
6V
6V
5.80
0.002
0.1
MAX
0.001
0.001
MIN
MAX
1.9
4.4
5.9
3.84
5.2
UNIT
V
•
5.34
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.17
0.15
0.26
0.26
0.4
0.4
0.33
0.33
±0.1
±100
±1000
160
10
±1000
80
3
8
10
6V
2 to 6 V
10 = 0
MIN
1.9
4.4
5.9
3.7
5.9 5.999
3.98
4.30
2V
4.5 V
6V
SN54HC4060 SN74HC4060
0.1
10
V
fI)
CD
U
'S;
nA
p.A
pF
CD
c
en
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
VCC
fclock
CKI high
or low
tw
Pulse duration
CLR high
tsu
Setup time. CLR inactive before CKI.
SN54HC4060 SN74HC4060
MIN
MAX
MIN
MAX
3.7
19
0
0
4.3
22
0
115
25
0
5.5
0
28
6V
2V
0
0
90
4.5 V
6V
18
15
2V
4.5 V
6V
90
18
15
0
0
135
27
23
135
2V
160
4.5 V
6V
32
27
2V
4.5 V
Clock frequency
TA = 25°C
MAX
MIN
33
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
27
23
240
48
41
23
20
22
UNIT
o
:E
o
J:
MHz
ns
115
23
20
200
40
34
ns
ns
2-645
SN54HC4060, SN74HC4060
ASYNCHRONOUS 14·STAGE BINARY COUNTERS
AND OSCILLATORS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
!INPUT)
TO
(OUTPUTI
TA = 25·C
MIN
TYP MAX
5.5
10
45
28
VCC
2V
4.5 V
f max
6V
2V
:::t
tpd
CKI
QD
tpHL
CLR
Any Q
(')
s:o
tt
Any
(I)
C
33
53
240
SN54HC4060 SN74HC4080
MIN
3.7
19
22
490
4.5 V
6V
58
42
2V
4.5 V
6V
2V
4.5 V
66
98
83
140
18
14
28
28
24
75
8
6V
6
15
13
MAX
MAX
22
25
UNIT
MHz
735
147
125
615
210
175
42
36
110
35
30
95
ns
22
19
19
16
ns
No load, TA = 25·C
Power dissipation capacitance
MIN
4.3
123
105
ns
88 pF typ
CD
<
C;"
Note 1: Load circuits and voltage waveforms are shown in Section 1.
CD
en
CONNECTING AN RC OSCILLATOR CIRCUIT TO THE 'HC4060
The 'HC4060 consists of an oscillator section and 14 ripple-carry binary counter stages. The oscillator
configuration allows design of either RC or crystal oscillator circuits.
When a RC oscillator circuit is implemented, two resistors and a capacitor are required. The components are
attached to the chip as follows:
2
3
4
18
15
14
13
5
12
8
7
8
11
10
9
R2
To determine the values of capacitance and resistance necessary to obtain a specific oscillator frequency f,
the following formula is used:
2(R1)(CII 0.405 R2
R1 + R2
+ 0.693)
If R2> > R1 (i.e. R2 = 1OR1), then the above formula simplifies to:
0.455
=
2-646
""""RC
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC4061, SN74HC4061
ASYNCHRONOUS 14·STAGE BINARY COUNTERS
AND OSCILLATORS
02804. MARCH 1984-REVISEO JUNE 1989
•
Allows Design of Either RC or Crystal
Oscillator Circuits
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
SN54HC4061 ... J PACKAGE
SN74HC4061 ... Dt OR N PACKAGE
(TOPVIEWI
•
Vee
OJ
OH
O(
CLR
CK(
eKO
eKO
OL
OM
ON
OF
OE
OG
OD
GND
Dependable Texas Instruments Quality and
Reliability
description
The 'HC4061 consists of an oscillator section
and 14 ripple-carry binary counter stages. The
oscillator configuration allows design of either
RC or crystal oscillator circuits. A high-to-Iow
transition on the clock input increments the
counter. A high level at CLR resets the counter
to zero (all Q outputs low) but has no effect on
the oscillator.
fI
SN54HC4061 ... FK PACKAGE
(TOPVIEWI
::i: ...J u tl ..,
ddz>d
3
2
1 2019
18
17
The SN 54HC4061 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC4061 is
characterized for operation from - 40°C to
85°C.
16
15
14
9 1011 1213
010
00 U
dZZ:':::'::
t!l
logic symbol*
UU
NC - No internal connection
RCTR14
3
t Contact the factory for 0 availability
17) QD
(5) QE
(4) QF
l.a+
(6) QG
(14)QH
CT
CLR (:..;1~2)_---t CT=O
(13) QI
9
11
(15) QJ
(1) QL
(2) OM
CKI (11)
13
(3) QN
Zl
(9) CKO
~This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for D. J. and N packages.
PRODUCTIOI DATA docUIII8IIIS _in i.f.,mllioa
currant I. af p.~llcoti•• dltl. Praducts ...larm la
.peciflcotl••• per tlta terms of TUII Inllromants
:"'=u~·{n':J':!1.i ~::I:~:: ~r:::.:~::.~ not
Copyright © 1989. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-647
SN54HC4061, SN74HC4061
ASYNCHRONOUS 14·STAGE BINARY COUNTERS
AND OSCILLATORS
logic diagram (positive logic)
::I:
n
3:
o(I)
CKI ..;(_11..;.1_ _-f
JIO-_-ClI >_-....;.;:;.,
L..._ _ _...i(.:,;10:::1 CKO
oCD
Pin numbers shown are for D, J, and N packages.
5·
absolute maximum ratings over operating free-air temperature range t
<
CD
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins ................................ "
± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package. . . . . . . . . . . . . . .. 260°C
Storage temperature range ......................................... - 65°C to 150°C
en
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Vee Supply voltage
VIH
High·level input voltage
Vll
low-level input voltage
Vee
Vee
Vee
Vee
Vee
Vee
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and falll times
TA
Operating free-air temperature
Vee
2-648
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
=
2 V
Vee'" 4.5 V
Vee = 6 V
SN54HC4061
MIN NOM MAX
SN74HC4061
MIN NOM MAX
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-55
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-40
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5
6
0.3
0.9
1.2
Vee
Vce
1000
500
400
125
5
6
UNIT
V
V
0.3
0.9
1.2
Vee
Vcr
1000
500
400
85
V
V
V
ns
°e
SN54HC4061, SN74HC4061
ASYNCHRONOUS 14-STAGE BINARY COUNTERS
AND OSCILLATORS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
=
VIH or Vil.
IOH
=
VCC
- 20 p.A
VOH
VI
VI
VI
=
=
=
VIH or Vil.
10H
VIH or Vil.
10H
VIH or Vil.
IOl
=
=
=
-4mA
-5.2 mA
20 ~A
VOL
VI = VIH or Vil.
VI - VIH or Vil.
II
VI
ICC
Ci
VI
=
=
IOl = 4 mA
10l - 5.2 mA
VCC or 0
VCC or O.
10
=0
TA - 25°C
MIN
TYP MAX
SN54HC4061
MIN
MAX
SN74HC4061
MIN
2V
1.9 1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
5.9 5.999
5.9
5.9
3.7
3.84
4.5 V
3.98
6V
5.48
4.30
5.BO
5.2
MAX
UNIT
V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.26
0.4
6V
0.17
0.15
0.26
0.4
0.33
0.33
6V
±0.1
±100
±1000
±1000
nA
8
160
80
10
10
10
p.A
pF
6V
2 to 6 V
3
•
5.34
2V
V
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
CKI high
or low
tw
Pulse duration
ClR high
tsu
Setup time. ClR inactive before CKII
TA
MIN
= 25°C
SN54HC4061
MAX
MIN
MAX
SN74HC4061
MIN
MAX
2V
5.5
3.7
4.3
4.5 V
28
19
22
6V
33
22
25
2V
4.5 V
90
18
135
115
27
23
6V
15
23
20
115
2V
90
135
4.5 V
18
27
23
6V
15
23
20
2V
4.5 V
160
240
200
32
48
40
6V
27
41
34
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TeXAS 75265
UNIT
MHz
ns
ns
ns
2·649
SN54HC4061, SN74HC4061
ASYNCHRONOUS 14;STAGE BINARY COUNTERS
AND OSCILLATORS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL ;: 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
f max
::J:
tpd
CKI
QD
tpHL
CLR
Any Q
n
s:o
tt
Any
t/)
cCD
<
SN54HC4061 SN74HC4061
TA = 25°C
MIN
TYP MAX
MIN MAX
MIN MAX
10
3.7
4.3
5.5
28
45
19
22
33
53
22
25
240
490
735
615
147
123
58
98
42
83
125
105
66
140
210
175
18
28
42
35
14
24
36
30
28
75
110
95
15
22
19
8
16
6
13
19
Vec
No load, TA
Power dissipation capacitance
=
25°C
UNIT
MHz
no
no
no
88 pF typ
Note 1: load circuits and voltage waveforms are shown in Section 1.
c;"
CD
U)
CONNECTING ANRC OSCILLATOR CIRCUIT TO THE'HC4061
The 'HC4061 consists of an oscillator section and 14 ripple-carry binary counter stages. The oscillator
configuration allows design of either RC or crystal oscillator circuits.
When a RC oscillator circuit is implemented, two resistors and a capacitor are required. The components are
attached to the chip as follows:
1
2
3
4
.5
6
7
8
16
15
14
13
12
11
10
R2
9
To determine the values of capacitance and resistance necessary to obtain a specific oscillator frequency f,
the following formula is used:
2(R1HC)/ 0.405 R2
\ R1 + R2
+ 0.6931
If R2 >,R1 (i.e. R2 = 10R1), then the above formula simplifies to:
f
2-650
=
0.455
(R1 HC)
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC4066, TLC40661
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
D2922, JANUARY 1986
•
High Degree of Linearity
•
High On-Off Output Voltage Ratio
•
Low Crosstalk Between Switches
•
Low On-State Impedance . . .Typically
30 Ohms at VCC = 12 V
•
Individual Switch Controls
SN54HC4066 •.• J OR N PACKAGE
TLC40661 ... 0 OR N PACKAGE
ITOPVIEW)
•
Extremely Low Input Current
•
Functionally Interchangeable with National
Semiconductor MM54/74HC4066, Motorola
MC54/74HC4066, and RCA CD4066A
1A
18
28
2A
2C
3C
GND
VCC
1C
4C
4A
4B
38
3A
II
logic symbol t
en
II)
1C
description
lA
The TLC4066 is a silicon-gate CMOS quadruple
analog switch integrated circuit designed to
handle both analog and digital signals. Each
switch permits signals with amplitudes up to
12 volts peak to be transmitted in either
direction.
Each switch section has its own enable input
control. A high-level voltage applied to this
control terminal turns on the associated switch
section.
2C
2A
3C
3A
4C
4A
n
(2)
n
n
(3)
n
n
(9)
n
n
110)
(13)
(1)
15)
(4)
(6)
18)
112)
111)
Xl
n
1
1
u
lB
'S
2B
a
3B
0
II)
en
:!
U
4B
J:
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617·12.
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and digital-toanalog conversion systems.
The SN54HC4066 is characterized for operation
from - 55°C to 125°C, and the TLC40661 is
characterized from - 40°C to 85 °C.
logic diagram (positive logic)
A
B
c
PRODUCTION DATA documants contain information
currant 8S of publication data. Preducts conform to
spacificatiDlls par the tarms of TeXIS Instruments
:':-=~~i~a:::1~1i :~:~ti:r ~~o:::~:.:~~ not
Copyright @ 1986, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-651
SN54HC4066, TLC40661
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5 V to 15 V
Control-input diode current (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
I/O port diode current (VI < 0 or Vila < VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
On-state switch current (Vila = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
o package ......................................................... 950 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package ......................................................... 875 mW
Operating free-air temperature, T A: SN54HC4066 ....................... - 55°C to 125°C
TLC40661 ........................... -40°C to 85°C
Storage temperature range ......................................... - 65°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: 0 and N packages ....... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300°C
::I:
n
s:o
tn
NOTES:
1. All voltages are with respect to ground unless otherwise specified.
2. For operation above 25°C free-air temperature, see Dissipation Derating Table.
C
CD
<
5'
CD
en
DISSIPATION DERATING TABLE
Maximum Power Dissipation
Package
25°C
0
J
N
950 mW
85°C
125°C
494 mW
1025 mW
533 mW
205 mW
875 mW
455 mW
175 mW
Derating
Factor
7.6 mW/oe
8.2 mW/oe
7.0 mW/oe
recommended operating conditions
MIN
NOM
MAX
2t
5
12
V
0
Vee
V
1.5
3.15
vee
Vee - 9 V
6.3
Vee
Vee = 12. V
Vee - 2 V
8.4
Supply voltage. Vee
110 port voltage, VI/O
Vee
High-level input voltage, VIH
Low-level input voltage, VIL
Input rise time, tr
Input fall time. tf
Operating free-air temperature, T A
~
2 V
Vee - 4.5 V
Vee
0
Vee
0.3
Vee - 4.5 V
0
0.9
Vee - 9 V
0
Vee - 12 V
0
1.8
2.4
UNIT
V
V
1000
Vee - 2 V
Vee ~ 4.5 V
500
Vee - 9 V
400
Vee - 2 V
1000
Vee - 4.5 V
500
Vee - 9 V
400
SN54He4066
TLe40661
-55
125
-40
85
ns
ns
°e
tWith supply voltages at or near 2 volts, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital
signals be transmitted at these low supply voltages.
2-652
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TeXAS 75265
SN54HC4066. TLC40661
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
IS
~
1 mA,
VA~OtoVee,
See Figure 1
On-state switch
'Son resistance
IS
~
1 mA,
VA~OOrVee,
See Figure 1
On-state switch
VA~OtoVee,
resistance matching
See Figure 1
Control input current
VI ~ 0 or Vee
Vee
SN54HC4066
Typt
MAX
MIN
4.5 V
100
220
MIN
TLC40661
Typt
MAX
100
200
105
9V
50
110
50
12 V
30
90
30
85
2V
120
240
120
215
4.5 V
50
120
50
100
9V
35
80
35
75
12 V
20
70
20
60
4.5 V
10
20
10
20
9V
5
15
5
15
12 V
5
15
5
15
UNIT
Q
Q
2 V
II
or
±1
±1
~A
6V
ISolf
ISon
ICC
ej
e,
Off-state switch
Vs ~ ±Vee,
leakage current
See Figure 2
On¥state switch
VA ~ OorVee,
leakage current
See Figure 3
VI ~ 0 or Vee,
Supply current
Input capacitance
feedthrough
capacitance
10
~
0
A or B
e
A to B
t All typical values are at T A
=::
VI
~
0
5.5 V
±10
±600
±10
±600
9V
±15
±800
±15
±800
12 V
± 20 ± 1000
± 20 ± 1000
5.5 V
±10
± 150
±10
± 150
9V
±15
±200
±15
±200
12 V
±20
±300
±20
±300
5.5 V
2
40
2
20
9V
8
160
8
80
12 V
16
320
16
160
2 V to
15
12 V
5
2 V to
12 V
5
15
10
5
5
10
nA
nA
~A
pf
pF
25°C.
TEXAS •
INSTRUMENTS
POST OFF1CE BOX 655012 • DAl.LAS. TeXAS 75265
2-653
SN54HC4066. TLC40661
SILlCON·GATE CMOS QUADRUPLE .BILATERAL ANALOG SWITCH
switching characteristics over recommended operating free-air temperature range, CL
otherwise noted)
PARAMETER
TEST CONDITIONS
Vcc
SN64HC4066
Typt
MAX
MIN
2V
Propagation delay time,
tpd
ton
See Figure 4
AtoBorBtoA
RL
=
1 kll.
See Figures 5 and 6
Switch turn-on time
::a::
(')
s:o
toff
(I)
o
CD
<
RL = 1 kll.
See Figures 5 and 6
Switch turn-off time
Ichannel loss
=
VOCFIPPI
(;-
to any switch, peak to peak
25
75
15
4.5 V
5
15
5
9V
12 V
4
4
3
12
13
3
10
11
2V
4.5 V
32
150
32
125
8
30
8
25
9V
6
18
6
15
30
13
12 V
5
15
5
13
2V
4.5 V
45
15
252
54
45
15
210
45
10
40
8
38
9V
10
48
8
45
4.5 V
100
100
9V
120
120
See Figure 7
4.5 V
180
See Figure 8
4.5 V
1
3 dBI
Control feedthrough voltage
TLC40661
Typt
MAX
12 V
Switch cutoff frequency
Ico
MIN
= 50 pF (unless
UNIT
ns
ns
ns
MHz
180
mV
Frequency at wl1ich crosstalk
CD
attenuation between any two
I/)
switches equals 50 dB
t All typical values are at T A = 25
ac.
PARAMETER MEASUREMENT INFORMATION
Vcc
VI
=
C
VCC
Xl
A 1
VA
TEST
SWITCH
1
B
'=
+--IS
FIGURE 1. ON-STATE RESISTANCE TEST CIRCUIT
VCC
VI
e
=0
Xl
TEST
SWITCH
B
Vs - VA - VB
CONDITION 1: VA
CONDITION 2: VA
= O. VB - Vce
= Vee. VB = 0
FIGURE 2. OFF-STATE SWITCH LEAKAGE CURRENT TEST CIRCUIT
2-654
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
1
MHz
SN54HC4066, TLC40661
SILlCON·GATE CMOS QUADRUPLE. BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
VCC
VI -
C
VIH
Xl
A 1
B
TEST
SWITCH
":"
FIGURE 3. ON-STATE SWITCH LEAKAGE CURRENT TEST CIRCUIT
U)
CD
CJ
VCC
'S;
CD
VI
TEST
SWITCH
A OR B
Q
""B..;;O-'-'-R..;..;A...... VO
en
o
~50PF
~
TEST CIRCUIT
VI
A OR B
-
I,..O-%-------.~I-:.
-----~
I
I
n::,
::t
I
I
~Ipd
B~~A
n
o
Ipd
~
I
I
_______
_J~~.
~
I
I
~:~"
VOLTAGE WAVEFORMS
FIGURE 4. PROPAGATION DELAY TIME. SIGNAL INPUT TO SIGNAL OUTPUT
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
.2-655
SN54HC4066, TLC40661
SllICON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
VCC
C Xl
•
A
,.-----------------.
VI
tn
<
Vo
- - - - - - - - - -Vcc
\"
I '---------0 V
toll - tpLZ ~141---"~1
1144--t~~I-ton - tpZL
CD
en
1-
----' I
C
CD
50PF
TEST CIRCUIT
(")
c;"
1 j..:B=--. . .-+--VO
J
::t:
3:
0
1 kll
TEST
SWITCH
(1 OF 4\
~O%,,---_----..,;;rl/
~
iO~----VOL
VOLTAGE WAVEFORMS
FIGURE 5. SWITCHING TIME (tPZL, tPLZI. CONTROL TO SIGNAL OUTPUT
I
2·656
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75285
=Vcc
SN54HC4066, TLC40661
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
VCC
C X1
V,
A
TEST CIRCUIT
II
en
Q)
(,)
Ji: ___"
'S
VCC
Q)
c
en
VI _ _ _ _
o
I
:E
~Ion - IpZH
(.)
I
I
VOH
VO _ _ _ _ _ _JM
Uu
3
2
1 2019
18
85°C.
NC
28
NC
2C
logic symbol t
1A
1B
1C
2A
2B
2C
3A
3B
3C
(1 )
",1
(2)
(9)
fI
SN54HC4075 •.. FK PACKAGE
(TOP VIEW)
5
17
6
16
7
15
8
14
38
NC
3A
NC
3Y
9 1011 1213
1Y
>-OUU>-
(8)
NZZ~~
(!)
(3)
(4)
(6)
NC -No internal connection
2Y
(5)
FUNCTION TABLE
(11)
(10)
(12)
3Y
(13)
A
H
INPUTS
B
C
OUTPUT
Y
tThis symbol is in accordance with ANSI/IEEE Std 91·1984
and lEe Publication 617-12.
X
X
H
X
X
X
H
H
Pin numbers shown are for C, J, and N packages.
L
L
L
L
X
H
H
logic diagram (positive logic)
~:~-1Y
1C~
~~==D-2Y
~~==D-3Y
PRODUCTION DATA do.uments .ontein information
currant II of publication dill. Products conform to
specifications per the terms of TaXI. Instruments
::=:~M"i~:I":li ~,:~::i; :{,o:.,,:!:':t:~~ not
Copyright © , 982, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 ,. DALLAS. TeXAS 75265
2-659
SN54HC4075, SN74HC4075
TRIPLE 3-INPUT OR GATES
absolute maximum ratings over operating free-air temperature range t
•"
:c
3:
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) .............................± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ................ 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absoluteMrnaximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
o(I)
c
vee Supply valtage
<
VIH
High-level input valtage
Vee
Vee
Law-level input valtage
vee
Vee
Vee
CD
nCD
In
VIL
Vee
VI
Input valtage
Va
Output valtage
tt
Input transition (rise and fall) times
Vee
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
3.15
4.2
0
0
0.3
0.9
0
0
0.3
0.9
0
0
1.2
0
0
1.2
Vee
0
0
Vee
1000
0
0
-40
500
400
n.
85
·e
Vee
Vee
1000
500
400
0
0
0
=2V
= 4.5 V
=6V
0
-55
Operating free-air temperature
TA
SN54HC4075
MIN NOM MAX
2
5
6
1.5
3.15
4.2
125
SN74HC4075
MIN NOM MAX
2
5
6
1.5
UNIT
V
V
V
V
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
VI
=
VIH ar VIL.
10H
=
-20
VI
=
=
VIH or VIL.
10H
VIH ar VIL.
10H
=
=
-4 rnA
-5.2 rnA
~A
VOH
VI
VI
=
VIH ar VIL.
10L
=
VI
=
=
=
=
VIH ar VIL.
10L
10L
= 4 rnA
= 5.2 rnA
20 ~A
VOL
II
lee
ei
2-660
VI
VI
VI
VIH ar VIL.
Vee ar 0
Vee ar O.
10
=0
2V
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 ta 6 V
TA - 25°C
MIN
TYP MAX
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.48
SN54HC4075 SN74HC4075
MIN MAX
MIN MAX
1.9
1.9
4.4
5.9
3.7
5.80
0.002
0.001
0.1
0.1
0.001
0.17
0.15
±0.1
0.1
0.26
0.26
±100
3
8
10
4.4
5.9
3.84
5.2
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
UNIT
V
5.34
0.1
0.1
0.1
0.4"
0.4
±1000
160
10
0.1
0.1
0.1
0.33
0.33
±1000
80
10
V
nA
~
pF
SN54HC4075, SN74HC4075
TRIPLE 3·INPUT OR GATES
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
Ipd
A, B, or C
Y
II
Y
VCC
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
TYP MAX
100
38
11
20
9
17
75
38
15
8
13
6
Power dissipation capacitance per gate
No load, TA
=
SN54HC4075 SN74HC4075
MIN MAX
MIN MAX
150
125
30
25
25
21
110
95
22
19
19
16
25°C
26 pF Iyp
UNIT
ns
ns
fI
CI)
CD
CJ
Note 1: Load circuits and voltage waveforms are shown in Section 1"
'S
CD
c
en
o
~
CJ
:::c
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
2-661
E
J:
(")
s:
oen
ca>
<
c;'
a>
en
2-662
SN54HC4078A, SN74HC4078A
8-INPUT ORINOR GATE
02804, MARCH 1984-REVISEO SEPTEMBER 1987
•
•
SN54HC4078A , , . J PACKAGE
SN74HC407BA ... 0 OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
(TOP VIEWI
Dependable Texas Instruments Quality and
Reliability
description
These devices contain a single 8-input OR/NOR
gate and perform the following Boolean
functions in positive logic:
w
y
VCC
A
B
W
H
C
D
NC
GND
F
E
Q)
U
U
<{>-~j;~
C .5
2
3
and
A + B+ C + D + E+ F + G + H
or
Y =
tn
(TOP VIEWI
or
Y
fI
NC
SN54HC4078A ... FK PACKAGE
A+B+C+D+E+F+G+H
w
G
'S;
Q)
c
1 20 19
4
18
H
5
17
6
16
15
NC
G
NC
14
F
A • B • C ·D • E • F • G • H
en
o
:!:
::c
o
9 10 11 12 13
The SN54HC4078A is characterized for
operation over the full military temperature range
of - 55°C to 125°C. The SN74HC4078A is
characterized for operation from - 40°C to
85°C.
UOUU
ZZZZ
W
1
B (31
(11 V
C (41
o
(51
E (91
(101
F
G (111
(131
H 1121
W
tThis symbol is in accordance with ANSIIIEEE Std 91-1984
and lEe Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
PRODUCTION DATA do.umanlS .ontain information
currant I. of publication data. Products conform tD
specifications per the terms of raxas Instruments
:~~::~~i~.{::I:ri ~=~~:i:r :'~O::::::t::S not
..tf
INSTRUMENTS
TEXAS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1984. Texas Instruments Incorporated
2-663
SN54HC4078A. SN74HC4078A
8-INPUT ORIN OR GATE
absolute maximum ratings over operating free-air temperature range t
•
J:
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ................ 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(')
s::
recommended operating conditions
o(I)
cCD
Vee Supply voltage
5"
VIH
<
SN54HC4078A
MIN NOM MAX
6
2
5
High-level input voltage
Vee - 2 V
Vee = 4.5 V
Low·level input voltage
Vee
Vee
Vee
CD
(II
VIL
Vee
Vo
Input voltage
Output voltage
tt
Input transition (rise and fall) times
VI
Vee
Vee
Vee
=6V
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6v
Operating free-air temperature
TA
1.5
3.15
4.2
SN74HC4078A
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0
0
0.9
0
0
1.2
Vee
Vee
1000
0
0
0
500
400
125
0
-55
UNIT
V
V
0
0
0.3
0.9
1.2
0
0
0
0
Vee
Vee
1000
V
V
V
500
400
n.
0
-40
85
°e
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
.
PARAMETER
TEST CONDITIONS
VCC
2V
VI
=
VI
VI
= VIH
= VIH
VIH or VIL.
10H
=
-20 p.A
10H
10H
=
=
-4 rnA
VOH
or VIL.
or VIL,
-5.2 rnA
VI
=
VIH or VIL,
10L
=
VI
VI
VI
VI
= VIH or VIL.
= VIH or VIL.
= Vee orO
= Vee orO,
10L
IOL
= 4 rnA
= 5.2 rnA
20 ~A
VOL
II
ICC
ej
2-664
10
=0
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5V
6V
6V
TA - 25°C
MIN
TVP MAX
1.9 1.99B
4.4 4.499
5.9 5.999
3.98
4.30
5.BO
5.4B
0.002
0.001
1.9
4.4
1.9
4.4
5.9
3.7
5.9
3.B4
5.2
0.1
0.1
0.1
0.1
0.1
0.4
0.4
0.26
0.26
±100
3
8
10
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
UNIT
V
5.34
0.1
0.001
0.17
0.15
±0.1
6V
2 to 6 V
SN54HC4078A SN74HC407BA
MIN MAX
MIN MAX
±1000
160
10
0.1
0.1
0.1
0.33
0.33
±1000
BO
10
V
nA
p.A
pF
SN54HC4018A, SN14HC4018A
8·INPUT ORINOR GATE
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(INPUTI
A thru H
TO
(OUTPUTI
YfW
Y/W
VCC
2V
4.5 V
6V
2V
4.5 V
6V
Power dissipation capacitance per gate
SN54HC407BA SN74HC407BA
TA - 25"C
MIN
TVP MAX
MIN MAX
MIN MAX
195
165
40
130
12
26
39
33
10
22
28
33
38
75
110
95
15
22
19
8
6
13
19
16
No load, TA
Note 1: Load circuits and voltage waveforms are shown in Section t.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
= 25"C
25 pF typ
UNIT
ns
ns
•
2-665
::z:
("')
s:o
t/)
cCD
,,.<
CD
(I)
2-666
SN54HC4514, SN74HC4514
4·LlNE TO 16·LlNE DECODERS/DEMUlTlPlEXERS
WITH ADDRESS LATCHES
02684. DECEMBER 1982-REVISED JUNE 1989
•
SN&4HC4514 .•. JT PACKAGE
SN74HC4514 ..• DW OR NT PACKAGE
(TOPVIEWl
Package Options Include Plastic "Smell
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
Vec
LE
G
Dependable Texas Instruments Quality and
Reliability
•
o
c
Y6
V5
description
The SN54HC4514 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC4514 is
characterized for operation from -40°C to
85°C.
FUNCTION TABLE
LE
H
INPUTS
l3' D C
L L L
H
H
L
L
L
L
L
L
H
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
H
H
H
H
B
L
A
L
H
L
H
L
H
H
L
L
H
L
6
7
8
L
H
H
L
H
L
H
L
H
L
L
H
L
H
H
H
H
H
L
H
H
X
X
X
L
X
X
X
X
fI
V9
V14
V15
Y12
VO
GND --..;.;"----"'".... V13
SN54HC4514 •.. FK PACKAGE
(TOPVIEWI
U
'" « ~ ~ ~'(!l
4
3 2
C
1 282726
V7
V6
V5
5
25
C
6
7
24
VIO
23
VII
NC
8
22
NC
V4
V3
VI
9
21
10
20
19
11
VI4
12131415 161718
NOCUC'lNLCl
>->-ZZ~~·~
(!l
>->->-
NC-No internal connection
Selected
Output = H
All others
=
L
9
10
11
12
13
14
15
All = L
All outputs remain in stale
existing before LE I
UILESS OTHERWISE IOTED this ......I118III ..II1II..
PRODUCTION DATA informalion cumnl al of
publ......n dote. Pr"""011 •••form I. _iflatlona
per Ih.
of T.xu I.strumlllll oIand.nI
ta....
OUTPUTS
V3
VI
V2
a
1
2
3
4
5
L
H
H
H
H
X
L
L
OUTPUT
SELECTED
VII
va
These devices present two output options of a
4-line to 16-line decoder with latched inputs. The
'HC4514 presents a high level at the selected
output.
These devices consist of four storage latches
with common latch enable (LE) and inhibit (0)
inputs. When a low signal is applied to the LE
input, the input data is stored, decoded, and
presented to the output. When 0 is high, all
sixteen 'HC4514 outputs are at a low logic level.
Yl0
:r~,i!'t;~o:,r==,,~·DI.""'riIY
Copyright @ 1989, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS; TEXAS 75265
2-667
SN54HC4514, SN74HC4514
4-LlNE TO· 16-LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
logic symbols (alternatives) t
XIV
(91
2
LE
III
3
C20
4
•
A
B
(21
(31
(211
C
(221
0
:t:
5
200
2
4
8
6
7
8
9
(")
G
3:
0
en
10
11
12
13
0
14
CD
<
15
(101
(81
(7)
(61
(51
(41
(181
(171
(201
(191
(141
(131
(161
(151
OMUX
YO
Y2
Y3
Y4
2
LE
III
C20
Y5
Y6
Y7
Y8
Y9
A
3
200
B
C
0
}&
CD
Yll
5
6
(81
(71
(61
(51
(41
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Yl0
G
11
Y12
12
Y13
13
Y14
14
Y15
15
tThese symbols are in accordance with ANSI/lEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for OW, JT, and NT packages.
2-668
4
(101
Yl0
5(I)
YO
Yl
Yl
..If
TEXAS
INSTRUMENTS
POST OFFICE BO)( 656012 • DALLAS. TeXAS 75265
(191
(141
(131
Yll
Y12
Y13
(161
Y14
(151
Y15
SN54HC4514, SN74HC4514
4·LlNE TO 16·LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
logic diagram (positive logic)
•
Pin numbers shown are for OW, JT, and NT packages.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·669
SN54HC4514, SN74HC4514
4·LlNE TO 16·LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
absolute maximum ratings over operating free-air temperature range t
E
::E:
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 mA
Continuous current through VCC or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or JT package .............. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or NT package ............. 260°C
Storage temperature range ......................................... - 65°C to 1 50°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
n
s:o
recommended operating conditions
en
SN54HC4514
oCD
Vee Supply valtage
c;'
VIH
<
MIN
2
High·level input valtage
Vee = 2 V
Vee = 4.5 V
1.5
3.15
4.2
Law-level input valtage
Vee = 6 V
Vee = 2 V
Vee = 4.5 V
CD
rn
VIL
VI
Vo
Input valtage
Output voltage
tt
Input transition (rise and fall) times
MIN
NOM
MAX
5
6
2
1.5
3.15
5
6
!
it"
Vee = 6 V
Vee = 2 V
Vee = 4.5 V
0$
0
0
!i
?I'
Operating free-air temperature
UNIT
V
V
4.2
0.3
0.9
1.2
Vee
Vee
1000
500
400
125
0
-55
Vee = 6 V
TA
MAX
0
0
0
0
SN74HC4514
NOM
0
0
0
0.3
0.9
1.2
V
0
0
0
0
Vee
Vee
1000
500
400
V
V
0
-40
85
ns
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
~A
VI = VIH ar VIL,
10H = -20
VI = VIH ar VIL,
10H = -4 rnA
10H = -5.2 rnA
VOH
VI = VIH ar VIL.
10L
20 ~A
6V
2V
4.5 V
VI = VIH or VIL,
IOL=4rnA
6V
4.5 V
VI = VIH ar VIL.
VI = Vee arO
10L = 5.2 rnA
VI = Vee arO.
10 = 0
VI = VIH ar VIL.
=
VOL
II
lee
ei
2-670
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 ta 6 V
TA - 25°C
MIN
TYP MAX
1.9 1.998
4.4 4.499
5.9 5.999
3.98
4.30
5.48
5.80
SN54HC4514 SN74HC4514
MIN MAX
MIN MAX
1.9
4.4
5.9
3.7
1.9
4.4
5.9
3.84
5.34
::e
i!
5.2 i.IJ
0.002
0.001
0.1
0.1
0.001
0.17
0.15
0.1
0.26
0.26
±0.1
±100
3
8
10
TEXAS . "
INSlRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
0.1
0.1
0.1
0.4
Q
0.4
;;: ± 1000
fo."
2?
"l
160
10
UNIT
V
0.1
0.1
0.1
0.33
0.33
±1000
80
10
V
nA
~A
pF
SN54HC4514. SN74HC4514
4·LlNE TO 16·LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
2V
Pulse duration, LE high
tw
4.5V
6V
2V
4.5 V
Setup time, A thru 0 before LEI
tsu
6V
2V
Hold time, A thru 0 before LEI
th
4.5 V
6V
TA - 25°C
MIN
MAX
SN54HC4514 SN74HC4514
MIN MAX
MIN MAX
119
24
80
16
14
30i~
2s::?'
,£'i5
21
5
5
5
5
§
5
5
5
ns
20
17
125
25
l
20
149 $~;
100
20
17
UNIT
100
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
FROM
(lNPUTI
TO
(OUTPUTI
tpd
A thru 0
Any
2V
4.5V
Any
6V
2V
4.5 V
tpd
tpd
tt
LE
"G"
Any
Any
VCC
TA - 25°C
MIN
TYP MAX
115
230
23
46
20
39
115
23
230
46
6V
2V
4.5 V
6V
20
88
18
2V
4.5 V
38
8
39
175
35
30
75
6V
6
Power dissipation capacitance
15
SN54HC4514 SN74HC4514
MIN MAX
MIN MAX
343
290
69
58
49
li 8
290
p3
'" 69
if
;!5~
15
13
No load, TA - 25°C
58
261
52
44
110
22
19
58
49
221
44
37
95
19
•
UNIT
ns
ns
ns
ns
16
60 pF typ
Note 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS .."
INSfRUMENlS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75286
2-671
l:
(')
~
oen
c
CD
<
c:r
CD
en
2-672
SN54HC4724. SN74HC4724
8·BIT ADDRESSABLE LATCHES
02684. DECEM8ER 1982 - REVISED JUNE 1989
•
8·Blt Parallel·Out Storage Register Performs
Serial-to-Parallel Conversion with Storage
•
Asynchronous Parallel Clear
•
Active-High Decoder
•
Enable Input Simplifies Expansion
•
Expandable for N-Bit Applications
SN54HC4724 •.. J PACKAGE
SN74HC4724 ••• N PACKAGE
(TOPVIEWI
so
•
Four Distinct Functional Modes
•
Package Options Include Ceramic Chip
Carriers and Standard Plastic and Ceramic
300-mil DIPs
•
Dependable Texas Instruments Quality and
Reliability
VCC
CLR
S1
S2
00
01
02
03
GND
G
D
07
06
05
04
'S;
Ua::
.- 0 u u-,
UlUlZ>U
3
Q)
c
1 20 19
2
S2
00
4
18
5
17
NC
6
16
Four distinct modes of operation are selectable
by controlling the clear (ClR) and enable (G)
inputs as enumerated in the function table. In the
addressable-latch mode, data at the data-in
terminal is written into the addressed latch. The
addressed latch will follow the data input with
all unaddressed latches remaining in their
previous states. In the memory mode, all latches
remain in their previous states and are
unaffected by the data or address inputs. To
eliminate the possibility of entering erroneous
data in the latches, enable G should be held high
(inactive) while the address lines are changing.
In the 1-of-8 decoding or demultiplexing mode,
the addressed output will follow the level of the
D input with all other outputs low. In the clear
mode, all outputs are low and unaffected by the
address and data inputs.
NC - No internal connection
01
02
en
o
:!
(J
15
:t
14
8
9 1011 1213
C'lCUq-Il)
dzzdd
(!l
FUNCTION TABLE
INPUTS
CLR
13
PRODUCTION DATA documants contain information
TEXAS
OUTPUT OF
EACH
ADDRESSED
OTHER
LATCH
OUTPUT
FUNCTION
L
L
D
GiO
Addressable Latch
L
H
L
GiQ
L
Memory
H
GiQ
D
H
H
L
L
8-Line Demultiplexer
Clear
LATCH SELECTION TABLE
SELECT INPUTS
The SN54HC4724 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC4724 is
characterized for operation from - 40°C to
85°C.
not
Q)
CJ
These 8-bit addressable latches are designed for
general purpose storage applications in digital
systems. Specific uses include working
registers, serial-holding registers, and active-high
decoders or demultiplexers. They are
multifunctional devices capable of storing singleline data in eight addressable latches, and being
a 1-of-8 decoder or demultiplexer with activehigh outputs.
:::~:~~i;a{::I~~i ~=:;ti:; :.~o:::~9t:~~
en
(TOP VIEWI
description
current 8S of publication data. Products conform to
spacifications per the tarms of Texl. Instruments
•
SN54HC4724 ... FK PACKAGE
52
51
L
L
L
H
L
L
H
H
H
L
L
H
L
H
ADDRESSED
L
L
L
H
0
1
2
3
4
5
6
7
H
H
L
H
H
H
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
LATCH
SO
Copyright © 1989, Texas Instruments Incorporated
2-673
SN54HC4724, SN74HC4724
8·BIT ADDRESSABLE LATCHES
logic symbol t
logic diagram (positive logic)
00
01
:::t
n
:s:
o
en
9,20
10JR
(6
9,30
10JR
(7)
9,40
(9)
cCD
10,4R
CD
9,60
10,6R
9,50
10;5R
<
c;'
(I)
02
03
04
(10) 05
9,70
(12) 07
10.7R
t This
symbol is in accordance with ANSI/IEEE
Std 91-1984 and lEe Publication 617-12_
Pin numbers shown are for J and N packages_
logic symbol and logic diagram. each internal latch (positive logic)
c
0=M.!:
R
0------1
c--.p---+
0
~1
Q
lR
R-==J.J---'
2-674
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, tEXAS 75265
SN54HC4724. SN74HC4724
8·BIT ADDRESSABLE LATCHES
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) ................................. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vec) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vec) ................................ ±25 mA
eontinuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1116 in) from case for 60 s: FK or J package ............... 300 0 e
Lead temperature 1,6 mm (1/16 in) from case for 10 s: N package. . . . . . . . . . . . . . . . . . .. 260°C
Storage temperature range ......................................... - 65 °e to 1 50 °e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute~maximum-rated conditions for extended periods may affect device reliability.
fI
recommended operating conditions
SN74HC4724
SN54HC4724
MIN
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
Vee Supply voltage
VIH
Vee
Vee
High-level input voltage
=2V
= 4.5 V
=6V
Low-level input voltage
Vee
Vee
1.5
3.15
3.15
4.2
4.2
Vee
Vee - 2 V
VIL
1.5
= 4.5 V
=6V
UNIT
V
V
0
0.3
0
0.3
0
0.9
0
0.9
0
1.2
0
1.2
V
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
Vee
1000
0
Vee
1000
V
n.
Vee
Input transition (rise and fall) times
tt
Vee
=
=
2 V
0
4.5 V
0
500
0
500
0
-55
400
0
-40
400
Vee = 6 V
Operating free-air temperature
TA
125
0
85
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
~A
VI = VIH or VIL.
10H = -20
VI = VIH or VIL.
VI = VIH or VIL.
10H = -4 rnA
10H = -5.2 rnA
VOH
VI
=
VIH or VIL.
10L
=
20 ~A
VOL
VI = VIH or VIL.
VI - VIH or VIL.
II
VI
lee
VI
ei
= Vee
= Vee
10L = 4 rnA
10L = 5.2 rnA
or 0
or O.
10
=0
TA - 25°C
MIN
TYP MAX
SN54HC4724 SN74HC4724
MIN
MAX
MIN
2V
1.9 1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
4.5 V
5.9 5.999
3.98
4.30
5.9
3.7
5.9
3.84
6V
5.48
5.80
MAX
UNIT
V
5.34
5.2
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
6V
0.17
0.15
0.26
0.26
0.4
0.4
0.33
0.33
6V
±0.1
±100
±1000
±1000
nA
8
160
80
~A
10
10
10
pF
6V
2 to 6 V
TEXAS
3
~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
V
2-675
SN54HC4724, SN74HC4724
8-BIT ADDRESSABLE LATCHES
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
CLR high
Pulse duration
tw
Glow
tsu
Setup time, data or address before Gt
th
Hold time, data or address after
:::t
o
s:
o
en
c
CD
c;t
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
80
16
14
80
16
14
75
15
13
5
5
5
SN54HC4724 SN74HC4724
MIN MAX
MIN MAX
120
100
24
20
20
17
120
100
24
20
20
17
115
95
23
19
20
16
5
5
5
5
5
5
UNIT
ns
ns
n.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL "" 50 pF (see Note 11
<
PARAMETER
0'
FROM
IINPUT)
TO
(OUTPUT)
CD
U)
tPHL
CLR
Any Q
tpd
Data
Any Q
tpd
Address
Any Q
tpd
G
Any Q
tt
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Power dissipation capacitance per latch
SN54HC4724 SN74HC4724
TA = 25°C
MIN
TYP MAX
MIN MAX
MIN MAX
150
225
190
60
18
30
45
38
14
26
38
32
56
130
195
165
17
26
39
33
13
22
28
33
74
200
300
250
21
40
60
50
17
34
43
51
66
170
255
215
20
34
51
43
16
29
43
37
28
75
110
95
8
15
22
19
6
13
19
16
No load, TA
Note 1: Load circuits and voltage waveforms are shown in Section 1.
2-676
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
=
25°C
33 pF typ
UNIT
ns
ns
ns
ns
ns
SN54HC7001. SN74HC7001
QUADRUPLE POSITIVE·AND GATES WITH SCHMITT·TRIGGER INPUTS
02831. MARCH 1984-REVISEO SEPTEMBER 1987
•
Operation from Very Slow Input Transitions
SN54HC7001 .•. J PACKAGE
SN74HC7001 ... 0 OR N PACKAGE
•
Temperature-Compensated Threshold Levels
(TOp·VIEW}
•
High Noise Immunity
•
Same Pinouts as 'HC08
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
1A
19
1Y
2A
29
2Y
VCC
49
4A
4Y
39
3A
3Y
GND
•
SN54HC7001 ..• FK PACKAGE
(TOP VIEW}
description
U
mOU>- Vee) . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output clamp current, 10K (Vo < 0 or Vo > Vee). . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 rnA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Lead temperature 1,6 mm (1/16 in) from case for 60 5: FK or J package ............... 300 De
Lead temperature 1,6 mm (1/16 in) from case for 105: D or N package ................ 260 De
Storage temperature range ......................................... - 65 DC to 150 DC
::I:
o
s:
o
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute~maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC7001
MIN NOM MAX
en
cCD
<
,r
CD
Vee Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
en
Vee
Vee
Vec
Vee
Vee
Vee
VI
Vo
TA
2-678
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Input voltage
Output voltage
2
1.5
TEXAS
6
3.15
4.2
0
0
0
0
0
-55
Operating free-air temperature
5
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN74HC7001
MIN NOM MAX
2
5
6
1.5
3.15
4.2
0.3
0.9
1.2
Vee
Vee
125
0
0
0
0
0
-40
UNIT
V
V
0.3
0.9
V
1.2
Vee
Vee
85
V
V
°e
SN54HC7001. SN74HC7001
QUADRUPLE POSITIVE-AND GATES WITH SCHMITT-TRIGGERED INPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
VI = VIH or VIL,
10H = -20 "A
VI = VIH or VIL,
VI = VIH or VIL,
VI = VIH or VIL,
10H = -4 rnA
10H = -5.2 rnA
10L = 20 "A
VOL
VI = VIH or VIL,
10L = 4 rnA
VI = VIH or VIL,
10L = 5.2 rnA
VT+
VT-
VT+ - VTII
VI - VCC or 0
ICC
Cj
VI = VCC or 0,
MAX
MAX
SN74HC7001
MIN
1.9
1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
4.5 V
5.9
5.999
3.98
4.30
5.9
3.7
5.9
3.84
6V
5.48
5.80
5.2
MAX
UNIT
V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
2V
0.70
1.2
1.50
0.70
1.50
0.70
1.50
4.5 V
1.55
2.5
3.15
1.55
3.15
1.55
3.15
6V
2.10
3.3
4.20
2.10
2.10
4.20
2V
0.30
0.6
1.00
0.30
4.20
1.00
0.30
1.00
4.5 V
6V
0.90
1.20
1.6
2.45
0.90
2.45
0.90
2.45
2.0
3.20
1.20
1.20
0.20
3.20
V
V
V
2V
0.20
0.6
1.20
0.20
3.20
1.20
4.5 V
0.40
0.9
2.10
0.40
2.10
0.40
2.10
6V
0.50
1.3
2.50
0.50
2.50
0.50
2.50
±0.1
±100
±1000
± 1000
nA
2
40
20
10
10
10
"A
pF
6V
2 to 6 V
3
•
5.34
2V
6V
10 = 0
MIN
TVP
2V
VOH
SN54HC7001
TA = 25°C
MIN
1.20
V
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
Any
VCC
SN5~C7001
TA = 25°C
MIN
2V
TVP
60
MAX
130
4.5 V
18
6V
14
MIN
MAX
SN74HC7001
MIN
MAX
195
163
26
39
33
22
33
28
2V
28
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance per gate
No load, TA = 25°C
UNIT
ns
ns
20 pF typ
Note 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-679
::I:
o
3:
oen
cCD
<
ri"
CD
(I)
2-680
SN54HC7002, SN74HC7002
QUADRUPLE POSITIVE·NOR GATES WITH SCHMITT·TRIGGER INPUTS
02831, MARCH 1984-REVISEO SEPTEMBER 1987
•
Operation from Very Slow Input Transitions
•
Temperature·Compensated Threshold Levels
•
High Noise Immunity
•
Same Pinouts as 'HC36
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers.
and Standard Plastic and Ceramic aOO·mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC7002 ••• J PACKAGE
SN74HC7002 .•• 0 OR N PACKAGE
(TOPVIEWI
VCC
lA
18
lY
2A
28
2Y
48
4A
4Y
38
3A
3Y
GND
Each circuit functions as a quadruple NOR gate.
They perform the Boolean function
y = A + B or Y = A.S in positive logic.
However. because of the Schmitt action. the
inputs have different input threshold levels for
positive- and negative-going signals.
2A
3A
3B
4A
4B
(21
141
<
3
2
CD
c
1 20 19
4
18
4A
5
17
NC
2A
6
16
4Y
NC
7
15
NC
8
14
38
en
o
:E
u
:c
9 1011 1213
"'22MM
(!l
NC-No internal connection
FUNCTION TABLE
;>1
151
UIIl
lY
INPUTS
.rr
.rr
U
NC
logic symbol t
(11
III
)-CU)-<
The SN54HC7002 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC7002 is
characterized for operation from - 40°C to 85°C.
2B
CD
U
'S:
U
~~2>v
The circuits are temperature compensated and
can be triggered from the slowest of input ramps
and will still give clean jitter-free output signals.
lB
U)
(TOP VIEWI
description
lA
II
SN54HC7002 •.. FK PACKAGE
OUTPUT
A
B
Y
H
X
L
X
H
L
L
L
H
logic diagram. each gate (positive logic I
191
1101
(121
1131
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEG Publication 617-12.
Pin numbers shown are for D, J, and N packages.
PRODUCTION DATA do.umonts .ontain i.lormotiDn
.urrent .s of publi••tion data. Products oonform to
specificatians par the terms of lUIS Instruments
:=~i~'i:::i ~::I:~i:; :.,,;::::m":." lUll
Copyright © 1984, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAl.lAS, TEXAS 75265
2-681
SN54HC7002, SN74HC7002
QUADRUPLE POSITIVE·NOR GATES WITH SCHMITT·TRIGGER INPUTS
absolute maximum ratirigs over operating free·air temperature range t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (V, < 0 or V, > Vee) . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K NO < 0 or Vo > Vee) ............................. ± 20 rnA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current 'through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: D or N package ................ 260°C
Storage temperature range ......................................... - 65°C to 150°C
::J:
(')
3:
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
oen
SN54HC7002
cCD
Vee Supply voltage
(;'
VIH
<
High-level input voltage
Low-level input voltage
Vee
Vee - 2 V
Vee = 4.5 V
CD
til
VIL
Vee
VI
Vo
TA
2-682
=2V
= 4.5 V
=6V
Vee
Vee
=
6V
Input voltage
Output voltage
Operating free-air temperature
SN74HC7002
MIN
NOM
MAX
2
1.5
3.15
4.2
5
6
0
0
0
0
0
-55
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
MIN
2
NOM
MAX
5
6
1.5
3.15
4.2
0.3
0.9
1.2
Vee
Vee
125
0
0
0
0
0
-40
UNIT
V
V
0.3
0.9
1.2
Vee
Vee
85
V
V
V
°e
SN54HC7002, SN74HC7002
QUADRUPLE POSITIVE-NOR GATES WITH SCHMITT-TRIGGERED INPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
TA
TEST CONDITIONS
PARAMETER
VCC
2V
VI
=
VIH or VIL.
10H
= -20 fiA.
VOH
V,
V,
V,
=
=
V,H or V,L.
lOH
V,H or V,L.
lOH
=
=
-4 mA
-S.2 mA
= V,H or V,L. lOL = 20 ~A
VOL
= V,H or V,L. lOL = 4 mA
V, = V,H or V,L. lOL = 5.2 mA
V,
VT+
VT-
VT+ .- VT-
V,
=
Vee or O.
10
=0
2SOC
SNS4HC7002
MAX
MIN
MAX
SN74HC7002
MIN
TYP
1.9
1.998
1.9
1.9
4.4 4.499
4.4
4.4
5.9
5.9
3.84
6V
4.5 V
5.9
3.98
6V
5.48
5.999
4.30
3.7
5.2
5.80
MAX
5.34
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.4
0.33
0.70
1.50
0.70
1.50
1.55
3.15
1.55
3.15
4.20
2V
0.70
1.2
0.26
1.50
4.5 V
1.55
2.5
3.15
UNIT
V
2V
V
'>
2.10
3.3
4.20
2.10
4.20
2.10
0.30
0.6
1.00
0.30
1.00
0.30
1.00
4.5 V
1.6
2.45
3.20
2.45
3.20
2.45
2.0
0.90
1.20
0.90
6V
0.90
1.20
1.20
3.20
2V
0.20
0.6
1.20
0.20
1.20
0.20
1.20
4.5 V
0.40
0.9
2.10
0.40
2.10
0.40
2.10
6V
0.50
1.3
2.50
0.50
2.50
0.50
2.50
±0.1
± 100
±1000
±1000
nA
2
40
10
20
fiA.
10
pF
3
10
Q)
c
V
2V
6V
2 to 6 V
II)
Q)
(.)
6V
6V
V, - Vee or 0
"
lee
ej
4.5 V
=
MIN
en
o
V
:!E
o
J:
V
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
TO
(INPUT)
IOUTPUT)
A or B
Y
Any
VCC
TA = 25°C
SN54HC7002 SN74HC7002
TYP
MAX
2V
60
130
195
163
4.5 V
18
26
39
33
6V
14
22
28
95
MIN
MIN
MAX
MIN
MAX
2V
28
75
33
110
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance per gate
No load. TA
= 25°C
UNIT
ns
ns
20 pF typ
Note 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-683
IE
::J:
C')
s:
o(J)
c
CD
<
5'
CD
til
2-684
SN54HC7032, SN74HC7032
QUADRUPLE POSITIVE·OR GATES WITH SCHMITT·TRIGGER INPUTS
02831, MARCH
•
Operation from Very Slow Input Transitions
•
Temperature-Compensated Threshold Levels
•
High Noise Immunity
•
Same Pinouts as 'HC32
•
Package Options Include Plastic "Small
Outline" Packagas. Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SEPTEMBER 1987
SN54HC7032 .•. J PACKAGE
SN74HC7032 ... D OR N PACKAGE
(TOP VIEW)
VCC
1A
18
1Y
2A
28
2Y
48
4A
4Y
38
3A
3Y
GND
•
SN54HC7032 ..• FK PACKAGE
en
(TOP VIEW)
description
CD
(J
__ z>U .....
m«UUm
Each circuit functions as a quadruple OR gate.
They perform the --.!Wolean function
Y = A + B or Y = A·S in positive logic.
However, because of the Schmitt action, the
inputs have different input threshold levels for
positive- and negative-going signals.
3
The circuits are temperature compensated and
can be triggered from the slowest of input ramps
and will still give clean jitter-free output signals.
2
'>CD
Q
1 20 19
en
4A
1Y
4
18
NC
5
17
NC
4Y
2A
6
16
NC
7
15
NC
28
8
14
38
o
:E
o
::t:
9 1011 12 13
>OU>«
"'ZZMM
The SN54HC7032 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC7032 is
characterized for operation from -40°C to 85°C.
Cl
NC - No internal connection
FUNCTION TABLE
logic symbol t
lA
18
2A
28
3A
3B
4A
48
(11
(2)
INPUTS
.IT
IT
;;'1
(3) IV
(4)
(5)
B
V
H
X
H
X
H
H
L
L
L
(6) 2V
logic diagram. each gate (positive logic)
(9)
(10)
OUTPUT
A
(8) 3V
(12)
(13)
(11) 4V
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
Copyright @ 1984. TeK8S Instrumalts Incorporated
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-685
SN54HC7032, SN74HC7032
QUADRUPLE POSITIVE·OR GATES WITH SCHMITT·TRIGGER INPUTS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee ........................... , . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ............................. ±20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 mA
Continuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1116 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1116 in) from case for 10 s: D or N package. . . . . . . . . . . . . . .. 260°C
Storage temperature range ......................................... - 65°C to 150°C
:::t
(')
s::
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
oen
SN54HC7032
cCD
Vee Supply voltage
(=)'
VIH
High-level input voltage
VIL
Low-level input voltage
<
CD
II)
Vee
Vee
Vee
Vee
Vee
Vee
VI
Vo
TA
2-686
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
Input voltage
Output voltage
Operating free-air temperature
TEXAS
SN74HC7032
MIN
NOM
MAX
MIN
NOM
MAX
2
1.5
3.15
4.2
5
6
2
1.5
3.15
4.2
5
6
0
O.~
0
0
0
0.9
0
1.2
0
0
Vee
Vee
0
0
-55
125
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
UNIT
V
V
0.3
0.9
V
1.2
0
Vee
Vee
-40
85
V
V
De
SN54HC7032, SN74HC7032
QUADRUPLE POSITIVE·OR GATES WITH SCHMITT·TRIGGERED INPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
=
VIH or VIL.
=
10H
VCC
-20",A
VOH
VI
VI
=
=
VIH or VIL.
10H
VIH or VIL.
10H
=
=
-4 rnA
-5.2 rnA
VI
=
VIH or VIL.
10L
=
VI
VI
=
=
VIH or VIL.
VIH or VIL.
10L
10L
= 4 rnA
= 5.2 rnA
20 ~A
VOL
2V
4.5V
6V
4.5V
6V
2V
4.5 V
BV
4.5 V
6V
2V
4.5 V
VT+
VT-
II
VI - VCC or 0
ICC
Cj
VI
=
VCC or O.
5.9 5.999
3.98
4.30
5.48
0.001
0.17
0.15
0.70
1.2
1.55
=0
MAX
MAX
UNIT
4.4
V
5.9
3.84
5.2
0.1
MIN
1.9
5.34
0.1
0.1
0.1
0.1
0.1
0.33
0.33
1.50
3.15
0.1
0.1
0.26
0.26
1.50
0.70
3.15
4.20
1.00
1.55
2.10
0.30
1.50
3.15
4.20
1.00
0.70
1.55
2.10
0.30
4.20
1.00
0.1
0.4
0.4
V
Q)
'>
2.10
0.30
4.5 V
6V
0.90
1.20
1.6
2.0
2.45
3.20
0.90
1.20
2.45
3.20
0.90
1.20
2.45
3.20
2V
0.20
0.40
0.50
0.6
1.20
0.20
0.20
0.9
1.3
2.10
2.50
0.40
0.50
1.20
2.10
2.50
1.20
2.10
2.50
±0.1
±100
±10oo
±1000
nA
40
20
10
~
3
2
10
6V
2 to 6 V
0.40
0.50
10
II)
U
BV
2V
6V
10
MIN
1.9
4.4
5.9
3.7
5.80
0.002
0.001
SN54HC7032 SN74HC7032
2.5
3.3
0.6
4.5 V
6V
VT+ - VT-
TA = 25°C
MIN
TYP MAX
1.9 1.998
4.4 4.499
Q)
V
C
en
V
o
V
CJ
J:
:E
pF
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 11
PARAMETER
tpd
tt
FROM
TO
(INPUTI
(OUTPUTI
Aor B
Y
Any
VCC
2V
4.5 V
TA = 25°C
MIN
TYP MAX
130
60
6V
2V
18
14
28
26
22
75
4.5 V
6V
8
B
15
13
Power dissipation capacitance per gate
SN54HC7032 SN74HC7032
MIN
No load. TA = 25°C
MAX
195
39
33
110
22
19
MIN
MAX
163
33
28
95
19
UNIT
n.
n.
16
20 pF typ
Note 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TeXAS 75265
2-687
E
J:
(')
s:o
en
c
CD
<
C:;'
CD
en
2-688
SN54HC7074, SN74HC7074
6-SECTION MULTIFUNCTION
(NAND, INVERT, NOR, FLIP-FLOP) CIRCUITS
D2831. MARCH 1984-REVISED SEPTEMBER 1987
SN54HC7074 ... JT PACKAGE
SN74HC7074 ... OW OR NT PACKAGE
(TOP VIEW)
•
Contains D-type Flip-Flops with Preset and
Clear. NAND. NOR. and Inverter Gates
•
Package Options Include Plastic "Small
Outline" Packages. Both Plastic and
Ceramic Chip Carriers. and Standard Plastic
and Ceramic 300-mil DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
INV
(1 AND 2)
VCC
1Y}
{lA
2Y
2A
3A
NAND { 38
3Y
4CLK
4PRE
{
40
FLIP-FLOP
40
The SN54HC7074 and SN74HC7074 are each
comprised of the following sections:
Two inverters
One 2-input NOR gate
One 2-input NAND gate
Two D-type flip-flops
They perform the Boolean functions shown
under the respective function table.
4CLR
:!}
~;:
4Q
5CLR
INV
(1 AND 2)
NOR
FI
6Y
}
FLIP-FLOP
II)
CI)
U
'S;
GND Y.:..::"""....:.::JI-' 5Q
CI)
C
SN54HC7074 ... FK PACKAGE
(TOP VIEW)
CI)
o
U
« ) - « U U)-«
:!
MC'\I,,-Z>-N
The D-type flip-flops are positive-edge-triggered
and are functionally similar to the SN54HC74
and SN74HC74. A low level at the PRE or CLR
inputs sets or resets the outputs regardless of
the levels of the other inputs. When PRE and CLR
are inactive (high). data at the D input meeting
the setup time requirements are transferred to
the outputs on the positive-going edge of the
clock pulse. Clock triggering occurs at a voltage
level and is not directly related to the rise time
of the clock pulse. Following the hold time
interval. data at the D input may be changed
without affecting the levels at the outputs.
The SN54HC7074 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC7074 is
characterized for operation from -40°C to
85°C.
PRODUCTION DATA documanlS ••ntain information
currant as af publication datI. Products conform to
specifications par the terms of Taus Instruments
::::~~;It::,~l~ ~:~:~ti:i :'ID:=:~n:t:is~1 not
TEXAS
4
38
3Y
4CLK
NC
4PRE
40
40
3
2
(.)
:x:
1 282726
5
25
6
24
8
22
9
21
10
20
23
11
19
6A
68
6Y
NC
5CLK
5PRE
50
12131415161718
NC - No internal connection
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1984, Texas Instruments Incorporated
2-689
SN54HC7074, SN74HC7074
6·SECTION MULTIFUNCTION
(NANO, INVERT, NOR, FLlp·FLOP) CIRCUITS
logic symbol t
lA
(11
2A
3A
3Y
3B
4PRE
II
40
4CLR
5PRE
%
50
ot/)
<
ci'
:
w
5CLK
(")
~
cCD
4Q
4CLK
~
5CLR
6A
6B
tThis symbol is in accordance with ANSI/IEEE SId 91-1984 and lEe Publication 617-12.
logic diagrams (positive logic)
INVERTERS
FUNCTION TABLE
(EACH INVERTERI
1A~lY
INPUT
OUTPUT
A
Y
2A~2Y
H
L
L
H
positive logic: Y
=A
2-INPUT NAND GATE
FUNCTION TABLE
INPUTS
OUTPUT
A
B
Y
H
L
H
X
H
X
L
H
L
positive logic: Y ~ A·8 or Y ~
Pin numbers shown are for OW, JT, and NT packages.
2-690
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
A+B
SN54HC7D74, SN74HC7D74
6·SECTION MULTIFUNCTION
(NAND, INVERT, NOR, FLlP·FLOP) CIRCUITS
logic diagrams (positive logic)
OOTYPE FLIP-FLOPS
4PRE_(~7~)________________________~~________- ,
~"~:
c
•
II)
Q)
CJ
'S;
Q)
C
4CLR
5PRE
5CLK
50
5CLR
40
(10)
(17)
(18)
(16)
(14)
tJ)
0
~
S
C2
The detail above. and the composite logic symbol to the left.
apply to both flip-flops_
(13) 50
20
CJ
l:
50
R
FUNCTION TABLE
(EACH 0 FLIP-FLOP)
OUTPUTS
INPUTS
PRE
ClR
ClK
D
Q
Q
l
H
l
l
l
H
l
l
X
X
X
H
H
X
X
X
H*
H*
H
H
H
l
H
t
t
H
H
l
l
H
H
H
l
X
Qo
00
*This configuration is nonstable; i.e., it will
not persist when either PRE or eLR returns
to the inactive (high) level.
2-INPUT NOR GATE
FUNCTION TABLE
INPUTS
6Y
OUTPUT
A
B
H
X
l
X
H
l
l
l
positive logic: Y
Y
H
= A+1i or Y = A.S
Pin numbers shown are for OW, JT, and NT packages.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-691
SN54HC7074. SN74HC7074
6·SECTION MULTIFUNCTION
(NAND. INVERT. NOR. FLlP·FLOP) CIRCUITS
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee .. '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) .. '. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GNO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or JT package .............. 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: OW or NT package ............. 260°C
Storage temperature range ......................................... - 65°C to 150°C
t Stresses beyond those listed under
::J:
(")
3:
oen
cCD
<
(;'
"absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC7074
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
Vee Supply voltage
Vee
VIH High-level input voltage
Vee
Vee
CD
Vee
(II
VIL
Low-level input voltage
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
SN74HC7074
MIN
1.5
1.5
3.15
3.15
4.2
4.2
UNIT
V
V
0
0.3
0
0
0.9
0
0.3
O.g
0
1.2
0
1.2
V
VI
Input voltage
0
Vee
0
Vee
V
Vo
Output voltage
0
0
Vee
1000
0
Vee
1000
V
0
500
0
500
n.
0
-55
400
0
-40
400
vee - 2 V
tt
Input transition (rise and fall) times
Vee
Vee
TA
= 4.5 V
=6V
Operating free-air temperature
125
0
85
·e
electrica, characteristics over recommended operating free-air temperature range (unless otherwise
notedl
PARAMETER
TEST CONDITIONS
VCC
2V
VI
=
VIH or VIL.
=
10H
-20 pA
VOH
VI ~ VIH or VIL.
VI - VIH or VIL.
10H = -4 mA
10H - -5.2 mA
lee
ei
2-692
1.9
SN54HC7074 SN74HC7074
MIN
MAX
MIN
1.998
1.9
1.9
4.4
4.4 4.499
4.4
6V
5.9
5.999
5.9
5.9
4.5 V
3.98
4.30
3.7
3.84
6V
5.48
4.5 V
5.80
5.2
MAX
5.34
2V
0.002
0.1
0.1
0.1
0.1
0.1
0.1
=
VIH or VIL.
10L
=
20 ~A
4.5 V
0.001
6V
0.001
0.1
0.1
0.1
VI
=
=
VIH or VIL.
10L
10L
= 4 mA
= 5.2 rnA
4.5 V
0.17
0.26
0.4
0.33
VI
VIH or VIL.
VI - Vee or 0
VI
=
Vee or O. 10
=0
UNIT
V
VI
VOL
II
TA - 25·C
MIN
TYP MAX
V
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
4
80
40
~A
10
10
10
pF
6V
2 to 6 V
TEXAS
3
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54HC7074, SN74HC7074
6·SECTION MULTIFUNCTION
(NAND, INVERT, NOR, FLlP·FLOP) CIRCUITS
timing requirements for each D-type flip-flop over recommended operating free-air temperature range
(unless otherwise noted)
vCC
fclock
MAX
5.5
0
3.7
0
4.5
28
0
19
0
22
6V
2V
0
31
21
0
110
25
90
0
135
4.5 V
18
26
23
ClR low
6V
16
24
20
P'RE low
2V
4.5 V
100
150
125
20
30
25
6V
2V
17
100
25
150
21
125
4.5 V
20
30
25
Data
Setup time
P'RE high
or
~Iow
Hold time. data after ClK I
th
MIN
0
ClR low
before ClKI
MAX
0
or
tsu
MIN
2V
or
Pulse duration
MAX
4.5 V
Clock frequency
ClK high
tw
SNS4HC7074 SN74HC7074
TA - 2SOC
MIN
6V
17
25
21
2V
25
38
31
4.5 V
5
8
6
6V
4
7
5
2V
5
5
4.5 V
5
5
5
5
5
5
5
6V
UNIT
MHz
FI
ns
(/)
CD
Co)
'S
CD
c
ns
en
o
:!:
u
ns
J:
switching characteristics for each D-type flip-flop over recommended operating free-air temperature
range (unless otherwise noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
TO
(INPUTI
(OUTPUTI
VCC
2V
f max
tpd
ClK
P'RE
tpd
or
-ClR
-
Qor Q
-
Qor Q
Power dissipation capacitance per
SN54HC7074 SN74HC7074
TA - 25°C
TYP MAX
MIN
5.5
MIN
10
MAX
MIN
3.7
4.5
4.5 V
28
50
19
22
6V
31
60
21
25
MAX
MHz
2V
4.5 V
45
15
175
263
219
35
53
44
6V
13
30
45
38
288
2V
45
230
345
4.5 V
15
46
69
58
6V
13
39
59
49
flip~flop
No load. TA
~
2SOC
UNIT
ns
ns
40 pF typ
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-693
SN54HC7074, SN74HC7074
6·SECTION MULTIFUNCTION
(NAND, INVERT, NOR, FLlp·FLOP) CIRCUITS
switching characteristics for gates and inverters over recommended operating free-air temperature
range (unless otherwise noted), CL = 50 pF (see Note 1)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
Y
A or B
tpd
Y
tt
:::J:
oen
SN54HC7074 SN74HC7074
MIN
MAX
MIN
MAX
2V
24
90
135
115
4.5 V
9
18
27
23
6V
2V
7
23
110
20
38
15
75
95
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance per NAND or NOR gate
o
s::
TA - 25°C
MiN
TYP MAX
VCC
Power dissipation capacitance per inverter
27 pF typ
No load, TA = 25°C
20 pF typ
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
cCD
TYPICAL APPLICATION DATA
<
(;'
CD
(I)
--1D:
(1)
(2)
(6)
CLK
S
(11)
(9)
lD
o
Q
(10) '" R
CUi
PRE
(3)
Cl
(8)
RESET 1
RESET 2
1
(4)
171",
1
(22)
&
(5)
20
(23)
1
,,-
(17)"
,...,
.r-.,.J
'HCOO
t
(18)
S
(13)
C2
(15)
~ 2D
(14)"
~
RESET
RESET
R
;'1
~(19)
~
FIGURE 1. CLOCK AND RESET GENERATION FOR MICROPROCESSOR-BASED SYSTEM
2-694
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
UNIT
ns
ns
SN54HC7266. SN74HC7266
QUADRUPLE 2·INPUT EXCLUSIVE·NOR GATES
MARCH 1984-REVISED SEPTEMBER 1987
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
Dependable Texas Instruments Quality and
Reliability
•
Totem-Pole Version of 'HC266
SN54HC7266 ... J PACKAGE
SN74HC7266 ... 0 OR N PACKAGE
(TOP VIEW)
1A
18
1Y
2Y
2A
28
description
GND
These devices are composed of four independent
2-input exclusive-NOR gates. They perform the
Boolean functions:
y = A ® B = AS + AB in positive logic.
The SN54HC7266 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC7266 is
characterized for operation from -40OC to 85°C.
logic symbol t
lA
lB
2A
28
3A
3B
4A
4B
VCC
48
4A
4Y
3Y
38
3A
(1)
(2)
=1
SN54HC7266 ... FK PACKAGE
(TOP VIEW)
m o:t
A
B
Y
L
L
H
L
L
H
H
L
L
H
H
H
Copyright © 1984, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-695
SN54HC7266, SN74HC7266
QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package ............... 300°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s: 0 or N package ................ 260°C
Storage temperature range ......................................... - 65°C to 150°C
l:
o
s:
o
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HC7266
t/)
cCD
<
C;"
MIN
2
Vee Supply voltage
VIH
High·level input voltage
Vee
Vee
low-level input voltage
Vee
Vee
Vee
CD
o
VIL
Vee
1.5
3.15
4.2
0
Output voltage
tt
Input transition (rise and fall I times
Vee
Vee
Vee
=2V
= 4.5 V
=6V
Operating free-air temperature
MAX
6
SN74HC7266
NOM MAX
UNIT
5
V
MIN
2
1.5
6
V
3.15
4.2
0.3
0.9
0.3
0.9
1.2
0
0
0
0
0
0
Vee
Vee
1000
500
0
0
0
0
0
-55
400
125
0
-40
Vee
Vee
1000
500
400
0
0
0
Input voltage
VI
Vo
TA
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
NOM
5
V
1.2
85
V
v
ns
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
VI
=
VIH or VIL.
10H
= -20,.p-
VI
=
=
VIH or VIL,
IOH
10H
=
=
6V
4.5 V
VOH
-4 mA
-5.2 mA
VIH or VIL.
10L
=
20 ~A
BV
2V
4.5 V
VI - VIH or VIL,
10L
IOL
= 4 mA
= 5.2 mA
6V
4.5 V
6V
VI
VI
=
VIH or VIL.
VOL
II
lee
ei
2-696
2V
4.5V
VI = VIH or VIL.
VI = Vee or 0
VI - Vee or 0,
10
=
0
TA - 25°C
TYP MAX
MIN
1.9 1.998
4.4 4.499
5.9 5.999
3.9B
4.30
5.48
6V
BV
2 to 6 V
TEXAS
5.80
0.002
0.001
SN54HC7266 SN74HC7266
MIN MAX
MIN MAX
1.9
4.4
5.9
1.9
4.4
5.9
3.84
3.7
5.2
UNIT
V
5.34
0.001
0.17
0.15
±0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.2B
0.26
±100
0.4
0.4
±1000
0.33
0.33
±1000
nA
40
10
20
10
,.p-
3
2
10
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
V
pF.
SN54HC7266. SN74HC7266
QUADRUPLE 2·INPUT EXCLUSIVE·NOR GATES
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
Ipd
II
FROM
(INPUT)
Aor B
TO
(OUTPUTI
V
V
vcc
2V
4.5V
6V
2V
4.5 V
6V
Power dissipation capacitance per gate
TA = 25°C
MIN
SN54HC7266 SN74HC7266
TYP
MAX
40
100
20
17
75
15
13
12
10
28
8
6
MIN
No load, TA = 25°C
MAX
150
30
25
110
22
19
MIN
MAX
125
25
21
95
19
16
UNIT
ns
ns
35 pF typ
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-697
II
::I:
(")
:s:
oen
c
CD
<
C)'
CD
en
2-698
Numerical Index
Functional Index
D Flip-Flop and Latch Signal Conventions
Explanation of Function Tables
Glossary
Parameter Measurement Information
Explanation of Logic Symbols
Ordering Instructions
Mechanical Data
Tape and Reel Information
IC Sockets
3-1
m
)C
"C
ii'
:::s
Q)
r+
o·
:::s
o....
r-
o
CQ
ri'
en
-<
3
co
'0
3-2
3
Explanation of Logic Symbols t
3.1
Introduction
The International Electrotechnical Commission (lEC) has been developing a
very powerful symbolic language that can show the relationship of each input
of a digital logic circuit to each output without showing explicitly the internal
logic. At the heart of the system is dependency notation, which will be
explained in section 3.4.
The system was introduced in the USA in a rudimentary form in IEEE/ANSI
Standard Y32.14-1973. Lacking at that time a complete development of
dependency notation, it offered little more than a substitution of rectangular
shapes for the familiar distinctive shapes for representing the basic functions
of AND, OR, negation, etc. This is no longer the case.
Internationally, IEC Technical Committee TC-3 has approved a new document
(Publication 617-12) that consolidates the original work started in the mid
1960s and published in 1972 (Publication 117-15) and the amendments and
supplements that have followed. Similarly for the USA, IEEE Committee SCC
11.9 has revised the publication IEEE Std 91/ANSI Y32.14. Now numbered
simply IEEE Std 91-1984, the IEEE standard contains all of the IEC work that
has been approved, and also a small amount of material still under international
consideration. Texas Instruments is participating in the work of both
organizations, and this document introduces new logic symbols in accordance
with the new standards. When changes are made as the standards develop,
future editions will take those changes into account.
The following explanation of the new symbolic language is necessarily brief
and greatly condensed from what the standards publications now contain.
This is not intended to be sufficient for those people who will be developing
symbols for new devices. It is primarily intended to make possible the
understanding of the symbols used in various data books and the comparison
of the symbols with logic diagrams, functional block diagrams, and/or function
tables to further help that understanding.
3.2
II
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'0
.Q
E
en
>-
u
"0,
o
...I
o
c
o
;
CO
C
CO
C.
><
w
Symbol Composition
A symbol comprises an outline or a combination of outlines together with
one or more qualifying symbols. The shape of the symbol is not Significant.
As shown in Figure 3-1 , general qualifying symbols are used to tell exactly
what logical operation is performed by the elements. Table 3-1 shows general
qualifying symbols defined in the new standards. Input lines are placed on
the left and output lines are placed on the right. When an exception is made
to that convention, the direction of signal flow is indicated by an arrow as
shown in Figure 3-11 .
t Written by F. A. Mann.
3-3
OUTLINE
**
**~ OUTPUT
LINES
**
**
INPUT {
LINES
•..
m
>C
"C
Si'
::::J
CD
0'
::::J
o....
6'
CQ
n'
en
<
3
CO
iii
GENERAL QUALIFYING
SYMBOL
*Possible positions for qualifying symbols relating to inputs and outputs
Figure 3-1. Symbol Composition
All outputs of a single, unsubdivided element always have identical internal
logic states determined by the function of the element except when otherwise
indicated by an associated qualifying symbol or ·'abe' inside the element.
The outlines of elements may be abutted or embedded in which case the
following conventions apply. There is no logic connection between the
elements when the line common to their outlines is in the direction of signal
flow. There is at least one logic connection between the elements when the
line common to their outlines is perpendicular to the direction of signal flow .
The number of logic connections between elements will be clarified by the
use of qualifying symbols, and this is discussed further under that topic. If
no indications are shown on either side of the common line, it is assumed
there is only one connection.
When a circuit has one or more inputs that are common to more than one
element of the circuit, the common-control block may be used. This is the
only distinctively shaped outline used in the lEe system. Figure 3-2 shows
that, unless otherwise qualified by dependency notation, an input to the
common-control block is an input to each of the elements below the commoncontrol block.
A common output depending on all elements of the array can be shown as
the output of a common-output element. Its distinctive visual feature is the
double line at its top. In addition, the common-output element may have other
inputs as shown in Figure 3-3. The function of the common-output element
must be shown by use of a general qualifying symbol.
3-4·
COMMON~ONTROLBLOCK
a
b--+--I
b
c
d
d----i
Figure 3-2. Common-Control Block
d
t -.....- - - - d
II
II)
b
COMMON..()UTPUT ----I====i
ELEMENT
--c
(must, like other elements,
have. qualifying symbol to
denote its logic function)
"6
e
f
.c
b
u
'6»
o
c------~
Figure 3-3. Common-Output Element
Qualifying Symbols
3.3.1
General Qualifying Symbols
>
til
9
9
3.3
E
.......>-+-+----- e
........Io
c
o
'+0
co
C
CO
Q.
><
w
Table 3-1 shows general qualifying symbols defined by IEEE Standard 91.
These characters are placed near the top center or the geometric center of
a symbol or symbol element to define the basic function of the device
represented by the symbol or of the element.
3-5
Table 3-1. General Qualifying Symbols
SYMBOL
&
~1
=1
2k
2k + 1
1
[>or
DESCRIPTION
Read-only memory.
Random-access read/write memory.
First-in, first-out memory.
Element powers up cleared to 0 state.
Element powers up set to 1 state.
Highly complex function; "gray box" symbol
with limited detail shown under special rules.
CMOS
EXAMPLE
'HC189
'HC7022
TTL
EXAMPLE
SN74187
SN74170
SN74LS222
SN74AS877
SN74AS877
SM74LS608
*Not all of the general qualifying symbols have been used in TI's CMOS and TTL data books,
but they are included here for the sake of completeness.
3.3.2
General Qualifying Symbols for Inputs and Outputs
Qualifying symbols for inputs and outputs are shown in Table 3-2, and many
will be familiar to most users, a likely exception being the logic polarity symbol
for directly indicating active-low inputs and outputs. The older logic negation
indicator means that the external 0 state produces the internal 1 state. The
internal 1 state means the active state. Logic negation may be used in pure
logic diagrams; in order to tie the external 1 and 0 logic states to the levels
H (high) and L (low), a statement of whether positive logic (1 = H, 0 = L)
or negative logic (1 = L,O = H) is being used is required or must be assumed.
Logic polarity indicators eliminate the need for calling out the logic convention
and are used in various data books in the symbology for actual devices. The
presence of the triangular polarity indicator indicates that the L logic level
will produce the internal 1 state (the active state) or that, in the case of an
output, the internal 1 state will produce the external L level. Note how the
active direction of transition for a dynamic input is indicated in positive logic,
negative logic, and with polarity indication.
The internal connections between logic elements abutted together in a symbol
may be indicated by the symbols shown in Table 3-2. Each logic connection
may be shown by the presence of qualifying symbols at one or both sides
of the common line, and, if confusion can arise about the number of
connections, use can be made of one of the internal connection symbols.
II
II)
'0
..Q
E
en>(,)
's,
o
..J
~
o
c
o
'';:
CI:I
C
CI:I
0..
w><
The internal (virtual) input is an input originating somewhere else in the circuit
and is not connected directly to a terminal. The internal (virtual) output is
likewise not connected directly to a terminal. The application of internal inputs
and outputs requires an understanding of dependency notation, which is
explained in section 3.4.
3-7
Table 3-2. Qualifying Symbols for Inputs and Outputs
Logic negation at input. External 0 produces internal 1.
Logic negation at output. Internal 1 produces external O.
Active-low input. Equivalent to-q in positive logic.
Active-low output. Equivalent to p--in positive logic.
Active-low input in the case of right-to-Ieft signal flow.
Active-low output in the case of right-to-Ieft signal flow.
Signal flow from right to left. If not otherwise indicated, signal flow is from left
to right.
•
Bidirectional signal flow.
Dynamic
inputs
active
on
indicated
transition
POSITIVE
NEGATIVE
POLARITY
LOGIC
LOGIC
INDICATION
Lo 1Io
not used
oI
not used
°L
1
not used
H
L
L
S
-7<:1
Nonlogic connection. A label inside the symbol will usually define the nature of
this pin.
~
Input for analog signals (on a digital symbol) (see Figure 3-14).
~
~~~1~~~~
~~~~9~~~~
~~~~E~
Input for digital signals (on an analog symbol) (see Figure 3-14).
Internal connection. 1 state on left produces 1 state on right.
Negated internal connection. 1 state on left produces 0 state on right.
Dynamic internal connection. Transition from 0 to 1 on left produces transitory
1 state on right.
Internal input (virtual input). It always stands at its internal 1 state unless
affected by an overriding dependency relationship.
Internal output (virtual output). Its effect on an internal input to which it is
connected is indicated by dependency notation.
3-8
L
H
In an array of elements, if the same general qualifying symbol and the same
qualifying symbols associated with inputs and outputs would appear inside
each of the elements of the array, then these qualifying symbols are usually
shown only in the first element. This is done to reduce clutter and to save
time in recognition. Similarly, large identical elements that are subdivided into
smaller elements may each be represented by an unsubdivided outline. The
SN54HC242 or SN54LS440 symbol illustrates this principle.
3.3.3
Symbols Inside the Outline
Table 3-3 shows some symbols used inside the outline. Note particularly that
open-collector (open-drain), open-emitter (open-source), and 3-state outputs
have distinctive symbols. An EN input affects all the external outputs of the
element in which it is placed, plus the external outputs of any elements shown
to be influenced by that element. It has no effect on inputs. When an enable
input affects only certain outputs, affects outputs located outside the indicated
influence of the element in which the enable input is placed, and/or affects
one or more inputs, a form of dependency notation will indicate this (see
3.4.10). The effects of the EN input on the various types of outputs are shown.
en
It is particularly important to note that a D input is always the data input of
a storage element. At its internal 1 state, the D input sets the storage element
to its 1 state, and at its internal 0 state, it resets the storage element to its
o state.
"0
~
E
>
C/)
The binary grouping symbol will be explained more fully in section 3.8. Binaryweighted inputs are arranged in order, and the binary weights of the least
significant and the most significant lines are indicated by numbers. In this
document, weights of input and output lines will usually be represented by
powers of two only when the binary grouping symbol is used; otherwise,
decimal numbers will be used. The grouped inputs generate an internal number
on which a mathematical function can be performed or that can be an
identifying number for dependency notation (Figure 3-31). A frequent use is
in addresses for memories.
-
.~
C)
o
....I
o
c:
o
.~
co
c:
co
ii
><
w
Reversed in direction, the binary grouping symbol can be used with outputs.
The concept is analogous to that for the inputs, and the weighted outputs
will indicate the internal number assumed to be developed within the circuit.
Other symbols are used inside the outlines in accordance with the IEC/lEEE
standards but are not shown here. Generally, these are associated with
arithmetic operations and are self-explanatory.
When nonstandardized information is shown inside an outline, it is usually
enclosed in square brackets [like thesel. The square brackets are omitted when
associated with a nonlogic input, which is indicated by an X superimposed
on the connection line outside the symbol.
3-9
Table 3-3, Symbols Inside the Outline
Postponed output (of a pulse-triggered flip-flop). The output changes
when input initiating change (e.g., a C input) returns to its initial external
state or level. See paragraph 3.5.
Bi-threshold input (input with hysteresis)
N-P-N open-collector or similar output that can supply a
relatively low-impedance L level when not turned off.
Requires external pull-up. Capable of positive-logic wiredAND connection.
+
Passive-pull-up output is similar to N-P-N open-collector
output but is supplemented with a built-in passive pull-up.
N-P-N open-emitter or similar output that can supply a
relatively low-impedance H level when not turned off.
Requires external pull-down. Capable of positive-logic wiredOR connection.
•
Passive-pull-down output is similar to N-P-N open-emitter
output but is supplemented with a built-in passive pull-down.
m
><
"C
ii'
:;,
Three-state output.
....
D)
Output with more than usual output capability (symbol is oriented in
the direction of signal flow).
0'
:;,
Enable input
When at its internal 1-state, all outputs are enabled.
When at its internal O-state, open-collector and open-emitter outputs
are off, three-state outputs are in the high-impedance state, and
all other outputs (I.e., totem-poles) are at the internal O-state.
2r-
o
CO
(;'
m
<
J, K, R, S
Usual meanings associated with flip-flops (e.g., R = reset to 0,
= reset to 1).
S
3
C"
--+T
o
0'
Toggle input causes internal state of output to change to its
complement.
---1D
---1- --1m
---1
+m
---1-
D:}
3-10
+
Data input to a storage element equivalent to:
m
m
~!
Shift right (left) inputs, m = 1, 2, 3, etc. If m = 1, it is usually not
shown.
Counting up (down) inputs, m
not shown.
1, 2, 3, etc. If m
Binary grouping. m is highest power of 2.
1, it is usually
Table 3-3. Symbols Inside the Outline (Continued)
~CT= 15
CT
The contents-setting input, when active, causes the content of a
register to take on the indicated value.
=9r-
The content output is active if the content of the register is as indicated.
Input line grouping . . . indicates two or more terminals used to
implement a single logic input.
e.g., The paired expander inputs of SN7450.
"1"~
;~JE
Fixed-state output always stands at its internal 1 state. For example,
see SN74185.
3.4
Dependency Notation
3.4.1
General Explanation
Dependency notation is the powerful tool that sets the IEC symbols apart from
previous systems and makes compact, meaningful symbols possible. It provides
the means of denoting the relationship between inputs, outputs, or inputs and
outputs without actually showing all the elements and interconnections involved.
The information provided by dependency notation supplements that provided
by the qualifying symbols for an element's function.
In the convention for the dependency notation, use will be made of the terms
"affecting" and "affected." In cases where it is not evident which inputs must
be considered as being the affecting or the affected ones (e.g., if they stand
in an AND relationship), the choice may be made in any convenient way.
So far, eleven types of dependency have been defined, and all of these are used
in various TI data books. X dependency is used mainly with CMOS circuits. They
are listed below in the order in which they are presented and are summarized
in Table 3-4 following 3.4.12.
Section
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
3.4.10
3.4.11
3.4.12
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o
c:
'
o
as
c:
as
C.
w><
Dependency Type or Other Subject
G,AND
General Rules for Dependency Notation
V,OR
N, Negate (Exclusive-OR)
Z, Interconnection
X, Transmission
C, Control
S, Set and R, Reset
EN, Enable
M, Mode
A, Address
3-11
3.4.2
G (AND) Dependency
A common relationship between two signals is to have them ANDed together.
This has traditionally been shown by explicitly drawing an AND gate with
the signals connected to the inputs of the gate. The 1972 lEe publication
and the 1973 IEEE/ANSI standard showed several ways to show this AND
relationship using dependency notation. While ten other forms of dependency
have since been defined, the ways to invoke AND dependency are now
reduced to one.
In Figure 3-4 input b is ANDed with input a, and the complement of b is ANDed
with c. The letter G has been chosen to indicate AND relationships and is
placed at input b, inside the symbol. A number considered appropriate by the
symbol designer (1 has been used here) is placed after the letter G and also
at each affected input. Note the bar over the 1 at input c.
II
m
)C
'a
..o·
i"
::::1
I»
::::1
o
6"
:~--
c~
Figure 3-4. G Dependency Between Inputs
In Figure 3-5, output b affects input a with an AND relationship. The lower
example shows that it is the internal logic state of b, unaffected by the
negation sign, that is ANDed. Figure 3-6 shows input a to be ANDed with
a dynamic input b.
CQ
c:r
til
<
3
c::r
C1]t---+--J
b
o
0'
Figure 3-5. G Dependency Between Outputs and Inputs
3-12
a-fG1-b---t 1
Figure 3-6. G Dependency with a Dynamic Input
The rules for G dependency can be summarized thus:
When a Gm input or output (m is a number) stands at its internal 1 state,
all inputs and outputs affected by Gm stand at their normally defined
internal logic states. When the Gm input or output stands at its 0 state,
all inputs and outputs affected by Gm stand at their internal 0 states.
3.4.3
Conventions for the Application of Dependency Notation in General
The rules for applying dependency relationships in general follow the same
pattern as was illustrated for G dependency.
Application of dependency notation is accomplished by:
1)
2)
labeling the input (or output) affecting other inputs or outputs
with the letter symbol indicating the relationship involved (e.g.,
G for AND) followed by an identifying number, appropriately
chosen, and
labeling each input or output affected by that affecting input
(or output) with that same number.
If it is the complement of the internal logic state of the affecting input or output
that does the affecting, then a bar is placed over the identifying numbers at
the affected inputs or outputs (Figure 3-4).
If two affecting inputs or outputs have the same letter and the same identifying
number, they stand in an OR relationship to each other (Figure 3-7).
ba={G-1G1
c
1
a~>-1
b
&
II
U)
'0
.Q
E
>-
en
(,)
"6»
....o
o
c
o
"';;
ca
c
ca
-a>C
W
c
Figure 3-7. ORed Affecting Inputs
If the affected input or output requires a label to denote its function (e.g.,
"D"), this label will be prefixed by the identifying number of the affecting
input (Figure 3-15).
If an input or output is affected by more than one affecting input, the
identifying numbers of each of the affecting inputs will appear in the label
3-13
of the affected one, separated by commas. The normal reading order of these
numbers is the same as the sequence of the affecting relationships
(Figure 3-15).
If the labels denoting the functions of affected inputs or outputs must be
numbers (e.g., outputs of a coder), the identifying numbers to be associated
with both affecting inputs and affected inputs or outputs may be replaced
by another character selected to avoid ambiguity, e.g., Greek letters
(Figure 3-8).
a
~
b
C
•..
--
==t
a
a
~a
a
b
C
--
1
~1
1
Figure 3-8. Substitution for Numbers
3.4.4
m
V (OR) Dependency
The symbol denoting OR dependency is the letter V (Figure 3-9).
)C
'C
When a Vm input or output stands at its internal 1 state, all inputs and outputs
affected by Vm stand at their internal 1 states. When the Vm input or output
stands at its internal 0 state, all inputs and outputs affected by Vm stand
at their normally defined internal logic states.
iii
::I
m
c)"
::I
o
ro
....
a-f~3-b
CQ
(i'
b
[~l-,
a~ a~b
==
[=l----f;;l
rA
<
3
cr
~~JI>l:
o
ur
3=5=:
Figure 3-9. V (OR) Dependency
3.4.5
N (Negate) (Exclusive-OR) Dependency
The symbol denoting negate dependency is the letter N (Figure 3-10). Each
input or output affected by an Nm input or output stands in an Exclusive-OR
relationship with the Nm input or output.
When an Nm input or output stands at its internal 1 state, the internal logic
state of each input and each output affected by Nm is the complement of
3-14
what it would otherwise be. When an Nm input or output stands at its internal
o state, all inputs and outputs affected by Nm stand at their normally defined
internal logic states.
If a = 0, then c = b
If a = 1, then c = ii
Figure 3-10. N (Negate) (Exclusive-OR) Dependency
3.4.6
Z (Interconnection) Dependency
The symbol denoting interconnection dependency is the letter Z.
Interconnection dependency is used to indicate the existence of internal logic
connections between inputs, outputs, internal inputs, and/or internal outputs.
The internal logic state of an input or output affected by a Zm input or output
will be the same as the internal logic state of the Zm input or output, unless
modified by additional dependency notation (Figure 3-11 I.
3.4.7
X (Transmission) Dependency
The symbol denoting transmission dependency is the letter X.
•
en
"0
..Q
E
>
U)
CJ
"6»
....o
....o
I:
Transmission dependency is used to indicate controlled bidirectional
connections between affected input/output ports (Figure 3-121.
o
"';:;
C'CI
I:
When an Xm input or output stands at its internal 1 state, all input-output
ports affected by this Xm input or output are bidirectionally connected together
and stand at the same internal logic state or analog signal level. When an
Xm input or output stands at its internal 0 state, the connection associated
with this set of dependency notation does not exist.
C'CI
Q.
><
w
Although the transmission paths represented by X dependency are inherently
bidirectional, use is not always made of this property. This is analogous to
a piece of wire, which may be constrained to carry current in only one
direction. If this is the case in a particular application, then the directional
arrows shown in Figures 3-12, 3-13, and 3-14 are omitted.
3-15
a-f~-tb
-
f zt-a
-
'W'
a
where
-tl- =--i>-
where
-&=-<1-
a
m
><
'C
Dr
a----fGl~c
a
b-!!Z2
b
J
L~J
c
:::I
...o·
I»
:::I
Figure 3-11. Z (Interconnection) Dependency
o....
ro
cc
............__ b
ri'
a-
t/)
X1
1/11-........-
,. .....
<
3
If a = 1, there is a bidirectional
connection between band c.
c
d
If a = 0, there is a bidirectional
connection between c and d.
C"
o
en
Figure 3-12. X (Transmission) Dependency
n
I
n
p
........
JX1
a
..
1
1
......
b
·-lIt-·
I
p
Figure 3-13. CMOS Transmission Gate Symbol and Schematic
3-16
MUXDMUX
#
O}
X..!3!..
1
#
...... n ..
r
0
0/1/2/3
1
2
3
.. n .
n
....n
n ..
Figure 3-14. Analog Data Selector (Multiplexer/Demultiplexer)
3.4.8
C (Control) Dependency
The symbol denoting control dependency is the letter C.
Control inputs are usually used to enable or disable the data (0, J, K, R, or
S) inputs of storage elements. They may take on their internal 1 states.(be
active) either statically or dynamically. In the latter case, the dynamic input
symbol is used as shown in the third example of Figure 3-15.
When a Cm input or output stands at its internal 1 state, the inputs affected
by Cm have their normally defined effect on the function of the element; i.e.,
these inputs are enabled. When a Cm input or output stands at its internal
o state, the inputs affected by Cm are disabled and have no effect on the
function of the element.
II
tn
"0
.c
E
en>(.)
'0,
....o
o
r:::
o
'+i
«I
r:::
«I
Q.
><
w
3-17
a-fc~
b-t O
a~;b
C2
1.!!l
c
==
_a~&s-
-
~lC2
a
b
c
Gl
=
20
b
c
&
/
Note AND relationship of a and b
•
a
b
m
~
-
Gl
1.20
c
C2
><
't:I
6)
:::s
...O·
a
1.20
b
1.20
o....
c
G1
b
c
r-
o
d
C2
d-------'
c;'
Input c selects which of a or b is stored when d goes low.
I»
:::s
CC
en
-<
3
0-
o
Ui
3-18
Figure 3-15. C (Control) Dependency
R
3.4.9
5 (Set) and R (Reset) Dependencies
The symbol denoting set dependency
is the letter S. The symbol denoting
reset dependency is the letter R.
Set and reset dependencies are used
if it is necessary to specify the effect
of the combination R = S = 1 on a
bistable element. Case 1 in
Figure 3-16 does not use S or R
dependency.
When an Sm input is at its internal 1
state, outputs affected by the Sm
input will react, regardless of the
state of an R input, as they normally
would react to the combination S = 1 ,
R = O. See cases 2, 4, and 5 in
Figure 3-16.
When an Rm input is at its internal 1
state, outputs affected by the Rm
input will react, regardless of the
state of an S input, as they normally
would react to the combination S = 0,
R = 1. See cases 3, 4, and 5 in
Figure 3-16.
When an Sm or Rm input is at its
internal 0 state, it has no effect.
Note that the noncomplementary
output patterns in cases 4 and 5 are
only pseudo stable. The simultaneous
return of the inputs to S =R =0
produces an unforeseeable stable and
complementary output pattern.
CASE 1
s--ft--:
R-lJ--a
s---Fl-:
S
0
0
1
1
R
a a
0
1
0
1
nc
nc
0
1
1
0
?
)
CASE 2
R-U-
a
S
0
0
1
1
a
s-nR-U-
R
0
1
0
1
a a
R
a a
0
1
0
1
nc
nc
0
1
0
1
0
1
nc
nc
0
1
1
1
0
0
CASE 3
0
S
0
0
1
1
II
fI)
'0
.Q
CASE 4
s---Ft-:
S
0
0
1
1
R
a a
0
1
0
1
nc
nc
0
1
1
1
0
1
R
a a
0
1
0
1
nc
nc
0
1
0
1
0
0
Rtr
s-F1-:
R-U-
S
0
0
1
1
o= e.ternal 0 state
1 = e.ternall state
nc = no change
? = unspecified
a
E
>
en
(.)
's,
....o
-
CASE 5
Q
o
c
o
'';::;
CO
C
CO
-a><
w
Figure 3-16. S (Set) and
R (Reset) Dependencies
3.4.10 EN (Enable) Dependency
The symbol denoting enable dependency is the combination of letters EN.
An ENm input has the same effect on outputs as an EN input, see 3.3.3, but
it affects only those outputs labeled with the identifying number m. It also
affects those inputs labeled with the identifying number m. By contrast, an
EN input affects all outputs and no inputs. The effect of an ENm input on
an affected input is identical to that of a Cm input (Figure 3-17).
3-19
1'\7
b
a--t..-----i EN1
d
If a = 0, b is disabled and d = c
lfa = 1, c is disabled and d = b
c
Figure 3-17. EN (Enable) Dependency
When an ENm input stands at its internal 1 state, the inputs affected by ENm
have their normally defined effect on the function of the element, and the
outputs affected by this input stand at their normally defined internal logic
states; i.e., these inputs and outputs are enabled.
•
m
)C
'C
Dr
:::J
....m
0'
:::J
When an ENm input stands at its internal 0 state, the inputs affected by ENm are
disabled and have no effect on the function of the element, and the outputs affected
by ENm are also disabled. Open-collector outputs are turned off, three-state outputs
stand at their normally defined internal logic states but externally exhibit high
impedance, and all other outputs (e.g., totem-pole outputs) stand at their internal 0
states.
3.4.11 M (MODE) Dependency
o....
The symbol denoting mode dependency is the letter M.
ro
Mode dependency is used to indicate that the effects of particular inputs and
outputs of an element depend on the mode in which the element is operating.
CCI
(;'
en
If an input or output has the same effect in different modes of operation, the
identifying numbers of the relevant affecting Mm inputs will appear in the
label of that affected input or output between parentheses and separated by
solidi (Figure 3-22).
-<
3
C"
o
ur
3.4.11.1
M Dependency Affecting Inputs
M dependency affects inputs the same as C dependency. When an Mm input
or Mm output stands at its internal 1 state, the inputs affected by this Mm
input or Mm output have their normally defined effect on the function of the
element; i.e., the inputs are enabled.
When an Mm input or Mm output stands at its internal 0 state, the inputs
affected by this Mm input or Mm output have no effect on the function of
the element. When an affected input has several sets of labels separated by
solidi (e.g., C4/2-+/3 + l. any set in which the identifying number of the Mm
input or Mm output appears has no effect and is to be ignored. This represents
disabling of some of the functions of a multifunction input.
3-20
The circuit in Figure 3-18 has two inputs, band c, that control which one
of four modes (0, 1, 2, or 3) will exist at any time. Inputs d, e, and fare D
inputs subject to dynamic control (clocking) by the a input. The numbers 1
and 2 are in the series chosen to indicate the modes so inputs e and fare
only enabled in mode 1 (for parallel loading). and input d is only enabled in
mode 2 (for serial loading). Note that input 8 has three functions. It is the
clock for entering data. In mode 2, it causes right shifting of data, which means
a shift away from the control block. In mode 3, it causes the contents of the
register to be incremented by one count.
Note that all o'perations are synchronous.
In MODE 0 (b =0, c =0), the outputs
remain at their existing states as none
of the inputs has an effect.
a
b
c
In MO DE 1 (b =1, c = 0), parallel loading
takes place thru inputs e and f.
d
e
1,40
In MODE 2 (b =0, c =1), shifting down
and serial loading thru input d take place.
In MODE 3 (b =c =1), counting up by
increment of 1 per clock pulse takes place.
Figure 3-18. M (Mode) Dependency Affecting Inputs
II
(I)
'0
.Q
E
>o
(.)
3.4.11.2
M Dependency Affecting Outputs
's,
o
...I
When an Mm input or Mm output stands at its internal 1 state, the affected
outputs stand at their normally defined internal logic states; i.e., the outputs
are enabled.
When an Mm input or Mm output stands at its internal 0 state, at each affected
output any set of labels containing the identifying number of that Mm input
or Mm output has no effect and is to be ignored. When an output has several
different sets of labels separated by solidi (e.g., 2,4/3,5). only those sets in
which the identifying number of this Mm input or Mm output appears are to
be ignored.
....o
c
o
'';:;
CO
C
CO
Q.
><
w
Figure 3-19 shows a symbol for a device whose output can behave as either
a 3-state output or an open-collector output depending on the signal applied
to input 8. Mode 1 exists when input a stands at its internal 1 state, and,
in that case, the three-state symbol applies, and the open-element symbol
has no effect. When a = 0, mode 1 does not exist so the three-state symbol
has no effect, and the open-element symbol applies.
3-21
t>
a
M1
b
EN
1 'V/l~
c
d
Figure 3-19. Type of Output Determined by Mode
In Figure 3-20, if input a stands at its internal 1 state establishing mode 1,
output b will stand at its internal 1 state only when the content of the register
equals 9. Since output b is located in the common-control block with no
defined function outside of mode 1 , the state of this output outside of mode 1
is not defined by the symbol.
II
m
>C
'a
---1
Ml
lCT=9
I
I
&"
::::I
...0"
I»
I
(
~b
I
I
I
~
::::I
...
o
Figure 3-20. An Output of the Common-Control Block
~
o
CO
c:r
rn
'<
3
cr
o
0"
In Figure 3-21, if input a stands at its internal 1 state establishing mode 1,
output b will stand at its internal 1 state only when the content of the register
equals 15. If input a stands at its internal 0 state, output b will stand at its
internal 1 state only when the content of the register equals O.
·-t'
I
I
I
(
l~T'15~b
lCT=D
I
I
I
S
Figure 3-21. Determining an Output's Function
In Figure 3-22, inputs a and b are binary weighted to generate the numbers
0, 1, 2, or 3. This determines which one of the four modes exists.
3-22
:ll}-M!! - -;21~)te
c
d
N4
G5
3
04
'
2,4/3,5
-----
f
9
Figure 3-22. Dependent Relationships
Affected by Mode
At output e, the label set causing negation (if c = 1) is effective only in modes
2 and 3. In modes 0 and 1, this output stands at its normally defined state
as if it had no labels. At output f, the label set has effect when the mode
is not 0 so output e is negated (if c = 1) in modes 1, 2, and 3. In mode 0,
the label set has no effect so the output stands at its normally defined state.
In this example, 0,4 is equivalent to (1/2/3)4. At output g, there are two label
sets: the first set, causing negation (if c = 1), is effective only in mode 2;
the second set, subjecting g to AND dependency on d, has effect only in mode
3.
Note that in mode 0 none of the dependency relationships has any effect on
the outputs, so e, 1. and g will all stand at the same state.
3.4.12
A (Address) Dependency
The symbol denoting address dependency is the letter A.
Address dependency provides a clear representation of those elements,
particularly memories, that use address control inputs to select specified
sections of a multildimensional array. Such a section of a memory array is
usually called a word. The purpose of address dependency is to allow a
symbolic presentation of the entire array. An input of the array shown at a
particular element of this general section is common to the corresponding
elements of all selected sections of the array. An output of the array shown
at a particular element of this general section is the result of the OR function
of the outputs of the corresponding elements of selected sections.
II
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15
.0
E
>en
(.)
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....o
o
c
o
"';:
as
as
c
Q.
w><
Inputs that are not affected by any affecting address input have their normally
defined effect on all sections of the array, whereas inputs affected by an
address input have their normally defined effect only on the section selected
by that address input.
An affecting address input is labeled with the letter A followed by an
identifying number that corresponds with the address of the particular section
of the array selected by this input. Within the general section presented by
the symbol, inputs and outputs affected by an Am input are labeled with the
letter A, which stands for the identifying numbers, i.e., the addresses, of the
particular sections.
3-23
Figure 3-23 shows a 3-word by 2-bit memory having a separate address line
for each word and uses EN dependency to explain the operation. To select
word 1, input a is taken to its 1 state, which establishes mode 1. Data can
now be clocked into the inputs marked "1,40." Unless words 2 and 3 are
also selected, data cannot be clocked in at the inputs marked "2,40" and
"3,40." The outputs will be the OR functions of the selected outputs; i.e.,
only those enabled by the active EN functions.
•b
Al
A2
c
A3
C4
d
I
b
f
h
e
9
11
c
d
EN1
EN2
EN3
C4
e
9
m
>C
'C
iii
Figure 3-23. A (Address) Dependency
::::I
...o·
C»
The identifying numbers of affecting address inputs correspond with the
addresses of the sections selected by these inputs. They need not necessarily
differ from those of other affecting dependency inputs (e.g., G, V, N, ... l.
because, in the general section presented by the symbol, they are replaced
by the letter A.
::::I
o....
r-
o
CQ
c:;'
If there are several sets of affecting Am inputs for the purpose of independent
and possibly simultaneous access to sections of the array, then the letter A
is modified to 1A, 2A, .... Since they have access to the same sections
of the array, these sets of A inputs may have the same identifying numbers.
The symbols for 'HC170 or SN74LS170 make use of this.
(f)
'<
3
tT
o
Cii
Figure 3-24 is another illustration of the concept.
3.5
Bistable Elements
The dynamic input symbol, the postponed output symbol, and dependency
notation provide the tools to differentiate four main types of bistable elements
and make synchronous and asynchronous inputs easily recognizable
(Figure 3-51. The first column shows the essential distinguishing features;
the other columns show examples.
3-24
RAM 16 X 4
EN
}.,',
C1
Figure 3-24. Array of 16 Sections of Four Transparent Latches with 3-State
Outputs Comprising a 16-Word X 4-Bit Random-Access Memory
Table 3-4. Summary of Dependency Notation
LETTER
SYMBOL"
AFFECTING INPUT
AT ITS 1-STATE
Address
A
Permits action laddress selected)
Prevents action laddress not selected)
Control
C
Permits. action
Enable
EN
Permits action
Prevents action
Prevents action of inputs
Ooutputs off
Qoutputs at external high impedance,
no change in internal logic state
Other outputs at internal 0 state
TYPE OF
DEPENDENCY
AFFECTING INPUT
AT ITS O-STATE
AND
G
Permits action
Imposes 0 state
Mode
M
Permits action Imode selected)
Prevents action Imode not selected)
Negate lEx-OR)
N
Complements state
No effect
Reset
R
A ffected output reacts as
it would to S = 0, R = 1
No effect
Set
S
A ffected output reacts as
it would to S = 1, R = 0
No effect
OR
V
Imposes 1 state
Permits action
Transmission
X
Bidirectional connection exists
Bidirectional connection does not exist
Interconnection
Z
Imposes 1 state
Imposes 0 state
II
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o
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'Po
o
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'
o
ca
ca
c:
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w
"These letter symbols appear at the AFFECTING input (or output) and are followed by a number.
Each input (or output) AFFECTED by that input is labeled with that same number. When the
labels EN, R, and S appear at inputs without the following numbers, the descriptions above
do not apply. The action of these inputs is described under "Symbols Inside the Outline,"
see 3.3.3.
3-25
r- --,
I
-1 Cm
I
rI
I
L __ ..J
H
D
C1
C2
20
TRANSPARENT
LATCHES
1/2 SN74HC75
+cm ~
~D
U
r ---,
I
I
L ___ J
EDGE·TRIGGERED
C1
R
1/2 SN74HC74
U
C1
J
1K
R
1/2 SN74HC107
r ---,
I
-1Cm
I
m
><
'rI
...0'::s
r - --,
C»
::s
o....
r-
o
I
I
-tCm-'~
I
C1
R
I
PULSE·TRIGGER ED
1J
1K
L ___ J
'0
ii'
..,
..,
..,
1/2 SN74107
..,
,
I
L ___ J
DATA·LOCKOUT
SN74110
1/2SN74111
CO
C:;'
(J)
<
3
cr
o
(i)
3·26
Figure 3-25. Four Types of Bistable Circuits
Transparent latches have a level-operated control input. The D input is active
as long as the C input is at its internal 1 state. The outputs respond
immediately. Edge-triggered elements accept data from D, J, K, R, or 5 inputs
on the active transition of C. Pulse-triggered elements require the setup of
data before the start of the control pulse; the C input is considered static since
the data must be maintained as long as C is at its 1 state. The output is
postponed until C returns to its 0 state. The data-lockout element is similar
to the pulse-triggered version except that the C input is considered dynamic
in that, shortly after C goes through its active transition, the data inputs are
disabled, and data does not have to be held. However, the output is still
postponed until the C input returns to its initial external level.
Notice that synchronous inputs can be readily recognized by their dependency
labels (1 D, 1J, 1K, 15, 1 R) compared to the asynchronous inputs (5, R), which
are not dependent on the C inputs.
3.6
II
Coders
The general symbol for a coder or
code converter is shown in
Figure 3-26. X and Y may be replaced
by appropriate indications of the code
used to represent the information at
the inputs and at the outputs,
respectively.
en
15
..Q
E
Figure 3-26. Coder General
Symbol
Indication of code conversion is based on the following rule:
Depending on the input code, the internal logic states of the inputs
determine an internal value. This value is reproduced by the internal logic
states of the outputs, depending on the output code.
>-
f/)
u
'eon
...J
.....o
c:
o
',t:;
CO
The indication of the relationships between the internal logic states of the
inputs and the internal value is accomplished by:
c:
CO
Q.
>C
1) labeling the inputs with numbers. In this case, the internal value equals
the sum of the weights associated with those inputs that stand at their
internal 1-state, or by
2) replacing X by an appropriate indication of the input code and labeling
the inputs with characters that refer to this code.
W
The relationships between the internal value and the internal logic states
of the outputs are indicated by:
1) labeling each output with a list of numbers representing those internal
values that lead to the internal 1-state of that output. These numbers
shall be separated by solidi as in Figure 3-27. This labeling may also
be applied when Y is replaced by a letter denoting a type of dependency
3-27
TRUTH TABLE
c
0
0
0
0
XIV
•b
d
1/4
•
2/3
3/4
----
c
7
INPUTS
b a
1
1
1
1
•
9
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
OUTPUTS
f
d
•0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
Figure 3-27. An X/V Code Converter
(see section 3.7). If a continuous range of internal values produces the
internal 1 state of an output, this can be indicated by two numbers that
are inclusively the beginning and the end of the range, with these two
numbers separated by three dots (e.g., 4 . . . 9 = 4/5/617/8/9)
or by
2) replacing V by an appropriate indiction of the output code and labeling
the outputs with characters that refer to this code as in Figure 3-28.
•..
m
>C
'0
i»
::s
I»
TRUTH TABLE
0'
::s
X/OCT
o
d
~
r0O
cc
n'
t/)
<
3
cr
o
1
b
c
2
4
2
3
4
5
6
7
e
f
•
h
INPUTS
b a
c
0
0
0
0
1
1
1
1
j
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
i.
0
0
0
0
0
0
1
0
OUTPUTS
h 9
f
0
0
0
0
0
0
0
•
d
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
iii
1
Figure 3-28. An X/Octal Code Converter
Alternatively, the general symbol may be used together with an appropriate
reference to a table in which the relationship between the inputs and outputs
is indicated. This is a recommended way to symbolize a PROM after it hllS
been programmed.
3-28
3.7
Use of a Coder to Produce Affecting Inputs
It often occurs that a set of affecting
inputs for dependency notation is
produced by decoding the signals on
certain inputs to an element. In such
a case, use can be made of the
symbol for a coder as an embedded
symbol (Figure 3-29).
x/v
0
2
Gl
1 G2
2 V4
213 N5
C3
I
Figure 3-29. Producing Various
Types of Dependencies
If all affecting inputs produced by a
coder are of the same type as their
identifying numbers shown at the
outputs of the coder, V (in the
qualifying symbol XIV) may be
replaced by the letter denoting the
type of dependency. The indications
of the affecting inputs should then be
omitted (Figure 3-30).
3.8
3.9
D D
IM
I
2
--
IY
1
2
0
1
2
I
I
I
I
0
1
MD
M1
2
M2
Figure 3-30. Producing One Type
of Dependency
o
Use of Binary Grouping to Produce Affecting Inputs
EI
en
"'0
~
E
en>CJ
.c,
If all affecting inputs produced by a coder are of the same type and have
consecutive identifying numbers not necessarily corresponding with the
numbers that would have been shown at the outputs of the coder, use can .
be made of the binary grouping symbol. k external lines effectively generate
2k internal inputs. The bracket is followed by the letter denoting the type of
dependency followed by m1/m2. The m1 is to be replaced by the smallest
identifying number and the m2 by the largest one, as shown in Figure 3-31.
-
Sequence of Input Labels
Q.
If an input having a single functional effect is affected by other inputs, the
qualifying symbol (if there is any) for that functional effect is 'preceded by
the labels corresponding to the affecting inputs. The left-to-right order of these
preceding labels is the order in which the effects or modifications must be
applied. The affected input has no functional effect on the element if the logic
state of anyone of the affecting inputs, considered separately, would cause
the affected input to have no effect, regardless of the logic states of other
affecting inputs.
....o
o
c
o
.';:;
ca
ca
c
w><
If an input has several different functional effects or has several different sets
of affecting inputs, depending on the mode of action, the input may be shown
as often as required. However, there are cases in which this method of
3-29
x/v
0
1
-1
-
2
3
2
4
-4
5
6
7
o
A
A1
A2
A3
A4
A5
A6
A7
x/v
-1
-2
o
G5
1 G6
2 G7
3 G8
~_;...J
•
m
>C
"iii'::s
..
I»
0'
::s
o....
r-
o
CO
t;'
t/)
<
3
C"
o
ii'
Figure 3-31. Use of the Binary Grouping Symbol
presentation is not advantageous. In those cases, the input may be shown
once with the different sets of labels separated by solidi (Figure 3-32). No
meaning is attached to the order of these sets of labels. If one of the functional
effects of an input is that of an unlabeled input to the element, a solidus will
precede the first set of labels shown.
If all inputs of a combinational
element are disabled (caused to have
no effect on the .function of the
element), the internal logic states of
the outputs of the element are not
specified by the symbol. If all inputs
of a sequential element are disabled,
the content of this element is not
changed, and the outputs remain at
their existing internal logic states.
Labels may be factored using
algebraic techniques (Figure 3-33).
-f~~.~~~~~~
==
Figure 3-32. Input Labels
-f0~~5~~2~.~~
Figure 3-33. Factoring Input Labels
3-30
3.10
Sequence of Output Labels
If an output has a number of different labels, regardless of whether they are '
identifying numbers of affecting inputs or outputs or not, these labels are
shown in the following order:
1) If the postponed output symbol has to be shown, this comes first, if
necessary preceded by the indications of the inputs to which it must
be applied
2) Followed by the labels indicating modifications of the internal logic state
of the output, such that the left-to-right order of these labels corresponds
with the order in which their effects must be applied
3) Followed by the label indicating the effect of the output on inputs and
other outputs of the element.
Symbols for open-circuit or 3-state
outputs, where applicable, are placed
just inside the outside boundary of the
symbol adjacent to the output line
(Figure 3-34).
II
U)
If an output needs several different
Figure 3-34. Placement of
sets of labels that represent
3-State Symbols
alternative functions (e.g., depending
on the mode of action), these sets
may be shown on different output
lines that must be connected outside the outline. However, there are cases
in which this method of presentation is not advantageous. In those cases,
the output may be shown once with the different sets of labels separated
by solidi (Figure 3-35).
o.l:2
E
>
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U
's,
....o
o
c
o
.~
ai;1--fC;:~b
1CT=15
-------
af~-~~;=;~~;=~tb
---------
CO
C
CO
Q.
>C
W
=
- ai~--li:T:tb
1CT=15
------
Figure 3-35. Output Labels
Two adjacent identifying numbers of affecting inputs in a set of labels that
are not already separated by a nonnumeric character should be separated by
a comma.
3-31
If a set of labels of an output not containing a solidus contains the identifying
number of an affecting Mm input standing at its internal 0 state, this set of
labels has no effect on that output.
Labels may be factored using algebraic techniques (Figure 3-36).
Figure 3-36. Factoring Output Labels
m
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CO
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en
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If you have questions on this Explanation of Logic Symbols, please contact:
Texas Instruments Incorporated
F.A. Mann, MS 49
P.O. Box 655012
Dallas, Texas 75265
Telephone (214) 995-2659
IEEE Standards may be purchased from:
Institute of Electrical and Electronics Engineers, Inc.
IEEE Standards Office
345 East 47th Street
New York, N.Y. 10Q17
International Electrotechnical Commission (IEC) publications may be purchased
from:
American National Standards Institute, Inc.
1430 Broadway
New York, N.Y. 10018
3-32
Numerical Index
Functional Index
o Flip-Flop and Latch Signal Conventions
Explanation of Function Tables
Glossary
Parameter Measurement Information
Designer's Information
Ordering Instructions
Mechanical Data
Tape and Reel Information
IC Sockets
4-1
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4-2
HCMOS DESIGN CONSIDERATIONS
Present HCMOS data sheets specify, under Recommended Operating Conditions, Input tt = 1000 ns,
(10%-90%) for VCC = 2 V. Since devices can be in the threshold region from Vil MAX = 0.3 V to
VIH MIN = 1.5 V (this translates into 750 ns), there is a potential for clocked devices to go into the wrong
state from any induced ground glitch causing double clocking of the device while in the threshold region. Note
that operation of devices with input tt = 1000 ns at VCC = 2 V will not damage the device, however,
functionality is not guaranteed for ClK inputs while in the Shift, Count, or Toggle operating modes.
Devices susceptible to the above condition are:
HC107
HC109
HCl12
HC113
HCl14
HC160
HC161
HC163
HC164
HC165
HC166
HC190
HC191
HC192
HC193
HC194
HC195
HC390
HC393
HC4024
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TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
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4-4
DESIGNER'S INFORMATION
CMOS Circuitry
The elementary CMOS building blocks are the inverter and the transmission gate. Each uses a complementary pair of
one n-channel and one p-channel enhancement-type field-effect transistor. Figures I and 2 show these together with various
logic symbols t used in this book to represent them.
Figure 1. Inverters
II
Figure 2. Transmission Gates
Logic gates are created by transistors added in parallel or series to the transistors making up the elementary inverter.
Thus the simplest gates are inverting. See Figure 3. An odd number of additional inverters are sometimes added to the outputs
of gates to make them noninverting. Basic CMOS gates usually have no more than three inputs. Arrays of gates are used
when more than three signals are ANDed or ORed.
c
o
',i:
..o
CIS
-.
E
.E
U)
~
The Exclusive-OR or Exclusive-NOR gate is most easily implemented using two inverters and two transmission gates
as shown in Figure 4. In complex chains of gates, the inverters may be made unnecessary by complementary signals being
already available.
CD
c
en
'iii
CD
C
t The various logic symbols are equivalent. The distinctive-shape fonn of the inverter and gate symbols and the "TO" fonn of the transmission gate are
usually used in the device logic diagrams. The logic inversion symbol (0) is shown at the input or the output, whichever msintsins logical consistency
with the driving output or the driven input, and this technique is used to indicate the true/complement levels of the signal as it progresses through the
circuit. For example, see Figure 7 in this section. The rectangular forms of the inverter and gate symbols and the polarity indicator (1:>0.) rePlacing the
inversion symbol are usually used in this book only in the device logic symbols. The I> indicates a high-current output.
4-5
AB---r-\...
v
A~
~B~V
v
POSITIVE LOGIC: V = A B or A+B
:=D-V
y
POSITIVE LOGIC: V
= A+ii or AB
Figure 3. Gates
A-I~------------~--~
B ....~---+--I
A=O--'
B
V
POSITIVE LOGIC: V =AB +A Bor A0B
A~---------~~~
--------+-......f
B ....
V
POSITIVE LOGIC: Y = AB + A B or A0 B
Figure 4. Exclusive-OR/NOR Gates
4-6
V
The three-state output buffer has logic elements in the gate connections to each of the transistors in the final inverter
so that both may be turned off under the control of an enable function. Figure 5 illustrates an inverting output buffer.
The transparent latch is typically implemented as shown in Figure 6. This is the simplest form. Logic diagrams in this
book show that additional inverters may be added as buffers or to optimize timing. The true and complementary outputs
(Q and Q) may be taken off at other points. Outputs brought out to terminals are always buffered to minimize any feedback
effects. The one exception to this is the 'HCV device, which has unbuffered outputs.
Putting two transparent latches in series produces the edge-triggered D-type flip-flop. The inverters can be converted
to two-input gates to provide asynchronous set and reset functions. Figure 7 illustrates a negative-edge-triggered circuit.
Exchanging the connections of C and C produces a positive-edge-triggered version.
I>
EN
y
Figure 5. Inverting Three-State Output Buffer with Active-Low Enable
C
o-Fr-
o
a
C~Q
t-....- - Q
II
c
Figure 6. Transparent Latches
c
0
"';:;
s--------------------------~------~
ca
.E
.
0
o
~
Q
o
U)
~
ClK
Ii
I-~~+-Q
.5
0
CD
C
C)
";
CD
C
R-----------------t~--------------------------------~
Figure 7. Negative-Edge-Triggered D-Type Fiip-Fiops
4-7
Detailed logic diagrams for flip-flops are given .on the data sheets in this book when useful to illustrate special features
such as synchronous clearing, J/K inputs, and toggle enabling.
In general the logic diagrams in this book have been simplified. They are believed to correctly indicate the logic
implementation but should not be used to predict dynamic performance. Inverters existing in series may be combined or
eliminated in the diagram as shown in Figure 8.
OR
---i>o---
OR
OR
Figure 8. Simplification of Diagrams by Combining Inverters
High-Speed CMOS Characteristics
Table I compares the main characteristics of the high-speed CMOS family with those of standard TTL, LSTTL, STTL,
ALSTTL, ASTTL, and metal-gate CMOS.
Table 1. Performance Comparison of High-Speed CMOS with Several Other Logic Families
TECHNOLOGY*
SILICON-
METAL
GATE
GATE
CMOS
CMOS
STD
TTL
LOW-POWER
SCHOTTKY
TTL
ADVANCED
SCHOTTKY
LOW-POWER
TTL
SCHOTTKY
TTL
ADVANCED
SCHOTTKY
TTL
SN74LS
SN74AS
SN74ALS
SN74AS
10
2
19
1
8,5
10
2
19
1
8,5
105
10
10
3
4
1.5
40
1,4
12
35
40
125
70
200
11
100
20
57
4
13
Standard outputs
4
8
20
8
20
6
1.6
1,6
16
High-current outputs
48
24
64
24/48
48/64
Standard outputs
10
4
40
20
50
20
50
High-current outputs
15
4
601120
120/160
-0,001
60
-0,4
160
±0,001
120
-1,6
-2.0
-0.1
-0,5
Device series
SN74HC
4000
SN74
0,0000025
0.001
0,17
0,1
8
Power dissipation per gate (mWl
Static
At 100 kHz
Propagation delay time (ns) (CL = 15 pFI
Maximum clock frequency (MHz) (el = 15 pF)
Speed/Power product (pJI (at 100 kHz I
Minimum output drive (rnA) (Vo
c
(1)
en
cC'
..
....
o..
3
:::J
(1)
en
~
OA V)
Fan-out (LS loads)
Maximum input current, IlL (rnA) (VI = 0.4 VI
:t Family characteristics at 25°C, Vee
= 5 V; all values typical unless otherwise noted. This table is provided for broad comparisons only .
Parameters for specific devices within a family may vary. For detailed comparisons, please consult the appropriate data book.
:::J
...o·
D)
:::J
The major advantages of high-speed CMOS can be summarized as follows:
I. The high-speed CMOS family can operate at speeds comparable to LSTTL. The high-speed CMOS family has ac
parameters guaranteed at a supply voltage of 2 V, 4.5 V, and 6 V over the full operating temperature range into
a 50-pF load (also, 150 pF for high-current outputs). Note that at the higher operating frequencies, the power
consumption is also comparable to LSTTL (Figure 9).
2. Figure 9 also shows that the high-speed CMOS family covers a wide range of applications: low power drain for
low-speed systems, and a slightly higher drain for higher speed systems.
4-8
3. Minimum system power - only the gates that are switching contribute to system power consumption. This reduces
the size of the power supply required, hence provides lower system cost and improved reliability through lower
heat dissipation.
As mentioned previously. the power consumption for an individual gate at the maximum speed is comparable to
LSTTL. However in typical systems, only a fraction of the gates are switching at the clock frequency; therefore,
significant power savings can be realized. On a system level where the individual gate switching frequencies are
distributed between zero and the system clock frequency (Figure 10), the power saved with high-speed CMOS can
be quite significant, as illustrated in Figure 11. The total system power is the area under each curve. The graph
in Figure 11 is obtained by mUltiplying the individual gate characteristics (Figure 9) by the frequency distribution
in Figure 10.
4. High-speed CMOS is ideal for battery-operated systems, or systems requiring battery back-up, because there is virtually
no static power dissipation (Figure 9).
~~------~------------~~
w
5
0..
FREQUENCY
Figure 9. Power Consumed Versus Frequency for High-Speed CMOS Compared to LSTTL
t:
o
"';:
a:s
E
...
....o
.E
....
I/)
FREQUENCY ------.
Figure 10. Typical Distribution of Switching Frequencies .for Gates
within a System with Maximum Clock Frequency, fs
5. Improved noise immunity over bipolar devices is due to the rail-to-rail (Vee to ground) output voltage swings.
Figure 12 illustrates the noise immunity provided by the high-speed CMOS family as it compares to the LSTTL
family. This noise immunity makes it ideal for high-noise environments. Minimum and maximum output voltages
are guaranteed at 4 rnA (6 rnA for high-current devices). If the output currents exceed these limits, the noise immunity
will be impaired. 'HCT devices have similar input noise margins to LSTTL because their inputs are TTL-voltage
compatible. The outputs of 'HCT are the same as standard 'HC outputs.
Go)
t:
C)
"C;;
Go)
C
4-9
6. High-speed CMOS devices can drive up to 10 LSTTL loads (15 LSTIL loads for high-current outputs) while
maintaining good noise immunity. Although VOHmin and VOLmax are guaranteed for output currents up to 4 rnA
(6 rnA for high-current outputs), currents up to ± 25 rnA (± 35 rnA for high-current outputs) can be obtained to
drive LEOs or relays (see Driving LEOs and Relays in this section.)
a::
OW
I-~
ZQ.
Q:;;
I-w
;;;)1Ill'"
->
a::",
1- ...
Zc(
01·°0
I-
FREQUENCY--+
Figure 11. Contribution to Total Power by Gates Running at Frequencies from 0 to fs
6
VOH =VCC -0.1 V
5
VNH(HCI = 0.29 VCC
4
VIH-0.7VCC
i
1
l-
;;;)
Q.W
I-CI
;;;)c(
e~
1-0
it>
i!:
•
c
i
3
VOH=2.7V
+
o
CD
VNH(LSI = 0.14 VCC
cO·
..
VIH=2V
+
-2
::::I
CD
0"
S-
.
O'
VIL=0.8V
VNL(LSI = 0.08 VCC:
VOL=0.4V
3
&»
...o·
::::I
Vee = 5 V ±10%
- - -•• POWER SUPPLY VOLTAGE
Figure 12. High-Speed CMOS and LS Noise Margins
4-10
7. High-speed CMOS devices are guaranteed over an extended temperature range:
SN54HC/HCT'
SN74HC/HCT'
-55°C to 125°C
-40°C to 85°C
(military)
(industrial)
All specified ac and dc characteristics are guaranteed over this range with the exception of Power Dissipation
Capacitance (Cpd), which is specified as a typical value at 25°C.
Protection Circuitry
Electrostatic discharge (ESD) and latch-up are two traditional causes of CMOS device failure. In order to protect HCMOS
devices from ESD and latch-up, additional circuitry has been implemented on the inputs and outputs.
ESD PROTECTION
ESD occurs when a buildup of static charges on one surface arcs through a dielectric to another surface that has the
opposite charge. The end effect is the ESD causes a short between the two surfaces. These damaged devices (walking-wounded)
may still pass normal data sheet tests, but will eventually fail. The unique input protection circnitry designed by Texas Instruments
provides immunity to typically 4500 V on the inputs and 3000V on the outputs, which exceeds
MIL-STD-883B, Method 3015, requirements for ESD protection (2000 V, 1.5 kll, 100 pF).
Figure 13 shows the circuitry implemented to provide protection for the input gates against ESD. The diode is forward
biased for input voltages greater than Vee + 0.5 V. The two transistors and resistor (actually one transistor diffused across
a resistor) act as a resistor-diode network against negative-going transients. As illustrated in Figure 14, the ESD protection
for the output consists of an additional diffused diode (D3) from the output to Vee. The other diodes (D I and D2) are parasitics.
For further information on handling CMOS devices, see Guidelines for Handling ESDS Devices aod Assemblies in this section.
r-----------~--------------~-----vcc
INPUT PIN
o----4I-----------...-----llV..,.,------<~----~ TO GATES
Figure 13. ESD Input Protection Circuitry
II
c
o
',i:
«S
vcc-------------.--~~----_,
01
.
E
03
...--...---.~_4~---O OUTPUT PIN
-o
c
02
=
Figure 14. ESD Output Protection Circuitry.
Dl and D2 are Parasitic Diodes
4-11
LATCH-UP PROTECTION
Internal to most all CMOS devices are two parasitic bipolar transistors; one p-n-p and one n-p-n. Figure 15 shows the
cross section of a typical CMOS inverter with the parasitic bipolar transistors. Note that, as shown in Figure 16, these parasitic
bipolar transistors are naturally configured as a thyristor or SCR. These transistors conduct when one or more of the p-n
junctions become forward biased. When this happens, each parasitic transistor supplies the necessary base current for the
other to remain in saturation. This is known as the "latch-up" condition and could possibly destroy the device if the supply
current is not limited.
INPUT
Vcc
OUTPUT
Figure 15. Parasitic Bipolar Transistors in CMOS
Vcc
Vcc
III
N SUBS.TRATE
RESISTANCE
c
CD
en
til'
...
..3
~
....._ _-t'I
NGATE
CD
en
=
S"
Figure 16. Schematic of Parasitic SCR - P Gate and N Gate Electrodes are Connected Together
~
o
C»
r+
0'
~
A conventional thyristor is fired (turned on) by applying a voltage to the base of the n-p-n transistor, but the parasitic
CMOS thyristor is fired by applying a voltage to the emitter of either transistor. One emitter of the p-n-p transistor is connected
to an emitter of the n-p-n transistor, which is also the output of the CMOS gate. The other two emitters of the p-n-p and
n-p-n transistors are connected to Vee and ground, respectively. Therefore, to trigger the thyristor there must be a voltage
greater than Vee + 0.5 V or less than - 0.5 V and there has to be sufficient current to cause the latch-up condition.
Latch-Up cannot be completely eliminated! The alternative is to impede the thyristor from triggering. Texas Instruments
has improved the circuit design by adding four additional diffusions or guard rings alternately connected to Vee and ground
as shown in Figure 17. The guard rings provide isolation between the device pins and any p-n junction that is not isolated
by a transistor gate. All internal p-n junctions are separated by two guard rings. Tests have shown effective latch-up protection
ranges from 450 rnA to greater than 1 A at 25°C, and typically greater than 250 rnA at 125°C.
4-12
FOUR·GUARD·RING ISOLATION
Vcc
GND
Vcc
GND
DRAIN
CGNDI
Figure 17. Unique Latch-Up Suppression Utilizes Guard Rings to Virtually Eliminate Latch-Up
Fan-Out and Capacitance Loading Effects
High·Speed CMOS is capable of up to 10 LSITL loads from a single standard output. or 15 loads from a high-current
output. From the dc values in the individual data sheets. the fan-out of high-speed CMOS devices is unlimited for all practical
purposes. However. from an ac point of view. there is a definite limit to the fan-out. The limiting constraint is the input rise time.
With a worst-case model. about 15 pF of capacitance is associated with the input of a high-speed CMOS device (10 pF
from the device itself plus 5 pF of stray capacitance; typically. the input capacitance is 3 pF for all devices except the transceivers.
which are 6 pF). The input resistance. 11. and the output resistance. roo can be approximated with the following equations
using the information contained in the electrical characteristics chart of the device in question.
where
VI = VCC
6V
II = 0.1 nA
ro
= (VCC - VOH)IIOH
where
Vcc = 4.5 V
VOH = 4.3 V (typical)
IOH = 4 rnA
II
The calculated input resistance is about 60 MD and the maximum output resistance is approximately 50 0. Figure 18
shows the schematic of the output and the input models using the values previously determined.
50.n
25.n
c
o
",j::
'..E"
~
.E
.5
.
o
VOH
~
VOL
Cj
'i
G)
C
C)
Cal OUTPUT MODEL
Cbl INPUT MODEL
';;
G)
C
Figilre 18. Worst-Case Output and Input Circuits of High-Speed CMOS
4-13
For a fan-out of n high-speed CMOS devices, the input capacitance will be (n x 15) pF (capacitances are in parallel).
When the driving device switches its output from the low level to the high level, the input capacitance of all devices in the
fan-out must be charged up and reach VIHmin within 500 ns (the recommended rise time). Therefore,
where
R= 50 ()
C= (15 x n) pF
t= 500 ns
n = number of devices in the fan-out
Taking the natural log of both sides:
-tlRC = In(1 - VIHminIVOHtyP)
Substituting in the appropriate values and solving for n indicates that the maximum fan-out of high-speed CMOS devices
is approximately 505. Alternately, solving for t in terms of n shows that each high-speed CMOS device added to the fan-out
will increase the propagation delay from input of the driving device to the input of the driven devices by about 0.989 ns.
This corresponds to approximately 0.066 ns/pF of added delay. Table 2 contains typical values of fan-out and capacitive
loading effects at different values of Vee.
Table 2. Typical Fan-Out of High-Speed CMOS Devices and·
Propagation Delay per pF at Various Values of Vee
n
tpd/pF
936
0.0667 ns
3.15 V
993
0.0629 ns
4.2 V
1004
0.0623 ns
Vee
2V
VOHmln
1.9 V
VIHmin
1.4 V
4.5 V
4.4V
6V
5.9 V
NOTE:
-tlRC
•
where
R= 50!l
C= 8 pF
n = number of devices in the fan-out
500 ns
tpd/pF= n x 8 pF
Power Dissipation
-..
o
::::I
3
D)
pot.
o·
::::I
The power dissipation of high-speed CMOS devices can be separated into three components: (1) quiescent power dissipation,
PQ; (2) transient power dissipation, I>r; and (3) capacitive power dissipation, PC. The total power dissipation is the sum
of the three components, PQ + I>r + Pc.
The quiescent power is the product of Vee and the quiescent current, Icc. The quiescent current is the reverse current
through the diodes that are reverse biased. This reverse current is generally very small (on the order of a few nA), which
makes the quiescent power almost insignificant. However, for circuits that are in static conditions for long periods of time,
the quiescent power becomes a factor to be considered.
4-14
The transient power is due to the current that flows only during the time the transistors are switching from one logic
level to the other. During this time both transistors are partially on (one turning off, the other turning on), which produces
a low-impedance path between vee and ground and results in a current spike. The rise (and fall) time of the input signal
has a direct effect on the duration of the current spike. This is because the faster the input signal goes through the transition
region, the less time both transistors are partially on. The transient power is dependent on the characteristics of the transistors,
the switching frequency, and the rise time of the input signal. This component can be calculated using the following equation:
where
Cpd = power dissipation capacitance (specified on each data sheet)
Vee = supply voltage
fj = input signal frequency
Additional capacitive power dissipation is caused by the charging and discharging of the external load capacitance and
is dependent on the switching frequency. To calculate this power, the following equation may be used:
where
CL = external (load) capacitance
Vee = supply voltage
fo = output signal frequency
'HCT POWER DISSIPATION
'HCT devices are primarily used to interface TTL output signals to high-speed CMOS inputs. To make the inputs of
the 'HCT devices TTL-voltage compatible, the input transistor geometries were changed. This increased the power consumption
compared to the equivalent 'HC device, however 'HCT still provides a considerable savings in power over TTL. The increase
in power consumption is due to the fact that the TTL input levels cause both transistors in the transistor pair to be partially
turned on. Included in the electrical characteristics chart for 'HCT devices is a parameter AlCC, which enables the designer
to compute how much additional current the 'HCT device draws per input when at a TTL voltage level.
Power Supply Decoupling
When an SN54HC174HC gate switches, there is a brief period (on the order of a nanosecond) during which both transistors
in the gate output buffer (Figure 19) are partially on. In this interval, the device draws a substantial supply current, producing
a current spike on the Vee and ground leads to the gate. This spike may exhibit dildt as high as 5000 A/s. These spikes
will react with the distributed inductance of the supply wiring to produce significant voltage transients on Vee and ground
unless adequate supply decoupling is provided. These transients, if allowed, will couple directly into the gate outputs, which
in normal usage switch from rail-to-rail.
Vee
0-----3--,
INPUT
•
c
o
+i
CO
-E
~
o
c
r~u,
"D~
Figure 19. Gate Output Buffer
4-15
DECOUPLING PROCEDURE
Figure 20 illustrates a circuit for testing the effectiveness of decoupling. In this test circuit, the Vee and ground connections
consist of two parallel runs of one-eighth inch copper on a G-IO epoxy-glass circuit board. As a O.OI-,.F decoupling capacitor
between Vee and ground is physically moved away from a driven gate in 1.5-inch increments, Vee transients increase as
shown in Figure 21.
I
I
I
--L.
Vcc=5V
"....
I 0.01 /IF
I
5 V p.p SQUARE WAVE
INPUT TO GATE
I
I
1.5
3
4.5
6
7.5
9
INCHES
Figure 20. Test Circuit for Decoupling Effects
TYPICAL POWER SUPPLY DECOUPLING
1.0
_
VCC~5V
L
C=O.OI/1F
0.9 -
TA =25"C
L
0.8
A
/
0.7
/
~
.!
0.6
~I
0.5
>
0.4
~
•
tJ
tJ
./
0.3
cCD
0.2
en
0.1
cE'
~
L
o
/
1.5
/'
/
6.0
7.5
3.0
4.5
Distance From Package-Inches
9.0
....en
Figure 21. VCC Transients vs Decoupling Capacitor Distance from DIP
5'
....
o
The results indicate the importance of adequate decoupling, and illustrate the correct procedure for obtaining it. This
procedure consists of locating decoupling capacitors as close as possible to the integrated circuit package, in order to maximize
noise margins .
CD
..3
C»
r+
Connecting Unused Inputs
0'
~
Unused inputs should be tied to Vee or ground to prevent the input from floating. If left to float, the power consumption
of the device will increase.
4-16
Matching
Another factor to consider when designing with high-speed CMOS is the VOHlnin-to-Vr matching. This is important
when the VOHmin of the driving device exceeds the Vee + 0.5 V of the driven device. If this occurs, the ESO protection
diode on the inputs will be forward biased. At this point, the driving device will attempt to "power-up" the driven device's
power supply. No damage will occur to the driven device, provided the current flowing through the diode does not exceed
20mA.
Powering Up/Down Sequence for High-Speed CMOS
To avoid any possible damage and reliability problems to the high-speed CMOS devices when applying power, the following
steps should be followed:
I. Connect ground
2. Connect Vee
3. Connect the input signal
When powering down a high-speed CMOS device, follow the above steps in reverse order.
High-Speed CMOS Interfacing
INTRODUCTION
The High-Speed CMOS logic family from Texas Instruments contains a broad spectrum of SSIIMSI functions. Within
this family are TTL functions, HCT devices, HC4000 series, and an HCU device. I Entire CMOS systems may be implemented
using this logic family. There is also a broad range of CMOS-system to non-CMOS-system interfaces that need to be considered.
The design engineer will inevitably encounter these interfaces. To develop the necessary interfaces, a thorough understanding
of data sheet parameters of both systems and an organized approach is recommended. This report uses basic examples to
present one possible approach to the SN54174HC interface solution.
There are two types of interfacing that must be considered: (1) interfacing CMOS system signals to non-CMOS systems
and (2) interfacing non-CMOS system signals to CMOS systems. The first type requires an understanding of the CMOS
output parameters and the non-CMOS input parameters and vice versa for the second type. In both cases, a model of the
inputs and outputs of both systems may be useful.
II
c
o
GENERAL INTERFACING SOLUTION
0';:;
An interfacing problem arises when the output logic levels and/or the current requirements of the driving system (or
device) are different from the input logic levels and/or the current requirements of the driven system (or device). When
determining the compatibility of the systems (or devices), the most important system/device parameters are VIH, VIL, VOH,
VOL, IIH, IlL, IOH, and VOL·
E
...
C'CI
....o
.5
...
.tn
Figure 22 is the voltage transfer characteristic of a typical unloaded inverter showing the various input and output voltage
parameters. Loading the output of the inverter will tend to lower VOH and raise VOL. The tables of electrical characteristics
specify minimum VOH and maximum VOL for various loads.
C\)
C
C)
0;;
Noise Margin
C\)
C
There are two noise margins to be considered: the low-voltage noise margin and the high-voltage noise margin. The
voltage difference between VILmax of the driven system/device and VOLmax of the driving system/device is the low-voltage
noise margin. The voltage difference between VOHmin of the driving system/device and VIHmin of the driven system/device
is the high-voltage noise margin (Figure 23).
I HCT devices are explained later. The HC4000 series devices are pin-for-pin functionally compatible, but not electrically compatible, with the older meta1gate CMOS devices. The HCU device is unbuffered.
4-17
It is desirable to have the noise margin as large as possible and the uncertain region (the difference between Vrnmin and
VJLIlIIlX) as sma1l as possible. When an input voltage falls into the uncertain region, we do not know how the output in conjuction
with other inputs driven by that output will respond. The problem with small noise margins is that any noise on the output
of the driving system or device will cause the signal to fall into the uncertain region and possibly cause a bit error in the
system. There are various sources of noise in digital systems. Three possible internal sources are inductive and resistive
drops, capacitive coupling from another logic node, and mutual inductance with another logic node. Radio signals are possible
external sources of noise.
Vo
---+I
I
I
I
I
I
I
I
__ 1. __ _
Figure 22. Voltage Transfer Characteristic of a Typical Inverter
Vo DRIVING DEVICE
•
VI DRIVEN DEVICE
Figure 23. Noise Margins
As an aid for interfacing between the various TTL families, the eight parameters previously defined are shown in Table 3.
The values are for Vee = 5 V and TA = 25°C (worst-case device parameters - the device will perform at least this well).
All currents are designated positive when flowing into the device.
4-18
Table 3. Worst-Case Values of Primary Interfacing Parameters
PARAMETER
74HCMOS
3.5 V
VIHmin
VILmax
VOHmin
VOLmax
IIHmilx
74TTL
2V
0.8 V
2.4V
0.4 V
74LSTTL
2V
1 ~A
-1 ~A
-4 rnA
40 ~A
-1.6 mA
4mA
16mA
20 ~A
-400 ~A
-400 ~A
8 rnA
1V
4.9 V
0.1 V
IILmax
IOHmax
IOLmax
-400~
0.8 V
2.7 V
0.4V
74ASTTL
2V
0.8 V
2.7 V
0.4 V
74ALSTTL
2V
0.8 V
2.7 V
0.4 V
200 ~A
-2 rnA
-2 rnA
20 ~A
-100 ~A
-400 ~A
4 mA
20 rnA
Driving Gate Output Model
Figure 24 shows the model of a driving gate derived from the data sheet specifications. VOH(n1) (nl = no load) is the
high-level output voltage expected when the output gate is unloaded. VOL(n1) is the low-level output voltage expected when
the output gate is unloaded. The values for these two voltages are usually not given on the data sheets. As a rule of thumb
for MOS devices, the output switches between the power rails VOH(n1) = Vee and VOL(n1) = GNO; for bipolar devices
(e.g., the TTL Family) VOL(n1) is about Vec(;.;4.;.1..._ _ OUTPUT
>;.;(4.;..1...._ _ OUTPUT
R: 2.7 kn to 2.7Mn
C: 50pFto 10",F
Figure 35. 0scllIat0r Circuit
Using a Crystal to Set the Period
Figure 34. Simple RC Osclliator
Using Two 'HC04 Gates
VOLTAGE-CONTROLLED OSCILLATORS
Voltage-controlled oscillators (VCOs) can also be designed using a minimal number of components. Figure 36 shows a
VCO using NAND and inverter gates. This VCO design exploits the phenomena of the slight variations in the propagation
delay of an 'HC gate with changes in the supply voltage. The 'HCOO is connected as a three-stage ring oscillator with a
buffer. As the control (supply) voltage Vc is varied, the ring oscillator's frequency changes according to the following:
fout "" 5.8 x Vc
r--------- -------,
Vc
I
I
(11
I
'21
(141
(131
(111
l00kn
12
I
OUTPUT
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(BII
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I 0.01 ",F
I
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L _______
~-------J
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Figure 36. Voltage-Controlled OscUlator (YCO)
The inverter, which is powered by a separate voltage source, serves to restore the oscillator output voltage to 5 V peak-topeak. This function is required, because the 'HCOO switches from rail-to-rail (as do all HC devices). The magnitude of the
oscillator output voltage is thus dependent on VC. The l00-ldl resistor across the inverter provides bias such that operation
will be within the linear operating region of the gate. The capacitor serves to ac-couple the oscillator to the inverter .
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4-26
The VCO output is linear for control voltages in the range of 1.5 to 4.5 V (Figure 37).
To prevent oscillator "bleed-through" onto the VCC line, adequate decoupling of the 'HC device power supply is required.
N
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10
L
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/
/
0
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TA = 2JO C
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3
4
5
VC-Control Voltage-V
Figure 37. VCO Output Frequency vs Input Voltage
Drivers for LEDs and Relays
INTRODUCTION
SN54174HC devices are capable of sinking or sourcing up to 25 rnA (35 rnA for high-current devices) per gate. As the
device sinks or sources more current, VOHmin or VOLmax levels will begin to fall or rise respectively.
Because of these characteristics, SN54174HC devices can be used to drive LEOs and relays.
DRIVING LEOs
Figure 38 shows an 'HC04 driving a TIL221 gallium phosphide light-emitting diode. The resistor performs the function
of current limiter. The luminous intensity of the LED depends on the amount of forward current.
VCC
a
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o
VIL AT THE INPUT TURNS ON THE LED
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o
VIH AT THE INPUT TURNS ON THE LED
Figure 38. 'HC04 Driving a LED
Example: Using 10 rnA forward current and 2.2 V forward voltage, the value of the current-limiting resistor can
be calculated using the following equations:
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[for Figure 38(a)] R = VOH - 2.2 V
lOrnA
[for Figure 38(b)] R
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VCC - 2.2 V - VOL
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lOrnA
C
It should be noted that as used here, VOH aod VOL are not the V.OHmin and Vounax specified in the data book. Figures 39
and 40 show typical values for VOH and VOL for an 'HCoo.
4-27
5
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4
3
5
VCC I=5V
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VCC=5V
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4 -VI=VIH
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TA=25'C
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3
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0
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VI=VIL
TA=25'C_
2
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1\
-10
-20
-30
-40
'OH-High-Level Output Current-mA
Figure 39. Typical Values for VOH
-50
o /
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V
/
/
30
40
10
20
IOL -Low-Level Output Current-mA
50
Figure 40. Typical Values for VOL
DRIVING RELAYS
Multiple gates can be connected in parallel to increase the current sinking or sourcing capability of SN54174HC devices.
Figure 41 shows two 'HC04 gates connected in parallel for relay driver application.
Precautions should be taken to prevent one gate from "hogging" the current. SmaIl resistors (typically 50 0) in series
with the output gate will limit the possibility of "current hogging" by anyone gate.
In all applications in which the SN54174HC output is required to source or sink substantial current (6 rnA to 25 rnA),
particular attention should be paid to providing adequate power supply decoupling for the driving device.
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Figure 41. SN54174HC04 Gates Connected in ParaUel to Drive a Relay
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SNS4HC/SN74HC Interchangeability Guide
INTRODUCTION
The following has been prepared as a guide to interchanging devices from other logic families, both bipolar and CMOS,
with those from the SN54HC/SN74HC family. This is not intended to be a comprehensive guide since interchangeability
can depend on many factors, and only careful data sheet comparisons can provide definitive answers. The considerations
listed below are based upon information accumulated in answering a large number of inquiries in this area.
First, a brief review is given on each logic technology, and second, discussion is given on the various aspects involved
in attempting to interchange that technology with the SN54HC/SN74HC family.
4-28
TIL: Transistor-Transistor Logic
TTL is the generic name for several bipolar families that have evolved over the past 20 years. Low-Power Schottky
(LSTTL) is the most widely used bipolar logic family today. Other families, e.g., Schottky (STTL), Advanced Schottky
(ASTTL or AS), and Advanced Low-Power Schottky (ALSTTL or ALS) are also used, depending on the speed versus power
performance required by a given system design.
4000 Series: Metal-Gate CMOS Logic
The device type numbers in this series have a variety of prefixes, although "CD" is probably the most widely recognized.
The suffix "B" is frequently used, indicating an improvement over the original family, i.e., buffered outputs and typical
output sink and source current capabilities of ± 1 rnA. This logic family became popular because it offered very low power
consumption, even though it is slower than TTL with a typical operating frequency of about 5 MHz, has a low level of ESD
protection, and is latch-up prone.
40HOO Series: Metal-Gate CMOS Logic
This series was designed to overcome the speed limitations of the original 4000 family. Even though these devices are
somewhat faster, they are still slow when compared to LSTTL.
74COO Series: Metal-Gate CMOS Logic
The distinguishing feature of this family is that the pinouts correspond to those of TTL, making interchangeability easier.
The devices, however, exhibit many of the same speed/power limitations as those of the 4000 series. The fan-out is typically
higher than the 4000 series, however, with typical output sink and source capabilities of ± 1.75 rnA.
74SCOO Series: Silicon-Gate CMOS Logic
This series was the forerunner to the SN54HC/SN74HC family, or more closely, to the SN54HCT/SN74HCT family.
The 74SC family was designed to overcome many of the 4000 series deficiencies, particularly the slower speed and the lower
drive capability.
Note: The "SC" designation should not be confused with that of Texas Instruments new Standard Cell family
(SN54SC/SN74SC series).
II
INTERCHANGEABILITY CONSIDERATIONS
Listed below are the highlights of benefits derived from replacing other logic families with SN54HC/SN74HC; also listed
are important considerations that may affect the feasibility or desirability of such replacement. All comparisons are by necessity
general in nature.
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LSTTL
-
Considerations:
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1. SN54HC/SN74HC high-level input voltage is not TTL-compatible. In a mixed family system (LS output driving
HC input) it will be necessary to use SN54HCT/SN74HCT, pull-up resistors, or level shifters.
2. SN54HC/SN74HC has less drive capability than some LSTTL functions.
3. LSTTL open-collector outputs have higher breakdowns than SN54HC/SN74HC open-drain equivalent functions.
HCMOS advantages:
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1. Lower system power consumption
2. Improved noise immunity
3. Wider supply voltage range.
4-29
Other TTL Families
Considerations:
1. SN54HC/SN74HC high-level input voltage is not TIL-compatible. In a mixed family system (TIL output
driving HC input) it will be necessary to use SN54HCT/SN74HCT, pull-up resistors, or level shifters.
2. SN54HC/SN74HC has less drive capability than some TIL functions.
3. TIL open-collector outputs have higher breakdowns than SN54HC/SN74HC open-drain equivalent functions.
4. Some of the TTL families offer greater operating speed, e.g., STTL, AS, and ALS.
HCMOS advantages:
1. Lower system power consumption
2. Improved noise immunity
3. Wider supply voltage range.
4000 Series and 74COO Series
Considerations:
1. Although most applications use a 5-V supply, these older families operate in the 3-V to l5-V range.
2. SN54HC/SN74HC must be operated with a supply voltage in the 2-V to 6-V range.
HCMOS advantages:
I. Higher frequency of operation
2. Improved ESD protection and latch-up performance
3. Higher output drive capability.
4OHOO Series
Considerations:
1. Although most applications use a 5-V supply, this family will operate in the 2-V to 8-V range.
2. SN54HC/SN74HC must be operated with a supply voltage in the 2-V to 6-V range.
HCMOS advantages:
1.
2.
3.
4.
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Higher frequency of operation
Improved ESD protection and latch-up performance
Higher output drive capability
Multiple-sourced family.
As a quick reference guide, Table 4 shows highlights of interchanging other logic families with high-speed CMOS.
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CONCLUSION
Within the constraints given above, the SN54HC/SN74HC family can be regarded as pin-for-pin equivalents to the other
logic families. The rapidly-expanding SN54HC/SN74HC family is ideally suited for system upgrading, system shrinking,
or especially, new system design.
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4-30
Table 4. Inghlights of Interchangeability
TTL FAMILY (TTL. LSTTL. STTL. ALS. AS)
HCMOS offers lower system power consumption
Power
Speed
METAL-GATE CMOS
Power consumption of HCMOS is less than metal-gate
than any of the TTL families.
CMOS.
HCMOS operating speed is comparable to LSTTL.
HCMOS operating speed is much faster than metal-gate
Some TTL families (STTL. AS, and ALS) offer
CMOS.
greater operating speed.
Input
The VIHmin of HCMOS is not compatible with the
HCMOS input voltage levels are compatible with metal-gate
Voltage
VOHmin of TTL. In a mixed family system, it is
CMOS outputs only when the power supply voltage for the
necessary to use
'Her
devices, pull-up resistors, or
metal-gate CMOS devices is between 2 V and 6 V.
level shifters.
Output
The output voltages of HCMOS are TTL-compatible.
HCMOS output voltage levels are compatible with metal-gate
CMOS inputs only when the power supply voltage for the
Voltage
metal-gate CMOS devices is between 2 V and 6 V.
Drive
The output current capability of HCMOS is not as
Capability
large as the TTL family.
Fan-out
HCMOS has a smaller fan-out to LS devices than
(LS devices)
the TTL family.
Supply
HCMOS has a wide operating supply voltage range
Voltage
12 V to 6 V).
HCMOS has a higher current drive capability.
HCMOS has a higher fan-out to LS devices.
Operating supply range of metal-gate is larger than HCMOS
Ifrom 3 V to 15 V).
ESD and
TTL family devices are not as vulnerable to ESD and
HCMOS has an improved protection circuitry against ESD
Latch-Up
latch-up damage.
and latch-up.
Guidelines for Handling Electrostatic-Discharge Sensitive (ESDS)
Devices and Assemblies
SCOPE
This specification establishes the requirements for methods and materials used to protect electronic parts, devices, and
assemblies (items) susceptible to damage or degradation from electrostatic discharge (ESD). The electrostatic charges referred
to in this specification are generated and stored on surfaces of ordinary plastics, most common textile garments, ungrounded
people's bodies, and many other commonly unnoticed static generators. The passage of these charges through an electrostaticsensitive part may result in catastrophic failure or performance degradation of the part.
The part types for which these requirements are applicable include, but are not limited to, those listed:
I)
2)
3)
4)
All metal-oxide semiconductor (MOS) devices, e.g., CMOS, PMOS, etc.
Junction field-effect transistors (JFET)
Bipolar digital and linear circuits
Op Amps, monolithic microcircuits with MOS compensating networks, on-board MOS capacitors, or other MOS
elements
5) Hybrid microcircuits and assemblies containing any of the types of devices listed
6) Printed circuit boards and any other type of assembly containing static-sensitive devices.
Definitions
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1. Antistatic material: ESD protective material having a surface resistivity between 109 and 10 14 O/square.
2. Static dissipative material: ESD protective material having surface resistivity between 105 and 109 O/square.
3. Conductive material: ESD protective material having a surface resistivity of lOS O/square maximum.
4-31
4. Electrostatic discharge (ESD): A transfer of electrostatic charge between bodies at different electrostatic potentials
caused by direct contact or induced by an electrostatic field.
5. Surface resistivity: An inverse measure of the conductivity of a material and is the resistance of unit length and
unit width of a surface. Note: Surface resistivity of a material is numerically equal to the surface resistance between
two electrodes forming opposite sides of a square. The size of the square is immaterial. Surface resistivity applies
to both surface and volume conductive materials and has the dimension of Il/square.
6. Volume resistivity: Also referred to as bulk resistivity. !tis normally determined by measuring the resistance
(R) of a square of material (surface resistivity) and multiplying this value by the thickness (T).
7. Ionizer: A blower that generates positive and negative ions, either by electrostatic means or by means of a radioactive
energy source, in an airstream, and distributes a layer of low velocity ionized air over a work area to neutralize
static charges.
8. Close proximity: For the purpose of this specification, is 6 inches or less.
Device Sensitivity per Test Circuit of Method 3015, MIL-STD-883
Devices are categorized according to their susceptibility to damage resulting from electrostatic discharge (ESD), and
the type packaging required to adequately protect them.
1) Device electrostatic sensitivity: (Effective Notice 8 of MIL-STD-883)
MIL-M-38510
ESD CLASS DESIGNATION
1
2
3
MARKING
ESD VOLTAGE RANGE
MINIMUM PROTECTIVE PACKAGING
1 TRIANGLE
0-1999 V
Antistatic Magazine and Conductive Bag or Box
2 TRIANGLES
2000-3999 V
;,,4000 V
NO TRIANGLE
Antistatic Magazine and Antistatic Bag
Same
2) Devices are to be categorized by their sensitivity
3) Devices are to be protected from ESD damage from receipt at incoming inspection through assembly, test and
shipment of completed equipment.
APPLICABLE REFERENCE DOCUMENTS
The following reference documents (of latest issue) can provide additional information on ESD controls.
1)
2)
3)
4)
5)
6)
7)
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MIL-M-3851O Microcircuits, General Specification
MIL-STD-883 Test Methods and Procedures for Microelectronics
MIL-S-I9491 Semiconductor Devices, Packaging of
MIL-M-55565 Microcircuits, Packaging of
DOD-HDBK-263 Electrostatic Discharge Control Handbook for Protection
DOD-STD-1686 Electrostatic Discharge Control Program
NAVSEA SE 003-11-TRN-OIO Electrostatic Discharge Training Manual
(1)
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FACILITms FOR STATIC-FREE WORK STATION
The minimum acceptable static-free work station shall consist of the work surface covered with an ESD protective materiill
attached to ground through a I Mil ± 10 % resistor, an attached grounding wrist strap with integral 1 Mil ± 10% resistor
for each operator, and air ionizer(s) of sufficient capacity for each operator. The wrist strap shall be connected to the ESD
protective material. Ground shall utilize the standard building earth ground, refer to Figure 42. Conductive floor tile along
with conductive shoes may be used in lieu of the conductive wrist straps. The Site Safety Engineer must review and approve
all electrical connections at the static-free work station prior to its implementation.
Air ionizers shall be positioned so that the devices at the static-free work stations are within a 4-foot arc measured by
a vertical line from the face of the ionizer and 45 degrees on each side of this line.
General grounding requiremenlS are to be in accordance with Table 5.
4-32
ESD PROTECTIVE
TRAYS. ETC.
PERSONNEL
GROUND STRAP
j
R
'VVV'
ESD PROTECTIVE
TABLE TOP
OTHER
~ ELEC.
EQUIP.
IONIZER
R
CHAIR
WITH GROUND
(OPTIONAL)
WORK BENCH
=
All electrical equipment sitting on the conductive table top must be hard grounded but must be isolated from the conductive
table top.
NOTE: Earth ground is not computer ground or RF ground or any other limited type ground.
Figure 42. Static-Free Work Station
Table S. General Grounding Requirements
Handling Equipment/Handtools
TREATED WITH ANTISTATIC SOLUTION
GROUNDED TO
OR MADE OF CONDUCTIVE MATERIAL
COMMON POINT
X
Metal Parts of Fixtures
X
and Tools/Storage Racks
Handling Trays/Tubes
X
Soldering Irons/Bath
Table Tops/Floor Mats
X
Personnel
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X
X
X Using Wrist Strap *
"With 1 MO ± 10% resistor
Usage of Antistatic Solution in Areas to Control tbe Generation of Static Charges
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The use of antistatic chemicals (antistats) should be a supplemental part of an overall organized ESD program. Any antistatic
chemical application shall be considered as a means to reduce or eliminate static charge generation on nonconductive materials
in the manufacturing or storage areas.
The application of any antistatic chemical in a clean room of class 10,000 or less shall not be permitted. Accordingly,
any user of antistatic solutions must consider the following precautions:
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1. Do not apply antistatic spray or solutions in any form to energized electrical parts, assemblies, panels, or equipment.
2. Do not perform antistatl'c chemical applications in any area when bare chips, raw parts, packages, and/or personnel
are exposed to spray mists and evaporation vapors.
4-33
The need for initial application and frequency of reapplication can only be established through routine electrostatic voltage
measurements using an electrostatic voltmeter. The following durability schedule is a reasonable expectation.
I} Soft surfaces (carpet, fabric seats, foam padding, etc.): each 6 months or after cleaning, by spraying.
2} Hard abused surfaces (floors, table tops, tools, etc.): each week (or day for heavy use) and after cleaning, by
wiping or mopping.
3} Hard unabused surfaces (cabinets, walls, fixtures, etc.): each 6 months or annually and after cleaning, by wiping
or spraying.
4} Company-furnished and maintained clothing and smocks: after each cleaning, by spraying or adding antistatic
concentrate to final rinse water when cleaned.
The use of antistatic chemicals, their application, and compliance with all appropriate specifications, precautions, and
requirements shall be the responsibility of the Area Supervisor where antistatic chemicals are used.
ESD Labels and Signs in Work Areas
ESD caution signs at work stations and labels on static-sensitive parts and containers shall be consistent in color, symbols,
class, and voltage sensitivity identification, and appropriate instructions. Signs shall be posted at all work stations performing
any handling operations with static-sensitive items. These signs shall contain the following information.
CAUTION
STATIC CAN DAMAGE COMPONENTS
Do not handle ESDS items unless grounding wrist strap is properly
worn and grounded. Do not let clothing or plain plastic materials
contact or come in close proximity to ESDS items.
II
Labels shall be affixed to all containers containing static-sensitive items at a place readily visible and proper for the intended
purpose. Additionally, labels must be consistently placed on containers and packages at a standard location to eliminate
mishandling. Use only QC accepted and approved signs and labels to identify static-sensitive products and work areas. The
use of ESD signs and labels, and their information content shall be the responsibility of the Area Supervisor to assure consistency
and compatibility throughout the static-sensitive routing.
Relative Humidity Control
.
Since relative humidity has a significant impact on the generation of static electricity, when possible, the work area should
be maintained within the following relative humidity ranges: incoming/assembly/test/storage 50%-65 % (ref. Ashrae, 55-74),
within ± 5 % to avoid static voltage monitor variations.
PREPARATION FOR WORKING AT STATIC-FREE WORK STATION
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A work station with a conductive work surface connected to ground through a I Mil ± 10% resistor, a grounding wrist
strap with the ground wire connected to the conductive work surface, and an ionizer constitute a static-free work station
(Figure 42). An operator is properly grounded when the wrist strap is in snug (no slack) contact with the bare skin, usually
positioned on the left wrist for a right-handed operator. The wrist strap must be worn the entire time an operator is at a
static-free work station. The operator should first touch the grounded bench top before handling static-sensitive items. This
precaution should be observed in addition to wearing the grouding wrist strap. If possible, operators should avoid touching
leads or contacts even though grounded .
:::s
CAUTION
Personnel shall never be attached to ground without the presence
of the I Mil ± 10% series resistor in the ground wire.
4-34
An operator's clothing should never make contact or come in close proximity with static sensitive items. They must
be especially careful to prevent any static-sensitive items (being handled) from touching their clothing. Long sleeves must
be rolled up or covered with antistatic sleeve protector banded to the bare wrist which shall "cage" the sleeve at least as
far up as the elbow. Only antistatic finger cots may be used when handling static-sensitive items.
Any person not properly prepared, while at or near the work station, shall not touch or come in close proximity with
any static-sensitive items. It is the responsibility of the operator and the Area Supervisor to ensure that the static-free work
area is clear of unnecessary static haiards, including such personal items as plastic coated cups or wrappers, plastic cosmetic
bottles or boxes, combs, tissue boxes, cigarette packages, and vinyl or plastic purses. All work-related items, including
information sheets, fluid containers, tools, and parts carriers must be those approved for use at the static-free work station.
GENERAL HANDLING PROCEDURES AND REQUIREMENTS
1. All static-sensitive items must be received in an antistatic/conductive container and must not be removed from
the container except at static-free work station. All protective folders or envelopes holding documentation (lot
travelers, etc.) shall be made of nonstatic-generating material.
2. Each packing (outermost) container and package (internal or intermediate) shall have a bright yellow warning
label attached, stating the following information or equivalent:
CAUTION
ELECTROSTATIC
SENSITIVE
DEVICES
DO NOT OPEN DR HANDLE
EXCEPT AT A
STATIC·FREE WORKSTATION
The warning label shall be legible and easily readable to normal vision at a distance of 3 feet.
3. Static-sensitive items are to remain in their protective containers except when actually in work at the static-free
station.
4. Before removing the items from their protective container, the operator should place the container on the conductive
grounded bench top and make sure the wrist strap fits snugly around the wrist and is properly plugged into
the ground receptacle, then touch hands to the conductive bench top.
5. All operations on the items should be performed with the items in contact with the grounded bench top as much
as possible. Do not allow conductive magazine to touch hard grounded test gear on bench top.
6. Ordinary plastic solder-suckers and other plastic assembly aids shall not be used.
7. In cases where it is impossible or impractical to ground the operator with a wrist strap, a conductive shoe strap
may be used along with conductive tile/mats.
8. When the operator moves from any other place to the static-free station, the start-up procedure shall be the
same as in PREPARATION FOR WORKING AT STATIC-FREE WORK STATION.
9. The ionizer shall be in operation prior to presenting any static-sensitive items to the static-free station, and shall
be in operation during the entire time period the items are at the station.
10. "Plastic snow" polystyrene foam, "peanuts," or other high-dielectric materials shall never come in contact
with or be used around electrostatic sensitive items, unless they have been treated with an antistat (as evidenced
by pink color and generation of less than ± 100 volts).
11. Static-sensitive items shall not be transported or stored in trays, tote boxes, vials, or similar containers made
of untreated plastic material unless items are protectively packaged in conductive material.
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PACKAGING REQUIREMENTS
Packaging of static-sensitive items is to be in accordance with Device Sensitivity, item 1). The use of tape and plain
plastic bags is prohibited. All outer and inner containers are to be marked as outlined in GENERAL HANDLING
PROCEDURES AND REQUIREMENTS, item 2, and conductive magazines/boxes may be used in lieu of conductive bags.
4-35
SPECIFIC HANDLING PROCEDURES FOR STATIC-SENSITIVE ITEMS
Stockroom Operations
1. Containers of static-sensitive items are not to be accepted into stock unless adequately identified as containing
static-sensitive items.
2. Items may be removed from the protective container (magazine/bag, etc.) for the purpose of subdividing for
order issue only by a properly grounded operator at an approved static-free station as defined in FACILITIES
FOR and PREPARATION FOR WORKING AT STATIC-FREE WORK STATION.
3. All subdivided lots must be carefully repackaged in protective containers (magazine/bag, etc.) prior to removal
from the static-free work station and labeled to indicate that the package(s) contain static-sensitive items. If it
is suspected that a static-sensitive item is not adequately protected, do not transfer it to another container, return
it to the originator for disposition unless the originator is a Customer. In that case, the QC Engineer should
contact the Customer and negotiate an appropriate disposition.
4. It is the responsibility of the Stockroom Supervisor to ensure that all personnel assigned to this operation are
familiar with handling procedures as outlined in this specification. A copy of this specification is to be posted
in the vicinity so that it is accessible to the operators. Stock handlers and all others who might have occasion
to move stock are to be instructed to avoid direct contact with unprotected static-sensitive items.
Module and Subassembly Operations
1. Static-sensitive items are not to be received from a stockroom, kitting, or machine insertion area unless received
in approved static-protective packaging, and properly labeled to indicate that its contents are static sensitive.
2. All single station, progressive line manual assembly operators, and visual inspectors prior to wave soldering
operations are to be properly grounded with a grounding wrist strap when handling static-sensitive items.
3. Progressive lines used as single stations where operators will be working on a mix of boards, both static-sensitive
and nonstatic-sensitive, will require that all operators working on the line be properly grounded. This is necessary
to accommodate the sliding of static-sensitive boards along the assembly bench or across positions not engaged
in the assembly of this type board.
4. It is the responsibility of the Area Supervisor to ensure that all personnel handling static-sensitive items are
familiar with this procedure and fully aware of the damage or degradation of these units in the event of
noncompliance. A periodic inspection should be made using an electrostatic voltmeter to assure that the staticfree stations are in proper working order and to ensure that operators are wearing grounding wrist straps properly
(snugly in contact with bare skin).
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Soldering and Lead-Forming Operations
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4-36
8.
All soldering machines, conveyors, cleaning machines, and equipment shall be electrically grounded to ensure
that they are at the same ground potential as the grounded operators working on their stations. No machine
surfaces exposed to static-sensitive items are to be above the ground potential.
Allprocessing equipment shall be grounded, including all loading and unloading stations, that is, the stations
before and after each piece of processing equipment.
All nonmetallic, static-generating components in the handling systems shall be treated to ensure protection from
static .
All stations shall be identified by posting signs as outlined in ESD Labels and Signs in Work Areas.
Operators are to be properly grounded with a grounding wrist strap during any handling, loading, unloading,
inspection, rework, or proximity to static-sensitive items.
Unloading operators working at a grounded station shall place static-sensitive items into approved static-protective
bags or containers.
All manual soldering, repair, and touch-up work stations on the solder line are to be static protected. Operators
are to wear grounding wrist straps when working on static-sensitive items. Only grounded-tip soldering/desoldering
irons are allowed when working on static-sensitive items.
It is the responsibility of the Area Spervisor to ensure that all personnel handling static-sensitive items are familiar
with this procedure and fully aware of the damage or degradation of these units in the event of noncompliance.
A periodic inspection should be made using an electrostatic voltmeter to assure that the static-free stations are
in proper working order and to ensure that operators are wearing grounding wrist straps properly (comfortably
snug in contact with bare skin).
Electrical Testing Operations
1.
2.
3.
4.
5.
6.
7.
8.
9.
All electrical test stations shall be static protected. Operators shall be properly grounded when working on these
items.
Reused antistatic magazines must be monitored for maintenance of antistatic characteristics.
Devices should be in an antistatic/conductive environment except at the moment when actually under test.
Devices should not be inserted into or removed from circuits or tester with the power on or with signals applied
to inputs to prevent transient voltages from causing permanent damage.
All unused input leads should be biased if possible.
Device or module repairs must be performed at static-free stations with the operator attached to a grounding
wrist strap. Grounded-tip soldering irons shall be used when working on static-sensitive items.
Static-sensitive items shall be handled through all electrical inspections in static protective containers. Removal
of the items from the protective containers shall be done at a static-free work station as discussed in
PREPARATION FOR WORKING AT A STATIC-FREE WORK STATION. The units must be returned
to the containers before leaving the station.
All such items shall be shipped with an ESD warning label affixed as listed.
It is the responsibility of the Area Supervisor to ensure that all personnel handling static-sensitive items are
familiar with this procedure and fully aware of the damage or possible degradation of these units in the event
of noncompliance. A periodic inspection should be made using an electrostatic voltmeter to assure that the static-free
stations are in proper working order and to ensure that operators are wearing grounding straps properly (snugly
in contact with bare skin).
Packing Operations
1.
2.
3.
Static-sensitive items are not to be accepted into the packing area unless they are contained in a static-protected
bag or conductive container.
A static-sensitive item delivered to the packer within an approved container or bag and found to be in order
regarding identification shall be packed in the standard shipping carton or other regular packaging material.
Containers are to be labeled in accordance with GENERAL HANDLING PROCEDURES AND
REQUIREMENTS, item 2.
Any void-fillers shall be made of an approved antistatic material.
Bum-In Operations
1.
2.
3.
4.
Bum-in board loading and unloading of static-sensitive items shall be done at a static-free station.
Shorting clips/shorted connectors shall be installed on the board plug-in tab prior to loading any units into the
board sockets. The clip/connector shall be taken off just prior to plugging the board into the oven connector.
The clip/connector shall be installed immediately upon removal of the board from the oven connector.
Installation and removal of the clip/connector shall be done by a properly grounded operator.
All automatic or semiautomatic loading and unloading equipment shall be properly electrically grounded.
It is the responsibility of the Area Supervisor to ensure that all personnel handling static-sensitive items are
familiar with this procedure and fully aware of the damage or possible degradation of these units in the event
of noncompliance. A periodic inspection should be made using an electrostatic voltmeter to assure that the static-free
stations are in proper working order and to ensure that operators are wearing grounding straps properly (snugly
in contact with bare skin).
CUSTOMER RETURNED ITEM HANDLING PROCEDURE
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Receipt of ESDS-labeled items is to be done at a static-free work station and handled in accordance with applicable sections
within this guideline.
QUALITY CONTROL PROVISIONS
Sampling
Each manufacturing, stockroom, and testing operation handling ESDS devices will be audited a minimum of once each
quarter for compliance with all terms of this specification by the responsible process control or QRA organization. Ground
continuity and the presence of uncontrolled static voltages are considered critical and shall be checked more frequently as
specified below.
4-37
Ground Continuity (minimum of once a week).
Ground connections (grounding wrist strap, ground wires on cords, etc.) shall be checked for electrical continuity. The
presence of a 1 MO ± 10% resistor in the ground connections between both the operator wrist straps to the work surface
and the work surface to ground connector must be verified.
Grounded Conditions (minimum of once a week).
A visual inspection shall be made to determine full compliance with this specification at static-free work stations during
handling of static-sensitive items, including operator being grounded as required, static-sensitive items not being handled
in unprotected or unauthorized areas, and no static-generating materials at the grounded work station.
Sleeve Protectors (minimum of once a week).
A visual check shall be made to determine that each operator wearing loose-fitting or long-sleeved clothing either has
sleeves properly rolled or covered with sleeve protectors properly grounded to the bare skin at the wrist.
Static Voltage Levels (minimum of once a week).
In addition to the visual inspections, a sample inspection using an electrostatic voltmeter will be used to check for
uncontrolled electrostatic voltages at or near electrostatic-controlled work stations.
Conductive Floor Tiles (minimum of once a month).
Conductive floors must have a resistance of not less than 25 kO from any point on the tile to earth ground. Also, resistance
from any point-to-point on the tile floor 3 feet apart shall be not less than 25 kO. The test methods to be used are
ASTM-F-150-72 and NFPA 56.
Records
Written records must be kept of all these QC audits.
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TRAINING
Training is applicable for all areas where individuals come in contact with ESDS (category A) devices. It is the responsibility
of each Area Supervisor to make sure that his/her people receive ESD training initially and every 12 months thereafter to
maintain proficiency. Training should include static fundamentals, a review of applicable parts of this specification, and actual
applications in the work area.
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4-38
Uses and Limitations
of the SN54/74HCT
CMOS Logic Family
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INSTRUMENTS
4-39
IMPORTANT NOTICE
Texas Instruments (Til reserves the right to make changes in the
devices or the device specifications identified in this publication
without notice. TI advises its customers to obtain the latest version
of device specifications to verify, before placing orders, that the
informat'ion being relied upon by the customer is current.
TI warrants performance of its semiconductor products, including SNJ
and SMJ devices, to current specifications in accordance with TI's
standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems such testing necessary to support this
warranty. Unless mandated by government requirements, specific
testing of all parameters of each device is not necessarily performed.
In the absence of written agreement to the contrary, TI assumes no
liability for TI applications assistance, customer's product design, or
infringement of patents or copyrights of third parties by or arising from
use of semiconductor devices described herein. Nor does TI warrant
or represent that any license, either express or implied, is granted
under any patent right, copyright, or other intellectual property right
of TI covering or relating to any combination, machine, or process in
which such semiconductor devices might be or are used.
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Copyright © 1985, Texas Instruments Incorporated
INTRODUCTION
To aid in interfacing TTL system signals to High-speed
CMOS (HCMOS) systems, Texas Instruments has
included in its HCMOS family a subfamily of 'HCT
devices. While functionally identical to their 'HC
counterparts, the input voltage thresholds of the 'HCT
subfamily are designed to recognize TTL-level voltages.
The output voltages of the 'HCT devices are identical to
those of the 'HC devices, i.e., rail-to-rail.
TTL to HCMOS Interface
There is an incompatibility between TTL output
voltages and the HCMOS input voltages, specifically the
VOH of TTL and VIH of HCMOS. To overcome this
incompatibility there are at least three methods to
interface TTL signals to HCMOS. The first method is to
use the HCMOS subfamily 'HCT. The second method
involves using a pull-up resistor to pull-up the VOH of the
TTL gate to a voltage that is greater than the VIH of the
HCMOS device. The final method is to use a voltage level
shifter.
Using the 'HCT devices is by far the easiest. The
'HCT devices were designed specifically for this type of
application. Use of 'HCT devices enables the system
designer to reduce the number of discrete components (no
pull-up resistors), and receive the benefits of HCMOS.
Using pull-up resistors to interface the TTL signals
to HCMOS requires the system designer to calculate the
range of acceptable values for the pull-up resistor. The
lower limit is determined by the current sinking capability
of the driving gate.
Rp min ".
VCC - VOL max
IOL + nIIL
Where n is the number of gates in the fanout.
Determining the upper limit of the pull-up resistor is
not as simple. The upper limit must satisfy two constraints.
The first is limited by the input current of the driven gate.
Since the driven gate is HCMOS the input current will be
extremely small (on the order of a nanoamp).
VCC - VIH min
nIIH
Rp max =
Where n is the number of gates in the fanout
In this equation, IOH of the driving gate has been
omitted because all the current is being supplied through
the pull-up resistor. For the second constraint, Rp max is
derived through the following equation:
Where
t is the maximum rise time requirement of 500 ns
C is the input capacitance of 3 pF typ., 10 pF max
Rearranging the equation:
Solving for
Rp:
-t
Rp
=
Cln(l-VIHlVecJ
Therefore R max';:; Vee - VIH
p
nIIL
and
Rpmax,;:;
-t
C In(l- VIHlVecJ
The upper limit to the pull-up resistor will be most
influenced by the rise time requirement of the input signal.
The larger the resistor, the longer the rise time of the input
signal. This will adversely affect the propagation delay of
the input signal. By reducing the value of the pull-up
resistor, the rise time of the input signal will benefit, but
the current through the pull-up resistor will be increased.
This will have an adverse effect on the system power
consumption.
The last method uses a voltage level shifter to make
the TTL signals HCMOS compatible. This method has a
major drawback, in that the level shifter performs no logic
function. Therefore additional logic will have to be added
to the system, increasing the board area.
From a designer's point of view, using 'HCT devices "';::;
to interface TTL signal to HCMOS is by far the easiest CO
and most efficient method. 'HCT devices provide the
voltage-level shifting and the logic function in a single o
chip. In addition, there is no need to compromise between c:
the input signal rise time and the pull-up resistor current.
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'HCT Operating Voltages
The 'HCT devices have a limited Vee operating
range due to the fact that these devices must be able to
recognize TTL-level voltages. Although the 'HCT devices
will operate from 2 V to 6 V (same as 'HC devices), there
are two major disadvantages in addition to the fact that
there are no guaranteed specifications for operation
outside the 4.5 V to 5.5 V Vee range. First, the noise
margins, especially the low-voltage noise margin, will
become smaller and smaller as t.he Vee is decreased.
Second, the input voltage thresholds will no longer remain
TTL-level compatible, which is the primary function of
'HCT.
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'HCT Noise Immunity
Noise immunity is an important criterion in system
designs. Noise immunity. has two components: highvoltage noise margin and low-voltage noise margin. Highvoltage noise margin is the voltage difference between the
guaranteed VOH of the driving gate and the guaranteed V
IH of the driven gate. Low-voltage noise margin is the
voltage difference between the guaranteed VIL of the
driven gate and the guaranteed VOL of the driving gate.
These two components of noise immunity are illustrated in
Figure 1.
It is desirable to have both noise margins as large as
possible, and the area in between (the uncertain region) as
small as possible. If the noise margins are not large
enough for a particular application. noise from any
internal or external source will cause the input/output
signal to fall into the uncertain region and possibly cause a
bit error to enter the system. Three possible sources of
internal noise are inductive and resistive drops, capacitive
coupling from another logic node, and mutual inductance
with anotitel logic node. External noise sources are mainly
radio signals.
Figure 2 illustrates the guaranteed noise margins of
'HC, 'HCT and 'LS devices. As can be seen, 'HC devices
have high- and low-voltage noise margins of 29% and 19%
of Vcc respectively. A coinparision of these noise margins
to those of 'LS devices, shows that 'HC devices have more
than twice the guaranteed noise margins than 'LS devices.
The 'HCT devices seem to have a larger noise margins
than the 'HC devices. However, this is slightly deceiving.
The only configuration to achieve the large high-voltage
noise margin is to have the input of the 'HCT device be
.....
6
Vo ORIVING OEVICE
VI DRIVEN DEVICE
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Figure 1. Noise Margins
driven from either another 'HCT device or an 'HC device.
Although this may be advantageous for noise margins, the
'HCT device is in the wrong application. The 'HCT
devices are designed to interface from TTL-level signals to
HCMOS-Ievel signals. Using the 'HCT device in its
appropriate application, i.e., an 'HCT device driven by an
LSTTL device, the noise margins will be identical to those
of 'LS. The 'HC noise margins allow a greater magnitude
of noise within the system without causing errors. This is
very beneficial for applications in high noise
environments. Figure 3 illustrates the noise margins of
'HC and 'HCT with respect to the devices' actual switching
threshold voltages. The switching threshold voltage is the
voltage to which the input transistors "compare" the
voltage on the input pin. If the input voltage is greater
than the threshold voltage, then the input transistors
recognize this input as a logic 1. If the input voltage is less
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HCT
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VNH(LS) = 0.14 VCC
VIH •= 2 V -2
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VIL =0.8V
VNL(LS) = 0.08 VCC :
VOL=0.4V
VCC = 5 V ±10%
_
POWER SUPPLY VOLTAGE
Figure 2. Guaranteed Noise Margins for
'He and 'LS Devices
4-42
HC
6 . . . . - - - - - - - - - - - - - -..... vOH = VCC -0.1 V
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VOH=VCC-O.1 V
1
VNH .. 0.7 VCC
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_ _ _ _ _ _ VTH(HCTI = 1.5 V
1.5
1
VNL .. 0.33 Vee
•
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~
VOL=0.1V
VOL=0.1V
_ _ POWER SUPPLY VOLTAGE
Figure 3. 1Ypical Noise Margins Based on Threshold
Voltages for 'RC and 'RCT Devices
than the threshold voltage, the input transistors recognize
the input as a logic O. This figure again presents slightly
deceiving 'HCT noise margins for the same reasons as
previously explained. Note that while both 'HC and 'HCT
noise margins have been enlarged, the 'HC noise margins
approach the ideal situation, 50% of Vee. 'HCT, on the
other hand, although exhibiting a larger high-voltage noise
margin than 'HC, has a smaller low-voltage noise margin.
In an 'HC system, both the high- and low-voltage noise
margins are almost 50% of Vee, and consequently, in an
actual system environment, there is very little possibility
for noise to introduce a bit error into the system.
For the best overall noise margins in a system, a
combination of 'HCT and 'HC devices are used. The
'HCT devices are used to interface the TTL-level signals
to the HCMOS. The 'HC devices are for the other parts of
the system not involved with TTL-level input signals.
'RCT Power Consumption
To enable the 'HCT devices to recognize the TTL
logic levels, the input transistor pair geometries were
altered. In an 'HC device, the width of the gate of the
input P-channel transistor is approximately twice the width
of the gate of the N-channel transistor. For 'HCT devices,
this configuration has been changed so that the N-channel
transistor gate is approximately seven times wider than the
P-channel transistor gate. This is illustrated in Figure 4. It
should be noted that the gate width is the parameter that
changes, not the gate length, which remains 3 fLm in both
the 'HC and 'HCT devices. The end result achieved with
this new input structure configuration is the capability of
turning on the N-channel transistor at a lower input
voltage.
To achieve the above results, however, trade-offs are
required. A major advantage of the HCMOS structure is
its low-power consumption. Because of the larger Nchannel transistor in the input structure of 'HCT device,
more supply current is drawn by these devices. This is due
to the N-channel transistor not completely turning off
when a TTL-level voltage is applied to the input, an effect
especially apparent when a TTL VOL level is applied. To
aid the system designer in using 'HCT devices, Texas
Instruments includes in the dc tables of the 1984 HighSpeed CMOS data book for 'HCT devices a parameter,
boIce, which is the additional supply current drawn by the
device when one input is at the specified TTL-level voltage
rather than at 0 V or Vee. Typical and maximum values
are specified.
Figure 5 illustrates this increase in supply current by
comparing ICC for a 'HCT243 with TTL-voltage levels on
one input versus TTL-voltage levels on four inputs. For
this test, each output is loaded with a 50-pF capacitor and
the input signal was a 0.5-V to 2.4-V peak-to-peak square
wave with a 50% duty cycle. Figure 6 shows the supply
current drawn by an 'HCT243 in the same circuit but with
a O-V to 5-V square wave with a 50% duty cycle. When the
input to an 'HCT device is rail-to-rail, the 'HCT device
draws no more current than is drawn by an 'HC device
under the same conditions. Figure 7 shows a comparison
of supply current drawn by an 'HCT device when
subjected to TTL-voltage level inputs versus rail-to-rail
inputs, with all four inputs being switched simultaneously.
At frequencies above 5 MHz, the additional supply
current is relatively insignificant (approximately 2 rnA),
but at lower operating frequencies the difference in the
total supply current as a percentage becomes much more
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VCC
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a. SCHEMATIC OF INPUT TRANSISTOR PAIR
P CHANNEL
N CHANNEL
HCT243 POWER CONSUMPTION
0.5 - 2.4 V Square Wave 50% Duty Cycle
32
28
8
4
O~~~~~~~~~~
0.1
0.5
1.0
5.0
10.0
15.0
20.0
Input Frequency (MHz)
Figure 5. 'HCT243 Power Consumption with TTL Le\'el
Voltages on the Inputs
HCT243 POWE R CONSUMPTION
o-
5.0 V Square Wave 50% Duty Cycle
30r-------------------------------,
b. HC GATE: P-CHANNEL GATE WIOTH
2 TIMES N-CHANNEL GATE
•
TA=25"C
VCC=5V
0.5
1.0
5.0
10.0
15.0
20.0
Input Frequency (MHz)
Figure 6. 'HCT243 Power Consumption with
"Rail-to-Rail" Voltages on the Inputs
c. HCT GATE: N-CHANNEL GATE WIDTH
7 TIMES P-CHANNEL GATE
Figure 4. Comparison of 'HC and 'HCT Input Gates
significant. Because of this, the use of 'HCT devices may
not seem to be a particularly desirable solution for
interfacing TTL-level voltages to HCMOS. The TTL-level
inputs in Figure 7 were the guaranteed VOH and VOL.
These guaranteed voltages are for a specified current
being sin ked or sourced by the TTL device. In fact,
because 'HC and 'HCT devices are voltage level sensitive
(Le., they require no input current), the VOH of the
driving TTL gate, when driving HCMOS, will be much
higher than the guaranteed voltage. Typically, the VOH of
an 'LS gate will be approximately one VBE plus a
VCE(sat) below Vee, and the VOL of an 'LS gate will be
approximately one VeE(sat) above ground. Due to this,
4-44
the additional Iec drawn by the 'HCT gate will not be as
significant.
By comparison, an alternative method for
interfacing TTL signals to 'HC is the use of pull-up
resistors (See Note I), but here again trade-offs will have
to be made. Using larger value pull-up resistors decreases
the amount of additional supply current drawn, but
degrades the rise time of the input signal to the 'HC gate,
limiting the use of this method in high-speed systems.
Decreasing the value of the pull-up resistor will shorten
the rise time, but will cause the supply current to increase.
The best overall solution is the use of 'HCT devices, which
reduces also the number of discrete components required
in the circuit.
Note 1: A complete description on how to interface TIL systems to
HCMOS systems, and vice versa, is given in the Texas Instruments
High-Speed Silicon-Gate CMOS data book.
Overall, the 'HCT devices provide a simple and
efficient means for a system designer to interface TTLlevel voltages to HCMOS systems, and gain many of the
advantages of HCMOS.
HCT243 POWER CONSUMPTION
HC Level Inputs Vs TTL Le..1 Inputs
32
TA = 25·
VCC=5V
28
24
~ 20
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16
12:
8
4
0
VIL-IIL and VIH-IIH characteristic of the driven gate as
illustrated in Figure 8. For switching from a logic I to a
logic 0, the next step is to draw a line from the VOH point
(Point to in Figure 9) on the Va axis toward the output
characteristic of the driving gate. The slope of the line is
- liZ, where Z is the impedance of the transmission line.
At the intersection of the - liZ line and the output
characteristic (Point t I in Figure 9), a new line is drawn
toward the Va axis. The slope of this line is + liZ. the
second Va axis intersection (Point t2 in Figure 9) or the
intersection with the input characteristic, is the voltage seen
by the driven gate. If this voltage is less than the switching
threshold voltage, then incident wave switching will be
achieved. If the second Va axis intersection is not less than
the switching threshold voltage then reflected wave switching
will occur.
IOH (mAl
0.1
0.'5
1.0
5.0
10.0
Input Frequency (MHzl
15.0
20.0
Figure 7. 'RCT243 Power Consumption Comparison of
TTL Level Inputs to "Rail-to-Rail" Inputs
Propagation delays
One other drawback to the use of 'HCT is the added
propagation delay. Although there are no additional
stages in an 'HCT device, compared to an 'HC device, the
relatively small p-channel device has more difficulty
charging and discharging the capacitance associated with
the relatively large n-channel device. This results in an
increase in propagation delay of approximately 1 to 2 ns
for each 'HCT input.
'RCT Bergeron Analysis
Within a logic system, It IS important to know
whether or not a signal sent from one subsystem will cause
incident wave or reflected wave switching on the input of
the receiving subsystem. The incident wave or reflected
wave switching issue is important because the transition
times of the outputs are as fast or faster than the
propagation times within the system's buses, causing the
system buses to have characteristics similar to those of
transmission lines. This in conjunction with impedance
discontinuities, will cause signal reflections on the system's
buses. These signal reflections may produce additional
propagation delays, ringing, and overshoot.
Due to the fact that digital logic devices do not have
linear input and output characteristics, the basic
transmission line equations are not easily applied. What is
needed is a simple method that will produce reasonably
accurate results. Using Bergeron diagrams, the digital
logic interconnections can be analyzed through a simple
graphics technique.
To illustrate the graphical technique, we are using an
example of an 'ALSOO driving an 'HCT245 through a 30-0
transmission line. The first step is to plot the VOL-IOL
and VOH-IOH characteristics of the driving gate and the
~----+-----1-----~--~-+-'VO
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Figure 8. Output Characteristics of Driving Gate
('ALSOO)
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For switching from logic 0 to . logic 1 the same
procedure previously described is followed except the
VOH-IOH characteristic of the driving gate and the
VIH-IIH characteristic of the driven gate are used
(see Figure 10). The initial -liZ line is drawn from the
VOL point (Point to in Figure 10) on the Va axis toward
the output characteristic (Point t1 on Figure 10). The same
criterion for incident wave switching is used; the second
Vo axis intersection (Point 12 on Figure 10) must be
greater than the switching threshold voltage.
In the preceding example, the switching threshold
voltage was used as the criterion for incident versus
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4
3
......--=.-"'T"""---,.-----r---.--........r-"'T""". Va
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to
Using the same analysis method, it can be seen (see
Figure 11) that an 'HCT device driving another 'HCT
device will have difficulty achieving incident wave
switching on low-impedance transmission line (see the
load lines for the 30-D line for a logic 1 to logic
transition). Because 'HC and 'HCT have the same output
characteristics, and because 'HC has its thresholds at a
higher voltage, the 'HC device can achieve incident wave
switching on the low-impedance line.
In order to maintain the ability to drive lowimpedance transmission lines throughout the system,
'HCT devices should be used only at the TTL interface,
and 'HC devices should be used elsewhere.
°
-20
-40
-60
IOL (rnA)
Figure 9. Bergeron Diagram for Switching from a
Logic 1 to a Logic 0 Using an 'ALSOO
Driving an 'HCT Device
VOIIO Characteristic of He and HCT
80
60
IOH (rnA)
40
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60
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40
0
-40
-60
20
0
2
4
Va (Volts)
~--L-~-~-~-L~L--4L-.VO
(V)
Figure 10. Bergeron Diagram for Switching from a
Logic 0 to a Logic 1 Using an ' ALSOO
Driving an 'HCT Device
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reflected wave switching. The switching threshold voltage
is where the device decides if the voltage on the input is
low enough for a logic 0, or high enough for a logic 1. For
'HCT devices this voltage will be around 1.5 V, and for
'HC devices the threshold voltage will be around one half
of Vee. To be guaranteed that the receiving gate will
switch, the load lines must intersect the Vo axis at a
voltage less than the guaranteed V IL or greater than the
guaranteed VIH.
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4-46
Figure 11. Bergeron Diagram of 'HC/'HCT
Driving 'HCI'HCT Device
Summary
The major application of 'HCT is to provide the
interface between TTL signals and HCMOS. Due to the
fact that the input transistor pair geometries were altered
to provide TTL compatibility, there were some inherent
drawbacks. For this reason 'HCT should be used only at
the TTL interface, and elsewhere 'HC should be used.
This will result in optimum system performance.
As the HCMOS technology progresses, more and
more systems will be designed in Silicon-Gate CMOS,
especially with more LSI functions being offered (e.g.,
memories and microprocessors). Consequently the trend
is expected towards .CMOS levels on the interconnecting
buses. Once this occurs, the need for 'HCT functions will
diminish rapidly.
SN74HC Input/Output
Voltage Specifications
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TEXAS
INSTRUMENTS
4-47
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes in the
devices or the device specifications identified in this publication
without notice. TI advises its customers to obtain the latest version
of device specifications to verify, before placing orders, that the
information being relied upon by the customer is current.
TI warrants performance of its semiconductor products, including SNJ
and SMJ devices, to current specifications in accordance with TI's
standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems such testing necessary to support this
warranty. Unless mandated by government requirements, specific
testing of all parameters of each device is not necessarily performed.
In the absence of written agreement to the contrary, TI assumes no
liability for TI applications assistance, customer's product design, or
infringement of patents or copyrights of third pa rties by or arising from
use of semiconductor devices described herein. Nor does TI warrant
or represent that any license, either express or implied, is granted
under any patent right, copyright, or other intellectual property right
of TI covering or relating to any combination, machine, or process in
which such semiconductor devices might be or are used .
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4-48
Copyright © 1985, Texas Instruments Incorporated
INTRODUCTION
There is considerable confusion over the maximum input and
output voltage specifications for the '74HC devices. Basically
there are two questions: what exactly do the specifications
mean; and why do different manufacturers have different
specifications? This report answers these questions by
considering the input and output structures of '74HC devices.
INPUT STRUCTURES
The maximum input and output voltages and currents
that can be applied to a '74HC device are primarily
determined by the ESD structures. Figure I illustrates the
input structure used on Texas Instruments SN74HC family,
'NPUTP'N~f
5~-3.;~~Am
Figure 1. TI's ESD Input Protection Circuitry
and Figure 2 illustrates the structure commonly used by other
manufacturers of the '74HC product line. It is beyond the
scope of this report to discuss the relative merits of each
structure from an ESD protection standpoint. Therefore, how
the specifications are affected by each structure is discussed.
TVCC
I
INPUTPIN~
POLY RESISTOR
TOGATES
Figure 2. Other MllUufacturers' ESD Input
Protection Circuitry
From Figure I it can be seen that in the Texas
Instruments' input structure, a voltage in excess of Vee will
be clamped to a VBE above Vee by the protection diode.
A voltage below ground will be similarly clamped to a VSE
below ground, this time by the base·emitter junction of the
distributed n-p-n transistor. Therefore, when the input voltage
is taken outside the Vee or ground rails, the characteristics
of a forward-biased diode can be seen. Thus, it is meaningless
to specify a maximum input voltage (either positive or
negative). It is the current through the forward-biased diode
which is the limiting parameter. If this current becomes too
large, there is the possibility of damage to the device either
from blowing the bond wire or excessively heating the diode
(or transistor).
The JEDEC committee does indeed recommend a
maximum input voltage of Vee + 0.5 V (in the positive
direction) and -0.5 V (in the negative direction). This
parameter can best be regarded as an indication that the
protection devices are present rather than a "traditional"
maximum voltage specification. For this reason Texas
Instruments does not include this parameter on the data sheet.
The key parameter included on the Texas Instruments
data sheet is the input diode current, and this diode current
corresponds to the JEDEC recommended limit. The
parameter, 11K, has a maximum value of ±20 rnA, which
is the maximum current that can be allowed to flow
continuously through the input protection structures. The
peak value of this current has a much higher value and is
usually limited by the degree of latch-up protection existing
on the input.
The structure shown in Figure 2 is different from the
Texas Instruments protection circuitry. In this configuration
a polysilicon resistor is located in series with the protection
diodes. The affect of this resistor on the input voltage
parameters is to limit the current flowing through the
protection diodes. The existence of this diode is the reason
why some manufacturers have chosen to specify the
maximum input voltage as Vee + 1.5 V (positive) and
- 1.5 V (negative). Since the input voltage corresponds to
the VBE of the protection diode plus the IR drop across the
resistor, this maximum input voltage specification ensures
the current flowing through the input structure is limited to
the JEDEC 20 mA value.
OUTPUT STRUCTURES
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The output structure is illustrated in Figure 3. In this
case it is the same for all manufacturers. Since two of the
diodes are parasitic in the output transistors, no alternative
is possible. The same considerations discussed earlier for
the inputs are true for the outputs. Therefore, the output
voltage will also be clamped to a VBE above the supply and
below the ground rails. A specification similar to the input
diode current exists for the output diode current (10K). The
maximum value is also ± 20 mA, corresponding to the
JEDEC recommendation. JEDEC also has a recommended
maximum output voltage specification of Vee + 0.5 V or
-0.5 V. The manufacturers use these same limits when
output voltages are specified. As with the maximum input
voltage specification, this parameter has limited usefulness.
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4-49
Vcc---------1~~----__,
01
03
...~. .__4~_t_- OUTPUT PIN
02
Figure 3. ESD Output Protection Circuitry
DI AND D2 ARE PARASITIC DIODES
whenever possible as the advantage of the 74HC fantily:s
high input impedance will be lost.
.
Under certain transient load conditions, particularly
when driving high capacitances or unterminated transmission
lines, undershoot or overshoot can Occur. The output
impedance of the SN74HC family is approximately 50 {} for
standard outputs, and approximately 25 {} for high current
outputs (Figure 5). This output impedance is symmetrical,
having about the same slope regardless of whether the output
is in a high or a low state. This alone overcomes many of
the transient problems experienced with bipolar circuits, since
the SN74HC family's output impedance tends to damp out
.
any overshoot or undershoot.
50r-----------~--------------_,
APPLICATION CONSIDERATIONS
40
Now that the input and output structures and the
parameters associated with them have been discussed, their
effects in an application will be examined. It is convenient
to consider transient effects and steady-state effects
individually.
In the steady state, if two systems or subsystems are
interconnected, and each has its own power supply, the
protection structures limit the difference between the two
supply voltages. If this difference exceeds a VBE, then
excessive supply current will be drawn from the higher of
the two supplies through the input protection structures of
devices powered from the other supply (Figure 4). If this
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20
Figure 4. Interconnected Structures with
Separate Supplies
current is not limited to a safe value, there is the potential
to damage the devices. However, in almost all applications,
the increase in supply current will be undesirable. It should
be noted in this case that neither of the two input structures
offers an advantage over the other as the output protection
structures limit the difference in supply voltage. This is the
only steady-state effect likely to be of interest in most
applications. The only other possibility is that voltages may
be applied to 74HC inputs from sources external to the
system, and these voltages exceed Vee. In this case,
additional resistors will be required in series with the inputs,
regardless of the input structure used, in order to limit the
input current to a safe value. This situation should be avoided
60
0
-20
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-40
-60
-60
2
3
4
5
Vo
(b) HIGH-CURRENT OUTPUT
Figure 5. SN74HC Output Impedances
(Vee - 5 V, TA - 25°C)
In an HC system, if undershoot or overshoot is present
or exceeds the turn-on voltage of the protection structures,
then an excess current will flow for the same reasons
discussed. However, this time it will only be a transient
current and it is possible to exceed the maximum 11K or 10K
ratings without causing damage to the device (11K and 10K
are continuous ratings). Unfortunately there is no peak
current limit in the existing specifications. However, in
practice the maximum limit is determined by the degree of
latch-up immunity offered by the devices being used. This
is to be expected since transients of this nature are the major
cause of latch-up problems. Therefore the manufacturer's
latch-up specifications should be carefully studied to
determine how much overshoot or undershoot can be
tolerated. A review of the specifications will reveal a
considerable variation between manufacturers. Some do not
even specify any degree of latch-up suppression. For this
reason Texas Instruments developed latch-up suppression
circuitry capable of withstanding in excess of 250 mA at
25°C, or in excess of 100 mA at l25°C.
Referring to the schematics for the input protection
structures (Figures 1 and 2), it will be seen that the version
shown in Figure 2 does offer an advantage in the transient
mode of operation as the poly resistor will inhibit the current
flowing through the diodes. However, the output structures
are again the limiting parameter as the outputs are also
susceptible to the transients and are capable of latching up
under extreme conditions.
In summary, under transient conditions, external current
limiting will not be required for most applications unless
severe overshoot or undershoot is present which would result
in input or output currents comparable to the trigger currents
of the parasitic SCRs inherent in HC devices.
CONCLUSION
As a result of the use of different ESD protection
structures, manufacturers specify different absolute
maximum voltage ratings for the input of HC devices. This
difference is of little importance to the system designer. The
maximum input current is really the key input parameter
which determines whether or not a device will be damaged.
The output ESD protection structures, which are inherent
in the output transistors, set the lower limit on the maximum
voltage that can be withstood on the outputs without forward
biasing these protection structures. Such forward biasing may
result in excessive current drain or, in extreme cases, device
damage:
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4-52
Using High-Speed CMOS and
Advanced CMOS Logic
in Systems with
Multiple VCC Supplies
or Partial Power-Down
Rick Curtis
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TEXAS
INSTRUMENlS
4-53
IMPORTANT NOTICE
Texas Instruments (Til reserves the right to make changes in the
devices or the device specifications identified in this publication
without notice. TI advises its customers to obtain the latest version
of device specifications to verify, before placing orders, that the
information being relied upon by the customer is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
such testing necessary to support this warranty. Unless mandated
by government requirements, specific testing of all parameters of each
device is not necessarily performed.
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In the absence of written agreement to the contrary, TI assumes no
liability for TI applications assistance, customer's product design, or
infringement of patents or copyrights of third parties by or arising from
use of semiconductor devices described herein. Nor does TI warrant
or represent that any license, either express or implied, is granted
under any patent right, copyright, or other intellectual property right
of TI covering or relating to any combination, machine, or process in
which such semiconductor devices might be or are used.
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Copyright
© 1986. Texas Instruments Incorporated
CMOS devices offer a designer many desirable features, the
most important one being a low power consumption.
However, in some systems a designer will find that even the
low power consumption of CMOS is insufficient to meet his
power supply constraints. Therefore, some designers will
utilize partial system power-down or multiple Vee supplies
to meet their system power requirements.
Whenever a system incorporates the lise of multiple
Vee supplies or partial power-down, the designer must take
into account several important device parameters if he is
using High-Speed CMOS (HC) or Advanced CMOS (ACL)
devices. This is necessary to avoid excessive power
dissipation and prevent damage to a device that could lead
to a degradation in the reliability of the device. These
parameters are the continuous input and output diode currents
(IlK and 10K) and the continuous output current (10). 11K
and 10K refer to the continuous current that is flowing
through the input and output electrostatic discharge (ESO)
protection circuits (Figure I shows functionally equivalent
schematics of the ESO structures for HC and ACL devices).
VCC
INPUT
VCC
--+---
•
•
•
--+-- OUTPUT
10 is the continuous current flowing through one of the two
output transistors. Table I shows the absolute maximum
ratings for 11K, 10K, and 10 for both HC and ACL devices,
as listed on device data sheets.
Table 1. Absolute Maximum Values for 10.
11K and 10K
ABSOLUTE MAXIMUM
PARAMETER
10
HIGH-SPEED
CMOS (HC)
± 25 rnA (Standard)
±35 rnA (High-Current)
ADVANCED
CMOS (ACL)
±50 rnA
11K
±20 rnA
±20 rnA
10K
±20 rnA
±20 rnA
To understand how 11K, 10K, and 10 can affect a
system design, consider an example of a partial system
power-down. Figure 2 illustrates a partial power-down
situation where a device powered with Vee = 5 V is driving
a device without power applied. The input voltage to the nonpowered device exceeds Vee by more than the threshold
voltage (0.6 to 0.8 volts), causing the ESO protection
structure to conduct whenever the output of the driver is in
a high state. Therefore, the driving device will power-up the
receiving device and any other device sharing the same Vee
line. If no current limiting is provided, then the maximum
10 of the driving device and the maximum 11K of the
receiving device could be exceeded.
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(a) HC EQUIVALENT ESD STRUCTURE
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--+--
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Figure 2. Example of Partial System Power-Down
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(b) ACL EQUIVALENT ESD STRUCTURE
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Figure 1. Simplified ESD Structures for
HC and ACL Devices
4-55
Several methods are available to protect the driving and
receiving devices during partial system power-down. If the
driving device has three-state outputs, then placing the
outputs in a high-impedance state will provide the best
solution. However, if this is not a viable option, then some
method of current limiting must be provided. Figure 3 shows
several methods that can be used, with current-limiting series
resistors being the simplest. The value of the resistor is
chosen to limit the current into the receiving device to less
than 20 rnA. The major drawback to using a current-limiting
resistor is power dissipation. Another drawback is the effect
that the resistor has on the input transition· time at the
receiving device during normal system operation. If the total
capacitance of the interconnects and receiving devices is high
(i.e., a high-capacitance bus), then a current-limiting resistor
will increase the input transition time. A system designer will
have to ensure that the addition of the resistor will not
increase the input transition time above the maximum input
transition time of the receiving device.
Vee - 5 V
Vee - 0 V
=t>---~....---t>=
(a) RESISTOR CURRENT LIMITING
Vee - 5 V
Vee - 0 V
IIc ~~mOD~~~f?=
Figure 3. Current Limiting for a
Partial System Power-Down
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A second method of current limiting shown in Figure 3
involves the use of a pull-up resistor and a diode. The
advantage of this method is that it allows for the use of a
large resistor, thereby holding power dissipation to a
minimum. The disadvantage of this method is that it requires
the use of additional components and results in a higher value
of VIL at the receiving device .
A second example of how a partial power-down can
cause unwanted operation is the case of two drivers connected
to the same bus with one device powered down, as shown
in Figure 4. In this case, the first bus driver will attempt
to power-up the second bus driver and any other devices
sharing the same Vee line through the output ESD structure
of the unpowered device.
4-56
Vee - 5V
Vee - 5 V
Vee - 0 V
Figure 4. Partial Power-Down with Bus Drivers
Several methods are available to solve this type of
problem. One method is simply to use a current limiting
resistor as outlined above. Another solution is to isolate the
unpowered driver from the Vee line by means of a diode
between the power pin and the Vee supply. If the unpowered
device is a transceiver, then pull-up or pull-down resistors
are required on the output control inputs to disable the
outputs. Not disabling the transceiver outputs would allow
the transceiver to power up the unpowered devices that are
driven by its outputs. Whenever an isolating diode is used,
the Vee at the driver will always be a diode forward drop
below the voltage of the supply, resulting in a degradation
of VOH. Figure 5 illustrates these circuit solutions.
Another example of a system that could require current
limiting protection is one that uses multiple Vee supplies,
or provides each· card with its own on-board voltage
regulator. If the Vee supplies of two connecting devices
differ by more than 0.5 V dc, then a current limiting scheme
should be considered if the driving device is a CMOS device
and is connected to the higher Vee. This is necessary
because VOH of a CMOS device will be the same as Vee
whenever the IoH requirement is very small. Therefore the
input ESD protection diode could conduct if the Vee of the
driver (or VOH) exceeds the Vee of the receiver by more
than 0.5 V dc. It should be pointed out that it is the resulting
current flow that causes the degradation of the diode, not
the voltage. Note: This applies only to supplies that vary
by more than 0.5 V dc. Dynamic switching currents could
cause transient voltage spiking on Vee lines such that a
0.5 V difference between supplies could easily exist. These
transients will not cause a problem as long as their duration
is short (less than 20 ns).
Vee - 5 V
Vee - 5 V
Vee - 0 V
Partial system power-down offers a designer a
convenient method to save on system power consumption.
However, when a partial power-down scheme is used, a
designer must take steps to ensure that no damage occurs
to devices and to avoid excessive power dissipation. He must
also take similar precautions when using multiple Vee
supplies if the supplies of two connecting devices differ by
more than 0.5 V dc.
R
(a) CURRENT LIMITING RESISTOR
Vee - 5 V
Vee - 5 V
Vee - 0 V
(b) DIODE ISOLATION (FOR A TRANSCEIVER,
DISABLE OUTPUTS)
Figure 5. Current Limiting for Bus Drivers
During Partial Power-Down
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4-58
Numerical Index
Functional Index
o Flip-Flop and Latch Signal Conventions
Explanation of Function Tables
Glossary
Parameter Measurement Information
Mechanical Data
Ordering Instructions
Mechanical Data
Tape and Reel Information
IC Sockets
5-1
•
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5-2
ORDERING INSTRUCTIONS
Electrical characteristics presented in this data book, unless otherwise noted, apply for circuit type(s) listed
in the page heading regardless of package. The availability of a circuit function in a particular package
is denoted by an alphabetical reference above the pin-connection diagram(s). These alphabetical references
refer to mechanical outline drawings shown in this section.
Factory orders for circuits described in this catalog should include a four-part type number as explained
in the following example.
EXAMPLE
(1.
Prefix
SN
54HC02
J
-~Ot
) r - - -_________Jf
MUST CONTAIN TWO TO FOUR LETTERS
SN
Standard Prefix
SNJ
MIL·STD-883 Processed and Screened
JANB
MIL-M-3851 0 Processed
per JEDEC Standard 101
2. Unique Circuit Description
MUST CONTAIN SIX TO NINE CHARACTERS
Examples:
54HCOO
74HC74
74HCT620
74HC4002
3. Package
MUST CONTAIN ONE OR TWO LETTERS
J, JT, N, NT IDual-in-line packagss)*
D, DW ("Small Outline" Packages)
FK (Leadlsss Ceramic Chip Carrier)
(From pin-connection diagram on individual data sheet)
4. Instructions (Dash No.)
MUST CONTAIN TWO NUMBERS
-
00 No special instructions
-
10 Solder-dipped leads (N and NT packages only)
tFor tape and reel information refer to page 15 of this section.
t:These circuits in dual-in-line packages are shipped in one of the carriers shown below. Unless a specific method of shipment is specified
by the customer (with possible additional costs), circuits will be shipped in the most practical carrier. Please contact your TI sales
representative for the method that will best suit your particular needs.
C
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Dual-in-line IJ, JT, N, NTI
'2
Slide Magazines
- A-Channel Plastic Tubing
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- Sectioned Cardboard Box
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TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
5-3
•
5-4
MECHANICAL DATA
D plastic "small outline" packages
Each of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulated
within a plastic compound. The compound will withstand soldering temperature with no deformation. and
circuit performance characteristics will remain stable when operated in high-humidity conditions. Leads
require no additional cleaning or processing when used in soldered assembly.
D PlASTIC PACKAGE
(16-pln package used for Illustration)
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6.20 (0.2441
5.80 (0.2281
4.00 (0.1571
3.81 (0.1501
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5.21 (0.2051
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0.356 (0.0141
0.79 (0.0311
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1.12 (0.0441
0,51 (0.0201
PIN SPACING
1.27 (0.0501
ISee Note Al
8
14
16
A MIN
4.80
(0.189)
8.55
(0.337)
9.80
(0.386)
A MAX
5.00
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8.74
(0.344)
10.00
(0.394)
DIM
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ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A.
B.
C.
D.
Leads are within 0,25, (0.01 01 radius of true position at maximum material dimension.
Body dimensions do not include mold flash or protrusion.
Mold flash or protrusion shall not exceed 0.15 (0.006),
Lead tips to be planar within ±0.051 (0.002) exclusive of solder.
II
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TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-5
MECHANICAL DATA
OW plastic "small outline" packages
Each of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulated
within a plastic compound. The compound will withstand soldering temperatl.lre with no deformation, and
circuit performance characteristics will remain stable when operated in high-humidity conditions. Leads
require no additional cleaning or processing when used in soldered assembly.
DW PLA~TlC PACKAGE
(20-pin package used for illustration)
Ir~~
10,6510.419)
10,15 10.400)
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7.45~~~~~~~~~~~~~~
9,0 (0.354)
0,5 (0.021
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0,40 (0.0161
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20
24
28 t
10,16
12,70
(0.400)
(0.500)
15,29
(0.602)
(0.696)
15.49
(0.610)
(0.704)
16
10,36
12,90
(0.408)
(0.508)
17,68
17,88
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
L - - - -_ _ _- - - - - - L - - - - , - - - - - - '
tThe 28-pin
NOTES: A.
B.
C.
D.
package drawing is presently classified as Advance Information.
Leads are within 0,25 (0.010) radius of true position at maximum material dimension.
Body dimensions do not i~clude mold flash or protrusion.
Mold flash or protrusion shall not exceed 0,15 (0.006).
Lead tips to be planar within ±0,051 (0.002) exclusive of solder.
C:;'
!.
C
....m
m
5-6
PII
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MECHANICAL DATA
FK ceramic chip carrier packages
Each of these hermetically sealed chip carrier packages has a three-layer ceramic base with a metal lid
and braze seal. The packages are intended for surface mounting on solder lands on 1,27 (O.050-inch)
centers. terminals require no additional cleaning or processing when used in soldered assembly.
FK package terminal assignments conform to JEDEC Standards 1 and 2.
FK CERAMIC CHIP CARRIER PACKAGES
(28-terminal package shown)
CERAMIC CHIP CARRIERS
JEDEC
OUTLINE
DESIGNA nON'
NO.OF
TERMINALS
MS004CB
20
MS004CC
28
B
A
MIN
MAX
MIN
MAX
8.69
10.342)
9.09
10.358)
7.BO
10.307)
10.31
10.406)
9.09
10.358)
11,23
11,63
10.442)
10.458)
11,63
10.458)
• All dimensions and notes for the specified JEDEC outline apply.
II
~I
J.--+
0.71 (0.028) I
0,56 (0.022)--j
2,03 (0.080)
1.63 (0.064)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-7
MECHANICAL DATA
J ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 7 ,62 (0.300) centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped") leads require no additional
cleaning or processing when used in soldered assembly.
l4·PIN J CERAMIC
-.l
~19,94(0.185)
I
I
19.18 (0.755)
i@@@@@cv®1
"M='""~t::::::
7,87 (0 310)
IL
I
Il-1B
7.11
m
(0;B~rI02901
(0 (2)
6.22 102451
'.27
0.5'10.020IMINl
lO 050) NOM
'~~:
I
CD 0 CD CD ())
5.08
MAX
-SEATING PLANE
I. PLACES
[-II«0.3610.0141
0.20 (0.0081
14 PLACES
to.2ool
--
GLASS
II.
iLj
H
8~~
~
U
3.30 (0.1301
MIN
".7810.070IMAX '4 PLACES
H
~
~ H
H
U
W
H
SEALANT
JII
"'.111- 0.6~41~~~~~~IN
0
100
I
-1L-~
,-
0.3810.0151
"PLACES
2.54 (0.1001
1,78 (0.070)
PIN SPACING 2,54 (0.100) T.P.
4 PLACES
(See Note Al
Falls Within JEDEC TD-ll6 and EIA MO-OOl AA Dimensions
ALL LINEAR D(MENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
II
5-8
TEXAS .."
INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MECHANICAL DATA
J ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 7,62 (0.3001 centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped"lleads require no additional
cleaning or processing when used in soldered assembly.
l6·PIN J CERAMIC
Ii.
Ii.
~
7.8710.3101
7.37 10.2901
~:~~ :~:~::.
t;:d""._, -
l,J1I\~",,",,~.
16 PLACES
\I..- 0.36
10.0141
0.2010.0081
~.
16 PLACES
G(3)00®@0®
1r
~--~--
~
5.o:,;}OOI
•
..
0.61 10.0201'
MIN
3.3~~~1301
Jtli .
1,78 (0.070) MAX 16 PLACES
U
L)' 'I
~AU
II
L
~
.J
[U l
I I I
0,305 (0.0121 MIN
W
-1
4 PLACES
PIN SPAC(I;: ~~~ ~il001 T.P.
GLASS
~
SEALANT
0.69 10.0271 MIN
jL.
12 PLACES
058 10.0231
-III~
f-l
16 PLACES
d7 10.050)
0,38 (0.015) 4 PLACES
• For memories of 64 bits and up. a few MSI/LSI products in Series 54174 and Series 5451745 that are
derived from memory circuit bars. and complex HCMOS parts. this maximum is 7,62 (0.300). AU other
dimensions apply without modification,
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
II
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-9
MECHANICAL DATA
J ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 7,62 (0.300) centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped") leads require no additional
cleaning or processing when used in soldered assembly.
20·PIN J CERAMIC
24.76 (0.975)
..
leo----- 23,62 (0.930)
'i.
'i.
~
1
~:~~ :~:~~~:
7,62 10.300}
6,2210.245}
-----1·..1
.m"'>""~{~~~~~~~~J
CD000®®0®®®
1,78 (0.070) MAX 20 PLACES
1,27 (0.050) NOM
II'r:;;t~;:;;:;~~;;;~~~
~_S~t;~~G -:-3-:-,30,- (~t.-'-I30=)t'----'-
GLASS
SEALANT
MAX
105'
"90'
MIN
20 PLACES
- ._ _ _ _ __
\I 0,36 10.014}
..-\\00-0,2010.008)
•
0,58 (0.023)
0,38 (0.015)
I
20 PLACES
20 PLACES
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
II
C
I»
~
I»
5-10
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MECHANICAL DATA
JT024 ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 7,62 (0.300) centers. Once the pins are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-diped") pins require no additional
cleaning or processing when used in soldered assembly.
24-PtN JT CERAMIC
1 0 - - - - 3 2 , 5 1 n.280~ MAX
----oj
GLASS
SEALANT
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
II
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-11
MECHANICAL DATA
N plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
l4·PIN N PLASTIC
'i~'i(;:?:~~:I
(0.250
~
:t.
0.010)
---I
2,0 (0.080) NOM
I
--L
[?\
----r,:0.25 (0.Q101
•
NOM
' .
-SEATING PLANE
~
1-".78 (0 0701 MAX 14 PLACES
'0'51(00201~1
508 (0.2001 MAX MIN
_~
,
,
--.J ~ 0.84 (0.0331 MIN
"'l ,.- 14 PLACES
j_
14PLACES ,-\\--0.36(0.0141
~:~~~~
ISee Note. 8 .nd CI
I
:I~ ~~ ~
_11_ 0533(00211
r--O:381 (0:015)
3,17 (0.i25) MIN
2.03' 0.51
(0.080' 0.0201
4 PLACES
ISee '::';.A~~!d CI
PIN SPACING 2.54 (0.1001 T. P.
(See Note Al
Falls Within JEDEC TO-116 and EIA MO-OOl AA Dimensions
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0,25 10.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 10.020) above seating
plane.
II
C
...
I»
I»
5-12
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALlAS. TEXAS 75265
MECHANICAL DATA
N plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
16-PIN N PLASTIC
7,621: 0,25
(0.300:t 0.010)
6,35:t 0,25
(0.2501: 0.010)
2.0 10.0801 NOM
0,84 (0,033) MIN
(See Notes Band C}
(See Notes Band C}
Part! may be supplied in accordance
with the alternate side view at the
option of TI plants located in Europe.
In this case, the oyeralliength of the
package is 22,1 (0.870) max.
ALTERNATE SIDE VIEW
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0,25 (0.0101 of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.0201 above seating
plane.
•
...mm
C
cau
'2
m
.c
u
Q)
:E
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
5-13
MECHANICAL DATA
N plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance. characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
20·PIN N PLASTIC
7,62:!: 0,25
(0.300 t 0.010)
li1
~
2,0 W.oao) NOM
0,25 (O.010) NOM
---1
-SEATING P L A N E - - - 1 c - - -.....
lOS"
90'
2D PLACES
-.\
\--~:;: :~:~~~:
20 PLACES
(See Notes B and C)
J~
L
1,9110.0751
r-- 1,02 (0.040)
4 PLACES
VIEWA
•
s:
Parts may be supplied in accordance
with the alternate side view at the
option of TI. European-manufactured
parts may have pin 1 as shown in
view A. Alternate-side-view parts
manufactured outside of the USA
may have a maximum package length
of 26,7 (1.050).
20 PLACES
(See Note AI
(See Notes B ilnd C\
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES:
CD
(')
::r
II)
A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating
plane.
:::I
(;'
!!.
...c
II)
II)
5-14
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MECHANICAL DATA
NT plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
NOTE: For all except 24-pin packages, the letter N is used by itself since only the 24-pin package is available in more than one row-spacing.
For the 24'pin package, the 7,62 10.300) version is designated NT; the 15,2410.600) version is designated NW. If no second
letter or row-spacing is specified, the package is assumed to have 15,24 (0.600) row-spacing.
24-PIN NT PLASTIC AND
28-PIN t NT PLASTIC
000000000@0@
c
-1
~
_._L20100BOINOM
~025100'OINOM
50~:'01
-1
E
fi1-SEATINGPLANE----c=I-
r
G
t r i - i-m
-w
-m
-m
w
-n
,
-.j
lOS"
9(jC
24 PLACES
\
J\
036100'41
. . . - - 0,25 io.OWI
4,06 (0.160)
24 PLACES
3,17 (0.125)
I
--~- ~
i--114(0045)MIN
I
24 PLACES
~
---IL
053310021)
1 1 - 0,381 (0.015)
24 PLACES
(See NOles Band CI
(See Notes B and Cl
PIN SPACING 2,54 (0.100) T.P.
F
{See Note A)
DIM
DESIGNATION
NT024
NT028 t
A
MIN
MAX
28,6
31,8
11.125)
34,0
(1.338)
B
7,62 ± 0.25
11.250) 10.300 ± 0.010)
37,1
7,88 ± 0,25
(1.462) (0.310 ± 0.010)
C
D
E
MAX
R NOM
MIN
G
F
MIN
MAX
MIN
MAX
7,1
0,71
2,16
1,14
1,78
0.38
2.4
(0.280) 10.093) (0.0151 10.028) (0.08S) 10.045} (0.070)
6,86
1,02
0,51
0,51
2,03
1,02
1,78
10.270) 10.040} (0.020) 10.020) 10.080) 10.040} 10.070)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t The 28-pin package drawing is presently classified as Advance Information.
NOTES:
A. Each pin centerline is located within 0.25 mm (0.010 inch) of its true longitudinal position.
II...
co
CO
S. This dimension does not apply for solder-dipped leads.
C
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating
plane.
ca
(J
'2
CO
.c
(J
Q)
:E
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-15
C
I»
r+
I»
5-16
MECHANICAL DATA
Tape and Reel Information
A new packaging system. SMti'" Tape and Reel. has emerged along
with the Introduction of surface-mount semiconductor packages by
Texas Instruments.
Benefits
SMti Tape and Reel not only offers a new shipping method that protects components
from mechanical and electrical damage, but also includes the benefits of automated
inventory control, ship to stock, and total compatibility with today's automated
placement systems. SMti Tape and Reel continues the trend towards industry
automation and cost reduction and contributes to the overall goal of electronic system
quality and reliability.
Features
The features of SMti Tape and Reel packaging are as follows .
• SMti Tape and Reel packaging is in full compliance with EIA Standard 481-A,
"Taping of Surface-Mount Components for Automatic Placement."
• Industry-compatible tape format allows second sourcing without costly and timeconsuming equipment changeovers and record-keeping changes.
• Static-inhibiting materials, used in carrier tape manufacture, provide device
protection from static damage.
• Rigid, dust-free polystyrene reels provide mechanical protection and clean room
compatibility for optimum equipment operation and manufacturing yield.
• Completely compatible with dereeling equipment currently available on most highspeed automated placement systems.
• Medium-density Code 39 bar coding enables inventory and manufacturing
automation, as well as complete component traceability prior to, during, and after
system manufacture .
• Efficient packaging offers savings in storage space and manufacturing overhead.
II
S!1lK • SURFACE MOUNT
__~ TEXAS INSTRUMENTS
and SMti are trademarks of
Texas Instruments Incorporated.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-17
MECHANICAL DATA
General Description
SMti Tape and Reel offers users of surface-mounted semiconductor
devices a new and efficient method of component handling. Tape and
reel consists of three major elements: a carrier tape. a cover tape. and
a reel.
Carrier Tape
The carrier tape is a conductive material with custom-embossed pockets for a
particular surface-mount package. Components are oriented in the embossed pockets
per EIA 481-A specification "Taping of Surface-Mount Components for Automatic
Placement. "
Cover Tape
With each component in its embossment and protected from mechanical and static
damage, a continuous opaque cover tape is heat sealed over the entire length of the
carrier tape, isolating each component from the outside environment. This heatsealing process guarantees sufficient seal strength to prevent components from falling
from the pockets before use. The cover tape has a peel strength of 40 ± 30 grams in
compliance with EIA 481-A and sufficient strength to ensure consistency during
dereeling operations.
Reel
The entire assemblage is wound on a high-strength polystyrene-based reel. The reel
provides a means of easy storage and handling as well as a method for feeding large
quantities of packages to high-speed placement systems. In addition, SMti Tape and
Reel offers a factory-automation alternative through the use of medium-density
Code 39 bar coding on all reel assemblies. The har code provides source, part
number, date code, and quantity.
•
5-18
TEXAS ~
INSTRUMENTS
POST OfFICE BOX 655012 • DALLAS, TEXAS 75266
MECHANICAL DATA
Bar-Code
Labeling
Each reel of SMti components is labeled with a "man-and-machine" readable label
that uses a medium-density Code 39 bar code in combination with alphanumeric
characters.
Figure 1
Bar-Code Label
1111111111111111111111111111111111111111111111111111111111111111111111111
TI PIN:
111111111111111111111111111111
SN74HCT651 DWR
Q TY:
1111111111111111111111111111111111
1000
O/C:
614XF
Note
I. Sample labels are available for system compatibility testing.
II
...
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C
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CO
.c:
(,)
Q)
:IE
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-19
MECHANICAL DATA
Specification
SMti Tape and Reel components are available in formats that are
compatible with most industry standard component loading and tape
drive equipment. Figures 2 through 5 and Tables 1 through 6
provide information regarding these formats. All dimensions are
given in millimeters.
Figure 2
Tape Format
If-.-
---1----
TRAILER
(NO COMPONENTS)
:;.:--j
COMPONENTS
LEADER
(NO COMPONENTS)
I
I--~:-:-:-+----{
r--, r---, r---,r-
---, r--..., rII
II
I'
.1
II
"
II
II
II
II
II
II
__ ...J L __ .J L
II
II
I I
II
"
'1
II
_J L__ J L __ J
II
"
II
II
L ___ J
I~340------~~~F~O~R~C~O~M~P~O~N~E~N~T~C;O~U~N~T~~~~----50O------~~
400
AS REQUIRED
560
Notes
1. Carrier tape is conductive with a resistivity value of less than I X lOS ohms per
square.
2. Cover tape is sealed over the entire length of the carrier tape.
Figure 3
Component Format (All components are packaged per Note 1.)
DIRECTION
OFFEED •
II
Note
1. Pin I orientation.
C
I»
....
I»
5-20
.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALlAS, TEXAS 75265
MECHANICAL DATA
Specification
(Continued)
Variables are used in Figure 4 and Tables 1 and 2. The definitions
for the variables are as follows: W is tape width, P is pocket phch,
Ao is pocket width, 8 0 is pocket length, Ko is pocket depth, K is
maximum tape depth, and F is the distance between the drive hole
and the centerline of the pocket. All dimensions are given in
millimeters.
Figure 4
Single-Sprocket Tape Oimensions
4.0::tO.10
r--
1.75 ::to.1
r
t
'~
r)
'!'
EMBOSSMENT
....
....
'!'
'I'
~
... 0.1
1.5-0.0
DIAMETER
J+
f
0.05
....
...
't'
't
...
I_~,
'I'
I"
II:
!
n
CARRIER TAPE
t-- 2.00 •
.I.
",
L
I-
p --
'!'
'I'
I--
1)
1
i
i
III
I'
MIN
F
f
,'," (
II)
gl
~A,
_
DIRECTION
OF FEED
'"--+
..
-
1,5MIN
DIAMETER
Notes
I. Tape widths are 12, 16, and 24 mm.
2. Camber per EIA Standard 481-A.
3. Minimum bending radius per EIA Standard 481-A.
II
...
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TEXAS
..tf
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-21
MECHANICAL DATA
Specification
Table 1
(Continlled)
Single-Sprocket Variable Tape Dimensions
Package
Type
Package
Designator
W
P
Ao
Bo
Ko
K
F
SO-14
D
16
8
6.5
9.5
2.1
2.5
7.5
SO-16
D
16
8
6.5
10.3
2.1
2.5
7.5
SO-16L
DW
16
12
10.9
10.7
3.0
3.4
7.5
SO-20L
DW
24
12
10.9
13.2
3.0
3.4
11.5
SO-24L
DW
24
12
10.9
15.8
3.0
3.4
11.5
±0.3
±0.1
±0.1
±0.1
±0.1
max
±0.1
Tolerance
Dimension
•
s::
CD
(')
::r
m
:::s
5"
e!.
c
m
r+
m
5-22
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MECHANICAL DATA
Specification
(Continued)
Variables are used in Figure 5 and Table 3. The definitions for the
variables are as follows: G is the distance between the flanges. T is
the maximum reel width. and N is the diameter of the reel hub. All
dimensions are given in millimeters.
Figure 5
Reel Dimensions
TMAX
330 +0.0
-4.0
13.0~0.2
1.5 MIN WIDTH
Table 2
TI BAR·CODE LABEL
Variable Reel Dimensions
Package
Type
Package
Designator
Dimension
T
G
N
80-14
D
16.4
22.4
100
80-16
D
16.4
22.4
100
80-16L
DW
16.4
22.4
100
80-20L
DW
24.4
30.4
100
80-24L
DW
24.4
30.4
100
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
II
5-23
MECHANICAL DATA
Specification
(Continued)
All dimensions are given in millimeters.
Taps and Reel Format Summary
Table 3
Tape Package Pocket Dimensions
Package Package
Type
Designator Width Pitch
Width Length
Reel
Reel Hub Parts
Depth Diameter Diameter Per Reel
SO-14
D
16
8
6.5
9.0
2.1
330
100
2500
SO-16
D
16
8
6.5
10.3
2.1
330
100
2500
SO-16L
DW
16
12
10.9
10.7
3.0
330
100
1000
SO-20L
DW
24
12
10.9
13.2
3.0
330
100
1000
SO-24L
DW
24
12
10.9
15.8
3.0
330
100
1000
•
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TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
MECHANICAL DATA
Ordering Information
To order tape and reel components, you need to provide information
about part numbers, quantities, shipping, and sample package
applications.
Ordering by
Part Number
When ordering tape and reel components, add the letter R as a suffix to the
part number. An example of the ordering sequence follows.
R
I. Prefix
2. Unique Circuit Designator
3. Package Type
4. Tape and Reel Packaging
Must be designated by the letter R
Formats and
Quantities
All orders for tape and reel packaging must be for whole reels. For example, if a
customer requires 9,900 TL074s in Tape and Reel packaging, he needs to place the
order for a quantity of 10,000 TL074s. The order will be filled and shipped on four
reels containing 2,500 parts per reel.
Note: TI reserves the right to provide a smaller quantity of devices per reel to
preserve date code integrity.
A list of package and tape formats and the quantity of devices per reel is provided in
Table 4.
Shipping
Taped and reeled components are shipped in individual packing boxes measuring
approximately 14" x 14". The depth of each box is tailored to the tape width.
Individual boxes are packed in a larger box whose size depends on the quantity of
components ordered.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
II
5-25
MECHANI.CAL DATA
Ordering Information
(Continued)
All dimensions are given in millimeters.
Table 4
II
5-26
Condensed Tape and Reel Formats
Package
Type
Package
Designator
Tape
Width
Package
Pitch
Reel
Diameter
Parts
Per Reel
SO-14
D
16
8
330
2500
SO-16
D
16
8
330
2500
SO-16L
DW
16
12
330
1000
SO-20L
DW
24
12
330
1000
SO-24L
DW
24
12
330
1000
Sample Package
Applications
Sample components are available for a number of applications, such as standard
mechanical sample packages, "daisy-chained" bars, and K-factor bars. Table 5
provides sample ordering information.
Table 5
Sample Package Applications
Package
Type
Package
Designator
Mechanical
Sample
Daisy Chain
K Factor
SO-14
D
SN72197
SN2ooo54
SN200060
SO-16
D
SN72198
SN2ooo55
SN200061
SO-16L
DW
N/A
N/A
N/A
SO-20L
DW
SN72199
SN200056
SN200062
SO-24L
DW
SN72200
SN200057
SN200063
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLA.S, TEXAS 75265
MECHANICAL DATA
More Information
As a major manufacturer of SMCs, TI is committed to helping you
make the transition to surface-mount as easy and as economical as
possible. Getting started in SMT -switching from older and less
efficient methods of PCB fabrication-means learning some new
manufacturing techniques, and it entails some capital outlay. But in
volume production, it can actually reduce your capital and space
costs by up to 50 percent.
Ship-to-Stock
Eliminates
Incoming
Inspection
As your usage per surface-mount component (SMC) grows, TI can implement its
ship-to stock program for you. With all the necessary quality-control procedures built
into our standard testing process, your SMCs can be shipped directly to you in tape
and reel or in factory-sealed boxes. Benefits to you:
• Incoming inspection, scrap, and rework reduced or eliminated.
• Inventory reduced.
• Quality levels maximized.
Learn by Doing
To help you realize the advantages of surface-mount technology (SMT), Texas
Instruments maintains a surface-mount laboratory. There you can gain hands-on
experience and guidance in building a surface-mount board from start to finish. To
schedule an appointment, contact your TI Field Sales Engineer or call
(800) 232-3200 for the address of the TI Field Sales Office nearest you.
Outside Help
Available
You can also find assistance among the growing number of SMT assembly houses,
consultants, and associations. They can help you reduce the costs of converting to
SMT, while supplying some valuable information on the latest technological advances
and industry standards.
Suppliers of assembly equipment such as pick-and-place machines and soldering and
test equipment can also help you make the transition to SMT board fabrication.
Want to Learn
More?
How to Use Surface Mount Technology is available free of charge from Texas
Instruments. This technical summary includes chapters on the process and the tooling
required to implement it; the wide variety of available SMCs; inspection, testing, and
repair; quality and reliability; and how to mix SMCs with standard DIP packages.
For additional information on the availability of TI's growing line of SMCs, contact
your local TI Field Sales Office or distributor.
If you would like to have your name placed on our mailing list for additional SMT
information as it becomes available from TI, please write Texas Instruments
Incorporated, Dept. SSP05, P.O. Box 809066, Dallas, Texas 75380-9066.
II
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TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
5-27
5-28
IC SOCKETS
INTRODUCTION
Texas Instruments has developed solutions for today's high density packaging needs. The TI facility at Attleboro,
Massachusetts (one of the world's largest suppliers of multimetal systems) provides leading-edge technology
which, combined with reliable, high-volume, off-the-shelf interconnection products, allows TI to quickly meet
volume commercial applications.
During the last decade, TI has produced one of the largest IC socket families. Tl's sockets include every type
and size socket in common use today and are available in a wide choice of contact materials and designs.
Our sockets are designed for:
•
•
•
easy and efficient hand assembly
compatibility with automatic assembly equipment
maximum performance and board density
This section provides information on the following types of IC socket products.
PRODUCTION SOCKETS
Plastic Leaded Chip Carrier
Single-in-Line Packages
Pin-Grid Arrays
Dual In-Line
Dual In-Line 0.070-inch spacing
Quad In-Line
TYPE
PLCC
SIP
PGA
DIP
Shrink Pack
QUIP
BURN-IN/TEST SOCKETS
Plastic Leaded Chip Carrier
Pin Grid Array
Small Outlilne
Dual In-Line
Dual In-Line 0.070-inch spacing
Small Outline
Quad
TYPE
PLCC
PGA
J Lead
DIP
Shrink Pack
Flat Pack
Flat Pack
Specially formulated alloys give the TI contact springs:
•
•
•
Low Contact Resistance
High Contact Strength (to stand up to repetitive insertions and withdrawals)
High normal forces assure gas-tight reliability
A full line of reliable, readily available, low-cost interconnection systems means premium performance at an
economical price.
Additional information on these and other TI products, including pricing and delivery quotations, may be obtained
from your nearest authorized TI Distributor, TI Sales Representative or:
Texas Instruments Incorporated
Connector Systems Department, MS 14-3
Attleboro, Massachusetts 02703
Telephone: (617) 699-5242/5375
TELEX: 92-7708
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TEXAS . "
INSTRUMENTS
34 Forest Street. Attleboro, Massachusetts 02703
5-29
IC SOCKETS
PLASTIC LEADED CHIP CARRIER
PERFORMANCE SPECIFICATIONS
_-,--IDEI/ICE GUIDE
BARRIERS
Mechanical
Recommended PCB thickness range: 0.062 in to 0.092 in
Recommended PCB hole size range: 0.032 in to 0.042 in
Vibration: 15 G max
Shock: 100 G max
Insertion force: 0.59 Ibs per position typ
Withdrawal force: 0.25 Ibs per position typ
Normal force: 200 g min, 450 g typ
Wipe: 0.075 in min
Durability: 5 cycles min
Contact retention: 1.5 Ibs min
UNIQUE, HIGH
NORMAL FORCE
CONTACT
Electrical
Current carrying capacity: 1 A per contact
Insulation resistance: 5000 MO min
Dielectric withstanding voltage: 1000 V ac rms min
Capacitance: 1 pF max
Environmental
Operating temperature:
Operating: - 40°C to 85 °C
Storage: - 40 °C to 95°C
Temperature cycling with humidity: will conform to final EIA
specifications
PART NUMBER SYSTEM
MATERIALS
Body - Ryton R-4 (40% glass) UL 94 v-a rating
Contacts - CDA 510 spring temper
Contact finish _. 90/10 tin/lead (200 I'in - 400 I'in) over
40 I'in copper
Extraction tool available, consult factory
Contact factory for detailed information
1111
CPR
PH
XXX-X-X-O
lcontact surface 1 - tin/lead
plating
Contact spacing 1 . 0.050 in
Number of pos 1044, 052, 068, 0841
Plated thru hole, solder tail
TI socket Series
PLASTIC LEADED CHIP CARRIER CPR SERIES
~
" "
!' "
" !'
" "
" :,
" "
"
; ;
0
~,
24
l'
" "
"
~
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0,.
~,
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~ " :' " "
0 "P ""
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4
0
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0 "
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(68-Pin shown
s:
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Plastic leaded chip carrier
2.54
1
10.1001 TVP
U
u
(-~
1
NOTE: Socket electrical pin·out pattern represents component side
CD
of p.e.B. layout. (TYP. counter clockwise numbering
out system.)
Pos
pin~
44
(")
A
21,43
10.8441
B
C
17,78
10.700)
12,70
10.5001
:::r
D)
52
23,98
10.944)
20,32
10.8001
15,24
10.600)
(;"
68
29,06
11.1441
25,40
(1.0001
20,32
10.800)
84
34,14
11.344)
30,48
11.200)
25,40
11.0001
:::s
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c
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2,54 (0.1001
I--_T:...:V.:..P_ _ c
Dimensions in parentheses; are in inches
D)
5-30
PRDDUCTIDI DATA docomonts contli. i.formalio.
currant 8S of publication dlta. Products conform to
specifications per the terms of Taxas Instruments
:=:~;8{::1~7i =~:~ti:r l!~o:;::::9t::.,:, nat
TEXAS
~
INSTRUMENTS
34 Forest Street· Attleboro. Massachusetts 02703
IC SOCKETS
PLCC BURN·IN/TEST
PRODUCT FEATURES
Can be loaded by top actuated insertion or press-in
insertion, either manually or automatically
High reliability due to high pressure contact point
Open body and high stand-off design provide high efficiency
in heat dissipation
High durability up to 10,000 cycles
Compact design
PERFORMANCE SPECIFICATIONS
Mechanical
Accommodates IC leads per specific IC device
Recommended PCB thickness range: 0.062 in to 0.092 in
Recommended PCB hole size range: 0.032 in to 0.042 in
Durability: 10,000 cycles 10 mQ max contact resistance
change
Insertion force: Zero g
Withdrawal force: Zero g t
PART NUMBER SYSTEM
CPJ
xx
Electrical
Contact rating: 1 A per contact
Contact resistance: 20 mQ max initial
Insulation resistance: 1000 MQ per MIL-STD 202,
Method 302, Condition B
Dielectric withstanding voltage: 500 V ac rms per
MIL-STD 202, Method 301
I
XX
t
X
XXX
L
B
Number
~f contacts
~t:h 0050
Contact finish
33
overall gold plate
Environmental
Thermal shock: 100 cycles, - 25°C to + 150°C
Temperature soak: 150 °C for 48 hours
Operating temperature: - 40°C to + 150°C
MATERIALS
Body Contact
Plating t
nickel
ULTEM glass filled (UL 94 V-OJ
- copper alloy
- overall gold plate 4 I'in over min 70 I'in
plating
Material
AA ~ copper alloy
TI Burn-in PLCC series
18 PIN FOOTPRINT SHOWN
2,54
10.1001
t After IC is unlocked from the socket
tFor additional plating options contact factory
For complete test report contact the factory
~
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PLCC BURN-IN/TEST SOCKETS CPJ SERIES
2.54
(0
(~0501
t.27
5.08 (0 2001
18,08 (0 712r----1
SIZES: 18 PIN
22 PIN
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Dimensions in parentheses are inches
Contact factory for detailed information
PRODUCTION DATA documents contain information
currant as of publication date. Products conform to
specifications par the terms of Texas Instruments
=:~~:~~i~ar::,~1i ~~:~:~ti:f :1~o::~::::9t::.~s not
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TEXAS
INSTRUMENTS
34 Forest Street. Attleboro, Massachusetts 02703
5-31
IC SOCKETS
SINGLE·IN·LlNE PACKAGE SOCKETS
PERFORMANCE SPECIFICATlONSt
LEADLESS
SINGLE-IN-LiNE _~-
PACKAGE
{SIP} MODULES
Mechanical
Vibration: MIL·STD-202
Durability: 30 cycles
Insertion force: Zero g
Withdrawal force: Zero g;
Contact (normal) force: 200 g min
Contact retention force: 2 Ibs per circuit min
HIGH TEMPERATURE
MOLDED BODY
Electrical
Contact rating: 1 A
Contact resistance: 30 mil max initial
Insulation resistance: 1000 Mil at 500 dc
Dielectric strength: 1500 V ac rms
Capacitance: 2 pF max
ZERO INSERTION FORCE,
HIGH NORMAL FORCE CONTACT
tValues may vary due to test sequence and SIP module
configuration
+After module is unlocked from the receptacle
PART NUMBER SYSTEM
TS8X
For a complete test report, please contact factory
xx xx
X
l
-xx - xx
Environmental
(20 mil max contact resistance change after all tests)
Operating and storage temperature: - 40°C to 100°C
Humidity: MIL-STD 202, Method 1060, 10 days
Temperature soak: 85°C for l60 hours
Thermal Shock: 5 cycles, - 40°C to 85°C per
MIL-STD 202, Method 107E
01-C17000/30 ~in gold
02-CA510/30 ~in gold
03 - C 1 7000/200 ~in tin/lead
04 - CA51 0/200 ~in tin/lead
Configuration/row-to-row spacing
01-single row/N/A
03-dual row/0.300 in
04-dual row/0.400 in
05-dual row/0.500 in
A
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Series number denotes
0-0.100 in pitch. vertical mount
1-0.100 in pitch, low· profile (25°1 mount
J
)
"1!4it"..
Size
Contact base material/plating
DUAL ROW VERTICAL
(0.]
product
contacts per row)
For additional plating options contact the factory.
~ r---=
Variations
00 - standard
Housing material
A - PES
Body - PES polyether sulfone, glass filled, UL 94 V-O
Contact - Beryllium copper C 17000; phosphor bronze alloy
CA510
Contact finishes - Post plate min 200 I'in tin/lead over min
50l'in nickel overall
Post plate min 30 I'in hard gold over min 751'in nickel overall
l?lL .
L
(number of
MATERIALS
I-
MOUNTING POST
.-r..-.-. • ~-~~~
-' .1 J
Consult factory for availability of configurations, materials. an.d
sizes.
SINGLE ROW LOW PROFILE
1.10
10.043)
0.15
10.0201
o
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C»
r+
Contact factory for detailed information
PRODUCTION DATA documents co.tain information
current •• of publicetio_ data. Produ... ca_form to
opociflcetio.. per the term. of T.... Instrum.nts
5-32 ::=~r,·i~:I~7.; = t i ; :.:o:."::::t::." _at
Dimensions in parentheses are in inches
TEXAS
~
INSTRUMENTS
34 Forest Street. Attleboro, Massachusetts 02703
IC SOCKETS
HIGH DENSITY PIN GRID ARRAY
PERFORMANCE SPECIFICATIONS
WIDE· TAPERED
ENTRY
Mechanical
Accommodates IC leads 0.015 in to 0.021 in diameter
Recommended PCB thickness range: 0.062 in to 0.092 in
Recommended PCB hole size range: 0.032 in to 0.042 in
Recommended hole grid pattern: 0.100 in ± 0.002 in each
direction
Vibration: 15 G, 10-2000 Hz per MIL-STD 1344A,
Method 2005.1 Test Condition III
Shock: 100 G, sawtooth waveform, 2 shocks each direction
per MIL-STD 202, Method 213, Test Condition I
Durability: 5 cycles, 10 ma max contact resistance change
per MIL-STD 1344, Method 2016
Insertion force: 3.6 oz (102 g) per pin typ using 0.018 in
diameter test pin
Withdrawal force: 0.5 oz (14 g) per pin min using 0.018 in
diameter test pin
Electrical
Contact rating: 1 A per contact
Contact resistance: 20 ma max initial
Insulation resistance: 1000 Ma at 500 V dc per
MIL-STD 1344, Method 3003.1
Dielectric withstanding voltage: 1000 V ac rms
per MIL-STD 1344, Method 3001.1
Capacitance: 1 pF max per MIL-STD 202, Method 305
PRECISION
MACHINED
SLEEVE
PRECISION
SIX-FINGERED
INNER CONTACT
Inner contact - 30 I'in gold over 50 I'in nickel or 100 I'in
tin/lead over 50 I'in nickel
Outer sleeve - 10 I'in gold over 50 I'in nickel or 50 I'in
tin/lead over 50 I'in nickel
PART NUMBER SYSTEM
C
X
G
xx - xxx x
x
~-
:i_nT_L_e_ng_t_h-,_ _ _ _---.
Environmental
WIRE WRAP
Operating temperature: - 65 °C to 125 °C, gold; - 40 °C to
100°C, tin/lead
Corrosive atmosphere: 10 ma max contact resistance
change when exposed to 22 % ammonium sulfide for
4 hours
Gas tight: 10 ma max contact resistance change when
exposed to nitric acid vapor for 1 hour
Temperature soak: 10 ma max contact resistance change
when exposed to 105 °C temperature for 48 hours
MATERIALS
Body - PBT polyester UL 94 V-O
On request, G 10/FR4 or Mylar film
Outer sleeve - Machined Brass (00-B-626)
Inner contact - Beryllium copper (00-C-530) heat treated
Plating: (specified by part number)
I rr...,:-.
PIN GRID ARRAY
B
J
3.6/4.6
(0'4/0
Number of Pins
024 to 324
Array
Overall Grid Size
5x5~05 to 18x18~18
BODY MATERIAL
G-- Glass Filled Epoxy
P - PBT Polyester
9x9
lOx 10
11 x 11
12x12
13x 13
14x 14
15x15
16x 16
17x17
18x18
@@@@@@@@
(0.10{0.12)
~I
2,54
(0.100) TYP NONCUMULATIVE
181L=_W WuuuuWuUU~
~~033
2,67{3,61
Body Style and Orientation
Contact Loading Pattern
Pin
Grid
Insulator Size
@@@@@@@.@@@·@
@@@@@@@@@@@
@@@@@@@@@@@
•
1,3/2,0
(0.05/0.08) TYP
Plating
TI Socket
-:@-:-:@-@:--@-@-0-@-@-0.0-@:-0-@"
@@@@@@@@@@@
@@@@@@@@@@@
@@@@@@@@@@@
tL
A
3-0.510 long
(0.0211 DIA
(0.' 05/0.150)
I
~~
1.3'
(0.053) OIA
A
B
± 0.010
± 0.005 1
(0.9501 24.13
(1.050126.67
(1.150129.21
(1.250131.75
(1.3501 34.29
(1,4501 36,83
(1.5501 39.37
(1.650141,91
(1. 7501 44,45
(1.8501 46.99
(0.8001 20,32
(0.9001 22,86
(1.0001 25,40
(1.100) 27,94
(1.200130,48
(1.300133.02
(1,4001 35.56
(1.500138.10
(1.600) 40.64
(1.700143.18
tNoncumulative
Dimensions in parentheses are inches
Consult factory for detailed information
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PRODUCTION DATA documents contain information
currant as of publication date. Products conform to
spacifications per the terms of TeX8S Instruments
::~~:~~i~at::I~~'; ~!:ti~~ti:f :I~o::~:~:t::'~s not
TEXAS . "
INSTRUMENTS
34 Forest Street. Attleboro, Massachusetts 02703
5-33
IC SOCKETS
SOJ BURN·IN/TEST
PERFORMANCE SPECIFICATIONS
Mechanical
Accommodates IC leads per specific IC device
Recommended PCB thickness range: 0.062 in to 0.092 in
Recommended PCB hole size range: 0.032 in to 0.042 in
Durability: 10,000 cycles, 20 mil max contact resistance
change
Insertion force: 1.3 oz per position max
Withdrawal force: B.B grams per position min
Electrical
Contact rating: 1.0 A per contact
Contact resistance: 20 mil max initial
Insulation resistance: 1000 Mil per MIL-STD 202,
Method 302, Condition B
Dielectric withstanding voltage: 700 V ac rms per
MIL-STD 202, Method 301
Environmental
Thermal shock: 100 cycles, - 25°C to + 1BO °C, 1 hour
Temperature soak: lBO°C for 1000 hours, 80 mil max
change
Operating temperature: - 65°C to + 180°C
PART NUMBER SYSTEM
xx
xx
xxx
CSJT
x
T
Body Material
MATERIALS
Body - PES glass filled UL 94 V-O
Contact - copper alloy
Plating - overall gold plate min 41'in over min 70 I'in nickel
plating
Blank = G.F. PES
A = PPS R4·03
B = G.F. PEl
Body Variation
02 = Standard 1 forward!
backward insertion
03 = Special/orientation pin
04 = Special/high standoff
05 = Special/24-pin
06 = Standard 2 forward
insertion. BECU
Contact Finish
37 =
38 =
57 =
58 =
Overall gold plate 4 "in
Overall gold plate 30 "in
Selective gold plate 4 "in
Selective gold plate 30 "in
Number of Contacts
TI SOJ series
02 VERSION SHOWN
SIZES: 20 pin
26 pin
20·PIN (02 VERSION) FOOTPRINT SHOWN
0,80
1..-10.0321
I
i
I
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!
-$
I
Contact factory for detailed information
PRODUCTION DATA documonts contain information
currant as of publication'data. Products conform to
spacificatioRI per the terms of T811S Instruments
5-34 :::=~i~at::I~~i ~!::i~~i:r :'~D:=::::~:~~ not
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,
1
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2,54
101001
hfj ··j~tif!
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14-1•21
10.0501
TEXAS •
INSTRUMENTS
34 Forest Street. Attleboro, Massachusetts 02703
'
102001
I
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