1989_TI_MOS_Memory_Data_Book 1989 TI MOS Memory Data Book
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"TEXAS
INSTRUMENTS
/VIOS Memory
Commercial and Military Specifications
1989
MOSMemory
Data Book
Commercial and Military
Specifications
•
TEXAS
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to
discontinue any semiconductor product or service identified in this
publication without notice. TI advises its customers to obtain the latest
version of the relevant information to verify, before placing orders,
that the information being relied upon is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. Unless mandated ,by government
requirements, specific testing of all parameters of each device is not
necessarily performed.
TI assumes no liability for TI applications assistance, customer product
design, software performance, or infringement of patents or services
described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or
relating to any combination, machine, or process in which such
semiconductor products or services might be or are used.
Copyright © 1988, Texas Instruments Incorporated
To receive future updates to this book, please fill out the form below
and mail it to:
Texas Instruments Incorporated
Literature Response Center
P.O. Box 809066
Dallas, Texas 75380-9066
- - - - - - - - - - - - -~- - - - - - - - - - - - - - Name
Title
Company
Address and MIS
City <--I----,------,------,------,----,-1--,-I----,-----,I State LLJ ZIP Cod e <--I----,--I-,--,---,----,I - <--I--'-----'-----'----'
Phone
SMY04IMY800R
Ext.
1
1
Expires 12/89
General Information . .
Alternate Source Directories . .
Glossary/Timing Conventions/Data Sheet Structure
Dynamic RAMS.
I.
Dynamic RAM MOdules.
EPROMs/PROMs/EEPROMs
VLSI Memory Management Products
Military Products _
Applications Information
Quality and Reliability
Logic Symbols
Mechanical Data
ESD Guidelines
INTRODUCTION
The 1988 MOS Memory Data Book from Texas Instruments includes complete detailed specifications on
the expanding MOS Memory product line including Dynamic Random-Access Memories (DRAMs), Single-InLine Package DRAM Memory Modules (SIPs), Video Random-Access Memories (VRAMs), First-In First-Out
Pseudo Static Memories (FRAMs), Erasable Programmable Read-Only Memories (EPROMs), and MOS onetime Programmable Read-Only Memories (PROMs). Also included are military specifications for DRAMs,
VRAMs, EPROMs, and Static Random-Access Memories (SRAMs). This is TI's first MOS Memory data book
to include specifications for the VLSI Memory Management products.
The data book is divided into 13 sections. Section 1, General Information, includes the table of contents,
an alphanumeric index for quickly finding device numbers, a part number guide with ordering information,
plus device selection guides, product reference guides, and an IC Line-up chart for a quick overview of the
broad TI MOS Memory product line. Page numbers are included on the product selection guides for easy
access to the detailed specifications. In Section 2, an Alternate Source Directory lists alternate vendor part
numbering examples in addition to alternate sources to TI devices (based on published data). Product
specifications for over 100 devices can be found in Sections 4 through 8.
Recently published technical articles and product applications information can be found in Section 9. For
the first time, a section on Quality and Reliability (Section 10) has been included in the TI MOS Memory data
book. Because all MOS Memory devices are ESD sensitive, handling guidelines are included in Section 13.
The data sheets within each section are in alphanumeric order; Product Preview information is included at
the end of the section. Data sheets listed with a "TMX" prefix and Product Preview disclaimer include target
specifications for products that are currently under development at TI. The inclusion of these specifications
does not imply that these products are or will be in production, or will meet these parameters.
Additional and/or updated information on these products is available from:
Texas Instruments
Customer Response Center
P.O. Box 809066
Dallas, Texas 75380-9066
For ordering information or further assistance, please contact your nearest Texas Instruments Sales Office
or authorized distributor as listed in the back of this book.
General Information
Alternate Source Directories·"
Glossary/Timing Conventions/Data Sheet Structure
Dynamic RAMs . .
Dynamic·RAM·Modules . .
EPROMs/PROMs/EEPROMs . .
VLSI Memory Management. Products . .
Military Products . .
Applications Information . .
Quality and Reliability
Logic Svmbols
Mechanical Data
ESO Guidelines
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CONTENTS
GENERAL INFORMATION
Alphanumeric Index to Data Sheets ............................................ 1-7
Part Number Guides and Ordering Information ..................................... 1-9
DRAM, FRAM, SRAM, VRAM ............................................. 1-9
DRAM Module ........................................................ 1-10
EPROM, PROM, EEPROM ................................................ 1-11
VLSI Memory Management Products ........................................ 1-12
Reference Guides .......................................................... 1-13
DRAM, VRAM, FRAM, SRAM, EPROM, PROM, EEPROM ......................... 1-13
Dynamic RAM Module .................................................. 1-1 5
Selection Guides .......................................................... 1-16
DRAM .............................................................. 1-16
Dynamic RAM Module .................................................. 1-18
EPROM, EEPROM ...................................................... 1-19
PROM .............................................................. 1-22
SRAM (Military Products) ................................................ 1-24
VLSI Memory Management Products ........................................ 1-25
IC Line-up Chart ........................................................... 1-27
ALTERNATE SOURCE DIRECTORIES
Dynamic RAM ............................................................ 2-3
Dynamic RAM Module .................................................. 2-5
EPROM ............................................................. 2-7
GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTURE
Part I - General Concept and Type of Memories ................................. 3-3
Part II - Operating Conditions and Characteristics (Including Letter Symbols) ............ 3-5
Part III - Timing Diagrams Conventions ......................................... 3-11
Part IV - Basic Data Sheet Structure ........................................... 3-11
DYNAMIC RAMs
TMS4256
TMS4257
TMS4461
TMS4464
TMS44C251
TMS44C256
TMS44C257
TMS4C1024
TMS4C1025
TMS4C1027
TMS4C1050
262,144-bit
262,144-bit
262,144-bit
262,144-bit
1,048,576-bit
1,048,576-bit
1,048,576-bit
1,048,576-bit
1,048,576-bit
1,048,576-bit
1,048,576-bit
(256Kx1) Page Mode .......................... 4-3
(256K x 1) Nibble Mode ......................... 4-3
(64K x 4) Multiport Video RAM ................... 4-27
(64K x4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
(256K x 4) Multiport Video RAM .................. 4-79
(256K x 4) Enhanced Page Mode ................. .4-11 9
(256K x 4) Nibble Mode ........................ .4-119
(1 024K x 1) Enhanced Page Mode ................. 4-1 51
(1 024K x 1) Nibble Mode ........................ 4-151
(1 024K x 1) Static Column Decode Mode ........... 4-1 51
(256K x 4) FRAM ............................. 4-189
DYNAMIC RAM MODULES
TM4256EC4
1,048,576-bit
(256K x 4) Page Mode .......................... 5-3
TM4256FC1
1,048,576-bit
(1 024K x 1) Page Mode ......................... 5-9
TM4256FL8
2,097, 152-bit
(256K x 8) Page Mode .......................... 5-15
TM4256GU8
2,097, 152-bit
(256K x 8) Page Mode .......................... 5-15
TM4256EL9
2,359,296-bit
(256K x 9) Page Mode .......................... 5-21
TM4256GU9
2,359,296-bit
(256K x 9) Page Mode .......................... 5-21
TM024HAC4
4,294,304-bit
(1 024K x 4) Enhanced Page Mode ................. 5-27
TM024GAD8
8,388,608-bit
(1 024K x 8) Enhanced Page Mode ................. 5-31
TM024EAD9
9,437, 184-bit
(1 024K x 9) Enhanced Page Mode ................. 5-31
MIMs (Memory Intensive Modules) ............................................. 5-39
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EPROMs/PROMs/EEPROMs
16,384-bit
TMS27C291
TMS27C292
16,384-bit
TMS27PC291
16,384-bit
TMS2732A
32,728-bit
TMS27C32
32,728-bit
32,728-bit
TMS27PC32
TMS2764
65,536-bit
65,536-bit
TMS27C49
65,536-bit
TMS27PC49
TMS27C64
65,536-bit
TMS27PC64
65,536-bit
TMS28C64
65,536-bit
TMS27C128
131,072-bit
131,072-bit
TMS27PC128
262,144-bit
TMS27C256
262,144-bit
TMS27PC256
524,288-bit
TMS27C512
524,288-bit
TMS27PC512
TMS27C010
1,048,576-bit
TMS27C210
1,048,576-bit
TMX27PC010
1,048,576-bit
1,048,576-bit
TMX27PC210
(2K x 8) High-speed CMOS EPROM ................ 6-3
(2K x 8) High-speed CMOS EPROM ................ 6-3
(2K x 8) High-speed CMOS PROM ................. 6-3
(4K x 8) NMOS EPROM ......................... 6-13
(4K x 8) CMOS EPROM .......................... 6-21
(4K x 8) CMOS PROM .......................... 6-21
(8K x 8) NMOS EPROM ......................... 6-35
(8K x 8) High-speed CMOS EPROM ................ 6-43
(8K x 8) High-speed CMOS PROM ................. 6-43
(8K x 8) CMOS EPROM ......................... 6-55
(8K x 8) CMOS PROM .......................... 6-55
(8K x 8) CMOS EEPROM ........................ 6-69
(16K x 8) CMOS EPROM ........................ 6-79
(16K x 8) CMOS PROM ......................... 6-79
(32K x 8) CMOS EPROM ................... '..... 6-91
(32K x 8) CMOS PROM ......................... 6-91
(64K x 8) CMOS EPROM ........................ 6-105
(64K x 8) CMOS PROM ......................... 6-105
(128K x 8) CMOS EPROM ....................... 6-119
(64K x 16) CMOS EPROM ....................... 6-131
(128Kx8) CMOS PROM ........................ 6-143
(64K x 16) CMOS PROM ......................... 6-145
VLSI MEMORY MANAGEMENT PRODUCTS
Asynchronous FIFO Memories
16 x 5 .............................................. 7-3
SN54ALS229A
16 x 5 .............................................. 7-3
SN74ALS229A
16 x 4 .............................................. 7-9
SN54ALS232A
16 x 4 ....................................... ·....... 7-9
SN74ALS232A
16 x 5 .............................................. 7-13
SN54ALS233A
16 x 5 .............................................. 7-13
SN74ALS233A
SN54ALS234
64 x 4 .............................................. 7-19
64 x 4 .............................................. 7-19
SN74ALS234
64 x 5 ............................................ : .7~27
SN54ALS235
SN74ALS235
64 x 5 .............................................. 7-27
64 x 4 .............................................. 7-39
SN54ALS236
64 x 4 .............................................. 7-39
SN74ALS236
SN74ACT7201A
512 x 9 ............................................. 7-47
SN74ACT7202
1024 x 9 ............................................ 7-63
64 x 8 .............................................. 7-77
SN74ALS2232
SN74ALS2233
64 x 9 .............................................. 7-83
32-bit Parallel EDAC Circuits
SN54ALS632B ........................................................ 7-89
SN74ALS632B ........................................................ 7-89
SN54ALS633 ....•.................................................... 7-89
SN74ALS633 ........................... '.............................. 7-89
SN54ALS634B .............. ; ......................................... 7-89
SN74ALS634B ........................................................ 7-89
SN54ALS635 ......................................................... 7-89
SN74ALS635 ......................................................... 7-89
SN54AS632 .......................................................... 7-107
SN74AS632 ..........................................................'7-107
SN54AS634 .......................................................... 7-107
SN74AS634 .......................................................... 7-107
Cache Address Comparators
SN74ACT2151
1K x 12 ............................................. 7-121 . .
SN74ACT2152
2K x 8 .............................................. 7-135
SN74ACT2153
1 K x 12 ............................................. 7-121
SN74ACT2154
2K x 8 .............................................. 7-135
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TACT2150
512 x 8 ............................................. 7-149
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Dynamic Memory Controllers
256K Dynamic RAM Controller ............................. 7-157
SN74ALS2967
SN74ALS2968
256K Dynamic RAM Controller ............................. 7-157
SN74ALS6301
1 Megabit Dynamic RAM Controller ......................... 7-177
SN74ALS6302
1 Megabit Dynamic RAM Controller ......................... 7-177
THCT4502B
256K Dynamic RAM Controller ............................. 7-197
TMS4500A
64K Dynamic RAM Controller .............................. 7-211
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Access Detectors
SN74ALS6310
SN74ALS6311
Static Column and Page Mode ............................. 7-227
Static Column and Page Mode ............................. 7-227
10-bit Bus Drivers
SN74BCT2827A
SN74BCT2828A
SN74BCT29827A
SN74BCT29828A
3-state
3-state
3-state
3-state
Output ......................................... 7-235
Output ......................................... 7-235
Output ......................................... 7-241
Output ......................................... 7-241
MILITARY PRODUCTS
Dynamic RAMs
SMJ4161
SMJ4164
SMJ4416
SMJ4256
SMJ4461
SMJ4464
SMJ44C256
SMJ4C1024
65,536-bit
65,536-bit
65,536-bit
262,144-bit
262,144-bit
262,144-bit
1,048,576-bit
1,048,576-bit
(64K x 1) Multiport Video RAM ............... 8-3
(64K x 1) ................................ 8-29
(16K x4) . ............................... 8-47
(256K x 1) Page Mode ...................... 8-65
(64K x 4) Multiport Video RAM ............... 8-85
(64K x4) . ............................... 8-115
(256K x 4) Enhanced Page Mode .............. 8-133
(1 024K x 1) Enhanced Page Mode ............. 8-135
EPROMs
SMJ27C128
SMJ27C256
SMJ27C512
SMJ27C010
SMJ27C210
131,072-bit
262,144-bit
524,288-bit
1,048,576-bit
1,048,576-bit
(16K x 8) ................................ 8-137
(32Kx8) ................................ 8-145
(64K x8) . ............................... 8-153
(128Kx8) ............................... 8-163
(64K x 16) ............................... 8-165
16,384-bit
16,384-bit
16,384-bit
65,536-bit
65,536-bit
65,536-bit
73,728-bit
262,144-bit
262,144-bit
262,144-bit
294,912-bit
(16Kx1) ................................ 8-167
(4K x 4) ................................. 8-1 77
(2Kx8) ................................. 8-187
(64K x 1) ............................. " .8-197
(16K x4) ................................ 8-207
(8K x 8) ................................. 8-217
(9K x 8) ................................. 8-227
(256K x 1) ............................... 8-237
(64K x 4) ................................ 8-239
(32K x 8) ................................ 8-241
(32K x 9) ................................ 8-243
SRAMs
SMJ61CD16
SMJ64C16
SMJ68CE16
SMJ61CD64
SMJ64C64
SMJ68CE64
SMJ69CE72
SMJ61CD256
SMJ64C256
SMJ68CE256
SMJ69CE288
General Purpose Interface Buffer
SMJ9914A ........................................................... 8-245
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APPLICATIONS INFORMATION
Technical Article
Designing and Manufacturing Surface Mount Assemblies ......................... 9-3
Product Applications
Memory Timing Controller Using 'ALS2967 and 'ALS2968 ....................... 9-9
Memory Timing Controller Using , ALS6301 and 'ALS6302 ....................... 9-22
THCT4502A/MC6S000LS Interface ......................................... 9-42
Cache Memory Systems Using 'ACT21 51 and ' ACT21 52 ........................ 9-49
Why Use an Error Detection and Correction Device ............................. 9-73
Error Detection and Correction Using 'ALS632B, 'ALS633 -' ALS635 ................ 9-S0
High-Speed Coupling Considerations - FIFO Memory Buffers .................... : .9-S7
BiCMOS Memory Drivers Boost Performance .................................. 9-93
BiCMOS Bus Interface ................. : ................................ 9-96
System Solutions for Static Column Decode .................................. 9-101
QUALITY AND RELIABILITY . ..................................................... 10-3
LOGIC SYMBOLS
Explanation of IEEE/IEC Logic Symbols for Memories ................................ 11-3
MECHANICAL DATA
Part I
- MaS Memory Products-Commercial ...................................
Part II - MaS Memory Products--Military ......................................
Part III - VLSI Memory Management Products ...................................
Part IV - IC Sockets .......................................................
12-3
12-19
12-23
12-37
ESD GUIDELINES . ............................................................. 13-3
1-6
ALPHANUMERIC INDEX
------------------------------111
SMJ27C010 ....................... 8-163
SMJ27C128 ....................... 8-137
SMJ27C210 ....................... 8-165
SMJ27C256 ....................... 8-145
SMJ27C512 ....................... 8-153
SMJ4161 .......................... 8-3
SMJ4164 .......................... 8-29
SMJ4256 .......................... 8-65
SMJ4416 .......................... 8-47
SMJ4461 .......................... 8-85
SMJ4464 .......................... 8-11 5
SMJ44C256 ....................... 8-133
SMJ4C1024 ....................... 8-135
SMJ61 CD16 ....................... 8-167
SMJ61 CD256 ...................... 8-237
SMJ61 CD64 ....................... 8-197
SMJ64C16 ........................ 8-177
SMJ64C256 ....................... 8-239
SMJ64C64 . . . . . . . . . . . . . . . . . . . . . . . . 8-207
SMJ68CE16 ........................ 8-187
SMJ68CE256 ....................... 8-241
SMJ68CE64 ........................ 8-217
SMJ69CE288 ....................... 8-243
SMJ69CE72 ........................ 8-227
SMJ9914A ........................ 8-245
SN54ALS229A ...................... 7-3
SN54ALS232A ...................... 7-9
SN54ALS233A ...................... 7-13
SN54ALS234 ....................... 7-19
SN54ALS235 ....................... 7-27
SN54ALS236 ....................... 7-39
SN54ALS632B ...................... 7-89
SN54ALS633 ....................... 7-89
SN54ALS634B ...................... 7-89
SN54ALS635 ....................... 7-89
SN54AS632 ........................ 7-107
SN54AS634 ........................ 7-107
SN74ACT2151 ..................... 7-121
SN74ACT2152 ..................... 7-135
SN74ACT2153 ..................... 7-121
SN74ACT2154 ..................... 7-135
SN74ACT7201A .................... 7-47
SN74ACT7202 ..................... 7-63
SN74ALS2232 ...................... 7-77
SN74ALS2233 ...................... 7-83
SN74ALS229A ...................... 7-3
SN74ALS232A ...................... 7-9
SN74ALS233A ...................... 7-13
SN74ALS234 ....................... 7-19
SN74ALS235 ....................... 7-27
SN74ALS236 ....................... 7-39
SN74ALS2967 ...................... 7-157
SN74ALS2968 .................... :.7-157
SN74ALS6301 ...................... 7-177
SN74ALS6302 ...................... 7-177
SN74ALS6310 ................... ; .. 7-227
SN74ALS6311 ...................... 7-227
SN74ALS632B ...................... 7-89
SN74ALS633 ....................... 7-89
SN74ALS634B ...................... 7-89
SN74ALS635 ....................... 7-89
SN74AS632 ........................ 7-107
SN74AS634 ........................ 7-107
SN74BCT2827A .................... 7-235
SN74BCT2828A .................... 7-235
SN74BCT29827A ................... 7-241
SN74BCT29828A ................... 7-241
TACT2150 ......................... 7-149
THCT4502B ........................ 7-197
TM024EAD9 ....................... 5-31
TM024GAD8 ....................... 5-31
TM024HAC4 ....................... 5-27
TM4256EC4 . . . . . . . . . . . . . . . . . . . . . . . 5-3
TM4256EL9 ........................ 5-21
TM4256FC1 ........................ 5-9
TM4256FL8 ........................ 5-15
TM4256GU8 ....................... 5-15
TM4256GU9 ....................... 5-21
TMS2732A ........................ 6-13
TMS2764 ......................... 6-35
TMS27C010 ....................... 6-119
TMS27C128 ....................... 6-79
TMS27C210 ....................... 6-131
TMS27C256 ....................... 6-91
TMS27C291 ....................... 6-3
TMS27C292 ....................... 6-3
TMS27C32 ........................ 6-21
TMS27C49 ........................ 6-43
TMS27C512 ....................... 6-105
TMS27C64 ........................ 6-55
TMS27PC128 ...................... 6-79
TMS27PC256 ...................... 6-91
TMS27PC291 ...................... 6-3
TMS27PC32 ....................... 6-21
TMS27PC49 ....................... 6-43
TMS27PC512 ...................... 6-105
TMS27PC64 ....................... 6-55
TMS28C64 ........................ 6-69
TMS4256 ......................... 4-3
TMS4257 ......................... 4-3
TMS4461 ......................... 4-27
TMS4464 ......................... 4-59
TMS44C251 ....................... 4-79
TMS44C256 ....................... 4-119
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
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ALPHANUMERIC INDEX
------------------TMS44C257 .......................
TMS4500A ........................
TMS4C1024 .......................
TMS4C1025 ................... ....
4-119
7-211
4-151
4-151
TMS4C1027 .......................
TMS4C1050 .......................
TMX27PC010 ..................... .
TMX27PC210 ......................
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TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-151
4-189
4-143
4-145
ORDERING INFORMATION
------------------DRAM/FRAM/SRAM ORDERING INFORMATION
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Factory orders for DRAM/FRAM/SRAMs described in this book should include an eight-part type number as
explained in the following example:
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1. Prefix: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......1
4
4
C
256
-10
DJ
TMS Commercial MOS
SMJ Military MOS
TMX Pre-production
Commercial MOS
CD
C
CD
CJ
2) Product Family: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
4 DRAM/FRAM
6 SRAM (Military Only)
3) Word Width: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
Blank
Blank
4
8
9
x1
x 1 (256K and 1 Meg DRAMs Only)
x 4 (1 Meg FRAM Only)
x4
x 8 (SRAMs Only)
x 9 (SRAMs Only)
4) Technology: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
Blank
C
CE
CD
NMOS
CMOS
CMOS with Output Enable Control (SRAMs Only)
CMOS with Separate I/O Pins (SRAMs Only)
5) Density: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'
16
16
64
64
61
72
64
256
257
256
16K SRAM
64K DRAM ('4416)
64K DRAM ('4164)
64K SRAM
64K VRAM ('4161)
72K SRAM
256K DRAM ('4464)
256K DRAM ('4256)
256K DRAM ('4257)
256K SRAM
61 256K VRAM ('4461)
288 288K SRAM
256 1 Meg DRAM (,44C256)
257 1 Meg DRAM ('44C257)
1024 1 Meg DRAM ('4C1024)
10251 Meg DRAM ('4C1025)
1027 1 Meg DRAM ('4Cl027)
10501 Meg FRAM (,4Cl050)
251 1 Meg VRAM ('44C251)
6) Speed Designator:
DRAMs
-8 80
-10 100
-12 120
-15 150
-20200
ns
ns
ns
ns
ns
FRAMs
-325 ns
-430 ns
-650 ns
SRAMs
- 2525 ns
-3535 ns
-4545ns
-5555 ns
7) Package: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---'
Commercial (Plastic)
DJ Small Outline J-Iead (SOJ)
FM Leaded Chip Carrier (PLCC)
SO Zig-zag In-line (ZIP)
N Dual In-line (DIP)
Military (Ceramic)
Dual In-line (DIP)
JD
FG,FV Leadless Chip Carrier (CLCC)
HJ
Small Outline J-Iead (SOJ)
8) Temperature Range: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
Commercial
L
OOC to 70°C
Blank OOC to 70°C (1 Meg DRAM Only)
Military
M -55°C to 125°C
S -55°C to 100 0 Ct
tExcept SMJ4164 and SMJ4256, which are - 55°C to 110°C.
TEXAS -II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
1-9
..
ORDERING INFORMATION
DRAM MODULE ORDERING INFORMATION
G)
CD
::J
~
e!.
5'
..d'3
Factory orders for DRAM modules described in this book should include a seven-part type number as explained
in the following example:
TM
1) Prefix:
m
~
ci"
4256
TM TI Module
C
I
2) Memory Device:
::J
F
I
4256 256K DRAM. Page Mode
024 1 Meg DRAM. Enhanced Page Mode
3) Pinout Configuration:
E G
F H
4) Board Dimensions:
C
L
U AD
AC
5) Word Width Output:
6) Speed Designator:
-10100 ns
-12 120 ns
-15 150 ns
7) Temperature Range:
L DoC to 70 D C
1-10
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
-10
ORDERING INFORMATION
EPROM/PROM/EEPROM ORDERING INFORMATION
..
c
o
-.;.
.E
ca.
CO
Factory orders for EPROMs/PROMs described in this book should include a nine-part type number as explained
in the following example:
TMS
27
P
C
512
-10
FM
o
'+.5
4
I
1. Prefix:
TMS Commercial MOS
SMJ Military MOS
TMX Pre-production
Commercial MOS
Q)
c
Q)
C!'
2) Product Family:
27 EPROM/PROM
28 EEPROM
3) Erasability:
P
Non-erasable
Blank Erasable
4) Technology:
C
CMOS
Blank NMOS
5) Density:
291 16K
29216K
32 32K
49 64K
64 64K
128128K
256256K
512512K
0101024K
210 1024K
6) Speed Designator t:
35
45
50
55
100
120
ns
ns
ns
ns
ns
ns
-3, -35
Blank, - 4, - 45
-5, -50
- 5, - 55
-10, -100
-12, -120
150
1 70
200
250
300
450
ns
ns
ns
ns
ns
ns
- 1, - 15, - 150
- 1, - 1 7, - 170
-2, -20, -200
Blank, - 25, - 250
-3, -30, -300
-45
7) Package:
PROMs (Plastic)
N Dual In-line (DIP)
FN Chip Carrier
FM Chip Carrier
NT 300-mil DIP
(TMS27PC49 Only)
EPROMs (Ceramic)
J Cerpak/Cerdip
JT 300-mil Cerdip
(TMS27C49 Only)
EEPROMs
J Ceramic DIP
N Plastic DIP
8) Temperature Range:
Commercial
E -40 DC to 85 DC
L
ODC to 70°C
Military
M - 55°C to 125°C
S -55°C to 100°C
9) 168 Hour Burn-in Option:
4
168 Hour Burn-in
Blank No Burn-in
tPlease check individual data sheets for available speeds.
-I!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
1-11
ORDERING INFORMATION
G)
CD
::::s
CD
..e.
..3
S"
o
VLSI MEMORY MANAGEMENT ORDERING INFORMATION
Factory orders for VLSI Memory Management products described in this book should include a four-part type
number as explained in the following example:
~
SN
---..1
74ACT2152- 25
JD
1) Prefix: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
....m
o·
SN
Standard Prefix
THCT Commercial CMOS
TACT Commercial Advanced CMOS
::::s
2) Circuit Description: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----'
4 to 10 Characters
3) Speed Designator: _-:-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
- xx Speed in ns
4) Package: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-"
D. OW
J. JD
N. NT
FK
FN
1-12
"Small Outline" Packages
Ceramic DIPs
Plastic DIPs
Ceramic Chip Carrier
Plastic Chip Carrier
.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
DRAM. VRAM. FRAM. SRAM. EPROM. PROM. EEPROM
REFERENCE GUIDE
WORDS
1
..
c
BITS PER WORD
9
8
4
o
ca
16
'';:;
(16K)
EPROMs
...oE
PROM
TMS27C291 TMS27PC291
'to-
.5
TMS27C292
2K
ca...
SRAM
G)
SMJ68CE16
(16K)
4K
cG)
(32K)
t!'
SRAM
EPROMs
PROM
SMJ64C16
TMS2732A
TMS27PC32
TMS27C32
(64K)
8K
PROMs
SRAM
SMJ69CE12
TMS2764
TMS27PC64
TMS27C64
TMS27C49
TMS27PC49
SRAM
EEPROM
SMJ68CE64 TMS28C64
(64K)
(128K)
(16K)
16K
(12K)
EPROMs
SRAM
DRAM
SRAM
EPROMs
SMJ61CD16
SMJ4416
SMJ64C64
TMS27C128 TMS27PC128
PROM
SMJ27C128
(256K)
EPROMs
TMS27C256 TMS27PC256
32K
(288K)
SRAM
PROM
SMJ69CE288
SMJ27C256
SRAM
SMJ68CE256
(64K)
(512K)
(256K)
(1024K)
VRAM
DRAMs
VRAMs
EPROMs
SMJ4164
SMJ4161
TMS4464
TMS4461
TMS27C512 TMS27PC512
TMS27C210
SMJ4464
SMJ4461
SMJ27C512
SMJ27C210
64K
SRAM
SMJ61CD64
PROM
EPROMs
DRAM
SRAM
PROM
SMJ64C256
TMX27PC210
Numbers in parentheses indicate overall complexity.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
1-13
..
G)
CD
::2
CD
DRAM, VRAM, FRAM, SRAM, EPROM, PROM, EEPROM
REFERENCE GUIDE
BITS PER WORD
WORDS
4
1
9
8
(1024K)
i-
EPROMs
128K
PROM
TMS27C010 TMX27PC010
S'
SMJ27C010
d'
...
(256K)
...3o·
I»
256K
::2
(1024K)
VRAM
DRAMs
SRAM
DRAMs
TMS4256
SMJ61CD256
TMS44C256 TMS44C251
SMJ4256
TMS4257
SMJ44C256
TMS44C257
FRAM
TMS4C1050
(1024K)
DRAMs
1024K
TMS4C1024
SMJ4C1024
TMS4C1025
TMS4C1027
Numbers in parentheses indicate overall complexity.
1-14
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
16
DYNAMIC RAM MODULE
REFERENCE GUIDE
WORDS
BITS PER WORD
1
4
5
1024K
(2048K)
TM4256EC4
TM4256EL9
TM4256GU8
TM4256GU9
(8192K)
TM024HAC4
TM024GAD8
"+i
(2304K)
TM4256FL8
(4096K)
(1024K)
TM4256FCl
c
o
ca
9
8
(1024K)
256K
..
...E
~
(9216K)
.5
TM024EAD9
...CD
(ij
Numbers in parentheses indicate overall complexity.
C
CD
~
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
1-15
..
C)
CD
::::I
CD
..
......3
e!.
SELECTION GUIDE
DRAM/VRAM/FRAM SELECTION GUIDE
Density
Organization
Device
IWords X Bits)
Number
5'
o
64K
,..
64K Xl
SMJ4161-15
SMJ4161-20
SMJ4164-12
Max
Power
Access
Time Ins)
Supply
IV)
150
200
5±50/0
120
D)
SMJ4164-15
150
0'
SMJ4164-20
200
150
::::I
16K X 4
SMJ4416-15
SMJ4416-20
TMS4256-8
TMS4256-10
TMS4256-12
TMS4256-15
256K X 1
SMJ4256-12
SMJ4256-15
SMJ4256-20
TMS4257-10
TMS4257-12
256K
64K X 4
1-16
Pins
Package t
Comments
Page
132
20
JD
Military
Video RAM
8-3
28
16,18
JD, FG
Military
8-29
28
18
JD
Military
8-47
16,18,
16
N, FM,
Page Mode
4-3
16,18
JD, FV
Military
8-65
16,18,
N, FM,
Nibble
16
SD
Mode
110
24,24
N,SD
TTLlmW)
525
264
5±100/0
5±100/0
248
203
264
231
5±50/0
5±100/0
5±100/0
368
385
358
24
25
25
150
120
5±100/0
330
420
25
150
5±50/0
394
27
200
100
120
150
TMS4461-12
120
TMS4461-15
SMJ4461-15
150
TMS4464-10
TMS4464-12
TMS4464-15
Dissipation
Standby
Active
ImW)
80
100
120
TMS4257-15
315
385
5±100/0
5±100/0
358
330
853
Multiport
4-3
4-27
150
100
5±100/0
770
385
110
24
JD
120
150
5±100/0
358
330
25
18,18
N, FM
Page Mode
4-59
44
18
JD
Military
8-115
120
SMJ4464-15
150
200
770
25
SD
Video RAM
Military VRAM
SMJ4464-12
SMJ4464-20
tN
JD
FG,FV
FM
SD
200
Max Power
8-85
440
5±100/0
385
330
Plastic Dual In-line Package (DIP)
Ceramic Dual In-line Package (DIP-Military)
Ceramic Chip Carrier (CLCC-Military)
Plastic Chip Carrier (PLCC)
Plastic Zig-zag In-line Package IZIP)
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
SELECTION GUIDE
DRAM/VRAM/FRAM SELECTION GUIDE (CONCLUDED)
..
c
o
Density
Organization
(Words X Bits)
Device
Number
Max
Access
Time (ns)
TMS4C1024-10
TMS4C1024-12
TMS4C1024-15
100
120
150
SMJ4C1024-12§
SMJ4C1024-15§
120
TMS4C1025-10
100
120
150
Power
Supply
(V)
5±10%
'';::;
Max Power
ca
Dissipation
Active Standby
(mW) TIl(mW)
385
330
Pins
5±10%
303
Comments
N. OJ
CMOS
Enhanced
o
18.
20/26
17
18.
20/26
17
TMS4C1025-12
TMS4C1025-15
1024K
256K X 4
5±.10%
JO. HJ
150
TMS4C1027-10
100
TMS4C1027-12
TMS4C1027-15
120
150
TMS44C251-10:j:
100
TMS44C251-12:j:
TMS44C251-15:j:
120
150
TMS44C256-10
TMS44C256-12
100
120
TMS44C256-15
150
SMJ44C256-12§
SMJ44C256-15§
120
150
TMS44C257-10
100
TMS44C257-12
TMS44C257-15
120
150
TMS4C1050-3:j:
TMS4C1050-4:j:
TMS4C1050-6:j:
30
50
N. OJ
18.
20/26
N. OJ
28. 28
DJ. SD
385
5±10%
5±10%
5±10%
330
303
605
523
468
385
330
17
28
330
303
25
5±10o/c
330
303
275
248
193
Enhanced Page 8-135
CMOS
Nibble
~
4-151
Mode
CMOS Static
Column
4-151
Oecode Mode
20.
20/26
N. DJ
17
20.
20/26
JD. HJ
17
20.
20/26
N. OJ
17
385
5±10o/c
Q)
C
Q)
CMOS
Multipart
4-79
Video RAM
303
5±10%
16
Mode
18.
20/26
17
4-151
Page Mode
Military CMOS
1024K X 1
385
330
303
.E
.5
.
Page
'too
303
330
Package t
39
CMOS
Enhanced
4-119
Page Mode
Military CMOS
16.20.26 N. SD. OJ
Enhanced
Page Mode
CMOS Static
Column
8-133
4-119
Decode Mode
CMOS FRAM
4-189
tN Plastic Dual In-line Package (DIP)
JD Ceramic Dual In-line Package (DIP-Military)
OJ Plastic Small Outline J-Iead (SOJ)
HJ Ceramic Small Outline J-Iead (SOJ-Military)
SD Plastic zig-zag in-line Package (ZIP)
:j:Advance Information for product under development by TI.
§Preliminary Target Specification for product under development by TI.
TEXAS . "
INSTRUMENTS
POST OFFice BOX 1443 •
HOUSTON, TeXAS 77001
1-17
..
SELECTION GUIDE
DYNAMIC RAM MODULE SELECTION GUIDE
G)
CD
..e.
~
CD
Density
5'
.....
o
Organization
(Words X Bits)
1024K X 1
3
1024K
....
D)
o·
256K X 4
~
2048K
256K X 8
Device
Number
TM4256FC 1-1 0
TM4256FC1-12
TM4256FC1-15
TM4256EC4-10
100
120
150
100
TM4256EC4-12
TM4256EC4-15
120
150
TM4256FL8-10
100
TM4256FL8-12
TM4256FL8-15
120
150
TM4256GU8-10
100
120
TM4256GU8-12
TM4256GU8-15
2304K
4096K
1024K X 4
8192K
1024K X 8
9216K
1-18
256K X9
1024K X 9
Max
Access
Time (ns)
Power
Supply
(V)
100
TM4256EL9-12
TM4256EL9-15
120
150
TM4256GU9-10
100
TM4256GU9-12
TM4256GU9-15
120
TM024HAC4-10
100
TM024HAC4-12
TM024HAC4-15
120
150
TM024GAD8-10
100
TM024GAD8-12
120
TM024GAD8-15
TM024EAD9-10
150
100
TM024EAD9-12
TM024EAD9-15
120
150
Dissipation
Standby
TTL(mW)
Active
(mW)
Pins
Package t
Comments
Page
440
5±10%
413
385
1540
99
22
Leaded
Page Mode
5-9
5±10%
1430
1320
99
22
Leaded
Page Mode
5-3
198
30
Leaded
Page Mode
5-15
198
30
with Presence
Page Mode
5-15
Page Mode
5-21
Presence
Detect
Page Mode
5-21
3080
5±10%
2860
2640
Socketable
3080
5±10%
150
TM4256EL9-10
Max Power
2860
2640
Detect
3465
5±10%
3218
2970
3465
226
30
5±10%
3218
226
30
66
24
Leaded
Enhanced
Page Mode
132
30
Socketable
Enhanced
150
Socketable
2970
1540
5±10%
1320
1210
Leaded
~ith
CMOS
CMOS
3080
5±10%
2640
2420
2970
2723
CMOS
149
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
5-31
Page Mode
3465
5±10%
5-27
HOUSTON, TEXAS 77001
30
Socketable
Enhanced
Page Mode
5-31
SELECTION GUIDE
EPROM/EEPROM SELECTION GUIDE
Density
16K
32K
64K
Organization
Device
(Words X Bitsl
Number
2K X 8
4K X 8
8K X 8
Max
Power
Dissipation
Access
Supply
(VI
Active
(mWI
TMS27C291-3
35
5±5%
394
TMS27C291-35
TMS27C291
35
45
5±10%
5±5%
413
315
TMS27C291-45
45
5±10%
330
TMS27C291-5
50
5±5%
289
TMS27C291-50
50
5±10%
303
TMS27C292-3
35
5±5%
394
TMS27C292-35
TMS27C292
35
45
5±10%
5±5%
413
315
TMS27C292-45
45
5±10%
330
TMS27C292-5
50
5±5%
289
TMS27C292-50
50
5±10%
303
TMS27C32-100t
100
5±5%
132
TMS27C32-10t
100
5±10%
138
TMS27C32-120t
120
5±5%
132
TMS27C32-12t
120
5±10%
138
TMS27C32-150t
150
5±5%
132
TMS27C32-15t
150
5±10%
138
TMS27C32-2t
200
5±5%
5±10%
132
5±5%
132
5±10%
138
5±5%
657
TMS27C32-20t
200
TMS27C32t
TMS27C32-25t
250
250
TMS2732A-17
170
c
o
Max Power
Time (nsl
Standby
"';=
Pins
Package t
Comments
200
TMS2732A-25
250
TMS2732A-45
450
TMS27C49-4t
45
5±5%
473
TMS27C49-45*
TMS27C49-5t
45
5±10%
495
55
5±5%
473
TMS27C49-55t
55
5±10%
495
TMS27C64-100
100
5±5%
158
TMS27C64-120
TMS27C64-12
120
158
120
5±5%
5±10%
TMS27C64-1
150
5±5%
158
TMS27C64-15
150
5±10%
165
TMS27C64-2
200
5±5%
158
TTL(mWI
.5
N/A
24
J
High-Speed
CMOS
Q)
cQ)
CJ
High-Speed
6-3
N/A
24
J
1.4
24
J
CMOS
6-21
158
24
J
NMOS
6-13
N/A
24
J, JT
CMOS
6-43
1.4
28
J
CMOS
6-55
CMOS
165
TMS27C64-20
200
5±10%
165
250
5±5%
158
TMS27C64-25
250
5±10%
165
TMS2764-17
170
TMS2764-20
200
TMS2764-25
250
5±5%
788
184
28
J
NMOS
6-35
TMS2764-45
450
5±10%
110
17
28
J,N
CMOS
6-69
250
350
e
6-3
TMS27C64
TMS28C64-35t
ca
...2E
Page
138
TMS2732A-20
TMS28C64-25t
..
t J Ceramic DIP
JT 300-mil Ceramic DIP (TMS27C49 onlyl
N Plastic DIP
tAdvance Information for product under development by TI.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
1-19
..
G)
CD
:::l
CD
...
e!.
,SELECTION GUIDE
EPROM/EEPROM SELECTION GUIDE (CONTINUED)
Density
Organization
(Words X Bltsl
....S'"
o...
Device
Number
TMS27C128-100
TMS27C128-120
TMS27C128-12
3g)
....
o·
:::l
128K
16K X 8
5±10%
158
165
TMS27C128-2
TMS27C 128-20
200
5±5%
158
200
250
250
5±10%
5±5%
5±10%
158
165
200
250
5±10%
220
5±5%
5±10%
5±5%
5±10%
165
158
TMS27C256-15
120
150
150
TMS27C256-1
170
5±5%
165
158
TMS27C256-17
TMS27C256-2
170
5±10%
165
200
200
250
5±5%
5±10%
5±5%
158
TMS27C256-20
TMS27C256
TMS27C256-25
250
5±10%
165
158
165
SMJ27C256-20
SMJ27C256-25
200
TMS27C256-12
TMS27C256-150
64K X 8
Page
1.4
28
J
CMOS
6-79
1.7
28
J
1.4
28
J
1.7
28
J
1.4
28
J
1.8
28
J
158
158
165
165
250
300
5±10%
220
TMS27C512-1
TMS27C512-17
TMS27C512-2
170
170
200
5±5%
5±10%
5±5%
158
165
158
TMS27C512-20
TMS27C512
200
5±10%
165
250
5±5%
158
TMS27C512-25
250
300
300
200
5±10%
5±5%
5±10%
165
158
165
SMJ27C512-25
250
5±10%
263
SMJ27C512-30
300
t J Ceramic DIP
JT 300-mil Ceramic DIP (TMS27C49 only)
1-20
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX
~443
•
Military
CMOS
8-137
158
SMJ 27C2 56-30
TMS27C512-3
TMS27C512-30
SMJ27C512-20
Comments
TTL(mWI
150
TMS27C256-120
Package t
Standby
(mWI
TMS27C 128-1
300
120
Pins
Active
TMS27C128-15
SMJ27C128-20
512K
(VI
5±5%
5±5%
5± 10%
5±5%
SMJ27C128-25
SMJ27C128-30
32K X 8
Max Power
Dissipation
Power
Supply
100
120
120
150
TMS27C128
TMS27C 128-25
256K
Max
Access
Time (nsl
HOUSTON, TEXAS 77001
CMOS
Military
CMOS
CMOS
Military
CMOS
6-91
8-145
6-105
8-153
SELECTION GUIDE
EPROM/EEPROM SELECTION GUIDE (CONCLUDED)
Density
Power
Supply
Time (nsl
(VI
TMS27C010-170~
170
5±50/0
210
TMS27C01 0-200~
200
5±5%
TMS27C01 0-20~
200
5±10%
210
220
TMS27C01 0-250~
250
5±5%
210
Device
(Words X Bitsl
Number
128K X 8
1024K
64K X 16
c
o
"';:;
Max Power
Max
Access
Organization
..
Dissipation
Active
Standby
(mWI
TTL(mWI
TMS27C010-25~
250
5±10%
220
TMS27C01 0-300~
300
5±50/0
210
TMS27C01 0-30~
5±10%
220
5±10%
220
5±5%
210
SMJ27C010-250§
300
250
SMJ27C010-300§
300
TMS27C210-170~
170
TMS27C21 0-200~
200
5±50/0
210
TMS27C21 0-20 ~
200
5±10%
220
TMS27C21 0-250~
250
5±5%
210
TMS27C21 0-25 ~
250
5±10%
220
TMS27C210-300~
300
5±5%
210
TMS27C210-30~
300
5±10%
220
SMJ27C210-250§
250
SMJ27C210-300§
300
5±10%
220
Pins
Package t
ca
Comments
E
...
o
'to.5
Page
ca...
1.4
32
J
CMOS
CD
C
CD
6-119
C!J
1.5
32
J
1.4
40
J
1.5
40
J
Military
CMOS
CMOS
Military
CMOS
8-163
6-131
8-165
t J Ceramic DIP
JT 300-mil Ceramic DIP (TMS27C49 onlyl
~ Advance Information for product under development by TI.
§Preliminary Target Specification for product under development by TI.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
1 -21
..
SELECTION GUIDE
ONE-TIME PROGRAMMABLE PROM SELECTION GUIDE
G')
CD
..e.
S..O'3
:s
CD
Density
....
16K
Q)
Organization
(Words X Bits)
2K X 8
0'
:s
32K
4K X 8
Device
Number
128K
256K
8K X 8
16K X 8
32K X 8
Power
Supply
Max Power
Dissipation
(V)
Active
(mW)
TMS27PC291-3:j:
TMS27PC291-35:j:
TMS27PC291 :j:
35
35
45
5±5%
5±10%
5±5%
394
413
315
TMS27PC291-45 :t:
TMS27PC291-5:j:
45
50
5±10%
330
289
TMS27PC291-50:j:
TMS27PC32-120:j:
50
5±5%
5±10%
120
5±5%
120
150
5±10%
5±5%
150
200
5±10%
138
132
200
5±5%
5±10%
250
250
45
5±5%
TMS27PC32-25:j:
TMS27PC49-4:t:
5±10%
5±5%
TMS27PC49-45:j:
45
5±10%
132
138
473
495
TMS27PC49-5:t:
TMS27PC49-55:j:
55
5±5%
473
55
120
5±10%
495
TMS27PC64-1 20
5±5%
158
TMS27PC64-12
TMS27PC64-1
120
150
5±10%
5±5%
165
158
TMS27PC64-15
150
200
5±10%
165
TMS27PC64-2
158
TMS27PC64-20
200
5±5%
5±10%
TMS27PC64
TMS27PC64-25
TMS27PC128-1
250
5±5%
5±10%
5±5%
158
165
158
TMS27PC128-15
TMS27PC128-2
150
200
165
158
TMS27PC32-12:j:
TMS27PC32-150:t:
TMS27PC32-15:j:
TMS27PC32-2:j:
TMS27PC32-20:j:
TMS27PC32:j:
64K
Max
Access
Time (ns)
250
150
Pins
Package t
N/A
24.28
N. FN
1.4
24
N
CMOS
N/A
24.24 •.
28
N. NT.
FN
CMOS
1.4
28
N
CMOS
6-55
1.4
28.32
N. FM
CMOS
6-79
1.4
28.32
N. FM
CMOS
6-91
Standby
High-Speed
CMOS
6-3
303
132
138
132
6-21
138
6-43
165
TMS27PC128-20
200
5±10%
5±5%
5±10%
TMS27PC128
250
5±5%
158
TMS27PC128-25
TMS27PC256-150
250
150
5±10%
5±5%
TMS27PC256-15
TMS27PC256-1
150
170
5±10%
5±5%
165
158
165
158
TMS27PC256-17
TMS27PC256-2
170
200
5±10%
165
158
TMS27PC256-20
TMS27PC256
200
250
5±5%
5±10%
5±5%
TMS27PC256-25
250
5±10%
165
165
158
165
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
Page
TTL(mW)
tN Plastic DIP
NT 300-mil Plastic DIP (TMS27PC49 only)
FM Plastic Chip Carrier
FN Plastic Chip Carrier
:j:Advance Information for product under development by TI.
1-22
Comments
HOUSTON, TEXAS 77001
'SELECTION GUIDE
ONE-TIME PROGRAMMABLE PROM SELECTION GUIDE (CONCLUDED)
Density
512K
Organization
Device
(Words X Bitsl
Number
64K X 8
128K X 8
1024K
64K X 16
Max
Access
Time (nsl
Power
Supply
Dissipation
(VI
TMS27PC512-2
TMS27PC512-20
TMS27PC512
200
200
250
5±50/0
5±100/0
5±50/0
158
165
158
TMS27PC512-25
250
165
158
TMS27PC512-3
300
5±100/0
5±50/0
TMS27PC512-30
TMX27PC010-200§
TMX27PC010-20§
TMX27PC010-250§
300
5±100/0
165
200
200
250
5±50/0
5±100/0
5±50/0
210
220
TMX27PC010-25§
250
5±100/0
220
TMX27PC010-300§
300
5±50/0
210
210
TMX27PC010-30§
300
5±100/0
220
TMX27PC21 0-200 §
TMX27PC210-20§
200
200
5±50/0
5±100/0
210
220
TMX27PC210-250§
TMX27PC210-25§
250
5±50/0
210
250
220
TMX27PC210-300§
300
5±100/0
5±50/0
TMX27PC210-30§
300
5±100/0
220
Standby
TTL(mWI
Pins
Package t
..E
.5
..
ra
Comments
Page
~
CO
1.4
28,32
N, FM
CMOS
6-105
Q)
C
Q)
c.::J
1.4
32
N
CMOS
6-143
1.4
40
N
CMOS
6-145
210
tN Plastic DIP
NT 300-mil Plastic DIP (TMS27PC49 only)
FM Plastic Chip Carrier
FN Plastic Chip Carrier
§Preliminary Target Specification for product under development by TI.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
c
o
"';:=
Max Power
Active
(mWI
..
HOUSTON, TEXAS 77001
..
SELECTION GUIDE
MILITARY SRAM SELECTION GUIDE
C)
CD
:J
CD
...e.
Density
Organization
(Words X Bits)
5'
....
o...
3
16K X 1
....
o·
:J
I»
16K
4K X 4
2K X 8
64K X 1
64K
16K X 4
8K X 8
72K
8K X 9
256K X 1
256K
288K
Device
Number
SMJ61CD16-25
SMJ61CD16-35
SMJ61CD16-45
Max
Access
Time (ns)
25
35
45
SMJ64C16-25;
25
SMJ64C16-35;
SMJ64C16-45;
35
45
SMJ68CE16-25;
25
SMJ68CE16-35;
SMJ68CE16-45;
35
45
SMJ61CD64-25;
25
SMJ61CD64-35;
SMJ61 CD64-45;
35
45
(V)
Max Power
Dissipation
Active Standby
(mW) TTl(mW)
Package t
Comments
Page
CMOS Military
Separate
1/0 Pins
8-167
5±10%
650
55
20
JD, FG
5±10%
650
55
20
JD, FG
5±10%
650
55
24,32
JD, FG
5±100/0
715
55
22
JD, FG
25
5±10%
715
55
22
JD, FG
SMJ68CE64-25;
35
45
25
SMJ68CE64-35;
SMJ68CE64-45 ;
35
45
5±10%
715
55
28,32
JD, FG
25
SMJ69CE72-35;
SMJ69CE72-45;
35
45
SMJ61 CD256-35;
35
SMJ61CD256-45;
SMJ61 CD256-55;
45
SMJ64C2 56-3 5 §
35
45
55
32K X 8
SMJ68CE256-45§
35
45
SMJ68CE256-55 §
55
SMJ69CE288-35 §
35
SMJ69CE288-45 §
SMJ69CE288-55§
45
55
Output Enable
Control
8-187
Separate
1/0 Pins
CMOS
Military
8-197
8-207
CMOS Military
Output Enable
8-217
Control
CMOS Military
5±100/0
715
55
28,32
JD, FG
Output Enable
Control
CMOS Military
8-227
5±100/0
440
55
24,28
JD, FG
Separate
1/0 Pins
8-237
5±10%
440
55
24,28
JD, FG
5±10%
440
55
28,32
JD, FG
5±100/0
440
55
32
JD, FG
55
SMJ64C256-45§
SMJ64C256-55 §
SMJ68CE256-35 §
8-177
CMOS Military
SMJ64C64-35;
SMJ64C64-45;
SMJ69CE72-25;
CMOS
Military
CMOS Military
CMOS
Military
8-239
CMOS Military
Output Enable
Control
8-241
CMOS Military
t JD Ceramic Dual In-line Package (DIP-Military)
FG Ceramic Chip Carrier (CLCC-Military)
; Advance Information for product under development by Ti.
§Preliminary Target Specification for product under development by Ti.
1-24
Pins
SMJ64C64-25;
64K X 4
32K X 9
Power
Supply
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Output Enable
Control
8-243
SELECTION GUIDE
VLSI MEMORY MANAGEMENT PRODUCTS
..
c
o
DRAM CONTROLLERS
PROVIDE ADDRESS MULTIPLEXING AND REFRESH CONTROL
Device
Features
Type
TMS4500A
THCT4502B
64K DRAMs, On-chip Refresh Timing Control
75ALS2967
74ALS296B
256K DRAMs,
256K DRAMs,
256K DRAMs, On-chip Refresh Timing Control
> 200 to 60 ns DRAMs, RAS, CAS
> 200 to 60 ns DRAMs, RAS, CAS
1 Megabit DRAMs, > 200 to 60 ns DRAMs, RAS, CAS
1 Megabit DRAMs, > 200 to 60 ns DRAMs, RAS, CAS
74ALS6301
74ALS6302
"';:=
CO
..-2E
..
tpd Insl
MAXt
Pins
Page
250
115
40
48
7-211
7-197
.5
16
35
35
48
48
7-157
7-157
35
35
52
52
7-177
7-177
CD
C
CD
Pins
Page
24
7-149
28
28
7-151
7-135
28
7-121
28
7-135
CJ
tMemory Access Time
CACHE ADDRESS COMPARATORS
ON-CHIP PARITY GENERATION AND CHECKING
Device
Type
TACT2150
tpd Insl
MAX*
Features
1 I'm EPIC", Fastest Available, 512 x 8 RAM
1K x 11 Cache Tag RAM
74ACT2151
74ACT2152
2K x 8 Cache Tag RAM
74ACT2153
1K x 11 Cache Tag RAM with Open Drain Match Pin
2K x 8 Cache Tag RAM with Open Drain Match Pin
74ACT2154
30/20
25/35
25/35
25/35
25/35
*Address Match Time
EPIC" is a trademark of Texas Instruments Incorporated.
ERROR DETECTION AND CORRECTION UNITS
CORRECTS 1-BIT MEMORY ERRORS AND FLAGS 2-BIT ERRORS
Device
Type
74ALS632B
74ALS634B
74AS632
74AS634
tpd Insl
MAX§
Features
Pins
Page
32-bit, 3-state with Byte-Write Capability
32-bit, 3-state, No Byte-Write
30
52
7-89
30
48
Fastest 32-bit EDAC Available
25
25
52
48
7-89
7-107
32-bit, 3-state, No Byte-Write (Speed Enhanced' ALS6341
7-107
§Single Bit Detection Time
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
1-25
-
SELECTION GUIDE
MOS MEMORY DRIVERS WITH SERIES DAMPING RESISTORS
G)
CD
Device
Type
:::::I
.,CD
9!..
74BCT2827A
....S'"
o.,
3
g)
74BCT2828A
74BCT29827A
74BCT29828A
IOllmAI
MAX
Pins
Page
BiCMOS 10-bit Buffer/Driver, 3-state Output
BiCMOS 10-bit Buffer/Driver, Inverting 3-state Output
12
24
7-235
12
BiCMOS 10-bit Buffer/Driver, 3-state Output
48
48
24
24
7-235
7-241
24
7-241
tpd Insl
MAX
Pins
Page
18
14
20
20
7-227
7-227
Pins
Page
Features
BiCMOS 10-bit Buffer/Driver, Inverting 3-state Output
MEMORY ACCESS DETECTORS
r+
0"
Device
Type
:::::I
74AlS6310
74AlS6311
Features
Static Column and Page Mode, High Performance Compare
Static Column and Page Mode, High Performance Compare
FIRST-IN FIRST-OUT (FIFO) MEMORIES
Device
Type
74ALS229A
74ALS232A
74ALS233A
74ALS234
74ALS235
74ALS236 t
74ALS2232
74ALS2233
74ACT7201A
74ACT7202
Density
Depth
f max
16 x 5
16 x 4
16 x 5
64 x 4
30
30
64 x 5
64 x 4
25
Expansion
No
No
No
30
30
Yes
Yes
Yes
1K x 9
7-13
20
7-27
7-39
7-19
28
Yes
28
7-77
7-83
7-47
22
Yes
28
7-63
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
20
16
No
No
tCompatible with the '67401
1-26
7-3
7-9
16
24
28
30
40
40
64 x 8
64 x 9
512 x 9
20
16
HOUSTON, TEXAS 77001
Ie LINE-UP
MOS MEMORY LlNE-Upt
..
r:
o
"';:
DRAMSLNMOS- 256K--r256K x l-TMS4256 -TMS4257
L.. 64K x 4 - TMS4464 TMS4461 Multipart Video
.E
.
ca
o
CMOS-l024K-,--lM x 1 -TMS4Cl024-TMS4Cl025-TMS4Cl027
L256K x 4 -TMS44C256-TMS44C257-TMS44C251
Multipart
Video
'too
.5
CO
C1)
DRAM1NMOS11024K--1M
MODULES
1024K--256K
2048K-- 256K
2304K--256K
CMOS
1
x
x
x
x
r:
C1)
C!J
l-TM4256FCl
4-TM4256EC4
8 - TM4256FL8 - TM4256GU8
9-TM4256EL9-TM4256GU9
4096K--1M x 4-TM024HAC4
8192K--1M x 8 -TM024GAD8
9216K--1M x 9-TM024EAD9
FRAM----CMOS-l024K--256K x 4 -TMS4Cl050
MOS
MEMORY
EPROMLNMOS .--32K--4K x 8-TMS2732A
L-64K--8K x 8-TMS2764
CMOS~16K _ _ 2K x 8 32K--4K
64K---8K
128K--16K
256K--32K
512K--64K
1024K-.64K
L128K
x
x
x
x
x
x
x
TMS27C291- TMS27C292
8-TMS27C32
8-TMS27C64-TMS27C49
8-TMS27C128
8-TMS27C256
8-TMS27C512
16-TMS27C210
8 - TMS27C010
PROM----CMOS~16K _ _ 2K x 8 -TMS27PC291
32K--4K
64K--8K
128K--16K
256K--32K
512K--64K
1024K-.64K
L128K
x
x
x
x
x
x
x
8 - TMS27PC32
8 -TMS27PC64-TMS27PC49
8 -TMS27PC128
8 -TMS27PC256
8 -TMS27PC512
16-TMX27PC210
8
TMX27PC010
EEPROM---CMOS--64K---8K x 8-TMS28C64
tOnly commercial devices are listed.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
1-27
G')
CD
:::s
...e.CD
5"
....
o...
3D)
....
o·:::s
1-28
General Information . .
I
Alternate Source Directories . .
Glossary/Timing Conventions/Data Sheet Structure
Dynamic RAMs . .
Dynamic RAM Modules . .
EPROMs/PROMs/EEPROMs . .
VLSI Memory Management Products . .
Military Products . .
Applications Information .. . .
Quality and Reliability
Logic Symbols
Mechanical Data
ESD Guidelines
-
»
..::s
;:;'
CD
,...
CD
en
o
Q)
.
c:
(')
CD
C
:;"
CD
,...
(')
.
o
iii"
en
2-2
ALTERNATE SOURCE DIRECTORY
DRAMs
ORGANIZATION
VENDOR
TI
ALTERNATE SOURCES
TI
PART NUMBER
TMS4461
64K X 4
VRAM
Fujitsu
MB81461
Hitachi
HM53462/HM53461
Hyundai
HY51C264
Mitsubishi
M5M4C264P
NEC
pPD41264~PD42264
Vitelic
V51C261/V51C264
TI
TMS4464
64K X 4
Fujitsu
MB81 C466/MB81464
Hitachi
HM50464/HM50465
Hyundai
HY 51464/HY 51 C464
Intel
51C259
Micron Tech
MT4064/MT4067
Mitsubishi
M5M4464
NEC
pPD41464
OKI
MSM41464
Sharp
LH2464/LH2465
Toshiba
TMM41464
TI
TMS4256
AMD
256K X 1
PAGE MODE
AM90C256
AT&T
M41256P
Fujitsu
MB81256/MB41256
Hitachi
HM50256
Hyundai
HY51C256UHY51256
Intel
51C256H
Micron Tech
MT1256
Mitsubishi
M5M4256
Mostek
Motorola
MK45H6
NEC
pPD41256
MCM6256B
NMB
AAA2800
OKI
MSM41256
Panasonic
MN41256
Samsung
KM41256
Sharp
LH21256
Toshiba
TMM41256
TI
TMS4257
AMD
256K X 1
NIBBLE MODE
AM90C255
AT&T
M41256N
Fujitsu
MB81257/MB41257
Hitachi
Mitsubishi
HM50257
M5M4257
NEC
pPD41257
NMB
AAA2800
OKI
MSM41257
Samsung
Sharp
KM41257
Toshiba
TMM41257
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
LH21257
..
( /)
CI)
".:
o
....CJ
...
CI)
C
CI)
...CJ
~
o
rn
....ca
CI)
...c:
....
CI)
«
ALTERNATE SOURCE DIRECTORY
..
DRAMs (CONCLUDED)
ORGANIZATION
VENDOR
TI
TI
ALTERNATE SOURCES
PART NUMBER
Fujitsu
TMS44C251
MB81 C4251 /MB81 C4252
Hitachi
OKI
HM534251/2/3
MSM514251/MSM514252
Toshiba
TC524256/TC524257
TMS44C256
en
AT&T
M441024
c
Hitachi
HM514256
Mitsubishi
NEC
NMB
/tPD414256//tPD424256
AAA 1M 104/AAA 1M204
OKI
Sharp
MSM414256/MSM514256
LH64256
Toshiba
Mitsubishi
TC514256
TMS44C257
M5M44C258
l>
::+
.
256K X 4
VIDEO RAM
CD
..
:J
Q)
CD
TI
.
o
256K X 4
ENHANCED PAGE MODE
()
CD
C
:;"
....
CD
()
o
TI
;"
(I)
256K X 4
STATIC COLUMN DECODE
NMB
AAA 1M 104/AAA 1M204
OKI
MSM514257
Sharp
LH64256
TC514258
Toshiba
TI
1M X 1
ENHANCED PAGE MODE
TMS4C1024
AT&T
Fujitsu
M511024
MB811000
Hitachi
HM511000
Hyundai
Micron Tech
HY51C100
MT41COO1
Mitsubishi
M5M4C1000
NEC
NMB
/tPD411000
AAA 1M 1OO/AAA 1M200
OKI
Panasonic
MSM411000/MSM511000
MN411000
Toshiba
TC511000
TI
1M X 1
NIBBLE MODE
TMS4C1025
Fujitsu
Mitsubishi
MB811001
M5M4C1001
NEC
NMB
/tPD411001
AAA1M200
OKI
Toshiba
MSM411001
TC511001
Hitachi
TMS4C1027
HM511001
TI
1M X 1
STATIC COLUMN DECODE
2-4
M5M44C256
Mitsubishi
M5M4C1002
NMB
AAA 1M 1OO/AAA 1M200
OKI
Toshiba
MSM511001
TC511002
TEXAS . .
INSTRUMENTS
POST OFFice BOX 1443 •
HOUSTON, TeXAS 77001
ALTERNATE SOURCE DIRECTORY
DYNAMIC RAM MODULES
ORGANIZATION
TI
TI
256K X 4
VENDOR
ALTERNATE SOURCES
TM4256EC4
DENSE-PAC
Fujitsu
DPD44256
MB85203/MB85204
Hitachi
HB561004A
Micron Tech
NEC
MT4259
MC41256A4
DENSE-PAC
DPD42568
Hitachi
Micron Tech
Mitsubishi
NEC
HB451008B
MT8259
MH25608A
MC41256A8
NMB
MM2800
OKI
MSC2304KS8
DENSE-PAC
TM4256GU8
DPD42568
Hitachi
HB561008B
Micron Tech
MT8259
Mitsubishi
NEC
MH25608
MC41256A8
NMB
OKI
MM2800
MSC2304YS8
TM4256EL9
DENSE-PAC
DPD42569
MB85227
TI
256K X 8
TI
Fujitsu
Hitachi
Micron Tech
Mitsubishi
256K X 9
NMB
NEC
1M X 4
..
is
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..
....
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MC41256A9
MSC2304KS9
Toyocom
TH22569/TH32569
DENSE-PAC
TM4256GU9
DPD42569
Fujitsu
MB85227
Hitachi
Micron Tech
Mitsubishi
HB561 003/HB561 009
MT9259
MH25609
NMB
NEC
MM2800
MC441256A9
OKI
MSC2304YS9
Toyocom
TH22569/TH32569
DENSE-PAC
EDI
TM4256FC1
DPD411M
DH411 M-__ C4/EDH411 M- -- C4
Fujitsu
NEC
MB85201/MB85208
MC411000A1
TI
1M X 1
fn
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·c
....o
HB561003/HB561009
MT9259
MH25609A
MM2800
OKI
TI
256K X 9
..
TM4256FL8
TI
256K X 8
PART NUMBER
TI
TM024HAC4
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
2-5
ALTERNATE SOURCE DIRECTORY
..
DYNAMIC RAM MODULES (CONCLUDED)
ORGANIZATION
.,
ALTERNATE SOURCES
TI
»
;::;:'
CD
VENDOR
TI
TM024GAD8
1M X 8
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pot.
CD
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Interplex (NAS)
1TM-S-1000-P-08
Micron
MT8C8024MN
Mitsubishi
MH1M08
OKI
2310- -- YS8
Toshiba
THM81000S
TI
o
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TM024EAD9
Hitachi
"C
~"
CD
HB56A198
Interplex (NAS)
1TM-S-1 000-P-09
Micron
MTC9024MN
Mitsubishi
OKI
MH1M09
2310- -- YS9
Toshiba
THM91000S
1M X 9
CD
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pot.
c"
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2-6
PART NUMBER
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
ALTERNATE SOURCE DIRECTORY
EPROMs
ORGANIZATION
VENDOR
TI
ALTERNATE SOURCES
TI
2K X 8
HIGH SPEED
CMOS
AMD
AM27S191A
Cypress
CY7C292
ICT
27CX322
MMI
63S1681
National
DM87S291
Signetics
N82S191
Waferscale
TI
-
tn
CD
'Ii:
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.....
()
...CD
is
WS57C291
CD
...
:l
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TMS2732A
AMD
4K X 8
NMOS
AM2732A/AM2732B
Fujitsu
MBM2732A
Hitachi
HN482732
Intel
2732A
National
NMC27C32
Panatech
RD27C32
SGS
4K X 8
PART NUMBER
TMS27C292
TI
o
en
CD
.....
CO
...c:CD
.....
M2732A
<
TMS27C32
National
CMOS
Panatech
TI
NMC27C32
RD27C32
TMS2764
AMD
Fujitsu
8K X 8
NMOS
AM2764A
MBM2764
Hitachi
HN482764
Hyundai
HY2764
Intel
2764A
Mitsubishi
M5L2764
Motorola
MSM68764
NEC
/-IPD2764
MSM2764
OKI
SEEQ
5133/2764
SGS
M2764
Toshiba
TMM2764
TI
TMS27C64
8K X 8
CMOS
Atmel
AM27HC64
Cypress
CY7C261/CY7C263/CY7C264
Cypress
CY7C268/CY7C269
Fujitsu
MBM27C64
GI
27C64
Goldstar
GM27HC64
Hitachi
HN27C64
Hyundai
HY27C64
Intel
27C64/87C64
National
NMC27C64
NEC
/-IPD27C64
OKI
MSM27C64
S-MOS
Signetics
SPM27C64
Thomson
TS27C64
Waferscale
WS27C64F/WS27C49
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
27C64/87C64
2-7
ALTERNATE SOURCE DIRECTORY
..
EPROMs (CONTINUED)
ORGANIZATION
»
::+
"m::s.
"en
o
VENDOR
TI
TI
TMS27C128
AMD
AM27128
AT27C128
MBM27C128/MBM27128
Atmel
Fujitsu
, GI
..
27C128
Hitachi
Mitsubishi
.
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HN27128A/HN4827128G
M5L27128/M5M27C128
16K X 8
National
NMC27CP128
CMOS
NEC
OKI
S-MOS
SEEQ
pPD27128
MSM27128/MSM27C128
SPM27129C
Toshiba
VLSI
TMM27128
VT27C128
VTI
Waferscale
VT27C128
WS57C128F/WS57C251
AMD
TMS27C256
AM27C256/AM27256
Atmel
AT27C256/AT27256
(')
"
"o
'0
:;"
...
(')
m"
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27128
TI
Fujitsu
MBM27C256/MBM27256
Hitachi
GI
Intel
HN27C256/HN27256
27C256/27256
27256/27C256
Mitsubishi
M5M27C256/M5L27256
Motorola
MCM67256/9
32K X 8
National
CMOS
NEC
OKI
Panatech
NMC27C256
pPD27256
MSM27C256/MSM27256
S-MOS
SEEQ
SGS
Signetics
Thomson
Toshiba
Waferscale
TI
WS57C256F
Intel
27512
Mitsubishi
M5L27512
National
NEC
OKI
pPD27C512
MSM27512
Panatech
Toshiba
TEXAS
"'11
INSTRUMENTS
POST OFFICE BOX 1443 •
27C256
TS27C256
TMM27256/TC57256
MBM27C512
27C512
HN27512
Hitachi
CMOS
SPM27C256
27C256
M27256A
AT27C512
Fujitsu
GI
64K X 8
RD27C256
TMS27C512
AM27512/AM27C512
AMD
Atmel
2-8
PART NUMBER
ALTERNATE SOURCES
HOUSTON, TEXAS 77001
NMC27C512
TMS27C512
TC57512/TMM27512
ALTERNATE SOURCE DIRECTORY
EPROMs (CONCLUDED)
ORGANIZATION
VENDOR
TI
TI
PART NUMBER
ALTERNATE SOURCES
TMS27C210
AMD
AM27C1024
AT27C1024
MBM27C1024
Atmel
Fujitsu
64K X 16
Intel
CMOS
National
NEC
OKI
128K X 8
CMOS
Atmel
Fujitsu
AT27C010
MBM27C1000/1
Hitachi
Intel
HN27C101
Mitsubishi
NEC
M5M27C100/1/2
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27010
OKI
/LPD27C1000
MSM271000
Toshiba
TC571000
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INSTRUMENTS
POST OFFICE BOX 1443 •
....oCJ
I'PD27C1024
MSM271 024/MSM27C 1024
TC571024
TMS27C010
TEXAS
en
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27210
NMC27C1024
Toshiba
TI
..
HOUSTON, TEXAS 77001
....
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..
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2-10
General Information . .
Alternate Source Directories . .
Glossary/Timing Conventions/Data Sheet Structure
Dynamic RAMs . .
Dynamic RAM Modules . .
EPROMs/PROMs/EEPROMs
VLSI Memory Management Products
Military Products . .
Applications Information. . .
Quality.and Reliability
Logic Symbols
Mechanical Data
ESD Guidelines
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3-2
GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTURE
PART I - GENERAL CONCEPTS AND TYPES OF MEMORIES
Address - Any given memory location in which data can be stored or from which it can be retrieved.
Automatic Chip-Select/Power Down Bit -
(see Chip Enable Input)
Contraction of Binary digiT, i.e., a 1 or a 0; in electrical terms the value of a bit may be represented by
the presence or absence of charge, voltage, or current.
.
Byte - A word of 8 bits (see word)
CMOS - A complementary MOS technology which uses transistors with electron (N-channel) and hole
(P-channel) conduction.
..
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Chip Enable Input - A control input to an integrated circuit that when active permits operation of the integrated
circuit for input, internal transfer, manipulation, refreshing, and/or output of data and when inactive causes
the integrated circuit to be in a reduced power standby mode.
.......
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Chip Select Input - Chip select inputs are gating inputs that control the input to and output from the memory.
They may be of two kinds:
1.
Synchronous-Clockedllatched with the memory clock. Affects the inputs and outputs for
the duration of that memory cycle.
2.
Asynchronous-Has direct asynchronous control of inputs and outputs. In the read mode,
an asynchronous chip select functions like an output enable.
.
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Column Address Strobe (CAS) - A clock used in dynamic RAMs to control the input of column addresses.
It can be active high (CAS) or active low (CAS).
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Data _. Any information stored or retrieved from a memory device.
DIP -
Dual In-line Package.
Dynamic (Read/Write) Memory (DRAM) - A read/write memory in which the cells require the repetitive
application of control signals in order to retain the stored data.
NOTES: 1. The words "read/write" may be omitted from the term when no misunderstanding 'will
result.
2. Such repetitive application of the control signals is normally called a refresh operation.
3. A dynamic memory may use static addressing or sensing circuits.
4. This definition applies whether the control signals are generated inside or outside the
integrated circuit.
(.)
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Electrically Erasable Programmable Read-Only Memory (EEPROM) - A nonvolatile memory that can be fieldprogrammed like a PROM or EPROM, but that can be electrically erased by a combination of electrical
signals at its inputs.
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Erasable and Programmable Read-Only Memory (EPROM) - A field-programmable read-only memory that can
have the data content of each memory cell altered more than once.
Erase - Typically associated with EPROMs and EEPROMs. The procedure whereby programmed data is removed
and the device returns to its unprogrammed state.
FRAM - First-in First-out pseudo static RAM or Field RAM.
Field-Programmable Read-Only Memory -
(see One-time Programmable Read-Only Memory)
Fixed Memory - A common term for ROMs, EPROMs, EEPROMs, etc., containing data that is not normally
changed. A more precise term for EPROMs and EEPROMs is nonvolatile since their data may be easily
changed.
Fully Static RAM - In a fully static RAM, the periphery as well as the memory array is fully static. The periphery
is thus always active and ready to respond to input changes without the need for clocks. There is no
precharge required for static periphery.
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
3-3
GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTURE
K - When used in the context of specifying a given number of bits of information, 1K
Thus, 64K = 64 X 1024 = 65,536 bits.
= 2 10 =
1024 bits.
Large-Scale Integration (LSI) - The description of any IC technology that enables condensing more than 100
qates onto a single chip.
Mask-Programmed Read-Only Memory - A read-only memory in which the data content of each cell is
determined during manufacture by the use of a mask, the data content thereafter being unalterable.
_
Memory - A medium capable of storing information that can be retrieved.
Memory Cell - The smallest subdivision of a memory into which a unit of data has been or can be entered,
in which it is or can be stored, and from which it can be retrieved.
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Metal-Oxide Semiconductor (MOS) - The technology involving photolithographic layering of metal and oxide
to produce a semiconductor device.
~
NMOS. - A type of MOS technology in which the basic conduction mechanism is governed by electrons. (Short
for N-channel MOS)
S'
Nonvolatile Memory - A memory in which the data content is maintained whether the power supply is connected
or not.
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One-time Programmable Read-Only Memory (PROM) - A read-only memory that after being manufactured,
can have the data content of each memory cell altered once.
(I)
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3'
CC
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Output Enable - A control input that, when true, permits data to appear at the memory output, and when false,
causes the output to assume a high-impedance state. (See also chip select)
,...::::s
0'
::::s
PLCC - Plastic Leaded Chip Carrier package.
C
PMOS - A type of MOS technology in which the basic conduction mechanism is governed by holes. (Short
for P-channel MOS)
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Parallel Access - A feature of a memory by which all the bits of a byte or word are entered simultaneously
at several inputs or retrieved simultaneously from several outputs.
CD
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,...
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Power Down - A mode of a memory during which the device is operating in a low-power or standby mode.
Normally read or write operations of the memory are not possible under this condition.
CD
C
Program - Typically associated with EPROM and PROM memories, the procedure whereby logical Os (or 1s)
are stored into various desired locations in a previously erased device.
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Program Enable - An input signal that when true, puts a programmable memory device into the program mode .
~
Programmable Read-Only Memory (PROM) -
(see One-time Programmable Read-Only Memory)
Printed Wiring Board (PWB) - A substrate of epoxy glass, clad material, or other material upon which a pattern
of conductive traces is formed to interconnect the components which will be mounted upon it.
Read - A memory operation whereby data is output from a desired address location.
Read-Only Memory (ROM) - A memory in which the contents are not intended to be altered during normal
operation.
NOTE:
Unless otherwise qualified, the term "read-only memory" implies that the contents is determined
by its structure and is unalterable.
Read/Write Memory - A memory in which each cell may be selected by applying appropriate electrical input
signals and the stored data may be either (a) sensed at appropriate output terminals; or (b) changed in
response to other similar electrical input signals.
Row Address Strobe (RAS) - A clock used in dynamic RAMs to control the input of the row addressed. It can
be active high (RAS) or active low (RAS).
3-4
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTURE
SOJ - Small Outline J-Iead package.
Scaled-MOS (SMOS) - MOS technology under which the device is scaled down in size in three dimensions
and in operating voltages allowing improved performance.
Semi-Static (Quasi-Static, Pseudo-Static) RAM - In a semi-static RAM, the periphery is clock-activated (i.e.,
dynamic). Thus the periphery is inactive until clocked, and only one memory cycle is permitted per clock.
The peripheral circuitry must be allowed to reset after each active memory cycle for a minimum precharge
time. No refresh is required.
Serial Access - A feature of a memory by which all the bits are entered sequentially at a single input or retrieved
sequentially from a single output.
SIP -
..
Single In-line package.
Small Outline Integrated Circuit (SOIC) - A package in which an integrated circuit chip can be mounted to form
a surface-mounted component. It is made of a plastic material which can withstand high temperatures
and has leads formed in a gull-wing shape along its two longer sides for connection to a PWB footprint.
....
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Static RAM (SRAM) - A read/write random-access device within which information is stored as latched voltage
levels. The memory cell is a static latch that retains data as long as power is applied to the memory array.
No refresh is required. The type of periphery circuitry sub-categorizes static RAMs.
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-
Very-large-Scale Integration (VlSI) - The description of any IC technology that is much more complex than
large-scale integration (LSI), and involves a much higher equivalent gate count. At this time an exact
definition including a minimum gate count has not been standardized by JEDEC or the IEEE.
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Volatile Memory - A memory in which the data content is lost when power supplied is disconnected.
Word - A series of one or more bits that occupy a given address location and that can be stored and retrieved
in parallel.
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Write - A memory operation whereby data is written into a desired address location.
(.)
Write Enable - A control signal that when true causes the memory to assume the write mode, and when false
causes it to assume the read mode.
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-
ZIP - Zig-zag In-line package.
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PART II - OPERATING CONDITIONS AND CHARACTERISTICS
(INCLUDING LETTER SYMBOLS)
t/)
t/)
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Capacitance
The inherent capacitance on every pin, which can vary with various inputs and outputs.
Example symbology:
Ci
Co
Ci(D)
Input capacitance
Output capacitance
Input capacitance, data input
Current
High-level input current, IIH
The current into an input when a high-level voltage is applied to that input.
TEXAS
-I/}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
3-5
GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTURE
High-level output current, 10H
The current into* an output with input conditions applied that according to the product specification will
establish a high level at the output.
Low-level input current, IlL
The current into an input when a low-level voltage is applied to that input.
-
Low-level output current, 10L
The current into* an output with input conditions applied that according to the product specification will
establish a low level at the output.
Off-state (high-impedance-state) output current (of a three-state output), 10Z
The current into* an output having three-state capability with input conditions applied that according to
the product specification will establish the high-impedance state at the output.
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Short-circuit output current, lOS
The current into * an output when the output is short-circuited to ground (or other specified potential) with
input conditions applied to establish the output logic level farthest from ground potential (or other specified
potential).
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Supply current, IBB, ICC, 100, Ipp
The current into, respectively, the VBB, Vee, VOD, Vpp supply terminals.
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*Current out of a terminal is given as a negative value.
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Operating Free-Air Temperature
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The temperature (T A) range over which the device will operate and meet the specified electrical
characteristics.
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Operating Case Temperature
m
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CA
The case temperature (Te) range over which the device will operate and meet the specified electrical
characteristics.
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Voltage
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High-level input voltage, VIH
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An input voltage within the more positive (less negative) of the two ranges of values used to represent
the binary variables.
NOTE:
A minimum is specified that is the least positive value of high-level input voltage for which
operation of the logic element within specification limits is guaranteed.
~
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High-level output voltage, VOH
The voltage at an output terminal with input conditions applied that according to the product specification
will establish a high level at the output.
Low-level input voltage, VIL
An input voltage level within the less positive (more negative) of the two ranges of values used to represent
the binary variables.
NOTE:
A maximum is specified that is the most positive value of low-level input voltage for which
operation of the logic element within specification limits is guaranteed.
3-6
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTURE
Low-level output voltage, VOL
The voltage at an output terminal with input conditions applied that according to the product specification
will establish a low level at the output.
Supply voltages, VBB, VCC, VOO, Vpp
The voltages supplied to the corresponding voltage pins that are required for the device to function. From
one to four of these supplies may be necessary, along with ground, VSS.
Time Intervals
..
New or revised data sheets in this book use letter symbols in accordance with standards recently adopted
by JEDEC, the IEEE, and the IEC. Two basic forms are used. The first form is usually used in this book
when intervals can easily be classified as access, cycle, disable, enable, hold, refresh, setup, transition,
or valid times and for pulse durations. The second form can be used generally but in this book is used
primarily for time intervals not easily classifiable. The second (unclassified) form will be described first.
Since some manufacturers use this form for all time intervals, symbols in the unclassified form are given
with the examples for most of the classified time intervals.
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Unclassified time intervals
C'CS
C'CS
Generalized letter symbols can be used to identify almost any time interval without classifying it using
traditional or contrived definintions. Symbols for unclassified time intervals identify two signal events listed
in from-to sequence using the format:
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Subscripts A and C indicate the names of the signals for which changes of state or level or establishment
of state or level constitute signal events assumed to occur first and last, respectively, that is, at the beginning
and end of the time interval. Every effort is made to keep the A and C subscript length down to one letter,
if possible (e.g., R for RAS and C for CAS).
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C
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Subscripts Band D indicate the direction of the transitions and/or the final states or levels of the signals
represented by A and C, respectively. One or two of the following is used:
-
H = high or transition to high
L = low or transition to low
V = a valid steady-state level
X = unknown, changing, or "don't care" level
Z = high-impedance (off) state
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The hyphen between the Band C subscripts is omitted when no confusion is likely to occur.
For examples of symbols of this type, see TMS4256 (e.g., tRLCLl.
Classified time intervals (general comments, specific times follow)
Because of the information contained in the definitions, frequently the identification of one or both of the
two signal events that begin and end the intervals can be significantly shortened compared to the unclassified
forms. For example, it is not necessary to indicate in the symbol that an access time ends with valid data
at the output. However, if both signals are named (e.g., in a hold time), the from-to sequence is maintained.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
3-7
GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTURE
Access time
..
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The time interval between the application of a specific input pulse and the availability of valid signals at
an output.
Example symbology:
Classified
talA)
tatS), ta(CS)
Unclassified
Description
tAVQV
tSLQV
Access time from address
Access time from chip select (low)
Cycle time
-<:=t
The time interval between the start and end of a cycle.
The cycle time is the actual time interval between two signal events and is determined by the
NOTE:
system in which the digital circuit operates. A minimum value is specified that is the shortest
interval that must be allowed for the digital circuit to perform a specified function (e.g., read,
write, etc.) correctly.
S'
Example symbology:
fA
fA
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Unclassified
Description
tc(R), tc(rd)
tc(W)
tAVAV(R)
tAVAV(W)
Read cycle time
Write cycle time
NOTE:
0'
-....
~
R is usually used as the abbreviation for "read"; however, in the case of dynamic memories,
"rd" is used to permit R to stand for RAS.
fA
Disable time (of a three-state output)
C
The time interval between the specified reference points on the input and output voltage waveforms, with
the three-state output changing from either of the defined active levels (high or low) to a high-impedance
(off) state.
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Example symbology:
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Classified
tdis(S)
tdis(W)
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Unclassified
tSHQZ
tWLQZ
Description
Output disable time after chip select (high)
Output disable time after write enable (low)
(')
These symbols supersede the older forms tpvz or tpXZ .
""I
Enable time (of a three-state output)
CD
The time interval between the specified reference points on the input and output voltage waveforms, with
the three-state output changing from a high-impedance (off) state to either of the defined active levels
(high or low).
NOTE:
For memories these intervals are often classified as access times.
Example symbology:
Classified
ten(SL)
Unclassified
tSLQV
Description
Output enable time after chip select low
These symbols supersede the older form tpZV.
3-8
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
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GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTURE
Hold time
The time interval during which a signal is retained at a specified input terminal after an active transition
occurs at another specified input terminal.
NOTES:
1. The hold time is the actual time interval between two signal events and is determined by
the system in which the digital circuit operates. A minimum value is specified that is the
shortest interval for which correct operation of the digital circuit is guaranteed .
2 . The hold time may have a negative value in which case the minimum limit defines the longest
interval (between the release of the signal and the active transition) for which correct
operation of the digital circuit is guaranteed.
..
.
CD
...,::::s
CJ
...,...::::s
en
...,
Example symbology:
Classified
th(D)
th(RHrd)
th(CHrd)
th(CLCA)
th(RLCA)
th(RA)
Unclassified
tWHDX
tRHWH
tCHWH
tCL-CAX
tRL-CAX
tRL-RAX
Description
Data hold time (after write high)
Read (write enable high) hold time after RAS high
Read (write enable high) hold time after CAS high
Column address hold time after CAS low
Column address hold time after RAS low
Row address hold time (after RAS low)
CD
CD
.c
en
...,CO
-
These last three symbols supersede the older forms:
NOTE:
NEW FORM
OLD FORM
th(CLCA)
th(RLCA)
th(RA)
th(ACL)
th(ARL)
th(AR)
CO
C
en
c:
"+=
c:
o
CD
>
c:
o
The from-to sequence in the order of subscripts in the unclassified form is maintained in the
classified form. In the case of hold times, this causes the order to seem reversed from what
would be suggested by the terms.
(J
en
c:
Pulse duration (width)
"e
-t=
The time interval between the specified reference points on the leading and trailing edges of the pulse
waveform.
~
Example symbology:
Classified
tw(W)
twIRL)
CO
en
Unclassified
tWLWHtRLRH
CI)
Description
Write pulse duration
Pulse duration, RAS low
o
G
Refresh time interval
The time interval between the beginnings of successive signals that are intended to restore the level in
a dynamic memory cell to its original level.
NOTE:
The refresh time interval is the actual time interval between two refresh operations and is
determined by the system in which the digital circuit operates. A maximum value is specified
that is the longest interval for which correct operation of the digital circuit is guaranteed.
Example symbology:
Classified
trf
Unclassified
Description
Refresh time interval
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
3-9
GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTURE
Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent active
transition at another specified input terminal.
NOTES:
-
1.
2.
C)
The setup time is the actual time interval between two signal events and is determined
by the system in which the digital circuit operates. A minimum value is specified that is
the shortest interval for which correct operation of the digital circuit is guaranteed.
The setup time may have a negative value in which case the minimum limit defines the
longest interval (between the active transition and the application of the other signal) for
which correct operation of the digital circuit is guaranteed.
0'
(I)
Example symbology:
(I)
Classified
tsu(D)
tsu(CA)
tsu(RA)
Dl
~
-t
3'
Unclassified
tDVWH
tCAV-CL
tRAV-RL
Description
Data setup time (before write high)
Column address setup time (before CAS low)
Row address setup time (before RAS low)
S'
Transition times (also called rise and fall times)
o
o
~
The time interval between two reference points (10% and 90% unless otherwise specified) on the same
waveform that is changing from the defined low level to the defined high level (rise time) or from the defined
high level to the defined low level (fall time).
.
CD
Example symbology:
cc
<
,..
~
Classified
S'
-,..
~
tt
tt(CH)
'tr(C)
tf(C)
(I)
C
Dl
Q)
tJ)
:::r
Valid time
,..
tJ)
...,..
(a)
CD
CD
Unclassified
Description
tCHCH
tCHCH
tCLCL
Transition time (general)
Low-to-high transition time of CAS
CAS rise time
CAS fall time
General
The time interval during which a signal is (or should be) valid.
c
,..(")
c
(b)
...
Output data-valid time
The time interval in which output data continues to be valid following a change of input conditions
that could cause the output data to change at the end of the interval.
CD
Example symbology:
Classified
Unclassified
Description
tv(A)
tAXQX
Output data valid time after change of address.,
This supersedes the older form tpVX.
3-10
TEXAS
'1.!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTURE
PART III - TIMING DIAGRAMS CONVENTIONS
MEANING
TIMING DIAGRAM
INPUT
OUTPUT
SYMBOL
FORCING FUNCTIONS
RESPONSE FUNCTIONS
Must be steady high or low
High-to-Iow changes
permitted
..
Will be steady high or low
Will be changing from high
to low some time during
designated interval
Low-to-high changes
Will be changing from low
permitted
to high sometime during
designated interval
Don't Care
State unknown or changing
.....
Q)
Centerline represents high-
..c
Q)
(Does not apply)
Ul
impedance (off) state.
('0
.....
('0
( I)
The front page of the data sheet begins with a list of key features such as organization, interface,
compatibility, operation (static or dynamic), access and cycle times, technology (N or P channel, silicon
or metal oxide gate), and power. In addition, the top view of the device is shown with the pinout provided.
Next a general description of the device, system interface considerations, and elaboration on other device
characteristics are presented. The next section is an explanation of the device's operation which includes
the function of each pin (i.e., the relationship between each input (output) and a given type of memory).
The functions basically involve starting, achieving, and ending a given type of memory cycle (e.g.,
programming or erasing EPROMs, or reading a memory location).
Augmenting the descriptive text there appears a logic symbol prepared in accordance with ANSI/IEEE Std
91-1984 and IEC Publication 617-12 and explained in Section 11 of this book. Following the symbol is
usually a functional block diagram, a flowchart of the basic internal structure of the device showing the
signal paths for data, addresses, and control signals, as well as the internal architecture. Usually the next
'few pages contain the absolute maximum ratings (e.g., voltage supplies, input voltage, and temperature)
applicable over the operating free-air temperature range. If the device is used outside of these values, it
may be permanently destroyed or at least it would not function as intended. Next, typically, are the
recommended operating conditions, (e.g., supply voltages, input voltages, and operating temperature).
The memory device is guaranteed to work reliably and to meet all data sheet parameters when operated
in accord with the recommended operating conditions and within the specified timing. If the device is
operated outside of these limits (minimum/maximum) it is no longer guaranteed to meet the data sheet
parameters. Operation beyond the absolute maximum ratings can result in catastrophic failures.
The next section provides a table of electrical characteristics over full ranges of recommended operating
conditions (e.g., input and output currents, output voltages, etc.). These are presented as minimum, typical,
and maximum values. Typical values are representative of operation at an ambient temperature of T A =
25°C with all power supply voltages at nominal value. Next, input and output capacitances are presented.
Each pin has a capacitance (whether an input, an output, or control pin). Minimum capacitances are not
given, as the typical and maximum values are the most crucial.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Q
PART IV - BASIC DATA SHEET STRUCTURE
3-11
C
o
'';:=
c
Q)
>
C
o
CJ
C')
c
's
i=
~
('0
(I)
(I)
o
G
GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTURE
The next few tables involve the device timing characteristics. The parameters are presented as minimum,
typical (or nominal), and maximum. The timing requirements over recommended supply voltage range and
operating free-air temperature indicate the device control requirements such as hold times, setup times,
and transition times. These values are referenced to the relative positioning of signals on the timing diagrams,
which follow. The switching characteristics over recommended supply voltage range are device performance
characteristics inherent to device operation once the inputs are applied. These parameters are guaranteed
for the test conditions given. The interrelationship of the timing requirements to the switching characteristics
is illustrated in timing diagrams for each type of memory cycle (e.g., read, write, program.)
-
At the end of a data sheet additional applications information may be provided such as how to use the
device, graphs of electrical characteristics, or other data on electrical characteristics.
Q
0'
(I)
(I)
D)
-<
:=t
3'
:i'
cc
(")
o
::s
<
CD
...0'::s
-...
::s
(I)
c
D)
D)
C/'J
::s'
CD
CD
...
....cC/'J
...c
(')
.
CD
3-12
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
General Information . .
Alternate Source Directories
GlossarylTiming ConventionslData Sheet Structure
Dynamic RAMs . .
I
Dynamic RAM Modules . ,
EPROMslPROMslEEPROMs
VLSI Memory Management Products
.rl
Military Products . .
Applications Information
Quality and Reliability
Logic Symbols
Mechanical Data
ESD Guidelines
..
4-2
TMS4256, TMS4257
262,144-8IT DYNAMIC RANDOM-ACCESS MEMORIES
MAY 1983-REVISED JANUARY 1988
•
262,144 x 1 Organization
•
Single 5-V Power Supply
- 5% Tolerance Required for TMS4256-8
- 10% Tolerance Required for TMS4256-1 0,
-12, -15, and TMS4257-10, -12, -15
•
JEDEC Standardized Pinouts
•
Performance Ranges:
DEVICE
'4256-8
'4256-10
'4257-10
'4256-12
'4257-12
'4256-15
'4257-15
•
•
•
W
RAS
A2
A1
VDD
ACCESS
READ
TIME
TIME
OR
ROW
COLUMN
WRITE
ADDRESS
ADDRESS
CYCLE
(MAX)
(MAX)
(MIN)
80 ns
40 ns
160 ns
± 5%
100 ns
50 ns
200 ns
±10%
120 ns
60 ns
220 ns
±10%
150 ns
75 ns
260 ns
±10%
SD PACKAGE
(TOP VIEW)
(TOP VIEW)
AS
D
AD
ACCESS
N PACKAGE
VSS
CAS
A6 ]1
CAS ]3
AS ]5
Q
3
4
5
6
7
8
A6
A3
A4
A5
A7
W
]7
]9
«
a:
2( Q
4( VSS
6( D
8~ RAS
AD
A2
A1 ]1110~
A7 ]1312~ VDD
14
A4 ]15 i. A5
16C A3
VDD
TOLERANCE
FM PACKAGE
CJ
'ECO
..
C
>
C
(TOP VIEW)
W
RAS
NC
AD
Long Refresh Period ... 4 ms (Max)
A2
Operations of the TMS4256/TMS4257 Can
Be Controlled by TI's SN74ALS2967,
SN74ALS2968, and THCT4502 Dynamic
RAM Controllers
3
4
5
6
7
Q
15
14
13
12
A6
NC
A3
A4
8 9 1011
.-
OI'LO
All Inputs, Outputs, and Clocks Fully TTL
Compatible
PIN NOMENCLATURE
•
3-State Unlatched Outputs
AO-AS
Address Inputs
•
Common I/O Capability with "Early Write"
Feature
CAS
Column-Address Strobe
D
Data In
NC
No Connection
o
Page Mode ('4256) or Nibble-Mode ('4257)
•
Low Power Dissipation
•
RAS-Only Refresh Mode
•
Hidden Refresh Mode
•
CAS-Before-RAS Refresh Mode
•
Available with MIL-STD-883B Processing
and L(O °C to 70°C), E( - 40°C to 85 DC), or
S( - 55°C to 100°C) Temperature Ranges
(SMJ4256, with 10% Power Supply)
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
spacifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
en
:2:
Q
Data Out
RAS
Row-Address Strobe
VDD
5-V Power Supply
VSS
Ground
W
Write Enable
Copyright © 1983, Texas Instruments Incorporated
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-3
TMS4256, TMS4257
262,144·8IT DYNAMIC RANDOM·ACCESS MEMORIES
description
The TMS4256 and TMS4257 are high-speed, 262, 144-bit dynamic random-access memories, organized
as 262,144 words of one bit each. They employ state-of-the-art SMOS (scaled MOS) N-channel doublelevel polysilicon/polycide gate technology for very high performance combined with low cost and improved
reliability.
The '4256-8 with a 5% voltage tolerance has a maximum RAS access time of 80 ns. The
'4256/,4257-10, -12, and -15 with 10% voltage tolerances have maximum RAS access times of
100 ns, 120 ns, and 150 ns, respectively.
-
New SMOS technology permits operation from a single 5-V supply, reducing system power supply and
decoupling requirements, and easing board layout. 100 peaks are 125 mA typical, and a - 1 V input voltage
undershoot can be tolerated, minimizing system noise considerations.
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All address and data-in lines
are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The '4256 and '4257 are offered in 16-pin plastic dual-in-line, 16-pin plastic zig-zag in-line (ZIP), and 18-lead
plastic chip carrier packages. They are guaranteed for operation from 0 ac to 70 ac. The dual-in-line package
is designed for insertion in mounting-hole rows on 7,62-mm (300-mil) centers.
operation
address (AO through A8)
Eighteen address bits are required to decode 1 of 262,144 storage cell locations. Nine row-address bits
are set up on pins AO through A8 and latched onto the chip by the row-address strobe (RAS). Then the
nine column-address bits are set up on pins AO through A8 and latched onto the chip by the column-address
strobe (CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar
to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a
chip select, activating the column decoder and the input and output buffers.
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects
the read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard
TTL circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When
W goes low prior to CAS, data out will remain in the high-impedance state for the entire cycle, permitting
common I/O operation.
data in (D)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling
edge of CAS or W strobes data into the on-chip data latch. This latch can be driven from standard TTL
circuits without a pull-up resistor. In an early write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-modifywrite cycle, CAS will already be low, thus the data will be strobed in by W with setup and hold times
referenced to this signal.
data out (a)
The three-state output buffer provides direct TTL compatibility (no pull-up resistor required) with a fanout
of two Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance
(floating) state until CAS is brought low. In a read cycle the output goes active after the access time interval
talC) that begins with the negative transition of CAS as long as ta(R) is satisfied. The output becomes
valid after the access time has elapsed and remains valid while CAS is low; CAS going high returns it to
a high-impedance state. In a read-modify-write cycle, the output will follow the sequence for the read cycle.
4-4
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TeXAS 77001
TMS4256, TMS4257
262,144·81T DYNAMIC RANDOM·ACCESS MEMORIES
refresh
U)
:!
A refresh operation must be performed at least once every four milliseconds to retain data. This can be
achieved by strobing each of the 256 rows (AO-A7). A normal read or write cycle will refresh all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
thus conserving power as the output buffer remains in the high-impedance state.
CAS-before-RAS refresh
«a:
(,)
Os
CO
..
C
The CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS (see parameter tCLRL) and
holding it low after RAS falls (see parameter tRLCHR). For successive CAS-before-RAS refresh cycles,
CAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated
internally.
hidden refresh
>-
C
Hidden refresh may be performed while maintaining valid data at the output pin. This is accomplished by
holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to
a CAS-before-RAS refresh cycle. The external address is also ignored during the hidden refresh cycles.
The data at the output pin remains valid up to the maximum CAS low pulse duration, tw(CL).
page mode (TMS4256)
Page-mode operation allows effectively faster memory access by keeping the same row address and strobing
random column addresses onto the chip. Thus, the time required to set up and strobe sequential row
addresses for the same page is eliminated. The maximum number of columns that can be addressed is
determined by tw(RL), the maximum RAS low pulse duration.
nibble mode (TMS4257)
Nibble-mode operation allows high-speed serial read, write, or read-modify-write access of 1 to 4 bits of
data. The first bit is accessed in the normal manner with read data coming out at talC) time. The next
sequential nibble bits can be read or written by cycling CAS while RAS remains low. The first bit is
determined by the row and column addresses, which need to be supplied only for the first access. Column
A8 and row A8 (CA8, RA8) provide the two binary bits for initial selection of the nibble addresses.
Thereafter, the falling edge of CAS will access the next bit of the circular 4-bit nibble in the following
sequence:
~-----~( 0 , 0 ) - - - - - - -( 0 , 1 ) - - - - - - -( 1 , 0 ) - - - - -.....(1,1
)-----.....,
In nibble-mo~e, all normal memory operations (read, write, or read-modify-write) may be performed in any
desired combination.
power-up
To achieve proper device operation, an initial pause of 200 JLs is required after power up, followed by a
minimum of eight initialization cycles.
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-5
TMS4256, TMS4257
262,144-8IT DYNAMIC RANDOM-ACCESS MEMORIES
logic symbol t
C
<::::J
AO
A1
A2
A3
D)
3
t;'
RAM 256K X 1
(5)
";""';'---12009/21 DO
(7)
(6)
(12)
A __
O_
(11)
A4
(10)
A5
(13)
A6
(9)
A7
(1)
A8
~
..
s:
(I)
RAS
262.143
(4)
CAS (15)
23C22
_
(3)
W (2)
0
(14) Q
All
tThis symbol is in accordance with ANSI/IEEE Std. 91-1084 and IEC Publication 617-12.
The pin numbers ~hown are for the 16-pin dual-in-line package.
, ,
functional block diagram
RAS
J
.1
CAS
:---+AD
AI
A2
A3
A4
A5
ROW
DECODE
r--
~
~
-
32K ARRAY
32K ARRAY
ROW
DECODE
32K ARRAY
E
ROW
DECODE
32K ARRAY
I
~~L~'L
ROW
L
4-6
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
I/O
BUFFERS
I of 4
SELEC·
TlON
32K ARRAY
256 SENSE AMPS
256 SENSE AMPS
32K ARRAY
. ,.
256 SENSE AMPS
ROW
DECODE
COLUMN DECODE
rt
1
A6
A7
AS
256 SENSE AMPS
I--
32K ARRAY
(8)
I
~t
(8)
COLUMN
ADDRESS
BUFFERS
t
TIMING AND CONTROL
32K ARRAY
ROW
ADDRESS
BUFFERS
W
HOUSTON. TEXAS 77001
..
i"
r---rn-IN
REG
HJ[rOUT
REG
Q
TMS4256, TMS4257
262,144·811 DYNAMIC RANDOM·ACCESS MEMORIES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
Voltage range for any pin, including VOO supply (see Note 1) .................... - 1 V to 7 V
Short circuit output current .................................................. 50 mA
Power dissipation ............................................................ 1 W
Operating free-air temperature range ....................................... 0 °C to 70°C
Storage temperature range .......................................... - 65°C to 1 50°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
VOO Supply voltage (,4256/,4257-10, -12, -15)
VOO Supply voltage ('4256-8)
VSS
Supply voltage
VIH
High-level input voltage
VIL
TA
Low-level input voltage (see Note 2)
4.5
4.75
2.4
-1
0
Operating free-air temperature
MAX
5
5.5
5 5.25
0
6.5
0.8
70
NOM
UNIT
V
-
V
V
V
V
DC
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as maximum, is used in this data sheet
for logic voltage levels only.
TEXAS •
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4-7
TMS4256. TMS4257
262.144·8IT DYNAMIC RANDOM·ACCESS MEMORIES
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
PARAMETER
-
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
1001
TEST
TMS4256-8
CONDITIONS
IOH = -5 mA
10L = 4.2 mA
MIN
MAX
2.4
VI = 0 V to 6.5 V, VOO = 5 V,
All other pins = 0 V to 6.5 V
Vo = 0 V to 5.5 V,
VOO = 5 V, CAS high
Average operating current
tc = minimum cycle,
during read or write cycle
Output open
TMS4256-10
TMS4257-10
MIN
UNIT
MAX
2.4
V
0.4
0.4
V
±10
±10
p.A
±10
±10
p.A
70
70
mA
4.5
4.5
mA
70
58
mA
60
50
mA
45
mA
After 1 memory cycle,
1002
Standby current
RAS and CAS high,
Output open
tc = minimum cycle,
1003
Average refresh current
RAS cycling, CAS high,
Output open
1004
Average page-mode current
tc(P) = minimum cycle,
RAS low, CAS cycling,
Output open
tc(N) = minimum cycle,
1005
Average nibble-mode current
RAS low, CAS cycling,
Output open
PARAMETER
TMS4256-12
TEST
CONDITIONS
VOH
High-level output voltage
IOH = -5 mA
VOL
Low-level output voltage
IOL = 4.2 mA
Input current (leakage)
VI = 0 V to 6.5 V, VOO = 5 V,
All other pins = 0 V to 6.5 V
II
10
1001
Output current (leakage)
TMS4257-12
MIN
MAX
2.4
Vo = 0 V to 5.5 V,
VOO = 5 V, CAS high
Average operating current
tc = minimum cycle,
during read or write cycle
Output open
TMS4256-15
TMS4257-15
MIN
UNIT
MAX
2.4
V
0.4
0.4
V
±10
±10
p.A
±10
±10
p.A
65
60
mA
4.5
4.5
mA
53
48
mA
45
40
mA
40
35
mA
After 1 memory cycle,
1002
Standby current
RAS and CAS high,
Output open
tc = minimum cycle,
1003
Average refresh current
RAS cycling,
CAS high,
Output open
tc(P) = minimum cycle,
1004
Average page-mode current
RAS low, CAS cycling,
Output open
tc(N) = minimum cycle,
1005
Average nibble-mode current
RAS low, CAS cycling,
Output open
4-8
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4256, TMS4257
262,144·BIT DYNAMIC RANDOM·ACCESS MEMORIES
capacitance over recommended supply voltage range and operating free-air temperature range,
f = 1 MHz
MAX
PARAMETER
Cj(A)
Input capacitance, address inputs
5
pF
Cj(D)
Input capacitance, data input
5
pF
Ci(RC) Input capacitance strobe inputs
Cj(W) Input capacitance, write enable input
5
pF
7
pF
7
pF
Co
Output capacitance
U)
:E
-
C
switching characteristics over recommended supply voltage range and operating free-air temperature
range
PARAMETER
ALT.
TEST CONDITIONS
SYMBOL
TMS4256-8
MIN
MAX
TMS4256-10
TMS4257-10
MIN
UNIT
MAX
ta(C)
Access time from CAS
tRLCL ~ MAX, CL = 100 pF,
Load = 2 Series 74 TTL gates
tCAC
40
50
ns
ta(R)
Access time from RAS
tRLCL = MAX, CL = 100 pF,
Load = 2 Series 74 TTL gates
tRAC
80
100
ns
Output disable time
CL
after CAS high
Load
30
ns
tdis(CH)
=
ta(R)
tdis(CH)
Access time from CAS
=
tOFF
2 Series 74 TTL gates
ALT.
TEST CONDITIONS
PARAMETER
ta(C)
100 pF,
SYMBOL
0
Load = 2 Series 74 TTL gates
Access time from RAS
Output disable time
CL
after CAS high
Load
=
TMS4256-15
TMS4257-12
TMS4257-15
MIN
TEXAS
UNIT
MAX
75
ns
tRAC
120
150
ns
30
ns
-8!p
INSTRUMENTS
POST OFFICE BOX 1443 •
MIN
60
tOFF
2 Series 74 TTL gates
MAX
tCAC
100 pF,
=
a
TMS4256-12
tRLCL ~ MAX, CL = 100 pF,
tRLCL = MAX, CL = 100 pF,
Load = 2 Series 74 TTL gates
20
HOUSTON, TEXAS 77001
a
30
liiiiii
IBitIII
a
4-9
TMS4256, TMS4257
262,144·811 DYNAMIC RANDOM·ACCESS MEMORIES
timing requirements over recommended supply voltage range and operating free-air temperature range
ALT.
PARAMETER
-
SYMBOL
TMS4256-8
MIN
MAX
TMS4256-10
TMS4257-10
MIN
UNIT
MAX
tc(P)
Page-mode cycle time (read or write cycle)
tpc
70
100
ns
tc(PM)
Page-mode cycle time (read-modify-write cycle)
tPCM
95
135
ns
tc(rd)
Read cycle time t
tRC
200
ns
tc(W)
Write cycle time
twc
160
160
200
ns
tc(rdW)
Read-write/read-modify-write cycle time
tRWC
185
235
ns
tw(CH)P
Pulse duration, CAS high (page mode)
tcp
20
40
ns
tw(CH)
Pulse duration, CAS high (non-page mode)
tCPN
25
25
tw(CL)
Pulse duration, CAS low *
tCAS
40
tw(RH)
Pulse duration, RAS high
tRP
70
twiRL)
tw(W)
Pulse duration, RAS low §
80
Write pulse duration
tRAS
twp
tt
Transition times (rise and fall) for RAS and CAS
tT
3
tsu(CA)
Column-address setup time
tASC
0
tsu(RA)
tsu(D)
Row-address setup time
tASR
tDS
0
0
ns
Data setup time
0
0
ns
tsu(rd)
Read-command setup time
tRCS
0
0
ns
twcs
0
0
ns
ns
Early write-command setup time
tsu(WCL)
before CAS low
10,000
50
10,000
100
ns
10,000
ns
90
20
10,000
3
0
ns
ns
30
50
ns
50
ns
ns
tsu(WCH)
Write-command setup time before CAS high
tCWL
20
30
tsu(WRH)
Write-command setup time before RAS high
tRWL
20
30
ns
th(CLCA)
Column-address hold time after CAS low
tCAH
15
15
ns
th(RA)
Row-address hold time
tRAH
15
15
ns
th(RLCA)
Column-address hold time after RAS low
tAR
55
65
ns
th(CLD)
Data hold time after CAS low
tDH
20
30
ns
th(RLD)
Data hold time after RAS low
tDHR
60
80
ns
th(WLD)
Data hold time after W low
tDH
20
30
ns
th(CHrd)
Read-command hold time after CAS high
tRCH
0
0
ns
th(RHrd)
Read-command hold time after RAS high
tRRH
10
10
ns
th(CLW)
Write-command hold time after CAS low
tWCH
20
30
ns
th(RLW)
Write-command hold time after RAS low
tWCR
65
80
ns
Continued next page.
NOTE 3: Timing measurements are referenced to VIL max and VIH min.
t All cycle times assume tt = 5 ns.
*In a read-modify-write cycle, tCLWL and tsu(WCH) must be observed. Depending on the user's transition times, this may require additional
CAS low time (tw(CL)). This applies to page-mode read-modify-write also.
§In a read-modify-write cycle, tRLWL and tsu(WRH) must be observed. Depending on the user's transition times, this may require additional
RAS low time (tw(RL)).
4-10
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4256, TMS4257
262,144·8IT DYNAMIC RANDOM·ACCESS MEMORIES
timing requirements over recommended supply voltage range and operating free-air temperature range
(continued)
ALT.
SYMBOL
PARAMETER
TMS4256·8
MIN
MAX
UNIT
(,)
0
0
ns
tRSH
40
50
ns
tCHR
20
20
ns
tCSH
tCHRL
Delay time, CAS high to RAS low
tCRP
tCLRH
Delay time, CAS low to RAS high
tRLCHR
Delay time, RAS low to CAS high'
80
TMS4257·10
MIN
MAX
ns
Delay time, RAS low to CAS high
tCLRL
Delay time, CAS low to RAS low'
tCSR
10
10
ns
tRHCL
Delay time, RAS high to CAS low'
tRPC
0
0
ns
tCWD
40
50
ns
tRCD
25
tRWD
80
Delay time, CAS low to W low
tCLWL
(read-modify-write cycle only)
«a:
TMS4256·10
100
tRLCH
t/)
~
Os
ca
c:
>
C
iiii
Delay time, RAS low to CAS low
tRLCL
(maximum value specified only
40
25
50
ns
4
ms
to guarantee access time)
tRLWL
Delay time, RAS low to W low
(read-modify-write cycle only)
trf
Refresh time interval
tREF
100
4
ns
Continued next page.
NOTE 3: Timing measurements are referenced to VIL max and VIH min.
, CAS-before-RAS refresh only.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-11
TMS4256. TMS4257
262.144·8IT DYNAMIC RANDOM·ACCESS MEMORIES
timing requirements over recommended supply voltage range and operating free-air temperature range
(continued)
o
'<
:::J
DI
ALT.
PARAMETER
3
C:;"
jJ
..
l>
s:
til
SYMBOL
TMS4256-12
TMS4256-15
TMS4257-12
TMS4257-15
MIN
MAX
MIN
UNIT
MAX
120
160
145
190
220
220
260
260
260
305
ns
tcp
50
60
ns
Pulse duration, CAS high (non-page mode)
tCPN
25
25
tw(CL)
Pulse duration, CAS lowt
tCAS
60
tw(RH)
Pulse duration, RAS high
tRP
90
tw(RL)
Pulse duration, RAS low §
tw(W)
Write pulse duration
tRAS
twp
tt
Transition times (rise and fall) for RAS and CAS
tT
tsu(CA)
Column-address setup time
tASC
tsu(RA)
Row-address setup time
tASR
tsu(D)
Data setup time
tDS
tsu(rd)
Read-command setup time
tsu(WCL)
tc(P)
Page-mode cycle time (read or write cycle)
tpc
tc(PM)
Page-mode cycle time (read-modify-write cycle)
tpCM
tc(rd)
Rilad cycle time t
tRC
tc(W)
Write cycle time
twc
tc(rdW)
Read-write/read-modify-write cycle time
tRWC
tw(CH)P
Pulse duration, CAS high (page mode)
tw(CH)
10,000
75
ns
ns
ns
ns
ns
10,000
100
ns
ns
120
30
10,000
150
45
10,000
50
3
0
0
0
0
50
tRCS
3
0
0
0
0
Early write-command setup time before CAS low
twcs
0
0
ns
tsu(WCH)
Write-command setup time before CAS high
tCWL
35
45
ns
tsu(WRH)
Write-command setup time before RAS high
tRWL
35
45
ns
th(CLCA)
Column-address hold time after CAS low
tCAH
Row-address hold time
tRAH
25
15
ns
th(RA)
20
15
th(RLCA)
Column-address hold time after RAS low
tAR
80
100
ns
th(CLD)
Data hold time after CAS low
tDH
30
45
ns
th(RLD)
Data hold time after RAS low
tDHR
90
120
ns
th(WLD)
Data hold time after W low
tDH
30
45
ns
th(CHrd)
Read-command hold time after CAS high
tRCH
0
0
ns
th(RHrd)
Read-command hold time after RAS high
tRRH
10
10
ns
th(CLW)
Write-command hold time after CAS low
tWCH
30
45
ns
th(RLW)
Write-command hold time after RAS low
tWCR
90
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
Continued next page.
NOTE 3: Timing measurements are referenced to VIL max and VIH min.
t All cycle times assume tt = 5 ns.
tin a read-modify-write cycle, tCLWL and tsu(WCH) must be observed. Depending on the user's transition times, this may require additional
CAS low time (tw(CL)). This applies to page-mode read-modify-write also.
§In a read-modify-write cycle, tRLWL and tsu(WRH) must be observed. Depending on the user's transition times, this may require additional
RAS low time (tw(RL)).
4-12
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS4256, TMS4257
262,144-81T DYNAMIC RANDOM-ACCESS MEMORIES
timing requirements over recommended supply voltage range and operating free-air temperature range
(concluded)
TMS4256-12
ALT.
PARAMETER
TMS4257-12
SYMBOL
tRLCH
Delay time, RAS low to CAS high
tCSH
MAX
MIN
120
TMS4257-15
MIN
UNIT
MAX
(,)
150
ns
tCHRL
Delay time, CAS high to RAS low
tCRP
0
0
ns
Delay time, CAS low to RAS high
tRSH
60
75
ns
tRLCHR
Delay time, RAS low to CAS high'
tCHR
25
30
ns
tCLRL
Delay time, CAS low to RAS low'
tCSR
10
20
ns
tRHCL
Delay time, RAS high to CAS low'
tRPC
0
0
ns
tCLWL
Delay time, CAS low to W low (read-modify-write cycle only)
tCWD
60
70
ns
tRCD
25
120
Delay time, RAS low to CAS low (maximum value specified
only to guarantee access time)
tRLWL
Delay time, RAS low to W low (read-modify-write cycle only)
tRWD
trf
Refresh time interval
tREF
60
«a::
TMS4256-15
tCLRH
tRLCL
en
:E
25
75
ns
4
ms
145
4
"sco
c::
>-
C
iiii
ns
NOTE 3: Timing measurements are referenced to VIL max and VIH min.
'CAS-before-RAS refresh only.
NIBBLE-MODE CYCLE
switching characteristics over recommended supply voltage range and operating free-air temperature
range
PARAMETER
ta(CN) Nibble-mode access from CAS
TMS4257-10
ALT.
MIN
SYMBOL
MAX
TMS4257-12
MIN
25
tNCAC
MAX
TMS4257-15
MIN
MAX
40
30
UNIT
ns
timing requirements over recommended supply voltage range and operating free-air temperature range
PARAMETER
tc(N)
Nibble-mode cycle time
TMS4257-10
ALT.
MIN
SYMBOL
write cycle time
CAS low to RAS high
CAS to
W delay
CAS low
tNRMW
70
85
105
tNRSH
25
30
40
tNCWD
20
25
30
tNCAS
25
30
40
tNCP
15
20
25
tNCWL
20
25
35
Nibble-mode pulse duration,
tw(CHN)
CAS high
Nibble-mode write command
tsu(WCHN)
setup before CAS high
TMS4257-15
MIN
tNC
Nibble-mode pulse duration,
tw(CLN)
MAX
75
Nibble-mode delay time,
tCLWLN
MIN
60
Nibble-mode delay time,
tCLRHN
TMS4257-12
50
Nibble-mode read-modifytc(rdWN)
MAX
MAX
UNIT
ns
NOTE 3: Timing measurements are referenced to VIL max and VIH min.
~
TEXAS
INSTRUMENTS
POST. OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-13
TMS4256, TMS4257
262,144·8IT DYNAMIC RANDOM·ACCESS MEMORIES
read cycle timing
c
-<
:::::I
,a
3
( (
... a _ - - - - -
m
c;'
RAS
..
tclrd)
twIRL)
.;
------a-ll
----.IN---------------~Y:I '-~ I--
tt
I.
tCLRH
•
(
twlRH)
~'-_____ ::~
---i
(~, tCHRL----t
r--:- tt
----!!-!~.~======;-}~ii-- tRLcH----~l tiL
( l-I
tRLCL
( (
---Jr------
_----I
twlCL) --------.
--t
I(
---f
t-t-
I'\:1O._ _ _ _ _ _ _~j(1
~th(RLCA)~
I-- th(RA)
I
--1 i-f- tsu(C~)
II~
,
tsu(RA)
I
I
I'
I
I
HI
tw(CH)
(
, - - - - - - - - VIH
/\,/\,,/\.A/\./\:lo.'
AO-AB
I
i·
7
•
i
th(CLCA)
tsulrd)
I
I
t--ta(R)
ta(C)
-----f
I
a!
........- -.....-f.II
r------~
Q - - - - - - - - HI-Z-------«
VALID
tdislCH)
)>---------
VOH
VOL
4-14
-IJ.J
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS4256, TMS4257
262,144·811 DYNAMIC RANDOM·ACCESS MEMORIES
early write cycle timing
tc(W)
I.
I
I I.
.1
twIRL)
-------II}t::
1 I
1
r--
~~_ _ _ __
I
Jif
RAS.
--, r--
I
1
I
tt
' •
tCLRH
1
tilLCL
I I
~
,-
1 I-
!
"
~
.;
tw(CL)
• I
X
VIL
1
tCHRL -----t
tt
l
ro
VIH
1 : I
1
l i t
1
1
w(CH)----,
1
1
I
I
VIL
r-r-
..
2@§§§$I%1~~!~""'-------V'H
Itsu(WCL) ~ 1
1
1 1
1
I I
tsu(WCHI
tsu(WRHI
i_
:th!RLWI
1
-
VIH
:-r...+
-I:~______~
1; :
\""'___
----'
........
-J
tsu(RA)
:
I
' - - - th(RLCAI..L.--..r
I
I
1 1_
.1 th(CLC
r-- th(RA) I 1
1
AI
I .....,
1
1
I
- J r-!- tsu(CA)
' : I .
1
1
1
COLUMN
AO-AB
~~v...z:.y\: 1
~7'0"!~~~;"7'1~~~~~~:
~
l
t--- tw(RH)--J
I
tRLCH
~
I
:
1
r--
th(CLW)
I
I
I
• 1
1
1
"'---------VIL
• 1
• II
----'
A/'o./\J'VV'V'V"VV
DON'T CARE;; J\./'V'VV'\/\.J"V\.f'V'\.
~
~~~~~~~~~-~------~~~~~~~~~~QQ~~~~~~VIL
I
I
"'1--;--111-- tw(W)
• •
J.....- th(CLDI' ~
D~
~'n"t"7'I:'7't'DO~~I"t"7'T~CrnAR'7't'E~'""'
_..;I[~ffiI~§§§§QlW :::
F-1:..--_VA_Ll_D_DA_T_A
1
I
I.
Q
--,
r--
tsu(D)
th(RLD)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HI-Z
TEXAS
-------------------------
'1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
VOH
VOL
4-15
TMS4256, TMS4257
262,144·811 DYNAMIC RANDOM·ACCESS MEMORIES
write cycle timing
c
-<
::::s
"
m
tc(W)
I I.
3
L!
(;'
:
twiRL) - - - - - -.......-11
Iif
I
i i~'----------------~}
rI•
·~i t--
~
..
tt
s:
o
I
I
r---
I'
I
tCLRH - - -......
tRLCL
~
::k
V,H
1"'------
V,L
tW(RH)--i
H-t'CHRL-----f
1-
-----f I I
--' H- tt
I
_ _ _~WI~-====~--;---tRLCH-----·"'1
• I
IX
II
--r
I I
I-j-
V!~-~"'k.
~ I I
1\
I
I
tsu(RA)
I I---I ---,
I I I
I
tw(CL)
_.
th(RLCAI-+-----l
I 1
I
I-- th(RA) I I •I
th(CLCA)
tsu(C~)
---!
I
I I
I
I i
I I
I (
H---I
w
I '----
V,L
I
(CH)
---..-I
--.
I
/'i7'r:7'V~"'V"C~':]'ij~~,~,~,,,7.'?',,';7'''~'''lU',..--------- VIH
AO-AS
I
I-
IN
' - - - - - - - - - V,L
I--- tsu(WCH) ~ I I
I
I I
I - - - tsu(WRH) ----t-;
I
I
th(RLW)
I
I
I
-I
!-.--i- th(CLW) --l
""~"""''''''''''''''''''''''D'''O'7'rN'''''T'''''''CA'''R'''E'''''''''''''''''''''''h1~. . . ...n""""''''''''''''''''''D'''O'''N'''''''T'''C''''A''''R'''E'''~'''''''''''''''''''''''''''''''''' V,H
~
om
I I
I
I I t-
:i'
'7'!'"~~g~~""'ffiM'rC"7't""~~RE~~nn
~
----1
tw(W)
th(WLD) --ooof
I
~~~~"'7M"t""l""'i~no'I:0""'·~~*~;no'I:E~"?n"n~"'7M"t""l~VIH
VALID DATA
-rr---
I
1-----1-- tdis(CH)
I
.1\
t-- tsu(D)
Q - - - - - - HI-Z
----------__________
VOH
-
VOL
tThe enable time (ten) for a write cycle is equal in duration to the access time from CAS (ta(C)) in a read cycle; but the active levels at
the output are invalid.
4-16
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS4256, TMS4257
262,144·8IT DYNAMIC RANDOM·ACCESS MEMORIES
read·write/read·modify·write cycle timing
t/)
tc(rdW)
;•
I I.
twIRL)
----liN
--t
I
I
I
I
I
II-- tt
~
I
tRLCL
I-
I-j-
•
I' •
----l
th(RLCAi
I
a::
~
1\. .----- ::~
CJ
's
• I t-- tw(RH) ----!
I ,
- - - - l f-t-I tCHRL ----t
I
t
w(CLl
CO
*
r:::
>
C
tt
! !i
-+1-------"::lI.1;.
--J
tRLCH
i
11I I
1/:";
I L-..........!
tsuIRA)
Y:
~
tCLRH
r--
"}
I
• :
II \. . ---
I
I I I
H---
tw(CH)
I I I
I I
VIL
iii
---I
r--------- VIH
AO-AS
I
I
I
I
W
:
I
E~
,-
i
tCLWL
i
I
I
~
I
I
I
I
Q -----ili----HI-Z
II
I-
1 r-
N
I
,,!
tRLWL
I
D
' - - - - - - - - - VIL
I i .
I I !
I
I · · I tsu(WCH)
t su (rd)-4---i
tsu(WRH)
-H
t-tw(W)-i
I
I
II
--11-+
~h~~"l"n"r'7'g~r7'I:*~{'f'M!g~r7'I:Rl~~~'?I"7'r7~:::
tsu(D)
II~
~!~~ j~~1g~K~ VIH
~I
I
VIL
I
th(WLD)
--J-----i
I
I
1..- - - - -+-1 tdis(CH)
I
I
I
(
I
t-taIR)
I
,
VALID DATA
I
ta(C)
j>----------
VOH
VOL
----t
-!
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-17
I
f"
....
slIII"l:I ::l!WRUAa
co
'C
Q)
ee
~
3
0
C.
~
(;
twIRl)
~I
RAS
: \.
r--- tRLCH -------!
1 1
I I-~
-,
CAS
~~
~~
z
u5~
:•
tRLCL
,-tt
~
-W
tc(P)
I
1 1
1--1
! 1
--I
1I
11
I
I
1
1
I
~ ~ th(CLCA)
rth(RA) 1
I
I
~ r-+- ~su(CA)
1
I
I-- tCLRH
I
~ tw(CH)P
I.
-_q_L tsu(RA)
I I- thIRLCA)~
I
tw(RH)
tW(CL~ tt !
1 1I
1
1 1
ViI
~tW(Cl)"1
~I
!
1
I I r- th(CLC~)1
II
-r-l
!1
I 1
-r-t
I
1
1
VIL
C
CD
s::
n
1
~
$
--I W t
I' 1 hleH'dI
w~gg~:gr
!
I
t - - - ta(R)
ta(C)
Q
~'- ~t-t tsu(rd)
~
I
!V
!
~
r----r- tdis(CH)
•
-----;
i..I
{
l I-----t-
VALlD}----{
~ i-!-I tsu(rd)
1 '-
- , ithleH,,"
!
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262,144·BIT DYNAMIC RANDOM·ACCESS MEMORY
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TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
0
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TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-25
C
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4-26
TMS4461
262,144-BIT MULTIPORT VIDEO RAM
JULY 1986-REVISED FEBRUARY 1988
0
65,536 x 4 Organization
0
Dual-Port Accessibility - Four II0s for
Sequential Access, Four II0s for Random
Access
0
One Serial Data Register Built into Each
Serial 1/0 for Sequential-Access Applications
0
Designed for Video and Non-Video
Applications
Fast Serial Ports ... 25-MHz Shift Rate
0
Mid-Scan Load - Serial Data Streams
Uninterrupted by Register Reload
(TOP VIEW)
~
SD01
CJ
SD02
D01
A6
0
Supported by TI's TMS34061 Video System
Controller and TMS34010 Graphics System
Processor (GSP)
C
15
PIN NOMENCLATURE
AO-A7
3-State Serial II0s Allow Easy Multiplexing
of Video Data Streams
Address Inputs
CAS
Column-Address Strobe
DQ1-DQ4
Random-Access Data In!
Data-OutlWrite-Mask Bit
Maximum Access Time from RAS
... 120 ns
Long Refresh Period ... 4 ms
..
C
>
19
Random-Access Port Is Compatible with the
TMS4464, 64K x 4 DRAM
0
CO
11
A2
AO
0
Minimum Cycle Time (Read or
Write) ... 220 ns
"s
17
TRG as Output Enable Allows Direct
Connection of DQ and Address Lines to
Simplify System Design
0
en
~
0
0
SO PACKAGE
(TOP VIEW)
13
0
0
N PACKAGE
RAS
Row-Address Strobe
SC
Serial Data Clock
SDQ1-SDQ4
Serial Data In!Data Out
'STI
Serial Enable
TRG
Transfer Register!
Q Output Enable
0
Low Refresh Overhead Time . . . As Low As
1.3% of Total Refresh Period
0
All Inputs, Outputs, Clocks Fully TTL
Compatible
0
3-State Unlatched Random-Access Outputs
0
Common Random-Access 1/0 Capability
with "Early Write" Feature
0
High-Speed Page-Mode Operation for Faster
Access
VDD
5-V Supply
VSS
Ground
WE
Write-Mask Select!
Write Enable
•
CAS-Before-RAS Refresh and Hidden
Refresh Modes
o
Low-Power Dissipation
•
24-Pin, 400-Mil Dual-in-line Package or
24-Pin, Zig-Zag In-line Package (ZIP)
description
The TMS4461 is a high-speed dual-ported 65,536 x4 bit dynamic random-access memory with on-chip
data registers. The random-access port makes the memory look as if it is organized as 65,536 words of
four bits each, like the TMS4464. The sequential-access port is interfaced to four internal 256-bit dynamic
data registers, which make the memory look as if it is organized as 256 four-bit words of up to 256 bits
each that are accessed serially.
The 256K Multiport Video RAM employs state-of-the-art scaled NMOS, double-level polysiliconipolycide
gate technology for very high performance combined with low cost and improved reliability.
PRODUCTION DATA documents contain information
current as of publication date. Products conform
to specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1986, Texas Instruments Incorporated
TEXAS
-IJ}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-27
TMS4461
262,144·8IT MULTIPORT VIDEO RAM
The TMS4461 features full asynchronous dual-port accessibility except when transferring data between
the data register and the random-access memory.
c
<:;:,
Refresh period is 4 milliseconds, and during this period each of the 256 rows must be strobed with RAS
in order to retain data. CAS can remain high during the refresh sequence to conserve power. Note that
the transfer of a row of data from the memory array to the data register also refreshes that particular row.
CAS-before-RAS and hidden refresh modes are also available.
Dl
3CiO
~
..
s:
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All inputs and outputs, including clocks, are compatible with Series 74 TTL. All address lines and data
in are latched on-chip to simplify system design. All data outs are unlatched to allow greater system
flexibility .
The 256K Multiport Video RAM is offered in a 24-pin dual-in-line plastic package (N suffix) and is guaranteed
for operation from 0 °C to 70°C. The package is designed for insertion in mounting-hole rows on 10, 16-mm
(400-mil) centers.
The TMS4461 Multiport Video RAM is also offered in a 24-pin zig-zag plastic package (SO suffix),
guaranteed for operation from OOC to 70°C.
functional block diagram
DQ1
DQ2
DQ3
DQ4
256-BIT
DATA REGISTER
256-BIT
DATA REGISTER
256-BIT
DATA REGISTER
256-BIT
DATA REGISTER
AO-A 7 ---'sO-/-....+-_--i
RAS - -....-r-----i
CAS - -....-'-----i
DRAM
LOGIC
W E - -....f-----i
TRG - -...._*---1
S C - -....~---t
SG - -.....'-----i
SERIAL
LOGICI
COUNTER
VDD~
VSS ------.,
1
I
I
I
L_~
_________________________________________ 1
SDQ2
SDQ1
4-28
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
SDQ3
SDQ4
TMS4461
262,144-8IT MULTIPORT VIDEO RAM
random port to serial port interface
The TMS4461 Multipart Video RAM consists of a 64K x 4 DRAM port and a 256 x 4 serial port. Each
of the four random (DRAM) I/Os is interfaced to a 256-bit data register that can be loaded with 256 bits
in parallel from any row in that I/O channel's memory then read out sequentially starting from one of 256
selectable locations along the data register. Conversely, each of the four data registers can be loaded with
data serially from the serial input (SO) and subsequently transferred, 256 bits in parallel, into any row of
memory for each respective DRAM I/O channel.
-f~w256
ROWS
ROW
l
ICOl
COLI
I 0
255 I
('0
..
0
MEMORY ARRAY
65,536 BITS
1.~_ L..-_ _ _ _ _ _ _ _ _r -_ _ _
65,..;._5_35-1
SG-.....- - - ,
CAS-.----...J
SDQ __-.----------------------------------------------~
random-access address space to sequential-address space mapping
The 256 bits in each of the four data registers correspond to the 256 column locations of each of the
four random I/Os. Data can be read out of the registers starting at any of the 256 data register bit locations.
This tap location is selected by addresses A 7 through AD on the falling edge of CAS during a transfer
cycle between the memory array and the data registers. All registers are read out starting from the selected
tap point proceeding from the least-significant bits to the most-significant bits. The four data registers
are configured as circular data registers when reading their contents to the serial outputs. After the mostsignificant bit (bit 255) is read out of each register, the next bit read will be 00 (see explanation under
section entitled "serial data input/output").
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
CJ
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TEXAS
«
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block diagram showing one random and serial interface
DQ-------.---------------------+I-------------------------~
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HOUSTON, TEXAS 77001
4-29
TMS4461
262.144·811 MULTIPORT VIDEO RAM
Note that if column address bits A 7 through AO equal 00 during the last memory-to-register transfer cycle,
a total of 256 bits can be sequentially read out of each of the four data registers starting from bit position 00.
operation
random·access operation
transfer register select (TRG)
The TRG selects either register transfer or random-access operation as RAS falls. To use the TMS4461 in
random-access mode, TRG must be held high as RAS falls. Holding TRG high as RAS falls causes the
256 storage elements of each data register to remain disconnected from the corresponding 256 bit lines
of the memory array. If serial data is to be written in or read out of the data registers, the data registers
must be disconnected from the bit lines. Holding TRG low as RAS falls enables the 256 switches that
connect the data registers to the bit lines and indicates that a transfer will occur between the data registers
and the selected memory row.
-
random output enable (TRG)
During random-access operations, TRG functions as an output enable for the random outputs after the
read access times have been satisfied (if this is a read cycle). Whenever TRG is held high, the 0 outputs
will be in the high-impedance state. This feature removes the possibility of an overlap between data on
the address lines and data appearing on the 0 outputs making it possible to connect the address lines
to the data I/O lines-although use of this organization prohibits the use of the early write cycle. It also
allows read-modify-write cycles to be performed by providing a three-state condition to the common I/O
pins to allow write data to be driven onto the pins after output read data has been externally latched.
address (AO through A 7)
Sixteen address bits are required to decode one of 65,536 storage cell locations. Eight row-address bits
are set up on pins AD through A 7 and latched onto the chip on the falling edge of RAS. Then the eight
column-address bits are set up on pins AD through A 7 and latched onto the chip on the falling edge of CAS.
All row and column addresses must be stable on or before the falling edges of RAS and CAS respectively.
RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is
used as a chip select, activating the device input and output buffers. CAS is also used to strobe the column
address into the memory.
write-mask enable (WE)
The WE pin selects the random-mode write-mask option. The TMS4461 random port is equipped with
two modes of write operations. If WE is held low on the falling edge of RAS (during a random access
operation), the write mask is enabled. Accordingly, a 4-bit binary code (the mask) is input to the device
via the random DO pins and is also latched on the falling edge of RAS. This binary pattern determines
which of the four DRAM I/Os will be written into on that access and which'DRAM I/Os will not. Thus,
after RAS has latched the write mask on chip, input data is driven onto the DO pins and is latched on
the falling edge of the latter of CAS or WE (for early write operation, WE can remain low for the entire
RAS low period). If a 0 was strobed into a particular I/O pin on the falling edge of RAS, then the write
circuits for that particular I/O will be defeated and data will not be written to that I/O. If a 1 was strobed
into a particular I/O pin on the falling edge of RAS, then the write circuits for that particular I/O will not
be defeated and data will be written to that I/O. See the corresponding timing diagrams for details.
4-30
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4461
262.144·BIT MULTIPORT VIDEO RAM
Important: The mask operation is selected only if WE is held low on the falling edge of RAS. If WE is held
high on the falling edge of RAS the mask is not enabled and the write operation is identical to
standard x 4 DRAMs, with all four I/Os being written by the data appearing on the DO pins when the latter
of WE or CAS is brought low. Thus, if it is not desired to use the mask function, then a standard
DRAM timing interface can be used.
:2!
«a:
WRITE MASK FUNCTION TABLE
Os
TRG
WE
DQ1-DQ4
MODE
1
1
1
X
1
Write enabled at OQ 1-0Q4
0
Write to OQ disabled
1
0
0
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Write to OQ enabled
NOTE 1: The logic states in the table above are assumed valid on the falling edge of RAS.
write enable (WE)
The read or write mode is selected through the write-enable (WE) input. A logic high on the WE input
selects the read mode and a logic low selects the write mode. The write-enable terminal can be driven
from standard TTL circuits without a pull-up resistor. The data input is disabled when the read mode is
selected. When WE goes low prior to CAS, data out will remain in the high-impedance state for the entire
cycle.
data I/O (001-004)
Memory data is written during a write or read-modify-write cycle. The falling edge of WE strobes data
into the on-chip data latches. These latches can be driven from standard TTL circuits without a pull-up
resistor. In an early write cycle, WE is brought low prior to CAS and the data is strobed in by
CAS with data setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle,
CAS will already be low. Thus, the data will be strobed in by WE with data setup and hold times
referenced to this signal. The three-state output buffers provide direct TTL compatibility (no pull-up resistors
required) with a fanout of two Series 74 TTL loads. Data out is the same polarity as data in. The outputs
are in the high-impedance (floating) state as long as CAS or TRG is held high. Data will not appear at the
outputs until after both CAS and TRG have been brought low.
Once the outputs are valid, they will remain valid while CAS and TRG are low. CAS or TRG going high
will return the outputs to a high-impedance state. In an early write cycle, the outputs are always in the
high-impedance state. In a delayed-write or read-modify-write cycle, the outputs will follow the sequence
for the read cycle. In a register-transfer operation (memory-to-register or register-to-memory), the outputs
remain in the high impedance state for the .entire cycle, regardless of transitions on CAS or TRG.
write mask bits (OQ1-004)
When the write mask is enabled (WE low on the falling edge of RAS), the write mask bits determine which
DRAM I/Os are to be written and which of the DRAM I/Os will have their write operations internally defeated.
The state of the write mask bits is latched on-chip on the falling edge of RAS and selectively
controls the internal write enable circuits of each corresponding DRAM I/O. If the write mask is not enabled
(WE high on the falling edge of RAS), then no write enable circuits will be defeated and data appearing
at the DO '-D04 pins on the falling edge of RAS will be ignored. See timing diagrams and the table under
"write mask enable (WE)" for details.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-31
TMS4461
262,144·8IT MULTIPORT VIDEO RAM
refresh
c
A refresh operation must be performed to each row at least once every four milliseconds to retain data.
Since the output buffer is in the high-impedance state unless CAS is applied, the RAS-only refresh sequence
avoids any output during refresh. Strobing each of the 256 row addresses with RAS causes all bits in
each row to be refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power.
Note that the data registers are dynamic storage elements and that the data held in the registers will be
lost unless SC is clocked 2 times or else the data is reloaded from the memory array. See specifications
for maximum register retention times.
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CAS-before-RAS refresh
CAS-before-RAS refresh is accomplished by bringing CAS low earlier than RAS (see parameter tCLRL).
The external row address is ignored and the refresh address is generated internally.
column-address strobe (CAS)
The CAS input latches the column addresses on-chip and also functions as an output enable for OQ 1-0Q4.
page mode
Page-mode operation allows faster memory access by keeping the same row address and strobing random
column addresses onto the chip. Thus, the time required to set up and strobe row addresses for the same
page is eliminated. The maximum number of columns that can be addressed is determined by twIRL), the
maximum RAS low pulse duration.
power up
After power up, the power supply must remain at its steady-state value for 1 ms. In addition, RAS must
remain high for 100 p.s immediately prior to initialization. Initialization consists of performing eight RAS
cycles and one memory-to-register transfer cycle with an SC cycle following the rising edge of TRG before
proper device operation is achieved.
sequential·access operation
transfer register select (TRG)
Memory operations involving parallel use (i.e., transfer from memory to data register or data register to
memory) of the data register are invoked by bringing TRG low with the address lines AO-A 7 before RAS
falls. This enables the switches connecting the 256 elements of each data register to the 256 bit lines
of each ORAM 1/0. The states of WE and SG, which are also latched on the falling edge of RAS,
determine whether the 256-bit data transfer will be from the memory array to the data registers or from
the data registers to memory array, as well as determining if the SOQs are in read or write mode (see
"transfer operation logic table").
Note that the state of TRG is latched on the falling edge of RAS just like a row address, to select the mode
of operation. Ouring read or read-modify-write cycles, TRG functions as output enable after CAS falls.
transfer write enable (WE)
In register transfer mode, WE determines whether a transfer will occur from the data registers to the memory
array, or from the memory array to the data registers. To transfer data from the data registers to the memory
array, WE and SG are held low as RAS falls. If SG were to be high during this transition, then no transfer
of data from the data register to the memory array would occur, but the SOQs would be put into the write
mode. This would allow serial data to be written into the register. To transfer from the memory array to
the data registers, WE is held high and SG is a don't care as RAS falls. This cycle puts the SOQs into
the read mode, thus allowing serial data to be read out of the data register. Note that WE and SG setup
and hold times are referenced to the falling edge of RAS for this mode of operation (see "transfer operation
logic table").
4-32
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4461
262,144-81T MULTIPORT VIDEO RAM
row address (AO through A 7)
Eight address bits are required to select one of the 256 possible rows involved in the transfer of data to
or from the data registers. (The states of AO-A 7. WE. TRG. and SG are latched on the falling edge of RAS.)
register column address (AO through A 7)
To select one of the 256 positions along each of the four data registers from which the first serial data
will be read out. or to which the first serial data will be written. the appropriate a-bit column address (AO-A7)
must be valid when CAS falls during the appropriate transfer cycle.
serial data clock (SC)
Data is written in or read out of the data registers on the rising edge of SC. This makes it possible to view _
the data registers as though they were made of 256 positive-edge-triggered D flip-flops which connect
D to
(not to be confused with the DO random I/O pins of the TMS4461). The TMS4461 is designed
to work with a wide range duty cycle clock to simplify system design.
a
serial data input/output (500'-5004)
SD and SO share a common I/O pin. Data is written in when SG is low during write mode. and data is
read out when SG is low during read mode (see "transfer operation logic table"). Note that when the serial
address counter reaches its maximum value of 255. it is reset to 00 with the next positive transition of
SC. This allows data to be read out in a continuous loop.
block diagram of one serial I/O
DATA REGISTER
sc
AO-A7
L
~
SERIAL
ADDRESS
COUNTER
I
256
I
t>-
SDa
t
SERIAL DECODER/MUX
~
SERIAL
MODE
CONTROL
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-33
~
TMS4461
262,144·8IT MULTIPORT VIDEO RAM
serial enable (SG)
The serial enable pin has two functions. First, it is used on the falling edge of RAS, with both TRG and
WE low. If SG is low during this transition, then a register-to-memory transfer will occur. On the other
hand, if SG were to be high as RAS falls, then a write-mode control cycle will be performed. The function
of this cycle is to switch the SOOs from the output mode to the input mode, thus allowing serial data
to be written into the data register. Second, SG is used as a SOO enable/disable. In the write mode, SG
is used as an input enable. SG high disables the input, and SG low enables the input. To take the device
out of the write mode and into the read mode, a memory-to-register transfer cycle must be performed.
The read mode allows data to be read out of the data register. SG high disables the output and SG low
enables the output. Note that the serial address counter will be incremented on each SC cycle regardless
of the state of SG .
..
TRANSFER OPERATION LOGIC TABLE
TRG
WE
SG
MOOE
0
0
0
Register to memory transfer and
0
0
0
1
1
X
Write-mode enable
write-mode enable
NOTE 2:
Memory-to-register transfer
The logic states in the table above are assumed valid on the falling edge of RAS. In a
serial write-mode to read-mode sequence, the first positive transition of SCLK after the
memory-to-register transfel will change the SOQs from three-state to output mode.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
Voltage range for any pin except VOO and data out (see Note 3) ................... - 1 to 7 V
Voltage range for VOO supply with respect to VSS .............................. -1 to 7 V
Voltage range for data out with respect to VSS ......................... - 1 to VOO + 0.3 V
Short circuit output current per output .......................................... 50 mA
Power dissipation ............................................................ 1 W
Operating free-air temperature ............................................ 0 °C to 70°C
Storage temperature range .......................................... - 65°C to 150°C
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 3: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
VOO Supply voltage
VSS Supply voltage
NOM
MAX
UNIT
4.5
5
5.5
V
V
0
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 4)
-1
TA
Operating free-air temperature
0.8
70
°C
NOTE 4:
4-34
MIN
0
25
V
The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet
for logic voltage levels only.
TEXAS
"'I}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4461
262,144·81T MULTIPORT VIDEO RAM
electrical characteristics over full range of recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
Average operating current
1001
CONDITIONS
=
= 4.2 mA
VI = 0 V to 6.5 V,
VOO = 5 V,
All other pins = 0 V
Vo = 0.4 V to 5.5 V,
VOO = 5 V
-5 mA
10H
10L
TMS4461-12
TMS4461-15
MIN
MIN
MAX
2.4
UNIT
MAX
V
2.4
0.4
0.4
V
±10
±10
p.A
No load on OQ
cycle (serial port in standby)
and SOQ pins
±10
±10
p.A
80
70
mA
25
25
mA
75
65
mA
55
50
mA
85
80
mA
155
140
mA
After 1 memory cycle,
1002
Standby current
RAS, CAS, SC, and
(total, both ports)
SG
~
ca
..
C
>-
Minimum cycle time,
during read, write, or transfer
u
Os
C
2.4 V,
No load on OQ and SOQ pins
Minimum cycle time,
1003
Average refresh current
Average page-mode current
1004
(serial port in standby)
Minimum cycle time,
RAS s 0.8 V, CAS cycling,
No load on OQ and SOQ pins
register shifting
tc(SC) = MIN,
RAS and CAS ~ 2.4 V,
No load on OQ and SOQ pins
Worst case average current
on both ports,
Average current with memory
1005
RAS s 0.8 V, CAS ~ 2.4 V,
No load on OQ and SOQ pins
array in standby and
Minimum cycle time
1006
No load on OQ and SOQ pins
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-35
TMS4461
262,144·8IT MULTIPORT VIDEO RAM
capacitance over recommended supply voltage and operating free-air temperature ranges, f - 1 MHz
PARAMETER
-
Ci(A)
Input capacitance. address inputs
Ci(RC)
MIN
MAX
UNIT
7
pF
Input capacitance. strobe inputs
10
pF
Ci(WE)
Input capacitance. write enable input
10
pF
Ci(SC)
Input capacitance. serial clock
10
pF
Ci(SG)
Input capacitance. serial enable
5
7
pF
7
pF
Ci(TRG) Input capacitance. transfer register input
Output capacitance
Co
pF
switching characteristics over recommended supply voltage and operating free-air temperature ranges
TEST
PARAMETER
ta(C)
Access time from CAS
ta(R)
Access time from RAS
Access time of oa
ta(TRG)
from TRG low
Access time of sa
ta(SC)
ta(SG)
tdis(CH)
fro SC high
Access time of sa
Load
=
CL = 100 pF. tRLCL :S Max
Load = 2 Series 74 TTL gates.
CL = 100pF
Load = 2 Series 74 TTL gates.
CL = 50 pF
Load = 2 Series 74 TTL gates.
from SG low
CL = 50 pF
Load = 2 Series 74 TTL gates.
Random-output disable
CL = 15 pF
Load = 2 Series 74 TTL gates.
time from CAS high.
=
Load
Random·output disable
time from TRG high
MAX
TMS4461-15
MIN MAX
tCAC
60
75
ns
tRAC
120
150
ns
tOEA
35
40
ns
tSCA
40
50
ns
tSOA
30
35
ns
2 Series 74 TTL gates.
CL = 15 pF
Load = 2 Series 74 TTL gates.
Serial-output disable
time from SG high
CL
Load
CL
4-36
=
=
15 pF
=
2 Series 74 TTL gates.
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
0
20
0
25
ns
0
25
0
30
ns
0
20
0
25
ns
0
25
0
30
ns
0
15
0
20
ns
0
20
0
25
ns
tsoz
50 pF
TEXAS
UNIT
tOEZ
CL = 100 pF
Load = 2 Series 74 TTL gates.
tdis(SG)
MIN
tOFF
100 pF
=
TMS4461-12
2 Series 74 TTL gates.
CL = 100 pF. tRLCL 2: Max
Load = 2 Series 74 TTL gates.
CL
tdis(TRG)
ALT.
SYMBOL
CONDITIONS
HOUSTON, TEXAS 77001
TMS4461
262,144·8IT MULTIPORT VIDEO RAM
timing requirements over recommended supply voltage and operating free-air temperature ranges
ALT.
SYMBOL
tc(rd)
Read cycle time t
tRC
tc(W)
Write cycle time
twc
tc(rdW)
Read-write/read-modify-write cycle time
tRWC
tc(Trd)
Transfer read cycle time
tRC
tc(TW)
Transfer write cycle time
twc
tc(P)
Page-mode read or write cycle time
tpc
tc(rdWP)
Page-mode read-write/read-modify-write cycle time
tRWC
tc(SC)
Serial clock cycle time
tscc
tw(CH)
Pulse duration, CAS duration (precharge time)
tw(CL)
Pulse duration, CAS low *
tw(RH)
Pulse duration, RAS high (pre charge time)
twIRL)
Pulse duration, RAS low §
tw(W)
Write pulse duration
tcp
tCAS
tRP
tRAS
twp
tw(SCL)
Pulse duration, SC low
tSCL
tw(SCH)
Pulse duration, SC high
tSCH
tw(TRG)
TRG pulse duration low time
tOE
tt
Transition times (rise and fall)
tT
TMS4461-12
MIN
MAX
220
220
295
220
220
120
195
40 50,000
TMS4461-15
MIN
MAX
260
260
345
260
260
145
230
50 50,000
tn
ns
ns
ns
ns
60 10,000
75 10,000
ns
ns
150 10,000
45
10
10
ns
ns
ns
ns
tsu(CA)
Column-address setup time
tASC
tsu(RA)
Row-address setup time
tASR
35
3
0
0
tws
0
0
ns
tDTS
0
0
ns
tDS
0
0
ns
WE setup time before RAS low with TRG low
tsu(RW)
(register transfer cycles)
DO setup time before RAS low with TRG
tsu(DO)
high (random access, write mask select)
tsu(D)
Data setup time
tsu(rd)
Read-command setup time
tRCS
0
0
tsu(WCL)
Early write-command setup time before CAS low
50
40
3
0
0
ns
50
ns
ns
ns
ns
twcs
-5
-5
ns
tsu(WCH) Write-command setup time before CAS high
tCWL
35
45
ns
tsu(WRH) Write-command setup time before RAS high
Serial data setup time before SC high
tsu(SD)
tRWL
35
0
45
0
ns
tsu(TRG)
TRG setup time before RAS low
tTSR
0
0
ns
tsu(SG)
SG setup time before RAS low with TRG and WE low
tESR
0
0
ns
tsu(WM)
WE setup time before RAS low (write mask select)
tRWS
0
0
ns
th(CLCA)
Column-address hold time after CAS low
tCAH
Row-address hold time
tRAH
25
15
ns
th(RA)
20
15
th(RW)
WE hold time after RAS low with TRG low (transfer cycles)
tWH
15
15
ns
tSDS
Q
ns
ns
100
..
c
>-
ns
ns
60
90
CJ
"eca
ns
50
120 10,000
30
10
10
::2:
C
I
tRLCHR Delay time, RAS low to CAS high (CAS-before-RAS refresh)
155
185
ns
tCSR
10
20
ns
tCHR
20
25
ns
ns
tSGSC
Delay time, SG low to SC high during serial data-in shift cycle
tsws
10
10
tGHD
trf(MA)
Delay time, TRG high before data applied at DO
tGDD
25
30
Refresh time interval, memory array
tREF1
4
4
ms
trf(SR)
Refresh time interval, data register
tREF2
4
4
ms
NOTE 5:
~
u
"eca
UNIT
tTHRH
tRLCL
en
:E
ns
Timing measurements are referenced to VIL max and VIH min.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-39
TMS4461
262,144·811 MULTIPORT VIDEO RAM
read cycle timing
-
4-40
l!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4461
262,144·8IT MUL TIPORT VIDEO RAM
early write cycle timing, write mask unselected
en
:2:
-
C
TEXAS
.Jt!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-41
TMS4461
262,144·8IT MULTIPORT VIDEO RAM
early write cycle timing, write mask selected
c
-<:::::I
,: I-
3
, I
n'
RAS
..
N
"I
tc(W)
C»
twIRL)
I
~
• ,
I
Vi-tW(RH)-'i\
tt--{
t--
I "-------
t - - tCLRH--'
l--
I
tRLCL ~ tw(CL) ---I H - - t CHRL - - - ,
I ItRLCH
• I I I
I
I I
CAS
-...I
4
tt --/
I
N
tsu(RA)
r-~
T\
I
- I
I I '\...- - I ~tw(CH)--+----I
I I
~I_ _ _ _ _ _
II I
I ;II r-;--th(RLCA)---J
th(RAI-t-i
I
tt=
.0, :
tSU(C~)
AO-A7
TRG
tsu(WCL)
I
.
DON'T CARE
,
------I
I
I
--1
I th(RLW)
I I II
WE~! 1~11
r-th(CLWI
tSU(WM)--/-Hr-t- 1
th(WM) I
t--
'--tsu(WMI
--I
I--t su (DO)
I
I++-tW(W)~
r+-_th(WLD)~
I
I I
I I·
• I th(CLD)
I I----t~(RLD)---l
DO
--i
I
1«~{N:!g~0i!
I
I
I
~ VALID DATA }@g~!{g!~&X.ri-M-A-S-K----
~
tsu(DO)--t!-i1
--tl--tsu(D)
~ ~th(DO)
4-42
TEXAS
"!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
VIL
VIH
TMS4461
262,144-81T MULTIPORT VIDEO RAM
delayed write cycle timing, mask unselected
'11
'"
I
I
RAS
tc(WI
I·
~
,
tt--t ~
'.
RLCL
I
t
--:
I
tRLCH
---I
'I
I
!-itsu(RAI ,
II
II
'
't--th(RLCAI---I
th(RAI-t-i J.-.
t-t- tsu(CAI
.,
AO-A7
--:
I
n-tsu(TRGI
I J
TRGr}
i!
1 I-j-
tsu(WMI
I " - - - - - VIL
,
I-l-- tCHRL----t
,
I
1-1---,tw(CHI--+--i
I~',
"!
,.
I
tt--t
,-,
,
,
,
,
,
,
I,
-, th(CLCAI
,
,
---I
l---.!.-
th(CLWI----i
,
:
I---- tsu(WCHI+--i
I
th(RLWI
• ,
I
j-tSU(WRHIt----t
Wi ! ~~
I ' I---tw(WI---I
J
I '-- th(WLDI
'I'
,-
l--+_th....:.(C_L_D.;..I=_
.....,j
th(RLDI
--;....I
I
........I
:
t--tsu(WMI
~
tClRH
tw(Cl)---------t
tsu(CA)-t---i
th(RlCA)
i;""'.......1-'---...1
r-th(RA)--f,
,..r7'T7~r'C"'I~~~T'\J"O"U'U"t:rv"I'T'J',o"v_tr'I!""'C"V~rv"I'T'J'o::TVVV VIH
AO-A7
---J
~
th(TRG),
I
r-- t su(TRG),
Sltl(1 L
:.-.-l..isu(rd)
I '
I
~t
(TRG)
t--tsu(WCH) --f,
I
t
--.I
su(WRH) --.
-'
1:
th(WQE)
th(WM)-,1\ \ : \ \ { w
'th(RlW)'
,
---' I I
" ,•
tClWl
_
I ~tsu(WM) I '
.
th(ClW)"
,, I.
,
,
I.I
C
i
'L..-----------------1 I
I
, L.....--tw(CH)---i
,'
, I
tsu(RA)
, , .•
(J
I t-tw(RH)......,
t R l C l - - -....'
~:IH
.I
Il
• I
VIH
..........,....,..-r-+----"'Iirc'nT't7"Ii---f-----~,-----'---::! i--tw(W)---l Arvv",,,,,,v',,,-,v,,rv\JV\
,
" II
~Ivvv,,~'v''''-Jvv'vv
,r-----J-ta(C)''
....-I
v Il
,
tsU(D):;J
,.
tRlWl-+I---+--+----+-,----...., r-th(WlD).....,
r--
DQ~
'·
-!I
ta(R)
,
I
ta(TRG)-r----t
t - - :
tG~D
'I
VALID}
OUT~UT
_
I
~
_
~'VOH/VIH
VALID}
INPUT
_ -VOliVll
~tdiS(TRG)
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-45
TMS4461
262,144·8IT MULTIPORT VIDEO RAM
page-mode read cycle timing
c
-<:::J
.1
.....- - - - - - - - - - - t w ( R L )
D)
3
~----------------'l\
n"
I I
~
I.
tCLRH
tw(CL)
-
I I
th(RA)~ I-I
I I I ~
I
~
I
I
CAS
~ r-;ts~(RA)
tsu(CA)
1I
IH
I
I
-.J RtSU(CA)
1I
I
I I
I
I
I
I
ROW
t-t-tsu(TRG)
I
~th(TRGI
I
1
I
I
I
I
-
I
I
I
I
I
_
WE
I
I
I"
I I
I
II I I
I
+H
i
COL
•I
tCHRL
VIH
VIL
r-- th(CLCAi·
COL
I
I
I
I
I
I
I
I
~ 4tsu(r~) I
,
i I --l ~tsu(rdl
I I
I i t-th(CHrdl
rth(CHrdl
II
I
1
I
I
I --f I-ta(TRG)
I II
~ta(C)
1
t
DQ --------~I
-f
I~
'VI'
II
I
I
'
I
I
I
·'ltdis(CH)
I
II
I
.
I
I
ta(CI~ --1 I-tdis(CH)
I
I
I
L -'
i l
VALID
OUTPUT
I
~I
I VALID
\
OUT
TEXAS
'
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
I
I I
I I
I
I I
I
II
I I
I
I I
I I
I
\~
---tI I
I
L.--ta(RI_
4-46
I
I
I I
I I
1I
I I
I
I I
I
I---ttCLGL
_?H I ~I
TRG
~ H-tsu(CA)
I I I
I I I
I I
I I
I I
I I
th(CLCA)
VIL
~tw(RH)
·II I1- II
I I
I I
I
VIH
I
I
I COL~~~
I
:~I~t"""~VIH
I~O~N!T~Ct:l{« v
~
!
-1
I I
I I
I
I I
'•
I t h (CL A)
I-ith(RLCA)t-l
II
I I I Ii: I
AO-A7
I
I
I
I.
I
.....- -...·r-tw(CL)
I
I
.1
HOUSTON. TEXAS 77001
1~-""'Db:""""N~tjJ~
I_E~5~7
II
I
I
I
I
'-t
VIH
VIL
1 '
1-1
'I
~tsu(rd)
I
IL
i
(C)~
r- a ,
r-th(RHrdl
.l-th(CHrdl
II
I
I
I
I
,_
VIH
I
I
I
I
VIL
t---f-tdis(TRGI
• I td" (CHI
I
IS
. ,
VOH
VALID } - I
~ OUT _"
V
OL
t
TMS4461
262,144·8IT MULTIPORT VIDEO RAM
page-mode write cycle timing, write mask unselected
-1 f
tw(RHI ,1--------------tw(RLI
~---------------...J\~'r~------......:I!ri
!---tCLRH---f ,
r
I
, ,
I"
• 1 th(CLCIA)
t-rtsu(CAI" I
I
'-::~"';-;"'""'-""'___.J'
, I
VIL
MtCHRL--f
(
I "
I
I I
iL
I
VIH
tW
, - I
,
II
I
CU
~~{!;fit-+I----1 ',
I
AO·A7
-:
,
VIH
VIL
I ,
-H
r-th(CLCAI
~ t-t-t~u(CAI
I
I
I'
~ :,:
I
I'
,
..
I
~Htsu(TRGI I
, ,
I ' I
, I
~~~I--~I~l~----~I----~I+I------~I~I'j\~--~I~I------+I~I--------VIH
TRG
I I-
YI
I
·1 th(CLWI
'r---:-th(RLWI---I
I
-t-1
,I
Ii.
~tsu(WMI
WE
1!
I
"
"
I
:
~th(WLDI~1
:_1
~:tsu(DI
I
1
I I ,
,
fiTtSU(WCHI-t
th(CLWI
I_
~
I
--·+-1
II
I I ......
~~!!
VIL
th(CLWI
~~""""D"'O"'Jf"'J(",-"""-'W'VIH
~~w
~VIL
'I ,tw(WI~
I j I tw (WI-i
~
t--th(CLDI~
J.e-+-tSU(WRHI~
, I
, I
uJ
--J
VALID
I
I
\1 \"
I I I tw(WI.
I
tsu(WCHI~
~!I
ill
I~
DQ _
I
I tsu(WCHIr-'
,
,
\Iii
I
I
I
I
i~M'
r--+-'I"
~th(WLDI----I
:_1
rr-tsu(DI
VALID
I
~
~
I
}
I
1
t-th(CLDI--f
"1
f\
~th(WLDI----I
r-:-t
• I
su(DI
VALID
,
,
~ VIH
I '
t--th(CLDI--t
VIL
I
L--th(RLDI~
NOTE 6:
Timing assumes use of the early write feature. 'fAG must remain high throughout the entire page-mode operation if the late write
feature is used to guarantee page-mode cycle time.
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-47
TMS4461
262,144·811 MULTIPORT VIDEO RAM
page-mode write cycle timing, write mask selected
c
-<
::s
t - o l - . . - - - - - - - - - - - - - - t w ( R L ) _ _ _ _ _ _ _ _ _ _ _ _... ~
_-_""_' tw(RH)
~!
Q)
3
:'{~I---------'-----------~'r---------""""'f
RAS
(i'
I L---tRLCH------f
I I
tc(P) I
~ I : t t 1-1
I I
I
tRLCL, ,
- - ' I'-tt
i•
~
..
~
CA~
en
I
1.1,
N
•
i
I tw(CH)
VIL
!
r-
,
H-
h(RA)ri r---II.-t
I
I
,su(CA)
I
th(RLCA)-,
I
I
~ I I
~
II I
I th(CLCA)I
VIH
'-~
I
I
tCLRH--:-t
,
I
!-ttCHRL ""'-t
tW (CL)1
yir+,---+,- -
~tW(CL) rr~
tw(CL)
~
I I
I I
I ,..
-H t-
I
I I
I
_I t '
I
h(CLCA)·
I.
I
I
I
I
th(CLCA)
I
I
I
.I
.
tSU(RA)~1"'"r1
--1 :r-t:tsU(CA)~1
'~~
~~SU(CA)
I
I
AO-A 7
IROW
~
I COL I
!
COL
I cOL I
VIH
I
TRG
VL
I I
II I
tsu(TRG) I
I
I I
II I
II
I
it~lRLW)----'
I
I
il4
--I
!- ~
---i!-f tsu(WM)
I tsu(WCH)
I:
'.'
~r--r-I
WE_I
! -I
l---i
on
!
i-l-tsu(D)
I
I I
I I
I
I
I I
" I
II ,-
I
l----!
I'
I'
'I
-:
I
~"II
~I
I
~
t--th(CLD)--j
th(CLW)
-l
~~
t--th(CLD)---1
I
tsu(WM)
II
_ I
I
tw(W)
tl--.--th(WLD)--I
t-rtSU(D)
tsu(D)
L
~
I
~I,
I
l-f4
!,J
rr
I
I
• ' th(CLW)
_
I ~III
~~II
I VALID
I
!'j-PSU(WCH)--J
II
I
I
.
I I I-
I
I
!'--TtW(W)..o,
~
I
I.
I
I
I
I_'
!1: tsu(WRH)~
I I
I
I
I
I
I
. I
' I I
I
th(C~W)
r,tSU(WCH)-----f
I'·
I
tw(W)-----I
t h (WLD)-1
~ ~ALlO
I
I
I
--f
VIH
VIL
I
th(WLD)--,
I
; VALID
I
tsu(DO)
-II
I
t--
~
:::
I--th(CLD)---i
I
r----th(RLD) -----t
NOTE 7:
4-48
Timing assumes use of the early write feature. TRG must remain high throughout the entire page-mode operation if the late
write feature is used to generate page-mode cycle time. Timing also assumes that only those II0s selected by DO 1-004 on
the falling edge of RAS are written during page-mode operation.
TEXAS
l!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS4461
262,144-8IT MULTIPORT VIDEO RAM
page-mode read-modify-write cycle timing
rn
~
-
C
TEXAS
.Jlj}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-49
TMS4461
262,144·81T MULTIPORT VIDEO RAM
RAS·only refresh timing
..
4-50
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS4461
262,144·8IT MULTIPORT VIDEO RAM
hidden refresh cycle timing
I--- REFRESH
t----MEMORY CYCLE--I
CYCLE----I
t---REFRESH CYCLE----!
i
I
I-tw(RHI-f
J-tw(RHI-I
I I--tw'RLI--j ,
I I--tW'RlI--j ,
I
RAS
Vi
~
I
I I
I f
I
I •
I
I
\l
I
I
I
Y
\
"
th(RA1l--'
'-1-1 'f
:TIl,'
~
L-/
r------xI
I
I
•
•
I
I'
I , --;
I
tRLCHR
tw(CLI
I
I
I' ,(
i \: '
jj :I I
_ r--l~
I
I
I
,
I
t.h(CLCAI
tsu(CA)
\ ,
VIH
VIL
VIH
VIL
I
I
f
•
,
d 'I ,I
,
_D~~tSUIRAI--tM
..
I
I ! I
I~
LL tsu(rd)
--t
I
-
I
~~~
t - th(RHrdl
I
I
I
DQ
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4·51
TMS4461
262,144·8IT MULTIPORT VIDEO RAM
CAS-before-RAS refresh
tc(rd)---------1~
I..
I-1
..
-j
tw(RH)
----j1 1/4..
I
-II
1----
twIRL)
N'r---- - - -Y.
I
~I
-I
\r
-------.. •
VIH
VIL
4-- t RLCHR-----j
Yr----------
1
I
tCLRL
VIH
VIL
tsu(TRG)~
I
1-I1..t--_
..+-1 th(TRG)
VOH
DQ - - - - - - - - - - - - H I - Z - - - - - - - - - - - - - - -
VOL
4-52
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4461
262,144·811 MULTIPORT VIDEO RAM
write-mode control timing
U)
The write-mode control cycle is used to change the SDQs from the output mode to the input mode. This
allows serial data to be written into the data register. The diagram below assumes that the device was
originally in the serial read mode.
~
~
CJ
I·
tw(RL)
.:
I
~tRLCL--:
CAS
tsu(RA)
I
I
I
I
I
tRLCH I
I
I
:
"
~
:
:
: : - - - th(RLCA)
th(RA) I I·
•
i
AO-A7
.
i
l \.
.
I I •i
t
r-------""'-----
---l
tsu(TRG)
--!--i
I
I
I I.
•I
.
I
th(TRG)
VIH
VIL
I
I
t----f- th(CLCA)
~~~~ IR~W ~ CO~UMN ~*g~:*~~
I ;
..
C
I
• :
itW(CL)---'
I
CO
c
>-
y
I
.
i·
"e
~
I ;
i.!
t-- tsu(CA)
I
VIH
VIL
tTHRL
I
TRG~ 1 i ~g~m~~
t sU (RW)7-i
I
I
I
I.
_~II
WE~I:
I
I•
tCLSH--I
th(RW)
I
I V I H
•
i
I
VIL
-:.---'-'t'~oT~-tW(SCH)
sCJ'
tRLSH
i\sS\\\\\\
:
tw(SCL)
i.
~
~
~VIH
VIL
tsu(SO)~
I
SOO
• :
DO~T: H+-H'-Z~~2~~ O~;A
tdis(SG)"" fool---,
I
I
tsu (SG) ---f------,
NOTES:
8. Random-mode (0 outputs) remain in 3-state for the entire write-mode controL
9_ SG must be high as RAS falls in order to perform a write-mode control cycle_
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-53
TMS4461
262,144·811 MULTIPORT VIDEO RAM
data·register-to-memory timing, serial input enabled
C
The data-register-to-memory cycle is used to transfer data from the data register to the memory array.
Every one of the 256 locations in the data register is written into the 256 columns of the selected row.
Note that the data that was in the data register may have arrived there either from a serial write in or
from a parallel load of the dat'a register from one of the memory array rows. The diagram below assumes
that the device is presently in the serial-write mode (Le., SD is enabled by a previous write-mode control
cycle, thus allowing data to be written in).
'<
:::::J
D)
3
5'
-
NOTES:
4-54
10. Random-mode (Q outputs) remain in 3-state for the entire data-register-to-memory transfer cycle.
11. SG must be low as RAS falls in order to perform a register-to-memory transfer.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS4461
262,144-81T MULTIPORT VIDEO RAM
memory-to-data register timing
The memory-to-data-register cycle is used to load the data register in parallel from the memory array. Every
one of the 256 locations in the data register are written into from the 256 columns of the selected row.
Note that the data that is loaded into the data register may be either read out or written back into another
row. This cycle puts the device into the serial read mode (i.e., the sa is enabled, thus allowing data to
be read out of the register).
Also, the first bit to be read from the data register, after TRG has gone high, must be activated by a positive
transition of SC.
u
"eca
..
c
>-
Q
~,
,
,,I
,,
VIH
VIL
VIH
VIL
vlH
AO-A7 "","'''',,,,,.,.,
vlL
tTHRH
~--~----------------------""vIH
I
I
~__~______________~__~. ~tTHCH
tsu(RW)~
I..---t...,- th(RW)'"
I
ioI,
..
,
,I
SC
SOQ
---------------------------------------------------------------VIL
NOTES:
12. Random mode (Q outputs) remain in 3-state for the entire memory-to-data-register transfer cycle.
13. Column address must be supplied to load register start address on every transfer cycle.
14. The first positive transition of SC after'i'RG has gone high, during a memory-to-register transfer cycle, is used to read the first
bit of new data.
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-55
TMS4461
262,144·81T MULTIPORT VIDEO RAM
serial data-in timing
C
The serial data-in write cycle is used to write data into the data register. Before data can be written into
the data register via SO, the device must be put into the write mode by performing a write-mode control
cycle. Register-to-memory transfer cycles occurring between the write-mode control cycle and the
subsequent writing in of data will not take the device out of the write mode. But, a memory-to-register
transfer cycle during that time will take the device out of the write mode and put it into the read mode,
thus not allowing the writing in of data.
'<
~
C»
3
(;'
::0
»
..
~
en
I'~
,
I
,
sc
r-
~
,
te(SCl
I
-,
,..--tw(SCHl-'"
,
,
j4-t su (SOl---l
I
,
I~th(SOl
.
I.--tw(SCLl~
~
t (SCLl7,
I
I
,
J.if
~C
W
¥l
!.-tsu(SOl-.l
I
,
VIH
SDO~ VAlIDDA~A m:;~
VIL
:
I----+-th(SOl
VALID DATA
_:::
,
I4 t SGSC.j
~...___________________________________________________ VIH
-
NOTE 15:
4-56
VIL
While writing data into the data register, the state of TRG is a don't care as long as TRG is held high when RAS goes low.
This is'to avoid the initiation of a register-to-memory or memory-to-register data-transfer function.
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4461
262,144-81T MULTIPORT VIDEO RAM
serial data-out timing
The serial data-out read cycle is used to read data out of the data register. Before data can be read out
via SQ, the device must be put into the read mode by performing a memory-to-data-register transfer cycle.
Register-to-memory transfer cycles occurring between the memory-to-register transfer cycle and the
subsequent reading out of data will not take the device out of the read mode. But, a write-mode control
cycle at that time will take the device out of the read mode and put it in the write mode, thus not allowing
the reading out of data.
en
:E
<2:
a::
Co)
"eas
c
>
C
NOTE 16:
While reading data out of the data register, the state of TRG is a don't care as long as TRG is held high when RAS goes low.
This is to avoid the initiation of a register-to-memory or memory-to-register data-transfer operation.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-57
C
'<
:::s
CI)
3
c:r
..
4-58
TMS4464
65,536·WORD BY 4·B11 DYNAMIC RANDOM·ACCESS MEMORY
NOVEMBER 1983 -
•
•
•
65,536 x 4 Organization
N PACKAGE
(TOP VIEW)
Single 5-V Supply (10% Tolerance)
VSS
DQ4
DQl
JEDEC Standardized Pinout
CAS
DQ3
o Pinout Identical to TMS4416 (16K x 4
Dynamic RAM)
•
o
o
o
Al
..
A2
ACCESS
READ
READMODIFY-
TIME
TIME
OR
ROW
COLUMN
WRITE
WRITE
ADDRESS ADDRESS CYCLE
MAX
MAX
MIN
CYCLE
A3
'-t..:=---------.:...:=__
TMS4464-10
100 ns
50 ns
200 ns
120 ns
60 ns
220 ns
295 ns
TMS4464-15
150 ns
75 ns
260 ns
345 ns
A7
FM PACKAGE
(TOP VIEW)
MIN
TMS4464-12
....
270 ns
o
Oil!)
DQ2
Long Refresh Period ... 4 ms (Max)
W
Low Refresh Overhead Time ... As Low As
1.3% of Total Refresh Period
RAS
A6
en
en
>
q-
0
0
3
CAS
4
5
6
A5
On-Chip Substrate Bias Generator
15
14
DQ3
AO
13
A1
12
A2
B 9 1011
All Inputs, Outputs, and Clocks Fully TTL
Compatible
q-
3-State Unlatched Output
o Early Write or
•
AO
Performance Ranges:
ACCESS
o
o
REVISED JUNE 1987
G to
Control Output Buffer
PIN NOMENCLATURE
Impedance
AO-A7
Address Inputs
Page-Mode Operation for Faster Access
CAS
Column-Address Strobe
o Power Dissipation As Low As:
-
Operating ... 330 mW (Max)
Standby ... 25 mW (Max)
(for 1 50 ns devices)
o
RAS-Only Refresh Mode
o
CAS-Before-RAS Refresh Mode
•
Available with MIL-STD-883C, Class B
Processing and S (- 55 °C to 110 °C)
Temperature Ranges (SMJ4464)
DQ1-DQ4
Data InlData Out
G
Output Enable
RAS
Row-Address Strobe
VDD
5-V Supply
VSS
Ground
W
Write Enable
description
The TMS4464 is a high-speed, 262, 144-bit dynamic random-access memory, organized as 65,536 words
of four bits each. It employs state-of-the-art SMOS (scaled MOS) N-channel double-level polysilicon/polycide
gate technology for very high performance combined with low cost and improved reliability_
This device features maximum RAS access times of 100 ns, 120 ns, or 150 ns. Power dissipation maximums
are 330 mW operating and 25 mW standby for 150-ns devices.
New SMOS technology permits operation from a single 5-V supply, reducing system power supply and
decoupling requirements, and easing board layout. 100 peaks are 125 rnA typical, and a -1-V input voltage
undershoot can be tolerated, minimizing system noise considerations.
PRODUCTION DATA documents contain information
current as of publication date_ Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~a{~~I~~B ~~~~~~ti~r :llo::~:~:t:ros~S not
Copyright © '1987, Texas Instruments Incorporated
TEXAS
-1.!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-59
TMS4464
65,536·WORD BY 4·81T DYNAMIC RANDOM·ACCESS MEMORY
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All address and data-in lines
are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility.
c
-<
:::s
m
The TMS4464 is offered in 18-pin plastic dual-in-line and 18-lead plastic chip carrier packages. It is
guaranteed for operation from 0 °C to 70°C. The dual-in-line package is designed for insertion in mountinghole rows on 7,62-mm (300-mil) centers.
3
5'
..
operation
address (AO through A7)
Sixteen address bits are required to decode 1 of 65,536 storage locations. Eight row-address bits are set
up on pins AO through A7 and latched onto the chip by the row-address strobe (RAS). Then the eight
column-address bits are set up on pins AO through A 7 and latched onto the chip by the column-address
strobe (CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar
to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a
chip select activating the column decoder and the input and output buffers.
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on the Vii input selects
the read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard
TTL circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When
Vii goes low prior to CAS, data out will remain in the high-impedance state for the entire cycle permitting
common I/O operation.
data in (DQ1·0Q4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling
edge of CAS or Vii strobes data into the on-chip data latches. These latches can be driven from standard
TTL circuits without a pull-up resistor. In an early write cycle, Vii is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-modifywrite cycle, CAS will already be low, thus the data will be strobed in by Vii with setup and hold times
referenced to this signal. In a delayed or read-modfy-write cycle, G must be high to bring the output buffers
to high impedance prior to impressing data on the I/O lines.
data out (OQ1-0Q4)
The three-state output buffer provides direct TTL compatibility (no pull-up resistor required) with a fan-out
of two Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance
(floating) state until CAS is brought low. In a read cycle the output goes active after the access time interval
talC) that begins with the negative transition of CAS as long as ta(R) and ta(G) are ~tisfied. The outP~
becomes valid after the access time has elapsed and remains valid while CAS and G are low. CAS or G
going high returns it to a high-impedance state. In a delayed-write or read-modify-write cycle, the output
must be put in the high-impedance state prior to applying data to the DQ input. This is accomplished by
bringing G high prior to applying data, thus satisfying tGHD.
output enable (G)
The G input controls the impedance of the output buffers. When G is high, the buffers will remain in the
high-impedance state. Bringing G low during a normal cycle will activate the output buffers putting them
in the low-impedance state. It is necessary for both RAS and CAS to be brought low for the output buffers
to go into the low-impedance state. Once in the low-impedance state they will remain in the low-impedance
state until G or CAS is brought high.
4-60
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS4464
65,536·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
refresh
tn
A refresh operation must be performed at least once every four milliseconds to retain data. This can be
achieved by strobing each of the 256 rows (AO-A7). A normal read or write cycle will refresh all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
thus conserving power as the output buffer remains in the high-impedance state.
:21
-
TMS4464
65,536·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
logic symbol t
C
-<
::J
m
3
AO
A1
A2
A3
A4
(;'
1141
2008/2100
1131
1121
1111
181
171
A5
161
A6
1101
A7
~
l>
en
..
s:
RAs
CAS
W
A _O_
65,535
151
1161
23C22
141
G 111
OQ1
121
A.Z26
131
002
003 1151
004 1171
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
Pin numbers shown are for the dual-in-line package.
functional block diagram
t
I
I
t
--e-
AO
ADDRESS
BUFFERS
--
ROW
DECODE
I :
32K ARRAY
A3
A4
A5
BUFFERS
IBI
-
ROW
DECODE
256 SENSE AMPS
:
32K ARRAY
256 SENSE AMPS
i----
32K ARRAY
A6
I: :
COLUMN DECODE
..;
..
ROW
DECODE
32K ARRAY
A7
4-62
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
~
32K ARRAY
DECODE
A1
COLUMN
32K ARRAY
ROW
32K ARRAY
M
ADDRESS
I
256 SENSE AMPS
256 SENSE AMPS
IBI
A2
t
~J
32K ARRAY
r-
t
TIMING AND CONTROL
~l
ROW
W
HOUSTON. TEXAS 77001
110
BUFFERS
(4)
~
DATA
~.
DATA
OUT
REG
IN
REG
r~-
DQ1·DQ4
TMS4464
65,536·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
Average operating current
1001
during read or write cycle
1002
Standby current
1003
Average refresh current
1004
Average page-mode current
CONDITIONS
= -5 mA
= 4.2 mA
VI = 0 V to 6.5 V, VOO = 5 V,
All other pins = 0 V to 6.5 V
Vo = 0 V to 5.5 V, VOO = 5 V,
TMS4464-10
TMS4464-12
MIN
MIN
2.4
10H
IOL
CAS high, All outputs open
=
tc
minimum cycle, All outputs open
After 1 memory cycle, 001-004 held at
> 0 V, RAS and CAS high, All outputs open
=
tc
minimum cycle, RAS low, CAS high,
All outputs open
tc(P)
=
MAX
minimum cycle, RAS low and
CAS cycling, All outputs open
UNIT
MAX
2.4
V
0.4
0.4
V
±10
±10
p.A
±10
±10
p.A
70
65
mA
4.5
4.5
mA
58
53
mA
50
45
mA
u
"sca
..
c
>-
C
TMS4464-15
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
Average operating current
1001
during read or write cycle
1002
Standby current
1003
Average refresh current
1004
Average page-mode current
TEST CONDITIONS
MIN
= -5 mA
= 4.2 mA
VI = 0 V to 6.5 V, VOO = 5 V, All other pins = 0 V to 6.5 V
Vo = 0 V to 5.5 V, VDO = 5 V, CAS high, All outputs open
10H
IOL
tc
=
minimum cycle, All outputs open
After 1 memory cycle, 001-004 held at
> 0 V,
RAS and CAS high, All outputs open
tc
=
tc(P)
minimum cycle, RAS low, CAS high, All outputs open
=
minimum cycle, RAS low, CAS cycling,
All outputs open
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
MAX
2.4
UNIT
V
0.4
V
±10
p.A
±10
p.A
60
mA
4.5
mA
48
mA
40
mA
4-63
TMS4464
65,536-WORD BY 4-BITDYNAMICRANDOM-ACCESS MEMORY
capacitance over recommended supply voltage range and 'operating free-air temperature range,
f = 1 MHz
TMS4464
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write enable input
7
pF
Ci/o
Output capacitance
7
pF
'switching characteristics over recommended supply voltage range and operating free-air temperature
. . range
PARAMETER
TEST CONDITIONS
ta(C)
Access time from CAS
tRLCL 2: MAX, CL = 100 pF,
Load = 2 Series 74 TTL gates
ta(R)
, Access time from RAS
tRLCL = MAX, CL = 100 pF,
Load = 2 Series 74 TTL gates
ta(G) t
Acce!,s time after Glow
..
tdis(CH) Output disable time after CAS high
tdis(G)
ta(C)
..
Output disable time after G high
MAX
TMS4464-12
MIN
MAX
UNIT
tCAC
50
60
ns
tRAC
100
120
ns
= 2 Series 74 TTL gates
tGAC
30
35
ns
CL = 100 pF •
Load = 2 Series 74 TTL gates
tOFF
a
30
a
30
ns
tGOFF
0
30
0
30
ns
CL
=
Load
CL
=
Load
100 pF,
100 pF.
= 2 Series
74 TTL gates
ALT.
TMS4464-15
TEST CONDITIONS
Access time from CAS
tRLCL 2: MAX, CL = 100 pF.
Load = 2 Series 74 TTL gates
tCAC
75
ns
tRLCL = MAX. CL = 100 pF •
Load = 2 Series 74 TTL gates
tRAC
150
ns
tGAC
40
ns
..
Access time from RAS
ta(G)t
Access time after Glow
CL
=
Load
CL
tdis(CH) Output disable time after CAS high
=
Load
CL
Output disable time after G high
=
Load
SYMBOL
MIN
100 pF.
=
2 Series 74 TTL gates
100 pF.
=
2 Series 74 TTL gates
2 Series 74 TTL gates
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MAX
UNIT
tOFF
a
30
ns
tGOFF
a
30
ns
100 pF.
=
tta(C) and ta(R) must be satisfied to guarantee ta(G),
-4-64
TMS4464-10
MIN
PARAMETER
ta(R)
tdis(G)
ALT.
SYMBOL
TMS4464
65,536-WORD BY 4-BI1 DYNAMIC RANDOM-ACCESS MEMORY
timing requirements over recommended supply voltage range and operating free-air temperature range
(see Note 3)
TMS4464-12
SYMBOL
MIN
MIN
tc(P)
Page-mode cycle time
tpc
100
120
ns
tc(PM)
Page-mode cycle time (read-modify-write cycle)
tpCM
170
195
ns
MAX
MAX
Read cycle time t
tRC
200
220
ns
tc(W)
Write cycle time
twc
200
220
ns
tc(rdW)
Read-write/read-modify-write cycle time
tRWC
270
295
ns
tw(CH)P
Pulse duration, CAS high (page mode)
tcp
40
50
ns
tw(CH)
Pulse duration, CAS high (non-page mode)
tCPN
25
25
ns
tw(CL)
Pulse duration, CAS low t
tCAS
50
tw(RH)
Pulse duration, RAS high
tRP
90
twiRL)
Pulse duration, RAS low §
tRAS
100
tw(W)
Write pulse duration
twp
30
tt
Transition times (rise and fall) for RAS and CAS
tT
3
60
10,000
90
10,000
120
3
a::
Co)
"E
co
c
..
>-
C
ns
ns
10,000
ns
50
ns
ns
30
50
C
ns
a
a
a
a
a
tDS
u
"sas
th(CLD)
Data hold time after CAS low
tDH
45
th(RLD)
Data hold time after RAS low
tDHR
120
ns
th(WLD)
Data hold time after W low
tDH
45
ns
th(CHrd)
Read-command hold time after CAS high
tRCH
a
ns
th(RHrd)
Read-command hold time after RAS high
tRRH
10
ns
th(CLW)
Write-command hold time after CAS low
tWCH
45
ns
th(RLW)
Write-command hold time after RAS low
tWCR
120
ns
Continued next page.
NOTE 3: Timing measurements are referenced to VIL MAX and VIH MIN.
t All cycle times assume tt = 5 ns.
:!:In a read-modify-write cycle, tCLWL and tsu(WCH) must be observed. Depending on the user's transition times, this may require additional
CAS low time (tw(CL))'
§In a read-modify-write cycle, tRLWL and tsu(WRH) must be observed. Depending on the user's transition times, this may require additional
RAS low time (tw(RL)).
. TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-67
TMS4464
65,536-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
C
timing requirements over recommended supply voltage range and operating free-air temperature range
(concluded) (see Note 3)
-<~
m
ALT.
SYMBOL
3'
n
TMS4464-15
MIN
MAX
UNIT
tRLCHR
Delay time. RAS low to CAS high'
tCHR
30
ns
tRLCH
Delay time. RAS low to CAS high
tCSH
150
ns
l>
tCHRL
Delay time. CAS high to RAS low
tCRP
0
ns
-
tRHCL
Delay time. RAS high to CAS low'
tRPC
0
ns
tCLRH
Delay time. CAS low to RAS high
tRSH
75
ns
tCLWL
Delay time. CAS low to W low (read-modify-write cycle only) #
tCWD
110
ns
tCLRL
Delay time. CAS low to RAS low'
tCSR
20
ns
::I:J
3:
en
Delay time. RAS low to CAS low (maximum value specified
tRCD
25
tRLWL
Delay time. RAS low to W low (read-modify-write cycle only) #
tRWD
185
ns
tGHD
Delay time. G high before data applied at DQ
tGDD
30
ns
trf
Refresh time interval
tREF
tRLCL
only to guarantee access time)
NOTE 3: Timing measurements are referenced to VIL MAX and VIH MIN.
~ CAS-before-RAS refresh option only.
# IT must disable the output buffers prior to applying data to the device.
4-68
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
75
4
ns
ms
TMS4464
65,536·WORD BY 4·BI1 DYNAMIC RANDOM·ACCESS MEMORY
read cycle timing
..
AO-A7
w
)()€o~.~c:~ot'
:~€NJ€A&m :::
I
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---I-,-
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,
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~
VALID OUTPUT
~
•
taIG)~
:I~------
I
~
I
VOH
VOL
tdislG)
I
-------~
t~------
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
tdislCH)
-k-
HOUSTON, TEXAS 77001
4-69
TMS4464
65,536·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
early write cycle timing
C
'<
:::I
C»
3
cr
AO-A7
iii
DQ
4-70
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4464
65,536·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
write cycle timing
u
Os
CO
c
>-
C
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-71
TMS4464
65,536·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
read-write/read-modify-write cycle timing
--u
·1
I_
RAS
--t
twlRlI
t
I_
-I , . - t
-
:L
: :.
I:
II
tRLCL
_I
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I
1.--.1-- th(CLCAI
-.I j.L tsu(CAI
tsu(rdl~ I
I
I
1
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10
tCHRL
--I
~ :::
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J.tsu(WCHI-.f
I
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.
th(WLDI..,
ta(CI~
~l-- tsu(DI
I
DQ
ta(GI~
\.---.I- tGHD
I
1
{
'
tftwlwl1<»Ht~~Q:(
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4-72
1
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tALC"
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AO-A7
It '-
t c ( r d W I - - - - - - - - - - -...
1
t
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
I
1
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,
1t \.
twlRLJ
RAS
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l
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I~P;
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I
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r-+~
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en
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VIL
VIL
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are not violated.
tAo)
en
~
o
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c
ca
+=:10
Cc
=t
c
<
2:
3:
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VOL
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,
,
I
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l>
2:
C
:i:n
n
t
VIH
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I
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3:
NOTE 4: A write cycle or read-modify-write cycle can be intermixed with read cycles as long as the write and read-modify-write timing specifications
~
U,
<
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V
IL
VIH
VIL
VIH
VIL
NOTE 5: A write cycle or read-modify-write cycle can be intermixed with write cycles as long as the read and read-modify-write timing specifications
are not violated.
=
C
ca
C)
th(CLDI
~S
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...
en
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NOTE 6: A read cycle or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated.
Dynamic RAMs
:DC)
-<~
TMS4464
65,536·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
RAS-only refresh cycle timing
141------tC(rd)----..-t·1
hidden refresh cycle timing
I--- REFRESH
t----MEMORY CYCLE----f
I
I-tw(RH)-I
I r-twIRlI-j I
RAS
r1I
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CAS
th(RA) U
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Vi
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/
tw(CL)
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1-+1
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VL
t-- th(RHrd)
I
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t--
WEW!
II I - -
!!
DO
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I
I
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\
tdis(CH)--,
I
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VALID DATA
I
~th(TRG)
I
TRGW
t--ta(C)
ta(R) ---,
~ t-+tsu(TRG)
t
::
I
I
\\
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
} - - :0'
.
dls(TRG)
I
~ta(TRG)
4-76
VIL
~VIH
t-t- tsu(rd)
I
I
I
I
I
I
I
tSU(RA~'--jrtlll
II I
AO.A7
VIL
• I
• I
I
I
:th(CLCA)
tsu(CA)
I I
•
I
I.
~V
I
IH
I;
nil
\------I
tRLCHR
I
I
jj
~ V,H
HOUSTON, TEXAS 77001
I
-4----t
I
I
OL
VIH
VIL
1M~4464
65,536-WORD BY 4-B11 DYNAMIC RANDOM-ACCESS MEMORY
CAS-before-RAS refresh cycle timing
(I)
~
-
-
C
VOH
OQ
---------HI-Z----------
-Ij}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-77
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4-78
TMS44C251
262.144 BY 4-BIT MULTIPORT VIDEO RAM
AUGUST 1988
•
•
•
•
•
DRAM: 262,144 Words x 4 Bits
SAM: 512 Words x 4 Bits
OJ PACKAGE
Dual Port Accessibility - Simultaneous and
Asynchronous Access from the DRAM and
SAM Ports
4 x 4 Block Write Feature for Fast Area Fill
Operations. As Many as Four Memory
Address Locations Written Per Cycle From
an On-Chip Color Register
Write Per Bit Feature for Selective Write to
Each RAM I/O. Two Write Per Bit Modes to
Simplify System Design
Enhanced Page Mode Operation for Faster
Access
•
CAS-before-RAS and Hidden Refresh Modes
o
RAM Output Enable Allows Direct
Connection of DQ and Address Lines to
Simplify System Design
o
Long Refresh Period ... Every 8 ms (Max)
•
DRAM Port is Compatible with the
TMS44C256
0
•
•
•
•
se
SDOO
SD01
ITOP VIEWI
VSS
SD03
SD02
TRG
Bidirectional Data Transfer Function
Between the DRAM and the Serial Data
Register
•
•
SO PACKAGE
(TOP VIEWI
SE
DOO
D01
W
GND
RAS
A8
A6
A5
A4
Vee....,
D03
D02
DSF
eAS
OSF
AO
A1
A2
A3
...- A7
D02
SD02
VSS
SDOO
5E
u
Os
SD03
SC
SD01
CO
C
>
DOO
C
W
RAS
A5
Vee
A3
A1
OSF
A6
A4
A7
A2
AO
2
o
i=
II(
:E
a:
PIN NOMENCLATURE
Up to 33 MHz Uninterrupted Serial Data
Streams
AO-A8
Address Inputs
CAS
Column Enable
DOO-D03
DRAM Data In-Out!
SE
Write Mask Bit
Serial Enable
RAS
Row Enable
SC
SDOO-SD03
Serial Data Clock
'FFiG
o
LL
-2w
o
2
~
Serial Data In-Out
Transfer Register!O Output
C
Enable
iN
Split Serial Data Register for Simplified
Realtime Register Reload
II(
Write Mask Select!
Write Enable
3-State Serial I/Os Allow Easy Multiplexing
of Video Data Streams
512 Selectable Serial Register Starting
Locations
DSF
Special Function Select
OSF
Split Register Activity Status
VCC
5-V Supply (TYPI
VSS
GND
Ground
Ground (Important: not
connected to internal VSSI
All Inputs and Outputs TTL Compatible
Performance Ranges:
ACCESS ACCESS ACCESS ACCESS
TIME
TIME
TIME
TIME
COLUMN SERIAL SERIAL
ROW
ENABLE
DATA
ADDRESS ENABLE
(MAXI
(MAXI
(MAXI
(MAXI
ta(SEI
ta(CI
ta(SCI
ta(RI
30 ns
20 ns
25 ns
TMS44C251-10 100 ns
25 ns
35 ns
35 ns
TMS44C251-12 120 ns
40 ns
30 ns
45 ns
TMS44C251-15 150 ns
•
Texas Instruments EPICTM CMOS Process
EPIC is a trademark of Texas Instruments Incorporated.
ADVANCE INFORMATION documents contain
information on new IIroducts in the samplinp or
IIreproduction phase of development. Characteristic
data and other specifications are subject to change
without notice.
.
TEXAS
"J1
INSTRUMENTS
POST OFFice BOX 1443 •
HOUSTON. TeXAS 77001
Copyright © 1988. Texas Instruments Incorporated
4-79
TMS44C251
262.144 BY 4·BIT MULTIPORT VIDEO RAM
descripton
c
The TMS44C251 Multiport Video RAM is a high speed, dual ported memory device. It consists of a dynamic
random-access memory (DRAM) organized as 262,144 words of 4 bits each, interfaced to a serial data
register, or Serial Access Memory (SAM), organized as 512 words of 4 bits each. The TMS44C251 supports
three basic types of operation: random access to and from the DRAM, serial access to and from the serial
register, and bidirectional transfer of data between any row in the DRAM and the serial register. Except
during transfer operations, the TMS44C251 can be accessed simultaneously and asynchronously from
the DRAM and SAM ports. During transfer operation, the 512 columns of the DRAM are connected to
the 512 positions in the serial data register. The 512 x 4 bit serial data register can be loaded from the
memory row (transfer read) or else the contents of the 512 x 4 bit serial data register can be written
to the memory row (transfer write).
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The TMS44C251 is equipped with several features designed to provide higher system level bandwidth
and simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw
rates can be achieved by the device's novel 4 x 4 Block Write Mode. Block Write mode allows four bits
of data present in an on-chip color data register to be written to any combination of four adjacent column
address locations. As many as 16 bits of data can be written to memory during each CAS cycle time.
Also on the DRAM port, a write mask register provides a persistent write per bit mode without repeated
mask loading.
On the serial register, or SAM port, the TMS44C251 offers a split register transfer read (DRAM to SAM)
option which enables realtime register reload implementation for truly continuous serial data streams,
without critical timing requirements. The register is divided into a high half and a low half. While one half
is being read out of the SAM port, the other half can be loaded from the memory array. This new realtime
register reload implementation allows truly continuous serial data. For applications not requiring realtime
register reload (for example, reloads done during CRT retrace periods), the single register mode of operation
is retained to simplify system design. The SAM can also be configured in input mode, accepting serial
data from an external device. Once the serial register within the SAM is loaded, its contents can be
transferred to the corresponding column positions in any row in memory in a single memory cycle.
The SAM port is designed for maximum performance. Data can be input to or accessed from the SAM
at serial rates up to 33 MHz. During split register mode of operation, internal circuitry detects when the
last bit position is accessed from the active half of the register and immediately transfers control to the
opposite half. A separate open drain output, designated QSF, is included to designate which half of the
serial register is active at any given time in split register mode.
All inputs, outputs, and clock signals on the TMS44C251 are compatible with Series 74 TTL. All address
lines and data-in are latched on-chip to simplify system design. All data-outs are unlatched to allow greater
system flexibility.
The TMS44C251 employs state-of-the-art Texas Instruments EPIC'· scaled-CMOS, double level
polysilicon/polycide gate technology for very high performance combined with low cost and improved
reliability.
The TMS44C251 is offered in a 2S-pin small-outline J-Ieaded package (DJ suffix) for direct surface mounting
in rows on 400-mil (5,OS-mm) centers. It is also offered in a 400-mil, 2S-pin zig-zag in-line package (SD
suffix). Both packages are characterized for operation from °C to 70°C (L suffix).
°
The TMS44C251 and other Multiport Video RAMs are supported by a broad line of graphics processor
and control devices from Texas Instruments, including the TMS3401 Graphics System Processor.
°
4-S0
TEXAS
"'J}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
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Dynamic RAMs
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
DETAILED PIN DESCRIPTION vs OPERATIONAL MODE
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PIN
TRANSFER
DRAM
Dl
AD-AS
Row. Column Address
Row. Tap Address
c:r
CAS
Column Enable
Tap Address Strobe
Dai
DRAM Data 1/0 Write Mask Bits
3
SE
Serial-In Mode Enable
RAS
-
SAM
Serial Enable
Row Enable
Row Enable
Serial Clock
SC
Serial Data 1/0
SDai
'i"'R'G
Transfer Enable
a Output Enable
W
Write Enable Write per Bit Select
Transfer Write Enable
DSF
Block Write Enable
Split Register Enable
Persistent Write per Bit Enable
Alternate Write Transfer Enable
Color Register Load Enable
Write per Bit Mask Load Enable
Split Register
aSF
Active Status
VCC
5-V Supply (typical)
VSS
GND
System Ground
Device Ground
operation
random access operation
Refer to Table 1, Functional Truth Table, for Random Access and Transfer Operations. Random access
operations are denoted by the designator "R" and transfer operations are denoted by a "T."
transfer register select and OQ enable (TRG)
The TRG pin selects either register or random access operation as RAS falls. For random access (DRAM)
mode, TRG must be held high as RAS falls. Asserting TRG high as RAS falls causes the 512 storage elements
of each data register to remain disconnected from the corresponding 512-bit lines of the memory array.
(Asserting TRG low as RAS falls connects the 512-bit positions in the serial register to the bit lines and
indicates that a transfer will occur between the data registers and the selected memory row. See "Transfer
Operation" for details.)
During random access operations, TRG also functions as an output enable for the random (Q) outputs.
Whenever TRG is held high, the Q outputs are in the high-impedance state to prevent an overlap between
the address and DRAM data. This organization allows the connection of the address lines to the data I/O
lines but prohibits the use of the early write cycle. It also allows read-modify-write cycles to be performed
by providing a three-state condition to the common I/O pins so that write data can be driven onto the
pins after output read data has been externally latched.
addresses (AO through AS)
Eighteen address bits are required to decode 1 of 262,144 storage cell locations. Nine row address bits
are set up on pins AO through AS and latched onto the chip on the falling edge of RAS. Then, the nine
column address bits are set up on pins AO through A8 and latched onto the chip on the falling edge of CAS.
4-82
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
RAS and CAS address strobes and device control clocks
RAS is a control input that latches the states of the row address, W, TRG, SE, CAS, and DSF onto the
chip to invoke the various DRAM and Transfer functions of the TMS44C251. RAS is similar to a chip enable
in that it activates the sense amplfiers as well as the row decoder. CAS is a control input that latches
the states of the column address and DSF to control various DRAM and Transfer functions. CAS also acts
as an output enable for the DRAM output pins.
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special function select (DSF)
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The Special Function Select input is latched on the falling edges of RAS and CAS, similarly to an address,
and serves four functions. First, during write cycles DSF invokes persistent write per bit operation. If TRG = 1,
W=0, and DSF =0 on the falling edge of RAS, the write mask will be reloaded with the data present on
the DO pins. If DSF = 1 , the mask will not be reloaded but will retain the data from the last mask reload cycle.
Second, DSF is used to change the internally stored write per bit mask register (or write mask) via the
load write mask cycle. The data present on the DO pins when W falls is written to the write mask rather
than to the addressed memory location. See "Delayed Write Cycle Timing" and the accompanying "Write
Cycle State Table" in the timing diagram section. Once the write mask is loaded, it can be used on
subsequent masked write per bit cycles. This feature allows systems with a common address and data
bus to use the write per bit feature, eliminating the time needed for multiplexing the write mask and input
data on the data bus.
Third, DSF is used to load an on-chip four-bit data, or "color," register via the Load Color Register cycle.
The contents of this register can subsequently be written to any combination of four adjacent column
memory locations using a 4 x 4 Block Write feature. The load color register cycle is performed using normal
write cycle timing except that DSF is held high on the falling edges of RAS and CAS. Once the color register
is loaded, it retains data until power is lost or until another load color register cycle is performed.
After loading the color register, the block write cycle can be enabled by holding DSF high on the falling
edge of CAS. During block write cycles, only the seven most significant column addresses (A2-A8) are
latched on the falling edge of CAS. The two least significant addresses (AO-A 1) are replaced by the four
DO bits, which are also latched on the later of CAS or W falling. These four bits are used as an address
mask and indicate which of the four column address locations addressed by A2-A8 will be written with
the contents of the color register during the write cycle, and which ones will not. DOO enables a write
to column address A 1 = 0, AO = 0; DO 1 enables a write to A 1 = 0, AO = 1; D02 enables a write to A 1 = 1,
AO = 0; and D03 enables a write to A 1 = 1, AO = 1. A logic level 1 enables a write and a logic level 0 disables
the write. A maximum of 16 bits can be written to memory during each CAS cycle (see Figure 1, Block
Write Diagram).
Fourth, the DSF pin is used to invoke the split register transfer and serial access operation, described in
the sections "Transfer Operation" and "Serial Operation."
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-83
>
C
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
N
DQ
~
. .
LOAD
COLOR
REGISTER
N+3
N+1
>--......t___----.
>--1
~~~------~;---\~--------------~~
DSF
J
\ ____---J/
DQ
BLOCK WRITE CYCLES
COLOR REGISTER LOAD
FIGURE 1. BLOCK WRITE DIAGRAM
4-84
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
write enable, write per bit enable (W)
en
The W pin enables data to be written to the DRAM and also is used to select the DRAM write per bit mode
of operation. A logic high level on the W input selects the read mode and logic low level selects the write
mode. In an Early Write cycle, W is brought low before CAS and the DRAM output pins (DO) remain in
the high-impedance state for the entire cycle. During DRAM write cycles, holding W Iowan the falling
edge of RAS will invoke the write per bit operation. Two modes of write per bit operation are supported.
Case 1. If DSF = 0 on the falling edge of RAS, the write mask is reloaded. Accordingly, a four-bit binary
code (the write per bit mask) is input to the device via the random DO pins and is latched on the falling
edge of RAS. The write per bit mask selects which of the four random I/Os are written and which are
not. After RAS has latched the write mask on-chip, input data is driven onto the DO pins and is latched
on the falling edge of the later of CAS or W. If a 0 was strobed into a particular I/O pin on the
falling edge of RAS; data will not be written to that I/O. If a 1 was strobed into a particular 110 pin on
the falling edge of RAS, data will be written to that I/O.
~
..
Case 2. If DSF = 1 on the falling edge of RAS, the mask is not reloaded from the DO pins but instead retains
the value stored during the last write per bit mask reload. This mode of operation is known as Persistent
Write per Bit, since the write per bit mask is persistent over an arbitrary number of cycles.
See the corresponding timing diagrams for details. IMPORTANT: The write per bit operation is invoked
only if W is held low on the falling edge of RAS. If W is held high on the falling edge of RAS, write per
bit is not enabled and the write operation is identical to that of standard x 4 DRAMs.
data I/O (DQO-DQ3)
DRAM data is written during a write or read-modify-write cycle. The falling edge of W strobes data into
the on-chip data latches. In an early write cycle, W is brought low prior to CAS and the data is strobed
in by CAS with data setup and hold times referenced to this signal. In a delayed write or read-modify-write
cycle, CAS will already be low. Thus, the data will be strobed-in by W with data setup and hold times
referenced to this signal.
The three-state output buffers provide direct TTL compatibility (no pull-up resistors required) with a fanout
of two Series 74 TTL loads. Data-out is the same polarity as Data-in. The outputs are in the high impedance
(floating) state as long as CAS or TRG is held high. Data will not appear at the outputs until after both
CAS and TRG have been brought low. Once the outputs are valid, they remain valid while CAS and TRG
are low. CAS or TRG going high returns the outputs to a high-impedance state. In an early write cycle,
the outputs are always in the high-impedance state. In a register transfer operation (memory to register
or register to memory), the outputs remain in the high-impedance state for the entire cycle.
enhanced page mode
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling
edge of CAS latches the column addresses. This feature allows the TMS44C251 to operate at a higher
data bandwidth than conventional page-mode parts, since data retrieval begins as soon as column address
is valid rather than when CAS transitions low. This performance improvement is referred to as "enhanced
page mode." Valid column address may be presented immediately after row address hold time has been
satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after talC) max
(access time from CAS low), if ta(CA) max (access time from column address) has been satisfied. In the
event that column addresses for the next page cycle are valid at the time CAS goes high, access time
for the next cycle is determined by the later occurrence of talC) or ta(CP) (access time from rising edge
of CAS).
TEXAS
"'J1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
~
CJ
"eCO
4-85
c
C
>-
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
Enhanced page mode operation allows faster memory access by keeping the same row address while
selecting random column addresses. The time for row address setup, row address hold, and address
mUltiplex is thus eliminated, and a memory cycle time reduction of up to 3 x can be achieved, compared
to minimum RAS cycle times. The maximum number of columns that may be accessed is determined by
the maximum RAS low time and page mode cycle time used. The TMS44C251 allows a full page (512
cycles) of information to be accessed in read, write, or read-modify-write mode during a single RAS low
period using relatively conservative page mode cycle times.
..
, During write per bit operations, the DO pins are used to load the write per bit mask register using either
mode of write per bit operation described above under the W pin description.
During block write operations, the DO pins are used to load the on-chip color register during the load color
register cycle and are also used as a write enable during block, write cycles.
refresh
A refresh operation must be performed to each row at least once every eight milliseconds to retain data.
Since the output buffer is in the high-impedance state (unless CAS is applied), the RAS-only refresh sequence
avoids any output during refresh. Strobing each of the 512 row addresses with RAS causes all bits in
each row to be refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power.
GND
This pin is reserved for the manufacturer's test operation. It is an input and should be tied to system ground
to ensure proper device operation.
IMPORTANT: GND is not connected internally to VSS.
CAS-before-RAS refresh
CAS-before-RAS refresh is accomplished by bringing CAS low earlier than RAS. The external row address
is ignored and the refresh address is generated internally.
4-86
TEXAS
~
INSTRUMENTS
POST OFFice BOX 1443 •
HOUSTON, TeXAS 77001
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
TABLE 1. FUNCTIONAL TRUTH TABLE
~t
CAS
RAS FALL
T
Y
FALL
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ADDRESS
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000-3
CASt
CAS
TRG
W
DSF
SE
DSF
RAS
CAS
RAS
R
0
X
1
X
X
X
X
X
X
X
T
1
0
0
X
0
X
X
X
T
T
T
T
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
1
X
1
X
X
X
X
X
X
R
1
1
0
0
X
0
R
1
1
0
0
X
1
R
1
1
0
1
X
0
R
1
1
0
1
X
1
R
1
1
1
0
X
0
R
R
R
1
1
1
1
1
1
1
1
1
0
1
1
X
X
X
1
ROW
TAP
ADDR
POINT
ROW
TAP
ADDR
POINT
REFRESH
TAP
ADDR
POINT
ROW
TAP
ADDR
POINT
ROW
TAP
ADDR
POINT
ROW
ADDR
X
X
X
SE)
SERIAL WRITE-MODE ENABLE
(PSEUDO-TRANSFER WRITE)
MEMORY TO REGISTER TRANSFER
X
X
X
COL
WRITE
VALID
LOAD AND USE WRITE MASK,
ADDR
MASK
DATA
WRITE DATA TO DRAM
(TRANSFER READ)
SPLIT REGISTER TRANSFER
READ (MUST RELOAD TAP)
COL
WRITE
AD DR
LOAD AND USE WRITE MASK,
A2-A8
MASK
MASK
BLOCK WRITE TO DRAM
ROW
COL
AD DR
AD DR
ROW
COL
A2-A8
ROW
COL
ADDR
ADDR
ROW
COL
ADDR
A2-A8
REFRESH
ADDR
X
X
X
X
X
X
X
X
VALID
PERSISTENT WRITE PER BIT,
DATA
WRITE DATA TO DRAM
ADDR
PERSISTENT WRITE PER BIT,
MASK
BLOCK WRITE TO DRAM
VALID
NORMAL DRAM READ/WRITE
DATA
(NON MASKED)
ADDR
BLOCK WRITE TO DRAM
MASK
WRITE
MASK
COLOR
DATA
(NON MASKED)
LOAD WRITE MASK
LOAD COLOR REGISTER
tR = RANDOM ACCESS OPERATION; T = TRANFER OPERATION
tDOO-3 ARE LATCHED ON THE LATER OF W OR CAS FALLING EDGE.
AD DR MASK = 1 WRITE TO ADDRESS LOCATION ENABLED
WRITE MASK = 1 WRITE TO 1/0 ENABLED
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
C
C
AL TERNA TE TRANSFER WRITE
(INDEPENDENT OF
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(TRANSFER WRITE)
ROW
ADDR
1
X
REGISTER TO MEMORY TRANSFER
ADDR
REFRESH
0
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CAS-BEFORE-RAS REFRESH
X
ADDR
~
FUNCTION
W
4-87
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
random port to serial port interface
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RANDOM-ACCESS PORT
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COL
COL
COL
COL
o
255
256
511
ROW
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AVS
DSF
W
Sf
SC
AO-AS
FIGURE 2. BLOCK DIAGRAM SHOWING ONE RANDOM AND ONE SERIAL 1/0 INTERFACE
random address space to serial address space mapping
The 512 bits in each of the four data registers of the SAM are connected to the 512 column locations
of each of the four random lIas. Data can be accessed in or out of the SAM starting at any of the 512
data bit locations. This start location is selected by addresses AO through A8 on the falling edge of CAS
during any transfer cycle. The SAM is accessed starting from the selected start address, proceeding from
the lowest to the highest significant bits. After the most significant bit position '(511) is accessed, the
serial counter wraps around such that bit 0 is accessed on the next clock pulse. The selected start address
is stored and used for all subsequent transfer cycles until CAS is again brought low during any
transfer cycle. Thus, the start address can be set once and CAS held high during all subsequent transfer
cycles and the start address point will not change regardless of data present on AO through A8.
split register mode random address to serial address space mapping
In split register transfer operation, the serial data register is split into halves, the low half containing bits
through 255 and the high half containing bits 256 through 511. When a split register transfer cycle
is performed, the tap address must be strobed in on the falling edge of CAS. The most significant column
address bit (A8) determines which register half will be reloaded from the memory array. The eight remaining
column address bits (AO-A 7) are used to select the SAM starting location for the register half selected
by A8. Thus when bit 255 or 511 is reached, the next bit read out will be from the previously loaded start
location.
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4-88
TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS44C251
262.144 BY 4·BIT MULTIPORT VIDEO RAM
To guarantee proper operation when using the split register read transfer feature, a non-split register transfer
must precede any split register sequence. The serial start address must be supplied for every split register
transfer.
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transfer operations
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As illustrated in Table 1, the TMS44C251 supports five basic transfer modes of operation:
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1. Normal Write Transfer (SAM to DRAM)
2. Alternate Write Transfer (independent of the state of SE)
3. Pseudo Write Transfer (Switches serial port from serial out mode to serial in mode. No actual
data transfer takes place between the DRAM and the SAM.)
4. Normal Read Transfer (Transfer entire contents of DRAM to SAM)
5. Split Register Read Transfer (Divides the SAM into a high and a low half. Only one half is
transferred to the SAM while the other half is read from the serial I/O port.)
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transfer register select (TRG)
Transfer operations between the memory array and the data registers are invoked by bringing TRG low
before RAS falls. The states of W, SE, and DSF, which are also latched on the falling edge of RAS, determine
which transfer operation will be invoked. (See Table 2.)
During read transfer cycles, TRG going high causes the addressed row of data to be transferred into the
data register. Although the previous data in the data register is overwritten, the last bit of data appearing
at SDO before TRG goes high will remain valid until the first positive transition of SC after TRG goes high.
The data at SDO will then switch to new data beginning from the selected start, or "tap," position.
transfer write enable (W)
In register transfer mode, W determines whether a read or a write transfer will occur. To perform a write
transfer, Wand SE are held low as RAS falls. If SE is high during this transition, no transfer of data from
the data register to the memory array occurs, but the SDQs are put into the input mode. This allows serial
data to be input into the SAM. An alternative way to perform the transfer write cycle is by holding DSF
high on the falling edge of RAS. In this way, the state of SE is a Don't Care as RAS falls. To perform
a read transfer operation, W is held high and SE is a Don't Care as RAS falls. This cycle also puts the
SDOs into the read mode, allowing serial data to be shifted out of the data register. (See Table 2.)
column enable (CAS)
If CAS is brought low during a control cycle, the address present on the pins AO through AS will become
the new register start location. If CAS is held high during a control cycle, the previous tap address will
be retained from the last transfer cycle in which CAS went low to set the tap address.
addresses (AO through AS)
Nine address bits are required to select one of the 512 possible rows involved in the transfer of data to
or from the data registers. The states of AO-AS are latched on the falling edge of RAS to select one
of 51 2 rows for the transfer operation.
To select one of the 512 positions in the SAM from which the first serial data will be read out, the appropriate
9-bit column address (AO-AS) must be valid when CAS falls. However, the CAS and start (tap) position
need not be supplied every cycle, only when changing to a different start position.
In split register transfer mode, the most siginificant column address bit (AS) selects which half of the register
will be reloaded from the memory array. The remaining eight addresses (AO-A 7) determine the register
starting location for the register to be reloaded.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-S9
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
special function input (OSF)
..
In read transfer mode, holding DSF high on the falling edge of RAS selects the split register mode read
transfer operation. This mode divides the serial data register into a high order half and a low order half;
one active, and one inactive. When the cycle is initiated, a transfer occurs between the memory array
and either the high half or the low half register, depending on the state of most significant column address
bit (A8) that is strobed in on the falling edge of CAS. If A8 is high, the transfer is to the high half of the
register. If A8 is low, the transfer is to the low half of the register. Use of the split register mode read
transfer feature allows on-the-fly read transfer operation without synchronizing TRG to the serial clock.
The transfer can be to either the active half or the inactive half register. If the transfer is to the active
register, with an uninterrupted serial data stream, then the timings td(SCTR) and td(THSC) must be met .
In write transfer mode, holding DSF high on the falling edge of RAS permits use of an alternate mode of
transfer write. This mode allows SE to be high on the falling edge of RAS without performing a pseudo
write transfer, with the serial port disabled during the entire transfer write cycle.
serial access operation
Refer to Tables 2 and 3 for the following discussion on serial access operation.
serial clock (SC)
Data (SDO) is accessed in or out of the data registers on the rising edge of SC. The TMS44C251 is designed
to work with a wide range of clock duty cycles to simplify system design. Since the data registers comprising
the SAM are of static design, there are no SAM refresh requirements and there is no minimum SC clock
operating frequency.
serial data input/output (SOOO-S003)
SD and SO share a common I/O pin. Data is input to the device when SE is low during write mode and
data is output from the device when SE is low during read mode. The data in the SAM will be accessed in
the direction from least significant bit to most significant bit. The data registers operate modulo 512. Thus,
after bit 511 is accessed, the next bits to be accessed will be bits 00, 01, 02, and so on.
serial enable (SE)
The Serial Enable pin has two functions: first, it is latched on the falling edge of RAS, with both TRG and
Vii low to select one of the transfer functions (see Table 3). If SE is low during this transition, then a transfer
write occurs. If SE is high as RAS falls and DSF is low, then a write mode control cycle is performed.
The function of this cycle is to switch the SDOs from the output mode to the input mode, thus allowing
data to be shifted into the data register. NOTE: All transfer read and serial mode enable (pseudo transfer
write) operations will perform a memory refresh operation on the selected row.
Second, during serial access operations, SE is used as an SDO enable/disable. In the write mode, SE is
used as an input enable. SE high disables the input and SE low enables the input. To take the device out
of the write mode and into the read mode, a transfer read cycle must be performed. The read mode allows
data to be accessed from the data register. While in the read mode, SE high disables the output and SE
low enables the output.
IMPORTANT: While SE is held high, the serial clock is NOT disabled. Thus, external SC pulses will increment
the internal serial address counter regardless of the state of SE. This ungated serial clock scheme minimizes
access time of serial output from SE low since the serial clock input buffer and the serial address counter
are not disabled by SE.
4-90
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
split register active status output (QSF)
en
QSF is an OPEN DRAIN output pin. During the split register mode of serial access operation, QSF indicates
which half of the serial register in the SAM is being accessed. If QSF is low, then the serial address pointer
is accessing the low (least significant) 256 bits of the SAM. If QSF is high, then the pointer is accessing
the higher (most significant) 256 bits of the SAM.
QSF changes state upon crossing the boundary between the two register halves. When the SAM is not
operating in split register mode, the QSF output remains in the high-impedance state.
QSF is designed as an open drain output to allow OR-tying of QSF outputs from several chips. Thus, an
external pull-up resistor is required for the zero to one transition Oli QSF and the output risetime is determined
by the load capacitance and the value of the pull-up resistor. The specification for QSF switching time
assumes a pull-up resistor of 820 ohms and a load capacitance of 50 picofarads.
TABLE 2. TRANSFER OPERATION LOGIC
TRG
W
SE
DSF
0
0
0
0
0
0
0
0
1
1
0
X
1
X
X
X
Register to memory (write) transfer
1
0
0
1
Alternate register to memory transfer
~
C
MODE
Serial write mode enable
Memory to register (read) transfer
Split register read transfer
NOTE: Above logic states are assumed valid on the falling edge of RAS.
TABLE 3. SERIAL OPERATION LOGIC
SE
LAST TRANSFER CYCLE
Alternate register to memory
1
0
1
0
1
Serial write mode enable t
Serial write mode enable t
Memory to register, split register
Memory to register, split register
SDa
Input Disabled
Input Enable
Input Disable
Output Enabled
Hi-Z
t Pseudo transfer write
power up
After power up, the power supply must remain at its steady-state value for 1 /Ls. In addition, RAS must
remain high for 100 /Ls immediately prior to initialization. Initialization consists of performing two RAS cycles
before proper device operation is achieved.
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-91
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
absolute maximum ratings over operating free-air temperature t
C
'<
Voltage on any pin except DO and SDO (see Note 1) ....................... -1.0 V to 7.0 V
Voltage on DO and SDO (see Note 1) .................................... - 1.0 V to Vee
Voltage range on Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.0 V to 7 V
Short circuit output current (per output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OOC to 70 0 e
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 °e to 1 50 0 e
::::I
m
3
5"
~
..
s:en
l>
C
<
l>
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only. and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
:2
VCC
Supply voltage
("')
VSS
Supply voltage
-
VIH
High-level input voltage
m
:2
VIL
Low-level input voltage (see Note 2)
VOH
High-level output voltage
o
VOL
Low-level output voltage
TA
Operating free-air temperature
."
::xl
S
MIN
NOM
MAX
4.5
5.0
0.0
5.5
V
VCC
V
2.4
-1.0
2.4
-1.0
0
25
UNIT
V
0.8
V
VCC
V
0.4
70
°c
V
NOTE 2: The algebraic convention. where the more negative (less positive) limit is designated as minimum. is used in this data sheet for
logic voltage levels only.
l>
:::!
o
:2
4-92
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C251
262.144 BY 4·BIT MULTIPORT VIDEO RAM
electrical characteristics over full ranges of recommended operating conditions
TEST
PARAMETER
VOH
VOL
High level output voltage
10H
Low level output voltage
10L
QSF low level
VOL(QSF) output voltage
'L
10
Output current leakage
MIN
= -5.0 mA
= 4.2 mA
2.4
'OL(QSF)
=
V,
Input leakage current
TMS44C251-10
CONDITIONS
=
MIN
MAX
2.4
TMS44C251-15
MIN
MAX
2.4
en
UNIT
~
V
a:
0.4
0.4
0.4
V
0.4
0.4
0.4
V
±10
±10
±10
I'A
±10
±10
±10
I'A
6 mA
VCC
(J
'ECO
..
>
0 V to VCC
Vo
~
r:
0 V to 5.8 V
VCC = 5.5 V
All other pins
=
TMS44C251-12
MAX
= 0 V to VCC
= 5.5 V
C
2
o
PARAMETER
ICCl
Operation current
tc(RW)
ICC1A
ICC2
tc(SC)
= Minimum
= Minimum
Standby current
All Clocks
=
=
TMS44C251-10
MIN
TMS44C251-12
MAX
Standby
MIN
MAX
TMS44C251-15
MIN
MAX
90
80
70
110
95
85
5
5
5
Active
35
30
30
Standby
90
80
70
110
95
85
Standby
50
45
40
Active
60
55
50
Standby
80
70
65
110
95
85
90
80
70
110
95
85
Active
Standby
i=
UNIT
mA
tc(P)
ICC4A
ICC5
=
tc(SC)
ICC5A
ICC6
tc(SC)
Minimum
= Minimum
= Minimum
Data transfer current
tc(RW)
ICC6A
=
CAS-before-RAS current
tc(RW)
tc(SC)
NOTE 3: VCC equal to 5.0 V ± 0.5 V and the bias on pins under test is 0.0 V.
~
2
switching characteristics over recommended supply voltage range and operating free-air temperature
range (see Note 4)
C
(")
PARAMETER
m
-
Access time from
ta(C)
2
."
ta(CA)
o::xJ
ta(CP)
~
l>
ta(R)
::!
ta(G)
2
ta(Sa)
TEST
ALT.
CONDITION
SYMBOL
td(RLCL)
=
MAX
CAS
=
column address
td(RLCL)
MAX
Access time from
td(RLCL)
=
Access time from
CAS high
Access time from
RAS
MAX
td(RLCL)
MAX
=
TMS44C251-10
MIN
MAX
TMS44C251-12
MIN
MAX
TMS44C251-15
MIN
MAX
tCAC
25
30
35
ns
tCAA
50
60
75
ns
tCAP
55
65
80
ns
tRAC
100
120
150
ns
tOEA
25
35
45
ns
Access time of a
o
from TRG low
Access time of sa
from SC high
Access time of sa
ta(SE)
from
SE low
Access time of
ta(aSF)
aSF from SC high
Random output
tdis(CH) disable time from
CAS high
tdis(G)
Random output
disable time from
UNIT
C1
=
50 pF
tSCA
30
35
40
ns
C1
= 50 pF
tSEA
20
25
30
ns
60
60
60
ns
C1 = 50 pF
See Figure 3
C1
=
100 pF
tOFF
0
25
0
30
0
35
ns
C1
=
100 pF
tOEZ
0
25
0
30
0
35
ns
25
ns
TAG high
Serial output
tdis(SE)
disable time from
C1
= 50 pF
20
tSEZ
SE high
NOTE 4: Switching times assume C 1
4-94
100 pF unless otherwise noted.
TEXAS
-I/}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
20
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
timing requirements over recommended supply voltage range and operating free·air temperature range t
ALT.
TMS44C251-10
SYMBOL
MIN
TMS44C251-12
MAX
MIN
MAX
TMS44C251-15
MIN
MAX
UNIT
tc(rd)
Read cycle time (see Note 5)
tRC
190
220
260
ns
tc(W)
Write cycle time
twc
190
220
260
ns
tc(rdW)
Read-modify-write cycle time
265
305
355
ns
tc(P)
Page-mode read, write cycle time
tRWC
tpc
60
70
90
ns
tc(RDWP)
Page-mode read-modify-write cycle time
tRWC
125
150
180
ns
tc(TRD)
Transfer read cycle time
tRC
190
220
260
ns
tc(TW)
Transfer write cycle time
twc
190
220
260
ns
tc(SC)
Serial clock cycle time
tscc
30
35
40
ns
tw(CH)
Pulse duration,
tcp
20
25
35
tw(CL)
Pulse duration,
Note 6)
tCAS
25
RAS low (see Note 7)
tRAS
100
twp
25
25
35
25
35
40
ns
15
ns
"C"AS high
"C"AS low (see
tw(RH)
Pulse duration, RAS high
twiRL)
Pulse duration,
tw(WL)
Pulse duration, W low
tw(TRG)
Pulse duration, TRG low
tRP
75,000
35
75,000
120
80
75,000
40
75,000
150
ns
Pulse duration, SC high
tsc
10
Pulse duration, SC low
tscp
10
12
15
ns
tsu(CA)
Column address setup time
tASC
0
0
0
ns
tsu(SFC)
DSF setup time before
0
0
0
ns
tsu(RA)
Row address setup time
tASR
0
0
0
ns
tsu(WMR)
tWSR
0
0
0
ns
tMS
0
0
0
ns
tTLS
0
0
0
ns
tESR
0
0
0
ns
tsu(SFR)
RAS low
DO setup time before RAS low
TAG setup time before RAS low
"SE setup time before RAS low
DSF setup time before RAS low
0
0
0
ns
tsu(DCL)
Data setup time before
tDSC
0
0
0
ns
tsu(DWL)
Data setup time before W low
tDSW
0
0
0
ns
tsu(rd)
Read command setup time
tRCS
0
0
0
ns
twcs
-5
-5
-5
ns
tCWL
25
30
35
ns
tsu(DOR)
tsu(TRG)
tsu(SE)
"C"AS low
Early write command setup time
tsu(WCL)
tsu(WCH)
before CAS low
Write setup time before
CAS high
Write setup time before RAS
tRWL
35
40
45
ns
tsu(SDS)
SD setup time before SC high
tSDS
3
3
3
ns
th(CLCA)
Column address hold time after CAS low
tCAH
20
20
25
ns
th(SFC)
DSF hold time after CAS low
20
20
25
ns
th(RA)
Row address hold time after
tRAH
15
15
20
ns
th(TRG)
TAG hold time after RAS low
tTLH
15
15
20
ns
tREH
15
15
20
ns
tRWH
15
15
20
ns
tsu(WRH)
high with TRG
= W = low
RAS low
SE hold time after RAS low
th(SE)
with
TAG = W = low
Write mask, transfer enable hold
th(RWM)
time after RAS low
i=
-
C
ns
75,000
100
90
CJ
"eca
oLL
2
w
o
2
~
C
s:
th(RLCA)
en
(see Note 8)
CAS low
MAX
TMS44C251-12
MIN
TMS44C251-15
MAX
MIN
MAX
UNIT
15
20
ns
15
15
20
ns
tAR
45
45
55
ns
ns
DSF hold time after RAS low
Column address hold time after RAS low
MIN
15
tMH
(write mask operation)
TMS44C251-10
th(CLD)
Data hold time after
tDH
25
30
40
th(RLD)
Data hold time after RAS low (see Note 8)
tDHR
50
55
70
ns
th(WlD)
Data hold time after W low
tDH
25
30
40
ns
th(CHrd)
Read hold time after CAS (see Note 9)
tRCH
0
0
0
ns
th(RHrd)
Read hold time after
RAS (see Note 9)
tRRH
10
10
10
ns
th(ClW)
Write hold time after CAS low
tWCH
25
35
45
ns
th(RLW)
Write hold time after
RAS low
tWCR
50
60
75
ns
:2
th(WLG)
'fRG hold time after W low (see Note 10)
tOEH
25
30
40
ns
th(SDS)
SD hold time after SC high
tSDH
5
5
5
ns
m
th(SHSO)
SO hold time after SC high
tSOH
10
10
10
ns
td(RLCH)
Delay time. RAS low to CAS high
tCSH
100
120
150
ns
:2
td(CHRL)
Delay time.
CAS high to RAS low
tCRP
0
0
0
ns
o
td(CLRH)
tRSH
35
40
45
ns
tCWD
60
75
90
ns
tRCD
25
60
75
ns
l>
c
<
l>
(j
-
"T1
Delay time CAS low to
:xl
RAS high. write (see Note 11)
Delay time. CAS low to W low
S
td(CLWL)
l>
(see Notes 12 and 13)
Delay time, CAS low to
td(RLCL)
::!
o
:2
CAS low (see Notes 14 and 15)
75
25
85
110
ns
td(CARH)
Delay time. column address to
RAS high
tRAL
50
td(CACH)
Delay time. column address to
CAS high
tCAl
50
60
75
ns
tRWD
135
160
195
ns
tAWD
85
100
120
ns
tCHR
25
25
30
ns
tCSR
10
10
15
ns
Delay time. RAS low to W low
td(RLWL)
(see Note 12)
Delay time. column address to W low
td(CAWL)
(see Note 12)
Delay time, RAS low to CAS high
td(RLCH)
(see Note 16)
Delay time,
td(CLRL)
CAS low
to RAS low
(see Note 16)
Delay time RAS high to CAS low
td(RHCL)
td(CLGH)
(see Note 16)
Delay time. CAS low to TRG high
tRCP
5
5
5
ns
tCTH
25
35
40
ns
Continued next page.
tTiming measurements are referenced to VIL max and VIH min.
NOTES: 8. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
9. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
10. Output Enable controlled write. Output remains in the high-impedance state for the entire cycle.
11. Write cycles only.
12. Read-modify write operation only.
.
13. 'i'RG must disable the output buffers prior to applying data to the DO pins.
14. Read cycles only.
15. Maximum value specified only to guarantee access time.
16. CAS-before-RAS refresh operation only.
4-96
30
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
timing requirements over recommended supply voltage range and operating free-air temperature range t
(concluded)
ALT.
TMS44C251-10
SYMBOL
Delay time, TRG high before
td(GHD)
-- I Early load
I
Delay time, RAS low to TRG
high (see Notes 17 and 18)
Mid-line real-
tRTH
time load
high after TRG high (see Note 18)
high after TRG high (see Note 18)
45
55
ns
tTSL
10
10
15
ns
-10
-10
-15
ns
-
40
Delay time, RAS high to SC high
td(RHSC)
c
ns
tCSD
Delay time, SC high to SE high
td(SCSE)
th(TRG)
95
ns
high (see Note 18)
W=
th(TRG)
80
"eca
:2
(see Notes 18 and 19)
TRG =
th(TRG)
CJ
ns
30
70
UNIT
115
Delay time, SC high to RAS low with
td(SCRL)
MAX
95
Delay time, TRG high to RAS
td(THRH)
30
MIN
85
Delay time, SC high to TRG high
td(SCTR)
MAX
(see Note 23)
o
~
~
oLL
-w
:2
CJ
:2
~
50PF
VSS
bl QSF LOAD CIRCUIT
al LOAD CIRCUIT EXCEPT QSF
C
2:
B-1T
le1
FIGURE 3. LOAD CIRCUIT
read cycle timing
om
-2:
."
o:lJ
s:
J>
::!
o
2:
I~
TRG
!,--th(TRGI
~tW(T~GI~ I
! ~....,_"'ft"'JOO"lI~---I~II~
I
i-+1,.. ~.: r
I
4-98
I I
W' I ~\ \{
tsu(rdl"'"
I
I
I
~h(CHrdl
TEXAS
I
I
I
"'J1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
th(RHrd)
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
early write cycle timing
en
:?!
1........-------------tc(WI------------+;~i
I
~
r--tW(RHI---l
"eca
___---,..! 1........---------tW(RLI--------~
.. 1
N
RAS
I 1. ...t---------td(RLCHI---------i~~1
tt --II
Vi
I
~
CJ
-e; ~
I+-
c
>C
I... . - - - - - - t d (CLRH 1----""1!1t-ttPn
tt
I
1ol
.
....- td (RLCL)--.ll.oI.....--_ _ _ _ t w (CL) -----..t~,
td(CHRL)-----..j
I
I
I
I
!
I
iIii
I
""'+---tw(CH) -----t
2:
AO-AS
o
'V'V''V,"",n.
-'
tsu(SFR)i
I.!
~
th(SFRrt..J
I
I
I--
I I I!41.......-.......
~ rrtsU(SFCI,
I
+-!
DSF~:;2
--I
!
-bl
!+i-tsu(TRG)
i4- t h(TRG)
I I
I I
I
th(SFC)
i=
c
~
I
I
-w
:2
s:
td(ClRHI'-----1-+II."
-
~
,.......twlRHI---..l
I
I
I
-~I------tw(Cll
(I)
----~--~~~
CAS
~
-I
td(CHRll~
I ~~------~
I I ,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- T
,
,
/4--t--t w (CHI
l>
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.-,
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~2
,
tsu(SFRI~
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I
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1
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."
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o
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o
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~
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r-r'
tsuiDORI--j
thIRDOI.....,
2
I.
~
I
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I
,
:
I
1
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I
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I
td(GHDI--ri
, , ,.
,
,
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~
f4- t h(RWMI
TRG
th(SFCI
,..
thlRlWI
i
I~ I
I
!N
tsulDWll....!
tsu(WRHI
tsulWCHI
I
-I
-,
,.,
-I
thlClWI
l&l888888W
t--r
,~
twlWll
J - t - th I WlDI - 1
thlRLDI
-I
I,
.
1
,
-,
DO-------5--------~
NOTE 24: See "Write Cycle State Table" for the logic state of "1", "2", "3", "4", and "5",
4-100
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C251
262.144 BY 4·BIT MULTIPORT VIDEO RAM
write cycle state table
CYCLE
Write mask load/use
Write DOs to I/Os
Write mask load/use
Block write
Use previous write mask
Write DOs to I/Os
Use previous write mask
Block write
Load write mask on later of
W fall
and CAS fall
Load color register on later of
W fall
and CAS fall
Write mask disabled,
Block write to all I/Os
Normal early or late
Write operation
en
STATE
1
2
3
0
0
0
0
1
0
1
0
0
1
1
0
1
0
1
1
1
1
0
1
1
0
0
1
4
5
WRITE
VALID
MASK
DATA
WRITE
ADDR
MASK
MASK
DON'T
VALID
CARE
DATA
DON'T
ADDR
CARE
MASK
DON'T
WRITE
CARE
MASK
DON'T
COLOR
CARE
DATA
DON'T
ADDR
CARE
MASK
DON'T
VALID
CARE
DATA
:?!
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2
(.)
2
«
>
c
«
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4- .101
··TMS44C251
262.144 BY4·BIT MULTIPORT VIDEO RAM
read-write/read-modify-write cycle timing
C
'<
:;::,
/II-t----------------tc(rdw-------------~·1
I
I
C»
3
RASN
c;"
,
-
I I
I
l>
~
I I
,
...
1_1--------td(CLRHI------~-.,i
..
t W ( C L I - - - - - -.......
,
I r--td(RLCLI~,..I---______
CAS 'hlj L.,
~
J.ltsU(RAlltsu(CAI1
'I
I th(RLCAI
1'rr1
~
2
~tw(RHI
iJ;!
}1]
I
I
th(CLCAI
AO-AB
o
I
I
1 I I 1 - t - - - - - - - - - - - - - - tw ( R L I - - - - - - - - - - - -...,
.,
""CHRL,
i\-
II!..-tW(CH1-.J
DON'T CARE J\I""IV'VV'A,N\/VVV""IV\.
DSF
("')
II
m
-
2
I I
I!-LI
."
ol:J
I
I
ril
s:l>
--I
1-~th(RW~)
"-+tsu(WMRI
:
W~:;3 20V
:::!
o
14
I I-
ta(RI
t:-tSU(WCHI~
,
I
I
,
II-
Ii
I
I
I
I
th(WLGI II
I
i
th(CLW)
td(CLWLI
DO
~_ _4_~~
_
:
1
I
NL
I
.,J ---
1
t,"'DWLI •
I
1
O~~~~T ~
J4-
--t
I
-,
.1
-:
.! r-- tw(WLI~
i
1_
ta(GI-!
,
td(RLWLI:
.:
-I
(4-td( GHD1 -..i
tsu(DORI~ ~.
--.,J
L
I • ~~t==--:Clr-
2
I
tsu(WRHI----'
~
~
----1
th(WLDI,
1
.
~
5
----------~
(oe-tdis(GI
NOTE 25: See "Write Cycle State Table" for logic state of ",", "2", "3", "4", and "5". Same logic oJ delayed write cycle.
4-102
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
enhanced page-mode read cycle timing
tWIRHI1
t-t--------------twIRLI--------------..,."'1 I
r1
u
.
1 1 I
~
11
~------------------------------------------------I
.....- - - tdIRLCLI----ta~1
t+-- tdICLI;IH~ 1 1
....... twlCLI--' ~twICHI~
I
~tdICHRLI~
f\\l
I
tdlRLCHl1
,
I
tclPI
~thICLC:AI
.•
I
tdlCARHI
I
COLUMN
AO-AS
HtSUISFRI
I
-;
~I
I
I
~ tsulTRGI
ll
I
1
I
I
'U
I
I
I
I-
~vVC~~"V'
..
I
I
I
, I
I
I
,I ~~~I~__~______~
I ____~__________- - J I 1I
I
11
I
-..-.I ~II tsulWMR) I
I
I
I- I
tsulrdl,
w X>O'"
i
I
I
I
I I f+th.'TRG'..-.ik
W
!I II
I I
I I
-I
tsuICAI-\
r--thlsFRI-I
II
DSF
DQ
I
I" i
r--tdlcACHI~ I
al.
I
TRG
I:
\\1
JA
I
I
I
I
1
al
I
---t
r-talCI
~taICAI--"
1
I
~
I·
t--------taIGI--+i
talRI*
1 w:xJ/
!-
.1"
1_
1I
I
r+-- talCAI t ---..I
talCp)t
.1
11 __ •
CJ
"'Q~--------
NOTE 26: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edges of RAS and CAS to select the
desired write mode (normal. block write. etc.).
t Access time is ta(CP) or ta(CA) dependent.
:l:Output may go from the high-impedance state to an invalid data state prior to the specified access time.
TEXAS
"!I
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
2
o
i=
C
-w
lthlRHrdl-.!
I
I
"eca
4-103
2
~
C
{
I
I
!I
I;
~
tsu(SFC)~
~'hISFC:~
CO~UM~
t--
~
I
I·
I
I
:-'hISFC!~
--I
I
I
I I
I
,....
tsu(WCH)
I
I
I
I
I
I
~ tsu(WRH)----I
I
II:'~~~~~~~
3~.1~~
tsu(DOR)
It--
~
I I..
tsu(DWL) t..l
I
tsu(DCL) t ~
~ th(RDO)---
I-
I.
II
I I
I I
I t~(CARH) I ~
,I
,!
W
I
i\\l A
~ th(RWM)~
HtW(WL)~
:I~!I
I
I
»
...
tw(RH).f.--.!
td(CLRH)W-----I I
,
r--td(CH R~)-.(
~ td(CAC~)-----1
I
I
I
, I ,
,I
I
I
I
I
I
/4--t- tsu(V';'CH) ------t
i.1
I I
I
I
j..!-tsu(WMR)
o
:a
s:
!
:1
CO~UMN
!
rI
tc(P)
\ 4 - - tw (CH)----.i
,I twlCL)
I--th(CLCAt.l
~h(Rl+. i
~.~
I
."
.. ;
I
i-
f0LY!
I!
tsu(CA)~!..-
th(RA)----.I
~ : ~'hISFR)~
~
m
i
~
... ,
I_
I
II
t
...
lfl\-
.. ,
I
I
th(CLD) t
~
... 1
th(WLD)t
th(RLD)
.. :
~
NOTES: 24. See "Write Cycle State Table" for logic state of "1", "2", "3", "4", and "5".
27. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing
specifications. TRG must remain high throughout the entire page-mode operation if the late write feature is used, to guarantee
page-mode cycle time. If the early write cycle timing is used, the state of TRG is a Don't Care after the minimum period th(TRG)
from the falling edge of RAS.
.
tReferenced to CAS or W, whichever occurs last.
4-104
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
enhanced page-mode read-modify-write cycle timing
t/)
i"
twIRL)
~
1
I
,..
/4""-- tw(CL)
~
--..,.j
AO-A.~
-J..j I...- th(SFR)
tSU(SF~R)---!
f4T 1 -J
I
1
I
!
i+---td(CLRH)RD----j
H-tW(CH)
1
----.!
.,'
I '
11
1\ '{
Mtsu(CA) ' I
t+----I-I th(CLCA)
1
1:-1 f..-th(RA)
I 1
,
""T-: I
'
I
,,I th(RL~A)
1
DSF
tc(RDWP)
r--td(RLCL)RD-----ft-!
!!
tW(RH)~
"1
td(RLCH)
1 '
tsu(RA)-i
(,)
"E
I
I ,.
I
I
«a::
-,
RASN
I ,
:2:
-,
:
:COLUMN
,
1
~
\\1
I
COLUMN
1
1
1
,
/1
i
I
~
, 1
II
,
I
..
c:
>-
C
I I
1 1
rTtSU(SFC)!
"I
co
I
td(CHRL)~
.~, Jc!
2
o
i=
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:2:
1
,
a:
ou.
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U
:2
C
c
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~II
DSF~IIII~
(')
I
m
I
-2
tsu(TRG)"
I 1
1 I1
1
~I
-I
th(TRG)
,..1
th(RDO)
I
."
o
::a
w~!!
I-1 "'11 1
3:
l>
I..
::!
o
!
tsu(DOR)
DO
2
4-106
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C251
262,144 BY 4-BI1 MULTIPORT VIDEO RAM
CAS-before-RAS refresh
en
~
iioI..t---------tc(rd)-------~..~1
«
a::
!
1'~----------
\4--tw(RH)~ 1...
...~---tw(RL)---~..,
...1
;1
_ _- - J
,..
~
It'! td(RHCL)
I
:--td (CLRL)1
i
\{:
~td(RLCH)7:
r-----------------------
I I
I I
I I
TRG~
CJ
"EctI
I
I!
..
I:
>-
C
2:
o
i=
~ ~th(RWM)
tsu(WMR) , :
I
C
2
o
i=
-
-
I
~.
U
I
"Eca
II
I I
I
I
I
I
I
:I
,r--th(RA)--I
~ ---rtsu(CA)
'I"
Ith(RLCA) I
~I
!~ ~
~th(CLCA)
Q
I
I
~ CO~UMN_
;
,
I
--,'
r+ t h(SFR)~
I
I
I
;
I
2:
o
i=
C
2
H:
tsu(SFR)..-I
«
I
Y~'wIRHI-l\I.....---I ..
--tl
Iy
I
1I
I
tw(CL)
~
I
-I
_ _ _ _ _--:1.I1
N
(I)
---------~-I
I
r'hISFRI--'~
o
i=
I~
«
2E
a:
oLL
-2:w
DQ
i
td(SCRL)
I~..
I
LLl.- thIRDQ)....j
tsu(DQR)~
Ii
1 1
I
1
_, I...
U
2
I
td(RLSH) I.--td(CLSH)
I"
tw(SCH) --I
I
1\\\\\\\,
SC~
---!
i
tW(Scut
tsu(SDS)
/4ttsu (sqS) 1
SDO){ Dt:- _
td(SCSE)---t
~t
~ su(SE)
:.:
_I
tdIRHSC)
Y!
1
I
~t~(SDS)
«
>
c
«
1
1
HI-Z---+-l-----------
dI
I
~
\~l-- th(SDS)
D:~ ~17C~~'7M't":~
I4-td(SESC)...J
I
I '
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-113
TMS44C251
262.144 BY 4·BIT MULTIPORT VIDEO RAM
memory to data register transfer timing
i.
II
tWIRL)
-'
_ _ _ _ _~I II4--td(RLCL)~I
~
RAS
:
..
I
II
l>
c
AO-AS
<
l>
~
-
I
I
td(RLTH)
II
-I th(RWM)
!
I
I
::!
o
SC
~
th(SHSO)
OLD DATA
SDO
SE
I.
td(SCTR)
*
,
I4-ta(SO)-..i
2
I
I
I
II
t W (CL)+-1
I
II
.. 1
Y
I
,I..
-
~
I
I
td(THRL)
"I
1....__
.._I_t.;..d(;..T_H_R_H.;..)_ _ _ _ _ _ _ _ _ _ _ __
Vi
I-I
I
I
I
I
I
!~~
I,
II
I..
I
l>
I
I
(".
j.e-tw(SCH)~
31:
"4"
II
.
:D
~~____
_I
I
~ C~LUMN ~~~~~O~~:~~~A}X~~~~
I
I I..
'TI
o
II
t
-J...:....II
tsu(CA)
- - h(RA)'--'
I ·
I
1-..1
r--th(CLCA)
I
tsu(WMR)-t----'i
2
1t
1 -
I
ROW
TRG~
-
m
N
~th(RLCA)
I;
tSU(TRG)~
I
2
(")
r
td(RLCH)1
I
tSU(RA)-+-----i
1
I
I
I
I
!}I
I.
I
-I
tc(TRD)
I I"
-!
I
I..
I
_I
I I.
_I
III
~
~
I
td(CLSH)
I
I td(RLSH)
-\
,I
tw(SCL)
OLD DATA
\
X
td(THSC)
Vi
I.
th(SHSO)
\""""'---Ir
tc(SC)---..._-t1
r:-ta(So~"i1
OLD DATA
:M1I!'j--N-E-W-D-A-T-A---
H
L----------------------------------------------------------------------
NOTES: 33. Random mode (a outputs) remain in the high-impedance state for the entire memory to data register transfer cycle. The memory
to data register transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each
data register are written into from the 512 corresponding columns of the selected row. The data that is transferred into the
data registers may be either shifted out or transferred back into another row.
34. Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., the SO is enabled!. thus allowing
data to be shifted out of the registers. Also, the first bit to be read from the data register after TRG has gone high must be activated
by a positive transition of SC.
4-114
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS44C251
262,144 BY 4·BIT MULTIPORT VIDEO RAM
split register mode read transfer timing
I-
I
_ _ _ _~I
tc(TRO)
N
RAS
I
I"
I
td(RLCH)I
JoII-tw(CL)~
N
Ii
-H Itsu(CA)~
~
t+"th(RA)
tsU(RA)M
AO-AB
I
TAPI"'
tsuITRG)-i.--.l
I"
~
I
+
·1
I
i\
0
1
.,
I
I
th(CLCA)
-e
.U
II
I
I
I
•
11:
I
I"
I
I
I
I
I I
II
.\
.,1
I.
twiRL)
r--td(RLCL)------J
I
~
>-
C
..
I
~$;x~~~
MSB
tdlRLTH)
2
o
'1\--tdITHRL)--t
II
r-thITRG)
i=
c
x"":__N_E_W_M_S_B_ _
:
ifTAPM\. . ..,.. _-. !rBiTT"\
_J
2
I
It (SC)
.,
I c._
-' ,
!"II--tw(SCL)----
I~_' I
(,)
I
I
ttdIRHMS)-';:--
C)C)<
ROWI TAPh
A8-1
ROWI TAPI
I
I
I
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
1MS44C251
262,144 BY 4·B11 MUL TIPORT VIDEO RAM
serial data-in timing
,...
te(SC)
I . - t (SCL)-------I ~tw(SCH)----1
I
w
I I
Vi
sc\t
14-1
tsU(SDS)----l_!
---.
:E'"
~
I
r--td(SESC)----.j
SE
~~!_________________________________________________________
2
o
i=
«
The Serial Data-in cycle is used to input serial data into the data registers. Before data can be written
into the data registers via SD, the device must be put into the write mode by performing a write mode
control, or pseudo-transfer, cycle. Transfer write cycles occurring between the write mode control cycle
and the subsequent writing or data will not take the device out of the write mode. However, a transfer
read cycle during that time will take the device out of the write mode and put it into the read mode, thus
disabling the input of data. Data will be written starting at the location specified by the input address loaded
on the previous transfer cycle.
While accessing data in the serial data registers, the state of TRG is a Don't Care as long as TRG is held
high when RAS goes low to prevent data transfers between memory and data registers.
~
a:
o
LL
-w2
U
2
~
C
«
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-117
TMS44C251
262,144 BY 4-BIT MULTIPORTVIDEO RAM
serial data-out timing
c
-<
~
Q)
I,.
n'
tWlsCLli
sc~
.
~I twISCH)~
.'
L
I .--.tw'SCL)4
0I--
'\
soa
~
)4
....--ta 'SQ
M
{
Vi
I
thISHSQ)--..I
t---taISQ)--t-i
·DC
I
--e.I
I
l>
!--taISE)
SE~~____________________________________________________________
c
o
m
--J
I
..
~2
telSC)
L
3
NOTE 37: While reading data through the serial data register, the state of TRG is a Don't Care as long as TRG is held high when RAS
goes low. This is to avoid the initiation of a register to memory or memory to register data transfer operation.
-
2
."
o
The Serial Data-out cycle is used to read data out of the data registers. Before data can be read via SQ,
the device must be put into the read mode by performing a transfer read cycle. Transfer write cycles
occurring between the transfer read cycle and the subsequent shifting out of data will not take the device
out of the read mode. But a write mode control cycle at that time will take the device out of the read
mode and put it in the write mode, thus not allowing the reading of data.
:a
3:
~
o
2
4-118
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C256, TMS44C257
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORIES
JUNE 1986 - REVISED MAY 1988
N PACKAGE
•
262,144 x 4 Organization
•
Single 5·V Supply (10% Tolerance)
•
(TOP VIEW)
D01
D02
Performance Ranges:
ACCESS
TIME
ta(R)
ItRAC)
(MAX)
TMS44C25_-10 100 ns
TMS44C25_-12 120 ns
TMS44C25_-15 150 ns
ACCESS
TIME
talC)
(tCAC)
(MAX)
25 ns
30 ns
40 ns
ACCESS
TIME
ta(CA)
(tCAA)
(MAX)
45 ns
55 ns
70 ns
W
READ
OR
WRITE
CYCLE
(MIN)
190 ns
220 ns
260 ns
•
TMS44C256 - Enhanced Page Mode
Operation with CAS-Before-RAS Refresh
o
TMS44C257 - Static Column Decode
Mode Operation with CAS-Before-RAS
Refresh
RAS
7020
2
3
4
TF
5
AO
A1
A2
A3
6
7
8
9
VCC
19
18
17
16
en
12
~
A4
14
13
~
(,)
"sca
G
A8
A7
A6
A5
15
:E
VSS
D04
D03
CAS
..
c
>
Q
OJ PACKAGEt
•
Long Refresh Period . . .
512-Cycle Refresh in 8 ms (Max)
•
3-State Unlatched Output
o
o
Texas Instruments EPIC"' CMOS Process
(TOP VIEW)
D01 L. 00
D02 2
W 3
RAS 4
TF
5
22
G
A8
A7
A6
A5
A4
25
24
Lower Power Dissipation
AO
A1
A2
A3
o All Inputs and Clocks Are TTL Compatible
•
23
VSS
D04
D03
CAS
26
High-Reliability Plastic 20-Pin 300-Mil-Wide
DIP or 20/26-Lead Surface Mount (SOJ)
Package
•
Operation of Tl's Megabit CMOS DRAMs
Can Be Controlled by Tl's SN74ALS6301
and SN74ALS6302 Dynamic RAM
Controllers
o
Operating Free-Air Temperature ...
OOC to 70°C
VCC
9
,18
10
17
11
16
12
15
13
14
tThe packages shown here are for pinout reference only.
The OJ package is actually 75% of the length of the N
package.
PIN NOMENCLATURE
AO-A8
description
The TMS44C256 and TMS44C257 series are
high-speed, 1,048,576-bit Dynamic RandomAccess Memories organized as 262,144 words
of four bits each. They employ state-of-the-art
EPIC'· (Enhanced Process Implanted CMOS)
technology for high performance, reliability, and
low power at a low cost.
Address Inputs
CAS
Column-Address Strobe
DQ1-DQ4
Data In/Data Out
IT
Data-Output Enable
RAS
Row-Address Strobe
TF
Test Function
W
Write Enable
VCC
5-V Supply
VSS
Ground
operation
enhanced page mode (TMS44C256)
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is thus eliminated. The
maximum number of columns that may be accessed is determined by the maximum RAS low time and
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~at:~1~1~ ~!:~~~ti:r fI~o~:::~:t:r~~s not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
Copyright © 1986, Texas Instruments Incorporated
4-119
TMS44C256, TMS44C257
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORIES
the CAS page-mode cycle time used. With minimum CAS page cycle time, all 512 columns specified by
column addresses AO through A8 can be accessed without intervening RAS cycles.
..
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling
edge of CAS latches the column addresses. This feature allows the TMS44C256 to operate at a higher
data bandwidth than conventional page-mode parts, since data retrieval begins as soon as column address
is valid rather than when CAS transitions low. This performance improvement is referred to as "enhanced
page mode." Valid column address may be presented immediately after th(RA) (row address hold time)
has been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after
talC) max (access time from CAS lowl. if ta(CA) max (access time from column address) has been satisfied.
In the event that column addresses for the next page cycle are valid at the time CAS goes high, access time
for the next cycle is determined by the later occurrence of talC) or ta(CP) (access time from rising edge
of CAS).
static column decode mode (TMS44C257)
The static column decode mode of operation allows high-speed read, write, or read-modify-write by reducing
the number of required signal setup, hold, and transition timings. This is achieved by first addressing the
row and column in the normal manner, but after the first access maintain CAS low. Subsequently changing
the column address produces valid data at the ta(CA). The first bit is accessed in the normal manner with
read data coming out at talC) time. Similarly, write or read-modify-write cycle times can be achieved with
appropriate toggling of W. The addresses are latched during the write operation, but at the completion
of the internal write operation the addresses are unlatched.
address (AO through A8)
Eighteen address bits are required to decode 1 of 262,144 storage cell locations. Nine row-address bits
are set up on pins AO through A8 and latched onto the chip by the row-address strobe (RAS). Then nine
column-address bits are set up on pins AO through A8 and latched onto the chip by the column-address
strobe (CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar
to a chip enable in that it activates the sense amplifiers as well as the row decoder. The TMS44C256
CAS is used as a chip select activating the output buffer, as well as latching the address bits into the
column-address buffers. The TMS44C257 column addresses are latched only on write cycles with the
later of the CAS or W falling edge.
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects
the read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard
TTL circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When
Wgoes low prior to CAS (early writel. data out will remain in the high-impedance state for the entire cycle
permitting a write operation with G grounded. The TMS44C257 latches the column addresses on write
cycles with the later of CAS or W falling edge.
data in (DQ 1-DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling
edge of CAS or W strobes data into the on-chip data latch. In an early write cycle, W is brought low prior
to CAS and the data is strobed in by CAS with setup and hold times referenced to this Signal. In a delayed
write or read-modify-write cycle, CAS will already be low, thus the data will be strobed in by Wwith setup
and hold times referenced to this signal. In a delayed or read-modify-write cycle, G must be high to bring
the output buffers to high impedance prior to impressing data on the I/O lines.
4-120
"'11
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C256. TMS44C257
262.144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORIES
data out (OQ 1·0Q4)
U)
The three-state output buffer provides direct TTL compatibility (no pull-up resistor required) with a fanout
of two Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance
(floating) state until CAS and G are brought low. In a read cycle the output becomes valid after the access
time interval talC) that begins with the negative transition of CAS as long as ta(R) and talCA) ar~satisfied.
The output becomes valid after the access time has elapsed and remains valid while CAS and G are low.
CAS or G going high returns it to a high-impedance state. This is accomplished by bringing G high prior
to applying data, thus satisfying td(GHD).
:E
~
CJ
"eca
c::
>-
..
C
output enable {G)
G controls the impedance of the output buffers. When Gis high, the buffers will remain in the high-impedance
state. Bringing G low during a normal cycle will activate the output buffers putting them in the lowimpedance state. It is necessary for both RAS and CAS to be brought low for the output buffers to go
into the low-impedance state. Once in the low-impedance state, they will remain in the low-impedance
state until either G or CAS is brought high.
refresh
A refresh operation must be performed at least once every eight milliseconds to retain data. This can be
achieved by strobing each of the 512 rows (AO-A8). A normal read or write cycle will refresh all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
thus conserving power as the output buffer remains in the high-impedance state. Externally generated
addresses must be used for a RAS-only refresh. Hidden refresh may be performed while maintaining valid
data at the output pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS
after a specified precharge period, similar to a RAS-only refresh cycle.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS [see parameter td(CLRL)R] and
holding it low after RAS falls [see parameter td(RLCH)R]. For successive CAS-before-RAS refresh cycles,
CAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated
internally. The external address is also ignored during the hidden refresh option.
power up
To achieve proper device operation, an initial pause of 200 J1.s followed by a minimum of eight initialization
cycles is required after power up to the full VCC level.
test function pin
During normal device operation, the TF pin must be either disconnected or biased at a voltage less than
or equal to VCC.
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-121
TMS44C256. TMS44C257
262.144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORIES
logic symbol t
AO
A1
A2
A3
A4
A5
A6
A7
A8
-
(6)
(7)
(8)
RAM 256K x 4
2009/2100
(9)
o
(11)
(12)
(13)
(14)
(15)
A 262.143
20017/2108
C20[ROW)
G23/[REFRESH ROW)
RAS ..:..(4":"":')*----1 24[PWR OWN)
C21 [COL)
G24
CAS (_1_7..
) --'--"'I
&
23C22
OQ1~(1~).--f.~~---------~------~~
(2)
OQ2~(1K8~)::=t====================:=j
OQ3
(19)
___________________________
OQ4~~~
~
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
4-122
TEXAS
.-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS44C256, TMS44C257
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORIES
functional block diagram
U)
:2
~
CJ
Os
CO
..
C
>-
C
ROW
ADDRESS
BUFFERS
(9)
256K
256K
ARRAY
ARRAY
SENSE AMPLlFIERS
AO
A1
A2
A3
A4
A5
A6
COLUMN
ADDRESS
BUFFERS
COLUMN DECODE
(9)
A7
AS
256K
absolute maximum ratings over operating free·air temperature range (unless otherwise noted) t
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1 V to 7 V
Voltage range on Vee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V
Short circuit output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-123
TMS44C256. TMS44C257
262.144·WORD BY 4·BI1 DYNAMIC RANDOM·ACCESS MEMORIES
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
VCC
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
2.4
6.5
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
°c
0
V
V
NOTE 2: The algebraic convention. where the more negative (less positive) limit is designated as minimum. is used in this data sheet for
logic voltage levels only.
_
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
TEST
TMS44C25_-10
CONDITIONS
MIN
10H = -5 mA
10L= 4.2 mA
2.4
TMS44C25_ -12
MAX
MIN
MAX
2.4
TMS44C25_-15
MIN
MAX
UNIT
V
2.4
0.4
0.4
0.4
V
±10
±10
±10
p.A
±10
±10
±10
p.A
70
60
55
mA
3
3
3
mA
65
55
50
mA
45
35
30
mA
45
35
30
mA
VI = 0 V to 5.8 V.
II
Input current (leakage)
VCC = 5 V.
All other pins
= 0 V to VCC
Vo = 0 V to Vcc.
10
Output current (leakage)
VCC = 5.5 V.
CAS high
ICCl
ICC2
Read/write
tc(rdW) = minimum.
cycle current
VCC = 5.5 V
After 1 memory cycle.
Standby current
RAS and CAS high.
VIH = 2.4 V
tc(rdW) = minimum.
ICC3
Average refresh current
VCC = 5.5 V.
RAS cycling.
CAS high
tc(P) = minimum.
ICC4
Average page current
VCC = 5.5 V.
RAS low.
CAS cycling
tc(rdW) = minimum.
Average static column
ICC6
decode current
VCC = 5.5 V.
RAS low.
CAS cycling
4-124
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C256, TMS44C257
262,144·WORD BY 4·BI1 DYNAMIC RANDOM·ACCESS MEMORIES
capacitance over recommended supply voltage range and operating free-air temperature range,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance. address inputs
6
pF
Ci(RC)
Input capacitance. strobe inputs
7
pF
Ci(W)
Input capacitance. write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 3: VCC equal to 5.0 V ± 0.5 V and the bias on pins under test is 0.0 V.
switching characteristics over recommended supply voltage range and operating free-air temperature
range (see Figure 1)
ALT.
PARAMETER
SYMBOL
TMS44C25 -10
MIN
TMS44C25 -12
MAX
MIN
MAX
TMS44C25 -15
MIN
MAX
UNIT
ta(C)
Access time from CAS low
tCAC
25
30
40
ta(CA)
Access time from column address
tCAA
45
55
70
ns
ta(R)
Access time from RAS low
tRAC
100
120
150
ns
Access time from Glow
tGAC
25
30
40
ns
tCAP
50
60
75
ns
tWRA
30
35
40
ns
tALW
95
115
120
ns
ta(G)
Access time from column precharge
ta(CP)
(TMS44C256 only)
..
ns
Access time from W high.
ta(WHQ)
Static column decode mode
(see Note 4) (TMS44C257 only)
Access time from W low.
ta(WLQ)
Static column decode mode
(see Note 4) (TMS44C257 only)
Output disable time after CAS
tdis(CH)
high (see Note 5)
tOFF
0
25
0
30
0
35
ns
tGOFF
0
25
0
30
0
35
ns
Output disable time after G
tdis(G)
high (see Note 5)
NOTES: 4. Read-modify-write operation only.
5. tdis(CH) and tdis(G) are specified when the output is no longer driven.
TEXAS
"11
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-125
TMS44C256
262.144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and operating free-air temperature range
c
-<
::s
m
ALT.
3
5·
MIN
TMS44C256-12
MAX
MIN
MAX
TMS44C256-15
MIN
MAX
UNIT
tc(rd)
Read cycle time (see Note 7)
tRC
190
220
260
ns
tc(W)
Write cycle time
twc
190
220
260
ns
tRWC
220
255
305
ns
tpc
55
65
80
ns
tpCM
85
10'0
125
ns
15
25
Read-write/read-modify-write
tc(rdW)
..
TMS44C256-10
SYMBOL
cycle time
Page-mode read or write
tc(P)
t~(PM)
cycle time (see Note 8)
Page-mode read-modify-write
cycle time
CAS high
CAS low (see
tw(CH)
Pulse duration,
tw(CL)
Pulse duration,
tw(RH)
Pulse duration RAS high (precharge)
Note 9)
tcp
10
tCAS
25
tRP
80
tRAS
100
Non-page-mode pulse duration,
twIRL)
RAS low (see Note 10)
Page-mode pulse duration,
tw(RL)P
tw(WL)
RAS low (see Note 10)
Write pulse duration
tRASP
before CAS low
before RAS low
iN low
(see Note 11)
CAS low
CAS low (see Note 12)
CAS high
th(CA)
RAS high
after RAS low
120 100,000
150 100,000
ns
ns
ns
tASC
ns
tASR
0
0
0
ns
tDS
0
0
0
ns
tRCS
0
0
0
ns
twcs
0
0
0
ns
tCWL
25
30
40
ns
tRWL
25
30
40
ns
tCAH
20
20
25
ns
tRAH
15
15
20
ns
Row-address hold time
th(RA)
ns
0
Column-address hold time
after CAS low (see Note 11)
10,000
150
0
W-Iow setup time before
tsu(WRH)
10,000
0
W-Iow setup time before
tsu(WCH)
ns
100
25
W-Iow setup time before
tsu(WCL)
120
ns
10,000
20
Read setup time before
tsu(rd)
10,000
40
15
Data setup time before
tsu(D)
10,000
90
100 100,000
Row-address setup time
tsu(RA)
30
twp
Column-address setup time
tsu(CA)
10,000
Continued next page.
NOTES: 6. Timing measurements are referenced to VIL max and VIH min.
7. All cycle times assume tt = 5 ns.
8. tc(P) > tw(CH) min + tw(CL) min + 2tt.
9. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user's transition times, this may
require additional CAS low time '[tw(CL»)'
10, In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed, Depending on the user's transition times, this may
require additional RAS low time [tw(RL»)'
11. Later of CAS or iN in write operations.
12. Early write operation only.
4-126
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C256
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and operating free~air temperature range
(continued)
ALT.
SYMBOL
TMS44C256-10
MIN
Column-address hold time
th(RLCA)
after RAS low (see Note 13)
Data hold time after
th(D)
CAS low (see Note 11)
RAS low (see Note 13)
CAS high (see Note 15)
RAS high (see Note 15)
CAS low (see Note 12)
RAS low (see Note 13)
CAS high
20
25
30
ns
tDHR
70
85
110
ns
tRCH
0
0
0
ns
tRRH
10
10
10
ns
tWCH
20
25
30
ns
tWCR
70
85
100
ns
tCSH
100
120
150
ns
tCRP
0
0
0
ns
tRSH
25
30
40
ns
tCWD
50
60
70
ns
tRCD
25
75
25
90
30
110
ns
tRAD
20
55
20
65
25
80
ns
tRAL
45
55
70
ns
tCAL
45
55
70
ns
tRWD
100
120
150
ns
tAWD
45
55
70
ns
tGDD
25
30
40
ns
tGSR
20
25
35
ns
Delay time, CAS high to
td(CHRL)
RAS low
Delay time, CAS low to
td(CLRH)
RAS high
Delay time, CAS low to
td(CLWL)
Vii
low (see Note 4)
Delay time, RAS low to
td(RLCL)
CAS low (see Note 14)
Delay time, RAS low to
td(RLCA)
column address (see Note 14)
Delay time, column address
td(CARH)
to RAS high
Delay time, column address
td(CACH)
to
CAS
high
Delay time, RAS low to
td(RLWL)
Vii
low (see Note 4)
Delay time, column address
td(CAWL)
to
Vii low
(see Note 4)
Delay time, G high before
td(GHD)
data at DQ
Delay time, Glow
td(GLRH)
to RAS high
UNIT
tDH
Delay time, RAS low to
td(RLCH)
MAX
ns
Write hold time after
th(RLW)
MIN
100
Write hold time after
th(CLW)
TMS44C256-15
80
Read hold time after
th(RHrd)
MAX
70
Read hold time after
th(CHrd)
MIN
tAR
Data hold time after
th(RLD)
TMS44C256-12
MAX
..
Continued next page.
NOTES: 4. Read·modify-write operation only.
11. Later of CAS or Vii in write operations.
12. Early write operation only.
13. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
14. Maximum value specified only to guarantee access time.
15. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-127
TMS44C256
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and operating free-air temperature range
(concluded)
C
-<
:::J
ALT.
I»
3C:;O
SYMBOL
Delay time. RAS low to
~
..
s:
en
td(RLCH)R
<:;AS high (see Note 16)
td(CLRL)R
Delay time. CAS low to
RAS low (see Note 16)
td(RHCL)R
CAS low
TMS44C256·10
MIN
trf
Refresh time interval
tt
Transition time
MAX
TMS44C256·15
MIN
MAX
UNIT
25
25
30
ns
tCSR
10
10
15
ns
tRPC
0
0
0
ns
tREF
tT
3
8
50
NOTE 16: CAS·before·RAS refresh only.
4-128
MIN
tCHR
Delay time. RAS high to
(see Note 16)
TMS44C256·12
MAX
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
8
3
50
3
8
ms
50
ns
TMS44C257
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and operating free-air temperature range
ALT.
TMS44C257-10
SYMBOL
MIN
TMS44C257-12
MAX
MIN
MAX
TMS44C257-15
MIN
MAX
UNIT
tc(rd)
Read cycle time (see Note 7)
tRC
190
220
260
tc(W)
Write cycle time
twc
190
220
260
ns
tRWC
220
255
305
ns
tSCR
50
60
90
ns
tcsw
50
60
90
ns
tSCRDW
100
120
150
ns
Read-write/read-modify-write
tc(rdW)
cycle time
Static column decode mode
tc(rd)SC
read-only cycle time
Static column decode mode
tc(W)SC
write-only cycle time
ns
Static column decode mode
tc(rdW)SC
read-modify-write cycle time
tw(CH)
Pulse duration, CAS high
tcp
10
tw(CL)
Pulse duration, CAS low (see Note 9)
tCAS
20
tw(RH)
Pulse duration, RAS high (precharge)
tRP
80
tRAS
100
Non-static column decode mode
twIRL)
pulse duration, RAS low (see Note 10)
Static column decode mode
tw(RL)P
tw(WL)
pulse duration, RAS low (see Note 10)
Write pulse duration
column address pulse duration
W high
pulse duration
before CAS low or
W low
(see Note 11)
before RAS low
W low
(see Note 11)
CAS low
CAS low (see Note 12)
tADP
45
55
70
ns
tWI
10
15
25
ns
tASC
0
0
0
ns
tASR
0
0
0
ns
tDS
0
0
0
ns
tRCS
0
0
0
ns
twcs
0
0
0
ns
tCWL
25
30
40
ns
tWHCH
0
0
0
ns
W-Iow setup time before
tsu(WCH)
CAS high
W-high setup time before
tsu(WHCH) CAS high (see Note 12)
ns
ns
W-Iow setup time before
tsu(WCL)
10,000
ns
Read setup time before
tsu(rd)
150
150 100,000
Data setup time before
tsu(D)
10,000
ns
ns
. 25
Row address setup time
tsu(RA)
10,000
20
Column-address setup times
tsu(CA)
120
35
100
90
10,000
ns
25
10,000
15
Static column decode mode
tw(WH)
25
twp
tRASP
Static column decode mode
tw(CA)
15
10,000
100 100,000
120 100,000
Continued next page.
NOTES: 6. Timing measurements are referenced to VIL max and VIH min.
7. All cycle times assume tt = 5 ns.
9. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user's transition times, this may
require additional CAS low time [tw(CL)].
10. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user's transition times, this may
require additional RAS low time [twIRL)]'
11. Later of CAS or W in write operations.
12. Early write operation only.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-129
TMS44C257
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and operating free·air temperature range
(continued)
C
-<
:::J
ALT.
D)
SYMBOL
3
(i'
W-Iow setup time before
tsu(WRH)
:xJ
:t>
RAS high
..
tsu(RLrd)
(I)
before RAS low
before RAS high
after CAS low,
Vii
low (see Note 11)
after RAS low
after RAS low (see Note 17)
CAS low (see Note 11)
RAS low (see Note 17)
CAS high (see Note 15)
0
ns
tCAR
50
60
75
ns
tCAH
20
20
25
ns
tRAH
15
15
20
ns
tAR
100
120
150
ns
tDH
20
25
30
ns
tDHR
70
85
110
ns
tRCH
0
0
0
ns
tRRH
10
10
10
ns
tWCH
20
25
30
ns
tWCR
70
85
100
ns
tAH
10
15
15
ns
tOH
5
5
5
ns
tCSH
100
120
150
ns
tCRP
0
0
0
ns
tRSH
25
30
40
ns
tCWD
25
30
40
ns
Read hold time after
th(RHrd)
RAS high (see Note 15)
Write hold time after
th(CLW)
CAS low
Write hold time after
th(RLW)
RAS low (see Note 17)
Column-address hold time
th(RHCA)
after RAS high
Output hold time after
th(CAQ)
address change
Delay time, RAS low to
td(RLCH)
CAS high
Delay time, CAS high to
td(CHRL)
RAS low
Delay time, CAS low to
td(CLRH)
RAS high
Delay time, CAS low to
td(CLWL)
Vii low
(see Note 4)
Continued next page.
NOTES: 4. Read-modify-write operation only.
11. Later of CAS or Vii in write operations.
15. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
17. The minimum value is measured when td(RLCA) is set to td(RLCA) min as a reference.
4-130
UNIT
0
Read hold time after
th(CHrd)
MAX
0
Data hold time after
th(RLD)
MIN
tWRP
Data hold time after
th(D)
TMS44C257-15
ns
Column-address hold time
th(RLCA)
MAX
40
Row-address hold time
th(RA)
MIN
30
Column-address hold time
th(CA)
TMS44C257-12
MAX
25
Column-address setup time
tsu(CAR)
MIN
tRWL
Read-command setup time
s:
TMS44C257-10
-Ij}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C257
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORIES
timing requirements over recommended supply voltage range and operating free·air temperature range
(concluded)
ALT.
TMS44C257-10
MIN
MAX
MIN
MAX
tRCD
25
75
25
90
30
110
ns
column address (see Note 14)
tRAD
20
55
20
65
25
80
ns
to RAS high
tRAL
45
55
70
ns
tCAL
45
55
70
ns
tRWD
100
120
150
ns
tAWD
45
55
70
ns
tGDD
25
30
40
ns
tGSR
20
25
35
ns
tow
0
0
0
ns
tCHR
25
25
30
ns
tCSR
10
10
15
ns
tRPC
0
0
0
ns
tREF
tT
3
Delay time, column address
td(CACH)
to CAS high
Delay time, RAS low to
td(RLWL)
W low
(see Note 4)
Delay time, column address
td(CAWL)
to
W low
(see Note 4)
Delay time, G high before
td(GHD)
data at DO
Delay time, Glow
td(GLRH)
~
(,)
CAS low (see Note 14)
Delay time, column address
td(CARH)
en
~
UNIT
MAX
Delay time, RAS low to
td(RLCA)
TMS44C257-15
MIN
SYMBOL
Delay time, RAS low to
td(RLCL)
TMS44C257-12
to RAS high
"sas
c
>
..
C
Delay time, W high to output
td(WO)
transition from high impedance
to active
Delay time, RAS low to
td(RLCH)R
CAS high (see Note 16)
Delay time, CAS low to
td(CLRL)R
RAS low (see Note 16)
Delay time RAS high to
td(RHCL)R
trf
tt
NOTES:
CAS low (see Note 16)
Refresh time interval
Transition time
8
50
8
3
50
3
8
50
ms
ns
4. Read-modify-write operation only.
14. Maximum value specified only to guarantee access time.
16. CAS-before-RAS refresh only.
PARAMETER MEASUREMENT INFORMATION
1.31 V
VCC = 5 V
OUTPUT - { R L = 218
UNDER
TEST
TCL
R1 = 828
OUTPUT
UNDER - - f ! I I - - - _
TEST
R2 = 295
CL = 100 pF
n
= , •• pF
(a) LOAD CIRCUIT
n
n
(b) ALTERNATE LOAD CIRCUIT
FIGURE 1. LOAD CIRCUITS FOR TIMING PARAMETERS
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-131
TMS44C256
262.144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
read cycle timing
I-
tc(rdl
' "
I
tt--l
,
'wl.lI
I-~I
_
td(RLCLI
, ., I
-
td(RLCA) , I
•
· ,t~u(CA)
t-:- tsu(RA)
~I
td(CARH)
I
I-
.
I
I, td(CACH)
~~~h(RLCA)
~+-I-+,---------~
11
'1'1
, too·.....,...,+---tw(CHI
"
• "
j\~--
VIH
VIL
• ,
"
,
"
I,
i' ,
,
~ cowM~M&ZHN~{iAtI0@(",--________ ::~
~
,
,
,
~
,
:
I
,
,.--r, th(CA)
.
"
t--t-th(RHrd)
, • ,
• , th(CHrdl
tsu(rdl--'
DO'D04
NOTE '8: Output may go from high impedance to an invalid data state prior to the specified access time.
4-132
VIL
Hi- td(CHRLI---i
l{
, , ~ I•
AD-AS
- ,
N,"
~
1tr
---.:,j ,
, '--------, ,I-...- tw(RH1------J,
r--- tw(CL) ---I
", ,-
---;
r--- td(CLRHI
~
td(RLCHI
11
th(RA)-:.J
• ,
TEXAS
..Jj}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C257
262,144·WORD BY 4·BI1 DYNAMIC RANDOM·ACCESS MEMORY
read cycle timing
o
,, I.
I..
RAS
N
,
,
~~
~
,
tc(rd)
}
!,
VIH
'7
,...
•
tw(CH)
.; "---VIL
Itd(CACHI------t ,~ "th(RHCA)
td(CARHI.
, ,
~__t~h(~R~LC~A~)~-__________~~__~
_---------------VIH
COLUMN
----------------VIL
I
I
'-- th(RHrd)
tsu(rd)
I
14--•• th(CHrd)
.I
CO
C
C
•
,
~-+---------
.0
t---tw(CL)---,
I.
~
CAS
td(RLCi)
t
..-.I
tsu(CA) ,.
su(RA) - I
I.
th(RA),.....
AD-A8
.,
I
CJ
"s
~:
--!
NOTE 18: Output may go from high impedance to an invalid data state prior to the specified access time.
TEXAS
-I/}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-133
TMS44C256
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
c
-<
:s
m
3
(;'
early write cycle timing
I-
tc(W)------------·~1
"AS ~.
--1 t-I
1I·
----II---
r-tt
..
I
CAS
I---
td(RLCL)
I
td(CLRH)
~
1
tw(CL)~
II
I•
0I
,
I
I
___
:11:
1
1-00
1 - - - - td(CHRL)---·~1
II
I)J
1\
VIH
} 1....~----tW(CH)-----.~ " - - - - VIL
titd!RLCH)
4tSU(RA)
I
I
I
'0-.---tW(RH)---'~'-
'wl""
td(CACH)
,td(CARH)
d
I
I • I
I
I
I I
t----t tsu(CA)
I
AO-AS
' - - - - - - - - - - - - VIL
w
TEXAS
-II}
INSTRUMENTS
POST OFFICE ~OX 1443 •
HOUSTON, TEXAS 77001
TMS44C257
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
early write cycle timing
en
~
l~
!1
RAS - } ,
i
I,
CAS
tw(RL)
----,I----
r-tt
,i
~
U
"E
tc(W)------------~
,-
I-
,
. ,I
td(CHRLI
!r.~. --
td(CACH)
,.
td(CARH)
t----t tsu(CA)
,
tw(RH)
E~
VIH
VIL
,I
.::;
,
,
,
!,
-I
VIH
tw(CHI
,LV'L
I
,
..
I,
VIH
AO-AB
-----+,
,
VIL
I
td(RLCAI
,I
I
I ..
I'
I
II
tsu(WCHI---+-I
tsu(WRHI--"';""-':""""'co!
"O"\."""7'O"t:~~~~!'-th(RL~ th(CLWI
tsu(WCLI
'
I
I-
t---
th(RLDI
tsu(D)
--1
~~~7'O"'i~""'V"O"Q"C7'O"'i~~'V"O~r\7'Ii7'\J1W\7
VIH
IAAAAJ"oJ'.J'V'.rv"'Ar
VIL
•I
......-;---if- tw(WLI
~ th(D) --I
• ,
I
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
ca
C
>
Q
I
, ,r'",,'_ _ _ _ _ _ _ _ _ _---,.
l'iU,
,-
(1.----
td(CLRH)----r
td(RLCH)
,
- I
1if
!---tw(CL)~'1-1" ' , - - -
td(RLCL)
~.'"'RAI
E
4-135
TMS44C256, TMS44C257
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORIES
write cycle timing
i.
I
tc(W)
I.
r---I{'-( I
I
I ,.
twiRL)
1;
tt
r----
-
(.
"
tsu(CA)
AO-AS
H-"tsuIRA)
,• I
2M R~W
•
tt
""
-, I
,.
,
f.:
I
td(CACH)
II!
I
th,(RLCA)
,
I
I
.1
.. :
'
I
I
t--
th(CAI-i
NOTE
I
,•
I
tsulWRH)
•
I
• -
r"I:'T"t7"'O"U"'t7"'!7"'rrrT"t7"'O"U"'trrrtTO~r'O""~~ VIH
I
4-136
VIL
------"
11 [---:--- tsu(WCH)
"tT'I'7"'!7"'rrrT-m,~rrrrrrT~r"O""Irrr~
W in
VIH
COLUM~ ~H{{~AH_,--__ ~:~
...._ _ _."""1
NOTE 11: Later of CAS or
1\
I ,..t·~---tw(CH)-----1·-I,
td(CARH)
I
!•
L:::
I I
I
I t----- tw (R H)-----,
~: f".-~!I-----------v
tw(CL)
1-
I"
• (
(
I---+- t d(CHRL)----1
I
td(RLCH)
thIRA)~
,I
~
--I
~
td(CLRH)
--------'
td(RLCL).
II
II
• (
write operation_
.Jj}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C256
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
read-write/read-modify-write cycle timing
,.
, ,-
RAS
tc(rdWI
~~
- - ' j--tt
,, r--td(RLCLI---i
, 1
, r- td!RLCAI-'
,
I
th(RAlr
Lftsu(RAI
---l
!
AO-AS
I'
It
i
I
, t----rtd(CHRLI-----i
M' ,"
!,
~_ _ _ _ _ _ _ _ ____"_.
,
"
I
!"---ttsu(CAI
!
I
,
i
,
th(RLCA)-t-------I
,
1
I
,
±
.' I
I
th(CA) ;-------!
,
7L
"
r
,
Vil
VIH
Vil
,
-T-I--tw(CHI-----.-aof'
1 - 0 '_ .
,
,
9,,
I-- tsulWCHI ---t
t---
VIH
'------
VIH
Vil
-
i--ttd(CAWLI-----'
tsulWRHI---i
td (CLWLI--1 t--twIWLI----I
-,
tsu(rdl!.'
'
N
~HHH~ v"
( I
0Er1HW' i i
, •
, td(RLWLI
-, ,.
'I
VIH
th(O)
t - - - tsu(OI-----!
VIHIVOH
001004
,
,
,-
G
,
"\
1'--t---tw(RHI~
_I
tw(Cll
N'
,
I,I
i
~ C~L'UMN ~~~~!t~R:~r----,
,
Vi
- I
1\
,
-
tw(RLI
VILiVOL
---t
i--ta(CI
r--taICAI--l
1
ta(RI-----\
~talGI -----1
VIH
!
Vil
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 7700 1
4-137
TMS44C256
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
enhanced page·mode read cycle timing
N:-------------------------1'
tW(RL)P------------.~
,
t w (RH)-r--1
,
'I
,
1
1<0
!""',---,-
, ,
, I
-
•
td
• I
(RLCL)
"
td(RLCH)'· "
tw(CL) -r----t
II
I I
II
!-- - - th(RLCA)
tsu(RA)
. - -
'~IrI
--l,
,
i\\{ lIf
'
I'
I 1·1 I
j II t sulCAlI
th(RA)
,
'
--I
I
I
f--
VIL
,
t-- td(C~RL)--'
....----tc(P)---.........
I"
''--
---+I-+'------~r----..,
I
VIH
, I
-l
,
,
, ,
\\{ IT
,I
t--
, ,
I-- td(CLRH)----'
tw(CH)
I
I
td(CACH)-t
' I
,
t---th(CA)
I
,
II
I ,
II
, I ,
•I ,
,
'
td(CARH) I
I'V'\,~~~~~
AO-A8
COLUMN
DQ1DQ4
NOTES: 18. Output may go from high impedance to an invalid data state prior to the specified access time.
19. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
20. Access time is ta(CP) or ta(CA) dependent.
4-138
-Ij}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
1MS44C256
262,144·WORD BY 4·B11 DYNAMIC RANDOM·ACCESS MEMORY
enhanced page-mode write cycle timing
I.
--; tw(RH)i--I I
I
tw(Rl)P
~!
!~
t,I
i\
I
I
I
I
I I.
I I
td(RlCH)
•
tdIRlCl)
f-- tw(CH)~
'-=
AO-AS
I I
tsu(CA)----(
1
I
I
11
I I
th(RlCA)
I t-- th(RA)
th(CAI I-
't I,.,RA'
:x . ROW
I
I
I
I
I~
I
I - - tw(Wl) -I
L--- td(RlCA)---1
I
I
I
tsu(WCH)
•
\ \l
I
1
~
I
~ td(CARHI :
:l@¢
I
I
---1
I I
Vil
I1 I
•
I
I
~
'--
I
0
1
--- tsu(WRH)---'
~MT"C""'O"'~~~MT":rT
"!7'"t~~:;~~;;:;;;:;:;:;;:i1 th(RlWI """'rI
oil I
I oFVV'"'V'I,/'
~~~~~~~~~~~~----~~~~~~~~~~~~--~~~~~~~~~
:
VIH
COLUMN I WZi~N:{{~m :::
tsu(WCH)--!
0
I
i
I-- td(CACH) ---.I
1
-1
I
!
VIH
Vil
td(CHRl)----t
I
Air"----;..1+1---i
II
M: COL~MN
I
I
I
I
--j I
r--
:-- td(ClRH)---j
k
t\ \l
II
---!
I
tw(Cl) H O t (P)
• I
I
c
IL
I
VIL
.. I th(D)
_+I---th(D) -------....1 NOTE 22
I!
NOTE 22
1
1 - - - - - - - - t h ( R l D ) - - - - - - - - - - - - - 4..~1
I
I
I
I-----tsu(DI-----i
I
I
NOTE 2 2 :
I·
tsu(D)
i
I
NOTE 22
I
I
I
I
DQ1DQ4
J
NOTES: 21. A read cycle or a read-modify-write cycle can be intermixed with the write cycles as long as the read and read-modify-write
timing specifications are not violated.
22. Referenced to CAS or Vii, whichever occurs last.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-139
TMS44C256
262.144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
enhanced page-mode read-modify-write cycle timing
tw(RH)
RAS
----I
t--
~"~-------------tW(RL)P-------------I'n
, ~'---------------------------,
,
I - - - tc(PM) - - - I
I - - - td(CLRH)
.. ,
I
td(RLCH)
.. ,
I
,
,
,
,
I
,
I---+t
td(CHRL) ,. I
•,
td(RLCL)~
, ,
I W(C7)
I I
, I
t--tW(CL)-, I
I
,
:,..1--;...'_ __
,, I-I
..
, r--
!
i\'{
!i
, I.
th(RLCA)
r- I I
ht~I:1
th(RA)
tSU(RA)---j
AO-A8
-l-{
~I
-I
~
,
I
I
-;
I
td(CAWL)
"',
~ ! !
_'
I
I
I
001004
,
,
I
,
I,
,
td(CLWL)
td(RLWL)
)Q0§§2R~~'I~~{E}X)«
COLUMN
.. ,
I .I
,--h. ,
I
tsu(WCH)
,
NOTE 18
,--1
I--
ta(R)
ta(G) - ,
,
VIH
VIL
,
I-- I
.. ,
tsu(WRH)
,
\l1t.._,J.~~~~CJJ.
NJ
1
tSUIO)~ J-I-t----t-
"
'I
~
",_
,:,
i
i,
I '
I I
,I
I
, w(WL) I-,
I "
Ir---- '
:I
------x
I
kiv
~
COLUMN
f4-t-'I~
\~
1:
• I th(C~)
!•
tsu(CA)
tsu(rd)-+----t-i ,
1
VIL
.
H--taICP)'~ NOTE 18
~~rrtrrrtr~~~"'a'
i
talC)
~
talCA)
tdis(G)
I
-----<-+-
Ioo!
td(GHO)
~
Vr--------,
NOTES: 18. Output may go from high impedance to an invalid data state prior to the specified access time.
23. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write cycle timing specifications
are not violated.
4-140
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
1MS44C257
262,144·WORD BY 4·B11 DYNAMIC RANDOM·ACCESS MEMORY
static column decode mode read timing with CAS cycling
J:
....
J:
....
J:
....
'>
'>
'>
'>
'>
'>
J:
en
~
....
'>
'>
J:
a
>
....
a
>
J:
'>
~
u
"eca
....
'>
c
..
>
C
a.i
E
.;:;
'"'"
C!l
U
U
co
1l
:;:
.~
g.
C!l
.s
B
o
'§.
~co
co
""C
~
co>
.s:
a5
B
C!l
u
a5
""C
C!l
Co
.s
.r:
Cl
:E
E
.g
o
Cl
I~
(I)
15
1:=
co
E
w
I-
a
z
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-141
TMS44C256, TMS44C257
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORIES
static column decode mode read cycle timing
C
'<
:::J
D)
3
C:;'
..
w~~~:w
4"ICI
t----ta(R)
• :
I
VOH
001-
004--------------~~~-<
.:::ro..--';;;";"",J
I
I
tdiS(G)~
t- ta(G)--I
G--------------~~~
______________________________________________J~VIH
-
VIL
NOTE 18: Output may go from high impedance to an invalid data state prior to the specified access time.
4-142
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS44C257
262,144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
static column decode mode early write cycle timing
I·
11
1
I 1
tw(RH)
t w ( R L ) P - - - - - - - - - - - - - t a o.1
I
Vi
--------!-------------------~-
1
...-----.-(,1 I
I1
, 1 1
-I
II
I
}
VIH
i \....VIL
I
..
~td(CHRL)-,
r-tsu(CJ}RI-H
I -t-I
I
AO-AS
COLUMN
COLUMN
~ td(~LCA).1
I
-1t-t-~(R~rd)
I
b
I
I
IN W I \1
I
II
I
I
I
-!t-tsu(D)
t--th(RLD~
I
>
~~~----+-I--4q V~~ID
I
t
th(D)
D
I
su
(CA) --' I-.I
'I i---th(CA)------t
,
I
r--tw(WH).....,
~_ _~I
\l
/
I I ' I,
I
\1_'___I
tw(WL)
--.---~ I
r--
r-- th(D)-----,
I
(
V~~ID
I
V~~ID
VIH
HI-ZVIL
t----t-td(GHD)
GJ
rl-------------------------------------------------------VIH
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-143
TMS44C257
262.144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
static column decode mode write cycle timing
C
'<
:::s
Q)
3
C:;'
:a:J
l>
..
s:
en
I~
4·144
15
>"
:r
..J
>"
>"
:r
:r
..J
>"
..J
>"
>"
>"
X ->
""::J
0
0
>
>
a:
..J
(J
:r
"sCO
..J
>"
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..
C
>
C
t----~ T
J
I~
I~
1:=
to
c:(
6
':'<:1"
00
It!)
cc
c:(
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-145
I
f'
.....
slIII"H :l!weuAa
~
N
O'l
!!!.
II)
...
n
~n
0'
0
C-
3
jltt
I :
AAS
I
1
r------'"td(RLCL)---
AD.AS
\.1
I
I..
~thIRA):
:AOW
1
IN
I
t su lrd)---1
~I
1
I
1
1
D01D04
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I
I
~14I
•
I•
• I
th(D)
tsu(D) --,
1
thIRLD)
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1
To
f--ta(WHO)--I
1
I•
I4
, 1
1
~taIG)~
\l
I
•
I
VIL
CD
I
"\
:
'{
-t-----I
I-- I
·1
VALID ,
I•
I
•I
VIH
VIL
VIH
VIL
I
:
--l
td(GHD)
1
1
11
!
I
\
NOTE 18: Output may go from high impedance to an invalid data state prior to the specified access time.
I
VOHiVlH
VOLiVlL
LtdiS(G)
I
VIH
VIL
~
CIa
-<
II)
o.
0.
:::;;
-<
C
i2
:t:-
s::
c::;
=
:t:-
~.
i2
C
0
n
:i:n
C"')
...
1
td(WO)
CCI
-<
CD
C;
CD
VIH
:e~
O .......
=
C
=i
-<
n
CD
n..
tIX
-~
~~
3
:3
0
VIL
-.i:.lI:--r----
0
0.
0
0.
1
1
1
ta(R)
CD
n
1
I:I !
'Pf1tWIWL)
1
I
'-Ita(C)
I
I--
-I
tw(WH)
1
1
G
I
• 1
0.
VIH
1
r-tsuIWRH)--{
.1 I
th(CA)---I
i
!
~
I
td(CAWL)
1
COLUMN
l i t - - - -ta(WLO) -------J
tal~A) I 4
1
1
~
:
1
tw(CA)
td(RLWL)
I.:
t-I
1
1
II
I
I
~
~
1.1
COLUMN
I
/
II
~
:
~~
tc(rdW)SC
y--
~
I
I
I
tsu(RA)!\.
r-tdIRLCA)--l
1
14
1
1
~~
~~
~
I
I
I
I
I
1
i!-f
1
1
zen
I
•
'I
'hIRLeAI
1
I
CAS
tw(RLlP
~'
.....
ens::
.!"en
3'
5'
CO
s::
m
en
en
s::
m
s::
0
=
-<
TMS44C256, TMS44C257
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORIES
RAS-only refresh timing
tn
~
«a:
as
CJ
VIH
ca
VIL
C
>-
C
VIH
VIL
VIH
VIL
-Ij}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
-
4-147
TMS44C256
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORIES
hidden refresh cycle (enhanced page mode)
4-148
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS44C257
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORIES
hidden refresh cycle (static column decode mode)
tn
~
«
a:
CJ
"ECO
c
C
..
>
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-149
TMS44C256, TMS44C257
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORIES
automatic (CAS-before-RAS) refresh cycle timing
c
-<~
m
.,,
Io.-I.o----------tc(rd)----------t
3
I
,
rtW(RH)~ r l - l - - - - - - - t W ( R L ) - - - - - -
c;"
..
RAS
i~---------------J}
-J:
,
Y
'i
I,
~-------------~
AO-AS
~~3~
OQ1- _ _ _ _ _ _ _ _ _ _ _ _ _
OQ4
4-150
VIL
.,,
,I. .
I
---t I-- tt
~ td(RHCL)R
_o-----td(RLCH)R------t
I
• I td(CLRL)R
CAS
VIH
VIH
VIL
::~
_ _ _ _ _ _ _ _ _ _ _ _ _ __ VIH
H1 Z
-II}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS4C1024, TMS4C1025, TMS4C1027
1,048,576-81T DYNAMIC RANDOM-ACCESS MEMORIES
MAY 1986-REVISED MAY 1988
•
1,048,576 x 1 Organization
•
Single 5-V Supply (10% Tolerance)
•
Performance Ranges:
TMS4C102_-10
•
N PACKAGE
D
ACCESS ACCESS ACCESS
READ
TIME
TIME
TIME
OR
TF
ta(R)
(tRAC)
(MAX)
talC)
(tCAC)
(MAX)
ta(CA)
(tCAA)
(MAX)
WRITE
CYCLE
(MIN)
100 ns
25 ns
45 ns
:?!
Q
RAS
()
CAS
AO
A9
AS
"eca
A1
A7
A2
A6
->
1S0 ns
A3
A5
VCC
A4
TMS4C 102_-12
120 ns
30 ns
55 ns
220 ns
TMS4C 1OL-1 5
150 ns
40 ns
70 ns
260 ns
•
TMS4C1027-Static Column Decode Mode
Operation
- Random Single-Bit Access Within a Row with
Only a Column Address Change
D
CAS-Before-RAS Refresh
Long Refresh Period ... 512-Cycle Refresh in
8 ms (Max)
VSS
W
Q
CAS
RAS
TMS44C256 - 256K x 4 Enhanced Page Mode
TMS44C257-256K x 4 Static Column Decode
•
TF
NC
NC
A9
AO
A8
Al
A7
A2
A6
A3
A5
V CC -"' _ _..r-" A4
tThe packages shown here are for pinout reference only.
The OJ package is actually 75% of the length of the N
package.
PIN NOMENCLATURE
AO-AS
Address Inputs
•
3-State Unlatched Output
CAS
Column-Address Strobe
•
Low Power Dissipation
0
Data In
o
NC
No Connection
Texas Instruments EPIC'" CMOS Process
Q
Data Out
•
All Inputs/Outputs and Clocks Are TTL
Compatible
RAS
Row-Address Strobe
TF
Test Function
W
Write Enable
High-Reliability Plastic 18-Pin 300-Mil-Wide
DIP or 20/26-Load Surfaco Mount (SOJ)
Packages
•
Operating Free-Air Temperature OOC to 70 0 C
•
Operations of TI's Megabit CMOS DRAMs
Can Be Controlled by TI's SN74ALS6301
and SN74ALS6302 Dynamic RAM
Controllers
C
(TOP VIEW)
One of TI's CMOS Megabit DRAM Family Including:
•
C
OJ PACKAGEt
TMS4C1024-Enhanced Page Mode Operation
for Faster Memory Access
- Higher Data Bandwidth than Conventional
Page-Mode Parts
- Random Single-Bit Access Within a Row
with a Column Address
TMS4C1025-4-Bit Nibble Mode Operation
- Four Sequential Single Bit Access Within
a Row By Toggling CAS
•
~
VSS
W
•
•
U)
(TOP VIEW)
VCC
5-V Supply
VSS
Ground
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~:~:~~i~Bi~~I~~i ~~:~~~ti:r :llo::~:~:t:~~s not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
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Copyright © 1986, Texas Instruments Incorporated
4-151
TMS4C1024, TMS4C1025; TMS4C1027
1,04B,576·BIT DYNAMIC RANDOM·ACCESS MEMORIES
description
The TMS4C1 024, TMS4C1 025, and TMS4C1 027 are high-speed, 1 ,048,576-bit dynamic random-access
memories, organized as 1,048,576 words of one bit each. They employ state-of-the-art EPIClM (Enhanced
Process Implanted CMOS) technology for high performance, reliability, and low power at a low cost.
These devices feature maximum RAS access times of 100 ns, 120 ns and 150 ns. Maximum power
dissipation is as low as 330 mW operating and 16.5 mW standby on 120 ns devices.
The EPIClM technology permits operation from a single 5-V supply, reducing system power supply and
decoupling requirements, and easing board layout. ICC peaks are 140 mA typical, and a - 1-V input voltage
undershoot can be tolerated, minimizing system noise considerations.
-
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines
are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS4C 102_ are offered in 18-pin plastic dual-in-line (N-suffix) and 20/26-lead plastic surface mount
SOJ (OJ suffix) packages. These packages are guaranteed for operation from OoC to 70°C.
operation
enhanced page mode (TMS4C1024)
Enhanced page-mode operation allows faster memory access by keeping the same row address while
selecting random column addresses. The time for row-address setup and hold and address multiplex is
thus eliminated. The maximum number of columns that may be accessed is determined by the maximum
RAS low time and the CAS page cycle time used. With minimum CAS page cycle time, all 1024 columns
specified by column addresses AO through A9 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling
edge of CAS latches the column addresses. This feature allows the TMS4C1 024 to operate at a higher
data bandwidth than conventional page-mode parts, since data retrieval begins as soon as column address
is valid rather than when CAS transitions low. This performance improvement is referred to as "enhanced
page mode." Valid column address may be presented immediately after row address hold time has been
satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after talC) max
(access time from CAS low), if ta(CA) max (access time from column address) has been satisfied. In the
event that column addresses for the next page cycle are valid at the time CAS goes high, access time
for the next cycle is determined by the later occurrence of talC) or ta(CP) (access time from rising edge
of CAS).
nibble mode (TMS4C1025)
Nibble-mode operation allows high-speed read, write, or read-write-modify-write access of 1 to 4 bits of
data. The first bit is accessed in the normal manner with read data coming out at talC) time as long as
ta(R) and ta(CA) are satisfied. The next sequential bits can be read or written by cycling CAS while RAS
remains low. The first bit is determined by the row and column addresses, which need to be supplied only
for the first access. Row A9 and column A9 provide the two binary bits for initial selection, with row A9
being the least-significant address and column A9 being the most significant. Thereafter, the falling edge
of CAS will access the next bit of the circular 4-bit nibble in the following sequence.
r+
(00)-.(01)-'(10)-'(11)--:J
Data written in a sequence of more than 4 consecutive cycles shall be capable of being read back without
exiting from the nibble mode. In a sequence of consecutive nibble-mode cycles the control of the highimpedance state for the data out (a) pin is determined by each individual cycle. This facilitates fully mixed
nibble-mode cycles (e.g., read/write/read-modify-write/read etc.).
4-152
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4C1024, TMS4C1025, TMS4C1027
1,048,576·81T DYNAMIC RANDOM·ACCESS MEMORIES
static column decode mode (TMS4C1027)
U)
The static column decode mode of operation allows high-speed read, write, or read-modify-write by reducing
the number of required signal setup, hold, and transition timings. This is achieved by first addressing the
row and column in the normal manner, but after the first access, maintaining CAS low. Subsequently
changing the column address produces valid data at ta(CA). The first bit is accessed in the normal manner
with read coming out at ta(R) time. Similarly, write or read-modify-write cycle times can be achieved with
appropriate toggling of W. The addresses are latched during the write operation, but at the completion
of the internal write operation the addresses are unlatched.
~
~
u
c
>
..
C
address (AO through A9) (TMS4C1024, TMS4C1025)
Twenty address bits are required to decode 1 of 1,048,576 storage cell locations. Ten row-address bits
are set up on inputs AO through A9 and latched onto the chip by the row-address strobe (RAS). The
ten column-address bits are set up on pins AO through A9 and latched onto the chip by the column-address
strobe (CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar
to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a
chip select activating the output buffer, as well as latching the address bits into the column-address buffer.
address (AO through A9) (TMS4C1027)
Twenty address bits are required to decode 1 of 1,048,576 storage cell locations. Ten row-address bits
are set up on inputs AO through A9 and latched onto the chip by the row-address strobe (RAS).
The ten column-address bits are set up on pins AO through A9. Row addresses must be stable on or before
the falling edges of RAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well
as the row decoder. In a write cycle, the later of CAS or Vii latches the column address bits.
write enable (Vii)
The read or write mode is selected through the write-enable (Vii) input. A logic high on the Vii input selects
the read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard
TTL circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When
Vii goes low prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle,
permitting common I/O operation.
data in (0)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling
edge of CAS or Vii strobes data into the on-chip data latch. In an early write cycle, W is brought low prior
to CAS and the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayedwrite or read-modify-write cycle, CAS will already be low, thus the data will be strobed in by W with setup
and hold times referenced to this signal.
data out (Q)
The three-state output buffer provides direct TTL compatibility (no pull-up resistor required) with a fanout
of two Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance
(floating) state until CAS is brought low. In a read cycle the output becomes valid after the access time
interval talC) that begins with the negative transition of CAS as long as ta(R) and ta(CA) are satisfied.
The output becomes valid after the access time has elapsed and remains valid while CAS is low; CAS
going high returns it to a high-impedance state. In a delayed-write or read-modify-write cycle, the output
will follow the sequence for the read cycle.
refresh
A refresh operation must be performed at least once every eight milliseconds to retain data. This can be
achieved by strobing each of the 512 rows (AO-A8). A normal read or write cycle will refresh all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
'Eca
HOUSTON, TEXAS 77001
4-153
TMS4C1024, TMS4C1025, TMS4C1027
1,048,576·811 DYNAMIC RANDOM·ACCESS MEMORIES
thus conserving power as the output buffer remains in the high-impedance state. Externally generated
addresses must be used for a RAS-only refresh. Hidden refresh may be performed while maintaining valid
data at the output pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS
after a specified precharge period, similar to a RAS-only refresh cycle.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS [see parameter td(CLRL)R1 and
holding it low after RAS falls [see parameter td(RLCH)R1. For successive CAS-before-RAS refresh cycles,
CAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated
internally. The external address is also ignored during the hidden refresh cycles .
..
power up
To achieve proper device operation, an initial pause of 200 p,s followed by a minimum of eight initialization
cycles is required after full VCC level is achieved.
test-function pin
During normal device operation the TF pin must either be disconnected or biased at a voltage less than
or equal to VCC.
logic symbol t
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
(5)
(6)
RAM 1024K x 1
20010/2100
(7)
(8)
(10)
(11)
(12)
(13)
(14)
(15)
O
A - -- 1.048.575
20019/2109
C20[ROW]
G23/[REFRESH ROW]
24[PWR OWN]
C21[COL]
G24
23C22
A'V
~------------------~
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and (Ee Publication 617-12.
The pin numbers shown are for the 18-pin dual-in-line package.
4-154
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
(17)0
TMS4C1024, TMS4C1025, TMS4C1027
1,048,576·8IT DYNAMIC RANDOM·ACCESS MEMORIES
functional block diagram
U)
G-
t
:?E
-
..
C
~
ROW
ADDRESS
BUFFERS
(10)
d
~
256K ./ ROW / 256K
ARRAY DECODE ARRAY
~
AO
[
~
A2
A4
r---
~
A1
A3
"
SENSE AMPLIFIERS
COLUMN
ADDRESS
BUFFERS
(10)
~
r----r---
A5
~
A6
SENSE AMPLIFIERS
AS
,I
256K
ROW 1256K
ARRA Y DECODE ARRAY
A9
I'
-'!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
I
r-- D
r-
r.-
r---
A7
-
1/0
BUFFERS
1 OF S
~ SELECTION
~
COLUMN DECODE
DATA
IN
REG.
DATA
OUT
REG.
f------ Q
""----
4-155
TMS4C1024, TMS4C1025, TMS4C1027
1,048,576-8IT DYNAMIC RANDOM-ACCESS MEMORIES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
c
Voltage range on any pin ............................................... - 1 V to 7 V
Voltage range on Vee ................................................. -1 V to 7 V
Short circuit output current .................................................. 50 mA
Power dissipation ............................................................ 1 W
Operating free-air temperature range ....................................... ooe to 70°C
Storage temperature range .......................................... - 65 °e to 150 0 e
-<
::::s
D)
3
(i"
:XJ
l>
s:
en
_
A
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maxim urn-rated conditions for extended periods may affect
device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
V
-1
6.5
0.8
V
V
0
70
°c
VCC Supply voltage
VIH High-level input voltage
Vil
TA
2.4
low-level input voltage (see Note 2)
Operating free-air temperature
NOTE 2:
UNIT
The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet
for logic voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
TMS4C1024-10 TMS4C1024-12 TMS4C1024-15
TMS4C1025-10 TMS4C1025-12 TMS4C1025-15
TEST CONDITIONS
PARAMETER
TMS4C1027-10 TMS4C1027-12 TMS4C1027-15
MIN
VOH High-level output voltage
low-level output voltage
VOL
II
10
Input current (leakage)
Output current (leakage)
10H
=
2.4
-5 mA
10l = 4.2 mA
VI = 0 V to 6.5 V, VCC
All other pins
=0
= 5.5
V,
V to VCC
Vo = 0 V to VCC, VCC
CAS high
= 5.5
V,
ICCl Read or write cycle current Minimum cycle, VCC = 5.5 V
After 1 memory cycle,
ICC2 Standby current
RAS and CAS high, VIH = 2.4 V
ICC3 Average refresh current
Average page current
ICC4
(TMS4C1024)
Average nibble current
ICC5
(TMS4C1025)
Average static column
ICC6 decode current
(TMS4C1027)
4-156
MAX
MIN
MAX
2.4
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
±10
±10
±10
p.A
±10
±10
±10
p.A
70
60
55
rnA
3
3
3
rnA
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high
65
55
50
rnA
tc(P) = minimum, VCC
RAS low, CAS cycling
45
35
30
rnA
tc(N) = minimum, VCC = 5.5 V,
RAS low, CAS cycling for 4 cycles
45
40
30
rnA
tc(rdW)SC = minimum,
VCC = 5.5 V,
RAS low, CAS cyclina
45
35
30
rnA
=
5.5 V,
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4C1024, TMS4C1025, TMS4C1027
1,048,576-8IT DYNAMIC RANDOM-ACCESS MEMORIES
capacitance over recommended supply voltage range and operating free-air temperature range, f = 1 MHz
(see Note 3)
PARAMETER
MIN
MAX
UNIT
Cj(A)
Input capacitance, address inputs
6
pF
Cj(D)
Input capacitance, data input
5
pF
Cj(RC) Input capacitance, strobe inputs
Ci(W) Input capacitance, write-enable input
7
pF
7
pF
7
pF
Co
NOTE 3:
Output capacitance
VCC equal to 5.0 V ± 0.5 V and the bias on pins under test is 0.0
v.
switching characteristics over recommended supply voltage range and operating free-air temperature
range (see Figure 1)
ALT.
PARAMETER
TMS4C1 02_-1 0
SYMBOL
MIN
MAX
Access time from CAS low t
tCAC
ta(CA)
Access time from column-address t
tCAA
45
ta(R)
Access time from RAS low t
tRAC
100
tCAP
50
ta(C)
(TMS4C1024 only)
Access time from CAS low (TMS4C1025 only)
MIN
MAX
MIN
MAX
UNIT
40
ns
55
70
ns
120
150
ns
60
75
ns
25
35
ns
25
Access time from column precharge
ta(CP)
TMS4C102_-12 TMS4C102_-15
30
tNCAC
20
ta(WHQ) Access time from W high (TMS4C1027 only)
tWRA
30
35
40
ns
ta(WLQ) Access time from W low (TMS4C1027 only)
Static column decode mode
tALW
95
115
120
ns
th(CAQ) output hold time after
address change (TMS4C1027 only)
tAOH
5
5
5
ns
tWOH
0
0
0
ns
tOFF
0
ta(C)N
-
Static column decode mode
th(WQ)
output hold time after
W low
(TMS4C1027 only)
tdis(CH) Output disable time after CAS high (see Note 4) t
25
0
30
0
35
ns
tparameters apply uniformly to TMS4C1024, TMS4C1025, TMS4C1027.
NOTE 4: tdis(CH) is specified when the output is no longer driven.
PARAMETER MEASUREMENT INFORMATION
VCC
1.31 V
=
5 V
R1 = 828 {}
OUTPUT
UNDER - - C I I I - - - - G
TEST
OUTPUT - { R L = 218 {}
UNDER
TEST
TCL
CL = 100 pF
~ 100 pF
(a) LOAD CIRCUIT
R2
=
295 {}
(b) ALTERNATE LOAD CIRCUIT
FIGURE 1. LOAD CIRCUITS FOR TIMING PARAMETERS
-I!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-157
TMS4C1024
1,048,576·81T DYNAMIC RANDOM·ACCESS MEMORY
c
timing requirements over recommended supply voltage range and operating free-air temperature range
ALT.
<:::J
CI)
3
(;'
~
s:
en
-
tc(rd)
Read cycle time (see Note 6)
tc(W)
Write cycle time
tc(rdW)
tc(P)
TMS4Cl024-10 TMS4Cl024-12 TMS4Cl024-15
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tRC
190
220
260
ns
190
220
260
ns
Read-write/read-modify-write cycle time
Page-mode read or write cycle time (see Note 7)
twc
tRWC
tpc
220
255
65
305
80
ns
55
tc(PM)
Page-mode read-modify-write cycle time
tpCM
85
100
125
ns
tw(CH)
Pulse duration, CAS high
tcp
10
15
25
tw(CL)
Pulse duration, CAS low (see Note 8)
tCAS
25
tw(RH)
Pulse duration, RAS high (precharge)
tRP
80
tRAS
100
10,000
120
10,000
100
100,000
120
100,000
Non-page-mode pulse duration, RAS low
twiRL)
(see Note 9)
tw(RL)P
Page-mode pulse duration, RAS low (see Note 9)
tw(WL)
Write pulse duration
tRASP
twp
tsu(CA)
Column-address setup time before CAS low
tsu(RA)
Row-address setup time before RAS low
Data setup time (see Note 10)
10,000
30
10,000
90
40
ns
ns
10,000
ns
100
150
ns
10,000
ns
150 100,000
ns
15
20
25
ns
tASC
0
0
0
ns
tASR
tDS
0
0
0
0
ns
0
0
ns
tRCS
0
0
0
ns
tsu(WCL) W-Iow setup time before CAS low (see Note 11)
twcs
0
0
0
ns
tsu(WCH) W-Iow setup time before CAS high
tCWL
25
30
40
ns
tsu(WRH) W-Iow setup time before RAS high
tRWL
25
30
40
ns
th(CLCA) Column-address hold time after CAS low
tCAH
20
20
25
ns
tRAH
15
15
20
ns
tAR
70
80
100
ns
25
30
ns
tsu(D)
tsu(rd)
th(RA)
. Read setup time before CAS low
Row-address hold time after RAS low
Column-address hold time after RAS low
th(RLCA)
(see Note 12)
th(D)
Data hold time (see Note 10)
tDH
20
th(RLD)
Data hold time after RAS low (see Note 12)
tDHR
70
85
110
ns
th(CHrd)
Read hold time after CAS high (see Note 15)
tRCH
0
0
0
ns
th(RHrd)
Read hold time after RAS high (see Note 15)
tRRH
10
10
10
ns
th(CLW)
Write hold time after CAS low (see Note 11)
twCH
20
25
30
ns
th(RLW)
Write hold time after RAS low (see Note 12)
twCR
70
85
100
ns
RAS low to CAS high
tCSH
100
120
150
ns
td(CHRL) Delay time, CAS high to RAS low
tCRP
0
0
0
ns
td(CLRH) Delay time, CAS low to RAS high
tRSH
25
30
40
ns
td(CLWL) Delay time, CAS low to W low (see Note 13)
tCWD
25
30
40
tRCD
25
80
25
95
30
115
ns
tRAD
20
55
20
65
25
80
ns
td(RLCH) Delay time,
td(RLCL)
Delay time, RAS low to CAS low (see Note 14)
td(RLCA) Delay time, RAS low to column-address (see Note 14
Continued next page.
NOTES:
5. Timing measurements in this table are referenced to VIL max
and VIH min.
6. All cycle times assume tt = 5 ns.
7. To guarantee tc(P) min, tsu(CA) should be greater than or
equal to tw(CH).
8. In a read-modify-write cycle, td(CLWL) and tsu(WCH)
must be observed.
9. In a read-modify-write cycle, td(RLWL) and tsu(WRH)
must be observed.
4-158
10. Referenced to the later of CAS or W in write operations.
11. Early write operation only.
12. The minimum value is measured when td(RLCL) is set to
td(RLCL) min as a reference.
13. Read-modify-write operation only.
14. Maximum value specified only to guarantee access time.
15. Either th(RHrd) or th(CHrd) must be satisfied for a read
cycle.
TEXAS
~
INSTRUMENTS
POST OFFice BOX 1443 •
ns
HOUSTON, TeXAS 77001
TMS4C1024
1,048,576-8IT DYNAMIC RANDOM-ACCESS MEMORY
timing requirements over recommended supply voltage range and operating free-air temperature range
(concluded)
ALT.
SYMBOL
TMS4Cl024-10 TMS4Cl024-12 TMS4Cl024-15
MIN
MAX
MIN
MAX
MIN
MAX
en
:!!:
<
a:
UNIT
ld(CARH)
Delay time, column-address to RAS hillh
tRAl
45
55
70
ns
td(CACH)
Delay time, column-address to CAS high
tCAl
45
55
70
ns
td(RlWL)
Delay time, RAS low to W low (see Note 13)
tRWD
100
120
150
ns
'sca
tAWD
45
55
70
ns
C
td(RLCH)R Delay time, RAS low to CAS high, (see Note 16)
tCHR
25
25
30
ns
td(CLRL)R Delay time, CAS low to RAS low, (see Note 16)
tCSR
10
10
15
ns
td(RHCL)R Delay time, RAS high to CAS low
Refresh time interval
trf
tRPC
0
0
0
ns
tREF
tT
3
Delay time, column address to W low
td(CAWL)
tt
(see Note 13)
Transition time
8
50
8
3
50
3
8
ms
50
ns
CJ
c
>-
-
NOTES: 13. Read-modify-write operation only.
16. CAS-before-RAS refresh only.
TEXAS
-IJ}
INSTRUMENTS
POST OFFice BOX 1443 •
HOUSTON, TeXAS 77001
4-159
TMS4C1025
1,048,576·81T DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and operating free-air temperature range
TMS4C1025-10 TMS4C1025-12 TMS4C1025-15
ALT.
tc(rd)
Read cycle time (see Note 6)
tc(W)
Write cycle time
tc(rdW)
tc(N)
Read-write/read-modify-write cycle time
-
tw(CH)
Pulse duration, CAS high
MIN
MAX
MIN
MAX
UNIT
MIN
tRC
190
220
260
ns
twc
tRWC
tNC
190
220
260
ns
220
255
305
ns
40
50
70
ns
tNRMW
65
75
110
ns
tcp
10
15
25
ns
Nibble-mode read or write cycle time
tc(rdW)N Nibble-mode read-modify-write cycle time
MAX
SYMBOL
tw(CL)
Pulse duration, CAS low (see Note 8)
tCAS
20
tw(RH)
Pulse duration, RAS high (precharge)
tRP
80
twIRL)
Pulse duration, RAS low
(see Note 9)
tRAS
100
tw(WL)
Write pulse duration
twp
15
20
25
ns
tsu(CA)
Column-address setup time before CAS low
tASC
0
0
0
ns
tsu(RA)
Row-address setup time before RAS low
tASR
0
0
0
ns
tsu(D)
Data setup time (see Note 10)
tDS
0
0
0
ns
tsu(rd)
Read setup time before CAS low
tRCS
0
0
0
ns
10,000
25
10,000
90
10,000
120
35
10,000
100
10,000
150
ns
ns
10,000
ns
tsu(WCL) W-Iow setup time before CAS low (see Note 11)
twcs
0
0
0
ns
tsu(WCH) W-Iow setup time before CAS high
tCWL
20
25
35
ns
tsu(WRH) W-Iow setup time before RAS high
tRWL
20
25
35
ns
th(CLCA) Column-address hold time after CAS low
tCAH
20
20
25
ns
tRAH
15
15
20
ns
tAR
70
80
100
ns
tDH
20
25
35
ns
th(RA)
Row-address hold time after RAS low
Column-address hold time after RAS low
th(RLCA)
(see Note 12)
th(D)
Data hold time (see Note 10)
th(RLD)
Data hold time after RAS low (see Note 12)
tDHR
70
85
110
ns
th(CHrd)
Read hold time after CAS high
tRCH
0
0
0
ns
th(RHrd)
Read hold time after RAS high
tRRH
10
10
10
ns
th(CLW)
Write hold time after CAS low (see Note 11)
tWCH
20
25
30
ns
tWCR
70
85
100
ns
Write hold time after RAS low
th(RLW)
(see Notes 11 and 12)
td(RLCH) Delay time, RAS low to CAS high
tCSH
100
120
150
ns
td(CHRL) Delay time, CAS high to RAS low
tCRP
0
0
0
ns
td(CLRH) Delay time, CAS low to RAS high
tRSH
20
25
35
ns
td(CLWL) Delay time, CAS low to W low (see Note 13)
tCWD
20
25
35
tRCD
25
80
25
95
30
115
ns
tRAD
20
55
20
65
25
80
ns
td(RLCL)
td(RLCA)
Delay time, RAS low to CAS low (see Note 14)
Delay time, RAS low to col~mn-address
(see Note 14)
Continued next page.
NOTES:
5. Timing measurements in this table are referenced to VIL max
and VIH min.
6. All cycle times assume tt = 5 ns.
8. In a read-modify-write cycle, td(CLWL) and tsu(WCH)
must be observed.
9. In a read-modify-write cycle, td(RLWL) and tsu(WRH)
must be observed.
4-160
10. Referenced to the later of CAS or Vii in write operations.
11. Early write operation only.
12. The minimum value is measured when td(RLCL) is set to
td(RLCL) min as a reference.
13. Read-modify-write operation only.
14. Maximum value specified only to guarantee access time.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 1443 •
ns
HOUSTON, TEXAS 77001
1MS4C1025
1,048,576-811 DYNAMIC RANDOM-ACCESS MEMORY
timing requirements over recommended supply voltage range and operating free-air temperature range
(concluded)
TMS4C1025-10 TMS4C1025-12 TMS4C1025-15
ALT.
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
td(CARH)
Delay time, column-address to RAS hi.9h
tRAL
45
55
70
td(CACH)
Delay time, column-address to CAS high
tCAL
45
55
70
ns
td(RLWL)
Delay time, RAS low to W low (see Note 13)
tRWD
100
120
150
ns
tAWD
45
55
70
ns
td(RLCH)R Delay time, RAS low to CAS high (see Note 16)
tCHR
25
25
30
ns
td(CLRL)R Delay time, CAS low to RAS low (see Note 16)
tCSR
10
10
15
ns
td(RHCL)R Delay time, RAS high to CAS low
Refresh time interval
trf
tRPC
0
0
0
ns
Delay time, column address to W low
td(CAWL)
tt
(see Note 13)
tREF
tT
Transition time
8
8
3
50
3
50
3
ns
8
ms
50
ns
..
NOTES: 13. Read-modify-write operation only.
16. CAS-before-RAS refresh only.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON,' TEXAS 77001
4-161
TMS4C1027
1,048,576·81T DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and operating free-air temperature range
ALT.
TMS4C1027-10 TMS4C1027-12 TMS4C1027-15
SYMBOL
MIN
MIN
MAX
MIN
MAX
UNIT
tc(rd)
Read cycle time (see Note 6)
tRC
190
220
260
ns
tc(W)
Write cycle time
twc
190
220
260
ns
tc(rdW)
Read-write/read-modify-write cycle time
tRWC
220
255
305
ns
tc(rd)SC
Static column decode mode read cycle time
tSCR
50
60
90
ns
tscw
50
60
90
ns
tSCRDW
100
120
150
ns
Static column decode mode
tc(W)SC
-
MAX
write cycle time
Static column decode mode,
tc(rdW)SC
read-modify-write cycle time
tw(CH)
Pulse duration, CAS high
tcp
10
tw(CL)
Pulse duration, CAS low (see Note 8)
tCAS
25
tw(RH)
Pulse duration, RAS high (precharge)
tRP
80
tRAS
100
10,000
120
10,000
tRASP
100
100,000
120
100,000
Non-static column decode mode
twIRL)
pulse duration, RAS low (see Note 9)
Static column decode mode
tw(RL)P
tw(WL)
tw(CA)
tw(WH)
pulse duration, RAS low (see Note 9)
Write pulse duration
Static column decode mode
column-address pulse duration
30
25
10,000
40
ns
10,000
100
90
150
ns
ns
10,000
ns
150 100,000
ns
twp
15
20
25
ns
tADP
45
55
70
ns
twl
10
15
25
ns
ns
Static column decode mode
W high pulse duration, inactive
15
10.000
Column-address setup time before CAS,
tsu(CA)
W low
tASC
0
0
0
tsu(CAR)
Column-address setup time before RAS
tCAR
50
60
75
ns
tsu(RA)
Row-address setup time before RAS low
tASR
0
0
0
ns
tsu(D)
Data setup time
tDS
0
0
0
ns
tsu(rd)
Read setup time before CAS low
tRCS
0
0
0
ns
tsu(WCL)
W-Iow setup time before CAS low (see Note 11)
twcs
0
0
0
ns
tsu(WCH)
W-Iow setup time before CAS high
tCWL
25
30
40
ns
tsu(WRH)
W-Iow setup time before RAS high
tRWL
25
30
40
ns
Setup time, W high to CAS high for early write,
tsu(WHCH) high impedance
tWH
0
0
0
ns
tCAH
20
20
25
ns
tRAH
15
15
20
ns
tAR
100
120
150
ns
(see Note 10)
th(CA)
Column-address hold time after CAS, W low
(see Note 10)
th(RA)
Row-address hold time after RAS low
Column-address hold time after RAS low
th(RLCA)
(see Note 18)
Continued next page.
NOTES:
5. Timing measurements in this table are referenced to VIL max
and VIH min.
6. All cycle times assume tt = 5 ns.
8. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must
be observed.
9. In a read-modify-write cycle, td(RLWL) and tsu(WRH)
must be observed.
10. Referenced to the later of CAS or W in write operations.
4-162
11. Early write operation only.
18. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4C1027
l,048,576·81T DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and operating free-air temperature range
(concluded)
TMS4C1027-10 TMS4C1027-12 TMS4C1027-15
ALT.
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
th(D)
th(RLD)
Data hold time after RAS low (see Note 17)
tDHR
th(CHrd)
Read hold time after CAS high (see Note 18)
tRCH
0
0
0
ns
th(RHrd)
Read hold time after RAS high (see Note 18)
tRRH
10
10
10
ns
ns
tDH
20
25
30
ns
70
85
110
ns
th(CLW)
Write hold time after CAS low (see Note 11)
tWCH
20
25
30
th(RLW)
Write hold time after RAS low (see Note 17)
tWCR
70
85
100
ns
th(RHCA)
Column-address hold time after RAS high
tAH
10
15
15
ns
tAHLW
95
115
135
ns
th(WLCA2)
address hold time after Wlow (see Note 13)
td(RLCH)
Delay time, RAS low to CAS high
tCSH
100
120
150
ns
td(CHRL)
Delay time, CAS high to RAS low
tCRP
0
0
0
ns
td(CLRH)
Delay time, CAS low to RAS high
tRSH
25
30
40
ns
td(CLWL)
Delay time, CAS low to W low (see Note 13)
tCWD
25
30
40
td(RLCL)
Delay time, RAS low to CAS low (see Note 14)
tRCD
25
80
25
95
30
115
ns
tRAD
20
55
20
65
25
80
ns
50
30
60
35
70
ns
Delay time, RAS low to column address
td(RLCA)
(see Note 14)
W low to column address
td(WLCA)
Delay time,
tLWAD
25
Delay time, column-address to RAS high
tRAL
45
55
70
ns
td(CACH)
Delay time, column-address to CAS high
tCAL
45
55
70
ns
td(RLWL)
Delay time, RAS low to W low (see Note 13)
tRWD
100
120
150
ns
tRSW
100
120
150
ns
tAWD
45
55
70
ns
td(RLWL2)
delay time, RAS low to second Wlow
Delay time, column address to W low
td(CAWL)
(see Note 13)
Delay time, W high to output transition
td(WQ)
from high impedance to active
td(RLCH)R Delay time, RAS low to CAS high, (see Note 16)
tow
0
0
0
ns
25
30
ns
ns
tCHR
25
Delay time, CAS low to RAS low (see Note 16)
tCSR
10
10
15
td(RHCL)R Delay time, RAS high to CAS low (see Note 16)
Refresh time interval
trf
tRPC
0
0
0
td(CLRL)R
Transition time
tt
8
tREF
tT
3
50
8
3
50
3
CJ
"sco
c
>
C
..
ns
td(CARH)
Static column decode mode
~
UNIT
Data hold time (see Note 10)
Static column decode mode second column-
en
~
ns
8
ms
50
ns
NOTES:
10.
11.
13.
14.
Referenced to later of CAS or W in write operations.
Early write operation only.
Read-modify-write operation only.
Maximum value specified only to guarantee access time.
16. CAS-before-RAS refresh only.
17. The minimum value is measured when td(RLCA) is set to
td(RLCA) min as a reference.
18. Either th(RDrd) or th(CHrd) must be satisfied for a read cycle.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-163
TMS4C1024, TMS4C1025
1,048,576·8IT DYNAMIC RANDOM·ACCESS MEMORIES
c
read cycle timing
-<:::l
m
I
5"
I '""
3
tclrdl
I
RAS~
t
•
-JI ~
CAS
tdIRLCA)
1:
I
I
I
j\
I--- tdlCLRHI ----I L---t
-...I ' - - - - - - - tdIRLCLI---J
I I
wlRHI
I
I c;::::=
tdlRLCHI
.1 ~tdICHRLI------t
t---twICLI-1 I
I I
I
t
-
•
twlRLI
ii I!
III I · •I
thIRA)~ I-!l '
X
I
I
L.tsuICAI-1
I,.
tdICACH)
If II
1\1...._ __
fI ;..!I .......,..1I I ---twICHI ____.~I ~
! 1I I II
VIL
VIH
VIL
+1
I
I'
~~RlCA)-tHR")
J· J
AO-A9~ COLUM~: ~~H~H~~. .__________ ~:~
0
I
I
w
I
~{o}}~c~R¢j
~
I
I
Q
I
H-tsu(rd)--,
I
I
I•
---~I---HI-Z
H-thICLCA)
I
i
I
I
i
I
t---taIC)----;
talCA)
• I
4-164
~{O~~~C}H~
I
I.
tdislCH)
•
I
TEXAS
-1!1
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POST OFFICE BOX 1443 •
VIL
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TEXAS
INSTRUMENTS
POST OFFice BOX 1443 •
HOUSTON, TeXAS 77001
ca
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4-167
TMS4C1024, TMS4C1025
1,048,576·8IT DYNAMIC RANDOM·ACCESS MEMORIES
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TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4C1027
1,048,576·81T DYNAMIC RANDOM·ACCESS MEMORY
write cycle timing
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TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-171
TMS4C1024
1,048,576-811 DYNAMIC RANDOM-ACCESS MEMORY
enhanced page-mode read cycle timing
-
VIH
VIL
VOH
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NOTES:
4-172
20. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write
timing specifications are not violated.
21. Access time is ta(CP) or ta(CA) dependent.
22. Output may go from three-state to an invalid data state prior to the specified access time.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4C1024
1,048,576·81T DYNAMIC RANDOM·ACCESS MEMORY
enhanced page-mode write cycle timing
tw(RH)--j
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specifications are not violated.
24. Referenced to CAS or IN. whichever occurs last.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
4-173
TMS4Cl024
1,048,576·8IT DYNAMIC RANDOM·ACCESS MEMORY
enhanced page-mode read-modify-write cycle timing
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TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
I
I
HOUSTON, TEXAS 77001
VOH
VOL
4-175
TMS4C1025
1,048,576-8IT DYNAMIC RANDOM-ACCESS MEMORY
nibble-mode write cycle timing
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------------HI-Z--------------
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4C1025
1,048,576-8IT DYNAMIC RANDOM-ACCESS MEMORY
nibble-mode read-modify-write cycle timing
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TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
VOH
VOL
4-177
TMS4C1027
1,048,576·811 DYNAMIC RANDOM·ACCESS MEMORY
static column decode mode read timing with CAS cycling
tW(RH)--j
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TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443 •
1
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1
19
19:
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HOUSTON, TEXAS 77001
VIL
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TMS4C1027
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NOTE
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NOTE 19:
Output may go from high impedance to an invalid data state prior to the specified access time.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4·179
TMS4C1027
1,048,576·BIT DYNAMIC RANDOM·ACCESS MEMORY
static column decode mode early write cycle timing
--I
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TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, ·,EXAS 77001
TMS4C1027
1,048,576-8IT DYNAMIC RANDOM-ACCESS MEMORY
static column decode mode write cycle timing
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TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
VOL
4-181
TMS4C1027
1,048,576·8IT DYNAMIC RANDOM·ACCESS MEMORY
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4-182
talR)
,-
,
VALID 'N
.
~
I
I.
-,
tsulWRH)
- I
i "
I
:::
I'
I
I
thIWLCA2)
I
,
"
I,
,
V'H
'i't.'~----:l:lii2l..Q,.j;lo.£VIL
,
!m,
I
,
: '
,
'\JJmv
thlWO)
:
~ V~~'D ~ V~~'D. ~ :::
ta(CAI'"
! - - aIWHO)~
-----HI-Z
NOTE 19:
-I
"
talCI..........,
, t--- t aICA)-----1
I"t.
_I
,•
I
'---!d(WOI---,1
t~IWLOI
----~I
~
,
"t-'.
I-----+-+_
,
,
I
1
.
tSUICA)-+-+fi l--thID)---t
I I I. !
,
II
+---f
I,
I'"' ,
y ! V:
i
..
I ', ,, I· I,,
!dIWLCA)
'r -
'tr--tW(Wll~
,
, , ,'I I
I
thICAO)
I
r--.tdICLWL)
I
I
tclrdW)SC'
,-
,', ....:..t,',1.'I
I
I I
"
: •
- ,
--j.--tsuIWCHI'
,
V'H
t--
COLUMN':
tdlC~Wll
I
VIL
VIL
I,
!---tsuICAR)
'twICA)
• I
I---thICA)----'
'I
I I
,thIRH9AI(1
~ COLUM~ X
COLUMN
VIH
I- : I .,
I
, \LJI
I II
'
--t--t
-I
thIRLCA)
I;tdlcHRL)
'\
/
"-.J
I
I I
I-
tdICLRHI'
I rtwICH)~
;1"
i
III ' / I
N
A.·A9
I
Ir-\
-{ I-tt
-
r--
twIRHI-:-i
.. 'I
twlRllP
• 1
~~:!{ V~~)
_"
,
" ,
" t d · l s I C H I - t.....
-- -....,·
"
,
"
,
~r----~:::
Output may go from high impedance to an invalid data state prior to the specified access time.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4C1027
1,048,576-8IT DYNAMIC RANDOM-ACCESS MEMORY
static column decode mode with read-modify-write cycle timing
RAS
NI' -
tw(RH)
_I
tt
, I~
I;
I L,I
tclIRLCL)
,
•
AO-A9){
I
M
~!
~i
!,
tsu~~)"1
'I
j-
I·
tdICAWL)
"
I
•
V
taIWLO)
VAUD,N
t-,
th(CAOi
ItsuIWRH) ,
"
~ :IH
IL
I
t
•
VIL
I
'I
..1...---1
~i'
VI \.
II
I
II
L-J.
'
I
thlD)
-I
-,
l '"
I t-tr---
COLUMN
I ,..
.........
tclrdW)SC
INi L.
I
..
C
!rVIH
W .......
:
,I
i 1 r- 'w,wLli
~ ~'RLDI
,I
I
M
COLUMN
~ ~tclIWLCA)---i
W~II
I
I
~
r- thlCA) ,I
thIRHCA)
',I--, tdICARH)---i
t--tdIWLCA)--t
I
I
,
!~
i
ca
i I
-I'
thlwLCA2)
! r-- twlCA) - - - - t !
t---tdIRLWL)
I
,- -\
'i
tsu(RD) ..... . I
I.
,
,
,
:
COLUMN
L
td!RLCA~
!
CJ
Os
I
' I
\l
thIRLCA)
., t
A
, hlR)
tsulRA) ,
;ROW
,
~I
...
...., t-t
o
VIL
L..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - : ,
~ L
D
r-
:-1
tW(RL)P--------------~1
I
VIH
I
I
., !-
V'H
tlVIL
thlWO)
---1
" .
I', ~~ta(C)----4
---1
talCA)
V~~D ~ V~~D ~:::
,
I
'I
I
t--- taIWHO) ~I
taIR)·
"
I
VOH
VALID
------------~t\OUT~VOL
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-183
>
Q
TMS4C1024, TMS4C1025, TMS4C1027
1,048,576·8IT DYNAMIC RANDOM·ACCESS MEMORIES
RAS only refresh timing
VIH
VIL
VIH
VIL
VIH
ROW
VIL
VOH
Q ---------------HI-Z-----------------
4-184
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4C1024, TMS4C1025, TMS4C1027
1,048,576·811 DYNAMIC RANDOM·ACCESS MEMORIES
hidden refresh cycle
~REFRESH CYCLE~
t--REF~ESH CYCLE----t
I - - - MEMORY CYCLE---t
I
I-tw(RHI~
1f
I i--tw(RLI---I I
RAS~
I
I I
I I
I •
I
I
I
'-tw(RHI~
Y
'{
I
IIth(CLCAI~
I I 1--1I
I I --;
I
I
I
tsu(RAI
II II
, ,.
VIH
VIL
I-• I
~VIH
I
\
I
VIL
I
I
H-+ tSUICAI
~ H-\h(R~1
----II'-
,It--{~rtcI(RLCHIR -1
tw(CLI
~II
i{ I
II
II
\
I r-tw(RLI .... I
I
I
I
I
AO-A9~":::
I! I
,I
tsu(rdl~
I --t
I--th(RHrdl
I
'
~
TEXAS
INSTRUMENlS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
-
I
4-185
TMS4C1024, TMS4C1025, TMS4C1027
1,048,576·8IT DYNAMIC RANDOM·ACCESS MEMORIES
automatic (CAS-before-RAS) refresh timing
i
.I"'I-----------tclrdl----------.-;-
I
I
':-twIRHl--J 1 " ' 1 . - - - - - - - t w I R L l - - - - - -.....~' I
RA5
I
--I
-
"\!
--YIt
y.1- - - - V I H
VIL
i\:'--______________~.
!
I•
\1
• tdlCLRLlR
t--tclIRHCLIR
-i
I ".
"j
-
-
-
-
~tt
tdlRLCHIR - - - - - - l l
y,.._----~---VIH
VIL
~~~I
AO-A9
:::
VOH
Q
---------------HI-Z--------------VOL
device symbolization
TI
[)
Package Cod e
N = DIP
-F,.
OJ = SOJ
-55-
TMS4C1024~
~r-
_~
~~-1-~
Front End Co de
Bar Revision Code
Assembly Sid e Code
Month Code
Lot Traceabil ity code
Speed 1-10 • -12. -151
·4-186
'111
TEXAS
INSTRUMENlS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
-
TMS4C1024, TMS4C1025, TMS4C1027
1,048,576·8IT DYNAMIC RANDOM·ACCESS MEMORIES
SUPPORT LITERATURE AVAILABLE
en
The following literature is available from Texas Instruments for assistance in DRAM design. Please contact your
local TI sales office to obtain a copy.
:E
1 MEGABIT DRAM FAMILY DATA SHEETS
~
"Eca
(.)
TMS44C256 - Specifications for the 1 Megabit DRAM organized 256K x 4 with enhanced page
mode access. (SMGS256)
TMS44C257 - Specifications for the 1 Megabit DRAM organized 256K x 4 with static column
decode. (SMGS257)
Single-In-Line Package Memory Modules
TM024GAD8, TM024EAD9 - Specifications for the socketable 1 Megabit x 8 and 1 Megabit x 9
Single-In-line Package memory modules. (SMMS102C)
..
TM024HAC4 - Specifications for the leaded 1 Megabit x 4 Single-In-line Package memory module.
(SMMS104A)
DESIGN CONSIDERATIONS
Megabit DRAM Topology - The information in this report is useful in developing algorithms for cell
sensitivity tests on TI's 1 Megabit DRAM configurations. (SMGA001)
TECHNICAL ARTICLE REPRINTS
1 Megabit Memories Demand New Design Choices - Discusses technical, technological, operational,
and packaging issues pertaining to Megabit DRAMs. (SMZY018)
1-Megabit DRAMs Spark Tech Advances - Chip designers are proposing technological changes
promising to significantly alter the design and layout landscape of the next generation of memory
boards. (SMZY020)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
4-187
c
>
C
..
4-188
TMS4C1050
1,048,576-81T FIRST-IN FIRST-OUT
PSEUDO-STATIC MEMORY
JANUARY 1988-REVISED JUNE 1988
•
262,144 x 4 Organization
•
Single 5-V Power Supply (± 10% Tolerance)
•
FIFO (First-In First-Out) Operation
- Full Word Continuous Read/Write
- Asynchronous Read/Write
•
Quasi-Static (Refresh Free)
•
High Speed Read/Write Cycle (30 ns Min)
ACCESS
TIME
(MAX)
N PACKAGE
(TOP VIEW)
W
RSTW
SWCK
DO
Dl
D2
D3
CYCLE TIME
REAO
(MIN)
WRITE
(MIN)
TMS4C1050-3
25 ns
30 ns
30 ns
TMS4C1050-4
30 ns
40 ns
40 ns
TMS4C1050-6
50 ns
60 ns
60 ns
•
=
R
50 mA at Minimum Cycle)
On-Chip Substrate Bias Generator
W
5
7
NC
NC
Dl
D3
Q3
Ql
9
Process Technology
•
Texas Instruments EPIC'" (Enhanced
Process Implanted CMOS) Technology
Operating Free-Air Temperature
... OOC to 70°C
11
13
15
17
19
CO
C
>
4
6
14
DO
NC
NC
D2
16
VSS
18
Q2
QO
8
10
12
20
C
(TOP VIEW)
26
RSTR
VCC
RSTW
2
3
SWCK
o 1 Megabit CMOS DRAM Compatible
•
1·
CJ
"§
OJ PACKAGE
SO PACKAGE
(TOP VIEW)
SRCK
C
PIN NOMENCLATURE
description
The TMS4C1 050 provides four-bit parallel and
asynchronous serial read and write operations
(first-in first-out feature) with each bit furnishing
access to 262,144 words.
The device employs state-of-art EPIC'"
(Enhanced Process Implanted CMOS)
technology for high performance, reliability and
lower power at low cost.
00-03
00-03
Data-In
R
Read Enable
RSTR
Reset Read
RSTW
Reset Write
SRCK
Serial Read Clock
SWCK
Serial Write Clock
5-V Supply
Vee
VSS
W
C
s:
-
en
»
~
»
2
capacitance over recommended supply voltage range and operating free-air temperature range,
f = 1 MHz*
PARAMETER
Ci
TEST CONDITIONS
Input capacitance
VI
VI
Co Output capacitance
=
=
0 V. f
0 V. f
=
=
"T1
JJ
S
~
o
2
UNIT
pF
1 MHz
10
pF
*Capacitance measurements are made on sample basis only.
switching characteristics over recommended supply voltage range and operating free-air temperature
range
PARAMETER
TEST CONDITIONS
Access time from SRCK high
ta(RC)
CL
CL
tv(RCH) Output disable time after SRCK high
Output disable time after R low
tv(RL)
CL
=
=
=
TMS4C1050·3 TMS4C1050·4 TMS4C1050·6
MIN
MAX
MIN
MAX
MIN MAX
50 pF
25
30
50
UNIT
ns
50 pF
6
6
6
ns
50 pF
10
10
10
ns
timing requirements over recommended supply voltage range and operating free-air temperature range
(see Notes 1, 3, and 4)
TMS4C1050-3 TMS4C1050·4 TMS4C1050·6
m
o
MAX
7
(")
2
TYP
1 MHz
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tc(W)
Write cycle time (see Notes 5 and 6)
30
106
40
106
60
106
ns
tc(R)
Read cycle time (see Notes 5 and 6)
30
106
40
106
60
106
ns
tw(WCH)
Pulse duration. SWCK high (see Note 6)
12
17
20
ns
tw(WCL)
tsu(D)
Pulse duration. SWCK low (see Note 6)
12
17
20
ns
5
5
5
ns
th(D)
Data hold time after SWCK high
10
10
10
ns
ns
Data setup time before SWCK high
tsu(WL)
W low setup time before SWCK high
0
0
0
tsu(WH)
W high setup time before SWCK high
0
0
0
tw(W)
Pulse duration. W low (see Notes 5 and 6)
10
tsu(RW)
th(RW)
RSTW setup time before SWCK high (see Note 7)
0
15
0
ns
RSTW hold time after SWCK high (see Note 7)
0
10
20
ns
tw(RCH)
Pulse duration. SRCK high (see Note 6)
12
17
20
ns
tw(RCL)
Pulse duration. SRCK low (see Note 6)'
12
17
20
ns
tsu(RL)
R low setup time before SRCK high
0
0
0
ns
tsu(RH)
R high setup time before SRCK high
0
0
0
twIRL)
tsu(RR)
Pulse duration. R low (see Notes 5 and 6)
th(RR)
RSTR hold time after SRCK high (see Note 7)
tt
Transition time
NOTES:
4-192
10
106
106
15
0
15
0
10
15
RSTR setup time before SRCK high (see Note 7)
3
30
1.
3.
4.
5.
6.
3
106
106
20
20
ns
106
ns
106
ns
20
3
ns
ns
0
30
ns
30
ns
Under absolute maximum ratings. all voltage values are with respect to VSS.
Timing measurements are referenced to VIH min = 2.4 V and VIL max = 0.8 V. tt is measured between VIH min and VIL max.
All cycle times assume tt = 3 ns.
.
No restriction for maximum value as long as the write and read address pointers are addressing the first addresses.
When the write and read address pointers are not addressing the first addresses. tc(W). tc(R). tw(WCH). tw(WCL). tw(W).
tw(RCH). tw(RCL). and twIRL) must be less than 1 ms. After improper operation [tsu(RW) over 1 msl, RSTW or RSTR
cycle is required to initialize the write or read address pointer.
7. Reset operation is not guaranteed in case tsu(RW). th(RW). t sulRR). and th(RR) do not meet the specification.
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS4C1050
1,048,576-8IT FIRST-IN FIRST-OUT
PSEUDO-STATIC MEMORY
write cycle timing (reset write)
~n th CYCLE~
(
j4- n
1
~1st CYCLE~
+ 1)th CYCLE--t
VIH
1
1
!
SWCK
VIL
I
tw(WCH)I
I
VIH
I
I
I 1
-I 1
I
I
I
1
tSU(RW)r
I
!
I
..
I
~th(RW) ---==!
I
I
I
I
I
I
j4--tsu (O)
VIL
!
I
I
I
"'tw(WCL)~
1
RSTW
1
1
1
1
1
r---tc(W)--"
1
\
--t
Z
o
ti~
a:
oLL
write cycle timing (write enable)
-I-
r-----n th CYCLE
SWCK
VIL
y \
---~
Y "
W VIH
VIL
~
"--_......J0
...-.I
1
-----------.\1
Z
DISABLE CYCLE-.....t--(n + 11th CYCLE----;
1
1
...-.I
1
I4-tsu (WL)
W
I
CJ
2:
/4-t su (WH)
~
I
C
«
\~
1
t---tw(W)~
00-03
:::=><'--_n_---J~)<
TEXAS
n+1
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
~
n+2
~
4-193
TMS4C1050
1,048,576·BIT FIRST·IN FIRST·OUT
PSEUDO·STATIC MEMORY
read cycle timing (reset read)
-I-
C
'<
104-----" th CYCLE
::l
C»
I.
1
3
~
..
VIL
s:
~
VIH
RSTR
-I.
+ 1 )th CYCLE
I
~-~
Vi
I
"I I
1 tw(RCL) I1
I
\
1 I
-I I
I
I
,-
tSU(RR)~
----+I---------+I-------J
VIH
------"'lIIM II
~
,
\
2{
* *
" + 1
~
l>
2
read cycle timing (read enable)
C')
m
2
o"
.J
1
VIH
5'
telR)
~
}>-----...,\Ir-',-------«
-I!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
"+1
TMS4C1050
1,048,576·81T FIRST·IN FIRST·OUT
PSEUDO·STATIC MEMORY
new data access mode
en
~
~
CJ
Os
SWCK
co
C
RSTW
J
NEW 0
00-03
\~-----------\\r\------------------------------X'-------'C~"""-----'X
X
X
>C
NEW 1
J''""_____'X
NEW 2
NEW 600
NEW 601
NEW 602
~
----------------------~\~\------~I
I
:!
a:
\'-----------
RSTW _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....J'\,\-I________
NEWO
-----------------------------------~I----------------------<
X
NEW 1
>C
119
120
2:
w
~
c
121
SWCK
«
J
\'------------~\TI--------------------------------NEWO
00-03
oLL
U
Z
old data access mode
RSTW
z
o
SRCK
00-03
>-
C
NEW 1
NEW 2
NEW 119
NEW 120
NEW 121
J _ ____JX'--_ ___JX'___~C~-----JX'------JX'------JX'---~>C
SRCK
----------------------~\I\~----~I
I
RSTW _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....J,\,\-I---_____
\~---------OLD 0
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
OLD 1
4-195
-
4-196
General Information
Alternate Source Directories
Glossary/Timing Conventions/Data Sheet Structure
Dynamic RAMs _ _ _
I
Dynamic RAM Modules . .
EPROMs/PROMs/EEPROMs
VLSI Memory Management Products
Military Products
Applications Information
Quality and .Reliability
Logic Symbols
Mechanical Data
ESD Guidelines
Ia
C
'<
~
m
3
C:;'
~
s:
s:
o
Q.
C
CD
en
5-2
TM4256EC4
262,144 BY 4-BIT DYNAMIC RAM MODULE
SEPTEMBER 19B5-REVISED MAY 1988
TM4256EC4 ••• C SINGLE-IN-L1NE PACKAGE
(TOPVIEWI
o 262,144 x 4 Organization
•
Q)
•
22-Pin Single-In-line Package (SIP)
•
Utilizes Four 256K Dynamic RAMs in Plastic
Chip Carrier
A8 (1)
VOO (2)
01 (3)
01 (4)
CAS (5)
A7 (6)
A5 (7)
A4 (8)
02 (9)
02 (10)
W(11)
A1 (12)
A3 (13)
A6 (14)
03 (15)
03 (16)
A2 (17)
AO (18)
RA'S (19)
04 (20)
04 (21)
o Long Refresh Period ... 4 ms (256 Cycles)
•
All Inputs, Outputs, Clocks Fully TTL
Compatible
o
3-State Outputs
•
Performance of Unmounted RAMs:
ACCESS
ACCESS
READ
TIME
TIME
COLUMN
OR
WRITE
ADDRESS
(MAXI
50 ns
CYCLE
(MINI
200 ns
ROW
ADDRESS
(MAXI
TMS4256-10
TMS4256-12
100 ns
120 ns
TMS4256-15
150 ns
60 ns
75 ns
230 ns
260 ns
o Common CAS Control with Separate Data
Input and Output Lines
o
o
en
Single 5-V Supply (10% Tolerance)
VSS (22)
Low Power Dissipation
"3
0
0
0 0
"'C
0
:E
:E
<2:
a:
OsU
ca
C
>-
C
Operating Free-Air Temperature ... 0 DC to
70 DC
PIN NOMENCLATURE
description
AO-AB
TM4256EC4
Address Inputs
Column-Address Strobe
The TM4256EC4 series is a 1024K, dynamic
random-access memory module, organized as
D1-D4
Data Inputs
262,144 x 4 bits in a 22-pin single-in-line
01-04
Data Outputs
package comprising four TMS4256FML,
Row-Address Strobe
RA"S
262,144 x 1 bit dynamic RAMs in 18-lead
5-V Supply
VDD
plastic chip-carriers mounted on top of a
Ground
VSS
substrate together with decoupling capacitors
Write Enable
W
mounted beneath the chip carriers. The onboard
capacitors eliminate the need for bypassing on
the motherboard and offer superior
performance over equivalent leaded capacitors due to reduced lead inductance. Also, with 0.3 inch board
spacing, the TM4256EC4 has a density of ten devices per square inch (approximately 4 x the density
of DIPs). With the elimination of bypass capacitors on the motherboard, reduced PC board size, and fewer
plated through-holes, a cost savings can be realized.
Each TMS4256FML is described in its data sheet and is fully electrically tested and processed according
to TI MIL-STD-8838 flows (as amended for commercial applications) prior to assembly. After assembly
onto the SIP, a further set of electrical tests is performed.
The TM4256EC4 features RAS access times of 100 ns, 120 ns, and 150 ns maximlfm.
Refresh period is extended to 4 milliseconds, and during this period each of the 256 rows must be strobed
with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power.
PRODUCTION DATA documents cantlin infarmltian
current IS of publicltian dlta. Praductl conform to
spacificltianl par the terml of Texil Instrumants
Itlndlrd wlrrlnty. Production processing daBS nat
nacesslrily include testing of III plrlmatarl.
TEXAS
l.!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Copyright © 1985. Texas Instruments Incorporated
5-3
TM4256EC4
262,144 BY 4-BIT DYNAMIC RAM MODULE
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines
are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TM4256EC4 is rated for operation from OOC to 70°C.
operation
The TM4256EC4 operates as four TMS4256FMLs connected as shown in the functional block diagram.
Refer to the TMS4256 data sheet for details of operation.
specifications
For TMS4256FML electrical specifications, refer to the TMS4256 data sheet.
single-in-line package and components
-
PC substrate: 0,79 mm (0.031 inch) minimum thickness
Bypass capacitors: Multilayer ceramic
Leads: Tin/lead solder coated over phosphor-bronze
5-4
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TM4256EC4
262,144 BY 4·BIT DYNAMIC RAM MODULE
functional block diagram
CI)
Q)
AO
Al
A2
A3
A4
A5
A6
A7
'3
"'0
o
(lSI
(121
~
(171
(131
~
(SI
(141
(.)
(61
(11
AS
RAS
CAS
W01
~
'Sco
(71
9
(191
~
(51
RAM 256Kxl
AO-AS
,.....,
(111
CAS
,....
W
(31
(41
Or------
0
VOO
01
VSS
I
9
~~ '~
,....
RAM 256Kx1
AO-AS
RAS
CAS
r---02
..
c:
>-
C
~-----t:::.. RAS
W
(91
(101
o t-----
0
VOO
02
VSS
I
RAM 256Kxl
~ AO-AS
~f---1:::.. RAS
9
....
CAS
,....
03
W
(161
(151
o t-----
0
VOO
03
VSS
I
9
~
r----
RAS
CAS
....
04
RAM 256Kxl
AO-AS
W
(20)
VOO
(2)
VSS
I
VOO
(22)
(21)
0 - 04
0
fC
--.
-L
T
C
VSS
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
5-5
TM4256EC4
262,144 BY 4-BIT DYNAMIC RAM MODULE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
C
'<
Voltage range on any pin, including VDD supply (see Note 1) .................... - 1 V to 7 V
Short circuit output current for any output ....................................... 50 rnA
Power dissipation ............................................................ 4 W
Operating free-air temperature range ....................................... 0 DC to 70 DC
Storage temperature range .......................................... - 65 DC to 150 DC
::l
D)
3
~.
~
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute·maximum·rated conditions for extended periods may affect
device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
s:
s:
o
c.
c
..
(i"
en
recommended operating conditions
VOO Supply voltage
VSS Supply voltage
MIN
NOM
MAX
4.5
5
5.5
0
UNIT
V
V
VIH
High·level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
TA
Operating free-air temperature
0
70
V
DC
NOTE 2:
The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet
for logic voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
Average operating current
= -5 rnA
= 4.2 rnA
VI = 0 V to 6.5 V, VOO =
All other pins = 0 V
Vo = 0.4 V to 5.5 V,
VOO = 5 V, CAS high
tc = minimum cycle,
during read or write cycle
All outputs open
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
1001~
TM4256EC4-10
CONDITIONS
10H
IOL
UNIT
MAX
MIN
MAX
2.4
VOO
0.4
2.4
VOO
0.4
V
±10
±10
IlA
±10
±10
IlA
280
260
rnA
18
18
rnA
232
212
rnA
200
180
rnA
0
5 V,
TM4256EC4-12
MIN
0
V
After 1 memory cycle,
1002~ Standby current
RAS and CAS high,
All outputs open
tc
1003~ Average refresh current
=
minimum cycle,
CAS high and RAS cycling,
All outputs open
tc(P)
1004~ Average page-mode current
=
minimum cycle,
RAS low and CAS cycling,
All outputs open
*1001-1004 are measured with Q1-Q4 in the same mode (Le., operating, standby, refresh, page mode).
5-6
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TM4256EC4
262,144 BY 4·BIT DYNAMIC RAM MODULE
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
1001 t
TM4256EC4-15
during read or write cycle
MIN
MAX
2.4
VOO
0.4
V
V
:E
±10
p.A
:E
±10
p.A
240
mA
18
mA
192
mA
160
mA
0
5 V,
All outputs open
All outputs open
1003 t
Average refresh current
=
minimum cycle,
CAS high and RAS cycling,
All outputs open
1004t Average page-mode current
"sca
c
RAS and CAS high,
tc
~
CJ
After 1 memory cycle,
1002t Standby current
"3
"C
o
CONDITIONS
= -5 mA
10L = 4.2 mA
VI = 0 V to 6.5 V, VOO =
All other pins = 0 V
Vo = 0.4 V to 5.5 V,
VOO = 5 V, CAS high
tc = minimum cycle,
10H
Average operating current
en
Q)
UNIT
tc(P) = minimum cycle,
RAS low and CAS cycling,
..
>
C
All outputs open
tI OD1 -IOD4 are measured with Q1-Q4 in the same mode (i.e., operating, standby refresh, page mode).
capacitance over recommended supply voltage range and operating free-air temperature range,
f = 1 MHz
MIN
PARAMETER
Ci(A)
Input capacitance, address inputs
Ci(D)
Input capacitance, data inputs
RAS
Ci(RAS)
Input capacitance,
Ci(W)
Input capacitance, W input
Ci(CAS)
Input capacitance,
CAS
input
input
MAX
pF
5
pF
20
pF
28
pF
20
pF
7
Output capacitance, data outputs
Co(Q)
Co(VOD) Decoupling capacitance
0.4
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
UNIT
20
pF
p.F
5-7
C
'<
:::::I
D)
3
C:)'
~
s:
s:
o
Co
c
(;'
en
-
5-8
TM4256FC1
1,048,576 8Y 1-81T DYNAMIC RAM MODULE
OCTOBER-19B5-REVISED FEBRUARY 19B8
TM4256FC1 •.. C SI~GLE-IN-LiNE PACKAGE
•
1,048,576 x 1 Organization
•
Single 5-V Supply (10% Tolerance)
•
22-Pin Single-ln-Iine Package (SIP)
•
Utilizes Four 256K Dynamic RAMs in Plastic
Chip Carrier
•
Long Refresh Period ... 4 ms (256 Cycles)
•
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
3-State Outputs
•
Performance of Unmounted RAMs
VSS
VDD
RAS1
Q
A3
A6
D
W
ACCESS
ACCESS
TIME
TIME
OR
ROW
COLUMN
WRITE
ADDRESS
ADDRESS
CYCLE
(MAX)
(MIN)
(MAX)
U)
CI)
(TOP VIEW)
RAS2
AO
A7
A8
CAS
RAS3
A2
A1
NC
A4
RAS4
A5
READ
TMS4256-10
100 ns
50 ns
TMS4256-12
120 ns
60 ns
200 ns
230 ns
TMS4256-15
150 ns
75 ns
260 ns
o
Common CAS Control with Separate Data
Input and Output Lines
o
Low Power Dissipation
•
Operating Free-Air Temperature ... OOC to
70°C
VDD
VSS
(1 )
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11 )
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21 )
(22)
'3
0
0
0
0
"C
0
~
~
c:r:
a:
CJ
'sm
c:
>-
..
C
I
PIN NOMENCLATURE
AO-AS
description
Address Inputs
CAS
Column-Address Strobe
D
Data Input
The TM4256FC1 series are 1024K, dynamic
No Connection
NC
random-access memory modules organized as
Q
Data Output
1,048,576 x 1 bit in a 22-pin single-in-line
Row-Address Strobes
package comprising four TMS4256FML,
5-V Supply
VDD
262,144 x 1 bit dynamic RAMs in 18-lead
Ground
VSS
plastic chip carriers mounted . on top of a
Write Enable
W
substrate together with decoupling capacitors
mounted beneath the chip carriers. The onboard
capacitors eliminate the need for bypassing on the motherboard and offer superior performance over
equivalent leaded capacitors due to reduced lead inductance. Also, with 0.3 inch board spacing, the
TM4256FC 1 has a density of ten devices per square inch (approximately 4 x the density of DIPs). With
the elimination of bypass capacitors on the motherboard, reduced PC board size, and fewer plated throughholes, a cost savings can be realized.
Each TMS4256FML is described in its data sheet and is fully electrically tested and processed according
to TI MIL-STD-8838 flows (as amended for commercial applications) prior to assembly. After assembly
onto the SIP, a further set of electrical tests is performed.
'
The TM4256FC1 features RAS access times of 100 ns, 120 ns, and 150 ns maximum.
Refresh period is extended to 4 milliseconds, and during this period each of the 256 row~ must be strobed
with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power.
PRODUCTION DATA documents contain information
current IS of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing dOBS notnecessarily include testing of all parameters.
Copyright © 19B5. Texas Instruments Incorporated
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
5-9
TM4256FC1
1,048,576 BY 1·BIT DYNAMIC RAM MODULE
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All address lines and data-in
are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
c
<::s
m
3
C:;'
The TM4256FC1 is rated for operation from ODC to 70 DC.
operation
~
s:
s:
o
The TM4256FC1 operates as four TMS4256FMLs connected as shown in the functional block diagram.
Refer to the TMS4256 data sheet for details of operation.
specifications
Co
For TMS4256FML electrical specifications, refer to the TMS4256 data sheet.
c·
CD
en
-
single-in-line package and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness epoxy-glass
Bypass capacitors: Multilayer ceramic
Leads: Tin/lead solder coated over phosphor-bronze
5-10
TEXAS
~
INSTRUMENTS
POST OFFice BOX 1443 •
HOUSTON, TeXAS 77001
TM4256FC1
1,048,576 BY 1·BIT DYNAMIC RAM MODULE
functional block diagram
AO
A1
A2
A3
A4
A5
A6
A7
AB
(10)
(16)
(15)
(5)
(1B)
(20)
(6)
(11)
()
"sco
(12)
9
RAS1
CAS
iN
e
RAS2
(3)
~ '~
(13)
(B)
,...
.......
(7)
(9)
,
RAS
CAS
W
(4)
e
aH'-Vee VSS
..
c
>
256Kx1
AO-AB
Q
a
I
256Kx1
;~ AO-AB
RAS
....... CAS
9
.......
W
e
aVee VSS
I
256Kx1
AO-AB
RAS
r... CAS
9
RAS3
(14)
~ '.:..
.....
W
e
aVee VSS
I
I
256Kx1
AO-AB
RAS
~ CAS
9
(19)
RAS4
~
.......
Vee
Vee
(2)
(21)
(1 )
VSS
-'"'
-L
-L
T C ... C T
W
a,.....
e
Veo VSS
J
(22)
VSS
-Ij}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
5-11
TM4256FC1
1,048,576 BY 1·BIT DYNAMIC RAM MODULE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
c
-<
:s
m
3
Voltage range on any pin, including VDD supply (see Note 1) .................... - 1 V to 7 V
Short circuit output current for any output ....................................... 50 mA
Power dissipation ............................................................ 4 W
Operating free-air temperature range ....................................... 0 °C to 70°C
Storage temperature range .......................................... - 65°C to 150°C
C:;"
::a
>
s:
s:o
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect
device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
Q.
..
C
CD
en
recommended operating conditions
VOO Supply voltage
VSS Supply voltage
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
V
0
VIH
High-level input voltage
2.4
6.5
V
VIL
TA
Low-level input voltage (see Note 2)
-1
0.8
Operating free-air temperature
0
70
V
DC
NOTE 2:
The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet
for logic voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
TEST
CONOITIONS
10H = -5 mA
10L = 4.2 mA
TM4256FC1-10
TM4256FC1-12
TM4256FC 1-1 5
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
2.4
VOO
0.4
2.4
VOO
0.4
2.4
VOO
0.4
V
0
0
0
V
VI = 0 V to 6.5 V,
1001
VOO = 5 V,
All other pins = 0 V
Vo = 0.4 V to 5.5 V,
VOO = 5 V, CAS high
Average operating current
tc = minimum cycle
during read or write cycle
Output open t
Standby current
RAS and CAS high,
±10
±10
±10
p.A
±10
±10
±10
p.A
80
75
70
mA
18
18
18
mA
232
212
192
mA
50
45
40
mA
After 1 memory cycle,
1002
Output open
tc = minimum cycle,
1003
Average refresh current
CAS high and RAS cycling,
Output open
tc(P) = minimum cycle,
1004
Average page-mode current
RAS low and CAS cycling,
Output open t
tAssuming standard operation of one device access.
5-12
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TM4256FC1
1,048,576 BY 1·BIT DYNAMIC RAM MODULE
capacitance over recommended supply voltage range and operating free-air temperature range,
(I)
Q)
f- 1 MHz
PARAMETER
Ci(A)
MIN
Input capacitance, address inputs
Ci(D)
Input capacitance, data inputs
Ci(RAS)
Input capacitance,
Ci(W)
Input capacitance, W input
Ci(CAS)
Input capacitance,
Co(Q)
Output capacitance, data output
RAS
input
CAS input
0.4
Co(VDD) Decoupling capacitance
MAX
"3
"C
o
UNIT
20
20
pF
5
pF
28
pF
20
28
pF
:!
:!
pF
~
CJ
"e
pF
/L F
ca
c
>-
..
C
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
5-13
c
-<
::s
m
3
cr
~
3:
3:
o
Q.
C
CD
en
-
5-14
TM4256FL8. TM4256GU8
262.144 BY 8·BIT DYNAMIC RAM MODULES
OCTOBER 19B5-REVISED FEBRUARY 1988
•
262,144 x 8 Organization
o
o
Single 5-V Supply (10% Tolerance)
o
o
o
o
o
TM4256FLS ••. L SINGLE-IN-LiNE PACKAGE
VDD
CAS
D01
AO
A1
D02
A2
A3
30-Pin Single-ln-Iine Package (SIP)
- Pinned Module for Through-Hole
Insertion (TM4256FL8)
- Leadless Module for Use with
Sockets (TM4256GU8)
Utilizes Eight 256K Dynamic RAMs in
Plastic Chip Carrier
VSS
D03
A4
A5
D04
A6
A7
D05
A8
NC
NC
D06
Long Refresh Period ... 4 ms (256 Cycles)
All Inputs, Outputs, Clocks Fully TTL
Compatible
3-State Outputs
Performance of Unmounted RAMs
READ
ACCESS
ACCESS
TIME
TIME
OR
ROW
COLUMN
WRITE
ADDRESS
(MAX)
ADDRESS
CYCLE
TMS4256-10
100 ns
TMS4256-12
TMS4256-15
(MAX)
en
(TOP VIEW)
(MIN)
50 ns
200 ns
120 ns
60 ns
230 ns
150 ns
75 ns
260 ns
o
Common CAS Control for Eight Common
Data-In and Data-Out Lines
o
o
Low Power Dissipation
W
VSS
D07
NC
D08
NC
RAS
NC
NC
VDD
Operating Free-Air Temperature ... OOC to
70°C
description
(1 )
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(1)
'3
0
0
0
0
0
0
0
0
"C
0
:21
:21
<
a:::
()
"eca
c:
>-
..
C
PIN NOMENCLATURE
The TM4256 __8 series are 2048K, dynamic
TM4256FLS
random-access memory modules organized as
AO-AS
Address Inputs
262,144 x 8 bits in a 30-pin single-in-line
Column-Address Strobe
DQ1-DQ8
package comprising eight TMS4256FML,
Data In/Data Out
262,144 x 1 bit dynamic RAMs in 18-lead
No Connection
NC
Row-Address Strobe
plastic chip carriers mounted on top of a
5-V Supply
substrate together with decoupling capacitors
VDD
mounted beneath the chip carriers. The onboard
Ground
VSS
capacitors eliminate the need for bypassing on
IN
Write Enable
the motherboard and offer superior performance
over equivalent leaded capacitors due to reduced lead inductance. Also, with 0.3 inch board spacing, the
TM4256 __8 has a density of ten devices per square inch (approximately 4 x the density of DIPs). With
the elimination of bypass capacitors on the motherboard, reduced PC board size, and fewer plated throughholes, a cost savings can be realized.
Each TMS4256FML is described in its data sheet and is fully electrically tested and processed according
to TI MIL-STD-8838 flows (as amended for commercial applications) prior to assembly. After assembly
onto the SIP, a further set of electrical tests is performed.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
nacessarily include testing of all parameters.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Copyright © 1985. Texas Instruments Incorporated
5-15
TM4256FL8. TM4256GU8
262.144 BY 8·BIT DYNAMIC RAM MODULES
c
The TM4256 __8 features RAS access times of
100 ns, 120 ns, and 150 ns maximum.
C:;'
Refresh period is extended to 4 milliseconds, and
during this period each of the 256 rows must be
strobed with RAS in order to retain data. CAS
can remain high during the refresh sequence to
conserve power.
-<
::s
m
3
~
s:
s:o
TM4256GUS ..• U SINGLE-IN-LiNE PACKAGE
{TOP VIEWI
VDD
CAS
D01
AO
A1
D02
A2
A3
VSS
D03
A4
A5
D04
A6
A7
D05
A8
NC
NC
D06
All inputs and outputs, including clocks, are
compatible with Series 74 TTL. All addresses
and data-in lines are latched on-chip to simplify
system design. Data out is unlatched to allow
greater system flexibility.
c.
c
CD
en
-
The TM4256 __ 8 is rated for operation from OOC
to 70 o C.
presence detect
This feature is included on the TM4256GU8 to
allow for hardware presence detection of the
memory module. The PRD pin for each module
in the system should be pulled high through a
pull-up resistor, resulting in a logic one when no
module is present. When a module is present,
PRD is a logic zero as this pin is connected to
VSS on the module. PRD can be used only to
detect a module's presence, not its functionality.
In a system not requiring presence detect, it is
recommended that this pin be left as a no
connect; this allows the use of either type of
module without adverse effects.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11 )
(12)
(13)
(14)
W
VSS
D07
PRD
D08
NC
RAS
NC
NC
VDD
operation
The TM4256FL8 and TM4256GU8 operate as
eight TMS4256FMLs connected as shown in the
functional block diagram. Refer to the TMS4256
data sheet for details of operation.
0
0
0
0
0
0
0
0
specifications
For TMS4256FML electrical specifications, refer
to the TMS4256 data sheet.
single-in-line package and components
PC substrate: 1,27 mm (0.05 inch) nominal
thickness epoxy-glass
Bypass capacitors: Multilayer ceramic
Leads: Tin/lead solder coated over
phosphor-bronze
Contact area for socketable devices: Nickel plate
and solder plate on top of copper
5-16
PIN NOMENCLATURE
TM4256GU8
AO-AS
Address Inputs
CAS
Column-Address Strobe
DQ1-DQ8
Data In/Data Out
NC
No Connection
PRO
Presence Detect (VSSI
RAS
Row-Address Strobe
VDD
5-V Supply
VSS
Ground
iN
Write Enable
l!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TM4256FL8. TM4256GU8
262.144 BY 8·BIT DYNAMIC RAM MODULES
functional block diagram
CI)
Q)
'3
o
"C
~
~
________________~~
-12)
CA~~/2~1~)~+-----------------~
W~~+r----------------~
DO 1 .:.,:/3;. :. .)-+++r"-;
Q
-
o02~/6;..:...)-++++-..-f
o03.!..;/1:..::;0"'-l1++-11---+-1
004.:...;11:..::3.:....)--_-i
tNot available on the TM4256FL8.
TEXAS
lJ1
INSTRUMENTS
onC:T
"«WE BOX 1443 •
HOUSTON. TEXAS 77001
5-17
TM4256FL8, TM4256GU8
262,144 BY 8·BIT DYNAMIC RAM MODULES
c
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
<:::J
Voltage range on any pin including VOO supply (see Note 1) ..................... - 1 V to 7 V
Short circuit output current for any output ....................................... 50 rnA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .... 8 W
Operating free-air temperature range ....................................... 0 °C to 70°C
Storage temperature range .......................................... - 65°C to 150°C
C)
3
n"
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
-
recommended operating conditions
MIN
4.5
VOO Supply voltage
VSS Supply voltage
VIH High-level input voltage
Vll
TA
MAX
5.5
UNIT
V
6.5
0.8
70
V
V
DC
V
0
2.4-1
low-level input voltage (see Note 2)
Operating free-air temperature
NOTE 2:
NOM
5
0
The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet
for logic voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
PARAMETER
VOL
High-level output voltage
low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
VOH
Average operating current
1001*
during read or write cycle
1002* Standby current
1003* Average refresh current
TM4256__8-10
TEST
CONDITIONS
10H = -5 mA
IOl = 4.2 mA
VI = 0 V to 6.5 V, VOO = 5 V,
All other pins = 0 V
Vo = 0.4 V to 5.5 V,
VOO = 5 V, CAS high
tc = minimum cycle
All outputs open
After 1 memory cycle,
RAS and CAS high,
All outputs open
tc = minimum cycle,
CAS high and RAS cycling,
MIN
MAX
2.4
VOO
0.4
0
TM4256 __8-12
MIN
2.4
MAX
UNIT
VOO
0.4
V
±10
±10
p.A
±10
±10
p.A
560
520
mA
36
36
mA
464
424
mA
400
360
mA
0
V
All outputs open
1004* Average page-mode current
tc(P) = minimum cycle,
RAS low and CAS cycling,
All outputs open
*1001-1004 are measured with M1-MB in the same mode (i.e., operating, standby, refresh, page mode).
5-18
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TM4256FL8, TM4256GU8
262,144 BY 8·BIT DYNAMIC RAM MODULES
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
1001 t
TM4256__8-15
TEST
PARAMETER
MIN
MAX
= -5 mA
10L = 4.2 mA
VI = 0 V to 6.5 V, VOO =
All other pins = 0 V
Vo = 0.4 V to 5.5 V,
VOO = 5 V, CAS high
tc = minimum cycle
2.4
VDD
0.4
V
±10
p.A
±10
p.A
480
mA
36
mA
384
mA
320
mA
10H
Output current (leakage)
Average operating current
during read or write cycle
UNIT
CONDITIONS
0
5 V,
All outputs open
V
..
After 1 memory cycle,
1002t Standby current
RAS and CAS high,
All outputs open
tc
1003 t
Average refresh current
=
minimum cycle,
CAS high and RAS cycling,
All outputs open
tc(P) = minimum cycle,
RAS low and CAS cycling,
1004t Average page-mode current
All outputs open
t1001-1004 are measured with Ml-M8 in the same mode (i.e., operating, standby, refresh, page mode).
capacitance over recommended supply voltage range and operating free-air temperature range,
f- 1 MHz
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
40
pF
Ci(Oa)
Input capacitance, data inputs
12
pF
Ci(RAS)
Input capacitance,
40
pF
Ci(W)
Input capacitance, W input
56
pF
Ci(CAS)
Input capacitance, CAS input
RAS
Co(VOO) Oecoupling capacitance
input
.
40
0.8
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
pF
p.F
5-19
c
<:s
D)
3
C:i"
..
5-20
TM4256EL9. TM4256GU9
262.144 BY 9-BIT DYNAMIC RAM MODULES
SEPTEMBER 19B5-REVISED MARCH 19BB
TM4256EL9 ... L SINGLE-IN-L1NE PACKAGE
•
262,144 x 9 Organization
•
Single 5-V Supply (10% Tolerance)
•
30-Pin single-In-line Package (SIP)
- Pinned Module for Through-Hole
Insertion (TM4256EL9,)
- Leadless Module for Use with
Sockets (TM4256GU9)
•
VDD
CAS
D01
AO
A1
D02
A2
A3
Utilizes Nine 256K Dynamic RAMs in Plastic
Chip Carriers
•
Long Refresh Period . . . 4 ms (256 Cycles)
•
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
3-state Outputs
•
Performance of Unmounted RAMs:
en
(TOP VIEW)
ACCESS
ACCESS
TIME
TIME
OR
ROW
COLUMN
WRITE
ADDRESS
ADDRESS
CYCLE
(MAX)
(MAX)
TMS4256-10
100 ns
50 ns
200 ns
TMS4256-12
120 ns
60 ns
230 ns
TMS4256-15
150 ns
75 ns
260 ns
VSS
D03
A4
A5
D04
A6
A7
D05
A8
NC
NC
D06
READ
(MIN)
•
Common CAS Control for Eight Common
Data-In and Data-Out Lines
•
Separate CAS Control for One Separate Pair
of Data-In and Data-Out Lines
•
Low Power Dissipation
•
Operating Free-Air Temperature ... OOC to
70°C
W
VSS
D07
NC
D08
09
RAS
CAS9
D9
VDD
(1 )
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11 )
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21 )
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
Q)
'3
D
"'C
0
~
D
D
D
D
D
D
D
D
~
~
C,)
"eca
..
c:
>
C
PIN NOMENCLATURE
description
TM4256EL9
The TM4256 __ 9 series are 2304K, dynamic
AO-A8
Address Inputs
random-access memory modules organized as
Column-Address Strobe
262,144 x 9 bits [bit nine (09, Q9) is generally
Data In/Data Out
DQ1-DQ8
used for parity and is controlled by CAS9] in a
09
Data In
NC
No Connection
30-pin single-in-line package comprising nine
TMS4256FML, 262,144 x 1 bit dynamic RAMs
Q9
Data Out
in 18-lead plastic chip carriers mounted on top
Row-Address Strobe
of a substrate together with decoupling
5-V Supply
VDD
capacitors mounted beneath the chip carriers.
Ground
VSS
The onboard capacitors eliminate the need for
W
Write Enable
bypassing on the motherboard and offer superior
performance over equivalent leaded capacitors due to reduced lead inductance. Also, with 0.3 inch board
spacing the TM4256 __ 9 has a density of ten devices per square inch (approximately 4 x the density
of DIPs). With the elimination of bypass capacitors on the motherboard, reduced PC board size, and fewer
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
speciflcatio.. per tha terms of Taxas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1985. Texas Instruments Incorporated
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
5-21
TM4256EL9, TM4256GU9
262,144 BY 9·BIT DYNAMIC RAM MODULES
c
plated through·holes, a cost savings can be
realized.
m
Each TMS4256FML is described in its data sheet
and is fully electrically tested and processed
according to TI MIL-STD-8838 flows (as
amended for commercial applications) prior to
assembly. After assembly onto the SIP, a further
set of electrical tests is performed.
<:::l
3
(;'
~
s:
s:
o
TM4256GU9 ••• U SINGLE-IN-LiNE PACKAGE
(TOP VIEW)
VDD
CAS
D01
AO
A1
DQ2
A2
A3
The TM4256 __ 9 features RAS access times of
100 ns, 120 ns, and 150 ns maximum.
c.
c
CD
(I)
..
Refresh period is extended to 4 milliseconds, and
during this period each of the 256 rows must be
strobed with RAS in order to retain data. CAS
can remain high during the refresh sequence to
conserve power.
VSS
DQ3
A4
A5
D04
A6
A7
D05
A8
NC
NC
D06
All inputs and outputs, including clocks, are
compatible with Series 74 TTL. All addresses
and data-in lines are latched on-chip to simplify
system design. Data out is unlatched to allow
greater system flexibility.
The TM4256 __ 9 is rated for operation from OOC
to 70°C.
iN
presence detect
VSS
D07
PRD
D08
09
RAS
CAS9
D9
This feature is included on the TM4256GU9 to
allow for hardware presence detection of the
memory module. The PRO pin for each module
in the system should be pulled high through a
pull-up resistor, resulting in a logic one when no
module is present. When a module is present,
PRO is a logic zero as this pin is connected to
VSS on the module. PRO can be used only to
detect a module's presence, not its functionality.
In a system not requiring presence detect, it is
recommended that this pin be left as a no
connect; this allows the use of either type of
module without adverse effects.
VDD
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
D
D
D
D
D
D
D
D
D
PIN NOMENCLATURE
TM4256GU9
operation
The TM4256EL9 and TM4256GU9 operate as
nine TMS4256FMLs connected as shown in the
functional block diagram. Refer to the TMS4256
data sheet for details of operation.
specifications
For TMS4256FML electrical specifications, refer
to the TMS4256 data sheet.
5-22
TEXAS
AO-AS
Address Inputs
CAS. CAS9
Column-Address Strobes
DOl-DOS
Data InfData Out
09
NC
Data In
PRO
Presence Detect (VSS)
09
Data Out
RAS
Row-Address Strobe
VDD
5-V Supply
VSS
Ground
W
Write Enable
~
INSTRUMENTS
POST OFFICE BOX 1443 •
No Connection
HOUSTON, TEXAS 77001
TM4256EL9, TM4256GU9
262,144 BY 9·BIT DYNAMIC RAM MODULES
single-in-line package and components
(I)
CD
PC substrate: 1,27 mm (0.05 inch) nominal thickness epoxy-glass
Bypass capacitors: Multilayer ceramic
Leads: Tin/lead solder coated over phosphor-bronze
Contact area for socketable devices: Nickel plate barrier and solder finish on top of copper foil
'3
"C
o
:E
:E
«a:
functional block diagram
(,)
"E
CO
c
..
>
C
I
-r__+-________-r__~
~9~(2~8~1______
09 (291
tNot available on the TM4256EL9.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
5-23
-
TM4256EL9, TM4256GU9
262,144 BY 9·BIT DYNAMIC RAM MODULES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
Voltage range on any pin including VDD supply (see Note 1) ..................... - 1 V to 7 V
Short circuit output current for any output ....................................... 50 rnA
Power dissipation ............................................................ 9 W
Operating free-air temperature range ....................................... 0 °C to 70°C
Storage temperature range .......................................... - 65°C to 150°C
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
VOO Supply voltage
VSS Supply voltage
UNIT
V
V
0
VIH
High-level input voltage
2.4
6.5
V
VIL
TA
Low-level input voltage (see Note 2)
-1
0.8
0
70
V
DC
Operating free-air temperature
NOTE 2:
The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet
for logic voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
UNIT
MIN
MAX
MIN
MAX
2.4
VOO
0.4
2.4
VOO
0.4
V
±10
±10
/LA
±10
±10
/LA
Average operating current
= -5 rnA
= 4.2 rnA
VI = 0 V to 6.5 V, VOO = 5 V,
All other pins = 0 V
Vo = 0.4 V to 5.5 V,
VOO = 5 V, CAS high
tc = minimum cycle
during read or write cycle
All outputs open
630
585
rnA
41
41
rnA
522
477
rnA
450
405
rnA
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
IOO1:t
TM4256__9-12
CONDITIONS
VOH
10
TM4256 __9-10
TEST
PARAMETER
Output current (leakage)
IOH
IOL
0
0
V
After 1 memory cycle,
IOO2:t Standby current
RAS and CAS high,
All outputs open
tc
IOO3:t Average refresh current
= minimum cycle,
CAS high and RAS cycling,
All outputs open
IOO4:t Average page-mode current
tc(P) = minimum cycle,
RAS low. and CAS cycling,
All outputs open
:tI 001 -I004 are measured with M1-M9 in the same mode (Le., operating, standby, refresh, page mode).
5-24
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TM4256EL9, TM4256GU9
262,144 BY 9·BIT DYNAMIC RAM MODULES
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
VOH
CONDITIONS
MIN
MAX
2.4
VDO
0.4
V
±10
p.A
±10
p.A
Average operating current
during read or write cycle
All outputs open
540
rnA
41
rnA
432
rnA
360
rnA
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
10H
0
5 V,
en
CJ)
'3
"C
o
::!
::!
UNIT
= -SmA
10L = 4.2 rnA
VI = 0 V to 6.5 V, VOO =
All other pins = 0 V
Vo = 0.4 V to 5.5 V,
VOO = 5 V, CAS high
tc = minimum cycle
High-level output voltage
VOL
1001 t
TM4256 __9-15
TEST
PARAMETER
V
~
u
"eca
c:
>-
After 1 memory cycle,
1002t Standby current
RAS and CAS high,
C
All outputs open
tc
1003 t
Average refresh current
=
minimum cycle,
CAS high and RAS cycling,
All outputs open
1004t Average page-mode current
tc(P) = minimum cycle,
RAS low and CAS cycling,
All outputs open
t1001-1004 are measured with M1-MS in the same mode (Le., operating, standby, refresh, page mode).
capacitance over recommended supply voltage range and operating free-air temperature range,
fa 1 MHz
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
45
pF
Ci(OO)
Input capacitance, data inputs
12
pF
Ci(RAS)
Input capacitance, RAS input
45
pF
Ci(W)
Input capacitance, W input
63
pF
Ci(CASS) Input capacitance, CASS input
5
pF
40
pF
pF
Ci(CAS)
Input capacitance, CAS input
Ci(OS)
Input capacitance, OS input
5
Co(OS)
Output capacitance, 09 input
7
Co(VOO) Oecoupling capacitance
0.8
"'!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
pF
p.F
5-25
c
-<::J
m
3
c;"
-
5-26
TM024HAC4
1,048,576 BY 4·BIT DYNAMIC RAM MODULE
MAY 1987-REVISED MAY 1988
•
•
0
•
•
•
•
•
Single 5-V Supply (10% Tolerance)
24-Pin Single-In-line Package (SIP)
(1 )
A9
(2)
A8
(3)
VCC
(4)
01
(5)
01
(6)
CAS
(7)
A7
(8)
A5
(9)
A4
02 (10)
02 (11 )
W (12)
A1 (13)
A3 (14)
A6 (15)
03 (16)
03 (17)
A2 (18)
AO (19)
RAS (20)
04 (21)
04 (22)
VSS (23)
NC (24)
Utilizes Four 1 Megabit Dynamic RAMs in
Plastic Small-Outline J-Lead (SOJ) Packages
Long Refresh Period ... 8 ms (512 Cycles)
All Inputs, Outputs, Clocks Fully TTL
Compatible
3-State Outputs
Performance of Unmounted RAMs:
ACCESS
•
•
•
AC SINGLE-IN-LiNE PACKAGE
(TOP VIEW)
1,048,516 x 4 Organization
ACCESS
READ
TIME
TIME
ROW
ADDRESS
(MAX)
COLUMN
OR
WRITE
ADDRESS
(MAX)
CYCLE
(MIN)
TMS4C 1024-1 0
TMS4C 1024-12
100 ns
120 ns
TMS4C1024-15
150 ns
45 ns
190 ns
55 ns
70 ns
220 ns
260 ns
Common CAS Control with Separate
Data-In and Data-Out Lines
Low Power Dissipation
Operating Free-Air Temperature ..• OOC to
10°C
Co)
"sca
c
>
..
C
description
PIN NOMENCLATURE
The TM024HAC4 is a 4,096K dynamic randomTM024HAC4
access memory module, organized as
AO-A9
Address Inputs
1,048,516 x 4 bits in a 24-pin single-in-line
Column-Address Strobe
package (SIP). The SIP is composed of four
01-04
Data Inputs
TMS4C1024DJ, 1,048,516 x 1 bit dynamic
NC
No Connection
RAMs, each in a 26/20-lead plastic small outline
01-04
Data Outputs
J-Iead package (SOJ), mounted on top of a
Row-Address Strobe
RAS
substrate together with decoupling capacitors
5-V Supply
VCC
mounted beneath the SOJs. The onboard
Ground
VSS
capacitors eliminate the need for bypassing on
W
Write Enable
the motherboard and offer superior performance
over equivalent leaded capacitors due to reduced lead inductance. With the elimination of bypass capacitors
on the motherboard, reduced PC board size, and fewer plated through-holes, a cost savings can be realized.
Each TMS4C1 024DJ is described in its data sheet and is fully electrically tested and processed 8ccording
to TI MIL-STD-8838 flows (as amended for commercial applications) prior to assembly. After assembly
onto the SIP, a further set of electrical tests is performed.
The lM024HAC4 features RAS access times of 100 ns, 120 ns, and 150 ns maximum.
"
The refresh period is extended to 8 milliseconds, and during this period each of the 512 rows must be
strobed with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve
power.
PRODUCTION DATA documents contain information
currlnt .. of publication data. Products conform to
specifications per the term. of TIxa. Instrumants
standlrd warranty. Production prDCIISing dOli not
necllsarily include tilting of an paramatars.
Copyright © 1987. Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
5-21
TM024HAC4
1,048,576 BY 4·BIT DYNAMIC RAM MODULE
c
description (continued)
-<
::s
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines
are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
D)
3
n"
~
s:
s:o
c.
The TM024HAC4 is rated for operation from OOC to 70°C.
operation
The TM024HAC4 operates as four TMS4C 1024s connected as shown in the functional block diagram
on the following page. Refer to the TMS4C 1024 data sheet for details of its operation.
specifications
c:
Ii"
tn
-
For TMS4C 1024DJ electrical specifications, refer to the TMS4C 1024 data sheet.
singJe-in-line package and components
PC substrate: 1,27 mm (0.05 in) nominal thickness; 0.005 in/in maximum warpage
Bypass capacitors: Multilayer ceramic
Leads: Tin/lead solder coated over phosphor-bronze
5-28
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TM024HAC4
1,048,576 BY 4·BIT DYNAMIC RAM MODULE
functional block diagram
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAS
eAS
W
(19)
(13)
(18)
(14)
(9)
(8)
(15)
(7)
(2)
(1 )
(20)
(6)
(12)
1024K x 1
t-~....
.....
01
(4)
AO-A9
RAS
CAS
W
o
Vee VSS
01
(5)
0l
1024K x 1
~~... RAS
AO-A9
eAS
02
..... w
(10)
o
Vee VSS
02
(11 )
-
on
1024K x 1
~~.....
......
03
(17)
AO-A9
RAS
CAS
W
oVee
03
VSS
0l
(16)
1024K x 1
~
AO-A9
RAS
.....
CAS
04
hW
(21)
oVee
04
Vee
vss
(22)
(3)
VSS
I
~ COo .C
(23iT
~
TEXAS
0rl
I
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
5-29
TM024HAC4
1,048,576 BY 4·BIT DYNAMIC RAM MODULE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
c
<::::I
Voltage range on any pin (see Note 1) ...................................... - 1 V to 7 V
Voltage range on Vee (see Note 1) ........................................ -1 V to 7 V
Short circuit output current .................................................. 50 rnA
Power dissipation ............................................................ 4 W
Operating free-air temperature range ....................................... 0 °e to 70 0 e
Storage temperature range .......................................... - 55 °e to 1 50 °e
D)
3
n'
~
s:
s:o
Q,
c
i'
(I)
-
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not"implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
VCC Supply voltage
VIH High-level input voltage
VIL
Low-level input voltage (see Note 2)
TA
Operating free-air temperature
NOTE 2:
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
2.4
6.5
V
-1
0.8
0
70
V
DC
The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet
for logic voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
PARAMETER
VOH High-level output voltage
VOL Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
ICC1 Read or write cycle current
ICC2 Standby current
TM024HAC4-10 TM024HAC4-12 TM024HAC4-1S
MIN MAX
MIN MAX
MIN MAX
TEST CONDITIONS
2.4
10H = -SmA
10L = 4.2 mA
VI = 0 V to 6.5 V, VCC = 5 V,
All other pins = 0 V to VCC
Vo = 0 V to VCC, VCC = 5.5 V,
CAS high
Minimum cycle, VCC = 5.5 V
After 1 memory cycle,
2.4
2.4
UNIT
V
0.4
0.4
0.4
V
±10
±10
±10
p.A
±10
±10
±10
p.A
280
240
220
mA
12
12
12
mA
RAS and CAS high, VIH = 2.4 V
ICC3 Average refresh current
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high
260
220
200
mA
ICC4 Average page current
tc(P) = minimum, VCC = 5.5 V,
RAS low, CAS cycling
180
140
120
mA
capacitance over recommended supply voltage range and operating free-air temperature range, f= 1 MHz
MIN
PARAMETER
UNIT
pF
Input capacitance, data inputs
Ci(RC)
Input capacitance, strobe inputs
28
pF
Ci(W)
Input capacitance, write-enable input
28
pF
Co
Output capacitance
7
pF
Input capacitance, address inputs
Ci(D)
NOTE 3: VCC equal to 5.0 V ± 0.5 V and the bias on pins under test is 0.0 V.
5-30
MAX
24
5
Ci(A)
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
pF
TM024EAD9 1.048.576 BY 9·BIT DYNAMIC RAM MODULE
TM024GAD8 1.048.576 BY 8·BIT DYNAMIC RAM MODULE
JULY 1987-REVISED MAY 1988
•
TM024EAD9 •.• AD SINGLE-IN-L1NE PACKAGE
TM024EAD9 ... 1,048,576 x 9
Organization
(TOP VIEW)
o
o
TM024GAD8 ... 1,048,576 x 8
Organization
•
Single 5-V Supply (10% Tolerance)
•
30-pin Single-ln-Iine Package (SIP)
- Leadless Module for Use with Sockets
D01
TM024EAD9 ... Utilizes Nine 1-Megabit
Dynamic RAMs in Plastic Small-Outlino
J-Lead (SOJ) Packages
D02
TM024GAD8... Utilizes Eight 1-Megabit
Dynamic RAMs in Plastic Small-Outline
J-Lead (SOJ) Packages
D03
•
•
AO
D
D
D
D
D
D
D
Do
A1
A2
A3
VSS
o
Long Refresh Period ... 8 ms (512 Cycles)
o
All Inputs, Outputs, Clocks Fully TTL
Compatible
o
3-State Output
o
Performance of Unmounted RAMs:
A4
A5
D04
A6
A7
D05
A8
A9
ACCESS
ACCESS
READ
TIME
TIME
OR
NC
D06
W
ROW
COLUMN
WRITE
ADDRESS
ADDRESS
CYCLE
VSS
D07
(MAX)
(MAX)
(MIN)
TMS4C1024-10
100 ns
45 ns
1S0 ns
NC
TMS4C 1024-12
120 ns
55 ns
220 ns
TMS4C1024-15
150 ns
70 ns
260 ns
D08
09
RAS
CAS9
o
Common CAS Control for Eight Common
Data-In and Data-Out Lines
o
Separate CAS Control for One Separate Pair
of Data-In and Data-Out Lines t
o
Low Power Dissipation
o
Operating Free Air Temperature ... OOC to
70°C
o
TM024EAD9 ... Downward Compatible
with TI TM4256GU9 (256K x 9)
o
D
VCC
CAS
D9
VCC
PIN NOMENCLATURE
TM024EAD9
TM024GAD8 ... Downward Compatible
with TM4256GU8 (256K x 8) SIP
t Available only on the TM024EADS
PRODUCTION DATA documents contain information
current IS of publication date. Products conform to
specifications par the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
..
TEXAS
AO-AS
Address Inputs
CAS, CAS9
Column-Address Strobe
DQ1-DQ8
Data In/Data Out
DS
Data In
NC
No Connection
QS
Data Out
RAS
Row-Address Strobe
VCC
5-V Supply
VSS
Ground
W
Write Enable
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Copyright © 1987. Texas Instruments Incorporated
5-31
TM024EAD9 1,048,576 BY 9·BIT DYNAMIC RAM MODULE
TM024GAD8 1,048,576 BY 8·BIT DYNAMIC RAM MODULE
description
TM024GADS •.. AD SINGLE-IN-LiNE PACKAGE
(TOP VIEW)
TM024EAD9
The TM024EAD9 is a 9216K (dynamic) randomaccess memory module organized as 1,048,576
x 9 bits [bit nine (D9, Q9) is generally used for
parity and is controlled by CAS9] in a 30-pin
single-in-line package (SIP). The SIP is composed
of nine TMS4C1024DJ, 1,048,576 x 1-bit
dynamic RAMs, each in 20/26-lead plastic smalloutline J-Iead packages (SOJs) mounted on top
of a substrate together with decoupling
capacitors mounted beneath the SOJs. Each
TMS4C1 024DJ is described in the TMS4C1 024
data sheet and is fully electrically tested and
processed according to TI MIL-STD-883B (as
amended for commercial applications) flows
prior to assembly. After assembly onto the SIP,
a further set of electrical tests is performed.
-
0
The TM024EAD9 SIP is available in the AD
single-sided, lead less module for use with
sockets.
The TM024EAD9 SIP is rated for operation from
OOC to 70°C.
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
W
TM024GAD8
VSS
D07
NC
D08
NC
RAS
NC
NC
VCC
The TM024GAD8 is a 8,192K (dynamic)
random-access memory module organized as
1,048,576 x 8 in a 30-pin single-in-line package
(SIP). The SIP is composed of eight
TMS4C1024DJ, 1,048,576 x 1 bit dynamic
RAMs, each in 20/26-lead plastic small-outline
J-Iead package (SOJ), mounted on top of a
substrate together with decoupling capacitors
mounted
beneath
the
SOJs.
Each
TMS4C1024DJ is described in its data sheet and
is fully electrically tested and processed
according to TI MIL-STD-883B flows (as
amended for commercial applications) prior to
assembly. After assembly onto the SIP, a further
set of electrical tests is performed.
0
PIN NOMENCLATURE
TM024GADS
The TM024GAD8 SIP is available in the AD
single-sided, leadless module for use with
sockets.
The TM024GAD8 SIP is rated for operation from
OOC to 70°C.
5-32
(1)
(2)
(3)
(4)
VCC
CAS
D01
AD
A1
D02
A2
A3
VSS
D03
A4
A5
D04
A6
A7
D05
A8
A9
NC
D06
TEXAS
AO-A9
Address Inputs
CAS
Column-Address Strobe
DQ1-D08
Oata In/Data Out
NC
No Connection
RAS
Row-Address Strobe
VCC
5-V Supply
VSS
Ground
Vi
Write Enable
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TM024EAD9 1,048,576 BY 9·BIT DYNAMIC RAM MODULE
TM024GAD8 1,048,576 BY 8·BIT DYNAMIC RAM MODULE
operation
(I)
CD
TM024EAD9
"S
"t:S
o
The TM024EAD9 operates as nine TMS4C1024DJs connected as shown in the functional block diagram.
Refer to the TMS4C1024 data sheet for details of its operation. The common I/O feature of the TM024EAD9
dictates the use of early write cycles to prevent contention on 0 and Q.
TM024GAD8
:s
:s-
..
C
For TMS4C 1024DJ electrical specifications, refer to the TMS4C 1024 data sheet .
single-in-Iine package and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and solder plate on top of copper
TEXAS •
INSTRUMENlS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
5-33
TM024EAD9 1,048,576 BY 9·BIT DYNAMIC RAM MODULE
functional block diagram (TM024EAD9)
C
'<
::::s
(4)
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
D)
3
C:;"
~
3:
3:
0
Q.
C
(5)
(7)
(8)
(11)
(12)
(14)
(15)
(17)
(18)
(27)
RAS
(2)
CAS
(21)
CD
en
-
W
1024K x 1
AO-A9
RAS
.. CAS
1024K x 1
~~
..
.. w
(3)
OQ1
I~ AO-A9
~----b
.....
OQ5(16)
1o
1
Qn
Vcc Vss
1024K x 1
AO-A9
RAS
CAS
...... W
1024K x 1
AO-A9
~:?::
...
DQ2
(6)
~:t ,RAS
Qn
Vcc Vss
1024K x 1
AO-A9
RAS
.. CAS
...... W
(10)
1
L::t...
..
(13)
OQ4
1
:7Mm
Vee (30)
Vee
(9)
VSS
VSS
.i2tJ.
5-34
1o
Ql
Vcc Vss
~tt..
~~
OQ3
.. ICAS
...... W
DQ6(20r
1o
t
e
_ •.
D
Qn
Vcc Vss
e
+
......
(23)
OQ7
1024K x 1
AO-A9
RAS
CAS
W
D
Qn
Vcc Vss
1
~~..
OQ8
_
(28)
CAS9
(29)
09
(26)
Q9
1024K x 1
AO-A9
RAS
CAS
W
o
Q
Vcc Vss
1
G:.....
TEXAS . .
HOUSTON, TEXAS 77001
l
1024K x 1
AO-A9
RAS
~CAS
"'w
(25)
INSTRUMENTS
POST OFFICE BOX 1443 •
RAS
CAS
W
0
VCC VSsQ l
o
Q
Vce Vss
O
1024K x 1
AO-A9
RAS
CAS
.... w
oVee
I
QO
VSS
TM024GAD8 1,048,576 BY 8·BIT DYNAMIC RAM MODULE
functional block diagram (TM024GAD8)
AO
A1
A2
A3
A4
AS
A6
A7
(41
(51
(71
(al
(111
(121
(14)
(15)
(17)
: : (1a)
AS (27)
(2)
AS (21)
1024K x 1
1024K x 1
~
AO-AS
RAS
CAS
r-... W
D
~ AO-AS
.-~
DQ1 (31
1
Vcc
I
~I
DQ5(16)
v~sQ~
J';:
RAS
CAS
~ W
D
I
1024K x 1
~
.-1 ;;
D Q2 (6)
I
D
Vcc
~~
--""'"
DQ6 (20)
VSsQ~
--
f
1024K x 1
~~
I
Vcc
Vcc
VSS
Vss
11)
i30n
(S)
I
Vcc
VlsQ~
1 J1
1024K
Vcc
1
~~
DQ7(23)
-
I
vssQl
v~sQ~
I I
1024K
1
Vcc
I
x
AO-AS
RAS
J"-.. CAS
...b", W
D
~
~
DQ4 (13)
AO-AS
RAS
CAS
W
D
AO-AS
RAS
CAS
J"-.. W
D
_ 1024K x 1
AO-AS
RAS
r-... CAS
r-... W
D
Q
h-'::-
AO-AS
RAS
CAS
.r--.. W
D
Vcc
Vl
1 J1
1024K
x
h7
D Q3 (10)
~
-
x
~
AO-AS
RAS
CAS
r-... w
-
sQ
Vcc
DQa (25)
VSsQ~
I
Vcc
VSsQQ
"4TC-- _c:;::: ~
illLJ
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
5-35
TM024EAD9 1,048,576 BY 9·BIT DYNAMIC RAM MODULE
TM024GAD8 1,048,576 BY 8·BIT DYNAMIC RAM MODULE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
Voltage range on any pin (see Note 1) ...................................... - 1 V to 7 V
Voltage range on Vee (see Note 1) ........................................ -1 V to 7 V
Short circuit output current .................................................. 50 mA
Power dissipation TM024GAD8 ................................................ 8 W
TM024EAD9 ................................................ 9 W
Operating free-air temperature range ....................................... 0 °e to 70°C
Storage temperature range .......................................... - 55°C to 150°C
-
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
V
2.4
-1
6.5
0.8
V
0
70
VCC Supply voltage
VIH High-level input voltage
Low-level input voltage (see Note 2)
VIL
TA
Operating free-air temperature
NOTE 2:
UNIT
V
DC
The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet
for logic voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
PARAMETER
VOH High-level output voltage
VOL Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
TM024EAD9-10 TM024EAD9-12 TM024EAD9-15
TEST CONDITIONS
MIN
= -5 mA
= 4.2 mA
VI = 0 V to 6.5 V, VCC = 5 V,
All other pins = 0 V to VCC
Vo = 0 V to VCC, VCC = 5.5 V,
10H
2.4
10L
CAS high
ICC1 Read or write cycle current Minimum cycle, VCC = 5.5 V
After 1 memory cycle,
ICC2 Standby current
RAS and CAS high, VIH = 2.4 V
5-36
MAX
MIN
MAX
MIN
MAX
2.4
2.4
UNIT
V
0.4
0.4
0.4
V
±10
±10
±10
p.A
±10
±10
±10
p.A
630
540
495
mA
27
27
27
mA
ICC3 Average refresh current
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high
585
495
450
mA
ICC4 Average page current
tc(P) = minimum, VCC
RAS low, CAS cycling
405
315
270
mA
=
5.5 V,
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TM024EAD9 1,048,576 BY 9-BIT DyrJAMIC RAM MODULE
TM024GAD8 1,048,576 BY 8-BIT DYNAMIC RAM MODULE
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
PARAMETER
VOH High-level output voltage
VOL Low-level output voltage
Input current (leakage)
10
Output current (leakage)
ICC1
Read or write cycle current Minimum cycle, VCC
ICC3 Average refresh current
ICC4 Average page current
MIN
= -5 rnA
= 4.2 rnA
VI = 0 V to 6.5 V, VCC = 5 V,
All other pins = 0 V to VCC
Vo = 0 V to VCC, VCC = 5.5 V,
10H
10L
II
ICC2 Standby current
TM024GAD8-10 TM024GAD8-12 TM024GAD8-15
TEST CONDITIONS
CAS high
RAS and CAS high, VIH
Minimum cycle, VCC
5.5 V
=
=
2.4 V
MAX
2.4
MIN
MAX
2.4
"3
"C
o
V
0.4
0.4
0.4
V
±10
±10
±10
p.A
±10
±10
±10
p.A
560
480
440
rnA
24
24
24
rnA
2
:E
sided assembly. Using proven design and production
C
techniques, a custom product can be built with a standard,
high-volume, cost-effective manufacturing process. TI will . .
turn-key the design, layout, manufacturing, and testing of
the module.
Os
4-8 MEG MEMORY MODULE
0
000000000 []
000000000 IJ
00000000;] IJ
OOOOOOOO;)U
o
I
DRAM
CAPACITOR
COMPONENT PITCH
AREA (sq. in ..)
I
TMS4Cl024DJ
0.10-0.22 p.F (1206 Style)
X = 0.425, Y = 0.800
18.80
Figure 1. Memory Intensive Modules
5-39
C
'<
::::I
D)
3
5"
::c
»
s:
s:
o
c.
c
CD
en
-
5-40
General Information
Alternate Source Directories
Glossary/Timing Conventions/Data Sheet Structure
Dynamic RAMs
Dynamic RAM Modules
EPROMs/PROMs/EEPROMs
VLSI Memory Management Products
Military Products
Quality and Reliability
Logic Symbols
Mechanical Data
ESD Guidelines
Ell
m
."
:JJ
o
3:
en
."
:JJ
o
3:
en
m
m
."
:JJ
o
3:
en
..
6-2
TMS27C291, TMS27C292 16,384-BIT UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
TMS27PC291 16,384-BIT PROGRAMMABLE READ-ONLY MEMORY
SEPTEMBER 19B6-REVISED APRIL 1988
J AND N PACKAGE
(TOP VIEW)
•
Organization... 2K x 8
•
Single 5-V Power Supply
•
Pin Compatible with Existing 2K x 8
Bipolar/High-Speed CMOS EPROMs
and PROMs
•
•
•
A6
A5
A4
A3
A2
A1
AO
01
02
03
All Inputs/Outputs TTL Compatible
High Speed
Max Access/Min Cycle Time
VCC
'27C/PC291-3
'27C/PC291
'27C/PC291-5
VCC
'27C/PC291-35
'27C/PC291-45
'27C/PC291-50
± 5%
'27C292-3
'27C292
'27C292-5
35 ns
45 ns
50 ns
GND
4
5
21
20
6
7
19
18
17
8
9
10
11
16
15
14
13
12
VCC
U)
A8
A9
A10
51 t
S2 t
S3 t
08
07
06
05
04
:!1
oa:
a..
w
-o
-o
w
U)
:!1
a:
a..
U)
:!1
± 10%
'27C292-35
'27C292-45
'27C292-50
(TOP VIEW)
It)
•
Low-Power CMOS Technology
o
3-State Output Buffers
•
Low Power Dissipation (VCC
- Active ... 394 mW Max
•
Erasable
•
100% Pretestable
a:
w
a..
FN PACKAGE
35 ns
45 ns
50 ns
co,..... u uu co
C')
«««z>««
3 2
5.25 V)
A1
AO
NC
01
1 282726
25
24
o
23
22
9
21
10
20
11
19
12131415161718
A10
51 t
S2 t
S3t
-
2
o
i=
«
NC
08
07
~
a:
o
LL
description
-w
:2
The TMS27C291 and TMS27C292 series are
16,384-bit, ultraviolet-light erasable, electrically
programmable read-only memories. The
TMS27PC291 series are 16,384-bit, one-time,
electrically programmable read-only memories.
These devices are fabricated using CMOS
technology for high speed and simple interface
with MOS and bipolar circuits. All inputs
(including program data inputs) can be driven by
Series 74 TTL circuits without the use of
external resistors. Each output can drive eight
Series 74 TTL circuits without external resistors.
The data outputs are three-state for connecting
multiple devices to a common bus. The J and N
dual-in-Iine packages are pin compatible with
existing 24-pin bipolar PROMs and high speed
EPROMs.
tThese pins have different pin assignments and
functions in the program mode (see page 3).
(.)
:2
~
C
READ MODE
«
PIN NOMENCLATURE
AO-Al0
Address Inputs
GND
Ground
NC
No Connection
01-08
S1. 52, 53
Outputs
VCC
5-V Power Supply
Chip Selects
The TMS27C291 and TMS27C292 are offered in dual-in-line ceramic packages (J suffix). The TMS27C291
ceramic package is designed for insertion in mounting-hole rows on 7,62-mm (300-mill centers. The
TMS27C292 ceramic package is designed for insertion in mounting-hole rows on 15,24-mm (600-mill
centers.
ADVANCE INFORMATION concarns new products in
sampling or preproduction phall of development.
tnaracteristic data and other specifications are
subject to change without notice.
~he
Copyright © 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-3
TMS27C291, TMS27C292 16,384-BIT UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
TMS27PC291 16,384-BIT PROGRAMMABLE READ-ONLY MEMORY
:B
The TMS27PC291 PROM is offered in dual-in-line plastic package (N suffix) designed for insertion in
mounting-hole rows on 7,62-mm (300-mil) centers. This version of the device is still in development, and
the ADVANCE INFORMATION notices in this data sheet pertain to the N package devices. The
TMS27PC291 PROM is also offered in a 28-lead plastic-leaded chip carrier (FN suffix) for surface mounting
applications on solder lands on 1,27-mm (50-mil) centers.
o
All devices are guaranteed for operation from 0 DC to. 70 DC.
m
s:
~
operation
"tJ
lJ
~
There are eight modes of operation for the TMS27C291, TMS27C292 and the TMS27PC291 as listed
in the following table. The read mode requires a single 5-V supply. All inputs are TTL or CMOS levels except
for Vpp during programming (13.5 V).
;-
m
m
MODE
"tJ
FUNCTION
lJ
o
s:UI
Read
Output
Output
Disable # Disable#
Output
Program
Program
Fast
Blank Check
Blank Check
Disable#
Verify
Inhibit
Program
Ones'
Zeros
Signature
S1/Vppt
VIL
VIH
X:I:
X
Vpp
Vpp
Vpp
VIL(P)'
VIL(P)
VIL
S2/vFyt
VIH
X
VIL
X
VIL(P)
VIH(P)
VIH(P)
VIL(P)
VIH(P)
VIH
S3/PGMt
ViH
X
X
VIL
VIH(P)
VIH(P)
VIL(P)
VH§
VH
VH
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
A9
X
X
X
X
X
X
X
X
X
Vpp
AO
X
X
X
X
X
X
X
X
X
VIL
Vpp
VIH
CODE
01-08
DOUT
HI-Z
HI-Z
HI-Z
DOUT
HI-Z
DIN
Ones
Zeros
MFG
DEV
97
02
tPin assignment for program mode.
:l:X can be VIL or VIH.
§VH = 12 V ± 0.5 V.
, (P) = Programming mode.
#Output can be disabled using any of these three methods.
read/output disable
When the outputs of two or more of these devices are connected in parallel on the same bus, the output
of any particular device in the circuit can be read with no interference from competing outputs of the other
devices. To read the output of a '27C291, '27PC291, or '27C292, a low-level signal is applied to 51 and
a high-level signal is applied to S2 and S3. Any other combination of logic states on these three inputs
will disable the outputs. Output data is accessed at pins Q1 through 08.
latchup immunity
Latchup immunity is a minimum of 250 mA on all inputs and outputs. This feature provides latchup immunity
beyond any potential transients at the P.C. board level when the devices are interfaced to industry-standard
TTL or MOS logic devices. The input/output layout approach controls latchup without compromising
performance or packing density.
6-4
TEXAS
-I/}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS27C291, TMS27C292 16,384·81T UV
ERASABLE PROGRAMMABLE READ·ONLY MEMORIES
TMS27PC291 16,384·BIT PROGRAMMABLE READ·ONLY MEMORY
erasure (TM527C291-__JL and
TM527C292-__JL)
PROGRAMMING AND
BLANK CHECK MODE
PIN ASSIGNMENTS
Before programming, the '27C291 or '27C292
is erased by exposing the chip through the
transparent lid to high intensity ultraviolet light
(wavelength
2537
angstroms).
The
recommended minimum exposure dose (UV
intensity x exposure time) is 25 watt-seconds
per square centimeter. A typical 12 milliwatt-persquare-centimeter, filterless UV lamp will erase
the device in 45 minutes. The lamp should be
located about 2.5 centimeters above the chip
during erasure. It should be noted that normal
ambient light contains the correct wavelength
for erasure. Therefore, when using the '27C291
or '27C292, the window should be covered with
an opaque label.
J AND N PACKAGES
tn
(TOP VIEW)
A7
A6
A3
A2
A1
AO
01
02
03
GND
programming mode pin functions
~
0
VCC
a:
A8
A9
A10
c..
Vpp
VFY
-
7
PGM
0
8
08
07
06
05
04
9
16
10
15
11
14
12
13
W
W
tn
:E
a:
c..
tn
~
0
a:
c..
w
FN PACKAGE
(TOP VIEW)
In the programming mode pins 18-20 on the
dual-in-line packages or pins 22-24 on the
plastic-leaded chip carrier no longer act as chip
selects. Pin S 1 becomes the Vpp power
supply, pin S2 becomes the VFY (verify) input,
and pin S3 becomes the PGM (program) input
in the programming mode. Programming mode
pin assignments and nomenclature are given in
the figures to the right.
U
co r-. U UCXl O"l
«««2>««
L!'l
/
A4
A3
A2
A1
AO
blank check mode
4
3 2
5
6
1 28 27 26
0
25
A10
24 Vpp
7
23 VFY
8
9
22
PGM
21
NC
20
08
NC 10
The '27C291 and '27C292 use a differential
memory cell. This means that an unprogrammed
device has ambiguous states in all address
locations. Prior to programming, the blank check
mode is used to verify that both sides of the
differential cell are erased. The blank check
mode is defined as 53 to VH and S 1 to
VIL. In this mode, S2 selects between blank
check Os and 1s.
-
NC")QU<:tL!'lCO
0022000
t9
PROGRAM MODE
PIN NOMENCLATURE
fast programming
Data is presented in parallel (eight bits) on pins
a 1 through 08. Once addresses and data are
stable, PGM is pulsed. The programming mode
is achieved when Vpp = 13.5 V, VCC = 5.0 V,
VFY = VIH, PGM = pulsed VIL. More than one
'27C291, '27C292, or '27PC291 can be
programmed when the devices are connected in
parallel. Locations can be programmed in any
order, but it is recommended that all locations
be programmed.
TEXAS
AO-A10
Address Inputs
GND
Ground
NC
P'G'M
No Connection
Program Input
Q1-Q8
Outputs
VCC
5-V Power Supply
VFY
Verify Input
Vpp
13.5-V Power Supply
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
6-5
TMS27C291, TMS27C292 16,384-BIT UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
TMS27PC291 16,384-BIT PROGRAMMABLE READ-ONLY MEMORY
Programming uses two types of programming pulses: Prime and Final. The length of the Prime pulse is
0.1 millisecond; this pulse is applied X times. After each Prime pulse, the byte being programmed is verified.
If the correct data is read, the Final programming pulse is applied. If correct data is not read, an additional
0.1-millisecond pulse is applied up to a maximum X of 4. The Final programming pulse is 24X long. This
sequence of programming and verification is performed at Vee = 5.0 V and VPP = 13.5 V. When the
full Fast programming routine is complete, all bits are verified with Vee = 5 V ± 10% (see Figure 1).
m
."
:xJ
o
s:
-o
s:
-
program inhibit
(I)
Programming may be inhibited by maintaining a high-level input on the PGM pin.
."
:xJ
program verify
Programmed bits may be verified with VPP
13.5 V when VFY
(I)
m
m
signature mode
."
:xJ
o
..
s:
(I)
The signature mode provides access to a binary code identifying the manufacturer and type. This mode
is activated when A9 is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AO, i.e., AO =
VIL accesses the manufacturer code; AO = VIH accesses device code. All other addresses must be held
at VIL. Each byte possesses odd parity on bit 08. The manufacturer code for these devices is 97, and
the device code is 02 .
FIGURE 1. FAST PROGRAMMING FLOWCHART
6-6
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS27C291, TMS27C292 16,384-BIT UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
TMS27PC291 16,384-BIT PROGRAMMABLE READ-ONLY MEMORY
logic symbols t
U)
EPROM 2048 x 8
(8)
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
(7)
Ay
Ay
Ay
Ay
(6)
(5)
(4)
(3)
0
A 2047
(2)
(1 )
(23)
(22)
(21)
(20)
51
(19)
S2
(18)
S3
Ay
Ay
Ay
Ay
(9)
Q1
(10)
Q2
(11 )
Q3
(13)
Q4
(14)
Q5
(15)
Q6
(16)
(17) Q7
Q8
-----
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
10
"
PROM 2048 x 8
(8)
0
(7)
(5)
(4)
EN
Ay
(3)
>
(2)
(1 )
0
A 2047
(23)
(22)
Ay
Ay
Ay
Ay
(21)
51
(19)
S2
(18)
S3
&
oa:
(9)
Q1
(10)
Q2
(11 )
Q3
(13)
Q4
(14)
Q5
(15)
Q6
(16)
(17) Q7
Ay
Ay
Ay
(6)
(20)
:E
0
-o
W
W
U)
:aE
a:
Q.
U)
Q8
:E
oa:
10
"
Q.
..
~
Q.
&
W
EN
2
o
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for J and N packages.
i=
c
c
«
ns
ten(VFY)
TEXAS
-w2
p's
35
tsu(D)
INSTRUMENTS
ou.
UNIT
0.1
ns
p's
6-9
TMS27C291, TMS27C292 16,384-BIT UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
TMS27PC291 16,384-BIT PROGRAMMABLE READ-ONLY MEMORY
supply current vs operating frequency
PARAMETER
m
."
Supply current
ICC
:D
o
3:
-o
-
Typt MAX*
TEST CONDITIONS
OHz::5f::51MHz
15
35
f = 10MHz
25
50
f=20MHz
32
f = 30MHz
40
60
75
UI
."
SUPPLY CURRENT
3:
UI
OPERATING FREQUENCY
:D
vs
m
m
80
."
:D
o
J
70
..
3:
UI
cr:
E
60
~
50
I
.!.c
:l
(J
l>
..... ~
>Do
~
2
:l
40
en
I
(J
!:f 30
----
10- ....
)
l/
(')
m
2
~,
-
20
."
10
-~
o
::a
s:
2
~
V
TYPICALt
""
o
0.1
l>
:::!
o
~AXIMUM* -
l...,...oo ~
Q.
C
II
)
10
f-Operating Frequency-MHz
tTypicallcc is measured at VCC = 5 V, T A = 25 DC and CMOS inputs levels.
tMaximum ICC is measured at VCC = 5.5 V, T A = 0 DC and CMOS input levels.
6-10
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
20
30
1--
UNIT
rnA
rnA
rnA
rnA
TMS27C291, TMS27C292 16,384-BIT UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
TMS27PC291 16,384-BIT PROGRAMMABLE READ-ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.0V
-J
U)
:iE
RL= 1000
OUTPUT
UNDER TEST
T
oa:
0-
W
W
CL =30 PF
U)
:iE
oa:
FIGURE 2. OUTPUT LOAD CIRCUIT
0-
read cycle timing
U)
:iE
V
.i.\
AO-A 10
_ _ _- - J
ADDRESS VALID
/1\
, ' -_ _ _ _ _- - J
,
+-1
1 - 1- _ .
talA)
,
,
........- - -
,-!
....+-I
0W
VIL
r-----t- tv(A)
s1---~~........____I~---~;f
,
z
o
I
~I.-
t en (S1)
1
1
i,r--+----____..~'__+--
S2
oa:
Vr----- VIH
---~,
__
,-
1.
1
. . . .. , . . . .
t en (S2)
,
,
i=
VIH
c
C
~
Z
I--ten(VFV)
I
I
t--tdis(VFVI
1,..--------
I
I
I.
VIH t
VIL t
~------------------VIHt
I
I
.1
•
VILt
tw(lPGM)
tw(FPGMI
m
tprogramming levels for VIH and VIL.
Z
'TI
o
::D
s:
>
::!
z
o
6-12
Vee
I
'L1
I•
("')
I
--,
. .
_ _ _""'\ I
PGM
I
i
r-tsU(VPPI
(I)
_
VIHt
____ VIL t
I.--th(AI----i
' - - , . . . - _ _ _.-J
(I)
~
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
1MS2732A
32,768-BI1 UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
AUGUST 1983-REVISED FEBRUARY 1988
•
•
•
•
•
0
•
•
0
Organization ... 4096 x 8
J PACKAGE
ITOPVIEWI
Single 5-V Power Supply
A7
A6
A5
A4
A3
A2
A1
AO
01
02
03
All Inputs/Outputs Fully TTL Compatible
Max Access/Min Cycle Times
TMS2732A-17
170 ns
TMS2732A-20
200 ns
TMS2732A-25
250 ns
TMS2732A-45
450 ns
Low Standby Power Dissipation ...
158 mW (Maximum)
JEDEC Approved Pinout ... Industry
Standard
GND
21-V Power Supply Required for
Programming
Vee
en
A8
A9
A11
:2:
0
a:
c..
G/Vpp
W
W
A10
E
en
08
07
06
05
04
:2!
0
a:
c..
en
:2:
0
a:
PIN NOMENCLATURE
N-Channel Silicon-Gate Technology
PEP4 Version Available with 168 Hour
Burn-In, and Extended Guaranteed Operating
Temperature Range from - 10°C to 85 °C
(TMS2732A-__JP4)
AD-A11
Address Inputs
E
Chip Enable
G/Vpp
Output Enable/21 V
GND
Ground
Q1-Q8
Outputs
vcc
5-V Power Supply
c..
W
description
The TMS2732A is an ultraviolet light-erasable, electrically programmable read-only memory. It has 32,768
bits organized as 4,096 words of 8-bit length. The TMS2732A only requires a single 5-volt power supply
with a tolerance of ± 5%.
The TMS2732A provides two output control lines: Output Enable (GJVpp) and Chip Enable (E). This feature
allows the GJVpp control line to eliminate bus contention in multibus microprocessor systems. The
TMS2732A has a power-down mode that reduces maximum power dissipation from 657 mW to 158 mW
when the device is placed on standby.
This EPROM is supplied in a 24-pin dual-in-line ceramic package and is designed for operation from OOC
to 70°C. The TMS2732A is also offered in the PEP4 version with an extended guaranteed operating
temperature range of - 10°C to 85 °C and 168 hour burn-in (TMS2732A-__JP4).
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of TeXIS Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Copyright © 1983. Texas Instruments Incorporated
6-13
TMS2732A
32,768-8IT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
operation
The six modes of operation for the TMS2732A are listed in the following table.
m
FUNCTION
(PINS)
""C
~
o
s:en
(18)
""C
G/Vpp
E
-o
s:
~
(20)
Vee
(24)
en
m
m
01-08
(9 to 11,
~
13 to 17)
""C
o
s:en
tx
-
MODE
Program
Inhibit
Verification
Programming
VIL
VIL
VIH
xt
21 V
VIL
21 V
5V
5V
5V
5V
5V
HI-Z
HI-Z
D
0
HI-Z
Disable
Power Down
(Standby)
Program
VIL
xt
VIH
VIL
VIH
5V
0
Read
Output
= VIH orVIL
read/output disable
The two control pins (E" and G/Vpp) must have low-level TTL signals in order to provide data at the outputs.
Chip enable (E") should be used for device selection. Output enable (GNpp) should be used to gate data to the
output pins.
power down
The power-down mode reduces the maximum power dissipation from 657 mW to 158 mW. A TTL high-level
signal applied to Eselects the power-down mode. In this mode, the outputs assume a high-impedance state,
independent of GNpp.
erasure
The TMS2732A is erased by exposing the chip to shortwave ultraviolet light that has a wavelength of 253.7
nanometers (2537 angstroms). The recommended minimum exposure dose (UV intensity x exposure time)
is fifteen watt-seconds per square centimeter. The lamp should be located about 2.5 centimeters (1 inch)
above the chip during erasure. After erasure, all bits are at a high level. It should be noted that normal ambient
light contains the correct wavelength for erasure. Therefore, when using the TMS2732A, the window should
be covered with an opaque label.
programming
Note that the application of a voltage in excess of 22 V to G/Vpp may damage the TMS2732A.
After erasure (all bits in logic 1 state), logic as are programmed into the desired locations. A logic a can only
be erased by ultraviolet light. In the program mode, GNpp is taken from a TTL low level to 21 V and data to be
programmed are applied in parallel to output pins Q 1-Q8. The location to be programmed is addressed. Once
data and addresses are stable, a 1a-millisecond TTL low-level pulse is applied to E. The maximum width of
this pulse is 11 milliseconds. The programming pulse must be applied at each location that is to be programmed.
Locations may be programmed in any order.
Several TMS2732As can be programmed simultaneously by connecting them in parallel and following the
programming sequence previously described.
program inhibit
The program inhibit is useful when programming multiple TMS2732As connected in parallel with different data.
Program inhibit can be implemented by applying a high-level signal to Eof the device that is notto be programmed
program verify
After the EPROM has been programmed, the programmed bits should be verified. To verify bit states, GNpp
and E are set to VIL.
6-14
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS2732A
32,768-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
logic symbol t
AO
A1
A2
A3
A4
A5
A6
A7
AS
A9
A10
A11
E
0
(7)
tn
:?1
(6)
(5)
(9)
A'V
A'V ~
(11 )
A'V
(13)
o A'V f -(14)
>A 4095 A'V
(15)
A'V
(16)
A'V
(17)
A'V
(4)
(3)
(2)
(1 )
-
(23)
(22)
(19)
(21)
0
0::
c..
01
07
-
OS
0
W
W
02
tn
03
:?1
04
0
0::
05
c..
06
tn
:?!
0::
c..
w
11
..
(1S)
(20)
G/Vpp
EPROM
4096 x S
(S)
L....
[PWR OWN]
"&
EN
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted):I:
Supply voltage range, Vee .......................................... - 0.3 V to 7 V
Supply voltage range, Vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 22 V
Input voltage range (except program) .................................... -0.3 to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 7 V
Operating free-air temperature range ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 0 e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 °e to 150 °e
~Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only. and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-15
TMS2732A
32,768·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
recommended operating conditions
PARAMETER
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
m
Vcc
Vpp
Supply voltage (see Note 1)
lJ
V1H
High-level input voltage
2
s:
:alJ
o
s:
VIL
TA
Low-level input voltage
-0.1
."
o
(I)
Supply voltage (see Note 2)
VCC+ 1
0.8
70
0
Operating free-air temperature
NOTES:
V
Vcc
V
V
°c
1. VCC must be applied before or at the same time as Vpp and removed after or at the same time as Vpp. The device must
not be inserted into or removed from the board when Vpp or VCC is applied.
2. Vpp can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC + Ipp.
During programming, Vpp must be maintained at 21 V (±0.5 V).
(I)
m
m
electrical characteristics over full ranges of recommended operating conditions
."
PARAMETER
lJ
o
s:
(I)
MIN
TEST CONDITIONS
MAX
2.4
UNIT
V
VOH
High-level output voltage
10H = -400 p,A
VOL
II
Low-level output voltage
10L = 2.1 rnA
VI = 0 V to 5.25 V
0.45
V
±10
p,A
Input current (leakage)
10
Output current (leakage)
Vo = 0.4 V to 5.25 V
±10
p,A
ICC1
VCC supply current (standby)
30
rnA
ICC2
VCC supply current (active)
E at VIH, GNpp at VIL
E and GNpp at VIL
125
rnA
capacitance over recommended supply voltage range and operating free-air temperature range,
f .. 1 MHzt
PARAMETER
TEST CONDITIONS
Ci
. I All except GNpp
Input capacitance I
GNpp
Co
Output capacitance
VI = 0 V
TYP*
MAX
6
9
UNIT
pF
20
8
Vo = 0 V
12
pF
tThese parameters are tested on sample basis only.
*Typical values are at T A = 25°C and nominal voltages.
switching characteristics over recommended supply voltage range and operating free-air temperature
range
TEST
PARAMETER
talA)
Access time from address
talE)
Access time from E
Output disable time from
E
or G, whichever occurs first
Output data valid time after
tv(A)
change of address,
E, or GNpp,
whichever occurs first
MIN
CL = 100 pF,
1 Series 74
ten(G) Output enable time from GIVpp
tdis t
TMS2732A-17 TMS2732A-20 TMS2732A-25 TMS2732A-45
CONDITIONS
TTL load,
tr :5 20 ns,
0
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
170
200
250
450
ns
170
200
250
450
ns
65
70
100
150
ns
130
ns
60
0
60
0
85
0
tf:5 20 ns,
See Figure 1
and Note 3
0
0
NOTE 3:
0
0
ns
For all switching characteristics and timing measurements, input pulse levels are 0.40 V and 2.4 V. Input and output reference
levels are 0.8 V and 2.0 V.
tValue calculated from 0.5 V delta to measured output level. This parameter is only sampled, not 100% tested.
6-16
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS2732A
32,768·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
recommended conditions for programming, T A -
25°C (see Note 4)
MIN
NOM
MAX
UNIT
Vee
vpp
Supply voltage
4.75
5
5.25
V
Supply voltage
20.5
21
21.5
V
VIH
High-level input voltage
2
V
-0.1
Vee+ 1
0.8
VIL
Low-level input voltage
tw(E)
E pulse duration
9
tsu(A)
Address setup time
2
/lS
tsu(D)
Data setup time
2
/lS
2
/ls
0
/lS
tsu(VPP) G/Vpp setup time
Address hold time
th(A)
10
11
Data hold time
2
/lS
th(VPP)
G/Vpp hold time
2
/lS
2
/lS
tr(PG)G
G/Vpp rise time during programming
tEHD
Delay time, data valid after
NOTE 4:
50
oa:
V
a..
w
w
ms
th(D)
trec(PG) G/Vpp recovery time
en
:!
-o
en
:!
a:
a..
en
:2:
oa:
a..
ns
E low
1
/lS
When programming the TMS2732A, connect a 0.1 /IF capacitor between G/Vpp and GND to suppress spurious voltage transients
which may damage the device.
programming characteristics, T A ... 25°C
PARAMETER
TEST CONDITIONS
VIH
High-level input voltage
VIL
VOH
Low-level input voltage
High-level output voltage (verify)
VOL
II
Low-level output voltage (verify)
IOL = 2.1 mA
Input current (all inputs)
VI = VIL or VIH
Ipp
Supply current
E = VIL, G = Vpp
ICC
Supply current
MIN
2
-0.1
IOH = -400/lA
tdis(PR) Output disable time
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MAX
UNIT
Vee+ 1
0.8
V
2.4
0
TEXAS •
INSTRUMENTS
TVP
..
V
V
0.45
V
10
/lA
50
mA
125
mA
130
ns
.6-17
w
TMS2732A
32,768-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.09 V
m
."
::u
o
OUTPUT
UNDER TEST
3:
-o
en
."
::u
3:
m
-1r
RL = 7aOO
CL = 100 pF
FIGURE 1. TYPICAL OUTPUT LOAD CIRCUIT
en
AC testing input/output wave forms
m
."
::u
o
..
2.4 V----"\1 2.0 V
\\
2.0 Vv
0.40 V----'~.,_..:o;.:.:.a::...v..::.....-~~lr~_......::o;.:.:.a::...v.:....fof-\....._ __
3:
en
A.C. testing inputs are driven at 2.4 V for logic 1 and 0.4 V for logic O. Timing measurements are made
at 2.0 V for logic 1 and 0.8 V for logic 0 for both inputs and outputs.
read cycle timing
AD-A11
===x:-------~
G/Vpp
VOH
Q1-Qa
VOL
standby mode
AO-A11
E
Q1-Qa
NOTE 3:
6-18
VIH
X
VIL
if
\
/
~I.-H
)-H10Z~
>r
VIH
VIL
VOH
VOL
For all switching characteristics and timing measurements, input pulse levels are 0.40 V and 2.4 V. Input and output timing
reference levels are o.a V and 2.0 V.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS2732A
32,768-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
program cycle timing
en
VIH
AO-A11
ADDRESS N
:E
ADDRESS N+1
oa:
VIL
a..
w
VIH/VOH
-o:a:
w
en
01-08
VIL/VOL
Vpp
-
G/Vpp
a:
a..
VIL
en
:E
VIH
E
VIL
tw(E)~
NOTE 3:
oa:
..
a..
w
For all switching characteristics and timing measurements, input pulse levels are 0.40 V and 2.4 V. Input and output timing
reference levels are 0.8 V and 2.0 V.
TEXAS
-II
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
6-19
m
"'tJ
:rJ
o
3:
-o
en
"'tJ
:rJ
3:
en
m
m
"'tJ
:rJ
o
3:
en
6-20
TMS27C32 32,768·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC32 32,768·BIT PROGRAMMABLE READ·ONLY MEMORY
MAY 1988
J & N PACKAGE
This Data Sheet is Applicable to All
TMS27C32s and TMS27PC32s Symbolized
with Code "A" as Described on Page 12.
o
Organization ... 4K x 8
o
Single 5-V Power Supply
o
Pin Compatible with Existing 32K MOS
ROMs, PROMs, and EPROMs
o
JEDEC Standard Pinout
o
All Inputs/Outputs Fully TTL Compatible
o
Max Access/Min Cycle Times
VCC ±5%
VCC ±10%
'27C32·100
'27C/PC32-120
'27C/PC32-150
'27C/PC32-2
'27C/PC32
'27C32·10
'27C/PC32-12
' 27C/PC32-15
'27C/PC32-20
'27C/PC32-25
100
120
150
200
250
(TOP VIEW)
A7
A6
A5
A4
A3
A2
Al
AO
Ql
Q2
Q3
GND
Power Saving CMOS Technology
o
Very High-Speed SNAP! Pulse Programming
or Fast Programming Algorithms
o
3-State Output Buffers
o
400 mV Guaranteed DC Noise Immunity
with Standard TTL Loads
o
Latchup Immunity of 250 rnA on All Input
and Output Lines
VI
~
A9
All
o
a:
G/Vpp
c..
w
w
A10
-o
-o
E
VI
08
12
13
~
Q7
Q6
Q5
Q4
a:
c..
VI
~
ns
ns
ns
ns
ns
o
VCC
A8
a:
c..
w
PIN NOMENCLATURE
Address Inputs
Chip Enable
E
Output Enable/12-13 V
G/Vpp
Programming Power Supply
GND
Ground
01-08
Outputs
5-V Power Supply
VCC
-
AD-A11
o
o
2:
o
~
Low Power Dissipation (VCC = 5.25 V)
- Active ... 132 mW Worst Case
- Standby ... 1.4 mW Worst Case
(CMOS Input Levels)
«
~
a:
oLL
PEP4 Version Available with 168 Hour BurnIn, and also Extended Guaranteed Operating
Temperature Ranges
2
w
(.)
description
2
«
>
c
«
The TMS27C32 series are 32,768-bit ultraviolet-light erasable, electrically programmable read-only
memories.
The TMS27PC32 series are 32,768-bit, one-time, electrically programmable read-only memories.
These devices are fabricated using power saving CMOS technology for high-speed and simple interface
with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL
circuits without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without
external resistors.
The data outputs are three-state for connecting multiple devices to a common bus. The TMS27C32 and
the TMS27PC32 are pin compatible with 24-pin 32K MOS ROMs, PROMs, and EPROMs.
The TMS27C32 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C32 is available with two guaranteed
temperature ranges of OOC to 70°C and -40°C to 85°C (TMS27C32-__JL and TMS27C32-__JE,
respectively). The TMS27C32 is also offered with 168 hour burn-in on both temperature ranges
(TMS27C32-__JL4 and TMS27C32-__JE4, respectively). (See table on page 2).
ADVANCE INFORMATION documents contain
information on new products in the samplinp or
preproduction phase of development. Charactenstic
data and other specifications are subject to change
without notice.
'I!J
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
Copyright © 1988. Texas Instruments Incorporated
6-21
TMS27C32 32,768-8IT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC32 32,768-BIT PROGRAMMABLE READ-ONLY MEMORY
The TMS27PC32 PROM is offered in a dual-in-line plastic package (N suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27PC32 is guaranteed for operation from
ODC to 70°C (NL suffix).
m
All package styles conform to JEDEC standards .
."
:0
o
s::
en
s::
-
EPROM
."
:0
o
SUFFIX FOR OPERATING
SUFFIX FOR PEP4
TEMPERATURE RANGES
168 ± 8 HR. BURN-IN
VS TEMPERATURE RANGES
ODe to 70 De
-40 De to 85 De
WITHOUT PEP4 BURN-IN
ODe to 70 De
I
-4oDe to 85 De
JL
I
JE
TMS27e32-XXX
I
I
JL4
JE4
These 32K EPROMs and PROMs operate from a single 5-V supply (in the read mode), thus are ideal for
use in microprocessor-based systems. One other 12-13 V supply is needed for programming. All
programming Signals are TTL level. These devices are programmable by either Fast or SNAP! Pulse
programming algorithms. Fast programming uses a Vpp of 12.5 V and a VCC of 6.0 V for a nominal
programming time of two minutes. SNAPI Pulse programming uses a Vpp of 13.0 V and a VCC
of 6.5 V for a nominal programming time of 1 second. For programming outside the system, existing EPROM
programmers can be used. Locations may be programmed singly, in blocks, or at random.
en
m
m
."
:0
o
s::en
operation
There are seven modes of operation listed in the following table. Read mode requires a single 5-V supply.
All inputs are TTL level except for Vpp during programming (12.5 V for Fast, or 13.0 V for SNAP! Pulse)
and 12 V on A9 for signature mode.
MODE
FUNCTION
(PINS)
E
Read
Output
Disable
Standby
Programming
Verify
Program
Signature
Inhibit
Mode
VIL
VIL
VIH
VIL
VIL
VIH
VIL
G/Vpp
(20)
VIL
VIH
xt
Vpp
VIL
Vpp
VIL
Vee
(24)
Vee
Vee
Vee
Vee
Vee
Vee
Vee
A9
(22)
X
X
X
X
X
X
VHt
VHt
AO
(8)
X
X
X
X
X
X
VIL
VIH
(18)
eODE
01-08
(9-11,
DOUT
. HI-Z
HI-Z
DIN
13-17)
tx ean be VIL or VIH.
tVH = 12 V ± 0.5 V.
6-22
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
DOUT
HI-Z
MFG
DEVICE
97
08
TMS27C32 32,768·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC32 32,768·BIT PROGRAMMABLE READ·ONLY MEMORY
read/output disable
When the outputs of two or more TMS27C32s or TMS27PC32s are connected in parallel on the same
bus, the output of any particular device in the circuit can be read with no interference from the competing
outputs of the other devices. To read the output of a single device, a low-level signal is applied to the
E and GNpp pins. All other devices in the circuit should have their outputs disabled by applying a high-level
signal to one of these pins. Output data is accessed at pins 01 to 08.
en
~
oa:
a.
w
w
latchup immunity
-o
Latchup immunity on the TMS27C32 and TMS27PC32 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the
devices are interfaced to industry-standard TTL or MOS logic devices. Input/output layout approach controls
latchup without compromising performance or packing density.
en
~
a:
a.
For more information see application report SMLA001; "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family," available through TI Field Sales Offices.
power down
Active ICC current can be reduced from 30 mA to 500 p.A (TTL-level inputs) or 250 p.A (CMOS-level inputs)
by applying a high TTL signal to the E pin. In this mode all outputs are in the high-impedance state .
erasure (TMS27C32)
Before programming, the TMS27C32 EPROM is erased by exposing the chip through the transparent lid
to high intensity ultraviolet light (wavelength 2537 angstroms). EPROM erasure before programming is
necessary to assure that all bits are in the logic 1 (high) state. Logic Os are programmed into the desired
locations. A programmed logic 0 can be erased only by ultraviolet light. The recommended minimum
ultraviolet light exposure dose (UV intensity x exposure time) is 15 watt-seconds per square centimeter.
A typical 12-milliwatt-per-square-centimeter, filterless UV lamp will erase the device in 21 minutes. The
lamp should be located about 2.5 centimeters above the chip during erasure. It should be noted that normal
ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C32, the
window should be covered with an opaque label.
en
~
oa:
..
a.
w
initializing (TMS27PC32)
The one-time programmable TMS27PC32 PROM is provided with all bits in the logic 1 state, then logic Os
are programmed into the desired locations. Logic Os programmed into a PROM cannot be erased.
SNAP! Pulse programming
The 32K EPROM and PROM can be programmed using the TI SNAP! Pulse programming algorithm illustrated
by the flowchart in Figure 1, which can reduce programming time to a nominal of one second. Actual
programming time will vary as a function of the programmer used.
Data is presented in parallel (eight bits) on pins 01 to 08. Once addresses and data are stable,
E is pulsed.
The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (p.s) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten)
100 p's pulses per byte are provided before a failure is recognized.
The programming mode is achieved when GNpp = 13.0 V, VCC = 6.5 V, and E = V,L. More than one
device can be programmed when the devices are connected in parallel. Locations can be programmed
in any order. When the SNAP! Pulse programming routine is complete, all bits are verified when
VCC = 5 V, GNpp = V'L, and E = V,L.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-23
TMS27C32 32,768·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC32 32,768·BIT PROGRAMMABLE READ·ONLY MEMORY
fast programming
The 32K EPROM and PROM can be programmed using the Fast programming algorithm illustrated by the
flowchart in Figure 2. During Fast programming, data is presented in parallel (eight bits) on pins 01 to
08. Once addresses and data are stable, E is pulsed. The programming mode is achieved when
G/Vpp = 12.5 V, Vee = 6.0 V, and E =VIL. More than one device can be programmed when the devices
are connected in parallel. Locations can be programmed in any order.
m
."
:::u
o
s:
s:
-
Fast programming uses two types of programming pulses: Prime and Final. The length of the Prime pulse
is 1 millisecond; this pulse is applied X times. After each Prime pulse, the byte being programmed is verified .
If the correct data is read, the Final programming pulse is applied; if correct data is not read, an additional
1 millisecond pulse is applied up to a maximum X of 25. The Final programming pulse is 3X long. This
sequence of programming and verification is performed at Vee = 6.0 V and G/Vpp = 12.5 V. When the
full Fast programming routine is complete, all bits are verified when Vee = G/Vpp = 5 V.
en
."
:::u
o
en
m
m
program inhibit
."
:::u
Programming may be inhibited by maintaining a high level input on the
s:en
program verify
o
E pin.
Programmed bits may be verified when G/Vpp and E = VIL.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode
is activated when A9 (pin 22) is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AO
(pin 8); i.e., AO = VIL accesses the manufacturer code which is output on 01-08; AO = VIH accesses
the device code which is output on 01-08. All other addresses must be held at VIL. Each byte possesses
odd parity on bit 08., The manufacturer code for these devices is 97, and the device code is 08.
6-24
TEXAS
-1.!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS27C32 32,768-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC32 32,768-BIT PROGRAMMABLE READ-ONLY MEMORY
(I)
~
ADDRESS = FIRST LOCATION
oa:
VCC
= 6.5
V ± 0.25 V. G/Vpp
=
a..
-
13.0 V ± 0.25 V
PROGRAM ONE PULSE = tw = 100
w
w
"s 14----1
INCREMENT ADDRESS
( I)
PROGRAM
MODE
~
oa:
a..
( I)
~
NO
oa:
a..
w
-
ADDRESS = FIRST LOCATION
x
= 0
1 4 - - - - - - - - - - - 1 PROGRAM ONE PULSE
= tw = 100 IlS
INTERACTIVE
MODE
X=X+11---_<
NO
YES
DEVICE FAILED
VCC = 5.0 V ± 0.5 V. G/Vpp = VIL
]TION
FINAL
FIGURE 1. SNAPI PULSE PROGRAMMING FLOWCHART
TEXAS
-1!1
INSTRUMENlS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-25
TMS27C32 32,768-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC32 32,768-BIT PROGRAMMABLE READ-ONLY MEMORY
m
"tJ
::JJ
o
3:
-o
en
"tJ
::JJ
3:
en
m
m
"tJ
::JJ
o
3:
en
YES
DEVICE
FAILED
INCREMENT
ADDRESS
FIGURE 2. FAST PROGRAMMING FLOWCHART
6-26
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS27C32 32,768-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC32 32,768-BIT PROGRAMMABLE READ-ONLY MEMORY
logic symbols t
EPROM 4096 x B
AO
A1
A2
A3
A4
A5
A6
A7
AB
A9
A10
A11
E
G/Vpp
(B)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(23)
(22)
(19)
(21)
(1B)
11
A1
A2
A3
A4
A5
AS
A7
AB
A9
A10
A11
O_
A_
4095
~
(20)
AO
r-..
A'V
A'V
A'V
A'V
A'V
A'V
A'V
en
PROM 4096 x B
0
(9)
(10)
(11 )
(13)
(14)
(15)
(16)
(17)
01
02
03
04
05
06
07
OB
E
[PWR OWN)
~EN
G/Vpp
(B)
(7)
(6)
(5)
(4)
(3)
(2)
(1 )
(23)
(22)
(19)
(21)
(1B)
:E
oa:
0'
O_
A_
4095
A'V
A'V
A'V
A'V
A'V
A'V
A'V
Q.
(9)
01
(10)
(11)
(13)
(14)
(15)
(1S)
(17)
-o
-o
W
W
02
en
03
:E
04
05
OS
a:
Q.
07
en
OB
:E
11
~
(20)
r-...
[PWR OWN)
a:
Q.
1EN
W
2
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
o
i=
<
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)*
Supply voltage range, VCC (see Note 1) ................................. -0.6 V to 7 V
Supply voltage range, Vpp (see Note 1) . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . .. - 0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 . . . . . . . . . . . . . . . . . . .. -0.6 V to 6.5 V
A9 ... '.' ............................ -0.6 V to 13.5 V
Output voltage range (see Note 1) ................................ -0.6 V to VCC + 1 V
Operating free-air temperature range ('27C32-__JL and JL4; '27PC32-__NL) ........ ooC to 70°C
Operating free-air temperature range ('27C32-__JE and JE4) .... . . . . . . . . . . . .. - 40°C to 85 °C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
::?1
a:
o
u.
-w
2
CJ
NOTE 1: Under absolute maximum ratings, voltage values are with respect to GND.
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect
device reliability.
TEXAS
-1!1
INSTRUMENlS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
2
~
<
C
6-27
TMS27C32 32,768·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC32 32,768·BIT. PROGRAMMABLE READ·ONLY MEMORY
recommended operating conditions
m
"
o
:lJ
-o"
s:
:lJ
G/Vpp Supply voltage
m
m
5
5.25
6.25
5.75
6
6.25
6.25
6.5
6.75
6.25
6.5
6.75
12
12.5
13
12
12.5
13
12.75
13
13.25
12.75
13
13.25
Vee+ 1
Vee+ 1
0.8
2
o"
:lJ
Vee- O.2
-0.5
TTL
Low-level input voltage
eMOS
Operating free-air temperature (See table, page 2)
VIL
s:
2
eMOS
TA
UNIT
6
TTL
High-level input voltage
VIH
'27C/PC32-20
5.75
Fast programming algorithm
SNAPI Pulse programming algorithm
'27C/PC32-15
'27C/PC32-2
4.75
Read mode (see Note 2)
Supply voltage Fast programming algorithm
SNAPI Pulse programming algorithm
(I)
'27C/PC32-12
'27C/PC32-150
MAX
MIN
Vee
'27C32-10
'27C/PC32-120
'27C/PC32
NOM
s:
(I)
'27C32-100
-0.5
0.2
(See table, page 2)
'27C/PC32-25
MIN
MAX
NOM
4.5
5.5
5
Vee+ 1
Vee- 0 . 2
-0.5
Vee+ 1
0.8
0.2
-0.5
(See table, page 2)
V
V
V
V
°C
(I)
NOTE 2:
_
•
Vee must be applied before or at the same time as Vpp and removed after or at the same time as Vpp. The device must
not be inserted into or removed from the board when Vpp or Vee is applied.
electrical characteristics over full ranges of recommended operating conditions
l>
PARAMETER
C
<
l>
= -2.5 mA
10H = -20 p.A
10L = 2.1 mA
10L = 20 p.A
VI = 0 V to 5.5 V
Vo = 0 V to Vee
G/Vpp = 13 V
Vee = 5.5 V, E = VIH
Vee = 5.5 V, E = Vee
Vee = 5.5 V, E = VIL,
tcycle = minimum cycle time,
VOH High-level output voltage
:2
(")
m
-
:2
."
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
Ipp
G/Vpp supply current (during program pulse)
I TTL-input level
o
lee1
s:
leC2 Vee supply current (active)
Vee supply current
::D
l>
(standby)
1 eMOS-input level .
Typt
MIN
MAX
3.5
UNIT
V
V
Vee- 0 . 1
0.4
V
0.1
V
±1
p.A
±1
p.A
50
mA
250
500
p.A
100
250
p.A
10
25
mA
35
outputs open
:::i
o
:2
TEST CONDITIONS
10H
tTypical values are at T A = 25°C and nominal voltages.
capacitance over recommended supply voltage range and operating free-air temperature range,
f = 1 MHz*
PARAMETER
ei
Input capacitance
eo
Output capacitance
TEST CONDITIONS
= 0 V, f = 1 MHz
Vo = 0 V, f = 1 MHz
VI
tTypical values are at T A = 25°e and nominal voltages.
:l:eapacitance measurements are made on sample basis only.
6-28
TEXAS
-1!1
INSTRUM~NTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MIN
Typt
MAX
6
10
pF
10
14
pF
UNIT
TMS27C32 32.768-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC32 32.768-BIT PROGRAMMABLE READ-ONLY MEMORY
switching characteristics over full ranges of recommended operating conditions (see Notes 3 and 4)
TEST CONDITIONS
PARAMETER
(SEE NOTES 3 AND 4)
'27C32-100
'27C/PC32-120 '27C/PC32-150
'27C32-10
'27C/PC32-12
MIN
MAX
MIN
'27C/PC32-15
MAX
MIN
UNIT
en
MAX
talA)
Access time from address
100
120
150
ns
talE)
Access time from chip enable
100
120
150
ns
ten(G)
Output enable time from G/Vpp
CL = 100 pF,
50
55
75
ns
Output disable time from G/Vpp
1 Series 74 TTL Load,
60
ns
tdis
or
E,
change of address,
E,
40
0
45
0
oa:
c..
w
w
o
en
:2:
Input tf :5 20 ns
Output data valid time after
tv(A)
0
Input tr :5 20 ns,
whichever occurs first t
:2:
or
0
0
0
a:
ns
c..
G/Vpp, whichever occurs first t
en
~
TEST CONDITIONS
PARAMETER
(SEE NOTES 3 AND 4)
'27C/PC32-2
'27C/PC32
'27C/PC32-20
'27C/PC32-25
MIN
talA)
Access time from address
talE)
Access time from chip enable
ten(G)
Output enable time from G/Vpp
tdis
tv(A)
CL = 100 pF,
1 Series 74 TTL Load,
Output disable time from G/Vpp or E, whichever
Input tr :5 20 ns,
occurs first t
Input tf :5 20 ns
Output data valid time after change of address,
E,
0
MAX
MIN
c..
w
MAX
200
250
ns
200
250
ns
75
100
ns
60
ns
o
ns
«
60
0
0
or G/Vpp, whichever occurs first t
oa:
UNIT
0
;;2
i=
~
tValue calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
swit~ing characteristics for programming: Vee = 6 V and G/Vpp = 12.5 V (Fast) or Vee
and G/Vpp = 13.0 V (SNAP! Pulse), T A = 25°e (see Note 3)
PARAMETER
tdis(G)
ten(G)
NOTES:
MIN
Output disable time from G/Vpp
0
Output enable time from G/Vpp
NOM
= 6.50 V
MAX
UNIT
130
ns
150
ns
a:
o
LL
-Zw
(.)
3. For all switching characteristics the input pulse levels are 0.40 V to 2.4 V. Timing measurements are made at 2.0 V for
logic 1 and O.B V for logic 0 (reference page 11).
4. Common test conditions apply for tdis except during programming.
;2
c
«
TEXAS
.J.!p
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
6-29
TMS27C32 32,768·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC32 32,768·BIT PROGRAMMABLE READ·ONLY READ·ONLY MEMORY
recommended timing requirements for programming: Vee = 6 V and G/Vpp
12.5 V (Fast) or
Vee = 6.50 V and G/Vpp = 13.0 V (SNAP! Pulse), TA = 25°e (see Note 3)
m
"0
tw(lPGM)
Initial program pulse duration
o
tw(FPGM)
Final pulse duration
:xJ
s:
-
I Fast programming algorithm
I SNAPI Pulse programming algorithm
I Fast programming only
MIN
NOM
0.95
1
MAX
1.05
95
100
105
p's
78.75
ms
2.85
UNIT
ms
tsu(A)
Address setup time
2
p's
tsu(D)
Data setup time
2
p.s
:xJ
tsu(VPP)
G/Vpp setup time
2
p.s
s:
en
tsu(VeC)
Vec setup time
2
p.s
th(A)
Address hold time
0
p's
th(D)
Data hold time
2
p.s
th(VPP)
G/Vpp hold time
2
p's
"0
trec(PG)
G/Vpp recovery time
2
o
tEHD
Data valid from E low
tr(PG)G
G/Vpp rise time
en
"0
o
m
m
:xJ
s:
en
_NOTE 3,
50
p's
ns
For all switching characteristics the input pulse levels are 0.40 V to 2.4 V. Timing measurements are made at 2.0 V for
logic 1 and 0.8 V for logic 0 (reference page 11).
l>
c
<
l>
2
nm
-2
'TI
o
::D
s:
l>
::!
o
2
6-30
p's
1
TEXAS
-I/}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS27C32 32.768-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC32 32.768-BIT PROGRAMMABLE READ-ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.08 V
OUTPUT
UNDER TEST
-J
f/)
RL = 800
l'
~
n
oa:
I:L
-o
W
W
CL = 100 pF
f /)
~
FIGURE 3. OUTPUT LOAD CIRCUIT
a:
I:L
AC testing input/output wave forms
2.4
f /)
v----vr
2.0 V
:\
2.0
~
oa:
V~
0.40 V --.I\:....;;0,;.;.8;,...V;......_-\,'r-\_ _0_._8.....,:V~
..
I:L
W
A.C. testing inputs are driven at 2.4 V for logic 1 and 0.4 V for logic O. Timing measurements are made
at 2.0 V for logic 1 and 0.8 V for logic 0 for both outputs.
2
read cycle timing
AO-A11
X
I
I
I
E
G/Vpp
I
:!
VIH
ou.
a:
f
\
talA)
HI-Z
11
..I
"I
«««:
TEXAS
I
11
-H
tvIA)~
OUTPUT
VALID
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
-2w
VIL
I
I I
I I
I
f 4 - - t aIE)---.l
I
I
I
I
I
tenlG) I-
\
I..
Q1-Q8
VIL
I
I
I
I
I
I
I
I
I
I
I
«
VIH
X
ADDRESSES VALID
o
t=
VIH
tdis
~
CJ
2
VIL
«
c>
I4-i
2Zl-
HI-Z·
VOH
c.;;
c. II)
:s N
en 'i
~
"t:I
E
STANDBY SUPPLY CURRENT
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
t/)
1.50
VCC - 5.0 V
TA - 25°C
.... ~
~
1.00
V
1.25
r-......... .........
0
~ g 0.75
r-- ""--
en
1.00
-
0.75
".
~
L
:2E
o
a:
./
'/
c..
w
w
t /)
~
I
c:;
a:
0.50
0.50
-75
9
-50
o
-25
25
50
75
100
125
4.25
4.5
4.75
S!
... ~
-a]
c. N
:s
~
1.25
c..
. . . r-......
~g 0.75
1.50
E
~:s
TA - 25°C
f - MAX
1.25
(J
"'"
>-"t:I
-
............
r--
I
a:
w
SUPPLY VOLTAGE
C.
C.
-
:s
en
-
II)
...>
to)
«
II)
N
iQ
1.00
g
0.75
E
0
V
- ... V
l.L ~
2
~
o
i=
«
:!!
I
N
9
N
0.50
(J
-50
t /)
vs
1.00
0.50
-75
c..
ACTIVE SUPPLY CURRENT
.~ 0
(J
5.75
vs
:=
E
5.5
ACTIVE SUPPLY CURRENT
VCC - 5.0 V
:;
(J
5.25
:;
FREE-AIR TEMPERATURE
1.50
5.0
VCC-Supply Voltage-V
T A - Free-Air Temperature- °C
E
-o
o
-25
0
25
50
75
100
9
125
4.25
4.5
TA-Free-Air Temperature- °C
4.75
5.0
5.25
5.5
5.75
VCC-Supply Voltage-V
a:
oLL
-w
:2
ACCESS TIME
ACCESS TIME
vs
SUPPLY VOLTAGE
vs
FREE-AIR TEMPERATURE
1.50
VCC'- 5.0 V
E
~ iQ
.~
:2
1.25
~
1.00
~
g
I z 0.75
:-0.50
-75
-'
~
~
~
E
1.25
i= ;;
~ .~
iQ
1.00
~ g
0.75
II)
"".." V
~ g
I-
-50
-25
«
""'-
4.75
5.0
5.25
5.5
5.75
VCC-Supply Voltage-V
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-33
m
"'a
:u
o
s:
en
"'a
:u
o
s:
en
m
m
"'a
:u
o
s:
en
-
6-34
TMS2764
65,536-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
JULY 1983 - REVISED MARCH 1988
•
Organization ... 8192K x 8
•
Single 5-V Power Supply
•
Pin Compatible with Existing 64K EPROMs
•
All Inputs and Outputs are TTL Compatible
•
Max Access/Min Cycle Time
TMS2764-17
170 ns
TMS2764-20
200 ns
TMS2764-25
. 250 ns
TMS2764-45
450 ns
J PACKAGE
ITOPVIEW)
Vpp
VCC
A12
PGM
A7
A6
A5
t/)
:2
NC
A8
AS
A4
A11
A3
G
A2
A1
E
oa:
Q.
W
W
-o
-o
t /)
A1D
•
Low Standby Power Dissipation . . .
184 mW (Maximum)
AD
01
08
07
•
JEDEC Approved Pinout
02
03
06
05
•
21-V Power Supply Required for
Programming
•
Fast Programming Algorithm
:2
a:
Q.
t /)
:2
GND -..._ _..r- 04
..
a:
Q.
W
PIN NOMENCLATURE
AO-A 12
•
N-Channel Silicon-Gate Technology
E
•
PEP4 Version Available with 168 Hour
Burn-in and Guaranteed Operating
Temperature Range from -10°C to 85°C
(TMS2764- __ JP4)
IT
GND
NC
PGM
01-08
description
VCC
Vpp
Address Inputs
Chip Enable
Output Enable
Ground
No Connection
Program
Outputs
5-V Power Supply
21-V Power Supply
The TMS2764 is an ultraviolet-light erasable,
electrically programmable read-only memory. It
has 65,536 bits organized as 8,192 words of
8-bit length. The TMS2764 only requires a single 5-volt power supply with a tolerance of ± 5%.
The TMS2764 provides two output control lines: Output Enable {G) and Chip Enable {E). This feature allows
the G control line to eliminate bus contention in microprocessor systems. The TMS2764 has a powerdown mode that reduces maximum power dissipation from 1 50 rnA to 35 rnA when the device is placed
on standby.
This EPROM is supplied in a 28-pin, 1 5,2-mm (600-mill dual-in-line ceramic package and is designed for
operation from 0 °C to 70°C. The TMS2764 is also offered in the PEP4 version with an extended guaranteed
operating temperature range of - 10°C to 85 °C and 168 hour burn-in (TMS2764- __ JP4).
operation
The six modes of operation for the TMS2764 are listed in the following t9ble.
PRODUCTION DATA documents contain information
currant as of publication date. Products conform to
spacifications per the terms of Texas Instruments
:~~~~:~~i~a[~~I~~i ~!~~~~tigr :I~o::::~:t::s~s not
Copyright © 1983. Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-35
TMS2764
65,536·BI1 UV ERASABLE PROGRAMMABLE READ·ONL Y MEMORY
FUNCTION
(PINS)
m
Power Down
Fast
Program
Inhibit
Disable
(Standby)
Programming
Verification
Programming
ViL
xt
ViH
ViL
ViL
ViH
VIL
VIH
xt
VIH
VIL
xt
VIH
VIH
xt
VIL
VIH
xt
Vpp
(1)
Vee
Vee
Vee
Vpp
Vpp
Vpp or Vee
Vee
(28)
Vee
Vee
Vee
Vee
Vee
Vee
DOUT
HI-Z
HI-Z
DIN
DOUT
HI-Z
-a
E
:xJ
o
(20)
o
s:
(22)
-a
PGM
o
(27)
G
s:
:xJ
o
m
m
-a
MODE
Output
Read
01-08
:xJ
o
(11 to 13,
s:o
15 to 19)
read/output disable
The two control pins (E and '(3) must have low-level TTL signals in order to provide data at the outputs.
Chip enable (E) should be used for device selection. Output enable (G) should be used to gate data to the
output pins.
power down
The power-down mode reduces the maximum active current from 150 mA to 35 mAo A TTL high-level
signal applied to E selects the power-down mode. In this mode, the outputs assume a high-impedance
state, independent of G.
erasure
Before programming, the TMS2764 is erased by exposing the chip to shortwave ultraviolet light that has
a wavelength of 253.7 nanometers (2537 angstroms). The recommended minimum exposure dose (UV
intensity x exposure time) is fifteen watt-seconds per square centimeter. A typical 12 mW/cm 2 UV lamp
will erase the device in approximately 20 minutes. The lamp should be located about 2.5 centimeters (1
inch) above the chip during erasure. After erasure, all bits are at a high level. It should be noted that normal
ambient light contains the correct wavelength for erasure. Therefore, when using the TMS2764, the window
should be covered with an opaque label.
Fast programming
Note that the application of a voltage in excess of 22 V to Vpp may damage the TMS2764.
After erasure, logic Os are programmed into the desired locations: Programming consists of the following
sequence of events. With the level on Vpp equal to 21 V and E at TTL low, data to be programmed is
applied in parallel to output pins 01-08. The location to be programmed is addressed. Once data and
addresses are stable, a TTL low-level pulse is applied to PGM. Programming pulses must be applied at
each location that is to be programmed. Locations may be programmed in any order.
·6-36
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
1MS2764
65,536-BI1 UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
Programming uses two types of programming pulse: Prime and Final. The length of the Prime pulse is
1 millisecond; this pulse is applied X times. After each application, the byte being programmed is verified.
If the correct data is read, the Final programming pulse is then applied. If correct data is not read, a further
1 millisecond programming pulse is applied up to a maximum X of 15. The Final programming pulse is
4X milliseconds long. This sequence of programming pulses and byte verification is done at
Vee = 6.0 V and Vpp = 21.0 V. When the full Fast programming routine is complete, all bits are verified
with Vee = Vpp = 5 V. A flowchart of the Fast programming routine is shown in Figure 1.
en
~
oa::
c..
w
w
en
multiple device programming
Several TMS2764s can be programmed simultaneously by connecting them in parallel and following the
programming sequence previously described.
:2:
oa::
program inhibit
c..
The program inhibit is useful when programming mUltiple TMS2764s connected in parallel with different
data. Program inhibit can be implemented by applying a high-level signal to Eor PGM of the device that is not
to be programmed.
en
2
o
a::
program verify
Programmed bits may be verified with Vpp
21 V when
G
VIL,
E
c..
w
VIL and PGM
FIGURE 1. FAST PROGRAMMING FLOWCHART
-I.!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-37
TMS2764
65,536·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
logic symbol t
m
"'a
AO
0
:%3
Al
3:
-
A2
(I)
A3
"'a
:%3
A4
3:
A5
0
A6
(I)
m
m
A7
"'a
A8
0
A9
(I)
Al0
:%3
3:
All
A12
E
G
(10)
(9)
EPROM 8192x8
0
(8)
(11 )
Q1
(7)
A\l
(6)
A\l
(5)
A\l
03
(4)
o A \l
A8191 A \l
04
(25)
A\l
06
(24)
A\l
07
A\l
08
(3)
(21 )
(12)
02
05
(23)
(2)
(20)
(22)
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted):I:
Supply voltage range, Vee .............................. '" . . . . .. ....
-0.6 V to 7 V
Supply voltage range, Vpp ....................................... ; . .. - 0.6 V to 22 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , - 0.6 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , - 0.6 V to 7 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Doe to 70 0 e
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
- 65 °e to 150 °e
*Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
recommended operating conditions
Supply voltage
VCC
Vpp
Supply voltage
VIH
High-level input voltage
VIL
TA
Low-level input voltage (see Note 1)
MIN
NOM
MAX
4.75
5
5.25
Operating free-air temperature
V
V
VCC
2
-0.1
0
UNIT
VCC+l
V
0.8
70
V
°c
NOTE 1: The algebraic convention, where the more negative (less positive) limit is designated as minimum is used in this data sheet
for logic voltage levels only.
6-38
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
1MS2764
65,536-BI1 UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
electrical characteristics over full ranges of recommended operating conditions
PARAMETER
MIN
TEST CONDITIONS
MAX
UNIT
10
Output current (leakage)
= -400 p.A
10L = 2.1 rnA
VI = 0 V to 5.25 V
Vo = 0.4 V to 5.25
±10
p.A
IpP1
Vpp supply current (read)
Vpp 5.25 V
15
rnA
IpP2
Vpp supply current (program)
E and
50
rnA
ICC1
Vee supply current (standby)
Eat VIH
35
rnA
ICC2
VCC supply current (active)
E and G at VIL
150
rnA
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (load)
2.4
10H
V
V
PGM at VIL
0.45
V
±10
p.A
U)
~
o~
c..
w
w
U)
~
o~
capacitance over recommended supply voltage range and operating free-air temperature range,
f - 1 MHzt
TEST CONDITIONS
PARAMETER
Ci
Input capacitance
VI
Co
Output capacitance
Vo
MAX
TYP*
=0 V
= OV
6
9
pF
8
12
pF
switching characteristics over recommended supply voltage range and operating free-air temperature
range, CL - 100 pF, 1 Series 74 TTL load (see Note 2 and Figure 2)
TMS2764-17
MIN
talA)
Access time from address
talE)
Access time from
ten(G)
Output enable time from G
tdis(G)§
Output disable time from
G
0
tv(A)
Output data valid time after
change of address, E, or G,
0
E
MAX
TMS2764-20
MIN
MAX
TMS2764-25
MIN
MAX
TMS2764-45
MIN
MAX
170
200
250
450
ns
200
250
450
ns
150
ns
130
ns
75
60
0
60
0
100
0
0
85
0
0
o~
..
c..
w
UNIT
170
65
U)
~
UNIT
tCapacitance measurements are made on a sample basis only.
:l=Typical values are at T A = 25°C and nominal voltage.
PARAMETER
c..
ns
whichever occurs first
NOTE 2: For all switching characteristics and timing measurements, input pulse levels are 0.40 V and 2.4 V. Input and output timing
reference levels are 0.8 V and 2.0 V.
§Value calculated from 0.5 V delta to measured output level; tdis(G) is specified from G or E, whichever occurs first. Refer to read-cycle
timing diagram. This parameter is only sampled and not 100% tested.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
6-39
TMS2764
65,536-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
recommended conditions for Fast programming routine, T A = 25 °C (see Note 2 and Fast programming
cycle time diagram)
PARAMETER
m
o"
lJ
s:en
-"o
s:
lJ
en
m
m
"olJ
s:en
MIN
NOM
MAX
UNIT
Vee
vpp
Supply voltage (see Note 3)
5.75
6
6.25
V
Supply voltage (see Note 4)
20.5
21
21.5
V
tw(lPGM)
PGM initial program pulse duration (see Note 5)
0.95
1
1.05
ms
63
ms
tw(FPGM)
PGM final pulse duration (see Note 6)
tsu(A)
Address setup time
2
/,s
tsu(D)
Data setup time
2
/,s
tsu(VPP)
VPP setup time
2
/,s
tsu(vee)
Vee setup time
2
/,s
th(A)
Address hold time
0
/,s
th(D)
Data hold time
2
/,s
tsu(E)
E setup time
2
/,s
tsu(G)
G setup time
2
/,s
3.8
Fast programming characteristics, T A = 25 °C (see Note 2 and Fast programming cycle timing diagram)
PARAMETER
Output disable time from G (see Note 7)
ten(G)FP
Output enable time from G
NOTES:
6-40
TEST CONDITIONS
tdis(G)FP
eL = 100 pF
1 Series 74 TTL Load
MIN
0
TYP
MAX
130
UNIT
ns
150
2. For all switching characteristics and timing measurements, input pulse levels are 0.40 V and 2.4 V. Input and output timing
reference levels are 0.8 V and 2.0 V.
3. Vee must be applied simultaneously or before VPP and removed simultaneously or after Vpp.
4. When programming the TMS2764, connect a 0.1 /,F capacitor between VPP and GND to suppress spurious voltage transients
which may damage the device.
5. The Initial program pulse duration tolerance is 1 ms ± 5%.
6. The length of the Final pulse will vary from 3.8 ms to 63 ms depending on the number of Initial pulse applications (X).
7. This parameter is only sampled and is not 100% tested.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS2764
65,536-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.09 V
-fr
(I)
~
oa:
RL-7800
OUTPUT
UNDER TEST
c..
w
w
-
CL - 100 pF
( I)
~
oa:
c..
NOTE 8: tf S 20 ns and tr S 20 ns.
( I)
~
FIGURE 2. TYPICAL OUTPUT LOAD CIRCUIT
oa:
AC testing input/output wave forms
c..
w
2.4V~V2.0V
::
2.0VV
0.40 v_........;.--JA1C-_...;.0....;.8....;V_ _,~_ _0;.;..8.;...;;..V...:If/.\"-._ __
A.C. testing inputs are driven at 2.4 for logic 1 and 0.4 V for logic O. Timing measurements are made
at 2.0 V for logic 1 and 0.8 V for logic 0 for both inputs and outputs.
-
read cycle timing
AO-A12
x
~---VIH
X
I
\
I
I
I
i+--t a(EI---1
<;-----+----"""'1\
I
ten(GI
~ta(AI
Q1-Q8----HI-Z
I'"
!
I
V
I
V
I
~
--I -.I
~.'
vlH
VIL
t-..l.. tdis(GI
ITtY(AI V
««(q O~;~~T»}HI_Z_
OH
VOL
-1!1
TEXAS
INSTRUMENTS
POST OFFice BOX 1443 •
HOUSTON, TeXAS 77001
6-41
TMS2764
65,536·BI1 UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
fast program cycle timing
m
"'a
r.-- PROGRAM---t"~i".-VERIFY ~
:a
I
o
AO-A12
3:
rn
-o
I
.....
"'a
:a
3:
rn
Q1-AB
--1
DATA OUT VALID
j.,..tsulAI
I
I
I
I
i
I
I
I
r--thlAI ~
DATA IN STABLE j--HI-f-1
I
I
I
I
~
m
m
I
ADDRESS STABLE
i '
,..-----VIH
ADDRESS N + 1
-----VIL
DAJ4~UT2}--------
I
--1
I
VIH/VOH
. VIL/VOL
r--tsulDI
I
I
"""tdislGIFP
r-~I_______+I__~I_~r__~I~_______________ VPP
"'a
:a
o
3:
rn
VPPJ:
I
.....
-
I
I
I
I
I
I
thlDI~ ~
I--- tsu,vPp,1
I
Vee
r--~I~----~I~I--~--+--~I~----------------vee+1
Vee
--./T I
I
-..!
-~
E
I
I I
I
I
t-"tsu,vee,l I
I
I I
I
II
I
I
I
I
I
Vee
i\
I
I I
,
I '-.--!·-------!·--..I---t--..,.....---f,--------------- VIL
II I
"",....---e......I-tsu,E,
_ _ _ _~I
I
I
I
,
I
t
I
~
-+t
.....I.--..-.l
I
wIlPGMI--r--J
twlFPGMI ~
I
I
.'--I tsulGI
I
I
'.
I
r..-tenlGIFP
I
I
. i
' L J r - - - - - - - - - - - VIH
-i-!
VIL
6-42
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS27C49 65,536-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC49 65,536-BIT PROGRAMMABLE READ-ONLY MEMORY
MAY 1988
•
Organization ... 8K x 8
o
J. JT. NAND
NT PACKAGEst
Single 5-V Power Supply
(TOP VIEW)
•
Pin Compatible with Existing 8K x 8
Bipolar/High-Speed CMOS EPROMs and
PROMs
•
All Inputs/Outputs TTL Compatible
•
High Speed
Q
Max Access/Min Cycle Time
VCC ± 5%
'27C49-4
'27PC49-4
'27C49-5
'27PC49-5
VCC ± 10%
'27C49-45
'27PC49-45
'27C49-55
'27PC49-55
45
45
55
55
Low-Power CMOS Technology
o
3-State Output Buffers
o
Fast Programming ... 100 p's Pulse
•
Low Power Dissipation (VCC = 5.25 V)
- Active ... 495 mW Worst Case
Erasable
•
100% Pretestable
ns
ns
ns
ns
4
21
VCC
A8
A9
Al0
5
20
E
6
19
All
A12
08
07
06
05
04
2
23
3
22
7
18
8
17
9
16
10
15
11
14
12
13
en
:e:
o
a::
c..
-:e:
w
w
en
~
oa::
c..
en
oa::
..
FN PACKAGEt
o
o
'7U24
A7
A6
A5
A4
A3
A2
Al
AO
01
02
03
GND
c..
w
(TOP VIEW)
U·
LOCOr--UUCX)C')
c
The data outputs are three-state for connecting multiple devices to a common bus. The J, JT, N, and NT
packaged devices are pin compatible with existing 24-pin high-speed EPROMs and bipolar PROMs.
The JT and NT packages are designed for insertion in mounting-hole rows on 7,62-mm (300 mil) centers.
The J and N packages are designed for insertion in mounting-hole rows on 15,24-mm (600 mil) centers.
The TMS27PC49 PROM is also provided in an FN plastic leaded chip carrier package for surface mounting
on pads of 1,27-mm (50 mil) lead spacing.
The TMS27C49 EPROM and the TMS27PC49 PROM are guaranteed for operation from OOC to 70°C (L
suffix).
ADVANCE .INFORMATION documents contain
information on new products in the sampling or
preproduction phase of development. Characteristic
data end other spacifications ara subject to change
without notice.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
Copyright © 1988. Texas Instruments Incorporated
6-43
TMS27C49 65,536-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC49 65,536-BI1 PROGRAMMABLE READ-ONLY MEMORY
operation
There are nine modes of operation forthe TMS27C49 and TMS27PC49 listed in the following table. The read
mode requires a single 5-V supply. All inputs are TTL or CMOS levels except for Vpp, E, and PGM,
which can be high level voltages during specific modes.
m
"o
:%J
s:
-"o
s:
o
Output
Program
Program
MODE
Program
Disable
Verify Os
Verify 1s
Inhibit
X~
X
VIL(P)'
VIH(P)
VIL(P)
X
X
VPP
VPP
VIL
VIH
VIL(P)
A10/LATt
X
X
A9/PGMt
X
A8/VFyt
X
FUNCTION
:%J
A12/vSELt
o
A11/Vppt
m
m
E/PE"t
o"
Read
Blank
Blank
Check Os
Check 1s
VIL(P)
VIL(P)
VIL(P)
X
VPP
VPP
VIL(P)
VIH(P)
X
VIL(P)
VIH(P)
VIL(P)
VH§
VH
VIL
LAT
LAT
LAT
LAT
LAT
LAT
X
X
VIH(P)
VIH(P)
VIH(P)
VIL(P)
VIL(P)
VIL(P)
VH
X
VIL(P)
VIL(P)
VIH(P)
VIH(P)
VIL(P)
VIL(P)
Program
Signature
:%J
s:
o
-
X
CODE
Q1·Q8
DOUT
HI-Z
DOUT
DOUT
HI-Z
DIN
Zeros
Ones
MFGIDEV
97 I F2
tPin assignments for program mode.
~X can be VIL or VIH.
§VH = 12 V ± 0.5 V.
, (P) = Programming mode.
read/output disable
When the outputs of two or more TMS27C49s or TMS27PC49s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs
of the other devices. To read the output of the selected TMS27C49 or TMS27PC49, a low-level signal is applied
to E. All other devices in the circuit should have their outputs disabled by applying a
high-level signal to their E pins. Output data is accessed at pins 01 through 08.
latch up immunity
Latchup immunity is a minimum of 250 rnA on all inputs and outputs. This feature provides latchup immunity
beyond any potential transients at the P.C. board level when the devices are interfaced to industry-standard
TTL or MOS logic devices. The input/output layout approach controls latchup without compromising
performance or packing density.
6-44
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS27C49 65,536-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC49 65,536-BIT PROGRAMMABLE READ-ONLY MEMORY
erasure (TMS27C49-__JL and JTL EPROMs)
PROGRAMMING AND
BLANK CHECK MODE
PIN ASSIGNMENTS
Before programming, the TMS27C49 EPROMs
are erased by exposing the chip through the
transparent lid to high intensity ultraviolet light
(wavelength
2537
angstroms).
The
recommended minimum exposure dose (UV
intensity x exposure time) is 25 watt-seconds per
square centimeter. A typical 12 milliwatt-persquare-centimeter, filterless UV lamp will erase
the device in 45 minutes. The lamp should be
located about 2.5 centimeters above the chip
during erasure. It should be noted that normal
ambient light contains the correct wavelength for
erasure. Therefore, when using the TMS27C49
EPROM, the window should be covered with an
opaque label.
J, JT. N, AND
NT PACKAGES
(TOP VIEW)
oa:
A7
A6
VCC
VFY
A4/A12L
A3/A11 L
LAT
PE
c..
w
w
-
PGM
A1/A9L
AO/A8L
Q1
Q2
Q3
GND -...._ _r-
programming mode pin functions
In the programming mode, A 12 becomes VSEL,
A 11 becomes Vpp supply, E becomes PE
(program enable), A 10 becomes LAT (latch)
input, A9 becomes PGM (program) input, and AS
becomes VFY (verify) input. Latched inputs
occur on pins S through 4 (J, JT, N, and NT
packages) and on pins 9 through 5 (FN package)
as ASL through A 12L are multiplexed with AO
through A4 addresses on these pins.
en
~
oa:
o
VPP
VSEL
Q8
Q7
Q6
Q5
Q4
c..
en
~
a:
w
c..
FN PACKAGE
(TOP VIEW)
4
A4/A12L
A3/A11L
A2/A10L
A1/A9L
AO/A8L
NC
Q1
blank check mode
The TMS27C49 and the TMS27PC49 use a
differential memory cell. This means that an
unprogrammed device has ambiguous states in all
address locations. Priorto programming, the blank
check mode is used to verify that both sides of the
differential cell are erased. The blank check mode
is defined as PE to VH; VSEL and PGM
to VIL(P). In this mode, Vpp selects between
blank check Os and 1 s. VFY acts as an output
enable (see Figure 1).
3
2
5
1 282726
25
0
6
LAT
PE
23 VPP
22 VSEL
21 NC
20 Q8
19 Q7
24
7
8
9
10
11
12131415161718
NC"lClUvU'lCO
0022000
(!)
PROGRAM MODE
PIN NOMENCLATURE
programming mode
After erasure, logic 1s and Os are programmed into
the desired locations. Data is presented in parallel
(eight bits) on pins Q 1-QS. High order addresses
(ASL-A 1 2 L) are latched by pulsing LAT. Once
addresses and data are stable, PGM
is pulsed. The programming mode is achieved
when Vpp = 13.5 V, VCC = 6.0V, PGM = VIL(P),
VFY = VIH(P), PE = VIL(P) ,and VSEL = VIL(P).
TEXAS
AO-A7
Address Inputs
A8L-A12L
Latched Address Inputs
GND
Ground
LAT
Latch Input
NC
No Connection
PE
Program Enable
PGM
Program Input
01-08
Data In/Data Out
VCC
VFY
Verify Input
VPP
VSEL
Verify Select
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
en
~
HOUSTON. TEXAS 77001
5-V Power Supply
13.5-V Power Supply
6-45
TMS27C49 65,536-BIT UVERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC49 65,536-B11 PROGRAMMABLE READ-ONLY MEMORY
More than one TMS27C49 or TMS27PC49 can be programmed when the devices are connected in parallel.
Locations can be programmed in any order, but it is recommended that all locations be programmed. The
length of the programming pulse is 100 JLs; this pulse is applied X times. After each pulse the byte being
programmed is verified. If it fails verify, another programming pulse is applied up to a maximum X = 25.
If the part passes verify, the algorithm continues programming the remaining memory locations. This
sequence of programming and verification is performed at VCC = 6.0 V and Vpp = 13.5 V. When the
programming routine is complete, all bits are verified with VCC
5.0 V ± 10% (see Figure 2).
m
"tJ
:tJ
o
s:
-o
s:
(I)
program inhibit
"tJ
:tJ
Programming may be inhibited by maintaining a high-level input on the PGM or PE pins.
program verify
(I)
The TMS27C49 and TMS27PC49 use a differential memory cell for data storage. It is composed of two
FAMOS transistors. One of the FAMOS transistors in the cell must be programmed for data to be read
correctly. The condition of both FAMOS transistors in a cell being erased or both being programmed results
in an undefined condition on the outputs. The TMS27C49 and the TMS27PC49 use a two-pass verify
to ensure that a reliable data storage margin in the differential memory cell has been achieved without
the need for an overprogramming pulse. During the program verify mode, the outputs from the differential
memory cell are intentionally biased, or offset, to insure that a highly reliable program margin is achieved
during normal read mode'operation. Verify 1s skew the differential memory cell toward zeros and are used
to check for programmed 1s. Verify Os skew the differential memory cell towards 1s and are used to check
for programmed Os. Programmed bits may be verified with Vpp = 13.5 V when VFY = VIL(P), PGM = VIH(P),
and VSEL = VIL(P) (verify Os) or VSEL = VIH(P) (verify 1 s).
m
m
"tJ
:tJ
o
s:
(I)
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode
is activated when A9 is forced to VH. Two identifier bytes are accessed by AO, ie., AO = VIL accesses
the manufacturer code; AO = VIH accesses device code. Addresses A 1-A4 must be held at VIL. Each
byte possesses odd parity on bit 08. The manufacturer code for these devices is 97, and the device
code is F2.
6-46
TEXAS
"'J1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS27C49 65,536·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC49 65,536·BIT PROGRAMMABLE READ·ONLY MEMORY
en
:!:
o
a::
c..
w
w
en
-o
~
a::
c..
en
~
oa::
c..
w
FIGURE 1. BLANK CHECK FLOWCHART
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-47
TMS27C49 65,536-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC49 65,536-BI1 PROGRAMMABLE READ·ONLY MEMORY
m
"'a
:::a
o
s:en
-o
s:
"'a
:::a
en
m
m
:::a
"'a
o
..
s:en
FIGURE 2. PROGRAMMING FLOWCHART
6-48
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS27C49 65,536-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC49 65,536-BIT PROGRAMMABLE READ-ONLY MEMORY
logic symbols t
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
E
(8)
(7)
(6)
(5)
(4)
(3)
(2)
(1 )
(23)
(22)
(21)
(19)
(18)
(20)
EPROM 8192 x 8
0
A'ij
A'ij
A'ij
>A_O_
8191
A'V
A'V
A'V
A'V
A'V
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
(9)
(10)
(11 )
(13)
(14)
(15)
(16)
Q1
Q2
Q3
Q4
Q5
Q6
Q7
(17)
Q8
12,.
E
(PWR OWN)
L..t:a EN
en
PROM 8192 x 8
0
(8)
(7)
(6)
(5)
(4)
(3)
(2)
(1 )
(23)
(22)
(21)
(19)
(18)
(20)
::2E
0
a:
>A_O_
8191
A'V
A'V
A'V
A'V
A'V
A'V
A'V
A'V
c..
w
(9)
(10)
(11 )
(13)
(14)
(15)
(16)
Q1
Q2
Q3
Q4
Q5
Q6
Q7
(17)
Q8
W
en
:2:
0
a:
c..
en
~
0
a:
c..
12,
w
(PWR OWN)
L..t:a EN
2
o
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for J, JT, N, and NT packages.
i='
absolute maximum ratings over operating free-air temperature range {unless otherwise noted):S:
c
c
«
NOTE 4: T A = 25 DC ± 5 DC. Assume inputs toggling between 0 V and 3 V with timing reference made at the 10% and 90% levels.
.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-51
TMS27C49 65.536-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC49 65.536-BIT PROGRAMMABLE READ-ONLY MEMORY
recommended timing requirements for blank check
PARAMETER
MIN
NOM
MAX
UNIT
m
tsu(VH)
VH setup time
1
tsu(A)
Address setup time
1
/lS
o
twILl
th(A)
Latch pulse duration
1
/lS
Address hold time
1
/ls
tsu(ABC)
Address setup time to Blank Check
1
/lS
1
/lS
"'tJ
:D
-o
3:
en
tsu(BCVPP) Blank O/Blank 1 Select setup time
"'tJ
:D
3:
en
m
m
ten(VFY)
Output enable time from VFY
1
/lS
tdis(VFY)
Output disable time from VFY
1
/lS
blank check cycle timing
"'tJ
:D
o
3:
E
en
Jf,
I·
I---f, , tw(LI
--I ,
I I
tsu(VHI
V\:
I
tSU(AI-r,
~I""'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''---
,
l>
ADDRESSES
<
:2
0
VFY
A8L-A 12L
.....
~r"i A-O--A-7........................................tsu(ABCI
--------------------~~
ten(VFYI~ ---f
m
2
."
0
-
1
Q(1-81
- - - - - HI-Z
1
r-tdiS(VFYI
•
----+-11---
::!
-{
t----t
l>
0
t---t th(AI
I
C
I
VPP
_
rtSU(BCVPPI
........
)~
...........................................1-...................................- - '
tVH = 12.5V ± O.5V
:2
6-52
/lS
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
VIH(PI
VIl(PI
TMS27C49 65,536·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC49 65,536·BIT PROGRAMMABLE READ·ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.0V
en
-lT
~
oa:
RL= 1000
OUTPUT
UNDER TEST
el
Q.
-o
W
W
en
:E
a:
P
=30 '
0..
en
~
FIGURE 3. OUTPUT LOAD CIRCUIT
oa:
..
0..
W
read cycle timing
¥
----.
AO-A12
t"'-----
~-----------..
ADDRESS VALID
t- t a(AI--1
----.,
E
\,
t-----+-tv(AI
"
1 I
I
,,",,,-~i-----~ I
I-ten (EI-1
01-08 - - - H I - Z
~---- VIH
I
:2:
o
i=
VIL
C
--~X
= X
INTERACTIVE
MODE
+ 1
NO
YES
DEVICE FAILED
FAIL
FINAL
I
FIGURE 1. SNAPI PULSE PROGRAMMING FLOWCHART
TEXAS
-1.!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-59
TMS27C64 65,536-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC64 65,536-BI1 PROGRAMMABLE READ-ONLY MEMORY
m
"tJ
:J:J
o
s:
-o
s:
en
"tJ
:J:J
en
m
m
"tJ
:J:J
o
s:
en
-
DEVICE
FAILED
INCREMENT
ADDRESS
FIGURE 2. FAST PROGRAMMING FLOWCHART
6-60
TEXAS
-Ij}
INSTRUMENlS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS27C64 65,536-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC64 65,536-BIT PROGRAMMABLE READ-ONLY MEMORY
logic symbols t
U)
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
E
(10)
(9)
(8)
(7)
(6)
(5)
(4)
(3)
(25)
(24)
(21)
(23)
(2)
(20)
(22)~
o "
0
A-8191
A'V
A'V
A'V
A'V
A'V
A'V
A'V
A'V
~
PROM 8192 )( 8
EPROM 8192 )( 8
(11)
(12)
(13)
(15)
(16)
(17)
(18)
(19)
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
12
~WN)
E
lEN
G
(10)
(9)
(8)
(7)
(6)
(5)
(4)
(3)
(25)
(24)
(21)
(23)
(2)
(20)
(22)~
oc::
o ..
Q.
W
W
O_
A_
8191
A'V
A'V
A'V
A'V
A'V
A'V
A'V
A'V
(11)
(12)
(13)
(15)
(16)
(17)
(18)
(19)
U)
Ql
~
Q2
Q3
Q4
Q5
Q6
Q7
Q8
o
c::
Q.
U)
~
oc::
12
~WN)
Q.
EN
W
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
J and N packages illustrated.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted):S:
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.6 V to 7 V
Supply voltage range, Vpp (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 ..................... -0.6 V to 6.5 V
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6 V to 13.5 V
Output voltage range (see Note 1) .............................. " - 0.6 V to VCC + 1 V
Operating free-air temperature range ('27C64-__JL and JL4; '27PC64-__NL) ........ DoC to 70°C
Operating free-air temperature range ('27C64-__JE and JE4) ................. -40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
:l:Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only. and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect
device reliability.
NOTE 1: Under absolute maximum ratings. voltage values are with respect to GND.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-61
TMS27C64 65,536-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC64 65,536-BIT PROGRAMMABLE READ-ONLY MEMORY
recommended operating conditions
'27C64-100
m
"C
~
o
-o
s:
"C
Vee Supply voltage
~
MAX
Fast programming algorithm
5.75
6
6.25
6.25
6.50
6.75
SNAP I Pulse programming algorithm
Vpp
m
m
Vee- 0 .6
12
Fast programming algorithm
SNAPI Pulse programming algorithm
"C
~
o
s:
-
Supply voltage
(I)
5.25
Vee+ 0 . 6
12.5
13
12.75
TTL
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature (see table, page 2)
eMOS
Vee- 0 .2
-0.5
-0.5
TTL
eM OS
'27C/PC64-20
'27C/PC64-25
MIN
MAX
NOM
4.5
5
5.5
5.75
6
6.25
6.25
12.75
Vee+ 1
Vee+ 1
2
0.8
0.2
(see table, page 2)
6.5
Vee- 0 .6
12
13.25
13
2
VIH
NOTES:
'27C/PC64-15
Read mode (see Note 2)
Read mode (see Note 3)
(I)
'27C/PC64-12
'27C/PC64-1
'27C/PC64-2
'27C/PC64
MIN
NOM
5
4.75
s:
(I)
'27C/PC64-120
6.75
Vee+ 0 . 6
12.5
13
13
13.25
Vee+ 1
Vee+ 1
Vee- 0 . 2
-0.5
-0.5
0.8
0.2
(see table, page 2)
UNIT
V
V
V
V
V
V
V
V
V
V
°e
2. Vee must be applied before or at the same time as Vpp and removed after or at the same time as Vpp. The device must
not be inserted into or removed from the board when Vpp or Vee is applied.
3. Vpp can be connected to Vee directly (except in the program mode). Vee supply current in this case would be lee + Ipp.
electrical characteristics over full ranges of recommended operating conditions
PARAMETER
TEST CONDITIONS
= -2.5 rnA
10H = -20 p.A
10L = 2.1 rnA
10L = 20 p.A
VI = 0 V to 5.5 V
Vo = 0 V to Vee
Vpp = Vee = 5.5
VOH High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
IpP1
Vpp supply current
Vee supply current
(standby)
lee2 Vee supply current (active)
UNIT
V
V
Vpp
I TTL-input level
I eMOS-input level
MAX
V
Vee- 0 . 1
= 13V
Vee = 5.5 V, E = VIH
Vee = 5.5 V, E = Vee
Vee = 5.5 V, E = VIL,
tcycle = minimum cycle time,
IpP2 Vpp supply current (during program pulse)
lee1
TVPt
MIN
3.5
10H
0.4
V
0.1
V
±1
p.A
±1
p.A
1
10
p.A
35
50
rnA
250
500
p.A
100
250
p.A
15
30
rnA
outputs open
tTypical values are at T A = 25°e and nominal voltages.
capacitance over recommended supply voltage range and operating free-air temperature range,
f = 1 MHz*
PARAMETER
ei
Input capacitance
eo
Output capacitance
TEST CONDITIONS
= 0 V, f = 1 MHz
Vo = 0 V, f = 1 MHz
VI
tTypical values are at T A = 25°e and nominal voltages.
teapacitance measurements are made on sample basis only.
6-62
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
MIN
TVPt
MAX
6
10
pF
10
14
pF
UNIT
TMS27C64 65,536-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC64 65,536-BIT PROGRAMMABLE READ-ONLY MEMORY
switching characteristics over full ranges of recommended operating conditions (see Notes 4 and 5)
'27C64-100
TEST CONDITIONS
PARAMETER
(SEE NOTES 4 AND 51
MIN
MAX
'27C/PC64-120
'27C/PC64-1
'27C/PC64-12
'27C/PC64-15
MIN
MAX
MIN
UNIT
talA)
Access time from address
100
120
150
ns
talE)
Access time from chip enable
100
120
150
ns
ten(G)
Output enable time from G
50
55
75
ns
60
ns
Output disable time from G or
tdis
E,
whichever occurs first t
Output data valid time after
tv(A)
change of address,
G,
E.
CL = 100 pF,
en
MAX
~
o~
c..
w
w
-
1 Series 74 TTL Load,
0
Input tr :S 20 ns,
40
0
45
0
en
~
o
Input tf :S 20 ns
or
0
0
~
-
ns
0
c..
whichever occurs first t
en
~
TEST CONDITIONS
PARAMETER
(SEE NOTES 4 AND 51
o
'27C/PC64-2
'27C/PC64
'27C/PC64-20
'27C/PC64-25
MIN
MAX
MIN
MAX
talA)
Access time from address
200
250
ns
talE)
Access time from chip enable
200
250
ns
ten(G)
Output enable time from G
75
100
ns
60
ns
Output disable time from G or
tdis
E,
CL = 100 pF,
1 Series 74 TTL Load,
Input tr :S 20 ns,
whichever occurs first t
change of address,
G,
E,
0
60
0
Input tf :S 20 ns
Output data valid time after
tv (AI
~
c..
w
UNIT
or
0
ns
0
whichever occurs first t
tValue calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
switching characteristics for programming: Vee = 6 V and Vpp = 12.5 V (Fast) or Vee
and Vpp = 13.0 V (SNAP! Pulse), T A = 25°e (see Note 4)
PARAMETER
tdis(G)
Output disable time from G
ten(G)
Output enable time from G
MIN
0
NOM
MAX
6.50V
UNIT
130
ns
150
ns
NOTES: 4. For all switching characteristics the input pulse levels are 0.40 V to 2.4 V. Timing measurements are made at 2.0 V for
logic 1 and 0.8 V for logic O. (Reference page 10.)
5. Common test conditions apply for tdis except during programming.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-63
TMS27C64 65,536-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC64 65,536-BIT PROGRAMMABLE READ-ONLY MEMORY
recommended timing requirements for programming: Vee = 6 V and Vpp
Vee = 6.5 V and Vpp = 13.0 V (SNAPI Pulse), TA = 25°e (see Note 4)
m
"'g
lJ
o
S
-
tw(lPGM)
Initial program pulse duration
tw(FPGM)
Final pulse duration
Fast programming algorithm
V -(Fast)
MIN
NOM
MAX
UNIT
1
1.05
ms
95
100
105
p's
7S.75
ms
2.S5
en
tsu(A)
Address setup time
2
p.s
" 'g
tsu(E)
E setup
time
2
p's
tsu(G)
G setup time
2
p's
tsu(D)
Data setup time
2
p's
tsu(VPP)
VPP setup time
2
p's
tsu(vee)
Vee setup time
2
p's
th(A)
Address hold time
0
p's
th(D)
Data hold time
2
p.s
lJ
o
S
t/)
m
m
"'g
lJ
o
..
S
en
or
0.95
SNAPI Pulse programming algorithm
Fast programming only
12.5
NOTE 4: For all switching characteristics the input pulse levels are 0.40 V to 2.4 V. Timing measurements are made at 2.0 V for logic 1 and
O.S V for logic 0 (reference below) .
PARAMETER MEASUREMENT INFORMATION
2.0S V
OUTPUT
UNDER TEST
-ll'
RL=soon
CL = 100 pF
FIGURE 3. OUTPUT LOAD CIRCUIT
Ae testing input/output wave forms
2.4V-----...,.~2.0V
2'OV~
1"'------------1 -------O.S V
0.40 V - - - - - - I
0.8 V
A.C. testing inputs are driven at 2.4 V for logic 1 and 0.4 V for logic O. Timing measurements are made
at 2.0 V for logic 1 and 0.8 V for logic 0 for both outputs.
6-64
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
1MS27C64 65,536-BI1 UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
1MS27PC64 65,536-BI1 PROGRAMMABLE READ-ONLY MEMORY
read cycle timing
x:_____
~
VIH
A_D_D_RE_S_S_ES_V_A_L_ID_ _ _ _-1
AO-A 12 _ _ _ _ _ _.......
I
I
en
0
\1'--____Y
II-I
I
---1-----\ I J!
_I
l.!-.I------taIAI
««~
01-08 - - - - - - - HI-Z
program cycle timing
.,
PROGRAM
AO-A12~
DAT~
1
1
1
1
1
1
1
1
J i lI
1
.....tsuIVPPI~
-A"
1
1
1
1
1
1
1
l::!j
1
1
1
1
a:
c.
VOH
W
HI-Z-VOL
I
..I
+
1 VIH
VIL
thlAI
I
1
1
1
1
1
1
1
1
1
1
...
'-/ L
tw(lPGMI
I..
..I
twlFPGMI
I..
..I
., !
I
1
I
I
I
tsulGI
I 1
I I
I
..I tenlGl t
1
1 14
'J.
G
.... tdislGl t
I
I
I
I
thlDI~
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I.--tsUIEI--,
PGM
1
1
I1
.-tsulveel""
E~
0
1
}-HI:-Z
1
Vee
::2:
VIH/VOH
IN STABLE
'--tsuIDI ___
VPP
en
tdis
*DDRESS N
:1
1
1
1
oa----{
..f
1
ADDRESS STABLE :
'--tsuIAI--..t
o
c.
~VERIFY--1lj
1••
Q1
0
a:
i
VALID
en
::2:
VIL
tVIAI--J.---..t
OUTPUT
W
VIH
I-
I--tenlGI--I
-
VIL
~--taIEI
I
a:
c.
w
VIH
i
I
::2:
VIL
I
VIL/VOL
Vpp
Vee
Vee*
Vee
VIH
VIL
VIH
VIL
VIH
VIL
ttdislGI and tenlGI are characteristics of the device but must be accommodated by the programmer.
12.5 V VPP and 6.0 V Vee for Fast programming; 13.0 V VPP and 6.5 V Vee for SNAPI Pulse programming.
*
TEXAS
-Ii}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-65
TMS27C64 65,536·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC64 65,536·BIT PROGRAMMABLE READ·ONLY MEMORY
device symbolization
This data sheet is applicable to all TI TMS27C64 CMOS EPROMs and TMS27PC64 PROMs with the data
sheet revision code A" as shown below.
m
II
"'a
::g
o
s:
(I)
"'a
::g
o
s:en
m
m
"'a
::g
o
s:
en
DATA SHEET REVISION CODE - - - - '
FRONT END CODE
DIE REVISION CODE _ _ _ _ _ _--A
BACK END CODE _ _ _ _ _ _ _ _....J
YEAR OF MANUFACTURE _ _ _ _ _ _.--A
-
WEEK OF MANUFACTURE-----------'
6-66
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS27C64 65,536-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC64 65,536-BIT PROGRAMMABLE READ-ONLY MEMORY
TYPICAL TMS27C/PC64 CHARACTERISTICS
STANDBY SUPPLY CURRENT
1.50
~Q.'a
Q.
~
...
1.25
SUPPLY VOLTAGE
C
TA = 25°d
$
c;
"- ~
1.25
'C.'C
Q. CD
............
E
0
r---.
I'-...
~ ~ 0.75
CI)
J! =i
-
~
'a
E
1.00
0
~ ~ 0.75
~
CI)
I
~
oa:
1.50
!
~
1.00
en
vs
FREE-AIR TEMPERATURE
VCC = 5.0 V
III
J! =i
'a
STANDBY SUPPLY CURRENT
vs
/"
L
V
~
V
Q.
en
oa:
Q.
I
(j
(j
0.50
-75
9
-50
o
-25
25
50
75
100
125
en
0.50
4.25
9
-=:
W
W
4.5
4.75
5.0
5.25
5.5
5.75
VCC-Supply Voltage-V
TA-Free-Air Temperature- °C
~
oa:
Q.
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
1.50
1.25
VCC = 5.0 V
.... ~
C
1.50
CJ
1.25
!
$
"""-~
1.00
TA = 25 o
f = MAX
c1
>-
~
'C.'g
Q.
...........
r--...
W
ACTIVE SUPPLY CURRENT
vs
ACTIVE SUPPLY CURRENT
vs
:::J
CI)
-
100..
0.75
CD
N
'i
~
1.00
E
""'~
> 0
U ~ 0.75
.~
ct
~
I---
V"
I
0.50
-75
N
-50 -25
o
CJ
25
50
75
100
125
9
0.50
4.25
4.5
TA-Free-Air Temperature- °C
ACCESS TIME
~
j::
1.25
= 'iii.~
III
U
:i
FREE-AIR TEMPERATURE
E
0
~
1.00
~ ~ 0.75
-'~
/
5.25
5.5
5.75
1.50
VCC' = 5.0·V
'C
5.0
ACCESS TIME
vs
SUPPLY VOLTAGE
vs
1.50
4.75
VCC-Supply Voltage-V
",-
TA = 25°C
~
1.25
1.00
"",
.......
.............. .......
0.75
I-
0.50
-75
-50 -25
0
25
50
75
100
0.50
4.25
125
TA-Free-Air Temperature- °C
4.5
4.75
5.0
5.25
5.5
5.75
VCC-Supply Voltage-V
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-67
m
"'C
lJ
o
3:
en
"'C
lJ
o
3:
en
m
m
"'C
lJ
o
3:
en
-
6-68
TMS28C64
65,536·BIT ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
JUNE 1988
o
Organization 8K x 8
NAND J PACKAGES
(TOP VIEW)
o
Single 5-V Power Supply (± 10%)
o
Compatible with Existing 64K MOS
EPROMs, PROMs, ROMs, and EEPROMs
o
JEDEC Standard Pinout
•
All Inputs/Outputs TTL Compatible
o
Max Access/Min Cycle Times
o
o
TMS28C64-25
250 ns
TMS28C64-35
350 ns
RIB
A12
A7
A6
A5
A4
A3
A2
A1
AO
DQO
DQ1
DQ2
2-p. CMOS Silicon Gate Technology
Single Byte and Page (32 Bytes) Write:
- Latched Address and Data
-Self-Timed Programming
Operation (10 ms Typical)
-Data Polling and Ready/Busy Verifications
c..
w
w
en
-o
~
o
DQ7
DQ6
DQ5
DQ4
a:
c..
en
~
a:
c..
w
PIN NOMENCLATURE
Addresses
AO-A12
-Byte Mode (250 ns Typical Access Time)
-Word Mode (350 ns Typical Access Time)
o
oa:
VSS_--...._ _....--DQ3
o Fast Read Mode Operation:
o
o
o
en
~
E
Chip Enable
G
Output Enable
10,000 Cycles Endurance
IN
Write Enable
Inadvertent Write Protection
DOO-DQ7
Inputs/Outputs
RiB
Ready/Busy Output
VCC
5-V Power Supply
VSS
NC
Ground
Low Power Dissipation:
-Active ... 110 mW Worst Case
-Standby ... 17 mW Worst Case
2
o
i=
c
C
6-73
TMS28C64
65,536·BIT ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.08 V
m
"'0
::D
o
3:
en
-o
OUTPUT
UNDER TEST
"'0
::D
3:
en
"'0
CL = 100 pF
FIGURE 1. OUTPUT LOAD CIRCUIT
m
m
::D
-Jr
RL= 800n
AC testing input/output wave forms
o
3:
0.40
<
l>
read cycle (byte mode)
2
."
o~
3:
l>
2
TMS28C64-35
TMS28C64-25
PARAMETER
2
om
::t
o
v------..I~,.._-0-.8......V--------0-.8-V~=f\\.._ _ _ _ _ __
A.C. testing inputs are driven at 2.4 V for logic 1 and 0.4 V for logic O. Timing measurements are made
at 2.0 V for logic 1 and 0.8 V for both inputs and outputs.
l>
c
20V~
2.4 V - - - - - " ' ! 2 . 0 V
en
MIN
NOM
MAX
MIN
NOM
MAX
350
250
UNIT
ns
tc(RD)
Read cycle time
talE)
Chip enable access time
250
350
ns
talA)
ta(G)
Address access time
250
350
ns
Output enable access time
100
150
ns
tlz
Chip enable to output enable
thz
Chip disable to output disable
tolz
tohz
Output disable time from
toh1
toh2
50
100
75
ns
125
ns
Output enable time from G
50
75
ns
G
100
125
ns
Output hold from AO-A 12 address change
20
20
ns
Output hold from AO address change
20
20
ns
NOTE 2: For all switching characteristics the input pulse levels are 0.40 V to 2.4 V. Timing measurements are made at 2.0 V for logic 1
and 0.8 V for logic 0 (reference above).
6-74
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS28C64
65,536-BIT ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
read cycle (word mode)
TMS28C64-25
PARAMETER
MIN
NOM
TMS28C64-35
MAX
MIN
NOM
MAX
UNIT
tc(RD)
Read cycle time 1st byte
250
350
ns
t c 2(RD)
Read cycle time 2nd byte
100
130
ns
talE)
Chip enable access time
250
350
ns
talA)
Address access time 1st byte
250
350
ns
t a 2(A)
AO access time 2nd byte
100
130
ns
150
ns
ta(G)
Output enable access time
tlz
Chip enable to output enable
50
75
100
U)
~
oa:
a..
w
w
U)
~
ns
thz
Chip disable to output disable
100
125
ns
tolz
Output enable time from G
50
75
ns
tohz
Output disable time from G
100
125
ns
toh1
Output hold from AO-A 12 address change
20
20
ns
toh2
Output hold from AO address change
20
20
ns
toh3
Output hold from A 1 -A 1 2 address change
50
50
ns
oa:
a..
U)
~
oa:
byte and word read mode (AO change hold time)
tc(RDI---~~1
I.
~====>
C
I
¢_ _
."
:xJ
o
I ~tc(RD)-----+I
I
~
A1A"~
(I)
."
:xJ
o
~
E~"'EI
m
G----"":"1""
-
I
---..J
(I)
m
."
:xJ
..
I
I
'I
I
1 ,Ie
I"""
I I ----~I---------:-I
I
I/i1
I ~F-I--":'1--:"'1
VIH
o
I+-ta(G)---..!
I
I
----
W--~~--~~-+I--~~------~--~----~----~I--~I
~
(I)
l>
C
DATA
HIGH
Z
OUT
,
I+---- ta2(A)------+I
byte write cycle
~
2
TMS28C64-25
PARAMETER
MIN
tc(WR)
Write cycle time
tas
Address setup time
tah
Address hold time
tcs
tch
o
tcw
Chip enable to end of write input
toes
Output enable setup time
10
s:
l>
toeh
Output enable hold time
10
twpt
Write pulse duration
tdl
Data latch time
:::!
tdv
Data valid time
tds
Data setup time
2
tdh
Data hold time
tdrb
Ready/Busy delay time
n
m
-2
."
::D
o
TMS28C64-35
NOM
MAX
10
15
MIN
NOM
MAX
10
15
UNIT
ms
10
15
ns
100
100
ns
Write setup time
0
0
ns
Write hold time
0
0
150
150
500
150
ns
500
ns
ns
15
500
20
150
ns
500
30
ns
ns
ns
100
130
ns
30
30
ns
400
tliJ
400
ns
is noise protected. Glitches will not activate a write cycle.
NOTE 2: For all switching characteristics the input pulse levels are 0.40 V to 2.4 V. Timing measurements are made at 2.0 V for logic 1
and 0.8 V for logic 0 (reference page 6).
6-76
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, rEXAS 77001
TMS28C64
65,536-BIT ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
E controlled
byte write cycle
en
~
oa:
a..
w
w
en
~
o
a:
a..
en
~
I
DATA OUT
I
~tdv
~I
DATAIN~'fO-_D_AT_A_VA_lID.........;.
_
~
~==-=
~
___
.1.
I I+-- tds
I
HIGH-Z
I
r
tdh--+l
I \
t+"tdrb-+j
oa:
..
a..
w
2
o
i=
tasfftah~
C
<
l>
I
I
II
:2
I
I
I /+-tdS-+/
---~~
ADDRESS
(A4-AO)
("")
m
2
o
"
::IJ
---
==x=>----
DATA
BYTE 31
I
I+-------------tplw------------~·I
s:l>
I
I
t+----------------tc(WR)---------------fIol'l
::!
o
tdrb1+--+1
:2
6·78
yI
I
R/B---"""
~~I_________________________________
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS27C128 131,072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC128131,072·BIT PROGRAMMABLE READ·ONLY MEMORY
'\!i~
'Jl~
'~'
"i-----------------------------------------OCTOBER 1984 - REVISED MAY 1988
J AND N PACKAGES
This Data Sheet is Applicable to All
TMS2 7C 128s and TMS27PC 128s Symbolized
with Code "A" as Described on Page 11.
o
o
o
o
o
ITOPVIEWI
A12 2
A7 3
A6 4
A5 r- 5
A4 6
A3 -7
A2 =8
A1 9
AO 10
01 11
02 12
03 13
Organization ... 16K x 8
Single 5·V Power Supply
Pin Compatible with Existing 128K MOS
ROMs, PROMs, and EPROMs
All Inputs/Outputs Fully TTL Compatible
Max Access/Min Cycle Times
VCC ±5%
'27C128·100
'27C128·120
'27C/PC128·1
'27C/PC128-2
'27C/PC128
VCC ±10%
'27C128-12
'27C/PC128·15
'27C/PC128·20
'27C/PC128-25
100 ns
120ns
150 ns
200ns
250ns
GND
rn
~
oa:
Q.
W
W
rn
~
oa:
Q.
rn
~
oa:
Q.
-
FM PACKAGE
W
(TOP VIEW)
o Power Saving CMOS Technology
o
Very High-Speed SNAP! Pulse Programming
or Fast Programming Algorithms
o
o
3-State Output Buffers
/
A6
A5
A4
A3
A2
A1
AO
400 mV Guaranteed DC Noise Immunity with
Standard TTL Loads
o
Latchup Immunity of 250 mA on All Input and
Output Lines
o
Low Power Dissipation (VCC = 5.25 V)
- Active ... 158 mW Worst Case
- Standby ... 1.4 mW Worst Case
(CMOS Input Levels)
o
1 U28 VCC
27 F PGM
26 ~ A13
25 A8
241- A9
23 A11
221- G
21 A10
20 E
19 08
18 07
17 06
16 05
14 15tJ 04
Vpp
NC
01
4 3 2 1 3231 30
0
291
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
NC"'l
2
o
i=
A8
A9
A11
c
o 128K EPROM Available with MIL·STD-883C
Class B High Reliability Processing
(SMJ27C128)
PIN NOMENCLATURE
--~X=X+1
NO
YES
DEVICE FAILED
FAIL
FINAL
I
FIGURE 1. SNAPI PULSE PROGRAMMING FLOWCHART
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-83
TMS27C128 131 ,072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC128131,072·BIT PROGRAMMABLE READ·ONLY MEMORY
m
"'U
::u
o
3:
til
-o
"'U
::u
3:
til
m
m
"'U
::u
o
3:
til
..
DEVICE
FAILED
INCREMENT
ADDRESS
FIGURE 2. FAST PROGRAMMING FLOWCHART
6-84
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS27C128 131 ,072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC128131,072·BIT PROGRAMMABLE READ·ONLY MEMORY
logic symbols t
EPROM 16,384 x 8
0-
(10)
AO
(9)
A1
(8)
A2
(7)
A3
(6)
A4
(5)
A5
(4)
A6
(3)
A7
(25)
A8
(24)
A9
(21)
A10
(23)
A11
(2)
A12
(26)
A13
(20)
E
(22)
A'V
A'V
A'V
>A
0
A'V
16,383 A'V
A'V
A'V
A'V
(11 )
(12)
(13)
01
02
03
(15)
04
(16)
05
(17)
06
(18)
07
(19)
08
13 ...
k
,......
PROM 16,384 x 8
0-
(10)
AO
MEN
(9)
A1
(8)
A2
(7)
A3
(6)
A4
(5)
A5
(4)
A6
(3)
A7
(25)
A8
(24)
A9
(21)
A10
(23)
A11
(2)
A12
(26)
A13
(20)_
E
[PWR OWN)
G
(22)
tn
~
0
A'V
A'V
A'V
>A
0
A'V
16,383
A'V
A'V
A'V
A'V
(11 )
(12)
(13)
a::
c..
W
02
03
(15)
04
(16)
05
(17)
06
(18)
07
(19)
08
.......
tn
~
0
a::
c..
w
fFNI
absolute maximum ratings over operating free-air temperature range (unless otherwise noted):I:
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 7 V
Supply voltage range, Vpp (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 .......................... - 0.6 V to 6.5 V
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6 Vto 13.5 V
Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to Vce + 1 V
Operating free-air temperature range ('27C128-__ JL and JL4; '27PC128-__ NL
and FML) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 °e to 70°C
Operating free-air temperature range (,27C 128-__ JE and JE4) . . . . . . . . . . . . . . . . . . - 40°C to 85 °C
Storage temperature range ........................ ~ . . . . . . . . . . . . . . . . . . - 65°C to 150 °C
~ Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device atthese or any other conditions beyond those indicated in the "Recommended Operating Conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE1: Under absolute maximum ratings, voltage values are with respect to GND.
TEXAS
~
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
0
-
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12.
Pin numbers shown are J and N packages.
INSTRUMENTS
tn
~
a::
c..
13 ...
b
w
01
6-85
TMS27C128 131,072-BI1 UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131,072-BI1 PROGRAMMABLE READ-ONLY MEMORY
recommended operating conditions
'27C128-100
m
'27C128-120
'27C128-12
"1:J
'27C/PC128-1
'27C/PC128-15
;0
o
'27C/PC128-2
'27C/PC128-20
3:
en
-
4.75
Vee
;0
o
3:
en
Supply Voltage Fast programming algorithm
5
5.25
5
5.5
V
5.75
6
6.25
5.75
6
6.25
SNAPI Pulse programming algorithm
V
6.25
6.5
6.75
6.25
6.5
6.75
-
VPP
;0
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature (See table, page 2)
Read mode (see Note 3)
V
m
SNAPI Pulse programming algorithm
"1:J
o
3:
en
-
Vee+ 0 . 6
13
12.5
Vee- 0 . 6
12
Supply voltage Fast programming algorithm
m
NOM
TTL
12.75
2
13
Vee- 0 . 2
-0.5
CMOS
TTL
MAX
Vee+ 0 .6
12.5
13
Vee- 0 .6
12
12.75
2
Vee+ 1
O.B
Vee- 0 . 2
-0.5
0.2
(See table, page 2)
V
V
13.25
V
Vee+ 1
V
Vee+ 1
O.B
V
13
13.25
Vee+ 1
-0.5
CMOS
NOM
MAX
MIN
4.5
MIN
Read mode (see Note 2)
"1:J
UNIT
'27C/PC128-25
'27C/PC128
-0.5
0.2
V
V
De
(See table, page 2)
NOTES: 2. Vee must be applied before or at the same time as VPP and removed after or at the same time as Vpp. The device must
not be inserted into or removed from the board when VpporVee is applied.
3. Vppcan be connected to Vee directly (except in the program mode). Vee supply current inthis case would be lee + Ipp.
electrical characteristics over full ranges of recommended operating conditions
PARAMETER
TEST CONDITIONS
10
Output current (leakage)
= -2.5mA
IOH = -20p.A
IOL = 2.1 mA
10L = 20p.A
VI = OVt05.5V
Vo = OVtoVee
IpP1
Vpp supply current
Vpp
IOH
VOH High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
lee1
(standby)
I TTL-input level
I CMOS-input level
lee2 Vee supply current (active)
MAX
3.5
UNIT
V
Vee- 0 . 1
V
0.4
= Vee = 5.5V
1
= 13V
= 5.5 V, E = VIH
Vee = 5.5 V, E = Vee
Vee = 5.5 V, E = VIL.
tcycl e = minimum cycle time.
IpP2 Vpp supply current (during program pulse)
Vee supply current
MIN Typt
V
0.1
V
±1
p.A
±1
p.A
10
mA
Vpp
35
50
mA
Vee
250
500
p.A
100
250
p.A
15
30
mA
outputs open
tTypical values are at T A = 25 De and nominal voltages.
capacitance over recommended supply voltage range and operating free-air temperature range,
f = 1 MHzt
PARAMETER
ei
Input capacitance
Co
Output capacitance
TEST CONDITIONS
= OV, f = 1 MHz
Vo = OV, f = 1 MHz
VI
tTypical values are at T A = 25 De and nominal voltages.
:l:eapacitance measurements are made on sample basis only.
6-86
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
MIN
Typt
MAX
6
10
pF
10
14
pF
UNIT
TMS27C128 131,072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC128 131,072·BIT PROGRAMMABLE READ·ONLY MEMORY
switching characteristics over full ranges of recommended operating conditions (see Notes 4 and 5)
TEST CONDITIONS
PARAMETER
'27C128-100
'27C128-12
MIN
talA)
Access time from address
talE)
Access time from chip enable
ten(G)
Output enable time from G
tdis
Output disable time from G or E, whichever occurs
first t
tv(A)
Output data valid time after change of address,
G,
'27C128-120
(SEE NOTES 4 AND 5)
MAX
MIN
UNIT
U)
MAX
100
120
ns
CL = 100 pf,
100
120
ns
1 Series 74 TTL Load,
50
55
ns
45
ns
Input tr :5 20 ns,
0
Input tf :5 20 ns
40
0
:2:
o
a:
c.
w
w
U)
~
E, or
0
whichever occurs first t
0
o
a:
ns
c.
TEST CONDITIONS
PARAMETER
(SEE NOTES 4 AND 5)
'27C/PC128-1
'27C/PC128-2
'27C/PC128-15
'27C/PC128-20 '27C/PC128-25
MIN
MAX
MIN
'27C/PC128
MAX
MIN
U)
MAX
talA)
Access time from address
150
200
250
ns
talE)
Access time from chip enable
150
200
250
ns
ten(G)
Output enable time from G
CL = 100 pf,
75
75
100
ns
Output disable time from G
1 Series 74 TTL Load,
tdis
or E, whichever occurs first t
Input tr :5 20 ns,
60
ns
Output data valid time after
Input tf :5 20 ns
tv (A)
change of address,
0
E, or G,
60
0
0
60
0
0
:?1
oa:
c.
UNIT
..
w
ns
0
whichever occurs first t
tValue calculated from 0.5 V delta to measured output level. This parameter is only sampled and not 100% tested.
switching characteristics for programming: Vee = 6 V and Vpp = 12.5 (Fast) or Vee
and Vpp = 13.0 V (SNAP! Pulse), T A = 25°e (see Note 4)
PARAMETER
tdis(G)
Output disable time from G
ten(G)
Output enable time from G
MIN
recommended timing requirements for programming: Vee = 6 V and Vpp
Vee = 6.50 V and Vpp = 13.0 V (SNAP! Pulse), TA = 25°e, (see Note 4)
twIlPGM)
Initial program pulse duration
tw(FPGM)
Final pulse duration
NOM
0
Fast programming algorithm
SNAPI Pulse programming algorithm
Fast programming only
6.50 V
MAX
UNIT
130
ns
150
ns
12.5 V (Fast) or
MIN
TVP
MAX
UNIT
0.95
1
1.05
ms
95
100
105
pS
78.75
ms
2.85
tsu(A)
Address setup time
2
pS
tsu(E)
E setup time
2
pS
tsu(G)
G setup time
2
/lS
tsu(D)
Data setup time
2
pS
tsu(VPP)
VPP setup time
2
pS
tsu(VCC)
VCC setup time
2
ps
th(A)
Address hold time
0
ps
thIDI
Data hold time
2
pS
NOTES:
4. For all switching characteristics the input pulse levels are 0.40 V to 2.4 V. Timing measurements are made at 2.0 V for logic 1
and 0.8 V for logic O. (Reference page 10).
5. Common test conditions apply for tdis except during programming.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-87
TMS27C128 131,072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC128 131,072·BIT PROGRAMMABLE READ·ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.08 V
m
."
:u
o
:s:
-o
:s:
-
OUTPUT
UNDER TEST
(I)
."
:u
-J1
RL = 800n
CL
= 100
pF
(I)
FIGURE 3. OUTPUT LOAD CIRCUIT
m
m
."
AC testing input/output wave forms
:u
o
:s:
2.4 V
----.....,.~20 V
20
vV
(I)
0.40 V _ _ _ _--It\F_.;;.;0..;;.8..;.V_ _ _ _ _ _..;.0.;.;;,8..;.V""iIJf\""'"- - - - - -
A.C. testing inputs are driven at 2.4 V for logic 1 and 0.4 V for logic O. Timing measurements are made at
2.0 V for logic 1 and 0.8 V for logic 0 for both inputs and outputs.
read cycle timing
AO·A13
>t
~
ADDRESSES VALID
I
I
G
I
I
I
I
'01·08
6-88
HI·Z
VIL
I
I
I
I
VIH
\
-I
\ . . - - talE)
\
\
I
j4
ten(G)
~
-\
talA)
(E<<<
l!:
1:
VIL
I I
I
I
VIH
-I
I \-
tV(A)+---i
OUTPUT
VALID
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
VIH
HOUSTON. TEXAS 77001
VIL
tdis
I
»}
VOH
HI·Z-VOL
TMS27C128 131,072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC128 131,072·BI1 PROGRAMMABLE READ·ONLY MEMORY
program cycle timing
PROGRAM~VERIFY-----1
en
:iE
oa:
c..
w
w
-o
en
:iE
Vpp
Vee
~I-',"'VPPI~
en
I
Vee*
~ tsulveel--j
~
\.-tsulEl----l
V
Vee
thlDl
VIH
I-
-I
'wIFPGMI I.
-I
tw(lPGM)
-:l!!
Vee
I
~
a:
c..
Vpp
k'"'GI
I
I
' I....,..._--e't--I
,I-
oa:
..
c..
w
VIL
I
'{r------I
tenlG) t
I
VIH
VIL
ttdiS(G) and ten(Gl are characteristics of the device but must be accommodated by the programmer.
t 12.5 V Vpp and
6.0 V Vee for Fast programming 13.0 V Vpp and 6.50 V Vee for SNAPI Pulse programming.
device symbolization
This data sheet is applicable to all TI TMS27C128 CMOS EPROMs and TMS27PC128 PROMs with the code
A" as shown below:
II
0
TMS
27C128
TI
FML
TMS27PC128
.ALXPYYWW
-Ij}
lLXPyr-'ti'(i
DATA SHEET REVISI ON CODE
FRONT END CODE
DIE REVISION CODE
BACK END CODE
YEAR OF MANUFACTURE
WEEK OF MANUFACTURE
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
I
6-89
\
\
TMS27C128 524,288·BI1 UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC128 131,072·BI1 PROGRAMMABLE READ·ONLY MEMORY
TYPICAL TMS27C/PC128 CHARACTERISTICS
m
STANDBY SUPPLY CURRENT
vs
."
:JJ
STANDBY SUPPLY CURRENT
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
o
:s:
1.50
c
-o
:s:
-
f
$
en
(.)
."
?:D.'C
:JJ
D.
E
VCC - 5.0 V
.............
1.25
~
Q)
:i 1.00
~ E
Jl
en
m
m
'C
,
.......... ..........
0
~ ~ 0.75
25 °C
-
Jl
-
~
'C
:i 1.00
E
0
~ ~ 0.75
".
en
/
V
./
V
/'
I
c:;
0.50
-75
9
o
_1
1.25
i5..:C
D. Q)
I
:JJ
TA
c;
en
."
1.50
Q)
:::::I
-50
-25
:s:
o
c:;
25
50
TA - Free-Air Temperature -
75
100
0.50
4.25
9
125
4.5
4.75
°c
5.0
5.25
5.5
5.75
VCC-Supply Voltage-V
en
1.50
ACTIVE SUPPLY CURRENT
vs
ACTIVE SUPPLY CURRENT
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
VB
.... ......
1.25
1.50
c
VCC - 5.0 V
TA - 25°C
1.25 f - MAX
f
:;
......
(.)
~ ..........
1.00
..........
r--..
0.75
-a]'
D.
-
:::I
N
::
Q)
E
en
-
.~
10
~
1.00
V"
.. V
~
~~
0.75
"""."",. ~
I
0.50
-75
N
(.)
-50 -25
o
25
50
75
100
9
125
0.50
4.25
4.5 4.75
TA-Free-Air Temperature- °c
ACCESS TIME
FREE-AIR TEMPERATURE
1.25
..,." ~
j:::C
:!!
:l 'i
~
U
E
1.00
~ 0
~ ~ 0.75
5.75
-"
"".
~
TA - 25°C
V
Q)
E
j:::C
= "iii.~
Q)
V"
E
~ 0
U
IZ
~-
....
0.50
-75
-50 -25
0
25
50
75
100
1.25
1.00
0.50
4.25
125
......
~ '"""--
-
0.75
TA - Free-Air Temperature- °c
6-90
5.5
1.50
VCC - 5.0'V
~
5.25
ACCESS TIME
vs
SUPPLY VOLTAGE
vs
1.50
5.0
VCC-Supply Voltage-V
4.5
4.75
5.0
5.25
5.5
VCC-Supply Voltage-V
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
5.75
TMS27C256 262,144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256 262,144·BIT PROGRAMMABLE READ·ONLY MEMORY
This Data Sheet is Applicable to All
TMS27C256s and TMS27PC256s Symbolized
with Code "A" as Described on Page 12.
•
Organization ... 32K x 8
•
Single 5· V Power Supply
•
Pin Compatible with Existing 256K MOS
ROMs, PROMS, and EPROMs
•
All Inputs/Outputs Fully TTL Compatible
•
Max AccesslMin Cycle Times
o
o
o
o
VCC ±5%
VCC ±10%
'27C256·120
'27C/PC256-150
'27C/PC256-1
'27C/PC256-2
'27C/PC256
'27C256-12
'27C/PC256-15
'27C/PC256-17
'27C/PC256-20
'27C/PC256-25
120
150
170
200
250
Power Saving CMOS Technology
Very High Speed SNAP! Pulse Programming
or Fast Programming Algorithms
3-State Output Buffers
N a..
U'lt M
,... .... 0..:::> U ........
Latchup Immunity of 250 rnA on All Input
and Output Lines
•
Low Power Dissipation (VCC = 5.25 V)
- Active ... 158 mW Worst Case
- Standby ... 1.4 mW Worst Case
(CMOS-Input Levels)
•
«>2>«
400 mV Guaranteed DC Noise Immunity
with Standard TTL Loads
•
o
ns
ns
ns
ns
ns
/
A6
A5
A4
A3
A2
A1
PEP4 Version Available with 168 Hour Burnin, and also Guaranteed Operating
Temperature Ranges
4 3
1 323130 ,I
0
10
29 1 A8
281 A9
27 A11
26 NC
25 G
24 A10
E
AO 11
23
NC 12
01 13
22 08
21 07
~~~J2.~~~
NMC:::>'ltIt)CO
dd22ddd
(!)
256K EPROM Available with MIL-STD-883C
Class B High Reliability Processing
(SMJ27C256)
description
PIN NOMENCLATURE
The TMS27C256 series are 262,144-bit,
ultraviolet-light
erasable,
electrically
programmable read-only memories.
AO-A 14 Address Inputs
Chip Enable/Power Down
E
The TMS27PC256 series are 262, 144-bit, onetime, electrically programmable read-only
memories.
These devices are fabricated using power saving
CMOS technology for high speed and simple
interface with MOS and bipolar circuits. All
inputs (including program data inputs) can
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~a{~~1~1e ~!~~~~ti~r ~;o::~:~:t:~~s not
2
5
6
7
8
9
TEXAS
G
Output Enable
GND
Ground
NC
NU
01-08
No Connection
Make No External Connecction
Outputs
VCC
Vpp
5-V Power Supply
12-13 V Programming Power Supply
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Copyright © 1984, Texas Instruments Incorporated
6-91
TMS27C256, 262,144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256 262,144·BIT PROGRAMMABLE READ·ONLY MEMORY
be driven by Series 74 TTL circuits without the use of external pull-up resistors. Each output can drive
one Series 74 TTL circuit without external resistors.
.
The data outputs are three-state for connecting multiple devices to a common bus. The TMS27C256 and
the TMS27PC256 are pin compatible with 28-pin 256K MaS ROMs, PROMs, and EPROMs .
m
."
:u
o
The TMS27C256 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C256 is offered with two guaranteed
temperature ranges of DOC to 70°C and -40°C to 85°C (TMS27C256-__JL and TMS27C256-__JE,
respectively). The TMS27C256 is also offered with 168-hour burn-in on both temperature ranges
(TMS27C256-__JL4 and TMS27C256-__JE4, respectively); see table below.
s:
-o
til
."
:u
s:
m
m
The TMS27PC256 PROM is offered in a dual-in-line plastic package (N suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27PC256 is also supplied in a 32-lead plastic
leaded chip carrier package using 1,25-mm (50-mil)· lead spacirig (FM suffix). The TMS27PC256 is
guaranteed for operation from DoC to 70°C (NL or FML suffix) .
o
:u
All package styles conform to JEDEC standards.
til
."
s:
til
EPROM
SUFFIX FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN-IN
oDe to
TMS27C256-XXX
70 D
e
JL
SUFFIX FOR PEP4
168 ± 8 HR. BURN-IN
VS TEMPERATURE RANGES
e TO 85 De
1-40 D
I
oDe TO
JE
70 De
JL4
e TO 85 De
1-40 D
I
JE4
These EPROMs and PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use
in microprocessor-based systems. One other 12-13 V supply is needed for programming. All programming
signals are TTL level. These devices are programmable by either Fast or SNAPI Pulse programming
algorithms. Fast programming uses a Vpp of 12.5 V and a VCC of 6.0 V for a nominal programming time
of two minutes. SNAP! Pulse programming uses a Vpp of 13.0 V and a VCC of 6.5 V for a nominal
programming time of four seconds. For programming outside the system, existing EPROM programmers
can be used. Locations may be programmed singly, in blocks, or at random.
operation
There are seven modes of operation listed in the following table. Read mode requires a single 5 V supply.
All inputs are TTL level except for Vpp during programming (12.5 V for Fast, or 13.0 V for SNAPI Pulse)
and 12 V on A9 for signature mode.
6-92
TEXAS
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INSTRUMENlS
POST OFFICE BOX 1443 •
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TMS27C256 262.144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256 262.144·BIT PROGRAMMABLE READ·ONLY MEMORY
MODE
FUNCTION
Read
Output
Disable
Standby
Programming
Verify
Program
Signature
Inhibit
Mode
en
E
VIL
VIL
VIH
VIL
VIH
VIH
VIL
G
VIL
VIH
xt
VIH
VIL
X
VIL
Vee
Vee
:2!
oa:
c..
w
w
-
Vpp
Vee
Vee
Vee
Vpp
Vpp
Vpp
Vee
Vee
Vee
Vee
Vee
Vee
Vee
A9
X
X
X
X
X
X
VHt
VHt
AO
X
X
X
X
X
X
VIL
VIH
DOUT
HI-Z
HI-Z
Dour
HI-Z
MFG
DEVICE
97
04
en
~
oa:
c..
en
CODE
01-08
DIN
tx can be VIL or VIH.
tVH = 12 V ± 0.5 V.
:2!
o
..
a:
c..
w
read/output disable
When the outputs of two or more TMS27C256s or TMS27PC256s are connected in parallel on the same
bus, the output of any particular device in the circuit can be read with no interference from the competing
outputs of the other devices. To read the output of a single device, a low-level signal is applied to the
E and G pins. All other devices in the circuit should have their outputs disabled by applying
a high-level signal to one of these pins. Output data is accessed at pins 1 to 08.
a
latchup immunity
Latchup immunity on the TMS27C256 and TMS27PC256 is a minimum of 250 mA on all inputs and outputs.
This feature provides latch up immunity beyond any potential transients at the P.C. board level when the
EPROM is interfaced to industry standard TTL or MOS logic devices. Inputloutput layout approach controls
latchup without compromising performance or packing density.
For more information see application report SMLA001; "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family. "
power down
Active ICC current can be reduced from 30 rnA to 500 p.A (TTL-level inputs) or 250 p.A (CMOS-level inputs)
by applying a high TTL signal to the E pin. In this mode all outputs are in the high-impedance state.
erasure (TMS27C256)
Before programming, the TMS27C256 EPROM is erased by exposing the chip through the transparent
lid to high intensity ultraviolet light (wavelength 2537 angstroms). The recommended minimum exposure
dose (UV intensity x exposure time) is 15 watt-seconds per square centimeter. A typical 12-milliwattper-square-centimeter, filterless UV lamp will erase the device in 21 minutes. The lamp should be located
about 2.5 centimeters above the chip during erasure. It should be noted that normal ambient light contains
the correct wavelength for erasure. Therefore, when using the TMS27C256, the window should be covered
with an opaque label. After erasure (all bits in logic 1 state), logic Os are programmed into the desired
locations. A programmed zero can be erased only by ultraviolet light.
TEXAS
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INSTRUMENTS
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6-93
TMS27C256 262,144·BIT UV ERASABLE PROGRAMMABLE READ·ONL Y MEMORY
TMS27PC256 262,144·BIT PROGRAMMABLE READ·ONLY MEMORY
initializing (TMS27PC256)
The one-time programmable TMS27pe256 PROM is provided with all bits in logic 1 state, then logic Os
are programmed into the desired locations. Logic Os programmed into a PROM cannot be erased.
m
\J
SNAPI Pulse programming
:JJ
o
The 256K EPROM and PROM can be programmed using the TI SNAP! Pulse programming algorithm as
illustrated by the flowchart of Figure 1, which can reduce programming time to a nominal of 4 seconds.
Actual programming time will vary as a function of the programmer used.
~
en
\J
:JJ
E is
o
Data is presented in parallel (eight bits) on pins 01 to 08. Once addresses and data are stable,
pulsed.
m
m
The SNAPI Pulse programming algorithm uses initial pulses of 100 microseconds (its) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10
(ten) 1DO-its pulses per byte are provided before a failure is recognized.
~
en
\J
:JJ
The programming mode is achieved when Vpp = 13.0 V, Vee = 6.5 V, G = VIH, and E = VIL.
More than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAPI Pulse programming routine is complete, all bits are verified
with Vee = Vpp = 5 V.
o
~
en
-
fast programming
The 256K EPROM and PROM can be programmed using the Fast programming algorithm illustrated by
the flowchart in Figure 2. During Fast programming, data is presented in parallel (eight bits) on pins 01
to 08. Once addresses and data are stable, E is pulsed. The programming mode is achieved
when Vpp = 12.5 V, Vee = 6.0 V, G = VIH, and E = VIL. More than one device can be
programmed when the devices are connected in parallel. Locations can be programmed in any order.
Fast programming uses two types of programming pulses: Prime and Final. The length of the Prime pulse
is 1 millisecond; this pulse is applied X times. After each Prime pulse, the byte being programmed is verified.
If the correct data is read, the Final programming pulse is applied; if correct data is not read, an additional
1 millisecond pulse is applied up to a maximum X of 25. The Final programming pulse is 3X long. This
sequence of programming and verification is performed at Vee = 6.0 V and Vpp = 12.5 V. When the
full Fast programming routine is complete, all bits are verified with Vee = Vpp = 5 V.
program inhibit
Programming may be inhibited by maintaining a high level input on the
E pin.
program verify
Programmed bits may be verified with Vpp
12.5 V when
G=
VIL and
E=
VIH.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode
is activated when A9 is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AD; i.e.,
AO = VIL accesses the manufacturer code which is output on 01-08; AO = VIH accesses the device
code which is output on 01-08. All other addresses must be held at VIL. Each byte possesses odd parity
on bit 08. The manufacturer code for these devices is 97, and the device code is 04.
6-94
TEXAS . .
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POST OFFICE BOX 1443 •
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TMS27C256 262.144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256 262.144·BIT PROGRAMMABLE READ·ONLY MEMORY
en
~
oa:
INCREMENT ADDRESS
c..
w
w
-
PROGRAM
MODE
en
:2:
oa:
c..
NO
en
~
oa:
..
c..
w
INTERACTIVE
MODE
NO
FINAL
I
FIGURE 1. SNAP! PULSE PROGRAMMING FLOWCHART
TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443 •
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6-95
TMS27C256 262,144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256 262,144·BIT PROGRAMMABLE READ·ONLY MEMORY
m
.."
:IJ
o
s:
til
.."
:IJ
o
s:til
m
m
.."
:IJ
o
s:
til
-
DEVICE
FAILED
INCREMENT
ADDRESS
FIGURE 2. FAST PROGRAMMING FLOWCHART
6-96
TEXAS
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INSTRUMEN~
POST OFFICE BOX 1443 •
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TMS27C256 262,144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256 262,144·BIT PROGRAMMABLE READ·ONLY MEMORY
logic symbols t
EPROM 32.768 x 8
AO
A1
A2
A3
A4
AS
A6
A7
A8
(10)
(9)
A1
(8)
(7)
A2
A3
(6)
(S)
A'V
(4)
o
A'V
A--A'V
32.767 A 'V
(3)
(2S)
(24)
A9
(21)
A10
(23)
A11
(2)
A12
(26)
A13
(27)
A14
(20)
E
(22)
A'V
A'V
A'V
A'V
en
PROM 32.768 x 8
AO
0
(~!L
01
- . -(12)
-02
(13)
03
(1S)
04
(16)
OS
(17)
06
(18)
07
(19)
08
14
[PWR OWN)
A4
AS
A6
A7
A8
(10)
(9)
a:
c..
w
w
G
-
(6)
(5)
(12)
A'V
A-O-A'V
32.767 A 'V
(3)
(2S)
(24)
(22)
(11 )
A'V
(4)
E
r--
0
(8)
(7)
A9
(21)
A10
(23)
A11
(2)
A12
(26)
A13
(27)
A14
(20)
Lc::". M E N
~
0
(13)
(1S)
A'V
A'V
A'V
~
r-
~
0
03
a:
c..
en
04
(16)
OS
(17)
06
(18)
07
(19)
08
A'V
en
01
02
14
[PWR OWN)
MEN
~
..
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12.
J and N packages illustrated.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted):t:
Supply voltage range, VCC (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.6 V to 7 V
Supply voltage range, Vpp (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.6 V to 14 V
Input voltage range (see Note 1): All inputs except AS. . . . . . . . . . . . . . . . . . . ..
- 0.6 V to 6.5 V
AS .................................. -0.6Vt013.5V
Output voltage range (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.6 V to VCC + 1 V
Operating free-air temperature range ('27C256-__JL and JL4; '27PC256-__ NL
°c to 70 °c
and FML) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Operating free-air temperature range ('27C256-__JE and JE4). . . . . . . . . . . . . . .. - 40 °c to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
- 65°C to 150 °C
a
:tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only. and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1: Under absolute maximum ratings. voltage values are with respect to GND.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
0
6-S7
a:
c..
w
TMS27C256 262,144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256 262,144·BIT PROGRAMMABLE READ·ONLY MEMORY
recommended operating conditions
m
'27C256-12
'27C256-150, '27PC256-150
'27C256-15, '27PC256-15
'27C256-17, '27PC256-17
'27C256-1, '27PC256-1
'27C256-2, '27PC256-2
."
:xl
o
'27C256, '27PC256
3:
-o
(I)
."
Vee Supply voltage
:xl
Read mode (see Note 2)
MIN
4.75
NOM
5
Fast programming algorithm
5.75
6
6.5
SNAP I Pulse programming algorithm
Read mode (see Note 3)
3:
(I)
Vpp
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature (See table, page 2)
m
m
."
:xl
o
3:
(I)
-
'27C256-120
Fast programming algorithm
SNAPI Pulse programming algorithm
TTL
eMOS
NOTES:
TTL
eM OS
6.25
Vee- O.6
12
12.75
2
Vee- 0 . 2
UNIT
'27C256-25, '27PC256-25
MAX
5.25
6.25
6.75
Vee+ 0 . 6
12.5
13
13.0
'27C256-20, '27PC256-20
13.25
Vee+ 1
Vee+ 1
-0.5
0.8
-0.5
0.2
(See table, page 2)
MIN
4.5
5.75
NOM
5
6
6.25
6.5
Vee- 0 . 6
12
12.75
2
MAX
5.5
6.25
6.75
V
V
V
Vee+ 0 . 6
12.5
13
V
V
13.0
V
V
13.25
Vee+ 1
Vee+ 1
Vee- 0 . 2
-0.5
0.8
-0.5
0.2
(See table, page 2)
V
V
V
De
2. Vee must be applied before or at the same time as Vpp and removed after or at the same time as Vpp. The device must
not be inserted into or removed from the board when Vpp or Vee is applied.
3. Vpp can be connected to Vee directly (except in the program mode). Vee supply current in this case would be lee + Ipp.
electrical characteristics over full ranges of recommended operating conditions
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
Output current (leakage)
10
IpP1
IpP2
Vpp supply current
Vpp supply current
(during program pulse)
Vee supply current
lee1
lee2
TEST CONDITIONS
= -2.5 rnA
IOH = -20 p.A
IOL = 2.1 rnA
IOL = 20 p.A
VI = 0 V to 5.5 V
Vo = 0 V to Vee
Vpp = Vee = 5.5
IOH
(standby)
=
Vpp
I TTL-input level
I eMOS-input level
Vec supply current (active)
MIN
3.5
Typt
MAX
V
V
Vee- 0 . 1
V
13 V
= 5.5 V, E = VIH
= 5.5 V, E = Vee
Vee = 5.5 V, E = VIL,
tcycl e = minimum cycle time,
UNIT
0.4
0.1
V
V
±1
±1
p.A
p.A
1
10
p.A
35
50
rnA
Vee
250
500
p.A
Vee
100
250
p.A
15
30
rnA
outputs open
tTypical values are at TA = 25 De and nominal voltages.
capacitance over recommended supply voltage range and operating free·air temperature range,
f = 1 MHz*
PARAMETER
TEST CONDITIONS
Ci
Input capacitance
VI = 0 V, f
eo
Output capacitance
Vo
=
0 V,
= 1 MHz
f = 1 MHz
tTypical values are at T A = 25 De and nominal voltages
teapacitance measurements are made on sample basis only.
6-98
TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MIN
Typt
MAX
6
10
pF
10
14
pF
UNIT
TMS27C256 262,144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256 262,144·BIT PROGRAMMABLE READ·ONLY MEMORY
switching characteristics over full ranges of recommended operating conditions (see Notes 4 and 5)
'27C256-120
TEST CONDITIONS
PARAMETER
(SEE NOTES 4 AND 5)
'27C256-12
Access time from address
talE)
Access time from chip enable
CL = 100 pF,
1 Series 74 TTL Load,
ten/G) Output enable time from G
tdis
Input tr :5 20 ns,
Output disable time from G or E, whichever occurs first t
UNIT
tn
:?1
oa:
a..
0
MAX
120
MIN
MAX
150
ns
120
150
ns
55
75
ns
60
ns
45
0
w
w
tn
:?1
oa:
a..
Input tf :5 20 ns
Output data valid time after change of address, E, or G,
tv/A)
'27C256-15
'27PC256-15
MIN
talA)
'27C256-150
'27PC256-150
0
0
whichever occurs first t
ns
-o
tn
TEST CONDITIONS
PARAMETER
(SEE NOTES 4 AND 5)
'27C256-1
'27C256-2
'27C256
'27PC256-1
'27PC256-2
'27PC256
'27C256-17
'27C256-20
'27C256-25
'27PC256-17
MAX
'27PC256-20
MAX
MIN
'27PC256-25
MIN
MAX
MIN
UNIT
Access time from address
170
200
250
ns
talE)
Access time from chip enable
170
200
250
ns
ten/G)
Output enable time from G
75
75
100
ns
tdis
E,
60
ns
Output disable time from G or
tv/A)
1 Series 74 TTL Load,
whichever occurs first t
Input tr :5 20 ns,
Output data valid time after
Input tf :520 ns
change of address,
G,
E.
0
or
60
0
0
60
0
0
..
w
talA)
CL = 100 pF,
:?1
a:
a..
ns
0
whichever occurs first t
tValue calculated from 0.5 V delta to measured output level. This parameter is only sampled and not 100% tested.
switching characteristics for programming: Vee = 6 V and VPP = 12.5 V (Fast) or Vee = 6.50 V
and Vpp ... 13.0 V (SNAP! Pulse), TA = 25°e (see Note 4)
MIN
PARAMETER
tdis/G)
Output disable time from G
ten/G)
Output enable time from G
0
NOM
MAX
UNIT
130
ns
150
ns
NOTES: 4. For all switching characteristics the input pulse levels are 0.40 V to 2.4 V. Timing measurements are made at 2.0 V for
logic 1 and 0.8 V for logic O. (Reference page 11.)
5. Common test conditions apply for the tdis except during programming.
TEXAS
"J1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 71001
6-99
TMS27C256 262.144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256 262.144·BIT PROGRAMMABLE READ·ONLY MEMORY
recommended timing requirements for programming, Vee = 6 V, and Vpp
Vee = 6.5 V and Vpp = 13.0 V (SNAP! Pulse), T A = 25°e (see Note 4)
m
"'tJ
::a
o
tw(lPGM)
Initial program pulse duration
Fast programming algorithm
SNAPI Pulse programming algorithm
12.5 V (Fast) or
MIN
NOM
MAX
UNIT
0.95
1
1.05
ms
95
100
105
",s
78.75
ms
s:
-o
s:
-
tw(FPGM)
tb
tsu(A)
Address setup time
2
",s
"'tJ
tsu(G)
G setup time
2
",s
tsu(E)
E setup time
2
",s
tsu(D)
Data setup time
2
",s
tsu(VPP)
VPP setup time
2
",s
m
tsu(vee)
Vee setup time
2
",s
::a
o
th(A)
Address hold time
0
",s
th(D)
Data hold time
2
",s
::a
tb
m
"'tJ
..
s:
tb
NOTES:
6-100
Final pulse duration
Fast programming only
2.85
4. For all switching characteristics the input pulse levels are 0.40 V to 2.4 V. Timing measurements are made at 2.0 V for logic 1
and 0.8 V for logic O. (Reference page 11.)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
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TMS27C256 262,144·BIT UV ERASABLE PROGRAMMAB~E READ·ONLY MEMORY
TMS27PC256 262,144·BIT PROGRAMMABLE READ·ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.oa v
-!1
tn
~
oa:
RL-aoon
OUTPUT
UNDER TEST
CL =
c..
w
w
-
100 pF
tn
:E
oa:
c..
FIGURE 3. OUTPUT LOAD CIRCUIT
tn
~
oa:
AC testing input/output wave forms
2.4 V
----,.~20 v
~:
2.0
..
c..
w
v-\;
0.40 V_ _ _ _---4f-+.=~
__o._a-v---S~"'._ _.......o......a_v"""I:(\"".- - - - - A.C. testing inputs are driven at 2.4 V for logic 1 and 0.4 V for logic O. Timing measurements are made
at 2.0 V for logic 1 and 0.8 V for logic 0 for both inputs and outputs.
read cycle timing
AO-A14
x
X
ADDRESSES VALID
I
I
I
I
I
I
IQ1-Qa
HI-Z
VIL
I
I
1
1
VIH
\I--\
I
talA)
I
1
j4 tenlG)
--i
... 1
«««
TEXAS
"I
1 I-
tVIA)--t----j
OUTPUT
VALID
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
1:
VIH
VIL
1
I 1
I
-I
talE)
11
VIH
HOUSTON, TEXAS 77001
VIL
tdis
I
B
VOH
HI-Z-VOL
6-101
TMS27C256 262,144·BIT UV ERASABLE PROGRAMMABLE READ·ONL Y MEMORY
TMS27PC256 262,144·BI1 PROGRAMMABLE READ·ONLY MEMORY
program cycle timing
PROGRAM---r---VERIFY------1
m
."
I
I
:xl
o
s:
en
."
:xl
o
s:en
m
m
."
:xl
o
s:
en
t tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer.
:1:12.5 V Vpp and 6.0 V Vee for Fast programming; 13.0 V Vpp and 6.5 V Vee for SNAPI Pulse programming.
device symbolization
This data sheet is applicable to all TI TMS27C256 CMOS EPROMs and TMS27PC256 PROMs with the
data sheet revision code A" as shown below:
II
0
TI
t
FML
TMS27PC256
_L_ X__P ~~:!!.~
DATA SHEET RE VISION CODEJ
FRONT END COD E
DIE REVISION CO DE
BACKEND CODE
YEAR OF MANUFACTURE
WEEK OF MANU FACTURE
6-102
DATA SHEET REVISION CODE
FRONT END CODE----~
DIE REVISION CODE-----~
BACKEND C O D E - - - - - - - - - '
YEAR OF MANUFACTURE-------'
WEEK OF MANUFACTURE-------....
TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443 •
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TMS27C256 262,144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256 262,144·BIT PROGRAMMABLE READ·ONLY MEMORY
TYPICAL TMS27C/PC256 CHARACTERISTICS
STANDBY SUPPLY CURRENT
1.50
STANDBY SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
1.25
TA
_1
~
~
1.00
25 °C
~
...........
r--. ""--
1.00
-
V
./
0.75
-50
-25
o
25
50
75
100
125
4.5
4.75
vs
SUPPLY VOLTAGE
5.5
...........
r---
--
~
1.00
~V
0.75
~
..
~
V
0.50
-50
-25
0
25
50
75
100
125
4.25
4.5
5.0
5.25
5.5
5.75
VCC-Supply Voltage-V
ACCESS TIME
ACCESS TIME
vs
SUPPLY VOLTAGE
vs
FREE-AIR TEMPERATURE
1.50
4.75
1.50
VCC - 5.0 V
E
U ..........
<{<{<{z><{<{
I ' ..........
•
•
o
43
400 mV Guaranteed DC Noise Immunity
with Standard TTL Loads
2 1323130
0
29
28
27
Latchup Immunity of 250 mA on All Input
and Output Lines
Low Power Dissipation (VCC = 5.25 V)
- Active ... 158 mW Worst Case
- Standby ... 1.4 mW Worst Case
(CMOS Input Levels)
26
NC
25
GNpp
24
A10
23
E
22
08
07
21
4 1 5 1 6 17 18 1 9 20
PEP4 Version Available with 168 Hour Burn-in,
and also Guaranteed Operating Temperature
Ranges
A8
A9
A11
o 512K EPROM Available with MILSTD-883C Class B High Reliability
Processing (SMJ27C512)
description
The TMS27C512 series are 524,288-bit,
ultraviolet-light
erasable,
electrically
programmable read-only memories.
PIN NOMENCLATURE
AO-A 15 Address Inputs
E
The TMS27PC512 series are 524, 288-bit, onetime, electrically programmable read-only
memories.
These devices are fabricated using power-saving
CMOS technology for high speed and simple
interface with MOS and bipolar circuits. All inputs
(including program data inputs) can be driven by
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
spacifications par the tarms of Taxas Instruments
standard warranty. Production processing does not
necessarily includa tasting of all parameters.
TEXAS
12-13 V Programming Power Supply
GND
Ground
NC
No Connection
NU
Make No External Connection
01-08
Outputs
VCC
5-V Power Supply
~
INSTRUMENTS
POST OFFICE BOX 1443 •
Chip Enable/Power Down
G/Vpp
HOUSTON, TEXAS 77001
Copyright © 1985. Texas Instruments Incorporated
6-105
TMS27C512 524,288·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC512 524,288·BIT PROGRAMMABLE READ·ONLY MEMORY
Series 74 TTL circuits without the use ofexternal pull-up resistors. Each output can drive one Series 74 TTL
circuit without external resistors.
m
The data outputs are three-state for connecting multiple devices to a common bus. The TMS27C512 and
the TMS27PC512 are pin compatible with 28-pin 512K MaS ROMs, PROMs, and EPROMs.
."
;:g
o
s:
en
The TMS27C512 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
moullting hole rows on 15,2-mm (600-mil) centers. The TMS27C512 is available with two guaranteed
temperature ranges of ooC to 70°C and -40°C to 85°C (TMS27C512-__ JL and TMS27C512-__ JE,
respectively). The TMS27C512 is also offered with 168 hour burn-in on both temperature ranges
(TMS27C512-__ JL4 and TMS27C512-__ JE4, respectively). (See table below.)
."
;:g
o
s:
en
m
m
The TMS27PC512 PROM is offered in a dual-in-line plastic package (N suffix) designed for insertion in mounting
hole rows on 15,2-mm (600-mil) centers. The TMS27PC512 is also supplied in a 32-lead plastic leaded chip
carrier package using 1,25-mm (50-mil) lead spacing (FM suffix). The TMS27PC512 is guaranteed for operation
from ooC to 70°C.
o
All package styles conform to JEDEC standards.
."
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..
s:
en
SUFFIX FOR PEP4
SUFFIX FOR OPERATING
TEMPERATURE RANGES
EPROM
168 HR. BURN-IN
VS TEMPERATURE RANGES
OOC TO 70°
-40°C TO 85°C
WITHOUT PEP4 BURN-IN
I
I
OOC TO 70°C
TMS27e512-XXX
JL
I
-40°C TO 85°C
JE
JL4
I
JE4
These EPROMs and PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use in
microprocessor-based systems. One other 12-13 V supply is needed for programming. All programming signals
are TTL level. These devices are programmable by either Fast or SNAP! Pulse programming algorithms. Fast
programming uses a Vpp of 12.5 V and a VCC of 6.0 V for a nominal programming time of two minutes. SNAP!
Pulse programming uses a Vppof 13.0 V and a V CC of 6. 5 V for a nominal programming time of four seconds.
For programming outside the system, existing EPROM programmers can be used. Locations may be
programmed singly, in blocks, or at random.
operation
There are seven modes of operation listed in the following table. Read mode requires a single 5-V supply. All
inputs are TTL level except for Vpp during programming (12.5 V for Fast or 13.0 V
for SNAP! Pulse) and 12 Von A9 for signature mode.
MODE
FUNCTION
Read
Output
Disable
Standby
Programming
Verify
Program
Signature
Inhibit
Mode
E
VIL
VIL
VIH
VIL
VIL
VIH
VIL
G/Vpp
VIL
VIH
xt
Vpp
VIL
Vpp
VIL
Vee
Vee
Vee
Vee
Vee
Vee
Vee
A9
X
X
X
X
X
X
VH~
AO
X
X
X
X
X
X
VIL
01·08
DOUT
HI-Z
HI-Z
DIN
DOUT
HI-Z
MFG
Vee
I VH~
I VIH
CODE
97
tx ean be VIL or VIH.
~VH = 12 V ± 0.5 V.
6-106
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
I DEVICE
I 85
TMS27C512 524,288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524,288-BIT PROGRAMMABLE READ-ONLY MEMORY
readloutput disable
When outputs of two or more TMS27C512s or TMS27PC512s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E and
GNpp pins. All other devices in the circuit should have their outputs disabled by applying a highlevel signal to one of these pins. Output data is accessed at pins 01 through 08.
tJ)
:!:
oa:
a..
w
-o
w
latchup immunity
t J)
Latchup immunity on the TMS27C512 and TMS27PC512 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients atthe P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input/output layout approach controls latchup
without compromising performance or packing density.
:!:
a:
a..
t J)
For more information see application report SMLA001; "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family, " available through TI Field Sales Offices.
power down
Active ICC current can be reduced from 30 mA to 500 p,A (TTL-level inputs) or 250 p,A (CMOS-level inputs)
by applying a high TTL signal to the E pin. In this mode all outputs are in the high-impedance state .
erasure (TMS27C512)
Before programming, the TMS27C512 EPROM is erased by exposing the chip through the transparent lid to
high intensity ultraviolet light (wavelength 2537 angstroms). EPROM erasure before programming is necessary
to assure that all bits are in the logic 1 (high) state. Logic Os are programmed into the desired locations. A
programmed logic 0 can be erased only by ultraviolet light. The recommended minimum ultraviolet light
exposure dose (UV intensity x exposure time) is 15 watt-seconds per square centimeter. A typical 12-milliwattper-square-centimeter, filterless UV lamp will erase the device in 21 minutes. The lamp should be located
about 2.5 centimeters above the chip during erasure. It should be noted that normal ambient light contains
the correct wavelength for erasure. Therefore, when using the TMS27C512, the window should be covered
with an opaque label.
:!:
..
initializing (TMS27PC512)
The one-time programmable TMS27PC512 PROM is provided with all bits in the logic 1 state, then logic Os
are programmed into the desired locations. Logic Os programmed into a PROM cannot be erased.
SNAP! Pulse programming
The 512K EPROM and PROM can be programmed using the TI SNAP! Pulse programming algorithm illustrated
by the flowchart in Figure 1, which can reduce programming time to a nominal of four seconds. Actual
programming time will vary as a function of the programmer used.
Data is presented in parallel (eight bits) on pins 01 to 08. Once addresses and data are stable,
E is pulsed.
The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (p,s) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10
(ten) 100-p,s pulses per byte are provided before a failure is recognized.
The programming mode is achieved when GNpp = 13.0 V, VCC = 6.5 V, and E = VIL. More than
one device can be programmed when the devices are connected in parallel. Locations can be programmed
in any order. When the SNAP! Pulse programming routine is complete, all bits are verified when
VCC = 5 V, GNpp = VIL, and E = VIL.
-1.!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
oa:
6-107
a..
w
TMS27C512 524,288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524,288-BIT PROGRAMMABLE READ-ONLY MEMORY
Fast programming
The 512K EPROM and PROM can be programmed using the Fast programming algorithm illustrated by the
flowchart in Figure 2. During Fast programming, data is presented in parallel (eight bits) on pins 01 through
08. Once addresses and data are stable, E is pLlsed. The· programming mode is achieved when
G/Vpp = 12.5 V, Vee = 6.0 V, and E = VIL. More than one device can be programmed when the devices
are connected in parallel. Locations can be programmed in any order.
m
"tI
::D
o
3:
en
-
Fast programming uses two types of programming pulses: Prime and Final. The length of the Prime pulse is
1 millisecond; this pulse is applied X times. After each Prime pulse, the byte being programmed is verified.
If the correct data is read, the Final programming pulse is applied; if correct data is not read, an additional 1
millisecond pulse is applied up to a maximum X of 25. The Final programming pulse is 3X long. This sequence
of programming and verification is performed at Vee = 6.0 V and G/Vpp = 12.5 V. When the
full Fast programming routine is complete, all bits are verified when Vee = 5 V and G/Vpp = VIL.
" tI
::D
o
3:
en
m
m
"tI
::D
program inhibit
o
Programming may be inhibited by maintaining a high level input on the
3:
en
E pin.
program verify
Programmed bits may be verified when G/Vpp and E = VIL.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated whenA9 is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AO; i.e., AO = VILaccesses
the manufacturer code, which is output on 01-08; AO = VIH accesses the device code, which is output on
01-08. All other addresses mustbe held atVIL. Each byte possesses odd parity on bit 08. The manufacturer
code for these devices is 97, and the device code is 85.
6-108
TEXAS
'1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS27C512 524,288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524,288-BIT PROGRAMMABLE READ-ONLY MEMORY
U)
~
o
r::r:::
a..
w
INCREMENT ADDRESS
-o
w
PROGRAM
MODE
U)
~
r::r:::
a..
NO
U)
~
or::r:::
..
a..
w
PROGRAM ONE PULSE = tw = 100 Ils
FAIL
>--~X=X+
INTERACTIVE
MODE
1
NO
YES
DEVICE FAILED
FAIL
FINAL
I
FIGURE 1. SNAP! PULSE PROGRAMMING FLOWCHART
TEXAS
"'!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-109
TMS27C512 524,288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524,288-BIT PROGRAMMABLE READ-ONLY MEMORY
m
."
:xl
o
s:en
-o
."
:xl
s:
en
m
m
."
:xl
o
..
s:
en
INCREMENT
ADDRESS
FIGURE 2. FAST PROGRAMMING FLOWCHART
6-110
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS27C512 524,288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524,288-BIT PROGRAMMABLE READ-ONLY MEMORY
logic symbols t
AO
A1
A2
A3
A4
A5
A6
A7
(10)
(9)
G/Vpp
EPROM
AO
65,536 x 8
A1
(8)
A2
(7)
A3
(6)
(5)
A'V
(4)
(3)
(25)
A8
(24)
A9
(21)
A10
(23)
A11
(2)
A12
(26)
A13
(27)
A14
(1 )
A15
(20)
E
0'"
A'V
0
;>A65.535
A'V
A'V
A'V
A'V
A'V
A'V
(11 )
(12)
(13)
(15)
(16)
(17)
(18)
(19)
01
A4
A5
02
A6
03
04
A7
05
06
07
08
15....
[PWR OWN]
0'"
(9)
tI)
PROM
~
65,536 x 8
0
a:
(8)
(7)
c..
w
w
(6)
(5)
AV
(4)
A'V
(3)
(25)
A8
(24)
A9
(21)
A10
(23)
A11
(2)
A12
(26)
A13
(27)
A14
(1 )
A15
(20)
E
(22)~ ~EN
(10)
0
>A65.535
A'V
A'V
A'V
AV
AV
AV
(11 )
(12)
(13)
(15)
(16)
(17)
(18)
(19)
t I)
~
01
0
02
a:
03
c..
04
t I)
~
05
06
07
08
15....
&
(22)~ ~-rNl
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for J and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted):I:
Supply voltage range, VCC (see Note 1) ., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.6 V to 7 V
Supply voltage range, Vpp (see Note 1) .... . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 ..................... -0.6 V to 6.5 V
A9 ................................. -0.6 V to 13.5 V
Output voltage range (see Note 1) ................................ -0.6 V to Vce + 1 V
Operating free-air temperature range ('27C512-_o_JL and JL4; '27PC512-__ NL
and FML) .............................. DoC to 70°C
Operating free-air temperature range ('27C512-__ JE and JE4) ............... -40°C to 85°C
Storage temperature range .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
*Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only. and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1: Under absolute maximum ratings. voltage values are with respect to GND.
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
a:
..
EN
G/Vpp
0
6-111
c..
W
TMS27C512 524,288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524,288-BIT PROGRAMMABLE READ-ONLY MEMORY
recommended operating conditions
m
"'C
::g
o
s:
en
"'C
::g
o
s:
en
m
m
"'C
::g
o
s:en
Read mode (see Note 2)
Supply voltage Fast programming algorithm
Vee
SNAPI Pulse programming algorithm
G/Vpp Supply voltage
Fast programming algorithm
SNAPI Pulse programming algorithm
'27C/PC512-20
'27C/PC512
'27C/PC512-25
'27C/PC512-3
'27C/PC512-30
NOM
MAX
5.25
MIN
4.5
NOM
5
5
MAX
5.5
V
5.75
6
6.25
5.75
6
6.25
V
6.25
6.5
6.75
6.25
6.5
6.75
V
12
12.5
13
12
12.5
13
V
12.75
13.0
VIL
Low-level input voltage
TA
Operating free-air temperature (See table, page 2)
13.25
Vee+ 1
Vee- 0 . 2
-0.5
TTL
Vee+ 1
0.8
-0.5
CMOS
UNIT
MIN
2
CMOS
NOTE 2:
'27C512-17
'27C/PC512-2
4.75
TTL
High-level input voltage
VIH
'27C512-1
0.2
(See table, page 2)
12.75
13.25
V
Vee+ 1
V
Vee+ 1
0.8
V
13.0
2
Vee- 0 . 2
-0.5
-0.5
0.2
V
V
DC
(See table, page 2)
Vee must be applied before or at the same time as G/Vpp and removed after or at the same time as G/Vpp. The device must not be
inserted into or removed from the board when Vpp or Vee is applied .
. . electrical characteristics over full ranges of recommended operating conditions
TEST CONDITIONS
PARAMETER
10H = -2.5mA
VOH High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10H = -20p.A
0.1
V
±1
p.A
Vo = OVtoVee
G/Vpp = 13V
I TTL-input level
V
10L = 20p.A
Output current (leakage)
I CMOS-input level
V
Vee- 0 . 1
VI = OVto 5.5 V
G/Vpp supply current (during program pulse)
(standby)
UNIT
0.4
Ipp
Vee supply current
MAX
3.5
10L = 2.1 mA
10
lee1
MIN Typt
V
±1
p.A
35
50
mA
Vee = 5.5 V, E = VIH
250
500
p.A
Vee = 5.5V, E = Vee
100
250
p.A
15
30
mA
Vee = 5.5 V, E = VIL,
leC2 Vce supply current (active)
tcycle = minimum cycle time,
outputs open
tTypical values are at T A = 25 DC and nominal voltages.
capacitance over recommended supply voltage range and operating free-air temperature range,
f = 1 MHz*
Typt
MAX
10
pF
Vo = OV,f = 1 MHz
6
10
14
pF
G/Vpp = OV,f = 1 MHz
20
25
pF
PARAMETER
TEST CONDITIONS
Ci
Input capacitance
VI=OV,f=1MHz
Co
Output capacitance
CG/vPP
G/Vpp input capacitance
tTypical values are at T A = 25 DC and nominal voltages.
~Capacitance measurements are made on sample basis only.
6-112
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MIN
UNIT
TMS27C512 524,288·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC512 524,288·BIT PROGRAMMABLE READ·ONLY MEMORY
switching characteristics over full ranges of recommended operating conditions (see Notes 3 and 4)
TEST CONDITIONS
PARAMETER
(SEE NOTES 3 AND 4)
'27C512-1
'27C/PC512-2
'27C512-17
'27C/PC512-20 '27C/PC512-25
MIN
MIN
MAX
'27C/PC512
MAX
MIN
UNIT
talA)
Access time from address
170
200
250
ns
talE)
Access time from chip enable
170
200
250
ns
ten(G)
Output enable time from G/Vpp
CL"'; 100 pf,
75
75
100
ns
Output disable time from G/Vpp
1 Series 74 TTL Load,
60
ns
tdis
tv(A)
or E, whichever occurs first t
Input tr :s 20 ns,
Output data valid time after
Input tf :s 20 ns
0
change of address, E, or G/Vpp,
whichever occurs first t
0
60
60
0
0
0
en
:2E
MAX
o
a:
c..
w
w
en
~
oa:
c..
ns
0
en
:2E
PARAMETER
'27C/PC512-30
(SEE NOTES 3 AND 4)
MIN
talA)
Access time from address
talE)
Access time from chip enable
CL = 100 pf,
1 Series 74 TTL Load,
tenlG) Output enable time from G/Vpp
tdis
Output disable time from G/Vpp or E, whichever occurs first t
Input tr :s20 ns
tvlA)
Output data valid time after change of address, E, or G/Vpp, whichever
occurs first t
Input tf :s 20 ns
oa:
'27C/PC512-3
TEST CONDITIONS
0
UNIT
MAX
300
ns
300
ns
120
ns
105
ns
ns
0
= 12.5 V (Fast) or Vee
MIN
PARAMETER
o
Output disable time from G/Vpp
NOM
6.50V
MAX
130
NOTES: 3. For all switching characteristics the input pulse levels are 0.40 V to 2.4 V. Timing measurements are made at 2.0 V for logic 1
and 0.8 V for logic O. IReference page 11.)
4. Common test conditions apply for tdis except during programming.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
w
-
tValue calculated from 0.5 V delta to measured output level. This parameter is only sampled and not 100% tested.
switching characteristics for programming: Vee = 6 V and G/Vpp
and G/Vpp = 13.0 V (SNAP! Pulse), T A = 25°e (see Note 3)
c..
6-113
TMS27C512 524,288·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC512 524,288·BIT PROGRAMMABLE READ·ONLY MEMORY
recommended timing requirements for programming: Vee = 6 V and G/Vpp = 12.5 V (Fast) or
Vee = 6.50 V and G/Vpp = 13.0 V (SNAP! Pulse), TA = 25°e (see Note 3)
m
."
:lJ
MIN
TYP
MAX
UNIT
0.95
1
1.05
ms
95
100
105
/lS
78.75
ms
tw(lPGM)
Initial program pulse duration
3:
(I)
-
tw(FPGM)
Final pulse duration
tsu(A)
Address setup time
2
/lS
."
:lJ
tsu(D)
Data setup time
2
/ls
tsu(VPP)
G/Vpp setup time
2
/ls
3:
(I)
m
tsu(vee)
Vee setup time
2
p.s
th(A)
Address hold time
0
p.s
th(D)
Data hold time
2
p.s
th(VPP)
G/Vpp hold time
2
/ls
trec(PG)
G/Vpp recovery time
2
tEHD
Data valid from E low
tr(PG)G
G/Vpp rise time
o
o
m
."
:lJ
o
3:
(I)
_
Fast programming algorithm
NOTE 3.
6-114
SNAPI Pulse programming algorithm
Fast programming only
2.85
/ls
1
50
/ls
ns
For a" switching characteristics the input pulse levels are 0.40 V to 2.4 V. Timing measurements are made at 2.0 V for
logic 1 and 0.8 V for logic O. (Reference page 11.)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS27C512 524,288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524,288-BIT PROGRAMMABLE READ-ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.0a v
OUTPUT
UNDER TEST
---Jr
RL
=
en
aoo n
:1E
oa:
c..
w
-o
-o
CL = 100 pF
w
en
:1E
FIGURE 3. OUTPUT LOAD CIRCUIT
a:
c..
en
AC testing input/output wave forms
2.4 V
-----\f20
0.40 V _ _ _ _
:1E
20 vV
V
a:
w
c..
--4~F_.;.o..;.a..;.v-------o-.a-v""""I":f\'-.- - - - - -
A.C. testing inputs are driven at 2.4 V for logic 1 and 0.4 V for logic O. Timing measurements are made at
2.0 V for logic 1 and 0.8 V for logic 0 for both inputs and outputs.
read cycle timing
AO-A15 _ _ _ _ _ _
-
.J~""----A-D-DR-E-S-SE-S-V-A-L1-D---_'l~""--------_:::
i,
1
I
E------~!-~\,(L.---------""'IHs,.I---------VIH
~
f!
VIL
~1
I
I
G/Vpp
!
...
' ......- - t a ( E I - -....
\",___
, I
-~M,IL11'---"'-1-td-iS-----::~
.....,..!
ten(GI-+o-1•.....- .......~I
I
..._ _ _ _ ta(AI __;:;:;:;;:::
..
,
~I-t-V(-A-I:'-.:-:.-:.....- ....j.I....l
01-0a-------':.2
<<<~ O~;~,~T
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
»)
VOH
HI-Z-
6-115
TMS27C512 524.288·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC512 524.288·BIT PROGRAMMABLE READ·ONLY MEMORY
program cycle timing
m
AO-A15
."
::u
:s:
C/I
."
Ql-Q8
::u
0
m
m
~
OAT~ IN
r-tSU(DI~
:s:
C/I
-
VIL
I+- tsu(AI--+f
0
-
=x
KVIH
ADDRESS STABLE
th(AI-k+J
VIH'
VOH
)
STABLE
1--
~I
HI-Z
DATA OUT VALID
VIL'
VOL
j4-tEHD
th(DI
I
I
G/Vpp
."
::u
0
:s:
-
C/I
E
r-tSU(VPPI~
Irtr(PGIG II
tdis(GI
J..-th(VPPI-.j
II
trec(PGI
I-
·1
i
!.',"IVCCI.,V
I
I
~
I
,.-,-tW(lPGMI
.-.t-'wIfPGMI
1
t., r
I I
VPP
VIL
I
I
I
VIH
VIL
VCC*
Vce
Vce
t tdis(GI is a characteristic of the device but must be accommodated by the programmer_
:I: 12_5 V G/Vpp and 6.0 V Vee for Fast programming; 13.0 V G/Vpp and 6.50 V Vee for SNAPI Pulse programming.
device symbolization
This data sheet is applicable to all TI TMS27C512 CMOS EPROMs and TMS27PC512 CMOS PROMs with
the code "A" shown below:
0
TMS
27C512
TI
FML
TMS27PC512
~
ALXPYY~~
TLXPn::~~
DATA SHEET REV ISION CODE
FRONT END CODE
DIE REVISION COD E
BACK END CODE
YEAR OF MANUFA CTURE
WEEK OF MANUF ACTURE
6-116
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS27C512 524,288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524,288-BI1 PROGRAMMABLE READ-ONLY MEMORY
TYPICAL TMS27C/PC512 CHARACTERISTICS
STANDBY SUPPLY CURRENT
c
1.50
~
:l
U
VCC -
~
"C
N
~
E
1.00
0
16 !!; 0.75
TA
r---....
..........
9
-
"""-- ~
0.75
"
0.50
-50
o
-25
25 °C
1.00
I
0.50
-75
-1
1.25
iii
c:;
(I)
~
oa:
1.50
'"
Q)
:l
SUPPLY VOLTAGE
5.0 V
ii:C
Q.
en
vs
FREE-AIR TEMPERATURE
.... t-.......
1.25
>
STANDBY SUPPLY CURRENT
vs
25
50
75
100
125
4.25
V"
L
./
V
c..
w
w
~V
-o
-o
( I)
:E
a:
c..
( I)
4.5
T A -Free-Air Temperature- °C
4.75
5.0
5.25
5.5
5.75
~
a:
VCC-Supply Voltage-V
c..
w
ACTIVE SUPPLY CURRENT
ACTIVE SUPPLY CURRENT
..
c
1.50
!!!
:s
u
-a:gN
CD
vs
SUPPLY VOLTAGE
VCC - 5.0 V
1.25
~~
III
E 1.00
I
TA - 25°C
:s
u
Q.
Q.
""'""' ............. r--
0.75
1.25
f - MAX
~:c
::
·fi
V
c
«
TEXAS
-1.!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
6-127
TMS27C010
1,048,576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.08 V
m
"0
o
3:
OUTPUT
UNDER TEST
en
"0
T C L - 100 pF
:JJ
o
3:
en
-
FIGURE 3. OUTPUT LOAD CIRCUIT
m
m
"0
:JJ
o
AC testing input/output wave forms
3:
en
-
l>
c
<
l>
2
nm
-I
RL-800ll
:JJ
2.4
0.4
V---~X
v------J.
2.0
V
2.0
vj(
1f.._~0.~8.....;;V_ _ _ _ _ _ _ _ _ _._....;;;0..;.;;.8;...V;...,;jII_.
'-._ _ __
AC testing inputs are driven at 2.4 V for logic 1 and 0.4 V for logic O. Timing measurements are made at
2.0 V for logic 1 and 0.8 V for logic 0 for both inputs and outputs.
read cycle timing
~~_______________________
~\IJ
ADDRESSES VALID
1\~--------------VIH
AO-A 16 ~_
-
I
","I,.t------ta(AI
o
\
I
:2
'T1
I
II
.. I
I
I
I
I
I
\
::!
o
I
VI
!
01:'"1---------------VIH
I
(4-ten (GI.......,
I
2
Q1-Q8
r--------------VIH
!I
HI-Z---<<<<<<<<{
VIL
I I
I4----ta(EI~
s:l>
'---------------VIL
I I
I
J4--tdis----.l
tv(AI~
I
OUTPUT VALID
VIL
I
I
D>>>>>}-HI-Z-VIH
VIL
6-128
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
TMS27C010
1,048,576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
program cycle timing-32 bits
INTERACTIVE MODE
!-----------PROGRAMMING M O D E - - - - - - -....
14
.... (SEE NOTE 7)~
! - - - - - - - - - P A G E DATA LATCH-------._•....., PAGE
'
.:
i
PROGRAM
SINGLE
i
:
th(A)
o
a:
c..
~
VERIFY
~__________________~.____~]x(
en
~
BV!§.......j
~ VIH
::::l
I--
w
w
en
VIL
~:======~/-----~
.
,
.
,. ,. . . D-C~-~-·:. .,~rT">i: A'~}-~~: /
~~~~;W< A< >- H
~
oa:
A1
'r-
' T - -___i-T----....J.
~
11:-.._ _~
X
DIN
r-
"IC.-_ _~
--t
t su (D2)
DIN
L----...:lI
i
--t
I
---I I-- t su (D3)
c..
en
~
~ ~:~
o
a:
i
HI-Z~
!
I
tsu(PGM)
I
i
I
I
I
I
I
I
I
I
I
I
I
~
-J
c..
w
I t . VIL
I
I t-- dis
t--ten(G)
~--~-~----~----~-----~I---~I--4I--~I~--VpP
I
I
I
I
I
I
I
I
It
-l
tsu(E) ~ I-!- h(G) I
(READ MODE)
'
N
~--~-~----4----~----~I--~-
I
!I
---~~~~~~~~~--+---------~--------~
I
I
th(E)--!
II I
II I
I I
II
t--
I
I
I
I
I
I
I
I
I
t w (PGM)--1
~__________~II
II
~
Vcc
Vcc+ 1
I--I
I
-
:2
o
i=
VCC
«
yVIH
~
a:
VIL
o
LL
-2w
()
:2
«
NOTE 7: 8-bit programming is applied in Interactive Mode when needed.
>
c
c:::(
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-129
TMS27C010
1,048,576·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
program cycle timing-8 bits
-j-
1oI-t-----PROGRAM
VERIFY
-I
A~A~~~-------A-D-D-RE-S-SE-S~~-T-A-~-E-------~~~H
m
"0
:IJ
o
I
,
tsu(A)-"'--';
3:
en
-o
"0
DIN-----{
:IJ
DA~A
I
1
IN STABLE
I
I
tsu(D)""""--';
I
I
VPP ---./
I
3:
en
t.
I
!
m
m
"0
:IJ
I
VIL
I
} - - - H I . z H DATA OUT S;ABlE } - - - V'H
I
I
I
ten(G)-..i
I
I
I
I
tsu(VPP)~
o
~th(A)--t
I
I
..-
I
I
~
I
!--tdis
I
I
I
I
I
I
VIL
VPP
Vee
r-~I-----~I------~~------~II--------Vee+
3:
en
-
vee~1
if
I
I
I
I
I
I
I
I1
II
~
I
I
I
E
t!t--~I-----~I----+--------+-!-----
Vee
tsu(Veel-+-----!
l>
c
tsu(EI~
--.I
I
..
'LJ
~
2
I
I
tw(PGM)...-j
("')
m
I
I+-
k-th(D)
VIL
I
I
-----..L--------411- - - - -
---+1
I
VIH
I
I
I
t--tsu(GI....,j
I
\lI
--------------~I
-2
VIH
I
I
I
I '__--------
VIL
VIH
VIL
'TI
o:D
s:
l>
::!
o
2
6-130
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
1
TMS27C210
1,048,576·BI1 UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
MAY 1987-REVISED JUNE 1988
•
Wide·Word Organization ... 64K x 16
•
Single 5-V Power Supply
•
Operationally Compatible with Existing
Megabit EPROMs
•
40-Pin Dual-In-line Package
•
All Inputs and Outputs Fully TTL Compatible
•
Static Operations (No Clocks, No Refresh)
•
Max Access/Min Cycle Time
VCC ± 5%
VCC± 10%
'27C210-170
'27C210-200
'27C210-250
'27C21 0-300
'27C210-20
'27C210-25
'27C21 0-30
Vpp
VCC
E
PGM
016
015
014
013
012
011
NC
A15
A14
A13
A12
A11
010
A10
A9
09
170
200
250
300
GNDt
ns
ns
ns
ns
e
16-Bit Output For Use in MicroprocessorBased Systems
•
32-Bit Programming (Two 16-Bit Words)
and 16-Bit Programming
o
16 Seconds Typical Programming Time
•
Power Saving CMOS Technology
•
3-State Output Buffers
•
Uses Tl's Innovative ACE (Advanced
Contactless EPROM) Technology for Noise
Immunity and Improved Reliability
en
~
oa:
a..
w
w
en
~
oa:
a..
GNDt
08
07
06
05
04
03
02
01
G~____ .._
en
A8
A7
~
oa:
A6
A5
A4
A3
A2
a..
w
A1
AO
2
o
i=
PIN NOMENCLATURE
•
400 mV Guaranteed DC Noise Immunity
with Standard TTL Loads
•
Latchup Immunity of 250 rnA on All Input
and Output Pins
•
No Pull-Up Resistors Required
•
Low Power Dissipation
-Active ... 220 mW Worst Case
-Standby ... 1.5 mW Worst Case
(CMOS-Input Levels)
•
J PACKAGE
(TOP VIEW)
AO-A 1 5
Address Inputs
E
Chip Enable
G
Output Enable
GND
Ground
NC
No Connection
PGM
Program
Q1-Q16
Outputs
VCC
5-V Supply
Vpp
12.5-V Supplyt
c
A _ _
65,535
::2!:
&
,.....
EN
:1:This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) §
Supply voltage range, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 7.0 V
Supply voltage range, Vpp (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 13.0 V
Input voltage range (see Note 1), All inputs except A9 .............. - 0.6 V to Vee + 1.0 V
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6Vt013.5V
Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to Vee + 1.0 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 De to 70 De
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 De to 150 De
§Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1: Under absolute maximum ratings, voltage values are with respect to GND.
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-137
TMS27C210
1,048,576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
recommended operating conditions
m
"'a
:a
o
3:
"'a
:a
o
3:
en
VIH
-
VIL
m
m
"'a
:a
3:
en
TA
NOTES:
o
-
High-level input voltage
Low-level input voltage
'27C210-20
'27C21 0-250
'27C210-25
'27C210-300
'27C21 0-30
UNIT
MIN
MAX
NOM
MAX
5.25
4.5
5.5
5.0
Vee-1.0 Vee Vee+ 1.O Vee- 1.O Vee Vee+ 1.0
2.0
2.0
Vee+ 1
Vee+ 1
Vee- O.2
Vee+ 1
Vee+ 1 Vee- 0.2
-0.5
-0.5
0.8
0.8
-0.5
-0.5
GND+0.2
GND+0.2
MIN
4.75
Vee Supply voltage-read mode (see Note 2)
Vpp Supply voltage-read mode (see Note 3)
(I)
'27C210-170
'27C210-200
TTL
eM OS
TTL
eMOS
Operating free-air temperature
NOM
5.0
0
70
70
0
V
V
V
V
°e
2. Vee must be applied after or at the same time as Vpp and removed before or at the same time as Vpp. The device must
not be inserted into or removed from the board when Vpp or Vee is applied.
3. Vpp can be connected to Vee directly (except in the program mode). Vee supply current in this case would be lee + Ipp. During
programming, Vpp must be maintained at 12.5 V ± 0.25 V.
electrical characteristics over full range of operating conditions
TEST CONDITIONS
PARAMETER
10H
10H
VOH High-level output voltage
VOL
Low-level output voltage
II
10
Input current (leakage)
Output current (leakage)
10L
II TTL-input level
eMOS-input level
lee2 Vee supply current (active)
Typt MAX
= OVtoVee
= Vee = 5.5V
= 12.75 V (16-bit programming)
Vpp = 12.75 V (32-bit programming)
Vee = 5.5 V, E = VIH
Vee = 5.5 V, E = Vee ± 0.2 V
Vee = 5.5 V, E = VIL
tcycle = minimum cycle time,
±10
Vpp
Vpp
100
tTypical values are at TA = 25 °e and nominal voltages.
:I: Minimum cycle time = maximum address access time.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
UNIT
V
0.4
0.1
±1
Vo
outputs open:l:
6-138
MIN
Vee- 0 . 2
2.4
10L
VI = OVto5.5V
IpP1 Vpp supply current
IpP2 Vpp supply current (during program pulse)
IpP3 Vpp supply current (during program pulse)
lee1 Vee supply current (standby)
= -20pA
= -2.0 mA
= 2.1 mA
= 20pA
30
V
pA
p.A
50
100
pA
mA
mA
1
mA
250
p.A
40
mA
TMS27C210
1,048,576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
capacitance over recommended supply voltage range and operating free-air temperature range,
f ... 1 MHzt
PARAMETER
MIN TYP*
MAX
Ci
Input capacitance
VI = 0 V, f = 1 MHz
TEST CONDITIONS
6
10
pF
Co
Output capacitance
Vo = OV,f= 1 MHz
10
14
pF
UNIT
U)
:5
oa:
tCapacitance measurements are made on sample basis only.
*Typical values are at TA = 25°C and nominal voltages.
~
-o
w
w
switching characteristics over full ranges of recommended operating conditions (see Note 4)
PARAMETER
TEST CONDITIONS
ISEENOTE4)
'27C21 0-170
MIN
MAX
'27C210-20
'27C210-25
'27C210-30
'27C21 0-200
'27C21 0-250
'27C210-300
MIN
MAX
MIN
MAX
MIN
U)
:5
~
talA)
Access time from address
170
200
250
300
ns
talE)
Access time from chip enable
170
200
250
300
ns
75
75
100
100
ns
80
ns
CL = 100 pF,
ten(G) Output enable time from G
1 Series 74
Output disable time from G or
tdis
tv(A)
E, whichever occurs first§
Output data valid time after
change of address, E, or G,
TTL load,
Input tr ~ 20 ns,
Input tf :::; 20 ns
a:
UNIT
MAX
U)
:5
oa:
~
0
60
0
60
0
0
0
80
0
0
0
w
ns
whichever occurs first§
§Value calculated from 0.5 V delta to measured output level. This parameter is only sampled and not 100% tested.
NOTE 4: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2.0 V for logic 1 and
0.8 V for logic 0 (reference page 10.)
recommended timing requirements for programming, Vee - 6.5 V and Vpp "" 12.75 V, TA
(see Notes 4 and 5)
= 25°e
MIN
TYP
MAX
UNIT
tw(PGM)
Program pulse duration
0.45
0.5
0.55
ms
tsu(E)
Chip enable setup time
2
P.s
tsu(A)
Address setup time
2
p'S
tsu(G)
G setup time
2
tdis(G)
Output disable time from G (see Note 6)
0
ten(G)
Output enable time from G
tsu(D)
Data setup time
2
p'S
tsu(VPP)
VPP setup time
VCC setup time
2
2
P.s
Address hold time
0
P.s
P.s
tsu(VCC)
th(A)
p'S
100
ns
150
ns
p'S
th(D)
Data hold time
2
th(G)
Output enable hold time from data
2
p'S
tsu(DAO)
th(DAO)
th(E)
Data
100
ns
100
ns
Chip enable hold time
2
p.s
tw(E)
Chip enable pulse duration
200
ns
NOTES:
~etup
time before AO high
Data hold time after AO high
-
4. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2.0 V for
logic 1 and 0.8 V for logic 0 (reference page 10.)
5. Input signal tr and tf ~ 20 ns.
6. Common test conditions apply for tdis(G) except during programming.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-139
TMS27C210
1,048,576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.08 V
m
."
:u
o
n
RL = 800
~
en
-
OUTPUT
UNDER TEST
."
:u
o
TCL
~
en
= 100pF
m
m
."
:u
o
~
en
FIGURE 3. OUTPUT LOAD CIRCUIT
AC testing input/output wave forms
2.4
v--------.."{ 2.0 V
2.0 V
"Iv'
0.40 V--------J~L_.;;.;0.~8....;;V_ _ _ _ _ _ ___"0.;.;;;.8;..;V'_"':I\'_._ _ _ _ __
A.C. testing inputs are driven at 2.4 V for logic 1 and 0.4 V for logic O. Timing measurements are made
at 2.0 V for logic 1 and 0.8 V for logic 0 for both inputs and outputs.
read cycle timing
AO-A 15 _ _ _
---JX~i____A_D_DR_E_S_SE_S_V_A_L_ID_ _ _ _X,..... . .-_-_-_-_-_-_-_-_::~
i
I
I
------+---..
E
\
r----VIH
.Vi
_______________- 3 I
1
t - - - talE)
-;
I I
~I
\
!
0r:- - - - V I H
---It--~I
)1;..
tenlG)
! - - - - - - talA)
01-016 - - - - - - - - - - - H I - Z
I•
.. I
VIL
t-----j-tdis
I'
a a
I I tvlA)
VIL
_I
i
(,....(r(r(r(r~:ir:1---::O~~A~TL~~~~T~D»-~ HI-Z- VOH
VOL
6-140
TEXAS
-I!I
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
Co\)
N
Cr
;::;."
'C
o
CC
m
I
PROGRAMMING
I
VERIFY
hABLE ADDRESSES
th(A) --1
~
I II t- ta(A)-t
\l
I
~------HI
!'-----~
I
z
~
;c~
~~
z
~~
HIGH-ORDER
WORD DATA
I
VPP
V
I
G
J
~ r-tY(A)
HIGH-ORDER
WORD OUTPUT
=
=
~
u,
......
VIH
=
=
:::;
I
VPP
:a
I
I
I
I
I
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I
I
I
VIL
\
I
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tsu(D)--t------;
I
I
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PGM
I I
VIL
c:
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I
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I
I
I---tsu(E)---=!
I
I
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VIH
VIL
!
--t
I
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t---tsu(vee)
LOW-ORDER
WORD OUTPUT
CC
VIH
I
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If
I
k
~ th(D)
+----f I
JL,-tsu(VPP)~I
ee J
E
th(DAO)
I
I
I
I
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3
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Vee + 1
I
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I
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~~I~--~------------------~
~I
I
tw(PGM)-i
I
t--
I
I
I
I
I
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I
th(G)
I
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Vee
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VIH
VIL
VIH
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VIH
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m
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CI
6
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.....
~
I
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ON
:a<=
EPROMs/PROMs/EEPROMs
TMS27C210
1,048,576-BI1 UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
16-bit programming
m
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PROGRAMMING
DATA - - {
I
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t---;-tsu(DAO)
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--, L--th(D)
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_______~I______~I
6-142
I
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1--1
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tw(E)
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____
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
Vee
II
!0
E---./0 It------~I~I-
I
-h ~ta(E)
II II
I
I
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--II-
tdis(G)--,
HOUSTON, TEXAS 77001
I
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..Jlr----::~
TMX27PC010
1,048,576·BIT PROGRAMMABLE READ·ONLY MEMORY
JANUARY 1988
o
Organization ... 128K x 8
o
Single 5-V Power Supply
o
Industry Standard 32-Pin Dual-In-line
Package
N PACKAGE
(TOP VIEW)
o All Inputs/Outputs Fully TTL Compatible
o
Static Operation (No Clocks, No Refresh)
A7
A6
A5
A4
A3
A2
A1
AD
o Max Access/Min Cycle Time
o
o
o
o
VCC ± 5%
VCC ± 10%
'27PC010-200
'27PC010-250
'27PC010-300
'27PC010-20
'27PC010-25
'27PC010-30
200 ns
250 ns
300 ns
8-Bit Output For Use in MicroprocessorBased Systems
32-Bit Programming (Four Bytes) and
Standard 8-Bit Programming
3-State Output Buffers
2
31
~
PGM
3
30
NC
4
29
5
28
A14
A13
6
27
26
A8
A9
8
25
A11
9
24
G
10
23
A1D
11
22
E
12
21
01
13
20
08
07
02
14
19
06
03
15
18
05
16
17
04
I---
en
VCC
7
GND
Power Saving CMOS Technology
oa:
c..
w
w
-o
-o
en
~
a:
c..
en
~
a:
..
c..
w
PIN NOMENCLATURE
o Uses TI's Innovative ACE (Advanced
Contactless EPROM) Technology for Noise
Immunity and Improved Reliability
o
400 mV Guaranteed DC Noise Immunity
with Standard TTL Loads
o
o
No Pull-Up Resistors Required
o
"i'""032
VPP
A16
A15
A12
Low Power Dissipation (VCC - 5.5 V)
-Active ... 220 mW Worst Case
-Standby ... 1.5 mW Worst Case
(CMOS-Input Levels)
AO-A16
Address Inputs
E
Chip Enable
G
Output Enable
GND
Ground
NC
No Connection
PGM
Program
01-08
Outputs
VCC
Vpp
5-V Supply
~
W
>
w
a:
c.
I-
CJ
12.~-V Power Supply t
::>
tOnly in program mode.
C
oa:
Operating Free-Air Temperature ... ooC to
70°C
c.
description
The TMX27PC01 0 series are 1,048,576-bit, one-time, electrically programmable read-only memories. These
devices are fabricated using CMOS technology for high speed and simple interface with MOS and bipolar
circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits. Each output
can drive one Series 74 TTL circuit without external resistors. The data outputs are three-state for connecting
mUltiple devices to a common bus. The TMX27PC01 0 is offered in a 600-mil dual-in-line plastic package
(N suffix) rated for operation from OOC to 70 o C.
Since these PROMs operate from a single 5-V supply (in the read mode), they are ideal for use in
microprocessor-based systems. One other (12.5 V) supply is needed for programming. All programming
signals are TTL level. For programming outside the system, existing PROM programmers can be used.
PRODUCT PREVIEW documents contain information
on products in the formative or design phase of
development. Characteristic data and other
~E:~~~~:t;~~sr:::~t ~~s~\na~~:I~'r ~~~~:~~~~~~~~::
products without notice.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Copyright
© 1988. Texas Instruments Incorporated
6-143
m
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:J:J
o
~
-o
(I)
"'a
:J:J
~
(I)
m
m
"'a
:J:J
o
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(I)
6-144
1MX27PC210
1,048,576-BI1 PROGRAMMABLE READ-ONLY MEMORY
JANUARY 1988
•
Wide-Word Organization ... 64K x 16
•
Single 5-V Power Supply
•
Operationally Compatible with Existing
Megabit EPROMs
•
40-Pin Dual-In-line Package
•
All Inputs and Outputs Fully TTL Compatible
(TOP VIEW)
•
Static Operation (No Clocks, No Refresh)
•
Max Access/Min Cycle Time
VCC ± 5%
'27PC210-200
'27PC210-250
'27PC210-300
VCC ± 10%
'27PC210-20
'27PC21 0-25
'27PC210-30
16-Bit Output for Use in Microprocessor
Systems
•
32-Bit Programming (Two 16-Bit Words)
and 16-Bit Programming
•
16 Seconds Typical Programming Time
o
Power Saving CMOS Technology
•
3-State Output Buffers
•
•
VCC
PGM
NC
A15
A14
A13
A12
All
Al0
A9
GN01
A8
A7
A6
A5
A4
A3
A2
Al
AO
016
015
014
013
012
011
010
09
GNOt
08
07
06
05
04
03
02
01
200 ns
250 ns
300 ns
•
•
N PACKAGE
G
(I)
::!
oa:
c..
w
w
o
( I)
::!
a:
c..
( I)
::!
o
a:
..
c..
w
$:
w
:>w
PIN NOMENCLATURE
Uses TI's Innovative ACE (Advanced
Contactless EPROM) Technology for Noise
Immunity and Improved Reliability
400 mV Guaranteed DC Noise Immunity
with Standard TTL Loads
Latchup Immunity of 250 mA on All Input
and Output Pins
•
No Pull-Up Resistors Required
•
Low Power Dissipation
-Active ... 220 mW Worst Case
-Standby ... 1.5 mW Worst Case
(CMOS-Input Levels)
•
Operating Free-Air Temperature ... ooC to
70°C
AO-A15
Address Inputs
E
G
Output Enable
GND
Ground
NC
No Connection
a:
Chip Enable
PGM
Program
01-016
Outputs
VCC
5-V Supply
Vpp
12.5-V Supplyt
0.
....
U
:::)
C
oa:
tPins 11 and 30 must be connected externally to ground.
tOnly in program mode.
description
The TMX27PC21 0 is a 1,048,576-bit, one-time, electrically programmable read-only memory. This device
is fabricated using CMOS technology for high speed and simple interface with MOS and bipolar circuits.
All inputs (including program data inputs) can be driven by Series 74 TTL circuits without the use of external
pull-up resistors and each output can drive one Series 74 TTL circuit without external resistors. The data
outputs are three-state for connecting multiple devices to a common bus. The TMX27PC21 0 is offered
in a dual-in-line plastic package (N suffix) rated for operation from OOC to 70°C.
PRODUCT PREVIEW documents contain information
on products in the formative or design phase of
development. Characteristic data and other
~~:::~::~g~srr::t dt~S~\na~~:I~'r ~~~:~~~~~~~::!:
products without notice.
Copyright © 1988. Texas Instruments Incorporated
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
6-145
0.
m
."
:::0
o
3:
en
."
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o
3:
en
m
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-
6-146
General··lnfOrmation . .
Alternate'Source Directories . .
Glossary/Timing 'Conventions/DataSheet Structure
Dynamic··.RAMs . .
Dyn~micRAM'Modules
..
. ····EPROMs/PROMsJEEPFlOMs . .
VLSI Memory Management Products . .
I· .
I·'
·Militttry Products . .
"Applic~tions "nformation .' . .
Qualitysl'ldReliabUity
Logic Symbols
M~chanical
Data
. ESDGuidelines
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s:
CD
3
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7-2
SN54ALS229A, SN74ALS229A
16
x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIES
02876. MARCH 1986-REVISED MAY 1986
o
Independent Asychronous Inputs and
Outputs
o
16 Words by 5 Bits Each
SN54ALS229A ... J PACKAGE
SN74ALS229A ... OW OR N PACKAGE
(TOP VIEW)
....
(I)
DE
•
Data Rates from Q to 30 MHz
•
Fall-Through Time ... 24 ns Typ
•
3-State Outputs
VCC
These aD-bit memories utilize Advanced LowPower Schottky technology and feature high
speed and fast fall-through times. They are
organized as 16 words by 5 bits each.
::J
"C
EMPTY + 2
FULL- 2
FULL
LOCK
00
01
02
03
04
GNO
description
(,)
.
o
c..
....c
UNCLK
EMPTY
00
01
02
03
Q4
CD
E
CD
C)
ca
c
ca
RST
:E
SN54ALS229A ... FK PACKAGE
SN74ALS229A ... FN PACKAGE
A FIFO memory is a storage device that allows
data to be written into and read from its array
at independent data rates. These FIFOs are
designed to process data at rates from 0 to 30
megahertz in a bit-parallel format, word by word.
~
o
(TOP VIEW)
E
CD
:E
N
+
N
>-
I
uh::
~ I~ UJ u ~
I u..u..O>UJ
....J....J
Data is written into memory on a low-to-high
transition at the load clock input (LOCK) and is
read out on a low-to-high transition at the unload
clock input (UNCK). The memory is full when the
number of words clocked in exceeds by 16 the
number of words clocked out. When the memory
is full, LOCK signals will have no effect. When
the memory is empty, UNCK signals have no
effect.
3
2
....I
>
1 20 19
4
18
5
17
6
16
7
15
14
8
..
(j)
UNCLK
01
02
9 1011 12 13
o::t Cllf- o::t C')
Clz(J)dd
Status of the FIFO memory is monitored by the
FULL, EMPTY, FULL - 2, and EMPTY + 2 output
flags. The FULL output will be low whenever the
memory is full, and high whenever not full. The
FULL - 2 output will be low whenever the
memory contains 14 data words. The EMPTY
output will be low whenever the memory is
empty, and high whenever it is not empty. The
EMPTY + 2 output will be low whenever 2 words
remain in memory.
c.:Ja:
A low level on the reset input (AST) resets the internal stack control pointers and also sets EMPTY low
and sets FULL, FULL - 2, and EMPTY + 2 high. The Q outputs are not reset to any specific logic level. The
first low-to-high transition on LOCK, after either a RST pulse or from an empty condition, will cause EMPTY
to go high and the data to appear on the Q outputs. It is important to note that the first word does not
have to be unloaded. Data outputs are noninverting with respect to the data inputs and are at high impedance
when the output enable input (OE) is low. OE does not affect the output flags. Cascading is easily
accomplished in the word-width direction, but is not possible in the word-depth direction.
PRODUCTION DATA documents contain information
current as of ,Publication date. Products conform to
these specifications per the terms of Texas
Instruments standard warranty. Production
processing does not necessarily include testing of all
parameters.
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © 1986. Texas Instruments Incorporated
7-3
SN54ALS229A, SN74ALS229A
. 16 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIES
logic symbol t
<
r-
FIF016X5
~
CTR
CT=O
RST
s:
CD
FULL
(CT=16)Gl
FULL-2
3
LOCK
-<
UNCK
o
s:
m
OE
m
00
::::I
CC
CD
01
3
CD
02
..
&.
04
03
::::I
r+
(4)
(18)
(1)
(5)
(6)
1(+/C2)
ErJiiiTY+2
3-
EMPTY
EN4
(16)
20
4'\7
(15)
(7)
(14)
(8)
(13)
(9)
(12)
00
01
02
03
04
""C
t This symbol is in accordance with ANSIIIEEE Standard 91-1984 and IEC Publication 617-12. The symbol is functionally accurate but
C
does not show the details of implementation; for these, see the logic diagram. The symbol represents the memory as if it were controlled
by a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is O.
()
r+
tn
7-4
TEXAS
"I}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ALS229A, SN74ALS229A
16
x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIES
logic diagram (positive logic)
OE
(1)
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RING COUNTER
CTR DIV 16 1
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c..
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WRITE
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10
11
12
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14
15
16
E
(1)
UNCK
16
~
RING COUNTER
CTR DIV 16
1
en
>
2
3
READ
ADDRESS
RST
(111
. _ _ - - - - - - - + - H l K l CT=l
.....I
-
9
10
11
12
13
14
15
16
(161
00
:~~: ~~
(131
(121
16
16
COMP
P=O t - - - - - - f - - - - - - - -....
(171
o
03
04
P=0+2
(31
P=0-2
EMPTY
t---.--I
t-----j--_e_--t
121
(191
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ruu:
FULL-2
E"MPfY"+2
7-5
SN54ALS229A, SN74ALS229A
16 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIES
timing diagram
<
....
~
~
I
s:
(1)
3
o
UNCK--~~--~--------~
-<
QO-Q3
s:m
INVALID
WORD 1
WORD 1
EMPTY
:::s
m
cc
(1)
I
EMPTY+2----~--~~~~---+--------~L__Jr-------------~1- - - - - - - - - - - - - - -
PUiLL-----+----~----------------~:--------------------~----------------------------------------~~
3
(1)
...
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FULL-2----~----~-----------------+I----------------~~---------------------------,L__J
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c.
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INITIALIZE
POINTERS
LOAD
W1
I
UNLOAD
W2
I
J
FULL
EMPTY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee .... __ ............................................... _ ... 7 V
Input voltage ......................................... _ . . . . . . . . . . . . . . . . . . .. 7 V
Voltage applied to a disabled 3-state output .................................... " 5.5 V
Operating free-air temperature range: SN54ALS229A ..................... - 55°C to 125°C
SN74ALS229A ............ _ ............ ooe to 70°C
Storage temperature range ...... _ ............................... _ .. - 65°C to 150°C
recommended operating conditions
SN54ALS229A
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
fclock
Clock frequency
7-6
Pulse duration
tsu
Setup time
th
Hold time
TA
Operating free-air temperature
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
2
2
0.8
Q outputs
-1.0
-1.6
Status flags
-0.4
-0.4
12
24
4
8
Q outputs
Status flags
LOCK
0
25
0
30
UNCK
0
25
0
30
20
15
10
LOCK high
25
20
UNCK low
15
10
UNCK high
25
20
10
10
IRST (inactive) before LOCKt
5
5
I Data after LOCKt
5
5
-55
TEXAS
-'!}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
V
V
mA
mA
MHz
15
LOCK low
I Data before LOCKt
UNIT
V
0.8
RST low
tw
SN74ALS229A
MIN
125
0
ns
ns
ns
70
°C
SN54ALS229A, SN74ALS229A
16
x 5 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORIES
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VCC = 4.5 V.
VIK
Status flags
VOH
SN54ALS229A
MIN Typt MAX
TEST CONDITIONS
II = -18 mA
-1.2
VCC = 4.5 V to 5.5 V. 10H = -0.4 mA
VCC = 4.5 V.
Q outputs
Q outputs
VOL
Status flags
SN74ALS229A
MIN Typt MAX
VCC- 2
2.4
3.3
10H = -1 mA
VCC = 4.5 V.
10H = -2.6 mA
VCC = 4.5 V.
IOL=12mA
VCC = 4.5 V.
10L = 24 mA
VCC = 4.5 V.
10L = 4 mA
VCC = 4.5 V.
10L = 8 mA
-1.2
t/)
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.
V
"C
o
VCC- 2
2.4
0.25
0.4
0.25
0.4
3.2
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
V
10ZH
VCC = 5.5 V.
Vo = 2.7 V
20
20
/lA
VCC = 5.5 V.
Vo = 0.4 V
-20
- 20
/lA
VCC = 5.5 V.
VI = 7 V
0.1
0.1
mA
IIH
VCC = 5.5 V.
VI = 2.7 V
20
20
IlL
VCC = 5.5 V.
VI = 0.4 V
-0.2
-0.2
/lA
mA
lOt
VCC = 5.5 V.
Vo = 2.25 V
-112
mA
ICC
VCC = 5.5 V
140
mA
-112
95
-30
150
95
c..
V
10ZL
II
-30
....CJ
UNIT
~
o
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Q)
~
Cii
t All typical values are at VCC = 5 V. T A = 25°C.
t The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current. lOS.
....I
>
switching characteristics (see Note 1)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
Vcc = 5 V.
VCC - 4.5 V to 5.5 V.
CL - 50 pF.
R1 = 50011.
R1 - 50011.
UNIT
R2 - 50011.
R2 - 50011.
TA - 25°C
TA - MIN to MAX
MIN
f max
CL - 50 pF.
'ALS229A
TYP MAX
SN54ALS229A
MIN
MAX
SN74ALS229A
MIN
MAX
LDCK
25
30
UNCK
25
30
MHz
tpd
LDCKi
Any Q
24
47
7
54
7
50
ns
tpd
UNCKi
Any Q
19
29
9
35
9
33
ns
tPLH
LDCKi
EMPTY
18
26
9
32
9
30
ns
tpHL
UNCKi
EMPTY
18
25
9
32
9
29
ns
RSH
EMPTY
15
21
6
26
6
24
ns
tpd
LDCKi
EMPTY +2
23
33
10
40
10
38
ns
tpd
UNCKi
EMPTY+2
20
29
9
38
9
35
ns
RSH
EMPTY +2
20
28
9
35
9
33
ns
tpd
LDCKi
FULL-2
23
33
10
40
10
38
ns
tpd
UNCKi
FULL- 2
20
29
9
38
9
35
ns
RSH
FULL- 2
20
28
9
35
9
33
ns
tpHL
tPLH
tpLH
tpHL
LDCKi
FULL
21
28
10
35
10
33
ns
tPLH
UNCKi
FULL
17
23
8
29
8
27
ns
tpLH
RSH
FULL
18
27
8
33
8
31
ns
ten
OEi
Q
8
13
1
16
2
15
ns
tdis
OE~
Q
8
14
2
20
2
17
ns
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-7
7-8
16
x 4 ASYNCHRONOUS
SN54ALS232A, SN74ALS232A
FIRST·IN FIRST·OUT MEMORIES
02876, OCTOBER 19B5-REVISED APRIL 1986
•
Independent Asynchronous Inputs and
Outputs
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•
SN54ALS232A ... J PACKAGE
SN74ALS232A ... 0 OR N PACKAGE
(TOP VIEW)
DE
FULL
LDCK
DO
D1
D2
D3
GND
16 Words by 4 Bits Each
•
Data Rates from 0 to 30 MHz
•
Fall-Through Time ... 24 ns Typ
•
3-State Outputs
....CJen
VCC
UNCK
::s
..
"C
EMPTY
o
00
01
02
03
Q.
....c:::
Q)
E
Q)
RST
en
ca
c:::
ca
SN54ALS232A ... FK PACKAGE
SN74ALS232A ... FN PACKAGE
description
:E
(TOP VIEW)
These 64-bit memories use Advanced LowPower Schottky technology and feature high
speed and fast fall-through times. They are
organized as 16 words by 4 bits each.
A FIFO memory is a storage device that allows
data to be written into and read from its array
at independent data rates. These FIFOs are
designed to process data at rates from 0 to 30
megahertz in a bit-parallel format, word by word.
Data is written into memory on a low-to-high
transition at the load clock input (LDCK) and is
read out on a low-to-high transition at the unload
clock input (UNCK). The memory is full when the
number of words clocked in exceeds by 16 the
number of words clocked out. When the memory
is full, LDCK signals have no effect on the data
residing in memory. When the memory is empty,
UNCK signals have no effect.
I~
LDCK
DO
NC
D1
D2
~
~
uu
w U uz
oz>:::>
4
o
18
EMPTY
17
00
NC
01
02
16
15
14
E
Q)
:E
en
.....
>
9 1011 12 13
C"'l C
If-
U
C"'l
CZZUlO
(!)
a:
NC-No internal connection.
Status of the FIFO memory is monitored by the FULL and EMPTY output flags. The FULL output will be
low when the memory is full, and high when the memory is not full. The EMPTY output will be low when
the memory is empty, and high when it is not empty.
A low level on the reset input (RST) resets the internal stack control pointers and also sets EMPTY low
and sets FULL high. The outputs are not reset to any specific logic levels. The first low-to-high transition
on LDCK, either after a RST pulse or from an empty condition, will cause EMPTY to go high and the data
to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Data
outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable
input (OE) is low. OE does not affect either the FULL or EMPTY output flags. Cascading is easily
accomplished in the word-width direction, but is not possible in the word-depth direction.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~a{~:1~1a ~~:~~~ti~; ~~o~:~:~:t:~~s not
Copyright © 1985, Texas Instruments Incorporated
TEXAS . .
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
7-9
SN54ALS232A, SN74ALS232A
16 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIES
logic symbol t
FIFO
16X4
CTR
<
I"'"
RST
~
LOCK
UNCK
S
(1)
3
FULL
EMPTY
3-
OE
o
DO
-<
20
(12)
01
02
S
03
D)
(6)
(11)
(7)
(10)
00
01
02
03
:::::I
D)
cc
(1)
3
(1)
:::::I
....
tThis symbol is in accordance with ANS)/IEEE Standard 91 - 1984 and lEe Publication 617- 12. The symbol is functionally accurate but
does not show the details of implementation; for these, see the logic diagram. The symbol represents the memory as if it were controlled
by a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content leT) is O.
logic diagram (positive logic)
...
."
o
RING
COUNTER
c.
c:
CTR DIV 161
2
(")
....
en
3
4
5
6
7
WRITE
~
ADDRESS 10
11
12
13
CT=1
14
15
16
RST-(~9~)--------________________~
READ
ADDRESS
~--------------~'-<:I CT=1
DO (4)
01 (5)
(13) 00
(12) 01
~~ :~:
(11) 02
(10) 03
COMP
16
P=O~~---------------4~
~___+-~~~--------------------~(1~4~) EMPTY
P=0+1
D-------..JL.~
o
P=0-1b------------Q
~----,1b----------------------~(~2~) FULL
Pin numbers shown are for D, J, and N packages.
7-10
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ALS232A, SN74ALS232A
16 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIES
timing diagram
RST
--.J
....Utn
I
I
:
I
:::s
r-fl-fL--
LOCK
I
I
"'C
...o
I
c..
....C
UNCK
(1)
QO-Q3
E
(1)
WORD 1
WORD 1
C)
ca
c
ca
L-J
:?!
I
I
L-J
FULL
~
o
I
INITIALIZE
POINTERS
LOAD
Wl
EMPTY
UNLOAD
E
FULL
(1)
W2
:?!
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, Vee _ . . . . . . . . . . .
Input voltage ... _ . . . . . . . . . . . . .
Voltage applied to a disabled 3-state
Operating free-air temperature range:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
output . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . .. 5.5 V
SN54ALS232A . . . . . . . . . . . . . . . . . . . . . - 55°C to 125°C
SN74ALS232A . . . . . . . . . . . . . . . . . . . . . . . . . DoC to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
en
..J
>
..
recommended operating conditions
SN54ALS232A
MIN NOM MAX
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
fclock
tw
tsu
Clock frequency
Pulse duration
Setup time
th
Hold time
TA
Operating free-air temperature
4.5
5
5.5
2
SN74ALS232A
MIN NOM MAX
4.5
outputs
FULL, EMPTY
Q
outputs
FULL, EMPTY
0.8
-1.6
-0.4
-0.4
12
24
0
25
UNCK
0
25
RST low
20
8
0
30
0
30
LDCK low
15
10
25
20
UNCK low
15
10
UNCK high
25
20
Data before LDCKt
10
10
5
5
Data after LDCKt
TEXAS
.Jt!p
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
V
mA
mA
MHz
ns
ns
ns
5
5
-55
V
15
LDCK high
RST (inactive) before LDCKt
UNIT
V
-1
4
LDCK
5.5
2
0.7
Q
5
125
0
70
DC
7-11
SN54ALS232A, SN74ALS232A
16 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIES
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
10ZH
VCC
10ZL
VCC
II
VCC
IIH
VCC
IlL
10;
VCC
VCC
= 4.5
= 4.5
= 4.5
= 4.5
= 4.5
= 4.5
= 4.5
= 4.5
= 5.5
= 5.5
= 5.5
= 5.5
= 5.5
= 5.5
ICC
Vec
=
VCC
VIK
FULL, EMPTY
VOH
VCC
VCC
Q outputs
VCC
VCC
Q outputs
VCC
VOL
VCC
FULL, EMPTY
..."0
o
Co
C
~
VCC
V,
II
=
MIN
= -0.4 mA
= -1 mA
10H = -2.6 mA
10L = 12 mA
10L = 24 mA
10H = 4 mA
10L = 8 mA
Vo = 2.7 V
Vo = 0.4 V
VI = 7 V
VI = 2.7 V
VI = 0.4 V
Vo = 2.25 V
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
MIN
-1.2
-18 mA
V to 5.5 V, 10H
V,
10H
V,
SN74ALS232A
Typt
MAX
SN54ALS232A
Typt
MAX
TEST CONDITIONS
Vee- 2
2.4
-1.2
UNIT
V
Vee- 2
3.3
V
2.4
0.25
0.25
-30
0.4
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
V
20
20
-20
-20
p.A
0.1
0.1
mA
p.A
20
20
p.A
-0.2
'-0.2
mA
-112
75
5.5 V
0.4
3.2
-30
75
125
-112
mA
125
mA
t All typical values are at VCC = 5 V, TA = 25°C.
; The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.
C/)
_ s w i t c h i n g characteristics (see Note 1)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
Vcc - 5 V,
vcc - 4.5 V to 5.5 V,
CL - 50 pF,
R1 - 500 n,
CL - 50 pF,
R2 - 500
R2 - 500
'ALS232A
TYP MAX
SN54ALS232A
MIN
MAX
UNIT
SN74ALS232A
MAX
MIN
LDCK
40
25
30
UNCK
40
25
30
MHz
tpd
LDCKi
Any Q
30
40
4
50
4
46
tpd
UNCKi
Any Q
20
27
7
35
7
31
ns
tpLH
LDCKi
EMPTY
17
23
8
29
8
26
ns
tpHL
UNCKi
EMPTY
19
24
10
36
10
29
ns
tpHL
RSn
EMPTY
13
18
5
23
5
20
ns
tpHL
LDCKi
FULL
21
26
10
35
10
31
ns
tpLH
UNCKi
FULL
17
23
8
28
8
25
ns
tpLH
RSn
FULL
18
24
8
31
8
28
ns
ten
OEi
Q
7
12
1
16
1
14
ns
tdis
OE~
Q
10
16
2
23
2
21
ns
NOTE 1; Load circuit and voltage waveforms are shown in Section 1.
TEXAS
7-12
n,
n,
TA - MIN to MAX
TA - 25°C
MIN
f max
R1 - 500
n,
-Ij}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ns
SN54ALS233A, SN74AlS233A
16 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIES
D2876, JANUARY 1986 - REVISED MAY 1986
o
Independent Asynchronous Inputs and
Outputs
o
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
o
16 Words by 5 Bits Each
o
Data Rates from 0 to 30 MHz
o
Fall· Through Time ... 24 ns Typ
o
3-State Outputs
SN54ALS233A ... J PACKAGE
SN74ALS233A ... DW OR N PACKAGE
(TOP VIEW)
OE
(I)
U
EMPTY+ 1
FULL - 1
FULL
LDCK
DO
D1
D2
D3
D4
GND
description
..,
VCC
:::l
"C
UNCK
...o
a..
EMPTY
QO
Q1
Q2
Q3
Q4
RST
SN54ALS233A ... FK PACKAGE
SN74ALS233A ... FN PACKAGE
These aD-bit memories utilize Advanced LowPower Schottky technology and feature high
speed and fast fall-through times. They are
organized as 16 words by 5 bits each.
~
(TOP VIEW)
I~I~ ~
A FIFO memory is a storage device that allows
data to be written into and read from its array
at independent data rates. These FIFOs are
designed to process data at rates from 0 to 30
megahertz in a bit-parallel format, word by word.
3
LDCK
DO
D1
D2
D3
Data is written into memory on a low-to-high
transition at the load clock input (LOCK) and is
read out on a low-to-high transition at the unload
clock input (UNCK). The memory is full when the
number of words clocked in exceeds by 16 the
number of words clocked out. When the memory
is full, LOCK signals will have no effect. When
the memory is empty, UNCK signals have no
effect.
2
o
E
+
Q)
f-
>ua..
u~
>w
:!
..
....Cii
>
1 20 19
UNCK
4
18
5
17
EMPTY
6
16
7
15
QO
Q1
Q2
14
8
9 1011 12 13
<:t Cl
ClZ
(!)
If-U>dd
<:t
C")
a:
Status of the FIFO memory is monitored by the
FULL, EMPTY, FULL-1, and EMPTY + 1 output
flags. The FULL output will be low whenever the
memory is full, and high whenever not full. The
FULL - 1 output will be low whenever the
memory contains 15 data words. The EMPTY
output will be low whenever the memory is
empty, and high whenever it is not empty. The
EMPTY + 1 output will be low whenever one
word remains in memory.
A low level on the reset input (RST) resets the internal stack control pointers and also sets EMPTY low
and sets FULL, FULL - 1, and EMPTY + 1 high. The Q outputs are not reset to any specific logic level. The
first low-to-high transition on LOCK, after either a RST pulse or from an empty condition, will cause EMPTY
to go high and the data to appear on the Q outputs. It is important to note that the first word does not
have to be unloaded. Oata outputs are noninverting with respect to the data inputs and are at high impedance
when the output enable input (OE) is low. OE does not affect the output flags. Cascading is easily
accomplished in the word-width direction, but is not possible in the word-depth direction.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~a{~~I~~~ ~!~~~~ti~r fl~o~:~:~it:ros~S not
Copyright © 1986, Texas Instruments Incorporated
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS. TEXAS 75265
7-13
SN54ALS233A, SN74ALS233A
16 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIES
logic symbol t
<
r-
FIFD16X5
~
CTR
RST
S
(1)
3
FiJIT
(CT=16)Gl
FiJTi::::j
LOCK
o
UNCK
-<
S
D)
DE
:::l
00
D)
co
(1)
01
3(1)
02
03
,..:::l
a
CT=O
04
(4)
(18)
(1)
(5)
(6)
1(+/C2)
EMPTY+l
3-
EMPTY
EN4
20
4V'
(16)
(15)
(7)
(14)
(8)
(13)
(9)
(12)
00
01
02
03
04
."
C.
r::::
,..
tThis symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. The symbol is functionally accurate but
does not show the details of implementation; for these, see the logic diagram. The symbol represents the memory as if it were controlled
by a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is O.
(")
en
7-14
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265
SN54ALS233A, SN74ALS233A
16
x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIES
logic diagram (positive logic)
OE
(1)
...
t/)
(J
::l
RING COUNTER
CTR DIV 16 1
"C
o...
0..
...c:
CD
E
CD
WRITE
ADDRESS
CT=l
C')
ca
c:
ca
10
11
12
13
14
15
16
:i!
~
o
E
CD
:i!
RING COUNTER
CTR DIV 16
1
..
en
>
2
..J
READ
ADDRESS
'RsT
(11)
....- - - - - - 4 -.....0
00
01
02
~!
CT=l
9
10
11
12
13
14
15
16
(5)
(16)
00
:~:I ~~
(6)
:~I
(13)
(12)
(9)
03
04
COMP
P=Or-------4----------------t
(17)
P=O+ll---__
EMPTY
~
o
(3)
P=O-l r - - - - - I - - - -....---l
FULL
(2)
~
(19)
EMPTY+1
Pin numbers are for D, J, and N packages.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-15
SN54ALS233A, SN74ALS233A
16 X 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIES
timing diagram
<
r-
LOCK
~
3:
CD
3
o
-<
00·03 ~1:u.NV~A~LI"D~\-.--:W:.:..:D:..:..:RD:..1.:......-_~.:..:.;.;;:..:...."-.:.:..:..:.;.:-...;..) ",,",",,,",~.,--_ _ _ _ _W_O_RD_l_ _ _....;-_,,-~ ,"--=--I ..--=-_
3:
D)
::::J
D)
CC
CD
3
L-1
L..JL..J
CD
...::::J
I
I
.
"'a
o
c.
I
INITIALIZE LOAD
POINTERS
W1
c
S
UNLOAD
FULL
EMPTY
W2
(I)
_
abSo~~:p~:~::: ~a;;ss .over. operati.ns. free:air temperature. range (Unlessother~ise. noted) 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54ALS233A .... . . . . . . . . . . . . . . . .. - 55 DC to 125 DC
SN74ALS233A ......................... oDe to 70 De
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 DC to 150 DC
7-16
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
16
x 5 ASYNCHRONOUS
SN54ALS233A, SN74ALS233A
FIRST·IN FIRST·OUT MEMORIES
recommended operating conditions
SN74ALS233A
SN54ALS233A
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
10H
High-level output current
10L
Low-level output current
fclock
Clock frequency
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
V
0.8
V
outputs
th
Hold time
Operating free-air temperature
-1
-1.6
-0.4
-0.4
12
24
Status flags
4
8
LOCK
0
25
0
30
UNCK
0
25
0
30
U)
Co)
:::::s
..o
"C
Q.
....C
mA
CD
mA
E
CD
MHz
C)
ca
c
ca
15
RST low
20
LOCK low
15
10
LOCK high
25
20
UNCK low
15
10
UNCK high
25
20
Data before LDCKi
10
10
5
5
Data after lDCKi
....
V
outputs
Q
RST inactive before lDCKi
TA
2
Status flags
Setup time
tsu
MAX
0.7
Pulse duration
tw
NOM
2
Q
UNIT
MIN
5
125
~
o
E
CD
:E
iii
.....
ns
5
-55
:E
ns
ns
0
70
°c
>
electrical characteristics over recommended operating free-air temperature range (unless otherwise·. .
noted)
PARAMETER
VCC = 4.5 V,
VIK
Status flags
VOH
Q outputs
Q outputs
VOL
Status flags
SN54ALS233A
Typt
MAX
TEST CONDITIONS
MIN
-1.2
II = -18 mA
VCC = 4.5 V to 5.5 V, IOH = -0.4 mA
VCC = 4.5 V,
IOH = -1 mA
VCC = 4.5 V,
IOH = -2.6 mA
VCC = 4.5 V,
IOl= 12mA
VCC = 4.5 V,
IOL = 24 mA
VCC = 4.5 V,
IOl = 4 mA
VCC = 4.5 V,
10l = 8 mA
SN74ALS233A
Typt
MAX
MIN
VCC- 2
2.4
3.3
-1.2
0.25
V
VCC-2
V
2.4
0.25
UNIT
0.4
0.4
3.2
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
V
IOZH
VCC = 5.5 V,
Vo = 2.7 V
20
20
JlA
IOZl
II
VCC = 5.5 V,
Vo = 0.4 V
-20
-20
VCC = 5.5 V,
VI = 7 V
0.1
0.1
JlA
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
20
III
VCC = 5.5 V,
VI = 0.4 V
-0.2
-0.2
JlA
mA
lOt
VCC = 5.5 V,
Vo = 2.25 V
-112
mA
ICC
VCC = 5.5 V
133
mA
-30
-112
88
143
-30
88
t All typical values are at VCC = 5 V, T A = 25°C.
t The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.
TEXAS
"J1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
7-17
SN54ALS233A, SN74ALS233A
16 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIES
switching characteristics (see Note 1)
<
r~
PARAMETER
eL - 50 pF.
FROM
TO
R1 - 500 fl.
R1 - 500 fl.
(OUTPUT)
R2 - 500 fl.
R2 - 500 fl.
TA - 25°e
'ALS233A
MIN
o
-<
~
Vec - 4.5 V to 5.5 V.
CL - 50 pF.
(INPUT)
3:
CD
3
3:
Vee - 5 V.
f max
C»
LDCK
TYP
MAX
MIN
40
UNCK
UNIT
TA - -MIN to MAX
SN54ALS233A
SN74ALS233A
MAX
25
40
MIN
MAX
30
MHz
::10
25
tpd
LDCKi
Any Q
24
44
7
52
7
48
ns
tpd
UNCKi
Any Q
19
29
9
35
9
33
ns
ns
C»
tpLH
LDCKi
EMPTY
18
25
9
30
9
28
CD
tpHL
UNCKi
EMPTY
18
25
9
33
10
30
ns
tpHL
RSn
EMPTY
13
19
6
24
6
22
ns
cc
3
CD
r+
~
tpd
LDCKi
EMPTY + 1
22
31
10
40
10
37
ns
"tJ
tpd
UNCKi
EMPTY + 1
22
31
9
40
10
37
ns
o
c.
c(')
tpLH
RSn
EMPTY + 1
19
27
8
32
8
31
ns
tpd
LDCKi
FULL-1
23
32
11
38
12
36
ns
tpd
UNCKi
FULL-1
23
32
11
39
12
36
ns
tpLH
RSn
FULL-1
20
28
10
34
11
32
ns
tpHL
LDCKi
FULL
21
28
10
35
12
33
ns
tpLH
UNCKi
FULL
17
24
8
29
9
27
ns
tpLH
RSn
FULL
18
27
8
32
9
30
ns
ten
OEt
Q
8
13
1
16
2
15
ns
tdis
OEt
Q
8
12
2
20
2
17
ns
..
r+
t/)
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
7-18
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ALS234, SN74ALS234
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
D2958. OCTOBER 1986
•
Asynchronous Operation
•
Organized as 64 Words of 4 Bits
•
Data Rates from 0 to 30 MHz
•
3·State Outputs
•
Similar to MMI67401 B with Higher Speed
and 3·State Outputs
•
Dependable Texas Instruments Quality
and Reliability
SN54ALS234 ... J PACKAGE
SN74ALS234 ... D OR N PACKAGE
...
(TOP VIEW)
OE
)R
t/)
(,)
~
VCC
SH)FT OUT
OR
SHIFT IN
00
01
02
03
"C
o...
c..
00
01
02
03
GNO
...c
Q)
E
Q)
RST
C)
description
CO
C
CO
SN54ALS234 ... FK PACKAGE
SN74ALS234 ... FN PACKAGE
The SN54ALS234 and SN74ALS234 are
256-bit memories utilizing Advanced Low-Power
Schottky IMPACT'M Technology. They feature
high speed with fast fall-through times and are
organized as 64 words by 4 bits.
:2:
>
...
o
(TOP VIEW)
I-
::J
o
E
Q)
AFIFO memory is a storage device that allows
data to be written into and read from its array
at independent data rates. The ' ALS234 is
designed to process data at rates from 0 to 30
megahertz in a bit-parallel format, word by word.
Data is written into memory on the rising edge
of the Shift In input. When Shift In goes low, the
first data word ripples through to the output (see
Figure 1). As the FIFO fills up, the data words
stack up in the order they were written. When
the FIFO is full, additional Shift In pulses have
no effect. Data is shifted out of memory on the
falling edge of the Shift Out input (see Figure 2).
When the FIFO is empty, additional Shift Out
pulses have no effect. The last data word
remains at the outputs until a new word falls
through or RST goes low.
:2:
3
SHIFT IN
2
(j)
..
1 20 19
18
4
..J
>
OR
00
5
17
00
NC
6
16
NC
01
02
7
15
8
14
01
02
9 1011 12 13
II-
C') Cl U
C')
ClzZ(J)O
t9
a:
NC - No internal connection
Status of the' ALS234 FIFO memory is monitored by the Output Ready (OR) and Input Ready (lR) flags.
When the OR flag is high, valid data is available at the outputs. The OR flag is low when Shift Out is high
and will stay low when the FIFO is empty. The IR status flag is high when the inputs are ready to receive
more data. The IR flag is low when Shift In is high and stays low when the FIFO is full.
When the FIFO is empty, input data is shifted to the output automatically when Shift In goes low. If Shift
Out is held high during this time, the OR flag pulses high indicating valid data at the outputs (see Figure 3).
When the FIFO is full, data can be shifted in automatically by holding Shift In high and taking Shift Out
low. A propagation delay after Shift Out goes low, IR will go high. If Shift In is still high when IR goes
high, data at the inputs are automatically shifted in. Since IR is normally low when the FIFO is full and
Shift In is high, only a high-level pulse is seen on the IR output (see Figure 4).
IMPACT is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~~~~i~ar::1~1~ ~!~~~~tigf ~lo::::~M~~s not
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © 1986. Texas Instruments Incorporated
7-19
SN54ALS234, SN74ALS234
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
description (continued)
The FIFO must be reset after power up with a low-level pulse on the Master Reset input (RST). This sets
Input Ready OR) high and Output Ready (OR) low signifying that the FIFO is empty. Resetting the FIFO
sets the outputs to a low logic level (see Figure 1). If Shift In is high when RST goes high, the
input data is shifted in and IR goes low and remains low until Shift In goes low. If Shift In goes low before
RST goes high, the input data will not be shifted in and IR goes high. Data outputs are noninverting with
respect to the data inputs and are at high impedance when Output Enable (OE) is high. OE does not affect
the IR and OR outputs.
<
r~
3:
CD
3
o
-<
The SN54ALS234 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ALS234 is characterized for operation from OOC to 70°C.
3:
Do)
~
Do)
cc
logic symbol t
CD
3CD
~
....
FIFO 64 x 4
CTR
(3)
.
SHIFT IN
3CT>0
(CT>0)G4
"'C
o
c.
c
n
....
-
(14)
(2)
2CT<64
t/)
OR
IR
(CT<64)G5
00
(4)
01
(5)
10
..,6"
~;......------.;;.;;....:..t
(13) 00
(12)
02 (6)
01
(11) 02
03
(10) 03
(7)
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617·12.
functional block diagram
~----~~~~OO
00
01
01
02
02
03
03
SHIFT
OUT
IR
SHIFT
IN
OR
RST---'~---4~----------~~----------~~----------~
Pin numbers shown are for D. J. and N packages.
7-20
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ALS234, SN74ALS234
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
logic diagram (positive logic)
...
---5~---------------------------------,
OE--------------------------------WORD 63
WORD 64
DO
WORD 2
WORD 3
U)
WORD 1
(J
:::I
.
"C
o
c..
c
Go)
E
Go)
en
l:H>-+-C)O- 00
~
I
c:(
D1-:--------------:------:----------~5_---------I------1-----------:----
c
02-
: :
WORDS 4-62
: :
SAME_A~~~Z
R::-
I
01
+-----02
' +--Q3
f:::l
...
a.
f:::l
o
~
c:(
C
C)
ca
c
ca
~
~
o
E
Go)
~
L---4--------SHIFT OUT
L--------------------OR
SHIFT IN ___+_---oJ '-~~-----------------
-
-
-I~'
-
- - ---------------------------------IR
timing diagram
RST
l-.J
..
Cii
....I
>
I
I
SHIFT IN
03-00
SHIFT OUT
~
:
I
--+I----!I
I
~ W1 @
~II
I
I
I
I
I
I
I
I
I
I
I
I
03-00
I
W2
i
~g4&kK*W%%kI W1 WI W2 w;I~w63f@1w64~ W1 W%&
I
L-J
I
~
I
I
.,.,
I
I WORD 2
I
I
~
I
I
I
I
I
I
I
I
I
I
I
I
r IL - L·_ _+-I_ _ _ _ I
I
WORD 2
,
I
,
I
WORD 3
~
LJrl~____~n~_~
U-I
I
I
IR
I
OR=j
I
I
I
I
I
I
I
CLEAR
SHIFT IN
W1
SHIFT OUT EMPTY
W2
FULL
t The last data word shifted out of the FIFO remains at the output until a new word falls through or a RST pulse clears the FIFO.
t While the output data is considered valid only when the OR flag is high, the stored data remains at the output. Any additional words
written into the FIFO will stack up behind the first word and will not appear at the output until Shift Out is taken low.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS. TEXAS 75265
7-21
SN54ALS234, SN74ALS234
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
I
<
r
14- tsu---+l
--=-_______.:1---"""-_____
~
s:
I
CD
3
03-00
o
-<
s:
Q)
I
I
I
I+-tsU---+/4-th~ I
~
)I(~_____
I
I
I
If-tPLH~
I
j4-tPHL --.I
FULL
I
I
I
I
Q)
CQ
CD
I
OR
::::s
I
I
EMPTY
I
..
r+
I
03-00
~tPLH-+I
r
1------
~tpd--~~I
j4-tpd--+i
"tJ
I
I
jf--tPLH---.~1
jf-tPHL-+!
3
CD
I
I
...JX-.. .-_-_-_-_-_-
IR
::::s
o
c..
c
(")
I
SHIFT IN _ _
--~--*-
*----
NOTE: SHIFT OUT is low
r+
U)
FIGURE 1. MASTER RESET AND DATA IN WAVEFORMS
SHIFT OUT
I
I
OR
j4--- tpLH
IR
-----+I
_ _ _ _F_U_LL_ _ _~I-----~~I------------
I
~ td(SOL-OX)
03-00
==:)~I--~K_~~~~
~.----------~»~~~~~~-L. J
14- tpd ----+I
tdiS~
OE
~ten
~~--~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
NOTE: SHIFT IN is low
FIGURE 2_ DATA OUT WAVEFORMS
7-22
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS. TEXAS 75265
SN54ALS234, SN74ALS234
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
03-00
t su
SHIFT IN
~
~
+
en
th-...j
~
CJ
~
I
"C
...
0
c..
SHIFT OUT
--.J
r::
Go)
I
I
\+OR
~
tpLH
EMPTY
---+I+I
I
~ td(OV-ORHI
03-00
E
Go)
tw---+l
C)
I
ca
ca
r::
::2:
...>-
>K
INVALID
0
E
Go)
::2:
FIGURE 3. DATA FALL THROUGH WAVEFORMS
Cii
SHIFT OUT
...J
>
I
I
SHIFT IN
--.J
I
~tPLH-+-tw~
IR
03-00
I
FULL
I
FULL
-
~
-AX
FIGURE 4. AUTOMATIC DATA IN WAVEFORMS
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-23
I
SN54ALS234, SN74ALS234
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3·state output. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free·air temperature range: SN54ALS234 . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
SN74ALS234 .......................... ooC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
<
r~
s:
CD
3
o
-<
recommended operating conditions
s:m
SN74ALS234
SN54ALS234
:s
m
Vee
Supply voltage
CD
VIH
High-level input voltage
VIL
Low-level input voltage
10H
High-level output current
CD
3CD
...
:s
"'0
a
c.
c
...
Low-level output current
fclock
elock frequency
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
V
0.8
0.8
V
2
Pulse duration
Q outputs
-1
-2.6
-0.4
-0.4
Q outputs
12
24
IR and OR
4
8
30
high or low
RST low
tsu
Setup time before SHIFT IN 1
th
TA
Hold time. data after SHIFT IN 1
V
IR and OR
SHIFT IN or SHIFT OUT
tw
MAX
SHIFT IN or SHIFT OUT
n
t/)
NOM
2
IOL
high (inactive)
25
0
15
20
15
0
0
15
15
-55
125
mA
mA
MHz
ns
ns
17
19
Operating free-air temperature
0
17
Data
RS'f
UNIT
MIN
ns
0
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
Vee
VIK
Q
VOH
IR. OR
Q
VOL
IR. OR
SN54ALS234
Typt
MAX
TEST CONDITIONS
Vee
Vee
Vee
Vee
Vee
Vee
Vee
10ZH
Vee
10ZL
II
Vee
IIH
Vee
IlL
Vee
lo~
Vee
Vee
= 4.5 V.
= 4.5 V.
= 4.5 V.
= 4.5 V.
= 4.5 V.
= 4.5 V.
= 4.5 V.
= 4.5 V.
= 5.5 V.
= 5.5 V.
= 5.5 V.
= 5.5 V.
= 5.5 V.
= 5.5 V.
II
MIN
=
-18 mA
10H = -1 mA
10H = -2.6 mA
= -0.4 mA
= 12 mA
10L = 24 mA
10L = 4 mA
10L = 8 mA
Vo = 2.7 V
Vo = 0.4 V
VI = 7 V
VI = 2.7 V
VI = 0.4 V
Vo = 2.25 V
10H
10L
-1.2
2.4
3.3
2.5
3.4
0.25
0.25
Vee
=
5.5 V
-1.2
2.4
3.2
2.7
3.4
0.25
0.4
0.35
0.5
0.4
0.25
0.4
0.4
0.35
0.5
0.4
UNIT
V
V
V
20
20
/LA
-20
-20
0.1
0.1
/LA
mA
20
-0.1
-0.1
/LA
mA
-112
mA
-112
-30
100
155
IleeH
97
Ileez
103
IleeL
Ice
SN74ALS234
Typt
MAX
MIN
20
-30
100
145
152
97
142
158
103
148
mA
t All typical values are at Vee = 5 V. T A = 25°e.
~ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current. lOS.
7-24
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ALS234, SN74ALS234
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
switching characteristics (see Note 1)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
Vcc - 5 V.
vcc - 4.5 V to 5.5 V.
Cl - 50 pF.
Cl - 50 pF.
R1 - 500 fl.
R1 - 500 fl.
R2 - 500 fl.
R2 - 500 fl.
TYP
MAX
MIN
MAX
MIN
SHIFT IN
35
25
30
SHIFT OUT
35
25
30
tw t
IR high
15
7
8
tw+
OR high
19
td(QV-ORH)
Q valid before OR t
f max
td(SOL-QX)
6
Q valid after SHIFT OUT!
UNIT
::::s
"'C
MHz
CD
ns
C)
.
o
c..
....c:
TA - MIN to MAX
SN74ALS234
SN54ALS234
TA - 25°C
'AlS234
MIN
....enu
-5
12
-5
4
13
E
CD
as
c:
as
ns
8
7
9
MAX
12
4
ns
:E
ns
tpd
SHIFT IN !
Q
600
800
350
1200
350
1000
ns
tpHL
SHIFT IN t
IR
20
26
8
36
8
30
ns
tPLH
SHIFT IN!
IR
16
21
6
28
6
25
ns
tPLH§
SHIFT IN!
OR
600
800
350
1200
350
1000
ns
tod
SHIFT OUT!
Q
13
17
4
24
4
22
ns
tpHL
SHIFT OUT t
OR
23
27
7
39
7
33
ns
tpLH
SHIFT OUT!
OR
20
24
6
33
6
30
ns
tPLH§
SHIFT OUT!
IR
600
800
350
1200
350
1000
ns
tpHL
RST!
OR
22
26
10
40
10
34
ns
tpLH
RST
!
IR
17
21
6
31
6
27
ns
tpHL
RST!
Q
14
17
5
21
5
19
ns
tdis
OE t
Q
7
13
2
16
2
15
ns
ten
OE!
Q
6
12
2
15
2
13
ns
~
o
E
CD
:E
Cii
-I
..
>
t The IR output pulse occurs when the FIFO is full. Shift In is high. and Shift Out is pulsed (see Figure 4).
+ The OR output pulse occurs when the FIFO is empty. Shift Out is high. and Shift In is pulsed (see Figure 3).
§ Data throughput or "fall through" times
NOTE 1: Load circuit and voltage waveforms are shown in Section 1 of the LSI Logic Data Book. 1986.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-25
SN54ALS234. SN74ALS234
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
TYPICAL APPLICATION INFORMATION
IR
SI
00
01
02
03
IR
SI
00
01
02
03 RST
SI
00
01
02
03 RST
..
<
r-
SHIFT IN
SO
SO
OR
00
01
02
03
OUTPUT REAOY
SO
OR
00
01
02
03
MASTER RESET
FIGURE 5. 192-WORD BY 12-BIT EXPANSION
~
3:
3
CD
o
-<
3:
m
::::s
m
CQ
CD
3
CD
::::s
.....
..."'0
o
c.
c(')
.....
t/)
TEXAS •
7-26
SHIFT OUT
SO t-----4t---......- - - - OR J----+--,
00
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ALS235, SN74ALS235
64 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
02958. OCT08ER 1986
SN54ALS235 ... J PACKAGE
SN74ALS235 ... OW OR N PACKAGE
•
Asynchronous Operation
•
Organized as 64 Words of 5 Bits
•
Data Rates from 0 to 25 MHz
•
3-State Outputs
•
Dependable Texas Instruments Quality
and Reliability
(TOP VIEW)
The SN54ALS235 and SN74ALS235 are
320-bit memories utilizing Advanced Low-Power
Schottky IMPACTTM Technology. They feature
high speed with fast fall-through times and are
organized as 64 words by 5 bits.
::::I
..
"C
o
c.
...
QO
Q1
Q2
Q3
Q4
GNO
C
Q)
E
Q)
C)
ca
ca
RST
c
:?!
SN54ALS235 ... FK PACKAGE
SN74ALS235 ... FN PACKAGE
A FIFO memory is a storage device that allows
data to be written into and read from its array
at independent data rates. The ' ALS235 is
designed to process data at rates from 0 to 25
megahertz in a bit-parallel format, word by word.
Data is written into memory on the rising edge
of the Shift In input. When Shift In goes low, the
first data word ripples through to the output (see
Figure 1). As the FIFO fills up, the data words
stack up in the order they were written. When
the FIFO is full, additional Shift In pulses have
no effect. Data is shifted out of memory on the
falling edge of the Shift Out input (see Figure 2).
When the FIFO is emply, additional Shift Out
pulses have no effect. The last data word
remains at the outputs until a new word falls
through or RST goes low.
t/)
(J
ALMOST FULL/EMPTY
SHIFT OUT
OR
00
01
02
03
04
description
...
Vee
DE
HALF FULL
IR
SHIFT IN
~
o
(TOP VIEW)
E
Q)
:?!
(j)
....I
3
2
>
-
1 2019
SHIFT IN
4
18
00
01
02
03
5
17
6
16
7
15
8
14
9 1011 12 13
'0
(CT>0)G4
CTs8/CT~56
CT~32
2CT<64
(17)
(19)
(2)
(3)
OR
ALMOST FULL/EMPTY
HALF FULL
IR
(CT<64)GS
r+
tn
OE
DO
Dl
02
03
04
(6)
-'6'\7
(16)
(lS)
(7)
(14)
(8)
(13)
(9)
(12)
00
01
02
03
04
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
7-28
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ALS235, SN74ALS235
64 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
functional block diagram
OE
....CJ
U)
00
:::::I
.
"C
o
c.
01
FIFO
OUTPUT
STAGE
02
(13)
(12)
....c
03
G)
04
E
G)
tn
CO
C
CO
1--_......_~(..:....:18:..:..) SHIFT
CONTROL
LOGIC
IN
:2!
(17) OUT
I--~~-j..-..:---':"'OR
FLAG
CONTROL
LOGIC
1.-._ _ _ _ _ _ _ _ _
--l~--.:...(1......:..9) ALMOST FULL/EMPTY
~_ _ _ _ _ _ _ _ _ _ _ _~_ _~(2)
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
HALF FULL
..
7-29
SN54ALS235, SN74ALS235
64 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
. logic diagram (positive logic)
N
<
r-
sa
s:
I"l
X
II:
w
~
Z
Z
o
r;
3
o
Q
w
C
II:
:l
Z
o
3:
-<
s:
m
i=
z
o
N
I"l
"
C
II:
::::s
o
3:
CQ
CD
I"l
I"l
m
C
3CD
II:
o
3:
....::::s
.
""C
o
c.
c
~
..
C
II:
n
....en
o
3:
It)
It)
C
II:
o
3:
CD
It)
C
II:
o
3:
....
It)
'r c
I II:
I
I
I"l
CD
C
3:
I
I
I
c
II:
0
3:
I
I
i-I
I
w
I I I
0
..
N
I"l
Io~
I~
III
-0
E
Q)
~
Cii
..I
-
>
co
oa:
o
;:
al
oa:
o
;:
N
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
M
-
OR
FULL
IR
1
04-00
~~~~
tdiS~
OE
L..
.J
~ten
~td(SOL-OXI
~~~------~»~~~~---
k--- tpd --+I
~------~________________________________________
NOTE: SHIFT IN is low
FIGURE 2. DATA OUT WAVEFORMS
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS. TEXAS 75265
7-33
I
SN54ALS235, SN74ALS235
64 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
04-00
<
r-
~
tsu
~
~
th---+\
I
SHIFT IN
s:
+
CD
..3
0
SHIFT OUT
-<
s:
---.1
I
I
I+-tPLH~tW----.j
Q)
~
Q)
OR
I
EMPTY
CC
I
I
CD
If--+\-td(OV-ORHI
3
CD
...
04-00
~
>K
INVALIO
".c.
FIGURE 3. DATA FALL THROUGH WAVEFORMS
0
c:::
...n
SHIFT OUT
til
I
SHIFT IN
I
---.1
I
j.-tPLH - - + - t w
04-00
4
I
FULL
IR
I
-~
FULL
~
FIGURE 4. AUTOMATIC DATA IN WAVEFORMS
SHIFT OUT
L
I
ALMOST FULL/EMPTY
!4-tPHL ~
I
SHIFT IN
FIGURE 5. ALMOST EMPTY WAVEFORMS
7-34
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ALS235, SN74ALS235
64 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
SHIFT IN
U)
....,
I
u
j4-tPLH-+I
~
I
L
I
I
ALMOST FULL/EMPTY
"C
...
0
a..
....,
!+-tPHL ~
C
Q)
I
E
Q)
I
SHIFT OUT
en
ca
ca
FIGURE 6. ALMOST FULL WAVEFORMS
SHIFTIN
~
C
~
II
~
0
E
!f-tPLH+I
Q)
I
HALF FULL
I
I..
I
I
SHIFT OUT
FIGURE 7. HALF FULL WAVEFORMS
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
L
I
tpHL
~I
~
Ui
....
..
>
7-35
SN54ALS235, SN74ALS235
64 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage .............................................................. 7 V
Voltage applied to a disabled 3-state output ..... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54ALS235 . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
SN74ALS235 .......................... DoC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
<
r~
3:
3
CD
o
-<
recommended operating conditions
::::J
Vee
Supply voltage
cc
VIH
High-level input voltage
VIL
Low-level input voltage
Q)
CD
3CD
10H
...
::::J
"...o
10L
fclock
Co
c
n
tw
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
Q outputs
High-level output current
Flags
Q outputs
Low-level output current
Flags
Clock frequency
SHIFT IN or SHIFT OUT
Pulse duration
high or low
(/)
RST low
tsu
Setup time before SHIFT IN i
th
Hold time, data after SHIFT IN i
TA
Operating free-air temperature
Data
RST high (inactive)
0
0.8
0.8
-1
-2.6
-0.4
-0.4
12
24
4
8
20
0
17
15
20
15
0
0
15
15
25
125
V
V
mA
mA
MHz
ns
ns
ns
17
19
-55
UNIT
V
2
2
SHIFT IN or SHIFT OUT
...
-
SN74ALS235
SN54ALS235
3:
Q)
70
0
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
Vee
VIK
Q
Vee
Vee
VOH
Flags
Q
Vee
Vee
Vee
VOL
Flags
Vee
Vee
10ZH
Vee
10ZL
II
Vee
IIH
Vee
IlL
Vee
lot
Vee
lee
SN54ALS235
TYpt
MAX
TEST CONDITIONS
Vee
Vee
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
=
5.5 V
II
MIN
=
-18 mA
10H = -1 mA
10H = -2.6 mA
= -0.4 mA
10L = 12 mA
10L = 24 mA
10L = 4 mA
10L = 8 mA
Va = 2.7 V
Va = 0.4 V
VI = 7 V
VI = 2.7 V
VI = 0.4 V
Va = 2.25 V
10H
SN74ALS235
Typt
MAX
MIN
-1.2
2.4
3.3
2.5
3.4
0.25
0.25
-1.2
2.4
3.2
2.7
3.4
0.4
0.35
0.5
0.4
0.25
0.4
0.4
0.35
0.5
V
20
20
p.A
-20
-20
p.A
0.1
0.1
mA
20
20
-0.1
mA
-112
mA
-0.1
-30
V
V
0.25
0.4
UNIT
-112
-30
IleCL
112
175
112
IleeH
105
170
105
160
Ileez
115
180
115
170
p.A
165
mA
t All typical values are at Vee = 5 V, T A = 25°e.
t The output conditions have been chosen to produce a current that closely approximates one half of the true short·circuit output current, lOS.
7-36
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ALS235, SN74ALS235
64 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
switching characteristics (see Note 1)
VCC - 4.5 V to 5.5 V.
Vcc - 5 V.
CL - 50 pF.
PARAMETER
TO
FROM
(INPUT)
(OUTPUT)
n.
500 n.
R1 - 500
R1 - 500
R2 -
R2 - 500
TYP
CI)
n.
n.
(,)
MAX
MIN
MAX
MIN
SHIFT IN
30
20
25
SHIFT OUT
30
20
25
IR high
15
7
8
tw l
OR high
19
td(QV-ORH)
Q valid before OR t
f max
tw t
td(SOL-QX)
6
Q valid after SHIFT OUT L
::::I
.
UNIT
"'C
o
TA - MIN to MAX
SN74ALS235
SN54ALS235.
TA - 25°C
'ALS235
MIN
....
CL - 50 pF.
7
9
-5
13
12
8
-5
4
0..
....c:
MAX
Q)
MHz
E
Q)
C)
ns
ca
c:
ca
ns
12
ns
~
ns
4
tpd
SHIFT IN L
Q
600
800
350
1200
350
1000
ns
tpHL
SHIFT IN t
IR
20
26
8
36
8
30
ns
tpLH
SHIFT IN L
IR
16
21
6
28
6
25
ns
tPLH§
SHIFT IN L
OR
600
800
350
1200
350
1000
ns
~
o
E
Q)
tpHL
SHIFT IN L
ALMOST FIE
550
700
290
1050
290
880
ns
~
tPLH
SHIFT IN L
ALMOST FIE
85
115
40
170
40
150
ns
(i.)
tpLH
SHIFT IN t
HALF FULL
340
410
180
590
180
510
ns
tpd
SHIFT OUT L
Q
13
17
4
24
4
22
ns
>
tPHL
SHIFT OUT t
OR
23
27
7
39
7
33
ns
tpLH
SHIFT OUT L
OR
20
24
6
33
6
30
ns
tPLH§
SHIFT OUT L
IR
600
800
350
1200
350
1000
ns
tpHL
SHIFT OUT L
ALMOST FIE
550
700
290
1050
290
880
ns
tpLH
SHIFT OUT L
ALMOST FIE
85
115
35
170
35
150
ns
tPHL
SHIFT OUT L
HALF FULL
340
410
170
590
170
510
ns
tpHL
RST L
OR
22
26
10
40
10
34
ns
tpLH
RST t
IR
12
18
5
24
5
22
ns
tpHL
RST L
IR
12
18
5
24
5
22
ns
tpHL
RST L
Q
14
17
5
21
5
19
ns
tdis
OE t
Q
7
13
2
16
2
15
ns
ten
OE L
Q
6
12
2
15
2
13
ns
...J
-
t The IR output pulse occurs when the FIFO is full. Shift In is high. and Shift Out is pulsed (see Figure 4).
l The OR output pulse occurs when the FIFO is empty. Shift Out is high. and Shift In is pulsed (see Figure 3).
§Data throughput or "fall through" times
NOTE 1: Load circuit and voltage waveforms are shown in Section 1 of the LSI Logic Data Book. 1986.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-37
SN54ALS235. SN74ALS235
64 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
TYPICAL APPLICATION INFORMATION
<
r-
HF
AF/E
SO
OR
r-----~IR
~
SI
DO
D1
D2
D3
s:
CD
3
o
-<
HF
AF/E
SHIFT OUT
SO~-~---~~----
OR 1-----+----.
00
00
01
02
03
04
D4 RST
s:
D)
:::s
INPUT READY
D)
cc
CD
t----+--~
3CD
:::s
.oc.
r+
"'C
HF
HF
IR
IR
SI
SI
00
01
02
03
00
01
02
03
04 RST
04
04
OUTPUT REAOY
03
ill
04
c
..
a
HF
L..--4-----I IR
SI
HF
IR
SI
AF/E
SO
OR
HF
IR
SI
00
01
02
03
00
01
02
03
00
01
02
03
00
01
02
03
04
04 RST
-----.--_--1
SHIFT IN
04
ill
04
04
ill
AF/E
SO
04
MASTER RESET
FIGURE 8. 192·WORD BY 15·BIT EXPANSION
7-38
-IJ1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS. TEXAS 75265
SN54ALS236, SN74ALS236
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
D2958, OCTOBER 1986
SN54ALS236 ... J PACKAGE
SN74ALS236 ... 0 OR N PACKAGE
•
Asynchronous Operation
•
Organized as 64 Words of 4 Bits
•
Data Rates from 0 to 30 MHz
•
Pin-Compatible with MMI67401 B with
Higher Speed
•
Dependable Texas Instruments Quality
and Reliability
(TOP VIEW)
NC
IR
SHIFT IN
DO
D1
D2
D3
GND
description
The SN54ALS236 and SN74ALS236 are
256-bit memories utilizing Advanced Low-Power
Schottky IMPACr" Technology, They feature
high speed with fast fall-through times and are
organized as 64 words by 4 bits.
A FIFO memory is a storage device that allows
data to be written into and read from its array
at independent data rates. The 'ALS236 is
designed to process data at rates from 0 to 30
megahertz in a bit-parallel format, word by word,
Data is written into memory on the rising edge
of the Shift In input. When Shift In goes low, the
first data word ripples through to the output (see
Figure 1). As the FIFO fills up, the data words
stack up in the order they were written. When
the FIFO is full, additional Shift In pulses have
no effect. Data is shifted out of memory on the
falling edge of the Shift Out input (see Figure 2).
When the FIFO is empty, additional Shift O!Jt
pulses have no effect. The last data word
remains at the outputs until a new word falls
through or RST goes low
en
....,
VCC
SHIFT OUT
OR
00
01
02
03
RST
(,)
~
"C
...o
a..
....,
cCI)
E
CI)
C)
CO
C
CO
SN54ALS236 ... FK PACKAGE
SN74ALS236 ... FN PACKAGE
~
(TOP VIEW)
I-
~
:::l
o
o
E
CI)
~
3
SHIFT IN
DO
NC
D1
D2
2
Ui
....J
1 2019
18
4
5
17
6
16
7
15
8
14
OR
00
NC
01
02
-
>
9 1011 12 13
II-a: (\')
ozzU'ld
(\') 0
U
(!J
NC-No internal connection.
Status of the' ALS236 FIFO memory is monitored by the Output Ready (OR) and Input Ready (IR) flags.
When the OR flag is high, valid data is available at the outputs. The OR flag is low when Shift Out is high
and will stay low when the FIFO is empty. The IR status flag is high when the inputs are ready to receive
more data. The IR flag is low when Shift In is high and stays low when the FIFO is full.
When the FIFO is empty, input data is shifted to the output automatically when Shift In goes low, If Shift
Out is held high during this time, the OR flag pulses high indicating valid data at the outputs (see Figure 3).
When the FIFO is full, data can be shifted in automatically by holding Shift In high and taking Shift Out
low. A propagation delay after Shift Out goes low, IR will go high. If Shift In is still high when IR goes
high, data at the inputs are automatically shifted in, Since IR is normally low when the FIFO is full and
Shift In is high, only a high-level pulse is seen on the IR output (see Figure 4).
IMPACT is a trademark of Texas Instruments
PRODUCTION DATA documents contain information
current as of publication date, Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~ai~:1~1e ~!~~~~ti~r :I~o::~:~:t:~~s not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1986, Texas Instruments Incorporated
7-39
I
SN54ALS236. SN74ALS236
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
description (continued)
The FIFO must be reset after power up with a low· level pulse on the Master Reset input (RST). This sets
Input Ready (lR) high and Output Ready (OR) low signifying that the FIFO is empty. Resetting the FIFO
sets the outputs to a low logic level (see Figure 1). If Shift In is high when RST goes high, the input data
is shifted in and IR goes low and remains low until Shift In goes low. If Shift In goes low before RST goes
high, the input data will not be shifted in and IR goes high. Data outputs are noninverting with respect
to the data inputs.
<
r-
~
3:
CD
3
o
The SN54ALS236 is characterized for operation over the full military temperature range of - 55 DC to
125 DC. The SN74ALS236 is characterized for operation from 0 DC to 70 DC.
-<
3:
C»
logic symbol t
::l
C»
cc
FIFO 64 x 4
CD
CTR
3
CD
SHIFT IN (31
...
::l
5+iC1
G2
."
~
SHIFT OUT (151
o
Co
c(')
4G3
...en
(141 OR
3CT>0
(CT>0IG4
(21
2CT<64
IR
(CT<64IG5
RST
02
03
..,
10
DO
01
(131
(51
(121
(61
(111
00
01
02
(101 03
(71
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
functional block diagram
r---"""L~~-OO
DO
01
01
02
02
03
03
SHIFT
IR
OUT
OR
Pin numbers shown are for 0, J, and N packages.
7·40
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ALS236, SN74ALS236
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
logic diagram (positive logic)
WORD 64
DO
WORD 63
WORD 1
WORD 2
WORD 3
en
U
::::I
"C
e
...
Q.
s:::::
CD
E
CD
C)
ca
s:::::
ca
:!
~
o
'----~----SHIFT
OUT
L------------------OR
SHIFT
N---+----"
'----+----+------------ - - - -H--
-------------------------IR
RSTl...J
I
03-00
SHIFT OUT
~
I
I
I
~II
:
::
II
I
I
I
I
I
11
11
I
I L-J
L--.J
I
I
I
I
i
~
l
W2~W63@W64W?mW1~
I
I
:
:
I
I
I
I
I
I
I
IR
OR
I
~ W1 @ w2~fflXS~ W1
03-00
..
>
timing diagram
SHIFT IN
I
I
I
ri
"----
r-------------~I~----WORD 2
WORD 3
I
Ln
I
n
I
I
I
CLEAR
E
CD
:!
US
.....
SHIFT IN
W1
SHIFT OUT EMPTY
W2
FULL
t The last data word shifted out of the FIFO remains at the output until a new word falls through or a RST pulse clears the FIFO.
~ While the output data is considered valid only when the OR flag is high, the stored data remains at the output. Any additional words
written into the FIFO will stack up behind the first word and will not appear at the output until SHIFT OUT is taken low.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-41
SN54ALS236, SN74ALS236
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
I
<
j4- t su ----.j
r~
! I- ----~I____~
SHIFT IN
s:
I
(II
3
I
s:
m
jf-tPLH
IR
::::J
m
FULL
I
cc
CD
jf-tPHL
3
CD
I
OR
...
::::J
..-a
o
c.
c(')
...en
-
I
-t-\
j4-tPHL
-+I
I
I
~tPLH
..
I
tf-tpLH
-+I
r
I
1""1- - - - -
I
.1
*----
~tpd
---+I
--......;....-.;.-*j4-tpd
I
I
I
EMPTY
I
I
03-00
I
~
I
I
I
)I(-------X,----
03-00 ~
-<
~I------
r-tsu~th~ I
I
o
I
I
I
NOTE: SHIFT OUT is low
FIGURE 1. MASTER RESET AND DATA IN WAVEFORMS
SHIFT OUT
OR
+~
l
!.--tPLH~
------------------------I
I
:'--tPLH _ _-..1
.. 1
!*--tPHL
I
~
I
I
I
FULL
IR
_____________
t
I
03-00
-==:J>----«
~td(SOL-OX)
»>X«<-r7-------»-~~~~(""____
!.- tpd ---+I
NOTE: SHIFT IN is low
FIGURE 2. DATA OUT WAVEFORMS
7-42
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ALS236, SN74ALS236
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
03-00
SHIFT IN
I
SHIFT OUT
I
~tPLH~tw~
OR
,______________________
_______
EM_P_T_Y____________~I
I
I4--+\-- td(QV-ORH)
Q3-QO
------IN-V-A-U-O-------->K_________________________________
FIGURE 3. DATA FALL THROUGH WAVEFORMS
SHIFT OUT
SHIFTIN
~
I
r-- -+tpLH
IR
03-00
tw
----t>J
I I~________F_U_LL___________
..
_______
FU_L_L______________
~...._ _ _ _ _ _ _ _~
FIGURE 4. AUTOMATIC DATA IN WAVEFORMS
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-43
SN54ALS236. SN74ALS236
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee ......................................................... 7 V
Input voltage .............................................................. 7 V
Operating free-air temperature range: SN54ALS236 . . . . . . . . . . . . . . . . . . . . . .. - 55 DC to 125 DC
SN74ALS236 .......................... 0 DC to 70 DC
Storage temperature range ......................................... - 65 DC to 150 DC
<
r-
~
3:
CD
3
o
recommended operating conditions
-<
3:
C»
::I
C»
cc
CD
3
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
CD
::I
r+
...o
Low-level output current
fclock
elock frequency
tw
Pulse duration
NOM
MAX
4.5
5
5.5
4.5
5
5.5
-1
-2.6
IR and OR
-0.4
-0.4
Q outputs
12
24
IR and OR
4
8
Setup time before SHIFT IN t
th
Hold time, data after SHIFT IN t
Operating free-air temperature
25
0
15
20
15
Data
RST high (inactive)
TA
0
17
0
0
15
15
30
125
V
V
rnA
rnA
MHz
ns
ns
ns
17
19
-55
UNIT
V
Q outputs
RST low
o
2
0.8
high or low
r+
tsu
MIN
0.8
SHIFT IN or SHIFT OUT
(")
MAX
SHIFT IN or SHIFT OUT
Q.
C
NOM
2
High-level output current
10L
"'tJ
-
SN74ALS236
SN54ALS236
MIN
0
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VIK
Q
VOH
IR, OR
Q
VOL
IR, OR
MIN
11=-18mA
2.4
3.3
Vee = 4.5 V,
IOH = -1 rnA
10H = -2.6 rnA
Vee = 4.5 V,
IOH = -0.4 rnA
2.5
3.4
Vee = 4.5 V,
IOL = 12 rnA
Vee = 4.5 V,
10L = 24 rnA
Vee = 4.5 V,
IOL
=
=
IOL
Vee = 5.5 V,
VI = 7 V
IIH
Vee = 5.5 V,
IlL
Vee = 5.5 V,
lo~
Vee = 5.5 V,
Vee = 5.5V
0.25
0.25
4 rnA
Vee = 4.5 V,
SN74ALS236
Typt
MAX
MIN
-1.2
Vee = 4.5 V,
Vee = 4.5 V,
II
lee
SN54ALS236
Typt
MAX
TEST CONDITIONS
8 rnA
-1.2
2.4
3.2
2.7
3.4
0.4
UNIT
V
V
0.25
0.4
0.35
0.5
0.4
0.25
0.4
0.4
0.35
V
0.5
rnA
0.1
0.1
VI = 2.7 V
20
20
p.A
VI = 0.4 V
-0.1
-0.1
rnA
-112
rnA
Vo = 2.25 V
-30
-112
-30
IleeL
100
155
100
145
IleeH
97
152
97
142
rnA
t All typical values are at Vee = 5 V, T A = 25°e.
~ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.
7-44
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ALS236, SN74ALS236
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
switching characteristics (see Note 1)
VCC - 4.5 V to 5.5 V.
VCC - 5 V.
CL - 50 pF.
PARAMETER
n.
500 n.
R1 - 500
FROM
TO
(INPUT)
(OUTPUT)
R2 -
f max
TYP
tI)
n.
500 n.
R2 -
MAX
MIN
MAX
MIN
35
25
30
SHIFT OUT
35
25
30
Q.
...c:
MAX
IR high
15
7
8
ns
tw+
OR high
19
7
8
ns
td(QV-ORH)
Q valid before OR i
td(SOL-QX)
tpd
Q valid after SHIFT OUT
~
9
-5
13
12
-5
12
4
4
600
800
350
1200
350
1000
ns
tpHL
SHIFT IN t
IR
20
26
8
36
8
30
ns
tPLH
SHIFT IN
~
IR
16
21
6
28
6
25
ns
tPLH§
SHIFT IN
~
tpd
SHIFT OUT
tpHL
tPlH
600
800
350
1200
350
1000
ns
Q
13
17
4
24
4
22
ns
SHIFT OUT t
OR
23
27
7
39
7
33
ns
SHIFT OUT
~
OR
20
24
6
33
6
30
ns
tPlH§
SHIFT OUT
~
IR
600
800
350
1200
350
1000
ns
tPHl
RST
OR
22
26
10
40
10
34
ns
tplH
RST ~
IR
17
21
6
31
6
27
ns
tpHl
RST!
Q
14
17
5
21
5
19
ns
~
en
ca
ca
c:
~
ns
Q
OR
E
Q)
ns
~
~
Q)
MHz
tw t
SHIFT IN
..o
UNIT
TA - MIN to MAX
SN74ALS236
SN54ALS236
SHIFT IN
6
CJ
::::I
"'C
R1 - 500
TA - 25°C
'ALS236
MIN
...
CL - 50 pF.
~
o
E
Q)
:?:
..
U)
....I
>
t The IR output pulse occurs when the FIFO is full. Shift In is high. and Shift Out is pulsed (see Figure 4).
+ The OR output pulse occurs when the FIFO is empty. Shift Out is high. and Shift In is pulsed (see Figure 3).
§ Data Throughput or "fall through" times
NOTE 1: load circuit and voltage waveforms are shown in Section 1 of the LSI Logic Data Book. 1986.
-Ii}
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
7-45
SN54ALS236, SN74ALS236
64 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
TYPICAL APPLICATION INFORMATION
<
r-
so
IR
SI
DO
01
02
03
~
3:
CD
3
RST
OR
QO
Q1
Q2
Q3
DO
01
02
03
Q1
Q2
RST Q3
IR
SI
DO
01
02
03
so
SHIFT OUT
OR
QO
Q1
Q2
o
-<
INPUT READY
OUTPUT READY
3:
m
:::s
m
(Q
CD
3
CD
,...:::s
...
."
~S_H_IF_T_I_N__~____- .__,
c:
,...n
-
(I)
03
RST Q3
03 RST
MASTER RESET
FIGURE 5. 192·WORD BY 12·BIT EXPANSION
TEXAS
-1/1
INSTRUMENTS
7-46
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74ACT7201A-25, SN74ACT7201A-35, SN74ACT7201A-50
512 x 9 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORY
D3101, MARCH 1988
SN74ACT7201A ... N PACKAGE
• Asynchronous Operation
(TOP VIEW)
• Organized as 512 Words of 9 Bits
WCLK
• Lower Power Consumption
Active ..• 400 mW
Power Down •.. 3 mW
Standby ... 44 mW
D8
D3
02
01
DO
• Fully Expandable in Word Width and/or
Word Depth
00
01
02
03
08
• EPICTM (Enhanced Performance Implanted
CMOS) 1-J.,lm Process
• Reliable Advanced CMOS Technology
GND
(I)
04
05
06
07
(J
::l
"C
o...
...
Q.
FLIRT
RST
EMPTY
XEI
FULL
• Designed to be Compatible with IDT7201A
But with Lower Power Consumption
...
VCC
2
9
C
Q)
E
Q)
XEO/HF
C')
07
06
05
04
ca
ca
c
~
~
RCLK
o
• Fully TTL-Compatible
E
Q)
For chip carrier information contact the factory.
descripJjon
~
This 4608-bit memory uses Advanced CMOS Technology and features high speed and fast fall-through times.
The 'ACT7201A is organized as 512 words by 9 bits each,
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The function is used as a buffer to couple two buses operating at different clock rates. The
'ACT7201A is designed to process data at rates from 0 to 28.5 MHz in a bit-parallel format, word by word.
Data is written into the memory on a low-to-high transition at the Write Clock (WCll<) input, and is read out of
the memory on a high-to-Iow transition at the Read Clock (RCll<) input, (see Figure 1). The data outputs are
non inverting with respect to the data inputs and are in a high-impedance state w~en RClK is high. The
memory is full when the number of words clocked in exceeds by 512 the number of words clocked out. When
the memory is full, write signals have no effect on the data residing in memory. When the memory is empty,
read Signals have no effect, and the data outputs remain in a high-impedance state.
..
Status of the FIFO memory is monitored by the Full Flag (FUll), Empty Flag (EMPTY), and Expansion Enable
Out/Half Full Flag (XEO/HF). The FUll output is low when the memory is full, and high when the memory is
not full (see Figure 2). The EMPTY output is low when the memory is empty, and high when it is not empty
(see Figure 3). When cascading two or more devices for word-depth expansion, XEO/HF functions as an
Expansion Enable Out output. When the 'ACT7201A is used as a 512-word FIFO memory (no word-depth
expansion), the XEO/HF output functions as a Half Full Flag. This 512-word memory mode is defined by
grounding the Expansion Enable In (XEI) input of the device. In this mode, XEO/HF is low whenever the FIFO
contains 257 or more words, and is high whenever the FIFO contains 256 or less words (see Figure 8).
The First load/Retransmit (FLIRT) input performs two separate functions. When cascading two or more
devices for word-depth expansion, FLIRT functions as a first-load input and is grounded on the first device in
the daisy chain to indicate that it is the first device loaded and unloaded. When the' ACT7201A is used as a
512-word FIFO memory, the FLIRT input performs the retransmit function. In this mode, a low-level pulse on
the FLIRT input resets the read painter to the first memory location to allow for retransmission from the
beginning of data entered. The write pointer is not affected by the FLIRT input. RClK and WClK must be at a
high level during the low-level FLIRT retransmit pulse (see Figure 4). The retransmit operation wilf affect the
value of the Half Full Flag (XEO/HF) by changing the position of the read painter relative to the write pointer.
The retransmit feature should be used only when less than 512 writes are performed between resets,
otherwise, an attempt to retransmit may cause loss of some data that has not yet been read.
EPIC is a trademark of Texas Instruments Incorporated.
ADVANCE INFORMATION documents contain
~~~~:d~~~~~h~::or~~!~f~:~;nth~h~~:J~ir~:ti~
data and other specifications are subject to change
without notice.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © 1988, Texas Instruments Incorporated
7-47
Cii
....
>
:2
o
i=
'ACT7201A
2.4 CT - 0 IRSTI
"tJ
6 IWR
6 C1
::Jl
m
PNTRI
21CT - 5111G6
IBI_
FUll
:5
m
=E
2.4 IREXMITI
5 IRO
PNTRI
ICT - WR PNTR - RO PNTR(
1261
(9l ao
(10 1
a1
(111
a2
(121
a3
(161
a4
(171 a5
1251
(1BI a6
1241
07
DB (21
(191 a7
(131
aB
DO 161
01
02
03
04
05
06
10
3<;7
151
141
131
1271
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
7-48
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ACT7201A-25, SN74ACT7201A-35, SN74ACT701A-50
512 x 9 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORY
functional block diagram
DATA INPUTS _ _ _ _ _ _ _ _ _ _ _ _ _ _-f
LOCATION 1
..,en
t------I
00-08
Co)
LOCATION 2
::::s
"C
o...
a.
512 x 9
WCLK - - - - I
..,
RAM
C
CI)
E
CI)
C)
DATA OUTPUTS
ca
c
ca
00-08
M--~~------h.~--~~------------------~
FriRT
~
I - - - - - - t - - - - - FULL
--4--1
~
o
I - - - - - - t - - - - EMPTY
E
'---r--~
CI)
~
RCLK - - 4 - - 1
XEI
------------------i
1---------- XEO/iiF
RESET AND RETRANSMIT FUNCTION TABLE
INTERNAL TO DEVICE
RST
FL/RT
XEI
L
X
L
Location Zero
H
L
L
H
H
L
READ POINTER
....I
>
Z
512 WORD BY N x 9-BIT OPERATION
INPUTS
..
(i)
.......
'---_
o
OUTPUTS
WRITE POINTER
i=
FUNCTION
EMPTY
FULL
XEO/HF
Location Zero
L
H
H
Reset Device
Location Zero
Unchanged
X
X
X
Retransmit
Increment if EMPTY high
Increment if FULL high
X
X
X
ReadlWrite
o
E
Q)
~
Vee = 5.5 V
MAX
UNIT
V
3.8
en
....J
-
>
0.4
V
10
IJ.A
10
IJ.A
10
IJ.A
80
mA
i=
8
mA
~
500
5
flA
pF
7
pF
-0.2 V
f
ca
ca
~
c
V
Supply voltage
High-level input voltage
VCC
C)
UNIT
2:
o
cd:
a:
oLL
-w
2
= 5 V. TA = 25°C.
(.)
:2
C
c
<
l>
2
('")
m
FIGURE
'ACT7201 A·25
'ACT7201 A·35
MIN
MIN
MAX
'ACT7201 A·50
MIN
22.2
MAX
Clock frequency, RCLK or WCLK
tc(R)
Cycle time, read
1(a)
35
45
65
ns
tc(W)
Cycle time, write
1(b)
35
45
65
ns
tc(RS)
Cycle time, reset
7
35
45
65
ns
tc(RT)
Cycle time, retransmit
4
35
45
65
ns
tw(RL)
Pulse duration, RCLK low
1 (a)
25
35
50
ns
tw(WL)
Pulse duration, WCLK low
1(b)
25
35
50
ns
tw(RH)
Pulse duration, RCLK high
1(a)
10
10
15
ns
tw(WH)
Pulse duration, WCLK high
1(b)
10
10
15
ns
tw(RT)
Pulse duration, FURT low
4
25
35
50
ns
28.5
15
UNIT
fclock
MHz
tw(RS)
Pulse duration, RST low
7
25
35
50
ns
tw(XIL)
Pulse duration, XEI low
10
25
35
50
ns
tw(XIH)
Pulse duration, XEI high
10
10
10
10
ns
tsu(D)
Setup time, data before WCLKt
1(b), 6
15
18
30
ns
tsu(RT)
Setup t~e~CLK and WCLK high
before FURTt
4
25
35
50
ns
tsu(RS)
Setup time, RCLK and WCLK high
before RSTt
7
25
35
50
ns
tsu(XI-R)
Setup time, XEI low before RCLK+
10
15
15
15
ns
tsu(XI-W)
Setup time, XEliow before WCLK+
15
15
ns
th(D)
Hold time, data after WCLKt
0
5
ns
th(E-R)
10
15
1(b),6
0
Hold time, RCLK low after EMPTYt
5
25
35
50
ns
th(F-W)
Hold time, WCLK low after FULLt
6
25
35
50
ns
th(RT)
ti91Q.!ime, RCLK and WCLK high after
FURTt
4
10
10
15
ns
th(RS)
Hold time, RCLK and WCLK high after
RSTt
7
10
10
15
ns
.-
:2
."
o
:D
3:
l>
::!
o
2
7·52
MAX
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ACT7201A-25, SN74ACT7201A-35, SN74ACT7201A-50
512 x 9 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORY
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
FIGURE
fmax
Clock frequency, RCLK or WCLK
~
or EMPTY
'ACT7201 A·25
'ACT7201A·35
'ACT7201 A·50
MIN
MIN
MIN
MAX
28.5
t to
MAX
22.2
MAX
15
CI)
+oJ
UNIT
CJ
:::s
MHz
"C
ns
c.
e
ta
Access time, RCLK
data out valid
tv(RH)
Valid time, data out valid after RCLK
ten(R-QX)
Enable time, RCLK ~ to Q outputs at low
impedance
ten(W-QX)
Enable time, WCLK
low impedance
t to Q outputs at
tdis(R)
Disable time, RCLK
high impedance
t to Q outputs at
1a
15
20
30
ns
tw(FH)
Pulse duration, FULL high in automatic
write mode
6
25
30
45
ns
tw(EH)
Pulse duration, EMPTY high in
automatic mode
5
25
30
45
ns
tp(W-F)
Propagation delay time, WCLK
FULL low
~
2
25
30
45
ns
tp(R-F)
Propagation delay time, RCLK
high
t to FULL
2,6
25
30
45
ns
tp(RS-F)
Propagation delay time, RST ~ to FULL
high
7
20
45
65
ns
tp(RS-HF)
Propagation delay time, RST ~ to XEO/
HF high
7
20
45
65
ns
tp(W-E)
Propagation delay time, WCLK
EMPTY high
3,5
25
30
45
ns
tp(R-E)
Propagation delay time, RCLK
EMPTY low
3
25
30
45
ns
i=
tp(RS-E)
Propagation delay time, RST ~ to
EMPTY low
7
20
45
65
ns
tp(W-HF)
Propagation delay time, WCLK
XEO/HF low
~
:E
8
35
45
65
ns
tp(R-HF)
Propagation delay time, RCLK
HF high
t to XEO/
8
35
45
65
ns
ou.
tp(R-XOL)
Propagation delay time, RCLK
HF low
~
9
25
35
50
ns
tp(W-XOL)
Propagation delay time, WCLK
XEO/HF low
~
9
25
35
50
ns
tp(R-XOH)
Propagation delay time, RCLK
HF high
t to XEO/
9
25
35
50
ns
tp(W-XOH)
Propagation delay time, WCLK
XEO/HF high
t to
9
25
35
50
ns
to
t to
~
25
1(a), 3, 5
t
to
to
to XEO/
to
35
50
1(a)
5
5
5
ns
1(a)
5
5
10
ns
5
5
10
15
ns
..
2
o
(b) WRITE
FIGURE 1. ASYNCHRONOUS WAVEFORMS
(')
m
2
L-fI
RCLK
-
."
WCLK~I'------J/
o
:a
s:
I....----i~~tp(W-F)
I+-tp(R-F)--+f
I
>
FULL ------------~L ______________________
-~~.
~
o
1
f----------------------------
FIGURE 2. FULL FLAG WAVEFORMS
2
7-54
TEXAS
l.!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ACT7201A-25, SN74ACT7201A-35, SN74ACT7201A-50
512 x 9 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORY
PARAMETER MEASUREMENT INFORMATION
....CJen
L{
WCLK
~---~/
RCLK
::::I
"'C
c..
....c:
(1)
I14
\~______________~t
~14---I~N-1 tp(R-EI
!
...o
I
~I tp(W-EI
E
(1)
C)
as
c:
as
~ta~
:a:
1
00-08
-----~@E)@-------------------
...o>
E
(1)
FIGURE 3. EMPTY FLAG WAVEFORMS
14
14
I
~
I
I
~14
I+-- tsu(RTI
-
>
I
1
'1/////////////.&
Cii
....I
1
I
'\
FLIRT
WCLK, RCLK
~I
twIRl)
~
~I
te(RT)
/
th(RTI--+t
2
o
i=
FIGURE 4. RETRANSMIT WAVEFORMS (see Note 2)
WCLK
~
£:t
\ ___1
~I~_ _~--------ll~---.
-2w
_ ______________ I
1
1
~:
EMPTY _ _ _ _ _ _ _ _ _ _ _ _ _
tp(W-EI
U
J~~-------
2
tw(EHI
c
~2
I
WCLKmCLK~
CO)
~I
m
-2
I
EMPTY~
."
o
:a
\4
3:
l>
::!
1
1
:
'\
I
tp(RS-EI---I
I
o
FULL
\ 4 - - tp(RS-HFI
2
14
--+i
tp(RS-FI-.t
FIGURE 7. MASTER RESET WAVEFORMS
7-56
r
I'------J'
I+- tsu(RSI-¥-- th(RSI ~
I
XEoiHF.
I
\
1
f~---~:------------
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ACT7201A-25, SN74ACT7201A-35, SN74ACT7201A-50
512 x 9 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORY
PARAMETER MEASUREMENT INFORMATION
256 WORDS IN MEMORY
I
I 256
I
257 WORDS IN MEMORY
~'-----_/
WCLK
I
I
I+- tp(R-FI-+I
1,------
RCLK - - - - - - - - - - - - - - - - - - _ _
\'------1,
-------r-:--__\
....enCJ
i
I
r-tp(W-HFI1
XEO/HF
WORDS IN MEMORY
:::::I
..
"C
o
I
c..
....c:
Q)
:-1
E
Q)
FIGURE 8. HALF-FULL FLAG WAVEFORMS
en
WCLK
ca
c:
ca
~I~,,-_W_R_IT_E_T_O_L_AS_T_...J
WORD LOCATION
F"r-----\$ 5
:2!
~
I
RCLK----------..;.I-----Jjf--."
I
I
~ "I
'p'W-XOll
o
READ FROM L A S T J j
~
WORD LOCATION
T
rf ,____
h'PIW-XOHI
XEO/HF~\_ _ _ _ _ _ _
~'PIR-XOll
~'PIR-XOHI
I~_"f
~I,
FIGURE 9. EXPANSION-OUT WAVEFORMS
_
!.-,-
tw(XILI
-LtW(XIHI~I
i
XEI\
WCLK
4
E
Q)
:2!
Cii
-I
-
>
:2
o
\ ______/
i=
:E
c
o
SN74ACT1201A
09-01S
00-08
WCLK
EMPTY
RCLK
..
FLIRT
(1)
L
~
'9
FULL
XEoiHF
(j)
EMPTY
....
>
FULL
XEO/HF
(s ee Note 3)
RST
~
E
09-018
00-08
2:
XEI
o
i=
NOTE 3: In word-width expansion, the status flags EMPTY, FULL, and XEO/HF can be monitored from either one of the cascaded devices. The
status flag outputs must not be tied together.
<3:
:?!
FIGURE 13. WORD-WIDTH EXPANSION: 512-WORD BY 18-BIT
a:
o
LL
-w2:
U
2:
~
C
c
<
l>
2
m
00-08
XEO/H'F
RCLK
EMPTY
RST
n
00-08 I---
WCLK
~
t-
FULL
~FL/Rf
-2
-
,XEI
'TI
0
FIGURE 14. WORD-DEPTH EXPANSION: 1S36-WORD BY 9-BIT
:JJ
~
l>
::!
0
2
7-60
TEXAS
"'-!}
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74ACT7201A-25, SN74ACT7201A-35, SN74ACT7201A-50
512 x 9 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORY
TYPICAL APPLICATION DATA
tJ)
00-017
00-08
+'
Co)
:::I
00-08
WCLK, RCLK,
RST
"C
09-017
...o
'ACT7201A
'ACT7201A
'ACT7201A
1 536 WORD-DEPTH
1536 WORD-DEPTH
1536 WORD-DEPTH
EXPANSION BLOCK
EXPANSION BLOCK
EXPANSION BLOCK
C.
+'
C
Q)
E
Q)
C)
00-026
09-026
ca
c
ca
018-026
09-017
018-026
~
...>o
FIGURE 15. 1536-WORD BY 27-BIT EXPANSION
E
Q)
~
..
Ci)
..oJ
>
2
o
i=
«
:E
a::
oLL
-2w
(.)
:2
«
>
c
«
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-61
<
r~
s:
CD
3
o
-<
s:
C)
~
C)
cc
CD
3
CD
...
~
.
"'0
o
Co
..
c
S
til
7-62
SN74ACT7202·35, SN74ACT7202·50
1024 x 9 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
D3056. NOVEMBER 1987
SN74ACT7202 ... N PACKAGE
•
Asynchronous Operation
•
Organized as 1024 Words of 9 Bits
•
Low Power Consumption
Active ... 440 mW
Power Down ... 3 mW
Standby ... 44 mW
•
•
(TOP VIEW)
WCLK
08
03
02
01
00
Fully Expandable in Word Width and/or
Word Depth
XEI
FULL
Designed to be Compatible with IDT7202
But with Lower Power Consumption
00
01
02
03
08
GNO
o EPICTM (Enhanced Performance Implanted
CMOS) 1·JLm Process
o
Reliable Advanced CMOS Technology
o
Fully TTL·Compatible
U)
.....
(J
VCC
04
05
06
07
:::s
-C
...o
c..
.....
FLIRT
RST
EMPTY
XED
r:::
Q)
E
Q)
C)
ca
r:::
ca
07
06
05
04
2
...>o
E
Q)
RCLK
For chip carrier information contact the factory.
2
description
en
This 9216-bit memory uses Advanced CMOS Technology and features high speed and fast fall-through
times. The' ACT7202 is organized as 1024 words by 9 bits each.
-I
>
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The' ACT7202 is designed to process data at rates from 0 to 22 MHz in a bit-parallel format,
word by word.
Data is written into the memory on a low-to-high transition at the Write Clock (WCLK) input, and is read
out of the memory on a high-to-Iow transition at the Read Clock (RCLK) input, (see Figure 1). The data
outputs are noninverting with respect to the data inputs and are in a high-impedance state when RCLK
is high. The memory is full when the number of words clocked in exceeds by 1024 the number of words
clocked out. When the memory is full, write signals have no effect on the data residing in memory. When
the memory is empty, read signals have no effect, and the data outputs remain in a high-impedance state.
Status of the FIFO memory is monitored by the Full Flag (FULL), Empty Flag (EMPTY). The FULL output
is low when the memory is full, and high when the memory is not full (see Figure 2). The EMPTY output
is low when the memory is empty, and high when it is not empty (see Figure 3).
The First Load/Retransmit (FL/RT) input performs two separate functions. When cascading two or more
devices for word-depth expansion, FLIRT functions as a first-load input and is grounded on the first device
in the daisy chain to indicate that it is the first device loaded and unloaded. When the' ACT7202 is used
as a 1024-word FIFO memory, the FLIRT input performs the retransmit function. This 1024-word memory
mode is defined by grounding the Expansion Enable Input (XEI) of the device. In this mode, a low-level
pulse on the FLIRT input resets the read pointer to the first memory location to allow for retransmission
from the beginning of data entered. The write pointer is not affected by the FLIRT input. RCLK and WCLK
must be at the high level during the low-level FLIRT retransmit pulse (see Figure 4).
The retransmit feature should be used only when less than 1024 writes are performed between resets,
otherwise, an attempt to retransmit may cause loss of some data that has not yet been read.
When the FIFO is empty, a data word can be read automaticalily at the Q outputs by holding RCLK low
when loading in the data word with a low-level pulse on the WCLK (see Figure 5).
When the FIFO is full, a data word can be written automatically into memory by holding WCLK low while
reading out another data word with a low-level pulse on RCLK (see Figure 6).
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~ar::I~~e ~!~~~~ti~r :I~o~:~:~:t:~~s not
"'-!1
INSTRUMENTS
TEXAS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © 1987. Texas Instruments Incorporated
7-63
SN74ACT7202·35, SN74ACT7202·50
.1024 x 9 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
description (continued)
The FIFO must be reset after power up with a low level pulse on the Reset (RST) input. This resets the
read and write internal stack control pointers to the first memory location, and also sets EMPTY low and
FULL high. Both the RCLK and WCLK inputs must be at a high level during reset (see Figure 7).
<
r~
The' ACT7202 is fully cascadable in word-width and/or word-depth over the specified temperature range.
Word-width expansion (see Figure 10) is accomplished by connecting together the corresponding input
control signals of the cascaded devices. The status flags EMPTY and FULL can be monitored from any
one of the cascaded devices. The XEI input of each device in the word-width expansion should be grounded.
Word-depth expansion (see Figure 11) is also accomplished by connecting together the corresponding input
control signals of the cascaded devices. The FLIRT input, on the first device in the daisy chain, is grounded
to designate it as the first device loaded. The FL/RT inputs of all the other devices in the daisy chain must
be tied high. The Expansion Enable Out (XED) output of each device in the word-depth expansion is
connected to the XEI input of the next device in the daisy chain. A composite EMPTY and FULL must
be generated by DRing the corresponding flags together. In addition, word-width and word-depth expansion
can be applied together to create large FIFO arrays (see Figure 12).
3:
3
CD
o
-<
3:
m
:::s
m
cc
CD
3CD
:::s
The SN74ACT7202 is characterized for operation from OOC to 70°C.
r+
"'C
a
c.
logic symbol t
c
n
r+
FIFO 1024 x 9
4>
-
en
'ACT1202
2.4 CT - 0 [RST)
-._-1>6 [WR
(8) _ _
PNTR) 2(CT-1023)G6
6 C1
FULL
4(CT-1023)G6
(CT - 1024)G6
2.4 [REXMIT)
- .....~~ 5 [RD
PNTR)
[CT - WR PNTR - RD PNTR)
(9)00
3'\7
(10)01
(11)02
(12)03
(16)04
(17)05
(18)06
(19) 07
(13) 08
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12
7-64
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ACT7202·35, SN74ACT7202·50
1024 x 9 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
functional block diagram
DATA INPUTS
DO-OS
------------------11 -LOCATION
1
-----1
en
ti:::s
LOCATION 2
.
"C
o
c..
.....
c:
Q)
1024 x 9
RAM
WCLK - - - - I
LOCATION 1023
E
Q)
DATA OUTPUTS
OO-OS
LOCATION 1024 t - - - + - - t - - I
en
CO
c:
~--~~------~~--~~------------------~
CO
:E
L--------------f:51~US~--------~-------FULL
FLiRf --+--1
~
o
' - - _ _oJ~-------+_-----EMPTY
E
Q)
:E
RCLK --+--t
XEI
1------------- XEO
---------------------1
RESET FUNCTION TABLE
1024 WORD BY N x 9-BIT OPERATION
..
(j)
....
>
I
INTERNAL TO DEVICE
INPUTS
RST
FL/RT
XEI
L
X
L
Location Zero
READ POINTER
H
L
L
Location Zero
H
H
L
Increment if
EF
OUTPUTS
WRITE POINTER
EMPTY
Location Zero
Unchanged
high
Increment if
FULL
L
FF high
H
FUNCTION
Reset Device
X
X
Retransmit
X
X
Read/Write
FIRST LOAD/RETRANSMIT FUNCTION TABLE
M x 1024 WORD BY N x 9-BIT OPERATION
INPUTS
RST
INTERNAL TO DEVICE
READ POINTER
WRITE POINTER
OUTPUTS
FL/RT
XEI
EMPTY
L
L
t
Location Zero
Location Zero
L
H
L
H
t
Location Zero
Unchanged
X
X
H
X
t
X
X
X
X
FULL
FUNCTION
Reset First Device
Reset All
Other Devices
Read/Write
tXEI is connected to XEO of the previous device in the daisy chain.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-65
SN74ACT7202·35, SN74ACT7202·50
1024 x 9 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
PIN
NAME
<
00
r~
s:
CD
3
o...
'<
s:
NO.
1/0
6
I
01
5
I
02
4
I
03
3
I
04
27
I
05
26
I
06
25
I
07
24
I
08
2
I
21
0
8
0
Q)
:s
Q)
cc
EMPTY
CD
FULL
3
DESCRIPTION
Oata Inputs
Empty flag output. The empty flag (EMPTY) output is low when the FIFO memory is empty, and high when the
memory is not empty. When the memory is empty, additional read operations are inhibited.
Full flag output. The full flag (FULL) output is low when the FIFO memory is full, and high when the memory
is not full. When the memory is full, additional write operations are inhibited.
CD
First loadlretransmit input. This input performs two separate functions. When cascading two or more devices
...
it is the first device loaded and unloaded. It is connected high on the other devices. In single-device operation
...:s
for word-depth expansion, the FLIRT input is grounded on the first device in the daisy chain to indicate that
."
o
or in word-width expansion, the
c.
c
n
en
mRT
23
I
...
FLIRT input initiates the retransmit function. In this mode, a low-level pulse
on the FLIRT input resets the read pointer to the first memory location to allow for retransmission from the
beginning of data entered. The write pointer is not affected by the
be at a high level during the low level
FLIRT retransmit
FLIRT input. The RCLK and WCLK must
pulse. The retransmit feature should be used only
when less than 1024 writes are performed between resets, otherwise, an attempt to retransmit may cause
loss of some data that has not yet been read.
GNO
14
QO
9
Q1
10
Ground
Q2
11
Q3
12
Q4
16
Q5
17
Q6
18
Q7
19
Q8
13
RCLK
15
I
RST
22
I
VCC
28
0
Oata outputs. These outputs are in the high-impedance state when the RCLK input is high or if the memory
is empty.
Read clock input. If the FIFO is not empty (i.e., EMPTY is high), data is read from the FIFO on RCLK input
high-to-Iow transition.
Master Reset Input. A low level pulse on the Master Reset input (RST) resets the FIFO. This sets the EMPTY
output low and the FULL output high, indicating that the FIFO is empty. RCLK and WCLK must both be
at a high level during reset.
Supply voltage
WCLK
1
I
XEI
7
I
Write clock input. If the FIFO is not full (i.e., FULL is high), data is written into the FIFO on a low-to-high
transition at the WCLK input.
Expansion Enable Input. When cascading two or more devices for word-depth expansion, the XEI input is
connected to the XEO output of the previous device in the daisy chain. The XEI input is grounded when
no word-depth expansion is desired.
XEO
7-66
20
0
Expansion Enable Output. When cascading two or more devices for word-depth expansion, the XEO output
is connected to the XEI input of the next device in the daisy chain.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ACT7202·35, SN74ACT7202·50
1024 x 9 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ...................................... -0.5 V to 7 V
Input voltage range, any input ....................................... "
-0.5 V to 7 V
Voltage applied to a disabled 3-state ouput ...................................... 5.5 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
....
U)
(,)
:::s
..
"C
o
a..
....C
NOTE 1: All voltage values are with respect to GND.
Q)
recommended operating conditions
Vcc Supply voltage
VIH High-level input voltage
MIN
NOM
MAX
4.5
5
5.5
UNIT
E
Q)
V
CO
VIL
Low-level input voltage
0.8
-8
rnA
8
rnA
70
°C
IOH
High-level output current
IOL
Low-lev~1
TA
Operating free-air temperature
output current
0
electrical characteristics over recommended operating free·air temperature range,
otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
VCC = 4.5 V.
IOH = -8 rnA
VOL
Low-level output voltage
VCC = 4.5 V.
IOL = 8 rnA
IOZH
High-impedance-state output current
IOZL
II
High-impedance-state output current
Vee -
MIN
Typt
MAX
UNIT
V
3.8
Vo = 2.7 V
10
p.A
10
p.A
Input current
Vo = 0.4 V
VI = 0 V to 5.5 V
10
p.A
ICCl
Supply current
f = 22 MHz
SO
rnA
ICC2
Standby current
RCLK. WCLK. RST. and FLIRT at VIH
8
rnA
ICC3
Ci
Power down current
VI = VCC -0.2 V
500
p.A
Input capacitance
VI = O.
f = 1 MHz
5
pF
Co
Output capacitance
Vo = O.
f = 1 MHz
7
pF
5 V. TA
~
~
o
E
Q)
5.5 V (unless
V
=
C
CO
V
0.4
tAli typical values are at VCC
C)
V
2
~
..
Cii
....I
>
= 25°C.
TEXAS . .
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS. TeXAS 75265
7-67
SN74ACT7202·35, SN74ACT7202·50
1024 x 9 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
timing requirements over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
<
r-
PARAMETER
~
FIGURE
3:
tc(Ri
tc(W)
Cycle time, read
3
tc(RS)
tc(RT)
Cycle time, reset
Cycle time, retransmit
twIRL)
Pulse duration, RCLK low
twlWL)
twlRH)
Pulse duration, WCLK low
tw(WH)
Pulse duration, WCLK high
Pulse duration, FLIRT low
C'D
twlRT)
tw(RS)
tsu(D)
Setup time, data before WCLKi
C'D
tsu(RT)
Setup time, FLIRT high before RCLK! or WCLK!
C'D
o...
-<
3:
m
:::::s
m
cc
3
.....
..
:::::s
la
Cycle time, write
lb
7
4
la
lb
la
lb
4
7
lb,6
4
7
7
lb,6
5
6
7
7
Pulse duration, RCLK high
Pulse duration, RST low
tsu(R·RS) Setup time, RCLK high before RSn
t sulW.RS) Setup time, WCLK high before RSn
"'a
o
th(D)
Hold time, data after WCLKi
r::
n
th(E·R)
th(F·W)
Hold time, RCLK low after EMPTYi
en
th(RS·W)
Hold time, WCLK high after RSn
th(RS·Rl
Hold time, RCLK high after RSn
Co
-
Hold time, WCLK low after FULLi
SN74ACT7202·50
MAX
MIN
SN74ACT7202·35
MIN
MAX
UNIT
65
45
ns
65
45
ns
65
25
ns
65
30
ns
50
30
ns
50
35
ns
15
15
ns
15
10
ns
50
20
ns
50
15
ns
30
10
ns
15
10
ns
50
30
ns
50
35
ns
5
50
3
30
ns
50
35
ns
15
10
ns
15
10
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
ta
Access time, RCLK! or EMPTYi to data out valid
SN74ACT7202·50
Typt
MAX
MIN
la, 3, 5
18
SN74ACT7202·35
Typt
MAX
MIN
50
18
35
UNIT
ns
Valid time, data out valid after RCLKi
tv(RH)
tenJR.QX) Enable time, RCLK! to Q outputs at low impedance
ten(W.QX) Enable time, WCLKi to Q outputs at low impedance
la
5
5
ns
1a
10
15
5
10
ns
ns
tdis(R)
Disable time, RCLKi to Q outputs at high impedance
la
10
30
10
20
ns
tw(FH)
tw(EH) •
Pulse duration, FULL high in automatic write mode
6
15
45
15
25
ns
Pulse duration, EMPTY high in automatic read mode
5
18
45
18
30
ns
tp(W·F)
Propagation delay time, WCLK! to FULL low
2
15
45
15
25
ns
tp(R·F)
Propagation delay time, RCLKi to FULL high
2,6
23
45
23
35
ns
tp(R·E)
Propagation delay time, RCLK! to EMPTY low
3
18
45
18
30
ns
tp(W·E)
Propagation delay time, WCLKi to EMPTY high
3,5
21
45
21
30
ns
tp(RS·E)
Propagation delay time, RST! to EMPTY low
6
9
65
9
20
ns
tp(RS-F)
Propagation delay time, RST! to FULL high
6
7
65
7
20
ns
tAli typical values are at VCC
7-68
FIGURE
= 5 V,
TA
5
= 25°C.
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74ACT7202·35, SN74ACT7202·50
1024 x 9 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
PARAMETER MEASUREMENT INFORMATION
I..
tc(Rl----M.I..f - - - t w ( R L l - - + l
I
1..- -...t ....
..
1 tw(RHl
I+----ta---+l
I
I
I
RCLK
ten(R-OXl
en
.....
I
I
"C
CJ
~
.
o
c..
.....
'"~II~______~I-JI~----------------
_____ I
~I"
k---ta~
I
: T
I
tl
'-
: {
\4--- tv(RHl~
I
c:
Q)
E
Q)
k - - - tdis(Rl-----..j
Y8~---
C)
CO
00-08 - - - - - - - ._ _ _
V_AL_ID_ _ _ _ _ _V_A_LlD
___
c:
CO
(al READ
~
14
14
00-08
~..
tw(WLl
--It
\'--__-J/
I
I+- tsu(Dl--*-th(Dl~
VALID
~
I
___
---------«k
E
Q)
tw(WHl---+i
I
~'---
o
tc(Wl-------+ltl
I
weLK
~
CiS
....I
>
..J»)----
-----«""___VA_L_ID_ _
) ..
1
(bl WRITE
-
FIGURE 1. ASYNCHRONOUS WAVEFORMS
LfI
RCLK
WCLK~
I
1"------'
1144---Itjll-tp(W-FI
I+- tp(R-Fl ~
ff---------\______________________I
FIGURE 2. FULL FLAG WAVEFORMS
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-69
SN74ACT7202·35, SN74ACT7202·50
1024 x 9 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
PARAMETER MEASUREMENT INFORMATION
<
r-
s:
CD
~I·
RCLK
3
0
-<
s:OJ
'---J
'----f
WCLK
~
.1
EMPTY
/
1
tp(R-E)
I.
.1
1
tp(W-E)
t
\
I
I
~
I
I
I4-- t a ----.t
OJ
CC
CD
1
3CD
~
00-08
~
r+
.
FIGURE 3. EMPTY FLAG WAVEFORMS
"U
0
CC
,.
r+
.1
tw(RT)
\
(I)
FI:/iff
·1
tc(RT)
14
(')
1
I
1
1
~
1
1
1
WCLK. RCLK
I
/
k--tsu(RT)~
FIGURE 4. RETRANSMIT WAVEFORMS
WCLK
\
1
_ _- - J
t+--th(E-R)~
1
:
RCLK
l
1
1
I
I
,,----
~~-----
EMPTY _ _ _ _ _ _ _ _ _ _ _ _:_ _ _ _
I
tp(W-E)
14
I
ten(W-OX)~
00-08
.1
14
I
.14~
If-
ta
I
,
------------"""i~,.....-V-AL-IO-'""\}FIGURE 5. AUTOMATIC READ WAVEFORMS
7-70
tw(EH)
TEXAS •
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS. TeXAS 75265
SN74ACT7202·35, SN74ACT7202·50
1024 x 9 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
PARAMETER MEASUREMENT INFORMATION
.J(
...,oCo)
I
"C
RCLK \ ' -_ _ _ _ _ _
::s
I
WCLK
/4---th(F-Wl~
I
I
I
I
1
I
c..
...,
1,._ _-
fI
C
Q)
E
Q)
I
I+- tp(R-Fl-+/
________________________________~f
C)
\_~:_______
/4--t w (FHl---+i
----------------.......j(
CO
C
CO
:E
I
-+I
00-08
...o
VALID
,
I
...o>-
k-th(OI
»)-'----
E
Q)
:E
/4-- tsu (0 1----+1
en
>
FIGURE 6. AUTOMATIC WRITE WAVEFORMS
14
14
~I
tc(RSl
~
tw(RSl
I
I
I
I
I
I
f,------:-: -------
RST \
,
weLKIReLK_
I tsu(W-RSl t
I
I
~~~~\~~~\\~~
EMPTY~
14
...I
'4
t
iI
~·4
tsu(R-RSl
....Jr
-
~'-___
th(RS-Wl t
t
w
.,
th(RS-Rl
tp(RS-El~
I
I
FULL
l1li
tp(RS-Fl~
tThe WCLK input must be high for a time equal to tsu(W-RSl before. and th(RS-Wl after. the rising edge of RST. The RCLK input must
be high for a time equal to tsu(R-RSl before. and th(RS-Rl after. the rising edge of RST.
FIGURE 7. MASTER RESET WAVEFORMS
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-71
I
SN74ACT7202·35, SN74ACT7202·50
1024 x 9 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
PARAMETER MEASUREMENT INFORMATION
<
r-
1100 {l
~
FROM OUTPUT--;....._ _ _..
3:
CD
3
UNDER TEST
680 {l
o
..(
3:
&»
::;,
I»
cc
tlncludes probe and jig capacitance.
CD
FIGURE 8. LOAD CIRCUIT
3
CD
...::;,
TIMING
INPUT
..
c.
"'a
o
c
n
~---3V
-----.t·
-I- ---tf4-t
I
--GND
h~
If--t su
I
...en
HIGH-LEVEL
5V
I
1.5 V
.
I
1.5 V
GND
:
jf
\f-t,:$ 5 ns
-+I \4- t f:$
I :
1.,..----~2.....7 ...V....~-
111.5V
-GND
VOLTAGE WAVEFORMS
PULSE DURATION
5 ns
-
-
-
\1,.:: -
-3 V
1.5V
~tpd----+l
10.3 V
GND
I+-tpd~
I
I
I
3-STATE OUTPUTS (00-08)
I
~tpd-+l
I
Xc
STANDARD CMOS OUTPUTS (EMPTY, FULL, XO)
FIGURE 9. TIMING REFERENCE LEVELS
7-72
-3V
'-.- - - - G N D
I
I
I
1---3V
1.5 V
LOW-LEVEL
PULSE
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
~
GND
I4--tw -----...,
DAT~I
:i
-3V
INPUT
I _ _-
I4------tw~
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ACT7202·35, SN74ACT7202·50
1024 x 9 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
TYPICAL APPLICATION DATA
SN74ACT1202
00-018
WCLK
RCLK
, ... 18
00-08
00-08
'"
,
00-08
WCLK
RCLK
00-08
9
/
, ... 18
U
:::J
.
"'C
o
EMPTY
EMPTY
...
~
FULL
(S ee Note 21
FULL
FLIRT
FLIRT
...en
00-018
C
Q)
E
Q)
RST
, ,,9
C)
ca
c
ca
XEI
F
:iE
~
SN74ACT7202
09-018
..
o
09-0} 8
00-08
00-08
WCLK
EMPTY
RCLK
FULL
EMPTY
FULL
(Se e Note 2)
FLIRT
..
RST
*
E
Q)
:iE
'9
XEI
CiS
....
-
>
NOTE 2: In word-width expansion, the status flags EMPTY and FULL can be monitored from either one of the cascaded devices. The status
flag outputs must not be tied together.
FIGURE 10. WORD·WIDTH EXPANSION: 1024·WORD BY 18-BIT
TEXAS . "
INSfRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-73
SN74ACT7202·35, SN74ACT7202·50
1024 x 9 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
TYPICAL APPLICATION DATA
SN74ACT7202
<
r-
00-08
~
~
CD
3
9
9.,
,
,
WCLK
WCLK
RCLK
RCLK
00-08
-<
, j9
-
9
,
00-08
XEO
EMPTY
RST
RST
0
00-08
FULL
FLIRT
,e
~
m
::::I
m
c.c
XE1
....
SN74ACT7202
CD
~ 00-08
...::::I
WCLK
3CD
.c.
00-08 I--
0
EMPTY
RST
c
Vcc
...
n
~
XEO I--
RCLK
"'C
~
FULL
FLIRT
-
(I)
,XEI
---;r~
SN74ACT7202
~
00-08
00-08
WCLK
XEO
RCLK
r-- ~
t-
EMPTY
RST
FULL
~FL/Rf
-
~XEI
~
FIGURE 11. WORD-DEPTH EXPANSION: 3072-WORD BY 9-BIT
7-74
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ACT7202·35, SN74ACT7202·50
1024 x 9 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
TYPICAL APPLICATION DATA
....enCJ
00-017
00-08
:::::I
00-08
WCLK, RCLK,
AS
"C
09-017
'ACT7202
3072 WORD-DEPTH
EXPANSION BLOCK
...o
c..
....c:
'ACT7202
3072 WORD-DEPTH
EXPANSION BLOCK
'ACT7202
3072 WORD-DEPTH
EXPANSION BLOCK
CI)
E
CI)
C')
CO
c:
00-026
09-026
CO
018-026
~
~
FIGURE 12. 3072-WORD BY 27-BIT EXPANSION
o
E
CI)
~
en
.....
..
>
I
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-75
<
r-
~
3:
(1)
3
o
-<
3:
D)
:::s
D)
cc
CD
3
(1)
...
:::s
..
."
o
Co
..
r::::
~
en
7-76
SN74ALS2232
64 x 8 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
03091. FEBRUARY 1988-REVISED MARCH 1988
o
Independent Asynchronous Inputs and
Outputs
o
64 Words by 8 Bits
U)
.....
()
DE
o
Data Rates from 0 to 40 MHz
o
Fall· Through Time ... 20 ns Typical
o
OW OR NT PACKAGE
(TOP VIEW)
DO
D1
D2
D3
VCC
D4
D5
D6
D7
FULL
LDCK
3·State Outputs
description
This 512-bit memory uses Advanced Low-Power
Schottky IMPACT-X'" technology and features
high speed and fast fall-through times. It is
organized as 64 words by 8 bits.
A FIFO memory is a storage device that allows
data to be written into and read from its array
at independent data rates. The function is used
as a buffer to couple two buses operating at
different clock rates. This FIFO is designed to
process data at rates from to 40 MHz in a bitparallel format, word by word.
Status of the FIFO memory is monitored by the
FULL and EMPTY output flags. The FULL output
will be low when the memory is full, and high
when the memory is not full. The EMPTY output
will be low when the memory is empty, and high
when it is not empty.
::::s
"C
...o
CL.
.....
c:
Q)
E
Q)
en
CIS
c:
EMPTY
CIS
UNCK
:E
FN PACKAGE
(TOP VIEW)
..... o
It;;
u
U.J
0
.....
ooa:zOdd
a
Data is written into memory on a low-to-high
transition of the load clock input (LDCK) and is
read out on a low-to-high transition of the unload
clock input (UNCK). The memory is full when the
number of words clocked in exceeds by 64 the
number of words clocked out. When the memory
is full, LOCK signals have no effect on the data
residing in memory. When the memory is empty,
UNCK signals have no effect.
00
01
02
03
GND
04
05
06
07
432
D2
D3
VCC
NC
5
6
7
8
9
10
11
1 28 2726
25
24
23
22
21
20
12131415161718
19
-
NC - No internal connection
A low level on the reset input (RST) resets the internal stack control pointers and also sets EMPTY low
and FULL high. The outputs are not reset to any specific logic levels. The first low-to-high transition on
LDCK, either after a RST pulse or from an empty condition, causes EMPTY to go high and the data to
appear on the Q outputs. The first word does not have to be unloaded. Data outputs are noninverting with
respect to the data inputs and are at a high-impedance state when the output-enable input (OE) is low.
The OE input does not effect either the FULL or EMPTY output flags. Cascading is easily accomplished
in the word-width direction, but is not possible in the word-depth direction.
The SN74ALS2232 is characterized for operation from OOC to 70°C.
IMPACT -x is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~!:c~~:~~i~ai~~1~7e ~~:~~~ti~r :I~o::~:~:t:r~~s not
"'11
INSTRUMENTS
TEXAS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © 1987. Texas Instruments Incorporated
7-77
I
SN74ALS2232
64 x 8 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
logic symbol t
<
r-
RST (1)
s:
UNCK (13)
FIFO 64 x 8
~
CTR
LOCK .;..(1_2"';')_-I>1(+/C2)
CD
3
o
3-
OE (24)
-<
s:
EN4
4'\7
D)
::::s
D)
cc
(21) 02
3CD
(18) 04
r+
(17) 05
CD
(20)
::::s
...o
03
""0
(16) 06
Co
(15) 07
c
n
r+
til
_
(23) 00
(22) 01
tThis symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. The symbol is functionally accurate but
does not show the details of implementation; for these. see the logic diagram. The symbol represents the memory as if it were controlled
by a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is O.
Pin numbers shown are for OW or NT packages.
7-78
TEXAS
l.!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ALS2232
64 x 8 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
logic diagram (positive logic)
...en
OE~--------------.------------------------------------------------------'
C.)
:J
"C
...o
c..
...r::::
DECODE
LATCH
1-----,-7'---_-1, PL
CI)
E
CI)
C)
ca
r::::
ca
~
~
~~CT~~E
o
I-----.--.<-I--.-+--I'OL
Q-QL +8QH
E
CI)
~
~~I1I~------
____________________~________~~__~-1
(j)
....I
>
1231
00
,
0
121102
1201
03
(181 ,
0
1221
(17)
05
(161
1151
P-________________
06
Q7
~I~14IfiWn
Pin numbers shown are for OW or NT packages.
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7·79
SN74ALS2232
64 x 8 ASYNCHRONOUS 'FIRST·IN FIRST·OUT MEMORY
timing diagram
<
r-
---.J
RST
I
~
~
LOCK
3:
CD
3
o
I
rl II
J--3'
I
Lf
l.......-.---
DO-D7~W,®w2®w31~io~»~{~W'®W2~~~1
1
:_
I
I
. •
I
-<
UNCK
D)
00-07
3:
::::I
I
I
I
I
.........................JI'..........J
~~~~'I~
D)
CQ
CD
3
I
CD
::::I
...
..
o
c.
c
n
I
I
I
I
I
I
LOAD
W1
I
UNLOAD
W2
L-J
I
EMPTY
FULL
absolute maximum ratings over operating free·air temperature range
ur
-
I
I
INITIALIZE
POINTERS
."
I
I
Supply voltage, Vee ......................................................... 7 V
Input voltage .............................................................. 7 V
Voltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 0 e
, Storage temperature range .......................................... - 65 °e to 150 °e
recommended operating conditions
NOM
MAX
4.5
5
5.5
UNIT
V
O.B
V
V
Supply voltage
VIH
VIL
High-level input voltage
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
fclock
Clock frequency
LOCK. UNCK
Pulse duration
RST low
LOCK low
LOCK high
25
13
12
UNCK low
13
12
tw
2
Q outputs
-2.6
FULL. EMPTY
Q outputs
-0.4
FULL. EMPTY
B
24
0
UNCK high
40
mA
mA
MHz
ns
ns
tsu1
Setup time, data before LOCKt
5
tsu2
th
Setup time. f{5'f high (inactive) before LDCKt
5
ns
Hold time. data after LOCKt
Operating free-air temperature
5
0
ns
TA
7-80
MIN
VCC
TEXAS
'1!1
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
70
°c
SN74ALS2232
64 x 8 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
TEST CONDITIONS
VCC = 4.5 V.
II = -18 mA
FULL. EMPTY
VCC = MIN TO MAX.
10H = 0.4 mA
Q outputs
VCC = 4.5 V.
VIK
VCC- 2
2.4
10H = -2.6 mA
10L = 24 mA
IOL = 4 mA
VCC =4.5 V
FULL. EMPTY
Typt
MAX
1.2
10L = 12 mA
Q outputs
VOL
MIN
10L = 8 mA
UNIT
V
V
3.2
0.25
0.35
0.4
0.5
0.25
0.4
0.35
0.5
10ZH
VCC = 5.5 V.
Vo = 2.7 V
20
p.A
10ZL
II
VCC = 5.5 V.
Vo = 0.4 V
-20
p.A
VCC = 5.5 V.
VI = 7 V
0.1
mA
IIH
VCC = 5.5 V.
VI = 2.7 V
20
p.A
IlL
VCC = 5.5 V.
VI = 0.4 V
-0.1
mA
VCC = 5.5 V.
Vo = 2.25 V
Q outputs
10i
FULL. EMPTY
-30
-112
-20
-112
270
175
VCC = 5.5 V
ICC
...c:
V
CD
E
CD
en
as
c:
as
:?:
~
o
mA
E
CD
:?:
mA
t All typical values are at VCC = 5 V. T A = 25°C.
iThe output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current. lOS.
>
switching characteristics (see Note 1)
PARAMETER
FROM
(INPUT)
en..J
TO
(OUTPUT)
Vee - 4.5 V to 5.5
Vee - 5 V.
eL - 50 pF.
R1 - 500 n.
R2 - 500
v.
eL - 50 pF.
R1 - 500
n.
TA - 25 0 e
TYP MAX
MIN
n.
UNIT
R2 - 500 n.
TA - ooe to 70 0 e
MAX
MIN
40
f max
LOCK
UNCK
ted
tpd
LOCKl
Any Q
18
26
30
ns
UNCKl
Any Q
18
24
27
ns
tpLH
LOCKl
EMPTY
12
16
18
ns
tpHL
UNCKl
EMPTY
12
17
20
ns
tpHL
RSn
EMPTY
12
17
20
ns
tpHL
LOCKl
FULL
16
21
22
ns
tpLH
UNCKl
FULL
10
15
18
ns
tpLH
RSn
FULL
13
19
23
ns
ten
OEl
Q
11
15
17
ns
tdis
OE!
Q
11
17
19
ns
"I
MHz
40
Note 1: Load circuit and voltage waveforms are shown in Section 1 of the LSI Logic Data Book. 1986.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-81
<
r-
~
s:
CD
3
o
-<
s:
CI)
::::s
CI)
(Q
CD
3
CD
...
::::s
..
"'C
oQ.
..
r::::
...
(')
t/)
7-82
SN74ALS2233
64 x 9 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
03092. FEBRUARY 1988 - REVISED APRIL 1988
•
Independent Asynchronous Inputs and
Outputs
•
64 Words by 9 Bits
•
Data Rates from 0 to 40 MHz
•
Fall·Through Time ... 20 ns Typical
o
3·State Outputs
description
This 576-bit memory uses Advanced Low-Power
Schottky IMPACT -X'· technology and features
high speed and fast fall-through times. It is
organized as 64 words by 9 bits.
A FIFO memory is a storage device that allows
data to be written into and read from its array
at independent data rates. The function is used
as a buffer to couple two buses operating at
different clock rates. This FIFO is designed to
process data at rates from 0 to 40 MHz in a bitparallel format, word by word.
N PACKAGE
(TOP VIEWI
RST
DO
D1
D2
D3
VCC
D4
D5
D6
D7
D8
ALMOST FULL/EMPTY
FULL
LDCK
Data is written into memory on a low-to-high
transition of the load clock input (LOCK) and is
read out on a low-to-high transition of the unload
clock input (UNCK). The memory is full when the
number of words clocked in exceeds by 64 the
number of words clocked out. When the memory
is full, LOCK signals have no effect on the data
residing in memory. When the memory is empty,
UNCK signals have no effect.
...
t/)
OE
00
01
02
03
GND
04
05
06
07
08
HALF FULL
EMPTY
UNCK
CJ
:::s
.
"'C
o
c.
...c:::
Q)
E
Q)
C)
CO
c:::
CO
~
~
o
E
Q)
FN PACKAGE
:!E
(TOP VIEWI
N
.- 0
4
3 2
It;;
W
0
Cii
...I
.-
0000:::000
D3
VCC
D4
D5
D6
D7
D8
>
1 282726
5
25
6
24
7
23
8
22
9
21
10
20
11
19
02
03
GND
04
05
06
07
-
12131415161718
..Jeo
Status of the FIFO memory is monitored by the
FULL, EMPTY, ALMOST FULL/EMPTY, and
HALF FULL output flags. The FULL output will
be low when the memory is full and high when
the memory is not full. The EMPTY output will
be low when the memory is empty and high
when it is not empty. The ALMOST
FULL/EMPTY flag is high when the FIFO contains
eight or less words or fifty-six or more words.
The ALMOST FULL/EMPTY flag is low when the
FIFO contains between nine and fifty-five words.
The HALF FULL flag is high when the FIFO
contains thirty-two or more words, and is low
when the FIFO contains thirty-one words or less.
50
u..
u..
..J
1( + /C2)
....::::I
..."'C
o
UNCK (15)
3-
CT~32
CT s 8/CT
~
56
(17) HALF FULL
(12) ALMOST FULL/EMPTY
FULL
(CT - 64) Gl
P - ' - - ' - EMPTY
Q.
C
....til
()
OE
-
DO
01
02
03
04
05
'06
07
08
(28)
(2)
(3)
EN4
20
4'\7
(27) 00
(26) 01
(4)
(25) 02
(5)
(24) 03
(7)
(22) 04
as
(8)
(21)
(9)
(20) 06
(19)
07
(18) 08
(10)
(11 )
tThis symbol is in accordance with ANSI/IEEE Standard 91 - 1984 and IEC Publication 617- 12. The symbol is functionally accurate but
does not show the details of implementation; for these, see the logic diagram. The symbol represents the memory as if it were controlled
by a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is O.
7·84
-I./}
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74ALS2233
64 x 9 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORY
logic diagram (positive logic)
....enCJ
:l
"C
..
0
WRITE
PL
DECODE LATCH
0.
....C
lPL
CD
P-PL+SPH
E
Cl
CD
C)
co
co
c
lPH
:E
~
RAM
64K9
READ
DECODE LATCH
0
E
CD
:E
Cii
....
10L
O-OL+SOH
Cl
0
DO
01
02
12)
13)
00
01
14)
02
15)
17)
IS)
05
19)
06
110)
07
Ill)
OS
-
>
10H
m
03
03
04
04
05
06
11S)
07
OS
LOW
COMP
PL
------<::1,-}--+....~____.,
PL-OLP---.....
OL
ALMOST FULL/EMPTY
HIGH
COMP
PH
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-85
I
I
....
00
en
s:a,3npOJd :a,uawa6euell\l Alowall\l ISlA
..3"
S"
eg
=en
~2:
x-""
~
;"
CD:z:.
:z:.r-
0;
--
0
E
CD
~
en
..
....I
>
'ALS632B, ALS633 ... FN PACKAGE
(TOP VIEW)
N~O
eI:
eI:
l
Ig
UU
~
0 Ol
C'lC'lN
uu~~~I~w8uu~o~~~uu
zzooow~~»~~ooozz
9
NC
DB3
DB4
DB5
DEBO
DB6
DB7
GND
GND
DB8
DB9
OEBI
DB10
DB11
DB12
DB13
DB14
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
~
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
NC
NC
DB28
DB27
DB26
OEB3
DB25
DB24
GND
M
2728293031323234353637383940414243
NC - No internal connection
Copyright © 1982. Texas Instruments Incorporated
~
TEXAS
INSTRUMENTS
655012 •
0
DB31
DB30
DB29
DB28
DB27
DB26
DEB3
DB25
DB24
GND
DB23
DB22
DEB2
DB21
DB20
DB19
DB18
DB17
DB16
CBO
CBl
CB2
CB3
DBI
DB2
DB3
DB4
DEVICE
POST OFFICE BOX
VCC
51
so
'ALS632B
This document contains information on products in
more than one phese of development. The status of
each device is indicated on the pagels) specifying its
electrical characteristics.
....
U)
LEDBD
MERR
DALLAS. TEXAS
7·89
75265
SN54AlS6328, SN54ALS633, SN54ALS6348, SN54ALS635
SN74ALS6328, SN74ALS633, SN54ALS6348, SN54ALS635
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
Read-modify-write (byte-control) operations can be performed with the' ALS632B and' ALS633 EDACs
by using output latch enable, LEDBO, and the individual OEBO thru OEB3 byte control pins.
<
r-
Diagnostics are performed on the EDACs by controls and internal paths that allow the user to read the
contents of the DB and CB input latches. These will determine if the failure occurred in memory or in the
EDAC.
~
~
CD
3
'ALS634B, 'ALS635 ... JD PACKAGE
'ALS634B, 'ALS635 ... FN PACKAGE
(TOP VIEW)
(TOP VIEW)
o
-<
MERR
ERR
OBO
OBl
OB2
OB3
OB4
OB5
OEOB
OB6
OB7
GNO
OB8
OB9
OB10
OBll
0812
OB13
OB14
OB15
CB6
CB5
CB4
OECB
~
D)
:::s
cc
D)
CD
3
CD
....:::s
.
"tJ
o
Co
c
n
....
..
(J)
VCC
51
50
OB31
OB30
OB29
OB2B
OB27
OB26
OB25
OB24
GNO
OB23
OB22
OB21
OB20
OB19
OB18
OB17
OB16
CBO
CBl
CB2
CB3
3
9
9 8
NC
OB3
OB4
OB5
OB7
7 6
5 4 3 2
1 68 67 6665 64 63 62 61
60
59
58
57
10
11
12
13
14
15
16
OB27
OB26
56
55
54
NC
OB25
OB24
GNO
GNO
OB23
OB22
NC
OB21
OB20
0819
OB18
53
52
51
50
17
18
19
20
21
49
48
47
46
22
23
24
45
25
26
44
2728293031323234353637383940414243
NC-No internal connection
TABLE 1. WRITE CONTROL FUNCTION
MEMORY
EDAC
CYCLE
FUNCTION
Write
Generate
check word
CONTROL
S1
L
SO
DB CONTROL
DB OUTPUT LATCH
OEBn OR
(' ALS632B, 'ALS633)
OEDB
LEDBO
DATA 1/0
L
Input
X
H
CB
CHECK 1/0 CONTROL
OECB
Output
check bitst
L
ERROR FLAGS
ERR
MERR
H
H
tSee Table 2 for details on check bit generation.
memory write cycle details
During a memory write cycle, the check bits (CBO thru CB6) are generated internally in the EDAC by seven
16-input parity generators using the 32-bit data word as defined in Table 2. These seven check bits are
stored in memory along with the original 32-bit data word. This 32-bit word will later be used in the memory
read cycle for error detection and correction. CBO, CB1 and CB2 are odd parity bits and CB3, CB4, CB5,
and CB6 are even parity bits. For example, for a data word of all zeros CBO-CB2 will be high and CB3-CB6
will be low.
7-90
TEXAS
"!}
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS. TEXAS 75265
SN54ALS632B, SN54ALS633, SN54ALS634B, SN54ALS635
SN74ALS632B, SN74ALS633, SN54ALS634B, SN54ALS635
32·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
TABLE 2. PARITY ALGORITHM
CHECK WORD
BIT
CBO
32-BIT DATA WORD
31 30 29 2B 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
X
X
CB1
CB2
X
X
X
X
X
X
CB3
X
X
X
X
X
X
X
X
X
X
CB4
X
X
CB5
X
X
X
X
X
X
X
X
CB6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7 6
X
X
X
X
5 4 3 2
X
X
X
X
X
....
t/)
1 0
(.)
X
X
X
X X
X
X
X
X
X
X
X
X X
X
X
X
X
X X
::::s
.
"0
X
o
c..
....c:
Q)
X
X
X
X
X
X
E
Q)
C)
The seven check bits are parity bits derived from the matrix of data bits as indicated by "X" for each bit.
CO
c:
CO
:2:
error detection and correction details
During a memory read cycle, the 7-bit check word is retrieved along with the actual data. In order to be
able to determine whether the data from memory is acceptable to use as presented to the bus, the error
flags must be tested to determine if they are at the high level.
The first case in Table 3 represents the normal, no-error conditions. The EDAC presents highs on both
flags. The next two cases of single-bit errors give a high on MERR and a low on ERR, which is the signal
for a correctable error, and the EDAC should be sent through the correction cycle. The last three cases
of double-bit errors will cause the EDAC to signal lows on both ERR and MERR, which is the interrupt
indication for the CPU.
TABLE 3. ERROR FUNCTION
TOTAL NUMBER OF ERRORS
ERROR FLAGS
DA T A CORRECTION
32-BIT DATA WORD
7-BIT CHECK WORD
ERR
MERR
0
0
H
Not applicable
1
0
1
1
L
L
H
H
H
L
L
Interrupt
0
L
L
Interrupt
2
L
L
Interrupt
0
1
2
0
Correction
Correction
Error detection is accomplished as the 7-bit,check word and the 32-bit data word from memory are applied
to internal parity generators/checkers. If the parity of all seven groupings of data and check bits are correct,
it is assumed that no error has occurred and both error flags will be high.
If the parity of one or more of the check groups is incorrect, an error has occurred and the proper error
flag or flags will be set low. Any single error in the 32-bit data word will change the state of either three
or five bits of the 7-bit check word. Any single error in the 7-bit check word changes the state of only
that one bit. In either case, the single error flag (ERR) will be set low while the dual error flag (MERR) will
remain high.
Any two-bit error will change the state of an even number of check bits. The two-bit error is not correctable
since the parity tree can only identify single-bit errors. Both error flags are set low when any two-bit error
is detected.
Three or more simultaneous bit errors can cause the EDAC to believe that no error, a correctable error,
or an uncorrectable error has occurred and will produce erroneous results in all three cases. It should be
noted that the gross-error conditions of all lows and all highs will be detected.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-91
~
o
E
Q)
:2:
(j)
...I
>
SN54ALS632B, SN54ALS633, SN54ALS634B, SN54ALS635
SN74ALS632B, SN74ALS633, SN54ALS634B, SN54ALS635
32·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
TABLE 4. READ. FLAG. AND CORRECT FUNCTION
<
rsa
MEMORY
EDAC
CONTROL
CYCLE
FUNCTION
S1
SO
s:
Read
Read & flag
H
L
3
Read
data & check
H
H
Latch input
CD
o
bits
-<
s:m
corrected data
m
(' ALS632B, 'ALS633)
OEDB
LEDBO
Input
H
X
Input
H
Enabledt
Latched
input
H
L
Latched
input
H
H
Enabledt
L
Enabledt
corrected
CB
CHECK I/O CONTROL
OECB
ERROR FLAGS
ERR
MERR
check word
Output
H
& syndrome bits
:::J
DB OUTPUT LATCH
OEBn OR
data
Output
Read
DB CONTROL
DATA I/O
Output
L
X
data word
syndrome
bitst
tSee Table 3 for error description.
tSee Table 5 for error location.
cc
CD
3
As the corrected word is made available on the data 110 port (DBa thru DB31), the check word I/O port
(CBO thru CB6) presents a 7-bit syndrome error code. This syndrome error code can be used to locate
the bad memory chip. See Table 5 for syndrome decoding.
CD
:::J
....
..
"'a
o
c
n
....
Co
..
tA
7-92
-I!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ALS632B, SN54ALS633, SN54ALS634B, SN54ALS635
SN74ALS632B, SN74ALS633, SN54ALS634B, SN54ALS635
32·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
TABLE 5. SYNDROME DECODING
SYNDROME BITS
6
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
5 4 3 2 1 0
L
L
L
L
L
L
L
L
L
L
L
L
L
L L H
L H L
L H H
L
L
L
L
L H L L
L H L H
L
L
L H H
L
L
L
L
L L H H H
L H L L L
L H L L H
L H L H L
L
L H L H H
L H H L L
L
L
L
L
L
L
L
L H H L H
L H H H L
L H H H H
L H
L H
L H
L
L
L
L L L
L L H
L H L
L H L L H H
L H L H L L
L H L H L H
L H L H H L
L H L H H H
L H H
L
L
L H H
L H H
L H H
L L H
L H L
L H H
L H H H L
L
L
L H H H L H
L H H H H L
L H H H H H
CB X=
OB Y=
2-bit =
unc =
ERROR
unc
2-bit
2-bit
unc
2-bit
unc
unc
2-bit
2-bit
unc
OB31
2-bit
unc
2-bit
2-bit
OB30
2-bit
unc
OB29
2-bit
OB28
2-bit
2-bit
OB27
OB26
2-bit
2-bit
OB25
2-bit
OB24
unc
2-bit
SYNDROME BITS
6
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
5 4 3 2 1 0
L
H L
H L
H L
H L
H L
L
L
L
L
L
L L
L H
L H
L
H
L
H
H L
H L
L H L
L H L H
L H H L
L
ERROR
H L L H H H
H L H L L L
H L H
H L H
H L H
H L H
L L H
L H L
L H H
H L
L
H L H H L H
H L H H H L
H L H H H H
H H L L L L
H H L L L H
H H
L
L H L
H H L L H H
H H L H L L
H H
L H L H
H H
H H
L H H L
L H H H
2-bit
unc
OB7
2-bit
OB6
2-bit
2-bit
OB5
OB4
2-bit
2-bit
OB3
2-bit
OB2
unc
2-bit
OBD
2-bit
2-bit
unc
2-bit
H H H H L H
H H H H H L
OBl
unc
2-bit
2-bit
unc
unc
2-bit
unc
2-bit
2-bit
H H H H H H
CB6
H H H
H H H
H H H
L L L
L L H
L H L
H H H L H H
H H H H L L
SYNDROME BITS
6
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
5 4 3 2 1 0
L
L
L
L
L
L
L
L
L
L
L L
L L
L L
L H
L
L H L H
L H H L
L H H H
H L L L
H L L H
H L H L
L
L
L
L
L
L H
H L
H H
L L
L
L
L
L
L
L
L
L
L
L
L
L H L H H
L H H L L
L H H L H
L H H H L
L H H H H
L
L
L
L
L H L
L H L
L H L
L L L
L L H
L H L
L H L L H H
L H L H L L
L H L H L H
L H L H H L
L H L H H H
L H H L
L
L
L H H L L H
L H H L H L
L H H L H H
L H H H L L
L H H H L H
L H H H H L
L H H H H H
ERROR
2-bit
unc
unc
2-bit
unc
2-bit
2-bit
unc
unc
2-bit
2-bit
OB15
2-bit
unc
OB14
2-bit
unc
2-bit
2-bit
OB13
2-bit
OB12
OBll
2-bit
2-bit
OB10
OB9
2-bit
OB8
2-bit
2-bit
CB5
SYNDROME BITS
6
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
5 4 3 2 1 0
H
L L L
L L H
L H L
L H H
L H L L
L
H L
H L
H L
H L
L
L
L
L
H
L
H
L
L H L H
L H H L
L H H H
H L L L
H L L H
H L H L
H L H H
H L
H L
H L
H L
H L
H L H H L L
H L H H L H
H L H H H L
H L H H H H
H H L
H H L
H H L
L L L
L L H
L H L
H H L L H H
H H L H L L
H H L H L H
H H L H H L
H H L H H H
H H H L L L
H H H L L H
H H H L H L
H H H L H H
H H H H L L
H H H H L H
H H H H H L
H H H H H H
ERROR
U)
.....
(J
unc
2-bit
2-bit
OB23
2-bit
OB22
OB21
2-bit
2-bit
OB20
OB19
2-bit
OB18
2-bit
2-bit
CB4
2-bit
OB16
unc
2-bit
OB17
2-bit
2-bit
CB3
unc
2-bit
2-bit
CB2
2-bit
CBl
CBO
none
:s
"C
...o
c.
.....
c:
Q)
E
Q)
C)
CO
c:
CO
:?i
...o>E
Q)
:?i
(j)
..
...J
>
error in check bit X
error in data bit Y
double-bit error
uncorrectable multibit error
read-modify-write (byte control) operations
The' ALS632B and' ALS633 devices are capable of byte-write operations. The 39-bit word from memory
must first be latched into the OB and CB input latches. This is easily accomplished by switching from the
read and flag mode (S 1 = H, SO = L) to the latch input mode (S 1 = H, SO = H). The EOAC will then
make any corrections, if necessary, to the data word and place it at the input of the output data latch.
This data word must then be latched into the output data latch by taking LEOBO from a low to a high.
Byte control can now be employed on the data word through the OEBO through OEB3 controls. OEBO
controls OBO-OB7 (byte 0)' OEB1 controls OB8-0B15 (byte 1)' OEB2 controls OB16-0B23 (byte 2), and
OEB3 controls OB24-0B31 (byte 3). Placing a high on the byte control will disable the output and the user
can modify the byte. If a low is placed on the byte control, then the original byte is allowed to pass onto
the data bus unchanged. If the original data word is altered through byte control, a new check word must
be generated before it is written back into memory. This is easily accomplished by taking control S 1 and
SO low. Table 6 lists the read-modify-write functions.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265
7-93
SN54ALS632B, SN54ALS633, SN54ALS634B, SN54ALS635
SN74ALS632B, SN74ALS633, SN54ALS634B, SN54ALS635
32·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
TABLE 6. READ-MODIFY-WRITE FUNCTION
<
r-
MEMORY
CYCLE
~
Read & Flag
Read
3:
3
CD
EDAC FUNCTION
Latch input data
Read
& check bits
o
-<
CONTROL
S1 SO
H
3:
Q)
::::I
H
H
H
,...
::::I
Iwrite
generate new
check word
...o"tJ
output
data
modified
L
L
ERR
MERR
H
Enabled
H
Enabled
check word
Hi-Z
~
H
H
r-----Output
H
-------
Syndrome
L
Enabled
bits
H
BYTEO
-----------Output
unchanged
ERROR FLAG
H
Output
check word
L
H
H
L
BYTEO
c.
c
(")
..
,...
en
byte or bytes &
input
L
H
word
Input
Modify appropriate
Modify
Input
CB
CONTROL
Latched
Latched
H
CHECK 1/0
Input
X
H
data
Q)
3CD
LATCH
Latched
output latch
CQ
CD
OEBnt
LEDBO
Input
L
Latch corrected
data word into
Read
DB OUTPUT
BYTEnt
tOEBO controls DBO-DB7 (BYTEO). OEB1 controls OB8-0B15 (BYTE1). OEB3 controls OB16-0B23 (BYTE2). OEB3 controls OB24-0B31
(BYTE3).
diagnostic operations
The ALS632B, , ALS633, , ALS634B and ' ALS635 are capable of diagnostics that allow the user to
determine whether the EDAC or the memory is failing. The diagnostic function tables will help the user
to see the possibilities for diagnostic control.
I
In the diagnostic mode (S1 = L, SO = H), the checkword is latched into the input latch while the data
input latch remains transparent. This lets the user apply various data words against a fixed known
checkword. If the user applies a diagnostic data word with an error in any bit location, the ERR flag should
be low. If a diagnostic data word with two errors in any bit location is applied, the MERR flag should be
low. After the checkword is latched into the input latch, it can be verified by taking OECB low. This outputs
the latched checkword. With the' ALS632B and' ALS633, the diagnostic data word can be latched into
the output data latch and verified. It should be noted that the ALS634B and' ALS635 do not have this
pass-through capability because they do not contain an output data latch. By changing from the diagnostic
mode (S1 = L, SO = H) to the correction mode (S1 = H, SO = HI, the user can verify that the EDAC
will correct the diagnostic data word. Also, the syndrome bits can be produced to verify that the EDAC
pinpoints the error location_ Table 7 (' ALS632B and' ALS633) and Table 8 (' ALS634B and' ALS635) list
the diagnostic functions.
I
7-94
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
D
SN54ALS632B, SN54ALS633, SN54ALS634B, SN54ALS635
SN74ALS632B, SN74ALS633, SN54ALS634B, SN54ALS635
32·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
TABLE 7. 'ALS632B,
EDAC FUNCTION
Read & flag
CONTROL
S1
SO
H
L
L
H
input latch remains
LEDBO
H
X
H
L
H
check bits
input
H
diagnostic
...c
Q)
-----
CO
Enabled
C
CO
H
~
syndrome
H
L
bits
~
Enabled
o
E
H
Q)
Output
syndrome bits
data word
Output corrected
Output
L
syndrome
H
L
bits
r------Hi-Z
~
Enabled
en
..J
>
..
----H
Output
corrected
L
diagnostic
syndrome bits
Enabled
C)
r-------Hi-Z
diagnostic
H
H
L
check bits
r------Hi-Z
Output
H
H
Output
input
H
.
o
c.
H
H
E
Q)
Output latched
H
H
data word
H
U
::J
check bits
Latched
Output diagnostic
VI
MERR
Latched
diagnostic
H
ERR
"C
Input correct
data word t
H
...
ERROR FLAGS
OECB
Input
L
input latch
word & output
OEBn
CB
CONTROL
CHECK 1/0
data word t
Latch diagnostic
diagnostic data
LATCH
Input
output latch
data word &
DB OUTPUT
diagnostic
Latch diagnostic
data word into
DB BYTE
Input correct
transparent
data word into
DIAGNOSTIC FUNCTION
CONTROL
data word
Latch input check
word while data
DATA 1/0
'~LS633
syndrome
L
L
bits
Enabled
------- f - - - - Hi-Z
data word
H
tDiagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case, the diagnostic data
word will contain errors in two bit locations.
TABLE 8. 'ALS634B, 'ALS635 DIAGNOSTIC FUNCTION
EDAC FUNCTION
Read & flag
CONTROL
S1
SO
H
L
L
H
Latch input check
bits while data
input latch remains
check bits
H
H
data word
check bits
diagnostic
Latched input
H
check bits
Output input
H
diagnostic
check bits
data word t
Output
Latched input
H
H
H
diagnostic
syndrome bits
r-------Hi-Z
data word
Output corrected
data word
Input correct
Input
L
input latch
diagnostic
Input correct
data word t
Latch diagnostic
data into
CHECK 1/0
OEDB
Input
transparent
Output input
DB CONTROL
DATA 1/0
Output
Output corrected
H
H
diagnostic
data word
L
syndrome bits
r-----Hi-Z
CB CONTROL
OECB
H
ERROR FLAGS
ERR
H
MERR
H
H
Enabled
L
Enabled
L
---H---L
Enabled
Enabled
---H----
tDiagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case, the diagnostic data
word will contain errors in two bit locations.
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-95
SN54ALS632B, SN54ALS633, SN74ALS632B, SN74ALS633
32·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
, ALS632B, , ALS633 logic diagram (positive logic)
DECODER
X/Y
<
r-
0
~
~
0"'
r-
3:
CD
3
so -
o
Sl - 2
-<
I
7,
3
1
3 ~
2f-
1
SYNDROME
GENERATOR
=1
~
r---
~1
I
t-Zr-
CHECK·BIT
3ENERATOR
-
~
CBl
~
~
-+-
3:
'~
"""
D)
:s
D)
LATCHES
CB5
~
CC
-
CD
3
CBOCB6
CD
,..:s
C1
10
7~
~
7
,
--
.
MUX
~
"tJ
r
-
LATCHES
""-
' - Cl
DBO·D B31
32
32
"
~~
10
7
,
•
EN
-
ERROR
C>--ER"R
MUL TI·
ERROR
P--MERR
32.,
32"
BUFFERS
ERROR
CORRECTOR
<]
=1
OE DB
.... 32"
,
EN
432
[32
X·OR]
... EN
"
-
f-
*
BIT·IN·
ERROR
DECODER
~
l
·'ALS634B has a 3·state (\7) check· bit and data outputs.
'ALS635 has open·collector (Q) check· bit and data outputs.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-97
SN54ALS632B, SN54ALS634B, SN74ALS632B, SN74ALS634B
32-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: eB and DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
All others .......... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Operating free-air temperature range:
SN74ALS632B, SN74ALS634B .............................. ooe to 70 0 e
Operating case temperature range:
SN54ALS632B, SN54ALS634B .......................... -55°eto 125°e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 °e to 150 °e
<
r~
3:
CD
3
o
-<
3:
recommended operating conditions
C»
:s
SN54ALS632B
(Q
SN54ALS634B
C»
CD
3
VCC
Supply voltage
:s
VIH
High-level input voltage
...o"'tI
VIL
Low-level input voltage
CD
~
Co
IOH
High-level output current
IOL
Low-level output current
tw
Pulse duration
c
(")
~
-
en
NOM
MAX
4.5
5
5.5
4.5
5
5.5
SO! or 5H t
(4) LEDBO high before 51l (SO = H)
(5) Diagnostic data word before 51 l
(50=H)
(6) Diagnostic check word before the
later of 51! or SOl
(7) Diagnostic data word before
LEDBOl (51 =L and 50=H)t
(8) Read-mode, SO low and 51 high
(9) Data and check word after SOl
(51 =H)
(10) Data word after 511 (50=H)
(11) Check word after the later of
5H or SOl
(12) Diagnostic data word after
LEDBOl (51 =L, 50=H)t
tcorr Correction time (see Figure 1) §
Operating case temperature
0.8
-0.4
-0.4
-1
-2.6
4
8
12
24
20
7
5
30
30
0
0
0
0
7
5
10
7
17
15
27
25
12
12
mA
mA
ns
10
12
10
0
0
ns
37
ns
0
°c
°c
125
-55
V
ns
10
~
43
Operating free-air temperature
V
V
0.6
20
TC
TA
2
ERR or MERR
(3) LEDBO high before the earlier of
Hold time
MIN
DB or CB
(51 =H)
th
MAX
DB or CB
LEDBO low
UNIT
NOM
ERR or MERR
(2) SO high before LEDBOl (51 =H)t
Setup time
SN74ALS634B
MIN
2
(1) Data and check word before SOl
tsu
SN74ALS632B
70
t These times ensure that corrected data is saved in the output data latch.
t These times ensure that the diagnostic data word is saved in the output data latch.
§ The tcorr specification includes the minimum setup time t su (1). The correction time from SO going high to valid data is equal to tcorr
minus t su (1)'
7-98
TEXAS
~
INSTRUMENTS
POST OFFICE .BOX 655012 - DALLAS. TEXAS 75265
SN54ALS6328, SN74ALS6328
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
WITH 3·STATE OUTPUTS
electrical characteristics over recommended operating temperature range (unless otherwise noted)
PARAMETER
MIN
II = -18 mA
VCC = 4.5 V to 5.5 V, 10H = -0.4 mA
VCC = 4.5 V,
10H = -1 mA
VCC = 4.5 V,
10H = -2.6 mA
Typt
All outputs
VOH
DB or CB
VCC- 2
2.4
2.4
0.25
0.4
0.4
0.35
0.5
0.25
0.4
0.35
0.5
VCC = 4.5 V,
10l = 12 mA
VCC = 4.5 V,
10l = 24 mA
50 or 51
VCC = 5.5 V,
VI = 7 V
0.1
0.1
All others
VCC = 5.5 V,
VI = 5.5 V
0.1
0.1
VCC = 5.5 V,
VI = 2.7 V
20
20
20
20
-0.4
-0.4
50 or 51
VCC = 5.5 V,
VI = 0.4 V
10§
VCC = 5.5 V,
ICC
VCC = 5.5 V,
Vo = 2.25 V
5ee Note 1
V
CJ
::l
"'0
V
a..
..
....,
o
3.2
0.25
10l = 8 mA
50 or 51
en
....,
VCC-2
3.3
0.25
0.4
All others:!:
III
-1.2
VCC = 4.5 V,
DB or CB
UNIT
MAX
10l = 4 mA
Val
IIH
Typt
VCC = 4.5 V,
ERR or MERR
II
MIN
MAX
-1.2
VCC = Open,
VIK
SN74AlS632B
SN54AlS632B
TEST CONDITION
All others+
-112
157
Q)
E
Q)
C)
CO
C
CO
mA
~
.
p.A
>
o
mA
E
Q)
:2:
Ui
.....I
-0.1
-0.1
-30
C
V
-30
157
250
-112
mA
250
mA
tAli typical values are at VCC = 5 V, TA = 25°C.
+For I/O ports, the parameters IIH and III include the off-state output current.
§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, 105.
NOTE1: ICC is measured with 50 and 51 at 4.5 V and all CB and DB pins grounded.
. .
>
switching characteristics over recommended ranges of supply voltage and operating temperature
(see Note 2)
PARAMETER
tpd
tpd
FROM
TO
(INPUT)
(OUTPUT)
DB and CB
ERR
DB
SN74AlS632B
SN54AlS632B
TEST CONDITIONS
MIN
MAX
MIN
MAX
51 =H, 50=l, Rl=5000
5
32
5
30
ERR
51 =l, 50=H, Rl=5000
5
32
5
30
DB and CB
MERR
51 =H, 50=l, Rl=5000
6
39
6
37
DB
MERR
51 =l, 50=H, Rl=5000
6
39
6
37
UNIT
ns
ns
tpd
501 and 511
CB
Rl =R2=5000
5
35
5
32
ns
tplH
501 and 511
ERR
RL = 5000
3
21
3
19
ns
tpd
DB
CB
51 =L, 50=l, Rl =R2=5000
5
33
5
30
ns
tpd
LEDBOI
DB
51=X,50=H,Rl=R2=5000
3
20
3
18
ns
tpd
511
CB
50=H, Rl =R2=5000
4
26
4
24
ns
ten
OECBI
CB
50=H,51=X, Rl=R2=5000
1
24
1
22
ns
tdis
OECBI
CB
50=H,51=~
Rl=R2=5000
1
22
1
20
ns
ten
OEBO thru OEB31
DB
50=H,51=X, Rl=R2=5000
1
24
1
22
ns
tdis
OEBO thru OEB31
DB
50=H,51=X, Rl=R2=500n
1
22
1
20
ns
NOTE 2: load circuit and voltage waveforms are shown in 5ection 1 of the LS/ Logic Data Book, 1986.
-I!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-99
SN54ALS634B, SN74ALS634B
32·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
WITH 3·STATE OUTPUTS
electrical characteristics over recommended operating temperature range (unless otherwise noted)
<
r-
PARAMETER
~
VCC = 4.5 V,
VIK
s:
All outputs
VOH
CD
3
c
ERR or MERR
-<
VOL
s:m
DB or CB
:::s
m
II
cc
IIH
2.
VCC = 4.5 V,
10L = 24 rnA
0.25
0.25
0.4
0.4
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
VI = 7 V
0.1
0.1
0.1
0.1
20
20
20
20
-0.4
-0.4
-0.1
-0.1
VCC = 5.5 V,
All others l
SO, 51, or OEDB
c..
c
10L = 12 rnA
3.2
2.4
VI = 5.5 V
All others l
"'C
C
VCC = 4.5 V,
VCC = 5.5 V,
VI = 2.7 V
VI = 0.4 V
10§
VCC = 5.5 V,
Vo = 2.25 V
ICC
VCC = 5.5 V,
5ee Note 1
V
V
3.3
VCC = 5.5 V,
IlL
.,
10L = 8 mA
UNIT
VCC-2
VCC = 5.5 V,
:::s
~
10L = 4 mA
VCC = 4.5 V,
VCC- 2
2.4
-1.5
SO or 51
SO or 51
3
-1.5
II = -18 rnA
VCC = 4.5 V,
MIN
All others
CD
CD
MIN
VCC = 4.5 V to 5.5 V, 10H = -0.4 rnA
VCC = 4.5 V,
10H = -1 rnA
VCC = 4.5 V,
10H = -2.6 rnA
DB or CB
SN74ALS634B
Typt
MAX
SN54ALS634B
Typt
MAX
TEST CONDITIONS
-112
-30
150
-30
250
150
V
mA
p.A
mA
-112
mA
250
mA
t All typical values are at VCC = 5 V, T A = 25°C.
l For 1/0 ports, the parameters IIH and IlL include the off-state output current.
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.
NOTE 1: ICC is measured with SO and 51 at 4.5 V and all CB and DB pins grounded.
t/)
. .
switching characteristics over recommended supply voltage range and operating temperature range
(see Note 2)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
SN54ALS634B
TEST CONDITIONS
SN74ALS634B
MIN
MAX
MIN
MAX
51 =H, 50=L, RL=500 fl
5
34
5
30
51 =L, 50=H, RL=500 fl
5
34
5
30
51 = H, 50 = L, RL = 500 fl
6
39
6
37
51 =L, SO=H, RL=500 fl
6
39
6
37
35
5
32
tpd
DB and CB
ERR
tpd
DB and CB
MERR
tpd
SO! and S1!
CB
R1 =R2=500 fl
5
tpLH
ns
ns
SO! and SH
ERR
RL = 500 fl
3
21
3
19
ns
tpd
DB
CB
S1 =L, SO=L, R1 =R2=500 fl
5
33
5
30
ns
tpd
S11
CB
SO=H, R1 =R2=500 fl
4
26
4
24
ns
ten
OECB!
CB
S1 =X, SO=H, R1 =R2=500 fl
1
24
1
22
ns
tdis
OECBf
CB
51 =X, SO=H, R1 =R2=500 fl
1
22
1
20
ns
ten
OEDB!
DB
S1 =X, SO=H, R1 =R2=500 fl
1
24
1
22
ns
tdis
OEDBf
DB
S1 =X, SO=H, R1 =;R2=500 fl
1
22
1
20
ns
NOTE 2: Load circuit and voltage waveforms are shown in Section 1 of the LSI Logic Data Book, 1986.
7-100
UNIT
TEXAS
l!I
INSTRUMENTS
POST OFFICE BOX 655012 • PALLAS. TEXAS 75265
SN54ALS633, SN54ALS635
SN74ALS633, SN74ALS635
32-BIT PARAllEL ERROR DETECTION AND CORRECTION CIRCUITS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: eB and DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
All others. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Operating free-air temperature range:
. ....... ooe to 70 0 e
SN74ALS633 and SN74ALS635 .
Operating case temperature range:
SN54ALS633 and SN54ALS635 ...
-55°e to 125°e
Storage temperature range ....... .
- 65 °e to 150 0 e
....CJen
::l
"C
...o
c..
....r::::
Q)
E
Q)
recommended operating conditions
VCC
5upply voltage
V,H
High-level input voltage
V,L
Low-level input voltage
C)
High-level output current
IOL
Low-level output current
tw
Pulse duration
SN54ALS635
SN74ALS635
r::::
CO
UNIT
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
ERR or MERR
DB or CB
I
'AL5634A
ERR or MERR
DB or CB
LEDBO low
(51 =H)
(2) 50 high before LEDBOt (51 =H)t
(3) LEDBO high before the earlier of
50! or 5H t
5etup time
(4) LEDBO high before 51 t (50 = H)
(5) Diagnostic data word before 51 t
(50=H)
(6) Diagnostic check word before the
later of 51! or 50t
(7) Diagnostic data word before
LEDBOt (51 =L and 50=H)+
(8) Read-mode, 50 low and 51 high
(9) Data and check word after 50t
(51 =H)
Hold time
(10) Data word after 51 t (50 = H)
(11) Check word after the later of
51! or 50t
(12) Diagnostic data word after
LEDBOt (51 =L, 50=H)+
2
~
~
V
o
V
0.6
0.8
-0.4
-0.4
-1
-2.6
tcorr Correction time (see Figure 1) §
Operating case temperature
4
8
12
24
45
25
15
10
45
45
E
V
~
mA
en....I
>
-
ns
~
a
a
a
28
10
:>w
15
10
c..
35
20
(.)
35
30
20
15
20
15
20
15
a
a
65
w
ns
a:
t-
=>
C
o
-55
a:
c..
ns
58
ns
a
°c
°c
125
Operating free-air temperature
mA
a
TC
TA
CO
MIN
2
(1) Data and check word before 50t
th
SN74ALS633
Q)
IOH
tsu
SN54ALS633
70
t These times ensure that corrected data is saved in the output data latch.
+ These times ensure that the diagnostic data word is saved in the output data latch.
§ The tcorr specification includes the minimum setup time tsu( 1). The correction time from 50 going high to valid data is equal to tcorr
minus tsu( 1)·
PRODUCT PREVIEW documents contain information
on products in the formative or design phase of
development. Characteristic data and other
specifications are design goals. Texas Instruments
reserves the right to change or discontinue these
products without notice.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-101
I
SN54ALS633, SN74ALS633
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
WITH OPEN·COLLECTOR OUTPUTS
electrical characteristics over recommended operating temperature range (unless otherwise noted)
<
r-
PARAMETER
SN54ALS633
Typt
MAX
TEST CONDITIONS
MIN
~
VIK
s:
CD
VOH
ERR or MERR
Vee = 4.5 V to 5.5 V, 10H = -0.4 mA
10H
DB or CB
Vee = 4.5 V,
VOH = 5.5 V
Vee = 4.5 V,
3
ERR or MERR
o
-<
s:
VOL
:::s
II
Q)
Q)
(Q
DB or CB
IIH
CD
:::s
r+
IlL
...o-g
10§
a
(/)
10L = 8 mA
VCC = 4.5 V,
10L = 12 mA
VCC = 4.5 V,
10L = 24 mA
0.25
0.25
0.1
0.4
0.4
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
Vce = 5.5 V,
VI = 7 V
0.1
0.1
VCC = 5.5 V,
VI = 5.5 V
0.1
0.1
20
20
20
20
-0.4
-0.4
-0.1
-0.1
VCC = 5.5 V,
VI = 2.7 V
Vce = 5.5 V,
All others;
ERR or MERR
ICC
VI = 0.4 V
VCC = 5.5 V,
Vo = 2.25 V
VCC = 5.5 V,
5ee Note 1
-30
-112
150
-30
250
UNIT
V
V
0.1
50 or 51
50 or 51
C
10L = 4 mA
-1.5
VCC- 2
Vcc- 2
All others;
3
c.
VCC = 4.5 V,
Vec = 4.5 V,
-1.5
All others
50 or 51
CD
II = -18 mA
SN74ALS633
Typt
MAX
MIN
150
mA
V
mA
p.A
mA
-112
mA
250
mA
;
t All typical values are at Vee = 5 V, T A = 25°C.
For 1/0 ports, the parameters IIH and IlL include the off-state output current.
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, 105.
NOTE 1: ICC is measured with 50 and 51 at 4.5 V and all CB and D8 pins grounded .
switching characteristics over recommended ranges of supply voltage and operating temperature
. . (see Note 2)
"'C
::a
o
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
DB and CB
ERR
DB
ERR
DB and CB
MERR
SN54ALS633
TEST CONDITIONS
SN74ALS633
UNIT
MIN
MAX
MIN
MAX
51 =H, 50=L, RL=500
10
43
10
40
51 =L, 50=H,
10
43
10
40
15
67
15
55
15
67
15
55
10
75
10
60
ns
5
30
5
25
ns
n
RL=500 n
RL=500 n
RL = 500 n
c
tpd
(")
tpd
-t
tpd
50~
and 5H
eB
RL =680
"'C
tpLH
50~
and 5H
ERR
RL =500
tpd
D8
CB
51 = L, 50 = L, RL = 680
10
70
10
60
ns
tpd
LEDBO~
DB
51 =X,
15
70
15
50
ns
tpd
51t
CB
50=H,
10
60
10
45
ns
tpLH
OECBf
CB
51 =X,
2
35
2
30
ns
tpHL
OEeB~
eB
51 =X,
2
35
2
30
ns
tpLH
OEBO thru OEB3f
DB
51 =X,
2
35
2
30
ns
tpHL
OEBO thru 0EB3~
DB
51 =X,
2
35
2
30
ns
c
::a
m
-<
m
~
51 =H, 50=L,
51 = L, 50 = H,
n
n
n
50=H, RL=680 n
RL =680 n
50=H, RL=680 n
50=H, RL=680 n
50=H, RL =680 n
50=H, RL=680 n
NOTE 2: Load circuit and voltage waveforms are shown in 5ection 1 of the LSI Logic Data Book, 1986.
7-102
PRODUCT PREVIEW documents contain information
on products in the formative or design ~hase of
development. Characteristic data ani! other
specifications are design goals. Texas Instruments
reserves the right to change or discontinue these
products without notice.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ns
ns
SN54ALS635, SN74ALS635
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
WITH OPEN·COLLECTOR OUTPUTS
electrical characteristics over recommended operating temperature range (unless otherwise noted)
PARAMETER
VOH
ERR or MERR
10H
DB or CB
VCC = 4.5 V to 5.5 V, 10H = -0.4 mA
VOH = 5.5 V
0.1
0.4
0.25
10L = 8 mA
VCC = 4.5 V,
10L = 12 mA
VCC = 4.5 V,
10L = 24 mA
SO or Sl
VCC = 5.5 V,
VI = 7 V
Ali others
VCC = 5.5 V,
VI = 5.5 V
VCC = 5.5 V,
VI = 2.7 V
JlA
VCC = 5.5 V,
VI = 0.4 V
mA
SO or Sl
Ali others i
SO or Sl
Ali others i
ERR or MERR
ICC
0.4
...o
mA
10L = 4 mA
0.25
"C
V
VCC-2
0.1
0.25
CJ
::s
V
VCC = 4.5 V,
DB or CB
10§
VCC- 2
-1.5
c..
0.4
0.35
0.5
0.25
0.4
0.35
0.5
V
mA
VCC = 5.5 V,
Vo = 2.25 V
VCC = 5.5 V,
See Note 1
-30
-112
-30
150
-112
150
~
o
E
CD
mA
::21
mA
l Ali typical values are at VCC = 5 V, TA = 25 °C.
i For 1/0 ports, the parameters IIH and IlL include the off-state output current.
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.
NOTE1: ICC is measured with SO and Sl at 4.5 V and ali CB and DB pins grounded.
switching characteristics over recommended ranges of supply voltage and operating temperature
(see Note 2)
PARAMETER
FROM
TO
SN54ALS635
MIN Typt
MAX
TEST CONDITIONS
(INPUT)
(OUTPUT)
DB and CB
ERR
51 =H, 50=L, RL=500
DB
ERR
S 1 = L, 50 = H, RL = 500
tpd
51 =H, 50=L, RL=500
tpd
DB and CB
MERR
tpd
5m and 5U
CB
RL =680
tpLH
5m and
ERR
RL =500
51~
51 = L, 50 = H, RL = 500
n
n
n
n
n
n
n
tpd
DB
CB
51 =L, 50=L, RL=680
tpd
51 i
DB
SO=H, RL =680
OECBi
CB
51 = X, SO = H, RL = 680
tpLH
...en
UNIT
VCC = 4.5 V,
VOL
IlL
SN74ALS635
Typt
MAX
MIN
-1.5
VCC = 4.5 V,
ERR or MERR
IIH
MIN
II = -18 mA
VCC = 4.5 V,
VIK
II
SN54ALS635
Typt
MAX
TEST CONDITIONS
n
tpHL
OECB~
CB
51 =X, 50=H, RL =680
tpLH
OEDBi
DB
51 =X, 50=H, RL=680
tpHL
OEDB~
DB
51 =X, 50=H, RL =680
n
n
n
n
SN74ALS635
MIN Typt
MAX
26
26
..
UNIT
~g:::~::~~~Sr:::~t dt~S~\~~::I~·r ~~~~~~~~~~~~~::
products without notice.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
>
~
w
:>w
ns
26
26
40
40
40
40
40
40
ns
14
14
ns
(.)
::>
a:
D..
ns
40
40
ns
40
40
ns
24
24
ns
24
24
ns
24
24
ns
24
24
ns
....
c
o
a:
D..
tAli typical values are at VCC = 5 V, TA = 25°C.
NOTE 2: Load circuit and voltage waveforms are shown in 5ection 1 of the LSI Logic Data Book, 1986.
PRODUCT PREVIEW documents contain information
on products in the formative or design phase of
development. Characteristic data and other
Cii
-I
7-103
I
SN54ALS632B, SN54ALS633, SN54ALS634B, SN54ALS635
SN74ALS632B, SN74ALS633, SN54ALS634B,SN54ALS635
32·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
I4-----READ---t~I·t----------CDRRECT----------~tl
I
I
~thI81----+!
<
r-
I
rl------------------------------------------~I~'__________
so-l
~
I
:~
I4- d,·,-too
tcorrection-------+ttlll
+-t,ulll~th(91-"
3:
3
CD
DBO THRU DB31
o
t
I
I
-------~:==:!~~$I~~====~I~~~~====:jI~~~~~~~~~~:2~~~---INPUT DATA WORD
OUTPUT CORRECTED DATA WORD
I
If--ten----tl
I
-<
~I--------------------------------~
OEBO THRU 0EB3
If--t su l l l - - :t j 4 - t hI91--Jt
I
It-- -too
I
I
tdis
-!
CBOTHRUCM------~==:I~N~PU~T~C~HE~C~K~W~DR~D~==~ZE~~c:====)C==~oU~T~P~UT~S~Y~ND~R~D~M~EC~O~D~E==~~~~~---
3:
D)
I
:::J
14-- t en ----.\
D)
CQ
i
I
I
CD
~tpd~
3
ERR
CD
f$//41~VAL(DW$ ff
.
4~Jla)M
$r--------------VA-L-ID"""E""R""R,.-F-LA-G-----------------..W
~
:::J
....
_I
tpd
"C
oQ.
FIGURE 1. READ, FLAG, AND CORRECT MODE SWITCHING WAVEFORMS
C
(')
....
o
14--- th181~
SO:
j4--READ
SI..-J
DBO THRU DB?
---<
i~--------------------~------------~I
_I_
CORRECT
tl_
WRITE
I
:
I
I
I
I
»»)
OUTPUT CORRECTED DATA WORD
INPUT DATt WORD
WK:)(
t
INPUT MODIFIED BYTE 0
I
DB8 THRU DB15
INPUT DATA WORD
OUTPUT CORRECTED DATA WORD
DB16 THRU DB23
INPUT DATA WORD
OUTPUT CORRECTED DATA WORD
DB24 THRU DB31
INPUT DATA WORD
OUTPUT CORRECTED DATA WORD
DEBO
~
~
____________________ __________
~
~r----
____________________________-+_______________
~r----
r----
I
I
I
Jf-lsuI31-+t
I+--- t su121---+t
UoBo ....
~,....~.....
~~~,....~.....
~
.....~
....~
....
~,....~....
~
-.WI!&/I////#/II////I///f
I.--tw--+l
INPUT CHECK WORD
________________ ____________
~
OUTPUT SYNDROME CODE
JI
\~________~V~A~LI~D~ER~R~F~LA~G~________
\~_______V_A_LI~D~M~ER~R~F~LA~G~____
_JI
FIGURE 2. READ, CORRECT, MODIFY MODE SWITCHING WAVEFORMS
-I.!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
~r----
OUTPUT CHECK WORD
I
k-tpd~
7-104
~
I
~
CBO THRU CB6
:
SN54ALS6328, SN54ALS633, SN54ALS6348, SN54ALS635
SN74ALS6328, SN74ALS633, SN74ALS6348, SN54ALS635
32·811 PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
L
so
uI51 -+i
Sl
:!4-'.
~I-----------------------------------------
II
I
~""'''''''''''''''''''''''''''''''''''''''''+I'''''''''''''''~I
DBO THRU DB31
INPUT VALID DATAWORO
:::s
INPUT DIAGNOSTIC DATA WORD
OUTPUT DIAGNOSTIC
DATA WORD
Q.
-+:____________~r_____
:
LI_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
I
1 : -
'sul7l-4!...---I.~I.H.*!-'SUI41:
I
j+-'Pd..t
~:--------------------_+:--~~I--~l---------r!---------------;I~------------------.......
:
I4-'SU(6I-+--'h(111~
CBO
THRU
CB6
o
,
oEBO--------~:~------------------_+I------_+I--------~:
I,
I
lE!rnO ________
..
."C
l4--'hl10l--+i
THRU:
OEB3
~
:
i+-+-'h1121-----.l
:
:
l4--'pd----l
I
I
r-.
~'Pd___+! _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
ERR
MEiiR
-""i
,
__
__ !I
VERIFY PROPER OPERATION OF ERR FLAG
,
VERIFY PROPER OPERATION OF ERR FLAG, FLAG SHOULD BE LOW
.....~.......,...-J ' - _ _ _ ..!."~A~~~~!!.E!!I!!H.l. _ _ _ _ J
WITH A DIAGNOSTIC DATA WORD WITH ASINGLE ERROR
~'~
I4---'Pd-+!________________________________ _
VERIFY PROPER OPERATION OF MERR FLAG
__....................--1 \.. _ _ _ ~.:.A~ S~O~L~ ~ ~~!..
___ ./
VERIFY PROPER OPERATION OF
ii1EiiR
FLAG, FLAG SHOULD BE LOW
~___W__IT__H_A__D__I_AG_N_O_ST_IC_D_A_T_A_W_O_RD_W_I_TH_A_DO_U_B_LE_E_R_R_O_R_ _ __
FIGURE 3. DIAGNOSTIC MODE SWITCHING WAVEFORM
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
C
Q)
E
Q)
en
c
C'O
:E
OUTPUT SYNDROME CODE
1'~~~~~~~.,'~'~------~I------~------J~---------------------------------'d-il~1.~.l
I
.....
C'O
i..--'Pd4
OUTPUT VALID CHECK WORD
I
o
.....
Co)
~
o
E
Q)
:E
en
>
....I
-
7-105
<
r-
~
3:
3
CD
o
-<
3:
m
:::s
m
cc
CD
3
CD
:::s
r+
..."tJ
o
c.
c
(')
-
r+
en
7-106
SN54AS632, SN54AS634
SN74AS632, SN74AS634
32·811 PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
02661. JANUARY 1986 - REVISED JUNE 1987
•
Detects and Corrects Single· Bit Errors
o
Detects and Flags Dual·Bit Errors
o
Built·ln Diagnostic Capability
o
Fast Write and Read Cycle Processing
Times
•AS632 ... JD PACKAGE
(TOP VIEW)
•
Byte·Write Capability ... 'AS632
o
Dependable Texas Instruments Quality and
Reliability
LEDBO
MERR
ERR
OBO
OBl
082
OB3
OB4
085
OEBO
OB6
OB7
GNO
OB8
OB9
OEBl
OB10
OBll
OB12
OB13
0814
OB15
CB6
CB5
CB4
OECB
description
The 'AS632 and 'AS634 devices are 32-bit
parallel error detection and correction circuits
(EDACs) in 52-pin (' AS632) or 48-pin (' AS634)
600-mil packages. The EDACs use a modified
Hamming code to generate a 7-bit check word
from a 32-bit data word. This check word is
stored along with the data word during the
memory write cycle. During the memory read
cycle, the 39-bit words from memory are
processed by the EDACs to determine if errors
have occurred in memory.
...
tn
VCC
51
50
OB31
OB30
0829
OB28
OB27
OB26
OEB3
OB25
OB24
GNO
0823
OB22
OEB2
0821
OB20
OB19
OB18
0817
OB16
CJ
::s
"C
0
...
c..
...c:
Q)
E
Q)
C)
CO
c:
CO
a
...0>
E
Q)
2
(j)
..J
>
CB2
CB3
•AS632 ... FN PACKAGE
(TOP VIEW)
In:
1
n:1~
N'-OCCCI:
Single-bit errors in the 32-bit data word are
flagged and corrected.
U U CD CD CD
LJ.J
5l
UU
~
0 en
MMN
u u ~ 0 CD CD CD U U
ZZOOOLJ.J~~»~~ooozz
9 8 7 6 5 4 3 2 1 68 67 666564 63 62 61
Single-bit errors in the 7-bit check word are
flagged, and the CPU sends the EDAC through
the correction cycle even though the 32-bit data
word is not in error. The correction cycle will
simply pass along the original 32-bit data word
in this case and produce error syndrome bits to
pinpoint the error-generating location.
Dual-bit errors are flagged but not corrected.
These errors may occur in any two bits of the
39-bit data word from memory (two errors in the
32-bit data word, two errors in the 7-bit check
word, or one error in each word). The gross-error
condition of all lows or all highs from memory
will be detected. Otherwise, errors in three or
more bits of the 39-bit word are beyond the
capabilities of these devices to detect.
NC
OB3
OB4
OB5
OEBO
OB6
OB7
GNO
GNO
OB8
OB9
OEBl
OB10
OBll
OB12
0813
OB14
~
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
NC
NC
OB28
OB27
OB26
OB25
OB24
0819
OB18
2728293031323234353637383940414243
NC - No internal connection
PRODUCTION DATA docunients contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~ai~:I~~~ ~!~~~~ti~r :I~o~:~:~~t:r~~s not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright'S 1986. Texas Instruments Incorporated
7-107
SN54AS632, SN54AS634
SN74AS632, SN74AS634
32-81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
Read-modify-write (byte-control) operations can be performed with the' AS632 EDAC by using output
latch enable, LEDBO, and the individual OEBO thru OEB3 byte control pins.
<
r-
Diagnostics are performed on the EDACs by controls and internal paths that allow the user to read the
contents of the DB and CB input latches. These will determine if the failure occurred in memory or in the
EDAC.
~
s:
CD
'AS634 ... JD PACKAGE
(TOP VIEW)
3
o
-<
a:
MERR
ERR
s:
C)
::s
CQ
CD
3
CD
::sr+
.
"C
o
a.
c
()
r+
(I)
N~Oa:a:
vCC
51
50
OB31
OB30
OB29
OB28
OB27
OB26
OB25
OB24
GNO
OB23
OB22
OB21
OB20
OB19
OB18
OB17
OB16
CBO
CBl
CB2
CB3
DBa
OBl
OB2
OB3
OB4
OB5
OEDB
OB6
OB7
GNO
OB8
OB9
OB10
OBll
OB12
OB13
OB14
OB15
CB6
CB5
CB4
OECS
C)
'AS634 ... FN PACKAGE
(TOP VIEW)
U
Z
9
U
LJ.J
II~
U
Z
5 4
3
2
aJ aJ aJ
0
zoo
8
7
6
Ia:
LJ..l
UU
U U
> >
~
~
0
(f)
(f)
0
OJ
MMN
aJ aJ aJ U
0 0 0 Z
U
Z
1 6867666564636261
10
NC
NC
OB28
OB27
OB26
NC
OB25
OB24
GNO
GNO
OB23
OB22
NC
OB21
OB20
OB19
OB18
60
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
2728293031323234353637383940414243
NC - No internal connection
TABLE 1. WRITE CONTROL FUNCTION
MEMORY
EDAC
CYCLE
FUNCTION
Write
Generate
check word
CONTROL
S1
L
SO
DB CONTROL
DATA 1/0
L
OEBn OR
DB OUTPUT LATCH
I'AS632)
OEDB
LEDBO
H
Input
X
CB
CHECK 1/0 CONTROL
OECB
Output
check bitst
L
ERROR FLAGS
ERR
MERR
H
H
tSee Table 2 for details on check bit generation.
memory write cycle details
During a memory write cycle, the check bits (CBO thru CB6) are generated internally in the EDAC by seven
16-input parity generators using the 32-bit data word as defined in Table 2. These seven check bits are
stored in memory along with the original 32-bit data word. This 32-bit word will later be used in the memory
read cycle for error detection and correction. CBO, CB1 and CB2 are odd parity bits and CB3, CB4, CB5,
and CB6 are even parity bits. For example, for a data word of all zeros CBO-CB2 will be high and CB3-CB6
will be low.
7-108
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54AS632. SN54AS634
SN74AS632. SN74AS634
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
TABLE 2. PARITY ALGORITHM
CHECK WORD
U)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
CBO
X
CBl
CB2
CB3
CB4
CB5
CB6
..,
32·BIT DATA WORD
BIT
8
7
6
5 4
3 2
1 0
X X
X
X X X
X
X
X X X X
X
X
X
X X
X
X
X
X
X
X X X
X
X
X
X
X
X X
X X
X
X X
X
X
X X
X X
X
X X X
X X X
X
X X X
X X
X X X
X X
X X X X X X
X X
X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X
X X X X X X X X
(,)
::s
X
X
X
X
"C
...o
c..
..,
C
CD
E
CD
X
C)
ca
c
ca
The seven check bits are parity bits derived from the matrix of data bits as indicated by "X" for each bit.
error detection and correction details
:2!
During a memory read cycle, the 7-bit check word is retrieved along with the actual data. In order to be
able to determine whether the data from memory is acceptable to use as presented to the bus, the error
flags must be tested to determine if they are at the high level.
The first case in Table 3 represents the normal, no-error conditions. The EDAC presents highs on both
flags. The next two cases of single-bit errors give a high on MERR and a low on ERR, which is the signal
for a correctable error, and the EDAC should be sent through the correction cycle. The last three cases
of double-bit errors will cause the EDAC to signal lows on both ERR and MERR, which is the interrupt
indication for the CPU.
TABLE 3. ERROR FUNCTION
TOTAL NUMBER OF ERRORS
ERROR FLAGS
DATA CORRECTION
32-BIT DATA WORD
7-BIT CHECK WORD
ERR
0
H
H
Not applicable
1
0
0
L
H
Correction
0
1
L
H
Correction
1
1
L
L
Interrupt
2
0
L
L
Interrupt
0
2
L
L
Interrupt
MERR
~
o
E
CD
:2!
..
Error detection is accomplished as the 7-bit check word and the 32-bit data word from memory are applied
to internal parity generators/checkers. If the parity of all seven groupings of data and check bits are correct,
it is assumed that no error has occurred and both error flags will be high.
If the parity of one or more of the check groups is incorrect, an error has occurred and the proper error
flag or flags will be set low. Any single error in the 32-bit data word will change the state of either three
or five bits of the 7-bit check word. Any single error in the 7-bit check word changes the state of only
that one bit. In either case, the single error flag (ERR) will be set low while the dual error flag (MERR) will
remain high.
Any two-bit error will change the state of an even number of check bits. The two-bit error is not correctable
since the parity tree can only identify single-bit errors. Both error flags are set low when any two-bit error
is detected.
Three or more simultaneous bit errors can cause the EDAC to believe that no error, a correctable error,
or an uncorrectable error has occurred and will produce erroneous results in all three cases. It should be
noted that the gross-error conditions of all lows and all highs will be detected.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Cii
7-109
.....
>
SN54AS632, SN54AS634
SN74AS632, SN74AS634
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
TABLE 4. READ, FLAG, AND CORRECT FUNCTION
<
r-
MEMORY
EDAC
CONTROL
~
CYCLE
FUNCTION
S1
SO
s:CD
Read
Read & flag
H
L
H
H
Latch input
3
Read
-<
s:
Read
o
:s
D)
CD
CHECK 1/0
OEDB
H
X
Input
input
H
L
& syndrome bits
H
corrected
OECB
ERROR FLAGS
ERR
MERR
H
Enabledt
input
H
Enabledt
L
Enabledt
check word
Output
H
CONTROL
Latched
data
Output
corrected data
Input
CB
DB OUTPUT LATCH
I'AS632)
LEDBO
OEBn OR
Latched
bits
D)
cc
data & check
DB CONTROL
DATA 1/0
Output
X
L
data word
syndrome
bitst
tSee Table 3 for error description.
tSee Table 5 for error location.
3
As the corrected word is made available on the data I/O port (DBa thru OB31). the check word I/O port
(CBO thru CB6) presents a 7-bit syndrome error code. This syndrome error code can be used to locate
the bad memory chip. See Table 5 for syndrome decoding.
CD
:s
r+
..
"tJ
o
Co
c::
(')
r+
-
C/)
7-110
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54AS632, SN54AS634
SN74AS632, SN74AS634
32·811 PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
TABLE 5 .. SYNDROME DECODING
SYNDROME BITS
6 5
L L
L L
L L
L L
L L
L L
L L
L L
L L
L L
L L
L L
L L
L L
L L
L L
L L
L L
L.L
L L
L L
L L
L L
L L
L L
L L
L L
L L
L L
L L
L L
L L
CB X=
DB Y=
2-bit =
unc =
4
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
3
L
L
L
L
L
L
L
L
2
L
L
L
L
1 0
L L
L H
H L
H H
L L
H L H
H H L
H
H H H
L
H L
H L
H L
H
L L
L H
H L
H H
L L
H H L H
H H H L
H H
H H H H
H L L L L
H L L L H
H L L H L
L
L
H L
H L
H L
H
H
L H H
H L L
H L H
H H L
H H H
L
H H L
H H L
H H L
H H
L L
L H
H L
H H
H H H L L
H H H L H
H H H H L
H H H H H
ERROR
unc
2-bit
2-bit
unc
2-bit
unc
unc
2-bit
2-bit
unc
DB31
2-bit
unc
2-bit
2-bit
DB30
2-bit
unc
DB29
2-bit
DB28
2-bit
2-bit
DB27
DB26
2-bit
2-bit
D825
2-bit
DB24
unc
2-bit
SYNDROME BITS
6
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
5
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
4
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
3
L
L
L
L
L
L
L
L
2
L
L
L
L
1 0
L L
L H
H L
H H
H L L
H L H
H H L
H H
H L L
H L L
H L H
H L H
H
L
H
L
H
H H L L
H H L H
H H H L
H H
H L L
H L L
H L L
H H
L L
L H
H L
H L L H
H L H L
H L H L
H L H H
L H
H L
H L
H L
H H L
H
H
H
H
ERROR
H
L
H
L
H H
L L
L H
H L
H H
H H H L L
H H H L H
H H H H L
H H H H H
2-bit
unc
DB7
2-bit
DB6
2-bit
2-bit
DB5
DB4
2-bit
2-bit
DB3
2-bit
DB2
unc
2-bit
DBO
2-bit
2-bit
unc
2-bit
DB1
unc
2-bit
2-bit
unc
unc
2-bit
unc
2-bit
2-bit
CB6
SYNDROME BITS
6 5
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
H L
4
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
3
L
L
L
L
L
L
L
L
2
L
L
L
L
1 0
L L
L H
H L
H H
H L L
H L H
H H
L
H H H
H L L L
H L L H
H L H L
H L H H
H H L L
H H L H
H H H L
H H H H
H L L L L
H L L L H
H L L H
L
H L L H H
H L H L L
L H L H
H L H H L
H L H H H
H H L L L
H H L L H
H H L H L
H H L H H
H H H L L
H H H L H
H H H H L
H
H H H H H
ERROR
2-bit
unc
unc
2-bit
unc
2-bit
2-bit
unc
unc
2-bit
2-bit
DB15
2-bit
unc
DB14
2-bit
unc
2-bit
2-bit
DB13
2-bit
DB12
DB11
2-bit
2-bit
DB10
DB9
2-bit
DB8
2-bit
2-bit
CB5
SYNDROME BITS
6 5 4
H H L
H H L
H H L
H H L
H H L
H H L
H H L
H H L
H H L
H H L
H H L
H H L
H H L
H H L
H H L
H H L
3
L
L
L
L
L
L
L
L
2
L
L
L
L
L L
L H
H L
H
L H
H H
H L L
H H L
H H H
L
L
H L
H L
H
H
1 0
L L
L H
H L
H H
H H L L
H H L H
H H H L
H H H H
H H H L L L L
H H H L L L H
H H H L L H L
H H H L L H H
H H H L H L L
H H H L H L H
H H H L H H L
H
H
H
H
H H L H H H
H H H L L L
H H H L L H
H H H L H L
H H H H L H H
H H H H H L L
H H H H H L H
H H H H H H L
H H H H H H H
....en
ERROR
unc
2-bit
2-bit
DB23
2-bit
DB22
DB21
2-bit
2-bit
DB20
DB19
2-bit
DB18
2-bit
2-bit
CB4
2-bit
DB16
unc
2-bit
DB17
2-bit
2-bit
CB3
unc
2-bit
2-bit
(,)
:::::s
.
"C
o
c..
....r::::
Q)
E
Q)
C')
ca
ca
r::::
:E
~
o
E
:E
Q)
..
CB2
2-bit
CB1
CBO
none
error in check bit X
error in data bit Y
double-bit error
uncorrectable multibit error
read-modify-write (byte control) operations
The' AS632 is capable of byte-write operations. The 39-bit word from memory must first be latched into
the OB and CB input latches. This is easily accomplished by switching from the read and flag mode (S1 = H.
SO = L) to the latch input mode (S1 = H. SO = H). The EOAC will then make any corrections. if necessary.
to the data word and place it at the input of the output data latch. This data word must then be latched
into the output data latch by taking LEOBO from a low to a high.
Byte control can now be employed on the data word through the OEBO through OEB3 controls. OEBO
controls OBO-OB7 (byte 0). OEB1 controls OB8-0B15 (byte 1). OEB2 controls OB16-0B23 (byte 2). and
OEB3 controls OB24-0B31 (byte 3). Placing a high on the byte control will disable the output and the user
can modify the byte. If a low is placed on the byte control. then the original byte is allowed to pass onto
the data bus unchanged. If the original data word is altered through byte control. a new check word must
be generated before it is written back into memory. This is easily accomplished by taking control S 1 and
SO low. Table 6 lists the read-modify-write functions.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Ci)
7-111
....I
>
I
SN54AS632, SN54AS634
SN74AS632, SN74AS634
32-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
TABLE 6. READ-MODIFY-WRITE FUNCTION
<:
r~
MEMORY
CYCLE
s:CD
Read
Read
3
o
-<
EDAC FUNCTION
Read & Flag
Latch input data
& check bits
CONTROL
51
50
H
L
H
H
Read
data word into
H
H
H
L
LEDBO
Input
CB
CONTROL
ERROR FLAG
ERR
MERR
H
Enabled
H
Enabled
Latched
Input
input
check word
Hi-Z
------
output
H
data
H
Output
Syndrome
H
------L
Enabled
bits
word
Modify appropriate
3
Modify
byte or bytes &
,..::::I
Iwrite
generate new
CD
..
check word
"'CJ
L
L
modified
H
BYTEO
Output
------
unchanged
L
-------
H
Output
check word
L
H
H
BYTEO
o
c
X
CHECK 1/0
Input
CD
(')
,..
H
Latched
IQ
Co
Input
data
output latch
::::I
OJ
LATCH
OEBnt
Latched
Latch corrected
s:OJ
DB OUTPUT
BYTEnt
t OEBO controls DBO-OB7 (8YTEO). OEB 1 controls DBa-DB 15 (BYTE 1). OEB3 controls DB 16-0B23 (8YTE2). OEB3 controls OB24-0B31
(BYTE3).
en
The' A5632 and' A5634 are capable of diagnostics that allow the user to determine whether the EDAC
or the memory is failing. The diagnostic function tables will help the user to see the possibilities for diagnostic
control.
In the diagnostic mode (51 = L, 50 = H), the checkword is latched into the input latch while the data
input latch remains transparent. This lets the user apply various data words against a fixed known
checkword. If the user applies a diagnostic data word with an error in any bit location, the ERR flag should
be low. If a diagnostic data word with two errors in any bit location is applied, the MERR flag should be
low. After the checkword is latched into the input latch, it can be verified by taking OECB low. This outputs
the latched checkword. With the' A5632, the diagnostic data word can be latched into the output data
latch and verified. It should be noted that the' A5634 does not have this pass-through capability because
they do not contain an output data latch. By changing from the diagnostic mode (51 = L, 50 = H) to
the correction mode (51 = H,50 = H), the user can verify that the EDAC will correct the diagnostic data
word. Also, the syndrome bits can be produced to verify that the EDAC pinpoints the error location. Table 7
(' A5632) and Table 8 (' A5634) list the diagnostic functions.
7-112
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54AS632, SN54AS634
SN74AS632, SN74AS634
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
TABLE 7. 'AS632 DIAGNOSTIC FUNCTION
EDAC FUNCTION
Read & flag
CONTROL
51
SO
H
L
Latch input check
word while data
input latch remains
L
H
L
H
Latch diagnostic
H
H
input latch
LEDBO
H
X
Input correct
data word
CONTROL
OECB
Input correct
check bits
....
U)
ERROR FLAGS
ERR
()
MERR
::::s
"C
H
a..
H
H
H
Enabled
e
....C
Latched
diagnostic
H
input
L
data word t
check bits
Input
Output latched
diagnostic
H
CD
E
CD
check bits
H
f--------
Hi-Z
Latched
Output
input
syndrome
H
diagnostic
H
H
1--------Hi-Z
diagnostic
data word
Output corrected
Output
H
H
syndrome bits
L
bits
Output
H
L
--H---
ca
c
ca
Enabled
:E
~
o
Enabled
E
CD
:E
Cii
..J
H
Output
syndrome bits
word & output
OEBn
CB
CHECK 1/0
data word
Output diagnostic
diagnostic data
LATCH
data word t
output latch
data word &
DB OUTPUT
C)
Latch diagnostic
data word into
DB BYTE
CONTROL
Input
transparent
data word into
DATA 1/0
L
syndrome
H
L
bits
..
Enabled
1 - - - - - - - - r----Hi-Z
>
H
Output
corrected
L
diagnostic
syndrome
L
L
bits
---------Hi-Z
data word
Enabled
H
TABLE 8. 'AS634 DIAGNOSTIC FUNCTION
EDAC FUNCTION
Read & flag
CONTROL
51
SO
H
L
L
H
Latch input check
bits while data
input latch remains
check bits
diagnostic
H
diagnostic
H
Latched input
H
H
H
H
diagnostic
check bits
Latched input
check bits
Output input
check bits
syndrome bits
--------Hi-Z
Output corrected
H
Input correct
Output
diagnostic
data word
Output corrected
data word
data word
data word t
input latch
diagnostic
H
Input
H
Latch diagnostic
data into
Input correct
data word t
L
CHECK 1/0
OEDB
Input
transparent
Output input
DB CONTROL
DATA 1/0
Output
L
data word
syndrome bits
-------Hi-Z
CB CONTROL
OECB
H
ERROR FLAGS
ERR
H
MERR
H
H
Enabled
L
Enabled
L
---H---L
Enabled
Enabled
- --H- - - -
tDiagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case, the diagnostic data
word will contain errors in two bit locations.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
7-113
SN54AS632, SN74AS632
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
I
AS632 logic diagram (positive logic)
DECODER
X/Y
<
r-
I
0
~
o
3:
CD
3
o
-<
so -
1
S1 -
2
1,
h
I""
I
7~
,
3
1
3 ~
21-
~
,----
>1
J
I
r-?r-
CHECK-BIT
GENERATOR
~
~
~
~
3:
C)
::::I
SYNDROME
GENERATOR
=1
CBO
h
~
LATCHES
C)
~
~
CQ
CD
C1
'--
3
C BO-
7"
CB6
CD
::::I
,7,
10
,
MUX
r+
.o
"'C
BUFFERS
kJ
o
E
Q)
x-oRl
~ 32
1~
Ik; GO
CO
c:
[7
~
MUX
7
~
....
G1
7
o '
U)
-
....
ERROR
DETECTOR
(See Table 3)
>
LATCHES
32
,
,
+'"
h
7
EN
32
.
o
c.
~
,
'---
DBO- DB31
:l
"C
~
~
~
BUFFERS
7
~
(,)
~
~
,.......C1
10
+'"
~
CB1
~
LATCHES
.....
(I)
SYNDROME
GENERATOR
=1
"""-
C1
~
10
ERROR p--ERR
EN
MULTIERROR
7
,
tJ-M"ERR
~
32,
32
ERROR
CORRECTOR
=1
BUFFERS
switching characteristics over recommended supply voltage range and operating temperature range
(see Note 2)
PARAMETER
...en
CJ
V
V
3.3
2.7 V
Vee
5.5 V,
=
-1.2
UNIT
Vcc- 2
vcc- 2
10H
4.5 V,
Typt MAX
MIN
-1.2
10H
4.5 V,
lo§
IlL
SN74AS632
SN54AS632
TEST CONDITIONS
SN74AS632
MAX
25
UNIT
MAX
27
MIN
4
4
27
4
25
5
34
5
32
5
4
34
32
32
5
4
2
19
2
17
ns
4
29
4
26
ns
28
ns
ns
ns
2
18
2
16
ns
3
1
22
3
1
20
ns
17
ns
1
1
1
15
17
ns
1
17
19
1
17
1
15
ns
19
ns
t All typical values are at Vee = 5 V, T A = 25 ae.
+For I/O ports, the parameters IIH and IlL include the off-state output current.
§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.
NOTE 2: Load circuit and voltage waveforms are shown in Section 1 of the LS/ Logic Data Book, 1986.
-IJI.
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-117
SN54AS634, SN74AS634
32·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
WITH 3·STATE OUTPUTS
electrical characteristics over recommended operating temperature range (unless otherwise noted)
<
r~
3:
3
PARAMETER
VOH
o
-<
ERR or MERR
DB or CB
3:
II)
II
CQ
CD
3CD
DB or CB
VOL
II)
:::J
II = -18 mA
VCC = 4.5 V to 5.5 V, 10H = -0.4 mA
VCC = 4.5 V,
10H = -1 mA
All outputs
VCC = 4.5 V,
10H = -2.6 mA
VCC = 4.5 V,
10H = 4 mA
VCC = 4.5 V,
10L = 8 mA
VCC = 4.5 V,
10L = 12 mA
3.3
V
0.25
0.4
0.4
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
10L = 24 mA
VCC = 5.5 V,
VI = 7 V
0.1
0.1
All others
VCC = 5.5 V,
VI = 5.5 V
0.1
0.1
VCC = 5.5 V,
VI = 2.7 V
20
20
20
20
All others+
SO, S 1 or OEDB
""C
10§
VCC = 5.5 V,
Vo = 2.25 V
ICC
VCC = 5.5 V,
See Note 1
VCC = 5.5 V,
V
3.2
2.4
VCC = 4.5 V,
IlL
..o
-1.5
UNIT
VCC-2
0.25
,...:::J
c.
c
-1.5
VCC- 2
2.4
SO or S1
DB or CB+
IIH
SN74AS634
Typt
MAX
MIN
MIN
VCC = 4.5 V,
VIK
CD
SN54AS634
Typt
MAX
TEST CONDITIONS
VI = 0.4 V
All others+
-0.4
-0.4
-0.1
,-0.1
-112
-30
200
-30
300
200
V
mA
p.A
mA
-112
mA
300
mA
n
e:
t All typical values are at VCC = 5 V, T A = 25°C.
+For 1/0 ports, the parameters IIH and IlL include the off-state output current.
§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS .
. . NOTE 1: ICC is measured with SO and S1 at 4.5 V and all CB and DB pins grounded.
switching characteristics over recommended supply voltage range and operating temperature range
(see Note 2)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
DB and CB
ERR
SN74AS634
SN54AS634
TEST CONDITIONS
MIN
MAX
S1 =H, SO=L, RL=500
4
S1 =L, SO=H, RL=500
4
MAX
30
4
25
30
4
25
5
34
5
32
5
34
5
32
4
32
4
28
2
19
2
17
ns
4
29
4
26
ns
3
22
3
20
ns
tpd
DB and CB
tpd
SOt and SH
CB
tpLH
SOt and SH
ERR
n
n
S1 =H, SO=L, RL=500 n
S1 =L, SO=H, RL=500 n
R1 =R2=500 n
RL = 500 n
tpd
DB
CB
S 1 = L, SO = L, R1 = R2 = 500
tpd
S11
CB
SO=H, R1 =R2=500
ten
OECBt
CB
S1 =X, SO=H, R1 =R2=500
1
19
1
17
ns
tdis
OECBi
CB
S1 =X, SO=H, R1
1
17
1
15
ns
ten
OEDBt
DB
S1 =X, SO=H, R1
n
=R2=500 n
=R2=500 n
1
19
1
17
ns
tdis
OEDBi
DB
S1 =X, SO=H, R1 =R2=500
n
1
17
1
15
ns
tpd
MERR
n
n
NOTE 2: Load circuit and voltage waveforms are shown in Section 1 of the LSI Logic Data Book, 1986.
7·118
UNIT
MIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ns
ns
SN54AS632, SN54AS634
SN74AS632, SN74AS634
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
I4---READ--~·ll4-t---------CORA~CT
_I
I
I
I
I
"""--'hI81---.,
i
so ...,
...
:::::I
.
tcorrection------~
:.
"'0
:.sulll~.hI91___+:
DBO THRU DB31
en
.....
(,)
1 _ _ _ __
o
a..
.....
c:
Q)
j+-'dis--+J
----i=::::!I~NP~U~T~D~AT~A~W~O~R~D==:]~tz~~1===*=~O~U~T~PU~T~C~O~RR~E~C~TE~D~D~A~TA~W~O~R~D~~~~~-l4--'on----.l
I
~I-------------------------------~~'dis--+J
OEBO THRU OEBJ
I
:
~'suI1l~'hI91~
CBO THRU CB6
~
~
INPUT CHECK WORD
CO
c:
~i__________________________________~
~'pd~
Meiiii
Q)
0)
l4--'en~
:
:
ERR
E
»»»»'
OUTPUT SYNDROME CODE
CO
4
W?'$1~(,ALID00W
$r--------------V-A-L-,D-=E=R=R-FL-A-G----------------'""IW
:2:
>o
..
Mlt?, 6:tm
~
'pd
_I
0"#lff);A'I~&1(lh%0WIff4r------VA-L-,D-=M=E=R=-R-FL-A-G-----~)00Mv~tM@
E
Q)
:2:
FIGURE 1. READ, FLAG, AND CORRECT MODE SWITCHING WAVEFORMS
US
...I
14--- 'hI81~
SO:
I4--READ
SI
--.J
:
I
INPUT
DAT~ WORD
WRITE
I
I
OBO THRU DB7 - - - {
>
~i------------------------------------~I
_It
CORRECT
_It
I
OUTPUT CORRECTED DATA WORD
I
»»)
M)Q
(
I
INPUT MODIFIED BYTE 0
I
OB8 THRU DB15
INPUT DATA WORD
OUTPUT CORRECTED DATA WORD
DB16 THRU DB23
INPUT DATA WORD
OUTPUT CORRECTEO DATA WORD
DB24 THRU DB31
INPUT DATA WORD
OUTPUT CORRECTED DATA WORD
-
WO
_________________________,----_________r____
OEBI
1
----------------------------------r:________________~r______
I
----------------------------------rl________________~r____
OEBJ
l+--'suI21-44
LED80
tt-'SUI31...t
~~~~<:"":~~~~~~~~~<:"":~~~~~~~
~/I///I////l/W//d
I.--'w---+l
:
I
OECB--------------~I----------------r--------~r---CBO THRU CB6
ERR
INPUT CHECK WORD
OUTPUT SYNDROME CODE
OUTPUT CHECK WORD
\~__________v~A~L~ID_E_R_R_F~LA~G~________~1
\~_______v_A_L_ID_M_E_R_R_F_LA_G______
_J1
FIGURE 2. READ, CORRECT, MODIFY MODE SWITCHING WAVEFORMS
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
7-119
SN54AS632. SN54AS634
SN74AS632. SN74AS634
32·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
so
r.w(S],.
<
SI
~---------_+I----JI
~
II
~
s:CD
_______________________L_
DBO THRU DB31
,,-'h(IOI---+f
I
,
INPUT DIAGNOSTIC DATA WORD
NPUT VALID DATA WORD
OUTPUT DIAGNOSTIC
DATA WORD
OEBO----~----------~I---~I----~:
I
IL_________-+:I______~r_____
3
o
THRU
\,
OEB3
-<
s:
1 ; -
."'(71~!.1----+t.1....-.~I-'W(41:
I
t'Pd-+t
~ ______~----------+:-~~I-,~----i~------~~I----------___
:
D)
~
D)
t+--'W(61+'h(II1~
CBO
THRU
CB6
cc
CD
!
i
1-+'h(121~
~'Pd4
OUTPUT SYNDROME CODE
OUTPUT VALID CHECK WORD
I~,-~~~~~~'~J\----~---~I---J~-----------------.d-;S~~~I
I
~
3
I
i
I
r--
~
....
:
I
:
~.Pd___+!
______________ :.. _______________ _
a"tJ
ERR - -;- - - -
CD
\+---'pd---1
_ _ _-~.....I
__
Co
cC')
..
....en
7-120
!!:==..~
,
VERIFY PROPER OPERATION OF ERR FLAG
I
____J
~ _ _ _ .!!!.!!.~~~ !.E~'~'!!.
__ !I
I
VERIFY PROPER OPERATION OF ERR FLAG, FLAG SHOULD BE LOW
WITH A DIAGNOSTIC DATA WORD WITH A SINGLE ERROR
I+---.pd--+! ________________________________ _
::F~ P!£~!~5~eE~ ~~~~ ~~) ~_ _V_E_R..:.I~;..~T..:.P~..:.~..:.PD;..E,'l_8;..~..:.~.;.~~;..;'"c;;..I%;..'1_~_X_X.;.5~..;~;..~_~_~_G'A_F;..~~;..S_:_~E_O~_~_~_JlR_E_LO_W_ __
MERR _ _ _ _ _- - ' \..
FIGURE 3. DIAGNOSTIC MODE SWITCHING WAVEFORM
..Jj}
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74ACT2151, SN74ACT2153
1Kx12 CACHE ADDRESS COMPARATORS
D3105. SEPTEMBER 1987-REVISED MARCH 1988
JD OR N PACKAGE
• Fast Address to Match Delay
,ACT2151 25 and xx ns Max
,ACT2153 28 and xx ns Max
(TOP VIEW)
RESET
A4
A3
A2
A1
AO
DO
01
02
03
09
• On-Chip Address/Data Comparator
• On-Chip Parity Generator and Checking
• Parity Error Output, Force Parity Error Input
• Easily Expandable
• Choice of Open-Drain or Totem-Pole
MATCH Output
• EPIC™ (Enhanced Performance Implanted
CMOS) 1-JLm Process
W
PE
• Fully TTL-Compatible
....
(I)
VCC
A5
A6
A7
A8
A9
010
04
05
06
07
08
MATCH
(J
:s
.
"C
o
c..
....r::::
CD
E
CD
C)
ca
ca
r::::
:!
~
S
GNO
o
E
CD
:!
Ui
....I
FN PACKAGE
(TOP VIEW)
description
The 'ACT2151 and 'ACT2153 cache address
comparators consist of a high-speed 1K x 12
static RAM array, parity generator, parity checker,
and 12-bit high-speed comparator. They are
fabricated using advanced silicon-gate CMOS
technology for high speed and simple interface
with bipolar TIL circuits. These cache address
comparators are easily cascadable for wider tag
addresses or deeper tag memories. Significant
reductions in cache memory component count,
board area, and power dissipation can be
achieved with these devices. The 'ACT2151 has
a totem-pole match output while the ' ACT2153
has an open-drain MATCH output for easy ANDtying.
..
>
A1
AO
DO
01
02
03
09
4 3 2 1 282726
5
25
6
24
23
8
22
9
21
10
20
11
19
12131415161718
A7
A8
A9
010
04
05
06
S
->ww
a:
c..
I(.)
If 8 is low and Vi is high, the cache address comparator compares the contents of the memory location
addressed by AO-A9 with the data DO-D1 0 plus generated parity. An equality is indicated by a high level on
the MATCH output. A low-level output on PE signifies a parity error in the internal RAM data. PE is an Nchannel open-drain output for easy OR-tying. During a write cycle (8 and Vi low), data on DO-DlO plus
generated odd parity are written in the 12-bit memory location addressed by AO-A 10. Also during write, a
parity error may be forced by holding PE low.
A reset input is provided for initialization. When RESET is taken low, all 1K x 12 RAM locations are cleared to
zero (with valid parity) and the MATCH output is forced high. If an input data word of zero is compared to any
memory location that has not been written into since reset, MATCH will be high indicating that input data, plus
generated parity, is equal to the reset memory location. PE will be high after reset for every addressed
memory location, indicating no parity error in the RAM data. By tying a single data input pin high, this bit will
function as a valid bit and a match will not occur unless data has been written into the addressed memory
location. When cascading in the width direction, only one bit must be tied high regardless of the address
width.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW documents contain information
on products in the formative or design phase of
development. Characteristic data ani! other
specifications are design goals. Tuas Instruments
reserves tha right to change or discontinue these
products without notice.
Copyright © 1988. Texas Instruments Incorporated
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-121
:::>
c
oa:
c..
SN74ACT2151, SN74ACT2153
1Kx12 CACHE ADDRESS COMPARATORS
These cache address comparators operate from a single 5-V supply and are offered in 28-pin 600-mil ceramic
side-brazed, plastic dual-in-line, or PLCC packages.
;::
The SN74ACT2151 and SN74ACT2153 are characterized for operation from O°C to 70°C.
~
3:
3
o
MATCH OUTPUT DESCRIPTION
CD
MATCH = VOH if: (AO-A9) = DO-D10
-<
+ parity,
or: RESET = VIL,
3:
or:
m
::::I
or:
~
S = VIH,
W = VIL
MATCH = VOL if: (AO-A9) ~ 00-010
3
+ parity,
with RESET = VIH,
.....
..
S
CD
::::I
."
= VIL, and W = VIH
FUNCTION TABLE
o
Co
s:
()
INPUTS
..
fA
"'C
II
o
OUTPUTS
W
S
RESET
H
L
H
L
X
X
MATCH
L
L
H
H
L
H
H
H
H
H
X
L
H
PE
L
FUNCTION
Parity error
H
Not equal
L
H
Undefined error
IN
Write
H
Device disabled
r
Memory reset
Equal
t The state of PE is dependent on inputs Wand S.
C
C
n
-I
"'C
II
m
~
m
~
7-122
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ACT2151, SN74ACT2153
1Kx12 CACHE ADDRESS COMPARATORS
logic symbols t
--(11
RES~ (121
~
AO
A1
A2
A3
A4
A5
A6
(151
(61
(51
(41
(31
(21
(271
(261
(251
:~ (241
A9 (231
DO (]I
(81
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
(91
(101
(211
(201
(191
(181
(171
(111
(221
CACHE ADDRESS
COMPARATOR
CACHE ADDRESS
COMPARATOR
'ALS2151
'ALS2153
--(11
RES~ (121
RESET
WRITE
SELECT
~
o
1
2
3
4
5
6
7
8
9
RAM
ADDRESS
MATCH t-----'(_16....
1 MATCH
PEQ
(131 PE
PE
AO
A1
A2
A3
A4
A5
A6
(151
(61
(51
(41
(31
(21
(271
(261
(251
:~
(241
A9 (231
DO (71
(81
D1
D2 (9)
D3 (101
D4 (211
D5 (201
D6 (191
D7 (181
D8 (171
D9 (111
D10 (221
...
(I)
Co)
:::s
.
"0
o
...
0..
RESET
WRITE
SELECT
C
Q)
o
E
Q)
C)
2
ca
ca
c
3
4
5
6
RAM
ADDRESS
:E
MATCH Q t-----'('-16....
) MATCH
PEQ
(131 PE
~
PE
o
8
9
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
E
Q)
:E
Cii
-I
>
-
~
->w
W
a:
c..
t-
O
:J
C
oa:
c..
TEXAS
-1./1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-123
I
SN74ACT2151, SN74ACT2153
1Kx 12 CACHE ADDRESS COMPARATORS
logic diagram (positive logic)
<
r-
RESET . .:. .1.( . :. .1-----'01
~
COMP
3:
CD
3
11
o
}
.----1-1---1}
-<
>-
Q
1---'---4....----
>--_ _(_16_) MATCH
o
3:
A1023
Q)
11
:::s
Q)
(131
cc
CD
3
...
..
9
CD
INPUT
:::s
C1
00 (71
"tJ
01 (81
02 (91
03 (101
o
Co
c:
n
04 (211
en
05 (201
06 (191
07 (181
08 (171
09 (11)
"'C
010 (221
:tI
o
C
c:
S (15)
('"')
-I
"'C
W (121
:tI
m
<
-
7-124
TEXAS
l.!1
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS. TEXAS 75265
FiE
SN74ACT2151, SN74ACT2153
1Kx12 CACHE ADDRESS COMPARATORS
PIN
NAME
DESCRIPTION
NO.
AO
6
A1
5
A2
4
A3
3
A4
2
A5
27
A6
26
A7
25
A8
24
A9
23
DO
7
01
8
02
9
03
10
04
21
....Utn
::::I
"C
...o
c..
....c
Q)
Address inputs, Addresses 1 of 1024 random access memory locations. Must be stable for the duration of the write cycle.
E
Q)
C)
as
c
as
:E
...>-o
Data inputs. Compared with memory locations addressed by AO-A9 when W is at VIH and
data to the RAM when Wand S are at VIL.
S is at VIL.
E
Q)
:E
Provides input
05
20
06
19
07
18
08
17
09
11
010
22
GND
14
Ground
MATCH
16
When MATCH output is at VOH during a compare cycle, 00-010 plus generated parity equals the contents of the 12-bit
memory location addressed by AO-A10. MATCH is also d~iven high during deselect and reset. Since the 'ACT2153
features an open-drain MATCH output, an external pull-up resistor of 220 n minimum is required.
PE
13
tii
-I
..
>
Parity error inpuVoutput. During compare cycles. PE at VOL indicates a parity error in the stored data. During write cycles,
RESET
1
PE can force a parity error into the 12th-bit location specified by AO-A9 when PE is taken to VIL. PE is an open-drain output
so an external pull-up resistor of 220 n minimum is required.
Reset input. Asynchronously clears entire RAM array to zero and forces MATCH high when RESET is at VIL.
S
15
Chip select input. Enables device when S is at VIL. Deselects device and forces MATCH and PE high when S is at VIH.
VCC
28
Supply voltage
12
Write control input. Writes DO-DO and generated parity into RAM and forces MATCH high when Wand S are at VIL. Places
selected device in compare mode when W is at VIH.
W
$
->w
W
a:
c..
I(J
::::J
C
oa:
c..
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-125
SN74ACT2151, SN74ACT2153
1Kx12 CACHE ADDRESS COMPARATORS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -1.5 to 7 V
Input voltage, any input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5 to 7 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ooe to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
<
r~
s:
NOTE 1: All voltage values are with respect to GNO.
(I)
3
o
recommended operating conditions
-<
s:
MIN
NOM
MAX
5
5.5
V
VCC+0.5
0.8
V
High-level output voltage, MATCH ('ACT2153) and PE outputs only
5.5
V
High-level output current, MATCH ('ACT2151)
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage (See Note 2)
VOH
3(I)
10H
.
10L
C)
::::I
C)
cc
(I)
....::::I
4.5
2.2
-0.5
Low-level output current
"a
o
0.
c
TA
..
n
....o
-8
mA
MATCH - 'ACT2151
8
mA
MATCH - 'ACT2153
24
mA
PE
24
mA
70
°c
Operating Iree-air temperature
0
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74ACT2151-25
PARAMETER
TEST CONDITIONS
:JJ
C
C
n
:JJ
m
<
-
SN74ACT2151-xx
SN74ACT2153-28
MIN
TYpt
SN74ACT2153-xx
MAX
MIN
TYpt
UNIT
MAX
10H
High-level
MATQj ('ACT2153)
output current and PE
VOH = 5.5 V,
VOH
High-level
MATCH ('ACT2151)
output voltage
IOH = -8 mA, VCC = 4.5 V
MATCH - 'ACT2153
Low-level
MATCH - 'ACT2151
output voltage
PE
IOL = 24 mA,
VCC = 4.5 V
0.4
0.4
VOL
10L = 8 mA,
VCC = 4.5 V
0.4
0.4
IOL = 24 mA,
VCC = 4.5 V
0.4
0.4
II
Input current
VI = O-VCC,
VCC = 5.5 V
lOSt
Short-circuit
output current
Va = 0,
VCC = 5.5 V
ICC1
Supply current (operative)
BESET at 3 V,
SatOV
VCC = 5.5 V
85
85
mA
Supply current (reset)
BESET at 0 V,
Sat OV
VCC = 5.5 V
5
5
mA
VCC = 5.5 V
75
-I
"'CJ
V
NOTE 2: The algebraic convention, in which the more negative (less positive) limit is designated as minimum, is used in this data sheet lor logic
voltage levels only.
"'CJ
o
UNIT
ICC2
MATCH (,ACT2151)
ICC3
Supply current (deselected)
BESET at 3 V,
S at3 V
Ci
Input capacitance
1=1 MHz
Co
Output capacitance
1= 1 MHz
5
VCC = 5.5 V
5
3.7
3.7
V
:!:1
150
50
50
t Not more than one output should be shorted at a time, and duration 01 the short-circuit should not exceed one second.
TEXAS """
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
V
:!:1
J.l.A
150
mA
75
5
6
t All typical values are at VCC = 5 V, TA = 25°C.
7-126
,..A
mA
5
pF
6
pF
SN74ACT2151, SN74ACT2153
1Kx12 CACHE ADDRESS COMPARATORS
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted), see Figures 1, 2, and 3
SN74ACT2151-25
PARAMETER
MIN
TYpt
MAX
(I)
SN74ACT2151-xx
MIN
TYpt
Access time from address to MATCH
19
28
ns
ta(A-PH)
Access time from address to PE high
21
27
ns
23
29
ns
9
15
ns
10
15
ns
ta(A-PL)
Access time from address to PE low
Access time from S to MATCH
tp(D-M)
Propagation time, data inputs to MATCH
11
ns
5
8
ns
5
8
ns
7
9
ns
5
5
ns
tp(RST-MH)
Propagation time, RESET low to MATCH high
7
tp(S-MH)
Propagation time, S high to MATCH high
tp(W-MH)
Propagation time, W low to MATCH high
tp(W-PH)
Propagation time, W low to PE high
tv(A-M)
MATCH valid time after change of address
tv(D-M)
MATCH valid time after change of data
5
5
ns
tv(S-M)
MATCH valid time (low) after S high
5
5
ns
tV(A-P)
PE valid time after change of address
10
10
ns
SN74ACT2153-25
PARAMETER
MIN
ta(A-M)
Access time from address to MATCH
ta(A-PH)
Access time from address to PE high
ta(A-PL)
Access time from address to
TYpt
19
PE low
ta(S-M)
Access time from S to MATCH
tp(D-M)
Propagation time, data inputs to MATCH
tp(RST-MH)
tp(S-MH)
Propagation time,
MAX
::s
"'C
...o
c..
+'"
C
(1)
E
(1)
C)
CO
C
CO
2!
...>-o
E
(1)
:?E
Ci)
SN74ACT2153-xx
MIN
TYpt
28
UNIT
MAX
ns
23
29
ns
25
31
ns
9
15
ns
10
15
ns
Propagation time, RESET low to MATCH high
7
11
ns
S high to
MATCH high
5
8
ns
tp(W-MH)
Propagation time, W low to MATCH high
5
8
ns
tp(W-PH)
Propagation time, W low to PE high
7
9
ns
tv(A-M)
MATCH valid time after change of address
5
5
ns
tv(D-M)
MATCH valid time after change of data
5
5
ns
tv(S-M)
MATCH valid time (low) after S high
5
5
ns
tV(A-P)
PE valid time after change of address
10
10
ns
t All typical values are at VCC
(,)
MAX
ta(A-M)
ta(S-M)
+'"
UNIT
..I
-
>
$
->w
W
a:
c..
....
(.)
=>
o
C
= 5 V, TA = 25°C.
a:
c..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-127
SN74ACT2151, SN74ACT2153
1Kx 12 CACHE ADDRESS COMPARATORS
timing requirements over recommended ranges of supply voltage and operating free-ail
temperature (unless otherwise noted)
<
r-
SN74ACT2151-25
~
3:
CD
3
o
PARAMETER
SN74ACT2153-28
MIN
NOM
MAX
SN74ACT2151-xx
SN74ACT2153-xx
MIN
NOM
UNIT
MAX
tw(RSTLl
Pulse duration, RESET low
30
30
ns
tw(wLl
Pulse duration, W low, without writing PE
15
15
ns
tw(WLlPE
Pulse duration, W, writing PE (see Note 3)
15
15
ns
tsu(A)
Address setup time before W low
0
0
ns
tsu(D)
Data setup time before W high
10
10
ns
:::J
tsu(p)
PE setup time before W high (see Note 3)
10
20
ns
CQ
tsu(S)
Chip select setup time before W high
10
20
ns
15
15
ns
0
0
ns
-<
3:
D)
D)
CD
3
CD
:::J
.-ao
r+
tsu(RST)
RESET inactive setup time before W high
th(A)
Address hold time after W high
th(WH-D)
Data hold time after W high
th(WL-D)
Data hold time after W low with MATCH high, (see Note 4)
5
5
ns
10
10
ns
th(P)
PE hold time after W high
0
0
ns
Co
thIs)
Chip select hold time after W high
0
ns
n
r+
en
tAVWH
Address valid to write enable high
15
0
15
c
-
NOTES:
3.
4.
'"'C
:c
o
c
c:
n
-I
'"'C
:c
m
<
m
=:
7-128
ns
Parameters twPE(wLl and tsu (p1!Pply only during the write cycle timing when writing a parity error.
th(WL-D) guarantees that when W is taken I~ during a compare cycle with MATCH high, match will remain high without e
glitch low. (As shown in the function table, W low forces MATCH high). th(WL-D) is guaranteed indirectly by tv(D-M) anc
tp(W-MH)·
l!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ACT2151, SN74ACT2153
1Kx12 CACHE ADDRESS COMPARATORS
PARAMETER MEASUREMENT INFORMATION
FROM OUTPUT
UNDER TEST
-----:11.
TEST
F
POINT
I
-f
INPUT
tn
....,
~~5:----3V
---Il
I .
I
CJ
::s
"C
o...
a..
....,
GND
14--- tpd ----.I
I
--.I tpd r+1,--_ _ _ _ _ 1
CL - 50 pFt
t
1
OUTPU_T_ _ _- - I
LOAD CIRCUIT
C
(1)
E
(1)
C')
ca
ca
VOLTAGE WAVEFORMS
c
FIGURE 1. TACT2151 MATCH OUTPUT
--+j tr
- - - 4 1 1 - - - - VCC
~
rl----~~~I-_-----3V
2.7 V
I
o
I
~
~
RL - 220
INPUT
TEST
FROM OUTPUT - -...... POINT
UNDER TEST
I
II 1.5V
I
rCL -
~
~ tf j+-6 ns
1+-6 ns
0.3 V
GND
en.....
I
i+--tpd---+l
I4-tpd~
I
I
I
I
50 pFt
>
-
OUTPUT
LOAD CIRCUIT
E
(1)
11 . 5V
VOLTAGE WAVEFORMS
~
FIGURE 2. OPEN-DRAIN MATCH AND PE OUTPUTS
w
PARAMETER
ten
tdis
I
tpZH
tpZL
640
-.!.e.!::!L
640
tPLZ
tod or tt
---o---VCC
CL t
RL
n
S1
OPEN
50 pF
n
50 pF
50 pF
-
5>
w
S2
CLOSED
CLOSED
OPEN
OPEN
CLOSED
D.
CLOSED
OPEN
OPEN
OPEN
I-
a:
(.)
:J
INPUT
FROM OUTPUT -~""'...JVII'v-"""
UNDER TEST
.5 V
1.5 V
I
14I
I
1.5 V
I
I
OUTPUT
LOAD CIRCUIT
14-
tpZH-.I
OUTPUT
oa:
I
j------OV
-.t I4-tpLZ
I
tPZL-+J
C
3 V
I I
I I
I I
c.
.. VCC
£,0.3 V
---x-='::-"':: VOL
tPHZ-+! t+- T
I
..t.
~
1.5 V
-::"-::"-="-=".fVOH
0.3 V
.. OV
VOLTAGE WAVEFORMS
FIGURE 3. 3-STATE DATA OUTPUTS
t CL includes probe and test fixture capacitance.
TEXAS
'1!1
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS. TEXAS 75265
7-,129
SN74ACT2151, SN74ACT2153
1Kx 12 CACHE ADDRESS COMPARATORS
PARAMETER MEASUREMENT INFORMATION
write cycle timing
AO-A'
~,--_ _ _ _ _ _ _ _A_D_D_R_ES_S_V_A_L_ID_ _ _ _ _ _ _ _
...
1..1-----th(AI---~.1
!4--tsu(AI--+i
I tAVWH---~.'
'III
""C
:c
o
c
c
(")
I
I
I
~----~~I--~~--------
J.I
""C
:c
DO-D10
m
tw(WLl/tw(WLIPE-.i
(see Note 31
I
'W'~......................._ _ _..............
<
m
-
DATA V:ALID
14- tsu(DI---+!
I
,
I
PE (lNPUTI
I
I
"11II---I."'-I-th(WH-DI
I
I
I
I
,
tsu(PI
~
I
(see Note 31
14-- th(PI----.!
I4t--
<
r-
~
I I
I
,
~
I
~
:
MATCH
s:
I
j4---~.I-tp(W-MHI
CD
3
o
PE (OUTPUTI
-<
s:
m
::::I
I
I
I
JoIIII4t----,.-t sU ( S I - - - - + t . l . - - t h(SI---.I
-I
m
m
''----+1---.
..
ktp(W-PHI---+i
reset cycle timing
cc
CD
3
CD
::::I
....
j.--tw(RSTLI
...o
~III
tsu(RSTI----+/
ADDRESS . ' - - - . . ; . . . . - - - - - -
"'tJ
Co
I
c
....en
(')
w
MATCH
I
I
I
,
14
.1
tp(R-MHI
NOTE 3: Parameters tw(WL)PE and tsu(P) apply only during the write cycle when writing a parity error.
7-130
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ACT2151, SN74ACT2153
1Kx12 CACHE ADDRESS COMPARATORS
PARAMETER MEASUREMENT INFORMATION
compare cycle timing
(I)
AO-A9~
ADDRESS VALID
DO-D 10 )()()()()(),(
I
I
MATCH
I
DATA VALID
~
tp(DI
!
~
I
¥
I
I
I
1
I
1---+1
I
I
I
I
I
I
I+--talSI----+i
I
DATA VALID
.
I4-tvID-MI
CO
t pIS-MHI14
~I
tv1S-M114
~I I
I
~I tvlA-MI
I
~
~
o
V
I
I
CO
C
I
~
I
1+---+1- tvlA-PI
I
E
I
I
I
c
Q)
Q)
C)
1
14
~
\
~
~
o
c..
I
I
14- taIA-PLI----.J
PE
i
1
I
I
I
xm
CJ
::::I
"C
I
I
I
5
>.<
~I
talAI
14
I
ADDRESS VALID
~
E
Q)
:2:
..
en
..J
>
talA-PHI
I
I
TYPICAL APPLICATION INFORMATION
I
~
cascading the' ACT2151 and' ACT2153
The 'ACT2151 and 'ACT2153 are easily cascaded in width and depth. Wider addresses can be compared by
driving the AO-A9 inputs of each device with the same index and a')plying the additional address bits to the
00-010 inputs. The select (8) input allows these devices to be cascaded in depth. When a device is
deselected, the MATCH output is driven high. It should be noted that a decoder can be used to drive the
select inputs since the propagation delay from select to match is much faster than from address to match.
MATCH on the 'ACT2153 is an open-drain output for easy AND-tying. Figure 4 shows the 'ACT2153
cascaded.
w
5>
w
a:
c..
IU
:J
C
cache coherency through bus watching
When cache designs are implemented, the problem of cache coherency is always a concern. One solution to
this problem is to implement bus-watching using the ACT2151 or ACT2153. By storing the same tags in the
bus-watcher RAM as are stored in the cache tag RAM, the bus-watcher will indicate a hit every time a cache
address passes down the main address bus. If data is being modified in main memory, the index can be
passed to the cache tag RAM for invalidation. Figure 5 shows a possible bus-watcher implementation.
I
I
application
Due to the high-performance switching characteristics of the ACT2151 and ACT2153, it is necessary that the
address inputs not be allowed to float in the three-state condition. Proper termination techniques should be
employed. It is recommended that the RC time constant associated with the address inputs (63.2% of rise
time at AO-A9) not exceed 60 ns.
I
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
I
7-131
oa:
c..
SN74ACT2151, SN74ACT2153
2Kx12 CACHE ADDRESS COMPARATORS
TYPICAL APPLICATION INFORMATION
-
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r~
s:
M
I
C
R
OATA BUS
I
P
R
3
o
C
E
S
S
s:
D)
EN
-t AO-A10
0
:::s
AOORESS BUS AO-A31
R
D)
~
co
(1)
MAIN
MEMORY
CACHE
0
<
ORAM
SRAM
2K
0
(1)
A10
AO-A9
A10
A11-A20
AO-A9
A21-A31
,J
3
(1)
:::s
....
.o
.....
"tJ
+5V-
c.
..
-
c::
(")
....
'ACT2153
00-09
MATCH f--
010
AO-A9
fiE
.....
'ACT2153
00-010
MATCH t-- H
AO-A9
~
fiE
t--4~
5
5
(I)
"'C
::a
c
c:
n
00-09
+ 5 V - 010
MATCH
-
...... 00-010
fiE --:--
AO-A9
-.
PE
'ACT2153
AO-A9
5
,5
FIGURE 4. CASCADING THE 'ACT2153
-I
"'C
::a
m
<
m
:e
7-132
T
'ACT2153
i..-.
~
o
V
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MATCH f-- r--
fiE
f--
SN74ACT2151, SN74ACT2153
1Kx12 CACHE ADDRRESS COMPARATORS
TYPICAL APPLICATION INFORMATION
....o
Co)
:s
"C
o
DATA BUS
...
M
I
C
R
c..
....s:
Q)
0
E
Q)
CACHE
DATA
BUFFER
P
R
0
C
E
S
S
C)
ca
s:
EN
CO
:E
0
R
ADDRESS BUS
~
LATCH
C
1;
CONTRO~~
SIGNALS
'ACT2151
CACHE
~W
M EMORY WRITE
-+
CONTROL
LOGIC
TAG
.. 07
~
W
~
~
r-
BUFFER
'ACT2151
BUS
WATCHER
M
r--
sw
L:J
>
w
DRAM
a:
Mf-
07
c..
J
t-
MAIN
MEMORY
A
(J
:::::>
C
LATCH
I
DMA --+
c
o
MAIN ADDRESS BUS
a:
-
c..
FIGURE 5. BUS WATCHING USING THE 'ACT2151
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS. TEXAS 75265
7-133
<
r-
!a
~
CD
3
o
-<
~
C»
::::I
C»
CQ
CD
3CD
...::::I
..
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o
c.
c
n
..
...en
7-134
SN74ACT2152, SN74ACT2154
2K x 8 CACHE ADDRESS COMPARATORS
D3050. SEPTEMBER 19B7-REVISED NOVEMBER 19B7
•
•
•
•
•
•
•
JD DR N PACKAGE
Fast Address to Match Delay
25 or 35 ns Max
(TOP VIEW)
RESET
A4
A3
A2
Al
AO
GND
GND
DO
Dl
D2
D3
Common I/O with Read Feature
On-Chip Address/Data Comparator
On-Chip Parity Generator and Checking
Parity Error Output, Force Parity Error Input
Easily Expandable
Choice of Open-Drain or Totem-Pole
MATCH Output
•
EPICTM (Enhanced Performance Implanted
CMOS) 1-pm Process
•
Fully TTL-Compatible
R
W
description
The ' ACT21 52 and 'ACT21 54 cache address
comparators consist of a high-speed 2K x 9
static RAM array, parity generator, parity
checker, and 9-bit high-speed comparator. They
are fabricated using advanced silicon-gate
CMOS technology for high speed and simple
interface with bipolar TTL circuits. These cache
address comparators are easily cascadable for
wider tag addresses or deeper tag memories.
Significant reductions in cache memory
component count, board area, and power
dissipation can be achieved with these devices.
The' ACT21 52 has a totem-pole MATCH output
while the' ACT2154 has an open-drain MATCH
output for easy AND-tying.
en
A5
A6
A7
AS
A9
A10
VCC
D4
D5
D6
D7
MATCH
S
PE
~
CJ
::::I
"C
..o
Q.
~
C
Go)
E
Go)
C')
ca
ca
c
:iI:
~
o
E
:iI:
FN PACKAGE
(TOP VIEW)
N
M
4
3
Go)
Ii
(j)
~ ~~~
....I
>
10
DO (9)
02 (11)
C)
...I
-
tThese symbols are in accordance with ANSI/IEEE Std 91·1984.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-137
SN74ACT2152, SN74ACT2154
2K x 8 CACHE ADDRESS COMPARATORS
functional block diagram (positive logic)
(1 )
<
r-
-
(13)
~
--=::$j
3:
CD
3
'-
_~N
-f
."
w-I
1-
8x
7-139
SN74ACT2152, SN74ACT2154
2K x 8 CACHE ADDRESS COMPARATORS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. -1.5 to 7 V
Input voltage, any input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -1.5 to 7 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
ooe
NOTE 1: All voltage values are with respect to GNO.
recommended operating conditions
..o
"'C
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
VIH
High-level input voltage, write or compare cycles
2.2
VCC+ 0 . 5
VIH
High-level input voltage, read cycle
2.6
-0.5
VCC+0.5
0.8
o
_
V
v
Low-level input voltage (See Note 2)
VOH
High-level output voltage, MATCH (' ACT2 154) and PE outputs only
5.5
V
10H
High-level output current, MATCH (' ACT2 152) and 00-07
-8
rnA
8
. 24
10L
Low-level output current
rnA
24
rnA
8
rnA
70
°c
MATCH -
'ACT2152
MATCH -
'ACT2154
PE
00-07
t:
(')
V
VIL
Q.
,.
UNIT
Operating free-air temperature
TA
0
rnA
NOTE 2: The algebraic convention, in which the more negative (less positive) limit is designated as minimum, is used in this data sheet
for logic voltage levels only.
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
High-level output MATCH ('ACT2154)
VOH = 5.5 V, VCC
current
and PE
High-level output MATCH ('ACT21 52)
10H = -8 mA,VCC
VOH voltage
and 00-07
PE
00-07
II
10Z
Input current
Off-state output current
t Short-circuit
lOS
output current
4.5 V
=
=
=
=
=
=
4.5 V
0.4
0.4
4.5 V
0.4
0.4
4.5 V
0.4
0.4
4.5 V
0.4
±1
0.4
±1
p.A
±5
±5
p.A
VCC
=
5.5 V
150
rnA
RESET at 3 V, VCC
=
5.5 V
=
5.5 V
=
5.5 V
= 24 rnA, VCC
= 8 rnA, VCC
10L = 24 rnA, VCC
10L = 8 rnA, VCC
VI = O-Vce, Vee
Vo = O-VCC, VCC
ICC3 Supply current (deselected)
Ci
Input capacitance
Co
Output capacitance
3.7
3.7
5.5 V
5.5 V
Sat VIH
and 00-07
ICC2 Supply current (reset)
5
=
I MATCH (' ACT2 152) Vo = 0,
ICCl Supply current (operative)
5
Sat 0 V
RESET at 0 V, VCC
Sat 0 V
RESET at 3 V, VCC
Sat 3 V
f
f
=
=
150
50
1 MHz
50
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
V
85
125
85
125
rnA
5
25
5
25
rnA
75
105
75
105
rnA
5
pF
6
pF
5
6
1 MHz
p.A
V
t All typical values are at VCC = 5 V, T A = 25 °c.
t Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
7-140
UNIT
5.5 V
MATCH - 'ACT2154 10L
Low-level output MATCH - 'ACT21 52 10L
voltage
SN74ACT2152-35
SN74ACT2154-35
MIN Typt
MAX
=
10H
VOL
SN74ACT2152-25
SN74ACT2154-25
MIN Typt
MAX
SN74ACT2152, SN74ACT2154
2K x 8 CACHE ADDRESS COMPARATORS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted), see Figures 1, 2, and 3
...
t/)
compare cycle
(,)
PARAMETER
ta(A-M)
Access time from address to MATCH
talA-PI
Access time from address to
ta(S-M)
Access time from S to MATCH
to(D-M)
Propagation time, data inputs to MATCH
PE high
SN74ACT2152-25
SN74ACT2152-35
SN74ACT2154-25
MIN Typt
MAX
SN74ACT2154-35
MAX
MIN Typt
or low
to(RST-MH) Propagation time, RESET low to MATCH high
::::s
"C
...o
UNIT
c..
19
25
20
35
ns
21
28
27
38
ns
12
15
13
18
ns
...c
CI)
E
CI)
11
16
12
18
ns
C)
12
18
13
20
ns
CO
6
12
8
15
ns
CO
tp(S-MH)
Propagation time,S high to MATCH high
tpiW-MH)
Propagation time, W low to MATCH high
9
14
9
15
ns
to(W-PH)
Propagation time, W low to PE high
7
14
8
18
ns
tv(A-M)
MATCH valid time after change of address
4
4
ns
tv(O-M)
MATCH valid time after change of data
2
2
ns
tv(S-M)
MATCH valid time (low) after S high
2
2
ns
tv(A-P)
PE valid time after change of address
6
6
ns
C
:?1
~
o
E
CI)
:?1
(j)
..J
>
read cycle
PARAMETER
SN74ACT2152-25
SN74ACT2152-35
SN74ACT2154-25
MIN Typt
MAX
SN74ACT2154-35
MIN Typt
MAX
Read Access time from address to 00-07
UNIT
25
30
26
35
ns
ten(S-O) Enable time,S low to 00-07
12
20
14
20
ns
ten(R-O) Enable time, R low to valid 00-07 output
16
20
18
20
ns
tp(R-MH) Propagation time, R low to MATCH high
7
12
8
15
ns
to(R-PH) Propagation time, R low to PE high
7
15
8
18
ns
15
20
16
20
ns
ta(A-O)
tdis
00-07 output disable time from high or low level
I From R, 5, W
t All typical values are at VCC = 5 V, TA = 25°C.
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-141
SN74ACT2152, SN74ACT2154
2K x 8 CACHE ADDRESS COMPARATORS
timing requirements over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
SN74ACT2152-25
SN74ACT2152-35
SN74ACT2154-25
SN74ACT2154-35
MIN NOM MAX
MIN
twlRSTLl
Pulse duration, RESET low·
twlWL)
Pulse duration,
tw(WL)PE
W low,
Pulse duration, W low,
tsu(A)
Address setup time before
tsulD)
thiS)
W high
l5E setup time before W high (see Note 3)
Chip select setup time before W high
~ inactive setup time before W high
Address hold time after W high
Data hold time after W high
Data hold time after W low with MATCH high,
PE hold time after W high
Chip select hold time after W high
tAVWH
Address valid to write enable high
tsulP)
tsu(S)
tsu(RST)
thlA)
.
""C
th(WL-D)
o
th(P)
0r::::
....en
(')
_
thIWH-D)
without writing
PE
writing ~ (see Note 3)
W low
Data setup time before
(see Note 4)
NOM
MAX
UNIT
30
35
ns
15
20
ns
15
20
ns
0
0
ns
10
15
ns
10
15
ns
10
15
ns
15
20
ns
0
0
ns
5
5
ns
10
10
ns
5
5
ns
0
15
0
ns
20
ns
NOTES: 3. Parameters twPE(WL) and tsu(PLIIPply only during the write cycle timing when writing a parity error.
4. th(WL-D) guarantees that when W is taken low during a compare cycle with MATCH high, match will remain high without
a glitch low. (As shown in the function table, W low forces MATCH high). th(WL-D) is guaranteed indirectly by tv(D-M) and
tp(W-MH)·
7-142
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ACT2152, SN74ACT2154
2K x 8 CACHE ADDRESS COMPARATORS
PARAMETER MEASUREMENT INFORMATION
~-:-5-;;-
FROM OUTPUT-----1. FTEST
~DlNT
UNDER TEST
---3V
INPUTJ
TC' -
I .
I
I
I+- tpd---+l
50 pFt
~
I
o
c.
..,
cC1)
r+I
_----Ill
OUTPUT
LOAD CIRCUIT
.
"'C
GND
tpd
~
,
E
C1)
en
VOLTAGE WAVEFORMS
ca
c
ca
FIGURE 1. T ACT2152 MATCH OUTPUT
----CI...--- VCC
I
I
INPUT
TEST
FROM OUTPUT ----e POINT
UNDER TEST
.
~
tf f4-6 ns
lr:'1_ _ _ _-:::-~~I- - -. - - - - 3 V
:j;,
RL - 220
TCL -
--+:
-+t tr 14-6 ns
2.7 V
1.5 V
I
11.5 V
0.3 V
I
I
I
GND
I
I+----- tpd--+l
50 pFt
14--tpd---+l
:
I
I
I
OUTPUT
VOLTAGE WAVEFORMS
FIGURE 2. OPEN-DRAIN MATCH AND PE OUTPUTS
ten
tdis
---e---VCC
RL
I tpZH
tpZL
I tpHZ
tpLZ
52
CLOSED
OPEN
CLOSED
CLOSED
OPEN
OPEN
OPEN
50 pF
640
n
50 pF
50 pF
-
tod or tt
.5V
, - - - - - - OV
I+-
tPZL...,
--./ I4-tpLZ
I
I
1.5 V
I
I
I I
I I
I I
""VCC
£,0.3 V
--""][-==-.=.:
tpHz-+I t4- T
14-
tpZH-+I
OUTPUT
3V
I
I
OUTPUT
OPEN
1.5V
I
LOAD CIRCUIT
S1
OPEN
CLOSED
n
INPUT
FROM OUTPUT ---4IIJ-""'V'",--'
UNDER TEST
CL t
640
I
VOL
l..
~
1.5 V
-::'-=--='-=-.f VOH
0.3 V
",,0 V
VOLTAGE WAVEFORMS
FIGURE 3. 3-STATE DATA OUTPUTS
tCL includes probe and test fixture capacitance.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
~
o
E
C1)
:2:
en
....I
>
LOAD CIRCUIT
PARAMETER
tn
1J::::s
7-143
SN74ACT2152, SN74ACT2154
2K x 8 CACHE ADDRESS COMPARATORS
PARAMETER MEASUREMENT INFORMATION
<:
write cycle timing
r~
'(l:!li
AO'A10~......_ _ _ _ _ _ _ _A_D_D_R_ES_S_V_A_L_ID_ _ _ _ _ _ _ _
s:
~tsuIAI---.I
CD
3
o
MI41-----thIAI---~tl
I tAVWH---~tl
14
I
I
I:
-<
s:
I»
:
MMI-----,:-tsuISI----t
..!.--thISI--.!
:s
I»
I
w
cc
CD
r.-
3CD
:s
....
,
.
o
00-07
"'0
"""-1- - - - - -
twIWLl/twIWLIPE...J
Isee Note 31
I
~'r'iI''''r'''Ir''''a
I
Q.
n
....
(I)
PE (INPUT)
1OII14---tt*!-thIWH-DI
I
I
I
!
I
t+t-
PE IOUTPUT)
I
I
14-- thlPI---.i
----+f
tsulPI
Isee Note 31
I
I
:
MATCH
~
I I
t+- tsuIDI--+f
I
I
I
I
c
-
DATA V;ALID
"I'''''Il''''':r''II.,..r'W.,.......
I
',\...---+:---I+- tpIW-PHI--.I
reset cycle timing
RESET
I~
_________
j.-twIRSTLI
"4
tsulRSTI~
ADDRESSr"---~------
w
"-----I
I
I
I
MATCH
I
~
.1
tpIR-MHI
NOTE 3: Parameters twlWL)PE and tsulP) apply only during the write cycle when writing a parity error.
7-144
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ACT2152, SN74ACT2154
2K x 8 CACHE ADDRESS COMPARATORS
PARAMETER MEASUREMENT INFORMATION
en
.....
u
compare cycle timing
AO-A 10
~
X
ADDRESS VALID
14
talAI
.1
..
"'C
D_A_T_A_V_AL_ID--+!_ _
1
1414---tpIDI
DA_T_A_V_A_L1_D_ _ _ _
I
1
1
I
1
I
.....
~
C
Q)
E
Q)
I
1
1-.1
1
en
ca
c
ca
I
I
I+- tviD-MI
1
1
1
I+--talSI~
,.
.1
1
I
1
,
tviA-MI
:E
tpS-MHI .....I·t----·~1
tvIS-MI-I4I.II------1.~1
~
I
o
~
~~---+:--~*:=============:V~·~t.--.I-
:
e.
1
1
:
MATCH
.....,ir---J~'-_____
.1
1
o
:
XXXXXX
. . . . . .:...... i ~___
00-07 ...
I+---taIA-PI--+I
,
I
tviA-PI
talA-PI
\_~1~____~1_______7
E
Q)
:E
en
..
....J
>
read cycle timing
AO-A10
:::s
\IW'\i
ADDRESS VALID
~--------------_I_--------------~
X
----------~l~---------------------------------
,
1
1
I
1
1
,I
I
1
1
1
1144---..+-1 taiA-DI
R ----,
I~----~I---------------~I
I
1144--~.It-tenIR-DI:
00-07 ---:----""'I(\-,_ _ _ _ _
tenIS-DI-toI14t---~.'
I4- tdi s -+t
...I*----------~
~tpIR-MHI
MATCH
I
I
I+-tdis~
I
'(-------'j-
,'----
I)
1
~tpIR-PHI
PE
1
, I
1
----
-)
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-145
SN74ACT2152, SN74ACT2154
2K x 8 CACHE ADDRESS COMPARATORS
TYPICAL APPLICATION INFORMATION
<
r-
cascading the ' ACT2152 and ' ACT2154
The' ACT2152 and' ACT21 54 are easily cascaded in width and depth. Wider addresses can be compared
by driving the AO-A 10 inputs of each device with the same index and applying the additional address bits
to the 00-07 inputs. The select (5) input allows these devices to be cascaded in depth. When a device
is deselected, the MATCH output is driven high. It should be noted that a decoder can be used to drive
the select inputs since the propagation delay from select to match is much faster than from address to
match. MATCH on the' ACT2154 is an open-drain output for easy AND-tying. Figure 4 shows the' ACT2154
cascaded.
~
s:
CD
3
o
-<
s:
D)
:sD)
cache coherency through bus watching
When cache designs are implemented, the problem of cache coherency is always a concern. One solution
to this problem is to implement bus-watching using the' ACT2152 or ' ACT21 54. By storing the same
tags in the bus-watcher RAM as are stored in the cache tag RAM, ,the bus-watcher will indicate a hit every
time a cache address passes down the main address bus. If data is being modified in main memory, the
index can be passed to the cache tag RAM for invalidation. Figure 5 shows a possible bus-watcher
implementation .
CQ
CD
3
:s....
CD
.o
"'C
c.
c
application
C')
....
tn
-
Due to the high-performance switching characteristics of the' ACT2152 and' ACT21 54, it is necessary
that the address inputs not be allowed to float in the three-state condition. Proper termination techniques
should be employed. It is recommended that the RC time constant associated with the address inputs
(63.2% of rise time at AO-A 10) not exceed 60 ns.
-
M
I
C
R
DATA BUS
I
P
R
MAIN
MEMORY
CACHE
0
C
E
S
EN
-t
s
0
AO·A11
ADDRESS BUS AO-A26
R
~
DRAM
SRAM
4K
0
A11 AO-A10 A12-A18
A11
'ACT2154
'ACT2154
~ 00-06
+5V- f-- 07
AO-A10
-
MATCH
PE
1000- 00-07
'Am IS.
4>
MAT~
S
PE
tU
--
PE
AO-A10
~
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PE
'ACT2154
00-07
AO-A10
IS
s
TEXAS
! ' - 1--4
+lV
FIGURE 4. CASCADING THE 'ACT2154
7-146
MATCH
AO-A10
s
00-06
+5V-07
JV
AO-A10 A19-A26
MATCH
--
PE-
SN74ACT2152, SN74ACT2154
2K x 8 CACHE ADDRESS COMPARATORS
TYPICAL APPLICATION INFORMATION
...en
(,)
:::s
DATA BUS
M
I
C
R
"C
...o
c..
*
0
p
R
...c
CD
CACHE
DATA
BUFFER
0
C
E
S
S
E
CD
C)
ca
ca
EN ...
c
~
0
R
~
ADDRESS BUS
o
E
CD
.. C
~
LATCH
en
....I
..
>
~~
CONTROL--.
SIGNALS
M EMORY WRITE --..
.. w
CONTROL
LOGIC
'ACT2152
CACHE
TAG
M-
07
IIF
-
j
~
W
r
f-+-i
'"'-
BUFFER
'ACT2152
BUS
WATCHER
DRAM
M,.......
07
I
t
MAIN
MEMORY
...
DMA ....
-
MAIN ADDRESS BUS
FIGURE 5. BUS WATCHING USING THE 'ACT2152
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-147
<
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(I)
7-148
512
x
TACT2150
8 CACHE ADDRESS COMPARATOR
D2993. JANUARY 1987 - REVISED SEPTEM8ER 1987
•
0
OW, JO. OR NT PACKAGE
(TOP VIEW)
Address to MATCH Valid Time
T ACT21 50-20 ... 20 ns max
T ACT21 50-30 ... 30 ns max
RESET
A5
A4
A3
A2
D3
DO
D1
D2
300-Mil 24-Pin Ceramic Side-Brazed or
Plastic Dual-In-Line or Small Outline
Packages
0
53 mA Typical Supply Current
0
On-Chip Parity Generation and Checking
0
Parity Error Output/Force Parity Error Input
en
VCC
A1
AO
A8
A7
A6
D5
D4
D7
D6
MATCH
S
~
(,)
::l
"C
.
o
c..
c:
~
CD
E
CD
C)
•
On-Chip Address/Data Comparator
W
0
Asynchronous, Single-Cycle Reset
PE
0
Easily Expandable
0
Fully Static
o
0
Reliable Advanced CMOS Technology
CD
0
Fully TTL Compatible
GND
CO
c:
CO
~
~
E
~
(j)
description
This B-bit-slice cache address comparator consists of a high-speed 512 x 9 static RAM array, parity
generator, parity checker, and 9-bit high-speed comparator. It is fabricated using Advanced CMOS
technology for high-speed, low-power interface with bipolar TTL circuits. The cache address comparator
is easily cascadable for wider tag addresses or deeper tag memories. Significant reductions in cache memory
component count, board area, and power dissipation can be achieved with this device.
When S is low and W is high, the cache address comparator compares the contents of the memory location
addressed by AO-AB with the data on 00-07 plus generated parity. An equality is indicated by the high
level on the MATCH output. A low-level output from PE signifies a parity error in the internal RAM data.
PE is an N-channel open-drain output for easy OR-tying. During a write cycle (S and W lowl. data on
00-07 plus generated even parity are written in the 9-bit memory location addressed by AO-AB. Also during
write, a parity error may be forced by holding PE low.
A reset input is provided for initialization. When RESET is taken low, all 512 x 9 RAM locations are cleared
to zero (with valid parity) and the MATCH output is forced high. If an input data word of zero is compared
to any memory location that has not been written into since reset, MATCH will be high indicating that
input data, plus generated parity, is equal to the reset memory location. PE will be high for every addressed
memory location after reset indicating no parity error in the RAM data. By tying a single data input pin
high, this bit will function as a valid bit and a match will not occur unless data has been written into the
addressed memory location. When cascading in the width direction, only one bit needs to be tied high
regardless of the address width.
The T ACT2150 operates from a single 5 V supply and is offered in a 24-pin 300-mil ceramic side-brazed
or plastic dual-in-line packages and plastic "Small Outline" packages. The device is fully TTL compatible
and is characterized for operation from 0 °C to 70 o C.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~ar~~I~~e ~!~:i~~ti~r :1~o::~:~:t~rOs~S not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © 1987. Texas Instruments Incorporated
7-149
....I
>
TACT2150
512 x 8 CACHE ADDRESS COMPARATOR
functional block diagram (positive logic)
<
rsa
3:
3
CD
o
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3:
C)
::::s
C)
cc
CD
3
CD
::::s
ET
RES
AO
Al
A2
A3
A4
A5
A6
A7
A8
....
.
o
DO
Q.
Dl
C
D2
"'a
....
til
()
D3
D4
D5
. . D6
D7
L
(22)
COMP
,.
8
0
(23)
}
(4)
(3)
r---
0
A
(2)
8,
,
(20)
(8)
~
(9)
~
(6)
~
(17)
~
(18)
~
(15)
~
(16)
t----
(13)
(10)
.,
8
-
r-;-
(7)
J
•
INPUT
BUFFERS
MA TCH
1
2k
~
~
PARITY
CHECKER
~ ~ (11)
EN
,..
Cl
>--I'
:......../
>--I'
~
10
-""""
(14)
r;::::L/
511
(19)
(21)
P P=Q
}Q
~
(5)
""
-""
-""""
j
~
W
~
W
W
""
""
'"--
w
RAM 512X9
R
t------
r0-
v-p-
~PARITV
GENERATOR
8
2k
II'
~
~
--
MATCH OUTPUT DESCRIPTION
MATCH
=
VOH if: [AO-A8]
=
FUNCTION TABLE
00-07 + parity.
or: RESET = VIL.
MATCH
7-150
=
VOL
OUTPUT
FUNCTION
MATCH
PE
DESCRIPTION
or:
S
= VIH.
L
IN
= VIL
L
L
H
Parity Error
or:
H
L
Undefined Error
if: [AO-A8]
*
DO-D7 + parity.
with
RESEi'
S=
VIL. andW
=
H
VIH.
=
VIH
Where
S=
TEXAS . "
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS, TeXAS 75265
Not Equal
H
VIL.
W=
VIH. RESET
Equal
=
VIH
PE
TACT2150
512 x 8 CACHE ADDRESS COMPARATOR
PIN FUNCTIONAL DESCRIPTION
PIN
DESCRIPTION
NAME
NO.
AO
22
....enCJ
"C
A1
23
A2
5
A3
4
A4
3
AS
2
A6
19
A7
20
A8
21
DO
7
01
8
02
9
:::s
.
o
a..
....C
Address inputs. Address 1 of 512-by-9-bit random-access memory locations. Must be stable for the duration of
the write cycle.
CI)
E
CI)
C)
ca
c
ca
:iE
W is
S is
~
D3
6
D4
17
D5
18
D6
15
~
07
16
(j)
Data inputs. Compared with memory location addressed by AO-A8 when
input data to RAM when
W is
at VIL and
S is
at VIH and
at VIL. Provide
o
at VIL'
E
Q)
GND
12
Ground
MATCH
14
When MATCH output is at VOH during a compare cycle, DO through D7 plus parity equal the contents of the
....
>
-
9-bit memory location addressed by AO through A8.
PE
11
Parity error input/output. During write cycles,
PE can
force a parity error into the 9-bit location specified by
AO through A8 when PE is at VIL' For compare cycles, PE at VOL indicates a parity error in the stored data.
PE is an open-drain output so an external pull-up resistor is required.
RESET
1
RESET input. Asynchronously clears entire RAM array and forces MATCH high when RESET is at VIL and W
is at VIH.
S
13
VCC
24
5-V supply voltage
W
10
Write control input. Writes DO through D7 and generated parity into RAM and forces MAT<;:H high when
Chip select input. Enables device when S is at VIL. Deselects device and forces MATCH high when S is at VIH.
at VIL and
S is
at VIL. Places selected device in compare mode if
W is
W is
at VIH.
application
Due to the high-performance switching characteristics of the T ACT21 50, it is necessary that the address
inputs not be allowed to float. Proper termination techniques should be employed. It is recommended that
the RC time constant associated with the address inputs (63.2% of rise time on AD-AS) not exceed 60 ns.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-151
TACT2150
512 x 8 CACHE ADDRESS COMPARATOR
absolute maximum ratings over operating free-air temperature range (unless otherwise specified)
Supply voltage range, Vce (see Note 1) ................................... -1.5 to 7 V
Input voltage range, any input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -1.5 to 7 V
Continuous power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 W
Operating free-air temperature range ....................................... 0 °C to 70°C
Storage temperature range ......................................... - 65°C to 150°C
<
r~
3:
3
NOTE 1: All voltage values are with respect to GND.
-<
recommended operating conditions
CD
o
3:
m
:::I
m
CQ
CD
3CD
PARAMETER
VCC Supply voltage
VIH High·level input voltage
low-level input voltage (See Note 2)
Vil
,..:::I
VOH High-level output voltage
IOH High-level output current
"0
IOl
low-level output current
TA
Operating free-air temperature
.
oQ.
C
,..
C')
en
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
0.8
V
V
5.5
-8
mA
VCC+ O. 5
2
-0.5
PE
MATCH
MATCH
V
8
PE
mA
16
cc
70
0
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for
logic voltage levels only.
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
10H = -8 mA, VCC = 4.5 V
VOH(M)
MATCH high-level output voltage
VOl(M)
MATCH low-level output voltage
10l = 8 mA,
VOl(PE)
II
PE low-level output voltage
Input current
10H = -20 p.A, VCC= 4.5 V
V
3.5
00
UNIT
VCC = 4.5 V
V
10l = 16 mA, VCC = 4.5 V,
VI = 0 V to 5.5 V
0.4
10
-150
0.4
10
-150
V
p.A
mA
Short-circuit MATCH output current
Vo = GND,
Supply current (operative)
RESET = VIH
ICC2
Ci
Co
Supply current (reset)
RESET =Vl
f = 1 MHz
f = 1 MHz
VCC = 5.5 V
TEXAS
53
95
53
95
mA
2.75
6
2.75
6
mA
pF
pF
5
6
t All typical values are at VCC = 5 V, T A = 25 cC.
7-152
2.4
0.4
lOS
Output capacitance
3.5
TACT2150-30
MIN Typt MAX
0.4
ICC1
Input capacitance
TACT2150-20
MIN Typt MAX
2.4
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
5
6
TACT2150
512 x 8 CACHE ADDRESS COMPARATOR
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
ta(A-MI
T ACT2150-30
TACT2150-20
PARAMETER
MIN
MAX
Access time from address to MATCH
MIN
MAX
20
ns
ta(A-PLI
Access time from address to PE low
22
30
ns
talA-PH)
Access time from address to Pi: high
30
35
ns
ta(S-Ml
to(D)
Access time from ~ to MATCH
10
15
ns
Propagation time, data inputs to MATCH
15
20
ns
to(R-MH)
Propagation time,
10
15
ns
to(S-MH)
Propagation time, ~ high to MATCH high
10
12
ns
10
12
ns
15
20
tp(W-MH) Propagation time,
RESET low to MATCH high
W low to MATCH
W low to PE high
high
tn
UNIT
30
to(W-PHI
Propagation time,
tv(A-M)
MATCH valid time after change of address
3
3
ns
ns
tv(A-P)
PE valid time after change of address
5
5
ns
1:)
::::s
"0
...o
c..
...
C
CI)
E
CI)
C)
ca
c
ca
:E
~
o
E
CI)
timing requirements over recommended ranges of supply voltage and operating free-air temperature
TACT2150-20
PARAMETER
twJRQ
Pulse duration, RESET low
tw(WLI
Pulse duration,
W low,
MIN
without writing
PE
twPE(WL) Pulse duration, W low, writing PE (see Note 3)
MAX
TACT2150-30
MAX
MIN
ns
35
40
20
25
ns
20
25
ns
tsu(A)
Address setup time before W low
0
0
ns
tsu{DJ
Data setup time before W high
20
25
ns
tsu(PI
PE
(see Note 3)
20
25
ns
tsu(S)
Chip select setup time before
W high
20
25
ns
tsu(RH)
RESET inactive setup time before first tag cycle
0
0
ns
th(A)
Address hold time after W high
0
0
ns
th(D1
Data hold time after
0
0
ns
th(PI
PE hold time after W high
0
0
ns
thIS)
Chip select hold time after
W high
0
0
ns
tAVWH
Address valid to write enable high
20
25
ns
setup time before
W high
W high
~
UNIT
US
....I
..
>
NOTE 3: Parameters twPE{WL) and tsu(P) apply only during the write cycle time when writing a parity error, tcPE(W)'
TEXAS
l!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-153
TACT2150
512 x 8 CACHE ADDRESS COMPARATOR
PARAMETER MEASUREMENT INFORMATION
--.---VCC
<
r~
FROM OUTPUT
UNDER TEST
3:
CD
3
o
--r1
RL - 330 ()
TEST
0INT
FROM OUTPUT
UNDER TEST
Cl - 30 pF
FI
CL - 30 P
-<
LOAD CIRCUIT
LOAD CIRCUIT
D)
FIGURE 1. TOTEM-POLE OUTPUTS
FIGURE 2. OPEN-DRAIN OUTPUTS
3:
:::I
D)
cc
3CD
~
tt------
~tfl+-6 ns
CD
1N:i
~
I
---::0
\~;V
I
.
I
0.3 V
I
,I,.-----""~
I
I4--tpd
OUTPUT
. . OU_T_P_U_T_ _..,.
OPEN-DRAIN OUTPUTS
TOTEM-POLE OUTPUTS
FIGURE 3. TIMING REFERENCE LEVELS
AO-AB
~I
00-07
I
I
I
~
-
MATCH
tp(W-MH)
PE (OUTPUT)
:e
'II"~""'-""'-""'-'--"""';""-...___D_A_T_A_V_A_L_ID__---'~
I
fiE
1
(see Note 3)
\
14
-,
I
I4------tp (W-PH)-+!
NOTE 3: Parameters twPE(WL) and tsu(P) apply only during the write cycle time when writing a parity error, tcPE(W)'
FIGURE 5. WRITE CYCLE TIMING
If--tw(RLI
_I
tsu(RH)--+i
----
A D D R E S S . FIRSTTAGCYCLE
MATCH
1
I
I
I~
M
tp(R-MH)
FIGURE 6. RESET CYCLE TIMING
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-155
<
r~
s:
CD
3
o
-<
s:
OJ
:l
OJ
CQ
CD
3
CD
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....
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a
c.
r:::
....en
(")
-
7-156
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
02900. JANUARY 1986 - REVISED MARCH 1988
•
•
•
•
•
Provides Control for 16K, 64K, and 256K
Dynamic RAMs
SN74ALS2967. SN74ALS2968 ... JD OR N PACKAGE
(TOP VIEW)
cs
Highest-Order Two-Address Bits Select One
of Four Banks of RAMs
Supports Scrubbing Operations and NibbleMode Access
Separate Output Enable for Multi-Channel
Access to Memory
48-Pin Dual-In-Line Package
description
The' ALS2967 and' ALS2968 dynamic memory
controllers (DMCs) are designed for use in
today's high-performance memory systems. The
DMC acts as the address controller between any
processor and dynamic memory array.
Two versions are provided that help simplify
interfacing to the system dynamic timing
controller. The' ALS2967 offers active-low Row
Address Strobe Input (RASI) and Column
Address Strobe Input (CASI), while the
, ALS2968 offers active-high Row Address
Strobe Input (RASI) and Column Address Strobe
Input (CASI) inputs.
The' ALS2967 and' ALS2968 have two basic
modes of operation, read/write and refresh.
During normal read/write operations, the row
and column addresses are multiplexed to the
dynamic RAM, with the corresponding RAS and
CAS signals activated to strobe the addresses
into the RAM. In the refresh mode, the two
counters cycle through the refresh addresses. If
memory scrubbing is not being implemented,
only the row counter is used. When memory
scrubbing is being performed, both the row and
column counters are used to perform readmodify-write cycles. In this mode all RAS
outputs will be active (low) while only one CAS
output is active at a time.
U)
::::s
"'C
...o
a..
....C
Q)
E
Q)
C)
ca
c
ca
OE
VCC
05
06
07
08
RAS2
CAS2
RAS3
CAS3
RASI or RASlt
MCO
MCl
:!
~
o
E
Q)
:!
en....I
>
SN74ALS2967. SN74ALS2968 ... FN PACKAGE
(TOP VIEW)
..J
Using two 9-bit address latches, the DMC will
hold the row and column addresses for any
DRAM up to 256K. These latches and the two
row/column refresh address counters feed into
a 9-bit, 4-input MUX for output to the dynamic
RAM address lines. A 2-bit bank select latch is
provided to select one of the four RAS and CAS
outputs. The two bits are normally obtained from
the two highest-order address bits.
....CJ
CASI or CASI t
RASO
CASO
RASl
CASl
00
01
02
03
04
GNO
MSEL
AO
A9
Al
A10
A2
All
A3
A12
A4
A13
GNO
LE
A5
A14
A6
A15
A7
A16
A8
A17
SELO
SEll
o
,_
oo~~
•
0
W
til
ItIl ItIl ItIl ItIl
uuu~~mo~ltIlCuCCCCoOu
ZZZCCCC~UUZ~U~U
9
NC
NC
A2
All
A3
A12
A4
A13
GNO
LE
NC
A5
A14
A6
A15
NC
NC
8
7 6
5 4 3 2
Z
1 68 67 666564 636261
10
11
60
59
12
13
58
57
14
15
16
56
55
54
17
53
52
51
50
18
19
20
21
49
48
47
46
45
22
23
24
25
26
44
NC
NC
NC
01
02
03
04
GNO
5E
VCC
VCC
05
06
07
08
NC
RAS2
2728293031323334353637383940414243
,.-..-..-..-.
NC-No internal connection
t •ALS2967 has active-low inputs CASI and RASI; •ALS2968 has
active-high inputs CASI and RASI.
The SN74ALS2967 and SN74ALS2968 are characterized for operation from O°C to 70 o C.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~a{::I~tl~ ~!:~~~ti~r :I~o::~:~:t::s~s not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright
© 1986. Texas Instruments Incorporated
7-157
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
logic symbols t
0
-<
3:
D)
:::s
~~~R
6
.
7
RAS
8 "
0
f
1
~ ...
(47)
(45)
(31)
(29)
A4
RASO
A5
RAS1
A6
RAS2
A7
RAS3
A8
A9
A10
1
2
3
4
A11
>
;g~R
5
6
7
8
~ }SEL
CASI
A12
CAS{~
(46)
-(44)
(30)
(28)
A13
CASO
A14
CAS1
A15
CAS2
A16
CAS3
A17
SELO
SEL1
CASI
(37)
-'"
(26)
(25)
(2)
(1)
(27)
(14)
(3)
(5)
(7)
(9)
(11)
(15)
(17)
(19)
(21)
(4)
(6)
(8)
(10)
(12)
(16)
(18)
(20)
(22)
(23)
(24)
(48)
EN
~} MODE
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS; TEXAS 75265
1
2
MSEL
3
CS
RASI
Q
4
5
LE
6
0
7
1
8
(43)
(42)
(41)
(40)
(39)
(35)
(34)
(33)
(32)
2
3
4
5
>~~~R
6
7
"Asf ~
3 ...
8."
(47)
(45)
(31)
(29)
0
1
2
3
4
>;g~R
5
6
7
8
~ }SEL
CAS I
t These symbols are in accordance with ANSI/IEEE Std '91-1984 and lEe Publication 617-12.
7-158
"'0
CAS{~
(46)
(44)
(30)
(28)
QO
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
logic diagram (positive logic)
....enCJ
MUX
OE
MCO
MCl
MSEL
cs
(37)
,. EN
'"~}
(26)
(2S)
1
(2)
::s
(43)
(42)
G4
,. GS
.,
(1)
r
9X
COUNTER
~
H'
I
9
CTR20
~
o
~p
(ROW)
2CT - 0
,.. Gl
6
CT C
(COL)
r-< p. 1 +/C2
J~)--~
'ALS2967 ONLY
SELO
SELl
Q)
E
Q)
en
ca
C
ca
:?!
>-
.
f-.-./
0
~
1
/
1
/
OMUX
17
:?!
,.. EN
en
XiV
1sl~
16
E
Q)
RAS DECODE
1
j
2
r-----/
0
V4
1
V4
3
V4
-'
>
i--
BCO
roo---
19~
r--
O}
10
1
G'IT
(27)
(14)
....C
Q3
04
05
06
07
08
'Vr-!--
10,4,S'V
11,4,S'V
GS
LATCHES
'ALS2968 ONLY
AO
Al
A2
A3
A4
AS
A6
A7
A8
A9
Al0
All
A12
A13
A14
A1S
Ale
A17
2,4,S
91
10
18
(BANK)
LE
~
0
c..
00
01
02
~~
11
12
13
14
RAS(
~
(33)
2,4,S
3~
4~
S~
(40)
~
1,4
f-.-./
~
(3S)
0/1.4
9
.
"C
0
G:r
12,4,S'V
,.
13,4,S'V k
""
ICl
(47)
(4S)
(31)
(29)
L;
9X
(ROW)
~
(S)
(7)
.19)
...!1.1l..(1S)
(17)
(19)
(21)
~
9
CAS DECODE
10
OMUX
,.. EN
~
~
(8)
(10)
(12)
(16)
(18)
(20)
(22)
1
r--:..-
(24)
9
10
-
(23)
~
9X
(COLUMN)
2
G4
0
1
I-GS
2
I-G6
3
G4
~
O}SZ 10
1
13
(BANK)
0}6G~
10
10
1
(10/20,4)7 'V '""
(46)
(44)
~~---~~~~~~-----CAS(
..!~
___ ....:-:.:.S~6!.0!:,l:.. _ _ _ _ _ _ _ _
(11/21,4)7 'V
G7
.JT
"
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 7S265
(12/22,4)7 'V
(13/23,4)7 'V
(30)
(28)
7-159
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
TABLE 1. PIN FUNCTION
<:
r-
PIN NAME
AO-A17
DMC is in the read/write mode and MSEL is low. A9-A 17 are latched in as the column address, and will drive 00-08
~
!:
CD
3
when MSEL is high and the DMC is in the read/write mode. The addresses are latched when the Latch Enable (LE) input
signal is low.
SELO, SELl
!:
Q)
::::I
Bank Select. These two inputs are normally the two highest-order address bits and are used in the read/write mode
to select which bank of memory will be receiving the RAS and CAS signals after RASI (' ALS2967) or RASI (' ALS2968)
o
-<
DESCRIPTION
Address Inputs. AO-A8 are latched in as the nine-bit row address for the DRAM. These inputs drive 00-08 when the
and CASI (' ALS2967) or CASI (' ALS2968) go active.
LE
Latch Enable. This active-high input causes the row, column, and bank select latches to become transparent, allowing
the latches to accept new input data. A low input on LE latches the input data.
MSEL
Multiplexer Select. This input determines whether the row or column address will be sent to the memory address inputs.
Q)
When MSEL is high, the column address is selected, while the row address is selected when MSEL is low. The address
CD
may come from either the address latch or refresh address counter depending on MeO and MCl (see Mode Control
cc
3CD
::::I
Function Table).
CS
r+
."
~
o
the same memory that the DMC is controlling.
OE
Co
c
a
en
-
Chip Select. This active-low input is used to enable the DMC. When CS is active, the DMC operates normally in all
four modes. When CS goes high, the device will not enter the read/write mode. This allows other devices to access
Output Enable. This active-low input enables/disables the output signals. When OE is high, the outputs of the DMC
enter the high-impedance state.
MCO-MCl
Mode Controls. These inputs determine in which of the four modes the DMC operates. The description of each of the
four operating modes is given in Table 2.
00-08
Address Outputs. These address outputs feed the DRAM address inputs and provide drive for memory systems having
capacitance of up to 500 picofarads.
RASlor
Row Address Strobe Input. During the normal memory cycles, the decoded RASn output (RASO, RAS 1, RAS2, or RAS3)
RASI
is forced low after receipt of an active Row Address Strobe Input signal. In either Refresh mode, all four RAS outputs
will be low while the Row Address Strobe Input signal is active. The RASI on the' ALS2967 is an active-low input while
on the' ALS2968, RASI is an active-high input. (For more details see timing diagrams).
RASO-RAS3
Row Address Strobe. Each of the Row Address Strobe outputs provides a RAS signal to one of the four banks of dynamic
memory. Each RASn output will go low when selected by SELO and SEL 1 after RASI ('ALS2967) or RASI ('ALS2968)
goes active. All four go low in response to RASI (' ALS2967) or RASI (' ALS2968) while in the refresh mode.
CASlor
Column Address Strobe Input. This input going active causes the selected CAS output to be forced low. The CAS I
CASI
input on the' ALS2967 is active low input while on the' ALS2968, CASI is active high input. (For more details see
timing diagrams.)
CASO-CAS3
Column Address Strobe. During normal Read/Write cycles the two selected bits (SELO, SEL 1) determine which CAS
output will go active following CASI (' ALS2967) or CASI (' ALS2968) going active. When memory scrubbing is being
performed, only the CASn signal selected will be active. For non-scrubbing cycles, all four CAS outputs will remain high.
7-160
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
TABLE 2. MODE-CONTROL FUNCTION TABLE
MC1
MCO
OPERATING MODE
L
L
Refresh Mode without Scrubbing. Refresh cycles are performed with only the row counter being used to generate
L
H
;:,
Refresh with Scrubbing/Initialize. During this mode, refresh cycles are done with both the row and column counters
generating the addresses. MSEL is used to select either the row or the column counter. All four RAS outputs go low
in response to RASI (' ALS2967) or RASI (' ALS2968), while only one CASn output goes low in response to CASI
L
to the address output lines using MSEL. SELO and SEL 1 are decoded to determine which RASn and CASn
H
o
c..
c
also be used during system power-up so that the memory can be written with a known data pattern.
Read/Write. This mode is used to perform read/write cycles. Both the Rowand Column addresses are multiplexed
C1)
E
Q)
C')
ca
c
ca
outputs will be active. The refresh counter is disabled while in this mode.
H
..
"C
~
(' ALS2967) or CASI (' ALS2968). The bank counter keeps track of which CAS output goes active. This mode can
H
t/)
~
(,)
the addresses. In this mode, all four RAS outputs are active while the four CAS outputs remain high.
Clear Refresh Counters. This mode clears the three refresh counters (row, column, and bank) on the inactive transition
of RASI (' ALS2967) or RASI (' ALS2968), putting them at start of the refresh sequence (see timing diagrams for more
detail). In this mode, all four RAS outputs are driven low after the active edge of RASI (' ALS2967) or RASI (' ALS2968)
~
~
o
so that DRAM wake-up cycles may also be performed.
E
C1)
~
CiS
..I
>
TEXAS . "
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS. TeXAS 75265
7-161
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
TABLE 3. ADDRESS OUTPUT FUNCTIONS
INPUTS
MODE
MC1
OUTPUTS 00-08
MCO
MSEL
CS
X
H
X
X
X
L
L
Row address t
Refresh without scrubbing
L
L
Refresh with scrubbing
L
H
L
Row counter address
Row counter address
Column counter address
Read/write
H
L
H
L
Column address t
All L
H
H
X
X
H
Clear refresh counter i
X
All L
TABLE 4. RAS OUTPUT FUNCTIONS
OUTPUTS
INPUTS
...o
""C
'ALS2967
'ALS2968
RASI
RASI
L
H
L
H
MCO
SEL1 t
SELot
CS
RASO
RAS1
RAS2
RAS3
L
L
X
X
X
X
L
L
L
H
X
X
L
L
L
L
L
L
L
L
L
H
L
H
H
MC1
Co
c:
,..n
H
L
-
H
L
t/)
L
H
H
H
H
L
X
X
L
H
L
L
H
H
H
H
L
L
H
H
L
H
H
H
L
H
H
H
L
X
X
X
X
X
X
H
H
H
H
H
X
X
L
L
L
L
H
H
H
H
TABLE 5. CAS OUTPUT FUNCTIONS
OUTPUTS
INPUTS
'ALS2967 'ALS2968
CAS I
CASI
L
H
L
L
H
H
MC1
MCO
SEL 1 t
SELot
L
L
X
X
L
H
H
L
X
X
L
L
L
H
H
L
H
H
X
X
X
X
L
H
H
H
X
H
L
X
X
X
INTERNAL
CS
CASO
CAS1
CAS2
CAS3
BC1
BCO
X
X
X
H
H
H
H
L
L
X
L
H
H
H
L
H
X
H
L
H
H
H
L
X
H
H
L
H
H
H
X
H
H
H
L
X
X
X
X
X
X
X
X
L
L
L
H
H
H
H
X
H
L
X
L
H
H
L
H
X
L
H
H
H
L
X
H
H
H
H
H
X
X
H
H
H
H
X
X
H
H
H
H
H
t If LE is low, outputs will be the levels entered when LE was last high. If LE is high, outputs will follow address inputs as selected by MSEL.
i For' ALS2967, clearing occurs on the low-to-high transition of RASI; for' ALS2968, clearing occurs on the high-to-Iow transition of RASI.
7-162
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74ALS2967 r SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
read/write operation details
During normal read/write operations, the row and column addresses are multiplexed to the dynamic RAM
controlled by the MSEL input. The corresponding RASn and CASn output signals strobe the addresses
into memory. The block diagram in Figure 1 shows a typical system interface for a one-megaword dynamic
memory. The DMC is used to control the four banks of 256K memory~
...tn
CJ
::l
"C
For systems where addresses and data are multiplexed onto a single bus, the DMC uses latches, (row,
column, and bank) to hold the address information. Figure 5 shows a typical timing diagram using the
input latches. The twenty input latches are transparent when latch enable (LE) is high, and latch the input
data whenever LE is taken low. For systems in which the processor has separate address and data buses,
LE may be permanently high (see timing diagram in Figure 4).
'ALS2967/
'ALS2968
DYNAMIC
MEMORY
CONTROLLER
t..
~
ADDRESS
~
9,
ADDRESS
RAS
,
CAS1
W
I
,
I-CASI MSEL
t- I - -
A
2
.
I--
"'.
~ MEMORY CONTROL
r
MEMORY
TIMING
CONTROLLER
..
RAS2
.... CAS2
.. w
-----------BANK3
256K X 16-BIT
t..
1'..
RAS3
CAS3
f-1--
J\
-----------BANK2
256K X 16-BIT
).
MCQ,1 RASI
TN
W
... -----------BANK4
~
r.
r
256K X 16-BIT
RAS4
CAS4
W
~
DATA BUS
DATA BUS
..,
~
~
7
>
FIGURE 1. 1-MEGAWORD X 16-BIT DYNAMIC MEMORY
.
E
4)
C)
RAS1
4
CAS
4)
~
Yo.
,.--
2
...c
ca
c
ca
256K X 16-BIT
/
I
r---
4
SELD,1
BANK1
).
...o
c..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-163
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
read/write operations (continued)
The DMC is designed with heavy-duty outputs that are capable of driving four banks of 16-bit words,
including six checkbits used for error detection and correction.
<
r-
n
~
In addition to heavy-duty output drivers, the outputs are designed with balanced output impedances (25
both high and low). This feature optimizes the drive low characteristics, based on safe undershoot, while
providing symmetrical drive high characteristics. It also eliminates the external resistors required to pull
the outputs up to the MOS VOH level (VCC - 1.5 V).
~
(1)
3
o
-<
~________~______~~'\IBANK1
~
CI)
I
::::s
256K X 16·BIT
CHECK·BITS
RAS1
~-
~CAS1
CI)
CQ
~W
(1)
3(1)
~--
~ BANK2
,....
::::s
.
~
----- -_.!-----_.
256K X 16-BIT
RAS2
""C
I
o
~ CAS2
c:
~W
~---------.~-----~ BANK3
256K X 16-BIT
Q.
n
,....
-
en
~
MEMORY
TIMING
CONTROLLER
tMEMORY CONTROL I
r
~
_
~
~RAs3
----t CAS3
----t W
~--------256K X 16-BIT
- - - \ BANK4
------
J
u..---------M.. RAs4
u..-----------!..M CAS4
: W
EDAC
CONTROL
J
.I EN
J I
TRANSCEIVER
~------------------iM'l~D_I_R__~~__~
"r
' - - I_ _
'ALS616
16-BIT
....I~'\I
DATA BUS
EDAC
ERR -
FIGURE 2. 1-MEGAWORD X 16-BIT DYNAMIC MEMORY WITH ERROR DETECTION AND CORRECTION
7-164
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ALS2967. SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
memory expansion
With a 9-bit address path, the DMC can control up to one megaword when using 256K dynamic RAMs.
If a larger memory size is desired, the DMC's chip select (CS) makes it easy to expand the memory size
by using additional DMCs. A four-megaword memory system is shown in Figure 3.
t/)
....,
CJ
::::I
"C
...o
To maintain maximum performance in 32-bit applications, it is recommended that individual bus drivers
be used for each bank.
~
9,
DMC
~
!
MC1
.---
~
...
t-
DMC
2,
9
/
DMC
9
CHIP
SELECT
DECODER
en
r
ONE-MEGAWORD
MEMORY ARRAY
4 BANKS (256K)
ADDR
RAS
CAS
ONE-MEGAWORD
MEMORY ARRAY
4 BANKS (256K)
-I
>
-
----+ W
RAS MsEI
f-f---
RAS
CAS
.
CAS
I--
E
Q)
~
iN
~
MC1
...>
o
ONE-MEGAWORD
MEMORY ARRAY
4 BANKS (256K)
ADDR
~
Cs3
~
RAS
~
MC1
TTl
C)
CO
C
CO
~
CAS
/
~
~
E
Q)
ONE-MEGAWORD
MEMORY ARRAY
4 BANKS (256K)
ADDR
.. iN
Cs2
I
ADDRESS
?
"'
CS1
iii
~
w
9,
,/
MC1
Jo.
RAS
CAS
DMC
Q)
ADDR
... CSO
~
C
~
,/
TTT
a..
....,
W
...
MEMORY
CONTROL
~
~I
)I
I
MEMORY TIMING CONTROLLER
FIGURE 3. 4-MEGAWORD X 16-BIT DYNAMIC MEMORY
.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS. TEXAS 75265
7-165
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
refresh operations
<
r~
s:CD
3
o
-<
s:
D)
::::s
D)
CQ
CD
3
CD
The two 9-bit counters inthe ' ALS2967 and' ALS2968 support 128-, 256-, and 512-line refresh operations.
Transparent, burst, synchronous, or asynchronous refresh modes are all possible. The refresh counters are
advanced on the low-to-high transition of RASI on the ' ALS2967, and on the high-to-Iow transition
of RASI on the' ALS2968. The refresh counters are reset to zero on the low-to-high transition of RASI
on the' ALS2967, and on the high-to-Iow transition of RASI on the' ALS2968, if MC 1 and MCO are at a high
logic level. See Figure 8 for additional timing details.
When performing refresh cycles without memory scrubbing (MC1 and MCO both low), all four RAS outputs
go low, while all CAS outputs are driv~n high. Typical timing for this mode of operation is shown in Figure 6.
decoupling
Due to the high switching speed and high drive capability of the' ALS2967 and' ALS2968, it is necessary
to decouple the device for proper operation. Multilayer ceramic 0.1 ItF to 1 ItF capacitors are recommended
for decoupling. It is important to mount the capacitors as close as possible to the power pins (VCC and GND)
to minimize lead inductance and noise. A ground plane is recommended.
::::s
.
1'+
-a
o
Q.
c
n
1'+
-
(I)
7-166
, TEXAS'"
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS, TeXAS 75265
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage .............................................................. 7 V
Voltage applied to disabled 3-state output .................... ; . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 0 e
Storage temperature range ......................................... - 65 °e to 150 °e
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
MIN
NOM
MAX
4.5
5
5.5
V
V
mA
mA
2
10H
High-level output current
10L
Low-level output current
12
tw
Pulse duration
Setup time
tsu
(23) RASI low or RASI high
15
RAm high or RASI low
15
(25) LE high
(26) An before LE!
(27) SELn before LE!
20
(28) MeO or Me1 before RASlt or RASI!
25
(29) SELn before RASI! or RASlt
(30) An after LE!
15
th
Hold time
TA
Operating free-air temperature
UNIT
~
~
o
E
Q)
ns
~
5
Ui
....I
ns
>
5
ns
5
70
0
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
TEST CONDITIONS
VIK
Vee
VOH
vee
VOL
Vee
Vee
10L +
Vee
10ZH
Vee
10ZL
II
Vee
vee
IIH
Vee
IlL
Vee
lo§
Vee
lee
Vee
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
II
=
MIN
Typt
-18 mA
= -2.6 mA
10L = 1 mA
10L = 12 mA
Vo = 2 V
Vo = 2.7 V
Vo = 0.4 V
VI = 7 V
VI = 2.7 V
VI = 0.4 V
Vo = 2.25 V
10H
2.4
MAX
UNIT
-1.5
V
V
3.2
0.15
0.5
0.35
0.8
V
mA
30
20
/LA
-20
/LA
mA
0.1
20
-30
136
-0.1
/LA
mA
-112
mA
200
mA
t All typical values are at Vee = 5 V, TA = 25°e.
+Not more than one output should be tested at a time, and duration should not exceed 1 second.
§ The output conditions have been chosen to produce a current that closely approximates one half the true short-circuit output current, lOS.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS. TEXAS 75265
E
co
c:
co
5
(31) SELn after LE!
PARAMETER
....,
o
a.
Q)
C)
V
0.8
-2.6
(24)
(,)
:s
"C
c:
Q)
recommended operating conditions
Vee
...,en
7-167
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
switching characteristics, CL .- 50 pF
FROM
TO
(INPUT)
(OUTPUT)
t pd(1)
RASI or RASI
s:
t pd(2)
RA'Si or RASI
tpd(3)
~orCASI
3
t pd(4)
Any A
tpd(5}
tpd(6)
MSEL
tpd(7)
LEt
Any
LEt
D)
t pd(8)
t od(9)
CD
<
r-
PARAMETER
~
CD
o
-<
s:
D)
::J
cc
MIN
TYP*
MAX
Any Q
9
18
25
ns
RASn
3
10
18
ns
'CA'Sn
Any Q
3
3
17
18
ns
ns
Any Q
Any Q
3
9
9
12
20
ns
13
25
ns
RA'S
13
25
ns
13
24
ns
MCO or MC1
Any'CA'S
Any Q
7
13
24
ns
3
10
21
ns
3
9
19
ns
13
23
ns
9
20
ns
LEt
TEST CONDITIONst
RA'S
UNIT
t pd(10)
MCO or MC1
Any
3CD
t pd(11 )
MCO or MC1
Any'CA'S
VCC = 4.5 V to 5.5 V,
....
t pd(12)
~
Any Q
TA = OoC to 70 0 C
t od(13)
~
Any RAS
t pd(14)
~
Any'CA'S
9
19
ns
t pd(15)
SELO or SEL1
Any
RA'S
10
20
ns
t pd(16)
SELO or SEL 1
Any'CA'S
11
18
ns
t el'lL17)
tiE!
Any Q
10
19
ns
t en (18)
tiE!
Any
11
19
ns
::J
.
""C
o
a.
c
n
....
tn
RA'S
t en (19)
tiE!
Any'CA'S
11
19
ns
tdis(20)
tiEt
Any Q
10
20
ns
tdisi21)
tiEt
Any RAS
10
20
ns
tdis(22)
tiEt
Any'CA'S
9
20
ns
MIN
TYP*
MAX
switching characteristics, CL .. 150 pF
FROM
(INPUT)
(OUTPUT)
t pd(1 )
RASI or RASI
Any Q
12
20
27
ns
tpd(2)
RA'Si or RASI
RASn
5
12
23
ns
t od(3)
~orCASI
4
12
22
ns
t pd(4)
Any A
tpd(5)
t pd(6)
MSEL
'CA'Sn
Any Q
Any Q
5
8
20
26
ns
ns
LEt
Any Q
12
15
15
27
ns
t pd(7)
LEt
Any RAS
15
28
ns
t pd(8)
Any'CA'S
Any Q
ns
7
16
14
27
tpdt91
LEt
MCO or MC1
28
ns
t od(10l
MCO or MC1
Any RAS
5
12
25
ns
tpd(11)
MCO or MC1
Any'CA'S
4
tpd(12)
~
Any Q
tpd(13)
~
Any
t od(14)
~
t pd(15)
SELO or SEL 1
Any
t pd(16)
SELO or SEL1
PARAMETER
TO
TEST CONDITIONst
VCC
TA
= 4.5 V to 5.5 V,
= ooC to 70 0 C
11
23
ns
14
27
ns
RA'S
11
22
ns
Any'CA'S
12
22
ns
RA'S
13
23
ns
Any~
13
22
ns
t See Figures 10, 11, 12, and 13 for test circuit and switching waveforms.
*All typical values are at VCC = 5 V, TA = 25°C.
7-168
UNIT
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • PALLAS. TEXAS 75265
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
'----:--_---:-_ _ _ _P_R_oC_E_S_So_R_A_D_D_RE_S_S_ _ _ _ _ _ _ _~\\\\\~ DON'T
Q OUTPUTS
CS
MC INPUTS
RASI ('ALS2967)
--+---
ROW ADDRESS VALID
1
I
I
--+----4-----R-EA-D-I-W-R-IT-E-M-OlI-D-IE:I---------~X :
I
I I
I
I
.
If- t
~
I
I
d(2)---+I
I
I
-+I
~\\
I:
t3 t
I
I
I
If--
I
~----~------------t p d(3)-.j
tsu(AC) ~
--tI
t"?!/'I'i"-+I--------t p d(5)
I
------~:I--------------~~
~
I
CASn OUTPUT
\
I
y------------------.,;~~I._~~t~l-d-(3:-)-~-:---~1+-
I
-----111----------"
1oII~f-----
I
~
If- t p d(5) -+t
!4--t2t-,~
I
MSEL
I
I4-f:
)~'-----+:--------------I
1\\\\
I
f4- t su(29)
/11/
SELINPUTS ::xr---------B-A-NK~S~E~LE"":'C~T--------""'X\\\\\\\1 DON'T CARE M\\\\\\\\~
FIGURE 4. READ/WRITE CYCLE TIMING (MC1, MCO
1, 0), (LE = H)
t Parameters tsu(AR). tsu(AC). and th(AR) are timing requirements of the dynamic RAM. Parameters tl. t2. and t3 represent the minimum
timing requirements at the inputs to the DMC that guarantee DRAM timing specifications and maximum system performance. The minimum
requirements for tl. t2. and t3 are as follows:
tl (min) = t p d(4) max + tsu(AR) min - t p d(2) min
t2(min) = t p d(2) max + th(AR) min - t p d(5) min
t3(min) = t2 min + t p d(5) max + tsu(AC) - t pd(3) min
See the DRAM data sheet for applicable tsu(AR). tsu(AR). and th(AR)' In addition. note that propagation delay times given in the above
equations are functions of capacitive loading. The values used in these equations must relate to actual system capacitive loading,
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
:::s
..
"'C
o
c..
CD
E
CD
~.......---tl-lll----------
II4-- th(AR)t --+I I
I4-y
I
I
~ tpd(2)~ I
I
....tnCJ
....C
REFRESH MODE
r-----+I---------------
L:J"--"T"!p -------11--+-1-----'If
RASI ('ALS2968) - - - - t
tsu(AR)
RASn OUTPUT
CASI (' ALS2968)
ROW REFRESH ADD
COLUMN ADDRESS VALID
I
-~----~--------------rl+-______________~#~1~w~~1fi~p~O~N~'T~C~A~RE~~~~~~~00~~
I
~ t p d(9) i+-
\+-t1
CAS I ('ALS2967)
CARE~\\\\~
7-169
C)
ca
c
ca
:?!
~
o
E
CD
:?!
CiS
....
>
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
A INPUTS ~~~~~~~==~~~~~~~~~~~~~~~~~~~~~~~_PR_OC_E_SS_O_RA_D_DR_E__
ss
I+- t pd(4) -+\
<
r-
Q
OUTPUTS
~
__________
n:,~----------~.I~.~------------~.~--------COLUMN ADDRESS VALID
ROW ADDRESS VALID
~----~'w·~~-------------JIV·~--------------~
~
cs----------4-------~~~------------~~---------------------------------
3
o...
<
MCINPUTS __r~__R_EA_D_'W_R~'TE_M_O_Df__M_C'_.O_-~HL~______________~~___R_EA_D_W_R_1E_M_OD_E_M_C_'_.O_-_H_L______________
I
RASI (' AlS2967)
1
CD
----------1'"-----....
~
Q)
:s
Q)
RASI ('AlS2968)
I
I.
I+- th(AR) t --+j
-.
I r-I
I I
I+-!.-
3
CD
:s
....
lE
-----1,....--+-1--'1
I
...o
"tJ
\4-
I
,.......------+1----------...., ....___ _______
t w (25) ~
r
CASI (' AlS2967)
I
CASI (' AlS2968)
CASn OUTPUT
I
)
I
tsu( 27) --+!I
I
~I
\~.I------~(
t4- t p d(3) .......-I
i+- t p d(3)--+i
I
--II----II-----..J
- - - -.....
1
~
I
I
I
1
I
(I)
.------'L-
I
---+:----j4--t~P-d(-5)-:::;I--t------i4_----Jtpd(5) -..:
LI
MSEl _ _ _ _ _~I-~---~--~1
c..
cC')
-+1
RASnOUTPUT----------~----------TI~\~~~____________~--------------~t~n~~~-----------tsu(26)~
I
~
th(30) 1_
I
CD
....
I
t
tsu(AR)
(Q
Y
)II---II----L-~If__----H------'~ t p d(2) -J I
I+- t p d(2) ~
1I
_
______-+__-Jl~~I-+I--~------~I~------~~~____J.-I---------
I
I
I'+-.
~ th(31)
I
I
I
til
tsu(AC) ~
I
I4t-
I
\.
\-.----.....:---------I
t"'MO+----------
Wt.
,....
0>~________.........
_I.U
__
~
SElINPUTS~~~~~~::~~~::~~~~~~~~~~~D~O~NIT~CA~A~[~~~~~~~B~A~NK~S~EL~EC~T::::
FIGURE 5. READ/WRITE CYCLE TIMING USING INPUT LATCHES (MC1, MCO
H, L)
t tsu(AR). tsu(AC). and th(AR) are timing requirements of the dynamic RAM. See the DRAM data sheet for applicable specifications.
7-170
TEXAS
lJ1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
A INPUTS
Q OUTPUTS
DO~;! ftrE
DON'T CARE
...
til
CJ
NEXT ROW REFRESH ADDRESS VALID
ROW REFRESH ADDRESS VALID
---------J-:1'-----------------J
:s
I
"C
...o
c.
MCINPUTS __-J.~__R_EF_RE_S_HrMO-D-E-M-C-'-.O---L-L----------~---------RE-F-RE_SH_M_O_D_E_M_C_'_.O_-_L_L__--'~__
RE_A_DI_W_RIT_E_M_O_OE__
~tpd(1)~
RASI (' ALS2967)
\~~---------(
I
RASI (' ALS2968)
----"!'"tS-U-(A~',..)t-~--+I--l.--I----\
I
RASn OUTPUT
~ twIRL)
--------T~m.%
t
I
---+j
...
C
CD
E
CD
: \~------------~/
C)
I
CO
~ (W(RH) t ---.I
I
\~-------------------
I
Jill
~~~>.J._ _ _ _ _ _--£4"''III
C
CO
~
~
o
E
CD
~
FIGURE 6. REFRESH CYCLE TIMING (MC1. MCO = L. L) WITHOUT SCRUBBING
Ui
t tsu(AR). tw(RL). and tw(RH) are timing requirements of the dynamic RAM. See DRAM data sheet for applicable specifications.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
-I
>
7-171
SN74ALS2967, SN74ALS296B
DYNAMIC MEMORY CONTROLLERS
aOUTPUTS ______~--J'~i'--R-ow--R-EF-RE-s-H-A-DD-R-Es-s-v-A-lI-D_':,,:~CO_L_U_M_N_RE_F_RE_S_H_A_DD_R_ES_S_V_A_lI_D_'~,~---'~I~__________
14- t pd(9)
<
r-
~
~
s:
-<
RASI ('AlS2968)
1+-1
RASn OUTPUT
MSEl
cc
(1)
1
-------II
:
Co
I
I
I
~ th(AR) t ----+I I~
I I
I l
i+1
~~
c
_
I
II
11
~my/~~I-------------
L
~
j4- tpd(S)
\4-t p d(S)
1 4 - - - t2t - - -..
~ 1,---.,...-+1----------,
I
i
------rl----------~I
------i!r---------------.l\
~I.~--- t3t----~~
1
CASI ('AlS2968) _ _ _ _ _ _ _ _ _ _....J
--+I
\
~--------------------I
,r-------------------
1
j.-
I
tpd(3)~
\
~
14- t p d(3)
1
I+l-
FIGURE 7. REFRESH CYCLE TIMING (MC1. MCO
=
1
\1--_--+1_ _ _- - - - tsu(AC) t
cAsnouTPuT*------------------------------------~\~~~
S
en
--------
I+- t p d)2) --+i 1
I "
1
r+
o
1
~:~----..I),.....---+-:
I
CASI ('AlS2967)
;:,
."
i+ tpd(9) +I
1
I
tsu(AR)t-+j
s:
.
t4t
I
m
;:,
m
3(1)
I
RASI ('AlS2967) - - - . . . , . \
...__..
I ____________
(1)
3
o
-.t
MCINPUTS:::JK---------I-----------RE-F-RE-s-H-M-oD-E--~~c~1:~0---L-H----------------~X~i-------------------
u/l
L. H) WITH MEMORY SCRUBBING
t Parameters tsu(AR). tsu(AC). and th(AR) are timing requirements of the dynamic RAM. Parameters t2. t3. and t4 represent the minimum
timing requirements at the inputs to the DMC that guarantee DRAM timing specifications and maximum system performance. The minimum
requirement for t2. t3. and t4 are as follows:
t2(min) = t p d(2) max + th(AR) min - t p d(5) min
t3(min) = t2 min + t p d(5) max + tsu(AC) - t pd(3) min
t4(min) = t p d(9) max + tsu(AR) min - t p d(2) min
See the DRAM data sheet for applicable tsu(AR). tsu(AC). and th(AR)' In addition. note that propagation delay times given in the above
equations are functions of capacitive loading. The values used in these equations must correspond to actual system capacitive loading.
t A CASn output is selected by the bank counter. All other CASn outputs will remain high.
7-172
TEXAS
"'-!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
A,SEL INPUTS
~~~~~,\~~_\,\,\,\\,\\\\\~:~ON'T :CARE ~'\\,\~_%~~~~~,\,\~,\,\,\%\~~~
r-tpd(9)~
1
Q
OUTPUTS
CS
:
I
::::s
"'0
I
~\,\~\\~,\'\\~~~%'\\~~DON'T CARE~,\\,\,\_ _%'@\'\\~\~~~
1111
MC INPUTS
~
....tnCJ
--------------1X
.1
t su (28)
I
CLR REFRESH MODE MC1,0
X'-___________
HH
,1--------------------
-----------------~, : ,
I4-tw(24)~
---------------------'1
\'-_____________
RASI rALS2968_)
!4-
~ t p d(2)
RASn OUTPUT
o
....c
(1)
=
j+- t w (23) -.I
RASI r ALS2967)
.
c..
E
(1)
en
CD
c
CD
~
~
o
E
(1)
~
{_----..II
CiS
....I
>
FIGURE 8. REFRESH COUNTER RESET (MC1. MCO
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
=
H. HI
7-173
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
OE~
<
r-
A INPUTS
Q
s:
OUTPUTS
3
o
CS
-<
s:
Q)
---+t t pd(91i4I
I
I
I
I,
tpd(121~1
I
I
I
{
I
!4-
~ t pd(61i4- I
I
,----~J,
}'----------t-I______+-___
I
RASn OUTPUT
...
::I
LE
...
I
t pd(10l--.l
I
tpd(101~
I
I
,
I
I
~ten(1911+-:
o
CASn OUTPUT
(J)
14-
--~~~«=:::::r!=J~\..
t p d(111--.l
SEL INPUTS
I
14-
I
"
I
I
""C
I
I
I
I+-
'
I
~pd(131-+t
,I
tpd(151~
14I
I
14-
:
tpd(111~
__-;-:I _,
I
I
14-:
I
\
I,
I
:
,'-~:__)'J/>'>-
I
:?
14-
I
~ t pd(71t+- I
I
tpd(141~
l+-
t
,
I
I
"
j+-
, tdis(221~
:+-
t______:__~:::::,»}~ t pd(SII4-
:::::::~BA:N:K:S~E:;:LE~C~T:::::::::*~:::~:::::~B3A:NK:~SE~L~EC:T:::::::::Xr-~B~A~N~K~S~EL~E~CT~tpd(161~
(4-
RASI (' ALS29671 - L. RASI (. ALS296S1 - H. MSEL - H or L. CASI (' ALS29671 - L. CAS I (' ALS296S1 - H
FIGURE 9. MISCELLANEOUS TIMING
7-174
tdis(211...!
\ ....,.I________
I
~pd(14I-+l
I+-
I ,
I tpd(121~
~W«__+:-....,..a)---1"!--("..'__-+I_~?
I
CD
-
I
I
,
I
(Q
...
«(
-+l t en(1SIt+-
::I
C")
:
~ t pd(91 ~
MCINPUTS __~~~~~~I~M~C~1.~O_-~L~.H~~_M~C1~.O~-~H~L~I__~RE~A~D~/W~R~IT~E~M~OD~E~__~I~M~C~1.~O_-~H~L_____
Q)
c..
c
¥
X:
tpd(121~
t+tdis(201~
I+, ___-:-:_..J*:::::::::)~_~I_ . l._____' i »>'-
:
I
CD
3
~
~ten(17I~
~
CD
_______________________________________________________
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74ALS2967, SN74ALS2968
DYNAMIC MEMORY CONTROLLERS
SWITCHING TEST CIRCUIT
r'
FROM
DEVICEl1
OUTPUT
<
....CJtn
VCC
FROM
DEVICE
OUTPUT
~ ~'"
1
~
J
1
n
6BO
::::J
.
LZ.ZL
"C
o
S
tl..
2
Cl - 50 pF
....c:
HZ. ZH
Q)
E
Q)
C)
• tpd specified at CL = 50. 150 pF
ca
c:
ca
FIGURE 11. THREE-STATE ENABLE/DISABLE
FIGURE 10. CAPACITIVE LOAD SWITCHING
~
TYPICAL SWITCHING CHARACTERISTICS
VOLTAGE WAVEFORMS
TYPICAL OUTPUT DRIVER
,..-----3 V
INPUT
1.5V)(
\t.5V
_ _ _---I I " - - - - - - - - I
tpLH~
-
OV
tPHL~
~I
~VOL
vl
OUTPUT
---o---VCC
2'4r
.
OUTPUT TO
- . RAM ADDRESS
OR CONTROL
LINES
OV
---o---GND
FIGURE 12. OUTPUT DRIVE LEVELS
THREE-STATE TIMING
3-STATE
,----------------""""\
CONT~~~-----..Jt
I"''II_ _-I~~I_
_ _ _ _ _.......;I_ _~ I
VOH
l
:
OUTPUT
tpHZ
(DISABLE)
~VOH
- 0.5V
I
: t
tpZH
(ENABLE)
I'll
I
:
l
(HIGH IMPEDANCE)
VOL + 0.5 V
--------,1-----1 I
VOL
-
~- -
1I4'11---I.~I-(D1ik~LE)
(E~~ZBLLE)
-
-
-
-
-
-
-
-
-
-
- 3 V
-- ----
~.~ V
~II
I ,..-_ _ _ _ _ _ VOH
l-----
---2.4V
:
:
'\- I :
I'll
-
-
-
- -
- -
-
O.B V
VOL
.1
NOTE: Decoupling is needed for all AC tests
FIGURE 13. THREE-STATE CONTROL LEVELS
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
7-175
I
<
r~
s:CD
3
o
-<
s:
m
:::J
m
cc
CD
3
CD
...:::J
...o""C
Co
..
c
...
C")
(I)
7-176
SN74ALS6301, SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
02900. JANUARY 1986-REVISEO MARCH 1988
•
•
SN74ALS6301. SN74ALS6302 ... JD OR N PACKAGE
Provides Control for 16K, 64K, 256K, and
1 M Dynamic RAMs
(TOP VIEW)
cs
Highest-Order Two-Address Bits Select One
of Four Banks of RAMs
•
Supports Scrubbing Operations and NibbleMode Access
•
Separate Output Enable for Multi-Channel
Access to Memory
All
A3
A4
o
52-Pin Dual-In-Line Package
GND
LE
A5
A15
A6
A16
A7
A17
A8
A18
A9
A19
SELO
SEL 1
The' ALS6301 and' ALS6302 dynamic memory
controllers (DMCs) are designed for use in
today's high-performance memory systems. The
DMC acts as the address controller between any
processor and dynamic memory array.
Two versions are provided that help simplify
interfacing to the system dynamic timing
controller. The' ALS6301 offers active-low Row
Address Strobe Input (RASI) and Column
Address Strobe Input (CAS!), while the
'ALS6302 offers active-high Row Address
Strobe Input (RASI) and Column Address Strobe
Input (CASI) inputs.
.
o
c..
....c
Q)
E
Q)
C)
ca
c
ca
VCC
05
06
07
08
09
RAS2
CAS2
RAS3
CAS3
RASI or RASI t
MCO
MCl
:!!:
SN74ALS6301. SN74ALS6302 ... FN PACKAGE
(TOP VIEW)
Using two 1O-bit address latches, the DMC will
hold the row and column addresses for any
DRAM up to 1 M. These latches and the two
row/column refresh address counters feed into
a 10-bit, 4-input MUX for output to the dynamic
RAM address lines. A 2-bit bank select latch is
provided to select one of the four RAS and CAS
outputs. The two bits are normally obtained from
the two highest-order address bits.
The' ALS6301 and' ALS6302 have two basic
modes of operation, read/write and refresh.
During normal read/write operations, the row
and column addresses are multiplexed to the
dynamic RAM, with the corresponding RAS and
CAS signals activated to strobe the addresses
into the RAM. In the refresh mode, the two
counters cycle through the refresh addresses. If
memory scrubbing is not being implemented,
only the row counter is used. When memory
scrubbing is being performed, both the row and
column counters are used to perform readmodify-write cycles. In this mode all RAS
outputs will be active (low) while only one CAS
output is active at a time.
(,)
::::s
"'0
DE
'fP
description
....o
MSEL
CAS I or CAS I t
RASO
CASO
RASl
CASl
00
01
02
03
04
GND
AO
...J
1_o
0
0
~ ~
uuuu~~~ol~~clclclcicou
zzzzccccu~u~u~uoz
.-
9
NC
A2
A12
A3
A13
A4
A14
GND
8
7 6
0
54 3 2
-
W(/)(I)(/)(/)(/)
16867666564636261
10
11
60[ NC
59[ NC
12
58
13
57
14
56
15
55
54
01
02
03
04
GND
16
17
53
DE
'fP
18
52
LE
A5
A15
A6
A16
A7
A17
NC
19
51
20
21
50
22
48
23
47
46
VCC
05
06
07
08
09
RAS2
CAS2
NC
49
24
45
25
26
44
2728 293031 32 3334 35363738 3940414243
o
I~
t 'ALS6301 has active-low inputs CAS I and RASI; 'ALS6302 has
active-high inputs CAS I and RASI.
The SN7 4ALS630 1 and SN74ALS6302 are characterized for operation from OOC to 70°C.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~8r::1~18 ~!;~:~ti~f :llo::~:~:t::s~s not
TEXAS
~
INSTRUMENTS
POST OFFiCe BOX 655012 • DALLAS. TeXAS 75265
Copyright © 1986, Texas Instruments Incorporated
7-177
I
SN74ALS6301, SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
logic symbols t
<
r~
TP
s:
CD
.
-<
3
0
OE
MCO
MC1
s:
MSEL
:::s
RASI
CI)
cs
CI)
LE
CD
AO
co
3CD
A1
A2
:::s
A3
.
~
A4
"'tJ
A5
0
A6
c:
A7
Co
n
A8
til
A9
~
-
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
SELO
SEL1
CAS I
(13)
(40)
,.,
,.,
(28)
(52)
---
TP
4>
TP
'ALS6301
OE
EN
,.,
(14)
(2)
(4)
(44)
2
(43)
3
CS
RASI
Q<
(42)
4
LE
5
6
0
7
(38)
(37)
(36)
(35)
(34)
8
2
(8)
(45)
1
1
(6)
(46)
"0
MSEL
(1)
... 9
00
MCO
01
MC1
02
MSEL
03
cs
04
RASI
05
LE
06
AO
07
A1
08
09
A2
A3
3
(10)
4
(15)
5
6
(17)
(19)
>~~:R
7
(21)
(50)
RAS{! _
3 "'"
8
9
(23)
(3)
(5)
(7)
(9)
(33)
(31)
RASO
A5
RAS1
A6
RAS2
A7
RAS3
A8
A9
A10
1
A11
A12
A13
3
4
(16)
(18)
(20)
(22)
(24)
(48)
A4
0'"
2
(11)
5
6
7
8
>~~~R
CAS
r-
(49)
(47)
1 ....
2 ....
(32)
(30)
3 ....
A14
A15
CASO
CAS1
A16
A17
A18
A19
CAS2
CAS3
9 ..
(25)
(26)
(51)
'ALS6302
DYNAMIC MEMORY
CONTROLLER
~} MODE
(27)
(29)
'ALS6301
DYNAMIC MEMORY
CONTROLLER
~
~} SEL
SELO
CAS I
CAS I
SEL1
(13)
,..
EN
(28)
~
(29)
(14)
(2)
(4)
(6)
(8)
(10)
(15)
(17)
(19)
(21)
(23)
(3)
(5)
(7)
(9)
(11)
(16)
(18)
(20)
(22)
(24)
(25)
(26)
(51)
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
1
2
MSEL
CS
RASI
LE
0
3
Q(
(45)
(44)
(43)
4
5
6
(37)
8
2
(46)
(42)
(38)
7
1
(36)
(35)
(34)
.... 9
00
01
02
03
04
05
06
07
08
09
3
4
5
6
>~~:R
7
RAsn~
(50)
(48)
CAS{
(47)
(33)
(31)
8
9
o'
1
2
3
4
5
6
(49)
>~~~R
7
8
9
~ }SEL
CAS I
tThese symbols are in accordance with ANSI/IEEE Std-91-1984 and lEG Publication 617-12.
Pin numbers shown are for JD and N packages.
7-178
.. 0
~} MODE
(27)
(52)
(1)
4>
TP
'ALS6302
(40)
(32)
(30)
CASO
CAS1
CAS2
CAS3
SN74ALS6301, SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
logic diagram (positive logic)
...,tn
MUX
1401
Of
,., EN
1281
MCO
1521
111
MSEL
cs
CJ
~}
0
1
G3"
1271
MCl
::::::I
1461
1451
G4
,., G5
..
COUNTER
r--------<
CTR22
10
O~
r - - f--<
10
3~
9
~
1351
~
"1~
2.4.5
:~
~:::::;::
[ROW)
1381
1371
2.4.5
CT.
Gl
r- 1 +/C2
12[
13
/
141
15
16
17 1
/
...>0
E
(1)
DMUX
~
--;:;y
~~
•
8CO
r---
-
21~
(j)
0
V4
1
V4
2
3-
V4
1
G10
13
1
-O}
....I
>
1501
10.4.5"1
P
12.4.5"1 P
11.4.5"1
LE
fii
121
141
161
181
1101
1151
1171
1191
"'"i211
1231
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
~
Al0
151
All
171
A12
191
A13
A14
1161
A15
1181
AlB
1201
A17
1221
A18
1241
A19
~
SELO
SEL 1 1261
.!1.!L _
G5
LATCHES
-
f'o
ICl
~.
1131
ca
c
ca
C')
,., EN
/
20
[BANK)
1141
E
(1)
09
RAS DECODE
10~
1;~
19~
J~I-c[>-~
1291
------
C
(1)
06
07
08
~
18~
'ALS6301 ONLY
'ALS6302 ONLY
...,
::::::;::
[COL)
RASI
...0
n-
~ as
r
lOX
1.4
1~
2CT-0
1431
0/1.4
2~
.~
~
"C
00
01
02
03
04
13.4.5"1
1481
1331
1311
RASO
RASl
~2
RAS3
lOX
[ROW)
4~S
~ r--
10
CAS DECODE
10
DMUX
,... EN
~5
~ f--
J.5!!. _ _ _
"XiV
0
lOX
[COLUMN)
1
G4
G5
1
G6
2
10
G4
3
2
~
10
O}
1
5Z -10
13
[BANK)
0}6G~
23
~kD
L.c
10
R
~~6~~~Y_
1
-
-
110/20.4)7"1 h
111/21.417"1
-<{>- - - T
G7
1511
'ALS6302 ONLY
I- - - _______________
.JI
~
112/22.417"1
113/23.4)7"1
r-
1491
1471
1321
1301
CAS
Pin numbers shown are for JD and N packages.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-179
SN74ALS6301, SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
TABLE 1. PIN FUNCTION
<
r-
PIN NAME
AO-A19
~
3:
CD
3
o
<
3:
DMC is in the read/write mode and MSEL is low. A 1O-A 19 are latched in as the column address, and will drive 00-09
when MSEL is high and the DMC is in the read/write mode. The addresses are latched when the Latch Enable (LE) input
signal is low.
SELO, SEL 1
and ~ ('ALS6301) or CASI (,ALS6302) go active.
LE
D)
,..
.o
may come from either the address latch or refresh address counter depending on MCO and MC1 (see Mode Control
Function Table).
~
c
aen
Chip Select. This active-low input is used to enable the DMC. When
CS is
active, the DMC operates normally in all
four modes. When ~ goes high, the device will not enter the read/write mode. This allows other devices to access
""C
Q.
Multiplexer Select. This input determines whether the row or column address will be sent to the memory address inputs.
When MSEL is high, the column address is selected, while the row address is selected when MSEL is low. The address
CD
::::I
Latch Enable. This active-high input causes the row, column, and bank select latches to become transparent, allowing
the latches to accept new input data. A low input on LE latches the input data.
MSEL
CQ
3
CD
Bank Select. These two inputs are normally the two highest-order address bits and are used in the read/write mode
to select which bank of memory will be receiving the RAS and CAS signals after RASI (' ALS630 1) or RASI (' ALS6302)
D)
::::I
DESCRIPTION
Address Inputs. AO-A9 are latched in as the nine-bit row address for the DRAM. These inputs drive 00-09 when the
the same memory that the DMC is controlling .
DE
Output Enable. This active-low input enables/disables the output signals. When
DE is high, the
outputs of the DMC
enter the high-impedance state.
MCO-MC1
Mode Controls. These inputs determine in which of the four modes the DMC operates. The description of each of the
four operating modes is given in Table 2.
00-09
Address Outputs. These address outputs feed the DRAM address inputs and provide drive for memory systems having
RASlor
Row Address Strobe Input. During the normal memory cycles, the decoded RASn output (RASO, RAS 1, RAS2, or RAS3)
capacitance of up to 500 picofarads.
RASI
is forced low after receipt of an active Row Address Strobe Input signal. In either Refresh mode, all four RAS outputs
will be low while the Row Address Strobe Input signal is active. The 'R'AST on the' ALS6301 is an active-low input while
on the' ALS6302, RASI is an active-high input. (For more details see timing diagrams).
RASO-RAS3
Row Address Strobe. Each of the Row Address Strobe outputs provides a RAS signal to one of the four banks of dynamic
memory. Each RASn output will go low when selected by SELO and SEL 1 after RASI (' ALS6301) or RASI (' ALS6302)
goes active. All four go low in response to
CASlor
CASI
'R'AST (' ALS6301)
or RASI (' ALS6302) while in the refresh mode.
Column Address Strobe Input. This input going active causes the selected CAS output to be forced low. The CAS I
input on the' ALS6301 is active low input while on the' ALS6302, CAS I is active high input. (For more details see
timing diagrams.)
CASO-CAS3
Column Address Strobe. During normal Read/Write cycles the two selected bits (SELO, SEL 1) determine which CAS
output will go active following CASI (' ALS6301) or CASI (' ALS6302) going active. When memory scrubbing is being
performed, only the CASn signal selected will be active. For non-scrubbing cycles, all four CAS outputs will remain high.
TP
This active-low test input asynchronously sets the row and column input latches high, while forcing the two bank
select latches low. In normal operation,
7-180
fP is tied high.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ALS6301, SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
TABLE 2. MODE-CONTROL FUNCTION TABLE
MC,
MCa
OPERATING MODE
L
L
Refresh Mode without Scrubbing. Refresh cycles are performed with only the row counter being used to generate
...en
CJ
::::I
"C
the addresses. In this mode, all four RAS outputs are active while the four CAS outputs remain high.
L
H
.
Refresh with Scrubbing/Initialize. During this mode, refresh cycles are done with both the row and column counters
o
generating the addresses. MSEL is used to select either the row or the column counter. All four RAS outputs go low
c..
(' ALS6301) or CASI (' ALS6302). The bank counter keeps track of which CAS output goes active. This mode can
...
also be used during system power-up so that the memory can be written with a known data pattern.
CD
in response to RASI (' ALS630 1) or RASI (' ALS63021. while only one CASn output goes low in response to CASI
H
L
C
E
Read/Write. This mode is used to perform read/write cycles. Both the Rowand Column addresses are multiplexed
CD
to the address output lines using MSEL. SELO and SEL 1 are decoded to determine which RASn and CASn
C)
ca
ca
outputs will be active. The refresh counter is disabled while in this mode.
H
H
c
Clear Refresh Counters. This mode clears the three refresh counters (row, column, and bank) on the inactive transition
~
of RASI ('ALS6301) or RASI (,ALS63021. putting them at start of the refresh sequence (see timing diagrams for more
detail). In this mode, all four RAS outputs are driven low after the active edge of RASI (' ALS630 1) or RASI (' ALS6302)
~
so that DRAM wake-up cycles may also be performed.
o
E
CD
~
(ii
..
....I
>
I
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-181
SN74ALS6301, SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
TABLE 3. ADDRESS OUTPUT FUNCTIONS
<
r-
INPUTS
MODE
~
Refresh without scrubbing
s:
Refresh with scrubbing
MCO
MSEL
CS
L
L
X
H
X
X
X
L
L
L
H
(I)
3
o
Read/write
-<
H
Clear refresh counter i
s:
OUTPUTS QO-Q9
MC1
H
L
Row counter address
Row counter address
Column counter address
Row address t
L
H
L
Column address t
H
All L
H
X
X
X
All L
D)
:sD)
TABLE 4. RAS OUTPUT FUNCTIONS
co
INPUTS
(I)
3(I)
'ALS6301
'ALS6302
:s
...
RASI
RASI
.o
L
H
"'CJ
L
H
SEL1 t
SELOt
CS
RASO
RAS1
RAS2
L
L
X
X
X
X
L
L
L
H
X
X
L
L
L
L
L
L
H
Q.
C
...en
L
(')
H
OUTPUTS
MCO
MC1
H
L
L
H
H
H
H
L
X
X
RAS3
L
L
L
L
H
H
L
H
L
H
L
H
H
H
L
L
H
H
L
H
H
H
L
H
H
H
L
X
X
X
X
X
H
H
H
H
H
X
X
L
L
L
L
H
H
H
H
X
TABLE 5. CAS OUTPUT FUNCTIONS
INPUTS
'ALS6301
'ALS6302
CAS I
CASI
L
H
L
L
H
H
OUTPUTS
MC1
MCO
SEL1 t
SELOt
L
L
X
X
L
H
H
L
L
H
H
H
H
L
X
X
X
X
L
L
L
H
H
L
H
H
X
X
X
X
X
X
INTERNAL
BC1
BCO
X
X
L
L
L
H
H
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CS
CASO
CAS1
CAS2
X
X
X
X
X
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
H
H
H
H
H
X
X
H
H
H
H
H
H
H
H
CAS3
t If fi5 is low, the row and column address latch will be high. If fi5 is high, the row and column address latch will be at the levels entered
when LE was last high.
i For' ALS6301, clearing occurs on the low-to-high transition of RASI; for' ALS6302, clearing occurs on the high-to-Iow transition of RASI.
7-182
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74ALS6301, SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
read/write operation details
During normal read/write operations, the row and column addresses are multiplexed to the dynamic RAM
controlled by the MSEL input. The corresponding RASn and CASn output signals strobe the addresses
into memory. The block diagram in Figure 1 shows a typical system interface for a four-megaword dynamic
memory. The DMC is used to control the four banks of 1M memory.
...
U)
(.)
:::s
.
"C
o
For systems where addresses and data are multiplexed onto a single bus, the DMC uses latches, (row,
column, and bank) to hold the address information. Figure 5 shows a typical timing diagram using the
input latches. The twenty-two input latches are transparent when latch enable (LE) is high, and latch the
input data whenever LE is taken low. For systems in which the processor has separate address and data
buses, LE may be permanently high (see timing diagram in Figure 4).
...c:
CL.
(1)
E
(1)
C)
CO
c:
'ALS6301/
'ALS6302
DYNAMIC
MEMORY
CONTROLLER
t..
~
ADDRESS
~
10 ~
ADDRESS
I
L
r-
r-
4
RAS
SELO,1
2
2
,
f--
-"
r
"...r
o
E
(1)
CAS1
~
Cii
...I
>
-
RAS2
CAS2
rW
~----------BANK3
1M X 16·BIT
PI.
-f--
~ MEMORY CONTROL
~
RAS1
~----------BANK2
1M X 16·BIT
f-~ f- f - -
.
~
.,W
-"
CASI MSEL
•
.~
CO
1M X 16·BIT
r
f--
MCO,1 RASI
Yo.
,
4
CAS
")
BANK1
.!'..r
RAS3
.... CAS3
MEMORY
TIMING
CONTROLLER
Vi
W
~----------BANK4
1M X 16·BIT
PI.
~~
)
~
RAS4
CAS4
"W
.., >
"< 7
>
DATA BUS
DATA BUS
>
FIGURE 1. 4-MEGAWORD X 16-BIT DYNAMIC MEMORY
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-183
I
SN74ALS6301, SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
read/write operations (continued)
<
r~
s:
CI)
3
o
The DMC is designed with heavy-duty outputs that are capable of driving four banks of 16-bit words,
including six checkbits used for error detection and correction.
In addition to heavy-duty output drivers, the outputs are designed with balanced output impedances (25 (}
both high and low). This feature optimizes the drive low characteristics, based on safe undershoot, while
providing symmetrical drive high characteristics. It also eliminates the external resistors required to pull
the outputs up to the MOS VOH level (VCC - 1.5 V).
<
s:
1 M X 16-BIT
'ALS6301/
'ALS6302
DYNAMIC
MEMORY.
CONTROLLER
D)
::::s
D)
CQ
CI)
3CI)
SELO,1
::::s
r+
CHECK-BITS
1M X 16-BIT
.
"C
oQ.
MCO,1
C
RAST CASi
MSEL
C')
r+
2
In
1M X 16-BIT
MEMORY CONTROL
MEMORY
TIMING
CONTROLLER
w
1M X 16-BIT
~------I"
CAS4
~-----~MW
EDAC
CONTROL
'ALS632B
32-BIT
EDAC
DATA BUS
FIGURE 2. 4-MEGAWORD X 16-BIT DYNAMIC MEMORY WITH ERROR DETECTION AND CORRECTION
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ALS6301, SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
memory expansion
With a 1O-bit address path, the DMC can control up to four megaword when using 1 M dynamic RAMs.
If a larger memory size is desired, the DMC's chip select (CS) makes it easy to expand the memory size
by using additional DMCs. A sixteen-megaword memory system is shown in Figure 3.
U)
.....
(,)
:s
"'C
...o
a..
To maintain maximum performance in 32-bit applications, it is recommended that individual bus drivers
be used for each bank.
.....
"
~
...
DMC
/
!
f
..
eso
DMC
"
,.....--
"
MC1
TTT
~
C
CD
10,
':. RAS
...
10
/
~
I
ADDRESS
./
1 1_1
~
2... ~
DMC
,/
MC1
CS3
bD
rr--
Vi
"
ADDR
..
10
CAS
RAS MsEL
C
CAS
.
~
MC1
CS2
~
FOUR-MEGAWORD
MEMORY ARRAY
4 BANKS 11M)
OJ
ca
c
ca
~
~
ADDR
.. CS1
DMC
RAS
CAS
10
/
iii
ADDR
Vi
MC1
J.
E
CD
CD
~
(j)
RAS
CAS
....I
FOUR·MEGAWORD
MEMORY ARRAY
4 BANKS 11M)
Vi
..
..
o
E
FOUR-MEGAWORD
MEMORY ARRAY
4 BANKS 11M)
ADDR
RAS
CAS
FOUR-MEGAWORD
MEMORY ARRAY
4 BANKS 11M)
>
-
~ Vi
f---CHIP
SELECT
DECODER
Iii
MEMORY
CONTROL
~
+
.. I
)I
MEMORY TIMING CONTROLLER
I
FIGURE 3. 16·MEGAWORD X 16·BIT DYNAMIC MEMORY
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
7-185
SN74ALS6301. SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
refresh operations
The two 1O-bit counters in the' ALS6301 and' ALS6302 support 128-, 256-, 512-, and 1024-line refresh
operations. Transparent, burst, synchronous, or asynchronous refresh modes are all possible. The refresh
counters are advanced on the low-to-high transition of RASI on the' ALS6301, and on the high-to-Iow
transition of RASI on the' ALS6302. The refresh counters are reset to zero on the low-to-high transition
of RASI on the' ALS630 1, and on the high-to-Iow transition of RASI on the' ALS6302, if MC 1 and MCO
are at a high logic level. See Figure 8 for additional timing details.
<:
r-
~
s:
CD
3
o
<
s:
D)
:::s
When performing refresh cycles without memory scrubbing (MC1 and MCO both low), all four RAS outputs
go low, while all CAS outputs are driven high. Typical timing for this mode of operation is shown in Figure 6.
decoupling
D)
Due to the high switching speed and high drive capability of the' ALS6301 and' ALS6302, it is necessary
to decouple the device for proper operation. Multilayer ceramic O. 1-/tF to 1-/tF capacitors are recommended
for decoupling. It is important to mount the capacitors as close as possible to the power pins (VCC and
GND) to minimize lead inductance and noise. A ground plane is recommended.
CQ
CD
3
CD
,..:::s
.
""C
oQ.
c:
,..
(')
en
-
7-186
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ALS6301, SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage .............................................................. 7 V
Voltage applied to disabled 3-state output .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 70°C
Storage temperature range ......................................... - 65 °e to 150 °e
U)
~
CJ
::::J
"C
..
o
c..
recommended operating conditions
CI)
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
10H
IOL
High-level output current
tw
tsu
MIN
NOM
MAX
4.5
5
5.5
2
Low-level output current
Pulse duration
Setup time
10
(24) RASi high or RASI low
(25) LE high
(26) An before LE!
(27) SELn before LE!
10
(28) MeO.1 high before RASlt or RASI!
10
Hold time
TA
Operating free-air temperature
V
-2.6
V
rnA
C)
12
rnA
ca
ca
C
:E
.
>
0
ns
E
CI)
10
~
5
5
(29) SELn before RASI! or RASlt
(30) An after LE!
th
E
CI)
V
0.8
(23) RASI low or RASI high
UNIT
(ii
ns
....I
>
5
5
(31) SELn after LE!
ns
5
0
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VIK
Vee
VOH
Vee
VOL
Vee
Vee
10L t
Vee
10ZH
Vee
10ZL
II
Vee
Vee
IIH
Vee
IlL
Vee
10§
Vee
lee
Vee
= 4.5 V.
= 4.5 V.
= 4.5 V.
= 4.5 V.
= 4.5 V.
= 5.5 V.
= 5.5 V.
= 5.5 V.
= 5.5 V.
= 5.5 V.
= 5.5 V.
= 5.5 V
II
MIN
TVPt
=
-18 rnA
10H = -2.6 rnA
10L = 1 rnA
= 12 rnA
Vo = 2 V
Vo = 2.7 V
Vo = 0.4 V
VI = 7 V
VI = 2.7 V
VI = 0.4 V
Vo = 2.25 V
2.4
10L
MAX
UNIT
-1.2
V
3.2
-
V
0.15
0.5
0.35
0.8
V
rnA
30
20
-30
136
p.A
-20
p.A
0.1
rnA
20
p.A
-0.1
rnA
-112
rnA
220
rnA
t All typical values are at Vee = 5 V. T A = 25°e.
Not more than one output should be tested at a time. and duration should not exceed 1 second.
§ The output conditions have been chosen to produce a current that closely approximates one half the true short-circuit output current. lOS.
:1=
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-187
SN74ALS6301
DYNAMIC MEMORY CONTROLLERS
,ALS630 1 switching characteristics, CL
PARAMETER
<
r-
50 pF
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONSt
MIN
TYP*
MAX
UNIT
~
t ed(1)
RASI
Any Q
5
16
30
3:
CD
3
o
t ed(2i
RASI
RASn
2
10
14
ns
t ed(3)
t ed(4)
CASI
Any A
CASn
Any Q
2
7
14
ns
3
9
17
ns
t ed(5)
MSEL
Any Q
5
13
22
ns
t pd(6)
LEl
Any Q
13
22
ns
3:
tpd(7)
LEl
Any RAS
13
22
ns
Q)
:::s
t ed(8)
LEl
13
22
ns
Q)
t pd(9)
MCO or MC1
Any CAS
Any Q
6
14
24
ns
t pd(10)
MCO or MC1
Any RAS
2
10
15
ns
t ed(11)
MCO or MC1
Any CAS
VCC = 4.5 V to 5.5 V,
2
10
15
ns
t pd(12)
CS
Any Q
TA = ooC to 70°C
13
24
ns
t pd(13)
Any RAS
7
13
ns
o
t pd(14)
CS
CS
CAS
9
13
ns
t pd(15)
SELO or SEL 1
Any~
9
15
ns
n
....
en
t pd(16)
SELO or SEL1
Any
CAS
9
15
ns
t en (17)
OE!
Any Q
10
18
ns
t en (18)
em
Any'R'AS
10
18
ns
t en (19)
OE!
Any CAS
10
18
ns
-<
cc
CD
3
CD
....:::s
.
"'0
c.
c
-
Any
ns
tdis(201
OEl
Any Q
12
20
ns
tdis(21 )
OEl
Any RAS
12
20
ns
tdis(22)
O'El
Any
CAS
12
20
ns
MIN
TYP*
MAX
, ALS6301 switching characteristics, CL = 150 pF
FROM
(INPUT)
TO
(OUTPUT)
t ed(1 )
RASI
Any Q
10
20
35
ns
t pd(2)
RASI
RASn
3
9
18
ns
t pd(3)
CASI
2
7
18
ns
t pd(4)
t pd(5)
Any A
CASn
Any Q
5
11
18
ns
MSEL
Any Q
5
15
24
ns
t pd(6)
LEl
Any Q
13
24
ns
t pd(7)
LEl
Any RAS
13
24
ns
t ed(8)
LEl
13
24
ns
t pd(9)
MCO or MC1
Any CAS
Any Q
8
15
25
ns
t pd(10)
MCO or MC1
Any RAS
5
10
16
ns
t ed(11)
MCO or MC1
Any CAS
5
10
16
ns
t pd(12)
CS
Any Q
16
25
ns
t pd(13)
CS
Any RAS
9
15
ns
t pd(14)
CS
Any CAS
9
15
ns
tpd(15)
SELO or SEL 1
Any RAS
10
17
ns
t pd(16)
SELO or SEL 1
Any CAS
10
17
ns
PARAMETER
TEST CONDITIONst
VCC = 4.5 V to 5.5 V,
TA = ooC to 70°C
tSee Figures 10, 11, 12, and 13 for test circuit and switching waveforms.
*AII typical values are at VCC = 5 V, T A = 25°C.
7-188
TEXAS
l!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
UNIT
SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
, ALS6302 switching characteristics, CL
50 pF
FROM
TO
(INPUT)
(OUTPUT)
MIN
TYP+
MAX
t pd(1)
RASI
Any Q
5
16
30
ns
t pd(2)
RASI
RASn
2
10
14
ns
tp_di3J
t pd(4)
CAS I
CASn
Any Q
2
7
14
ns
Any A
3
9
17
ns
tpd(5)
MSEL
Any Q
5
13
22
ns
t pd(6}
LEt
Any Q
13
22
ns
t pd(7}
LEt
Any RAS
13
22
ns
t pd(8}
LEt
Any CAS
13
22
ns
!!tdi9J
MCO or MC1
Any Q
6
14
24
ns
t pd(10}
MCO or MC1
Any RAS
2
10
15
ns
t pd(11)
MCO or MC1
Any CAS
2
10
15
ns
t pd(12)
CS
Any Q
13
24
ns
t pd(13}
CS
Any RAS
7
13
ns
tpdL14}
CS
Any CAS
9
13
ns
t pd(15)
SELO or SEL 1
Any RAS
9
15
ns
t pd(16}
SELO or SEL 1
Any CAS
9
15
ns
ten (17}
OE!
Any Q
10
18
ns
t en t18}
GE!
Any RAS
10
18
ns
tent 19)
OE!
Any CAS
10
18
ns
tdis(20}
OEt
Any Q
12
20
ns
tdis(21 }
GEt
Any RAS
12
20
ns
tdis(22}
OEt
Any CAS
12
20
ns
MIN
TYP+
MAX
PARAMETER
, ALS6302 switching characteristics, CL
TEST CONDITIONSt
= 4.5 V to 5.5 V,
T A = ooC to 70°C
VCC
(.)
:::2
"C
...
0
0-
....C
Go)
E
Go)
C)
ca
C
ca
:2:
...0>-
E
Go)
:2:
Cii
-I
>
lUi
I
150 pF
FROM
TO
(INPUT)
(OUTPUT)
t pd(1}
RASI
Any Q
10
20
35
ns
t pd(2)
RASI
RASn
3
9
18
ns
t pd(3}
CASI
CASn
2
7
18
ns
t pd(4)
Any A
Any Q
5
11
18
ns
t pd(5)
MSEL
Any Q
5
15
24
ns
tpd(6}
LEt
Any Q
13
24
ns
tpd(7J
LEt
Any RAS
13
24
ns
ns
PARAMETER
....rn
UNIT
t pd(8}
LEt
Any CAS
t pd(9)
MCO or MC1
Any Q
t pd(1O)
MCO or MC1
t pd(11)
t pd(12)
t pd(13}
TEST CONDITIONst
= 4.5 V to 5.5 V,
= O°C to 70°C
UNIT
13
24
8
15
25
ns
Any RAS
5
10
16
ns
MCO or MC1
Any CAS
5
10
16
ns
CS
Any Q
16
25
ns
CS
Any RAS
9
15
ns
tpd(14)
CS
Any CAS
9
15
ns
t pd(15}
SELO or SEL 1
Any RAS
10
17
ns
t pd(16}
SELO or SEL 1
Any CAS
10
17
ns
VCC
TA
tSee Figures 10, 11, 12, and 13 for test circuit and switching waveforms.
+AII typical values are at VCC = 5 V, TA = 25°C.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-189
SN74ALS6301. SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
'--_ _ _ _ _ _ _
PR_o_c_ES_S_o_R_A_DD_R_E_SS_ _ _ _ _ _ _----J~\\\~DON·T
A INPUTS
<
r-
Q OUTPUTS
ROW ADDRESS VALID
(1)
MC INPUTS
3
o
-<
s:m
:::l
m
CD
RASI('ALS6301)
...o
-
I
t"'mm1/J'77~'TT0~DO~N':":'::·T!"'::C~A"!:":RE!"';~'77~'TT:mm1h'77";~
L..
I
MSEL
CASi
I
I
. If- tpd(5)~
i
i
t3 t
1
--.j
,
--tI
Ii
:
I
"n~"1~1-----------
Y
. \ . - t p dl31--.J
A
1
tsu(ACI t
-.I
1
CASI (' ALS6302)
CASn OUTPUT
4-1- - - - - - - -
I
I
('ALS6301)
~
en
~
~'----+-I
---+I
I
t p d(5)
It-Jf-- t2t ----+ll:,..-=------II------~
..
}~_ _~I~_ _ _ _ _- - I
I -
c.
c
n
....
I
__+I---+I-------~I~I-----------J I
I+-t1LJ. !
I I
(,----+1------If- t pd(2)---+i
I
t d(2) ~ I
~~~I----~I--------~I~I--------~~ p
~ I
RASI (' ALS6302) - - - - t
I
14-- thlAR)t
tsulAR) -.I!4T
RASn OUTPUT
3(1)
-g
I
_-+-___-I-_ _ _ _ _ _ _ _.j..~-l:I----------~_ t p d(9) t4READ/WRITE M01DE
X\.:I~-R-E-FR-E-S-H-M-O-DE---
(1)
....:::l
I
I
~
s:
ROW REFRESH ADD
COLUMN ADDRESS VALID
I
CARE_~
I
~
I+- t pd(3) ~
{
I
:
~~~~~ _______~t"z~f.~?~------------
I+--- t su (29)
SELINPUTS ::x.---------B-A-N-K-SE-L-EC-T---------~\\\~DON·T CARE ~\\\\\\\\~
FIGURE 4. READ/WRITE CYCLE TIMING (MC1, MCO
1, 0)' (LE - H)
t Parameters tsuIAR), tsuIAC), and thlARI are timing requirements of the dynamic RAM. Parameters t1, t2, and t3 represent the minimum
timing requirements at the inputs to the DMC that guarantee DRAM timing specifications and maximum system performance. The minimum
requirements for t1, t2, and t3 are as follows:
t1 (min)
t2lmin)
t3lmin)
= t p d(4) max + tsulAR) min - t p d(2) min
= t p d(2) max + thlAR) min - tpdlS) min
= t2 min + tpdlS) max + tsulAC) - t pd(3)
min
See the DRAM data sheet for applicable tsuIAR). tsuIAR), and thIAR)' In addition, note that propagation delay times given in the above
equations are functions of capacitive loading. The values used in these equations must relate to actual system capacitive loading.
7-190
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN74ALS6301, SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
Q OUTPUTS
CS
MC INPUTS
RASI ('ALS63011
RASI (' ALS6302)
_______
~~
__
COLUMN ADDRESS VALID
ROW ADDRESS VALID
--J~~~-----------J~~--------------'w:'----------
-----4----~~
__------4-+----------~---------
READ/WRITE MODE MC1.0 - HL
READWRIE MODE MC1.0 - HL
--~'----~~------T-T-------------~------------------~I----------
-------t--"--"\
y~-----t-I------
I
I
I\---+---'--+-------+--t------~ t p d(2)
-J
RASn OUTPUT
t su (26)-+I
It-
-+1
LE~~--~I--~I
I
I
th(30)
CASn OUTPUT
t SU (27)-.\
I
I
I.--+I
th(31)
...c
Cl)
E
Cl)
en
CO
c
CO
o
~I_~I------.j..1-------~)t
I
.
o
c..
1
~
I
r-------~L---
-----+-----j4-'"""":"'tp- d-(S-)::::;l---+------I4----'td(S)
L-I
--.:
p
I
I
1
..
I
~----~------1
I
I
-----...:.I---I~--'"T"------""""\I\0-...I - - - - - - (
1
I
J+- t p d(3) --+I
*-t p d(3)--+J
I
:::s
"C
:?!
k___tw_(r2S_)_~-T______~------~I~------~I----------~~
CASI ('ALS6302) _______
(.)
I \~~4-___________--------------~/~~
1
I
MSEL _______
CAS I ('ALS6301)
I
I+- t p d(2) ~
1I
_
______~--~1~~1~1----------~1~------~~~----~1-1--------t I I
!.- th(AR) t ~
- .
tsu(AR) -+1
I Jt-I
1
...en
:
tsu(AC) ---.,
I
I:
I4t-
\\\
~
tn:1I."~-----------
FIGURE 5. READ/WRITE CYCLE TIMING USING INPUT LATCHES (MC1, MCO = H, L)
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
~
en
....I
>
~;
I
t tsu(AR). tsu(AC). and th(AR) are timing requirements of the dynamic RAM. See the DRAM data sheet for applicable specifications.
TEXAS . .
E
Cl)
\'-____.....:...1_ _ _ _ _ _ _ _ _ _ _ _
SELINPUTS~~~~~~==~BA~NK~S~E~LE~CT~~~~~~~~~~~~D~DN~T~C~A~RE~~~~~~==~BA~N~K~SE~LE~CT~::=
INSTRUMENTS
~
7-191
I
SN74ALS6301, SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
<
Q OUTPUTS
~
~
-----'
ROW REFRESH AODRESS VALID
r~EXT
ROW REFRESH ADDRESS VALID
I
I
s:
CD
3
MCINPUTS __~,,~__
RE_FR_ES_H~M_0_DE__
M_Cl_.0_-_ LL
___________~________R_EF_R_ES_H_M_OD_E__
MC_l_.0_-_L_L__~,~_R_EA_D_/W_R_IT_E_MO_D_E__
o
-<
s:
!+- tpd( 1) 41
--r-------(
RASI ('ALS6301) - - - " " ' \ \.....
Q)
1
,.--41-----\
:::::I
Q)
cc
RASI ('ALS6302) ----,t-sU-(A.JR)t
3
RASn OUTPUT
CD
:::::I
.
~
LE
."
o
.
,,------""'\\
I
I+-- twIRL) t --+j
------~~"'~\\
i+-tw(RH)t
--.I
....- - - - - - - - - - - - -
I
1
Jill
~'Wo~~ _ _ _ _ _"JJlrjjJ
~f~~'iAF£_~?~:m~~(_
FIGURE 6. REFRESH CYCLE TIMING (MC1, MCO - L, L) WITHOUT SCRUBBING
Co
(')
1.-1
I
CD
c
-.I
\'-______..,,/
t tsu(AR). twIRL). and twlRH) are timing requirements of the dynamic RAM. See DRAM data sheet for applicable specifications.
~
-
til
7-192
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74ALS6301, SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
Q OUTPUTS
MCINPUTS
ROW REFRESH ADDRESS VALID
COLUMN REFRESH ADDRESS VALID
----~--tp-d-(9-)'~~~il'----------------J:IVI~-----------------J"~III~tp-d(J9)~
:::JK~------~I-----------RE-F-RE-S-H-M-O-DE--M~iC-11~O---L-H----------------~)(MI-------------------
~ t4 t t+- I
....u
U)
I I
I
...,1.-+:__________-'1-------+:----------------
:::s
.
"C
o
RASI (' ALS6301) ----""","'-__..
1 _______________
a.
I
1
I+- t p d)2) --+i 1
r-+I------------~I~I-------I
I I+-- th(AR) t ----.! I
~
\1
tsu(AR) t -+I
i+1
I I
1
1I
....c
I
RASI (' ALS6302) _ _ _ _ _
RASn OUTPUT
:
I ~
\\\\
~!4- tp d(5)
--~~"
I I
______~I------------~1
I4--t p d(5)
I_
MSEL
14----- t2 t
\~
E
CD
-+I
I:J)
CO
_____________________
C
CO
:iE
I
I
CASi (' ALS6301)
CD
M""'II..r~1- - - - - - -
l 1
1~-------!~~-------t3t ________~.~-+I----------~
k- t p d(3)-+/
--'1
CAS I (' ALS6302) ________________________
I
--+I
I
L1
I+- t p d(3)
_ tsu(AC) t
cAsnouTPuT*----____________________________________~~~
1
\\\
-+1
\ ________11----------------1
lid
FIGURE 7. REFRESH CYCLE TIMING (MC1, MCO = L, H) WITH MEMORY SCRUBBING
t Parameters tsu(AR), tsu(AC), and th(AR) are timing requirements of the dynamic RAM. Parameters t2, t3. and t4 represent the minimum
timing requirements at the inputs to the DMC that guarantee DRAM timing specifications and maximum system performance. The minimum
requirement for t2, t3, and t4 are as follows:
t2(min) = t p d(2) max + th(AR) min - t p d(5) min
t3(min) = t2 min + t p d(5) max + tsu(AC) - t p d(3) min
t4(min) = t p d(9) max + tsu(AR) min - t p d(2) min
-
See the DRAM data sheet for applicable tsu(AR), tsu(AC), and th(AR)' In addition, note that propagation delay times given in the above
equations are functions of capacitive loading. The values used in these equations must correspond to actual system capacitive loading.
+A CASn output is selected by the bank counter. All other CASn outputs will remain high.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-193
SN74ALS6301, SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
<
r5!!
t p d(9)
14I
1
Q OUTPUTS
s:
CD
3
o
-<
s:
MC INPUTS
::::s
Q)
(,Q
RASI (6301)
CD
::::s
r+
...o""C
c.
c
________
,'"-------',
I
)
I4-tw(24)~
3
CD
_
, _ ____________
CLR REFRESH MODE
MC1.0 - HH
, _
--_-_-_-_-_-_-_-_-_-_-_-_-~Xl~
~:~---------JX~-14-- t w (23) ~
Q)
I
RASI (6302)
I
--------------------..,;0;1
, ________________________
I
-+I
RASn OUTPUT
t p d(2)
t4-
1
' _ _ _..J
(")
r+
-
til
FIGURE 8, REFRESH COUNTER RESET (MC1. MCO = H. H)
7-194
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74ALS6301. SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
OE
A INPUTS
r
,
:
~ten(17)!4-
a
OUTPUTS
CS
: «(
--+t t pd(9) . . -
I
I
I
I
I
I
MC INPUTS
RASI (6301)
RASI (6302)
RASn OUTPUT
I
I
I
I
I
I
-+l t en(1S)(4I
I
I
I
I
I
LE
«<
MSEL
CASI (6301)
MC1.0 - L.H
:
14-
«<
BANK SELECT
I
I
I
tpd(15)~
~I+- II
+of
I+-
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~ t pd(6)
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IMC1.0 - HL
I
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I
(
I
I
t pd(12)-+I
I
: ?l+-
~pd(13)-+I
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I
14-
I
I
i
I
tpd(14)~
14-
I
I
X
I
*i
t pd(14)--+I
?t+-
SANK SELECT
I
I
tdis(21)~
:
X
tI
14-
~~
en....I
I
>
I
I
I
I tdis(22)~
i
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-.I tpd(S) I+-
X
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Q)
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I
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0
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I
t+-
~
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I
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,
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t pd(16)--.t
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tpd(11)~
C)
I
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tpd(11)~
SELINPUTS
}
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CASn OUTPUT
MC1.0 - HL
I
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I
CASI (6302)
I
-.Pen(19)i+-
I
l.
en
:
tdis(20)~
I+-
I
I
READ/WRITE MODE
I
I
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I
I
r4-
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I
I
~
t pd(12)-+I
.
I
I
t pd(10)-+i
I
I
XI
I
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I
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'
tpd(12)~
I
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X
I
tpd(10)~
I
¥
~ t p d(9)i+-
I
I
I
r-I
l+I
~
-
SANK SELECT
t+-
FIGURE 9. MISCELLANEOUS TIMING
TEXAS
"'I}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-195
I
SN74ALS6301. SN74ALS6302
DYNAMIC MEMORY CONTROLLERS
SWITCHING TEST CIRCUIT
<
r-
VCC
~
FROM
DEVICE
OUTPUT
3:
CD
3
-<
3:
6800
LZ.ZL
S
2
CL - 50 OF
o
D)
~
r 1
1
FROM
HZ, ZH
• tpd specified at CL = 50. 150 pF
::J
FIGURE 10. CAPACITIVE LOAD SWITCHING
D)
cc
FIGURE 11. THREE-STATE ENABLE/DISABLE
CD
3
CD
TYPICAL SWITCHING CHARACTERISTICS
::J
r+
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VOLTAGE WAVEFORMS
""I
C.
~--------3V
------__
c
n
r+
en
INPUT
r
4v
2.
R '" 250
I '------- I
tpLH~
OUTPUT
---e---VCC
~.5V
1.5VX
_ _ _ _ _ _....J
TYPICAL OUTPUT DRIVER
OV
tPHL~
~l
l
.
0----.
-VOL
OV
R '" 250
OUTPUT TO
RAM ADDRESS
OR CONTROL
LINES
---e---GND
FIGURE 12. OUTPUT DRIVE LEVELS
THREE-STATE TIMING
3.STATE
~---------------~
..JI.
CONT~~~ _ _ _ _ _
~
141114f----I~""1-
_ _ _ _ _--:.I_ _~ 1
VOH
OUTPUT
I
:
tpHZ
(DISABLE)
~ VOH
- 0.5 V
I
: t
---V-O-L--""'II--....JI
tpZH
(ENABLE)
(HIGH IMPEDANCE)
VOL
+
tpLZ
0.5 V
)~4r---....,~MI-(DISABLE)
-
-
-
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
-
-
-
-
- 3 V
V
VOH
2.4 V
1--------
:
I
:
' \-
FIGURE 13. THREE-STATE CONTROL LEVELS
TEXAS . .
-
:
tpZL
I :
(ENABLE) 14
~I
INSTRUMENTS
-
14
~I
I :
NOTE: Decoupling is needed for all AC tests
7-196
-
- - - - - -- - - - --~.~
-
-
-
- -
- -
-
0.8 V
VOL
THCT4502B
DYNAMIC RAM CONTROLLER
D2989. JUNE 1987
CIt
o
JD OR N PACKAGE
Inputs are TTL- and CMOS-Voltage
Compatible
(TOP VIEW)
Controls Operation of 64K and 256K
Dynamic RAMs
o
Creates Static RAM Appearance
•
One Package Contains Address Multiplexer,
Refresh Control, and Timing Control
o
Directly Addresses and Drives Up to 2
Megabytes of Memory Without External
Drivers
o
o
o
Operates from Microprocessor Clock
No Crystals, Delay Lines, or RC
Networks
Eliminates Arbitration Delays
Refresh May Be Internally or Externally
Initiated
Versatile
Strap-Selected Refresh Rate
Synchronous, Predictable Refresh
Selection of Distributed, Transparent,
and Cycle-Steal Refresh Modes
Interfaces Easily to Popular
Microprocessors
Asynchronous RESET Function Provided
in FK and FN Packages
o
High-Performance Si-Gate CMOS
Technology
o
Strap-Selected Wait State Generation for
Microprocessor/Memory Speed Matching
o
Ability to Synchronize or Interleave
Controller with the Microprocessor System
(Including Multiple Controllers)
3-State Outputs Allow Multiport Memory
Configuration
o
Performance Range:
11 5 ns ALE low to CAS low
o
Functionally Equivalent to TMS4500A/B and
to VTI VL4500A and VL4502
o
Available in Plastic and Ceramic Chip
Carriers in Addition to Plastic and Ceramic
DIPs
CJ
:::J
"'C
.
o
cs
CL
RENO
RDY
ClK
RAS3
RAS2
CASl
GND
RENl
9
11
....,
c:
CD
E
CD
C)
CO
c:
CO
VCC
MA8
CA8
RA8
REFREQ
TWST
FSO
FSl
RA7
CA7
MA7
~
~
o
E
CD
~
Ui
...I
>
-
FK OR FN PACKAGE
(TOP VIEW)
98765432
1 68 67 666564 636261
NC JlO
NC J11
CAl 12
RAl 13
RA2 14
CA2 15
MA2 16
GND 17
GND 18
MA3 19
CA3 20
RA3 21
MA4 22
CA4 23
RA4 24
NC 25
NC 26
o
o
MAO
MAl
CAl
RAl
RA2
CA2
MA2
GND
MA3
CA3
RA3
MA4
CA4
RA4
MA5
CA5
RA5
RA6
CA6
MA6
VI
....,
ACR
RASl
RASO
ALE
ACW
CASO
60~ NC
59~ NC
58~ ClK
57[ RAS3
56[ RAS2
5S[ CASl
54[ GND
53[ RENl
52[ VCC
VCC
MA8
49 CA8
48 RA8
47
RESET
46 REFREQ
4S[ NC
44[ NC
51
50
2728293031323234353637383940414243
uu~~~~~~o~~~~o~uu
zz~~~~~~z~~~~~~zz
~ua::a::U~(:J~ua::u.u.~
~
NC - No internal connection
Dependable Texas Instruments Quality and
Reliability
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~~~~i~a{~~I~lJ~ ~!~~~~ti~r fl\o::~:~~t:ros~s not
Copyright © 1987. Texas Instruments Incorporated
TEXAS
J.q,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-197
I
THCT45028
DYNAMIC RAM CONTROLLER
description
The THCT4502B is a monolithic DRAM system controller providing address multiplexing, timing, control
and refresh/access arbitration functions to simplify the interface of dynamic RAMs to microprocessor
systems.
<
r-
!!!
s:
3
The controller contains an 18-bit multiplexer that generates the address lines for the memory device from
the 18 system address bits and provides the strobe signals required by the memory to decode the address.
A 9-bit refresh counter generates up to 512 row addresses required to refresh.
-<
A refresh timer is provided to generate the necessary timing to refresh the dynamic memories and ensure
data retention.
m
::l
The THCT4502B also contains refresh/access arbitration circuitry to resolve conflicts between access
requests and memory-refresh cycles.
CD
The THCT4502B is characterized for operation from O°C to 70°C.
CD
o
s:
m
CQ
3
CD
....
::l
functional block diagram
."
RAO
a
Co
RAl
RA2
c
n
....
RAJ
RA4
o
RA5
RA6
RA7
RAB
(3)
(B)
(9)
<:J
(15)
ROW
(lB)
ADDRESS
\
(21)
LATCH
v
(22)
<:J
CAl
CA2
CA3
CA4
CAS
CA6
CA7
CAB
ALE
cs
RENO
RENl
Acii
AcW
(13)
(32)
FSl
CLK
MULTI. <:J
PLEXER
<:J
(7)
<:J
(14)
(16)
(19)
(20)
,
(26)
REFRESH:
COUNTER
(33)
J--
(45)
1=L
SELECT
(43)
I
(36)
<:J
v
(23)
(44)
(24)
f\
COLUMN
ADDRESS
LATCH
(17)
<:J
~
<:J
MA3
MA4
MAS
I
<:J
<:J
(4B)
(1)
'V
~ .,,,'" f=:=
1 1 --+--
(30)
(29)
(2B)
r-
(41)
REFRESH
RATE
GENER·
ATOR
t
1
(25)
(34)
MA6
MA7
MAB
~ll
l
LATCH
RESET (FK and FN packages only I
TIMING
(46)
mO
(47)
(39)
(40)
AND <:J
CONTROL
<:J
-
r
'V
(2)
t
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
CASO
(38)
(42)
Pin numbers shown are for JD and N packages.
7-198
MA2
(10)
1
FSO
MAl
(4)
(31)
TWST
(6)
(11)
MAO
(27)
~
CAO
<:J
(5)
ROY
THCT4502B
DYNAMIC RAM CONTROLLER
pin descriptions
RAO-RA8
Input
Row Address - These address inputs are used to generate the row address
for the multiplexer.
....en
CAO-CA8
Input
Column Address - These address inputs are used to generate the column
address for the multiplexer.
"C
MAO-MAS
Output
Memory Address - These three-state outputs are designed to drive the
addresses of the dynamic RAM array.
....C
ALE
Input
Address latch Enable - This input is used to latch the 18 address inputs,
CS, RENO, and REN 1. This also initiates an access cycle if CS is low. The
rising edge (low level to high level) of ALE returns all RAS outputs to the
high level.
(.)
::s
..
o
a..
CI)
RENO, REN1
Input
Chip Select - A low on this input enables an access cycle. The trailing
edge of ALE latches the chip select input.
Inputs
RAS Enable 0 and 1 - These inputs are used to select one of four banks
of RAM when CS is low. When REN1 is low, the lower banks are enabled
via CASO, RASO, and RAS 1. When REN 1 is high, the higher banks are
enabled via CAS 1, RAS2 and RAS3. RENO selects RASO and RAS2 when
low, or RAS1 and RAS3 when high. (see Table 2).
Input
Access Control, Read; Access Control, Write - A low on either of these
inputs causes the column address to appear on MAO-MA8 and a 10W-gOing _
pulse from CAS. The rising edge of ACR or ACW terminates the cycle by
forcing RAS and CAS high. When ACR and ACW are both low, MAO-MA8,
RASO, RAS 1, RAS2, RAS3, CASO and CAS 1 go into a high-impedance
(floating) state.
Input
System Clock - This input provides the master timing to generate refresh
cycle timings and refresh rate. Refresh rate is determined by the TWST,
FS 1, and FSO inputs.
1/0
Refresh Request - This input should be driven by an open-collector or opendrain output. On input, a low-going edge initiates a refresh cycle and will
cause the internal refresh timer to be reset on the next falling edge of the
ClK. As an output, a low-going edge signals an internal refresh request
and that the refresh timer will be reset on the next low-going edge of ClK.
REFREQ will remain low until the refresh cycle is in progress and
the current refresh address is present on MAO-MA8. (Note: REFREQ
contains an internal active pullup with a nominal resistance of 10 kn, which
is disabled when REFREQ is low).
RASO, RAS1
RAS2, RAS3
Output
Row Address Strobe - These three-state outputs are used to latch the
row address into the bank of DRAMs selected by RENO and REN1. On
refresh, all RAS signals are active.
CASO,CAS1
Output
Column Address Strobe - These three-state outputs are used to latch the
column address into the DRAM array.
RDY
Output
Ready - This totem-pole output synchronizes memories that are too slow
to guarantee microprocessor access time requirements. This output is also
used to inhibit access cycles during refresh when in cycle-steal mode.
ClK
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
7-199
E
CI)
C)
ca
c
ca
~
en...I
>
THCT4502B
DYNAMIC RAM CONTROLLER
pin descriptions (continued)
TWST
Input
Timing/Wait Strap - A high on this input indicates a wait state should be
added to each memory cycle. In addition it is used in conjunction with FSO
and FS 1 to determine refresh rate and timing or initialize the controller.
3:
FSO, FS1
Inputs
Frequency Select 0; Frequency Select 1 - These are strap inputs to select
Mode and Frequency of operation as shown in Table 1.
3
o
RESETt
Input
RESET - Active-low input to initialize the controller asynchronously.
Refresh Address is set to IFF16, internal refresh requests, synchronizer,
and frequency divider are cleared. (Note: RESET contains an internal pullup
resistor with a nominal resistance of 100 k!l, which allows this pin to be
left open.)
<
r~
CD
-<
3:
m
~
m
cc
CD
tThis function is available only in the FK and FN packages.
3
TABLE 1. STRAP CONFIGURATION
CD
~
r+
WAIT
...
o
"0
STRAP INPUT MODES
Co
c
STATES
MINIMUM
FOR
MEMORY
CLOCK
REFRESH
ACCESS
RATE
0
CLOCK
FREQUENCY
(MHz)
REFRESH
FREQUENCY
(kHz)
CYCLES
FOR EACH
EXTERNAL
-
REFREQ
4
-
REFREQ
3
3.904
4
3
()
TWST
FS1
o
L
l
FSO
l t
l
l
H
0
l
H
l
0
EXTERNAL
ClK .;- 61
l
H
H
0
ClK .;-
91
5.824
64-95:1:
64-88§
H
l
l
1
ClK .;-
H
l
H
1
ClK .;-
H
H
l
H
H
H
r+
REFRESH
3
61
3.904
64-95:1:
5.824
64-75:1:
4
1
91
ClK.;- 106
6.784
64-73:1:
4
1
ClK.;- 121
7.744
64-83'
4
t This strap configuration resets the Refresh Timer Circuitry.
:I: Upper figure in refresh frequency is the frequency that is produced if the minimum clock frequency of the next select state is used.
§ Refresh frequency if clock frequency is 8 MHz.
, Refresh frequency if clock frequency is 10 MHz.
TABLE 2. OUTPUT STROBE SELECTION
CONTROL INPUT
SELECTED OUTPUT
REN1
l
RENO
RASe
l
X
l
H
H
l
H
H
RAS1
RAS2
RAS3
CASO
CAS 1
X
X
X
X
X
X
NOTE: Changing the logic value of REN1 after a low-to-high transition of ALE and before
~. signals remain low until ACX rises.
X
ACX rises causes the other 'C'AS to fall. Both
functional description
The THCT45028 consists of six basic blocks: address and select latches, refresh rate generator, refresh
counter, the multiplexer, the arbiter, and the timing and control block.
7-200
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
THCT45028
DYNAMIC RAM CONTROLLER
address and select latches
The address and select latches allow the DRAM controller to be used in systems that multiplex address
and data on the same lines without external latches. The row address latches are transparent, meaning
that while ALE is high, the output at MAO-MAS follows the inputs RAO-RAS.
....en
(,)
:::s
"C
refresh rate generator
The refresh rate generator is a counter that indicates to the arbiter that it is time for a refresh cycle. The
counter divides the clock frequency according to the configuration straps as shown in Table 1. The counter
is reset when a refresh cycle is requested or when TWST, FS1, and FSO are low. The configuration straps
allow the matching of memories to the system access time. Upon power-up it is necessary to provide
a reset signal by driving all three straps to the controller (or RESET for devices in the FK and FN packages
only) low. A systems power-on reset (RESET) can be used to do this by connecting it to those straps
that are desired high during operation. During this reset period, at least four clock cycles should occur.
e
c..
....c:
CD
E
CD
C')
ca
c:
ca
~
refresh counter
The refresh counter contains the address of the row to be refreshed. The counter is decremented after
each refresh cycle. A low-to-high transition on TWST sets the refresh counter to 1 FF16 (51110).
multiplexer
The multiplexer provides the DRAM array with row, column, and refresh addresses at the proper times.
Its inputs are the address latches and the refresh counter. The outputs provide up to 1S multiplexed
addresses on nine lines.
arbiter
The arbiter provides two operational cycles: access and refresh. The arbiter resolves conflicts between
cycle requests and cycles in execution, and schedules the inhibited cycle when used in cycle-steal mode.
timing and control block
The timing and control block executes the operational cycle at the request of the arbiter. It provides the
DRAM array with RAS and CAS signals. It provides the CPU with a ROY signal. It controls the multiplexer
during all cycles. It resets the refresh rate generator and decrements the refresh counter during refresh
cycles.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
Supply voltage range, VCC (See Note 1) ................................ -1.5 V to 7 V
Input diode current, 11K (VI < 0, VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output diode current, 10K (Vo < 0, Vo > Vcc) ............................... ±20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±35 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: FK or JD package . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FN or N package. . . . . . .. 260°C
t Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only,
and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions"
section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values are with respect to network ground.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-201
THCT4502B
DYNAMIC RAM CONTROLLER
recommended operating conditions
<
r-
MIN
NOM
MAX
4.5
5
5.5
VCC
Supply voltage
VIH
High-level input voltage
2
VIL
Low-level input voltage
-0.5 t
Vo
Output voltage
CD
tt
Input transition (rise and fall) time
0
o
TA
Operating free-air temperature
0
~
s:
3
--o
tROl-Cl
Time delay, REFREO low to ClK starting low (see Note 8)
35
ns
Q)
twJHOU
Pulse width REFREO low
30
ns
~
tw(ACl)
ACX low width (see Note 9)
120
ns
treset
Power-up reset
4tcCLK
ns
Cii
-I
NOTES:
2
E
1. Coincidence of the trailing edge of ClK and the trailing edge of ALE should be avoided as the refresh/access occurs on tho
trailing ClK edge.
2. If ALE rises before ACX and a refresh request is present, the falling edge of ClK after tCl-AEH will output the refresh address
to MAO-MA 7 and initiate a refresh cycle.
3. These specifications relate to system timing and do not directly reflect device performance.
4. On the access grant cycle following refresh, the occurrence of CAS low depends on the relative occurrence of ALE low to
ACX low. If ACX occurs prior to or coincident with ALE, then CAS is timed from the ClK high transition that causes RAS
low. If ACX occurs 20 ns or more after ALE, then CAS is timed from the ClK low transition following the ClK hightransition
causing RAS low.
5. For maximum speed access (internal delays on both access and access grant cycles), ACX should occur prior to or coincident
with ALE.
6. th(RA) is the dynamic memory row address hold time. ACX should follow ALE by tAEl-CEl in systems where the required
th(RA) is greater than tREL-MAX minimum.
7. The minimum of 30 ns is specified to ensure arbitration will occur on falling ClK edge, tACH-Cl also affects precharge time
such that the minimum tACH-Cl should be equal or greater than: tw(RH) - tw(Cl) + 30 ns (for a cycle where ACX high
occurs prior to ALE high) where tw(RH) is the DRAM RAS precharge time.
8. This parameter is necessary only if refresh arbitration is to occur on this low-going ClK edge (in systems where refresh is
synchronized to external events).
9. The specification tw(ACl) is designed to allow a CAS pulse. This assures normal operation of the device in testing and system
operation.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-203
>
THCT4502B
DYNAMIC RAM CONTROLLER
switching characteristics over recommended supply voltage range and operating free-air temperature
range (see Figure 1)
<:
r-
~
3:
CD
3
o
-<
PARAMETER
tAEL-REL
TEST CONDITIONS
THCT4502B-115
MIN
Time delay, ALE low to RAS starting low
Cl = 180 pF
35
ns
Cl = 360 pF
42
ns
Cl = 360 pF
60
ns
CL = 40 pF
33
ns
115
ns
35
ns
Time delay, ALE to ROY starting low (TWST = 1
tAEl-RYL
or refresh in progress)
tAEL-CEL
Time delay, ALE loW to CAS starting low (see Note 10)
CL = 360 pF
tAEH-REH
Time delay, ALE high to RAS starting high
Cl = 180 pF
C»
tACl-MAX
Row address valid after ACX
Cl = 360 pF
10
CD
tMAV-CEL
Time delay, memory address valid to
Cl = 360 pF
0
3
tACL-CEL
Time delay, ACX low to CAS starting low (see Note 10)
Cl = 360 pF
25
tACH-REH
Time delay,
tACH-CEH
Time delay, ACX high to
cc
CD
::::s
.o
r+
."
Co
c:
a
rn
-
UNIT
tRAV-MAV Time delay, row address valid to memory address valid
tAEH-MAV Time delay, ALE high to valid memory address
3:
C»
::::s
MAX
ACX to 'R'AS
CAS starting low
starting high
CAS starting
after ACX high
Cl = 180 pF
high
tACH-MAX Column address valid
Time delay, ClK high to ROY starting high
tCH-RYH
(after ACX low) (see Note 11)
Time delay, REFREQ external till supported by
tRFL-RFL
50
REFREQ internal
CL = 360 pF
5
Cl = 360 pF
5
ns
ns
80
ns
40
ns
30
ns
ns
Cl = 40 pF
42
ns
Cl = 40 pF
35
ns
tCH-RFL
Time delay, ClK high till REFREQ internal starting low
CL = 40 pF
50
ns
tCL-MAV
Time delay, ClK low till refresh address valid
CL = 360 pF
70
ns
tCH-RRL
Time delay, ClK high till refresh RAS starting low
CL = 180 pF
5
50
ns
tMAV-RRl
Time delay, refresh address valid till refresh RAS low
Cl = 180 pF
5
Time delay, ClK low to REFREQ starting high
tCL-RFH
(3 cycle refresh)
Time delay, ClK high to REFREQ starting high
tCH-RFH
(4 cycle refresh)
Cl = 40 pF
50
ns
CL = 40 pF
50
ns
30
ns
tCH-RRH
Time delay, ClK high to refresh RAS starting high
Cl = 180 pF
5
tCH-MAX
Refresh address valid after ClK high
Cl = 360 pF
10
NOTES:
7-204
ns
ns
10. The falling edge of CAS occurs when both ALE low to CAS low time delay (tAEL-CEl) and ACX low to CAS low time delay
(tACl-CEl) have elapsed, i.e., if ACX goes low prior to (tAEL-CEL - tACl-CEl) after the falling edge of ALE, the falling edge
of CAS is measured from the falling edge of ALE (tAEL-CELI. Otherwise, the access time increases and the falling edge of
CAS is measured from the falling edge of ACX (tACl-CEll.
11. ROY returns high on the rising edge of ClK. If TWST = 0, then on an access grant cycle ROY goes high on the same edge
that causes access RAS low. If TWST = 1, then ROY goes to the high level on the first rising ClK edge after ACX goes low
on access cycles and on the next rising edge after the edge that causes access RAS low on access grant cycles (assuming
ACX low).
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
THCT4502B
DYNAMIC RAM CONTROLLER
switching characteristics over recommended supply voltage range and operating free-air temperature
range (see Figure 1) (continued)
TEST CONDITIONS
PARAMETER
tCH-REl
Time delay, ClK high till access RAS starting low
Time delay, ClK low to access
tCl-CEl
CAS
starting low
(see Note 12)
THCT4502B·115
MIN
MAX
:::s
ns
"C
Cl = 360 pF
70
ns
CL.
C
Cl = 360 pF
15
ns
tREL-MAX
Row address valid after RAS low
Cl = 360 pF
20
ns
tAEH-MAX
Column address valid after ALE high
Cl = 360 pF
10
ns
tdis
Output disable time (3-state outputs)
Cl = 360 pF
90
ns
ten
Output enable time (3-state outputs)
Cl = 360 pF
55
ns
Cl = 360 pF
CAS starting low after refresh (see Note 12)
Time delay, ClK high to access CAS starting low
tCH-CEl
(see Note 13)
..
45
Row address valid after ClK low
Time delay, column address valid to
CJ
Cl = 180 pF
tCl-MAX
tCAV-CEl
(I)
.....
UNIT
Cl = 360 pF
o
.....
Q)
E
Q)
en
CO
c
CO
:E
ns
0
140
ns
tt(CEl)
CAS fall time
Cl = 360 pF
20
ns
tt(CEH)
CAS rise time
Cl = 360 pF
30
ns
tt(REl)
RAS fall time
Cl = 180 pF
20
ns
tt(REH)
RAS rise time
Cl = 180 pF
30
ns
tt(MAV)
Address transition time
Cl = 360 pF
30
ns
tt(RYU
RDY fall time
Cl = 40 pF
20
ns
tt(RYH)
RDY rise time
Cl = 40 pF
27
ns
NOTES: 12. The occurrence of CAS low is guaranteed not to occur until the column address is valid on MAX.
13. On the access grant cycle following refresh, the occurrence of CAS low depends on the relative occurrence of ALE low to
ACX low. If ACX occurs prior to or coincident with ALE then CAS is timed from the ClK high transition that causes RAS low.
If ACX occurs 20 ns or more after ALE then CAS is timed from the ClK low transition following the ClK high transition
causing RAS low. (See Refresh Cycle Timing Diagram)
..
PARAMETER MEASUREMENT INFORMATION
OUTPUT~
UNDER TEST
1
r
Cl
FIGURE 1. LOAD CIRCUIT
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-205
THCT4502B
DYNAMIC RAM CONTROLLER
I
CLK
<
r-
r-----~~~~190%
1.3 V
tCL-AEL~
~
3V
~lli~~10!!%~
I
I _ _ _oJ
I
~t~(CL):::t ~ tt
I
~) t
t+-tol- tAEL-CL
L.
i+-tw(AEH)---.i
s:
\1.3
I·
I
ALE
CD
3
o
.
-<
RENO,REN1,
ROW,COL,CS
s:
-1.1.3 V
---'l
I
tAV-AEL
~
I
1
f.3V
I
I
_I_ -I
tAEL-AX
I
D)
(Q
1
1
~
I
3
I
CD
1
--l ' \4- tt(REL)
1
--+----~----r----=~II
1
1
~03%V 110 %
::;,
r+
..."'C
~
tRAV-MAVI4
I
I'
I
I
r+--tAEH-MAV~
o
Co
c
'--_ _ _ 0 V
I
I
1
I
I
~ ---t
:
I
10"..
19~~
~ tACH-MAX
'~~~mVOH
~
VOL
MAO-MAS
(")
r+
f/)
I
I~ I r-tt(CEL)
I
I+-tREL-MAX----.j
1
1
;°3. V
tAEL-RYL~
VOH
~tCH-RYH
: 90%~i~;:
1
I...r,,.,,.,,,.------
10%
t---tACL_CEL--+--!~~---------:.=...:.::..;r.:
1
ROY
VOH
~r----------- VOL
tt-tAEH-~AX,
\+---.l-tACL-MAX
90%
OV
I4- t t(REH)
14- tAEH-REH +.IZ::=------------
1
I
1
1TTT'TTT.777l'7TI7777T7'TT7"."'-- 3 V
1 . 3V_
t~CH-RE~ :
I
I
1
1
t4-tACH-CL...I
1
I
1
I
3V
~OV
.-----3V
r-tAEL-ACL---+t.-tACL_CH-----l
1~'.3V
CD
I
I
1
I~
'
1.3V
\
I
1
I
'1
~I'~
D)
::;,
.J tCL-AEH
~r-------------:-----'
V
..-I I4-
t
,~%r:_-~9~0~~_----------------------------------------- ~::
I~
t(RYL)
\4-tt(RYH)
...
1-f--------tAEL-CEL------~.1
NOTE 14: All transition times (tt) are measured between 10% and 90% points.
FIGURE 2. ACCESS CYCLE TIMING
CLK--.-i
\1.3V
I
I
I
tRQL.CL ..
!4t----.t·1
OV
I
tw(RQL) 1111
REFREQ
tCH-RFL-1~Ie----1~'11
1.3 V
(EXTERNAL)
----::
1
I
REFREQ
\
1.3Vf
\
.1
'1~~-----
I+--tRFL-RFL~
(INTERNAL)
VOH
VOL
FIGURE 3. REFRESH REQUEST TIMING
NOTE 15: All input pulses are supplied by generators having the following characteristics: PRR :5 1 MHz, Zout
7-206
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
= 50 n, tr = 6 ns, tf = 6 ns.
THCT4502B
DYNAMIC RAM CONTROLLER
~.
i\~1._3_V
ACR·ACW
...Jt~3~ __________ 0v
3V
__________
I
If-- ten ----+I
I
:::l
I
-
"C
...o
'Vee
'\~.------+-:_____-b -----
I
I
I
(See Note 151
(J
~ tdis----+j
~"
I
OUTPUT
WAVEFORM 1
rn
+"
I
c..
VOL
+"
C
tt-- ten---.l
OUTPUT
__
WAVEFORM 2
(See Note 151
CI)
E
CI)
I
1
-J/
tn
CO
C
CO
~
VOLTAGE WAVEFORMS
~
NOTE 16: Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the access controls.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the access controls.
o
FIGURE 4. ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
CI)
CLK \
ALE
t
oJ
)10.1_ _ _
l
I
~I
_ _ _oJ
~I---I----------------~--------~I~-----------
:
\
t
it\ :
r
I
:
==x:
:
¥
I
REFRESH ADDRESS
H-tCH.RRL
I
1
r-+tCL-MAY
RAS
:
tCL.RFH~
I
1
:
k
tCH-MAX
j.--.J-tCL.MAX
X. .----: \\.____!~---__~!~---~
D~D-R-E-S-S---~-
X\._______
R_O_W_A
__
H-tCH.RRH
tCH·REL
1
"1\\.__________________. .
~tMAV.RRL~
..
>
1
ACX ----~--------~------_T--~~--~
MAO·MA7
~
en..J
\
f,
!;"---'"'!""'\.\
i
1
E
H
:
...
tCAy.CEL~
tCL.CELt ...........- -..
j..-- tCH·CEL t
lL
t On access grant cycle following refreSh, CAS low and address multiplexing are timed from ClK high transition (tCH.CEll if ACX low
occurs prior to or coincident with the falling edge of ALE.
t On access grant cycle following refresh, CAS low and address multiplexing are timed from ClK low transition (tCl.CEll if ACX low occurs
20 ns or more after the falling edge of ALE.
FIGURE 5. REFRESH CYCLE TIMING (THREE CYCLE)
NOTE 15: All input pulses are supplied by generators having the following characteristics: PRR
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
::s
1 MHz, Zout = 50 fl, tr = 6 ns, tf = 6 ns.
7-207
THCT4502B
DYNAMIC RAM CONTROLLER
ClK
-";"'_ _JI
I
<
r-
~ _ _ _~IJ~~____~____________~______________~______~________
ALE
__
~
'\~t~~~*_\~~~________~__________~____~~______
s:
ACX
3
o
REFREQ __
tCH-RFH~ r---------~--------------~----~~-------
CD
~__~__~________________~~
-<
tCH-MAX
tcl-MAV
s:
REFRESH ADDRESS
MAO-MA7
L»
~
~tcH-RRl
L»
co
RAS
CD
-----~I~----:L
I
--------------or
1414-----.~1t-
3
I
I
I
I
tMAV -R R l
CD
~
.o
~
tCl-CEl t
~
~
CAS
""C
Co
c:
..
aen
t On access grant cycle following refresh, CAS low and address multiplexing are timed from ClK high transition (tCH-CEl) if ACX low
occurs prior to or coincident with the falling edge of ALE.
t On access grant cycle following refresh, CAS low and address multiplexing are timed from ClK low transition (tCl-CELl if ACX low occurs
20 ns or more after the falling edge of ALE.
NOTE 15: All input pulses are supplied by generators having the following characteristics: PRR ::5 1 MHz, Zout = 50 n, tr = 6 ns, tf = 6 ns .
FIGURE 6. REFRESH CYCLE TIMING (FOUR CYCLE)
I
ACCESS
2
I
3
I
REFRESH/ACCESS GRANT
I w, I
W2
I
2
3
I
ACCESS
I
2
I
3
ClK
AlEY\1
I
ACX
(ACR or ACW)
""'":-I----J
I
MAX
ROY
FIGURE 7. TYPICAL ACCESS/REFRESH/ACCESS CYCLE (THREE-CYCLE, TWST IS LOW)
7-208
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2
I
THCT4502B
DYNAMIC RAM CONTROLLER
I
ACCESS
1
I
4
I
REFRESH/ACCESS GRANT
I
1
I
W1
I
W2
I
W3
I
2
I
I
3
4
1
I
2
I
....tnCJ
ClK
ALE
h
I
I
I
I
ACX
(ACR or ACWI
I
I8
MAX
I
I
w
iiEFi'iEQ
ROY
I
I
I
I
--RE-FR-ES':""'H
I
I
I
I
I
I i \!
I
I
I
I
I
COLUMN
I
I
! II
i
I
I
I
I
I
I _._______/1
I
I
I
I
\1
I
REFRESH/ACCESS GRANT
1
ALE
MAX
REFREQ
ROY
I
W3
I
2
3
I,
I
w,
C)
CO
C
CO
I
~
'+
I
I
I
~
o
E
CD
~
en
....I
>
..
I
Y.\,~I_______I~h-.:.-I---:------~____:_____'
1m
I
II~~----i-------':----""""'"
I
I
COLUMN
I
CAS
W2
CD
E
CD
I
_AC~ hi'.
(ACR or ACWI
, I W1 I
....C
~
FIGURE 8. TYPICAL ACCESS/REFRESH/ACCESS CYCLE (FOUR-CYCLE. TWST IS LOW)
ClK
...o
c.
I
-:--~
COLUMN
i \!
I
lr\~1
I ~
I I
~------'-~------'----~I
1\\\\\\\\\\\\\
I
~
"C
I
i\!
I
! Ii
I \\%t~
~
I
COLUMNI
I
I
\J,--I- - : ' - - - - - J
FIGURE 9. TYPICAL ACCESS/REFRESH/ACCESS CYCLE (THREE-CYCLE. TWST IS HIGH)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-209
THCT4502B
DYNAMIC RAM CONTROLLER
I'
<
r-
ACCESS
I w,
2
I
REFRESH/ACCESS GRANT
I , I
4
3
w,
CLK
!:!!
ALEhl
3:
3
o
<
3:
D)
MAX
::::s
D)
CQ
C'D
3
"AS
C'D
::::s
....
.
CAS
"'tJ
o
c.
c
REFREQ
fA
ROY
..
....
C")
I y-
"'I
COLUMN
REFRESH
'»\\\\\\)\~
I\L.lI
COLUMN
I
,~ ~
\'\,
~
~I~I
I
\l~_I_----J/1
I
FIGURE 10. TYPICAL ACCESS/REFRESH/ACCESS CYCLE (FOUR-CYCLE. TWST IS HIGH)
TYPICAL CHARACTERISTICS
ICC vs CLOCK FREQUENCY
TMS4500A ... FN PACKAGE
(TOP VIEW)
o Strap-Selected Wait-State Generation for
Microprocessor/Memory Speed Matching
o
o
o
z>-~
w
Ability to Synchronize or Interleave
Controller with the Microprocessor System
(including Multiple Controllers)
3-State Outputs Allow Multiport Memory
Configuration
u~tno~
1°
-' IUl lJ.J Cl -' U U LJ.J ~ Ul Ul
«ua:a:uz>a:f-lJ..lJ..
6
RASO
RASl
ACR
ACW
Performance Ranges of 150 ns. 200 ns. or
250 ns
5
4
3 2
1 4443424140
39
38
37
10
36
11
35
12
34
13
33
14
32
RA7
CA7
MA7
MA6
description
The TMS4500A is a monolithic DRAM system
controller designed to provide address multiplexing. timing. control and refresh/access
arbitration functions to simplify the interface of
dynamic RAMs to microprocessor systems.
~NNNClClC"lC"lC"l
I
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
7-213
TMS4500A
DYNAMIC·RAM CONTROLLER
TABLE 1. STRAP CONFIGURATION
WAIT
<
r-
STRAP INPUT MODES
(I)
3
o
-<
s:
::J
(I)
FOR EACH
MEMORY
REFRESH
ClK FREQ.
REFRESH
FOR EACH
TWST
FS1
FSO
ACCESS
RATE
(MHz)
FREQ. (kHz)
REFRESH
l
l
l
l
l
l
lt
a
a
a
a
EXTERNAL
-
REFREQ
ClK+31
ClK+46
ClK+61
ClK+46
ClK+61
ClK+76
ClK+91
1.984
2.944
3.904
2.944
3.904
4.864
5.824
64-95 t
4
3
3
4
3
4
4
4
H
H
l
H
H
l
H
l
l
H
H
H
l
H
H
H
H
=
=
cc
MINIMUM
FOR
~
s:
CLOCK
STATES
1
1
1
1
64-85 t
64-82§
64-85 t
64-80 t
64-77 t
64-88~
3(I)
t This strap configuration resets the Refresh Timer circuitry.
.o
t The highest frequency in the refresh frequency column is the frequency that is produced if the minimum ClK frequency of the next select
state is used.
§ The highest frequency in the refresh column is the refresh frequency if the ClK frequency is 5 MHz .
, The highest frequency in the refresh column is the refresh frequency if the elK frequency is 8 MHz.
n
,...
functional description
::J
,...
'"a
Co
r::::
(I)
TMS4500A consists of six basic blocks; address and select latches, refresh rate generator, refresh counter,
the multiplexer, the arbiter, and timing and control block_
address and select latches
The address and select latches allow the DRAM controller to be used in systems that mUltiplex address
and data on the same lines without external latches. The row address latches are transparent, meaning
that while ALE is high, the output at MAO-MA7 follows the inputs RAO-RA7.
refresh rate generator
The refresh rate generator is a counter that indicates to the arbiter that it is time for a refresh cycle. The
counter divides the clock frequency according to the configuration straps as shown in Table 1. The counter
is reset when a refresh cycle is requested or when TWST, FS 1 and FSO are low. The configuration straps
allow the matching of memories to the system access time.
Upon Power-Up it is necessary to provide a reset signal by driving all three straps to the controller low
to initialize internal counters. A system's low-active, power-on reset (RESET) can be used to accomplish
this by connecting it to those straps that are desired high during operation. During this reset period, at
least four clock cycles should occur_
refresh counter
The refresh counter contains the address of the row to be refreshed_ The counter is decremented after
each refresh cycle_ [A low-to-high transition on TWST sets the refresh counter to FF16 (25510).]
multiplexer
The multiplexer provides the DRAM array with row, column, and refresh addresses at the proper times.
Its inputs are the address latches and the refresh counter. The outputs provide up to 16 multiplexed
addresses on eight lines.
7-214
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TMS4500A
DYNAMIC·RAM CONTROLLER
arbiter
The arbiter provides two operational cycles: access and refresh. The arbiter resolves conflicts between
cycle requests and cycles in execution, and schedules the inhibited cycle when used in cycle-steal mode.
...
VI
CJ
::s
timing and control block
"C
The timing and control block executes the operational cycle at the request of the arbiter. It provides the
DRAM array with RAS and CAS signals. It provides the CPU with a RDY signal. It controls the mUltiplexer
during all cycles. It resets the refresh rate generator and decrements the refresh counter during refresh
cycles.
...o
c..
...
C
CI)
E
CI)
C)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
CO
C
Supply voltage range, VCC (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -1.5 V to 7 V
Input voltage range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 1 .5 V to 7 V
Continuous power dissipation ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.2 W
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 1 50°C
t Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1: Voltage values are with respect to the ground terminal.
recommended operating conditions
MIN
NOM
MAX
Supply voltage. VCC
PARAMETER
4.5
5
5.5
V
High-level input voltage. VIH
2.4
6
V
Low-level input voltage. VIL
_ll
0.8
V
-1
mA
High-level output current. 10H
Low-level output current. IOL
Short-circuit output current. lOS §
Operating free-air temperature. T A
4
mA
-50
mA
ac
70
0
UNIT
CO
:iE
...o>
E
:iE
CI)
(j)
-I
-
t The algebraic convention. where the less positive (more negative) limit is designated as minimum. is used in this data sheet for logic
voltage levels only.
§ Not more than one output should be shorted at a time.
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
[MAO-MA7. RDY
VOH
High-level output voltage
I RASa.
RAS1. CAS
IREFREQ
Vcc
=
4.5 V.
IOH
=
VCC
=
=
4.5 V.
IOH
IOL
= -100
= 4 mA
VOL
Low-level output voltage
VCC
IIH
High-level input current except REFREQ
VI
=
5.5 V
IlL
Low-level input current
VI
=
0
10Z
Off-state output current
ICC
Operating supply current
Ci
Input capacitance
Co
Output capacitance
IREFREQ
I All others
, All typical values are at VCC = 5 V. T A
4.5 V.
= 5.5
TA = oac
VI = O.
Vo = O.
VCC
V.
Vo
=
MIN
-1 mA
/lA
TYP'
f
=
=
UNIT
2.4
V
2.7
2.4
0 to 4.5 V
100
f
MAX
0.4
V
10
/lA
-1.25
mA
-10
/lA
± 50
/lA
mA
140
1 MHz
5
pF
1 MHz
6
pF
25 ac.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
>
7-215
TMS4500A
DYNAMIC·RAM CONTROLLER
timing requirements over recommended supply voltage range and operating free-air temperature (unless
otherwise noted)
<
r-
s:
CD
3
o
-<
s:m
::::s
m
CQ
CD
TMS4500A-25
MIN
MIN
MAX
100
120
140
ClK high pulse duration
40
40
40
tw(Cl)
ClK low pulse duration
40
45
tt
Transition time, all inputs
50
Time delay, ALE low to ClK
tAEl-Cl
starting low (see Note 1)
Time delay, ClK low to ALE
tCl-AEl
starting low (see Note 1)
Time delay, ClK low to ALE
tCl-AEH
tAV-AEl
starting high (see Note 2)
Pulse duration, ALE high
Time delay, address REN1, CS
."
n
....
TMS4500A-20
ClK cycle time
tw(AEH)
c.
c
MAX
tw(CH)
....::::s
...o
MIN
tc(C)
3
CD
TMS4500A-15
PARAMETER
!a
valid to ALE low
Time delay, ALE low to address
tAEl-AX
not valid
rn
(see Notes 3, 4, 5, and 6)
Time delay, ACX high to ClK low
tACH-Cl
(see Notes 3 and 7)
Time delay, ACX low to ClK
tACl-CH
starting high (to remove ROY)
Time delay, REFREQ low to ClK
tRQL-Cl
starting low (see Note 8)
twlRQU
Pulse duration, REFREQ low
tw(ACl)
ACX low duration (see Note 9)
NOTES:
7-216
UNIT
45
50
50
10
10
15
10
10
15
15
20
20
50
60
60
5
10
15
10
10
10
th(RA) +30
th(RA)+40
th(RA) +50
20
20
20
30
30
30
20
20
20
20
20
20
110
140
175
Time delay, ALE low to ACX low
tAEl-ACl
MAX
ns
1. Coincidence of the trailing edge of ClK and the trailing edge of ALE should be avoided as the refresh/access occurs on the
trailing ClK edge. A trailing edge of ClK should occur during the interval from ACX high to ALE low.
2. If ALE rises before ACX and a refresh request is present, the falling edge of ClK after tCl-AEH will output the refresh address
to MAO-MA7 and initiate a refresh cycle.
3. These specifications relate to system timing and do not directly reflect device performance.
4. On the access grant cycle following refresh, the occurrence of CAS low depends on the relative occurrence of ALE low to
ACX low. If ACX occurs prior to or coincident with ALE then CAS is timed from the ClK high transition that causes RAS
low. If ACX occurs 20 ns or more after ALE then CAS is timed from the ClK low transition following the ClK high transition
causing RAS low.
.
5. For maximum speed access (internal delays on both access and access grant cycles), ACX should occur prior to or coincident
with ALE.
6. th(RA) is the dynamic memory row address hold time. ACX should follow ALE by tAEl-CEl in systems where the required
th(RA) is greater than tREl-MAX minimum.
7. The minimum of 20 ns is specified to ensure arbitration will occur on falling ClK edge, tACH-Cl also affects precharge time
such that the minimum tACH-Cl should be equal or greater than: tw(RH) - tw(Cl) + 30 ns (for a cycle where ACX high
occurs prior to ALE high) where tw(RH) is the DRAM RAS precharge time.
8. This parameter is necessary only if refresh arbitration is to occur on this low-going ClK edge (in systems where refresh is
synchronized to external events).
9. The specification tw(ACl) is designed to allow a CAS pulse. This assures normal operation of the device in testing and system
operation.
TEXAS ""
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TMS4500A
DYNAMIC·RAM CONTROLLER
switching characteristics over recommended supply voltage range and operating free-air temperature
range (see Figure 1)
TEST
PARAMETER
TMS4500A-15
CONDITIONS
MIN
RAS starting low
Time delay, row address valid to
tRAV-MAV
=
Cl
memory address valid
160 pF
valid memory address
Time delay, ALE to ROY starting
tAEl-RYl
low (TWST
MIN
MAX
MIN
MAX
...,en
UNIT
35
40
50
(,)
45
50
60
65
75
90
40
40
40
....,
"'C
o
a..
r::::
Time delay, ALE high to
tAEH-MAV
TMS4500A-20 TMS4500A-25
;::,
Time delay, ALE low to
tAEl-REl
MAX
= 1 or refresh in progress)
Cl
=
40 pF
Q)
E
Q)
C)
as
r::::
as
Time delay, ALE low to CAS
tAEL-CEl
60
starting low (see Note 10)
Time delay, ALE high to RAS
tAEH-REH
tACl-MAX
tACl-CEl
Row address valid after ACX low
valid to CAS starting low
=
Cl
Time delay, ACX low to CAS
starting low (see Note 10)
0
0
0
5
starting high
ACX high
high (after ACX low) (see Note 11)
Cl
supported by REFREQ internal
= 40 pF
address valid
Time delay, ClK high till
10
refresh RAS starting low
Time delay, refresh address
tMAV-RRl
Cl
= 160 pF
starting high (3 cycle refresh)
Time delay, ClK high to REFREQ
tCH-RFH
tCH-RRH
tCH-MAX
NOTES:
45
130
50
40
10
40
E
Q)
2
en
165
..
>
50
15
50
starting high (4 cycle refresh)
Time delay, ClK high to refresh
5
RAS starting high
Refresh address valid after ClK high
15
15
40
45
60
30
35
35
30
35
45
75
100
125
50
5
valid till refresh RAS low
Time delay, ClK low to REFREQ
tCl-RFH
.
ns
internal starting low
tCH-RRl
30
10
Time delay, ClK low till refresh
tCl-MAV
100
30
starting high
Time delay, ClK high till REFREQ
tCH-RFl
2
>o
..J
Time delay, REFREQ external till
tRFl-RFl
250
40
25
Time delay, ClK high to ROY starting
tCH-RYH
30
20
40
Column address valid after
tACH-MAX
80
160 pF
Time delay, ACX high to CAS
tACH-CEH
200
15
Time delay, ACX to RAS
tACH-REH
70
30
starting high
Time delay, memory address
tMAV-CEl
150
15
60
20
80
5
5
50
55
75
50
55
75
35
15
10
20
45
10
60
25
10. The falling edge of CAS occurs when both ALE low to CAS low time delay (tAEl-CEl) and ACX low to CAS low time delay
(tACl-CEl) have elapsed, i.e., if ACX goes low prior to (tAEl-CEl - tACl-CEl) after the falling edge of ALE, the falling
edge of CAS is measured from the falling edge of ALE (tAEl-CEl)' Otherwise, the access time increases and the falling
edge of CAS is measured from the falling edge of ACX (tACl-CEl).
11. ROY returns high on the rising edge of ClK. If TWST = 0, then on an access grant cycle ROY goes high on the same edge
that causes access RAS low. If TWST = 1, then ROY goes to the high level on the first rising ClK edge after ACX goes low
on access cycles and on the next rising edge after the edge that causes access RAS low on access grant cycles (assuming
ACX low).
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-217
TMS4500A
DYNAMIC-RAM CONTROLLER
switching characteristics over recommended supply voltage range and operating free-air temperature
range (see Figure 1) (continued)
<
r-
s:
TMS4500A-15
CONDITIONS
MIN
Time delay, ClK high till access
tCH-REl
CD
3
o
TEST
PARAMETER
~
TMS4500A-20 TMS4500A-25
MIN
60
RAS starting low
Time delay, ClK low to access
tCl-CEl
MAX
=
Cl
CAS starting low (see Note 12)
tREl-MAX
Row address valid after RAS low
25
30
tAEH-MAX
Column address valid after ALE high
10
15
m
cc
tdis
Output disable time (3-state outputs)
100
125
ten
Output enable time (3-state outputs)
75
80
::::s
CD
25
30
40
35
Time delay, column address valid to
=
Cl
160 pF
3CD
::::s
....
..
tCH-CEl
."
tACl-Cl
ACX low to ClK starting low
Cl
tACl-RYH
ACX low to RDY starting high
Cl = 40 pF
tCl-ACl
ClK low to ACX starting low
Cl
=
40 pF
tt(CEl)
CAS fall time
tt(CEH)
CAS rise time
Cl
=
320 pF
Cl
=
160 pF
o
Co
c
....tnn
-
0
CAS starting low after refresh
Time delay, ClK high to access
tt(REl)
RAS fall time
tt(REH)
RAS rise time
tt(MAV)
Address transition time
tt(RYl)
RDY fall time
tt(RYH)
RDY rise time
Cl
=
=
25
40 pF
105
0
35
0
165
200
40
40 pF
20
0
180
CAS starting low (see Note 12)
UNIT
185
Row address valid after ClK low
tCAV-CEl
MAX
95
140
-<
s:
m
tCl-MAX
MIN
70
125
160 pF
MAX
235
ns
45
50
0
60
0
15
20
25
30
35
45
15
20
25
15
20
25
20
20
25
10
15
20
20
25
35
NOTE 12: On the access grant cycle following refresh, the occurrence of CAS low depends on the relative occurrence of ALE low
to ACX low. If ACX occurs prior to or coincident with ALE then CAS is timed from the ClK high transition that causes RAS
low. If ACX occurs 20 ns or more after ALE then CAS is timed from the ClK low transition following the ClK high transition
causing RAS low. (See Refresh Cycle Timing Diagram)
PARAMETER MEASUREMENT INFORMATION
VCC
Rl
OUTPUT
UNDER TEST
=
1150!l
Cl ' 160 pF
2400 !l
FIGURE 1 - LOAD CIRCUIT
7-218
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TMS4500A
DYNAMIC·RAM CONTROLLER
access cycle timing
en
.fJ
CJ
::::s
"C
ClK
..o
a..
ALE
.fJ
C
CD
ROW ~rT_ _~~~ ~--~~ ~~~~~Ir~~~~~rr~~~~~rr~~~~~~~~~"
REN1
COL CS L...:>I.:...¥.....l4-.lL....loL..:;/ 1'---...---'1
E
CD
C)
ca
c
ca
~
~
RAS
o
MAO-MA,
~
E
CD
CiS
...J
>
CAS
ROY
I'-----------------------+-----'I
I~---
refresh request timing
ClK~
\
/
\~-1
tRQl-ClH
REFREQ
(EXTERNAL)
RE"FFiEci
(INTERNAL)
"'H",,~
r\.
q.
~
tw(RQl)
~
\~-
:-
14- tRFL-RFL ~
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-219
TMS4500A
DYNAMIC·RAM CONTROLLER
ready timing (ACX during ClK high) (see notes 13 thru 16)
CLK~
<
r-
~
3:
(1)
ALE
3
I
}
l
\:
\\\\\\\\~tACl~l~
o
-<
D~
ACX
3:
tAEl-RY~ t,.A_C_l_-R_Y_H_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
D)
~
::s
D)
ROY
CQ
~
(1)
3(1)
...::s
ROY starting high is timed from ACX low (tACl-RYH) for the condition ACX going low while ClK high.
ready timing (ACX during ClK low) (see notes 13 thru 16)
...
o
."
c.
ClK
c(')
...en
-
~
r
\I
tCl-ACl~
ALE \
I
\
ACX
ROY
\
I
I
I
tCH-RYH-+j
r-
jr
ROY starting high is timed from ClK high (tCH-RYH) for the' condition ACX going low while ClK low.
NOTES: 13. For ROY high transition (during normal access) to be timed from the rising edge of ClK. ACX must occur tCl-ACl after
the falling edge of ClK.
14. For ACX prior to the falling edge of ClK by tACl-Cl. the ROY high transition will be tACl-RYH.
15. tACl-Cl is a limiting parameter for control of ROY to be dependent upon ACX low.
16. Ouring the interval for tACl-Cl < MINIMUM to tCl-ACl > MINIMUM. the control of ROY may vary between the rising
clock edge or falling edge of ACX.
output 3-state timing
ACR-ACW
OUTPUTS
7-220
TEXAS
~
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS, TeXAS 75265
TMS4500A
DYNAMIC-RAM CONTROLLER
refresh cycle timing (three-cycle)
CLK \
J
I l 0 0 ,_ _ _
;f
\
I
J
'"'I_ _ _
f,
\
I
!
:/'"---"":,",,,\\
-----I---------J·
\r-----I
Jf
\-.._ _..J
i
ALE
I~------'------------------~--------~I-----------ACX ____~--------~------~__~~~
:
\ \\t\ :
==x:
!+-+tCL-MA'v
:
RAS
X
REFRESH ADDRESS
ROW ADDRESS
~tCH-RRH
KtCH-RRL
~
:~tCL-MAX
X_______
KtCH-MAX
tcAV-CEL~
tCH-REL-H
"K""________________~y
!
~ tMAV-RRL~
I
\!
tCl-CEl t
t~",--
~----~~~~------~---------~-------\tit\
tCH-RFH---H
----~~~--~----------------~+f
tCL-MAV
I
I
tCH-MAX
±:!I _-------------...:........,;
REFRESH ADDRESS
MAO-MA7
~tCH-RRL
tCA V -C EL
-----I~--~~
I
I ____________
~
1144---~~I-tMAV-RR L
I
I
I
I
tCl-CEl t
I
14
--J4--+I
I
I
~I
t On access grant cycle following refresh. CAS low and address mUltiplexing are timed from ClK high transition (tCH-CEl) if ACX low
occurs prior to or coincident with the falling edge of ALE.
t On access grant cycle following refresh. CAS low and address multiplexing are timed from ClK low transition (tCl-CEl) if ACX low occurs
20 ns or more after the falling edge of ALE.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
CO
c:
CO
~
~
o
:2E
~
14
Q)
C)
Cii
...J
CLK
REFREQ
.
o
a..
....c:
Q)
E
refresh cycle timing (four-cycle)
ALE
ACX
:::s
"C
Q)
!
\'--tCH-CEl
(,)
E
I
JI :
I
MAO-MA7
:
tCL.RFH~
:
....tn
7-221
>
TMS4500A
DYNAMIC·RAM CONTROLLER
typical access/refresh/access cycle
(three-cycle, TWST is low)
<
r-
2
~
::2:
::J
s:
CD
N
.
3
"
U
0
'<
s:
CI)
::I
CI)
C"l
CC
CD
3CD
en
en
w
u
U
~
<
~
CIl
w
a:
u.
w
a:
~
~
o;t
- - --- CIl
CIl
w
<
:2!
....I
--- ---
U
u
z
:J
M
-
0
U
N
---
W
....I
«
I~
x
«
:2!
I~
15
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
I~
>
oa:
7-223
TMS4500A
DYNAMIC·RAM CONTROLLER
typical access/refresh/access cycle
(three·cycle, TWST is high)
<
r~
z
3:
3
o
:!:
N
CD
:;)
..I
oU
_ _ _ _ _ _ _ _ _ _ __
-<
3:
D)
:::s
D)
CQ
CD
3
CD
...:::s
M
..
."
o
c.
c(')
...z
...en
N
ct
a:
-
~
en
en
w
u
u
ct
:t
en
w
a:
N
3:
u..
w
a:
M
N
en
en
w
uu
ct
3:
I~
7-224
I~
15
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Ii
>
o
a:
TMS4500A
DYNAMIC·RAM CONTROLLER
typical access/refresh/access cycle
(four-cycle, TWST is high)
....CJ
U)
::::J
"C
oa-
-
N
3:
----- - - - - --
J:
(/)
w
a::
~
u..
w
a::
z
----- ----- --
(/)
(/)
w
U
U
:!:
3 ----- ----- -o
u
N
ct
w
....
ct
I~
I~
TEXAS
15
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
II
>
C
a::
7-225
<
r~
s:
CD
3
o
-<
s:
m
:::J
m
CQ
CD
3
CD
:::J
....
...""CI
o
Co
c:
n
....en
-
7-226
SN74ALS6310, SN74ALS6311
STATIC COLUMN AND PAGE·MODE ACCESS DETECTORS
03020. JUNE 1987-REVISED APRIL 1988
o
Detects Present Row Equal to Last Row
Address
o
High·Performance Compare:
'ALS6310 CLK to HSA - 18 ns
, ALS6311 Address to HSA - 14 ns
o
o
o
OW OR N PACKAGE
(TOP VIEWI
ClK
ClKEN
Easily Interfaced with Microprocessor and
Memory Timing Controller
Dependable Texas Instruments Quality and
Reliability
(.)
~
HSA
HSA
83
82
81
80
A9
A8
A7
AO
A1
A2
A3
A4
A5
A6
Compatible with 16K to 1 M DRAMs
....en
VCC
GND
"C
...0
c..
....C
Q)
E
Cl)
C')
as
c
as
escription
a
FN PACKAGE
The ' AlS631 0 and ' AlS6311 are highperformance address comparators designed for
implementing static column and page-mode
access cycles.
...>-
(TOP VIEWI
z
0
~ ~ U I
When interfaced with the memory timing
controller, these devices will detect if the present
row being accessed is the same as the last row
accessed. This is the fundamental requirement
for implementing static column decode or pagemode access cycles.
3
A1
A2
A3
A4
A5
2
E
Q)
:E
1 20 19
18
17
16
15
14
(j)
HSA
83
82
81
80
....I
>
9 10 11 12 13
The' AlS631 0 features two 14-bit registers and
a high-speed address comparator. The first
register is used to save the present row address
while the second register is used to save the
previous row address. On the high-to-Iow transition of elK, the first register loads the new row address
present on AO-A9. At the same time, the second register loads the address previously saved in the first
register. The two row addresses are then compared. The High-Speed Access outputs (HSA and HSA) will
signal if the two addresses are equal.
The BO-B1 inputs are provided to monitor access cycles to different banks of memory. When used in
conjunction with the' AlS2968 and' AlS6302 series DRAM controllers, the' AlS631 0 and' AlS6311
can monitor up to 16 banks of memory. The elK input on the' AlS631 0 can typically be interfaced with
the microprocessor's Address latch Enable (ALE) or Address Strobe (AS) outputs. This configuration
simplifies the memory timing controller interface. Refer to the typical application diagram for further
information.
The' AlS6311 features one 14-bit register feeding a high-speed address comparator. This architecture
offers a faster address match time, but does require the memory timing controller to generate the elK
input. Typically, the 14-bit register would only be updated if there was a change in row or bank address.
Refer to the application diagram for further information.
More information on static column DRAM access can be found in the Texas Instruments application report
System Solutions for Static Column Decode.
The SN74AlS6310 and SN74AlS6311 are characterized for operation from oDe to 70 o e.
ADVANCE INFORMATION documents contain
information on new products in the samplin~ or
~reproduction phase of development Characteristic
data and other specifications are subject to change
without notice.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © 1987. Texas Instruments Incorporated
7-227
;2
o
ti~
ex:
o
u.
2
w
()
2
~
C
H
HSAO HSAO
:2
n
m
o
HSA
HSAOtHSAOt
logic symbols
'ALS6310
:2
"T1
OUTPUTS
CLKEN
'ALS6311
ClKEN
15C16
ClK
:lJ
S
15C16
CaMP
~
o
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
BO
Bl
B2
B3
:2
-
<
r~
s:
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
160
160
160
160
160
160
160
160
160
160
160
160
160
160
Zl
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Z9
Z10
Zll
Z12
Z13
Z14
160
160
160
160
160
160
160
160
160
160
160
160
160
160
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CD
3
o
-<
s:
m
::::I
m
CC
CD
3
CD
::::I
r+
CaMP
0
AO
13
P-O
P-O
0
(19)
HSA
(18)
HSA
Al
A2
A3
A4
A5
A6
A7
A8
A9
BO
Bl
B2
B3
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
P
p-o
13
0
P-O
(19)
HSA
HSA
Q
7
8
9
10
11
12
13
14
13
...
c.
c
n
r+
0
1
2
3
4
5
"'C
o
Zl/160
Z2/160
Z3/160
Z4/160
Z5/160
Z6/160
Z7/160
Z8/160
Z9/160
Z10/160
Zll/160
Z12/160
Z13/160
Z14/160
0
13
t Only if AO-A9 and BO-B3 inputs do not change from the time HSA
and HSA were detected.
(/)
7-228
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74ALS6310. SN74ALS6311
STATIC COLUMN AND PAGE·MODE ACCESS DETECTORS
logic diagrams (positive logic)
'AlS6310
....CJ
t/)
ClKEN
:::s
..
ClK
"C
PRESENT ADDRESS
PREVIOUS ADDRESS
REGISTER
REGISTER
0
c..
~Nl
yEN 1
....c
CaMP
CD
E
CD
1C2
-,1C2
C)
AO-AS
I
)
10
[ROW]
,.L
2D
[ROW]
BO-B3
I
)
4X
4
[BANK]
2D
=i=
2D
4X
4
ca
ca
10X
10X
10
)
-
~
[BANK]
2D
10
)
4
)
}.
P-Q
-
C
HSA
:E
>-
.
0
E
CD
:E
P-Q ~ HSA
en
...I
>
-
~}a
2:
0
'AlS6311
~
PREVIOUS ADDRESS
~
REGISTER
ClKEN
ClK
a:
CaMP
------t
0
--------4>
LL
2:
10
AO-AS
4X
[BANK]
4
BO-B3
10
4
TEXAS
}.
P-Q
w
HSA
(.)
2:
P-Q
~
C
«
HSA
~}a
-1!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-229
I
SN74ALS6310, SN74ALS6311
STATIC COLUMN AND PAGE·MODE ACCESS DETECTORS
absolute maximum ratings over operating free-air temperature range
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage .............................................................. 7 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 0 e
Storage temperature range ......................................... - 65 °e to 150 °e
:t>
~
»
2
recommended operating conditions
SN74ALS6310
SN74ALS6311
(')
m
2
-n
o:J::J
S
~
o
2
<
r~
s:
MIN
4.5
Vee Supply voltage
VIH High-level input voltage
VIL low-level input voltage
10H High-level output current
low-level output current
Pulse duration, elK high or low
tsu
Setup time before elK! (' AlS631 0)
tsu
Setup time before elKi (' AlS6311)
th
Hold time after elK! (,AlS6310)
th
Hold time after elKi ('AlS6311)
TA
Operating free-air temperature
5.5
24
10
AO-A9 or 80-83
elKEN high or low
AO-A9 or 80-83
elKEN high or low
AO-A9 or 80-83
elKEN
AO-A9 or 80-83
elKEN
8
8
8
V
V
V
mA
mA
ns
ns
ns
8
5
ns
5
5
5
0
ns
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
SN74ALS6310
PARAMETER
o
-<
TEST CONDITIONS
CD
IIH
Vee
Vee
Vee
r+
III
Vee
a."
10*
Vee
= 4.5 V,
= 4.5 V to
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
lee
Vee
=
VIK
s:
VOH
D)
:s
D)
cc
Val
CD
II
3
:s
Co
(I)
5
0.8
-2.6
10l
tw
3
S.
MAX
2
CD
c
UNIT
NOM
Vee
Vee
Vee
Vee
5.5 V
II
5.5 V,
=
-18 mA
= -0.4 mA
10H = -2.6 mA
10l = 12 mA
10l = 24 mA
VI = 7 V
VI = 2.7 V
VI = 0.4 V
Va = 2.25 V
10H
I 'AlS6310
I 'AlS6311
SN74ALS6311
MAX
MIN TVpt
-1.2
Vee- 2
3.2
2.4
0.25
0.35
50
40
V
V
0.4
0.5
0.1
20
-0.2
-30
UNIT
V
mA
p.A
mA
-112
mA
80
70
mA
tAli typical values are at Vee = 5 V, TA = 25°e.
*The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current. lOS.
7-230
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN7 4ALS631 0, SN74ALS6311
STATIC COLUMN AND PAGE·MODE ACCESS DETECTORS
,ALS631 0 switching characteristics (see Note 1)
PARAMETER
tpLH
tpHL
tpLH
tpHL
FROM
(INPUT)
TO
(OUTPUT)
CLK!
HSA
CLK!
HSA
Vce - S v.
eL - so pF.
RL - SOO n.
TA - 2soe
MIN
TYP
MAX
12
11
12
18
12
12
18
11
...en
vee - 4.S v to s.s V.
eL - so pF.
UNIT
RL - SOO n.
TA - ooe to 70 0 e
MAX
MIN
4
18 ns
4
18 ns
4
18
ns
4
18
ns
CJ
::l
"C
...o
Q.
, ALS6311 switching characteristics (see Note 1)
Vcc - 4.5 V to 5.5 V.
Vcc - 5 V.
CL - SO pF.
CL - SO pF.
FROM
(INPUT)
TO
(OUTPUT)
tpLH
CLKt
HSA
7
11
tPHL
tpLH
CLKt
HSA
7
11
4
7
10
14
3
12
12
ns
ns
14
4
4
14
14
ns
ns
10
3
12
ns
PARAMETER
tpHL
tpLH
tpHL
AO-A9 or BO-B3
HSA
AO-A9 or BO-B3
HSA
RL - SOO n.
TA - 2SoC
MIN
TYP
MAX
9
9
7
NOTE 1: Load circuit and voltage waveforms are shown in Section 1 of The LSI Logic Data Book.
UNIT
RL - SOO n.
TA - ooc to 70°C
MAX
MIN
4
12 ns
2
o-
!:(
:2E
a:
oLL
2
w
U
2
:§
C
nrn en
c=
r-~
c:-
J\)
VCC
L
4
SO-S3
REFREO
--.-
RFC
--+-
~
;or;;i
.-
AS
T
~~
'AlS6310
ONLY
I
I
I
·
r.,
r--+
CO~~:~
:
4
AS
HSA
AO
> •
•
A9
ROW
A10-A19 •
f
101M
W
10
---+---+---+---+-
ClK<
-
HSA
Zen
>Z
Z .......
CASO
c,;::..
>
W
r
II
RASI
MSEl
10
)
CASI
MC1
··•
MCO
RAS1
r- r-
es
CAS1 f-- I--
CAS1
-
10
>
_____ .- ___ JI
BANK 2
1MEG X 32 BITS
(32) TMS4C1027
···
AO
RAS2 f-- I--
RAS2
CAS2 f-- I--
CAS2
BO
~
···
10
)
A19
AO
··•
II
BANK 3
1 MEG X 32 BITS
(32) TMS4C1027
A9
A20
SElO
RAS3
A21
SEl1
CAS3
.
r-
"C
r-
0
»-I
0
»-I
»
II
)
-<
0
:2
C
W
AO
20
II
A9
'AlS6311 ONLY
-I
»
»"C
W
I I
ClKOUT ...,
-
m~
"C
RAS1
~
-ar:z:-en
C)=
II
BANK 1
1 MEG X 32 BITS
(32) TMS4C1027
AO
A9
OE
:s::?
RASO
RASO f - - -
R/W
STATIC COLUMN
DETECT
SN74AlS6310/6311
4l f> ClK
A10-A19
MC1
ClK
..
..
R/W
~~
CASI
RESET
SYS RST
···
RFC
MSEl
BANK 0
1 MEG X 32 BITS
(32) TMS4C1027
AO
A9
CASO f - - -
RASI
10/M(A22)
>
• f---
09
REFREO
SYSClK
Z
··
10
r-
ClK
OSC
DYNAMIC RAM
00
~ RST
SYSTEM
CLOCK
-
lE
TIMING
CONTROllER
(PROGRAMMED
TIBPSG507)
REFRESH
TIMER
SN74AlS6300
REFRESH
RATE
SELECT
DRAM
CONTROllER
SN74AlS6301
RAS3
CAS3
W
DO • • • 031
00 • • • 031
.
:s::c
C
m
:z:-
n
n
m
en
en
C
m
.....
m
n
.....
C
=
en
SN74ALS6310, SN74ALS6311
STATIC COLUMN AND PAGE·MODE ACCESS DETECTORS
TYPICAL APPLICATION DATA
....enCJ
'AlS6310/'AlS6311 WORD lENGTH EXPANSION
::s
'AlS6310/'AlS6311
.
"'C
ClKEN
ClKEN
ClK
0
ClK
)
,
'")
AO-A9
~
....C
HSA
CD
E
CD
80-83
C)
ca
c
ca
~
'AlS6310/'AlS6311
ClKEN
~
ClK
>
AO-A9
>
80-83
'"
,
0
E
CD
HSA t - - -
~
Cii
....I
>
'AlS631 O/' AlS6311
HSA1
ClKEN
ClK
70
,
>
,
)
AO-A9
HSA2
HSA
HSA3
,
,
)
T18PAD16N8-7
HSA
2
0
~
HSA4
80-83
HSA5
~
a:
'AlS631 O/' AlS6311
0
ClKEN
ClK
)
AO-A9
'"
,'2
80-83
,
LL
-w
2
HSA
-
(.)
2
c~
'AlS6310/'AlS6311
- AO-A9
" 80-83
>
HSA
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-233
I
<
r~
s:
CD
3
o
-<
s:
Q)
:::s
Q)
co
CD
3
CD
:::s
,...
.
"0
o
c.
..
c
(')
,...
U)
7-234
SN74BCT2827A, SN74BCT2828A
10-BIT BUS/MOS MEMORY DRIVERS WITH 3-STATE OUTPUTS
D2977, APRIL 1987-REVISED APRIL 1988
•
•
ow
BiCMOs Design Substantially Reduces
Standby Current
OR NT PACKAGE
(TOP VIEW)
<31
Al
A2
A3
A4
A5
A6
A7
A8
A9
A10
25-{} Series Resistors at Outputs
Significantly Reduce Overshoot and
Undershoot
•
Specifically Designed to Drive MOs DRAMs
•
3-state Outputs
o
Data Flow-Thru Pinout (All Inputs on
Opposite Side from Outputs)
o
Power-Up High-Impedance State
o
Package Options Include Plastic "Small
Outline" Packages, Plastic Chip Carriers,
and Standard Plastic DIPs
tn
.....
(,)
VCC
Yl
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
<32
GND
::::J
"'C
.
o
0.
.....
r::::
Q)
E
Q)
C)
CO
r::::
CO
:E
>-
..
o
FN PACKAGE
E
Q)
:2!
(TOP VIEW)
description
U
These 10-bit buffers and bus drivers are
specifically designed to drive the capacitive input
characteristics of MOS DRAMs. They provide
high-performance bus interface for wide data
paths or buses carrying parity.
N~-UU_N
>- >-
(j)
...J
The three-state control gate is a 2-input positive
NOR gate so if either G 1 or G2 is high. all 10
outputs are in the high-impedance state.
The SN74BCT2827 A provides true data and the
SN74BCT2828A provides inverted data at the
outputs.
25
NC
22
NC
A6
A7
A8
21
Y6
Y7
Y8
24
23
20
19
>
Y3
Y4
Y5
A3
A4
A5
2
o
~
12 13 14 15 16 17 18
Cl'lOOUNOCl'l
-
These devices are characterized for operation
from OOC to 70°C.
>-
~
a:
oLL
NC-No internal connection
-w
2
CJ
2
~
C
«
ADVANCE INFORMATION documents contain
~~~~~~:~~~rO:~h~:: o~r::vue~~~~~ntt~8c~:~~!~~rsti~
ilata and other specifications are subject to change
without notice.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © 1987. Texas Instruments Incorporated
7-235
SN74BCT2827A, SN74BCT2828A
10·BIT BUS/MOS MEMORY DRIVERS WITH 3·STATE OUTPUTS
logic symbols t
SN74BCT2827A
SN74BCT2828A
J>
~
»
2
A2 (3)
A3 (4)
(")
A4
m
A5 (6)
2
A7
o
A9 (10)
S
~
(S)
(1S) Y6
(17) Y7
AS (9)
(16) YS
A10 (11)
::D
A1
A2
A3
A4
(20) Y4
(19) Y5
(5)
A6 (7)
"TI
(2)
(3)
(4)
(5)
A5 (6)
A6 (7)
A7 (S)
AS (9)
(15) Y9
A9 (10)
(14) Y10
A10 (11)
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
..
o
(23) Y1
(22) Y2
(21) Y3
A1 (2)
logic diagrams (positive logic)
SN74BCT2828A
SN74BCT2827A
2
01 (1)
02
(13)
(23) V1
(23) V1
(22) V2
(22) V2
(21) V3
(21) V3
-<
(20)
V4
(20) V4
:s
(19) V5
(19) V5
(1S) V6
(1S) V6
(17)
V7
(17) V7
(16)
va
(16)
(151
V9
(15) V9
<
r~
3:
CD
3
o
3:
m
m
CQ
CD
3CD
....:s
."
a
Q.
c
....
va
C')
(I)
>-_--...:(...;.14..;.:.)
v 10
~_---,(_14...;.) V 1 0
Pin numbers shown are for OW and NT packages.
7-236
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74BCT2827A
1n·BIT BUS/MOS MEMORY DRIVERS WITH 3·STATE OUTPUTS
Ibsolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
....CJ
U)
::::s
.
"'0
o
~
....C
'ecommended operating conditions
C1)
MIN
NOM
MAX
4.5
5
5.5
Vee
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
V
2
V
C)
V
10H
High-level output current
-1
10L
Low-level output current
12
mA
mA
TA
Operating free-air temperature
70
°e
~Iectrical
E
C1)
UNIT
Supply voltage
0
ca
c
ca
~
~
o
E
characteristics over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Vee
Vee
VIK
VOH
Vee
VOL
Vee
10ZH
10ZL
Vee
10L
Vee
10H
II
Vee
Vee
Vee
IIH
Vee
IlL
Vee
lo~
Vee
leeL
Vee
leez
Vee
=
=
=
=
=
=
=
=
=
=
=
=
=
=
4.5 V.
4.5 V to 5.5 V.
II
= -1 mA
= 1 mA
10L = 12 mA
Vo = 2.7 V
Vo = 0.4 v
Vo = 2 V
Vo = 2 V
VI = 7 V
VI = 2.7 V
VI = 0.4 V
Vo = 2.25 v
4.5 V.
5.5 V.
5.5 V.
4.5 V.
4.5 V.
5.5 V.
5.5 V.
5.5 V.
v.
Tvpt
-18 mA
MAX
-1.2
UNIT
:E
V
U)
V
VCC- 2
10H
10L
4.5 V.
5.5
MIN
=
0.15
0.5
0.35
0.8
20
-20
50
-35
0.1
20
-0.2
-112
-30
5.5 V.
Outputs open
28
40
5.5 V.
Outputs open
3.5
6
C1)
..J
-
>
V
p.A
p.A
mA
mA
mA
p.A
mA
mA
2
o
~
2
a:
mA
t All typical values are at Vec = 5 V. T A = 25°C.
~ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current. lOS.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CL - 50 pF.
R1 - 500 fl.
R1 - 500 fl.
R2 - 500 fl.
TA - 25°C.
MIN
TVP
MAX
tpLH
tpHL
tpZH
tpZL
tpHZ
tpLZ
A
IT
IT
4
V
V
7
6
8
9
8
10
13
11
14
17
8
7
12
15
11
13
y
TEXAS
6
R2 - 500 fl.
TA - MIN to MAX
MAX
MIN
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
-2w
U
VCC - 4.5 V to 5.5 V.
VCC - 5 V.
CL - 50 pF.
oLL
2
~
UNIT
C
<:(
ns
ns
ns
7-237
SN74BCT2828A
10-BIT BUFFERS BUS/MOS MEMORY DRIVERS WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7·
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5·
Voltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5'
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 °
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 °e to 1 50°,
l>
c
<
l>
2
recommended operating conditions
("')
MIN
NOM
MAX
4.5
5
5.5
UNIT
m
Vee
Supply voltage
VIH
High-level input voltage
2
Vil
Low-level input voltage
0.8
V
IOH
High-level output current
-1
mA
IOL
TA
Low-level output current
12
mA
70
°e
."
o
:a
s:
l>
Operating free-air temperature
0
electrical characteristics over recommended operating free-air temperature (unless otherwise noted
::!
PARAMETER
o
-
2
TEST CONDITIONS
VIK
Vee
VOH
Vee
Vee
VOL
Vee
IOZH
IOZl
Vee
IOL
Vee
IOH
II
Vee
s:
IIH
Vee
(1)
IlL
Vee
3
lot
Vee
-<
leeL
Vee
leez
Vee
<
r~
o
s:
m
:l
m
co
(1)
V
V
2
Vee
Vee
= 4.5
= 4.5
= 4.5
= 4.5
= 5.5
= 5.5
= 4.5
= 4.5
= 5.5
= 5.5
= 5.5
= 5.5
= 5.5
= 5.5
MIN
=
V,
II
V to 5.5 V,
IOH
IOL
Typt
-18 mA
MAX
UNIT
-1.2
V
V,
= -1 mA
= 1 mA
IOl = 12 mA
Va = 2.7 V
Va = 0.4 V
Va = 2 V
Va = 2 V
VI = 7 V
VI = 2.7 V
VI = 0.4 V
Va = 2.25 V
V,
Outputs open
28
40
V,
Outputs open
4.5
8
V,
V,
V,
V,
V,
V,
V,
V,
V,
V
VCC- 2
0.15
0.5
0.35
0.8
20
-20
V
p.A
p.A
mA
50
- 35
mA
0.1
-30
mA
20
p.A
-0.2
mA
-112
mA
mA
t All typical values are at Vee = 5 V, T A = 25 °e.
t The output conditions have been chosen to produce a curent that closely approximates one half of the true short-circuit output current, lOS
switching characteristics (see Figure 1)
3(1)
:l
,..
.o
."
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
c.
c
MIN
,..
(")
tpLH
en
tPHL
tpZH
tpZL
tpHZ
tpLZ
7-238
A
y
G
Y
G
Vcc - 5 V,
CL - 50 pF,
Vcc - 4.5 V to 5.5 V,
R1 - 500 fI,
R2 - 500 fI,
R1 - 500 fI,
R2 - 500 fI,
TA - 25°C,
TYP
MAX
TA - MIN to MAX
MIN
MAX
y
TEXAS
CL - 50 pF,
UNIT
5
7
8
5
7
8
8
11
12
10
14
16
10
14
16
8
12
14
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ns
ns
ns
SN74BCT2827A, SN74BCT2828A
10-BIT BUS/MOS MEMORY DRIVERS WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
....
t/)
7V
b
(.)
RL - R1 - R2
::s
.
SWITCH POSITION TABLE
"C
S1
TEST
S1
tpLH
Open
tpHL
Open
R1
FROM OUTPUT---4....-4I~-4I~ TEST
UNDER TEST
POINT
R2
CL
(See Note AI
tpZH
Open
tpZL
Closed
tPHZ
Open
tpLZ
Closed
o
c..
....c
Q)
E
Q)
C)
CO
C
CO
TIMING
INPUT
2:
-=
LOAD CIRCUIT
HIGH·LEVEL
PULSE
./.,----- 3 V
_ _ _--'4_1'-.5
':! ___ --0 V
.... tsu~th~
I
DATA
INPUT
~
LOW-LEVEL
PULSE
1.5V
0 V
..L1 . 5 V
~
I·
tPLH~
IN-PHASE
OUTPUT
I
I
/1
1.5 V :
tpHL~
3 V
OUTPUT
CONTROL
OV
1.5 V
.
~VOH
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
-
~E
1 5 V
I
VOL
.
:2
3V
~
-I
----OV
tPZL~ f4""""
VOH
I4------+t-tpLH
1
\
~1-!;~
~
I
I
OUT-OF-PHASE
OUTPUT
~tPHL
I
tw
1.5 V
0 V
>
VOLTAGE WAVEFORMS
PULSE DURATIONS
~5~- -
\
-!
~
1.5 V
I
E
Q)
1.5 V
I
I
I
....--tw~
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT
1.5 V
I
'4
-:----3V
1.5V
~
..
>
o
----3V
I
3V
2
1 5 V
o
J - - - - OV
I
tPLZ~
i=
/4-
C
>- >-
Cii
1 2827 26
A3
A4
A5
6
23
Y3
Y4
Y5
NC
8
22
NC
A6
A7
A8
9
21
10
20
Y6
Y7
Y8
25
24
11
19
....I
>
12 131415 1617 18
NC- No internal connection
The SN74BCT29827 A provides true data and
the SN74BCT29828A provides inverted data at
the outputs.
The SN74BCT29827 A and SN74BCT29828A
are characterized for operation from O°C to
70°C.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~at~:I~~~ ~!~:i~~ti:r ~lo~:~:~:t::s~S not
Copyright © 1987. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
7-241
SN74BCT29827A, SN74BCT29828A
10·BIT BUFFERS AND BUS DRIVERS WITH 3·STATE OUTPUTS
logic symbols t
SN74BCT29828A
SN74BCT29827A
<
r~
s:
CD
(22) Y2
Al (2)
A2 (3)
(21) Y3
A3 (4)
(20) Y4
A4 (5)
Al (2)
A2 (3)
A3 (4)
(23) Yl
s:
A4 (5)
AS (6)
(19) Y5
AS (6)
::::J
A6 (7)
(18) Y6
A6 (7)
A7 (8)
(171 Y7
A7 (8)
A8 (9)
(16) Y8
A8 (9)
A9 (10)
(15) Y9
A9 (10)
Al0 (11)
(14) Yl0
Al0 (11)
3
o
-<
D)
D)
CC
CD
3CD
....::::J
...
"'tJ
oQ.
C
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
logic diagrams (positive logic)
....
en
(")
SN74BCT29827A
SN74BCT29828A
G1..;.(1;..:.,)_ _..a--",
0'1 (1)
G2 (13)
0'2 (13)
A 1 ....
(2"";")_--1
(23) Yl
A 1 ..
(2"";')_--1
(23) Y1
A2 (3)
(22) Y2
A2 (3)
(22) Y2
A3 (4)
(21) Y3
A3 (4)
(21) Y3
A4 (5)
(20)
Y4
A4 (5)
(20) Y4
AS (6)
(19) Y5
AS (6)
(19) Y5
(18) Y6
A6 (7)
(18) Y6
A7 (S)
(17)
AS (9)
(16)
Y8
AS (9)
(16) Y8
A9 (10)
(15)
Y9
A9 (10)
(15) Y9
(14)
Y10
(17) Y7
Y7
A 10 (11)
Pin numbers shown are for DW and NT packages.
7-242
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
(14) Y10
SN74BCT29827A
10·BIT BUFFERS AND BUS DRIVERS WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (all inputs and I/O ports) " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Vee
Supply voltage
High-level input voltage
VIL
Low-level input voltage
IOH
IOL
TA
Operating free-air temperature
MIN
NOM
MAX
4.5
5
5.5
2
Q)
V
E
V
V
High-level output current
-24
mA
Low-level output current
48
mA
70
°e
0
Q)
C')
C'CI
C
C'CI
~
electrical characteristics over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST eONDITIONSt
VIK
Vee
=
MIN.
VOH
Vee
=
MIN
VOL
Vee
=
MIN.
IOZH
Vee - MAX.
IOZL
II
Vee
IIH
Vee
IlL
Vee
=
=
=
=
=
=
=
Vee
IOS§
Vee
leeL
Vee
leez
Vee
II
=
IIOH
I IOH
MIN
Typt
-18 mA
= -15 mA
= -24 mA
= 48 mA
MAX
-1.2
2.4
2
~
V
ti)
V
Vo - 2.7 V
20
p.A
-20
p.A
0.1
mA
MAX.
= 0.4 V
VI = 5.5 V
VI = 2.7 V
VI = 0.4 V
Vo = 0
-250
mA
MAX.
Outputs open
28
40
mA
MAX.
Outputs open
3.5
6
mA
MAX.
MAX.
MAX.
MAX.
0.35
V
0.5
IOL
Vo
-75
20
p.A
-0.2
mA
,-I
>
I
switching characteristics
vee - 4.5 V to 5.5 V.
vee - 5 V
tpZH
tpZL
tpHZ
tpLZ
eL - 50 pF.
FROM
TO
R1 - 500 fl.
R1 - 500 fl.
(INPUT)
(OUTPUT)
R2 - 500 fl.
R2 - 500 fl.
TA - 25°e
TYP
MAX
TA - MIN to MAX
MIN
MAX
6
7
7
MIN
tpHL
eL - 50 pF.
A
Y
G
y
G
3.5
5
Y
TEXAS
UNIT
9
7
10
12
10
13
15
7
10
12
7
10
12
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
...o>-
E
Q)
UNIT
t For conditions shown as MIN or MAX. use appropriate value specified under recommended operating conditions.
t All typical values are at Vee = 5 V. T A = 25°e.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed 1 second.
tpLH
...o
....C
UNIT
0.8
PARAMETER
(,)
~
"C
c..
recommended operating conditions
VIH
....en
ns
ns
ns
7-243
SN74BCT29828A
10·BIT BUFFERS AND BUS DRIVERS WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (all inputs and I/O ports) .......................................... 5.5 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 0 e
Storage temperature range ......................................... - 65 °e to 150 °e
<
r~
:s::
CD
3
o
-<
:s::
m
~
m
CQ
CD
3
CD
,..
~
..
recommended operating conditions
MIN
4.5
Vee
Supply voltage
VIH
VIL
High-level input voltage
IOH
IOL
TA
High-level output current
Low-level output current
NOM
MAX
5
5.5
V
V
2
Low-level input voltage
Operating free-air temperature
UNIT
0
0.8
-24
V
mA
48
mA
70
°e
electrical characteristics over recommended operating free-air temperature (unless otherwise noted)
TEST CONDITIONSt
PARAMETER
""C
o
c.
c
n
,..
en
-
VIK
vee
=
MIN,
VOH
Vee
=
MIN
VOL
Vee
Vee
IOZL
II
Vee
Vee
IIH
IlL
Vee
Vee
IOS§
leeL
Vee
Vee
leez
Vee
=
=
=
=
=
=
=
=
=
MIN,
IOZH
MAX,
MAX,
MAX,
MAX,
MAX,
MAX,
MAX,
MAX,
II
=
MIN
TYP*
-18 mA
= -15 mA
= -24 mA
= 48 mA
= 2.7 V
Vo = 0.4 V
VI = 5.5 V
VI = 2.7 V
VI = 0.4 V
Vo = 0
IIOH
2.4
IIOH
IOL
Vo
2
MAX
-1.2
UNIT
V
V
0.5
V
20
p.A
-20
0.1
p.A
mA
20
-0.2
p.A
mA
-250
mA
0.35
-75
Outputs open
28
40
mA
Outputs open
3.5
6.5
mA
t For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions.
t All typical values are at Vee = 5 V, T A = 25°e.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed 1 second.
switching characteristics
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
tpLH
tpHL
tpZH
tPZL
tpHZ
tpLZ
7-244
A
Y
G
Y
G
- 5 V
50 pF,
500 n,
500 n,
Vee - 4.5 V to 5.5 V,
TA - 25°e
TYP
MAX
TA - MIN to MAX
MIN
MAX
Vce
eL R1 R2 -
3.5
3.5
7
9
6
6
Y
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
CL - 50 pF,
R1 - 500 n,
R2 - 500 n,
6
6
UNIT
7
7
9
11
13
15
10
9
10
11
ns
ns
ns
SN74BCT29827A, SN74BCT29828A
10·BIT BUFFERS AND BUS DRIVERS WITH 3·STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
7V
b
S1
R1
FROM OUTPUT_t_---4.----4I.-. TEST
UNDER TEST
POINT
R2
CL
(See Note A)
LOAD CIRCUIT
TIMING
INPUT
~;.~:;3V
~OV
:
IN-PHASE
OUTPUT
I
I
I
/1
1
0 V
e
i1-5~
1
VOL
~ tpLH
1
~VOH
1.5 V
OUT-OF-PHASE
OUTPUT
\
1.5 V
•
Open
tpZL
Closed
tpHZ
Open
tpLZ
Closed
...o
D.
....C
CI)
E
CI)
C)
LOW·LEVEL
: - - tw ------:
~1.5V ··1. 5V
: . - - tw
-.I
~
o
E
CI)
:E
0 V
..v-
3 V
en
....I
>
~---OV
PULSE
OUTPUT
CONTROL
F
~15V
~ s---L1~'~'--ov
tPZL...-I
I
VOH
tpHL """'14----+1
I
tpZH
"'0
~- - - 3 V
~1.5V
1.5V~
~tPHL
,1.5V:
Open
VOLTAGE WAVEFORMS
PULSE DURATIONS
\~:--3V
tPLH~
Open
tpHL
HIGH-LEVEL
PULSE
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT J 1 . 5 V
tpLH
:2E
~tsu~th~
v
S1
-=
V
___-J_,/>.5
__ ------oV
I ....
C.)
:::s
TEST
ca
c
ca
3V
DATA
INPUT ~
....en
SWITCH POSITION TABLE
RL - R1 - R2
t+-
I
3V
I
tpLZ
-+J /+"
WAVEFORM1~-I~'~-U4I-I- ",3.5V
I
I
(See Note B)
'VOL
tpZH~
I
~
I
__
.r.
- . VOL
..J
tpHZ..,...
IA....
jJ.
Lo
.
3 V
.J[-VOH
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
WAVEFORM 2
IS.. Noto 8'
~~
:t-~.g~
~3t
I
_
___
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. THREE·STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR :5 10 MHz. Zo = 50 11. tr :5 2.5 ns.
tf :5 2.5 ns.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265
7-245
<
r~
~
CD
..<3
o
s:
D)
::::I
D)
(Q
CD
3
CD
::::I
r+
.
"'0
o
Co
c
..
(')
r+
tn
7-246
General Information
II.
Alternate Source Directories . .
Glossary /Timing Conventions/Data Sheet Structure
Dynamic RAMs
'B
Dynamic RAM Modules
EPROMs/PROMs/EEPROMs
VlSI Memory Management Products _
I
Military Products _
Applications Information
Quality and Reliability
Logic Symbols
Mechanical Data
ESD Guidelines
~
;:;'"
m
-<
."
~
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Co
c:
..
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r+
en
8-2
SMJ4161
65,536-8IT MULTIPORT VIDEO RAM
JUNE 1985 - REVISED FEBRUARY 1988
•
JD PACKAGE
MIL-STD-883C High-Reliability Processed
and - 55°C to 100°C (S Designator)
Temperature Range, 20-Pin 300-Mil Ceramic
Side brazed Package
•
Dual Accessibility - One Port Sequential
Access, One Port Random Access
•
Four Cascaded 64-Bit Serial Shift Registers
for Sequential Access Applications
Q
Designed for both Video and Non-Video
Applications
•
Fast Serial Port ... Can Be Configured for
Video Data Rates in Excess of 150 MHz
•
TR/QE as Output Enable Allows Direct
Connection of D, Q, and Address Lines to
Simplify System Design
•
Random-Access Port Looks Exactly Like a
SMJ4164
o
Separate Serial In and Serial Out to Allow
Simultaneous Shift In and Out
•
65,536 x 1 Organization
•
Supported by TI's Video System Controller
(VSC)
•
Maximum Access Time from RAS Less
Than 150 ns
•
Minimum Cycle Time (Read or Write) Less
Than 240 ns
•
Long Refresh Period ... 4 ms
o
Low Refresh Overhead Time ... As Low As
1.7% of Total Refresh Period
•
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
3-State Unlatched Outputs for Both Random
and Serial Access
•
Common 1/0 Capability with Early Write
Feature
•
Page-Mode Operation for Faster Access
•
Low Power Dissipation (SMJ4161-15)
- Operating ... 250 mW (Typical)
- Standby ... 80 mW (Typical)
•
New SMOS (Scaled-MOS) N-Channel
Technology
•
SOE Simplifies Multiplexing of Serial Data
Streams
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~8[~~I~~.i ~!~~~~ti~r :I~o::~:~:t:ros~s not
(TOP VIEW)
SIN
SCLK
SOE
D
IN
RAS
A6
A5
A4
VDD
VSS
SOUT
TR/QE
AO
A1
A2
A3
PIN NOMENCLATURE
AO-A7
Address Inputs
CAS
Column-Address Strobe
D
Random-Access Data In
Q
Random-Access Data Out
RAS
Row-Address Strobe
SCLK
Serial Data Clock
SIN
Serial Data In
SOE
Serial Output Enable
SOUT
Serial Data Out
ffi/QE
Register Transfer/Q Output Enable
VDD
5-V Supply
VSS
Ground
W
Write Enable
..
Copyright © 1985, Texas Instruments Incorporated
-I.!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-3
SMJ4161
65,536-8IT MULTIPORT VIDEO RAM
description
The SMJ4161 is a high-speed, dual-access 65,536-bit dynamic random-access memory. The randomaccess port makes the memory look like it is organized as 65,536 words of one bit each, like the SMJ4164.
The sequential access port is interfaced to an internal 256-bit dynamic shift register organized as four
cascaded 64-bit shift registers which makes the memory look like it is organized as up to 256 words of
up to 256 bits each which are accessed serially. One, two, three, or four 64-bit shift registers can be
sequentially read out after a transfer cycle, depending on a two-bit code applied to the two most significant
column address inputs. The SMJ4161 employs state-of-the-art SMOS (Scaled-MaS) N-channel doublelevel polysilicon gate technology for very high performance combined with low cost and improved reliability.
The SMJ4161 features full asynchronous dual access capability except when transferring data between
the shift register and the memory array.
Refresh period is extended to 4 milliseconds, and during this period each of the 256 rows must be strobed
with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power.
Note that the transfer of a row of data from the memory array to the shift register also refreshes that row.
All inputs and outputs, including clocks, are compatible with Series 54 TTL. All address lines and data
in are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The SMJ4161 is offered in a 20-pin ceramic dual-in-Iine package. It is guaranteed for operation from
TA = - 55°C to TC = 100°C. The dual-in-line package is designed for insertion in mounting-hole rows
on 7,62-mm (300-mil) centers.
random access address space to sequential address space mapping
The SMJ4161 is designed with each row divided into four, 64-column sections (see functional block
diagram). The first column section to be shifted out is selected by the two most significant column address
bits. If the two bits represent binary 00, then one to four registers can be shifted out in order. If the two
bits represent binary 01, then only 1 to 3 (the most significant) registers can be shifted out in order. If
the two bits represent binary 10, then one to two of the most significant registers can be shifted out in
order. Finally, if the two bits represent 11, only the most significant registers can be shifted out. All registers
are shifted out with the least significant bit (bit 0) first and the most significant bit (bit 63) last. Note that
if the two column address bits equal 00 during the last register transfer cycle (TR/QE at logic level 0 as
RAS falls) a total of 256 bits can be sequentially read out.
~
;::;:
m
-<
.o
."
c.
c
...nen
8-4
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ4161
65,536·8IT MULTIPORT VIDEO RAM
functional block diagram
TIMING & CONTROL
~
A5
A6
A7
DUMMY CELLS
RAO
AO
A1
A2
AJ
A4
ROW
ADDRESS RA7
BUFFERS
-------
r~
L-+-
'------+-
~
CA1
r-
~
COLUMN.
ADDRESS
BUFFERS .
CA6
~
--=::
-+-
....
(1/21
1 OF 256
ROW
DECODE
11/21 4 OF 256 COLUMN DECODE
SENSE
AMP
CONTROL
REFRESH
256 SENSE
AMPLIFIERS
11/21
1 OF 256
ROW
DECODE
11/21 MEMORY ARRAY
ts
Q
DUMMY CELLS
i
Y
r
CAO
CA1
<""2TRANSFER CONTROL
I
REGISTER
00
SCLK
S10F4
SELECTOR
11/21 4 OF 256 COLUMN DECODE
SIN
DATA
IN
REG
11/21 MEMORY ARRAY
I
<--;..
I
~?
REGISTER
REGISTER
01
10
I
REGISTER
11
1.I
1.
~
too'"., '"
COLUMN 128
I COLUMN
64
COLUMN 0
1 OF 4
SELECTOR
i1<--
SOUT
..
CA7J
CA6
random-access operation
TR/QE
The TR/QE pin has two functions. First, it selects either register transfer or random-access operation as
RAS falls, and second, if this is a random-access operation, it functions as an output enable after CAS falls.
To use the SMJ4161 in the random-access mode, TR/QE must be high as RAS falls. Holding TR/OE high
as RAS falls keeps the 256 elements of the shift registers disconnected from the corresponding 256 bit
lines of the memory array. If data is to be transferred, the shift registers must be connected to the bit
lines. Holding TR/QE low as RAS falls enables the 256 switches that connect the shift register to the bit lines
and indicates that a transfer will occur between the shift registers and one of the memory rows.
During random-access operation, once CAS has been pulled low, TR/QE controls when the data will appear
at the Q output (if this is a read cycle). Whenever TR/QE is held high during random-access operation,
the 0 output will be in the high-impedance state. This feature removes the possibility of an overlap between
data on the address lines and data appearing on the Q output, making it possible to connect the address
lines to the 0 and D lines (use of this organization prohibits the use of the early write cycle).
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
8-5
SMJ4161
65,536-8IT MULTIPORT VIDEO RAM
address (AO through A 7)
Sixteen address bits are required to decode 1 of 65,536 storage cell locations. Eight row-address bits are
set up on pins AO through A 7 and latched onto the chip by the row-address strobe (RAS). Then the eight
column-address bits are set up on pins AO through A 7 and latched onto the chip by the column-address
strobe (CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar
to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a
chip select activating the column decoder and the input and output buffers.
write enable (W)
The read or write mode is selected through the write enable (W) input. A logic high on the W input selects
the read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard
TTL circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When
W goes low prior to CAS, data out will remain in the high-impedance state for the entire cycle permitting
common I/O operation.
data in (0)
Data is written during a write or read-modify-write cycle. The falling edge of CAS or Vii strobes data into
the on-chip data latch. This latch can be driven from standard TTL circuits without a pull-up resistor. In
an early write cycle, Vii is brought low prior to CAS and the data is strobed in by CAS with setup and
hold times referenced to this signal. In a delayed write or read-modify-write cycle, CAS will already be
low, thus the data will be strobed in by Vii with setup and hold times referenced to this signal.
data out (0)
..
~
;;'
Q)
<""C
.
o
The three-state output buffer provides direct TTL compatability (no pull-up resistor required) with a fanout
of two Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance
(floating) state as long as CAS or TR/QE is held high. Data will not appear on the output until after both
CAS and TR/QE have been brought low. In a read cycle, the guaranteed maximum output enable access
time is valid only if tCQE is greater than tCQE MAX and tRLCL is greater than tRLCL MAX. Likewise, talC)
MAX is valid only if tRLCL is greater than tRLCL MAX. Once the output is valid, it will remain valid while
CAS and TR/QE are both low; CAS or TR/QE going high will return the output to a high-impedance
state. In an early write cycle, the output is always in a high-impedance state. In a delayed write or readmodify-write cycle, the output will follow the sequence for the read cycle. In a register transfer cycle,
the output will always be in a high-impedance state.
refresh
A refresh operation must be performed at least every four milliseconds to retain data. Since the output
buffer is in high-impedance state unless CAS is applied, the RAS-only refresh sequence avoids any output
during refresh. Strobing each of the 256 row addresses (AO through A 7) with RAS causes all bits in each
row to be refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power.
Co
c
...en
C')
page mode
Page~mode operation allows effectively faster memory access by keeping the same row address strobing
successive column addresses onto the chip. Thus, the time required to set up and strobe sequential row
addresses for the same page is eliminated. To extend beyond the 256 column locations on a single RAM,
the row address and RAS are applied to multiple 64K RAMs. CAS is then decoded to select the proper RAM.
power up
After power up, the power supply must remain at its steady-state value for 1 ms. In addition, RAS must
remain high for 100 JJ,s immediately prior to initialization . Initialization consists of performing eight RAS
cycles before proper device operation is achieved.
8-6
"'J}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
SMJ4161
65,536-81T MULTIPORT VIDEO RAM
sequential access operation
TR/QE
Memory transfer operations involving parallel use of the shift register are first indicated by bringing TR/OE
low before RAS falls low. This enables the switches connecting the 256 elements of the shift register
to the 256 bit lines of the memory array. The W line determines whether the data will be transferred from
or to the shift registers.
write enable (W)
In the sequential access mode, W determines whether a transfer will occur from the shift registers to the
memory array, or from the memory array to the shift registers. To transfer from the shift registers to the
memory array, W is held low as RAS falls, and, to transfer from the memory array to the shift registers,
W is held high as RAS falls. Thus, reads and writes are always with respect to the memory array. The
write setup and hold times are referenced to the falling edge of RAS for this mode of operation.
row address (AO through A 7)
Eight address bits are required to select one of the 256 possible rows involved in the transfer of data to
or from the shift registers. AO-A 7, W, and TR/OE are latched on the falling edge of RAS.
register column address (A 7, A6)
To select one of the four shift registers (transfer from memory to register only), the appropriate 2-bit column
address (A 7, A6) must be valid when CAS falls. However, the CAS and register address signals need not
be supplied every cycle, only when it is desired to change or select a new register.
SCLK
Data is shifted in and out on the rising edge of SCLK. This makes it possible to view the shift registers
as though they were made of 256 rising edge D flip-flops connected D to O. The SMJ4161 is designed
to work with a wide range duty cycle clock to simplify system design. Note that data will appear at the
SOUT pin not only on the rising edge of SCLK but also after an access time of ta(RSO) from RAS high during
a parallel load of the shift registers.
SIN and SOUT
..
Data is shifted in through the SIN pin and is shifted out through the SOUT pin. The SMJ4161 is designed
such that it requires 3 ns hold time on SIN as SCLK rises. SOUT is guaranteed not to change for at least
6 ns after SCLK rises. These features make it possible to easily connect SMJ4161 s together, to allow
SOUT to be connected to SIN, and to give external circuitry a full SCLK cycle time to allow manipulation
of the serial data. If SOUT is connected to SIN, the SCLK cycle time must include tsu(SI). When loading
data into the shift register from the serial input in preparation for a shift-register-to-memory transfer
operation, the serial clock must be clocked an even number of times. To guarantee proper serial clock
sequence after power up, a transfer cycle must be initiated before a serial data stream is applied at SIN.
SOE
The serial output enable pin controls the impedance of the serial output, allowing multiplexing of more
than one bank of SMJ4161 memories into the same external video circuitry. When SOE is at a logic low
level, SOUT will be enabled and the proper data read out. When SOE is at a logic high level, SOUT will
be disabled and be in the high-impedance state.
refresh
The shift registers are also dynamic storage elements. The data held in the registers will be lost unless
SCLK goes high to shift the data one bit position, a transfer write operation is invoked, or the data is reloaded
from the memory array. See specifications for maximum register data retention times.
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-7
SMJ4161
65,536-8IT MUL TIPORT VIDEO RAM
absolute maximum ratings over operating temperature range (unless otherwise noted) t
Voltage on any pin except VOO and data out (see Note 1). . . . . . . . . . . . . . . . . . .. - 1.5 V to 10 V
Voltage on VOO supply and data out with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 6 V
Short circuit output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Minimum operating free-air temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55 °C
Operating case temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 °C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 °C to 150 °C
tStress beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
VDD
Supply voltage
VSS
Supply voltage
VIH
High·level input voltage
VIL
Low·level input voltage (see Notes 2 and 3)
TA
Operating free-air temperature
TC
Operating case temperature
MIN
NOM
MAX
UNIT
4.75
5
0
5.25
V
2.4
-0.6
-55
V
VOO+O.3
V
0.8
V
100
°c
°c
NOTES: 2. The algebraic convention, where the more negative (less positive) limit is designated as maximum, is used in this data sheet
for logic voltage levels only.
3. Due to input protection circuitry, the applied voltage may begin to clamp at - 0.6 V; test conditions must comprehend this
occurrence .
..
~
;:+"
C)
-<
..,"'"
C
Co
c
....enn
8-8
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ4161
65,536-81T MULTIPORT VIDEO RAM
electrical characteristics over full range of recommended operating conditions (unless otherwise noted)
SMJ4161-15
PARAMETER
TEST CONDITIONS
High-level output
VOH
voltage
(a.
SOUT)
Low-level output
VOL
voltage
(a.
SOUT)
IOH
=
-5 mA
IOL
=
4.2 mA
VI
II
IOl
Input current (leakage)
MIN
Typt
MAX
2.4
VOO = 5 V.
Outputs = open
=
Va
Voo = 5 V
tc(rd) = minimum cycle time.
TRinE low after RAS falls. §
during read or write cycle
SMJ4161-20
MAX
UNIT
V
0.4
0.4
V
±10
±10
JlA
±10
±10
JlA
0 V to 5.8 V.
(a.
SOUT)
Typt
2.4
Output current (leakage)
Average operating current
1001
=
MIN
0.4 V to 5.5 V.
SCLK and SIN low.
50
75
45
75
mA
16
25
16
25
mA
42
60
37
60
mA
45
75
40
75
mA
SOE high.
a
No load on
and SOUT
After 1 - RAS cycle.
RAS and CAS high.
1002' Standby current
SCLK and SIN low.
SOE high.
a
No load on
=
tc(rd)
and SOUT
minimum cycle time.
CAS high. RAS cycling.
1003
Average refresh current
SCLK and SIN low.
SOE high.
TR/OE high.
a
No load on
tc(P)
=
RAS low.
1004
Average page-mode current
and SOUT
minimum cycle time.
CAS cycling.
TR/OE low after RAS falls.
SCLK and SIN low.
..
....CJ
U)
::::s
"C
...o
c.
...>-
SOE high.
a
No load on
Average shift register
1005
current (includes 1002)
Worst case average
1006
ORAM and shift
register current
and SOUT
RAS and CAS high.
a
No load on
and SOUT.
30
45
30
45
mA
85
100
85
100
mA
CO
:s
tc(SCLK) = tc(SCLK) min
tc(rd) = minimum cycle time.
tc(SCLK)
TR/N
=
minimum cycle time.
low after RAS falls.
No load on
a
~
and SOUT
t All typical values are at T A = 25°C and nominal supply voltages.
lSOUT output current (leakage) is guaranteed but not tested.
§See appropriate timing diagram.
'VIL > -0.6 V.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-9
SMJ4161
65,536-811 MULTIPORT VIDEO RAM
1 MHz
capacitance over recommended supply voltage and operating temperature range, f
Typt
PARAMETER
Ci(A)
Input capacitance, address inputs
4
Ci(D)
Input capacitance, data input
4
Ci(RC)
Input capacitance, strobe inputs
8
Ci(W)
Input capacitance, write enable input
8
Ci(CK)
Input capacitance, serial clock
8
Ci(SI)
Input capacitance, serial in
4
Ci(SOE)
Input capacitance, serial output enable
4
Ci(TR)
Input capacitance, register transfer input
4
Co(Q)
Output capacitance, random-access data
5
Co(SOUT)
Output capacitance, serial out
5
MAX
UNIT
pF
t All typical values are at T A = 25°C and nominal supply voltages.
switching characteristics over recommended supply voltage range and operating temperature range
(see Figure 1)
PARAMETER
ta(C)
ta(QE)
ta(R)
TEST CONDITIONS*
Access time from CAS
CL
Access time of Q from
IOL
TR/QE low
Access time from
ALT.
SYMBOL
= 80 pF,
= 4.2 mA,
tCAC
RAS
tRLCL = max,
CL = 80 pF,
IOL
tRAC
= 4.2 mA,
= -5 mA
SOUT access time from
RAS high
Access time from SOE
ta(SOE)
~
~
ta(SO)
tdis(CH)
-<
..o-a
tdis(QE)
Access time from SCLK
C
tdis(SOE)
from CAS high
= 80 pF,
IOL = 4.2 mA,
CL
IOH = -5 mA
tOFF
Q output disable time
from TR/QE high
Serial output disable time
Co
C')
c:
low to SOUT
Q output disable time
D)
from SOE high
tFigure 1 shows the load circuit; CL values shown are typical for test system used.
8-10
MIN
MAX
SMJ4161-20
MIN
MAX
100
135
40
50
150
200
65
85
UNIT
IOH = -5 mA
IOH
ta(RSO)
SMJ4161-15
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
45
50
45
55
40
40
30
40
20
25
ns
SMJ4161
65,536·81T MULTIPORT VIDEO RAM
timing requirements over recommended supply voltage range and operating temperature range
ALT.
PARAMETER
SMJ4161-15
MAX
SMJ4161-20
MIN
MAX
UNIT
SYMBOL
MIN
tc(P)
Page-mode cycle time
tpc
160
225
ns
tc(rd)
Read cycle time t
tRC
240
315
ns
tc(WI
Write cycle time
twc
240
315
ns
tc(TW)
Transfer write cycle timet
240
315
ns
tc(Trd)
Transfer read cycle time
240
315
ns
tc(rdW)
Read-write/read-modify-write cycle time
tRWC
265
tc(SCLK)
Serial clock cycle time (see Note 4)
tscc
45
tw(CH)
Pulse duration,
tcp
50
tw(CL)
Pulse duration,
CAS high (precharge time) §
CAS low'
'R'AS high (precharge time)
tw(RH)
Pulse duration,
twiRL)
Pulse duration, RAS low#
tw(W)
Write pulse duration
tCAS
100
tRP
80
tRAS
twp
150
ns
330
50,000
55
50,000
ns
10,000
ns
ns
80
10,000
135
10,000
200
105
ns
10,000
ns
45
45
ns
tw(CKL)
Pulse duration, SCLK low ll
20
20
ns
tw(CKH)
Pulse duration, SCLK high ll
20
20
ns
tw(OE)
TR/QE pulse duration low time (read cycle)
50
50
ns
tsu(CA)
Column address setup time
tASC
0
0
ns
tsu(RA)
Row address setup time
tASR
0
0
ns
ns
W setup time before RAS low
tsu(RW)
0
0
tDS
0
0
ns
tRCS
5
5
ns
twcs
-5
-5
ns
with ffi/OE low
tsu(D)
Data setup time
tsu(rd)
Read command setup time
Early write command setup time
tsu(WCL)
before CAS low
tsu(WCH)
Write command setup time before CAS high
tCWL
40
60
ns
tsu(WRH)
Write command setup time before RAS high
tRWL
40
60
ns
tsu(TR)
TR/OE setup time before RAS low
5
5
ns
tsu(SI)
Serial data setup time before SCLK high
6
6
ns
th(SI)
Serial data in hold time after SCLK high
3
3
ns
th(CLCA)
Column address hold time after CAS low
tCAH
45
55
ns
th(RA)
Row address hold time
tRAH
20
25
ns
30
30
ns
95
120
ns
th(RW)
W hold time after RAS low with TR/OE low
thfRLCAI
Column address hold time after
'R'AS
low
tAR
-
...
(I)
(J
::::s
..
"C
o
c..
~
CO
~
~
Continued next page.
NOTES: 4. tc(SCLK) min is tested by connecting SIN to SOUT and test conditions include tsu(SI); see paragraph entitled SIN and SOUT
on page 5.
5. Timing measurements are made at the 10% and 90% points of input and clock transitions. In addition, VIL max and VIH min
must be met at the 10% and 90% points.
6. System transition times (rise and fall) for RAS, CAS. and SCLK are to be a minimum of 3 ns and a maximum of 50 ns.
t All cycle times assume tt = 5 ns except tc(SCLK) which assumes tt = 3 ns.
+Multiple transfer write cycles require separation by either a 1-/Ls RAS-precharge interval or any other active RAS-cycle.
§Page-mode only.
, In a read-modify-write cycle, tCLWL and tsu(WCH) must be observed. Depending on the user's transition times, this may require additional
CAS low time (tW(CL)). This applies to page-mode read-modify-write also.
#In a read-modify-write cycle, tRLWL and tsu(WRH) must be observed. Depending on the user's transition times, this may require additional
. RAS low time (tw(RL)).
II This parameter is guaranteed but not tested.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-11
SMJ4161
65,536-81T MULTIPORT VIDEO RAM
timing requirements over recommended supply voltage range and operating temperature range
(concluded)
ALT.
PARAMETER
SYMBOL
th(CLD)
Data hold time after CAS low
th(RLD)
Data hold time after RAS low
th(WLD)
Data hold time after W low
th(CHrd)
Read command hold time after CAS high
MIN
SMJ4161-20
MAX
MIN
MAX
UNIT
tDH
60
80
ns
tDHR
110
145
ns
tDH
45
55
ns
tRCH
0
0
ns
th(RHrd)
Read command hold time after
RAS
high
tRRH
5
5
ns
th(CLW)
Write command hold time after
CAS low
tWCH
60
80
ns
th(RLW)
Write command hold time after
RAS
tWCR
110
145
ns
th(RSO)
Serial data out hold time after
RAS low with TR/OE low ll
30
30
ns
th(SO)
Serial data out hold time after SCLK high
6
6
ns
th(TR)
TR/OE hold time after RAS low (tansfer)
40
40
ns
tRLCH
Delay time, RAS low to CAS high
tCSH
150
200
ns
tCHRL
Delay time, CAS high to RAS low
tCRP
0
0
ns
tCLOEH
Delay time CAS low to OE high
100
135
ns
tCLRH
Delay time, CAS low to RAS high
tRSH
100
135
ns
tCWD
65
75
ns
low
Delay time, CAS low to W low
tCLWL
..
SMJ4161-15
(read·modify-write cycle only)
Delay time, CAS low to OE low
tCOE
(maximum value specified only
60
85
ns
to guarantee ta(OE) access time)
tRHSC
Delay time, RAS high to SCLK high
80
Delay time, RAS low to CAS low (maximum
tRLCL
~
value specified only to guarantee access time)
tRCD
25
tRWD
135
150
ns
10
10
ns
Delay time, RAS low to W low
tRLWL
;;'
c
(read-modify-write cycle only)
ns
80
Delay time, SCLK high before
50
30
65
ns
-<
tCKRL
trf(MA)
Refresh time interval, memory array
tREF1
4
4
ms
o
trf(SR)
Refresh time interval, shift register O
tREF2
50,000
50,000
ns
"c....
C
S
en
RAS low with TR/OE low *
NOTE 5: Timing measurements are made at the 10% and 90% points of input and clock transitions. In addition, VIL max and VIH min
must be met at the 10% and 90% points.
II This parameter is guaranteed but not tested.
*SCLK may be high or low during tw(RL), but there cannot be any positive edge transitions on SLCK for a minimum of 10 ns prior to
RAS going low with TR/OE low (i.e., before a transfer cycle).
OSee "refresh" on page 5.
8-12
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ4161
65,536·8IT MULTIPORT VIDEO RAM
PARAMETER MEASUREMENT INFORMATION
v
OUTPUT
UNDER TEST
-sf
1"
IOH/IOL
CL = 80 pF
FIGURE 1. EQUIVALENT LOAD CIRCUIT
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
8-13
SMJ4161
65,536-8IT MULTIPaRT VIDEO RAM
read cycle timing
~
__
~I'dl
twiRL!
--1 r-
tt
,-
~ tRLCL
I ,-
"I_
tCLRH-------t
tCHRL-----,.f
i~tt
~-I--tW-(CHI-----;~~-
'N-
'I'
I r
.....--t-I--
II
th(RLCAI
.. ,
"
,.-..tth(RAI
'~tcLaEH~
tsU
(CAI
:
I II
AO-A7
-,
II
I
1
I
1
~
!
W
tsu(rdl
~
I
1
.
1
I"
,
I
."
o
c.
,-
I
I
-<
I ~ j4- t h(RHrdl
I
I
C»
a
....
en
I ..,
th(CHrdl
, I
I I
j--tcaE--.j
ta(aEI~
I - - - ta(CI--1
c:::
,
th(TRIU
::+
C')
.,
I,
ID; ROW ~ COLUMN mD;fC~E:XXX,-______
,,
Ir
"I
II
=1 ~tsu(TRI II
j.,! I
y;J : \ \:: \ 'ttwIQElf4r-:-Z-r--Z""'7"--:Z,.....---.,:\-\~\
I
th(CLCAI
..
_ __
.. "
I
~ ~t'"'RAI
~\.-
LtW(RHI-----l
tw(CLI-----i ,-
tRLCH
II
~
I
~tdiS(aEI-1
r--tdiS(CHI~
---~!-----------«~--_V_AL-ID--"""'~
...- - - - - -
.1-- - - - t a ( R I - - - - - ....'
8-14
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
~::
SMJ4161
65,536-8IT MULTIPORT VIDEO RAM
early write cycle timing
_~~
--,
I
!
'wlRl)
j4-tt
\.
III
-,
I
I I ~th(RLCAI
D\
II
I I! i --.( ~tsu(CAI
7\l\f=1~"
~
iii
-of
ROW
II
r:-
I :"
M
COLUMN
I
tsu(TRI
•
I III
I
I
__
---J ,
j...:...-.-tCHRL----.I
I ,
}fIr---:- - - -.. .\. ___
I I
th(RAI~
~""'--
--1 I-j- tt
X
I
AO-A7
_, I+--tw(RHI
tw(CLI~
tRLCH
I
~',"IRAI
I
tCLRH
-I-
r--tRLCL
~
',IWI
1 4 , _ - - - tW (CHI----ot.'
\
I
I
I
I
\
.
nx»e·ccBO<""
_____
I
.
I
------1
I
-rth(CLCAI
tsu(WCHI
~',"IWRHI
"I
-
\'----
TR/QE
VOH
Q
---------------HI-Z-------------VOL
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75~65
8-15
SMJ4161
65,536-8IT MULTIPORT VIDEO RAM
write cycle timing
l
14l11- - - - - - - - - - - tC ( W I - - - - - - - - - - - - . ! . 1
====~~~~_tw_(R_LI=====~~~~:;tIr------!ill
I
t\r-I4-.
tt---+
I
I~
·1
..
lII~----tCLRH-----... lr---tw(RHI~
~tRLCL----'"
1I
I
1
1
I ,..l I I - - - - - - - t R L c H - - - - - - -....·Il.:--tcHRL----..j
~ ~''"'RAI "l\t14--III
I
I
th(RAI-i--
I
II
t--- th(RLCAI I
f.-.t
!1
I
--I
j{!
t
W ( C L I - - -.....
I ..
~--tw(CHI
'I
tt ~ -....., . - - - - - - t c L Q E H - - - l I I - I.....I~~
..
~ tsu(CAI
I
~II
1
II
AO-A7
----1
iY
th(TRI
",ce
t..tsu(TRI
:.
I
1\\ \
1111
'I th(CLCAI
1
I II 1
t\\ S~'WIQElim17ZZ7
I
I
~
~
I
1111
1111
I
tsu(WCHI~
tsu(WRHI
II I
I
I
.-
llII-------+--th(RLWI.
...
,I
1
,.---t--th(CLWI----....-i'
..
1
m
I:
~)()()OO~"""'X"'"D.e·D-c&~O<>CD*NJ&~-----
.F-----------~¥
VOH
VOL
-I
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-17
sJ3npOJd AleJ!I!1III
cp
-x-
-"
CD
RAS
I ,.
I.I
I
tt
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~
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
8-21
SMJ4161
65,536-8IT MULTIPORT VIDEO RAM
shift register to memory timing
-
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NOTES: 11. The shift register to memory cycle is used to transfer data from the shift register to the memory array. Everyone of the 256
locations in the shift register is written into the 256 columns of the selected row. Note that the data that was in the shift
register may have resulted either from a serial shift in or from a parallel load of the shift register from one of the memory rows.
12. SOE assumed low.
13. SCLK may be high or low during twIRL)'
14. Multiple transfer write cycles require either a 1-p.s RAS-precharge interval or any other active RAS cycle before initiation of
the transfer write cycles and separation between any two consecutive transfer write cycles.
8-22
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
SMJ4161
65,536·81T MULTIPORT VIDEO RAM
memory to shift register timing
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13. SCLK may be high or low during twIRL)'
14. Multiple transfer write cycles require either a 500-ns RAS-precharge interval or any other active RAS cycle before initiation
of the transfer write cycles and separation between any two consecutive transfer write cycles.
15. The memory to shift register cycle is used to load the shift register in parallel from the memory array. Everyone of the 256
locations in the shift register are written into from the 256 columns of the selected row. Note that the data that is loaded
into the shift register may be either shifted out or written back into another row.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-23
SMJ4161
65,536-8IT MULTIPORT VIDEO RAM
serial data shift timing
I_
SCLK
-I
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4. tc(SCLK) min is tested by connecting SIN to SOUT and test conditions include tsU(SI); see paragraph entitled SIN and SOUT
on page 5.
16. While shifting data through the serial shift register, the state of TR/QE is a don't care as long as TR/QE is held high when
RAS goes low and tsu(TR) and th(TR) timings are observed. This requirement avoids the initiation of a register-to-memory
or memory-to-register data transfer operation. The serial data transfer cycle is used to shift data in andlor out of the shift register.
17. When loading data into the shift register from the serial input in preparation for a shift-register-to-memory transfer operation,
the serial clock must be clocked an even number of times .
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8-24
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
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1001
1003
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100
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IN
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o
Q
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Common I/O Capability with Early Write
Feature
NC
NC
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A3
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A2
A4
8 9 1D 11
o Low Power Dissipation
-Operating ... 125 mW (Typ)
-Standby ... 17.5 mW (Typ)
o
Performance Ranges:
..
PIN NOMENCLATURE
ACCESS
ACCESS
READ
READ-
TIME
TIME
OR
MODIFY-
ROW
COLUMN
WRITE
ADDRESS ADDRESS
(MAX)
(MAX)
AO-A 7
Address Inputs
CAS
Column-Address Strobe
WRITE
D
Data In
CYCLE
(MIN)
CYCLE
(MIN)
NC
Q
No Connection
Data Out
'4164-12
120 ns
70 ns
230 ns
260 ns
RAS
Row-Address Strobe
'4164-15
150 ns
85 ns
260 ns
285 ns
VDD
5-V Supply
'4164-20
200 ns
135 ns
326 ns
345 ns
o SMOS (Scaled-MOS) N-Channel Technology
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W
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description
The SMJ4164 is a Military high-speed, 65,536-bit, dynamic random-access memory, organized as 65,536
words of one bit each. It employs state-of-the-art SMOS (scaled MOS) N-channel double-level polysilicon
gate technology for very high performance combined with low cost and improved reliability.
The SMJ4164 features RAS access times of 120 ns, 150 ns, and 200 ns maximum. Power dissipation is
125 mW typical operating and 17.5 mW typical standby.
PRODUCTION DATA documents contain informetion
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
neceSlarily include testing of all parameters.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright © 1985, Texas Instruments Incorporated
8-29
SMJ4164
65,536·81T DYNAMIC RANDOM·ACCESS MEMORY
Refresh period is extended to 4 milliseconds, and during this period each of the 256 rows must be strobed
with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power.
All inputs and outputs, including clocks, are compatible with Series 54/74 TTL. All address lines and data
in are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
Pin 1 has no internal connection to allow compatibility with other 64K RAMs that use this pin for an additional
function.
The SMJ4164 is offered in a 16-pin dual-in-line ceramic side braze package (JD suffix) and in a lead less
ceramic chip carrier package (FG suffix). The JD package is designed for insertion in mounting-hole rows
on 7,62-mm (300-mil) centers, whereas the FG package is intended for surface mounting on solder lands
on 1,27-mm (0.050-inch) centers. The FG package is a three-layer, 18-pad, rectangular ceramic chip carrier
with dimensions of 7,37 x 10,8 x 1,65 mm (0.290 x 0.425 x 0.065 inches).
operation
address (AO through A 7)
Sixteen address bits are required to decode 1 of 65,536 storage cell locations. Eight row-address bits are
set up on pins AO through A 7 and latched onto the chip by the row-address strobe (RAS). Then the
eight column-address bits are set up on pins AO through A 7 and latched onto the chip by the columnaddress strobe (CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS
is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used
as a chip select activating the column decoder and the input and output buffers.
write enable (W)
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The read or write mode is selected through the write-enable (iii! input. A logic high on the W input selects
the read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard
TTL circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When
W goes low prior to CAS, data-out will remain in the high-impedance state for the entire cycle, permitting
common I/O operation.
data in (0)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling
edge of CAS or W strobes data into the on-chip data latch. This latch can be driven from standard TTL
circuits without a pull-up resistor. In an early write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed write or read-modifywrite cycle, CAS will already be low, thus the data will be strobed in by W with setup and hold times
referenced to this signal.
data out (Q)
rn
The three-state output buffer provides direct TTL compatibility (no pull-up resistor required) with a fanout
of two Series 54/74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance
(floating) state until CAS is brought low. In a read cycle the output goes active after the access time interval
talC) that begins with the negative transition of CAS as long as ta(R) is satisfied. The output becomes
valid after the access time has elapsed and remains valid while CAS is low; CAS going high returns
it to a high-impedance state. In an early write cycle, the output is always in the high-impedance state.
In a delayed-write or read-modify-write cycle, the output will follow the sequence for the read cycle.
refresh
A refresh operation must be performed at least every four milliseconds to retain data. Since the output
buffer is in the high-impedance state unless CAS is applied, the RAS-only refresh sequence avoids
any output during refresh. Strobing each of the 256 row addresses (AO through A 7) with RAS
causes all bits in each row to be refreshed. CAS can remain high (inactive) for this refresh sequence to
conserve power.
8-30
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ4164
65,536·8IT DYNAMIC RANDOM·ACCESS MEMORY
page mode
Page-mode operation allows effectively faster memory access by keeping the same row address and strobing
successive column addresses onto the chip. Thus, the time required to set up and strobe sequential row
addresses for the same page is eliminated. To extend beyond the 256 column locations on a single RAM,
the row address and RAS are applied to multiple 64K RAMs. CAS is then decoded to select the proper RAM.
power up
After power up, the power supply must remain at its steady-state value for 1 ms. In addition, RAS must
remain high for 100 p.s immediately prior to initialization. Initialization consists of performing eight RAS
cycles before proper device operation is achieved.
logic symbol t
RAM 64K X 1
(51
AO ....;.;;.=-------1 2008/21 DO
(71
A1
A2
A3
A4
A5
A6
A7
RAS
CAS
W
(61
(121
o
A-65.535
(111
(101
(131
(91
..
(41
(151
23C22
(31
(21
0 - - - - - I A.220
(141
A'\lJ.----
Q
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
Pin numbers shown are for the dual-in-line package.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-31
SMJ4164
65,536-BIT DYNAMIC RANDOM-ACCESS MEMORY
functional block diagram
RAS=3
CAS
W
~
TIMING & CONTROL
____________________
~
0
A7
A6
r<~
A5
ROW
I-r<~
ADDRESS
BUFFERS
(B)
A4
A3
A2
Al
ROW
DECODE
(112 MEMORY ARRAY)
IN
REG
AO
(112) 4 OF 256 COLUMN DECODE
SENSE
AMP
CONTR.
L--
(112) 4 OF 256 COLUMN DECODE
COLUMN
ADDRESS
BUFFERS
i---f-
256 SENSE - REFRESH
AMPS
L.--
'---
qJ
I/O
IIO~ ;:::
f--~
BUFFER &
1 OF 4110
SElECTION
~
OUT
REG.
Q
~
L..
(8)
~
-
ROW
DECODE
(112) MEMORY ARRAY
AO-A7
~
~.
absolute maximum ratings over operating temperature range (unless otherwise noted) t
...
D)
Voltage on any pin except VDD and data out (see Note 1). . . . . . . . . . . . . . . . . . .. - 1.5 V to 10 V
Voltage on VDD supply and data out with respect to VSS ....................... - 1 V to 6 V
Short circuit output current; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Minimum operating free-air temperature: S version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55°C
L version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C
Operating case temperature: S version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 110°C
L version. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
<
...
."
oQ.
r::::
aen
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only. and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
8~32
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
SMJ4164
65,536-BIT DYNAMIC RANDOM-ACCESS MEMORY
recommended operating conditions
S VERSION
MIN
VOO
Supply voltage
VSS
Supply voltage
VIH
VIL
High-level input voltage
TA
Operating free-air temperature
TC
Operating case temperature
L VERSION
NOM
MAX
MIN
5
5.5
4.5
4.5
MAX
5
5.5
0
0
Low-level input voltage (see Notes 3 and 4)
NOM
UNIT
V
V
2.4
VCC+ 0 .3
2.4
VCC+O.3
-0.6
-55
0.8
-0.6
0.8
V
DC
70
DC
0
110
V
NOTES: 2. The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet
for logic voltage levels only.
3. Oue to input protection circuitry, the applied voltage may begin to clamp at - 0.6 V. Test conditions must comprehend this
occurrence.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
CONOITIONS
-5 rnA
10H =
10L = 4.2 rnA
VI = 0 V to 5.8 V,
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
VOO = 5 V,
CAS high
Average operating current
tc
during read or write cycle
All outputs open
TYpt
= 0.4 V
SMJ4164-15
MAX
2.4
VOO = 5.5 V
All outputs open
Vo
1001:/:
SMJ4164-12
MIN
MIN
2.4
Typt
UNIT
MAX
V
0.4
0.4
V
±10
±10
p.A
±10
±10
p.A
to 5.5 V,
= minimum cycle,
40
48
35
45
rnA
3.5
5
3.5
5
rnA
After 1 memory cycle,
1002§
Standby current
RAS and CAS high,
..
....
U)
C.)
All outputs open
tc
1003:/:
Average refresh current
= minimum
:::s
..
..
cycle,
CAS high and RAS cycling,
"C
28
40
25
37
rnA
28
40
25
37
rnA
o
c..
All outputs open
1004
Average page-mode current
tc(P) = minimum cycle,
RAS low and CAS cycling,
All outputs open
>-
ca
~
~
t All typical values are at TC = 25°C and nominal supply voltages.
:/: Additional information on last page of data sheet.
§VIL § -0.6 V.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-33
SMJ4164
65.536-811 DYNAMIC RANDOM-ACCESS MEMORY
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
=
= 4.2 mA
VI = 0 V to 5.8
VOO = 5.5 V.
Output = open
-5 mA
10H
10L
SMJ4164-20
MIN
Typt
MAX
2.4
UNIT
V
0.4
V
±10
/LA
±10
/LA
27
37
mA
3.5
5
mA
20
32
mA
20
32
mA
V,
Vo = 0.4 V to 5.5 V,
VOO
=
5 V,
CAS high
1001 i
= minimum
Average operating current
tc
during read or write cycle
All outputs open
cycle
After 1 memory cycle,
1002§
Standby current
RAS and CAS high,
All outputs open
tc
1003 i
Average refresh current
= minimum cycle,
CAS high and RAS cycling,
All outputs open
tc(P)
.o
1004
Average page-mode current
= minimum
RAS low and
-0
All outputs open
c.
t All typical values are at TC = 25 DC and nominal supply voltages.
iAdditional information on last page of data sheet.
§VIL > - 0.6 V.
c
n
,..
cycle,
'CAS cycling,
en
. . capacitance over recommended supply voltage range and recommended temparature range. f
SMJ4164
PARAMETER
UNIT
Typt
MAX
Ci(A)
Input capacitance, address inputs
pF
Input capacitance, data input
4
4
7
Cj(O)
7
pF
Cj(RC)
Input capacitance, strobe inputs
8
10
pF
Cj(W)
Input capacitance, write enable input
8
10
pF
Co
Output capacitance
5
8
pF
t All typical values are at TC = 25 DC and nominal supply voltages.
'These parameters are guaranteed but not tested.
8-34
= 1 MHz'
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ4164
65,536-8IT DYNAMIC RANDOM-ACCESS MEMORY
switching characteristics over recommended supply voltage range and recommended operating
temperature range
PARAMETER
ta(C)
ta(R)
tdis(CH)
Access time from CAS
CL
=
Output disable time
CL = 80 pF,
"CAS high
see Figure 1
=
MAX,
MIN
MAX
SMJ4164-15
MIN
85
ns
tRAC
120
150
ns
40
ns
0
ALT.
SYMBOL
40
0
SMJ4164-20
MIN
CL = 80 pF,
ta(R)
Access time from RAS
CL = 80 pF, tRLCL
see Figure 1
Output disable time
CL = 80 pF,
after CAS high
see Figure 1
see Figure 1
=
MAX,
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
MAX
UNIT
tCAC
135
ns
tRAC
200
ns
50
ns
tOFF
TEXAS
UNIT
70
TEST CONDITIONS
Access time from CAS
MAX
tCAC
tOFF
ta(C)
tdis(CH)
SMJ4164-12
80 pF,
Access time from RAS
PARAMETER
SYMBOL
see Figure 1
CL = 80 pF, tRLCL
see Figure 1
after
ALT.
TEST CONDITIONS
0
8-35
SMJ4164
65,536-811 DYNAMIC RANDOM-ACCESS MEMORY
timing requirements over recommended supply voltage range and recommended operating temperature
range
ALT.
PARAMETER
SYMBOL
SMJ4164-12
MIN
MAX
SMJ4164-15
MIN
MAX
UNIT
tc(P)
Page-mode cycle time
tpc
130
160
tc(rd)
Read cycle time t
tRC
230
260
ns
tc(W)
Write cycle time
twc
230
260
ns
tc(rdW)
Read-write/read-modify-write cycle time
tRWC
ns
tw(CH)
Pulse duration,
tw(CL)
Pulse duration,
tw(RH)
Pulse duration, fiAS high (precharge time)
tWIRL)
tw(W)
Pulse duration,
ns
260
285
tcp
50
50
tCAS
70
tRP
80
120
Write pulse duration
tRAS
twp
40
45
tsu(CA)
Column-address setup time
tASC
-5
-5
ns
tsu(RA)
Row·address setup time
tASR
0
0
ns
CAS high (precharge
CAS low§
RAS
time):t
low'
10,000
85
ns
10,000
100
10,000
150
ns
ns
10,000
ns
ns
tsu(D)
Data setup time
tDS
0
0
ns
tsu(rd)
Read-command setup time
tRCS
0
0
ns
tsu(WCH)
Write-command setup time before ~ high
tCWL
50
50
ns
tsu(WRH)
Write-command setup time before
tRWL
50
50
ns
th(CLCA)
Column-address hold time after CAS low
tCAH
40
45
ns
th(RA)
Row-address hold time
tRAH
15
20
ns
th(RLCA)
Column-address hold time after RAS low
tAR
85
95
ns
th(CLD)
Data hold time after
tDHC
40
45
ns
th(RLD)
Data hold time
tDHR
85
95
ns
RAS
high
CAS low
after RAS low
after W low
th(WLD)
Data hold time
tDHW
40
45
ns
th(CHrd)
Read-command hold time after ~ high"
tRCH
0
0
ns
th(RHrd)
Read-command hold time after RAS high"
tRRH
5
5
ns
~
th(CLW)
Write-command hold time after
tWCH
40
45
ns
th(RLW)
Write-command hold time
tWCR
85
95
ns
D)
tRLCH
Delay time,
tCSH
120
150
ns
tCHRL
Delay time, ~ high to
low
tCRP
0
0
ns
tCLRH
Delay time, ~ low to RAS high
tRSH
70
85
ns
~.
~
.
"'C
o
Co
~
..
(/)
RAS
CAS low
after RAS low
low to CAS high
RAS
Continued next page.
NOTE 4: Timing measurements are made at the 10% and 90% points of input and clock transitions. In addition, VIL max and VIH min
must be met at the 10% and 90% points.
t All cycle times assume tt = 5 ns. The recommended rise and fall times for the CAS and RAS inputs are a minimum of 3 ns and a maximum
of 50 ns.
:tpage-mode only.
§In a read-modify-write cycle, tCLWL and tsu(WCH) must be observed. Depending on the user's transition times, this may require additional
CAS low time (tw(CL))' This applies to page-mode read-modify-write also.
'In a read-modify-write cycle, tRLWL and tsu(WRH) must be observed. Depending on the user's transition times, this may require additional
RAS low time (tw(RL))'
I These parameters are guaranteed but not tested.
8-36
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
SMJ4164
65,536·81T DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and recommended operating temperature
range (continued)
ALT.
PARAMETER
MIN
Delay time, CAS low to W low
tCLWL
(read-modify-write cycle only)
SMJ4164-15
SMJ4164-12
SYMBOL
tCWD
40
tRCD
15
tRWD
85
twcs
-5
MAX
MIN
MAX
60
UNIT
ns
Delay time, RAS low to CAS low
tRLCL
(maximum value specified only
45
20
50
ns
to guarantee access time)
Delay time, RAS low to W low
tRLWL
(read-modify-write cycle only)
Delay time, W low to CAS
tWLCL
trf
low (early write cycle)
Refresh time interval
100
ns
-5
ns
4
tREF
4
ms
timing requirements over recommended supply voltage range and recommended operating temperature
range (continued)
ALT.
PARAMETER
SMJ4164-20
MAX
UNIT
SYMBOL
MIN
tc(P)
Page-mode cycle time
tpc
225
ns
tc(rd)
Read cycle time t
tRC
330
ns
tc(W)
Write cycle time
twc
330
ns
tc(rdW)
Read-write/read-modify-write cycle time
tRWC
345
ns
tw(CH)
Pulse duration, ~ high (precharge time) i
tw(CL)
Pulse duration,
tw(RH)
twIRL)
Pulse duration,
tw(W)
tcp
80
tCAS
135
Pulse duration, RAS high (precharge time)
tRP
120
RAS low'
200
Write pulse duration
tRAS
twp
55
ns
ns
'CA'S
low §
ns
ns
10,000
ns
tsu(CA)
Column-address setup time
tASC
-5
tsu(RA)
Row-address setup time
tASR
0
ns
tsu(D)
Data setup time
tDS
0
ns
tsu(rd)
Read-command setup time
tRCS
0
ns
tsu(WCH)
Write-command setup time before CAS high
tCWL
80
ns
tsu(WRH)
Write-command setup time before RAS high
tRWL
80
ns
th(CLCA)
Column-address hold time after CAS low
tCAH
55
ns
th(RA)
Row-address hold time
tRAH
25
ns
th(RLCA)
Column-address hold time after RAS low
tAR
140
ns
th(CLD)
Data hold time after CAS low
tDHC
80
ns
th(RLD)
Data hold time after
tDHR
145
ns
RAS
low
..
ns
10,000
Continued next page.
NOTE 4: Timing measurements are made at the 10% and 90% points of input and clock transitions. In addition, VIL max and VIH min
must be met at the 10% and 90% points.
t All cycle times assume tt = 5 ns. The recommended rise and fall times for the CAS and RAS inputs are a minimum of 3 ns and a maximum
of 50 ns.
ipage-mode only.
§In a read-modify-write cycle, tCLWL and tsu(WCH) must be observed. Depending on the user's transition times, this may require additional
CAS low time (tw(CL))' This applies to page-mode read-modify-write also.
, In a read-modify-write cycle, tRLWL and tsu(WRH) must be observed. Depending on the user's transition times, this may require additional
RAS low time (tw(RL)).
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-37
SMJ4164
65,536·811 DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and recommended operating temperature
range (concluded)
ALT.
PARAMETERS
SYMBOL
SMJ4164-20
MIN
MAX
UNIT
th(WLD)
Data hold time after W low
tDHW
55
ns
th(CHrd)
tRCH
0
ns
tRRH
5
ns
th(CLW)
CAS high"
Read-command hold time after RAS high"
Write:command hold time after CAS low
tWCH
80
ns
th(RLW)
Write-command hold time after RAS low
tWCR
145
ns
tRLCH
Delay time.
low to CAS high
tCSH
200
ns
tCHRL
Delay time. CAS high to RAS low
tCRP
0
ns
Delay time. CAS low to RAS high
tRSH
135
ns
tCWD
65
ns
tRCD
25
tRWD
130
ns
twcs
-5
ns
th(RHrd)
tCLRH
Read-command hold time after
RAS
Delay time. CAS low to W low
tCLWL
(read-modify-write cycle only)
Delay time. RAS low to CAS low
tRLCL
(maximum value specified only
65
ns
to guarantee access time)
Delay time. RAS low to W low
tRLWL
(read-modify-write cycle only)
Delay time. W low to CAS
tWLCL
trf
low (early write cycle)
Refresh time interval
tREF
"These parameters are guaranteed but not tested.
~
::i-'
D)
-<
.
"a
o
c.
c
,..n
en
8-38
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4
ms
SMJ4164
65,536·811 DYNAMIC RANDOM·ACCESS MEMORY
PARAMETER MEASUREMENT INFORMATION
1.31 V
OUTPUT
UNDER
TEST
-JI
RL
CL
FIGURE 1. LOAD CIRCUIT
read cycle timing
\.
.j
tc(rd)
I
RAS ,
~tCLRH~
\.-tt
I j4- tRLCL ~ tw(CL)---.t
I.
4
I
~
I I
I
I
II
I
I
i~
L
-1
I
I
I
I
sulrd)
II
r---r- th(CLCA)
~t
~
I
I
t--- talC) ---+J
I
\
I..
HI-2
talR)
¢::
..
...rn
CJ
::s
NEXT CYCLE
I
VIL
"C
VIH
...>CO
o...
c.
it+--t-I th(RHrd)
I.
-1
th(CHrd)
~
\)ik~t~!~i~~~m
I
I
----1--
I
:II~
I
I
~ COLUMN~_
I --J
Q
~tw(CH)----..j
1
I I --.../ I4j- tsu(CA)
~
W
-f7i-J;r---:----~~
I I.-- th(RLC~)I~
th(RA)--j
AO-A7
~
!
I
~ !+-+tt
I
I
~tsu(RA)
I--tw(RH)---i
~ tCHRL--t
.1 I
tRLCH
1I
t----
~
twiRl]
---i
I
I
~
~
VIL
I
t41·--~~
VALID
tdis(CH)
~>-------
.j
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 2250,2 • DALLAS. TEXAS 75265
8-39
SMJ4164
65,536-BIT DYNAMIC RANDOM-ACCESS MEMORY
early write cycle timing
,-
tc(W)
I
II-
RAS
twIRL)
~
tCLRH
~
~.
Q)
-<
.o
"'C
Co
c:
...
en
(')
Q
8-40
-----------HI-Z - - - - - - - - - - - - -
TEXAS
-1.!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
VOH
SMJ4164
65,536·811 DYNAMIC RANDOM·ACCESS MEMORY
write cycle timing
D
I
I
I
I I
I
r--
tw(W)--t
t--th(WLD)..j
I
I4f-- th(CLD) ---t
I
Ith(RLD)
.1
I
~~~nD~ON~'"TTCnAR~E~~!"!a VALID DATA ~1~:"'rrlIr"lr'l!'DO~N"'T:"'rrlCA"R~E~:"lrlr'l1r"lr'l!'7'
I ,
I
--t j4-tsu (D)
I
II
t+-- ten t ----.f
Q
...
I
I
-----HIOZ--------<¢
....tnCJ
:s
"'C
...o
c..
...>-
~ tdis(CH)
NOT VALID
~)-------
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
CO
VOH
~
~
8-41
SMJ4164
65,536·811 DYNAMICRANDOM·ACCESS MEMORY
read·write/read-modify-write cycle timing
..
~
;:;'"
Dl
-<
.
."
o
c.
...cen
(')
8-42
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
'0
II)
CC
(l)
I"
RAS~
: I"
~
:
I
z
~
fOr;;i
~~
thlRA)
tt
tRLCL
I..
tclP)
~
I
I 1
1
~~
I
I
1
I
W
r--
I.
~ ~ thICLCA)
• COL
II
ItalRl
1
I
I
I
I
1
I
I
I \
I
. I I
thlCHrdl -ot ....--
II
¥;
-I
I
j.--taICl~
I ~ tdislCH)
VALID
~:
:::s
CC
VIH
1I
I:
II
1\
I I
1I
I
1.1
f4"""' tsulrdl
I.
en
?'
UI
:IH
IL
i--+thIRHrd)
~
:z:.
V,H
VIL
~
\
¢
J:..
Military Products
I
2
C
:i:-
I
}~
¢
n
n
I.--+tdiS(CH)
VALID
~>----
m
VOH
VOL
NOTE 5: A write cycle or a read-modify-write cycle can be intermixed with read cycles as long as the write and read-modify-write timing specifications are not violated.
(,J
=
:z:.
s:
I
~ tdislCHl
VALID
n
o
Io--ta(C)~
1
=
=i
s:
............ th(CHrd)
I
w
en
c
-<
2
I
.1
I
I
¢
(j)
...
VIL
I
I
0
tCHRL-I
II
1I
iWm.J
;
:I~W·
I
I
--J
C;
Co
<0
!
....--~:~~--.::1f--;;m%-
COL
(l)
II)
VIL
I
\
t1r.;;I~---
thICLCA)
Co
VIH
f4"t w IRH ).,
~
'wlClI---I I
~-{H-tSUICA)
I
II I
----.l ...... thICHrd)
tCLRH - - . ,
MI
I
:
---,I.!-tsulrdl
~taICl---.f I
co
!~
I
---..J!ttSUICAl
I
I
~!oj- tsulrd)
I
Q
!-----{ ~
=~~:::f~??~::{~€~
1~19
II
\1
II
I ....,.. thICLCA)
I
:
r
I
!
~I
I..
twlCH)
C
tSUI~RA)'L.j
I ~~tSU~CA)
. ROW
~
l-----
}r-1
=r::~
I ,.... thlRLCAl ~
AD-A1
-I
I
I I.-'WIClI-=::l 1'"""" I i--'W1ClI--i
I N.
jf
I
It t
\I
-I
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I-I !.-~I
CAS
1
twiRL)
:30
en
en
s:en
m==
s:c..
0::
=
en
-<+=-
Sl:>npOJd Alel!1!1I\I
00
I
,J:.
~
I-
-RAS
~
I
1
~
I
r
tRLCH
\.-tt
I
'I
I i....-.L
-..j ~ tt -I tw(CH)
n
~
;o~
~~
~~
tsu(RA)
-.jt.L ,
f.
I
I-e--.f-th(CLCA)
I-------{. ~ 'w'CLI --l
i~
V'H
VIL
I
f4'- tCHRL ~
I
1
I
I I
~---~II:
~
I
I
I
~th(CLW)
I
h
I
t---th(RLW)-----.f
, I
I
~l:
I
I
I
i~~!
II.
1~_i!--,-----4"~,t~v'H
W~~~R~
:
: I.'
tSU(D)~
I
1
tw(W)
:
~
II
,.
I
,_
,J
II
,I
I
D DON'T CARE
-I
tsu(D)-.f
-I
I
th(WLD)
1
1~~
_I
1---. th(RLD)~
th(CLD)
-I
tw(W)
_I
~I
,
,-
tsu(D)-.,
-I
th(WLD)
I
1 IJ
tw(W)
LII
r-:II
I-
I
~~~
VAl~D
.f9)=
10
.,
th(CLD)
~VIl
-I
I-
·1
DATA
th(WLD)
-kH&?E!:~~~~~
~
.1
>
CD
n
...
5'
CO
s:
=
>
2
c
0
en
en
s:
s:
0
m
<
I
j.--tsu(WCH)---,
~tSU(WCH)---'
C
<
2
=
(WRH)~
su
'c)
~,;::..
.....
m
I I
tt-t
I
"--tSU(WCH)~
I
I
,
th(CLW)
C)_
n
n
AO-A7~~COl~:"~
I I
W,;::..
CD
0
3'
en
:i:-
I
I 1
,.....~.....
I -.,~.................._
I
CD
C)
.?'Is:
U'1 c..
s:
I 1
~ ~ tsu(CA)
c.
-<
0
t.L.:i
I
3
0
~,
I 1\1----4- th(CLCA)' I
:
I:
I,
I
I I
I
--i ~ tsu(CA)
tsu(CA)
I
tw(RH)-,
Q)
1
1
¥
,I
t.
'l:l
CO
CD
J.--tCLRH-----'
I I-- 'w'ClI----!
I
~ th(CLCA) I
I I I
I I
I ~th(RLC,A) ~
z
S
tc(P)
T\
~
lit
fLj4-
I,
t
II.- 'w'ClI----i
!!
th(RA;
•
I_
I
I+- tRLCL -rI
::
CAS
·1
twIRL)
VVIH
IL
th(CLD)
NOTE 6: A read cycle or a read-modify-write cycle can be intermixed with write cycles as long as the read and read-modify-write timing specifications are not violated.
't:I
Q)
(C
CD
3
o
loG
RAS "
twIRL)
IS
-.f ,.- tt
I
CAS
\-
10--
tRLCL---;..t-
~
;o~
~~
\ct;tsu(RA)
~
I ICI
i~
I.- tt
I,
II
tw(CL)
I
I
:
t
~th(CLCA)
III &-tCHRL
li
-f
0
§;
t. i
V,H
~ 10--
I
t
,r.--twCH)4
I
VIL
CD
0
~
CD
! II
---- ~tsu(CA)
I
3
.., jOtwIRH).,
~eOLUMN~~$¢:eOLUMN~;~~
V,H
[
:
tsu(rd)"'fO"+I1
VIL
g
i--tsU(WCH)-I1
I
I
th(RLD) I
-I I
.~
I+-- th(CLD)
I
&>I
~E~VIAUD
I
I
HIZ
I
th(WLD)_
¢
ta(R)
Io--tCLWL
I
--,1
ICI
II
r----t-
VAUD DATA
I
Q)
U'i
~l--tW(W)-f~l"""llllll~
DON'T CARE
I
I
11'
I
I
th(CLD)
I
-
I
I
JJp u 3JY
--------.l-----c.I
'b1
VIH
VIL
I
<
~~tsu(D) ~
~r-f
th(WLD)CI
HI-Z
¢
'1
:2
~tdis(CH)
VAUD DATA
=
C
I
~~IALID DAT~r:M"T1:T'yrl1n~A""!.T":cn:'TA~T'~~rln :II~
tdis(CH)
w
Q)
:::::j
~ ~:~
Io--ta(c)~
l...----ta(C)=::'
I-
!--tsU(WRH)
I
DATA+¥*i
-I
!.-tsU(WCH)-:!j
I
I
~tsU(D) ~
•
I
I
I
I
ttlo-tW(W)-...l~~
DON'T CARE
I
tRLWL
tsU(rd)~ I
---ti I
I
loG
I~
I
I
I
DON'T CARE
"
Q
t-- : : l
~
tCLRH
rf-4~
I
'r---tCLWL
o
-
tG;-tsu(CA)
I
- %iiiiiiiiiiiW
~~
ICI
ROW
I
W
III
'RLeH
i~
~th(RLCA)...L..........l
I ~th(RA) I j.---ct-th(CLCA)
AO-A7~
-\
tw(CL)
4J
II
z
tc(P)
I I
: ;"
-.I
CCD
,
::t:-
~
n
::::a
::t:-
:2
C
C)
s
:i:n
C"')
m
NOTE 7: A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and the write timing specifications are not violated.
en
en
sen
m3
sc..
CD
,J:..
C1I
Military Products
I
C)~
::::a Q)
<~
SMJ4164
65,536·81T DYNAMIC RANDOM·ACCESS MEMORY
RAS-only refresh timing
Q
~
--------------HI-Z---------------
vOH
VOL
;:;.'
...
D)
<
IDOl vs_ CYCLE TIME
...
"'C
1003 vs. CYCLE TIME
100
0
Q.
c:
«
,....
(")
E
tn
80
70
60
50
~
zw
a:
a:
~
u
100
40
«
E
~
30
1<1....
"
20
0
I....
..
I'~
....
9
10
100
200
50
~
zw
...!. )'y~ r"..
a.
a.
~
I..
~....'()~
>
....I
III
I
i'...~'(), 1ft.
80
70
60
300 400 500
,
40
a:
a:
~
u
>
....I
30
~'()a
~
20
'~~a
.... "Y~
~
a.
a.
.......
.....
..... 1'
....... ....
700
1000
III
M
C
' ..... .......
9
10
100
........
, "' ..... r-..
~
200
300
400 500
700
tc/rd) - CYCLE TIME - ns
tc/rd) - CYCLE TIME - ns
8-46
........
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
1000
SMJ4416
16,384-WORD BY 4-BIT DYNAMIC RAM
AUGUST 1980 -
•
•
0
JD PACKAGE
16,384 x 4 Organization
(TOP VIEW)
Single 5-V Supply (± 10% Tolerance)
G
Performance Ranges
ACCESS ACCESS
TIME
TIME
ROW
COLUMN
ADDRESS ADDRESS
(MAX)
(MAX)
'4416-12
120 ns
70 ns
'4416-15
150 ns
80 ns
'4416-20 200 ns
120 ns
REVISED FEBRUARY 1988
READ
OR
WRITE
CYCLE
(MIN)
230 ns
260 ns
330 ns
READMODIFYWRITE
CYCLE
(MIN)
320 ns
330 ns
440 ns
o
Available Temperature Ranges with MILSTD-883C Class B High-Reliability
Processing
-S ... -55°C to 100°C
-L. ..
OOC to 70°C
..
Long Refresh Period ... 4 ms
VSS
DQ4
CAS
DQ3
DQ1
DQ2
W
RAS
AO
A6
A1
A5
A2
A4
A3
VDD ......._ _J - A7
o Low Refresh Overhead Time ... As Low
As 1.7% of Total Refresh Period
o
o
•
PIN NOMENCLATURE
All Inputs, Outputs, Clocks Fully TTL
Compatible
AO-A7
Address Inputs
CAS
Column-Address Strobe
3-State Unlatched Outputs
DQ1-DQ4
Data In/Data Out
IT
Output Enable
RAS
Row-Address Strobe
Early Write or
Impedance
G to
Control Output Buffer
o Page-Mode Operation for Faster Access
•
Low Power Dissipation
-Operation ... 200 mW (Typ)
-Standby ... 17.5 mW (Typ)
VDD
5-V Supply
VSS
Ground
Vii
Write Enable
..
o SMOS (Scaled-MOS) N-Channel Technology
description
The SMJ4416 is a Military high-speed, 65,536-bit, dynamic random-access memory organized as 16,384
words of 4 bits each. It employs state-of-the-art SMOS (scaled MOS) N-channel double-level polysilicon
gate technology for very high performance combined with low cost and improved reliability_
The SMJ4416 features RAS access times to 150 ns maximum. Power dissipation is 200 mW typical
operating, 17.5 mW typical standby.
SMOS technology permits operation from a single 5-V supply, reducing system power supply and decoupling
requirements, and easing board layout. IDD peaks have been reduced to 60 mA typical, and a - 1 V input
voltage undershoot can be tolerated, minimizing system noise considerations. Input clamp diodes are used
to ease system design.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~a{~~I~~e ~!~:i~~ti~r :I~o::~:~~t:~s~s not
~
TEXAS
i
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright © 1980, ·Texas Instruments Incorporated
8-47
SMJ4416
16,384·WORD BY 4·B11 DYNAMIC RAM
Refresh period is extended to 4 milliseconds, and during this period each of the 256 rows must be strobed
with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power.
All inputs and outputs, including clocks, are compatible with Series 54/74 TTL. All address lines and data
in are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The SMJ4416 is offered in 18-pin 300-mil ceramic side-braze dual-in-line package. It is available in - 55°C
to 100°C and 0 °C to 70°C temperature ranges. Dual-in-line packages are designed for insertion in mountinghole rows on 7,62 mm (300-mil) centers.
operation
address (AO through A 7)
Fourteen address bits are required to decode 1 of 16,384 storage locations. Eight row-address bits are
set up on pins AD through A 7 and latched onto the chip by the row-address strobe (RAS). Then the six
column-address bits are set up on pins A 1 through A6 and latched onto the chip by the column-address
strobe (CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar
to a chip enable iii that it activates the sense amplifiers as well as the row decoder. CAS is used as a
chip select activating the column decoder and the input and output buffers.
write enable (W)
..
~
;:;'
Q)
-<
.
o
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects
the read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard
TTL circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When
W goes low prior to CAS, data out will remain in the high-impedance state allowing a write cycle with
G grounded.
data in (DO 1 through 004)
Da'ta is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling
edge of CAS or W strobes data into the on-chip data latches. These latches can be driven from standard
TTL circuits without a pull-up resistor. In an early write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-modifywrite cycle, CAS will already be low, thus the data will be strobed in by W with setup and hold times
referenced to this signal. In delayed write or read-modify-write, G must be high to bring the output buffers
to high impedance prior to impressing data on the I/O lines.
data out (DO 1 through 004)
""C
The three-state output buffer provides direct TTL compatibility (no pull-up resistor required) with a fanout
of two Series 54/74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance
(floating) state until CAS is brought low. In a read cycle the output goes active after the access time
interval talC) that begins with the negative transition of CAS as long as ta(R) and ta(E) are sati~ied.
The output becomes valid after the access time has elapsed and remains valid while CAS and G are
low. CAS or G going high returns it to a high-impedance state. In an early write cycle, the output is
always in the high-impedance state. In a delayed-write or read-modify-write cycle, the output must be
put in the high-impedance state prior to applying data to the DQ input. This is accomplished by bringing
G ~igh prior to applying data, thus satisfying tGHD.
c.
c
(")
,...
en
output enable (G)
The G signal controls the impedance of the output buffers. When G is high, the buffers will remain in the
high-impedance state. Bringing G low during a normal cycle will activate the output buffers, putting them
in the low-impedance state. It is necessary for both RASand CAS to be brought low for the output buffers
to go into the low-impedance state. Once in the low-impedance state, they will remain in the low-impedance
state until G or CAS is brought high.
8-48
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
SMJ4416
16,384-WORD BY 4-B11 DYNAMIC RAM
refresh
A refresh operation must be performed at least every four milliseconds to retain data. Since the output
buffer is in the high-impedance state unless CAS is applied, the RAS-only refresh sequence avoids any
output during refresh. Strobing each of the 256 row addresses (AD through A 7) with RAS causes all bits
in each row to be refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power.
page mode
Page-mode operation allows effectively faster memory access by keeping the same row address and strobing
successive column addresses onto the chip. Thus, the time required to set up and strobe sequential row
addresses for the same page is eliminated. To extend beyond the 64 column locations on a single RAM,
the row address and RAS are applied to multiple 16K x 4 RAMs. CAS is then decoded to select the proper
RAM.
power up
After power up, the power supply must remain at its steady-state value for 1 ms. In addition, the RAS
input must remain high for 100 p's immediately prior to initialization. Initialization consists of performing
eight RAS cycles before proper device operation is achieved.
logic symbol t
(14)
AO
(13)
Al
(12)
A2
(11 )
A3
(8)
A4
(7)
AS
(6)
A6 -:"';'';''''''---i 20012/2105
(10)
A7
RAS
-
(5)
CAS (16)
23C22
W (4)
G
(1)
(2)
001
A.Z26
002 (3)
003 (15)
004 (17)
tThis symbol is in accordance with ANSI/lEEE Std. 91-1984 and lEe Publication 617- 12.
Pin numbers shown are for the dual-in-line package.
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-49
SMJ4416
16,384-WORD BY 4-BIT DYNAMIC RAM
functional block diagram
RAS3
CAS
W
TIMING & CONTROL
~----------------~
AD
Al
ROW
DECODE
A2
ROW
ADDRESS
BUFFERS
181
A3
A4
A5
11/21 MEMORY ARRAY
DUMMY CELLS
A6
11/214 OF 256 COLUMN DECODE
A7
SENSE
AMP
CONTR
-
'--
111214 OF 256 COLUMN DECODE
COLUMN
ADDRESS
BUFFERS
161
~
-
~
256 SENSE REFRESH
AMPS
~
DUMMY CELLS
ROW
DECODE
---_
.....
5p
DATA IN
REG.
141
I
1/0
BUFFERS
G
141
DATA
OUT
REG.
4
DQ
11/21 MEMORY ARRAY
Al-A6
absolute maximum ratings over operating temperature range (unless otherwise noted) t
Voltage on any pin except VDD and data out (see Note 1) .................... - 1.5 V to 10 V
Voltage on VDD supply and data out with respect to VSS ....................... - 1 V to 6 V
Short circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Minimum operating free-air temperature: S version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55 DC
L version ...
. ....... 0 DC
Operating case temperature: S version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 DC
L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DC
Storage temperature range ............................ : .............. - 65 DC to 150 DC
;:::i.'
e»
-<
...
."
o
Co
c
(')
....en
t Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only. and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1. All voltage values in this data sheet are with respect to VSS'
8-50
TEXAS
~
INSTRUMENTS
POST OFFiCe BOX 225012 • DALLAS. TeXAS 75265
SMJ4416
16,384·WORD BY 4·B11 DYNAMIC RAM
refresh
A refresh operation must be performed at least every four milliseconds to retain data. Since the output
buffer is in the high-impedance state unless CAS is applied, the RAS-only refresh sequence avoids any
output during refresh. Strobing each of the 256 row addresses (AO through A 7) with RAS causes all bits
in each row to be refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power.
page mode
Page-mode operation allows effectively faster memory access by keeping the same row address and strobing
successive column addresses onto the chip. Thus, the time required to set up and strobe sequential row
addresses for the same page is eliminated. To extend beyond the 64 column locations on a single RAM,
the row address and RAS are applied to multiple 16K x 4 RAMs. CAS is then decoded to select the proper
RAM.
power up
After power up, the power supply must remain at its steady-state value for 1 ms. In addition, the RAS
input must remain high for 100 p.s immediately prior to initialization. Initialization consists of performing
eight RAS cycles before proper device operation is achieved.
logic symbol t
RAM 16K x 4
(14)
AO
(13)
2006
A1
(12)
A2
(11 )
A3
(8)
A4
(7)
AS
(6)
A6
(10)
A7
2007/2100
0
A16.383
20012/2105
U)
....,
CJ
::::I
..
.
RAS (5)
"C
0
0..
CAS (16)
>-
23C22
iN
G
ns
(4)
(1)
:!:
~
(2)
OQ1
A.Z26
OQ2 (3)
OQ3 (15)
OQ4 (17)
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the dual-in-line package.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-51
SMJ4416
16,384-W-ORD BY 4-BIT DYNAMIC RAM
functional block diagram
RAS3
CAS
W
TIMING & CONTROL
~------------~
AO
A1
ROW
DECODE
A2
ROW
ADDRESS
BUFFERS
(81
A3
A4
A5
(1/21 MEMORY ARRAY
A6
(1/214 OF 256 COLUMN DECODE
A7
SENSE
AMP
CONTR
L....-
'--
DUMMY CELLS
~
L..........-
11
~
DATA IN
REG.
ROW
DECODE
r-I---
256 SENSE REFRESH
AMPS
(1/214 OF 256 COLUMN DECODE
COLUMN
ADDRESS
BUFFERS
(61
5p
DUMMY CELLS
I
-
(41
I/O
BUFFERS
G
(41
DATA
OUT
REG.
4
DQ
1----<
(1/21 MEMORY ARRAY
A1·A6
absolute maximum ratings over operating temperature range (unless otherwise noted) t
Voltage on any pin except VOO and data out (see Note 1) . . . . . . . . . . . . . . . . . . . . - 1.5 V to 10 V
Voltage on VOO supply and data out with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 6 V
Short circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 rnA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Minimum operating free-air temperature: S version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55 DC
L version
. . . . . . . . . . . . . . . . . . 0 DC
Operating case temperature: S version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 DC
L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DC
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 DC to 150 DC
;::;.'
m
-<
.
."
o
Co
c
....
en
(')
t Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only. and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1. All voltage values in this data sheet are with respect to VSS.
8-52
TEXAS
l.!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
SMJ4416
16,384-WORD BY 4-B11 DYNAMIC RAM
recommended operating conditions
S VERSION
MIN
VOO
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
TC
Operating case temperature
L VERSION
NOM
MAX
MIN
5
5.5
4.5
4.5
a
I
I
VOO
VOO
=
=
NOM
MAX
5
5.5
a
V
V
4.5 V
2.4
4.8
2.4
4.8
5.5 V
2.4
5.8
2.4
5.8
-0.6
0.8
-0.6
0.8
- 55
UNIT
0
V
V
°c
100
70
°c
NOTES: 2. The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet
for logic voltage levels only.
3. Oue to input protection circuitry, the applied voltage may begin to clamp at -0.6 V. Test conditions must comprehend this
occurrence.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
SMJ4416-15
TEST CONOITIONS
PARAMETERS
MIN
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
1001 t
I002t
IOO3 t
1004t
= -2 rnA
= 4.2 rnA
VI = a V to 5.8 V,
VOO = 5 V,
All other pins = a V
Vo = 0.4 V to 5.5 V,
VOO = 5 V, CAS high
10H
10L
Average operating current
At tc
during read or write cycle
(see Note 4)
minimum cycle
=
minimum cycle,
RAS cycling, CAS high
=
Average page-mode
tc(P)
current
RAS low, CAS cycling
MIN
Typt
UNIT
MAX
2.4
V
0.4
0.4
V
±10
±10
p.A
±10
±10
p.A
40
48
35
42
rnA
3.5
5
3.5
5
rnA
25
40
21
34
rnA
25
40
21
34
rnA
...
U)
RAS and CAS high
tc
SMJ4416·20
MAX
2.4
After 1 memory cycle,
Standby current
Average refresh current
=
Typt
minimum cycle,
(.)
::s
"C
...o
c..
...CO>-
tAli typical values are at TC = 25°C and nominal supply voltages.
tI D01 -ID04 are measured with open outputs.
NOTE 4. VIL ~ -0.6 V on all inputs.
~
~
capacitance over recommended supply voltage range and recommended temparature range,
f = 1 MHz§
SMJ4416
PARAMETER
Typt
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
7
pF
Ci(RC)
Input capacitance, strobe inputs
8
10
pF
Ci(W)
Input capacitance, write enable input
8
10
pF
Cilo
Input/output capacitance, data ports
8
10
pF
t All typical values are at TC = 25°C and nominal supply voltages.
§These parameters are guaranteed but not tested.
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-53
SMJ4416
16,384·WORD BY 4·B11 DYNAMIC RAM
switching characteristics over recommended supply voltage range and recommended operating
temperature range
PARAMETER
TEST CONDITIONS
= 100 pF,
IOH = -5 rnA,
IOL = 4.2 rnA
tRLCL = MAX,
CL = 100 pF,
IOH = -5 rnA,
IOL = 4.2 rnA
CL = 100 pF,
IOH = -5 rnA,
IOL = 4.2 rnA
CL = 100 pF,
IOH = 5 rnA,
IOL = 4.2 rnA
CL = 100 pF,
IOH = -5 rnA,
IOL = 4.2 rnA
ALT.
SYMBOL
SMJ4416-15
MIN
MAX
SMJ4416-20
MIN
MAX
UNIT
CL
ta(C)
Access time from CAS
ta(R)
Access time from
ta(G)
Access time after Glow
tdis(CH)
Output disable time after CAS high
i'iAS"
Output disable time
tdis(G)
after G high
tCAC
70
120
ns
tRAC
150
200
ns
40
50
ns
tOFF
-
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c.
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,..
en
8-54
TEXAS
"J}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
0
30
0
40
ns
0
30
0
40
ns
SMJ4416
16,384·WORD BY 4·BIT DYNAMIC RAM
timing requirements over recommended supply voltage range and recommended operating temperature
range
ALT.
PARAMETER
SMJ4416-15
SMJ4416-20
UNIT
SYMBOL
MIN
tc(P)
Page-mode cycle time
tpc
140
210
ns
tc(rd)
Read cycle time t
tRC
Write cycle time
twc
tc(rdW)
Read-write/read-modify-write cycle time
330
330
440
ns
tc(W)
260
260
360
tw(CH)
Pulse duration, CAS high (percharge time):t
tcp
50
80
tw(CL)
Pulse duration, CAS low§
tCAS
70
tw(RH)
Pulse duration, RAS high (precharge time)
tRP
100
twIRL)
Pulse duration, RAS low'
tw(W)
Write pulse duration
tRAS
twp
tRWC
MAX
5000
MIN
120
MAX
ns
ns
ns
5000
120
200
50
0
0
0
0
ns
tsu(CA)
Column-address setup time
tASC
tsu(RA)
Row-address setup time
tASR
tsu(D)
Data setup time
tsu(rd)
Read-command setup time
tRCS
150
40
0
0
0
0
tsu(WCH)
Write-command setup time before CAS high
tCWL
70
80
ns
tsu(WCH)R Write-command setup time before CAS high for RMW cycles
60
80
ns
tsu(RMW)R Write-command setup time before RAS high for RMW cycles
60
80
ns
tDS
5000
ns
5000
ns
ns
ns
ns
ns
ns
tsu(WRH)
Write-command setup time before RAS high
tRWL
70
80
ns
th(CLCA)
Column-address hold time after CAS low
tCAH
Row-address hold time
tRAH
50
25
ns
th(RA)
40
20
th(RLCA)
Column-address hold time after RAS low
tAR
110
130
ns
th(CLD)
Data hold time after CAS low
tDH
50
80
ns
th(RLD)
Data hold time after RAS low
tDHR
130
160
ns
tDH
40
50
ns
tRRH
10
10
ns
ns
th(WLD)
Data hold time after W low
th(RHrd)
Read-command hold time after RAS high"
th(CHrd)
Read-command hold time after CAS high"
tRCH
0
0
th(CLW)
Write-command hold time after CAS low
tWCH
50
80
ns
th(RLW)
Write-command hold time after RAS low
tWCR
130
160
ns
tRLCH
Delay time, RAS low to CAS high
tCSH
150
200
ns
tCHRL
Delay time, CAS high to RAS low
tCRP
0
0
ns
tCLRH
Delay time, CAS low to RAS high
tRSH
70
120
ns
tCWD
110
170
ns
tRCD
70
tRWD
190
250
ns
[WCS
-5
-5
ns
30
40
Delay time, CAS low to W low
tCLWL
(read-modify-write-cycle only)#
Delay time, RAS low to CAS low
tRLCL
(maximum value specified only to guarantee access time)
Delay time, RAS low to W low
tRLWL
(read-modify-write-cycle only)#
tWLCL
Delay time, W low to CAS low (early write cycle)
tGHD
Delay time, G high before data applied at DQ
trf
Refresh time interval
tREF
t All cycle times assume tt = 5 ns.
:t Page mode only.
§In a read-modify-write cycle, tCLWL and tsu(WCH) must be
observed. Depending on the user's transition times, this may require
additional CAS low time tW(CL)'
80
4
70
..
ns
80
ns
ns
4
ms
'In a read-modify-write cycle, tRLWL and tsu(WRH) must be
observed. Depending on the user's transition time, this may require
additional RAS low time twIRL)'
II These parameters are guaranteed but not tested.
#Necessary to insure G has disabled the output buffers prior to
applying data to the device.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-55
SMJ4416
16,384-WORD BY 4-BI1 DYNAMIC RAM
PARAMETER MEASUREMENT INFORMATION
Vee
II
4--(-)
OUTPUT(S)
OPEN
REMAINING{
INPUTS
OPEN
OUTPUT
UNDER TEST
t
TCL
~
'OHilOL
= 80 pF
NOTE 5. Each input is tested separately.
FIGURE 1. INPUT CLAMP VOLTAGE TEST CIRCUIT
FIGURE 2. EQUIVALENT LOAD CIRCUIT
read eycle timing
-
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...............
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VOH
VALID OUTPUT ) ..- - - - - - -
----------~~~I
I
I
____t~--------
TEXAS
"'J}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
SMJ4416
16,384-WORD BY 4-BIT DYNAMIC RAM
early write cycle timing
..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-57
SMJ4416
16,384·WORD BY 4·BIT DYNAMIC RAM
write cycle timing
..
8-58
TEXAS
-1!1
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS, TeXAS 75265
SMJ4416
16,384-WORD BY 4-B11 DYNAMIC RAM
read-write/read-modify-write cycle timing
..
DQ
talG)
-r--.J
I
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{
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~
TEXAS
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS, TeXAS 75265
8-59
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AO-A8
MIL-STD-883C Class B
High-Reliability Processing
•
RAS-Only Refresh Mode
•
Hidden Refresh Mode
•
CAS-Before-RAS Refresh Mode
•
Full Military DRAM Temperature Range
Operation ... - 55 °C to 110 °C
Address Inputs
(J
:::s
CAS
Column-Address Strobe
0
Data In
"C
NC
Q
No Connect
Data Out
RAS
Row-Address Strobe
c..
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VDD
VSS
Ground
IN
Write Enable
...
0
ca
5-V Supply
~
~
description
The SMJ4256 is a high-speed, 262, 144-bit dynamic random-access memory, organized as 262,144 words
of one bit each. It employs state-of-the-art SMOS (scaled MOS) N-channel double-level pldysilicon/polycide
gate technology for very high performance combined with low cost and improved reliability.
The SMJ4256 features maximum RAS access times of 120 ns, 150 ns, or 200 ns. Typical power dissipation
is as low as 300 mW operating and 12.5 mW standby.
New SMOS technology permits operation from a single 5-V supply, reducing system power supply and
decoupling requirements, and easing board layout. IDD peaks are 125 mA typical, and a - 0.5-V input
voltage undershoot can be tolerated, minimizing system noise considerations.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~a{~~I~~e ~~~~~~ti~r :I~o::~:~:t::s~s not
Copyright © 1985. Texas Instruments Incorporated
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-65
SMJ4256
262.144·BIT DYNAMIC RANDOM·ACCESS MEMORY
All inputs and outputs, including clocks, are compatible with Series 54 TTL. All address and data-in lines
are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The SMJ4256 is offered in 16-pin 300-mil ceramic side-braze dual-in-line and 18-pad ceramic chip carrier
packages. It is guaranteed for operation from - 55°C to 110°C. The dual-in-line package is designed for
insertion in mounting-hole rows on 7 ,62-mm (300-mil) centers.
operation
address (AD through A8)
Eighteen address bits are required to decode 1 of 262,144 storage cell locations. Nine row-address bits
are set up on pins AO through A8 and latched onto the chip by the row-address strobe (RAS). Then the
nine column-address bits are set up on pins AO through A8 and latched onto the chip by the column-address
strobe (CAS). All addresses must be stable on or before the falling edge of RAS and CAS. RAS is similar
to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a
chip select activating the column decoder and the input and output buffers.
write enable (W)
The read or write mode is selected through the write-enable {WI input. A logic high on the W input
selects the read mode and a logic low selects the write mode. The write-enable terminal can be driven
from standard TTL circuits without a pull-up resistor. The data input is disabled when the read mode is
selected. When W goes low prior to CAS, data out will remain in the high-impedance state for the entire
cycle, permitting common I/O operation.
data in (0)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling
edge of CAS or W strobes data into the on-chip data latch. This latch can be driven from standard TTL
circuits without a pull-up resistor. In an early write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-modifywrite cycle, CAS will already be low, thus the data will be strobed in by W with setup and hold times
referenced to this signal.
-
~
data out (Q)
;:;:
The three-state output buffer provides direct TTL compatibility (no pull-up resistor required) with a fanout
of two Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance
(floating) state until CAS is brought low. In a read cycle the output goes active after the access time
interval talC) that begins with the negative transition of CAS as long as ta(R) is satisfied. The output becomes
valid after the access time has elapsed and remains valid while CAS is low; CAS going high returns it to
a high-impedance state. In a read-modify-write cycle, the output will follow the sequence for the read cycle.
Q)
-<
.
."
oQ.
C
C')
r+
(I)
refresh
A refresh operation must be performed at least once every four milliseconds to retain data. This can be
achieved by strobing each of the 256 rows (AO-A 7). A normal read or write cycle will refresh all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
thus conserving power as the output buffer remains in the high-impedance state.
CAS-before·RAS refresh
The CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS (see parameter tCLRLl and
holding it low after RAS falls (see parameter tRLCHR). For successive CAS-before-RAS refresh cycles,
CAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated
internally.
8-66
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ4256
262,144·81T DYNAMIC RANDOM·ACCESS MEMORY
hidden refresh
Hidden refresh may be performed while maintaining valid data at the output pin. This is accomplished by
holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to
a "RAS-only" refresh cycle. The external address is also ignored during the hidden refresh cycles.
page mode
Page-mode operation allows effectively faster memory access by keeping the same row address and strobing
random column addresses onto the chip. Thus, the time required to set up and strobe sequential row
addresses for the same page is eliminated. The maximum number of columns that can be addressed is
determined by twiRL), the maximum RAS low pulse duration.
power-up
To achieve proper device operation, an initial pause of 200 p,S is required after power up followed by a
minimum of eight initialization cycles.
logic symbol t
RAM 256K x 1
AO
A1
A2
A3
A4
A5
A6
A7
A8
(5)
(7)
(6)
(12)
(11 )
(10)
(13)
(9)
(1 )
(4)
20D9/21DO
A
1
I
-
1
(15)~
(3)
W
(2)
D
0
262,143
•
20D17/21D8
C20[ROW]
G23/[REFRESH ROW]
24[PWR DWN]
r--.. C21[COL]
G24
r-......
&
23C22
r-......
r--....
-~
23.21D 124EN
A.22D
....
(/)
(,)
::::s
"C
...o
c..
A\l
(14)
~
ca
Q
~
~
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
Pin numbers shown are for the JD package.
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-67
SMJ4256
262,144·8IT DYNAMIC RANDOM·ACCESS MEMORY
functional block diagram
RAS
I
~1
CAS
+
+
TIMING AND CONTROL
--+-
rc
AD
ROW
DECODE
r--
256 SENSE AMPS
r--r---1\
A5
J2K ARRAY
I--
r---
ROW
DECODE
J2K ARRAY
ROW
DECODE
~
J2K ARRAY
I; 5
110
BOFFERS
I of 4
SELEC·
TIDN
J2K ARRAY
256 SENSE AMPS
256 SENSE AMPS
A6
A7
..
256 SENSE AMPS
COLUMN DECODE
--I
COLUMN
ADDRESS
BUFFERS
(81
J2K ARRAY
ROW
DECODE
J2K ARRAY
1
Al
A2
AJ
A4
I
<.t
J2K ARRAY
ROW
ADDRESS
BUFFERS
(81
W
J
•
~
IN
REG
HlfrOUT
REG
J2K ARRAY
I
~~L~'LI
AS
•
ROW
absolute maximum ratings over operating temperature range (unless otherwise noted)t
Voltage range for any pin, including VDD supply (see Note 1). . . . . . .. . . . . . . . . . . .. - 1 V to 7 V
Short circuit output current ....................... : . . . . . . . . . . . . . . . . . . . . . . . . .. 50 mA .
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Minimum operating free-air temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C
Operating case temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 110°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
~
;:;'"
m
-<
".oc.
c
....en
(')
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
VOO
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage (see Note 2)
TA
Operating free-air temperature
TC
Operating case temperature
MIN
NOM
MAX
UNIT
4.75
5
0
5.25
V
5
0.8
V
2.4
-0.5
-55
V
110
V
°c
°c
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as maximum, is used in this data sheet for
logic voltage levels only.
8-68
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ4256
262,144·8IT DYNAMIC RANDOM·ACCESS MEMORY
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
II
10
=
V
V
±10
p.A
±10
p.A
60
80
rnA
2.5
5
rnA
45
63
rnA
35
50
rnA
5.25 V,
= 0 V to 5.5 V,
VOO = 5.25 V, CAS high
tc = minimum cycle,
during read or write cycle
UNIT
0.4
Vo
Output current (leakage)
MAX
2.4
VI = 0 V to 5 V, VOO
Output open
Input current (leakage)
Typt
MIN
10H = -5 rnA
10L = 4.2 rnA
Average operating current
1001
SMJ4256-12
CONDITIONS
Output open
After 1 memory cycle,
1002
Standby current
RAS and
CAS
high,
Output open
=
tc
1003
RAS
Average refresh current
minimum cycle,
cycling,
CAS high,
Output open
tc(P) = minimum cycle,
1004
RAS low, CAS cycling,
Average page-mode current
Output open
TEST
PARAMETER
SMJ4256-15
CONDITIONS
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
= -5 rnA
= 4.2 rnA
VI = 0 V to 5 V,
VOO = 5.25 V,
MIN
Typt
SMJ4256-20
MAX
2.4
10H
10L
MIN
Typt
UNIT
MAX
2.4
V
0.4
0.4
V
±10
±10
p.A
±10
±10
p.A
Output open
= 0 V to 5.5
VOO = 5.25 V,
Vo
10
Output current (leakage)
V,
..
CAS high
1001
=
Average operating current
tc
during read or write cycle
Output open
Standby current
RAS
minimum cycle,
60
75
45
60
rnA
2.5
5
2.5
5
rnA
45
60
35
45
rnA
35
50
25
45
rnA
After 1 memory cycle,
1002
and
CAS
high,
Output open
tc
1003
Average refresh current
= minimum
RAS
cycling,
cycle,
CAS high,
Output open
tc(P)
1004
Average page-mode current
= minimum cycle,
RAS low, CAS cycling,
Output open
t All typical values are at T A = 25°C and nominal supply voltages.
TEXAS
'1!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-69
SMJ4256
262,144·811 DYNAMIC RANDOM·ACCESS MEMORY
capacitance over recommended supply voltage range and operating temparature range, f
1 MHz
Typt
PARAMETER
UNIT
Ci(A)
Input capacitance, address inputs
4
pF
Cj(D)
Input capacitance, data input
4
pF
Cj(RC)
Cj(W)
Input capacitance, strobe inputs
4
pF
Input capacitance, write enable input
4
Co
Output capacitance
5
pF
pF
t All typical values are at T A = 25 DC and nominal supply voltages.
switching characteristics over recommended supply voltage range and operating temperature range
PARAMETER
CAS
ta(C)
Access time from
ta(R)
Access time from RAS
Output disable time
tdis(CH)
after CAS high
= 80 pF,
= 4.2 rnA
tRLCL = MAX, CL = 80 pF,
IOH = -5 rnA, IOL = 4.2 mA
CL = 80 pF, IOH = -5 mA,
IOL = 4.2 mA
IOH
ta(C)
Access time from CAS
ta(R)
Access time from RAS
Output disable time
~
after
CAS
high
=
5 rnA. IOL
SYMBOL
= 80 pF,
IOL = 4.2 mA
tRLCL ~ MAX, CL
IOH
=
-5 mA,
= MAX, CL = 80, pF,
= -5 mA, IOL = 4.2 mA
CL = 80 pF, IOH = -5 mA,
IOL = 4.2 mA
tRLCL
IOH
UNIT
tCAC
65
ns
tRAC
120
ns
30
ns
0
SMJ4256·15
MIN
MAX
SMJ4256·20
MIN
MAX
UNIT
80
100
ns
tRAC
150
200
ns
35
ns
tOFF
*Figure 1 shows the load circuit; CL values shown are typical for test system used.
Q)
-<
...
."
oQ,
I:
n
....
(I)
TEXAS
MAX
tCAC
;:;'
8-70
MIN
tOFF
ALT.
TEST CONDITIONS*
SMJ4256·12
SYMBOL
tRLCL ~ MAX, CL
PARAMETER
tdis(CH)
ALT.
TEST CONDITIONS*
'I!.J
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS,TEXAS 75265
0
30
0
SMJ4256
262,144·8IT DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and operating temperature range
ALT.
SYMBOL
tc(P)
Page-mode cycle time (read or write cycle)
tc(PM)
Page-mode cycle time (read-modify-write cycle)
tc(rd)
SMJ4256-12
MAX
MIN
..
UNIT
tpc
125
ns
tpCM
172
ns
Read cycle time t
tRC
230
ns
tc(W)
Write cycle time
twc
230
ns
tc(rdW)
Read-write/read-modify-write cycle time
tRWC
277
ns
tw(CH)P
Pulse duration,
50
ns
tw(CH)
Pulse duration,
tw(CL)
Pulse duration,
tw(RH)P
Pulse duration, RAS high (page mode)
tw(RH)
tWIRL)
CAS high (page mode)
CAS high (non-page mode)
CAS low+
tcp
tCPN
25
tCAS
65
tRP
115
Pulse duration, RAS high (non-page mode)
tRPN
.100
Pulse duration, RAS low §
tRAS
120
ns
10,000
ns
ns
ns
10,000
ns
tw(W)
Write pulse duration
twp
40
ns
tsu(CA)
Column-address setup time
tASC
0
ns
tsu(RA)
Row-address setup time
tASR
0
ns
tsu(D)
Data setup time
tDS
3
ns
tsu(rd)
Read-command setup time
tRCS
5
ns
tsu(WCL)
Early write-command setup time before CAS low
twcs
0
ns
tsu(WCH)
Write-command setup time before CAS high
tCWL
40
ns
tsu(WRH)
Write-command setup time before RAS high
tRWL
40
ns
th(CLCA)
Column-address hold time after
tCAH
20
ns
th(RA)
Row-address hold time
tRAH
15
ns
th(RLCA)
Column-address hold time after RAS low
tAR
75
ns
th(CLD)
Data hold time after
CAS low
tDH
40
ns
th(RLD)
Data hold time after
RAS
tDHR
95
ns
th(WLD)
Data hold time after W low
tDH
40
ns
th(CHrd)
tRCH
0
ns
tRRH
10
ns
th(CLW)
CAS high
Read-command hold time after "RAS high
Write-command hold time after CAS low
tWCH
40
ns
th(RLW)
Write-command hold time after RAS low
tWCR
95
ns
th(RHrd)
CAS low
low
Read-command hold time after
..
I
....en
(,)
:2
"C
Continued next page.
NOTES: 3. Timing measurements are referenced to VIL max and VIH min.
4. System transition times (rise and fall) for RAS and CAS are to be a minimum of 3 ns and a maximum of 50 ns.
t All cycle times assume tt = 5 ns.
+In a read-modify-write cycle, tCLWL and tsu(WCH) must be observed. Depending on the user's transition times, this may require additional
CAS low time (tw(CL)). This applies to page·mode read-modify-write also.
§In a read-modify-write cycle, tRLWL and tsu(WRH) must be observed. Depending on the user's transition times, this may require additional
RAS low time (tw(RL)).
TEXAS
.JI!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
..
..>o
c..
8-71
CO
~
~
SMJ4256
262,144·BIT DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and operating temperature range
(continued)
ALT.
SMJ4256-12
SYMBOL
MIN
MAX
UNIT
tRLCH
Delay time. ~ low to
120
ns
Delay time. CAS high to
'C'AS high
RAS low
tCSH
tCHRL
tCRP
5
ns
tCLRH
Delay time. CAS low to
'RAS
tRSH
65
ns
tRHCL
Delay time. ~ high to
tRCP
25
ns
tRLCHR
Delay time.
'C'AS low'
'C'AS high'
tCHR
30
ns
tCLRL
Delay time. CAS low to~ low'
tCSR
30
ns
tCWD
67
ns
tRCD
25
tRWD
122
'RAS low
to
high
Delay time. CAS low to W low
tCLWL
(read·modify-write cycle only)
Delay time. RAS low to CAS low
tRLCL
(maximum value specified only
55
ns
to guarantee access time
Delay time. RAS low to W low
tRLWL
trf
(read·modify-write cycle only)
Refresh time interval
tREF
Continued next page.
NOTE 3: Timing requirements are referenced to VIL max and VIH min.
'~-before-~ refresh only .
..
~
::4"
C»
-<
...""0
o
Co
C
(')
'*
en
8-72
TEXAS
~
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS. TeXAS 75265
ns
4
ms
SMJ4256
262, 144·81T ·DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and operating temperature range
(continued)
ALT.
SYMBOL
tc(P)
Page-mode cycle time (read or write cycle)
tc(PM)
Page-mode cycle time (read-modify-write cycle)
SMJ4256-15
MIN
MAX
SMJ4256-20
MIN
MAX
UNIT
tpc
145
190
ns
tpCM
205
250
ns
tc(rd)
Read cycle time t
tRC
260
330
ns
tc(W)
Write cycle time
twc
260
330
ns
tRWC
ns
tc(rdW)
Read-write/read-modify-write cycle time
tw(CH)P
Pulse duration, CAS high (page mode)
tw(CH)
Pulse duration,
CAS high
tw(CL)
Pulse duration, CAS low:!:
tw(RH)P
Pulse duration,
tw(RH)
(non-page mode)
315
390
tcp
60
80
ns
tCPN
30
40
ns
10,000
80
tRP
120
120
ns
Pulse duration, RAS high (non-page mode)
tRPN
100
120
ns
twIRL)
Pulse duration, RAS low§
Write pulse duration
tRAS
twp
150
tw(W)
45
55
tsu(CA)
Column-address setup time
tASC
0
0
ns
tsu(RA)
Row-address setup time
tASR
0
0
ns
high (page mode)
tsu(D)
Data setup time
tsu(rd)
Read-command setup time
before
CAS low
10,000
200
10,000
ns
ns
ns
tDS
3
3
ns
tRCS
5
5
ns
twcs
0
0
ns
Early write-command setup time
tsu(WCL)
10,000
100
tCAS
RAS
tsu(WCH)
Write-command setup time before
CAS high
tCWL
45
65
ns
tsu(WRH)
Write-command setup time before RAS high
tRWL
45
65
ns
th(CLCA)
Column-address hold time after CAS low
tCAH
30
45
ns
th(RA)
Row-address hold time
tRAH
20
25
ns
th(RLCA)
Column-address hold time after RAS low
tAR
100
145
ns
th(CLD)
Data hold time after CAS low
tDH
50
55
ns
th(RLD)
Data hold time after RAS low
tDHR
120
155
ns
th(WLD)
Data hold time after W low
tDH
45
55
ns
th(CHrd)
Read-command hold time after CAS high
0
0
ns
tRCH
th(RHrd)
Read-command hold time after RAS high
tRRH
10
15
ns
th(CLW)
Write-command hold time after CAS low
tWCH
50
55
ns
th(RLW)
Write-command hold time after RAS low
tWCR
120
155
ns
..
o
~
CJ
:::s
"'C
o...
c.
~
ca
~
Continued next page.
NOTES: 3. Timing measurements are referenced to VIL max and VIH min.
4. System transition times (rise and fall) for RAS and CAS are to be a minimum of 3 ns and a maximum of 50 ns.
t All cycle times assume tt = 5 ns.
:!:In a read-modify-write cycle, tCLWL and tsu(WCH) must be observed. Depending on the user's transition times, this may require additional
CAS low time (tw(CL)l. This applies to page-mode read-modify-write also.
§In a read-modify-write cycle, tRLWL and tsu(WRH) must be observed. Depending on the user's transition times, this may require additional
RAS low time (tw(RL))'
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
8-73
~
SMJ4256
262,144·811 DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and operating temperature range
(concluded)
ALT.
tRLCH
Delay time, RAS low to CAS high
tCHRL
Delay time,
tCLRH
Delay time,
tRHCL
Delay time,
tRLCHR
Delay time,
tCLRL
Delay time,
CAS high to RAS low
CAS low to RAS high
RAS high to CAS low'
RAS low to CAS high'
CAS low to RAS low'
SMJ4256-15
(read-modify-write cycle only)
Delay time,
tRLCL
RAS
MAX
MIN
MAX
UNIT
MIN
tCSH
150
200
ns
tCRP
5
5
ns
tRSH
80
100
ns
tRCP
25
25
ns
tCHR
30
40
ns
tCSR
30
35
ns
tCWD
85
90
ns
tRCD
25
tRWD
155
Delay time, CAS low to W low
tCLWL
SMJ4256-20
SYMBOL
low to CAS low
(maximum value specified only
70
35
100
ns
4
ms
to guarantee access time)
Delay time, RAS low to W low
tRLWL
trf
(read-modify-write cycle only)
Refresh time interval
tREF
NOTE 3: Timing measurements are referenced to VIL max and VIH min.
, CAS-before-RAS refresh only.
PARAMETER MEASUREMENT INFORMATION
V
~
OUTPUT
UNDER TEST
~.
D)
-<
"'C
ac.
~1
IOHIIOL
CL = 80 pF
c:
....
en
C')
FIGURE 1. EQUIVALENT LOAD CIRCUIT
8-74
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAs. TEXAS 75265
ns
190
4
SMJ4256
262,144·81T DYNAMIC RANDOM·ACCESS MEMORY
read cycle timing
I~.------tc(rd)-------·~I
1
I \..
RAS
1~
I.
l.-tt
I
1
~
twIRL)
tCLRH----t
-l-
;\_____ ~:~
I--tw(RH)~
1 j4-tRLCL~tW(CL)--I ~tCHRL--i
I.
tRLCH
.1 1 I
1I
I
--..I !+-+ tt
~
1
j+-tsu(RA)
AO-AS
I
~
I
---I
1I
~~
: tw(CH)~
----1
' - ;,:
I I
I.--th(RLCA)~
th(RA)--i
1
~
1\
V
I
I
~ tsu(CA)
I
I
I
1
~ COLUMN ~£?Ei:~~~zm<,-____
~I II;~III
1_
_I
th(RHrd)
1
I r---r- th(CLCA)
1 i
1
~
II ~
I.
1 It
I4j- su(rd)
..,
th(CHrd)
-
TEXAS
-I./}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
8-75
SMJ4256
262,144·BIT DYNAMIC RANDOM·ACCESS MEMORY
early write cycle timing
I-
~
tc(W)
1
,
1I-
t r-
-+I
tt
I1
,
th(RA)
I
~
tt
:f-~ i
----I ~tsu(CA)
I
~th(RILCA\ ~
I I ~ th(CLCA)
;\
tsu(WCL)
1
~
~
I
I
I
I
I
.1
I. I I tsu(WCH)
.. II I•
tsu(WRH)
I
t.-----.,.-I--Y01 th(RLW)
I.
I
VIL
II
__
~~~~'ml~~
VIH
l4--- t w(CH)-----1
wwt RO~ ~C~LUMN~JJ~!',-'m~~,-~I~II
AO-A8
~ tCHRL......J
!!...
=\:~ tW(CL)~JF.l::I=---------::::i4::::::I
tRLCH
~
~,:
L
+' ~tW(RH)-.l
tCLRH
--1
1 I·
1
.¥t
I_
1 /.- tRLCL
tsu(RA)...J...-.i
-I,
twiRL)
_
1
_ __
I
I
N
..
I ~th(CLW)--'
W~:!
~
I
~tW(W)---~~
-
I j.-th(CLD)~
~
-.
D
;::;'"
D)
-<
.
~
Ith(RLD)
~l:::-V-A-L-ID-DA-T-A-,=,~r""'~~DO"N~'T~CA~RX'lE~~~
"
:::
----.II+- tsu(D)
...""C
o
Co
c
VOH
n
Q
- - - - - - - - - - - HI-Z - - - - - - - - - - - - -
( J)
VOL
TEXAS
~
INSTRUMENTS
8-76
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ4256
262.144·8IT DYNAMIC RANDOM·ACCESS MEMORY
write cycle timing
,-
tclW)
-,
1
I I-
~r-
~
I_
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ca
:l:
tThe enable time (ten) for a write cycle is equal in duration to the access time from CAS (talC)) in a read cycle. but the active levels at
the output are invalid.
TEXAS
.
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
8-77
~
SMJ4256
262,144·BIT DYNAMIC RANDOM·ACCESS MEMORY
read-write/read-modify-write cycle timing
IRAS ,
\
I+-tt
,.
I ~ th(RAI
-J ~
I
tSU(RAI
Ir
I
I.
1----+
th(CLCAI
:
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I
.1
TEXAS """
INSTRUMENTS
8-78
II
II
----I I
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::
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twiRl)
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AO-AB
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POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
tdis(CHI
*
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VIL
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NOTE 6: A read cycle or a read-modify-write cycle can be intermixed with write cycles as long as read and read-modify-write timing specifications are not violated.
'C
III
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I
NOTE 7: A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated.
Military Products
=U1
ctS
~
~
SM/SMJ4461
262,144·BIT MULTIPORT VIDEO RAM
refresh
A refresh operation must be performed to each row at least once every four milliseconds to retain data.
Since the output buffer is in the high-impedance state unless CAS is applied, the RAS-only refresh sequence
avoids any output during refresh. Strobing each of the 256 row addresses with RAS causes all bits in
each row to be refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power.
Note that the data registers are dynamic storage elements and that the data held in the registers will be
lost unless SC is clocked two times or else the data is reloaded from the memory array. See specifications
for maximum register retention times.
CAS-before-RAS refresh
CAS-before-RAS refresh is accomplished by bringing CAS low earlier than RAS (see parameter tCLRU.
The external row address is ignored and the refresh address is generated internally.
column-address strobe (CAS)
The CAS input latches the column addresses on-chip and also functions as an output enable for 001-004.
power up
After power up, the power supply must remain at its steady-state value for one millisecond. In addition,
RAS must remain high for 100 p's immediately prior to initialization. Initialization consists of performing
eight RAS cycles and one memory-to-register transfer cycle with an SC cycle following the rising edge
of TRG before proper device operation is achieved.
sequential·access operation
..
~
::+
Q)
transfer register select (TRG)
Memory operations involving parallel use (i.e., transfer from memory to data register or data register to
memory) of the data register are invoked by bringing TRG low with the address lines AO-A 7 before RAS
falls. This enables the switches connecting the 256 elements of each data register to the 256 bit lines
of each ORAM I/O. The states of WE and SG, which are also latched on the falling edge of RAS,
determine whether the 256-bit data transfer will be from the memory array to the data registers or from
the data registers to memory array, as well as determining if the SOOs are in read or write mode (see
"transfer operation logic table").
Note that the state of TRG is latched on the falling edge of RAS just like a row address to select the mode
of operation. Ouring read or read-modify-write cycles, TRG functions as output enable after CAS falls.
-<
.oc.
""C
transfer write enable (WE)
In register transfer mode, WE determines whether a transfer will occur from the data registers to the
memory array, or from the memory array to the data registers. To transfer data from the data registers
to the memory array, WE and SG are held low as RAS falls. If SG were to be high during this transition,
then no transfer of data from the data register to the memory array would occur, but the SOOs would
be put into the write mode. This would allow serial data to be written into the register. To transfer from
the memory array to the data registers, WE is held high and SG is a don't care as RAS falls. This cycle puts
the SOOs into the read mode, thus allowing serial data to be read out of the data register. Note that WE
and SG setup and hold times are referenced to the falling edge of RAS for this mode of operation (see
"transfer operation logic" table).
c(")
....en
row address (AD through A 7)
Eight address bits are required to select one of the 256 possible rows involved in the transfer of data to
or from the data registers. (The states of AO-A 7, WE, TRG, and SG are latched on the falling edge of RAS).
8·90
TEXAS ' "
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
SM/SMJ4461
262,144·BIT MULTIPORT VIDEO RAM
register column address (AO through A 71
To select one of the 256 positions along each of the four data registers from which the first serial data
will be read out, or to which the first serial data will be written, the appropiate 8-bit column address (AO-A 7)
must be valid when CAS falls during the appropriate transfer cycle.
serial data clock (SCI
Data is written in or read out of the data registers on the rising edge of SC. This makes it possible to view
the data registers as though they were made of 256 positive-edge-triggered 0 flip-flops connected 0 to
o (not to be confused with the DO random I/O pins of the SMJ4461 ). The SMJ4461 is designed to work
with a wide range duty cycle clock to simplify system design.
serial data input/output (SOO 1-S0041
SO and SO share a common I/O pin. Data is written in when SG is low during write mode and data is
read out when SG is low during read mode (see "transfer operation logic table"). Note that when the
serial address counter reaches its maximum value of 255, it is reset back to 00 with the next positive
transition of SC. This allows data to be read out in a continuous loop.
block diagram of one serial I/O
DATA REGISTER
SC
AO·A7
"
~
SERIAL
ADDRESS
COUNTER
SDQ
~ 256
I
-[>-
l
SERIAL DECODER/MUX
~
..
SERIAL
MODE
CONTROL
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
8-91
SM/SMJ4461
262,144·81T MULTIPORT VIDEO RAM
serial enable (SG)
The serial enable pin has two functions. First, it is used on the falling edge of RAS, with both TRG and
WE low. If SG is low during this transition, then a register-to-memory transfer will occur. On the other
hand, if SG were to be high as RAS falls, then a write-mode control cycle will be performed. The function
of this cycle is to switch the SOOs from the output mode to the input mode, thus allowing serial data
to be written into the data register. Second, SG is used as a SOO enable/disable. In the write mode, SG
is used as an input enable. SG high disables the input, and SG low enables the input. To take the device
out of the write mode and into the read mode, a memory-to-register transfer cycle must be performed.
The read mode allows data to be read out of the data register. SG high disables the output and SG low
enables the output. Note that the serial address counter will be incremented on each SC cycle regardless
of the state of SG.
TRANSFER OPERATION LOGIC TABLE
TRG
WE
SG
0
0
0
0
0
1
0
1
X
MOOE
Register-to-memory transfer
Write-mode enable
Memory-to-register transfer
NOTE 2: The logic states in the table above are assumed valid on the falling edge of RAS.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
Voltage range for any pin except VOO and data out (see Note 3) ................ - 1.0 V to 7 V
Voltage range for VOO supply with respect to VSS ............................ - 1 V to 7 V
Voltage range for data out with respect to VSS ....................... - 1 V to VOO + 0.3 V
Short circuit output current per output .......................................... 50 mA
Power dissipation ............................................................ 1 W
Operating temperature range ...................... ; .................. - 55°C to 110°C
Storage temperature range .......................................... - 65°C to 1 50°C
~
..
.
o"
;:;'"
C)
'<
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only. and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect
device reliability.
NOTE 3: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
.
Q.
VOD Supply voltage
VSS Supply voltage
C
()
o
VIH
High-level input voltage
All inputs except SC
II SC
VIL
Low-level input voltage (see Note 4)
TA
Operating free-air temperature
TC
Operating case temperature
MIN
NOM
MAX
4.5
5
0
5.5
2.4
2.6
-1
-55
UNIT
V
V
5.5
5.5
0.8
110
V
V
DC
DC
NOTE 4: The algebraic convention where the more negative (Jess positive) limit is designated as minimum is used in this data sheet for
logic voltage levels only.
8-92
-Ij}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SM/SMJ4461
262,144·8IT MULTIPORT VIDEO RAM
electrical characteristics over full range of recommended operating conditions (unless otherwise noted)
VOH High-level output voltage
Low-level output voltage
VOL
II
10
Input current (leakage)
Output current (leakage)
SMJ4461-15
TEST
PARAMETER
CONDITIONS
= -5 mA
= 4.2 mA
VI = 0 V to 5.8 V,
Vo = 0.4 V to 5.5
MIN Typt
2.4
IOH
V
0.4
V
5 V, All outputs open
±10
JlA
=
±10
JlA
50
80
rnA
15
20
rnA
45
75
rnA
35
60
rnA
70
80
rnA
110
140
rnA
TYP
MAX
IOL
VDO
=
UNIT
MAX
V, VOO
5 V
Average operating current
1001 during read, write or transfer
cycle (serial port in standby)
1002
Standby current
After 1 memory cycle, RAS, CAS, SC, and SG
(total, both ports)
No load on DO and SOO pins
1003 Average refresh current
1004
Mininum cycle time, No load on DO and SOO pins
Minimum cycle time, RAS
Minimum cycle time, RAS
(serial port in standby)
No load on DO and SOO
Average current with
1006 Worst case average current
0.8 V, CAS
~
2.4 V,
2.4 V,
No load on DO and SOO pins
Average page-mode current
1005 memory array in standby
and register shifting
~
~
~
0.8 V, CAS cycling,
tc(SC) = MIN, RAS and CAS ~ 2.4 V,
No load on DO and SOO pins
Minimum cycle time on both ports,
No load on DO and SOO pins·
t All typical values are at T A = 25°C and nominal supply voltages.
capacitance at 25 °C with nominal supply voltage, f
1 MHz
MIN
PARAMETER*
UNIT
pF
Ci(A)
Input capacitance, address inputs
4
Ci(RC)
Input capacitance, strobe inputs
8
pF
Ci(WE)
Input capacitance, write enable input
8
pF
Ci(SC)
Input capacitance, serial clock
8
pF
Ci(SG)
Input capacitance, serial enable
4
pF
Ci(TRG)
Input capacitance, transfer register input
4
pF
Co
Output capacitance
5
pF
....CJ
t/)
:::l
"C
:l:Capacitance data collected for major design or process changes only.
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(see Figure 1)
PARAMETER
TEST
ALT.
CONDITIONS
SYMBOL
= 80 pF, tRLCL
= 80 pF, tRLCL
SMJ4461-15
MIN
MAX
~ MAX
tCAC
75
ns
~ MAX
tRAC
150
ns
ta(C)
Access time from CAS
CL
Access time from RAS
CL
ta(TRG)
Access time of DO from TRG low
CL = 80 pF
45
ns
ta(SC)
Access time of SO from SC high
CL
50
ns
ta(SG)
Access time of SO from SG low
CL
tdis(CH)
Random-output disable time from CAS high
CL
tdis(TRG) Random-output disable time from TRG high
CL
= 80 pF
= 80 pF
= 80 pF
= 80 pF
= 80 pF
tdis(SG)
Serial-output disable time from SG high
CL
tOFF
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
40
ns
0
30
ns
0
30
ns
30
ns
CO
~
~
UNIT
ta(R)
...o
c.
...>-
8-93
SM/SMJ4461
262,144·81T MULTIPORT VIDEO RAM
timing requirements over recommended supply voltage and operating free-air temperature ranges
ALT.
~
.
-<
.c.
o
;:;"
G)
"g
c
...
n
(II
MIN
MAX
UNIT
tc(rd)
Read cycle time t
tRC
260
ns
tc(W)
Write cycle time
twc
260
ns
tc(rdW)
Read-write/read-modify-write cycle time
tRWC
345
ns
tc(Trd)
Transfer read cycle time
tRC
260
ns
tc(TW)
Transfer write cycle time
twc
260
ns
tcIP)
Page-mode read or write cycle time
tpc
145
ns
tRWC
230
ns
tc(rdWP) Page-mode read-write/read-modify-write cycle time
Serial clock cycle time
tc(SC)
..
SMJ4461·15
SYMBOL
tscc
50 20,000
ns
60
ns
75 10,000
ns
tw(CH)
Pulse duration, CAS duration (precharge time)
tw(CL)
Pulse duration, CAS low:t
tw(RH)
Pulse duration, RAS high (precharge time)
twIRL)
Pulse duration, RAS low§
tw(W)
Write pulse duration
tw(SCL)
Pulse duration, SC low
10
ns
tw(SCH)
Pulse duration, SC high
10
ns
45
ns
tcp
tCAS
tRP
tRAS
twp
100
150 10,000
45
ns
ns
ns
tw(TRG)
Pulse duration, TRG low
tsu(CA)
Column-address setup time
tASC
0
ns
tsu(RA)
Row-address setup time
tASR
0
ns
tsu(RW)
WE setup time before RAS low with TRG low (register transfer cycles)
0
ns
tsu(DQ)
DQ setup time before RAS low with TRG high (random access, write mask select)
8
ns
tsu(D)
Data setup time
5
ns
tsu(rd)
Read-command setup time
tos
tRCS
0
ns
tsu(WCL) Early write-command setup time before CAS low
twcs
0
ns
tsu(WCH) Write-command setup time before CAS high
tCWL
45
ns
tsu(WRH) Write-command setup time before RAS high
tRWL
45
ns
5
ns
0
ns
tsu(SD)
Serial data setup time before SC high
tsu(TRG) TRG setup time before RAS low
tsu(SG)
SG setup time before RAS low with TRG and WE low
0
ns
0
ns
tCAH
25
ns
tRAH
15
ns
15
ns
ns
tsu(WM) WE setup time before RAS low (write mask select)
th(CLCA) Column-address hold time after CAS low
Row-address hold time
th(RA)
th(RW)
WE hold time after RAS low with TRG low (transfer cycles)
th(RLCA) Column-address hold time after RAS low
tAR
100
th(CLD)
Oata hold time after CAS low
tDH
45
ns
th(RLD)
Data hold time after RAS low
tOHR
120
ns
tDH
th(WLD)
Data hold time after WE low
45
ns
th(CHrd)
Read-command hold time after CAS high
tRCH
0
ns
th(RHrd)
Read-command hold time after RAS high
tRRH
10
ns
Continued next page.
NOTES: 5. Timing measurements referenced to V,L max and V,H min.
6. System transition times (rise and fall) are to be a minimum of 3 ns and a maximum of 50 ns.
t All cycle times assume tt = 5 ns.
:tIn a read-modify-write cycle, tCLWL and tsu(WCH) must be observed. Depending on the user's transition times, this may require additional
CAS low time (tw(CL)).
§'n a read-modify-write cycle, tRLWL and tsu(WRH) must be observed. Depending on the user's transition times, this may require additional
RAS low time (tw(RL)).
8-94
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SM/SMJ4461
262,144-BIT MULTIPORT VIDEO RAM
timing requirements over recommended supply voltage and operating free-air temperature ranges
(continued)
ALT.
SYMBOL
SMJ4461-15
MIN
MAX
UNIT
th(CLW)
Write·command hold time after CAS low
tWCH
45
ns
th(RLW)
Write-command hold time after RAS low
tWCR
120
ns
th(WOE)
TRG hold time after WE low
ns
th(SD)
Serial data-in hold time after SC high
40
15
th(SO)
Serial data-out hold time after SC high 0
6
ns
ns
th(TRG)
TRG hold time after RAS low
15
ns
th(DO)
DO hold time after RAS low with TRG high and WE low
15
ns
th(SG)
SG hold time after RAS low with TRG and WE low
15
ns
th(WM)
WE hold time after RAS low (write mask select)
15
ns
tRLCH
Delay time, RAS low to CAS high
tCSH
150
ns
tCHRL
Delay time, CAS high to RAS low
tCRP
5
ns
tCLGH
Delay time, CAS low to TRG high
tCLRH
Delay time, CAS low to RAS high
tCLWL
Delay time, CAS low to WE low (read·modify·write cycle only)'
Delay time, RAS low to TRG high
tRLTH
(memory-to-register transfer cycle)
I Early load#
I Mid-line real-time load
Delay time, RAS low to the first positive transition of SC after
tRLSH
tTHRL
TRG high (register transfer cycle)
Delay time, TRG high to RAS low after a transfer cycle
Delay time, CAS low to the first positive transition of SC after
tCLSH
TRG high (register transfer cycle)
Delay time, SC high to RAS low with TRG and WE low
tSHRL
(register-to-memory transfer cycle) I
tSHTH
Delay time, SC high to TRG high (memory-to-register transfer cycle)
*
80
ns
tRSH
75
ns
tCWD
110
ns
25
100
ns
125
ns
100
ns
50
ns
50
ns
15
ns
..
Continued next page.
NOTE 5: Timing measurements are referenced to VIL max and VIH min.
, TRG must disable the output buffers prior to applying data to the device.
# TRG may be brought high early during a memory-to-registertransfer cycle as long as the th(TRG), tSHTH, and tRLSH specifications are met.
I In a register-to-memorytransfer cycle, the state of SC when RAS falls is a don't care condition. However, to guarantee proper sequencing
of the internal clock circuitry there can be no positive transitions of SC for at least 40 ns prior to when RAS goes low. See the section entitled
"sequential access operation" for a complete explanation of the transfer operation.
In a memory-to-register transfer cycle, the state of SC when TRG rises is a don't care condition. However, to guarantee proper sequencing
of the internal clock circuitry there can be no positive transitions of SC for at least 10 ns prior to when TRG goes high. See the section entitled
"sequential access operation" for a complete explanation of the transfer operation.
DThis parameter is guaranteed but not tested.
*
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
8-95
SM/SMJ4461
262,144·81T MULTIPORT VIDEO RAM
timing requirements over recommended supply voltage and operating free-air temperature ranges
(concluded)
ALT.
SYMBOL
SMJ4461-15
MIN
MAX
20
UNIT
tTHSH
Delay time, TRG high to SC high (memory-to-register transfer cycle)
tTHRH
Delay time, TRG high to RAS high (memory-to-register transfer cycle)
0
ns
tTHCH
Delay time, TRG high to CAS high (register transfer cycles)
0
ns
tCLTH
Delay time, CAS low to TRG high (memory-to-register transfer cycle)
25
ns
Delay time, RAS low to CAS low (maximum value specified only
tRLCL
25
tRCD
to guarantee RAS access time)
ns
Delay time, CAS low to TRG low (maximum value specified
tCLGL
to guarantee column access time)
75
ns
30
ns
tRLWL
Delay time, RAS low to WE low (read-modify-write cycle only)
tRWD
185
ns
tCLRL
Delay time, CAS low to RAS low (CAS-before-RAS refresh)
tCSR
25
ns
tRLCHR
Delay time, RAS low to CAS high (CAS-before-RAS refresh)
tCHR
25
ns
tSGSC
Delay time, SG low to SC high during serial data-in shift cycle
10
ns
tGHD
Delay time, TRG high before data applied at DQ
tGDD
trf(MA)
Refresh time interval, memory array
tREFl
trf(SR)
Refresh time interval, shift register
tREF2
30
ns
4
20,000
NOTE 5: Timing measurements are referenced to V,L max and vlH min.
..
~
PARAMETER MEASUREMENT INFORMATON
1.31 V
D)
-<
.,"tI
o
c
-I
RL =2180
OUTPUT
UNDER
TEST
;:;"
VCC = 5 V
TCL
R1 = 8280
OUTPUT
UNDER--~-------b
TEST
CL = 80 pF
~80pF
R2 = 2950
Co
n
r+
(b) ALTERNATE LOAD CIRCUIT
(a) LOAD CIRCUIT
en
FIGURE 1. LOAD CIRCUITS FOR TIMING PARAMETERS
8-96
TEXAS.
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
ms
ns
SM/SMJ4461
262. 144-81T MULTIPORT VIDEO RAM
read cycle timing
I.
I '.
I I
RAS
tc(rd)
--rJI
~
tt
I
I
'--.t
r - - CLRH~
II I.I
I
I
I
.,
T\. . _____ ~:~
11
'--
I
.,
twIRL)
~ tw(CL)---t
~
I,
II II
I
I
N
I
I
I4--+-tCHRL
-.I I
tRLCH
/+-tRLCL---.j
(4--t w (RH)--1
I
I--t<
.V!I..
i l - ' I-
I------~
~
..;!
.....
II
I
I I
l ~tCLGH~ I
I ~th(RLCA)---t
I II
I~tsu(RA)--.I
~th(RA) i i I
II II II
I
~
tw(CH)-----i•
\4-t sU (CA)1
~
~o~ ~ ;~~LUMN
~~~~""""'~·mR~~W===
I. J
i
I
I
th(CLCA)!
I4,-tsu (TRG)
II
'hlTRGlimvwtr
I.
.-t
I
I
I ., I
!:
:
t
su(rd)
~ I
I
1
I
1
I
th(CHrd)~
I
1
I ...... ,.....th(RH
I
TEXAS
I,
d)
'
~
INSTRUMENTS
POST OFFICE BOX 1443 •
VIL
::
tw(TRG)
TRGW : ~\~ :~
I
I
VIH
HOUSTON. TEXAS 77001
..
8-97
SM/SMJ4461
262, 144·81T MULTIPORT VIDEO RAM
early write cycle timing, write mask un selected
8-98
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SM/SMJ4461
262, 144·81T MULTIPORT VIDEO RAM
early write cycle timing, write mask selected
II I!I
RAS
--y..
tt
CAS
-I
tc(W)
twIRL)
•
I
I
I
~
Vi--tW(RHI~\
I ""'-------
I I-t--tCLRH--1
I
tRLCL ---!-- tw(CLI ---l rtCHRL----,
I I·
tRLCH
• I I I
I
I I
I
tt~ ft:
I
i I
!.tl
I
I--
-1
titSUIRAI
II
r--!
N
I ~'
r-:-- th(RLCAI----l
th(RAI-t-i
I tSU(C~1
¥ll
I
I
"\
I 1\. . .----
L+----- tw(CHI--+--t
I
I
,...------
AO-A7
VIL
VIH
VIL
VIH
VIL
1-L
I'
tsu(TRGI--j
th(TRGI-j-!
VIH
I--
I
th(CLCAI
IJ.-L-tsu(WRHI -----J
!++-tsu(WCH)
--1 '--
.!
I I
I I
~I:. 'Cl~1
tsu(TRGI
VIH
VIL
VIH
VIL
..
VIH
....CJ
VIL
"C
(I)
:::s
...
0
c.
...>CO
:!:
~
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
8-99
SM/SMJ4461
262,144·8IT MULTIPORT VIDEO RAM
delayed write cycle timing, mask unselected
,,RAS - - ' ,
,
tclW}
,,-
.,
~
twiRL)
~!
CAS
I
_.
!
{ t - t w I R H I - j \______ VIL
•-
tCLRH
t:= tRLCL --1
I I
tRLCH
,
I
A
sulR I
•
twlCLI
: -I,
,
I
'--t
• ,
I
i
~
n--1
I
TnG
..
-<
DQ
.o
,-..--, twlCHI--+---i
,
,
r-t,
,
I
I
I
:'
---I
1-" I tsulTRGI
., thICLCA}
I
I
I
','
I-
,
I
tsulWCHI+--i
I
thlRLWI
• ,
,
rtsulWRHlt-----t
--'
I
r--tsulWMI
lW!rgEr
, I L--tW(W)--I
, I L.. th(WLDI -I
~th(CLDI==
th(RLDI-------I.......
~=1X 0
2
DQ2
16
CAS
4
15
5
14
D03
AO
6
13
A1
12
A2
o
On-Chip Substrate Bias Generator
o
All Inputs, Outputs, and Clocks Fully TTL
Compatible
B 9 1011
o
3·State Unlatched Output
v
•
Early Write or
Impedance
•
Page-Mode Operation for Faster Access
o
•
o
~
G to Control Output Buffer
....en
1 1 B 17
3
(J
~
.
..
"C
o
c..
>co
~
0"'" C"l
0
>
~
~
~
NOTE: Pin 1 indicator on back.
PIN NOMENCLATURE
Power Dissipation As Low As:
- Operating ... 275 mW (Typ)
- Standby ... 12.5 mW (Typ)
RAS-Only Refresh Mode
CAS-Before-RAS Refresh Mode
AO-A7
Address Inputs
CAS
Column-Addreess Strobe
D01-D04
Data In/Data Out
G
Output Enable
RAS
Row-Address Strobe
VDD
5-V Supply
VSS
Ground
IN
Write Enable
description
The SMJ4464 is a high-speed, 262, 144-bit dynamic random-access memory, organized as 65,536 words
of four bits each. It employs state-of-the-art SMOS (scaled MOS) I\!-channel double-level polysilicon/polycide
gate technology for very high performance combined with low cost and improved reliability.
This device features maximum RAS access times of 120 ns, 150 ns, or 200 ns. Typical power dissipation
is as low as 275 mW operating and 12.5 mW standby.
New SMOS technology permits operation from a single 5-V supply, reducing system power supply and
decoupling requirements, and easing board layout. 100 peaks of 125 mA are typical, and a - O. 7-V input
voltage undershoot can be tolerated, minimizing system noise considerations.
All inputs and outputs, including clocks, are compatible with Series 54 TTL. All address and data-in lines
are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
PRODUCTION DATA documents contain information
current as of publication date. Products conform
to specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
-1!1
INSTRUMENTS
TEXAS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright © 1987, Texas Instruments Incurporated
8-115
SMJ4464
65,536·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
The SMJ4464 is offered in 18-pin 300-mil ceramic side-braze dual-in-line and 18-pad lead less ceramic
chip carrier packages. It is guaranteed for operation from - 55°C to 110°C for the S version and from
aoc to 70°C for the L version. The dual-in-line package is designed for insertion in mounting-hole rows
on 7,62-mm (300-mil) centers).
operation
address (AO through A 7)
Sixteen address bits are required to decode 1 of 65,536 storage locations. Eight row-address bits are set
up on pins AO through A7 and latched onto the chip by the row-address strobe (RAS). Then the eight
column-address bits are set up on pins AO through A 7 and latched onto the chip by the column-address
strobe (CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar
to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a
chip select, activating the column decoder and the input and output buffers.
write enable (W)
The read or write mode is selected through the write enable (W) input. A logic high on the W input selects
the read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard
TTL circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When
W goes low prior to CAS, data out will remain in the high-impedance state for the entire cycle, permitting
common I/O operation.
data in (OQ1-0Q4)
Data is written during a write or a read-modify-write cycle. Depending on the mode of operation, the falling
edge of CAS or W strobes data into the on-chip data latches. These latches can be driven from standard
TTL circuits without a pull-up resistor. In an early write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or a read-modifywrite cycle, CAS will already be low, thus the data will be strobed in by W with setup and hold times
referenced to this signal. In a delayed or read-modify write cycle, G must be high to bring the output buffers
to high impedance prior to impressing data on the I/O lines.
-
~
data out (OQ1-0Q4)
;::;'.
The three-state output buffer provides direct TTL compatibility (no pull-up resistor required) with a fanout
of two Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance
(floating) state until CAS is brought low. In a read cycle the output goes active after the access time interval
talC) that begins with the negative transition of CAS as long as ta(R) and ta(G) are ~tisfied. The outP~
becomes valid after the access time has elapsed and remains valid while CAS and G are low. CAS or G
going high returns it to a high-impedance state. In a delayed-write or read-modify-write cycle, the output
must be put in the high-impedance state prior to applying data to the DQ input. This is accomplished by
bringing G high prior to applying data, thus satisfying tGHD.
...
D)
-<
"...
o
Co
r::::
...o
(')
output enable {G)
The G input controls the impedance of the output buffers. When G is high, the buffers will remain in the
high-impedance state. Bringing G low during a normal cycle will activate the output buffers, putting them
in the low-impedance state. It is necessary for both RAS and CAS to be brought low for the output buffers
to go into the low-impedance state. Once in the low-impedance state they will remain in the low-impedance
state until G or CAS is brought high.
refresh
A refresh operation must be performed at least once every four milliseconds to retain data. This can be
achieved by strobing each of the 256 rows (AO-A 7). A normal read or write cycle will refresh all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
thus conserving power as the output buffer remains in the high-impedance state.
8-116
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
SMJ4464
65,536-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
operation (continued)
CAS-before-RAS refresh
The CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS (see parameter tCLRLl and
holding it low after RAS falls (see parameter tRLCHR). For successive CAS-before-RAS refresh cycles,
CAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated
internally.
page mode
Page-mode operation allows effectively faster memory access by keeping the same row address and strobing
random column addresses onto the chip. Thus, the time required to set up and strobe sequential row
addresses for the same page is eliminated. The maximum number of columns that can be addressed is
determined by tw(RL), the maximum RAS low pulse duration.
power up
To achieve proper device operation, an initial pause of 200 p's is required after power up, followed by a
minimum of eight initialization cycles.
logic symbol t
RAM 64K X 4
AO _(_14_)_ _
2008/2100
(13)
Al
(12)
A2
(11)
A3
A _O
_
(8)
65,535
A4
(7)
A5
(6)
A6
(10)
A7
RAS
(5)
..
I
....
U)
Co)
CAS
::::s
.
.
"0
0
(16)
23C22
Q.
(4)
W
G
001
>-
(1)
ca
(2)
:!:
~
A.Z26
(3)
002
003 (15)
(17)
004
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the dual-in-line package.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-117
SMJ4464
65,536·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
functional block diagram
W
t t
I
~l
---
ADDRESS
BUFFERS
-
ROW
e-
A1
ROW
32K ARRAY
A3
ADDRESS
BUFFERS
A4
(8)
A5
-
DECODE
t:;::;:
r:-:-
32K ARRAY
A6
1/0
BUFFERS
(4)
32K ARRAY
r-
~
DATA
S
DATA
OUT
REG
IN
REG
~~
D01·D04
256 SENSE AMPS
256 SENSE AMPS
r--
.. ..
32K ARRAY
DECODE
COLUMN DECODE
-.I
COLUMN
256 SENSE AMPS
ROW
32K ARRAY
M
32K ARRAY
DECODE
256 SENSE AMPS
(8)
A2
I
~J
r--
AO
t
TIMING AND CONTROL
32K ARRAY
ROW
t
ROW
32K ARRAY
DECODE
A7
absolute maximum ratings over operating temperature range (unless otherwise noted) t
Voltage on any pin including VOO supply (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V
Short circuit output current . . . . . . . . . . . . . . . . . . . . . .
. ......... 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Minimum operating free-air temperature: S version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55°C
L version
.... 0 °e
Maximum operating case temperature:
S version
......... 110°C
L version
. . . . . . . . .
. ......... 70oe
......................... - 65°C to 150°C
Storage temperature range ........ .
~
::+"
e»
-<
.
."
o
c..
c
n
....
en
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute·maximum·rated conditions for extended periods may affect
device reliability .
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
S VERSION
VOO
Supply voltage
VSS
Supply voltage
VIH
High·level input voltage
VIL
Low-level input voltage (see Note 2)
TA
Operating free·air temperature
TC
Operating case temperature
NOTE 2:
8-118
L VERSION
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
2.4
VOO+0.3
-0.7
0.7
-55
2.4
-0.7
VOO +0.3
V
0.7
V
DC
70
DC
0
110
V
V
0
0
UNIT
The algebraic convention, where the negative (less positive) limit is designated as maximum, is used in this data sheet for logic
voltage levels only.
TEXAS
-I!}
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ4464
65,536·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
PARAMETER
SMJ4464-12
TEST CONDITIONS
MIN Typt
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
= -5 mA
= 4.2 mA
VI = 0 V to 5.8 V, VOO = 5 V, All outputs open
Output current (leakage)
Vo
10
1001
1002
1003
1004
tc
during read or write cycle
Standby current
tc
Average refresh current
All outputs open
= minimum cycle, RAS low, CAS cycling,
All outputs open
SMJ4464-15
TEST CONDITIONS
Low-level output voltage
II
Input current (leakage)
Average operating current
during read or write cycle
= -5 mA
= 4.2 mA
VI = 0 V to 5.8 V, VOO = 5 V,
2.4
IOH
Standby current
1003
Average refresh current
1004
Average page-mode current
±10
/LA
65
80
mA
2.5
8
mA
50
60
mA
45
55
mA
= 0 V to 5.5 V, VOO = 5 V,
Vo
CAS high
tc
= minimum cycle, All outputs open
high, All outputs open
tc
= minimum cycle, RAS low, CAS
high, All outputs open
tc(P)
= minimum cycle, RAS low, CAS
cycling, All outputs open
MIN Typt
UNIT
MAX
2.4
IOL
After 1 memory cycle, RAS and CAS
1002
/LA
SMJ4464-20
MIN Typt MAX
All outputs open
Output current (leakage)
t All typical values are at T A
= minimum cycle, RAS low, CAS high,
tc(P)
Average page-mode current
High-level output voltage
1001
= minimum cycle, All outputs open
All outputs open
VOL
V
±10
= 0 V to 5.5 V, VOO = 5 V, CAS high
After 1 memory cycle, RAS and CAS high,
VOH
V
0.4
IOL
PARAMETER
10
2.4
10H
Average operating current
UNIT
MAX
V
0.4
0.4
V
±10
±10
/LA
±10
±10
/LA
55
70
50
60
mA
2.5
8
2.5
8
mA
45
55
40
50
mA
40
50
30
40
mA
..
25°C and nominal supply voltages.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-119
SMJ4464
65,536·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
1 MHz
capacitance over recommended supply voltage range and operating temperature range, f
SMJ4464
PARAMETER
Cj(A)
Typt
Input capacitance. address inputs
Cj(RC) Input capacitance. strobe inputs
Cj(W) Input capacitance. write enable input
Ci/o
Output capacitance
t All typical values are at T A
=
UNIT
MAX
4
pF
8
pF
8
pF
8
pF
25°C and nominal supply voltages.
switching characteristics over recommended supply voltage range and operating temperature range
ta(C)
Access time from CAS
ta(R)
Access time from RAS
ta(G)§
Access time after Glow
tdis(CH) Output disable time after CAS high
tdis(G)
Output disable time after G high
ALT.
TEST CONDITIONSf
PARAMETER
=
SYMBOL
=
-5 mA.
CL
= 80 pF. IOH =
= 4.2 mA
= 80 pF. IOH = -5 mA. IOL =
= 80 pF. IOH = -5 mA. IOL =
-5 mA.
CL
=
tRLCL 2: MAX. CL
IOL
=
80 pF. IOH
4.2 mA
tRLCL 2: MAX. CL
IOL
CL
80 pF. IOH
=
-5 mA. IOL
=
4.2 mA
4.2 mA
4.2 mA
SMJ4464-12
MIN
MAX
UNIT
tCAC
60
ns
tRAC
120
ns
tGAC
35
ns
tOFF
0
30
ns
tGOFF
0
38
ns
switching characteristics over recommended supply voltage range and operating temperature range
TEST CONDITIONSf
PARAMETER
ta(C)
Access time from CAS
ta(R)
Access time from RAS
~
ta(G)§
Access time after Glow
D)
tdis(CH) Output disable time after CAS high
.
.
;:;"
<
-a
tdis(G)
0
Co
c:
C")
...
Output disable time after G high
ALT.
SYMBOL
= 80 pF.
= 4.2 mA
tRLCL 2: MAX. CL = 80 pF.
IOH = -5 mA. IOL = 4.2 mA
-5 mA.
CL = 80 pF. IOH
IOL = 4.2 mA
-5 mA.
CL = 80 pF. IOH
IOL = 4.2 mA
CL = 80 pF. IOH = -5 mA.
IOL = 4.2 mA
tRLCL 2: MAX. CL
IOH
=
-5 mA. IOL
MIN
MAX
SMJ4464-20
MIN
MAX
UNIT
tCAC
75
100
ns
tRAC
150
200
ns
tGAC
45
55
ns
tOFF
0
30
0
35
ns
tGOFF
0
38
0
38
ns
+Figure 1 shows the load circuit; CL values shown are typical for test system used.
§ta(C) and ta(R) must be satisfied to guarantee ta(G)'
(/)
8-120
SMJ4464-15
TEXAS •
INSTRUMENTS
POST OFFiCe BOX 225012 • DALLAS. TeXAS 75265
SMJ4464
65,536-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
timing requirements over recommended supply voltage range and operating temperature range
ALT.
SYMBOL
tc(P)
Page-mode cycle time
tc(PM)
Page-mode cycle time (read-modify-write cycle)
SMJ4464-12
MIN
MAX
UNIT
tpc
120
ns
tpCM
205
ns
tc(rd)
Read cycle time t
tRC
230
ns
tc(W)
Write cycle time
twc
230
ns
tc(rdW)
Read-write/read-modify-write cycle time
tRWC
320
ns
tw(CH)P
Pulse duration, CAS high (page mode)
tw(CH)
tcp
50
ns
Pulse duration, CAS high (non-page mode)
tCPN
50
ns
tw(CL)
Pulse duration, CAS 10w1=
tCAS
60
tw(RH)
Pulse duration, RAS high
tRP
100
twiRL)
Pulse duration, RAS low §
tRAS
120
tw(W)
Write pulse duration
twp
40
tsu(CA)
Column-address setup time
tASC
0
ns
tsu(RA)
Row-address setup time
tASR
0
ns
ns
10,000
ns
ns
10,000
ns
ns
tsu(D)
Data setup time
tDS
10
tsu(rd)
Read-command setup time
tRCS
0
ns
tsu(WCL)
Early-write command setup time before CAS low
twcs
0
ns
tsu(WCH) Write-command setup time before CAS high
tCWL
40
ns
tsu(WRH) Write-command setup time before RAS high
tRWL
40
ns
th(CLCA)
Column-address hold time after CAS low
tCAH
20
ns
th(RA)
Row-address hold time
tRAH
15
ns
th(RLCA)
Column-address hold time after RAS low
tAR
80
ns
th(CLD)
Data hold time after CAS low
tDH
35
ns
tDHR
95
ns
tDH
35
ns
th(RLD)
Data hold time after RAS low
th(WLD)
Data hold time after W low
th(CHrd)
Read-command hold time after CAS high
tRCH
0
ns
th(RHrd)
Read-command hold time after RAS high
tRRH
10
ns
ns
th(CLW)
Write-command hold time after CAS low
tWCH
35
th(RLW)
Write-command hold time after RAS low
tWCR
95
ns
tRLCHR
Delay time, RAS low to CAS high'
tCHR
25
ns
tRLCH
Delay time, RAS low to CAS high
tCSH
120
ns
tCHRL
Delay time, CAS high to RAS low
tCRP
0
ns
tRHCL
Delay time, RAS high to CAS low'
tRCP
0
ns
ns
tCLRH
Delay time, CAS low to RAS high
tRSH
60
tCLWL
Delay time, CAS low to W low (read-modify-write cycle only)#
tCWD
100
ns
tCLRL
Delay time, CAS low to RAS low'
tCSR
25
ns
tRCD
25
Delay time, RAS low to CAS low (maximum value specified only
tRLCL
to guarantee access time)
tRLWL
Delay time, RAS low to W low (read-modify-write cycle only)#
tRWD
160
tGHD
Delay time, G high before data applied at DQ
tGDD
25
trf
Refresh time interval
tREF
60
..
ns
ns
ns
4
ms
t All cycle times assume tt = 5 ns.
1= ~ead-modify-write cycle, tCLWL and tsu(WCH) must be observed. Depending on the user's transition times, this may require additional
CAS low time (tw(CL)).
§ ~ead-modify-write cycle, tRLWL and tsu(WRH) must be observed. Depending on the user's transition times, this may require additional
RAS low time (tw(RL)).
, CAS-before-RAS refresh option only.
#(3 must disable the output buffers prior to applying data to the device.
NOTE 3: System transition times (rise and fall) for RAS and CAS are to be a minimum of 3 ns and a maximum of 50 ns.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-121
SMJ4464
65,536-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
timing requirements over recommended supply voltage range and operating temperature range
ALT.
SYMBOL
tc(P)
Page·mode cycle time
tc(PM)
Page-mode cycle time (read-modify-write cycle)
MIN
MAX
SMJ4464-20
MIN
MAX
UNIT
tpc
145
190
ns
tpCM
230
295
ns
tc(rd)
Read cycle time t
tRC
260
330
ns
tc(W)
Write cycle time
twc
260
330
ns
tc(rdW)
Read-write/read-modify-write cycle time
tRWC
345
435
ns
tw(CH)P
Pulse duration, CAS high (page mode)
tcp
60
80
ns
tw(CH)
Pulse duration, CAS high (non-page mode)
tCPN
60
80
ns
tw(CL)
Pulse duration, CAS low t
tCAS
75 10,000
tw(RH)
Pulse duration, RAS high
tRP
tw(RL)
Pulse duration,. RAS low §
tw(W)
Write pulse duration
tRAS
twp
tsu(CA)
Column-address setup time
tsu(RA)
Row-address setup time
tsu(D)
Data setup time
tsu(rd)
tsu(WCL)
th(CLCA)
100 10,000
ns
100
120
ns
150 10,000
200 10,000
ns
45
55
ns
tASC
0
0
ns
tASR
0
0
ns
tDS
10
10
ns
Read-command setup time
tRCS
0
0
ns
Early-write command setup time before CAS low
twcs
0
0
ns
tCWL
45
60
ns
tRWL
45
60
ns
Column-address hold time after CAS low
tCAH
25
45
ns
tRAH
ns
tsu(WCH) Write-command setup time before CAS high
tsu(WRH) Write-command setup time before RAS high
-
SMJ4464-15
th(RA)
Row-address hold time
15
20
th(RLCA)
Column-address hold time after RAS low
tAR
100
145
ns
th(CLD)
Data hold time after CAS low
tDH
45
55
ns
th(RLD)
Data hold time after RAS low
tDHR
120
155
ns
th(WLD)
Data hold time after W low
tDH
45
55
ns
th(CHrd)
Read-command hold time after CAS high
0
0
ns
ns
tRCH
th(RHrd)
Read-command hold time after RAS high
tRRH
10
15
th(CLW)
Write-command hold time after CAS low
tWCH
45
55
ns
th(RLW)
Write-command hold time after RAS low
tWCR
120
155
ns
-<
tRLCHR
Delay time, RAS low to CAS high ~
tCHR
30
35
ns
tRLCH
Delay time, RAS low to CAS high
tCSH
150
200
ns
oQ.
tCHRL
Delay time, CAS high to RAS low
tCRP
0
0
ns
tRHCL
Delay time, RAS high to CAS low'
tRCP
10
15
ns
tCLRH
Delay time, CAS low to RAS high
tRSH
75
100
ns
tCLWL
Delay time, CAS low to W low (read-modify·write cycle only)#
tCWD
110
140
ns
tCLRL
Delay time, CAS low to RAS low'
tCSR
30
35
~
;:;'
C»
..."'a
c:
n
,...
en
Delay time, RAS low to CAS low (maximum value specified only
tRCD
tRLWL
Delay time, RAS low to W low (read-modify-write cycle only)#
tRWD
185
240
tGHD
td
Delay time, G high before data applied at DQ
tGDD
25
35
Refresh time interval
tREF
tRLCL
to guarantee access time)
t All cycle times assume tt
75
30
25
4
ns
100
ns
ns
ns
4
ms
= 5 ns.
must be observed. Depending on the user's transition times, this may require additional
CAS low time (tw(CL)).
§ ~ead-modify-write cycle, tRLWL and tsu(WRH) must be observed. Depending on the user's transition times, this may require additional
RAS low time (tw(RL)).
, CAS-before-RAS refresh option only.
#(3 must disable the output buffers prior to applying data to the device.
NOTE 3: System transition times (rise and fall) for RAS and CAS are to be a minimum of 3 ns and a maximum of 50 ns.
t ~ead-modify-write cycle, tCLWL and tsu(WCH)
8-122
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ4464
65,536·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
PARAMETER MEASUREMENT INFORMATION
v
OUTPUT
UNDER TEST
~1
IOH/lOL
CL
= 80 pF
FIGURE 1. TYPICAL LOAD CIRCUIT
-
-II}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-123
SMJ4464
65,536·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
read cycle timing
AO-A7
w
~
DQ
;::;.'
2Q€oa·~c:~1
:
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II
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--J
jtRLCLt\
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w
if
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all
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A read cycle or read-modify-write cycle can be intermixed with write cycles as long as the read and read-modify-write timing specifications are not violated.
Military Products
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th(RLD)---I
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tt'
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ta(c~
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ell
=
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A read cycle or a write cycle can be intermixed with
~.
cycles as long as the read and write timing specifications are not violated.
c...
c....1~
en~
o
3:
VIL/VOL
1
r----rtGHD
~
a-CD
W
W
HJ PACKAGEt
(TOP VIEW)
CAS-Before-RAS Refresh
DOl
Long Refresh Period . . .
512-Cycle Refresh in 8 ms (Max)
VSS
D04
D02
3-State Unlatched Output
W
D03
RAS
CAS
c..
G
TF
Low Power Dissipation
a:
I-
0
Texas Instruments EPIC'" CMOS Process
All Inputs and Clocks Are TTL Compatible
High-Reliability Ceramic 20-Pin 300-Mil-Wide
DIP or 20/26-Lead Ceramic Surface Mount
(CSOJ) Package
- 55°C to 125°C Operating Temperature
Range
AO
A8
Al
A7
A2
A6
A3
A5
VCC
A4
::J
C
0
a:
c..
...
tThe packages shown here are for pinout reference only.
The HJ package is actually 75% of the length of the JD
package.
Standard and Class B Processing
- SM44C256 ... Standard
-SMJ44C256 ... Class B
(I)
U
:::I
"C
.
PIN NOMENCLATURE
description
The SMJ44C256 is a high-speed, 1,048,576-bit
dynamic random-access memory organized as
262,144 words of four bits each. It employs
state-of-the-art EPIC'" (Enhanced Process
Implanted CMOS) technology for high
performance, reliability, and low power at a low
cost.
AO-AS
Address Inputs
CAS
Column-Address Strobe
DQ1-DQ4
Data In/Data Out
G
Data-Output Enable
RAS
Row-Address Strobe
TF
Test Function
W
Write Enable
Vce
5-V Supply
VSS
Ground
o
a..
~
CO
~
~
operation
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold, and address multiplex is thus eliminated.
The maximum number of columns that may be accessed is determined by the maximum RAS low time and
the CAS page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by column
addresses AO through A9 can be accessed without intervening RAS cycles.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW documents contain information
on products in the formative or design phase of
development. Characteristic data and other
specifications are design goals. Texas Instruments
reserves the right to change or discontinue these
products without notice.
..;opyright © 1988. Texas Instruments Incorporated
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
8-133
..
8-134
SMJ4C1024
1,048,576-8IT DYNAMIC RANDOM-ACCESS MEMORY
FEBRUARY 1988
0
1,048,576 x 1 Organization
0
Single 5-V Supply (10% Tolerance)
0
JD PACKAGE
(TOP VIEW)
D
Performance Ranges:
ACCESS ACCESS ACCESS
0
Q
RAS
CAS
TIME
TIME
TIME
OR
NC
A9
ta(R)
(tRAC)
(MAX)
talC)
(tCAC)
(MAX)
ta(CA)
(tCAA)
(MAX)
WRITE
AO
AS
CYCLE
Al
A7
(MIN)
A2
A6
A3
A5
VCC
A4
120 ns
35 ns
60 ns
230 ns
SMJ4C 1024-1 5
150 ns
45 ns
75 ns
270 ns
sw
-w
>
Enhanced Page Mode
HJ PACKAGEt
(TOP VIEW)
0
CAS-Before-RAS Refresh
0
Long Refresh Period ...
512-Cycle Refresh in 8 ms (Max)
0
READ
SMJ4C 1024-12
SMJ4C1024 Operation
VSS
IN
D
VSS
IN
Q
NC
0
Low Power Dissipation
0
Texas Instruments EPIC'" CMOS Process
0
All Inputs and Clocks Are TTL Compatible
0
High-Reliability Ceramic 18-Pin 300-Mil-Wide
DIP or 20/26 Ceramic Surface Mount (CSOJ)
Package
0
- 55 °C to 125°C Operating Temperature
Range
0
Standard and Class B Processing
-SM4C1024 ... Standard
-SMJ4C1024 ... Class B
c..
NC
A9
NC
3-State Unlatched Output
a:
CAS
RAS
lt)
::;)
AO
AS
Al
A7
A2
A6
A3
A5
C
oa:
..
c..
VCC ........._ _....r- A4
I
tThe packages shown here are for pinout reference only.
The HJ package is actually 75% of the length of the JD
package.
I
rn
.....
CJ
::::I
PIN NOMENCLATURE
description
The SMJ4C 1024 is a high-speed, 1,048,576-bit
dynamic random-access memory organized as
1,048,576 words of one bit each. It employs
state-of-the-art EPIC'" (Enhanced Process
Implanted CMOS) technology for high
performance, reliability, and low power at a low
cost.
AO-AS
Address Inputs
CAS
Column-Address Strobe
D
Data In
NC
No Connection
Q
Data Out
RAS
Row-Address Strobe
TF
Test Function
W
Write Enable
VCC
5-V Supply
VSS
Ground
"C
...o
c.
...>CO
==
~
operation
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is thus eliminated. The
maximum number of columns that may be accessed is determined by the maximum RAS low time and
the CAS page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by column
addresses AO through A9 can be accessed without intervening RAS cycles.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW documents contain information
on products in the formative or design phase of
development. Characteristic data and other
specifications ara design goals. Texas Instrumants
raserves the right to change or discontinue these
products without notice.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
Copyright © 1988. Texas Instruments Incorporated
8-135
~
;:;
Q)
<."
.
oQ.
C
(')
....
en
8-136
SMJ27C128
131,072·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORY
AUGUST 1986-REVISED JULY 1987
•
Organization ... 16K x 8
•
Single 5·V Power Supply
J PACKAGE
(TOP VIEW)
Vpp
A12
•
Pin Compatible with Existing 64K and
128K EPROMs
•
All Inputs/Outputs Fully TTL Compatible
•
Max Access/Min Cycle Time
SMJ27C 128-20
200 ns
SMJ27C128·25
250 ns
SMJ27C128·30
300 ns
•
HVCMOS Technology
•
3-State Output Buffers
Q2
o
400 mV Guaranteed DC Noise Immunity
with Standard TTL Loads
03
•
Low Power Dissipation (VCC = 5.5 V)
-Active ... 220 mW Worst Case
-Standby ... 1.7 mW Worst Case
(CMOS-Input Levels)
A7
A6
A5
A4
A3
A2
Al
AO
Ql
•
GND
--,.,--~-
PIN NOMENCLATURE
Temperature Range ...
- 55°C to 125°C
description
AO-A13
Address Inputs
E
Chip Enable/Power Down
G
Output Enable
GND
Ground
PGM
Program
01-08
Outputs
The SMJ27C128 series are 131,072-bit,
5-V Power Supply
VCC
ultraviolet-light
erasable,
electrically
12.5-V Power Supply
Vpp
programmable read-only memories. These
devices are fabricated using HVCMOS
technology for high speed and simple interface
with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 54 TTL
circuits without the use of external pull-up resistors, and each output can drive one Series 54 TTL circuit
without external resistors. The data outputs are three state for connecting multiple devices to a common
bus. The SMJ27C 128 is pin compatible with existing 28-pin ROMs and EPROMs. It is offered in a dual-inline ceramic package (J suffix) rated for operation from - 55°C to 125°C.
..
Since these EPROMs operate from a single 5-V supply (in the read mode). they are ideal for use in
microprocessor-based systems. One other (12.5 V) supply is needed for programming, but all programming
signals are TTL level. For programming outside the system, existing EPROM programmers can be used.
Locations may be programmed individually, in blocks, or at random.
operation
There are seven modes of operation for the SMJ27C128 listed on the following page. Read mode requires
a single 5-V supply. All inputs are TTL level except for Vpp during programming (12.5 V) and 12 V on
A9 for signature mode.
PRODUCTION DATA documents contain information
current as of publication date. Products conform
to specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
8-137
en
~
(J
:::s
"C
o...
c..
...>
CO
~
~
SMJ27C128
131,072·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORY
MODE
FUNCTION
(PINS)
Read
Output
Disable
Standby
Programming
Verify
Program
Signature
Inhibit
Mode
E
VIL
VIL
VIH
VIL
VIH
VIH
VIL
VIL
VIH
xt
VIH
VIL
VIH
VIL
VIH
VIH
X
VIL
VIH
X
VIH
Vee
Vee
Vee
Vpp
Vpp
Vpp
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
X
X
X
X
X
X
VH~
VHf
X
X
X
X
X
X
VIL
VIH
(20)
G
(22)
PGM
(27)
Vpp
(1)
Vee
(28)
A9
(24)
AO
(10)
eODE
01-08
(11-13.
DOUT
HI-Z
HI-Z
DIN
15-19)
DOUT
HI-Z
MFG
DEVleE
97
04
tx can be VIL or VIH.
iVH = 12V ± 0.5V.
read/output disable
-
When the outputs of two or more SMJ27C 128's are connected in parallel on the same bus, the output
of any particular device in the circuit can be read with no interference from the competing outputs of the
other devices. To read the output of the SMJ27C 128, a low-level signal is applied to the E and G pins.
All other devices in the circuit should have their outputs disabled by applying a high-level signal to one
of these pins. Output data is accessed at pins Q 1 to Q8.
~
power down
;:+'
Active ICC current can be reduced from 40 mA to 500 Jl-A (TTL-level inputs) or 300 Jl-A (CMOS-level inputs)
by applying a high TTL signal to the E pin. In this mode all outputs are in the high-impedance state.
Q)
-<
.o
~
erasure
c.
c
n
.....
Before programming, the SMJ27C128 is erased by exposing the chip through the transparent lid to high
intensity ultraviolet light (wavelength 2537 angstroms). The recommended minimum exposure dose (UV
intensity x exposure time) is fifteen watt-seconds per square centimeter. A typical 12 milliwat per square
centimeter, filterless UV lamp will erase the device in 21 minutes. The lamp should be located about 2.5
centimeters above the chip during erasure. After erasure, all bits are in the high state. It should be noted
that normal ambient light contains the correct wavelength for erasure. Therefore, when using the
SMJ27C 128, the window should be covered with an opaque label.
(I)
fast programming
After erasure (all bits in logic' l' state), logic 'O's are programmed into the desired locations. A programmed
'0' can only be erased by ultraviolet light. Data is presented in parallel (eight bits) on pins Q 1 to Q8. Once
addresses and data are stable, PGM is pulsed. The programming mode is achieved when Vpp = 12.5 V,
VCC = 6.0 V, G = VIH, PGM = VIL, and E = VIL. More than one SMJ27C128 can be programmed when
the devices are connected in parallel. Locations can be programmed in any order.
Programming uses two types of programming pulses: Prime and Final. The length of the Prime pulse is
1 millisecond; this pulse is applied X times. After each Prime pulse, the byte being programmed is verified.
8-138
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SMJ27C128
131,072-BI1 ERASABLE PROGRAMMABLE READ-ONLY MEMORY
If the correct data is read, the Final programming pulse is applied; if correct data is not read, an additional
1 millisecond pulse is applied up to a maximum X of 25. The Final programming pulse is 3X long. This
sequence of programming and verification is performed at Vee = 6.0 V and Vpp = 12.5 V. When the
full fast programming routine is complete, all bits are verified with Vee = Vpp = 5 V (see Figure 1).
program inhibit
Programming may be inhibited by maintaining a high level input on the
E pin
or PGM pin.
program verify
Programmed bits may be verified with Vpp
12.5 V when
G
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode
is activated when A9 (pin 24) is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AO (pin
10) i.e., AO = VIL - manufacturer; AO = VIH - device. All other addresses must be held at VIL. Each
byte possesses odd parity on bit 08. The manufacturer code for this device is 97, and the device code is 04.
DEVICE
FAILED
INCREMENT
ADDRESS
DEVICE
FAILED
FIGURE 1. FAST PROGRAMMING FLOWCHART
TEXAS
..Jtj}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
8-139
SMJ27C128
131,072-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
logic symbol t
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12
A13
E
EPROM 16.384 X 8
0-
(10)
(9)
(8)
(7)
(6)
(5)
(4)
0
(3)
>A16.383
(25)
(24)
(21)
(23)
(2)
(26)
(20)_
b
(22) ......
A\l
A\l
A\l
A\l
Ay
A\l
A\l
A\l
(11 )
(12)
01
02
03
(15)
04
(16)
05
(17)
06
(18)
07
(19)
08
(13)
1~
[PWR OWN]
~EN
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating temperature range (unless otherwise noted) t
Supply voltage range. Vee (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.6 V to 7 V
Supply voltage range. Vpp (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9. . . . . . . . . . . . . . . . . . . ..
- 0.6 V to 6.5 V
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6 V to 13.5 V
Output voltage range (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
- 0.6 V to Vee + 1 V
Minimum operating free-air temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 De
Operating case temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 125 De
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
- 65 De to 150 De
. .
.
"C
o
c.
s:
()
,..
o
NOTE 1: Under absolute maximum ratings. voltage values are with respect to GND.
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
8-140
TEXAS
"'JI
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SMJ27C128
131,072·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORY
recommended operating conditions
SMJ27C128-20
SMJ27C 128-25
UNIT
SMJ27C128-30
Vee
Vpp
Supply voltage (see Note 2)
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
Te
NOM
MAX
4.5
5
5.5
V
V
Supply voltage (see Note 3)
VIH
NOTES:
MIN
V
Vee
2
TTL
Vee-O.2
-0.5
Vee+ 1
Vee +0.2
0.8
eMOS
GND-0.2
GND+0.2
TTL
eMOS
- 55
V
V
V
°e
125
Operating case temperature
°e
2. Vee must be applied before or at the same time as Vpp and removed after or at the same time as Vpp. The device must
not be inserted into or removed from the board when Vpp or Vee is applied.
3. Vpp can be connected to Vee directly (except in the program mode). Vee supply current in this case would be lee + Ipp.
During programming, Vpp must be maintained at 12.5 V (± O. 5V).
electrical characteristics over full ranges of recommended operating conditions
TEST CONDITIONS
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
IpP1
Vpp supply current
= -400 pA
10L = 2.1 mA
VI = 0 V to 5.5 V
Vo = 0 V to Vee
Vpp = Vee = 5.5' V
10H
Vpp supply current:!:
IpP2
Vee supply current
lee1
lee2
(standby)
I TTL-input level
I CMOS-input level
Vee supply current (active)
Typt
MAX
UNIT
V
2.4
0.4
V
±10
pA
±10
pA
100
p.A
50
mA
Vee
500
pA
Vee
300
pA
25
mA
Vpp
(during program pulse)
MIN
=
13 V
= 5.5 V, E = VIH
= 5.5 V, E = Vee
Vee = 5.5 V, E = VIL,
tcycle = minimum cycle time,
30
10
..
en
1:)
::s
.
"'0
outputs open
o
a..
tTypical values are at T A = 25°e and nominal voltages.
:!:This parameter has been characterized at 25°C and is not tested.
~
ca
~
:E
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
8-141
SMJ27C128
131,072·BI1 ERASABLE PROGRAMMABLE READ·ONLY MEMORY
capacitance,
Te
1 MHzt
25°e, f
TEST CONDITIONS
PARAMETER
Ci
Input capacitance
Co
Output capacitance
MIN
= 0 V, f = 1 MHz
Vo = 0 V, f = 1 MHz
VI
TYPJ:
MAX
6
10
pF
8
14
pF
UNIT
t Capacitance measurements are made on sample basis only.
J:Typical values are at T A = 25 DC and nominal voltages.
switching characteristics over full ranges of recommended operating conditions (see Note 4)
TEST CONDITIONS
PARAMETER
(SEE' NOTES 4 AND 5)
'27C128-20
'27C128-25
'27C128-30
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
talA)
Access time from address
200
250
300
ns
talE)
Access time from chip enable
200
250
300
ns
ten(G)
Output enable time from G
75
100
120
ns
105
ns
Output disable time from G or
tdis
E,
See Figure 2.
0
whichever occurs first t
60
0
60
0
Output data valid time after
change of address,
tv(A)
G,
E.
or
0
ns
0
0
whichever occurs first t.
NOTES: 4. For all switching characteristics and timing measurements, input pulse levels are 0.40 V to 2.4 V and Vpp = 12.5 V ± 0.5 V
during programming. tr ::5 20 ns and tf ::5 20 ns.
5. Common test conditions apply for tdis(G) except during programming.
tValue calculated from 0.5 V delta to measured output level. This parameter is only sampled and not 100% tested.
..
recommended timing requirements for programming, TA
(see Note 4)
=
25°e, Vee
=
6 V, Vpp
12.5 V
MIN
NOM
MAX
tw(lPGM)
Initial program pulse duration
0.95
1
1.05
ms
tw(FPGM)
Final pulse duration
2.85
78.75
ms
tsu(A)
Address setup time
2
tsu(G)
G setup time
2
Q)
tdis(G)
Output disable time from G
0
-<
ten(GI
Output enable time from
...
tsu(D)
Data setup time
2
p's
tsu(VPP)
VPP setup time
2
p's
Co
tsu(VeC)
Vec setup time
2
p's
...en
th(A)
Address hold time
0
p'S
th(D)
Data hold time
2
p's
~
;::;."
""C
o
C
(')
NOTES:
8-142
G
p's
p'S
130
150
4. For all switching characteristics and timing measurements input pulse levels are 0.40 V to 2.4 V and VPP
during programming.
5. Common test conditions apply for tdis(G) except during programming.
-I!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
UNIT
= 12.5 V
ns
ns
± O. 5 V
SMJ27C128
131,072·BI1 ERASABLE PROGRAMMABLE READ·ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.08 V
UND~~~:~~ ----J
1
RL
0
800 0
CL - 100 pF
FIGURE 2. OUTPUT LOAD CIRCUIT
read cycle timing
AO-A13
X
X
ADDRESSES VALID
I
I
I
I
-G
I
y
01-08
I
\
\
HI-Z
talA)
~
«««
TEXAS
-I
\4
t V (A)--f4--1
OUTPUT
VALID
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
VIH
Y
I
-I
VIL"
I
I
\4 ten(G)
VIH
I
-I
\ . . - talE)
I
I
I
I.
VIL
I
I
E
VIH
HOUSTON. TEXAS 77001
VIL
:::s
..
..>
"C
0
tdis
Q.
I
})}
....0CJ
VOH
HI-Z-VOL
8-143
CO
:l:
~
I
SMJ27C128
131,072·BI1 ERASABLE PROGRAMMABLE READ·ONL Y MEMORY
program cycle timing
P R O G R A M - - - - ; - - - - VERIFY--1
I
I
..
VIH
VIL
,
VIH
I
PGM
I
VIL
ten{GII
I
I
8-144
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
VIH
VIL
SMJ27C256
262,144·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORY
MAY 1986-REVISED JULY 1987
•
Organization ... 32K x 8
0
Single 5-V Power Supply
0
Pin Compatible with Existing 128K and
256K EPROMs
•
•
J PACKAGE
(TOP VIEW)
All Inputs/Outputs Fully TTL Compatible
Vpp
Vee
A12
A7
A14
A13
A6
A5
Max Access/Min Cycle Time
SMJ27C256-20
200 ns
SMJ27C256-25
250 ns
SMJ27C256-30
300 ns
A4
A3
A2
A1
•
HVCMOS Technology
AO
•
3-State Output Buffers
•
400 mV Guaranteed DC Noise Immunity
with Standard TTL Loads
01
02
03
•
Low Power Dissipation (VCC = 5.5 V)
-Active ... 220 mW Worst Case
-Standby ... 1.7 mW Worst Case
(CMOS-Input Levels)
•
•
A8
A9
GND
A11
G
A10
E
-....----
08
07
06
05
04
PIN NOMENCLATURE
AO-A14
Address Inputs
E
Chip Enable/Power Down
Temperature Range ...
-55 D C to 125 D C
G
Output Enable
GND
Ground
MIL-STD-883C Class B
High-Reliability Processing
01-08
Outputs
VCC
Vpp
5-V Power Supply
12.5-V Power Supply
description
The SMJ27C256 series are 262.144-bit. ultraviolet-light erasable. electrically programmable read-only
memories. These devices are fabricated using HVCMOS technology for high speed and simple interface
with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 54 TTL
circuits without the use of external pull-up resistors. and each output can drive one Series 54 TTL circuit
without external resistors. The data outputs are three state for connecting multiple devices to a common
bus. The SMJ27C256 is pin compatible with existing 28-pin ROMs and EPROMs. It is offered in a dual-inline ceramic package (J suffix) rated for operation from - 55 DC to 125 DC.
Since these EPROMs operate from a single 5-V supply (in the read mode). they are ideal for use in
microprocessor-based systems. One other (12.5 V) supply is needed for programming. but all programming
signals are TTL level. For programming outside the system. existing EPROM programmers can be used.
Locations may be programmed singly. in blocks. or at random.
operation
There are seven modes of operation for the SMJ27C256 listed on the following page. Read mode requires
a single 5-V supply. All inputs are TTL level except for Vpp during programming (12.5 V) and 12 V on
A9 for signature mode.
PRODUCTION DATA documents contain information
current as of publication date. Products conform
to specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily inclu~e testing of all parameters.
Copyright
1986, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-145
..
SMJ27C256
262,144·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORY
MODE
FUNCTION
(PINS)
Read
Output
Disable
Standby
Programming
Verify
Program
Signature
Inhibit
Mode
E
VIL
VIL
VIH
VIL
VIH
VIH
VIL
G
(22)
VIL
VIH
xt
VIH
VIL
VIH
VIL
Vpp
(1)
Vee
' Vee
Vee
Vpp
Vpp
Vpp
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
X
X
X
X
X
X
VH~
VH~
X
X
X
X
X
X
VIL
VIH
DOUT
HI-Z
HI-Z
DIN
DOUT
HI-Z
MFG
DEVICE
97
04
(20)
Vee
(28)
A9
(24)
AO
(10)
01-08
(11-13.
CODE
15-19)
tx can be VIL or VIH.
~VH = 12 V ± 0.5 V.
read/output disable
When the outputs of two or more SMJ27C256's are connected in parallel on the same bus, the output
of any particular device in the circuit can be read with no interference from the competing outputs of the
other devices. To read the output of the SMJ27C256, a low-level signal is applied to the E and G pins.
All other devices in the circuit should have their outputs disabled by applying a high-level signal to one
of these pins. Output data is accessed at pins 01 to 08.
power down.'
~
Active ICC current can be reduced from 40 mA to 500 p..A (TTL-level inputs) or 300 p..A (CMOS-level inputs)
by applying a high TTL signal to .the E pin. In this mode all outputs are in the high-impedance state.
..
o..
;::;.'
D)
-<
erasure
"a
Before programming, the SMJ27C256 is erased by exposing the chip through the transparent. lid to high
intensity ultraviolet light (wavelength 2537 angstroms). The recommended minimum exposure dose (UV
intensity x expos'ure time) is fifteen watt-seconds per square centimeter. A typical 12 milliwat per square
centimeter, filterless Uy lamp 'will erase the device in 21 minutes. The lamp should be located about 2.5
centimeters above the chip during erasure. After erasure, all bits are in the high state. It should be noted
that normal ambient light contains the correct wavelength for erasure. Therefore, when using the
SMJ27C256, the window should be covered with an opaque label.
0-
r::
(')
,..
en
fast programming
After erasure (all bits in logic' l' state). logic 'O's are programmed into the desired locations. A programmed
'0' can only be erased by ultraviolet light. Data is presented in parallel (eight bits) on pins 01 to 08. Once
addresses and data are stable, E is pulsed. The programming mode is achieved when Vpp = 12.5 V,
VCC = 6.0 V, G = VIH, and E = VIL. More than one SMJ27C256 can be programmed when the devices
are connected in parallel. Locations can be programmed in any order.
Programming uses two types of programming pulses: Prime and Final. The length of the Prime pulse is
1 millisecond; this pulse is applied X times. After each Prime pulse, the byte being programmed is verified.
If the correct data is read, the Final programming pulse is applied; if correct data is not read, an additional
8-146
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ27C256
262,144·BI1 ERASABLE PROGRAMMABLE READ·ONLY MEMORY
1 millisecond pulse is applied up to a maximum X of 25. The Final programming pulse is 3X long. This
sequence of programming and verification is performed at Vee = 6.0 V and Vpp = 12.5 V. When the
full fast programming routine is complete. all bits are verified with Vee = Vpp = 5 V (see Figure 1).
program inhibit
Programming may be inhibited by maintaining a high level input on the
E pin.
program verify
Programmed bits may be verified with Vpp
12.5 V when G
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode
is activated when A9 (pin 24) is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AO (pin
10) i.e .• AO = VIL - manufacturer; AO = VIH - device. All other addresses must be held at VIL. Each
byte possesses odd parity on bit 08. The manufacturer code for this device is 97. and the device code is 04.
DEVICE
FAILED
INCREMENT
ADDRESS
..
I
DEVICE
FAILED
3X ms DURATION
FIGURE 1. FAST PROGRAMMING FLOWCHART
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-147
SMJ27C256
262,144·BIT ERASABLE PROGRAMMABLE READ·ON LY MEMORY
logic symbol t
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
E
(10)
(9)
E!ROM 32.768 X 8
0
(8)
(7)
(6)
(5)
(4)
(3)
(25)
~
A
0
32.767
(24)
(21)
(23)
(2)
(26)
(27)
(20)
~
(22) ........
A'V
A'V
A'V
A'V
A'V
A'V
A'V
A'V
(11 )
(12)
(13)
(15)
(16)
(17)
(18)
(19)
01
02
03
04
05
06
07
08
14
[PWR DWN)
rl
EN
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
_
•
absolute maximum ratings over operating temperature range (unless otherwise noted) t
Supply voltage range. Vee (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.6 V to 7 V
Supply voltage range. Vpp (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9. . . . . . . . . . . . . . . . . . . ..
- 0.6 V to 6.5 V
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6 V to 13.5 V
Output voltage range (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
- 0.6 V to Vee + 1 V
Minimum operating free-air temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e
Maximum operating case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 125 De
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
- 65 °e to 150 °e
~
.
.
::+
~
<
."
o
Co
r::
...en
C')
NOTE 1: Under absolute maximum ratings. voltage values are with respect to GND.
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute·maximum·rated conditions for extended periods may affect
device reliability.
8-148
. TEXAS
-I/}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ27C256
262,144·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORY
recommended operating conditions
SMJ27C256-20
SMJ27C256-25
UNIT
SMJ27C256-30
Vce
Supply voltage (see Note 2)
Vpp
Supply voltage (see Note 3)
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
TC
NOTES:
MIN
NOM
MAX
4.5
5
5.5
TTL
V
V
Vee
2
Vee· 1
V
Vee + 0.2
V
TTL
Vee- O.2
- 0.5
0.8
V
CMOS
GNO-0.2
GNO+0.2
CMOS
- 55
V
°e
Operating case temperature
125
°c
2. Vee must be applied before or at the same time as Vpp and removed after or at the same time as Vpp. The device must
not be inserted into or removed from the board when Vpp or VCC is applied.
3. Vpp can be connected to VCC directly (except in the program mode). Vce supply current in this case would be ICC + Ipp.
During programming, Vpp must be maintained at 12.5 V (±0.5V).
electrical characteristics over full ranges of recommended operating conditions
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
IpPl
Vpp supply current
TEST CONDITIONS
= -400 p.A
10L = 2.1 mA
VI = 0 V to 5.5 V
Vo = 0 V to Vee
Vpp = Vee = 5.5
Vpp supply current ~
IpP2
(during program pulse)
Vec supply current
ICCl
ICC2
(standby)
I TTL-input level
I CMOS-input level
Vee supply current (active)
MIN
Typt
MAX
2.4
IOH
UNIT
V
V
0.4
V
±1O
I,A
±10
I,A
100
/,A
50
mA
Vpp
=
13 V
Vee
=
5.5 V, E
VIH
500
p.A
Vec
=
5.5 V, E
Vec
300
/,A
Vee
=
5.5 V,
VIL,
25
mA
35
=
=
E=
tcycle = minimum cycle time,
outputs open
10
..
tTypical values are at T A = 25°C and nominal voltages.
~This parameter has been characterized at 25°C and is not tested.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-149
SMJ27C256
262,144·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORY
capacitance,
Te
1 MHz t
25°e, f
PARAMETER
Ci
Input capacitance
Co
Output capacitance
TEST CONDITIONS
MIN
= 0 V, f = 1 MHz
Vo = 0 V, f = 1 MHz
VI
Typt
MAX
6
9
pF
8
12
pF
UNIT
t Capacitance measurements are made on sample basis only.
tTypical values are at TC = 25°C and nominal voltages.
switching characteristics over full ranges of recommended operating conditions (see Note 4)
TEST CONDITIONS
PARAMETER
(SEE NOTES 4 AND 51
'27C256-20
'27C256-25
'27C256-30
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
talA)
Access time from address
200
250
300
ns
talE)
Access time from chip enable
200
250
300
ns
ten(G)
Output enable time from G
75
100
120
ns
105
ns
CL
Output disable time from G or
tdis
E.
change of address,
G,
E.
0
Input tr ::5 20 ns,
whichever occurs first t
60
0
60
0
Input tf ::5 20 ns
Output data valid time after
tv(A)
= 100 pF,
1 Series 54 TTL Load,
or
0
0
0
ns
whichever occurs first t
NOTES: 4. For all switching characteristics and timing measurements, input pulse levels are 0.40 V to 2.4 V and Vpp = 12.5 V ± O. 5 V
during programming.
5. Common test conditions apply for tdis(GI except during programming.
tValue calculated from 0.5 V delta to measured output level. This parameter is only sampled and not 100% tested.
recommended timing requirements for programming, TA
(see Note 4)
~
..
<
..o
;:;'
e»
'tJ
Q.
C
,..
(")
en
25°e, Vee
=
6 V, Vpp
12.5 V
MIN
NOM
MAX
UNIT
tw(lPGM)
Initial program pulse duration
0.95
1
1.05
ms
tw(FPGM)
Final pulse duration
2.85
78.75
ms
tsu(A)
Address setup time
2
p'S
tsu(G)
G setup time
2
P.s
tdis(G)
Output disable time from G
0
ten(G)
Output enable time from G
130
ns
150
ns
tsu(D)
Data setup time
2
P.s
tsu(VPP)
VPP setup time
2
p's
tsu(VCC)
VCC setup time
2
p'S
th(A)
Address hold time
0
th(D)
Data hold time
2
P.s
p'S
NOTES:
8-150
=
4. For all switching characteristics and timing measurements input pulse levels are 0.40 V to 2.4 V and VPP
during programming.
5. Common test conditions apply for tdis(G) except during programming.
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
= 12.5 V
± 0.5 V
SMJ27C256
262,144·BI1 ERASABLE PROGRAMMABLE READ·ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.08 V
OUTPUT
UNDER TEST
----!1
RL = 800 fl
CL = 100 pF
FIGURE 2. OUTPUT LOAD CIRCUIT
read cycle timing
AO-A14
x:
~
J/
ADDRESSES VALID
I
I
I
I
-G
\ Ics---
Q1-Q8 - - - - - - HI-Z
I
talA)
VIH
VIL
I
talE)
\
I
I
I
I..
VIL
I
I
I
VIH
"'I
I
I
\4 tenlG) +I
«««
...1
VIH
Y
1
VIL
... , tdis
loCI
t V IA
)-+-----1
OUTPUT
VALID
en
.....
I
}»
..
CJ
VOH
~
.
.>-
"C
HI-Z--
0
VOL
c..
CO
~
~
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-151
SMJ27C256
262,144·BI1 ERASABLE PROGRAMMABLE READ·ONLY MEMORY
program cycle timing
PROGRAM - - - -....~~i4.-- VERIFY~
Vee+ 1
Vee
VIH
I
I
-
-I
I
I
ten(G)
I
!
~
;:;'"
...
""tJ
...
o
Q)
<
c.
c:
n
....
en
8-152
TEXAS
VIL
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
VIH
VIL
SMJ27C512
524,288-B11 UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SEPTEMBER 1987 - REVISED DECEMBER 1987
•
Organization... 64K x 8
•
Single 5-V Power Supply
•
Pin Compatible with Existing 512K EPROMs
•
All Inputs/Outputs Fully TTL Compatible
•
Max Access/Min Cycle Time
'27C512-20
200 ns
'27C512-25
250 ns
'27C512-30
300 ns
J PACKAGE
(TOP VIEW)
A10
E
HVCMOS Technology
o
3-State Output Buffers
o
Latchup Immunity of 250 mA on all Input
and Output Pins
•
400 mV Guaranteed DC Noise Immunity
with Standard TTL Loads
•
Low Power Dissipation (VCC
5.5 V)
- Active ... 263 mW (MAX)
- Standby ... 1.8 mW (MAX)
(CMOS Input Levels)
•
A14
A13
A8
A9
A11
G/Vpp
•
o
Vee
A15
A12
A7
A6
A5
08
07
06
01
05
GND ---' _ _~ 04
PIN NOMENCLATURE
- 55 DC to 125 DC Operating Temperature
Range
Standard and Class B Processing
- SM27C512 ... Standard
- SMJ27C512 ... Class B
AO-A15
Address Inputs
E
Chip Enable/Power Down
GND
Ground
01-08
Outputs
VCC
5-V Power Supply
G/Vpp
12.5-V Power Supply/
Outp'ut Enable
description
The SMJ27C512 series is a 524,288-bit, ultraviolet-light erasable, electrically programmable read-only
memory. This device is fabricated using HVCMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 54 TTL circuits
without the use of external pull-up resistors, and each output can drive one Series 54 TTL circuit without
external resistors. The data outputs are three-state for connecting multiple devices to a common bus. The
SMJ27C512 is pin compatible with existing 28-pin ROMs and EPROMs. It is offered in a dual-in-line ceramic
package (J suffix) rated for operation from - 55 DC to 125 DC.
Since this EPROM operates from a single 5-V supply (in the read mode), it is are ideal for use in
microprocessor-based systems. One other (12.5 V) supply is needed for programming, but all programming
signals are TTL level. For programming outside the system, existing EPROM programmers can be used.
Locations may be programmed singly, in blocks, or at random.
operation
There are seven modes of operation for the SMJ27C512 listed on the following page. Read mode requires
a single 5-V supply. All inputs are TTL level except for Vpp during programming (12.5 V) and 12 V on
A9 for signature mode.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Copyright © 1987 Texas Instruments Incorporated
8-153
....en
(,)
:::l
"'C
.
..
o
0..
>-
ca
~
~
SMJ27C512
524,288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
MODE
FUNCTION
(PINS)
Read
E
(20)
VIL
G/Vpp
(22)
Output
Program
Signature
Inhibit
Mode
ViL
VIH
VIL
Vpp
VIL
Vpp
VIL
Vee
Vee
Vee
Vee
Vee
X
X
X
X
X
VH~
VH~
x
x
x
x
X
VIL
VIH
Standby
Programming
Verify
VIL
VIH
VIL
VIL
VIH
xt
Vee
(28)
Vee
Vee
A9
(24)
X
AO
(10)
X
Disable
01-08
(11-13.
eODE
DOUT
HI-Z
HI-Z
DIN
15-19)
DOUT
HI-Z
MFG
DEVICE
97
85
tx
ean be VIL or VIH.
1=VH = 12 V ± 0.5 V.
read/output disable
When the outputs of two or more SMJ27C512s are connected in parallel on the same bus. the output of any
particular device in the circuit can be read with no interference from the competing outputs of the other devices.
To read the output of the SMJ27C512. a low-level signal is applied to the E and G/Vpp pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins 01 to 08.
power down
Active ICC current can be reduced from 50 mA to 500 p.A (TTL-level inputs) or 350 p.A (CMOS-level inputs)
by applying a high logic signal to the E pin. In this mode all outputs are in the high-impedance state.
~
~
erasure
...
...
o"
m
Before programming, the SMJ27C512 is erased by exposing the chip through the transparent lid to high
intensity ultraviolet light (wavelength 2537 angstroms). The recommended minimum exposure dose (UV
intensity x exposure time) is 15 watt-seconds-per-square-centimeter. A typical 12 milliwatt-per-squarecentimeter, filterless UV lamp will erase the device in 21 minutes. The lamp should be located about 2.5
centimeters above the chip during erasure. After erasure, all bits are in the high state. It should be noted that
normal ambient light contains the correct wavelength for erasure. Therefore, when using the SMJ27C512,
the window should be covered with an opaque label.
-<
Co
c
...
n
en
fast programming
After erasure (all bits in logic 1 state). logic Os are programmed into the desired locations. A programmed 0
can be erased only by ultraviolet light. Data is presented in parallel (eight bits) on pins 01 to 08. Once addresses
and data are stable, Eis pulsed. The programming mode is achieved when G/Vpp = 12.5 V, VCC = 6.0V, and
E = VIL. More than one SMJ27C512 can be programmed when the devices are connected in parallel.
Locations can be programmed in any order.
Programming uses two types of programming pulses: Prime and Final. The length of the Prime pulse is 1
millisecond; this pulse is applied X times. After each Prime pulse, the byte being programmed is verified. If
the correct data is read, the Final programming pulse is applied; if correct data is not read, an additional 1
millisecond pulse is applied upto a maximum X of 25. The Final programming pulse is 3X long. This sequence
of programming and verification is performed at VCC = 6.0 V. When the full Fast programming routine is
complete, all bits are verified with VCC = 5 V (see Figure 1).
8-154
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SMJ27C512
524,288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
program inhibit
Programming may be inhibited by maintaining a high level input on the E pin.
program verify
Programmed bits may be verified with G/Vpp and EVIL.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode
is activated when A9 (pin 24) is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AO (pin
10); i.e., AO = VIL accesses the manufacturer code; AO = VIH accesses the device code. All other addresses
must be held at VIL. Each byte possesses odd parity on bit 08. The manufacturer code for this device
is 97, and the device code is 85.
latchup immunity
Latchup immunity on the SMJ27C512 is minimum of 250 mA on all inputs and outputs. This feature provides
latchup immunity beyond any potential transients at the P.C. board level when the EPROM is interfaced
to industry standard TTL or MOS logic devices. Input-output layout approach controls latchup without
compromising performance or packing density.
For more information see application report SMLA001; "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family, " available through TI Field Sales Offices.
..
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
8-155
SMJ27C512
524,288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
-
INCREMENT
ADDRESS
~
;::;."
I»
-<
..oc.
"'C
c
(")
~
en
FIGURE 1. FAST PROGRAMMING FLOWCHART
8·156
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
SMJ27C512
524,288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
logic symbol t
AO
A1
A2
A3
A4
A5
A6
A7
AS
A9
A10
A11
A12
A13
A14
A15
E
(10)
(9)
(S)
(7)
(6)
(5)
A'V
(4)
A'V
(3)
0
>A-65,535
(25)
(24)
A'V
(2)
A'V
(26)
(20)
A'V
A'V
(23)
(27)
(1 )
A'V
A'V
(21)
(22)
G/Vpp
EPROM 65,536 XS
0 ....
(11 )
(12)
(13)
(15)
(16)
(17)
(1S)
(19)
01
02
03
04
05
06
07
OS
15
[PWR OWN)
1;: ~EN
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
Supply voltage range, Vee (see Note 1) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.6 V to 7 V
Supply voltage range, Vpp (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . -0.6 to 6.5 V
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6Vto13.5V
Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to Vee + 1 V
Minimum operating free-air temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55 DC
Maximum operating case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 DC
Storage temperature range ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 DC to 150 DC
..
NOTE 1: Under absolute maximum ratings, voltage values are with respect to GND.
t Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
S-157
( I)
~
CJ
::l
"C
...o
c..
...>CO
~
~
SMJ27C512
524,288-BI1 UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
recommended operating conditions
SM/SMJ27C512-25
UNIT
SM/SMJ27C512-30
SM/SMJ27C512-45
Vee
Supply voltage (see Note 21
Vpp
Supply voltage (see Note 31
VIH
High·level input voltage
CMOS
TTL
Low·level input voltage
TA
Operating free-air temperature
Te
Operating case temperature
NOM
MAX
4.5
5
5.5
CMOS
V
V
Vee
TTL
VIL
MIN
2
Vee+ 1
V
Vee - 0.2
Vee+ 0 . 2
V
-0.5
0.8
V
GND - 0.2
GND +0.2
- 55
V
°e
125
°e
NOTES: 2. Vee must be applied before or at the same time as Vpp and removed after or at the same time as Vpp. The device must
not be inserted into or removed from the board when Vpp or Vee is applied.
3. Vpp can be connected to Vee directly (except in the program model. Vee supply current in this case would be ICC + Ipp.
During programming, Vpp must be maintained at 12.5 V (± 0.5 VI.
electrical characteristics over full ranges of recommended operating conditions
PARAMETER
..
TEST CONDITIONS
= -400 p.A
= 2.1 mA
VI = 0 V to 5.5 V
Vo = a V to Vee
G/Vpp = 13 V
Vee = 5.5 V, E = VIH
Vee = 5.5 V, E = Vee
Vee = 5.5 V, E = VIL,
tcycle = minimum cycle time,
VOH High-level output voltage
VOL Low-level output voltage
10H
IOL
II
Input current (leakage)
10
Output current (leakage)
Ipp
Vpp supply current (during program pulse)
Vee supply current
lee1
(standby)
I TTL-input level
I CMOS-input level
Ice2 Vee supply current (active)
outputs open
tTypical values are at T A
8-158
25°C and nominal voltages.
TEXAS
-I!}
INSTRUMENTS
POST' OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MIN Typt
MAX
2.4
UNIT
V
35
35
0.4
V
±10
p.A
±10
p.A
70
mA
500
p.A
350
p.A
50
mA
SMJ27C512
524,288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
capacitance over recommended supply voltage range and operating free-air temperature range,
f == 1 MHz
PARAMETER
TEST CONDITIONS
MIN
Ci
Input capacitance
VI = 0 V, f = 1 MHz
Co
Output capacitance
Vo = 0
CG/Vpp
G/Vpp input capacitance
G/Vpp = 0 V, f = 1 MHz
V,
f = 1 MHz
Tvpt
UNIT
6
pF
8
pF
20
pF
tTypical values are at T A = 25°C and nominal voltages.
TEST CONDITIONS
PARAMETER
(SEE NOTE 4)
'27C512-20
MIN
MAX
'27C512-25
'27C512-30
MIN
MIN
MAX
MAX
UNIT
talA)
Access time from address
200
250
300
ns
talE)
Access time from chip enable
200
250
300
ns
ten(G)
Output enable time from G
75
100
120
ns
105
ns
Output disable time from G or
tdis
E,
tv(A)
change of address,
whichever occurs first:):
See Figure 2
0
60
0
60
0
Output data valid time after
G,
E,
or
0
0
0
ns
whichever occurs first:):
:):Value calculated from 0.5 V delta to measured output level.
NOTE 4: For all switching characteristics and timing measurements input pulse levels are 0.4 V to 2.4 V. Timing measurements are made
at 2.0 V for logic 1 and 0.8 V for logic 0 (reference page 8, AC testing waveforms).
..
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
8-159
SMJ27C512
524,288·BI1 UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
12.5 V
6 V, Vpp
recommended timing requirements for programming, T A
(see Note 4)
MIN
NOM
MAX
UNIT
tw(lPGM)
Initial program pulse duration
0.95
1
1.05
ms
tw(FPGM)
Final pulse duration
2.85
78.75
ms
tsu(A)
Address setup time
2
tdis(G)
Output disable time from G
0
tEHD
Data valid from E low
pS
130
ns
1
ps
tsu(D)
Data setup time
2
ps
tsu(VPP)
VPP setup time
2
ps
tsu(vee)
Vee setup time
2
ps
th(A)
Address hold time
0
pS
th(D)
Data hold time
tr(PG)G
VPP rise time
2
ps
50
th(VPP)
ns
VPP hold time
2
trec(PG)
ps
VPP recovery time
2
ps
NOTE 4: For all switching characteristics and timing measurements input pulse levels are 0.4 V to 2.4 V. Timing measurements are made
at 2.0 V for logic 1 and 0.8 V for logic 0 (reference below).
PARAMETER MEASUREMENT INFORMATION
..
2.08 V
OUTPUT
UNDER TEST
~
;:;
---J1
Rl
=
800 fl
Cl = 100 pF
I»
-<
.o
FIGURE 2. OUTPUT LOAD CIRCUIT
""C
Co
C
2.4 V - - - - - . . , \ } ( 2 0 V
...en
(')
0.40 V _ _ _ _ _
20 V"\;
--'~~_:.;:0;.:,;.8;;..V.;...------....;;0.;.;.8;..V.;.~~\.._ _ _ _ _ __
AC testing input/output wave forms
A.C. testing inputs are driven at 2.4 V for logic 1 and 0.4 V for logic O. Timing measurements are made
at 2.0 V for logic 1 and 0.8 V for logic O.
8-160
TEXAS
-I/}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SMJ27C512
524,288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
read cycle timing
...IIX""_________:::
.JX""____
AO-A15 _ _ _ _ _ _
A_D_DR_E_S_SE_S_V_A_Ll_D_ _ _
i
1
-------+-!-"""'\. ._________""IH~,f!
1
E
1
---------VIH
1
..
, .........- - t a ( E I - -....~1
1
\1"0---.. !. ---'1M.'Ir~---"'-I-td-is-----::~
i
G/Vpp
VIL
1 1
ten(GI-Ip..ClO----Cl
..~1
1
• tv(AI ..
, --------..,
I.......
-.....----ta(AI~;:;:;:;;:::
. .~I-----.j.·
Q1-Q8-------HI-Z------4(~(f-+(..{-4(i-(~ O~;~~T
1
»J
-II
VOH
HI-Z-
VOL
program cycle timing
AO-A'5
J ___________
~ OAT~ STASLE i
r-
KVIH
th(AI~
I--tsu(AI-+i
a,-as
IN
tsu(D)
G/Vpp
..
A_DD_R_E_SS_ST_A_B_LE_ _ _ _ _ _ _ _ __
-+j
r-tSU(VPPI~
I
I
VIH'
VOH
HI-2----<
1
.....I---I~~Ir- th(D)
~
I
I
Ir"""th(VPPI--+i
I
~
r--r-tW(lPGMI
I ~'w"PGM'
VIL'
VOL
en
.....
(J
I
r
II
tdiS(EI-,
I
I
1."uIVCC'.,Vr----------I
I
DATA OUT VALID
j+-tEHD
rtr(PG'G
I
VIL
:s
"C
0
Vpp
...
c..
>
...
VIL
I
I
ca
:!:
~
VIH
VIL
Vee+1
Vee
Vee
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
8-161
I
SMJ27C512
524,288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TYPICAL SMJ27C512 CHARACTERISTICS
STANDBY SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
1.50
~
Vee - 5.0 V
u
'" - -----r-.........
1.00
0.75
0.50
-75 -50
1.50
:;
-.... i".....
1.25
STANDBY SUPPLY CURRENT
vs
SUPPLY VOLTAGE
-25
0
25
50
75
100
>
c.'C
Co CD
:l
~E
1.00
0
1ii!!;
iii
0.75
I
0.50
4.25
125
./
/
4.5
TA-Free-Air Temperature- °e
"',
..
t:
U
~
-------
~
0.75
0.50
-75
-a:g
1.50
-25
o
25
50
75
100
125
1.25
CoN
:l::
.~
.,V
0
~!!; 0.75
~
.
....(')en
'en:,:
"~
"ct" E'0"
1.00
ct
0.75
CD
I !!;
t-
~
1.25
..,....,..... V
.-'
0.50
-75 -50
.........-
0.50
4.25 4.5
~
t-"i
'" N
(I):,:
CD '"
/'
0
25
1.25
~~
1.00
ct
4.75
5.0
0.75
---
5.25
5.5
5.75
--
............... i""--.
I !!;
50
75
100
0.50
4.25
125
TA-Free-Air Temperature- °e
8-162
--
TA=25°e
CD
.5 _
t-
-25
~
1.50
CD
t-"t:I
~
V
ACCESS TIME
vs
SUPPLY VOLTAGE
Vee=5.0 V
.5 _
5.75
vee-Supply Voltage-V
1.50
o
c.
5.5
N
5:?
ACCESS TIME
vs
FREE-AIR TEMPERATURE
<"0
5.25
I
TA-Free-Air Temperature- °e
D)
5.0
TA=25°e
f=MAX
en
'" 1.00
CD E
U
-50
;+
c
~
:;
1.00
4.75
~
ACTIVE SUPPLY CURRENT
vs
SUPPLY VOLTAGE
Vee=5.0 V
1.25
/'
V
vee-Supply Voltage-V
ACTIVE SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
1.50
..,V
N
en ~
"t:I
TA=25°e
1.25
4.5
4.75
5.0
5.25
5.5
Vee-Supply Voltage-V
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
5.75
SMJ27C010
1,048,576·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
MARCH 1988-REVISED JULY 1988
•
Organization ... 128K x 8
o
Single 5-V Power Supply
o
Industry Standard 32-Pin Dual-In-line
Package
o
All Inputs/Outputs Fully TTL Compatible
J PACKAGE
(TOP VIEW)
o
Static Operation (No Clocks, No Refresh)
o
Max Access/Min Cycle Time
Vpp
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
01
02
03
VCC± 10%
SMJ27C010-25
SMJ27C010-30
o
o
250 ns
300 ns
8-Bit Output For Use in MicroprocessorBased Systems
32-Bit Programming (Four Bytes) and
Standard 8-Bit Programming
o
Power Saving CMOS Technology
o
3-State Output Buffers
o
o
$
->w
W
07
06
05
04
GND
a:
c..
l-
PIN NOMENCLATURE
Uses TI's Innovative ACE (Advanced
Contactless EPROM) Technology for Noise
Immunity and Improved Reliability
400 mV Guaranteed DC Noise Immunity
with Standard TTL Loads
o
No Pull-Up Resistors Required
o
Low Power Dissipation (VCC = 5.5 V)
-Active ... 220 mW Worst Case
-Standby ... 1.5 mW Worst Case
(CMOS-Input Levels)
o
A10
AD-A16
Address Inputs
E
Chip Enable
G
Output Enable
GND
Ground
NC
No Connection
J5ITM
Program
Ql-Q8
Outputs
VCC
5-V Supply
l2.5-V Power Supply t
vPP
t)
::>
c
oa:
0.
...tn
tOnly in program mode.
CJ
:::l
"'C
o...
Operating Free-Air Temperature - 55 DC to
125 DC
D.
...>-CO
description
The SMJ27C01 0 series are 1 ,048,576-bit, ultraviolet-light erasable electrically programmable read-only
memories. These devices are fabricated using CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 54 TTL circuits.
Each output can drive one Series 54 TTL circuit without external resistors. The data outputs are threestate for connecting multiple devices to a common bus. The SMJ27C010 is offered in a 600-mil dual-inline cerdip package (J suffix) rated for operation from - 55 DC to 125 DC.
Since these EPROMs operate from a single 5-V supply (in the read mode), they are ideal for IJse in
microprocessor-based systems. One other (12.5 V) supply is needed for programming. All programming
signals are TTL level. For programming outside the system, existing PROM programmers can be used.
PRODUCT PREVIEW documents contain information
on products in the formative or design phlSe of
development. Characteristic data and other
specifications are design goals. Texas Instruments
reserves the right to change or discontinue these
products without notice.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright © 1988, Texas Instruments Incorporated
8-163
:l:
~
~
::+
OJ
-<
"o.
Q.
C
...en
C')
8-164
SMJ27C210
1,048,576-Bll UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
MARCH 1988
•
Wide-Word Organization _ .. 64K x 16
•
Single 5-V Power Supply
•
Operationally Compatible with Existing
Megabit EPROMs
•
40-Pin Dual-In-line Package
•
All Inputs and Outputs Fully TTL Compatible
•
Static Operations (No Clocks, No Refresh)
•
Max Access/Min Cycle Time
VCC± 10%
SMJ27C21 0-25
SMJ27C21 0-30
16-Bit Output For Use in MicroprocessorBased Systems
•
32-Bit Programming (Two 16-Bit Words)
and 16-Bit Programming
o
o
16 Seconds Typical Programming Time
Power Saving CMOS Technology
•
3-State Output Buffers
•
•
Vpp
E
016
015
014
013
012
011
010
09
GNOt
08
07
06
05
04
03
02
01
250 ns
300 ns
•
•
J PACKAGE
ITOPVIEW)
G
400 mV Guaranteed DC Noise Immunity
with Standard TTL Loads
Latchup Immunity of 250 mA on All Input
and Output Pins
No Pull-Up Resistors Required
•
Low Power Dissipation
-Active ... 220 mW Worst Case
-Standby ... 1.5 mW Worst Case
(CMOS-Input Levels)
•
Operating Free-Air Temperature - 55°C to
125°C
21
~
->w
W
a:
c..
....
CJ
::::>
c
oa:
..
PIN NOMENCLATURE
Uses TI's Innovative ACE (Advanced
Contactless EPROM) Technology for Noise
Immunity and Improved Reliability
•
20
VCC
PGM
NC
A15
A14
A13
A12
A11
A10
A9
GNot
A8
A7
A6
A5
A4
A3
A2
A1
AO
AO-A15
Address Inputs
E
G
Chip Enable
GND
Ground
c..
Output Enable
NC
No Connection
PmJ
Program
Q1-Q16
Outputs
VCC
Vpp
5-V Supply
...o
(,)
::::s
.
"C
12.5-V Supply~
o
Q.
tPins 11 and 30 must be connected
externally to ground.
~Only in program mode.
description
The SMJ27C21 0 is a 1 ,048,576-bit, ultraviolet-light erasable, electrically programmable read-only memory.
This device is fabricated using CMOS technology for high speed and simple interface with MOS and bipolar
circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits without the
use of external pull-up resistors and each output can drive one Series 74 TTL circuit without external
resistors. The data outputs are three-state for connecting multiple devices to a common bus. The
SMJ27C210 is offered in a 600-mil dual-in-line cerdip package (J suffix) rated for operation from - 55°C
to 125°C.
PRODUCT PREVIEW documents cantlin informltion
on products in the formltive or design phase of
development. Characteristic dlta and other
specifications Ire design gOlls. TexIs Instruments
reserves the right to chlnge or discontinue these
products without notice.
TEXAS
-Ii}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright © 1988. Texas Instruments Incorporated
8-165
I
~
;::;'"
m
-<
"'U
ac.
c
...nen
8-166
SM61CD16, SMJ61CD16
16,384·WORD BY 1·BIT STATIC RAMS
APRIL 1987-REVISED NOVEMBER 1987
o
16,384)( 1 Organization
o
o
Separate I/O
o
o
Fast Static Operation
JD PACKAGE
(TOP VIEW)
Battery Back·Up Operation ... 2 Volt Data
Retention
o Maximum Access Time from Address or
A13
A12
A11
A10
A9
AS
A7
Q
W
Chip Enable
'61 CD16·25 ... 25 ns
'61CD16-35 ... 35 ns
'61CD16-45 ... 45 ns
D
JEDEC Standardized Pinout
o
TTL Compatible Inputs and Outputs
o
Automatic Powerdown When Deselected
- 125 p.A MAX Standby Current at CMOS
Levels
Single 5-V Supply (10% Tolerance)
11
10
GND
o
o
o
o
Vee
AO
A1
A2
A3
A4
A5
A6
Military Temperature Range ... - 55°C to
125°C (M Suffix)
E
FG PACKAGE
(TOP VIEW)
Complementary Silicon Gate MOS
Technology with a 6-Transistor Memory Cell
~
0
UC")
u~
««>«
2
2019
A2 3
A3 4
A4 5
A5 6
A6 7
Low Power Dissipation (VCC - 5.5 V)
- Active ... 660 mW MAX
- Standby ... 110 mW MAX (TTL Inputs)
- Standby ... 0.68 mW MAX (CMOS
Inputs)
18
17
16
15
14
Q 8
13
A12
A11
A10
A9
A8
A7
-
9 1011 12
13:
Cllw Cl
Z
(!)
...en
o Standard and Class B Processing
-
o
o
CJ
::s
SM Prefix ... Standard Processing
SMJ Prefix . . . Class B Processing
"'C
...o
PIN NOMENCLATURE
Three State Output
Packaging Options:
- 20-Pin Ceramic 300-mil DIP
- 20-Pad Leadless Ceramic Chip Carrier
AO-A13
Address Inputs
D
Data Input
Q
Data Output
c..
~
ca
:l:
~
Chip Enable/Power Down
GND
vcc
description
Ground
5-V Supply
Write Enable
The '61 CD 16 is a separate I/O, 16,384-bit static
random-access memory organized as 16,384
words by 1 bit. This memory is fabricated using
complementary MOS technology utilizing a full
CMOS (six transistor cell) memory array. The six transistor cell provides for inherently lower soft error
rates, improved stability across the operating temperature range, and extremely low standby power
compared to the four transistor/two poly load cell making it ideal for military applications.
The '61 CD16's static design and control signals (E and W) remove the need for refresh circuitry and simplify
timing requirements. The chip-enable pin allows for easy memory expansion and automatic power-down.
Access time from either address or chip enable is a maximum of 25,35, or 45 ns, allowing speed upgrades
for new and existing designs.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~~~~i~at~~I~~e ~~~:i~~tigf ~Io;:~:~~t:r~~s not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Copyright © 1987. Texas Instruments Incorporated
8-167
SM61CD16, SMJ61CD16
16,384·WORD BY 1·BIT STATIC RAMS
operation
addresses (AO-A 13)
The 14 address inputs select one of the 16,384 -bit words in the RAM. The address inputs must be stable
for the duration of a read or write cycle. The address inputs can be driven directly from standard Series
54/74 TTL with no external pull-up resistors.
chip enable/power down (EI
The chip enable/power down terminal, which can be driven directly by standard TTL circuits, affects the
data-in and data-out terminals and the internal functioning of the chip itself. Whenever the chip enable/power
down is low (enabled), the device is operational, input and output terminals are enabled, and data can
be read or written. When the chip enable/power down terminal is high (disabled), the device is deselected
and put into a reduced-power standby mode. Data is retained during standby.
write enable (W)
The read or write mode is selected through the write-enable terminal. A logic high selects the read mode;
a logic low selects the write mode. W or E must be high when changing addresses to prevent inadvertently
writing data into a memory location. The W input can be driven directly from standard TTL circuits.
data in (01
Data can be written into a selected device when the write-enable input is low. The input terminal can be
driven directly from standard TTL circuits. Data on the input pin (D) is written into the memory location
specified on the address pins (AO-A 13).
data out (Q)
The three-state output buffer provides direct TTL compatability with a fanout of two Series 54 TTL gates,
one Series 54S TTL gate, or eight Series 54LS TTL gates. The output terminal is in the high-impedance
state when chip enable (E) is high or whevever a write operation is being performed. Data out is the same
polarity as data in.
~
logic symbol t
RAM 16,384 x 1
;::;."
CU
AO
Al
A2
A3
A4
AS
A6
A7
A8
A9
Al0
All
A12
A13
-<
.
"'a
0
CC
,..enn
E
W
D
(1 )
o'
(2)
(3)
(4)
(5)
(6)
(7)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
( 11)
(9)
FUNCTION TABLE
INPUTS
0
A 16,383
L-.....t:.
(12)~
E
x
13
[PWR DWN)
Gl
lEN [READ)
lC2 [WRITE)
W
X
HI-Z
Standby
Standby
H
Data Output
Read
Active
L
L
HI-Z
Write
Active
=
Don't Care.
Q
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
POWER
L
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
Pin numbers shown are for the JD package.
8-168
MODE
Q
H
(8)
\73
OUTPUTS
HOUSTON, TEXAS 77001
SM61CD16, SMJ61CD16
16,384-WORD BY 1-BIT STATIC RAMS
functional block diagram
.-------0
A10
A11
A12
A13
AO
A1
A2
rn
c..
::!:
MEMORY ARRAY
128 ROWS
BY 128 COLUMNS
c:x:
~I-------Q
w
rn
2
w
rn
POWER
DOWN
CONTROL
A3 A4
A5 A6
A7 A8
A9
....
(I)
(,)
::l
"'C
...o
c.
~
CO
~
~
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
8-169
I
SM61 CD16. SMJ61 CD16
16.384-WORD BY 1-BI1 STATIC RAMS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
Supply voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V
Input voltage range (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V
Output voltage range in high-impedance state .............................. -0.5 V to 7 V
Output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Minimum operating free-air temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55°C
Maximum operating case-temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 1 50°C
Latch-up current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTES: 1. All voltage values in this data sheet are with respect to GND.
2. VIL (MIN) of - 3 V for short pulse durations of 20 ns or less. Prolonged operation at VIL levels below - 1 V will result in excessive
currents that may damage the device.
recommended operating conditions
VCC Supply voltage
VIH High-level input voltage
..
~
;:;'
D)
-<
.
."
0
C.
Cit
NOM
MAX
4.5
5
5.5
V
VCC+1
0.8
V
2
VIL
Low-level input voltage (see Note 2)
TC
Operating case temperature
TA
Operating free-air temperature
-1
125
UNIT
V
DC
DC
-55
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
Vee
VOL Low-level output voltage
Input current (load)
II
10
lOS
leel
oV
TYP
2.4
ITTL-level inputs
MIN
TYP
MAX
2.4
UNIT
V
0.4
0.4
V
-10
10
-10
10
p.A
:5 Vo :5 Vee, Output disabled
-50
50
-50
50
p.A
= 5.5 V, Vo = GND
-350
-350
mA
120
120
mA
20
20
mA
125
125
p.A
= 5.5 V, 10 = 0 mA
E ~ VIH, Vee = 5.5V
Inputs = Vee±0.3, Vee = 5.5 V
Vce
current (standby) CMOS-level inputs
'61CD16-35
MAX
:5 VI :5 Vee
Vce
(see Note 3)
Vee operating supply current
I
= 4.5 V,IOH = -4 mA
= 4.5 V, 10L = 8 mA
oV
Output current (leakage)
Vee supply
MIN
Vee
Short circuit output current
ICC
'61CD16-25
CONDITIONS
VOH High-level output voltage
c
C")
MIN
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
CONDITIONS
VOH High-level output voltage
VOL Low-level output voltage
II
Input current (load)
Vec
= 4.5 V,IOH = -4 mA
= 4.5 V, 10L = 8 mA
o V :5 VI
:5 Vce
10
Output current (leakage)
o V :5 Vo
Short circuit output current (see Note 3)
ICC
Vee operating supply current
= 5.5 V, Vo = GND
Vee = 5.5V,10 = OmA
E ~ VIH, Vee = 5.5 V
Inputs = Vee±0.3, Vee = 5.5 V
Vec supply current (standby)
:5 Vee, Output disabled
Vce
II TTL-level inputs
.
CMOS-Ievelmputs
TYP
MAX
2.4
Vce
lOS
leel
'61CD16-45
MIN
-10
-50
UNIT
V
0.4
V
10
p.A
50
p.A
-350
mA
120
mA
20
mA
125
p.A
NOTE 3: Not more than one output should be shorted at a time. The duration of the short circuit should not exceed 30 seconds.
8-170
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
SM61CD16, SMJ61CD16
16,384·WORD BY 1·BIT STATIC RAMS
data retention characteristics
PARAMETER
TEST CONDITION
MIN
MAX
VCC@
2.0 V 3.0 V
2.0
VCC for data retention
VDR
Typt
VCC@
2.0 V 3.0 V
E :2:
ICCDR Data retention current
tCDR Chip deselect to data retention time
tR
Operation recovery time
III §
Input leakage current
VCC - 0.2 V,
3
0
VIN :2: VCC - 0.2 V
or :5 GND
+
0.2 V
tc(RD):I:
UNIT
-
-
-
V
5
50
75
p.A
-
-
-
-
ns
-
1
p.A
ns
tTYP values listed are typical values at 25°C.
:l:tc(RD) = read cycle time.
§This parameter is guaranteed but not tested.
data retention waveform
I-.---- DATA RETENTION _ _ _.....-11
MODE
rl~~_ _ _ _ _ __
Ii
1
VCC
--------4-::.5::-V~1\1
VDR :2: 2 V
~---------~
--t
I-- tCDR---l
1
E
~l//;r-r-rI/)'T""T"r'!J~VIH---.\
capacitance, T A
2SoC, f
4.5 V
1
t--
tR
~~I~~~~~~
/VIH~\~~~
VDR
1 MHz~
TEST CONDITIONS
PARAMETER
Ci
Input capacitance
TA
Co
Output capacitance
TA
=
=
25°C, f
25°C, f
=
=
1 MHz, VCC
1 MHz, VCC
MIN
=
=
TYP
MAX
5 V
4
5 V
7
...
U)
(,)
'Capacitance measurements are made on sample basis only.
:::::I
"'C
timing requirements over recommended supply voltage range and operating temperature range
0..
'S1CD1S-25
MIN
TYP
'S1CD1S-35
MAX
MIN
TYP
MAX
UNIT
tc(rd)
Read cycle time
25
35
ns
tc(wr)
Write cycle time
25
35
ns
tw(W)
Write-enable pulse duration
15
20
ns
tELWH
Chip-enable low to end of write
25
30
ns
tsu(A)
Address setup time to write start
0
0
ns
tsu(D)
Data setup time to write end
12
15
ns
th(A)
Address hold from write end
0
0
ns
th(D)
Data hold from write end
0
0
ns
tELIH
Delay time, chip-enable low to power up§
5
5
tEHIL
Delay time, chip-enable high to power down §
tAVWH
Address setup to write end
35
25
:l:
~
ns
35
30
...o
...CO>-
ns
ns
§This parameter is guaranteed but not tested.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
8-171
SM61CD16, SMJ61CD16
16,384-WORD BY 1-BIT STATIC RAMS
timing requirements over recommended supply voltage range and operating temperature range
'61CD16-45
MIN
TYP
MAX
UNIT
tc(rd)
Read cycle time
45
ns
tc(wr)
Write cycle time
45
ns
tw(W)
Write-enable pulse duration
20
ns
tELWH
Chip-enable low to end of write
40
ns
tsu(A)
Address setup time to write start
0
ns
tsu(D)
Data setup time to write end
15
ns
th(A)
Address hold from write end
0
ns
th(D)
Data hold from write end
0
ns
tELlH
Delay time, chip-enable low to power up t
5
ns
tEHIL
Delay time, chip-enable high to power down t
tAVWH
Address setup to write end
35
40
ns
ns
tThis parameter is guaranteed but not tested.
switching characteristics over recommended supply voltage range and operating temperature range
TEST
PARAMETER
talA)
Access time from address
talE)
Access time from chip enable low
tv(A)
Output data valid after address change
10H
~
-4 mA, 10L
~
-
CL = 30 pF,
See Figure 1a.
0
tdis(E) Output disable time from chip enable high t
.
o
."
c.
c
...
0
n, R2
~
481
CL
~
5 pF, See Figure 1b.
~
255
n,
R1
MIN
TYP
MAX
25
35
25
35
0
15
ns
ns
ns
3
20
0
5
UNIT
ns
ns
5
10
15
ns
10
15
ns
switching characteristics over recommended supply voltage range and operating temperature range
~
-<
Output enable time from chip enable lowt
MAX
3
tdis(W) Output disable time from write enable low t
'61CD16-45
TEST
PARAMETER
;:;"
m
TYP
8 mA
ten(W) Output enable time from write enable high t
ten(E)
'61CD16-35
'61CD16-25
MIN
CONDITIONS
MIN
CONDITIONS
talA)
Access time from address
talE)
Access time from chip enable low
tv(A)
Output data valid after address change
IOH
=
- 4 rnA, IOL
CL
=
=
See Figure 1a.
Output enable time from chip enable lowt
ten(E)
fA
tdis(E) Output disable time from chip enable high t
CL
= 481 0, R2 = 255O,
= 5 pF, See Figure 1b.
tdis(W) Output disable time from write enable low t
tTransition is measured ± 500 mV from steady state voltage; this parameter is guaranteed but not tested.
8-172
45
0
0
R1
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MAX
45
8 rnA
30 pF,
ten(W) Output enable time from write enable high t
(')
TYP
UNIT
ns
ns
ns
3
20
ns
20
ns
20
ns
ns
5
SM61CD16, SMJ61CD16
16,384-WORD BY 1-BIT STATIC RAMS
PARAMETER MEASUREMENT INFORMATION
5V
5V
OUTPUT ____--------~
UNDER TEST
R2 = 255 fl
(b)
(a) Representation of Actual load
THEVENIN EQUIVALENT OF (a) OR (b)
167 f!
OUTPUT
UNDER TEST
---m'----- 1.73 V
tel includes jig and scope capacitances.
FIGURE 1. OUTPUT LOAD CIRCUIT
90%
...--------:s, .------- 3
j{I
1\:0%
I
1 0%
_ _ _1.:...:0:"":%'::"0.:1
I I
~ t-- tr
I
tf ---I
NOTE 4:
i
V
°V
..
t--
tr and tf :5 5 ns.
FIGURE 2. TRANSITION TIMES
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
8-173
SM61CD16, SMJ61CD16
16,384-WORD BY 1-BIT STATIC RAMS
read cycle timing from address t
.-----------tc(rd)--------------'.:
100:
~~--------------------------------------Xlr---------VIH
AO-A13~
---J,
', - - - - - - - - - -
I. . . ._________________________________________
•
talA)
: II
r---tv(A)---'
____________________
~'~~
Q
PREVIOUS DATA VALID
VIL
I
____ I r -__________________________________
XXXXX
DATA VALID
VOH
~---------------------------------VOL
tw is high. and E is low.
read cycle timing from chip enable*
yr-------- V,H
- - - - - - - - - t c ( r d ) - - - - - - - - - - .I
1 . . :. . . .
E----------""""\
I
~
___________________________________J
:..
-
Q ____________.:..:_
talE) - - - - -........:
HI-Z
ten(E)
r------t--tdis(E)
---·..;~XSX}(r-----D-A-TA--V-A-L-,D-I---~ HI-Z _____ VOH
I
VOL
~tELlH ---i
I---tEHIL ----.J
\:..
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ICC
~
_ _ _ _ _ _ _ _ _ _J
I
I
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.
iW
is high. address is valid prior to or simultaneously with the high-to-Iow transition of
E.
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8-174
J;:nOL
ICC
~ ICCl
;:+
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V,L
:
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
c;~"
0
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CD
...3"
5"
CC
0
0
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CD
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!
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tw(W)
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1
I
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• ~th(A)----l
-,
tAVWH
, •
------~X
...:......_ _ _ _ _ _ _--L.:
tsu(D)
-----.J-----,
DATA-IN
,
DATA UNDEFINED
)
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en
W
VIL
'r----
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CD
-+
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---------------~,
C"
VIH
th(D)---;
I
r---- tdis(W)---I
D~~~
VA~ID
VIL
VOH
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VOL
=
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s:
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01
Military Products
SM61CD16, SMJ61 CD16
16,384·WDRD BY 1·BIT STATIC RAMS
write cycle timing controlled by chip enable t
J:
J:
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J:
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A2
A1
5
16
AD
6
15
A1D
7
14
A11
8
13
DQ1
DQ2
DQ3
A6
A7
A8
A9
Low Power Dissipation (VCC - 5.5 V)
- Active ... 660 mW
- Standby ... 55 mW MAX (TTL Levels)
- Standby ... 0.68 mW MAX (CMOS Levels)
Standard and Class B Processing
- SM Prefix . . . Standard Processing
- SMJ Prefix . . . Class B Processing
Packaging Options:
- 20-Pin Ceramic 300-mil DIP
- 20-Pad Leadless Ceramic Chip Carrier
Z
18
TTL Compatible Inputs and Outputs
Automatic Power Down when Deselected
- 125 p.A MAX Standby Current
at CMOS Levels
-w
'212019
-
I
--i
I-- tCDR--l
"C
,!f4.5 V
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
~
8-181
SM64C16, SMJ64C16
4096·WORD BY 4·BI1 STATIC RAMS
capacitance, TA ... 25°C, f ... 1 MHzt
PARAMETER
TEST CONDITIONS
Ci
Input capacitance
TA
Co
Output capacitance
TA
=
=
25°C, f
25°C, f
=
=
1 MHz, VCC
1 MHz, VCC
MIN
=
=
TYP
MAX
UNIT
5V
4
pF
5V
7
pF
tCapacitance measurements are made on sample basis only.
timing requirements over recommended supply voltage range and operating temperature range
'64C16-25
MIN
olJ
s:
~
o
2
MIN
TYP
'64C16-45
MIN
MAX
TYP
MAX
UNIT
Read cycle time
25
35
45
ns
tc(wr)
Write cycle time
25
35
45
ns
tw(W)
Write-enable pulse duration
20
30
35
ns
0
0
0
ns
25
30
35
ns
0
0
0
ns
10
15
15
ns
0
0
0
ns
Write enable high to chip enable low
'TI
'64C16-35
MAX
tc(rd)
tsu(W)rd
2
TYP
(read command setup)
tELWH
Chip-enable low to end of write
tsu(A)
Address setup time to write start
tsu(D)
Data setup time to write end
Write enable low from chip enable high
th(W)rd
(read command hold)
th(A)
Address hold time from write end
0
0
0
ns
th(D)
Data hold time from write end
0
0
3
ns
tELIH
Delay time, chip-enable low to power upt
5
5
5
tEHIL
Delay time, chip-enable high to power downt
tAVWH
Address setup to write end
35
20
ns
35
35
30
ns
ns
35
tThis parameter is guaranteed but not tested.
switching characteristics over recommended supply voltage range and operating temperature range
~
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D)
-<
.oc.
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c:
n
...en
PARAMETER
talA)
Access time from address
talE)
Access time from chip enable low
tv(A)
Output data valid after address change
ten(W)
R1
TEST
'64C16-25
'64C16-35
'64C16-45
CONDITIONS
MIN MAX
MIN MAX
MIN MAX
25
35
45
ns
25
35
45
ns
= 481
CL
fl, R2
= 255fl,
= 30 pF,
UNIT
0
0
0
ns
Output enable time from write enable high t
6
6
6
ns
ten(E)
Output enable time from chip enable low
5
5
5
tdis(E)
Output disable time from
chip enable high t
Output disable time from
tdis(W)
write enable lowt
See Figure 1a.
= 481 n,
= 255 n,
CL = 5 pF,
R1
R2
See Figure 1 b.
20
25
ns
10
15
20
ns
tTransition is measured ± 500 mV from steady state voltage. This parameter is guaranteed but not tested.
tThis parameter is guaranteed but not tested.
8-182
TEXAS
-Ii}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
ns
15
SM64C16, SMJ64C16
4096·WORD BY 4·BIT STATIC RAMS
PARAMETER MEASUREMENT INFORMATION
5V
5V
UND~~~~~~ - - 0 - - - - - - - ,
R2
=
2
o-
Cl = 5 pFt
255 f!
~
~
a:
oLL
(b)
(a)
2
w
U
THEVENIN EQUIVALENT OF (a) OR (b)
167 f!
OUTPUT ------,/W~--- 1.73 V
UNDER TEST
2
tel includes jig and scope capacitances.
~
C
FIGURE 1. OUTPUT LOAD CIRCUIT
j1I
1\:0%
I I
i
«
90% r - - - - - - - - . , . . - - - - - - - 3 V
1
I
_ _....:.1.;;..O°.:.::,Yo...:;l
---!
t-- tr
NOTE 4:
tf --J
10 %
....en
0 V
(,)
:::::I
"C
t--
...o
c..
...>
tr and tf :5 5 ns.
CO
FIGURE 2. TRANSITION TIMES
~
~
TEXAS
"!}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
8-183
SM64C16. SMJ64C16
4096·WORD BY 4·BIT STATIC RAMS
read cycle timing from address t
:...- - - - - - - - - - - t c ( r d ) - - - - - - - - - - - . - · :
~,.....------------------------\!t,-------- VIH
AO-A 11
---A
A
I '--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----J ' - - - - - - - - VIL
:"'
.'
talA)
r---tv(A) -------'
l>
~
001004
»
2
PREVIOUS DATA VALID
O O x x . , . . - - - - - - - - O - A - T - A - V - A - L l - O - - - - - - - - VOH
--
--
'---------------------VOL
tw is high. and E is low.
nm
read cycle timing from chip enable*
2
'TI
o
1.,---------
:1000O I O - - - - - - - - - t c ( r d ) - - - - - - - - - 1
:lJ
E-------'\\
S
I '--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----J :
~
o
II·
..
001-.
004-----........:..:-HI-Z
I
2
t a ( E ) - - - - - ·...:
r;tdis(E)
~
_ _ _ _ _......r.:I_ _ _..J
:-----+-
;::;
~
I
th(W)rd I-
tsu(W)rd
VOL
.1
I
'\
"tJ
tw is high. address is valid prior to or simultaneously with the high-to-Iow transition of E.
....
en
8-184
VOH
HI -Z - -
'{
ICC
50% ~
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50%
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c.
c:
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rtEHIL----:
0)
.o
r
...
ten(E)-----t..
IO'I~,.....------DATA VALID
IIL.-tELlH}
ICC
VIH
VIL
TEXAS
"'J1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
VIH
VIL
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CD
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~~
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i
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m
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tAVWH
tw(W)
I
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•
tsu(D)
r--
l
------I-I
DATA-INVALID
'
th(A)
-----,
VIH
VIL
th(D)------;
I
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1
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1/0
DATA UNDEFINED
~
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VIH
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HI-Z
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VOH
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VOL
tE
or
W must
NOTE:
=
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VIL
t----ten(W)~
r---tdis(W)-----I
____________________________
DATA
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8-186
TEXAS
-II}
INSTRUMENTS
POST OFFice BOX 655012 • OALLAS. TeXAS 75265
etlI-~
eto
c
13:
(;
1':'
SM68CE16, SMJ68CE16
2048·WDRD BY 8·BIT STATIC RAMS
APRIL 1987- REVISED APRIL 1988
o
2048 x 8 Organization
o
o
Common I/O
o
o
o
o
o
JD PACKAGE
(TOP VIEW)
Fast Static Operation
o
o
o
o
A6
A8
A5
A9
A4
W
IT
A3
Battery Back·Up Operation ... 2·Volt Data
Retention
Maximum Access Time from Address or
Chip Enable
'68CE16·25 ... 25 ns
'68CE16-35 ... 35 ns
'68CE16-45 ... 45 ns
A2
A10
A1
E
AO
D08
D01
D07
2
D02
D06
D03
D05
GND
D04
o
-ti
:2
a:
oLL
Single 5-V Supply (10% Tolerance)
FG PACKAGE
Complementary Silicon Gate MOS
Technology with a 6-Transistor Memory Cell
(TOP VIEW)
2
U
r--uuu uuu
«zzz>zz
o Automatic Powerdown When Deselected
o
o
Vee
A7
Military Temperature Range ... - 55 DC to
125 DC (M Suffix)
4
TTL Compatible Inputs and Outputs
w
3-State Output
Low Power Dissipation (VCC - 5.5 V)
- Active ... 660 mW MAX
- Standby ... 110 mW MAX (TTL Inputs)
- Standby ... 5.5 mW MAX (CMOS
Inputs)
Standard and Class B Processing
- SM Prefix ... Standard Processing
- SMJ Prefix . . . Class B Processing
c.J
2
3 2
A8
A6
A9
A5
6
28
A4
7
27
NC
A3
8
26
W
IT
A2
9
25
A1
10
24
A10
AO
11
23
E
22
D08
21
14151617181920
D07
NC
12
D01
13
~
C
«
-
....o
NMOUo:tLO<.O
OOzzOOO
Output Enable for Bus Control
OO(!)
Packaging Options:
- 24-Pin Ceramic 300-mil DIP
- 32-Pad Leadless Ceramic Chip Carrier
PIN NOMENCLATURE
(,)
~
000
"'C
AO-A10
description
The '68CE16 is a common I/O, 16,384-bit static
random-access memory organized as 2048
words by 8 bits. This memory is fabricated using
complementary MOS technology utilizing a full
CMOS (six transistor cell) memory array.
o...
Q.
Address Inputs
D01-D08
Data Input/Data Out
E
Chip Enable/Power Down
G
Output Enable
GND
Ground
NC
No Connection
VCC
5-V Supply
W
Write Enable
...CO>-
~
~
The '68CE16's static design and control signals
{E, G, and W) remove the need for refresh
circuitry and simplify timing requirements. The
chip-enable pin allows for easy memory expansion and automatic power-down. This feature, in conjunction
with the full CMOS array, allows for low standby power operation when the memory is deselected, greatly
reducing the overall memory power requirements. The output-enable pin minimizes bus contention problems
and adds flexibility.
ADVANCE INFORMATION documents contain
informltion cn new products in the simpling Dr
preproduction phase of development Characteristic
dallind other spacifications are subject to change
without notice.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Copyright © 1987, Texas Instruments Incorporated
8-187
SM68CE16, SMJ68CE16
2048·WDRD BY 8·BIT STATIC RAMS
Access time from either address or chip enable is a maximum of 25, 35, or 45 ns, allowing speed upgrades
for new and existing designs.
operation
addresses (AO-A 10)
The 11 address inputs select one of the 2048 8-bit words in the RAM. The address inputs must be stable
for the duration of a read or write cycle. The address inputs can be driven directly from standard Series
54/74 TTL with no external pull-up resistors.
chip enable/power down (E)
The chip enable/power down terminal, which can be driven directly by standard TTL circuits, affects the
data-in and data-out terminals and the internal functioning of the chip itself. Whenever the chip enable/power
down is low (enabled), the device is operational, input and output terminals are enabled, and data can
be read or written. When the chip enable/power down terminal is high (disabled), the device is deselected
and put into a reduced-power standby mode. Data is retained during standby.
write enable (W)
The read or write mode is selected through the write-enable terminal. A logic high selects the read mode;
a logic low selects the write mode. W or E must be high when changing addresses to prevent inadvertently
writing data into a memory location. The W input can be driven directly from standard TTL circuits.
output enable (G)
The output-enable terminal affects only the data-out terminals. When output enable is at a logic high level,
the output terminals are disabled to the high-impedance state. Output enable provides greater output control
flexibility, simplifying data bus design.
data in/data out (DQ 1-DQ8)
Data can be written into a selected device when the write-enable input is low. The DQ terminals can be
driven directly from standard TTL circuits. The three-state output buffer provides direct TTL compatibility
with a fanout of twenty Series 54LS or 54ALS TTL gates, sixteen Series 54AS TTL gates, or thirteen
Series 54F TTL gates. The DQ terminals are in the high-impedance state when chip enable (E) is high or
whenever a write operation is being performed. Data out is the same polarity as data in.
~
.
.
o
;:;.Q)
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"'C
Q.
c:
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8-188
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
SM68CE16, SMJ68CE16
2048·WORD BY 8·BIT STATIC RAMS
logic symbolt
RAM 204B x B
AO (B)
Al (7)
A2 (6)
o
FUNCTION TABLE
A3 (S)
A4 (4)
AS (3)
A6 (2)
A7
INPUTS
o
A 2047
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OUTPUTS
MODE
POWER
E
W
G
D01-DOB
H
X
X
HI-Z
Standby
Standby
L
H
L
Data Output
Read
Active
: : (22)
L
H
H
HI-Z
Read
Active
Al0 (19)
L
L
X
Data Input
Write
Active
E
(lB)
x
= Don't Care.
A,Z4
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the JD package.
..
functional block diagram
....CJ
t /)
:s
"'C
>--++++++--+*- DO 1
...o
c..
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>--+l-t-I-t-I+-- 002
~
CO
~
>--+++++0-- 003
>-++++.....- - 0 0 4
>--+HH~---OOS
>--++---- 006
>--+-41----- 007
>--*-----008
E--'--Q
W----i--..-c:1
G--Hf--<::&-_
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
8-189
SM68CE16, SMJ68CE16
2048·WDRD BY 8·BIT STATIC RAMS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
Supply voltage range (see Note 1) ................... ; ................... - 0.5 V to 7 V
Input voltage range (see Note 2) .......................................... - 1 V to 7 V
Output voltage range in high-impedance state .............................. -0.5 V to 7 V
Output current ................................................ '............ 20 mA
Minimum operating free-air temperature ......................................... - 55°C
Maximum operating case-temperature ........................................... 125°C
Storage temperature range .......................................... - 65°C to 150°C
Latch-up current .......................................................... 200 mA
l>
~
l>
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
eonditions" section of this specification is not implied. Exposure to absolute-maxim urn-rated conditions for extended periods may affect
device reliability.
NOTES: 1. All voltage values in this data sheet are with respect to GND.
2. VIL (min) of - 3 V for short pulse durations. Prolonged operation at VIL levels below -1 V will result in excessive currents
that may damage the device.
2
("')
m
2
recommended operating conditions
'TI
o
Vee Supply voltage
VIH High-level input voltage
Low-level input voltage (see Note 2)
VIL
:xJ
S
~
o
..
2
~
;:;"
Te
Operating case temperature
TA
Operating free-air temperature
NOTE 2:
UNIT
5.5
V
V
Vee+ 1
0.8
-1
125
V
De
De
-55
'68CE16-25
TEST
PARAMETER
TYP
'68CE16-35
MAX
CONDITIONS
MIN
VOH High-level output voltage
VOL Low-level output voltage
Vee = 4.5 V,IOH = -4 rnA
Vee = 4.5 V, 10L = 8 rnA
2.4
o V :S VI :s Vee
o V :s Vo :s Vee, Output disabled
-10
10
-10
10
II
Input current (load)
.
o"
Output current (leakage)
lee
Vee operating supply current
lee I
Vee supply
TIL-level inputs
current (standby) eM OS-level inputs
c
MAX
5
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
10
c.
NOM
4.5
2.2
VIL (min) of - 3 V for short pulse durations. Prolonged operation at VIL levels below - 1 V will result in excessive currents
that may damage the device .
D)
<
MIN
I
I
Vee
= 5.5 V, 10
120
= 0 rnA
TYP
MAX
2.4
UNIT
0.4
V
V
-10
10
p.A
-10
10
p.A
120
rnA
0.4
E ~ VIH, Vee = 5.5 V
20
20
rnA
E = Vee±0.3, Vee = 5.5 V
0.9
0.9
rnA
()
....
(I)
8-190
MIN
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SM68CE16, SMJ68CE16
2048·WDRD BY 8·BIT STATIC RAMS
:!Iectrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
VOH High-level output voltage
VOL Low-level output voltage
'68CE16-45
CONDITIONS
MIN
Vee = 4.5 V,IOH = -4 mA
2.4
TVP
MAX
V
0.4
V
-10
10
p.A
-10
10
p.A
120
mA
20
mA
mA
Vee = 4.5 V, 10L = 8 mA
II
Input current (load)
10
Output current (leakage)
lee
Vee operating supply current
leel
Vee supply current (standby)
VI s Vee
Vee, Output disabled
OV
oV
S
S
Vee = 5.5 V, 10 = 0 mA
II TIL-level inputs
E 2:
CMOS-level inputs
I
s Vo
UNIT
VIH, Vee = 5.5 V
0.9
E = Vee±0.3, Vee = 5.5 V
2
o!d:
data retention characteristics
PARAMETER
VDR
TEST CONDITION
MIN
2.0
Vee for data retention
E 2: Vee
lee DR Data retention current
tR§
Operation recovery time
III §
Input leakage current
or s GND
MAX
VCC@
2.0V 3.0V
3
- 0.2V,
VIN 2: Vee - 0.2 V
teDR§ ehip deselect to data retention time
TVPt
VCC@
2.0V 3.0V
-
+ O.2V
0
tc(RD)'"
5
100
:E
a:
UNIT
-
V
oLL
200
p.A
;2
-
-
-
-
ns
-
1
p.A
-w
ns
CJ
2
c~
tTYP values listed are typical values at 25 ce.
"'tc(RD) = read cycle time.
§This parameter is guaranteed but not tested.
MIN
~
TYP
'68CE16-35
MAX
MIN
TYP
'68CE16-45
MAX
MIN
TYP
MAX
UNIT
tc(rd)
Read cycle time
25
35
45
ns
l>
tc(wr)
Write cycle time
25
35
45
ns
:2
tw(W)
Write-enable pulse duration
20
30
tsu(E)
Chip-enable low to end of write
20
30
30
40
ns
(")
m
tsu(A)
Address setup time to write start
0
0
0
ns
tsu(D)
Data setup time to write end
10
15
20
ns
:2
th(A)
Address hold time from write end
0
0
0
ns
th(D)
Data hold time from write end
0
0
0
ns
o
tpu
Delay time, chip-enable low to power up~
5
5
5
ns
'TI
l:J
s:
~
o
~
~.
Q)
-<
...
o
"tJ
tpD
to power down ~
tAW
Address setup to write end
35
20
35
30
40
ns
ns
switching characteristics over recommended supply voltage range and operating temperature range
PARAMETER
TEST
'68CE16-25
CONDITIONS
MIN MAX
'68CE16-35 '68CE16-45
MIN MAX
MIN MAX
= 481 n,
= 255 n,
CL = 30 pf,
UNIT
talA)
Access time from address
R1
25
35
45
ns
talE)
Access time from chip enable low
R2
25
35
45
ns
ta(Gl
Output enable low to data valid
15
20
25
ns
tv(A)
Output data valid after address change
ten(W)
ten(E)
c.
c(')
ten(G)
tn
tdis(E)
....
35
~This parameter is guaranteed but not tested.
..
:2
Delay time, chip-enable high
ns
See Figure 1 a
0
0
0
ns
Output enable time from write enable high §
0
0
0
ns
Output enable time from chip enable low§
5
5
5
ns
0
0
0
ns
Output enable time from output
enable (G) low §
R1
= 481
Output disable time from chip enable high §
CL
= 5 pF, See Figure 1b
0, R2
= 2550,
tdis(W) Output disable time from write enable low §
Output disable time from output
tdis(G)
enable (G) high §
15
20
20
ns
10
15
20
ns
12
15
15
ns
§Transition is measured ± 500 mV from steady state voltage. This parameter is guaranteed but not tested.
8-192
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
SM68CE16, SMJ68CE16
2048·WDRD BY 8·BIT STATIC RAMS
PARAMETER MEASUREMENT INFORMATION
5V
5V
2
-o
ti
:2!
a:
la)
ou.
(b)
Representation of Actual Load
-w
2
THEVENIN EQUIVALENT OF la) OR Ib)
167
n
OUTPUT
.AU
UNDER TEST -----.vvv ......- - - - 1.73 V
(J
2
t CL includes jig and scope capacitances.
c~
..
FIGURE 1. OUTPUT LOAD CIRCUIT
-
"C
t--
o
c..
NOTE 4: tr and tf S 5 ns.
CO
FIGURE 2. TRANSITION TIMES
~
~
NOTE: All switching characteristics and timing requirements assume test conditions as depicted in Figures 1 and 2 with timing references
of 1.5 V (50% reference point) as shown in the subsequent timing diagrams.
TEXAS
"!}
INSTRUMENTS
POST OFFice BOX 1443 •
HOUSTON. TeXAS 77001
8-193
SM68CE16, SMJ68CE16
2048·WDRD BY 8·BIT STATIC RAMS
read cycle timing from address t
""":- - - - - - - - - - - - t C ( r d l - - - - - - - - - - - . - - :
~--------------------------------------~Xl~-------------VIH
AO·A10
--AI ____________________________________ ..
---J
:~
ta(A)
c
DQ1DOS
~
VIL
.:
r----tv(AI~
l>
~----------
:
\!NX~·~------VOH
7\/\
PREVIOUS DATA VALID
/\A
DATA VALID
~----------------------------------VOL
tWhen iN is high, E is low, and G is low, device is continuously selected.
2
(")
m
-
read cycle timing from chip enable*
2
o"
s:
::a
I"'"..I - - - - - - - - - - - t c ( r d l - - - - - - - - - - - - t..~1
I
l>
E
::!
I
~~---------------------------------------J;(~-----------~:
I
o
..
I
I
t a ( E I - - - - - t..~1
I"
~~I------------
I
2
}I'"
DATA OUT
1
1
1
ta(GI
(4--tdis(GI----.(
tdis(EI I.
~
HI-Z
DATA VALID
----I
::"
VOH
J---HI-Z-
1
~~~
~
VIL
~~~
, - I ICC
T~%
~%
_ _ _ _ _ _ _ _ _J.
:tWhen iN is high, address is valid prior to or simultaneously with the high-to-Iow transition of E.
8-194
-I
I
I
,...ten(GI---t(-----
VIH
VIL
,_---HI-Z
~,
CD
:::l
III
N
t---ten(W)~
I
__________________--J)
------,
VIL
I
r---- tdis(W)-----4
1/0
th(A)
I
I
DATA
r
I
tAW
I•
•
Q
VOH
''''_ _ _ __
tE: or Vii must be high during address transitions.
NOTES: 4. The internal write time of the memory is defined by the overlap of CE low and WE low. Both signals must be low to initiate a
write, and either signal can terminate a write by going high. The data input setup and hold timing should be referenced to the
rising edge of the signal that terminates the write.
5. Data 1/0 pins enter high-impedance state, as shown when IT is held low during write.
VOL
+=co
:e
C
:c
c
CClCI)
<3:
co
, en
co
CClC")
-m
""""'CI):n
""""'CI)
~3:
-c...
cp
.....
CO
C")en
I
:cco
::c:-C")
s:~
CI) en
(J1
Military Products
ADVANCE INFORMATION
SM68CE16, SMJ68CE16
2048·WDRD BY 8·BIT STATIC RAMS
write cycle timing controlled by chip enable t
J:
J:
-I
-> ->
J:
-I
-> ->
J:
-I
-> ->
J:
-I
-I
0
0
-> ->
>
>
l>
C
<
l>
- ---
2
----j
-2
l-
nm
~
Ci
:E
0
l-
."
0
:rJ
::!
0
~
2
-..
.~
r
s:
l>
~
~
-1-
iii
§
~
J
'5
01
c:
"§
r-
It!)'"
iii
.c:
"0
?:
.2
"0
iii
.c:
§
j
1
11
__L
c:
(I)
?:
3:
c:
So
~
m
-<
.
."
0
Ci
c..
C
....n
(I)
?:
0
"£i
III
I'll
0
W
z
u::
W
0
Z
:l
C
A
(13)
1C2 [WRITE)
73
(9)
Q
..
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
Pin numbers shown are for the JD package.
functional block diagram
....CJen
::s
0
"C
o...
c.
...>-
AO
A1
A2
A3
A4
C'CI
MEMORY ARRAY
128 ROWS
BY 512 COLUMNS
~
~
Q
A5
A6
E
w
NOTE: Memory array shown is functionally equivalent to 256 rows by 256 columns.
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-199
SM61CD64. SMJ61CD64
65.536·WORD BY 1·BIT STATIC RAMS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
Supply voltage range (see Note 1) ....................................... - 0.5 V to 7 "
Input voltage range (see Note 2) .......................................... - 1 V to 7 "
Output voltage range in high-impedance state .............................. - 0.5 V to 7 "
Output current ............................................................ 20 m)!
Minimum operating free-air temperature ......................................... - 55°C
Maximum operating case-temperature ........................................... 125°C
Storage temperature range .......................................... - 65°C to 150°C
Latch-up current .......................................................... 200 rnA
l>
C
~
:2
(")
m
:2
-
."
t Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress ratin~
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operatin~
eonditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affecl
device reliability.
NOTES: 1. All voltage values in this data sheet are with respect to GND.
2. VIL (MIN) of - 3 V for short pulse durations of 20 ns or less. Prolonged operation at VIL levels below - 1 V will result in
excessive currents that may damage the device.
recommended operating conditions
o
::c
3:
MIN
l>
Operating case temperature
o
TA
Operating free-air temperature
:2
-
~
;::;:
Do)
-<
...
o
"tI
2.2
-1
Low-level input voltage (see Note 2)
VIL
Te
::!
4.5
vee Supply voltage
VIH High-level input voltage
MAX
NOM
5
5.5
Vee+ 1
0.8
125
UNIT
V
V
I
V
De
De
-55
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
VOH High-level output voltage
Vee
VOL Low-level output voltage
Input current (load)
II
10
Output current (leakage)
lee
Vee operating supply current
leel
Vee supply
MIN
= 4.5 V,IOH = -4 mA
= 4.5 V, 10L = 8 mA
TYP
oV s
2.4
MIN
TYP
OV S VI s Vee
Vo s Vee, Output disabled
-10
-10
= 5.5V,10 = OmA
E;:: VIH, Vee = 5.5V
E = Vee±0.3, Vee = 5.5 V
MAX
2.4
UNIT
V
0.4
Vee
current (standby) CMOS-level inputs
'61CD64-35
MAX
Vee
ITTL-level inputs
I
'61CD64-25
CONDITIONS
0.4
V
10
10
p.A
p.A
130
120
mA
10
10
mA
0.9
0.9
mA
10
10
-10
-10
Co
c
C")
.....
en
TEST
PARAMETER
CONDITIONS
VOH High-level output voltage
VOL Low-level output voltage
II
Input current (load)
10
Output current (leakage)
lee
Vee operating supply current
leel
Vee supply current (standby)
·8-200
Vee
= 4.5 V, 10H = -4 mA
= 4.5 V, 10L = 8 mA
'61CD64-45
MIN
oV s
= 5.5V,10 = OmA
E ;:: VIH, Vee = 5.5 V
E = Vee±0.3, Vee = 5.5 V
Vee
II TTL-level inputs
CMOS-level inputs
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
MAX
2.4
Vee
OV s VI s Vee
Vo s Vee, Output disabled
TYP
-10
-50
UNIT
V
0.4
V
10
p.A
50
120
p.A
mA
10
mA
0.9
mA
SM61CD64, SMJ61CD64
65,536·WORD BY 1·BIT STATIC RAMS
lata retention characteristics
PARAMETER
TEST CONDITION
Vee for data retention
VDR
,leeDR Data retention current
MIN
2.0
E~
tCDR§ Chip deselect to data retention time
tR§
Operation recovery time
III §
Input leakage current
Vee - 0.2 V,
VIN ~ VCC - 0.2 V,
or :s; GND
+
0.2 V
Typt
MAX
VCC@
2.0V 3.0V
VCC@
2.0V 3.0V
-
-
3
5
0
tc(RD)t
-
V
200
/LA
100
UNIT
-
-
-
-
ns
-
1
/LA
ns
2
o
i=
tTYP values listed are typical values at 25°C.
C
o
<
:t>
talA)
Access time from address
talE)
Access time from chip enable low
tv(A)
Output data valid after address change
IOH
ten(E)
=
- 4 mA, IOL
CL
Output enable time from chip enable low t
tdis(E) Output disable time from chip enable high t
=
8 rnA
30 pF,
See Figure 1a.
R1
CL
= 481 0, R2 = 2550,
= 5pF, See Figure 1b.
PARAMETER
m
2
-
talA)
Access time from address
talE)
Access time from chip enable low
tv(A)
Output data valid after address change
'TI
o
:c
ten(W) Output enable time from write enable high t
ten(E)
IOH
=
tdis(E) Output disable time from chip enable high t
CL
=
=
3
ns
5
5
ns
10
15
ns
7
10
ns
'61CD64-45
MIN TYP MAX
=
=
8 mA
30 pF,
481 0, R2
=
2550,
5 pF, See Figure 1 b.
tTransition is measured ± 500 mV from steady voltage; this parameter is guaranteed but not tested.
o
2
~
;:;'
Q)
-<
.
""C
o
Co
c:
,...
(')
en
-I!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
ns
3
TEST
- 4 mA, IOL
ns
ns
tdis(W) Output disable time from write enable low t
8-202
35
5
See Figure 1a.
R1
35
25
CONDITIONS
CL
Output enable time from chip enable low t
25
UNIT
5
tdis(W) Output disable time from write enable low t
2
::::I
=
'61CD64-35
MIN TYP MAX MIN TYP MAX
ten(W) Output enable time from write enable high t
(")
3:
:t>
'61CD64-25
CONDITIONS
UNIT
45
ns
45
ns
5
ns
3
ns
5
ns
15
ns
15
ns
SM61 CD64, SMJ61 CD64
65,536·WORD BY 1·BIT STATIC RAMS
PARAMETER MEASUREMENT INFORMATION
SV
SV
:2
o
CL
=
i=
S pFt
c
FIGURE 1. OUTPUT LOAD CIRCUIT
90%
~-----":I.
._,
}
10%
--....;.;;.~II
~
.------3 V
90%
1\
Ii
./!
J--tr
tf--J
NOTE 4:
tr and tf
:$
«
10%
0 V
t-S ns.
FIGURE 2. TRANSITION TIMES
NOTE: All switching characteristics and timing requirements assume test conditions as depicted in Figures 1 and 2 with timing references
of 1.S V (SO% reference point) as shown in the subsequent timing diagrams.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-203
SM61CD64, SMJ61CD64
65,536-WORD BY 1-BIT STATIC RAMS
read cycle timing from address t
"":•. . - - - - - - - - - - - t C ( r d ) - - - - - - - - - - -....:
~~----------------------------------------:r~-------------VIH
i\" - - - - - - - - - - - - VIL
AO-A15 ~
I ......._________________________________________----J
: ..
l>
c
<
l>
2
nm
2
."
t a ( A ) - - - -.....··'
r--- tv(A)---'
Q
PREVIOUS DATA VALID
xxx><*r----------------O-A-TA--V-A-Ll-O--------------VOH
"-------------------------------------VOL
tljJ is high, and
E is
low.
read cycle timing from chip enable*
o:D
p,
:L.w o - - - - - - - - - - t c ( r d ) - -_ _ _ _ _ _ _
s:
l>
_______
I ______________
~
--JJr-
~~----______________________
E
::::I
I
:..."'--------ta(E) - - - - - - - . - :
....
, o-----ten(E) ____.......,. _....-...,............
o
2
,..-----------1-__
-1-:- H I - Z - - - - - - - - - -..~XX)(}(
-
I
r------t-tdis(E)
I
Q _____
OATA VAllO
I
:
ICC
~
...
..."tJ
o
---'
I
~-----------------------------------~~n~ ICC
~%
~ ICC1
!
_ _ _ _ _ _ _ _ _- J
Q)
tljJ is high, address is valid prior to or simultaneously with the high-to-Iow transition of
E.
..
Co
c
C')
en
8-204
VOH
VOL
I---- tpo
~ tpu ~
;::;
<
~HI-Z--
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Oil:
~.
CD
C)
-
.(
W
!
~
DA~~
(.
tw(W)
t\\'}
tsuIA)-----l
(
I
_ _ _ _ _ _ _ _ _ _ _-J..( _ _ _ _ _ _~ ( •
X
:
-(
---------------~
DATA UNDEFINED
tsu(D)
--1---
DATA-IN
VA~'D
....
~
VIH
VIL
c.
C-
-<
VIH
VIL
~
....CD
~.
CD
~
D)
C-
VIH
CD
-+
t hID)------;
1,.-_ __
VIH
)('-_ _ __
VIL
I
C)
U'I
U,
t-- ten(W)----I
(~----
HI-Z
~
es-
VIL
(
(
)
~---------
;(
(
D~~~
7
_ _ _ _ _ _ _.....·~~thIA)------{
tAW
r---- tdisIW)-------i
'"
(
(
l77ll/Zm
(..
000
gJ~~
~c~
~
(
tsu(E)
E \\)\\
~z
~...;
I•
0
i
~
VOH
(
"------
tE or W
VOL
must be high during address transitions.
NOTE: For both W-controlled and E ccontrolled Write operations. the internal write time of the memory is defined by the overlap of E low and W
low. Both signals must be low to initiate a write. and either signal can terminate a write by going high. The data input setup and hold times
should be referenced to the edge that terminates the write.
C)
:ec
=
Cen
=3:
3:
:::!c...
nC)
=c:;
;a;;.oc
CD
~
o
tTl
Military Products
I
3:C)
en~
ADVANCE INFORMATION
SM61 CD64, SMJ61 CD64
65,536-WORD BY 1-BIT STATIC RAMS
write cycle timing controlled by chip enable t
:J:
:J:
....I
;>
;>
-
---
:J:
....I
;>
;>
:J:
....I
;>
;>
;>
....I
:J:
....I
0
0
;>
>
>
l>
c
<
l>
----I
2
(")
m
":l
:I:
~
-2
:E
C
~
'TI
0
:a
r
3:
l>
::!
0
~
~
2
w
r-
3
J
J
3u;
;:
So
11
~
::.
...
...""CJ
0
m
<
1
l.
W
Z
~
__L
C
...
n
en
en
c:
0
";0
0
"iii
~
~
Z
J
c.
0
u::
W
«
U
:2
2 1 22 21
0
o TTL Compatible Inputs and Outputs
o
i=
«
(TOP VIEW)
Automatic Powerdown When Deselected
Technology with a 6-Transistor Memory Cell
o
11
z
o
FG PACKAGE
o Complementary Silicon Gate MOS
o
A4
A3
A2
A1
AD
DQ4
DQ3
DQ2
DQ1
E
o Single 5-V Supply (10% Tolerance)
o
Vee
A5
A6
A7
AS
A9
A1D
A11
A12
A13
125°C (M Suffix)
o
o
REVISED MAY 1988
Low Power Dissipation (VCC = 5.5 VI
- Active ... 715 mW MAX
- Standby ... 55 mW MAX (TTL Inputs)
- Standby ... 5.5 mW MAX (CMOS Inputs)
3
20
4
19
5
18
6
17
7
16
8
15
9
Standard and Class B Processing
- SM Prefix ... Standard Processing
- SMJ Prefix . . . Class B Processing
14
A3
A2
A1
AD
DQ4
DQ3
DQ2
«
>
c
«
-
1011 1213
IW
~13
"
Packaging Options:
- 22-Pin Ceramic 300-mil DIP
- 22-Pad Leadless Ceramic Chip Carrier
d
0
....
t/)
(.)
::s
"'C
PIN NOMENCLATURE
description
AO-A13
Address Inputs
DQ1-DQ4
Data In/Data Out
E
Chip Enable/Power Down
o...
c..
GND
Ground
The '64C64 is a common I/O, 65,536-bit static
5-V Supply
random-access memory organized as 65,536
VCC
Write Enable
W
words by 4 bits. This memory is fabricated using
complementary MOS technology utilizing a full
CMOS (six transistor cell) memory array. The six
transistor cell provides for inherently lower soft error rates, improved stability across the operating
temperature range, and low standby power compared to the four-transistor/two-poly load cell, making
it ideal for military applications.
The '64C64's static design and control signals (E" and W) remove the need for refresh circuitry and simplify
timing requirements. The chip-enable pin provides for easy memory expansion and for automatic powerdown. This feature, in conjunction with the full CMOS array, greatly reduces the overall memory power
requirements. Access time from either address or chip enable is a maximum of 25, 35, or 45 ns, allowing
speed enhancements for new and existing designs.
ADVANCE INFORMATION documents contain
information on new products in the sampling or
preproduction phase of development Characteristic
data and other specifications are subject to change
without notice.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Copyright © 1987. Texas Instruments Incorporated
8-207
...>-CO
~
~
SM64C64, SMJ64C64
16,384-WORD BY 4-BIT STATIC RAMS
operation
addresses (AO-A 13)
The 14 address inputs select one of the 16,384 4-bit words in the RAM. The address inputs must be stable
for the duration of a read or write cycle. The address inputs can be driven directly from standard Series
54/74 TTL with no external pull-up resistors.
chip enable/power down
lE)
The chip enable/power down terminal, which can be driven directly by standard TTL circuits, affects the
data-in and data-out terminals and the internal functioning of the chip itself. Whenever the chip enable/power
down is low (enabled), the device is operational, input and output terminals are enabled, and data can
be read or written. When the chip enable/power down terminal is high (disabled), the device is deselected
and put into a reduced-power standby mode. Data is retained during standby.
write enable (W)
The read or write mode is selected through the write-enable terminal. A logic high selects the read mode;
a logic low selects the write mode. Wor E must be high when changing addresses to prevent inadvertently
writing data into a memory location. The W input can be driven directly from standard TTL circuits.
data in/data out (001-004)
Data can be written into a selected device when the write-enable input is low. The OQ terminals can be
driven directly from standard TTL circuits. The three-state output buffer provides direct TTL compatibility
with a fanout of twenty Series 54LS or 54ALS TTL gates, sixteen Series 54AS TTL gates, or thirteen
Series 54F TTL gates. The OQ terminals are in the high-impedance state when chip enable (E) is high or
whenever a write operation is being performed. Data out is the same polarity as data in.
-
logic symbol t
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
~
::;'
D)
-<
.
"'tI
o
c.
c
n
r+
o
E
(171
(181
(191
(201
(211
(11
(21
(31
(41
(51
(61
(71
(81
(91
(101
(121
DQ1
DQ2
DQ3
DQ4
RAM 16.384 x 4
0'
FUNCTION TABLE
INPUTS
0
:> A 16.383
x
13
[PWR OWN)
L::- G1
1EN [READ)
~ ,1 C2 [WRITE)
(131
(141
(151
(161
L
A.1D
\73
E
W
H
X
L
H
L
L
= Don't Care.
r
A.Z3
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the JD package.
8-208
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
OUTPUTS
MODE
POWER
HI-Z
Standby
Standby
Data Output
HI-Z
Read
Active
Write
Active
Q
SM64C64, SMJ64C64
16,384·WORD BY 4·BIT STATIC RAMS
functional block diagram
001
S
AO
E
N
A1
A2
A3
A4
S
002
E
A
003
M
P
A5
AS
S
004
... -----:1
POWER
DOWN
CONTROL
A7----_,...I
A8----_-.. .
A9-------_--~
A13----_-------'
A10-------_------~
A11------.-----~
A12-------_--------~
r---------------~
-
I
I
I
I
I
W-'""!-
C
~
2
n
m
-2
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rat
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operat
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may aff
device reliability.
NOTES: 1. All voltage values in this data sheet are with respect to GND.
2. VIL (MIN) of - 3 V for short pulse durations of 20 ns or less. Prolonged operation at VIL levels below - 1 V will resul1
excessive currents that may damage the device.
recommended operating conditions
."
o
:0
Vee Supply voltage
VIH High-level input voltage
l>
VIL
Low-level input voltage (see Note 2)
TC
Operating case temperature
TA
Operating free-air temperature
S
:::!
o
NOTE 2:
2
-
~
.
.
~.
D)
-<
NOM
MAX
4.5
5
5.5
V
VCC+1
0.8
V
2.2
-1
125
UNIl
V
DC
DC
-55
VIL (MIN) of - 3 V for short pulse durations of 20 ns or less. Prolonged operation at VIL levels below -1 V will result in excess
currents that may damage the device.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise note
VOH High-level output voltage
'64C64-25
TEST
PARAMETER
CONDITIONS
MIN
= 4.5 V, 10H = -4 rnA
VCC = 4.5 V, 10L = 8 rnA
2.4
VCC
VOL Low-level output voltage
Input current (load)
II
o V :5 VI
-10
10
Output current (leakage)
oV
ICC
VCC operating supply current
o
c.
ICCI
= 5.5 V, 10 = 0 rnA
E -
4.5 V
I
t-- tR ~
I
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
ca
Ir---.V~IH~~~~~~~
VOR
HOUSTON, TEXAS 77001
:!:
~
8-211
SM64C64, SMJ64C64
16,384·WORD BY 4·BIT STATIC RAMS
capacitance, T A
25°C,
1 MHzt
PARAMETER
Ci
Input capacitance
Co
Output capacitance
TEST CONDITIONS
TA
=
25°C, f
=
1 MHz, VCC
MIN
=
TYP
MAX
5
5 V
7
UNIT
pF
tCapacitance measurements are made on sample basis only.
timing requirements over recommended supply voltage range and operating temperature range
l>
'64C64-25
c
MIN
<
l>
TYP
'64C64-35
MAX
MIN
TYP
'64C64-45
MAX
MIN
TYP
MAX
UNIT
tc(rd)
Read cycle time
25
35
45
ns
tc(wr)
Write cycle time
25
35
45
ns
tw(W)
Write-enable pulse duration
20
25
35
ns
(")
tsu(E)
Chip-enable low to end of write
20
30
35
ns
-2
tsu(A)
Address setup time to write start
0
0
0
ns
tsu(D)
Data setup time to write end
10
15
15
ns
th(A)
Address hold time from write end
0
0
0
ns
th(D)
Data hold time from write end
0
0
0
ns
tpu
Delay time, chip-enable low to power up:
0
0
0
tpD
Delay time, chip-enable high to power down:!:
tAW
Address setup to write end
2
m
."
o
::a
s:
l>
o=!
35
25
35
ns
ns
switching characteristics over recommended supply voltage range and operating temperature range
PARAMETER
~
;:;'
Q)
talA)
Access time from address
talE)
Access time from chip enable low
tv(A)
Output data valid after address change
ten(W)
Output enable time from write enable high §
ten(E)
Output enable time from chip enable low §
Output disable time from
-<
tdis(E)
.oc.
"0
....
20
ns
35
:!:This parameter is guaranteed but not tested.
2
5
25
chip enable high §
Output disable time from
tdis(W)
R1
TEST
'64C64-25
'64C64-35
'64C64-45
CONDITIONS
MIN MAX
MIN MAX
MIN MAX
25
35
45
ns
25
35
45
ns
= 481
0, R2 = 2550,
CL = 30 pF,
See Figure 1a.
= 4810,
R2 = 2550,
CL = 5 pF,
R1
5
5
5
ns
3
3
3
ns
5
5
5
ns
See Figure 1 b .
write enable low§
10
15
15
ns
7
10
15
ns
§Transition is measured ± 500 mV from steady state voltage. This parameter is guaranteed but not tested .
en
8-212
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
UNIT
HOUSTON, TEXAS 77001
I
SM64C64. SMJ64C64
16.384·WORD BY 4·BIT STATIC RAMS
PARAMETER MEASUREMENT INFORMATION
5V
5V
R1 = 481
n
OUTPUT
UNDER TEST-....- - - - - ,
R2 = 255
OUTPUT
UNDER TEST """"'4Ii"---...,
n
R2 = 255
:2
o
n
i=
C
FIGURE 1. OUTPUT LOAD CIRCUIT
-
NOTE 5: tr and tf :S 5 ns.
FIGURE 2. TRANSITION TIMES
ca
~
~
NOTE: All switching characteristics and timing requirements assume test conditions as depicted in Figures 1 and 2 with timing references
of 1.5 V (50% pointl as shown in the subsequent timing diagrams.
TEXAS
-1.!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
8-213
SM64C64, SMJ64C64
16,384-WORD BY 4-BI1 STATIC RAMS
read cycle timing from address t
1oI1-t--------tc(rd)-------~~I
I ~------------------------------------~I
AO-A11
\!(I~---VIH
~
I ....______________________~J\
.
'-----VIL
I-
l>
OQ1-
c
ta(A)------.I
r--tv(A)--.I
PREVIOUS
1_-------------
~J
-OATAVALIO
VOH
OQ4 ___.:;.O;..;AT.;.;A..;..;.V;..;AL::.:.IO~_L.~..JoL.~_loI~J\.
'----------------VOL
~2
tilJ is high, and E is low.
m
read cycle timing from chip enable:l:
('")
-2
o"
:0
tc(rd) - - - - -.....~~I
'--------------------~;(-------::~
s:l>
I
J.-.tdis(E).,
DATA VA~ID /-HI-Z-:::
OQ1- _ _---1_ _
::!
OQ4
o
..
4-- tpo ----..I
2'.
I
------------------~~ICC
50%
ICC
ICC1
~w is high, address is valid prior to or simultaneously with the high-to-Iow transition of E.
8-214
TEXAS
-I/}
INSTRUMENlS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
SM64C64, SMJ6~C64
16,384-WORD BY 4-BIT STATIC RAMS
write cycle timing controlled by write enable t
IooI.......- - - - - - - - - - t c ( w r ) ------------II~~I
I
AO-A13
~,....----VIH
i.\
I
.""--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _. - . J
I
1
E
I
~
I
IooI.......------tsuIE)------~~1
%\\i
W
!
I
:2
VI/fffl///II:'H
,"
1
VIL
I
I
.. j
tAW
I
1011_....---- tw(W) - - - - - - ...~r__ th(A)~
~
~
IL
C
C
~
:2
'{~IoIt----
'wIE,
!
}
tAw.-------I·~1
I-
~\)
l0III\
W \ \ \ \ \ \\ \
m
--n
t/IITi/T//IJlv::
tsu(D)~
1
:2
1
1
.....J
I'
i-th(D)
1
DA~~ - - - - - - - - - - - ' - : - - - - - -......~--------VIH
o
I
:::g
--------VIL
~ tdis(W)----..I
3:
l>
---------------""")]L!_____ H I - Z - - - - - - -VOH
VOL
DATA
OUT _ _ _ _ _ _ DATA
_ _UNDEFINED
_ _ _ _ _ _ _J
T'
=!
:2
1
!.---th(A) ------,
"'T""T"""'r"""T""T'""T"""~:-T"~T"""\ .1----tw(W) ---~"I ,.......,......,..-r-T""'7--r.....,...~~......,..V
(")
o
VIH
1' - - - - - V I L
I
tE or iN must be high during address transitions:
-
~
;:::;:
Q)
-<
.
."
o
c.
c:
C")
,.
en
8-216
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SM68CE64. SMJ68CE64
8192-WDRD BY 8-BIT STATIC RAMS
APRIL 1987 -
JD PACKAGE
(TOP VIEW)
•
8192 x 8 Organization
•
Common I/O
•
Military Temperature Range ... - 55°C to
125°C (M Suffix)
o
Fast Static Operation
•
Battery Back-Up Operation ... 2-Volt Data
Retention
•
Maximum Access Time from Address or
Chip Enable
'68CE64-25 ... 25 ns
'68CE64-35 ... 35 ns
'68CE64-45 ... 45 ns
•
Single 5-V Supply (10% Tolerance)
o
Complementary Silicon Gate MOS
Technology with a 6-Transistor Memory Cell
o
o
o
•
NC
A12
A7
A6
A5
A4
A3
A2
Al
AO
OQl
OQ2
OQ3
GNO
VCC
W
E2
A8
A9
All
I'
3-State Outputs
c
A8
A9
All
NC
-I~-+4"""-DQ3
>-I~+4I~-DQ4
">-+++~--DQ5
~~I----DQ6
>-......- - - D Q 7
E1 ---..&-~-....
">-41-----DQ8
E2
W--r-T-.--.L.t.-_
A5 A4 A3 A2 A1 AO
8-220
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
SM68CE64. SMJ68CE64
8192·WORD BY 8·BIT STATIC RAMS
data retention characteristics
TEST CONDITION
PARAMETER
VDR
2.0
Vee for data retention
leeDR Data retention current
E1 ;:: Vee - 0.2 V,
tCDR§ Chip deselect to data retention time
VIN ;:: VCC - 0.2 V,
tR§
Operation recovery time
III §
Input leakage current
MIN
or
s
GND
+ 0.2 V
TYpt
MAX
VCC@
2.0V 3.0V
VCC@
2.0V 3.0V
UNIT
-
-
-
-
V
3
5
100
200
p.A
0
tc(RD)*
-
-
-
-
ns
-
1
p.A
ns
2
o
i=
tTYP values listed are typical values at 25 DC.
*T c(RD) = read cycle time.
§This parameter is guaranteed but not tested.
-
ca
==
~
SM68CE64, SMJ68CE64
8192·WORD BY 8·BIT STATIC RAMS
recommended operating conditions
MIN
4.5
Vee Supply voltage
VIH High-level input voltage
Low-level input voltage (see Note 2)
VIL
Te
TA
NOM
MAX
5
5.5
2.2
-1
Operating case temperature
Operating free-air temperature
Vee+ 1
0.8
125
-55
UNIT
V
V
V
°e
°e
l>
NOTE 2:
<
l>
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
C
:2
nm
-
:2
."
o
::xl
3:
l>
:2
~
;:;
TEST
CONDITIONS
PARAMETER
VOL Low-level output voltage
Input current (load)
II
Output current (leakage)
10
ICC
leel
oV s
Vee operating supply current
Vee supply
current (standby) CMOS-level inputs
OV S VI s Vee
'vO s Vee, Output disabled
f:1
TEST
ICC
Vee operating supply current
leel
Vee supply current (standby)
OV s VI s Vee
Vo s Vee, Output disabled
Vee
l TTL-level inputs
leo I I'
M S- eve Inputs
=
5.5V, 10
= OmA
E1 ~ VIH, Vee = 5.5 V
E1 = Vee ± 0.3, Vee = 5.5 V
I»
-<
.
."
oQ.
C
...en
(")
8-222
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
2.4
HOUSTON, TEXAS 77001
UNIT
V
0.4
V
10
10
120
pA
/loA
mA
10
10
mA
0.9
0.9
mA
0.4
10
10
-10
-10
'68CE64-45
Vee = 4.5 V, 10H = -4 rnA
Vee = 4.5 V, 10L = 8 mA
oV s
'68CE64-35
TYP MAX
MIN
130
CONDITIONS
High-level output voltage
Low-level output voltage
Input current (load)
Output current (leakage)
-10
-10
= 5.5 V, 10 = 0 mA
E1 ~ VIH, Vee = 5.5 V
= Vee±O.3, Vee = 5.5 V
PARAMETER
VOH
VOL
II
10
2.4
Vee
ITTL-level inputs
I
'68CE64-25
MIN TYP MAX
Vee = ~·.5 V,IOH = -4 mA
Vee ,. 4.5 V, 10L = 8 mA
VOH High-level output voltage
::!
o
VIL (min) for short pulse durations of 20 ns or less. Prolonged operation at VIL levels below -1 V will result in excessive current
that may damage the device input.
MIN
2.4
TYP
MAX
0.4
-10
-10
10
10
UNIT
V
V
120
/loA
/loA
mA
10
0.9
mA
rnA
I
SM68CE64. SMJ68CE64
8192·WORD BY 8·BIT STATIC RAMS
capacitance, TA ... 2SoC, f ... 1 MHzt
TEST CONDITIONS
PARAMETER
Ci
Input capacitance
Co
Output capacitance
TA
=
25°C, f
=
1 MHz, VCC
MIN
=
TYP
MAX
5 V
UNIT
5
pF
7
pF
tCapacitance measurements are made on sample basis only.
timing requirements over recommended supply voltage range and operating temperature range
'68CE64-25
TYP
MIN
'68CE64-35
MAX
MIN
TYP
2
'68CE64-45
MAX
MIN
TYP
MAX
tc(rd)
Read cycle time
25
35
45
ns
tc(wr)
Write cycle time
25
35
45
ns
tw(W)
Write-enable pulse duration
15
20
25
ns
t su (E1)
Chip-enable 1 low to end of write
20
30
40
ns
t su (E2)
Chip-enable 2 high to end of write
15
20
25
ns
tsu(A)
Address setup time to write start
0
0
0
ns
ns
tsu(D)
Data setup time to write end
10
15
20
th(A)
Address hold time from write end
0
0
0
ns
th(D)
Data hold time from write end
0
0
0
ns
tpu
Delay time, chip-enable E1 low to power up~
0
0
0
ns
Delay time, chip-enable E1 high
tpD
to power down ~
tAW
Address setup to write end
20
25
25
20
40
30
c
<
l>
:2
('")
m
-
:2
."
THEVENIN EQUIVALENT OF (a) OR (b)
o
::a
s:
167 fl
OUTPUT - - -......:/W------- 1.73 V
UNDER TEST
l>
teL includes jig and scope capacitances.
:::!
o
..
FIGURE 1. OUTPUT LOAD CIRCUIT
:2
-------/Ir-------:.
~O%
I
90%
_ _......:.;10:;..:°Ic..;;.o~
10 %
1
I I
I
~ J--tr
NOTE 5:
tf~
3 V
0 V
i
t--
tr and tf :S 5 ns.
FIGURE 2. TRANSITION TIMES
NOTE: All switching characteristics and timing requirements assume test conditions as depicted in Figures 1 and 2 with timing references
of 1.5 V (50% reference pointl as shown in the subsequent timing diagrams.
8-224
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SM68CE64. SMJ68CE64
8192·WORD BY 8·BIT STATIC RAMS
read cycle timing from address t
.0-
----,Ji
A12
---'i'----------------------oJ. . . . - - - - VIL
""dl-----------iX~l, . . - - - - V I H
,..
~~~.
"I
talA)
10.-- tv(A)~
PREVIOUS DATA
,
VALlD~,..------D-A-T-A-V-A-Ll-D------ VOH
-------------
2
o
~------------------VOL
tw is high. and E is low.
i=
«
read cycle timing from chip enable:l:
:2:
_ _ _ _ _ _ _ ICCllt------- t c ( r d ) - - - - - - o -..j,
E1
t
~
....Jl
a:
o
LL
r---~----VIH
,~-------------~ I
~. . _________ ::~
E2 _ _ _ _ _ _
------T-'""""I\
'Ll
'I
I
I
r--ta(G)j
~ten(G)
I
~,
I
DO~----HI-Z-...;....---~
DATA VALID
!
!
~
I
_ _ _ _ _ _ _ _ _ _- J
VOH
r-HI-Z-
~------~I--~
VOL
I--tpD~
i4-ten (E1) •
I
tpu
I..
-Vr----------------~~
ICC
:2
ICC
50% ~ ICC,
50%
«
>
c
«
I
! . - - tdis(G)-----o-I
'I'
D01
r-- t en(E2)..!
..J
(.)
j. tdis(E1)-1
r-- tdis (E2) ~
Io.---ta(E1)---.I
! . - - ta (E2)------j
G
-
2
w
..
tw is high. address is valid prior to or simultaneously with the high-to-Iow transition of E.
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
8-225
SM68CE64, SMJ68CE64
8192-WORD BY 8-BIT STATIC RAMS
write cycle timing controlled by write enable t
:t>
o
~2
~
G
(")
.
m
2
I.
-
o::g
DA~~
~
DA~~
:t>
::!
o
tE1 or
\.-th(A)
tsu(A)--~"1
I
E1
...
E2
CI)
th(D)
~ten(W)-
.... 'Wl
k======== :::
H'-Z
be high during address transitions.
tc
I14
. - - - - - - - - (wr)
1
----------t
r - - - - - - VIH
1 ' - - - - - - - vlL
I
)4--
t su (E1)
-/I,..-----rl------VIH
'\
.
...
1.----tsu(A)---~.1
Lt
1
I
I
I.
w
~
_ _ _ _ _D_AT_A_U_N_DE_FI_N_ED_ _ _
I .._ _ _
_--+-1- - - - - - -
o""
c.
c
()
Vii:
~ :DATA-R X"-_______ :::
I
I
"'C
t
V
______________
:10~ J
Q)
~,...---------
,r;±::=tSU(D)
W must
-<
-.!
t---tw(W) -------t
I
write cycle timing controlled by chip enable t
~
;:;:
m
v
~\\\\\\\\\~ V:~
I
------.1
tAW
iN --------"'T'~n~~~
."
2
~~.- - - -
tAW
su(E2)
I
I
J!
I
t- th(A) .....!
VIL
:IH
IL
.1
~~\%\\~%~""wl~$///$ff#ff/J:::
t---I- tsu(D) - - - . I
DA~~
---'x
1
_________
~rth..;..(D..;..)- - - - - - VIH
I
I
DATA-IN VALID
I.
DATA
I/O
t'E'
8-226
or
W must
"I
X'-_______
----------------~ll-_____
J1
DATA UNDEFINED
be high during address transitions.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
VIL
tdls(W)
HOUSTON. TEXAS 77001
VOH
HI-Z - - - - - VOL
SM69CE72, SMJ69CE72
8192-WDRD BY 9-BIT STATIC RAMS
APRIL 1987-REVISED MAY 1988
•
8192 x 9 Organization
•
Common I/O
•
Military Temperature Range ... - 55°C to
125°C (M Suffix)
•
Fast Static Operation
•
Battery Back-Up Operation ... 2-Volt Data
Retention
•
Maximum Access Time from Address or
Chip Enable
'69CE72-25 ... 25 ns
'69CE72-35 ... 35 ns
'69CE72-45 ... 45 ns
JD PACKAGE
(TOP VIEW)
Vcc
IN
E2
A2
A1
AD
A7
2
G
A11
o
A3
i=
E1
D09
D08
D07
o
Single 5-V Supply (10% Tolerance)
•
Complementary Silicon Gate MOS
Technology with a 6-Transistor Memory Cell
______
~
C
A2
A1
AD
NC
A S191
L
Data In
High Z
Deselect
Read
Write
Deselect
X = Don't Care.
(6J
(7)
(S)
(9)
(20)
(2S)
~
12
[PWR OWN]
G1
L::..
... G2
1,2 EN [READ]
L::.. , 1C3 [WRITE] r
A,30
001 (10)
A,Z4
(11)
\J 4
002
(12)
003
(13)
004 (15)
005 (1S)
DOS
(17)
007 (1S)
DOS
(19)
G
(22)
W (27)
I-.
009
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the JD package.
TEXAS
-Ii}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8-229
SM69CE72, SMJ69CE72
8192·WDRD BY 9·BIT STATIC RAMS
functional block diagram
>+-+++-HI+I-'*""- DQ 1
>++++-+-1H-e>--DQ2
>-1-Hr-H--t-4----DQ3
>-+-+++t-<~-DQ4
~--~H >-+++t-<~---DQ5
>+-++~---DQ6
>-+~------.,;...DQ7
>-++-------DQa
E1---""'"'--'rr"""">-4.....------DQ9
E2
W---r-T............u.-_
G--,-,-_"
8-230.
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
SM69CE72, SMJ69CE72
8192·WORD BY 9·BIT STATIC RAMS
data retention characteristics
PARAMETER
TEST CONDITION
VCC for data retention
ICCDR Data retention current
E1 2: VCC - 0.2 V.
tCDR§ Chip deselect to data retention time
VIN 2: VCC - 0.2 V.
MIN
2.0
VDR
tR§
Operation recovery time
III §
Input leakage current
0
or s GND + 0.2 V
tcJRD):I:
TYpt
MAX
Vee@
2.0 V 3.0 V
Vee@
2.0 V 3.0V
-
-
-
-
3
5
100
200
UNIT
V
p.A
-
-
ns
-
ns
-
1
p.A
tTYP values listed are typical values at 25°C.
:l:tc(RD) = read cycle time.
§This parameter is guaranteed but not tested.
data retention waveform
Vee
,........DATA RETENTION .......
D
VD:: : V
-------4~.~5-:"Vj~1\
r
ALIr:-::4-:.5~V~------
teDR
tR----.j
E1~VIH
\
I
VDR
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
VIH~
8-231
SM69CE72, SMJ69CE72
8192·WDRD BY 9·BIT STATIC RAMS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted) t
Supply voltage range (see Note 1) ....................................... -0.5 V to 7 V
Input voltage range (see Note 2) .......................................... - 1 V to 7 V
Output voltage range in high-impedance state .............................. -0.5 V to 7 V
Output current ................................................. ~ .......... 20 mA
Minimum operating free-air temperature ......................................... - 55°C
Maximum operating case-temperature ........................................... 125°C
Storage temperature range .......................................... - 65°C to 150°C
Latch-up current .......................................................... 200 mA
l>
c
~
2
nm
-2
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum· rated conditions for extended periods may affect
device reliability.
NOTES: 1. All voltage values in this data sheet are with respect to GND.
2. Prolonged operation at VIL levels below - 1 V will result in excessive currents that may damage the device input.
recommended operating conditions
."
o
:0
s:l>
::!
o
Vee Supply voltage
VIH High·level input voltage
Low-level input voltage (see Note 3)
VIL
TC
Operating case temperature
TA
Operating free-air temperature
NOTE 3:
2
-
II
Input current (load)
-<
Output current (leakage)
lec
Vee operating supply current
Co
r::::
5.5
V
Vec+ 1
O.S
V
-1
125
UNIT
V
De
De
-55
leel
'69CE72-25
TEST
PARAMETER
10
"'tI
MAX
5
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
~
::+
.
o
NOM
4.5
2.2
VIL (min) for short pulse durations of 20 ns or less. Prolonged operation at VIL levels below - 1 V will result in excessive currents
that may damage the device input.
VOH High-level output voltage
VOL Low-level output voltage
OJ
MIN
CONDITIONS
MIN
= 4.5 V, 10H = -4 mA
Vec = 4.5 V, 10L = SmA
2.4
Vee
:5 Vo
:S VI :s Vee
:s Vce, Output disabled
=
TYP
MAX
2.4
0.4
-10
10 -10
10
10 -10
10
130
5.5 V, 10
E1 CO
c..
ns
15
15
20
ns
15
15
20
ns
10
15
20
ns
10
15
20
ns
~
~
:1:This parameter is guaranteed but not tested.
NOTE 4: Transition is measured ± 500 mV from steady state voltage. This parameter is guaranteed but not tested.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
C
ns
8-233
SM69CE72, SMJ69CE72
8192·WDRD BY 9·BIT STATIC RAMS
PARAMETER MEASUREMENT INFORMATION
5V
5V
=
481 11
UND~~~~~+------------'
»
c
<
»
2
R2
=
255
n
CL
=
5 pFt
(")
m
-2
(b)
(a)
THEVENIN EQUIVALENT OF (a) OR (b)
."
o
:::c
16711
OUTPUT _ _---".1. A 1."--_ _ _ 1.73 V
UNDER TEST
VVV'
s:
t CL includes jig and scope capacitances.
::!
FIGURE 1. OUTPUT LOAD CIRCUIT
»
o
2
90%
r------~
·-------3 V
90%
,\..10%
OV
. --7
"
10%.I!
~
;::;:
Ii
--"-"-~II
~ t--tr*
tf*.....I t--
D)
-<
.
*t r and tf
""C
S
5 ns.
FIGURE 2. TRANSITION TIMES
o
Co
c
n
....
NOTE 5:
(J)
8-234
All switching characteristics and timing requirements assume test conditions as depicted in Figures 1 and 2 with timing references
of 1.5 V (50% reference point) as shown in subsequent timing diagrams.
TEXAS
l!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SM69CE72. SMJ69CE72
8192·WDRD BY 9·BIT STATIC RAMS
'ead cycle timing from address t
AO
A1;
~r
I
tC(rd)------------1W~1, - - - - -
J!\
~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-
' - - - - - - Vil
I..
DD~~
_I
I
ta(A)
I.--tv(A)~
PREVIOUS DATA VALID
~,-------D-A-TA-V-A-L1-D------
-------------
W is
:2
o
VOH
~.- - - - - - - - - - - - - - - - - - VOL
i=
high, and E is low.
C
-ca
~W is high, address is valid prior to or simultaneously with the high-to-Iow transition of E.
:!:
~
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
8-235
SM69CE72. SMJ69CE72
8192·WDRD BY 9·BIT STATIC RAMS
write cycle timing controlled by write enable t
. - , . - - - - - - - - t c l w r ) - - - - - - -.....
·j
AO- ~
: K r - - - - - - - VIH
A12
----h----------------.....I, I \....- - - - - - VIL
j
E1
j
~Ie-"---tsuIE1)1----.../J;rr7W/;"'7"To/;rl7~"'7"T1I/;T'T"7!h"'T"T'1I/;T'T"71h"'T"T'm'7"T"7~ :::
l>
I
C
d
E211//
////
I
'..._ _ _ _ _ t
<
l>
:2
l
m
--n
•
•
tsulA)
j
~\\
\\~
\\\\
\\
~
IL
l.---t
j hiD)
VIL
~tsuID)--
DA~: _ _ _ _ _ _ _ _ _-J~DATA-IN VALID:
s:
I
l>
DA~~
:IH
l~------V'H
j
o
::D
:IH
IL
I..-thIA)-..---twIW)----'
j
:2
:2
lE2) _ _ _ _....'
G @!.tAW---.......,;.1
('")
::!
o
'l\\\\\\}\\\\\\\\\\\\\\\
su
-----------1-._---'\.,
~
DATA UNDEFINED
)(\..._ _ _ _ _ _ :::
-tenIW)----,
I r----- VOH
K\...____
tdislW)
HI-Z
VOL
tE"
or
iN ~ust
be high during address transitions.
write cycle timing controlled by chip enable t
.-I·--------tclw)-----------.-,
AO
A1;
---..v
'VIr - - - - - - -A'--_______________.....IA
_
E1
_
+-1_ _ _ _ _ _
~ t o - - t su lE1) ~
I
'\
1
I:
\
I.-- tsulE2) ----..I
_
.1
.- - - - - -
I
, r - - - - I I I - - - - - - VIH
1
.. . - - - - t s u I A ) - - - - - - ....,
E2
VIH
11....-_ _ _ _ _ VIL
I
tAW
I
1
VIL
I
'---:::;1-+------- VIL
.t--thIA)
~"'TT'"~"""""'~T"T'"'I"'TT'"~"""""'~~ I-- tWIW)------l
~
V
&1////////III11///1//~ v::
iN \ \ \ \
\ \\\\\\\\\\\\\\\\\
r--+-- tsuID)----..i
,
DATA - - - - - - - - - " " " ' \ : ( ,
l\.
~
I
I
L.---.t-thlDI
DATA-IN VALID
____________
,._-.....,
DATA
DATA UNDEFINED
00
tE"
8-236
or
iN
\:(1~.;.:.:;.:..------VIH
l\.
tdislW)
~J-----HI-Z------
,
must be high during address transitions.
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
~
VOH
~
SM61 CD256, SMJ61 CD256
262,144 BY 1·BIT STATIC RAMS
DECEMBER 1987 - REVISED FEBRUARY 1988
•
262,144 x 1 Organization
•
Separate I/O
•
Military Temperature Range ... - 55°C to
125°C (M Suffix)
•
Fast Static Operation
•
Maximum Access Time from Address or
Chip Enable
'61CD256-35 ... 35 ns
'61 CD256-45 ... 45 ns
'61 CD256-55 ... 55 ns
•
Single 5-V Supply (10% Tolerance)
•
Automatic Powerdown when Deselected
o
3-State Output
o
Complementary Silicon Gate MOS
Technology with a 6-Transistor Memory Cell
AO-A 17
Address Inputs
D
TTL Compatible Inputs and Outputs
Q
Data Input
Data Output
E
Chip Enable/Power Down
GND
Ground
VCC
5-V Supply
Write Enable
JD PACKAGE
(TOP VIEW)
Vee
AO
Al
A2
A3
A4
A5
A6
A7
AS
A17
A16
A15
A14
A13
A12
All
Al0
A9
Q
iN
GND
12 13
sw
->w
D
E
PIN NOMENCLATURE
o
o
Low Power Dissipation (VCC = 5.5 V)
-Active ... 660 mW MAX
-Standby ... 27.5 mW MAX (TTL Inputs)
-Standby ... 1.1 mW MAX (CMOS Inputs)
W
a:
c..
t-
C
oa:
c..
•
Standard and Class B Processing
- SM Prefix . . . Standard Processing
-SMJ Prefix ... Class B Processing
•
Packaging Options:
-24-Pin Ceramic 300-mil DIP
- 28-Pad Leadless Ceramic Chip Carrier
•
Chip Enable Pin for Memory Expansion and
Standby Operation
description
The '61 CD256 is a separate I/O, 262, 144-bit static random-access memory organized as 262,144 words
by 1 bit. This memory is fabricated using complementary MOS technology utilizing a full CMOS (six-transistor
cell) memory array. The six-transistor cell provides inherently lower soft error rates, improved stability over
the operating temperature range, and very low standby power compared to the four-transistor/two-poly
load cell, making it ideal for military applications.
The '61 CD256's static design and control signals (E" and vi) remove the need for refresh circuitry and
simplify timing requirements. The chip-enable pin provides for easy memory expansion and for automatic
power-down. This feature, in conjunction with the full CMOS array, provides for very low standby power
operation when the memory is deselected, greatly reducing the overall memory power requirements.
Access time from either address or chip enable is a maximum of 35, 45, or 55 ns, allowing speed
enhancements for new and existing designs.
PRODUCT PREVIEW documents contain information
on products in the formative or design ~hase of
development. Characteristic data an~ other
specifications are design goals. Texas Instruments
reserves the right to change or discontinue these
products without notice.
O
::::>
TEXAS
~
Copyright © 1987, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
8-237
..
8~238
SM64C256, SMJ64C256
65,536·WORD BY 4·BIT STATIC RAMS
JANUARY 1988
o
65,536 x 4 Organization
o
Common I/O
JD PACKAGE
(TOP VIEW)
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
o Military Temperature Range ... - 55°C to
125°C (M Suffix)
o
o
o
o
o
o
o
Fast Static Operation
Maximum Access Time from Address or
Chip Enable
'64C256·35 ... 35 ns
'64C256-45 ... 45 ns
'64C256-55 ... 55 ns
E
Single 5-V Supply (10% Tolerance)
Complementary Silicon Gate MOS
Technology with a 6-Transistor Memory Cell
~
->w
W
GND
TTL Compatible Inputs and Outputs
L!l
W
a:
U
c..
cn .... uuu
z
Low Power Dissipation (VCC = 5.5 V)
-Active ... 660 mW MAX
-Standby ... 27.5 mW MAX (TTL Inputs)
-Standby ... 1.1 mW MAX (CMOS
Inputs)
321 28 27
26
25
24
7
23
8
22
9
21
10
20
11
19
A8
A7
A6
A5
A4
A3
A2
A1
Standard and Class B Processing
- SM Prefix ... Standard Processing
-SMJ Prefix ... Class B
o Chip Enable Pin for Memory Expansion and
E
Standby Operation
o
VCC
A15
A14
A13
A12
A11
A10
DQ4
DQ3
DQ2
DQ1
I-
o
NC
A10
A11
A12
A13
A14
DQ4
DQ3
DQ2
::J
C
oa:
c..
-
Packaging Options:
-24-Pin Ceramic 300-mil DIP
- 28-Pad Leadless Ceramic Chip Carrier
description
The '64C256 is a common I/O, 262,144-bit
static random-access memory organized as
65,536 words by 4 bits. This memory is
fabricated using complementary MaS
technology utilizing a full CMOS (six-transistor
cell) memory array. The six-transistor cell
provides for inherently lower soft error rates,
improved stability over the operating
temperature range, and very low standby power
compared to the four-transistor/two-poly load
cell, making it ideal for military applications.
PIN NOMENCLATURE
AO-A 15
DO 1-D04
E
GND
VCC
W
Address Inputs
Data In/Data Out
Chip Enable/Power Down
Ground
5-V Supply
Write Enable
The '64C256's static design and control signals{E and W) remove the need for refresh circuitry and simplify
timing requirements. The chip-enable pin provides for simplified memory expansion/design and for automatic
powerdown. Access time from either address or chip enable is a maximum of 35, 45, or 55 ns.
PRODUCT PREVIEW documents contain information
on products in the formative or design ~hase of
development. Characteristic data an~ other
speCifications are design goals. Texas Instruments
reserves the right to change or discontinue these
products without notice.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Copyright © 1988. Texas Instruments Incorporated
8-239
~
~
m
-<
..."U
o
Q.
c
n
r+
en
8-240
SM68CE256, SMJ68CE256
32,768-WORD BY 8-BIT STATIC RAMS
JULY 1987-REVISED NOVEMBER 1987
o
32,768 x 8 Organization
o
Common I/O
•
Military Temperature Range ... - 55°C to
125°C (M Suffix)
o
Fast Static Operation
•
Maximum Access
Chip Enable
'68CE256-35 ...
'68CE256-45 ...
'68CE256-55 ...
JD PACKAGE
(TOP VIEW)
A5
Time from Address or
Single 5-V Supply (10% Tolerance)
o
Complementary Silicon Gate MOS
Technology with a 6-Transistor Memory Cell
o
TTL Compatible Inputs and Outputs
o
Low Power Dissipation (VCC - 5.5 V)
- Active ... 660 mW MAX
- Standby ... 27.5 mW MAX (TTL Inputs)
- Standby ... 1.1 mW MAX (CMOS
Inputs)
s:
w
>
w
GND
o
Chip Enable Pin for Memory Expansion and
Standby Operation
c..
N
q-
U
tU
C">
~ ~ ~ ~ ;;>I~ ~
4
3
2
A4
A3
A2
A1
AO
NC
D01
Packaging Options:
- 28-Pin Ceramic 400-mil DIP
- 28-Pin Ceramic 600-mil DIP
- 32-Pad Leadless Ceramic Chip Carrier
::J
1 3231'30
29 A8
28 A9
C
~
A6 5
A5 6
Output Enable for Simplified Bus Control
a:
FG PACKAGE
(TOP VIEW)
Standard and Class B Processing
- SM Prefix ... Standard Processing
- SMJ Prefix . . . Class B
•
o
A4
A3
A2
A1
AO
D01
D02
D03
35 ns
45 ns
55 ns
o
o
A14
A12
A7
A6
oa:
27 A11
26 NC
25 IT
7
8
9
10
11
c..
24 A10
23
E
22 D08
12
13
21
~ 1 5 16 17 18 19 20
....CJ
fI)
D07
:::s
..
NC">OUq-Lt)CO
OOzzOOO
00t!)
"C
o
a..
000
PIN NOMENCLATURE
description
AO-A14
DQ1-DQ8
~
Address Inputs
The '68CE256 is a common I/O, 262,144-bit
Data In/Data Out
static random-access memory organized as
E
Chip Enable/Power Down
32,768 words by 8 bits. This memory is
Ground
GND
fabricated using complementary MOS
5-V Supply
VCC
technology utilizing a full CMOS (six transistor
Vii
Write Enable
cell) memory array. The six transistor cell
Output Enable
G
provides for inherently lower soft error rates,
improved stability over the operating temperature range, and very low standby power compared to the
four-transistor/two-poly load cell, making it ideal for military applications.
The '68CE256's static design and control signals (E, (3, and W) remove the need for refresh circuitry and
simplify timing requirements. The chip-enable pin provides for simplified memory expansion/design and
for automatic powerdown. Access time from either address or chip enable is a maximum of 35, 45, or
55 ns. The output enable-pin minimizes bus contention problems.
PRODUCT PREVIEW documents contain information
on products in the formative or design phase of
development. Characteristic data and other
~~:~:~~:t;~:Sri:~t dt~S~\na~::I~'r ~~:~~~ti~~:~~:!:
products without notice.
TEXAS
~
Copyright © 1987, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
8-241
ca
==
:i
~
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8-242
SM69CE288, SMJ69CE288
32,768·WDRD BY 9·BIT STATIC RAMS
JULY 1987-REVISED FEBRUARY 1988
•
32,768 x 9 Organization
•
Common 1/0
•
JD PACKAGE
(TOP VIEW)
Military Temperature Range ... - 55°C to
125°C (M Suffix)
•
Fast Static Operation
•
Maximum Access
Chip Enable
'69CE288-35 ...
'69CE288-45 ...
'69CE288-55 ...
35 ns
45 ns
55 ns
Single 5-V Supply (10% Tolerance)
•
Complementary Silicon Gate MOS
Technology with a 6-Transistor Memory Cell
•
TTL Compatible Inputs and Outputs
•
Low Power Dissipation (VCC = 5.5 V)
- Active ... 660 mW MAX
- Standby ... 27.5 mW MAX (TTL Inputs)
- Standby ... 1.1 mW MAX (CMOS Inputs)
GND
~~ Vce
A14
2
31
3
30
NC
4
29
W
5
28
6
27
7
26
8
25
A13
A9
A10
A11
9
24
G
10
23
A12
11
E
12
22
21 ~
13
20
14
19
15
18
16
17
'-----
~
w
D09
DOS
D07
D06
D05
:>w
a:
a.
tCJ
::l
FG PACKAGE
(TOP VIEW)
C
Standard and Class B Processing
- SM Prefix ... Standard Processing
- SMJ Prefix . . . Class B
oa:
..
432
•
Output Enable for Simplified Bus Control
o
Chip Enable Pin for Memory Expansion and
Standby Operation
.
o
AS
A7
A6
A5
A4
A3
A2
A1
AO
D01
D02
D03
D04
Time from Address or
•
o
GND
NC
A6
A5
A4
A3
A2
A1
AO
Packaging Options:
- 32-Pin Ceramic 400-mil DIP
- 32-Pad Leadless Ceramic Chip Carrier
5
6
28
7
27
8
26
NC
9
25
G
10
24
A10
11
23
E
NC 12
22
D01
description
13
21
14 1 5 1 6 1 7 18 1 9 26
a.
AS
A9
A11
D09
DOS
NMCq-L.()CO
Oozooo
CCl!)CCC
The '69CE288 is a common 1/0, 294,912-bit
static random-access memory organized as
32,768 words by 9 bits. This memory is
fabricated using complementary MaS
technology utilizing a full CMOS (six-transistor
cell) memory array. The six-transistor cell
provides for inherently lower soft error rates,
improved stability over the operating
temperature range, and very low standby power
compared to the four-transistor/two-poly load
cell, making it ideal for military applications.
PIN NOMENCLATURE
AO-A 14
Address Inputs
DQ 1-DQ9
Data In/Data Out
E
Chip Enable/Power Down
GND
Ground
VCC
5-V Supply
W
Write Enable
G
Output Enable
The '69CE288's static design and control signals
NC
No Connection
{E, G, and W) remove the need for refresh
circuitry and simplify timing requirements. The chip-enable pin provides for simplified memory
expansion/design and for automatic powerdown. Access time from either address or chip enable is a
maximum of 35, 45, or 55 ns. The output enable-pin minimizes bus contention problems.
PRODUCT PREVIEW documents contain information
on products in the formative or design IIhase of
development. Characteristic data and other
specifications are design goals. Texas Instruments
reserves the right to change Dr discontinue these
products without notice.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Copyright © 1987. Texas Instruments Incorporated
8-243
~
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8-244
SMJ9914A
GPIB CONTROLLER
JUNE 1986 - REVISED MARCH 1988
•
Handles All IEEE-488 1975/78 Functions
•
Compatible with IEEE-488A 1980
Supplement
•
Maximum Transfer Rate . . . Greater Than
360 Kilobytes/Second
JD PACKAGE
(TOP VIEW)
•
Talker and Listener Function (T, TE, L, LE)
•
Automatic Source and Acceptor
Handshakes (SH, AH)
•
Controller with Pass Control
•
System Controller Capabilities
•
Device Trigger and Device Clear Capabilities
(DT, DC)
•
Optional Automatically Cleared 'Request
Service Bit'
•
Parallel and Serial Poll Facilities (PP)
•
Remote/Local Function with Local Lockout
(RL)
•
Single or Dual Primary Addressing
•
Secondary Address Capabilities
•
Direct Interface to SN75160/161/162 Bus
Transceivers with No Additional Logic
ACCRO
ACCGR
CE
WE
OBIN
RSO
RS1
RS2
INT
07
06
05
04
03
VCC
TR
0101
0102
0103
0104
0105
0106
0107
0108
CO NT
SRO
ATN
EOI
OAV
NRFO
NOAC
IFC
REN
TE
01
...o
c..
>
...
CO
Compatible with Most Microprocessors
•
Direct-Memory-Access Facilities
•
Memory-Mapped Microprocessor Interface
•
Temperature Range ... - 55 °C to 110 °C
(5 Suffix)
..
~
~
(TOP VIEW)
85
z
IW 1
6 5
4 3 2 1 44 43 42 41 40
39
1
U
.... N
ii51~
U U U U a: Q Q U
C:>UI-CCZ
RSO
RS1
RS2
INT
07
06
05
04
03
02
01
description
The SMJ9914A provides an interface between
a Microprocessor System and the General
Purpose Interface Bus (GPIB) specified in the
IEEE-488 1975/78 standards and the IEEE-488A
1980 supplement. The device is controlled and
configured through 8-bit memory-mapped
registers and enables all aspects of the standards
to be implemented, including talker, listener and
controller. The functional block diagram is shown
on page 3.
~:~~:~~i~a{~~I~~8 ~!~~~~ti~r :I~o::~:~:t:ros~s not
(.)
::::s
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FD PACKAGE
•
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
...en
7
8
38
9
37
10
36
11
35
34
12
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
0 -G-II- (/) W Z U U C U
ZC
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INSTRUMENTS
TEXAS
POST OFFICE BOX 1443 •
0103
0104
0105
0106
0107
0108
CO NT
SRO
ATN
EOI
DAV
HOUSTON, TEXAS 77001
Copyright © 1986. Texas Instruments Incorporated
8-245
SMJ9914A
GPIB CONTROLLER
The GPIB is designed to allow up to 15 instruments within a localized area to communicate with each
other over a common bus. Each device has a unique address, read from external switches at power-on,
to which it responds. Information is transmitted by byte-serial bit-parallel format and may consist of either
device-dependent data or interface messages, commonly referred to as data or command, respectively.
A typical application is shown in Figure 1. Auxiliary commands are listed in Table 1.
Device data may be sent by anyone device (the talker) and received by a number of other devices (listeners).
Instructions, such as select range, select function, or measurement data for processing or printout, may
be sent in this way.
The SMJ9914A performs the interface function between the microprocessor and GPIB bus and relieves
the processor of the task of maintaining the IEEE protocol. By utilizing the interrupt capabilities of the device,
the bus does not have to be continually polled, and fast responses to changes in the interface configuration
can be achieved.
The GPIB input/output pins are connected to the IEEE-488 bus via bus tranceivers. The direction of data
flow is controlled by the TE and CaNT outputs generated on the SMJ9914A. The SN75160, 75161 and
75162 bus transceivers are designed specifically for use with a GPIB interface. The TE and CaNT signals
are routed within the devices so that the buffers on particular lines are controlled as required by the
SMJ9914A. Other buffers may be used, but they may require a small amount of external logic, particularly
around the EOI line buffer .
..
8-246
-II}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
SMJ9914A
GPIB CONTROLLER
functional block diagram
REN. IFC. ATN
EOI. SRQ. DAV.
NRFD & NDAC
0101·0108
RSO·RS2
DBIN
REGISTER
ADDRESS
DECODE
WE
INTERRUPT
MASK 0
INTERRUPT
STATUS 1
INTERRUPT
MASK 1
AUXILIARY
COMMAND
DECODE
ADDRESS
STATUS
..
00-07
DATA AND
PROGRAM
MEMORY
00-07
DATA
BUS
BUFFERS
75160
DATA
BUS
WE
WE
SMJ9914A
GPIB
DBIN
DBIN
TE
IEEE-488
GPIB
MPU
BUS
MANAGEMENT
BUFFERS
75161
OR
75162
BUS
MANAGEMENT
FIGURE 1. TYPICAL SMJ9914A APPLICATION
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
8-247
SMJ9914A
GPIB CONTROLLER
pin descriptions
I/O
PIN
NO.
(TVPE)
1
ACCRO
ot
2
ACCGR
I
3
CE
I
4
WE
I
5
DBIN
I
6
RSO
I
7
RSl
I
8
RS2
I
9
INT
ot
17-10
~
~
NAME
18
00-07
I/ot
I
I
19
RESET§
20
VSS
...o"'tJ
21
TE
cC')
..
22
REN
I/O'
(J)
23
IFC
I/O'
24
NDAC
I/ot
25
NRFD
IlOt
26
DAV
I/ot
27
EOI
I/ot
28
ATN
I/ot
29
SRO
IlOt
30
co NT
...
<
Il)
c.
r+
31-38
0108-0101
39
TR
40
VCC
DESCRIPTION
Access Request. This pin becomes active (low) to request a direct memory access.
Access Granted. When received from the direct·memory-access control logic, this enables the
byte onto the data bus. ACCGR must be high when not participating in DMA transfer.
Chip Enable. CE allows access of read and write registers. If CE is high, 00·07 are in high
impedance unless ACCGR is low.
Write Enable. When active (low), indicates to the SMJ9914A that data is being written to one
of its registers.
Data Bus In. An active (high) state indicates to the SMJ9914A that a read is about to be
carried out by the MPU.
Register Select Lines. Determine which register is addressed by the MPU during a read
or write operation.
Interrupt. Sent to the MPU to cause a branch to a service routine.
Data transfer lines on the MPU side of the device. DO is the most-significant bit.
Clock Input. 500 kHz to 5 MHz. Need not be synchronous to system clock.
Initializes the SMJ9914A at power-on.
Ground reference voltage.
ot
Talk Enable. Controls the direction of the transfer of the line transceivers. Logically, it is:
[CACS + TACS + EIO.ATN.(CIDS + CADS) SWRST].
Remote Enable. Sent by system controller to select control either from the front panel or from
the IEEE bus.
Interface Clear. Sent by the system controller to set the interface system into a known
ot
I/ot
ot
quiescent state. The system controller becomes the controller in charge .
Not Data Accepted. Handshake line. Acceptor sets this false (high) when it has latched the
data from the I/O lines.
Not Ready For Data. Handshake line. Sent by acceptor to indicate readiness for the next byte.
Data Valid. Handshake line controlled by source to show acceptors when valid data is present
to the bus.
End Or Identify. If ATN is false (high), this indicates the end of a message block. If ATN is
true (low). the controller is requesting a parallel poll.
Attention. Sent by controller in charge. When true (low), interface commands are being sent
over the 010 lines. When false (high). these lines carry data ..
Service Request. Set true (low) by a device to indicate a need for service.
Indicates (low) if a device is controller in charge. It is used to control direction of SRO and
ATN in pass control systems. Logically, it is (CIDS + CADS).
0108 through DID 1 are the data input/output lines on the GPIB side. These pins connect to
the IEEE-488 bus via non-inverting transceivers.
Trigger. Activated when the GET command is received over the interface or the fget command
is given by the MPU.
Supply voltage (5 V nominal).
tpush-pull output
"'Open-drain output with no internal pullup
§The hardware RESET pin has the following effect on the SMJ9914A:
- Serial and Parallel Poll registers cleared
-All clear/set auxiliary commands cleared except 'swrst'
-'swrst' auxiliary command set. This holds the SMJ9914A in known states.
'Open-drain output with internal pullup
8-248
TEXAS
"'!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SMJ9914A
GPIB CONTROLLER
Communication between the microprocessor and SMJ9914A is carried out via memory-mapped registers.
There are 13 registers within the SMJ9914A, 6 of which are read and 7 are write. These registers both
pass control data to and get status information from the device. These registers are listed in Table 2 and
shown in Figure 2.
The three least-significant address lines from the MPU are connected to register select lines RSO, RS 1,
and RS2 and determine the particular register selected. The high-order address lines are decoded by external
logic to cause the CE input to the SMJ9914A to be pulled low when anyone of eight consecutive addresses
are selected. Thus the internal registers appear to be situated at eight consecutive locations within the
MPU address space. Reading or writing to these locations transfers information between the SMJ9914A
and the microprocessor. Note that reading and writing to the same location will not access the same register
within the SMJ9914A since they are either read-only or write-only registers. For example, a read operation
with RS2-RSO = 011 gives the current status of the GPIB interface control lines, whereas a write to this
location loads the auxiliary-command register.
Each device on the bus interface is given a 5-bit address enabling it to be addressed as a talker or listener.
This address is set on an external DIP switch (usually at the rear of an instrument) before power-on.
Typical SMJ9914A configuration utilizes registers 100 or 101 as an address switch register (see Table
2.). This register may consist of a DIP switch which drives the data lines via 3-state buffers when one
of these addresses is read. This allows the host MPU to read a device address which is manually set and
write this address into the address register of the SMJ9914A for device identification on the bus. The
SMJ9914A responds by causing a My Address (MA) interrupt and entering the required addressed state
when this address is detected on the GPIB data lines.
TABLE 1. AUXILIARY COMMANDS
CIS
RS2
DESCRIPTION
CLEAR
SET
dacr
dai
feoi
fget
Release DAC holdoff
Disable all interrupts
Send EOI with next byte
Force group execute
trigger
Go to standby
Holdoff on all data
Holdoff on EOI only
Listen only
New byte available false
Pass through next
secondary
Release RFD holdoff
Release control
Request parallel poll
Request control
Request service bit 2
Return to local
Shadow handshake
Send interface clear
Send remote enable
Short T1 settling time
Take control
asynchronously
Take control
synchronously
Talk only
Very short T1 delay
01
13
81
93
06
86
NA
CODE
gts
hdfa
hdfe
Ion
nbaf
pts
rhdf
ric
rpp
rqc
rsv2
rtl
shdw
sic
sre
std1
tca
tcs
ton
vstd1
08
OB
03
04
09
83
84
89
05
14
02
12
OE
8E
18
07
16
OF
10
15
98
87
96
8F
90
95
0
0
0
0
1
1
1
1
ADDRESS
RSO
RSl
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
READ
REGISTERS
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TABLE 2. REGISTER ADDRESSES
MNEMONIC
....en
..
~
~
WRITE
REGISTERS
Interrupt Status 0
Interrupt Mask 0
Interrupt Status 1
Interrupt Mask 1
Address Status
t
Bus Status
Auxiliary Command
t
Address
t
Serial Poll
Command Pass Thru
Parallel Poll
Data In
Data Out
tThe SMJ99 14A host interface data lines will remain in the highimpedance state when these register locations are addressed. An
Address Switch Register may therefore be included in the address
space of the device at these locations.
+This address is not decoded by the SMJ9914A. A write to this
location will have no effect on the device, as if a write had not
occurred.
11
OC
00
OA
17
8A
97
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
8-249
SMJ9914A
GPIB CONTROLLER
reference documentation
• TMS9914A GPIB Controller User's Guide (SPPU013)
• TMS9914A General Purpose Interface Bus (GPIB) Controller Data Manual (MP033A)
AOORESS STATUS REGISTER
DATA-IN REGISTER
ADDRESS )1
RS2 RS1 RSO DO
1
1
ADDRESS )1
RS2 RS1 RSO DO
BIT ASSIGNMENT
01
02
03
04
05
06
07
0
1 1010810107101061010510104101031010210101 GPIB
REM
LLO
ATN
LPAS
DATA-OUT REGISTER
ADDRESS )\
RS2 RS 1 RSO DO
1
1
BIT ASSIGNMENT
01
D2
03
04
05
06
07
1 1010810107101061010510104101031010210101
GPIB
~
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Q)
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0
1
D2
03
04
05
D6
1 1 cs 1 xx 1 xx 1 f4 1 f3 1 f2 1 f1
.oc.
cs
Clear or Set
(')
RS2 RS1 RSO DO
D7
1
1 fO
Cit
Remote State
Local Lockout
Attention
Listener Primary
Addressed State
0
edpa
f4-fO Auxiliary command select
"'C
r::::
03
D5
04
06
D7
1REM 1 LLO 1ATN ILPASITPASILAOSITAOSI ulpa
ADORESS )1
RS2 RS 1 RSO DO
BIT ASSIGNMENT
01
o
D2
TPAS
LAOS
TAOS
ulpa
Talker Primary Addressed Stat
Addressed to listen
Addressed to talk
LSB last address
AOORESS REGISTER
AUXILIARY-COMMAND REGISTER
ADDRESS II
RS2 RS1 RSO DO
1
BIT ASSIGNMENT
D1
das
BIT ASSIGNMENT
01
o Jedpal
D2
03
04
D5
I A3 I
dal I dati A5 I A4
D6
D7
A2 I A1
Enable dual-primary
dat
Oisable talker function
addressing mode
A5-A 1 Primary address
Oisable listener function
INTERRUPT MASK/STATUS REGISTER 0
ADDRESS
0
0
0
0
INn
INTO
BI
BO
o
o
BIT ASSIGNMENT
D1
D2
D3
04
BUS STATUS REGISTER
D5
06
D7
)1
BIT ASSIGNMENT
ADDRESS
INT MASK 0 RS2 RS1 RSO 00 01
02 03 04 D5 06
D7
xx ,I xx I BI I BO I EN~ISPA~I RLC I~AC
INTO INn BI
BO ENO SPAS RLC MAC INT STATO
0
1
1 IATN 10AVlNOACINRFDI EOI ISROIIFC I REN
Interrupt Status Register 1
Interrupt Status Register 0
Byte In
Byte Out
ENO
SPAS
RLC
MAC
Last byte in string received
Oevice has been serial polled
Remote/Local Change
My Address Change
SERIAL POLL REGISTER
ADDRESS
BIT ASSIGNMENT
RS2 RS1 RSO DO
1
0
1
INTERRUPT MASK/STATUS REGISTER 1
ADDRESS
0
1
0
0
1
GET
ERR
UNC
APT
D2
D3
04
D5
06
D7
S8 1rsv11 S6 1 S5 1 S4 1 S3 1 S2 1 S1
0108101071 01061010510104101031010210101 GPIB
BIT ASSIGNMENT
RS2 RS1 RSO DO
0
01
01
D2
03
D4
D5
06
GET I ERR I UNC I APT I~CA~I MA I SRO IIFC
GET ERR UNC APT DCAS MA SRO IFC
Group Execute Trigger
Error
Unrecognized Command
Address Pass Through
OCAS
SRO
MA
IFC
S8,S6-S 1 Oevice Status
D7
rsv1
Request Service bit 1
INT MASK 1
INT STAT 1
Oevice Clear Active State
Service Request
My Address
Interface Clear
COMMAND PASS THROUGH REGISTER
ADDRESS )\
RS2 RS1 RSO DO
1
1
o
BIT ASSIGNMENT
01
02
D3
04
05
06
D7
1010810107101061010510104101031010210101
GPIB
PARALLEL POLL REGISTER
BIT ASSIGNMENT
ADDRESS
RS2 RS1 RSO DO
1
1
0
01
02
03
04
05
06
07
PP8 1PP71 PP6 1 PP51 PP4 1 PP31 PP2 1 PP1
010810107101061010510104101031010210101 GPIB
FIGURE 2_ INTERNAL REGISTERS
8-250
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SMJ9914A
GPIB CONTROLLER
absolute maximum ratings over operating case temperature range (unless otherwise noted) t
Supply voltage range V CC t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All input and output voltage ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
Continuous power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -
- 0.3 V to 20 V
- 0.3 V to 20 V
. . . . . .. 1.0 W
55°C to 110°C
55°C to 150°C
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
:j: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
VCC
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
TC
Operating case temperature
MIN
NOM
MAX
4.75
5
5.25
0
I
V
V
2
I
UNIT
V
0.8
V
All outputs except REN, IFC, INT
-400
p.A
REN, IFC only
-100
p.A
2
rnA
110
°c
-55
electrical characteristics over full range of recommended operating conditions
PARAMETER
VOH
High-level
output voltage
I
TEST CONDITIONS
All outputs except
REN,IFC,INT
10H
I REN, IFC only
VOL
Low-level output voltage
II
Input current (any input)
IOZ
Off-state output current
ICC
VCC supply current
Ci
Input capacitance (any input) t
=
-400 p.A
= -100 p.A
IOL = 2 mA
VCC = 5.25 V, VI =
MAX
5.25 V, Va
UNIT
V
2.2
VSS to VCC
VCC = 5.25 V, Va = 2.4 V
=
TYP
2.4
IOH
VCC
MIN
=
0.4 V
VCC = 5.25 V
f = 1 MHz, all other
pins at 0 V
0.4
V
±10
p.A
20
p.A
-20
p.A
200
mA
15
pF
..
I
tparameter guaranteed via characterization data.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
8-251
SMJ9914A
GPIB CONTROLLER
clock and host interface timing requirements over full range of operating conditions
MIN
~
..
.
o
c.
;:;:
NOM
200
MAX
UNIT
tc(ct»
Clock cycle time
2000
tw(ct>H)
Clock high pulse duration
ns
1955
ns
tw(ct>l)
Clock low pulse duration
tsu(AD)
Address setup time
tsu(DBIN)
DBIN setup time t
tsu(CE)
CE setup time
tsu(WE)
WE setup time t
tw(WE)
WE low pulse duration
80
ns
tsu(DA)
Data setup time
80
ns
th(DA)
Data hold time
15
ns
th(AD)
Address hold time
ns
th(DBIN)
DBIN hold time t
a
a
th(CE)
CE hold time
80
ns
tsu(GR)
ACCGR setup time
100
ns
th(GR)
ACCGR hold time
80
ns
45
ns
a
a
ns
100
ns
a
ns
ns
ns
tparameter guaranteed via characterization data.
D)
'<
host interface timing characteristics over full range of operating conditions
"'C
PARAMETER
MIN
NOM
MAX
UNIT
c
ta(CE)
Access time from CE
150
ns
(')
ta(DBIN)
Access time from DBIN low
150
ns
o
tsu(AD)
Address setup time to CE
td(DBINl-DZ)
DBIN low to data high impedance
50
100
ns
td(CEH-DZ)
CE high to data high impedance
50
100
ns
ta(GR)
Access time from ACCGR low
150
ns
td(AGRH-DZ)
ACCGR high to data high impedance
100
ns
td(GRl-ROH)
Delay of ACCRO high from ACCGR low
100
ns
..
,...
a
ns
50
PARAMETER MEASUREMENT INFORMATION
~
2.07:l =
FROM OUTPUT
UNDER TEST
~
2'11:l
833 n
TEST
POINT
FROM OUTPUT
UNDER TEST
I C l = 50 pF
= 850n
TEST
POINT
I C l = 50 pF
(b) IFC AND REN
(a) ALL OUTPUTS EXCEPT REN AND IFC
NOTE1: Timing measurements are referenced to or from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
FIGURE 3. TEST LOAD CIRCUITS
8-252
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SMJ9914A
GPIB CONTROLLER
20V-l---~V'H(M'N)
1.BBV ....
-----
0.92 V ...
O.BO V....
---
---
-
------
V
IL
(MAX)
o
(a) INPUT
w-i-- ~--2.0VO.BV-
---__
--____
-
VOH (MIN)
_
0.4 V....
VOL (MAX)
o
...uen
(b) OUTPUTS
:::s
..o
..>
"C
FIGURE 4. VOLTAGE REFERENCE LEVELS
D.
CO
OUTPUT
CONTROL
SIGNAL - - - - - - " ' " '
(CE. ACCGR.
\
OR DBIN)
~
~.
_ _ _ _..J.
---t
r-tPLZ
I'Ik ~HI-Z
__ +
{---------------iI -k=--:.---=.{-
rVOL
OUTPUT
~
r-----VIH
1.BB V
A,'
1--11
0.3 V
,--VOL
-
VOH
,, iI ~OH-0.3V
HI-Z
---!
t--tpHZ
FIGURE 5. HIGH-IMPEDANCE MEASUREMENTS
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
8-253
SMJ9914A
GPIB CONTROLLER
clock cycle timing
read cycle timing
DBIN
____Ii+-
\
~~
...
14~---ta(DBIN}----.~1
WE
CE
~
8-254
td(DBINL-DZ}~
~ta(CE}---".1
j.--tsu(WE} ~
I
\~
I
1c
I
~tSU(AD}~
..
). . ---------~¢
00-07
~
VALID ADDRESS
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
IIi-
I
td(CEH-DZ}~
I
RSO-RS2
__
HOUSTON, TEXAS 77001
VALID DATA
}HI.Z-
SMJ9914A
GPIB CONTROLLER
write cycle timing
OBIN
RSO-RS2
...en
00-07
CJ
~
.
"'C
o
NOTE 2: th(AD) and thiDA) are shown measured from the rising edge of WE. This is the correct reference point in this figure, since the
measurements should be from the rising edge of WE or CE - whichever comes first.
~
ca
DMA read operation
..
:l:
\
~
1.
~ td(GRL-RQH)..\
--~"
'il--'
I
OBIN
0..
I
-----I"""'\~
I
I
/
~F--- - - - - - - - -
I
/1
ISEE \
NOTE 31'--J
I
00-07
I
I
~~-----)~---.1
:
\4--ta(OBIN)~
,-
tdIAGRH-OZ)
1
.....- - - t a I G R ) - - - - J
NOTE 3: A write-enable pulse may occur in a DMA read operation. A write-enable pulse may therefore be provided for system
memory and need not be suppressed at the SMJ9914A.
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
8-255
SMJ9914A
GPIB CONTROLLER
DMA write operation
rtW(WE----!
It
'1-
I
I
I...·.....-----.;..I·'·'GO,
X
ACCGR
j.tSU(DBINI
~
"I _J- '
I ;;1
I
1
....I----th(GRI----.~r_th(OBINII
OBIN~
I
t
~tsu(OA)
\!
I
I I
~
..-...--th(OA) t - . l
I---tsU(OA)t--.t.t
t.,1
I
h(OA)
00-07
--_____________--J>¢"
~
VALID DATA
ttsu(DA)and thIDA) are only applicable to the first signal to become inactive, whether it is
WE or
ACCGR.
source handshake timing characteristics over full range of operating conditions (see Note 4)
PARAMETER
..
td1
MIN
MAX
12(1i + 310
Short T 1 (see Note 5)
8(li + 310
ns
140
ns
TEST CONDITIONS
Delay of DAV true from end
Normal T 1 (see Note 5)
of write operation to
data out register
UNIT
ns
Delay of valid GPIB
td2
data lines from end of
write cycle
td3
DelaYof BO interrupt from DAC true
300
ns
td4
Delay of ACCRa DAC true
BO interrupt unmasked
300
ns
td5
Delay of DAV false from DAC true
160
ns
NOTES: 4. The timing of the source handshake is the same whether ATN is true or false; i.e., whether the device is in TACS, CACS, or SPAS.
5. A very short bus settling time (T 1) occurs on the second and subsequent data byte when ATN is false if the "vstd 1" feature
is set. A slightly longer bus settling time takes place if "std1" is set unless there is a very short bus settling time. In all other
instances, a normal bus settling time occurs.
8-256
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SMJ9914A
GPIB CONTROLLER
acceptor handshake timing characteristics over full range of operating conditions
PARAMETER
TEST CONDITIONS
td6
td7
td8
ATN
from DAV true
=
false,
=
Delay of ACCRO from
ATN
DAV true
device is in LACS
Delay of NDAC false
ATN
from DA V true
device in LACS
ATN
end of read operation
ATN
2(li
2(li + 415
ns
7(li + 415
ns
UNIT
=
=
false,
false,
false,
=
false,
device not in CACS,
Delay of interface
all interface
message interupt
message interrupts
from DA V true
(except UNC)
UNC interrupt only
ATN
Delay of NDAC false
tdll
2(-
ns
ca
operation
td13
=
Delay of NRFD false
ATN
from DA V false
device not in CACS
true,
180
:s
..
~
ns
I
NOTE 6: The interrupts generated by interface messages are shown in Table 3-15 of the TMS9914A General Purpose Interface Bus (GPIB)
Controller Data Manual (MP033A).
ATN, EOI, and IFe timing characteristics over full range of operating conditions
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td14
Delay of NDAC true from ATN true
Device is not in CACS
195
td15
Delay of TE high from EOI true
Device is not in CACS
125
ns
td16
Delay of valid data from EOI true
Device is not in CACS
140
ns
td17
Delay of TE low from EOI false
Device is not in CACS
125
ns
td18
Delay of NRFD true from ATN false
Device is in LADS/LACS
140
ns
td19
Response time to IFC
30tGlOl
ns
16tc (0)
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
ns
8-257
SMJ9914A
GPIB CONTROLLER
controller timing characteristics over full range of operating conditions
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay of A TN true
td20
from end of tca
Stc(O)
10(.p)t
+ 220
ns
1Stc (0)
22(.plt
+ 415
ns
Stc(O)
10(.plt
+ 220
ns
22(.p)t + 415
ns
230
ns
230
ns
+ 415
ns
210
ns
auxiliary command
Delay of BO interrupt
td21
from end of tca
auxiliary command
Delay of A TN true
td22
from end of tcs
auxiliary command
Delay of BO interrupt
td23
from end of tcs
auxiliary command
BO unmasked.
device is in ANRS
BO unmasked.
device is in ANRS
18tc (0)
Delay of EOI true from
td24
rpp auxiliary command set
Delay of EOI false from
td25
rpp auxiliary command set
Delay of BO interrupt from rpp
td26
auxiliary command cleared
Delay of ATN false from
td27
8-258
gts auxiliary command
BO unmasked
8t c (0)
Device is not in SDYS or STRS
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
10(.plt
SMJ9914A
GPIB CONTROLLER
SMJ9914A source and acceptor handshake timing(s)
WE
--vr
=..,J
010S-0101
S
o
U
R
C
E
INT
ACCRa
ACCGR
~td2
II~
_ _
----------J1I
----7.
~----------------------------------------
II
\
r------
r-td3~
I
/rl-.;.....-----------.;:~\r-----\
,
~td4
"
,
I
~td5
'-_J1
OAV
~~____---:~/r-----------i\-t
.
III
j+-- t
NRFO
(SEE NOTE 7)
d1---1
td9~
1\
I -----~------~;---r- ---!
I
r---\___
1fIJ/1I//II//!I
I
..
tdS
NOAC
A
C
C
I
INT
I
E
T
\
j.-tdS--l (SEE NOTE S)
P
ACCRa
0
--------------------------:~~~---------_/
J-......f- t d7
R
ACCGR
\ ,1
"--' I
cJ
CE
NOTES: 7. The interrupt line is taken low by a BO interrupt.
S. The interrupt line is taken low by a BI interrupt.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
8-259
SMJ9914A
GPIB CONTROLLER
SMJ9914A acceptor handshake timing "ATN" true
III
i--- td11 - - - . ,
A
NDAC
C
C
E
P
T
INT
!
-I
td12
/~S;E~;~;j"--T\,-____
I
- - - - - - 1--~\
I
;,----------
o
R
i4- td10--.f
1
V\JJ
I
CE
..
v
WE
I
I
READ INTERRUPT
STATUS
WRITE dacr TO
AUXILIARY
COMMAND REGISTER
NOTE 9: The broken line shows the waveform if there is no DAC holdoff. The solid lines assume there is a DAC holdoff.
8-260
TEXAS
"!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SMJ9914A
GPIB CONTROLLER
SMJ9914A response to 'ATN' and 'EOI'
ATN
~F-----_-JX
I
\
EOI
~td15
t
TE
NOAC
I
td17
L
NRFO
"
1
/.
\-,
(SEE NOTE 10)
I
HI -Z
I
'--__--J"'.-----
\
CJ
..
..
::::s
"'0
I
~td14
OAV
...tn
jHI-Z\
--'I
o
\"--_ _ _1 _ -
---HI-Z ____
CL.
>
ca
~td16
0108-0101
--------~~~-~----~)~--~---I----~
r--;t d19
IFC
(SEE NOTE 111
~I'-_ _~_ _ __
I
..
:l:
~
~F--I-
INT
NOTES: 10_ This assumes that an RFD hold off occurs.
11. IFC causes the SMJ9914A to be unaddressed and an IFC interrupt occurs.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
8-261
SMJ9914A
GPIB CONTROLLER
SMJ9914A controller timing
ATN
EOI
INT
CE
~
;+
WE
m
-<
".
o
c.
..
WRITE
tcs or tca
c
READ INT
STAT 0
"",""""--_~I
,-I_--'
CLEAR
rpp
WRITE
gts
SET
rpp
(')
0+
(II
NOTE 12: A BO interrupt occurs as the SMJ9914A enters CACS .
8-262
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
General Information
Alternate Source Directories
Glossary/Timing Conventions/Data Sheet Structure
Dynamic RAMs
Dynamic RAM Modules
EPROMs/PROMs/EEPROMs
VLSI Memory Management Products
Military Products
Applications Information
Quality and Reliability
Logic Symbols
Mechanical Data
ESD Guidelines
f'~~?;
l>
"25"
'C
,..
CI)
0"
:::s
en
S'"
....
o
.
3CI)
,..
..
0"
:::s
9-2
Designing' and Manufacturing
Surface Mount Assemblies
Elizabeth Gunther, Charles Hutchins, and Paul Peterson
The competitive nature of the semiconductor industry has
driven vendors to minimize the size of electronic components,
so that more functions can be achieved in a given volume.
In addition, improved electrical performance, decreased mass,
and the potential for lower system cost are all by-products
of compacted packaging and circuitry which hold interest to
component manufacturers and users alike.
Surface Mount Technology (SMT) offers an excellent
method of reducing component size. A typical memory array can be reduced to 50 percent of its original PWB size
with single-sided mounting, and 25 to 30 percent with doublesided mounting. Logic designs cannot achieve the same
dramatic reduction, but decreases up to 40 to 60 percent can
be achieved for single-sided and double-sided assemblies
respectively.
The key design and manufacturing process issues must
be understood in order to fully reap the benefits of Surface
Mount Technology. This article gives a general overview of
the key aspects of design, process, and manufacturing of surface mounted assemblies, and offers surface mount as an opportunity to lower a system's cost without sacrificing
reliability.
Components
Most surface mount components are at least one-third
the size of the comparable through-hole mounted device (Figure 1). The 68-pin chip carrier is approxmiately one square
inch, while the 64-pin DIP is approximately three square inches. The 20-pin chip carrier is slightly larger than 0.1 square
inch, while the 20-pin DIP is 0.3 square inch. Similarly, other
IC packages are reduced to approximately one-third the size
of comparable lead count packages. The passive components
occupy approximately one-tenth the board area, and this is
why they have been used in most small consumer products
built in the last couple of years.
There were many references in the recent past to problems with component availability, cost, and standardization.
This area of SMT has probably received more attention than
any other. Several recent magazine articles now state that
significantly more components (particularly actives) are now
available and that cost parity has been achieved on most of
them. The effort by various industry committees on standardization has also been effective.
Thus, although more needs to be accomplished in these
areas, a designer can begin a project with confidence that
there will be no insurmountable barriers in this area. There
are several consultants and subcontract assembly companies
to assist in this effort. It is strongly recommended that all
new designs utilize some form of SMT, particularly when
space is an important consideration.
Process
The process to manufacture a surface mount assembly
(SMA) is very simple. It consists of four basic steps, as shown
in Figure 2. First, the solder paste is screened on the PWB.
Then the component is placed on the board, with due care
to get it positioned correctly. Typical geometries require
placement accuracy of less than plus/minus 4 mils. Next the
solder is reflowed with either a vapor phase or infrared
system. Finally, the assembly is cleaned and is now ready
for test. This process, although simple in concept, relies on
board and component planarity and solderability. These are
easily achievable with the chip carriers and memory modules
we will discuss later.
Texas Instruments has installed a Surface Mount
Technology Center at its plant in Houston, Texas. At this center, we have a complete and flexible engineering line to assist
our customers in converting to Surface Mount Technology.
The engineering line is equipped with a screen printer, pick and place system, vapor phase reflow, and clean-up
station that will easily handle PWBs up to 9/1 X 10/1. Larger
boards up to 14/1 X 16" can be processed with some additional care. TI uses this engineering line to produce its prototype and demo boards. It is also available to any of TI's
customers, free of charge, for use in building test or prototype
boards.
The effectiveness of the assembly process can be
characterized by the number of unacceptable solder joints
formed during the process. Unacceptable joints are defined
by their electrical and mechanical (strength and reliability)
characteristics. The major problem is open solder joints,
followed by bridging and misregistration.
Figure 1. Component Site Reduction
9-3
c:
o
'+=i
CO
...E
o
'to-
.5
t/)
c:
o
'+=i
CO
,2
C.
Q.
'Eo
20
.475
.430
.070
.025
.050
24
.575
.430
.070
.025
.050
Test
4164A PLCC 4164 DIP
Units
'C
42
64
85°C/85% RH
0.17
0.37
%/1000 Hours
:s
Autoclave
0.17
0.96
%/240 Hours
S
....
T/C-65/150
0.52
1.44
%/1000 Cycles
0.0
0.0
%/2000 Cycles
Cr
....O·
D)
en
o...
3D)
....
o·
..
Life Test. 125°C
T/C 0/125
Fits*-60% UCL
*Derated to 55°C Assuming 0.5EV Activation Energy
:s
Figure 5. Failure Rate Comparison
4164A PLCC VS DIP
probably be the most expensive item in the list above and
therefore, should get the most attention.
The gross number of components and PWBs will provide data for choosing the pick and place. Component per
hour placement speed should be checked in actual operation,
as the interrelationship may affect ultimate speed. The number
of different components per board will determine how many
feeders and what types of feeders will be required. This is
a very key issue, as well as the accuracy of placement.
Reflow
The solder reflow is easily achieved with any of the
commercially available equipment. Subtle differences between vapor phase, either batch or in-line, and infrared are
overshadowed by the choice of solder paste and the
solderability/planarity issue. A batch vapor phase is extremely
flexible for different sizes of boards with different component counts. The in-line vapor phase is a good choice for a
more automated processing line with standard or similar sized
boards. The infrared has the advantage of being less expensive to operate, but requires more alteration to set up the timetemperature profile for a different size PWB. This would be
a minimal problem on a manufacturing line building high
volumes of the same board.
Clean-up
The most popular flux for SMT is the mildly activated
rosin flux (RMA). This was developed in the days of vacuum
tube assembly when clean-up was next to impossible. It is
noncorrosive but provides sufficient fluxing action for good
quality components and PWBs. Thus it is the preferred choice
for SMAs with small spacings under most passives and
SOICs, where complete cleaning is difficult. A mild solvent,
such as Freon TMS, is generally sufficient to achieve a good
visual cleanup, and there are several systems available that
provide hot vapor, spray, or ultrasonic de-fluxing.
Reliability
Manufacturing
The SMT manufacturing area must have the following
basic equipment:
• Solder Paste Printer
• Component Pick and Place Machine
• Solder Paste Reflow Machine
• Clean-up System
• Inspection/Process Control Aids
• Electrical Test
The criteria for choosing the above is determined mainly by the size(s) and quantity of PWBs per month, the gross
number of components per PWB, and the number of different
components per PWB.
The size of the largest PWB is an important criterion
in the choice of all of the major items. The printer, pick and
place, reflow, and clean-up must all be able to handle it with
no difficulty or process nonuniformity. The number and size
of the various PWBs that may be produced will secondarily
be considered for ease of set up and changeover in the printer and pick and place. The pick and place machine(s) will
9-6
With the smaller surface mount packages, there is some
concern about component reliability. Texas Instruments addressed the overall DRAM reliability issue several years ago.
Through an extensive task force effort, the major problems
of the life test, humidity performance, and temperature cycle were identified. The best solutions to these problems required several changes in the design and process of the silicon
chip. In doing so, the reliability of the DRAM chip became
independent 0f the package used. Thus, the 64K DRAM in
the plastic chip carrier package performs equivalently to the
same chip in a DIP as shown in Figure 5. Similar data is
available on most semiconductor ICs.
An additional reliability concern originates in the surface mount solder reflow process, which submits components
to higher reflow temperatures more suddenly than the wavesoldering methods of DIP components, with oftentimes
repeated reflow cycles for rework and repair.
The best method for resolving this issue involves comparing the temperature-time differential of the vapor phase
or infrared solder reflow process to the standard temperaturc
cycling reliability tests to which surface mount components
are routinely submitted. Figures 6 and 7 show temperature
profiles of the vapor phase and infrared solder reflow processes. In the vapor phase process, the maximum temperature
change with time is:
45 sec
45 sec
equaling approximately 4°C/sec. The infrared solder reflow
method submits the ICs to a similar, yet less severe
temperature over time change of 3°C/second. Comparing
these temperature profile ramp-ups to that which a surface
mount component undergoes in a temperature cycling
reliability test proves that there should be no concern over
damage to the component during reflow. In the temp cycling
test, the surface mount components were submitted to 1000
cycles of sudden cycling from 150°C to -65°C within three
seconds. This represents a temperature-time differential of:
3 sec
3
sec
with less than 0.5 percent failures.
Since the surface mounted components were able to
withstand a 70°C/second temperature change of 1000 cycles,
they should be able to withstand the less severe conditions
of a 4°C/second damage during reflow without reliability
degradation.
Another concern in the solder reflow processing of surface mount components is the dwell time in reflow
temperatures of 215°C or above. The dwell time for a small
PWB populated with surface mount devices is about 20
seconds. For a larger board of about 10" x!2" up to 50
seconds is needed for reflow. A generalized component
degradation curve, relating accumulated time and
temperature, can be assumed to exist. The shape of the curve
for this discussion is assumed to be a decaying parabolic for
simplicity and conservatism. There are two generally known
points of this curve. The flame retardant mold compound
(FRMC) of a plastic package starts to break down at 300°C
in two to three seconds. Also, the molding and curing of a
surface mount device is performed over several hours at
175°C. These two points are shown on the generalized curve
shown in Figure 8, with the "safe" region being the area under
the curve. Two points that fall within this region are the industry standard practice of solder dipping leads of several
types ofICs, and of the soldering plastic devices on the bottom with Type III surface mount assembly, each submerges
the component for three to four seconds in a solder wave.
c
o
'.j:i
as
.
E
o
'to-
C
200
(I)
t:
o
300
150
'.j:i
as
a... u
250
CQC. _
CD
215
E
200
CD
100
~
50
°
150
Time (seconds)
o
Figure 6. Typical Temperature Profile
for In-Line Vapor Phase Reflow
20
40
60
80
100 120 140 160
180
Time. MIN.
Figure 8. General Plastic Degradation Curve
Summary
30
60
90
120
150
180
210
Time (seconds)
Figure 7. Typical
m Reflow System Profile
240
,~
..
Molding and Curing
Point
Surface mount assembly techniques provide a significant advantage in cost, volume, and reliability over the current "thru-hole" technology. These are well documented, and
the manufacturing equipment and related products are becoming readily available to support new production lines. Also,
as experience grows, improved products and ideas are developed from the cooperative efforts of vendors and users in standardization organizations and in problem-solving sessions.
The broad selection of package types and product technologies
available now are sufficient to begin conversion of existing
electronic system products for size reduction or feature
enhancement. Definitely, new products should be designed
with surface mount technology.
9-7
C.
c.
--4
f---./
16~
17~
..
.;!9
.,.
,.
~
V4
..-+------1 1 0-11
V4
2
3-
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18
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13
14 1
15
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10.4.5V
11.4.5V ...
(27)
RASI - - - - - - . . .
•ALS2968 ONLY
----------+-+--f
__~+_+__+_+-+_+__4 G5
LATCHES
LE
1141
AO
131
A3
A4
A5
A6
A7
J
~1
9X
IROWI
Al~
A2
A13
A14
A15
A16
A17
SELO
SEL 1
1111
1151
1171
1191
1291
RASO
RASl
~2
RAS3
9
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CAS DECODE
DMUX
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(8)
(10)
(12)
~
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(COLUMN]
'----t--l~-t
~
1161
(18)
(20)
(22)
9
10
---
-O} 5Z
3
10
n
0}6G~
10
~~2~7...E~Y_ -
G5
G6
10
1
--- -e-T-+--------t
...!.4~ -
CAS I
..!~ ___ ~~S~6!:.O~:" _ _ _ _ _ _ _ _
-
G4
1
I- G4
(24)
-
o
2
'-------+------1-t--i 1
(BANKI
1231
1
'------t--t--i 2
CASi
-
J
110/20.417 V
111/21.4)7V
G7
112/22.4)7 V
113/23.4)7 V
Figure 2-1. 'ALS2967, 'ALS2968 Functional Block Diagram
9-10
(31)
.J21
A9~
A12
13.4.5V
(45)
...!l!l.--
A8~
:~~
12.4.5V ~
,.
....
(47)
1461
1441
(30)
1281
000
001
CAS2
CAS3
Table 2-1 describes the four operating modes of the 'ALS2967 and 'ALS2968 as
controlled by inputs MCO and MC1. During normal read/write operatio'ns, the row
and column addresses are multiplexed to the DRAM. When MSEL is high, the column
address is selected; when MSEL is low, the row address is selected. The corresponding
RASn and CASn output signals strobe the addresses into the selected memory bank
or banks. A single 'ALS2967 or 'ALS2968 can control as many as four banks of 256K
memory. Additional banks of memory can be controlled by using additional 'ALS2967
or 'ALS2968 devices and decoding each chip select (CS) input.
Table 2-1. 'ALS2967, 'ALS2968 Mode-Control Function Table
SIGNAL
MCl
MCO
L
L
MODE SELECTED
Refresh without Scrubbing. Refresh cycles are performed using
the row counter to generate the addresses. In this mode, all four
RAS outputs are active while the four CAS outputs remain high.
L
H
Refresh with Scrubbing/Initialize. Refresh cycles are performed
c
o
using both the row and column counters to generate the
0';::;
addresses. MSEL selects the row or the column counter. All four
ca
RAS outputs go low in response to RASI ('ALS2967) or RASI
('ALS2968). while only one CASn output goes low in response
to CAS I ('ALS2967) or CAS I ('ALS2968). The bank counter keeps
track of which CAS output goes active. This mode can also be
used during system power-up so that the memory can be written
with a known data pattern.
H
L
Read/Write. This mode is used to perform read/write cycles. Both
en
c
o
0';::;
ca
..
Q.
output lines using MSEL. SELO and SELl are decoded to
c.
determine which RASn and CASn outputs will be active.
H
'to-
.5
o~
the row and column addresses are multiplexed to the address
H
...oE
<
Clear Refresh Counters. This mode clears the three refresh
counters (row, column, and bank) on the inactive transition of
RASI ('ALS2967) or RASI ('ALS2968). putting them at the
beginning of the refresh sequence. In this mode, all four RAS
outputs are driven low after the active edge of RASI ('ALS2967)
or RASI ('ALS2968) so that DRAM wake-up cycles can also be
performed.
In systems where addresses and data are both multiplexed onto a single bus, the
'ALS2967 and 'ALS2968 use latches (row, column and bank) to hold the address
information. The 20 input latches are transparent when the latch enable input (LE)
is high; the input data is latched whenever LE goes low. For systems in which the
processor has separate address and data buses, LE may be tied high.
The two 9-bit counters in the 'ALS2967 and 'ALS2968 support 128, 256, and 512
line refresh operations. Transparent, burst, synchronous, or asynchronous refresh
modes are all possible as determined by the memory timing controller. The refresh
counters are advanced on the low-to-high transition of RASI on the 'ALS2967, and
on the high-to-Iow transition of RASI on the 'ALS2968. This is true in either refresh
mode. In the clear refresh counter mode, the refresh counters (row, column, and bank)
can be reset to zero on the low-to-high transition of RASI on the 'ALS2967 or on
the high-to-Iow transition of RASI on the 'ALS2968.
9-11
2.2.2
Typical Implementation
Figure 2-2 shows a system interface using the 'ALS2967 between an Intel 8086 and
four banks of 256K DRAMs. Addresses A 18 and A 19 are used to select one of the
four memory banks. Since members of the 8086 processor family multiplex both data
and addresses onto the same data bus, input latches on the 'ALS2967 must be used
to store the row, column, and bank information. The ALE signal from the 8086 can
be directly connected to the latch enable (LE) input on the 'ALS2967.
The RASI, CASI, MSEL and mode control (MCO, MC1) inputs on the 'ALS2967 must
be generated by the memory timing controller. The memory timing controller functions
as an arbitrator between refresh cycles and 8086 access cycles. It also guarantees
that timing requirements of the DRAM will be met.
DYNAMIC
MEMORY
CONTROLLER
DYNAMIC RAMs
REFRESH
TIMER
l>
~ SANKO
~
---y'
RFC ....- - - - - - - - - - ,
'C
"E-
REFREQ
-
...s·rr
RESET
Q)
r---
'ALS2967
ft-
::s
-
- - . RASO
-
- - . CASO
---'Iii
TIMING
CONTROLLER
CLOCK
GENERATOR
II
(I)
S2S4A
5"
-h
o...
~ REFREO
ROY M-+----I ROY
CLK
3Q)
osc
...s·
256K X 16-BIT
TMS4256 (16)
BANK 1
RFC
r--
OS-OO:=:
~
'r-
-+
-+
RESET
' - - - - - - ' H OSC
..
256K X 16-BIT
TMS4256 (16)
AS-AO
AS-AO
RAS1
CAS1
...... N
::s
CLK READY
SOS6-2
RASI---~
RASI
CASI---~
CASI
MSEL
.
M/lOI----..... M/iO
RDt--<__- ..... -RD
r
.. WR
II
1----., MSEL
~
---.
---.
r
MC1
J:-
MC1
MCO
rr-
......
AS-AO
RAS2
CAS2
Iii
II
ALE
ALE~~~~-------~
LE
A
J.. ROW (AS-AO)
A 17-AO I\,r-T-r------, r - - - - - - V ' I COL (A9-A 17)
,.
A1S~~r_---,
A19~~r_---,
256K X 16-BIT
TMS4256 (16)
BANK 2
r---~H
r---~H
BANK 3
-~
AS-AO
256K X 16-SIT
TMS4256 (16)
.... RAS3
SELO
SEL1
CAS3
.-. Iii
<
l
015-00
rnIlAl.-·A_S_2_4_0_ _ _ _--'
'---
L---------------------4G
,
Figure 2-2. 'ALS2967, 'ALS2968 Timing Controller Interface
9-12
015-00
2.2.3
Timing Controller Details
Figure 2-3 is a timing diagram for a typical 8086 access cycle. The 'ALS2967 control
signals required to execute the access cycle are also shown. Control signals for the
'ALS2967 are referenced from the OSC output of the 8284A clock generator. The
timing controller in this example is generated from a state machine referenced from
the OSC output of the 8284A. In critical timing situations, it may be necessary to
tightly control the phase relationship of the system clock to the OSC signal. This can
be accomplished by using a phase lock loop or similar method to generate the OSC
signal.
\4--t,
_14
t2
-14
_14
t3
t4----+1
CLK
/
ALE
\
I
I
C
I
I
I
MilO
I
I
X:
!lDX
(
AO-A17
I
\
I
I
X:
![ADX
E
X
AO-A17
I
I
I
WR
en
C
0
".t=
X
WRI1E DATA
I
I
I
I
\
I
ST21
ca
"~
Q.
/
STO
ST26
I
RAS
I
I
I
I
/
I
\
I
/
MSEL
I
S10
~Ta(c)--.I
/
\
CAS
REFREQ
= H. RESET = L
MC1
= li.
RFC
= L.
ROY
..
Co
----
i
"
AO-A17
ST2
ST3 ST4 ST5 ST6 ST7
STS
ST9 STO
I STO
(IF ROY = HI
STO
DSC
MCl
ROY
RFC
RAS
MSEL
CAS
\
,__________'- ________ .\._. __________1
------------~/
\~-------------------------------------------\'-__________--J/
\~------_____~I
------------------------------------~I
\~------
\~------------------~I
Figure 2-4. Refresh/Access Cycle
9-14
INITIALIZE
(RESET = H)
STO
MCI = H
RAS = H
ROY = H
MSEL= L
RFC = L
CAS = H
c
o
'';:'
ca
...E
....o
REFRESH CYCLE
ST 1 THRU
ST9
(FIGURE 4)
.5
en
NOTE:
'';:'
C
o
ca
IF ALE&M/lO=H
THEN
ROY = L
ACCESS CYCLE
ST 21 THRU
ST30
(FIGURE 3)
,~
Q.
c.
«
IF RESET = H
THEN
INITIALIZE
NOTE:
IF RESET = H
THEN
INITIALIZE
YES
ACCESS CYCLE
(FIGURE 4)
ST10 THRU
ST20
Figure 2-5. 'ALS2967, 'ALS2968 Memory Timing Controller Flow Chart
9-15
Figure 2-6 shows the actual circuit implementation of the refresh and memory timing
controller. The refresh timer signals the controller whenever it is time to execute a
refresh cycle. As required by memory, every row (256 on the TMS4256 DRAM) must
be addressed every 4 ms. This implies that one row should be refreshed at least once
every 15.6 I's. With an 8-MHz system clock, the refresh timer should use
approximately a division factor of 122. This results in a refresh request every 15.3 I's.
The refresh complete input (RFC) is used to signal the refresh timer that the refresh
has been completed. It is important that the timer not stop so that the 4-ms memory
requirement is maintained.
TIMING CONTROllER
r---------------------------~(3~)~RESET
REFRESH TIMER
>
'C
TIBB2S167B
(2)
'2.
RESET
5"
RFC M-.:..;(3;.:,.)_ _ _ _ _ _ _..:....:..:~ RFC
....m
0"
REFREQ t-"-(1_9..;..)_ _ _ _ _ _ _.:..::.:....
::::J
en
TIBPAl16RB
S-
.3
O'
(1)
MIlO
ClK
m
....
..
0"
::::J
Figure 2-6. Refresh/Memory Timing Controller
The TIBPAL 16R8 circuit shown in Figure 2-6 is used to generate the refresh request
signal every 122 clock cycles. The refresh request signal (active low) will remain active
(low) until a refresh complete (RFC) signal is received from the timing controller. During
a system reset, the refresh request output is set to a high-logic level. When using
different clock rates or memory sizes, the division circuit in the refresh timer should
be adjusted accordingly.
The TIB82S167B field programmable sequencer shown in Figure 2-6 is configured
as a state machine to execute the flow chart shown in Figure 2-5. In cases with
different system timings, the CUPLTM file can be modified to fit the processor
requirements. In addition, a slight modification to the file will allow an ' ALS2968 to
be used instead of an ' ALS2967.
A preprogrammed sample of the refresh and timing controllers shown in Figure 2-6
can be obtained by calling PAL/PROM Applications, 214/995-2980.
2.2.4
Summary
The 'ALS2967 and 'ALS2968, coupled with programmable logic, offer the system
designer a solution to high-speed dynamic memory requirements. Programmable logic
allows the designer to tailor the timing controller to a selected processor and memory.
In many cases, the generation of a high-speed timing controller from programmable
logic will allow the designer to use slower DRAMs without affecting system speed.
This results in lower total system cost because of the large number of memory devices
used.
9-16
2.2.5
ABELTM and CUPLTM Files
2.2.5. 1 ABELTM File
module RF_TIMER
title 'REFRESH TIMER
R. K. BREUNINGER
RFT
DEVICE
TEXAS INSTRUMENTS, DALLAS, 08/12/86'
'PI6R8';
"input declarations
CLK
RESET
RFC
OE
pin
pin
pin
pin
1:
2;
3:
11:
" SYSTEM CLOCK (8086)
" RESETS WHEN HIGH
" REFRESH COMPLETE
" MUST BE TIED LOW
"output declarations
QO,Q1,Q2
Q3,Q4,Q5,Q6
REFREQ_
pin 12,13,14:
pin 15,16,17,18:
pin 19:
c
o
"';=
" COUNTER STATES
" COUNTER STATES
" REFRESH REQUEST - ACTIVE LOW
.J2E
(U
"intermediate variables
.5
en
QO & IQI & !02 & 03 & 04 & 05 & Q6:
RESET # CNT_REF:
[06,Q5,04,03,02,QI,QO]:
CNT REF
SCLR
count
C,H,L
c
o
"+i
(U
.c., 1 ,0;
"~
Q.
..
equations
REFREQ_
QO
QI
Q2
Q3
04
Q5
06
Q.
.....-
...-
test_vectors
@CONST cnt
«
RFC # !CNT_REF & REFREQ_ # RESET:
(IQO ) & ISCLR:
( Q1 $ QO) & I SCLR;
( Q2 $ Q1 & 00) & !SCLR:
( 03 $ (02 & 01 & 00» & ISCLR:
( 04 $ (Q3 & Q2 & Q1 & 00» & !SCLR:
( Q5 $ (Q4 & 03 & Q2 & QI & QO» & !SCLR:
1(105 & IQ6 # 104 & 106 # IQ3 & IQ6
# IQO & IQ6 # 102 & 106 # IQ1 & !06 # SCLR):
= I:
@CONST cnt
@REPEAT 121
I; @REPEAT 20
([OE,RESET,CLK,RFC]
[0, I ,C, 0 ]
[0, 0 ,C, 0 ]
@CONST cnt = cnt +
-) [count,REFREQ_])
-) [ 0 ,
H ];
-) [ cnt,
H ]:
I:}
[ 0,
0 , C , o ] -) [ 0 ,
[ 0, 0 , C , o ] -) [ cnt
@CONST cnt = cnt + I; }
0,
0,
0
0
0
, C , 1
, C , 0
, C , 0
-)
21
22
23
0,
0
, C , 0
-)
24
0,
-)
-)
,
,
L
L
];
]:
H
H
H
H
end RF_TIMER
9-17
2.2.5.2
CUPLTM Source File
Partno
Name
Date
Revision
Designer
Company
Assembly
Location
MTC-SI67
MTC-SI67
08/13/86
03;
BREUNINGER;
TEXAS INSTRUMENTS;
None;
DALLAS, TEXAS;
/***************************************************** ***********1
1*
DYNAMIC TIMING CONTROLER
*/
/*
(FOR ALS2967)
*1
1***************************************************** ***********/
1* Allowable Target Device Types: TIB82S167B
*/
1****************************************************************1
/**
:t>
pin
pin
pin
pin
pin
pin
pin
pin
'C
'2.
c;"
cu
....
2)"
:s
en
5'"
0'
...
/**
3cu
pin
pin
pin
pin
pin
pin
....
0"
:s
Inputs **1
OSC;
REFREQi
RESET;
3
4 MIOi
5 RDi
6 WR;
7 ALE;
16 = GNDi
I
2
Outputs **/
9 MCI _i
10
MSELi
II
CAS;
RAS;
13
14
RDYi
IS
RFCi
1*
1*
/*
1*
1*
1*
1*
1*
1*
/*
1*
1*
/*
/*
/** Internal Node Group node [P4_,P3_,P2_,PI_,PO_];
OSCILLATOR (8284A)
REFRESH REQUEST
RESET - INITIALIZES WHEN HIGH
MEMORY 1/0
READ
WRITE
ADDRESS LATCH ENABLE
PIN 16 MUST BE TIED LOW
*/
*1
*1
*1
*1
*1
MODE CONTROL
MULTIPLEXER SELECT
COLUMN ADDRESS STROBE
ROW ADDRESS STOBE
READY
REFRESH COMPLETE
*1
*/
*/
*/
*1
*/
State bits declared as nodes
1** Declarations and Intermediate Variable Definitions
Field State = [P4_,P3_,P2_,PI_,PO_];
$define
$deflne
$deflne
$deflne
$deflne
$deflne
$deflne
$deflne
$define
$deflne
$deflne
$define
$define
9-18
STO
STI
ST2
ST3
ST4
ST5
ST6
ST7
ST8
ST9
STIO
STII
STI2
'b'OOOOO
'b'OOOOI
'b'OOOIO
'b'OOOII
'b'OOIOO
'b'OOIOI
'b'OOIIO
'b'OOIII
'b'OIOOO
'b'OIOOI
'b'OIOIO
'b'OIOII
'b'OIIOO
*/
*/
**1
**1
$define
$define
$define
$define
$define
$define
$define
$define
$define
$define
$define
$define
$deffne
$define
$define
$define
$define
$define
$define
STI3
STI4
STI5
STI6
STI7
STI8
STI9
ST20
ST21
5T22
5T23
5T24
5T25
5T26
5T27
5T28
5T29
5T30
5T31
'b'OIIOI
'b'OIIIO
'b'OIIII
'b'IOOOO
'b'IOOOI
'b'IOOIO
'b'IOOII
'b'IOIOO
'b'IOIOI
'b'IOIIO
'b'IOIII
'b'IIOOO
'b'IIOOI
'b'11010
'b'IIOll
'b'IIIOO
'b'IIIOl
'b'IIIIO
'b'llI11
c:
o
"';:;
/** Logic Equations **/
Sequence State
NEXT
{Present STO IF RESET
IF IRESET & !REFREQ NEXT
IF !RESET & REFREQ & ALE
NEXT
DEFAULT
ALE & MIO&!RESET
!RESET
ALE & MIO&!RESET
IRESET
ALE & MIO&!RESET
!RESET
ALE & MIO&IRESET
IRESET
ALE & MIO&!RESET
IRESET
ALE & MIO&!RESET
!RESET
ALE & MIO&!RESET
I RESET
ALE & MIO&!RESET
!RESET
ROY & IRESET
IROY & !RESET
STO OUT [MCI_. ROY.IRFC. RA5.IM5EL. CAS];
STI:
& MIO NEXT ST21;
STO;
....
.5
en
c:
o
"';:;
/** REFRESH CYCLE **/
Present STI IF
IF
Present ST2 IF
IF
Present ST3 IF
IF
Present ST4 IF
IF
Present ST5 IF
IF
Present ST6 IF
IF
Present ST7 IF
IF
Present ST8 IF
IF
Present ST9 IF
IF
CO
...oE
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
ST2 OUT [IMCI_. !ROY];
ST2 OUT [!MCl_]:
ST3 OUT [!ROY, RFC.IRAS]:
ST3 OUT [ RFC.!RAS]:
ST4 OUT [!ROY]:
ST4:
ST5 OUT [!ROy] :
ST5:
ST6 OUT [IROy] ;
ST6:
ST7 OUT [ ! ROY. ! RFC] ;
ST7 OUT [IRFC]:
ST8 OUT [!ROY. RAS];
ST8 OUT [ RAS]:
ST9 OUT [!ROy];
ST9:
STO OUT [ MCI_. ROY.!RFC. RAS.IMSEL. CAS];
STIO OUT [ MCI_]:
9-19
CO
"~
..
C.
Co
-~
-<>1+/C2
(BANK)
'ALS6301 ONLY
c
DMUX
0
.-----_J"UI EN
~
14~
15~
(COL)
'\7 ~
18~
.~
..E
,....
CO
0-
V4
1-
V4
0
3-t-V4
~~ ~
-O}
r-
21~
1
10
G-
1501
13
RASIJ~I~-__. - ....------------------_+_t__lf_r_+_;__t__T--;__r......,G5
LE 1141
1131
AO
Al
A2
A3
~1
121
141
161
1
""7:-;:81::--_"-1
::~:
::
A6 1171
lOX
IROW)
H-O
1311
~
CAS DECODE
DMUX
EN
J'
....
All~
~
lOX
(COLUMN)
A 12 _1~7;-1____'1.1
A 13 ~1~9:-:1____'"
A14 1111
10
1
10
A15~1"""""'"r-1D
'------__1:--r_-1 2
:~~~
2
G6
3
G4
'--------_+--------_t--r_-t 1
13
0}6G*
1
110/20.417'\7
J.5!!, _ _ _
~~6~~~Y_ _ _
--c{:>- - - tTt---+---------------t
I
CASI J~
G4
G5
(BANK)
SEL 1 1261
~
0
1
~-----t----------T--1r-~~}5Z~
A16~
SELO~
~2
~3
C
0
.~
CO
.~
Q.
..
Co
10
t"'>"""""- 10
A19 1241
RASl
'2.
5·
H
Refresh with Scrubbing/Initialize. Refresh cycles are performed
using both the row and column counters to generate the
"0
addresses. MSEL selects the row or the column counter. All four
RAS outputs go low in response to RASI ('ALS630 1) or RASI
D)
r+
('ALS6302), while only one CASn output goes low in response
to CAST ('ALS6301) or CASI ('ALS6302). The bank counter keeps
en
track of which CAS output goes active. This mode can also be
o·
:::s
used during system power-up so that the memory can be written
:;
....
.3
with a known data pattern .
o
H
L
Read/Write. This mode is used to perform read/write cycles. Both
the row and column addresses are multiplexed to the address
D)
output lines using MSEL. SELO and SEL 1 are decoded to
r+
o·
determine which RASn and CASn outputs will be active.
:::s
H
H
Clear Refresh Counters. This mode clears the three refresh
counters (row, column, and bank) on the inactive transition of
RASI ('ALS6301) or RASI ('ALS6302), putting them at the
beginning of the refresh sequence. In this mode, all four RAS
outputs are driven low after the active edge of RASI ('ALS6301)
or RASI ('ALS6302) so that DRAM wake-up cycles can also be
performed.
In systems where addresses and data are both multiplexed onto a single bus, the
'ALS6301 and 'ALS6302 use latches (row, column and bank) to hold the address
information. The 22 input latches are transparent when the latch enable input (LE)
is high; the input data is latched whenever LE goes low. For systems in which the
processor has separate address and data buses, LE may be tied high.
The two 1O-bit counters in the 'ALS6301 and 'ALS6302 support 128, 256, and 512
line refresh operations. Transparent, burst, synchronous, or asynchronous refresh
modes are all possible as determined by the memory timing controller. The refresh
counters are advanced on the low-to-high transition of RASI on the 'ALS6301, and
on the high-to-Iow transition of RASI on the 'ALS6302. This is true in either refresh
mode. In the clear refresh counter mode, the refresh counters (row, column, and bank)
can be reset to zero on the low-to-high transition of RASI on the 'ALS6301 or on
the high-to-Iow transition of RASI on the 'ALS6302.
9-24
2.3.2
Typical Implementation
Figure 2-8 shows a system interface using the 'ALS6301 between a Motorola
68000L 10 and four banks of 1 M DRAMs. Addresses A21 and A22 are used to select
one of the four memory banks. Since members of the 68000 processor family have
separate address and data busses, the input latches on the 'ALS6301 are left
transparent by tying the latch enable (LE) input high. The CASO thru CAS3 outputs
of the 'ALS6301 are fed into the byte controller along with processor signals LDS
and UDS. The byte controller made from programmable logic allows the processor
to determine whether upper, lower or both bytes are accessed.
The RASI, CASI, MSEL and mode control (MCO, MC1) inputs on the 'ALS6301 must
be generated by the memory timing controller. The memory timing controller functions
as an arbitrator between refresh cycles and 68000L 10 access cycles. It also
guarantees that timing requirements of the DRAM will be met.
DYNAMIC
MEMORY
CONTROLLER
REFRESH
~
c
RFCM----------.
REFREQ
r--
p.
DYNAMIC RAMs
BANKO
o
'ALS6301
.~
I-
RESET!f-
..E
m
-
Lo....--
CLOCK
GENERATOR
~
TIMING
CONTROLLER
4
REFREO
OSCI-~ OSC
RFC
09- 00 1-_ _ _ _-r=0=-9--=.QO=___,
~ RESET
CLK
.
1
-- - - - - - i - - . t CLK
-i
CLK
A5
f-----MSEl f-----CAS
r-----.
A5
DTACK f - - DTACK
A23
vee:
-----t
A23
I
I
UCASl
I
A9-AO
.~
LCASl it-
I
UPPER
_~
CASi
1 MEG
----f A9-AO
- - t liAS2
-
I
.~
..
LOWER
Q.
~u
BYTE
C~R
UCASO
CASO~
CASl
~2
CAS3
r---r----.
r----
I
LCAS2
it-
LOWER
1 MEG ~ l6-BIT
'--- ---f A9-AO
r---r~UCAS3
H
I
BANK3
'-----++lliAS3
UCAS18
UCAS21--
Co
«
l6-BIT
I
UPPER
'--"""",
x
I
I
I
-t UCAS2
.... W
MCO
A20-All-'----------\l~~~~~ ~ :~~g~
W
UPPER BYTE
I
I
I
I
LCAS3it-
I LOWER
BYTE
UCAS3
LCASO~------i--~
r----- r----
LCAS1~---_1--~
r--~
LDSr------------------------------~
LCAS21------~----~
UDSr---------------------~
LCAS3~-----_1----~
R/W
U)
c
o
m
BANK2
MSEL
MCl ______ MCl
-f
RASl
~W
LE
A 2 l t - - - - - - - - - - - - + i SElO
An
-r'
-~
-~
RAS~ RASI
RST~"'"
68000Ll0
.5
1 MEG x l6-BIT
r-----
-
Figure 2-8. 'ALS6301, 'ALS6302 Timing Controller Interface
9-25
2.3.3
Timing Controller Details
Figure 2-9 is a timing diagram for a typical 6800011 0 access cycle. The 'AlS6301
control signals required to execute the access cycle are also shown. Control signals
for the 'AlS6301 are referenced from the OSC output of the 8284A clock generator.
OSC runs at 2 times the speed of the system clock, that is ClK = 10 MHz and
OSC = 20 MHz. By running the timing controller at a higher speed than the system
clock, the system performance is improved. A programmable logic sequencer, the
TIB82S167B, was programmed for use as the timing controller.
In this example, refresh requests (REFREQ) are generated every 155 clock cycles.
The timing controller will perform the refresh cycle (RAS only) immediately if the
processor is not in the middle of an access cycle. If the controller is in the middle
of an access cycle, the refresh cycle will be delayed until the access cycle is complete.
If the controller is asked to perform an access cycle during a refresh, the access cycle
will begin immediately after the refresh cycle is completed. Address bit A23 indicates
whether the access requested is a memory access (A23 = l) or an t/O access
(A23 = H). The timing controller will perform an access cycle only if Address bit A23
is low. Figure 2-10 is a timing diagram of the refresh/access cycle as explained above.
To implement memory scrubbing, the controller must execute a read/write cycle during
the refresh cycle and then place the 'AlS6301 in the memory scrubbing mode. (This
example executes a RAS only refresh.) The flowchart in Figure 2-11 outlines the
required functionality of the timing controller. This flowchart was used along with
the timing diagrams in Figures 2-9 and 2-10 to design the timing controller.
l>
"2-
'C
n'
I»
.....
0'
::s
tn
so
:;a'
...
3
I»
S2
ClK
J/
AS'~ ____________
.....
\~
______________________~_______
ADX ____________~---J~
0'
::s
~
VALID ADRESS
7
R/W
~Ia(cl~
[ DATA
:
(
READ DATA
>-
I
i
ADX ________________~--..J>---<~--------------V-A~ll-D-AD-D-R-ES-S----------------
[
R/W ________________
~--\~--------------------~---------------------
DATA----------------tl--------------------~c:~====~VA~l~ID~W~R~IT~E~DA~T~A========
I
OSC
STO
STO
:tST14
ST15
*ST16
ST17
ST19
ST20
STO STATE
\~------~----------~;-MSEL __________________________________~/
'-""I.-______--J1
\~
________________..J;__
MC1-H. RFC-L
tStart sequence when AS = H, elK = H, REFREQ = H, STATE = 0
:l:Return to STO if A23 is high
Figure 2-9. 68000 Access Cycle
9-26
~
~14
REFRESH CYCLE
.J
W
SO
ClK
AS. lOS.
UDS
~I
~I
~
ADX
R/iN
ADDRESS VALID
X
ADDRESS VALID
/
X
ADDRESS VALID
/
X
ADDRESS VALID
/
DATA
ADX
R/iN
MCI
REQ§
RFC
(
ADDRESS VALlD:X ADDRESS VALID
~
X
ADDRESS VALID
~
x:
ADDRESS VALID
~
\
'~
>
READ DATA
I
__
~
___ ~ ___')..._.).
I
RAS ---------~\
I
===
___________________
I
\
I
I
\_____
~'-
====:::::
MSEl _ _ _ _ _ _ _ _ _ _ _ _ _ _
CAS
=========---------------~\
\
DTACK
t Start sequence when REFREO = l. STATE = 0
i Return to STATE 0 if REO = H or A23 =H
§ REO is internal status register used to store an access request during a refresh cycle. (If AS
= H during refresh cycle ST1-ST5)
Figure 2-10. Refresh/Access Cycle
co
N
"'-l
I
Applications Information
I
I
INITIALIZE
(RESET - LI
STO
MC1 - H
RAS - H
DTACK - H
MSEL - L
RFC - L
CAS -
H
REFRESH CYCLE
ST1 THRU ST6
(FIGURE 2-101
NOTE:
IF AS-H
THEN
REQ-L
..
ACCESS CYCLE
IF RESET - L
THEN
INITIALIZE
ST14 THRU
ST20
(FIGURE 2-91
NOTE:
IF RESET - L
THEN
INITIALIZE
ACCESS CYCLE
(FIGURE 2-101
ST7 THRU ST13
Figure 2-11. 'ALS6301, 'ALS6302 Memory Timing Controller Flow Chart
9-28
2.3.4
Refresh Timer Details
Figure 2-12 shows the actual circuit implementation of the refresh and memory timing
controller. The refresh timer signals the controller whenever it is time to execute a
refresh cycle. As required by memory, every row (512 on the TMS4C1025 DRAM)
must be addressed every 8 ms. This implies that one row should be refreshed at least
once every 15.6 ms. With a 10-MHz system clock, the refresh timer should use
approximately a division factor of 155. This results in a refresh request every 15.3 ms.
The refresh complete input (RFC) is used to signal the refresh timer that the refresh
has been completed. It is important that the timer not stop so that the 8 ms memory
requirement is maintained.
The TIBPAL22V1 0 circuit shown in Figure 2-12 is used to generate the refresh request
signal every 155 clock cycles. The refresh request signal (active low) will remain active
(low) until a refresh complete (RFC) signal is received from the timing controller. During
a system reset, the refresh request output is set to a high logic level. W~en using
different clock rates or memory sizes, the division circuit in the refresh timer should
be adjusted accordingly.
TIMING CONTROllER
c
o
.~
.E
CO
o
r-----------------------------~(-3~)MRESET
\t-
.5
en
c
TIB82S167B
REFRESH TIMER
o
(2)
.~
CO
RESET
RFC
REFREQ
(3)
M-:..;;;.;..------------~~
.~
c..
c.
RFC
(22)
'2.
'C
n'
...m
S'
::::s
en
As seen in Figures 2-9, 2-10, and 2-11, a state, STO-ST30, has been assigned to
each clock cycle. The appended ABELTM and CUPLTM files can be easily understood
by comparing the state equations to the states shown in these figures. Since the only
difference between the 'ALS6301 and the 'ALS6302 is that the RASI and the CASI
inputs are active-high instead of active-low, a slight modification to the timing
controller software file will allow an 'ALS6302 to be used instead of an 'ALS6301.
The TIBPAL22V10 refresh timer and the TIBPAL 16L8 byte controller designs are
straight forward and easily achieved as can be seen in the appended files .
:;
...d'
3
...S'm
..
::::s
In applications with different systems timings, the ABELTM and CUPLTM files can be
modified to fit the processor requirements. A preprogrammed sample of the timing
controller, refresh timer and byte controller can be obtained by calling LSI/PAL/PROM
Applications, 214/995-2980. If a basic understanding of programmable logic is
needed, see the Texas Instruments Field Programmable Logic Applications note.
2.3.6
Summary
The 'ALS6301 and 'ALS6302, coupled with programmable logic, offer the system
designer a solution to high speed dynamic memory requirements. Programmable logic
allows the designer to tailor the timing controller to a selected processor and memory.
In many cases, the generation of a high speed timing controller from programmable
logic will allow the designer to use slower DRAMs without affecting system speed.
This results in lower total system cost because of the large number of memory devices
used.
9-30
2.3.7
ABELTM Files
module DMC S167
module DHC_SI67 flag '-KY','-R2' "leave unused OR terms connected
title 'DYNAHIC HEHORY CONTROLLER FOR THE ALS6301 APPLICATION
Loren Schiele Texas Instruments, August 15, 1986'
DHC
device 'F82S167';
" Input pin assignments
OSC
REFREQ
RESET
CLK
AS
A23
GND
pin
pin
pin
pin
pin
pin
pin
I;
2;
3;
4;
5;
6;
16;
" OSCILLATOR
" REFRESH REQUEST
RESET - INITIALIZES WHEN LOW
OSC DIVIDED BY 2
" ADDRESS STROBE
" HOST SIGNIFICANT ADDRESS BIT
" PIN 16 HUST BE TIED LOW
It
It
c:
o
as
'';::'
" Output pin and node assignments
HCI
HSEL
CAS
RAS
DTACK
RFC
pin
pin
pin
pin
pin
pin
9;
10;
II;
13;
14;
15;
HCI_R
HSEL_R
CAS_R
RAS_R
DTACK_R
RFC_R
node
node
node
node
node
node
25;
26;
27;
28;
29;
30;
...oE
" HODE CONTROL
" HULTIPLEXER SELECT
COLUHN ADDRESS STROBE
ROW ADDRESS STROBE
" DATA ACKNOWLEDGE
REFRESH COHPLETE
'too
.5
U)
c:
It
It
o
'';::'
It
as
,~
" Internal status and counter nodes
PO
PI
P2
P3
P4
REQ
node
node
node
node
node
node
36;
35;
34;
33;
32;
31 ;
PO_R
PI R
P2~)
P3_R
P4_R
RECLR
node
node
node
node
node
node
42;
41;
40;
39;
38;
37;
Q.
c.
INTERNAL COUNTER REGISTER
" INTERNAL COUNTER REGISTER
It
INTERNAL COUNTER REGISTER
It
INTERNAL COUNTER REGISTER
" INTERNAL COUNTER REGISTER
" REFRESH REQUEST STATUS REGISTER
It
""2-c;"
State 4:
o·
State 5:
II)
....
::s
o
S'"
.
3
case
!REfREQ
REfREQ
REFREQ
endcase;
MCI
REQ_
case
RFC RAS
REQ_
case
REQ_
case
RFC
REQ_
case
RAS
REQ_
case
..-
..-
.-
.....-
" NEXT
" STATE
&
&
&
RESET
AS & CLK & RESET
(!AS # ICLK)
low & RESET;
low & (AS & RESET);
RESET==l
high & RESET;
low & RESET;
low & (AS & RESET);
RESET==l
low & (AS & RESET) ;
RESET==1
low & RESET;
low & (AS & RESET);
RESET==1
high;
low & (AS & RESET);
RESET == 1
" DETERMINE If ACCESS HAS BEEN REQUESTED
State 6:
REQ_ := high & A23;
MCl_ := high & RESET;
case
REQ # A23
!A23 & !REQ & RESET
endcase;
o"""
....
o·
..
II)
::s
" ACCESS AfTER REfRESH
State 7:
0;
2; endcase;
3; endcase;
4; endcase;
5; endcase;
6; endcase;
0;
7;
State 10:
low & RESET;
RESET==l
high & RESET;
high & RESET;
RESET==l
low & RESET;
low & RESET;
RESET==l
RESET==l
:10; endcase;
:11; endcase;
State 11:
case
RESET==1
:12; endcase;
State 12:
case
RESET==l
:13; endcase;
State 13:
RAS_ .HSEL CAS_ .DTACK case
high;
low;
high;
high;
RESET==l
0; endcase;
State 9:
9-32
:14;
:
RAS_
case
REQ_ .MSEL- .case
CAS
DTACK- .case
case
State B:
@page
.-
: 1;
.-
..-
8; endcase;
9; endcase;
" ACCESS TIHING CYCLE
State 14:
State 15:
State 16:
State 17:
State 18:
State 19:
State 20:
equations
enable HCI = I;
case
RAS - .case A23
IA23
endease;
HSEL .DTACK_:=
case
CAS - .case
case
case·
RAS
.HSEL- .CAS
.DTACK- .case
RESET==I
low & IA23 & RESET;
-- I
& RESET
high & RESET;
low & RESET;
RESET==I
low & RESET;
RESET==I
RESET==I
RESET==I
high;
low;
high;
high;
RESET==I
: 15; endease;
: 0;
: 16;
: 17; endease;
: 18; endease;
: 19; endease;
:20; endease;
0; endease;
C
0
"always enabled. pin 19 Is preset
.~
.
ca
" INITIALIZATION WHEN RESET IS LOW
( HCI.RAS.OTACK.REQ,CAS]
.[ PO_R,PI_R,P2_R,P3_R,P4_R,HSEL_R,RFC_R] :=
E
IRESET;
!RESET;
0
'to-
.5
test_vectors ' REFRESH WITH ACCESS FOLLOWING'
([GND,OSC,RESET,REFREQ,CLK.AS.A23]
0 .elk. 0
X
X • X. X ]
0 .elk. I
0
X , X. X ]
0 .elk. I
X
X
I. X ]
0 .elk. I
X
X • X. X ]
0 ,elk. I
X
X • X. X ]
0 ,elk,
X
X , X, X ]
0 ,elk,
X
X X, X ]
0 ,elk,
X
X X, o ]
0 ,elk,
X
X , X, X ]
0 ,elk,
X
X X, X ]
0 ,elk,
X
X , X, X ]
0 .elk.
X
X • X. X ]
0 .elk.
X
X X. X ]
0 .elk,
X
X • X. X ]
0 .elk.
X
X X. X ]
0 .elk.
0, X ]
0
0 .elk.
I, X ]
0
0 .elk,
I • O. X ]
-)
-)
-)
-)
-)
-)
-)
-)
-)
-)
-)
-)
-)
-)
-)
-)
-)
-)
-)
tn
C
[HCI.HSEL.CAS,RAS.DTACK.RFC.REQ.Cnt])
H
H
L H H
L H 0 ];
H
L H H
H
L H I ];
L
H
L H H
L L 2 ];
H
L
L H L
H L 3 ];
L
H
H L 4 ];
L H L
L
H
L H L
L L 5 ];
L
H
L H H
L L 6 ];
H
H
L H H
L L 7 ];
H
H
L H L
L L 8 ];
H
H H L
H
L H 9 ];
H
H L L
L
L H ,10 ] ;
H
H L L
L
L H .11 ];
H
L
H L • L
L H .12 ];
H
H L L
L
L H .13 ] ;
H • L H 0 ];
H
L H• H
H
H • L H 0 ];
L • H• H
H
H • L H 0 ];
L H, H
H
H , L H 0 ];
L • H, H
0
.~
ca
.~
C.
Co
<2:
test_veetors ' REFRESH WITHOUT ACCESS FOLLOWING'
([GND,OSC,RESET.REFREQ.CLK.AS.A23]
[ 0 .elk. 0
X
X • X. X
[ 0 ,elk.
I
X X. X
0
[ 0 .elk, I
X
X 0, X
[ 0 ,elk,
0, X
I
X
X
[ 0 ,elk,
I
0, X
X
X
[ 0 ,elk, I
0, X
X
X
[ 0 ,elk,
I
X
X , X, X
[ 0 ,el k,
I
X
0, X
X
[ o ,elk,
0, X
I
0
X
@page
-)
-)
-)
-)
-)
-)
-)
-)
-)
-)
[HCI,HSEL.CAS,RAS.DTACK.RFC.REQ.Cnt])
H
H
L H H
L H 0 ];
H
L H H , H
L H I ];
L
L H H, H
L H 2 ];
L
H
H 3 ];
L H L , H
,
L
H
H 4 );
L H L
H
,
H
,
L
,
,
L
L
H
L
H 5 ];
L
L , H , H , H , L H 6 );
H
L , H , H , H , L H 0 ];
H, L , H, H, H , L H
I ];
9-33
test_vectors
REFRESH WITH ACCESS REQUEST BUT DATA NOT IN DRAM (A23=H) ,
([GND,OSC,RESET,REFREQ,CLK,AS,A23]
0 ,elk, 0
X
X X, X ]
0 ,elk, 1
0
X X, X ]
0 ,elk, 1
X
X 1, X ]
0 .elk, 1
X
X 0, X ]
0 ,elk, 1
X
X 0, X ]
0 ,elk. 1
X
X 0, X ]
0 .elk, 1
X
X 0, X ]
0 ,elk, 1
X
X 0, I ]
0 ,elk, I
I
0 0, X ]
-)
-)
-)
-)
-)
-)
-)
-)
-)
-)
[MCI,HSEL,CAS,RAS,DTACK,RFC,REQ,Cnt]}
[ H
L H H
H
L H 0 ];
[ H
L H H
H
L H 1 ];
[ L
L H H • H
L L 2 ];
[ L
L H• L , H
H L 3 ];
[ L
L H, L • H
H L 4 ];
[ L
L H, L , H
L L 5 ];
[ L
L H• H, H
L L 6 ];
[ H
L H, H, H
L H 0 ];
[ H
L H• H, H
L H 0 ];
test_vectors ' ACCESS TIMING CYCLE '
l>
"C
"25'
,..CI)
0'
:::::s
en
....S'
.3
0
,..CI)
..
0'
:::::s
([GND,OSC,RESET,REFREQ,CLK,AS,A23] -) [MCl,HSEL.CAS,RAS,DTACK,RFC,REQ,Cnt]}
0 ,elk, 0
X
X , X, X ] - ) [ H
L H H
H
L H , 0 ];
0 ,elk, 1
1
1 1, X ] - ) [ H
L H H
H
L H ,14 ] ;
0 ,elk, I
X
X , X, X ] - ) [ H
L H H
H
L H ,15 ] ;
0 .elk, 1
X
X X, o ] - ) [ H
L H L
H
L H ,16 ] ;
0 ,elk, 1
X
X , X, X ] - ) [ H
H H L
L
L H ,17 ] ;
0 ,elk, 1
X
X , X, X ] - ) [ H
H L L
L
L H ,18 ] ;
0 .elk, 1
X
X , X, X ] - ) [ H
H L L
L
L H ,19 ] ;
0 ,elk, 1
X
X , X, X ] - ) [ H
H L L
L
L H ,20 ] ;
0 ,elk, 1
X
X , X, X ] - ) [ H
L H H
H
L H, 0 ];
0 ,elk, 1
1
0 , 0, X ] - ) [ H
L H H
H
L H , 0 ];
test_vectors ' ACCESS TIMING CYCLE BUT DATA NOT IN DRAM (A23=H) ,
([GND,OSC,RESET,REFREQ,CLK,AS,A23]
[ 0 ,elk, 0
X , X , X, X ]
[ 0 ,elk, 1
1 , 1 , 1, X ]
[ 0 ,elk, 1
X , X , X, X ]
[ 0 ,elk, 1
X , X , X, 1 ]
[ 0 ,elk, 1
1 , 0 , 0, X ]
-)
-)
-)
-)
-)
-)
[HCl,MSEL,CAS,RAS,DTACK,RFC,REQ,Cnt])
[ H • L , H • H , H , L , H , 0 ];
[ H • L , H , H , H , L , H ,14 ];
[ H , L , H , H , H , L , H ,15 ];
[ H , L , H , H , H , L , H , 0 ];
[ H, L , H, H, H , L , H, 0 ];
test_vectors ' RESET DURING ACCESS TIMING CYCLE '
([GND,OSC.RESET,REFREQ,CLK,AS,A23]
[ 0 ,elk, 0
X , X , X, X ]
[ 0 ,elk, 1
1 , 1 , I, X ]
[ 0 ,elk, 1
X , X , X, X ]
[ 0 ,elk, 1
X , X , X. o ]
[ 0 ,elk, 1
X , X , X, X ]
[ 0 ,elk, 1
X , X , X, X ]
[ 0 ,elk, 0
X , X , X, X ]
[ 0 ,elk, 0
X , X , X, X ]
end DHC_SI67
9-34
-)
-)
-)
-)
-)
-)
-)
-)
-)
[MCl,HSEL,CAS,RAS,DTACK,RFC,REQ,Cnt]}
H
L H H
H
L H, 0 ];
H
L H H
H
L H ,14 ] ;
H
L H H
H
L H ,15 ] ;
H
L H L
H
L
H ,16 ] ;
H
H H L
L
L
H ,17 ] ;
H L L
H
L
L H ,18 ] ;
H
L
H H
H
L
H, 0 ];
H
L
H H
H
L
H , 0 ];
module TIMER154
module TIHERI54 flag '-r2','-f'
title 'REFRESH TIMER
LOREN SCHIELE TEXAS I NSTRUHENTS , DALLAS, 08/15/86'
T154
DEVICE
'P22VI0';
"Input declarations
CLK
RESET
RFC
pin 1;
pin 2;
pin 3;
" SYSTEM CLOCK
" RESETS WHEN LOW
" REFRESH COMPLETE
"output declarations
QO,Ql,Q2,Q3
Q4,Q5,Q6,Q7
REFREQ_
pin 14,15,16,17;
pin 18,19,20,21;
pin 22;
"
"
"
COUNTER STATES
COUNTER STATES
REFRESH REQUEST - ACTIVE LOW
c
o
"';:::;
.E
CO
"intermediate variables
o
'too
CNT_ 154SCLR
count
C,H,L,X
.5
!QO & Ql & !Q2 & Q3 & Q4 & !Q5 & !Q6 & Q7;
!RESET # CNT_154_;
[Q7,Q6,Q5,Q4,Q3,Q2,Ql,QO];
.C., 1,0, .X.;
en
c
o
"';:::;
CO
"~
equations
REFREQ_
QO
Ql
Q2
Q3
Q4
Q5
Q6
Q7
C.
Co
.........-
test_vectors
@CONST cnt = 1;
@REPEAT 154 (
@CONST cnt = cnt + 1; }
@CONST cnt
@REPEAT 20
@CONST cnt
GND,~3,OSC,~3,RESET,~6,REFREQ,~4,CLK,~3,AS,~2,A23_,~6,
HCI _,~4,HSEL,~3,CAS,~3,RAS,~4,DTACK,~4,RFC,~4,REQ;
'C
'2.
VECTORS:
$msg" REFRESH WITH ACCESS FOLLOWING";
".
$msg"
$msg"
------------ INPUT ------------- -------- OUTPUT ---------- ACCESS";
$msg"
GND OSC RESET REFREQ CLK AS A23
HCI HSEL CAS RAS DTACK RFC REQ";
$msg"
--------------------------------------------------------------------,.;
H
I·RESET·I 0 C
0
X
H
L
X X X
H
L H H
H
/* STO* I 0 C
I
0
X X X
H
H
L
L H H
H
L
I· STI*I 0 C
I
X
X I X
L H H
L
L
H
H
L
/* ST2· I 0 C
I
X
X X X
L
L H L
H
H
L
X
1* sn·1 0 C
I
X X X
L
L H L
H
L
L
X
X
/* ST4*1 0 C
X X
L
L H L
I
H
/* STS· I 0
C
I
X
X X X
L
L
L
L H H
H
L
/* ST6· I 0
C
X
X X 0
H
L H H
L
I
L
H
L
1* ST7· I 0 C
I
X
X X X
H
L H L
H
/* ST8· I 0 C
I
X
X X X
H
H H L
H
L
H
I
X
X X X
H
H L L
L
L
I· ST9·1 0 C
H
/*STIO·I 0 C
I
X
X X X
H
H L L
L
L
H
/*STI I· I 0 C
X
X X X
H
H L L
L
L
I
L
H
X
/* STI 2· I 0 C
X X X
H
H L L
L
I
H
/*STI3·1 0
X
X X X
H
L
C
I
H
L H H
H
/*STO ·1 0
C
I
0 0 X
H
L H H
H
L
H
H
H
/*STO ·1 0 C
I
0
I X
H
L H
L
H
I
I
0 X
H
H
L
L H H
/*STO • I 0 C
C:;"
.
,...
Q)
0"
:::::I
en
.3S""""
0
Q)
,...
..
0"
:::::I
.
".
$msg"
$msg"
";
$msg"REFRESH WITHOUT ACCESS FOLLOWING";
".,
$msg"
$msg"
------------ INPUT -------------------- OUTPUT ---------- ACCESS"
$msg"
GND OSC RESET REFREQ CLK AS A23
MCI HSEL CAS RAS DTACK RFC REQ
$msg"
--------------------------------------------------------------------"
H
H
X
X X X
H
L
H H
L
/*RESET· I 0 C
0
H
0
H
L
X X X
H
/* STO· I 0 C
I
L H H
H
I
X
X 0 X
L H H
H
L
I· STI·I 0 C
L
/* ST2· I 0
X
X 0 X
H
H
H
C
I
L
L H L
X 0 X
H
I· sn·1 0 C
I
X
L
L H L
H
H
I
X
X 0 X
H
H
/* 5T4·1 0
C
L
L H L
L
H
H
X
X
X
H
H
I
0
L
L
L
I· STS·I 0 C
X
X X 0
H
H
/* ST6· I 0 C
I
H
L H H
L
I
X
X 0 X
H
L H H
H
L
H
I· 5TO·I 0 C
9-38
$msg"
";
$msg"
$msg"REfRESH WITH ACCESS REQUEST BUT DATA NOT IN DRAM (A23=H)";
"
$msg"
$msg"
------------ INPUT ------------- -------- OUTPUT ---------- ACCESS"
$msg"
GND OSC RESET REfREQ ClK AS A23
MCI MSEl CAS RAS DTACK RfC REQ "
$msg"
--------------------------------------------------------------------"
/-RESET-/ 0
C
0
X
X
X X
H
l
H H
H
l
H
C
I
r STO-/ 0
X
0
X X
H
l
H H
H
l
H
/- STI- / 0 C
I
X
X
I X
l
l
H H
H
l
l
C
I
r ST2-/ 0
X
X
0 X
l
l
H l
H
H
l
r s13-/ 0
C
I
X
X
0 X
l
l
H l
H
H
l
C
X
I
X
r S14-/ 0
0 X
l
l
H l
H
l
l
r STS- / 0
C
I
X
X
0 X
l
l
H
H
H
L
l
c
I
X
r ST6-/ 0
X
0 I
H
L
H H
H
H
L
/- STO-/ 0
C
I
I
0
0 X
H
H
H
l
H
l
H
$msg"
";
$msg"
".
$msg"ACCESS TIMING CYCLE ";
$msg"
";
$msg"
------------ INPUT ------------- -------- OUTPUT ---------- ACCESS"
$msg"
GND OSC RESET REfREQ ClK AS A23
MCI MSEl CAS RAS DTACK RfC REQ "
$msg"
--------------------------------------------------------------------"
/-RESET-/ 0
C
0
X
X
X X
H
l
H
H
H
l
H
rSTO -/ 0
C
I
I
I
I X
H
l
H H
H
l
H
/-STl4- / 0 C
I
X
X
X X
H
l
H
H
H
l
H
rSTIs-/ 0 C
I
X
X
X 0
H
l
H l
H
l
H
rSTl6- / 0
C
1
X
X
X 'X
H
H
H
l
l
H
l
rST17-/ 0 C
1
X
X
X X
H
H
l
l
l
l
H
rSTIs-/ 0
C
1
X
X
X X
H
H
l
l
l
l
H
rSTl9-/ 0
C
1
X
X
X X
H
H l
l
l
H
l
/-ST20-/ 0
C
1
X
X
X X
H
H
l
H
H
l
H
rSTO -/ 0
C
I
0
I
0 X
H
H H
l
H
l
H
$msg"
";
It;
$msg"
$msg"ACCESS TIMING CYCLE BUT DATA NOT IN DRAM (A23=H)";
$msg"
";
$msg"
------------ INPUT ------------- -------- OUTPUT ---------- ACCESS"
$msg"
GND OSC RESET REFREQ ClK AS A23
MCI MSEl CAS RAS DTACK RFC REQ "
- - - - - - - - - - - - - - - - - - - - - - - _____________________________________________ tt
$msg"
rSTO -/ 0
C
I
I
I X
H
l
H H
H
l
H
rSTl4-/ 0
C
X
X
X X
H
l
H
H
H
L
H
/-STlS- / 0 C
X
X
X I
H
H
H
l
H
l
H
rSTO -/ 0 C
I
0
0 X
H
l
H H
H
l
H
It.
0
.
0
0
C
0
"+=
CO
.E
0
'too
.5
U)
C
0
+=
CO
"~
..
C.
C.
"2-
"C
< 0.5T + 0.25T - tCHSl
< 0.5(125) + 0.25(125) - 60
< 33.75
It should be noted that all of the following equations take into account the 90 degree
phase shift. At lower clock frequencies, such as 6 MHz, the AS signal can be directly
connected to the THCT45028 and the phase shift circuits are not required.
c:r
D)
"'
0'
:::s
o
S"
....
o
3
D)
2.4.3
DRAM Refresh Time
The refresh clock frequency is controlled by the strap input pins (TWST, FS 1, and
FSO) on the THCT45028. Table 2-3 shows the strap configuration for the
THCT45028. At 8 MHz, with no wait states, setting TWST low, FS1 high, and FSO
high yields a refresh rate of 11.375 p.s/row. The TMS4256/4257 requires that each
of the 256 rows be refreshed at least once every 4 ms. With a refresh rate of
11.375 p.s/row, the time required to refresh all 256 rows will be 2.9 ms. This easily
satisfies the 4-ms refresh requirement .
..
..
"'
0'
:::s
Table 2-3. Refresh Clock Frequency Input Pin Strap Configuration
-._-
--
---
WAIT
STRAP INPUT MODES
STATES
MINIMUM
FOR
CLOCK
REFRESH
CYCLES
CLOCK
MEMORY
REFRESH
FREQUENCY
FREQUENCY
FOR EACH
TWST
FS1
FSO
ACCESS
RATE
(MHz)
(kHz)
REFRESH
l
l
l
l
l
l
lt
0
EXTERNAL
REFREQ
H
0
0
0
EXTERNAL
-
elK -;elK -;-
4
3
3
4
1
1
1
1
elK
elK
elK
elK
H
l
H
H
H
l
l
H
H
H
l
H
H
H
H
l
61
91
3.904
5.824
-;- 61
-;- 91
-;- 106
-;- 121
3.904
5_824
6.784
7.744
REFREQ
64-95~
64-88§
64-95~
64-75~
64-73~
64-83'
3
4
4
4
t This strap configuration resets the Refresh Timer Circuitry.
:I: Upper figure in refresh frequency is the frequency that is produced if the minimum clock frequency of the next select state is used.
§ Refresh frequency if clock frequency is 8 MHz.
, Refresh frequency if clock frequency is 10 MHz.
9-44
2.4.4
DRAM Precharge Time
The precharge time is the time required between access cycles to allow internal nodes
on the DRAM to charge to their correct reference levels. This is specified on the DRAM
data sheet as tw(RH) min. As with most DRAMs, there is a choice of performance
ranges. For the TMS4256/4257, tw(RH) ranges from 100 ns on the -12 device to
120 ns on the - 20 device.
When using the THCT45028, there are three precharge conditions which can occur
during normal operation. Each condition must be checked to be sure the precharge
condition is met. The following equations check these three conditions.
1. Access-to-Access cycle
tw(RH)
tw(RH)
tw(RH)
< tSH - tAEH-REH - tt(REH) + tAEL-REL
< 150 - 35 - 30 + 35
< 120
2. Access-to-Refresh cycle
tw(RH) < 1.5T + 0.25T + tCH-RRL - tCLSH - tAEH-REH - tt(REH)
tw(RH) < 1.5(125) + 0.25(125) + 50 - 70 - 35 - 30
tw(RH) h 133.75
3. Refresh-to-Access cycle
tw(RH)
tw(RH)
tw(RH)
c
o
i
.E
~
< T - tCH-RRH - tt(REH) + tCH-REL
< 125 - 30 - 30 + 45
< 110
.5
en
c
When the listed equations are correct, the THCT45028 guarantees the precharge
condition for either the - 12 or - 1 5 TMS4256/4257 DRAMs.
...cao
Row Address Setup and Hold Time
To meet the row address setup-time requirement, the address must be present at
the RAO-RA8 and CAO-CA8 inputs to the THCT45028 for at least 10 ns (tAV-AELl
before ALE goes low. The row address setup time from the MC68000L8 is defined
by the tAVSL specification. At 8 MHz, tAVSL is 30 ns minimum. This meets the
THCT45028 specification. The row address setup time to the DRAM must also be
satisfied. For the TMS4256/4257, tsu(RA) is specified as O-ns minimum. The following
equation applies:
C.
Co
'E..
5·
....m
'C
Read Access Time from CAS
When the microprocessor tries to read data from memory, the Read-Access-Time
guarantees that data is available. When using the THCT45028, there are two possible
access situations. The most common is the normal access cycle. Another possible
access situation is the access-grant cycle. The access-grant cycle occurs when an
access cycle immediately follows a refresh cycle.
For the TMS4256/4257, access from CAS is specified as ta(C). When using the
TMS4256/4257, three speed types are available for selection. The three speed types
are as follows:
o·
:s
(I)
Speed type - 12
Speed type - 15
Speed type - 20
:r
....
o
..
ta(CA)
ta(CA)
ta(CA)
60 ns
75 ns
100 ns
The following equations apply to the circuit shown in Figure 2-14 .
3
m
1. Normal Access Cycles
....
..
o·
ta(C)
ta(C)
ta(C)
:s
<
<
<
2.5T - tCHSL - tAEL-CEL - tt(CEL) - tp(OR) - tDICL
2.5(125) - 60 - 115 - 20 - 15 - 15
87.5
2. Access Grant Cycles
ta(C)
ta(C)
ta(C)
<
<
<
2.5T - 0.25T - tCH-CEL - tt(CEl) - tp(OR) - tDICL
2.5(125) - 0.25(125) - 140 - 20 - 15 - 15
91.25
As shown by the equations, the only speed type that does not meet the access time
requirement is the - 20 device. The - 12 and -15 devices both meet ta(C).
2.4.8
Other Considerations
The DT ACK input on the MC68000L8 informs the microprocessor that data is
available. Wait states are inserted by holding DT ACK high. This process for the accessgrant cycle is illustrated in Figure 2-15. If an access request occurs during a refresh
cycle, the THCT45028 completes the refresh cycle, then finishes the access request.
In this situation, the DTACK signal is held high until data is available. The AS74 flipflop shown in Figure 2-13 is used to time the DT ACK signal in relationship to the falling
edge of S6.
On normal accesses, the ROY signal is high allowing either UDS, LOS or Rlw to force
DTACK low. During write cycles, R/W will force DTACK low. During read cycles, UDS
and/or LOS will force DTACK low. During access-grant cycles, the low ROY signal
holds DT ACK high until it is released.
9-46
2.4.9
Summary
This application report provides an example of how to interface the THCT4502B with
the MC68000L8. The major design criteria has been calculated and checked against
typical DRAM specifications. When using processor speeds lower than 8 MHz, the
interface is simplified further because it is not necessary to shift the THCT4502B input
clock frequencies. Additional design ideas can be obtained from an Applications Brief
"TMS4500B/MC68000 INTERFACE", Texas Instruments publication SMCA008.
2.5
2.5.1
Programmer and Software Manufacturers Addresses t
Programmer Manufacturers Addresses
ECI Semiconductor
975 Comstock St.
Santa Clara, CA 95054
(408) 727-6562
Structured Design
988 Bryant Way
Sunnyvale, CA 94087
(408) 988-0725
c:
o
ca
.';:=
DATA I/O
10525 Willows Rd. NE
Redmond, WA 98073-9746
(206) 881-6444
Sunrise Electronics
524 S. Vermont Avenue
Glendora, CA 9.1740
(818) 914-1926
DIGITAL MEDIA
11770 Warner Ave. Suite 225
Fountain Valley, CA 92708
(714) 751-1373
Valley Data Sciences
2426 Charleston Rd.
Mountain View, CA 94043
(415) 968-2900
Kontron Electronics
1230 Charleston Rd.
Mountain View, CA 94039-7230
(415) 965-7020
Varix
1210 Campbell Rd. Suite 100
Richardson, TX 75081
(214) 437-0777
Stag Micro Systems
528-5 Weddell Drive
Sunnyvale, CA 94089
(408) 745-1991
Digelec
1602 Lawerence Ave. Suite 113
Ocean, NJ 07712
(201) 493-2420
...oE
'too
.5
en
c:
o
.';:=
ca
Storey Systems
3201 N. Hwy 67, Suite E
Mesquite, TX 75150
(214) 270-4135
9-47
.2
C.
Co
-
'C
'2.
r;'
...0'
D)
::I
en
S"
.3
0'
...0'
..
D)
::I
9-48
3
Cache Memory Systems
3.1
Introduction
As the typical operating speeds of processors have increased to provide for the ever
increasing need for computing power, the necessity of developing a memory hierarchy
(the incorporation of two or more memory technologies in the same system) has
become apparent. One of these memory technologies is selected on the basis of fast
access time (with associated high cost per bit) to allow minimum system cycle time.
The other technologies are chosen with the lowest possible cost per bit relative to
speed in order to achieve the maximum system memory capacity. In a system with
a multiple level hierarchy, the speed-to-cost relationship depends upon the frequency
of access and the total memory requirement at that level. By proper use of this
hierarchy through coordination of hardware, system software, and in some cases user
software, the overall memory system will reflect the characteristics that approximate
the fast access time of the fast memory technology and the low cost per bit of the
low cost memory technology. Large computer systems have made use of this memory
optimization technique to maintain very large data bases and high throughput (see
Figure 3-1). Many smaller processor systems use this technique to allow mass storage
of data, where a tape or a disk is the low-cost memory and Random Access Memory
(RAM) is the fast memory technology.
Because of the increase in processor speeds, memory hierarchy is now extending to
the RAM memory used in microcomputer systems. Typically, Dynamic RAM (DRAM)
is used as the bulk or main memory and High-Speed Static RAM (HSS) serves as the
fast-access memory. This HSS RAM is usually 1K to 8K words deep and serves as
a fast buffer memory between the processor and the main memory. This small fast
buffer memory is called "cache" memory because it is the storage location for a
carefully selected portion of the data from the main memory. The addresses for that
portion of memory currently in the buffer memory is saved in the cache tag RAM (a
small memory that is used to store the addresses of the data that has been mapped
to cache).
11oiII4------RELATIVE MEMORY SIZE-------.t.1
ARCHIVAL STORAGE
(MAGNETIC TAPE)
BULK STORAGE
(DISK)
INCREASING
COST PER BIT
INCREASING
ACCESS TIME
Figure 3-1. Memory Size vs Access Time and Cost Per Bit
9-49
c
o
.~
CO
...oE
'too
.5
en
c
o
;
CO
.~
C.
c.
The Cache Address Comparators were designed to reduce this cache access
degradation to a minimum by incorporating the matching logic on-chip. This provides
match-recognition times that are compatible to the access time of the cache-buffer
memory.
'C
'E..
n·
...ci"
0)
::J
en
\
L
'I
S"
....
o...
3
0)
DATA BUS
'\
\
~
...o·
..
,
,
J
I
~
~
D
::J
PROCESSOR
CACHE BUFFER
RAM
E I--
MAIN
MEMORY
A
\
ADDRESS BUS
il
11
D
,
J
I
A
CACHE TAG
RAM
M
I
Figure 3-2. Typical Memory System with Cache
9-50
3.3
3.3.1
Cache Memory Systems Using 'ACT2151 and 'ACT2152
Set-Associative Cache Address Matching
The' ACT21 51 and' ACT21 52 implement the set-associative type of cache address
matching. This algorithm may be more clearly understood by considering main memory
as an (m) by (n) array of blocks and the cache is an (n) by (k) array (see Figure 3-3).
Each block is composed of (x) words, and transfers between main memory and cache
memory always move all (x) words in that block. Corresponding to every block in the
buffer RAM is a tag address specifying which block of main memory is currently
resident in the buffer RAM at that location. The set-associative algorithm maps each
modulo (n) group of (m) blocks into the corresponding (n) row of the cache. The low
order address lines of the processor covering the sets (n) select a row of the cache
buffer and the corresponding row in the tag RAM. The data is stored in the cache
buffer and the high-order address specifying the block (m) is saved in the tag RAM.
The high-order address then becomes the tag.
CACHE
I~----------------_A-----------------~\
TAG RAM
BUFFER RAM
-,
--,
NV
MAIN MEMORY
n-1
x
--1
-;
--i
LOW ORDER n
ADDRESS
-
x
2
--/
x
x
-;
-;
x
o
o
1 2
-f
_
•
•
•
oJ
m
(HIGH ORDER ADDRESS)
=
=
o =
?
NV
0, 1, 2, m-1
=
=
=
NV
NV
2
0
-
0
1
-
;
_.J
m-1
K
\-------~v~------~
K
X
m-1
--I
- ;
--f
--I
--I
- -f
DATA
·1
LABEL
Number of BUFFER/TAG groups for multiple cache systems
Blocks moved to cache
Valid data from main memory
Areas of cache that have not been loaded from main memory
Code to indicate non-valid label
Labels from high order address specifying the block moved from main memory.
Figure 3-3. Set-Associative Cache Address Matching
3.3.2
Cycle Time Improvement
There are several algorithms used to determine which areas of main memory should
be resident in cache and which should be replaced (first-in, first-out; least recently
used; or random). Since programs typically have the property of locality (over short
periods of time most accesses are to a small group of memory addresses), these
replacement algorithms can make the cache have the majority of processor accesses
resulting in hits. The hit ratio (number of hits x 1OO%/number of memory accesses)
runs 90% and higher in systems with well coordinated memory to cache mapping
routines. As the block size (x) increases, the replacement mapping algorithm options
have greater impact on the cache performance.
9-51
c:
o
m
.~
...oE
'too
.5
en
c:
o
m
.~
.~
15.
Co
"0
+ [(MEM) x (CYC + DEL)]
"2-
Average Cycle Time = [(lNT) x (CYC)]
,..
where INT
percent of time doing internal operations
CYC = processor cycle time
MEM = percent of time doing memory accesses
DEL = number of delay increments x 100 ns
(;'
~
S'
:::I
en
For a processor using 120-ns DRAMs:
....oS"
.3
Average Cycle Time = [(70%) x (125 ns)]
Average Cycle Time = 163 ns
,..
For a processor using 200-ns DRAMs:
:::I
Average Cycle Time = [(70%) x (125 ns)]
Average Cycle Time = 200 ns
~
..
S'
+ [(30%) x (125 + 125)]
+ [(30%) x (125 + 250)]
For the same system with cache memory assume a 90% hit ratio with 60-ns cache
and 120-ns DRAM:
Average Cycle Time = [lNT x CYC]
DEL))]]
+ [MEM x [(HIT x CAC) + (MIS x (CYC +
where INT
percent of time doing internal operations
CYC
processor cycle time
MEM = percent of time doing memory accesses
number of delay increments x 100 ns
DEL
HIT
percent of memory accesses hit cache
MIS
percent of memory accesses miss cache
CAC
cache memory access cycle time
Average Cycle Time = [70% x 125] + [30% x [(90% x 125) + (10% x
125 + 125))]]
Average Cycle Time = 129 ns
This value represents a 20% improvement with 120-ns devices over the non-cache
implementation with 120-ns devices and 35% using 200-ns devices. This performance
improvement can be further demonstrated for those systems using custom or bitslice processors where the memory cycle time as well as access time is of concern.
For this example, consider a processor with a cycle time of 50 ns and main memory
cycle time of 100 ns (use the same access ratios as in the previous example):
9-52
[(70%) x (50)]
Average Cycle Time
(Without Cache)
Average Cycle Time = [70% x 50]
(With Cache)
= 52 ns
+ [(30%) x (100)]
= 65 ns
+ [30% x [(90% x 50) + (10% x 100)]
This represents a 20% decrease in average cycle time for the processor using 50-ns
cache memory. If the main memory was rated at a cycle time of 200 ns, either using
slow main memory or due to allocation of alternate cycles for some other activity
(multiprocessors, direct memory access, display refresh, etc.), the cache would still
give an average cycle time of 55 ns. This is an improvement of 63% over the 95 ns
average cycle time for a non-cache system.
3.3.3
Cache Memory Configurations
Figures 3-4, 3-5, and 3-6 illustrate applications for the' ACT2151 and the' ACT21 52
in cache memory systems. Figure 3-4 shows a cache-memory configuration that has
a 512M-byte main memory with a block size of 4 32-bit words. In this particular
application, a cache containing 1024 four-word blocks was chosen thus defining the
main (n) x (m) array as being 1024 sets of 32,728 four word blocks. The 128Mword memory requires an address bus of 27 lines. The least significant bits (A2·A3)
are used as a word select for one of the four words in each block. The next least
significant address lines (A4-A 13) are used as the set select inputs to the cache buffer
RAM and the cache tag RAM. The remaining high order address lines (A 14-A28) form
the label or tag which is stored and compared by the tag RAM.
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'ACT2151
+
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TIBPAL 16R8
CONTROL
(RESET. W. PE. CS)
Figure 3-4. Cache Memory Configuration (Block Size - 4)
9-53
Since the label in this example is composed of 1 5 address lines, two' ACT21 51 devices
are used to expand the tag. The 15 address lines are the data inputs to the tag RAM.
The other data inputs are tied to 5 V so that, after Reset, invalid data cannot force
a match. The match output of the two' ACT21 51 devices are combined to form the
enable for the cache data buffer. If the contents of either' ACT21 51 do not contain
a match, the cache is not enabled. These signals are also used by the control circuits
to inform the system that the address is not present in the cache so that main memory
might be accessed. The control circuit also resets the cache upon power-up. This
is accomplished by taking the RESET input of the' ACT21 51 low. After reset, no
matches will occur at any locations until that location has been written.
In the application shown in Figure 3-5, the expansion of the cache RAM is carried
out in both depth (more sets) and width (wider tag). The block size was chosen as
one such that the 4K cache now represents 4096 blocks of one word each. The highorder addresses are still used as the label to the tag RAM. A 13 is used to select
between two' ACT21 52 pairs. Each pair contains labels for 2048 of the cache-memory
blocks. Address lines A2 thru A 12 are used as the set-address inputs. If the
chip select (CS) is at a logic high (deselected), the' ACT2152 match output (M) is high.
An AND function can be used to enable the cache data buffers and also notify the
control circuit if access needs to be made into the main memory. The logic for this
system illustrates that the upper pair are compared for the first 2048 blocks within
cache and the lower pair are compared for the second depending on the state of
address A 13.
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CONTROL
AO-A 1 0 M1 t------------------'
'ACT2152
M2~-------------~
'----------is
'ACT2152
Figure 3-5. Cache Memory Configuration (Block Size = 1)
9-54
A dual cache structure (K = 2) is shown in Figure 3-6. The M-word memory is divided
into 4096 sets of 256 four-word blocks. In this example, AO and A 1 are used to select
which one of the four words within a block are accessed. A2-A 12 select which of
the 2048 block labels are to be compared. Addresses A 14-A21 form the eight-bit
label for the block. Address A 13 is used by the cache control logic in conjunction
with the possible processor status lines as chip select inputs. The match outputs from
the two' ACT2152 devices, A 1 and A2, are NANDed to form an active-low enable
to the cache data buffers and to serve as a request to the control logic. The match
outputs from B 1 and B2 also are NAN Ded to perform a similar function for cache RAM
B. If no match is found in cache RAM A or B, the control logic will initiate an access
from main memory. The purpose of the dual-cache architecture is to allow for rapid
switching between multiple tasks or programs since the processor can have access
to one cache while the controller moves data between main memory and the other
cache. The dual or mUltiple cache approach also yields more replacement options than
the single cache architecture. When an access results in a miss in the single cache
system, the data in cache is replaced by the current data even though the old data
may still be useful. By using independent caches, the control can determine which
data is most expendable and replace that block while the other caches keep their
potentially useful data.
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9-56
Until main-memory speeds catch up to CPU processing speeds,
cache memories can be called upon to keep overall throughput rates
up-especiallyas main-memory sizes grow.
Caches keep maim memories
irom s~owing down fast CPUs
This article begins a series on cache-memory
systems long employed in mainframes and high-end
minicomputers, and just now ready to enter
microcomputers as large, but slow dynamic RAMs
become available. The strategy of Texas Instruments
is sketched by Richard N. Gossen, manager of
advanced development, in this issue (p. 32).
Whenever a speed mismatch occurs between mainmemory bulk storage and a fast-processing CPU, a
cache memory can provide the interface to take full
advantage of the CPU's processing speed. From the
main memory, the cache memory extracts and temporarily stores enough data to satisfy immediate
CPU needs. Writing from the main memory is at
the main-memory's slow speed, but reading to the
CPU is at the CPU's high speed. As
the word "cache" implies, the
memory's operation is hidden from
(or rather, transparent to) the user.
Figure la exemplifies an 8-Mbyte
main-and-cache-memory system in a
typical large computer (see "Caches
Needed as Main Memories Grow").
The main memory alone can attain a
cycle time of about 400 ns, but with
error-detection-and-correction circuitry added to the system, a cycle
time of about 500 ns is more likely.
On the other hand, an ECL- or TTLbased CPU can be ten times faster
with about a 50-ns cycle time. Buffering main
memory with a 50-ns cache-well within current
technology-enables the computer to run at a speed
close to the CPU's maximum speed.
Figure lb shows a more detailed block diagram
of a typical cache memory. It represents a set-
associative cache system with 2-kbytes of data storage
capacity in a single-set configuration and it serves
a l6-bit microprocessor system with a 22-bit address
bus. The basic storage elements are two RAM arrays:
one, a 1024 X l6-bit-word unit for data storage; and
the other, a 1024 X l3-bit-word unit for address, or
tag, storage. Addresses that arrive via the CPU data
bus (Ao to A2d are compared with those held in the
tag RAM. If they match, the desired data are located
in the cache's data RAM and the main memory can
be bypassed.
When first turned on, or should the computer
system malfunction or be shut down momentarily,
the cache would then probably contain improper or
erroneous data. Thus, a most important function not
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Cliff Rhodes, Static-RAM Design Manager
Texas Instruments Inc.
4000 Greenbriar Dr., Stafford, TX 77477
Reprinted with permission from ELECTRONIC DESIGN, Vol. 30, No.2 January 21, 1982. Copyright 1982 Hayden Publishing Co., I~c.
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9-57
Cache memories
specifically shown in the block diagram is a special
control-logic section to perform initialization operations for loading the cache with valid initial data.
Particularly important is the proper loading of the
tag RAM to prevent false matches.
Traditionally, cache memories have been constructed with static-RAM bipolar-semiconductor
technology, but recent improvements have given
NMOS static RAMs an edge by requiring less power
at the same speeds as bipolars. The CPUs, of course,
are built from high-speed ECL or Schottky TTL,
whereas main memories usually are composed of
dynamic RAMs that are about an order of magnitude
slower than the CPU.
Cache concept based on probability
No matter what the cache is made of or how it
is configured, its operation is based on "propertyof-locality" probability principles, which experience
has shown to have the following characteristics:
First, over short time periods, most CPU memory
accesses are made to adjacent, small groups of
locations; therefore, even a small cache, storing
carefully selected data, will have data the CPU needs
most of the time. Second, data stored in the cache
and recently used will likely be reused shortly
thereafter. Finally, data adjacent to data that have
been recently used will most likely be used next.
Usually, then, several adjacent words are
transferred from main memory into the cache: The
immediate need may be for just one of the words,
but eventually the subsequent words are likely to
be required. This procedure reduces repeated accesses to main memory ("misses"), and increases the
probability of finding the data in the cache, or "hits."
'To demonstrate the effectiveness of a cache, consider a typical system, where 20% of all CPU operations are memory accesses (misses), the CPU cycle-
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1. In a computer system with a main memory, whose cycle time is a relatively slow 500 ns,
a fast 50·ns cache memory is interposed to match the CPU's 50·ns cycle time (a). In more
detail, a set·associative cache system has address tag words stored in one RAM, while the
data words are stored in a separate RAM (b).
9-58
time is 50 ns, and main-memory cycle-time is 500
ns. Accordingly, average machine-cycle time is
20 X 500 + 80 X 50
100
=140 ns.
However, with a 90%-efficient, 50-ns cache, the
average cycle time is
2 X 500 + 18 X 50 + 80 X 50
100
=59 ns.
Note that with an effective 90% hft ratio, the CPU
is forced to access the main memory on just 2% of
all machine cycles (10% of 20% of the cycles). Thus,
most memory accesses are handled through the
cache, and the average machine cycle-time is cut to
almost a third. However, these calculations are
Address
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Block
Word
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scan
2. A fully associative mapping algorithm allows anyone of
the m X n maln·memory blocks to be placed into anyone
of the cache-memory blocks.
simplified, because only a monoprogram instruction
stream is considered. Indeed, properly designed
cache memories routinely achieve considerably better performance in mainframes and minicomputers
with actual, more complex programs.
A cache memory's data-storage section can be
implemented fairly simply with standard, highspeed static RAMs. However, the address, or tagstorage, section must do more than just store-it
must also compare addresses on the CPU bus with
those it stores. This is best done with an associativeaddressing technique.
Data access by association
Data in an associative or content-addressable
memory are not accessed merely by a location, or
address, code as in conventional memories, but are
found according to some property or "value" of the
data. Instead of an address word, a so-called search
key, or descriptor, is presented to the cache, which
represents particular values of all or some of the bits
of a stored word. When it is compared together with
a "lock"-the so-called tag bits-with all the words
stored in the cache, the search key ferrets out all
associated words. If the key has few attributes-is
therefore said to be "loose" -many words can match
and be accessed.
Though simple in concept, the associative-search
procedure is very complex in execution. The two most
common mapping algorithms that associate a set of
data in main memory-called a "block"-with a
corresponding block in the cache are designated
"fully associative mapping" and "minimal set-associative mapping."
In fully associative mapping (Fig. 2), anyone of
the m X n blocks in main memory can be placed in
anyone of the cache blocks, which then has a tag
address associated with it that specifies from which
main-memory block it came. (One of the tag bitsa control bit-checks the validity of the block, and
(b)
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3. The larger the cache, the smaller the number of misses (a). Splitting the cache Into several Independent
sets further reduces the miss ratio (b); however, In both these cases the Improvement rate tapers off sharply
beyond some specific point. And when block-size and blOCk-quantity are traded off against each other
(c). miss rates are minimized sharply at some particular optimum size/number relationship.
9-59
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Of course, the larger the cache, the smaller the
number of misses on each CPU cycle. However, for
a normalized miss-rate-vs-cache-size plot that assumes a fixed number of blocks in the cache and a
main-memory size from 2 to 4 Mbytes, the rate of
improvement in miss rate diminishes rapidly above
8 kbytes of cache size (Fig. 3a). Thus, the cost of a
very large cache is not paid back in higher
performance, when optimum size is exceeded.
However, further improvement can be obtained by
breaking the cache capacity into a number of sets
-defined as the number of parallel, independent
caches in a system. For the same 2-to-4-Mbyte main
memory and with the total cache size fixed at 8
kbytes, two separate caches of 4 kbytes each offer
better performance than a single 8-kbyte implementation, because another quick data-replacement trial
is available whenever a miss occurs the first time
(Fig. 3b). With a single set, a miss forces accessing
the slow main memory, which replaces all the data
in the cache, even though the replaced data may soon
be required again in the program. However, again
performance increase slows significantly above an
the low-order address bits can define bytes and datatransfer units, or words.) Each address generated by
the CPU must be compared with all of the tags, and
the field of address tags must span all main-memory
m x n blocks, regardless of the cache's capacity. In
this case, the cache acts as a linear array.
In set-associative mapping, a selection from an n
row of m blocks is placed into the corresponding row
of the cache. Then only those bits covering dimension
m become the tag of the set n. Thus, for each CPU
address only the tags in that row must be compared.
However, for the minimum effective set-having a
dimension of two-a linear array must swap blocks
frequently because the cache cannot hold more than
one block from a row at any time.
Whether fully associative or set-associative mapping, if data-block addresses in the cache tag-store
match those on the CPU address-bus, the data are
made available from the cache. And if no match, or
a miss, occurs, the CPU is delayed while the needed
data are fetched from main memory. In this process,
the entire block containing the data sought is
transferred into the cache.
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10 9
Tag
Index
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Word In block
Main-memory physical-address word
Byte
(b)
4. The cache forthe PDP 11/70 Is organized Into two 256 blocks of data totaling 1024 words
(a). Every block has a tag field representative of the physical address of the word In the main
memory(b).
9-60
optimum size-in this case, above between two and
three independent sets for the 8-kbyte cache capacity.
Naturally, block size and the number of blocks also
affect miss rate. However, in a constant-capacity
cache, trading the number of blocks against their size
seems to raise a conflict: Large blocks accommodate
more adjacent data and thus would tend to reduce
the miss rate. But a higher number of smaller blocks
also would help reduce misses by providing more
data choices. Figure 3c shows a minimum miss rate
at about 8 bytes per block, or 1000 blocks, for a total
8-kbyte cache capacity. For block sizes between 2 and
16 bytes, an 8-, 16-, or 32-kbyte cache offers the same
normalized miss-rate performance, although larger
the total capacity, the smaller the absolute miss-rate.
To complete this general overall description of
cache operation, one additional important function
must be examined-the data-replacement algorithm. Again, any time a cache memory records a
miss, a new block containing the required data must
Caches needed as main memories grow
Although advanced microprocessor-based systems
are beginning to see the dawn of the cache-memory
era, large systems like the IBM 360 class and large
minicomputers like the DEC PDP-ll series have bee.n
"caching-in" for years. On a cost-effective basis, a
cache system offers higher system speed for the cost
of just a small quantity of fast memory plus its
associated logic.
The resulting speed depends on the size and organization of the cache, not the size of main memory,
and no programming changes follow when a cache
system is used. Nevertheless, it is the increased mainmemory size that will fuel the growth of cache-type
systems in the upcoming high-performance microcomputers and microprocessor systems.
The high-density RAM chips that will significantly
memories to enable CPU s to make full use of their
improved capabilities. The accompanying table projects the expected speed performance in 1982 of
several of the best known processors.
For example, TI's 99000, with a maximum clockrate of 6 MHz, is expected to support memory access
times of 90 ns. This meshes perfectly with the new
generations of NMOS static RAMs, whose access
times are now in the 3O-to-50 ns range. A 99000 will
almost certainly benefit from a cache-memory system
wh,en it" supports main memories in the megabyte
range. Indeed, the Zilog Z800lA, the MotorolaM68000,
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Fastest supportable
Processor Maximum clock rate
memory access
99000
8001A
68000
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MHz
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RAM
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(kbytes)
64
90 ns
215 ns
225 ns
280 ns
increase the main-memory 'sizes that microprocessors
and microcomputers will be called upon to support
are relatively slow dynamic units (see table). By 1983,
as the 64-kbit dynamic RAM becomes a cost-effective
chip, the average 16-bit processor will be operating
with 128 kbytes of memory. And by 1985, with the
expected maturity of the 256-kbit dynamic RAM, V2Mbyte memories will be commonplace in 16-bit processor systems (see curve). Already, TI's 16-bit 99000
processors can address up to 16 Mbytes with the
addition of a memory-management unit. Systems of
this size, like mainframes and large minicomputers,
will demand cache memories to enhance performance.
While physical memory size encourages the growth
of cache systems, improved microprocessor performance also contributes to wider cache use. Processor
speeds will certainly increase, necessitating fast cache
16
1981
1982
1983
1984
1985
"and the Intel 8086-2 are somewhat slower than the
99000 in memory-ac~ess times; therefore, they should
most definitely benefit from a cache for highperformance applications.
In such microprocessor systems, dynamic RAM
used as the main memory will always remain the
limiting factor to improved system performance
because it is slower than a microprocessor. Even a
dynamic RAM with access time as fast as 150 ns slows
considerably when operated in a 1-Mbyte memory
system using error-detection-and-correction circuitry.
The best performance of such a RAM is in the range
of 400 to 500 ns, minimum. If a processor is forced
to interface at this slow speed, severe performance
penalties result in the system.
9-61
Cache memories
be fetched from main memory to replace the block
already in the cache. But which block should be
removed to make way for the new information?
Clearly, replacement should be based on some type
of index of value for maximum effectiveness, not
randomly performed. An index of value can be based
on the chronology of the data, such as FIFO (firstin, first-out), or the frequency of use, LRU (least
recently used), or a combination of the two. Of these,
LRU is one of the most popular techniques. It is based
on the theory that if information has been often and
recently referenced, it is likely to be referenced again
in the near future.
LRU offers some advantage over the FIFO
algorithm. Even though FIFO eliminates the
possibility of loading data and immediately removing it, FIFO has a serious disadvantage: Even' when
a block of data is frequently and continually used,
eventually it becomes the oldest and is removed,
although experience shows it likely will be needed
again, soon. In addition, FIFO can introduce some
unusual side effects.
The associative cache In the PDP·11
In an actual cache system, say the PDP-1l170, a
1024-word (2048-byte) memory is organized as an
associative cache in two gro·ups, or sets-each group
containing 256 blocks of data and each block containing two. words divided into two bytes (Fig. 4a). Every
block also has a tag field to represent the physical
address in main memory, where the original copy
of the data-block resides.
Data from main memory can be stored in the cache
in an index position determined by its main-memory
physical address (Fig. 4b). An 8-bit index field (bits
2 to 9) of the main memory's 22-bit physical-address
word determines which of the 256 cache-memoryarray blocks will contain the data (either in group
o or group 1 as determined by the hit or miss
conditions). And the lowest two bits (bits 1 and 2)
select word-lor word-2 and byte locations in the
block. But only the high-address field (bits 10 to 21)
-the tag field-is stored in the cache.
Data are always sought in the cache first. If the
information is not present-a miss-a two-word
block of data is transferred (written) from main to
cache memory. In a typical program, writes to the
cache occur just 10% and reads from the cache, 90%
of the time. Read hits average 80 to 95% of all
memory operations in a typical program.O
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9-62
Design
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A cache-tag store and comparator on a single chip will reduce parts
count, save space, and also greatly simplify cache systems in upcoming
minicomputers and microcomputers having large memories.
Cache-memory functoorns
surface on VlS~ chop
This is the second article in a series on
cache-memory systems. The first article,
which covers the basic philosophy of cache
systems, appeared in the Jan. 21 issue (p.
179). The overall approach was sketched by
Richard N. Gossen, manager of advanced
memory development at Texas Instrument.~. in the same issue (p. 32).
Given the growth now occurring, and in
the offing, in the main-memory size of
minicomputer and microcomputer systems, cache memories will be needed to take
full advantage of their CPUs' speed. The
TMS2150 cache-address and comparator IC
represents a major step in simplifying the
cache designer's task, as it handles most of
the so-called tag functions-cache-address
storage and comparison.
A cache memory is a small, fast buffer
memory interposed between a fast CPU
and a relatively slow main memory, like a
dynamic RAM. In this way, with anticipated and frequently used information
prestored in the cache, the CPU can obtain
most of the data and addresses it needs at
a speed comparable to its own. By proper
design, the number of information accesses
to the large but slow main memory can be
reduced to a minimum. With a special memorymapping technique, a small number of cache storage
locations can represent large blocks of backingmemory information.
The cache, a fast static RAM, is divided into two
sections-the tag store for the cache addresses; and
the data store for numerical, program, or other types
Clifford C. Rhodes, Static RAM Design Manager
Jlno Chun, Memory Design Engineer
Troy Herndon, Memory Design Engineer
Texas Instruments Inc.
P.O. Box 1443. Houston. TX 77001
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of data. Cache memories, however, require more
than mere storage. Just as important is high-speed
data comparison to check a portion of the CPU
address field against the tag addresses previously
stored in the static RAM. This operation determines
whether the data addressed by the CPU resides in
the cache.
The 2150 (Fig. 1) stores the cache tags (or addresses) in a 512-word X 9-bit static RAM, and also
contains a 9-bit comparator. In addition, it generates
and checks parity. The RAM's high speed, of course,
matches or exceeds that of most available
Reprinted with permission from ELECTRONIC DESIGN, Vol. 30, No.4 February 18, 1982. Copyright 1982 Hayden Publishing Co., Inc.
9-63
Cache tag-comparator
microprocessors, and the 9-bit comparator circuit,
which is integrated into the chip's memory-sensing
amplifiers, is about 50% faster than bipolar comparators currently found in cache systems.
Housed in a 24-pin, 300-mil ceramic DIP, the 2150
works over an ambient temperature range of 0° to
70°C. Operation is from a single +5-V power supply,
and the chip interfaces directly with both TTL and
MOS logic circuits. Because of the ceramic package,
power dissipation can go as high as 660 !1lW; typical
dissipation, however, is 400 mW. To simplify cachesystem design, the 2150 works fully statically-no
clock or synchronizing signals needed-and it is
easily expandable to fit any size processor bus or
memory system (see "VLSI Built with Proven
Techniques").
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1. The TMS21S0 cache-tag store and comparator, a sIngle
VLSI chIp housed In a ceramIc 24-pln DIP, occupIes 24,600mll2 of silicon and Is fabrIcated wIth proven 4,S-llm desIgn
rules and NMOS technology.
9-64
The use of the 2150 makes for a minimum chipcount cache system, especially in conjunction with
the companion TMS2149 1-k-x-4-bit static RAMs to
store the data. The 2150 alone replaces 14 chips in
conventional systems. Still, even the simplest cachecontrol circuit with the 2150 requires several TIL
devices for buffering and control and some fast
RAMs (like the 2149s) for storage.
In the block diagram of the 2150 (Fig. 2), the tag
static-memory array of 64 rows by 72 columns is
organized into the 512 words of 9 bits each, for a
total of 4608 bits.
Initializing this memory is simple: Merely pulsing
the Reset terminal low to clear all 512 memory
locations forces the chip's Match output terminal
high; and the reset pulse can be as short as 35 ns.
Initializing a conventional cache memory, however,
is much more complex. It requires a set of sequential
operations that is time-consuming and demands far
more hardware than the 2150's asynchronous single
pulse.
A read cycle is enabled when the chip-select
(CS) input is driven low while the write-control input
(W) is held high (Fig. 3a). During this cycle, nine
input-address bits (Ao-As) select a 9-bit word in the
memory array for comparison with eight input-data
bits (Do-D7) and an internally generated parity bit.
Upon a valid match, the Match output terminal goes
high. However, if the parity check indicates an error
in the internal-memory data, the parity-error output
(FE) and the Match output go low. The PE output is
an open-collector type, allowing simple oR-tie connections to other devices.
For a write cycle, both cs and w must be driven
low. Then, the data on the Do-D7 terminals, plus an
even parity bit from the internal parity generator
are written into the memory-array location addressed (or rather tagged) by Ao-As. A parity error
can be forced by holding the PE terminal low, which
is very useful for testing.
The 512-X-9-bit tag memory-array structure
permits the system to be expanded in building-block
fashion for either wider or deeper tag stores. Patterned after bit-slice techniques, the 2150 can be
considered an 8-bit-slice cache-address and comparator; accordingly, a 16-bit word could be divided
into two 8-bit segments and operated on in parallel
by two cache systems, speeding up performance in
comparison with serial operation.
A key speed specification of a cache-address comparator is the delay time, ~ (A), needed for the signal
to go from the address input to the match outputs.
Generally, this specification is a worst-case delay
path in a cache-memory system. The 2150 is available
with four delay versions-maximums of 45, 55, 70,
and 90 ns-to meet a variety of cache-memory
VLSI built with proven techniques
Occupying just 24,600 miP of silicon, the TMS2150
cache-address store and comparator is fabricated with
conservative, 4.5-J,lm design rules and 2.5-J,lm NMOS
polysilicon gate lengths. Many of the 2150's circuit
techniques were first proven on the TMS2147H and
TMS2149 4-k low-power, fast static RAMs. One such
circuit, a distributed column-sensing amplifier (Fig.
a), significantly improves the speed-power product
over that of previous high-speed MOS designs. '
During read cycles, tag data stored in the 2150's
on-board memory are not directly accessible; instead,
they are eompared with the input data and checked
for parity. Since this parity check must be performed
at high speed, the sense amplifiers must reach valid
Bit
level signal to the circuit's column-select input. This
input activates the column amplifier, which differentially drives the pair of common-data lines to the
sensed state, which is then quickly transformed into
sharp, clean logic levels by the sense amplifier.
To write data into the on-board memory, the pair
of data-in signal lines (Din and Din> must activate the
gates of the bit-line pull-down transistors. With the
desired column selected, forcing a data-in line to the
V00 voltage level pulls the associated bit line low to
write the data in. At the same time, the complementary Data In line is held low, which permits the
complementary bit line to rise to Voo via the bit-line
bias circuitry (not shown).
Because the bit lines are fully isolated from dataline loading, they can be driven efficiently by the
D,
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logic levels very quickly. That is beyond conventional
differential amplifiers, but does not faze the distributed, column-sensing amplifier in the 2150. One
method employed in the sense amplifier to help
achieve the required speed is to isolate the bit lines
(BIT and BIT) fully from the data lines (D out and
Douv thus reducing the amplifier loading, which
would hold speed down.
A cross-coupled pair of FETs driven by data-line
source-followers acts as the main sense amplifier. This
circuit provides fast level shifting, high gain, and
excellent performance over the total expected range
of semiconductor processing variations and operating
temperatures.
Reading occurs when a column is selected by a high-
-
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2. The 2150 contains a 64-row-x-72-column static-RAM memory array organized as 512 words
of 9 bits each. The RAM stores tag-address data for the cache system, and the rest of the
chip provides the logic for comparing the stored tag address with the address on the databus line for validity, and providing or checking the data's parity.
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3. The timing cycles for 2150 start with a 'Cs-Iow signal. After comparison and matching, either
a Match high or a parity error (PE) low Is obtained (a). The worst-case time delay between
the address input and match output, td (A), Is a key 2150 specification, and Is available as
one of four maximum values. A unit actually measured has a typlcal30-ns l.! (A) delay (b).
9-66
required. Moreover, a single-board cache memory
virtually eliminates the delay times from the
capacitances introduced by buffers, conductor
traces, board connectors, and backplane wiring.
For example, the board can contain a single-set,
2-kbyte cache memory for 16-bit words (Fig. 5). Two
2150s serve for tag storage and comparison and four
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2149s hold the 16-bit data words. Taken together with
some TTL packages-four 74S240 octal buffers and
one 74S10-they make an ll-package tag and datastorage system that requires only a controller (not
shown) to support a two-way interleaved backing
dynamic memory. This cache board, which operates
at a total delay from address input to valid-data
output of less than 80 ns, can be applied to almost
any 16-bit minicomputer or microprocessor system
having a 22-bit address field.
Acting as 8-bit-slice devices, the two 2150s split
the processor address bus into two sections when
comparing and matching addresses. When an address match is verified by both chips, the Match
outputs-gated through GI-supply an enable signal
to the 74S240s configured as bidirectional buffers.
that way, address-input data can move from the
2149 static RAMs to the processor data bus.
When the write-enable (WE) line is pulled low, data
are entered into the 2149 RAMs from the processor,
while the tag addresses of the data are entered into
the 2150's internal tag-store RAM.o
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After the decision has been made to go with block
transfers of data to the cache in the distributedintelligence system, the next thing to determine is
the location of the cache. InFig. 2, the cache is located
on the global-memory board. This cache location can
decrease the time on the bus for memory accesses;
accordingly, the bus is available for more data
transfers. While this cache location decreases the
overhead time per memory-data bus transfer, the
number of such bus transfers remains the same as
without the cache.
However, if the cache memory is located as in Fig.
4, the number of transfers over the bus is reduced.
A block of data is accessed from main memory just
once, but locally the same data can be used many
times over without having to go back to the main
memory via the bus. The bus bandwidth, thus freed
up, now allows an increase in the amount of data
transferred in each block. In addition, the cache block
can be made large enough to achieve a desired hit
ratio.
But if the processors run very long, uninterrupted
programs and need just a few global-memory accesses, a simple FF A configuration (Fig. 4 without
a cache, but with ordinary local memory) could be
the most economical approach. With such programs,
each processor executes the same on-board routines
and accesses the same data locations repeatedly.
Then the global memory need handle just messages
between processors and system-wide instructions
and data.
With the traffic on the bus reduced substantially,
more processors can be added to the bus. And globalto-local-memory transfers could proceed via a directmemory-access (DMA) system, which of course
would be initialized under software control.
Transfers via a local cache system (Fig. 4 with cache
systems), however, would carry out the transfers
automatically, transparent to the software.
Almost transparent
When a distributed system is implemented with
local caches, the software is virtually unaware of the
split between the local and global memories:
9-70
System
throughput
(words!s)
Number of processors (n)
3. When a multiprocessor system shares a sIngle
bus, throughput rIses proportionately at fIrst wIth
the number of processors, but tapers off as the
bus's data-handling capacIty saturates.
Hardware-the cache's control logic-maps the contents of each local cache into the global memory, and
the cache is largely transparent to the software. (By
comparison, in a DMA arrangement, the software
would have to be totally involved in the local-global
memory split.) Accordingly, with distributed cache
systems, existing software (such as Pascal) for
centralized-CPU systems can be used, with but
minor modifications, for a higher-performance
distributed-intelligence system.
Clearly, the distributed cache-system approach is
general-purpose: All data and instructions can be
mapped into the global memory as in the centralized
system, and the local caches will then (almost)
transparently remap the information for local use.
In other words, the distributed system with local
cache can best serve a general-purpose processing
environment, where the specific functions of the
individual processors cannot be predicted in advance,
and thus where the contents of the local memories
cannot be fixed at the time the system hardware is
configured.
On the other hand, with a fairly fixed and predictable installation, perhaps with Fortran software, or
in a plant-process-control application, where the data
and software needed on each processor (board) are
firmly established, the FF A approach could be used
in place of local caches. But to achieve even greater
performance, a distributed memory system can combine two or more of the approaches described. For
example, cache memories can be employed for both
the local and global memories-a combination of
Figs. 2 and 4. The local cache decreases the number
of references to the global memory, and the global
cache decreases the average length of the bus cycles
when global accesses do become necessary. Or, in a
variation of the distributed-processor system of Fig.
2c, local memory and local cache can be used on the
same processor. In Fig. 2d, the addition of a cache
improves the performance of a large but slow local
memory composed of 64-kbyte (or larger) dynamic
RAMs.
Cache-memory archHectures
Although, in general, employing local caches in a
distributed system (like the one in Fig. 2c) will
remove local instruction and data traffic from the
bus and speed throughput substantially, trying to
make the caches appear totally transparent can
introduce interference problems with messages
between processors. In the distributed system of Fig.
2c, for example, messages between processors should
not be accessed through the local caches because this
class of data is not held there: The caches contain
only local current instructions and data from the
global memory. As a result, in Fig. 3, when microprocessor 1 writes a message to microprocessor 2, the
data should pass via a particular location in the
global memory that acts as a message buffer. In the
process, the local cache on the microprocessor-1
board must be prevented from intercepting the
message. And when microprocessor 2 tries to read
the message, its cache also must be removed from
the message path. Otherwise, microprocessor 2 will
encounter stale data in cache memory, and not the
new message from microprocessor 1, which had just
been deposited into the global-memory.
A write-through (as opposed to nonwrite through
or write-back) caching policy can ensure microprocessor 1 writes its message to global memory, but
additional steps are needed to ensure that
microprocessor 2 reads the message from global
memory without interference from its cache.
Software recognition of the special status of interprocessor messages can easily solve this potential
problem. But this approach constitutes a lack of total
transparency for the caches.
One approach passes all interprocessor messages
through the microprocessor's I/O space. Since I/O
data are not cached, this strategy automatically
4. A cache, located at the slow global memory as in Fig. 2,
can reduce the number of required slow accesses to main
memory, thus leaving the bus more time for other activities.
But locating part of the memory at each processor-in a
distributed architecture-Is even better.
avoids the interference problem. Interprocessor
messages pass through the I/O space, bypassing the
caches altogether. So if the software is initially
written to handle the interprocessor messages via
the I/O space, then when caches are introduced, they
will automatically be transparent to the caches.
Alternately, a particular set of addresses in the
global-memory space can be dedicated to message
passing. The control logic in each processor-hoard's
cache could incorporate a comparison circuit that
recognized the message-space addresses and allows
access to the message area in global memory to
bypass the cache.
System data should also bypass the caches and be
taken by a processor directly from the master copy
in the main memory: Such data are constantly being
updated by the other processors. If passed via the
local caches, such data would invariably be perceived
as stale because of the constant updating. If allocated
to specific and exclusive global-memory addresses,
these system data can be handled like the interprocessor messages to bypass the caches.
Similarly, each processor should have exclusive
access to its own private instruction and data segments in the global memory. In this way, the data
are "protected," with some support from bus
hardware, from a processor that may go "berserk"
and corrupt the instruction and data segments of the
other processors in the system.
Clearly, with caches in distributed-intelligence
systems, the memory accesses must be organized
rationally to optimize throughput, avoid inefficient
data thrashing and, most important of all, avoid
using data belonging to other processors. Of course,
with a single cache (as in Figs. 1 and 2), it is rather
difficult to mix up the data, since the cache should
always contain updated master versions of the corresponding blocks of memory (which is never
changed without knowledge of the cache). In a
multiprocessor system like Fig. 4, however, each
local cache is supposed to keep a separate, accurate
copy of some portion of the global memory-as it
pertains to its own processor. But a mixup is possible
because of the multiplicity of processors.
The point of all this is that it is exceedingly
difficult to make the cache memories in a distributed
system totally transparent to software, while simultaneously ensuring that each processor is provided
with a coherent, updated version of the contents of
global memory. Methods have been proposed for
accomplishing just this, but they tend to be expensive
in terms of the hardware required, and are thereforcbeyond the reach of the typical microprocessor-based
system.
In some systems, the entire contents of the cache
may have to be "flushed," if for any reason its
9-71
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contents have become invalid. For example, a DMA
device may alter the contents of main memory,
invalidating the contents of the cache. Also, consider
the case of a processor attached to a memory mapper
(like a 74LS610), which translates the logical addresses output from the processor into the physical
addresses used to access the memory. A cache will
usually be attached directly to the processor to avoid
lengthening the cache access time with the propagation delay through the mapper circuitry. However,
this means that the cache contents are mapped into
the logical rather than the physical address space.
Consequently, when the map file is altered, this
makes the cache contents invalid since the mapping
of the logical into the physical address space is no
longer the same.
For applications where the cache contents must
frequently be flushed, a cache-reset function is
. essential. Without the ability to flush the cache
instantaneously, the system would be forced to clear
each cache block, one by one.
But flushing the entire cache when just a small
portion of its contents needs updating is wasteful.
Naturally, a more complex reloading arrangement
can be designed to provide higher caching efficiency
where only part of the cache data must be replaced
frequently, but only at the expense of increased
overhead in logic and software. Selectively dumping
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5. The local memory can be In "ordinary" RAM
form (as in functlon-to-functlon architecture) or in
cache form. Or, both a cache and a local dynamic
RAM can be used.
only the affected areas of the cache capacity-such
as when a DMA operation partially alters the contents of the global memory-instead of a total reset,
would be more efficient, but also much more expensive. It would also occupy more board space.
Complexity requires board space. With the trend
to smallness in electronic packaging, sometimes
compromises must be made. CPU speed is generally
compromised when going from a multiboard
minicomputer design to a design that just barely
crams a CPU onto a single board. To put substantial
memory onto the board as well usually requires going
to a slower microcomputer design, which puts the
CPU into a chip, and leaves board room for the
memory. However, the speed lost because of these
compromises can be partially recovered by incorporating a cache on the board (or even on the
microprocessor chip). The cache effectively raises the
individual processor's memory access speed when it
is used with a slow on-board dynamic RAM (Fig. 5).
The TMS9995 microprocessor is a precache step
in this direction: It contains a modest chunk (256
bytes) of high-speed random-access memory, which
is mapped into a fixed area of the processor's address
space. Thus, it does not qualify strictly as a cache.
However, it can be used to the same effect by loading
the RAM-under explicit software control-with
currently needed data and instructions .
The next step would be to put a cache on the
processor board (or chip) with as much memory as
the board space allows, all of which would be almost
transparent to the system software. Equally important, a cache could make the most of the limited
amount of memory that now can be put onto a board
with the microprocessor and 110.
Despite the transparency, a programmer who is
aware of the cache's capability can fine-tune the
software to maximize its efficiency. On the other
hand, overly refined software for one hardware
system can produce poor efficiency on another, while
remaining transportable in the sense that it executes
without error. But as software can be adapted to
maximize the efficiency of cache configuration and
minimize its limitations, so can cache-system
hardware be designed to best fit very extensive
existing software. It is a two-way street. 0
References
1. "Functional Architecture Threatens Central CPU," ELECSept. 3, 1981, p. 141-156.
TRONIC DESIGN,
6. Interprocessor messages should bypass caches to avoid
interference. This can be accomplished with the software or
special overhead hardware, or by employing the
. microprocessor's I/O space to carry the messages.
9-72
4
Error Detection and Correction (EDAC)
4.1
Use of an Error Detection and Correction (EDAC) Device
4.1 .1
Introduction
The DRAM technology of today (i.e., 256K/M) has enabled system designers to use
much larger memory sizes than ever before. However, as with most advances in
technology, this has brought a new problem. For system memory sizes larger than
1/2 million bits, it is generally considered that error detection and correction is required
to guarantee system reliability without a tradeoff in performance. Although present
methods of parity checking will identify errors, they are not able to correct them. And
not correcting these errors can be co'stly. For example, in personal computers when
parity errors are encountered, the system has to be reset to eliminate the problem.
This system reset destroys any data stored in RAM and it must be reentered. Obviously
this is unacceptable to your customers. To eliminate this problem, TI has produced
a cost effective Error Detection and Correction (EDAC) device.
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4.1.2
Error Types and Sources in Dynamic Memories
Two kinds of errors occur in memory devices; soft and/or hard errors. A hard error
is a physical failure of the memory device (e.g., an internal short or an open lead).
This type of error causes the memory location to always be either a high or a low.
A soft error is a random occurrence of a memory location change from a high level
to low level. These errors may be caused by system noise, alpha particle radiation,
or power surges.
In spite of design techniques used by memory chip manufactures to reduce these
errors, they are still a source of major concern in your system. Table 4-1 indicates
that as the density of memory chips increase their probability of errors also increase.
Therefore, your data integrity decreases in larger memory arrays.
Table 4-1. Chip Densities vs Soft-Error Rates
4.1.3
CHIP DENSITY
TYPICAL SOFT-ERROR RATE
BITS/CHIP
(% PER 1000 HOURS)
64K
0.10 - 0.20
256K
0.15 - 0.30
1M
0.20 - 0.35
Solutions to Boost System Reliability
There are several alternatives available that will either decrease or eliminate these
errors in your system. One method used to determine data integrity is the incorporation
of parity checking. This can be accomplished by using an SN74ALS29833 Parity Bus
Transceiver. To identify an error, the data word and the generated parity are compared
by performing an exclusive-OR operation. If several bits in the data word are in error
or the parity has changed, the exclusive-OR output would be low. While data integrity
can be determined using this method, it is unable to correct errors.
9-73
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tBased on 16M-Bit memory system using 256K DRAMs with a 0_30% per 1000 hour soft error rate.
When you include the other system' variables causing errors (power surges, noisy
systems, etc.), your memory system MTBF, without an EDAC could be reduced to
several days. These types of memory-cell errors can be corrected using an EDAC.
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When data is written to memory, the TI SN74AS632 (32-Bit EDAC) generates parity
check bits. Each check bit is generated by performing a specific parity check on the
32-bit data word. For example, CBO is obtained by comparing specific bits of the 32-bit
word with those corresponding to an "x" in the Hamming Code Parity Algorithm (see
Table 4-3). CBO will be at a high level if the total number of highs corresponding to
these locations is an odd number. CBO will be at a low level if this number is even .
This procedure is repeated 7 times to obtain the 7 check bits, CBO-CB6 of the Hamming
Code. Check bits CBO-CB2 are used to determine odd parity. Check bits CB3-CB6
are used for even parity.
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Table 4-3. Hamming Code Parity Algorithm
CHECK
WORD
BIT
CBO
CB1
CB2
CB3
CB4
CB5
CB6
32-BIT OAT A WORD
1
0
X
X X X X
X
X X
X
X
X X X
X
X
X X X
X
X
X
X
X X
X
X
X
X
X
X
X X
X
X
X
X X
X X
X
X X
X X
X X X
X X
X X X
X
X X X
X X X
X X X X X X
X X
X X X X X X
X X
X X X X X X X X
X X X X X X X X
X X X X X X X
X X X X X X X X
X
X
X
X
31 30292827262524232221 20 19 18 17 16 15 1413 12 11 10 9
8
7
6
5
X
4
3
2
X
The seven check bits are parity bits derived from the matrix of data bits as indicated by "X" for each bit.
These check bits are stored along with the data in your systems main memory. This
additional memory requirement is the only overhead involved with the use of an EDAC.
Figure 4-1 shows a typical system using an EDAC and illustrates this overhead.
9-74
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During a read cycle, the data and check bits are read from memory, any of which
may be invalid. New check bits are computed from the stored data bits. To determine
the validity of the data, the new and old check bits are exciusive-ORed producing
a 7-bit syndrome code. When decoded, these syndrome bits describe the condition
of the data word: free of errors, having a single bit error, or having multiple errors.
See Table 4-4. Any single error in the 32-bit word can be corrected. Both single and
double bit errors are indicated to the processor via single and double bit error flags.
There are two additional options for implementing EDAC into your system; detect
only and correct always. Of these two, correct always is the easiest to implement.
The EDAC always corrects single-bit errors and writes this corrected word onto the
system data bus or into memory.
Because days can elapse between errors, correction can be done only when needed.
The detect-only option increases your system performance during a read cycle by
allowing data to be written directly to the system processor. If a single or double bit
error occurs, the EDAC will flag the processor. This enables the processor to enter
a wait cycle until the word is corrected. This method of implementation does not use
the error correction portion of the EDAC until the processor determines what action
to take in the event of an error.
Another method of ensuring data integrity in your system is to use an EDAC unit during
memory refresh. The EDAC will "clean" every memory location of errors during the
mandatory refresh cycles. This process is known as memory scrubbing. The data can
then be checked again during a memory-access cycle. By checking the data twice,
the time between corrections is reduced. Therefore, the probability of multibit errors
in your system declines.
9-75
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OB18
L
L L H H L H
L L L H H H L
2-bit
OB2
H H L H H L H
2-bit
unc
H L L H H L H
H L L H H H L
unc
2-bit
L H L H H L H
L H L H H H L
OB14
H H L H H H L
2-bit
Q)
....
L L L H H H H
OB30
L H L H H H H
2-bit
H L L H H H H
2-bit
H H L H H H H
CB4
'C
0'
0'
::s
en
L
L H L L L L
2-bit
L H H L L L L
OBO
H L H L L L L
unc
H H H L L L L
2-bit
L
L H L L L H
unc
L H H L L L H
2-bit
H L H L L L H
2-bit
H H H L L L H
OB16
unc
L L H L L H L
OB29
L H H L L H L
2-bit
H L H L L H L
2-bit
H H H L L H L
L
L H L L H H
2-bit
L H H L L H H
unc
H L H L L H H
OB13
H H H L L H H
2-bit
o
L
L H L H L L
OB28
L H H L H L L
2-bit
H L H L H L L
2-bit
H H H L H L L
OB17
L L H L H L H
2-bit
L H H L H L H
OB1
H L H L H L H
OB12
H H H L H L H
2-bit
Q)
....
L L H L H H L
2-bit
L H H L H H L
unc
H L H L H H L
OB11
H H H L H H L
2-bit
0'
::s
L L H L H H H
OB27
L H H L H H H
2-bit
H L H L H H H
2-bit
H H H L H H H
CB3
L
OB26
L H H H L L L
2-bit
H L H H L L L
2-bit
H H H H L L L
unc
2-bit
L H H H L L H
unc
OB10
H H H H L L H
2-bit
2-bit
L H H H L H L
unc
H L H H L L H
H L H H L H L
OB9
H H H H L H L
2-bit
OB25
L H H H L H H
2-bit
H L H H L H H
2-bit
H H H H L H H
CB2
S'
-h
..3
..
L H H L L L
L
L H H L L H
L L H H L H L
L
L H H L H H
L
L H H H L L
2-bit
L H H H H L L
unc
H L H H H L L
OB8
H H H H H L L
2-bit
L
L H H H L H
OB24
L H H H H L H
2-bit
H L H H H L H
2-bit
H H H H H L H
CB1
unc
L H H H H H L
2-bit
H L H H H H L
2-bit
H H H H H H L
CBO
2-bit
L H H H H H H
CB6
H L H H H H H
CB5
H H H H H H H
none
L L H H H H L
L
L H H H H H
CB X = error in check bit X
OB Y = error in data bit Y
2-bit = double-bit error
unc = uncorrectable multibit error
The circuit illustrated in Figure 4-2 is an example of a memory system that used
scrubbing. This circuit consists of the TI SN74ALS6302, a 1 M-DRAM Controller, the
TMS4C1024, 1 M DRAMs, the SN74AS632, a 32-bit EDAC, and control circuits.
9-76
REFRESH
TIMER
TIBPAL16RB
~
~
REF REO
REID
CLOCK
OSC
TIMING
CONTROLLER
TIBPAL.
TMS4Cl024
REFREQ
f----- OSC
RFC
CLK
~
CLK
CAS
~
RAS
RASi
MCI
MCO
MCO
A23 I - - - -
r - - RIW
r-G
I
00·09
SOt---
A23
re:
r-.
MSEL
MCl
I N T I - - - - INT
r--'
RASO
LE
MSEL
A 5 1 - - - - AS
~ A9·AO
'AL6301
LE
RSf f--~ REID
CPU
I+-
SIt----
r - r-r-
OECB t - - -
RAS1
TMS4Cl024
I
lMx 16 BITS
UCASI
~W
i
I
I
I
I
6 CHECK
BITS
LCAST I -
TMS4Cl024
OEBO'3~
tb RAn
RAS2
RAS3
SELO
I
A22
LCASO I -
I
EARl-MERii f--
A21
6 CHECKS
BITS
I
I
1M x 16 BITS
r-r
r-f---t
RASI
I
I
RASli
BYTE
"~OO"'"~
UCAS0t-
SEL1
ROW IA1·Al01
COLUMN IA II·A201
A20·Al
CASO
CASI
CAS2
CAS3
r--r---
t"-i
I'----i
r
A9·AO
t--
UCAS2
~W
TIBPAL16LB
LCA50
rn
LCA51
LCA52
LCA53
L~I-
~==
'-1=
I
RAn
lMx 16 BITS
A9·AO
UCAS5
015·00
015·00
I
I
I
..E
ca
6 CHECK
BITS
LCAnf-
I
r-- r - - - / - r-- r - - - r--r--r-- t - - -
r-- t---
RIW
II
I II
'AS632
~~
00·07 -VCC
024·031 -VCC
(1'
' - - - - 0ECii
' - - - ERR
CBO·CB5
' - - - - - MERR
L - - - OEBO·3
CB61
Figure 4-2. Memory Management Systems Using Scrubbing
4.1.5
.5
en
c
o
.~
ca
.~
C.
Q.
-
~
121
05·023
J2
'C
'E.
ri"
Q)
;::,
The 'ALS632B series devices are not limited to 32-bit systems. They can be
implemented in 16- or 24-bit systems. In the case of 16-bit systems, the additional
memory needed for holding the check bits can be reduced when compared to
conventional 16-bit EDACs.
S'...."
The pin functions are listed in Table 4-6. Mechanical data for the 'ALS632B, 'ALS633,
'ALS634A, and 'ALS635 is shown in Figure 4-4 .
,...
0"
en
...o
3Q)
0"
;::,
Table 4-6. Pin Function for' ALS632B, ,ALS633, , ALS634A, and' ALS635
,...
..
DESCRIPTION
PIN NAME
Selects the operating mode of the EDAC
Sl
MODE
SO
WRITE
L
L
READ & FLAG
H
L
CORRECT
H
H
Sl,SO
L
H
DIAGNOSTIC
OPERATION
Input dataworp and output checkword
Input dataword and output error flags
Latched input data and checkword/output corrected
Data and error syndrome code
Input various datawords against latched
checkword/output valid error flags
DBa through DB31
I/O port for entering or outputing data
OEBO through OEB3
Three state control for the data I/O port. A high allows data to be entered, and
low outputs the data. Each pin controls 8 data I/O ports (or one byte). OEBO
controls DBa through DB7, OEBl controls DB8 through DB15, OEB2 controls DB16 through
DB23, and OEB3 controls DB24 through DB31.
('ALS632B, 'ALS633)
OEDB
(ALS634, ALS635)
Three state control for the data 1/0 port. When low allows data to outputed and a high allows
data to be entered.
LEDBO
Controls the dataword output latch. When low, the data output latch is transparent. When high, the
latch stores whatever data was setup at its inputs when the last low to high transistion occured on the pin.
csa through
CS6
I/O Port for entering or outputing the checkword. It is also us'ed to output the syndrome error code
during the error correction mode.
OECS
Three state control for the checkword I/O port. A high allows data to be entered and a low
allows either the checkword or syndrome code (depending on EDAC mode) to be outputed.
ERR
Single error output flag, a low indicates at least a single bit error.
MERR
Multiple error output flag, when low indicates two Or more errors present
9-80
ceramic packages - side-braze (JD suffix)
This is a hermetically sealed ceramic package with a metal cap and side-brazed tin-plated leads.
'ALS632B, 'ALS633 ••• JD PACKAGE
(TOP VIEW)
'ALS634A, 'ALS635 ••• JD PACKAGE
(TOP VIEW)
Vcc
LEOBO
MERR
ERR
OBO
OBl
OB2
OB3
OB4
OB5
OEBO
DB6
OB7
GNO
OBS
OB9
OEBl
OB10
OBll
OB12
OB13
OB14
OB15
CB6
CB5
CB4
OECB
MERR
ERR
OBO
OBl
DB2
OB3
DB4
OB5
OEOB
OB6
OB7
GNO
DB8
OB9
OB10
OBll
OB12
OB13
OB14
OB15
CB6
CB5
CB4
OECB
Sl
SO
OB31
OB30
OB29
OB28
OB27
OB26
OEB3
OB25
OB24
GNO
OB23
OB22
OEB2
OB21
OB20
OB19
OB18
OB17
OB16
CBO
CBl
CB2
CB3
~
CO
...Eo
....
Q
IJ
.5
r::::
j
BMAX
o
'';::;
CO
.2
C.
Q,
,"n'''o>~ ~1[::] ~ ~ ~ ]1
(0
f.AI
"C
"2.
1
(XIY - 1)
For example, with depth = 64, X
of a frame = 256 words.
= 1 MHz, and Y = 0.8 MHz, the maximum length
c:;"
,..
D)
0"
::::s
en
S"
o"""
5.1.5
.3
Synchronization Design Considerations
In synchronizing applications, the data producer and consumer can operate
continuously but asynchronously. The maximum throughput of the FIFO depends on
both the clock rate at each port (Fin and Fout) and the fall-through time (TFl. (fmax)
is derived from the maximum one-word time delay through the FIFO. The equations are:
,..
7. MAXIMUM DELAY
::::s
8. - - - -
..
D)
=~ +
TF
Fin
0"
f max
9. f max = - - - 1/Fin + TF
For a toggle fall-through FIFO in these conditions f max is considerably less than
Fin. For example, if Fin = 30 MHz and TF = 1000 ns, then f max = 967 KHz.
For a zero fall-through FIFO, f max approaches Fin. For example, if Fin = 35 MHz
and TF = 40 ns, then f max = 14.6 MHz. To ensure only a single-clock delay from
the input and to output ports, the FIFO must be clocked at a rate less than f max .
The FIFO may be operated at higher rates by working near the half-full condition.
The number of words that can be written into an empty FIFO in the fall-through
time (or read from a full FIFO) determines the margins from the empty condition
for operating the FIFO at its maximum rate (Fin)' The numbers correspond to:
10. MARGIN
F'
=~
1/TF
For example, if Fin = 30 MHz and TF = 1000 ns, then the margin = 30 words.
For a 64-word FIFO this would mean that the FIFO could be operated at its maximum
throughput rate (Fin) when it is between 30 words and 64words full. Figure 5-4
shows the throughput curve for this type FIFO.
9-90
~
~
30
I
o>
c:
Ql
::l
g
Fin = 30 MHz
TF = 1000 ns
20
u:
E
E
::l
.~
10
~
I
>C
III
J
0.967
o 01....-----....- - - - - -....30
64
FIFO Words
Figure 5-4. Throughput Curve for 64-Word, 30-MHz FIFO
In general, cascading N FIFOs in depth causes equations 9 and 10 to change to:
12. MARGIN
c
o
11. f max = - - - - - - 1/(Fin + N • TF)
.~
as
...oE
Fin
1/(N • TF)
'to-
.E
en
5.1.6
c
Summary
FIFOs are versatile building blocks for the design of data communication products.
The need for buffering and/or synchronization of data can be met by selecting the
appropriately-sized toggle or zero fall-through FIFO using the methods presented in
this report. TI produces many different single-chip FIFO products for a wide range
of applications. Contact your local TI representative to obtain individual FIFO data
sheets for further information about a particular product.
9-91
o
;
as
.~
Q.
Co
<
9-92
6
BiCMOS
6.1
BiCMOS Memory Drivers Boost Performance
In current memory management systems, the replacement of discrete logic with singlechip solutions for DRAM control, Error Detection and Correction, and Cache Tag control
has greatly improved memory access times. However, in large MaS memory
applications the use of external drivers in conjunction with the memory management
products can provide added drive to maintain maximum performance. These drivers
must meet the requirements of high drive for high capacitive loads, high speed for
maximum system throughput, and low power for system power constraints. The
designer can now meet these needs with the TI 2000 series Sus Interface devices
with improved performance and reliability. The devices offered in new SiCMOS, 'AS,
and 'ALS technologies provide designers with the characteristics needed to drive the
high capacitive loads in MaS memory and bus-intensive systems while reducing
undershoot for reliable system performance.
c
o
"';:;
6.1.1
Reducing Undershoot Problems
In order to maintain maximum system throughput, memory drivers require high-speed
operation with very fast switching speeds. As a result, these switching speeds
together with the high inductance and capacitance in bus intensive environments can
create problems with output signal undershoot and overshoot. This undershoot and
overshoot can cause system reliability problems such as false reads at the input to
DRAMs. Commonly, these problems with undershoot and overshoot are controlled
with an external series resistor, which increases package count and board space. The
2000 series devices provide on-chip 25-0 series damping resistors on all outputs to
reduce undershoot and overshoot without adding to board real estate. Figure 6-1
compares the initial undershoot of the 'AS640 and the 'AS2640 with on-chip series
damping resistors. The 'AS2640 can reduce initial undershoot by 58% thus supplying
a more reliable input to systems susceptible to undershoot problems.
\
\
2
1\
'\
\
1\
yI . . . .
o
'f-'
-
vrl
-2
SN74AS2640
SN74AS640
J
V
1 VOLT/DIV
Figure 6.-1. Effect of On-Chip Series Output Resistors
9-93
.....E
CO
o
.5
tn
C
o
".;::;
CO
"~
Q.
c.
<
6.1.2
BiCMOS Drivers Match MOS Memory Needs
The 2000 series devices offered in the new TI BiCMOS technology provide the
advantages of both bipolar and CMOS. BiCMOS combines 2-ItM IMPAGTTM bipolar
with 1 .5-ItM CMOS to provide the high drive and speeds of bipolar and the low power
of CMOS. These interface devices have TTL input and output transistors with CMOS
internal circuits. The output transistors supply 48/64 mA of drive current necessary
for bus structures such as VME and MULTIBUS II, while the CMOS internal circuits
provide low power during disabled or 3-state operation. As with all 2000 series
devices, the BiCMOS parts have series damping resistors to reduce undershoot and
overshoot.
The BiGMOS drivers can provide the drive and speed necessary in MOS memory
applications with a power savings over bipolar devices. Figure 6-2 shows a 4-M word
x 32-bit memory configuration consisting of a SN74ALS6301 Dynamic Memory
Controller (DMC), a SN74BCT2828 Memory Driver and 4-M words of memory
comprised of four banks of TMS4G1024 DRAMs. Each SN74ALS6301 can control
up to 4M words of memory. The memory driver provides extra drive to maintain
maximum performance in a 32-bit system.
>
"C
"2c;"
..
0)
0"
::::I
o
;-
\
J
..3
CPU
o"""
.
0)
..
,
ADDRESS
SN74ALS6301
DYNAMIC
MEMORY
CONTROLLER
,
MCO.1
0"
2lf
::::I
RASi
r--
MEMORY
TIMING
CONTROLLER
10
\
ADDR
/
TMS4C1024
4 BANKS
4·MEGAWORDS x 32·BITS
RAS
_
CAS
CAS I MSEL
r
SN74BCT2828
MEMORY
DRIVER
r-;4
.,4
.. RAS
.. CAS
~iii
~~
..
r--
iii
~
~
I
DATA BUS
Figure 6-2. 4M Word x 32-Bit Memory System
6.1.3
BiCMOS Lowers Power by 50% or More
When comparing the performance of the SN74BCT2828 to the functionally equivalent
AM29828, there is a considerable power reduction. As shown below, there is a 50%
reduction in supply current while enabled. However, the real savings comes from the
disabled operation. There is more than a 95% supply current reduction while disabled.
Since the amount of time a driver is enabled varies with each system, power reduction
will vary with the minimum being 50% improvement.
ICC enabled
ICC disabled
9-94
AM29828
80 mA
80 mA
'BCT2828
40 mA
3 mA
In applications that involve mUltiple drivers the power savings is even more apparent.
For example, if a system requires five drivers with only one enabled at any given time,
the AM29828 would use almost 8 times more current then the SN74BCT2828.
Total
Result
6.1.4
=
'BCT2828
1 x 40 mA
4 x 3 mA
AM29828
1 x 80 mA
4 x 80 mA
ICC enabled
ICC disabled
52 mA
400 mA
87% power savings
Less Undershoot Means Higher Reliability
The use of the 2000 series SiCMOS drivers also provides the reduced undershoot
to prevent false reads at the inputs to the DRAMs without the addition of external
resistors. Figure 6-3 shows the improvement of initial undershoot of the
SN74SCT2828 compared with the AM29828. The SN74BCT2828 undershoot is 40%
less than the AM29828 providing a more reliable signal with the same package count.
"';:
.E
-r
o
'too
BCT2B2J
:>
Ci
:>
I
I
I
I
I
I
I
.5
~
AM29828
B
o
I
I
I
I
I
I
\'
I
en
c
r
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
o
"';:
m
"~
..
Q.
\.
Co
~
,~
""
J;r
~~
--
--
-
o
,~
-2
Figure 6-3. Initial Undershoot Comparison of 74BCT2828 vs AM2928
6.1.5
c
o
m
40% REDUCTION OF INITIAL UNDERSHOOT
How Do I Get More Information
Each of the 2000 Bus Interface series devices provide the designer with reliable signals
without increasing package count and board real estate. The high drive and speed
complement Memory Management products for use in large memory and bus
applications. The onset of BiCMOS also brings a tremendous power savings which
can be appreciated in all designs. Below is a listing of the 2000 series offered. For
more information on these Bus Interface and Memory Management products, contact
your local Texas Instruments field sales representative or authorized distributor.
9-95
IOL (mAl
35
'BCT2828
10-bit Buffer/Driver
Inverting
'ALS2240
Octal Buffer/Driver
Inverting
15
'ALS2242
Octal Transceiver
Inverting
30
'ALS2244
Octal Buffer/Driver
True
30
'ALS2540
'ALS2541
Octal Buffer/Driver
Inverting
Octal Buffer/Driver
True
30
30
'AS2620
Octal Transceiver
Inverting
35
'AS2623
Octal Transceiver
True
35
'AS2640
Octal Transceiver
Inverting
35
'AS2645
Octal Transceiver
True
35
'C
"2n"
m
....
c)"
::::s
en
6.2 BiCMOS Bus Interface
6.2.1
Abstract
Bipolar and CMOS processes have their individual advantages. The advantages of
bipolar are speed and output drive current capability. The advantage of CMOS is
significantly lower power consumption with continually improving speed performance.
The merge of the two processes in order to use their individual advantages for optimal
product development was therefore a predictable technology transition.
S'"
-h
.3
o
....m
..
c)"
This portion of this report concerns the use of such a process, BiCMOS, and the
advantages provided in bus-interface logic. Ultimately, the system advantage gained
from the use of BiCMOS bus interface logic results in a 25% reduction of total system
power.
::::s
6.2.2
Introduction
Bus-interface logic requires very high output-drive currents of 48/64 mAo These
currents are required to drive high-capacitive loads and backplanes and to meet the
required specifications of established standards. Advanced speed performance is also
a necessity to allow the rapid transfer of information and to complement the
performance of other system components.
Excessive power consumption was the tradeoff that system designers were forced
to accept to achieve the desired output-drive current and speed performance. In an
average system, 30% of the total device supply current is required to support the
bus interface logic. The use of BiCMOS bus-interface logic can reduce the required
device supply current by more than 90%. This results in an overall system power
savings of more than 25%.
6.2.3
9-96
Reduction of Supply Current Demand Without Sacrificing Performance
The combination of bipolar and CMOS components makes the power savings a reality
without sacrificing required output drive current or speed performance. An examination
of bus-interface logic in system operation reveals that the devi'ce is either enabled
(active) or disabled. Since in bus configurations only one device is active at any given
time. the remaining devices tied to the bus are disabled. Therefore. for the majority
of the time. devices tied to the bus are in a disabled mode. Further evaluation reveals
that the currently available bipolar devices that are capable of meeting the
specifications required for bus-interface logic require supply currents ranging from
75 mA to 160 mA per device depending upon the function.
BiCMOS requires approximately 10 mA maximum (lCCZ) when disabled and further
reduces the active supply current demand by approximately 50% compared to
equivalent bipolar devices. Table 6-1 is a comparison of the SN 74BCT29861 and
AM29861 supply currents. Figure 6-4 illustrates typical switching performance and
disabled supply current demand between the two devices.
Table 6-1. SN74BCT29861/AM29861 ICC Comparison
SN74BCT29861
ICC
Supply current
Enable
=
Disable
(Vee
5.5 V @ 70 D e)
30 mA (Max)
c
7 mA (Max)
o
as
~
AM29861
tlee Supply current
(Vee = 5.5
v
.E
150 mA (Max)
@ 70 D e)
....o
t Advanced Micro Devices Bipolar Microprocessor Logic and
Interface 1985 Data Book. No breakout given for enable or disable
ICC·
.5
en
c
o
~
UI
as
c
:L 10
ell
Gi
c
c
.g
ell
CI
ell
Co
0
ct
CI)
CI
ell
Qj
98
7
6
5
4
.2
C.
..
VCC .. 5 V
TA - 25°C
CL - 50 pF
c.
'C
"2-
...n'0'
TI warrants performance of its semiconductor products to current
specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
such testing necessary to support this warranty. Unless mandated
by government requirements, specific testing of all parameters of each
device is not necessarily performed .
D)
:::J
en
5'
....
o
.3
In the absence of written agreement to the contrary, TI assumes no
liability for TI applications assistance, customer's product design, or
infringement of patents or copyrights of third parties by or arising from
use of semiconductor devices described herein. Nor does TI warrant
or represent that any license, either express or implied, is granted
under any patent right, copyright, or other intellectual property right
of TI covering or relating to any combination, machine, or process in
which such semiconductor devices might be or are used.
...0'
D)
:::J
Copyright © 1987, Texas Instruments Incorporated
9-102
Contents
Title
INTRODUCTION .............................................................................
STATIC COLUMN DECODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TYPICAL MEMORY CONTROLLER............................................................
TIMING CONTROLLER DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NORMAL ACCESS SEQUENCE ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HIGH-SPEED ACCESS SEQUENCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXTENDED ACCESS SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. NORMAL/EXTENDED REFRESH SEQUENCES ..................................................
SOFTWARE SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .
SUMMARY ..................................................................................
Page
3-85
3-85
3-87
3-87
3-89
3-89
3-90
3-90
3-94
3-94
c
o
Appendixes
A
B
ABEL
CUPL
1M
1M
Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Files ........................ '" ..................................... , . . . .... . . . . ..
3-95
3-101
"';:;
..E
ca
o
'too
.5
en
ABEL is a trademark of DATA 110
CUPL is a trademark of Personal CAD Systems, Inc.
C
o
"';:;
ca
"~
Q.
..
Co
---
CASl
OE
~
BANK 1
1 MEG X 32 BITS
(32) TMS4Cl027
W
I I I I
Wf--
··
AO
RAS2
CAS2
A9
·
\
AO
7
:9
r-f--r-f---
CAS2
W
I
··
\
AO
I
A19
BANK 2
1 MEG X 32 BITS
(32) TMS4Cl027
RAS2
~
BO
r"
\
··
\
AO
7
A9
A20
SELO
RAS3
RAS3
A21
SEll
CAS3
CAS3
I I I
BANK 3
1MEG X 32 BITS
(32) TMS4Cl027
W
DO • • • 031
Figure 2. 68020 Static Column Memory Controller
00 • • • 031
TYPICAL MEMORY CONTROLLER
Figure 2 shows a block diagram of a memory system
utilizing static column decode. The ALS63 10 is a new circuit
offered by Texas Instruments which detects if the present
row being accessed is the same as last row accessed. This
is the fundamental requirement for implementing static
column decode. Note that the row addresses from the 68020
'are used as the most significant bits (AIO-AI9) and the
column addresses are used as the least significant bits
(AO-A9). Figure 3 shows a block diagram of the ALS6310.
In circuit operation, when address strobe (AS) from
the 68020 is taken low, the present row (AIO-AI9) and bank
address (BO, B I) is clocked into the first register of the
ALS631O. The previous bank and row address, stored in the
first register, is clocked into the second register at the same
time. The two addresses are then compared to see if they
are equal. If they are equal, the high speed access output
(HSA) will be logically low. If not, HSA will be high.
The function of the PSG507 is to generate the required
memory timing control signals (RAS, CAS, etc.) for the
ALS6301 dynamic memory controller. The ALS6301 is
responsible for multiplexing row and column addresses into
DRAM. The ALS6301 is also capable of driving 4 banks
of 1M-byte memory.
Supporting the PSG507 is the ALS6300 refresh timer.
This device is responsible for generating a refresh request
signal (REFREQ) every 15.5 J1.s. The input select lines are
hardwired to match the microprocessor clock frequency. The
refresh complete input (RFC), resets the REFREQ signal
after the timing controller completes the refresh cycle.
TIMING CONTROLLER DETAILS
Figure 4 shows a typical flow chart for implementing
static column decode. As stated before, the PSG507 is
responsible for implementing the flow chart shown in
Figure 4. A breakdown of this flow chart reveals 9 states
(STO-ST8), associated with 5 different sequences. States STO,
STl, ST3, and ST4 are holding and transition states, leading
into the various sequences. The five possible sequences are
listed below.
ST2 Normal Access Sequence
ST5 Extended Access Sequence
ST6 High-Speed Access Sequence
ST7 Normal Refresh Sequence
ST8 Extended Refresh Sequence
Notice that the HSA signal from the ALS63 10 decides
if the timing controller will execute ST5, the Extended Access
Sequence, or ST6, the High-Speed Access Sequence. A brief
description of each sequence follows.
ca
E
~
2
.5
tn
C
CLKEN----~------------------------------~
o
ca
CLK--~~----------------------------~
PRESENT ADDRESS
REGISTER
c
o
.~
.~
.~
PREVIOUS ADDRESS
REGISTER
..
Q.
Co
MSEL-------------------------------------------------+--------------------------
"C
"2-
n'
D)
r+
CASI-------------------------------------------------+---------------------------
0'
:I
(I)
MADR
....5'
o
ssssssssssssss\\SX
COLUMN ADDR SS
I
.
3
I+-TA (CI-+!
I
00-031
D)
..
\S SSSSSSS \\ SSS SS SSSSSSSSSSX
VALID MEMORY DATA
r+
0'
:I
DSACK
,-------
w
Figure 6. High-Speed Access Cycle
EXTENDED ACCESS SEQUENCE
NORMAL/EXTENDED REFRESH SEQUENCES
The extended access sequence is executed if the
ALS63 10 detects a difference between the present, and last
row addresses .. This cycle is called extended because RAS
and CAS are presently low and both must be brought high to
strobe in the new row and column addresses. The precharge
time of the DRAM has to be met before taking RAS and CAS
low. From the timing diagram in Figure 7, it can be seen
that wait states of three clock cycles are generated when
executing this timing sequence.
In systems where sequential data is not the general rule,
it would be more efficient to execute only normal access
sequences, since this generates fewer wait states. The system
designer must understand what type of memory accesses will
be used. For example, the designer may want only to enter
the high-speed access portion of the flow chart when the
system is performing DMA access cycles.
Figures 8 and 9 show the timing diagrams for the
normal and extended refresh sequences. The refresh sequence
selected is a function of the present condition of RAS and
CAS. IfRAS and CAS are presently low, an extended refresh
cycle is performed. If RAS and CAS are presently high, a
normal refresh cycle is executed. At the end of each refresh
sequence" the controller checks to see if an access request
has been generated. If there has been an access request, the
controller will perform an access grant sequence at the end
of the refresh cycle before returning to normal process flow.
Referring back to Figure I, there is a maximum time
that RAS and CAS can be held low, tw(RL)P. For the
TMS4CI027, tw(RL)P must not exceed 100 J.tS. Since our
refresh timer forces a refresh cycle every 15.5 J.tS, tw(RL)P
cannot be violated. If the designer chooses to use a different
refresh scheme, then tw(RL)P must be considered.
9-110
ST3
CNTO
ST4
CNTO
ST4
CNT1
ST5
CNT2
ST5
CNT3
ST5
CNT4
ST5
CNT5
ST5
CNT7
ST5
CNT6
ST5
CNT8
ST5
CNT9
ST5
CNT10
ST3
CNTO
OSC
so
S1
S2
SW
SW
SW
SW
SW
SW
S3
S4
S5
r
SYSCLK--1
r
AS-..-J
ADX
\ \ \ \ \ \ \ \ \ \ \
X
xs:
VALID PRDCESSOR ADDRESS
HSA ______________________-1
I
I
I
R/IN
\\\\\\\\\\\\>C - - - - - - - - - - - - - - - - - -
I
VAUDiiiwDATA -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
=xs
I
I
I
RASI
I
I
I
I
MSEL
CASI ____________________________
MADRSTIl\\\\\\\S\\\\\X
~
COL
-A
ROW ADDRESS
XI
COL ADDRESS
I
I
I
1,4
I
00-031 \\\\ \\ \\ \ \ \ \ \ \ \ \ \ \ \ \\\\\\ \\\\\ \ \ \)
I
I..-TA ICA)J
DSACK-------------------------------------------------------------------------------
~
Figure 7. Extended Access Cycle
~
I
~
VALID MEMORY DATA
___________________Jr
,-------T
W
[RFC,RASI,MSEL,CASI,MCl, W,DSACK, STATE])
X, X, X ] -> [ H, H, L, H,- H , H,
X, X, 0 ] -> [ H, H, L, H, H ,H,
X, H, 0 ] -> [ H, H, L, H, H ,H,
X, X, 0 1 -> [ H, H, L, H, H ,H,
X, X, 0 1 -> [ H, L, L, H, H ,H,
X, X, 1 1 -> [ H, L, H, H, H ,H,
X, X, 2 1 -> [ H, L, H, L, H ,H,
X, X, 3 ] -> [ H, L, H, L, H ,L,
X, X, 4 ] -> [ H, L, H, L, H ,L,
X, X, 5 ] -> [ H, L, Ii, L, H ,H,
H
H
H
H
H
H
L
,
,
,
,
,
,
0
0
1
2
H
,
,
,
,
2
2
2
2
2
3
test vectors ' HOLDING STATE 4 WITH EXTENDED ACCESS REQUEST'
([OSC, RESET,A22, RW, REFREQ, AS, HSA, SYSCLK, COUNT] -> [RFC, RASI,MSEL,CASI,MCl, W,DSACK, STAT& ])
[clk,
H , H , X, H
, H, X, H, 0 ] -> [ H, L, H, L ,-H ,H, H
[clk,
H , L , X, X
, X, X, X, 0 1 -> [ H, L, H, L, H ,H, H
[clk,
H , X , X, X
, X, H, X, 1 ] -> [ H, H, L, H, H ,H, H
,
,
,
4
4
5
9-118
L
L
];
];
];
];
];
];
];
];
];
];
test vectors 'EXTENDED ACCESS'
(IOSC, RESET,A22, RW, REFREQ,AS, HSA, SYSCLK, COUNT]
, X,
Iclk,
H , X , X, X
, X,
H , X , X, X
Iclk,
, X,
H , X , X, X
Iclk,
H , X , X, X
, X,
Iclk,
, X,
Iclk,
H , X , X, X
, X,
H , X , X, X
Iclk,
, X,
Iclk,
H , X , X, X
, X,
Iclk,
H , X , X, X
[clk,
, X,
H , X , X, X
-> IRFC, RASI,MSEL,CASI,MCl, W,DSACK, STATEJ)
X , X , 2 ] -> I H , H , L , H , H ,H,
X , X , 3 ] -> I H , H , L , H , H ,H,
X , X , 4 ] -> I H , H , L , H , H ,H,
X , X , 5 ] -> I H , L , L , H , H ,H,
X , X , 6 ] -> I H , L , H , H , H ,H,
X , X , 7 ] -> I H , L , H , L , H ,H,
X , X , 8 ] -> I H , L , H , L , H ,L,
X , X , 9 ] -> I H , L , H , L , H ,L,
H
H
H
H
H
L
L
L
X , 10 ] -) [ H , L , H , L , H ,H, H
,
,
,
,
,
,
,
,
,
5
5
5
5
5
5
5
5
3
];
];
];
];
];
];
];
];
];
test vectors ' HOLDING STATE 4 WITH HIGH SPEED
(IOSC, RESET,A22, RW, REFREQ,AS, HSA, SYSCLK,COUNT]
[clk,
, H,
H , H , X, H
[clk,
H , L , X, X
, X,
[clk,
H , L , X, X
, X,
ACCESS REQUEST'
-> IRFC, RASI,MSEL, CASI,MCl, W,DSACK, STATEJ)
X , H , 0 ] -> [ H , L , H , L , H ,H, H
X , X , 0 ] -> I H , L , H , L , H ,H, H
L , X , 1 ] -) [ H , L , H , L , H ,H, L
,
,
,
4
4
6
];
];
];
,
,
,
6
6
3
];
];
];
X,
test vectors 'HIGH SPEED ACCESS'
([OSC,RESET,A22, RW, REFREQ,AS, HSA, SYSCLK,COUNT] -> [RFC, RASI,MSEL, CASI,MCl, W,DSACK, STATEJ)
[clk,
, X, X , X , 2 ] -) I H , L , H , L , H ,L, L
H , X , X, X
[clk,
, X, X , X , 3 ] -> I H , L , H , L , H ,L, L
H , X , X, X
[clk,
, X, X , X , 4 ] -> I H , L , H , L , H ,H, H
H , X , X, X
test vectors 'NON-MEMORY ACCESS FOLLOWED BY REFRESH REQUEST'
([OSC,RESET,A22, RW, REFREQ,AS, HSA, SYSCLK, COUNT] -) [RFC,RASI,MSEL,CASI,MCl, W,DSACK, STATEJ)
[clk,
, H, X , H , 0 ] -> [ H , L , H , L , H ,H,
H , H , X, H
[clk,
, X, X , X , 0 ] -> [ H , H , L , H , H ,H,
H , H , X, X
[clk,
, L, X , X , 0 ] -> [ H , H , L , H , H ,H,
H , X , X, H
[clk,
, X, X , L
H , X , X, H
0 ] -> [ H , H , L , H , H ,H,
[clk,
H , X , X, L
, X, X , X , 0 ] -> I H , H , L , H , H ,H,
test vectors 'NORMAL REFRESH CYCLE'
([OSC, RESET,A22, RH, REFREQ,AS, HSA, SYSCLK,COUNT]
[clk,
, L,
H , X , X, X
[clk,
, L,
H , X , X, X
[clk,
, L,
H , X , X, X
[clk,
, L,
H , X , X, X
H , X , X, X
Iclk,
, L,
, L,
H , X , X, H
Iclk,
, L,
H , X , X, X
Iclk,
H
H
H
H
H
-> IRFC,RASI,MSEL, CASI,MCl, W,DSACK, STATEJ)
X , X , 0 ] -> [ H , H , L , H , L ,H, H
X,
X,
X,
X,
X,
X,
X
X
X
X
X
X
,
,
,
,
,
,
1 I -) [ H , L , L , H , L ,H, H
2
3
4
5
6
]
]
]
]
]
->
->
->
->
->
I H,
I L,
[ L,
I H,
[ H,
L,
L,
L,
H,
H,
L,
L,
L,
L,
L,
H,
H,
H,
H,
H,
L ,H,
L ,H,
L ,H,
L ,H,
H ,H,
H
H
H
H
H
,
,
,
,
4
0
0
0
7
c
0
0';:;
..E
ca
....0
.5
];
];
];
];
];
en
c
0
0';:;
ca
o~
C.
Q.
,
,
,
,
,
,
,
7
7
7
7
7
7
0
«
];
];
];
];
];
];
];
9-119
test vectors 'NORMAL REFRESH CYCLE FOLLOWED BY ACCESS GRANT REQUEST'
([OSC, RESET,A22, RIi, REFREQ, AS, HSA, SYSCLK, COUNT) -> [RFC, RASI,MSEL, CASI,MC1, W,DSACK, STATE ))
[clk, H ,X, X, L
, X, X, X, 0 ) -> [ H ,
H, L, H, H ,H~ H
, L, X, X, 0 ) -> [ H ,
H, L, H, L ,H, H
[clk, H ,X, X, X
, L, X, X, 1 ) -> [ H ,
L, L, H, L ,H, H
[clk, H ,X, X, X
, H, X, X, 2 ) -> [ H ,
L, L, H, L ,H, H
[elk, H ,X, X, X
[elk, H ,X, X, X
, H, X, X, 3 ) -> [ L ,
L, L, H, L ,H, H
, L, X, X, 4 ) -> [ L ,
L, L, H, L ,H, H
[clk, H , X ,X, X
, L, X, X, 5 ) -> [ H ,
H, L, H, L ,H, H
[clk, H , L ,X, H
, L, X, X, 6 ) -> [ H ,
H, L, H, H ,H, H
[clk, H ,L, X, X
, L, X, X, 7 ) -> [ H ,
H, L, H, H ,H, H
[clk, H ,L, X, X
, L, X, X, 8 ) -> [ H ,
H, L, H, H ,H, H
[clk, H ,L, X, X
, L, X, X, 9 ) -> [ H ,
L, L, H, H , H, H
[elk, H , L ,X, X
, L, X, X, 10 ) -> [ H ,
L, H, H, H ,H, H
[elk, H , L , X, X
, L, X, X, 11 ) -> [ H ,
L, H, L, H ,H, L
[elk, H , L , X, X
, L, X, X, 12 ) -> [ H ,
L, H, L, H , L, L
[clk, H , L , X, X
, L, X, X, 13 ) -> [ H ,
L, H, L, H ,L, L
[clk, H , L , X, X
, L, X, X, 14 ) -> [ H ,
L, H, L, H ,H, H
[clk, H , L ,X, X
l>
'E..
"0
c:r
Q)
....
0'
;:,
en
5'
....
o...
3Q)
..
;:,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
3
test vectors 'HOLDING STATE 3 WITH EXTENDED REFRESH REQUEST'
([OSC, RESET,A22, RIi, REFREQ,AS, HSA, SYSCLK,COUNT) -> [RFC, RASI,MSEL,CASI,MC1, W,DSACK, STATE ))
[clk,
H ,X, X, H
, X, X, L, 0 ) -> [ H, L, H, L ,- H ,H, H
[clk,
H ,X, X, H
, L, X, X, 0 ) - > [ H, L, H, L, H ,H, H
[elk,
H ,X, X, L
, X, X, X, 0 ) -> [ H, L, H, L, H ,H, H
,
,
,
test vectors 'EXTENDED REFRESH CYCLE'
([OSC, RESET,A22, RW, REFREQ, AS, HSA, SYSCLK,COUNT)
[clk,
H ,X, X, X
, X,
[clk,
H , X ,X, X
, X,
[clk,
H , X ,X, X
, X,
[clk,
H ,X, X, X
, X,
,
,
,
,
....
0'
,
,
end SCDECODE
9-120
-> [RFC, RASI,MSEL,CASI,MC1, W,DSACK, STATE ))
X, X, 0 ) -> [ H, L, H, L ,-H ,H,
X, X, 1 ) -> [ H, H, L, H, H ,H,
X, X, 2 ) -> [ H, H, L, H, H ,H,
X, X, 3 ) -> [ H, H, L, H, H ,H,
H
H
H
H
)i
)i
)i
)i
)i
)i
)i
)i
)i
)i
)i
)i
)i
)i
)i
)i
)i
)i
)i
)i
APPENDIX B
NAME
PARTNO
DATE
REV
DES I GNER
COMPANY
ASSEHBL Y
LOCATION
SCDECODE;
T10004;
05/07/87 ;
01 ;
Breun i nger /Peprah;
Texas Instruments;
None ;
Dallas;
/""1111111""1111111111111"111111111"1111"1111111111111111111111111111111111111111/
/1
/1
/1
/1
/1
/1
/1
/1
/1
Static Column Decode
Th i sis an examp I e of how the PSG507 can be used to generate the
required memory timing control signals (RAS, CAS, HSEL etc) for static
column decode implementation using the ALS6301, ALS6310 and the ALS630
ALS6300, in a system environment.
1/
1/
1/
1/
1/
II"
1/
1/
1/
c::
/111111111111111111111111111111111111111111111111111111111111111111111111111111111111111/
/1
Allowable Target Device Types:
TEXAS INSTRUHENTS PSG507
o
1/
'.;:i
~
/111111 111111111111111111111111111111111111111111111111111111111111111111111111111111111/
E
...
J2
/" Inputs "/
pin
pin
pin
pin
pin
pin
pin
pin
1
2
3
4
5
6
7
18
OSC
RESET
A22
RW
REFREQ
AS
HSA
SYSCLK
Oscillator
System Reset - when low
/1 10llH - Hemory access
/1 Read / Write
Enab Ie
/1 Refresh Request
/' Addr Strobe - access request
/' High Speed Access
/1 System Clock - (OSC/2)
RFC
RASI
MSEL
CAS)
HC I
W
DSACK
/" Refresh Comp I ete
/" Row Address Strobe
.5
/1
1/
/1
1/
(I)
c::
o
1/
'.;:i
~
1/
,~
1/
c.
c.
"/
"/
'C
'2.
CNIHOLD I. s
5"
....
I»
0"
::::I
rn
:r
..3
0'
I»
....
: [C5 .. 0]
: [P3 .. 0]
'b'OOOO
'b'OOOI
'b'OOIO
'b'OOII
'b'OIOO
'b'OIOI
'b'OllO
'b'OIII
'b'IOOO
: !RESET
# ST2 & COUNT:'d'5
, ST4 & COUNT: 'd'O
# STS & COUNT:'d'IO
, ST6 & COUNT: 'd' 4
, ST1 & COUNT:'d'6 & (A22 & AGREQ)
t ST1 & COUNT: 'd' 14
, STB & COUNT:' d' 3;
/" CI ear counter when RESET I s low
I' and during transitions at the end
'" the indicated states and counts.
: ! RESET
• ST2 & COUNT:'d'S
• ST4 & COUNT:'d'O
# ST5 & COUNT:'d'IO
, ST6 & COUNT:'d'4
, ST1 & COUNT:'d'6 & (A22 & AGREQ)
, ST7 & COUNT:' d' 14
, STB & COUNT: 'd'3;
CNTHOLOI.r : STO & !REFREQ & RESET
, STi & !A22 & RESET
, sn & !REFREQ & RESET
# sn & REFREQ & AS
& SYSCLK & RESET;
0"
::::I
9-122
'/
'/
"/
/"
t /
/'
I'
/"
'/
"/
'/
I"
"/
/' Set count hold while clearing
/" the counters accord i n9 I y.
'/
'/
/"
/'
/'
/'
/'
/'
"/
'/
'/
'/
'/
'/
/'
/"
/'
/'
Reset
Reset
Reset
Reset
/" I State "ach i ne Equat ions I I /
sequence STATE {
present STO:
if(REFREQ & (!AS ,!SYSCLK))
if(REFREQ & AS & SYSCLK & RESET)
if ( ! REFREQ & RESET)
defaul t
next STO;
nextSTI;
next ST1;
next STO;
present STI:
if(COUNT:'d'O & !A22)
if(COUNT:'d'O & A22)
defau It
next ST2;
next STO;
next STI;
present ST2:
I" NOR"AL ACCESS CYCLE 'I
if(COUNT:'d'O) & RESET
if(COUNT: 'd' I)
if(COUNT:'d'2) & RESET
if(COUNT:'d'3) & RESET
if(COUNT: 'd'S)
defaul t
next
next
next
next
next
next
ST2
ST2
ST2
ST2
sn
ST2;
out
out
out
out
out
count
count
count
count
hold
hold
hold
hold
on
on
on
on
!RASI;
"SEL;
[!CAS!, !DSACK];
! w;
[W ,DSACK];
transition
transition
transition
transition
to
to
to
to
ST1
ST2
STB
S14
'/
'/
'/
'/
present S13:
/1 HOLDING STATE
1/
if{ !AS # !SYSCLK) & REFREQ & RESET
if{REFREQ & AS & SYSCLK & RESET)
if{ !REFREQ & RESET)
default
next
next
next
next
ST3;
S14;
ST8;
ST3;
present S14:
if{COUNT:'d'O)
if{COUNT: 'd'O)
if{COUNT: 'd' I)
if{COUNT: 'd'I)
defaul t
next
next
next
next
next
STO out [RASI,lHSEL,CASI1;
S14;
STS out [RASI,lHSEL,CASI1;
ST6 out !DSACK;
ST 4;
next
next
next
next
next
next
ST5 out
STS out
STS out
STS out
S13 out
STS;
& A22 & RESET
& !A22 & RESET
& HSA & RESET
& !HSA & RESET
present STS:
/1 EXTENDED ACCESS CYCLE
if{COUNT: 'd'S) & RESET
if{COUNT: 'd'6) & RESET
if{COUNT:'d'7) & RESET
if{COUNT:'d'8) & RESET
if(COUNT:'d'IO) & RESET
default
J /
lRASI;
HSEL;
[!CASI,!DSACK1;
lW;
[W,DSACK1;
c:
o
ca
"';:::;
present ST6:
/' HIGH SPEED ACCESS
'/
if{COUNT: 'd'2) & RESET
if{COUNT:'d'4)
default
...oE
next ST6 out ! W;
next S13 out [W,DSACK1;
next ST6;
present ST7:
/' NORMAL REFRESH CYCLE '/
if AS
if{COUNT: 'd'O) & RESET
if{COUNT:'d'I) & RESET
if{COUNT:'d'3) & RESET
if{COUNT: 'd'S)
if{COUNT: 'd'6) & (A22 # AGREQ)
if{COUNT: 'd'6) & !A22 & !AGREQ
if{COUNT:'d'9) & RESET
if{COUNT: 'd'IO) & RESET
if(COUNT: 'd'll) & RESET
if{COUNT:'d'I2) & RESET
if{COUNT: 'd'14)
default
'too
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ca
next
next
next
next
next
next
next
next
next
next
next
next
next
ST7 out
ST7 out
ST7 out
ST7 out
ST7 out
STO out
ST7 out
ST7 out
ST7 out
ST7 out
ST7 out
S13 out
ST7;
! AGREQ;
lHCU
lRASI;
! RFC;
[RfC,RASI);
HCU
HCU
!RASI;
HSEL;
[!CASI,lDSACKj;
!W;
[W, DSACK 1;
"~
..
C.
c.
'C
"2-
$msg" " j
$msg" " i
$msg"NORHAL REFRESH CYCLE FOLLOWED BY ACCESS GRANT REQUEST" i
$msg" " j
$msg"
------------------ INPUT ------------------ -------------- OUTPUT --------------- "
$msg"
OSC ,RESET, A22, RW, REFREQ, AS,HSA, SYSCLK, COUNT RFC,RASI ,HSEL,CASI ,HCI ,W,DSACK,STATE "
$msg"
---------------------------------------- --- ------------------- --- -- - ------------- "
C
X
0
X X
' 0'
L
H
"1"
C
X
X
0 X
' 0'
L
L
"1"
C
X
X
X
0 X
'I'
H L H
L
"1"
C
X
X
X
I X
'2 '
H L H
L
"7 "
C
X
X
I X
X
' 3'
L
H L H
"1"
X
' 4'
C
X
0 X
X
L
H L H
"7"
C
0
X
0 X
X
' 5'
H L H
L
"7"
C
0
X
'6'
0 X
X
H H H
L
"7"
C
0
X
0 X
X
' 7'
H H H
L
"7"
C
0
X
0 X
X
'6'
H H H
L
"7"
C
0
X
0 X
X
'9'
L
H H H
"7"
C
0
X
0 X
X ' 10'
H H H H
"7"
C
0 X X
X
'II'
L
"1"
C
0 X X
X
' 12'
L
"7"
C
0 X X
X
' 13'
L
"7"
C
0 X X
' 14'
X
L
"3"
-
cr
....
D)
0'
:::::s
en
:;
0'
...
3D)
....
..
0'
:::::s
$msg" • i
$msg" "i
$msg"HOLDING STATE 3 WITH EXTENDED REFRESH REQUEST" i
$msg" • i
$msg"
------------------ INPUT ------------------ -------------- OUTPUT --------------- "
$msg"
OSC ,RESET, A22, RW ,REFREQ,AS ,HSA,SYSCLK, COUNT RFC ,RASI, HSEL ,CASI ,HC I, W, DSACK, STATE "
$msg"
--------------------- ----- ---- - ---- -- - --- ------------------- - ------------- -- ----- - "
X X
'0 '
"3"
'0'
X X
"3"
X X
'0'
"6"
9-126
$msg" "j
$msg" "j
$msg"EXTENDED REfRESH CYCLE" i
$msg" "j
$msg"
------------------ INPUT ------------------ -------------- OUTPUT --------------- "
$msg"
OSC,RESET,A22,RW,REFREQ,AS,HSA,SYSCLK,COUNT RfC,RASI ,HSEL,CASI ,HCI ,W,DSACK,STATE "
------ -- -------- --- --------- ------- ------------- - - ------------- --------- ----- - "
$msg"
--
x
X
--
'0'
'1'
X
'2'
X
, 3'
"S"
"S"
"S"
"7"
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PLAN
DEFINE REQUIREMENTS
ESTABLISH BASELINE
UNDERSTAND NEEDS
DO
DESIGN RULES/PACKAGE CAPABILITY
DOCUMENT/AUDIT/CONTROL
THROUGH STANDARDS/SPe
SERVICE - ON-TIME DELIVERY. JIT
IJUST IN TIME). SHIP-TO-STOCK.
JOINT QUALIFICATION
CHECK
PROCESS ASSURANCE
MEASURE/ASSESS THROUGH
RELIABILITY TESTING
SUPPORT - FIELD THROUGH FACTORY
ACT
ANALYSISIIMPROVEMENT
PRODUCT/PROCESS IMPROVEMENT
VERIFY - FEEDBACK WITH CUSTOMER
ASSESSMENT
Figure 1. Total Quality Control
FROM NEGATIVE LOOP
TO POSITIVE LOOP
oc
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Figure 2. TQC Philosophy
Q.
:0
!.
S"
~
~"
IDENTIFY PROBLEMS AND
DATA COLLECTION
- PARETO OF DEFECTS
-
D
TRAINING
- SPe
- DESIGN OF
EXPERIMENTS
IDENTIFY SOURCE OF
VARIATION
- MULTI-VARIABLE
CHART
- FISH-BONE
Figure 3. Computer Aided Statistical Process Control
10-4
Wafer (slice) level quality control focuses on reduction of variability around target values (CPK) for key functionality parameters and controls the processes that affect
parameters. For example: Column access time (tCAC) is
a key DRAM parameter. One of the die manufacturing processes that affects tCAC is the photo etch. To reduce
variability of the target value of tCAC, we control
polysilicon width dimension at the photo etch process.
Wafer level reliability controls address process control of known reliability hazards. For example: Excessive
phosphorus use in die processing can lead to corrosion
defects in the finished device. Wafer level reliability controls require that phosphorus level control is built into the
manufacturing process and that action is prescribed for out
of control material. Other wafer level reliability controls
are shown.
Table 2. Major Assembly Steps Using SPC/SQC t
PLASTIC DEVICE ASSEMBLY
PROCESS
CONTROL PARAMETER
MOUNT
% COVERAGE OF EPOXY
BOND
BOND STRENGTH
MOLD
TEMPERATURE AND MOLDING
PARAMETERS
TRIM/FORM
LEAD DEFLECTION (DIPt
CERAMIC DEVICE ASSEMBLY
BOND
BOND STRENGTH
SEAL
SEAL FURNACE
TEMPERATURE
Table 1. Wafer Reliability Controls
tStatistical Process Control/Statistical Quality Control
PARAMETER
METAL
PROTECTIVE
OVERCOAT
CORROSION
GATE OXIDE
INTEGRITY
CONTROL
ELECTROMIGRATION TESTING
GRAIN SIZE, SILICON NODULE
MONITOR
STEP COVERAGE/METAL
NECKING MONITOR
STRESS INDUCED METAL
VOID TESTING
P.O. INTEGRITY
STRESS TESTING
THICKNESS MONITOR
REFRACTION
% PHOSPHORUS IN MULTILEVEL OXIDE MONITOR
Table 3. MOS Memory Assembly Level Reliability
Controls
PARAMETER
P.O. INTEGRITY
CHIP/CRACK
BOND INTEGRITY
BREAKDOWN VOLTAGE
Device Assembly Control
TI has also implemented assembly level reliability
controls and SPC at critical assembly points (see Table
2) to ensure highly reliable device packaging. Each parameter has certain controls performed at appropriate frequencies to ensure that assembly processing is progressing
at qualified levels. Controls may be added or reduced after
extensive testing has been performed and results studied
carefully to preclude reliability problem introduction into
the assembly process. The parameters and controls are
shown in Table 3.
CONTROL
CONTACTLESS WAFER MOUNT
ON TAPE DIE MOUNT SYSTEM
MOLD COMPOUND PARAMETERS
~
VISUAL INSPECTION
TEMP CYCLE
SAW BLADE CONDITIONS
. POKER PIN HEIGHT
WET ETCH MONITOR (EPROM)
:c
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a:
"C
C
BOND STRENGTH MONITOR
BOND PARAMETERS
BAKE/BOND PULL MONITOR
CAPILLARY CHANGE
PACKAGE
INTEGRITY
VISUAL INSPECTION
MOLD PRESS PARAMETERS
(PLASTICt
X-RA Y INSPECTION (PLASTIC)
TRIM/FORM (PLASTIC)
PACKAGE SEAL (CERAMIC)
TEMP CYCLE (CERAMIC)
HERMETICITY MONITOR
(CERAMICt
DIE MOUNT
INTEGRITY
DIE-SHEAR MONITOR
CENTRIFUGE MONITOR
X-RAY INSPECT
LEADFRAME POLYIMIDE
PATTERN INSPECT
PICK-UP ARM FORCE
CONTAMINATION
VISUAL INSPECTION
CO
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10-5
C. Product Assessment/Improvement
Reliability Control System
The MOS Memory reliability control system (Figure 4) provides closed loop system feedback resulting in
corrective actions and ongoing product improvements.
Each new product, process, or major change to an existing product is internally qualified to industry leadership standards prior to production. This is followed by
eight weeks of monitoring during production ramp-up and
routine monitoring of more than 20,000 units a month once
product achieves final production release. In 1986, almost
one million memory devices were tested in all phases of
the reliability control system.
Reliability Development Issues
Soft Error. TI has been doing much work in all
phases of device development to minimize the effects of
soft error. Soft errors are caused by alpha particles emitted by the decay of small amounts of thorium and uranium
located in device packaging materials. TI maintains an aggressive program of evaluating new mold compounds to
ensure low alpha emissivity. Certain device design and
processing techniques are also applied to ensure a low soft
error rate. The goal of device design and processing is
to maximize the cell capacitance by employing an oxidenitride dielectric, as opposed to an oxide dielectric. Also,
the cell capacitance increases as the dielectric thickness
decreases. Testing has shown that the trench capacitor used
in dynamic RAMs has competitive soft error rates.
Channel Hot Electron. Channel hot electrons are
caused by impact ionization in the drain pinch-off region.
Electrons are accelerated toward the drain, collide with
positive ions and can be trapped in the gate oxide. This
trapped charge can change the characteristics of the transistor by raising the VT (threshold voltage). One method
employed to reduce the effects of hot electrons is to add
a lightly doped drain to reduce the electric field at the
gate. Testing for channel hot electrons is performed at a
low temperature (-lO°C) and a high drain voltage.
Latch-up. A CMOS device can latch up when the
gain of the parasitic PNP+ NPN transistors is greater
than 1. These PNP+ NPN transistors act as a silicon
controlled rectifier (SCR). If enough current flows through
the resistors, the transistors will turn on and the device
will latch up.
10-6
To control latch-up, the SCR gain must be controlled
to less than or equal to one. Methods for improving latchup immunity include using an epitaxial substrate, incorporating guard rings between P+ and N + diffusions, and
isolating P+ and N+ diffusions.
Latch-up testing is performed to ensure our CMOS
devices meet the minimum holding current for industry
standards.
.
D. Customer. Service
Quality, Reliability, Service, and the Cost of Ownership
The goal of Texas Instruments is to offer the best
quality, reliability, and service in the semiconductor industry. The foundation for this approach is to ship consistent quality. Consistent quality allows ship-to-stock
programs that foster the elimination of the customer's incoming inspection. Ship-to-stock quality, coupled with
100 % on-time delivery to narrow shipping windows mean
support of the customer's just-in-time manufucturing program. This combination of quality, reliability, and service
can be measured by a single index called "the cost of
ownership." The "cost of ownership" is defined as being
composed of the purchase price, quality adders (for incoming inspection imd board rework), inventory adders
(for maintenance of a buffer inventory for suppliers who
cannot meetjust-in-time delivery), in-house reliability adders (for system burn-in and rework), and field reliability adders (for warranty and post warranty field repairs).
For more information about the cost of ownership
concept, contact your local TI sales office and request the
brochure "Texas Instruments Lowers Semiconductor Cost
of Ownership," SSYB057.
Quality Improvement
Significant improvement in product quality has been
achieved through:
- Better definition of customer requirements.
- Greater emphasis on quality as a design criterion.
- Improved control of incoming materials.
- Intensive training of supervisors and operators.
- Extensive use of statistical process control.
- More automation of operations to minimize operator
related defects.
QUALIFICATION
PROOUCTION RAMP MONITOR
•
• Process baseline
• 3 - 6 Diffusion lots
• Up to 7000 units tested
TEST
TEST
DRAM
125 'C op. life
EFR*
85/85
Temp. cycle
Autoclave
Static bias/
Storage
Soft error
1100
2000
300
600
300
250
EPROM PROMt
300
1000
600
150
400
20
200
20
150
125'C op. life
85/85
Temp. cycle
Autoclave
200'C bake
2000
Data retention
Bake
EJectromigration
Package integrity
ESC
300
200
500
200
600
200
150
150
470
30
tOne·time programmable
*EFR IEarly Failure Ratel
DRAM - 125'C, 168 hr. op. life
EPROM, PROM - 200'C bake (PROM in
ceramic package)
FINAL PRODUCTION RELEASE
Up to 6400 units tested over 8 weeks
• Control each package/wafer fabrication site/
device combination
DRAM
(WEEKLYI
EPROM
(81-MONTHLYI
PROMt
(WEEKLYI
200
200
200
200
200
120
120
120
120
•
Scrap analysis
- Die test escapes
- Assembly defects
- Test marginality
•
Failure analysis studies
- Failure mechanism
200
200
• Ongoing reliability monitor of 125'C
op. life, data retention bake, temp. cycle,
85/85, autoclave, package integrity, and
internal cavity moisture
• Control limits set for each test
• Approximately 20,000 units tested each
month
• Early failure rate monitor (devices tested
monthlyl
TEST
DRAM
125'C op. life, 168 hr.
200'C bake, 44 hr.
25,000
EPROM
1000-2000
• DRAMs receive 100% burn-in and burn-
- Activation energy
in lot acceptance
tOne-tim a programmable
• EPROMs receive 100% 32 hr. data
retention bake and/or 32 hr. data
retention bake lot acceptance
Figure 4. Reliability Control System
As is demonstrated in Figure 5, MOS Memory EPROM
and DRAM outgoing quality has dramatically improved during the last few years. This significant improvement has occurred for all TI product lines and has been recognized
publicly by many of our customers, who have given TI more
than 70 major quality awards in the last three years. Included among these awards are Ford's Q-l award, the Naval Quality award, and the Deming Prize, which is Japan's most
prestigious quality award.
Reliability Improvement
Low IC failure rates are achieved through design-in
reliability, computer aided design, stringent qualification
testing prior to product release, routine monitoring of released
products, and an extensive failure mode tracking and feedback system for IC failures.
Since the early '80's, MOS Memory products have exhibited a device failure rate improvement trend which has
resulted in highly reliable memory devices (see Figure 6).
Since the memory device complexity also increases in an
ongoing manner, the failure rate by function has improved
at an even faster pace. TI continues to emphasize reliability
improvement as a major factor in reducing the total cost of
ownership for our customers. Reliability improvement is
reflected as a reduction in the expected field failures during
system lifetime.
Up-to-date quality and reliability data for MOS Mell\ory products is available. Please contact your local TI sales
office for information,
~
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a:
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C
ca
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ca:;,
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PPM
82
83
84
85
86
Figure 5. MOS Memory Quality Improvement
85
86
Figure 6. MOS Memory Reliability Improvement
10-7
10-8
General Information . .
Alternate Source Directories . .
Glossary/Timing Conventions/Data Sheet Structure
Dynamic RAMs . .
Dynamic RAM Modules . .
EPROMs/PROMs/EEPROMs . .
VLSI Memory Management Products . .
Military Products . .
Applications Information . .
Quality and Reliability
Logic Symbols
Mechanical Data
ESD Guidelines
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11-2
LOGIC SYMBOLS
EXPLANATION OF IEEE/IEC LOGIC SYMBOLS
FOR MEMORIES
1.
INTRODUCTION
The International Electrotechnical Commission (IEC) has been developing a very powerful symbolic language
that can show the relationship of each input of a digital logic circuit to each output without showing explicitly
the internal logic. At the heart of the system is dependency notation, which will be partially explained below.
The system was introduced in the USA in a rudimentary form in IEEE/ANSI Standard Y32. 14-1973. Lacking
at that time a complete development of dependency notation, it offered little more than a substitution
of rectangular shapes for the familiar distinctive shapes for representing the basic functions of AND, OR,
negation, etc. This is no longer the case.
The current standards are IEC Publication 617-12, 1983, and ANSI/IEEE Standard 91-1984. Most of the
data sheets in this data book include symbols prepared in accordance with these standards. The explanation
that follows is necessarily brief and greatly condensed from the explanation given in the standards. This
is not intended to be sufficient for people who will be developing symbols for new devices. It is primarily
intended to make possible the understanding of the symbols used in this book.
2.
EXPLANATION OF A TYPICAL SYMBOL FOR A STATIC MEMORY
The TMS27C256 symbol will be explained in detail. This symbol includes almost all the features found
in the PROMs and EPROMs.
The address inputs are arranged in the order of their assigned
binary weights and the range of addresses are shown as AW
where m is the decimal equivalent of the lowest address and n
TMS27C256
is the highest. The outputs affected by these addresses are
EPROM 32.768 x B
designated by the letter A, as data inputs would also be if the
(10)
AO
device were a RAM.
o '
(9)
Al
A2
A3
A4
A5
A6
A7
AB
A9
Al0
All
A12
A13
A14
(B)
(7)
(6)
(5)
(4)
(3)
(25)
(24)
(21)
(23)
(2)
(26)
(27)
(20)
(22)
A'V
A'V
>A-O-A'V
32.767 A 'V
A'V
A'V
A'V
A'V
~:WR OWN]
L:'- ~EN
(11)
(12)
(13)
(15)
a
a
a
(16)
(17)
(lB)
a
a
(19)
~
The polarity indicator t:::::,.. indicates that the external low level
causes the internal 1-state (the active or asserted state) at an
input or that the internal 1-state causes the external low level
at an output. The effect is similar to specifying positive logic and
using the negation symbol 0 .
The V symbols indicate three-state outputs. Three-state outputs
will always be controlled by an EN function. When EN stands
at its internal 1-state, the outputs are enabled; when EN stands
at its internal O-state, the outputs stand at their high-impedance
states. Sometimes the EN is a single input but in the illustrated
case, it is the output of a two-input AND gate. Both inputs (pins
20 and 22) are active low so if either one of them goes high,
the outputs will be disabled. The upper one of these two inputs
(pin 20) has another function. When nonstandard labels and
explanatory labels are used within symbols, they are enclosed
within square brackets. Here we find the label "[PWR DWN]".
This is intended to indicate that if pin 20 is high, the memory
will go to a low-power standby state.
TEXAS
l!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
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LOGIC SYMBOLS
3.
THE BASICS
Section 3.1 illustrates the most common building blocks that are used in constructing symbols for memories.
On the left are shown the symbols that specify the active levels for level-operated inputs, and the direction
of active transition for dynamic inputs.
It is preferred to show all input lines on the left and all output lines on the right. When an exception is
made to this left-to-right signal flow, an arrowhead is used to show the reverse signal flow.
Three symbols are shown that indicate three-state, open-drain, and open-source outputs. If none of these
are used, the output should be assumed to be totem-pole. The common control block is a point of placement
for inputs that affect an array of elements.
The drawings on the right define the three forms of dependency notation used in this book. At an input
(or output)that affects other inputs or outputs, a letter (G, C, or Z) is placed followed by a number. That
same number is placed at the affected inputs and outputs. The letter G indicates that an AND relationship
. exists; if the affecting input stands at the O-state, it imposes that O-state on the affected input or output.
The letter C indicates a control relationship, usually between a clock and a 0 (data) input. If the C input
stands at its O-state, the affected input is disabled. A D input is always an input to a storage element,
which it either sets to the 1-state or resets to the O-state, unless the D input is disabled to have no effect.
Z dependency is used to transfer a signal from one place in a symbol to another, for example from the
output at Z4 across to a terminal labeled" 4", or from the output at Z5 back to the" 5" where it serves
as an input with no terminal attached.
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11-4
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
LOGIC SYMBOLS
3.1 DIAGRAMATIC SUMMARY
INPUTS
~
G
(AND) DEPENDENCY
--
Active H (high)
Active L (low)
Active on L-to-H transition
Active on H-to-L transition
a
b
c
d
a
a
b
b
c
=c
d
d
ab
ac
ad
C(CONTROL) DEPENDENCY
INPUT /OUTPUT
a
-----rc; -
b---E
OUTPUTS
a-+-.......
b -...~CI
S [Set)
R [Reset)
Z (INTERCONNECTION) DEPENDENCY
ai--z:tz1
Active high
Active low*
3-State
a
5
Open-Circuit (L-type) t
en
Open-Circuit (H-type):j:
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til
COMMON CONTROL BLOCK
Co)
a
a
*The active-low indicator may be used in combination with
the 3-state and open-circuit indicators.
tL-types include N-channel open-drain and P-channel opensource outputs.
:l:H-types include P-channel open-drain and N-channel opensource outputs.
b
b
c
d
c
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....I
-
d
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
11-5
I
LOGIC SYMBOLS
4.
EXPLANATION OF A TYPICAL SYMBOL FOR A DYNAMIC MEMORY
4.1 THE TMS4C1024 SYMBOL
AO (5)
Al (6)
A2 (7)
The TMS4C1 024 symbol will be explained in detail for
each operating function. The assumption is made that
Sections 2 and 3 have been read and understood. While
this symbol is complex, so is the device it represents and
the symbol shows how the part will perform depending
on the sequence in which signals are applied.
RAM 1024K xl
20010/2100
(8)
A3(10)
A4 (11)
A5 (12)
A6 (13)
A7
A8 (14)
A9 (15)
A - -O
-1.048.575
20019/2109
C20[ROW]
G23/[REFRESH ROW]
24[PWR OWN]
C21[COL]
G24
23C22
~
______________ A \l
(17) Q
~-J
4.2 ADDRESSING
The symbol above makes use of an abbreviated form to show the multiplexed, latched addresses. The
blocks representing the address latches are implied but not shown.
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AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAS
CAS
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11-6
0
A
1,048,575
--
CAS
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C21
.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
0
A
1,048.575
LOGIC SYMBOLS
p>
When RAS goes low, it momentarily enables (through C20,
indicates a dynamic input) the 0 inputs
of the ten address registers 10 through 19. When CAS goes low, it momentarily enables (through C21)
the D inputs of the ten address registers 0 through 9. The outputs of the address registers are in 20 internal
address lines that select 1 of 1,048,576 cells.
4.3 REFRESH
RAS
--4
When RAS goes low, row refresh starts. It ends when RAS goes
. high. The other input signals required for refreshing are not
indicated by the symbol.
[REFRESH ROW]
4.4 POWER DOWN
CAS is ANDed with RAS (through G24) so when RAS and
CAS are both high, the device is powered down.
RAS --124 [PWR DWN]
CAS
-----t
G24
4.5 WRITE
By virtue of the AND relationship between CAS and W (explicitly
shown), when either one of these inputs goes low with the other
one and RAS already low (RAS is ANDed by G23),
the D input is momentarily enabled (through C22). In an "earlywrite" cycle it is W that goes low first; this causes the output
to remain off as explained below.
R A S § :. r 2 3
CAS
W
&
D
A,22D
23C22
4.6 READ
RAS ----~
W
.....----. 24EN
A'V
The ANDed result of RAS and W (produced by G23) is
clocked into a latch (through C21) at the instant CAS
goes low. This result will be a "1" if RAS is low and W
is high. The complement of CAS is shown to be ANDed
with the output of the latch (by G24 and 24). Therefore,
as long as CAS stays low, the output is enabled. In the
Q "early-write" cycle referred to above, a "0" was stored
in the latch by W being low when CAS went low, so
the output remained disabled.
en
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TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
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11-7
LOGIC SYMBOLS
5.
SYMBOLS FOR DYNAMIC RAM MODULES
A dynamic RAM module is created by attaching separate DRAMs in chip-carrier packages to a commor
substrate. The symbols for the composite memory thus created starts with the symbol for the origina
DRAM and is used with as little change as possible.
So far, two types of organizations have evolved. In the first, all like address and control inputs are connecte(
in parallel between the separate packages. Taking the TM4256EC4 as typical of this group, the symbo
starts with that of the TMS4256 with the qualifying symbol changed from "RAM 256K x 1" to "RAIV
256 x 4", and this becomes a common control block for an array of four input-output elements showr
below it.
In the second type of organization, of which the TM4256FC 1 is typical, most of the address and contro
lines are parallel connected, but some are brought out separately for each of the DRAM packages. Tc
maintain the recognizability of the original TMS4256 symbol, it has now been placed in the first elemen1
of the array. The empty rectangles located below the first element represents three other identical elements.
Now interconnection (Z) dependency has been used (see 2 and 2.1) to show how CAS, W, D, and the
address inputs connect to the first element, and since these inputs are located in the common contro
block, the connections apply equally to all the elements. The connections for RAS 1, RAS2, RAS3, anc
RAS4 apply only to the individual elements.
TM4256EC4
AO
A1
A2
A3
A4
AS
A6
A7
A8
TM4256FC1
(18)
AO
A1
(12)
(17)
A2
A3
A4
AS
A6
A7
A8
(13)
(8)
(7)
0
A 262.143
(14)
(6)
(1 )
CAS
iN
r-
0
CQ
n"
0
(10)
(16)
(15)
(5)
(18)
(20)
(6)
(11)
(12)
(13)
(8)
(7)
RAM 1024Kx1
Z30
Z31
Z32
Z33
Z34
Z35
Z36
Z37
_(19)
RAS
30
31
32
tJ)
'<
3
C'"
(5)
33
34
35
36
37
CAS
0
c;r
-
(3)
01
01
02
02
03
04
(20)
(21 )
03
04
2009/2100
0
A 262 ,143
RAs1
~~~~________~t1~(4~1 Q
11-8
TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443 •
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LOGIC SYMBOLS
The drawings below illustrate the handling of control lines that in the original symbol were broken up into
active-high and active-low functions. To make the combined symbol, the one of the two levels that seemed
most appropriate was chosen, and then bars were used over the dependency numbers if necessary. For
example, PWR DWN is an active-high function of pin 3, but it was decided that pin 3, RAS, should be
considered active low. The bar over the number 39 indicates that PWR DWN is a function of the complement
of Z39 (ANDed with the complement of 240 through G24), and the complement of active low is active high.
CAS (13)
RAS1
""""1 Z40
(3)
Z39
39
39
RAS1-(3_).....- - t
39
40
40
_(13)
CAS-...........&....;;=-I
40
Another modification of the basic symbols that can occur in either organization is illustrated by the
TM4256FL8. The TMS4256 has separate input and output pins. In the module, these have been connected
together to form a single I/O port. In the module symbol, this is indicated using 2 dependency to transfer
the output signal from the right side to the left side.
TM4256FL8
If you have questions on this Explanation
of IEEE/IEC Logic Symbols, please contact:
RAM 256Kx8
AO ;..;14~'----t2009/2100
A1 ;...15_'_--i
A2 ',,:-7,:-'- - - i
'8
A3 '
A41;...1...;.:1' - - - i
A5 1~1-:-,2'_--i
A6 1;...1...;.:4'_--i
A7 1~1..;..;5'_--f
AS 1;...1..;..;7'_--i
F.A. Mann, MS49
Texas Instruments Incorporated
P.O. Box 225012
Dallas, Texas 75265
Telephone (214) 995-2659
o
A 262.143
en
"0
IEEE Standards may be purchased from:
Institute of Electrical and Electronics Engineers, Inc.
345 East 47th Street
New York, N.Y. 10017
International Electrotechnical Commission (lEC)
publications may be purchased from:
23C22
American National Standards Institute, Inc.
1430 Broadway
New York, N.Y. 10018
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TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
11-9
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(i)
11-10
General Information
Alternate Source Directories ; - .
Glossary/Timing Conventions/Data Sheet Structure
Dynamic RAMs
Dynamic RAM Modules
EPROMs/PROMs/EEPROMs
am
VLSI Memory Management Products . .
Military Products . .
Applications Information
Quality and Reliability
Logic Symbols
Mechanical Data
ESD Guidelines
12-2
MECHANICAL DATA
MOS MEMORY PRODUCTS-COMMERCIAL
SOO-mil cerpak (J suffix)
I--------A--------i
2.29 (0.090)
1.53 (0.060)
INDEX ----...
~----t--+-
B
C
5.21 (0.
4.19(1'
5.08 (0.200)
3.81 (0.0150)
0.457 (0.018)
~
MINL
0.56 (0.022)
0.36 (0.014)
j
L
I'
fl
J
L
0.305 (0.012)-\r0.203 (0.008)
18.29 (0.720)
16.36 (0.644)
2.79 (0.110)
2.29 (0.090)
,
I
-------l
MIN
~
24
28
(MAX)
15,75
(0.620)
15,75
(0.620)
(MIN)
14,99
(0.590)
32,13
(1.265)
14,99
(0.590)
37,21
(1.465)
31,37
(1.235)
13,74
(0.541)
36,45
(1.435)
13,74
(0.541)
C
12,67
(0.499)
12,90
(0.508)
1267
(0.499)
17,02
(0.670)
..c
12,50
(0.492)
16,51
(0.650)
DIM
A
B
(MAX)
(MIN)
C
(MAX)
(MIN)
0
(MAX)
(MIN)
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
....caca
caCJ
'2
ca
CJ
CD
-
~
12-3
I
MECHANICAL DATA
MOS MEMORY PRODUCTS-COMMERCIAL
GOO-mil cerdip (J suffix)
2.29 10.090)
1.5310.060)
c
0.457 10.018)
MIN
J
LENS PROTRUSION
4.45 10.175)
3.56 10.140)
0.55910.022)
0.35610.014)
-ll
0.25410.010) MAX
5.08 10.200)
3.81 10.150)
J
2.7910.110)
2.29iQ.09oi
DIM
~
A
B
C
32
40
WIDE
NARR
WIDE
NARR
WIDE
NARR
WIDE
(MAX)
15,85
(0.624)
15,85
(0.624)
15,85
(0.624)
15,85
(0.624)
15,85
(0.624)
15,85
(0.624)
15,85
(0.624)
15,85
(0.624)
(MIN)
14,99
(0.590)
32,13
(1.265)
14,99
(0.590)
32,13
(1.265)
14,99
(0.590)
37,21
(1.465)
14,99
(0.590)
37,21
(1.465)
14,99
(0.590)
42,37
(1.668)
14,99
(0.590)
42,37
(1.668)
14,99
(0.590)
52,53
(2.068)
14,99
(0.590)
52,53
(2.068)
31,37
(1.235)
13,74
(0.541)
31,37
(1.235)
15,19
(0.598)
36,45
(1.435)
13,74
(0.541)
36,45
(1.435)
15,19
(0.598)
41,45
(1.632)
13,74
(0.541)
41,45
(1.632)
15,19
(0.598)
51,61
(2.032)
13,74
(0.541)
51,61
(2.032)
15,19
(0.598)
13,06
(0.514)
14,50
(0.571)
13,06
(0.514)
14,50
(0.571)
13,06
(0.514)
14,50
(0.571)
13,06
(0.514)
14,50
(0.571)
(MAX)
(MIN)
3:
28
24
NARR
(MAX)
CD
(")
:::r
(MIN)
m
::::s
c=)'
et
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
cm
r+
m
12-4
TEXAS
-I/}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
MECHANICAL DATA
MOS MEMORY PRODUCTS-COMMERCIAL
300-mil cerdip (J, JT suffixes)
32.00 (1.26)
1------ ~31:::-.5=:0:-:(~1.~247.)-------I
2.29 (0.090)
1.53 (0.060)
I--_ _ _Cl+_ 8.05 (0.317)
MAX
7.90 (0.311)
0.457 (0.018)
MIN
J
0.457 (0.018)
LENS PROTRUSION
4.45 (0.175)
3.56 (0.140)
TYP-H--2.79 (0.110)
2.29 (0.090)
0.254 (0.010) MAX
J
U
10.0310.39.
9.27 (0.365)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
....caca
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TEXAS
-I!}
INSTRUMENTS
POST OFFice BOX 1443 •
HOUSTON, TeXAS 77001
12-5
MECHANICAL DATA
MOS MEMORY PRODUCTS-COMMERCIAL
plastic packages (N suffix)
~----------BMAX----------~·~I
~
EITHER
OR BOTH ...,....-----.1
INDEX MARKS
CMAX
~-----If------I~
t=M~X:j
~
~i
~
5
fi_O_,5_0_8_(0_.0_2_0_I_M_IN__________,O_8_(_0_.2_0_01_M_A,.X__-+
-SEATING PlANE
~:~~: :~:~~:: -.J~
t
0,533 (0.021IjL
0,381 (0.0151
JL
o MIN
PIN SPACING
2,54 (0.1001 NOM
1,78 (0.0701 MAX
0,838 (0.0331 NOM
~
DIM
-
16
18
20
22
24
24
24
28
32
40
A
(MAXI
8,26
(0.3251
8,26
(0.3251
8,26
(0.3251
10,80
(0.4251
7,62
(0.3001
10,80
(0.4251
15,88
(0.6251
15,88
(0.6251
15,88
(0.6251
15,49
(0.6101
B
(MAXI
22,10
(0.8701
23,37
(0.9201
27,18
(1.0701
28,45
(1.1201
31,75
(1.2521
31,04
(1.2221
32,26
(1.2701
36,83
(1.4501
41,94
(1.6511
53,09
(2.0901
C
(MAXI
6,86
(0.2701
6,86
(0.2701
6,86
(0.2701
9,02
(0.3551
6,60
(0.2601
9,14
(0.3601
13,97
(0.5501
13,97
(0.5501
13,97
(0.5501
13,97
(0.5501
D
(MINI
3,18
(0.1251
2,921
(0.1151
2,92
(0.1151
3,18
(0.1251
3,30
(0.1301
3,18
(0.1251
2,92
(0.1151
2,92
(0.1151
3,18
(0.1251
3,18
(0.1251
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
12-6
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MECHANICAL DATA
MOS MEMORY PRODUCTS-COMMERCIAL
24-pin 300-mil plastic dual-in-line package (N, NT suffixes)
31.BO (1.252)
31.69 (1.248)
f
INDEX
6.60 (0.260)
6.55 (0.258)
i 2~3001 r O.60810'O;:~1
~TT""""""'TT'-~~~
~::~:
7••
~_S~~~G-1~=t
-Jl.-0.254(0.010)TYP
j /..,
JL
1.91 (0.075) TYP
3.30 (0.130)
TYP
2.54 (0.100) TYP
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
12-7
MECHANICAL DATA
MOS MEMORY PRODUCTS-COMMERCIAL
zig-zag plastic package (SO suffix)
.....- - - - - - - B
2,90 (0.114)
-----------4
2,70 (0.110)1
:..-tI"':--T"
-J I--
(0.02~
I
0,610
0.406 (0.0162...\
L
1,52 (0.059)
1,02 (0.040)
PIN 1
LEAD THICKNESS: 2,59 (0.012)
2,49 (0.008)
PIN N
DIM
~
16
24
28
A
7,00 (0.276)
680 (0.268)
8,74 (0.344) MAX
6,09 (0.342) NOM
B
20,70 (0.815)
2030 (0.799)
31,29 (1.232) MAX
36,07 (1.420) NOM
C (MAX)
8,26 (0.325)
10,16 (0.400)
10,16 (0.400)
D
2,79 (0.110)
229 (0.0901
2,64 (0.104)
244 (0.096)
2,64 (0.104)
244 (0.096)
E
3,30 (0.130)
3,00 (0.120)
3,25 (0.128)
2,95 (0.116)
3,25 (0.128)
2,95 (0.116)
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
12-8
TEXAS
lj}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MECHANICAL DATA
MOS MEMORY PRODUCTS-COMMERCIAL
plastic chip carrier packages
18-lead plastic chip carrier package (FM suffix)
:
:
:
:
:
·
i
F
I
7.26 (0.286)
r----------7,r---r~
11
10
9
8
0.737 (0.029)
13.38 (0.527)
13.13 (0.517)
12.55 (0.494)
'2'3l~·J
12
7
13
6
14
51
~ 0.660
(0.026)
Co_INR_~_E -\~ _ _ \_4~
1--:_:_____
SEATING PLANE
____
3.53 (0.139)
r--------tot- 3.38 (0.133)
3.28 (0.129)
17
3.12 (0.123)
1.24 (0.049)
1.09 (0.043)
0.20 (0.008) NOM
1.27 (0.050)
=£
TYP
TYP
11.76 (0.463)
11.61 (0.457)
0.53 (0.021)
0.43 (0.017)l
~--I'----------~~
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443 •
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12-9
MECHANICAL DATA
MOS MEMORY PRODUCTS-COMMERCIAL
32-lead plastic chip carrier package (FM suffix)
12.57 (0.495)
12.32 (0.485)
14
21
15.11 (0.595)
14.86 (0.585)
SEATING PLANE
356 (0.140)
3.35 (0.132)
1.24 (0.049)
1.09 (0.043)
0.20 (0.008)
NOM
:'\l-----,-It
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
12-10
TEXAS
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INSTRUMENTS
POST OFFice BOX 1443 •
HOUSTON. TeXAS 77001
MECHANICAL DATA
MOS MEMORY PRODUCTS-COMMERCIAL
28-lead plastic chip carrier package (FN suffix)
r
l
1.22 (0.048) x 45 0
r-rr.
iii iii
~q~:g~
q- q-
ee ee
10
~
~~
M
;~
ex)
1,07
~0.042]
1.19 (0.047)
3 2128272625
6
7
8
1.27 (0.050) T.P.
9
10
11
(See Note A)
19
12 1314.151617 18
I
8.38 (0.330)
7.87 (0.310)
12.57 (0.495)
12.32 (0.485)
(See Note B)
0.813 (0.032)
0.660 (0.026)
1r
~ 1,.2 ]0.060] MIN
0.508 ]0.020]
1.36 (0.014)
--l~~
0," ]0.02.] MIN
...caca
LEAD DETAIL
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
C
ca
NOTES: A. Location of each pin is within 0.127 (0.005) of true position with respect to center pin on each side.
B. The lead contact points are planar within 0.101 (0.004).
(J
"2
ca
.c
(J
..
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~
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
1,2-11
MECHANICAL DATA
MOS MEMORY PRODUCTS-COMMERCIAL
20/26-lead plastic small outline J-Iead surface mount package (OJ suffix)
r.
1
17,22 (0.678) t
17.07 (0.672(
26 25 24 23 22
18
f7 Q~
14l
f
8,64 (0.340)
8,38 (0.330)
7,65 (0.301)t
,INDEX DOT
o
2,85 (0.112)
7.49 (0.295)
~
1,27 (0.050)
2,69 (0.106)
1,14 (0.045)
I
0,89 (0.035)
I
I
t------>~-------:----SEATING
' - - 1 ,02 (0.040)
0,76 (0.030)
L~0'050'
PLANE
3,76 (0.148)
TYP
3,25 (0.128)
IUI~R----......
ALL LINEAR DIMENSIONS ARE IN MILLlME'TERS AND PARENTHETICALLY IN INCHES
tPlastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0,125 (0.005).
12-12
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Cf.
MECHANICAL DATA
MOS MEMORY PRODUCTS-COMMERCIAL
28-lead plastic small outline J-Iead surface mount package (OJ suffix)
r - - - - 1 8 , 5 4 (0.730) NOM~
I~
~I
INDEX
/MARK
11,05 (0.435) NOM
..
10,16 (0.400) NOM
9,39 (0.370) NOM
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
....ccs
CCS
C
co
(.)
"2
ctI
.c
..
(.)
(1)
:E
I
I
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
12-13
MECHANICAL DATA
MOS MEMORY PRODUCTS-COMMERCIAL
22-pin C singJe-in-line package
I~·---------
56,13 (2.210)
55,63 (2.190)
5,08 (0.200)
----------~·I
MAX
l
CDDDD
11
... (0.443)
11,38
L
---I
I
1f'7.1..'2" MIN
PIN SPACING 2,54 (0.100) T.P.--t......l
(SEE NOTE A)
0,330 (0.013)
0,178 (0.007)
0,584 (0.023)
0.432 (0.017)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A:
Each pin centerline is located within 0.25 (0.010) of its true longitudinal position.
12-14
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MECHANICAL DATA
MOS MEMORY PRODUCTS-COMMERCIAL
24-pin AC single-in-line package
INDEX
~
_________________
=71~,~37~(2~.8~1~0~).
__________________~
70,87 (2.790)
5,71
(0.225)
MAX
11.45 (0.467)
r
"::.::,:J= J
MIN
LPIN 'PAC'NG 2,54'0,100' T,P.
(SEE NOTE A)
Jl
0,330 (0.013)
0,178 (0.007)
0,.8. '0.0231
0.432 (0.017)
ALL LINEAR DIMENSIONS ARE IN MIlliMETERS AND PARENTHETICALLY IN INCHES
NOTE A:
Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
..
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ca
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TEXAS
"J1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
12-15
MECHANICAL DATA
MOS MEMORY PRODUCTS-COMMERCIAL
30-pin L single-in-line package
5.08 (0.200)
MAX
1
78.99 (3.110)
78.49 (3.090)
0000000
c'17510.,25IMIN
JL
L
)
PIN SPACING 2.54 (0.100) T.P.
(SEE NOTE A)
0.330 (0.013)
0.178 (0.007)
0.584 (0.023)
0.432 (0.017)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A:
Each pin centerline is located within 0.25 (0.010) of its true longitudinal position.
30-pin U single-in-line package
5.08 (0.200)
MAX
....._ _ _ _ _ _ _ _ _ _ _ 89.15 (3.510) _ _ _ _ _ _ _ _ _......
88.65 (3.490)
r
r
16 52 (0 657)
O
1.:" 4 l
3!
V-(0~;~5)
DDDDDDDJDL L
1±f.
T
}I~~~l
...J l-
PIN SPACING 2.54(0.100) T.P .
(SEE NOTE A)
1.78(0.070) TYP
3.38 (0.133)TYP
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
. .NOTE A:
12-16
Each pin centerline is located within 0.25 (0.010) of its true longitudinal position.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TYP
1.37(0.054)
1.17 (0.046)
MECHANICAL DATA
MOS MEMORY PRODUCTS-COMMERCIAL
3D-pin AD singJe-in-line package (TMD24GAD8)
89.15 (3.510)
__
i-
5.33 (0.210)
-=~==~~~~~~~8=8.=6=5-(3~.4=9=0=)~====~====~===_~~1r
I
3.38 (0.133) TYP
DDDDDDCf
.
I
.
.
.
PIN SPACING 2.54 (0.100) T.P.
(SEE NOTE A)
~
.
II
--I ~ 1.78 (0.070)
.
.
Mt;
~
JO.•07]
20.19(0.793)
~
TYP
r
1.37 (0.054)
1.19 (0.047)
j
L
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
3D-pin AD singJe-in-line package (TMD24EAD9)
5.33 (0.210)
MAX
89.15 (3.510)
88.65 (3.490)
$DOJDDDDDD
LPIN SPACING 2.54 (0.100) T.J.
(SEE NOTE A)
L
1.78 (0.070) TYP
n
(0.125)
3.18
TYP
1.37 (0.054)
1.19 (0.047)
JL
...caca
C
caCJ
'2
ca
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
..c
..
CJ
NOTE A:
Each pin centerline is located within 0.25 (0.010) of its true longitudinal position.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
Q)
:E
12-17
12-18
MECHANICAL DATA
MOS MEMORY PRODUCTS-MILITARY
Military Packages
The packages offered by the Military Products Division of Texas Instruments Semiconductor Group are designed to
provide the most efficient and cost-effective method of meeting Military system requirements. Products are offered
in hermetic ceramic dual-in-line, ceramic flatpack, leadless ceramic chip carrier, leaded ceramic chip carrier, and
ceramic pin grid array packages. All packages conform to the mechanical outlines contained in Appendix C of
MIL-M-38S10 except for package types that are not included in that speCification. In the event of a conflict between
dimensions contained in MIL-M-38S10 Appendix C and other TI published mechanical outlines, MIL-M-38510 will
take precedence.
Physical dimensions of the packages not contained in MIL-M-38S10 Appendix C are contained in this document.
This document also includes packages that are not completely defined in MIL-M-38S10.
CERAMIC PACKAGES AVAILABLE
Package
Designator
GB.
Description
PGA
FO
Three-Layer Square LLCC - Non-JEOEC Pinouts
FG, FV
Three-Layer Rectangular LLCC - JEOEC Pinouts
FJ
Three-Layer Square "J" Formed LOCC
FK
Three Square LLCC - JEOEC Pinouts
J, JG, JT
Glass-Sealed COIP
JO
Side-Brazed COIP
HJ
"J" Formed Small Outline LOCC
HQ
Glass-Sealed Square LOCC
m
m
~
W,WA,WC,U
CPAK
C
caCJ
'2
m
.c
CJ
Q)
-
:2
-II}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
12-19
MECHANICAL DATA
MOS MEMORY PRODUCTS-MILITARY
The TI published mechanical outlines for a given package type may vary slightly from product to product. To
identify the detailed outline drawing for a particular product, refer to the specific data sheet for that product. There
will be detail outline subsets within a generic package category that will be identified as follows:
xx
\
YYY
Z
\
'------- Sp,,;f;, O,ti;oe Rev;,;oo
.
' - - - - - Number of Terminations
' - - - - - - - Basic Package Identifier
For example, there are two "FV" package outlines identified in this book:
Mechanical Outline
Description
FV018
18-Pad Leadless Ceramic Chip Carrier used for
SMJ4256-XXFV
18-Pad Leadless Ceramic Chip Carrier used for
SMJ4464-XXFV
FV018A
MIL-M-38S10 APPENDIX C OUTLINES
Ceramic Dual·ln·L1ne
Flat Package
Chip Carrier Pin Grid Array
Number
Leads/
Contacts
MIL
ID
TI
ID
Appendix C
Outline
8
P
JG
0-4
H
U
F-4
D,B
W,WA
F-2, F-3
F
W
F-5
10
14
C
J
0-1
16
E
J, JO
0-2
18
V
J, JO
0-6
20
R
J, JO
0-8
MIL
ID
TI
ID
S
Appendix C
Outline
F-9
MIL
ID
n
:::r
Appendix C
Outline
FG
C-10
FO,FK
C-2
FG
C-13A
FO,FK
C-4
28
FG
C-11
32
FG
C-12
W
2
20
s:
CD
TI
ID
24
L
JT
24
J
J,JO
0-3
J, JO
0-10
28
0-9
K
W
F-6
3
Q)
:I
c=r
!.
c
,...
40
Q
JO
0-5
Q)
Q)
12·20
44
FO, FJ
C-5, C-J4
68
FO, GB, FJ
C-7, P-BC, C-J5
84
FJ
C-J6
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MECHANICAL DATA
MOS MEMORY PRODUCTS-MILITARY
20-pin leaded ceramic chip carrier (HJ suffix)
E
I-
~~:~::~::~::3
-.:l
15.44 (0.608)
15.04 (0.592)
1.22 (0.048)
0.71 (0.028)
n
I
r
7.62 (0.300)
" '",. . ,. .'T'"T0"T.7. . .,6. . .,(r-0.r-01" 30_)_R_A_D_IU_S-r-,. . ,. .'T'"T"T" 'I-,- ~ 7,11
16.76 (0.660)
16.26 (0.640) .
2.01 (0.079)
1.40 (0.055)
£ £
1
"[3 0,3281
2.29 (0.090)
3.18 (0.125)
~j0701
2.67 (0.105)
t-r J
~L J
2.57(0.101)
8.59 (0.338)
.1
1.42 (0.056)
~
280I
TVP
4 PLCS
LO.562 (0.022)
0.302 (0.012)
RADIUS
1--- 7 •82 (0.308) ---!
£
6.86(0.270)
£
0.89 (0.035)
0.64 (0.025)
1.20 (0.045)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALV IN INCHES
...co
CO
C
caCJ
"2
CO
.c
..
CJ
Q)
~
"!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
12-21
12-22
MECHANICAL DATA
VLSI MEMORY MANAGEMENT PRODUCTS
D PLASTIC PACKAGE
(16-pin package used for illustration)
f
I-
6,20 (0.244) , - - - - F====::!::======::::!::!::::::!:::::!:==Y;
5,80 (0.228)
I
4,00 (0.157)
3.ii1iD.i5oi
*--~+;:::;:;:::;;=;::;:::;:::;:::;:;::;;Y
'"'''''' "~~"""""~
'."".''''
'.""'.'"''
):~~~~d~:::::~lc~~E~~J~~J~~J~~OJ'2~5~(=,,0~'_0;1~0~'
1~';,:~~JL~'.
-'--'-
PIN SPACING
1,27 (0.050)
~
-"'~
0,51 (0.020)
(See Note A)
~
8
14
16
A MIN
4,80
(0.189)
8,55
(0.337)
9,80
A MAX
5,00
(0.197)
8,74
10,00
(0.344)
(0.394)
DIM
(0.386)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A.
B.
C.
D.
Leads are within 0,25 (0.010) radius of true position at maximum material dimension.
Body dimensions do not include mold flash 0: protrusion.
Mold flash or protrusion shall not exceed 0,15 (0.006).
Lead tips to be planar within ± 0,051 (0.002) exclusive of solder.
co
+'
CO
C
C6
CJ
'2
CO
.c
..
CJ
Q)
::2:
I
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
12-23
MECHANICAL DATA
VLSI MEMORY MANAGEMENT PRODUCTS
20-PIN
ow
r
r-- ~!:~ :~::~::-----,
irm-A AA - AAAAI
10.6510.419)
10.1510.4001
20
11
7.5510.2971
'A'~Ir=G)~________________________~10~1
2.65 (0.104)
~r
70NOM
4 PLACES
""F:=J~
~I I
I
0.1010.004)
0.78510.031)
il.585iD.ii231
-
I
\4-
I
-
I I 0,49010.0191
\t-iiTsOiQ.Oi4i
-.j
I
I
1+-*-1.27 (0.050) TP
NOTES:
s:
CD
(')
::r
Q)
A.
B.
C.
D.
Body dimensions do not include mold flash or protrusion.
Mold flash or protrusion shall not exceed 0,15 (0.006).
Leads are within 0,25 (0.010) radius of true position at maximum material dimension.
Lead tips to be planar within ±O,051 (0.002) exclusive of solder.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
::::I
a"
!!.
c
Q)
,..
Q)
12-24
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
MECHANICAL DATA
VLSI MEMORY MANAGEMENT PRODUCTS
OW plastic "small outline" packages
ow
24-PIN
15'5(O'6101~
15,3 (0.6021
-
-
-
- - -
13
12
I::~:~:~::I
0,5 (0.021 X 45°
LI=-r-
q)
~
T
4° 14°
----:LI
7°NOM
. \ 4 PLACES
0,785 (0.0311
0,320 (0.0131
1,27 (0.0501
0,585 (0.0231
0,230 (0.0091
0,40 (0.0161
NOTES:
A.
B.
C.
D.
JJ)l
Body dimensions do not include mold flash or protrusion.
Mold flash or protrusion shall not exceed 0,15 (0.006).
Leads are within 0,25 (0.010) radius of true position at maximum material dimension.
Lead tips to be planar within ± 0,051 (0.002) exclusive of solder.
....caca
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
C
cau
"2
ca
.c
u
CD
:E
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
12-25
MECHANICAL DATA
VLSI MEMORY MANAGEMENT PRODUCTS
44-TERMINAL FD and FK
~-----------A------------~
FD AND FK PACKAGES
NO. OF
282726
2S
242322
21
20
19
TERMINALS
18
A
MAX
9.09
10.358)
9.09
(0.358)
28
11.23
10.442)
1'.63
10.458)
44
16.26
10.640)
18.78
10.739)
23.83
10.938)
28.83
11.135)
S2
68
84
C
B
MAX
20
MIN
8.69
(0.342)
MIN
1.63
10.064)
MAX
2.03
(0.080)
1.63
(0.064)
2.03
(0.080)
16.76
10.660)
11.63
10.458)
14.22
10.S60)
1.75
10.069)
3.05
10.120)
19.33
10.761)
24.43
10.962)
14.22
10.S60)
21.89
10.862)
2.08
10.082)
2.08
10.082)
3.0S
10.120)
3.05
10.120)
29.S9
11.16S)
27.0S
11.06S)
2.08
10.082)
3.0S
10.120)
INDEX CORNER
I+- .
IJ--L
0.64 100251-+1
0.3e 10.0151
LO.64 10.0251
0.3810.0151
0.63510.0251 T.YP."
.'
'.
DOBOOOG
fClDDDDDO
[
0.635 x 1.27
10.025 x 00501
TYPICAL
35 PLACES
(See Note AI
iJDDDDDEl
faGEHJOOQ
rHJDDEHJO
s:
0.71 1O.0281..!
0.56 10.0221
CD
I.-
(')
:::r
Q)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
:::s
(;'
e!.
c
Q)
..
NOTE A: The checkerboard pattern is aligned vertically with the contact pads and is symmetrical horizontally as shown; it is applicable
to some 44-terminal packages only.
....
Q)
12-26
TEXAS
.Jj}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
MECHANICAL DATA
VLSI MEMORY MANAGEMENT PRODUCTS
FK CERAMIC CHIP CARRIER
(28-terminal package shown)
CERAMIC CHIP CARRIERS
JEDEC
OUTLINE
DESIGNATION'
NO. OF
TERMINALS
MS004CB
20
MS004CC
28
A
B
MIN
MAX
MIN
MAX
8,69
103421
11,23
10.4421
9,09
10.3581
11,63
(0.4581
7,80
(0.3071
10,31
(0.4061
9,09
(03581
11,63
(0.4581
* All dimensions and notes for the specified JEDEC outline apply,
...co
CO
C
~
I
~
co
(,)
"2
2,03 (0.080)
CO
1,63 (0.064)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
.c
(,)
Q)
-
:JE
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
12-27
I
MECHANICAL DATA
VLSI MEMORY MANAGEMENT PRODUCTS
FN PLASTIC CHIP CARRIER
(28-terminal package used for illustration)
1,22 (0.048) X450
1,07 (0.042)
o
28
27
26
25
24
23
A
B
22
8
~::
21
20
19
12
\!;-
JEDEC
NO. OF
OUTLINE
TERMINALS
MO·047AA
20
M0047AB
28
M0047AC
44
MO·047AE
68
13
15
14
16
17
18
I
.~I' 0," 10.0101
B
(See Note A)
A
3 PLACES
R MAX
I
SEATING PLANE
(See Note C)
A
MIN
MAX
MIN
MAX
MIN
MAX
0,81 (o,032)--t--+I
9.78
10.03
8.89
9.04
7.87
8.38
0,66 (0.026)
10.3851
10.3951
10.3501
10.3561
10.3101
10.3301
12.32
12.57
11.43
11.58
10.41
10.92
10.4851
10.4951
10.4501
10.4561
10.4101
10.4301
17.40
17.65
16.51
16.66
15.49
16,00
106851
10.6951
10.6501
10.6301
25,27
24, I 3
10 6561
24,33
10 6101
25.02
23,11
23,62
10.9851
10 9951
10.9501
10.9561
10 9101
10.9301
~T
I
~ (0,060) MIN
I "l64 (0,025) MIN
I...i:.
I
0,51 (0.020) 4\ ~
0,36 (0.014)
LEAD DETAIL
All dimensions and notes for the specified JEDEC outline apply.
NOTES: A. Centerline of center pin each side is within 0,10 (0.004) of package centerline as determined by dimension B.
B. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side.
C. The lead contact points are planar within 0,10 (0.004).
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
12-28
TEXAS . .
INSTRUMENTS
POST CFFICE 80X 1443 •
HOUSTON, TEXAS 77001
MECHANICAL DATA
VLSI MEMORY MANAGEMENT PRODUCTS
NOTE: For the 14-, 16-, and 20-pin packages, the letter J is used by itself since these packages are available only in the 7,62 (0.300)
row spacing. For the 24-pin packages, if no second letter or row spacing is specified, the package is assumed to have 15,24 (0.600)
row spacing.
l4-PIN J CERAMIC
1.---19.94 (0.785)
19.18 (0.755)
I
f ::::::
I
Fall,W,thinJEDECTO·116and
".":oo,~o,_:::.'".""'~
I
@@
® ® @)G0
I
\I \I \I \I \I \I Q
7,87 (0310)
1+----o+--7.-11-(0:B~J (0.290)
0 CD 0 0 0 0 0
~
-1
1.27
~
8
5.08(0200)
MAX
-SEATING PLANE
105"
90'"
14 PLACES,.-l""036 (0 014)
020(0008)
14 PLACES
1,7810.070) MAX 14 PLACES
0.51 (0.020) MIN
(0050) NOM
3.30 (0 130)
MIN
--I
l.- I
2.54(0100)
1,78 (0070)
4 PLACES
~
0.58 (0.023) 14 PLACES
fe- 0.38 (0.015)
PIN SPACING 254 (0 100) T P
(See Note A)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
l6-PIN J CERAMIC
I.
19,94 ( 0 . 7 8 5 ) - 1
19.18 (0.755)
I
J
{f\
Ii
Ii
Ih ,~~?~;:.
lOS"
00000000
r
1,78 (0.070) MAX 16 PLACES
1r-!1III"'"1I!'"''IIr"''''III'..,....,.....,III''''I~ SE~~~S~T
- SEATING PLANE _ _-.'L--_-----,.--I r'
90'
16 PLACES
·~'".,,,,,~e~~~~:j
11r--+t--tt--tlt
~I-~:~~:~:~~::
j~
-I!]:,
16 PLACES
....coCO
0.6i2(~~~~)E~IN
C
0.58(0.023) 16 PLACES
0.38 (0.015)
CO
u
'2
I
~:~~ :~~~~: 4 PLACES
• For memories of 64 bits and up and a few MSIILSI products in Series 54174 and Series 54S174S
that are derived from memory circuit bars, this maximum is 7,62 (0.300). All other dimensions apply
without modification.
L-______
A_L_L_L_IN_E_A_R__D_I_M_E_N_S_IO__
N_S_A_R_E__IN__M_I_LL_I_M_E_T_E_R_S_A_N__
D_P_A_R_E_N_T_H_E_T_IC_A
__L_LY__IN__IN_C__
H_ES
______
CO
J:
U
CD
:E
~__________________~ .
.I
NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
I
TEXAS
-1!1
INSTRUMENTS
POST OFF)CE BOX 1443 •
HOUSTON. TEXAS 77001
12-29
MECHANICAL DATA
VLSI MEMORY MANAGEMENT PRODUCTS
J ceramic dual-in-line packages (continued)
r-
l8-PIN J CERAMIC
''''''~'''OM{~~~~~~~j
~----+H--~:~~:~:~~~:
-1
23,1 (0.910) M A X - - - 1
MAX lB PLACES
1,27 (0.050) NOM
l1\
105
SEATING'"
PLANE
90~
~\
---
t
3,30 (0.130)t
MIN
-.l~O,356(0.014)
lBPLACES
GLASS
SEALANT
5,O~~;00)
-:t,.-------u
0,203 (O.OOB)
lB PLACES
PIN SPACING
2,~4
-H
O,5B (0.023)
0,38 (0.015)
lB PLACES
(0.100)
(See Note A)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
20-PIN J CERAMIC
I
24,76 (0.975)
fooI
..t - - - - - - 23,62 (0.930)
Ii
1
~
~
-
' ' ' ' ' ' M{~::::::
Ii
s
-
90
20 PLACES
\I
-----I·~I
~:~~:~~~~:
7,62 (0.300)
6,22 (0.245)
!j
1,27 (0050) NOM
GLASS
SEALANT
S~~~~~G
MAX
-3-,30-(-'-:.-13-0).'..---...MIN
I
- y -_ _ _ _ _ _ _ _ _ _ _
0,36 (0.014)
-toI~O,20 (0.008)
y
•
0,58 (0.023)
0,38 (0.015)
20 PLACES
I
20 PLACES
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
12-30
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MECHANICAL DATA
VLSI MEMORY MANAGEMENT PRODUCTS
J ceramic dual-in-line packages (continued)
This is a hermetically sealed ceramic package with a metal cap and side-brazed tin-plated leads.
JD CERAMIC-SIDE BRAZE
-=---=--_-_---+1'1
bl4--N_ . -_ __B
M_AX
'DO;~ ~ A~ ~:.- .n
bJl D [J+
~
I0.51(0.~20m'M'NvWJlArJ'm ·
~
OR NUM"',
G)---------------------
,, MAX -01
~I
-.j
1+-2.54 (0 100) NOM
j
~~~eS~:~I~~
~
DIM
A +0,51 (+0.020)
-0,25 (-0.010)
B (MAX)
C (NOM)
~
DIM
3.'." m, M'N
*
0.53 (0.021)
0.38 (0.015)
16
18
20
22
24
7,62
7,62
7,62
7,62
7,62
(0.300)
(0.300)
(0.300)
(0.3001
(0.300)
20,57
23,11
25,65
27,94
30,86
(0.810)
(0.910)
(1.010)
(1.100)
(1.215)
7,37
7,37
7,37
9,91
7,37
(0.290)
(0.290)
(0.290)
(0.390)
(0.290)
24
28
40
48
52
64
A +0,51 (+0.020)
15,24
15,24
15,24
15,24
15,24
22,86
-0,25 (-0.010)
(0,600)
(0.600)
(0.600)
(0.6001
(0.600)
(0.900)
B (MAX)
C (NOM)
31,8
36,8
52,1
62,2
67,3
82,6
(1.250)
(1,450)
(2.050)
(2.450)
(2.650)
(3.250)
15,0
15,0
15,0
15,0
15,0
22,6
(0.590)
(0.590)
(0.590)
(0.590)
(0.590)
(0.890)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
12-31
MECHANICAL DATA
VLSI MEMORY MANAGEMENT PRODUCTS
N plastic dual-in-line packages
r
16-PIN N
19,8 (0.780) MAX
-1
~@@@@@®®
::l~I~:, ':~:~~~ ~:i
'itoe---------+-'
:::::J
00000000
2,0(0.080) NOM
--i 1--1,78 (0.070) MAX 16 PLACES
..L
O'51iO'020i~1
MIN
t
:--r't.0,25 (0,010) NOM
5,08 (0.200) MAX
~
~
--SEATING PLANE
105"
:90'
16 PLACES
~
U~
IL 0,36(0.014)
--I r- ~:~~~~~~
[
[
~
f 'I f 'I
UU
3,17 (0.125) MIN
_IL
--,
r-- O;!8~L~g~~i
~:~~ :~:~~:
(Soe Note B)
0,84 (0.033) MIN
12 PLACES
0,533(0.021)
(S .. Note B)
PIN SPACING 2,54 (0.100) T. p,
(See NoteA)
4 PLACES
Parts may be supplied in accordance
with the alternate side view at the
option of TI plants located in Europe.
In this case, the overall length of the
package i122.1 (0.8701 max.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES:
A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. For solder-dipped leads, this dimension applies from the lead tip to the standoff,
18-PIN N
7.62! 0,25
(0.300 ! 0.010)
1-----.,-++--6.99 (0.275) MAX
_i
..
--l
2,03 (0.080) NOM
-.::: 0,25 (0 010) NOM
-SEA TlNG PLANE
_1~O,279±O,076
~1(0011±0003)
18 PLACES
(S.. Not•• B and C)
L
J
1--1,78 (0.070) MAX 18 PLACES
'O'51(0020)~1
MIN
5,08 (02 00) MAX
L
,
1
3,17 (0.125) MIN
-
1,91 (0075)
023 (0 009)
PLACES
4
~
I-- 08198(~~~~)E~IN
~
---l1---0,457±0,Q76
(0018±0003)
18 PLACES
(S.. Note. B and C)
PIN SPACING 2,54 (0 100) T P
(S.. Not. A)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES:
12-32
A. Each pin centerline is located with 0,25 (0.010) of its true longitudinal position.
B, This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0,020) above seating
plane.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MECHANICAL DATA
VLSI MEMORY MANAGEMENT PRODUCTS
N plastic dual-in-line packages (continued)
20-PIN N
7,62 ± 0,25
(0.300 ± 0.010)
I f - - - - - - ~~:~~
2,0 (0.080) NOM
:~::~::-----+t
(See Note B)
8=t
1,91 (0'075)JI
1,02 (0.040)
4 PLACES
~I---....m
m
VIEW A
Parts may be supplied in accordance
with the alternate side view atthe
C
oPtion of TI. European-manufactured
parts may have pm 1 as shown in
caCJ
view A. Altarnate-side-view parts
manufactured outside of the USA
may have a maximum package length
of 26,1It.0501.
"2
m
NOTES:
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
~---------""
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
_I
.c
~
:2
A. Each pin centerline is located within 0,25 (0.0101 of its true longitudinal position.
B. For solder-dipped leads, this dimension applies from the lead tip to the standoff.
C. Parts may be supplied with a draft angle of 7 0 typical at the option of TI.
12-33
MECHANICAL DATA
VLSI MEMORY MANAGEMENT PRODUCTS
N plastic dual-in-line packages (continued)
24-PIN NT PLASTIC
~--------------~~:~g:~~~\--------------~
7,1 10.2801 MAX
I
--~
l11
2,010.0801 NOM
8000 CD CD 0 CD 0) 80 ®
0,38 10.0151
MIN
~
-.!I 10--1,7810.0701
I
1,1410.0451
~:::::~:::_M- - -I- 5,o~ !0~Oo_:---j~1
- x-1
-.j
lOS'
90'
24 PLACES
\
~
J\
0,3610.0141
. - - 0,2510.0101
24 PLACES
IS.e Note BI
T
4,0610.1601
3,17 10.1251
2,1610.0851
0,71 10.0281
L
I
r-1,14 10.0451 MIN
24 PLACES
I
~
-.J L
I
A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. For solder-dipped leads, this dimension applies from the lead tip to the standoff.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
12-34
0,53310.0211
r - 0,381 10.0151
24 PLACES
ISee Note BI
PIN SPACING 2,54 (0.1001 T.P.
ISee Note AI
4 PLACES
NOTES:
24 PLACES
~----~-~~------------------------~
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MECHANICAL DATA
VLSI MEMORY MANAGEMENT PRODUCTS
N plastic dual-in-line packages (continued)
24-PIN NW PLASTIC
r------
32,8 (1,290) M A X - - - - - - - - I
@@®@@@@@@@@@
14'~b~550)~
CD000®®0®®@@@
2,0 (0,080) NOM
H
~O,25 (0 DID) NOM
1"1,78 (0.070) MAX 24 PLACES
-SEATINGPLANE---.0,51 (0.020) MIN
24 PLACES
JL
I I
L~"
J
--I~
90 0,28 t 0,08
(0.01 I t 0.003)
24 PLACES
(See Note B)
-P
J-
L.-~( -----r
5,08 (0.200) MAX
);\
I
..-r--r
~
I
0,457 t 0,076
(0.018 t 0.003)
24 PLACES
(See Note B)
I
0,83 (0.033) MIN
24 PLACES
2,42 (0.095) MAX
4 PLACES
PIN SPACING 2,54 (0.100) T, p,
(S.e Note A)
3,17 (0.125) MIN
24 PLACES
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
2a-PIN N PLASTIC
~----36,6
\\4' (0 °o~~ ~ ~'~~3)
.
-.
16
(,)
-}-~mrnrnMJJ
l'"j ::::::::::::~NX
--.I \.-
"2
CO
.c
(,)
0,84 (0.033) MIN
127 + 051
(0 050 ~ 0'020)
0,46 ± 0,08
(0.018 ± 0.003)
PIN SPACING 2,54 (0.100) T.P.
(S.e Note A)
.
Q)
-.
1,52 (0.060) NOM
:2E
L-____A__
LL__
L_IN_E_A_R_D_I_M_E_N_S_IO
__
N_S_A_R_E__
IN__
M_IL_L_IM
__
ET_E_R_S__
A_N_D_P_A_R_E_N_T_H_E_T_IC_A_L_L_Y_I_N_I_N_C_H_E_S____-L____________________~IFI'
NOTES:
A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. For solder-dipped leads, this dimension applies from the lead tip to the standoff.
TEXAS
.J.!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
12-35
MECHANICAL DATA
VLSI MEMORY MANAGEMENT PRODUCTS
N plastic dual"in-Iine packages (continued)
40-PIN N PLASTIC
I'
'I
53.1 (2.0901 MAX
'n,~~~~~~~{:::::::::::::::::::
o
Ii
~
1524 + 0 25
Ii
1
I
,@
.''.-------------,----.
(0.600 ±- 0.0101 ~
0.51 (0.0201
t~'"':,::'.~1~""":;:;':-t~J
~jl~,::~~~:
tH~ :~.~~~:
PIN SPACING 2.54 (01001 TP
(See Not. AI
1.52 (0.0601 NOM
.
.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
48-PIN, 52-PIN, AND 64-PIN N PLASTIC
t=A:j
,,,,,~cl4----:-~
-==-BMAX~~:tll
\ c:
t~
(D-----------------------------+
PIN SPACING IS 2.54 (0.1001 T.P.
(5 •• Not. AI
s:
CD
:::r
I»
::s
e.
52
64
A ± 0,25 (0.010)
15,24 (0.600)
15,24 (0.600)
22,86 (0.900)
62,2 (2.45)
67,3 (2.65)
81,3 (3.20)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
..
C
I»
I»
48
BMAX
n'
...
~
DIM
C')
NOTE:
12-36
A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MECHANICAL DATA
IC SOCKETS
INTRODUCTION
Texas Instruments has developed solutions for today's high density packaging needs. The TI facility at Attleboro,
Massachusetts (one of the world's largest suppliers of multimetal systems) provides leading-edge technology
which, combined with reliable, high-volume, off-the-shelf interconnection products, allows TI to quickly meet
volume commercial applications.
.
During the last decade, TI has produced one of the largest IC socket families. TI's sockets include every type
and size socket in common use today and are available in a wide choice of contact materials and designs.
Our sockets are designed for:
•
•
o
easy and efficient hand assembly
compatibility with automatic assembly equipment
maximum performance and board density
This section provides information on the following types of IC socket products.
PRODUCTION SOCKETS
Plastic Leaded Chip Carrier
Single-in-Line Packages
Pin-Grid Arrays
Dual In-Line
Dual In-Line 0.070-inch spacing
Quad In-Line
TYPE
PLCC
SIP
PGA
DIP
Shrink Pack
QUIP
BURN-IN/TEST SOCKETS
Plastic Leaded Chip Carrier
Pin Grid Array
Small Outline
Dual In-Line
Dual In-Line 0.070-inch spacing
Small Outline
Quad
TYPE
PLCC
PGA
J Lead
DIP
Shrink Pack
Flat Pack
Flat Pack
Specially formulated alloys give the TI contact springs:
o
o
•
Low Contact Resistance
High Contact Strength (to stand up to repetitive insertions and withdrawals)
High normal forces assure gas-tight reliability
....caca
C
CO
u
A full line of reliable, readily available, low-cost interconnection systems means premium performance at an
economical price.
Additional information on these and other TI products, including pricing and delivery quotations, may be obtained
from your nearest authorized TI Distributor, TI Sales Representative or:
Texas Instruments Incorporated
Connector Systems Department, MS 14-3
Attleboro, Massachusetts 02703
"2
ca
.c
..
u
(1)
:2!:
Telephone: (617) 699-5242/5375
TELEX: 92-7708
TEXAS
lj}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
12-37
MECHANICAL DATA
IC SOCKETS
PLASTIC LEADED CHIP CARRIER
PERFORMANCE SPECIFICATIONS
DEVICE GUIDE
BARRIERS
Mechanical
Recommended PCB thickness range: 0.062 in to 0.092 in
Recommended PCB hole size range: 0.032 in to 0.042 in
Vibration: 15 G max
Shock: 100 G max
Insertion force: 0.59 Ibs per position typ
Withdrawal force: 0.25 Ibs per position typ
Normal force: 200 g min, 450 g typ
Wipe: 0.075 in min
Durability: 5 cycles min
Contact retention: 1.5 Ibs min
UNIQUE, HIGH
NORMAL FORCE
CONTACT
EASILY
AUTO INSERTE
CLOSED BOTTOM
DESIGN
Electrical
Current carrying capacity: 1 A per contact
Insulation resistance: 5000 MO min
Dielectric withstanding voltage: 1000 V ac rms min
Capacitance: 1 pF max
Environmental
Operating temperature:
Operating: - 40°C to 85 °C
Storage: - 40°C to 95 °C
Temperature cycling with humidity: will conform to final EIA
specifications
PART NUMBER SYSTEM
MATERIALS
Body - Ryton R-4 (40% glass) UL 94 V-O rating
Contacts - CDA 510 spring temper
Contact finish - 90/10 tinllead (200 /-tin - 400 /-tin) over
40 /-tin copper
Extraction tool available, consult factory
Contact factory for detailed information
CPR
~
12
~ ~ ? !
! ! !
14
15
11
18
"21
61
6S
63
61
68
66
64
62
60
5.
58
4
13
16
~o
..
"
0
0
57
56
XXX -
X -
1111
I
II
II
0 j
55
22
23
24
;50
26
28
30
32
!4
36
21
2'
31
~3
35
54
53
52
51
50
4.
46
41
46
38
0
40 !2
4S
!"
31
3.
41
43
X -
0
IContact surface 1 -tin/lead
plating
Contact spacing 1 - 0.050 in
Numbuof pos W44, 052, 068, 084)
Plated thru hole, solder tail
TI socket Series
Plastic leaded chip carrier
PLASTIC LEADED CHIP CARRIER CPR SERIES
10
PH
II
•
2.54
(0.100) TYP
II
0
0
II
68-Pin shown
NOTE: Socket electrical pin-out pattern represents component side
of P.C.B. layout. (TYP. counter clockwise numbering pinout system.)
.
2.54 (0.100)
TYP
12-38
Pos
A
B
C
44
21,43
(0.844)
17,78
(0.700)
12,70
(0.500)
52
23,98
(0.944)
20,32
(0.800)
15,24
(0.600)
68
29,06
(1.144)
25,40
(1.000)
20,32
(0.800)
84
34,14
(1.344)
30,48
(1.200)
25,40
(1.000)
Dimensions in parentheses are in inches
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
MECHANICAL DATA
IC SOCKETS
PlCC BURN·IN/TEST
PRODUCT FEATURES
Can be loaded by top actuated insertion or press-in
insertion, either manually or automatically
High reliability due to high pressure contact point
Open body and high stand-off design provide high efficiency
in heat dissipation
High durability up to 10,000 cycles
Compact design
PERFORMANCE SPECIFICATIONS
Mechanical
Accommodates IC leads per specific IC device
Recommended PCB thickness range: 0.062 in to 0.092 in
Recommended PCB hole size range: 0.032 in to 0.042 in
Durability: 10,000 cycles 10 m!l max contact resistance
change
Insertion force: Zero g
Withdrawal force: Zero g t
PART NUMBER SYSTEM
CPJ
XX
Electrical
Contact rating: 1 A per contact
Contact resistance: 20 m!l max initial
Insulation resistance: 1000 M!l per MIL-STD 202,
Method 302, Condition 8
Dielectric withstanding voltage: 500 V ac rms per
MIL-STD 202, Method 301
I
xx
xxx
X
l
L
B
Number
~f contacts
P,toh
A" 0050
Contact finish
33 = overall gold plate
Environmental
Thermal shock: 100 cycles, - 25 DC to + 150 DC
Temperature soak: 150 DC for 48 hours
Operating temperature: - 40 DC to + 1 50 DC
Material
AA = copper alloy
TI Burn-in PLCC series
MATERIALS
Body Contact
Plating+
nickel
ULTEM glass filled (UL 94 V-Oj
- copper alloy
- overall gold plate 4 JLin over min 70 JLin
plating
18 PIN FOOTPRINT SHOWN
t After IC is unlocked from the socket
+For additional plating options contact factory
For complete test report contact the factory
PLCC BURN-IN/TEST SOCKETS CPJ SERIES
...caca
Q
"i
(J
"2
ca
.c
SIZES: 18 PIN
22 PIN
u
CD
:z
-
1,27 (0.0501
L
5,08 (0.2001
12,90 (0.5071-1
Dimensions in parentheses are inches
Contact factory for detailed information
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
12-39
MECHANICAL DATA
IC SOCKETS
SINGLE·IN·L1NE PACKAGE SOCKETS
PERFORMANCE SPECIFICATIONS t
LEAD LESS
SINGLE-IN-L1NE
PACKAGE
(SIP) MODULES
Mechanical
Vibration: MIL-STD-202
Durability: 30 cycles
Insertion force: Zero g
Withdrawal force: Zero g:t:
Contact (normal) force: 200 g min
Contact retention force: 2 Ibs per circuit min
00;::----
AUTOMATIC
MODULE RETENTIOII
AND SUPPORT
HIGH TEMPERATURE
MOLDED BODY
Electrical
Contact rating: 1 A
Contact resistance: 30 mn max initial
Insulation resistance: 1000 Mn at 500 dc
Dielectric strength: 1500 V ac rms
Capacitance: 2 pF max
POLARIZINGI
MOUNTING POSl
ZERO INSERTION FORCE,
HIGH NORMAL FORCE CONTACT
tValues may vary due to test sequence and SIP module
configuration
~ After module is unlocked from the receptacle
For a complete test report, please contact factory
PART NUMBER SYSTEM
TS8X
xx xx
X
-xx - xx
I
Environmental
(20 mn max contact resistance change after all tests)
Operating and storage temperature: - 40°C to 100°C
Humidity: MIL-STD 202, Method 106D, 10 days
Temperature soak: 85°C for 160 hours
Thermal Shock: 5 cycles, - 40 °C to 85°C per
MIL-STD 202, Method 107E
Lvariations
00 - standard
product
Size
(number of
contacts per row)
Housing material
A - PES
MATERIALS
Body - PES polyether sulfone, glass filled, UL 94 V-O
Contact - Beryllium copper C17000; phosphor bronze alloy
CA510
Contact finishes - Post plate min 200 !tin tin/lead over min
50!tin nickel overall
Post plate min 30 !tin hard gold over min 75 !tin nickel overall
Contact base material/plating
01-C17000/30 I'in gold
02-CA510/30 I'in gold
03-C17000/200 I'in tin/lead
04-CA510/200 I'in tin/lead
For additional plating options contact the factory.
Configuration/row-to-row spacing
01 -single row/N/A
03-dual row/0.300 in
04-dual row/0.400 in
05-dual row/0.500 in
DUAL ROW VERTICAL
Series number denotes
0-0.100 in pitch, vertical mount
1 -0.100 in pitch, low-profile (25°) mount
Consult factory for availability of configurations, materials, and
sizes.
SINGLE ROW LOW PROFILE
Contact factory for detailed information
12-40
Dimensions in parentheses are in inches
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
MECHANICAL DATA
IC SOCKETS
HIGH DENSITY PIN GRID ARRAY
PERFORMANCE SPECIFICATIONS
Mechanical
Accommodates IC leads 0.015 in to 0.021 in diameter
Recommended PCB thickness range: 0.062 in to 0.092 in
Recommended PCB hole size range: 0.032 in to 0.042 in
Recommended hole grid pattern: 0.100 in ± 0.002 in each
direction
Vibration: 15 G, 10-2000 Hz per MIL-STD 1344A,
Method 2005.1 Test Condition III
Shock: 100 G, sawtooth waveform, 2 shocks each direction
per MIL-STD 202, Method 213, Test Condition I
Durability: 5 cycles, 10 m!l max contact resistance change
per MIL-STD 1344, Method 2016
Insertion force: 3.6 oz (102 g) per pin typ using 0.018 in
diameter test pin
Withdrawal force: 0.5 oz (14 g) per pin min using 0.018 in
diameter test pin
Electrical
Contact rating: 1 A per contact
Contact resistance: 20 m!l max initial
Insulation resistance: 1000 M!l at 500 V dc per
MIL-STD 1344, Method 3003.1
Dielectric withstanding voltage: 1000 V ac rms
per MIL-STD 1344, Method 3001.1
Capacitance: 1 pF max per MIL-STD 202, Method 305
/
WIDE-TAPERED
/.,__
ENTR'
~}:;ff''\f!-l
'~.J;
'T"
t
SIX.FlNGERED'~l
1'}:,1. 1.'
PRECISION
Inner contact tin/lead over
Outer sleeve tin/lead over
30 /-tin gold over 50 /-tin nickel or 100 /-tin
50 /-tin nickel
10 /-tin gold over 50 /-tin nickel or 50 /-tin
50 /-tin nickel
PART NUMBER SYSTEM
C
X
G XX -
XXX
X
X
~-
:in1ength
W~I~R~E~W~R~A~P-r~~~~~
Operating temperature: - 65 DC to 125 DC, gold; - 40 DC to
100 DC, tinllead
Corrosive atmosphere: 10 m!l max contact resistance
change when exposed to 22% ammonium sulfide for
4 hours
Gas tight: 10 m!l max contact resistance change when
exposed to nitric acid vapor for 1 hour
Temperature soak: 10 m!l max contact resistance change
when exposed to 105 DC temperature for 48 hours
3-0.510 long
Plating
Body Style and Orientation
Body - PBT polyester UL 94 V-O
On request, G 10/FR4 or Mylar film
Outer sleeve - Machined Brass (00-B-626)
Inner contact - Beryllium copper (00-C-530) heat treated
Plating: (specified by part number)
IT
,,,,,lL
@@@@@@@@@@@
@@@@@@@@@@@
@@@@@@@@@@@
-$-CflCfl@@@@@@®®
Insulator Size
9x9
10x10
11 x11
12x 12
13x 13
14x 14
15x15
16x 16
17x 17
18x 18
--l
1--2.54
(0.10/0.12)
(0.100) TYP NONCUMULATIVE
.c·I"'T"'1'""T"T""T"T'""I"'T"T"T"'T"T"T"",....,...,,...,...,....,...,...~
(0.14/0.18)~W WW WWWtr wwtr ~
~~033
2.67/3.61
(0.105/0.150)
....caca
BODY MATERIAL
G - Glass Filled Epoxy
P - PBT Polyester
C
cau
TI Socket
-@®®®®®®®®®®
®®@@@@@@@@@
@@@@@@@@@@@
@@@@@@@@@@@
3.6/4.6
Number of Pins
024 to 324
Overall Grid Size
5x5=05to 18x18=18
PIN GRID ARRAY
(0.05/0.08) TYP
Contact Loading Pattern
Pin
Grid
Array
MATERIALS
B
PRECISION
MACHINED
SLEEVE
INNER CONT.rr
Environmental
A
.
' 2000
Antistatic Magazine & Conductive Bag/Box
Antistatic Magazine & Antistatic Bag
B
"C
·S
~
C
2) Devices are to be categorized by their sensitivity
(J)
3) Devices are to be protected from ESD damage from receipt at incoming inspection through assembly, test and
W
shipment of completed equipment.
. .
13-3
APPLICABLE REFERENCE DOCUMENTS
The following reference documents (of latest issue) can provide additional information on ESD controls.
1)
2)
3)
4)
5)
6)
7)
MIL-M-3851O Microcircuits, General Specification
MIL-STD-883 Test Methods and Procedures for Microelectronics
MIL-S-19491 Semiconductor Devices, Packaging of
MIL-M-55565 Microcircuits, Packaging of
DOD-HDBK-263 Electrostatic Discharge Control Handbook for Protection
DOD-STD-1686 Electrostatic Discharge Control Program
N AVSEA SE 003-11-TRN -010 Electrostatic Discharge Training Manual
FACILITIES FOR STATIC-FREE WORK STATION
The minimum acceptable static-free work station shall consist of the work surface covered with an ESD protective material
attached to ground through a 1 MO ± 10 % resistor, an attached grounding wrist strap with integral 1 MO ± 10 % resistor
for each operator, and air ionizer(s) of sufficient capacity for each operator. The wrist strap shall be connected to the ESD
protective material. Ground shall utilize the standard building earth ground, refer to Figure 1. Conductive floor tile along
with conductive shoes may be used in lieu of the conductive wrist straps. The Site Safety Engineer must review and approve
all electrical connections at the static-free work station prior to its implementation.
Air ionizers shall be positioned so that the devices at the static-free work stations are within a 4-foot arc measured by
a vertical line from the face of the ionizer and 45 degrees on each side of this line.
General grounding requirements are to be in accordance with Table 1.
PERSONNEL
GROUNO STRAP
ESD PROTECTIVE
TRAYS, ETC.
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1'0./\/\
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ESD PROTECTIVE
TABLE TOP
A
IONIZER
OTHER
ELEC.
EQUIP.
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CHAIR
WITH GROUND
(OPTIONAL)
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ESD PROTECTIVE
FLOOR MAT
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All electrical equipment sitting on the conductive table top must be hard grounded but must be isolated from the conductive
table top.
NOTE: Earth ground is not computer ground or RF ground or any other limited type ground.
Figure 1. Static-Free Work Station
13-4
Table 1. General Grounding Requirements
Handling Equipment/Handtools
TREATED WITH ANTISTATIC SOLUTION
GROUNDED TO
OR MADE OF CONDUCTIVE MATERIAL
COMMON POINT
X
Metal Parts of Fixtures
X
and Tools/Storage Racks
Handling Trays/Tubes
X
Soldering Irons/Bath
X
Table Tops/Floor Mats
X
X
X Using Wrist Strap *
Personnel
·With 1 M[J ± 10% resistor
Usage of Antistatic Solution in Areas to Control the Generation of Static Charges
The use of antistatic chemicals (antistats) should be a supplemental part of an overall organized ESD program. Any antistatic
chemical application shall be considered as a means to reduce or eliminate static charge generation on nonconductive materials
in the manufacturing or storage areas.
The application of any antistatic chemical in a clean room of class 10,000 or less shall not be permitted. Accordingly,
any user of antistatic solutions must consider the following precautions:
1. Do not apply antistatic spray or solutions in any form to energized electrical parts, assemblies, panels, or equipment.
2. Do not perform antistatic chemical application~ in any area when bare chips, raw parts, packages, and/or personnel
are exposed to spray mists and evaporation vapors.
The need for initial application and frequency of reapplication can only be established through routine electrostatic voltage
measurements using an electrostatic voltmeter. The following durability schedule is a reasonable expectation.
1) Soft surfaces (carpet, fabric seats, foam padding, etc.): each 6 months or after cleaning, by spraying.
2) Hard abused surfaces (floors, table tops, tools, etc.): each week (or day for heavy use) and after cleaning, by
wiping or mopping.
3) Hard unabused surfaces (cabinets, walls, fixtures, etc.): each 6 months or annually and after cleaning, by wiping
or spraying.
4) Company-furnished and maintained clothing and smocks: after each cleaning, by spraying or adding antistatic
concentrate to final rinse water when cleaned.
The use of antistatic chemicals, their application, and compliance with all appropriate specifications, precautions, and
requirements shall be the responsibility of the Area Supervisor where antistatic chemicals are used.
ESD Labels and Signs in Work Areas
ESD caution signs at work stations and labels on static-sensitive parts and containers shall be consistent in color, symbols,
class, and voltage sensitivity identification, and appropriate instructions. Signs shall be posted at all work stations performing
any handling operations with static-sensitive items. These signs shall contain the following information.
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CAUTION
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STATIC CAN DAMAGE COMPONENTS
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Do not handle ESDS items unless grounding wrist strap is properly
worn and grounded. Do not let clothing or plain plastic materials
contact or come in close proximity to ESDS items.
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Labels shall be affixed to all containers containing static-sensitive items at a place readily visible and proper for the intended . .
purpose. Additionally, labels must be consistently placed on containers and packages at a standard location to eliminate
mishandling. Use only QC accepted and approved signs and labels to identify static-sensitive products and work areas. The
use of ESD signs and labels, and their information content shall be the responsibility of the Area Supervisor to assure consistency
and compatibility throughout the static-sensitive routing.
13-5
Relative Humidity Control
Since relative humidity has a significant impact on the generation of static electricity, when possible, the work area should
be maintained within the following relative humidity ranges: incoming/assembly/test/storage 50%-65% (ref. Ashrae, 55-74),
within ± 5 % to avoid static voltage monitor variations.
PREPARATION FOR WORKING AT STATIC-FREE WORK STATION
A work station with a conductive work surface connected to ground through a 1 MO ± 10 % resistor, a grounding wrist
strap with the ground wire connected to the conductive work surface, and an ionizer constitute a static-free work station
(Figure 42). An operator is properly grounded when the wrist strap is in snug (no slack) contact with the bare skin, usually
positioned on the left wrist for a right-handed operator. The wrist strap must be worn the entire time an operator is at a
static-free work station. The operator should first touch the grounded bench top before handling static-sensitive items. This
precaution should be observed in addition to wearing the grouding wrist strap. If possible, operators should avoid touching
leads or contacts even though grounded.
CAUTION
Personnel shall never be attached to ground without the presence
of the 1 MO ± 10% series resistor in the ground wire.
An operator's clothing should never make contact or come in close proximity with static sensitive items. They must
be especially careful to prevent any static-sensitive items (being handled) from touching their clothing. Long sleeves must
be rolled up or covered with antistatic sleeve protector banded to the bare wrist which shall "cage" the sleeve at least as
far up as the elbow. Only antistatic finger cots may be used when handling static-sensitive items.
Any person not properly prepared, while at or near the work station, shall not touch or come in close proximity with
any static-sensitive items. It is the responsibility of the operator and the Area Supervisor to ensure that the static-free work
area is clear of unnecessary static hazards, including such personal items as plastic coated cups or wrappers, plastic cosmetic
bottles or boxes, combs, tissue boxes, cigarette packages, and vinyl or plastic purses. All work-related items, including
information sheets, fluid containers, tools, and parts carriers must be those approved for use at the static-free work station.
GENERAL HANDLING PROCEDURES AND REQUIREMENTS
1. All static-sensitive items must be received in an antistatic/conductive container and must not be removed from
the container except at static-free work station. All protective folders or envelopes holding documentation (lot
travelers, etc.) shall be made of nonstatic-generating material.
2. Each packing (outermost) container and package (internal or intermediate) shall have a bright yellow warning
label attached, stating the following information or equivalent:
CAUTION
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ELECTROSTATIC
SENSITIVE
DEVICES
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DO NOT OPEN OR HANDLE
EXCEPT AT A
STATlC·FREE WORKSTATION
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The warning label shall be legible and easily readable to normal vision at a distance of 3 feet.
3. Static-sensitive items are to remain in their protective containers except when actually in work at the static-free
station.
4. Before removing the items from their protective container, the operator should place the container on the conductive
grounded bench top and make sure the wrist strap fits snugly around the wrist and is properly plugged into
the ground receptacle, then touch hands to the conductive bench top.
5. All operations on the items should be performed with the items in contact with the grounded bench top as much
as possible. Do not allow conductive magazine to touch hard grounded test gear on bench top.
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13-6
6. Ordinary plastic solder-suckers and other plastic assembly aids shall not be used.
7. In cases where it is impossible or impractical to ground the operator with a wrist strap, a conductive shoe strap
may be used along with conductive tile/mats.
8. When the operator moves from any other place to the static-free station, the start-up procedure shall be the
same as in PREPARATION FOR WORKING AT STATIC-FREE WORK STATION.
9. The ionizer shall be in operation prior to presenting any static-sensitive items to the static-free station, and shall
be in operation during the entire time period the items are at the station.
10. "Plastic snow" polystyrene foam, "peanuts," or other high-dielectric materials shall never come in contact
with or be used around electrostatic sensitive items, unless they have been treated with an antis tat (as evidenced
by pink color and generation of less than ± 100 volts).
11. Static-sensitive items shall not be transported or stored in trays, tote boxes, vials, or similar containers made
of untreated plastic material unless items are protectively packaged in conductive material.
PACKAGING REQUIREMENTS
Packaging of static-sensitive items is to be in accordance with Device Sensitivity, item 1). The use of tape and plain
plastic bags is prohibited. All outer and inner containers are to be marked as outlined in GENERAL HANDLING
PROCEDURES AND REQUIREMENTS, item 2, and conductive magazines/boxes may be used in lieu of conductive bags.
SPECIFIC HANDLING PROCEDURES FOR STATIC-SENSITIVE ITEMS
Stockroom Operations
1. Containers of static-sensitive items are not to be accepted into stock unless adequately identified as containing
static-sensitive items.
2. Items may be removed from the protective container (magazine/bag, etc.) for the purpose of subdividing for
order issue only by a properly grounded operator at an approved static-free station as defined in FACILITIES
FOR and PREPARATION FOR WORKING AT STATIC-FREE WORK STATION.
3. All subdivided lots must be carefully repackaged in protective containers (magazine/bag, etc.) prior to removal
from the static-free work station and labeled to indicate that the package(s) contain static-sensitive items. If it
is suspected that a static-sensitive item is not adequately protected, do not transfer it to another container, return
it to the originator for disposition unless the originator is a Customer. In that case, the QC Engineer should
contact the Customer and negotiate an appropriate disposition.
4. It is the responsibility of the Stockroom Supervisor to ensure that all personnel assigned to this operation are
familiar with handling procedures as outlined in this specification. A copy of this specification is to be posted
in the vicinity so that it is accessible to the operators. Stock handlers and all others who might have occasion
to move stock are to be instructed to avoid direct contact with unprotected static-sensitive items.
Module and Subassembly Operations
1. Static-sensitive items are not to be received from a stockroom, kitting, or machine insertion area unless received
in approved static-protective packaging, and properly labeled to indicate that its contents are static sensitive.
2. All single station, progressive line manual assembly operators, and visual inspectors prior to wave soldering
operations are to be properly grounded with a grounding wrist strap when handling static-sensitive items.
3. Progressive lines used as single stations where operators will be working on a mix of boards, both static-sensitive
and nonstatic-sensitive, will require that all operators working on the line be properly grounded. This is necessary
to accommodate the sliding of static-sensitive boards along the assembly bench or across positions not engaged
in the assembly of this type board.
4. It is the responsibility of the Area Supervisor to ensure that all personnel handling static-sensitive items are
familiar with this procedure and fully aware of the damage or degradation of these units in the event of
noncompliance. A periodic inspection should be made using an electrostatic voltmeter to assure that the staticfree stations are in proper working order and to ensure that operators are wearing grounding wrist straps properly
(snugly in contact with bare skin).
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13-7
Soldering and Lead-Forming Operations
1.
2.
3.
4.
5.
6.
7.
8.
All soldering machines, conveyors, cleaning machines, and equipment shall be electrically grounded to ensure
that they are at the same ground potential as the grounded operators working on their stations. No machine
surfaces exposed to static-sensitive items are to be above the ground potential.
All processing equipment shall be grounded, including all loading and unloading stations, that is, the stations
.
before and after each piece of processing equipment.
All nonmetallic, static-generating components in the handling systems shall be treated to ens~re protection from
static.
All stations shall be identified by posting signs as outlined in ESD Labels and Signs in Work Areas.
Operators are to be properly grounded with a grounding wrist strap during any handling, loading, unloading,
inspection, rework, or proximity to static-sensitive items.
Unloading operators working at a grounded station shall place static-sensitive items into approved static-protective
bags or containers.
All manual soldering, repair, and touch-up work stations on the solder line are to be static protected. Operators
are to wear grounding wrist straps when working on static-sensitive items. Only grounded-tip soldering/desoldering
irons are allowed when working on static-sensitive items.
It is the responsibility of the Area Spervisor to ensure that all personnel handling static-sensitive items are familiar
with this procedure and fully aware of the damage or degradation of these units in the event of noncompliance.
A periodic inspection should be made using an electrostatic voltmeter to assure that the static-free stations are
in proper working order and to ensure that operators are wearing grounding wrist straps properly (comfortably
snug in contact with bare skin).
Electrical Testing Operations
1.
2.
3.
4.
5.
6.
7.
8.
9.
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All electrical test stations shall be static protected. Operators shall be properly grounded when working on these
items.
Reused antistatic magazines must be monitored for maintenance of antistatic characteristics.
Devices should be in an antistatic/conductive environment except at the moment when actually under test.
Devices should not be inserted into or removed from circuits or tester with the power on or with signals applied
to inputs to prevent transient voltages from causing permanent damage.
All unused input leads should be biased if possible.
Device or module repairs must be performed at static-free stations with the operator attached to a grounding
wrist strap. Grounded-tip soldering irons shall be used when working on static-sensitive items;
Static-sensitive items shall be handled through all electrical inspections in static protective containers. Removal
of the items from the protective containers shall be done at a static-free work station as discussed in
PREPARATION FOR WORKING AT A STATIC-FREE WORK STATION. The units must be returned
to the containers before leaving the station.
All such items shall be shipped with an ESD warning label affixed as listed.
It is the responsibility of the Area Supervisor to ensure that all personnel handling static-sensitive items are
familiar with this procedure and fully aware of the damage or possible degradation of these units in the event
of noncompliance. A periodic inspection should be made using an electrostatic voltmeter to assure that the static-free
stations are in proper working order and to ensure that operators are wearing grounding straps properly (snugly
in contact with bare skin).
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Packing Operations
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13-8
Static-sensitive items are not to be accepted into the packing area unless they are contained in a static-protected
bag or conductive container.
A static-sensitive item delivered to the packer within an approved container or bag and found to be in order
regarding identification shall be packed in the standard shipping carton or other regular packaging material.
Containers are to be labeled in accordance· with GENERAL HANDLING PROCEDURES AND
REQUIREMENTS, item 2.
Any void-fillers shall be made of an approved antistatic material.
Burn-In Operations
1.
2.
3.
4.
Burn-in board loading and unloading of static-sensitive items shall be done at a static-free station.
Shorting clips/shorted connectors shall be installed on the board plug-in tab prior to loading any units into the
board sockets. The clip/connector shall be taken off just prior to plugging the board into the oven connector.
The clip/connector shall be installed immediately upon removal of the board from the oven connector.
Installation and removal of the clip/connector shall be done by a properly grounded operator.
All automatic or semiautomatic loading and unloading equipment shall be properly electrically grounded.
It is the responsibility of the Area Supervisor to ensure that all personnel handling static-sensitive items are
familiar with this procedure and fully aware of the damage or possible degradation of these units in the event
of noncompliance. A periodic inspection should be made using an electrostatic voltmeter to assure that the static-free
stations are in proper working order and to ensure that operators are wearing grounding straps properly (snugly
in contact with bare skin).
CUSTOMER RETURNED ITEM HANDLING PROCEDURE
Receipt of ESDS-labeled items is to be done at a static-free work station and handled in accordance with applicable sections
within this guideline.
QUALITY CONTROL PROVISIONS
Sampling
Each manufacturing, stockroom, and testing operation handling ESDS devices will be audited a minimum of once each
quarter for compliance with all terms of this specification by the responsible process control or QRA organization. Ground
continuity and the presence of uncontrolled static voltages are considered critical and shall be checked more frequently as
specified below.
Ground Continuity (minimum of once a week).
Ground connections (grounding wrist strap, ground wires on cords, etc.) shall be checked for electrical continuity. The
presence of a 1 MO ± 10% resistor in the ground connections between both the operator wrist straps to the work surface
and the work surface to ground connector must be verified.
Grounded Conditions (minimum of once a week).
A visual inspection shall be made to determine full compliance with this specification at static-free work stations during
handling of static-sensitive items, including operator being grounded as required, static-sensitive items not being handled
in unprotected or unauthorized areas, and no static-generating materials at the grounded work station.
Sleeve Protectors (minimum of once a week).
A visual check shall be made to determine thllt each operator wearing loose-fitting or long-sleeved clothing either has
sleeves properly rolled or covered with sleeve protectors properly grounded to the bare skin at the wrist.
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Static Voltage Levels (minimum of once a week).
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In addition to the visual inspections, a sample inspection using an electrostatic voltmeter will be used to check for
uncontrolled electrostatic voltages at or near electrostatic-controlled work stations.
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Conductive Floor Tiles (minimum of once a month).
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Conductive floors must have a resistance of not less than 25 kO from any point on the tile to earth ground. Also, resistance
from any point-to-point on the tile floor 3 feet apart shall be not less than 25 kO. The test methods to be used are _
ASTM-F-150-72 and NFPA 56.
13-9
Records
Written records must be kept of all these QC audits.
TRAINING
Training is applicable for all areas where individuals come in contact with ESDS (category A) devices. It is the responsibility
of each Area Supervisor to make sure that his/her people receive ESD training initially and every 12 months thereafter to
maintain proficiency. Training should include static fundamentals, a review of applicable parts of this specification, and actual
applications in the work area.
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13-10
TI Japan Regional
Technology Centers
NAGOYA
Daini Toyota Bid. West·Wing 7F
4·10·27 Meieki Nakanura·Ku,
Nagoya-City, 450 japan
TEL: 052·583·8691
FAX: 052·583·8696
OSAKA
Nissho 1wai Bid. 5F
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Osaka-City, 541 japan
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FAX: 06·204·1895
TI Japan
Sales Offices
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NAGOYA
2597·1 Harudai, Yasaka,
Kitsuki-City,
Oita, 873 japan
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Asia Pacific Division
APD Sales Offices
AUSTRALIA
Texas Instruments Australia Limited
6-10 Talavera Road
North Ryde, NSW
Sydney, Australia 2113
TEL: 011 +61 +2+887-1122
FAX: 011+61+2+888-3415
TLX: AA25685
Texas Instruments Australia Limited
418 SI. Kilda Road
Melhourne, VIC 3004
Australia
TEL: 011+61+03+267-4677
FAX: 011 +61 +03 + 267-6381
TLX: AA36410
HONG KONG
Texas Instruments Asia Ltd.
8/F, World Shipping Centre
Harhour City, 7 Canton Rd.
Kowloon, Hong Kong
TEL: 011 +852 + 3 + 722-1 223
FAX: 011+852+3+724-4954
TLX: 43809 ASIAT HX
PHILIPPINES
Texas Instruments Asia Ltd.
14th/F, BA-Lepanto Bldg.
8747 Paseo De Roxas
Makati, Metro Manila,
Philippines
TEL: 011+63+2+817-6031
TLX: 45337 ASIAT PM
SINGAPORE
Texas Instruments Singapore (PTE) LTD ..
Asia Pacific Division
101 Thomson Rd. # 23-01
Goldhill Square
Singapore 1130
TEL: 011+65+251-9818
FAX: 011 +65 + 253-6655
TLX: RS3687I
SOUTH KOREA
Texas Instruments Supply Co.
3/F, Saman Building
678-39, Yuksam-Dong,
Gangnam-Ku,
Seoul. Korea 135
TEL: 011 +82 +2 + 556-8661
FAX: 011+82+2+555-6158
TLX: TIKOR K292 I 2
TAIWAN
Texas Instruments Supply Co.
903, 9/F, Bank Tower
205 , Tung Hua N. Road
Taipei, Taiwan R.O.C.
TEL: 011 +886 + 2 + 713-9311
FAX: 011+886+2+716-9487
TLX: 24903 TISCOTAI
APD Regional
Technology Centers
HONG KONG
Texas Instruments Asia Ltd.
8/F, World Shipping Centre
Harbour City, 7 Canton Rd.
Kowloon, Hong Kong
TEL: 011 +852+3+722-IZZ3
FAX: 011+852+3+724-4954
TLX: 43809 ASIAT HX
SINGAPORE
Texas Instruments Singapore (PTE) Ltd.
Asia Pacific Division
101 Thomson Rd. # 23-01
Goldhill Square
Singapore 1130
TEL: 011 +65+251-9818
FAX: 011 +65 + 253-6655
TLX: RS36871
SOUTH KOREA
Texas Instruments Supply Co.
3/F, Saman Building
678-39, Yuksam-Dong,
Gangnam-Ku,
Seoul, Korea 135
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FAX: 011+82+2+555-6158
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TAIWAN
Texas Instruments Supply Co.
903, 9/F, Bank Tower
205, Tung Hua N. Road
Taipei, Taiwan R.O.C.
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APD Distributors
AUSTRALIA
ACDfltronics PTY Limited
106 Belmore Road
.
North Riverwuod, NSW ZZ 10
TEL: (02) 534 6200
FAX: (02) 534 4910
TLX: AA 12 1398
VSI Electronics (AUST) PTY Limited
16 Dickson Avenue
Artarmon, NSW 2064
VSI Electronics (N.Z.) Limited
7 Beasley Avenue
Penrose, Auckland
New Zealand
TEL: (649) 59 6603
FAX: (649) 59 3694
TLX: NZX60340
RIFA PTY Limited
202 Bell Street
Preston, VIC 3072
TEL: (03) 480 1211
FAX: (03) 484 6345
TLX: AA31001
Electronic Components & Equipment PTY Ltd.
30-40 Hurtle Square
Adelaide, S.A. 5000
TEL: (08) Z32 0001
FAX: (08) Z32 0670
TLX: AA89417
Electrocon Products Ltd
5th Floor, Perfect Commercial Building
20 Austin Avenue
Kowloon, Hong Kong
TEL: 3-687214,3-7392023
FAX: 3-7220869
TLX: 39916 EPLET HX
INDIA
Zenith Electronics PVT Ltd.
A to Z Industrial Estate
A-3 Annex Building, 3rd Floor
Ganpatrao Kadam Marg.
Lower Parel
Bomhay 400-013
India
TEL: 91-22-4946027,4941677
TLX: 1173772 ZNTH, IN
PHILIPPINES
DEE HWA Liong Eleci. Equipment Corp.
(DEECO)
607 Sales St., Quiapo, Manila
TEL: 011 +63 +2 +4016511408859/475725/
408134
TLX: 27691 DEEPH
R & I Electronics
1157 Quezon Avenue
Quezon City
TEL: 011 +63+2+983344/985778
SINGAPORE
Transco Electronics PTE Ltd.
IO Jalan Besar
Sim lim Tower, # 02-01 & 02-02
Singapore 0820
TEL: 011 +65+294-71Z7
FAX: 011 +65 + 296-7435
TLX: RS34550 TE
SOUTH KOREA
Tong Baek Trading Co. Ltd.
New Hanil Building, 2nd Floor
156-1, Yeomri-Dong, Mapo-Ku
Seoul. Korea
TEL: 2-7166625,2-7190817
FAX: 2-7190818
TLX: K28569 TBTRACO
TAIWAN
Sertek Intemation Co. Ltd.
I3F, No. 135 Sec. 2
Chien Kuo North Road
Taipei, Taiwan
R.O.C.
TEL: 2-5010055
FAX: 2-5058414
TLX: 23756 SERTEK
World Peace Industrial Co. Ltd.
5F, No. 309 Sung Chiang Road
Taipei, Taiwan
TEL: 2-505-6345
FAX: 2-501-6026
TLX: 14030 WPINDCO
THAILAND
Choakchai Electronic Supplies L.P.
128/ZZ Thanon Atsadang
Bangkok 2
Thailand
TEL: 66-2-221043,2215384,2223921,2227001
FAX: 66-2-2247639
TLX: 84809 CESLP TH
AUSTRALIA
Texas Instruments Australia Limited
6-10 Talavera Road
North Ryde, NSW
Sydney, Australia 2113
TEL: 011 +61 + 2 +887-1122
FAX: 011 +61 + 2 +888-3415
TLX: AA25685
Texas Instruments Australia Limited
418 SI. Kilda Road
Melbourne, VIC 3004
Australia
TEL: 011+61+03+267-4677
FAX: 011+61+03+267-6381
TLX: AA36410
HONG KONG
A TEK Electronics Co. Ltd.
RM 1301. 1302, 1309, Argyle Centre
Phase I
688 Nathan Road
Kowloon, Hong Kong
TEL: 3-916833-4, 3-953165-0
FAX: 3-7779603
TLX: 37119ATEKHX
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Latin America
Division
LAD Sales Offices
Texas Instrumentes Argentina
Vi,lmonte 1119
1053 Capital Federal
Bueno, Aires, Argentina
Tel: 5411748·3699
Texas Instrumentos Eiectronicos
Do Brasil LTDA
Rua Azarias de Melo. 648/660
Caixa Po>tai 988/86
13.090 Campinas, SP. Brasil
Tel:
55/192/51·8144
Texas Instruments de Mexico
Alfonso Reyes -115
Col. Hipodromo Condesa
06120 Mexico. D.F., Mexiw
525/525·3860
Tel:
ENEKA ARGENTINA
Tucuman 299
1049 Buenos Aires
Argentina
Tel:
311·3363
RODAR SEMICONDUCTORES
Parana 789
1017 Bueno, Aires
Argentina
Tel: 45-6063
BRAZIL
ALFATRONIC S/A
Av. Rehoucas, 1028
05402 - Sao Paulo - SP
Brazil
Tel: (011)852·8277
INTERTEK COMPONENTES
ELECTRONICOS LTDA
R. Miguel Casagrande, 200
02714 - Sao Paulo - SP
Brazil
Tel: (011) 266·2922
ARGENTINA
ELECTROCOMPONENTES
Solis 227
1078 Buenos Aires
Argentina
Tel: 45·1864
L.F. INDUSTRIA E COMERCIO DE
COMPONENTES ELETRONICOS LTDA
Av. Ipiranga, 1100 - 8. Andar
01040 - Sao Paulo - SP
Bra:il
Tel: (011) 229·9644
PAN AMERICANA COMERCIAL
IMPORTADORA LTDA
Rua Aurora, 263
02714 - Sao Paulo - SP
Bra:il
Td: (011) 222·2311
TECNOS
Av. Independencia 1861
1225 Buenos Aires
Argentina
Tel:
37·3793
TELEIMPORT ELETRONICA LTDA
Rua Santa Ifigenia, 402 - 10. Andar
01207 - Sao Paulo - SP
Bra:il
Tel: (011)222·2122
DESAC
Santa Rosa 3803 - Florida
1602 Buenos Aires
Argentina
Tel: 760·5749
TELERADIO ELETRONICA LTDA
Rua Sen a Madureira, 42
04021 - Sao Paulo - SP
Brazil
Tel: (011) 544·1722
TITRONIX ELETRONICA LTDA
R. Dr. Euriw Rangel, 40
04602 - Sao Paulo - SP
Bra:il
Tel: (011)543-4766
CHILE
VICTRONICS Limitada
Mac·lver 225 Oficina 301
Santiago de Chile
Tel: 5621330237
LAD Distributors
UNION T.V.
Lavalle 350
5500 Mendoza
Argentina
Tel: (061)252231
RAMBLERT
Santa Rosa 53/55
5000 Cordoha
Argentina
Tel: (051)27361
G.B. INGENIERIA ELECTRONIC A
Mitre 1173 - Rosario
2000 Santa Fe
Argentina
Tel: (041)45890
MENDEZ COLLADO
Av. Corricntes 3500
1194 Buenos Aires
Argentina
Tel: 88·1152
."
TEXAS
INSTRUMENTS
COLOMBIA
TEKCIEN Electronica
~k~a~5. ~e~~4d.~~7
Bogota. Colombia
Tel: 57112417·940
COSTA RICA
Electro Mundo Inti. S.A.
Apdo. Postal 1824·1000
Av. 4, Calles 6 y 8
San Jose, Costa Rica
Tel: 506/57-0222
ECUADOR
D1MATRONIC
P.O. Box 3373
Junin 703 y Boyaca
Guayaquil, Ecuador
Tel: 593-4·301863
D1MATRONIC
(Div. MANTENIMIENTO ELECTRONICO)
Plaza 414 y Roca
Quito, Ecuador
Tel: 234·284
MEXICO
D1COPEL, S.A. DE C.V.
Tochli 1/368
Frace. Ind. San Antonio Azcapotzalco
02760 Mexico, D.F., Mexico
Tel: 561·32·11
GRUPO D1STELE, S.A.
Obrero Mundial 11736.
Col. Alamos
03400 Mexico, D.F., Mexico
Tel: 538-05-00 AL 04
ELECTRONICA, COMPONENTES Y
MODULOS, S.A.
Ave. Universidad 1/ 626,
Col. Vertiz Narvarte
03600 Mexico, D.F., Mexico
Tel: 575-84-65
ELECTRONICA SETA, S.A. DE C.V.
Ings. Militares 1135 - 101
Naucalpan de Juarez, E.M., Mexico
Tel: 358·39·38/358·51·98/358·73-65
PARAGUAY
Micro Sistemas S.R.L.
Tte. Farina 1126 Casi Brasil
Asuncion, Paraguay
Tel: 59/521·208284
URUGUAY
Eneka S.A. Division Electronica
Av. Gral. Rondeau 1534
P.O. Box 695
Montevideo, Uruguay
Tel: 598/907·944
VENEZUELA
Logibyte de Venezuela
Apdo. Los Chaguaramos 47776
Av. Ciudad Universitaria
Edif. Los Moriches
Caracas 104I·A, Venezuela
Tel: 5821662·1980
Pedro Benavides
Avilanes a Rio
Residencia Kamarata Local 4
Apdo. Postal 20249
Caracas I 020·A , Venezuela
Tel: 582/572-4908
TI Sales Offices
BELGIQUE/BELGIE
S.A. Texas Instruments Belgium N.V.
II, Avenue Jules Bordetlaan 11,
1140 Bruxelles/Brussel
Tel: (02) 242 30 80
Telex: 61161 TEXBEL
DAN MARK
Texas Instruments A/S
Marielundvej 46E
2730 Herlev
Tel: 02 91 7400
Telefax: 02 91 8400
Telex: 35123 TEXIN
DEUTSCHLAND
Texas Instruments
Deutschland GmbH:
HaggertystraG.e I
8050 Freising
Tel: 0 81 61/80-0 od. Nbst
Telex: 5 26 529 texin d
Btx : *280505 #
Kurfurstendamm 195·196
1000 Berlin 15
Tel: 030/8 82 73 65
Telex : 5 26 529 texin d
Dusseldorfer StraG.e 40
6236 Eschborn I
Tel: 06196/80 70
Telex : 5 26 529 texin d
Ill. Hagen 43/KibbelstraG.e 19
4300 Essen I
Tel: 0201124 25-0
Telex 5 26 529 texin d
Kirchhorster StraG.e 2
3000 Hannover 51
Tel: 0511164 8021
Telex: 5 26 529 texin d
MaybachstraG.e II
7302 Ostfildern 2 (Nellingen)
Tel. 0711134 03-0
Telex 5 26 529 texin d
EIRE
Texas Instruments Ireland Ltd
718 Harcourt Street
Dublin 2
Tel: (01) 78 16 77
Telex : 32626
ESPANA
Texas Instruments Espana S.A.
C/Jose Lazaro Galdiano No.6
28036 Madrid
Tel: (I) 458 14 58
Telex: 23634
Fax: (I) 457 94 04
C/Diputacion, 279-3-5
08007 Barcelona
Tel:(3)3179180
Telex: 50436
Fax: (3) 301 84 61
FRANCE
Texas Instruments France
8-10 Avenue Morane Saulnier - B.P. 67
78141 VeIizy Villacoublay cedex
Tel: Standard: (I) 30 70 10 03
Service Technique: (1) 30 70 II 33
Telex: 698707 F
HOLLAND
Texas Instruments Holland B.V.
Hogehilweg 19
Postbus 12995
1100 AZ Amsterdam-Zuidoost
Tel: (020) 5602911
Telex: 12196
('''J1yright © 1988, Texas Instruments
~t/\Y
25TH 1988
ITALIA
Texas Instruments Italia S.p.A.
Divisione Semiconduttori
Viale Europa, 40
20093 Cologno Monzese (Milano)
Tel: (02) 25300 1
Telex: 332633 MITEX I
Via Castello della Magliana, 38
00148 Roma
Tel. (06) 5222651
Telex 610587 ROTEX I
T elefax 5220447
Via Amendola, 17
40100 Bologna
Tel. (051) 554004
NORGE
Texas Instruments Norge A/S
PB 106
Refstad (Sinsenveien 53)
0585 Oslo 5
Tel: (02) 155090
OSTERREICH
Texas Instruments Ges.m.b.H.
Hietzinger Kai 101-105
A-I130 Wien
Tel: 0222/9100-0
Telex: 136 796
PORTUGAL
Texas Instruments Equipamento
Electronico (Portugal) LDA.
R. Eng. Frederico Ulrich, 2650
Moreira Da Maia
4470 Maia
Tel: (2) 948 1003
Telex: 22485
SCHWEIZ/SUISSE
Texas Instruments Switzerland AG
RiedstraG.e 6
CH-8953 Dietikon
Tel: (01) 740 22 20
Telex: 825 260 TEXIN
SUOMI FINLAND
Texas Instruments OY
Ahertajantie 3
P.O. Box 81,
0201 Espoo
Tel: (90) 0-461-422
Telex: 121457
SVERIGE
Texas Instruments
International Trade Corporation
(Sverigefilialen)
Box 30,
S-163 93 Stockholm
Visit address: lsafjordsgatan 7, Kista
Tel: (08) 793 91 70
Telefax: (08) 751 97 15
Telex: 10377 SVENTEX S
UNITED KINGDOM
Texas Instruments Ltd.
Manton Lane,
Bedford,
England, MK41 7PA
Tel: (0234) 270 111
Telex: 82178
Technical Enquiry Service
Tel: (0234) 223000
~
TEXAS
INSTRUMENTS
TI Regional
Technology Centres
DEUTSCHLAND
Texas Instruments
Deutschland GmbH.
HaggertystraG.e 1
8050 Freising
Tel: (08161) 80 40 43
Frankfurt/Main
Dusseldorfer StraG.e 40
6236 Eschborn
Tel: (061 96) 80 74 18
Kirchhorster StraG.e 2
3000 Hannover 51
Tel: (0511) 64 80 21
MaybachstraG.e 11
7302 Ostfildern 2 (Nellingen)
Stutrgart
Tel: (0711) 34 03-0
FRANCE
Centre de Technologie
Texas Instruments France
8·10 Avenue Morane Saulnier, B.P. 67
78141 Velizy Villacoublay cedex
Tel: Standard: (I) 30 70 10 03
Service Technique: (I) 30 70 II 33
Telex: 698707 F
Texas Instruments France
B. P. 5
06270 Villeneuve-Loubet
Tel: 93 22 2001
Telex: 470127 F
HOLLAND
Texas Instruments Holland B.V.
Hogehilweg 19
Postbus 12995
1I00 AZ Amsterdam·Zuidoost
Tel: (020) 5602911
Telex: 12196
ITALIA
Texas Instruments ltalia S.p.A.
Divisione Semiconduttori
Viale Europa, 40
20093 Cologno Monzese (Milano)
Tel: (02) 25300 I
Telex: 332633 MITEX I
SVERIGE
Texas Instruments
International Trade Corporation
(Sverigefilialen)
Box 30
S·163 93 Stockholm
Visit address: lsafjordsgatan 7, Kista
Tel: (08) 793 91 70
Telefax: (08) 751 97 15
Telex: 10377 SVENTEX
UNITED KINGDOM
Texas Instruments Ltd.
Regional Technology Centre
Manton Lane,
Bedford,
England, MK41 7PA
Tel: (0234) 270 III
Telex: 82178
Technical Enquiry Service
Tel: (0234) 223000
REFERENCE
TI Sales Offices TI Distributors
ALABAMA: Huntsville (205) 837-7530.
ARIZONA: Phoenix (602) 995-,007;
Tucson (602) 624-3276.
CALIFORNIA: Irvine (7'4) 660-'200;
Sacramento (9'6) 929-0'97;
San Diego (6'9) 278-9600;
Santa Clara (408) 980-9000;
Torrance (2,3) 2'7-7000;
Woodland Hills (8,8) 704-7759.
COLORADO: Aurora (303) 368-8000.
CONNECTICUT: Wallingford (203) 269·0074.
FLORIDA: Altamonte Springs (305) 260-2"6;
Ft. Lauderdale (305) 973-8502;
Tampa (8' 3) 286-0420.
GEORGIA: Norcross (404) 662-7900.
ILLINOIS: Arlington Heights (3,2) 640-3000.
INDIANA: Carmel (317) 573·6400;
Ft. Wayne (2'9) 424-5174.
IOWA: Cedar Rapids (3'9) 395-9550.
TI AUTHORIZED DISTRIBUTORS
Arrow/Klerulff Electronics Group
Arrow Canada (Canada)
Future Electronics (Canada)
GRS Electronics Coo, Inc.
Hall-Mark Electronics
Marshall Industries
Newark Electronics
Schweber Electronics
Time Electronics
Wyle Laboratories
Zeus Components
- OBSOLETE PRODUCT ONLYRochester ElectroniCS, Inc.
Newburyport, Massachusetts
(617) 462-9332
KANSAS: Overland Park (9,3) 45' -45' 1MARYLAND: Baltimore (30,) 944-8600.
MASSACHUSETTS: Waltham (6,7) 895-9'00.
MICHIGAN: Farmington HillS 13'3) 553-'500;
Grand Rapids 16,6)957-4200.
MINNESOTA: Eden Prairie 16'2) 828-9300.
MISSOURI: St.Louis (3'4) 569-7600.
NEW JERSEY: Iselin (20,) 750-, 050.
NEW MEXICO: Albuquerque (505) 345-2555.
NEW YORK: East Syracuse (3,5)463-929,;
Melville (5'6)454-6600; Pittsford (7'6)385-6770;
Poughkeepsie (9'4) 473·2900.
NORTH CAROLINA: Charlotte (704) 527·0930;
Raleigh (9'9) 876-2725.
OHIO: Beachwood (2'6)464-6'00;
Dayton (5' 3) 258-3877.
OREGON: Beaverton (503) 643-6758.
PENNSYLVANIA: Blue Bell (2'5) 825-9500.
PUERTO RICO: Hato Rey (809) 753-8700.
TENNESSEE: Johnson City (6'5) 46'-2'92.
TEXAS: Austin (5,2) 250-6769;
~~~~~ro~63(5mtii~~~~chardson (2'4) 680-5082;
UTAH: Murray (80,) 266-8972.
VIRGINIA: Falrtax (703) 849-'400.
WASHINGTON: Redmond (206) 88'-3080.
WISCONSIN: Brookfield (4'4) 782-2899.
~~~~~~~ ~~r.~~ia~l~t(~\06)(~~~_~fg; ~ 970;
St. laurent, Quebec (5'4) 336-' 860.
TI Regional
Technology Centers
CALIFORNIA: Irvine (7'4) 660-8'40;
Santa Clara (408) 748-2220;
Torrance (2'3) 217-70'9.
COLORADO: Aurora (303) 368-8000.
GEORGIA: NorcroSl (404) 662-7945.
ILLINOIS Arlington Heights (3,3) 54()"2909.
MASSACHUSETTS: Wanham (617) 895-9' 96.
TEXAS: Richardson (2,4) 680-5066.
ALABAMA: Arrow/Kierulff (205) 837-6955;
Hall-Mark (205) 837-8700; Marshall (205)88'-9235;
Schweber (205) 895-0480.
ARIZONA: Arrow/K,erulff (602) 437-0750;
Hall-Mark (602) 437-,200; Marshall (602) 496-0290;
Schweber (602) 997-4874; Wyle (602) 866-2888.
CALIFORNIA: LOl Angeles/Orange County:
Arrow/Kierulff (8'8)70'-7500, (7'4) 838-5422;
Hall-Mark (8'8)7'6-7300, (7'4) 669-4'00,
(2'3)2,7-8400; Marshall (8,8)407-0,0',18,8) 459·5500,
(714)458-5395; Schweber (8'8) 999-4702;
(7'4) 863-0200, (2,3)320-8090; Wyle (2,3) 322·9953,
k8~c8;a~~~~~~OH~~~~~~ksr9~~~M~~:0~' 4) 92' -9000;
Marshall (9,6) 635-9700; Schweber (9,6) 929-9732;
Wyle 19'6) 638·5282;
San Diego: Arrow/Kierulff (6'9) 565-4800;
Hall-Mark 16,9)268-,20,; Marshall (6'9) 578-9600;
Schweber (6,9) 450-0454; Wyle (6'9) 565-9'7';
San Francisco Bay Area: Arrow/Kierulff (408) 745-6600,
Hall-Mark (408) 432-0900; Marshall (408) 942-4600;
Schweber (408)432-717'; Wyle (408) 727-2500;
Zeus (408) 998-5'21COLORADO: Arrow/Kierulff (303) 790-4444;
Hall-Mark (303) 790-,662; Marshall (303) 45'-8383;
Schweber (303) 799-0258; Wyle (303) 457-9953
CONNETICUT: Arrow/Kierulff (203)265-774,;
Hall-Mark (203)269-0'00; Marshall (203) 265-3822;
Schweber (203) 748-7080.
FLORIDA: Ft. lauderdale:
Arrow/Kierulff (305) 429·8200; Hall-Mark (305) 97, ·9280;
Marshall (305) 977-4880; Schweber (305) 977-75";
Orlando: Arrow/Klerulff (305) 725-'480, (305) 682-6923;
Hall-Mark (305) 855-4020; Marshall (305) 767-8585;
Schweber (305) 33'-7555; Zeus (305) 365-3000;
Tampa: Hall·Mark (8'3) 530-4543;
Marshall (8,3) 576-'399.
GEORGIA: Arrow/Kierulff (404) 449-8252;
Hall·Mark (404) 447-8000; Marshall (404) 923-5750;
Schweber (404) 449-9170.
ILLINOIS: Arrow/Kierulff (3'2) 250-0500;
Hall·Mark (3'2)860-3800; Marshall 13'2)490-0'55;
Newark (3'2) 784-5'00; Schweber (3'2)364-3750.
INDIANA: Indianapolis: Arrow/Kierulff (3'7) 243-9353;
Hall·Mark (317) 872-8875; Marshall (3'7) 297-0483.
IOWA: Arrow/Kierulff 13,9) 395-7230;
Schweber (3'9) 373-'4,7.
KANSAS: Kans .. City: Arrow/Kierulff (9'3)54'-9542;
Hall-Mark (9'3)888-4747; Marshall (9,3) 492-3'2';
Schweber (9'3) 492-2922.
MARYLAND: Arrow/Kierulff (30,) 995-6002;
Hall-Mark (30,) 988-9800; Marshall (30') 840-9450;
Schweber (30') 840-5900; Zeus (301) 997-" '8.
MASSACHUSETTS Arrow/Kierulff (6'7) 935-5'34;
Hall·Mark (6'7) 667·0902; Marshall (6,7) 658·08,0;
Schweber (6,7) 275-5,00, (617) 657-0760;
TIme 16'7) 532-6200; Zeus (6,7) 863-8800.
MICHIGAN: Detroit: Arrow/Kierulff (3,3) 97,-8220;
Marshall 13,3) 525-5850; Newark (3'3) 967-0600;
Schweber (3,3) 525-8'00;
Grand Rapids: Arrow/Kierulff (6,6) 243-09' 2.
MINNESOTA: Arrow/Kierulff (6'2) 830-1800;
Hall·Mark (6'2) 941-2600; Marshall (6,2) 559-22";
Schweber 16'2)94'-5280.
MISSOURI: St. louis: Arrow/Kierulff (3,4) 567-6888;
Hall-Mark (3'4) 29'-5350; Marshall (3'4) 29'-4650;
Schweber 13'4) 739-0526.
NEW HAMPSHIRE: Arrow/Kierulff (603) 668-6968;
Schweber (603) 625-2250.
NEW JERSEY: Arrow/Kierulff (20,) 538-0900,
(609)596-8000; GRS ElectroniCS (609) 964-8560;
Hall-Mark 120')575-44'5,1609)235-'900;
Marshall (20') 882-0320, (609) 234-9'00;
Schweber (20') 227-7880,
NEW MEXICO: Arrow/Kierulff (505) 243-4566,
NEW YORK: Long Island:
Arrow/K,erulff 15'6) 23,-,000; Hall·Mark (5'6) 737-0600;
Marshall (5'6)273-2424; Schweber (5'6) 334-7555;
Zeus 19'4) 937-7400;
Roch.ster: Arrow/Kierulff (7'6) 427-0300;
Hall-Mark (7'6) 244-9290; Marshall (7,6) 235-7620;
Schweber (7'6) 424-2222;
Syracu .. : Marshall (607)798-,6",
NOATH CAROLINA: Arrow/Kierulff (919) 878-3132,
19,9)725-8711; Hall-Mark (9,9) 872-07,2;
Marshall 19'9) 878-9882; Schweber (919) 876-0000.
OHIO: Cleveland: Arrow/Kierulff (2, 6) 248-3990;
Hall-Mark (2'6)349-4632; Marshall (2'6) 248-1788;
Schweber (2,6) 464-.2970;
Columbus: Arrow/Klerulff (6'4) 436-0928;
Hall-Mark (6'4) 888-33'3;
Day1on: Arrow/Kierulff (5,3) 435-5563;
Marshall (513) 898-4480; Schweber (5,3) 439-1800.
OKLAHOMA: Arrow/Kierulff (918) 252-7537;
Schweber (9'8) 622-8003.
OREGON: Arrow/Kierulff (503) 545-6456;
Marshall (503) 644-5050; Wyle (503) 54()"6000.
PENNSYLVANIA: ArrowlKierulff (4'2) 856-7000,
~~';l;,;:; W~~i ~R,~ci~r~~i~) ~1~J:0~~-7037;
~~~_~~:':(~~~)k5~~ra'.fa:i~~I~~~112(5~~~-:;:'~~9' ;
Schweber (512) 339-0088; Wyle (5'2) 834-9957;
Da"a" Arrow/K,erulff (2'4) 380-6454;
Hall-Mark (2'4) 553-4300; Marshall (2'4) 233-5200;
Schweber (2'4) 66,-50,0; Wyle (214) 235-9953;
Zeus 12,4) 783-7010;
Houslon: Arrow/Klerulff (7'3)530-4700;
Hall-Mark (7'3) 78'-6,00; Marshall (7,3) 895-9200;
Schweber (7,3) 784-3600; Wyle (7,3) 879-9953.
UTAH: Arrow/Kierulff (80,) 973-6913;
Hall-Mark (80') 972-,008; Marshall (80') 485-,55,;
Wyle 180') 974-9953.
WASHINGTON: Arrow/Kierulff (206) 575-4420;
Marshall (206) 747-9,00; Wyle (206)453-8300.
WISCONSIN: Arrow/Kierulff (414) 792-0,50;
Hall-Mark (414)797-7544; Marshall (4'4) 797-8400;
Schweber (414) 784-9020.
CANADA: Calgary: Fulure (403) 235-5325;
Edmonton: FUlure (403) 438-2858;
Montr.al: Arrow Canada (5,4) 735-55,1;
Fulure (514) 694-77'0;
Ottawa: Arrow Canada (6,3) 226-6903;
Fu'ure (6,3)820-83,3; .
Queb.c City: Arrow Canada (4'8) 687-423';
Toronto: Arrow Canada (4'6) 672-7769;
Fulure (4'6) 638-477';
Vancouver: Future (604) 294-1166;
Winnipeg: Fulure (204) 339-0554.
Customer
Response Center
CANADA: Nep.. n, Ontario (6'3) 726-'970.
TOLL FREE: (800) 232-3200
~
TEXAS
INSTRUMENTS
OUTSIDE USA: 12'4)995-6611
(8.00 a.m. - 5:00 p.m. CST)
BU
- - - - ----------------- -------------
-'!1
TEXAS
INSTRUMENTS
Printed in U.S.A.
0788-160
SMYDOm
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:01:03 09:20:42-08:00 Modify Date : 2017:01:03 12:21:42-08:00 Metadata Date : 2017:01:03 12:21:42-08:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:cd6fb247-75aa-d049-87ee-3dc4b456161c Instance ID : uuid:8ac93d28-785b-4948-a6a3-d23f7dc809bb Page Layout : SinglePage Page Mode : UseNone Page Count : 1172EXIF Metadata provided by EXIF.tools