1989_Xilinx_Programmable_Gate_Array_Data_Book 1989 Xilinx Programmable Gate Array Data Book
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1:XIUNX
The Programmable Gate Array
Data Book
,
1989
SECTION TITLES
1
Programmable Gate Arrays
2
Produc·t Specifications
3
Quality, Testing, Packaging
4
Technical Support
5
Development Systems
6
Applications
7
Article Reprints
8
Index
The Programmable Gate Array Company
PROGRAMMABLE LOGIC
DEVICES
GATE ARRAYS
EXTENSIVE
SIMULATION
PRIMITIVE
USER
PROGRAMMABLE
DEVELOPMENT
TOOLS
116201
THE PROGRAMMABLE GATE ARRAY
(LOGIC CELLTM ARRAY)
l:XllIXX
TABLE OF CONTENTS
1 Programmable Gate Arrays
About the Company
Introduction to Programmable Gate Arrays
A Cost of Ownership Comparison
1-1
1-3
1-9
III
2 Product Specifications
XC3000 Logic Cell Array Family
XC2064, XC2018
Military Logic Cell Arrays
XC1736 Serial Configuration PROM
XC1764 Serial Configuration PROM
Ordering Information
•
•
•
•
2-1
2-55
2-97
2-139
2-150
2-152
3 Quality, Testing, and Packaging
Quality Assurance and Reliability
Methodology
Packaging
3-1
3-11
3-17
4 Technical Support
Technical Seminars and Users' Group Meetings
Video Tapes
Newsletter
Technical Bulletin Board
Field Applications Engineers
Training Course
XACT Manuals
User's Guides
4-1
4-2
4-3
4-4
4-6
4-7
4-8
4-9
5 Development Systems
Overview
Design Manager
System Architecture
PC Hardware Requirements
Macro Library
Product Briefs
Ordering Information
5-3
5-4
5-18
5-22
5-25
5-32
5-49
6 Applications
Introduction
Estimating Size and Performance
Incorporating PLD Equations Into LCAs
The XC2000 User's Guide to the XC3000 Family
Designing with the XC3QOO Family
Designing with the XC2000 Family
6-1
6-3
6-7
6-11
6-12
6-13
1962
TABLE OF CONTENTS
6 Applications (Con'f)
Additional Electrical Parameters
LCA Performance
Start-up and Reset
Metastable Recovery
Battery Backup for Logic Cell Arrays
Compact Multiplexer and Barrel Shifter
Majority Logic, Parity
Multiple Address Decoding
Binary Adders, Subtractors, and Accumulators
Adders and Comparators
Conditional Sum Adder
Building Latches Out of Logic
Synchronous Counters, Fast and Compact
30 MHz Binary Counter
Up/Down Counter
Loadable Up/Down Counter
30 MHz Counter with Synchronous Reset
Fast Bidirectional Counters for Robotics
40 MHz Presettable Counter
Asynchronous Preset in XC3000 CLBs
Frequency/Phase Comparator for Phase-Locked-Loops
Gigahertz Presettable Counter
100 MHz Frequency Counter
Serial Pattern Detectors
Serial Code Conversion
8-Bit Format Converter
Megabit FIFO in Two Chips
State Machines
Complex State Machine in One LCA
Self-Diagnosing Hardware
PS/2 Micro Channel Interface
High-Speed Bar Code Reader
DRAM Controller with Error Correction
Logic Analyzer/In-Circuit Emulator
6-14
6-16
6-19
6-20
6-22
6-23
6-24
6-25
6-26
6-27
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-40
6-41
6-42
6-44
6-45
6-46
6-48
6-50
6-52
6-53
6-54
6-57
6-59
6-61
6-67
7 Article Reprints
Building Tomorrow's Disk Controller Today
The Acid Test
Programmable Logic Betters the Odds
Using LCAs in a Satellite Earth Station
Faster Turnaround for a T1 Interface
Two, Two, Two Chips in One
LCA Stars in Video
Taking Advantage of Reconfigurable Logic
7-1
7-5
7-8
7-12
7-17
7-19
7-22
7-24
8 Index
Index
Sales Office Listing
8-1
8-3
1962
SECTION 1
Programmable Gate Arrays
1
Programmable Gate Arrays
2
Product Specifications
3 'Quality, Testing, Packaging
4
Technical Support
5
Development Systems
6
Applications
7
Article Reprints
8
Index
Programmable Gate Arrays
About the Company ............................................................................ 1-1
Introduction to Programmable Gate Arrays ......................................... 1-3
A Cost of Ownership Comparison ....................................................... 1-9
Contributors
Peter AlIke
Keath Armstrong
Jim Chumbley
Rick Dudley
Chuck Erickson
Lee Farrell
Brad Fawcett
Chuck Fox
Dave Galli
Jim Hsieh
Steve Knapp
Dave Lautzenheiser
Mark Markham
Bob McGrath
Bill O'Neill
Wes Patterson
Richard Ravel
Ed Resler
Steve Schreifels
Don Soderman
Robert Stransky
Thomas Waugh
Perry Wu
Pardner Wynn
© Copyright 1989 by Xilinx, Inc. All Rights Reserved.
Patents Pending
Xilinx, Logic Cell, LCA, XACT, XACTOR, Programmable Gate Array,
and Logic Processor are trademarks 01 Xilinx, Inc. The Programmable Gate Array Company is a Service Mark of Xilinx, Inc.
IBM is a registered trademark and PCIAT, PC/XT, PS/2, and Micro
Channel are trademarks of International Business Machines
Corporation. ABEL is a trademark and Data 110 is a registered
trademark of Data 1/0 Corporation. FutureNet is a registered
trademark and DASH is a trademark of FutureNet Corporation, a
Data I/O Company. SimuCad and Silos are registered trademarks
and P-Silos and PIC-Silos are trademarks of SimuCad Corporation.
Microsoft is a registered trademark and MS-DOS is a trademark of
Microsoft Corporation. Logitech is a registered trademark of
LOGITECH Inc. Lotus is a registered trademark of Lotus
Development Corporation. AboveBoard and AboveBoard/PS are
trademarks of Intel Corporation. RAMpage!, SixPakPlus and
SixPakPremium are registered trademarks of AST Research, Inc.
Mouse Systems is a trademark of Mouse Systems Corporation.
Centronics is a registered trademark of Centronics Data Computer
Corporation. PAL and PALASM are registered trademarks of
Advanced Micro Devices, Inc., DAISY, Logician, and DNIX are
registered tradmarks of Daisy Systems. UNIX is a trademark of
AT&T Technologies, Inc. CUPL is a trademark of Logical Devices,
Inc.. Apollo and AEGIS are registered trademarks of APOLLO
Computer. Mentor and IDEA are registered trademarks and
QuickSim, NETED, EXPAND are trademarks of Mentor Graphics,
Inc. ValidGED and ValidSim are trademarks of Valid Logic Systems,
Inc. Sun is a registered trademark of Sun Microsystems, Inc.
SCHEMA II is a trademark of Omation Corporation. OrCAD is a
registered trademark of OrCAD Systems Corporation. Viewlogic is a
registered trademark of Viewlogic Systems, Inc. CASE Technology
is a trademark of CASE Technology, a division of Teradyne's
Electronic Design Automation Group. Xilinx, Inc. does not assume
any liability arising out of the appiication or use of any produci
described herein; nor does it convey any license under its patent,
copyright or maskwork rights or any rights of others. Xilinx, Inc.
reserves the right to make changes, at any time, in order to improve
reliability, function or design and to supply the best product possible.
Xilinx, Inc. cannot assume responsibility for the use of any circuitry
described other than circuitry entirely embodied in their product. No
other circuit patent licenses are implied. Xilinx, Inc. cannot assume
responsibility for any circuits shown or represent that they are free
from patent infringement or of any other third party right. Xilinx, Inc.
assumes no obligation to correct any errors contained herein or to
advise any user of this text of any correction if such be made.
Printed in U.S.A.
1962
About the Company ...
Xilinx is the first company to develop a user-programmable
gate array. The invention of a high-density, generalpurpose user-programmable logic device was the result of
a number of breakthroughs, and several aspects of the
device's array architecture have been patented. Since the
introduction of its first product in 1985, Xilinx has continued
to lead in the development of new programmable gate arrays with higher speeds, higher densities, and lower costs.
Due to their density and the convenience of user programmability, Xilinx's Programmable Gate Arrays represent an
important new alternative in the market for Application •
Specific Integrated Circuits (ASICs). The company continues to concentrate its resources exclusively on expanding
its growing family of Programmable Gate Arrays and associated development systems, and on providing technical
support to a rapidly growing customer base.
1-1
1-2
INTRODUCTION TO
PROGRAMMABLE GATE ARRA YS
Steady advances in the level of integration in electronic circuits have improved many equipment features,
reducing costs, power consumption, and system size,
while increasing performance and reliability. Increasing levels of integration are most evident in microprocessor and memory ICs. With each process generation,
the technology gap between these VLSI circuits and
other standard logic ICs has widened. To achieve
comparable densities for their proprietary logic functions, designers of digital equipment have been forced
to consider factory-programmed custom and semicustom Application Specific Integrated Circuits (ASICs).
Recent breakthroughs in logic architectures have resulted in the first high density ASICs that can be configured by the user. These user programmable gate arrays
combine the logic integration benefits of custom VLSI
with the design, production, and time to market advantages of standard products. The flexibility of user programming significantly reduces the risks of design
changes and production rate changes.
ASIC ALTERNATIVES
Application Specific ICs are the best solution for most logic functions. The best ASIC solution depends on density requirements and production volumes.
20,000
STANDARD
CELL AND
CUSTOM
10,000
z
Q
I-
0
5,000
~
1,000
Z
::J
w
~
USER PROGRAMMABLE
GATE ARRAYS
0
100
0
100
1,000
10,000
100,000
1101 01
VOLUME/DESIGN
USER PROGRAMMABLE
O GATE
ARRAYS
STANDARD CELL
AND CUSTOM ICS
Standard cell and custom ICs require unique masks for all
layers used. in manufacturing. This imposes extra costs and
delays for development, but results in the lowest production
costs for high volume applications. Standard cell ICs offer the
advantages of high level building blocks and analog functions.
Unlike conventional gate arrays,programmable gate arrays
require no fixed costs, and no custom factory fabrication. Since
each device is identical, manufacturing costs follow the same
learning curve as other high-volume standard product ICs.
GATE
ARRAYS
Gate arrays implement user logic by interconnecting transistors
or sim pIe gates into more complex functio~sduring the last
stages of the manufacturing process. Gate arrays offer densitieE
up to 100,000 gates or more, with utilization of 80-90% for
smaller devices, and 40-60% for the largest.
Unlike standard IC products, gate array costs include fixed
costs as well as the production cost per unit. Gate arrays
become cost effective when production volumes are high
enough to provide a broad base for amortization of fixed costs.
PLDs are often used in place of fiveto ten SSIjMSI devices,
and are the most efficient ASIC solution for densities up to a
few hundred gates. Programmable Logic Devices (PLDs)
include a number of competing alternatives, all based on variations of AND-OR plane architectures. The primary limitations of the PLD architecture are the number of flip-flops, the
nUl;nqer of input/out~utsignals, and the rigidity of the ANDOR plane logic and its interconnections. The use of one function often precludes the use of many other similar functions.
1-3
II
Introduction to Programmable Gate Arrays
PROGRAMMABLE GATE ARRA Y ARCHITECTURE
l:.
Xilinx's proprietary Logic Cell Array architecture
is similar to that of other gate arrays, with an interior matrix of logic blocks and a surrounding ring of
I/O interface blocks. Interconnect resources occupy the
channels between the rows and columns of logic blocks,
and between the logic blocks and the I/O blocks.
Like a microprocessor, the Logic Cell Array (LCA) is
a program-driven logic device. The functions of the
LCA's configurable logic blocks and I/O blocks, and
their interconnection, are controlled by a configuration
program stored in an on-chip memory. The configuration program is loaded automatically from an external
memory on power-up or on command, or is programmed by a microprocessor as a part of system
initialization.
Logic Cell Array performance is determined by the
speed of logic, storage elements, and programmable
interconnect. LCA performance is specified by the
maximum toggle rate for a logic block storage element
configured as a toggle flip-flop. For typical applications, system clock rates are one-third to one-half the
maximum flip-flop toggle rate.
DO
00
0
0
0
0
0
0
00
0
00
0
0
0
°00
0
0
DO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
00
0
0
0
0
00
0
0
0
0
00
0
0
0
00
0
00
°
00
0
00
°DO 0 0 0 0 0 0 0 0 0
°0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
DOD
1101 02
0
-:~
----:..
~···jf······················ ~:""".
:D-= o. _ _ _ _ _ _
~
1101 04
1101 03
CONFIGURABLE
LOGIC BLOCK
The core of the Logic Cell Array is a
matrix of identical Configurable Logic
Blocks (CLBs). Each CLB contains programmable combinatorial logic and
storage registers. The combinatorial
logic section of the block is capable of
implementing any Boolean function of
its input variables. The registers can be
loaded from the combinatorial logic or
directly from a CLB input. The register
outputs can be inputs to the combinatorial logic via an internal feedback path.
0
INPUT/OUTPUT
BLOCK
The periphery of the Logic Cell Array is
made up of user programmable Input/
Output Blocks (lOBs). Each block can be
programmed independently to be an input, an output, or a bi-directional pin
with three-state control. Inputs can be
programmed to recognize either TTL or
CMOS thresholds. Each lOB also
includes flip-flops that can be used to
buffer inputs and outputs.
1-4
'"
0
1101 05
INTERCONNECT
The flexibility of the LCA is due to resources that permit program control of
the interconnection of any two points on
the chip. Like other gate arrays, the
LCA's interconnection resources include
a two-layer metal network of lines that
run horizontally and vertically in the
rcws and columns between the CLBs.
Programmable switches connect the
inputs and outputs of lOBs and CLBs to
nearby metal lines. Crosspoint switches
and interchanges at the intersections of
rows and columns allow signals to be
switched from one path to another.
Long lines run the entire length or
breadth of the chip, bypassing interchanges to provide distribution of critical
signals with minimum delay or skew.
XC2000
PROGRAMMABLE GATE ARRAY FAMILY
The XC2000 series of programmable gate arrays was
introduced in 1985. Price reductions since that time have
reflected steadily increasing production volumes. The
family includes two compatible arrays: the XC2064 with
1200 gates, and the XC2018 with 1800 gates.
II
FEATURES
o
Fully user-programmable:
• I/O Functions
• Logic and storage functions
• Interconnections
o
o
Three performance options: 33,50, and 70 MHz toggle rates
o
TTL or CMOS input thresholds
Three package types:
Dual In-line Package
Plastic Leaded Chip Carrier
Pin Grid Array
THE XC2000 FAMILY OF PROGRAMMABLE GATE ARRAYS
Number of gates
Configurable Logic Blocks
Combinatorial Logic Functions
Latches and flip-flops
Input/Outputs
XC2064
XC2018
1200
64
128
122
1800
58
74
XC1736
CMOS SERIAL CONFIGURATION PROM
The 1736 Serial Configuration PROM is a companion device that
provides permanent storage of LCA configuration programs. It can
be used whenever a dedicated device is preferable to sharing of a
larger EPROM, or to loading from a microprocessor.
FEATURES
o
o
o
o
o
o
o
One-Time Programmable (OTP) 36,288 bit serial memory designed to
store configuration programs for Programmable Gate Arrays
Simple interface to a Logic Cell Array (LCA) requires only two I/O pins
Daisy chain support for multiple devices
Cascadable for large arrays or manyLCAs
Storage of multiple configurations for a single LCA
Low power CMOS EPROM process
Space-efficient, low-cost 8-pin DIP packages
1-5
100
200
174
Introduction to Programmable Gate Arrays.
XC3000
PROGRAMMABI.E GATE ARRAY FAMII.Y
The XC3000 series is a second generation family of CMOS programmable gate
arrays that includes five compatible
members with logic densities from 2000
to 9000 gates.
FEATURES
o
Fully user-programmable:
• I/O Functions
• Logic and storage functions
• Interconnections
o
Five member product family
.2000-9000 gates
• Compatibility for ease of design migration
o
Two performance options:
.50 and 70 MHz toggle rates
o
Second generation afthitecture
• 5-input logic functions
.2 flip-flops per CLB/IOB
• Enhanced routing resources
• Three-state drivers for wide ANDs
o
o
Programmable voltage slew rates on outputs
Three package types:
• Plastic Leaded Chip Carrier
• Pin Grid Array
• Quad Hat Package
The XC3000 Family of Programmable Gafe Arrays
Number of gates
Combinatorial Logic Functions
Latches and flip-flops
Input/Outputs
1-6
XC3020
XC3030
XC3042
2000
128
256
64
3000
200
360
80
4200
288
480
96
XC3064 XC3090
6400
,448
688
120
9000
740
928
144
DEVELOPMENT SYSTEMS
Designing with Xilinx Programmable Gate Arrays is similar to designing with other gate arrays. Designers can use familiar CAE tools for
design entry and simulation. The open Xilinx development system
includes a standard netlist format, the Xilinx Netlist File (XNF), that
provides a bridge between schematic editors or simulators, and the Xilinx
XACT software for design implementation and real time design verification. The Xilinx software is supported on the PCI AT and compatibles as
well as on popular engineering workstations.
II
Design Entry Software
DESIGN
ENTRY
j
consists of libraries and netlist interfaces for
standard CAE software such as FutureNet,
Schema II, OrCAD, Viewlogic, Daisy,
Mentor, Valid, CASE, and PALASM.
Programmable gate array libraries permit
design entry with standard TTL functions,
with Boolean equations, and with userdefined macros.
PALASMTM.
TO·XNF
TRANSLATOR
Simulation Software
includes models and netlist interfaces to
standard simulator software, such as SILOS
and CADAT, that is used for logic and timing
simulations.
Design Implementation
Software
DESIGN
IMPLEMENTATION
IN·CIRCUIT
DESIGN
VERIFICATION
is used to convert schematic netlists and
Boolean equations into efficient designs for
programmable gate arrays. The software
includes programs that perform partitioning,
optimization, placement and routing, and
interactive design editing.
DESIGN EDITOR
TIMING CALCULATOR
DOWNLOAD CABLE
BITSTREAM GENERATOR
XACTORTM
DESIGN VERIFIER
DS21
DS26127/28
In-circuit Design
Verification Tools
permit real-time verification and debugging
of a programmable gate array design as soon
as it is placed and routed. Designers benefit
from faster and more comprehensive design
verification, and from reduced requirements
to generate simulation vectors to exercise a
design.
l:XILlNX
XC3020·70
PC6SC
X9201MB730
1101 06
1-7
Introduction to Programmable Gate Arrays
TECHNICAl. SUPPORT
SOFTWARE UPDATES
TECHNICAl. I.ITERATURE
Xilinx is continuing to improve the XACT development
system software, and new versions are released two-three
times per year. Updates are provided free of charge during
the first year after purchase, provided the user returns the
registration card. After the first year, users are encouraged to
purchase a Software Maintenance Agreement so that they will
continue to recieve software updates.
In addition to this databook, technical literature for the XiJinx
programmable gate array includes four volumes that are
delivered with every XACT development system.
o
User's Guide
The User's Guide is a collection of "how to" applications
notes on such subjects as getting started with an LCA
design, Boolean equation design entry, use of the simulator, placement and routing optimization, and LCA configuration.
o
Reference Manuals (2 vols)
The XACT Reference Manuals include a detailed description of each Xilinx software program.
o
Macro library
The Xilinx development system includes over 100 macros,
including counters, registers, and multiplexers. The macro
library manual includes schematics and documentation for
each macro.
XII.INX USER GROUP
Xilinx users are invited to attend training and information
exchange sessions that are held two-three times per year in
various locations worldwide. These User Group meetings are
intended for experienced users of Xilinx Programmable Gate
Arrays, and they emphasize the efficient use of the XACT
development system.
FIEI.D APPI.ICATIONS
ENGINEERS
Xilinx provides local technical support to customers through a
network of Field Applications Engineers (FAEs). For the
name and phone number of the nearest FAE, customers may
caJl one of the Xilinx sales offices listed in the back of this
book.
APPI.ICATIONS HOT I.INE
Xilinx maintains an applications hot line to provide technical
support to LCA users. This service is available from 8:00 am
to 6:00 pm Pacific Time. CaJl (408) 879-5199 or (800) 255-7778
and ask for Applications Engineering.
BUI.I.ETIN BOARD
To provide customers with up-to-date information and an immediate response to questions, Xilinx provides 24-hour access
to an electronic bulletin board. The Xilinx Technical bulletin
board provides the following services to all registered XACT
customers.
o
o
o
o
o
Read files from the bulletin board
Check current software version numbers
Download files
Upload files
Leave messages for other Bulletin Board Users.
1-8
&XlliNX
A Cost of Ownership
Comparison
CONTENTS
Programmable
Gate Arrays
Gate Arrays
Standard product
Off-the-Shelf delivery
Fast time to market
Programmed by the user
NoNRE
No inventory risk
Fully factory tested
Simulation useful
In-circuit design verification
Design changes anytime
Second source exists
Custom product
Months to manufacture
Manufacturing delays
Programmed in the factory
NRECosts
Design specific
User develops test
Simulation critical
Not possible
NRE charge repeated
Additional cost and time
Executive Summary
ROM vs. EPROM Analogy
Who Recognizes the Costs?
Total Cost Fixed Cost + (Variable Cost) (Units)
Fixed Development Costs for Gate Arrays
Simulation
Time to Design For Testability
NRECharges
Design Iterations
Test Program Development
Second Source
Summary of Fixed Development Costs
Variable Costs
Unit Cost (Cents/Gate)
Inventory
Yield to Production
Cost of Ownership Analysis
Breakeven Analysis
Time to Market
Product Life Cycles
References
=
Methodology
This analysis compares the total costs of custom gate
arrays with those of user programmable gate arrays. It
looks at the various categories of costs, both fixed and
variable, for devices from 2000 to 9000 gates, 90% of the
gate array market according to most studies.
Because the gate array has fixed or up-front development
costs (NRE, extra simulation time, generating lest vectors,
etc.) that the programmable gate array doesnot, its total
cost of ownership is higher until a sufficienf quantity is
purchased. This analysis allows the user to calculate
total cost of ownership at different quantities and
derive breakeven quantities-the volume below which
it is more cost effective to use the programmable gate
array (Breakeven Analysis). The overall objective is to
determine the production volumes at which each product
is most cost effective.
EXECUTIVE SUMMARY
Introduction
Custom or mask-programmed gate arrays have many
hidden costs beyond the obvious unit cost and NRE (nonrecurring engineering) charges. Most of these additional
costs are due to the fact that a gate array is a custom
integrated circuit, one manufactured exclusively for a
particular customer. Compared to a standard product,
there are many hidden expenses, both du';ng the design
phase and after purchase, beyond the direct device cost.
Executive Summary Conclusion
The choice between user and mask programmed gate
arrays must take into account more than the NRE and
cents/gate unit cost. The use of a custom product entails
many other costs and risks. Because of these fixed costs,
4t is less .expensiVe at lower volumes to use a standard
·product: a programmable gate array. Since many of the
User programmable gate arrays, on the other hand, are
high volume standard products-manufactured and fully
tested devices that are used by all customers. There is no
customization of the silicon.
1-9
II
A Cost of Ownership Comparison
hidden costs of using a custom gate array do not accrue
to anyone department, only the project manager can
recognize the total cost.
multiplied by the number of units. At lower volumes, the
custom gate array is more expensive because of fixed
costs that are incurred even if no units are purchased. The
programmable gate array project cost starts at zero, but
rises faster because of a higher cost per-unit. In this case
the breakeven volume is between 10k and 20k units. This
paper will discuss the various components of this analysis
and show the user how to make a similar calculation for a
specific situation.
Similar considerations have led to the widespread acceptance of EPROM memories as compared to ROMs,
despite a higher EPROM cost per unit. The same factors
can be applied in the choice of a gate array.
Figure 1 shows a representative breakeven graph for a
2000 gate device. The data are for 1990. The vertical axis
shows the total project cost-fixed costs plus unit costs
Several significant factors are omitted from this graph.
First, the additional fixed costs (NRE, simulation) of bringing on a custom gate array second source are not included.
Second, and much more important, the cost of the longer
time to market when designing with the mask gate array is
not included. This factor is reviewed in Time to Market.
Both of these factors would raise the custom gate array
curve and increase the breakeven quantity. In other
words, the programmable gate array would be more cost
effective at an even higher production volume.
TOTAL
PROJECT
COST ($)
~~Th~~~}
NRE
SIMULATION TIME
DESIGNING TESTABILITY
TEST PROGRAM
DESIGN ITERATIONS
ROM VS. EPROM ANALOGY
~
There is a relevant historical precedent for the use of a
flexible standard product instead of a custom product with
a lowerdirectcost perunit. While EPROMs have a cost per
bit that is 2 to 3 times that of ROMs, they have consistently
captured almost half the programmable memory market,
measured in bits shipped. See Figure 2. Many of the reasons forthe use of EPROMs are the same as those forthe
use of programmable gate arrays: faster time to market,
_ _ _ _ _ _ _ _ _ __
20K
10K
PROJECT UNITS
110201
-
CUSTOM GATE ARRAY
PROGRAMMABLE GATE ARRAY
Figure 1. Typical Breakeven Analysis 2000 Gates-1990
ROM/EPROM ANALOGY
140
120
100
TERABITS
SHIPPED
80
•
ROM
60
IlllI
EPROM
40
20
0
1983
1984
1985
1986
1987
1988
1989
EPROM MIL¢lBIT 10.9
ROM MIL¢lBIT 4.5
9.2
3.2
4.0
1.7
2.5
1.0
1.8
0.7
1.3
0.5
0.9
0.4
2.9
2.4
2.5
2.6
2.6
2.3
RATIO
2.4
SOURCE:DATAQUEST
Figure 2. ROM/EPROM Analogy
1-10
110205
design is all-or-nothing. Simulation is a useful tool with
programmable gate arrays, but it is a critical one with gate
arrays, and the designer can expect to spend more time
simulating a custom gate array design. The programmable gate array designer can count on in-circuit
verification and on-line changes if necessary.
lower inventory risk, easy design changes, faster delivery,
and second sources. The higher price per bit is offset by
the elimination of inventory and production risks.
Gate arrays have even more disadvantages versus programmable gate arrays than do ROMs versus EPROMs.
The upfront design time, risk, and expense of ROMs is
minimal, while that of gate arrays is substantial. ROM test
tape generation is automatic, while that for gate arrays requires extensive engineering effort. Therefore, programmable gate arrays may be even more widely used versus
gate arrays than are EPROMs versus ROMs.
Gate array simulation cost includes both computer time
charges and the time of the engineer doing the simulation.
While the gate array vendor mayor may not charge explicitlyforcomputertime, an estimate wou Id be $5,000 and 2.5
manweeks of simulation effort for a 2000 gate array, and
$10,000 and 7 manweeks for a 9000 gate array. This
compares to 0.5 and 1 week for the programmable gate
array, with no Simulation charge.
WHO RECOGNIZES THE COSTS?
Many of the elements of the total cost of ownership for a
gate array do not accrue to a single department, and often
are not fully recognized. For example, the additional engineering time needed to design for testability may not be
seen by purchasing. The inventory costs of a custom product may not be recognized by the design department.
However, these are real costs, and they influence the
profitability of the product and company. The person
making the choice between custom gate arrays and
programmable gate arrays should consider the total
costs of ownership for each alternative.
.
Typically one fully burdened manweek, including computer support, costs about $2000.
2000 Gates
9000 Gates
Gate Array
Simulation Charge
Man Weeks
$SK
$10K
2.SMW
7MW
None
O.SMW
None
1MW
Programmable Gate Array
Simulation Charge
Man Weeks
TOTAL COST = FIXED COST +
(VARIABLE COST)(ONITS)
The total costs of using a product can be separated into
two components. The first is the fixed costs: upfront development costs that are independent of volume. Some
examples of these for gate arrays are the masking charge,
simulation charge, and test program development. Due to
amortization of these costs, the user's cost per unit can be
very high until a sufficient volume of units is purchased.
The second component of total cost is the variable cost,
the incremental cost per unit. Besides the obvious unit
cost, another element of variable cost is inventory cost.
Time to Design for Testability
One key to getting a successful gate array the firsttime is to
focus on testing issues. The user must guarantee that the
device can be fully tested in a reasonable amount of time.
Since the gate array vendor's only guarantee is that the
device will pass the test program, the user must be certain
that if the IC meets the user-generated test specifications,
it will work in the circuit.
Spending extra time in the design phase provides insurance that the device can be tested. A 1987 Dataquest
ASIC Market Report observes that "an engineer can sit
down at a $20,000 CAE/CAD station and design a
$1,000,000 test problem." Designing in testability may
also be the only way to provide for testing of complex
sequential circuitry, or elements like long counters.
Therefore the gate array designer must spend additional
time in the design phase. An estimate is 1 additional week
for a 2000 gate arraY,and 2 additional weeks for a 9000
gate array.
This analysis will examine costs by these two categories.
Fixed costs are summarized first, then variable costs.
They are added to produce total cost.
FIXED DEVELOPMENT COSTS
Simulation
With a custom product, it is critical that the device work the
first time. Otherwise, the user must pay to have the device
prototyped a second time and will incur the manufacturing
delay a second time. Custom gate arrays do not support a
conventional, iterative, modular design process-the
The programmable gate array is a standard product with
no incremental test costs. It is fully tested by Xilinx before
shipment. No application specific testing is needed.
1-11
•
A Cost of Ownership Comparison
Gate Array Incremental Cost
Gate Array Incremental Cost
2000 Gates
9000 Gates
1 Man Week
2 Man Weeks
50%
Probability
of
(original NRE time and cost + one half of
original simulation time and cost)
Test Program Development
NRE Charges
As noted in Time to Design forTestability, testability is critical to production success for gate arrays. Gate array vendors rarely make production errors, but faulty devices may
not be detected because the test vectors are not
comprehensive.
NRE (Non-Recurring Engineering) charges cover the online vendor interface, design verification, mask charges,
prototype samples and a nominal simulation (pre- and
post-layout) time. The charges may vary with estimated
production volumes. At volumes below 50,000 units,
$15,000 to $20,000 is a competitive quote for lower density
gate arrays. At the 9000 gate level, NRE charges may be
in excess of $30,000.
The estimate for test vector development is 2 weeks for a
2000 gate array, and 4 weeks for a9000 gate array. Since
the programmable gate array is a standard product, it is
fully tested at the factory. No application-specific testing is
needed.
There are no NRE charges for programmable gate arrays.
The entire design process is done by the customer. Programmable gate array software tools run on common
workstations and personal computers, and are much less
expensive than comparable tools for custom gate arrays.
A risk that the program manager should consider involves
the level of experience or knowledge that the design team
has with test development. lithe first pass design is unsuccessful, how much time and effort will be required to debug
the problem? Both additional cost and time to market are
at risk.
Typical Gate Array NRE for 10,000to 50,000 units
2000 Gates
9000 Gates
Gate Array Incremental Cost
$15K-$20K
$30K-$40K
2000 Gates
9000 Gates
Design Iterations
2 Man Weeks
4 Man Weeks
The phrase 'We need to add this feature" is all too common
to the designer of electronic equipment. Designers often
find themselves faced with the need to modify a design
during prototyping or initial customer evaluation. Changes
may be required to add features or reduce costs. As
systems become more complex, "bugs" can be more
prevalent.
Second Source
If a second source is required, the gate array designer
must identify a compatible vendor and resubmit the
design. This involves another NRE charge and time for
translating logic and resimulation. The model used here is
the NRE charge plus one half the simulation cost.
Design iterations are almost never due to the failure of the
gate array vendor. Rather, it is a risk associated with the
choice of an inflexible technology in a very dynamic industry.
Programmable gate arrays are standard products that already have a second source.
Gate Array Incremental Cost
Industry data suggest that about half of all gate array designs are modified before they are released to production.
When a modification is required, NRE costs are incurred
forthe second pass. Since resimulation is likely to involve
less effort than the initial simulation, 25% (50% probability
times one half the effort) of the simulation cost is added.
NRE
Simulation
Charge
Man Weeks
1-12
2000 Gates
9000 Gates
$15K-$20K
$30K-$40K
$2.5K
1MW
$5K
3MW
--------- - - - -
Summary of Gate Array Fixed Development Costs
volume will be purchased. Since programmable gate
arrays are newer products, their cost is declining at a
steeper rate than gate arrays. They are in the introduction
phase of their life cycle, while gate arrays are in a more
mature phase of the cycle. Price comparisions should be
based on projections overthe production life ofthe product.
The summary in Table 1 shows typical fixed costs for both
a 2000 gate and a 9000 gate array. Since assumptions
may vary, a blank column is provided as a worksheet.
VARIABLE COSTS
A standard product has more silicon content and less factory overhead than a custom product. Since all customers
buy the same product, there is more of the semiconductor
leaming curve with cumulative volume. Given the
profitability levels of array manufacturers, gate array
prices may decline only slightly over time and could even
rise.
Production Unit Cost (Cents/Gate)
Gate array prices are often quoted in terms of cents per
gate. For 1.5 micron, 2000 gate arrays, at the volumes
considered in this analysis (10,000 to 30,000 units), a
figure of 0.15-0.20 cents/gate (without package) is typical.
At similar volumes, the cost per gate (without package) for
a programmable gate array is 2-3 times the cost of a custom gate array. For reasons explained below, this gap is
expected to narrow over the next few years. All of the
cents/gate numbers are for die only. Since CMOS gate
arrays and programmable gate arrays use the same packages, the package adders are equivalent.
1990 Programmable Gate Array Unit CostsWithout Package
An important consideration in calculating the total cost of
ownership is the year during which most of the production
1. Simulation
NRE
Man Weeks
2. Design for Testability
3. NRE Charges
4. Design Iterations @ 50% probability
NRE
Man Weeks
5. Test Program Development
6. Second Source (NRE + 50% SIM)
NRE
Man Weeks
Total Without Second Source
NRE
Man Weeks
Total With Second Source
• NRE
Man Weeks
Total Fixed Costs@ $2K!MW
Without Second Source
With Second Source
Programmable
(Cents/Gate)
Typical
2000 Gates
Typical
9000 Gates
$5,000
2MW
1MW
$15K-$20K
$10,000
6MW
2MW
$30K-$40K
$11,250
0.5MW
2MW
$22,500
1.5MW
4MW
$20,000
1MW
$40,000
3MW
$33,750
5.5MW
$67,500
13.5 MW
$53,750
6.5MW
$107,500
16.5 MW
$44,750
$66,750
$94,500
$140,500
2000
Gates
4000
Gates
9000
Gates
20KUOty
0.30-0.40
10KUOty
0.35-0.45
10KUOty
0.50-0.60
Customer
Application
@$-,MW
Table 1. Typical Fixed Costs
1-13
•
A Cost of Ownership Comparison
volume applications, few gate arrays are retooled to take
advantage of process advances. The time from design
start to end of production lifetime is usually several years.
Overthis period, the programmable gate array will move to
successively more advanced processes, resulting in
steadily decreasing costs. By the end of the production
lifetime, the programmable gate array will be several processes ahead and the cost difference will be reduced
significantly.
Process Technology
There are also technology reasons forthe steeper decline
in cost of the programmable gate array. Figure 3 shows
that the processes used for logic IC's, including gate
arrays, typically lag behind those used for memory IC's.
Since the programmable gate array is a standard IC built
on a memory process, it can take advantage of each new
process to shrink the die and reduce costs.
With a conventional gate array, the process that is available at the time of design is usually used throughout the
production lifetime of the product. Except for very high
Pad-Limited Die Sizes
As gate arrays and programmable gate arrays grow in I/O
pin count, a phenomenon known as "pad-limiting" is more
likely to occur. The spacing between I/O pads is determined by mechanical limitations of the equipment used for
lead bonding. In I/O intensive applications the number of
pads around the outer edge of the die determines the die
size, instead of the number of gates. See Figure 4. In I/O
intensive applications, a "cost per 1/0" may be a more
useful measure than "cost per gate."
(2.0~)
MEMORIES
For a given 1/0 count, in the pad-limited case the programmable gate array and the gate array would be the same die
size. As a result, the highervolume, standard product, programmable gate array could actually be less expensive on
a per-unit basis than the custom product gate array. There
would be no breakeven quantity-the programmable gate
array would have a lower cost of ownership at all volumes.
0.1 L-..l...-...L-L-L---1---l_L-..l...-...L-L---L--1_L-L-l
ro
~
~
~
M
~
M
~
M
~
00
~
~
~
~
~
YEAR
110202
Figure 3. Process Evolution
PAD LIMITED DIE
350 , - - - - - - - - - - - - - .
300
1---------/--7fI'.;~--l
2501--------:.J;£-----l
/~/""--------I
DIE 200 1 - - - - WIDTH
/'
MILS 1 5 0 I - - / - - : . J t f L - - - - - - - - - l
100 1-~~---------_1
501------------_1
000000000000000
o
o
o
o
0
0
0
0
§ 1'111 §
o
o
o
o
o
0
0
0
0
0
000000000000000
ol-~--._--r__,--,__,--~
40
60
80
100
120
140
160
180
NUMBER OF PADS
110203
Figure 4. Minimum Die Size vs. 1/0
1-14
mum economical wafer lot quantity. Inventory is created
and costs are incurred. Moreover, there is the problem of
inventory ownership if the parts are never ordered by the
customer.
Effect of Die Cost on Total Cost
Figure 5 illustrates a third point about the capability of programmable gate arrays to narrow the cost difference with
custom gate arrays. The chart shows the contribution to
total device cost of wafer, die, assembly and test. Wafer
cost represents about 20% to 40% of the total device cost,
and die cost about 30% to 50%. A 50% difference in die
cost-between a gate array and a programmable gate
array-shown in the chart translates to only a 20% difference (80 vs. 100) in total cost by the time the device has
been tested. This comparison is based on production of
the programmable gate array in a more advanced process
than the custom gate array, as discussed in Unit Cost
(Cents/Gate).
Although the safety stock reserve is a function ofthe cost of
the product itself, a figure of 10% is reasonable for gate
arrays that have unit costs under $25.00. In comparison,
since changes to programmable gate arrays can be made
in software in minutes, and since only one part type is
widely stocked, the comparative safety stock reserve
is 0%.
Gate Array Incremental Inventory Cost
10% Additional Unit Cost
Inventory ReserveS
Inventories include extra devices ordered and stocked to
cover contingencies. For a custom product this is the only
way parts can be delivered in less than the normal productiontime (2-4 months). Contingencies are often thought of
in terms of negative events like a defective lot or manufacturing shortfalls.
YIELD TO PRODUCTION
Due to rapidly changing markets, many designs never go
into production. Sometimes acompanywill develop competing projects, with only one moving to production. Many
times the market will change, or competition will emerge,
and projects will be cancelled or redirected. Of course
each design team expects that its project will succeed, but
in the aggregate this is not true. If a company chooses gate
arrays as the primary logic technology, and starts many
designs, this factor will occur.
However, contingencies also include positive events like
stocking for large, upside orders or where demand is
difficult to estimate. This can be especially true during a
product's introduction, when design changes and demand
spikes occur simultaneously.
The March, 1986 Technology Research Letter states that
only 1/3 of gate array designs go into production. The 1987
Dataquest ASIC and Standard Logic Semiconductor Volume 1 reports 50% go into production. With 50%, the true
cost of the gate array should recognize additional costs for
simulation, designing for testability, and NRE. For 2000
gates, using the numbe.rs in Summary of Fixed Development Costs, this would mean an additional ($5,000 + 3 MW
+ $17,500). For 9000 gates the number is ($10,000 +
8 MW +$35,000).
With a custom product it is also necessary to build inventory as the product nears the end of its life cycle. Demand
is low and difficu It to forecast, and it may not be possible to
reorder a small quantity. Spares and replacements must
be stocked. A JIT inventory system is less practical.
Since minimum manufacturing quantities for semiconductors· are determined by wafer lots, a custom product will
have excess WIP (work in process) or finished goods
inventory.if the desired order quantity is less than the mini-
100
"#-
80
§
60
~
40
•
o
GATE ARRAY (211)
PROGRAMMABLE GATE ARRAY (ql1)
w
w
a:
20
110204
WAFER
DIE
ASSEMBLY
TEST
Figure 5. Relative Manufacturing Cost by Stage of Completion
1-15
II
A Cost of Ownership Comparison
Gate Array Incremental Cost
mary of Fixed Development Costs}. Therefore, at lower
unit volumes the programmable gate array is less expensive, until the gate array can amortize the upfront fixed
costs.
Simulation Cost + Time to Design for Testability + NRE Cost
COST OF OWNERSHIP ANALYSIS
Table 2 is a form that can be used for calculating the total
cost of ownership at various volumes. Table 2 pOints tothe
"breakeven quantity"-the quantity where the unit cost of
the two devices is the same-of the next section.
While gate arrays have a lower unit cost, they have incremental fixed costs that must be incurred before the first unit
is received. Example costs are shown in Table 1 (Sum-
Project Quantity
1,000
5,000
Gate Array-No second source
1. Fixed costs from Table 1
2. Unit cost
3. Inventory reserves: (Line 2)(1.1)
4. Total variable cost = (Line 3)(Qty)
5. Total cost = Line 1 + Line 4
6. Unit cost = Line S/aty
Gate Array-second source
7. Fixed costs from Table 1
8. Second source costs
9. Total fixed costs
10. Total variable cost-Line 4 above
11. Total cost = Line 9 + Line 10
12. Unit cost = Line II/Qty
Programmable Gate Array
13. Unit cost
Table 2. Total Cost VS. Volume Purchased
1-16
10,000
20,000
E:XILINX
BREAKEVEN ANALYSIS
$2,000 product that has 15% profit margins. For 10,000
units sold:
Figure 6 is a graphical representation ofthe breakeven calculation for the case of 2000 gates, 1990 pricing, and no
second source. Upto the breakeven unit volume, the programmable gate array solution has a lower total project
cost.
Lost Profit = $2,000 x 10,000x 15%x 113= $1.0 million or
$100 per device
At the 9000 gate level, assume the gate array is used in a
$10,000 product that has 20% profit margins. For 2000
units sold:
Similar graphs can be built for different assumptions by
filling in Table 1. Forthe gate array, the breakeven graph is
merely line 5 or line 11 plotted versus quantity. For the
programmable gate array, it is line 13 times the quantity
plotted versus the quantity.
Lost Profit = $10,000 x 2, 000 x 20% x 113 = $1.33 million or
$667 per device
Note that these catastrophic costs are not included in any
of the previous sections. They are a quantitative estimate
of the risk of using a custom product.
TOTAL
PROJECT
COST ($)
PRODUCT LIFE CYCLES
In the electronics industry the lifet.imes of products are
shrinking. In the personal computer industry it is not uncommon to find product upgrades within.6-12 months.
This means that the volumes associated with anyone gate
array design can be much smaller than anticipated, even if
the end product still exists. It alsomeans that it is critical to
achieve a rapid design time.
r.m~=}
NRE
SIMULATION TIME
DESIGNING TESTABILITY
TESTPROORAM
DESIGN ITERATIONS
~--------~--------~
10K
20K
The numbers used for Figure 1 show that 2000 gate programmable gate arrays are more economical at volumes
up to 10,000 to 20,000 units. These volumes will represent
an increasing number of products.
PROJECT UNITS
110201
-
CUSTOM GATE ARRAY
PROGRAMMABLE GATE ARRAY
REFERENCES· .
Figure 6. Typical Breakeven Analysis 2000 Gates-1990
1. Technology Research Group Letter, March 1986,
page 7.
TIME TO MARKET
2. Dataquest Inc., Gate Arrays-Product Analysis,
page 3. ASIC and Standard Logic Semiconductors.
1987.
There are numerous examples of products.that failed due
to late market entry. A study by McKinsey & Co. stated that
a product that is six months late to market Will miss out on
1/3 ofthe potential profit overthe product's lifetime. Ifthere
is any problem in simulation, or any iteration of the gate
array deSign, then a gate array would easily add six
additional months to a product schedule.
3. Reinertsen. Donald G ....Whodunit? The Search forthe
New-Product Killers." Electronic Business, July 1983.
pages 62-66.
4. Integrated Circuit Engineering Corp .• ASIC Outlook,
1987.
At the 2,000 gate level, assume the gate array is used in a
1-17
•
I:XILINX
The Programmable Gate Array Company
1-18
SECTION 2
Product Specifications
1
2
Programmable Gate Arrays
•
Product' Specifications
3
Quality, Testing, Packaging
4
Technical Support
5
Development Systems
6 Applications
7
Article Reprints
8
Index
•
•
•
•
•
•
Product Specifications
XC3000 Logic Cell Array Family
Features, Description, Architecture ............................................... 2-1
Interconnect ................................................................................... 2-7
Internal Buses ................................................................................ 2-11
Programming ................................................................................. 2-14
Special Configuration Functions .................................................... 2-21
Performance .................................................................................. 2-24
Power ............................................................................................. 2-26
Component Selection, Ordering Information ................................. 2-29
Pin Descriptions ............................................................................. 2-30
Parametrics .................................................................................... 2-38
Package Dimensions ..................................................................... 2-48
XC2064, XC2018 Logic Cell Arrays
Features, Description, Architecture ............................................... 2-55
Interconnect ................................................................................... 2-59
Power ............................................................................................. 2-64
Programming ................................................................................. 2-66
Performance .................................................................................. 2-72
Pin Descriptions ............................................................................. 2-78
Parametrics .................................................................................... 2-82
Component Selection, Ordering Information ................................. 2-29
Package Dimensions ..................................................................... 2-92
Military Logic Cell Arrays
XC2018B ....................................................................................... 2-95
XC3020B ....................................................................................... 2-99
XC3090B ....................................................................................... 2-125
Serial Configuration PROM
XC1736 Features, Descriptions ..................................................... 2-139
Parametrics .................................................................................... 2-144
Ordering Information, Package Dimensions .................................. 2-149
XC1764 Advance Information ........................................................ 2-150
Sockets ............................................................................................... 2-151
LCA Component Selection, Ordering Information ............................... 2-152
1962
XC3000
Logic Celi™Array Family
Product Specification
The Logic Cell Array's user logic functions and interconnections are determined by the configuration program
data stored in internal static memory cells. The program
can be loaded in any of several modes to accommodate
various system requirements. The program data resides
externally in an EEPROM, EPROM or ROM on the application circuit board, or on a floppy disk or hard disk.
On-chip initialization logic provides for optional automatic
loading of program data at power-up. Xilinx's companion
XC1736 Serial Configuration PROM provides a very
simple serial configuration program storage in a one-timeprogrammable eight-pin DIP.
FEATURES
• High Performance-50, 70 and 100 MHz Toggle
Rates
• Second Generation User-Programmable Gate Array
• 1/0 functions
• Digital logic functions
• Interconnections
• Flexible array architecture
• Compatible arrays, 2000 to 9000 gate
logic complexity
• Extensive register and 1/0 capabilities
• High fan-out signal distribution
• Internal three-state bus capabilities
• TTL or CMOS input thresholds
• On-chip oscillator amplifier
• Standard product availability
• Low power, CMOS, static memory technology
• Performance equivalent to TTL SSIIMSI
• 100% factory pre-tested
• Selectable configuration modes
• Complete XACTTM development system
• Schematic Capture
• Automatic PlacelRoute
• Logic and Timing Simulation
• Design Editor
• Library and User Macros
• Timing Calculator
• XACTOR In-Circuit Verifier
• Standard PROM File Interface
Basic
Array
XC3020
XC3030
XC3042
XC3064
XC3090
Logic
Capacity
(usable
gates)
Configurable
Logic
Blocks
User
IIOs
Program
Data
(bits)
2000
3000
4200
6400
9000
64
100
144
224
320
64
80
96
120
144
14779
22176
30784
46064
64160
The XC3000 Logic Cell Arrays are an enhanced family of
Programmable Gate Arrays, which provide a variety of
logic capacities, package styles, temperature ranges and
speed grades.
DESCRIPTION
ARCHITECTURE
The CMOS XC3000 Logic Cell™ Array (LCA) family
provides a group of high-performance, high-density, digital, integrated circuits. Their regular, extendable, flexible,
user-programmable array architecture is composed of a
configuration program store plus three types of configurable elements: a perimeter of 1/0 Blocks, a core array of
Logic Blocks and resources for interconnection. The
general structure of a Logic Cell Array is shown in
Figure 1 on the next page. The XACT development
system provides schematic capture and auto place-androute for design entry. Logic and timing simulation, and incircuit emulation are available as design verification alternatives. The deSign editor is used for interactive design
optimizaton, and to compile the data pattern which represents the configuration program.
The perimeter of configurable I/O Blocks (lOBs) provides
a programmable interface between the internal logic array
and the device package pins. The array of Configurable
Logic Blocks (CLBs) performs user-specified logic functions. The interconnect resources are programmed to
form networks, carrying logic signals among· blocks,
analogous to printed circuit board traces connecting
MSIISSI packages.
The blocks' logic functions are implemented by programmed look-up tables. Functional options are implemented by program-controlled multiplexers. Interconnecting networks between blocks are implemented with
metal segments joined by program-controlled pass tran-
2-1
•
XC3000 Logic Cell Array Family
sistors. These functions of the Logic Cell Array are
established by a configuration program which is loaded
into an internal, distributed array of configuration memory
cells. The configuration program is loaded into the Logic
Cell Array at power-up and may be reloaded on command.
The Logic Cell Array includes logic and control signals to
implement automatic or passive configuration. Program
data may be either bit serial or byte parallel. The XACT
development system generates the configuration program
bit-stream used to configure the Logic Cell Array. The
memory loading process is independent of the user logic
functions.
ing cell data. The cell is only written during configuration
and only read during readback. During normal operation
the cell provides continuous control and the pass transistor is "off" and does not affect cell stability. This is quite
different from the operation of conventional memory devices, in which the cells are frequently read and re-written.
CONFIGURATION MEMORY
RW09~~
The memory cell output!) Q and Q use full Ground and Vcc
levels and provide continuous, direct control. The additional capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
The static memory cell used for the configuration memory
in the LogiC Cell Array has been designed specifically for
high reliability and noise immunity. Integrity of the LCA
configuration memory based on this design is assured
even under adverse conditions. Compared with other
programming alternatives, static memory provides the
best combination of high density, high performance, high
reliability and comprehensive testability. As shown in
Figure 2, the basic memory cell consists of two CMOS
inverters plus a pass transistor used for writing and read-
DATA
y-
•
_ CONTROL
1105 12
Figure 2. A static configuration memory cell is loaded
with one bit of configuration program and controls one
program selection in the Logic Cell Array.
CONFIGURABLE LOGIC
BLOCKS
y------- --------y-
O
.,
}--a
-I . ". . ". . . . . ,.,.,.,. ".1
THREE-STATE BUFFERS WITH ACCESS
TO HORIZONTAL LONG LINES
p y-
.------i·L.
a
'"
CONFIGURATION
0
y-
y-
1
o
y-
y-
.---------INTERCONNECTAREA-------~·
p
~-
n
u
p y-
~-
0
I
o
,;,..-,-.-.L---fL---I a: f--t'--..::::po""
w
f-
Z
~~L--¥_~~ f--~~L-~~
yC
y-
w
~~~---fL-~~ f--t'--~-~-~
~
p
~~~--~~~
L.L.
f-~-~-~~~
~-
Figure 1. The structure of the Logic Cell Array consists of a perimeter of programmable
110 blocks, a core of configurable logic blocks and their interconnect resources.
These are all controlled by the distributed array of configuration program memory cells.
2-2
I/O BLOCK
cell. Due to the structure of the configuration memory
cells, they are not affected by extreme power supply
excursions or very high levels of alpha particle radiation. In
reliability testing no soft errors have been observed, even
in the presence of very high doses of alpha radiation.
Each user-configurable I/O Block (lOB), shown in Figure 3,
provides an interface between the external package pin of
the device and the internal user logic. Each I/O Block
includes both registered and direct input paths. Each lOB
provides a programmable three-state output buffer which
may be driven by a registered or direct output signal.
Configuration options allow each lOB an inversion, a controlled slew rate and a high impedance pull-up. Each input
circuit also provides input clamping diodes to provide
electro-static protection, and circuits to inhibit latch-up
produced by input currents.
The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte wide
data. The internal configuration logic utilizes framing
information, embedded in the program data by the XACT
development system, to direct memory cell loading. The
serial data framing and length count preamble. provide
programming compatibility for mixes of various Xilinx
programmable gate arrays in a synchronous, serial, daisychain fashion.
The input buffer portion of each I/O Block provides thresh........................................................................................,.
PROGRAM·CONTROLLED MEMORY CELLS
THREE·
STATE
INVERT
OUT
INVERT
,"'" ",no
(OUTPUT ENABLE)
SLEW
RATE
PASSIVE
PULL UP
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o,,~," ~,
REGISTERED IN
OUTPUT
SELECT
.~~
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----+-----1 Q
VOPAD
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FLIP
FLOP
or
LATCH
R
.ok
=tJ--
.ik
L--'-_-+-_ _ _ _ _ _ _ _ (GLOBAL RESET)
~~~ · ~f-=. . .,. . P-RO-G-R-'-"-"-:-,-:-.-:-, -,-O-"-"-~-·,-· ~'" " ":~,~.-. ---~
110501
Figure 3. The IhpuVOutput Block includes input and output storage elements and I/O options selected by
configuration memory cells.
A choice of two clocks is available on each die edge.
The polarity of each clock line (not each flip·flop or latch) is programmable. A clock line that triggers the flip·flop
on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice versa.
Passive Pull·up can only be enabled on inputs, not on outputs.
All user inputs are programmed for TTL or CMOS thresholds.
2·3
•
XC3000 Logic Cell Array Family
Configuration program bits for each I/O Block control
features such as optional output register, logical signal
inversion, and three-state and slew rate control of the
output.
old detection to translate external signals applied to the
package pin to internal logic levels. The global input-buffer
threshold of the I/O Blocks can be programmed to be
compatible with either TTL or CMOS levels. The buffered
input signal drives the data input of a storage element
which may be configured as a positive edge-triggered "0"
flip-flop or a low level-transparent latch. The sense of the
clock can be inverted (negative edge/high transparent) as
long as all lOBs on the same clock net use the same clock
sense. Clock/load signals (I/O Block pins .ik and .ok) can
be selected from either of two die edge metal lines. I/O
storage elements are reset during configuration or by the
active low chip RESET input. Both direct input [from I/O
Block pin .1] and registered input [from I/O Block pin .q]
signals are available for interconnect.
The program-controlled memory cells of Figure 3 control
the following options:
• Logical Inversion of the output is controlled by one
configuration program bit per I/O Block.
• Logical three-state control of each I/O Block output
buffer is determined by the states of configuration program bits which turn the buffer on, or off, or select the
output buffer three-state control interconnection
[I/O Block pin .q. When this I/O Block output control
signal is HIGH, a logic "1", the buffer is disabled and the
package pin is high impedance. When this 110 block
output control signal is LOW, a logic "0", the buffer is
enabled and the package pin is active. Inversion of the
buffer three-state control logic sense (output enable) is
controlled by an additional configuration program bit.
For reliable operation inputs should have transition times
of less than 100 ns and should not be left floating. Floating
CMOS input-pin circuits might be at threshold and produce
oscillations. This can produce additional power dissipation and system noise. A typical hysteresis of about 300
mV reduces sensitivity to input noise. Each user I/O Block
includes a programmable high impedance pull-up resistor
which may be selected by the program to provide a
constant HIGH for otherwise undriven package pins. Although the Logic Cell Array provides circuitry to provide
input protection for electrostatic discharge, normal CMOS
handling precautions should be observed.
• Direct or registered output is selectable for each 110
block. The register uses a positive-edge, clocked flipflop. The clock source may be supplied [110 Block pin
.ok) by either of two metal lines available along each die
edge. Each ofthese lines is driven by an invertible buffer.
Flip-flop loop delays for the I/O Block and logic block flipflops are about 3 nanoseconds. This short delay provides
good performance under asynchronous clock and data
conditions. Short loop delays minimize the probability of a
metastable condition which can result from assertion of the
clock during data transitions. Because of the short loop
delay characteristic in the Logic Cell Array, the I/O Block
flip-flops can be used to synchronize external signals
applied to the device. Once synchronized in the I/O Block,
the signals can be used internally without further consideration of their clock relative timing, except as it applies to
the internal logic and routing path delays.
• Increased output transition speed can be selected to
improve critical timing. Slower transitions reduce capacitive load peak currents of non-critical outputs and
minimize system noise.
• A high impedance pull-up resistor may be used to
prevent unused inputs from floating.
Summary of I/O Options
• Inputs
• Direct
• Flip-flopllatch
• CMOSITTL threshold (chip inputs)
• Pull-up resistor/open circuit
Output buffers of the 110 Blocks provide CMOS-compatible 4 mA source-or-sink drive for high fan-out CMOS or
TTL compatible signal levels. The network driving I/O
Block pin .0 becomes the registered or direct data source
for the output buffer. The three-state control signal
[I/O Block pin.q can control output activity. An open-drain
type output may be obtained by using the same signal for
driving the output and three-state signal nets so that the
buffer output is enabled only for a LOW.
• Outputs
• Direct/registered
• Inverted/not
• Three-state/onloff
• Full speed/slew limited
• Three-state/output enable (inverse)
2-4
Each configurable logic block has a combinatorial logic
section, two flip-flops, and an internal control section. See
Figure 4. There are: five logic inputs [.a, .b, .C, .d and .e];
a common clock input [.k]; an asynchronous direct reset
input [.rdj; and an enable clock [.ec]. Allmaybedrivenfrom
the interconnect resources adjacent to the blocks. Each
CLB also has two outputs [.x and .y] which may, drive
interconnect networks.
CONFIGURABLE LOGIC BLOCK
The array of Configurable Logic Blocks (CLBs) provides
the functional elements from which the user's logic is
constructed. The logic blocks are arranged in a matrix
within the perimeter of I/O Blocks. The XC3020 has 64
such blocks arranged in 8 rows and 8 columns. The XACT
development system is used to compile the configuration
data which are to be loaded into 1he internal configuration
memory to define the operation and interconnection of
each block. User definition of configurable logic blocks
and their interconnecting networks may be done by automatic translation from a schematic capture logic diagram
or optionally by installing library or user macros.
Data input for either flip-flop within a CLB is supplied from
the function For G outputs ofthe combinatorial logic, orthe
block input, data-in [.dl]. Both flip-flops in each CLB share
the asynchronous reset [.rd] whic~, when enabled and
HIGH, is dominant over clogked inputs. All flip-flops are
......,.............................,..,.......................................................................................................................................................................................................................................·...·.......·........n.·•.•·.-..•..-...·.·.::;
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.
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.....w.·.·..·.·.·.·.·.·.·.·.·.·.·.·.··.,·.·.·.w.·.·.,w.·.·.vm.wu.w.•..w.•......•.•..w...w.w.wmm...wMwM..... .....
1105 02
Figure 4., Each Configurable Logic Block includes a combinatorial logic section,
two flip-flops and a program memory controlled muHiplexer selection of function.
It has: five logic variable inputs .a, .b, .c, .d and .e.
a direct data in .di
an enable clock .ec
a clOCk (invertible) .k
an asynchronous reset .rd
two outputs .x arid .y
2-5
~
:wouw""
•
XC3000 Logic Cell Array Family
ANY FUNCTION
OFUPT04
VARIABLES
F
+_
=-
CLOCK ENABLE=::::;-TFr:g~~~~~t)-_ _ _ _
PARALLEL E~t&~
TERMINAL
COUNT
DUAL FUNCTION OF 4 VARIABLES
ANY FUNCTION
OF UP TO 4
VARIABLES
DO~i=t::==~~'Qt~~
G
t-+++-+-h.c-,- - -
,
~l
!l
Sa
t. .,. . . . . . . . . . . . . . . . . . . . . . . . ..·.·.·.·.·.·.·.·u.....·•••·•·.·.•...•••.·.·... ..........................::
F
-01
ANY FUNCTION
OF 5 VARIABLES
01
G
'---
FUNCTION OF 5 VARIABLES
5b
,...... .
.......•
ANY FUNCTION
OF UPTO 4
VARIABLES
02
-
FUNCTION OF 6 VARIABLES
ANY FUNCTION
OF UPT04
VARIABLES
5c
1105 03
Figure 5
Figure 6. The C8BCP macro (modulo 8 binary counter
parallel enable and clock enable) uses one combinatoriallogic block of each option.
w~h
5a. Combinatorial Logic Option 1 generates two functions of
four variables each. One variable, A, must be common to
both functions. The second and third variable can be any
choice of of B, C, Ox and Oy. The fourth variable can be
any choice of 0 or E.
5b. Combinatorial Logic Option 2 generates any function of five
variables: A, 0, E and and two choices out of.B, C, Ox, Oy.
5c. Combinatorial Logic Option 3 allows variable E to select
between two functions of four variables: Both have common
inputs A and 0 and any choice out of B, C, Ox and Oy for the
remaining two variables. Option 3 can then implement some
functions of six or seven variables.
2-6
(as are block outputs) they are usable only for block
Input connection and not routing. Figure 8 illustrates
reset by the active low chip input, RESET, or during the
configuration process. The flip-flops share the enable
clock [.ee] which, when LOW, recirculates the t'lip-fiops'
present states and inhibits response to the data-in orcombinatorial function inputs on a CLB. The user may enable
these control inputs and select their sources. The user
may also select the clock net input [.k], as well as its active
sense within each logic block. This programmable inversion eliminates the need to route both phases of a clock
signal throughout the device. Flexible routing allows use
of common or individual CLB clocking.
routing access to logic block input variables,.control inputs
and block outputs. Three types of metal resources are
provided to accommodate various network interconnect
requirements:
• General Purpose Interconnect
• Direct Connection
• Long Lines (multiplexed busses and wide AND gates)
General Purpose Interconnect
The combinatorial logic portion of the logic block uses a 32
by 1 look-up table to implement Boolean functions. Variables selected from the five logic inputs and two internal
block flip-flops are used as table address inputs. The
combinatorial propagation delay through the network is
independent of the logic function generated and is spike
free for single input variable changes. This technique can
generate two independent logic functions of up to four
variables each as shown in Figure 5a, or a single function
of five variables as shown in Figure 5b, or some functions
of seven variables as shown in Figure 5c. Rgure 6 shows
a modu 108 binary counter with parallel enable. It uses one
CLB of each type. The partial functions of six or seven
variables are implemented using the input variable [.e] to
dynamically select between two functions of four different
variables. For the two functions offour variables each, the
independent results (F and G) may be used as data inputs
to either flip-flop or either logic block output. Forthe single
function of five variables and merged functions of six or
seven variables, the F and G outputs are identical. Symmetry of the F and G functions and the flip-flops allows the
interchange of CLB outputs to optimize routing efficiencies
of the networks interconnecting the logic blocks and 1/0
Blocks.
General purpose interconnect, as shown in Figure 9,
consists of a grid of five horizontal and five vertical metal
segments located between the rows and columns of logic
and I/O Blocks. Each segment is the "height" or ''width'' of
a logic block. Switching matrices join the ends of these
segments and allow programmed interconnections between the metal grid segments of adjoining rows and
columns. The switches of an unprogrammed device are all
non-conducting. The connections through the switch
matrix may be established by the automatic routing or by
using "Edit net" to select the desired pairs of matrix pins to
be connected or disconnected. The legitimate switching
matrix combinations for each pin are indicated in
Figure 10 and may be highlighted by the use of the show
matrix command in XACT.
INTERCONNECT
"PIPs"
SWITCHING
MATRIX
. r·.:/, . t-·.:
0·::···:·::0
.. . :
~-
...
PROGRAMMABLE INTERCONNECT
Programmable Interconnection resources in the Logic Cell
Array provide routing paths to connect inputs and outputs
of the I/O and logic blocks into logical networks, Interconnections between blocks are composed from a tWO-layer
grid of metal segments. Specially designed pass transistors, each controlled by a configuration bit, form programmable interconnect points (PIPs) and switching matrices
used to implement the necessary connections between
selected metal segments and block pins. Figure 7 is an
example of a routed net. The XACT development system
provides automatic routing of these interconnections.
Interactive routing (Editnet) is also available for design
optimization. The inputs of the logic or I/O Blocks are
multiplexers which can be programmed to select an input
network from the adjacent interconnect segments. As the
Figure 7. An XACT view of routing resources used to form a
switch connections to block inputs are unidirectional
typical interconnection network from CLB GA.
. t-·.;
··::0
.
...
....
:
t
L.:·:
CONFIGURABLE
LOGIC BLOCK
2-7
~-
4.: .:
INTERCONNECT
BUFFER
•
XC3000 Logic Cell Array Family
..
t· ..
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CLB lOGiC INPUTS
ClB CONTROL INPUTS
0:···
l- ...
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:'.' ·':'"·5
.. ...;.:.--~-d
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. . .. .. . .
t· ..
.
.
:0'
0'" . .... +-0·:
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':.".{5
...
:
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:
:
Figure 8. The Xilinx XACT Development System view of the
locations of interconnect access, ClB control inputs, logic inputs and outputs.
The dot pattern represents the available programmable interconnection points (PIPs).
Some of the interconnect "PIPs" are directional. This is indicated on the XACT design editor status line:
ND is a nondirectional interconnection.
D:H->V is a PIP which drives from a horizontal to a vertical line.
D:V->H is a PIP which drives from a vertical to a horizontal line.
D:C->T is a "T" PIP which drives from a cross of a T to the tail.
D:CW isa corner PiP which drives in the clockwise direction.
PO indicates the PIP is non-conducting, P1 is "on."
2-8
to its right and to the .C input of the CLB to its left. The.y
output can use direct interconnect to drive the .d input of
Special buffers within the general interconnect areas
provide periodic signal isolation and restoration for improved performance of lengthy nets. The interconnect
buffers are available to propagate signals in either direction on a given general interconnect segment. These bidirectional (bidi) buffers are found adjacent to the switching matricies, above and to the right and may be highlighted by the use of the "Show BIDI" command in XACT.
The other PIPs adjacent to the matrices are access to or
from long lines. The development system automatically
defines the buffer direction based on the location of the
interconnection network source. The delay calculator of
the XACT development system automatically calculates
and displays the block, interconnect and buffer delays for
any paths selected. Generation of the simulation nellist
with a worst-case delay model is provided by an XACT
option.
rV
~
2
4
~~
~=
6
8
~~~
11
Direct Interconnect
12
13
=~ =~
Direct interconnect, shown in Figure 11, provides the most
efficient implementation of networks between adjacent
logic or I/O Blocks. Signals routed from block to block
using the direct interconnect exhibit minimum interconnect
propagation and use no general interconnect resources.
For each Configurable Logic Block, the .X output may be
connected directly to the .b input of the CLB immediately
16
17
e
e =e~ •
15
19
1105 13
20
Figure 10. Switch matrix interconnection options for each "pin."
Switch matrices on the edges are different.
Use "Show Matrix" menu option in XACT
'::Ci :.
:
.' t· ..
~-
. ~q .
t·
t·.; .
..
:
:
'::[5
.' t
t- .. ; .:
0·:·::····
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..
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.
t- .. ;
..
0·····..
+- ...
t
..
~
MATRIX
GRID OF GENERAL INTERCONNECT
METAL SEGMENTS
':"5
:
l:
Figure 9. Logic Cell Array general-purpose interconnect is .
composed of a grid of metal segments which may be
interconnected through switch matrices to form networks for
CLB and 110 block inputs and outputs.
:
:.-:
El
Figure 11. The.x and .y outputs of each CLB have single
contact, direct access to inputs of adjacent CLBs.
2-9
XC3000 Logic Cell Array Family
GLOBAL BUFFER DIRECT INPUT
GLOBAL BUFFER INTERCONNECT
ALTERNATE BUFFER DIRECT INPUT
*UNBONDED lOBs (6 PLACES)
Figure 12. X3020 die edge I/O blocks are provided with direct access to adjacent CLBs.
2-10
A buffer in the upper left corner of the Logic Cell Array chip
drives a global net which is available to all.kinputs of logic
blocks. Using the global buffer for a clock signal provides
a skew-free, high fan-out, synchronized clock for use at
any or all of the I/O and logic blocks. Configuration bits for
the .k input to each logic block can select this global line or
another routing resource as the clock source for its flipflops. This net may also be programmed to drive the die
edge clock lines for I/O Block use. An enhanced speed,
CMOS threshold, direct access tothis buffer is available at
the second pad from the top of the left die edge.
the block immediately above and the .8 input of the block
below. Direct interconnect should be used to maxi mize the
speed of high performance portions of logic. Where logic
blocks are adjacent to I/O Blocks, direct connect is provided alternately to the I/O Block inputs [./] and outputs [.0]
on all four edges of the die. The right edge provides
additional direct connects from CLB outputs to adjacent
lOBs. Direct interconnections of I/O Blocks with CLBs are
shown in Figure 12.
Long Lines
A buffer in the lower right comer of the array drives a
horizontal long line that can drive programmed connections to a vertical long line in each interconnection column.
This alternate buffer also has low skew and high fan-out.
The network formed by this alternate buffer's long lines
can be selected to drive the .k inputs of the logiC blocks.
CMOS threshold, high speed access to this buffer is •
available from the third pad from the bottom of the right die
edge.
The long lines bypass the switch matrices and are intended primarily for signals which must travel a long
distance, or must have minimum skew among multiple
destinations. Long Lines, shown in Figure 13, run vertically
and horizontally the height or width of the interconnect
area. Each interconnection column has three vertical long
lines, and each interconnection row has two horizontal
long lines. An additional two long lines are located adjacent to the outer sets of switching matrices. In devices
larger than the XC3020, two vertical long lines in each
column are connectible half-length lines. On the XC3020
only the outer long lines are.
Internal Busses
A pair of three-state buffers is located adjacent to each
configurable logic block. These buffers allow logic to drive
the horizontal long lines. Logical operation of the threestate buffer controls allows them to implement wide multiplexing functions. Any three-state buffer input can be
selected as drive for the horizontal long line bus by
applying a low logic level on its three-state control line.
See Figure 15a. The user is required to avoid contention
which can result from multiple drivers with opposing logic
Long Ii nes can be driven by a logic block or 110 block output
on a column by column basis. This capability provides a
common low skew control or clock line within each column
of logic blocks. Interconnections of these long lines are
shown in Figure 14. Isolation buffers are provided at each
input to a long line and are enabled automatically by the
development system when a connection is made.
3 VERTICAL LONG LINES
BUFFER
~:::O···:::--::::: ~::O··:0-:: :~::O
.
..
':g ....... . ::: : 0··:::--:::::
....
..
.. ..
....
~... .::::;:.;:::
. ...
~
ON-CHIP
THREE STATE
BUFFERS
PULL-UP
RESISTORS (
FOR ON-CHIP
OPEN DRAIN
SIGNALS
66 ~bb
bb
~
GLOBAL
..
~ ~;:: ~::
. . .. . . .
:"
.
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~~~------~~~Da~------~~~-------r~~-4H---~~~
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2 HORIZONTAL LONG LINES
. t-.;
rsEt ...
':,"W ..
. t" .. ;
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W.··.·
.' t· ..
Figure 13. Horizontal and vertical long lines provide high fan-out, low-skew signal distribution in each row and column. The global
buffer in the upper left die corner drives a common line throughout the LCA.
2-11
XC3000 Logic Cell Array Family
levels. Control of the three-state input by the same signal
that drives the buffer input, creates an 'open drain' wiredAND function. A logical HIGH on both buffer inputs creates
a high impedance which represents no contention. A·
logical LOW enables the buffer to drive the long line low.
See Figure 15b. Pull-up resistors are available at each end
of the long line to provide a HIGH output when all connected buffers are non-conducting. This forms fast, wide
gating functions. When data drives the inputs, and separate signals drive the three-state control lines, these buffers form multiplexers (three-state buses). Inthis case care
must be used to prevent contention through multiple active
* FOUR OUTER LONG LINES ARE
CONNECTIBLE HALF-LENGTH LINES
o c:-
D
g.:.:."~F~~t#=~~~~~~~~===~*==
o
1/0 BLOCK CLOCK NETS
(2 PER DIE EDGE)
::p;-<,"-':7'••-;r-Ht-"'=:----Ht-=~-_tlII-:::=-''----lH-_:_:_.L...-_IlI__:_:_--L.-_flj_,_:_.-
HORIZONTAL
LONG LINES
THREE STATE
BUFFERS
*
Figure 14. Programmable interconnection of long lines is provided at the edges of the routing area. Three-state buffers allow the
use of horizontal long lines to form on-chip wired-AND and multiplexed buses. The left two vertical long lines per column
(except 3020) and the outer perimeter long lines may be programmed as connectible half-length.
(LOW1§=J
DN.
Figure 15a. Three-state buffers implement a Wired-AND function. When all the buffer three
state lines are HIGH, (high impedance), the pull-up resistor(s) provide the HIGH
output. The buffer inputs are driven by the control signals or a LOW.
I
1105 04
Figure 15b. Three-state buffers implement a Multiplexer where the selection is
accomplished by the buffer three-state signal.
2-12
complete in orderto allowthe oscillator to stabilize. Actual
internal connection is delayed until completion of configuration. In Figure 17 the feedback resistor, R1, between
output and input biases the amplifier at threshold. The
value should be as large as practical to minimize loading
of the crystal. The inversion of the amplifier, togetherwith
the R-C networks and an AT cut series resonant crystal,
produce the 360 degree phase shiftofthe Pierce oscillator.
A series resistor, R2, may be included to add to the
amplifier output impedance when needed for phase shift
control, crystal resistance matching, orto Iimitthe amplifier
input swing to control clipping at large amplitudes. Excess
feedback voltage may be corrected by the ratio of C2/C 1.
The amplifier is designed to be used from 1 MHz to onehalf the specified CLB toggle frequency. Use at frequen-
buffers of conflicting levels on a common line. Figure 16
shows three state buffers, long lines and pull-up resistors.
Crystal Oscillator
Figure 16 also shows the location of an internal high speed
inverting amplifier which may be used to implement an onchip crystal oscillator. It is associated with the auxiliary
buffer in the lower right corner of the die. When the
oscillator is configured by "MAKEBITS" and connected as
a signal source, two special user 1/0 Blocks are also configured to connect the oscillator amplifier with external
crystal oscillator components as shoWn in Figure 17. A
divide by two option is available to assure symmetry. The
. oscillator circuit becomes active before configuration is
BI-DIRECTIONAL
INTERCONNECT
BUFFERS
II I
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-
-
II I
3 VERTICAL LONG
LINES PER COLUMN
/
~
1
-
GLOBALNET\
k
L
L..::-"
~¥;l>
y.. -
.0
~ I' 00
eJeJ
tI:
J-
JI
e;Je;J 1
HORIZONTAL LONG LINE
V
V
fecc ~
~
'--
-p
~J
.0
HORIZONTAL LONG LINE
PULL-UP RESISTOR
:----~
OSCILLATOR
AMPLIFIER OUTPUT
DIRECT INPUT OF P47
TO AUXILIARY BUFFER
CRYSTAL OSCILLATOR
BUFFER
THREE-STATE INPUT
THREE-STATE CONTROL
THREE-STATE BUFFER
.q.ok
~
~
000 []
00
r- ALTERNATE BUFFER
~
\ OSCILLATOR
AMPLIFIER INPUT
Figure 16. An XACT Development System extra large view of possible
interconnections in the lower right corner of the XC3020.
2-13
•
XC3000 Logic Cell Array Family
cies below 1 MHz may require individual characterization
with respect to a series resistance. Crystal oscillators
above 20 MHz generally require a crystal which operates
in a third overtone mode, where the fundamental frequency must be suppressed by the R-C networks. When
the oscillator inverter is not used, these 1/0 Blocks and
their package pins are available for general user 1/0.
determined by the input levels of three mode pins; MO, M1
and M2.
In Master configuration modes the LCA becomes the
source of Configuration Clock (CCLK). The beginning of
configuration of devices using Peripheral or Slave modes
must be delayed long enough for their initialization to be
completed. An LCA with mode lines selecting a Master
configuration mode extends its initialization state using
four times the delay (43 to 130 ms) to assure that all daisychained slave devices which it may be driving will be ready
even if the master is very fast, and the slave(s) very slow.
Figure 18 shows the state sequences. At the end of Initiali-
PROGRAMMING
Initialization Phase
An internal power-on-reset circuit is triggered when power
is applied. When Vee reaches the voltage at which
portions of the LCA begin to operate (2.5 to 3 Volts), the
programmable 1/0 output buffers are disabled and a high
impedance pull-up resistor ·is provided for the user 1/0
pins. A time-out delay is initiated to allow the power supply
voltage to stabilize. During this time the power-down
mode is inhibited. The Initialization state time-out (about
11 to 33 ms) is determined by a 14-bit counter driven by a
self-generated, internal timer. This nominal 1 MHz timer is
subject to variations with process, temperature and power
supply over the range of 0.5 to 1.5 MHz. As shown in
Table 1, five configuration mode choices are available as
Table 1
MO M1 M2 Clock
0
0
0
0
0
0
1
1
0
0
1
Mode
0 active
1 active
0
1 active
0
1 passive
0
1 passive
Master
Master
reserved
Master :
reserved
Peripheral
reserved
Slave
INTERNAL
Data
Bit Serial
Byte Wide Addr. = 0000 up
Byte Wide Addr. = FFFF down
Byte Wide
Bit Serial
EXTERNAL
XTALl
o
o
R2
SUGGESTED COMPONENT VALUES
Rl 1-4MO
R2 0-1 KO
(may be required for low frequency, phase
shift andlor compensation level for crystal Q)
Cl,C210-40pf
Yl 1 - 20 MHz AT cut series resonant
I XTAL 1 (OUn
XTAL2 IN
68 PIN
PLCC
47
43
84 PIN
PLCC I PGA
57 I Jll
53 J Lll
~ Cl
~C2
100 PIN
132 PIN 164 PIN 175 PIN
PGA
COFP I PQFP
PGA
COFP
P13
105
T14
67 I 82
99
P15
M13
61 J 76
Figure 17. When activated in the "MAKEBITS" program and by selecting an output network for its buffer, the
crystal oscillator inverter uses two unconfigured package pins and external components to implement an oscillator.
An optional divide-by-two mode is available to assure symmetry.
2-14
1105 14
preamble and length count in on positive and out on
negative configuration clock edges. An LCA which has
received the preamble and length count then presents a
HIGH Data Out until it has intercepted the appropriate
number of data frames. When the configuration program
memory of an LCA is full and the length count does not
compare, the LCA shifts any additional data through, as it
did for preamble and length count.
zation the LCA enters the Clear state where it clears the
configuration memory. The active low, open-drain initialization signal INIT indicates when the Initialization and
Clear states are complete. The LCA tests for the absence
of an external active low RESET before it makes a final
sample of the mode lines and enters the Configuration
state. An external wired-AND of one or more INIT pins can
be used to control configuration by the assertion of the
active low RESET of a master mode device or to signal a
processor that the LCAs are not yet initialized.
When the LCA configuration memory is full and the length
count compares, the LCA will execute a synchronous
start-up sequence and become operational.
See
Figure 20. Three CCLK cycles after the completion of
loading configuration data the user 110 pins are enabled as
configured. As selected in MAKEBITS, the internal userlogic reset is released either one clock cycle before or after
the 1/0 pins become active. A similar timing selection is
programmable for the DONE/PROG output signal.
DONE/PROG may also be programmed to be an open
drain or include a pull-up resistor to accommodate wired
ANDing. The High During Configuration (HDC) and Low
During Configuration (LDC) are two user 1/0 pins which
are driven active when an LCA is in its Initialization, Clear
or Configure states. They and DONE/PROG provide
signals for control of external logic signals such as reset,
bus enable or PROM enable during configuration. For
parallel Masterconfiguration modes these signals provide
PROM enable control and allow the data pins to be shared
with user logic signals.
If a configuration has begun, a re-assertion of RESET for
a minimum ofthree internal timer cycles will be recognized
and the LCA will initiate an abort, returning to the Clear
state to clear the partially loaded configuration memory
words. The LCA will then re-sample RESET and the mode
lines before re-entering the Configuration state. A reprogram is initiated when a configured LCA senses a
HIGH to LOW transition on the DONEIPROG package pin.
The LCA returns to the Clear state where the configuration
memory is cleared and mode lines re-sampled, as for an
aborted configuration. The complete configuration program is cleared and loaded during each configuration program cycle.
Length count control allows a system of multiple Logic Cell
Arrays, of assorted sizes, to begin operation in a synchronized fashion. The configuration program generated by
the MakePROM program of the XACT development system begins with a preamble of 111111110010 followed by
a 24-bit 'length count' representing the total number of
configuration clocks needed to complete loading of the
configuration program(s). The data framing is shown in
Figure 19. All LCAs connected in series read and shift
User 1/0 inputs can be programmed to be either TTL or
CMOS compatible thresholds. At power-up, all inputs
have TTL thresholds and can change to CMOS thresholds
POWER-ON DELAY IS
214 CYCLES FOR NON-MASTER MODE-11 TO 33 mS
2'· CYCLES FOR MASTER MODE--43 TO 130 mS
USER UO PINS WITH HIGH IMPEDANCE PULL-UP
~_ _I_NI_T_SI_GN_A_L~LO_W_(:...XC_3_00_0:...)_~ .• t~:~6~H
LOW ON DONE/PROGRAM AND RESET
110515
CLEAR IS
-200 CYCLES FOR THE XC3020--130 TO 400 I'S
-250 CYCLES FOR THE XC303D-165 TO 500!'8
-290 CYCLES FOR THE XC3042-195 TO 580 I'S
-330 CYCLES FOR THE XC3064-220 TO 660 !'8
-375 CYCLES FOR THE XC3090-250 TO 750 !'8
Figure 18. A state diagram of the configuration process for power-up and reprogram.
2-15
XC3000 Logic Cell Array Family
at the completion of configuration if the user has selected
CMOS thresholds. The threshold of PWRDWN and the
direct clock inputs are fixed at a CMOS level.
Configuration Data
Configuration data to define the function and interconnection within a Logic Cell Array are loaded from an external
storage at power-up and on a re-program signal. Several
methods of automatic and controlled loading of the required data are available. Logic levels applied to mode se-
If the crystal oscillator is used it will begin operation before
configuration is complete to allow time for stabilization
before it is connected to the internal circuitry.
11111111
0010
< 24-BIT LENGTH COUNT>
1111
o < DATA FRAME #001>
o < DATA FRAME #002 >
o
o
o < DATA FRAME # 197>
-
DUMMY BITS'
PREAMBLE CODE
CONFIGURATION PROGRAM LENGTH
DUMMY BITS (4 BITS MINIMUM)
111
111
111
]
HEADER
FORXC3020
197 CONFIGURATION DATA FRAMES
PROGRAM DATA
(EACH FRAME CONSISTS OF:
A START BIT (0)
A 71-BIT DATA FIELD
THREE STOP BITS
REPEATED FOR EACH LOGIC
CELL ARRAY IN A DAISY CHAIN
111
111
1111
POSTAMBLE CODE (4 BITS MINIMUM)
'THE LCA DEVICES REQUIRE 4 DUMMY BITS MIN., XACT 2.10 GENERATES 8 DUMMY BITS
1105 05
Device
XC3020
XC3030
XC3042
XC3064
XC3090
Gates
2000
3000
4200
6400
9000
CLBs
Row X Col
64
(8 X8)
100
(lOX 10)
144
(12 X 12)
224
(16X 14)
320
(20 X 16)
lOBs
64
80
96
120
144
Flip-flops
256
360
480
688
928
Bits per frame
(w/l start 3 stop)
75
92
108
140
172
Frames
197
241
285
329
373
Program Data =
Bits· Frames + 4
(excludes header)
14779
22176
30784
46064
64160
PROM size (bits) =
Program Data
14819
22216
30824
46104
64200
+ 40 bit Headers
Figure 19. The internal Configuration Data Structure for an LCA shows the preamble, length count
and data frames which are generated by the XACT Development System.
The Length Count produced by the "MAKEBIT" program = [(40-bit preamble + sum of program data + 1 per daisy chain device)
rounded up to multiple of 8]- (2::; K::; 4) where K is a function of DONE and RESET timing selected. An additional 8 is added if
roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached.
2-16
supply currents. If unused blocks are not sufficient to
complete the 'tie,' the FLAGNET command of EDITLCA
can be used to indicate nets which must not be used to
drive the remaining unused routing, as that might affect
timing of user nets. NORESTORE will retain the results of
TIE for timing analysis with QUERYNET before
RESTORE returns the design to the untied condition. TIE
can be omitted for quick breadboard iterations where a few
additional mA of Icc are acceptable.
lection pins at the start of configuration time determine the
method to be used. See Table 1. The data may be either
bit-serial or byte-parallel, depending on the configuration
mode. Various Xilinx Programmable Gate Arrays have
different sizes and numbers of data frames. To maintain
compatibility between various device types, the Xilinx
2000 and 3000 product families use compatible configuration formats. For the XC3020, configuration requires
14779 bits for each device, arranged in 197 data frames.
An additional 40 bits are used in the header. See
Figure 20. The specific data format for each device is produced by the MAKEBITS command of the development
system and one or more of these files can then be
combined and appended to a length count preamble and
be transformed into a PROM format file by the 'MAKE
PROM' command of the XACT development system. A
compatibility exception precludes the use of a 2000 series
device as the masterfor3000 series devices iftheir DONE
or RESET are programmed to occur after their outputs
become active. The ''tie'' option of the MAKEBITS program
defines output levels of unused blocks of a design and
connects these to unused routing resources. This prevents indeterminant levels which might produce parasitic
The configuration bit-stream begins with HIGH preamble
bits, a four-bit preamble code and a 24-bit length count.
When configuration is initiated, a counter in the LCA is set
to 0 and begins to count the total number of configuration
clock cycles applied to the device. As each configuration
data frame is supplied to the LCA, it is internally assembled
into a data word. As each data word is completely
assembled, it is loaded in parallel into one word of the
internal configuration memory array. The configuration
loading process is complete when the current length count
equals the loaded length count and the required configuration program data frames have been written. Internal
user flip-flops are held reset during configuration.
POSTAMBLE
r"J :l' rJ}Gt--LAST--+-r~'-i-r~
Irr-'I-
'f
, PREAMBLE 'LENGTH COUNT'
DATA
START
START
1Ul.l--1
, ,
'r'
,
J3
LENG TH COUNT*
WEAK PULL·UP
_----l
I/O ACTIVE
HIGH
DOUT LEAD DEVICE
1/2 CLOCK CYCLE
DELAY FROM DATA INPUT
• THE CONFIGURATION DATA CONSISTS OF A COMPOSITE
4O-BIT PREAMBLE/LENGTH-COUNT, FOLLOWED BY ONE OR
MORE CONCATENATED LCA PROGRAMS, SEPARATED BY
4-BIT POSTAMBLES. AN ADDITIONAL FINAL POSTAMBLE BIT
IS ADDED FOR EACH SLAVE DEVICE AND THE RESULT ROUNDED
UP TO A BYTE BOUNDRY. THE LENGTH COUNT IS TWO LESS
THAN THE NUMBER OF RESULTING BITS.
110506
PROGRAM
/
. ; DONE
INTERNAL RESET
\
'\
TIMING OF THE ASSERTION OF DONE AND
TERMINATION OF THE INTERNAL RESET
MAY EACH BE PROGRAMMED TO OCCUR
ONE CYCLE BEFORE OR AFTER THE I/O
OUTPUTS BECOME ACTIVE.
Figure 20. Configuration and start-up of one or more LCAs.
110506
2-17
•
XC3000 Logic Cell Array Family
Two user programmable pins are defined in the unconfigured Logic Cell array. High During Configuration (HDC)
and Low During Configuration (LDC) as well as
DONEIPROG may be used as external control signals
during configuration. In Master mode configurations it is
convenient to use LDC as an active-low EPROM Chip
Enable. After the last configuration data-bit is loaded and
the length count compares, the user 1/0 pins become
active. Options in the MAKEBITS program allow timing
choices of one clock earlier or later for the timing of the end
of the internal logic reset and the assertion of the DONE
signal. The open-drain DONE/PROG output can be ANDtied with multiple Logic Cell Arrays and used as an active
high READY, an active low PROM enable or a RESET to
DURING CONFIGURATION
THE 5KO M2 PULL·DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL·UP.
BUT IT ALLOWS M2 TO
BE USER 110.
other portions of the system. The state diagram of Figure
18 illustrates the configuration process.
Master Mode
In Master mode, the Logic Cell Array automatically loads
configuration data from an external memory device. There
are three Master modes which use the internal timing
source to supply the configuration clock (CCLK) to time the
incoming data. Serial Master mode uses serial configuration data supplied to data-in (DIN) from a synchronous
serial source such as the Xilinx Serial Configuration
PROM shown in Figure 21. Parallel Master Low and
Master High modes automatically use parallel data sup-
DOUT
M2
HOC
LDC
GENERAL·
PURPOSE
USER I/O
PNS
INIT (XC3000)
: }OTHER
:
110 PINS
LCA
OPTIONAL
IDENTICAL SLAVE
LeAs CONFIGURED
THE SAME
.5V
RESET
RESET
Vpp
Vee
DATA SERIAL
MEMORY
CLK
DIN
CCLK
LDC
DONE
CE
OE
DIP
,. .................. .,,
CASCADED
SERIAL
MEMORY
CEO
XC1736
..
.,,
,,
~
.................. .
,
~
1105 16
Figure 21. Master Serial Mode. The one-time·programmable XC1736 Serial Configuration PROM supports automatic loading of
configuration programs up to 36K bits. Multiple devices can be cascaded to support additional LCAs. An early DONE inhibits the
XC1736 data output a CCLK cycle before the LCA lID become active.
2-18
internally serialized by the configuration clock. As each
data byte is read, the least significant bit of the next byte,
~O, becomes the next bit in the internal serial configuration
word. One Master mode LCA can be used to interface the
configuration program-store and pass additional concatenated configuration data to additional LCAs in a serial
daisy-chain fashion. CCLK is provided for the slaved
devices and their serialized data is supplied from OOUT to
DIN - OOUT to DIN etc.
plied to the 00-07 pins in response to the 16-bit address
generated by the LCA. Figure 22 shows an example of the
parallel Master mode connections required. The LCA HEX
starting address is 0000 and increments for Master Low
mode and it is FFFF and decrements for Master High
mode. These two modes provide address compatibility
with microprocessors which begin execution from opposite ends of memory. For Master high or low, data bytes
are read in parallel by each read clock (RCLK) and
USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT FROM
ALTERNATIV E CONFIGU RATIONS
.--r---------,...-+5V
5kn
DOUT
*
M2
CCLK
*
II
HOC
GENERALPURPOSE
USER 110
PNS
A15
RCLK
A14
INIT (XC3000)
A13
A12
} OTHER
I/O PINS
LeA
RESET
A11
A10
A10
A9
A9
RESET
04
DONE
EPROM
(2Kx S
OR LARGER)
AS
AS
A7
A7
A6
A6
A5
A5
A4
A4
02
A3
A3
01
A2
A2
DO
A1
A1
AO
AO
07
01
DIP
-----d=
DATA BUS
(OC~pt~~ _ _ _-'X'-_A_DD_R_E_SS_...:
-------.X
~
--{,..----.~~:~:::rs:TS====t1~'1THr=~\
(~~Tt~~~ l1+_ _ _ _ _\~.'8O~~=====:I.
00-07
PROM:
BYTE N
'--
RCLK
S CCLKs
(OU{P - -
CCLK
DOUT
(OUTPUT)
D6
D7
RESET
==x,.
BITN
j
-
I-f-+5V
LCA
*
*
GEN ERALPUR POSE
USERI/o
;--
D41--
DIN
--
D2
D5
-
-
-
Dl
03 t--
r
M2
DOUT
f--
r
liP
OTHER {
VO PINS
!----
INIT
RESET
~
BITN+l
\-------.
BITN-l
m
I
BITN
* FOR OPTIONAL SLAVE MODE LeAs IN A DAISY CHAIN
110519
Figure 24. Slave Mode. Bit-serial configuration data are read at rising edge of the CCLK.
Data on DOUr are provided on the falling edge of CCLK.
2-21
II
XC3000 Logic Cell Array Family
Input Thresholds
Readback
Prior to the completion of configuration all LCA input
thresholds are TTL compatible. Upon completion of configuration the input thresholds become either TTL or
CMOS compatible as programmed. The use of the TTL
threshold option requires some additional supply current
forthreshold shifting. The exception is the threshold ofthe
PWRDWN input and direct clocks which always have a
CMOS input. Prior to the completion of configuration the
user 1/0 pins each have a high impedance pull-up. The
configuration program can be used to enable the 1/0 Block
pull-up resistors in the Operational mode to act either as an
input load or to avoid a floating input on an otherwise
unused pin.
The contents of a Logic Cell Array may be read back if it
has been programmed with a bit-stream in which the
Readback option has been enabled. Readback may be
used for verification of configuration and as a method of
determining the state of intemallogic nodes during debugging with the XACTOR In-Circuit debugger. There are
three options in generating the configuration bit-stream:
+5V
51<0
l~
I I
• "Never" will inhibit the Readback capability.
• "One-time," will inhibit Readback after one Readback
has been executed to verify the configuration.
• "On-command" will allow unrestricted use of Readback.
I I
MO M1 PWRDWN
CCLK
GENERAL·
PURPOSE
USER 110
PNS
r--
DIN
MO M1 PWRDWN
51<0
M2
....
A15
HOC
r-
A14
A14
LDC
p-
A13
A13
A12
A12
A11
A11
A10
LCA
MASTER
A9
A10
OTHER
I/O PINS
r- .... -
r--
EPROM
OTHER {
VO PINS
INIT
'---
\I
DOUT
LCA
SLAVE #1
A15
" ...
LCA
SLAVE#n
GENERAL·
PURPOSE
USER VO
r - - DIP
r<
r - - 06
A7
A7
07'"
06",
A6
A5
A5
03
A4
A4
02
/>3
/>3
r - - 01
A2
A2
r - - DO
A1
A1
AO
AO
rI
LOC
-< RESET
olP
INIT
P;;c.L
RESET
03 """"
D2 """"
RESET
01 """"
00""""
OE
CE
r-r--"+5V
5 1<0 EACH
8
OPEN
' " COLLECTOR
~
GENERALPURPOSE
USER VO
NOTE: XC2QOO DEVICESOONOT
HAVE INIT TO HOLD OF FAMASTER
DEVICE. RESET OF A MASTER DEVICE
SHOULD BE ASSERTED BY AN EXTERNAL
TIMING CIRCUIT TO ALLOW FOR LCA CCLK
VARIATIONS IN CLEAR STATE TIME.
05 """"
04",
REPROGRAM
SYSTEM RESET
p-
INITP-
r<
A6
LOC
I--
f>-
r - - DIP
04
....
I--
OTHER {
VOPINS
r-
A9
05
M2
HOC
r--
AS
r-r--r--
I-
DOUT
DIN
A8
V--
5
CCLK
07
r--
~
I
' - - - CCLK
M2
HOC
-< RCLK
-
~
MO M1 PWRDWN
DOUT
-
+~v
+~v
T
\I
....
.."
~
""
Figure 25. Master Mode configuration with daisy chained slave mode devices.
All are configured from the common EPROM source. The Slave mode device INIT signals
delay the Master device configuration until they are initialized. A well defined termination
of SYSTEM RESET is needed when controlling multiple LCAs.
Any XC3000 slave driven by an XC2000 master mode device must use "early DONE and early internal reset".
(The XC2000 master will not supply the extra clock required by a "late" programmed XC3000.)
2-22
1105 20
Readback is accomplished without the use of any of the
user 1/0 pins; only MO, M1 and CCLK are used. The
initiation of readback is produced by a LOW to HIGH
transition of the MO/RTRIG (Read Trigger) pin. Once the
readback command has been given, the input CCLK is
driven by external logic to read back each data bit in a
format similar to loading. After two dummy bits, the first
data frame is shifted out, in inverted sense, on the
M 1/RDATA (Read Data) pin. All data frames must be read
back to complete the process and return the mode select
and CCLK pins to their normal functions.
driver which pulls DONEIPROG LOW. Once it recognizes
a stable request, the Logic Cell Array will hold a LOW until
the new configuration has been completed. Even if the reprogram request is externally held LOW beyond the configuration period, the Logic Cell Array will begin operation
upon completion of configuration.
DONE Pull-up
DONEIPROG is an open drain 1/0 pin that indicates the
LCA is in the operational state. An optional internal pull-up
resistor can be enabled by the user of the XACT development system when 'Make Bits' is executed.
The
DONEIPROG pins of multiple LCAs in a daisy-chain may
be connected together to indicate all are DONE or to direct
them all to re-program.
The readback data includes the current state of each
internal logic block storage element, and the state of the
[.i and .ff] connection pins on each 1/0 Block. These data
are imbedded into unused configuration bit positions during readback. This state information is used by the Logic
Cell Array development system In-Circuit Verifier to provide visibility into the internal operation of the logic while
the system is operating. To readback a uniform timesample of all storage elements it may be necessary to
inhibit the system clock.
DONE Timing
The timing of the DONE status signal can be controlled by
a selection in the MAKEBITS program to occur a CCLK
cycle before, or after, the timing of outputs being activated.
See Figure 20. This facilitates control of external functions
such as a PROM enable or holding a system in a wait state.
Re-program
RESET Timing
The Logic Cell Array configuration memory can re-written
while the device is operating in the user's system. To
initiate a re-programming cycle, the dual function package
pin DON E/PROG must be given a HIGH to LOW transition.
To reduce sensitivity to noise, the input signal is filtered for
2 cycles of the LCA's internal timing generator. When reprogram begins, the user programmable 1/0 output buffers
are disabled and high impedance pull-ups are provided for
the package pins. The device returns to the Clear state
and clears the configuration memory before it indicates
'initialized'. Since this clear operation uses chip-individual
internal timing, the master might complete the clear operation and then start configuration before the slave has
completed the clear operation. To avoid this problem,
wire-AND the slave INIT pins and use them to force a
RESET on the master (see Figure 25). Reprogram control
is often implemented using an external open collector
As with DONE timing, the timing of the release of the
internal RESET can be controlled by a selection in the
MAKEBITS program to occur a CCLK cycle before, or
after, the timing of outputs being enabled. See Figure 20.
This reset maintains all user programmable flip-flops and
latches in a 'zero' state during configuration.
Crystal Oscillator Division
A selection in the MAKEBITS program allows the user to
incorporate a dedicated divide-by-two flip-flop in the crystal oscillator function. This provides higher assurance of a
symmetrical timing signal. Although the frequency stability of crystal oscillators is high, the symmetry of the
waveform can be affected by bias or feedback drive.
2-23
XC3000 Logic Cell Array Family
of the storage element, the critical timing is data set-up
relative to the clock edge provided to the flip-flop element.
The delay from the clock source to the output of the logic
block is critical in the ti ming of signals produced by storage
elements. Loading of a Logic Block output is limited only
by the resulting propagation delay of the larger interconnect network. Speed performance of the logic block is a
function of supply voltage and temperature. See Figures
28 and 29.
PERFORMANCE
Device Performance
The high performance of the Logic Cell Array is due in part
to the manufacturing process, which is similar to that used
for high speed CMOS static; memories. Performance can
be measured in terms of minimum propagation times for
logic elements. The parameter which traditionally de~
scribes the overall performance of a gate array:is the
toggle frequency of a flip-flop. The configuration for
determining the toggle performance of the Logic Cell Array
is shown in Figure 26. The flip-flop output Q is fed back
through the combinatorial logic as to form the toggle flipflop.
Interconnect Performance
Interconnect performance depends on the routing resource used to implement the signal path. As discussed
earlier, direct interconnect from block to block provides a
fast path for a signal. The single metal segment used for
Long lines exhibits low resistance from end to end, but
relatively high capacitance. Signals driven through a
programmable switch will have the additional impedance
of the switch added to their normal drive impedance.
a
Actual Logic Cell Array performance is determined by the
timing of critical paths, including both the fixed timing for
the logic and storage elements in that path, and the timing
associated with the routing of the network. Examples of
internal worst case timing are incluqed in the performance
data to allow the user to make the best use of the capabilities of the device. The XACT development system timing
calculator or XACT generated simulation models should
be used to calculate worst case paths by using actual
impedance and loading information. Figure 27 shows a
variety of elements which are. involved in determing system performance. Actual measurement of internal timing
is not practical and often only the sum of component timing
is relevant as in the case of input to output. The relationship between input and output timing is arbitrary and only
the total determines performance. Timing components of
internal functions may be determined by measurement of
differences at the pins of the package. A synchronous
logic function which involves a clock to block"output, and
a block-input to clock set-up is capable of higher speed
operation than a logic configuration of two synchronous
blocks with an extra combinatorial block level between
them. System clock rates to 60% of the toggle frequency
are practical for logic in which an extra combinatorial level
is located between synchronized blocks. This allows impie mentation of functions of up to 25 variables. The use of
the wired-AND is also available for wide, high speed functions.
General purpose interconnect performance depends on
the number of switches and segments used, the presence
of the bi-directional re-powering buffers and the overall
loading on the signal path at all points along the path. In
calculating the worst case timing for a general interconnect
path the timing calculator portion of the XACT development system accounts for all of these elements. As an
approximation, interconnect timing is proportional 10 the
summation of totals of local metal segments beyond each
programmable switCh. In effect, the time is a sum of R-C
time each approximated by an R times the total C it drives.
The R of the switch and the C of the interconnect isa
function of the particular device performance grade. For a
string of three local interconnects, the approximate time at
the first segment, afterlhe first switch resistance would be
three units; an additional two units after the next switch
plus an additional unit after the last switch in the chain. The
interconnect R-C chain terminates at each re-powering
buffer. The capacitance of the actual block inputs is not
significant; the capacitance is in the interconnect metal
and switches. Figure 30 illustrates this.
Logic Block Performance
Logic block performance is expressed as the propagation
time from the interconnect point at the input of the combinato rial logic to the output of the block in the interconnect
area. Combinatorial performance is independent of the
specific logicfundion because of the table look-up based
implementation. Timing is different when the combinatorial logic is used in conjunction with the storage element.
For the combinatorial logic function driving the data input
CLOCK -:.,-:- - - I >
t.
....J
Figure 26. ''Toggle" Flip-Flop used to
characterize device performance.
2-24
1105 07
CLOCK TO
OUTPUT
r--TCKO
COMBINATORIAL
.1'
SETUP
T,Lo--....•...I·>-----T,CK ---Of·1
......................................................CLB
····································-········-·····CLB............~
.....::
CLS· •.
w
LOGIC
r·······
lOS
.-{>+
1-+--;'---;
L_
••
PAD
~ .. .. ......................................... .........
r
(K)
,
CLOCK-~-----+-----------4r~
I"---TCKO~
lOS ••
PAD
110521
~-----{>-J
~TPID~
I'
TOKOP-------t·1
Description
Symbol
Min
Max
Combinatorial
TllO
K Clock
To output
Logic-input setup
Logic-input hold
TCKo
TICK
TCKI
Pad to input (direct)
TPID
Units
Min Max
9
12
12
0
-100
Min Max
14
Logic input to Output
InputlOutput
-70
-50
Speed Grade
8
7
ns
7
ns
ns
ns
7
0
8
0
9
6
4
ns
-
Output to pad (fast)
Top
15
9
6
ns
1/0 clock to pad (fast)
TOKPo
18
13
10
ns
FClK
50
70
100 MHz
FF toggle frequency
Figure 27. Examples of Primary Block Speed Factors.
Actual timing is a function of various block factors combined with routing factors.
Overall performance can be evaluated with the XACT timing calculator or by an optional simulation.
1.2
1.3
1.2
C
w
1.1
:::;
<:
1.0
a:
0.9
N
o
w
N
:::;
::;
0
~
~
0
1.0+-------------"1-
~
>- 0.8
:5
w
1.1
..:
~
w
Cl
0.7
0.9
0.6
4
0.5
-55 -40
1105 08
0
30
70 85
4.5
5.0
5.5
6.0
Vcc
TEMPERATURE iC)
110522
Figure 28. Change in speed performance as a function of
temperature. normalized for 30°C.
Figure 29. The speed performance of a CMOS device
increases with Vcc within the operating range.
2-25
•
XC3000 Logic Cell Array Family
POWER
Power Dissipation
Power Distribution
The Logic Cell Array exhibits the low power consumption
characteristic of CMOS ICs. For any design the user can
use Figure 32 to calculate the total power requirement
based on the sum of the capacitive and DC loads both
external and internal. The configuration option of TTL chip
inputthreshold requires power for the threshold reference.
The pOwer required by the static memory cells which hold
the configuration data is very low and may be maintained
in a power-down mode.
Power for the LCA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the LCA, a dedicated Vcc and ground ring surrounding the logic array provides power to the I/O drivers. See
Figure 31. An independent matrix of Vcc and ground lines
supplies the interior logic of the device. This power
distribution grid provides a stable supply and ground for all
internal logic, providing the external package power pins
are all connected and appropriately decoupled. Typically
a 0.1 ~F capacitor connected near the Vcc and ground pins
of the package will provide adequate decoupling.
Typically most of power dissipation is produced by external capacitive loads on the output buffers. This load and
frequency dependent power is 25 ~W/pF/MHz per output.
Another component of I/O power is the DC loading on each
output pin by devices driven by the Logic Cell Array.
Output buffers capable of driving the specified 4 mA loads
under worst-case conditions may be capable of driving 25
to 30 times that current in a best case. Noise can be
reduced by minimizing external load capacitance and
reducing simultaneous output transitions in the same
direction. It may also be beneficial to locate heavily loaded
output buffers near the ground pads .. The I/O Block output
buffers have a slew limited mode which should be used
where output rise and fall times are not speed critical.
Slew-limited outputs maintain their DC drive capability, but
generate less external reflections and internal noise. More
than 32 fast outputs should not be switching in the same
direction exactly simultaneously. A few ns of deliberate
skew can alleviate this problem of "ground-bounce".
Internal power dissipation is a function of the number and
size olthe nodes, and the frequency at which they change.
In an LCA the fraction of nodes changing on a given clock
is typically low (10-20%). For example, in a large binary
counter, the average clock cycle produces changes equal
to one CLB output at the clock frequency. Typical global
clock buffer power is between 1.7 mW/MHz for the
XC3020 and 3.6 mW/MHz for the XC3090. The internal
capacitive lo~d is more a function of interconnectthan fanout. With a ''typical'' load ofthree general interconnect segments, each Configurable Logic Block output requires
about 0.4 mW per MHz of its output frequency.
~ ___ -: ~WITCH MATRIX --.... ~ ___ -:
'~~------~---r----~~~-----'------~~---; ~--~-/ i. ___ ~
i.
R3
CLB
1-- ..
,
t----.~_
TIMING: INCREMENTAL
IF R1=R2=R3=R AND C,=C2=C 3 =C
THEN CUMULATIVE TIMING
T1 =3RC
=3RC
T2=3RC+2RC
T3=3RC+2RC+1RC
=5RC
=6RC
6RC+ BUFFER
Figure 30. Interconection timing example. Use of the XACT timing calculator
or XACT-generated simulation model provide actual worst-case performance information.
2-26
110523
Total Power = Vcc· Iceo + external (DC + capacitive)
+ internal (CLB + lOB + Long line + pull-up)
supply a retention voltage to the Vcc pins of the package.
When normal power is restored, Vcc is elevated to its
normal operating voltage and PWRDWN is returned to a
HIGH. The Logic Cell Array resumes operation with the
same internal sequence that occurs at the conclusion of
configuration. Internal I/O and logic block storage elements will be reset, the outputs will become enabled and
the DONE/PROG pin will be released. No configuration
programming is involved.
Because the control storage of the Logic Cell Array is
CMOS static memory, its cells require a very low standby
current for data retention. In some systems, this low data
retention current characteristic can be used as a method
of preserving configurations in the event of a primary
power loss. The Logic Cell Array has built in power-down
logic which, when activated, will disable normal operation
of the device and retain only the configuration data. All
internal operation is suspended and output buffers are
placed in their high impedance state with no pull-ups.
Power-down data retention is possible with a simple battery-backup circuit because the power requirement is
extremely low. For retention at 2.4 volts the required
current is typically on the order of 50 nanoamps.
When the power supply is removed from a CMOS device
it is possible to supply some power from an input signal.
The conventional electro-static input protection is implemented with diodes to the supply and ground. A positive
voltage applied to an input (or output) will cause the
positive protection diode to conduct and drive the power
pin. This condition can produce invalid power conditions
and should be avoided. A large series resistor might be
used to limit the current or a bi-polar buffer may be used to
isolate the input signal.
To force the Logic Cell Array into the Power-Down state,
the user must pull the PWRDWN pin low and continue to
GND
Vee
+ --+- -+-- +- -+-- + --+- -+
+-- +-- + --+ --+ --+--+, --+,
,
,
+--+- -+ -- +- -+- -+--+- -+
+-- + -- + --+ --+- -+--+ --+
+ --+- -+ -- +- -+- -+-- +-- +
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
,
I
,
I
,
I
--~~~
..
.
+-- +- -+ --+ --+- -+--+ --+
+ --+- -+--+-- +--+-- +--+
I
I
I
I
I
•
I
I
I
I
I
I
I
I
,
I
GND
1105 24
Figure 31. LCA Power Distribution.
2-27
GROUND AND
VeeRING FOR
1/0 DRIVERS
LOGIC POWER GRID
XC3000 Logic Cell Array Family
,
500
100
90
IL
80
70
/
60
/
/
50
40
/
150
30
/
/
/
100
20
/
V
V
/
50
/
/
L
1/
40
/
30
/
(mW)
/
20
V
/
L
/
/
L
/
/
50 CLB OUTPUTS10
/
(18 mW/MHz)
,v
V
/
5
20 CLB OUTPUTS
(7.2 mW/MHz)
/
1/
4
7
/
6
5
/
2
/
V
OR
ONE OUTPUT WITH 50 pF LOAD
(1.8 mW/MHz)
/
/
o. 5
0.5
1/
/
L
/
V
.L
2
1
.9
.8
/
/"
/
3020 GLOBAL CLOCK BUFFER 1
3
V
/
V
/
V
V
V
/
(mA)
4
/
L
V
/
3
10
8
/
/
V
.7
L
.6
.5
.4
.3
.2
.1
2
4
3
5
10
20
30
40
50
FREQUENCY MHz
ONE CLB OR lOB OUTPUT /
DRIVING THREE LOCAL
INTERCONNECTS
(0.36 mW/MHz)
1105 09
Figure 32. LeA Power Consumption by Element. Total chip power is the sum of Vee-leeo plus effective internal and external
values of frequency dependent capacitive charging currents and duty factor dependent resistive loads.
2-28
Comp.onent Selection,
Ordering Information,
Electrical Parameters &
Physical Dimensions
E:XllINX
XC2064
XC2018
XC3020
XC3030
XC3042
XC3090
1972 01
XC1736-PD8C
XC1736-CD8M
plastic 8 Pin, Mini-DIP -40'C to 85'C
Ceramic 8 Pin, Mini-DIP -55'C to 125'C
COMPATIBLE PACKAGE OPTIONS
"
A range of Xilinx LCA (levices is available in iejentiCal
packages with identical pin-outs. A desi~n can thus be
started with one device, then migrated to a larger or
smaller chip while retaining the original footprint and
PC-board layout.
.
Examples: PLCC .68:.
2064-20H3-3020-3030
LCA Temperature Options
Symbol
Description
C
I
M
B
Commercial
Industrial
Military
Military
Temperature
O'Cto 70'C
-40'C to 85'C
-55'C 125'C
MIL~STD-883, Class B
to
PLCC 84:
PGA 84:
PQFP 100:.
CQFP100:
PGA 132:
ORDERING INFORMATION
Ex~mple: . .~Q2.]0.
DeVice Type .
T~ggle
iL..
L
2018.,3020-3030-3042
2018~3()20-3030-3042
3020-3030-3042
3020-3030-3042
3042-3064
Note, however, that the XC2000 and XC3\lOO .families
differ in the position ofXTl1 as well as th(~e garallel
address bits (6; 7 ancl11) and most of the da~.pi(ls u$id
in parallel master mode.
' '.
Temperature
Range
XC2018 and XC3020 are not ,available in P~esl since
the PGA84 is the same size and offers Ill9reIIO•.
Number of Pins
Rate
'.
':~ '~';<:~\\ :"v"
, , '
Note that a PlCC in a socket with PGMootP"'1IIf fi{lemtEt~
a printed circuit board pin-out dlffertnt from ~~gev:ice.
Package Type
2-29
XC3000 Logic Cell Array Family
DONE
The DONE output is configurable as open drain with or
without an internal pull-up resistor. At the completion of
configuration, the circuitry of the LCA becomes active in a
synchronous order, and DONE may be programmed to
occur one cycle before or after that.
PIN DESCRIPTIONS
1. Permanently Dedicated Pins.
Vee
Two to eight (depending on package type) connections to
the nominal +5 V supply voltage. All must be connected.
PROG
Once configuration is done, a HIGH to LOW transition of
this pin will cause an initialization of the LCA and start a
reconfiguration.
GND
Two to eight (depending on package type) connections to
ground. All must be connected.
MO
As Mode 0, this input and M1, M2 are sampled before the
startot configuration to establish the configuration mode to
be used.
PWRDWN
A LOW on this CMOS compatible input stops all internal
activity to minimize Vcc power, and puts all output buffers
in a high impedance state, but configuration is retained.
When the PWRDWN pin returns HIGH, the device returns
to operation with the same sequence of buffer enable and
DONE/PROGRAM as at the completion of configuration.
All internal storage elements are reset. If not used,
PWRDWN must be tied to Vcc.
RTRIG
As a Read Trigger, a LOW-to-HIGH input transition, after
configuration is complete, will initiate a Readback of configuration and storage element data by CCLK. This operation may be limited to a single request, or be inhibited altogether, by selecting the appropriate readback option
when generating the bit stream.
RESET
This is an active low input which has three functons.
Priortothe start of configuration, a LOW input will delay the
start of the configuration process. An internal circuit
senses the application of power and begins a minimal
time-out cycle. When the time-out and RESET are complete, the levels of the "M" lines are sampled and configuration begins.
M1
As Mode 1, this input and MO, M2 are sampled before the
start of configuration to establish the configuration mode to
be used. If Readback is to be used, a 5 KQ resistor should
be used to define mode level inputs.
RDATA
As an active low Read Data, after configuration is complete, this pin is the output of the readback datil.
If RESET is asserted during a configuration, the LCA is reinitialized and will restart the configuration at the termination of RESET.
If RESET is asserted after configuration is complete it will
provide an asynchronous reset of all lOB and CLB storage
elements of the LCA.
CCLK
During configuration, Configuration Clock is an output of
an LCA in Master mode or Peripheral mode. LCAs in Slave
mode use it as a clock input. During a Readback operation
it is a clock input for the configuration data being shifted
out.
2-30
2. User 1/0 Pins that can have special functions.
RClK
During Master parallel mode configuration RCLK represents a "read" of an external dynamic memory device
(normally not used).
M2
As Mode 2 this input has a passive pullup during configuration. Together with MO and M1 it is sampled before the
start of configuration to establish the configuration mode to
be used. After configuration this pin becomes a user programmable 1/0 pin.
ROYIBUSY
During Peripheral parallel mode configuration this pin
indicates when the chip is ready for another byte of data to
be written to it. After configuration is complete, this pin becomes a user programmed lID pin.
HOC
High During Configuration is held at a HIGH level by the
LCA until after configuration. It is available as a control
output indicating that configuration is not yet completed.
After configuration this pin is a user lID pin.
00-07
This set of 8 pins represent the parallel configuration byte
for the parallel Master and Peripheral modes. After configuration is complete they are user programmed lID pin.
lOC
Low During Configuration is held at a lOW level by the
LCA until after configuration. It is available as a control
output indicating that configuration is not yet completed. It
is particularly useful in Master mode as a LOW enable for
an EPROM. After configuration this pin is a user lID pin.
If used as a LOW EPROM enable, it must be programmed
as a HIGH after configuration.
AO-A15
This set of 16 pins present an address output for a
configuration EPROM during Master parallel mode. After
configuration is complete they are user programmed lID
pin.
DIN
This user lID pin is used as serial Data input during Slave
or Master Serial configuration. This pin is Data 0 input in
Master or Peripheral configuration mode.
INIT
This is an active low open drain output which is held LOW
during the power stabilization and internal clearing of the
configuration memory. It can be used to indicate status to
a configu ring microprocessor or, as a wired AN D of several
slave mode devices, a hold-off signal for a master mode
device. After configuration this pin becomes a user programmable lID pin.
OOUT
This user lID pin is used during configuration to output
serial configuration data for daisy-chained slaves' Data In.
TClKIN
This is a direct CMOS level input to the global clock buffer.
BClKIN
This is a direct CMOS level input to the alternate clock
buffer (Auxiliary Buffer) in the lower right corner.
3. Unrestricted User 1/0 Pins.
XTl1
This user I/O pin can be used to operate as the output of
an amplifier driving an external crystal and bias circuitry.
1/0
A pin which may be programmed by the user to be Input
and/or Output pin following configuration. Some of these
pins present a high impedance pull-up (see next page) or
perform other functions before configuration is complete
(see above).
XTl2
This user lID pin can be used as the input of an amplifier
connected to an external crystal and bias circuitry. The
lID Block is left unconfigured. The oscillator configuration
is activated by routing a net from the oscillator buffer
symbol output and by the MAKEBITS program.
CSD, CS1, CS2, WS
These four inputs represent a set of Signals, three active
low and one active high, which are used in the Peripheral
mode to control configuration data entry. The assertion of
all 4 generates a write to the internal d(ita buffer. The removal of any assertion, clocks in the DO':';D7 data present.
2-31
•
XC3()OO Logic Cell Array Family
XC3000 Family Configuration Pin Assignments
100
100
132
PGA
164
175
PGA
USER
OPERATION
I::'
I/O
I/O
II
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
_
REPRESENTS A 50KO TO 100KO PULL-UP
• INIT IS AN OPEN DRAIN OUTPUT DURING CONFIGURATION
(I) REPRESENTS AN INPUT
AVAILABLE PACKAGES
1105 25
Note: Pin assignments of "PGA Footprint" PLCC sockets and PGA packages are not electrically identical.
Generic I/O pins are not shown_
2-32
XC3000 Family 68-Pln PLCC, 84-Pln PLCC and PGA Pinouts
68PLCC
XC-3020'
XC-3030, XC-3042
84 PLCC
84PGA
68 PLCC
XC-3020'
XC-3030, XC-3042
84 PLCC
84PGA
10
l'WRON
12
B2
44
I'!ESET
54
K10
11
lCLKIN-IiO
13
C2
45
DONE-PG"
55
J10
n.c.
110'
14
B1
46
D7-1/0
56
K11
12
1/0
15
C1
47
XTl1 (OUll-BClKIN-I/O
57
J11
16
D2
48
D6-1I0
58
H10
H11
-
va
va
17
D1
-
14
1/0
18
E3
49
15
va
19
E2
50
16
1/0
20
E1
17
va
21
F2
18
Vee
22
13
-
va
va
20
1/0
19
1/0
59
60
F10
61
G10
51
D5-I/O
C"SO-I/O
D4-1/0
62
G11
-
VO
63
G9
F3
52
Vee
64
23
G3
53
D3-IIO
65
F9
F11
24
G1
54
CST-IIO
66
E11
25
G2
55
D2-VO
67
E10
21
va
26
F1
-
1/0
68
E9
22
1/0
27
H1
n.c.
69
D11
-
1/0
28
H2
56
1/0'
D1-VO
70
D10
29
J1
57
RDY/BUSV-"RcrK-I/O
71
C11
24
va
va
30
K1
58
DO-DIN-I/O
72
B11
25
M1-lmATA
31
J2
59
DOUl-I/O
73
C10
26
MO-l1TRlG"
32
l1
60
CClK
74
A11
27
M2-1I0
33
K2
61
AO-WS-IIO
75
B10
28
HOC-Va
34
K3
62
A1-CS2-1/0
76
B9
29
110
35
L2
63
A2-1/0
77
A10
30
EOC-VO
36
L3
64
A3-1/0
78
A9
31
1/0
37
K4
n.c.
110'
79
B8
n.c.
va·
L4
J5
n.c.
1/0'
BO
AB
B6
23
32
1/0
38
39
65
A15-1/0
81
33
110
40
K5
66
M-I/O
82
B7
n.c,
1/0'
41
l5
67
A14-1/0
83
A7
34
TfllT-I/O
42
K6
68
A5-1/0
84
C7
35
GND
43
J6
1
GND
1
C6
36
1/0
44
J7
2
A13-1/0
2
A6
37
1/0
45
l7
3
AS-I/O
3
AS
36
1/0
46
K7
4
A12-1/0
4
B5
39
1/0
47
l6
5
A7-1/0
5
C5
40
1/0
48
l8
6
M
110
49
K8
n.c.
n.c.
1/0'
41
1/0'
7
B4
n.c.
n.c.
50
19
6
A11-1/0
8
A3
51
L10
7
AB-IIO
9
A2
42
110'
1/0'
1/0
52
K9
8
A10-1I0
10
B3
43
XTl2(INl-1/0
53
l11
9
A9-1/0
11
A1
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-limited .
• Indicates unconnected package pins for the XC3020.
2-33
•
XC3000 Logic Cell Array Family
XC3000 Family 100·Pin QFP Pinouts
PIN No.
CQFP
PQFP
PIN No.
XC3020
XC3030
XC3042
CQFP
PQFP
XC3020
XC3030
XC3042
PIN No.
CQFP
PQFP
XC3020
XC3030
XC3042
1
16
GNO
35
50
I/O'
69
84
I/O'
2
17
A13-VO
36
51
I/O'
70
85
I/O'
3
18
A6-VO
37
52
M1-RO
71
86
I/O
4
19
A12-1/0
3B
53
GNO'
72
87
OS-I/O
5
20
A7-1/0
39
54
Ma-RT
73
88
CSO-I/O
6
21
I/O'
40
55
Vee"
74
89
04-VO
7
22
I/O'
41
56
M2-1/0
75
90
I/O
8
23
A11-1/0
42
57
HOC-I/O
76
91
Vee
9
24
A8-1/0
43
58
I/O
77
92
03-1/0
10
25
A10-1/0
44
59
LOC-I/O
78
93
~-I/O
02-1/0
11
26
A9-1/0
45
60
I/O'
79
94
12
27
Vee·
46
61
I/O
80
95
I/O
13
28
GNO'
47
62
81
96
I/O'
14
29
l'Wlml'l"
48
63
15
30
I/O
49
64
VO
VO
VO
16
31
I/O"
50
65
lliIlT-I/O
17
32
I/O'
51
66
GNO
18
33
I/O'
52
67
19
34
I/O
53
20
35
I/O
21
36
22
23
24
25
82
97
110'
83
98
01-1/0
84
99
"RcrR"-lIDSY/RDY -I/O
85
100
DO-DIN-I/O
I/O
86
1
DOUT-I/O
68
VO
87
2
CCLK
54
69
I/O
88
3
Vee"
I/O
55
70
I/O
89
4
GNO'
37
I/O
56
71
I/O
90
5
AO-WS-I/O
38
I/O
57
72
I/O
91
6
A1-CS2-1/0
39
I/O
58
73
VO
92
7
40
I/O
59
74
I/O'
93
8
I/O'
A2-1/0
26
41
Vee
60
75
9
A3-1/0
42
I/O
61
76
I/O'
XTAL2-1/0
94
27
95
10
I/O'
28
43
I/O
62
77
GNO'
96
11
I/O'
A15-1/0
29
44
I/O
63
78
"RESET
97
12
30
45
VO
64
79
Vee"
98
13
M-I/O
31
46
I/O
65
80
OONE-l'IT
99
14
A14-1/0
32
47
I/O
66
81
07-1/0
100
15
AS-I/O
33
48
I/O
67
82
XTALH/O
34
49
I/O
68
83
06-1/0
Unprogrammed lOBs have a default pull-up.
This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew limited.
, Indicates unconnected package pins for the XC3020 .
• , Indicates unconnected package pins for the XC3020 and the XC3030.
2-34
~XIUNX
Table 2d. XC3000 Family 132 Pin PGA Pinouts
PGAPin
Number
XC·3042
XC·3064
C4
Al
PGAPln
Number
XC-3042
XC-3064
GND
813
J5WI.'IDN
Cll
A14
PGAPin
Number
XC·3042
XC·3064
PGAPln
Number
XC·3042
XC·3064
Ml·m:;
P14
m:sE'f
M3
OOUT-I/O
GND
Mll
vee
P1
CCLK
MO-RT
N13
OONE-PG
vee
M4
M12
07-1/0
AO-WS-I/O
vee
84
1/0
1/0
1/0
1/0*
1/0
C14
1/0
P12
1i0
M1
110
C5
110
E12
1i0
Nll
06-1i0
K3
A3
013
1/0
Ml0
1i0
L2
1/0
A2-1/0
014
IDC"-I/O
Pll
1/0*
1/0
1/0
L1
AS-I/O
J3
1/0
1/0
AS
1i0
E14
M9
05-1/0
Kl
A15-1/0
86
1i0
F13
N9
C"Sli-1/0
J2
M-IIO
AS
1/0
F14
P9
110
G13
Hl
1/0*
A14-1/0
C7
GND
G14
lNIT-11O
1/0*
1/0*
04-110
Jl
87
1/0*
1/0
1/0
1/0
1/0
1/0
K2
C6
1/0*
1/0
1/0
1/0
H2
AS-IIO
GND
A13-1I0
AS-IiO
C3
82
83
A2
M
85
GNO
012
C13
M2-1/0
P13
XTAL1-1/0
L3
M2
814
HOC-IIO
N12
1i0
N1
A1-CS2-1/0
E13
F12
Nl0
Pl0
P8
vee
N8
P7
GNO
M8
H14
1/0
GNO
H13
1i0
M7
N7
H3
G3
G2
AS
1/0
1/0
1/0
G12
H12
03-1/0
Gl
A9
1i0
J14
1/0
P6
~-I/O
Fl
1/0*
89
1i0
J13
1/0
N6
F2
A12-1I0
C9
1i0
K14
1i0
P5
El
A7-1/0
Al0
J12
1/0
M6
F3
1i0
K13
1i0
N5
All
1/0
1/0
1/0*
L14
P4
Cl0
110
L13
P3
811
1/0
1/0*
1/0
1/0*
ItO
K12
1/0*
1/0
1/0
1/0*
1/0*
02,1/0
1/0
1/0
M5
M14
110
N4
RCLK-BUSYIROY-I/O
C8
A7
88
810
A12
812
A13
C12
vee
1i0
vee
vee
E2
1/0
01
All·I/O
1i0
02
AS-I/O
01-1/0
E3
Cl
1/0
1/0
N14
1i0
P2
1i0
81
Al0-1i0
M13
XTAL2-1/0
N3
1i0
C2
A9-1/0
L12
GNO
N2
OO-OIN-I/O
03
vee
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-limited .
• Indicates unconnected package pins for the XC3042.
2-35
•
XC3000 Logic Cell Array Family
XC3000 Family 164-Pin CQFP Pinouts
CQFPPin
Number
XC-3064
XC-3090
CQFPPin
Number
XC-3064
XC-3090
CQFPPin
Number
XC-3064
XC-3090
CQFPPin
Number
XC-3064
XC-3090
20
l'WROO
61
vo·
103
DONE-PG"
143
DO-DIN-IIO
21
TCLKIN-IIO
62
M1-~
104
07-110
144
DOUT-I/O
22
1/0'
63
GND
105
145
CClK
23
1/0'
64
MO-RTRIG
XTAl1(OUT)BClKIN-VO
146
Vee
24
VO
65
Vee
106
1/0'
147
GND
25
1/0'
66
M2-1/0
107
I/O
148
AO-WS-I/O
26
110
67
HDC-VO
108
I/O
149
A1-CS2-110
27
110'
68
110
109
D6-VO
150
110
28
VO
69
1/0
110
110
151
110
29
110
70
I/O
111
I/O
152
A2-1/0
153
A3-1/0
154
110
30
I/O
71
JJ::jC"-1/0
112
31
I/O
72
1/0'
113
VO
VO
32
I/O
73
VO
114
1/0
155
110
33
I/O
74
1/0'
115
D5-VO
156
A15-1I0
C"SO-VO
157
M-IIO
34
110
75
I/O
116
35
110
76
I/O
117
1/0'
158
110
36
77
I/O
118
VO
159
110
37
VO
VO
78
VO
119
1/0'
160
A14-110
38
110
79
110
120
I/O
161
A5-110
39
I/O
80
VO
121
D4-1/0
162
1/0'
40
I/O
81
W-IIO
122
110
41
GND
82
Vee
123
Vee
42
Vee
83
GND
124
GND
1
Vee
43
84
110
125
D3-VO
2
A13-1/0
44
VO
VO
85
1/0
126
CST-IIO
3
A6-1/0
45
110
86
VO
127
I/O
4
1/0
46
110
87
110
128
110'
5
1/0'
47
110
88
I/O
129
110
6
110
48
110
89
130
1/0'
7
1/0'
163
110'
164
GND
49
I/O
90
VO
VO
131
D2-110
8
A12-110
50
I/O
91
I/O
132
110
9
A7-1I0
51
110
92
I/O
133
110
10
110
52
93
110
134
110
11
110
53
VO
VO
94
110
135
110
12
A1HO
54
I/O
95
1/0
136
110
13
AS-IIO
55
VO
96
1/0'
137
D1-110
56
110
97
VO
138
RDYi£lUSYl'lcrK-110
57
1/0'
98
110'
58
VO
99
XTAl2(IN)-1I0
59
1/0'
100
GND
60
I/O
101
"RESET
102
Vee
139
I/O
140
110'
141
I/O
142
110'
Unprogrammed lOBs have a default pull-up_
This Prevents an undefined pad level for unbonded or unused 10Bs_
Programmed outputs are default slew-limited_
• Indicates unconnected package pins for the XC-3064_
2-36
14
VO
15
110
16
A10-1/0
17
A9-1/0
18
Vee
19
GND
E:XIUNX
XC3000 Family 175-Pin PGA Pinouts
PGA Pin
Number
B2
D4
B3
C4
B4
M
D5
C5
B5
AS
C6
D6
B6
A6
B7
C7
D7
A7
AS
88
C8
D8
D9
C9
B9
A9
Al0
Dl0
Cl0
Bl0
All
Bll
Dl1
Cll
A12
B12
C12
D12
A13
B13
C13
A14
XC-3090
I'WflOO
TClKIN-I/O
VO
VO
110
VO
110
110
VO
110
..
110
vq
110
110
VO
110
110
VO
110
110
110
GND
vee
VO
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
PGA Pin
Number
D13
B14
C14
B15
D14
C15
E14
B16
D15
Cll;
D16
F14
E15
E16
F15
F16
G14
G15
G16
H16
H15
H14
J14
J15
J16
K16
K15
K14
l16
l15
M16
110
PGA Pin
Number
R14
N13
T14
P13
R13
T13
N12
P12
R12
T12
Pll
Nll
Rll
Tll
Rl0
Pl0
Nl0
T10
T9
110
1IiIlT-VO
R9
P9
vee
N9
N8
P8
RB
T8
XC-3090
110
Ml-1mATl\"
GND
MO-RTRIG
vee
M2-VO
HDC-I/O
110
110
110
IDC"-vO
VO
110
110
VO
110
110
VO
GND
VO
110
110
110
110
T7
N7
P7
R7
T6
110
110
110
M15
L14
N16
P16
N15
R16
M14
P15
110
110
110
110
110
110
110
XTAl2(IN)-110
N14
R15
m:sET
P14
vee
R6
N6
P6
T5
R5
P5
N5
T4
R4
P4
GND
XC-3090
DONE-I'l!
07-1/0
XTAll (OUT)-BClKIN-VO
110
110
110
VO
D6-1/0
VO
VO
VO
110
VO
D5-1/0
CSO-I/O
110
110
110
110
D4-110
110
vee
GND
D3-IIO
CS"f-IiO
110
110
110
110
D2-1/0
110
110
110
110
110
Dl-IIO
RDYilmS'i'-~-lIo
110
110
VO
110
PGA Pin
Number
R3
N4
R2
P3
N3
P2
M3
Rl
N2
Pl
Nl
l3
M2
Ml
l2
L1
K3
K2
Kl
Jl
J2
J3
H3
H2
Hl
Gl
G2
G3
Fl
F2
El
E2
F3
Dl
Cl
D2
Bl
E3
C2
D3
C3
XC-3090
DO-DIN-IIO
DOUT-VO
CClK
vee
GND
AO-WS-I/O
Al:CS2-1/0
110
110
A2-1/0
A3-110
110
110
A15-110
M-IIO
VO
VO
A14-VO
AS-VO
VO
VO
GND
vee
A13-VO
A6-110
110
110
110
110
A12-1/0
A7-110
110
110
A11-IIO
AS-liD
110
110
A10-1I0
A9-110
vee
GND
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-limited.
Pins A2, A3, A15, A16, T1, T2, T3, T15 and T16 are not connected.
Pin A 1 does not exist.
2-37
•
XC3000 Logic Cell. Array Family
PARAMETRICS
Absolute Maximum Ratings
Units
Vee
Supply voltage relative to GND
-0.5 to 7.0
V
VIN
Input voltage with respect to GND
-0.5 to Vee + 0.5
V
VTS
Voltage applied to three-state output
-0.5 to Vee + 0.5
V
TSTG
Storage temperature (aml:?ient)
-65 to + 150
°C
TSOL
Maximum soldering temperature (10 sec @ 1/16 in.)
+ 260
°C
Junction temperature plastic
+ 125
°C
Junction temperature ceramic
+ 150
°C
TJ
"Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings
conditions for extended periods of time may affect device reliability.
Recommended Operating Conditions
Vee
Supply voltage relative to GND
Commercial
Supply voltage relative to GND
Industrial
Supply voltage relative to GND
Military
Min
Max
Units
4.75
5.25
V
-40°C to 85°C
4.5
5.5
V
-55°C to 125°C
4.5
5.5
V
O°C to 70°C
VIHT
High-level input voltage -
TIL configuration
2.0
Vee
V
VILT
Low-level input voltage -
TIL configuration
0
0.8
V
VIHe
High-level input voltage - CMOS configuration
70%
100%
Vee
ViLe
Low-level input voltage -
0
20%
Vee
TIN
Input signal transition time
250
ns
CMOS configuration
2-38
Min
Electrical Characteristics Over Operating Conditions
= -4.0 rnA, Vee min) Commercial
VOH
High-level output voltage (@ IOH
VOL
Low-level output voltage (@ IOl = 4.0 rnA, Vee min)
VOH
High-level output voltage (@ IOH = -4.0 rnA, Vec min)
VOL
Low-level output voHage (@ IOl
VOH
High-level output voltage (@loH = -4.0 rnA, Vee min)
VOL
Low-level output voltage (@ IOl = 4.0 rnA, Vee min)
leePD
Power-down supply current (Vee = 5.0 V @ 70°C)
Max
3.86
V
0.32
Industrial
3.76
= 4.0 rnA, Vee min)
V
V
0.37
Military
Units
3.7
V
V
0.4
V
XC3020
500
~
XC3030
800
~
XC3042
1150
~
XC3064
1650
~
XC3090
2500
~
500
~
10
rnA
,
leeo
Quiescent LCA supply current in addition to leePD 1
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels
ill
CIN
,
Leakage Current Commercial/Industrial Temperature
-10
+10
~
Leakage Current Military -55°C to 125°C
-20
+20
~
Input capacitance, all packages except PGA 175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2
10
15
pF
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2
15
20
pF
pF
0.02
0.17
rnA
0.4
3.4
rnA
= OV (sample tested)
IRIN
Pad pull-up (when selected) @ VIN
IRll
Horizontal long line pull-up (when selected) @ logic LOW
Note: 1. With no output current loads, no active input or long line pull-up resistors, all
package pins at Vee or GND, and the LCA configured with a MAKEBITS '1ie"
option. See LCA power chart for additional activity dependent operating component.
2-39
•
XC3000 Logic Cell Array Family
CLB SWITCHING CHARACTERISTIC GUIDELINES
CLB OUTPUT (X,V)
(COMBINATORIAL)
CLB INPUT (A,B,C,D,E)
CLBCLOCK
~---@TCL--~
o
TDICK
-----+--
CLB INPUT
(DIRECT IN)
CLB INPUT
(ENABLE CLOCK)
CLBOUTPUT
(FLIP-FLOP)
CLB INPUT
(RESET DIRECT)
CLBOUTPUT
(FLIP-FLOP)
1105 26
BUFFER (Internal) SWITCHING CHARACTERISTIC GUIDELINES
Speed Grade
Description
Symbol
Global and Alternate Clock Distribution""
Either: Normal lOB input pad to clock buffer input
Or: Fast (CMOS only) input pad to clock buffer input
Plus: Clock buffer input to any clock k
TPID
TPIDC
TBUF driving a Horizontal Longline (L.L.)"
I to L.L. while T is Low (buffer active)
T,J,. to L.L. active and valid
Ti to L.L. (inactive) with single pull-up resistor
with pair of pull-up resistors
TID
TON
Tpus
TpUF
BIOI
Bi-directional buffer delay
•• Timing is based on the XC3020, for other devices see XACT timing calculator.
2-40
-50
Min
-70
Max
Min
Units
-100
Max
Min Max
9
6
4
5
3
2
9
6
5
ns
ns
ns
ns
ns
ns
ns
ns
8
5
15
34
17
9
22
11
4
7
14
7
6
4
3
CLB SWITCHING CHARACTERISTIC GUIDELINES (Continued)
Testing of the switching characteristic guidelines is modeled after testing specified by MIL-M-3851 0/605. Devices are 100%
functionally tested. Benchmark timing patterns are used to provide correlation to the switching characteristic guideline values.
Actual worst-case timing is provided by the XACT Timing calculator or Simulation modeling.
Speed Grade
Description
Combinatorial Delay
Logic Variables a, b, c, d, e, to outputs x, y
Sequential delay
Clock k to outputs x, y
Clock k to outputs x,y when Q is returned
through function generators F or G to drive x, y
Set-up time before clock K
Logic Variables
a,b,c,d,e
Data In
di
Enable Clock
ec
Reset Direct inactive rd
Hold Time after clock k
Logic Variables
a,b,c,d,e
Data In
di
Enable Clock
ec
Clock
Clock High time'
Clock Low time'
Max. flip-flop toggle rate'
Reset Direct (rd)
rd width
delay from rd to outputs x, y
Symbol
-50
Min
Max
Units
-70
-100
Min Max
Min Max
1
TllO
14
9
7
ns
8
TCKO
12
8
7
ns
23
15
12
ns
2
4
6
TICK
TDICK
TECCK
12
8
10
2
8
5
7
1
7
4
5
1
ns
ns
ns
ns
3
5
7
TCKI
TCKDI
TCKEc
0
6
0
0
4
0
0
2
0
ns
ns
ns
11
12
TCH
TCl
FClK
9
9
50
7
7
70
5
5
100
ns
ns
MHz
13
9
TRpw
TRIO
12
TMRw
TMRQ
38
Master Reset (MR)
MRwidth
delay from MR to outputs x, y
7
8
12
8
25
30
7
ns
ns
17
ns
ns
21
20
• These timing limits are based on calculations.
Note: The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (TCKDI, #5) of any CLB on the same die.
2-41
•
XC3000 Logic Cell Array Family
lOB SWITCHING CHARACTERISTIC GUIDELINES
==®~"Dt-·=0_t-=--=--_-]-~~=
.'.
110 BLOCK (I)
110 PAD INPUT
~
110 CLOCK
(IKlOK)
1
TplCK
@
TIOl
®
TIKPI
@TloHJ-
4-0TIKR~
110 BLOCK (RI)
J@
RESET
~®
.... @TRPOI+-
@TOKO
TOOK
110 BLOCK (0)
@TOp _
f
110 PAD OUTPUT
(DIRECT)
110 PAD OUTPUT
(REGISTERED)
--
r,=..0
TOKPO
)K
J
VOPADTS
va PAD OUTPUT
1105 27
PROGRAM·CONTROLLED MEMORY CELLS
THREE STATE
(OUTPUT ENABLE)
OUT
Vo<
~~f.:~.t'--I-____=;IL)------t-~
J.~!--,,_ /
I~
DIRECT IN
REGISTERED IN
~.".
~1~·q'----t---I
'----f--------.
j}
CCNTROlLED
MULTIPLEXER
"i~'
0"'
_.._. _
. ._
. ._"f:-
PROGRAMMABLE INTERCONNECTION POINT'or PIP
2-42
lOB SWITCHING CHARACTERISTIC GUIDELINES (Continued)
Testing of the switching characteristic guidelines is modeled after testing specified by MIL-M-3851 0/605. Devices are 100%
functionally tested. Benchmark timing patterns are used to provide correlation to the switching charC1eristic guideline values.
Actual worst-case timing is provided by the XACT Timing calculator or Simulation modeling.
-50
Description
Propagation Delays (Input)
Pad to Direct In (i)
Pad to Registered In (q) with latch transparent
Clock (ik) to Registered In (q)
Symbol
3
4
TPID
TpTG
TIKRI
Set-up Time (Input)
Pad to Clock (ik) set-up time
1
TPICK
Propagation Delays (Output)
Clock (ok) to Pad
(fast)
same
(slew rate limited)
Output (0) to Pad
(fast)
same
(slew-rate limited)
Three-state to Pad begin hi-Z (fast)
same
(slew-rate limited)
Three state to Pad active and valid (fast)
same
(slew -rate limited)
7
7
10
10
9
9
8
8
TOKPO
TOKPo
TOPF
Tops
TTsHz
TTsHz
TTsoN
TTsoN
5
TOOK
TOKO
Set-up and Hold Times (Output)
Output (0) to clock (ok) set-up time
Output (0) to clock (ok) hold time
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Master Reset Delays
RESET Pad to Registered In (q)
RESET Pad to output pad
6
11
12
TCH
TCl
FCLK
13
15
TRRI
TRPO
Min
Max
-70
-100
Min Max
Min Max
9
34
11
18
43
15
40
12
37
20
45
15
0
9
9
50
35
50
4
17
6
21
7
20
30
Units
6
17
ns
10
27
13
33
9
29
8
28
14
34
ns
ns
ns
6
23
8
25
12
29
ns
ns
ns
ns
ns
ns
ns
ns
10
0
9
0
ns
ns
7
7
70
5
5
100
ns
ns
MHz
23
33
20
28
ns
ns
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture).
Typical fast mode output riselfall times are 2 ns and will increase approximately 2%/pF of additional load.
Typical slew rate limited output rise/fall times are approximately 4 times longer.
A maximum total external capacitive load for simUltaneous fast mode switching in the same direction
is 500 pF per power/ground pin pair. For Slew-rate limited outputs this total is 4 times larger.
2. Voltage levels of unused (bonded and Unbonded) pads must be valid logic levels. Each can be configured
with the internal pull-up resistor or alternatively configured .as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (.ik)
In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value.
Input pad holdtime with respect to the internal clock (ik) is negative. This means that pad level changes immediately
before the internal clock edge (ik) will not be recognized.
For a more detailed description see the discussion on "LeA Performance" in the Applications chapter
(6-14 to 18).
2-43
XC3000 Logic Cell Array Family
GENERAL LCA SWITCHING CHARACTERISTICS
(0™RW)________
r - - - - - - - i l t....
' __
MO/M1/M2
----,f®'~®'~f-------~®TPGW=-1
DONEtPROG
___J
__----,[®TPGI
INIT
(OUTPUT)
USER STATE
______C_L_EA~RI_S-T-AT-E--------J/
--
II
CONFIGURATION STATE
.
\~~-~/
r-NOTE3-j
Vee (VAUDj
------------------------------~\
(~~t-----
•\.
____ i
J~
VCCPD
1105 28
-50
Description
RESET (2)
DONEJPROG
PWRDWN (3)
Symbol
MO, M1, M2 setup time required
MO, M1, M2 hold time required
RESET Width (Low) req. for Abort
2
3
Width (Low) required for Re-config.
INIT response after Dip is pulled Low
5
4
6
Power Down Vcc
TMR
TRM
TMRW
TpGW
TpGI
VCCPD
Min
1
1
-70
Units
Max
Min
Max
Min
Max
0
1
1
0
0
0
6
6
6
6
7
2.0
Notes: 1. Vee must rise from 2.0 Volts to Vee minimum in less than 10 ms for master modes.
2. RESET timing relative to valid mode lines (MO, M1, M2) is relevant
when ~ is used to delay configuration.
3. PWRDWN transitions must occur during operational Vcc levels.
2-44
-100
6
7
7
2.0
2.0
115
115
115
115
115
V
MASTER SERIAL MODE SWITCHING CHARACTERISTICS GUIDELINES
CClK
(OUTPUT)
SERIAL DATA IN
1105 29
SERIAL DOUT
(OUTPUT) _ _ _ _ _---J
' - - _ _ _ _ _---J ' - -_ _ _ _ _- ' '-_ _ _ _ _ _ __
Description
CCLK3
Data In setup
Data In hold
Symbol
1
2
Min
TDSCK
TCKDS
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min. in less than 10 ms,
otherwise delay configuration using RESET until Vcc is valid.
2. Configuration can be controlled by holding RESET low with or until after
the INIT of all daisy-chain slave mode devices is HIGH.
3. Master serial mode timing is based on slave mode testing.
2-45
-70
-50
Speed Grade
60
0
Max
Min
60
0
Max
Units
Min
Max
ns
ns
•
XC3000 Logic Cell Array Family
MASTER PARALLEL MODE PROGRAMMING SWITCHING
CHARACTERISTIC GUIDELINES
Testing of the switching characteristic guidelines is modeled after testing specified by MIL-M-3851 0/605. Devices are 100%
functionally tested. Benchmark timing patterns are used to provide correlation to the switching charcteristic guideline values.
Actual worst-case timing is provided by the XACT Timing calculator or Simulation modeling.
AO-A15
ADDRESS for BYTE n
(OUTPUl)
ADDRESS for BYTE n + 1
DO-D7
RCLK
(OUTPUl)
~~====-::"-::"-:'~-7-C-C-L-KS-
/
_-_-_-_-_-_-J""""",,_--
CCLK
(OUTPUl)
DOUT
(OUTPUl)
D7
BYTE
n-1
110530
-70
-50
Symbol
Description
RCLK
To address valid
To data setup
To data hold
RCLK high
RCLK low
1
2
3
TRAC
TDRC
TRCD
TRCH
TRCL
Min
Max
Min
Max
0
60
0
600
4.0
200
0 200
60
0
600
4.0
Units
Min
Max
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vee min. in less than 10 ms,
otherwise delay configuration using RESET until Vee is valid.
2. Configuration can be contorlled by holding RESET low with or until
after the TNlT of all daisy-chain slave mode devices is HIGH.
This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.
2-46
ns
ns
ns
ns
Ils
PERIPHERAL MODE PROGRAMMING SWITCHING CHARACTERISTICS
7
CS2
(
I
\
\
CSlICSO
,,
,
,J
,,
00-07
CCLI<
ROY/BUSY
OOUT
1105 10
,,
\. ___ J
,,
II
,,
,,
\. ___ J
_______________________ J
:
_---Jx'--_-.Jx'--_____
---J
\...----.JX'---__L
-50
Description
Write
ROY
Notes:
Symbol
Min
-70
Max
Units
-100
Min Max
Min
Max
WS Low time reqired
1
TCA
0.5
0.5
0.5
JlS
DIN setup time required
DIN hold time required
2
3
Toc
Tco
60
0
60
0
60
0
ns
ns
ROY/BUSY delay after end of WS
4
TWTRB
Earliest next WS after end of BUSY
5
TRBWT
0
BUSY Low time generated
6
TBUSY
4
60
60
0
9
4
60
ns
0
9
4
ns
9
CCLK
Periods
mrr
1. Configuration must be delayed until the
of all LCAs is HIGH.
2. Time from end of WS to CCLK cycle for the new byte of data
depends on completion of previous byte processing and the phase
of the internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
This timing diagram shows very relaxed requirements:
Data need not be held beyond the rising edge of WS. BUSY will go active within 60 ns after the end of WS. BUSY will stay
active for several microseconds. WS may be asserted immediately after the end of BUSY.
2-47
XC3000 Logic Cell Array Family
SLAVE MODE PROGRAMMING SWITCHING CHARACTERISTICS
:: =to ·=tl4:_@_2_l:_=2= - - -<'1*'~1_'·~ '=j~_TC_C_L r__
___
(OUTPUT)
JK
BIT N-1
-50
Description
CCLK
Symbol
To DOUT
DIN setup
DIN hold
High time
Low time
Frequency
Min
Tcco
TDCC
TCCD
TCCH
TCCL
Fcc
3
1
2
4
5
BIT N
Units
-70
Max
Min Max
5.0
1
Min Max
ns
ns
ns
ns
100
100
60
0
0.5
0.5
110531
60
0
0.5
0.5
5.0
1
~s
MHz
Note: Configuration must be delayed until the INIT of all LCAs is HIGH.
PROGRAM READBACK SWITCHING CHARACTERISTICS
DONE/PROG
(OUTPUT)
____-L/___________________________________ _
~0
RTRIG
@
RDATA
t~
7
TRTCC~
CCLK(1)
(OUTPUT)
TRTH--1
_ __
Ir----~
CD TCCRD ~Ir-------------
)K VALID
_ _ _ _ _ _---J
-50
Description
Symbol
RTRIG
RTRIG high
1
TRTH
CCLK
RTRIG setup
RDATAdelay
2
3
TRTCC
TCCRD
Min
Units
-70
Max
250
Min Max
10
10
100
Min Max
ns
250
100
Notes: 1. CCLK and DOUT timing are the same as for slave mode.
2. RETRIG (MO positive transition) shall not be done until after one clock following active 110 pins.
3. Readback should not be initiated until configuration is complete.
2-48
1105 32
ns
ns
E':XIUNX
L
1/.
PIN NO. 1
.045
PIN NO.1 IDENTIFIER
.045 x 45' " "
9
61
c
PWRDWN
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±.OO5 ±.OO4
Va;
Va;
1
PIN SPACING
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M1
MO
DONE
RESET
Ir~:2~7~~~~~~~~5'::'i:~;:;4i5':'i::;=;::~
LEAD C()'PLANARllY ± 0.002 IN
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ALL DIMENSIONS ARE
IN INCHES
9 JA = 35-40 'CIW
110534
58-Pin PLCC Package
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PIN NO. 1
11
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±.005
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PIN NO.1 IDENTIFIER
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I
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CCLK
DOUT/IO
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PIN SPACING
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RESET
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DIMENSIONS ARE IN INCHES
1105 36
9 JA = 30-35 'C/W
84-Pin PLCC Package
2-49
.028 ~=I==I:=*""7""--lL
•
XC3000 Logic Cell Array Family
1.100:t.012
1.000±.010
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110535
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0.009 +/- 0.005
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PIN SPACING
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All. DIMENSIONS IN INCHES
0JA • 71l-8O" CtW (OSl)
110539
100·Pin PQFP Package
2·50
----------------------
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LEAOFRAME
O.OO5THK
DEVfTREOUS
SOLDER GLASS
r
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0.145 MAX
0.0300 .0.0050
BOTTOM VIEW
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0.0500 10.0050
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SIDE VIEW
TYP
PIN SPACING
0.025 TYPICAL
NOTES:
1. LEADS.ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS
2. FORMINce TOOL INFORMATION:
- FANCORT INDUSTRIES - (201) 575-0610 weST CALDWELL NJ.
-IlISIINOUSTllIES(619}425-a970CHULA VISTA, CA
4
ALL DIMENSIONS IN INCHES
8JA - 40'50" CJW (ost'
TOP VIEW
(DIE FACING OQWN)
8JC - 5-41° CIW(oSt)
110540
100-PiilCQFP Package
2-51
XC3000 Logic Cell Array Family
INDEX
MARK
DIMENSIONS ARE IN INCHES
--+------ ---------+--------
___-+__
8 JA =25-30·CIW
8.;c=5°CNV
,.085 i.OO9
PIN KOVAR
----i !+- .018 ±.OO2 DIA. 132 PlCS
.040 X 45°
4PLCS.
10
11
12
13
14
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--------1
1----------1~g---------~
132·Pin PGA Package
2·52
1105 38
LEADFRAME
0.005 THK
DEvrrREOUS
SOLDER GLASS
HYP
.~[
PIN SPACING
0.025 TYPICAL
L
0.145 MAxj 1111
0:0300 .0.0050
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(LID SIDE UP)
(DIE FACING UP)
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0.0500 .0.0050
0.120 MAX
SIDE VIEW
0.011 TYP
PIN SPACING
0.025 TYPICAL
NOTES:
1. LEADS ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS
2. FORMING TOOL INFORMATION:
_ FANCORT INDUSTRIES - (201) 575-0610 WEST CALDWELL NJ.
_ RISIINDUSTRIES INC. (619) 425-3970 CHULA VISTA, CA
TOP VIEW
(DIE FACING DOWN)
ALL DIMENSIONS IN INCHES
9JA - 35-45' CIW (e.l)
9JC -3-5' CIW (e.t)
1105.41
164-Pin CQFP Package
2-53
II
XC3000 Logic Cell Array Family
o
-I--ir------,+------tt--t-
NOEl<
8JA_18 DC/rN
8JC.O.5-1.0"CIW
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WE10 METAUC HEATSIIIK
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J
PIN KOVAR
.OOSR. TYP.
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110000
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J
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DIELECTRIC COAT
STANO OFF PIN
4PL
F
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110537
175-Pin PGA Package
2-54
0.046
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o
o
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o
0
0
0
0
0
0
0
0
0
0
0
0
0
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0
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0
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0
0
0
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0
0
0
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0
0
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0
0
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0
0
0
0
0
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0
0
0
0
0
0
0
0
0
0
0
0
0
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0
0
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0
0
0
0
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0
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0
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Typ
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175-Pin PPGA Package
•
Component Selection &
Ordering Information
XC2064
XC2018
XC3020
XC3030
XC3042
XC3064
XC3090
197201
XC1736-PD8C
XC1736-CD8M
Plastic 8 Pin, Mini-DIP -40°C to 85°C
Ceramic 8 Pin, Mini-DIP -55°C to 125°C
LCA Temperature Options
Symbol
Description
C
I
M
B
Commercial
Industrial
Military
Military
Temperature
O°Cto 70°C
-40°C to 85°C
-55°C to 125°C
MIL-STD-883, Class B
ORDERING INFORMATION
-- IJ TTL
Example:
Toggle
Rate
XC2064-70PC68C
,_.M.
Range
Number of Pins
Package Type
COMPATIBLE PACKAGE OPTIONS
A range of Xilinx LCA devices is available in identical
packages with identical pin-outs. A design can thus be
started with one device, then migrated to a larger or
smaller chip while retaining the original footprint and
PC-board layout.
Examples:
PLCC 68:
PLCC84:
PGA84:
POFP 100:
COFP100:
PGA 132:
2064-2018-3020-3030
2018-3020-3030-3042
2018·3020-3030-3042
3020·3030-3042
3020-3030-3042
3042-3064
Note, however, that the XC2000 and XC3000 families
differ in the position of XTL 1 as well as three parallel
address bits (6, 7 and 11) and most of the data pins used
in parallel master mode.
XC2018 and XC3020 are not available in PGA68, since
the PGA84 is the same size and offers more I/O.
Note that a PLCC in a socket with PGA footprint generates
a printed circuit board pin-out differentfrom a PGA device.
1972
XC2064
XC2018
Logic Cell™ Array
Product Specification
Part
Number
FEATURES
• Fully user-programmable:
• 1/0 functions
• Digital logic functions
• Interconnections
• General-purpose array architecture
• Complete user control of design cycle
• Compatible arrays with logic cell complexity equivalent
to 1200 and 1800 usable gates
• Standard product availability
• 100% factory-tested
• Selectable configuration modes
• Low-power, CMOS, static memory technology
• Performance equivalent to TTL SSIIMSI
• TTL or CMOS input thresholds
• Complete development system support
• XACT Design Editor
• Schematic Entry
• XACTOR In Circuit Emulator
• Macro Library
• Timing Calculator
• Logic and Timing Simulator
• Auto Place I Route
DESCRIPTION
The Logic Cell™ Array (LCA) is a high density CMOS
integrated circuit. Its user-programmable array architecture is made up of three types of configurable elements:
InputlOutput Blocks, Logic Blocks and Interconnect. The
designer can define individual 1/0 blocks for interface to
external circuitry, define logic blocks to implement logic
functions and define interconnection networks to compose
larger scale logic functions. The XACTTM Development
System provides interactive graphic design capture and
automatic routing. Both logic simulation and in-circuit
emulation are available for design verification.
XC2064
XC2018
Logic
Capacity
User
lias
(usable)
gates
Configurable
Logic
Blocks
1200
1800
64
100
58
74
Configuration
Program
(bits)
12038
17878
The Logic Cell Array's logic functions and interconnections are determined by data stored in internal static
memory cells. On-chip logic provides for automatic loading of configuration data at power-up. The program data
can reside in an EEPROM, EPROM or ROM on the circuit
board or on a floppy disk or hard disk. The program can be
loaded in a number of modes to accommodate various
system requirements.
ARCHITECTURE
The general structure of a Logic Cell Array is shown in
Figure 1. The elements of the array include three categories of user programmable elements: 1/0 Blocks,Configurable Logic Blocks and Programmable Interconnections.
The 1/0 Blocks provide an interface between the logic
array and the device package pins. The Configurable
Logic Blocks perform user-specified logic functions, and
the interconnect resources are programmed to form networks that carry logic signals among blocks.
Configuration of the Logic Cell Array is established
through a distributed array of memory cells. The XACT
development system generates the program used to
configure the Logic Cell Array. The Logic Cell Array
includes logic to implement automatic configuration.
Configuration Memory
The configuration of the Xilinx Logic Cell Array is established by programming memory cells which determine the
logic functions and interconnections. The memory loading
process is independent of the user logic functions.
The Logic Cell Array is available in a variety of logic
capacities, package styles, temperature ranges and
speed grades.
2-55
XC206412018 Logic Cell Array
The static memory cell used for the configuration memory
in the Logic Cell Array has been designed specifically for
high reliability and noise immunity. Based on this design,
which is covered by a pending patent application, integrity
of the LCA configuration memory is assured even under
adverse conditions. Compared with other programming
alternatives, static memory provides the best combination
of high density, high performance, high reliability and
comprehensive testability. As shown in Figure 2, the basic
memory cell consists of two CMOS inverters plus a pass
transistor used for writing data to the cell. The cell is only
written during configuration and only read during readback. During normal operation the pass transistor is "off"
and does not affect the stability of the cell. This is quite
different from the normal operation of conventional memory devices, in which the cells are continuously read and
rewritten.
structure of the configuration memory cells, they are not
affected by extreme power supply excursions or very high
levels of alpha particle radiation. In reliability testing no
soft errors have been observed, even in the presence of
very high doses of alpha radiation.
Input/Output Block
Each user-configurable I/O block (lOB) provides an interface between the external package pin of the device and
the internal logic. Each I/O block includes a programmable
input path and a programmable output buffer. It also
provides input clamping diodes to provide protection from
electro-static damage, and circuits to protect the LCA from
latch-up due to input currents. Figure 3 shows the general
structure of the I/O block.
The input buffer portion of each I/O block provides threshold detection to translate external signals applied to the
package pin to internal logic levels. The input buffer
threshold of the I/O blocks can be programmed to be
The outputs Q and Q control pass-transistor gates directly.
The absence of sense amplifiers and the output capacitive
load provide additional stability to the cell. Due to the
I/O BLOCK
Q OQ
0
CONFIGURABLE
LOGIC BLOCK~
-[}
-[}
-[}
-[}
-[}
-[}
-[}
o
0 0 0
0 01 0 0
0 0j0 0
0 0 0 0
•
INTERCONNECT AREA
Figure 1. Logic Cell Array Structure
2-56
•
M04 01
block output buffer. Each I/O block output buffer is controlled by the contents of two configuration memory cells
which turn the buffer ON or OFF or select logical threestate buffer control. The user may also select the output
buffer three-state control (I/O block pin TS). When this
I/O block output control signal is HIGH (a logic "1") the
buffer is disabled and the package pin is high-impedance.
compatible with either TTL (1.4 V) or CMOS (2.2 V) levels.
The buffered input signal drives both the data input of an
edge triggered 0 flip-flop and one input of a two-input
multiplexer. The output of the flip-flop provides the other
input to the multiplexer. The user can select either the
direct input path or the registered input, based on the
content of the memory cell controlling the multiplexer. The
I/O Blocks along each edge of the die share common
clocks. The flip-flops are reset during configuration as well
as by the active-low chip RESET input.
Configurable Logic Block
An array of Configurable Logic Blocks (CLBs) provides the
functional elements from which the user's logic is constructed. The Logic Blocks are arranged in a matrix in the
center of the device. The XC2064 has 64 such blocks
Output buffers inthe I/O blocks provide 4 mAdrive for high
fan-out CMOS or TTL compatible signal levels. The output
data (driving I/O block pin 0) is the data source for the I/O
READorWRITE _ _
DATA
l~ :,- -·'·'·'·_· · · ·- ,-· ~~---,--·····-~t:
· - +~r.
=;iiMTI~
__
--.W'-
~
:~""-"'-"'-'-'-"" ....-...-.-.-.-.-...-.-...-.....-...-.-...-...........-.-.:.:.-.:.:.:.:.:...:...:.-.:.-.:.:.:.:.....:.:.:.-.~:.:.:.......... ;:
1104 02
Figure 2. Configuration Memory Cell
I--------------;;_-+--
TS (OUTPUT ENABLE)
OUT
IN
D
0 f-----J
VOCLOCK
~
_ PROGRAM-CONTROLLED
~ - MULTIPLEXER
1104 03
Figure 3. 1/0 Block
2-57
XC206412018 Logic Cell Array
X
OUTPUTS
A
INPUTS
B
C
0
G
Y
COMB.
LOGIC
F
CLOCK
1104 04
Figure 4. Conflgurable Logic Block
arranged in an 8-row by 8-column matrix. The XC2018 has
100 logic blocks arranged in a 10 by 10 matrix.
third form of the combinatorial logic (Option 3) is a special
case of the two-function form in which the B input dynamically selects between the two function tables providing a
single merged logic function output. This dynamic selec-
Each logic block has a combinatorial logic section, a
storage element, and an internal routing and control section. Each CLB has four general-purpose inputs: A, B, C
and D; and a special clock input (K), which may be driven
fromthe interconnect adjacenttothe block. Each CLB also
has two outputs, X and Y, which may drive interconnect
networks. Figure 4 shows the resources of a Configurable
Logic Block.
The logic block combinatorial logic uses a table look-up
memory to implement Boolean functions. This tech-nique
can generate any logic function of up to four variables with
a high speed sixteen-bit memory. The propagation delay
through the combinatorial network is independent of the
function generated. Each block can perform any function
of four variables or any two functions of three variables
each. The variables may be selected from among the four
inputs and the block's storage element output "Q".
Figure 5 shows various options which may be specified for
the combinatorial logic.
F
A
ANY
FUNCTION
B
OF4
C
D
If the single four-variable configuration is selected (Option
1), the F and G outputs are identical. If the two-function
alternative is selected (Option 2), logic functions F and G
-
~
G
OPTION 1
may be independent functions of three variables each.
The three variables can be selected from among the four
logic block inputs and its storage element output "Q". A
1 FUNCTION OF 4
VARIABLES
2-58
I----<
VARIABLES
High inputs and the asynchronous reset is dominant. The
storage elements are reset by the active-low chip RESET
pin as well as by the initialization phase preceding configuration. If the storage element is not used, it is disabled.
tion allows some five-variable functions to be generated
from the four block inputs and storage element Q. Combinatorial functions are restricted in that one may not use
both its storage element output Q and the input variable of
the logic block pin "0" in the same function.
The two block outputs, X and Y, can be driven by either the
combinatorial functions, F or G, or the storage element
output Q (Figure 4). Selection of the outputs is completely
interchangeable and may be made to optimize routing
efficiencies of the networks interconnecting the logic
blocks and 1/0 blocks.
If used, the storage element in each Configurable Logic
Block (Figure 6) can be programmed to be either an edgesensitive "0" type flip-flop or a level-sensitive "0" latch.
The clock or enable for each storage element can be
selected from:
Programmable Interconnect
• The special-purpose clock input K
• The general-purpose input C
• The combinatorial function G
Programmable interconnection resources in the Logic Cell
Array provide routing paths to connect inputs and outputs
of the I/O and logic blocks into desired networks. All
interconnections are composed of metal segments, with
programmable switching points provided to implement the
necessary routing. Three types of resources accommodate different types of networks:
The user may also select the clock active sense within
each logic block. This programmable inversion eliminates the need to route both phases of a clock signal
throughout the device.
The storage element data input is supplied from the
function F output of the combinatorial logic. Asynchronous SET and RESET controls are provided for each
storage element. The user may enable these controls
independently and select their source. They are active
1104 05
• General purpose interconnect
• Long lines
• Oirect connection
OPTION 2
OPTION 3
2 FUNCTIONS OF 3
VARIABLES
DYNAMIC SELECTION OF
2 FUNCTIONS OF 3
VARIABLES
Figure 5. CLB Combinatorial Logic Options
Note: Variables 0 and Q can not be used in the csame function.
2-59
•
XC206412018 Logic Cell Array
General·Purpose Interconnect
General-purpose interconnect, as shown in Figure 7a, is
composed of four horizontal metal segments between the
rows and five vertical metal segments between the columns of logic and 1/0 blocks. Each segment is only the
"height" or "width" of a logic block. Where these segments
would cross at the intersections of rows and columns,
switching matrices are provided to allow interconnections
of metal segments from the adjoining rows and columns.
Switches in the switch matrices and on block outputs are
specially designed transistors, each controlled by a configuration bit.
Logic block output switches provide contacts to adjacent
general interconnect segments and therefore to the
switching matrix at each end of those segments. A switch
matrix can connect an interconnect segment to other
segments to form a network. Figure 7a shows the general
interconnect used to route a signal from one logic block to
three other logic blocks. As shown, combinations of
closed switches in a switch matrix allow multiple branches
for each network. The inputs of the logic or 1/0 blocks are
multiplexers that can be program-med with configuration
bits to select an input network from the adjacent interconnect segments. Since the switch connections to block
inputs are unidirectional (as are block outputs) they are
usable only for input connection. The development system software provides automatic routing of these interconnections. Interactive routing is also available for design
optimization. This is accomplished by selecting a network
and then toggling the states of the interconnect points by
selecting them with the "mouse". In this mode, the connections through the switch matrix may be established by
selecting pairs of matrix pins. The switching matrix combinations are indicated in Figure 7b.
Special buffers withi!) the interconnect area provide periodic signal isolation and restoration for higher general
interconnect fan-out and better performance. The repowering buffers are bidirectional, since signals must be able
to propagate in either direction on a general interconnect
segment. Direction controls are automatically established
by the Logic Cell Array development system software.
Repowering buffers are provided only for the generalpurpose interconnect since the direct and long line resources do not exhibit the same R-C delay accumulation.
The Logic Cell Array is divided into nine sections with
buffers automatically provided for general interconnect at
the boundaries of these sections. These boundaries can
be viewed with the development system. For routing
within a section, no buffers are used. The delay calculator
of the XACT development system automatically calculates
and displays the block, interconnect and buffer delays for
any selected paths.
CLB
1104 06
I
I
A-(-----I
•• ...l
A
B
C
K
SET
F-----------lD
x
CLB J-+--t*i+t--
y
0
K-}----I
-,:-----1
SEE FIG. 7b
o
C
RES
D-'~---I
CLB
t+++r----.-J
CLB
1104 07
Figure 6. CLB Storage Elememt
Figure 7a. General·Purpose Interconnect
2-60
the global buffer for a clock provides a very low skew, high
fan-out synchronized clock for use at any or all of the logic
blocks. At each block, a configuration bit for the K input to
the block can select this global line as the storage element
clock signal. Alternatively, other clock sources can be
used.
Long Lines
Long-lines, shown in Figure 8a, run both vertically and
horizontally the height or width of the interconnect area.
Each vertical interconnection column has two long lines;
each horizontal row has one, with an additional long line
adjacent to each set of I/O blocks. The long lines bypass
the switch matrices and are intended primarily for signals
that must travel a long distance or must have minimum
skew among multiple destinations.
A second buffer below the bottom row of the array drives
a horizontal long line which, in tum, can drive a vertical long
line in each interconnection column. This aHernate buffer
also has low skew and high fan-out capability. The
network formed by this alternate buffer's long lines can be
selected to drive the B, C or K inputs of the logic blocks.
A global buffer in the Logic Cell Array is available to drive
a single signal to all Band K inputs of logic blocks. Using
2 VERTICAL
LONG LINES
~
I I I I
GLOBAL
NET
r-'--.
I I
I,
AVAILABLE PROGRAMMABLE
SWITCH MATRIX INTERCONNECTIONS
OF GENERAL INTERCONNECT
SEGMENTS BY PIN
g' tJ'
,
,,,
t;r,
, ,
00
0
0
a
7
6
,-I
,,
:0
,,
a
b
a
X
Y
:,
3
a
3
4
7
4
3
{~
0
-}
_
_
4 HORIZONTAL
GENERAL PURPOSE
INTERCONNECT
:0
a
3
s
4
7
~'
8
4
7
I I I I
,
\
PROGRAMMABLE
INTERCONNECT POINTS
(DO NOT USE MORE THAN
ONE PER INPUT PIN)
1104 08
Figure 7b. Routing and Switch Matrix Connections
2-61
5
S'
3
5
4
6
a
I
I
I
I
I
I
I
5 VERTICAL
GENERAL PURPOSE
INTERCONNECT
BETWEEN SWITCH
MATRICES
5
7
6
r-'
0
0
•
7
,
DO
4
• •
7
6
0
7
3
a
6
QQO
OQ
4
•
U'
QQO
, ,
a
s.. .'
a., e.,
0
t;r,
, ,
3
3
4
6
6
•
XC206412018 Logic Cell Array
bottom of the die. Direct interconnections of 1/0 blocks
with CLBs are shown in Figure 8b.
Alternatively, these long. lines can be driven by a logic or
1/0 block on a column by column basis. This capability
provides a common, low-slsew clock or control line within
each column of logic blocks. Interconnections of these
long lines are shown in Figure 8b.
Crystal Oscillator
An internal high speed inverting amplifier is available to
implement an on-Chip crystal OSCillator, ·It is associated
with the auxiliary clock buffer in the lower right corner of the
die. When configured to drive the auxiliary clock buffer,
two special adjacent user 110 blocks are also configured to
connect the oscillator amplifier with external crystal oscillator components, as shown in Figure 10. This circuit
becomes active before configuration is complete in order
to allow the oscillator to stabilize. Actual internal connection is delayed until completion of configuration. The
feedback resistor R1 between output and input, biases the
amplifier at threshold. It should be as large a value as
practical to minimize loading of the crystal. The inversion
of the amplifier, together with the R-C networks and
crystal, produce the 360-degree phase shift of the Pierce
oscillator. A series resistor R2 may be included to add to
Direct Interconnect
Direct interconnect, shown in Figure 9, provides the most
efficient implementation of networks between adjacent
logic or 1/0 blocks. Signals routed from blgck to block by
means of direct interconnect exhibit minimum int!lrconnect propagation and use minimum interconnect resources. For each Configurable Logic Block, the X output
may be connected directly to the Cor D inputs of the CLB
above and to the A or B inputs of the CLB below it. The Y
output can use direct interconnect to drive the B input of the
block immediately to its right. Where logic blocks are
adjacent to 1/0 blocks, direct connect is provided to the
1/0 block input (I) on the left edge ofthe die, the output (0)
on the right edge, or both on 1/0 blocks at the top and
a a
a a
a a
I
B
~
.
0 CLB
SWITCH
MATRIX
I
L-
X
Y
SWITCH
MATRIX
-----l
TWO VERTICAL
LONG LINES
L-
HORIZONTAL
LONG LINE
GLOBAL
LONG LINE
1104 09
Figure 8a. Long Line Interconnect
2-62
GLOBAL
BUFFER
VERTICAL LONG LINES
(2 PER COLUMN)
HORIZONTAL LONG LINES
(1 PERROW)
1/0 CLOCKS
(1 PER EDGE)
•
~
z
z
i
1/0 CLOCKS
(1PER EDGE)
ALTERNATE
BUFFER
Figure ab. XC2064 Long Lines, (fa Clocks, 1/0 Direct Interconnect
2-63
OSCILLATOR
AMPLIFIER
XC2064/2018 Logic Cell Array
the amplifier output impe-dance when needed for phaseshift control or crystal resistance matching or to limit the
amplifier input swing to control clipping at large amplitudes. Excess feedback voltage may be adjusted by the
ratio of C2/C1. The amplifier is designed to be used over
the range from 1 MHz up to one-half the specified CLB
toggle frequency. Use at frequencies below 1 MHz may
require individual characterization with respect to a series
resistance. Operation at frequencies above 20 MHz
generally requires a crystal to operate in a third overtone
mode, in which the fundamental frequency must be suppressed by the R-C networks. When the amplifier does not
drive the auxiliary buffer, these 1/0 blocks and their package pins are available for general user 1/0.
For packages having more than 48 pins, two Vcc pins and
two ground pins are provided (see Figure 11). Inside the
LCA, a dedicated Vcc and ground ring surrounding the
logic array provides power to the 110 drivers. An independent matrix of Vcc and ground lines supplies the interior
logic of the device. This power distribution grid provides a
stable supply and ground for all internal logic, providing the
external package power pins are appropriately decoupled.
Typically a 0.1 ~F capacitor connected between the Vcc
and ground pins near the package will provide adequate
decoupling.
Output buffers capable of driving the specified 4 rnA loads
under worst-case conditions may be capable of driving 25
to 30 times that current in a best case. Noise can be
reduced by minimizing external load capacitance and
reducing simultaneous output transitions in the same
direction. It may also be beneficial to locate heavily loaded
output buffers near the ground pads. Multiple Vcc and
ground pin connections are required for package types
which provide them.
POWER
Power Distribution
Power for the LCA is distributed through a grid to achieve
high noise immunity and isolation between logic and 1/0.
Power Dissipation
The Logic Cell Array exhibits the low power consumption
characteristic of CMOS ICs. Only quiescent power is
required for the LCA configured for CMOS input levels.
The TTL input level configuration option requires additional power for level shifting. The power required by the
static memory cells which hold the configuration data is
very low and may be maintained in a power-down mode.
Typically most of power dissipation is produced by capacitive loads on the output buffers, since the power per output
is 25 ~W I pF I MHz. Another component of 1/0 power is
the DC loading on each output pin. For any given system,
the user can calculate the 110 power requirement based on
the sum of capacitive and reSistive loading of the devices
driven by the Logic Cell Array.
Internal power supply dissipation is a function of clock
frequency and the number of nodes changing on each
clock. In an LCA the fraction of nodes changing on a given
clock is typically low (10-20%). For example, in a 16-bit
binary counter, the average clock produces a change in
slightly less than 2 of the 16 bits. In a 4-input AND gate
there will be 2 transitions in 16 states. Typical global clock
buffer power is about 3 mW I MHz for the XC2064 and
4mW I MHz for the XC2018. With a ''typical'' load of three
general interconnect segments, each Configurable Logic
Block output requires about 0.4 mW I MHz of its output
frequency. Graphs of power versus operating frequency
are shown in Table 1.
1104 10
Figure 9. Direct Interconnect
2-64
ON-CHIP
ALTERNATE
CLOCK BUFFER
EXTERNAL
XTAll
o
o
R2
SUGGESTED COMPONENT VALUES
R1 1-4Mn
R20-1Kn
(may be required for low frequency, phase
shift andlor oompensation level for crystal OJ
~ Cl
~C2
C1,C2 10-40pF
Y1 1 -20 MHz AT cut
48 DIP
XTAL1
XTAL2
33
30
68PLCC
46
43
68PGA
J10
L10
84PLCC
56
53
84PGA
K11
L11
1104 11
Figure 10. Crystal Oscillator
GND
Vee
+- -+ -- + --+ --+- -+- -+- -+
+- -+ -- + --+- -+- -+- -+--+
+- -+ --+ --+ --+- -+--+--+,
,
+ --+ -- +- -+ --+- -+-- +-- +,
,
+ --+ -- +- -+ --+,, -+ -- +-, +,
+--+--+--+--+-,, ,, ,,
,,
+ --+- -+- -+- -+ --+ -- +-- +
r
+ -- +- -+--+ --+ -- + -- +--+
I
I
t
I
I
I
I
I
I
,
I
,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1
I
I
I
I
I
I
I
I
1
I
I
I
GROUND AND
VeeRING FOR
UODRIVERS
I
I
I
I
GND
1104 12
Figure 11. LCA Power Distribution
2-65
Vee
LOGIC POWERGRID
•
XC206412018 Logic Cell Array
PROGRAMMING
As each data bit is supplied to the LCA, it is internally
assembled into a data word. As each data word is
completely assembled, it is loaded in parallel into one word
of the internal configuration memory array. The last word
must be loaded before the current length count compare is
true. If the configuration data are in error, e.g., PROM
address lines swapped, the LCA will not be ready at the
length count and the counter will cycle through an additional complete count prior to configuration being "done".
Configuration data to define the function and interconnection within a Logic Cell Array are loaded automatically
at power-up or upon command. Several methods of
automatically loading the required data are designed into
the Logic Cell Array and are determined by logic levels
applied to mode selection pins at configuration time. The
form of the data may be either serial or parallel, depending
on the configuration mode. The programming data are
independent of the configuration mode selected. The
state diagram of Figure 12 illustrates the configuration
process.
Figure 14 shows the selection of the configuration mode
based on the state of the mode pins MO and MI. These
package pins are sampled priorto the start of the configuration process to determine the mode to be used. Once
configuration is DONE and subsequent operation has
begun, the mode pins may be used to perform data
readback, as discussed later. An additional mode pin, M2,
must be defined althe start of configuration. This package
pin is a user-configurable 1/0 after configuration is complete.
Input thresholds for user 1/0 pins can be selected to be
either TTL-compatible or CMOS-compatible. At powerup, all inputs are TTL-compatible and remain in that state
until the LCA begins operation. If the user has selected
CMOS compatibility, the input thresholds are changed to
CMOS levels during configuration.
Initialization Phase
Figure 13 shows the specific data arrangement for the
XC2064 device. Future products will use the same data
format to maintain compatibility between different devices
of the Xilinx product line, but they will have different sizes
and numbers of data frames. For the XC2064, configuration requires 12,038 bits for each device. Forthe XC2018,
the configuration of each device requires 17,878 bits. The
XC2064 uses 160 configuration data frames and the
XC2018 uses 197.
When power is applied, an internal power-on-reset circuit
is triggered. When Vcc reaches the voltage at which the
LCA begins to operate (2.5 to 3 Volts), the chip is initialized, outputs are made high-impedance and a time-out is
initiated to allow time for power to stabilize. This time-out
(15 to 35 ms) is determined by a counter driven by a selfgenerated, internal sampling clock that drives the configuration clock (CCLK) in master configuration mode. This
internal sampling clock will vary with process, temperature
and power supply over the range of 0.5 to 1.5 MHz. LCAs
with mode lines set for master mode will time-out of their
initialization using a longer counter (60 to 140 ms) to
assure that all devices, which it may be driving in a daisy
chain, will be ready. Configuration using peripheral or
The configuration bit stream begins with preamble bits, a
preamble code and a length count. The length count is
loaded into the control logic of the Logic Cell Array and is
used to determine the completion of the configuration
process. When configuration is initiated, a 24-bit length
counter is set to 0 and begins to count the total number of
configuration clock cycles applied to the device. When the
current length count equals the loaded length count, the
configuration process is complete. Two clocks before
completion, the internal logic becomes active and is reset.
On the next clock, the inputs and outputs become active as
configured and consideration should be given to avoid
configuration signal contention. (Attention must be paid to
1104 13
MODE PIN
MODE SELECTED
avoid contention on pins which are used as inputs during
configuration and become outputs in operation.) On the
last configuration clock, the completion of configuration is
signalled by the release of the DONE I PROG pin of the
device as the device begins operation. This open-drain
output can be AN D-tied with multiple Logic Cell Arrays and
used as an active-high READY or active-low, RESET, to
other portions of the system. High during configuration
(HOC) and low during configuration (LDC), are released
one CCLK cycle before DONE is asserted. In master
mode configurations, it is convenient to use LDC as an
active-low EPROM chip enable.
MO
Ml
M2
0
0
0
MASTER SERIAL
0
0
1
MASTER LOW MODE
0
1
1
MASTER HIGH MODE
1
0
1
PERIPHERAL MODE
1
1
1
SLAVE MODE
MASTER lOW ADDRESSES BEGIN AT 0000 AND INCREMENT
MASTER HIGH ADDRESSES BEGIN AT FFFF AND DECREMENT
Figure 14. Configuration Mode Selection
2-66
E:XIUNX
zation will require about 160 additional cycles of the internal sampling clock (197 for the XC2018) to clear the
internal memory before another configuration may begin.
Reprogramming is initialized by a HIGH-to-LOW transition
on RESET (after RESET has been HIGH for at least 6 ns)
followed by a LOW level (for at least 6 ns) on both the
RESET and the open drain DONE/PROG pins. This returns the LCA to the CLEAR state, as shown in Fig. 12.
slave modes must be delayed long enough for this initialization to be completed.
The initialization phase may be extended by asserting the
active-low external RESET. If a configuration has begun,
an assertion of RESET will initiate an abort, including an
orderly clearing of partially loaded configuration memory
bits. After about 3 clock cycles for synchronization, initiali-
POWER·ON DELAY IS
214 CYCLES FOR NON-MASTER MODE-1 1 TO 33 mS
216 CYCLES FOR MASTER MODE-43 TO 130 mS
USER 110 PINS WITH HI<;iH IMPEDANCE PULL·UP
HDC= HIGH
LDC=LOW
LOW ON DONEIPROGRAM AND RESET
CLEAR IS
-160 CYCLES FOR THE XC2064-100 TO 320 liS
-200 CYCLES FOR THE XC2016-125 TO 390 liS
1104 14
Figure 12. A State Diagram of tile Configuration Process for Power-up and Re-program
11111111
0010
< 24-BIT LENGTH COUNT >
1111
o < DATA FRAME # 001 >
o < DATA FRAME # 002 >
o
DUMMY BITS (4 BITS MINIMUM), XACT 2.10 GENERATES 8 BJTS
PREAMBLE CODE
CONFIGURATION PROGRAM LENGTH
DUMMY BITS (4 BITS MINIMUM)
111
111
111
CONFIGURATION
FRAMES
DATA BITS
PER FRAME
XC2018
XC2064
196
160
87
71
o < DATA FRAME # 159>
o
111
111
1111
HEADER
PROGRAM DATA
REPEATED FOR EACH LOGIC
CELL ARRAY IN A DAISY CHAIN
POSTAMBLE CODE (4 BITS MINIMUM)
START-UP REQUIRES THREE CONFIGURATION CLOCKS BEYOND LENGTH COUNT
1104 15
Figure 13. XC2064 Internal Configuration Data Arrangement
2-67
XC206412018 Logic Cell Array
Master Mode
least significant bit of each byte, normally DO, is the next bit
in the serial stream.
In master mode, the Logic Cell Array automatically loads
the configuration program from an external memory device. Figure 15a shows an example of the master mode
connections required. The Logic Cell Array provides
sixteen address outputs and the control signals RCLK
(read clock), HOC (high during configuration) and LOC
(low during configuration) to execute read cycles from the
external memory. Parallel eight-bit data words are read
and internally serialized. As each data word is read, the
°
Addresses supplied by the Logic Cell Array can be selected by the mode lines to begin at address
and
incremented to read the memory (master low mode), or
they can begin at address FFFF Hex and be decremented
(master high mode). This capability is provided to allowthe
Logic Cell Array to share external memory with another
device, such as a microprocessor. For example, if the
processor begins its execution from low memory, the Logic
USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT FROM
ALTERNATIVE CONFIGURATIONS
.--1--------.--- +5V
5i---( RESET
Vpp
Vee
DATA
SERIAL
MEMORY
CLK
DIN
CCLK
CE
LDC
DONE-
-
CEO
XC1736
DIP
r---·----------.... --;
~
~
rOE
'"v
CASCADED
SERIAL
MEMORY
:L .. _________________ .J
(HIGH RESETS THE XC1736 ADDRESS POINTER)
_====='
CCLK~
(00::
(OUTPUT)
1104 17
_
-------'- _ *
* FOR OPTIONAL SLAVE MODE LCAs IN A DAISY CHAIN
Figure 15b. Master Serial Mode. The one time programmable XC1736 Serial Configuration PROM
supports automatic loading of configuration programs up to 36K bits. Multiple XC1736s can be cascaded to
support additional LCAs. An XC2000 LOC signal can provide an XC1736 inhibit as the user lias become active.
2-69
XC206412018 Logic Cell Array
same fashion with the next word, etc. After the configu ration program has been loaded, an additional three clocks
(a total of three more than the length count) must be
supplied in order to complete the configuration process.
When more than one device is being used in the system,
each device can be assigned a different bit in the processor data bus, and multiple devices can be loaded on each
processor write cycle. This "broadside" loading method
provides a very easy and time-efficient method of loading
several devices.
supplied by the lead device, which is configured in master
or peripheral mode. After the configuration program has
been loaded, an additional three clocks (a total of three
more than the length count) must be supplied in order to
complete the configuration process.
Daisy Chain
The daisy-chain programming mode is supported by Logic
Cell Arrays in all programming modes. In master mode
and peripheral mode, the LCA can act as a source of data
and control for slave devices. For example, Figure 18
shows a single device in master mode, with 2 devices in
slave mode. The master mode device reads the external
memory and begins the configuration loading process for
all of the devices.
Slave Mode
Slave mode, Figure 17, provides the simplest interface for
loading the Logic Cell Array configuration. Data is supplied in conjunction with a synchronizing clock. For each
LOW-to-HIGH input transition of configuration clock
(CCLK), the data present on the data input (DIN) pin is
loaded into the internal shift register. Data may be supplied by a processor or by other special circuits. Slave
mode is used for downstream devices in a daisy-chain
configuration. The data for each slave LCA are supplied
by the preceding LCA in the chain, and the clock is
ADDRESS
BUS
DATA
BUS
The data begin with a preamble and a length count which
are supplied to all devices at the beginning of the configuration. The length count represents the total number of
cycles required to load all of the devices in the daisy chain.
After loading the length count, the lead device will load its
configuration data while providing a HIGH DOUTto down-
+5V
+5V
5kn
DO
DIN
10WRT
CCLK
*
DOUT
*
WRT
M2
ADDRESS
DECODE
LOGIC
CSO
HDC
LDC
,~
OTHER
CS1
1
GENERAL·
PURPOSE
USER 1/0
1/0 PINS
CS2
DONE
RESET
CS2
CCLK
(OUTPUT)
DIN
DIP
RESET
-':....t....I..~1...L..J1
-----t----.
-----il===~L----l:===
_____
~uw---~~----~---
DOUT-----~~'r--------~-.
(OUTPUT) _ _ _ _ _ _ _ _, ,_ _ _ _ _ _ _ _ _ _- - '
* FOR OPTIONAL SLAVE MODE LCAs IN A DAISY CHAIN
Figure 16. XC2000 Peripheral Mode. Configuration data are loaded using serialized data from a microprocessor.
2-70
1104 18
stream devices. When the lead device has been loaded
and the current length count has not reached the full value,
memory access continues. Data bytes are read and
serialized by the lead device. The data are passed through
the lead device and appear on the data out (DOUT) pin in
serial form. The lead device also generates the configuration clock (CCLK)to synchronize the serial output data. A
master mode device generates an internal CCLK of
8 times the EPROM address rate, while a peripheral mode
device produces CCLK from the chip select and write
strobe timing.
connected to the internal circuitry.
SPECIAL CONFIGURATION FUNCTIONS
In addition to the normal user logic functions and interconnect, the configuration data include control for several
special functions:
•
•
•
•
Input thresholds
Readback enable
Reprogram
DONE pull-up resistor
Operation
Each of these functions is controlled by a portion of the
configuration program generated by the XACT Development System.
When all of the devices have been loaded and the length
count is complete, a synchronous start-up of operation is
performed. Onthe clock cycle following the end of loading,
the intemallogic begins functioning in the reset state. On
the next CCLK, the configured output buffers become
active to allow signals to stabilize. The next CCLK cycle
produces the DONE condition. The length count control of
operation allows a system of multiple Logic Cell Arrays to
begin operation in a synchronized fashion. If the crystal
oscillator is used, it will begin operation before configuration is complete to allow time for stabilization before it is
Input Thresholds
During configuration, all input thresholds are TTL level.
During configuration input thresholds are established as
specified, either TTL or CMOS. The PWRDWN input
threshold is an exception; it is always a CMOS level input.
The TTL threshold option requires additional power for
threshold shifting.
+5V
5kQ
MICRO
COMPUTER
CCLK
STRB
DIN
DO
*
-*
HDC
D1
1/0
LDC
D2
PORT
M2
DOUT
D3
GENERALPURPOSE
USER 1/0
LCA
D4
OTHER {
D5
1/0 PINS
DIP
D6
D7
RESET
RESET
DIN
CCLK
DOUT
(OUTPUT)
1104 19
==xI;
BITN
~
~
BITN +1
h
BITN-1
~
I
BITN
*FOR OPTIONAL SLAVE MODE LCAs IN A DAISY CHAIN
Figure 17. Slave Mode. Bit-serial configuration data are read at rising edge of the CCLK. Data on DOUT are
provided on the falling edge of CCLK. Identically configured non-master mode LCAs can be configured in parallel
by connecting DINs and CCLKs.
2-71
XC2064/2018 Logic Cell Array
guarantees that the LCA will return to the Clear state.
Either of these methods may be needed in the event of an
incomplete voltage interruption. They are not needed for a
normal application of power from an off condition.
Readback
After a Logic Cell Array has been programmed, the configuration program may be read back from the device.
Readback may be used for verification of configuration,
and as a method of determining the state of internal logic
nodes during debugging. Three readback options are
provided: on command, only once, and never.
DONE Pull-up
The DONE I PROG pin is an open drain 1/0 that indicates
programming status. As an input, it initiates a reprogram
operation. An optional internal pull-up resistor may be
enabled.
An initiation of read back is produced by a LOW-to-HIGH
transition of the MO I RTRIG (read trigger) pin. Once the
readback cornmand has been given, CCLK is cycled to
read back each data bit in aformat similar to loading. After
two dummy bits, the first data frame is shifted out, in
inverted sense, on the M1 I RDATA (read data) pin. All
data frames must be read back to complete the process
and return the mode select and CCLK pins to their normal
functions. Read back data includes the state of all internal
storage elements. This information is used by the Logic
Cell Array development system In-Circuit Debugger to
provide visibility into the internal operation of the logic
while the system is operating. To read back a uniform time
sample of all storage elements, it may be necessary to
inhibit the system clock.
Battery Backup
Because the control store of the Logic Cell Array is a
CMOS static memory, its cells require only a very low
standby current for data retention. In some systems, this
low data retention current characteristic facilitates preserving configurations in the event of a primary power loss.
The LogiC Cell Array has built in power-down logic which,
when activated, will disable normal operation of the device
and retain only the configuration data. All internal operation is suspended and all o\Jtput buffers are placed in their
high impedance state.
Power-down data retention is possible with a simple battery-backup circuit because the power requirement is
extremely low. For retention at 2.0 volts, the required
current is typically on the order of 50 nanoamps. Screening to this parameter is available. To force the Logic Cell
Array into the power-down state, the user must pull the
PWRDWN pin LOW and continue to supply a retention
voltage to the Vcc pins of the package. When normal
power is restored, Vcc is elevated to its normal operating
voltage and PWRDWN is returned to a HIGH. The Logic
Cell Array resumes operation with the same internal sequence that occurs at the conclusion of configuration.
Internal 1/0 and logic block storage elements will be reset,
the outputs will become enabled and then the
DONEIPROG pin will be released. No configuration
programming is involved.
Re-program
The Logic Cell Array configuration memory may be rewritten while the device is operating in the user's system.
The LCA returns to the Clear state where the configuration
memory is cleared, 1/0 pins disabled, and mode lines resampled. Re-program control is often implemented using
an external open collector driver which pulls DONE/PROG
LOW. Once it recognizes a stable request, the Logic Cell
Array will hold DONE/PROG LOW until the new configuration has been completed. Even if the DONE/PROG pin is
externally held LOW beyond the configuration period, the
Logic Cell Array will begin operation upon completion of
configuration. To reduce sensitivity to noise, these reprogram signals are filtered for 2-3 cycles of the LCA's
internal timing generator (2 to 6I1S). Note that the Clear
time out for a Master mode re-program or abort does not
have the 4 times delay of the Initialization state. If a daisy
chain is used, an external RESET is required, long enough
to guarantee clearing all non-master mode devices. For
XC2000 series LCAs this is accomplished with an external
time delay.
PERFORMANCE
The high performance of the Logic Cell Array results from
its patented architectural features and from the use of an
advanced high-speed CMOS manufacturing process.
Performance may be measured in terms of minimum
propagation times for logic elements.
In some applications the system power supply might have
momentary failures which can leave the LCA's control
logic in an invalid state. There are two metods to recover
from this state. The first is to cycle the Vcc supply to less
than 0.1 Volt and reapply valid Vcc. The second is to
provide the LCAwith simultaneous LOW levels of at least
611S on RESET and DONE/PROG pins after the RESET
pin has been HIGH following a return to valid Vcc. This
Flip-flop loop delays for the 1/0 block and logic block flipflops are about 3 nanoseconds. This short delay provides
very good performance under asynchronous clock and
data conditions. Short loop delays minimize the probability
2-72
I
~
II
r
GENERAL·
PURPOSE
USERVO
PNS
-
I\)
23
M2
I--
HDC
A14
A14
LDC
~
A13
A13
I-EPROM
A10
LCA
MASTER
A9
Ala
AS
~
AS
AS
--<
A7
A7
D7
AS
De
v-----
fr
r<
AS
A5
05
03
A4
A4
D4
02
AS
AS
D3
01
A2
A2
02,
00
Al
Al
01
AD
AD
LOC
O/P
RESET
L
OTHER{
VOPINS
GENERAL·
PURPOSE
USERVO
cc-
-
DIP
DIP
-< RESET
RESET
r-r-r-,
04
f-
LOC """"
I--
AS
rr-
GENERAL·
PURPOSE
USERVO
OTHER {
VOPINS
A12
All
r - - D5
,--
LCA
SLAVEiIn
HOC
_ .... --:-
r - - De
,--
...
A15
A15
All
07
DOUT
M2
A12
OTHER
I/O PINS
5k!l
CCLK
DIN
I-
HDC
-< RCLK
,--
"
LCA
SLAVE'l
M2
-
5k!l
DOUT
DIN
!
MO Ml PWRDWN
' - - CCLK
CCLK-
-
II
MO Ml PWRDWN
DOUT
-
1
I I 1
Ma Ml PWRDWN
5k!l
-
+5V
+~v
NOTE: RESET OF AI ASTER DEVICE
SHOULD BE ASSERT o BY AN EXTERNAL
TIMING CIRCUIT TO , ,LLOW FOR LeA CCLK
VARIATIONS IN CLEI R STATE TIME.
,
,
00,
DE
r-----"+5V
CE
5k!l
B
OPEN
..... COUECTOR
...
REPROGRAM
~
SYSTEM RESET
---
I
.
"
"
Figure 18. Master Mode with Daisy Chain
M
1104 20
Any XC3000 slave driven by an XC2000 master mode device must use "early DONE and early internal reset".
(The XC2000 master will not supply the extra clock required by a "late" programmed XC3000.)
•
XC2064/2018 Logic Cell Array
of a metastable condition which can result from assertion
of the clock during data transitions. Because of the short
loop delay characteristic in the Logic Cell Array, the 1/0
block flip-flops can be used very effectively to synchronize
external signals applied to the device. Once synchronized
in the 1/0 block, the signals can be used internally without
further consideration of their clock relative timing, except
as it applies to the internal logic and routing path delays.
Logic Block Performance
Logic block propagation times are measured from the
interconnect point at the input of the combinatorial logic to
the output of the block in the interconnect area. Combinatorial performance is independent of logic function
because of the table look-up based implementation.
Timing is different when the combinatorial logic is used in
conjunction with the storage element. Forthe combinatorial logic function driving the data input of the storage
element, the critical timing is data set-up relative to the
clock edge provided to the storage element. The delay
from the clock source to the output of the logic block is
critical in the timing of signals produced by storage elements, The loading on a logic block output is limited only
by the additional propagation delay of the interconnect
network. Performance of the logic block is a function of
supply voltage and temperature, as shown in Figures 22
and 23.
Device Performance
The single parameter which most accurately describes the
overall performance of the Logic Cell Array is the maximum toggle rate for a logic block storage element configured as a toggle flip-flop. The configuration for determining the toggle performance of the Logic Cell Array is shown
in Figure 19. The clock forthe storage element is provided
by the global clock buffer and the flip-flop output Q is fed
back through the combinatorial logic to form the data input
forthe next clock edge. Using this arrangement, flip-flops
in the Logic Cell Array can be toggled at clock rates from
33-70 MHz, depending on the speed grade used.
Interconnect Performance
Interconnect performance depends on the routing resource used to implement the signal path. As discussed
earlier, direct interconnect from block to block provides a
minimum delay path for a signal.
Actual Logic Cell Array performance is determined by the
critical path speed, including both the speed of the logic
and storage elements in that path, and the speed of tM
particular network routing. Figure 20 shows a typical
system logic configuration of two flip-flops with an extra
combinatorial level between them. Depending on speed
grade, system clock rates to 35 MHz are practical for this
logic. To allow the user to make the best use of the
capabilities of the device, the delay calculator in the XACT
Development System determines worst-case path delays
using actual impedance and loading information.
D
K
Q
The single metal segment used for long lines exhibits low
resistance from end to end, but relatively high capacitance. Signals driven through a programmable switch
will have the additional impedance of the switch added to
their normal drive impedance.
General-purpose interconnect performance depends on
the number of switches and segments used, the pre-sence
of the bidirectional repowering buffers and the overall
loading on the signal path at all pOints along the path. In
calculating the worst-case delay for a general interconnect
path, the delay calculator portion of the XACT development system accounts for all of these elements. As an
approximation, interconnect delay is proportional to the
summation of totals of local metal segments beyond each
programmable switch. In effect, the delay is a sum of
R-C delays each approximated by an R times the total C
it drives. The R of the switch and the C of the interconnect
are functions of the particular device performance grade.
For a string of three local interconnects, the approximate
delay at the first segment, after the first switch resistance,
would be three units; an additional two delay units afterthe
next switch plus an additional delay after the last switch in
the chain. The interconnect R-C chain terminates at each
repowering buffer. Nearly all of the capacitance is in the
interconnect metal and switches; the capacitance of the
block inputs is not significant. Figure 21 shows an estimation of this delay.
f--+--i:-- x, Y
-'::~-------I
1104 21
Figure 19. Logic Block Configuration for
Toggle Rate Measurement
2-74
COMBINATORIAL CLB
......................................................
,.,.,.,...,.,....•.CLB
,.,...,...,.,.".,.,',.,.,.".".,,1:NPUTS
"......... . ...SOURCE
DESTINATION CLB
~GENERAL/ =
Q
INPUTS
1
=E-
,.
:--
Q
INTERCONNECT!:
GLOBAL
CLOCK
GLOBAL
CLOCK
J:.-____---'
II
1104 22
Figure 20. Typical Logic Path
r-,
r-,
L_~
L_~
rr------~~------~4-----~~------4--+~ ~_+~----~
REPOWERING
BUFFER
CLB
r ,
I
I
L_~
R1
C1
DELAY:
INCREMENTAL
IF R,=R 2 =R3 =R AND C,=C 2=C 3 =C
THEN CUMULATIVE DELAY
3RC
SRC
6RC
1104 23
Figure 21. Interconnection Delay Factors Example
2-75
6RC + BUFFER
~
XC2064f2018 Logic Cell Array
1.3
1.2
0
§
..J
<
::;
1.1
1.0
a: 0.9
0
~
0.8
S
w
c
0.7
0.6
0.5
-55-40
o
30
TEMPERATURE
70 85
125
r C)
NOTE: NORMALIZED FOR 3O'C
1104 25
Figure 22. Delay
vs. Temperature
1.2
5"
llJ
N
1.1
::::;
<
::i!
0:
~
1.0
>-
S
llJ
0
0.9
4
4.5
5.0
5.5
6.0
Vee
1104 26
Figure 23. Delay
vs. Power Supply Voltage
2-76
I:XILINX
100
90
80
/
70
60
/
50
/
100
0
/
0
5
~
/
V
/
/
/
/
2
V
/
GLOBAL CLOCK
BUFFER
/
1 110 OUTPUT
(50pF)0.5
0.5
/
/
/
/
/
~/
1
/
/
/
/
/
V
/
/
/
/
6
5
/
V
/
/
/
4
V
3
2
/
.9
.8
..
.7
.6
/
.5
.4
V
V
/
.3
V
.2
.1
2
4
5
10
20
FREQUENCY MHz
(0.4 mWIMHz) /
1 CLBOUTPUT
3 LOCAL
INTERCONNECT
1104 'Zl
Table 1. Typical LCA Power Consumptl.on By Element
2-77
III
10
9
8
/
/
V
V
V
/
/
/
3
/
/
/
/
/
V
V
/
/
30
20
/
/
/
V
/
/
/
20
(1.25 mWIMHz)
V
/
0
1
/
/
/
L
(mW)
(3mWIMHz)
/
/
/
/
1/
40
20 CLB OUTPUTS
3 LOCAL SEGMENTS
EACH
40
/
150
30
40
50
(rnA)
XC206412018 Logie Cell Array
DEVELOPMENT SYSTEMS
Design verification may be accomplished by using the
XILINX XACTOR In-Circuit Design Verifier directly in the
target system and/or the P-SILOS logic simulator.
To accomplish hardware development support for the
Logic Cell Array, Xilinx provides a development system
with several options to support added capabilities. The
XACT system provides the following:
•
•
•
•
•
PIN DESCRIPTIONS
1. Permanently Dedicated Pins.
Schematic entry
Automatic place and route
Interactive design editing for optimization
Interactive timing calculations
Macro library support, both for standard Xilinx
supplied functions and user defined functions
Vee
One or two (depending on package type) connections to
the nominal +5 V supply voltage. All must be connected.
GND
One or two (depending on package type) connections to
ground. All must be connected.
• Design entry checking for consistency and
completeness
• Automatic design documentation generation
• PROM programmer format output capabilities
• Simulation interface support including automatic
netlist (circuit description) and timing extraction
PWRDWN
A LOW on this CMOS compatible input stops all internal
activity to minimize Vcc power and puts all output buffers
in a high impedance state, but Configuration is retained.
When the PWRDWN pin returns HIGH the device returns
to operation with the same sequence of buffer enable and
DONE/PROGRAM as at the completion of configuration.
All internal storage elements are reset. If not used,
PWRDWN must be tied to Vcc.
• Logic and timing simulation
• In-circuit design verification for multiple devices
The host system on which the XACTsystem operates is an
IBM PC/ATorcompatible system with DOS 3.0{)r higher.
The system requires 640K bytes of internal RAM, 1.5 to 5.5
Mbyte of Extended Memory, color graphics and a mouse.
A complete system requires one parallel I/O port and two
serial ports for the mouse and in-circuit emulation.
RESET
This is an active low input which has three functons.
Priorto the start of configuration, a LOWinputwili delay the
start of the configuration process. An internal circuit
senses the application of power and begins a minimal
time-out cycle. When the time-out and RESET are complete, the levels of the "M" lines are sampled and configuration begins.
Designing with the XACT Development System
Designing with the Logic Cell Array is similar to using
conventional MSI elements or gate array cells. A range of
supported packages, including FutureNet and Schema,
provide schematic capture with elements from a macro
library. The XACT development system then translates
the schematic description into partitioned Logic Blocks
and I/O Blocks, based on shared input variables or efficient
use of flip-flop and combinatorial logic. Design entry can
also be implemented directly with the XACT development
system using an interactive graphic design editor. The
design information includes both the functional specifications for each block and a definition of the interconnection
networks. Automatic placement and routing is available
for either method of design entry. After routing the interconnections, various checking stages and processing of
that data are performed to insure that the design is correct.
Design changes may be implemented in minutes. The
design file is used to generate the programming data
which can be down loaded directly into an LCA in the user's
target system and operated. The program information
maybe usedto program PROM, EPROM or ROM devices,
or stored in some other media as needed by the final
system.
If RESET is asserted during a configuration, the LCA is reinitialized and will restart the configuration at the termination of RESET.
If RESET is asserted after configuration is complete, it will
provide an asynchronous reset of all lOB and CLB storage
elements of the LCA.
RESET can also be used to recover from partial power
failure. See section on Re-program under "Special Configuration Functions."
CCLK
During configuration, Configuration Clock is an output of
an LCAin Master mode or Peripheral mode. LCAs in Slave
mode use it as a clock input. During a Readback operation
it is a clock input for the configuration data being shifted
out.
2-78
DONE
The DONE output is configurable as open drain with or
without an internal pull~up resistor. At the completion of
configuration, the circuitry of the LCA becomes active in a
synchronous order, and DONE may be programmed to
occur one cycle before or after that.
PROG
Once configuration is done, a HIGH to LOW transition of
this pin will cause an initialization of the LCA and start a
reconfiguration.
MO
As Mode 0, this input and M1, M2 are sampled before the
start of configuration to establish the configuration mode to
be used.
RTRIG
As a Read Trigger, a LOW-to-HIGH input transition, after
configuration is complete, will initiate a Readback of configuration and storage element data by CCLK. This operation may be limited to a single request, or be inhibited altogether, by selecting the appropriate read back option
when generating the bit stream.
M1
As Mode 1, this input and MO, M2 are sampled before the
start of configurationto establish the configuration modeto
be used. If Read back is to be used, a 5 kQ resistor should
be used to define mode level inputs.
RDATA
As an active low Read Data, after configuration is complete, this pin is the output of the readback data.
2. User I/O Pins that can have special functions.
M2
As Mode 2, this input has a passive pullup during configuration. Together with MO and M1 it is sampled before the
start of configuration to establish the configuration mode to
be used. After configuration this pin becomes a user programmable I/O pin.
HDC
High During Configuration is held at a HIGH level by the
LCA until after configuration. It is available as a control
output indicating that configuration is not yet completed.
After configuration this pin is a user I/O pin.
LDC
Low During Configuration is held at a LOW level by the
LCA until after configuration. It is available as a control
output indicating that configuration is not yet completed. It
is particularly useful in Master mode as a LOW enable for
an EPROM. After configuration this pin is a user I/O pin.
If used as a LOW EPROM enable, it must be programmed
as a HIGH after configuration.
XTL1
This user I/O pin can be used to operate as the output of
an amplifier driving an external crystal and bias circuitry.
XTL2
This user I/O pin can be used as the input of an amplifier
connected to an external crystal and bias circuitry. The
I/O Block is left unconfigured. The oscillator configuration
is activated by routing a net from the oscillator buffer
symbol output and by the MAKEBITS program.
CSO,CS1,CS2,WRT
These four inputs represent a set of signals, three active
low and one active high, which are used in the peripheral
mode to control configuration data entry. The assertion of
all four generates a LOW CCLK. In master mode, these
pins become part of the parallel configuration byte
(D4,D3,D2,D1). After configuration is complete, they are
user-programmed I/O.
RCLK
During Master parallel mode configuration RCLK represents a "read" of an external dynamic memory device
(normally not used).
DO-D7
This set of 8 pins represent the parallel configuration byte
for the parallel Master mode. After configuration is complete they are user programmed I/O pin.
AO-A15
This set of 16 pins present an address output for a
configuration EPROM during Master parallel mode. After
configuration is complete they are user programmed 110
pin.
DIN
°
This user I/O pin is used as serial Data input during Slave
or Master Serial configuration. This pin is Data input in
Master or Peripheral configuration mode.
DOUT
This user I/O pin is used during configuration to output
serial configuration data for daisy-chained slaves' Data In.
3. Unrestricted User I/O Pins.
I/O
A pin which may be programmed by the user to be Input
and/or Output pin following configuration. Some of these
pins present a high impedance pull-up (see next page) or
perform other functions before configuration is complete
(see above).
2-79
•
XC2064/2018 Logic Cell Array
CONFIGURATION MODE:
~r,~';.
,
PE~\~~~~l
I ,.- .
...
~~.
LDC
I/O
.OW
K4
•
it
«HIGH»
*
I/O
K8
D6
...
:.~
~
110~
. .........:..!:e.
.~
OS21~
~
37
.J:!
E10
I/O
C10
)11
qO)
Llli't~.
~
-""A
62
\10
I/O
«HIGH» IS HIGH IMPEDANCE WITH A 20-50 KO INTERNAL PULL-UP DURING CONFIGURATION
1104 28
Table 2a. XC2064 Pin Assignments
A PLCC in a "PGA-Footprint" socket has a different signal pinout than a PGA device.
2-80
I
M~~~~O~ER
I
~y,~;
'MODE,
I PE~:~~~~AL I MAS<~~,~~'GH I M~~~~:OW
A1:
;;HiG'<~~
A1:
IpLCC
"!!!!!'
~
II}
I A6
I A5
4
5
•
"4
, B4
'"
9
10
12
I Al
I B2
l'WImWII
14
15
i»,
,~<
OPERATION
3
IO}
IO}
10}
USER
Ip~6c I :~A
,.
02
01
, E3
20
21
I El
I F2
20
25
2.
I G2
I Fl
I Hl
24
25
3{)
I Kl
I J2
2.
29
30
34
35
,36
~~H}GH>~,
'"
"~I!
'Ml .oW
MO HIGH
MO LOW
""I
, «HIGH»
LOC (LOW)
31
=i~)
I K3
L2
L3
1,0
~~~'
I»
33
34
40
41
36
44
45
I"
L5
,,«HIGH»,
1,0
49
39
40 150
41 1 51
KB
LO
Ll0
'Ill
4315:
44
54
0)
45.
Lll
(10
,Jl0
49
!Hl
'10
51
G9
~>
~
1,0
I
'"~I,
rllh'
~;
55 I 6.
I 69
~~~"
59
60
DC
LK
CCLJ«O)
A2
AS
73
1,0
:10
I
63
64
\10
AO
.~~~I~B~;
1,0
! .2
«HIGH» IS HIGH IMPEDANCE WITH A 20-50 Kn INTERNAL PULl·UP DURING CONFIGURATJON
1104 29
Table 2b, XC2018 Pin Assignments
2-81
XC206412018 Logic Cell Array
PARAMETRICS
Absolute Maximum Ratings
Units
Vee
Supply voltage relative to GN D
-0.5 to 7.0
V
VIN
Input voltage with respect to GND
-0.5 to Vee + 0.5
V
VTS
Voltage applied to three-state output
-0.5 to Vee + 0.5
V
TSTG
Storage temperature (ambient)
-65 to +150
°C
TSOL
Maximum soldering temperature (10 sec @ 1/16 in.)
+260
°C
'Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only. and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure
to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operating Conditions
Vee
Supply voltage relative to GN D
Commercial
Supply voltage relative to GND
Industrial
Supply voltage relative to GN D
Military
Min
Max
Units
4.75
5.25
V
-40°C to 85°C
4.5
5.5
V
-55°C to 125°C
4.5
5.5
V
Vee
V
0.8
V
.7 Vee
Vee
V
0
.2 Vee
V
DoC to 70°C
VIHT
High-level input voltage -
TTL configuration
2.0
VILT
Low-level input voltage -
TTL configuration
0
VI He
High-level input voltage -
CMOS configuration
VILe
Low-level input voltage -
CMOS configuration
2-82
Electrical Characteristics Over Operating Conditions
= -4.0 ma Vee min)
VOH
High-level output voltage (@ IOH
VOL
Low-level output voltage (@ IOL
VOH
High-level output voltage (@ IOH
VOL
Low-level output voltage (@ IOL
= 4.0 ma Vee)
VOH
High-level output voltage (@IOH
= -4.0 ma Vee)
VOL
LOW-level output voltage (@ IOH
= 4.0 ma Vee)
leeo
Quiescent operating power supply current
Min
Commercial
3.86
= 4.0 ma Vee min)
= -4.0 ma Vee)
Max
V
0.32
Industrial
3.76
V
V
0.37
Military
Units
V
V
3.7
0.4
V
CMOS thresholds (@ Vee Max)
5
mA
TTL thresholds (@ Vee Max)
10
mA
0.5
mA
= 5.0 V)
leePD
Power-down supply current (@ Vee
IlL
Leakage Current Commercial/Industrial Temperature
-10
+10
~
Leakage Current Military -55°C to 125°C
-100
+100
~
10
pF
CIN
Input capacitance (sample tested)
2-83
III
XC2064120HI Logic Cell Array
CLB SWITCHING CHARACTERISTICS
x
INPUT (A,B,C,D)
x
--0 TllO~
OUTPUT (X,V)
(COMBINATORIAL)
CD
XX
TITO
OUTPUT (X ,V)
(TRANSPARENT LATCH)
--0
TICK
--0
Tlcc
xXI
o
TCKI4
CLOCK(K)
CLOCK (C)
-0
CD
Tccl -
7
TICI
CLOCK (G)
(DTCII -
!+-- G)
TCKO--to
@
Tcco--to
@TCIO-
XX
OUTPUT (VIA FF)
tI
SET/RESET DIRECT (A,D)
-k
SET/RESET DIRECT (F,G)
fr.=:-@
_ _..J
CLOCK (ANY SOURCE)
_
TCH
@
TRIO
@
TRlO
@
TCl
=-1----1104 30
2-84
ClB SWITCHING GUIDELINES (Continued)
Speed Grade
Description
Logic Input
to Output
Symbol
-50
-33
Min
-70
Min
-100
Max
Max
Min Max
Min Max
TllO
TITO
20
25
15
20
10
14
7.5
10
ns
ns
ToLO
13
8
6
6
ns
7
6
0
ns
ns
ns
9
5
0
ns
ns
ns
Combinatorial
Transparent latch
Additional for Q
through F or G to out
1
2
To output
Logic-input setup
Logic-input hold
9
3
4
TCKO
TICK
TCKI
12
0
To output
Logic-input setup
Logic-input hold
10
5
6
Tcco
Tlcc
Tcci
12
6
Logic Input
to G Clock
To output
Logic-input setup
LogiC-input hold
11
7
8
TClo
Tici
TCII
6
9
Set/Reset direct
Input A or D to out
12
Through F or G to out
13
Master Reset pin to out
Separation of set/reset
Set/Reset pulse-width
TRIO
TRlo
TMRO
TRs
TRPW
17
12
9
9
7
7
5"
5"
Flip-flop Toggle
rate
Q through F to flip-flop
FClK
33
50
70
100"
Clock
Clock High
Clock Low
TCH
TCl
12
12
8
8
7
7
6
6
K Clock
CClock
Notes:
14
15
Units
20
15
25
10
7
0
8
0
19
9
0
37
13
6
0
27
4
5
20
22
28
25
25
37
35
13
ns
ns
ns
10
14
17
ns
ns
ns
ns
ns
2
3
3
4
16
21
20
MHz
ns
ns
1. All switching characteristics apply to all valid combinations of process, temperature and supply with a
nominal chip power dissipation of 250 mW.
" These parameters are for clock pulses generated within a CLB. For an externally generated pulse, derate
these paramenters by 20%.
2-85
•
XC2064/2018 Logic Cell Array
108 SWITCHING CHARACTERISTIC GUIDELINES
PAD
(PACKAGE PIN)
=m
(IN)
0
X
OUTPUT SIGNAL
f4- 0TpID~
INPUT
(DIRECT)
0- TTHZ j.-
'!XX
THREE-S
-,
G)TLP
®TpL
r--
ri } T
-18 LW
L
(1/0
XX)
(OUT)
Top:/
CLOCK)
--- XX
t
®TLlr,:
INPUT
(REGISTERED)
\ \ JA = 30--35 °CIW
84-Pin PLCC Package
1
f<.-------1.10Ot.012
5QI--------->l'1
1.oo0:t.010
I-'
.100 TYP
~
L
rhffi
I"
1:'1
..L
V '-
!"
("t\ !"
'-
.100
..u.
;t
.~
'-V'-V
TVP
1
I"
1.1:
G
'-
..L
("
'1.
'-
'-
1'1'-I-' \
'-
1'-
..L
''-f-'
BL D...L ..L
.LA
DIMENSIONS ARE IN INCHES
T
!.-'050
:6~2DlA
±.010 .
~
1.000
±.O10
("
INDEX PIN
/1"
I-'
:'P \0\:08 MAX
'-
It--. r:\..
..L
1.
1.
..'- ..'-1::. "
1'l1.
'-
~
'-
\..
~
"I-' "
1
I-' '-
f-' '£.
..L
\..
1.
'-
"V
..G::::,.£, D...L
'-'
r::-.
'-J
t\
10
11
NQTE: INDEX PIN MAY OR MAY NOT BE
ELECTRICALLY CONNECTED TO PIN C2.
1104 44
84-Pin PGA Package
2-94
Military Logic CelfMArrays
XC2018B,XC3020B,XC3090B
Product Specifications
INTRODUCTION
Xilinx introduced the first field programmable gate array
(FPGA) in 1985. The development of the PGA was the
result of a number of technical breakthroughs and truly
represents the latest in advanced technology for microelectronic applications. Due to its density and the convenience of user programmability, the Logic Cell™ Array is an
important new alternative in the ASIC market. Xilinx
continues to concentrate its resources exclusively on
expanding its growing family of programmable gate arrays
and associated development systems. See the Xilinx
Programmable Gate Array Data Book for a complete
description of the architecture of both the 2000 and 3000
series arrays.
Device
XC2018B
XC3020B
XC3030B
XC3042B
XC3064B
XC3090B
1800
2000
3000
4200
6400
9000
100
64
100
144
224
320
User
II0s
74
64
80
96
120
144
74
64
80
96
120
144
COFP
COFP
COFP
COFP
COFP
100
100
100
164
164
64
80
82
120
142
Through Hole
Ceramic
User
PGA
1/0
CPGA
CPGA
CPGA
CPGA
CPGA
CPGA
84
84
84
132
132
175
74
64
74
96
110
144
The Standard Military Drawing program (SMD) is a program initiated by the Federal government to simplify the
procurement of Integrated Microcircuits (especially the
more advanced technologies) by military contractors. The
Defense Electronics Supply Center (DESC) issues the
SMD that is consistent with the Xilinx military product
specification and test conditions. DESC assigns an SMD
specification number and releases the drawing. This
drawing is then availble for use by all departments and
agencies of the Department of Defense. The Xilinx device
can then be easily procured by a military contractor by
specifying the SMD# instead of the Xilinx part number.
This eliminates the need for a separate Source Control
Drawing (SCD) and greatly reduces paperwork.
Xilinx continues its leadership in field programmable gate
arrays (FPGA) by announcing the first military qualified
FPGA's. The 2018B and the 3020B were introduced in the
first quarter of 1989. The balance olthe Xilinx 3000 series
family will be available during 1989.
Config·
urable
Logic
Blocks
XC2018
XC3020
XC3030
XC3042
XC3064
XC3090
Surface Mount
User
Ceramic
QFP
1/0
STANDARD MILITARY DRAWINGS (SMD)
MIL·STD-883 CLASS B INTRODUCED
Logic
Capacity
(usable
gates)
Device
Total
1/0
Program
Data
(bits)
DESC has assigned the Xilinx XC2018-50PG84B device
SMD# 5962-88638. SMD numbers are under development by DESC for other Xilinx devices. Contact your Xilinx
representative for more information.
17878
14779
22176
30784
46064
64160
LCA IDEAL FOR MILITARY APPLICATIONS
Field programmable gate arrays are taking market share
from mask gate arrays in the commercial market are
expected to be even more successful in the military market. Approximately 50% of all logic sales in the U.S.
military market are ASIC's today. That number is expected
to grow to 70% by 1993.. FPGA's offer lower costs and
more flexibility than mask gate arrays.
MILITARY PACKAGING
Xilinx offers two military packaging alternatives. In addition to the industry standard ceramic pin grid array (CPGA)
packages we offer a ceramic quad flat package (CQFP)
that meets the JEDEC standard outline drawing #MO-082.
This CQFP has 25 mil pin-to-pin spacing. It is shipped with
the leads unfonned allowing selection of cavity up or cavity
down and lead forming at the point of board assembly for
better contact.
The LCA is especially suited to military ASIC applications.
With a FPGA one specification can be written to cover
2-95
•
Military Logic Cell Arrays
multiple applications. Xilinx programmable gate arrays
are "configured" by downloading software to the part - no
fuses are blown. There is no requirement for post-programming testing for fault verification. The device is never
obsolete because it can be reprogrammed many times.
• Standard Product
- No overrun charges
- Simplified product qualification.
- No test vectors to write
- Simplified documentation (SMD)
Because Xilinx FPGA's are standard parts, they can be
stocked in inventory at Xilinx, at Xilinx distributors or at the
user site. One part can be stocked for multiple applications, minimizing inventory costs. Another benefit of being
a standard product is the inherent high reliability of a high
volume memory product rather than a low volume custom
circuit. Non-recurring engineering costs (NRE) are never
required for a FPGA thereby providing cost effective
solutions in military volumes and allowing very inexpensive design iterations.
Reliability
For maximum security the configuration data may be
"down-loaded" from a remote site thereby eliminating the
potential of tampering with the configuration data locally.
The FPGA can be made non-volatile in this instance with
the addition of a small battery backup.
One of the most effective advantages of the Xilinx FPGA
is the ability to reconfigure some or all of the device while
it remains in the circuit. This opens up entirely new
possibilities allowing the same gates to be used by different functions at different times.
• Standard Product
- Reliability of hi-volume memory product
• Fully tested by Xilinx
- Fault coverage assured by vendor
Security
• No design information needed by manufacturer
- Secure design process. Design data held to
vendor at user site.
• Remote configuration
- Ensures secure design data capability
Flexibility
• Standard product
- An ASIC where one spec can be used for multiple
applications
- An ASIC stocked by distribution'
IMPORTANT BENEFITS FOR MILITARY DESIGNS
Cost Containment
• No NRE
- Very cost effective in military volumes
- Low cost design iterations
• Reprogrammable
- Logic can be changed "on the fly"
• No FAB turnaround
- Design changes in minutes
2-96
MIL-STD-883 CLASS B COMPLIANCE
MIL-STD-883 CLASS B-METHOD 5005 QUALITY
CONFORMANCE INSPECTION (QCI) TESTING
Xilinx is now serving military customers in accordance with
MIL-STD-883 Class 8 paragraph 1.2.1 together with the
attendant requirements of M IL-M-38S1 O. This includes full
compliance with all processing requirements of Method
S004 and all Quality Conformance Inspection (QCI)
requirements of Method SOOS (Groups A,B,C,D).
Every lot of devices shipped to the requirements of
MIL-STD-883C is required to be qualified by four kinds of
Quality Conformance Inspection (QCI) Tests. The QCI
requirements specified by the Defense Electronics Supply
Center (DESC) undergo regular revisions. Xilinx rigorously incorporates these revisions into our QCI testing in
conformance with the requirements of MIL-STD-883C.
These are:
MIL-M-38510 (as invoked by MIL-STD-883)
Military Specification Microcircuits-General
Specification (describes the design, processing and assembly workmanship guidelines)
Group A-Electrical tests done to data sheet limits at all
three temperatures of the military temperature range,
-SsoC to +12SoC. These are performed on a sample from
the same lot being shipped.
MIL-STD-883
Military Standards-Test Methods and Procedures for
Microelectronics (delineates the detailed testing and inspection methods for military integrated circuits)
Group B-Mechanical tests performed on a sample of
devices of the same device/package type assembled
within the same 6 week widow of the lot being shipped.
This group consists of upto 8 subgroups including physical
dimensions, mark permanency, solderability, internal visual/mechanical, bond strength, internal water vapor content, fine & gross leak, and ESD sensitivity.
MIL-STD-883 Class B-Method 5004 Processing Flow
METHOD CONDo
FULL TRACEABILITY
Group c-Packagerelated reliability tests performed on
a sample of devices made with die from the same 1 year
window. This group consists of up to 2 subgroups including (1) life testing (1000 hr at 125°C) and (2) temperature
cycling, constant acceleration, fine & gross leak, and a
visual examination.
XILINX SPECIFICATION
2010/B
10101C
Group D-Package related reliability tests performed on
a sample of devices made in the same package within the
same 1 year window. This group consists of up to 8 subgroups: physical dimensions; lead integrity and seal; thermal shockltemperature cycling/moisture resistance/seal/
visual; mechanical shock vibration (variable frequency)/
constant acceleration/seal/visual; salt atmosphere/seal/
visual; internal water-vapor content; adhesion of lead
finish; lid torque.
2001/E
1014
250(;
1015
250(;
55°C. 25°C. +1250(;
2009
5005
1637 01
2-97
•
Military Logic Cell Arrays
2-98
XC20188
Military Logic Celi™Array
Product Specification. See Note 1.
FEATURES
Part
Number
Logic
Capacity
(usable
gates)
Configurable
Logic
Blocks
User
I/O's
Configuration
Program
(bits)
XC2018
1800
100
74
17878
• MIL-ST0-883 Class B Processing.
Complies with paragraph 1.2.1
• User-programmable gate array
• Low power CMOS static memory technology
• Standard product. Completely tested at factory
• Oesign changes made in minutes
in internal static memory cells. On-chip logic provides for
automatic loading of configuration data at power-up or on
command. The program data can reside in an EEPROM,
EPROM or ROM on the circuit board oron a floppy disk or
hard disk.
Complete user control for design cycle.
Secure design process
• Complete PC or workstation based
development system
- Schematic entry
- Auto Place/ Route (OS23)
- Oesign Editor (OS21)
- Logic & Timing Simulator (OS22)
- XACTOR In-circuit Verifier (OS24)
DESCRIPTION
Several methods of automatically loading the required
data are designed into the Logic Cell Array and are
determined by logic levels applied to mode selection pins
at configuration time. The form of the data may be either
serial or parallel, depending on the configuration mode.
The programming data are independent of the configuration mode selected.
The Logic Cell™ Array (LCA) is a high density CMOS
programmable gate array. Its patented array architecture
consists of three type of configurable elements: Input!
Output Blocks, Configurable Logic Blocks and Interconnect. The designer can define individual 110 blocks for
interface to external circuitry, define logic blocks to implement logic functions and define interconnection networks
to compose larger scale logic functions.
The XACT development system allows the user to define
the logic functions of the device. Schematic capture is
available for design entry, while logic and timing simulation, and in-circuit debugging are available for design
verification. XACT is used to compile the data pattern
which represents the configuration program. This data
can then be converted to a PROM programmer format file
to create the configuration program storage.
The Logic Cell Array's logic functions and interconnections are determined by the configuration program stored
See the XC2018 Commercial datasheet for a full description.
ORDERING INFORMATION
XC2018 - 50PG84B
I I 1 - B~MIL-STD·883,CLASS
33 (33 MHz TOGGLE)
50 (SO MHz TOGGLE)
~ ~ ~CERAMIC
PG
B, FULLYCOMPUANT
PIN GRID ARRAY PACKAGE.
84-LEAD
1637 02
TSCOD26 Rev:06
2-99
•
XC201 BB Military logic Cell Array
PIN ASSIGNMENTS
USER
OPERATION
10
10
va
va
va
10
TSC0026 Rev:06
«HIGH» IS HIGH IMPEDANCE WITH A 20-50 KO INTERNAL PULL-UP DURING CONFIGURATION
2-100
163703
CASE OUTLINE DRAWING
Conforms to MIL-M-38S10 Appendix C, Case P-8C.
1.000±.O10
'I
1.100±.012SO
I----
.100TVP
~
t"\
~
\..1--' \..
("r, ~ t\ (" r, ~ t\
\..
\..
~
r,
\..
f/
(" t\~
'-
r, r:
I--' \..
r, ("t\
f/
~
r,
\..
f/
TYP
:'I
'"
:'I (" t\ :'Ill
.100
If:
~
t"\
f/ \..1--'
G
I--'
\..
t"\
r:
f/ \..
I--'
{h~ tlLl\
f/ \..
r:
f/ \..
1.000
i.Ol0
\..
INDEX PIN
/
f/ \,.
•
r:
I--' '("1:'\ c\
:P ,O\'~OB MAX
'-
('
I--' '-
\,.
('
~
r:'\
\,.
\,.
_'-./
~
'-"
/"L:.
PIN NO.1 INDEX, /
DIMENSIONS ARE IN INCHES
--Ir--!.- OSO
6'~ ~
TA
r:'\
.01.
10
1:.010 ±.OO2DIA
NOTE: INDEX PIN MAY OR MAY NOT BE
ELECTRICALLY CONNECTED TO PIN C2.
XC2018: 84-Pin PGA Package
1637 04
STATIC BURN-IN CIRCUITS
S.0±.2SV
30
1.31<
1.15k
8.06k
lID
B2
C2
Bl
Cl
02
01
E3
E2
El
F2
F3
G3
Gl
G2
Fl
Hl
H2
Jl
Kl
J2
Ll
VCC
XC2018
PGA84
vee
DONEIPROG
RESET
1.51<
1.51<
1.3k
A11
Cl0
B11
C11
010
011
E9
El0
E11
F11
F9
G9
G11
Gl0
FlO
H11
Hl0
J11
K11
Jl0
Kl0
715
1-"'''-1---+--,
NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 118 WATT AT 1500C WITH A
4.99k
BUILD TOLERANCE OF 1% AND A 5%
III
lk
TOLERANCE OVER LI FE.
CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
III 30 "RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 WAT 150"C WITH A
TOLERANCE OF 5%.
1637 05
TSC0026 Rev:06
2-101
XC20188 Military Logic Cell Array
XC2018B Test Specification
Absolute Maximum Ratings
Units
Limits
Vee
Supply voltage relative to GND
-0.5 to 7.0
V
VIN
Input voltage with respect to GND
-0.5 to Vee + 0.5
V
VTS
Voltage applied to three-state output
-0.5 to Vee + 0.5
V
TSTG
Storage temperature (ambient)
-65 to +150
°C
TSOl
Maximum soldering temperature (10 sec@ 1/16 in.)
+260
°C
TJ
Maximum junction temperature
+150
°C
1637 Thl 04
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Test
High Level Output Voltage
Low Level Output Voltage
Quiescent Operating
Power Supply Current
Power-Down Supply Current
Leakage Current
Input High Level TIL
Input Low Level TTL
Input High Level CMOS
Input Low Level CMOS
Conditions
-55°C ~ Te ~ +125°C
Vee = 5.0 V ±10%
Symbol
VOH
VOL
leeo
leePD
III
VIHT
VllT
VIHe
Vile
Group A
Subgroups
Vee = 4.5 V, IOH = -4.0 mA
Vee = 5.5 V, IOl = 4.0 mA
CMOS Inputs, Yin = Vee = 5.5 V
TIL Inputs, Yin = Vee = 5.5 V
Yin = Vee = 5.5 V,
PWR DWN =OV
Vee = 5.5 V, Yin = Vee and 0 V
Guaranteed Input High
Guaranteed Input Low
Guaranteed Input High
Guaranteed Input Low
Limits
Min
Max
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
3.7
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
-10
2.0
0.4
10
15
0.5
10
Units
V
V
mA
mA
mA
.2 Vee
j.tA
V
V
V
V
7
j.ts
j.ts
0.8
.7 Vee
Switching Characteristics, General LCA
DONEIPROG
Program Width (Low)
Initialization
TpGW
TpGI
PWR OWN"
Power Down Supply
VPD
4
5
See Fig. 3
9,10,11
9,10,11
1,2,3
6
3.5
V
1637 Thl 05.
Table 1. Electrical Performance Characteristics
TSC0026 Rev:06
2-102
Conditions
-55°C ~ Tc ~ +125°C Group A
Sym
VCC = 5.0 V ±10% Subgroups
Test
2018-33
Limits
Min
Max
2018-50
Limits
Min
Max
Units
Switching Characteristics, Peripheral Mode Programming
Controls (CS, WRT)3.4
Last Active Input to First Inactive TCA
First Inactive Input to Last Active
TCI
1
2
CCLKs
DIN Setup
DIN Hold
3
4
5
Tccc
Toe
Tco
See Fig. 4
9,10,11
9,10,11
0.5
0.5
9,10,11
9,10,11
9,10,11
50
5
9,10,11
250
9,10,11
9,10,11
100
1.0
0.5
0.5
1.0
Ils
Ils
75
50
5
ns
ns
ns
250
ns
75
Switching Characteristics, Program Readback6
RTRIG Setup
TRTH
1
CCLK,
RTRIG Setup
RDATA Delay
TRTCC
TCCRO
2
3
See Fig. 7
100
100
100
ns
ns
Benchmark Patterns7
TplO + interconnect + 10 (TILO) +
Top. Measured on 10 cols.
Tplo + interconnect + 10 (TITO) +
Top. Measured on 10 cols.
Tplo + interconnect + 10 (TQLO) +
Top. Measured on 10 cols.
Tested on all CLBs with TICK
+ interconnect.
Tested on all CLBs with Tlcc
+ interconnect.
Tested on all CLBs with Tici
+ interconnect.
Tplo + interconnect + 10 (TRIO) +
Top. Measured on 10 rows.
Tplo + interconnect + TPL + TLI +
Top. Tested on aI/lOB's.
TS1
9,10,11
238
178
ns
TS2
9,10,11
288
228
ns
TS3
9,10,11
410
302
ns
TS4
9,10,11
85
62
ns
TS5
9,10,11
66
49
ns
TS6
9,10,11
90
67
ns
TS7
9,10,11
318
269
ns
TS8
9,10,11
274
204
ns
1637 Tbl 05b
Table 1. Electrical Performance Characteristics (Continued)
TSC0026 Rev:06
2-103
XC2018B Military Logic Cell Array
Test
Sym
Conditions
-55°C ~ Tc ~ +125°C
Vcc =5.0 V ±10%
Group A
Subgroups
2018-33
Limits
Min
Max
2018-50
Limits
Min
Max
Units
Application Guidelines, Switching, CLB7
Logic Input to Output,
Combinatorial
TllO
1
Transparent Latch
Additional for Q Through
For G to Out
TITO
TOlo
K Clock,
To Output
Logic-Input Setup
Logic-Input Hold
See Fig. 1
N/A
20
15
ns
2
N/A
N/A
25
13
20
8
ns
ns
TCKo
TICK
TCKI
9
3
4
N/A
N/A
N/A
15
12
1
ns
ns
ns
C Clock,
To Output
Logic- Input Setup
Logic-Input Hold
Tcco
TICC
TCCI
10
5
6
N/A
N/A
N/A
19
12
6
ns
ns
ns
Logic Input to G Clock,
To Output
Logic-Input Setup
Logic-Input Hold
TClo
Tici
TCII
11
7
8
N/A
N/A
N/A
27
6
9
ns
ns
ns
Set/Reset Direct,
Input A or D to Out
Through For G to Out
Master Reset Pin to Out
Separation of Set/Reset
Set/Reset Pulse-Width
TRIO
TRlo
TMRo
TRs
TRPW
12
13
N/A
N/A
N/A
N/A
N/A
22
28
45
17
12
9
9
ns
ns
ns
ns
ns
N/A
33
50
MHz
20
8
1
25
9
1
37
4
5
25
37
55
Flip-Flop Toggle Rate,
Q Through F to Flip-Flop
FClK
Clock HighS
TCH
14
N/A
12
8
ns
Clock Lows
TCl
15
N/A
12
8
ns
1637 Tbl 05c
Table 1. Electrical Performance Characteristics (Continued)
TSC0026 Rev:06
2-104
Test
Sym
Conditions
-55°C:.:;; Tc:.:;; +125°C
VCC = 5.0 V ±10%
Group A
Subgroups
2018-33
Limits
Min
Max
2018-50
Limits
Min
Max
Units
Application Guidelines, Switching, IOB7
Pad (Package Pin) to
Input (Direct)
I/O Clock
To Input (Storage)
To Pad-Input Setup
To Pad Input Hold
Pulse Width
Frequency
TPID
1
TLI
TpL
TLP
TLw
5
2
3
4
N/A
See Fig. 2
N/A
N/A
N/A
N/A
N/A
12
8
20
33
50
ns
ns
ns
ns
MHz
12
0
12
15
ns
8
0
9
Output,
To Pad (Output Enable)
Top
8
N/A
15
12
ns
Three-State,
To Pad Begin hi-Z
To Pad End hi-Z
TTHZ
TTON
9
10
N/A
N/A
25
25
20
20
ns
ns
RESET,
To Input (Storage)
To Input Clock
TRI
TRC
6
7
N/A
N/A
40
35
30
25
ns
ns
Application Guidelines, Switching, Slave Mode Programming 7
CCLK,
To DOUT
DIN Setup
DIN Hold
High Time
Low Time
Frequency
Tcco
TDCC
TCCD
TCCH
TccL
Fcc
3
1
2
4
5
See Fig. 6
N/A
N/A
N/A
N/A
N/A
N/A
100
10
40
0.5
0.5
1.0
1
100
10
40
0.5
0.5
1.0
1
ns
ns
ns
JlS
Jls
MHz
Application Guidelines, Switching, Master Mode Programming 7.RCLK,
From Address Invalid
To Address Valid
To Data Setup
To Data Hold
RCLK High
RCLK Low
TARC
TRAC
TDRC
TRCD
TRCH
TRCL
1
2
3
4
5
6
See Fig. 5
N/A
N/A
N/A
N/A
N/A
I N/A
60
0
600
4.0
60
0
600
4.0
ns
ns
ns
ns
ns
JlS
N/A
N/A
N/A
1
1
150
1
1
150
JlS
Jls
ns
0
200
0
200
Application Guidelines, Switching, General LCA7
RESETlO
M2, M1, MO Setup
M2, M1, MO Hold
Width (Low)
TMR
TRM
TMRW
1
2
3
See Fig. 3
1637 Tbl 05d
Table 1. Electrical Performance Characteristics (Continued)
TSC0026 Rev:06
2-105
XC2018B Military Logic Cell Array
INPUT (A,B,C,D)
x
x
-CDTILO~
XX
OUTPUT (X,Y)
(COMBINATORIAL)
® TITO
OUTPUT (X,Y)
(TRANSPARENT LATCH)
XX~
o
-G)TICK
TCKI-
CLOCK(K)
- 0 Tlcc
I
- (!)
I
® Tccl -
CLOCK(C)
T ICI
f-
CLOCK (G)
® TclI -
I - - @ TCKO @Tcco -
@
TclO
AIJ
OUTPUT (VIA FF)
{
SET/RESET DIRECT (A,D)
I
SET/RESET DIRECT (F,G)
f
@
TRIO
@
TRLO
@TCL
CLOCK (ANY SOURCE)
=1____
Timing is measured at 0.5 Vee levels with 50 pF minimum output load.
Input signal conditioning: Rise and fall times,; 6 ns, Amplitude = 0 and 3V
Figure 1. Switching Characteristics Waveforms, CLB
TSC0026 Rev:06
2-106
1637 06
I:XIUNX
PAD
(PACKAGE PIN)
x----....
_ _oJ
(IN)
OUTPUT SIGNAL
®
TTHZj.-
INPUT
(DIRECT)
THREE-STATE
l
(VOCLOCK)
INPUT
(REGISTERED)
163707
Figure 2. Switching Characteristics, lOB
__--II
~r- ~~
1
Vee (VALID)
\
/ t
,"- __ - : -•_ ' , VPO
-...,.....---1
MO/M11M2
DONEJPROG
(OUTPUT)
USERVO
CLOCK
J=:? .
--U-S-ER-S-.T~A-TE-"""WO
PIN NO.1 INDEX. /
INDEX PIN
TYP
S;'A108
t\
MAX
("l"\ ("
f".
\.
r.
r.
\.
\.
-.l
TA
\.
\.
'-
-+Ir--~.050 ±o~g2DIA
±.010
DIMENSIONS ARE IN INCHES
f".":-..£.
1.000
±.O10
V
r:t\ ("l\
I""
\.
/"::\
\::/\. V
(""
/"::\
'-
-'--"
10
r.
\.
11
.
NOTE: INDEX PIN MAY OR MAY NOT BE
ELECTRICAlLY CONNECTED TO PIN C2.
XC3020: 84-Pin PGA Package
1637 17
STATIC BURN-IN CIRCUIT
S.0±'2SV
30 ;:~ B.OSk
(1)
1.3k
1.3k
1.1Sk
,Ir ~k ~1hhH~
--t,-
=IT:
1.Sk
Al1
C10
Bll
t-tr,-
ef,-
7
1.5k
~
To
"E1
To
fa
1.3k
[II
rn
RATED FOR 118 WATT AT 1SOa C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LIFE.
CAPACITOR HAS 10"10 TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
30 0 RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 WAT150 D C WITH A
TOLERANCE OF 5%.
1637 18
TSC0085 Rev:03
2-114
E:XlUNX
XC3020B Test SjJeclflcatlon
Absolute Maximum Ratings
Limits
Units
Vee
Supply voltage relative to GND
-0.5 to 7.0
V
VIN
Input voltage with respect to GND
-0.5 to Vee + 0.5
V
VTS
VoHage applied to three-state output
-0.5 to Vee + 0.5
V
TSTG
Storage temperature (ambient)
-65 to +150
·C
~~
TSOL
Maximum soldering temperature (10 sec@ 1/16 in.)
TJ.
Maxi~um
junction temperature
+260
·C
+150
·C
1637 Thl07
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device ..These are stress ratings only, and funGlional operation of the device at lhese or any other
conditions beyond those listed under RecommE!nded Operating Conditions, is not implied. Exposure
to, Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Test
Symbol
High Level Output Voltage
Low Level Output Voltage
Quiescent Operating2
Power Supply Current
VOH
VOL
lceo
Power-Down Supply Current
ICCPD
Leakage Current
Horizontal Long Line
Pull-up Current
Input High Level TTL
Input Low Level TTL
Input High Level CMOS
Input Low Level CMOS
IlL
IRll
.
VIHT
VILT
VIHe
VILe
Conditions
-55°C ~ Te ~ +125°C
Vee;= 5,OV ±10%
Group A
Subgroups
Vee = 4.5 V,IOH == -4.0 rnA
Vee = 5.5V, IOL '" 4.0 rnA
CMOS Mode, Vin = Vee == 5.5 V
TTL Mode, Vin = Vee = 5.5 V
' Vin = Vee = 5.5 V,
PWRDWN=OV
Vee = 5.5 V, Vin = Vee and 0 V
Measured as an;average
Guaranteed
(3uaranteed
Guaranteed
Guaranteed
Input High
Input Low
Input High
Input Low
1,2,3
1,2,3
1,2,3
Lirnits
Max
Min
3.7
1,2,3
1,2,3
1,2,3
1,2,3
-20
1,2,3
1,,2,3
1,2,3
1,2,3
2.0
Units
0.4
1
V
V
rnA
15
0.5
rnA
rnA
20
2.4
rnA
0.8
.7 Vee
.2 Vee
~
V
V
V
V
1637Thloaa
Table 1. Electrical Performance Characteristics
TSCOOS5 Rev:03
XC3020B Military Logic Cell Array
Test
Conditions
-55°C ~ Tc ~ +125°C
Vcc = 5.0 V ±10%
Sym
Group A
Subgroups
Limits
Min Max
Units
Switching Characteristics, Gelleral LCA
DONEIPROG
Program Width (low)
Initialization
TpGW
TpGI
PWR OWN3
Power Down Supply
Vccpo
RESET4
M2,M1,MO Setup
M2,M1,MO Hold
Width (low) abort
TMR
TRM
TMRW
5
6
See Fig. 1
9,10,11
9,10,11
1,2,3
2
3
4
6
7
J.Ls
J.Ls
3.5
V
9,10,11
9,10,11
9,10,11
1
1
6
J.LS
J.Ls
J.LS
9,10,11
9,10,11
9,10,11
9,10,11
0.5
60
0
J.Ls
ns
ns
ns
Switching Characteristics, Peripheral Mode Programming 5
WRTlOW
DIN Setup
DIN Hold
Ready/Busy
TCA
Toc
Tco
TWTRB
1
2
3
See Fig. 4
4
60
Switching Characteristics, Slave Mode Programming 5
CClK,
To DOUT
DIN Setup
DIN Hold
High Time
low Time
Frequency
Tcco
Tocc
Tcco
TCCH
TCCl
Fcc
3
1
2
See Fig. 5
4
5
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
100
60
0
0.5
0.5
1.0
1
ns
ns
ns
J.Ls
J.LS
MHz
1637 lbl OBb
Table 1. Electrical Performance Characteristics (Continued)
TSC0085 Rev:03
2-116
Conditions
-55°C ~ Tc ~ +125°C
VCC = 5.0 V ±10%
Sym
Test
Group A
Subgroups
Limits
Min Max
Units
Switching Characteristics, Program Readback 6 ,7
RTRIG Setup
TRTH
1
CCLK,1
RTRIG Setup
RDATA Delay
TRTCC
TCCRD
2
3
See Fig. 7
9,10,11
250
9,10,11
9,10,11
200
ns
100
ns
ns
9,10,11
135
ns
Benchmark PatternsB
TPID + interconnect + 8 (TllO) +
Top. Measured on 8 cols.
TCKO + TICK + TCKI +
interconnect
TCKO + TOlO + TllO + TDICK +
interconnect
TllO + TECCK + interconnect
TBl
TB2
Tested on all CLBs
9,10,11
32
ns
TB3
Tested on all CLBs
9,10,11
53
ns
TB4
Tested on all CLBs
9,10,11
35
ns
TOKPO + Tops - TOPF + TPICK
TBS
Tested on all CLBs
9,10,11
73
ns
TCKO + TOLO + Tpus + TICK +
interconnect
TCKO + TOLO + Tpus + TICK +
interconnect
TCKO + TOLO + Tlo + TICK +
interconnect
TCKO + TOLO + Tlo + TICK +
interconnect
Too
One long line pull-up
9,10,11
73
ns
TB7
The other long line pull-up
9,10,11
83
ns
TBB
No pull-up, lower long lines
9,10,11
47
ns
TB9
No pull-up, upper long lines
9,10,11
57
ns
1637Tb10Bc
Table 1. Electrical Performance Characteristics (Continued)
TSC0085 Rev:03
2-117
XC3020B Military Logic Cell Array
Test
Conditions
-SsoC ~ Tc ~ +12SoC
Vcc =S.O V±10%
Sym
Application Guidelines, Switching,
Combinatorial
Reset to CLB output
Reset Direct width
Master Reset pin to CLB out
Group A
Subgroups
Limits
Min Max
Units
elB8
TllO
TRIO
TRPW
TMRO
1
9
13
See Fig. 2
N/A
N/A
N/A
N/A
14
12
30
ns
ns
ns
ns
12
11
ns
ns
12
K Clock9
To CLB output
Additional for Q returning
through F or G to CLB out
Logic-input setup
Logic-input hold
Data In setup
Data In hold
Enable Clock setup
Enable Clock hold
Clock (high)
Clock (low)
TCKO
TOLO
8
N/A
N/A
TICK
TCKI
TDICK
TCKDI
TECCK
TCKEC
TCH
TCl
2
3
4
S
6
7
11
12
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12
0
8
6
10
0
9
9
ns
ns
ns
ns
ns
ns
ns
ns
Flip-flop Toggle Rate
FClK
N/A
SO
MHz
Application Guidelines, Switching, Internal Buffers8
Clock Buffer
TBUF
Data to Output
Three-state to Output
Single Pull-up
Pair of Pull-ups
Bidirectional
TGCK
N/A
9
ns
Tlo
N/A
8
ns
Tpus
TpUF
N/A
N/A
34
17
ns
ns
BIDI
N/A
6
ns
1637 "fbI oad
Table 1. Electrical Performance Characteristics (Continued)
TSC0085 Rev:03
2-118
Test
Conditions
-55°C::; Tc::; +125°C
Vcc = 5.0 V ±10%
Sym
Group A
Subgroups
Limits
Min
Max
Units
Application Guidelines, Switching, IOB8,10
Pad (package pin)
To inputs TClKIN, BClKIN
To inputs DIRECT IN
See Fig. 3
TplDC
TplO
N/A
N/A
3
110 Clock
5
9
ns
ns
11
ns
ns
ns
ns
ns
ns
ns
ns
TIKRI
TpicK
TIKPI
TOKPo
TooK
TOKo
TIOH
Tlol
11
12
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Output
To pad (enabled fast)
To pad (enabled slow)
TOPF
Tops
10
10
N/A
N/A
14
39
ns
ns
Three-State
To pad begin hi-Z (fast)
To pad valid (fast)
TTSHZ
TTSON
9
8
N/A
N/A
12
20
ns
ns
Master Reset
To input RI
To output (FF)
TRRI
TRPo
13
14
N/A
N/A
35
50
ns
ns
200
ns
ns
ns
ns
To 1/0 RI input (FF)
1/0 pad-input setup
1/0 pad-input hold
To 110 pad (fast)
1/0 pad output setup
1/0 pad output hold
Clock (high)
Clock (low)
4
1
2
7
5
5
30
0
18
15
0
9
9
Application Guidelines, Switching, Master Parallel Mode Programming 8,11
RClK,
To Address Valid
To Data Setup
To Data Hold
RClK High
RClK low
TRAC
TORc
TRco
TRCH
TRcl
1
2
3
4
5
See Fig.S
N/A
N/A
N/A
N/A
N/A
0
SO
0
600
4.0
f..lS
1637 Tbl OBe
Table 1. Electrical Performance Characteristics (Continued)
TSC0085 Rev:03
2-119
XC3020B Military Logic Cell Array
, . - -_ _ _
MO/M1/M2
~IIt_--(0TMRW)-------
-f®'~®'~f------->C®"~=-1
DONE/PROG
(OUTPUT)
__J__·C®T
PG1
INIT
(OUTPUT)
USER STATE
-J/
_ _ _ _ _ _C_l_E_ARlt-ST_A_T_E_ _ _ _ _ _ _
-
II
CONFIGURE
.
\'---------/
________________________________________________--4~NOTE3~~______
\,
I t
r
'-----.1-,-
Vee (VALID)
V
CCPD
1637 19
Figure 1. General LCA Waveforms
ClB OUTPUT (X,V)
(COMBINATORIAL)
ClB INPUT (A,B,C,D,E)
ClBClOCK
14----
@
o
TCl
--401<"--
@
TCH
~----~
TDICK
ClBINPUT
(DIRECT IN)
® TECCK
ClBINPUT
(ENABLE CLOCK)
ClBOUTPUT
(FLIP-FLOP)
ClB INPUT
(RESET DIRECT)
ClBOUTPUT
(FLIP-FLOP)
1637 20
Figure 2. CLB Waveforms
TSC0085 Rev:03
2-120
E:XIUNX
VO BLOCK (I)
110 PAD INPUT
-®-TPID~~[-t CD TpICK--.... ® TIKPI]~----'!"'.t-
110 CLOCK
(IKIOK)
~---
@
T1DL - - - I 4 - - - -
110 BLOCK (RI)
RESET
110 BLOCK (0)
@TOp
II
110 PAD OUTPUT
(DIRECn
VO PAD OUTPUT
(REGISTERED)
------------------~f0) TOKPO
J---rr-®-~-SON----@-~-~,j I
VO PADTS
VO PAD OUTPUT
--------~(~
____________~r__
163721
Figure 3. lOB Waveforms
CS2
I
/
\
CS11CSO
__---17
\~
,
__________________~i_______
WRT
~--------------------.
DO-D7
CCLK
,,
\. ___ J
RDY/BUSY
DOUT
,,
,,
,,
\. ___ J
_______________________ J
GROUP OF
8 CCLKs
,,
__~x~·_~x~____________~
Figure 4. Peripheral Mode Waveforms
TSC0085 Rev:03
2-121
1637 22
XC3020B Military Logic Cell Array
DIN
CCLI<
=tG)'=f(i),~J
'f'.'
1-~,~--- 0 ---_114,. . . @ Tccoj,~
TCCH
DOUT
(OUTPUT)
_ _ _ _ _ _ __
)K
BITN-1
r-
0'=
BITN
1637 23
Figure 5. Slave Mode Waveforms
AO-A1S
(OUTPUT)
DD-D7
ADDRESS n + 1
ADDRESS n
\:
CD
-------------------)~----~~~-----TRAC
BYTE n
RClK
(OUTPUT)
CClK
(OUTPUT)
DOUT
(OUTPUT)
BYTE n-1
Figure 6. Master Parallel Mode Waveforms
TSC0085 Rev:03
2-122
1637 24a
DONE/PROG
(OUTPUT)
____-L/___________________________________ _
~0 TRTH-::-1
t'----_ __
RTRIG
(1)
TRTCC~
CCLK
1..----""'
@TCCRD~.
I
RDATA
(OUTPUT)
VALID
1637 25
Figure 7. Program Readback Waveforms
XC3020B Data Sheet Notes
1. Xilinx maintains this specification as a controlled document. To comply with the intent of MIL-STD-883, and to insure the
use of the most recently released device performance parameters, please request a copy of the current revision of this
Table 1 Test Specification (TSC 0085) from Xilinx.
2. No output current loads, no active input or long line pull· up resistors, and with the device configured with the MAKEBITS
'1ie" option.
3. PWRDWN transitions must occur during operational Vcc levels.
4. RESET timing relative to valid mode lines (MO, Ml, M2) is relevant only when RESET is used to delay configuration.
5. Configuration must be delayed until the INIT of all LCA's is HIGH. WRT cannot go active until RDVisOSY goes high.
6. Readback should not be initiated until configuration is complete.
7. CCLK and DOUT timing are the same as for slave mode.
8. Testing of the Applications Guidelines is modeled after testing specified by MIL-M-38S1 0/605. Devices are first 100%
functionally tested. Benchmark patterns are then used to measure the Application Guidelines. Characterization data are
taken at initial device qualification, prior to introduction of significant changes, and at least twice yearly to monitor correlation
between benchmark patterns, device performance, XACT software timings, and the data sheet.
9. The CLB K to Q output delay (TCKO) plus the shortest possible interconnect delay is always longer than the Data In hold
time requirement (TCKDI) on the same die.
10. Voltage levels of unused pads must be valid logic levels. Each can be configured with the internal pull-up resistor, configured as a driven output, or driven from an external source.
11. At power-up, Vcc must rise from 2.0V to Vcc minimum in less than 10 ms. Otherwise, delay configuration using RESET.
12. All timings except TTSHZ and TTSON are measured at 1.5 V level with 50 pF minimum load output. For input signals, rise and
fall times are less than 6 ns, with low amplitude = OV, and high = 3V.
TTSHZ is determined when the output shifts 10% (of the output voltage swing) from VOL level or VOH level. The following
circuit is used:
fue
11K
vCC
1K
PAD
GND
SOp! MIN
1637 26
12. (continued)
TTSON is measured at 0.5 Vee level with VIN
following load circuit is used:
= 0 for Tri-State to active high, and VIN = Vcc for Tri-State to active low.
The
~VIN
... I1
~
·1K
SOp! MIN
1637 27
TSC0085 Rev:03
2-123
•
XC3020B Military Logic Cell Array
TSC0085 Rev:03
2-124
XC3090B
Military Logic Cell™ Array
PRELIMINARY
Subject to Change
Product Specification. See Note 1.
FEATURES
Part
Number
Logic
Capacity
(gates)
Configurable
Logic
Blocks
XC3090
9000
320
MIL-ST0-883 Class B Processing.
Complies with paragraph 1.2.1
• User-programmable gate array
• Low power CMOS static memory technology
User
110's
144
Conflguration
Program
(bits)
64160
• Standard product. Completely tested al factory
• Design changes made in minutes
in internal static memory cells. On-Chip logic provides for
automatic loading of configuration data at power-up or on
command. The program data can reside in an EEPROM,
EPROM or ROM on the circuit board or on a floppy disk or
hard disk.
• Complete user control for design cycle.
Secure design process
• Complete PC or workstation based
development system
- Schematic entry
- Auto Placel Route (OS23)
- Design Editor (OS21)
- Logic & Timing Simulator (OS22)
- XACTOR In-circuit Verifier (OS24)
DESCRIPTION
Several methods of automatically loading the required
data are designed into the Logic Cell Array and are
determined by logic levels applied to mode selection pins
at configuration time. The form of the data may be either
serial or parallel, depending on the configuration mode.
The programming data are independent of the configuration mode selected.
The Logic Cell™ Array (LCA) is a high density CMOS
programmable gate array. Its patented array architecture
consists of three type of configurable elements: InpuV
Output Blocks, Configurable Logic Blocks and Interconnect. The designer can define individual 1/0 blocks for
interface to external circuitry, define logic blocks to implement logic functions and define interconnection networks
to compose larger scale logic functions.
The XACT development system allows the user to define
the logic functions of the device. Schematic capture is
available for design entry, while logic and timing simulation, and in-circuit debugging are available for design
verification. XACT is used to compile the data pattern
which represents the configuration program. This data
can then be converted to a PROM programmer format file
to create the configuration program storage.
The Logic Cell Array's logic functions and interconnections are determined by the configuration program stored
See the XC3000 Commercial data sheet for a full description.
ORDERING INFORMATION
XC3090 - 50 PG175 B
T11_
50 (50 MHz TOGGLE) - - - - - - - ' -
B= MIL·STD-883. CLASS B. FULLY COMPLIANT
~ PG =CERAMIC
PIN GRID ARRAY PACKAGE.
175-LEAD
1637 28
TSC0097 Rev:03
2-125
•
XC3090B Military Logic Cell Array
PIN ASSIGNMENTS
USER
OPERATION
PWR DWN (1\
VCC
(HI
I(H
DC
PWR UWN (1\
PWR
PWR OWN (1\
PWR OWN III
M1 OW)
MON)
M1
MOil
M' HIGH
MO
M1 OW)
MOLOW)
He
H[
HD
HD
Ifl (1\
I
I
1m
OVi
Oil
I
3ND
I I
GNC
_~-lIL
RESF"(I)
I
GNI
fiES
'(I)
'QIj
rA_
JA
JA
lA'
rA
" UA I A 2
PWRDWi'JIII
E14
116
H1S
,J14
vc
RDATA
RTRIG(I)
~
I/O
I/O
GNC
~ '(I)
DAJ
JAl
VC
DATA
I I
B2
D9
814
815
IKJ
H1
R9
I/O
_Vc~NJl
I/CC
IA
\199
1(11:':""""
_~
:~
I,',•••,.,.,""',,"" UA I A 2 (I).,.,•••"""""",',,, IJA I A 2 (I) ,•••,••,."
HT
I/O
",·"" ••,.,.,.,··,·.,.,DATA l(1)
LK
CCLK
A1
A2
A3
A15
A4
A14
AS
GN[
A13
A6
A12
A,
A'
AS
A10
A9
AO
A1
A2
A3
A1S
A4
A14
AS
GN[
A13
A6
A12
A,
A'
AS
A10
A9
R2 ",,,',',","
LK (11"'.,."""'"
"2
I/U
I/O
I/O
I/O
M3
p'
N'
M1
K2
K'
J3
H2
H:
F2
E~
"3
C2
IKJ
I/O
I/O
I/O
GNC
I/O
I/O
IKJ
I/O
I/O
I/O
I/O
I/O
1637 29
[ ] ] ] REPRESENTS A SOKn TO 100Kn PULL-UP
* INIT IS AN OPEN DRAIN OUTPUT DURING CONFIGURATION
(I) REPRESENTS AN INPUT
TSC0097 Rev,03
2-126
PIN ASSIGNMENTS (Continued)
PGA Pin
Number
B2
XC-3090
PGAPln
Number
XC-3090
PGAPin
Number
XC-3090
PGA Pin
Number
XC-3090
l'WRON
D13
110
R14
DONE-l'rr
R3
DO-DIN-I/O
D4
TCLKIN-I/O
Ml-11D7i1'A
N13
D7-1/0
N4
DOUT-I/O
B3
GNO
T14
XTALl (OUTj-BCLKIN-1I0
CCLK
B15
MO-RTRlG"
P13
D14
vee
R13
M2-1I0
T13
N3
P2
GNO
C15
E14
HOC-liD
N12
110
110
110
110
R2
P3
B16
110
110
110
P12
06-110
Rl
R12
110
110
110
110
110
D5-1/0
CSll"-1/0
110
110
110
110
D4-1I0
110
N2
C8
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
B14
C14
D8
GNO
C4
B4
A4
D5
C5
B5
AS
C6
D6
B6
A6
B7
C7
D7
A7
A8
B8
vee
D9
110
110
110
110
110
110
110
110
110
110
110
110
110
C9
B9
A9
Al0
Dl0
Cl0
Bl0
All
Bll
Dll
Cll
A12
B12
110
110
110
110
110
110
C12
D12
A13
B13
C13
A14
D15
C16
H16
H15
lNlT-I/O
P9
F14
\
T12
roc-liD
110
110
110
110
110
110
110
110
110
016
E15
E16
F15
F16
G14
G15
G16
H14
J14
J15
J16
K16
K15
K14
L16
L15
M16
M15
L14
N16
P16
N15
Pll
Nll
Rll
Tll
Rl0
Pl0
Nl0
Tl0
T9
R9
vee
N9
vee
GNO
N8
GNO
110
110
110
110
110
110
110
110
110
110
110
110
110
P8
D3-1I0
CST-liD
R8
Pl
Nl
AS-li~
L3
Ml
110
110
Al5-I/O
L2
A4-1I0
11
J2
110
110
A14-1/0
AS-liD
110
110
J3
GNO
M2
K3
K2
Kl
Jl
H3
H2
Hl
Gl
R5
T7
N7
P7
R7
T6
R6
N6
P6
T5
AO-WS"-1I0
Al-CS2-1/0
110
110
A2-1/0
M3
110
110
110
110
D2-1I0
110
110
110
110
110
Dl-I/O
T8
vee
vee
A13-1/0
AS-liD
F2
110
110
110
110
A12-1/0
El
A7-UO
E2
Cl
110
110
All-liD
A8-1/0
D2
110
G2
G3
Fl
F3
Dl
P5
RDY/lIDSV-RcrK-1I0
Bl
110
M14
110
110
N5
110
110
110
110
E3
Al0-1I0
C2
A9-1/0
D3
C3
GNO
R16
P15
XTAL2(IN)-1I0
T4
N14
R15
GNO
R4
11ESET
P4
P14
vee
vee
1637 Tbl 09
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-limited.
Pins A2, A3, A 15, A 16, Tl, T2, T3, T15 and T16 are not connected.
Pin A 1 does nol exist.
_u
TSC0097 Rev:03
2-127
•
XC3090B Military Logic Cell Array
CASE OUTLINE DRAWING
Conforms to MIL-M-38510 Appendix C, Case P-BC.
o
.025 REF.
WE10 METAL1C HEATSINK
ElECTRICALLY CQNIIECTED TO
INDEX
vee
f
!
.180
PIN KOVAR
.000R.TYP.
.016 REF.
GGGGGGGGGGGGGGG 0 - + + - - - - - - .
G0GGGGGG,GGGGGG0 0
MGGGGGGGGGGGGGGGG
13 GGGG
12GGGG
GGGG
GGGG
"GGGG
I. GGGG
GGGG
GGGG
·GGGG
«. G 0--=GO-G=0-If---+
GG0G
7GGGG
GGGG
GGGG
'GGGG
GGGG
'GGGG
G G G G !!=====F====lj.--r"""<""..,......,.~4-----i
3GGGG
2G0GG
'GGGG GGGGGG
I.
16
15
lYP..070 OIA
,,005
1.660SO±.016
1.500±.015
4
DielECTRIC COAT
STAND OFF PIN
4PL
T
R
P
N
M
.695±OO7----!
TSC0097 Rev:03
2-128
1637 30
I:XIUI\JX
STATIC BURN-IN CIRCUIT
1
30
3
5.0±0.25V
4.02k
8 ('j ~
a;1~blJd~lwldu:lal~ldJ:h ~ "l ~l"l;;:l~ld:;l~:hl!1jl~lzld~l1[l;]l~l~
~~
D4
8
~\
~
~r
i
;j
8~
tt ,~
>
4
/
'"
g;
»
~
~
N4
R3
~
~
DIN
~
~
~
~
~
~
~
~
~
,.¥,
~
~
~
~
~
~
~
~
~
~
•
~
~
4
~
715
1.5«
?
~
~
~
~
1.5«
1.151<
'*faTsvss
vcc
vss
XC3090
PG 175
VCC
~
~
f-jjfo-
-¥sN9
4
~
~
¥o
cWo-
~
~
~
irtO
-'fif""
"iiiT
Mmf-ffit
'-j:ffi--'prt-
~
-Tit
iIT2-
'itr
>-jjf2
~
~
*-ifr--j;ffz-
f-N
~
jM1
~f 8Ng
~
~
f-5&
DONEJPGM\
vss
VCC\
R~~
MO
>:E:I:
C14
~~I~
I~ ~~
. '" WmOOQ i'.LwwU::U::EE5II
00
'Fii3"
-p,g
-w
w
ifit
"~ISI&r ~1~1~1~1~15IGIGlil'" .... rl~I~I~l~l~l~l~l~lil~lil~lilr
1k
1.3k
1.3k
P14
R15
4.S9k
i"'~~~~~~i~z£z~i~z
1.3k
O1~F+
rn
NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 118 WAn AT 150"C WITH A
BUILD TOLERANCE OF 1'% AND A 5%
TOLERANCE OVER LIFE.
[gJ CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
300 RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 WAT150"C WITH A
TOLERANCE OF 5%.
rn
TSC0097 Rev:03
2-129
163731
XC3090B Military Logic Cell Array
XC3090B Test Specification
Absolute Maximum Ratings
Limits
Units
Vee
Supply voltage relative to GND
-0.5 to 7.0
V
VIN
Input voltage with respect to GND
-0.5 to Vee + 0.5
V
VTS
Voltage applied to three-state output
-0.5 to Vee + 0.5
V
TSTG
Storage temperature (ambient)
-65 to +150
°C
TSOL
Maximum soldering temperature (10 sec@ 1/16 in.)
+260
°C
TJ
Maximum junction temperature
+150
°C
1637Tbll0
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure
to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Test
Symbol
High Level Output Voltage
Low Level Output Voltage
Quiescent Operating 2
Power Supply Current
VOH
VOL
leeo
Power-Down Supply Current
leePD
Leakage Current
Horizontal Long Line
Pull-up Current
Input High Level TIL
Input Low Level TTL
Input High Level CMOS
Input Low Level CMOS
Conditions
-55°C ~ Te ~ +125°C
Vee = 5.0 V ±10%
Group A
Subgroups
Limits
Min
Max
Vee = 4.5 V, IOH = -4.0 mA
Vee = 5.5 V, IOL = 4.0 mA
CMOS Mode, Yin = Vee = 5.5 V
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
IlL
IRLL
TIL Mode, Yin = Vee = 5.5 V
Yin = Vee = 5.5 V,
PWR DWN =OV
Vee = 5.5 V, Yin = Vee and 0 V
Measured as an average
1,2,3
1,2,3
-20
VIHT
VILT
VIHe
VILe
Guaranteed
Guaranteed
Guaranteed
Guaranteed
1,2,3
1,2,3
1,2,3
1,2,3
2.0
Input
Input
Input
Input
High
Low
High
Low
3.7
Units
0.4
3
V
V
mA
15
2.5
mA
mA
20
2.4
~
mA
0.8
.7 Vee
.2 Vee
V
V
V
V
1637 Tbl l1a
Table 1. Electrical Performance Characteristics
TSC0097 Rev:03
2-130
Test
Conditions
-55°C ~ Tc ~ +125°C
Vcc =5.0 V ±10%
Sym
Group A
Subgroups
Limits
Min
Max
Units
Switching Characteristics, General LCA
DONEIPROG
Program Width (Low)
Initialization
TpGW
TpGI
PWR OWN'
Power Down Supply
VCCPD
RESET4
M2,M1,MO Setup
M2,M1,MO Hold
Width (low) abort
TMR
TRM
TMRW
5
6
TCA
Toe
TeD
TWTRB
9,10,11
9,10,11
2
3
4
1
2
3
6
7
/ls
/lS
3.5
V
9,10,11
9,10,11
9,10,11
1
1
6
/ls
/lS
9,10,11
9,10,11
9,10,11
9,10,11
0.5
60
0
/ls
ns
ns
ns
1,2,3
Switching Characteristics, Peripheral Mode
WRTLOW
DIN Setup
DIN Hold
Ready/Busy
See Fig. 1
/lS
Programmlng 5
See Fig. 4
4
60
Switching Characteristics, Slave Mode Programming 5
CCLK,
To DOUT
DIN Setup
DIN Hold
High Time
Low Time
Frequency
TCCD
TDCC
TCCD
TCCH
TCCL
Fcc
3
1
2
See Fig. 5
4
5
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
100
60
0
0.5
0.5
1.0
1
ns
ns
ns
/lS
/lS
MHz
16371blllb
Table 1. Electrical Performance Characteristics (Continued)
TSC0097 Rev:03
2-131
•
XC3090B Military Logic Cell Array
Test
Conditions
-55°C ~ Tc ~ +125°C
Vcc =5.0 V ±10%
Sym
Group A
Subgroups
Limits
Min Max
Units
Switching Characteristics, Program Readback6 .7
RTRIG Setup
TRTH
1
CCLK,
RTRIG Setup
RDATA Delay
Clock Low
Clock High
TRTCC
TCCRO
TCClR
TCCHR
2
3
4
5
See Fig. 7
9,10,11
250
9,10,11
9,10,11
9,10,11
9,10,11
200
ns
100
2.0
ns
ns
J.1S
J.1S
9,10,11
303
ns
1.2
0.5
Benchmark PatternsB
Tplo + interconnect + 20 (TllO) +
Top. Measured on 16 cols.
TCKO + TICK + TCKI +
interconnect
TCKO + TOlO + TllO + TOICK +
interconnect
TOLD + TECCK + interconnect
TBl
TB2
Tested on all CLBs
9,10,11
32
ns
TB3
Tested on all CLBs
9,10,11
53
ns
TB4
Tested on all CLBs
9,10,11
35
ns
TOKPO + Tops - TOPF + TPICK
TB5
Tested on all CLBs
9,10,11
73
ns
TCKO + TOLO + TBUF + TICK +
interconnect
TCKO + TOLO + TBUF + TICK +
interconnect
TCKO + TOLO + TBUF + TICK +
interconnect
TCKO + TOLO + TBUF + TICK +
interconnect
TB6
One long line pull-up
9,10,11
73
ns
TB7
The other long line pull-up
9,10,11
83
ns
TB8
No pull-up, lower long lines
9,10,11
47
ns
TB9
No pull-up, upper long lines
9,10,11
57
ns
1637Tbll1c
Table 1. Electrical Performance Characteristics (Continued)
TSC0097 Rev:03
2-132
Conditions
-SsoC ~ Tc ~ +12SoC
Vcc =S.O V ±10%
Sym
Test
Group A
Subgroups
Limits
Min Max
Units
Application Guidelines, Switching, ClBa
Combinatorial
Reset to ClB output
Reset Direct width
Master Reset pin to CLB out
TILO
TRIO
TRPW
TMRO
1
9
13
See Fig. 2
N/A
N/A
N/A
N/A
14
12
30
ns
ns
ns
ns
12
11
ns
ns
12
K Clock9
To CLB output
Additional for Q returning
through F or G to CLB out
Logic-input setup
Logic-input hold
Data In setup
Data In hold (1)
Enable Clock setup
Enable Clock hold
Clock (high)
Clock (low)
TCKO
TOLO
8
N/A
N/A
TICK
TCKI
TDICK
TCKDI
TECCK
TCKEC
TCH
TCl
2
3
4
S
6
7
11
12
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12
0
8
6
10
0
9
9
ns
ns
ns
ns
ns
ns
ns
ns
Flip-flop Toggle Rate
FClK
N/A
SO
MHz
Application Guidelines, Switching, Internal BuffersB
Clock Buffer
TGCK
N/A
9
ns
TBUF
Data to Output
Three-state to Output
Single Pull-up
Pair of Pull-ups
TID
N/A
8
ns
Tpus
TpLJF
N/A
N/A
34
17
ns
ns
Bidirectional
BIOI
N/A
6
ns
1637TbIlld
Table 1. Electrical Performance Characteristics (Continued)
TSC0097· Rev:03
2-133
•
XC3090B Military Logic Cell Array
Test
Conditions
-55°C ~ Tc ~ +125°C
Vcc = 5.0 V ±10%
Sym
Group A
Subgroups
Limits
Min
Max
Units
Application Guidelines, Switching, IOB8.10
Pad (package pin)
To inputs TClKIN, BClKIN
To inputs DIRECT IN
TPIDC
TplD
I/O Clock
To I/O RI input (FF)
I/O pad-input setup
I/O pad-input hold
To I/O pad.(fast)
I/O pad output setup
I/O pad output hold
Clock (high)
Clock (low)
TIKRI
TPICK
TIKPI
TOKPO
TOOK
TOKO
TloH
TIOl
5
6
11
12
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Output
To pad (enabled fast)
To pad (enabled slow)
TOPF
Tops
10
10
N/A
N/A
14
39
ns
ns
Three-State
To pad begin hi-Z (fast)
To pad valid (fast)
TTSHZ
TTSON
9
8
N/A
N/A
12
20
ns
ns
Master Reset
To input RI
To output (FF)
TRRI
TRPo
13
14
N/A
N/A
35
50
ns
ns
See Fig. 3
N/A
N/A
3
4
1
2
7
5
9
ns
ns
11
ns
ns
ns
ns
ns
ns
ns
ns
30
0
18
15
0
9
9
1637lbll1.
Table 1. Electrical Performance Characteristics (Continued)
Test
Conditions
-55°C::; Tc ~ +125°C
Vcc = 5.0 V ±10%
Sym
Group A
Subgroups
Limits
Min
Max
Units
Application Guidelines, Switching, Master Parallel Mode Programming 8 •11
RClK,
To Address Valid
To Data Setup
To Data Hold
RCLK High
RCLK low
TRAC
TDRc
TRCD
TRcH
TRCl
1
2
3
4
5
See Fig.6
N/A
N/A
N/A
N/A
N/A
0
60
0
600
4.0
200
ns
ns
ns
ns
Ils
1637lbllli
Table 1. Electrical Performance Characteristics (Continued)
TSC0097 Rev:03
2-134
_--,(G)TMRW)________
,....--------oI!1--1
MO/M1/M2
DONEIPROG
(OUTPUT)
INIT
(OUTPUT)
-r~'~®,~[--~--~®TPGW~
___J___~[@TPGI
USER STATE
-
C_LE_A~R!rS-T-A-T-E--------------~;1
II
.
\ r-
PWRDWN
Vee (VALID)
CONFIGURE
____________
-----------------------------------------------~\
rNOTE3 -j
Ir~t------
'V
'- ____ J-,.-
,
CCPD
1637 32
Figure 1. General LCA Waveforms
CLB OUTPUT (X,V)
(COMBINATORIAL)
CLB INPUT (A,B,C,D,E)
CLBCLOCK
14---
@
TCL--~
o
T DICK ----1~
CLB INPUT
(DIRECT IN)
CLB INPUT
(ENABLE CLOCK)
CLBOUTPUT
(FLIP-FLOP)
CLBINPUT
(RESET DIRECT)
CLBOUTPUT
(FLIP-FLOP)
1637 33
Figure 2. CLB Waveforms
TSCOO97 Rev:03
2-135
•
XC3090B Military Logic Cell Array
110 BLOCK (I)
-®-TPID~-[----
110 PAD INPUT
110 CLOCK
(IKIOK)
- - - ,,
tCD
·""'·I-® T I K P I J - - - - - - -
TpICK--...
~---@ TIOL---~--
'ir-----n-110 BLOCK (RI)
110 BLOCK (0)
@TOp
110 PAD OUTPUT
(DIRECn
110 PAD OUTPUT
(REGISTERED)
-----------------~f0
J---rr-0-~-SON----@-~-~j
IIOPADTS
110 PAD OUTPUT
OKPO
T
r
--------~<~----------~~
1637 34
Figure 3, lOB Waveforms
CS11CSO
CS2
\
,,
,
\
/
7
\~------------/~!----
.
,
WRT
DO-D7
CCLK
,
GROUP OF
8 CCLKs
I
,
I
\.
-_.,
RDYIBUSY _______________________ JI I
DOUT
_~x~_~x~
____________
~
Figure 4, Peripheral Mode Waveforms
TSC0097 Rev:03
2-136
1637 35
I:XIU~~X
DOUT
(OUTPUT)
1637 36
Figure 5. Slave Mode Waveforms
AO-A1S
(OUTPUT)
DO-D7
•
ADDRESS n
ADDRESS n + 1
\:
0)
TRAC
----~------------~~-----+~~----BYTE n
~ CD -~'--'of-- ®
TDRC
T RCD
RCLK
(OUTPUT)
CCLK
(OUTPUT)
DOUT
(OUTPUT)
1637 37
BYTE n-1
Figure 6. Master Parallel Mode Waveforms
TSC0097 Rev:03
2-137
XC3090B Military Logic Cell Array
DONEIPROG
(OUTPUT)
_--L../___________________________________ _
RTRIG
~T~~--~r--------
CCLK
RDATA
(OUTPUT)
VALID
1637 36
Figure 7. Program Readback Waveforms
XC3090B Data Sheet Notes
1. Xilinx maintains this specification as a controlled document. To comply with the intent of MIL-STD-883, and to insure the
use of the most recently released device performance parameters, please request a copy of the current revision of this
Table 1 Test Specification (TSC 0097) from Xilinx.
2. No output current loads, no active input or long line pull-up resistors, and with the device configured with the MAKEBITS
'tie" option.
3. PWRDWN transitions must occur during operational Vcc levels.
4. RESET timing relative to valid mode lines (MO, Ml, M2) is relevant only when RESET is used to delay configuration.
5. Configuration must be delayed until the TNlT of all LCA's is HIGH. WRT cannot go active until RDY/BUSY goes High.
6. Readback should not be initiated until configuration is complete.
7. DOUT timing is the same as for slave mode.
8. Testing of the Applications Guidelines is modeled after testing specified by MIL-M-38S1 0/605. Devices are first 100%
functionally tested. Benchmark patterns are then used to measure the Application Guidelines. Characterization data are
taken at initial device qualification, prior to introduction of significant changes, and at least twice yearly to monitor correlation
between benchmark patterns, device performance, XACT software timings, and the data sheet.
9. The CLB K to Q output delay (TCKO) plus the shortest possible interconnect delay is always longer than the Data In hold
time requirement (TCKDI) on the same die.
10. Voltage levels of unused pads must be valid logic levels. Each can be configured with the internal pull-up resistor, configured as a driven output, or driven from an external source.
11. At power-up, Vee must rise from 2.0V to V~ minimum in less than 10 ms. Otherwise, delay configuration using RESET.
12. All timings except TTSHZ and TTSON are measured at 1.5 V level with 50 pF minimum load output. For input signals, rise and
fall times are less than 6 ns, with low amplitude = OV, and high = 3V.
TTSHZ is determined when the output shifts 10% (of the output voltage swing) from VOL level or VOH level. The following
circuit is used:
fuC
vCC
1K
PAD
SOp! MIN 1 1 K
GND
1637 39
12. (continued)
TTSON is measured at 0.5 Vee level with VIN = 0 for Tri-State to active high, and VIN = Vee for Tri-State to active low. The
following load circuit is used:
~VIN
~_.1
SOp! MIN
I
-II<
1637 40
Tse0097 Rev:03
2-138
XC1736 Serial
Configuration PROM
Product Specification
vPP
FEATURES
• One-Time Programmable (OTP) 36,288 x 1 bit serial
memory designed to store configuration programs for
Programmable Gate Arrays
PROGRAMMING
DATA SHIFT
REGISTER
• Simple interface to a XILINX logic CellTM Array (lCA)
requires only two I/O pins
• Daisy chain configuration support for multiple lCAs
• Cascadable to provide more memory for additional
configurations or future higher-density arrays
24
• Storage for multiple configurations for a single logic Cell
Array
ROW
DECODER
• low power CMOS EPROM process
• Space-efficient, 8-pin plastic/ceramic DIP package
• PC-based Xilinx programmer for development. Production programming support from leading programmer
manufacturers
DESCRIPTION
The XC1736 Serial Configuration PROM (SCP) provides
an easy-to-use, cost-effective configuration memory for
the Xilinx family of programmable gate arrays. Packaged
in an economical8-pin plastic DIP package, the XC1736
uses a simple serial access procedure to configure one or
more logic Cell Arrays (lCAs). The 36,288 x 1 organization of the configuration PROM supplies enough memory
to configure three XC2064's, two XC2018's, two
XC3020s, one XC3030 or one XC3042. Multiple Serial
Configu ration PROMs can be cascaded to provide a larger
memory for higher density arrays. Mu Itiple configurations
for a single lCA can also be loaded from the XC 1736.
The XC1736 can be programmed with the PC-based Xilinx
XC-DSl12 Configuration PROM Programmer orwith programmers from other manufacturers. The logic Cell Array
design file is first compiled into a standard HEX format with
the XC-DS21 Development System. It can then be transferred to the XC-DSl12 programmer connected to the
serial port.
ClK
DATA
RESET/DE
1106905
Figure 1. XC1736 Block Diagram
DATAU8 VCC
ClK
2
7
vpp
RESET/OE
3
6
CEO
CE
4
5
GND
11069 04
XC1736 Pin Assignments
2-139
II
XC1736 Serial Configuration PROM
Table 1. XC1736 Pin Assignments
Pin Name
DATA
2
3
4
ClK
RESETI
OE
CE
5
GND
6
CEO
Description
1/0
0 Three-state DATA output for reading.
Input/Output pin for programming.
DOUT
CClK
M2
HDC
lDC
Clock input. Used to increment the
internal address and bit counters for
reading and programming.
GENERAL·
PURPOSE
USER 1/0
PNS
Output Enable input. A lOW level on
both the CE and OE inputs enables
the data output driver. A HIGH level on
RESET/OE resets both the address
and bit counters.
Chip Enable input. A lOW level on
both CE and OE enables the data
output driver. A HIGH level on CE disables both the address and bit counters and forces the device into a low
power mode. Used for device
selection.
Ground pin.
0 Chip Enable Out output. This signal is
asserted lOW on the clock cycle
following the last bit read from
the memory. It will stay lOW as long as
CE and OE are both lOW. It will follow
CE, but if OE goes HIGH, CEO will
stay HIGH until the entire PROM is
read again.
7
VPP
Programming Voltage Supply. Used
to enter programming mode (+6V) and
to program the memory (+21V) Must
be connected directly to VCC for
normal read operation. No overshoot
above +22V permitted.
8
Vcc
+5 volt power supply input.
2-140
} ADDITIONAL
SLAVE MODE
lCAs (OPTIONAL)
)~
OTHER
PINS
RESET
LOGIC
CELL
ARRAY
+5V
DIN
CClK
DIP
Vpp
Vee
DATA XC1736
ClK
SERIAL
CONFIG·
CE
URATION
PROM
OE
1106 06
Figure 2. Master Serial Mode Configuration
E:XIUNX
LCA MASTER SERIAL MODE SUMMARY
CCLK will clock data out of the SCP on every rising clock
edge. At the completion of configuration, the DONE!
PROG signal will go high and reset the internal address
counters of the SCPo
The I/O and logic functions of the Xilinx Programmable
Gate Array, and their associated interconnections, are
established by a configuration program. The program is
loaded either automatically upon power up, or on command, depending on the state ofthe three LCA mode pins.
In Master Mode, the Logic Cell Array automatically loads
the configuration program from an external memory. The
Serial Configuration· PROM has been designed for compatibility with the Master Serial Mode.
If the user-programmable, dual function DIN and CCLK
pins are used only for the configuration process, they
should be programmed on the LCA so that no nodes are
floating or in contention. For example, both DIN and CCLK
can be programmed as output highs during normal operation. An alternate method is to program both DIN and
CCLK as inputs, with external pullup resistors attached.
Upon power-up or upon reconfiguration, an LCA will enter
Master Serial Mode whenever all three of the LCA's mode
select pins are LOW (MO=O, M1=O, M2=O). Data are read
from the Serial Configuration PROM sequentially on a
single data line. Synchronization is provided by the rising
edge of the temporary signal CCLK, which is generated
during configuration.
If DIN and CCLK are to be used for another function after
configuration, the user must avoid contention. The Low
During Configuration (LDC) pin can be used to control the
SCP's CE and OE inputs to disable the SCP's DATA pin 1
clock cyCle before Dip is active.
If the LCA is to be reprogrammed after .initial power-up,
note that the LCA requires several microseconds to respond after.the DiP pin ispulled low. In this case, the LOC
pin can be used instead of the DIP pin to control the SCP.
Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are
required to configure an LCA. Data from the Serial Configuration PROM is read sequentially, accessed via the
internal address and"bit counters which are incremented
on every valid rising edge of CCLK.
Programming The LCA With Counters Unchanged
Upon Completion
.
Programming The LCA With Counters Reset UpIIi\'3.(lo
,!\'o(e
'P'<»\\
1'\\'3.(1\'3.
"(O(i(lO
\,\'3.i\'3.
?'3.00-J'3.
Users' Group meetings are intended for experienced
users of Xilinx Programmable Gate Arrays, and emphasize the use of the various development system tools to
generate LCA~based designs,
Xilinx sponsors technical seminars at locations throughout
North America, Europe, and Asia.
Product-oriented seminars are directed toward new and
potential users of Programmable Gate Arrays, These
seminars include a basic description of the Logic Cell
Array architecture and its· benefits of· this technology,
Experienced users will also find these seminars useful fOf
learning about newly-released products from Xilinx.
Contact your local Xilinx sales office, sales representative,
or distributor for information about seminars in your area.
4-1
•
Videotapes
A one-hour videotape, entitled "Programmable Gate Arrays: The Ideal Logic Device," is available from Xilinx. The
presentation is divided into three main sections. The first
portion of the videotape is an overview of the Logic Cell
Array architecture and the development system, including
some example applications. The second section contains
a description of the Xilinx product families, a more detailed
description of the XC3000 series architecture, a description of the LCA configuration modes, and a brief discussion
of programmable gate array performance in terms of
speed, density, and cost. Development systems and the
design methodology are discussed in the last third of the
presentation, including on-screen demonstrations of
some of the software tools. Additional videotapes covering specific details are in preparation.
VHS copies are available in NTSC, PAL, and SECAM
formats; contact your local Xilinx sales office, sales representative, or distributor.
4-2
Newsletter
II
customersPP~h~p-to-date
m~
~eas
aVls"lne~sletterinform~tio~erlyteChnical~n~ew:s-;-~;:;;;~ds":~~=:-----·
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InSeptember'8
"" started a ua
letter
to su
8 Xlhnx
;and
1 softwa"re a,.b""" d gives uPdtotregistered
a es 0" hardXilinx
n ormation on PC I
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c one compatibility
"also carries
_ ________________
01
,,'evam
aod
.
work-arounds
App r"",110",
of informatl"on fgazlne
articles make thO r user
andLCA
a list
uSingtiPS
Xilinx
s"
or the
IS a val b
__________
4-3
Xilinx Technical
Bulletin Board
..,.,,,.
~r_
The file section is divided into
several areas. Enter this
sectio~6~~~;~d ~~!~~d and
TYPE:
E
~~~":TI~
'IIVN
Enter this section to send and
receive messages.
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To send a message.
G)OODBYE
At this time you can leave a
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Enter this section to read the
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A list of bulletins is automatically displayed.
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systems or upload files to the XTBB. They can also leave
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To provide customers with up-to-date information and an
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4-4
E:XILINX
The XTBB is based on a bulletin board system called
FIDO. FIDO is a menu-driven system-you choose commands from menus to decide what happens next. To
choose a menu command, simply type the first letterof the
command and press return . Listed below are some
helpful hints for using the XTBB ..
New bulletin board users must answer a questionnaire
when they first access the XTBB. After answering the
questionnaire callers can browse through the bulletin and
general information file areas. Before exiting, they should
leave a message for the system operator requesting full
access. A caller with a valid XACT protection key will be
given full user privileges within 24 hours.
• To perform a sequence of commands, type the firstletter
of each command, followed by a space, and press
return. For example, typing F A 1 F [F)ile A)rea
1 F)iles] from the main menu will list all of the files
contained in file area 1.
The software and hardware requirements for accessing
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Baud Rate
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1200 or 2400
8 data bits, no parity, 1 stop bit
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• Often the user is asked a question and prompted to
choose between two options (e.g. [yes NO]). The option
displayed in all capital letters is the default choice. To
select this option, simply press return. Otherwise, type
your choice and hit return.
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Information contained on the XTBB is divided into three
general categories: 1. Bulletins, 2. Files and 3. Messages.
• The XTBB has an extensive help section. To get help,
type ?. If you have questions about a specific command, type the first letter of the command followed by a
question mark and a carriage return (e.g.F? .. ROO
~--------------~--------~PALASM
Text File
Logic Synthesis
Program Optimizes
for LCA Architecture
I
Optimized XNF Files
Partitions and Maps Collection
of Gate Level Logic into CLBs
and lOBs. Unused Logic Removed.
LCA Interactive Layout
Graphical Editor and
Automated CLB & lOB
Placement and Routing
within
TimingLCA;
Report Generation'--L!::==~==:~=~=~r-...1
nmr
C./coi"M
CLB-Ievel Netlist
with Timing Delays
to Interface with
Logic Simulators
roTarget _______________________________
~
System
Containing LCA
195201
195201
Software Included in XC-DS501
5-35
•
XC-DS31 FutureNet DASH™
Schematic Entry Interface
and Design Library
Product Brief
FEATURES
• Library and translator for users with the FutureNet
DASHTM Schematic Designer
• Macro library of over 100 standard logic family
equivalents derived from the XACTfM Macro Library
• Library of logic symbols including all two-input, threeinput and four-input AND, OR and XOR gates plus
storage, inpuVoutput and clock elements
• User control for flagging critical paths for the
Automated Placement and Routing keep
• Converts schematic drawings to a Xilinx Netlist
Format (XNF) output file
• Output compatibility with XC-DS501 XACT Design
Implementation System
the schematic. A Xilinx conversion utility converts the
schematic into an XNF output file.
Once partitioned, the design may be placed and routed
with the PC-based XC-DS501 XACT Design
Implementation System.
The Xilinx symbol library
includes symbols to flag critical data and clock signals
which the Automatic Placement and Routing Program
uses to prioritize those signals for minimum delay.
Xilinx provides ongoing support for users of the FutureNet
DASH Schematic Designer Library. For the first year,
software updates are included. After that, the user may
purchase the XC-SC31 Annual Support Agreement to
continue to receive the latest software releases.
• Runs on an IBM'" PC/ATTM or compatible personal
computer
GENERAL
Schematic entry and automatic partitioning of Logic Cell
Array designs shortens logic reduction and product
development times. Complex designs can be specified
schematically and quickly implemented for in-circuit
design verification.
Xilinx's FutureNet DASH Schematic Designer Library provides the symbol library and conversion utility to permit
designers to enter Logic Cell Array designs with the
FutureNet DASH Schematic Designer. The Xilinx library
provides the logic, I/O, and macro symbols to be used in
1964
5-36
XC-DS311
7400 TTL Library for FutureNet
DASH and DASH-LCA
Product Brief
FEATURES
74151
74152
74153
74154
74157
74158
74160
74161
74162
74163
74164
74166
74168
74169
74174
74179
74194
74195
74198
74199
74240
74241
74244
74245
74257
74258
74259
74273
74278
74280
74283
74298
74352
74373
74374
74377
74390
74393
74518
74521
74540
74541
74577
8-lnput Multiplexer
8-lnput Multiplexer
Dual4-lnput Multiplexer
1-of-16 Decoder/Demultiplexer
Quad 2-lnput Multiplexer
Quad 2-lnput MuHiplexer
Presettable Decade Counter
Presettable Binary Counter
Presettable Decade Counter w/ Sync Clear
Synchronous Binary Counterw/ Sync Clear
Serial-In, Parallel-Out Shift Register
Parallel Load 8-Bit Shift Register
4-Bit BCD Synchronous Up/Down Counter
4-Bit Binary Synchronous Up/Down Counter
Hex 0 Flip-Flop with Master Reset
4-Bit Parallel Access Shift Register
4-Bit Bidirectional Universal Shift Register
4-Bit Parallel Access Shift Register
8-Bit Bidirectional Shift Register
8-Bit Shift Register with Clock Inhibit
Octallnv Buffer, Three-State Outputs
Octal Non-Inverting Three-State Buffers
Octal Non-lnv Buffer, Three-State Outputs
Octal Bidirectional Transceiver
Quad 2-lnput Multiplexer
Quad 2"lnput Multiplexer
8-Bit Addressable Latch
Octal 0 Flip-Flop
4-Bit Cascadable Priority Register
9-Bit Parity Checker/Generator
4-Bit Binary Full Adder
Quad 2-lnput Multiplexer with Storage
DuaI4-to-1 Da.ta Selector/MultipleXer
Octal Latchwith Three-State Outputs
Octal 0 Flip-Flops with Three-State Outputs
Octal. 0 Flip-Flop with Clock Enable
Dual4-Bit Decade Counters with Clear
Dual4-Bit Binary Counters with Clear
8-Bit Indentity Comparator
8-Bit Indentity Comparator
Octallnv Buffer, Three-State Outputs
Octal Non-Inv Buffer, Three-State Outputs
Octal 0 Flip-Flops with Reset a.nd Three-State
Outputs
74590 8-BitBinary Counter with Output Register
74595 8-Bit Shift Register with Output Register
• Over 507400 TIL library elements for use with
FutureNet DASHTM Schematic Designer
• Permits XC3000 family Logic CeUTM Array design
using familiar 7400 MSI functions
• Supports XC-DS531 PGA Development Systems with
FutureNet DASH-LCA
GENERAL
The XC-DS311 7400 TIL Library is a set of over 50
FutureNet DASH logic symbols for schematic entry of
Logic Cell Array (LCA TM) designs. The library can be used
with the XC-DS531 Development System, or with the
FutureNet DASH Schematic Designer and XC-DS31
Future Net DASH Schematic Interface and Library. Use of
the XC-DS-311 Library· allows the designer to enter
compleX programmable gate array designs in terms of
familiar TIL functions.
The XC-DS311TIL Library supplements the library of
more than 100 logic elements that are included with
XC-DS531.
Xilinx provides ongoing support for XACTusers. For the
first year, software updates (such as support for new
devices) are included at no charge. After that, users may
purchase the XC-SC311 to continue receiving software
updates. In addition, Xilinx operates a technical support
telephone hotline and an electronic bulletin board to
provide software enhancements and factory support.
LIST OF TTL MACROS
7442
7448
7477
7483
7485
74125
74138
74139
74147
74148
4-10-10 Line Decoder
BCD-to~Seven-Segment Decoder
4-Bit Latch
4-Bit Binary Adder With Fast Carry
4-Bit Magnitude Comparator
Quad Three-State Bus Buffer
1-of-8 Decoder/Demultiplexer
Dual1 cof-4 Decoder
10-to-4 Line Priority Encoder
8-to-3 Line Priority Encoder
1957
5-37
•
XC-DS32 Schema II
Schematic Entry Interface
and Design Library
Product Brief
FEATURES
Once partitioned, the design may be placed and routed
with the PC-based XACT Design Implementation System.
The Xilinx symbol library includes symbols to llag critical
data and clock signals which the Automatic Placement and
Routing Program uses to prioritize those signals for
minimum delay.
• Library and translator for users with the Schema II
Schematic Editor
• Macro library of over 100 standard logic family
equivalents derived from the XAC"fTM Macro Library
• Library of logic symbols including all two-input, threeinput and four-input AND, OR and XOR gates plus
storage, input/output and clock elements
Xilinx provides ongoing support for users of the Schema II
Schematic Entry Interface. For the first year, software
updates are included. After that, the user may purchase
the XC-SC32 Annual Support Agreement to continue to
receive the latest software releases.
• User control for flagging critical paths for the
Automated Placement and Routing Program
• Converts schematic drawings to a Xilinx Nellist
Format (XNF) output file
,------------------,
• Output compatibility with XACT Design
Implementation System
SCHEMA II EDITOR
SCHEMA
• Runs on an IBM~ PCIApM or compatible personal
computer
_________ .J
GENERAL
---------,
Schematic entry and automatic partitioning of Logic Cell
Array designs shortens logic reduction and product
development times. Complex designs can be specified
schematically and quickly implemented for in-circuit
.
design verification.
I
I
I
XC-DS32 I
SCHEMA II I
INTERFACE I
I
I
I
I
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .J
XILINX NETLIST
FORMAT
Xilinx's Schema II Schematic Entry Interface provides the
symbol library and conversion utility to permit designers to
enter Logic Cell Array designs with the Schema II
Schematic Editor. The Xilinx library provides the logic,
1/0, and macro symbols to be used in the schematic. A
Xilinx conversion utility converts the schematic into an
XN F output file.
To Xilinx XC-DS501
Design Implementation System
5-38
196501
XC-DS33 Daisy Schematic
Entry Interface, Library,
Unit-Delay Simulation
Product Brief
FEATURES
• Schematic entry via the Daisy OED II and ACE
Schematic editors
• Unit-delay simulation with Daisy simulator
• Macro library of over 100 standard logic family
equivalents derived from the XAC"fTM Macro Library
• Library of logic symbols including all two-input, threeinput and four-input AND, OR and XOR gates plus
storage, inpuVoutput and clock elements
• User control for flagging critical path;s for the
Automated Placement and Routing Program
• Converts schematic drawings to a Xilinx Netlisi
Format (XNF) output file
• Output compatibility with XC-DS501 XACT Design
Implementation System
Once partitioned, the design may be placed and routed
with the PC-based XC-DS501 XACT Design
Implementation System.
The Xilinx symbol library
includes symbols to flag critical data and clock signals
which the Automatic Placement and Routing Program
uses to prioritize those signals for minimum delay.
Xilinx provides ongoing support for users of the Daisy
Schematic Interface. For the first year, software updates
are included. After that, the user may purchase the
XC-SC33 Annual Support Agreement to continue to
receive the latest software releases.
DAISY SYSTEM REQUIREMENTS
Any Daisy workstation listed on the chart on the next page
can be used to produce a design netlist in the Xilinx Netlist
Format using a utility provided with the library.
GENERAL
Schematic entry and automatic partitioning of Logic Cell
Array designs shortens logic reduction and product
development times. Complex designs can be specified
schematically and quickly implemented for in-circuit
design verification.
Xilinx's Daisy schematic i.nterface provides the symbol
library and conversion utility to permit designers to enter
Logic Cell Array designs with either OED II or ACE on
Daisy workstations. The Xilinx library provides the logic,
I/O, and macro symbols to be used in the schematic. A
Xilinx utility converts the Daisy format to an XNF output file.
An IBM PC/AT equipped with the XC-DS501 Design
Implementation System is then used to physically
implement the design in an LCA.
PC/AT-based Daisy workstations (such as the Daisy
ENTRY system) can have the XC-DS501 software
installed in the PC's DOS partition. Designers using •
non-PC/ATworkstations can transfer the schematic netlist
to an MSDOS floppy and complete the LCA physical
design on a PC/AT computer.
Personal LOGICIAN® and LOGICIAN® are registered
trademarks of Daisy Systems Corporation.
1967
5-39
XC·DS343 Mentor Interface
Schematic Entry, Timing
Simulation Interface, and Library
Product Brief
FEATURES
• Mentor certified
• Mentor IDEA® Station can be used for schematic
entry and simulation of programmable gate array
designs
• Simulation with post placement/routing LCA timing
• Macro library includes over 100 standard logic
elements (counters, multiplexers, registers, etc.)
• Primitive library includes flip-flops, latches, AND, OR,
XOR, NAND, NOR gates
• Xilinx Netlist Format (XNF}output is compatible with
XC-DS501 Design Implementation System
GENERAL
The Xilinx XC-DS343 Mentor Interface allows designers
to use their Mentor IDEA Station to enter and simulate
programmable gate array schematics. The Logic Cell™
Array library includes over 100 macros for commonly used
counters, registers, multiplexers, etc.
The resulting Mentor design files are then processed
using Xilinx's XC-DS501 Design Implementation System,
which permits rapid design development and real-time
in-circuit design verification.
Xilinx provides ongoing support for users of the Mentor
Interface. Forthe first year, software updates are included.
After that, the user may purchase the XC-SC343 Annual
Support Agreement to continue to receive the latest
software releases.
Xilinx also maintains a Technical
Hotline and an electronic bulletin board to provide technical
product support to LCA users.
SYSTEM REQUIREMENTS
Mentor IDEA V6.0 or greater is required for schematic
entry and simulation. The XC-DS343 Mentor Interface
software requires the APOLLO SR9.6 or DOMAIN/IX
operating system.
File transfer from the Mentor system to other PC-based
Xilinx software may be accomplished using any existing
PC/Apollo link, such as the DOMAIN/PC I software
available from Mentor and Apollo.
The XC-DS501-AP1 Developement System is partially
resident on Apollo (DN3000, DN3500, DN4000, and
DN4500) and IBM PC System platforms. The Mentor
interface, Automated Placement/Routing, timing analysis,
and bitstream compilation are resident on the Apollo
system, while the XACT Design Editor is currently resident
on the IBM PC system.
1958
5-40
DESIGN
VERIFICATON
DESIGN ENTRY
r-----------------------~A~
STATE MACHINE
LANGUAGE
__________________________
MENTOR GRAPHICS
NETED/SYMED
BOOLEAN
EQUATIONS
II
~-----'A'-----________.,
I
QUICKSIM LOGIC &
TIMING SIMULATION
1~
I I
'---
-
r-I
,
7
1\
I
:
F
NETLIST
TRANSLATION
------
-
I
/
J~
XC·DS343
MENTOR
INTERFACE
/ - ANNOTATED
NETLIST CREATION
I
I
I
L _____
D ESIGN
IMPLEMENTATION
,-----------I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-------------------------~
AUTOMATIC
PLACE AND ROUTE
V'
------ --I
------------------------,
XC·DS501 XACT
DESIGN IMPLEMENTATION
SYSTEM
LOGIC SYNTHESIS
MAP TO LCA
l~
-,
~t
f>.
I'\r---v1
INTERACTIVE
PLACE AND ROUTE
I I
II
*
POST ROUTE TIMING
ANALYSIS AND REPORTS
I I
• SHIPPED ON PC WITH UPGRADE
TO APOLLO WHEN AVAILABLE
LCA CONFIGURATION &
PROM FILE GENERATION
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
L _____________________________ - - - - - - - - - - I
1958 02
Xilinx LCA Design Flow on Mentor Graphics Workstations
5·41
•
XC-OS35 OrCAO SOT
Schematic Entry Interface
Product Brief
Once partitioned, the design may be placed and routed
with the PC-based XACT Automated Design
Implementation Program. The Xilinx symbol library
includes symbols to flag critical data and clock signals
which the Automatic Placement and Routing Program
uses to prioritize those signals for minimum delay.
FEATURES
• Library and translator for users with the OrCAD SDT
Schematic Editor
• Macro library of over 100 standard logic family
equivalents derived from the XACTfM Macro Library
• Primitive library of logic symbols includes all twoinput, three-input and four-input AND, OR and XOR
gates plus storage, input/output and clock elements
Xilinx provides ongoing support for users of the OrCAD
Schematic Entry Interface. For the first year, software
updates are included. After that, the user may purchase
the XC-SC35 Annual Support Agreement to continue to
receive the latest software releases.
• User control for flagging critical paths for the
Automated Placement and Routing Program
• Converts schematic drawings to a Xilinx Netiist
Format (XNF) output file
,------------------,
• Output compatibility with XACT Design Implementation System
I
OrCAO SOT III
I
• Runs on an IBM®PC/ApM or compatible personal
computer
GENERAL
Schematic entry and automatic partitioning of Logic Cell
Array designs shortens logic reduction and product
development times. Complex designs can be specified
schematically and quickly implemented for in-circuit
design verification.
Xilinx's OrCAD Schematic Entry Interface provides the
symbol library and conversion utility to permit designers to
enter Logic Cell Array designs with the SDT Schematic
Editor. The Xilinx library provides the logic, 1/0, and macro
symbols to be used in the schematic. A Xilinx conversion
utility converts the schematic into an XNF output file.
To Xlllnx XC·OSSOl
Oeslgn Implementallon System
5-42
_ 196601
XC-DS3S1 OrCAD VST
Simulator Interface
.
Product Brief
FEATURES
• Model library and netlist translator for users of the
OrCAD VST Simulator
• Supports full timing simulation of routed LCA designs,
and unit-delay simulation of unrouted designs
• Permits simulation of schematics which include PAL
logic defined with PALASM, ABEL, CUPL, Log/IC, or
PLDesigner.
Input compatible with XACT Design Implementation
System
• Includes unique automated Trace and Stimulus file
generation
in an unplaced and unrouted design. This saves design
time because logic errors can be detected and corrected
prior to final placement and routing. After a circuit has
been placed, routed and then fully debugged using
in-circuit emulation, worst case timing may be verified.
This enables the user to select the correct Logic Cell Array
speed grade for a particular application.
Network inputs for Logic Cell Array designs are
automatically created by the XNF2VST utility from the
XNF output of the XACT Design Implementation System.
The network includes logic and routing delay parameters
and setup and hold times based upon the selected speed
grade operating under worst case conditions.
• Runs on an IBM PC/AT or compatible personal
computer
GENERAL
r---XC·OS351
OrCAD VST
Simulation is particularly useful for testing designs or
design segments as well as for verifying critical timing over
worst case power supply, temperature and process
conditions.
Simulator
Interface
From XC-DS501 XACT
Simulation is useful in several stages of the design cycle.
After design entry, simulation may be used to debug logic
Design Implementation System
1970 01
5-43
XC-DS22 and XC-DS221
PC-SILOSTM Simulators
Product Brief
FEATURES
• PC based simulator for LCA design verification
• Simulates any LCA design, regardless of design input
format (combined logic schematics, Boolean equations, and state machine descriptions)
• General purpose event driven logic and timing
simulator
• Input automatically generated from XNF file
• Control and observation of any physical circuit node
• Multiple file input for vectors and commands
• Interactive or batch mode operation
in-circuit emulation, worst case timing may be verified.
This enables the userto select the correct Logic Cell Array
speed grade for a particular application.
Network inputs for Logic Cell Array designs are
automatically created by the XNF2SILO utility. The
network. includes logic and routing delay parameters and
setup and hold times based upon the selected speed
grade operating under worst case conditions. Simulation
stimuli are created with a set of clock statements orwith an
input pattern for either pad inputs or internal nodes.
Simulation results are available in tabular, plotted and
graphic formats. This flexibility makes the "logic debug"
easy for both the circuit function and timing.
• Output available in printed or tabular formats
• Runs on an IBM®PC/AT'" or compatible personal
computer
• Simulates logic complexities up to 16,000 gates
(OS22) or 5,000 gates (OS221)
GENERAL
PC-SILOS is a powerful PC based simulatorthat provides
event driven logic and timing simulation of Logic Cell™
Array designs. Simulation is particularly useful for testing
designs or design segments as well as for verifying critical
timing over worst case power supply, temperature and
process conditions.
Simulation is useful in several stages of the design cycle.
After design entry, simulation may be used to debug logic
in an unplaced and unrouted design. This saves design
time because logic errors can be detected and corrected
prior to final placement and routing. After a circuit has
been placed, routed and then fully debugged using
195~
5-44
XC-OS112 Configuration
PROM Programmer
Product Brief
FEATURES
The programming unit connects to a serial port of an IBM
PC/AT or compatible and is controlled using PC-based
software included with the XC-DS112.
• Programs XC1736 Serial Configuration PROM
• Connects to serial port of IBM PC/AT or compatibles
• Operates from PC via software provided with
programming unit
• Accepts HEX format data files created by the DS501
XACT Design Implementation System
Designers compile their Logic Cell Array designs into a
standard HEX format file USing the PC-based XACT
development system.
The· programming software
provided with the XC-DS112 is then used to download the
HEX file into the programming unit and program a
XC1736.
GENERAL
Designers using the Xilinx XC1736 Serial Configuration
PROM-an 8-pin mini-DIP PROM used to configure
programmable gate arrays-can program the XC 1736
with the XC-DS112 Configuration PROM Programmer.
XC-DS112
PROGRAMMER
Since the XC-DS112 software is separate from the XACT
software, the XC-DS112 software and programming unit
can be installed on a PC otherthan the oneusedfordesign
development-such as a PC located in a manufacturing
area.
PC
(0625 RECEPTACLE)
(OB25 PLUG)
TxD (FROM PC)
RxD (TO PC)
RTS
CTS
.. 6 DSR
7 GND
.. 8 DCD
20 DTR
2
••- - - - 2
3
[4
5
.. 3
4
.. 5
•
+V -'VV"- 6
GND 7 •
[ ·8
20.
•
196001
XC-DS112 Interface to PC
1960
5-45
XC-DS26, XC-DS27, XC-DS28
XACTOR™ In-Circuit
Design Verifier
Product Brief
FEATURES
• Real time in-circuit verification in user's target system
• Concurrent emulation of up to four devices
• Readback and display of Logic Cell™ Array internal
storage element states
• Device status display with automatic update of
asynchronous events
• Control and I/O pin isolation from target system
• Support for daisy chain programming of up to seven
devices in a daisy chain
.
• Support for multiple device and package types
• Runs on an IBM® PC/ATTM or compatible personal
computer
GENERAL
The XACTORTM real-time in-circuit design verifier
provides interactive target system emulation of up to four
Logic Cell Arrays from the host PC system. In-circuit
"debug" provides a powerful productivity enhancement to
simulation, providing capabilities to verify functionality in
the target system at full speed with all other circuits and
system software.
device isolation and configuration is controlled with mouse
or keyboard commands and may be supplemented with
user-defined setup files for easy system debugging.
Readback of device configuration may be performed on
command for verification of the configuration process and
interrogation of the internal states. The state of all internal
storage elements is displayed after readback has been
performed. Status displays showing the state of all
isolation switches and control signal states are provided.
The status display includes automatic reporting of
asynchronous status changes in the target system.
UNIVERSAL IN-CIRCUIT EMULATOR PODS
Additional pods may be connected to the XACTOR
controller, up to a maximum of four pods per controller.
Pod headers are interchangeable for different device and
package types. Each pod provides a direct in-socket
connection without disruption of the target system. Test
points are provided to allow connection of a logic analyzer
or other test equipment to aid in the system debugging.
The design verifier is composed of a microcomputerbased controller, and from one to four universal emulation
pods, each with an emulation header. The controller is
connected to the host PC through a serial port and
provides local storage of configuration programs, control
of individual device configurations, and control of the
isolation of the pod device(s) from the target system. The
user can set the state and isolation for each of the control
signals to provide debugging of target hardware. Four
general 110 pins are available to provide test points which
may also be isolated from the target system.
Target Logic Cell Arrays can be programmed individually
or in a daisy chain. Daisy chains of up to seven devices
may be supported from any of the four pods. Individual
1968
5-46
Development Systems
Ordering Information
Further information is available from your local distributor
sales office or the nearest Xilinx sales representitive.
ORDERING GUIDELINES
To design with XilinxTM programmable gate arrays, designers should have as a minimum:
• XC-DS501 XACTTM Design Implementation System, plus
• LCA Interface and library for their schematic editor
(see DS300 Optional Libraries and Interfaces, below)
PC-based designers who wish to use the Xilinx-provided FutureNet® DASH-LCA schematic editor can purchase all of
the above from Xilinx as the "XC-DS53 XACT Design Implementation System with FutureNet DASH-LCA."
Workstation-based DS501 customers will initially received the PC version of the interactive XACT Design Editor; the
workstation version of the XACT Design Editor will be provided as a no charge upgrade when available.
DS500 DESIGN IMPLEMENTATION DEVELOPMENT SYSTEMS
XC-DS501
XC-SC501
XACT Design Implementation System for IBM PC/AT
Annual Software Support Agreement
Bundled system equivalent to DS21 plus DS23-contains graphical interactive LCA editing tool
plus all non-graphical, automated implementation tools.
• Design Manager provides convenient front-end for all Xilinx programs
• Accepts any combination of schematic netlists (XNF format) and PALASM-compatible text files
(also accepts input form ABEL, CUPL, PLDesigner, and Log/IC)
• Automatic placement and routing program reduces design implementation time
• LogiC synthesis software efficiently optimizes designs for LCA
• Automatically eliminates unused, disabled logic
• Bitstream compiler compiles design into LCA programming bitstream
• Graphical LCA design editor permits interactive editing of design placement/routing
• Download cable facilitates in-circuit debugging of LCA designs
XC-DS501-AP1
XC-SC501-AP1
XACT Design Implementation System for Apollo workstation and PC/AT
Annual Software Support Agreement
XC-DS501-SN1
XC-SC501-SN1
XACT Design Implementation System for Sun® 3 workstation and PC/AT
Annual Software Support Agreement
AP1 and SN1 versions contain PC-based XACT Design Editor and workstation-based
enhanced automated design implementation software (includes bitstream compiler). Designer
must have access to a PC/AT to run the XACT Design Editor for interactive placement/routing
editing. An update to the workstation version of XACT Design Editor will be shipped when
available.
• Accepts any combination of schematics netlists (XNF format) and PALASM-compatible text
files (also accepts input from ABEL, CUPL, PLDesigner, and Log/IC)
• Automatic placement and routing program reduces design implementation time
• Logic synthesis software efficiently optimizes designs for LCA
• Automatically eliminates unused, disabled logic
• Bitstream compiler generates LCA programmable bitstream on workstation system.
5-47
•
Development Systems
DS500 DESIGN IMPLEMENTATION DEVELOPMENT SYSTEMS (Con't)
XC-DS53
XC-SC53
XACT Design Implementation System with FutureNet DASH-LCA
Annual Software Support Agreement
Includes al/ software required to enter programmable gate array schematics, place/route
designs, and compile designs into configuration bitstreams to program LCA devices
Includes DS501 XACT Design Implementation System plus a FutureNet DASH-LCA schematic
editor (a version of FutureNet DASH4 solely for LCA designs) plus a DS31 FutureNet library
and interface
Design Manager provides convenient front-end for all Xilinx programs
Includes support for PALASM®-compatible Boolean equation entry
(also accepts input from ABEL, CUPL, PLDesigner, and Log/IC)
Runs on IBM® PC/ATTM or compatible
DS100 OPTIONAL HARDWARE PRODUCTS
XC-DS112*
XC-SC112
Enhanced Serial Configuration PROM Programmer
Annual Software Support Agreement
DS200 OPTIONAL DESIGN IMPLEMENTATION & VERIFICATION TOOLS
XC-DS21
XC-SC21
XACT Design Editor for IBM PC
Annual Software Support Agreement
• Graphics-based interactive LCA design editor
• Timing calculator, bitstream compiler, and macro library
• Download cable, demo board and 2 LCA devices
XC-DS23
XC-SC23
Automated Design Implementation (A.D.I.) software for IBM PC
Annual Software Support Agreement
• Accepts any combination of schematic netlists (XNF format) and PALASM-compatible text files
• Logic synthesis software efficiently optimizes designs for LCA
• Automatically eliminates unused, disabled logic
• Automatic placement and routing program reduces design implementation time
XC-DS22
XC-SC22
P/C-SILOSTM Simulator (16,OO(), gates) with LCA interface
Annual Software Support Agreement
XC-DS221
XC-SC221
P/C-SILOSTM Simulator (5,000 gates) with LCA interface
Annual Software Support Agreement
XC-DS28
XACTORTM In-Circuit Design Verifier (Controller Hardware and Software)
Order one XC-DS28 Controller, from one to four XC-DS26 Emulation Pods, and one XC-DS27
Emulation Header (of desired package type) per Emulation Pod
•
•
•
•
Runs on IBM PC/AT or compatible (connects to serial port)
Controller supports up to four XC-DS26 Emulation Pods
XC-DS26 Emulation Pod accepts any XC-DS27 Emulation Header
XC-DS27 Emulation Header connects Emulation Pod to LCA socket in target system
XC-DS26
Emulation Pod for XACTOR (accepts any XC-DS27 Emulation Header)
XC-DS27-PD48
XC-DS27-PC68
XC-DS27-PG68
XC-DS27"PC84
XC-DS27-PG84
XC-DS27-PG132
XC-DS27-PC175
Emulation
Emulation
Emulation
Emulation
Emulation
Emulation
Emulation
Header,
Header,
Header,
Header,
Header,
Header,
Header,
48 Pin DIP package
68 PinPLCC package
68 Pin Grid Array package
84 Pin PLCC package
84 Pin Grid Array package
132 Pin Grid Array package
175 Pin Grid Array package
• XC-OS112 is an enhanced version of former XC-OS81 serial configuration PROM programmer
5-48
E:XIUNX
DS300 OPTIONAL LIBRARIES AND INTERFACES
XC-DS31
XC-SC31
FutureNet DASH Schematic Interface and Library
Annual Software Support Agreement
XC-DS311
XC-SC311
TTL Library for FutureNet DASH and DASH-LCA
Annual Software Support Agreement
XC-DS32
XC-SC32
Schema 11+ Schematic Interface and Library
Annual Software Support Agre.ement
XC-DS33
XC-SC33
Daisy® Schematic and Unit-delay Simulation Interface and Library
Annual Software Support Agreement
XC-DS343*
XC-SC343
Mentor®-certified Schematic and Full-timing Simulation Interface and Library
Annual Software Support Agreement
XC-DS35
XC-SC35
OrCAD/SDT® Schematic Interface and Library
XC-DS351
XC-SC351
OrCADIVST® Simulation Interface
Annual Software Support Agreement
XC-MANUAL
Additional Xilinx Development System Documention
• Complete XACT LCA Development System Reference Manuals (Volumes I, II)
• LCA User's Guide Manual (including several Application Notes)
• XACT Macro Library Manual
Annual Software Support Agreement
•
• XC-OS343 is an enhanced version of former XC-OS34 which now includes full timing simulation
5-49
1961
The Programmable Gate Array Company
XC3090 Die
SECTION 6
Applications
1
Programmable Gate Arrays
2
Product Specifications
3
Quality, Testing, Packaging
4
Technical Support
5
Development Systems
6
Applications
7
Article Reprints
8
Index
Applications
Introduction ......................................................................................... 6-1
Estimating Size and Performance ....................................................... 6-3
Incorporating PLD Equations Into LCAs ............................................. 6-7
The XC2000 User's Guide to the XC3000 Family ............................... 6-11
Designing with the XC3000 Family ..................................................... 6-12
Designing with the XC2000 Family ..................................................... 6-13
Additional Electrical Parameters ......................................................... 6-14
LCA Performance ................................................................................ 6-16
Start-up and Reset .............................................................................. 6-19
Metastable Recovery .......................................................................... 6-20
Battery Backup for Logic Cell Arrays .................................................. 6-22
Compact Multiplexer and Barrel Shifter .............................................. 6-23
Majority Logic, Parity ........................................................................... 6-24
Multiple Address Decoding ................................................................. 6-25
Binary' Adders, Subtractors, and Accumulators .................................. 6-26
Adders and Comparators .................................................................... 6-27
Conditional Sum Adder ....................................................................... 6-30
Building Latches Out of Logic ............................................................. 6-31
Synchronous Counters, Fast and Compact ........................................ 6-32
30 MHz Binary Counter ....................................................................... 6-33
Up/Down Counter ................................................................................ 6-34
Loadable Up/Down Counter ................................................................ 6-35
30 MHz Counter with Synchronous Reset .......................................... 6-36
Fast Bidirectional Counters for Robotics ............................................. 6-37
40 MHz Presettable Counter ............................................................... 6-38
Asynchronous Preset in XC3000 CLBs .............................................. 6-40
FrequencylPhaseComparator for Phase-Locked-Loops ................... ,6-41
Gigahertz Presettable Counter............................................................ 6-42
100 MHz Frequency Counter .............................................................. 6-44
Serial Pattern Detectors ...................................................................... 6-45
Serial Code Conversion ...................................................................... 6-46
8-Bit Format Converter .......................................... :............................. 6-48
Megabit FIFO in Two Chips ................................................................ 6-50
State Machines ................................................................................... 6-52
Complex State Machine in One LCA .................................................. 6-53
Self-Diagnosing Hardware .................................................................. 6-54
PS/2 Micro Channel Interface ............................................................. 6-57
High-Speed Bar Code Reader ............................................................ 6-59
DRAM Controller with Error Correction ............................................... 6-61
Logic Analyzer/In-Circuit Emulator ...................................................... 6-67
1962
Applications
INTRODUCTION
Gate Arrays offer maximum flexibility and a high level of
integration, but burden the user with high risk, high cost,
and a long delay from finished design to working prototype.
Generating test vectors and worrying about testability is
another price the gate array user has to pay.
The following pages show examples of systems and subsystems solutions using Xilinx Programmable Gate Arrays. Some of these designs have been implemented, a
few are in production, but most are conceptual designs.
These are intended to demonstrate the devices' capabilities, to highlight special advantage, to emphasize the best
design methods, and in general to stimulate the designer's
imagination.
Programmable Gate Arrays offer a very large number of
flip-flops (128 inthe CLBs and another128 inthe IOBofthe
3020, a total of more than 800 in the 3090). Different from
the situation with Gate Arrays, these LCA flip-flops cannot,
or do not have to be, traded off against logic. Logic coexists
with the flip-flops in the form of function generators. The
function generators are surprisingly versatile pieces of
logic, unlimited in theirflexibilty, limited only by their fan-in
of four or five signals.
A Xilinx programmable gate array can implement virtually
any digital design. Xilinx offers a software package that
covers the gamut from schematic capture through logic
optimization to automatic place and route and to the generation of a programming bit stream. The designer can use
these tools and achieve a working LCA design while paying very little attention to the architectual details of the Xilinx programmable gate array.
When the logic has five inputs or less and is interspersed
with flip-flops driven by a common clock, the Xilinx Programmable Gate Arrays are extremely efficient. Certain
high fan-in functions like ALUs tend to be less efficient, and
bus-oriented designs have to be routed carefully to take
advantage of the long lines and 3-state drivers of the 3000series.
Such an approach, however, will not always achieve the
highest possible performance and the lowest possible
cost. For specific, well-structured designs it may pay to
work out a good match with the LCA architecture. This
chapter gives several examples of such solutions. The
XC2000 and XC3000 family programmable gate arrays
have inherent features different from those of LSTIL MSI
Circuits, or PAL devices, or conventional gate arrays.
Th esefourtechnologies all have different structures which
lea.d to different strengths and weaknesses when they are
being used to implement any specific type of logic.
Fortunately, the user normally has some freedom in structuring the system design. Wheneverpossible, this freedom
should be used to improve either the performance or the
efficiency of the implementation.
GENERAL TOPICS
TTL-MSI was originally defined to fit into a 16-pin package
and to provide a maximum of flexibility, so that each standard part could be used in a myriad of applications. Some
functions are therefore overdesigned (counters and shift
registers have parallel inputs and outputs, when few applications need both) and some are crippled by the 16-pin
limitation (notably the up-down counters).
Most designers want to estimate density and performance
before they begin an LCA design, and some want to know
the definition of equivalent gates. Finally, there is interest
in converting existing PAL designs to LCAs. All these
subjects are covered in the beginning of this chapter.
While the data sheets provide worst-case guaranteed
parameters, many designers need additional information
about input and output characteristics, power consumption, crystal oscillator design, and the exact interpretation
of certain ac parameters. CLB flip-flops show excellent
recoveryfrom metastable problems, an important concern
with asynchronous interfaces.
PAL devlcessufferfrom the rigidity of their AND-OR architecture and from the fixed assignment of flip-flops to output
pins. While the numberof inputs is generous, ideal for wide
decoding, the limited number of product terms that can be
ORed together makes many designs inefficient and slow.
The number of flip-flops available in PALs is very limited.
6-1
II
Applications
COMBINATORIAL FUNCTIONS
Using the fast flip-flops and distributed logic in the LCA to
their best advantage, a synchronous presettable counter
of arbitrary length has been demonstrated to run at
40 MHz. This is much faster than any available popular
microprocessor peripheral counter/timer.
The 5-input function generator of the XC3000 family CLBs
offers unlimited flexibility to implement anyone of the more
than 4 billion (2 32) possible functions of up to five variables
in one CLB, all with the same combinatorial delay. The
4-input function generator in the XC2000 family can implement anyone of the 64K (2 16) possible functions of four
variables. The logic designer should take advantage of this
flexibility while avoiding the possible speed penalty imposed by the limitation to only five or four inputs. This may
lead to logic partitioning that is different from traditional
design orfrom MSI or PAL implementation.
State Machine design is another example in which the
creative use of CLB resources can result in a straightforward and easily understood solution.
As explained in the beginning of this chapter, the CLB flipflops are "metastable-resistant," they resolve metastable
situations typically within a few nanoseconds. Designers
are nevertheless encouraged to avoid asynchronous designs whenever possible. The combination of very fast
CLB flip-flops with relatively slow and layout-dependent
interconnects can lead to internal decoding spikes and
glitches that cannot be observed with an oscilloscope, but
which can play havoc with internal asynchronous logic.
The high-speed, low-skew global clock lines and the individual Clock Enable inputs on each CLB favor synchronous design approaches that are inherently safer and more
predictable.
Majority logic is just one example in which the CLB excels:
A 5 input majority function wou Id use 29 gates when implementedwith 2-input NANOs and inverters, but itfits into the
combinatorial portion of one 3000 series CLB.
Address decoding is the classical strength of PAL devices.
It is done efficiently in LCAs if the complete function includes the combination of several addresses or groups of
addresses.
ALUs consume many LCA resources, but adders or subtractors can be implemented quite efficiently, even using
carry-look-ahead for functions that exceed a width of eight
bits.
SYSTEMS DESCRIPTIONS
LCAs are universal programming building blocks, that are
used in a wide variety of systems.
SEQUENTIAL FUNCTIONS
An 8-digit frequency counter implemented in a 2064 is a
simple illustration. A PS/2 Micro Channel Controller and a
DRAM Controller/Error Corrector demonstrate the versatility of the LCA in speed-critical applications.
LCAs offer an abundance of flip-flops, from 119 in the
XC2064t0928intheXC3090. EachCLBflip-flop(64inthe
XC2064, 128 in the XC3020, 640 in the XC3090) has a
''free'' combinatorial function generator available as its input. This simplifies the design of shift registers and counters.
Article reprints from the trade press indicate the broad
range of LCA applications.
The purpose of this applications chapter is not to provide
cookbook solutions, but rather to stimulate the imagination, convey ideas and demonstrate that LCAs offer a better solution for a large variety of digital designs.
The "Corner Bender" serial-parallel or parallel-serial converter design, is a two-dimensional shift register array that
fits very efficiently into an XC2064 or half of an XC3020,
with 100% utilization of the CLB flip-flops.
6-2
Estimating Size and
Performance
E:XllIXX
BY DAVE LAUTZENHEISER
INTRODUCTION
If the desired programmable gate array has enough I/O
pins, the next step is to count the required storage elements. Table 1 shows both logic block storage elements
and I/O block storage elements. Logic block storage
elements should be considered first, since they are the
most flexible. If the number of storage elements required
is less than the number of logic storage elements, the
desired functions can probably be performed in the chosen
Logic Cell Array.
Programmable gate arrays are available in a range of
densities and speed grades. Before committing resources
to design implementation, the user should estimate which
Programmable Gate Array best fits the specific application. Such size and performance estimates cannot be
expected to provide exact details, but they provide useful
guidelines for device selection and cost estimates. A
complete design will always be the final test for both
density and performance.
In some cases, the I/O block storage elements can also be
used to meet storage element requirements. In particular,
if the number of additional storage elements required
beyond the available logic storage elements is less than
the number of unused I/O pins, then the desired functions
may still fit into the chosen device.
The following two examples illustrate the Step One quick
estimation procedure:
Design fit estimates can be done in two steps. The first is
a quick I/O and storage element count, with no regard for
performance. The second step counts logic blocks based
on details of the intended circuit, and includes gross
performance estimates, still without regard for routing
delays. Performance estimates should always be considered "best-case," recognizing that actual system performance can only be verified on a completed design.
Example 1. An 8-bit microprocessor peripheral.
STEP 1 : I/O and Storage Element Fit
Function
A quick initial estimate ofthe fit of a system into a Programmable Gate Array can be made by counting the required
input and output pins and internal storage elements. Table
1 lists Xilinx's XC2000 and XC3000 series Logic Cell Array
(LCA) devices and their respective I/O and storage element counts. To estimate a fit, first count the required
inputs and outputs and compare the total with the I/O pin
count of the desired device. Ifthe desired functions require
more I/O than listed for a device, one must either select a
larger device or package, or reduce the I/O requirements.
Maximum
Device
110
XC2064
XC2018
XC3020
XC3030
XC3042
XC3064
XC3090
58
74
64
80
96
120
144
Logic
Block
Storage
Block
Storage
58
100
128
200
288
448
640
58
100
128
160
192
240
288
I/O requirements
8 bit data bus
5 bus-control signals
16 bits of output
4 bits of output control
2 internal control registers
Interrupt control logic
8
5
16
4
TOTAL
33
Even the smallest Xilinx Logic Cell Array, the XC2064,
passes the I/O test. It has 58 user I/O in its 68 pin PLCC
package.
I/O
Function
Storage Elements
Control registers (assume 8 bits)
Buffered input shift register
Miscellaneous control logic
16
16
10
TOTAL
42
All of the storage elements can be put into logic storage in
the XC2064. The XC2064 should fit this application,
provided the desired performance can be achieved.
Table 1. I/O and Storage Element Summary
6-3
II
Estimating Size and Performance
Example 2. A memory controller for
performance processor.
a 32 bit high
32 bit processor data bus
32 bit processor memory bus
32 bit memory bus
32 bit control register
32 bit DMA control
Address multiplexing control
RAS/CAS/Refresh generation
Memory error check and correct
Processor and memory timing
32
32
16 (muxed)
10
With two storage elements per logic block, the XC3042
can provide up to 288 storage elements. Based on this
estimate, the desired functions should fit into the device.
Some caution is indicated for two reasons. First, the 1/0
count is very near the limit of the device. This could cause
some routing congestion in the 1/0 area, making a higher
pincount device a better choice. Second, high performance requires making the best use of a device's features.
The 32-bit bus may impose critical performance requirements. Only the XC3064 and XC3090 allow a 32 bit
internal bus, based on the number of available Long Lines.
Choosing the XC3064 could address the 1/0 requirements
as well as the performance needs.
TOTAL
93
STEP 2: Logic Block Requirements
Function
1/0 Requirements
3
After establishing design fit by counting 1/0 and storage
elements, it may be necessary to make a more detailed
analysis of the blocks required. The macro library summary table in the development system section of this data
book may be used to determine specific Configurable
Logic Block (CLB) counts for each function to be implemented.
Based on this 1/0 count, the XC3042 with 96 pins would be
marginal. An XC3064 with up to 120 1/0 pins may be
required.
Storage Elements
Function
32 bit DMA (two-32 bit Counters)
Refresh generation (minimum)
32 bit control register
32 bit processor memory Address
Error check and correct
Miscellaneous control
TOTAL
64
10
32
32
44
20
The macro list shows the various gates and functions
available with each design library. Each entry in the list
includes the required number of logic blocks to implement
that function. Where there are differences between
XC2000 and XC3000 family block counts, these are noted.
To develop a rough block count, the designer simply
tabulates all ofthe blocks required by each ofthefunctional
elements in the design. Figure 1 shows a portion of a
schematic and the block count from the macro list.
202
8-BIT DATA BUS
REGISTER
SHIFT
REGISTER
OUT
SHIFT
REGISTER
IN
REGISTER
WITH 3-STATE
OUTPUTS
SERIAL DATA
VO
CPU
RD4
2CLBs
DECODER
HXl38
SCLBs
REGISTER
RDS
4CLBs
RSSPR
4CLBs
RSS
4CLBs
HX374
4CLBs
CONTROL REGISTER
AO
A1
READIWRITE
DECODER
SHIFT REGISTER OUT
SHIFT REGISTER IN
REGISTER IN 3·STATE
TOTAL
6-4
23 CLBs
113301
In many schematics there are collections of random gates
which need to be considered, along with the higher level
functions such as counters, decoders and multiplexers.
The following technique can be used to estimate the logic
blocks required for random logic. Begin at an output point
and move back along the path collecting gates until the
number of inputs is 4 for XC2000 family devices, or 5 for
XC3000 family devices. These gates can be marked in
some way to show that they occupy a single logic block.
Blocks identified by this method are added to the block
count from the macro list analysis. Figure 2 shows an
example of this gate collecting technique.
Estimating the block count for integrating PLD devices is
more difficult. Each PLD output should be counted as at
least one block. PLD devices using five or fewer of the
inputs, will require only one block per output for the
XC3000 family (four inputs for the XC2000 family). For
complex equations using more than five (or four) inputs, a
conservative estimate is to use three blocks per output pin.
Decisions about the appropriate device can be reviewed
as more information is collected. Block count estimates
which are near the limit of a device, either in block count or
in I/O and storage element count, may suggest use of the
next higher density device.
8~==:t:::::r-
__
8b
CET-_----------------........:::'£.::=4.==I-./
TC
CEP
D3--++------L~
D
Q
D
Q
D
Q
CP
1133802
Figure 2. Six CLBs Are Required to Implement a 74161 Binary Counter
6-5
Q2
•
Q
o
Estimating Size and Performance
Estimating Performance
Allowing 30% for routing (10 nsec) and 8 nsec for setup
gives a total delay of 48 nsec. This should allow operation
at a system clock rate of up to 20 MHz.
After selecting the right programmable gate array based
on logic resources, an estimation of performance is often
the next step. If the system clock rate is less than 20% of
.•11' Summary
the flip-flop toggle rate of the selected device, then the
performance goals can usually be met easily. In cases of
The final determination whether a logic device meets the
higher system clock rates or very complex functions, a
goals for integration and performance can come only after
more detailed analysis may be required.
the design has been completed. For Programmable Gate
Arrays, estimating logic capacity and performance should
The macro library for each device family includes the
precede device selection. If the design fits, the programnumber of logic block levels used for each listed function,
mable gate array development system, and the simplicity .
and the LeA datasheet specifies the block delay for each
of in-system design verification allow cost effective and
level.
rapid design implementation.
Some routing delay must be added to the block delay.
Of course, speCifications sometimes change during the
Such routing delays can add 25-50% to the block delays.
execution of a design. Logic changes may result in
As an example, a circuit might have three levels of blocks
different requirements for 1/0 and logic blocks. In such
in the path from one clock edge to another. For a device
cases the Xilinx products product line simplifies the
with 10 nsec block delays, this gives 30 nsec delay from
migration to a compatible array that meets the new
the first clock to the setup required for the next clock.
requirements.
6-6
Incorporating PLD
Equations into LeAs
Application Brief BYTHOMASWAUGH
The ideal design environment allows entering a design in
many different ways, independent of the target techno logy,
then mapping that design into the technology that best
suits the application. The design entry system should
support the integration of several design entry methods.
For example, a designer should be able to enter a combination of schematics, Boolean equations, and state machines, using whichever method best expresses the logic
in any part of the design. Once the design is entered, the
designer should then be ableto optimize itforthe particular
technology in which it is to be implemented. Xilinx's
Programmable Gate Array design tools support the integration of both schematics, state machines and Boolean
equations into a design.
programs comprise the tools necessary to create designs
that integrate schematics and equations.
INCORPORATING BOOLEAN EQUATIONS
INTO SCHEMATICS
There are a number of ways in which PLD equations can
be used in designing LCAs. Perhaps the best way is to
incorporate PLDs into a schematic (see Figure 1).
PALASM
DESIGN FILE
Some designs or parts of designs are more easily expressed in Boolean equations or state machines than in
schematics. A simple yet effective illustration of this is a
seven segment decoder deSign, which expressed schematically requires many AND and OR gates, but expressed with equations requires only a text file. The
XC-DS23 Automatic Design Implementation (ADI) software allows designers to integrate designs entered using
a schematic editor with Boolean equations expressed in
the PALASM2 format. Designers can enter Boolean equations directly using a text editor or they can create them
with ABEL or CUPL using their PALASM translators. The
ability to create a design using schematics, equations,
state machines, or a combination of the three makes the
design entry process more flexible and more powerful.
~
~
PDS2XNF
~
SCHEMATIC·TO-XNF
TRANSLATOR PROGRAM
SUCH AS
SCH2XNF (SCHEMA) OR
PIN2XNF (FUTURENET)
UNOPTIMIZED
XNFFILE
~
~n~'" I '~
XNF FILE
,...---"---, SCHEMATIC
NETLIST
TRANSLATED TO
1...----,,_--' AN XNF FILE
XNFMERGE
There are four programs in the XC-DS23 that help the
designer incorporate Boolean equations into a deSign. A
translator program called PDS2XNF translates PALASM2
design files into Xilinx Nellist Format (XNF) files. XNF is a
standard interface between the Xilinx Development System and various design entry packages, e.g., schematic
editors. An optimization program called XNFOPT optimizes the logic for Xilinx's Logic Cell Array (LCA) ar,gu1ecture for highest efficiency in terms of density or speed. A
program called XNFMERGE, merges various hierarchically related design files such as schematics and PLD
designs into one flattened file. After merging, a program
called XNF2LCA partitions a deSign's logic and assigns
the logic to the elements of the LCA: configurable logiC
blocks (CLBs) and input/output blocks (lOBs). These four
113501
dp
XNF2LCA
Figure 1. Design Flow of PLDs in a Schematic
Xilinx provides PLD symbols for both Schema 11+ and
DASH-LCA, so that designers can call up PLD symbols
into their schematics. The user attaches a special attribute
called a "FILE=" parameter to each PLD symbol. This
parameter (FILE= file_name) references an optimized
XNF file that contains the translated Boolean equations for
that particular PLD (see Figure 2).
6-7
II
5'
8
OPA:)
OPAO
::~
::J
I/)
seq_'
5'
0"
,....
14
IJ
12
~
OPAD
OPAD
se ,,_
08UF
OPAO
~
OPAD
OPAD
OPAD
OPAO
OPAD
OPAO
'I
"
0"
18
17
. ~08U!
,....
o
!!l.
19
I
a
:i"
cc
.S'
c
PALI0H8
I
I'
-ao
• ~o
~
Figure 2. FutureNet Schematic of a Counter with a 7·Segment Decoder
TITLE
AUTHOR
COMPANY
DATE
7SEG.PDS
BART REYNOLDS AND THOMAS WAUGH
XILINX
APRIL 8, 1988
LeA. The logic represented by Boolean equations such as
these must be optimized using the XNFOPT program
before it can be translated into an LCA. The schematic
portion of the design is also translated into an XNF file.
CHIP
7SEG
;Input Pins
1 2 3
NC NC DO
11 12 13
NC NC G
The schematic XNF file is considered the top level of the
design hierarchy, since it contains references to other XNF
files like optimized XNF files from PLD designs. The
XNFMERGE program merges lower level XNF files into
the top level XNF file from the schematic to form one
flallened file that can be partitioned into the LCA architecture, then placed and routed just like any other design.
;Output Pins
PALI0H8
4 5 6
Dl D2 D3
14 15 16
F E D
7 8 9 10
NC NC NC NC
17 18 19 20
CB A NC
;Input combinations
STRING
STRING
STRING
STRING
STRING
STRING
STRING
STRING
STRING
STRING
STRING
STRING
STRING
STRING
STRING
STRING
ZERO
ONE
TWO
THREE
FOUR
FIVE
SIX
SEVEN
EIGHT
NINE
TEN
ELEVEN
TWELVE
THIRTEEN
FOURTEEN
FIFTEEN
'/D3
'/D3
'/D3
'/D3
'/D3
'/D3
'/D3
'/D3
' D3
' D3
' D3
' D3
' D3
' D3
'D3
'D3
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
/D2
/D2
/D2
/D2
D2
D2
D2
D2
/D2
/D2
/D2
/D2
D2
D2
D2
D2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
/Dl
/Dl
Dl
Dl
/D1
/Dl
Dl
Dl
/D1
/Dl
Dl
Dl
/D1
/Dl
D1
D1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
/DO'
DO'
/DO'
DO'
/DO'
DO'
/DO'
DO'
/DO'
DO'
/DO'
DO'
/DO'
DO'
/DO'
DO'
DESIGNING LOGIC CELL ARRAYS WITH BOOLEAN
EQUATIONS
Another method of using equations to design LCAs is to
express the LCA completely in terms of Boolean equations
without regard for a particular PLD type (shown in Figure
4). The PDS2XNF program will translate PLD equations
into an XNF file, even if the PLDdesign file does not correspond to an existing PLD device. The PDS2XNF program recognizes some features that are not permissible in
the standardPALASM2 format, including unlimited signal
names in the design pinlist, internal signals not named in
the pinlist, arbitrarily complex equations, and 32 character
signalnames.LCA design with equations does not allow
the use of all the features of the LCA (e.g., input flip-flops
on XC3000 lOBs), but it is a useful and convenientway of
designing LCAs. completely and quickly using BooJean
equations.
EQUATIONS
A = ZERO + TWO + THREE + FIVE + SIX + SEVEN
+ EIGHT + NINE + TEN + TWELVE + FOURTEEN
+ FIFTEEN
B = ZERO + ONE + TWO + THREE + FOUR + SEVEN
+ EIGHT + NINE + TEN + THIRTEEN
C = ZERO + ONE + THREE + FOUR + FIVE + SIX
+ SEVEN + EIGHT + NINE + TEN + ELEVEN
+ THIRTEEN
D = ZERO + TWO + THREE + FIVE + SIX + EIGHT
+ ELEVEN + TWELVE + THIRTEEN + FOURTEEN
E = ZERO + TWO + SIX + EIGHT + TEN + ELEVEN
+ TWELVE + THIRTEEN +.FOURTEEN + FIFTEEN
F = ZERO + FOUR + FIVE + SIX + EIGHT + NINE
+ TEN + ELEVEN + TWELVE + FOURTEEN
+ FIFTEEN
G
TWO + THREE + FOUR + FIVE + SIX + EIGHT
+ NINE + TEN + ELEVEN + THIRTEEN
+ FOURTEEN + FIFTEEN
PALASM
DESIGN FILE
UNOPTIMIZED
XNFFIL£
OPTIMIXED
XNF FILE
Figure 3. PALASM2 Design File Referenced in the
Schematic
c;J
GJ •
GJ
8
XNF2LCA
XNFFILE
MAPPED INTO.
LeA TECHNOLOGY
The PLD design file, entered in the PALASM2 format (see
Figure 3), is translated into the Xilinx Netlist Format using
the PDS2XNF program and then optimized for the LCA
architecture using the XNFOPT program. PLD equations
like the ones shown below are in a sum-of-products form
that does not always map efficiently into the CLBs of an
LOA.
1135 Q2
Figure 4. Flow Chart of Direct Translation of PLD
Equations
6-9
Incorporating PLD Equations Into LCAs
into the PALASM2 Format. This PALASM2 formatfile can
then be translated into an XNF file and optimized like a
PLD equation file originally entered in PALASM2.
DESIGN OPTIMIZATION
The cornerstone of the PLD conversion software is a
program called XNFOPT. PLD equations are usually
expressed in a sum-of-products form that is not optimally
suited forthe CLB architecture, with blocks of 4 or 5 inputs
that perform any function of those inputs. The XNFOPT
program is used to optimize logic so that the logic fits
efficiently into the CLBs and lOBs of the LCA. XNF files
translated from PLD equation design files should always
be optimized using the XNFOPT program; in some situations XNFOPT may be used to optimize a design from a
schematic as well, although there are some caveats.
SUMMARY
In many cases, designs are most easily expressed using
a combination of logic equations and schematics. Software tools in Xilinx's ADI package give deSigners the
capability to integrate equation and schematic entry methods. The benefits of these logic synthesis tools are simpler
and more powerful design entry, more efficient use of LCA
logiC, and clearer design documentation.
There are some designs for which optimization using the
XNFOPT program is inappropriate. XNFOPT is meant for
synchronous designs, not asynchronous ones. XNFOPT
significantly alters logic, so it may not preserve a deSign's
asynchronous timing dependencies. Furthermore, although optimized logic is functionally equivalent to the
original deSign, the structure may be significantly changed
making debugging more difficult. It is generally a good
idea to first simulate a design functionally to insure its
correctness before optimizing it. Logic in an XNF file that
is expressed as CLB or CLBMAP primitives cannot be optimized, as it is already partitioned into the LCA architecture.
~
ABELORCUPL
DESIGN FilE
~
ABEL OR CUPl TO PDS
PALASM
DESIGN FILE
UNOPTIMIZED
XNF FILE
The XNFOPT program can be directed to optimize a
design for speed or for density. Optimizing for density
reduces the number of CLBs used by the deSign, while
optimizing for speed reduces the number of levels of logiC
used by the design. In its default mode of operation,
XNFOPT optimizes for density, using the -L option directs
XNFOPT to optimize for speed.
OPTIMIXED
XNF FILE
I'M~r'l
I '~' I
I
':f I
XNF2lCA
~~~~~l6INTO ~
~
STATE MACHINES
Xilinx LeA designs can be entered as state machines
through either the ABEL or CUPL PLD entry language.
Data 1/0's ABEL software and Logical Devices' CUPL
software offer options that convert their source design files
lCA TECHNOLOGY
113503
Figure 5. Converting PLD Designs from ABEL or CUPL
6-10
The XC2000 User's
Guide to the XC3000 Family.
In late 1987 Xilinx introduced the XC3000 family which,
within a year grew to five members: the XC3020, XC3030,
XC3042, XC3064 and XC3090.
1 additional horizontal long line per row.
1 additional vertical clock line per column.
• All CLB inputs and outputs have access to both horizontal and vertical routing channels:
Designers already familiarwiththe original XC2000 family
may be interested in the following synopsis of the differences between the 2000 and 3000 families.
• Capability of magic box is enhanced.
COMBINATORIAL LOGIC:
• Both horizontal long lines have 3-state bus drivers.
• Combinatorial logic is wider (5 inputs vs. of 4 in XC2000
family).
• Bi-directional buffers are evenly distributed and used
only when needed to boost a signal.
CLB STORAGE ELEMENTS:
OTHER DIFFERENCES
• There are two storage elements in a CLB.
• Crystal oscillator has a "+ 2" option (50% duty cycle)
• Storage element is a flip-flop only, the latch option is
eliminated.
• Oscillator output can be connected to the general interconnect.
• Data input of either flip-flop can come from the combinatoriallogic output, (F or G,) or from the one direct data
input, DIN of each CLB.
• Added fast, dedicated CMOS input buffer for the global
and alternate clocks.
• Capability of the edge magic box is enhanced.
• Clock input can be driven from local lines in addition to
global and alternate clock lines,
• Each edge has two 10CLKS, clock source multiplexers
are located in each corner.
• Enable Clock signal eliminates need for clock gating.
• Asynchronous set is removed but asynchronous reset is
retained, consistent with TTL-MSI design practices.
• 10CLK can be synchronized to the global and alternate
clock. 10Bon adjacent chip edges can be driven from the
same clock source.
• No flip-flop inputs are shared with combinatorial logic.
• All 10CLK clock drivers can be inverted.
• Clock, Enable Clock, and Reset are commonto both flipflops.
lOBs
• Two vertical long-lines in each column and one long-line
on each horizontal and vertical edge can each be split
into two half long-lines. (On the XC3020 this can only be
done with one long-line on each edge.)
• Both direct input (I) and registered input (Q) are available
simultaneously.
DIFFERENCE IN CONFIGURATION
• Inputstorage element can be flip-flop or latch.
• Parallel peripheral mode is added.
• Output signal and 3-state control signal can be inverted.
• Modified timing for slave mode avoids hold time.
• Output signal can be either direct or registered.
• No RCLK output in master serial mode, use CCLK.
• Output buffer has a programmable passive pull-up to
prevent floating input.
• Modified pinout for master and peripheral mode, all data
pins are on the right hand edge.
• Output buffer has option to slow down the output transition to reduce transient noise.
• INIT state brought out as output.
ROUTING RESOURCES:
• PWRDN does not affect "House Cleaning".
• Done and Reset, programmable one clock early or late.
1 additional horizontal local line per row.
6-11
•
Designing with the
XC3000 Family
Application Brief BY THOMAS WAUGH
CLOCKING
THREE·STATEBUFFERS
Global and Alternate Clocks Buffers
Active High three-state is the sarne as active low enable.
There are two high-fanout,low-skew clock resources. The
global clock originates from the GClK buffer in the upper
left corner of the chip and the alternate clock originates
from the AClK buffer in the lower right corner of the chip.
In other words: A "1" on the T pin of a TBUF or an OBUFZ
three-states the output, and a "0" enables it.
Input/Output Blocks (lOBs)
These resources drive nothing but the K pins (clock pins)
of every register in the device. They cannot drive logic
inputs. In the rare case where this connection is required,
tap a signal off the input to the clock buffer and route it to
the logic inputs.
Unused lOBs should be left unconfigured. They default to
inputs pulled High with an internal resistor.
lOB pullup resistors cannot be used with lOB outputs, only
on pins that are inputs exclusively.
The global and alternate clocks each have fast CMOS
inputs, called TClKIN and BClKIN respectively. Using
these inputs provides the fastest path from the PC board
to internal flip-flops and latches because the signal bypasses the input buffer. CMOS levels on the input clock
signal must be guaranteed.
Configurable logic Blocks (CLBs)
ClBs have two flip-flops (not latches). They share a common clock, a common reset, and a common clock enable
signal.
Asynchronous preset can be achieved by the asynchronous reset, by just inverting D and Q of the flip-flops.
To specify the use of TClKIN or BClKIN in a schematic,
connect an IPAD symbol directly to a GClK or AClK
symbol. Placing an IBUF between the IPAD and GClK or
AClK will prevent the TClKIN and BClKIN from being
used.
ROUTING RESOURCES
Horizontal Long Lines
The number of Horizontal long Lines (Hll) per device is
double the number of rows of ClBs.
Always use GCLK and ACLK for the highest fanou~ clocks.
I/O Clocks
The number of TBUFs that drive each Horizontal long
Line is one higher than the number of columns on the
device.
There are a total of eight different I/O clocks, two per edge
on each of the four edges.
I/O storage elements can be configured to be latches or
flip-flops. Clocking polarity is programmable perclock line,
not per lOB. A clock linethattriggers aflip-floponthe rising
edge can be an active low latch Enable (latch transparent) and vice versa.
Crystal Oscillator
Connects to alternate clock buffer, AClK, not to GClK.
Part
Name
Rows x
Columns
3020
3030.
3042
3064
3090
10 x 10
12 x 12
16 x 14
20 x 16
8x8
CLBs
64
100
144
224
320
HLL.
TBUFs
per HLL
16
20
24
32
40
9
11
13
15
17
Continued on the opposite page
6-12
Designing with the
XC2000 Family
E:XILIXX
Application Brief BY THOMAS WAUGH
CLOCKING
CONFIGURABLE LOGIC BLOCKS (CLBS)
Global and Alternate Clocks Buffers
CLBs have one storage element that can be configured as
a flip-flop or a latch.
There are two high-fanout, low-skew clock resources. The
global clock originates from the GCLK buffer in the upper
left corner of the chip and the alternate clock originates
from the ACLK buffer in the lower right corner of the chip.
CLB storage elements have both an asynchronous set and
an asynchronous reset.
ROUTING RESOURCES
The global clock buffer, GCLK, drives the Band K pins of
the Configurable Logic Block (CLB).
Horizontal Long Lines
The alternate clock buffer, ACLK, drives the B, C, and K
pins of the Configurable Logic Block (CLB). The crystal
oscillator drives the ACLK.
There is one Horizontal Long Line per routing channel.
Always use GCLK and ACLK for the highestfanout clocks.
Vertical Long Lines
1/0 Clocks
There are four different 1/0 clocks, one per edge.
There are three Vertical Long Lines per routing channel,
one general purpose, one for the global clock net and one
for the alternate clock net.
1/0 flip"flops are positive-edged triggered.
CLB pins with Direct Access to Long Lines
There are no internal three-state buffers on the chip.
A- Horizontal Long Line above the CLB.
B- Global clock buffer, Middle and Left Vertical Long
Line.
C- Middle and Left Vertical Long Line.
D- Horizontal Long Line below the CLB.
X- To Left Vertical Long Line.
Y- To Middle Vertical Long Line.
INPUTIOUTPUT BLOCKS (lOBS)
Unconfigured lOB outputs must not be left floating. Configure them as outputs and drive them from internal logic
or leave them unconfigured and pull them up with an
external resistor.
•
Designing with the XC3000 Family (Continued)
T and I pins of TBUFs have limited interconnect resources.
CLB Pins with Direct Access to Long Lines
AECBCK-
Lower Horizontal Long Line.
Left Middle Vertical Long Line.
Left Middle Vertical Long Line.
Right Middle Vertical Long Line
Rightmost and Leftmost Vertical Long Lines
(ACLK and GCLK).
E- Right Middle Vertical Long Line.
D- Upper Horizontal Long Line.
RD- Left Middle Vertical and Lower Horizontal
Long line.
Never use fewer than .four TBUFs per Horizontal Long
Line. When using TBUFs for multiplexing applications,
using fewer than four wastes resources. Use CLBs for
multiplexing instead.
Vertical Long Lines
There are four Ve rtical Long Lines per routing channel, two
general purpose, one for the global clock net and one for
the alternate clock net.
1976
6-13
Additional
Electrical Parameters
E:XILINX
Application Brief
The XILINX LCA data sheets specify worst case device
parameters, 100% tested in production and guaranteed
over the full range of supply voltage and temperature.
OUTPUTS
All LCA outputs are true CMOS with n-channel transistors
pulling down, p-channel transistors pulling up. Unloaded,
these outputs pull rail-to-rail.
Some users may be interested in additional data that is not
100% tested and, therefore, not guaranteed. Here are
results from recent bench measurements:
DC Parameters
PULL-UP RESISTOR VALUES
lOB Pull-ups
DONE Pull-up
Long Line Pull-up(each)
40 to 150 kn
2to 8 kn
3 to 10 kn
These values were measured with the node pulled LOW.
At a logic HIGH the resistor value is 5 to 10 times higher.
Output Impedance
Sinking, near ground:
Sourcing, near Vcc:
son
Output Short Circuit Current
Sinking current by the LCA
Sourcing current by the LeA
96 mA
60mA
25n
The data sheets guarantee the outputs only for 4 mA at320 mV
in order to avoid problems when many outputs are sinking
current simultaneously.
INPUTS
AC Parameters
Hysteresis
Unloaded Output Slew Rate
Unloaded Transition Time
Additional rise time for 812 pF
normalized
Additional fall time for 812 pF
normalized
All inputs, except PWRDN, and XTL2 when configured as
the crystal oscillator input, have limited hysteresis, typically in excess of 200 mV for TTL input thresholds, in
excess of 100 mV for CMOS thresholds.
Required Input Rise and Fall Times
Fast'
2.8 V/ns
1.45 ns
100 ns
0.12 ns/pF
50 ns
0.06 ns/pF
Slow'
0.5 V/ns
7.9 ns
100 ns
0.12 nspF
64 ns
0.08 nspF
, "Fast" and "Slow" refer to the output programming option.
For unambiguous operation, the input rise time should not
exceed 200 ns, the inputfall time should not exceed 80 ns.
There is good agreement between output impedance and
loaded output rise and fall time, since the rise and fall time is
slightly longer than two time constants.
These values were established through a worst-case test
with internal ring oscillators driving all I/O pins except two,
thus generating a maximum of on-Chip noise. One of the
remaining 1/0 pin was then tested as an input for singleedge response, the other one was the output monitoring
the response. This specification may, therefore, be overly
pessimistic, but, on the other hand, it assumes negligible
PC board ground noise and good Vcc decoupling.
6-14
E:
Power Dissipation:
Vcc
LCA power dissipation is largely dynamic, due to the
charging and discharging of internal capacitances. The
dynamic power, expressed in mW per MHz of actual node
or line activity is given below.
4.5V
5.0V
5.5V
4.5V
4.5V
Clock line frequency is easy to specify, but the designerwill
usually have great difficulty estimating the average frequency on other nodes.
The on-chip oscillator circuit consists of a high-speed, high
gain inverting amplifier between two device pins, requiring
an external biasing resistor R1 of 4 MQ.
1. Binary counter, where half the total power is dissipated
in the first flip-flop.
A series-resonant crystal Y1 and additional phase-shifting
components R2, C1 , C2 complete the circuit.
2. A shift register with alternating zeros and ones, where
the whole circuit is excercised at the clocking speed.
Fundamental Frequency Operation up to 24 MHz:
Dynamic Power
(mW/MHz)
C1 = C2 = 34 pF
R2 = 1 KO up to 12 MHz, 8000 to 520 0 for 15 to 24 MHz
1.9
1.7
3.6
0.36
0.09
0.15
0.08
0.19
0.075
Third Overtone Operation from 20 MHz to 72 MHz:
Replace C2 with a parallel resonant LC tank circuit tuned
to ~ 2/3 of the desired frequency, i.e., twice the crystal fundamental frequency.
Frequency
(MHz)
L (IlH)
'Add 2.5 mW/MHz for every 100 pF of additional load
Example:
XC3020 with
32.00
35.00
49.00
72.00
Dynamic Power
(mW/MHz)
3 outputs at 5 MHz
20 outputs at 0.1 MHz
Global Clock at 20 MHz
10 CLBs at 5 MHz
40 CLBs at 0.2 MHz
16 Vertical Long Lines at 1 MHz
20 Inputs at 4 MHz
28
4
34
18
3
Total
94mW
687 kHz
691 kHz
695 kHz
966 kHz
457 kHz
25°C
25°C
25°C
-30°C
+130°C
CRYSTAL OSCILLATOR
Two extreme cases are:
Output with 50 pF load'
Global Clock (XC3020)
Global Clock (XC3090)
CLB with Local Interconnect
Horizontal Long Line (XC3020)
Horizontal Long Line (XC3090)
Vertical Long Line (XC3020)
Vertical Long Line (XC3090)
Input without Pull-up
Fr~q
T
C (pF)
LCTank
Freq (MHz)
60
44
31
18
20.6
24.0
28.6
37.5
R2 (0) C1 (pF)
430
310
190
150
23
23
23
12
•
1
6
CCLK Frequency Variation
R1
Configuration Clock (CCLK) is the internally generated
free-running clock that is responsible for shifting configuration data into and out of the device.
R2
I
CCLK frequency is fairly stable over Vee, varying only
0.6%.for a 10% change in Vcc, but is very temperature
dependent, increasing 40% when the temperature drops
from 25°C to -30°C, decreasing 40% when the temperature increases from 25°C to +130°C.
C2_C(JL
3RD
OVERTONE
115802
Crystal Oscillator
6-15
LeA Performance
Application Brief
clock-to-output
routing
logic set-up
-50
12 ns
12 ns
12 ns
-70
8 ns
8 ns
8 ns
-100
7 ns
6 ns
7 ns
clock period
clock frequency
36 ns
28 MHz
24ns
42 MHz
20 ns
50 MHz
ESTIMATING CLB PERFORMANCE
Since the delays in LCA-based designs are lay-out dependent, the data sheet cannot give all the answers
needed to predict the worst case guaranteed performance.
The timing calculator in )(ACT is a better tool, and a
simulation using SILOS, after the design has been routed,
will be the final arbiter for worst-case performance.
3.
Still, most designer want to evaluate the possible performance, well before they have finished the design.
Here are some guidelines for XC3000 family devices:
1.
2.
A simple synchronous design-like a shift register,
where a flip-flop feeds a flip-flop in the next vertical or
horizontal CLB through the one level of combinatorial
logic in front of the target flip-flop:
clock-to-output
routing
logic set-up
-50
12 ns
1 ns
12 ns
-70
8 ns
1 ns
8 ns
-100
7 ns
1 ns
7 ns
clock period
clock frequency
25 ns
40 MHz
17 ns
59 MHz
15 ns
67 MHz
TCKO
SETUP
I+-
-4
ClB
0
0
-70
8 ns
8 ns
9 ns
1 ns
8 ns
-100
7 ns
6 ns
7 ns
1 ns
7 ns
clock period
clock frequency
51 ns
20 MHz
34ns
29 MHz
28 ns
36 MHz
These numbers assume synchronous clocking from the
global clock lines. Remember, these are all worst-case
numbers, guaranteed over temperature and supply voltage. Nobody should design with typical numbers.
TICK
-I
TWO-LEVEL
CLOCK TO OUTPUT
-+--
----l
TCKO
COMBINATORIAL
I+-
TILO
----l I+--
SETUP
TICK
--I
ClB
ClB
INTERCONNECT
-50
12 ns
12 ns
14 ns
1 ns
12 ns
~-
SINGLE LEVEL
CLOCK TO OUTPUT
I-
clock-to-output
routing
logic delay
routing
logic set-up
Therefore, as a rule of thumb, the system clock rate should
not exceed one third to one half of the specified toggle rate.
Simple deSigns, like shift registers and simple counters,
can run faster, approximately two thirds of the specified
toggle rate.
A similar design with flip-flops several rows or columns
apart would add routing delay:
I-
An additional level of combinatorial logic plus routing
reduces performance further:
0
a
0
C~CK-*--------------------------------~------------------------------~
Figure 1. Critical Timing Parameters for Clocked CLB Driving Clocked CLB Directly (Single Level)
and Driving it Through Additional Combinational Logie (TWO-Level)
6-16
0
1159 04
E:XIIJNX
time is:
DESIGNING FOR HIGHEST DATA TRANSFER RATE
BETWEEN 3000 FAMILY LeAs
20-3-6 = 11 ns for the -70 device
30-5-9 = 16 ns for the -50 device
Worst case analysis of a synchronous data transfer between 3000 family devices postulates that the sum of
clock-to-output propagation delay of the sending device,
plus the input-to-clock set-up time of the receiving device,
must be less than the clock period.
Under these assumptions, the worst case (shortest) value
for the clock period is:
22 + 11 = 33 ns, I.e., max 30 MHz for the -70 device
31 + 16 = 47 ns, I.e., max 21 MHz for the -50 device
The inherent freedom in clock and signal routing makes it
impossible to give exact values for an unprogrammed LCA
without specifying certain restrictions:
Bypassing the input flip-flop in the lOB and going directly
to the DI input of the closest CLB is another, non-obvious,
way of improving performance by 8 ns forthe -70 device,
by 12 ns for the -50 device.
Onthe transmitting LCA, the clock-pinto output-pin propagation delay is minimized if TCLKIN or BCLKIN are chosen
as clock inputs. They are CMOS-level only, and offer the
shortest on-chip clock delay.
Ifthis is notfast enough, there are design methodS that can
improve the performance. Let us assume a -70 device.
The easiest and safest method is to increase the clock
delay on the receiving LCA, thus reducing the apparent
input set-up time. Changing to a direct input (instead of
TCLKIN) adds 4 ns to the clock delay, thus subtracts at
least 3 ns from the input set-up time.
The clock-pin to output delay is then
3 + 6 + 13 = 22 ns for the -70 part
5+9+18=31 nsforthe-50part
On the receiving LCA, the input-pin to clock-pin set-uptime
is the specified I/O pad input set-up time (parameter TPICK
in the lOB switching characteristic table of the XC3000
family data sheet) minus the actual delay for clock buffering and routing.
More aggressive methods of increasing clock delay inside
or outside the receiving LCA must be used with care, since
they might reduce the "best case" set-up time (fast process, low temperature, high Vcc) to a value of less than
zero, i.e., make it a hold time requirement, which, in
conjunction with a best case very fast transmitting device,
can lead to problems.
Assuming the same clock buffer choice on the receiver as
on the transmitter, the longest input-pin to clock-pin set-up
T OKPO ~
o
CLOCK
I+- TClKIN -+-
T GClK-of
115903
Figure 2. CrItical TIming Parameters for Data Transfer Between LeAs
6-17
•
LeA Performance
INPUT SET-UP TIME ON A 3000 SERIES LCA IS
BETTER THAN THE SPECIFICATION.
WHY ARE THERE NO GUARANTEED MIN. DELAY
SPECIFICATIONS?
The Xilinx 3000 series data sheet specifies a worst case
input set-up time of 20 ns for the -70 speed grade
(parameter #1 on page 41), but this is the data input pad
set-up time with respect to the internal lOB clock, not with
respect to the clock input pad.
IC manufacturers do not usually guarantee minimum
propagation delay values, though some specify a token
min delay of 1 ns. There are compelling reasons:
These short delays are extremely difficult to measure on a
production tester. Even if it were possible, the necessary
tester guard-banding might make the result
meaningless.The spread between a conservative worstcase maximum value and a similarly conservative worstcase (best-case?) minimum value would be surprisingly
large. There are five reasons:
Any delay from clock pad to lOB clock must be subtracted
fromthe specified set-up value in orderto arrive atthe true
systems set-up time as seen on the device package pins
(pads) for data and clock. Since the internal clock delay
can be manipulated by the user, Xilinx cannot specify the
systems set-up time.
1. Temperature. CMOS propagation delays decrease
approximately 0.3% per degree C.
The shortest possible clock delay from the package pin to
the lOB clock is achieved by selecting the CMOS
compatible clock inputs TClK or BClK. The guaranteed
max value for their delay is 9 ns (XC3000-70), the sum of
3 ns for pad-to-ClKIN plus 6 ns for the clock buffer and
clock distribution.
2. Supply Voltage. CMOS propagation delays are roughly
inverse proportional to Vcc.
3. Test Guardband. The max delay test is performed at a
temperature well above TMAX and a supply voltage
well below Vee MIN. The accepted max delay is
also less than the data sheet value. Equally conservative methods applied at the opposite extremes would
give very short values.
Xilinx does not guarantee any shortest values for all these
parameters. An unrealistic worst-worst case analysis
might, therefore, assume two extreme values:
20 ns set -up time for a slow data input with an infinitely
fast clock path
4. Process Variations. lCAs are sorted into a few speed
classes. A part marked-50 might have barely missed
the -70 specification in only a few or perhaps only one
parameter. IC manufacturers may sometimes mark
down (call a -70 part a -50 part) in order to adjust
production yield to market demand. This increases the
spread even more.
9 ns hold time for an infinitely fast data input combined
with a slow clock path.
That is a meaningless mathematical exercise. In reality,
all these delays track very well over temperature, supply
voltage and processing variations, never deviating more
than 30% from each other's normalized value. When one
parameter is at its absolute max value, any other parameter will be between 54% and 100% of its max value (54=
100 x 0.71 1.3). The longest required set-up time for the
data input with respect to the CMOS compatible clock
input is, therefore, 15 ns (20 ns minus 54% of 9 ns).
5. Process Evolution. As IC technology improves, smaller
geometries reduce not only device size and cost, but
also propagation delay. Tight min. specifications would
be a hindrance to progress.
Finally, it can be argued that a proper synchronous design
is insensitiveto minimum propagation delay values. When
the clock skew is small, ( Xilinx clock networks guarantee
extremely small clock skew values, less than 2ns over a
big chip like the XC3090) the designer can safely ignore
the minimum delay issue. No Xilinx ClB or lOB input has
a hold time requirement.
What is the shortest set-up time, Is there a danger of
malfunction due to a positive hold time?
The fastest delay parameter is always longer than 10% of
the specified guaranteed max value for the fastest
available version of this device. The fastest value occurs
at the lowest temperature and highest supply voltage.
In the past, designers have faced far greater uncertainties
when they populated PC boards with a variety of SSI, MSI
and PAL devices, each from a different production run,
each with different power dissipation and junction temperature. Such problems do not exist inside the lCA
where delays track, and the temperature is the same for all
elements.
The shortest data set-up time with respect to the CMOS
compatible clock input is, therefore, 1.1 ns (10% of 20 ns
minus 9 ns). This is still a positive value, sometimes called
a negative hold time.
There will never be a hold time requirement if the user
selects the CMOS compatible clock input option.
6-18
Start-Up and Reset
Application Brief
INTERNAL LOGIC DURING CONFIGURATION
SYNCHRONOUS RESET AFTER CONFIGURATION
During configuration, all 1/0 pins not used forconfiguration
are 3-stated and all internal flip-flops and latches are held
reset until the chip goes active. Even multiple LCAs
hooked up in a daisy chain will go active simultaneously as
a result of the same CCLK edge. This is well documented.
After configuration is completed, the LCA becomes active
in response to a rising edge of CCLK. All outputs that go
active will do so simultaneously, but they are obviously not
synchronized to the system clock. Some designs might
require a reset pulse synchronous with the system clock to
avoid start-up problems due to asynchronous timing between the end of internal reset and the system clock.
Not documented is how the internal combinatorial logic
comes alive during configuration: As configuration data is
shifted in and reaches its destination, it activates the logic
and also "looks at" the inputs .. Even the crystal oscillator
starts operating as soon as it sees its configuration data.
Since all flip-flops and latches are being held reset, and all
outputs are being held 3-stated, there is no danger in this
"staged awakening" of the Chip. The user can take
advantage of this to make sure that the chip comes to life
with the internal output 3-state control signal on the output
driver already active before the end of configuration, so
that there is no chance of any output glitch.
The circuit below generates a short global reset pulse in
response to the first system clock after the end of configuration. It consumes one CLB plus one output pin, and it
also precludes the use of the "LDC" pin as 1/0.
During Configuration:
LDC (Low) holds D High, but Q is held Low by internal
reset.
RESET is pulled High by internal and external resistors.
FAST RECOVERY FROM RESET
End of Configuration before first System Clock:
Recovery from Reset is not specified in our data sheets
because it is very difficult to measure in a production
environment.
LDC pin goes active High, Q stays Low, D stays High.
RESET is still pulled High by external resistor.
Result of first System Clock after end of Configuration:
Here are benchmark values:
The CLB can be clocked immediately (i.e. within 0.2 ns)
after the end of the internal direct reset (rd).
Q is clocked High, which forces D Low.
Output driver goes active Low and forces RESET Low.
This resets the whole chip until the Low on Q
causes RESET to be pulled High again
The whole chip has thus been reset by a short pulse •
instigated by System Clock.
The CLBcan be clocked no earlier than (worst case) 25 ns
after the release (rising edge) of the externally applied
Global Reset (acting Low) signal.
1971 01
HIGH
Figure 1. Synchronous Reset
6-19
-+.-l>'-'--+-
f lOB
_
~::.:.:.:.:.:-:.:.:.:-:.:-:.:-:-:.:.:.:.:::
Additional Electrical Parameters
Metastable Recovery
Applications Brief BY PETERALFKE &PERRYWU
When an asynchronous event frequency of approximately 1 MHz is being synchronized by a 10 MHz clock,
the CLB flip-flOp will suffer an additional delay of
CLB FLIP-FLOPS RECOVER SURPRISINGLY FAST
FROM METASTABLE PROBLEMS
A specter is haunting digital design, the specter of metastability. From a poorly understood phenomenon in the
seventies, it has developed into a scary subject for every
designer of asynchronous interfaces. Now Xilinx offers
data and a demonstration kit to help users analyze and
predict the metastable behavior of LCAs.
4.2 ns statistically once per hour
6.6 ns statistically once per year
8.4 ns statistically once per 1000 years
Thefrequency of occurrence of these metastable delays is
proportional to the product of the asynchronous event
frequency and the clock frequency.
Whenever a clocked flip-flop synchronizes a truly asynchronous input, there is a small but finite probability that
the flip-flop output will exhibit an unpredictable delay. This
happens when the input transition not only violates the
setup and hold-time specification, but actually occurs
within the tiny timing window where the flip-flop "decides"
to accept the new input. Under these circumstances the
flip-flop enters a symmetrically balanced state, called
metastable, (meta = between) that is only conditionally
stable. The slightest deviation from perfect balance will
eventually cause the outputs to'revert to one of the two
stable states, but the delay in dOing so depends not only on
the gain bandwidth product of the circuit, but also on the
original balance and the noise level of the circuit; it can,
therefore, only be described in statistical terms.
If, for example, a 100 kHz event is synchronized by a 2
MHz clock, the above mentioned delays (besides being far
more tolerable) will occur 50 times less often.
The mean time between metastable events lasting longer
than a specified duration is an exponential function of that
duration. Two points measured onthat line, allow extrapolation to any desired MTBF (mean time between failure).
MTBF
SEC
10 '1
The problemforthe system designer is not the illegal logic
level in the balanced state (it's easy enough to translate
that to either a 0 or a 1), but the unpredictable timing of the
final change to a valid logic state.
10 '0
10'
10·
1 YEAR
10 7
The basic phenomenon is as unavoidable as death and
taxes, but the probability of erroneous operation can be
determined, and the impact of various countermeasures
can be evaluated quantitatively, if two fundamental flipflop parameters are known, i.e., the metastability capture
window, and the metastability recovery rate.
1 MONTH
10·
10'
1 DAY
10'
1 HOUR
10'
Xilinx has evaluated the XC3020 CLB flip-flop with the help
of a mostly self-contained circuit on the Demonstration
Board that is available to any Xilinx customer.
10 2
10'
The result of this experimental evaluation shows the Xilinx
CLB flip-flop superior in metastable performance to many
popular MSI or PLD devices.
4
6
NS
1160 01
Metastable MTBF as a Function
of Additional Acceptable Delay
6-20
Metastable Recovery
MEASURING METASTABLE RECOVERY
Every ns in additional acceptable delay reduces the
frequency of metastable events by a factor 40.
The excellent metastable recovery rate of Xilinx lCA flipflops was measured in a working XC3020-70 on the Xilinx
evaluation board. Since metastability can only be measured as a statistical event, the device was configured with
eight concurrent detectors:
The MTBF curve was then normalized to a reasonable
combination of clock and asynchronous data rates, using
the generally accepted theory that, everything else being
equal, the frequency of metastable events is proportioned
to the product of the two frequencies at the D and ClK
inputs of the flip-flop under test.
Eight D flip-flops are clocked from a common high speed
source. Their D inputs are driven from a common, lower
frequency asynchronous signal. Each flip-flop feeds the
D inputs of two more flip-flops, one of them clocked on the
opposite clock edge. This cuts the clock rate forthe experiment in half, from 50 MHz to a more manageable 25 MHz.
A comparator detects when 01 differs from D = 00 = 02.
Assuming that the metastable window is 0.1 ns wide, and
the clock is 10 MHz, one data change in 1000 will fall into
the metastable window. A 1 MHz data rate gives an MTBF
of 1 ms for an additional delay of zero. Each additional ns
of acceptable delay increases the MTBF by a factor 40,
see diagram on the previous page. It is difficult to measure
the exact width of the window, but it hardly matters. If the
assumption of 0.1 ns were wrong by a factor of 10, it would
only move the graph horizontally by 0.624 ns.
This can only be the result of 00 having a clock-to-output
delay in excess of a half clock period minus a set-up time.
Varying the clock frequency and monitoring the pulse rate
at the detector gives an indication of the probability of
metastable delays.
Over the past fifteen years this writer has made many
attempts to pin-point, demonstrate and quantify metastable behavior. Success came with the integration of
multiple test circuits, multiple detectors and a common
read-out, all in one Logic Cell Array.
The deliberate skew on the D-inputs of the eight flip-flops
under test makes it extremely unlikely that more than one
flip-flop will go metastable on anyone clock edge. The
eight detector outputs can, therefore, be ORed together
and drive a counter with LED read-out. As expected, no
metastable events were observed at clock rates below
25 MHz since a half clock period of 20 ns allows for propagation delay plus set-up time.
After so many inconclusive attempts, any repeatable results would have been appreciated, but these results also
show the metastable response of LCA flip-flops to be
superior to any othercircuil documented so far. There is
a reason. lCA flip-flops are dedicated circuits, small and
very fast, with an extremely short loop delay. TTL flip-flops
are bigger and slower, and gate arrays and gate-array-like
structures that construct their flip-flops by interconnecting
gates are bound to be far inferior.
Increasing the clock rate brought a sudden burst of metastable events around a clock rate of 27 MHz. Careful adjustment of the clock frequency gave repeated, reliable measurements showing that a 500 ps decrease in the relevant
half clock period increased the frequency of metastable
occurrences by a factor of 41. In order to be conservative,
to compensate for favorable conditions at room temperature, and to avoid any possibility of overstating a good
case, the measurement was interpreted as follows:
Metastability is still a treacherous subject, but lCAs offer
the closest thing to an acceptable solution.
,
,
//////1,
,,
J
o
D
00
0,
,
:1
,
CLB/----;",r......,
,,
CLOCK
D
02
CLOCK
.
-
COUNT PlLSE IFMETASTA8lE
REPEATED EIGHT TIMES
6-21
:
NON-METASTABLE
METASTABLE
/
I
:
1/
!f
:
,
,
:
•
Battery Backup for
Logic Cell Arrays
Application Brief BY DAVID P. LAUTZENHEISER
Logic Cell Arrays use a high performance low power
CMOS process. They can, therefore, preserve the program contents stored in the internal static memory cells
even during a loss of primary power. This is accomplished
by forcing the device into a low-power non-operational
state while supplying Vee from a battery.
Figures.1 and 2 show two circuits which satisfy the above
requirements. In Figure 1, discrete components are used
to perform the switching while the power sensing is performed by a linear circuit, the TL7705A, made by Texas
Instruments. This circuit lets the user adapt the Vcc passtransistor to the load required. The same switching arrangement might also be used to battery back-up additional circuits, such as RAMs. The user also has control
over the timing of the PWRDWN signal after Vee has returned. While the LCA only requires microseconds to
return to a normal state, other circuits may want to have a
longer RESET period.
There are two primary considerations for battery backup
which must be accomplished by external circuits:
• Control of the Power-Down (PWRDWN) pin and
• Switching between primary Vee supply and battery.
Figure 2 uses a single chip solution, the DS1259 from
Dallas Semiconductor Corporation,
4350 Beltwood Parkway South, Dallas, Texas 75244,
Telephone (214) 450-0400.
The user only needs to supply the device and battery to accomplish the desired function. The DS 1259 provides up to
250 mA of Icc with a drop of less than 0.2 Volt.
Important considerations are:
• Insure that PWRDWN is asserted logic Low prior to Vcc
falling, held Low during the primary Vee loss time, and
returned High after Vee has retumed to a normal level.
PWRDWN edges must not be slow rising or falling.
• Insure "glitch-free" switching of the power connections
to the LCA from the primary Vee to the battery voltage
and back.
In both circuits, the user must supply both bulk and high
speed decoupling. Use a large bulk capacitor in conjunction with a high speed 0.1 IlF capacitor for each Vcc pin.
Both capacitors should have low leakage to insure long
battery life.
• Insure that during normal operation the LCA Vee is
maintained at an acceptable level, 5.0 Volts ± 5% (±1 0%
for Industrial and Military).
+
BATTERY
(3.•••V)
FROM Vee
SOURCE
C>----Dt-------,
Cl--1r-----------{; :r-i-,.-..,....-o
TO Vee
10 " OF L.CA
+-_ _-V1~K~-~r-4_---~__Oro~
PIN OF LCA
• BATTERY
(3_.4V)
2 Vbat
6 RST
• Vee
7 SENSE
7 GND
2 RESIN
•
GNO
DSl25D
Pi'1-'1",-1_ _ _ _-o~~~~~~~N
19n 01
19n 02
Figure 1. Discrete Battery Backup Clrcul~
Figure 2. Integrated Battery Backup Circuit
6-22
Compact Multiplexer and
Barrel Shifter
Application Brief
FOUR-INPUT MULTIPLEXER IN ONE CLB
FOUR-BIT BARREL SHIFTER IN ONLY FOUR CLBs
Since the function generator in the XC3000 series CLB
has only five inputs, it cannot directly implement a 4 input
multiplexer which needs four data inputs and two select
inputs.
A four-input barrel shifter has four data inputs, four data
outputs and two control inputs that specify rotation by 0, 1,
2 or 3 positions. A brute force design would use four 4input multiplexers, since each output can receive data
from any input. Each four multiplexer requires two
XC3000 family CLBs, for a total of eight CLBs.
Registering one of the select inputs in the same CLB frees
up one input and puts a complete 4-input multiplexer into
one CLB. It is even possible to register the multiplexer
output.
There is, however, a smarter method that reduces the
deSign to .only four CLBs. The key to this approach lies in
the signal cross-overs althe input and output of the second
level CLBs.
This non-obvious trick increases the apparent delay of the
registered select input, but that will be acceptable in the
majority of applications. Since it reduces not only the size
but also the through-delay of the 4-input multiplexer by
50%, this approach is definitely worth considering.
o
Eight-Bit Barrel Shifter in 12 CLBs
The 4-Bit Barrel Shifter design can be extended to eight
bits. A first level shifter consisting of four CLBs rotates the
eight inputs by one position, controlled by the least significant control input. Two interleaved 4-Bit Barrel Shifters
then take the eight outputs from the first level and rotate
them by 0, 2, 4 or 6 positions.
0
l'
So
di
o
0
3'
197801
80
1978 02
6-23
8,
•
Additional Electrical Parameters
Majority Logic,
Parity
Application Brief
MAJORITY LOGIC, N-OF·X DECODING
PARITY
Majority logic has interesting mathematical features, but
has not become popular because its traditional logic
implementation is quite complicat~ and expensive.
Since LCAs can generate any functiQn of five variables at
the same cost and the same delay, they can easily decode
majority logic.
Two CLBs can generate the parity for nine inputs, or can
check a nine-bit input for odd or even parity with a throughdelay of two cascaded CLBs. Three CLBs can check
13 inputs; four CLBs can check 17 inputs; five CLBs can
check 21 inputs; six CLBs can check 25 inputs; all with the
same delay of two cascaded CLBs.
We can define the output F, Gto be Low for 0, 1, or2inputs
High, to be High for 3, 4, or 5 inputs High.
MajOrity logic is a special case of "N-of-X Deepding." A
3000-series CLB can directly encode any "N of 5" inputs
active. This concept can be cascaded so that three LCBs
encode any "N of 7" inputs active.
9 INPUTS
OPOOREVEN
1139 02
5-INPUT MAJORITY FUNCTION:
F. ABC + ABO + ABE + ACO + ACE
+AOE +SCO+ BOE + SCE+ CDE
NOF7
113901
Figure 1. N of X, e.g., Majority logic
The first-level blocks can only nave 3 inputs, since the two
outputs can only encode4 different states: none, one, two,
or three active.
6~24
Figure 2. Parity
Multiple Address Decoding
Application Brief
Address Block Detection
A 3000-series CLB can decode a 5-bit address in any
conceivable way, or it can decode a 4-bit address in two
different ways, each without any restrictions.
8
II
The idea mentioned above is not restricted to detecting
three specific addresses, it can also detect th ree groups of
addresses, as long as none of them straddles the boundaries defined by the individual CLBs. If they do, this circuit
cannot detect three address blocks, but can still detect any
one address block in an 8-bit address.
0
~I
Suppose we want to decode the block of 8-bit addresses
starting at 24 and including 68 (hex).
With one CLB we encode the least significant address
nibble into a 2 bit output called LS:
~IIIIWA
!@"al
generate LS = 1
generate LS = 2
generate LS = 3
inputs 0 through 3
inputs 4 through 8
inputs 9 through F
114001
,Figure 1. Multiple Address Decoding
With another CLB we encode the most significant address
nibble into a 2 bit output called MS:
Three 3000-series CLBs can decode three distinct
addresses in an 8-bit address field: One CLB decodes the
lower 4 bits and encodes the result on its two outputs
(00 = no match). The second CLB decodes and encodes
the upper 4 bits in a similar way.
inputs 0, 1, 7, 8 through F
input 2
input 3,4,5
input 6
The third CLB encodes the four signals into two outputs
(00 = no match). This works for any three distinct
addresses, even when some share the same upper or
lower nibble.
=
generate MS 0
generates MS = 1
generate MS = 2
generates MS = 3
The third CLB then encodes these signals
MS
This scheme can be expanded to a 16-bit wide address,
using sevenCLBs.
0
1
2
3
3
MSB 1 - - - - - - ,
LS
Output
x
0
1
1
1
0
2,3
x
1,2
3
The solution can be generalized:
Three CLBs can decode anyone block of an 8-bit address.
LSB
114002
Figure 2.
6-25
•
Binary Adders, Subtractors
and Accumulators
E:XllJXX
Application Brief
descendents. These signals can reduce the ripple carry
delay. Both CP and CG are outputs from an arithmetic
block (often of four bits). Both these outputs can be
generated immediately since they are not affected by any
incoming carry that might arrive late. As the names imply,
Carry Generate is active if the block creates an overflow
(carry), e.g. if the 4-bit sum, regardless of incoming carry,
exceeds F. Carry Propagate is active if the block does not
generate a carry by itself, but would generate a carry as a
result of an incoming carry. In our 4-bit example this
occurs when the sum is exactly F.
There are many different ways to implement binary
adders, subtractors and accumulators in Xilinx LCAs,
using different trade-offs between size and speed.
Most compact, but slowest is the bit-serial function that
operates on one bit pair per clock cycle, generating sum
and carry. The sum is fed back into the shiftregister, the
carry is stored for the subsequent bit time.
The most compact combinatorial (parallel) adder,
subtractor, or accumulator consists of cascaded CLBs.
Each CLB (XC2000 or XC3000 family) is a full adder,
accepting one operator bit pair (A, B) and an incoming
carry. The CLBgeneratesthe sum and the outgoing carry.
A 16-bit function requires 16 CLBs. It performs an
operation in 16 combinatorial delays.
There is an even faster algorithm. As originally described
by J. Sklansky in the June 1960 issue of the IRE Transaction on Electronic Computers, Conditional-Sum Addition
can save time at the expense of higher logic complexity.
Matt Klein of Hewlett Packard recently modified this algorithm to fitthe XC3000 architecture. His design requires 41
CLBs to add or accumulate two 16 bit numbers in only
three(!) combinatorial delays. With careful layout, such an
adder! accumulator can run at 30 MHz.
The 5-input function generator of the XC3000 family can
add a carry to two operator pairs. Three CLBs can thus
handle two input bit pairs, generating two sum outputs and
the outgoing carry. A 16-bit function requires 24 CLBs. It
performs an operation in 8 combinatorial delays.
Note that all Xilinx adder structures can also be an accu-.
mulator without any size or speed penalty. Conventional
gate arrays and other gate array-like structures usually
configure flip-flops out of gates. The flip-flop set up time
must then be added to the combinatorial propagation
delay. Xilinx LCAs hide the flip-flop set up time in the combinatorial propagation delay of the CLB. Adders and
accumulators thus operate at the same speed.
Carry Propagate and Carry Generate are intermediate
signals that can speed up the operation as shown on
pages 6-27 and 6-28. Such a 16 bit function requires 30
CLBs. It performs an operation in 6 combinatorial delays.
The concept of Carry Propagate and Carry Generate has
been made popular by the 74181 ALU and its
1979
6-26
Adders and
Comparators
Application Brief BY PETERAlFKE
For eight bits, this look-ahead carry scheme is of marginal
use, it reduces only the carry delay, and only by one CLB
delay. For this small speed improvement it uses two
additional CLBs (14 instead of 12). See truth table on page
6-24.
The LCA-structure accommodates 1-bit and 2-bit adders
very efficiently. A 1-bit adder with 3 inputs (A ;B, Cin)
generating 2 outputs (S, Cout) fits exactly in one 2000
series CLB, where the flip-flop might be used for storing the
carry in a bit serial adder. A 3000-series CLB can even
include an additional control input, either ADD/SUBTRACT or ADD ENABLE.
A 16-bit adder benefits from carry-Iookahead. Simply
cascading di-bit adders uses 24 CLBs at a max propagation delay of 8 CLBs from Cin to Cout orto S14, 15. A lookahead carry scheme uses 30 CLB at a max prop delay of
5 CLBs from Cin to Cout(6 delays to S14, 15).
A two-bit adder requires three 3000 series CLBs. The five
inputs AO, BO, A 1, B1, and Cin are common to all three
CLBs, the outputs are SO, S1, and Cout. The propagation
delay is only one CLB combinatorial delay, as little as 10
ns. Two such adders can be cascaded to form a four bit
adder in 6 CLBs with a through-delay of two CLBs, i.e.,
25 ns (allowing for some interconnect delay).
Four two-bit adders can be cascaded to form a byte-wide
adder, using 12 CLBs with a through-delay of 4 CLBs, but
there is also a slightly faster design using a carry lookahead technique: The third and fourth di-bit adders are
changed, they no longer generate Carry out, but now each
generates two outputs as a function of the four A and B
inputs (ignoring Cin). These two outputs are called Carry
Generate (when the addition exceeds a binary 3) and
Carry Propagate (when the addition is exactly 3). These
outputs from two di-bit adders are combined with Cin and
generate the Carry inputs to the fourth di-bit adder and its
carry out. The whole 8 bit adder uses 14 CLBs and has a
through-delay of four CLB delays from input to S6 and S7,
only three CLB delays from input to Cout.
No0-
A,
B,
A,
1--+-+---+8,
1-t-+-+-_8,
B,
.,
.,
1--+-1--1-- s,
A,
C,
co
So
S,
CP
co
I-
:=:
r-
B
•
I--++-+-+--- s,
I--I--+--I-++s,
A
B
14 CLBs
3 Delays to COUT
4 Delays to S6, S7
H-+---+8,
A,
I
I
C,
A
C,"
CP
IC,
C2
I-+---s,
I-+---s,
S3
A2=:
:=:
B
COUT
I-
A
B3 -
I1141 01
1141 02
Figure 1. 4-Bit Adder
Figure 2. 8-Bit Adder with Carry Lookahead
6-27
e.
-J
I
'-
So
=:
-J
-J
-
s,
I-
I
A.
B.
A.
B.
e2
4
_
_
_
_
f-
S.
f-
S9
I--
=:
S2
S3
-J
-J
-J
I
-
I
~
4
A,oB,oA,,_
B,,_
I--
~
-
I--
-
s,o
S"
r--
S.
S5
==
==
C'2
I--
~
~
-
~
-
~
I
I
-
-
I
r--
L.t
C.
-
~
l-
f-
I
==
-
e,o
I-
C.
=:
~
~
~
f-
S'2
S'3
A'2B'2A'3B'3-
t--
I--
eG~
~
~
S.
~
S7
r--
-
~
e,.
30 CLBs
I
5 Delays to COUT
6 Delays to S14, S15
-
r-t--
-J
A,.-t
B'4-t
A,;=:
B'5
I-
5,.
5'15
1141 03
Figure 3. 16-81t Adder with Carry Lookahead
6-28
Adders and Comparators
Adder Logic Truth Tables
Bit-Serial Adder, Subtractor, Comparator
After adjusting the subscripts appropriately. the truth table
for the three CLBs generating 8 2 and S3 is identical with
that for the CLBs generating So and S1; and the truth table
for the bottom three CLBs is identical to that of the three
CLBs generating S4 and S5'
The CLB architecture is ideally suited for bit-serial arithmetic. where the function generator performs the serial arithmetic (LSB first). and the associated flip-flop stores the
carry or borrow.
Outputs
S,=1
S,=1
Inputs
C,
1
C,=1
S5=1
CG,=1
CP,=1
A
B,
0
0
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
1
1
1
1
x
1
1
1
x
1
1
1
x
0
0
0
x
x
x
0
0
0
0
x
0
0
0
x
x
1
1
1
x
1
1
1
x
x
x
1
1
x
1
1
S._1
B,
0
1
x
Outputs
A,
0
x
Inputs
C.
1
1
1
1
x
x
1
1
x
x
1
1
1
x
A,
0
B,
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
A,
B,
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
CLOCK - - - , - - - - - '
1141
04
Figure 4. Serial Adder/Subtractor
A bitcserial identity comparator detects only whether the
two operands are equal or not. without determining which
one (if any) is larger. The bit stream can come in LSB or
MSB first. the flip-flop gets set for any difference between
A and B. and stays set until the end of the word. then gets
reset before the beginning of the next word. This "difference detector" can also be implemented as a latch and
folded into the combinatorial logic.
1
Abit-serial magnitude comparator distinguishes between
A = B. A > B and A < B. It can operate LSB first or MSB first.
if the logic is adjusted:
LSB first: Start with both flip-flops reset
0
0
1
()
0
1
1
1
1
x
1
1
1
x
1
1
1
x
x
0
0
0
0
x
()
if A > B set Ox. reset Oy
if A < B set Oy, reset Ox
MSB first: Start with both flip-flops reset
if A > Band Oy = 0: set Ox
if A < B and Ox = 0: set Oy
x
x
0
0
1
1
1
()
x
0
0
0
0
()
x
()
x
1
1
1
x
1
1
x
x
x
x
x
x
x
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
()
1
Q
1
1
A
1
1
1
0
1
1
1
0
0
0
0
0
1
B
x
x
x
Q
B
ADDISUBTRACT
0
0
0
0
I---*"---*I 0
A
The 16-bit adder is a natural extension of the 8-bit adder.
1
()
Result in both cases:
Qx
Qy
o
0
1
0
o
1
Impossible
1
1
Ox
Inputs
Lower
Outputs
Higher
Oy
C,.
CP
CG
CP
CG
Lower
Carry
x
x
1
1
1
x
x
x
x
Higher
Carry
x
x
x
x
x
x
1
0
1
1
0
1
1
x
1
Oy
1141 05
x
CLOCK _ _ _ _ _...1
Figure 5. Serial Magnitude Comparator
6-29
•
Conditional Sum Adder
Adds 16 Bits in 33 ns
Application Brief BY MATI KLEIN, HEWLETI·PACKARD
This circuit is based on a 1960 paper by J. Sklansky (see
page 6-26). With careful placement and routing the total
delay can be kept below 33 ns.
subscripts denote the binary positiDn (weight), and superscripts describe the assumed input condition:
The block diagram below shows each CLB and its inputs
and outputs.
0: carrry into this position is assumed inactive
"0: carry into the position one lower is assumed inactive
1 : carrry into this position is assumed inactive
"1: carry into the position one lower is assumed inactive
27 of the CLBs each generate one function of up to 5
variables, 14 of the CLBs each generate two functions of
four varibles. In accordance with the original paper all
A complete LCA file is available from Xilinx Applications
and will be published in XCELL.
CoAoBo
r::l _ A2B:.
=t:r
r+~~----------~==~------------------,
CoAoBoA'B,tt
A2B:.A, B3
A,.B,.A 15 B15
1988 01
16-Bit Conditional Sum Adder
6-30
Building Latches
Out of Logic
Application Brief
Since the 3000-series, unlike the 2000-series, cannot
configure its CLB flip-flops into latches, there must be
other ways to design latches. Obviously, the I/O block can
be configured with latches on either the input, the output,
or both. Beyond that, every CLB can form a latch.
Sand R (again 16 different flavors) or we use multiple S
and multiple R, either ORed, or ANDed, or XORed. We
can also have two D inputs, each with its own Enable; or
we can have two D inputs, a Select input and an Enable
input; orwe can have an Enable and three D inputs defined
in any arbitrary way. Majority gating could be one way: if
none or one is active, reset the latch; if,two or three are
active, setthe latch. Or, if none is active, reset; if oneortwo
are active, hold; if three are active: set. Orwe can assign
positive or negative weights to the D inputs.
The five-input logic structure allows an amazing diversity
of latch designs: four examples are documented in the
3000-series Macro Library on page 15 and 16. Here are
additional ideas:
With F fed back to close the feedback path, there are four
control inputs left. We might call them Set, Reset, Data
and Enable, defining them such that Sand R are independent of E, but D is activated by E. We can still define any of
these four inputs as active High or active Low. That gives
us 16 different latch designs, all with the same basic
characteristics and the same timing.
Since there are 65,536 differentfunctions offourvariables,
there are many different ways to define a latch, not
counting pin rotations and active High/active Low variations.
All these latches have the same timing characteristics:
propagation delay from input to output = 14/9 ns for the
50/70 MHz part. Set-up time to the end of Enable, or min.
Enable width = 19/14 ns assuming 5 ns interconnect delay.
We can also eliminate D and have two Enables, affecting
D
EN.D
SET
RESET
D1
EN.01
02
EN.02
RESET
EN.RES.
SET 1
SET 2
RES 1
RES2
01
02
SEL.
01
D2
03
SET
EN.SET
EN
EN.
114201
Figure 1. Latched Logic
6-31
II
Additional Electrical Parameters
Synchronous Counters,
Fast and Compact
Application Brief
FULLY SYNCHRONOUS 4·BIT COUNTER USES
ONLY TWO CLB'S TO COUNT ANY CODE
FULLY SYNCHRONOUS 5·BIT COUNTER USES
ONLY THREE CLBS
This four-bit counter operates synchronously and has a
Count Enable(Clock Enable) input. Count length, count
direction, and even the code sequence can be selected
through configuration. There are 15!, i.e. more than 10,2
different possible sequences. All four outputs are available. This counter cannot be preset to an arbitrary value,
but it can be cleared by an asynchronous input.
Three 3000-series CLBs can implement a modified shiftregister counter with the following features:
• Fully synchronous operation
• Count Enable Asynchronous clear
• Count-Modulus defined during configuration: 2 ... 32
as, but with complete
ANY SEQUENCE:
• Only one meaningful output,
freedom to define its waveform
BINARY
GRAY
BCD
X3
X3·GRAY
BIQUINARY
ETC.
00 through 04 form a linear shift register counter. The 5
input combinatorial function FO determines the modulus
(there are no illegal or hang-up states). The 5-input
combinatorial function Fl decodes the counter in any
synchronizes and de-glitches Fl.
conceivable way,
as
Examples:
114301
Figure 1. Synchronous 4-Bit Counter in 2 CLBs
+ 28 counter with output High at times
T2, 3, Tl0, T22 through T27
The advantage of a Gray code is its glitch-less decoding,
since only one bit changes on any code transition. A Gray
counter can also be read "onethe-fly" without the wellknown problems of reading a binary counter e.g., on its
transition between 7 and 8, where any code might be read.
+
1(·;·:···········
Decimal
Binary
Gray
X3 Binary
X3 Gray
0
1
2
3
4
5
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
6
7
8
9
10
11
12
13
14
15
i
~~
19 counter with output Low at times
T9, T12, T15, T18.
.......................................................;.:.;.:.:.:.:.:.:.:.: .......................................................................:.:.:.:.:.:.:::::.;.:.:.:...:.:...........
i
0,
03
0,
0,
00
~(}&--
°3
02
0,
00
F,
Os
ENCODED OUTPUT
(ANY PATIERN)
27
0
e.g .• ~
1144 01
Figure 2. Synchronous 5-Bit Counter in 3 CLBs
6-32
30 MHz Binary Counter Uses
Less Than One CLB per Bit
Application Brief BY PETERALFKE
The least significant tri-bit thus stops the remaining
counter chain for 7 out of 8 incoming clock pulses, allowing
ample time forlhe CEO-CET ripple-carry chain to stabilize.
Max cloCk rate is determined by the first tri-bit's Clock-toCEOdelay (TOKO +TllO), plu5the CEP input set-uptime
forall othertri-bits (TICK), pluS the routing delay ofthe CEP
net. In a-70 device this sum can be below 32 ns. The
highertri-bits are not speed critical if they propagate the
CET signalin less than eight clock periods, easilyachievable for counters as long as 20 tri-bits, i.e. 60 bits.
Borrowing the concept of Count Enable Trickle/Count
Enable Parallel that was'pioneered in the popular 74160
TTL -MSI counter, a fast non-Ioadable synchronous binary
counter of arbitrary length can be implemented efficiently
in the XC3000 series CLBs. For best partitioning into
ClBs,the counter is segmented into a series of tri-bits.
The least significant (i.e. the faslest changing) tri-bithas a
Count Enable Output (CEO) thaJ is routed to all the Count
Enable Parallel (CEP) inputs of the whole counter.
The two least significant .tri-bits each have a single Count
Enable input; they fit, therefore, in only two ClBs, each.
The highertri-bits have two Count Enableinputs (CEP and
CET) and require tHree ClBs.
Each Count Enable Output from any other tri-bit drives the
next more significant Count Enable Trickle (CET) input
The clock causes any tri-bit to increment if all its Count
Enable inputs are active. CEO is active when all three bits
are set AND CET isHigh. CEP does not affect CEO.
ETC
30 MHz Non-LoadabJe Binary Counter, Expandable up to 60 Bits
1980 01
O.
~
. .,
00
1980 02
'"
.
'D",
,
'
•
°c
'
First and SilcondTri-Bits Use Two CLBs Each
Q"
".
CET~
OB,'
00
1980 03
All More Significant Trl-Blts Use Three elBs
6-33
:
CEO
Up/Down Counter Uses
Less Than One CLB per Bit
Application Brief BY PETERALFKE
A fully synchronous resettable but non-Ioadable up/down
counter of arbitrary length can be implemented with only
one XC2000 CLB per bit. This design cascades the toggle
information from the least significant toward the most
significant position. Such an architecture reduces the
maximum clock rate for longer counters, from 30 MHz for
2 bits, to 10 MHz: for 8 bits, down to 5 MHz for 16 bits,
assuming a -70 part. This simple design is, therefore, not
suited for high speed clocking, but it generates fully syn-
chronous outputs; i.e., all flip-flops clock on the same
edge.
The better functionality of the XC3000 CLBs can cut the
cascaded toggle control delay in half by looking at two
counter bits in parallel. This doubles the max frequency for
a given counter size. A 16-bit counter in a -70 part can
count 10 MHz, guaranteed worst case.
"'\
UP/DOWN
I
Count Enable
IN
,.........
I
) >-n
Count Enable
X
0 UT
I
1
1))- D
y
Q
>
1981 01
CEO
eEl
-t--t+---.---+-----t--+----'
1981 02
6-34
Loadable Up/Down Counter
Uses One CLB per Bit
E:XllINX
Application Brief BY PETERALFKE
control circuit is moved to a separate CLB which serves
two counter bits simultaneously. This cuts the effective
ripple delay in half. A 16-bit counter in a ~70 part can count
10 MHz, guaranteed worst case.
The five-input function generator of the XC3000 family
CLBs makes it possible to build expandable fUlly
synchronous /oadab/e up/down counters of arbitrary
length using only two CLBs per two bits, Le. one CLB per
bit.
The CEP/CET speed enhancement cannot be used on updown counters that might reverse their direction of count in
any position. They can, therefore, not guarantee a defined
number of clock periods for the ripple-carry chain to
stabilize.
The basic concept is similar to the non-Ioadable up/down
counter described on the previous page. The function
generator driving the counter flip-flop has two additional
inputs (Parallel Enable and Data). The cascaded toggle
ca--~~============~-----'
u~~--~~~===r,
CEO
II
PE--~--~------------~----~
1982 01
6-35
30 MHz Binary Counter with
Synchronous Reset
I:XlllNX
Application Brief BYPETERALFKE
In many applications, design modularity is more important
than highest clock speed and best space efficiency. This
applications brief· describes a counter design that uses
identical CLB primitives, one CLB per bit. The Count
Enable Trickle/Count Enable Parallel concept, introduced
by the 74160 family, is changed here to a one-bit block
size. Any block increments only if both Count Enables are
High, but the outgoing count enable (COUT) is not a
function of CEP. The CEP input thus prevents erroneous
counts while the ripple carry chain is settling.
A shorter counter (6 bits or less) drives the CEP net from
the Qo output, achieving a 40 MHz speed. A longer
counter generates a 1-in-4 duty cycle on CEP and runs at
30 MHz up to 12 bits long, or at 25 MHz up to 18 bits long
as shown below. In order to achieve this performance,
CEP and R must be driven by long lines.
ETC TO 017
RESET~·~~-----+++------~~------HH-------+~------~~
CLOCK--~------+-~----~~-------r~------+-~----~~
00
01
198301
CEP
R~~~.------------~
CLOCK-..::tr;----------------~-----I>
CLB PRIMITIVE, ONE PER BIT
6-36
o
198302
Fast Bidirectional Counters
for Robotics
Application Brief BY PETERALFKE
The position of a robotics arm is usually determined by
three shaft encoders consisting of up/down pulse generators and counters. Ata maximum speed of 5 meters per
second and a resolution of 1 micron, these counters must
resolve 0.21-1S pulses and should have a capacity of at least
2 million steps. The counters must have an easy interface
to the microprocessor so that the count value can be read
on-the-fly, without ambiguity.
Communication between these two parts of the counter is
through a carefully controlled mailbox. Whenever the 4,bit
up/down counter reaches plus or minus 8, it sets a carry or
a borrow flip-flop. The shift register counter accepts these
inputs synchronously, with a max delay of 1 microsecond.
When the microprocessor wants to read the counter, it first
disables the interaction between the two parts of the
counter. Then both parts are transferred into 240I,Jtput
registers and the counter interaction is enabled again.
This mechanism insures reliable read-out, even if the
counter is oscillating around certain critical values.
The established microprocessor peripheral counters have
severe limitations. They are too short, lack up/down control or quadrature clock inputs, and cannot be read easily.
The problem of a traditional up/down counter is that it can
oscillate between two values where all (or most) counter
bits change at the incoming count rate. This makes a reliable microprocessor interface virtually impossible.
Now Xilinx suggests a design that packs three 22-bit
counters into one Logic Cell Array, the XC3020. Max count
rate is 8 MHz, and Ihecount values can easily be read onthe-fly. The counter architecture is somewhat unconventionaLEach counter consists of two parts:
In this design the most significant 20 bits otthe counter do
not have this problem, and the least significant 4 bits count
in a Grey code, where only one bit changes on any clock
transition. Such counters can safety be read on-the-fly.
This safe and compact design puts one additional burden
on the microprocessor: The two parts of thecountermust
be added in software, since they have independent signs.
1; A conventional up/down 4-bit Grey-code counter with a
cilpacity from -8.to +7. Thiscounter is asynchronous to
the system clock, affected only by the incoming clocks.
2. A 20-bit up/down counter in the form of a 20-bit recirculating shift register, a serial adder/subtractor, and a
carry/borrow flip"flop. This shift register forms the most
Significant part of the counter. Synchronous with the
LCA clock, itis easily synchronized to the microprocessor clock. At a 20 MHz clock rate it recirculates once,
and can be incremented, decremented, and also read
or preset, once per microsecond.
Speed can be increased to 20 MHz by changing the partitioning from 4/20 bits to 8/16 bits. The up/down count
control can be implemented in several different ways.
CLOCKS
Handshake
1984 01
Figure 1. Triple 22-.8it Up/Down Counter with Microprocessor Interface
6-37
l:xuxxx
40 MHz Presettable Counter
Application Brief
This application note describes a new counter architecture
used to implement a very high speed presettable. up to
40- bit long binary counter in an XC3020 Programmable
Gate Array. The design can easily be modified to implement two 20-bit counters, orthe equivalent BCD counters.
Carry Propagation:
• Since a presettable counter only decodes one state, TC,
the decision to toggle any of the more significant bits can
be delayed and thus pipe lined without any problem.
The counter is divided into a number of small sections,
each two bits (a dibit) long, implemented as a synchronou s
presettable down-counter, with carry-in (=count enable),
parallel enable and two data inputs. Terminal count (0.0)
is decoded with an additional input coming from the next
higher section. The least significant section decodes the
state prior to TC, its output activates the parallel enable for
all counters. The carry function between sections is
pipelined. The carry flip-flop is set when carry-in is active
and the dibit is in state 00. The carry flip-flop stays set for
only one clock period, its output drives the carry-in function
of the next higher section. As a result of this pipe lining, the
counter can be made arbitrarily long, without any speed
penalty. Note that each dibit, except the first, makes its
transition n clock pulses later than required by the binary
code sequence (n is the relative position of the dibit, n=O
forthe input dibit). This code violation has no impact on TC
decoding. This counter can be four times faster than
presently available standard microprocessor peripherals
like the 8254 and 9513. Typical applications are in
instrumentation and communications, e.g., as the frequency determining counter in a phase-locked-loop frequency synthesizer.
Traditional counter designs always represent a comJ?romise between two conflicting goals: highest clock speed/
event resolution on one hand, sophisticated features (like
preset to any arbitrary value, or decode any state) on the
other hand.
Asynchronous ripple counters offer highest speed, but
cannot be decoded in one clock period, thus cannot be
made programmable.
Synchronous counters allow decoding and presetting in
one clock period, but pay for this with complex carry logiC.
Carry propagation is always the limiting factor in the
traditional design of presettable synchronous counters,
since the complete carry chain must reach a steady state
before the next incoming clock edge. Brute force parallel
decoding of all previous states becomes unmanageable
beyond 8 stages, but cascaded decoding introduces
additional delays. Either approach reduces the inherent
resolution of the counter.
Decoding Terminal Count (TC) in order to preset the
counter again, poses a similar problem. The design
described in this paper separates the two functions of the
carry chain into:
Different from conventional synchronous counters, the
speed ofthis design is independent of its length. All speedcritical paths are single-level, their interconnect delay can
be kept below 9ns, which means that a -70 device can
count at a 40 MHz rate (worst case).
• One which decodes the terminal count of the whole
counter and generates a Parallel Enable signal
• One which propagates the carry signal from the less
significant to the more significant bit positions, and
causes the appropriate flip-flop to toggle.
MSB + n=2
Cascaded TC Decoding:
1145 01
c~~ ; (
il
40 BITS
~
LSB
n=O
n=l
1
1
010
o
0
1
o
0
0
• The TC decoder must receive inputs from all counter
bits, but only the LSB timing is critical, the more significant bits have been stable before. TC can, therefore, be
decoded in a slow gating chain that starts at the most
significant end of the counter.
PE
BYPETERALFKEANDPERRYWU
o
1
1
010
1145 02
TC
6-38
1~Wf1
-
-
CARRIES
................................................;:..•.
......................} .................
CI-"-~----+--~----;~
bJU
PE----.---'
PE
Do------L..I
D1
o
1.1;;
co
i
.............................
:;
TO-------------------------~;----------'
CI ~ Carry In
CO ~ Carry Out
~ Parallel Enable (Active Low)
TI ~ Terminal Count In
TO ~ Terminal Count Out
PI':
'-----TI
..............)
::.....
Any Dibit Except the Least Significant
....
~."
1145 04
....................,.,.........................1'
a
CARRY
DO
RD
....•.•.•.......•;;
fiE
. . . . . . . . . . . . . . .J
TO ALL 0lBIT8
TI
CE
~
a
Clock Enable
TERM.
COUNT
RD
PRESET----------------------------------------------;~--------------------~~----J
Least Significant Dibit
114505
PRESET
START/STOP
HIGH
Most Significant Dibit
Least Significant Dibit
Synchronous Presettable Counter--40 Bits in 60 CLBs
6-39
114503
40 MHz Counter
Since this circuit was first published in mid 1988, several
designers have used it to create fast counters.
In the unlikely case where this might cause a problem,
most TC pipeline flip-flops can be eliminated. They were
inserted to simplify modeling and because they are
available for free.
There have also been many questions about the rather
terse description and about an error in the schematic
drawing (the AND gate generating PEl that has been corrected in this printing.
Why Is the least significant dibit different?
What Is the function of the TC pipeline flip-flop,
formerly called Q3?
In orderto achieve a40 MHz clock rate, the PE Signal must
be made as fast as possible. It has to come directly from
a flip-flop output so that the sum of clock-to-output delay,
routing delay, and input set-up time is kept below 25 ns.
The unconventional idea behind this counter design is that
Terminal Cou nt decoding can be "rippled" from the MSB to
the LSB, i.e. against the direction of carries. This is
possible because the high order bits reached theirTC long
before the LSB does.
The position of the LSB TC pipeline flip-flop is, therefore,
changed, so that it detects the TC-1 state (in a downcounter, that is state 1).
The flip-flop output is made active Low PE so that the
asynchronous clear input can be used to force the counter
into loading.
There is, however, a potential problem when the counter
is being preset to a value with a string of LSB zeros. Let's
assume the worst case where the preset value is all Zeros
except a single One in the MSB position:
For operation below 30 MHz the least significant dibit can
be like all the other dibits, but PE must be excluded from
the AND gate generating PE, and the user may want to
adjust the polarity of the last TC pipeline flip-flop to
facilitate the preset function mentioned above.
When this counter reaches the all-zero Terminal Count,
PE is activated and the counter is preset. This action
should obviously de-activate the TC decoding, but in the
given example a simple ripple decoder would have a very
long delay. It might take 400 ns for the MSB= 1 condition
to ripple down through a 40 bit decoding chain. Such a
delay would defeat the concept of the counter, reducing its
max clock rate to 2.5 MHz. A better way must be found to
de-activate TC within 25 ns.
Where should this design be used?
The TC pipeline flip-flop and the inclusion of PE in the AND
gate that detects TC, reliably de-activate TC and thus PE
one clock after they have been activated. This has one
side effect, however: It makes it illegal to presetthe counter
to very small numbers (less than 10 for a 20-bit counter),
since the TC-pipeline takes that many clock pulses to
become active again.
For the intended application, timebase counters or
frequency synthesizers, this design offers the highest
possible count speed.
This counter design achieves high performance by using
several logic ''tricks''. It generates incorrect outputs when
undigested carries sit in the carry flip-flops. That makes
this design useless for any parallel application like DMA
counters.
Asynchronous Preset in XC3000 CLBs
The XC3000 CLB lacks the asynchronous preset capability available in the XC2000 CLB. Some designers are looking for this feature. Here are several solutions:
3.
1.
The design can usually be transformed into a synchronous solution where all flip-flop changes occur as a result
of the same clock edge.
If asynchronous preset is needed, but no asynchronous clear:
Turn the flip-flop upside down, i.e. invert the D input
and the Q output and considerthe asynchronous clear
a preset. These inversions of D and Q come for free
in a Xilinx LCA. Note, however, that the flip-flop will
now come alive in the apparent preset state.
2.
If the circuit really needs asynchronous preset and
clear(or asynchronous data transfer) in a flip-flop, the
problem must be solved on a system level:
Truly asynchronous parallel data transfer into several
clocked flip-flOps is inherently unreliable and must be
avoided. If, however, the transfer pulse is synchronized
with the clock, it should not be too difficult to change the
design to utilize the clock for loading.
If the circuit needs both asynchronous preset and
clear, chances are that the function can be performed
by a latch. The XC3000 CLB can implement complex
latches in its fu nction generators (see page 6-31).
Asynchronous data transfer was popular in early TTL MSI
Circuits deSigned in the late sixties, e.g., the 7494 and
7496. It is time to getaway from the limitations of the past.
6-40
Frequency/Phase
Comparator for
Phase-Locked-Loops
Application Brief BY PETERALFKE
A Phase-Locked-Loop (PLL) manipulates a local voltagecontrolled oscillator (veO) so that it is in phase with a reference signal. One popular application is a programmable
frequency synthesizer for radio communications. Here a
crystal oscillator is divided down to a low reference frequency of 5 kHz, for example.
only to pull in a small phase error, but also to correct a large
frequency error. It may not generate false outputs when
the input is at a multiple or fraction of the desired frequency.
The well-known circuit shown in Figure 1 performs this
function. It generates "pump-up" pulse when the veo
frequency is too low, "pump-down" when its too high. The
multiple feedback network assures proper operation even
at large frequency errors.
A programmable divider scales the veo frequency down
to the same reference frequency. The two counter outputs
are compared to generate a signal that, when required,
modifies the veo frequency up or down until the two comparator inputs are not only of the same frequency, but also
in phase.
Figure 2 shows this circuit implemented in two eLBs plus
two lOBs, directly driving the integrator (low pass filter)
controlling the veo. The LeA solution has been
breadboarded at 10 MHz. It achieved a phase error of less
than 2 ns.
This frequency/phase comparator must have a wide capture range, i.e. it must generate the appropriate output not
............................................................"'::
FROM
DIVI~~g+---++-_....J
BYN
t.. . ,. .~.~.~. ~. :-. ,. .:-:. . .,. . . .:. . . . .:-. . . . :.:-. . . :-. . . . . . . . . . . . . . . . . . . ". . . . . . . . . . . . .J
III
FROM
REFERENCE +--++-_....J
FREQUENCY
198501
Figure 1. Digital Frequency/Phase Detector
ToveD
+2.5 V
1985 02
INTEGRATOR
Figure 2. Frequency/Phase Detector Using Four Blocks
6-41
Gigahertz
Presettable Counter
Application Brief BY PETERALFKE
Some frequency synthesizers for communications, e.g.,
cellular telephone networks, require a clock frequency of
hundreds of megahertz, up to a gigahertz. Obviously, the
LCA cannot operate quite that fast, but with the help of a
2-modulus prescaler, the LCA can implement a fully presettable ultra-fast counter, resolving time in increments of
one clock period, as small as 1 ns at 1 GHz.
a smart but slow counter (in the LCA) to achieve the
performance of a fast and smart, fully presettable counter.
The prescaler divides by either n or n + 1, depending on
the state of the control input. In other words, it "swallows"
one additional clock pulse if told so by the control input. By
keeping the control input active forthe appropriate number
of prescaler output periods, the LCA can fine tune the total
divide ratio to any integer number.
Prescaling is the obvious method to adapt a slow device to
a high clock rate. Simple prescaling by a fixed number,
e.g. 8, 16, or 64, however, reduces not only the clock rate,
but also the resolution. If, for example, the GHz clock of a
phase-locked-loop synthesizer is first divided by 64, then
the whole presettable counter is clocked at this lower rate.
For a 25 kHz channel spacing, the PLL must, therefore,
operate at 25 kHz + 64, i.e. less than 400 Hz. This results
in slow response and might produce excessive phase
jitter.
Well, there are some impossible numbers:
When the prescaler divides by either n or n + 1, then the
system cannot divide by certain numbers below n (n-1).
An 8/9 prescaler has blind spots below 56
A 64/65 prescaler has blind spots below 4,032
A 128/129 prescaler has blind spots below 16,256
This limitation is usually of no practical consequence in a
real design:
A "Pulse Swallowing" 2-modulus prescaler, originally
described in 1970 by John Nichols of Fairchild Semiconductor Applications, avoids this drawback. Pulse swallowing combines a fast but dumb counter (the prescaler) with
The prescaler-LCA combination can divide by any integer
number higher than the values above.
INPUT
200 MHz
OUTPUT
0.280 ~s
0.285 ~s
0.290 ~s
Example 1:
200 MHz clock, 12-bit
presettable time base generator
achieves 5 ns output resolution.
20.475 ~s
20.480 ~s
INPUT
450 TO
1000 MHz
OUTPUT
TO 25 kHz
PHASE-LOCKEDLOOP
Example 2:
450 to 1000 MHz clock, 16-bit
presettable counter achieves
25 kHz channel spacing with a
25 kHz phase comparator frequency.
6-42
E:XIUNX
o ori------------------TC=PE
CP
°7
06
Os
°4
00
°6
03
°2
°1
00
CLBM7
°4
03
°2
°1
°0
Os
°2
°0
°1
°4
1988 01
00
°1
°2
TO
03
TC
00
01
...
PE+----~
Dl~------_L__J
°1
1988.02
3-Bit Presettable Down Counter with
Pipelined Terminal Count, Locking Up on TC
PE
9-Bit Presettable Down Counter with
Decoded Terminal Count (Te)
6-43
100 MHz Frequency Counter
Application Brief BY PETERALFKE
The block diagram below describes a complete 100 MHz
frequency counter in an XC3020.
nously, each decade consisting of a synchronous BCD
counter.
A 32,768 kHz crystal oscillator generates a time base of
two seconds. The frequency to be measured clocks an 8digit BCD counter. At the end of the measuring period of
two seconds the counter content is transferred into four
shift registers, and the counter is then reset before the
beginning of the next measuring period. The shift register
drives a multiplexed 8-digit, 7 segment LED or LCD
display.
The high resolution of 100 MHz or 10ns is achieved by
using the divide-by-two flip flop driven by the alternate
clock buffer. This is the simplest and therefore fastest flipflop on the device.
The whole frequency counter uses 51 of the 64 CLBs in an
XC3020:
Time Base
BCD Counter
5 Shift Registers
7-Segment Encoder
Leading Zero Suppressor
Control
The oscillator uses three lOBs, since the dedicated crystal
oscillator input is already used as signal input.
The time base is already generated by a.16 bit binary
counter consisting of four asynchronously c~scaded 2-bit
synchronous counters. The control unit eliminates the
clock ripple delay by re-synchronizing the time base output. The eight counter decades are cascaded asynchroXC3020
LSD
fin
8 CLBs
16 CLBs
20 CLBs
4 CLBs
1 CLB
2CLBs
r--r+-r--,
i..
(0 ...1ooMHz)
'61
a:
IIII
50 MHz
a-Digit
BCD
Counter
-=:E
I
en
.
..,
....
CD
I:
aI
a-Digit
co
MSD
LED
Matrix
I!!
!
Leading
Zero
Suppress
~I:
aI"
.!!O
0
..,t
4
0
U
I:
W
.
C
E
en2'
,:.
1129 01
Figure 1. Block Diagram
6-44
&XILINX
l:XllINX
Serial Pattern Detectors
Application Brief BY PETERALFKE
ously shifted-in pattern, using only one XC3000-seriesCLB per pattern bit. The output of the comparators are
ANDed with 3-state buffers on a long line. The desired
pattern is first shifted through the DIN input into the Y-flipflop, and then routed to the DIN input of the next CLB.
FIXED PATTERN DETECTOR
This circuit compares a serial bit-stream against a predetermined (configured) pattern. Two bits are compared in
each XC3000-series CLB. The outputs of the comparator
are ANDed in with 3-state buffers on a long line.
When the complete pattern has been shifted in, it is transferred with one clock pulse to the X-flip-flops, using the
lower half of the function generator. Data to be detected is
then shifted inthrough the DIN input intotheY-flip-flop, and
from there to the DIN input of the next CLB. The upper half
of the function generator compares the content of Ox and
Oy, and indicates a match on the CLB output. For identity
comparison, these outputs are ANDed through 3-state
buffers driving a long line.
Data is shifted through DIN into the Y-flip-flop, then shifted
through the upper half of the combinatorial array into the
X-flip-flop of the same CLB. From there it is routed to the
DIN input of the next CLB.
The lower half of the combinatorial array compares the
content of the two flip-flops against data supplied on the A
and D inputs. A match is indicated on the G output and
routed to a 3-state buffer driving a long line.
This circuit can also be used as acorrelator, inwhich case
the outputs must be summed in a Wallace-type adder.
DYNAMIC PATTERN DETECTOR OR CORRELATOR
This circuit compares a serial bit stream against a previ-
~-...,.
LONG
LINE
•
LONG
LINE
DIN
DIN
114702
114701
Figure 2. Serial Comparator Finds Pattern Match or
Correlates Patterns
Figure 1. Fixed Pattern Detector
6-45
Incorporating PLD Equations Into LCAs
Serial Code Conversion
Binary to BCD
Application Brief BY PETERALFKE
CONVERTJSHIFT
1146 03
Figure 1. Binary to BCD (MSB First)
The LCA architecture with its powerful function generators
evenly interspersed between flip-flops lends itself very
well to serial code conversion, where data is shifted into a
register in one format, and shifted out of the same register
in a converted format.
MODIFY
A binary to BCD converter requires 3 CLBs for every 4 bits
of BCD output (i.e., for every digit). Data is shifted in
serially, most significant bit first. Each shift thus doubles
the content of the register.
f----~D
°3
In order to stay a valid BCD number, a 4-bit number of 5 or
greater must not just be shifted, but must be converted into
the proper BCD representation of its doubled value: A·
"one" is shifted into the next higher decade and the 5 is
converted into a 0, a 6 into a 2, a 7 into a 4, an 8 into a 6,
a 9 into an 8. When the binary LSB has been shifted in,
BCD data is available in parallel form, ·or it can be shifted
out serially with the conversion logic disabled.
MODIFY:
5~OJ
SHIFT
6'-'2, 7-+4, 8-+6,9 ...... 8
MODIFY
0 2 - 0 3 - 0 0 · 'lI
°1-02-~ XNOR
° 0 _ 0 , _ °0
03----+°34---- 03
a..
114601b
114601a
Figure 2. Binary to BCD converter 3 CLB's per 4 Bits:
MSB First
6-46
Serial Code Conversion
BCD to Binary
Application Brief BY PETERALFKE
CONVERT/SHIFT
o·
o
114604
Figure 1. BCD to Binary (LSB First)
......... J
The LCA architecture with its powerful function generators
evenly interspersed between flip-flops lends itself very
well to serial code conversion, where data is shifted into a
register in one format, and shifted out of the same register
in a converted format.
r--
A BCD-to-binaryconverter requires 3 CLBs per digit. BCD
data is shifted in, least significant bit first. Once the
complete BCD word has been shifted in, the conversion
process begins, shifting out binary data, LSB first.
-
.---
CONVERT
MODIFY
--~
Each shift divides the content by two. When the LSB of a
BCD digit is a "one", shifting it one position down would
give it a weight of 8 in the lower decade instead of the
weight of 5 appropriate for a 10 divided by 2. A value of 3
is therefore subtracted from the content of the decade
whenever a "one" is being shifted into it.
.--°1-<1
r--
This design can be made smaller and faster by starting the
conversion before the most significant BCD digit is being
shifted in. Since these converters can be laid out with very
short interconnect delays, they can operate at up to 60%
of the specified toggle frequency, i.e. 42 MHz for the -70
parts.
-
°1-<1
°2-<1
r-t
~
MODIFY: 0 -to- 5, 2-+ 6, 4-+ 7,6 ...... 8, 8 -+ 9
SHIFT
~U
.---
-
° 1 -0 0 - c : l ' 1
02 - 0 1 01 XOR 02
0 3 -0 2 - c : l ' 3 AND (c:l'10R c:l'2)
0'0 - 0 3 03 OR (01 • 02)
D
°11---
-~U
--
~J
D
°2-<1
MOOIFY
,..--
0,
'---
-:J
1146 02b
114602a
-
Figure 2. BCD to Binary converter 3 CLB's per 4 Bits:
LSB First
6-47
•
Incorporating PLD Equations Into LeAs
"Corner Bender" or
a-Bit Format Converter
Application Brief BY PETERALFKE
Pulse Code Modulation (PCM) has become the dominating encoding method in digital telephony. Analog signals
are sampled at 8 kHz and represented by their 8-bit digital
equivalent, using a logarithmic encoding scheme, Il-Iaw in
the US and Japan, A-Law in the rest of the world using the
CCITT standard.
XC2064
OR
8
1/2 XC3020
These eight bits are usually transmitted serially (the T1
standard time-multiplexes 24 channels on a single wire at
1.544 MHz. The CCITT standard time-multiplexes 32
channels at 2.048 MHz.
1122 03
In the central office or PBX, however, the eight bits
representing one particular sample must be routed
together. The telephone system thus uses a large number
of serial-to-parallel and parallel-to-serial converters, all
operating on 8-bit words, all running synchronously. Eight
Sop converters with 8 data inputs and 8 data outputs can
easily be combined in one package. Eight serial data
streams are shifted in simultaneously. After eight clock
pulses the eight serial words can be shifted out in parallel,
one word per clock pulse, and newserial bits can be shifted
shifted in simultaneously. It is interesting to note that the
same circuit can also accept parallel words and shift them
out in eight serial streams. The difference between Sop
and P-S is not in the circuit, but in the mind ofthe beholder.
OUT
I0
I0
I0
I0
I0
I0
I0
I0
CORNER
BENDER
J}
1 71
1 71
I 71
71
71
71
71
71
Such a "Corner Bender" is available as a standard part, the
Plessey MJ 1410 8-Bit Format Converter. Its drawbacks
are high power consumption (max 500 mW) and slow
speed (2.4 MHz guaranteed worst case), a result of its
nMOS heritage.
This design can be simplified and made to fit into an
XC2064 or half an XC3020.
112201
1
1
1
1
1
1
~
OUT
6-48
I
I
10 1
10 1
10 1
101
10 1
101
I01
I01
"Corner Bender" or S-Bit Format Converter
The LCA implementation of a 2-dimensional shift register
is straight forward:
A common clock drives all flip-flops, organized in an
8x8 array. In mode A each flip-flop receives data from its
"left" neighbor, in mode B each flip-flop receives data from
its neighbor above.
For the first eight clock pulses the array is in mode A,
receiving 8 bit streams and right-shifting them into the
array. Forthe next eight clock pulses, the array is in mode
B, down-shifting the previously received 64 bits.
-- ----- ----- ----- ----- - ---- - --- - ----
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PHASE A
New serial data can be shifted in from one side while old
parallel data is being shifted out at the opposite side.
There is no need for any ofthe additionalflip-flops required
by the older designs.
After eight clock pulses the mode control is again changed
to A and old data is shifted out on the right side while new
data is shifted in from the left.
This design uses only 64 flip-flops, and a mode control
Signal derived from a divide-by-8 counter.
The physical routing of the input signals can be done onchip, but the eight bottom output pins must externally be
wire-ored with the eight right-hand outputs.
PHASE B
The design fits exactly into one XC2064 or into half of an
XC3020 and can run at up to 35 MHz.
6-49
112202
Incorporating PLD Equations Into LCAs
Megabit FIFO in Two Chips:
One LCA and One DRAM
I:XUXNX
Application Brief BYPETERALFKE
This FIFO DRAM controller consists of:
A bit serial FIFO buffer is a general-purpose tool to relieve
system bottlenecks, e.g., in LANs, in communications, and
in the interface between computers and peripherals.
Small FIFOs are usually designed as asynchronous shift
registers, but a larger FIFO with more than 256 locations
is better implemented as a controller plus a two-port RAM,
or as a controller plus a single port RAM, either SRAM or
DRAM.
• An input/output buffer with synchronizing logic
• A 20-bit write pointer (counter)
• A 20-bit read pointer (counter)
• A 20-bit fulVempty comparator
SRAMs are fast and easy to use, but at least four times
more expensive than DRAMs of equivalent size. Dynamic
RAMs offer low cost data storage, but require complex
timing and address multiplexing, which makes them unattractive in small designs. For FIFOs with more than 256K
bit capacity, a DRAM offers the lowest cost solution, if the
controller can be implemented in a compact and costeffective way. A Xilinx XC3020 Logic Cell Array can easily
perform all the control and addressing functions with many
gates left over for additional features.
• A 10-bit refresh counter
• A 5-to-1, 10-bit address multiplexer
• Control and arbitration logic
The write pointer defines the memory location where the
incoming data is being written, the read pointer defines the
memory location where the next data can be read. The
identity comparator Signals when the FIFO is getting full or
empty.
DIN
CLK
CLK
DOUT
I---------------D
READY
CONTROL
10
BUSY
MUX
3
DRAM
A
RAS
~-------_,~----~CAS
WE
1130 01
Figure 1. Megabit FIFO Controller In an XC3020
6-50
Megabit Serial FIFO in Two Chips
)D--i
= +-1
When write and read pointer become identical as a result
of a write operation, then the FIFO is full, and further write
operation must be prevented until data has been read out.
When the two pointers become identical as a result of a
read operation, then the FIFO is empty and further read
operation must be prevented until new data has been
written in. With a single-port RAM, read and write operations must be inherently sequential, and there is no danger
of confusing the full and empty state, a problem that has
plagued some two-port designs.
COMPARATOR
113002
Figure 2. Shift-Register-Counter and Free Row-Column
MUX
A straightforward design would use synchronous binary
counters for the two pointers, but it is far more efficient to
use linear shift register counters. Such counters require
far less logic and are faster since they avoid the carry
propagation problems of binary counters. LSR counters
have two peculiarities: they count in a pseudo-random
sequence and they usually skip one state, I.e., a 20-bit LSR
counter repeats after 220_1 clock pulses. In a FIFO
Controller, both these features are irrelevant, the address
sequence is arbitrary, provided both counter sequence
identically. The loss of one memory location is more than
compensated by the two bits (one incoming, one outgoing)
stored in the controller.
register counter is pseudo-random anyhow, this is no
problem. It's an elegant and efficient trick).
Both 20-bit pointers,plus their 20-bit identity comparator,
plus the Row/Column multiplexer thus fit into only 20
CLBs; refresh timer and refresh address counter and
multiplexer use another 15 CLBs and the data buffer plus
control and arbitration logic might take another 15 CLBs,
for a total of 50 CLBs, an easy fit in an XC3020.
This design can easily be modified for 256K DRAMs.
Other variations are: multiple parallel bits, e;g., byteparallel operation, or byte parallel storage with bit-serial
I/O. The latter case requires special attention when the
FIFO is emptied after a non-integer number of bytes had
been entered, requiring direct communication between
the input Serial-to-Parallel converter and the output PIS
converter.
This design fits two shift register counter bits in one
3000-series CLB, the identity comparator uses the combinatorial portion of the same CLB.
The RAS/CAS multiplexing of the 20-bit address is performed without any logic by tapping every other bit of the
shift register counter and using the 10 outputs before the
incrementing shift as Row address, after the incrementing
shift as Column address. (The Column address of any
position is thus identical with the Row address of the
following position, but since the binary sequence of a shift
,-- D
SHiFT-REGiSTER-COUNTER
This applications brief shows that the XC3020 can be
programmed to control one or a few DRAMs as a large
FIFO of up to a Megabyte, with data rates up to 16 Mbps
serially or 2 Megabytes per second byte-parallel.
or--
,-- D
DIN
or--
DiN
READ
ADDRESS
r--l
D
U
~D
or--
o~
D
F
~
DIN
WRITE
ADDRESS
COMPARE
L
f-----
0
COMPo
J
TWO
-D
o....J
ADDRESS
BITS
DIN
READ ADDRESS
WRiTE ADDRESS
113003
Figure 3. 2-Bit Slice of Two Counters and Comparator in Two ClBs
6-51
State Machines
Application Brief BYPETERALFKE
SIMPLE STATE MACHINE RUNS AT 30 MHz
State machine design is a methodology that defines the
contents of all flip-flops for any possible state of the design.
then defines all possible paths that can cause the design
to go from one state to another. In its simplest form this is
just a rigorous way of designing synchronous logic. like 4bit counters. For complex designs. the state machine approach gives the designer a tool to investigate all possible
operating conditions and avoid overlooked hang-up states
or undesired transitions. Xilinx LCAs with their abundance
of flip-flops lend themselves wellto state machine designs.
This simple state machine uses only eleven CLBs. It has
up to 16 states. and eight outputs. each decoding/encoding any combination of states. It performs a 2-way branch
from any state to anyone of two freely assigned states.
(possibly including the present state) determined by control input C. (Avoid the branch by making both destination
states equal).
.
SIMPLE, FAST STATE MACHINES
This design can also perform an 8-way branch from any
state so programmed to either one of two selected quadrants (0 .. 3. 4 ... 7. 8... 11 or 12 ... 15). Control inputs A.B then
determine the location within the quad~ant.
Using the 5-input function generator of the XC3000-70
family devices as a 32 bit ROM. a state machine with up to
32 states without any conditional jumps uses only 5 CLBs
and operates at up to 50 MHz.
Examples:
• From state@. if C=High. go to ® else go to ®
• From state rJ). if C=High. go to @else stay in rJ)
• From state ®. unconditionally go to ®
• From state ®. execute the truth-table below
The 5 registered CLB outputs drive the 5 function generator inputs of the 5 CLBs in parallel. This implements a fully
programmable sequencer similar to the synchronous
counter shown in the left column of page 6-23.
For a smaller number of states. some inputs can be used
as conditional jump inputs. Encoding these condition
codes may require an additional level of logic which
reduces the maximum clock rate to 30 MHz.
AS
C=Low
00
10
01
@
11
@
C=High
@
@
ACTIVE 4·WAY BRANCH
A
B
C-=~~~~~~~~
6CLBs
WITH
COMMON
INPUTS
4CLBs
WITH
COMMON
INPUTS
8
198601
30 MHz State Machine, 16 States, 2-Way/B-Way Branch, B Outputs
6-52
Complex State Machine
in One LCA
Application Brief BY PETERALFKE
Simple and fast state machines can easily be implemented
in a Xilinx LCA. as shown on the previous page. This page
shows how an external EPROM can be the source of the
next address in a complex state machine. This look-up
table can easily be hidden in the EPROM required to store
the LCA configuration data.
EPROM address bits. For reliable operation with asynchronous control inputs, they must be synchronized in an
input register.
This rudimentary state machine can thus· have 240
different states, and can jump from any state to anyone of
128 arbitrarily defined hext states, controlled by the 7 bit
condition code.
Assume that an XC3020 is configured in Master Parallel
Mode, where it reads its configuration data out of a 256K
(32K x 8) EPROM, starting at the top address location
7FFF (32K) through 77FF (about 30K). The remaining
94% of the EPROM can be used as next-state lookcup
table with a capacity of 240 states.
This basic design uses no CLBsin the LCA, just lOBs, but
it allows a number of states and. a multi-way branch
complexity far in excess of any normal need. For most
states, almost all of the 128 possible next states will be
programmed to be identical.
The state address isreiid out ofthe EPROM, then manipulated (decoded, encoded, etc.) in the XC3020 LCA. The
result is combined with incoming control information to
generate a new EPROM address. The EPROM can be
considered as having 240 locations, each 128 bytes wide.
Each byte is a potential next state value, only one of which
will be chosen bY the 7 bit condition code.
The user has the logic resources of the LCA available to
add features like:
•
•
•
•
In the simplest case, the EPROM output d~ta is just
latched in the LCA and is fed back as the most significant
part of the new EPROM address. Since the top 16 address
locations are used for configuration data,the state codes
are limited to 240 different values, .0 ... 239.
State decoding/encoding
Stack registers
Loop counters
More sophisticated branch logic, etc.
This design is straightforward, inexpensive, compact and
very flexible. Its speed is limited by the EPROM access
time which can be as low as 100ns. For higher speed- at
a higher cost- the EPROM can be shadowed by fast
SRAMS.
The seven control inputsform the seven least significant
27C256
EPROM
LCA
STATE
OUTPUTS
ADORES
~-';;;--"-----1
R
E .,,/'-,...- CONDITION
CODES
\.r---'---'!!'ic-'-----I G
198701
6-53
•
Incorporating PLD Equations into LCAs
Programmable Gate Arrays
and Self-Diagnosing
Hardware
£XILINX
Application Brief BY RICHARD B. RAVEL
SELF-DIAGNOSING HARDWARE
DIAGNOSTIC HARDWARE
Most designers would agree that it is desirable to incorporate self-diagnostics into their circuit boards, and they
would do it more often if the cost of additional components
and board space were acceptable. It is obviously best to
consider diagnostics at the beginning of a project so that
the board is designed with testability in mind. This not only
makes a board more manufacturable, but it makes it easier
to find failures in the end-user environment.
The circuitrywhich is most easily diagnosable is that which
is immediately accessible by the microprocessor. In many
cases, however, some of this circuitry cannot be tested
directly due to the specific design. Testing this logic, as
well as other unrelated circuitry, requires additional logic
on the board specifically for the purpose of diagnostics.
This is typically noldone because of board space and cost
considerations.
Programmable Gate Arrays are used in many different
applications, and have the unique capability of having their
specific functions defined by the systems in which they
reside. Xilinx Logic Cell Arrays (LCAs) can also be reprogrammed, in-system, as many times as necessary.
This ability to dynamically re-configure the logic of the LCA
makes board-level self-diagnostics a practical goal. An
LCA can perform diagnostic functions at power-up or in
test modes, and perform normal functions when the board
is determined to be operational. (See the application note
on "Configuring Xilinx Logic Cell Arrays" in the Programmable Gate Array User's Guide.) This approach to diagnostics based on reprogrammable gate arrays adds no
additional cost to the circuit board.
The logic which typically surrounds a microprocessor is
the I/O control, memory control, bus control, and interrupt
control logic. The peripheral control logic is the most
difficult to diagnose using the microprocessor. I/O control
functions are usually implemented with dedicated peripheral controller chips, since they are cost effective and
readily available. If they do not give the designer enough
flexibility to perform all of the required functions, logiC is
added to the board. Some peripheral controller chips allow
the designer to include diagnostic readback firmware.
This firmware, however, would usually not include access
to the supplemental circuitry which might be required.
Even when this readback capability is available, its scope
is limited.
This concept is really not new. Board-level self-diagnostics became popular with the advent of microprocessors.
A special diagnostic program written for the microprocessor and stored in its normal EPROM could be invoked at
power-up, by the press of a button, or by a special
command. This approach adds little cost to the system
because it requires only a small amount of EPROM storage. For example, when a PC is initially powered-up, all of
the system RAM is tested. Further initialization of the PC
will not take place unless this memory is 100% functional.
If there is a memory failure, it can be isolated to the specific
IC. The LCA allows an extension of this idea. The
microprocessor will still have some special programs for
diagnostics, but now the diagnostics can extend well
beyond the immediate reach of the microprocessor, without adding circuitry just for this purpose.
Peripheral control logic is usually diagnosable by writing
speCial programs for the microprocessor, and adding
special circuitry that the microprocessor can access
specifically for this purpose. Adding special logic for this
purpose is certainly not desirable and, with the use of Logic
Cell Arrays, not necessary.
The Logic Cell Arrays can perform many different peripheral control functions, and can also be the primary interface between a microprocessor and its peripherals. In
these microprocessor designs, as previously mentioned,
there would usually be circuitry on the board to which the
microprocessor mayor may not have immediate access.
The LCA, as the bus and I/O controller for example, would
easily be able to access this logic as an extension of the
microprocessor.
6-54
SELF-TEST TECHNIQUES
LOOPBACK
LCAs can be used to implement hardware diagnostics.
When the board is initially powered-up, the Logic Cell
Array can be programmed with a special diagnostic
configuration. The LCA can then be used in conjunction
with the microprocessor to test the peripheral circuitry.
This LCA configuration can include the ability to communicate status information about the peripherals and other
circuitry to the microprocessor that might otherwise require additional logic.
Many designs have special drivers and receivers on a
board to which there is no direct access. A special
loopback test connector is usually needed to test these
drivers and receivers. This connector must be installed
before and removed aftertesting. This usually means that
this test is only performed as a last resort, when all other
tests have failed to find a fault. The Logic Cell Array's userconfigurable interconnections allow the drivers and receivers to be tested without any additional test connectors or
manual intervention. To fully test this circuitry, it is only
necessary to connect traces on the printed circuit board
from the drivers and receivers to I/O pins on the Programmable Gate Array. This allows the LCA, with a diagnostic
configuration loaded, to drive the receivers and to read the
data from the drivers without the use of a loopback test
connector. Refer to Figure 1.
The remainderofthis paperwill focus on several examples
of how the Logic Cell Array can be used to perform boardlevel self-diagnostics.
L
~DRE~
v
J
"
\
I
\
I
1/0
A
J.lp
CONTROL
"
v
A
"-
)
CONTROL
PGA
~AT~
PERIPHERAL
L
1131 01
Figure 1. Diagram of LCA Used in LOOPBACK Testing
6-55
•
Incorporating PLD Equations into LCAs
TESTING I/O AND MEMORY ERROR DETECTION
CIRCUITRY
board is fully functional, it can re-program the LCAs for
their normal functions and the board can begin normal
operation.
A microprocessor can use the LCA to drive the peripherals
and additional supporting logic in non-standard ways. This
is often valuable in diagnosing circuitry. For example,
during normal operation of a serial communications channel, it is not possible to force an error in the transmission
of the data. This can easily be done, however, when an
LCA is used as an I/O controller. It can be programmed
with a special diagnostic configuration that can force parity
errors, overrun errors, and CRC/checksum errors in the
data stream which should be caught by the error detection
circuitry. This, along with special diagnostic firmware for
a microprocessor, allows full testing of serial (or parallel)
communications channels.
This same concept can be applied to testing standard
memory when the LCA is performing memory control
functions or has write access to the memory. With a
diagnostic configuration in the LCA, it can force data into
the memory with incorrect parity or check bits. The normal
circuitry and firmware for reading the memory should then
detect the errors, and the operation of the error correcting
logic can be verified.
INTERRUPT VECTORS
Interrupt circuitry is also difficult to test, as. there is not
always a straight-forward method of generating all of the
interrupt requests. With a Logic Cell Array as the interrupt
controller in the system, it can be configured with a special
test configuration that can sequence through all of the
different interrupts. It can even generate multiple interrupts in sequences that test interrupt prioritization logic.
Refer to Figure 2.
TIMEOUT INTERRUPTS
.J Some systems include timeout interrupts such as watch-
dog timers that do not occur in normal operation. This type
of timeout interrupt is difficult to generate during normal
operation. Again, using a Programmable Gate Array as an
interrupt controller allows the designer to easily force this
type of interrupt and verify that the detection circuitry and
error recovery routines are functioning correctly.
As soon as the microprocessor has determined that the
TIMER
ADDRESS
A
CONTROL
J.lP
DISK
INTERRUPT
CONTROL
LCA
"-
"-
A
DATA
MEMORY REFRESH
SERIAL PORT
CLOCK
\
LCA WILL PRESENT
DIAGNOSTIC INTERRUPT
VECTORS HERE
Figure 2. LCA Used as an Interrupt Controller
6-56
1131 02
E:.XILINX
PS/2 Micro Channel Interface
Application Brief BY ROB STRANSKY
18M's new general-purpose microcomputer, the Personal
System 2, is available in several models, from the low-end
Model 25 to the high-end Model 80. These third-generation PCs haveseveral new and innovative features, including 3 1/2 inch floppy disk drives, high-resolution VGA
graphics, and a 20 MHz 80386 processor as the main
engine for the Model 80. Among the most interesting
features is the Micro Channel interface,the bus
specification for the interface between the system and
adapter cards. The Micro Chan riel's streamlined characteristics and flexibiHty provide PS/2 designers and users
with many advantabes over previous PC architectures.
Utilities, an add"on card's addressing and other optional
configuration data are established ar1d stored in CMOS
battery-backed memorY on the main board.
Upon power-up, this information is loaded into Programmable Option Select (POS) registers residing on the
adapter cards:
Figure 1indicate.s one way in which a Programmable Gate
Array can be usedfor the POS register Section of a Micro
Channel adapter card.. The Micro Channel interface
includes logiC to decode the address, status, andcontrol
signals associated with the bus to identify the appropriate
POS register to be accessed. These signals determine if
the· card is being addressed, and wheth.er the. current
operation is a read or write.
.
One key aspect Of this architecture is the ability to
configure the system without the need for DIP switches on
the bus adapter cards .. Defined with System Configuration
co~RoL ------------~~--~~------~--_"
READ
. ENABLE
RD
STATUS
LINES
READI
WRITE
DECODE
WE
EN
LATCtlES
1-----'--+-"
CARD
SELECT
ADDRESS
INPUTS
111901
REGISTER
DECODES
GATED
WRITE
STROBES
1-__-f.N_____~--------l
Figure 1. Micro Channel Interface B.lock Dlagr..m
6-57
SYSTEM
BIDIRECTIONAL
DATA BUS
Incorporating PLD Equations Into LeAs
The Micro Channel specification reserves two P~S registers for the upper and lower bytes of the Adapter
Identification (10). Six other byte-wide P~S registers can
hold additional configuration information; some of the bits
within these are specifically dedicated to channel status
information. Some applications will require the use of only
portions of these six registers.
to the adapter with the highest priority.
As can be seen by the logic in Figure 2, this priority level
(ARB 100:3) is driven onto the bus via an open collector
driver. The logic then turns around and accepts the driven
bus as input. The cycle may repeat a few times before the
adapter with the highest priority level actually gains control
of the bus. For proper operation each haH of the cycle must
complete in 50 ns, a performance that can be achieved in
the 70 MHz Programmable Gate Array devices.
A second key ~spect of the Micro Channel architecture is
its ability to arbitrate the bus access of multiple adapters.
The Micro Channel specification clearly defines the logic
required for this arbitration. Each adapter in the system is
assigned a priority level. These levels vary from the
highest priority "-2" to the lowest priority "P'. This "-2, -1,
0,1, 2... A, B, ... F" scheme defines unique priority levels.
The higher levels are primarily used for memory refresh or
error recovery. The lower levels are reserved for the
System Board processor and spares. The middle levels
are used for DNA Ports 0-7, typically used for high speed
transfers. The priority level assigned to any adapter is
stored in one of its P~S register nibbles. The arbitration
logic must be very fast in order to grant control of the bus
Implementation of the P~S registers, arbitration, logic and
control sections typically requires only 1/3 to 2/3 of a single
XC2018 or XC3020; the remainder of the PGA is available
for implementing the unique functionality of the, specific
adapter card. Some Xilinx users have developed the
standard interface and stored it as a recallable macro
funcUon in the Xilinx development system. Applications
including hard disk controllers, communication controllers, and specialized memory controllers have been developed forthe PS/2 using Xilinx Programmable Gate Arrays.
COMPLETE LATCH
~
0.0.
ARB 10·3
~
0.0.
ARB BUS 2
1--/
ARB 10·2
r
bn
I~
0.0.
ARB BUS 1
r
ARB 10·1
~
,
../
ARB 10·0
ARB BUS 3
0.0.
ARB BUS 0
~
~
~
-'
ARB/·ENT
WON COMPETfTlON
FOROHANNEl
'.
Figure 2. Local Arbiter Logic
6-58
111902
E:XIUNX
High-Speed Bar Code
Reader Interface
Application Brief BY DAVE LAUTZENHEISER
Bar code readers have become familiar to the average
consumer due to their widespread use in point-of-sale
systems, such as those used in most grocery stores.
Additionally, many industrial applications are now using
bar codes to identify materials in various phases of manufacturing, inventory and distribution. Bar codes can be
automatically read and processed to provide for computerized control and optimization of virtually all phases of a
manufacturing process. In many industrial applications,
the performance requirements of the bar code system are
significantly higher than those of the point-of-sale system.
The block diagram in Figure 1 shows the functions performed in the PGA. For each type of sensor, the specific
controls and data signals have different functions and
timing relationships. In addition, the amount of data can
vary depending on the specific application. In different
scanner interfaces, the counter control logic, edge detect
circuitry and the operation of the black area and white area
counters can be modified to fit the needs of the particular
scanner. The bus control logic and the data loading into
the interface memory remain virtually unchanged, providing a consistent interface to the processor.
As an example, consider an industrial application where
material on a conveyor is being scanned to read bar code
data. If the conveyor is moving at 5 meters/second, and a
barcode label with 30 bars is 25 mm long, that label passes
a point scanner i n 5 milliseconds, or 166 microseconds per
bar. If the minimum bar width is 12% of the average time
period, it must be detected and its width determined in 20
microseconds. For a maximum bar width five times the
minimum, the time period is 100 microseconds. If a
multiple scan system is being used, the active period for a
bar is reduced proportional to the scan rate.
Implementation of the interface logic can be accomplished
with either an XC2000 or XC3000 family device. Because
there are processor and memory data and address bus
structures, the XC3000 family would provide a simpler
solution. Even with a master clock rate of 10 or 15 MHz,
the 16-bit counters forthe black and white areas are easily
implemented as up counters with reset capability. Edge
detection is performed with either simple gating, or synchronization to the master clock. Memory FIFO control
also involves counters, but these operate at a much slower
rate. A new word is written to memory only after a bar in
the target has been passed.
For this type of scanning system, some pre-processing of
the scan data is required to insure that a processor can
decode the label into code numbers and process them
accordingly. In addition, systems may be required to
operate with a variety of different bar code scanners or
sensors for different objects or labels, at different scan
rates. Traditionally, different logic and micro computer
coding dedicated to each application was designed.
Programmable Gate Arrays provide a method of implementing the scanner specific interface logic in a cost
effective, compact manner. At the same time, system
design flexibility is provided while meeting the performance constraints of the system. Designers of bar code
processing systems can design a single interface card that
utilizes the programmability of the PGA to define the logic
for a specific scanner in software as part of the system
initialization.
At the completion of a scan an End Of Label is signalled by
forcing a data entry in the RAM of FF hex. An interrupt to
the processor can be generated based onthe End Of Label
or End Of Scan condition. The microprocessor then
normalizes the absolute timing information for black and
white bars stored in the FIFO in order to extract the
encoded data. This allows for variations in scan speed,
scan angle, etc.
This type of interface represents only one of several
methods that can be used to pass the information to the
host processor. For other types of systems, different
techniques may be used. Regardless of the technique, the
flexibility of the PGA provides significant advantages over
a fixed logic solution.
6-59
•
Incorporating PLD Equations into LCAs
ON/OFF
COUNTER
CONTROL
LOGIC
BAR
MEMORY
FIFO
CONTROL
ADDRESS
DATA
PROCESSOR
ADDRESS
PROCESSOR
DATA
MEMORY
ARRAY
MASTER
CLOCK
GENERATOR
ARBITRATION
CONTROL
Figure 1. Bar Code Reader Interface
6-60
PROCESSOR ACCESS
CONTROL SIGNAL
1126 01
DRAM Controller
with Error Correction and
Detection
Application Note
AN INTRODUCTION TO MEMORY CONTROL AND
ERROR CORRECTION
The need to design memory controllers for systems that
have a large amount of memory is a common design
challenge that engineers must deal with today. Almost all
large memory systems· use dynamic random access
memory (DRAM) because of its density and low cost.
While designing large memory systems with static random
access memory (SRAM), would make the design task
easier, the drive to produce more cost effective products
forces the engineer to design with DRAMs, despite their
inherent drawbacks. The memory cell of a DRAM is a
capacitorthat holds a charge corresponding to the value of
the data bit. Since all capacitors leak charge, a DRAM cell
will gradually lose its charge, and its stored value, unless
it is recharged. This recharging, known as refreshing,
must typically be performed once every 2 to 4 ms depending on the DRAM. Refreshing is one of the DRAM
controller's two. primary functions. The other function is to
arbitrate between requests for memory read and write
accesses from the system's central processing unit and
requirements for memory refreshes.
In addition to its need for periodic refreshing, the. DRAM
exhibits another problem that SRAM and other memory
devices do not-greater susceptibility to soft errors. A soft
error is the loss of a data bit in a memory cell in which the
memory cell is not physically damaged. Rewriting the data
in the cell corrects the error. This type of error is different
from a hard errorwhich is caused by a memory cell that has
failed permanently. Soft errors in DRAMs are usually
caused by alpha particles (helium nUClei), which are normally present in the atmosphere, but which are more often
emitted by radioactive impurities in the IC packages of the
DRAMs themselves. If an alpha particle hits a memory
cell, it can corrupt the cell's charge, causing a data bit error.
Most people believe that the likelihood of such an error is
so low that it can be safely ignored .. While this may have
been true for the smaller memory systems of the past, it
may no longer be so. The size of some memory systems
today can make the likelihood of soft errors unacceptably
high. The probability of a soft error can be reduced by
device and packaging improvements and by reduction in
signal noise. Another method of dealing with soft errors is
6-61
BYTOMWAUGH
to incorporate error detection and correction into the
memory system. This solution decreases system performance and adds the cost of redundant memory, but prevents parity errors from causing system failures.
OPTIONS FOR DRAM CONTROLLER DESIGN
There are a number of options available to the engineer
designing a memory system that requires DRAM control.
(The following options apply to the design of error detection and correction circuits as well.) The simplest option is
a standard off-the-shelf LSI memory controller. The
manufacturers of these devices. provide an integrated
solution to DRAM control by combining CPU interface
logic with the necessary memory access/memory refresh
arbitration on a single chip. However, each memory
system has unique timing and protocolrequirements, and
it is extremely difficult for these standard parts to accommodate the requirements of every system. This realization
has driven many DRAM controller manufacturers to incorporate some degree of programmability into their parts to
make them more flexible. Unfortunately, this has made the
parts more complex, hungrier for power, and more expensive. Even so, they simply cannot meet every system's
requirements without employing external "glue logic."
The need to match the DRAM controller to the specific
requirements of the system has forced many engineers to
consider two optionsfbr creating their own controllers:
SSI!MSI packages or custom gate arrays. The use of SSI!
MSI is low risk, but wastes space and power; while the use
of the custom gate array provides a highly integrated
solution, but at considerable risk and expense. Nonrecurring engineering costs (NRE), testing and simulation
costs, inventory risk, and a long design cycle make the
custom gate array option unattractive for most designs.
Recent architectural advances in high density user programmable logic have created a third option. Xilinx's 3000
familyof programmable gate arrays brings unprecedented
density to programmable logic, with devices containing as
many 9000 usable gates. The architecture of the 3000
family devices make them particularly well-suited to
memory controller applications.
•
Incorporating PLD Equations into LeAs
WHY IMPLEMENT A DRAM CONTROLLER WITH A
PROGRAMMABLE GATE ARRAY?
(ECC) with an LCA. The example is an 8 MHz8086-based
system that directly addresses 1 MB of memory comprised
of forty-four 256 KB DRAM chips: thirty-two for data and
twelve for the correction bits. A single LCA can serve as
both the DRAM controller and the ECC, which performs
single bit error correction and double bit error detection.
There are several features of the 3000 family architecture
that make this design possible. These include five input
configurable logic blocks (CLBs) with two storage elements, internal buses, and flexible input/output blocks
(lOB).
There are several reasons why one would want to design
a DRAM controller with a Xilinx Logic Cell™ Array. First,
the true programmability of the LCA gives the designer the
freedom to design the DRAM controller to the exact
specifications of the memory system. There is no need for
the external "glue logic" often necessary with standard
solutions, because any necessary design tweaking is
implemented internally. The LCA solution has the advantage of the SSI/MSI or custom gate array solution in that it
can be configured to meet unique system requirements.
There is no loss in integration as with the SSI/MSI solution,
and the cost and risks of the custom gate array solution can
be avoided. Second, the density of the 3000 family of
LCAs makes it possible to implement DRAM control and
error detection/correction in a single LCA. This is traditionally a two chip solution using standard parts: a DRAM
controller and a separate error correction and detection
unit. It can of course be implemented in a single custom
gate array, but again with the earlier caveats. Finally, the
CMOS LCA consumes less power than traditional standard "programmable" controllers which are typically implemented in NMOS or bipolar processes.
DESIGN OVERVIEW
The DRAM Controller/ECC uses a 16 MHz clock synchronized with the processor's clock, and sits between the
8086 microprocessor with its 8288 bus controller and the
system memory (Figure 1). The 8288 decodes the processorstatus lines (S2, S1, SO) and tells the DRAM Controller whether it is to perform a read or write access to the
memory. (It is also possible to incorporate the bus controller logic into the larger LCAs). The DRAM Controller then
performs the appropriate access issuing Row Address
Strobe (RAS), Column Address Strobe (CAS), and Write,
if necessary. The Error Checker and Corrector generates
check bits on each write, and checks for and corrects
errors on each read. The controller also signals the 8086
if the memory access requires a wait state or if a noncorrectable error is detected.
DESIGN EXAMPLE
The following design example shows the implementation
of a DRAM controller and an error checker/corrector
8284
CLOCK
GENERATOR
READY
iCLK
------ READY
------ RESET
SO
f--
Sl
f---t>
f---t>
S2
8288
BUS
CONTROLLER
MRDC
AMWC
CEN
8086
DEN
XILINX LeA
W
CASH.L
=:
-
RAS 0.1
READ
WRITE
HOLD
OUT 0-8
BANKO
(512K BYTES)
t;
~
r~
6+16=22
256K DRAMS
AO-8
CHECK
BITS
BANK SELECT
A19
Al6-18
CBO·5 ~
(CHECK BITS)
ADO-15
v-- I"'"
ADO-15
MULTI-BIT
ERROR
WAIT
74LS245
DATA
BITS
~
BITS
Al6-18
ENABLE
DATA BUS
r--
BANK 1
(512K BYTES)
DATA
BITS
T08086NMI
r--
16
112709
Figure 1. System Overview
System overview of DRAM Controller with error correction and detection.
6-62
~XIUNX
address and data on a multiplexed bus to be latched from
the same I/O pin. Figure 4 is a bit sliced view of an lOB
used to latch the multiplexed Address/Data bus. In this
design, the address is latched into the lOB input flip-flop
with the 8086's ALE. The data from the 8086 can enterthe
same input pin and go directly to the ECC circuit via the lOB
direct input-there is no need for external latches.
SYSTEM TIMING
Rgures 3a-3c show the timing involved in some of the
different memory cycles. The Word Write (Figure 3a)
requires no wait states as shown. The check bits from the
ECC are written to memory along with the data. The Read
cycle (Figures 3b & 3c) requires a minimum of one wait
state. The insertion of a wait state is unavoidable because
of the time it takes the 120 ns DRAMs to output the data.
If the ECC detects no errors in the data, the WAIT signal
is released and the read operation is completed. If an error
is detected, the insertion oftwo more wait states is required
to allow time to correct the error. The insertion of the two
additional wait states effects system performance, but this
is the trade-off for having error correction, which avoids the
fatal system errors that occur with parity-checking-only
solutions.
Another feature of the lOBs is the output flip-flops with
three-state buffer enables. This feature permits bit error
correction using only one I/O pin. Figure 5 shows a bit
sliced view of how the ECC is accomplished. A memory
read cycle provides the best example for showing the
capabilities of the lOB structure. During a read, the lOB
output is three-stated, permitting the DRAM data on the
Data Bus to enter the ECC via the lOB direct input. If the
ECC detects a data bit error, it corrects the error and
latches the corrected data word into the output flip-flops of
the lOBs. The Data Bus is then three-stated by turning off
the DRAM outputs. The corrected word, latched in the
outputs of the flip-flops, is then released onto the Data Bus
by enabling the three-state buffer. This allows the corrected data to be read by the 8086 at the same time it is
being written back to the DRAM.
DESIGN FOCUS
The 3000 family LCA architecture has a number of features that are essential to the DRAM controller design. The
first such feature is the dual data input paths in the lOBs,
one registered and one direct. This structure permits the
r--------------------
r - - - - - - t - - O U T P U T ENABLE
I
rI
I
-4- -iQ---~ - - - - - - -- ---I
I
CORRECTED DATA OUT
~-+--FROMERROR
]
CHECKER/CORRECTOR
I
I
~-1
I
L. ___ .J:
I
q..---t-- OUTPUT CLOCK
DIRECT INPUT
REGISTERED INPUT
DATA TO ERROR
CHECKER'CORRECTOR
ADDRESS TO INTERNAL
.-------+---.- g~~~~~~~~~ECTOR
BUS VIA THREE STATE
r---'
QL __ _
BUFFER
IL _______________________ _
I
I
I
I
I
I ___ 40--L
J
I
I
10
I
ALE
112706
112707
Figure 4. Address and Data Latching
Latching Data off a Multiplexed Address and Data Bus.
The Input/Output block configuration shown above illustrates how the direct and registered inputs in the lOBs
can be used to latch a multiplexed address/data bus
into the LCA. The address is latched into the lOB flipflop; the data flows directly into the ECC logic.
Figure 5. Data In and out through ECC
Data Flow through the ECC The data from the bus goes
into the LCA, where it is corrected in the ECC. The
corrected data is then put back onto the bus via the lOB
output flip-flop.
6-63
•
Incorporating PLD Equations into LeAs
T1
T2
T4
T3
8086
CLOCK
ALE
~~__________________________________________
CONTROLLER
CLOCK
RAS
CAS
W
DATA FROM
BOB6
--------~(~--------------------------------~>~----
112703
Figure 3a. Word Write Timing
T2
TW
T3
TW
TW
T4
8066
CLOCK ' - -____-'
CONTROLLER
CLOCK
MS
----11
~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
1 - . - -_ _
'------'I
CAS
~
w
WAIT
~L._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - '
ERROR DETECTED
DATA BUS
CORRECTED DATA LATCHED
CORRECTED DATA RELEASED
I/O 3·STATED
-----------<
1127 04
Figure 3b. Word Read Timing with Errors Detected
g
I
c~~~ ~__~r--l~
B
I
ffl
I
R
I
____~r--l~____~r--l~____~r--l~_____
RAS~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
CAS
WAIT
DATAb~2~
1'--________________--'
______________
~(~___________________________'>~------1127 05
Figure 3c Word Read Timing with No Errors Detected
6·64
E:XILINX
Figure 2 is a block level diagram of the DRAM Controller
and ECC that reside in the LCA. A functional description
of each block follows:
The refresh timer is driven by the 16 MHz clock to provide
a signal that tells the DRAM controller that the memory
needs refreshing. Each of the 256 rows of memory in this
system must be refreshed every 4 ms. The controller
attempts to refresh eight rows every 125 I1sec, so that all
256 rows are refreshed in 4 ms. The refreshing technique
employed in this design is a unique combination of burst
and hidden refreshing to show the flexibility of the
LCA-based solution. There is no need to force a system to
conform to the constraints of an off-the-shelf part. The
Hidden Refresh is performed when the 8086is doing a read
from or write to somewhere other than memory, like an 1/0
port. This involves giving the DRAM a refresh address from
the refresh address counter via the address selector and a
RAS pulse low from the timing generator. The Burst
Refresh is performed only if it has not received its eight
required refreshes during the 125 I1sec refresh period.
When a Burst Refresh is required, the controller will isolate
the memory from the 8086, insert wait states, and provide
the number of refreshes it needs in order to complete the
eight refreshes required during the refresh period.
The timing generator, a state machine triggered by Address Latch Enable (ALE) at the beginning of the processor cycle, produces all the timing required to perform the
memory accesses and refreshes. The signals generated
by this block include the row address and column address
strobes (RAS and CAS), the WRITE Signal, the WAIT state
signal for the processor, the HOLD signal that isolates the
processor from the memory, the clock for the refresh
address counter, and the select control for the address
select.
The refresh address counter is an eight bit counter that
provides the eight bit addresses necessary to refresh the
DRAMs.
The address selector selects which address is sent to the
DRAM. During a read or write cycle the timing generator
select control signal tells the address selectorto select the
DRAM row address, strobe it with the RAS, and then select
the column address and strobe it with the CAS. During a
refresh, the address selector selects the address from the
refresh address selector and strobes it into the DRAM with
RAS.
During a write cycle, the error checker/corrector (EGG)
generates six check bits using a modified Hamming code
for each sixteen bit data word and writes them to memory
along with the data. Use of a modified Hamming code
permits single bit data correction and double bit error
detection. During a read cycle, the ECC compares the
check bits read back from memory with new check bits
generated from the data read back. If the comparison
yields a correctable error, the ECCwill correct it. Ifthe error
is not correctable, it will flag the NMI on the processor.
16
DATA BUS
TO DRAM DATA
REFRESH TIMER
DO-I5
TIMING
GENERATOR
CBO·5
BURST REQUEST
HIDDEN REQUES,T1--~
RESET
MULTI· BIT ERROR
BANK SELECT
TO DRAM
CASH.L
MRDC
WAIT
HOLD
AMWC
MUX CONTROL
16MHz
TOB086NMI
W
RASO.l
ALE
TO DRAM DATA
ERROR CHECKER!
CORRECTOR
ECC
CONTROLS
TOB086
TO BUS CONTROLLER
III
b==:rAADD5iDRRiEEiS~siiM~Uu:xK]
INCREMENT
AI·9
OUT 0·8
TO DRAM ADDRESS
AIO·IS
REFRESH
ADDRESS
COUNTER
REFRESH
ADDRESS 0·7
INCREMENT
COUNTER
112702
Figure 2. LCA Block Diagram
Block diagram of the DRAM controller functions implemented in the LCA.
6-65
Incorporating PLD Equations into LeAs
CONCLUSION
Perhaps the most important feature of the LCA architecture for implementing a DRAM Controller is its intemal
three-state bus capability. The three-state buffer enables
onto the horizontallonglines allow the designer to implement an internal bus in the LCA. This feature permits the
implementation of the Address Selector without using any
CLBs. Figure 6 shows a bit slice view. The row, column,
and refresh addresses all have access onto the internal
bus, and to the outputs that lead to the DRAMs. By
controlling the three-state enables, only one address is
allowed onto the bus at a time. This feature is essential to
this design, and has many other applications including
performing wired-AND functions and address decoding.
Although the bottom-up design of a DRAM controller is a
complex task, it is necessary in cases in which off-the-shelf
controllers do not meet the requirements of the system.
SSIIMSI and custom gate array solutions involve tradeoffs and compromises. Designing a DRAM controller and
ECC with an LCA is a straightforward application and a
good fit for the 3000 family architecture. The Programmable Gate Array offers the flexibility. necessary to match
the many different memory systems, the integration desirable for board level designs today, and the cost effectiveness required to make a competitive product.
INTERNAL BUS
----------~------------------~------------------T----!gg::S~LlNE
ROW
ADDRESS
COLUMN
ADDRESS
REFRESH
ADDRESS
ROW
ENABLE
COLUMN
ENABLE
REFRESH
ENABLE
1127 OS
Figure 6. Address Multiplexing Using Three-State Enables onto Internal Buses
6-66
Logic Analyzer/In-Circuit
Emulator
Application Brief
Logic analyzers and in-circuit emulators are similar types
of electronic test equipment. Each involves the monitoring
of certain digital signals within the system being tested. For
general-purpose logic analyzers, these signals can be any
nodes on the board being tested that the user selects.
Anothercategory of logic analyzers, sometimes called bus
analyzers, are designed to plug into a specific microcomputer bus (such as a PC-bus or Multibus) and monitor and
control the activity on that bus. In-circuit emulation of a
specific component (usually a microprocessor) involves
monitoring and controlling the signals input and output by
the device being emulated.
BYBRADFAWCETI
ger or breakpoint occurs. Triggers and breakpoints might
be defined as a single event in the target system, or some
ordered sequence of multiple events. Usually, trigger and
breakpoint conditions are simply stored in registers and
then continuously compared to the target system signals
that are being monitored. Typically, logic analyzers and
in-circuit emulators use many SSI/MSI latches and comparators to perform these functions.
The large numberof logic functions and registers available
in the Xilinx Programmable Gate Arrays make them ideal
for implementing these trigger and breakpoint functions
within a single device. Furthermore, the interface logic for
controlling the trace memory can also be integrated into the
PGA. This application can take advantage olthe re-configurable nature of the PGA architecture. (Effectively, the
Programmable Gate Array can perform different functions
within the same system at different times by loading different configuration programs. This can lead to fewer packages on the printed circuit board and increased reliability.)
One configuration of the PGA could be used for acquisition
mode operation, capturing data, searching for the triggers
and breakpoints, and filling the trace memory. When the
breakpoint is reached, a different configuration could be
loaded into the same PGA forthe analysis mode; the PGA
now controls the reading of the captured data from the
trace memory. Additional functions, such as control of the
user interface, also could be incorporated into the PGA.
A record of the activity on the nodes being tested by the
analyzer is stored in a memory buffer called '1race memory"; this activity is called "acquisition mode." In some
cases, the analyzer might also be contrOlling some of the
target system's functions, such as single stepping a clock
or interrupting a processor. After tracing is completed, the
trace memory is then read and displayed by control logic in
the analyzer; this is the "analysis mode." Trigger and
breakpoint logic is integraltothisoperation;the userspecifies when the tracing of signals in the target system should
begin (triggering) and end (the breakpoint). Hence, a descriptionolthe combination of Signals that make upthetriggers and breakpoints must be stored in the analyzerbefore
beginning operation, and the state of the target system
must be continuously monitored to determine when a trig-
ADDRESS
DATA
DATA
TRACE
SYSTEM
INPUT
UNDER
CAPTURE
TEST
LOGIC
MEMORY
MEMORY
TRIGGER
AND
ADDRESS
GENERATION
BREAKPOINT
LOGIC
CONTROL
II
CONTROL
CONTROL
CONTAOI.
CONTROLLER
PGA
ACQUISITION MODE
ADDRESS
DATA
DATA
MEMORY
ADDRESS
USER
USER
INTERFACE
INTERFACE
TRACE
MEMORY
CONTAOL
GENERATION
CONTROL
+
CONTROL
CONTROL
CONTROL
PGA
ANALYSIS MODE
1128 01
Figure 1. Logic Analyzerlln-Circuit Emulator
6-67
CONTROlLER
E:XILIXX
The Programmable Gate Array Company
l:XllJXX
SECTION 7
Article Reprints
1
Programmable Gate Arrays
2
Product Specifications
3
Quality, Testing, Packaging
4
Technical Support
5
Development Systems
6
Applications
7 Article Reprints
8
Index
Article Reprints
Building Tomorrow's Disk Controller Today ........................................ 7-1
The Acid Test ...................................................................................... 7-5
Programmable Logic Betters the Odds ............................................... 7-8
Using LCAs in a Satellite Earth Station ............................................... 7-12
Faster Turnaround for a T1 Interface .................................................. 7-17
Two, Two, Two Chips in One ..................................................; ........... 7-19
LCA Stars in Video .............................................................................. 7-22
Taking Advantage of Reconfigurable Logic ........................................ 7-24
1962
Electronic
Products
Building Tomorrow's Disk
Controller Today
~o,;_,","""~,,rp"."" ,,,h,,,',,.
Jim Reynolds, President, Dave Randall, Chief Engineer, Andromeda Systems, Canoga Park, CA
Reprogrammable logic with a flexible architecture
enables a controller to keep up with today's highcapacity, high-speed disk drives
could be surface mounted onto a 35-in. 2 dual-width board.
The only answer appeared to be VLSI custom or semicustom devices like gate arrays. But gate array definition
requires absolute design accuracy, and so a prototype
must be constructed long before custom-tooled ICs can be
specified and manufactured. Paradoxically, the prototype
itself required highly integrated logic.
Computer manufacturers historically have relied on advances in CPU and semiconductor memory tech nology for
increasing system throughput. At the same time, they
accepted as inevitable the hardware-bound I/O bottleneck. This position is becoming untenable with recent
advances in magnetic disk technologies, which have led to
a proliferation of high-capacity, high-speed drives.
To break thatfrustrating circle, il was necessary to convert
directly from schematic capture to a silicon breadboard of
multiple electrically programmable logic devices (EPLDs).
Because many logic functions would be added to the
prototype after the initial test, EPROM-based PALs were
considered, like the EP1200 from Altera, which licenses
the technology from Monolithic Memories.
Full performance from these drives needs sophisticated
controllers like Andromeda Systems' new Storage Module
Device Controller (SMDC). With a 1-Mbyte data cache
and dynamic read-ahead algorithms, the SMDC dramatically reduces average disk access time and significantly
improves overall system performance (see box, "The
Storage Module Device Controller"). The design and
performance benefitted greatly from using Xilinx's Logic
Cell Arrays (LCAs).
The EP1200 could provide the minimum functionality on
the silicon breadboard, but not the level of device integration for the production circuit board. To implement the
various state machines and other logic of the design, each
target gate array would need three EP1200s. The resulting schematic capture and simulation would then be used
to fabricate the gate arrays for Ihe final product.
Very early in the design, it was clear that its high-performance caching scheme needed more SSIIMSI logic than
CACHE MEMORY
1-MBYTE DRAM
...
f
I
O-BUS
INTERFACE
CACHE
ADDRESS
MAPPER
~
LCA.1
O-BUS AND DMA
CONTROLLER
!
I
>----0
DISK
CONTROLLER
...
~
LCA3
LCA2
CACHE
CONTROLLER
SM&~~~:g~I~~~AL
r
i
i
J
65C802 MICROPROCESSOR
STATIC
RAM
I
PERIPHERAL
EXPANSION
PORT
STORAGE
MODULE
DEVICE
INTERFACE
..
CONTROLLER
USER
SERVICE
PORT
EEPROM
114801
Figure 1. On Andromeda Systems' new Storage Module Device Controller, Xilinx Logic Cell Arrays handle the Q-bus interface
and direct memory access (DMA) Control, RAM/data-cache control, and SMD and peripheral expansion port control.
7-1
II
Article Reprints
Fortunately, this circuitous design path was bypassed by
using Xilinx's LCA (see box, "Xilinx's programmable gate
array"). There are two basic differences between LCAs
and other EPLDs. First, the LCA has the flexible architecture of a gate array. Second, LCAs employ static memory
to hold the logic configuration data.
The LCAs brought several significant advantages to the
controller design. Since the Xilinx 2064 LCA has 64
configurable logic blocks and the EP1200 only 20, a single
LCA could replace the three target gate arrays, elimination
the fabrication delays and costs of custom tooling.
Figure 2. The user service port can create color bar graphs
Furthermore, the position of the LCAs on the board could
be determined before their internal logic configuration was
designed. Other than dedication input and output pins,
only a general idea of the function of each LCA was
needed. The board layout and the internal LCA logic
design could proceed in parallel, greatly reducing development time. Most design changes could be implemented
merely by reprogramming the LCAs. Thus, u!>e of the
LCAs allowed the design to go directly from schematic
capture to a production board, skipping the wire-wrapped
prototype.
that dynamically show various attributes of the data cache,
such as read times, forward block reads, and 110
completion rates.
Aside from the LSI circuitry, the only other logic on the
SMDC board are TIL bus transceivers, SMD interface
drivers, and a few PALs.
The RAM of the data cache is in ZIPs. Most of the interface
logic was surface mounted to the board. Despite the
board's small size, these VLSI devices permit several
advanced features.
The first LCA on the SMDC is the Q-bus interface and
direct memory access (DMA) controller (see Fig. 1). All but
5 of the 64 internal logic blocks were used. The LCA holds
the DMA addressing logic, the bus registers, and the
interrupt logic.
The SMDC's user service port connects directly to terminals or modems. No special test programs for specific
system environments are needed to communicate with the
controller. Users can define drives, assign logical units,
format drives, and do other more esoteric functions.
RAM/data-cache control is the job of the second LCA. It
controls the cache and has the interface between the disk
controller IC and the DMA logic. It signals cache-write
enables, multiplexes memory addresses, and enable
DMA reads and writes.
This port can monitor the operation of the controller while
the drive is in operation. The user can display color bar
graphs that dynamically show various attributes of the data
cache, such as read times, forward block reads, and 1/0
completion rates. Caching parameters can·be adjusted,
letting the user tune the system for optimum performance.
The third LCA controls the SMD port and peripheral
expansion port. The expansion port is just a group of
programmable I/O connections. Since the LCA is programmable, the control logic forthe expansion port can be
reconfigured for any desired 1/0 interface. Thus, this port
provides for future expansions (like adding a tape drive,
optical disk, or extra cache memory) at a fraction of the
cost of a separate controller. Unused logic in this LCA will
permit on-board functions to be added in future microcode
revisions to the controller.
Firmware can alter the configuration data for the LCAs,
modifying the circuit schematic and not the board. Since
the firmware is in EEPROMs, the service port can accept
microcode upgrades in the field via modem. PROM set
replacement and on-shelf obsolescence are avoided.
7-2
E:XILINX
THE STORAGE MODULE DEVICE CONTROLLER
Andromeda divides the cache into 1,024 granules. The
information kept for each 1-Kbyte granule depends on
select criteria, which include:
Designed for LSI-11 and MicroNAX II systems,
Andromeda Systems' Storage Module Device Controller
(SMDC) for Winchester drives supports two SMD or
SMDE drives at data rates up to 25 Mbits/s. Another
Andromeda controller, the ESDC, works with the Enhanced Small Device Interface, the ESDI, for Winchesters or floppy-disk drives. Both controllers use the standard DU device driver and work with such operation systems as RT-11, TSX+, RSX, RSX-11M, MicroRSX,
RSTS, MicroRSTS, Ultrix, DSM, Unix, and MicroVMS.
The time data is first accessed
The number of times data is read
The time of the most recent read
The size of the read.
This information is then entered into an equation that
approximates how probable it is that the granule will be
requested again soon. Those granules with low probabilities are designated to be overwritten by the next diskread operation. During cache accesses, a memory
mapper translates logical memory addresses into the
physical addresses of the appropriate granule in much
the same waythatthe Micro-Vax II memory management
unit would.
The SMDC achieves more performance and flexibility
than did previous generations of disk controllers. It includes data caching, high data-transfer rates, a peripheral expansion port, field-Ioadable microcode, and a user
service port. State-of-the-art VLSI components and
packaging techniques fit the entire controller within the
35 sq in. of a dual-width a-bus board (see figure).
PREDICTIVE CACHING
Using Digital Equipment's Mass Storage Control Protocol (MSCP), the SMDC can partition two drives into as
many as 16 logical units with up to 32 Gbytes each. Onboard intelligence comes from a 65C802 microprocessor, and all the processor's code resides in just two
EEPROMs. The majority of the remaining logic is implemented with Xilinx programmable Logic Cell Arrays
(LCAs). Data integrity is ensured by 48-bit error detection and correction logic. An expansion port can be connected to accessory modules, allowing control of devices
like tape drives, optical disks, or extra cache memory.
In a novel departure from· most caching schemes, the
SMDC caching mechanism not only looks at the past, but
tries to gaze into the future as well. Asthe system requests the data that has been pre-fetched into the cache,
the controller retrieves not only the requested data, but
also preemptively reads extra sequentiafblocks when
specific probability conditions are met. As a result, the
on-board cache's typical hit rate is over 80%. In other
words, the data being sought by the applicatiOn wil.l be
ready and waiting in the cache over 80% Onlle time.
Approximately 90% of the disk access time is due more
to average seek times and rotational latency than to the
actual data tran$fer rate. However, when a cache hit
occurs, the access time depends only on the speed ofthe
DMA channel responsible for sending the data to the
a-bus.
The performance of the SM DC is greatly enhanced with
a 1-Mbyte data cache and unique caching algorithms.
That DMA channel operates as fast as a-bus specifications allow.,....to be specific, at a rate of upt04 Mbytes/s.
Consequently, with the SMDC cache, see.k time androtationallatency are reduced to zero over80% ofthe time.
This reduces the average time for a four-blockread from
27 ms to less than 6 ms.
In the majority of computer systems, mass-storage access time is undoubtedly the largest component of
throughput. In this situation, use of the SMOC
enormously improves total system performance.
$$$$$
Andromeda Systems' Storage Module Device Controller
is available now for $2, 195. (The company's ESDI controller is available for $1,995.) For more information,call
Don Talmadge at 818-709-7600,or circle 336 for the
SMOC and 337 forthe ESDC.
7-3
ArUcla Reprints
XILlNX'S PROGRAMMABLE GATE ARRAY
The Xilinx programmable gate array, known as a Logic
Cell Array (LCA) , is a high-density CMOS IC that combines
user programmability with the flexibility of a gate array
architecture and the economy and testability of standard
products. Elements of the array include three categories
of configurable elements: 1/0 blocks, configurable logic
blocks, and programmable interconnections (see figure).
0
g
Qg
CONFIGURABLE
LOGIC BLOCK~
-[}
-[}
-[}
-[}
-[}
-[}
-[}
I/O blocks provide an interface between the external
package pin and the internal logic. Each block includes a
programmable input path and output buffer. The array of
configurable logic blocks contains the functional elements
from which the user's logic is constructed. Each array
includes a combinatorial section, storage elements, and
internal routing and control logic. Programmable interconnection resources connect the inputs and outputs of the
I/O .blocks and configurable logic blocks into the desire
networks.
An LCA is configured by programming static memory cells
that determine the logic functions and interconnections.
On-chip logic provides for automatic loading of the configuration program at power-up or upon command. A
personal computer-based development software package
generates the configuration program. Other tools include
a simulator, in-circuit, and schematic capture package.
o
0 0 0
0 oro 0
0 010 0
0 0 0 0
4---INTERCONNECT AREA-----+-
1148 02
Reprinted with permission of Electronic Products.
7-4
FJectronic Engineering
TlMF~
The Acid Test
By Steven K. Knapp, Field Applications Engineer, Xilinx Inc.
Using an EPLD vendor's application, the same circuit
was built with a Logic Cell Array. The comparison
provides real insight to the differences between these
two technologies.
The configurable logic blocks contain combinatorial logic
plus storage elements. The combinatorial logic within
each block implements any possible single function of four
variables, or any two functions of up to three variables.
The storage element is configurable as an edge-triggered
flip-flop, or as a level-sensitive latch, both with asynchronous SET and RESET inputs. The programmable interconnect allows each of th e storage elements to be clocked
either synchronously or asynchronously.
As with a processor, a PLD's architecture determines its
functional logic density and its performance.
Among processors, general-purpose microprocessors
and application-oriented devices like digital signal processors share many similar internal logic structures and
functions. DSPs have a more rigid architecture, designed
for particular applications, while general-purpose microprocessors address a much wider set of applications. The
same situation exists in the world of PLDs.
Three levels of programmable interconnect resources
provide the interconnection between blocks:
• Direct interconnect allows fast connections between adjacent blocks.
Until recently, the sum-of-products (SOP, also known as
AND-OR) structure was the only one available for PLDs.
Its simple, fixed architecture fits a variety of low-density,
high-speed applications. These include fast, wide logic
functions found in decoders, multiplexers and counters.
• General-purpose Signals travel through an array of
switching matrices that yield an efficient means of connecting scattered random logic.
• Long metal lines that traverse the chip distribute clock or
other signals with high fan-out or requirements for minimum skew.
Some recently introduced high-density PLDs are based on
extensions of the conventional AND-OR architecture.
Examples include the MMI 64R32 MegaPAL and the
Altera EP1800 Erasable Programmable Logic Device
(EPLD).
The best way to illustrate the difference between the Logic
Cell Array and the more conventional AND-OR architectures is through a design example.
An X-V position controller design was originally developed
by Altera as an application example for its EP1800. The
design is fairly simple, and illustrates the capability of
programmable logic to address the problems faced by
logic designers. The example can be used to demonstrate
the capabilities of both the Altera EPLD, and the Xilinx
Logic Cell Array.
Like a DSP processor, the sum-ol-products architecture of
these devices efficiently meets certain needs. However,
this architecture is not suitable for higher-density, registerintensive random logic structures commonly found in logic
designs.
LOGIC CELL ARRA V
X-V position controllers are employed in a variety of design
applications to control motors for printers, plotters, robotics, and numerical controllers. The controller compares
the desired location loaded from an external processor
with the present motor position stored within the PLD.
Based on the results of the comparison, the controller
drives two four-phase stepper motors (an X- and a
V-position motor) to its desired position.
The Programmable Gate Array differs vastly from the
conventional sum-of-products architecture. Its flexible,
register- and I/O-rich, array-style architecture addresses a
wider set of common logic design problems.
Its Logic Cell Array architecture consists of three basic
programmable elements: inpuVoutput blocks, configurable logic blocks and programmable interconnects.
In this design, X- and V-position data is loaded into the
device from an external microprocessor. The 1,800-gate
EPLD has no input storage elements, so the data must be
held valid by some external device until both motors reach
Each 1/0 block can be individually configured as a direct or
registered input, a direct or three-state output or as a
bidirectional 1/0.
7-5
II
Article Reprints
final location. This also signals the processor that further
motor action may be taken. A master RESET signal resets
the present position to zero.
their final position. Since the Logic Cell Array has inputflipflops which hold the X- and the V-position data,.it offers a
.
simpler interface to the processor.
The desired position data is compared against the present
position data. The result of the comparison drives the
7-bit upldown counters which, in turn, drive the statemachine motor control. The stepper motors used in the
application have 7.5 degree fullstep increments with optional3.75 degree half-step increments available. A 7-bit
binary up-down counter is required to keep track of the 96
motor steps required to rotate each motor a full 360
degrees.
.
In the EPLDdesigns, seven macrocells are used toimplement the binary upldown counter for each half of the
position controller. Because of the low-frequency clock
(500 kHz), this same counter requires only seven Logic
Cell Array logic blocks. If this were a high-speed counter,
a few additional blocks would perform some level of carrylook-ahead.
RESOURCE REQUIREMENTS
. Based on the requirements of the deSign, the X-V position
controller example requires 47 of the 48 macrocells in the
1,800-gate EPLD and all of its 64 1/0 pins. A number of the
1/0 pins are used simply because a register is hardconnected to the pin. The two 7-bit counter, for example,
use 141/0 pins because they cannot be buried. The X-V
controller design uses 98 percent of the macrocells and
100 percent of its 1/0 pins.
The same design (plus the input data registers) fits in 49
configurable logic blocks and 27 inpuUoutput blocks in a
Logic Cell Array (the MASTER RESET input uses the
Logic Cell Array's dedicated master reset pin). Fewer 1/0
pins are requ ired, since the 7-bit upldown counters and the
state-machines were buried in the Logic Cell Array design.
If the desired position is greater than the present pOSition,
the state-machine-based motor control drives the stepper
motor clockwise. lithe position is less, the controllerdrives
the motor counter-clockwise.
The X-V controller design would occupy 77 percent olthe
1,200-gate XC2064's logic blocks and 47 percent of its
1/0 pins. Or if the 1,800-gate Logic Cell Array were used,
the X-V controller would occupy just 49 percent of the logic
blocks and 36 percent of its 1/0. The remaining logic and
1/0 blocks can be used to build chip select logic to make a
clean interface to the microprocessor.
Four EPLD macrocells are required to implement the
state-machine for each half of the position controller, while
seven Logic Cell Array logic block.s are required to implement the same function.
The architectural differences between the two technologies allow a design which requires an entire 1,800-gate
EPLD to fit in just a portion of a 1,200-gate Logic Cell Array.
The EPLD can perform anyone of the required tasks quite
To signal the processor that the entire operation is complete, an open drain interrupt signal is generated when
both the X-and the V-position motor have reached their
CLOCKWISE-X
CW
X-8IDE
DATA
LATCH
STATEMACHINE
HALF-8T
. T·BIT
UP/DOWN
COUNTER
7-BIT
COMPARE
CCW
X-8IDE
DONE-X
HALF-8TEP-X
X-GLOCK
OPEN-DRAIN
INTERRUPT
CLOCK
GENERATOR
-;---
-
-
-"
-1148 03
The schematic above Illustrates the X-axis half of the p~sltlon controljer used as the design example. The other half Is
identical to this cirCUit, and drives the Y axis instead of the
x.
7-6
E:XIUNX
well. The sum-of-products architecture allows EPLDs to
implement fast counter, decoders, and multiplexers in a
single pass. Combining these elements into a larger, more
complex system with additional passes through the array
however, hurts both performance and density.
equal gate counts will differ on functional density within a
system because of differences in architecture. A better
way to determine density is to countthe types and amounts
of various resources on the chip, and compare those with
the needs of your application .
The flexible Logic Cell Array architecture allows entire
complex systems to be implemented efficiently and
quickly. Given the same 1,800 gates of logic, and
1,800-gate Logic Cell Array could implement an X-Y-Z
position controller in the same density used to implement
an X-V controller in an EPLD.
• Understand which PLD architecture best suits your application. The sum-of-products (AND-OR) architecture is
well suited to applications that require ANDing of a large
number of inputs, like those found in address decoders
and some counters. The interconnect structure of an
AND-OR PLD makes single-pass logic functions quick
and efficient. However, the complex random logic requirements of higher-density logic design stretches the limits of
conventional AND-OR devices because of the feedback
requirements.
CONCLUSION
The benefits of programmable logic devices within any
design are generally undeniable. Both devices shown in
the design example (the EP1800 EPLD, and the XC2064
Logic Cell Array) replace many SSI/MSI components.
• Determine your 1/0 and register requirements. In most
AND-OR PLDs, outputs are hard-connectors to the registers within the device. Therefore, each register either uses
orwastes an 1/0 pin and vice versa. In the Logic Cell Array,
1/0 and registers are separated by programmable interconnects. Therefore, entire register resources like counters and shift registers can be buried without using or
wasting 1/0 pins.
However, not all PLDs are created equal. A designer
should contemplate his system needs and goals when
deciding which PLD to use. Like making the correct choice
of a system processor, the correct PLD choice will have an
impact on the final system performance.
Major enhancements in high-density PLDs will stem from
architectural. innovations rather than process-related
developments. Regardfess of which production process is
used, all PLD manufacturers are searching forthe optimal
mix of high performance, high density, and production cost
to best meet deSigner's logic needs.
Some guidelines and cautionary notes are necessary for
designers new to the PLD approach. These are:
• Be wary of PLD gates counts. As mentioned before, not
all PLDs are created equal. Equivalent gate counting is
used by many manufacturers to compare their devices
against a competitor's. Two devices with approximately
MegaPAL
Claimed Gate
Density
Architecture
Times.
MegaPAL
EPLD
EPLD
LCA
LCA
1,500
5,000
1,200
1,800
1,200
1,800
AND-OR
AND-OR
AND-OR
AND-OR
Array
Array
MMI
MMI
Altera
Altera
Xilinx
Xilinx
Inputs (max.)
32
64
36
64
58
74
Outputs (max.)
Storage Elements
16
32
24
48
58
74
16
32
28
48
64
100
0
0
12
0
58
74
40
50
50
50
45
45
16
16
20
23.2
58.8
58.8
Developed By
Elements
Speed For
16-lnput AND
(ns, On-throughOff, fastest)
Register-ToRegister Clock
Frequency (Max. MHz)
Quiescent
Power(W)
Packages
Process
114804
Reprinted with permission from Electronic Engineering
Technology
1.4
3.25
0.Q15
0.001
0.025
0.025
40DIP
44 PLCC
84 PLCC
88PGA
40DIP
44 CJCC
44 PLCC
68CJCC
68 PLCC
68PGA
48DIP
68 PLCC
68PGA
68 PLCC
84 PLCC
Bipolar
Bipolar
CMOS
CMOS
CMOS
CMOS
Fuse
Fuse
EPROM
EPROM
SRAM
SRAM
Shown above is data on several types of high-density EPLDs. Though the MegaPAL devices offer the most gates, they
are bipolar, fuse-based design, and so are not reprogrammable.
.
7-7
ESD:
Programmable Logic
Betters the Odds for
Bet-Slip Readers
THE EleCtroniC System DeSign MagaZIne
by Cliff Dutton, GTECH Corp., Providence, RI
In countries throughout the world, the vitality of the on-line
lottery industry is enhanced by seasonal and special
promotional games. But new games require new bet-slips,
and bet-slip readers must be able to accommodate frequent changes in format. To accomplish this, programmable gate arrays are replacing older, less flexible architectures.
the sensor interface. Similar difficulties hindered direct
comparison of achieved resolution. To accurately evaluate these parameters, each sensor had to be designed into
prototype readers; This involved driver and frame acquisition clock signal generation.
Because lotteries have no standard bet-slip size, as many
"standards" as possible need to be accommodated. Thus,
it was necessary to maintain flexibility in the format of the
target image.
In the development of GTECH's Solid State Reader, many
existing technologies were evaluated, but they imposed
unacceptable limitations on bet-slip processing, restricting
bet-Slip formats to rows and columns. Moreover, the
process of reading the coupons was dependent on complex moving parts, and the reading elements were exposed to the external environment.
PROTOTYPING A SYSTEM
The implementation of a prototype system had one goal:
to prove the feasibility of recognizing handmade marks in
an imaging system. Because the volume of readers is
potentially high, component costs were a serious issue.
To maximize flexibility and minimize board space, Xilinx's
(San Jose, CAl Logic Cell Array (LCA) was chosen forthe
Solid State Reader. The LCA, touted by the company as
a "programmable gate array," represents a novel programmabie logic device that is notable for its reprogrammable
architecture. This architecture provides flexibility throughout the product's life span, which allows on-line bet-slips to
be produced with marks in any arrangement. Each bet-slip
reader at every terminal can be configured on-line to read
any bet-slip from an active suite of eight different bet-slips.
BOARD 1 MAIN CPU
COMMUNICATIONS
LINK
PROCESSOR
MEMORY
CONTROL LOGIC
BOARD 3
Figure 1 shows three lottery bet-slips. Some of the
pertinent features of the European Lotto game slip (a)
include strobe marks along the top edge, the OCRB-3
characters (bottom center), and the name and address
field (bottom right). In the sample bet-slip from a lottery in
the U.S. (b), there are no OCR characters or name and
address information. However, there is an area from
which handwritten information must be extracted. Apart
from the different features, the aspect ratios of bet-slips
are not standard. Modern bet-Slip processing systems
must be able to read all of the different formats in many
aspect ratios. A format that forgoes the usual row and
column arrangement (c) is also depicted.
BOARD 2
CLOCK
GENERATOR
AND DRIVER
CIRCUITS
ANALOG SIGNAL
CONDITIONING
CIRCUITS
BOARD 4
IMAGE SENSOR BOARD
PRECISION OPTICS
As there are no standard architectures or interfaces for
image sensors, GTECH evaluated many image sensor
approaches. However, direct comparison of sensor performance could not be made in the application environment. For example, comparisons of sensor sensitivity at
the pixel level were impossible due to the differences in
sensor-interface electronics. If degraded sensitivities
were evident, they could derive from either the sensor or
Figure 2. The goal of developing a prototype bet-slip processor (shown above) was to prove that handmade marks could
be recognized in an imaging system. Four boards were
initially developed for this modular design: CPU/memory,
clock-driver, analog amplifier, and sensor mounting.
7-8
l:XIUNX
First, a working model was developed. To balance development costs, a set of printed circuit boards based on TIL
logic devices was manufactured. Partitioned functionally,
the board set supported modular design changes. Fourpc
boards were initially developed: a CPU/memory board, a
clock-driver board, an analog amplifier board, and a sensor mounting board (Figure 2).
In the initial design, flexibility did not exist. Even though
modularity protected the design from becoming obsolete,
significant design alterations were required to accommodate different sensors. Because sensor clock signals are
multiphase, new clock generators would be needed for
new sensors. Also, bugs were difficuH to find, and circuit
board modifications were required to eradijate such bugs.
(a)
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Figure 1. Betting slips for lotteries come in varied shapes and sizes. (a) Shown here are lotto slips from Europe
and (b and c) the United States. Such variety in slip design must be accommodated in the developement of bet-slip readers.
7-9
Article Reprints
Finally, the target image aspect ratio was fixed because
the clock generation 'circuits were implemented in hardware.
Semicustom and full-custom technologies would have
solved all the functional problems, but they lack flexibility.
Because the development of the reader was ongoing, the
commitment to custom implementations was out of the
question. In addition, nonrecurring engineering (NRE)
costs were prohibitive and the devices could not be
adapted to changing sensortechnologies or changing betslip reading requirements.
Aspect ratios of target images are important because only
necessary information on the image needs to be processed. If the tjrget image is 2:1 and the imaging format is
1:1, for example, then half the image is useless. A better
solution would mirror the aspect ratio of the target image
in the image format.
Xilinx's LCAs permit a two-board set to be designed
without sacrificing functional modularity. In addition,
counting algorithms can be implemented in the LCAs.
Finally, LCAs allow for a multiple-iteration development
cycle.
To overcome the limitations of hardwired logic and reduce
board space, several technologies were evaluated. These
included programmable logic arrays (PLAs), field programmable logic devices (FPLDs), semicustom and
fullcustom devices, and Xilinx's Logic Cell Array (LCA).
PUTTING A BUG TO REST
Size constraints indicated the necessity for semicustom of
full-custom integration, but traditional LSI technologies
violated the flexibility constraint. Although full-custom was
attractive, design costs were prohibitive and did not permit
iterative development. Standard PLDs did not allowforthe
variety of register-like functions that the clock generation
logic required.
Initially, the TTL-based system was implemented infourpc
boards. However, it contained a bug. For every horizontal
line, an extra pixel pulse was being supplied. Although this
was confusing to the eye, it was compensated for in
firmware. Because the redesign of the clock driver board
was a significant task, the bug was allowed to live through
many iterations of the development cycle. When the
design of the clock generation circuit was translated into
the LCA, it was a trivial matter to delete a single horizontal
clock pulse and put the bug to rest in an aftemoon.
Programmable logic arrays were attractive for some logic
functions and would have been the least costly. However,
PLAs did not allow the multiple register implementation
necessary for clock generation. Thus, the counting algorithms would have remained external to any integration of
the combinatorial logic. Also, although the PLA architecture would have saved board space, it would not have
preserved the functional modularity achieved in the first
implementation. Thus, it would have been impossible to
evolve a PLA-based system in response to changes in
sensor technology. Finally, any required changes would
have to be performed by field replacement. With over
35,000 lottery terminals installed on five continents, this
was unacceptable.
Using the LCA also provided the ability to vary the clock
generation circuitry to evaluate different sensors. Because there is no standard architecture for solid-state
digital imaging devices, clock requirements vary for different sensors. In a standard imaging application, it might be
possible to source the appropriate support chips for each
sensor from the manufacturer. But because development
of the reader involved nonstandard video speeds in a
noninterlaced mode, it was impossible to use standard
support chips. If it had been necessary to develop a clock
driver pc board for every sensor evaluated, it would have
been impossible to evaluate more than one sensor in the
development time. Because LCAs were used, varying
multiphase clocks could be generated for different sensors
under evaluation. Thus, the turnaround time for a design
change in the clock generation circuits was reduced from
one to Sixweeks to one day.
Field programmable logic devices, an update of the
PLA-style architecture allowing limited reprogrammability,
appeared to provide some of the flexibility needed. If the
problem were merely a straight combinatorial one, FPLDs
could have been used. However, the difficulty in supporting both registers and counting algorithms ruled out their
use.
7-10
SINGLE MAIN BOARD
PROCESSOR
MEMORY
The Solid State Reader does not rely on standard video
output. Thus, the 4:3 standard aspect ratio for broadcast
television is not a requirement. All image processing is
internal to the system. Real-time display of the image is
never required. Therefore, only those areas of the sensor
that may contain relevant information need to be required.
Information-bearing areas of a bet-slip vary with the betslip deSign, so it is helpfulto redefine the area ofthe sensor
that is acquired for processing.
COMMUNICATIONS
LINK
ANALOG
CIRCUITS
Because the clock driver circuitry, the memory addressing
logic, and the frame-grabber logic are all implemented in
the reconfigurable LeA, it is possible to acquire only
certain areas of the image. As each sensor has different
horizontal and vertical clock pulses, this flexibility cannot
be achieved in hardwired logic.
SENSOR
SOARD
IMAGE SENSOR BOARD
PRECISION OPTICS
Figure 3 illustrates the current architecture of the Solid
State Reader. Because of the functions consolidated in
the LeA, the system was reduced from four pc boards to
two. This could have been done using other technologies,
but they would not have preserved the functional modularity of the system. The LeA-based design provides both
size reduction and functional modularity,
114806
Figure 3. GTECH's Solid State Reader uses Logic Cell
Arrays (LCAs) to maximize flexibility and minimize board
space. Frame·grabber, memory addressing, and sensor clock
driver functions are cOl)solidated in the LCA. By reducing the
number of chips, the required number of boards shrinks from
four to two.
Reprinted with permission from ESD: The Electronic
System Design Magazine.
•
7-11
Using Programmable Logic
Cell Arrays In a Satellite
Earthstation
Dave Farrow, MIA-Com Telecommunications, Germantown, MD
Conventional programmable logic devices (PLDs) include
several interesting variations of latch-based AND-OR
plane architectures in various technologies, all of which
are useful for low-gate-density applications. Typically, a
PLD can replace five to ten SSI/MSI parts.
3 Mbls transmission rate. The earthstation product, called
an OPT (for On-Premises Terminal) is a "small-aperture"
satellite earthstation, permitting efficient employment in a
large number of remote locations, as illustrated in
Figure 1.
A newer digital logic technology with an array architecture
and flexible interconnection offers the programming flexibility of PLDs plus the gate density of low-end gate arrays.
Architecturally, these devices have some Similarities to
gate arrays: they contain an internal matrix of logic blocks
and a ring of configurable I/O interface blocks. Unlike
conventional gate arrays, each part is a standard off-theshelf unit that can be programmed by the user. The
configuration program is automatically loaded into an onchip static memory at power-up from either an on-board
EPROM or an external source such as a floppy disk.
Two main components comprise the OPT: an indoor unit
and an outdoor u nit. The outdoor unit includes the antenna
and associated radio-frequency equipment.
At the outset of the design process, the indoor unit was
intended to be contained in a small chassis that cou Id
support three standard-size boards. The boards originally
planned for the system included one board each for
controlling data traffic, transmit functions, receive functions, and demodulation. However, the chassis provided
space for only three boards.
Project goals included the use of an existing proprietary
custom chip design from a previous application. MIA-Com
also investigated whether the design could be fit on only
two boards, by using a gate array. Board design itseH was
driven by three primary factors: resource availability, cost,
and schedule. Since reducing the number of required
boards would reduce design time and keep product costs
lower, MIA-Com decided to go with the gate array.
THE EARTHSTATION SYSTEM
MIA-Com recently employed one of these "programmable
gate arrays" in the design of a satellite earthstation, intended to network commercial facsimile operations. The
network handles traffic at 56 kbls, multiplexed into 26
channels and convolution ally encoded, yielding an overall
EACH ON-PREMISES
TERMINAL HAS ITS OWN
TRANSMIT FREQUENCY
GROUPS OF ON-PREMISES
TERMINALS SHARE A
RECEIVE FREQUENCY
Figure 1. Satellite System
7-12
UP TO 5,000
ON-PREMISES
TERMINALS
HUB
1148 07
OTY.
DESCRIPTION
ITEM
3
8-BIT SHIFT REGISTER
74HCT164
6
4-BIT COUNTERS
74HCT163
4
DUAL D FLIP-FLOP
74HCT74
2
OUAD2:1 MULTIPLEXER
74HCT157
1
OUADXOR
74HCT86
1
HEX INVERTER
74HCT04
1
OUADNOR
74HCT02
port controller and handles base-band X.25 data. Due to
the use of semicustom and programmable technology, the
remaining three functions were all merged onto the other
board, which we call a "satellite channel interface" (see
Figure 2).
1148 08
Table 1. Standard Off·the-Shelf Equivalents to the Logic
Contained In the LCA.
We used a gate array for the transmit function, which
otherwise would have required about 70 chips. For the
receive function, we originally planned to use an existing
full-custom ASIC (previously designed by MIA-Com) for
forward error correction, and an additional 25 SSIIMSI
parts for the receive logic. However, due to chassis
constraints, the high density of components would have
necessitated a multi-layer board for the initial design.
Furthermore, based on previous experience, the likelihood of changes in the design specification was too high
to risk a custom or semicustom solution for the initial
design. Therefore, we originally planned to produce the
high-density boards in quantity and to reduce the cost of
the system at a later date, by first transferring the receive
logic into a gate array and then replacing the expensive
high-density four-layer board with a tWO-layer board.
The completed design employs a full custom IC, a gate
array, and programmable logic, and subsists on only two
boards. On one board, an Intel processor acts as a traffic-
While the design criteria were being prescribed and boardlevel functionality was being determined, we also investigated the newer programmable gate-array technology.
The programmable part, the Xilinx Logic Cell Array (LCA),
2
OUADOR
74HCT32
3
OUADAND
74HCT08
1
OCTAL LATCH
74HCT374
1
OCTAL BUFFER
74HCT244
251Cs
TRANsMmER
ADDRESS
ADDRESS
a:
o
f/)w
f:l~
g~
a: w
a. ...
Oz
a:-
o
:iii
KEY
114809
•
!TIl LOGIC-CELL ARRAY
o
o
FULL-CUSTOM CHIP
GATE ARRAY
Figure 2. Block Diagram of Satellite Channel Interface.
7-13
Article Reprints
UNIQUE WORD SENSE
STATE
MACHINE
(4 STATES)
15
::;~
0:::>
tt:o
LLO
::;
W
0
a:
0
::;o(/)
Oa:(/)
a:O w
LL-g
::;a:
a.
r'
DATA
MAG
DATA
TPP
DATA
{
DEMUX-SGN DATA
WR
RD
DEMUX-MAG DATA
KEY:
[j
[j
Iffil
DEMULTIPLEXER
DESCRAMBLER
DEMUX-CLK
TIME-DIVISION MULTIPLEXER
(SYNCRONIZATION CIRCUITS)
1148 10
Figure 3. A Schematic of the Digital Systems Incorporated into the LeA.
in-circuit emulator for debugging.
is architecturally similarto a gate array and is supported by
a PC/AT-based workstation.
Ouroriginal schematic was based on conventional LS and
HCT parts; it included JK flip-flops and large counters
(implemented by cascading common 4-bit counters),
rather than gate-level elements. Since that method of
design was inefficient for the LCA, we redesigned the
receive circuit at the gate level and then implemented it in
software via the cell array editor.
We determined that the internal organization of the LCA
fitted the design requirements of the receive function.
Specifically, the LCA provides many more flip-flops than
other programmable logic devices, so that one chip contained enough functionality for our needs. Further, the
LCA provided the required density savings, and its reprogrammability obviated the risks associated with late engineering changes. When engineering management was
presented with the design alternatives, we decided to
prototype a reduced portion of the receive circuit and thus
evaluate the reconfigurable Chip.
Using an LCA reduced the amount of hardware overhead
normally associated with LKS and HCT technology. It was
not necessary to waste control inputs, to cascade counters, or to determine whatto do with unused bits of multiplexers. In our design, 25 SSI/MSI gate-equivalents did
not even use up all the resources available in one LCA.
Table 1 indicates the parts that we actually employed in the
present design. Putting these functions in the LCA resulted in an 88% utilization of the internal cells, and a 60%
utilization of the I/O cells. Thus it still remains feasible to
add further functionality to the system, with no PCB
To implement the design, MIA-Com acquired the Xilinx
XACT PC-based LCA development system. The system
includes a macro library, with some of the required logic
already defined. After several days of experimenting with
the design tools, it took us one day to enter and only two
hours to debug the design. We uses Xilinx's XACTOR
7-14
I:XILINX
The fourth state is entered every time a unique word is
missed; the system stays in the fourth state until the unique
word is found or is missed 11 consecutive times. If the
unique word is found, the system returns to state three; if
it is not found after 11 attempts, then the first state (the
search mode) is initiated again. This method of operation
ensures that the demultiplexer will remain locked even in
the presence of random bit errors in the data stream.
changes. We plan to do so in the future. Figure 3 is a
schematic of the circuit placed in the LCA. Since the
design is not 110 limited, there was no necessity to multiplex any of the input or output lines; but additional logic
could have been added, should 110 multiplexing been
needed. Note also that the descrambling circuit can easily
be reconfigured, or made more complex. Changing the
descrambler can be achieved merely by reprogramming
the LCA.
After the unique word is detected, the receiver locks onto
the data. The LCA chip then de scrambles the data stream.
The data is originally scrambled by the transmitterto place
a fairly equal number of ones and zeros into the transmitted carrier. If this is not done, the transmitted carrier may
not contain an even distribution of spectral components,
which makes it difficult for a demodulator to acquire the
carrier. The descrambling process is. merely the reverse
of the 9-bit scrambling procedure.
One criticism leveled againstthe LCA is that it requires 12K
bits of storage space to program the part during power-up.
However, in our deSign, a 27C64 EPROM (used for a lookup table) was already on the board. A portion of this
EPROM was available to store the LCA configuratic:>"
program at no additional cost. Since the 12K bits of
storage space are used to program all the RAM cell
locations in the LCA, adding furtheffunctionality to the
LCA would not require more storage space.
.
A single channel is isolated from the others by demultiplexing the descrambled data stream. The demultiplexing
function is performedthrough a pair of counters that count
the bits between unique words and tell the demultiplexer
when data is available.
.
ARCHITECTURE
From the OPT, transmission is executed in the SCPC
(single channel per carrier) mode. All scrambling, encoding, and error-code generation are performed by
MIA-Corn's proprietary transmit gate array. The gate array
contains registers, allowing it to be programmed to. transmit in different schemes and protocols, including scpe
mode. .
.
Once the incoming data stream has been descrambled
and demultlplexed, it moves on to the MIA-Com proprietary convolutional decoder, a custom chip where error
detection.and correction is done on a per-channel basis.
Decoded data is passed on to.a microp~sor forda:ta
extraction.
.
a
The qPT' receives' TDtvI (time n-Ifne for a wf;leK to
ensure a thorough test of the Xilinx part under operational
conditions: Our concern was how well the lCA:would
retain its configuration, since this information is stor~d by
RAMc~lls. HOV'f,ever, in our. environment,it performed
flawlessly.
7-15
Article Reprints
UNIQUE WORD
MISS >1
UNIQUE WORD
DETECT
UNIQUE
WORD MISS
UNIQUE
WORD DETECT
UNIQUE
WORD MISS
UNIQUE
WORD DETECT
114811
Figure 4. State Machine for the Time·divislon Multiplexer.
OPEN·END I;)EVELOPMENT
Late into the design cycle we began to add additional
planned functions to the LCA. Because we knew we could
add these extra features, we finished the PCB layout and
ordered PC boards without waiting for the final design.
Then the process of adding putting functions into the LCA
was begun.
basic digital circuitry. For example, designers must be
able to recognize the worst-case timing scenarios of their
networks. Delay and system-speed considerations can
now be checked with the Xilinx Simulator, but atthe time of
our deSign, the simulator was still in beta test; we calculated the circuit behavior with preliminary timing software.
Since then the simulator has been revised and its present
version would have spotted our timing error.
Normally this. time would have been used to design a test
fixture. Instead, another LCA design was created to
support a test implementation. Before the PCB was
delivered, the test fixture simulating the system was built,
primarily around the second Xilinx part. In the process of
building the fixture, we discovered an error in the PCB
layout, even before it was delivered. It was possible to fix
the error by reconfiguring the LCA.
Rather than packing complete deSign into the front end of
an ASIC development, as is required for conventional gate
arrays, the LCA offers the flexibility to indicate roles forthe
part. Designers can specify the lID pins for the LCA then
send the PC board to fabrica\ion. While the board is in
fabrication, designers can build into the LCA the gate-level
logic they want and continue to make changes up until, and
even after, the PCB is delivered.
When the board was delivered, a new version of our logic
design had been implemented in the Xilinx LCA, including
the demultiplexing and descrambling functions.
After final product delivery, the on-board logic can still be
reconfigured to match specific customer needs-without
having to cast custom silicon for a few dozen units or
changing the PC artwork. Great NRE savings are passed
back to the customer. In summary, the LCA has proved to
be an extremely efficient, useful, and cost-effective extension to our semicustom design capabilities.
CONCLUSIONS
The flexibility of the Xilinx LCA lowers design costs,
reduces project schedule risks, and reduces inventory
risks. Using the LCA does not requir~ much design
sophistication, but rather a good general knowledge of
Reprinted with permission from VLSI System Design.
7-16
ESD:
Faster Turnaround
for a T1 Interface
by Carl Erite, Teltrend Inc., St. Charles, IL
Important design considerations for an interface system to
a digital T1 network (which carries voice, data, video and
fax traffic at rates up to 56 Kbytes/sec) include conserving
board space, improving throughput and reducing power
consumption. The user interface is achieved via a conventional four-wire loop providing independent transmit and
receive capabilities. In designs that Teletrend Inc. initially
conS.idered for a single;.user T1 interlace; 5.000 gates of
conventional SSIIMSI glue logic were to be integrated
using two custom gate arrays. However, a short development cycle and low market risks were also desired. This
led to a search for an aHetnative to th time-consuming
process of casting two gate arrays.
design requirements-high integration, high density, high
performance,low cost, low risk and quick time-to-maiket.
The Xilinx devices implement a digital phase-locked loop,
as well as the T1 transmilterand receiver. A Hitachi
microprocessor provides overall intelligence to handle T1
Controls, network code manipulation and other tasks.
The dual digital phase-lock loop provides the key function
of the system. Data on the user interface is encoded with
the clock signals, a process that may occur at various
send/receive data rates. Data extraction from the user
interface must be phase-locked and, at the same time,
data must by synchronized with the T1 network clock. A
Xilinx LCA implements the phas!,-Iocked loop that synchronizes both the interface and the T1 network.
Upon completing the initial circuit deSign, a breadboard
was built using CMOS SSIIMSI logic components. After
the breadboard was working, integration path decisions
were needed. Instead of. hard-tooling two custom gate
arrays, designers detennined that three standard, programmable Xilinx L?gic Cell Arrays (LCAs) met all of the
The second LCA transmits data onto the T1 network.
Here, data transmits serially at 1.544 Mbits/sec in one of
the 24 assigned time slots. A unique data word to be
RECEIVE DATA AT BAUD RATES FROM
1.2K TO 56K ARE PI1ASE·LOCKED TO
THE RECOVERED BAUD RATE CLOCK
AND TO THE T1 NETWORK CLOCK.
RECEIVE DATA
STANDARD 4 WIRE
USER INTERFACE
FOR SUBSCRIBER
LOOP SERVICE
T1
TRANSMITTER
TRANSMIT·
DATA
AT 1.544
MBlTSiSEC
T1 NETWORK CLOCK
LOGIC TO
TRANSMIT
TO USER
TRANSMIT DATA
CONTROl
MICROPROCESSOR
T1 RECEIVER
WITH a-BIT
CRCERROR
CORRECTION
r--
I
I
I
I
I
I
I
DUAL PI1ASED·
lOCKED
LOOP
FOR
RECEIVER
-------
r----
RECEIVE
DATA
AT 1.544
MBITSISEC
i
I
I
I
I
I
I
I
I
I
I
I
I
I
,
I
L ___ _
T1 SWITCH
WITH ONE
ASSIGNED
TIME SLOT
1148 12
Figure 7. Teltrend's digital TI interface is built around three user-programmable Xilinx Logic Cell Arrays in lieu of two conventional
gate arrays. One LCA implements a dual digital phase-lock loop around four-wire loop; other LCAs form both the transmitter and
reciever logic circuits, including error correction.
7-17
Article Reprints
transmitted is held in the LCA while logic synchronization
determines the start 9f the first time slot or the beginning
ofthe data frame. The assigned time slot is found by
counting titne slots from the start of a complete frame.
After locating the assigned time slot, data is transmitted
onto the T1 network.
higher performance in critical timing paths and higher
overall device utilization. In all three designs, LCA logic
resource utilization exceeded 95% ...
All three deSigns are flip-flop intensive,involving multiple
counters, shHters, registers and other memory-oriented
functions. The LCAs provide more flip-flops per. device
than any other programmable logic alternative. Only a few
simple8-blt.registers were implemented externally with
octal devices. Next-generation designs will. use Xilinx's
compatible higher density devices to achieve greater logic
density in the same socket.
A third LCA, complementary to the transmitter function,
receives data. It also furnishes complete error correction
for incoming data. Time-slot detection logic dete.rrnines
the start of data for the assigned ch~nnel. Serial data
comes from the T1 network. After the LCA performs 8-bit
error correction, the data passes to the processor and user
interface.
Overall, the ability to enter the original design using the
Xilinx LCA XACT design system ensured that all the
integrated logic functioned as desired before the part was
placed in the system. With a conventional gate array, the
design might still be waiting for silicon, since turnaround
times for production quantity gate arrays typically range
from 8 to 16weeks (production quantities).
The first iteration of the design was extrpcted directly form
the CMOS breadboard schematics using the Xilinx XACT
system running on an IBM PCIAT. The working design for
the first device was completed in two weeks, with some
time-critical elements moved off the Chip. Designs for the
second and third parts took about the same time, but
additional interaction during the design process resulted in
Reprinted with permissiol1 from ESO: The Electronic System Oesign Magazine.
.
7-18
Two, Two, Two Chips in One
By Tom Liehe, Principal Design Engineer, Test Instrument Division, Honeywell Inc., Denver:Colo.
Designers at Honeywell picked the RAM·based Xlllnx
LCA for Its shon development cycle, and realized
savings In board real estate through Its dynamic
.
reprog ram mablllty.
Errors on tape typically are caused by tape defects, dirt,
head clogs, etc. Because these error bursts can be
thousands of bits long, sophisticated ECC techniques are
required. Initially, two basic circuits, using Reed-Solomon
algorithms and TTL technology, were designed. These
were the ECC encoder and decoder.
Advances in one technology often lead to improvements in
other, mor'e dated design and manufacturing practices. A
recent example of this occurred at Honeywell during the
development of a high-capacity digital tape recorder.
The write portion of the circuitry (the encoder) uses a bytewide linear feed~back shift register (LFSR) to create a
58-byte code word form each 64-byte incoming message
block. During operation, parity check bits are computed
based on the data within a block of the message to be
encoded. These check bits are appended to the block to
create the code word.
Honeywell's original objective was to design the VLDS
(very large data storage) recorder, taking maximum advantage ofthe available analog technology currently being
used in standard VCRs for home use. The recorder
developed under this program uses digital rotary technology to record large amounts of data on a standard VHS
video cassette. It transfers data at a rate of 4 Mbauds, and
is able to store 5.2 Gbauds of information on a single BHS
tape. Its major planned application is in capturing and
storing digital medical images, such as those produced by
a CAT scanner.
During decoding, the code words are checked for errors by
regenerating the parity bits which are then compared with
the check bits. If they match, it is assumed that no errors
have occurred. If they do not, the pattern of mis-matches
(called the syndrome of the error) is used to compute the
corrected form of the message block.
When this recorder was in the prototype stage, it became
apparent that the addition of an error-correction circuit
would significantly enhance system performance. This
requirement dictated the design of an entirely new and
major logic circuit to accomplish the desired error correction.
The ECC decoder (the read circuit) required a partial
syndrome generator and the solution of a set of simultaneous non-linear equations to determine error locations and
values. ThiS error-determination step is performed by a
special-purpose processor with a microinstruction sequencer,a finite field arithmetic unit, two discrete registers
and an eight-word memory. The correction step is then
accomplished in circuitry whereby the error values are
exclusive-ORedwith the message althe address given by
the previously computed error 10caUons.
Design of this circuitry would not normally be a problem,
but at this. stage of development, there were several
challenges. First, the design allowed almost no circuit
board space for addition ofthe error correction code (ECC)
circuitry. Second, very tight deadlines were being faced if
the promised delivery date was to be met.
Using wrapped-wire t~cliniques, a working prototype of
the ECC circuitry was developed. However, it was quickly
recognized that the long leadUme required to design and
fabricate a factory-programmed gate array to replace this
prototype TTL cirCUit was not practical with the tight
delivery schedule.
The entire system was housed in a 19-inch-wide by
20-inch-deep rack-mounted cabinet. The cabinet already
contained eight separate circuit boards, and there was
room enough for only one additional board to incorporate
the ECC circuitry. Space was at a premium. The goal was
to design and manufacture a 10-12 corrected bit error rate
circuit that could be contained on one circuit card. The
targeted time for completion of this work was tnree
months.
An option ,considered, but not chosen, was to design and
fabricate a conventional gate array. The considerable
design time required, together with the inherent risks
associated with masking and manufacturing a custom
logic circuit, made this an unattractive alternative.
7-19
•
Article Reprints
XILINX'S LCA
ANOTHER BENEFIT
Finally, the search for an alternative solution led to the
discovery of a programmable gate array known as the
logic cell array (LCA) , designed and manufactured by
Xilinx Inc. (San Jose, Calif.). The LCA is a standard, offthe-shelf device that is custom configured to the
customer's requirements by means of the Xilinx development system. This development package consists of a
personal-computer-based software system combined
with an in-circuit emulator.
Another significant. benefit derived from the use of the
Xilinx LCA was reduced power consumption. The original
bipolar IC design consumed approximately 12 Wof power.
Through the use of CMOS technology, the replacement
LCA consu mes only 50 mWof power. It should be pointed
out that the bipolar version was capable of operating at
.a much higher clock rate than the LCA. However, the clock
rate used this particular design was only.2 MHz. The
speed of the LCA was, therefore, adequate for the VLDS
application.
Use of theLCA seemed to be the ideal solution to the time
constraints. SO,a Xilinx XC2064 LCA was sected. In this
device, any logic function having up to four variables can
be implemented in anyone of the 64 configurable logic
blocks (CLBs). Optionally, results can be stored in either
a latch or a flip-flop. Thus, implementation of the design
can be constrained by a fixed set of standard logic elements.
Because the required logic circuitry was already designed
and tested, the development of the configuration program
for the LCA went very smoothly. It took only two days to
configure the circuit using the Xilinx XACT LCA development system running on a standard, IBM-compatible personal computer. The primary effort involved was the
partitioning of the logic to match the capabilities of the LCA.
The I/O pins of this device also can be configured as
registered inputs. The large number of flip-flops, plus the
ability of each CLB to function as four-input exclusiveORs, made this LCA ideal for ECC circuit implementation.
For a regular, repetitive design, a small portion of the logic
was defined. This portion was then copied .and minor
modifications were made to complete the design. The
byte-oriented nature of the RS ECC circuitry lent itself to
easy entry. Starting with tables showing the bits to be
exclusive-ORed, the entire circuit was entered in a few
hours.
MULTIFUNCTION CAPABILITY
One of the real benefits of this LCA is its multifunction
capability. The capability of performing a number of
functions with the same device provides optimum utilization of circuit board space. This was a real bonus with the
VLDS recorder. At any given time, the VLDS operates in
only the read or the write mode~t is never required to do
both simultaneously. Consequently, the same LCAcouid
be reconfiguredelectronicalfy to perform one function in
the write mode, and a completely different fUl1ction in the
read mode. This versat1lity eliminated the need for two
separate circuits, and thereby conserved space.
The software simulation capability, which enabled the
modeling of physical delays and logic functions, resulted
in a very high design confidence factor before the first
hardware checkout. The simulator provided both tabular
output and logic analyzer style waveforms, which aided
.considerably in the visualization of the circuit performance. A high-level language program was used to generate expected results of the encoder, and to perf9rm
partial syndrome generator simulations. This greatly
aided the evaluation of the simulation output.
By using the in-system emulation feature, configurations
were. loaded directly from the PC to an LCA mounted in
the target system; Thus, the usual step of programming
an EPROM from which the LCA can boot itself was eliminated. Initial design Checkout of the ECC circuitry was
performed using the emulator connected to the wrappedwire board containing the diserete IC version.
The LCA has a usable density of 1,000- to 1,SOO-gate
equivalents, and is capable of replacing up to 75 SSI/MSI
devices, five to 15 PALctype devices, or some combination
of both. Inthe VLDS, the entire ECC en.codel' and the
partial syndrome generator portion of the ECC decoder
wererepJaeed by the LCA. The initial encodercircuitused
eight identical PALs, each of which implemented a 1-bit
slice of the Shift register, and four PROMS. The original
partial syndrome generator design useclsix PALs and four
74LS374 tri-state octal flip-flops to .store the four syndromes. Thus, the LCA replaced a total of 14 PALs, four
2S6k x 8 PROMs and four 74LS374s, or a total of 22
20-pin Dips;
There was a problem with the encoc;ler circuit that was
delaying data for an extra byte. Correcting this problem
required re.moving the input flip-flops or) the LCA. The
entire process ofreentering the LCA editor. removing the
mouse and reloading the new cOnfiguration took no more
than five minutes.
7-20
E:XIUNX
Compared with the time required to rework any other type
of hardware, the LCA is the only way to go. Also, taking into
consideration the high costs associated with reworking a
factory-programmed gate array, or even a semi-custom
PLD, the LCA technology is an extremely cost-effective
alternative.
using equivalent discrete ICs. And finally, the ability to
perform design entry, simulation, emulation and in-system
testing through the software development system facilitated quick and easy implementation of the user's ideas.
Today, the Honeywell VLDS offer error correction as
powerful as most major computer tape subsystems. It is
ideally suited for the newly developing imaging technologies used in electronic office documents, advanced geophysical analysis and computer-aided graphic arts. Withoutthe Xilinx logic cell array however, Honeywell could still
be waiting for a custom gate array.
In summary, the Xilinx part was well suited for our application because of its high flip-flop count and its ability to be
configured in exclusive-OR trees. Additionally, its capability of being electronically reconfigured while in the system
(when switching from write to read) offered significant
savings.
Reprinted with permission from Electronic Engineering
TImes.
Further, power consumption was much lower than when
•
7-21
ESD:
LeA Stars in Video
THE Electronic System Design Magazine
by Rusty Woodbury, Interactive Educational Video, Salt Lake City, UT.
Reprinted with permission from ESD: The Electrical Sys-
mines howto increment the counter. All of these functions,
plus logic to generate the read/modify/write cycle timing,
are implemented in a single LCA that replaces nine MSI
parts, four of which are PLDs.
tem Design Magazine.
The market for tools and overlay products for video pictures generated from laser disks is in its infancy. Applications for this emerging video-based technology can require high resolution and high performance, and the wide
variety of video disk players employed means that problems associated with varied noise characteristics must be
overcome. What works with one particular brand and
model in the factory may falter with another brand in the
field.
Two more LCAs implement a three-bit ALU. This technique achieves ultra-high-speed screen writes for both
horizontal and vertical lines. For many applications, these
are the most common lines drawn, so a special control bit
is used to simultaneously modify pixels. Horizontal lines
can be written at 14 Mpixels/sec instead of the normal
2 Mpixels/sec-a seven-fold improvement. Though more
logic could be placed in these two devices, a bit-sliced logic
approach permits continuous enhancements. Moreover,
a board layout can be defined at the beginning of the
product cycle while logic enhancements are made internally in the LCA. Nearly 30 SSI/MSI devices were integrated into the LCAs.
The Xilinx Logic Cell Array (LCA) helps to solve the
problem of meeting different system requirements because the device elevates hardware to the same level of
programmability as software. Before the LCA, once a
design had been committed to hardware, revisions to the
design could only be implemented via software changes.
A fourth LCA fully implements the graphics engine. To
read out data to the screen, scan counters pOint to memory. A shift register serializes at a rate of 14 Mpixels/sec.
USing traditional MSI devices, these functions require
about 10 chips.
Interactive Educational Video (lEV) has implemented
three separate designs and logic replacements with the
LCA. These functions reside on IBM PC expansion cards,
where space limitations would ordinarily preclude such a
design. Although application-specific video ICs could
perform similar functions, they cost more than the LCA and
offer lower performance.
The second design fabricated by lEV is a graphics controller (Figure 6). Using an external genlock IC, the LCA
relies on an NTSC composite sync signal to generate
timing signals forthe CRT display. Instead of using PLDs,
lEV uses the LCA to implement digital counter and timers.
The result is higher performance and reduced complexity.
The previous generation board has only half the functionality and demands four times the board space. To further
reduce complexity, the same hardware can be used with
a different configuration program to match a particular
video disk player's noise characteristics. Withoutthe LCA,
this design needs eight PALs plus 12 to 15 MSI devices.
The first application is a graphics engine that uses four
LCAs. Here, the LCAs replace over 50 SSI/MSI chips,
including four traditional programmable logic devices
(PLDs).
One LCA functions as the address generator for the video
memory. By relying on a pair of high-speed counters to
locate horizontal and vertical coordinates, memory write
functions (which implement line drawing) can perform at
high rates. Given the slope, starting point and length of
a line, the logic simply increments counters that point to
video memory locations. Scanning and writing to the
screen are interleaved. The data written to memory
corresponds to a particular color and, by simple incremental additions to the slope of the address pOinter counters, powerful line drawing functions are easily implemented.
In another lEV design, a PC serial port emulator integrates
a subset of the IBM PC serial port functions onto the
graphics card, making an IBM serial card unnecessary.
With the given space restrictions, this implementation
proves particularly cost-effective. Seven PLDs are required to match this design.
Reprinted with permission from ESD: The Electronic Sys-
Important to the design is the decision logic, which deter-
tem Design Magazine.
7-22
E:XIUNX
XC206.4 LOGIC CELL ARRAY
GRAPHICS
OVERLAY
VIDEO
DOT
CLOCK
ADDRESS
AND -~-..j
CONTROL
COMPOSITE
SYNC
INPUT
EXTERNAL
COMP~~~~ - - - 7 - - - -.....- - - - - . . j
TV
CAMERA
SYNC
GENERATOR
INPUT
VD
HD
14.318 MHZ
INPUT
FROM 3301 -'--~--I
\---=-,.,.
I
1---;,-.
HB
BFW
\---..,.c.----,.,:--'"+ GVB'
POSITION
DETECT,
I--~_GHB
114813
FigureS., IEVimplementatedari nelligenf GraphICS Overlay Controller.micropr6cessor peripherafwith one XG2t:l64logic Cet!·'
Array, replacing eight PALs and 12 MSI devices. Th.e controller generates all timing for a video graphicsoverfay by deriving the
,
necessary timin~ from the underlying video disk~giiaf.
II
Taking Advantage of
Reconfigurable Logic
by Bradly K. Fawcett, Xilinx Inc., San Jose, CA
An abbreviated version of this paper was published in the High
Performance Systems Programmable Logic Guide, 1989.
The availability of programmable logic devices based on
static memory cells now allows the implementation of
"soft" hardware-hardware whose functions can be
changed while resident in the system. When using most
current IC component technologies, hardware is indeed
"hard"; once a given logic function is implemented in
hardware, changing that logic is difficult, requiring modifications to printed circuit board traces, the addition or
replacement of components, and other costly measures.
However, with static-memory-based programmable logic,
changes can be made to a system's logic functions simply
by reconfiguring the programmable logic in the system.
This capability can lead to significant advantages for the
system designer. These include both product-related
benefits, in the form of smaller, less expensive, and more
reliable systems, and design-related benefits, such as
increased design flexibility, decreased risk, and faster
design cycles.
suit is smaller, more powerful, less expensive, and more
reliable systems. As an added benefit, use of reconfigurable LCAs simplifies hardware design and shortens a
product's time-to-market.
RECONFIGURING FOR SYSTEM DIAGNOSTICS
System self-diagnostics can be implemented by using
programmable gate array configurations dedicated to
testing functions. When the system is powered-up or
placed in a test mode, its programmable gate arrays are
configured with logic functions dedicated to testing other
circuitry in the system. Once the testing is successfully
completed, another configuration program is loaded into
the programmable gate array to implement the actual logic
of the particular end application intended for that system.
Typically, very little additional logic is required to add selfdiagnostic functions in this manner (usually just some
additional memory to hold the extra configuration programs). Such self-diagnostic capabilities make products
easier to manufacture, increase system reliability, and
simplify system maintenance, with little, if any, additional
cost.
Programmable logic devices capable of being reconfigured in the system are available to system designers in the
form of programmable gate arrays from Xilinx, Inc. The
Xilinx Logic Cell Array (LCA) architecture features three
types of user-configurable elements: an interior array of
logic blocks, a perimeter of I/O blocks, and programmable
interconnection resources. Configuration is established
by programming internal static memory cells that determine the logic functions and interconnections. The configuration programs can be loaded automatically at powerup or upon command at any time. Several available configuration loading modes accommodate various system
requirements. The benefits of a static-memory-based
device include high density, high performance, testability,
and the flexibility inherent to a device that can be programmed while resident in a system. Designers have
taken advantage of this capability in a wide range of
applications.
Designers at Tellabs Inc. (Usle, IL) used this strategy in a
voice compression module, an optional unit for the
Crossnet 440 T1 multiplexer. The design includes two
XC2018 devices, 1800-gate programmable gate arrays
(Figure 1). During normal operation, one LCA provides all
the interface logic for the board's microcontroller, RAM,
and system backplane, arbitrating accesses to the RAM
from the controller and the main system. The second LCA
contains most of the "glue logic" for the data compression
operation. However, both LCAs can be loaded with special
diagnostic configurations. In the test mode, the first LCA
connects the microcontroller to the RAM for memory
testing, and monitors controls on the system backplane.
The second LCA can receive timing information from the
microcontroller instead of the system backplane, verify the
data paths, and check the contents of the 32K-bit EPROM
used to implement the code converter's companding algorithm. Actually, two different test configurations have been
generated, and other diagnostic LCA configurations are
planned for a future upgrade. All the configurations are
present in memory on the board; the microcontroller
handles the downloading of LCA configuration programs.
The flexibility inherent in reconfigurable Logic Cell Arrays
(LCAs) can be used to create systems that are also more
flexible and, therefore, more powerful. Often systems will
include multiple configuration programs for their LCAs,
allowing varying operations to be efficiently performed
with a minimal amount of hardware. For example, reconfigurable logic can be used to implement system sejfe
diagnostics, create systems capable of being reconfigured
for different environments or operations, or implement
"dual-purpose" hardware for a given application. The re-
7-24
ADAPTABLE SYSTEM DESIGNS
system with logic that selects the appropriate configuration at the appropriate time. Many different types of applications benefit from this approach.
A similar use of reconfigurable logic is the implementation
of a single hardware design that can be adapted for varying
tasks or environments. In such systems, any of a number
of potential configuration programs can be downloaded
into a system's LCAs to alter the logic for particular
applications or operations as needed. Hence, more functions are implemented with fewer components, hardware
design costs can be amortized over a greater number of
systems, and design cycle times are greatly reduced. The
manufacturer could select the configuration program to be
included in the system dependent on the intended end
application or customer, or, alternatively, all the different
LCA configuration programs could be included in the
The Freeland Medical Division of Good Technologies Inc.
(Indianapolis, IN) used reconfigurable LCAs in this manner when designing a "frame grabber" board for the Cine'
View family of digital imaging systems. A mix of seven
XC2064, XC2018, and XC3020 LCAs are used on this
AT-format board, providing graphics control and interfacing a PC-compatible computer to the video output of
medical equipment such as ultrasound scanners and
magnetic resonance imaging systems. In orderto support
different video formats from the varying types of medical
instruments, several different LCA configuration programs
MICRoCONTROLLER
~t
ADDRESS + CONTROL
A
"-
A
v
XC2018
v
~
256x4
DATA
LCA
195301
A
"-
~
v
RAM
CHANNEL
SIGNALING
An LeA contains interface logic for the micro-controller, memory, and system backplane.
MICROCONTROLLER
fJ
"
XC2018 LCA
TIMING
I'LAW
DATA
TIMESLOT
AND
CONVERSION
CONTROL
"-
/I
tJ
CODE
CONVERTER
ROM
LINEAR DATA
NIBBLE/
TIMESLOT
INTERCHANGE
LOGIC
t
DSP
1953 02
A second LeA implements the glue logic for the data compression circuit.
Figure 1. LeAs in a voice compression system can be reconfigured to implement internal system diagnostics.
7-25
III
Taking Advantage of Reconfigurable Logic
are available for the LCA devices in the system. When
system operation begins, the user selects the desired
video format (monochrome or RGB color, for example);
the appropriate LCA configuration program is then loaded
to match that format. Thus, one hardware design can
support virtually any video format, without having to include customized hardware for each one.
A similar scheme was used on Tellabs' channel interface
cards forthe Crossnet 440 T1 multiplexer. Each channel's
PARALLEL·TOSERIAL SIR
.--8051
PROCESSOR
logic consists of an 8051. microcontroller and a 3000-gate
XC3030 LCA; four channels are implemented on each
card. Using a keyboard, the user can select from among
three communication protocols for each channel: a Data
Service Unit (DSU) interface, an Office Channel Unit
(OCU) interface, or a secondary-mode OCU interface
(Figure 2). A fifth 8051 processor controls the user interface and the downloading of the appropriate LeA configuration programs.
--
8-BIT SELFCENTERING FIFO
r---
-
XC3030 LCA
SERIAL-TOPARALLEL SIR
'---
8'BIT SELFCENTERING FIFO
r---------
r-- CLOCK
f-IDATA
r-- CLOCK
r-- DATA
1953 03
DSU mode block diagram
,----.
RETURN-TOZERO
GENERATOR
BIPOLAR
VIOLATION
GENERATOR
PARALLEL-TOSERIAL SIR
8051
PROCESSOR
~DATA+
~DATA-
XC3030 LCA
~
SERIAL-TOPARALLEL SIR
I+-
TRANSPARENT DATA AND
CONTROL CODE TRANSLATER
~
~DATA+
I---DATA~CLOCK
3-BIT
FIFO
1953 04
OCU mode block diagram
r---t
RETURN-TOZERO
GENERATOR
PARALLEL-TOSERIAL SIR
t
I
I
8051
PROCESSOR
I
~
FRAME BIT
GENERATOR
FRAME SYNC
RECOVERY
SERIAL-TOPARALLEL SIR
I
~
I--
I-
DATA +
DATA-
XC3030 LCA
3·BIT
FIFO
-
~I+- -
Secondary OCU block diagram
Figure 2. By reconfiguring an XC3030 LCA, each channel in a multiplexer from
Tellabs can implement any of three communication protocols.
7-26
=:
DATA +
DATACLOCK
1953 05
Reconfigurable logic can be used to adapt add-in circuit
boards to the environment of a particular computer. In
such systems, configuration programs can be downloaded by the host processor (from a floppy disk or
modem, for example), allowing simple installation procedures and easy field upgrades. Several recently announced personal computer products illustrate this capability. Buffalo Product's (Salem, OR) More Memory memory expansion card for PC/XT or PC/AT compatible systems employs a 1200-gate XC2064 LCA for the bus and
memory interface and control logic. An installation program analyzes system parameters (bus width, type of card
slot, available address spaces, etc.) and then loads the
appropriate configuration program to match the system's
requirements. Similarly, the Mach II/SE (Figure 3), an
accelerator board for the Macintosh II from Dove Computers (Wilmington, NC), uses an XC2018 LCA for all its
interface logic; different LCA configurations are used to
support different memory sizes and speeds. The
MultiScreen card from Mobius Technologies Inc.
(Oakland, CAl, a monitor interface board, includes an
XC2018 LCA for controlling the video output. Different
LCA configurations support different monitor types, allowing for variations in timing requirements and screen resolution. As new monitors are introduced in the market,
additional LCA configuration programs will be developed
and distributed on floppy disks.
Several other applications involving the use of Xilinx LeAs
to implement adaptable hardware have been described in
recent articles:
• Tektronix Inc. (Wilsonville, OR) employed an XC2018
LCA for the printer interface logic in their Phaser Card
printer controller. 1 Interfaces to several different types
of printers can be implemented through reconfiguration
of the LCA.
• The FASTPACKET data multiplexer from Stratacom
Inc. (Campbell, CAl uses LCAs to incorporate its four
serial channel interfaces. 2 Different communication
protocols can be accommodated through reconfiguration of ttie LCAs. A speCial configuration of the LCAs
also provides for bit error rate testing without the use of
external test equipment.
Reconfiguring an LCA in a graphics controller for a laser
disk system from Interactive Educational Video
(Salt Lake City, UT) allowed a single hardware design
to be matched with various video disk players' noise
characteristics. 3
GTECH Corp. (Providence, RI) designed a lottery betslip reader using LCA technology that can be reconfigured to accommodate variations in bet-slip size and
format without hardware alterations.4
Figure 3. The Dove Computer Mach IIISE includes a micro-processor, floating-point co-processor, memory, bus drivers, and an
LCA that holds all the interface logic.
7-27
Taking Advantage of Reconfigurable Lclgic
CONFIGURABLE TEST EQUIPMENT
the test patterns and the pins of the memory device being
tested. Different LCA configurations are used for testing
different types of memory devices. An extended vector
memory option uses an XC2018 LCA as a FIFO buffer
between the extended memory and the pattern control
logic. Upon command, this LCA can be reconfigured to
create a cyclic redundancy code (CRC) checker used to
verify the test patterns stored in the extended memory.
In a similar manner, programmable gate arrays often are
used to implement configurable test equipment, wherein
different LCAconfigurations are used to program the same
hardware to perform varying types of tests.
Innovage Microsystems (Calgary, Alberta) chose programmable gate arrays for test circuitry used in the Fluke
90 Series (John Fluke Mfg. Co., Everett, WA) and Innovage Microsystems' own Tracer-4 series of microprocessor board testers. These portable test instruments facilitate the trouble-shooting of microprocessor-based
boards; testers are available for a number of popular
microprocessor types (Z80, 8086, etc.). As shown in
Figure 4, an LCA provides interface and control logic
between a resident microcontroller and the unit-under-test
interface card. An 1800-gate XC2018 LCA is used in the
8-bit series, and a 2000-gate ~C3020 is used in the
16/32-bit series of testers. Different configuration programs are stored in the system's ROM during production,
dependent on the type of microprocessor targeted for that
tester, allowing the same basic hardware configuration for
all tester types. A keypad allows the user to choose from
a variety of pre-programmed trouble-shooting modes; the
microcontroller downloads one of seven different available
configuration programs to the LCA, dependent on the type
of test selected. Use of the LCA allowed Innovage
Microsystems to increase the functionality of their testers
while reducing the number of components by 49%, as
compared to previous models.
Designers of telecommunications test equipment have
also discovered the advantages of reconfigurable logic.
Three LCAs are used in the PC-based TC2000-B1
T1/PCM tester from LP Com, a Tektronix subsidiary
(Mountain View, CAl. The LCAs provide clock and timing
generationforthe receiver/transmitter, interface logic, and
bit error generation logic. The logic can be altered by
downloading different LCA configuration programs to
support several user-selected operating modes. When
analyzing DS1 lines, any standard framing mode can be
selected (D1 D, D2, D3/4, or ESF). In DS1 bit error testing
(BERT) mode, any AT&T standard or user-defined test bit
pattern can be specified. The use of reconfigurable LCAs
allowed the logic to be packed into just two boards; LP
Com engineers estimate that the design would be at least
twice as complex with traditional logic devices.
Sage Instruments (Freedom, CAl used a similar strategy
in their Model 930A Communication Test Set, a general
purpose channel access test system. Four LCAs are used
to implement data interface, channel signalling, diagnostic, and microprocessor interface functions, respectively.
The LCA that handles channel signalling has two possible
configurations to support two different signaling formats,
RBS (robbed-bit signalling) and DMI (digital multiplex
interface). The data interface and channel signalling LCAs
are both reconfigured to support bit error rate testing.
Semiconductor Test Solutions (Santa Clara, CAl included
reconfigurable logic in several optional units for their STS
6000 and 8000 series of Sentry-compatible IC testers. For
example, an optional memory test unit uses the XC2018
LCA to interface between the internal memory that holds
SYSTEM
PROCESSOR
~
XC2018
OR
XC3020
LCA
~
"-rI/
UNIT·UNDER·
TEST
INTERFACE
CARD
r-..I'-'
/!
TEST CLIP
L
'--
UNIT UNDER TEST
(ROM)
CONFIGURATION
FILE #1
II
CONFIGURATION
FILE #2
. ..
II
CONFIGURATION
FILE #7
MICROPROCESSOR BOARD TESTER
1953 06
Figure 4. In Innovage Microsystem's microprocessor board tester, an LeA is configured for the appropriate
microprocessor type and selected diagnostic test.
7-28
By reconfiguring a 3000-gate XC3030 LCA, an errorcorrection channel designed by Wiltron Co. (Morgan Hill,
CAl can support either of two error checking and correction (ECC) formats, one for Digital Data System (DDS) and
one for Adaptive Data Port (ADP) network configurations.
The circuit is incorporated into several products, including
Wiltron's Model 9966 Digital Services Test Unit for testing
DDS-like services. Use of the LCA also provides insurance
against evolving standards; new LCA configuration programs can be developed if standards for ECC formats and
network configurations change.
when writing data to the tape, and then reprogrammed to
perform a different function when reading from the tape.
Honeywell's Test Instruments Division (Denver, CO) incorporated this scheme in their VLDS (Very Large Data
Storage) recorder.5 An XC2064 LCA is configured to
perform error code generation in write mode, and then
reconfigured to perform error code checking and correction in read mode. This type of application is especially
cost-effective; about twice the logic would be required to
implement the same functions with traditional logic devices.
A similar strategy can be used in the deSign of most logic
analyzers, microprocessor in-circuit emulators, and similar test equipment. Each involves the monitoring and
control of nodes within the system being tested. In the
"acquisition mode", the target system is active and a
record of the target's activity is stored in a memory buffer
called trace memory. Trigger and breakpoint logic specifies when tracing begins and ends. A history of the system's operation can then be read from trace memory and
displayed to the user, the "analysis mode". In an LCAbased system, programmable gate arrays could be used
to implement the multiplexer, registers, and comparators
of the trigger and breakpoint logic, interface to the system
undertest, and control the writes to the trace memory while
in acquisition mode. Those same LCAs could be reconfig-
DUAL·PURPOSE HARDWARE
In the examples sited above, programmable gate arrays
are reconfigured to implement internal system diagnostics, adapt a circuit to the external environment, or completely change the functions of a system. Some logic
designers have taken this concept one step furtherprogrammable gate arrays are reconfigured as part ofthe
normal operation 01 the system.
For example, at any given time, a tape recorder can either
read or write, but it never does both simultaneously.
Consequently, a programmable gate array within a digital
tape recorder could be configured to perform one function
ADDRESS
"-
DATA
DATA
:
SYSTEM
UNDER
TEST
INPUT
CAPTURE
LOGIC
TRIGGER
AND
BREAKPOINT
LOGIC
CONTROL
MEMORY
ADDRESS
GENERATION
+
CONTROL
"
v
TRACE
MEMORY
CONTROL
/1
/1
PGA
CONTROL
"
CONTROLLER
~
ACQUISITION MODE
ADDRESS
DATA
DATA
/1
v
USER
INTERFACE
CONTROL
SYSTEM
UNDER
TEST
PGA
CONTROL
MEMORY
ADDRESS
GENERATION
+
CONTROL
CONTROL ..I\.,
"
CONTROL
CONTROLLER
"
1953 07
TRACE
MEMORY
'I
v
ANALYSIS MODE
Figure 5. An LeA can be reconfigured to support both acquisition mode and analysis mode operations in a logic analyzer.
7-29
II
Taking Advantage of Reconfigurable Logic
ured to control reading trace memory and displaying its
contents when in the analysis mode (Figure 5). For example, Data I/O's MESA-1, an in-circuit verifier for LCA
designs, uses LCAs exclusively to implement its logic
(Figure 6).
RECONFIGURABLE LOGIC EASES DESIGN
While not every system requires reconfigurable logic to
implement its digital functions, the design-related benefits
of static-memory-based programmable logiC apply to all
deSigns. The ability to reconfigure programmable gate
arrays resident in the target system significantly eases the
debugging process, reducing overall development time
and shortening the product's time-to-market. A download
cable provided with the basic development system allows
configuration programs to be downloaded directly from a
PC to an LCA device resident in the target system; the
actual download operation requires less than 1 00 milliseconds. Thus, the designer can immediately check the
results of design changes in the target system. Often,
design changes can be implemented and tested in just a
few minutes time.
'
Intel's Development Tools Operation (Hillsboro, OR) used
a slightly different tactic when designing a series of incircuit emulators for derivatives of the 80386 processor.
The emulators contain six LCAs. Four of them comprise
the bus event recognition circuitry used to define and
detect triggers and breakpoints; three of these are largely
filled with comparators, and the fourth holds the breakpoint
state machine. When preparing for an emulation, these
four LCAs can be reconfigured in the system, dependent
on the type of breakpoints and triggers being specified. A
DMA channel is used to download the LCA configuration
programs. A fifth LCA holds the bus interface state machines; as a future product upgrade, Intel deSigners may
generate another optional configuration program for that
LCA to add additional tracing capabilities.
In essence, Xilinx programmable gate arrays provide a
flexible means of "breadboarding" logic designs, as well as
a cost-effective means of implementing the logic in the
final product. Temporary modifications to the logic, such
as routing an internal node to an otherwise unused I/O pad,
can be quickly implemented for debugging purposes and
then removed from the production design. Devices are
reusable simply by downloading a new configuration.
There is no lengthy wait for a custom device to be manufactured, and no waste of components as with one-time-
THE ULTIMATE RECONFIGURABLE SYSTEM
A system composed entirely of programmable gate arrays
could be configured to implement any given logic functions. This concept has been incorporated into a new ASIC
design tool that provides real-time in-circuit emulation of
complex ASIC designs. The RPM Emulation System, from
Quickturn Systems Inc. (Mountain View, CAl, is a workstation-based design verification tool that combines automatic ASIC netlist conversion software with emulation
hardware based on 9000-gate XC3090 LCAs (See
Figure 6). The RPM Emulation System can be configured
with up to four emulation modules with over thirty XC3090
LCAs each, allowing emulation of ASIC designs of up to
100,000 gates. Once the ASIC design is converted for
emulation, existing complex VLSI devices may be
internally connected to the emulation logic with
Component Adapter boards, orthe design may be plugged
into a target system with an In-Circuit Interface consisting
of cables, an active Pod, and ASIC Plug Adapters. The
netlist conversion software reads the netlist (a variety of
popular formats and libraries are supported), partitions the
design for programming each XC3090 LCA, places and
routes the design into the matrix of XC3090 LCAs, and
checks the timing to determine the maximum speed of
correct functional operation. The Control Panel user
interface on the workstation guides the designer through
the emulation set-up and provides the controls for the
integral Logic Analyzer and Stimulus Generator, allowing
quick access to any node in the design during debugging.
Thus, using the RPM Emulation System, a designer can
emulate and debug the logiC operation of any large digital
design before committing to a custom implementation.
Figure 6. The internal logic of Data 110's MESA-1 in-circuit
debugger is implemented entirely in Xilinx programmable
gate arrays.
7-30
programmable solutions; there is not even the inconvenience of long erase times using ultraviolet lights, as with
EPROM-based logic. The designer receives nearly instantaneous feedback on the effects of design modifications.
Furthermore, since the LCA's configuration can be verified
in the target system, extensive simulation is not required;
typically, simulation is used only for critical timing path
analysis under worst-case conditions.
Buffalo Products' design of the More Memory board
mentioned above. During testing of the board using various manufacturers' PC clones, problems caused by incompatibilities in some PC models were corrected as they
were found through reconfiguration of the LCA device.
The ability to implement easily modifications to the logic
enables and encourages experimentation during the
design cycle, resulting in better designs. For example, the
use of Xilinx LCAs allowed GTECH Corp. to evaluate
different image sensors during the design of a betcslip
reader for the lottery industry.4 Since there are no standard
architectures or interfaces for image sensors, different
interface logic was required for each sensor type. By
incorporating the sensor interface logic in LCAs, a single
hardware implementation could be reconfigured for each
sensor type, allowing the sensitivity and resolution of each
to be measured under identical conditions.
Similarly, field upgrades can be easily implemented
through changes to LCA configuration programs.
Andromeda Systems (Canoga Park, CAl took full
advantage ofthis capability in their Storage Module Device
Controller, a disk controller for LSI-11 and MicrolVAX
systems. 8 The configuration programs for three XC2064
devices are stored in EEPROM that can be altered using
a service port that connects directly to terminals or
modems. The interfaces to the disk, processor bus,
service port, and cache memory are implemented in the
LCAs (Figure 7). Modifications to the logic, such as
adjusting the caching algorithm to match the requirements
of a particular application, can be made without removing
the disk controllerfrom the system; new LCA configuration
programs can be sent to the controller us.ing a modem.
FIELD UPGRADES SIMPLIFIED
The flexibility of in-circuit reconfiguration greatly reduces
design risks. The inevitable last-minute bug fixes and
specification changes can be implemented by changing
an LCA's configuration program rather than altering the
hardware. MIA-Com Telecommunications (Germantown,
MD), for example, was able to correct an error in the PCB
layout without changing the board by reconfiguring an LCA
used to implement the channel interface logic within a
satellite earthstation. 7 This flexibility proved critical during
In many cases, compatible programmable gate arrays
with a range of densities are available in identical packages. (For example, the 2000-gate XC3020, 3000-gate
XC3030, and 4200-gate XC3042 are all available in 84-pin
PLCC and PGA packages.) So if logic needs exceed the
current LCA device, during either initial design or a product
CACHE MEMORY
1M BYTE DRAM
PERIPHERAL
EXPANSION
PORT
CACHE
ADDRESS
MAPPER
Q-BUS
INTERFACE
SMD
INTERFACE
II
65C802 MICROPROCESSOR
STATIC
RAM
EEPROM
1953 08
Figure 7_ In Andromeda Systems' SMDG disk controller, LGA configurations can be
downloaded to EEPROM through a modem port for easy field upgrades.
7-31
USER
SERVICE
PORT
Taking Advantage of Reconfigurable Logic
upgrade (due to the addition of new product features, for
example), a higher-density device can be placed in the
same PCB location, with no modifications required to the
circuit board.
The reconfigurable nature of the programmable gate array
also allows for the design of its own in-circuit debugging
tools, such as Xilinx's XACTOR and Data I/O's MESA-1
(Figure 8).9 Similar in many ways to microprocessor incircuit emulators, these sophisticated verification tools
provide for easy, fast debugging and testing. Since configuration programs can be downloaded into an LCA at will,
LCA devices in the target system can be replaced or
functionally duplicated by an LCA device in an in-circuit
debugger; LCA activity can then be controlled and monitored by the user.
SUMMARY
The advent of programmable logic that can be reconfigured while resident in a system has freed the designer from
the "hard" nature of traditional logic ICs. With programmable gate arrays, adaptable systems that adjust to
changing environments or varying tasks can be created,
and hardware design is simplified. New system architectures that take advantage of reconfigurable logic will
continue to emerge as programmable gate array densities
and performance levels continue to increase.
REFERENCES
1. Loring Wirbel, ''Tek Takes Color Printer to the Office,"
Electronic Engineering Times, Nov. 14, 1988.
2. David Smith, "User-Programmable Chips Take on a
Broader Range of Applications," VLSI Systems Design,
July, 1988.
3. Rusty Woodbury, "LeA Stars in Video," ESD: The
Electronic System Design Magazine, Feb., 1987.
4. Cliff Dutton, "Programmable Logic Betters the Odds for
Bet-Slip Readers," ESD: The Electronic System Design
Magazine, Oct., 1987.
5. Tom Liehe, ''Two, Two, Two Chips in One," Electronic
Engineering Times, Nov. 17, 1986.
6. Loring Wirbel, "Quickturn Offers ASIC Emulator," Electronic Engineering Times, Nov. 14, 1988.
7. Dave Farrow, "Using Programmable Logic Cell Arrays
in a Satellite Earthstation," VLSI Systems Design, April,
1987.
8. Jim Reynolds, "Building Tomorrow's Disk Controller
Today," Electronic Products, Dec. 15, 1987.
9. John Novellino, "Development Tool Trouble-Shoots
PGAs in the Target System," Electronic Design, Jan. 26,
1989.
Figure 8. The reconfigurability of LeAs allows for the design
of their own in-circuit verification tools, such as the MESA-1
from Data 110.
TECHOOC 1953
7-32
SECTIONS
Index
1
Programmable Gate Arrays
2
Product Specifications
3
Quality, Testing, Packaging
4
Technical Support
5
Development Systems
6
Applications
7
Article Reprints
8
Index
Index
Index ................................................................................................... 8-1
Sales Office Listing ............................................................................. 8-3
1962
Index
abort .............................................................. 2-15, 2-67
DRAM controller ..................................................... 6-61
accumulator ........................................................... 6-26
EditNet ............................................................ 2-7,2-60
adder ...................................................................... 6-22
electrostatic discharge ............................................. 3-8
alpha particle ............................................................ 3-8
error correction .............................................. 6-61, 7-19
ASIC ........................................ ;................................ 1-9
FIFO ....................................................................... 6-50
Automatic Place & Route ....................................... 5-17
flat pack .................................................................. 3-18
bar code reader ...................................................... 6-59
frequency comparator ............................................ 6-41
barrel shifter ........................................................... 6-23
frequency counter ........................ 6-38, 6-41,6-42,6-44
battery back-up ............................................. 6-22, 2-27
FutureNet ............................................................... 5-38
BIOI ..... ,........................................................... 2-60, 2-7
in-circuit verification ............................................... 5-36
Boolean equations .......................................... 5-35, 6-7
initialization ................................................... 2-14, 2-66
buffers .................................................................... 2-10
input ............................................................... (see lOB)
bulletin board .................................................... 3-1.4-4
input protection ............................................... 2-27.3-8
burn-in .................................................................. 2-100
interconnect .................................. 2-7, 2-13. 2-59.2-60
busing .....................................................................2-11
lOB ........................................................ 2-3, 2-56, 6-14
carry generate, carry propagate ............................. 6-26
lOB timing ............................................ 2-42, 2-86,6-14
CLB ................................................................. 2-5, 2-57
latches .................................................................... 6-31
CLB timing ........................................... 2-40, 2-84, 6-16
latch-Up ..................................................................... 3-9
code conversion .............................................. ,...... 6-46
length count .................................................. 2~17,2-67
combinatorial functions ................................... 2-6, 2-58
library ..................................................................... 5-25
comparator ............................................................. 6-27
logic analyzer ......................................................... 6-67
conf.iguration ................................................. 2,14, 2-66
logic synthesis ......... ;.................................... 5-13, 5-34
configuration data .................................................. 2-16
long lines ....................................................... 2-11, 2-60
configuration memory ..................... 2-2, 2-55, 3-7. 3-11
macros ................................................... ;............... 5-25
configuration pins ................................................... 2-32
magic box ....................................................... 2-9, 2-60
cost .......................................................................... 1-9
majority logic .......................................................... 6-.24
counters ........................... 6-32-6-38, 6-41, 6-42. 6-44
MAKEBITS .................................................... 2-17, 5-21
crystal oscillator ............................................ 2-13. 2-62
MAKEPROM ................................................. 2-17.5-21
Daisy ................................................................. :.... 5-40
master mode timing ...................................... 2-45, 2-88
daisy chain ............................................................. 2-20
master parallel mode .................. 2-14.2-19,2-66,2-68
design considerations ............................................ 6-12
master serial mode .......... 2-14, 2-18.2"66,2-69.2-141
diagnostic ............................................................... 6-54
memory cell ..................................... 2-2, 2-55. 3-7, 3-11
direct inputs ............................................................ 2-1 0
memory requirements .............................................. 5,1
disk controller .........................................................;. 7-1
Mentor .................................................................... 5-42
DON E ............................................................ 2-23,2-72
metastability ........................................................... 6-20
download ............................................................ ,... 5-21
Micro Channel ........................................................ 6-57
8-1
III
Index
MIL-STD-883 ........................................................... 3-1
reliability ................................................................... 3-1
military .................................................................... 2-95
RESET ....................................... 2-15, 2-23, 2-67, 6-14
minimum specifications .......................................... 6-18
retention ................................................................. 2-27
modes ........................................................... 2-14, 2-66
Schema 11 ............................................................... 5-39
multiplexer ..................................................... 2-12, 6-23
schematic capture ......................................... 5-1 0, 5-37
OrCAD ................................................................... 5-43
self test ................................................................... 6-54
ordering information .......................... 2-29, 2-91,2-152,
serial PROM ............................................. 2-139, 2-150
5-47,5-49
SILOS ...........................................................5-21, 5-33
oscillator ..................................... 2-13, 2-23, 2-62, 6-15
simulation ............................................................... 5-21
output ............................................................. (see lOB)
sizing ........................................................................ 6-3
output inversion ........................................................ 2-4
slave mode ................................. 2-14, 2-20, 2-66, 2-71
output slew rate ........................................................ 2-3
slave mode timing ......................................... 2-47, 2-90
package dimensions ..................................... 2-50, 2-92
package pins .......................................................... 2-33
sockets ................................................................. 2-151
packages ..................... 2-49, 2-101, 2-114, 2-128, 3-17
specifications ................................................ 2-37, 2-82
PALASM ....................................................... 5-13, 5-34
start-up ................................................... ,...... 2-17, 6-19
part numbers .......................................................... 2-49
state machine ................................................ 6-52, 6-53
pattern detector ..... ................................................. 6-45
subtractor ............................................................... 6-26
PC requirements ...................................................... 5-1
supply voltage ............................................... 2-26, 2-76
PC-SILOS .............................................................. 5-33
switch matrix ................................................... 2-9, 2-60
PDS2XNF .............................................................. 5-34
performance ........................................ 2-24, 2-74,6-16
T1Interface ............................................................ 7-17
peripheral mode .......................... 2-14, 2-20, 2-66, 2-70
peripheral mode timing ................................. 2-47, 2-89
testing .................................................................... 3-11
three-state buffers .................................................. 2-12
phase comparator .................................................. 6-41
threshold ....................................................... 2-15, 2-71
pin description ................................... 2-30, 2-78, 2-140
tie option ................................................................ 2-17
pinouts .......................................................... 2-80, 2-33
timing ................................................... 2-40, 2-84, 6-16
PIP .................................................................. 2-8, 2-60
timing calculator .......... ........................................... 2-24
power dissipation .............. 2-26, 2-28, 2-64, 2-77, 6-16
timing, CLB ................................................... 2-25, 2-84
power distribution .......................................... 2-24, 2-64
timing, interconnect ....................................... 2-26, 2-75
power-down ......................................... 2-15, 2-27, 2-72
timing, lOB .................................................... 2-25, 2-86
power-on ....................................................... 2-15, 2-67
timing, PROM ....................................................... 2-145
preamble ....................................................... 2-15, 2-67
toggle frequency ........................................... 2-72, 2-23
prescaler ................... ............................................. 6-42
training course ......................................................... 4-7
process .................................................................. 1-14
TIL - MSllibrary .................................................... 5-44
soft errors ................................................................. 3-8
temperature ........................................... 2-26, 2-76, 3-9
PROM programmer ................................................ 5-46
video control ........................................................... 7-22
PROM programming ............................................ 2-142
wired-AND .............................................................. 2-12
quality ....................................................................... 3-1
XACT Design Editor ...................................... 5-19, 5-32
radiation ................................................................. 3-10
XACTOR ................................................................ 5-36
re-program .................................................... 2-23, 2-72
XNF2LCA ............................................................... 5-16
readback ....................................................... 2-22, 2-72
XNFMERGE .................................................. 5-17, 5-34
readback timing ............................................. 2-47, 2-90
XNFOPT ....................................................... 5-16, 5-34
reconfigure ............................................................. 7-19
8-2
Sales
Offices
SALES OFFICES
DOMESTIC SALES
CONNECTICUT
INDIANA
MASSACHUSETTS
EUROPE
ALABAMA
XILlNX, Ltd.
Station House
Bepton Road, Midhurst
Sussex GU 299RE
England
Tel: 0730816725
FAX: 073081 4910
Technology Marketing
Associates, Inc.
3315 So. Memorial Pkwy.
Suite 5
Huntsville, AL 35801
(205) 883-7893
FAX: 205-882-6162
Lindco Associates, Inc.
Cornerstone
Professional Park
Suite C-l0l
Woodbury CT, 06798
(203) 266-0728
FAX: 203-266-0784
Arete Sales Inc.
2260 Lake Ave Suite 250
Fort Wayne, IN 46805
(219) 423-1478
FAX: 219-420-1440
Mill-Bern Associates, Inc.
2 Mack Road
Woburn, MA 01801
(617) 932-3311
TWX: 710-332-0077
FAX: 617-932-0511
JAPAN
ARIZONA
XILINX K. K.
Kybashi No.8
Nagaoka Bldg. 8F
20-9 Hatchobori Nichome
Chuo-ku, Tokyo 104, Japan
Tel: 03-297-9191
FAX: 03-297-9189
Ouatra Associates
4645 S. Lakeshore Dr.,
Suite 1
Tempe, AZ 85282
(602) 820-7050
TWX: 910-950-1153
FAX: 602-820-7054
ARKANSAS
NORTH AMERICA
Bonser-Philhower Sales
4614 S. Knoxville Avenue
Tulsa, OK 74135
(918) 744-9964
TWX: 510-600-5274
XILlNX, INC.
2100 Logic Drive
San Jose, CA 95124
(408) 559-7778
TWX: 510-600-8750
FAX: 408-559-7114
CALIFORNIA
XILlNX, INC.
1270 Oakmead Parkway
Suite 201
Sunnyvale, CA 94086
(408) 245-1361
FAX: 408-245-0517
SC Cubed
468 Pennsfield Place
Suite lOlA
Thousand Oaks, CA 91360
(805) 496-7307
FAX: 805-495-3601
XILlNX, INC.
2659 Townsgate Road
Suite 101
Westlake Village, CA 91361
(805) 494-5026
FAX: 805-496-0239
SC Cubed
1786217th. SI. #207
Tustin, CA 92680
(714) 731-9206
FAX: 714-731-7801
XILlNX, INC.
61 Spit Brook Rd.
Suite 403
Nashua, NH 03060
(603) 891-1096
FAX: 603-891-0890
Ouest-Rep Inc.
9444 Farnham SI., Suite 107
San Diego, CA 92123
(619) 565-8797
FAX: 619-565-8990
Norcomp
3350 Scott Blvd., Suite 24
Santa Clara, CA 95054
(408) 727-7707
TWX: 510-600-1477
FAX: 408-986-1947
XILlNX, INC.
65 Valley Stream Parkway
Suite 140
Malvem, PA 19355
(215) 296-8302
FAX: 215-296-8378
COLORADO
XILlNX, INC.
919 North Plum Grove Road
Suite A
Schaumburg, IL 60173
(312) 605-1972
TLX: 510-601-5973
FAX: 312-605-1985
Front Range Marketing
3100 Arapahoe Rd"
Suite 404
Boulder, CO 80303
(303) 443-4780
TWX: 910-940-3442
FAX: 303-447-0371
DELAWARE
Micro Comp, Inc.
1421 S. Caton Avenue
Baltimore, MD 21227
(301) 644-5700
TWX: 510-600-9460
FAX: 301-644-5707
FLORIDA
Technology Marketing
Associates, Inc.
8000 Orange Ave., Suite 111
Orlando, FL 32809
(407) 857-3760
TWX: 510-600-4721
FAX: 407-857-6412
Technology Marketing
Associates, Inc.
1239 E. Newport Center Dr.,
Suite 107
Deerfield Beach, Fl33442
(305) 427-1090
FAX: 305-427-1626
Technology Marketing
Associates, Inc.
1110066 SI. No., Suite 25
Largo, FL 34643
(813) 541-1591
FAX: 813-545-8617
GEORGIA
Technology Marketing
Associates, Inc.
6655 Jimmy Carter Boulevard
Suite 2420
Norcross, GA 30071
(404) 446-3565
FAX: 404-446-0569
IDAHO (Southwest)
Thorson Company Northwest
12301 N.E. 10th Place
Bellevue, WA 98005
(206) 455-9180
ILLINOIS
Beta Technology Sales, Inc.
1009 Hawthorne Drive
Itasca, IL 60143
(312) 250-9586
TWX: 62865853
FAX: (312) 250-9592
8-3
Arete Sales Inc.
918 Fry Road Suite B
Greenwood,lN 46142
(317) 882-4407
FAX: 317-888-8416
IOWA
Advanced Technical Sales
375 Collins Road N.E.
Cedar Rapids, IA 52402
(319) 393-8280
FAX: 319-393-7258
KANSAS
Advanced Technical Sales
610 N. Mur-Len, Suite 8
Olathe, KS 66062
(913) 782-8702
FAX: 913-782-8641
TWX: 910-350-6002
LOUISIANA (Northern)
Bonser-Philhower Sales
689 W. Renner Rd., Suite III
Richardson, TX 75060
(214) 234-8438
TWX: 910-867-4752
FAX: 214-437-0897
LOUISIANA (Southern)
Bonser-Philhower Sale.s
10700 Richmond, Suite 150
Houston, TX 77042
(713) 782-4144
TWX: 910-350-3451
MAINE
Mill-Bern Associates, Inc.
2 Mac Road
Woburn, MA 01801
(617) 932-3311
TWX: 710-332-0077
FAX: 617-932-0511
MARYLAND
Micro Comp, Inc.
1421 S. Caton Avenue
Baltimore, MD 21227-1082
(301) 644-5700
TWX: 510-600-9460
FAX: 301-644-5707
MICHIGAN
A. P. Associates
810 E. Grand River
Brighton, MI48116
(313) 229-6550
TWX: 816-287-310
FAX: 313-229-9356
MINNESOTA
Com-Tek
6525 City West Parkway
Eden Prairie, MN 55344
(612) 941-7181
TWX: 310-431-0122
FAX: 612-941-4322
MISSOURI
Advanced Technical Sales
1810 Craig Road, Suite 213
SI. Louis, MO 36146
(314) 878-2921
FAX: 314-878-1994
NEVADA
Norcomp
(Excluding Clark County)
3350 Scott Blvd., Suite 24
Santa Clara, CA 95054
(408) 727-7707
TWX: 510-600-1477
Quatra Associates
(Clark County)
4645 S. Lakeshore Dr.,
Suite 1
Tempe, AZ 85282
(602) 820-7050
FAX: 602-820-7054
NEW HAMPSHIRE
Mill-Bern Associates, Inc.
2 Mack Road
Woburn, MA 01801
(617) 932-3311
TWX: 710-332-0077
FAX: 617-932-0511
•
Sales Offices
NEW JERSEY (Northern)
OHIO
SOUTH CAROLINA
WASHINGTON
AUSTRIA
Parallax
734 Walt Whitman Road
Mellville, NY 11747
(516) 351-1000
FAX: 516-351-1606
Bear Marketing, ·Inc.
P.O. Box 427
3623 Brecksville Road
Richfield, OH 44286-0177
(216) 659·3131
FAX: 216-659-4823
TWX: 810-427-9100
The Novus Group, Inc.
5337 Trestlewood Lane
Raleigh, NC 27610
(919) 833-7771
TWX: 510~oo-OS58
FAX: 919-839-0791
Thorson Company Northwest
12340 N.E. 8th Place
Suite 201
Bellevue, WA 98005
(206) 455-9180
FAX: 206-455-9185
TWX: 910-443-2300
Eljapex Ges. m.b.h.
Eitnergasse 6
A-1232Wien
Austria
(01) 86 3211
FAX: (01) 86 3211 200
NEW JERSEY (Southern)
BELGIUM & LUXEMBURG
SOUTH DAKOTA
Delta Technical Sales, Inc.
3901 Commerce Avenue
Suite 180
Willow Grove, PA 19090
(215) 657-7250
TWX: 510-601-1856
FAX: 215-65~-378t
Bear Marketing, Inc.
240 W. Elmwood Drive
Suite 1002
Centerville, OH 45459-4248
(513) 436-2061
FAX: 513-436-9137
Com-Tek
6525 City West Parkway
Eden Prairie, MN 55344.
(612) 941-7181
TWX: 310-431-0122
FAX: 612-941-4322
OKLAHOMA
NEWMEXICQ
Quatra Associates
9704 Admiral Dewey N.E.
Albuquerque, NM 87111
(505) 821-1455
TEXAS
Bonser-Philhower Sales
2727 E. 21st Street
Suite 602
Tulsa, OK 74114
(918) 744-9964
FAX: 918-749-0497
OREGON
Bonser-Philhower Sales
8240 MoPac Expwy.,
Suite 135
Austin, TX 78759.
(512) 346-9186
TWX: 910-997-8141
FAX: 512-346-2393
Thorson Company Northwest
6700 S. W. 105th Ave.,
Suite 104
Beaverton, OR 97005
(503) 644-5900
FAX: 503-644-5919
Bonser-Philhower Sales
10700 Richmond, Suite 150
Houston, TX 77042
(713) 782-4144
TWX: 910-350·3451
FAX: 713-789-3072
PENNSYLVANIA (Eastern)
Bonser-Philhower SaI!!S
689 W. Renner Rd., Suite 101
Richardson, TX 75080
(214) 234-8438
TWX: 910-867-4752
FAX: 214-437-0897
NEW YORK (Metro)
Parallax
734 Walt Whitman Road
Mellville, NY 11747
(516) 351-1000
FAX: 516-351-1606
NEW YORK
Gen-Tech Electronics
4855 Executive Drive
Liverpool, NY 13088
(315) 451-3480
TWX: 710-545-0250
FAX: 315-451-0988
Gen-Tech Electronics
41 Burning Tree Lane
Rochester, NY 14526
(716) 381-5159
Gen-Tech Electronics
70 Sandoris Circle
Rochester, NY 14622
(716) 467-5016
Gen-Tech Electronics
5 Arbutus Lane
Binghampton, NY 13901
(607) 648-8833
NORTH CAROLINA
The Novus Group, Inc.
5337 T restlewoOd Lane
Raleigh, NC 27610
(919) 833-7771
TWX: 510-600-0558
FAX: 919'856-1644
NORTH DAKOTA'
Com-Tek '.
6525 City West Parkway
Eden Pmirie, MN 55344
(612) 941-7181
TwX: 310-431-0122
FAX: 612-941-4322
Delta Technical Sales, Inc.
122 New York Road
Suite 9
Hatboro, PA 19040
(215) 957-0600
FAX: 215-957-0920
PENNSYLVANIA (Western)
Bear Marketing, Inc.
300 Mt. Lebanon Blvd.
Pittsburg, PA 15234
(412)531-2002
FAX: 412-531-2008
PUERTO RICO
Mill-Bern Associates, Inc.
2 Mac Road
Woburn, MA 01801
(617) 932-3311
TWX: 710-332-0077
FAX, 617-~32-0511
Technology Marketillg
Associates, Inc.
1280 S. W. 36ih Ave.,
Suite 201
Pompano Beach, FL 33069
(305) 977-9006
TWX: 510-601-0120
FAX: 305-Q77-9044
RHODE ISLAND
Mill-Bern Associales, Inc.
2 Mack Road
Woburn, MA01801
(617) 932-3311
TWX: 710-332-0077
FAX: 617-932-0511
TEXAS (EI Paso County)
Quatra Associates
9704 Admiral Dewey N.E.
Albuquerque, NM 87111
(505)821-1455
UTAH
Front Range Marketing
7050 Union Park Center
Suite 440
Midvale, UT 84047
(801) 566-2500
FAX: 801-566-2951
VERMONT
WASHINGTON
(Vancouver, WA only)
Thorson Company Northwest
6700 S.W. 105th Ave.,
Suite 104
Beaverton, OJl.97005
(503) 644-5900
FAX: 503-644-6919
WASHINGTON D.C.
Micro Comp, Inc.
1421 S. Caton Avenue
Baltimore, MD 21227
(301) 644-5700
TWX: 510-600-9460
FAX: 301-644-5707.
WEST VIRGINA
Bear Marketing, Inc.
1563 East Dorothy Lane
Suite 104
Kettering, OH 45429
(513) 299-5877
FAX: 513-299-0756
WISCONSINIWestern)
Com-Tek
6525 City West Parkway
Eden Prairie, MN 55344
(612) 941-7181
TWX: 310-431-0t22
FAX: 612-941-4322
WISCONSIN (Eastern)
Beta Technology Sales, Inc.
9401 Beloit, Suite 304C
Milwaukee, WI 53227
(414) 543-6609
VIRGINA
Micro Comp, Inc.
1421 S. Caton Avenue
Baltimore, MD 21227
(301) 644-5700
TWX: 510-600-9460
FAX: 301·644-5707
8-4
BRAZIL
Intemational Trade
Development Corporation
450 San Antonio Road
Suite 32
Palo Alto, CA 94306
(415) 856-8686
Telex: 650-282-9742
CANADA
BRITISH COLUMBIA
(Vancouver)
.Thorson Company Northwest
12301 N.E.l0th Place
Bellevue, WA 98005
(206) 455-9180
ONTARIO
Electro Source, Inc.
320 March Road, Suite 500
Kanata, Ontario K2K 2E3
(613) 592-3214
FAX: 613-592-4256
Electro Source, Inc.
230 Galaxy Boulevard
Rexdale, Ontario M9W 5R8
(416) 675-4490
TWX: 06-989271
FAX: 416-675-6871
QUEBEC
INTERNATIONAL
SALES
AUSTRALIA
Mill-Bern Associates; Inc.
2 Mac Road
Woburn, MA 01801
(617) 932-3311
TWX, 710-332-0071
FAX: 617-932-0511
Le Mar Rodelco
Limburg Stirum 243
1810Wemmel
Belgium
(02) 460-0560
FAX: (02) 460-0271
ACDIITRONICS
106 Belmore Rd. Noith
Riverwood, N.S.W; 2210
Tel: Sydney 534-6200 .
FAX: Sydney 5:\4-4910
ACD/ITRONICS
Uni12, 17-1.9 Melrich Road
Beyswater VIC 3153 '
P.O. Box 139
Tel: Melbourne (03) 762 7644
Fax: Melbourne (03)762 5446
ACD1ITRONICS
55 Noreen Street
Chapel Hill OLD 4069
Tel: OLD 8781488
Fax: OLD 878 1490
Electro Source
6600 TransCanada Hwy
Suite 420 Point Claire
Quebec H9R 4S2
(514) 630-7486
FAX: 514-630-7421
DENMARK
Dana"ech KS .
POBox 1361
Smedeland 8
?SOOGlostrup
Denmark
Tel: (02) 4345 47
FAX: (02) 4345 67
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FINLAND
GERMANY
ISRAEL
KOREA
SWEDEN
OY SW-Instruments AB
Ala Portti IC
SF-02210 Espoo, Finland
Tel: (08) 4110 41
FAX: (08) 0319 55
Metronik
Leonhardsweg 2
Postfach 13 28
8025 Unterhaching
Munch en, Germany
Tel: (089) 611080
TLX: 897434
FAX: (089) 611 6468
E.I.M International Ltd.
8, Emil Zola Street
P.O. Box 4000
Petach Tiqva
Tel Aviv, Israel
Tel: (3) 92 33257
FAX: (3) 924 4857
TLX: 381144 E.I.M.I.L.
Excel-Tech
410-5 Hapjeong-Dong
Mapo-Gu
Seoul, Korea
Tel: 82-2-3357823
FAX: 82-2-3357825
D.I.P. Electronics AS
P.O. Box 15046
S-104 65 Stockholm, Sweden
Tel: (08) 44 91 90
FAX: (08) 43 00 47
Metronik
Semerteichstrasse 92
4600 Dortmund 30
Dortmund, Germany
Tel: (0231) 423037/38
TLX: 8227082
ITALY
FRANCE
Reptronic
11, Escalier des Ulis
91400 Orsay, France
Tel: (16) 928 8700
FAX: (16) 928 1750
R.T.F. Gentilly
9, rue d'Arcueil
94253 Gentilly Cedex,
France
Tel:(16)46641110
TLX: 2010169F
FAX: (16) 4 66 4419 9
R.T.F. (Radio Television
Francaise SA)
13, rue Lhote
33000 Bordeaux. France
Tel: 56 52 9959
TLX: 560827
FAX: 56 4817 83
R.T.F. Ouest
3, rue de Paris
35510 Cesson Sevigne,
France
Tel: 99 83 64 85
TLX: 741127
FAX: 99 83 8Q 83
R.T.F. Sud Ouest
Avenue de la Mairie
31320 Escalquens, France
Tel: 61 81 51 57
TLX: 520927F
FAX: 61 81 2236
Metronik
Osterbrooksweg 61
2000 Schenefeld
Hamburg, Germany
Tel: (040) 8304061
TLX: 2162488
Metronik
Siemensstrasse 4-6
6805 Heddesheim
Mannheim. Germany
Tel: (06203) 4701-03
TLX: 465053
Metronik
Laufamholzstr. 118
8500 NQrnberg 30
NOrnberg, Germany
Tel: (0911) 590061162
TLX: 626205
Metronik
LOwenstr. 37
7000 Stuttgart 70
Stuttgart, Germany
Tel: (0711) 764033135
TLX: 7255228
HONG KONG
R.T.F. Rhone Alpes
SI. Mury, Le Vaucanson
38240 Maylan, France
Tel: 7690 1188
TLX: 980796
FAX: 76 410409
Excel Associates, Ltd.
1502 Austin Tower
22-26A Austin Avenue
Tsimshatsui, Kowloon
Hong Kong
Tel: 3-7210900
FAX: 3-696826
TLX: 30841
ACSIS S.R.L.
Via Alberto Mario. 26
20149 Milano, Italy
Tel: (02) 4390832
TLX: 326566
FAX: (02) 4697607
Celdis Italiana S.PA
ViaF.i1l Gracchi 36
20092 Ciniselio Balsamo
Milano, Italy
Tel: (02) 61 8391
TLX: 334887
FAX: (02) 61 73513
Celdis Italiana S.P.A.
Via Massarenti 219/4
40138 Bologna, Italy
Tel: (051) 533336
Celdis Italiana S.PA
Via Savelli 15
35100 Padova, Italy
Tel: (049) 77 209 9
Celdis Italiana S.PA
ViaG. Pitre' 11
00162 Roma, Italy
Tel: (06) 42 897 1
Celdis Italiana S.PA
Via Mombarcaro 96
10136 Torino, Italy
Tel: (011) 3299388
JAPAN
Okura &Co., Ltd.
6-12, Ginza Nichome
Chuo-Ku
Tokyo, 104 Japan
Tel: (03) 5666361
TWX:J22306
FAX: (03) 563 5447
SWITZERLAND
Shinhwa Corp.
Room 902, Bang-hyoup Bldg.
43-8 Kwanchul-Dong
Chongro-ku
Seoul, Korea
THE NETHERLANDS
Rodelco BV Electronics
Takkebijsters 2
P.O. Box 6824
4802 HV Breda
Netherlands
Tel: (076) 784911
TLX: 54195
FAX: (076) 710029
NORWAY
B.I.T. Elektronikk AS
P.O. Box 36 Lerbyen
N-3401 Lier, Norway
Tel: (03) 847099
FAX: (03) 84 55 10
Data Comp AG
Silbernstrasse 10
CH-8953 Dietikon
Switzerland
Tel: (01) 7405140
Telex: 827750
FAX: (01) 7413423
TAIWAN
Molecatex, Inc.
21F 258 Sec3
Nankin9 East Road
Taipei, Taiwan R.O.C.
Tel: (02) 7410400
FAX: (02) 7217461
TLX: 29214 MTEX
Jeritron Ltd.
5/F Fu San Building
1182 Cheng-Teh Road
Taipei, Taiwan. R.O.C.
Tel: (02) 8823154
FAX: (02) 8820710
SINGAPORE
Excel Associates Ltd.
Singapore Representative
Office
111 North Bridge Road
#11-04/06 Peninsula Plaza
Singapore 0617
Tel: 3366577
FAX: 3395291
Telex: RS 36033 WWBCS
SOUTHEAST ASIA
Excel Associates, Ltd.
1502 Austin Tower
22-26A Austin Avenue
Tsimshatsui, Kowloon
Hong Kong
Tel: 852-3-7210900
FAX: 852-3-696826
TLX:30841
SPAIN
ADM Electronica SA
Menorea No.3 Entreplanta
Madrid 28009
Spain
Tel: (01) 409 4725
FAX: (01) 409 5215
Sertek Int'I Inc.
15/F, 135 Sec 2
Chien Kuo N. Road
Taipei 10479
Taiwan R.O.C.
Tel: 2 501 0055
Fax: 2501 2521
Telex: 23756 Sertek
UK AND IRELAND
Microcali, Ltd.
17 Thame Park Road
Thame
Oxon OX9 3XD
England
Tel: (084) 421 5405
TLX: 837457
FAX: (084) 421 4267
Microcali, L,t9..
The Genesis Centre
Birchwood Science Park
Garrett Field
Warrington WA3 7BN
England
Tel: (0925) 825065
Distributed By
Hamiiton/Avnet
locations throughout
the U.S. and Canada.
1-800-HAM-ASIC
FAX: 408-743-3003
Western Microtechnology
12900 Saratoga Ave.
Saratoga, CA 95070
(408) 725-1660
TWX: 91 0-338-0013
FAX: 408-255-6491
Insight Electronics
6885 Flanders Drive
San Diego, CA 92121
(619) 587-9757
TWX: 183035-UD
FAX: 619-587-1380
Marshall Industries
locations throughout
the U.S. and Canada.
(818) 459-5500
FAX: 818-459-5660
Phase 1 Technology
Corporation
1110 Rte. 109
N. Lindenhurst, NY 11757
(516) 957-4900
FAX: 516-957-4909
Nu Horizons
Electronics Corp.
6000 New Horizons Blvd.
Amityvilie, New York 11701
(516) 226-6000
FAX: 516-226-6262
16738
8-5
II
•
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The Programmable Gate Array Company
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The Programmable Gate Array Company
NO POSTAGE
NECESSARY
IF MAILED
IN THE
UNITED STATES
BUSINESS REPLY MAIL
FIRST CLASS
PERMIT NO. 8051
SAN JOSE, CA
POSTAGE PAID BY ADDRESSEE
XlLINX
2100 Logic Drive
San]ose, CA 95124-9920
Ii
Ii
Ii
1111 I III III I III 1111111111111111111111111111 III
I
BUSINESS REPLY MAIL
FIRST CLASS
PERMIT NO. 8051
SAN JOSE, CA
POSTAGE PAID BY ADDRESSEE
XILINX
2100 Logic Drive
San]ose, CA 95124-9920
Ii Ii
Ii
II 1111 11111111111.1111111111 111111111111111111
NO POSTAGE
NECESSARY
IF MAILED
IN THE
UNITED STATES
~ XILINX
The Programmable Gate Array Company.
2100 Logic Drive, San Jose, CA 95124.
Easyunk 62916309 TWX: 5106008750 X1UNX UQ FAX: (408) 559-7114
<01989 XIUNX, In
PIN 0010048 02
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