1990_AMI_Products_Catalog 1990 AMI Products Catalog
1990_AMI_Products_Catalog 1990_AMI_Products_Catalog
User Manual: 1990_AMI_Products_Catalog
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1990 Products
Catalog
Gould AMI
2300 Buckskin Road
Pocatello, ID 83201
Telephone: (208) 233-4690
-} GOULD
~MII®Semiconductors
-) GOULD
AIMII®Semiconductors
Introduction
Gould AMI, a division of Gould, Inc., is headquartered in
Pocatello, Idaho and isthe semiconductor industry
leader in the design and manufacture of application
specific integrated circuits. It manufactures special circuits for leading computer manufacturers, telecommunications companies, automobile manufacturers,
consumer and military product companies worldwide.
Our E2 PLDs are desirable for lower volume production
or low gate-density requirements. Gould's HCMOS gate
arrays provide solutions for a variety of high-pertormance applications with gate-counts up to 40K. For
higher production volume requirements or mega cell implementation, Gould's standard cell and cell-based circuits are especially cost effective.
Gould AMI has always focused on customer needs. As
the original architect of Application Specific Integrated
Circuit (ASIC) technology, Gould has a rock solid foundation and knows that great service, short development
spans, good first silicon, competitive production prices,
and the highest quality product are what it takes to keep
our customers competitive. From the early days of handdrawn custom through the CAE/CAD boom, to today's
silicon compilers, Gould has been providing custom,
semicustom and standard product solutions for over 20
years, longer than any other ASIC vendor.
Along with being the leading designer of custom VLSI,
Gould is a leading innovator in combining digital and
analog circuitry on a single silicon chip, and is a recognized leader of standard products based on switched
capacitor filter technology.
While extensive quality assurance programs are utilized,
the Gould belief is that quality must be "built-in" to a
product, not "inspected-in." This is a critical element in
the philosophy of Gould AMI. Statistical Process Control
(SPC) is the tool which has been implemented
throughout the company to assure that quality products
are produced and the improvement process is on-going.
The company leads all other U.S. semiconductor
manufacturers in the implementation of SPC.
Gould brings to its customers what is known as the ASIC
continuum. This is a complete range of ASIC design
styles which will allow each of its customers to have the
optimum solution suited to his unique application. The
ASIC continuum includes: programmable logic in the
form of Electrically Erasable Programmable Logic
devices (EEPLDs), gate arrays, standard cells and cellbased custom designs supported by industry-leading
cell compilers, and silicon foundry services. Gould engineers and marketers work with each customer to
select the type of ASIC that best meets the requirements
of his system.
Gould provides components for station equipment,
PABX and Central Office Switching systems, data communications, and advanced digital signal processing
(DSP) applications.
The company also provides ROMs, ranging from 16K to
1 Meg.
Gould offers silicon foundry services including water
fabrication, assembly and final test. Originally founded
as an MOS company, Gould currently offers process
flexibility with more than 30 high-speed, low-power
CMOS processes which span 1.25-micron to the mature
5-micron processes.
Gould offers one of the broadest package selections
available in the industry. Over 250 standard packaging
alternatives, all meeting JEDEC standards, are available
to meet your individual circuit requirements.
Gould operates an assembly and test operation in
Manila, Philippines. Regional sales offices and representatives are extensive; please see listing in the last
section.
-) GOULD
AIMII®Semiconductors
Table of Contents
1. Indices
D Numerical
D Functional
2. ASIC Products
D E2 PLDs
D
D
D
D
D
Gate Arrays
Standard Cells
Cell-Based Custom
Foundry
ASIC Services
3. Communication Products
D Station Products
D Modems, Filters and PCM Products
D Digital Signal Processors and
High Performance Digital Circuits
4. Microprocessor Support Circuits
5. Display Driver Circuits
6.PLDs
7. CMOS & NMOS ROMs
8. General Information
D Quality Program
D Packaging
D Ordering Information
D Terms of Sale
D World Wide Sales Offices
D Domestic Representatives
D Domestic Distributors
o
International Representatives and Distributors
-} GOULD
AIMII®Semiconductors
Copyright © 1989 Gould AMI
(All rights reserved) Trade Marks Registered ®
Information furnished by Gould AMI in this publication is
believed to be accurate. Devices sold by Gould are
covered by the warranty and patent indemnification
provisions appearing in its Terms of Sale only. Gould
makes no warranty, express, statutory, implied, or by
description regarding the information set forth herein or
regarding the freedom of the described devices from
patent infringement. Gould makes no warranty of merchantability or fitness for any purposes. Gould reserves
the right to discontinue production and change specifications and prices at any time and without notice.
Advanced Product Description means that this
product has not been produced in volume, the specifications are preliminary and subject to change, and device
Trademarks:
Viewlogic ® is a registered trademark of Viewlogic Systems Inc.
FutureNet ® is a registered trademark of FutureNet Corporation,
a Data flO Company
SCEPTRE III is a trademark of Gould Inc., Semiconductor Division
PEEL is a trademark of International CMOS Technology, Inc.
Printed in U.S.A.
characterization has not been done. Therefore; prior to
programming or designing this product into a system, it
is necessary to check with Gould for current information.
Preliminary means that this product is in limited production, the specifications are preliminary and subject to
change. Therefore, prior to programming or designing
this product into a system, it is necessary to.check with
Gould for current information.
These products are intended for use in normal commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or high reliability application, such as military,
medical life-support or life-sustaining equipment are
specifically not recommended without additional
processing by Gould for such application.
SCORE is a 'trademark of Gould Inc., Semiconductor Division
Sentry ® is a registered trademark of Fairchild Camera and Instrument
Corporation
SCHOLAR is a trademark of Gould Inc., Semiconductor Division
NETRANS is a. trademark of Gould Inc., Semiconductor Division
GATE GOBBLER is a trademark of Gould Inc., Semiconductor Division
EXPERT ASIC is a trademark of Gould Inc., Semiconductor Division
-) GOULD
~MII®Semiconductol'S
Indices
-} GOULD
AIMll,Semiconductors
Indices
AlphalNumericallndex
Device
Page
G8 Family Gate Arrays ..... 2.5
GC Family Gate Arrays ..... 2.4
18CV8 .................. 6.3
18CV8-15 ................ 6.13
20CG10 ................. 6.16
20CV10 ................. 6.24
22CV10Z ................ 6.29
PEEL153 ................ 6.34
PEEL 173 ................ 6.39
PEEL253 ................ 6.44
PEEL273 ................ 6.49
PDS .................... 6.54
S23128 .................. 8.3
S23256 .................. 8.3
S23256 .................. 8.3
S25089 .................. 3.34
S2559E ................. 3.3
S2559F .................. 3.3
S2560A ................. 3.12
S2560G ................. 3.19
S2560G1 ................ 3.19
S2561 ................... 3.21
Device
Page
S2561A .................
S2569 ..................
S2569A .................
S2579 ..................
S35061 '" ...............
S35071 ..................
S3507AI .................
S3524A .................
S3525A .................
S35268 .................
S35288 .......•.........
S35298 .................
S3531 ..................
S3541 ..................
S3547 ..................
S35212A ................
S352128 ................
S35213 .................
S4520 ..................
S4521 ..................
S4534 ..................
S4535 ..................
1.2
3.21
3.27
3.27
3.40
3.154
3.154
3.154
3.118
3.121
3.128
3.135
3.145
3.103
3.170
3.171
3.78
3.84
3.91
5.3
5.11
5.14
5.17
Device
Page
S61 C35 ................. 3.202
S61C337 ................ 3.221
S614381 ................ 3.197
S618839 ................ 3.227
S618840 ................ 3.241
S6316 .................. 7.3
S6333 .................. 7.3
S63256 ................. 7.3
S63332 ................. 7.3
S6364 .................. 7.3
S63364 .................. 7.3
S63512 ................. 7.3
S631000 ................ 7.17
S631001 ................ 7.17
S6551 .................. 4.3
S6551A ................. 4.3
S65C51 ................. 4.11
S6845E ................. 4.26
S7720 .................. 3.181
S77C20 ................. 3.186
S8980 .................. 3.48
S8981 .................. 3.62
-} GOULD
AIMII®Semiconductors
Indices
Functional Index
Device
Device
Page
ASIC Products ........................ 2.3
Page
S61 C35 ................................. 3.202
S61 C337 ................................ 3.221
S618839 ................................ 3.227
S618840 ................................ 3.241
EPLDs ................................. 2.3
Gate Arrays ............................. 2.4
Standard Cells ........................... 2.5
Cell-based Custom ........................ 2.6
Foundry ................................ 2.7
ASiC Services ........................... 2.8
Microprocessor Support Circuits
S6551 .................................. 4.3
S6551 A ................................. 4.3
S65C51 ................................. 4.11
S6845E ................................. 4.26
Communication Products
Station Products
Display Driver Circuits
S2559E ................................ 3.3
S2559F ................................. 3.3
S2560A ................................ 3.12
S2560G/1 ............................... 3.19
S2561 .................................. 3.21
S2561A ................................ 3.21
82569 ....................... : .......... 3.27
S2569A ................................ 3.27
S25089 ................................. 3.34
S2579 .................................. 3.40
S8980 .................................. 3.48
S8981 .................................. 3.62
S4520
S4521
S4534
S4535
.................................. 5.3
.................................. 5.11
.................................. 5.14
.................................. 5.17
PLDs (PEELs)
18CV8 .................................. 6.3
18CV8-15 ............................... 6.13
20CG10 ................................ 6.16
22CV10 ................................. 6.24
22CV102 ............................... 6.29
PEEL 153 ............................... 6.34
PEEL 173 ............................... 6.39
PEEL 253 ............................... 6.44
PEEL 273 .............................. 6.49
PEEL Development System (PDS) ........... 6.54
Modems, Filters and PCM Products
S35212A ............................... 3.78
S352128 ............................... 3.84
S35213 ................................. 3.91
S3531 .................................. 3.103
83524A ................................ 3.118
S3525A ................................ 3.121
835268 ................................ 3.128
S35288 ................................ 3.135
S3529B ................................ 3.145
S35061 ................................. 3.154
S35071 ................................. 3.154
83507AI ................................ 3.154
83541 .................................. 3.170
S3547 .................................. 3.171
S7720 .................................. 3.181
S77C20 ................................ 3.186
S614381 ................................ 3.197
Static CMOS & NMOS ROMs
Static CMOS & NMOS ROMs Family of ROMs .. 7.3
S631000/1 .............................. 7.17
Mask ROMs App Note ..................... 7.24
General Information
Quality Program .......................... 8.3
Packaging ............................... 8.6
Ordering Information ....................... 8.21
Sales Offices, Representatives
and Distributors .......................... 8.23
1.3
-) GOULD
AIMII®Semiconductors
ASIC Products
-) GOUL[]
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AIMII®Semiconductors
I
ASIC Products
CMOS EEPLDs
Gould AMI was the first company to recognize the need
for custom integrated circuits in the mid-1960's, and to
pioneer the development of application-specific integrated circuits (ASICs). With more than twenty years'
dedication to providing ASIC system solutions, Gould
AMI has more experience than any other vendor of
ASICs.
User-programmable digital devices ideal for small and
medium-scale integration
Electrically erasable programmable logic devices are
ideal for small and medium-scale integration system
design in low-volume production. Our lowest development cost ASICs, these devices deliver plenty of performance and offer a surprising measure of versatility and
customer-control.
The company now offers a continuum of ASIC products,
ranging from CMOS programmable logic devices to complex cell-based custom ICs. This spectrum of offerings
provides customers with a full range of ASIC chOices, so
that the optimum solution for an application can be
selected.
Built using our unique PEEL'" (Programmable Electrically Erasable Logic) technology, these PLDs are userprogrammable, so there's no pre-production customer
design and development risk. You may use PC-based
or industry-standard PLD programmers to configure the
macrocells and, if necessary, to repeatedly erase and
reconfigure them.
Gould AMI's ASIC technology allows system designers
to tailor their systems and reduce the number of parts in
their products by combining multiple memory and
processing functions on a single device, instead of
mixing and matching several standard parts. The result:
smaller board sizes, lower final product cost and higher
reliability. ASIC users also benefit by greater product differentiation due to custom tailoring and higher security
ensured by an ASIC's resistance to duplication.
The table below can help you select the right PLD for
you. See the PLD section later in this catalog for
detailed data sheets.
Gould AMI's CMOS PLD Family
Part No.
Architecture
Complexity
Speed
18CV8
20 pin E2PLD
74 product terms x 36 input array
25ns Tpd
Bipolar PLDs
18CV8-15
20 pin E2PLD
74 product terms x 36 input array
15ns Tpd
Bipolar PLDs
20CG10
24 pin E2PLD
92 product terms x 44 input arrays
25ns Tpd
20V8,20G10
22CV10Z
24 pin E2PLD
132 product terms x 44 inputs
25ns Tpd
Bipolar PLDs
Zero power mode
22CV10
24 pin E2PLD
132 product terms x 44 inputs
25ns Tpd
Bipolar PLDs
PEEL 153
20 pin E2PLD
42 product terms x 36 inputs
10 sum terms x 32 product terms
30ns Tpd
Bipolar PLS153
PEEL 173
24 pin E2PLD
42 product terms x 44 inputs
10 sum terms x 32 product terms
30ns Tpd·
Bipolar PLS173
PEEL 253
·20 pin E2PLD
42 product terms x 36 inputs
20 sum terms x 42 product terms
30ns Tpd
Bipolar PLS 153
PEEL 153
PEEL 273
24 pin E2PLD
42 product terms x 44 inputs
20 sum terms x 42 product terms
30ns Tpd
Bipolar PLS 173
PEEL 173
2.3
Replaces
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-) GOULD
~MII®Semiconductors
ASIC Products
customize your design as a network of logic functions.
With only the metal layers to fabricate, gate array
development time is fast--typically four weeks.
Gate Arrays
Semi-finished digital chips provide high performance for
medium volume production with quick development
Gould AMI's gate arrays are fabricated in a double
metal, single poly, twin tub CMOS process. They offer
the CMOS advantages of low power dissipation, broad
power supply voltage range (2.5 to 5.5 Volts), and high
noise immunity.
• 1.25-micron and 2.0-micron Double Metal CMOS
Processes
• Basic Logic, Interface, MSI and 7400 Functions
• Custom RAMs and ROMs available in 1.25-micron
gate arrays
• Artificial Intelligence Software Services Available for
Netlist Translation and Gate Reduction
Over 600 macros in the process families include:
Gate arrays provide solutions for a variety of high performance digital applications--at a low development cost
and quick design time. If you need fast turn production
runs, gate arrays may be the right ASIC for you.
Gate arrays are semi-finished digital circuits that contain
patterns of uncommitted transistors pre-fabricated on
silicon base wafers. Using any major CAE workstation
at your own facility, you can use Gould AMI libraries to
Basic functions:
Simple gates, clock drivers,
flip/flops, latches
Interface functions:
TTL, CMOS Schmitt trigger, slew
rate buffers, TTL with hysteresis
MSI functions:
Counters, multiplexers, decoders,
adders
7400 funCtions:
Digital megacells:
Over 160 TTL compatible functions
RAMs
1.25·mlcron Gate Arrays
Array
Total Gates
Usable Gates
TAB
Programmable
Fine Pitch Standard Pitch
Power Pins
GC 100K
100000
54000
438
324
250
12
GC 50K
51456
28300
312
236
184
12
GC 40K
35640
19602
260
194
154
12
GC 30K
31920
17556
246
184
142
12
GC 25K
25728
14150
220
166
132
12
GC 20K
19840
10912
196
146
116
12
GC 15K
15000
8250
168
128 .
100
12
GC 10K
10320
5676
136
100
84
12
GC 7K
6912
3801
116
84
68
12
GC 5K
5280
2904
98
72
56
12
GC 3K
2520
1386
72
52
40
12
2.4
-) GOULD
AIMII®Semiconductors
I
ASIC Products
2.0-micron Gate Arrays
Array Name
Equivalent Gates
Max. Usable Gates
GB1000D
1120
1008
60
68
GB2000D
2128
1978 .
76
84
GB3000D
3264
3099
100
108
GB4000D
4256
4086
112
120
GB6000D
5880
5680
132
144
GB8000D
7872
7637
168
184
GB10000D
9776
9483
192
208
Standard Cell Circuits
Prog. Pins
Total Pins.
a gate array design specifies only the final metal layers
of a pre-fabricated silicon base, all of a standard cell's
base and metal layers are custom fabricated from precharacterized cells. This feature gives standard cells
greater design flexibility, but requires an eight week
development time.
Analog and digital building blocks offer higher density
and smaller size for medium to high volume needs
• 1.25 and 2-micron Double Metal CMOS Families
• 3-micron and 2-micron Double Poly, Double Metal
CMOS Families
• Cells Created by Expert-based Cell Generator
• Basic Logic, Interface, MSI, 7400 and Megacell
Functions
• 2-micron Process includes Analog Functions
• Tailor-made RAMs, ROMs and PLAs Available
• Artificial Intelligence Software Services Available for
Digital Netlist Translation and Gate Reduction
A standard cell circuit also uses only the number of cells
required for a design, whereas gate arrays seldom utilize all of the available cells. This means a smaller die
size and lower cost to you for a given circuit function.
Gould AMI offers over 850 cells in its four standard cell
families:
•
•
•
•
Chips designed with these cells, offered in analog and
digital formats, surpass gate array density and approach
that of cell-based custom designs at half the development cost and development time. They're cost effective
for medium to high-volume production.
1.25-micron digital CMOS (CAB family)
2-micron digital CMOS (CBB family)
3-micron analog and digital CMOS (CCI family)
2-micron analog and digital CMOS (ABX family)
Digital Standard Cells
Standard cells are pre-designed circuit building blocks
whose functional, timing and performance parameters
exist in Gould AMI's libraries. As with a gate array, you
design a standard cell circuit by choosing logic functions
from a library installed on a CAE workstation. But while
Both the CAB and CBB families use a double metal,
single poly, twin tub CMOS process. They are intended
primarily for 5 Volt operation but will operate down to 2.5
Volts.
2.5
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-) GOULD
~MII®Semiconductors
ASIC Products
Cells in these libraries include:
Cell-based Custom
Basic functions:
Most tailored ASIC solution--best for high performance,
mixed signal or high volume needs
simple gates, clock drivers,
flip/flops. latches
Interface functions:· TTL, CMOS, Schmitt trigger, slew
rate buffers, TIL with hysteresis
MSI functions:
Cell-based custom chips use a combination of Gould's
megacells, custom cells and standard cells to provide
you with the ultimate in design tailoring and performance. This approach is ideal when you have a requirement for high speed, special interfaces, mixed
analog/digital; or very high volume production runs.
counters, multiplexers, decoders,
adders
7400 functions:
over 160 ,TIL compatible functions
Digital megacells:
barrel shifter, funnel shifter, RAM,
ROM and PLA
Analog/Digital Standard Cells
The CCI family uses a 3-micron double metal, double
poly, p-well CMOS process. It is intended primarily for
analog and/or digital applications running at 10 Volts
analog with 5 Volts digital operation.
Though their development costs and time are longer
than with standard cells, cell-based custom circuits pack
the most functions into the smallest area. Fewer custom
chips need be used in a given deSign, thus saving board
space. Custom devices also provide greater security because they are nearly impossible to copy.
Gould AM·I's, new A~X process is a 2-micron double
poly, double metal process. This is Gould AMI's most
flexible process, built on N or P-type starting material,
with a range of 13 to 17 process layers. Ideal for mixed
signal analog and digital applications, itcan operate
from 5 to 12 volts. Functions include electrically
erasable ROMs,implant programmable ROMs and NPN
and PNP bipolar transistors ·on board.
Over twenty years' experience in custom design have
given Gould AMI's design team the kind of engineering
expertise that complex solutions demand. Particular
areas of expertise are analog, mixed signal, high voltage
and E2 applications. The following illustrate some examples of Gould AMI's answers to our customers' technical challenges.
Cells inthe CCI and ABX libraries include:
A consumer products manufacturer is developing an instrumentation device that measures pressure, room
dimensions and weight. The technical challenge? .To
reduce the number of discrete logic parts and consolidate into one device, which requires analog and digi~
tal functions on a single ASIC.
Basic functions:
simple gates, clock drivers,
flip/flops, latches
Interface functions:· TIL, CMOS, Schmitt trigger
MSI functions:
counters, multiplexers, decoders,
adders
7400 functions:
over 160 TIL compatible functions
Analog functions:
Op amps, NO, D/A, comparators,
switches, voltage references,
input buffer and output buffer
Case History #1
Gould AMI's Solution: A cell-based custom chip which incorporates LCD drivers, a comparator, aid converters,
gain stages and voltage references on a single chip,
thus making the measuring device perform more reliably
and reducing the number of components required. This
saves the customer money in component costs, as well
as assembly and inventory costs.
2.6
-) GOULD
AIMII®Semiconductors
I
ASIC Products
You'll then receive either untested protoypes or mapped
wafers that met our visual and parametric process
specifications. You'll inspect the sample to verify circuit
functionality and performance. With your approval, we
produce and assemble additional units that are tested
rigorously with your test program (or one we generate
from your specs). Gould AMI uses a variety of industrystandard and specialty testers, including Sentry, GenRad, Teradyne, and LTX.
Case History #2
Problem: An automotive company needs a drop-in re"
placement for a device that nearest fuel, oil and temperature and displays the results on a car dashboard. The
technical challenge? Thissmart device needs to be fast'
and super-accurate, with numerous features on a single
densely packed chip. The customer also requires fault
coverage to be 99%.
Gould AMI's solution: To integrate analog and digital
blocks on a single custom chip. The analog portion of
the circuit allows sampling of a greater number of bits,
thus resulting in a faster, more accurate display. The integrated solution enables Gould AMI to meet the size,
power, speed and accuracy requirements so that the
device will drop right in to the customer's board.
Gould AMI Process Technology Comparison
Process
Family
Geometry
Maximum
Voltage
Characteristics
CMOS
1.25 11
5.5 Volts
Digital
CMOS
2.011
5.0 to 12.0 Volts
Mixed Signal
Silicon Foundry Capabilities
CMOS
2.011
5.5 Volts
Digital
Flexible and experienced foundry services for existing
customer designs'
CMOS
3.011
5.0 to 10.0 Volts
Analog
CMOS
3.011
5.5 Volts
Digital
Gould AMI's foundry service is the solution for customers who have circuits ready for fabrication and need
a primary or secondary manufacturing source. Fifteen
years' experience in providing foundry services means
well-documented process specifications and a ilexible
factory, with the ability to accomodate process variations
for an existing customer design.
CMOS
2.011
5.5 Volts
EE Digital
CMOS
5.011
5.5 Volts
Digital
CMOS
5.011
5.5 Volts
Analog
CMOS
7.011
5.5 Volts
Digital
CMOS
7.011
5.5 Volts
Analog
NMOS
3.011
5.5 Volts
Digital
NMOS
4.011
5.5 Volts
Digital
NMOS
5.011
5.5 Volts
Digital
Foundry Steps
Gould AMI performs a thorough engineering review of
your database tape to assure accurate input. Aft~r
receiving your Calma II database tape, we generate
both single level plots and a final layout tape and submit
them for your approval. This verifies the design data
transfer to the tooling tape--before you commit the
design to silicon.
2.7
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AMll,Semiconductors
ASIC Products
TypIcal ASIC Development Flow
ASIC DESIGN SYSTEM
SCORE: SSI,
MSI MEGACELLS
. EXPERT SYSTEMS:
GATE G0881:.ER
GATE CRUNCHER
DESIGN ANALYZER
PATTERN ANALYZER
NETRANS
PALTRANS
Analog/DigItal
ASIC Software Services
Optional design services give you the power of choice
and ease your designs
Unlike many ASIC vendors that accept only completed
designs or finished netlists, Gould AMI is able to pick up
an ASIC design at any stage, whether customers submit
a partially finished design, a foundry-ready database
tape, or a simple set of specifications. In order to ease
logic design for its customers, Gould AMI has installed
its analog and digital cell libraries on popular engineering workstations including Mentor Graphics, Daisy Systems, Intergraph, VALID Logic Systems, FutureNet and
Viewlogic.
Gould AMI uses several advanced expert systems inhouse, each of which taps the combined experience of
Gould AMI's engineers to accelerate device layout and
design optimization.
2.8
-} GOULD
~MII®Semiconductors
ASIC Products
ASIC Netlist Translation Services:
Gate Gobbler, Gate Cruncher, Design Analyzer and Pattern Analyzer are artificial intelligence (AI) tools that assist with the conversion of conventional standard
devices to CMOS ASICs.
If a client has already designed a digital chip using
another vendor's or their own proprietary tools, Gould
AMI's NETRANST• expert system will "translate" the netlist into Gould AMI-compatible form in just a few hours.
This automated design transfer works independently of
workstation libraries or processes, and can save customers thousands of dollars and weeks of precious time.
For turning programmable logic device into gate arrays
or standard cells, PALTRANST• is the answer.
PALTRANS converts standard programmable array logic
(PAL), programmable electrically erasable logic (PEEL)
and field programmable gate arrays (FPGAs) into netlists used to deSign gate array or standard cell ASICs.
You can use an off-the-shelf PLD as a prototype for
programming, debugging, and beta-testing logic
deSigns, instead of first requiring the production of an
ASIC. Engineers then use PALTRANS to convert the
data into a nellis!. In about eight hours, mask production can begin and an ASIC design is produced in two to
three weeks.
By the end of 1989, Gould AMI will offer an Automatic
Test Generation tool that will generate test vectors in a
matter of hours, relieving designers of the task and
saving at least six weeks for manual test generation
This tool will automatically partition a circuit into a set of
combinatorial functions and insert a scan path. Each
function, seen as a distinct circuit, can be quickly and
easily tested with an automatic test program generator
employing the D-Algorithm.
Transitioning from standard TTL parts to ASICs can be
fraught with difficulty, and when ASIC prototypes don't
work, design re-work through traditional analysis and optimization techniques can take weeks or months. Gould
AMI's AI tools minimize the delays caused by having to
re-work a design through traditional analysis and optimization techniques. The tools incorporate a continually expanding knowledge base, applying Gould AMI's
hundreds of engineering man-years to every job.
Tools Speed Layout and Optimization
The SCORET• cell compiler generates and tailors cells to
a client's specific requirements in one-tenth the time required for hand-built cells.
2.9
I
-} GOULD
Communication Products
AIMll~Semiconductors
I·:
- .
I
DTMF Tone Generator
-} GOULD
AIMII®Semiconductors
S2559E/F
Features
o Wide Operating Supply. Voltage Range: 2.5 to 10
Volts
o Low 'Power CMOS Circuitry Allows Device Power to
be Derived Directly from the Telephone Lines or
from Small Batteries, e.g., 9V
o Uses TV Crystal Standard (3.58MHz) to Derive all
, Frequencies thus Providing Very High Accuracy
and Stability
o Mute Drivers On-Chip
o Interfaces Directly to a Standard Telephone PushButton or Calculator Type X-V Keyboard
o The Total Harmonic Distortion is Below Industry
Specification
o
o
o
o
Oscillator Resistor On Chip
On·Chip Generation of a Reference Voltage to
Assure Amplitude Stability of the Dual Tones Over
the Operating Voltage and Temperature Range
Single Tone as Well as Dual Tone Capability
Two Options Available:
'
E: Mode Select
F: Chip Disable
General Description
The S2559 DTMF Generator is specifically designed to
implement,a dual tone telephone dialing system. The
device can interface directly to a standard pushbutton
Block Diagram
Pin Configuration
VDD
XMIT
3.3
TONE OUT
MOSL/CD
C,
R,
C2
R2
C,
R3
V"
R,
OSC,
MUTE
OSC,
C,
1
- _=-
I
-} GOULD
AIMII®Semiconductors
S2559E/F
General Description (Continued)
telephone keyboard or calculator type X-V keyboard
and operates directly from the telephone lines_ All
necessary dual-tone frequencies are derived from the
widely used TV crystal standard providing very high accuracy and stability_ The required sinudsoidal waveform for the individual tones is digitally synthesized on
the chip. The waveform so generated has very lOW total
harmonic distortion. A voltage reference is generated
on the chip which is stable over the operating voltage
and temperature range and regulates the signal levels
of the dual tones to meet the recommended telephone
industry specifications. These features permit the
S2559 to be incorporated with a slight modification of
the standard 500 type telephone basic circuitry to form
a pushbutton dual-tone telephone. Other applications
of the device include radio and mobile telephones,
remote control, Point-of-Sale, and Credit Card Verification Terminals and process control.
Absolute Maximum Ratings
DC Supply Voltage (VDD - Vss ) ............................... ; ............................ , ... + 10.5V
Operating Temperature ............................................................ " - O°C to + 70°C
Storage Temperature ............ : .............................................. "... - 30°C to + 125°C
Power DiSSipation at25°.C ............... ; ....... , ................... ~ ...................... 1000mW
Input ................ " ............. ; .................... '.' .. , ....... "'.".: ." . '>' Vss ~ ·0.3~VIt~~VDD + 0.3
S2559EJF Electrical Characteristics:
(Specifications apply over the operating temperature range of O°C to + 70°C unless otherwise noted. Absolute values
of measured parameters are specified.)
Symbol
(Voo-Vss)
Volts
Parameter/Conditions
Min.
Typ.
Max.
Units
Supply Voltage
Tone Out Mode (Valid Key Depressed)
2.5
10.0
V
Non Tone Out Mode (No Key Depressed)
1.6
10.0
V
Voo
Supply Current
Standby (No Key Selected, Tone, XMIT
3.0
0.3
30 "
,..A
and MUTE Outputs Unloaded)
10.0
1.0
100
,..A
".
100
Operating (One Key Selected, Tone, XMIT "
3.0
1.0
2.0
mA
and MUTE Outputs Unloaded)
10 . 0
8'
16.0
mA
Tone Output
Single Tone
Row Tone, RL = 390Q
3.5
335
465
565
mVrms
5.0
380
540
710
mVrms
10.0
380
550
735
mVrms
dBCR
Ratio of Column to Row Tone (Dual Tone Mode)2559E/F
3.5 -10.0
1.0
2.0
3.0
dB
%DIS
Distortion *
3.5 -10.0
7
%
S2559E/F
VOR
Mode Output
Voltage
Row Tone, RL = 240Q
2559E/F
3.4'
-} GOULD
.AlMII®Semiconductors
S2559E/F
S2559EJF Electrical Characteristics: (continued)
Symbol
(Voo·Vss)
Volls
Parameter/Conditions
Unils
XMIT, MUTE Outputs
VOH
XMIT, Oulput Vollage, High
(IOH=15mA)
3.0
1.5
1.8
(No Key Depressed)(Pin 2)
(lOH=50mA)
10.0
8.5
8.8
10.0
XMIT, Output Source Leakage Current, VOF=OV
IOF
VOL
VOH
flA
MUTE (Pin 10) Output Voltage, Low,
2.75
0
0.5
V
10.0
0
0.5
V
MUTE, Output Voltage, High,
2.75
2.5
2.75
V
(One Key Depressed) No Load
10.0
9.5
10.0
V
VOL =0.5V
Current
IOH
V
100
(No Key Depressed), No Load
MUTE, Output Sink
IOl
V
3.0
0.53
1.3
mA
10.0
2.0
5.3
mA
MUTE, Output Source
VOH=2.5V
3.0
0.17
0.41
mA
Current
VOH =9.5V
10.0
0.57
1.5
mA
'Distortion Is defined as "the ralio of the total power of ail extraneous frequencies, in the VOICE band above 500Hz, to the total power of
. the DTMF frequency pair".
Table 2. XMIT and MUTE Output Functional Relationship
Table 1. Comparisons of Specified vs Actual Tone
Frequencies Generated by S2559
OUTPUT FREQUENCY Hz
% ERROR
ACTIVE
INPUT
SPECIFIED
ACTUAL
SEE NOTE
R1
R2
R3
R4
C1
'C2
C3
C4 .
697
770
852
941
1,209
1,336
1,477
1,633
699.1
766.2
847.4
948.0
1,215.9
1,331.7
1,417.9 .
1,645.0
+0.30
-0.49
-0.54
. +0.74
+0.57
-0.32
-0.35
+0.73
NOTE: % Error does not include oscillator drift.
3.5
OUTPUT
RELEASED
'DIGIT' KEY
DEPRESSED
XMIT
MUTE
'DIGIT' KEY
COMMENT
VDD
High
Impedance
Can source at least
50mA at 1OV with
1.5V max. drop
Vss
VDD
Can source or
sink current
_:1'
-
.
I
-} GOULD
AIMII®Semiconductors
S2559E/F
Figure 1. Standard Telephone Push Button Keyboard
,-
Al~'-
:0-----,
--cp--cp--cp
I
I
I
I
I
I
I
I
I
I
I
I
8--0--0---1
A3~r-
e-o-+
A2
--cp--cp--cp
0--0--0----;
I
I
I
0-0- A4
COMMON
(CONNECT TO Voo OR
LEAVE FLOATING)
- - - MECHANICAL
LINKAGE
Ron (Contact Resistance).;;;; lkn
Circuit Description
The S2559 is designed so that it can be interfaced easi·
Iy to the dual tone signaling telephone system and that
it will more than adequately meet the recommended
telephone industry specifications regarding the dual
tone signaling scheme.
highest high group frequency of 1633Hz (Col. 4) is not
used. The frequency tolerance must be ± 1,.0%. How·
ever, the S2559 provides a better than .75% accuracy.
The total harmonic and intermodulation distortion of
the dual tone must be less than 10% as seen at the, tele·
phone terminals. (Ref. 1.) The high group to low group
signal amplitude ratio should be 2.0 ± 2dB and the
absolute amplitude of the low group and high group
tones must be within the allowed range. (Ref. 1.) These
requirements apply when the telephone is used over a
short loop or long loop and over the operating tempera·
ture range. The design of the S2559 takes into account
these considerations.
Design Objectives
The specifications that are important to the design of
the DTMF Generator are summarized below: the dual
tone signal consists of linear addition of two voice fre·
quency signals. One of the two signals is selected from
a group of frequencies called the "Low Group" and the
other is selected from a group of frequencies called the
"High Group". The low group consists of four frequen·
cies 697,770,852 and 941 Hz. The high group consists
of four frequencies 1209, 1336, 1477 and 1633 Hz. A
keyboard arranged in a row, column format (4 rows x 3
or 4 columns) is used for number entry. When a push
button corresponding to a digit (0 thru 9) is pushed, one
appropriate row (R1 thru R4) and one appropriate col·
umn (C1 thru C4) is selected. The active row input
selects one of the low group frequencies and the active
column input selects one of the high group frequen·
cies. In standard dual tone telephone systems, the
Oscillator
The device contains an oscillator circuit with the
necessary parasitic capacitances and feedback
resistor on chip so that it is only necessary to connect a
standard 3.58MHz TV crystal across the OSC I and
OSC o terminals to implement the oscillator function.
The oscillator functions whenever a row input is actio
vated. The reference frequency is divided by 2 and then
drives two sets of programmable dividers, the high
group and the low group.
3.6
-) GOULD
~MII®Semiconductors
I
S2559E/F
for a common line, can be used. Conventional telephone push button keyboards as shown in Figure 1 or
X-V keyboards with common can also be used. The
common line of these keyboards can be left unconnected or wired "high".
Keyboard Interface
The S2559 employs a calculator type scanning circuitry
to determine key closures. When no key is depressed,
active pull·down resistors are "on" on the row inputs
and active pull·up resistors are "on" on the column in·
puts. When a key is pushed a high level is seen on one
of the row inputs, the oscillator starts and the keyboard
scan logic turns on. The active pull·up or pull·down
resistors are selectively switched on and off as the
keyboard scan logic determines the row and the column inputs that are selected. The advantage of the
scanning technique is that a keyboard arrangement of
SPST switches are shown in Figure 2 without the need
Logic Interface
The S2559 can also interface with CMOS logic outputs
directly. The S2559 requires active "High" logic levels.
Since the active pull-up resistors present in the S2559
are fairly low value (500Q typ), diodes can be used as
shown in Figure 3 to eliminate excessive sink current
flowing into the logic outputs in their "Low" state.
Figure 2. SPST Matrix Keyboard Arranged in the 2 of 8 Row, Column Format
Al
A2
R3
A4
SPST MATRIX KEYSORTED:
/
JNO
01
C2
C3
C4
(OPTIONAL COLUMN)
are used to digitally synthesize a stair-step waveform to
approximate the sinewave function (see Figure 3). This
is done by connecting a weighted resistor ladder network between the outputs of the Johnson counter, VDD
and V REF . V REF closely tracks V DD over the operating
voltage and temperature range and therefore the peakto-peak amplitude Vp (VDD - V REF) of the stairstep function is fairly constant. VREF is so chosen that Vp falls
within the allowed range of the high group and low
group tones.
Tone Generation
When a valid key closure is detected, the keyboard
logic programs the high and low group dividers with
appropriate divider ratios so that the output of these
dividers cycle at 16 times the desired high group and
low group frequencies. The outputs of the programmable dividers drive two 8-stage Johnson counters.
The symmetry of the clock input to the two divide by 16
Johnson counters allows 32 equal time segments to be
generated within each output cycle. The 32 segments
3.7
I
I
1
- _=.
-} GOULD
~MII®Semiconductors
S2559E/F
Figure 3. Logic Interface for Keyb08rd Inputs of the S2559
01
S2559
Vss
08
Vss
6
G1 THRU G8 ANY TYPE CMOS GATE
01 THRU 08 DIODES TYPE IN914
Figure 4. Stairstep Waveform of the Digitally Synthesized Sinewave
IVoo ) 1.0
0.9
0.8
0.7
>"
:il
N
0.6
""
0.5
::;
c:
c
'"
0.4
0.3
0.2
0.1
IV,d)
0
3.8
-} GOULD
AIMII®Semiconductors
S2559E/F
states. The effect is the device essentially disconnects
from the keyboard. This allows one keyboard to be shared
among several devices. The CD pin has an internal
pull-down.
The individual tones generated by the sinewave synthesizer are then linearly added and drive a bipolar NPN
transistor connected as emitter follower to allow proper impedance transformation, at the same time preserving signal level.
MUTE, XMIT Outputs
Dual Tone Mode
The S2559E, F have a CMOS buffer for the MUTE output
and a bipolar NPN transistor for the XMIT output. With
no keys depressed, the MUTE output is "low" and the
XMIT output is in the active state so that substantial
current can be sourced to a load. When a key is
depressed, the MUTE output goes high, while the XMIT
output goes into a high impedance state. When Chip
Disable is "high" the MUTE output is forced "low" and
the XMIT output is in active state regardless of the state
of the keyboard inputs.
When one row and one column is selected dual tone
output consisting of an appropriate low group and high
group tone is generated. If two digit keys, that are not
either in the same row or in the same column, are depressed, the dual tone mode is disabled and no output
is provided.
Single Tone Mode
Single tones either in the low group or the high group
can .be generated as follows. A low group tone can be
generated by activating the appropriate row input or by
depressing two digit keys in the appropriate row. A high
group tone can be generated by depressing two digit
keys in the appropriate column, Le., selecting the
appropriate column input and two row inputs in that
column.
Amplitude/Distortion Measurements
Amplitude and distortion are two important parameters
in all applications of the Digital Tone Generator. Amplitude depends upon the operating supply voltage as
well as the load resistance connected on the Tone Output pin. The on-chip reference circuit is fully operational when the supply voltage equals or exceeds 5 volts
and as a consequence the tone amplitude is regulated
in the supply voltage range above 5 volts. The load
resistor value also controls the amplitude. If RL is low
the reflected impedance into the base of the output
transistor is low and the tone output amplitude is lower.
For RL greater than 5kQ the reflected impedance is sufficiently large and highest amplitude is produced. Individual tone amplitudes can be measured by applying
the dual tone signal to a wave analyzer(H-P type 3581A)
and amplitudes at the selected frequencies can be
noted. This measurement also permits verification of
the preemphasis between the individual frequency
tones.
Mode Select
The S2559E has a Mode Select (MDSL) input (Pin 15).
When MDSL is left floating (unconnected) or connected
to VDD , both the dual tone and single tone modes are
available. If MDSL is connected to Vss , the single tone
mode is disabled and no output tone is produced if an
attempt for single tone is made. The S2559F does not
have the Mode Select option.
Chip Disable
The S2559F has a Chip Disable input at Pin 15 instead
of the Mode Select input. The chip disable for the
S2559F is active "high." When the chip disable is active, the tone output goes to Vss , the row, column inputs go into a high impedance state, the oscillator is inhibited and the MUTE and XMIT outputs go into active
Quartz Crystal Specification (25° C ± 2°C)
Distortion is defined as "the ratio of the total power of
all extraneous frequencies in the voiceband above
500Hz accompanying the signal to the power of the frequency pair." This ratio must be less than 10% or when
expressed in dB must be lower than - 20dB.
Operating Temperature Range: DoC to + 70°C
Frequency ............................... 3.579545MHz
Frequency Calibration Tolerance .................... 02 ± %
Load Capacitance ................................. 18pF
Effective Series Resistance .................. 180 Ohms, max.
Drive Level-Correlation/Operating ..................... 2mW
Shunt Capacitance ............................. 7pF, max.
Oscillation Mode ............................ Fundamental
(Ref. 1.) Voiceband is conventionally the frequency
band of 300Hz to 3400Hz. Mathematically distortion
can be expressed as:
.
V"-(V-1-)2-+-(-V2-)2-+-.-.+-(VN-)2DIs!. =
V (VLl2 + (VH)2
where (V1) .• (V N) are extraneous frequency (Le., intermodulation and harmonic) components in the 500Hz to
3.9
-) GOULD
AIMII®Semiconductors
S2559E/F
"As a first approximation distortion in dB equals the difference between the amplitude (dB) of the extraneous
component that has the highest amplitude and the
amplitude (dB) of the low frequency signal." This rule of
thumb would give an estimate of - 28dB as distortion
for the spectrum plot of Figure 6 which is close to the
computed result of - 30dB.
3400Hz band and VL and VH are the individual frequency
components of the DTMF signal. The expression can
be expressed in dB as:
DIST = 20 log
dB
Vr-(-V1
-)-2+-(V2)-2+-.-.-(V-N-)2-
V (VLl2 + (VH)2
=
10{ log[(V1)2 + .. (VN)2]-log[ (VLl2 + (VL)2 + (VH)2]) ... (1)
In a telephone application amplitude and distortion are
affected by several factors that are interdependent. For
detailed discussion of the telephone application and
other applications of the 2559 Tone Generator, refer to
the applications note "Applications of Digital Tone
Generator."
An accurate way of measuring distortion is to plot a
spectrum of the signal by using a spectrum analyzer
(H-P type 3580A) and an X-V plotter (H-P type 7046A). Individual extraneous and signal frequency components
are then noted and distortion is calculated by using the
expression (1) above. Figure 6 shows a spectrum plot of
a typical signal obtained from a S2559 device operating
from a fixed supply of 4Vdc and RL = 10kQ in the test
circuit of Figure 5. Mathematical analysis of the spectrum shows distortion to be - 30dB (3.2%). For quick
estimate of distortion, a rule of thumb as outlined
below can be used.
Ref. 1: Bell System Communications Technical Reference, PUB 47001; "Electrical Characteristics of Bell
System Network Facilities at the Interface with Voiceband Ancillary and Data Equipment," August 1976.
Figure 5. Test Circuit for Distortion Measurement
1
+
LOW IMPEO.
DC
POWER
SUPPLY
r-.;0
V
M
--=-
-
"iD
T
TONE
OUT
16
MOSL
..!!.
..1.
XMIT
.2.
C1
....i
C2
R2
---2..
CJ
R,
Vss
R,
CD
R,
SIG
14
SPECTRUM
ANALYZER
X·Y
pLonER
H·P
TYPE
J580A
H·P
TYPE
7046A
52559
6
J.579545MHz
CRYSTAL
Voo
7
8
..!!
~.
:~
MUTE
~
OSCo
C,
jl..
GND
3.10
=
XIN
YOUT
I
YIN
RL = 10kn
f.!.!..
OSCi
XOUT
.y
GOULD
~MII®Semiconductors
S2559E/F
Figure 6. A Typical Spectrum Plot
1
VOICEBAND
/
/
·5
/
/
-lD
/
/
/
/
/
/
/
-15
-20
I
V
V
V
V
V
V
V
VHt-l.5)
Vll_4.S)
-25
/
-45
-so
/
V
VZ(_321
/
/
V5(_36)
V
/
V31_44)
V81_411
V4(-411
VI \-481
~
-55
-60
-65
Ii
I
RL" IDkn
TEST CKT" FIGURE 5
/
/
/
/
/
/
/
/
-40
TEMP" ROOM
V
/
-35
DEVICE .. SZ5590
(Villi - Vss) " 4V DC FIXED
V
/
-3D
- _=.
/
/
/
/
/
/
D.5
1.0
1.5
2.D
~
~
2.5
'.D
FREQUENCY (KHz)
--..
•
~
'.5
I
4.D
,
4.5
~I
5.D
An application note is also available describing the design considerations, test methods, and results obtained using the 82559 Tone Generator
family in DTMF pushbutton telephones. Interface with type 500 and 2500 networks are discussed. Use in ancillary equipment is also covered.
Please contact factory.
3.11
Pulse Dialer
-) GOULD
AIMII®Semiconductors
S2560A
Features
D Low Voltage CMOS Process for Direct Operation
from Telephone Lines
D Inexpensive R-C Oscillator Design Provides Better
than ± 5% Accuracy Over Temperature and Unit to
Unit Variations
D Dialing Rate Can be Varied by Changing the Dial
Rate Oscillator Frequency
D Dial Rate Select Input Allows Changing of the Dialing Rate by a 2:1 Factor Without Changing Oscillator Components
D Two Selections of Mark/Space Ratios (33 1/3/66 2/3 or
40/60)
D Twenty Digit Memory for Input Buffering and for Redial with Access Pause Capability
. D Mute and Dial Pulse Drivers on Chip
D Accepts DPCT Keypad with Common Arranged in a
2 of 7 Format; Also Capable of Interface to SPST
Switch Matrix
General Description
The S2560A Pulse Dialer is a CMOS integrated circuit
that converts pushbutton inputs to a series of pulses
suitable for telephone dialing. It is intended as a
replacement for the mechanical telephone dial and can
operate directly from the telephone lines with
minimum interface. Storage is provided for 20 digits,
therefore, the last dialed number is available for redial
until a new number is entered. IDP is scaled to the dialing rate such as to produce smaller IDP at higher dialing rates. Additionally, the lOP can be changed by a 2:1
factor at a given dialing rate by means of the IDP select
input.
Block Diagram
Pin Configuration
KEYBOARD
INPUTS
R,
C3
R,
C,
R,
C,
R3
lOP
itS
DRS
DIAL \ RO
R,
VDD
RATE
OSC
Co
MIS
Ro
MUTE
jjji
V"
I
Co
RE
ifi'
MTf11
DRS
IPS
MIS
3.12
GOULD
AIMII®Semiconductors
S2560A
Absolute Maximum Ratings:
Supply Voltage' ......................................................................................................................................................................... + 5.5V
Operating Temperature Range .............................................................................................................................. "' O·C to + 70·C
StorageTemperatureRange .............................................................................................................................. -65·Cto +150·C
Voltage at any Pin ...................................................................................................................................... Vss - O.3V to VDD + O.3V
Lead Temperature (Soldering, 10sec) ..................................................................................................................................... 300·C
Electrical Characteristics:
1.5V~VDD
- Vss
VOO"Vss
(Volts)
Min.
Max.
Specifications apply over the operating temperature and
Symbol
Parameter
~3.5V
unless otherwise specified.
Units
Conditions
Output Current Levels
IOLOP
DP Output Low
Current (Sink)
3.5
125
,..A
VOUT
=
0.4V
IOHOP
DP Output High
Current (Source)
1.5
3.5
20
125
,..A
,..A
VO UT
VOUT
tV
2.5V
IOLM
MUTE Output Low
Current (Sink)
3.5
125
,..A
VO UT
=
=
=
O.4V
IOHM
MUTE Output High
Current (Source)
1.5
3.5
20
125
,..A
,..A
VOUT
VOUT
=
=
tV
2.5V
IOLT
Tone Output Low
Current (Sink) .
1.5
20
~A
VOUT
=
O.4V
IOHT
Tone Output High
Current (Source)
1.5
20
~A
VOUT
=
IV
VOR
Data Retention Voltage
100
Quiescent Current
1.0
1.0
750
nA
V
100
Operating Current
1.5
3.5
100
500
,..A
~A
fo
Oscillator Frequency
1.5
10
kHz
IIfo/fo
Frequency Deviation
1.5 to 2.5
-3
+3
%
2.5 to 3.5
-3
+3
%
"On Hook" HS = VOO. Keyboard open, all
other input pins to Voo or Vss
DP, MUTE open, HS = Vss ("Off Hook")
Keyboard processing and dial pulsing at 10
pps al conditions as above
Fixed R'C oscillator components
50KQ"R o" 750KQ; 100pF" Co' ,,1000pF;
750kQ" RE ,,5MQ
• 300pF most desirable value for CD
Input Voltage Levels
VIH
Logical "1"
80% of
(Voo- Vss )
Voo
+0.3
V
VIL
Logical "0"
Vss
-0.3
20% of
(Voo- Vss )
V
CIN
Input Capacitance Any Pin
7.5
pF
The device power supply should always be turned on before the input signal sources, and the input signals should be turned off before the power supply is turned off (Vss"
VI" VOO as a maximum limit). This rule will prevenl over'dissipation and possible damage of the input-prolection diode when the device power supply is grounded. When
power is first applied to the device, the device should be in "On Hook" condition (HS = 1). This is necessary because there is no internal power orreset on chip and for proper operation all internal latches musl come up in a known slate. In applications where the device is hard wired in "Off Hook" (HS = 0) condition, a momentary "On Hook"
condition can be presented to the device during power up by use of a capacitor resistor network as shown in Figure 6.
3.13
-} GOULD
AIMII®semiconductors
S2560A
by simply changing the external resistorvalue. The dial
rate select input allows changing of the dialing rate by a
factor of 2 without the necessity of changing the exter·
nal component values. Thus, vvith the oscillator adjusted
to 2400Hz, dialing rates of 10 or 20pps canbe achieved.
Dialing rates of 7 and 14pps similarly can be achieved by
changing the oscillator frequency to 1680Hz.
Functional Description
The pin function designations are outlined in Table 1.
Oscillator
The device contains an oscillator circuit that requires
three external components: two resistors (RD and RE)
and one capacitor (CD). All internal timing is derived
from this master time base. To eliminate clock interfer·
ence in the talk state, the oscillator is only enabled duro
ing key closures and during the dialing state. It is
disabled at all other times including the "on hook" con·
dition. For a dialing rate of 10pps the oscillator should
be adjusted to 2400Hz. Typical values of external com·
.ponents for this are RD and RE = 750kQ and
CD = 270pF. It is recommended that the tolerance of
resistors to be 5% and capacitor to be 1 % to insure a
10% tolerance of the dialing rate in the system.
The Inter·Digit Pause (lOP) time is also derived from the
oscillator frequency and can be changed by a factor of 2
by the lOP select input. With lOP select pin wired to Vss,
an lOP of 800ms is obtained for dial rates of 10 and
20pps. lOP can be reduced to 400ms by wiring the lOP
select pin to VDD . At dialing rates of 7 and 14pps, lOP's of
1143ms and 572ms can be similarly obtained. If the lOP
select is connected to the dial rate select pin, the lOP is
scaled to the dial rate such that at 10pps an lOP of 800ms
is obtained and at 20pps an lOP of 400ms is obtained.
The user can enter a number up to 20 digits long from a
standard 3x4 double contact keypad with common
(Figure 1). It is also possible to use a logic interface as
shown in Figure 2 for number entry. Antibounce protec·
tion circuitry is provided on chip (min. 20ms) to prevent
false entry.
Keyboard Interface (S2560A)
The S2560A employs a scanning technique to determine
a key closure. This permits interface to a DPCT keyboard
with common connected to VDD (Figure 1), logic inter·
face (Figure 2) and interface to a SPST switch matrix
(Figure 7). A high level on the appropriate row and col·
umn inputs constitutes a key closure for logic interface.
When using a SPST switch matrix, it is necessary to add
small capacitors (30pF) from the column inputs to Vss to
insure that the oscillator is shut off after a key is released
or after the dialing is complete.
Any key depressions during the on·hook condition are
ignored and the oscillator is inhibited. This insures that
the current drain in the on·hook condition is very low and
used to retain the memory.
Normal Dialing
The user enters the desired numbers through the key·
board after going off hook. Dial pulsing starts as soon as
the first digit is entered. The entered digits are stored se·
quentially in the internal memory. Since the device is
designed in a FIFO arrangement, digits can be entered at
a rate considerably faster than the output rate. Digits can
be entered approximately once every 50ms while the
dialing rate may vary from 7 to 20pps. The number
entered is retained in the memory for future redial.
Pauses may be entered when required in the dial se·
quence by pressing the "#" key, which provides access
pauses for future redial. Any number of access pauses
may be entered as long as the total entries do not exceed
twenty.
OFF Hook Operation: The device is continuously powered
through a 150kQ resistor during Off hook operation. The
DP output is normally high and sources base drive to
transistor 0 1 to turn ON transistor 02. Transistor 02
replaces the mechanical dial contact used in the rotary
dial phones. Dial pulsing begins when the user enters a
number through the keyboard. The DP output goes low
shutting the base drive toOl OFF causing 02 to open
during the pulse break. The MUTE output also goes low
during dial pulsing allowing muting of the receiver
through transistors 0 3 and 0 4 . The relationship of dial
pulse and mute outputs are shown in Figure 3.
ON Hook Operation: The device is continuously powered
through a 10-20MQ resistor during the ON hook opera·
tion. This resistor allows enough current from the tip and
ring lines to the device to allow the internal memory to
hold and thereby providing storage of the last number
dialed.
Auto Dialing
The last number dialed is retained in the memory and
therefore can be redialed out by going off hook and
pressing the "#" key. Dial pulsing will start when the
key is depressed and finish after the entire number is
dialed out unless an access pause is detected. In such
a case, the dial pulsing will stop and will resume again
only after the user pushes the "#" key.
The dialing rate is derived by dividing down the dial rate
oscillator frequency. Table 2 shows the relationship of
the dialing tate with the oscillator frequency and the dial
rate select input. Different dialing rates can be derived
3.14
-) GOULD
~MII®Semiconductors
S2560A
Table 1. S2560A/S2560B Pin/Function Descriptions
Pin
Keyboard
(R1' R2 , R3 , R4 , C1 , C2 , C3)
Number
Function
2, 3,4,
1, 16,
17, 18
These are 4 row and 3 column inputs from the keyboard contacts. These inputs are
open when the keyboard is inactive. When a key is pushed, an appropriate row and
column input must go to Voo or connect with each other. A logic interface is also possible as shown in Figure 2. Active pull up and pull down networks are present on these
inputs when the device begins keyboard scan. The keyboard scan begins when a key
is pressed and starts the oscillator. Debouncing is provided to avoid false entry (typ.
20ms).
Inter·Digit Pause Select (lOP)
15
One programmable line is available that allows selection of the pause duration that exists between dialed digits. It is programmed according to the truth table shown in
Table 3. Note that preceding the first dialed pulse is an inter-digit time equal to the
selected lOP. Two pauses either 400ms or 800ms are available for dialing rates of 10
and 20 pps. lOP's corresponding to other dialing rates can be determined from Tables
2 and 3.
Dial Rate Select (DRS)
14
A programmable line allows selection of two different output rates such as 7 or 14 pps,
10 or 20 pps, etc. See Tables 2 and 3.
Mark/Space (M/S)
12
This input allows selection of the mark/space ratio, as per Table 3.
Mute Out (MUTE)
11
A pulse is available that can provide a drive to turn on an external transistor to mute
the receiver during the dial pulsing.
Dial Pulse Out '(DP)
9
Output drive is provided to turn on a transistor at the dial pulse rate. The normal output
will be "low" during "space" and "high" otherwise.
Dial Rate Oscillator
(RE' CD, RD)
6, 7, 8
These pins are provided to connect external resistors RD, RE and capacitor Co to form
an R-C oscillator that generates the time base for the Key Pulser. The output dialing
rate and lOP are derived from this time base.
Hook Switch (HS)
5
This input detects the state of the hook switch contact; "off hook" corresponds to Vss
condition.
Power (VDD , Vss )
13, 10
These are the power supply inputs. The device is designed to operate from
1.5V-3.5V.
Figure 1. Standard Telephone Pushbutton Keyboard
r
I
I
HI--a----
Figure 2. Logic Interface for the S2560
G
1
.- - -0)--(0--(0
I
I
r
I
I
1
0)--0--8-- P..o-A?
1
1
1
I
1
1
KEYBOARD
INPUTS
--(0--0--0
1l3--o---e~
1
I
,I
1
I
0--0)--0I
I
I
,1
,.
RON (CONTACT RESISTANCE).;; lkn
?"
I.J.
~'3
-~..o-Hl
G
7
COMMor;
(CONNECTTQ Voa)
- - - MECHANICAL
LINKAGE
3.15
S2561J
_:1'
-
.
I
-} GOULD
AIMII®Semiconductors
S2560A
n
LOOPCURRENT---=---'I
DIAL PULSES·
:
'--_.....J
1MARK I
lOP
SPACE
I
I
I
' - - _......
:
I
1
lOP
I
I
I
I
~I...-I_~_ _ _~~~,--I_ _ _ __ _
Table 2. Table for Selecting Oscillator Component Values for Desired Dialing Rates and Inter-Digit Pauses
Dial Rale
Desired
Osc. Freq.
(Hz)
5.5/11
6/12
6.5/13
7/14
7.5/15
8/16
8.5/17
9/18
9.5/19
10/20
1320
1440
1560
1680
1800
1920
2040
2160
2280
2400
(fd/ 24O)/
(fd/ 12O)
fd
RD
Re
(kQ)
(kQ)
CD
(pF)
Select components in the
ranges indicated in table
of electrical specifications
750
270
750
Dial Rale (pps)
lOP (ms)
DRS';' Vss
DRS = VDD
IPS = Vss
IPS = VDD
5.5
6
6.5
11
12
13
14
15
16
1454
1334
1230
1142
1066
1000
942
888
842
800
727
667
615
571
533
500
471
444
421
400
1920 10 3
fi
x
960 10 3
fi x
7.5
8
8.5
9
9.5
10
18
19
20
(fd/ 24O)
(fd/ 12O)
17
NOTE: lOp is dependent on the dialing rate selected. For example, for a dialing rate of 10pps, an lOP of either BOOms or 400ms can be selected. For a dialing rate of 14pps,
and lOP of either 1142ms or 571ms can be selected.
Table 3.
Function
Dial Pulse Rate Selection
Inter-Digit Pause Selection
Pin Designation
Input Logic Level
Selection
DRS (14)
VSS
Voo
(1/240)pps
(1/120)pps
lOP (15)
Voo
-r
960
s
Vss
--r
1920
s
Mark/Space Ratio
M/S (12)
On Hook/Off Hook
HS
Vss
Voo
Voo
Vss
(5)
NOTE: f is the oscillator frequency and is detemined as shown in Figure 5.
3,16
33V3/66 213
40/60
On Hook
Off Hook
GOULD
AIMII®Semiconductors
S2560A
Figure 4. Pulse Dialer Circuit with Redial
Ro= 10-20MQ, R, = 150kQ, R,= 2kQ
R3 = 470kQ, R" Rs = 10kQ, RlO = 47kQ
R6, Rs = 2kQ, R" Rg = 30kQ, R11 = 20Q. 2W
Z,=3.9V. D,-D,=IN4004, os, 06, o,=IN914, C,=15~F
RE = Ro = 750kQ, Co = 270pF, C, = O.01~F
0" 0, = 2N5550 TYPE 0" 03 = 2N5401 TYPE
Z, = IN5379 110V ZENER OR 2XIN4758
"
Ilion
'AIITSREOUIRECQMMONOfTHEKEYBOAROCONNECTEDTOVOO
Figure 5. Pulse Dialer Circuit with Redial (Single Hook Switch Contact Application for PABX)
R, = 10-20MQ, R, = 2kQ
R3=470kQ, R" Rs=10kQ
R6, RB = 2kQ, R" Rg = 30kQ
RlO = 47kQ, R" = 20Q, 2W
Z,=3.9V, D,-D,=IN4004
Ds, D6, D,=IN914, C,=15f1F
RE, Ro = 750kQ, Co = 270pF
C, = O.01~F, Q" 04 = 2N5550
0" 03= 2N5401
Z,= 150V ZENER OR VARISTOR TYPE GE MOV150
NOTE.rARTSAEDUIAECOMMONOFTHEKen(lAAOCOflfllECHOTOV OD
3.17
-) GOULD
~MII®Semiconductors
S2560A
Figure 6. Circuit for Applying Momentary "ON Hook"
Condition During Power Up
~~
13
Figure 7. SPST Switch Matrix Interface
VDD
C,
C2
C3
I I
S2560A
S2560A
Rl
HS
R2
lDOk!l
R3
R4
*
10
VSS
30pFT
3.18
TT
VSS
1
¢
-} GOULD
AIMII®Semiconductors
Pulse Dialer
S2560G/S2560G1
_:1'
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-
General Description
The S2560G is a modified version of the S2560A Pulse Dialer with complete pin/function compatibility. It is recom·
mended to be used in all new and existing designs. Most electrical specifications for both devices are identical.
Please refer to S2560A data sheet for details. S2560G1 is low voltage version of S2560G.
Operating Voltage, Dialing:
Operating Voltage, Voice Mode:
Data Retention Voltage (Minimum):
100 Operating Current:
100 Standby Current:
Keyboard Debounce Time:
X-V Keyboard Interface:
Redial Buffer:
Dialing Characteristics:
Inter-digit pause timing
2560G1
2.0V to 3.5V
1.5V to 3.5V
1.0V
200IlA@2.0V
1000IlA@3.5V
21lA@1V
1.5V to 3.5V
1.5V to 3.5V
1.0V
100IlA@1.5V
500IlA@3.5V
750nA @ 1V
10msec
Does not need capacitors
22 digits
Can dial more than 22 digits. Redial
disabled if more than 22 digits are entered.
Follows dial pu Ises.
2560A
1.5V to 3.5V
1.5V to 3.5V
1.0V
100IlA@1.5V
500IlA@3.5V
750nA@1V
16msec
Capacitors required between column inputs
and Vss
20 digits
Accepts a maximum of 20 digits. Will not dial
additional digits.
Precedes dial pulses
Application Suggestions
1) In most existing designs, the S2560G will work in place of S2560A without any modifications. Problems may
arise however, if the keyboard bounce time exceeds 10ms. In such a case, the device may interpret a single key
entry as a double key. To avoid this false detection, the keyboard debounce time can be easily increased from
10ms to 20ms by changing the Oscillator Frequency from 2400Hz down to 1200Hz. This is done by changing the
value of the capacitor connected to pin 7 from 270pF to 470pF. To preserve the dialing rate at 10pps and IDP at
aOOms the DRS and lOP pins now must be connected to VDD instead of Vss. Figure 1 shows the implementation
details. Note, that interfacing with X-V keyboard no longer requires capacitors to Vss from column pins.
2) The hookswitch input pin (pin 5) must be protected from spikes that can occur when the phone goes from off·
hook condition to on-hook. Voltage exceeding VDD on this pin can cause the device to draw excessive current.
This will discharge the capacitor across VDD and Vss causing the supply voltage to drop. If the voltage drops
below 1 volt (data retention voltage) the device could lose redial memory. To prevent the voltage on the
hookswitch pin from exceeding VDD , an external diode must be added on the hookswitch pin as shown in Figure 1.
3.19
I
I
Differences between the two devices are summarized below:
2560G
.
-} GOULD
~MII®Semiconductors
S2560G/S2560G1
Figure 1. Transient Protection Technique Using Diode Between Voo and HS
Voo
13
1
2
3
4
5
6
.
8
9
7
0
#
I
I
3
4
1
18
17
16
0,
R,
HE
Ro
CD
S,
J12
MIS
DRS
r!!-
R2
lOP
~
H3
liS
2 R, voo
H.
82560G
MUTE
C2
. HE
IN914
750kQ
750kQ
750kQ
470pF
HOOK SWITCH CONTACT
Co
Vss
po
.1
Vss
3.20
0
~
'\
5
S,
iiP~
C3
c,
R,
~
HE
6
~•.~
Ro
AD
-) GOULD
Tone Ringer
AIMII®Semiconductors
S2561/S2561 A
Features
o CMOS Process for Low Power Operation
o Operates Directly from Telephone Lines with
Simple Interface
o Provides a Tone Signal that Shifts Between Two
Predetermined Frequencies at Approximately 16Hz
to Closely Simulate the Effects of the· Telephone
Bell
o Push-Pull Output Stage Allows Direct Drive, Eliminating Capacitive Coupling and Provides Increased
Power Output
o 50mW Output Drive Capability at 10V
Operating Voltage
o
o
Auto Mode Allows Amplitude Sequencing such that
the Tone Amplitude Increases in Each of the First
Three Rings and Thereafter Continues at the Maximum Level
Single Frequency Tone Capability
General Description
The S2561 Tone Ringer is a CMOS integrated circuit
that is intended as a replacement for the mechanical
telephone bell. It can be powered directly from the
telephone lines with minimum interface and can drive a
speaker to produce sound effects closely Simulating
the telephone bell.
. Pin Configuration
Block Diagram
512HI
SFS
Voo
OSCR,
THe
OSCRm
aSCRa
f-----<> OUTL
~::: o - - - - - - - - - J
'" 0 - - - - - - - - .
f-----<>OUTM
OUTPUT
STA.GE
OStT,
I - - - - - c OUTH
aSCI,
1-----caUTc
OSCR,
DUT ,n
05CT 1I1
DUll
OSCTu
OUTe
A,M
EN
v"
EN
3.21
Vss
VDO
OSCRm
OUTh
aSCRa
OUTe
Vss
~
OUT H
aSCI,
DSCR,
Voa
"
EN
1
-_=.
I
-} GOULD
AIMII®Semiconductors
S2561/S2561 A
Absolute Maximum Ratings:
Supply Voltage ....................................................................................................................................................................... + 12.0V·
Operating Temperature Range ...................................................................................................................................... ODC to + 70 DC
Storage Temperature Range .................................................................................................................................. - 40 DC to + 125DC
Voltage at any Pin ......................................................................................................................................... Vss - O.3V to Voo + O.3V
Lead Temperature (Soldering, 10sec) ....................,.................................................................................................................... 300 DC .
'This device incorporates a l2V internal zener diode across the VOO to VSS pins. 00 NOT connect a low impedance power supply directly
across the device unless the supply voltage can be malntai,;ed below l2V or current limited to <25mA.
Electrical Characteristics:
Specifications apply over the operating temperature and 3.5V';;Vo o to Vss <'12.0V unless otherwise specified.
Symbol
Parameter
Min.
Max.
Units
VDs
Operating Voltage (Voo to Vss)
8.0
12.0
V
Vos
Operating Voltage
4.2
los
Operating Current
10HC
Output Drive
Output Source Current
(OUT H, DUT C outputs)
IOLC
Conditions
Ringing, THC pin open
V
"Auto" mode, non'ringing
!lA
Non·ringing, Voo= 10V, THC pin open, DI pin open or Vss
5
mA
Voo=10V, VO UT =8.75V
Output Sink Current
(OUT H, OUT C outputs)
5
mA
Voo =10V, VOUT'",,0.75V
10HM
Output Source Current (OutM output)
2
mA
Voo=10V, VOUT=8J5V
10LM
Output Sink Current (OUT M output)
2
mA
Voo=10V, VOUT=0.75V
10HL
Output Source Current (OUT L output)
1
mA
Voo= 10V, VOUT=8.75V
lOLL
Output Sink Current (OUT L output)
1
mA
Voo=10V. VOUT=0.75V
500
CMOS to CMOS
VIH
Input Logic "1" Level
VIL
Input Logic "0" Level
VOHR
Output Logic "1" Level (Rate output)
VOLR
Output Logic "0" Level (Rate output)
Voz
Dutput Leakage Current
(OUT H. OUT M outputs in high
impedance state)
'.
OJ Voo
Voo+0.3
V
All inputs
Vss - 0.3
0.3 Voo
V
All inputs
V
10= 10!lA (Source)
0.9 VOO
CIN
Input Capacitance
Mollo
Dscillator Frequency Oeviation
-5
RLOAO
Output Load Impedance Connected Across
OUT H and OUT C
600
0.5
V
1
t
~A
!lA
Voo = 10V. VOUT = OV
Voo=10V, VOUT=10V
7.5
pF
Any pin
+5
%
Fixed RC component values lMQ "Rri. Rti,,5MQ;
1OOkQ" Rrm , Rtm" 750kQ; 150pF" Cro • Cto" 3000pF; 330pF
recommended value of Cro and Cto, supply voltage varied from
9V ± 2V (over temperat~re and unit·unit variations)
Q
IIH, IL
Leakage Current. VIN = Voo or Vss
100
nA
VTH
POE Threshold Voltage
6.5
8
V
Vz
Internal Zener Voltage
11
13
V
10 = 10!lA (Sink)
Tone Frequency Range = 300Hz to 3400Hz
Any input. except DI pin Vaa = 10V
Iz = 5mA
The device power supply should always be turned on before the input signal sources, and the input signals should be turned off
before the power supply is turned off (Vss ';;V I "V DD as a maximum limit). This rule will prevent over·dissipation and possible damage of
the input·protection diode when the device power supply is grounded.
3.22
-} GOULD
AIMII®Semiconductors
52561/52561 A
Functional Description
The S2561 is a CMOS device capable of simulating the
effects of the telephone bell. This is achieved by pro:
ducing a: tone that shifts between two predetermined
frequencies (512 and 640Hz) with a frequency ratio of
5:4 at a 16Hz rate:
Tone Generation: The output tone is derived from a tone
oscillator that uses a 3 pin R-Coscillator design consisting of one capacitor and two resistors_ The oscillator
frequency is divided alternately by 4 or 5 at the shift
rate_ Thus, with the oscillator adjusted for 5120Hz, a
tone signal is produced that alternates between 512Hz
and 640Hz at the shift rate_ The shift rate is derived from
another 3 pin R-C oscillator which is adjusted for a nom- .
inal frequency of 5120Hz_ It is divided down to 16Hz
which.is used to produce the shift in the tone frequency_ It should be noted that in the special case
where both oscillators are adjusted for 5120Hz, it is
only necessary to have one external R-C network for
one oscillator with the other oscillator driven from it.
The oscillators are designed such. that for fixed R-C
component values an accuracy of ± 5% can be obtained over the operating supply voltage, temperature and
unit-unit variations_ See Table 2 for component and frequency selections_ In the single frequency mode, activated by connecting the SFS input to Vss only the·
higher frequency continuous tone is produced by using
a fixed divider ratio of 4 and by disabling the shift
operation_
Ring Signal Detection: In the following description it is
assumed that both the tone and rate oscillators are adjusted for a frequency of 5120Hz. Ringing signal (nominally 42 to 105 VAC, 20Hz, 2 sec on/4 sec off duty cycle)·
applied by the central office between the telephone line
pair is capacitively coupled to the tone ringer Circuitry
as shown in Figure 2. Power for the device is derived
from the ringing Signal itself by rectification (diodes D1
thru D4) and zener diode clamping (Z2)' The signal is
also applied to the EN input after limiting and clamping
by a resistor (R 2) and internal diodes to VDD and Vss
supplies. Internally the signal is first squared up and
then processed thru a 2ms filter followed by a dial pulse
reject filter. The 2ns filter is a two-stage register clocked by a 512Hz signal derived from the rate oscillator by
a divide by 10 circuit. The squared ring signal (typically:
a square wave) is applied to the D input of the first stage·
and also to reset inputs of both stages. This provides
for rejection of spurious noise spikes. Signals exceeding a duration of 2ms only can pass through the filter.
3.23
The dial pulse reject filter is clocked at 8Hz derived
from the rate oscillator by divide by 640 circuit. This circuit is designed to pass any signal that has at least two
transitions in a given 125ms time period. This insures
that signals below 8Hz will be rejected with certainty.
Signals over 16Hz will be passed with certainty and between 8Hz and 16Hz there is region of uncertainty. By
adjusting the rate oscillator to a different frequency the
break pOints of 10Hz and 20Hz the rate oscillator can be
adjusted to 6400Hz. Of course this also increases the
tone shift rate to 20Hz. The action of the dial pulse reject filter minimizes the dial pulse interference during
dialing although it does not completely eliminate it due
to the rather large region of uncertainty associated with
this type of discrimination circuitry. The dial pulse filter
also has the characteristic that an input signal is not
detected unless its duration exceeds 125ms. This insures that the tone ringer will not respond to momentary bursts of ringing less than125 milliseconds in duration (Ref. 1).
a
In logic interface applications, the 2ms filter and the
dial pulse reject filter can be inhibited by wiring the Det.
INHIBIT pin to VDD . This allows the tone ringer to be
enabled by a logic '1' level applied at the "ENABLE" input without the necessity of a 20Hz ring signal.
Voltage Sensing: The S2561 contains a voltage sensing
circuit that enables the output stage and the rate and
tone oscillators, only when the supply voltage exceeds
a predetermined value. Typical value of this threshold is
7.3 volts. This prduces two benefits. First, it insures
that the audible intensity of the output tone is fairly
constant throughout the ringing period; and secondly,
it insures proper circuit operation during the "auto"
mode operation by reducing the power consumption to
a minimum when the supply voltage drops below 7.3
volts. This extends the supply voltage decay time
beyond 4 seconds (off period of the ring signal) with an
adequate filter capacitor and insures the proper functioning of the "amplitude sequencing" counter. It is
important to note that the operating supply voltage
should be well above the threshold value during the
ringing period and that the filter capacitor should be
large enough so that the ripple on .the supply voltage
does not fall below the .threshold value. A supply
voltage of 10 to 12 volts is recommended.
In applications where the tone ringer is continuously
powered and below the threshold level, the internal
threshold can be bypassed by connecting the THC pin
to VDD' The internal threshold can also be reduced by
~:'
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.
I
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-) GOULD
AIMII®Semiconductors
S2561/S2561 A
connecting an external zener diode between the THe
and Voo pins.
rings thereafter are at maximum amplitude. For the proper functioning of the "amplitude sequencing" counter
the device must have at least 4.2 volts across it
throughout the ring sequence. The filter capacitor is so
chosen that the supply voltage will not drop below 4.0
volts during the off period. At the end of a ring sequence when the off period substantially exceeds the 4
second duration, the counter will be reset. This will insure that the amplitude sequencing will start correctly
beginning a new ring sequence. The counter is held In
reset during the "manual" mode operation. This produces a maximum ring amplitude at all times.
Auto Mode: In the "auto" mode, activated by wiring the
"au.to/manual" input to Vss , an amplitude sequencing
of the output tone can Qe achieved. Resistors Rl and
RM are inserted in series with the Outl and OutM outputs, respectively, and paralleled with the Out H output
(Figure 1). Load. is connected across OutH and· Oute
pins.R l is chosen to be higher than RM.ln this manner
the first ring is of the lowest amplitude, second ring is
of medium amplitude and the third and consecutive
Figure 1-8. Output Stage Connected for
Manual Mode Operation
Figure 1-A. Output Stage Connected for
Auto Mode Operation
-------~
.
I .
~
:OUTH
I
I
I
I
II (JSPEAKER
OUTc
_ _ _ _ _ _ _ .JI
Figure 2-A. Typical Telephone Application of
the S2561
n.
VOLUME
CONTROL
TRANSFORMER
Figure 2-8. Typical Telephone Application of
.
the S2561A
, o--jh--.-">-
Voo
18
S2561A
C,
.47~FI20QV
C,
47~F/l5V
D1-D~
1N4004
1,
»14142
12VZENEII
"
"
"
'00
51KQ
"'m
C,
Z(lOKQ
300pF
".
"'.
no 27V Z
18KQ
3.3KQ
100KQ
"
2DDOQ/8QXFMR
9 T027V ZENER
3.24
S1K~!
.y
GOULD
AIMII®Semiconductors
S2561/S2561 A
ring and in the "high impedance" state at all other
times. Buffer H is active beginning the third ring. In the
"manual" mode buffers H, Land C are active at all
times while buffer M is in a high impedance state. The
output buffers are so designed that they can source or
sink 5mA at a VDD of 10 volts without appreciable
voltage drop. Care has been taken to make them symmetrical in both source and sink configurations. Diode
clamping is provided on all outputs to limit the voltage
spikes associated with transformer drive in both directions VDD and Vss.
Output Stage: The output stage is of push-pull type consisting of buffers L, M, Hand C. The load is connected
across pins Out H and Outc (Figure 2). During ringing,
the OutH and Outc outputs are out of phase with each
other and pulse at the tone rate. During a non-ringing
state, all outputs are forced to a known level such as
ground which insures that there is no DC component in
the load. Thus, direct coupling can be used for driving
the load. The major benefit of the push-pull arrangement is increased power output. Four times as much
power can be delivered to the load for the same operating voltage. Buffers M and H are three-state. In the
"auto" mode buffer M is active only during the second
Normal protection circuits are present on all inputs.
Table 1. 52561 (52561 A) Pin/Function Descriptions
Pin
Power (Voo', Vss ')
Number
Function
18,9
These are the power supply pins. The device is designed to operate over
the range of 3.5 to 12.0 volts. A range of 10 to 12 volts is recommended
for the telephone application.
(8,4)
Ring Enable (EN',
EN)
Auto/Manual (AI M)
10, 11, (5)
These pins are for the 20Hz ring enable input. They can also be used for
DC level enabling by wiring the 01 pin to Voo. EN is available for the
S2561 only.
8
"Auto" mode for amplitude sequencing is implemented by wiring this
pin to Vss. "Manual" mode results when connected to Voo. The
amplitude sequencing counter is held in reset during the "manual"
mode.
13,14,15,
These are the push-pull outputs. Load is directly connected across OutH
and Outc outputs. In the "auto" mode, resistors RL and RM can be inserted in series with the OutL and Out Moutputs for amplitude sequencing (see Figure 1).
Outputs (OutL, OutM' Out~, Out~)
(7,6)
Oscillators
Rate Oscillator i
(OSCRj, OSCR~ OSCR~)
2,3,4,
(1, 2,3)
These pins are provided to connect external resistors RRi, RRm and capacitor CRo to form an R-C oscillator with a nominal frequency of 5120Hz.
See Table 2 for components selection.
Tone Oscillator
(OSCTi, OSCT m, OSCTo)
5, 6, 7
These pins are provided to connect external resistors RTi, RT m and
capacitor CT a to form an R-C oscillator from which the tone signal is
derived. With the oscillator adjusted to 512Hz and 640Hz results. See
Table 2 for components selection.
Threshold Control (THC)
17
The internal threshold voltage is brought out to this pin for modification
in non-telephone applications. It should be left open fortelephone applications. For power supplies less than 9V connect to Voo.
3.25
1
- _=.
-} GOULD
~MtI®Semiconductors
S2561/S2561 A
Table 1. (Continued)
Pin
Detector Inhibit (DI)
Number
Function
16
When this pin is connected to Voo. the dial pulse reject filter is disabled
to allow DC level enabling of the tone ringer. This pin should be hardwired to Vss in normal telephone-type applications.
Single Frequency Select (SFS)
When this pin is connected to Vss. only a single frequency continuous
tone is produced as long as the tone ringer is enabled. In normal applications this pin should be hardwired to VOD.
·Pinouts of 8 pin S2561A package.
Table 2. Selection Chart for Oscillator Components and Output Frequencies
Tone/Rate Oscillator
Frequency
(Hz)
RI
Oscillator Components
RM
(kQ)
(kQ)
CD
(pF)
5120
1000
200
330
6400
3200
8000
Rate
(Hz)
Tone
(Hz)
16
10
512/640
640/800
320/400
25
800/1000
fo
fo fa
-
20
Select components in the ranges indicated in the
table of electrical characteristics
-
fa
320
Applications
10
8
The configuration shown will produce a tone with
frequency components of 512Hz and 540 Hz with a shift
rate of approximately 16 Hz and deliver at least 25mW
to an SQ speaker through a 2000Q:SQ transformer. If
"manual" mode is used, a potentiometer may be inserted in series with the transformer primary to provide
volume control. If "automatic" mode is used, resistors
RL and RM can be chosen to provide desired amplitude
sequencing. Typically, signal power
Typical Telephone Application: Figure 2 shows the'
schematic diagram of a typical telephone application
for the 82561 tone ringer. Circuit power is derived from
the telephone lines by the network formed by capacitor
C1 , resistor R1, diode bridge 0 1 through 0 4 , and filter
capacitor C2. C2 is chosen to be large enough so as to
insure that the power supply ripple during ringing does
not fall below the internal threshold level (typ. 7.3 volts)
and to provide large enough decay time during the off
period. A typical value of C2 may be .47/-1F. C1 and Rl are
chosen to satisfy the Ringer Equivalence Number
(REN) specification (Ref. 1). For REN = 1 the resistor
should be a minimum of S.2kQ. It must be noted that the
amount of power that can be delivered to the load
depends upon the selection of C1 and R1•
will be down 20 log
first ring. and down 20 log
RLOAD
dB during the·
dB during the
second ring with maximum power delivered to the load
beginning the third and consecutive rings.
The device is enabled by limiting the incoming ring
signal through resistors R2 , R3 and diodes d 5 and d6 .
Zener diode ZI (typ. 9-27 volts) may be required in certain applications where large voltage transients may
occur on the line during dial pulsing. The internal 2ms
filter and the dial pulse reject filter will suppress any
undesirable components of the signal and will only respond to the normal 20Hz ring signal. Ring signals with
frequencies above 16Hz will be detected.
In applications where dial pulse rejection is not necessary, such as in OTMF telephone systems, the ENABLE
pin may be connected directly to Voo. Oet. Inh pin must
be connected to Voo to allow DC level enabling of the
ringer.
Reference 1. Betl system communications technical reference: PUB 47001 of August
1976. "Electrical Characteristics of Bell System Network Facilities at the Interface with
Voiceband AnciUiary and Data Equipment"-2.S.1. and 2.6.3
3.26
GOULD
AIMII®Semiconductors
DTMF Tone Generator
With Redial
S2569/S2569A
Features
D Wide Operating Supply Voltage Range (2.50-10V)
D Low Power CMOS Circuitry Allows Device Power
to be Derived Directly from the Telephone Lines
D 21 Digit Memory for Redial
D Uses Standard 3x4 (S2569A) or 4x4 (S2569) SPST or
x-v Matrix Keyboard
D The Total Harmonic Distortion is Below Industry
Specification (Max. 7% Over Typical Loop Current
Range)
D Separate Control Keys (S2569) for Disconnect,
Pause, Redial and Flash in Column Four
D Allows Dialing of * and # Keys on S2569. For
S2569A Redial Initiated by * or # Key as First Key
Offhook, * or # can be Dialed After First Key
Offhook.
General Description
The S2569/S2569A are members of the S2559 Tone
Generator family with the added features of Redial,
. Disconnect, Pause and Flash. They produces the 12
dual tones corresponding to the 12 keys located .on the
conventional Touch-Tone® telephone keypad. The
S2569 has separate keys, located in column four, which
initiate the Disconnect(D), Pause(P), Redial(R), and
Flash(F) functions. (Note: column four keys do not
generate tones.) Only the redial feature is available on
the S2569A. Redial on the S2569A is initiated by pressing * or # as the first key offhook.
A voltage reference generated on the chip regulates the
signal levels of the dual tones to meet the recommended telephone industry specifications.
S2569 Pin Configuration
Block Diagram
Voo
TONE
CE
DIS.
C,
H,
C,
H,
C3
H3
Vss
H,
OSC,
MUTE
OSC,
C,
S2569/A Pin Configuration
Voo
Touch-Tone Is a registered trademark of AT&T
3.27
TONE
CE
N.C.
C,
H,
C,
H,
C3
H3
Vss
H,
OSC,
MUTE
DSC,
N.C.
1
- _=.
I
-} GOULD
AIMII®Semiconductors
S2569/S2569A
Absolute Maximum Rating:
De Supply Voltage (Voo-Vss) .............................................................. + 13.5V
Operating Temperature ............................................................. ooe to + 70 0 e
Storage Temperature ........................................................... - 65°e to + 140 0 e
Power Dissipation at 25°e ................................................................ 500mW
Input Voltage ........................................................... Vss - O.6
•
Vref
AKD (Any Key Down or Mute) Output
The AKD output (pin 10) consists of an open drain N
channel device (see Figure 6.) When no key is depressed the AKD output is open. When a key is depressed
Vss
3.38
-) GOULD
AIMII®Semiconductors
525089
Figure 5. Typical Single Tone Output Amplitude Vs Supply Voltage (1\ = 10k)
1
- _=.
800
700
I
t
'"
600
~E
~
.~
'"
500
w
z
:=
400
10
SUPPLY VOLTAGE (VOLTS) ___
Figure 6. AKD output Structure
, - - - - - - ( ) (PIN 101 AKD
AKD
OPEN WITH KEY RELEASED
LOW IMPEDANCE TO Vss
WITH KEY CLOSED.
/>--------1
(FROM INTERNAL
LOGIC)
Vss
3.39
-} GOULD
AIMII®Semiconductors
DTMF Tone Generator
With Binary. Input
S2579
Features
Available in 16 pin Small Outline IC Package for
Space Savings
o Wide Operating Supply Voltage Range
3.0 to 10.0 Volts
o Direct Interface to TTL 4-Bit Logic for Binary Inputs
or Standard X-V Keyboard with Common Terminal
o Uses Low Cost 3.58MHz TV Crystal to Derive
16 Standard Dual Tone Frequencies
o Reference Voltage Generated On-Chip Eliminates
External Circuitry
o Dual Tone and Single Tone Capabilities
o Low Power CMOS Circuitry Allows Telephone Line
Power Operation
o
General Description
The S2579 binary input DTMF generator is a CMOS
integrated circuit specially designed to accept external
logic or microprocessor inputs. The S2579 can also be
programmed to interface to 3x4 or 4x4 keyboard with
common. The 16 standard dual tone frequencies are
derived from a 3.58MHz crystal providing high accuracy and stability. A voltage reference is generated on
the chip which is stable over the operating voltage and
temperature range and regulates the signal levels of
the dual tones to meet the recommended telephone
industry speCification. Other applications for the
S2579 include radio and mobile telephones, remote
control, pOint-of-sale, and credit card verification terminals and process control.
Block Diagram
r-------- -
Pin Configuration
-
Von
MUTE
KIB
CE
c;
TONE
CE
C,
D,
(ii;)
c,
D,
(R,)
C,
D, (Ra)
v"
Do (ii4)
C,
C,
08C;
KEY/BIN
C4
08C,
C4
ALSO AVAILABLE IN 16 PIN sOle
3.40
-} GOULD
AIMII®Semiconductors
52579
Absolute Maximum Ratings:
. DCSupplyVoltage(VDD - Vss) ................................................................................................................... + 10.5V
Operating Temperature ..................................................................................................................... O°C to + 70°C
Storage Temperature ................................................................................................................. - 55°C to + 125°C
Power Dissipation at 25°C ...........................................................:................................................................ 500mW
Input Voltage ................................................................................................................. Vss - 0.6,;;VIN,;;VDD + 0.6
Input/Output Current (except tone output) ..................................................................................................... 15mA
Tone Output Current ........................................................................................................................................ 50mA
1
- _=.
I
Electrical Characteristics:
Specifications apply over the operating temperature range of O°C to
values of measured parameters are specified.
Symbol
(VDD-VSS)
Volts
Parameter/Conditions
+ 70°C unless otherwise noted. Absolute
Min.
Typ.
Max.
Units
3.0
5.0
10.0
V
Supply Voltage
Voo
Tone Output Mode (With Valid Data)
Supply Current
100
Standby (No Key Selected, No
Data, Tone and Mute Unloaded)
5.0
10.0
1.6
2.8
2.0
3.2
mA
mA
Operating (Tone and Mute,
Unloaded)
5.0
10.0
4.0
9.0
5.0
18.0
Pullup Resistor
(Column, Rowand CE Inputs)
5.0
10.0
13
13
mA
mA
Kll
13
13
Rp
Key/BIN Select
Unloaded)
5.0
10.0
OSC
Operating Frequency
5.010.0
25
25
KO
25
25
Kll
Kll
3.58
MHz
Tone Output
VOR
Low Band Alone
5.0
393
481
598
mVrms
dBCR
Ratio of Column to Row Tone
RL = 150ll
5.0
10.0
1.0
2.0
3.0
dB
%DIS
Distortion *
7
10
%
1.6
IOL
Output Sink Current (Pin2' MUTE)
5.010.0
5.0
DST
Data Setup Time
5.0
100
ns
DHT
Data Hold Time
5.0
50
ns
4.8
mA
Logic Inputs
VIL
Input Voltage, Low
5.0
VIH
Input Voltage, High
5.0
0.8
2.0
V
V
'Distortion measured in accordance with the specifications described in Ref. 1 as the "ratio of the total power of all extraneous frequencies in the voiceband above 500Hz accompanying the signal to the total power of the frequency pair".
3.41
I
-} GOULD
AIMII®Semiconductors
S2579
Pin/Function Descriptions
Pin #
. Name
Function
The positive supply voltage pin.
VDO
2
MUTE
. This is an open drain output that turns on, to mute the microphone and speaker when a
key is pressed.
3
4
5
9
Cl
C2
6
Vss
The negative supply voltage pin.
7
8
OSCi
OSC o
A standard 3.58 MHz TV crystal is connected across
these pins. There is an internal resistor.
10
KEY /BIN
11
12
13
14
Do (R4)
D1 (R3)
D2 (112)
D3 (R1)
15
CE
When pin 10 is high these are the 4 column inputs and must be pulled low true. When pin
10 is low, a Iowan Cl provides a single low group tone when CE is valid. If C2 is Iowa
single high group tone will be generated. Pull-up resistors are present on each pin in the
3DKQ range. These are not latching inputs like the row inputs. These pins
(C1 (;2) must be held low for the duration of the single tone.
}
C3
C4
Keyboard/Binary: This pin selects whether the 52579 will be interfaced with a X-Y
keyboard or 4 bit data bus from a microprocessor.
1
When pin 10 is high these are the 4 row inputs and must be pulled low true. When pin 1D
is low these are the binary data inputs for the 16 DTMF tones (See table 1).
Pull-up resistors are on each pin in the 3DKQ range. The data is latched into the 52579
. on the rising edge of CEo
CHIP ENABLE: When this pin is low, all outputs are disabled. When CE and KEY/BIN are
high, any single key depression will output a valid DTMF tone. If KEY/BIN is low, each
time CE is brought high a tone will be output, the value will depend on the levels present
at the DO, Dl, D2, D3, Ci, and C2 input pins during the positive transition of CEo The tone
will continue until CE is brought low. (In the case of single tones
or
must be kept
low for the duration of the tone).
C1 C2
16
TONE
TONE OUT. This output is an emitter follower DC coupled for impedance transformation.
Typically drives a 1DOQ or 150Q resistor.
3.42
-} GOULD
AIMII®Semiconductors
52579
Single Tone Mode
8ingle tones in either the low group frequencies or the
high group frequencies can be generated using the
82579. With pin 10 low, (Binary input) and valid data on
the row inputs, a low input on the C1 or C2 pin will generate the appropriate single row or column frequency
tone (Table 3). When pin 10 is high, a low group tone can
be generated by depressing two digit keys in the appropriate column, i.e., selecting the appropriate column input and two row inputs in that column.
Functional Description
Basic Chip Operation
The dual tone multifrequency(DTMF) signal consists of
linear addition of two voice frequency signals. One of
four signals is selected from a group of frequencies
called "low group" and the other is selected from a
group of frequencies called "high group". The low
group consists of four frequencies; 697, 770, 852 and
941 Hz. The high group consists of four frequencies;
1209, 1336, 1477 and 1633Hz.
Key/BIN
This input is used for programming the 82579 to accept
either logic or keyboard inputs. If the Key/BIN pin is tied
"low", the 82579 will be programmed to accept logic or
binary input levels. Left floating or tied "high" the
82579 will accept keyboard inputs.
Tone Generation
When a valid address is detected, the 82579 programs
the high and low group dividers with appropriate divider
ratios so that the output of these dividers cycle at 16
times the desired high group and low group frequencies. The outputs of the programmable dividers drive
two 8-stage Johnson counters. The symmetry of the
clock input to the two divide by 16 Johnson counters
allows 32 equal time segments to be generated within
each output cycle. The 32 segments are used to digitally synthesize a stair-step waveform to approximate
the sinewave function (see Figure 2). This is done by
connecting a weighted resistor ladder network between the outputs of the Johnson counter, Voo and
VREF . VREF closely tracks Voo over the operating
voltage and temperature range and therefore the peakto-peak amplitude Vp (Voo - VREF) of the stair-step
function is fairly constant. VREF is so chosen that Vp
falls within the allowed range of the high group and low
group tones (see Table 3).
MUTE Output
The 82579 has a N-Channel transistor forthe MUTE output. With no keys depressed, the MUTE output is open.
When a valid address is enabled, the MUTE output goes
low.
Oscillator
The device contains an oscillator circuit with the required
paraSitic capacitances and feedback resistance on chip
so that it is only necessary to connect a standard
3.58MHzz TV crystal across the 08Ci and 08C o terminals to implement the oscillator function.
Figure 1. Standard Telephone Push Button Keyboard
The individual tones generated by the sinewave synthe·
sizer are then linearly added and drive an emitter
follower to allow proper impedance transformation
while preserving signal level.
iC,
i-i~__~
R
Logic Interface
The 82579 will directly interface with TIL and CM08
logic outputs. When programmed for logic inputs, the
82579 requires active "high" logic levels. Pull-up
resistors are. present on the row and column inputs in
the 30KQ range.
,-
'-0--0
--8--0--0
Q-
R
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-
8--0--0-T'~
r----".-o- "
~---O--0--0
I
I
I
3 --0-0 -E--
9-- 0 --9- -P.o-
Keyboard Interface
The 82579 can interface with either the standard telephone pushbutton keyboard (see Figure 1) or an X-V
keyboard with common. The common of the keyboard
must be connected to Vss.
When programmed for keyboard interface, the 82579
requires active "low inputs".
I
[J.0
1 c,
'(
ROil (Contact Resistance).;; Ikn
3.43
I
L1.
.!.)' Cj
R4
COMMON
(CONNECT TO Vssl
--- MECHANICAL
LINKAGE
I
~:I
I
-
.
-) GOULD
AIMII®Semiconductors
52579
Table 1 Functional Truth Table for Logic Interface
Keyboard
Binary Inputs
C1
Inputs
C2
03
01
02
1
0
0
0
.
2
1
0
0
.
1
3
0
0
4
0
1
0
O·
5
1
0
6
0
1
1
*
7
1
1
0
0
8
1
0
9
1
0
0
0
1
1
0
1
1
0
#
1
1
0
A
1
1
0
B
1
1
1
C
1
1
1
D
0
0
0
SINGLE TONE
0
VALID DATA
SINGLE TONE
0
VALID DATA
.
··
··
··
··
··
··
··
··
·
··
·
··
··
··
··
··
··
·
Frequencies Generated
DO
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
.'1.
III
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
FH
FL
• Indicates Normally Open, Internal Pullups Make This a "1" State.
Table 2. Functional Truth Table for Keyboard Interface
Inputs
Number of
Number of
Keys Depressed
Columns Low
Rows Low
X
X
X
None
0
0
One
1
1
Two or more keys in column
1
2 or 3 or 4
Two or more keys in row
2 or 3 or 4
1
Output
chip Enable
Tone
MUTE
0
1
1
0
0
1(OPEN)
1(OPEN)
0
0
0
FL + FH
FH
FL'
then drives two sets of programmable dividers, the high
group and the low group.
Table 3. Comparisons of Specified Vs. Actual Tone
Frequencies Generated by S2579
Chip Enable
ACTIVE
OUTPUT FREQUENCY Hz
%ERROR
INPUT
SPECIFIED
ACTUAL
SEE NOTE
R1
697
699.1
+0.30
R2
770
766.2
-0.49
R3
852
847.4
- 0.54
R4
941
948.0
+ 0.74
C1
1209
1215.9
+ 0.57
C2
1336
1331.7
-0.32
C3
1477
1471.9
-0.35
C4
1633
1645.0
+ 0.73
NOTE: % ERROR DOES NOT INCLUDE OSCILLATOR DRIFT
The 82579 has a chip enable input at pin 15. The chip
enable for the 82579 is active "High". When the chip
enable is "Low", the tone output goes to Vss , the
oscillator is inhibited and the MD"i'E output goes open.
Quartz Crystal Specification (250 C ± 2°C)
Operating Temperature Range: OOC to + 70°C
Frequency ............................... 3.579545MHz
Frequency Calibration Tolerance .................... 02 ± %
Load Capacitance ................................. 18pF
Effective Series Resistance .................. 180 Ohms, max.
Drive Level-Correlation/Operating .......... : .......... 2mW
Shunt Capacitance ............................. 7pF, max.
Oscillation Mode ............................ Fundamental
The oscillator functions whenever a row input is activated. The reference frequency is divided by 2 and
3.44
-) GOULD
AIMII®Semiconductors
S2579
Figure 2. Stairstep Waveform of the Digitally Synthesized Sinewave
- ~:
I
.
(Vee)
1.0
0.9
0.8
>0.
c
....
N
0.7
0.6
::::;
oCt
::;:
a:
'"
0.5
213,415,6,718,9110111112113114115,16 1'718119120121122,23124125,26,27128,29130,31,32
8
2
0.4
0.3
02
D.l
0
TIME SEGMENTS
FIGURE 6. STAIRSTEPWAVEFDRM OF THE DIGITALLY SYNTHESIZED SINEWAVE
3.45
-} GOULD
AIMII®Semiconductors
52579
Figure 3. 52579 Timing Diagram
KEY/BINARY + - KEYBDARD DPERATlDN
-Ll-______L_DG_IC_D_PE_RA_TI_DN_-_-_-_-_-_-_-_-____
-.J
BINARY DATA
~DST
i! X
-+: ~DHT
'----~xl
I
,
I'
I
,
'---------
CE
MUTE
(DPEN DRAIN)
TONE
----.J
DTMF DIGIT
OTMFOIGIT
SINGLE TONE
TEST MDOE
~----~~
L..-_---'
500Hz accompanying the signal to the power of the frequency pair". This ratio must be less than 10% or when
expressed in dB must be lower than - 20dB. (Ref. 1.)
Voiceband is conventionally the frequency band of
300Hz to 3400Hz. Mathematically distortion can be expressed as:
Amplitude/Distortion Measurements
Amplitude and distortion are two important parameters
,in all applications of the digital tone generator. Amplitude depends upon the operating supply voltage as
.well as the load resistance connected on the tone output pin. The on-chip reference circuit is fully operational when the supply voltage equals or exceeds 4
volts and as a consequence the tone amplitude is regulated in the supply voltage range above 4 volts. The load
resistor value also controls the amplitude. If RL is low,
the reflected impedance into the base of the output
transistor is low and the tone output amplitude is lower.
For RL greater than 1KQ the reflected impedance is sufficiently large and highest amplitude is produced. Individual tone amplitudes can be measured by applying
the dual tone signal to a wave analyzer (H-P type 3580A)
and amplitudes at the selected frequencies can be
noted. This measurement also permits verification of
the pre-emphasis between the individual frequency
tones.
Dist.
V (V1)2 + (V2)2 + ..
V (VL)2 + (VH)2
+ (V N)2
where (V1) ... (VN) are extraneous frequency (Le.,
intermodulation and harmonic) components in the
500 Hz to 3400Hz band and VL and VH are the individual frequency components of the DTMF signal.
The expression can be expressed in dB as:
DISTdB == 20 log
.Distortion is defined as "the ratio of the total power of
all extraneous frequencies in the voiceband above
V (V1)2 + (V2)2 + ..
V (VL\2 + (VH)2
+ (V N)2
== 10{ log [(V12 + .. (VN)2j - log [(VL\2 + (VH)2j} ... (1)
3.46
-) GOULD
AIMII®Semiconductors
52579
Figure 4. Test Circuit for Distortion Measurement
,-_ _.,---\-_.!..j v"
T~~~
mm:
CE
-f---,---I SlG
1-'1,,-6
15
C,
SPECTRUM
ANALYZER
c;
0,
52579
C,
Vss
0,
Do
13
x-v
H-PTYPE
PLOTTER
H -PTYPE
3saOA
7D46A
12
XOUT
11
'---------------+---+.---IGNO
Figure 5. A Typical Spectrum Plot
"As a first approximation distortion in dB equals the difference between the amplitude (dB) of the extraneous
component that hC!s the highest amplitude and the
amplitude (dB) of the low frequency signal." This rule of
thumb would give an estimate of - 28dB as distortion
for the spectrum plot of Figure 5 which is close to the
computed result of - 30dB.
DEVICE: S2579
RL = 390Q
TEMP: ROOM
TEST CKT: FIGURE 4
(Voo-Vss): 5V DC FIXED
DUAL TONE: R4 • C1
HORIZONTAL SCALE = O.5KHz/DIV
VERTICAL SCALE = 10dB/DIV
In a telephone application amplitude and distortion are
affected by several factors that are interdependent. For
detailed discussion of the telephone application and
other applications of the S2579 Tone Generator, refer to
the applications note "Applications of Digital Tone
Generator."
Ref. 1: Bell System Communications Technical Reference,
PUB 47001, "Electrical Characteristics of Bell System Network Facilities at the Interface with Voiceband Ancillary and
Data Equipment," August 1976.
3.47
-
-
I
I
RL
YOUT
An accurate way of measuring distortion is to plot a
spectrum of the signal by using a spectrum analyzer
(H-P type 3580A) and an X-Y plotter (H-P type 7046A).
Individual extraneous and signal frequency components are then noted and distortion is calculated by
using the expression (1) above. Figure 5 shows a spectrum plot of a typical signal obtained from S2579 device
operating from a fixed supply of 5Voc and RL = 390Q in
the test circuit of Figure 4. Mathematical analysis of the
spectrum shows distortion to be - 30dB (3.2%). For
quick estimate of distortion, a rule of thumb as outlined
below can be used.
1-:
-) GOULD
Digital Time/Space
Crosspoint Switch
AIMII®Semiconductors
Advanced Product Description
58980
Features
General Description
o
This VLSI ISO·CMOS device is designed for switching
PCM·encoded voice or data, under microprocessor
control, in a modern digital exchange, PBX or Central
Office. It provides simultaneous connections for up to
256 64 kbitlsec channels. Each of the eight serial in~
puts and outputs consist of 32 64 kbits/sec channels
multiplexed to form a 2048 kbitlsec Serial Data Stream.
ST·BUSTM (Serial Telecom Bus)
Compatible
. 0 8·Line x 32·Channel Inputs
o 8·Line x 32·Channel Outputs
o 256 Ports Non·Blocking Switch
o Single Power (+ 5 V)
o Low Power Consumption: 150 mW Typ
o Microprocessor·Controllnterface
o Three·state Serial Outputs
Functional Block Diagram
Pin Configuration
C4i
v..
FOi
DOE
V"
OTA
STIO
sm
sm
sn4
5103
8T04
C4i
5T01
S1I1
sm
STI2
STI3
8TI4
8TI5
8TI6
8m
VOO
SToO
STIO
SERIAL
TO
PARALLEL
CONVERTER
ST02
DATA
MEMORY
PARAllEL
TO
SERIAL
CONVERTER
sn5
Sf05
STI6
ST06
STI7
S107
Fiii
AD
A1
A2
A3
A4
A5
os
RiW
OS
cs
RM
A5/
AD
ill
07/
DO
CSTo
3.48
1
40
2 •
39
3
38
4
37
36 .
5
6
35
7
34
8
33
9
88980. '·32
10
31
11
30
12
29
28
13
14 '
27
15
26
16
25
17
24
18
23
19
22
20
21
CSTo
Doe
SToo
ST01
8T02
8T03
8T04
8T05
8T06
8T07
V88
00
01
02
03
04
05
06
07
CS
-) GOULD
AIMII®Semiconductors
88980
Absolute Maximum Ratings t
Supply Voltage Voo - Vss· .................................................................. + 7V
Voltage on Digital Inputs (Vi) ............................................................... +O.3V
Current at Digital Inputs .................................................................... 40mA
Voltage on Digital Outputs (Vo)· ......................................................... Voo + O.3V
Current at Digital Outputs .............................................................. .' ... 40mA
Storage Temperature ........................................................... ~ 55°C to + 150°C
Power Dissipation ........................................................................... 2W
tExceeding these values may cause permanent damage. Functional operation under these conditions Is not implied.
Recommended Operating Conditions: Voltages are with respect to ground (Vss), unless otherwise stated
Symbol
Parameter
Min.
TypJ
Max.
Units
Operating Temperature
Top
0
70
°C
Positive Supply
Voo
4.75
5.0
5.25
V
Input Voltage
VI
0
V
Voo
nyplcal figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
DC Electrical Characteristics' Clocked operation over recommended temperature and voltage ranges.
Symbol
Parameter
Conditions
Outputs Unloaded
Min.
100
Supply Current
VIH
Input High Voltage
VIL
Input Low Voltage
IlL
Input Leakage
VI between Vss and Voo
Output High Voltage
IOH=10 mA
2.4
IOH
Output High Current
Source Current VO H= 2.4 V
Source Current VOH"':'3.0V
10
8
VOL
Output Low Voltage
IOL =5 mA
IOL
Output Low Current
Sink Current VOL =0.4 V
Sink Current VOL - 2.0 V
loz
High Impedance Leakage
Vas between Vss and Voo
VOH
TypJ
Max.
Units
30
50
mA
2.0
V
0.8
V
10
V
15
12
mA
mA
0.4
7.5
30
5
20
p.A
V
mA
mA
10
p.A
tTypical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
r
Figure 2. Output Test Load
•
Voo
TEST POINT
OUTPUT
PIN
c-L·
0
S1
~S2
~
~
3.49
51 is open circuit except when
testing output levels or high impedance states.
52 is switched to VDD or Vss when
testing output levels or high impedance states.
-) GOULD
AIMII®Semiconductors
S8980
AC Electrical Characteristics:
Capacitances
Symbol
Parameter
Min.
TypJ
Max.
Units
CI
Input Pin Capacitance
8
pF
Co
Output Pin Capacitance
8
pF
Clock Timing (Figures 3 and 4)
Symbol
Parameters
Min.
TypJ
Max.
Units
tCLK
Clock Period'
tCHL
300
150
tcn
Clock Transition Time
244
122
20
ns
Clock Width High or Low
200
100
tFPS
Frame Pulse Set up Time
tFPH
Frame Pulse Hold Time
tFPW
Frame Pulse Width
ns
50
50
ns
ns
244
ns
'Contents of Connection Memory are not lost If the clock stops.
NOTE: Frame pulse is repeated every 125 "s in synchronization with the clock.
tTiming is over recommended temperature and voltage ranges.
:t:Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Figure 3. Frame Alignment
BIT
CELLS
I
I
I
I
I
J
J
I
CHANNEL 0
BIT 7
CHANNEL 31
BIT 0
r---
,
Figure 4. Clock Timing
- - - Ic:HL
--
Ic:LK - - - - -......~I
-- leTT
".----,1
C41
3.50
ns
-) GOULD
AIMII®Semiconductors
58980
Serial Streams (Figures 2, 5, 6, and 7)
Symbol
Parameter
Conditions
Max.
Units
tSAz
SToO/7 Delay - Active to High Z
RL = 1 kn*, CL = 40 pF
80
ns
tSZA
SToO/7 Delay - High Z to active
RL = 1 kO-, CL= 40 pF
100
ns
tSM
SToO/7 Delay - Active to Active
tSOH
SToO/7 Hold Time
tOED
Output Driver Enable Delay
tSID
Serial Input Delay
tSIH
Serial Input Hold Time
tXCH
External Control Hold Time
tXCD
External Control Delay
Min.
TypJ
RL = 1 kn*, CL = 200 pF
125
ns
CL"= 40 pF
100
ns
CL = 200 pF
125
ns
CL = 40 pF
0
CL = 200 pF
0
100
ns
RL = 1 kn*, CL = 200 pF
125
ns
20
ns
75
Figure 5. Serial Outputs and External Control
Figure 6. Output Driver Enable
.
~~~~~~~~~~~~~~~~~~~~~~:
BIT CELL BOUNDARY
ODE
SToO 2.4 V----SToO 2.4 Y·-------- ----- V
~oT07 0.4 Y.-------- ----- ~
to
-
Sl07 0.4 V_--_-_---+....J
1"'-----
tOED
to::: I::: ::~~~~:~~~ ~~~~~~~~ ~~~~~~~~~~:
Figure 7. Serial Inputs
ISlA
1..----IlsOH
~OTOO 2.4 Y--------- -_-_-_-_-_-_-_-_-_ rv_
ST07 0.4 Y .-------~
2.0 VC41
1 . . - - - - . . - [ ISAA
1-----1
0.8 V
IXCH
2.4 Y·-------- --------- rv
CSTo 0.4 Y- ________ ---------~
SliD 2.0 V·-----------------
to
S1170.8 V ------------------
1..-----+1
ns
0
tTiming is over recommended temperature and voltage ranges.
;Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
'High Impedance Is measured by pulling to the appropriate rail with A L, with timing corrected to cancel time taken to discharge C L.
C41 ::::
ns
90
. CL = 50 pF
IXCD
3.51
1
- _=
,
I
RL = 1 kn*, CL =40 pF
CL = 50 pF
I
ns
I
-} GOULD
AMII®Semiconductors
S8980
Processor Bus (Figures 2, and 8)
Symbol
Parameter
Conditions
TypJ
Min.
Max.
Units
tess
Chip Select Set-up Time
20
ns
tRWS
Read/Write Set-up Time
40
ns
tADS
Address Set-up Time
40
tAKD
Acknowledgement Delay
tFWS
Fast Write Data Set-up Time
tSWD
Slow Write Data Delay
tRDS
Read Data Set-up Time
tDHT
Data Hold Time
tRDZ
Read Data to High Impedance
ns
Fast RL = 1 kO·, CL = 130 pF
Slow RL = 1 kO*, CL = 130 pF
60
100
ns
1.2
1.8
p,s
250
ns
ns
30
RL = 1 kO*, CL = 130 pF
0
ns
Read RL = 1 kO·, CL = 130 pF
20
ns
Write
20
ns
40
RL = 1 kO*, CL = 130 pF
90
ns
tCSH
Chip Select Hold Time
20
tRWH
Read/Write Hold Time
15
ns
tfADH
Address Hold Time
15
ns
tAKH
Acknowledgement Hold Time
RL = 1 kO*, CL = 130 pF
ns
0
60
100
tTlmlng is over recommended temperature and voltage ranges.
tTyplcal figures are at 2S'C and are for design aid only; not guaranteed and not subiect to production testing.
'High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge C L.
Figure 8. Processor Bus
tRws
• tRwH
:05. 2.0 V------"V --------- - ----------------------------- - -_-_-__--_-_-_:-_ V_ -_-_-_~-_-_
AD
~
0.8 V------p --------- - ----------------------------- -
1+--.--;--1 IADH'
~~~A~7:~:~::::~
DTA 2.4 V----------.-----------
0.4 V--------------------IRDS I~'I----I
D7
~oo
2.4 V (READ) 2.0 v (WRITE)-:---0.4 V (READ) 0.8 V (WRITEj-----ISWD
-----""y ------------------- - --------- 'Vi"----------/--'l ------------------- - --------- ~--:--1 - - . - - ; - - 1 - IFWS -
3.52
-
IRDZ
--1
ns
-} GOULD
AIMll,Semiconductors
S8980
Pin Function Description
Pin Name
Number
Function
Data Acknowledgement (Open Drain Pulldown Output). This· is the data acknowledgement on the
microprocessor interface. This pin is pulled low to signal that the chip has processed the data.
OTA
STiO-STi7
2-9
ST-BUS™ Input 0 to 7 (Inputs). These are the inputs for the 2048 kbitlsec ST-BUS™ input streams.
Voo
FOi
10
11
Power Input. Positive Supply.
Framing O-Type (Input). This is the input for the frame synchronization pulse for the 2048 kbitlsec ST-BUS™
streams. A Iowan this input causes the internal counter to reset on the next negative transition of C4i.
4.096 MHz Clock (Input). ST-BUS™ bit cell boundaries lie on the alternate falling edges of this clock.
Address 0 to 5 (Inputs). These are the inputs for the address lines on the microprocessor interface.
Data Strobe (Input). This is the input for the active high data strobe on the microprocessor interface.
C4i
AO-A5
12
13-18
19
OS
R/W
Read or Write (Input). This is the input for the read/write signal on the microprocessor interface - high for
read, low for write.
Chip Select (Input). This is the input for the active low chip select on the microprocessor interface.
Data 7 to 0 (Three-state I/O Pins). These are the bidirectional data pins on the microprocessor interface.
20
CS
07-00
21
22-29
Vss
ST07-SToO
30
31-38
ODE
39
CSTo
40
Power Input. Negative Supply (Ground).
ST-BUS™ Output 7 to 0 (Three-state Outputs). These are the pins for the eight 2048 kbitlsec ST-BUS™
output streams.
Output Drive Enable (Input). If this input is held high, the SToO-ST07 output drivers function normally. If this
input is low, the SToO-ST07 output drivers go into their high impedance state. NOTE: Even when ODE is
high, channels on the SToO-ST07 outputs can go high impedance under software control.
Control ST-BUS™ Output (Complementary Output). Each frame of 256 bits on this ST-BUS™ output contains
the values of bit 1 in the 256 locations of the Connection Memory High.
Figure 9. Address Memory Map
A5
A4
A3
A2
A1
AD
Hex Address
Location
0
1
1
X
0
0
X
0
0
X
0
0
X
0
0
X
0
1
00-1F
20
21
Control Register"
Channel ot
Channel 1t
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
•
•
•
•
1
3F
·•
1
·Writing to the Control Register is the only fast transaction.
tMemory and stream are specified by the contents of the Control Regist,er.
3.53
·•
•
Channel31t
1_:
1
-
.
I
-) GOULD
~MII®Semiconductors
S8980
Functional, Description
In recent years, there has been a trend in telephony
towards digital switching, particularly in association
with software control. Simultaneously, there has been
a trend in system architectures towards distributed
processing or multi-processor systems_
In accordance with these trends, Mitel has devised the
ST-BUS™ (Serial Telecom Bus). This bus architecture
can be used both in software-controlled digital voice
and data switching, and for interprocessor com- ~
munications. The uses in switching and in interprocessor communications are completely integrated
to allow for a simple general purpose architecture appropriate for the systems of the future.
The serial streams of the ST-BUS™ operate continuously at 2048 kbitlsec and are arranged in 125 pS
wide frames which contain 32 8-bit channels. Gould
AMI manufactures a number of devices which interface
to the ST_BUS™; a key device being the S8980 chip.
The S8980 can switch data from channels on ST_BUS™
inputs to channels on ST-BUST~ outputs, and simultaneously allows its controlling microprocessor to read
channels on ST-BUS™ inputs or write 'to channels on
ST-BUS™ outputs (Message Mode). To the microproc~
essor,the S8980 looks like a memory peripheral. The
microprocessor can write to the S8980 to establish
switched connections between input ST_BUS™ channels and output ST-BUS™ channels, or to transmit
messages on the output ST_BUS™ channels. By
reading from the S8980, the microprocessor can receivEl, messages from ST_BUS™ input channels or
check which switched connections have already been
established.
By integrating both switching and interprocessor com,
munications, the S8980 allows systems to use
distributed processing and to switch voice or data in
an ST-BUS™ architecture.
Hardware Description
Serial data at 2048 kbitlsec is received at the eight STBUS™ inputs (STiO to STi7), and serial data is transmitted at the eight ST-BUS™ outputs (SToO to ST07). Each
serial input accepts 32 channels of digital data, each
channel containing an 8-bit word which may represent
a PCM-encoded analog/voice sample as provided by a
codec (e.g. Gould AMI's S3507, S3507A, S3506,
S44231-8).
This serial input word is converted into parallel data
and stored in the 256x8 Data Memory. Locations in the
Data Memory are associated with particular channels
on particular ST-BUS™ input streams. These locations
can be read by the microprocessor which controls the
chip.
Locations in the Connection Memory, which is split into high and low parts, are associated with particular
ST-BUS™output streams. When a channel is due to be
transmitted on an ST-BUS™ output, the data for the
channel can either be switched from anST-BUS™ input or it can originate from the microprocessor. If the
data is switched from an input, then the contents of
the Connection Memory Low location associated with
the output channel is used to address the Data
Memory. This Data Memory address corresponds to
the channel on the input ST-BUS™ stream on which
the data for switching arrived. If the data for the output
channel originates from the microprocessor (Message
Mode), then the contents of the Connection Memory
Low location associated with the output channel are
output. directly, and this data is output repetitively on
the channel once every frame until the microprocessor
intervenes.
The Connection Memory data is received, via the Control Interface, at 07 to DO. The Control Interface also
receives address information at A5 to AO and handles
the microprocesor control signals CS, DTA, RIW and
OS. There are two parts to any address in the Data
Memory or Connection Memory. The higher order bits
come from the Control Register, which may be written
to or read from via the Control Interface. The lower
order bits come from th address lines directly.
The Control Register also allows the chip to broadcast
messages on all ST-BUS ™ outputs (Le., to put every
channel into Message Mode), or to split the memory
so that reads are from the Data Memory and writes are
to. the Connection Memory Low. The Connection
Memory High determines whether individual output
channels are in Message Mode, and allows individual
output channels to go into a ,high-impedance state,
which enables arrays of'S8980s to be constructed. It
also controls the CSTo pin. All ST-BUS™ timing is
derived from the two signals C4i and FOL
Software Control
The address lines on the Control Interface give access
to the Control Register directly or, depending on the
contents of the Control Register, to the High or Low
sections of the Connection Memory or to the Data
Memory.
If address line A5 is low, then the Control Register is
addressed regardless of the other address lines (See
Figure 9). If A5 is high, then the address lines A4-AO
3.54
-) GOULD
AIMII®Semiconductors
58980
select the memory location corresponding to channel
0-31 for the memory and stream selected in the Control Register.
The data in·the Control Register consists of mode control bits, memory select bits, and stream address bits
(see Figure 10). The memory select bits allow the Connection Memory High or Low or the Data Memory to
be chosen, and the stream address bits define one of
the ST_BUS™ input or output streams.
Figures 11a and 11b show the effect of the control
register on subsequent operations.
Bit 7 of the Control Register allows split memory
operation - reads are from the Data Memory and
writes are to the Connection Memory Low.
The other mode control bit, bit 6, puts every output
channel on every output stream into active Message
Mode, i.e., the contents of the Connection Memory Low
are output on the ST-BUS ™ output streams once every
frame unless the ODE pin is low. In this mode the chip
behaves as if bits 2 and 0 of every Connection Memory
High location were 1, regardless of the actual values.
If bit 7 of the Control Register is 0, then bits 2 and 0 of
each Connection Memory High location function norFigure 10. Control Register Bits
Bit Name
Split
Memory
Number
7
Message
Mode
(unused)
Memory
Select
Bits
6
Stream
Address Bits
5
4-3
2-0
MODE
CONTROL
BITS
mally (see Figure 12). If bit 2 is 1, the associated STBUS™output channel is in Message Mode; i.e., the
byte in the corresponding Connection Memory Low
location is transmitted on the stream at that channel.
Otherwise, one of the bytes received on the serial inputs is transmitted and the contents of the Connection
Memory Low define the ST_BUS™ input stream and
channel where the byte is to be found (see Figure 13.).
If the ODE pin is low, then all serial outputs are highimpedance. If it is high and bit 6 in the Control Register
is 1, then all outputs are active. If the ODE pin is high
and bit 6 in the Control Register is 0, then the bit 0 in
the Connection Memory High location enables the
output drivers for the corresponding individual STBUS™ outputstream and channel - bit 0 = 1 enables
the driver and bit 0 = 0 disables it (see Figure 12).
Bit 1 of each Connection Memory High location (see
Figure 12) is output on the CSTo pin once every frame.
To allow for delay in any external control circuitry the
bit is output one channel before the corresponding
channel on the ST-BUS™ streams, and the bit for
. stream 0 is output first in the channel; e.g., bit 1s for
channel 9 of streams 0-7 are output synchronously
with ST-BUSTM channel 8 bits 7-0.
(UNUSED)
MEMORY
SELECT
BITS
STREAM
ADDRESS
BITS
Function
When 1, on subsequent operations all reads are from the Data Memory and all writes are to the Connection
Memory, except when the Control Register is accessed. When 0, the Meinory Select Bits specify the
memory for subsequent operations. In either case, the Stream Address Bits select the subsection of the
memory which is made available.
When 1, the contents of the Connection Memory Low are output on the Serial Output streams except when
the ODE pin is low. When 0, the Connection Memory bits for each channel determine what is output.
0-0 - Reserved for testing
0-1 - Data Memory
1-0 - Connection Memory Low
1-1 - Connection Memory High
The number expressed in binary notation on these bits refers to the input or output BUSTM stream which corresponds to the subsection of memory made accessible for subsequent operations.
3.55
I
I
1-:
I,
-
.
I
I
-) GOULD
AIMII®Semiconductors
S8980
Figure 11a Control Register: Memory and Mode to Contents
Bil7
Bit 6
Bil5
Bit 4
Bill"
BiIO"
Hex Value"
0
X
0
Bil3
1.
Bi12"
0
X
X
X
08-0F &.28-2F
0
1
0
1
X
X
X
X
48-4F & 68-6F
0
0
X
1
0
X
X
X
10-17 & 30-37
0
1
X
1
0
X
X
X
50-57 & 70-77
0
0
X
1
1
X
X
X
18-1F & 38-3F
0
1
X
1
1
X
X
X
58-5F & 78-7F
1
0
X
0
1
1,
1
0
1
X
X
X
88-8F. A8-AF.
90-97; BO-B7.
98-9F & B8-BF .
1
1
X
0
1
1
1
0
1
X
X
X
C8-CF. E8-EF,
00-07, FO-F7.
D8-DF & F8-FF
Memory
Data
Mode .'
Normal
Message
Connection
Low
Normal
Connection
High
Normal
Message
. Normal
Split
. Message
Figure 11 b Control Register' Contents to Memory and Mode
Bit7
. Bil6
Bit 5
Bit 4
Bit 3
Blt2"
Bii 1*
Bit 0*
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
0
1
L
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
1
0
1
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
.'
'The range of values for bits 0 to 2 corresponds to the ST·BUS™ streams 0 to 7.
NOTE: All other combinations of values for the 8 bits are reserved for testing.
3.56
Hex Value*
08-0F
10'17
18-1 F
28-2F
30,37
38-3F
4B'4F
50-57
5B-5F
6B-6F .
70-77
78-7F
BB-8F
90-97
9B-9F
AB'AF
BO-B7
BB-BF
CB-CF
00-07
DB-OF
EB-EF
FO-F7
FB-FF
Memory
Data
Connection Low
. Connection High
Data
Connection Low .
Connection High
Data
Connection Low
Connection High
Data
Connection Low
Connection High
Split
Split
Split
Split
Split
Split
Split
Split
Split
Split
Split
split
Mode
Normal
Normal
Normal
Normal
Normal
Normal
Message
Message
Message
Message
Message
Message
Normal
.. Normal
Normal
.. Normal
Normal
Normal
Message
Message
Message
Message
Message
Message
-} GOULD
AIMII®Semiconductors
58980
Figure 12. Connection Memory High Bits
STREAM
ADDRESS
BITS
(, I~I
Bit Name
Message
Channel
Number
2
CHANNEL
ADDRESS
BITS
'I
4
A
I I I I
3
2
1
0
I
Function
When 1, the contents of the corresponding location in Connection Memory Low are output on the location's
channel and stream. When 0, the contenst of the corresponding location in Connection Memory Low act as
an address for the Data Memory and so determine the source of the connection to the location's channel and
stream.
CSTo Bit
1
This bit is output on the CSTo pin one channel early. The CSTo bit for stream 0 is output first.
Output
Enable
0
If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the output driver for the location's channel and stream. This allows individual channels on individual streams to be made highimpedance, allowing switching matrices to be constructed. A 1 enables the driver and a 0 disables it.
Figure 13. Connection Memory Low Bits
PER CHANNEL
CONTROL BITS
NO CORRESPONDING MEMORY
THESE BITS GIVE Os IF READ
A
( I I I I
7
6
5
4
3
Y'I~I'l
Bit Name
Stream
Address
Bits·
Number
7-5·
Function
The number expressed in binary notation on these 3 bits is the number of the BUSTM stream for the source of
the connection. Bit 7 is the most significant bit. E.G., if bit 7 is 1, bit 6 is 0 and bit 5 is 0, then the source of
the connection is a channel on STi4.
Channel
Address
Bits·
4-0·
The number expressed in binary notation on these 5 bits is the number of the channel which is the source of
the connection. (The BUSTM stream where the channel lies is defined by bits 6 and 5.) Bit 4 is the most
significant bit. E.g., if bit 4 is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.
*If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and
stream associated with this location. Otherwise the bits are used as indicated to define the source of the connection which is output on the channel and
stream associated with this location.
3.57
1_:
1
-
.
I
I
-) GOULD
AIMII®Semiconductors
58980
input Dc originating from the bottom S8980, which generates the appropriate signals from an output channel. in
Message Mode. This architecture optimizes the messaging capability of the line circuit by building signaling logic,
e.g., for on-off hook detection, which communicates ~n
an ST-8USTM output. This signaling ST-8USTM output IS
monitored by a microprocessor (not shown) through an
ST-8USTM input on the bottom S8980.
Applications
Use in a Simple Digital Switching System
Figures 14 and 15 show how S8980s can be used with
S8970 and S3507A to form a simple digital switching system. Figure 14 shows the interface between the ~~980s
and the filter/codecs. Figure 15 shows the position of
these components in an example architecture.
The S3507A filter/codec and S8970 line interface in Figure 14 receives and transmits digitized voice signals on
the ST-BUSTM input DR, and the ST-8USTM output Ox,
respectively. These signals are routed to the ST-BUSTM
inputs and outputs on the top S8980, which is used as a
digital speech switch.
The S8970 and S3507A are controlled by the ST-8USTM
Figure 15 shows how a simple digital switching
system may be designed using the ST_BUS™ architecture. This is a private telephone network with 256 extensions which uses a single S8980 as a speech
switch and a second S8980 ·for communication with
the line interface circuits.
Figure 14_ Example of Typical Interface between 589805, 58970, and S3507A for Simple Digital
Switching System
8100..:b
81iO
S0900
USED AS
SPEECH
SWITCH
88980
...-t-~
7 ' DR
r•
S0900
USED IN
MESSAGE
MODE FOR
CONTROL A'ND
SIGNALING
8100~.
I- . •
81iO
r+
..
C
S3507A
FILTER/CO DEC
AND 58970
LINE INTERFACE
(
,+. _.
SIGNALING
LOGIC
LINE DRIVER
AND
2- TO 4WIRE
CONVERTOR
LINE INTERFACE CIRCUIT WITH 88970 AND
83507A FILTER/CO DEC
88980
3.58
~ GOULD
AIMII®Semiconductors
58980
. Figure 15. Example Architecture of a Simple Digital Switching System
r-;i===~1
....
I
r.t .-
SPEECH
SWITCH
LINE INTERFACE CIRCUIT
WITH CODEC
(e.g. S8970 AND S3507A)
~
LINE 1,
•
I
.I
I
PR~~~~~OR
•
•
•
I
-
REPEATED FOR LINES
2 TO 255
I
,ts
I
_
CONTROL &
SIGNALING
S8980
I
I
S8980 '
CONTROLLING
IIII
f·. I
~~!
~.l-! -I
~
.
3.59
LINE INTERFACE CIRCUIT
WITH CODEC
• _ (e.g. S8970 AND S3507A)
REPEATED FOR LINES
2 TO 255
-) GOULD
.AJMII®Semiconductors
58980
A larger digital switching system may be designed by
cascading a number of S8980s. Figure 16 shows how
four S8980s may be arranged in a non-blocking configuration which can switch any channel on any of the
ST-BUS™ inputs to any channel on the ST-BUS™ outputs.
the limits of the chip's specifications. The RC delay
used with the 393 counters ensures a sufficient hold
time for the FP signal, but the values used may have to
be changed if faster 393 counters become available.
The chip is shown as memory mapped,into the S6802
system. Chip addresses 00-3F correspond to processor addresses 2000-203F. Delay through the address decoder requires the VMA signal to be used
twice to remove glitches. The S6802 board uses a 10KO
pullup on the MR pin, which would have to be incorporated into the circuit if the board was replaced by a
processor.
Application Circuit with 6802 Processor
Figure 17 shows an example of a complete circuit
which may be used to evaluate the chip.
For convenience, a 4 MHz crystal oscillator has been
used rather than a 4.096 MHz clock, as both are within
Figure 16. Four 889808 Arranged in a Non-Blocking 16 x 16 Configuration,
8980
.
IN 0/7
"
A
STiO/7 SToO/7
"
8980
B
4
.
STiO/7 SToO/7
8980
C
IN8/15
STiO/7 S1'00/7
H
8980
D
~
STiO/7 SToO/7
3.60
"
OUT 0/7
OUT 8/15
GOULD
~MII®Semiconductors
S8980
Figure 17. Application Circuit with 6802
II56802
07·00
I
A15·AO
(--RIW
SYSTEM
I
I-- MR
I
I-- VMA
1
lr
I
I
I
I
~
I
I--El
I
OTA
STlO
STI1
STl2
STl3
ST14
STl5
STl6
1
2
3
4
5
6
7
8
sm 9
VOO- 10
FOI- 11
C41- 12
AO- 13
A l - 14
15
16
A 4 - 17
A 5 - 18
DS 19
20
RIW -
2D kll
5V
5V -
rri
411=
1.
40
CSTo
39 -:- ODE
38
SToO
37
STol
36
ST02
35
ST03
34
STo4
33
ST05
32
ST06
31
ST07
30 t-- VSS
29 t-- DO
28 t-- 01
27 I- 02
26 I- 03
25
24 t-- 05
23 t-- 06
22 t-- 07
21 t-- CS
-
sa9ao
~~=
-
C41oV -
oV-
1
2
3
4
5
6
7
SM
74
LS
393
I
5V
I
I
I
I
I
-
OV
14 t- 5 V
13(--121- 0 v
11
10
'9
8
I
I
I
I
I
~
510 \I
CS
OV
C41
oV
FOI
oV
-
OV -
OV
OV
1
2
3
4
5
6
7
-
SM
74
LS
393
14
13
12
11
10
9
8
r
5v
1!::-
100 pF
A9
A8
A7
OV
OV
1
2
3
4
5
6
7
8
OV
1-04
I
:-
1
2
3
4
5
6
7
8
A12
All
Al0
OV
OV
oV
-
~
1
A15
2
A14
A13 • 3
4
OV
5
OV
6
VMA
7
oV • 8
1
2
3
4
5
6
7
8
A6
VMA
oV
oV
oV
oV
1
2
3
4
5
6
7
8
9
10
20
19
MD
74
SC
240
18
17
10 1
l-'VV\.
II JI.
3.61
MO
74
SC
238
MD
74
SC
238
MO
74
SC
238
III-
5V
0V
MR -
I-
5V
16
12
11
'Mil
-
15
14
13
4 MHZ
I
MO
74
SC
238
16
15
14
13
12
11
10
9
I-
5V
t---
- ~:
I
.
I
16
15
14
13
12
11
10
9
I-
5V
16
15
14
13
12
11
10
9
I-
5V
16
15
14
13
12
11
10
9
I-
5V
t-
t---
t---
Digital Time/Space
Crosspoint Switch
-} GOULD
AIMII®Semiconductors
Preliminary Data Sheet
S8981
General Description
This VLSI ISO-CMOS device is' designed for switching PCM-encoded voice or data, under microprocessor control, in a modern digital exchange,
PBX or Central Office_ It provides simultaneous con:
nections for up to 12864 kbit/s channels_ Each of the
four serial inputs and outputs consist of 32 64 kbit/s
channels multiplexed to form a 2048 kbit/s ST-BUSTM
stream,
Features
D ST _BUSTM compatible
D 4-Line x 32-Channel Inputs
D 4-Line x 32-Channel Outputs
D 128 Ports Non-Blocking Switch
D Single Power Supply (+ 5V)
D Low Power Consumption: 150 mW Typ
D Microprocessor-Control Interface
D Three-state Serial Outputs'
Piri Configuration
Block Diagram
STID
.~
STII
.~
STI2 .~
STi3
.1-00
vss
~
t
t
~
FRAME
COUNTER
SERIAL
TO
PARALLEL
CONVERTER
, ,
, ,
VOO
l
,
DOE
t
OUTPUT
MUX
~
...
DATA
MEMORY
1+-1
CONTROL REGISTER
~
I'"
OS
CONTROL INTERFACE
~
I--
CONNECTION
MEMORY
I'"
t,J; •
1"u.a
!:
CS R/W
A5/ OTA 07/
AD
~
-f-. SToD
PARALLEL
TO
SERIAL
CONVERTER
-f-. 8Tol
-f-e STo2
~~
5103
OTA
SliD
STi1
STi2
STi3
IC
Ie
IC
IC
VOO
FOI
C4i
AD
AI
A2
A3
A4
A5
OS
R/W
DO
3,62
1
2
3
4
5
6
7
8
9
10
11
·12
13
14
15
16
17
18
19
20
U
.88981
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
IC
ODE
SToO
STol
ST02
S103
IC
IC
IC
IC
VSS
00
01
02
03
04
05
06
07
cs
.y
GOULD
AIMII®Semiconductors
S8981
Absolute Maximum Ratings
Symbol
Parameter
VDD
VI
Supply Voltage
Voltage at Digital Inputs
II
Current at Digital Inputs
Vo
Voltage on Digital Outputs
10
Current at Digital Outputs
TST
P
Min.
Max.
-0.3
Vss-0.3
7
VDD
Vss-0.3
VDD
+
Units
0.3
40
Storage Temperature
Power Dissipation
-65
V
V
mA
+
0.3
V
40
mA
150
°C
W
2
..
Note: Exceeding these values may cause permanent damage. Functional operation under these conditions IS not Implied.
Recommended Operating Conditions-Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics
Min.
Typ.
Max.
Units
Test Conditions
Symbol
Top
VDD
VI
Operating Temperature
Positive Supply
Input Voltage
0
4.75
5.0
0
70
5.25
°C
V
VDD
V
Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
DC Electrical Characteristics-Clocked operation over recommended temperature and voltage ranges.
Characteristics
Typ.
Max.
Units Test Conditions
Min.
Symbol
IDD
VIH
VIL
Supply Current
30
Input High Voltage
Input Low Voltage
Input Leakage
Output High Voltage
2.4
IDH
Output High Current
10
15
8
12
Output Low Voltage
0.8
V
10
,..A
0.4
10L
Output Low Current
loz
High Impedance Leakage
mA
Outputs unloaded
V
IlL
VOH
VOL
50
2.0
5
7.5
20
30
10
V
mA
VI between Vss and VDD
10H =mA
Source Current. VOH = 2.4V
mA
Source Current. VOH = 3.0V
V
mA
10L =5mA
Sink current. VOL = O.4V
rnA
Sink Current. VOL = 2.0V
,..A
Vo between Vss and VDD
Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Figure 2. Output Test Load
OUTPUT
PIN
81 is open circuit except when
testing output levels or high impedance states.
S2 is switched to Voo or Vss when
testing output levels or high im·
pedance states.
I
-r::
n777-
Cl
3.63
-) GOULD
AIMII®Semiconductors
88981
AC Electrical Characteristics-Capacitances
Symbol
CI
Co
Characteristics
Min.
Typ.
Input Pin Capacitance
Output Pin Capacitance
Max.
Units
pF
pF
Test Conditions
Test Conditions
8
8
AC Electrical Characteristics-clock timing (Figure 3 and 4).
.Min.
Typ-
Max.
Units
tClK
tCHl
tCTT
Clock Period'
Clock Width High or Low
Clock Transition Time
200
100
244
122
20
300
150
tFPS
tFPH
tFPW
Frame Pulse Set Up Time
Frame Pulse Set Up Time.
Frame Pulse Width
50
.50
ns
ns
ns
ns
244
ns
Symbol
. Characteristics
ns
Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing .
• Contents of Connection Memory are not lost if the clock stops:,
Frame pulse is repeated every 125 ms in synchronisation with the clock.
Timing is over recommended temperature and voltage ranges.
Figure 3. Frame Alignment
-
I
I
J
I
I
I
I
BIT
CHANNEL 31
CELLS
CHANNEL 0
BIT 0
BIT 7
-
Figure 4. Clock Timing
2.0V
ICHl
-
IClK
ICTT
O.BV
FOi
2.0V
O.BV
3.64
I
f---
..
-} GOULD
AIMII®Semiconductors
58981
AC Electrical Characteristics-Serial streams (Figure 2, 5, 6 and 7).
Sym·
bol
Characteristics
Max.
Units
tSAl
SToO/3 Delay-Active to High Z
80
ns
RL = 1kQ', CL = 40 pF
tSZA
SToO/3 Delay-High Z to Active
100
125
ns
ns
RI =1kQ', C1 =40pF
RL - 1kQ , !,;L ~ ZUU pI"
tSM
SToO/3 Delay-Active to Active
100
125
ns
ns
CL = 40 pF
CL - 200 pF
tSOH
SToO/3 Hold Time
toED
Output Driver Enable Delay
tSID
tSIH
SeriaJ Input Delay
Serial Input Hold Time
Typ.
Min.
0
0
Test Conditions
C =40 pF
CLD - 200 pF
100
125
ns
ns
20
ns
90
RL = 1kQ' ,CL = 40pF
RL - 1kg" ,CL ~ 200 pF
ns
Figure 6. Output Driver Enable
BIT CELL BOUNDARY
~ :::: ~::::~~~:::::::::::::::::::::
---.
ODE
tSOH
SToO 2.4V· - - - - - -10
*
ST03 O.4V . - - - - - - - IDEO
..
~
I~""----"'~·I
BIT CELL BOUNDARIES
~
2.0V O.BV
tSZA
ISOH
STiD
to
STI3
2.0V· - - - - - -- -- - - -- ~ --O.BV· - - - - -- - - - - - - - - - --
-
3.65
-.
I
I
I
Note: Timing is over recommended temperature and voltage ranges.
Note 2: Typical figures are at 25'C and are for design aid only; not guaranteed and not subject to p'roduction testing.,
"High impedance is measured by pulling to the appropriate rail with CL,with timing corrected to cancel time taken to discharge CL•
Figure 5. Serial Outputs
1_:
1
tSID
-) GOULD
AIMII®Semiconductors
58981
AC Electrical Characteristics1 -Processor Bus (Figure 2 and 8) ,
Symbol
tADS
Characteristics
Chip Select Set-Up Time
Read/Write Set-Up time
Address Set Up Time
tAKO
Acknowledgement Delay
tess
tRws
Min.
20
40
40
I Fast
I Slow
tFWS
Fast Write Data Set-Up Time
tswo
Slow Write Data Delay
Read Data Set Up Time
tRDS
Typ.
Max.
60
1,2
100
Units
ns
ns
ns
ns
",s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,8
30
250
0
20
20
I Read
. . I Write
tDHT
Data Hold Time
tRDZ
tesH
tRWH
tAOH
tAKH
Read Data to High Impedance
Chip Select Hold Time
Read/Write Hold Time ,
Address Hold Time
40
90
60
100
20
15
15
0
Acknowledgement Hold Time
Test Conditions
RI =lkQ*,C =130 pF
RL-lkQ ,t;L - lJU pt-
RL = 1kQ*, CL';; 130 pF
R = lkQ*,CL = 130 pF
Rc = 1kQ*, CL= 130 pF
RL = 1kQ*, CL= 130 pF
Note 1: Timing is over recommended temperature and voltage ranges,
Note 2: Typical figures are at 25'C and are for design aid only: not guaranteed and not subject to production testing,
• High impedance is measured by pulling tothe appropriate rail with Ru with timing corrected to cancel time taken to discharge CL•
Figure 8. Processor Bus
:::: ~~~~~~~~~
-----------~
~.------- Y--~------
less II_ _- - J
RlW
2,OV
0,8V
------~
--------- -
ICSH
-----------'------------------
-----cp _" _____________________________________
V
~ ~~~~~~~~~ ~~~~~~~
1----·.-1
IRWS
IRYIll
tADH
DTA
2.4V
...
----------*---"--------
O.4V - - - - - - - - - - - - - - - - - - - - lADS
07
to
DO
2,4V('ead)2,OV(Write)
0,4V(ReadjO,8VIWrilej
IsWD
3.66
IAKH
.... , . . - - -
-} GOULD
AIMII®Semiconductors
58981
Pin Description
Pin
Label
Description
1
DTA
Data Acknowledgement (Open Drain Pulldown Output)-This is the data acknowledgement on the microprocessor interface. This pin is pulled low to signal that the chip has processed the data.
2-5
STiOSTi3
ST-BUS Input 0 to 3 (Inputs)- These are the inputs for the 2048 kbitls ST-8USTM input streams.
6-9
IC
10
VDD
Power Input-Positive Supply.
11
FOi
Framing O-Type (Input)- This is the input for the frame synchronization pulse for the 2048 kbitls ST-8USTM
streams. A Iowan this input causes the internal counter to reset on the next negative transistion of C4i.
12
C4i
4_096 MHz Clock (Input)-ST-BUSTM bit cell boundaries lie on the alternate falling edges of this clock.
13-18
I
Internal Connections-Must be connected to Voo.
AO-A5
Address 0 to 5 (Inputs)- These are the inputs for the address lines on the microprocessor interface.
19
DS
Data Strobe (Input)-This is the input for the active high data strobe on the microprocessor interface.
20
R/W
21
22-29
30
CS
D7-DO
VSS
Read or Write (Input)- This is the input for the read/write signal on the microprocessor interface-high for
read, low for write.
Chip Select (Input)- This is the input for the active low chip select on the microprocessor interface.
Data 7 to 0 (Three-state 110 Pins)- These are the bidireCtional data pins on the microprocessor interface.
Power Input-Negative Supply (Ground).
Internal Con~ections-Leave pins disconnected.
31-34
IC
35-38
ST03SToO
ST-BUSTM Output 3 to 0 (Three-state Outputs)-These are the pins for the four 2048 kbitls ST-8USTM output
streams.
39
ODE
Output Drive Enable (Input)-If this input is held high, the SToO-ST03 output drivers function normally. If this input is low, the SToO-ST03 output ddvers go into their high impedance state. NB: Even when ODE is high, channels on the SToO-ST03 outputs can go high impedance under software control.
40
IC
Internal Connection-Leave pin disconnected.
Functional Description
In recent years, there has been a trend in telephony
towards digital switching, particularly in association
with software control. Simultaneously, there has
been a trend in system architectures towards distributed processing or multi-processor systems.
In accordance with these trends, MITEL has devised
the ST-BUSTM (Serial Telecom Bus). This bus architecture can be used both in software-controlled
digital voice and data switching, and for interprocessor communications. The uses in switching
and in interprocessor communications are completely integrated to allow for a simple general pur-
pose architecture appropriate for the systems·of the
future.
The serial streams of the ST-BUSTM operate continuously at 2,048 kbitls and are arranged in 125/ls
wide frames which contain 32 8-bit channels. Gould
AMI manufactures a number of devices which interface to the ST-BUSTM; a key device being the S8981
chip.
'
The S8981 can switch data from channels on
ST-BUSTM inputs to channels on ST-BUSTM outputs,
and simultaneously allows its controlling microprocessor to read channels on ST-BUSTM
3.67
- ~:
I
-
I
-} GOULD
AIMII®Semiconductors
S8981
associated with the output channel is used to address the Data Memory. This Data Memory address
corresponds to the channel on the input ST-BUSTM
stream on which the data for switching arrived. If the
data for the output channel originates from the
microprocessor (Message Mode), then the contents
of the Connection Memory Low location associated
with the output channel are output directly, and this
data is output repetitively on the channel once every
frame until the microprocessor intervenes.
The Connection Memory data is received, via the
Control Interface, at 07 to DO. The Control Interface
also receives address information at A5 to AO and
handles the microprocessor control signals CS, DTA,
R/W and OS. There are two parts to any address in the
Data Memory or Connection Memory. The higher
order bits come from the Control Register, which
may be written to or read from via/he Control Interface. The lower order bits come from the address
lines directly.
The Control Register also allows the chip to broadcast message on all ST-BUSTM outputs (I.e., to put
every channel into Message Mode), or to split the
memory so that reads are from the Data Memory and
writes are to the Connection. Memory Low. The Connection Memory High determines whether individual
output channels are in Message Mode, and allows individual output channels to go into a high-impedance
state which enables arrays of S8981 s to be constructed.
All ST-BUSTM timing is derived from the two signals
C4i and FOL
Software Control
The Address Lines on the Control Interface give ac,
cess to the Control Register directly or, depending
on the contents of the Control Registerto the High or
inputs or write to channels on ST-BUSTM outputs
(Message Mode.) To the microprocessor, the S8981
looks like a memory peripheral. The microprocessor
can write to the S8981 to establish switched connec-,
tions between input ST-BUSTM channels and output
ST-BUSTM channels, or to transmit message on output ST-BUSTM channels. By reading from the S8981,
the microprocessor can receive messages from STBUSTM input channels or check which switched connections have already been established.
By integrating both switching and interprocessor
communications, the S8981 allows systems to use
distributed processing and to switch voice or data in
an ST·BUSTM architecture.
Hardware Description
Serial data at 2048 kbit/s is received at the four STBUSTM inputs (STiO to STi3), and serial data is
transmitted at the four ST-BUSTM outputs (SToO to
ST03). Each serial input accepts 32 channels of
digital data, each channel containing an 8-bit word
which may represent a PCM-encoded analogiVoice
sample as provided by a codec (such as the S3507).
This serial input word is converted into parallel data
and stored in the 128x8 static Data Memory. Loca·
tions in the Data Memory are associated with particular channels on particular ST-BUSTM input
streams. These locations can be read by the microprocessor which controls the chip.
Locations in the Connection Memory, which is split
into high and low parts, are associated with particular ST-BUSTM output streams. When a channel is
due to be transmitted on an ST-BUSTM output, the
data for the channel can either be switched from an
ST-BUSTM input or it can originate from the microprocessor. If the data is switched from an input, then
the contents of the Connection Memory Low location
A5
A4
A3
A2
A1
AD
HEX ADDRESS
LOCATION
0
1
1
X
X
X
X
X
0
0
0
0
0
0
0
0
1
00-1 F
20
21
Control RegisterChannelOt
Channel 1t
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
•
o.
•
•
•
1.
•
•
•
•
3F
Channel 31t
•
•
'Wrltlng to the Control Register is the only fast transaction.
tMemory and stream are specified by the contents of the Control Register.
3.68
-) GOUL[]
AIMII®Semiconductors
S8981
Low sections of the Connection Memory or to the Data
Memory.
If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Figure
9). If A5 is high, then the address lines A4-AO select the
memory location corresponding to channel 0-31 for the
memory and stream selected in the Control Register.
The data in the Control Register consists of mode control bits, memory select bits, stream address bits, and a
test bit which should be kept at 0 for normal operation
(see Figure 10). The memory select bits allow the Connection Memory High or Low or the Data Memory to be
chosen, and the stream address bits define one of the
ST-BUSTM input or output streams
Figure 10. Control Register Bits
Figure 11 a and 11 b show the effect of the control
register on subsequent operations.
Bit 7 of the Control Register allows split memory
operation- reads are from the Data Memory and
writes are to the Connection Memory Low.
The other mode control bit, bit 6, puts every output
channel on every output stream into active Message
Mode; i.e., the contents of the Connection Memory
Low are output on the ST-BUSTM output streams once
every frame unless the ODE pin is low. In this mode
the chip behaves as if bits 2 and 0 of every Connection Memory High location were 1, regardless of the
actual values.
(UNUSED)
TEST BIT
MEMORY
SELECT
BITS
MODE
CONTROL
BITS
STREAM
ADDRESS
BITS
Function
Pin
Label
7
Split
Memory
When 1, on subsequent operations all reads are from the Data Memory and all writes are to the Connection
Memory, except when the Control Register is accessed. When 0, the Memory Select Bits specify the memory
for subsequent operations. In either case, the Stream Address Bits select the subsection of the memory which
is made available.
6
Message
Mode
When 1, the contents of the Connection Memory Low are output on the Serial Output streams except when the
ODE pin is low. When 0, the Connection Memory bits for each channel determine what is output.
5
(unused)
4-3
Memory
Select
Bits
0-0
0-1
1-0
1-1
2
Test Bit
This bit is used during probe testing. It should be kept at 0 for normal operations.
1-0
Stream
Address
Bits
The number expressed in binary notation on these bits refers to the inputor output ST-BUSTM stream which
corresponds to the subsection of memory made accessible for subsequent operations
- Reserved for testing.
- Data Memory.
- Connection Memory Low.
- Connection Memory High.
3.69
1
-_=.
I
-) GOULD
AIMII®Semiconductors
S8981
Figure 11A. Control Register: Memory and Mode to Contents
MEMORY
MODE
DATA
NORMAL
MESSAGE
CONNECTION
LOW
CONNECTION
HIGH
SPLIT
NORMAL
MESSAGE
NORMAL
MESSAGE
NORMAL
MESSAGE
HEX
VALUE*
BIT
7
BIT
6
BIT
5
08·OB & 28·2B
0
48·4B &.68·6B
10·13 & 30·33
50·53 & 70'73
0
0
0
0
1
18·1 B & 38·3B
58·5B & 78· 7B
88·8B, A8·AB,
90·93, BO·B3,
98·9B & B8-BB
C8-CB, E8-EB,
DO-D3, FO·F3
D8-DB & F8·FB
0
0
1
0
X
X
X
X
X
X
X
1
1
X
0
1
0
1
BIT
4
0
0
BIT
3
1
1
1
0
0
1
1
0
1
1
0
1
1
1
' 1
0
1
1
0
1
1
1
BIT
BIT
BIT
2
0
0
0
0
0
0
0
1*
0*
X
X
.X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
. 'The range of values for bits 0 and 1 corresponds to the TDM streams 0 to 3.
Figure 11 B. Control Register: Contents to Memory and Mode.
BIT
7
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
BIT
BIT
6
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
5
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
BIT
4
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
BIT
3
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
BIT BIT
2
0
0
0
0
.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1*
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0*
HEX
VALUE*
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
08-OB
10-13
18·1 B
28-2B
30-33
38-3B
48-4B
50-53
58-5B .
68-6B
70-73
78-7B
88·8B
90-93
98-9B
A8-AB
BO-B3
B8-BB
C8-CB
DO-D3
D8-DB
E8-EB
FO-F3
F8-FB
BIT
'The range of values for bits 0 and 1 corresponds to the TDM streams 0 to 3.
All other combinations of values for the 8 bits are reserved for testing.
3.70
MEMORY
DATA
CONNECTION
CONNECTION
DATA
CONNECTION
CONNECTION
DATA
CONNECTION
CONNECTION
DATA
CONNECTION
CONNECTION
SPLIT
SPLIT
SPLIT
SPLIT
SPLIT
SPLIT
SPLIT
SPLIT
SPLIT
SPLIT
SPLIT
SPLIT
MODE
LOW
HIGH
LOYV
HIGH
LOW
HIGH
LOW
HIGH
NORMAL·
NORMAL
NORMAL
NORMAL
NORMAL
NORMAL
MESSAGE
MESSAGE
MESSAGE
MESSAGE
MESSAGE
MESSAGE
NORMAL
NORMAL
NORMAL
NORMAL
NORMAL
NORMAL
MESSAGE
MESSAGE
MESSAGE
MESSAGE
MESSAGE
MESSAGE
-) GOULD
AIMII®Semiconductors
58981
If bit 7 of the Control Register is 0, then bits 2 and 0 of
each Connection Memory High location function nor·
mally. If bit 2 is 1, the associated ST·BUSTM output chan·
nel is in Message Mode; i.e., the byte in the cor·
responding Connection Memory Low location is
transmitted on the stream at that channel. Otherwise,
one of the bytes received on the serial inputs is
transmitted and the contents of the Connection
Memory Low define the ST·BUSTM input stream and
channel where the byte is to be found (see Figure 13).
If the ODE pin is low, then all serial outputs are high·
impedance. If it is high and bit 6 in the Control
Register is 1, then all outputs are active. If the ODE
pin is high and bit 6 in the Control Register is 0, then
the bit 0 in the Connection Memory High location
enables the output drivers for the corresponding in·
dividual ST·BUSTM output stream and channel-bit
o = 1 enables the driver and bit 0 = 0 disables it (see
Figure 12).
Figure 12. Connection Memory High Bits
NO CORRESPONDING MEMORY
-THESE BITS GIVE 0s IF READ.
PER CHANNEL
CONTROL BITS
r
Pin
Label
2
Message
Channel
Description
When 1, the contents of the corresponding location in Connection Memory Low are output on the location's
channel and stream. When 0, the contents of the corresponding location in Connection Memory Low act as an
address for the Data Memory and so determine the source of the connection to the location's channel and
stream.
(unused)
o
Output
Enable
If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the output driver for the
location's channel and stream. This allows individual channels on individual streams to be made high·
impedance, allowing switching matrices to be constructed. A 1 enables the driver and a 0 disables it.
3.71
I
1
- _=.
-) GOULD
AIMII®Semiconductors
S8981
Figure 13. Connection Memory. Low Bits
TEST
BIT
.Pin
. 7"
CHANNEL
ADDRESS
BITS
STREAM
ADDRESS
BITS
Label
Description
Test
Bit"
Used during probe test. Keep at unless channel is in the message mode (bit 2 of the corresponding Connection
Memory High location or bit 6 of the Control Register).
6·5"
Stream
Address
Bits"
The number expressed in binary notation on these 2 bits is the number of the ST·BUSTM stream for the source of
the connection. Bit 6 is the most significant bit. E.g., if bit 6 is 1 and bit 5 is 0, then the source of the connection is a channel on STi2. .
'.
.
4·0"
Channel
Address
Bits"
The number expressed in binary notation on these 5 bits is the number of the channel which is the source of
the connection (the ST·BUSTM stream where the, channel lies is. defined by tiits 6 and 5). Bit 4 is the most
significant bit. E.g., if bit 4 is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.
°
"If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and
stream associated with this location. Otherwide the bits are used as indicated to define the source of the connection which is output on the channel and
stream associated with this location.
3.72
-} GOULD
AIMII®Semiconductors
58981
Applications
Use in a Simple Digital Switching System
Figures 14 and 15 show how S8981 s can be used with
S8970 and S3507A to form a simple digital switching system. Figure 14 shows the interface between the S8981s
and the filter/codecs. Figure 15 shows the position of
these components in an example architecture.
The 83507 A filter/codec and 88970 line interface in Figure 14 receives and transmits digitized voice signals on
the ST-8U8™ input DR, and ST-8U8™ output DxD ,
respectively. These signals are routed to the ST-8U8™
inputs and outputs on the top 88981, which is used as a
digital speech switch.
The 88970 and S3507A are controlled by the ST-8USTM
input Dc originates the appropriate signals from an output
channel in Message Mode. This architecture optimizes
the messaging capability of the line circuit by building
signalling logic, e.g., for on-off hook detection, which
communicates on an ST-8U8™ output. This signalling
ST-8USTM output is monitored by a microprocessor (not
shown) through an 8T-8USTM input on the bottom 88981.
Figure 15 shows how a simple digital switching
system may be designed using the 8T-8U8™ architecture. This is a private telephone network with
128 extensions which uses a single 88981 as a
speech switch and a second 88981 for communication with the line interface circuits.
Figure 14. Example of Typical Interface between S8981s, S8970, and S3507A for Simple Digital
Switching System
SToO
STiO
8981
AS
SPEECH
SWITCH
58981
SToO
STiO
SToO
STiD
' - - - _....
SToO
STiO """-~-r
,--+--<,!f:-~
r-+
r .
STOo~
8981 USED
IN MESSAGE
MODE FOR
CONTROL AND
SIGNALLING
S8981
•• 1
SliD
~
SToO
STiO
~
SToO
STiO
~
SToO
STiO
~
4..........
• -<
Ox
DR
Dc
\+. _.
LINE DRIVER
AND
2- TO 4WIRE
CONVERTOR
LINE INTERFACE CIRCUIT WITH S8970 AND S3507A FILTER/CD DEC
~.
-:-+-......
3.73
-} GOULD
AIMII®Semiconductors
S8981
Figure 15. Example Architecture of a Simple Digital Switching System
LINE INTERFACE CIRCUIT
WITH CODEC
(e.g. 88970 AND 83507A)
rI
I
I
8PEECH
SWITCH
•
••
REPEATED FOR LINES
2 TO 32
REPEATED FOR LINES
2 TO 32
S8981
LINE INTERFACE CIRCUIT
WITH CODEC
(e.g. 88970 AND 83507A)
•
REPEATED FOR LINES
34 TO 64
••
REPEATED FOR LINES
34 TO 64
CONTROLLING
MICRO·
PROCESSOR
I
)'21 I
I
I
.J
CONTROL &
81GNALLING
88981
LINE INTERFACE CIRCUIT
WITH CODEC
(e.g. 88970 AND 83507A)
•
•
•
I
}21
I
_.J
I
REPEATED FOR LINES
66 TO 96
REPEATED FOR LINES
66 TO 96
{2
-_ .....
--...,
LINE INTERFACE CIRCUIT
WITH CODEC
(e.g. 88970AND83507A)
3.74
••
•
REPEATED FOR LINES
••
•
REPEATED FOR LINES
98 TO 128
98 TO 128
-} GOULD
AIMII®Semiconductors
S8981
A larger digital switching system may be designed by
cascading a number of 88981s. Figure 16 shows how
four 88981s may be arranged in a non-blocking con-
figuration which can switch any channel on any of the
8T-BU8™ inputs to any channel on the 8T-BU8™ outputs.
- ~:
I
Figure 16. Four 58981 s Arranged in a Non-Blocking 8 x 8 Configuration
.
8981
A
IN 0/3
,
snOl3 STo013
8981
B
Y
,
IN 417
DUT 417
snO/3 SToo/3
~
8981
c
8TIO/3 SToO/3
4
OUT 0/3
H
8981
D
STIO/3 SToO/3
Application Circuit with 56802 Processor
Figure 17 shows an example of a complete circuit
which may be used to evaluate the chip.
For convenience, a 4 MHz crystal oscillator has been
used rather than a 4.096 MHz clock, as both are within
the limits of the chips specifications. The RC delay
used with the 393 counters ensures a sufficient hold
time for the FP signal, but the values used may have
to be changed if faster 393 counters become available.
The chip is shown as memory mapped into the
MEK6802D3 system. Chip addresses 00-3F correspond to processor addresses 2000-203F. Delay
through the address decoder requires the VMA
signal to be used twice to remove glitches. The
MEK6802D3 board uses a 10KQ pullup on the MR pin,
which would have to be incorporated into the circuit
if the board was replaced by a processor.
3.75
GOULD
~MII®Semiconductors
3.76
-} GOULD
AIMII®Semiconductors
88981
A
_
))
0
t/
....
F-.c, ............... ......... ....
)
MILLIMETERS
PIN 1
)
(
I..............................I .... 1·
_1-
L
-IA_
J
H
~_WfiJtmtirl
0
F
t
Mt
C
G
3.77
I
INCHES
DIM
MIN
MAX
MIN
A
50.29
51.31
1.980
2.020
B
14.73
15.24
0.580
0.600
e
2.92
3.94
0.115
0.155
0
0.41
0.51
0.016
0.020
F
1.02
1.52
0.040
2.54 Bse
G
MAX
0.060
0.100 Bse
H
1.14
1.40
0.045
J
0.23
0.30
0.009
0.012
K
2.54
3.81
0.100
0.150
L
15.24 Bse
0.055
0.600 Bse
M
1.02
1.52
0.040
0.060
N
-
10°
-
10°
1
- _=.
I
212A/V.22 Modem Filter With
Equalizers &Analog Loopback
-} GOULD
AIMII®Semiconductors
S35212A
Features
• Bell 21.2A!V.221V.22BIS Compatible
• Usable for Bell 103/113 Applications
• High and Low Band Filters With Compromise
Group Delay Equalizers and Smoothing Filters
• Guard Tone Notch Filters for CCITT
V.22!V.22BIS Applications
• Originate/Answer Operating Modes
• Low Power CMOS: 75 mW Typ.
• Two Uncommitted Operational Amps
.• Choice of Clocking Frequencies: 2.4576 MHz,
1.2288 MHz, or 153.6 kHz
• Call· Progress Tone Filter Capability
• Analog Loopback Test Capability
General Description
The S35212A Modem Filter is a monolithic CMOS integrated circuit. It does the filter/equalizing functions of
Bell 212A and CCITT V.22 (or V.22BIS) modems. The
S35212A includes high band and low band filters. It
features on-chip originate/answer mode selection. Included are compromise amplitude and group delay
equalizers for full compromise equalization. There is a
CCITT notch filter included. It provides rejection at 1800
Hz or 550 Hz; Two uncommitted operational amplifiers
are available to use for gain control or anti-aliasing filters. A continuous low pass filter is also included on the
RX(OUT) pin to act as a smoothing filter. SEL2
switches the S35212A between the normal data mode
Block Diagram
Pin Configuration
T-~
1+
'MT
+
"'0
TIOUT)
SEL2
24
Vss
23
OGNO
RX(IN)
22
ClK2
ClKl
21
T-
R(OUn
20
T+
R-
6 212AIV.22 19
T(OUT)
R+
7
MODEM
FILTER
18
TX(IN)
Von
17
NSEl
SELl
16
NFO
15
TX(OUT)
RX(OUT)
NSEL
TX(IN)
TX(OUT)
S35212A
IiI
RX(IN)
RXIOUT)
AGND
R-~
R+
'lOUT)
Rev
+
"'=1
'"
CLOCK
DIVIDER
eLK1
Alii MODE
11
14
iiI
SELl
NC
12
13
NC
ClK2
SEl2
3.78
10
GOULD
AIMII®Semiconductors
S35212A
and the call progress monitoring mode. For maximum
flexibility the 835212A will operate from a 2.4576 MHz,
1.2228 MHz or 153.6 kHz clock. The 835212A has
Analog Loopback capability to switch the transmit carrier output back through the receive output for testing.
Pin Functional Description
Pin Name
Pin Number
Function
Logic '0' for normal operation. Logic '1' scales down the frequency response by a factor of 6 for Call Progress
Tone Detection through the high-band filter.
SEL2
Vss
RX(lN)
2
Negative Supply Voltage (-5 Volts).
3
Receive Signal Input.
CLKl
4
2.4576 MHz or 1.2288 MHz Clock Input. This input is TTL and CMOS compatible. Leave open when using
CLK2.
1
- _=-
I
I
R(OUT)
5
Receive Uncommitted Op Amp Output (10 kD load maximum).
R-
6
Receive Uncommitted Op Amp Negative Input.
R+
7
Receive Uncommitted Op Amp Positive Input.
VDD
8
Positive Supply Voltage (+5 Volts).
SELl
9
Logic '0' selects 1.2288 MHz. Logic '1' selects 2.4576 MHz clock into Pin 4.
AGND
10
Analog Ground.
MODE (AiCi)
11
Originate/Answer Mode Control Input. A logic '0' sets the device in Originate Mode with the transmit signal in
the low-band and receive signal in the high-band. A logic '1' reverses the connections.
N/C
12
Do not connect to this pin.
N/C
13
Do not connect to this pin.
j[
14
Analog Loopback Control Input. A logic '0' sets the device in Loopback Mode. A logic '1' sets the device in
Normal Mode.
TX(OUT)
15
Transmit Signal Output. This output will drive a 20k load.
NFO
16
Notch Filter Output. This output will drive a 20k load.
NSEL
17
A logic '0' on this input programs the notch filter to reject 500 Hz. A logic '1' programs it to reject 1800 Hz.
TX(IN)
18
Transmit Signal Input.
T(OUT)
19
Transmit Uncommitted Op Amp Output (10 kD load maximum).
T+
20
Transmit Uncommitted Op Amp Positive Input.
T-
21
Transmit Uncommitted Op Amp Negative Input.
CLK2
22
153.6 kHz Clock Input. This input is TTL and CMOS compatible. Leave open when using CLK1.
DGND
23
Digital Ground.
RX(OUT)
24
Receive Signal Output. This output will drive a 20k load.
3.79
-} GOULD
AIMII®Semiconductors
S35212A
Absolute Maximum Ratings
DC Supply Voltage (VDD - Vss ) ........................................................................................................................ + 13.5V
Operating Temperature .......................................................................................................................... O°C to + 70°C
Storage Temperature ..................................................................................................................... -55°Cto +125°C
Analog Input .........................................................................,........................................... Vss -:- 0.3V",V IN ",VDO + 0.3V
D.C. Electrical Operating Characteristics: TA=O°C to +70°C; Voo= +5V±10%; Vss= -5V±10% unless
otherwise specified
Symbol
VIH
Min.
Parameter/Conditions
High Level Logic Input (Pins 1, 9, 11, 17, 14)
SEL2,SEL 1, MODE, NSEL,AL
Typ.
Max.
Units
4
Voo
V
Voo
0.8
V
V
VIH
VIL
High Level Logic Input (Pins 4 and 22) CLK1, CLK2
2.0
Low Level Logic Input (Pins 1,4,9,11,17,22,14)
Vss
RIN
Input Resistance (Pins 3 and 18) RX(lN), TX(IN)
5
CIN
Input Capacitance (Pins 3 and 18) RX(IN), TX(IN)
10
Po
Power Dissipation @ ± 5.25V
75
MQ
pF
150
mW
A.C. System Specifications: TA = 25°C; VDD = + 5V ± 10%; Vss = - 5V ±1 0% unless otherwise specified
Symbol
Va
VMAX
Parameter/Conditions
Min .
. Reference Signal Level Input
Typ.
VRMS
Maximum Signal Level Input
1.4
Bandwidth (both bands; - 3dB)
960
AFO
Gain at Center Frequencies
ICN L
ICN H
NFT
Clock Feedthrough with Respect to Signal Level
Hz
0
+1
dB
Idle Channel Noise-Low Band Filter
22
33
dBrnCO
Idle Channel Noise-High Band Filter
23
33
dBrnCO
TX
RX
Frequency vs. Amplitude Performance of Low- and High- Band Filters
Frequency (Hz) Relative Gain (dB)
Low·Band Filter
Min.
Max.
400
800
1200
1600
1800
2000
2400
2800
Units
VRMS
BW
-1
Max.
1
-35
+1
-1
0
-1.5
+1
-18
-48
-55
-50
Frequency (Hz) Relative Gain (dB)
High·Band Filter
Min.
Max.
800
1200
1600
2000
2400
2800
3200
3500
-2.5
3.80
dB
dB
Notch Filter Response
Frequency (Hz)
-50
-53
-50
+0.5
Low-Band Filter +
1800 Hz Notch Filter
1200 Hz
1800 Hz
+2.5
-10
-20
Low-Band Filter +
550 Hz Notch Filter
1200 Hz
550 Hz
0
0
- 23
-60
Relative Gain (dB)
Min.
Max.
-1
+1
-32
-1
+1
-32
-) GOULD
AIMII®Semiconductors
535212A
Frequency Response Characteristics
The curves on this page illustrate typical filter responses of the S35212A. Figure 1 shows the basic
band split function. This allows full duplex operation
within a voice channel. Figures 2 and 3 show the frequency response of the two filters. These curves include the compromise equalizers. Figures 4 and 5 show
the typical group delay response of the filters and
equalizers.
Figure 1. Typical Amplitude vs. Frequency Plot
-~:
I
-
Figure 3. Typical High-Band Amplitude
vs. Frequency Plot
Figure 2. Typical Low-Band Amplitude
vs. Frequency Plot
i
DD
1-..
1:'
.. '--_-=__....",,....-_.....,,,,.:::-.__-=-__.-:,,±
.._ - - J
-407
fREDUElICl!Hrl
FIIEDUEIICY'Itz)
Figure 5. Typical High-Band Group Delay
vs. Frequency Plot
Figure 4. Typical Low-Band Group Delay
vs. Frequency Plot
!lQQ
~
0
~
-'00
1'''"''--~----=:----'''''''----'-----':::'''-----'
FIIEDUUCY(HI)
fHQUEIIC'(Itz)
3.81
-) GOULD
AIMII®Semiconductors
S35212A
Call Progress Monitoring (Pin 1)
The center frequencies of the two filters shift down to
one-sixth of their original values when pin 1 goes high.
The high-band 2400 Hz filter centers around 400 Hz. Its
passband is approximately 300 to 480 Hz. Precision
dial tone (350/440 Hz) will pass. Ringback (440/480 Hz)
and half of busy/reorder (480/620 Hz) will also pass.
Call Progress Tones
The modem's energy detector software can determine
the cadence or timing of the information to identify the
proper status of the call.
V.22 Notch Filter (Pins 16, 17)
The S35212A includes a notch filter for CCITT V.22
modem operation. This filter notches out the guard tone.
required in V.22 operation. When a V.22 modem
answers, it sends the 2100 Hz answer tone, and then
the 2400 Hz data carrier. It is also required to send
along with the data carrier a guard tone of 1800 Hz.
(Some administrations require 550 Hz.) The purpose of
this tone is to prevent the network from disconnecting:
It provides energy at another point in the spectrum
other than 2400 Hz. This simulates speech and will not
trigger signaling receivers. The tone is only 3 dB below
the data carrier. It is 600 Hz closer to the desired
receive frequency of 1200 Hz, requiring additional filtering to maintain performance.
Frequencies
Timing/Cadence
Condition
Indicated
350+440 Hz
. Can stant Tone
Dial Tone
440+480 Hz
2s8C' on, 4sec off
Audible Ringing
480+620 Hz
0.5sec on, 0.5sec off
(60 ppm)
Line Busy
(Station Busy)
480 + 620 Hz
0.25sec on, 0.25sec off
(120 ppm)
Trunk Busy
(Reorder)
analog signal passes back through the RX(OUT) pin to
the modem. It is demodulated and returned to the
terminal/computer as received data.
Clock Input Selection (Pins 4, 9, 22)
The filter uses one of three possible clock frequencies.
Either 2.4576 MHz or 1 .2288 MHz can be applied to pin
4, CLK1. Pin 9, SEL 1, when high, selects the divider for
2.4576 MHz. When low, it selects the divider for 1.2288
MHz. When using the S35212A with the S35213
modem chip, or if a 153.6 kHz clock is available, the
clock is applied to pin 22, CLK2. Leave pins 4 and 9
open.
Compatibility with Previous Filters (Pins 12, 13, 14)
The S35212A plugs directly into any socket that previ- .
ously held an S35212. It functions exactly as the
S35212 as long as pin 14 is high. Pins 12 and 13
should be left open.
Pin 17, NSEL, when high, provides 1800 Hz notching.
When low, it provides 550 Hz notching.
The output of the low-band filter, through the notch filter,
is always available at pin 16, Notch Filter Out.
Answer/Originate Mode Selection (Pin 11)
Pin 11 selects the filters for the particular mode of
operation. When it is low for the originate mode, the
transmit path is through the low-band filter. Receive is
through the high-band filter, When this pin is high for
the answer mode, the transmit path is through the high-·
band filter. Receive is through the low-band filter. An internal pull-down resistor keeps the chip in the originate
mode when this pin is not connected.
Analog Loopback (ALB) (Pin 14)
When pin 14, AL, is low, the signal at pin 18, TX(IN),
passes through the filter selected by pin 11, Ala, and
out through pin 5, RX(OUT).
Analog Loopback tests the local modem and terminal/
computer hardware and software. Any character sent
from the keyboard echoes back to the screen after
being sent to the modem. It is modulated by the
modem and sent out to the filter. If pin 14 is low, the
3.82
-} GOULD
AIMII®Semiconductors
S35212A
Uncommitted Operational Amplifiers
Figure 6. Anti-Aliasing Low-Pass Filter
for S35212A
The two operational amplifiers are available to use as
gain stages or anti-aliasing filters for the complete
modem circuit. These are CMOS op amps. They do not
have low impedance drive capability. Do not load by
less than 10 kf!. The open loop voltage gain is typically
about 86 dB and the unity gain frequency is about 1.5
MHz with < 5 pF loading. Input offset voltages will be
10 mV or less.
FROM
LINE
'>=--1-"':'" RXIIN)
5 kO
HYBRID
0.0064
~F
low-pass filter constructed around the receive op amp.
It is a critically-damped, unity-gain, Sallen-Key filter with
a cutoff frequency of 6 kHz.
Figure 7. RS-232 Serial Modem for 1200/300bps Asynchronous Operation/Auto-Answer/Auto-Dial Capability
'"2~
LEVEL
-SHIFTER
jjjj
25~
20
r?-
21~
23~
----
CPM
RI
TO
r
1489
8051
Ai
~
-
DAA
f
i
CE
GOULD AMI
S2579
OTMF
DIALER
R1·R4
( ..
Ir'~-
AO·A3
/ ~I
DTMF
TONES
I
0,
TXO
3,.J!!L -
RD
5~
6~
8~
CTS
12J!...
22~
1488
--
'-/
~
Te
LEVEL
SHIFTER
OSR
OCO
GOULD
RXO
SP1
Re
835213
MODEM
AID
SP2
Ai
SP3
elK
~CATE
1if
Fe.
4~~
2.4576MHz
'----
3.83
"m.EPHONE
-
I-
OTR
ROL
-
.
I
Using one of the op amps for anti-aliasing is a good
idea. The receive input to the filters must be band limited to avoid aliasing. The telephone network band
limits the incoming signals from distant modems. Nevertheless, local noise or noise on the modem board itself
can create problems. Figure 6 shows a second-order
RH32C
08·25
1_:
1
GOULD
835212A
FILTER
Re
~
LINE
212A/V.22 Modem Filter
With Equalizers
-} GOULD
AIMII®Semiconductors
Advanced Product Description
S352128
Features
General Description
o Bell 212Atv.221\1.22BIS Compatible
. 0 Usable for Bell 103/113 Applications
o High and Low Band Filters With Compromise
Group Delay Equalizers and Smoothing Filters
o Guard Tone Notch Filters for CCITT
\l.22/\l.22BIS Applications
o Originate/Answer Operating Modes
o Low Power CMOS: 75 mW Typ.
o Two Uncommitted Operational Amps
o Choice of Clocking Frequencies: 2.4576 MHz,
1.2288 MHz, or 153.6 kHz
o Call Progress Tone Filter Capabilities
o Analog Loopback Test Capability
The S35212B Modem Filter is a monolithic CMOS
integrated circuit. It does the filter/equalizing functions of Bell 212A and CCITT V.22 (or V.22BIS)
modems. The S35212B includes high band and low
band filters. .It features on-chip originate/answer
mode selection. Included are compromise amplitude
and group delay equalizers for full compromise
equalization. There isa CCITT notch filter included. It
provides rejection at 1800 Hz or 550 Hz. The NFl pin
switches the notch filter in or out of the low band
filter path. It is in for V.22 and out for 212A operation.
Two uncommitted operational amplifiers are available
to use for gain control or anti-aliasing filters. A con-
Block Diagram
Pin Configuration
NFO
NSEL
TX(IN)
TX(DUT}
SEL2
24
v"
23
DGNII
RX(IN)
22
CLK2
elK1
21
RX(IN)
R)((OUT)
A-:3b
+ +
R
Rev
R(OUT)
Nfl
",
'"
"3
CLOCK
DIVIDER
6 8352128
l(OUT)
7
TX(IN)
212AIV.22
MODEM
FILTER
v..
NSEl
SEll
NFO
AGND
10
lX(oUT)
CPM
AIO MODE
11
A[
elK1
CP.
12
Nfl
SEl1
elK2
SEll
3.84
AA+
T-
T+
R(OUT)
A[
RX(OU1)
-} GOUL[]
AIMII®Semiconductors
8352128
tinuous low pass filter is also included on the
RX(OUT) pin to act as a smoothing filter. 8EL2
switches the 8352128 between the normal data mode
and the call progress monitoring mode. The CPM pin
switches on a second call progress mode. For max-
imum flexibility the 8352128 will operate from a
2.4576 MHz, 1.2228 MHz or 153.6 kHz clock. The
8352128 has Analog Loopback capability to switch
the transmit carrier output back through the receive
output for testing.
\
- ~:
I
-
Pin Number
Pin Name
SEL2
Function
Logic '0' for normal operation. Logic '1' scales down the frequency response by a factor of 6 for Call
Progress Tone Detection through the high-band filter.
Vss
RX(IN)
2
Negative Supply Voltage (- 5 Volts).
3
Receive Signal Input.
CLK1
4
2.4576 MHz or 1.2288 MHz Clock Input. This input is TTL and CMOS compatible. Leave open when
using CLK2.
R(OUT)
5
Receive Uncommitted Op Amp Output (10 kfl load maximum).
R-
6
Receive Uncommitted Op Amp Negative Input.
R+
7
Receive Uncommitted Op Amp Positive Input.
Voo
SEL 1
8
Positive Supply Voltage (+ 5 Volts).
AGND
10
Analog Ground.
MODE (A/O) *
11
Orginatel Answer Mode Control Input. A logic '0' sets the device in Originate Mode with the transmit
signal in the low-band and receive signal in the high-band. A logic '1' reverses the connections.
CPM
12
This pin scales down the frequency response of the low-band filter by 2.5 for Call Progress Detection,
leaving the high-band filter to receive incoming carriers.
9
Logic '0' selects 1.2288 MHz. Logic '1' selects 2.4576 MHz clock into Pin 4.
13
Notch'Filter Insert. A logic '1' inserts the notch filter in the path from the low-band filter.
14
Analog Loopback Control Input. A logic '0' sets the device in Loopback Mode. A logic '1' sets the device
in Normal Mode.
TX(OUT)
15
Transmit Signal Output. This output will drive a 20k load.
NFO
16
Notch Filter Output. This output will drive a 20k load.
NSEL
17
A logic '0' on this input programs the notch filter to reject 500 Hz. A logic '1' programs it to reject
1800 Hz.
NFl
iiI
t
TX(IN)
18
Transmit Signal Input.
T(OUT)
19
Transmit Uncommitted Op Amp Output (10 kfl load maximum).
T+
20
Transmit Uncommitted Op Amp Positive Input.
T-
21
Transmit Uncommitted Op Amp Negative Input.
CLK2
22
153.6 kHz Clock Input. This input is TTL and CMOS compatible. Leave open when using CLK1.
DGND
23
Digital Ground.
RX(OUT)
24
Receive Signal Output. This output will drive a 20k load.
'Internal Pull·downs.
j:lnternal Pull·up.
3.85
-} GOULD
AIMII®Semiconductors
S352128
Absolute Maximum Ratings
DC Supply Voltage (Voo- Vss) .......... : .............................. : ..•.............. + 13.5V
Operating Temperature ........... : ............................................... O°C to + 70°C
Storage Temperature ....•.................................................... -55°Cto + 125°C
Analog Input ................... :: ................................... Vss-'0.3VS;VINS;VOO+O.3V
D.C. Electrical Operating Characteristics: TA=O°Cto +70°C;Voo=+5V ±10%;Vss=-5V ±10% unless
otherwise specified
Symbol
Parameter/Conditions
Min.
Typ.
VIN
High Level Logic Input (Pins 1,4,9,11,12, 13, 14, 17, 22)
2.0
VIL
Low Level Logic Input (Pins 1, 4, 9,11,12,13,14,17,22)
Vss
RIN
Input Resistance (Pins 3 and 18) RX(IN), TX(IN)
5
CIN
Input Capacitance (Pins 3 and 18) RX(IN), TX(IN)
10
Po
Power Dissipation @ ± 5.5V
75
Max.
Units
Voo.
0.8
V
V
MO
pF
150
mW
A.C. System Specifications: T A = 25°C; Voo = + 5V ± 10%; Vss = 5V ± 10% unless otherwise specified.
Symbol
Parameter/Conditions
Min.
Vo
Reference Signal Level Input
VMAX
BW
AFO
ICNL
Gain at Center Frequencies
ICNH
Idle Channel Noise -
NFl
Clock Feedthrough with Respect to Reference Signal Level
Typ.
Max.
Units
1
VRMS
Maximum Signal Level Input
1.4
VRMS
Bandwidth (both bands; -3 dB)
960
Hz
-1
Idle Channel Noise -. Low-Band Filter
High-Band Filter
TX
RX
0
+1
dB
22
33
dBrnCO
23
33
dBrnCO
-40
-60
dB
dB
THDRX
THDlX
Frequency vs. Amplitude Performance of Low· and High· Band Filters
Frequency (Hz) Relative Gain (d B)
Low·Band Filter
Min.
Max.
400
800
1200
1600
1800
2000
2400
2800
-35
+1
-1
0
-1.5
+1
-18
-48
-55
-50
Frequency (Hz) Relative Gain (dB)
High-Band Filter
Min.
Max.
800
1200
1600
2000
2400
2800
3200
3500
-2.5
3.86
Frequency (Hz)
-50
-53
-50
+0.5
Low-Band Filter +
1800 Hz Notch Filter
1200 Hz
1800 Hz
+2.5
-10
-20
Low-Band Filter +
550 Hz Notch Filter
1200 Hz
550 Hz
0
0
Notch Filter Response
Relative Gain (dB)
Min.
Max.
-1
+1
-45
-1
+1
-35
-) GOULD
AIMII®Semiconductors
5352128
Figure 1. Typical Amplitude vs. Frequency Plot
Frequency Response Characteristics
The curves on this page illustrate typical filter responses of the 835212B. Figure 1 shows the basic
band split function. This allows full duplex operation
within a voice channel. Figures 2 and 3 show the frequency response of the two filters .. These curves
include the compromise equalizers. Figures 4 and 5
show the typical group delay response of the filters
and equalizers.
1
- _=.
Call Progress Monitoring (Pins 1, 12)
The 835212B has two methods of doing call progress
monitoring. The first method, in common with the
835212A, uses pin 1, 8EL2, for activation. The second
method, uses pin 12, CPM, for activation .
. Figure 2. Typical Low-Band Amplitude
vs. Frequency Plot
Figure 3. Typical High-Band Amplitude
vs. Frequency Plot
uno
fIIU)UUICY!Hl)
fREOUENCY'Hl)
Figure 5. Typical High-Band Group Delay
vs. Frequency Plot
Figure 4. Typical Low-Band Group Delay
vs. Frequency Plot
¥
;;lDD
il
i.
neOUUICJ(Hll
3.87
-} GOULD
AIMII®Semiconductors
5352128
The center frequencies of the two filters shift doWn to
one-sixth of their original values when pin 1 goes
high. The high-band 2400 Hz filter centers around 400
Hz. Its passband is approximately 300 to 480 Hz.
Precision dial tone (350/440 Hz) will pass. Ringback
(440/480 Hz) and half of busy/reorder (480/620 Hz) will
also pass.
The second method, using pin 12, leaves the highband filter at 2400 Hz. It shifts the low-band filter
down by a factor of 2.5 for a center frequency of 480
Hz. The 620 Hz frequency passes through along with
the others. Because the high-band filter remains at .
2400 Hz, it takes fewer instructions to switch between
call progress tones and data carrier. The receive input
goes to both filters under this condition. Either the
received carrier or the CPM tones are available at the
receive output pin.
The modem's energy detector software can determine the cadence or timing of the information to identify the proper status of the call.
Call Progress Tones
Frequencies
Timing/Cadence
Condition
Indicated
350+440 Hz
Constant Tone
440+480 Hz
2sec on, 4sec off
Audible Ringing
480+620 Hz
0.5sec on, 0.5secoff
'(60 ppm) .
Line Busy
(Station Busy) .
480 + 620 Hz
0.25sec on, 0.25sec off
(120 ppm) .
Dial Tone
Trunk Busy
(Reorder)
high, provides 1800 Hz notching. When low, it provides 550 Hz notching.
The output of the low-band filter, through the notch
filter, is always available at pin 16, Notch Filter Out.
This is the same as the S35212A.
.
Analog Loopback (ALB) (Pin 14)
The second mode also squelches the transmit output
to the line. No tones will come from the originating
modem until answering carrier detection. This is not
necessary with the S35213 modem chip, as it already
has a squelch command for this purpose.
When pin 14, AL, is low, the signal at pin 18, TX(IN),
passes through the filter selected by pin 11, A/5, and
out through pin 5, RX(OUT). An internal pull-up resistor holds this pin high when not used. The S35212B.
will directly replace the S35212A without any circuit
changes.
V.22 Notch Filter (Pins 13, 16, 17)
Analog Loopback tests the local modem and terminal/computer hardware and software. Any character
sent from the keyboard echoes back to the screen
after being sent to the modem. It is modulated by the
modem and sent out to the filter. If pin 14 is low, the
analog signal passes back through the RX(OUT) pin to
themodem. It is demodulated and returned to the terminal/computer as received data.
The S35212B includes a notch filter for CCITT V.22
modem operation. This filter notches out the guard
ton~ required in V.22 operation. When a V.22 modem
answers, it sends the 2100 Hz answer tone, and then
the 2400 Hz data carrier. It is also required to send
along with the data carrier a guard tone of 1800 Hz.
(Some adminstrations require 550 Hz.) The purpose of
this tone is to prevent the network from disconnecting. It provides energy at another point in the spectrum other than 2400 Hz. This simulates speech and
will not trigger signaling receivers. The tone is only 3
dB below the data carrier. It is 600 Hz closer to the
desired receive frequency of 1200 Hz, requiring additional filtering to maintain performance.
.
Pin 13, NFl, when made high, switches in the notch
filter. It goes between the output of the low-band fi Iter
and the receive smoothing filter. Pin 17, NSEL, when
3.88
Clock Input Selection (Pins 4, 9, 22)
The filter uses one of three possible clock frequencies. Either 2.4576 MHz or 1.2288 MHz can be applied
to pin 4, CLK1. Pin 9, SEL 1, when high, selects the
divider for 2.4576 MHz. When low, it selects the
divider for 1.2288 MHz. When using the S35212B with
the S35213 modem chip, or if a 153.6 kHz clock is
available, the clock is applied to pin 22, CLK2. Leave
pins 4 and 9 open.
-) GOULD
AIMII®Semiconductors
5352128
Compatibility with Previous Filters (Pins 12, 13,14)
S35212A. The additional four modes of the S35212B
provide additional call progress monitoring using pin
12. Only five of the 12 modes are normally used.
Analog Loopback testing uses another two modes.
See Table 1 below.
The 835212B plugs directly into any socket that previously held an 835212 or 835212A_ It functions exactly
as the 835212 as long as pins 12, 13, and 14 are open_
Pins 12 and 13 may be low and pin 14 high for the
same results. The 835212B directly replaces the
835212A when pins 12 and 13 are open or low.
Uncommitted Operational Amplifiers
The two operational amplifiers are available to use as
gain stages or anti-aliasing filters for the complete
modem circuit. These are CMOS op amps. They do
not have low impedance drive capability. Do not load
by less than 10 kn. The open loop voltage gain is
typically about 86 dB and the unity gain frequency is
about 1.5 MHz with < 5 pF loading. Input offset
voltages will be 10 mV or less.
Answer/Originate Mode Selection (Pin 11)
Pin 11 selects the filters for the particular mode of
operation. When it is low for the originate mode, the
transmit path is through the low-band filter. Receive
is through the high-band filter. When this pin is high
for the answer mode, the transmit path is through the
high-band filter. Receive is through the low-band
filter. An internal pull-down resistor keeps the chip in
the originate mode when this pin is not connected.
Using one of the op amps for anti-aliasing is a good
idea. The receive input to the filters must be band
limited to avoid aliasing. The telephone network band
limits the incoming signals from distant modems.
Operation Mode Selection
The four control pins, 12 (CPM), 1 (8EL2), 14 (AL), and
11 (AiD) put the 835212B into 12 different operating
modes. The first eight modes are the same as the
Nevertheless, local noise or noise on the modem
board itself can create problems. Figure 6 shows a
Table 1. Operating Modes
Function
Mode
14
11
15
3
24
TX(OUT)
RX(IN)
RX(OUT)
L
L
H
H
H
H
L
L
18
12
CPM
1
SEL2
AI
Aio
TX(lN)
Normal Orig.
Normal Ans.
0
1
0
0
0
0
1
1
0
1
ALB - Orig.
ALB - Ans.
2
3
0
0
0
0
0
0
0
1
L
L
H
L
H
H
L
H
CPM1 - Orig.
Test - N/U
Test - N/U
Test - N/U
4
5
6
7
0
0
0
0
1
1
1
1
1
1
0
0
0
1
0
1
Ll6
H/6
L/6
H/6
Ll6
H/6
Ll6
H/6
H/6
Ll6
H/6
Ll6
H/6
Ll6
H/6
Ll6
Det Ans Tone
Test - N/U
Det CPM Tone
Test - N/U
8
9
10
11
1
1
1
1
X
X
X
X
1
1
0
0
0
1
0
1
-
SaT
SaT
SaT
SaT
Ll2.5+H
Ll2.5
Ll2.5+H
Ll2.5
H
Ll2.5
Ll2.5
H
Notes:
sar
indicates
L
indicates
H indicates
+ indicates
indicates
X indicates
U6 indicates
U25 indicates
that the transmit output is squelched.
the filter with a center frequency of 1200 Hz.
the filter with a center frequency of 2400 Hz.
connection to both filters.
no filter connection.
a "don't care" condition.
the low-band filter scaled down by 6.
the low-band filter scaled down by 2.5.
H
H
Normal operation uses modes 0 and 1 for originate and answer.
Call progress capability uses modes 4, 8, or 10.
Analog Loopback testing uses modes 2 and 3.
Modes 5,6,7,9, and 11 are additional test modes, not normally used.
3.89
-) GOULD
AIMII®Semiconductors
8352128
Figure 6. Anti-Aliasing Low-Pass Filter for 5352128
second·order low·pass filter constructed around the
receive op amp. It is a critically-damped, unity-gain,
Sallen·Key filter with a cutoff frequency of 6 kHz.
Figures 7 and 8 illustrate the signal path during CPM2
modes 8 and 10. The NO, pin 14, is used to select between Call Progress Tones through the low-band filter or
data/voice through the high-band filter.
>'---+---''-- ",(IH)
500
Figure 7. Call Progress Monitor Mode 8: Monitoring Answer Tone/Voice
TX(OUT) 15
18
NO
TX(DUT)
AH.
TONE
OUT
SMOOTHING
FILTERS
Figure 8. Call Progress Monitor Mode 10: Monitoring Call Progress Tones
TX(DUT) 15 NO
TX(DUT)
18
CPM
OUT
SMOOTHING
FILTERS
3.90
Bell 212A Single Chip
1200/300 BPS Modem
-) GOUL[]
AIMII®semiconductors
S35213
Features
D Bell 212A compatible
D Single-chip 1200 bps Full Duplex PSK Modem with
300 bps FSK Fallback Mode
DOn-Chip Scrambler-Descrambler
...
DOn-Chip Async/Sync and Sync/Async Conversion
D Full Analog and Digital Loopback Test Capability
D Carrier Detect and Automatic Gain Control
D 1200Hz Clock Output for Receive and Transmit Data
D Selectable for Operation with Internal or
External Clock
D 2.4576MHz Crystal Controlled with Filter Clock
(153.6kHz) Output Available
D 4SdB (0 to -4SdBm) Dynamic Input Range
D Selectable Character Length (S, 9, 10 or 11 Bits)
D Microprocessor Bus Interface
D CMOS with TTL Compatible Input/Outputs
D 2S-Pin Package
General Description
The S35213 is a single-chip ModulatorlDemodulator
circuit fully compatible with the Bell 212A standard. It
contains a 1200 bps PSK Mod/Demod and a fallback
300 bps FSK ModlDemod. When used with the
S35212A modem filter, all the modulationdemodulation and filtering functions to realize a Bell
212A modem are in place.
The S35213 has on-chip Scrambler and Descrambler,
asynchronous-to-synchronous and synchronous-toasynchronous conversion circuitry. It can accept internally generated clock or external clock. It features a
1200Hz output to optionally clock receive or transmit
digital data to or from the data terminal. Digital and analog
loop back test capability are also provided.
Block Diagram
Pin Configuration
'c
CARRIER OUT
'cCARRIEIIIN
AD
CE
Viii
A,
D,
A,
V"
A,
AL
A,
Re
A,
AGND
C,
835213
212A
8 MODEM
7
FCO
C,
,-_'_"_"_..JI LI__p,_H:H_"_-,
IXl COMMAND lOCA1J'JNS
Iy) READ LOCA11OHS, See page 7
3.91
TXD
DGND
AiD
10
OSC,
Te
11
OSC,
Vss
12
SXC/SP3
SRC/SP1
13
STC/SP2
RXO
14
RCV SYNC
-} GOULD
.AJMII®Semiconductors
535213
General Description (Continued)
Applications
The S35212A1S35213 chip set is designed for standalone as well as integrated modem applications. Both
chips are implemented using Gould's proprietary doublepoly CMOS technology which guarantees low power operation. This makes the chip set ideal for portable or battery
operated systems. It runs from ±5 volt supplies with inputs
and outputs being TTL level compatible.
o
o
o
o
o
Stand-Alone RS-232C Interface Modems
Modem in a Telephone Set with RS-232C Jack
Board Level ",p bus Interface Modems
"Smart Modems"
Data Telemetry Systems
Pin Functions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
Description
14
15
RXD
RCV SYNC
0
0
TTL
TTL
16
STC/SP2
0
TTL
17
SXC/SP3
1/0
TTL
18
19
OS Co
OSCi
0
I
CMOS
CMOS
20
21
22
FCO
DGNO
TXD
0
I
TTL
TTL
23
24
25
26
27
28
Ao
A1
A2
, A3
A4
CE
I
I
I
I
I
I
TTL
TTL
TTL
TTL
TTL
TTL
1m
WR
D~
Voo
iiI.
Re
AGNO
C1
C2
Ala
Te
Vss
SRC/SP1
levels
UO
TTL
I
I
TTL
1/0
TTL
Supply +5V
CMOS
0
I
Analog
-
,-
}
CMOS
0
0
Analog
Supply -5V
0
TTL
-
Function
Read Enable
Write Enable
Data 1/0 - Is high impedance when not selected.
+ 5V supply pin
Analog loopback signal to filter chip S35212A.
Receive carrier input signal
Analog ground pin,
External .1/tFcapacitor for offset compensation connected across these pins.
Answer or originate mode signal to filter chip S35212A.
Transmit carrier output signal drives 20kO load at -7dBm (346mVRMS)
- 5V supply pin.
Synchronous Receive Clock. Received 1200Hz clock (recovered)- The data bit transitions are synchronous with positive edge of SRC. Alternatively, under asynchronous
mode, this pin can be used as a spare line, SP1 (addresses 18,19).
Received digital data to terminal-will be synchronous with SRC in the sync. mode.
Provides a negative pulse 3",sec or 6",sec wide on the leading edge of each received
data bit.
Synchronous Transmit Clock. Transmitted 1200Hz clock. It's rising edge indicates
time to change To data. Alternatively, SP2 (addresses 20,21).,
Synchronous External Clock. External transmit clock from data terminal for sync. in
the external synchronous mode. Alternatively, SP3 output (addresses 22, 23)
Crystal oscillator output pin-capacitor to Vss.
Uses 2.4576 MHz crystal across
Crystal oscillator input pin-capacitor to Vss.
these pins. The capacitors should
be 20pF each.
153.6kHz clock signal to S35212A filter chip.
Digital ground pin.
Digital data input from terminal must be synchronized to STC or SXC when in sync.
mode.
Address Line.
Address Line.
Address Line
Address Line
Address Line
Chip Enable
3.92
-} GOUL[]
AIMII®Semiconductors
535213
Absolute Maximum Ratings
DC Supply Voltage (Voo- Vss) ............................................................. + 13.5V
Operating Temperature ............................................................. O°C to + 70°C
Storage Temperature ........................................................... -55°C to +125°C
Analog Input/Digital Input. ............................................... Vss- O.3V :5VIN:5VOO+ O.3V
D.C. Electrical Operating Characteristics: TA=O°C to +70°C; Voo= +5V (±10%); Vss= -5V (±10%) unless
otherwise specified
Symbol
Typ.
Parameter/Conditions
Min.
Max.
Units
High Level Logic Input (Pins 1-3, 17, 22-28)
V
2.0
Voo
VIH
Low Level Logic Input (Pins 1-3, 17, 22-28)
+0.8
V
VIL
Vss
High Level Logic Outputs (Pins 3, 13-17, 20)
2.4
V
IOH= 100jlA
VOH
Voo
Low Level Logic Outputs (Pins 3,13-17,20)
V
0
+0.4
IOL = 1.6mA
VOL
High Level Logic Outputs (Pins 5, 10)
V
Voo- .3(Voo- VSS)
VOH
Voo
Low
Level
Logic
Outputs
(Pins
5,
10)
V
Vss + .3(Voo-Vss)
VOL
Vss
170
mW
90
Power
Dissipation
@±5.5V
Po
*
A.C. System Specifications:TA=25°C; Voo= +5V; Vss= -5V unless otherwise specified
Typ.
Symbol Parameter/Conditions
Min.
Oscillator Frequency
2.4576
losc
Clock Signal Output to Drive S35212A Filter
153.6
fco
346
291
TOUT Transmit Carrier Output Level into 20KO Load (-7 .O± 1.5dBm)
3.0
RSENS Receive Carrier Input Level
+The power consumption is approximately 60% from the positive supply and 40% from the negative supply.
3.93
Max.
411
775
Units
MHz
KHz
mVRMS
mVRMS
I
I
1
- _=.
,
GOULD
AIMII®Semiconductors
535213
Figure 1. Preliminary Signal Relationships, Serial Data Path, High Speed Mode
ASYNCRONOUS MODE
TXD
==::x'---_____
AXD _ _ _ _
~X'_
~X'-
_______1X'______
_____-----'X'-______x==
----..U- 3
Rev SYNC
U
J.1SEC
U--
11------833/'8Ec (825"SEC)----~1
IN THE ASYNCHRONOUS MOOE SRC, STC, SCT ARE NOT VALID.
IN LOW SPEED MODE iiCii'SVNC FREE RUNS AND IS NOT RELATED TO RECEIVE DATA
SYNCHRONOUS MODE
833jlSEC
I
I
'xc
\
/
\
/
'TC
\
/
\
/
'x.
=:x
X
!
/
\
\
X
IN THE EXTERNAL MODE STC IS DERIVED FROM SXC WHICH IS THE EXTERNAL SYNCHRONIZING SIGNAl. THE DATA SHOULD BE
CHANGING ON THE NEGATIVE EDGES OF STC. IT IS SAMPLED ON THE POSITIVE EDGE OF STC.
=><
"X,
SRC
Rev SYNC
\
---=u-
/
6j..tSEC
833j.1SEC
1
X
X
/
\
U
'I
\
U
SRC IS DERIVED FROM THE TRANSITIONS OF THE INCOMING DATA STREAM. THE NEGATIVE TRANSITIONS OF SRC COINCIDE WITH
THE BIT CHANGES IN RXD. RCVSYNC IS A NEGATIVE·GOING PULSE COINCIDING WITH THE NEGATIVE EDGES OF SRC.
3.94
;-
-) GOULD
AIMII®Semiconductors
535213
j.lP
or j.lC
Interface Timing
Figure 2. Read Timing Characteristics
ADDRESS
-t
~:'
x'---_ I
.
I
\
I
,/
I
CD
i---IeSR
iiii
®
@
IpWR
IEHR+
\
/
@
""'-IOAR-
0
DATA BUS
• ADDRESS MAY BE COINCIDENT DR PRIOR TO
-®
IOHR
VALID DATA
I
I
CE GOING LOW.
Read Cycle
Symbol
Parameter
Min.
Max.
Unit
CD tESR
® tPWR
Enable Setup' Read
70
Pulse Width - Read
250
ns
@
Enable Hold- Read
0
ns
tEHR
CD tDAR
Data Access - Read
®
Data Hold - Read
tDHR
ns
200
20
3.95
ns
ns
-} GOULD
AMII®Semiconductors
S35213
/.Ip or /.IC Interface Timing (Continued)
Figure 3. Write Timing Characteristics
ADDRESS
}
.
\
t
WITH UART AND
DUAL PDRT
REGISTER FILE
{
AO·A4,OO
liii
Wii
TXO
RXO
GDULO
835213
MODEM
T,
R,
GOULD
835212A
FILTER
CE
Rev SYNC
SHC, STC
3
I
CPM
.y_~f-1
AJO
Ai: ClK2 SEl2
AIO
sxc
'"
Ai:
2.4576 MHz
3.100
153.6KHZ
~
J
T,
I--"'-
-
TElEPHDN
LINE
r--
-} GOULD
~MII®Semiconductors
S35213
Figure 6. Apple liE Parallel Interface Example for 12001300 BPS Asynchronous Operation
1
- _=.
I
1'-
-- -------------------------
I
I
I
I
I
I
I
I
I
---;=;1J=. }~~1!,#J.ff".M:".E_~~"I'Ir_=FA=F·==_;=);.·.·1 ~! ~~.~ ~"
j_1
" "
~ ~ ~ I~ I~ a ,; I~ I. I§ ~ n::
~I. ~
• " ••
12 I."
_- T,;·,~~"·:'-,., !~
i----:lN"h
____
.
J
1i!
~
~
1:;
;2
~
~
~
" -"
:f ~ ~ ~ :eo :!' ~
"I~'
...
~
::1
3.101
I:;;
'-11'
"I ."
107msec on Ai will put the device in
the Answer Mode. Similarly (with OTR high) 8H can be
pulled low for >54msec to put the 83531 into the
Originate Mode.
Passthru Mode
With the "Test 0" and "TesI1" lines the 83531 can be
put into the Passthru Mode disabling the handshake
protocol. The transmit and receive functions are enabled but become independent of timing and control.
CD works as usual and the Answer and Originate
Modes are selected manually with Ai and SH.
Abort Mode
There is an automatic abort feature in the 83531 to
avoid tying up a system when there is difficulty
establishing a link. If no carrier is detected within 14
seconds of being put into the answer or originate
mode it will abort the call by turning off OH and
disconnecting the phone line. OSR will also go off
(high). This abort time can be extended by pulsing RTS
low for 1msec before the 14 seconds have elapsed.
This will reset the abort timer. If time does run out OTR
should be pulsed off to. reset the 83531.
Shutdown Mode
8hould the received carrier fall below -48 dBm (approx.)
during data exchange for more than 213msec the
83531 will terminate the call and go on hook, disconnecting the phone line.
Test 0
PIN 7
Test 1
PIN 6
S3531
STATUS
0
1
0
0
NORMAL
PASSTHRU
1 = +5V (VDD )
0= -5V (Vss)
V.21 Mode, CCITT Operation
With the SL pin tied high the 83531 functions in the
CCITT V.21 Mode but performs the same operations
described above. The basic principle is the same but
the frequencies aAd the timings are switched to V.21
specifications. When in V.21 Mode the V.25 answer
tone of 2100Hz will be generated upon answering. 8ee
the timing charts and Table 1 for additional details.
Diagnostic Modes
The 8353"1 has two diagnostic modes for either local or
remote testing. By putting the AL pin high while OTR is
high, the device enters the Analog Loopback Mode.
OH goes low to busy out the phone line. The receive
filter center frequency is switched to the transmit
Table 1. 103/V.21 Mark and Space Frequencies
Transmit Frequency (Hz)
Mode
Bell 103 Originate
Bell 103 Answer
CCITT V.21 Originate
CCITT V.21 Answer
CCITT V.25 Answer Tone
Mark
1270
2225
980
1650
Space
1070
2025
1180
1850
Receive Frequency (Hz)
Mark
2225
1270
1650
980
2100
"(Note that OH only follows RTS. The proper timing for dialing must come from the terminal on the RTS line.)
3.112
Space
2025
1070
1850
1180
N/A
-} GOULD
AIMII®Semiconductors
53531
center frequency and the TC signal is internally connected to the RC input. The transmit signal also
remains available on the TC pin_ Thus any digital data
input at TD is coded and sent out via TC, and at the
same time back through the analog input, decoded,
and out on the RD pin.
By putting the DL pin high the 83531 enters the Digital
Loopback mode. In this mode any data received from
the remote end of the phone line is retransmitted back
to its source and D8R is forced high. The digital or
decoded data is not available at the RD output in this
mode. See Table 2.
Table 2. Control Logic During Diagnostic Modes
Test
Mode
OTR
RTS
Status Lines
OSR
OH
CTS
CO
AL
On
On
On
On
On
On
DL
On
On
Off
On
Off
Off
To establish diagnostic modes in either originate or
answer, establish handshaking in the preferred mode
(originate or answer), then enter diagnostic modes.
Oscillator Details
Quartz Crystal Specification (25°C + 2°C)
Operating Temperature Range ............ O°C to + 70°C
Frequency. . . . . . . . . . . . . . . . . . . . . . . . .. 3.579545MHz
Frequency Calibration Tolerance. . . . . . . . . . . . .. .02 ± %
Load Capacitance .........
. . . . . .. . .. 18pF
Effective Series Resistance . . . . . . . . . . .. 180 Ohms, max.
Drive Level-Correlation/Operating. . . . . . . . . . . . . . .. 2mW
Shunt Capacitance. . . . . . . . . . . . . . . . . . . . . .. 7pF, max.
Oscillation Mode. . . . . . . . . . . . . . . . . . . . . .. Fundamental
External Drive Requirements
To use an
duty cycle,
through a
amplitude
capacitor.
external 3.58MHz clock a TTL level, 50%
square wave can be applied to pin 12, OSCo
.1JLF capacitor. It must have a 2V pop
and be AC coupled through the .1JLF
Applications Circuits
Two applications circuits are illustrated. The first circuit is
for a stand-alone R8-232 interface modem to be used as
a peripheral accessory to a terminal or computer. Plugging into an R8-232 serial port on one side and into a
standard modular phone jackon the other side it is a
stand-alone direct connect modem for operation at rates
up to 300bps.
The second circuit is an add-on modem for building
into a computer and connecting to the internal parallel
buss structure. The ACIA or UART does the parallel-toserial and serial-to·parallel conversion required. The
edge connector is numbered for an Apple II application
but the same interface applies to most JLP systems.
Both circuits are intended for direct connection to the
phone lines. This requires meeting FCC Part 68
requirements for network protection as well as protection of the modem. No suppression components are
illustrated on these examples as the design of the interface will vary depending on the needs of the
designer. After a design is completed it must be subjected to Part 68 certification before sale to the public.
If one wants to avoid the protection/certification
details a certified DAA (Data Access Arrangement)
such as the Cermetek CH1810 can be used instead.
The DAA is designed to handle the phone line interface including the 4-wire to 2-wire function and is
already registered with the FCC.
Whether using a DAA or not, the 83531 requires very
few external components.
Hybrid Function
In the stand-alone circuit the hybrid 4-wire to 2-wire
converter utilizing the dual op amp was configured to
provide 1:1 conversion in each direction. A - 9dBm
voltage level from the Transmit Carrier pin on the
83531 is amplified by the op amp to compensate for
the losses in the 300n matching resistor and the coupling transformer. The transmit carrier is delivered to the
line at - 9dBm. (For CCITT applications this should be
reduced to - 13dBm.)
In the receive direction the loss in the coupling
transformer is compensated for by the other half of the
op amp. If there is a - 20dBm signal across Tip and
Ring then a - 20dBm signal is delivered to the Receive
Carrier pin on the 83531.
The 300n resistor is to provide the proper termination
so that Tip and Ring look like a 600n AC impedance to
the line. The 16Kn resistor from the Transmit Carrier
pin to the inverting input of the receive op amp is to
provide sidetone suppression. The transmit carrier is
provided through the 16Kn resistor 180 0 out of phase
from the transmit carrier presented to the line. Thus,
the transmit carrier is cancelled and presented to the
Recieve Carrier pin on the 83531 at a reduced level.
3.113
I~:
-
.
I
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=:
C/)
c:
CC
CC
.-c
W 0
~' c::
CD
~
MC145406
14
D-
RXii
13
1--=--='---1'---1
12
f-------t=-'----=--j
C/)
...
CD
~
11
10
~
r[ C
...~
Dr
n
CD
»
"C
"2-
+5V
TO CARRIER
INDICATOR
C'i"
a
0'
::J
C/)
n
::r
CD
3
a0'
0...
!='l
~
.f:>.
U1.
Co)
......
i
r
NORMAL ~
+5V
ANALOG LOOPBACK
10K
"5V
10K
103 SWS
+SV
1
V.21
SW1-SWS DIP SWITCH PAK
CJ)
w
w
(,J1
""""
CD
>~
~
"tI
f(l
til
s::
CQ
CQ
~Q
~
PI
~
Dr
g
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"tl
"2.
r)'
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::J
til
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3
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n'
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...
M
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gJ.
~~
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~~
I
~~
....
~~
PI
~~
::J
~-
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a.
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llill§lilii!l
~~~!!~
:!!~!;Iiltl
~~§~~
~1:I!i!~i'l
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~
f::~!
di~~
~eBIl
=
10K
10K
-5V
103 SW5
il'l;;-!lS!
~~;:il:l
CD
ANALOG LOOPBACK
~§. H~
l!ii!lSm
:I>
"tl
"tl
+5V
::l~§i~
+5V
V.21
SW1-SW5 DIP SWITCH PAK
(J)
w
(1J
W
...I.
III
' I
, 'II
iii
r-
~
i
01
c:
5-
![
S'
0
~.
C
-} GOULD
AMII®Semiconductors
S3531
Under ideal conditions 20dB or more of cancellation
might be achieved, but because telephone lines vary
considerably, a cancellation of around 10dB Is a more
realistic number.
AC and DC specifications. The T2112 is much smaller
and lighter because the low end frequency response is
not needed. It is a modem transformer, not a voice
transformer.
The transformer listed is rated to 90mA loop current. To
go to the maximum loop current the Microtran number
would be T5115 for 120mA loop current capability. The
DC resistance may be slightly different and various components may need to be adjusted to retain the necessary
NOTE once again, that only minimal transient protec·
tion is illustrated in these examples, This must be add·
ed to meet the needs of the application and the FCC
Part 68 requirements.
3.116
-} GOULD
AIMII®Semiconductors
S3531
Modem Glossary
is important in all asynchronous serial data systems
because the edges of the data bits are used to
reconstruct all timing information.
Analog Loopback - A diagnostic test for the entire internal signal path of the modem chip_ The transmitted
analog output is internally connected to the analog
input.
DAA - Data Access Arrangement. An FCC registered
device necessary for correctly connecting a device to
the switched telephone network. Refer to Part 68 of the
FCC's regulations.
Asynchronous - A scheme for transmitting data on a
character-by-character ba,sis without a synchronizing
clock signal. In general the asynchronous protocol includes a start bit to identify the beginning of a
character, the data bits, and stop bit(s)_
DCE - Data Communication Equipment. Modem or
any other equipment necessary for the transmission
and reception of data between computers and
terminals.
Bandwidth - The frequency range of a communications channel. Normal phone lines have a bandwidth of
3000Hz for voice, from 300Hz to 3300Hz. ,
Digital Loopback A diagnostic test for the entire
phone line and remote modem. The remote modem's
digital output to the DTE is connected to the digital input from the DTE and fed back to the transmitting
modem.
BPS - The speed at which a modem can transmit or
receive data, measured in bits per second. 300 bps is
roughly equal to 300 words per minute.
Bias Distortion - Distortion such that the actual mark
and space bits are not of equal time duration, thus
causing a deviation from the expected 50% duty cycle.
Direct Connect Modems - Modems that contain a DAA'
rather than requiring an acoustic coupler or a tie-in to a
phone handset mouthpiece.
CCITT - International Telegraph and Telephone Consultative Committee. An organization for developing
communication system standards. The European
equivalent of BELL standards.
DTE - Data Terminal Equipment. The digital equip-'
ment that attaches to a modem as the end of the data
path. Usually a terminal or a computer.
Data Distortion - Bit bias distortion occurs when the
width of bits received are not equivalent for both a '
logic one and a logic zero. Bit bias is easily measured
as it shows up as a deviation in average voltage. In a
normal data stream of alternating ones and zeros the
average voltage is zero. However when bit bias destortion is present the duty cycle is not exactly 50% and
hence the average voltage is not zero. Excessive bit
bias will lead to quality degradation as system UARTs
deserialize data correctly only when bit bias distortion
is low.
Bit jitter distortion is also important for proper operation of all modems. Bit jitter occurs when the actual
center of the data bit drifts around the theoretical
center. Again, this is important to the proper operation
of a modem because UARTs only deserialize data correctly when bit jitter distortion is low. Jitter distortion
FSK - Frequency Shift Keying. A modulation method
which varies the carrier frequency to correspond with
the binary signals to be transmitted.
Full Duplex - Simultaneous two-way communication
(transmission and reception) between two computers
'
or modems.
Off-Hook - Connected to the telephone line.
RS232C - A serial communications interface defined
by the Electronic Industries Association. Frequently
used to connect stand-alone modems to personal
computers.
3.117
1
- _=.
I
-} GOULD
2600Hz Digital Frequency
AIMII®Semiconductors
Detector
S3524A
Features
o
o
o
2600Hz Center Frequency With 70Hz Bandwidth.
o
Input Comparator for Squaring and Sensitivity
Adjustment
o
l.ow Power CMOS Technology
Description
The S3524 is a digital Frequency Detector used to
accurately determine if an incoming tone is within" a
set of predefined limit frequencies. It checks every
period of the incoming signal, giving a true output for
each period falling within the desired bandwidth.
Small 8-Pin Minidip Package
Operation From a Low Cost 3.58MHz TV Colorburst Crystal or External Clock
"
The S3524A, using a 3.58 MHz clock, will detect a
2600Hz frequency within 70Hz bandwidth. It is primarily designed to follow the S3526B 2600Hz bandpass
filter as shown in Figure 4.
Block Diagram
Pin Configuration
Voo
OSCin
OSCout
IN-
5
Vss
3.118
DEl
OUT
IN+
2
FB
3
Vss
4
S3524A
a
Voo
7
OSC.
6
OSCi
5
DEl OUT
-} GOULD
AIMII®Semiconductors
S3524A
Absolute Maximum Ratings
Supply Voltage (Voo-Vss ................................................................... ± 15V
Operating Temperature ............................................................... O°C to 70°C
Storage Temperature .......................................................... - 65°C to + 150°C
Analog Input ......................................................... Vss - O.3V';; VIN .;; Voo + O.3V
Parameter Conditions
Min.
Typ.
Max.
Units
VDD
Positive Supply (Ref. to GND)
Vss
PD
Negative Supply (Ref. to GND)
VIN
Input Signal Level
4.75
5
5.25
V
-4.75
-5
- 5.25
V
43
mV (RMS)
Ro
Load Resistance
6
kQ
Power Dissipation
100
I
mW
Pin Description
Name
Number
Description
VDD
B
Positive Power Supply. Typically + 5V.
Vss
ININ+
4
Negative Power Supply. Typically - 5V.
1
Input comparator for setting sensitivity and squaring of analog signals. Signal sensitivity is
controlled by selecting external resistors.
FB
2
3
DET OUT
5
The detector output. Open drain type output for ease of interface. DET OUT will be high after
one full cycle of valid signal is detected. and will remain high until an out of frequency cycle
is detected.
OSC IN
OSC OUT
6
7
Oscillator terminals for 3.5BMHz reference crystal or clock. Uses standard TV crystal or a
rail-to-rail CMOS clock may be used.
Operation and Applications Information
Figure 1.
Figure 2. Representative Circuit
+5VOLTS
FILTERED
ANALOG
~ f-1'F-'- - - - - d
h
J
,aKQ
150KQ
DETECTOR
OUTPUT
-5V
INPUT _ (.5V SUPPLYI RT
mEL-~
-$VOLTS
1'S'Slll1z
2600Hz
2650Hz
5HzPERDlVISJON
3.119
- ~:
I
.
DC Electrical Operating Characteristics: TA = O°C to + 70°C
Symbol
I
GOULD
AIMII®Semiconductors
S3524A
Figure 3. Effective Response of S3526 Bandpass
Filter Followed by S3524A Digital Detector
Figure 5. A Typical Detection Bandwidth 2600 for
Application Circuit in Figure 4 at 10V
osc
-,
-,
TRANSISTION
REGION
TRANSISTION
REGION
NON·DETECT
REGION
NON·DETECT
REGION
TYPICAL 83526
/ ' BANDPASS RESPONSE
RESULTING RESPONSE
OF FOLLOWING 83526
W/S3524A DETECTOR
-3
-,
~5
h
-6
_7~
2500
-L~~
2550
__
~
____
~~4-
__
2650
'600
13
I,
2574
2552
__
2700
I,
2628
2642
I
I
~
2564
2636
IN SINGLE SUPPLY SITUATION THE GROUND FOR THE SENSITIVITY ADJUSTMENT WOULD BE 112
(VDo-VSS) AS DETERMINED BY A REGULATOR OR RESISTIVE VOLTAGE DIVIDER. OFFSET COMPENSA·
TlON WOULD BE DONE BY VARYING THE HALF VOLTAGE POINT SLIGHTLY IF DESIRED.
Figure 4. Circuit Example Showing S3526B and S3524A Combined to Provide Narrow Detection Bandwidth
+10V
AUDIO IN
.0 1
114
-l
1 INPUT
51KQ
~
CIT
1
CS
VAG
l~M
OSCi
DSC, 3
INV
24pF
¢3.5B
MHz
S3526B
TONE LN/C
HE
BUFF
J
1100~~
l~F i"
13
Voo
.1it
lKQ
2
N/C.-! NOTCH
11
.
17
Voo BPF 12
i
-I, 2~F
J
24PF
10
~N/C
Vss
6
~7
3.120
1 IN3
560:1
--I
10 of
FB
10KQ
DET 5
OUT
2 ,N +
llKQ
1.9KQ
8
VOD
S3524A
...! DSC,
OSC. L.N/C
Vss
4
DETECTOR
OUT
-} GOULD
DTMF Bandsplit Filter
AIMII®Semiconductors
S3525A
Features
General Description
o
The S3525 DTMF (Touch Tone® ) Bandsplit Filter is an
18-pin monolithic CMOS integrated circuit designed to
implement a high quality DTMF tone receiver system
when used with a suitable decoder circuit. The device
includes a dial tone filter, high group and low group
separation filters and limiters for squaring of the filtered signals. An uncommitted input amplifier allows a
programmable gain stage or anti-aliasing filter. The dial
tone filter is designed to provide a rejection of at least
52dB in the frequency band of 300Hz to 500Hz. The
S3525A can be used with digital DTMF decoder chips
that need the TV crystal time base allowing use of only
one crystal between the filter and decoder chips.
o
o
o
o
o
CMOS Technology for Wide Operating Single
Supply Voltage Range (7.0V to 13.5V). Dual
Supplies (± 3.5V to ± 6.75V) Can Also Be Used.
Uses Standard 3.58MHz Crystal as Time Base.
Provides Buffered Clock to Extemal Decoder
Circuit.
Ground Reference Internally Derived and Brought
Out.
Uncommitted Differential Input Amplifier Stage for
Gain Adjustment
Filter and Limiter Outputs Separately Available
Providing Analog or Digital Outputs of Adjustable
Sensitivity.
Can be Used with Variety of Available Decoders to
Build 2-Chip DTMF Receivers.
Block Diagram
Pin Configuration
v..
VREF
IN-
CKoor (3.5BMH.)
OSCOUT
BVREF
OSCIN
Vss
FHoUT
LD IH-
FLOUT
LD IH+
FEEDBACK
FLSQ
FHSQ
IH+
IH-
BVREf
HIIN+ .
v"
VREf
v~
®
Registered trademark of AT&T
3.121
HIIH-
1
- _=-
I
I
-} GOULD
~MII®Semiconductors
S3525A
Absolute Maximum Ratings:
DC Supply Voltage (VDD - Vss) ........................................................................................................................•... +15.0V
Operating Temperature .............................................................................................................................. O·C to + 70·C
Storage Temperature ...................................................................................................•...................... -55·Cto +125·C
Analog Input .........................................................................................•.............................. Vss - O.3V';;;VIN ,;;;VDD + O.3V
DC Electrical Operating Characteristics: TA = O·C to + 70·C
Symbol
Parameter/Conditions
Min.
Typ.
Max.
Units
Voo
Positive Supply (Ref to Vss)
9.6
12.0
13.5
V
VOL(CKOUT)
Logic Output" Low." Voltage 10L = 160flA
Vss + 0.4
V
VOH(CKOUT)
Logic Output"High" Voltage 10H = 4f1A
Voo-1.0
V
. VOL(FH, FL)
Comparator
Output Voltage
Low
VOH(FH, FL)
Comparator
Output Voltage
High
RINA (IN - ,IN +)
Analog Input Resistance
CINA(INA-,IN+)
VREF
Analog Input Capacitance
VOR = [BVREF • VREF 1
Offset Reference Voltage
500pF Load
10kQ Load
Vss + 2.0
10kQ Load
Voo - 2.0
V
8
MQ
V
0.50
(Voo - Vss )
15
pF
0.51
(Voo - Vss )
V
50
I
V
Voo-0.5
0.49
(Voo - Vss)
I
V
500pF Load
Reference Voltage Out
Power Dissipation
. Po
Vss+0.5
mV
Voo= 10V
170
mW
Voo= 12.5V
400
mW
Voo =13.5V
650
mW
AC System Specifications:
Symbol
AF
DTRL
DTRH
Parameter/Conditions
Min.
Typ.
Max.
Units
Pass Band Gain
5.5
6
6.5
dB
55
59
dB wrt
700Hz
50
53
dB wrt
700Hz
Dial Tone Rejection
Dial Tone Rejection is measured at the
output of each filter with respect to
the passband
350Hz
Low Group
Rejection
440Hz
High Group
Rejection
Either Tone
3.122
55
68
dB wrt
1200Hz
~ GOULD
AIMII®Semiconductors
S3525A
AC System Specifications (Continued)
Symbol
Parameter/Conditions
Min.
Typ.
Max.
Units
Attenuation Between Groups
GAL
Attenu'ation of the nearest frequency of the opposite group is measured
at the output of each filter with respect to the passband
Attenuation of 1209H z
50
>60
GAH
Attenuation of 941 Hz
40
42
dB wrt
700Hz
dB wrt
1200Hz
Total Harmonic Distortion
THD
Total Harmonic Distortion (dB). Dual tone of 770Hz and 1336Hz sinewave applied at the input of the filter at a level of 3dBm each. Distortion
measured at the output of each filter over the band of 300 Hz to 10kHz
(Voo = 12V)
Idle Channel Noise
-40
dB
ICN
Idle Channel Noise measured at the output of each filter with C-message
weighting. Input of the filter terminated to BVREF
Group Delay (Absolute)
1
mVrms
GD L
Low Group Filter Delay over the band of 50Hz to 3kHz
4.5
6.0
ms
GD H
High Group Filter Delay over the band of 50Hz to 3kHz
4.5
6.0
ms
Pin #
Function
Descriptions
16,17
OSC 1N , OSC OUT
These pins are for connection of a standard 3:579545MHz TV crystal and a 10MQ
± 10% resistor for the oscillator from which all clocking is derived. Necessary
capacitances are on-chip, eliminating the need for external capacitors.
18
CKOUT
11,12,13
IN -, IN +, Feedback
Oscillator output of 3.58MHz is buffered and brought out at this pin. This output
drives the oscillator input of a decoder chip that uses the TV crystal as time base.
(Only one crystal between the filter and decoder chips is required.)
These three pins provide access to the differential input operational amplifier on
chip. The feedback pin in conjunction with the IN - and IN + pins allows a programmable gain stage and implementation of an anti-aliasing filter if required.
15,14
FH OUT, FL OUT
These are outputs from the high group and low group filters. These can be used as
inputs to analog receiver circuits or to the on-chip limiters.
HI IN -, HI IN +
LO IN -, LO IN +.
These are inputs of the high group and low group limiters. These are used for
squaring of the respective filter outputs. (See Figure 2.)
9,10,5,6
8,7
FHSQ, FLSQ
These are respectively the high group and low group square wave outputs from the
limiters. These are connected to the respective inputs of digital decoder circuits.
1,4
Voo , Vss
These are the power supply voltage pins. The device can operate over a range of
7V';;(Voo - Vss)';;13.5V.
2
VREF
An internal ground reference is derived from the Voo and Vss supply pins and
brought out to this pin. VREF is 112(Voo - Vs s) above Vss.
3
BVREF
Buffered VREF is brought out to this pin for use with the input and limiter stages.
3_123
1_:
1
-
.
I
-) GOULD
AIMII®Semiconductors
S3525A
Figure 1. Typical 83525 DTMF Bandsplit Filter Loss/Delay Characteristics·
0.8dBlOCTAVE
ROLLOFF
10
20
19.85dB(600Hz) - - -
3D
40
.....
50
60
--SOdB (1209Hz)
tl
:l
70
5.0
80
4.5
4.0
LOW GROUP DELAY (GOLl
3.5
.
3.0
!
100
2.5
i
110
1.5
2.0
i
1.0
120
0.5
0.5
1.0
2.0
1.5
2.5
3.0
FREQUENCY (kHz)
Input Configurations
The applications circuits show some of the possible input configurations, including balanced differential and
single ended inputs. Transformer coupling can be used
if desired. The basic input circuit is a CMOS op amp
which can be used for impedance matching, gain
adjustment, and even filtering if desired. In the differential mode, the common mode rejection is used to reject
power line-induced noise, but layout care must be
taken to minimize capacitive feedback from pin 13 to
pin 12 to maintain stability.
Since the filters have approximately 6dS gain, the in-
puts should be kept low to minimize clipping at the
analog outputs (FlouT and FH oUT)'
Output Considerations
The S3525 has both analog and digital outputs
available. Most integrated decoder circuits require
digital inputs so the on-chip comparators are used with
hysteresis to square the analog outputs. The sensitivity
of the receiver system can be set by the ratio of R1 and
R2, shown in Figure 2. The amount of hysteresis will set
the basic sensitivity and eliminate noise response
below that level.
3.124
-) GOULD
AIMII®Semiconductors
S3525A
Figure 2. Typical Squaring Circuit
S3525A BANDSPLIT FILTER
I
I
I LOW GROUP
I SQUARED OUTPUT
I
IL _____ ...JI
ASSUMING DVREF= 0 OR
'I,(VOItVss) then
UTP = ED(SAn __
Rl_
Rl + Rz
LTP=-ED(SAn __
Rl_
Rl + Rz
Crystal Oscillator
Applications
The S3525 crystal oscillator circuit requires a 10 Meg
ohm resistor in parallel with a standard 3.58MHz tele·
vision colorburst crystal. For this appl ication, however,
crystals with relaxed tolerances can be used. Specifica·
tions can be as follows:
The circuits shown are not necessarily optimal but are
intended to be good starting points from which an opti·
mal design can be developed for each individual appli·
cation.
Quartz Crystal Specification (25°C ± 2°C)
Operating Temperature Range. . . . . . . . . .. DoC to + 70°C
Frequency. . . . . . . . . . . . . . . . . . . . . . . . .. 3.579545MHz
Frequency Calibration Tolerance. . . . . . . . . . .
.02 ± %
Load Capacitance ........................... 18pF
Effective Series Resistance . . . . . . . . . . .. 180 Ohms, max.
Drive Level·Correlation/Operating . . . . . . . . . . . . . . .. 2mW
Shunt Capacitance. . . . . . . . . . . . . . . . . . . . . . . 7pF, max.
Oscillation Mode. . . . . . . . . . . . . . . . . . . . . .. Fundamental
Companion decoders to be used with the S3525 vary in
performance and features. Nitron's NC2030 and
MOSTEK's MK5102/03 are available units that can be
used with the S3525.
Typical Applications
o
o
o
o
o
o
o
Alternate Clock Configurations
If 3.58MHz is already available in the system it can be,
applied directly as a logic level to the OSCIN (pin 16).
[Max. zero "-'30 % VDD , min. one,,-,70% VDDI. Waveforms
not satisfying these logic levels can be capacitively
coupled to OSCIN as long as the 10 Meg ohm feedback
resistor is installed.
The S3525A provides a buffered 3.58MHz signal from
the on·chip oscillator to external decoders or other
devices requiring 3.58MHz.
3.125
o
o
Wireline DTMF Signal Receivers
Radio DTMF Signal Receivers
Dial Tone Detectors
Offsite Data Collectors/Test Instruments
Security Alarms
Remote Command Receivers
Phone Message Playback
Camera Controllers
Robot Arm Controllers
- ~:
I
.
-) GOULD
AIMII®Semiconductors
S3525A
Figure 6. DTMF End-to-end Signaling Using the Telephone Network
TRANSMISSION MEDIUM·
WIRE, CABLE, COAX, MICROWAVE, SATELLITE, ETC.
~
~t--DT-:-:
~
/
I~·"U~==--.
/
1
--1-- '1
NETWORK
V\I'
CO
.
.
~
RECEIVER
CENTRAL
OFFICE
______
CENTRAL
OFFICE
AUTO·ANSWER
OTMF
RECEIVER
REMOTELY
CONTROLLED
DEVICE
(408) 246·0330
J
(914) 352·5333 DTMF
HIGH SPEED
-'--DlALING
I••-------INTER·OFFICE
OF PHONE NOS.,
SIGNALING (MF)
'.1
. '
I
1-------------~~~~DS~~LlNG--------------J
..
Remote Control
Dial Tone Detector
In some systems, a telephone set is used to do remote
controlling. A remote device to be signalled is'inter·
connected to the telephone network with its own num·
ber (see Figure 6). When that number is dialed, the con·
nection is established. The calling party continues to
push the buttons on his telephone, sending command
codes.' The DTMF Receiver at the central office is
disconnected once the line connection is established,
so no problem arises in the telephone network. Now
the DTMF Receiver in the answering device is detect·
ing and responding to the dialed digits, performing the
control functions.
Since the frequency response of switched capacitor
filters can be varied directly by varying the clock fre·
quency, the S3525A can be used for other
Telecommunications applications.
One application is a dial tone detector for telephone
accessory equipment to determine the presence or
absence of dial tone. Precision dial tone is a combina·
tion of 350 and 440Hz. By using a crystal of 1.758MHz
the 3dB points of the low group filter output will be 334
to 496Hz. Thus, all the energy from precision dial tone
will be available at the low group output.'
, Need "Polarity Guard" or non·reversing central office so encoder stays enabled.
3.126
GOULD
AIMII®Semiconductors
S3525A
Figure 3. DTMF Keyboard
I
I
I
I
I
I
I
0--
697--8-[]-~
I
I
1
I
I
I
I
77o-{~J-8-~ ~-I
I
- _=.
I
I
B52--0-~-0 ~-I
I
I
I
I
J
I
I
I
I
I
I
941--[:]-8- 0 [~}1209 1336 1477 1633
Figure 4. AMI/Mostek 2 Chip DTMF Receiver
+12 V
+5V
FH OUT
15
0.05 JlF
5.1 K
1K
470 pF
0.1 JlF
HI IN-
10
0.1 JlF
>--1
DTMF
IN
FORMAT
CONTROL
208
12
FH SO
10 K
330 K
12
1
S3525A
HIIN+
IN+
FLOUT 14
680 K
HIGH·
GROUP
IN
MOSTEK
MK5102
OR
MK5103
2K .
1K
0.1 JlF
3 BV""
1 JlF
0
LO IN11
FL SO
4
STROBE
STROBE
0.05 JlF
330 K
Vss
LOW.
GROUP
IN
)
LO IN+
2K
V-
An application note on the S3525A is also available. Please contact factory.
3.127
A
10
4·BIT
BINARY
OUTPUT
-} GOULD
AIMII®Semiconductors
Single Frequency Tuneable
Bandpass/Notch Filter/Tone Generator
535268
Features
General Description
o
The S3526B is a low power CMOS Circuit which may be
used in a variety of single frequency (SF) communication applications such as SF-Tone Receivers, Tone
Remote Control in Mobile systems, Loopback Diagnostics in Modems, control of Echo Cancellers, dialing and
privacy functions in Common Carrier Radio Telephone,
etc. The main functional blocks of the S3526B include a
low distortion tone (sinewave) generator whose frequency may be programmed using a crystal (Le. 2600Hz
using a low cost TV color burst crystal) or external
clock time base; a bandpass filter used to extract tone
information from the input signal; a band reject filter
which is used to "Notch" out tone information from the
input signal; and a buffer amplifier with selectable input (unfiltered input signal, or input signal with tone
notched) capable of driving a 600Q load.
o
o
o
o
o
o
o
Center Frequency of Filters Match and Track Frequency of Generated Tone
Tone Frequency Adjustable Over a 100Hz to 5kHz
Range
Unfiltered Input, Input with Notched Tone, Input
Tone and Tone Generator Outputs
Operation from a Crystal or External CMOSmL
Clock
Operation at 2600Hz from a Low Cost 3.58MHz TV
Color Burst Crystal or 256kHz Ext. Clock
Buffered Output Drives 600Q Loads
Single or Split Supply Operation
Low Power CMOS Technology
53526B Block Diagram
Pin Configuration
cif 0,.,-1------,
TONE
OSCo
cs~I--+------r-----~
INPUT o-;-I--------~-------___tl~
BP'
v"
NOTCH
'NV
BUFF
NE~I_-----------~
3.128
INPUT
ciT
OSC,
v,.
OSCO
BPF
CS
INV
TONE
HE
Vs.
BUFF
V,,
NOTCH
-) GOULD
AIMII®Semiconductors
53526B
Absolute Maximum Ratings
Supply Voltage (Voo - Vss ) .....................................•...................................................................................... + 15.0V
Operating Temperature .................................................................:..................................................... O°C to + 70°C
Storage Temperature ..................................................................................................................; - 6'5°C to + 150°C
Input Voltage, All Pins .................................................................................................. Vss - O.3V51 dB for f>1.3fc
D Uncommitted Input and Output Op Amps for AntiAliasing and Smoothing Functions
D Steps May Be Custom Programmed from a Set of
2,048 Discrete Points Via Internal ROM
D Low Power CMOS Technology
535288 Block Diagram
Typical Applications for the S35288 and 535298
Programmable Filters
Telecommunications
D P8X and Trunk Line Status Monitoring·
D Automatic Answering/Forwarding/Billing Systems
D Anti-Alias Filtering
D Adaptive Filtering
Remote Control
D Alarm Systems
D Heating Systems
D Acoustic Controllers
Test Equipment/Instrumentation
D Spectrum Analyzers
D Computer Controlled Analog Circuit Testers
D Medical Telemetry/Filtering
D ECG Signal Filtering
D Automotive Command Selection and Filtering
Pin Configuration
VDO
FB
SIG(llI)
Dseo
0,
03
0,
0,
Du
0,
ee
'"
OS~
'DO
BUFF OUT
Ou
BUFF IN
0,
FlT OUT
0,
03
0,
0,
CE
15
V"
ACND
DCNO
3.135
DCMO
oseo
DS~
SIG IN
ACND
FB
~:I
I
-
.
I
-} GOULD
AIMII®Semiconductors
S35288
Typical Applications for the S3528B and S3529B
Programmable Filters (continued)
Audio
D
D
D
D
D
D
Electronic Organs
Speech Analysis and Synthesis
Speaker Crossovers
Sonabuoys
Spectrum Selection
Low Distortion Digitally Tuned Audio Oscillators
General Description
The S35288's CMOS design using switched-capacitor
techniques allows easy programming of the filter's cutoff
frequency (fel in 64 steps via a six-bit control word. For
dynamic control of cutoff frequencies, the S35288 can
operate as a peripheral to a microprocessor system with
the code for the cutoff frequency being latched in from the
data bus. When used with the companion high pass filter,
the S35298, a bandpass or a band reject filter with a
variable center frequency is obtained. For special applications the S35288's internal ROM can be customized to
accommodate a specific set of cutoff frequencies from a
choice of 2,048 possibilities.
.
Absolute Maximum Ratings
Supply Voltage (Voo - Vss) .............................................................................................................................. + 15.0V
Operating Temperature .......................................................................................................................... O°C to + 70°C
Storage Temperature ....................................:........ :....................................................................... - 65°C to + 150°C
Input Voltage, All Pins ....................................................................................................... Vss - 0.3V~VIN~VOO + 0.3V
D.C. Electrical Operating Characteristics: TA
Symbol
Voo
Po
RIN
CIN
=O°C to + 70°C, (Voo -
Parameter/Conditions
Vss)
=10V unless otherwise specified
Min.
Typ.
Max.
Positive Supply (Ref. to Vss )
Power Dissipation
@10V
@13.5V
9.0
10
13.5
V
60
135
110
225
mW
mW
Input Resistance (Pins 1-4.8.12,13.16-18)
8
MQ
Input Capacitance (Pins 1-4, 8, 12, 13, 16-18)
15.0
General Analog Signal Parameters: (Voo - VSS) = 10V ± 10%, TA = O°C to
Symbol
Parameter/Conditions
Units
pF
+ 70°C, fclock = 3.58MHz
Min.
-0.5
Typ.
Max.
0
0.5
Units
AF
Pass Band Gain at 0.6 fc
Va
VFS
Relerence Level Point (OdBmO)
RL
Load Resistance FLT OUT, Pin 9
10
kQ
RL
VOUT
Load Resistance BU FF OUT, Pin 7
600
ohms
Output Signal Level into RL lor FLT OUT, BUFF OUT, VIN = 2.1V
2.0
2.1
VRMS
THD
Total Harmonic Distortion at .31c
.3
%
WBN
Wideband Noise (to 30kHz) Ie = 3. 2kHz
.15
mVRMS
WBN
Wideband Noise (to 80kHz) Ie = 15kHz
.13
ICN
Idle Channel Noise Ie = 3200Hz
Vos
VOFS
Maximum Input Signal Level ( + 3dBmO)
dB
1.5
VRMS
2.1
VRMS
mvRMS
8
23
Buffer Output (Pin 7) Offset Voltage
± 10
±30
mV
Filter Output (Pin 9) Offset Voltage
±80
±200
mV
3.136
dBrnCO
-) GOULD
AIMII®Semiconductors
535288
Filter Performance Specifications
Low Pass Filter Characteristics: fclock 3.58MHz, (VDD
Symbol
Parameter/Conditions
Pass Band Ripple (ReI. 0.6 fel
Filter Response(l): Fe = 3200Hz (Pin 9)
(See Figure 5)
=
DR
-
Vss )
=10V, TA =O°C to
Typ.
(fc) 3200Hz
(1.0Bfc) 3372Hz
(1.27fc) 4060
(1.3fc) 4155
(1.32fc) 4235
(1.62fc) 5175
(1.3fc Upward)
4155 to 100,000Hz
Dynamic Range (V FS to ICN) [+3.0 to -82 dBm]
=
+ 70°C
-0.5
-5.5
0.5
-0.5
dB
dB
dB
dB
dB
dB
dB
dB
-48
-48
-48
85
= - 5V, TA =O°C to
Digital Electrical Parameters: VDD + 5V, Vss
Symbol
Parameter/Conditions
VIH
Input High Voltage
VIL
Input Low Voltage
Input Leakage Current (VIN = 0 to 4VDC)
IN
CIN
Input Capacitance
±0.1
-3.0
-42
-51
-65
-75
<-51
Units
dB
+ 70°C unless otherwise specified
Digital Timing Characteristics
Chip Enable Pulse Width
tCE
Address Setup Time
tAS
Address Hold Time
tAH
Crystal Oscillator Frequency(2)
fose
Settling Time from CE to Stable fe (fe = 3200)(3)
tSET
Min.
2.0
Vss
Typ.
200
300
300
20
3.58
6
Max.
Voo
0.8
10
15
Units
Volts
Volts
J.lADC
pF
nsec
nsec
nsec
MHz
msec
1.) Filter Response Relerenced to 1= 1,920Hz
2.) The tables are based on common TV crystal. See paragraph on "Clock Fre·
quencies" lor more detail.
3.)
Pin Function Description
Pin Name
Number
Voo
Vss
AGNO
DGNO
Do
Dl
D2
D3
D4
D5
CE
_
10
lSET - -1,-
+ 3msec
Function
6
5
11
15
Positive supply voltage pin. Normally + 5V ± 10%.
Negative supply voltage pin. Normally - 5V ± 10% ..
Analog ground reference point for analog input and output signals. Normally connected to ground.
Digital ground reference point for digital input signals. Normally connected to ground.
2
Control word Inputs: The set of six bits allows selection of one of sixty-four cutoff frequencies. The 6 bit control word is latched on the rising edge of CE. The high-impedance inputs may be bridged directly across a
microprocessor data bus. These inputs are TTL or CMOS compatible. A "1" is 2.0V to Voo, and a "0" is
0.8V to Vss.
31 }
18
17
16
4
Chip Enable: This pin has 3 states. When CE is at Voo the data in the latch is presented to the ROM and the
inputs have no effect. When CE is at ground the data presented on the inputs is read into the latch but the
previo~ data is still in the ROM. Returning CE to Voo presents the new data to the ROM and fe changes.
When CE is at Vss the inputs go directly to the ROM, changing fe immediately. This is the configuration for a
fixed filter; CE is at Vss and the Do through D5 are tied to Voo or VSS/DGRNO depending on the desired fe·
3.137
-} GOULD
AIMII®Semiconductors
S35288
Pin Function Description (continued)
Pin Name
Number
OSC I
OS Co
SIGIN
13
14
12
FB
10
FLT OUT
9
8
7
BUFF IN
BUFF OUT
Function
Oscillator In and Oscillator Out: Placing a crystal and a 10MQ resistor across these pins creates the time
base oscillator. An inexpensive choice is to use the 3.58MHz TV colorburst crystal.
Signal Input: This is the inverting input of the input op amp. The non-inverting input is internally connected
to Analog Ground.
Feedback: This is the feedback point for the input op amp. The feedback resistor should be ~10kQ for
proper operation.
Filter Out: This is the high impedance output of the programmable low pass filter. Loads must be ~10kQ.
Buffer Input: The inverting input of the buffer amplifier.
Buffer Out: The buffer amplifier output to drive low impedance loads. This pin may drive as low as 600Q
loads.
. '
Figure 2. Microprocessor Interface
Example of Circuit Connection for S35288
Figure 1. Stand Alone Operation
+5V
~
3. Do'
VOD
2 D,
1 0,
OSCI
13
Yl
. c:::J
oseo
14
FlT
OUT
9
10MQ
18
835288
-5V-------"-I
OUTPUT AMPLIFIER RESISTORS
10,KQ s R :s; • _ _
50_ (KQ)
--v;;-
AUDIO IN
ANTI-ALIASING
ALTER
AUDIOOlfT
AUDIO OUT
SMOOTHING
ALTER
c=
1
-5V
Operation
S3528B Filter is a CMOS Switched Capacitor Filter'
device designed to provide' a very accurate, very flat,
programmable filter that can be used in fixed applica·
tions where only one cutoff frequency is used, or in
dynamic applications where logic or a microprocessor
can select anyone of 64 different cutoff frequencies. It
is normally clocked by an inexpensive TV color burst
crystal and provides the cutoff frequencies seen in
Table 1 when the Data Bus pins are program~ed.
All that is required for fixed operation is a 10MQ
resistor, the 3.58MHz TV crystal, and some resistors
arid capacitors around the input and output amplifiers
to set the gain, anti-aliasing, and smoothing. The Data
Bus pins are programmed from the table to either a "1"
(+ 5V) or a "0" (ground or - 5V) for the desired cutoff
frequency. The CE pin is tied low, to Vss.
3.138
.y
GOULD
AIMII®Semiconductors
S35288
Operation (continued)
The ROM is addressed by the contents of the latch and
presents an 11-bit word to the programmable divider
which divides fClK '
The FILTER OUT pin is capable of driving a 10kQ load
directly or, for smoothing and driving a 600Q load, the
output buffer amplifier can be used for impedance
matching.
As illustrated in the curves of Figures 3, and 5 through
7, the passband ripple (for fc<18kHz) is less than
±0.1dB and the stop band rejection is better than
50dB, as measured on a network analyzer.
For microprocessor controlled operation, the Data Bus
can be bridged across a regular TIL bus and when CE is
strobed, the data present will be latched in and the filter
will settle down to its new cutoff frequency. In CMOS
systems, the Data Bus and CE can be swung rail-to-rail.
AGND and DGND must be at V2 the supply voltage.
The following table illustrates the available cutoff frequencies based on using a 3.58MHz TV crystal for a
time base, by approximately 100Hz steps through the
voice band from 100Hz to 3900Hz. Note that the hex input code for each frequency in the voice band is onehundredth of the cutoff frequency. For 3200Hz, the hex
code is 32, for 900Hz it is 09. Additional frequencies are
listed with their codes on the right side of the Table 1.0.
Table 1.0-5tandard Frequency Table: Programmable Filter 535288.
= 3.58MHz
fCLOCK
Voice Band
Additional Points Available
Input Code
(HEX)
05-0 0
Divider
Ratio
Actual
(Hz)
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
36
37
39
2048
895
447
298
224
179
149
128
112
99
89
81
74
69
64
60
56
53
50
47
45
43
41
39
37
36
34
33
32
31
30
29
28
27
26
25
24
23
44
100
200
300
399
500
601
699
799
904
1005
1105
1209
1297
1398
1491
1598
1688
1790
1904
1989
2081
2183
2295
2418
2486
2632
2711
2797
2887
2983
3086
3196
3314
3442
3579
3728
3891
Ie
Input Code
(HEX)
05-0 0
Divider
Ratio
Actual
(Hz)
OA
OB
OC
00
OE
OF
lA
1B
lC
10
lE
IF
2A
2B
2C
20
2E
2F
35
38
3A
3B
3C
3D
3E
3F
188
358
90
87
85
78
61
58
52
46
44
40
38
35
22
20
18
16
15
14
12
10
9
6
5
4
476
250
994
1028
1053
1147
1467
1542
1721
1945
2034
2237
2350
2557
4067
4474
4971
5593
5965
6392
7457
8949
9943
14915
17897
22372
fcutoff
=
Ie
fclOCK
40 (Divider Ratio)
fsampli ng
= __f_C_LO_C_K_ _
Divider Ratio
3.139
_:1'
I[
-
.
I
-} GOULD
~MII®Semiconductors
S35288
Figure 6. Passband Control Detail,
Control
110010, fc
3200Hz
Figure 3; Family of Loss Curves for
4 Different Control Codes
=
=
75
65
0.40
"
0.30
45
"~" "
25
0.20
0.10
.~
""
15
0.00
-0.10
-0.20
-'0':-~--'--'-'-:o!50':-:OO""""'-'-'--'-ClO'"'OO""O~~~'''"50'''O~O~~~2"'O-DOO
-0.30
FREQUENCY 1Hz]
-'0.40
0
900
1800
FREDUEHCY 1Hz]
Figure 4. Address and Chip Enable Timing
Figure 7. Family of Loss Curves for
4 Different Control Codes
Figure 5. Loss Curve, Control
110010, fc
3200Hz
75
65
75
"
65
""
"
~
45
35
45
~
5
25
"
15
25
15
FREQUENCY [Hz1
FREQUENCY 1Hz]
3.140
2700
3600
-} GOULD
AIMII®Semiconductors
535288
=110010, FC =3.2kHz
GDfc = x == GDfc = 3.2kHz ( 3;2kHz ~
Figure 8. Loss and Group Delay, Fe = 3200Hz
Figure 9. Group Delay, Control
\X kHz)
75
2000
2000
1800
"
lBOO
1600
55
1600
''--------1
!
45
1
1200
:5
):"1000
~
~
~
~
800
~
25
50'
1>D'
tOaD
800
50'
"
'00
-
iJ 1400
1400
.00
200~~-_ _ _ _--~
,,
'~'~~~'±OO'~~~'~00~'~--~5O~00~~~8000·5
FREOUENCY!H:)
OD'
1800
2700
3600
FREQUENCY!Hz)
Applications Information
Many filter applications can benefit from the 83528B,
particularly if extremely flat passband response with
precise, repeatable cutoff frequencies are required. Or,
if the same performance is required at different fre·
quencies it can be switched or microprocessor control·
led. The circuits (Figures 1 and 2) illustrate how the
83528B might be connected for two different uses. The
"stand alone" drawing (Figure 1) shows how it would be
programmed as a fixed, 3200Hz low pass filter. The
other drawing (Figure 2) shows a microprocessor driven
application that lets the cutoff frequency be varied on
command.
80me fields that can use such a fi Iter are speech analy·
sis and scrambling, geo·physical instrumentation,
under water accoustical instrumentation, two·way
radio, telecommunications, electronic music, remotely
programmable test equipment, tracking filter, etc.
Anti-Aliasing
In planning an application the basic fundamentals of
sampling devices must be considered. For example,
aliasing must be taken into consideration. If a fre·
quency close to the sampling frequency is presented to
the input it can be aliased or folded back into the pass·
3.141
1-:
,
band. Because the 83528B has an input cosine filter the
effective sample frequency is twice the filter clock frequency of 40 times the cutoff frequency. If fe = 1000Hz
and a signal of 79,200Hz is put into the filter, it will alias
the 80kHz effective sampling frequency of the input
cosine filter and appear as an 800Hz signal at the output.
This means that for some applications the input op amp
must be used to construct a simple one or two pole RC
anti-aliasing filter to insure performance. In many situations, however, this will not be necessary since the input
signal will already be band-limited.
Smoothing
In addition, all sampling devices will have aliased components near the clock frequency in the output. For example, there will be small components at fclk ± fin in
the output waveform. This can be reduced by constructing a simple smoothing filter around the output buffer
amplifier. Because of the sinxlx characteristics of a
sample and hold stage the aliasing components are
already better than 30dB down. The clock feed through
is approximately - 50dBV. This means that a simple
one pole filter can provide another 20dB of rejection to
keep the aliasing below 50dB down. In the case of a
3kHz fCUTOFF and the smoothing filter designed for a
3dB point at 4fcUTOFF the smoothing filter will affect
.
-} GOULD
AIMII®Semiconductors
535288
5moothing (continued)
Figure 11_ Cascaded 53528B and 53529B
Control = 100001
Bandpass Configuration-1 0 % Bandwidth
the 3kHz point by .25d8. If this is not desirable then the
smoothing filter might be constructed as a second
.
order filter.
For a fixed application, anti-aliasing and smoothing are
straight forward. For a dynamic operation, the desired
operating range of frequencies must be considered
carefully. It may be necessary to switch in or out additional components in the RC filters to move cutoff frequencies. The S35288 has a ratio of cutoff frequencies of
550:1 and to use the full range would require some
switching.
Notch Rejection
The filter is designed to have 51d8 of rejection at
1.3fcUTOFF and greater. If greater rejection of a specific
tone or signal frequency is desired, the cutoff frequency can be selected to position the undesired tone at
1.325fcUTOFF or 1.62fcUTOFF. This will place it in a notch
as illustrated in Figure 5.
The S35298 (High Pass Filter) and the S35288 (Low
Pass Filter) can be used together to make either 8and
Pass or 8and Reject/Notch filters. The control code selection determines the bandwidth of the resulting filter.
1500
3000
FREQUENCY {HZ]
4500
6000
Figure 12. 53528B and 53529B in Parallel
Notch Configuration-Wide Bandwidth
It should be noted that with the S35288 and S35298 data
pins connected in parallel and their analog inputs and
outputs in series a bandpass filter of approximately 10%
bandwidth is created.
75
"
55
Figure 10; 53528B and 53529B in Parallel
Notch Configuration-Narrow Bandwidth
45
~
~
75
"
"
25
55
"
"
"!l
or,
!<
45
-5
15011
4500
3000
FREOUENC~
6000
1HZ]
25
"
Crystal Oscillator
15011
3000
, FREQUENCY (HZ)
4500
6000
The S35288 crystal oscillator circuit requires a. 10 Meg
ohm resistor in parallel with a standard 3.58MHz television colorburst crystal. For this application, however,
. crystals with relaxed tolerances can be used. Specifications can be as follows:
3.142
-) GOULD
AIMII®Semiconductors
S35288
1_:
Figure 13. Bandpass Application: General Case Configuration
D
1
-
SIG IN
OUT
.
I
Note:
- Anti·aliasing and smoothing filters on both chips A1, A2,
81,82
• For same digital logic code
N = multiple of clock#1 to clock#2
fel = .9 fcu
N
- Lowpass after highpass to remove higher harmonics,
unless cosine input filler of lowpass needed to clean noisy in·
put signal
'
:
jl
,'
,,
", ,
:, :,
,,
:, ''
:, ::
- For wider band width two different oscillalors can be used.
ttl
,
leu
Figure 14. Notch Applications: General Case Configuration
SIGIN
83528B
~
...._,
SIGNAL
SUMMATION
3.143
-) GOULD
AIMII®Semiconductors
535288
Figure 15. Low Distortion Digitally Tuned Audio Oscillator Application Circuit
C,
0.1
C2
t
2KO
OSCILLATOR OUT
10
f--+-=-......- - O
R2
R,
10KIl
20KQ
IN914
R,
R2
0,. 02
C,. C2
, X,
12
~p
Frequency
RS";180Q
CL = 18pF
~lVp·P
ZL;>10K
f.se = 0.68fcUTOFF
50KQ .25W 5%
10KQ .25W 5%
IN914
O.l~F CERAMIC
3.579545MHz COLORBURST CRYSTAL
BUS OR SWITCHES
3.579545 ± .02%
LM "'96MH
Ch
7pF
=
Figure 16_ S3528B Driving Additional S3528B or
S3529B Devices
Alternate Clock Configurations
If 3.58MHz is already available in the system it can be
applied directly as a logic level to the OSC1N (pin 13).
[Max. zero"'30% (Voo-Vs s), min. one",70% (Voo-Vss )].
Waveforms not satisfying these logic levels can be
capacitively coupled to OSC1N as long as the 10 Meg
ohm feedback resistor is installed as shown in Figure
16.
OSC.
14
OSCIN
10MQ::!:
S3528
OSC;
'D3.58MHz
13
S3528
OR
S3529
r-- OSCOUT
To
HE XT
DEVICE
Although the tables are constructed around the TV
colorburst crystal, other clock frequencies can be used
from crystals or external clocks to achieve any cutoff
frequency in the operating range. For example, by using a rate multiplier and duty-cycle restorer circuit between the system clock and the S35288, and switching
the inputs to the S35288, almost any cutoff frequency
between 40Hz and 35kHz can be selected. The clock
input frequency can be anywhere between 500kHz and
5MHz.
OSCI
Figure 17. External Driving S3528B Pin OSCi
OSC.ut
r!!,
>
~ 10MO
S3528
OSCI.
In addition to crystals or external clocks the S35288 can
be used with ceramic resonators such as the Murata CSA
series "Ceralock" devices. All that is required is the
resonator and 2 capacitors to Vss. Although the resonators are not quite as accurate as crystals they can be less
expensive.
L..-_~
I~
13
>
1k
~
\;
3.144
3JO PF
TTL CLOCK
Programmable
Highpass Filter
-} GOULD
AIMII®Semiconductors
535298
Features
D Cutoff Frequency Selectable in 64 Steps Via Six-Bit
Control Word
D Cutoff Frequency (fc) Range of 10Hz to 20kHz,
40Hz to 20kHz Via 3.58MHz TV Crystal
D Seventh Order Elliptical Filter
D Passband Ripple: O.1dB
D Stopband Attenuation: 51dB for f<.77 fc
D Clock Tunable Cutoff Frequency Continuously
Variable Vii:1External Clock (Crystal, Resonator, or
TTUCMOS Clock)
D Uncommitted Input and Output Op Amps for AntiAliasing and Smoot!ling Functions
D Low Power CMOS Technology
Typical Applications for the 83528B and 83529B
Programmable Filters
Telecommunications
D PBX & Trunk Line Status Monitoring
D Automatic Answering/Forwarding/Billing Systems
D Adaptive Filtering
Remote Control
D Alarm Systems
D Heating Systems
D Acoustic Controllers
Test Equipment/Instrumentation
D Spectrum Analyzers
D Computer Controlled Analog Circuit Testers
D Medical Telemetry Filtering
D ECG Signal Filtering
D Automotive Command Selection and Filtering
Block Diagram
Pin Configuration
+ 5V
' 8
VDD
FLTOUT
BU~N
6
BUFouT
0,
03
01
0,
Do
0,
eE
OSC,
Vss
OSC;
BUFouT
DGND
BUFIN
SIGIN
VDD
AGND
FLToUT
AGND
3.145
FB
1
- _=.
-} GOULD
AIMII®Semiconductors
'.
S3529B
General Description
The S3529B's eMOS design using switched-capacitor
techniques allows easy programming of the filter's cutoff
frequency (fe) in 64 steps via a six-bit control word. For
dynamic control of cutoff frequencies, the S3529B can
operate as a peripheral to a microprocessor system with
the code for the cutoff freql!ency being latched in from the
data bus. When used with the companion low pass filter,
the S3528B, a bandpass filter with a variable center frequency is obtained. For special applications the S3529B's
internal ROM can be customized to accommodate a specific set of cutoff frequencies from a choice of 2,048
possibilities.
Absolute Maximum Ratings
Supply Voltage (VDD - Vs s) .. ,................ ,....................................................................................,......................... + 15.0V
Operating Temperature ., ........................... ,...........................................................,..................................... ooe to + 70 0 e
Storage Temperature ........................... :...................................................................... ,...................... - 65°e to. +. 150 0 e
Input Voltage, All Pins ................................................................................................................Vss - 0.3V,;;;VIN';;; + 0.3V
.
D.C. Electrical Operating Characteristics: TA
Symbol
Voo
Po
RIN
CIN
.
=ooe to + 70 oe, (VDD "':Vss) =10V unless otherwise specified'
Parameter/Conditions
Positive Supply (Ref. to VSS )
Power Dissipation
@10V
@13.5V
Input Resistance (Pins 1-4,7,12,14,16'18)
Min.
Typ..
9.0
10
13.5
V
60
135
110
225
'inW
mW
Symbol
15.0
= + 5V ± 10%, V55 = -
5V ± 10%, TA
Parameter/Conditions
VIH
VIL
Input High Voltage
IN
CIN
Input Leakage Current (VIN
= ooe to + 70 e
Typ.
2.0
Input Low Voltage
Vss
=
0 to 4VDCj
pF
unless otherwise specified
0
Min.
Units
MQ
8
Input Capacitance (Pins 1'4, 7,12,14,16-18)
Digital Electrical Parameters: VDD
Ma.x. .
.
Input Capacitance
Max.
Units
Voo
0.8
V
10
/JADC
15
pF
Max.
Units
V
Digital Timing Characteristics
Symbol
Parameter/Conditions
Typ.
200
300
ns
lAS
. Address Setup Time
300
ns
IAH
Address Hold Time
20
ns
lose
Crystal Oscillator Frequency(1)
3.58
MHz
ISET
Settling Time From CE to Stable Idle = 3200)(2)
6
ms
ICE
Chip Enable Pulse Wid1h
Min.
Notes:
1. The tables are based on the common 3.58MHz color burst TV crystal.
2. tSET =
+
+ 3msec
'3.146
-} GOULD
AIMII®Semiconductors
S35298
General Analog Signal Parameters: (Voo - Vss) = 10V, TA = O°C to
Symbol
Parameter/Conditions
AF
Pass Band Gain at 2.2 Ic
VMAX
Reference Level Point (OdBmO)
VFS
Maximum Input Signal Level (+ 3dBmO)
RL
Load Resistance (FLTOUT' Pin 9)
Load Resistance (BUFoUT , Pin 6)
RL
VOUT
THO
+ 70°C, fosc = 3.58MHz
I
Min.
Typ.
Max.
-0.5
0
0.5
VRMS
2.1
VRMS
kQ
Q
600
2.0
dB
1.5
10
Output Signal Level into RL for FLToUT' BUFouT
Total Harmonic Distortion: Input code 22, Frequency = 2kHz;
Bandlimited to Iclk/2
Units
2.1
VRMS
.15
%
WBN
Wideband Noise: Input code 22, Bandlimited to 15kHz
.25
mVRMS
Vos
Buffer Output (Pin 6) Offset Voltage
± 10
mV
VoEs
Filter Output (Pin 9) Offset Voltage
±80
mV
Filter Performance Specifications: High Pass Filter Characteristics (fosc = 3.58MHz) (Voo - Vss) = 10V,
TA = O°C to + 70°C
Symbol
Parameter/Conditions
Min.
Passband ripple (Ref. 2.2 fc) fc<::;f<7fc
Typ.
Max.
Units
-0.5
±0.05
0.5
dB
-0.5
±0.1
0.5
dB
-5
-3.0
-1
db
db
db
Filter Response: fc = 1005Hz
(fc)
Stopband
DR
1005Hz
(0.96 fc)
960
(0.768 fc)
772
-53
(.754 tc)
758
-85
-43
-43
(.614fc)
617
-70
-43
1<.768 fc
Dynamic Range (VFS to WBN)
db
<-53
db
78
dB
Pin Description
Pin Name
Voo
Vss
AGNO
DGNO
Do
01
02
03
04
05
Pin#
Function
8
5
11
13
3
2
1
18
17
16
Positive supply voltage pin. Normally + 5 volts ±10%.
Negative supply voltage pin. Normally - 5 volts ±10%.
Analog ground reference point for analog input signals. Normally connected to ground.
Digital ground reference point for digital input signals. Normally connected to ground.
The input bus to allow selection of the desired cutoff frequency. The value of the word presented to these pins
selects the cutoff frequency. It is latched in on the rising edge of CEo These are high impedance CMOS inputs
and can be bridged directly across a microprocessor data bus.
3.147
1
- _=.
I
GOULD
AIMII®Semiconductors
53529B
Pin Description (Continued)
Pin Name
Pin#
Function
CE
4
OSCi
OSCo
SIG 1N
14
15
12
FB
10
FLToUT
BUF 1N
BUFoUT
9
7
6
Chip Enable: This pin has 3 states. When CE is at VDD the data in the latch is presented to the ROM and the inputs have no effect. When CE is at ground the data presented on the inputs is read into the latch but the
previo~ data is still in the ROM. Returning CE to VDD presents the new data,to the ROM and fculol/changes.
When CE is at Vss the inputs go directly to the ROM, changing fCUIOff immediately. The configuration for a fixed
filter is: CE at Vss and the DO through 05 are tied to VDD or VSS/OGND depending on the desired fculoff.
Oscillator In and Oscillator Out. Placing a crystal and a 10MQ resistor across these pins creates the time base
oscillator. An inexpensive choice is to use the 3.58MHz TV crystal.
Signal Input. This is the inverting input of the input op amp. The non-inverting input is internally connected to
Analog Ground.
Feedback. This is the feedback point for the input op amp. The feedback resistor should be ~10kQ for proper
operation.
The high impedance output of the high pass filter. Load should be 10KQ.
. The inverting input of the buffer amplifier.
The buffer amplifier output to drive low impedance loads. Load should be ~600Q.
Example of Circuit Connection for 535298
Figure 2_ Microprocessor Interface
Figure 1. Stand Alone Operation
+5V
8~
v"
+sv
~
VI
lDMQ
3
oseo
2
1
835298
18
OUTPUT AMPLIFIER RESISTORS
1/
-5V
lDKQ .;; R
17
50
fe(KHz)
16
(KQ)
Des,
"'"
""
""
14
.VI
10MQ
83529B
AUDlOI"
AN'Jl.AUASING
AUDIO IN
ALTER
ANTI-ALIASING
FILTER
AUDIO OUT
SMOOTHING
"
ALTEII
-sv
AUDIO OUT
C=
21TRFc
-sv
3.148
-} GOULD
AIMII®Semiconductors
S3529B
Table 1. Standard Frequency Table: Programmable Filter S3529B,
Voice Band
Input
05.00
(HEX)
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
36
37
39
Divider
Ratio
fe
Actual
(Hz)
2048
895
447
298
224
179
149
128
112
99
89
81
74
69
64
60
56
53
50
47
45
43
41
39
37
36
34
33
32
31
30
29
28
27
26
25
24
23
40
91
182
273
363
455
546
635
726
822
914
1005
1099
1179
1271
1355
1453
1535
1627
1731
1808
1892
1985
2086
2198
2260
2392
2465
2543
2625
2712
2805
2905
3013
3129
3254
3389
3537
fclock
= 3.58MHz
Additional Points
Input Code
05. 00
(HEX)
OA
DB
DC
OD
DE
OF
1A
1B
1C
1D
1E
1F
2A
2B
2C
2D
2E
2F
35
38
3A
3B
3C
3D
3E
3F
f
fe
Actual
(Hz)
188
358
90
87
85
78
61
58
52
46
44
40
38
35
22
20
18
16
15
14
12
10
9
6
5
4
433
227
904
935
957
1043
1334
1402
1565
1768
1849
2034
2136
2325
3697
4067
4519
5085
5423
5811
6779
8135
9039
13559
16270
20338
= fclock
CUTOFF
Alternate Clock Configurations
If 3.58MHz is already available in the system it can be
applied directly as a logic level to the OSC IN (pin 14).
(Max. zero "'30% VDD , min. one"'70% Vss). Waveforms
not satisfying these logic levels can be capacitively
coupled to OSC 1N as long as the 10MQ feedback
resistor is installed as shown in Figure 3.
Divider
Ratio
44 (Divider Ratio)
Figure 3. External Driving S3529B Pin
05Co~
10MQ
53529B
+---1: ~
05Cj 1-1_4
L..-_ _~
3.149
ascI
15PF
TTL CLOCK
I
I
-
.
I
-) GOULD
AIMII®Semiconductors
S35298
Figure 4. Passband Detail, Control
te = 1005Hz
=
110010,
Figure 5. Loss Curve, Control = 110010,
te = 1005Hz
."~
0.40
0.30
"
0.20
.
0.10
,§
§
0.00
35
25
-0.10
-0.20
-0.30
\
-O.4D~,--+--+-+-,,-100-+--+--'001-'-+--->-'-+00::-'- -........--:18000
-5~'~-+--+-'+"'~--'+"-'+-""""-3+"-'-""""-'+"-'+-""""~5000
FREQUENCY (Hz)
FREOUENCY (Hz)
Figure 6. loss Response, DC to Clock Detail,
Control = 110010, te = 1005Hz
Figure 7. Cascaded 53528B and 53529B,
Control
100001
Bandpass Configuration-l0% Bandwidth
=
"
.
75
65
"
..
§
"
"
35
25
"
15
15
8800
17600
2f.tGO
352DO
44000
1500
3000
mEQUENCY [HZ)
FREQUENCY(IU)
3.150
4500
6000
-) GOULD
AIMII®Semiconductors
53529B
Figure 8. 53528B and 53529B in Parallel,
Notch Configuration-Narrow Bandwidth
Figure 9. 53528B and 53529B in Parallel,
Notch Configuration-Wide Bandwidth
75
..
65
65
"
55
45
45
,.
~ 35
25
15
15
-5~~~~+-~~~4-
o
1500
__~-+~____~~
3000
4500
-5~~-+~4-+-~-+~
o
6000
FREQUENCY 1HZ]
1500
__+-~-+~
3000
4500
__
+-~
6000
FREQUENCY [HZ)
Applications Information
The 83529B High Pass Filter has a very sharp 50dB drop off at f e . The Passband Ripple is less than O.5dB. Note that
unlike passive element filter, attenuation increases for sampled-data filters at the higher frequencies due to the sample
and hold effect. (feLocK = 44xfeuTOFF).
The 83529B High Pass Filter and the 83528B Low Pass Filter can be used together to make either Band Pass or Band
Reject filters. The control code selection determines the bandwidth of the resulting filter.
3.151
-) GOULD
AIMII®Semiconductors
53529B
Figure 10. Bandpass Application: General Case Configuration
SIGIN
OUT
Note:
- Anti·aliasing and smoothing filters on both chips A1, A2,
81, 82
• For same digital logic code
N = multiple of clock#1 to clock#2
- Lowpass after highpass to remove higher harmonics,
unless cosine input filter of lowpass needed to clean noisy in·
put signal
.
fel = .glcu
N
- For wider band width two different oscillators can be used.
- If filter clock (fclock) for lowpass is an integer multiple of
the fclock for highpass, then 81 and A2 may be removed
without causing beat frequencies.
Figure 11. Notch Applications: General Case Configuration.
SIGIN
835288
~.~.SIGNAL
SUMMATION
3.152
-} GOULD
AIMII®Semiconductors
S3529B
Applications Information
Anti-Aliasing
Figure 12. Sampling Theory
OVERSAMPlED
-10
fs = sampling frequency
fm = frequency bandwidth of message
-jm
1m
0
f
is
In planning an application the fundamentals of sampling devices must be considered.
o Make certain the harmonic image does not fold into
the desired pass band. I.e, Oversample.
o Bandlimit the input so that the input frequencies,
noise, and tails will not come too close to the clock and
be folded back into the pass band.
o
-3f.
- f, -1m
-2/,
1m II
D
Z/s
J/,
f
o For dynamic operation check for aliasing at each
cutoff frequency.
Figure 13. Avoiding Aliasing
1
en
-8
-f.
I
Bandlimit the output so that the image is sufficiently attenuated and the switched capacitor output is
smoothed. I.e., kill the higher order terms in the Fourier
Series.
f
f.
I
1
"DD~
- 28
f.=2D
28
f
fo = 0.58
-28 -8
- f. " " " " "
~I~
-48 -3D -28 -8
8
28
I UW%jIB
,.-,.",."",
f.
8
28
38
f. = 38
f
48
Note that crit,ical sampling avoids aliasing, but in the above example no real life filter
can separate the message from the image. One must oversample in real life.
Figure 14. Implementation'
iRCFILTERSMOOTllSS16NALOUlPllT
•
I'
.//6-T-o'~·:~,·:::·;
1
•
3.153
I
-
~:I
.
I
I
Industrial Temperature
CMOS Single Chip JL-LawI A-Law
Synchronous Combo CodecsWith Filters
GOULD
AIMII®Semiconductors
S35061/S35071/S3507AI
o
Features
o
o
o
o
o
o
o
o
Independent Transmit and Receive Sections
With 75dB Isolation
Low Power CMOS 80mW (Operating)
10mW (Standby)
Stable Voltage Reference On-Chip
Meets or Exceeds AT&T 03, and CCITT G.711,'
G.712 and G.733 Specifications
Input Analog Filter Eliminates Need for External
Anti-Aliasing Prefilter
Input/Output Op Amps for Programming Gain
Output Op Amp Provides ±3_1V into a 600n Load
or Can Be Switched Off for Reduced Power(70mW)
Special Idle Channel Noise Reduction Circuitry
for Crosstalk Suppression
o
Encoder has Dual-Speed Auto-Zero Loop for
Fast Acquisition on Power-up
Low Absolute Group Delay = 450"sec @ 1kHz
General Description
The S3506 and S3507 are monolithic silicon gate
CMOS Companding Encoder/Decoder chips designed
to implement the per channel voice frequency Codecs
used in PCM systems_ The chips contain the bandlimiting filters and the analog-digital conversion circuits that conform to the desired· transfer
characteristic. TheS3506 provides the European A-Law
companding and the S3507 provides the North
American wLaw companding characteristic.
Block Diagram
v•
.,..-+-__
Pin Configuration (22 Pin)
~
S35061
S3507
PCMOUT
.IN
BIN
"-_+--<>H/BSEL
\ -_ _ _ _ _ _ _ _ _ _-+-+<>fLTOIJT
Pin Configuration (28 Pin)
Vm
Voo(+5V)
,--___+---<
nU1-
T·AlB SEL
Vorr
OUT-
FlT OUT
PDO
V.
L _ _ _ _ _ _ _ _ _ _+--of.STROBE
1010+
ClKSEL
SYSCU:
CAl GNO
AGNO
A GNO
Vss(-5V)
peM IN
3.154
-) GOULD
AIMII®Semiconductors
S35061/S35071/S3507AI
General Description (Continued)
These circuits provide the interface between the analog
signals of the subscriber loop and the digital signals of
the PCM highway in a digital telephone switching
system. The devices operate from dual power supplies
of ±5V.
.
In 22-pin cerdip or ceramic packages (0400" centers) the
S3506/S3507 are ideally suited for PCM applications: Exchange, PABX, or Digital Telephone as well as fiber optic
and other non-telephone uses. A 28-pin version, the
S3507A, provides standard WLaw AlB signaling capability. These devices are also available in a 28-pin chip carrier.
For a sampling rate of 8kHz, PCM input/output data rate
can vary from 64kb/s to 2.1 Mb/s. Separate transmit!
receive timing allows synchronous or time-slot asynchronous operation.
Absolute Maximum Ratings
DC Supply Voltage VDD ...................................................................................................................................... + 6.0V
DC Supply Voltage Vss ......................................................................................................................................... - 6.0V
Operating Temperature ..................................................................................................................... -40°C to +85°C
Storage Temperature ...................................................................................................................... - 65°C to + 150°C
Power Dissipation at 25°C .............................................................................................................................. 1000mW
Digitallnput ......................................................................................................................... Vss - 0.3<;;V1N <;;VDD + 0.3
Analog Input ........................................................................................................................ Vss - 0.3<;;V1N<;;VDD + 0.3
Electrical Operating Characteristics (TA =-46° to 90°C)
Power Supply Requirements
Symbol
Parameter
Voo
Positive Supply
Min.
Vss
Negative Supply
PaPR
Power Dissipation (Operating)
80
PaPR
Power Dissipation (Operating
wlo Output Op Amp
70
PSTBY
Power Dissipation (Standby)
10
Typ.
Max.
Units
4.75
5.0
5.25
V
-4.75
-5.0
-5.25
V
140
mW
Conditions
mW
Voo
=
25
mW
Voo
=-
5.0V
5.0V
AC Characteristics (Refer to Figures 3A and 4A)
Symbol
Parameter
Min.
Typ.
Max.
Units
40
50
60
%
2.048
MHz
60
%
DSYS
System Clock Duty Cycle
Isc
Shift Clock Frequency
0.064
Dsc
Shift Clock Duty Cycle
40
trc
Shift Clock Rise Time
100
ns
tic
Shift Clock Fall Time
100
ns
trs
Strobe Rise Time
100
ns
lts
Strobe Fall Time
100
ns
tsc
Shift Clock to Strobe (On) Delay
tsw
Strobe Width
-100
600ns
3.155
50
0
200
ns
124.31-1s
@2.048
MHz
Conditions
700ns min
@1.544MHz
I
I
- :-
-} GOULD
AIMII®Semiconductors
S35061/S35071/S3507AI
AC Characteristics (continued) (Refer to Figures 3A and 4A)
Symbol
Parameter
tcd
T-Shift Clock to PCM OUT Delay
tdc
R-Shift Clock to PCM IN Set-Up Time
Min.
Typ.
Max.
Units
100
150
ns
60
Conditions
1OOpF,
510Q Load
ns
trd
PCM Output Rise Time CL = 100pF
50
100
ns
to 3V; 510Q to VDD
tid
PCM Output Fall Time CL= 100pF
50
100
ns
to .4V; 510Q to VDD
tdss
AI B Select to Strobe Trailing Edge
Set-up Time
DC Characteristics (VDD
100
= + 5V, Vss = - 5V)
Symbol
Parameter
Min.
RINA
CIN
Analog Input Resistance IN +, IN-
100
IINL
IINH
IINL
IINH
VIL
ns
Typ.
Units
Conditions
KQ
7
Input Capacitance to Ground
Max.
R-Shift Clock, T-Shift Clock, PCM IN,
System Clock, Strobe, PDN
Logic Input Low Current
Logic Input High Current
T-A/B SEL, A IN, BIN, R-AiB SEL
Logic Input Low Current
Logic Input High Current
Logic Input" Low" Voltage
15
pF
All Logic and
Analog Inputs
1
1
/-IA
/-IA
VIL
VIH
= 0.8V
= 2.0V
600
600
/-IA
/-IA
V
VIL
VIH
= 0.8V
= 2.0V
0.8
VIH
Logic Input "High" Voltage
2.0
VOL
Logic Output" Low" Voltage
(PCM Out)
0,4:
V
V
51 OQ Pull-up to
VDD + 2 LSTTL
VOL
VOH
Logic Output "Low" Voltage (AlB OUT)
0.4
V
IOL
=
Logic Output" High" Voltage
2.4
V
IOH
= 40/-iA
RL
Output Load Resistance VOUT
600
Q
1.6mA
TransmissIOn Delays
Symbol
Parameter
Min.
Encoder
Decoder
30
Typ.
Max.
Units
Conditions
125
/-Is
From TSTROBE to
the Start of Digital
Transmitting
8T +25
/-Is
Transmit Section Filter
182
/-Is
T = Period in /-Is of
RSHIFT CLOCK
@lkHz
Receive Section Filter
110
/-Is
@lkHz
3,156
-} GOULD
AIMII®semiconductors
S35061/S35071/S3507AI
S3506 Single-Chip A·Law Filter/Codec Performance
Symbol
Parameter
ICN w
ICNs F
Idle Channel Noise (Weighted Noise)
Idle Channel Noise
(Single Frequency Noise)
Idle Channel Noise (Receive Section)
ICN R
IMD2F
IMDpF
Typ.
Max.
-85
-66.5
-60
dBmOp
dBmO
CCITT G.712 4.1
CCITT G.712 4.2
-74
dBmOp
CCITT G.712 4.3
Spurious Out-ot-Band Signals at
Channel Output
-28
dBmO
CCITT G.712 6.1
Intermodulation (2 Tone method)
Intermodulation
(1 Tone + Power Frequency)
-35
-49
dBm
dBm
CCITT G.712 7.1
CCITT G. 7127.2
Spurious In-Band Signals at the
Channel Output Port
-40
dBmO
CCITT G.712 9
CCITT G.71211
Min.
Interchannel Crosstalk V1N - VO UT
75
Units
Conditions
80
dB
V1N(Max)
Max Coding Analog Input Level
±3.1
VOpk
VOUT
(Max)
Max Coding Analog Output Level
±3.1
VOpk
RL = 6000
AD
Absolute Delay End-to-End @ 1KHz
450
500
/1sec
@ OdBmO
ED
Envelope
500 to 600Hz
200
750
/1sec
Relative to Mini-
Delay
600 to 1000Hz
120
375
/1sec
mum Delay
Distortion
1000Hz to 2600Hz
110
125
/1sec
Frequency
160
750
/1sec
Signal to
oto
Total
Distortion
2600Hz to 2800Hz
SD
33.5
39
dB
Method 2 - Sine-
-40dBmO
27.5
31
dB
wave Signal Used
-45dBmO
22.5
26
- 30dBmO
dB
FR
Frequency Response 300Hz to 3000Hz
GT
Gain Tracking with Input Level
Variations (End-to-End. Each halt
channel is one halt this value.)
±0.2
±0.4
± 1.0
Gain Variation with Temperature
and Power Supply Variation
±0.25
Transmit Gain Repeatability
±0.1
±0.2
Receive Gain Repeatability
±0.1
±0.2
OTLPR
Zero Transmission Level Point
(Decoder See Figure 1)
1.51
VRMS
VOUT Digital Milliwatt Response
OTLPT
Zero Transmission Level Point
(Encoder See Figure 1)
1.51
VRMS
V1N to Yield Same
as Digital Milliwatt Response at
Decoder
AG
3.157
±.25
dB
±0.5
± 1.0
±3.0
dB
+3 to -40 dBmO
-45 to -50 dBmO
-55dBmO
dB
dB
dB
1
- _=.
,
-} GOULD
AIMII®Semiconductors
S35061/S35071/S3507AI
S3507/S3507A Single-Chip p.-Law Filter/Codec Performance
Symbol
Parameter
ICN w
ICN sF
ICN R
Idle Channel Noise (Weighted Noise)
Idle Channel Noise (Single Frequency Noise)
Idle Channel Noise (Receive Section)
Spurious Out-of-Band Signals at
the Channel Output
OTLP T
Zero Transmission Level Point
(Encoder See Figure 1)
1.51
VRMS
V1N to Yield Same
as Digital Milliwatt
Response at Decoder
DTLP R
Zero Transmission Level Point
(Decoder See Figure 1)
1A4
VRMS
VOUT Digital Milliwatt
Response
AD
Absolute Delay End-to-End
ED
Envelope
SO
Min.
Typ.
5
Max.
-6.6.5
-60
-74
-28
1KHz
450
500
Ilsec
@
200
120
750
Delay
500 to 600Hz
600 to 1000Hz
375
Ilsec
Ilsec
Relative to
Minimum
Distortion
1000Hz to 2600Hz
110
125
Ilsec
Delay
2600Hz to 2800Hz
160
750
Ilsec
dB
Frequency
@
Signal to
o to
Total
Distortion
-40dBmO
- 45dBmO
-30dBmO
33.5
27.5
22.5
39
. 31
dB
Frequency Response 300Hz to 3000Hz
±.25
dB
IMD2F
IMDpF
Intermodulation (2Tone method)
Intermodulation (1 Tone + Power Frequency)
Spurious In-Band Signals at the
Channel Output Port
Interchannel Crosstalk V1N - VOUT
-35
-49
-40
dBm
dBm
dBmO
80
dB
V1N(Max)
VOUT(Max
GT
Max Coding Analog Input Level
Max Coding Analog Output Level
±3.1
±3.1
Gain Tracking with Input Level Variations
(End-to-End. Each Half Channel is One
Half of this Value.)
±0.2
±0.5
±1.0
±3.0
VO pk
VO pk
dB
dB
dB
75.
±OA
±1.0
Gain Variation with Temperature
and Power Supply Variation
Transmit Gain Repeatability
Receive Gain Repeatability
dB
±0.25
±0.1
±0.1
3.158
OdBmO
dB
26
FR
LG
Conditions .
Units
. dBmO
dBmO
dBmO·
dBmO
±0.2
±0.2
dB
dB
RL = 600f!
. +3 to -40 dBmO
-45 to -50 dBmO
-55 dBmO
-} GOULD
AIMII®Semiconductors
S35061/S35071/S3507AI
Pin/Function Descriptions
Pin
S3506/S3507
S3507A
Description
SYS ClK
4
5
T-SHIFT
3
4
R-SHIFT
9
13
System Clock-This pin is a TTL compatible input for a 256kHz, 1.544MHz, 2048MHz,
or 1.536MHz clock that is divided down to provide the filter clocks. The status of ClK
SEl pin must correspond to the provided clock frequency.
Transmit Shift Clock- This TTL compatible input shifts PCM data out of the coder on
the positive going edges after receiving a positive edge on the T-STROBE input. The
clocking rate can vary from 64kHz to 2.048MHz.
Receive Shift Clock- This TTL compatible input shifts PCM data into the decoder on
the negative going edges after receiving a positive edge on the R-STROBE input. The
clocking rate can vary from 64kHz to 2.048MHz.
T-STROBE
5
6
R-STROBE
10
14
ClK SEl
2
3
Clock Select-This pin selects the proper divide ratios to utilize either 256kHz,
1.544MHz, 2.048MHz, or 1.536MHz as the system clock. The pin is tied to Voo
(+ 5V) for 2.048MHz, to Vss (- 5V) for 1.544MHz or 1.536MHz operation, or to 0
GND for 256kHz operation.
PCM OUT
6
7
PCM Output- This is a lS-TTL compatible open-drain output. It is active only during
transmission of PCM output for 8 bit periods of T-SHIFT clock signal following a
positive edge of the T-STROBE input. Data is clocked out by the positive edge of the
T-SHIFT clock into one 510Q pull-up per system plus 2 LS-TTL inputs.
PCM IN
11
15
PCM Input-This is a TTL compatible input for supplying PCM input data to the
decoder. Data is clocked in by the negative edge of T-SHIFT clock.
CAZ
CAZ GND
8
14
11
18
VREF
1
28
IN+
INV1N
15
16
17
19
20
21
FLT OUT
19
23
Auto Zero-A capacitor of 0.1J.lF ± 20% should be connected between these pins for
coder auto zero operation. Sign bit of the PCM data is integrated and fed back to the
comparator for DC offset cancellation ..
Voltage Reference-Output of the internal band-gap reference voltage .(::::- 3.075V)
generator is' brought out to VREF pin. Do not load this pin.
These pins are for analog input signals in the range 01.- VREF to + VREF . IN - and
IN + are the inputs of a high input impedance op amp and V1N is the output of this op
amp. These three pins allow the user complete control over the input stage so that it
can be connected as a unity gain amplifier, amplifier with gain, amplifier with adjustable gain or as a differential input amplifier. The adjustable gain configuration will
facilitate calibration of the transmit channel. V1N should not be loaded by less than 47K
. ohms.
Filter Out- This is the output of the low pass filter which represents the recreated
analog signal from the .received PCM data words. The filter sample frequency of
256kHz is down 37dB at this point. This is a high impedance output which can be
used by itself or connected to the output amplifier stage which has a low output impedance. It should not be loaded by less than 47K ohms, or the Digital MilliWatt
response will fall off slightly.
Transmit Strobe-This TTL compatible pulse input (8kHz) is used for analog sampling
and for initiating the PCM output from the coder. It must be synchronized with the
T-SHIFT clock with its positive going edges occurring with the positive edge of the shift
clock. The width of this signal is not critical. An internal bit counter generates the
necessary timing for PCM output.
Receive Strobe'- This TTL compatible pulse input (8kHz) initiates clocking of PCM
input data into the decoder. It must be synchronized with the R-SHIFT clock with its
positive going edges occurring with the positive edge of the shift clock. The width of
the signal is not critical. An internal bit counter generates necessary timing for PCM
input.
3.159
I·:
-
.
I
-) GOULD
AIMII®Semiconductors
S35061/S35071/S3507AI
Pin/Function Descriptions (Continued)
Pin
83506183507 83507A
Description
OUT VOUT
20
21
24
25
These two pins are the output and input of the uncommitted output amplifier stage. Signal
at the FLT OUT pin can be connected to this amplifier to realize a low output impedance
with unity gain, increased gain or reduced gain. This allows easier calibration of the
receive channel. The VOUT pin has the capability of driving OdBm into a 600!'lload. (See
Figure 1). If OUT - is connected directly to Vss the op amp will be powered down, reducing power consumption by 10mW, typically.
Voo
Vss
22
12
27
16
These are power supply pins. Voo and Vss are positive and negative supply pins, repectively (typ. +5V, -5V). VOD should be applied first.
A GND
D GND
PDN
13
7
18
17
8
22
Analog and digital ground pins are separate for minimizing crosstalk.
--
A IN
B IN
T-AiB SEL
2
1.
26
A OUT
BOUT
R-AiB SEL
10
9
12
Power Down-This TTL compatible input when held low puts the chip into the powered
down mode regardless of strobes. The chip will also power down if the strobes stop. The
strobes can be high or low, but as long as they are static, the powered down mode is in
effect. Should be tied to +5 when not used.
The transmit AlB select input selects the A signal input on a positive transition and the B
signal input on the negative transition. These inputs are TTL compatible. The AlB signaling
bits are sent in bit 8 of the PCM word in the frame following the frame in which T-AiB SEL inpiJt makes atransition. Acommon AlB select input can be used for all channels in a multiplex
operation, since it is synchronized to the T-STROBE input in each device.
In the decoder the AlB signaling bits received in the PCM input word are latched to the
respective outputs inthe same frame in which the R-AB SEL input makes a transition. A bit
is latched on a positive transition and B bit is latched on a negative transition. A common
AlB select input can be used for all channels in a multiplex operation .
.
Functional Description
The simplified block diagram of the 83506183507
appears on page one. The device contains independent
circuitry for processing transmit and receive signals.
8witched capacitor filters provide the necessary band- .
width limiting of voice signa'ls in both directions. Circuitry for coding and decoding operates on the princi'
pie of successive approximation, using charge redistribution in a binary weighted capacitor array to define
segments and a resistor chain to define steps. A bandgap voltage generator supplies the reference level for
the conversion process.
Transmit Section
256kHz, followed by a 3rd Order High-Pass Filter clocked at 64kHz. The resulting band-pass characteristics
meet the CCITT G.711, G.712 and G.733 specifications.
80me representative attenuations are >26dB (typ) from
to 60Hz and >35dB (typ) from 4.6kHz to 100kHz. The
output of the high pass filter is sampled by a capacitor
array at the sampling rate of 8kHz. The polarity of the in. coming signal selects the appropriate polarity of the
reference voltage. The successive approximation
analog-to-digital conversion process requires 9V2 clock
cycles, or about 72lls. A switched capacitor dual-speed,
auto-zero loop using a small' non-critical external
capacitor (0.1IlF) provides DC offset cancellation by integrating the sign bit of the PCM data and feeding it
back to the non-inverting input of the comparator.
Input analog signals first enter the chip at the
uncommitted op amp terminals. This op amp allows
gain trim to be used to set OTLP in the system. From the
VIN pin the Signal enters the 2nd order analog antialiasing filter. This filter eliminates the need for any offchip filtering as it provides attenuation of 34dB (typ.) at
256kHz and 46dB (typ.) at 512Hz. From the Cosine Filter
the signal enters a 5th Order Low-Pass Filter clocked at
3.160
o
The PCM data word is formatted according to the wlaw
companding curve for the 83507 with the sign bit and
the ones complement of the 7 magnitude bits according to the AT&T D3 specification. In the 83506 the PCM
data word is formatted according to the A-Law companding curve with alternate mark inversion (AMI),
meaning that the even bits are inverted per CCITT
specifications.
-) GOULD
AMII®Semiconductors
S35061/S35071/S3507AI
Included in the circuitry of the S3507/S3507A is "All
Zero" code suppression so that negative input signal
values between decision value numbers 127 and 128
are encoded as 00000010. This prevents loss of
repeater synchronization by T1 line clock recovery circuitry as there are never more than 15 consecutive
zeros. The 8-bit PCM data is clocked out by the transmit
shift clock which can vary from 64kHz to 2.048MHz.
Idle Channel Noise Suppression
An additional feature of the CODEC is a special circuit
to eliminate any transmitted idle channel noise during
quiet periods. When the input of the chip is such that
for 250m sec. the only code words generated were + 0,
-0, +1, or ~1, the output word will be a +0. The
steady + 0 state prevents alternating sign bits or LSB
from toggling and thus results in a quieter signal at the
decoder. Upon detection of a different value, the output
resumes normal operation, resetting the 250msec.
timer. This feature is a form of Idle Channel Noise or
Crosstalk Suppression. It is of particular importance in
the 83506 A-Law version because the A-Law transfer
characteristic has "mid-riser" bias which enhances low
level signals from crosstalk.
Receive Section
A receive shift clock, variable between the frequencies
of 64kHz to 2.048MHz, clocks the PCM data into the input buffer register once every sampling period. A
charge proportional to the received PCM data word
appears on the decoder capacitor array. A sample and
hold initialized to zero by a narrow pulse at the beginning of each sampling period integrates the charge and
holds for the rest of the sampling period. A switchedcapacitor 5th Order Low-Pass Filter clocked at 256kHz
smooths the sampled and held signal. It also performs
the loss equalization to compensate for the sin xix
distortion due to the sample and hold operation. The
filter output is available for driving electronic hybrids
directly as long as the impedance is greater than 47kQ.
When used in this fashion the low impedance output
amp can be switched off for a savings in pow.er consumption. When it is required to drive a 600Q load the
output is configured as shown in Figure 1 allowing gain
trimming as well as impedance matching. With this
configuration a transmission level of OdBm can be
delivered into the load with the +3.14dB or +3.17dB
overload level being the maximum expected 'level.
Figure 1. 53507 Input/Output Reference Signal Levels
~
lID
/
47.5Kn
FLT OUT
+" "00 /
AID
f-:P::::CM~OU~T--..!....-P-:C-:M-IN~
>-t---4>----'+-[ID
DlA
600n
Load
TIle resistors are illustrated for a OdBm IN/OdBm OUT system, Point [K} bridges a GOOn termination and Point [jj] drives a 6001lioad (tnustrated), The
OdBm level ~ro.duces the e.qulvalent digital mllliwaH code al Point II] as defined in the AT&T and CetTY specifications for PCM. This is cailed the
zero transmiSSion level pOint Dr OTlP and 3.17dB of Dvedoad capability remains before saturation occurs.
VoHage for
OTLP
.775VRMS
1.lDVpk
1.51VRMS
2.13Vpk
1.44VRMS
2.04Vpk
.775VRMS
1.10Vpk
VoHage for
Saturation
1,12VRMS
1.58Vpk
2,17VRMS
3.075Vpk
2,07VRMS
2.93Vpk
1.12VRMS
1,58Vpk
3.161
Digital MiWwatt
' Code per AT& TICCfTT
Saturation
Cod.s
1
- _=.
!
-) GOULD
AIMII®Semiconductors
S35061/S35071/S3507AI
shifted. It is reset on the leading (+) edges of the.
strobe, forcing the PCM output in a high impedance
state after the 8th bit is shifted out. This allows the
strobe signal to have any duty cycle as long as its
repetition rate is 8kHz and transmit/receive shift clocks
are synchronized to it. Figure 2 shows the waveforms in
typical multiplexed uses of the CODEC.
Power Down Logic
Powering down the. CODEC .can be done in several
ways. The most direct is to drive the PDN pin to a.low
level. Stopping both the transmit strobe and the receive
strobe will also put the chip into the stand·by mode.
The strobes can be held high or low.
Voltage Reference Circuitry
A temperature compensated band-gap voltage
generator ( - 3.075V) provides a stable reference for the
coder and decoder. Two amplifiers buffer the reference
and supply the ·coder and decoder independently to
minimize crosstalk. This reference voltage is trimmed
during assembly to ensure a minimum gain error of
:;!: 0.2dB due to all causes. The VREF .pin should not be
connected to any load.
Power Supply and Clock Application .
For proper 9peration Voo and Vss sh'ould be applied
simultaneously. If not -possible, then Vss shouid be
applied first. To avoid forward-biasing the device the
clock voltages should notbe applied before the power
supply voltages are stable. When cards must be plugged into a "hot" system it may be necessary to install
1000Q current-limiting resistors in series with the clock
lines to prevent latch-up.
Timing Requirements
The internal design of the Single-Chip CODEC paid
careful attention to the timing requirements of various
systems. In North America, central office and channelbank designs follow the American Telephone and Telegraph Company's T1 Carrier PCM format to multiplex
24 voice channell'-at a data rate of 1.544Mb/s. PABX
designs, on the other hand, may use their own multiplexing formats with different data rates. Yet, in digital
telephone designs, CODEC'smay be used in a nonmultiplexed form with a data rate as low as 64kb/s. The
S3507 and S3507A fill these requirements.
In Europe, telephone exchange and channelbank
designs follow the CCITT carrier PCM format to multiplex 30 voice channels at a data rate of 2.048Mb/s. The
S3506 is designed for this market and will also handle
PABX and digital telephone applications requiring the
A-Law transfer characteristics.
The timing format chosen for the AMI Codec allows
operation in both multiplexed or'non-multiplexed form
with data rates variable from 64kb/s to 2.048Mb/s. Use
of separate internal clocks for filters and for shifting of
PCM input/output data allows the variable data rate
capability. Additionally, the S3506/S3507 does not require that the 8kHz transmit and' ..receive sampling
strobes be exactly 8 bit periods wide. The device has an
internal bit counter that counts the number of data bits
System Clock
The basic timing of. the Codec is provided by the
system clock. This 2.048MHz, 1.544MHz, or 256kHz
clock is divided down internally to provide the various
filter clocks and the timing for the conversions. In most
systems this clock will also be used as the, shift clock
to clock in and ounhe data. However, the shift clock can
actually be between 64kHz and 2.048MHz as long as one
of the system clock frequencies is provided, Independent
strobes and shift clocks allow asynchronous time slot operation of transmit and receive, The 3507 will also operate
with a 1.536MHz system clock; as used in some PABX
systems, with the ClK SEl pin in the 1.544MHz Mode.
Signaling in /A"law Systems
The 83506 and S3507are compact 22-pin devices to
meet the two worldwide· PCM 'standards. In J.l-Law
systems there can be a requirement for signaling information to be carried in the bit stream with the coded
analog data. This coding scheme is sometimes called
7-5/6 bit rather than 8 bit because the l8B of every 6th
frame is replaced by a signaling bit. This is referred to
as AlB Signaling and if a signaling frame carries the "A"
bit, then 6 frames later the lSB will carry the "B" bit. To
meet this requirement, the S3507A is available in a
28-pin dip package, or in a 28-pin chip carrier, as 6 more
pins are required for the inputs and outputs of the AlB
-signaling.
3.162
Pin Configuration-S3507A 28-Lead Chip Carrier
CAl GND
A GND
Vss (-5V)
BI"
peM IN
iI·STROBE
AIN
II·SHln
eLK SEL
R·A/B SEl
r·SHIFT
, TOP VIEW
ill
:; ~
"~
§ § J
0
c
.y
GOULD
AIMII®Semiconductors
S35061/S35071/S3507AI
Figure 2A. Wavefonns in a 24 Channel PCM System
'.544MHI SHIFT CLOCK
~
I
I
I
I
I
I
~JHi241
I
S
I
I
I
I
I
:
C~·'12
I
3
I 4 I 5 I 61
7
I
8
c~.21 2 [~:'~~~-ICHrl
2I
3
I 4 I 5.1
6
I7 I8
!,
SI
TRANSMIT/RECEIVE PCM HIGHWAY
~~~==~----~----~~
FRAME RESET PULSE
--lw---r-----L.!~4___------..--l1
_--..l"I·;......--______
CH.' STROBE
CH.2 STROBE
CH.24 STROBE
NOTE:
tw MIN=200ns, Iw MAX=124.8jJs.
Figure 28. Waveforms in 30 Channel PCM System
2.04BMHz SHIFT CLOCK
~J
I
:
~T: I
=~~~~~~~.~I-=-S1;-;;;L.....OI:32=1'I. . .-_'.J...--'..4==:1=6=-1~':~:+-1---,""
ST1
I
PCM BIT STREAM
-ill..---F"':R-:'A:":M""E.,.,RE"':S'::ET::-P-oU"'"L.,.,SE---......- - - - - - - - -
,
------------~nI
I
~'"""'_-------tw-----.-----~
TIME SLOT .8'STROBE (FRAME ALIGNMENT SIGNAL)
.. - - - - - - - - - - - - - - - - - - '
TIME SLOT 1 STROBE (CHANNEL 1)
TIME SLOT 31 STROBE (CHANNEL 30)
NOTE:
3.163
200ns';;Tw';;124.B~sec
1
- _=.
I
-) GOULD
AIMII®Semiconductors
S35061/S35071/S3507AI
Figure 2C. Waveform Details
if-- /-- =1--------------------\
~ ~trs
-...J
l----tfs
tsw
STROBE
tse(tss) .-J
!-i--I.-J t+--tse(-Iss)
I
I
.
I
.
I
.
I
I
I
I..-t'e
\\:!J
il!:
DATA OUT
I
: - ted
I
BIT 1
I
I
~
BIT 2
I I
tde-~tde
I
: It,d;
I
I
I ~
--lI ~
BIT 5
,-+~\_---------J/r------
~ '....
DATA-,-N---------"""""'\
/:
4-:----f::
~,--:::BI::-'T3:----:::BI:;'"T
t'd
t,d""
~:..- t'd;
'
I
*In this example, the shift clock is the system clock (1.544 or 2.048MHz). In systems where the data shift rate is not the same, the relationship 01 each to the strobe
remains the same. The system clock and shift clock must relale 10 Ihe strobe within Ihe Ise, Iss liming requiremenls.
The effect of the strobe occurring after the shift clock is
to shorten the first (sign) bit at the data output.
The length of the strobe is not critical. It must be at a
logic state longer than one system clock cycle.
Therefore, the minimum would be >488ns at 2.048 and
the maximum <124.3Ilsec at 1.544MHz.
Icw
MIN
MAX
195nsec.
9.38I'sec.
lOOns
Irs
lOOns
lIs
Isdlss)
-100nsec.
I rc
200ns
lOOns
lOOns
Ilc
Isw
600ns*
124.3I'sec.
Icd
100nsec.
150ns
Idc(setup time, hold time)
60nsec.
trdi
lOOns
tldi
lOOns
:(:That is, the strobe can precede the shift clock by 200nsec, or 'allow it by as
much as 100nsec.
*@2.048MHz 700ns @1.S44MHz
Signaling Interface
In the AT&T T1 carrier PCM format an .AlB signaling
method conveys channel information. It might include
the on·or·off hook status of the channel, dial pulsing (10
or 20 pulses per second), loop closure, ring ground,
etc., depending on the application. Two signaling con·
ditions (A and B) per channel, giving four possible signaling states per channel are repeated every 12 frames
(1.5 milliseconds). The A signaling condition is sent in
bit 8 of all 24 channels in frame 6. The B signaling conditions is sent in frame 12. In each frame, bit 193 (the S
bit) performs the terminal framing function and serves
.
to identify frames 6 and 12.
The S3507A in a 28-pin package is designed to simplify
the signaling interface. For example, the AlB select input pins are tra.nsition sensitive. The transmit AlB
select pin selects the A signal input on a positive transition and the B signal input on the negative transition.
Internally, the device synchronizes the AlB select input
with the strobe signal. As a result, a common AlB select
signal can be used for all 24 transmit channels in the
channelbank. The A and B signaling bits are sent in the
frame following the frame in which the AlB select input
makes the transition. Therefore, AlB select input must
go positive in the beginning of frame 5 and the negative
in the beginning of frame 11 (see Figure 3).
3.164
-} GOULD
AIMII®Semiconductors
S35061/S35071/S3507AI
Figure 3. Signaling Waveforms in a T1 Carrier System
1
B BITS/CHANNEL
- _=.
24 CHANNElS/FRAME
I
i"'1__
· ~---------SUPERFRAME-----------+l·1
TRANSMIT A/B SElECT INPUT
RECEIVE AlB SELECT INPUT
Figure 3A. Signaling Waveform Details
I+--FRAME-------I
I+--FP'ME-----+1
TSTROBE
I
I
~
PCM OUT
I
~
MSB~
I
LSD
ildssl
~
r-----------1~-----~III-'ll'-----------~--f+--Isin---.\
T·AfB SEL
I .
~
----~
~
I
A SIGNALING INFORMATION
TRANSMITIED AS LSB
B SIGNAL IN
I
SHIFT CLOCK
3.165
~ B SIGNALING INFORMATION
---->R=
~
t"os
,~
RSTROBE'
I
~tsin~ j .
TRANSMITTED AS LSB
-) GOULD
AIMII®Semiconductors
S35061/S35071/S3507AI
Figure 4. A Subscriber Line Interface Circuit
R:=====+===~------I
r.:-:--1---':C+-_'''-17 ANA. GND
S35D7A
16 Vss
3 ClKSEl
CAZ 11
8 DIG.GND
tAzGND
18
PCMIN
RstROBf
R·A/B5El
(1.544MHJjSHIFTCLOCK - - - - - "
The decoder uses a similar scheme for receiving the A
and B signaling bits, with one difference. They are lat·
ched to the respective outputs in the same frame in
which the AlB select input makes a transition. There·
fore, the receive A/B select input must go high at the
beginning of frame 6 and go low at the beginning of
frame 12.
Applications Examples
There are two major categories of Codec applications.
Central office, channel bank and PABX applications us·
ing a multiplex scheme, and digital telephone type
dedicated applications. Minor applications are various
AlD or D/A needs where the 8 bit word size is desirable
. for I1P interface and fiber optic multiplex systems
where non·standard data rates may be used.
A Subscriber line Interface Circuit
. Figure 4 shows a typical diagram of a subscriber line
interface circuit using the S3507 A. The major elements
3.166
of such a circuit used in the central office or PABX are a
two·to·four wire converter, PCM Codec with filters
(S3507A) and circuitry for line supervision and control.
The two·to-fourwire converter- generally implemented
by a transformer·resistor hybrid-provides the inter·
face between the two-wire analog subscriber loop and
the digital signals of the time·division-multiplexed PCM
highways. It also supplies battery feed to the sub·
scriber telephone. The line supervision and control circuitry provides off·hook and disconnect supervision,
generates ringing and decodes rotary dial pulses. It
supplies the AlB signaling bits to the coder for trans·
mission within the PCM voice words. It receives AlB
signaling outputs from the decoder and operates the
AlB signaling relays .
In the T1 carrier system, 24 voice channels are multiplexed to form the transmit and receive highways, 8
data bits from each channel plus a framing bit called
the S bit form a 193 bit frame. Since each channel is
sampled 8000 times per second, the resultant data rate
is 1.544Mb/s.
-) GOULD
AIMII®Semiconductors
S35061/S35071/S3507AI
signals for the associated Codec under control of a
central processor. Alternatively, a common circuitry
within the channelbank can generate the timing signals
for all channels. Generation of the timing signals for the
83506 and 83507 is straightforward because of the simplified timing requirements (see Timing Requirements
for details). Figures 5 and 5A show design schemes for
generating these timing signals in a common circuitry.
Note that only three signals: a shift clock, a frame reset
pulse (coincident with the 8 bit) and a superframe reset
pulse (coincident with the 8 bit in Frame 1) are needed.
These signals are generated by clock recovery circuitry in
the channelbank. 8ince the Gould Codec does not need
channel strobes to be exactly 8-bit periods wide, extra
decoding circuitry is not needed.
Within the channel bank the transmit and receive channels of a Codec can occupy the same time slot for a
synchronous operation or they can be independent of
each other for time slot asynchronous operation. Asynchronous operation helps minimize switching delays
through the system. 8ince the strobe or sync pulse for
the coder and decoder sections is independent of each
other in the 83507 A, it can be operated in either manner.
In the CCITI carrier system, 30 voice channels and 2
framing and signaling channels are multiplexed to form
the transmit and receive PCM highways, 8 data bits
from each channel. 8ince each channel is sampled
8000 times per second, the resultant data rate is
2.048Mb/s.
The line supervision and control circuitry within each
subscriber line interface can generate all the timing
Figure 5_ Generating Timing Signals in a T1 Carrier System
SUPERFRAME
RESHP>-UlCCC
"---------:----
1 544MHz
>--
SHIFT eLK
REe AlB
FRAME
RESETP·U"l::-"-~
"
'-+-+--1 0,
-+--1--1 0;
. . . .-+--1--1 0,
a;
. . . .---+-+--1
TR AlDSI
ST81 . . . .
5T813 . . . .
5182
51814
SR2
0,
"
0,
0;
0,
a;
SRJ
0,
iii
o.
a.
"III
R
0,
0,
STBll
~----I
STB2J~_
_ _-I
STB12~----I
5TB24
~_
_---,--I
a;
S..
0,
iii
o.
a.
3.167
-} GOULD
AIMII®Semiconductors
S35061/S35071/S3507AI
Figure SA. Generating Timing Signals in a CCITT Carrier System (30 + 2 Channels)
TIME SLOT STROBES
o
4
1,6
20
1
S
17
,
21
2
6
18
.'
22
3
7
t 23
11l
T
2048kHz
CK
01
FRAME RESET
-
-
r-
Cl
04
74175
01
74175
"-
74175
01
CK
Cl
CK
Cl
CK
Cl
CK
Cl
-
.
74175
01
r-
! 24J
74175
01
1\
-
J
28
13
9
29
25
10
14
26
30
15
11
27
3.168
31
-) GOULD
AIMII®Semiconductors
S35061/S35071/S3507AI
A Digital Telephone Application
Most new PABX designs are using PCM techniques for
voice switching with an increasing trend toward applying them at the telephone level. The simplest form of a
digital telephone design uses four wire pairs to interface to the switch. Two pairs carry transmit and receive
PCM voice data. One pair supplies an 8kHz synchronizing clock signal and the remaining pair supplies power
to the telephone. More sophisticated designs reduce
costs by time-division-multiplexing and superimposition techniques which minimize the number of wire pairs.
The Gould Single-Chip Codec is ideally suited for this
application because of the low component count and its
simplified timing requirements. Figure 6 shows a schematic for a typical digital telephone design.
I
Since asynchronous operation is not necessary,
transmit and receive timing signals are common. A
phase-lock-loop derives the 256kHz system clock and
64kHz shift clock from the 8kHz synchronizing signal
received from the switch. The synchronizing signal
also serves as the transmit/receive strobe signal since
its duty cycle is not important for Codec operation.
Microphone output feeds directly into the coder input
while the decoder output drives the receiver through
an impedance transformer to complete the design.
I
Figure 6. A Digital Telephone Application
+5V
-5\1
+"
1
510Q
peM
83506 OR
S3501
CODEC
W/FILTER
6
:::IN r'--""'---______ ::::::IT INTERFACE
SWITCH
TSTROBE 5
_SYNC
SYS elK
I
1+-_ _--.
-5V
C21"JtF
-5V
+5V
14
04
6
(-16)
&04024
COUNTER/DIVIDER
os
(~32)
-5V
3.169
5
1
- _=.
I
I
-} GOULD
AIMII®Semiconductors
83541 Digital C Message
Weighted and 1 KHz Notch Filter
53541
Features
• All Digital Operation for compatibility with all digital
, telephone systems and for higher reliability.
• Serial Port for Direct connection.
• Parallel Port for Direct connection to host
microcontrollers.
• C Message Weighted Filter for line noise
measurement to Bell and IEEE specifications.
• High Pass filter for removal of DC offsets and/or
measurement.
• Notch filter for line noise measurements under 1 KHz
load conditions to Bell and IEEE specifications. Notch
filter has more than 50 dB of rejection.
• Single +5 volt power supply operation for reduced
system cost.
• Space saving 28-pin plastic DIP package.
General Description
The S3541 is a monolithic, integrated circuit based
upon Digital Signal Processing (DSP) techniques and
represents a human ear response to noise during telephone line noise measurements. The primary application for the S3541 is line noise measurement within
U.S. telephony system channels., Other applications include diagnostic functions within a PABX system, and
voice energy detect systems. The device contains three
filters: A C Message Weighted filter, a 1 KHz Notch filter, and a High Pass filter. These filters meet specifications defined by Bell Systems Technical Reference
Publication #41009, May 1975 and IEEE Std
743-1984.
Block Diagram
Pin Configuration
SIGNAL
PROCESSING
SECTION
SERIAL IN
SERIAL OUT
.. I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ALL BLOCKS EXCEPT I-lP INTERFACE ARE SOFTWARE FUNCTIONS.
ALL SWITCHES SHOWN ARE SOFTWARE SWITCHES.
3.170
NC
Ao
DRO
cs
Po
Ro
P1
WR
Do
SORO
CONTROL FROM f.lP
i
if
DATA FROM I-lP
Vee
DACK
DATA TO f.lP
01
SO
D2
SI
D3
SOEN
04
SIEN
D5
SCK
06
INT
D7
RST
GND
ClK
-} GOULD
AIMII® Semiconductors
Single Chip
Conference Trunk
Preliminary Data Sheet
83547
Features
• 6 telephones/persons maximum conference with
AGe
•
•
•
•
•
2 groups of 3 telephones/persons conferences
+3 dB gain pad function
PCM highway (1.544/2.04B Mbps) serial interface
Parallel microprocessor bus interface
500 Hz tone generator
It 8mall 2B pin plastic DIP package
• +5 V single power supply
level is automatically controlled by using the peak value
to avoid the over range error. 2 separate conferences of
3 persons each can also be realized concurrently with
this chip.
General Description
83547 has a serial interface for PCM highway to realize
the conference trunk without any CODEC or Op-Amp in
the digital exchange system. It has a 500 Hz tone generator that can be used, for example, as the signal for
speakers to indicate that an additional speaker is
joining the conference.
83547 is the single chip conference trunk for 6
telephones/persons. 83547 uses the N-1 addition
method to realize a natural conversation. The output
83547 is easily controlled by various microprocessors
because it has a bus interface which is compatible with
BOBO, BOB5, BOB6, ZBO, etc.
Figure 1.
53547 Conference Trunk
Figure 2.
Pin Configuration
R-DATA
T-DATA
PCMIN
2.048/1.544MHz
8.192MHz
POEN
PIEN
PORQ
SCK
PCM
1.544/2.048Mbps
PCMOUT
S3547
RST
\'iii
07-00
3.171
NC
PU
NC
NC
NC
DO
01
02
D3
04
05
D6
D7
GND
vee
GND
CS (GND)
AD
\'iii
PORQ
PCM OUT
PCM IN
POEN
PIEN
SCK
RST
m
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AIMII®Semiconductors
53547
Figure 3.
S3547 Block Diagram
CONVERSION
FROM ,....LAW
FORMAT TO 2'S
COMPLEMENT
,....LAW
PCM IN
,....LAW
PCM OUT
TIMING
SIGNALS
1.
Functional Description
The Block Diagram of S3547 is shown in Fig, 3. S3547
has the DSP architecture.
Compressed wlaw PCM data is expanded to the linear
2's complement data for internal arithmetic operation.
After the arithmetic operation, the output data for each
channel is converted to wlaw PCM data again.
The output data for each channel is the data that is
generated by subtracting its own channel data from the
sum of all channel data in a conference. This is called
the N-1 addition method.
As the simple addition operation of 6 channel data may
cause the over-range error, the input data from each
channel is attenuated to non-over range level. The output signal level is automatically controlled to provide
sufficient audio level to hear. The peak value of sum of
all channel data is held for about 100 ms, which provides a natural conversation. This peak value is used
for the output level control.
The automatic gain control is not executed in the 2
groups of 3 persons conference mode.
S3547 is easily controlled by 2 types of a-bit command.
These commands are defined as "command 1" and
"command 2" according to the MSB value. The MSB of
command 1 is high and that of command 2 is low.
The level of the 500 Hz tone is also selectable by the
command 1.
1.1
6 persons/phones conference mode
When D6 bit of the command 1 is high, 6 persons/
phones conference mode is set. 6 consecutive time
slots are assigned for this mode. It is possible to use 2
t06 channels arbitrarily. The channel assignment for a
conference is done by command 2.
1.2 2 groups of 3 persons/phones conference
mode
When D6 bit of the command 1 is low, 2 groups of 3
persons/phones conference mode is set. First 3 chan-
3.172
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AIMII®Semiconductors
S3547
Table 1.
Pin Description
Pin No.
1
2
3,4,5
Name
NC
PU
NC
6-13
00-07
Type
I
I
I
1/0
3 state
14
15
GNO
ClK
I
16
RST
I
17
GNO
I
18
SCK
I
19
PI EN
I
20
POEN
0
21
PCMIN
I
22
PCMOUT
0
23
PORO
0
24
WR
I
25
RD
I
26
CS
I
27
28
GNO
Vcc
I
Function
No Connection
Must be pulled up to Vcc
Must be open.
Port for 8 bit data of command1 and command2.
I·:
-
.
I
Connect to GNO
Single phase master clock 8MHzl8.192MHz
Reset and initialize the S3547 internal logic. Set the first
command waiting state.
Connect to GNO
PCM data inputloutput clock. A serial data bit is transferred
when this pin is high.
PCM input enable pin. This pin enables the shift clock to serial
input register.
PCM output enable pin. This pin enables the shift clock to
serial output register.
PCM data input. Serial data is latched at the rising edge of
SCK.
PCM data output. Serial data is clocked out at the falling edge
of SCK.
PCM output request. It generates an output signal for an
external device indicating that the serial data register has been
loaded and is ready for output. PORO is reset when the entire
8-bit word has been transferred.
Write control signal. Write the contents of data bus into the
data register.
Read control signal. It is possible to read out the previous
command. This pin should be pulled up to Vcc in normal case.
Chip select. This pin enables data transfer with data or status
port with RO or WR signal.
Connect to GNO
+5 V Power.
3.173
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AIMII®Semiconductors
53547
Table 2.1
Bit
Command 1 (07=0)
06
Status
0
1
05
0
1
04
0
1
03
0
1
02, 01
00
Table 2.2
Bit
06
11
10
01
00
0
1
Function
6 persons/phones conference .mode
2 groups of 3 persons/phones conference mode.
"
500 Hz tone disable
500 Hz tone out for 0.2 seconds
For 3 phones conference mode
500 Hz tone out for group 1
500 Hz tone out for group 2
,
Tone level control bit
Hold the previous data
500 Hz tone level is selectable by 02 and 01 data.
500 Hz tone level data when 03 is high.
Large
Medium'
Small
Oisable a 500 Hz tone
Command 1 enable
Program reset
Command 2 (07=1)
Status
0
1
05-00
Functions
Enable channel position select
Optional gain position select
The .allocation of channels.
05-Ch6, D4-Ch5, 03-Ch4
D2-Ch3, 01-Ch2, 0D-Ch1
By setting these bits high, channels for the conference
are selected, The output of the channel which is not se·
lected is "11111111". The selection of channels for
each group in 2 groups of 3 phones mode is the same
as 6 phones conference mode.
nels of a series of 6 channels are the Group 1, and the
. others are the Group 2. Selection of the channels for '
each group is done by command 2.
1.3 500 Hz tone
When 05 bit of the command 1 is high, 500 Hz single
tone signal is added to each channel for about 0.2
seconds. In the 3 persons/phones conference
mode, the selection of groups is done by 04 bit of
command 1.
1.5 Optional input gain
S3547 has the optional gain function for input data of
each channel to compensate the outside line loss.
When 06 bit of the command 2 is high, the selected
channels have +3 dB optional gain for incoming signal.
In the 6 phones conference mode, it is possible to set
the optional gain up to two channels.
02 and 01 command bits are used for tone level data
when 03 bit of command 1 is high,
1.4 Selection of channels for conference
1.6 Program reset
When 06 bit of command 2 is low, DO-OS of command
2 are correspond to channel assignment of channel 1-6.
When DO bit of command 1 is high, internal program is
reset. Once program reset is complete, S3547 ter·
3.174
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AIMII®Semiconductors
S3547
Figure 4.
I·:
Serial I/O Timing
-
SHIFT FOR
CODEC
SCK FOR
S3547
--,
11
11
n
11
11
H5-, n n n
U U U U U U ..
U
U
U
n L.Jn L.JnL.JI
y~
r-~----~~~---------
~________~I________~~~____~r-
PCMOUT_
~~~
CODEC~~~
minates the conference function and waits for the command 1 for the next conference.
2.
3.
Timing for command input
The first control command input timing is shown in Fig.
6. The first input command after the reset pulse or program reset is to set conference mode and to select 500
Hz tone level, using command 1. After this initial sequence, the command for 83547 can be controlled dynamically until 83547 is reset by software or hardware.
Timing for serial data
The serial input and output data of 83547 is the 8-bit
wlaw PCM data.
83547 treats a series of 6 PCM data. The timing for the
PCM highway is shown in Fig. 4. Example of the PCM
highway interface circuit is shown in Fig. 5.
3.175
.
I
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AMII®Semiconductors
53547
Figure 5.
Example of PCM.lnterface Circuit
PCM
1.544/2.048. MHz
+5V
+5V
+5V
ClK
SCK
STO
PCM OUT
1.54412.048 MHz
CLOCK
lD
1/274HC74
PCM IN
PR
ClK
EP ClK RCO
83547
ET
DO
DC
DB
DA
POEN
PiEN
PORn
112 74HC74
74HC161
cs
AD
Wii
0,
D.
0,
0,
03
O2
0,
Do
Figure 6. Timing For Command Input
I
l- 4<1>CY
MIN
--:-111....S MIN ~,I
I
I
I
RST------!
1
I
I
DATA----------~:~·------~------------~~~------FIRST COMMAND INPUT.
3.176
DATA BUS
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AIMII®Semiconductors
53547
Absolute Maximum Rating
Voltage (Vee) ..................................................................... -0.5 to +7.0 Volts 1
Voltage, Any Input (VI) ............................................................. -0.5 to +7.0 Volts 1
Voltage, Any Output (VO) ........................................................... -0.5 to +7.0 Volts 1
Operating Temperature (TOPT) ........................................................... O°C to + 70 0 e
Storage Temperature (TSTG) ......................................................... -65°e to + 1500 e
Note 1: With respect to GND
- ~:
I
.
I
D.C. Characteristics: (TA=Ooe to + 70°C, vec= +5V±5%)
Symbol
Vil
VIH
Vl
VH
VOL
VOH
ILil
ILiH
ILOl
ILOH
ICC
Parameter
Input low Voltage
Input High Voltage
ClK low Voltage
ClK High Voltage
Output low Voltage
Output High Voltage
Input load Current
Input load Current
Output Float leakage
Output Float leakage
Power Supply Current
(0 to 70°C)
Min.
-0.5
2.0
-0.5
Typ.
3.5
Max.
0.8
VCC+0.5
0.45
VCC+0.5
0.45
Unit
V
V
V
V
V
V
-10
10
-10
10
!LA
!LA
!LA
fLA
280
rnA
20'
10'
20'
pF
pF
pF
2.4
180
Condition
IOl=2.0rnA
IOH=400!LA
VIN=OV
VIN=VCC
VOUT=0.47V
VOUT=VCC
Capacitance
C
CIN
COUT
ClK, SCK Input Capacitance
Input Pin Capacitance
Output Pin Capacitance
'These values are not 100% tested in production.
3.177
fc = 1MHz
fe = 1MHz
fe=1MHz
-} GOULD
AIMII®Semiconductors
S3547
A.C. Characteristics: (TA=O°C to +70°C, VCC=+5V±5%)
Symbol
Parameter
CY
ClK Cycle Time
D
R
ClK Pulse Width
ClK Rise Time
F
tAR
tRA
tRR
ClK Fall Time
Address Setup Time for RD
tRD
tDF
tAW
tWA
tWW
tDW
tWD
tRV
tSCY
tSCK
tRSC
tFSC
tDRQ
tSOC
·tCSO
tDCK
tDZRQ
Min.
122
Max.
Unit
2000
ns
ns
10
10
ns
ns
ns
ns
60
0
Address Hold Time for RD
. RD Pulse Width
0
.' 250
Data Delay from RD
Read to Data Floating
Address Setup Time for WR
10
150
100
0
Address Hold Time for WR
WR Pulse Width
Data Setup Time for WR
. Data Hold Time for WR
0
250
480
SCK Pulse Width
SCK Rise Time
30
50
30
DC
ns
ns
20
20
ns
ns
ns
tDZSC
PCMOUT Delay from SCK with PORQ t
PCMOUT Delay from SCK
tDZE
tHZE
tHZSC
PCMOUT Delay from POEN
POEN to PCMOUT Floating
SCK to PCMOUT Floating
tHZRQ
tDC
tCD
PCMOUT Delay from SCK with PORQ~
PIEN, PCMIN Setup Time for SCK
PIEN, PCMIN Hold Time from SCK
tRST
RST Pulse Width
150
ns
ns
20
150
300
ns
ns
. ns
20
20
20
300
180
200
ns
ns
ns
20
70*
55*
300
300
ns
ns
PCMOUT Delay from SCK=lOW
30*
4*
VIH~VOH~2.0V
3.178
S~e
Note 1
See Note 1
See Note 1
ns
ns
ns
ns
ns
ns
230
SCK Fall Time
PORQ Delay
POEN Setup Time for SCK
PO EN Hold Time for SCK
'. Condition '
i
Cl=100pF
Cl=100pF
ns
ns
0
250
150
RD, WR, Recovery Time
SCK Cycle Time
• These values are guaranteed by design and not by 100% testing.
Note 1: Voltage at measuring point of timing 1.0V and 3.0V
Note 2: Voltage at measuring point of AC Timing: Vll~VOl~O.BV,
Input Waveform of AC Test (expected ClK, SCK)
Typ.
ns
ns
CY
... '
. See Note 2
.. ,'
. See Note 1
See Note 1
Cl=100pF
See Note 2
See Note 2
See Note 2
See Note 2
See Note 2
See Note 2
See Note 2
-} GOULD
AIMII®Semiconductors
53547
Timing Waveforms
I
I
CLOCK
CLK
READ
1'"t ,~
CS_
Rii
08 0_7
- - - -- - -----
_
-----:":1 -'" r------
WRITE
08 0_7
- - -
3.179
GOULD
~MII®Semiconductors
S3547
Timing Waveforms
SCK
PORQ
- t-- I
-~-----
PCMOUT
"1
=cc
10C~ L
PCMIN
DZE
tHzi~ ~tHZRO
Inzno
ilco
"1: For PCMOUT timing, the data at rising edge 01 SCK is valid and the other data is
invalid. In setup hold time of data for SCK, the most slrict specifications are the
following.
SETUP = tSCK - lOCK
HOLD = tHZRQ
"2: Vollage at measuring point of tRSC and tFSC for SCK timing
® 1.0V
G) 3.0V,
PORT OUTPUT
CLK~
~
RST - - - . /
"'---
3.180
Digital Signal
Processor·
-} GOULD
AIMII®Semiconductors
57720
1_:
1
Features
General Description .
o
o
o
The S7720 Digital Signal Processor (DSP) is an
advanced architecture microcomputer optimized for
signal processing algorithms. Its speed and flexibility
allow the DSP to efficiently implement signal processing functions in a wide range of environments and
applications.
o
o
o
o
o
o
o
o
o
Fast Instruction Execution - 250 ns
16-Bit Data Word
Multi-Operation Instructions for Optimizing
Program Execution
.
Large Memory Capacities
- Program ROM
512 x 23 Bits
- Coefficient ROM
510 x 13 Bits
128 x 16 Bits
- Data RAM
Fast (250 ns) 16 x 16-31 Bit Multiplier
Dual Accumulators
Four Level Subroutine Stack for Program
Efficiency
Multiple 1/0 Capabilities: Serial, Parallel, DMA
Compatible with Most Microprocessors,
Including: 8080, 8085, 8086, Z80™·
Power Supply + 5V
NMOS
Package - 28 Pin Dip
The DSP is the state of the art in signal processing
today, and for the future.
Performance Benchmarks
o
o
Second Order Digital Filter (BiQuad)
SINE/COS of Angles
Oil/A LAW to Linear Conversion
o FFT: 32 Point Complex
64 Point Complex
·Trademark of Zilog Corp.
Functional Block Diagram
Pin Configuration
NC
ORO
m-~::::5
INT
Vcc-
GNO _
~~
DB
Do-07
jfii
LI-
INTERRUPT
2.25 JlS
5.25 JlS
'0.50 JlS
0.7 ms
·1.6 ms
Wii
,--,---,--,--,-,'-,-,-,0
cs
Vee
DACK
Ao
ORO
CS
Po
Rii
P,
WR
Do
SORO
01
SO
02
SI
03
SOEN
04
SIEN
. D.
SCK
06
INT
07
RST
GND
ClK
AD
3.181
-
.
I
-)GOULD
AIMII®Semiconductors
S7720
Functional Description
cycie. In addition, each arithmetic instruction provides for a number of data movement operations to
further increase throughout. Two serial I/O ports are
provided for interfacing to codecs and other seriallyoriented devices while a parallel port provides both
data and status information to conventional JLP for
more sophisticated applications. Handshaking
signals, including DMA controls, allow the DSP to act
as a sophisticated programmable peripheral as well
as a stand alone microcomputer.
Fabricated in high speed NMOS, the S7720 DSP is a
complete 16-bit microcomputer on a single chip.
ROM space is provided for coefficient storage, while
the on-chip RAM may be used for temporary data,
coefficients and results. Computational power is provided by a 16-bit Arithmetic/Logic Unit (ALU) and a
separate 16 x 16-bit fully parallel multiplier. This
combination allows the implementation of a "sum of
products" operation in a single 250 nsec instruction
Absolute Maximum Ratings·
Voltage (Vcc Pin) .............................................................. - 0.5 to + 7.0 Volts 1
Voltage, Any Input (VI)' ......................................................... - 0.5 to + 7.0 Volts 1
Voltage, Any Output (Vo) ....................................................... - 0.5 to + 7.0 Volts 1
Operating Temperature (TOPT) ..................................................... ~ 40°C to + 85°C
Storage Temperature (TSTG) ...................................................... - 65°C to + 150°C
NOTE 1: With respect to GND.
"COMMENT: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The device is
not meant to be operated under conditions outside the limits described in the operational sections 'of this ·specification. 'Exposure to
ab~olute maximum rating conditions for extended periods may affect device reliability.
Capacitance
Symbol
Parameter
C'"
CIN
COUT
Min.
Typ.
Max.
Unit
Condition
ClK, SCK Input Capacitance
20'
pF
fc= 1MHz
Input Pin. Capacitance
10'
pF
fc=IMHz
Output Pin Capacitance
20'
pF
fc=IMHz
Max.
Unit
"These values are noll00% lested in production.
Electrical Specifications: (TA= 0° - + 70°C, Vcc= + 5V ± 5%)
D.C. Characteristics
Symbol
Parameter
Min.
VIL
VIH
Input low Voltage
-0.5
Input High Voltage
2.0
Vq,L
ClK low Voltage
-0.5
Vq,H
ClK High Voltage
3.5
VOL
Output low Voltage
VOH
Output High Voltage
ILiL
Input load Current
ILiH
Input load Current·
ILOL
ILOH
lee
Power Supply Current (0 to 70°C)
lee
Power Supply Current ( - 40 to 85°C)
Typ.
0.8
V
Vee +0.5
V
0.45
V
Condition
Vee +0.5
V
0.45
V
IOL =2.0mA
V
IOH-400JLA
2.4
-10
JLA
VIN=OV
10
,.A
VIN=V ee
Output Float leakage
-10
,.A
VouT=0.47V
Output Float leakage
10
JLA
VOUT= Vee
280
mA
330
mA
180
3.182
-) GOULD
AIMII®Semiconductors
57720
A.C. Characteristics: (T A= _10· - + 70·C, Vee= + 5V ± 5%)
•
Symbol
Parameter
CY
ClK Cycle Time
Min .
122
Typ.
Max.
Unit
2000
ns
0
ClK Pulse Width
60
R
ClK Rise Time
10
ns
See Note 1
F
ClK Fall Time
10
ns
See Note 1
tAR
Address Setup Time for RD
0
ns
tRA
Address Hold Time for RD
0
ns
ns
RD Pulse Width
Data Delay from RD
250
tOF
Read to Data Floating
tAW
Address Setup Time for WR
0
ns
tWA
Address Hold Time for WR
0
ns
tww
WR Pulse Width
250
ns
tow
Data Setup Time for WR
150
ns
two
Data Hold Time for WR
0
ns
tRV
RD, WR, Recovery Time
tAM
ORO Delay
10
150
ns
100
ns
ns
250
150
1-
DACK Delay Time
tSCY
SCK Cycle Time
480
tSCK
SCK . Pulse Width
230
tRSC
SCK Rise/Fall Time
tORO
SORa Delay
tsoc
SOEN Setup Time
50
tcso
SOEN Hold Time
30
tOCK
SO Delay from SCK=; lOW
tOZRO
SO Delay from SCK with SORa I
tozSC
SO Delay from SCK
tOZE
tHZE
Cl =100pF
Cl .= 100pF
See Note 2
See Note 2
ns
ns
30
20
ns
See Note 1
150
ns
Cl =100pF
ns
ns
150
ns
300
ns
See Note 2
20
300
ns
See Note 2
SO Delay from SOEN
20
180
ns
See Note 2
SOEN to SO Floating .
20
200
ns
See Note 2
tHZSC
SCK TO SO Floating
20
300
ns
See Note 2
tHZRO
SO Delay from SCK with SOROI
70-
300
ns
See Note 2
toc
SIEN, SI Setup Time
80
ns
See Note 2
tco
SIEN, SI Hold Time
160
ns
top
Po, P1 Delay
RST Pulse Width
20
CY
tRST
INT Pulse Width
tiNT
'These values are guaranteed by deSign and not by 100% testing.
NOTE 1: Voltage at measuring point of timing 1.0V and 3.0V
NOTE 2: Voltage at measuring pOint'of AC Timing: ~L = VOL =0.8V, ~H =VOH =2.0V·
3.183
4-
8Input Waveform of AC Test
(except ClK, SCK)
+ 150-
ns
CY
CY
2.4
-
.
I
ns
0
DC
1_:
1
ns
tRR
tRO
tOACK
Condition
See Note 1
,~=-o_ _-...:~
D.45--"t8:------:~
-) GOULD
AIMII®Semiconductors
S7720
"
Clock
0--r
"1
1/ - - -
-
1,DY
-<1>01
Figure 1, Clock
Read
AD. CS. DACK
iiii
J~
.
.
~t
.1
tRR
\.
,
lilt"
J
--
~ftl
DBo-7 - - - - - - - - - - - - - - - - - - Figure 2. Read Operation
tnF
f--------
Write
AD. CS. DACK
WR
J.
I.
'"
DBo_7
.1
tww
~~
I
~
tow
Figure 3, Write Operation
3.184
~I.
I
~1
GOULD
AIMII®Semiconductors
57720
I
57720
PRODUCT EXAMPLE
USING THE 57720
SENSOR
"'ROPHONE
THERMAL
1
.... : .............. .
PRESSURE
LIGHT
FRED.-
- _=.
I
AN AMALDG TO
ANALOG DIGITAL
PROCESSING SYSTEM
USING A SINGLE OSP
ANALOG
OUT
ANALOG
•
RECONSTRUCTION
RLTER
ANALOG
OUT
A SIliHALPROCESSING SYSTEM USING
CASCADEDDSPs '" SERIAL COMMUNICATION.
A SlG'NAl PROCESSING
SYSTEM USING DSPs
AS A COMPLEX COMPUTER
PERIPHERAL
3.185
Digital Signal
-) GOUL[]
Proc.essor
AIMII®Semiconductors
Advanced Product Description
S77C20
Features
General Description
o
o
o
The S77C20 Digital Signal Processor (DSP) is an
advanced architecture microcomputer optimized for
signal processing algorithms. Its speed and flexibility
allow the DSP to efficiently implement signal process·
ing functions in a wide range of environments and
appl ications.
o
o
o
o
o
o
o
o
o
o
Fast Instruction Execution - 250 ns
16·Bit Data Word
Multi·Operation Instructions for Optimizing
Program Execution
Large Memory Capacities
512 x 23 Bits
- Program ROM
510,x 13 Bits
- Coefficient ROM
128 x 16 Bits
- Data RAM
Fast (250 ns) 16 x 16·31 Bit Multiplier
Dual Accumulators
Four Level Subroutine Stack for Program
Efficiency
Multiple I/O Capabilities: Serial, Parallel, DMA
Compatible with Most Microprocessors,
Including: 8080, 8085, 8086, Z80™o .
Power Supply + 5V
CMOS
Package - 28 Pin Dip
Package - 28 Pin PLCC
The DSP is the state of the art in signal processing
today, and for the future.
Performance Benchmarks
o
o
o
o
Second Order Digital Filter (BiQuad)
SINE/COS of Angles
pJA LAW to Linear Conversion
FFT: 32 Point Complex
64 Point Complex
*Trademark of Zllog Corp.
Functional Block Diagram
Pin Configuration
NC
ORO
~k~
INT
----H] : ::
Vee ----.
GNO - - INTERRUPT
~10
w..
2.25pS
5.25pS
0.50pS
0.7 ms
1.6 ms
0,-0,
~ ~BB~
iiii
Wii
CS
0
L...I...I....I....L.:.J'.:.J
AD
3.186
Vee
oACK
Ao
ORO
CS
Po
Ro
P,
WR
Do
SoRO
0,
SO
02
SI
03
SoEN
04
SIEN
05
SCK
06
INT
07
RST
GNo
ClK
-} GOULD
AIMII®Semiconductors
S77C20
Functional Description
Fabricated in high speed CMOS, the S77C20 DSP is a
complete 16-bit microcomputer on a single chip.
ROM space is provided for coefficient storage, while
the on-chip RAM may be used for temporary data,
coefficients and results_ Computational power is provided by a 16-bit Arithmetic/Logic Unit (ALU) and a
separate 16 x 16-bit fully parallel multiplier. This
combination allows the implementation of a "sum of
products" operation in a single 250 nsec instruction
cycle. In addition, each arithmetic instruction provides for a number of data movement operations to
further increase throughout. Two serial 110 ports are
provided for interfacing to codecs and other seriallyoriented devices while a parallel port provides both
data and status information to conventional JLP for
more sophisticated applications. Handshaking
signals, including DMA controls, allow the DSP to act
as a sophisticated programmable peripheral as well
as a stand alone microcomputer.
Absolute Maximum Ratings·
Voltage (Vcc Pin) .............................................................. - 0.5 to + 7.0 Volts 1
Voltage, Any Input (VI)' ......................................................... - 0.5 to + 7.0 Volts 1
Voltage, Any Output (Vol ..................................................... ,. - 0.5 to + 7.0 Volts 1
Operating Temperature (TOPT) . . . . • • . . . . . • • . . . • . . . . . . • . . . . . . . . . . . . . • . . . . . . • . . • . . . . . -O°C to + 70 DC
Storage Temperature (TSTG) •.••..•..••....•..•.•.......•....•........•...•....... - 65°C to + 150 D C
NOTE 1: With respect to GND.
'COMMENT: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The device is
not meant to be operated under conditions outside the limits described in the operational sections of t~is specification. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Capacitance
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
fc=1MHz
C
ClK, SCK Input Capacitance
20'
pF
CIN
Input Pin Capacitance
10'
pF
fc=1MHz
COUT
Output Pin .Capacitance
20'
pF
fc=1MHz
Max.
Unit
0.8
V
Vee +0.5
V
-These values are not 100% tested in production.
Electrical Specifications: (TA = 0° - +70°C, Vcc= + 5V ± 5%)
D.C_ Characteristics
Symbol
Parameter
Min.
VIL
VIH
Input low Voltage
-0.5
V",L
ClK low Voltage
-0.5
V",H
ClK High Vollage
3.5
VOL
Output low Voltage
VOH
Output High Voltage
IUL
Input load Current
Input High Voltage
IUH
Input load Current
I LOL
Output Float leakage
ILOH
Output Float leakage
Icc
Power Supply Current (0 to 70°C)
Typ.
2.0
0.45
V
Vee +0.5
V
0.45
V
2.4
-10
3.187
IOL=2.0rnA
V
IOH-400JLA
JLA
VIN=OV
10
jLA
VIN=V ee
-10
JLA
VOUT=0:47V
JLA
VouT=Vee
10
18
Condition
24
rnA
I
1
I
- _=-
I
-) GOULD
AIMII®Semiconductors
S77C20
A.C. Characteristics: (fA= -O·C- + 70·C, Vee= +5V±5%)
Symbol
Parameter
Min.
CY
CLK Cycle Time
122
D
CLK Pulse Width
60
Typ.
Max.
Unit
Condition
2000
ns
See Note.1
ns
R
CLK Rise Time
10
ns
See Note 1
F
CLK Fall Time
10
ns
See Note 1
tAR
Address Setup Time for RD
0
ns
tRA
Address Hold Time for RD
0
ns
tRR
RD Pulse Width
tRo
Data Delay from RD
toF
Read to Data Floating
ns
250
10
150
ns
Cl=100pF
100
ns
Cl =100pF
tAW
Address Setup Time for WR
0
ns
tWA
Address Hold Time for WR
0
ns
tww
WR Pulse Width
250
ns
tow
Data Setup Time for WR
150
ns
two
Data Hold Time for WR
0
ns
tRV
RD, WR, Recovery Time
tAM
DRO Delay
toACK
DACK Delay Time
ns
250
150
1*
tsCY
SCK Cycle Time
480
tSCK
SCK Pulse Width
230
tRSC
SCK Rise/Fall Time
tORa
SORO Delay
30
tsoc
SO EN Setup Time
50
tcso
SOEN Hold Time
30
toCK
SO Delay from SCK = LOW
tozRa
SO Delay from SCK withSOROf
tozsc
SO Delay from SCK
tozE
SO Delay from SOEN
tHZE
DC
See Note 2
ns
.
D
See Note 2
ns
ns
20
ns
. See Note 1
150
ns
Cl = 100pF
ns
ns
150
ns
20
300
ns
See Note 2
20
300
ns
See Note 2
20
180
ns
See Note 2
SOEN to SO Floating
20
200
ns
See Note 2
tHZSC
SCK TO SO Floating
20
300
ns
See Note 2
tHzRa
SO Delay from SCK with SOROI
70*
300
ns
See Note 2
toc
SIEN, Sl Setup Time
55*
ns
See Note 2
tco
SIEN, Sl Hold Time
30*
top
tRST
Po, P1 Delay
RST Pulse Width
ns
CY +150*
4*
INT Pulse Width
tiNT
'These values are guaranteed .by design and not by 100% testing.
NOTE 1: Voltage at measuring point of timing 1.0V and 3.0V
NOTE 2: Voltage at measuring point of AC Timing: V,L = VOL = 0.8V, ~H = VOH = 2.0V
ns
CY
8*
CY
20
2.0
Input Waveform of AC Test
(except ClK, SCK)
2"=X~~K=
3.188
0.45
o:a:-----:•.•
-) GOULD
AIMII®Semiconductors
S77C20
Clock
-
3.DY
-
1.DY
ClK
Figure 1. Clock
Read
AD. CS. DACK
iiii----
~
'~1c----~ f--------
OBO_7 - - - - - - - - - - - - - - - - -
d Operation
Figure 2. Rea
Write
Ao. CS. OACK
~t-AW-tww~tw_.~_
WR - - - -
:
---OBO_7 - - - - - - -
~Ial
~
toW~ ,1'_~3<---
__
Write Operation
Figure 3.
3.189
_ _'_
I
I
-} GOULD
AIMII®semiconductors
S77C20
Arithmetic Capabilities
Stack
General
The SPI contains a 4-level program stack for efficient
program usage and interrupt handling.
One of the unique features of the SPI's architecture is
its arithmetic facilities. With a separate multiplier,
ALU, and multiple internal data paths, the SPI is
capable of carrying out a multiply, an add, or other
arithmetic operation, and a data move between internal
registers in a single instruction cycle.
ALU
The ALU is a 16-bit 2's complement unit capable of
executing 16 distinct operations on virtually any of the
SPI's internal registers, thus giving the SPI both speed
and versatility for efficient data management.
Accumulators (ACCA/ACCB)
Associated with the ALU are a pair of 16-bit accumulators, each with its own set of flags, which are
updated at the end of each arithmetic instruction (except NOP). In addition to Zero Result, Sign Carry, and
Overflow Flags, the SPI incorporates auxiliary
Overflow and Sign Flags (SA1, SB1, OVA1, OVB1).
These flags enable the detection of an overflow condition and maintain the correct sign after as many as
three successive additions or subtractions.
FLAG B
SAl
SBl
SAO
SBO
CA
CB
ZA
ZB
Input/Output
General
The SPI has three communication ports; two serial and
one 8-bit parallel,each with its own control lines for interface handshaking. The parallel port also includes
DMA control lines (DRO and DACK) for high speed
data transfer and reduced processor overhead. A.
general purpose 2-line output port rounds out a full
complement of interface capability.
TO EXTERNAL
DATA BUS
OVAl
OVBl
DVAO
DVBO
I
Figure 1.
..RAllEl va
INTERFACE
Table 2. ACC· AlB Flag Registers
FLAG A
Interrupt
A single level interrupt is supported by the SPI. Upon
sensing a high level on the INT terminal, a subroutine
call to location 100H is executed. The EI bit of the
status register is automatically reset to 0, thus disabling the interrupt facilities until reenabled under program control.
OMA {
INTERFACE
INTERRUPT
RESET
CLOCK
---
011- 07
SERiAL 110
INTERFACE
m:K
Oft,
~T
RST
eLK
Po
P,
} GEHERAl
PURPOSE
OUTPUT PORT
Sign Register (SGN)
Serial 1/0
When OVA1 (or OVB1) is set, the SA1 (or SB1) bit will
hold the corrected sign of the overflow. The SGN
Register will use SAl (SB1) to automatically generate
saturation constants 7FFFH( +) or 8000H( - ) to permit
efficient limiting of a calculated value.
The two shift registers (SI, SO) are software·
cOflfigurable to single or double byte transfers. The
shift registers are externally clocked (SCK) to provide a
simple interface between the SPI and serial.
peripherals such as AID and D/A converters, codecs, or
other SPls.
Multiplier
Thirty-one bit results are developed by a 16 x 16-bit 2's
complement multiplier in 250 ns. The result is
automatically latched to two 16-bit registers M&N (sign
and 15 higher bits in M, 15 lower bits in N; LSB in N is
zero) at the end of each instruction cycle. A new product is available for use after every instruction cycle,
providing significant advantages in maximizing processing speed for real time signal processing.
Parallel 1/0
The 8-bit parallel 1/0 port may be used for transferring
data or reading the SPI's status. Data transfer is handled
through a 16-bit Data Register (DR) that is software·
configurable for double or single byte data transfers.
The port is ideally suited for operating with 8080, 8085,
and 8086 processor buses and may be used with other
processors and computer systems.
3.190
-} GOULD
AIMII®Semiconductors
S77C20
Figure 2. Serial 1/0 Timing
sex
o.~
o,~
>----------
SORO!
'-------
,'---------..,Il-I---------L-------HIGH'
OUTPUT
DATA
Q)
i --- -- -(HEXTDATASEn- ------ -j
SOACK
.J
SO LOAD
~
r---...,
!
!
(%J
INPUT DATA
180R5
,'-----------------~!
W
SI LOAD
SlACK
140R6
---------------------------------~--~II~------------------------------------~~
NOTES:cD DATA CLOCKEQ OUT ON FALLING EDGE OF SCK
CZl DATA CLOCKED IN ON RISING EDGE OF seK
C'l BROKEN LINE DENOTES CONSECUTIVE SENDING OF NEXT DATA
Table 3. Parallel R/W Operation
Table 4. Status Register Flags
CS Ao WR RD OPERATION
FLAG
OPERATION
X X X Internal operation is not affected: 00-07
X X 1 1 are kept under a high impedance
ROM (Request for
Master)
A read or write from DR to IDB sets
ROM = 1. An external read (write) resets
ROM=O.
USFI and USFO
(User Flags 1
and 0
General purpose flags which may be read
by an external processor for user defined
signaling
DRS (DR Status)
For 16-bit DR transfers (ORC = 0). DRS = 1
after first 8 bits have been transferred.
ORS=Oafter all 16 bits transferred.
OMA
(OMA Enable)
OMA= 0 (Non-OMA transfer mode)
OMA= 1 (OMA transfer mode).
ORC (DR Control)
ORC=O (16-bit mode)
ORC = 1 (a-bit mode).
SOC (SO Control)
SOC=O (16-bit mode)
SOC = 1 (a-bit mode).
SIC (SI Control)
SIC=O (16-bit mode)
SIC = 1 (a-bit mode).
EI
(Enable Interupt)
EI = 0 (interrupts disabled)
EI = 1 (interrupts enabled).
PI, PO
(Ports 0 and 1)
PO and PI directly control the state of output pins PO and PI.
1
0
0
0
1
Data of 00-07 are latched to DR register'
0
0
1
Contents of DR register are output to 00-07'
0
1
0
0
1
0
1
1
0
8 higher bits of SR register are output to
00-07
0
X 0
0
Inhibited
Inhibited
NOTE 1: Eight MSBs or 8 LSBs of data register (DR) are used depending on DR status
bit (DRS). The condition of ilACi(=0 is equivalent to Ao=CS=O.
Figure 3. Status Register
MSB
S
4
EIOO:O',O:O
The status register is a 16-bit register in which the 8
most significant bits may be read by the system's MPU
for the latest 1/0 and processing status.
3.191
-) GOULD
AIMII®Semiconductors .
S77C20
Instructions
Table 5. P-Select Field
The SPI has 3 types of instructions, all of which are
one 23-blt word and execute in 250 ns.
P·SELECT FIELD
MNEMONIC
D'9
a
RAM
IDB
a
a
1
Internal Data Bus'
M
1
a
M Register
N
1
1
N Register
RAM
Figure 4. ArithmeticlMove-Return (OP = OOIRT = 01)
OPIRT
INPUT
020
NOTE 1· Any value on the on,chip data bus. Value may be selected from any. of the
registers listed in Table 11 source register selections.
OP/RT Instruction Field Specification
There are two instructions of this type, both of which
are capable of executing all ALU functions listed in
Table 6. The ALU functions operate on the value
specified by the P·select field. (See Table 5.)
Besides the arithmetic functions these instructions
can also modify (1) the RAM Data Pointer DP, (2) the
Data ROM Pointer RP, and (3) move data along the on·
chip data bus from a source register to a destination
register (the possible source and destination registers
are listed in Tables 11 and 12 respectively). The dif·
ference in the two instructions of this type is that RT
executes a subroutine or interrupt return at the end of
the instruction cycle while the OP does not.
Table 6. ALU Field
FLAGS AFFECTED"
ALU FIELD
MNEMONIC
. ALU FUNCTION
FLAG A
SA1
SAO
CA
ZA
OVA1
OVAO
FLAG B
SB1
SBO
CB
ZB
OVB1
OVBO
-
-
-
-
-
a
a
a
D'8
D17
D'6
D15
a
a
a
a
a
a
a
No Operation
-
1
OR
X
1
1
a
AND
x
XOR
a
a
a
a
1
1
Exclusive OR
SUB
0
1
a
ADD
1
SBB
a
a
a
a
1
1
ADC
0
1
DEC
1
INC
1
CMP
1
a
a
a
NOP
OR
AND
1
1
a
a
X
1
0
1
a
a
a
Subtract
1
1
1
1
1
1
1
ADD
1
1
1
1
1
1
a
Subtract with
Borrow
1
1
1
1
1
1
1
1
Add with Carry
1
1
1
1
1
1
a
a
Decrement Acc
1
1
1
1
1
.1
0
1
Increment Acc
1
1
1
1
1
1
1
0
Complement Acc
(1 's Complement)
X
1
a
1
a
a
1
SHR1
1
0
1
1
1-bit R·Shift
X
1
1
1
0
0
SHL1
1
1
a
Hit L·Shift·
X
1
1
1
a
a
SHL2
1
1
a
a
1
2-bit L·Shift
X
1
a
1
0
SHL4
1
1
1
a
4-bit L·Shift
X
1
0
1
a
XCHG
1
1
1
1
S·bit Exchange
X
1
a
1
0
0
0
0
NOTES:
t May be affected, depending on the results
,.,. Previous status can be held
3.192
o Reset
X Indefinite
-) GOULD
AIMII®Semiconductors
S77C20
Table 7. ASL Field
Table 11. DPH-M Field
ASL FIELD
MNEMONIC
014
MNEMONIC
011
010
09
MO'
0
0
0
b
1
1
0
M3
0
0
0
1
1
LOW OP MODIFY
M4
1
0
0
ACC SELECTION
ACCA
0
ACCA
M1
ACCB
1
ACCB
M2
Table 8. DPL Field
MNEMONIC
013
012
(OP3·0PO)
M5
1
0
1
DPNOP
0
No Operation
M6
1
1
0
DPINC
0
0
1
1
1
1
1
0
DPCLR·
1
1
Increment DPL
Decrement DP L
Clear DPL
M7
DPDEC
Table 12. Destination Field Specifications
OST RELO
RPDCR
03
02
01
@NON
0
0
0
0
0
0
0
0
0
0
1
1 TR Temporary Register
0
0
1
0 DP Data Pointer
1
0
0
1
1
0 DR Data Register
1
1
1 SR Status Register
0
0
0 SO Serial Out LSB'
1
0 K (Mult)
08
OPERATION
RPNOP
0
No Operation
@A
RPDEC
1
Decrement RP
@B
@TR
Table 10. SRC Field
@DP
SCR RELO
NON
A
B
TR
DP
RP
RO
SGN
0
0
0
0
0
0
0
0
06
0
0
0
05
04
@RP
SPECIREO REGISTER
Do SPECIREO REGISTER
0 NO Register
MNEMONIC
MNEMONIC
07
Exclusive OR or OPH (OP S-OP4)
with the Mask defined by the
three bits (0 11 -0 9) of the
OPwM field
"No change
Table 9. RPDCR Field
MNEMONIC
HIGH OP MODIFY
0
0
0 NO Register
@DR
1 AccA (Accumulator A)
@SR
0
0
1
0 AccB (Accumulator B)
@SOL
1
0
0
1
1 TR Temporary Register
@SOM
1
1
0
0 DP Data Pointer
@K
1
1
0
1 RP ROM Pointer
@KLR
1
0
0
0
1
1
1
1 Acc A (Accumulator A)
0 Acc B (Accumulator B)
1 RP ROM Pointer
1 SO Serial Out MSB'
1
1 IDB-K ROM-L'
0 Hi RAM-K IDB-L4
1
1
0 RO ROM Output Data
@KLM
1
1
1 SGN Sign Register
@L
1
1
0
0
@NON
1
1
1
0 NO Register
@MEM •
1
1
1
1 RAM
DR
1
0
0
a
DRNF
1
0
1 DR Data No Flag'
SR
1
0
0
1
0 SR Status
SIM
1
0
1
1 SI Serial in MSB'
SIL
1
1
1
1
0
0
0 SI Serial in LSB'
K
L
1
1
1
0 L Register
MEM
1
1
1
1 RAM
DR Data Register
NOTE 1:
NOTE 2:
NOTE 3:
NOTE 4:
1 K Register
NOTE 1: DR to lOB ROM not set. IN OMA ORO not set.
NOTE 2: First bit in goes to MSB, last bit to LSB.
NOTE 3: First bit in goes to LSB, last bit to MSB (bit reversed).
3.193
1 L (Mult)
LSB is first bit out.
MSB is first bit out.
Internal data bus to K and ROM to L register.
Contents of RAM address specified by OPs= 1 (i.e., t, OPs. OP4 , OPo) is
placed In K register. lOB is placed in l.
-} GOULD
AIMII®Semiconductors
S77C20
Jump/Call/Branch
Table 14. BRCH/eND Fields
CNO FELO
Figure 5. JP Instruction Field Specification
MNEMONK:
CONDITION'
017
016
015
014
013
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CA=O
1
CA=l
1
0
CB=O
1
1
CB=1
1
0
0
0
ZA=O
1I
1;
ZA=1
1
.1
0
ZB=O
1
1
1
ZB=l
JNOVAO
0
0
0
0
0
0
0
0
0
1
1
0
0
OVAO=O
0
1
jNOVBO
1
1
0
OVAO;=, 1
OVBO=O .
1
1
OVBO=l
JNOVA1
0
0
0
0
0
0
0
0
JOVAO
1
0
0
OVAl =0
JOVAl
0
1
1
0
1
OVAl == 1
JNOVBl
0
1
1
1
0
OVBl =0
For the conditional jump instruction,the condition
field specifies the jump condition. Table 14 lists all the
instruction mnemonics of the Jump/Call/Branch
codes.
JOVB1
0
1
1
1
1
OVBl =1
JNSAO
1
0
0
0
0
SAO=O
JSAO
1
0
0
0
1
SAO=l
JNSBO ,
1
0
0
SBO=O
JSBO
1
0
0
0
1
Load Data (LOI) .
1
1
SBO=l
Figure 6. LD Instruction Field Specification
JNSAl
1
0
1
0
SAl =0
JSAl
1
0
1
0
.0
JNCA
JCA
JNCB
Three types of program count~r modificati:ons are ac·
commodated by the processor and are listed in Table
13. All the instructions, if unconditional or if the
specified condition is true, take their next program ex·
ecution address from the Next. Address field (NA);
otherwise PC = PC + 1.
Table 13 BRCH Field
BRCH FELO
MNEMONK:
FUNCTION.
020
019
018
JMP
1
0
Unconditional Jump
CALL
1
0
0
1
.Subroutine Call
JNCA
0
1
O.
Conditional Jump
JCB
JNZA
JZA
JNZB
JZB
JOVBO
The Load Data instruction will take the 16·bit value
contained in the Immediate Data field (10) and place it
in the location specified by the Destination field (DSn
(see Table 12).
1
1:
1
SAl =1
SBl =0
JNSBl
1
0
1
1
o.
JSBl
1.
0
1
1
1
SB1 =1
JDPLO
1
1
0
0
0
DPL =0
JDPLF
1
1
0
0
1
DPL =F(HEX)
JNSIAK
1
.1
0
1
0
SIACK=O
JSIAK
1
1
0
1
1
SIACK= l'
JNSOAK
1
1
1
0
0
. SOACK=O
1
.1
1
1
0
1
SOACK= 1
1
1
1
0
ROM=O
1
1
1
1
1
ROM=1
JSOAK
JNROM
JROM
NOTE 1: BRCH or CND values not in this table are prohibited.
3.194
-} GOULD
AIMII®Semiconductors
S77C20
Figure 7. Instruction Timing (Four Phase-Internal Clock)
., .,
., .,
.3
••
., .,
.3
¢.
(N-1)
IHSTRUC110N
:>
(N+1)
1_:
1
..
-
.
I
I
DESTlNA110N
REGISTER RAM
} WRITE
INTERNAL DATA BUS (lOB)
ALU DPERA110N
-- ¢------t
------
..
ACC LATCH
MULTI'LICAllDN OPERAllDN
-(N-1)
MULT INPUT SET
MULT OUTPUT SET
I >
<:
SOURCE REGISTER } READ
RAM DR DATA ROM
-
-c----
..
-
MULTI'LICATlON
INPUT (N)
(N-1)
..
__
.... -----
MULTlPLICAllDN
RESULT (N)
--
... INSTRUCllDN CYCLE
250 ns AT 8 MHz
CLOCK CYCLE
62.5 ns AT 8 MHz
Instruction Timing
To control the execution of instructions, the external
a-MHz clock is divided into a four-phase, nonoverlapping clock_ Execution begins at the rising edge of
<1>3 and ends at the falling edge of <1>2_ The ALU commences operation at the rise of <1>1, and completes all
operations at the fall of cf>3Once an instruction-ROM address is available at the
rise of <1>3, the instruction is latched, and the source
3.195
register and RAM address are determined so that data
may be put on the internal bus by the fall of <1>4. The
ALU input is latched at the rise of <1>1, and the output is
available for accumulator latch at the rise of cf>3. The
cycle then repeats.
The multiplier takes its input at the rise of <1>1, and its
results are available in 250 ns, at the rise of the next <1>1.
GOULD
AIMII®Semiconductors
S77C20
57720
----
••
PRODUCT EXAMPlE
USING T'HE smm
..
"""'"
: : .............. :
lII1IT
FREQ.-
AJt AllAlOR TO
AltAl08 ...,.AL
PIIOCESIIMD SYITEII
USlt8AlIIIlfDSP
ANALOG
•
RECONlT1IucnIH
Fl.'"
lllAlOll
OUT
A SllNAL I'IIOCEIIMI SYSTEM UIII8
CASCADED lISPs • SEIIAL COMIllUlCATDI.
A SIGNAL PROCESSItG
SYST£M USIC 0Sh
AS " COMPlEX COMPUTER
PERFHERAl
Technical manual also available describing the use of the S77C20 Signal Processing Interface chip including functional description, instructions,
and several system examples. Please contact factory.
3.196
16-Bit Cascadable
CMOS ALU
-) GOULD
~MII®Semiconductors
Preliminary Data Sheet
5614381
Features
General Description
•
•
•
•
•
The S614381 is a flexible 16-bit hi-speed Arithmetic
Logic Unit Slice. It combines four 74S381 type 4-bit
ALU's with a 748182 carry lookahead generator, along
with input and output registers for pipeline operation. It
also contains a multiplexed input operand to the ALU
for added ALU functions. It retains full functional compatibility to the 74S381 type devices in a single 68-pin
J-Lead PLCC package.
Hi-Speed HCMOS 16-Bit Cascadable ALU.
Extension Architecture of 74S381.
InputlOutput Registers with Transparent Mode.
Cascadable, With or Without Carry Lookahead.
Force A or B = 0 Allows two's complement, also
Pass A, Pass B.
• Internal Feedback Path for Accumulator Operation.
• Status & Carry Outputs Available.
• CMOS Technology with 5v and TTL 1/0 Operation.
Block Diagram
Pin Configuration
CLOCK
B
,9r-
r -____
r--
f
16_______CJ
rnA
"'P--
L _ _R,
_ _ -':-------t--<::::J FT,
16
3.197
-}OOUlD
AIMII®Semiconductors
5614381
Pin Definitions
AO- 15
BO- 15
FO- 15
Co
C16
P
G
OVF
ZERO
ENA
ENB
FTAB
ENF
FTF
OSB
OSA
SO-2
OE
ClK
Vee, GND
ALU Status
A Input
B Input
Result Output
Carry Input
Carry Output
Carry Propagate Output
Carry Generate Output
AlU Overflow Flag
AlU Result Zero Flag
A Register Enable
B Register Enable
. A, B, Register Feedthrough Control
F Register Enable
F Register Feedthrough Control
B Operand Select
A Operand Select
Instruction Select
Output Enable
Clock
Power Supply
Two status bits are provided from the ALU. They are
overflow and zero. Three cascading functions are also
provided which are Carry, Propogate, and Generate.
These outputs are defined for the three arithmetic functions only. The Generate, Propogate, C16, and OVF
flags for the A + S operation are defined in Figure 2.
The status flags produced for NOT(A) + S and A +
NOT(S) can be found by complementing Aj and Sj in
Figure 2 respectively. The ALU sets the Zero output
when all sixteen output bits are zero.
Figure 1.
Architecture and Operation
The S614381 operates on 16 bit operands denoted A
and S, and produces a 16 bit result F. The AlU provides three arithmetic, three logical and two initialization·
functions, selectable from three select lines. Full AlU
status is provided, allowing the S614381 to be
cascaded for longer words. Input/output registers are
provided for pipeline operation with a bypass feature
under user control. An internal multiplexer allows multiple source operand selection into the ALU. This allows
extended ALU functions; such as PASS A, PASS S,
two's complementation and a feedback path of the output of the ALU back to its input for accumulator operation. Furthermore, the mux can force A or S input to
zero, allowing unary functions to be performed on either
operand.
ALU Function Definition
S2
S1
So
Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CLEAR (F = 00 . . . . 0)
NOT(A) + B (B MINUS A)
A + NOT(B) (A MINUS B)
(A PLUS B)
A+B
A XOR B
A OR B
A AND B
PRESET (F = 11 .... 1)
Figure 2.
ALU Status Flags
BIT CARRY GENERATE=gj=AjBj.
FOR i=O,1, ... ,15
BITCARRYPROPAGATE=pj=Aj+Bj, FORi=O,1, ... ,15
Po=Po
Pj=Pj(Pj-1)
FOR i=1,2, ... ,15
and
Go=go
Gj=gj+Pj(Gj_1)
Cj=Gj_1+Pj-1(Cj-1)
ALU Operation
The ALU is controlled by three select lines S2-S0' The
ALU functions and associated control signals are given
in Figure 1.
then
G=NOT(G 15)
P=NOT(P 15)
C16=G15+P15C15
OVF=C 15 XOR C16
The functions S minus A, and A minus S, (two's complement subtraction) can be achieved by setting Co = 1
of the least significant S614381 slice and selecting the
function codes 001 and 010 respectively.
3.198
FOR i=1,2, ... ,15
FOR i=1,2, ... ,15
-} GOULD
AIMII®Semiconductors
5614381
Operand Registers
Operand Selection
There are two 16-bit wide input registers for operands A
and B. These registers have a common clock triggered
on the rising edge, and separate register enable control
signals ENA and EN B. This architecture allows the
8614381 to accept arguments from a single 16-bit data
bus. In the case where it is not desired to have registered inputs for A and B, a control line FTAB allows the
registers to become transparent.
There are two operand select lines OSA and OSB that
control the 4 to 1 multiplexers immediately preceding
the ALU inputs. These multiplexers allow several options as to ALU source inputs. Figure 3 shows the inputs to the ALU as a function of the operand select
inputs. Either A or B operand may be forced to zero.
Figure 3.
When FTAB is asserted, the operand registers A,B are
bypassed; however, they continue to function normally
via the ENA and ENB controls. The contents of the input ..
registers will again be available to the ALU by releasing ,
the control line FTAB .
OSo
o
o
1
1
Output Register'
The output of the ALU, drives the input of a 16-bit register. This register is clocked by the same rising edge
clock as the input registers. By disabling the output register, intermediate results can be held while loading new
, input operands. The output buffer of the output register
is three-state controlled by OE input to allow the
8614381 to be used in a single bi-directional bus system. The output register can also be made transparent
by asserting the FTF control signal. As with the input
registers, when FTF is asserted, the output register is
bypassed, but the register continues to function normally viaJhe ENF control. The contents of the output
register will again be made available on the output pins
if FTF is released. With both control signals FTAB and
. FT F asserted (High), the S614381 is functionally identical to four cascaded 74S381 type devices.
Operand Selection Control
o
1
o
OPERAND B
F
1
o
OPERAND A
A
A
B
B
A
o
The S614381 can be configured as a chain calculation
by having both select lines released (low). The registered ALU output is passed back to the B input of the
ALU. In this way, accumulation operations can be performed by providing. new operands via the A input port.
The accumulator can be pre-loaded from the A input by
setting OSA true. By forcing the function select lines to
the clear state 000, the accumulator may be cleared.
Note that this feedback operation is not affected by the
state of the FTF control. That is, the F outputs of the
S614381 may be driven directly by the ALU (FT F =
high). The output register continues to function, however, and p'rovides the ALU B operand source.
Absolute Maximum Ratings
DC Supply Voltage (Voo-Vss) .................................................................... + 7V
Operating Temperature .................................................................... O°C to' 70°C
Storage Temperature ...................................................... '........... -55°C to + 150°C
Digital Input ............................................................. Vss - 0.3V "" V 1N "" Voo +.3V
DC Electrical Operating Characteristics: TA = O°C to +70°C; Voo = +5V (±10%); Vss = OV unless otherwise
specified.
Symbol
V1L
V1H
VOL
VOH
Parameter
Test Conditions
Low Level Input Voltage
High Level Input Voltage
Low Level Output Voltage
High Level Output Voltage
Min
Vss
IOL =4mA
IOH=·BmA
3.199
2.0
0
2.4
Typ
Max
Unit
O.B
Voo
V
V
V
V
0.4
Voo
1
- _=.
-} GOULD
AIMII®Semiconductors
S614381
AC Electrical Characteristics: TA
= 70 oe; VDD = +4.75V; Vss = OV
Input
FTAB = 0, FTF = 0
Clock
Co
SO-S2, asA, ass
FTAB = 0, FTF = 1
Clock
Co
SO-S2, asA, ass
FTAB = 1, FTF =0
AO- 15 , 80- 15
Clock
Co
. SO-S2, as A, ass
FTAB = 1, FTF = 1
Ao-15 , 80- 15
Clock
Co
SO-S2, asA, ass
FO- 15
P,G
25
43
-
-
FO- 15
60
45
44
To Output
OVF, ZERO
42
P,G
OVF, ZERO
45
48
38
49
C16
49
50
50
38
. FO-15
P,G.
OVF, ZERO
-
35
50
-
-
25
-
C16
43
50
42
39
38
49
. C16
-
38
-
47
50
38
FO- 15
P,G
OVF, ZERO
57
35
50
37
-
-
50
38
38
49 .
ns
ns
15
15
50
ns
ns
ns
15
10
ns
ns
-
-
-
-
45
44
47
38
47
Units
ns
ns
ns
Units
ns
ns
ns
Units
ns
ns
ns
ns
Units
ns
C16
NOTE:
.
1. Values are of average times based on the given: test truth table (inputs/outputs)
2. Actual values depend on the specific input patterns of Ao-Ai" Bo-B15, Co, 50 _ 2 ,
3. All outputs are loaded with 50pf, during AC testing.
Clock Cycle Time and Pulse Width
High. Pulse
Low Pulse
Minimum Cycle Time
Setup and Hold Time With Respect to
Clock Rising Edge
Setup
Hold
FTAB = 0 FTAB = 1 FTAB = 0/1 Units
.2
6
ns
Ao-A15, 80-815
I 31
EN A, ENB, ENF,
5
5
0
ns
Input
Three State Enable/Disable Times
I
3.200
-} GOULD
AIMII®Semiconductors
8614381
I
Inpuls
Function
Clear
B Minus A
80
0
1
81
0
0
82
0
0
Cn
X
0
0
a
a
1
1
1
1
0
A Minus B
0
1
0
a
0
a
1
1
1
1
0
0
A Plus B
1
1_:'
I
Test Truth Table (Inputs/Outputs)
1
0
A(j)B
0
0
1
A+ B
1
0
1
AB
0
1
1
Preset
1
1
1
a
0
1
1
1
1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
I
Outputs
An
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
a
1
1
Bn
X
0
1
0
1
a
1
a
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
a
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1 = HIGH Voltage Level
LOW Voltage Level
o=
3.201
Fo
F1
F2
F3
G
P
OVF
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
1
1.
0
0
0
1
0
1
1
0
0
1
1
1
0
0
0
1
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
a
0
1
1
1
1
1
a
1
0
1
0
0
1
a
1
1
0
0
1
0
0
1
1
1
0
0
a
1
0
1
1
0
0
1
1
1
0
0
0
1
1
1
1
1
a
0
1
0
1
1
a
0
1
0
0
1
1
1
a
0
0
1
0
1
1
0
0
1
1
1
0
0
0
1
1
1
1
1
a
0
1
a
0
0
1
0
0
0
1
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
a
a
0/1
1
0
0
0
0/1
1
0
1
0/1
0
0
0
0/1
C16
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
0/1
1
0
0
0
0/1
1
0
1
0/1
0
0
0
0/1
-
.
Dual Port Memory
Controller (D.P.M.C.)
-} GOULD
AIMII®Semiconductors
Preliminary Data Sheet
S61C35
Features
• INT output function for both Ports
(open drain for or-tied operation)
• Both Ports operate independently
• Master/slave mode for controller ganging
• 5V supply, 48 pin DIP
• Full TTL compatibility
• Full asynchronous arbitration between two Ports for
access to user selected memory (SRAM, DRAM,
EPROM, etc.)
• Easy 8/16 (32) bit microprocessor interface
• Allows building Dual Port Memory of any depth,
width, from standard (SRAM, DRAM, EPROM)
• Fast control signal passing of winning port to user
selected RAM
• Upper/lower Data Strobes for 8/16 (32) bit
applications
• BUSY output function for loosing Port
(open drain for or-tied operation)
• Four separately selected registers per Port for:
-message passing between Ports
-locking capability for either Port
-interrupt mechanism for above features
Applications
•
•
•
•
Multiprocessor shared memory
Asynchronous interprocessor communication
Data buffenng between asynchronous processes
Software FIFO buffers
General Description
The S6.1 C35 is a fast access Dual Port Memory Controller (D.P.M.C.). It allows fully asynchronous fast arbitration between two (2) different Ports (Microprocessor type interfaces). The winning Port is allowed
Pin Function
Functional Block Diagram
00,
01,
02,
03,
04,
05,
06,
07,
I
I
I
I
I
LEFT REG.
BANK LOGIC
I
I
I
_________ J I _ _ _ _ _ _ _ _ _ _
'0,
(~.C.)
",
iiii'L
m,
RIGHT REG.
BANK LOGIC
I
I
I
LEFT CS, iNi'
LOGIC
...
Al,
RIGHT CS, iNi'
LOGIC
I
I
I
00,
01,
02,
03,
04,
05,
06,
07,
iif~· (O.C.1
m,
REGISTER BANKS
16
MODE
R/W,
CSRL
R/W,
m,
ADOR STEERING
LOGIC
UoL
ED,.
liiiiA,
i5!ii,
Ii!!
"'- _ _ _ _ _ _ _ _ _ _ _ _ _ .J
(~.C.) ~L
m,
ARBITRATION UNIT AND
CONTROL LOGIC
OE
w
3.202
R/W,
m,
iii!'I,
UIi,
ED,.
Alii,
liiiiA,
i5!ii,
i&
re!
i5!ii"
re!
MODE
VSS
liiiiA,
i&
",
M,
Alii,
RiW STEERING LOGIC
."
""
06,
01,
AD,
BUSYN (~.C.)
----------------------
"..
os,
UIi,
ro,
..
0",
01,
02,
03,
M,
m,
I§
~ I~ I~ Ii i9 ::~ ,=:' 95' I~ I~ ~~
!, CONTENTION LOGIC
LEFT
PORT
41
10
11
12
13
"
"
RIGHT
PORT
0"
01,
02,
03,
0',
OS,
",
...",
01,
iii,
ill
31
m,
"
"
m,
Ii!!
R/W,
"
35
16
17
33
32
1iiSV,
UIi,
18
18
31
30
iD"
voo
15
"
21
22
23
"
...
.,
..
IS
m.
IiIiM,
Ii1l\.
Ilr
W
GOULD
AIMII®Semiconductors
S61C35
Figure 1.
Example Configuration of S61C35 forNK x 16 Dual Port Memory
•
VSS
(0 1
Delt
-
iNT~
(D.C.)
•
CONTROLI
STATUSI
MESSAGE/
REGISTERS
AD,
Al,
CSCL
(01 - Dal"
AD,
",
CScA
I
CONTENT)ON I
:L ___________
LOGIC
:I
iiSf
UOl
AODRIeS STEERING
LOG)C
BUSYII
lOt
-----------
AENL
RtVi STEERING
m,
CSRL
10.C.) ElUSY t
DOIR l
m,
CSRR
AEN~
LOGIC
DOIR"
DDENA
ucs
A/II - A,
(D.C.)
UoR
loA
DDENl
-~
LCS
Vi
OE
5240
lS24
/
/
/
lS24S
SINGLE PORT
RAM
r-
DATA
ADDR
J
1
I
DATA
Dl~ - Da
L+
.8
V
:1
..
V
~
DUAL PORT MEMORY SYSTEM
DUAL PORT
MEMORY SYSTEM
~~+-----~-------+--r-~
DoiR:
- _=.
iNTA 10.C.)
-., ----------1--
MODE
1
VDO
HI
LOW
= OUT
= IN
LS24D
DOiR: HI
= OUT
lOW", IN
3.203
.~tAM - A,
DATA
Ou - Dc
-} GOULD
AIMII®Semiconductors
S61C35
control signal access to a bank of user selected and
designed dual ported memory (SRAM, DRAM, EPROM,
etc.). (See fig. 1 for example). The loosing Port is sent
a busy signal to indicate it should wait for access. The
S61C35 allows the system designer to create fast inexpensive dual ported memory out of existing single port
RAM chips of any variety and type (SRAM, DRAM,
EPROM, etc.). He also has the freedom to create any
desired depth or width to his dual port memory.
.Dlp Pin Description
In addition to fast, arbitrated, dual ported user designed
memory, each port can access its own on chip register
bank, composed of four (4) independent registers per
port for added control features. These registers are
control, status, message-in, and message-out. They allow the system designer the ability under program control to lock out the opposite port to access of the dual
ported memory. There is also the ability for the locked
out port to override this condition and select whether he
will receive a busy condition in hardware when he is
locked out. Furthermore, there is a complete facility for
message passing between ports via status register
handshake flags. Both the locking and message passing facility cause appropriate status bits to be set or
cleared. The control register allows selected masking of
these status bits to form a master interrupt to the user.
Finally, the S61C35 can be used in a slave mode
through use of a hardware mode pin. This allows selected options for ganging of controllers.
Detailed Description
The Dual Port Memory Controller (S61 C35) is a high
speed dual ported arbitration unit between two (2) fully
asynchronous ports to allow multiplexed access to a
user defined dual ported memory, built from off the
shelf single ported RAM devices. In this way, a user
can define and build his own dual port memory system
in accordance to his own specified depth, width, speed,
type (Le., SRAM, DRAM, EPROM, etc.) or other
considerations.
Pin
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DOL
D1L
D2L
D3 L
D4L
D5 L
D6 L
Dh
AO L
A1L
INTL
CSC L
MODE
RiWL
CSR L
BUSY L
UD L
LDL
VSS
AENL
DDIRL
DENL
UCS
LCS
17
18
19
20
21
22
23
24
Pin
Name
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26 .
25
DO R
D1R
D2R
D3 R
D4A
D5 R
D6 A
D7A
AO R
A1R
INTA
CSC A
RST
RiWR
CSR R
BUSY R
UD A
LOA
VDD
AENR
DDIRA
DENR
OE
W
the necessary dual port memory system control signals.
They are broken down into two (2) classes:
I Arbitration Unit and Control Logic
1) RAM enable signals for the winning ports data and
address lines (DDIR, DEN, AEN). And
2) RAM Control signals for the winning port to control
the sin~o.!!. RAM of the user's own specification
(UCS, LCS, W, OE).
The Dual Port Memory Controller (D.P.M.C.) uses the
input signals of CSR L and CSR R to asynchronously arbitrate as to who will gain access to the user defined
dual port memory system. Once arbitration is complete,
the loosing port receives its BUSY signal low, as long
as its CSR is low. The D.P.M.C. will then use the status
Signals of RiW, UDS, LOS of the winning port to create
The RAM enable signals are used in conjunction with
user defined external data and address drivers (e.g.,
74xx245, 74xx240 or similar type). The RAM control
signals are used to form an upper and/or lower chip
select for the user specified sing~ort RAM. These are
directly generated from UD and LD of the winning port.
Furthermore, the RiW of the winning port generates the
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I
Pin Description
I
Pin Name
110
D7 uR-DO UR
I/O
A1 uR-AO uR
I
Address lines for left/right port register bank register selection.
CSC UR
I
System chip select for left/right port register bank.
INTuR
Mode
O(O.C.)
I
Pin Function
8 bit bi-directional data bus, for access to the left/right port register bank.
Interrupt output for left/right port. (Open collector output)
Allows selection of controller mode for either:
Hi = Master Mode
lo = Slave Mode
I
Reset input for the controller.
RIWuR
CSR UR
BUSYUR
I
Read/write input for the left/right port register bank, as well as dual port memory control logic.
I
System chip select for left/right port dual port memory system access.
left/right port busy flag to indicate port has lost dual port memory access or control/status register
bank access rights. (Open collector output)
UDUR
I
lDuR
DDIRuR
I
System left/right port lower data strobe.
a
a
a
a
a
a
System left/right port data direction output control line.
i5ENUR
UCS
lCS
OE
W
System left/right port upper data strobe.
System left/right port data enable output control line.
Single port RAM. Upper (byte, word, etc.) chip select line.
Single port RAM. lower (byte, word, etc.) chip select line.
Single port RAM output enable line option.
Single port memory write control line.
-
-
-
Note: Both left and right ports are designated together for clarity. (i.e. CSC L , CSC R = CSC UR )
appropriate Vi or OE for the single port RAM. Table 1
shows the port's status signals and resulting winning
ports RAM enable and RAM control signal generation. It
must be kept in mind that it is the user's responsibility
to alleviate any possible common 110 contention problems in his dual port memory system from use of common I/O single port RAM.
II Register Bank
A) General Overview
The Dual Port Memory Controller (D.P.M.C.) has two
separate independent register banks, one for each port.
Each register bank has its own separate chip select
pins (CSC L, CSC R) for access to that port's register
bank. There are four registers within each register
bank, which are separately addressed by each port
through their respective A1-AO address lines. This allows for four (4) internal registers per register bank and
are designated in Table 2. Each register bank uses its
appropriate RIW signal to read and write to its registers.
It is important to note that except for Control Register
(CRO) and Status Register (CR1) each port can simUltaneously read or write to its own register bank independent of the other port. The register banks are also
separately selected (CSC UR), apart from the dual port
memory chip selects (CSR uR ) and are on-board the
chip. The register banks contain four (4) separate registers each, and their access is outlined in Table 3.
They are: 1) Control Register (CRO)
2) Status Register (CR1)
3) Message-In Register (CR2)
4) Message-Out Register (CR3)
Figures 3-5 show the Left/Right port register bit
definitions of (CRO-CR3) respectively.
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O(O.C.)
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AIMII®Semiconductors
S61C35
Table 1. Control Signals Generated For Winning Port
A.
UDUR
LDUR
eSR uR
a
a
1
1
a
1
a
1
a
a
a
a
Les
ues
0
1
0
1
a
a
1.
1
•
GENERATES.
Port That Loses Has Its UD, LD Ignored
B.
CSRUR
RffluR
a
a
1
a
GENERATES
..
DENIJR
-,
DDIR UR
Vi
OE
1
a
1
a
1
a
a
0
Pori That loses Has lis DEN = 1
DDIR = a
'DDIR Is Defined as a = Data Direction Is Into Single
Pori RAM
1= Dala Direction Is Out of Single
Pori RAM
Table 2.
Register Banks
LEFT PORT
REGISTER BANK
RIGHT PORT
REGISTER BANK
CONTROL REG.
STATUS REG.
MESSAGE IN REG.
MESSAGE OUT REG.
CONTROL REG.
STATUS REG.
MESSAGE IN REG.
MESSAGE OUT REG.
The left pori's message out register becomes the
right pori's message in register.
The right pori's message out register becomes the
left pori's message in register.
Table 3. Left/Right Port Register Bank (Access)
CONTROL SIGNALS
A1
Aa
a
a
REGISTER NAME
ABBREVIATED
NAME
CONTROL REGISTER
CRa
esc RNi
a
110
a
t
a
110'
STATUS REGISTER
CR1
1
a
a
I
MESSAGE IN REGISTER
CR2
1
1
a
110
MESSAGE OUT REGISTER
CR3
'ONLY BITS O2 -0 0 CAN BE WRITIEN
roo
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S61C35
Figure 2.
I
I
Left/Right Port Control Register (CRO)
(If Current Port
= Left/Right, Then Opposite Port = Right/Left)
MIE IIE"l IIE"2 IIE"3 IIEN41 E"BSY
07
06
05
04
03
02
I
LOV
LOC
01
DO
INTERRUPT MASK BITS
I
.
L
I
1 = CURRENT PORT TO LOCK OUT
OPPOSITE PORT FROM DUAL PORT
MEMORY ACCESS
o = DON'T LOCK OUT OPPOSITE PORT
LOCK OVERRID E
1 = RELEASE LOCK OUT OF CURRENT PORT IF IT
IS LOCKED OUT BY OPPOSITE PORT
o = DON'T OVERRIDE LOCK
ENABLE BUSY PIN
1 = ENABLE BUSY PIN ON CSii OF CURRENT
PORT, IF IT IS LOCKED OUT
o = DISABLE BUSY ON CSR OF CURRENT PORT IF
IT IS LOCKED OUT
INTERRUPT ENABLE BITS
1 = ENABLE CORRESPONDING INTERRUPT STATUS BIT
o = DISABLE CORRESPONDING INTERRUPT STATUS BIT
IEN1-IEN4-ENABLE BITS FOR CORRESPONDING INTERRUPT
STATUS BITS (MO, MI, LAK, SLOe) OF STATUS
REGISTER,
MASTER INTERRUPT ENABLE
1 = ENABLE MASTER INTERRUPT
o = DISABLE MASTER INTERRUPT
MIE-ENABLE BIT FOR MASTER INTERRUPT (INT) OF
STATUS REGISTER,
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Figure 3.
Left/Right Port Status Register (CR1)
(If Current Port
INT
07
= Left/Right, Then Opposite Port = Right/Left)
I I I I I
MI
MO
LAK
SLOC
06
05
D4
D3
D2
D1
DO
INTERRUPT STATUS BITS
GENERAL BITS FOR USER (READ AND WRITE)
SOFTWARE LOCK
1 = CURRENT PORT HAS BEEN LOCKED OUT BY
OPPOSITE PORT
o = CURRENT PORT IS NO LONGER LOCKED DUT
BY OPPOSITE PORT
LOCK ACKNOWLEDGE"
1 = OPPOSITE PDRT HAS BEEN LOCKED OUT BY
CURRENT PORT SETTING LOC(DO)(CRO) BIT
o = OPPOSITE PORT HAS NOT BEEN LOCKED OUT
BY CURRENT PORT SETTING LOC(DO)(CRO) BIT
MESSAGE OUT
1 = CURRENT PORTS MESSAGE OUT REGISTER
HAS BEEN READ BY OPPOSITE PORT
o = CURRENT PORTS MESSAGE OUT REGISTER
HAS NOT BEEN READ BY OPPOSITE PORT
MESSAGE IN
1 = OPPOSITE PDRT HAS WRITTEN INTO
CURRENT PORTS MESSAGE·IN REGISTER
o = CURRENT PORT HAS READ ITS MESSAGE IN
REGISTER.
MASTER INTERRUPT""
1 = INT PIN GOES LOW
o = iNi' PIN GDES HI
"LAK (LOCK ACKNOWLEDGE) (D4)(CR1) OF THE CURRENT PORT IS SET. ONLY AFTER THE
"LOC(DO)(CRO) OF THE CURRENT PDRT IS SET AND LOC(DO)(CRO) OF THE OPPOSITE PORT HAS NOT
BEEN SET.
""INT(D7)(CR1) IS THE CURRENT PORT'S MASTER INTERRUPT.
INT(PIN) = INT· MIE
WERE INT = (MI· IEN1) + (MD, IEN2) + (LAK' IEN3) + (SLOC • IEN4)
INT IS GENERATED ON THE
S
OF ANY OF THE INTERRUPT SOURCES IF THEY ARE ENABLED.
THE MASTER INTERRUPT (lNT). IS CLEARED BY READING THE STATUS REGISTER. WHILE EACH
INTERRUPT STATUS BIT (MI. MO. LAK. SLOC) IS CLEARED BY THE APPROPRIATE ACTIDN. THE
INTERRUPT STATUS BITS (MI. MO. LAK AND SLOC) CAN ALWAYS BE READ AS TO THEIR STATUS.
NOTE: THE CONTROL REGISTER (CRO) LEFT AND (CRO) RIGHT ARE ARBITRATED AGAINST EACH
O~HER TO PREVENT MUTUAL SIMULTANEOUS LOCK·OUT. THEIR ACCESS IS MUTUALLY
EXCLUSIVE. THE STATUS REGISTER (CR1) LEFT AND (CR1) RIGHT ARE ALSD ARBITRATED TO
ENSURE NO LOOSE OF INTERRUPT SETIING.
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S61C35
Figure 4.
Left/Right Po.rt Message In Register (CR2)
(If Current Po.rt
= Left/Right, Then Oppo.site Po.rt = Right/Left)
_:1'
-
07
06
05
04
03
02
01
.
00
I
MESSAGE·IN REGISTER
ANY 8 BIT BYTE WRITTEN TO THE OPPOSITE
PORTS MESSAGE·OUT REGISTER WILL GO TO THE
CURRENT PORTS MESSAGE·IN REGISTER.
Figure 5.
Left/Right Po.rt Message Out Register (CR3)
(If Current Po.rt = Left/Right, Then Oppo.site Po.rt = Right/Left)
07
06
05
04
03
02
01·
00
MESSAGE·OUT REGISTER
ANY 8 BIT BYTE WRITTEN TO THE CURRENT PORT'S
MESSAGE·OUT REGISTER WILL GO TO THE OPPOSITE
PORT'S MESSAGE·IN REGISTER.
B) Co.ntro.l and Status Register Detailed Descriptio.n
The following is a detailed description of the control and
status registers. This description applies to the left or
right port (see figures 3-5 as references). This description is for a control/status register of the same port.
Co.ntro.l Register Bit Descriptio.n (D7-DD) o.f (CRD)
(If current port = left/right, then opposite port =
right/left)
MIE(07)(CRO) = Master INT Enable
When set to 1, this enables the master interrupt
INT(07)(CR1) of the status register. If INT(07)(CR1)
goes to 1, then INT pin will go low. When set to 0, this
will disable the master interrupt INT(07)(CR1) of the
status register. If INT(07)(CR1) goes to 1, the INT pin
will not go low.
IEN1-4{D6.;.03){CRO) = Interrupt Enable Bits 1-4
Each bit is an interrupt enable bit for the corresponding
interrupt status bit in the status register. When set to 1,
they enable the corresponding bit in the status register
to form the master interrupt.
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AIMII®Semiconductors
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This guarantees that there is never a case of mutual
lock out by both ports simultaneously setting their respective LOC(OO)(CRO) bits.
INT PIN = (INT, MIE)
were INT = (MI, IEN1) + (MO' IEN2) +
(LAK' IEN3) + (SLOC~ IEN4)
were INT, MI, MO, LAK, SLOC = 07-03 (CR1) of the
status register.
and MIE, IEN1, IEN2, IEN3, IEN4, = 07-03 (CRO) of
the control register.
Status Register Bit Description (D7-DO) of (CR1)
(If current port = left/right, then opposite port =
right/left).
=
ENBSY(D2)(CRO)
Enable Busy
When set to 1 on the current port, this enables the
BUSY pin for the current port, to be activated by the
current ports CSR pin, if that port has been locked out
by the opposite port. This allows the locked out port to
have a hardware BUSY pin status for the locked condition, if it trys to access the Dual Port Memory with its
CSR pin. When ENBSY bit of the current port is set,
BUSY pin of the current port will follow the current ports
CSR pin in logic sense if the current port has been
locked out by the opposite port.
=
. LOV(D1)(CRO)
Lock Override
This bit is enabled to be set on the current port only
when the current port has been locked out by the opposite port and the current ports SLOC bit has gone to 1.
Only at that time, can the user set the LOV(01 )(CRO)
bit. When set, this bit will unlock the current port and
then the current ports SLOC bit will go low. When this •
happens LOV(01 )(CRO) will automatically be cleared
and disabled. In this way, neither port can permanently
unlock his port.
INT(D7)(CR1) = Master Interrupt
This bit is set by the leading edge of any of the status
bit flags (1M, MO, LAK, SLOC) of the same port. As explained before, these bits are enabled by IEN1-4 of the
same ports control register (see IEN1-4(06-03)(CRO) of
control register).
MI(D6)(CR1) = Message-In
When set to one, this flag indicates that the opposite
port has written a message into its message-out regis. ter and is ready to be read on the current port's
message-in register. When the current port reads its
message in register, this flag bit is cleared .
=
MO(DS)(CR1)
Message Out
When set to 1, this flag indicates that the opposite port
has read its message-in register and the current port is
clear to write new data into its message-out register.
When the current port writes new data to its messageout register, then this flag bit is cleared.
LAK(D4)(CR1) = Lock Acknowledge
This is an acknowledgment flag bit that tells the current
port that it has successfully locked out the opposite port
from dual port memory access. This occurs when the
current port sets its LOC(OO)(CR) bit. If the opposite
port has not already set its own LOC bit, then the current port will lock out the opposite port and then the
current ports LAK flag bit will be set.
The user should always check his SLOC(03)(CR1 ) bit
to make sure that he is unlocked before trying to ac•cess the dual port memory again.
LOC(DO)(CRO) = Lock Out
When set to 1 on the current port, the opposite port will
be locked out from dual port memory accesses if the
current port's SLOC(03)(CR1) bit was not previously
set. If the current port's SLOC(03)(CR1) bit was set,
this would mean the current port was already locked
out. In this case, the LOC bit of the current port will
be set, but will not take effect until either the current
port clears its locked out condition by using its
LOV(01 )(CRO) bit or the opposite port clears its
LOC(OO)(CRO) bit. It is. important to note that the con:
trol register, as well as status register of both register
banks, are arbitrated against each other, to prevent simultaneous access ..
=
SLOC(D3)(CR1)
Software Lock
This is a software status flag that indicates that the current port has been locked out of dual port memory access by the opposite port. When set to 1, in the current
port, the opposite port has set its LOC(OO)(CRO) bit
and the opposite ports LAK(04)(CR1) flag bit has in
turn been set, indicating the opposite port has locked
out the current port. It is cleared when either the opposite port clears its LOC(OO)(CRO) bit, or the current po~
sets its lock override bit LOV(01 )(CRO) to override the
lock.
3.210
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S61C35
Setting/Clearing Status Flags
The master interrupt (INT) bit is a combination of MO,
MI, LAK, or SLOC bits of the status register, depending
on which of these bits is enabled by their corresponding
interrupt enable bits of the control register (lEN 1-4
respectively).
The master interrupt (INT) bit is cleared on any subsequent reading of the status register. The individual interrupt status bits (MO, MI, LAK, SLOC) are cleared in the
following way:
1) MO, MI
-are cleared in the status register by subsequent reads or writes to the same ports
message in and message out registers.
2) LAK
-is cleared by the opposite port overriding
its lockout, or the current port clearing its
LOCbit.
3) SLOC
-is cleared by the current port overriding
its lockout by using the lock override bit
LOV, or by the opposite port clearing its
LOCbit.
C. Reset
On reset, the following bits are set in the Left/Right Port
Register Bank:
(D7-DO)(CRO)-Control register
(D7 -DO)(CR1 )-Status register
(07 -DO)(CR2)-Message-in register
(D7 -DO)(CR3)-Message-out register
0000000
0010000
0000000
0000000
D. Mode
The mode pin is a special pin that is used to switch the
S61C35 from a master device to a slave device. When
set to one, the S61C35 is a master device and
operates as previously described in the datasheet. In
certain cases where the user needs more than one
controller, he can combine several S61 C35s together.
In this case, one controller can be the master mode in
that all contention arbitration and register banks will be
in the master and only the master will output the BUSY
pin. The other S61 C35s can be in a slave mode in
which their BUSY pins become inputs which would be
tied to the master's BUSY output. This makes the slave
control signals dependent on the BUSY of the master.
When an S61 C35 is in the slave mode, its contention
arbitration and register banks are turned off to allow
only one master device. It should be noted that using
the S61 C35 in a slave mode will effectively double the
overall access time of the system due to the added
propagation delay from the master BUSY output to the
slave BUSY input and subsequent enabling and generation of control signals. This can be reduced however
with careful system design considerations.
Design Precautions
The user has the flexibility of reading his own status
register by a polling method or interrupt method. If the
user uses the polled method for an indication of lockout, he should be aware that if he does not have his
ENBSY(D2)(CRO) bit on, and is not locked out, he
could begin to write to the Dual Port Memory System,
and if at that exact same time, he does become locked
out, he could complete his write cycle with no BUSY to
him. As a result, he would perform a write to the dual
port memory and never know that it never was accomplished. This can never happen if his lock was interrupt
driven.
Other such potential problems could exist and it is the
designer's responsibility to realize these and understand
how he wants to program the device.
3.211
I
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- _=.
I
-} GOULD
AIMII®Semiconductors
S61C35
Absolute Maximum Ratings
DC Supply Voltage (Voo - Vss) ..... "' ............................................................ +7V
Operating Temperature ........ ; ..................................................... : .... O°C to + 70°C
Storage Temperature ................................................................. -55°C to +150°C
Digital Input ........................................................... Vss - O.3V .;;; VIN ,;;;Voo +O.3V
D.C. Electrical Operating Characteristics: TA = O°C to +70°C; Voo= +5V (±10%); Vss = OV unless
otherwise specified
Symbol
VIH
VIL
VOH
VOL
Po
Parameter/Conditions
High Level Logic Input
. Low Level Logic Input
High Level Logic Outputs IOH = .8mA
Low Level Logic Outputs IOL = 4.0mA
Power. Dissipation @ ±5.5V
Minimum
2.0
Typical
Units
V
V
V
V
mW
Maximum
Voo
+0.8
Vss
2.4
0
Voo
+0.4
150
AC Electrical Characteristics (Vee = 5V ±10%, al\ temperature ranges)
No
Parameter Description
Test Condition
(Note)
f-;;;;--,--;;;---,-;;:;-:--l
Units
BUSY Timing
35ns
(typical) then tRAGis as given. If tRS < 35ns, then tRAG is not valid as given but will follow IeSAG, timing.
3.213
I
ns
ns
30
30
10
- _=.
ns
Interrupt Timing
@
@
@
1
-) GOULD
AIMII®Semiconductors
S61C35
Figure 6.
C'S'RLJR to BUSYRIL (Left/Right Port-Not Locked Out)
j-..--------CD---------'
CSRUR-----~~'~
~'~r---------
BUSY R/L
Figure 7.
C'S'RLJR to BUSYRIL (Left/Right Port-Locked Out)
CD
CSR UR
BUSYR/L
-
-
,r
-it-
t
- FCD
CD
3.214
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AIMII®Semiconductors
S61C35
1_:
I
. Figure 8. CSR UR Contention Arbitration ('C'SRLValid First) .
..
CSRL
o
CSR
R
BUSY R
..
1
'-)
I.-
4 (2) __
1
/ / / / / / / / /
CD
I
I
+
.
I
I
f-
~0)
=1--3
1-0
0)-
Figure 9. CSR UR Contention Arbitration ('C'SRR Valid First)
~-------CD--------~
I~~~~~~~~-
0(2)
-
~---CD-----~
CSRL--~I
~---------------I~--------------------~~
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AIMII®Semiconductors
S61C35
Figure 10. BUSYUR to Control Signals Valid (Left/Right Port) of Winning Port from Contention Arbitration
.
(Master Mode)(7)
1
CSR lIR
BUSvRlL
AENl/R
F-:
f---CDIf-
-
f--®-
~G)
..,
DENlIR(6)
DDIR lIR(6)
UCS(6)
-0~
LCS(6)
W(6)
OE(6)
3.216
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AIMII®Semiconductors
S61C35
I
I
Figure 11.
BUSY uR to Control Signals Valid (Left/Right Port) of Winning Port from Contention
Arbitration (Slave Mode)(8)
(INPUT)
AENuR
I
f-G)~
-'r-
DENuR(6)
-- -CD
DD1RuR(6)
UCS(6)
LCS(6)
r-CD.:1
t
-f--.
W(6)
OE(6)
Figure 12.
Register Bank (Left/Right Port) (Read Cycle)(4,5)
~------------CD----------~
A1, AD
----~I'~--------------------------------~~--------
-®~,
(0 7
-
1
- _=.
f-
k-
I
Do)uR PREVIOUS DATA VAjJD1==========D~A:TA2v~A~LI~0=====:======)--
3.217
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S61C35
Figure 13. Register Bank (Left/Right Port) (Read Cycle)(3,4)
A1, AD
..
(3)
CD
CSC UR
(3)
~
~®-+®II IIII IJ VII/;r-
f--@-R
Figure 14.
DATA OUT
DATA OU T
Register Bank (Left/Right Port) (Write Cycle)(3)
@
-
~®
(iii Controlled)
..
-.
A1, AD
®
(3)
(3)
-r-
.
R/WUR
..
®
®~ ~®-
\\~
~®R
DATA IN
DATA IN
r-®-..
R
DATA OUT
DATA UNDEFINED
3.218
-
.~@
r---
-@
-} GOULD
AIMII®semiconductors
S61C35
Figure 15.
Register Bank (Left/Right Port) (Write Cycle)(3) (CSC UR Controlled)
1
15
- _=.
A1, AD
I
(17)
CSC UR
®
(3)
--'l--
~
@-
®
\\\\\\\\
\\\\\\
r
~®-DATA IN
DATA IN
(0 7
Figure 16.
-
Do)uR
DATA OUT
r-@
1
L®~
DATA UNDEFINED ~II-----------
Interrupt Timing (Interrupt Setting)(9)(11)
~
R/WUR
~®--\
f--
~@-' .....
3.219
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S61C35
Figure 17. Interrupt Timing (Interrupt Clearlng)(10)
CSC UR
RJWUR
-
-I<-
f--@
Illh
-
3.220
~@
r
16-Bit
Bounds Checker
-) GOULD
~MII®Semiconductors
Preliminary Data Sheet
S61C337
1
Features
• Applications include;
-Arithmetic underflow/overflow checking
-Virtual memory to real memory address boundary
comparisons
• Double Comparator
-Compares a 16-bit input number with a lower limit
and an upper limit
• Cascadable
-16-bit cascadable to longer words
• Out-of-Bounds Flag
-Flags values that are outside the bounds of a
lower and an upper limit
- _=.
• Compares Signed or Unsigned Numbers
• 28-Pin Plastic Dip Package
• CMOS
I
General Description
The S61 C337 is a 16-bit bounds checker, which can
compare a 16-bit signed or unsigned number with a
. lower and an upper bound limit stored in registers. The
device can flag values that are out of bounds, as well
as inbounds. The device is also cascadable up to
32-bits or greater.
Block Diagram
Pin Configuration
16
ENu
ENl
CP
Cil
008
Clu
GNO
NC
COL
00
01
O2
03
Clu
SIGNED
COL
008
CO u
3.221
0 15
0 14
013
0 12
CO u
SIGNEO
011
010
09
08
CP
Voo
~Nl
ENu
04
05
06
01
Cil
-) GOULD
AIMII®Semiconductors
S61C337
Pin Name
Pin Function
110
0 15-0 0
I
Input to limit registers and comparators.
EN l , ENu
I
Load enable signals for the limit registers.
CP
I
Clock pulse to load limit registers when enabled. (Low-to-High transition)
Cll, Clu
I
Carry input signals for cascading.
COL, CO u
0
0
Carry output signals from results of comparisons.
OOB
SIGNED
I
Out-of-boundssignal to flag values that are out of bounds. Defined as (COL • CO u).
Hi-selects signed comparisons.
Low-selects unsigned comparisons.
No connect
GND
-
VDD
-
Power, +5V
NC
.
Ground
Detailed Description
The S6iC337 is a high speed CMOS bounds checker
that can determine if a signed or unsigned i6-bit number lies within a lower and upper limit. The device can
easily be cascaded for larger words.
Limit Registers and Comparators
The S6iC333 has an upper limit and lower limit registers. These registers are loaded from the 0 15 -0 0 bus
with the load enable inputs EN u, ENl arid clock pulse
CP, rising edge. The values then presented to the
D15-Do data bus are compared with the values stored
in the limit registers through comparators. The comparators can operate on either signed or unsigned numbers depending on the SIGNED signal input (Hi =
signed, Low =:' unsigned). The results oUhe compari- '
son are given in the outputs CO u C l , and OOB. The
definitions of carry inputs Clu and Cil are given in
Table-i and the combination of the different regions
Table-2. If ,data being compared is out of the region,
the out-of-bounds flag OOEl, is set which is defined
as (CO u • Cad.
slice (LSS) with Cl u, Gil of the LSS acting as inputs to
the overall bounds checker. The CO u , Cal of the LSS
slice act as inputs to the most significant slice (MSS)
inputs Cl u , Cil' The MSS outputs CO u, cal and OOB,
act as the outputs of the overall bounds checker. The
SIGNED input of the MSS identifies the value when
being compared with either signed or unsigned numbers when the SIGNED input of theLSS is tied low.
The comparison can also start from the MSS. In this
case, CO u, Cal, OOB of the LSS act as outputs of the
overali bounds checker, while CO u , Cal of the MSS
•are connected to Cl u , Cil of the' LSS.
Table 1.
Outputs
Inpuls
Cil
0
0
1
1
Cascading
Comparison of numbers longer than i6-bits requires
cascading of two or more bounds-checker slices. (See
Fig.-i) The comparison starts from the least significant
Definition of COL and COu
Note:
o ~ Data Input
l ~ lower Unit
U ~ Upper Unit
3.222
Clu
0
1
0
1
COL
CO u
Lt®~
X
X
X
{~
b@~
3.240
64-Bit Digital
Crossbar Switch
-} GOULD
AIMII®Semiconductors
Preliminary Data Sheet
5618840
Features
• Hi speed, low power HCMOS digital cross bar switch.
• Programmable switch for parallel processing
applications.
• Dynamically reconfigurable for fault-tolerant routing.
• 64-bit bidirectional I/O's in 16-(4 bit) nibbles.
• Data switch source, programmable by nibble.
• Two banks of control flip-flops for storing switch
source configurations.
• Two selectable hard-wired switch source
configurations.
• CMOS technology with 5V operation and TTL 1/0
levels.
• Functionally compatible to TI 74AS8840.
General Description
The S618840 is a 64 Bit Digital Crossbar Switch. It
has 64 data 1/0 pins arranged in 16 switchable nibbles
(4 bits). There are 16, 4 bit multiplexers, which allows
each input nibble to be broadcast (switched) to any
other 1 to 15 nibbles, as output, in a single cycle. Multiple input nibbles can be switched to multiple output
nibbles, under control of programmable configurations
or hard-wired options (See Figure 1).
The control of the multiplexers is selectable from four
sources including two banks of programmable control
flip-flops (Bank 1, Bank 2) and two hard-wired control
circuits.
Pin Configuration
Block Diagram
CRClK
SElOlS
lSClK
SElOMS
MSClK
0E00
0E0i
03-00
132 PGA
(PLASTIC)
035-032
OED9
OED1
P
039-036
07-04
N
M
L
K
0Effi0
0ED2
011-08
043-040
64
OED3
i5EDfi
MUX 3
015-012
om
MUX 4
019-016
MUX 12
64
0E55
MUX 5
023-020
0ED6
MUX 13
MUX 14
MUX 6
027-024
64
om
MUX 15
MUX 1
031-028
J
047-044
(BOnOM VIEW)
0Effi2
051-048
F
E
0E0i3
D
055-052
0Effi4
059-056
oms
063-060
lPO. TP1
CRAOR1·n
CRSRCE
CRWRITE
CREAO
CNTR15-
CNTR11-
CNTR7-
CNTR3-
CNTR12
CNTR8
CNTR4
CNTRO
WE
3.241
C
..
B
~
1
PIN NO.1 INDEX
CRSEl1·0
H
G
A
91011121314
1
- _=.
I
-} GOULD
AMII®Seilliconductors
S618840
Figure 1. S618840 Digital Crossbar Switch
MSH
(MOST-SIGNIFICANT HALF)
(063-032)
LSH
(LEAST·SI(l~IFICANT
HALF)
(031-00)
MUX
LOGIC
03-00
INTERNAL
DATA BUS
64
64
MUX
LOGIC
4\
4
MUX
LOGIC
07-04
64
64
MUX
LOGIC
64
MUX
LOGIC
64
MUX
LOGIC
4
011-08
64
4
015-012
64
4
019-016
64
64
4
MUX
LOGIC
MUX
LOGIC
64
64
MUX
LOGIC
64
MUX
LOGIC
64
MUX
LOGIC
4
027-024
4\
031-028
f4
047-044
f4
051-048
j4
055-052
f4
059-056
4
64
4
MUX
LOGIC
043-040
4
4l
MUX
LOGIC
f4
4
4\
023-020
039-036
4
4\
MUX
LOGIC
f4
4
4\
MUX
LOGIC
035-032
4
4\
MUX
LOGIC
J4
4
64
4\
4
4
3.242
j4
063-060
-} GOULD
AIMII®Semiconductors
S618840
The S618840 is primarily intended for multiprocessor interconnection networks and parallel processing applications. In a more general sense, it can be used
whenever one needs to transfer data from multiple
sources to multiple destinations. Also, since the switching can take place dynamically, this device is also
suitable for reconfigurable networks for fault-tolerant
routing.
Pin Designation
Ai
A2
A3
TP1
CRSELO
A4
Vss
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
C1
C2
C3
C4
C5
CREAO
OEC
CNTR1
CNTR2
CNTR5
CNTR8
CNTR10
CNTR13
LSCLK
Vss
Vss
MSCLK
TPO
CRAOR1
CRSEL1
CWRITE
CRCLK
Vss
CNTR4
CNTR6
CNTR9
CNTR12
CNTR14
SELOLS
031
062
063
Voo
CRAORO
CRSRCE
C6
C7
C8
C9
C10
C11
C12
C13
C14
01
02
03
012
013
014
E1
E2
E3
E12
E13
E14
F1
F2
F3
F12
F13
F14
G1
G2
G3
G12
G13
G14
WE
CNTRO
CNTR3
CNTR7
CNTR11
CNTR15
Hi
H2
H3
H12
H13
H14
J1
J2
J3
J12
J13
J14
K1
K2
K3
K12
K13
K14
L1
L2
L3
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
Voo
029
028
OE015
061
SELOMS
030
OED7
Vss
059
Vss
060
027
026
025
056
057
058
024
OED6
023
054
OED14
055
022
Vss
Voo
3.243
Voo
Vss
053
020
OE05
021
052
OED13
051
017
018
019
050
049
048
015
Vss
016
~
OED12
045
OED3
014
OED4
047
046
Voo
042
039
OED9
032
OEDO
02
M10
M11
M12
M13
M14
N1
N2
N3
N4
N5
N6
N7
05
08
012
013
044
OED11
041
OED1D
037
035
033
N8
Vss
N9
N10
N11
N12
N13
N14
Pi
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P12
P14
01
OED1
06
OED2
010
011
Voo
Vss
043
040
038
036
034
OED8
Voo
00
03
04
07
09
Vss
-} GOULD
AIMII®Semiconductors
5618840
Pin Description
Pin Name
No.
00
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
P9
N9
M9
P10
P11
M10
N11
P12
M11
P13
N13
N14
M13
M14
L13
K12
K14
J12
J13
J14
H12
H14
G12
F14
F12
E14
E13
E12
C14
C13
012
B14
M7
N7
P6
N6
P5
N5
P4
M5
P3
N3
M4
P2
N1
L3
110
Description
liD
Bi-directional data liD pins
(031 :-00 are Least-Significant Half) (LSH)
liD
Bi-directional data liD pins
(063-031 are Most-Significant Half) (MSH)
3.244
«
-} GOULD
AIMII®Semiconductors
5618840
Pin Description (cant.)
Description
Pin Name
046
047
04B
049
050
051
052
053
054
055
056
057
058
059
060
061
062
063
OEOD
OEOI
OE02
OE03
OE04
OE05
OE06
OED?
OED8
OED9
OE01D
OEDII
OED12
OED13
OED14
OED15
No.
M2
M1
K3
K2
K1
J3
J1
H3
G1
G3
F1
F2
F3
E1
E3
D2
C1
C2
M8
N10
N12
L12
L14
H13
F13
013
P?
M6
N4
N2
L2
J2
G2
018
110
SELOLS
B13
I
Selects either data input registers or real-time data of (LSH) data input
to main internal 64-bit bus
SELOMS
03
I
Selects either data input registers or real-time data of (MSH) data input
to main internal 64-bit bus
LSCLK
A13
I
Clock input to clock (LSH) data input into data input registers ( ...r )
MSCLK
OEe
B1
I
Clock input to clock (MSH) data input into data input registers ( s)
A6
I
Output enable for CNTR15-CNTRO
1-:
-
.
I
Bi-directional data liD pins
(063-031 are Most-Significant Half) (MSH)
liD
Output enable for
nibbles within
i.e. OEOO OEDI -
·
I
··
OED15 -
3.245
data liD pins,
(063-00)
03-00
07-04
063-060
I
.) GOULD
AIMII®Semiconductors
S618840
Pin Description (cont.)
Pin Name
TP1
TPO
CRSELO
CRSEL1
CRSRCE
CWRITE
WE
CRADR1
CRADRO
CRCLK
No.
A2
82
A3
84
C5
85
C6
83
C4
86
110
CREAD
A5
I
CNTRO
CNTR1
CNTR2
CNTR3
CNTR4
CNTR5
CNTR6
CNTR7
CNTR8
CNTR9
CNTR10
CNTR11
CNTR12
CNTR13
CNTR14
CNTR15
C7
A7
A8
C8
88
A9
89
C9
A10
810
A11
C10
811
A12
812
C11
A1
E2
H2
L1
P1
NB
P14
K13
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Description
I
Test pins
I
Selects one of four control functions to control the multiplexers
I
I
I
Selects source load for control flip flop register banks
Control flip flop register bank select (CF(X)-bank1, CF(X)-bank2)
Write enable for control flip flop registers (CF(X))
Control flip-flop register address select. Decodes/selects, 1 of 4, 16 bit
groups of control flip-flops for I/O on CNTR15-CNTRO
Control flip flop register clock ( ...r)
Selects between control flip flop register banks (1) or (2), to read out
on CNTR15-CNTRO
I
I
I/O
Cantrall/D. Input/Output pins
(four groups of four bits,
for data liD to the control
flip flop registers addressed
by CRADR1-0)
-
Ground pins
3.246
-} GOULD
AIMII®Semiconductors
S618840
Pin Description (cont.)
Pin Name
Vss
Vss
Vss
Vss
Vss
Voo
Voo
Voo
Voo
Voo
Voo
Voo
.No.
G13
D14
A14
B7
I/O
Description
-
Ground pins
-
5-volt supply pins
A4
H1
M3
P8
M12
G14
C12
C3
Table 1. S618840 Response to Control Inputs
Signal
LSCLK
MSCLK
SELDLS
SELDMS
CNTR15-CNTRO
CRADR1-CRADRO
CREAD
CRWRITE
CRSRCE
WE
CRCLK
OEe
OED15-0EDO
CRSEL 1-CRSELO
TP1-TPO
High
Low
Clocks LSH of data input into input data
registers on low-to-hightransition
Clocks MSH of data input into input data
registers on low-to-high transition
Selects real-time LSH data input to main
internal data bus
Selects real-time MSH data input to main
internal data bus
Selects stored LSH data input to main
internal data bus
Selects stored MSH data input to main
internal data bus
liD pins for control flip-flops (see Table 7)
Selects 16-bit groups of control flip-flops as destination or
source for inputs or outputs on CNTR15-CNTRO (see Table 7)
Selects second bank of control flip-flops to
Selects first bank of control flip-flops to
read on CNTR15-CNTRO in 16-bit words
read on CNTR15-CNTRO in 16-bit words
addressed by CRADR1-CRADRO
addressed by CRADR1-CRADRO
Control flip-flops destination select (see Table 5)
Control flip-flops load source select (see Table 5)
Inhibits write to control flip-flops
Clocks CNTR15-CNTRO inputs into control
flip-flops
Inhibits output of data from control
flip-flops on CNTR15-CNTRO
Enables write to control flip-flops
Enables output of data from control
flip-flops on CNTR15-CNTRO
Inhibits output of data liD pin nibbles
Enables output of data liD pin nibbles
Selects one of four control functions to control the switch (see Table 2)
Test pins (see Table 8)
3.247
-} GOULD
AIMII®Semiconductors
S618840
This 64 bit internal data bus supplies 16 data nibbles to
16, 16 X 4 bit output multiplexers (MUX(16X4)). One of
the four selectable control sources controls the 16 X 4
bit output multiplexers to multiplex one of the 16 nibbles
of the 64 bit internal data bus to one of the 16 nibbles
of the data I/O pins, under control of a tri-state output
driver OEO(15-0).
Detailed Description
The 64 data I/O pins of the S618840 are arranged as
16, 4 bit nibble groups. Each of these nibble I/O pins is
. a bidirectional input/output to 1 of 16 nibble multiplexers
(See Figure 1, 2). Ouring a switching cycle, each multiplexer passes four bits of data, either stored in data input registers or as direct real-time data input, to a 64 bit
internal data bus. Then, each of the 16 nibble multiplexers independently selects 1 of 16 nibbles from the
internal data bus as output on 1 of the 16 data I/O pin
nibbles.
The input to output pattern of the entire crossbar switch
is controlled by the input and output multiplexers. Many
switching configurations can be selected by programming the control flip-flop banks to control the output selection from the 16 X 4 bit multiplexers (MUX(16X4)).
The 16 input data nibbles are organized into two groups
of 8 nibbles. These are: LSH (Least Significant Half)
and MSH (Most Significant Half). Oata to the internal 64
bit data bus, is selectable from the data input registers
or real-time data input by SELOLS for LSH and
SELOMS for MSH. Two clocks, LSCLK and MSCLK are
used to clock data into the data input registers for the
LSH, MSH respectively.
Multiplexer logic group (MUX(X), X = 15-0)
Input data flows into the 64 bit internal data bus and
thus each of the 16 multiplexers, on four data I/O pins
connected to a data input register and a 2 X 4 bit multiplexer (MUX(2X4». Oata inputs to the 4 bit internal data
bus are thus, either clocked into a data input register
and input, or passed directly to the internal bus. The 64
bits of internal data bus are presented to each of the
16 X 4 bit multiplexers (MUX(16X4)), which selects the
data nibble output.
Each output nibble, is selected from 1 of 16 nibbles of
the 64 bit internal data bus. This is done by a 16 X 4 bit
multiplexer; one for each output nibble (See Figure 2
& 3). These 16 multiplexers are controlled by a selectable control source input. This control source input can
be either one of two banks of programmable control
flip-flops, or one of two hand-wired control circuits. Inputs to the programmable control flip-flops can be
loaded from either a pre-defined nibble of the 64 bit internal data bus or from the CNTRL(15-0) pins. A separate CRCLK is used along with WE to load the banks of
the control flip-flops (See Figure 3).
Each of the 16 multiplexers (MUX(X), (X = 15-0) (Figure
3), contains two control flip-flop CF(X) nibbles, Bank 1
and Bank 2. Each CF(X) is composed of four Ootype
positive edge triggered flip-flops. Table 2 shows the
control source selection decoding.
Table 2. 16-to-1 Output Multiplexer Control Source
Selects
Architecture
The S618840 has its 64 data I/O pins arranged in 16
multiplexer logic groups (See Figure 2 and 3). Each
multiplexer group controls four bits of real-time data input and four bits of stored data input register to the
internal 64 bit data bus.
CRSEL1
CRSELO
0
0
1
1
0
1
0
1
Control Source Selected
CF(X) Flip-flOp Bank l'
CF(X) Flip-flop Bank 2'
MSH/LSH Exchange"
Read-Back (output echoes input)"
" Programmable
""Hard-wired control function
Two input controls are provided to select between the
stored data input register .or real-time data input to go
to the 64 bit internal data bus. These are SELOLS for
the LSH side (031-00) and SELOMS for the MSH side
(063-032). The data stored in the data input registers is
controlled by LSCLK for the LSH side (031-00) and
MSCLK for the MSH side (063-032). The 16 data input
nibbles (N(X)) make. up the 64 bit internal data bus.
In addition to the two programmable CF(X) banks,
there are two hard-wired, pre-defined control functions
which can be selected. The REAO-BACK source, allows each multiplexer to output its own input bits. (eg.
MUX(5) read back is (N(5), (023-020)), of the 64 bit internal data bus). The MSH/LSH EXCHANGE directs all
the nibbles of the LSH side and MSH side respectively
3.248
GOULD
AIMII®Semiconductors
5618840
I
I
I
Figure 2. Block Diagram-Digital Crossbar Switch 5618840
_:1'
i
.'H
"H
(LEAST SIGNIFICANT)
L.;
INTERNAL
HALF
SELDlS
D----"""'-
(MOST SIGNIRCANT)
HALF
~BIT
Offii
MSCLK
\
I I
MUXIS)
(BNK1/BNK2)
~
0Ei5i
~
"
IBNK11 SHIll
h
"
om
r
~
tBNK11 BNK2)
MUll;!)
015-012
(BNKll BNK2)
0EDi
~
~
"
019_016
~
(SNKtl BNK2)
0E05
r
~
MUXtS)
~
(BNKll BNK2)
0ED6
(tS_12)
(7-4)
~
r
"
MUK(6)
--Ci'(6'-.--..... 027_024
(BNKll BNK2)
(BNKll BNK2)
TPD
UST
Oslo'
Rs'IT, } - . . .
,m
r; 0iC
~
~
(7-4)
115-12)
~
~
16
;") , l
t
DEClO
-----CF(10)
043-040
(BNK1/BNK2)
0ffiIT
- - CF(11) - 047_D44
tONK11 BNK1)
0Eiii2
-----CF{1Z)
051_048
(BNK1/BNK2)
i5E6i3
-----CF(13)
055-052
~
(BNKll BNK21
0Effi'i
-----CF(14)
05;_056
16
2
LOAD
~NTR(15-0)
0Effi5 -
055-052
Table 3. MUX(X), N(X), N(EX), DYY-DZZ, CNTR VV-CNTR WW
X
MUX(X)
N(X)
DYY-DZZ
N(EX)
CNTR(VV-WW)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MUX(O)
MUX(1)
MUX(2)
MUX(3)
MUX(4)
. MUX(5)
MUX(6)
MUX(7)
MUX(8)
MUX(9)
MUX(10)
MUX(11)
MUX(12)
MUX(13)
MUX(14)
MUX(15)
N(O)
N(1)
N(2)
N(3)
N(4)
N(5)
N(6)
N(7)
N(8)
N(9)
N(10)
N(11 )
N(12)
N(13)
N(14)
N(15)
03-00
07-04
011-08
015-012
019-016
023-020
027-024
031-028
035-032
039-036
043-040
047-044
051-048
055-052
059-056
063-060
N(8)
N(9)
N(10)
N(11)
N(12)
N(13)
N(14)
N(15)
N(O)
N(1)
N(2)
N(3)
N(4)
N(5)
N(6)
N(7)
(3-0)
(3-0)
(3-0)
(3-0)
(7-4)
(7-4)
(7-4)
(7-4)
(11-8)
(11-8)
(11-8)
(11-8)
(15-12)
(15-12)
(15-12)
(15-12)
3.251
-} GOULD
AIMII® Semiconducton;
5618840
Table 4. 16 X 4 Bit Multiplexer Control Nibbles
Control Nibble Values
CN2
CN1
CNO
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
D3-DO
D7-D4
D11-D8
D15-D12
0
1
2
3
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
4
5
6
7
D19-D16
D23-D20
D27-D24
D31-D28
4
5
6
7
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
8
9
D35-D32
D39-D36
D43-D40
D47-D44
8
9
10
11
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
D51-D48
D55-D52
D59-D56
D63-D60
12
13
14
15
CN3
A
B
C
D
E
F
The CRSRCE pin controls the source used as input to
the CN(3-0) lines from the multiplexer, to then be used
as input to the CF(X) control flip·flops. As stated before,
this can be from either the internal data bus as nibble
N(EX) or from the external control I/O pins CNTR
(15-0). The CRWRITE pin selects whether bank 1 or
bank 2 of the control flip-flops is to be loaded. In effect,
CRWRITE and CRSRCE, together, control the source,
destination for loading the control flip-flops. (See Table
5).
Table 5. Control Flip-Flops Load Selects
CRSRCE CRWRITE
0
0
1
1
Nibble from 64 Bit Internal
Data Bus Selected as
Multiplexer Output
CN(3-0)
Hex
0
1
0
1
Source and Destination
CNTR
CNTR
N(EX)
N(EX)
inputs to flip-flop bank
inputs to flip-flop bank
Data inputs to flip-flop
Data inputs to flip-flop
1
2
bank 1
bank 2
When either CF(X), bank 1 or 2 is beinJL!paded from
the internal data bus, the four signals; WE, CRSRCE,
CRWRITE, and the control flip-flop clock CRCLK are
used in combination, to load all 16 control nibbles in a
single cycle. Table 3 shows that internal data bus
nibbles on the LSH side of the switch are sent to the
N(X)
CN(3-0) control nibbles of the MSH side. Likewise the
internal data bus nibbles on the MSH side of the switch
are sent to the CN(3-0) control nibbles of the LSH side.
For example, the data nibble N(8) for MUX(8) would
use the internal data bus nibble N(EX)=N(O), (03-00)
as input to its CN(3-0) control nibble to be loaded into
CF(8) bank 1 or 2. Likewise, the data nibble N(O) for
MUX(O) would use the internal data bus nibble
N(EX)=N(8), (035-032) as inputs to its CN(3-0) control
nibble to be loaded into CF(O) bank 1. or 2. Table 6
shows the pattern for MSH/LSH exchange when a bank
of CF(X) flip-flops is loaded with CN(3-0) from the internal data bus as its sources.
.
When either CF(X), bank 1 or 2 is being loaded from
the external control 1/0 pins CNTR(15-0), the four signals; WE, CRSRCE, CRWRITE, and the control flip-flop
clock CRCLK are used. However, the CRAOR1 and
CRAORO pins address four control nibbles at a time to
be loaded in one clock cycle from the control 1/0 pins
CNTR(15-0). This can be seen in Table 7. Note that
the load sequence for each CRAOR1-0 address is
staggered. The same addresses of CRAOR1-0 in combination with CREAO and OEC will read out four CF(X)
groups at a time on the control 110 pins CNTR(15-0).
(See Table 6).
3.252
-} GOULD
AIMII®Semiconductors
5618840
Table 6. Inputs to Control Flip-Flops (CF)
Control Flip-Flop
Nibbles
Data Outputs
Affected
N(X)
CFO
CF1
CF2
CF3
03-00
07-04
011-08
015-012
CF4
CF5
CF6
CF7
CNTR Inputs to
Control Flip-Flops
Data Inputs to
Control Flip-Flops
N(EX)
N(O)
N(1)
N(2)
N(3)
CNTR3-CNTRO
035-032
039-036
043-040
047-044
N(8)
N(9)
N(10)
N(11 )
019-016
023-020
027-024
031-028
N(4)
N(5)
N(6)
N(7)
CNTR7-CNTR4
051-048
055-052
059-056
063-060
N(12)
N(13)
N(14)
N(15)
CF8
CF9
CF10
CF11
035-032
039-036
043-040
047-044
N(8)
N(9)
N(10)
N(11 )
CNTR11-CNTR8
03-00
07-04
011-08
015-012
N(O)
N(1 )
N(2)
N(3)
C12
CF13
CF14
CF15
051-048
055-052
059-056
063-060
N(12)
N(13)
N(14)
N(15)
CNTR15-CNTR12
019-016
023-020
027-024
031-028
N(4)
N(5)
N(6)
N(7)
Table 7. Loading Control Flip-Flops From CNTR 1I0's
CRADR1
CRADRO
WE
0
0
L
L
L
L
H
Control (CNTR)
1/0 Numbers
CRCLK
15-12 11-8
0
1
1
0
1
1
X
X
J
CF12
CF(X)
Selected
7-4
3-0
CFB
CF4
CFO
12,B,4,O
13,9,5,1
J
CF13
CF9
CF5
CF1
J
CF14
CF10
CF6
CF2
14, 10, 6, 2
s
CF15
CF11
CF7 CF3
Inhibit write to flip-flops
15,11,7,3
X
Table 8. Test Pin Inputs
TP1
TPD
OED15-0EDO
OEC
0
0
0
0
All outputs and liDs forced low
Result
0
1
0
0
All outputs and liDs forced high
1
0
X
All outputs placed in a high-impedance state
1
1
X
X
X
Normal operation (default state)
Test Pins
The test pins TP1-TPO are provided for various system
tests. The normal operation as depicted in Table 8, is for
the test pins to be in a high state. To force all outputs in
a high impedance state (CNTR(15-0) and 063-00),
set TP1 = high and TPO = low. To force all outputs in
a high state, set TP1 = low, TPO = high. To force all
outputs in a low state, set TP1 = low, TPO = low.
3.253
- ~:
I
.
I
-} GOULD
AIMII®Semiconductors
5618840
Programming Examples
Programming the S618840 is a straight forward procedure involving few control signals and procedures to set
up the switch configurations by loading the control
words in the control flip-flop banks. The following examples, help to demonstrate the control signals and
procedures for loading and using control words.
MSH/LSH Exchange
This example will show two ways to swap LSH nibbles
to MSH nibbles. This can be done by two methods,
either using the predefined control source MSH/LSH
EXCHANGE selected by the CRSEL(1-0) pins or by
separately loading the CF(X) control flip-flops of each
multiplexer with the proper control nibble to select the
exact opposite nibble for an MSH/LSH exchange.
are brought low. The result is to read out the MSH/LSH
data stored in the data input registers of the MSH/LSH
switch halves-in an exchanged order.
The same effect can be done by separately programming each CF(X) control flip-flop of bank 1 of all the
multiplexers. The control nibbles for this can be seen in
Table 9 which are taken from Table 3, 4, and 6.
With this list of control words, the control 1/0 pins
CNTR(15-0) are used to load the CF(X) (X=15-0) control flip-flops. These are loaded into bank 1, four control
flip-flops at a time for a total of four clocks. This is
shown in Figure 4, lines 3, 4, 5, and 6. In line 7, once
the control flip-flops are set up, the MSH/LSH exchange
is made with the control source of the 16 X 4 MUX now
coming from bank 1 (CRSEL(1-0) = 00). Line 8 is
used to show how by using (CRSEL(1-0) = 11), the
read back control source is selected which shows the
contents of each data input register read out on its corresponding data 1/0 pins.
In the first case, where the pre-defined MSH/LSH EXCHANGE control source is used, Figure 4, line 1, 2
gives a programming example. In line 1, an input data
pattern is written into the LSH, MSH halves of the
switch and stored in the data input registers. This is
done by putting all OED lines high and presenting input
data to the data 1/0 pins. This is followed by clocking
LSCLK and MSCLK. In line 2, the MSH/LSH exchange
is selected by (CRSEL(1-0) = 10) and all OED lines
The CF(X) control flip-flops of bank 1 could also have
been loaded from the internal 64 bit data bus. In this
mode and from Table 3, it can be seen that the MSH
data 1/0 pins (063-033) are used as inputs to the
Table 9. Control Words for an MSH/LSH Exchange
Conlrol Flip-Flop
Nibbles
CFO
CF1
CF2
CF3
CF4
CF5
CF6
CF7
CF8
CF9
CF10
CF11
CF12
CF13
CF14
CF15
CNTR Inpuls 10
Load Flip-Flops
CNTR3-CNTRO
CNTR7-CNTR4
CNTR11-CNTR8
CNTR15-CNTR12
CN (3-D)
Binary
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
3.254
CN(3-DJ
Hex
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
Results
035-032 --'>
039-036 --'>
043-040 --'>
047-044 --'>
051-048 --'>
055-052 --'>
059-056 --'>
063-060 --'>
03-00 --'>
07-04 --'>
011-08 --'>
015-012 --'>
019-016 --'>
023-020 --'>
027-024 --'>
031-028 --'>
03-00
07-04
011-08
015-012
019-016
023-020
027-024
031-028
035-032
039-036
043-040
047-044
051-048
055-052
059-056
063-060
-) GOULD
AIMII®Semiconductors
5618840
corresponding LSH, CN(3-0) control nibble. Likewise
the LSH data 110 pins (032-00) are used as inputs
to the corresponding MSH, CN(3-0) control nibble.
These control nibbles are then loaded into either bank 1
or 2 of the CF(X) control flip-flops. The control flip-flops
are loaded from the data I/O pins in one CRCLK
cycle (all 16 nibbles). This is shown in line 9 of Figure
4. Following this, lines 10-13 read out the contents of
CF(X) bank 1 on the CNTR(15-0) lines as addressed
by CRAOR(1-0). This shows the correct control ni~ble
pattern was loaded into bank 1 from the data I/O pinS
to program an MSH/LSH exchange mode. The control
nibbles loaded from the data I/O pins may be loaded as
one 64 bit real-time input or as two 32 bit words stored
previously in the data input registers. To use the data
stored in the data input registers, the MSCLK, LSCLK
are used to load the MSH, LSH data inputs into the
. data input registers. Then SELOMS, SELOLS are used
to select these registers as the data input to the internal
data bus and as a source input to load the control flipflops. Whenever the control flip-flops are loaded from
the data inputs, all 64 bits of control data must be present when the CRCLK is used so that all control nibbles
in a program are loaded simultaneously.
Figure 4 lines 14 and 15 show the loading of the M.SH
and LSH data input registers on separate cycles. Line
16 shows the loading of the CF(X) bank 1 control flipflops in one cycle from the data input registers.
Broadcast a Nibble
In this example, any of the 16 data I/O input nibbles
can be broadcast to any of the other 15 data I/O output
nibbles. Input nibble (03-00) will be used as input in
this example, to be broadcast to all the other data I/O
pins as output. The CF(X) bank 2 control flip-flops will
be used as the control source of the 16 X 4 MUX's.
Also the control flip-flops will be loaded using the
CNTR(15-0) control I/O pins. To do this, CRSRCE is
set low to select the CNTR pins as input for the
CN(3-0) control nibble. Then the CRWRITE pin is set
high to select bank 2. Also CREAO is set high so as to
select bank 2 for reading CF(X) out on the CNTR pins.
Figure 4, lines 17-20 show the loading of CF(X) control
flip-flops bank 2 with the control nibbles necessary for
broadcasting of data I/O pins (03-00) to all other 15
data I/O nibbles. Line 21 shows (03-00) set as input
to the value ''/!\' which is broadcast to all other pins
which are set as outputs. Note that OEOO= 1, while
OE015-2=0. Also note that the previously control
nibbles set in bank 1 are still valid. The input pins
CRSEL(1-0) simply select which bank (or hard-wire
function) is to be the control source input to the 16 X
4 MUX input.
Absolute Maximum Ratings
OC Supply Voltage (Voo - Vss) ........................................... , ............... '00'6 't~' ~ ;0~6
Operating Temperature ................................................................ ~'550C to + 1500C
Storage Temperature .................................................
~ V .;; Voo + 0.3V
Oigital Input ........................................................... s s ·
IN
"':"i . ':': () 3\i
D.C. Electrical Operating Characteristics: TA = O°Cto +70°C; Voo = +5V (±10%); Vss = OV unless
otherwise specified
Symbol
VIH
VIL
VOH
VOL
Po
Parameter/Conditions
High Level Logic Input
Low Level Logic Input
High Level Logic Outputs
Minimum
Typical
2.0
Vss
2.4
IOH - .8mA
Low Level Logic Outputs IOL
Power Dissipation @ +5.5V
=
4.omA
Units
Voo
+0.8
V
Voo
+0.4
0
150
3.255
Maximum
V
V
V •
mW
1
I
- _=.
I
I
:::>~
"TI
IS'
t::
~
~Q
fa
~
"tJ
o
Ia.
Ul
iil
CNTR 1/0
N
co v
= co
C
C
C
In
,-
~I~I;:!:!I
:.:1;;:12IC1I~~;~'dll::::;91~:.:I~:.:1
~ i§
.5~~ 1:=wg~~~~~'~~
(..)
",1(.) (.) 10~~~
(.) (.) ~g~g'cl=m:g :g
3
3
Data 1/0 Pins
(Hex)
Pins (Hexl
N-
-co "'="
N
I
c.l U
....I (.) ( j
t.l (.)
C'J)::E en...J,
C
I
C
I
I
r-- M
jg jg
C
I
C
I
en an
C
I
'I"""
C
I
......
to N
C
C
c·c -.:r
a"I
in'-
I
M
I
0>
I
=
ICC
I
I
8 8 8 1::: 1:::0 0 0 ::; 8
I151413.121110 9 8 7
6 5 4 3 2· 1 0
e: e:=
I~
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
000000000000000011
3 0 0 Os
400 OS
5 0 0 Os
600 Os
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
111111111111111111
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
000000000000000011
0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 1 1
X
X
X
X
A
5
X XX
X X X
X X X
X XX
AAA
5 55
~
Ul
1 X X 1 1 X X X X X X X 1 X X XS X s 6 6 6 6 A A A A 9 9 9 9 5 5 55
2XX11XXXXXXX11 0 0 1 0 1 9 9 9 9 5 5 5 5 6 6 6 6 A AAA
00 X 4 0 C 8 1 X X X 1 X 1 X X X X X X X X X X X X
01 X 5 1 D 9 1 X X X 1 X 1 X X X X X X X X X X X X
10 X 6 2 E A 1 X X X 1 X 1 X X X X X X X X X X X X
1 1 X 73 F B 1 X X X 1 X 1 X X X X X X X X X X X X
7XX11XXXXXXX1000101 9 9 9 9 5 5 5 5 6 6 6 6
8 X X 1 1 X X X X X X X 1 1 1 0 1 0 1 6 6 6 6 A A A A 9 9 9 9
w
~
:r
OED
0
&n""l:t
GOULD
AIMII®Semiconductors
Asynchronous Communication
Interface Adapter
56551 156551 A
Features
o On·Chip Baud Rate Generator: 15 Programmable
Baud Rates Derived from a Standard 1.8432MHz
External Crystal (50 to 19,200 Baud)
o Programmabl.e Interrupt and Status Register to
Simplify Software Design
o Single + 5 Volt Power Supply
o Serial Echo Mode
.
o False Start BH Detection
o 8·Bit Bi·Directional Data Bus for Direct Communi·
cation With the Microprocessor
o External 16X Clock Input for Non·Standard Baud
Rates (Up to 125K Baud)
o Programmable: Word Lengths; Number of Stop
Bits; and Parity Bit Generation and Detection
o
o
o
o
Data Set and Modem Control Signals Provided
Parity: (Odd, Even, None, Mark, Space)
Full·Duplex or Half·Duplex Operation
5, 6, 7, 8 and 9·Bit Transmission
General Description
The S6551/S6551A is an Asynchronous Communica·
tion Adapter (ACIA) intended to provide interfacing for
the microprocessors to serial communication data
sets and modems. A unique feature is the inclusion of
an on·chip programmable baud rate generator, with a
crystal being the only external component required.
Block Diagram
Pin Configuration
TxD
GND
R/VI
CSo
t2
__
CS,
IRO
lIlQ
RIW _ _
OCD
RES
DB,
DSR
RxC
DB6
XTAL1
DBs
~2
CSo _ _
cs,--
-RSQ _ _
SelECT
AND
CONTROL
. LOGIC
RxC
RS, _ _
Rfs _ _
D80~
:
DB1~
XTALI
XTAL2
DB,
XTAL2
RTS
DB3
CTS
DB,
TxD
DB,
DATA
BUS
BUFFERS
DTR
iiTS
4.3
DTR
DB,
RxD
OSR
RSo
DCD
RS,
Vee
I
I
-} GOULD
AIMII®Semiconductors
56551/56551 A.
Absolute Maximum Ratings
Supply Voltage Vee ............................................................................................................................ - O.3V to + 7.0V
Input/Output Voltage VIN .•.••••....•.•.••....•..••..•..•.•.•.•••.••.•••..•..•...........•••......•.•.•••.••..•.••......•..•..•.......•.••.•..... - O.3V to + 7.0V
Operating Temperature Range TA .............................................................................................................. ODC to + 70 DC
StorageTemperatureRangeTstg ...................................................................................................... -55 DCto + 150 DC
All inputs contain protection circuitry to prevent damage to high static charges. eare should be exercised to prevent unnecessary appli·
cation of voltages in excess of the allowable limits.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifica·
tion is not implied.
Electrical Operating Characteristics (Vee
=5.0V ± 5%, TA =ODC to
+ 70 DC, unless otherwise noted)
Symbol
Parameter
Min.
VIH
VIL
Input High Voltage
2.0
-
Input Low Voltage
-0.3
-
Typ.
'Max.
Units
Vcc
0.8
V
V
Input Leakage Current: VIN = 0 to 5V (~2. R/W. RES.
CS o• CS 1 • RS o. RS 1 • CTS. RxO. OCO. OSR)
-
±1.0
±2.5
/lA
ITsl
Input Leakage Current for High Impedance State (Three State)
-
±2.0
±10.0
/lA
VOH
Output High Voltage: ILOAD = -100/lA (OBo-OB7. TxO.
RxC. RTS. OTR)
2.4
-
-
V
VOL
Output Low Voltage: ILOAD = 1.6mA (OB o-OB 7• Tx O.
Rx C. RTS. OTR. IRQ)
-
-
0.4
V
10H
Output High Current (Sourcing): VOH = 2.4V (OBo-OB 7•
TxO. RxC. RTS. OTR)
-
-
-100
/lA
10L
Output Low Current (Sinking): VOL = 0.4V (OB o-OB7•
TxO. RxC. RTS. OTR. IRQ)
-
-
1.6
rnA
Output Leakage Current (Off State): VOUT = 5V (IRQ).
Clock Capacitance (~2)
-
1.0
10.0
-
20
/lA
pF
pF
liN
10FF
CCLK
CIN
Input Capacitance (Except XTAL 1 and XTAL2)
-
COUT
-
-
10
Output Capacitance
10
pF
Po
Power Dissipation (See Graph) (TA = 0° C)
-
170
300
mW
Write Cycle (Vee
=5.0V ± 5%, TA =ODC to
+ 70 DC,
unless otherwise noted)
S6551
Symbol
tCYC
tc
tACW
tCAH
twcw
tCWH
tDCW
tHW
Min_
Parameter
Cycle Time
~2 Pulse Width
Address Set-Up Time
Address Hold Time
R/W Set-Up Time
R/W Hold Time
Data Bus Set-Up Time
Data Bus Hold Time
1.0
400
120
a
120
0
150
20
(Ir and If = 10 to 30ns)
4.4
Max.
-
-
-
-
Min.
0.5
200
70
0
70
a
60
20
S6551A
Max.
-
-
Unit
/ls
ns
ns
ns
ns
ns
ns
ns
-} GOULD
AIMII®Semiconductors
S6551/S6551 A
Figure 1. Power Dissipation vs. Temperature
200
175
TYPICAL
POWER
DISSIPATION
~
150
"-
(mW)
-
125
I
100
o
I
20
40
60
80
I
\o.MBIENT (OC)
Figure 2. Write Timing Characteristics
1 - - - - - - - - lcYe - - - - - - - - 1
Iwew
r-.-------- v,"
RIW
OATABUS
="""=""""===="""''''''''~ r:-r
__I_Dew_ _ _:--_I_"W_--,l1
====
_~_ _ _ _ _ _ _ _~~
V'L
'V""L
Read Cycle (Vee = 5.DV ± 5%, TA = DOG to + 7DoG, unless otherwise noted)
S655'1
Symbol
Parameter
Min.
tCYC
Cycle Time
1.0
tc
~2
400
tACR
Address Set-Up Time
tCAR
Address Hold Time
0
tWCR
R/W Set-Up Time
tCoR
Read Access Time (Valid Data)
Pulse Width
S6551A
Max.
Min.
Max.
Unit
0.5
-
f.ls
200
ns
70
-
0
-
ns
120
-
70
-
ns
-
200
-
150
ns
120
.'
ns
tHR
Read Hold Time
20
-
20
-
ns
tcoA
Bus Active Time (Invalid Data)
40
-
40
--:-
ns
4.5
-} GOULD
AIMII®Semiconductors
56551/56551 A
Figure Sa_ Interrupt and Output Timing
Figure 5. Test Load for Data Bus (OB o-OB 7 ), TxO,
OTR, RTS Outputs
Vee
\
2.4kQ
S6551 PIN
---~--;---KI---+---
)r-
OTR. RTS
--------~~-.~-"~f_~
IRQ
(CLEAR) _ _ _ _ _ _ _ _ _ _J
Figure 6b. Transmit Timing with External Clock
~
lecy
-IeH-l
XTALI
(TRANSMIT
CLOCK INPUn
T,O
\
Figure Sc. Receive External Clock Timing
)-
-l
.
1-IeL_1
1-----'1
(1:;8n
~~Di~---
.
IeCl
~'I
J-le~-J
~'IeL~f..
"-
NOTE: R,O RATE IS 1/16 RIC RATE.
NOTE: T,O RATE IS 1/16 T,C RATE.
CSO-CS1 (Chip Selects). The two chip select inputs are
normally connected to the processor address lines
either directly or through decoders. The 86551 is selected when C8a is high and ~ is low.
RSo, RS1 (Register Selects). The two register select lines
are normally connected to the processor address lines
to allow the processor to select the various 86551 internal registers. The following table indicates the internal
register select coding:
Table 1
WRITE
READ
RS
RS o
Pin Description
RES (Reset). During system initialization a low on the
RE8 input will cause internal registers to be cleared.
~2 Input Clock. The input clock is the system ~2 clock
and is used to trigger all data transfers between the
system microprocessor and the 86551.
R/W (Read/Write). The RIW is generated by the microprocessor and is used to control the direction of data
transfers. A high on the RiW pin allows the processor to
read the data supplied by the 86551. A low on the RIW
pin allows a write to the 86551.
IRQ (Interrupt Request). The IRQ pin is an interrupt signal
from the interrupt control logic. It is an open drain output, permitting several devices to be connected to the
common IRQ microprocessor input. Normally a high
level, IRQ goes low when an interrupt occurs.
0
0
0
1
1
1
0
1
Transmit Data Register
Receiver Data Register
Programmed Reset
Status Register
(Data is "Don't Care")
Command Register
Control Register
The table shows that only the Command and Control
registers are read/write. The Programmed Reset operation does not cause any data transfer, but is used to
clear the 86551 registers. The Programmed Reset is
slightly different from the Hardware Reset (RE8) and
these diferences are described in the individual register
definitions.
OBo-OB7 (Data Bus). The DBa-DB7 pins are the eight
data lines used for transfer of data between the processor and the 86551. These lines are bi-directional and
are normally high-impedance except during Read
cycles when selected.
4.6
~ GOULD
AIMII®Semiconductors
S6551 IS6551 A
Figure 3. Clock Generation
XTAL 1 6
~~~~~NAL
XTAL 1 6
OPEN
XTAL2 7
o
HAL2
CIRCUIT
6551
INTERNAL CLOCK
I
EXTERNAL CLOCK
Figure 4. Read Timing Characteristics
I
I
CSo. CS" RSo. RS,
RN
j,----+----------+------------ V,.
DATA BUS --------t--~
Transmit/Receive Characteristics
S6551
S6551A
Symbol
Parameter
Min.
tCCY
Transmit/Receive Clock Rate
400'
-
400'
-
ns
tCH
Transmit/Receive Clock High Time
175
-
175
-
ns
tCl
Transmit/Receive Low Time
175
-
175
-
ns
Max.
Min.
Max.
Unit
too
EXTAL 1 to TxD Propagation Delay
-
500
-
500
ns
tOlY
Propagation Delay (RTS, DTR)
-
500
-
500
ns
tlRa
IRQ Propagation Delay (Clear)
-
500
-
550
ns
(Ir and If = 10 to 30ns)
'The baud rate with external clocking is: Baud Rate =
1
16 x lCCY
4.7
-} GOULD
AIMII®Semiconductors
S6551/S6551 A
DSR (Data Set Ready). The D8R input pin is used to indicate to the 86551 the status of the modem. A low indicates the "ready" state and a high, "not-ready." D8R is
a high-impedance input and must not be a no-connect.
If unused, it should be driven high or low, but not
switched.
XTAL1, XTAL2 (Crystal Pins). These pins are normally
directly connected to the external crystal (1.8432MHz
M-Tron MP-2 recommended) used to derive the various
baud rates. Alternatively, an externally generated clock
may be used to drive the XTAL 1 pin, in which case the
XTAL2 pin must float.
TxD (Transmit Data). The TxD output line is used to
transfer serial NRZ (non-return-to-zero) data to the
modem. The L8B (least significant bit) of the Transmit
Data Register is the first data bit transmitted and the
rate of data transmission is determined by the baud
rate selected.
RxD (Receive Data). The RxD input line is used to
transfer serial NRZ data into the ACIA from the
modem, L8B first. The receiver data rate is either the
,programmed baud rate or the rate of an externally
generated receiver clock. This selection is made by
programming the Control Register.
RxC (Receive Clock). The RxC is a bi-directional pin
which serves as either the receiver 16xclock input or
the receiver 16xclock output. The latter mode results if
the internal baud rate generator is selected for receiver
data clocking.
RTS (Request to Send). The RT8 output pin is used to
control the modem from the processor. The state of
the RT8 pin is determined by the contents of the Command Register.
CTS (Clear to Send). The CT8 input pin is used to control the transmitter operation. The enable state is with
CT8 low. The transmitter is automatically disabled if
CT8 is high.
DTR (Data Terminal Ready). This output pin is used to
indicate the status of the 86551 to the modem. A Iowan
DTR indicates the 86551 is enabled and a high indicates it is disabled. The processor controls this pin via
bit 0 of the Command Register.
Figure 8. Control Register Format
STUP BITS
6
5
I
I
, STOP BIT IF WORD LENGTH
.. 8 BITS AND PAflrTY'
Hi STOP BITS IF WORD LENGTH
'" 5 BITS AND NO PARITY
WORD lENGTH
0
0
0
1
1
0
1
1
DATA WORD
LENGTH
,
Note: If Command Register Bit 0 ='1 and a change of state on DCD
occurs, IRQ will be set, and Status Register Bit 5 will reflect the
new level. The state of iJCiJdoes not affect Transmitter operation,
but must be low for the Receiver to operate.
Figure 7. Transmitter/Receiver Clock Circuits
I
RIC
4
I ~ 16)
BW'~I:r~~..
XTAL 1
D
XTAL2
BAUD
I GE:E~~\oR
3
2
1
II
0
I
BAUD RATE
GENERATOR
o
0
o
o
0
0
0
,
0
o
0
1
1
tI
1
0
0
o
o
1
0
1
1
1
0
3DO
1
'DO
1200
0
0
1
lh.EXTERMAlClOCK
"
"
,"
109.92
134.58
1
1
0
0
0
,
0
0
1
1
0
1
0
2400
5
1
0
1
1
1
laoo
,
0
0
1·'
0
1
1
1
1
0
3600
4800
nOD
9800
1
1
1
1
19.200
"THIS AllOWS FOR 9·BIT TRANSMISSION (8 DATA BLTS PLUS PARITY).
4.8
RID
SYNC
LOGIC
y
r
L'LOCK
~I!I~~~
,II, II ,
BITS 0·3 IN
CONTROL
REGISTER
1
I
~
CONTROL
o
EXTERNAL RECEIVER CLOCK
1 '" BAUD RATE GENERATOR
RECEIVER
HIFTREGISTER
-~---;--t ~~?~E~
1
7
RECEIVER CLOCK SOURCE
o ""
DCD (Data Carrier Detect). The DCD input pin is used to
indicate to the 86551 the status of the carrier-detect
output of the modem. A low indicates that the modem
carrier signal is present and a high, that it is not. DCD,
like D8R, is a high-impedance input and must not be a
no-connect.
CONTROL REGISTER
7
o "" 1 STOP BIT
1 "" 2 STOP BITS
~
Note: If Command Register Bit 0 = 1 and a change of state on DSR
occurs, IRQ will be set, and Status Register Bit 6 will reflect the
new level. The state of DSR does not affect either Transmitter or
Receiver operation.
BAUD
I
TRANSMmER
SHIFT REGISTER
(----TID
GOULD
AIMII®Semiconductors
56551/56551 A
Internal Organization
Control Register
The Control Register is used to select the desired
mode for the 86551. The word length, number of stop
bits, and clock controls are all determined by the Control Register, which is depicted in Figure 8.
The Transmitter/Receiver sections of the S6551 are
depicted by the block diagram in Figure 7.
Bits 0-3 of the Control Register select the divisor used
to generate the baud rate for the Transmitter. If the
Receiver clock is to use the same baud rate as the
Transmitter, then RxC becomes an output pin and can
be used to slave other circuits to the 86551.
Figure 9. Command Register Format
Command Register
The Command Register is used to control 8pecific
Transmit/Receive functions and is shown in Figure 9.
COMMAND REGISTER
, , •,
I I L.!..i
2
7
PARITY CHECK CONTROLS
0
0
0
1
0
DATA TERMINAL READY
OPERATION
7-T5
- -
1
o=
I
PAfllTY DISABLED
NO PARITY BIT
NO PARITY BIT RECEIVED
GENERATED
1
=
DISABLE RECEIVER AND ALL
INTERRUPTS (lITH HIGH)
ENABLE RECEIVER AND ALL
INTERRUPTS (orn lOW)
ODD PARITY RECEIVER AND TRANSMITTER
RECEIVER INTERRUPT ENABLE
0
1
1
EVEN PARITY RECEIVER AND
TRANSMITTER
o=
1
0
1
MARK PARITY BIT TRANSMITIED,
1 =
1
1
1
iim INTERRUPT ENABLED FROM BIT 3
OF STATUS REGISTER
iRa INTERRUPT DISABLED
PARITY CHECK DlSABUD
TRA.NSMmER CONTROLS
SPACE PARITY BIT TRANSMITTED,
3,
BIT
PARITY CHECK DISABLED
0
0
1
1
NDRMAUECHO MODE
FOR RECEIVER
o = NORMAL
1 = ECHO (SITS 2 AND 3
MUST BE "D")
0
1
0
1
TRANSMIT
INTERRUPT
LEVEL
Rrr
TRAHSMmEII
DISABLED
HIGH
OFF
ENABLED
LOW
DISABLED
LOW
011
DISABLED
LOW
TRANSMIT BRK
ON
, • ,
:::~:AA;::::~T I I~ I I: I: I: I: I~ I
I
7
5
D
0
2
1
0
Status Register
Figure 1O. Status Register Format
The Status Register is used to indicate to the processor the status of various 86551 functions and is
outlined in Figure 10.
L:=~--+-::-:-::-+--~
Transmit and Receive Data Registers
These registers are used as temporary data storage for
the 86551 Transmit and Receive circuits. The Transmit
Data Register is characterized as follows:
OBit 0 is the leading bit to be transmitted.
o Unused data bits are the high-order bits and are
"don't care" for transmission.
The Receive Data Register is characterized in a similar
fashion:
OBit 0 is the leading bit received.
o Unused data bits are the high-order bits and are "0"
for the receiver.
o Parity bits are not contained in the Receive Data
Register, but are stripped-off after being used for
external parity checking. Parity and all unused highorder bits are "0".
W~~E lRA"S"'OATARtGlSTtR
NOIRUEnAS,t
RE1~tl'iitii
STUt
'NOIIITtRRUPTGt~ERATtOFo. TJT••"
I :D"
. . . .0,,"0
_______________~_lt_'RQ~D)_
Figure Sb. Transmit Timing with External Clock
1----tEcP-----j
XTAL1
(TRANSMIT
CLOCK INPUT)
TESTPOINT~
I
)r-
~--J~
TxO
NOTE: TxD RATE IS 1/16 TxC RATE.
Figure Sc. Receive External Clock Timing
The S65C51 Asynchronous Communications Interface
Adapter provides processor (IlP) based systems with a full
duplex serial interface. The IlP port is directly compatible
with 6800/6500 style bus architectures. Coupled with the
Status Register, a powerful and flexible interrupt facility is
included on the S65C51 to allow fast response from the IlP
to the ACIA.
RxC
(INPUT)
-------.1.\' .
_'F-'~ d~
Y
l~tECL~1
NOTE: RxD RATE IS 1/16 RxC RATE.
The serial port provides signals which may be used to control a communication channel compatible to the EIA Standard RS-232 specification. An on-board baud rate
generator allows 16 different baud rates, for data transmission and reception timing. All frequencies are derived from
an external clock or crystal. The receive frequency may be
received separately from the transmit frequency, allowing
reception and transmission at independent speeds. Alternatively, the ACIA
produce a signal that is 16 times the
baud rate, for use by a remote ACIA (Table 1 - RxC).
also be forced high or low. Either 1,1.5, or 2 stop bits may
be added to the end of the serial data stream. For maintenance applications, the received data stream may be
looped back onto the transmit data stream using echo
mode operation.
will
SERIAL INTERFACE DESCRIPTION
Transmitted and Received Data
Data is transmitted from the ACIA on the TxD pin, and
received on the RxD pin. The inactive state of either data
channel (RxD or TxD) is a mark condition (logical high).
The format of the data word is programmable. The word
length ranges from 5 to 9 bits (including parity). Parity can
be odd, even or deselected altogether. The parity bit may
4.15
I
I
I
I
30Pf
FUNCTIONAL DESCRIPTION
I
-} GOULD
AIMII®Semiconductors
S65C51
Table 1. Pin Description
Pin
Name
1
2,3
Vss
CSO, CS1
4
RES
5
RxC
6
XTAL1
7
XTALO
8
RTS
9
CTS
Clear to send. Input signal from the modem to the ACIA to control data transfers. When this
input is held high, the transmitter is disabled.
10
TxD
11
DTR
12
13, 14
RxD
RSO, RS1
15
16
Voo
DCD
Transmit Data. Serial data output in NRZ (Non Return to Zero) format.
Data Terminal Ready. Output to the modem to indicate the ACIA status. DTR=1 if ACIA is
disabled (See COMMAND REGISTER table 3).
Receive Data. Serial data input NRZ (Non Return to Zero) format.
Register Select Inputs. The state of these pins determines which internal register is connected
to the data bus when the device is selected (see chip select description and Register Decode
Table).
Positive Supply Input. +5V.
17
DSR
Data Set Ready Input. DSR =0 if the modem is ready to perform a data transfer. The state of
this pin is reflected by SRb6. If interrupts are enabled (CRbO=;,1), and the logical state of DSR is
changed, an interrupt will occur. When not used, this input should be connected to ground or
to a logic high. The input state does not affect the transmitter or the receiver function.
18-25
00-07
26
IRQ
Microprocessor Data Bus. Bidirectional data bus which is TIL compatible. When the device is
not selected these pins enter a high impedance state.
Interrupt request to. MPU. (open drain output). When an interrupt occurs, this output is forced
low until the interrupt is serviced (by reading the Status Register).
27
02
RIW
28
Description
Ground Input. OV.
Chip Select. TIL inputs CSO=1 & CST=O select the chip for data transfer on the
microprocessor bus. The direction of the transfer is determined by the state of the
R!W pin.
Hardware Reset. RES=Oto reset the chip. All internal registers will be cleared except bits 4,
5 and 6 in the Status Register (SRb4, SRb5 and SRb6). SRb4 is set, and SRb5 and SRb6 are
unaffected.
Receive Clock. This is a bidirectional pin which serves as either the receiver 16x clock input
or the receiver clock 16x output. The latter mode is selected if the internal baud rate generator
is used as the receiver clock source.
Clock Input. For External Clock or Crystal connection. If clock is stopped, this input rnust be
held high. XTAL1 has CMOS cornpatible thresholds (See figure 4).
Clock connection. This pin must be connected to the side of a crystal opposite to XTAL1, or
left floating when using an external clock (See figure 4) .
. Request to Sent. Output signal to the modem from the ACIA to control data transfers (See
COMMAND REGISTER table 3).
Data Carrier Detect Input. Status of carrier at the modem. [DCD=O if the. carrier is detected].
The state of this pin is reflected by bit 5 of the Status ~ter (SR). If interrupts are enabled
(Command Register (CRY bit 0=1) and the logical state DCD is changed, an interrupt will occur.
When not used, this input should be connected to ground or to a logic high. The input state
does not affect transmitter function but a logical low must be present for the receiver to
operate.
System clock input. This synchronizes data transfer with the microprocessor.
Read/Write Input. Controls the direction of data transfer between the microprocessor and the
ACIA.
4.16
GOULD
AIMII®Semiconductors
S65C51
This type of data code is termed Non-Return to Zero (NRZ).
Data transmitted or received by the S65C51 is always
preceded by a "start bit." The Transmitter/Receiver sections of the S65C51 are depicted in Fig. 6.
bit (MSB) last. The MSB depends on the number of bits
per word selected; the ACIA can be programmed for 5 bit,
6 bit, 7 bit or 8 bit data word transmission/reception, Each
bit has a period equal to the reciprocal of the selected baud
rate, which in turn is dependent on the clock source frequency (see table 4).
The start bit is. a space condition (logical low) which signifies the start of active data on the channel. The receiving
ACIA also uses the start bit to optimize its sampling for the
middle of the data bits that follow. Between received words,
the ACIA samples the channel at 16x Baud rate. When a
low is detected, the ACIA waits half a bit period before sampling again. This delay allows subsequent bits (sampled
at the same frequency as the baud rate) to be sampled as
far from the bit boundaries as possible. Noise or "glitch"
immunity is also added by this mechanism. Low going
pulses of less than 1/2 a bit period wide will not be mistaken for the start bit (the ACIA resumes the 16x sampling
rate).
Parity sensing and generation can be chosen for odd parity, even parity or no parity, When parity is selected, the
parity bit follows the MSB of the data word. For even parity, the condition of the parity bit will be such that there are
an even number of marks when considering the data word
Figure 6. Transmitter/Receiver Clock Circuits
I--~-R'O
Data bits following the start bit are in ascending order, with
the least significant bit (LSB) first, and the most significant
R~
RSo
0
0
Transmit Data Register
0
1
Programmed Reset
(Dala is "Don't Care")
1
0
1
1
I
R,C - - - - - . , - j
XTAL1
Table 2. Register Address Decoding
WRITE
o
READ
XTAL2
Receiver Data Register
Status Register
I----T'O
Command Register
Control Register
Table 3. Command Register Description
7
6
5
I J
PARITY CHECK CONTRDLS
BIT
6
COMMAND REGISTER
7
4
3
0
0
1
0
1
1
PARITY DISABLED
GENERATED
I
DATA TERMINAL READY
~
NO PARITY BIT
NO PARITY BIT RECEIVED
ODD PARITY RECEIVER AND TRANSMITIER
EVEN PARITY RECEIVER AND
o
0
1
MARK PARITY BIT TRANSMITTED,
PARITY CHECK DISABLED
1
1
1
SPACE PARITY BIT TRANSMITTED,
PARITY CHECK DISABLED
o ""
DISABLE RECEIVER AND ALL
INTERRUPTS (llfiflliGII)
1 ::::: ENABLE RECEIVER AND ALL
INTERRUPTS (IITRLoW)
RECEIVER INTERRUPT ENABLE
molMTERRUPT ENABLED FROM BIT 3
OF STATUS REGISTER
1 ~ m1!lIITERRUP7 DISABLED
TRANSMmER
1
=
TRAHSMITIER CONTROLS
r,-B;-
NDRMAUECHO MODE
FOR RECEIVER
=
a
5
0
o=
1
OPERATION
- -
1
2
.l-'-
NORMAL
ECHO (BITS 2 AND 3
MUST BE "0')
I
TRANSMIT
INTERRUPT
RTS
LEVEL
TRANSMITTER
0
0
DISABLED
HIGH
OFF
0
1
ENABLED
LOW
ON
1
1
0
DISABLED
LOW
ON
1
DISABLED
LOW
TRANSMITBRK
HARDWARE RESET
PROGRAM RESET
4.17
I
7
6
5
4
3
2
1
0
0
-
0
-
0
-
0
0
0
0
0
0
0
0
0
0
II I I I I I I I
-} GOULD
AIMII®Semiconductors
S65C51
and the parity bit. With odd parity, the condition of the parity bit will be. such that there is an odd number of marks
when considering the data word and the parity bit (both
cases exclude the start and stop bits).
Control Signals
These signals are compatible with the RS-232C modem
control circuits. The signals are the Request To Send
(RTS) , Data Terminal Ready (DTR) outputs and the Clear
To Send (CTS), Data Set Ready (DSR) and the Data
Carrier Detect (DC D) inputs. Note that the ACIA is viewed
as the Data Termination Equipment (OTE) as opposed to
the Data Communication Equipment (DCE) when referencing the RS-232C specification.
Transmit and Receive Clocks
The signals used by the ACIA for transmit/receive timing
are found on 3 pins: XTALO, XTAL1 and RxC. XTAL1 and
XTALO are the input and output, respectively, of a crystal
oscillator circuit. The crystal can be connected to these
pins as seen in figure 7. This oscillator circuit drives the
internal baud rate generator, which divides the square
wave output of the oscillator by the divisor selected (see
table 4). If a crystal is not used, an external clock may drive
the oscillator input while the oscillator output is left floating. If the clock is stopped (device still powered), the oscillator input should be held to a logical high.
Request To Send. RTS is used to indicate to the DCE
that it should assume the data channel transmit mode. The
state of this output is controlled by bits 2 and 3 of the Command Register (COMRb2 and COMRb3, see table 3).
When it is high (not asserted, or in other words,!'negated")
the ACIA's transmitter is disabled.
Data Terminal Ready. The DTR signal indicates to the
DCE that the ACIA is ready for communication. This output is asserted when COMRbO is set.
The clock for the receiver may be taken from 1 of 2
sources: the output of the internal baud rate generator, or
from an external clock input on the RxC pin. In the latter
case, the baud rate is 1I16th of the external clock. If the
source of receiver timing is the internal baud rate generator, RxC becomes an output and sources a clock 16 times
(16x) the baud rate (for driving remote ACIAs).
Clear To Send. The CTS signal from the DCE tells the
ACIA that the DCE is prepared to accept data to pass on
to the remote end of the communication channel. When
this signal is not asserted, the transmitter of the ACIA is
disabled. If the ACIA is in the middle of transmitting a data
Table 4. Control Register Description
CONTROL REGISTER
17
STOP BITS
o1 -
1 6 1 5 141 3 1211
I I
1 STOP BIT
2 STOP BITS
1 STOP BIT IF WORD LENGTH
.. 8 BITS AND PARITY 0
1Y, STOP BITS IF WORO LENGTH
- 5 BITS ANO NO PARITY
WORD LENGTH
~
6
5
DATA WORO
LENGTH
0
0
8
0
1
7
1
0
6
1
1
5
RECEIVER CLOCK SOURCE
o1 -
EXTERNAL RECEIVER CLOCK
BAUO RATE GENERATOR
I
rI
o1
BAUD RATE
GENERATOR
I I
16, EXTERNAL CLOCK
0
0
0
0
0
0
0
1
50
0
0
1
0
75
0
0
1
1
109.92
0
1
0
0
134.58
0
1
0
1
150
0
0
1
1
0
300
1
1
1
600
1
0
0
0
1200
1
0
0
1
1800
1
0
1
0
2400
1
0
1
1
3600
1
1
0
0
4800
1
1
0
1
7200
1
1
1
0
9600
1
1
1
1
19,200
°THIS ALLOWS FOR 9·BIT TRANSMISSION (8 OATA BITS PLUS PARITY).
BAU~
76543210
HAROWARE RESET
PROGRAM RESET
4.18
I I I I I I I I I
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
~ GOULD
AIMII®Semiconductors
S65C51
Table 6. Crystal Specification
Table 5. Status Register Description
STATUSnEGISTER
7
8
5
4
,
L
ClEA~ED
Characteristics
BY
Temperature stability
~IL -_ _ _ _-I--_'_'_"_'"'_"'-+_"_lf_ce'_"'_".-4.
, "URDR
FRA"'I~G ERAOA'
~ ~ ~~R~~ROR
=
o NO ERROB
1 = URC.R
RU-D RECEIVE
REGISTERFUtL
DATA REGISTER
TRANSMIT DATA
REGISTER EMPTY
0= OCDLDW
1 " fiCiiH1G.1I
a
1
'"
= iiSiiLOW
= iiSii HIGH
/I" NO INTERRUPT
1
INTERRUPT
=
Spec.
-45 to +85°C
Frequency" (MHz)
SElf CLEARING"
RfCElVEIIAT"
@
±0.01%
1.8432
Frequency tolerance" (±%)
0.02
Resonance mode"
parallel
Equivalent resistance" (ohms)
400 max.
Drive level" (mW)
2
Shunt capacitance" (pF)
7 max.
Load capacitance" (pF)
16.5 typo
Oscillation mode"
HOTAESETT.e.SlE
REFlECTSDCD
STATE
• characteristics at 25°C ±2'C
NOTRESHTA8LE
RUtECTSCSR
STATE
Figure 7. Suggested Crystal Connection
STATUS REGISTER
'IIDIHTEIlRIlPTGEHERAT£DFOIlIHUECONDlTIIlNS.
"CLEARED AUTOMATICAllY AFTER A II[AOOF ADR AND
S65C51
THE HEXTERIIOR FREE RECEIPT OF DATA.
33 pF
xmu
~----~----~
o
word when CTS is negated, the TxD channel goes
immediately to a mark condition. The data .word being
transmitted at the time is lost, but the character (if any) in
the Transmit Data Register. (TDR) is not (see register
description). As soon as CTS is asserted, this data word
will be transmitted, if the transmitter is still enabled internally (see figure 11).
Data Set Ready. The DSR signal from the DCE tells the
ACIA that the DCE is ready to operate. A transition on this
pin can cause an interrupt (if interrupts are enabled) and
the state of the pin is reflected in the state of SRb6. Transitions that follow will not affect the status bit until after the
JLP has serviced the first interrupt (read the SR). At that
point the SR will again reflect the current level of the DSR
input, and an interrupt will occur again if it has changed.
Transmitter and receiver operation is not affected by the
level of this pin.
Data Carrier Detect; The DCD signal from the DCE indicates to the ACIA that the received signal is within specified limits. When DCD is not true, the receiver of the ACIA
will be disabled and the data being shifted in at that
moment is lost. A transition on this pin, like the DSR input,
causes an interrupt. Subsequent transitions will not affect
XTALO I-----......L.--------l
7
33 pF
the status bit until the first interrupt is serviced. If the pin
has changed since the first occurred and before it was
serviced, another interrupt will occur. An even number of
level changes on DSR and DCD, before the first interrupt
has been serviced, will not cause another interrupt. This
is because the status bits will be at the same logic level that
caused the original interrupt.
REGISTER DESCRIPTION
The S65C51 contains 7 registers, 5 that are visible to the
JLP. These registers are: the Transmit Shift Register (TSR,
not available to JLP), the Receive Shift Register (RSR, not
available to JLP), the Transmit Data Register (TDR), the
Receive Data Register (RDR), the Status Register (SR), the
Command Register (COMR), and the Control Register
(CR). One of the 5 latter registers is visible to the JLP
4.19
I
I
-) GOULD
AIMII®Semiconductors
S65C51
the ItP when the chip selects (CSO, SC1) are asserted and
the E clock is true (high); the register chosen by the state
of the register selects (RSO, RS1). The direction of ItP bus
transfer is determined by the state of the RiW signal (a
high indicates a read of the contents of the register, a low
a write to a register). When the SR is written to (the data
written doesn't matter) a software reset will occur. For a
comparison between the effect of a hardware reset and a
software reset, see table 2.
If transmit interrupts are enabled, when the TDR is empty
an interrupt will occur and SRb4 will be set (SRb4 will be
set even if interrupts are disabled). This coincides with the
beginning of the start bit for the data just transferred to the
TSR. The interrupt must be serviced to be removed (by
reading SR), but SRb4 may only be cleared by a write to
the TDR. If the interrupt is serviced but TOR is not written
to, another interrupt will occur at the next word boundary
(word boundaries are referenced to the start of the last
transmitted word, and occur every full word period after the
end of the word. This timing is reset by a new transmission
because, if TxD is idle the new word is transmitted immediately - see figures 8 & 10).
Transmit Data Register
The Transmit Data Register (TDR), in conjunction with the
Transmit Shift Register, is used to place data on the transmit channel (TxD). If no word is being transmitted, a data
word written to the TDR is immediately transferred into the
TSR to be shifted out. A start bit precedes the data on the
TxD channel; parity is added to the end of the word as
needed (after the valid MSB is shifted out); and 1, 1.5, or
2 stop bits follow to end the transmitted information. If the
ACIA is programmed to send a data word that is less than
8 bits in length (5, 6 or 7 bits), the extra bits in the data word
are ignored.
Receive Data Register
Data on the receive channel (RxD) is stripped of the overhead bits (start, parity and stop) by the ACIA and shifted
into the Receive Shift Register (RSR). When a full data
word has been received (depending on the programmed
length), the contents of the RSR are transferred into the
Receive Data Register (RDR). If receive interrupts are enabled, this transfer will cause an interrupt to occur and
SRb3 to be set (SRb3 is set even when interrupts are disabled). The interrupt actually occurs about 9/16 through the
last stop bit. As with the TDR, the interrupt is removed by
reading SR and SRb3 is cleared by reading the RDA.
While the TSR is occupied shifting out active data onto TxD
(including the bit periods for the transmission of parity bits
and stop bits), information written to TDR will be latched
and held. When the last stop bit of the previous word is finished, the ACIA will transfer the data word in the TDR into
the TSR and transmit it. If the TOR is written to more than
once while information is being transmitted on TxD, the
data word in TDR will be overwritten and retain the data
associated with the last write.
If DCD is not asserted, the RSR is immediately disabled
and any word being received at the time is lost. If the
receive circuitry is disabled through the Command Register, a data word in the process of being received will be
finished before the RSR is disabled.
Figure 8. Contiuous Data Transmit
CHAR (n)
TxO
CHAR (n+ 1)
CHAR (n+2)
CHAR (n+3)
CHAR (n+4)
11-_---+-+0--------·1----------;·~I·-----+-+------1·1
r-t ....... T-r-fl-{. -t·· ...... r-T-ru-' . · .... ,.-r-ru-' ........ ,.-r-ru-'........ ,..-r-.rL
lJ
, ........
I
r
LS~
rip
~S~-
:,
r
I
I
r
I
:I START
I
lL-'-"----'
~PINTERRUPT
~
(TOR EMPTY)
I
_J ........ L_L! I
~p
I
•
I
_J.. ..... L_l._
I
I
I
I
I
_J.. ...... L._L_
"
I
I
_J ........ L_L
STOP :
I
L
I
~
READS SR_
AND CLEA!lS IRa
I
NEW OATA MUST BE LOAOED INTO THE TDR DURING
THIS TIME INTERVAL, OR A MARK WILL BE TRANSMITTED
4.20
-) GOULD
AIMII®Semiconductors
S65C51
When a continuous break character is received, the first
character period will look like a data word of all zeroes and
a framing error. If interrupts are enabled, an interrupt will
occur. Thereafter the receiver will be disabled until a stop
bit is received, so no more interrupts will occur. It is possible that the /-IP could interpret a data word made up of
zeroes, without a stop bit in the correct position, as a
received break condition (see figure 9 and 15).
COMRb2 and COMRb3 control the transmit circuitry, disabling or enabling the transmitter and RTS, and disabling
or enabling transmit interrupts. If continuous break mode
is selected during the transmission of a data word, the current word will be transmitted and the break condition will
begin immediately after. Transmit interrupts are automatically disabled during the transmit break condition.
The break condition will last for at least one character
period, so if the transmitter is enabled immediately after
the break condition has been set (assuming the ACIA has
begun to transmit the break) the transmitter will not return
to normal operation until after one character period of
break. When the break mode is removed, one stop bit will
be placed on TxD before the transmission of the next word.
Command Register
The Command Register (COMR) determines the type of
parity used in the transmitted word, and the type of parity
checked for in the received word. Parity is controlled by
COMbS - COMb7 (see table 3). The bit position normally
occupied by a parity bit may be forced to a mark or a space
.
if required.
COMRb 1 enables or disables receiver interrupts and
COMRbO enables or disables the receiver circuitry, all
interrupts and the DTR signal. See figure 4b.
COMRb4 enables or disables echo mode (for echo to be
enabled, COMb2 and COMb3must both be O).When in
echo mode, the ACIA's receive circuitry is still operational,
but data written to the TDR will not be transmitted until
echo mode is disabled and the transmitter is reenabled.
RTS is asserted in echo mode, even though it is not programmed to be active by COMRb3 and COMRb2.
Control Register
The Control Register (CR) determines the number of stop
bits in transmitted and received information; the length of
the word; the source of the receive and transmit timing and
the divisor used by the baud rate generator.
When data is received on RxD (the receiver must be enabled internally and DCD true) it is transmitted 1/2 bit period
after it has been received. Interrupts occur just as they
would when initiated by any received data (if interrupts are
enabled). If echo mode is disabled during reception of a
character, transmission on TxD stops immediately and RTS
is negated. The word continues to be shifted into the RSR
if it is still enabled (see figures 13 and 14).
Note that when the receiver clock source is chosen such
that RxC is an input, the setting of the baud rate generator has no effect on the receiver speed. See table 4.
Status Register
The Status Register (SR) performs a. "housekeeping"
function for the ACIA. The SR contains several error bits,
Figure 9. Contiuous Data Receive
CHAR (n)
CHAR
(n+1)
CHAR
CHAR
(n+2)
CHAR
(n+3)
(n+4)
---,1-·---·1-,-'-----1----_.jl_4---·1
11-1"
·····r-rpn \.,-1' ······;-r- ru-r'o "T-r-ru-r'"
······r-r-Q
~s~· . ···~si-J :\_J.. ..... L_.L_~
_L. ....
L-l_!
1_.
RxD
"T-T-ru-~
L_L
START
I
/-IP INTERRUPT (RDR FULL) OCCUR~
9/16 INTO LAST STOP BIT. PARITY,
OVERRUN AND FRAMING ERROR UPDATED
I
_L ....
_l... .... L_L
STOP ;
1
,
I I
1---1
'----,--.y-----
NEW DATA MUST BE READ FROM THE RDR DURING
THIS TIME INTERVAL, DR AN OVERRUN WILL OCCUR
r
,.,p reads SR _
AND CLEARS IRQ
4.21
L
I
I
I
-) GOULD
AIMII®Semiconductors
S65C51
2 bits to display the state of the transmit and receive
registers, 2 bits used for modem status and 1 bit for displaying interrupt status.
word received in the RSR as normal (see figure 12). When
an overrun occurs in echo mode, the TxD channel goes to
a mark until the first start bit after the RDR is read by
the ",P.
SRb 7 is the inverse of the IRQ signal. When an interrupt
is active, SRb7 is set. It is cleared by reading the SR.
SRbS and SRb6 reflect the state of the DCD pin and the
DSR pin respectively. These bits cannot be reset or cleared
Suggested sequence fQr reading SR after interrupt
Read Status Register.
This operation automatically clears SRb7 and negates
the IRQ signal. Subsequent transitions on DSR and
DCD will cause another interrupt. .
2 Check SRb7
If not set, source was not the ACIA.
3 Check SRb6 and SRb5
These must be compared to their previouslevels, which
must be stored externally by the processor. If they are
both a logical low (modem on-line) and they are
unchanged then the remaining bits must be checked.
4 Check SRb3
Is RDR full?
SCheck SRbO, SRb1, SRb2
Only if RDR is set.
6 Check SRb4
Is TDR empty? Check even if RDR is full when in full
duplex operation.
7 If none of the above occurred, CTS must have been
negated.
by the ",P.
SRb3 is the Receive Data Register full bit and SRb4 is the
Transmit Data Register Empty bit. These bits have been
described fully in the TDR and RDR sections.
The 3 LSB bits in the SR are error bits, set when a specific
error condition occurs. These bits may only be cleared if
the RDRis read and a word is received without an error
(the error that occurred previously). SRbO is the parity error
detect bit. When this bit is set, it indicates that parity is enabled and the level of the parity bit received by the ACIA was
incorrect. SRb 1 is the Framing error detect bit. If a word
is received that does not have a stop bit where expected,
the framing error bit will be set.
SRb2 is the Overrun error bit. This bit is set if a data word
is received without the previous word having been read.
The word in theRDR is maintained until it is read, so subsequent words in the RSR, that result in an overrun condition, are lost. Interrupts continue to occur with each data
Figure 10. TOR not loaded by Processor
CHAR (n)
CHAR (n+1)
CHAR (n+2)
CONTINUOUS MARK
I--I~---·1-·---·1------·1-
TxD
1J -l ........
I
I
I
L,l_/,
I
I
I
I
1 CHARACTER
PERIOD
I
--.J ht I
I'P READS SR_
AND CLEARS IRQ
I
I
I
_J . ......1-L_
I
I
START
STOP I ....-----~.,i
r---.-~'
I
I
I'P INTERRUPT
(TOR EMPTY)
·1
Iru-l' ...... r-r' Jljr-l
r-r-~-' ......... r-rI P
I
I
I'
Ls~""""~si_J.. ......
I
I
I
_J
:
I
~/nL-....J..I----'
I
NEW DATA NOT LOADED
BEFORE NEXT INTERRUPT
BUT INTERRUPTS CONTINUE
AT CHARACTER RATE
4.22
'"
WHEN MICRO FINALLY LOADS NEW DATA
TRANSMISSION STARTS IMMEDIATELY AND
INTERRUPT OCCURS, INDICATING TOR EMPTY
-} GOULD
AIMII®Semiconductors
S65C51
Figure 11. Effect of
crs on TxD
CHAR (n)
TxD
CHAR (n+ 1)
CHAR (n+2)
CHAR (n+3)
I. . . -----·1 ...·----.j-I. / LOST
rr-----------1
lJ -!········~-fp~' -~······rr-n
L_LJ/UJ
1 CHARACTER
: LSB
MSB
:
:
:
PERIOD
l
_J.. ...... L.J._
l
,
_J ........
: START
STOP
I
I
,
i-' I==;===:,--,
-1.---"
i-;=;
1'1,--'--L..----'
I
CTS GOES HIGH INDICATING
MODEM IS NOT READY TO
RECEIVE DATA. TxD IMMEDIATELY
GOES TO A MARK CONDITION
I
L
NEXT INTERRUPT
OCCURS AT NORMAL
TIME
WHEN SR IS READ
TOR IS NOT EMPTY.
SO CTS HIGH MUST
BE DEDUCTED
CTS LOW INITIATES THE
TRANSMISSION OF THE
WORD IN THE TDR
CHAR (n+2)
CHAR (n+3)
CHAR (n+4)
Figure 12. Effect of overrun on receiver
CHAR (n)
CHAR (n+1)
1-'---·11"----_·r-I·o-----__·I_·----1'-'---·1
RxD
,
p.P INTERRUPT
(RDR FULL)
I
J ITI
p.P READS SR_
AND CLEARS IRQ
\
\
NEW DATA HAS
NOT BEEN READ
FROM THE RDR
4.23
L
RDR NOT UPDATED BECAUSE p.P DID NOT READ
PREVIOUS DATA, OVERRUN BIT SET IN STATUS
I
\
-) GOULD
AIMII®Semiconductors
S65C51
Figure 13. Effect of CTS on Echo mode operation
CHAR (n)
RxD
CHAR (n+ 1)
CHAR (n+2)
CHAR (n+3)
rI
I
L._i_
: START
STOP
I
TxD
CHAR In+4)
1-'---·1-·----1--·---'11--·
----1--'
----I
-r-ru
·r -r-ru--r········,.-T-!l
·····T-rpn \.!-r' · . ·r-T-n ;-i'
1Jr-r
Ls~""'~si-J :\_J.. . L_L_11: LLJ.[
I
I
I
I
.... r-T-n f
:,\_J.. .... ~_Lj! U~
START
STOP
!
lJr-~ ...... ·T-Tpn~f-r·
Lst . ··~s~ -,
r -, ···· ..
I
I
I
I
_J ....... L .. .1_
I
I
I
I
_J ........ L_L ..
I
I
I
I
I
I
'
r
:
I
!
,
RECEIVER INTERRUPTS CONTINUE
AS NORMAL AS BEFORE
r-----------------------------CTS NEGATEO;TRANSMITTER DISABLED
Figure 14. Overrun in Echo mode
CHAR In)
CHAR (n+1)
1--·----1-·--_.I·
CHAR (n+2)
CHAR 1n+3)
_1 ...__C_H_AR_In_+_41_
-1-·- - - - -
-I
RxO
TxO
RDR NOT READ BEFORE THIS POINT, TxO IS DISABLED ANO OVERRUN
OCCURS. INTERRUPTS CONTINUE AT PREVIOUS RATE AS NEW WORDS
SHIFTEOIN. WHEN I'P READS RDR, TxD WILL BE ENABLED AGAIN
4.24
GOULD
AIMII®Semiconductors
S65C51
Figure 15. Effect of DCD on receiver
CDNTINOUS MARK
RxD
11-r ···· . r-rpn \.f-r· .... ·-r-y-n
1
lSB' ...... L l _ . : ' \ _ L ...... L_1-J
MSB
',: START
,
t Li_J.......
STOP ',:
'
~~~
i-r·· .... ·l
r-,. .... ··-r-'-n
U_J
....... LLJ , L
I-I
MODEM DELAY
I-I
MODEM DELAY
:
L
~~==~----~I
INTERRUPT CAUSED BY DCD GOING
HIG~
I
I
/
/7
I~_ _-
INTERRUPT CAUSED BY DCD GOING lOW, NO FURTHER INTERRUPTS UNTil NEXT FUll WORD
Package Outlines
28-Lead Plastic
28-Lead Cerdip
28-Lead Ceramic
PIN 1 IDENTIFIER
PIN 1 IDENTIFIER
T
1
"
,)
"
MAHKI~GS
V
I
1.450 MAX
a.a2D
0.015
L
14
1D;:J~------'---'-'--L~O'59--'"oj
0,015 MIN
~
•
15
0.480
~O'6101BENO
0.590
0.200 MAX
flE3 f\
150MA~ II
4.25
'L
-J
0.012
0.008
15
ON LID
SURFACE
ONL~
I
CRT Controller
-} GOULD
AIMII®Semiconductors
S6845E
Features
• Single + 5 volt (± 5%) power supply.
• Alphanumeric and limited graphics capabilities.
• Fully programmable display (rows, columns,
blanking, etc.).
• Interlaced or non-interlaced scan.
• 50/60 Hz operation.
• Fully programmable cursor.
• External light pen capability.
• Capable of addressing up to 16K character Video
Display RAM.
• No DMA required
• Pin-compatible with MC6845R.
• Row/Column or straight-binary addressing for
Video Display RAM.
• Video Display RAM may be configured as part of
microprocessor memory field or independently
slaved to 6845.
.
.• Internal status register.
• 3.7 MHz Character Clock..
• Transparent Address Mode.
Description
The S6845E is a CRT Controller intended to provide
capability for interfacing any 8 or 16 bit microprocessor
family to CRT or TV-type raster scan displays. A unique feature is the inclusion of several modes of operation, so that the system designer can configure the
system with a wide assortment of techniques.
Interface Diagram
Pin Configuration
GND
Vee
GNU
RES
LPEN
ceD/MAD
080·087 ' - _ - / 1
R/W--....
HA1
~-_HSYNC
eC1/MA1
HA2
!---VSYNC
CC2/MA2
HAl
~-- DISPLAY ENA8LE
eC3/MA3
HA4/STB
~--CURSOR
CC4/MA4
DBD
LPEN
CCLK
CC5/MA5
DB1
CC6/MA6
DB2
RES
CC7/MA7
DBl
CS
R S - -....
DB4
DB5
DB6
\ MAD·MA13
DB7
RAD·RA4 /
cs
VIDEO DISPLAY RAM AND CHARACTER ROM
RS
Riw
CCLK
4.26
-) GOULD
AIMII®Semiconductors
56845E
Absolute Maximum Ratings·
Supply Voltage, Vee ............................................................................................................................ - 0.3V to + 7.0V
Input/Output Voltage, VIN ••••••••••••••••••••••••..•••••••••••...••••..•••..••••.••....•....••••••••••••...••••...••••..•••••.•••••.•..•••• - 0.3V to + 7.0V
Operating Temperature, Top ...................................................................................................................... O·C to 70·C
Storage Temperature, TSTG •••••••••••.••••.•••••..••..•••...••..••••...••••...•••••••..•..••••••.•.••.••••...••...•.••••...••••..••••..... - 55·C to 150·C
'COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device, These are stress ratings only. Functional
operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied and exposure to absolute max·
imum rating conditions for extended periods may affect device reliability ..
Electrical Characteristics: Vee:::
Symbol
VIH
VIL
+ 5.0 ± 5%, TA ::: O·C to 70·C, unless otherwise noted.
Parameter
Min.
Input High Voltage
2,0
Input Low Voltage
-0.3
liN
Input Leakage (~2,
LPEN, CCLK)
ITSI
Three-State Input Leakage (DBO-DB7)
VIN = 0,4 to 2.4V
VOH
Output High Voltage
ILO AO = - 2051-/A (DBO- DB7)
ILOAD = - 100i-tA (all others)
VOL
Output Low Voltage
ILOAO = 1,6mA
Typ.
Max.
Units
Vce
O.B
V
2.5
I-/A
±10,0
I-/A
Conditions
V
R/W, RES, CS, RS,
2.4
V
325
PD
Power Dissipation
CIN
Input C~acitance
~2, R/W, RES, CS, RS, LPEN, CCLK
DBO-DB7
0.4
V
650
mW
10,0
12.5
pF
pF
10,0
Output Capacitance
pF
COUT
All inputs contain protection circuitry to prevent damage due to high static discharges. Care should be exercised to prevent unnecessary application 01 voltages in excess of
the allowable limits.
Test Load
Vee
2.4KQ
S6845E PIN --.----..-~
• • • • • • • •
• • • • • • •
• • • • • • • •
G
V2 V1 Va
H3
H2
H1
Ho
• • •
•
to\~. • •
~~~ • • •
U1 Uo C D
t;\.:•• ~:;~> f0\\'\. •
0;\'~\\ B1 8 •
\~; ~~ ~\~ •
~ ~~ • •
• • • •
\~\ ~~'\I • •
• • • •
\\~ ~\\ • •
• • • •
'&~ l\\\~ • •
• • • •
•
•
•
•T
•
•
•
•
•
•
•
•
RC
•
•
•
•
•
•
•
•
•
•
•
•
•
11
•
•
•
•
•
•
•
•
•
10
•
•
•
•
•
V3
t\~\\
~\\'\ l\~\ fi~\\~·
G
0
•
•
•
•
• •
• •
• •
• • •
• • •
• • • •
~\\\\ ~\~~ ~\~\ ~~\\ \{';\' .,'\ ..';;; '~
0
I
I
-} GOULD
AIMII®Semiconductors
S6845E
Cursor Start (R10) and Cl.!rsor End (R1 i)
These 5-bit registers select the starting and ending
scan lines for the cursor. In addition, bits 5 and 6 of R10
are used to select the cursor mode, as follows:
Vertical Total Adjust (RS) .
The Vertical Total Adjust Register is a 5-bit write only
register containing the number of additional scan lines
needed to complete an entire frame scan and is intended as a fine adjustment for the video frame time.
Vertical Displayed (R6)
This 7-bit register contains the number of displayed
character rows in each frame. In this way, the vertical
size of the displayed text is determined.
Vertical Sync Position (R7)
This 7-bit register is used to select the character row
time at which the VSYNC pulse is desired to occur and,
thus, is used to position the displayed text in the vertical direction ..
Mode Control (RS)
This register is used to select the operating modes of
the S6845 and is outlined as follows:
L
0
1
~
-
6
0
0
1
1
INTERLACE MODE CONTROL
r--;+u
X
BIT
0
1
1
OPERATION
Non·lnlerlace
Interlace SYNC Rasler Scan
Interlace SYNC and Video Raster Scan
VIDEO DISPLAY RAM AODRESSING
"0" for straight binary
"1" fur Row/Column
VIDEO DISPLAY RAM ACCESS
"0" fur shared memory
"1" for transpanmt memory addressing
DISPLAY ENABLE SKEW
"0" fur no delay
"1" to delay DIsplay Enable one character tim
CURSOR SKEW
"0" fur no delay
111" to deily Cursor one character time
UPDATE STROBE (TRANSPARENT MOOE, ONLY)
"0" fur pin 34 to function as memory. address
"1" fur pin 34 to function as update slnlbe
UPDATE/READ MODE (TR ANSPARENT MODE, ONLy)
"0· for updates to occur durlng horizontal and vertical
blanking times with update slnlbe
"1" for update to be interleaved In <1>2 portion of cycle
Scan Line (R9)
This 5-bit register contains the number of scan lines per
character row, including spacing minus one.
CURSOR MODE
5
0
1
0
1
No Blinking
No Cursor
Blink at 16x field rate (fast)
Blink at 32x field rate (slow)
Note that the ability to program both the start and end
scan line for the cursor enables either block cursor or
underline to be accommodated. Registers R14 and R15
are used to control the character position of the cursor
over the entire 16K address field.
Display Start Address High (R12) and Low (R13)
These registers together comprise a 14-bit register
whose contents is the memory address of the first
character of the displayed scan (the character on the
. top left of the video display, as in Figure 1). Subsequent
memory addresses are generated by the S6845 as a
result of CCLK input pulses. Scrolling of the display is
accomplished by changing R12 and R13 to the memory
address associated with the first character of the
desired line of text to be displayed first. Entire pages of
text may be scrolled or changed as well via R12 and
R13.
Cursor Position High (R14) and Low (R1S)
These registers together comprise a 14-bit register
whose contents is the memory address of the current
cursor position. When the video display scan counter
(MA lines) matches the contents of this register, and
when the scan line counter (RA lines) falls within the
bounds set by R10 and R11, then the CURSOR output
becomes active. Bit 5 of the Mode Control Register (R8)
may be used to delay the CURSOR output by a full
CCLK time to accommodate slow access memories.
LPEN High (R16) and Low (R17)
These registers together comprise a 14-bit register
whose contents is the light pen strobe position, in
terms of the video display address at which the strobe
occurred. When the LPEN input changes from low to
high, then, on the next negative-going edge of CCLK,
the contents of the internal scan counter is stored in
registers R16 and R17.
4.34
~ GOULD
AIMII®Semiconductors
S6845E
Update Address High (R1S) and Low (R19)
Figure 4 illustrates the address sequence for the video
display control for each mode.
Note from Figure 4 that the straight-binary mode has
the advantage that all display memory addresses are
stored in a continuous memory block, starting with address 0 and ending at 1919. The disadvantage with this
method is that, if it is desired to change a displayed
character location, the row and column identity of the
location must be written. The row/column mode, on the
other hand, does not need to undergo this conversion.
However, memory is not used as efficiently, since the
memory addresses are not continuous, but gaps exist.
This requires that the system be equipped with more
memory than is actually used and this extra memory is
wasted. Alternatively, address compression logic may
be employed to translate the row/column format into a
continuous address block.
In this way, the user may select whichever mode is best
for the given application. The trade-offs between the
modes are software versus hardware. Straight-binary
mode minimizes hardware requirements and
row/column requires minimum software.
These registers together comprise a 14-bit register
whose contents is the memory address at which the
next read or update will occur (for transparent address
mode, only). Whenever a read/update occurs, the update location automatically increments to allow for fast
updates or readouts of consecutive character locations. This is described elsewhere in this document.
Dummy Location (R31)
This register does not store any data, but is required to
detect when transparent addreSSing updates occur.
This is necessary to increment the Update Address
Register and to set the Update Ready bit in the status
register.
Description of Operation
Register Formats
Register pairs R121R13, R14/R15, R16/R17, and R18/R19
are formatted in one of two ways:
1. Straight binary if register R8, bit 2 is a "0".
2. Row/column if register R8, bit 2 is a "1". In this
case the low byte is the Character Column and
the high byte is the Character Row.
Figure 4. Display Address Sequences (with Start Address = 0) for SO
~
I
77 ! 78
79
157 . 158 ' 159
BO
160
240
Bl
161
241
B'
I_N' 0
169
--I ~~~B~O=~Bl~~'
~B2~=-=--===:~~~~~~;t~;~~~:=:;~
237 238 ~ 239
160 161 162
24'
I
"
I
:;
~
~
7
ITT~,
,
0
:
:
BO -~-~
::: ,
--
1917 1918: 1919 1920 1921
1997 1998 1999 2000 2001
2071 2078 2079 2080 2081
---
I
2717 2718 2719 2720' 2721
---
I
1
2
1
257
513
2
25B
514
---
,
5633
5889
6145:
6401
5634
5B90
77
78
79
---
5B9
7B
33.
590
79
---
77
333
I
81
BO
336
592
Bl
337
593
B9
345
60'
5110 5711 5712 5713
5966 5967 5968 t 5969
6222 6223 6224 6225
6478 6479 6480 6481
5721
5977
6233
6489
335
591
5632
5888
6144
6400
6146
6402
---------
---------
5709
5965
6221
6477
2729
J
8448 8449, 8450
---
---
8525 8526 8527· 8528 8529
J
:
STRAIGHT BINARY ADDRESSING SEQUENCE
--
80
,
,
--ILI-2-,-!00,=0~'2=00.,J':,=20~02,.:---,-_,-==--=o=-"=-c=~=--_+=~
:
2640 ' 2641 : 2642: ...
0
0
256
512
1929
2009
20B9
1837 183B 1839 1840 1841
1849
L~17~60~"~76~1~"~762~-~--~~~~~~~~~_~
~::~ :~::~ I ~::~:
~SPlAY ~
:
, ::
:
I
is
II
~
-------TOTAl~90---~
,---~-~-COlUMH AOORESS(MAO·MA71-~--
I
I
Ir
I
-------
TOTAl~'O
x 24 Example
Bst-
ROW/COLUMN ADDRESSING SEQUENCE
4.35
I
I
-} GOULD
AIMII®Semiconductors
S6845E
must resolve this multiple access requirement.
Figure 5 illustrates the system configuration.
2. Transparent Memory Addressing
For this mode, the display RAM is not directly accessible by the MPU, but is controlled entirely by
the 56845. All MPU accesses are made via the
56845 and a small amount of external circuits. Figure 6 shows the system configuration for this approach.
Video Display RAM Addressing
There are two modes of addressing for the video
display memory:
1. 5hared Memory
In this mode the memory is shared between the
MPU address bus and the 56845 address bus. For
this case, memory contention must be resolved by
means of external timing and control circuits.
Both the MPU and the 56845 must have access to
the video display RAM and the contention circuits
Figure 5_ Shared Memory System Configuration
SYSTEM
BUS
VSYNC
HSYNC
S6845E
CRT COHT1IOUEIl
[XSPlAY ENABlE
RAD-RU
CURSOR
TO
VIlEO
ClllCUTS
Figure 6_ Transparent Memory Addressing System Configuration (Data Hold Latch needed for
HorizontallVertical Blanking updates, only)_
SYSTEM
BUS
MAIJ.MA 13
RAo.RA3
SCAN I.I
VBB[=>
,p
LCD,
DPT
5.3
1-:
--
-) GOULD
AIMII®Semiconductors
S4520
Absolute Maximum Ratings
VD D ............................................................................ - O.3V to + 17V
VB B ...................................................................... Vss + O.3V to VDD - 32V
Inputs (ClK, DATA IN, lOAD) ................................................. Vss - O.3V to VDD + O.3V
Inputs (lCD",) ............................................................. VBB - O.3V to VDD + O.3V
Power Dissipation ....................................................................... 250mW
Storage Temperature ........................................................... - 65°C to + 125°C
Operating Temperature ........................................................ " - 55°C to + 85°C
Electrical Characteristics: 3V~VDD~16V, -55°C~TA~ +85°C, unless otherwise noted
Symbol
Parameter
Voo
Power Supply
Logic Supply Voltage
Vss
Display Supply Voltage
100
Supply Current (external oscillator)'
Supply Current (internal oscillator) ,
Iss
Display Driver Current
V1H
V1L
Min.
Inputs (CLK, DATA IN, LOAD, CS)
Input High Level,
Input Low Level
Max.
Units
3
16
V
Voo - 32
VDD-15
V
200
200
fAA
fAA
-200
fAA
0. 5Voo
Voo
V
Vss
0. 2Voo
5
V
Input Leakage Current
Test Condition
Vss:5Vss
CMOS input levels. No loads.
fsp = 100Hz. No loads.
Voo~5V
5
fAA
pF
±25
mV
Voo
0.1 Voo
V
Externally Driven
V
Externally Driven
Capacitance Loads (typical)
Segment Output
1000
pF
jsp~ 100Hz
CLsp
Backplane Output
40000
pF
fsp~ 100Hz
RSEG
Segment Output Impedance
10
KQ
Rsp
Backplane Output Impedance
312
Q
IL= 1O fAA
IL= 1O fAA
Roo
Data Out Output Impedance
3
KQ
IL = 1O fAA
IL
C1
Input Capacitance
VO AVG
DC Bias (Average) Any Segment Output to
Backplane
V1H
V1L
LCD~
Input High Level
0. 9Voo
LCD~
Input Low Level
Vss
CLSEG
5.4
jsp~ 100Hz
-) GOULD
AIMII®Semiconductors
54520
Timing Characteristics:
Symbol
tCYC
Parameter
Min.
Max.
Units
Cycle time (noncascaded)
1000
500
320
ns
ns
ns
1300
600
350
ns
ns
ns
tCYC
Cycle time (cascaded)
tOl, tOH
Clock pulse width low/high
450
220
140
ns
ns
ns
tOH
Clock pulse width high (cascaded)
750
320
180
ns
ns
ns
t r, tf
Clock rise, fall (Note 12)
tos
Data In setu p
300
150
120
ns
ns
ns
tcsc
CS setup to Clock
200
100
50
ns
ns
ns
tOH
Data hold
10
ns
tccs
CS hold
450
220
140
ns
ns
ns
tCl
Load pulse setup (Note 5)
500
280
180
ns
ns
ns
tlCS
CS hold (rising LOAD to rising CS)
300
200
150
ns
ns
ns
500
220
140
ns
ns
ns
1
tlW
Load pulse width (Note 5)
tlC
Load pulse delay (Falling load to falling clock)
tcoo
Data Out valid from Clock
tCSl
0
5.5
3.0V
5.0V
~7.5V
3.0V
5.0V
~7.5V
3.0V
5.0V
~7.5V
3.0V
5.0V
~7.5V
I-ls
3.0V
5.0V
~7.5V
3.0V
5.0V
~7.5V
3.0V
5.0V
~7.5V
3.0V
5.0V
~7.5V
3.0V
5.0V
~7.5V
3.0V
5.0V
~7.5V
ns
0
550
220
110
CS setup to LOAD
Vou
ns
ns
ns'
ns
3.0V
5.0V
~7.5V
1-:
--
-) GOULD
AIMII®Semiconductors
54520
Figure 1. Signal Timing Diagram
leye
H'l -'' l
I,
CLOCK
~
j~DATAIN~
j+-
V.
1,-
I
10.
~
/
,,
I
,I
I
I
I
~"'1Y
CS~
~
P.=, leSl
I
,lleS-j !
~
~tCL ----..
Yi
-1-'"
--Ilw-
~
)/
LOAD
-I I~DD C=
X
?<
DATA OUT
'i
/
X
Logic Truth Table
x
X
X
X
a
a
a
a
1
1
1
1
Noles:
s
s
LL-
s
s
LL-
NC = No Change
1
1
a
a
a
a
a
a
a
a
a
NC
NC
NC
NC
1
a
1
a
a
a
1
0
NC
NC
1
1
1
a
1
SR = Shift Register
L = Latch
5.6
NC
NC
NC
NC
ON-1-+0N
ON-1-+0N
NC
NC
ON-1-+0N
ON-1-+0N
QN(L)
ON(L)
ON(L)
ON(L)
ON(L)
ON(SR)
ON(L)
ON(L)
ON(L)
QN(SR)
-} GOULD
AIMII®Semiconductors
54520
Operating Notes
1. The shift register loads and shifts on the falling edge of CLK. DATA OUT changes on the rising edge of CLK.
2. The buffer number corresponds to how many clock pulses have occurred since its data was present at the input
(e.g., the data on Q10 was input 10 clock pulses earlier). DATA is shifted into Segment 1 and shifted out from Segments 30, 32 or 38, depending on bonding option used.
3. A logic 1, shifted into the shift register (through DATA IN), causes the corresponding segment's output to be out
of phase with the backplane.
4. A logic 1 on LOAD causes a parallel load of the data in the shift register, into the latches that control the output
drivers.
5. LOAD may also be held high while clocking. In this case, the latch is transparent and, the falling edge of LOAD will
latch the data.
6. To cascade units, (a) connect the DATA OUT of one chip to the DATA IN of the next chip, and (b) either connect
the backplane of one chip to LCD~ of all other chips (thus one RC provides frequency control for all chips) or connect LCD~ of all chips to a common driving signal. If the former is chosen, the backplane that is tied to the LCD~ of
the other chips should not also be connected to the backplanes of those chips.
7. The LCD~ pin can be used in two modes, driven or self-oscillating. If LCD~ is driven, the circuit will sense this
condition. If the LCD~ pin is allowed to oscillate, its frequency is determined by an external capacitor. The
Backplane frequency is a divide by 256 of the LCD~ frequency, in the self-oscillating mode.
8. If
LCD~
is driven externally, it is in phase with the backplane output.
9. Backplanes can be tied together, if they have the same signal applied to their
LDC~
--
inputs.
10. In the self-oscillating mode, the backplane frequency is approximately defined by the relationship
fsp(Hz) = 10 -+- R(C + .0002) at VDD = 5V, R in KQ, C in {.IF.
examples:
R
R
= 56Kf!, C = .0015/tF:
= 110Kf!, C = .00068/tF:
f BP =100Hz
f BP =100Hz
11. Minimum value of R for RC oscillator is 50KQ.
12. Power consumption increases for clock rise or fall times greater than 100ns.
Ordering Information
1. All orders must specify a package type (i.e. S4520C, 48 CLCC)
2. All orders must specify whether an internal oscillator or external oscillator will be used (i.e. S4520D external
oscillator).
3. A set-up charge or minimum order quantity may apply for packaging options not shown.
4. Standard products available, (refer to pages 1 and 8 for pin out descriptions):
Version
Package
Segments
S4520G
48 GLGG
38
Internal
S4502D
48 GLGG
38
External
38
S4520G
44 PLGG
32
Int or Ext
32
Contact sales office for other packaging options.
5.7
Oscillator
1-:
Data Out
38
-) GOULD
AIMII®Semiconductors
54520
Data Input
Chip Select Inverse Input
The C8 input is used to enable clocking of the shift
register. When C8 is low, the chip will be selected and
the shift register will be enabled. When C8 is high, the
shift register will be disabled and the output buffers will
be driven by the data in the latches.
Data present at DATA IN will be clocked into the shift
'register,when C8 is low. Data is loaded into the shift
register on the falling edge of the clock and shifts to the
output on the riSing clock edge.
Clock Input
Data Output
The CLOCK input is used to clock data serially, into the
shift register. A clock signal may be continuously pre·,
sent, because the shift register is enabled only when
C8 is low.
Depending on the packaging option selected, 0030,
0032 and 0038 are buffered outputs driven by the
corresponding element of the shift register. The value
of DOxx will be the same as the value of the matching
shift register bit (Le. the value at 0032 will be the same
as bit 32 of the shift register). The data output is typi·
cally used to drive the data input of another 84520. By
cascading 84520 circuits in this manner, additional
display elements can be driven.
Load Input
The LOAD input controls the operation of the data lat·
ches and allows new data to be loaded into the shift
register, without changing the appearance of the dis·
play. When LOAD is high, the values in the shift register
will be loaded into the data latches. If desired, LOAD,
can be held high and the data latches will be trans·
parent. The LOAD input is disabled when C8 is high.
Backplane Output
The backplane output provides the voltage waveform
for the LCD backplane. When used with the internal
oscillator, the backplane frequency will be equal to the
oscillator frequency divided by 256:
LCD Oscillator Input
When used with an external oscillator, the LCD
oscillator is driven by the input voltage level. In this
configuration, the backplane output will be in phase
with the input waveform. In the self·oscillating mode,
an external resistor and capacitor are connected to the
oscillator input pin, and the backplane frequency will
be a divide by 256 of the internal oscillator frequency.
fBP = fosc (int) + 256.
With an external oscillator, the backplane frequency
will be in phase with and equal in magnitude to the in·
put signal.
'
Segment Drive Outputs
LCD Oscillator Options
The segment drive outputs provide the segment drive
voltage to the LCD. With a logic level "1" in the latch
associated with the segment drive output, the output
voltage will be out of phase with the backplane (i.e the
segment will be ON). A logic level "0" will cause the
segment drive to be in phase with the backplane output
voltage.
Internal Oscillator - The LCD oscillator option (LCDq,
OPT) is internally (or externally) connected to the LCD
oscillator input (LCDq,) and, it provides the oscillator
feedback.
External Oscillator - The LCD oscillator option is not
connected.
5.8
-?
GOULD
AIMII®Semiconductors
54520
Figure 2. Typical Application
MICROPROCESSOR DRIVEN
CASCADED DISPLAY DRIVERS
4-2~V
6t-::l-
J
~
R
VBB~
VDD
21 ..
LCD~
0, 25
··
··
··
··
l.LCD~ OPT.
C ....L..
1-
flPRDCESSOR
-1Z.
cs
P,
S4520A
20 DATA IN
P2
19 LOAD
18
P3
03B
Vss
24
BP~ -
CLOCK
I
P4
~
-
39
0038
~-
I:
I
LCD
SEGMENT.
I
···
·
--
I
I
LCD
BAC KPLANE
r-
I
,'-
~
I
VBB~
VDD
l! LCD~
··
··
···
·
0, 25
-:fLCD~ OPT.
~
cs
S4520B
20 DATA IN
19 LOAD
18 CLOCK
,
t
Vss
Q3B
24
BP 45
0038
46
,
:
:t
y
TO OTHER S4520 DISPLAY DRIVERS
5.9
··
···
J
I
GOULD
AIMII®Semiconductors
54520
44-Plastic Leaded Chip Carrier (PLCC)
39·0,7
37·0,5
36·V BB
35-0,.
845206
34-013
HIM3
33-0 12
VSS·14
32.0 11
&S'15
31·0,0
CLOCK·16
30·Qg
LOAD-17
18 19
~
21
DATA lCD¢ LCD\b VDD
IN
OPT.
22
0,
23
0:
~
0,
25
o(
26
05
V
06
28
07
48-Ceramic Leadless Chip Carrier (CLCC)
0"
42
0" VM 0,. 0'3
41 40
39 38
012 0"
37 36
010 Og
0,
35 34
33
0,
32
0,
0"
42
31
0" V..
41
40
0,. 0'3
39 38
Ou 0 11
37 36
D'D Og
35 34
0,
33
0,
32
0,
31
O,r43
30-05
°
17,43
30-05
018-44
"..
0,8,44
29.Q(
28-03
O,rt5
28-U3
BP46
27-02
BP4.
27-0 2
DATA ~~.47
26.(1,
DATA ~~.47
26-0,
,9
0 45
02n,48
25-038
02D,48
25'(ha
021"
24.0 31
021 "
24-031
022"2
Z3-Voo
022 ,2
23.V oo
0 23 ,3
22·lCD<,6 OPT.
02J·3
2HCOqi
024 -4
21-DATA IN
024 -4
21-DATA II
025 ,5
20·LOAD
02s,5
21J.lOAD
Ou·6
19-tLOCK
026,6
19-ClOCK
7
0"
8
9
OZB 029
10 11
030 031
12 13
032 033
14 15
034 035
16 17
0]6 Vss
7
0"
18
os
NOTE: Viewed From Top Side of Package
Contact sales for other possible package options.
5.10
8
an
9
0 29
10 11
030 031
12 13
032 033
14 15
0" 0"
16 17
036 VSS
18
CS
32 Bit Driver
-) GOUL[]
AIMII®Semiconductors
S4521
General Description
Features
D Drives Up to 32 Devices
D Cascadable
The S4521 is an MOS/LSI circuit that drives a variety of output devices, usually under microprocessor
control. This device requires only three control lines
due to its serial input construction. It latches the data
to be output, relieving the microprocessor from the
task of generating the required waveform, or it may be
used to bring data directly to the drivers. The part acts
as a versatile peripheral to drive displays, motors,
relays and solenoids within its output limitations. It is
especially well suited to driving liquid crystal displays,
with a backplane A.C. signal option that is provided.
The A.C. frequency of the backplane output that can be
user supplied or generated by attaching a capacitor to
the LCD! input, which controls the frequency of the internal oscillator. One circuit will drive up to 32 devices
and more can be driven by cascading several drivers
together. The S4521 F version is available in a surfacemountable plastic mini-flat pack.
D On Chip Oscillator
D Requires Only 3 Control Lines
D CMOS Construction For:
Wide Supply Range
High Noise Immunity
Wide Temperature Range
Applications:
D Liquid Crystal Displays
D LED and Incandescent Displays
D Solenoids
D Print Head Drives
D DC and Stepping Motors
D Relays
Pin Configuration
Functional Block Diagram
CLOCK
DATA
OUT
DATA IN
LOAD
5.11
1-:
I
--
I
+VDD
CLOCK
LOAD
0,
0"
0,
0"
OJ
0"
Vss
0"
DATA OUT
0"
DATA IN
0"
0,
0"
0,
0"
LCO~
0"
SP
0"
0,
0"
0,
0"
0,
0"
019
0,
010
018
011
017
0"
Q1"6
0"
015
0"
I
-) GOULD
AIMII®Semiconductors
S4521
Absolute Maximum Ratings
VDD .... ......... ........ ................. ............ ...... ....... ....... ...... ... ......... ... .............. ............. ........ ....... ....... .... ......... - 0.3 to + 17V
Inputs (ClK, DATA IN, lOAD, lCD",) ....................................................................................... Vss - 0.3 to VDD + 0.3V
Power Dissipation ............................................................................................................................................. 250mW
Storage Temperature ..................................................................................................................... - 65°C to + 125°C
Operating Temperature ................................................................................................................... - 40°C to + 85°C
Electrical Characteristics:
Symbol
Parameter
Voo
Supply Voltage
1001
1002
Operating
Quiescent
3V~VDD~13V,
unless otherwise noted
Min.
Max.
Units
3
13
V
Test Condition
200
200
!-iA
!-iA
fsp = 120Hz, No load, Voo = 5V
lCD", High or low, fsp=O
load @ logic 0, Voo = 5V
Voo
Voo
0.2 Voo
5
5
V
V
V
!-iA
pF
3V~Voo<5V
2
MHz
Supply Current
Inputs (CLK, DATA IN, LOAD)
0.6 Voo
0.5 Voo .
Vss
V1H
High level
V1L
IL
CI
low level
Input Current
Input Capacitance
fCLK
ClK Rate
DC
los
Data Set-Up Time
100
ns
Data Change to ClK Falling Edge
IOH
Data Hold Time
10
ns
Falling ClK Edge to Data Change
Ipw
load Pulse Width
200
ns
Ipo
Data Out Prop. Delay
ILC
load Pulse Set-U p
ILCO
load Pulse Delay
VOAVG
DC Bias (Average) Any Q
Output to Backplane
V1H
V1L
lCD", Input High level
lCD", Input low level
220
5V~Voo~13V
50% Duty Cycle
ns
CL = 30pF, From Rising ClK Edge
300
ns
Falling CLK Edge to Rising load
Pulse
0
ns
Falling load Pulse to Falling ClK
Edge
±25
mV
fsp = 120Hz
.9 Voo
Voo
V
Externally Driven
Vss
.1 Voo
V
Externally Driven
50,000
1.5
Capacitance Loads
CLQ
CLSP
Q Output
Backplane
RON
Q Output Impedance
3.0
pF
!-IF
KQ
RON
Backplane Output Impedance
100
Q
IL = 10!-iA, Voo = 5V
RON
Data Out Output Impedance
3.0
KQ
IL = 10!-iA, Voo = 5V
5.12
fsp = 120Hz
fsp = 120Hz, See Note 8
IL = 10!-iA, Voo = 5V
-) GOULD
AIMII®Semiconductors
54521
sense this condition. If the LCDt pin is allowed to
oscillate, its frequency is determined by an external
capacitor. The Backplane frequency is a divide by 32
of the LCDt frequency, in the self-oscillating mode.
Operating Notes
1. The shift register shifts on the falling edge of CLK. It
outputs on the rising edge of the CLK.
2. The buffer number corresponds to how many clock
pulses have occurred since its data was present at
the input (e.g., the data on Q10 was input 10 clock
pulses earlier).
8. In the self-oscillating mode, the backplane frequency
is approximately defined by the relationship
fsp(Hz) = 0.2 + C(in (.IF) at VDD :: 5V.
3. A logic 1 on Data In causes a Q output to be out of
phase with the Backplane.
9. If the total display capacitance is greater than 100,000
pF, a decoupling capacitor of 1/AF is required
across the power supply (pins 1 and 36).
4. A logic 1 on Load causes a parallel load of the data in
the shift register, into the latches that control the Q
output drivers.
Pin Description
5. To cascade units, (a) connect the Data Out of one
chip to Data In of next chip, and (b) either connect
Backplane of one chip to LCDt of all other chips
(thus one RC provides frequency control for all
chips) or connect LCDt of all chips to a common
driving signal. If the former is chosen, the Backplane
that is tied to the LCDt inputs of the other chips
should not also be connected to the Backplanes of
those chips.
Name
2
30
31
34
35
VDD
LOAD
BP
LCDt
DATA IN
DATA OUT
36
40
3-29,
32·33,
37-39
6. If LCDt is driven, it is in phase with the Backplane
output.
7. The LCDt pin can be used in two modes, driven or
self-oscillating. If LCDt is driven, the circuit will
S"",, Tlml", DI,,
0,
02 --------------------------010
Output Buffer (Functional Diagram)
,-------.-<:::::J v"
'-N~_NV+_<--, OUTPUT
D-uJU
'lB
I/O
t-- MACRO
CELL
'--------,-
r-tr
~
INPUT
.:::L
""
"
'" ""
""
~
17
t--
I/O
MACRO
CELL
.
.
.
~
~
j
" ""
""
""
ru
~
~
INPllT
"
.....L
~w
16
lio
MACRO
t--
.
CELL
r-H>-0n
W .
~
i
" ""
"
",. ""
INPUT
I:
-0-<
"
6
I/O
MACRO
!---
'
CELL
~
"
."'" .,""
lNPllT
7
it ~':::tJ
::B:\
'" "
I/O
'W
CELL
~
. ""
INPUT
B
~
"
" ""
""
~
r---
W
~rw
MACRO
~
CELL
-r
I/O
~
" "
" ""
" ""
w~
~
INPlJT
CD
12
I/O
' - - MACRO
CELL
~USCLEAR:
"
(TO ALL MACRO CELLS)
DIl
6.4
INPUT
-) GOULD
AIMII®Semiconductors
PEEC 18CV8
M
18CV8 not only reduces development and field retrofit
costs but enhances testability enabling Gould to ensure
100% field programmability and function.
Packaged in a cost-effective "window-less" 20 pin DIP,
the flexible architecture of the PEEL 18CV8 allows for
replacement of standard SSI/MSI logic circuitry or pin-out
compatible emulation of 20-pin bipolar PAL devices and
the Altera EP300/310.ln addition, over a hundred new logic
configurations, not possible with earlier generation PLDs,
can be implemented. Primary development and programming support of the PEEL 18CV8 is provided by popular
third-party PC based development tools and stand-alone
programmers. Gould also offers a Development System
specifically for the PEEL 18CV8 and other PEEL devices.
feedback, registered or combinatorial output and output
polarity control. The output enable term of each 1/0 pin can
be used to force a high impedance state for bi-directional
1/0 operations or for dedicated input usage. The synchronous preset term; asynchronous clear term and clock (pin
1, IICLK) are globally routed to all macro cells.
Logic Array Operation
A more detailed view of the overall architecture, specifically the logic array, is illustrated by the PEEL 18CV8 Logic
Array diagram in figure 3. As referred to previously, the
logic array of the PEEL 18CV8 consists of:
• 36 Input Lines:
10 true and complement inputs
8 true and complement inputslfeedbacks
• 74 Product Terms:
64 product terms (8x8 Sum-of-Products form)
8 output enable product terms
1 synchronous preset term
1 asynchronous clear term
Looking at the logic array diagram, the 36 input lines (035) run vertically and the 74 product terms (0-73) run
horizontally. Each input line and product term intersection
in the array has an associated programmable E2PROM
memory cell that determines whether the intersection is
connected or open. A connection allows an input line to
become a logical input of the intersected product term
(AND gate). Thus, each product term, although unlikely in
a real application, truly equals a 36 input AND gate.
In figure 3, the logic array has 64 product terms that
are divided into groups of 8 each feeding into a sum (OR
gate). By connecting specific inputs or 110 macro cell
feedbacks to the product terms, complex sum - ofproducts logic functions can be created. Each sum feeds
into its associated 110 macro cell where the logic function
can be further controlled for output to an I/O pin or feedback into the array.
In addition to the 64 product terms of the 8 sum-ofproduct groups, there are 8 output enable product terms, 1
synchronous preset product term and 1 asynchronous
clear product term. These additional terms are used to
directly control specific I/O functions which are covered in
the following section.
Architectural Overview
The basic architecture of the PEEL 18CV8 is similar to
that of earlier generation PLDs to the extent that it utilizes
a sum-of-products logic array in a programmable AND
fixed OR structure. This familiar logic arrangement allows
user defined output functions to be created by programming the connection of input signals into the array. What
makes the architecture of the PEEL 18CV8 different, however, is the increased capability and flexibility it provides
resulting in a higher level of equivalent gate integration and
a simplification of design. '
The block diagram in figure 2 illustrates the key elements
of the PEEL 18CV8 architecture. Externally, the PEEL
18CV8 provides up to 18 inputs and 8 outputs for use. At
lhe core is a programmable electrically erasable "AND
array" of 36 input lines by 74 product terms. The 36 input
lines are derived from the true and complements of the 18
possible input pins. The 74 product terms are made up of:
1 synchronous preset term, 1 asynchronous G,lear term, 8
output enable terms and 64 terms divided into groups of 8
each feeding into an OR function.
Each OR function is directly associated with one of eight
macro cells and 1/0 pins. An individual macro cell can be
programmed into one of twelve different configurations.
Depending on the configuration, the output of the macro
cell can be fed back into the array or output via its associated 110 pin. The configurations include various arrangements for bi-directional 110, registered or combinatorial
6.5
-} GOULD
AIMII®Semiconductors
PEEC 18CV8
M
1/0 Macro Cell and Output Enable Operation
ity allows a single PEEL 18CV8 to implement a combination
of configurations among its eight macro cells. The configurations include various arrangements for bi-directional II
0, registered or combinatorial feedback, registered or
combinatorial output and output polarity control. The twelve
possible 1/0 macro cell configurations are listed in table 1.
Their equivalent circuits are illustrated in figure 5.
A great amount of architectural flexibility is provided by
the PEEL 18CV8's reconfigurable 1/0 macro cells and independently controlled output enables. A closer look at the
1/0 macro cell, figure 4, shows that it consists ofa Ootype
flip-flop and two signal select multiplexers.
The Ootype flip-flop operates similarly to standard TTL
o flip-flops to the extent that the 0 input is latched on the
rising edge (lOW to HIGH transition) of the ClK input and
Q or 0' output signals can be used. Two additional inputs
are controlled by the asynchronous clear and synchronous
preset terms.
When the asynchronous clear product term is asserted
(HIGH) the Q output will immediately be set to a lOW
regardless of the clock state. When the synchronous preset term is asserted (HIGH) the Q output will be set to a
HIGH on theJoliowing rising edge (LOW to HIGH transition)
of the ClK input. Priority is given to the asynchronous clear
signal if both asynchronous clear and synchronous preset
have been asserted. Upon power-up, the asynchronous
clear function is automatically performed setting the Q
outputs of all macro cell flip-flops to a lO"'!.
The two signal select multiplexers of each macro cell are
controlled by four E2PROM programmable bits (A,B,C and
0) that determine which of the twelve possible configurations the ~acro cell will assume. This independent flexibil-
Table 1. PEEL 1jiCV8 macro cell configurations
Configuration
A B C
1 1 1 1
2 0 1 1
3 1 0 1
4 0 0 1
5 1 1 1
6 0 1 1
7 1 0 1
8 0 0 1
9 1 1 0
10 0 1 0
11 1 0 0
12 0 0 0
#
D InputlFeedback Select
Output Select
1 Bi-Directional 1/0
Register
Active
1
Active
1
Combinatorial
Active
1
Active
0 Combinatorial Feedback Register
Active
0
Active
0
Combinatorial Active
0
Active
0 Register Feedback
Register
Active
0
Active
0
Combinatorial
Active
0
Active
Figure 4. PEEL 18CV8 macro cell diagram
ClK
SP
OUTPUT
SELECT
Q
a
AC
INPUT I
FEEDBACK
SELECT
MACRO
CELL
6.6
SP
AC
OE
~ Synchronous Preset
~ Asynchronous Clear
~OutpUI'Enable
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
GOULD
AIMII®Semiconductors
PEEL™ 18CV8
Each of the 8 output enable terms can enable or disable
the output of its associated I/O macro cell. When. the output
enable product term is a logical true (HIGH) the output
signal is enabled to the I/O pin. When it is a logical false
(LOW) the I/O pin is in a high impedance state. The output
enable product terms allow individual I/O pins to be input
only or bi-direction I/O.
Figure 5. PEEL 18CV8 macro cell configuration equivalent circuits
REGISTERED OUTPUT
COMBINATORIAL OUTPUT
o~
S<
~m
c:,-
-<0
:!;
6.7
-) GOULD
AIMII®Semiconductors
PEEC 18CV8
M
Applications of the PEEL 18CV8
made or an upgrade is necessary, the changes can simply
be reprogrammed.
Similar· to SSI/MSI logic, PALs and low density gate
arrays, applications of the PEEL 1SCVS cover all the primary areas of system deSign including, data processing,
communications, industrial, consumer, military and transportation. Specific functions implemented using the PEEL
1SCVS range from basic logic and system support circuitry
to stand-alone controllers. Some of these applications possibilities include:
• SSI/MSI Logic Replacement/Customization
Random logic
Decoders/encoders
Comparators
Multiplexers
Counters
Shift registers
• Processor System Support
Address decoding
Wait-state generation
Memory protection
.
Memory refresh
DMAcontrol
Interrupt control
Timer/Counter functions
Bus arbitration and interface
Error detection and correction
• I/O Interface and Support
Intelligent I/O port
Data Comm interface
Display interface
Keyboard scanning
Disk and tape drive control
Front panel interface
• Stand-Alone Non JLP Based Controllers
Motor control
Sensor monitoring
Security access control
Display Control
The versatility of the PEEL makes it an effective
alternative to conventional methods of logic design over
a broad range of applications.
As an SSI/MSI logic replacement, the PEEL enhances
the design process with increased flexibility, higher· performance, faster development time and design security.
Manufacturing benefits are also realized by requiring
fewer components and interconnects resulting in more
efficient use of space, simplified inventory control and
higher reliability.
As a bipolar PAL replacement, the PEEL has comparable speed yet offers several advantages including: enhanced design flexibility, simplified inventory control,
reduced power consumption, reprogrammability, and
100% factory testability for function and programming.
Design flexibility is of particular importance since the
PEEL 1SCVS not only emulates the majority of the 20 pin
PAL devices (see table 2) but also allows functions found
among several PAL device types to be combined. In addition, completely new functions, not supported by the standard PAL devices, can be implemented. This flexibility
means a designer can focus on the design rather than on
the restrictions of a fixed architecture. Reprogrammability
is also a key benefit over one time programmable PALs.
This feature adds convenience and cost savings in development prototyping and field retrofitting of systems. Converting existing PAL designs to the PEEL 1SCVS for plugin replacement is easily accomplished using the PEEL
evaluation or development tools described later in this data
sheet.
As a design alternative to low-density gate arrays, one
or more PEEL 1SCVSs offer a cost-effective and low-risk
option. With its architectural flexibility and equivalent gate
density of approximately 300 gates, designs traditionally
employing low-density gate arrays can be implemented
quickly at no factory development (NRE) cost. Unlike the
lead times encountered with gate arrays, the PEEL 1SCVS
is off-the-shelf available. Futhermore, if a design error is
Table 2. PLD devices that can be emulated by the PEEL 18CV8
20-pin PAL
Part Number and I/O Capacity
Output Type
Combinatorial-High
Combinatorial-Low
CombinatorialCPolarity
Registered-Low
Registered-Polarity
10H8
10L8
12H6
12L6
14H4
14L4
16H2
16L2
16R4
16RP4
ALTERA
I
EP 300/310
6.S
16R6
16RP6
16H8
16L8
16P8
16R8
16RP8
16HD8
16LD8
18P8
->
GOULD
AIMII®Semiconductors
PEEC 18CV8
M
Absolute Maximum Ratings"8
Symbol
Parameter
Conditions
MIN
MAX
Vee
V,
Supply Voltage
-.5
7.0
Voltage applied to Inpu(lO
relative to GNO
relative to GNO'l.2
-.5
7.0
Va
Voltage applied to Output
relative to GNO'l.2
-.5
10
Output Current
per pin (loL,loH)
TST
Storage Temperature
TLT
Lead Temperature
-65
(soldering 10 seconds)
UNIT
7.0
V
V
V
±25
mA
+125
°C
+300
°C
UNIT
Operating Ranges
Symbol
Parameter
Conditions
MIN
MAX
Vee
Supply Voltage
Commercial
4.75
5.25
V
TA
Operating Temperature
Commercial
0
+70
°C
TR
Clock Rise Time
'5
500
nS
TF
TRvee
Clock Fall Time
'5
500
Vee Rise Time
'5
10
nS
mS
D.C. Characteristics (Over Operating Range Specifications)
Symbol
Parameter
Conditions
Ices
Vco Current Standby
Vee Current Active
V'N=V L or V'H"
V'N=V L or Vo<, All
leeA
MIN
TYP'7
MAX
UNIT
12
25
mA
Iccs +
,7 mA/MHz
mA
inputs, feedback and I/O
switching. "
III
Input Leakage
V'N=GNO to Vee
±10
uA
loz
Output Leakage
I/O = High Impedance,
Vo=GNO to Vee
±10
uA
VIL
Input Low Voltage
-0.3
.8
V'H
VOL
VOLe
VOH
VoHe
Input High Voltage
2.0
V
V
V
V
V
V
Output Low Voltage
IOL = +8.0mA
Output Low Voltage CMOS
10L =101'A
Output High Voltage TIL
IOH=-4.0mA
Output High Voltage CMOS
IOH=-10I'A
Vee+ 0.3
.45
'12
0.1V
2.4
Vee- O.W
Capacitance "3
Symbol
Parameter
TYP
MAX
UNIT
C'N
COUT
Input Capacitance
f=1MHz
4
6
pf
Output Capacitance
f=1MHz
8
12
pI
CeLK
Clock Pin Capacitance
1=1MHz
8
13
pI
Conditions
6,9
MIN
GOULD
AIMII®Semiconductors
PEEL 18CV8
M
A.C. Switching Waveforms
Combinatorial
Input, 1/0
, or Feedbac~
Combinatorial
Output
Output Enable
Input to Output
Enable Term
Registered or
Combinatorial Output
Registered
. Clock
Input to Product or
Sync. Preset Term
Registered
Output
tC02~
Combinatorial Output
(From Registered Feedback)
Input to Async.
Clear Term
Registered
Outputs
~=======================~ ~VALiD
OUTPUT
-f.~
~_r~~=AL=ID==O=UT=P=UT===============~
_________________
:Power-Up Reset
Registered Output
--1;.~~tRESET===1 /~_
_
RESET STATE ~ VALID OUTPUT VIA CLOCK
6.10
GOULD
AIMII®Semiconductors
PEECM 18CV8
A.C. Characteristics (Over Operating Range Specifications)
1SCVS-25
1SCVS-35
1SCVS-50
Symbol
Parameter
tpD
Input"' to combinatorial output
100
Input"4 to output disable
tOE
Input"' output enable
tse
Input"' set·up to clock
20
30
32
nS
tHe
Input"' hold after clock
0
0
0
nS
teL
Clock low time
'5
15
15
20
nS
teH
Clock high time
'5
15
15
20
teal
Clock to output
15
20
28
nS
tC02
Clock to combinatorial output
delay via registered feedback
35
50
70
nS
tCP1
Minimum clock period
(register feedback to register
output via internal path)
30
45
42
nS
Conditions
fMAx1
Max. frequency (1/t ep1 )
tep2
Minimum clock period (tse
fMAx2
Max. frequency (1/ted
MAX
MIN
MAX
UNIT
50
nS
'6
25
35
50
nS
'6
25
35
50
nS
35.3
22.2
35
'11
20
25
'5
A.C. Equvialent load Circuit
nS
MHz
23.8
50
2S.5
Power·on reset time for
registers in clear state
~
MIN
35
Input"' to async. clear
r
MAX
25
+ tco ,)
Async. clear pulse width
tAP
MIN
60
16.6
50
35
nS
MHz
nS
30
40
55
nS
5
5
5
uS
A.C. Testing Input/Output Waveform
3.0Y
51
D.DY
~
~
NORMAL
~~_T.c:E~5T,-,-PO:.:.IN~T-=-5_ _~
Rl
OUTPUT
UNDER
TEST
1-+---1
f--~
Cl
I
A.C. Test Point flood Circuit Table
TEST POINT
R2
-~
TTL Levels
R1 ~ 464~
R2 ~ 250~
CMOS Levels
R1 ~ 480K~
R2 ~ 480K~
AC TEST
TEST POINT
Cl
51
NORMAL
1.5Y
3Dp!
closed
tOE(Z+I)
YOH
3Dp!
open
tOE(Z+O)
VOl
3Dp!
closed
tOD(l+Z)
YOH-.5Y
Sp!
open
tOD(D+Z)
YOl+.5Y
5p!
closed
Z=HIgh Impedance
Notes
Exposure to absolute maximum ratings over extended periods
of time may affect device reliability. Exceeding absolute maximum ratings may cause permanent damage.
'9 110 pins are open (no load).
'm V ,N specified is not for program/verify operation. Contact Gould
for information regarding PEEL 18CVS program/verify
specifications.
'11 Minimum width required to ensure proper asynchronous clear
operation and does not imply rejection of signal less than this
value.
'12 Contact factory for increased 10l requirements.
'8
., Minimum DC input is - .5V, however, inputs may undershoot
to - 2.0V for periods less than 20ns.
'2 Voltage applied to input or output must not exceed Vee + 1.0V.
., These measurements are periodically sample tested.
'4 "Input" refers to an Input signal.
'5 Test points for Clock and Vee in tR, t F , teL> teH' and tRESET are
referenced at 10% and 90% levels.
'6 See A.C. test paint 1load circuit table for tOE' and too testing.
'7 Typical values and capacitance are measured at Vee = 5.0V
and T A = 25°C.
6.11
-) GOULD
AIMII®Semiconductors
PEEL 18CV8
M
Packaging
20-Pin Plastic
PIN 1 IDENTIFIER
.070 MAX
10
L·270MAXJ
.220MIN
.200 MAX 1----+\
'--_ _---../1
I
II
.012 MAX
.OOB MIN
II
JL 'L~~~~~-J'
6.12
BEND
-+--
15° MAX
CMOS Programmable
Electrically Erasable Logic Device
-} GOULD
AIMII®Semiconductors
Preliminary Data Sheet
PEECM 18CV8-15
Features
-Synchronous preset, asynchronous clear
-Independent output enables
• Advanced CMOS EEPROM Technology
• Application Versatility
-Replaces SSI/MSllogic
-Emulates bipolar PAL' devices and EPLDs
-Simplifies inventory control
-Allows new design possibilities
• Low Power Consumption
-TTL: 90mA standby +0.7mA/MHz max
• High Performance
-tpD =15ns max
-tco =12ns max, tsc =12ns min
• Development/Programmer Support
-PC-based development tools and programmer
support from Gould and third-party manufacturers
• EE Instant Reprogrammability
-100% factory tested
-Cost-effective windowless package
-Erases and programs in seconds
-Adds convenience, reduces field retrofit and
development costs
General Description
The Gould PEEL18CV8-15 is a CMOS Programmable
Electrically Erasable Logic device that provides a
high-performance, low-power, reprogram mable, and
architecturally flexible alternative to early-generation
programmable logic devices (PLDs). Designed in
advanced CMOS EEPROM technology, the performance
of the PEEL18CV8-15 rivals speed parameters of bipolar
PLDs with a dramatic reduction in power consumption.
• Foolproof Design Security
-Prevents unauthorized reading or copying of design
• Architectural Flexibility
-74 product term x 36 input array
-Up to 18 inputs and 8 I/O pins
-Independently configurable I/O macro cells
Block Diagram
Pin Configuration
vee
Input/elK
Input/eLK
Input
I/o
Input
I/O
Input
I/O
Input
Input
I/O
Input
Input
I/O
Input
Input
I/O
Input
I/O
Input
Input
I/O
Input
Input
Input
>r-t-t-t--t=-~-----T-QD
110
l{elK
110
MACROI-l>r-T-r-r-T1--t:::t!=l=====~
I/O
-----=1/0
I'I=I==1==l===~
I/O
liD
I-t-+-+----T4-+-IR---------H>-H---+-f-<~'-<
Outputs:
Combinatorial
------t----\Ir-~____,I/---------------'----~~
>--H>--H-+<+<'-<
Outputs:
. Preliminary Designation
goals or preliminary part evaluation, and are not guaranteed. Gould or an authorized sales representative
should be consulted for current information before using
this product.
The "Preliminary" designation on a Gould data sheet in~ica~es that the ~roduct is not characterized. The specifications are subject to change, are based on design
6.33
CMOS Programmable
Electrically Erasable Logic Device
-) GOULD
AIMII®Semiconductors
Preliminary Data Sheet
Features
• Application Versatility
-Replace random SSI/MSI logic
-Create customized comparators, multiplexers,
encoders, converters, etc.
• Advanced CMOS EEPROM Technology
• Low Power Consumption
- 65mA + 0:5mNMHz max
• Development Support
- Third-party software and programmers
-Gould PEEL Development System with APEEL'M
Logic Assembler
• High Performance
-tPD = 30ns max, tOE = 30ns max
• Architectural Flexibility
-8 inputs and 10 II0s
-Programmable ANDIOR arrays with 42
product terms/20 sum terms
General Description
The Gould PEEL 153 is a CMOS Programmable Electrically Erasable Logic device that provides a highperformance, low-power, reprogram mabie , and
architecturally enhanced alternative to conventional programmable logic devices (PLDs). Designed in advanced
CMOS EEPROM technology, the PEEL153 rivals
speed parameters of comparable bipolar PLDs while
providing a dramatic improvement in active power consumption. The EE-reprogrammability of the PEEL 153
reduces development and field retrofit costs and enhances testability to ensure 100% field programmability
• EE Reprogrammability
-Superior programming and functional yield
-Low cost windowless package
-Erases and programs in seconds
• Replacement for PLS153
-Ten additional product terms
-'-Output-enable terms in OR array
-Signature word
. -"-Foolproof design security
Block Diagram
Pin Diagram
~+
I/O
r-t=t++=1=1R~ I/O
___ JfEEm~I/O
..J
1'0
I
1-t-++-t-t-~'~----~~~------~~~~H va
H"l uo
''''I''-"'
""I~
6.40
r"'l
uo
~
110
-) GOULD
~MII®Semiconductors
PEE~M173
Absolute Maximum Ratings Exposure to absolute maximum ratings over extended periods of time may affect
device reliability. Exceeding absolute maximum ratings may cause permanent damage.
Symbol Parameter
Conditions
Raling
Unit
Vee
Supply Voltage
Relative to GND
-0.6 to +7.0
V
Relative to GND 1
-0.6 to Vec + 0.6
Via
Voltage Applied to Any Pin 8
TA
Ambient Temp, Power Applied
-10 to +S5
V
·C
TST
Storage Temperature
-65 to +150
·C
TlT
Lead Temperature
+300
·C
Soldering 10 Seconds
Operating Ranges
Symbol Parameter
Conditions
Min
Max
Vee
Supply Voltage
Commercial
4.75
5.25
Unit
V
TA
Ambient Temperature
Commercial
0
70
·C
D.C. Electrical Characteristics Over the operating range.
Min
Max
Unit
VIH
Vil
Input HIGH Level
2.0
Vee + 0.3
V
Input LOW Level
-0.3
O.S
V
VOH
Output HIGH Voltage
Vee
Val
Output LOW Voltage
Vee
Il
Input Leakage Current
los
Output Short Circuit Current2
loz
Output Leakage Current
IcesT
Power Supply Current,
Standby, TIL Interface
VIN
IccAT
Power Supply Current,
Active, TIL Interface
VIN = Vil or VIH . All inputs,
feedback, and II0s switching 3 .
Symbol Parameter
Conditions
= Min, 10H = -3.2mA
= Min, 10l = SmA4
Vee = Max, GND ,,; VI ~ Vee
Vee = Max, Va = GND
1/0 = High Impedence
Vee = Max, GND ,,; Va ~ Vce
= Vil or VIH3
6.41
V
2.4
-30
0.5
V
10
",A
-90
rnA
±10
",A
65
rnA
IccST+
O.5mAlMHz
rnA
GOULD
AIMII®Semiconductors
PEEL: 173
M
Capacitance These measurements are periodically sample tested.
Symbol Parameter
Conditions
CIN
Input Capacitance
COUT
Output Capacitance
Min
TA = 25°C
Vee = 5.0V, f = 1kHz
Max
Unit
6
pF
12
pF
A.C. Electrical Characteristics Over the operating ranges.
PEEL173C-30
Symbol Parameter
Min
PEEL173·35
Max
Min
Max
PEEL173C-40
Min
Max
Unit
t PD
Propagation Delay, Input to Output
30
35
40
ns
tOE
Input to Output Enable 6
30
35
40
ns
too
Input to Output Disable 6 .?
30
35
40
ns
Switching Waveforms
~t'~::~ t~D~ t~E~
Inputs
) K Valid Output
Outputs
I\.
Valid Output
Notes:
Test Loads
1. Minimum DC input is -0.5V, however, inputs may undershoot to
-2.0V for periods less than 30ns.
5.0V
Tesl Load7
2. Test one output at a time. Duration of short circuit should not
exceed 1 second.
TTL Interface
R, = 4580
3. All I/O pins open (no load).
R, = 2700
Oulpul
4. Assumes worst-case conditions-all outputs loaded. Val = 0.5V
@ IOl = 15mA with one output loaded.
0--.-----+
CMOS IAlert"e
R, = 4490
R,
5. Test conditions assume: signal transitions of 5ns or less from the
10% and 90% points; timing reference levels of 1.5V (unless
otherwise specified); and test loads shown.
= 4330
6. too and tOE are measured at VOH -O.lV and Val +O.lV.
Thevenln Equivalent
7. Cl includes scope and jig capacitance. too is measured with
Cl = 5pF.
TIL Interface
R, = 1690
VRel
Oulpul 0-----;
30pF
.l
= 1.86V
8. Via specified is not for programlverily operation. Contact Gould for
information regarding PEEL173 program/verily specifications.
CMOS IAlert.ce
R, = 227KO
VRel
= 2.38V
6.42
-} GOULD
AIMII®Semiconductors
PEEL™173
Preliminary Designation
its use. No license is granted under any patents or patent rights of Gould.
The "Preliminary" designation on a Gould data sheet indicates that the product is not characterized. The specifications are subject to change, are based on design
goals or preliminary part evaluation, and are not guaranteed. Gould or an authorized sales representative
should be consulted for current information before using
this product.
Gould's products are not authorized for use as critical
components in life support devices or systems without
the written approval of the president of Gould, Inc. Life
support devices, or systems, are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
Specifications, Patents, and Life Support Policy
Gould reserves the right to make changes in specifications at any time and without notice. The information
furnished by Gould in this publication is believed to be
accurate and reliable. However, no responsibility is
assumed by Gould for its use, nor for any infringements
of patents of other rights of third parties resulting from
6.43
CMOS Programmable
Electrically Erasable Logic Device
-} GOULD
AIMII®Semiconductors
Preliminary Data Sheet
PEEL'M 253
-PC-based software translates existing JEDEC files
to PEEL253 format
Features
• Advanced CMOS E2 PROM Technology
• Architectural and Design Enhancements
-8 dedicated inputs, 10 I/O pins
-Dual programmable logic arrays: AND (36 inputs X
42 product terms) OR (20 sum terms X 42 products)
-Sharing of all 42 product terms
-I/O polarity controls
-Output enable terms in OR array
-Security from unauthorized copying
-Signature word for user specified ID
• Low Power Consumption
-TTL: 65mA+0.5mA/MHz Max
• High Performance
- TPD 30nS Max, TOE 30nS Max
• Reprogrammability
-100% factory tested
-Cost effective window-less package
-Erases and programs in seconds
-Adds convenience, reduces field retrofit and development cost
• Application Versatility
-Replaces random SSI/MSI logic
-Ideal for customized combinatorial functions: comparators, multiplexers, encoders, converters, etc.
• Development/Programmer Support
-Popular third party development tools and stand
alone programmers
-PC based evaluation and development tools from
Gould
General Description
The Gould PEEL'· 253 is a CMOS Programmable
Electrically Erasable Logic device that provides a high
performance, low power, reprogrammable, and architecturally enhanced alternative to conventional programma-
• Plug-in Compatibility
-Signetics PLS 153, ICT 253
Block Diagram
Pin Diagram
>---y-+-+--I-1-l-------------<'\ Valid Output
Notes:
Test Loads
1. Minimum DC input is -0.5V, however, inputs may undershoot to
-2.0V for periods less than 30ns.
5.DV
2. Test one output at a time. Duration of short circuit should not
exceed 1 second.
TTL Interface
R, = 4580
R,
3. All I/O pins open (no load).
= 2700
4. Assumes worst-case conditions-all outputs loaded. Val
@ IOl = 15mA with one output loaded.
CMOS I"tert".
R, = 4490
R, = 4330
=
0.5V
5. Test conditions assume: signal transitions of 5ns or less from the
10% and 90% points; timing reference levels of 1.5V (unless
otherwise specified); and test loads shown.
6. too and tOE are measured at VOH -0.1V and Val +O.1V.
Thevenin Equivalent
7. Cl includes scope and jig capacitance. too is measured with
Cl = 5pF.
TIL Interface
RL = 1690
VRel = 1.86V
Output
0--------4
30pF
.I
8. Via specified is not for program/verify operation. Contact Gould for
information regarding PEEL253 program/verify specifications.
CMOS Interface
RL = 227KO
VRel = 2.38V
6.47
-} GOULD
AIMII®Semiconductors
PEEL:"M 253
Preliminary Designation
its use. No license is granted under any patents or patent rights of Gould .
. The "Preliminary" designation on a Gould data sheet indicates that the product is not characterized. The specifications are subject to change, are based on design
goals or preliminary part evaluation, and are not guaranteed. Gould or an authorized sales representative
should be consulted for current information before using
this product.
Gould's products are not authorized for use as critical
components in life support devices or systems without
the written approval of the president of Gould, Inc. Life
support devices, or systems, are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life and whose failure to
perform, when properly used in accordance with in. structions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
Specifications; Patents, and Life Support Policy
Gould reserves the right to make changes in specifications at any time and without notice. The information
furnished by Gould in this publication is believed to be
accurate and reliable. However, no responsibility is
assumed by Gould for its use, nor for any infringements
of patents of other rights of third parties resulting from
6.48
CMOS Programmable
Electrically Erasable logic Device
-) GOULD
AIMII®Semiconductors
Preliminary Data Sheet
PEEL:M 273
-PC-based software translates existing JEDEC files
to 273 format
Features
• Advanced CMOS
E2 PROM
Technology
• Architectural and Design Enhancements .
-12 dedicated inputs, 10 1/0 pins
-Dual programmable logic arrays: AND (44 inputs X
44 product terms) OR (20 sum terms X 42 products)
-Sharing of all 42 product terms
-1/0 polarity controls·
-Output enable terms in OR array
-Security from unauthorized copying
-Signature word for user specified 10
• Low Power Consumption
-TTL: 65mA+0.5mA/MHz Max
• High Performance
- T PD 30nS Max, TOE 30nS Max
• Reprogrammability
-100% factory tested
-Cost effective window-less package
-Erases and programs in seconds
-Adds convenience, reduces field retrofit and development cost
• Development/Programmer Support
-Popular third party development tools and stand
alone programmers
-PC based evaluation and development tools from
Gould
• Plug-in Compatibility
-Signetics PLS 173, ICT 273
• Application Versatility
-Replaces random SSIIMSI logic
-Ideal for customized combinatorial functions: comparators, multiplexers, encoders, converters, etc.
General Description
The Gould PEEL'· 273 is a CMOS Programmable
Electrically Erasable Logic device that provides a high
performance, low power, reprogram mable, and architecturally enhanced alternative to conventional programma-
Block Diagram
Pin Diagram
lFEEE~~'/O
110
~-+-------'
~L:;:;====:.J
I/O
IFE=EEE'/O
HH-t--I--t-+----<'"
,
II-jl=t=t~
®= Polarity Control
a
1
6.49
=
=
Non Inverted
Inverted
110
110
110
1/0
110
110
Pin Names
I
I/O
GND
Vee
=
=
=
=
Input Only
Bi-Direetionallnput/Output
Ground
Power Supply (+ 5V)
-} GOULD
AIMII®Semiconductors
PEEL'M 273
82S173) plus several architectural enhancements including: output enable terms in the "OR" array, 10 additional
general purpose product terms, security from unauthorized copying of designs, and signature word for user
specified device identification. Applications of the
PEEL 273 include replacement of random SSI/MSI
logic circuitry, and a wide range of combinatorial logic
functions, such as priority encoders, comparators, parity
generators, code converters, address decoders, and
multiplexers. Development and programming for the
PEEL 273 is supported by popular development
tools and programmers from third-party manufacturers,
plus PC-based PEEL Development System from Gould.
ble logic devices (PLDs). Designed in advanced CMOS
E2 PROM technology, the PEEL 273 rivals speed
parameters of comparable bipolar PLDs with a sUbstantial improvement in power consumption. The E2
reprogrammability of the PEEL273 not only
reduces development and field retrofit costs but enhances testability ensuring 100% field programmability
and function. Additionally, the PEEL 273 technology
allows for cost effective "window-less" packaging in a
24-pin 300-mil DIP.
Providing both programmable "AND" and programmable
"OR" arrays, the PEEL 273 offers functional compatibility to the Signetics PLS173 (previously numbered
PEEL273 Logic Array Diagram
ProductTerms(0-41)
41393735333\ 2927252321,g 171513 11 9
7
5
3
1
'03638343230282624_2220.'816141210864
2
0
I[DI
[II[II'4'
10-
'"
'6'
lIT}-
[III[II-
"""
""
""
""
"
!ill
lIE\@}-
"
"
"
""
""
.""
"
"
""" ;=
~
"""
t- 3
""53
,
04
os
"
",
58
59
60
63
6.50
>--' F"'-ri
-EI
I/O
~
I/O
21
I/O
--@i
I/O
~
-@
-@
~
~
"
I/O
I/O
I/O
I/O
I/O
I/O
->
GOULD
AIMII®Semiconductors
PEEL'M 273
Absolute Maximum Ratings Exposure to absolute maximum ratings over extended periods of time may affect
device reliability. Exceeding absolute maximum ratings may cause permanent damage.
Symbol Parameter
Rating
Unit
Vee
VIO
Supply Voltage
Relative to GND
Conditions
-0.6 to + 7.0
V
Voltage Applied to Any Pin 8
Relative to GND 1
-0.6 to Vec + 0.6
V
TA
Ambient Temp. Power Applied
-10to +B5
'C
TST
Storage Temperature
-65 to +150
'C
TlT
Lead Temperature
+300
'C
Soldering 10 Seconds
Operating Ranges
Symbol Parameter
Conditions
Min
Max
Vee
Supply Voltage
Commercial
4.75
5.25
Unit
V
TA
Ambient Temperature
Commercial
0
70
'C
D.C. Electrical Characteristics Over the operating range.
Min
Max
Unit
VIH
Vil
Symbol Parameter
Input HIGH Level
2.0
Vee + 0.3
V
Input LOW Level
-0.3
O.B
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Vee = Min, 10l = BmA4
0.5
V
Il
Input Leakage Current
Vee = Max, GND .;; VI .;; Vee
10
los
Output Short Circuit Current 2
Vee = Max, Vo = GND
-90
f.1A
mA
loz
Output Leakage Current
110 = High Impedence
Vee = Max, GND .;; Vo .;; Vee
:,:10
f.1A
leesT
Power Supply Current,
Standby, TIL Interface
VIN = Vil or VIH 3
65
mA
leeAT
Power Supply Current,
Active, TIL Interface
VIN = Vil or VIH . All inputs,
feedback, and 1105 switching 3 .
Iccsr+
o.5mA/MHz
mA
Conditions
Vee = Min, 10H = -3.2mA
6.51
-30
V
V
2.4
GOULD
AIMII®Semiconductors
PEELTM 273
Capacitance These measurements are periodically sample tested.
Symbol Parameter
Conditions
CIN
Input Capacitance
COUT
Output Capacitance
Vee
Min
TA = 25'C
= 5.0V, f = 1kHz
Max
Unit
6
pF
12
pF
A.C. Electrical Characteristics Over the operating ranges.
273-30
Symbol Parameter
Min
273-40
273-35
Max
Min
Min
Max
Max
Unit
tpo
Propagation Delay, Input to Output
30
35
40
ns
tOE
Input to Output Enable 6
30
35
40
ns
too
Input to Output Disable 6 .7
30
35
40
ns
Switching Waveforms
t',::~ t,oo; t~E~
Inputs
) K Valid Output
Outputs
"-
.7 Valid Output
~
Noles:
Test Loads
1. Minimum DC input is -O.SV, however, inputs may undershoot to
-2.0V for periods less than 30ns. '
5.0V
Test load7
TIL Interface
R, = 458n
R, = 270n
Output
0--.---4
CMOS Interlace
R, = 449n
R, = 433n
2. Test one output at a time. Duration of short circuit should not
exceed 1 second.
3. All 1/0 pins open (no load).
4. Assumes worst-case conditions-all outputs loaded. VOL
= O.SV
@ IOL = 15mA with one output loaded.
S. Test conditions assume:' signal transitions of 5ns or less from the
10% and 90% points; timing reference levels of 1.5V (unless
otherwise specified); and test loads shown.
6. tOD and tOE are measured at VOH -0.1V and VOL +0.1V.
Thevenin Equivalent
TIllnlerface
RL = 169n
VRel = 1.S6V
HL
Output
0------1
30pF
I
7. CL includes scope and jig capacitance. tOD is measured with
CL = SpF.
8. VIO specified is not for programlverify operation. Contact Gould for
information regarding PEEL273 programlverify specifications.
CMOS Interlace
RL = 227KH
VRel = 2.38V
6.52
-} GOULD
AIMII®Semiconductors
PEEL'M 273
Preliminary Designation
its use. No license is granted under any patents or patent rights of Gould.
The "Preliminary" designation on a Gould data sheet indicates that the product is not characterized. The specifications are subject to change, are based on design
goals or preliminary part evaluation, and are not guaranteed. Gould or an authorized sales representative
should be consulted for current information before using
this product.
Gould's products are not authorized for use as critical
components in life support devices or systems without
the written approval of the president of Gould, Inc. Life
support devices, or systems, are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
Specifications, Patents, and Life Support Policy
Gould reserves the right to make changes in specifications at any time and without notice. The information
furnished by Gould in this publication is believed to be
accurate and reliable. However, no responsibility is
assumed by Gould for its use, nor for any infringements
of patents of other rights of third parties resulting from
6.53
-) GOULD
AIMII®Semiconductors
PEEL:M
Development System, PDS
Features
• Development System for PEEL Devices
-Editor, logic assembler, translator programmer, and
tester all in one system
-Runs on PC-compatible computers
• Conventional PLD Programmer Functions
-Program, Load, Verify, Secure
• APEEL '" Boolean Logic Assembler
-Supports all advanced features of PEEL devices
-"PALASM®-like" sum-of-products equations
-'fI,BEL'"-like" macro cell definitions
-Logic simulation
• Translates Standard PLDs to PEEL Devices
-Loads PLD or reads JEDEC file
-Automatically translates to PEEL device
• Built-in File Editor
-Edit source, JEDEC, or test-vector files
• Enhanced Logic-Test Capabilities
-Tests device in socket to JEDEC test vectors
-Special features: single step, loop, capture
• Expandable and Accessible
-New features and devices supported with software
updates
-No copy protection
General Description
The PEEL'M Development System is a powerful, yet inexpensive, PC-based system for designing with PEEL
(Programmable Electrically Erasable Logic) devices.
The PDS is a personal PLD work-station providing
PEEL Development System, PDS
PEEL and APEEl are trademarks of International CMOS Technology, Inc.
6.54
PAL and PALASM are registered trademarks of Monolithic Memories, Inc.
ABEL Is a trademark of DATA lID Corporation.
WordStar is a registered trademark of MicroPro International Corporation.
PEEL
Development System, PDS
-} GOULD
AIMII®Semiconductors
everything needed to implement your logic designs from
concept to silicon. Several options for designing with
PEEL devices are available with the PDS. For example,
an existing PLD design (Le., a PAL® or EPLD JEDEC
file) can be automatically translated and programmed
into a PEEL device. Additionally, the translation capability allows you to use your present PLD logic assembler
or compiler to design with PEEL devices.
To fully support the advanced features of PEEL
devices, the PDS also provides the tools needed to
design from start to finish, including a built-in word
processor for design entry and editing, the APEEL '"
boolean-logic assembler, a complete PEEL-device
programmer and enhanced logic tester.
The PEEL Development System provides an editor,
logic assembler, translator, programmer, and tester
all in one integrated package.
The capabilities of the software-controlled programmer
will be expanded as new devices are released by
Gould. Registered owners are enrolled in the Gould
software update service and receive programmer/
development-software updates.
SYSTEM CONTENTS
Software
o PEEL Development System Software
(on 5 1/4" 360K diskettes)
Hardware
e PEEL-device-programmer module with ribbon-cable
connector
o PEEL-device programmer card
COl Sample PEEL 18CV8 devices
Literature
PEEL Development System Manual
PEEL-device data sheets
Gould license agreement and warranty
Gould warranty/update registration card
Existing PLDs (i.e., PAL or EPLD) can be translated
and programmed to a PEEL device
•
..
•
•
SYSTEM REQUIREMENTS
•
•
•
e
tl
IBM-PC/XT/AT or compatible computer
Minimum 256K RAM memory
Monochrome or color display
Two 360K floppy-disk drives or one floppy-disk drive
and a hard disk
DOS version 2.1 or greater
For more information contact:
-Gould Inc., Semiconductor Division
2300 Buckskin Rd.
Pocatello, ID 83201
(208) 233-4690
Built-in file editor with "WordStar®-like" commands
allows design entry for APEEL source, test-vector,
and formatted JEDEC files.
6.55
PDS00189
-} GOULD
AIMII®semiconductors
Static CMOS &
NMOS ROMs
Static CMOS & NMOS
Family of ROMs
-} GOULD
AIMII®Semiconductors
Features
• 16K, 32K, 64K, 128K, 256K, 512K, 1 Meg Selections
• Fast Access Time
• Mate With State Of The Art 32 Bit Microprocessors
o Low Standby Power CMOS
• Fully Static Operation
o Single +5V ±10% Power Supply
• Directly TTL Compatible For Clean Interface
o Three-State TTL Compatible Outputs
• EPROM Pin Compatible
• Late Mask Programmable For Quick Turn Times
• Programmable Output/Chip Enable
General Description
The Gould AMI family of ROMs are static mask programmable and organized by 8 bits. The device is fully
TTL compatible on all inputs and outputs and uses a
single +5V power supply. There are no requirements
for clocks or refreshing, because they are static in
operation. The three state outputs facilitate memory
expansion by allowing the outputs to be OR-tied to other
devices. OEICE active level inputs and the memory
contents are user defined.
Block Diagram
Logic Symbol
·OEfCE ·0f'CE
A,
A,
A.
A,
Au
_
_
_
_
AI1 _
ADDRESS
DECODER
DRIVER
f--+-
Ao
A, A,
A,
A4
As
A,
A,
A. A, A1O -
BIT ARRAY
Au _
A'l Au _
A'5 _
t
t
A,
A,
A,
A,
A.
A,
_
_
_
_
_
_
ADDRESS
DECODER
DRIVER
A13 -
110
CIRCUITS
A14 -
A15 -
t
f·
POWER
DOWN
·OEfCE -
CHIP
ENABLE
DECODER-
·OE/CE-
00
0,
0,
0,
04
Os
0,
0,
Au A12 -
COLUMN
r-- -1-+
-
~
~
Pin Names
OUTPUT
BUFFERS
I
I
I
Ao-A15
00-0 7
11""11
DEICE
Vee; GND; NC
00 0, O2 Qa 04 05 06 07
• THE USER DECIDES BETWEEN AN DE OR CE FUNCTION AND
THEN DEFINES THE ACTIVE LEVEL FOR DEICE
7.3
Address Inputs
Data Outputs
Output Enable/Chip Enable
5V; Ground; No Contact
-) GOULD
AIMII®Semiconductors
Static CMOS & NMOS Family of ROMs
Table 1.
Device Name
Process
Capacity
Organization
Compatible EPROM
Number of Pins
Plastic Dip Package Available
Ceramic Dip Package Available
SOIC Plastic Package Available
Temperature Range: C/I/M; 0 to 70'C/-40 to
85'C/-55 to 125'C
Electrical Characteristics: Vee
= +5V
Symbol Parameter
Val
Vah
lah
Vii
Vih
ILi
ILa
Icc1
Icc2
Isb1
Isb2
tM
tACE
tOE
tCEO
tOEO
tOH
Output LOW Voltage (ial=3.2mA)
Output HIGH Voltage
Output HIGH Current
Input LOW Voltage
Input HIGH Voltage
Input Leakage Current
Output Leakage Current
Power Supply Current-TIL Active
Power Supply Current-CMOS Active
Power Supply Current-TIL
Power Supply Current-CMOS
Address Access Time-Commercial Temp.
Industrial Temp.
Mil Temp.
Chip Enable Access Time
Industrial Temp.
Mil Temp.
Output Enable Access Time
Industrial Temp.
Mil Temp.
Disable Time From Chip Enable
Industrial Temp.
Mil Temp.
Disable Time From Output Enable (Note 5)
Industrial Temp.
Mil Temp.
Output Hold Time
Industrial Temp.
Mil Temp.
S6316
CMOS
16K
2K x 8
2516
24
YES
YES
NO
S6333/S63332
CMOS
32K
4K x 8
2732/2532
24 (A)/24 (8)
YES
YES
NO
S63364
CMOS
64K
8K x 8
68764
24
YES
YES
NO
C/I/M
CIIIM
C/I/M
±10%
Units Min.
V
V
V
V
fl.A
fl.A
mA
mA
mA
fl.A
ns
ns
ns
ns
ns
ns
Max.
Min.
2.4
Max.
2.4
-1.0 mA
-0.3
0.8
2.2 Vcc + 0.3
-1
1
-10
10
40
Note 3
Note 4
35
Note 5
2
Note 6
100
100/120
150
175
100/120
150
175
70
75
80
0
50
0
65
70
0
0
50
0
65
0
70
0
0
0
Notes
1. NMOS Power Test: Vee=Veemax; OEICE=Active; Address inputs @ Vii
2. NMOS Standby Power Test: Same as Note 1 except CE=Deselected
3. CMOS Power Test: TR=150ns, duty=100%
4. CMOS Active Test: TR=150ns, duty=100%, Vj=Gnd or Vee
5. Deselect Power Test: Chip in Standby Mode, Vj=ViI or Vjh
6. Standby Power Test: Chip in Standby Mode, Vj=Gnd or Vee
7. In Notes 1 through 6 the Output Loads are Disconnected.
*
Package under development
7.4
Min.
0.4
0.4
-1.0 mA
-0.3
0.8
2.2 Vcc + 0.3
-1
1
-10
10
Note 3
40
Note 4
35
Note 5
2
Note 6
100
100/120
150
175
100/120
150
175
70
75
80
0
50
0
65
0
70
0
50
0
65
70
0
0
0
0
Max.
0.4
2.4
-1.0 mA
-0.3
0.8
2.2 Vcc + 0.3
-1
1
-10
10
Note 3
40
Note 4
35
Note 5
2
Note 6
100
100/120
150
175
100/120
150
175
70
75
80
50
0
65
0
70
0
50
0
0
65
70
0
0
0
0
GOULD
AIMII®Semiconductors
Static CMOS & NMOS Family of ROMs
Table 1. (continued)
Preliminary
Device Name
Process
Capacity
Organization
Compatible EPROM
Number of Pins
Plastic Dip Package Available
Ceramic Dip Package Available
SOIC Plastic Package Available
PLCC Package Available
Temp Range: C/I/M; 0 to 70"C/-40 to 85"C/-55 to 125"C
Electrical Characteristics: Vee
=
Parameter
Vol
Voh
loh
Vii
Vih
ILi
ILo
Icc1
Icc2
Isb1
Isb2
tM
Output LOW Voltage (iol=3.2mA)
Output HIGH Voltage
Output HIGH Current
Input LOW Voltage
Input HIGH Voltage
Input Leakage Current
Output Leakage Current
Power Supply Current-TIL Active
Power Supply Current-CMOS Active
Power Supply Current-TIL
Power Supply Current-CMOS
Address Access Time-Commercial Temp.
Industrial Temp.
Mil Temp.
Chip Enable Access Time
Industrial Temp.
Mil Temp.
Output Enable Access Time
Industrial Temp.
Mil Temp.
Disable Time From Chip Enable
Industrial Temp.
Mil Temp.
Disable Time From Output Enable (Note 5)
Industrial Temp.
Mil Temp.
Output Hold Time
Industrial Temp.
Mil Temp.
tOE
tCEO
tOEO
tOH
S23128
NMOS
128K
16K x 8
27128
28
YES
YES
YES
NO
C/IiM
S631000/S631001
CMOS
1 Meg
128Kx8
27011/27010
28/32
YES
YES
NO
YES
C/I/M
S63512
CMOS
512K
64K x 8
27512
28
YES
NO
NO
YES
Cll/Mt
S63256
CMOS
256K
32K x 8
27256
28
YES
YES
YES
YES
C/I/M
+5V ±10%
Symbol
tACE
S6364
CMOS
64K
8K x 8
2764
28
YES
YES
YES
YES
C/I/M
Units Min.
V
V
V
V
IJ.A
IJ.A
mA
mA
mA
IJ.A
ns
ns
ns
ns
ns
ns
Max.
Min.
0.4
2.4
Max.
0.4
Noles
I. NMOS Power Test: Vee~Veemax; OE/CE~Active; Address inputs @ Vii
2. NMOS Standby Power Test: Same as Note 1 except CE~Deselected
3. CMOS Power Test: TR~150ns, duty~IOO%
4. CMOS Active Test: TR~150ns, duty~IOO%, Vi~Gnd or Vee
5. Deselect Power Test: Chip in Standby Mode, Vi~ViI or Vih
6. Standby Power Test: Chip in Standby Mode. Vi~Gnd or Vee
7. In Notes 1 through 6 the Output Loads are Disconnected.
t Package under development
7.5
-220
-0.5
2.0
-10
-10
Note 1
IJ.A
0.8
Vcc
10
10
80
Note 2
20
0
0
0
0
0
0
0
0
0
250
280
300
250
280
300
80
115
120
80
115
120
80
115
120
Max.
Min.
Max.
Min.
Max.
0.4
2.4
-1.0 mA
-1.0mA
-1.0 mA
-0.3
-0.3
0.8
0.8
-0.3
0.8
2.2 Vcc + 0.3 2.2 Vcc + 0.3 2.2 Vcc+0.3
-1
-1
1
1
-1
1
-10
-10
10
10
-10
10
Note 3
Note 3
40
50
50
Note 3
Note 4
45
Note 4
35
Note 4
45
Note 5
2
Note 5
2
Note 5
2
Note 6
Note 6
150
100
Note 6
150
120/150
150/200
150
175
200
175
250
200
200
150/200
120/150
150
200
175
175
250
200
200
70
80
80
75
85
90
80
90
100
0
0
50
60
70
0
0
0
65
75
80
0
0
70
0
80
90
0
0
0
50
0
60
70
0
0
65
75
0
80
0
0
70
80
90
0
0
0
0
0
0
0
0
0
0
0.4
2.4
2.4
-1.0 mA
-0.3
0.8
2.2 VCC + 0.3
-1
1
-10
10
Note 3
40
Note 4
35
Note 5
2
Note 6
100
100/120
150
175
1001120
150
175
70
75
80
0
50
0
65
0
70
0
50
0
65
0
70
0
0
0
Min.
0.4
2.4
I
-} GOULD
AIMII®Semiconductors
Static CMOS & NMOS Family of ROMs
Capacitance: TA = 25°C, f = 1.0 MHz
Symbol
Parameter
CIN
Input CapaCitance
COUT
Output Capacitance
Minimum
Maximum
Units
7
10
pF
pF
Conditions
VIN = OV
VOUT = OV
Figure 1
,---.
TEST COMPARATOR
AC TEST CONDITIONS:
INPUT PULSE LEVEL:
O.OV TO 3.0V (CMOS)
0.8V AND 2.0V (NMOS)
INPUT RISE AND FALL TIMES:
INPUT TIMING LEVEL:
OUTPUT TIMING LEVEL:
OUTPUT LOAD:
I
OUT
Cl = 100pF
10ns
1.5V
1.5V
See Figure 1
I
\ r - - - - Vl = 1.92V (CMOS)
Rl = 4760 (CMOS) Vl = 2.27V (NMOS)
Rl = 5850 (NMOS)
Cl = CSTRAY + CTEST FIXTURE + CCAP
Application of Gould ROMs
Flexibility on Control Line Programming
All of the ROMs offered by Gould are fully static, asynchronous, non-multiplexed devices. No matter what
microprocessor you're using in your system, careful
planning will give you the greatest flexibility in using
our ever-expanding family of ROMs.
You can use the programmable control functions to
your best advantage. Let's take the 86364 as an example. If four 86364s are used in a system, pin 22 on
each device could be a common OE signal for a master
tristate control; pin 20 on each device could be a master powerdown control; and pins 26 and 27 could serve
as 1-of-4 addressing to select which of four ROMs is
active.
No Clocks Are Required
A clock is not required by our ROMs to latch addresses, precharge internal circuitry, or perform any
other function. All control lines (CE, or OE) may
remain in a valid read state for an indefinite period of
time, during which the address inputs may be changed
as desired to access various stored data.
Another possibility would be to use all four control
lines on the 86364 as higher order addresses. While
the data sheet may show different labels on these pins
to conform with common industry practice, all control
lines on the 86364 can in reality be programmed with
equal flexibility. Taking advantage of this, sixteen 86364
devices can be addressed from four control lines.
These control lines can be all powerdown, all nonpowerdown, or any combination. With this approach, a
later system evolution to higher density ROMs means
that the correct signals are already in place for both
addressing and bus control.
The Address Inputs Must Be Valid for the
Entire Cycle
The addresses must be held constant to a Gould ROM
until the output data has been placed onto the system
data bus and read by the microprocessor or a peripheral device. If the microprocessor is one of several
common types using a multiplexed address/data bus,
the system design must incorporate latches to extract
address information from this bus and supply the
latched addresses to our ROM.
7.6
-) GOULD
AIMII®Semiconductors
Static CMOS & NMOS Family of ROMs
AC Timing Diagram
ADDRESS TO OUTPUT DELAY (OUTPUT ENABLED)
ADDRESS
INPUTS
DATA
OUTPUTS
OUTPUT ENABLE TO OUTPUT DELAY
(ADDRESS VALIDIOUTPUT ENABLED
OUTPUT
ENABLE
VALID ENABLE
tOE
DATA
OUTPUTS
-
Hi-Z
------<1
CHIP ENABLE/OUTPUT ENABLE TO OUTPUT DELAY (ADDRESS VALID)
CHIP
ENABLE
OUTPUT
ENABLE
DATA
OUTPUTS
7.7
-) GOUL[]
AIMII®Semiconductors
Static CMOS & NMOS Family of ROMs
Figure 1. Example of minimum configuration for a Gould ROM and a microprocessor using a
non-multiplexed address bus.
CPU
20
CEIOE
A15
~
AO-A14
00-07
RO
~
AO·A14
563256
00-07
22
OE
Figure 2. Example of a minimum configuration for a system using a multiplexed address/data bus.
ALE
~
r
CPU
CLK
OCTAL
LATCH
DE
-
ADO·AD7
.R
AO·A7
~
QO·Q7
56364
"-
A8·A15
/
27 v
RD
7.S
A8·A12, Control
Pins 20, 22, 26
DE
-) GOULD
AIMII®Semiconductors
Static CMOS & NMOS Family of ROMs
Powerdown or Not: It's Up to You
Finally, you have the option on most of our ROMs to
choose whether or not to incorporate powerdown or
standby capability. The key is in the control line programming that you specify when the order is placed.
Any pin specified as a Chip Enable, either high or low,
can place the device into a powerdown mode as well
as place all outputs in a tristate condition. In powerdown, or standby, the device draws much less current
than in the active mode.
the only difference in the two options. Because of the
differences in internal circuitry being controlled, a CE
pin has relatively long access time, perhaps 250ns,
compared to a OE pin, perhaps 80ns. Therefore,
system timing requirements must be evaluated
when weighing the relative merits of programming
for powerdown.
Another item to consider is printed circuit (PC) board
layout. A powerdown device has a noticeable change in
power supply current when it is switched into the active
mode. Careful PC board layout and power supply decoupling will prevent the introduction of noise into
your system. This noise is due to the interaction of
the change in current and the inherent inductance of
PC board wiring traces.
If, instead a pin is programmed as Output Enable, that
pin controls only the output mode (active or tristate);
device current is relatively constant. All Gould ROMs
which provide powerdown capability allow you to choose
your own combination of CE and OE. For example, the
823128 can be programmed with three CE functions, or
one CE and two OE, etc.
Note that a device whose outputs are switched to the
active state by a OE pin will not exhibit this change in
power supply current, however, power supply decoupiing is still recommended. A device which is simply in
an output tristate mode and not in powerdown shows
little difference in current compared to the active mode.
When you are making a decision between CE and OE
programming, note that standby current is not
Table 2. Control Lin,e Options
AMI ROMs offer you the choice of control line functions as well as the active level. The possible functions and active level for each pin are shown
below (a "bar" above the function name means active low).
CE Function = Power Down
OE Function = Non Power Down, tristate output control only
DC
= Don't Care (Control pins programmed as DC have no effect on either the powerdown mode or tristate control but are still connected
to input protection devices.)
2K x 8 (16K) 24 Pin S6316 CMOS
Pins 2l-0E, DE, CE, CE, DC
2D-OE, DE, CE, CE, DC
l8-0E, DE, CE, CE, DC
4K x 8 (32K) 24 Pin S6333 CMOS
Pins 2D-OE, DE, CE, CE, DC
l8·0E, DE, CE, CE, DC
4K x 8 (32K) 24 Pin S63A332 CMOS
Pins 2D-OE, OE, CE, CE, DC
2l·DE, OE, CE, CE, DC
8K x 8 (64K) 24 Pin S63364 (CMOS)
Pin 20·0E, DE, CE, CE, DC
8K x 8 (64K) 28 Pin S6364 CMOS
Pins 27-0E, DE, CE, CE, DC
26-0E, DE, CE, CE, DC
22-0E, DE, CE, CE, DC
2D-OE, OE, CE, CE, DC
16K x 8 (128K) 28 Pins S23128 NMOS
Pins 27-0E, OE, CE, CE, DC
22-0E, DE, CE, CE, DC
20-0E, DE, CE, CE, DC
32K x 8 (256K) 28 Pin S63256 CMOS
Pins 22-0E, DE, CE, CE, DC
20-0E, OE, CE, CE, DC
7.9
64K x 8 (512K) 28 Pin S63512 CMOS
Pins 22-0E, OE, CE, CE, DC
20-0E, DE, CE, CE, DC
128K x 8 (1 MEG) 28 Pin S631000 CMOS
Pin 20-0E, QE, CE, CE, DC
.
128K x 8 (1 MEG) 32 Pin S631001 CMOS
Pins 3l-0E, DE, CE, CE, DC
3D-OE, DE, CE, CE, DC
24-0E, DE, CE, CE, DC
22-0E, DE, CE, CE, DC
I
-} GOULD
AIMII®Semiconductors
Static CMOS & NMOS Family of ROMs
Customer Requirements
Upon your approval of the returned EPROM and receipt
of your purchase order by Gould, masks are generated
for production. Prototypes can be furnished to you upon
request. Depending upon the volume required, production shipments are made within six to eight weeks after
code approval and receipt of the purchase order. Under
the Gould corporate policy, if at any time you wish to
cancel your code, you are liable for all work in process (WIP). For additional information on cancellation
charges, please contact your local Gould sales office.
Truth Table: (For simplicity, all control functions in the
Truth Table are defined as actilYe high).
OE/CE
OEICE
Outputs
Power
CE
X
X
CE
DE
DEICE
DEICE
DEICE
OE
DEICE
HI-Z
HI-Z
HI-Z
HI-Z
DATA DUT
STANDBY
STANDBY
ACTIVE
ACTIVE
ACTIVE
How to Get Your ROMs Fast
ROM Ordering Simplified
The following information should be included in the
purchase order when ROM devices are being ordered:
-Part number
-Quantity of prototypes for each pattern (if any)
- Total quantity of each pattern
-Pricing and delivery (quotes can be obtained from
any Gould AMI sales office)
-Package type (plastic or ceramic)
---:Special marking (if required)
-Access speed
-Required temperature range
Other Programming Requirements
Depending upon the ROM required, you must define the
correct pinout options. Programmable pins are either
chip enable (CE) high or low, don't care (DC), or output
enable (OE) high or low. If a device pin is designated
with a CE function, that pin can put the device into a
powerdown cofldition. If DE function is used for a pin,
that pin cannot control powerdown for the device. If a
device has all control pins designated with DE functions,
it is a non-powerdown device.
If a drawing of your pin configuration is available, it
should be provided at the time of EPROM conversion
along with any special package marking requirements.
Your Access Time Requirements
As a further guarantee that the correct Gould device
type has been specified, the following switching
characteristics. need to be defined by you when the
order is placed.
ROM Code Data
The preferred method of receiving ROM CODE DATA
is by electronic data transmission or in EPROM. For
EPROM ROM CODE DATA submission, two EPROMs
should be submitted. One is programmed to the desired
code and the other is blank. Gould AMI will read the
programmed EPROM, transfer this data to disk and then
program the blank EPROM from the stored information.
This procedure guarantees the the EPROM has been
properly entered into the Gould AMI computer system.
The Gould AMI programmed EPROM is returned to
the customer for verification of the ROM data. Unless
otherwise requested, Gould AMI will not proceed until
the customer has returned the ROM CODE VERIFICATION form.
TAA (Address Access Time)
TACE (Chip Enable Access Time)
TADE (Output Enable Access Time)
For electronic data transmission, contact your Gould
AMI sales office for details.
7.10
-) GOULD
AIMII®Semiconductors
Static CMOS & NMOS Family of ROMs
Logic Symbol 512K
DEICE
Logic Symbol 256K
Pin Configuration 512K
DEICE
DEICE
Pin Configuration 256K
DEICE
I
Ao
A,
A,
A,
A,
A,
A,
A,
A,
A,
AlO
Al1
A12
Au
A14
A15
Ao
A,
A,
A,
A,
A,
A,
A,
A,
A,
AlO
Al1
A12
Au
A14
Uo
U,
U,
U,
U,
U,
U,
0,
Ao
00
0,
0,
GNU
Logic Symbol 128K
Pin Configuration 128K
Vee
A14
Au
A,
A,
Al1
DEICE
AlO
DEICE
U,
U,
Uo
0,
U,
0,
U,
0,
0,
0,
0,
0,
0,
Logic Symbol 64K
Pin Configuration 64K
28 Pin
DEI DEI DEI
CE, eE2 CE3
DEICE, DEICE,
I
Ao
A,
A,
A,
A,
A,
A,
A,
A,
A,
AlO
Al1
A12
Au
00
0,
0,
0,
0,
0,
0,
0,
Vee
DEICE,
Au
A,
A,
Al1
DEICE
A,
Ao
00
U,
U,
GNU
Ao
A,
A,
A,
0,
0,
0,
U,
0,
00
U,
~
0,
A,
A,
A,
A,
A,
AlO
Al1
A12
U,
0,
U,
0,
U,
7.11
00
U,
DEICE
DEICE
NC
A12
A,
A,
A,
A,
A,
A,
A,
Ao
Vee
DEICE,
DEICE,
A,
A,
"A11
DEICE
0,
.) GOULD
AIMII®Semiconductors
Static CMOS & NMOS Family of ROMs
(A)
Logic Symbol 32K
Pin Configuration 64K
Logic Symbol 64K
S6333
24 Pin
CEIDE
AD
A,
A,
A,
A,
A,
A.
A,
A,
A,
AlO
A"
A12
Pin Configuration 32K
OE/CE ·OE/CE
A,
A,
0,
0,
0,
Q,
AlO
O.
0,
0,
0,
A,
0,
A,
A,
A,
Q,
All
OE/CE
0,
A.
0,
0,
A,
Q,
A,
O.
A,
AlO
0,
A"
22
Vee
A,
A,
L-_---I
(8)
Logic Symbol 32K
Logic Symbol 16K
Pin Configuration 32K
Pin Configuration 16K
S63332
OEI OEI OEI
OE/CE OE/CE
CE CE
Ao
A,
A,
A,.,
A.
A,
A,
A,
A,
A,
AlO
A"
A,
A,
A,
A,
A.
A,
A,
A,
A,
A,
AlO
0,
Q,
Q,
0,
O.
0,
O.
0,
OE/CE
AlO
7.12
CE
0,
0,
0,
Q,
O.
0,
O.
0,
A,
A.
A,
A,
A,
A,
A,
A,
0,
7
GOULD
AIMII®Semiconductors
Static CMOS & NMOS Family of ROMs
28 Pin P-Dip
32 Pin P-Dip
32 Pin PLCC
5361001
S631001
5361000
A1S
~
VCC
NC
A12
A7
A.
27
A14
2.
25
A13
Al'
A15
A12
AS
A.
A3
A'
Al
A.
D.
2.
A'
A,
23
A11
,."
Al'
Al'
CPl·
07
21
,.
19
11
16
01
12
17
0'
GNO
13
"
"
15
O'
05
D.
03
~
31
3.
29
A7
A.
AS
A.
A3
A'
Al
A.
DO
01
0'
GNO
26
'7
26
25
,.
,.
VCC
~~~~d~5§
CP'
CP3
"'MC\I"'~;;;:;
Al'
A13
A'
A'
A11
CP'
13
'3
22
21
20
15
19
16
O'
OS
D.
17
03
11
12
,.
"
Al'
CPl
07
A7
A.
AS
A.
A3
A'
Al
AD
DO
29
26
'7
26
25
,.
,.
11
12
13
'3
22
21
"'II)IOI'oCOcnO
... . . . . . . . . . . . . . . . ('1,1
.... C\lQM'"
It)
10
oozoooo
"
CP=OE/CE/DC
7.13
A1'
A13
A'
A.
A11
CP2
Al'
CPl
07
-} GOULD
AMII®Semiconductors
Static CMOS & NMOS Family of ROMs
24-Lead PDIP Outline
24-Lead Ceramic DIP Outline
PIN I IDENTIFIER
PIN 1 IDENTIFIER
11
O.200MAX -
~;.~
T,
lOOM'Nl1
~:~-.~'
020 MIN
''''
0.590
14
"
1.5611 MAX !
.520 MIN
~
200 MAX
J[li
.610 MAX
L
150 MAX
l.560MIN
.012 MAX
.nOB MIN
28-Lead Ceramic
DIP Outline
BEND
'
28-Lead PDIP Outline
--T-;-
PIN 1 IDENTIFIER
I
' ' 1' 0
28-Lead SOIC Outline
t==.1I' MAX~
.099
±.ooa
:~~IIh.104±.ooa
.025 ±.1Kl5 J
...JL~16TYP r - '
.050 TYP
7.14
-} GOULD
AIMII®Semiconductors
Static CMOS & NMOS Family of ROMs
PLCCOutline
.023
.029 830
.042
.048
29
I
lU~"
,.
J L.::o ssc.
DIMENSIONS (INCHES)
NOM.
MAX.
MIN.
.118/.129 DIA. EJECTOR PIN
A
A1
A2
0
01
02
03
E
E1
E2
E3
F1
G1
.123
.078
.106
.485
.449
.390
.585
.549
.490
.441
.541
N
No
NE
C
7.15
.0097
.130
.085
.109
.490
.451
.420
.300 REF .
.590
.551
.520
.400 REF.
.443
.543
32
7
9
.0100
NOTE
.140
.095
.112
.495
.453
.430
3
2
.595
.553
.530
3
2
.445
.545
.0103
9
9
5
-} GOULD
AIMII®Semiconductors
Static CMOS & NMOS Family of ROMs
P·DIP Outline
S
y
M
A
B
C
D
E
F
G
7.16
Dimensions
lead
Count
28
32
1.470
1.655
MAX
.560
.520
.610
.580
.020
MIN
.200
MAX
.070
.050
.020
.015
MAX
.560
.520
.610
.580
.020
MIN
.200
MAX
.040
.060
.020
.015
1M Bit (131,072x8)
Static CMOS Mask ROM
-} GOULD
AIMII®Semiconductors
Preliminary Data Sheet
S631000/S631001
Features
o
•
•
•
•
•
o
•
•
•
•
•
General Description
Fast Access Time:
S631 000-15/S631 001-15-150ns
S631 000-20/S631 001-20-200ns
Fully Static Operation
Low Power Dissipation
Active: 275mW Maximum
Standby: 825J1-W Maximum
Single +5V±10% Power Supply
Directly TTL Compatible Inputs
Three-State TTL Compatible Outputs
Late Mask Programmable
Programmable Chip Select/Enable or
Programmable Output Enable
EPROM Compatible (see table 1)
JEDEC Standard 32 pin dip-S631001
JEDEC Standard 28 pin dip-S631000
32 Lead PLCC package available-S631001
The Gould AMI S631000 device is a 1,048,576 bit static
mask programmable CMOS ROM organized as 131,072
words by 8 bits. The device is fully TTL compatible on all
inputs and outputs and uses a Single +5V power supply.
The three-state outputs facilitate memory expansion by
allowing the outputs to be OR-tied to other devices.
The S631000 is pin compatible with most UV EPROMS,
making system development much easier and more cost
effective. The device is fully static, requiring no clocks for
operation. The four control pins are mask programmable,
with the active level and function for each being specified
by the user. When a chip enable pin is not enabled, the
power supply current is reduced to a 150pA maximum.
Pin Configuration
Logic Symbol
8631001
32 PIN P·DIP
$631001
5631000
28 PIN P·DIP
32 PIN PLCC
Vee
Vee
CP4*
Al'
CPl·
A"
AS
A9
All
A16
Al'
A13
AS
A9
N
~
~
:; :; .:;
n
" ;g
Z
CP2·
I
M
Co
"
n
AD -
A9
All
CP2·
DO
D7
D6
Al
CPl·
AD
AlO
CP1*
D7
D6
Dl
D5
DO
D7
Al0
D'
D3
D5
D.
I
I
I
-- 00
A1 --
Al'
A13
AS
Al0
CP1*
All
CP1 CP2 CP3 CP4
~
"-
U
A2 A3 -
Dl
A4 -
-- 02
AS A6 A7 AS A9 A10 A11A12 A13A14 A15AlB -
-
D3
-
D.
-
D5
-
D6
-
D7
NOTE: CP2, CP3 AND CP4 - $631 001 ONLY
D3
Pin Names
Control Pin Options
AO·A16
Address Inputs
DO· 07
Data Outputs
CP1· CP4
Control Pins
Vee
+5 Volts Supply
GNO
Ground
The user deCides the control pin function and then defines the active level. The
funchon may also be defined as Don't Care (DC). The chIp IS enabled when the
Inpuls malch the user defined states Don't Care pins are slill connected to Inpul
protection diodes and are subject to "Absolute Maximum Ratmgs"
7.17
All control pins CP1 - CP4, can tie programmed as:
• CE, ICE, OE, IDE, Don't Care
S631000
Pin 20 (CP1)
S631001
Pin 22 (CP1)
Pin 24 (CP2)
Pin 30 (CP3)
Pin 31 (CP4)
·cs IS eqUivalent to DE.
I
-} GOULD
AIMII®Semiconductors
5631000/5631001
Absolute Maximum Ratings
Ambient Temperature Under Bias-TA .............................................. -55°C to +125°C
Storage Temperature ........................................................... -65°C to +150°C
Operating Temperature .................................................................. +125°C
Input or Output Voltages ........................................................ -0.3 to Vcc +0.3V
Maximum Current ....................................................................... 50mA
Maximum Power ....................................................................... 350mW
'COMMENT: Stresses above those listed under '»'bsolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics: Vcc =5V+100f0,
TA =O°C to 70°C
Symbol
VOL
Parameter
Minimum
Maximum
Units
0.4
V
V
Output LOW Voltage
VOH
Output HIGH Voltage
2.4
VIL
Input LOW Voltage
-0.3
0.8
Conditions
V
VIH
Input HIGH Voltage
2.2
Vcc+0.3
V
III
Input Leakage Current
-1.0
1.0
/LA
VIN=OV to Vcc
ILO
Output Leakage Current
-10
10
/LA
Vo=OV to Vcc, Chip Deselected
Icc1
Power Supply Current-Active
50.0
mA
10 =0, TR=Tcyc, duty=100%
VI=0.8V or 2.2V
ICC2
Power Supply Current':"'Active
30.0
mA
10=0, TR=Tcyc, duty=100%
VI=GND or Vcc
1581
Power Supply Current-Standby
2.0
mA
Chip in standby mode, VI=VIL or VIH
1582
Power Supply Current-Standby
150
/LA
Chip in standby mode, VI =GND or Vcc
Maximum
Units
'.
Capacitance: TA =25°C, f=1.0MHz
Symbol
Parameter
Minimum
Conditions
CIN
Input Capacitance
7
pi
VIN=OV
COUT
Output Capacitance
10
pi
VIN=OV
7.18
-} GOULD
AIMII®Semiconductors
5631000/5631001
AC Electrical Characteristics: Vcc =+5V+10%,
TA =O°C to 70°C
Symbol
Parameter
Minimum
Maximum
Tcyc
Period
8631000-15/8631001-15
8631000-20/8631001-20
150ns
200ns
TAA
Address Access Time
8631000-15/8631001-15
8631000-20/8631001-20
150ns
200ns
TACE
Chip Enable Access Time
8631000-15/8631001-15
8631000-20/8631001-20
150ns
200ns
TOE
Output Enable Access Time
8631000-15/8631001-15 '
8631000-20/8631001-20
BOns
100ns
THOLD
Output Hold Time
8631000-15/8631001-15
8631000-20/ 8631 001-20
Ons
Ons
TCD
Chip Disable Time
8631000-15/8631001-15
8631000-20/8631001-20
Ons
Ons
50ns
50ns
NOTE: See AC Timing Diagram and Test Load for Conditions
ROM Code Data
The preferred method of receiving ROM CODE DATA
is by electronic data transmission or in EPROM. For
EPROM ROM CODE DATA submission, two EPROMs
should be submitted. One is programmed to the desired
code and the other is blank. Gould AMI will read the
programmed EPROM, transfer this data to disk and then
program the blank EPROM from the stored information.
This procedure guarantees the the EPROM has been
properly entered into the Gould AMI computer system.
The Gould AMI programmed EPROM is returned to
the customer for verification of the ROM data. Unless
otherwise requested, Gould AMI will not proceed until
the customer has returned the ROM CODE VERIFICATION form.
If two EPROMS are used to specify one ROM pattern,
the programmed EPROMs must clearly state which of
the EPROMs is for the lower and upper address
locations in the ROM.
For electronic data transmission consult Gould sales
office for details.
Pattern Data from ROMs
If a customer has ROMs produced by another supplier,
these ROMs can be submitted for ROM pattern instead
of EPROMs. Obviously, these ROMs must be pin compatible with the Gould device. (NOTE:'ln some cases a
competitor's ROM may have a different chip select or
enable that is not customer defined. However, if this pin
is customer defined for the Gould ROM, the required
active logic level for this input must be specified.)
EPROM Requirements
Optional Method of Supplying ROM Data"
The following EPROMs should be used for submitted
ROM Code Data:
PREFERRED 27010/27011
Optional 2 - 27512
If an EPROM or ROM cannot be supplied, and electronic
data transmission cannot be used, the ROM CODE DATA
can be provided on floppy disc (51/4" floppy disc).
'Consult Gould sales office for format.
7.19
I
-} GOULD
AIMII®Semiconductors
5631000/5631001
AC Timing Diagram
ADDRESS TO OUTPUT DELAY (OUTPUT ENABLED)
ADDRESS
INPUTS
VALID
DATA
DUTPUTS
OUTPUT ENABLE TO OUTPUT DELAY
(ADDRESS VALID/OUTPUT ENABLED)
OUTPUT
ENABLE
DATA
OUTPUTS
VALID ENABLE
Hi-Z
VALID DATA
CHIP ENABLEIOUTPUT ENABLE TO OUTPUT DELAY (ADDRESS VALID)
CHIP
ENABLE
VALID
OUTPUT
ENABLE
DATA
OUTPUTS
7.20
-) GOULD
AIMII®Semiconductors
8631000/8631001
Test Load
f.
AC TEST CONOITIONS:
OUTPUT REFERENCE LEVELS:
LOW O.BV
HIGH 2.0V
OUT
1-----+---'VV'v
CL = 100pF
EPROM Cross Reference
Manulaclurer
Gould AMI Device
8631000
28 pin dip
AMD
Fujitsu
Hitachi
Intel
27C100
27C301
27011
UVEPROM
A"
A,
A"
A"
ADDRESS
1,048,576
81T ARRAY
DECODE
DRIVER
A"
A"
A"
i
Mitsubishi
National
NEC
{512
A,
A,
A,
A,
ADDRESS
DECODE
COLUMN
110
A,
DRIVER
CIRCUITS
As
A"
T
CPl
CP2
CP3
CP4
CHIP
SELECT
DECODER-
= 1.92V (CMOS)
I
Block Diagram
A,
A,
A,
• VL
RL = 4760
L...-_---I
INPUT PULSE LEVEL:
O.6V AND 2.2V
TEST COMPARATOR
POWER
DOWN
la
OUTPUT
BUFFERS
ENABLE
7.21
27C100
27C1000
Gould AMI Device
8631001
32 pin dip
27C010
27C1001
27C1001
27010
27C010
27C101
27C1023
27C1001
-} GOULD
AIMII®Semiconductors
5631000/5631001
PLCC Outline
.023
.029 e30
.042
.048
I
UJ~21
..
J
L.::OBSC:
.118/.129 DIA. EJECTOR PIN
A
A1
A2
0
01
02
03
E
E1
E2
E3
F1
G1
N
ND
NE
C
7.22
DIMENSIONS (INCHES)
NOM.
MAX.
MIN .
.140
.123
.130
.095
.078
.085
.106
.109
.112
.495
.485
.490
.453
.451
.449
.430
.390
.420
.300 REF.
.590
.595
.585
.549
.551
.553
.490
.520
.530
.400 REF.
.445
.441
.443
.545
.541
.543
32
7
9
.0100
.0103
.0097
NOTE
3
2
3
2
9
9
5
-) GOULD
AIMII®Semiconductors '
5631000/5631001
P-DIP Outline
S
y
M
A
.012
.008
B
C
D
E
F
G
Dimensions
Lead
Count
28
32
1.470
1.655
MAX
.560
.520
.610
.580
.020
MIN
.200
MAX
.070
.050
.020
.015
MAX
.560
.520
,610
.580
.020
MIN
.200
MAX
.040
.060
.020
.015
I
7.23
Mask ROMs
Minimize Cost
-} GOULD
AIMII®Semiconductors
Application Note
Using mask ROMs in place of EPROMs offers an ideal
solution to many manufacturers seeking cost reduction.
Although EPROMs offer the flexibility to debug code
and to do field upgrades, this flexibility comes at a
higher price.
This application note is a quick, comprehensive reference for a buyer of EPROMs who is interested in the
advantages of using Gould late mask programmable
ROMs in a debugged, volume application.
dow cerdip packages. This is why mask ROMs can
inherently cost less. than EPROMs. However, the
additional fixed mask charge increases the effective
piece price for ROMs in low volumes.. .
The total cost of EPROMs includes programming fees
(as high as $.50 per part) or equipment, programming
personnel, part labeling and inventory costs after the
EPROMs are completed. This inventory cost can be
comparable to mask ROM inventory costs.
Included are:
•
•
•
•
Compatibility Issues
Many performance issues are nearly identical between
ROMs and EPROMs such as:
CostlVolume considerations
Compatibility issues
Specific EPROMs which can be replaced
Ordering information
•
•
•
•
•
Cost/Volume Considerations
. Mask ROMs require fewer fabrication steps than
EPROMs and are often assembled in plastic, not win-
Storage and operating temperature
Vee Tolerance
Input and output leakage
Packaging (600mil dip, standard pinouts)
Access times (for popularly priced devices)
Relative ROM Pricing
512K EPROM
...
w
ii:
0...
w
:>
~
...J
W
a:
o
1,000
5,000
10,000
VOLUME
7.24
50,000
100,000
(Price source is 1987-88 Dataquest)
GOULD
AIMII®Semiconductors
Application Note
and cause the cell to be marginal or to fail. This failure mode is not present in a ROM, which is typically
programmed by implanting dopant ions into the channel region of the memory cell (which changes the
gate voltage necessary to turn on the memory cell).
The dopant ions are trapped in the silicon and are
virtually immobile except at temperatures above approximately 900°C.
Other issues usually favor Gould Semiconductor late
mask programmable ROMs:
• Alternate packages (28 pin SOIC, for example)
• Lower power dissipation
• Reliability: EPROMs are typically programmed by
accumulating electrons on a floating gate which
changes the control gate voltage necessary to turn
on the memory cell. Any leakage path through the
surrounding oxides can drain off the electron charge
EPROM Replacements
"Best" EPROM to be replaced 5
Power (rnA)
Device 6 Access
Number time (ns) ICC/ISB/ISBcMOS
2716 1
350
100/25
2532 1
450
150/30
2732 1
350
150/30
2764 1
27C64
271281
150
200
80/20
30/1/0.1
150
272561
27C2561
150
120
27C512
150
Specify these Control options Other parameter comparison
(j = ROM is better or equal)
to replace EPROM:
Gould Semiconductor ROM
Device 6
Number
Access
Power (rnA)
Pin Number
time (ns) ICC/15B/ISB cMOS 18 20 21 22 26
80/350
CSI CSI DC S68A3161.2
20/5/0.1
150
CEI C51 DC 568A3221,2
350
- CSI DC - 70/150
20/5/0.1
CSI DC 52333 1
200
70/15
CEI C51 150
20/5/0.1
56333
CEI CSI -
5%
j
j
j
j
j
l
j
j
5%
j
j
j
j
j
l
j
j
j
j
j
j
j
j
l
j
j
OEI DC CS
DEI DC CS
j
j
j
j
j
j
l
j
j
l
l
-
-
CEI CEI -
VIN
Vcc
27 10% ILEAK VOUT lOUT lAOE
-
52364
56364
200
150
90 4115
20/5/0.1
-
100/30
523128
200
80/20
-
CEI -
DEI -
CS
j
j
j
100/30
30/1/0.1
523256
563256
200
120
80/20
40/2/0.1
-
CEI CEI -
OEI DEI -
-
j
j
j
j
j
j
30/1/0.1
563512
150
50/2/0.15
-
CEI -
DEI -
-
j
j
j
1. Typically tested at 5% Vee, a 10% Vee screened part is available
in some cases. Gould Semiconductor ROMs 64K and larger are
specified at 10% Vee tolerance.
2. These two Gould Semiconductor NMOS ROMs do not provide
powerdown operation. However, the CMOS versions do.
3. Gould Semiconductor specification is IOL = 3.2mA,
IOH = -220fLA, a typical IOH is greater than -800fLA.
4. The typical lee value is less than 40mA over a temperature range
of 0-70cC.
5. The "best" EPROM specifications come from many catalogs.
No single EPROM may meet all these listed specifications
simultaneously. Because the device specifications frequently
change, the information provided here should be considered
-
j
j
j
j
j
j
100ns
j
j
j
representative. The intent is to show performance similarity,
and to provide control pin options for replacement compatibility.
6. The NMOS version of each device type is listed first, the CMOS
version is second.
Notes:
-Optional Gould Semiconductor ROM test limits to match a
particular EPROM can be specified.
-Gould Semiconductor nomenclature for an output control pin which
provides powerdown operation is "CE". An output control pin which
does not provide powerdown is "CS" or "OE". These functions,
along with polarity, are programmable.
7.25
-) GOULD
AIMII®semiconductors
Application Note
Specific Ordering Information
1. Choose the appropriate Gould Semiconductor
part number.
4. Supply one programmed and one blank, EPROM,
Gould Semiconductor will read your code and burn it
into the blank. It will then be returned along with a
form showing exactly what was ordered, for your
approval.
2. Specify speed and chip select, chip enable
information.
---or---
Conclusion
Gould Semiconductor late mask ROMs provide the
same or beUer direct replacement for EPROMs in
debugged, volume applications. The cost is substantially less, for mid to high volumes.
1, 2. Specify which EPROM is to be replaced
(part number and speed).
---then--3. Specify marking:
Gould logo, date code
line 1, 13 characters max
line 2, 13 characters max
7.26
-} GOULD
AIMII®Semiconductors
General Information
I
-) GOULD
AIMII®Semiconductors
Quality Program
Introduction
Quality Assurance
The most important activities in maintaining quality are
controlling and monitoring through the effective use of
Quality Improvement, Quality Assurance, Manufacturing
Quality Control, Reliability, Failure Analysis, and Corrective Action. Controlling and monitoring assure a consistently good, reliable product that can be manufactured
and delivered with predictable consistency.
There are two functions within the scope of Quality Assurance (QA), QA Operations and QA Engineering.
These areas are involved in checking the ability of
manufactured parts to meet specific limits. QA audits all
internal product specifications and procedures to assure
that they conform to customer specifications or Gould
AMI requirements, whichever are more stringent.
The Quality Program is based on MIL-Q-9858 and MILM-3851 0, using statistical methods to regulate all
aspects of the design and manufacture of Gould AMI
products.
QA Operations checks all phases of the manufacturing
process, including incoming material, to insure adherence to specifications and procedures through the
use of audits, inspections, and other monitoring techniques. In conjunction with audits, QA Operations administers the Customers Returns and Corrective Action
systems.
Committed to Quality through SPC
Statistical Process Control (SPC), a scientific method of
collecting, analyzing, responding, and continually improving processes, is a culture at Gould AMI. Gould AMI's
SPC program, begun in 1981, is the oldest among U.S.
semiconductor manufacturers. Customers therefore
benefit from years of accumulated knowledge in quality
control. The SPC system provides continuous feedback,
drawing attention to problems and focusing resources
on collective problem solving to create solutions.
The Customer Return System documents quality system
failures which result in returned product. This aids in
elimination of the causes for such failures, with the long
range purpose of eliminating returned products completely. A Corrective Action Request is initiated after the
cause for the return has been identified.
The Corrective Action System addresses quality system
failures to insure appropriate corrective action is taken to
preclude subsequent failures. QA Operations follows up
on each Corrective Action Request to insure the proper
resolution is attained.
Quality Improvement
The Quality Improvement Department is responsible for
training in the Quality Improvement Process throughout
Gould AMI, including but not limited to the use of SPC
and experimental design. Training includes the
philosophy of constant improvement and control chart
concepts, as well as statistical classes in Regression
Analysis and Design of Experiments.
QA Engineering provides the technical expertise for QA
Operations in addition to assuring that design and
manufacturing processes and documents are consistent
with company standards and customer requirements.
QA Engineering is also responsible for determining the
significance of product and process configuration changes as they pertain to customer requirements.
The classes are designed to approach problem solving
in a logical progression using more sophisticated tools
with each phase of the process. The definition of
process is given to be any task that has an input from
some source and an output going to a customer. Beginning with process flow charts, the analytic tools are explained with emphasis on practical application, using
actual data whenever possible.
Manufacturing Quality Control
Manufacturing Quality Control (MQC) is principally comprised of Fabrication QC and Test QC. Fabrication QC
is not a formal organization, rather an integral part of
Fabrication. Having these quality activities reporting to
8.3
I
.-
-} GOULD
AIMII®Semiconductors
Quality Program
Manufacturing reinforces the concept of individual
responsibility for quality.
Gould AMI Standard Product Flow
Fabrication QC makes extensive use of SPC via the
Shewart control charts maintained at each major step of
the fabrication process on oneor more measured variables. Equipment and test wafers are measured as well
as the actual product in evaluating the results of operations.
Test QC performs internal and.customer specified Lot Acceptance Testing (LAT) after Production screening
and/or environmental processing. Lots are defined,
sample sizes are determined, a[ld using the product
specifications, the type of tests to be performed and
equipment to be used are determined. In lieu of specifying a particular AQL for lot acceptance of standard
products, Test QC strives to reduce defects through continual improvement using SPC and other process control
methods.
All lots go through Plant Clearance where a .final inspection for visual/mechanical criteria and all supporting
documentation for the lot is verified (including LAT
sheets, special customer specifications, certificates of
compliance, etc.). The material is packed and sent to
the customer immediately after acceptance for "Just In
Time" delivery.
If a lot is rejected, analysis is done on the rejected
unit(s) to determine the cause(s). If the failure was due
to inadequate screening, it is returned for 100%
rescreening, identified as a resubmission, and LAT is
again performed, but to a tighter sampling plan. If the
resubmitted lot fails, an engineering review is done to ensure proper corrective action is taken before submitting
for the third time. No further submissions are allowed
beyond the third without a detailed analysis and correction of the root cause.
-
QAMonltor
-
MQC Inspections
-
MQC Inspections
• Assembly:
Incoming
Wafer Saw
1st Optical
Ole Attach
Wire Bond
2nd Optical
External Visual
-
QC Inspections
• Final Electrical:
Program Verification
Electrical
Vsuall Mecanical
-
MQC Inspections
-
MQC Inspections
• All manufacturing operations are audited by QA.
Reliability
The Reliability Department is responsible for demonstrating the dependability of Gould AMI products. Reliability
is assured through the evaluation of processes, devices,
and packages to establish that they are capable of meeting both the Gould AMI internal requirements and any
special customer requirements.
Reliability analyses are performed on a routine basis to
observe the degree of control in the manufacturing
processes. This is accomplished by the testing of parts
in numerous environments, e.g. temperature cycling,
vibration, constant acceleration, autoclave, etc..
8.4
-) GOULD
AIMII®Semiconductors
Quality Program
All aspects of new processes or process changes are
monitored and analyzed to determine what the final effect is on product reliability. Qualifications are performed to establish the capability of any significant
configuration changes. Reports are distributed, when
appropriate, on the results of such analyses.
electronics in order to verify, identify, and characterize
the mechanisms of failure. The analysis procedure
produces documented evidence to support the conclusions of the cause of faiiure.
Failure Analysis
While Gould AMI strives for prevention of errors, Corrective Action is occasionally required. There are many
sources of information which can generate corrective action including customer returns, receiving inspection
records, Failure Analysis reports, process audit reports,
and final lot acceptance inspection records.
The Failure Analysis (FA) organization provides physics
of faiiure investigations. Results are supplied to
Manufacturing to continually improve quality and
reliability. Complete analysis of faiiures from life, tests,
environmental tests, field applications, and critical factory applications are routinely provided by the department.
The FA laboratory is equipped to do post mortem examinations of failed devices employing, as required,
electrical measurements and many advanced analytical
techniques of physics, metallurgy, chemistry, and
Corrective Action System
Each Corrective Action Request will clearly state the
quality system faiiure along with the specific product or
material lot/run numbers, the date of discovery of the
faiiure, and the expected result of corrective action.
Records of all requests are maintained and followed up
to ensure against recurrence of deficiencies.
I
.-
8.5
-} GOULD
AIMII®Semiconductors
Package Availability I Testability
We can meet your package requirements in a variety
of ways. You can choose from eight basic package
types, including advanced technologies such as plastic
and ceramic chip carriers, small outline ICs and pin
grid arrays, with up to 180 lead test handling capability.
Gould AMI, a semiconductor industry leader in ASIC,
offers you space-saving and cost-efficient packages
and package processes spanning a broad spectrum
of capabilities.
SURFACE MOUNT PACKAGES
:-.' •
PLASTIC
I~:
PACKAGE TYPE
LEAD SHAPE
LEAD ~ - ~
LEADS:
16
20
24
28
32
40
44
48
52
64
68
80
84
100
120
128
144
160
MATERIAL COST
BOARD DENSITY
(1/0's per sq. in.)
THERMAL
DISSIPATION
RELIABILITY
LEADED CHIP
CARRIER
(PLCC)
SMALL OUTLINE
INTEGRATED CIRCUIT
(SOIC)
J
50 mils
Gullwing
50 mils
CERAMIC
'"
QUAD FLATPACK
(QFP)
1mm
Gullwing
.8mm
.65mm
.....•~..~.~~~....
LEADLESS CHIP
CARRIER
(CLCC)
Pad
50 mils 40 mils
A
B
A
B
A
A
A
A
A
A
B
A
B
A
B
A
A
B
A
A
A
A
A
A
Low
Low
Intermediate
High
High
High
High
Highest
Good
Good
Fair
Fair
Fair
Good
High
Intermediate
Best
High
Intermediate
Best
8.6
-} GOULD
AIMII®Semiconductors
Package Availability I Testability
,.!
THROUGH·HOLE PACKAGES
PLASTIC
~
,
PACKAGE TYPE
LEAD SHAPE
LEAD ~. ~
,
DUAL-IN-LiNE
(P-DIP)
'
PIN GRID ARRAY
(PPGA)
-.'
CERAMIC
~
,/.iiiil
SIDE BRAZE
PIN GRID ARRAY
(CPGA)
Lead
Pin
Lead
Pin
100 mils
100 mils
100 mils
100 mils
LEADCOUNT:
8
A
14
A
A
16
A
A
18
A
A
20
A
A
22
A
A
24
*A
A
A
28
A
32
A
40
A
48
A
A
A
68
A
A
84
A
A
100
A
A
108
A
120
A
132
A
144
A
180
A
A
MATERIAL COST
Lowest
High
High
Highest
BOARD DENSITY
(I/O's per sq. in.)
Low
High
Low
High
THERMAL
DISSIPATION
Fair
Good
Very Good
Best
RELIABILITY
Good
Fair
Best
Best
Legend:
A. Test -50°C to 150°C
B. Test -50°C to 150°C (leaded version available)
• Skinny body width ,,300 inches) also available
8.7
I
A
.-
I
-} GOULD
AIMII®Semiconductors
Package Description
Plastic Leaded Chip Carrier (PLCC)
For gate arrays, standard cell designs and custom ICs, our
PLCC meets your need for a quality surface-mount quad
package to support complex integrated circuits requiring
high lead counts. An added benefit is the PLCC's J-form
leads which make it ideal for easy handling and shipping.
The PLCC is transfer molded and thermosonically wire
bonded. Die are mounted on a copper leadframe and
external leads are wave soldered to provide improved
solderability required for vapor phase reflow application.
BODY
Small Outline Integrated Circuit (SOIC)
Our SOIC package is the smallest dual-in-line package
. available, and is an excellent choice for maximum board
density. It can be surface mounted on your printed circuit
board and is ideal for the automotive, telecommunications
and computer industries, or any industry .that requires
dense placement of chips on boards.
8.8
-} GOULD
AIMII®Semiconductors
Package Description
Plastic Pin Grid Array (PPGA)
The PPGA is a lower cost alternative to the Ceramic Pin
Grid Array if high reliability is not required. The body is an
epoxy glass composite with a gold plated cavity. The pins
are soldered in place (not force fit) and have a tin lead
(90/10) solder finish. The seal is an epoxy "glob top"
beneath a black anodized aluminum lid.
&7<
~NODIZED
I
ALUMINUM LID
"GLOB TOP" EPOXY
(FilLS CAVITY)
. EPOXY GLASS
COMPOSITE
Ceramic Pin Grid Array (CPGA)
The CPGA is a through-hole mount package for high
density packaging with very high pin counts. The lead
design also makes it compatible with socket insertion
mounting.
The CPGAs are built on the same concept as the ceramic
side brazed packages and are designed for high reliability
applications. They have an AI203 ceramic body, gold
plating on the pins and die cavity, and are sealed with a
Kovar/alloy 42 lid with gold-tin eutectic solder.
~\
KOVAR OR A42 LID
WITH NICKEL THEN GOLD PLATING
Au/Sn
SOLDER
SEALING
DIE
I
.-
GOLD
SEAL
RING
~~
ALUMINA
BODY
GOLD PLATED PINS
8.9
-} GOULD
AIMII®Semiconductors
Package Description
Ceramic Side Braze
The ceramic side braze is an industry standard high
performance, high reliability package, made of three
layers of AI203 ceramic and Tungsten refractory metal. A
gold tin eutectic sealed Kovar lid is used to form the
ALUMINUM
BOND
KOVAR LID
hermetic cavity of this package. Package leads are
available with gold or tin plating covered with 200
microinches of Sn/Pb 60/40 solder.
DIE
AuSn SOLDER
SEAL
WIRE
Ni & Au PLATING
PLATED KOVAR
ALLOY 42 LEAD
CuAg
BRAZE
TUNGSTEN
METALLIZATION
Quad Flatpack (QFP)
Quad flatpack is a high-density, low-cost plastic package
for high leadcount applications. It uses a smaller lead-tolead spacing than the PLCC, has gull-wing leads bent outward on all four sides which permits better inspection of
solder joints, solder-plated external leads. The package is
registered with the Electronics Industry Association of Japan.
QFPs are assembled with the latest technology of low stress
die-attach material and molding compound and exhibit better reliability.
BODY
8.10
-) GOULD
AIMII®Semiconductors
Package Description
Ceramic Leadless Chip Carrier (CLCC)
The package comes with a gold tin eutectic sealed metal
lid creating a hermetic cavity.
Built on the same concept as the highly reliablesidebraze
ceramic package, the CLCC is made of three layers of
AI 20 3 ceramic, refractory metallization, gold over nickel
plating, and contact pads equally spaced on all four sides
of the carrier.
(All Type C except 68 lead where both Type B and Type C
are available.)
GOLD PLATED SEAL RING
GOLD PLATED D/A CAVITY
AND SIDE CONTACTS
Plastic Dual-In-Line Package (PDIP)
The Gould AMI PDIP package is the equivalent of the widely
accepted industry standard, refined by Gould AMI for
MOSNLSI applications. The package consists of a plastic
body, transfer-molded around the leadframe and die. The
leadframe is copper alloy, with external pins tin plated. Internally, there is 150p in silver spot plating on the die attach
pad and on each bonding fingertip. These fingers are
electrically connected to the die by thermosonic gold ball
bonding techniques.
During manufacture every critical step of the process is
statistically monitored and controlled to assure maximum
quality.
DIE
BODY
SPOT
SILVER
GOLD
BONDING
PLATING
WIRE
I
CONDUCTIVE
DIE ATTACH
MATERIAL
TIN PLATING
8.11
-) GOULD
AIMII®Semiconductors
Package Thermal Resistance
The ability of the package to conduct heat from the device
to the environment is measured by thermal resistance. This
thermal resistance is calculated from the temperature dif·
ference between the die junction and the' surrounding am·
bient air environment (BJA)'
BJA data is based on a still-air environment where the
device is mounted ina package and the package mounted
on a board. The graph ranges reflect deviations in package
parameters within a lead count such as, but not limited to
die size, die attach pad size, etc. Chart values are given as
a guideline. Thermal resistance from junction to case ( BJcl
is typically better than junction to ambient. Use BJA for
worst case condition.
Surface-Mount Package Thermal Resistance
PLASTIC CHIP CARRIERS
PLASTIC SMALL OUTLINE I.C.
60
80
70
50
60
!;'I~
~13:40
50
<
<
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N
o@@@O@O@(!)@@@~
M
OI~Hj}@\Q)CO~@@OO@
L
/
k-
± .004
.018
~g
1
2
3
4
5
6
7,
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I
D2
E3
D1
E2
El
F3
F2
Fl
G2
G3
Gl
Hl
H2
H3
Jl
J2
Kl
J3
p:g
I
25
26
27
28
29
~Ag
30
31
32
33
34
35
' -36
37
38
"
M3
N3
M4
L5
N4
M5
N5
39
40
41
42
43
44
45
46
± .002 OIA.
61
62
83
64
65
66
67
L8
68
69
17
70
71
72
N7
N8
48
73
74
75
76
77
78
PIN
NO
H12
H13
G12
Gil
G13
"3
"2
Fll
E13
E12
D13
Ell
D12
C13
813
Dll
C12
A13
Cll
812
A12
ClO
811
All
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
~Ag
I
97
98
99
100
101
102
103
104
105
lOG
107
108
109
110
111
112
113
114
115
116
117
118
119
120
';tg
PIN
NO
810
C9
Al0
89
A9
C8
88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
AS
87
C7
A7
A6
86
C6
A5
85
A4
C5
84
A3
A2
C4
83
Al
TOP VIEW
sa
1.320 ± .012
I
e
@©@
~~~@'
"
PIN 1 INDICATOR,
.019 MAX
/
r
J
1rtl1~ l~ ~ ~ ~ ~ ~ ~ ~ ~ ~t~
-.I I.- STANDOFF
.018
i
,--II.-
± .002
INDEX PIN
D
1 23 4 5 6 7 8910111213
.085 ± .008
DIA.
I ~~
~g
23
Al
81
D3
C2
Cl
24
25
26
27
D2
28
EO
D1
29
30
31
32
E2
El
F3
F2
Fl
G2
G3
Gl
Hl
H2
H3
Jl,
J2
J3
33
34
35
36
37
38
39
40
41
42
43
"
I ~I~
Kl
K2
11
K3
L2
Ml
M2
C3
Nl
N2
M3
P1
P2
M4
N3
P3
N4
M5
P4
N5
P5
M6
P,fg
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
G5
66
I ~I~
N8
P6
N7
M7
P7
P8
N8
M8
P9
N9
M9
PlO
NlO
Pll
MlO
Nll
P12
N12
Mll
P13
N13
M12
~g
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
67
88
I ~I~ ,;:g I ~I~ r;:g I ~I~
P14
N14
L12
M13
M14
L13
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L14
K13
K14
J12
J13
J14
H13
H12
H14
G14
G13
G12
F14
Fl3
F12
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
E14
E13
D14
E12
D13
C14
C13
D12
814
813
C12
A14
A13
Cll
812
A12
811
ClO
All
810
AlO
C9
111
112
113
·114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
89
A9
B8
C8
AS
A7
87
C7
A6
86'
C6
AS
85
A4
C5
84
A3
83
C4
A2
82
C3
.-
@@@@@@@@@@@@@ c
@@@@@@@@@@@@@ B
@@@@@@@@@@@@ A
"-LID
L
@@@@@@@
@@@@@@@@@
@@@@@@@@@
©@@
@@@
©@@
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1==
± .012
I
120-Pin CPGA Outline
1--
.180
WIRE BONO I CONNECTOR PIN
PLASTIC AND CERAMIC
';:8 I
LB
N9
M9
NlO
L9
MlO
Nll
N12
L10
Mll
N13
L11
M12
M13
Kll
L12
L13
K12
Jll
K13
J12
J13
Hll
60
M6
N6
M7
47
I
49
50
51
52
53
54
55
56
57
58
59
l .047 MAX
STANDOFF
.180 ± .012
PIN
NO
M8
@@@
@@@
@@@@@@@@@Q@@@@
:@@@@(!)@@@O@@@@
o@@@o@@@@@@@@
ii
\
rin i
rruuuu
n~~~TIo±.o10
PLASTIC AND CERAMIC
PIN
NO
K2
L1
Ml
K3
L2
Nl
L3
M2
N2
@"'''
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K
J
H
G
F
E
D
C
B
A
1234567891011121314
STANDOFF .050 ± .004 DlA.
4 PLACES
STANDOFF
WIRE BONO I CONNECTOR PIN
PIN
NO
C3
82
81
D3
C2
Cl
@@@
@@@
: : : r/INDEX PIN
/
.050
±
.018 ±'.002 CIA.
,,@@
P
N
M
L
il
:
~H trrmlrh~@It.=Ik ~01O
.050 ± ,008
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I
sal
@@@@@@@@@@@@@@
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@@@@@@@@@@CO@(!!;I
@@@
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LID
STANDOFF .050 ± .004 DIA.
4 PLACES
.
~';~got .010
----j
PIN 1 INDICATOR---..,
1\2345678910111213
LID
~::~~ sa
D
K
J
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F
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E
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D
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~@o@@o@oo@o@@
A
PIN 1 INDICATOR~
BonOM VIEW
TOP VIEW
STANDOFF .050 ± .005 DIA.
.050 ±4.::ACES
.~o ± .010
8.19
GOULD
~MII®Semiconductors
Package Outline Dimensions
144-Pin PPGA Outline
180-Pin PPGA Outline
1--_ _ _ '.580 so--l
I
1.540
1.400
BOTTOM VIEW
TOP VIEW
± '.012 SQ
1.400 ± .012
~ccc@o@@oo@o@@@
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"""
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PIN 1 INDICAToR "\"
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STANDOFF .050 ± .004 DIA.
4 PLACES
00001001000001001010
K
J
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PIN 1 INDICATOR ' \ ,
1 23456789101112131415
LID
a
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G
F
c@ .C, ,01' INDEX PIN
E
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100100CCIOIOOO@IOIOOO B
OOO(llO@OOOOOO@O A
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sa-
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@!O@coO@O@OCOOIDlO N
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LID
STANDOFF .050 ± .004 DIA.
4 PLACES
.047 MAX
.018
!
L
± .002 DIA. U1\
~TI[itrtrtrtrtrtrtrtrtrtr~@1
±
±
=:j
STANDOFF
WIRE BOND' CONNECTOR PIN
PLASTIC AND CERAMIC
J
.050
.008
'
.018
L1
D3
2
3
,
5
6
7
8
9
10
11
12
13
14
15
16
17
16
19
20
21
22
23
24
e2
81
D2
E3
el
E2
Dl
F3
F2
El
G2
G3
F1
G'
H2
Hl
H3
J3
Jl
Kl
J2
K2
K3
26
"ZI
'28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45'
46
47
48
l2 .
M'
Nl
M2
L3
N2
Pl
M3
N3
P2
D'
N'
P3
02
P'
N5
03
P5
04
N6
P6
05
P7
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
'"
68
69
70
71
72
06
07
P8
08
N8
N9
09
010
P9
PlO
Nl0
011
P11
012
013
P12
N11
P13
015
N12
N13
P14
015
74
75
76
77
78
79
oo
81
82
83
84
85
86
fJ/
88
89
90
91
92
93
94
95
96
N14
P15
M14
l13
N15
l14
M15
K13
K14
L15
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J15
H14
H15
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F15
G14
F14
F13
ffI
E15
98
99
100
101
102
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D14
E13
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814
A15
e12
813
A14
812
e11
A13
811
103'
10'
105
106
107
,os
109
110
111
112
113
114
115
116
117
118
119
120
'22
123
12'
125
126
A12
el0
810'
A11
89
AlO
WIRE BOND I CONNECTOR PIN
'",..
88
';f8 I ~JS ';f8 I ~JS
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127
r::r
128
129
130
131
132
133
134
135
136
137
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139
140
141
142
143
144
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2
3
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86
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5
6
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8
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