1990_Altera_Data_Book 1990 Altera Data Book

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Altera, the Logical Alternative, MAX, MAX+PLUS, LogicMap, LogiCaps, and Alterans are
registered trademarks of Altera Corporation. The following are trademarks of Altera Corpora tion:
A+PLUS, AHDL, MPLD, SAM, BUSTER, MCMAP, MacroMuncher, TURBO-BIT, SALSA, ADUB,
PLDS-ENCORE, PLDS-MAX, PLCAD-SUPREME, PLDS-SAM, PLDS-MCMAP, PLS-MAX, PLSSUPREME, PLS-MCKIT, PLS-SAM, SAM+PLUS, SAMSIM, ASMILE, PLDS2, PLS4, PLS2,
PLCAD, PLE, ASAP, EP3OO, EP310, EP320, EP33O, EP512, EP600, EP610, EP630, EP640, EP900,
EP910,EF120~EF1210, EP1800,EP181~EP1830,EPS44~EPS464,EPB1400,EPB2001, EP2002,
EPB2002A, EPM5016, EPMS024, EPM5032, EPMS064, EPM5127, EPMS12B, EPMSl30, EPMS192,
MP1810, MPM5032, MPMS064, MPM5128, and MPM5192. A+PLUS and MAX+PLUS design
elements and mnemonics are Altera Corporation copyright. Altera Corporation acknowledges
the trademarks of other organizations for their respective products or services mentioned in this
document.
Altera reserves the right to make changes, without notice, in the devices or the device specifica tions
identified in this document. Altera advises its customers to obtain the latest version of device
specifications to verify, before placing orders, that the information being relied upon by the
customer is current. Altera warrants performance of its semiconductor products to current
Specifications in accordance with Altera's standard warranty. Testing and other quality control
techniques are used to the extent Altera deems such testing necessary to support this warranty.
Unless mandated by government requirements, specific testing of all parameters of each device
is not necessarily performed. In the absence of written agreement to the contrary, Altera
assumes no liability for Altera applications assistance, customers product design, or infringement
of patents or copyrights of third parties by or arising from use of semiconductor devices
described herein. Nor does Altera warrant or represent any patent right, copyright, or other
intellectual property right of Altera covering or relating to any combina tion, machine, or process
in which such semiconductor devices might be or are used.
Altera's products are not authorized for use as critical components in life support devices or
systems without the express written approval of the president of Altera Corporation. As used
herein:

Altera Corporation
2610 Orchard Parkway
San Jose, CA 95134-2020
(408) 984-2800
Applications Hotline:
1 (800) 800-EPLD
Marketing Hotline:
1 (800) SOS-EPLD

1. Life support devices or systems are devices or systems that (a) are intended for surgical
implant into the body or (b) support or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to
perform can be reasonably expected to cause the failure of the life support device or system, or
to affect its safety or effectiveness.
Altera cannot assume any responsibility for any circuits shown, or represent that they are free
from pa tent infringement.
Products mentioned in this document are covered by one or more of the following U.S. patents:
4,609,986; 4,617,479; 4,67l,318; 4,713,792; 4,774,421; 4,831,571; 4,864,161; 4,871,930; 4,899,067;
4,899,070; 4,903,223; 4,912,342; 4,930,107. and the following foreign patents: England: 2,072,384;
2,073,487; West Germany: 3,103,160; and Japan: 1,279,100. Additional patents pending.
Copyright © 1990 Altera Corporation

About this Data Book
I October 1990
This Data Book contains complete information about Altera products:
Section 1 provides an introduction to Erasable Programmable Logic
Devices (EPLDs). This section describes the principles
underlying EPLD architecture, summarizes EPLD families and
software tools offered by Altera, and explains the advantages
of CMOS EPROM technology. The section also contains a
Product Selection Guide for a quick overview of Altera products.
Section 2 describes the EP-series "classic" EPLDs, including A+PLUS
software support.
Section3 describes the EPMSOOO-series MAX EPLDs, including
MAX+PLUS software support.
Section 4 provides preliminary information about the EPM7000-series
MAX EPLDs.
Section 5 describes the EPS-series EPLDs, including SAM+PLUS software
support. This series includes the Stand-AloneMicrosequencer
(SAM) and Synchronous Timing Generator (STG) EPLDs.
Section 6 gives an overview of the EPB-series EPLDs, Altera's userconfigurable adapter interface chips for the IBM PS/2 Micro
Channel. The EPB2001 and EPB2002A EPLDs are described in
detail in the Micro Channel Adapter Handbook (April 1990).
Section 7 describes operating requirements for all Altera EPLDs.
SectionS describes Altera's development products, including
development systems, software utility programs, EDIF netlist
interface, software support for Apollo computers, device
programmer, adapters, and software warranty. This section
also includes a description of third-party support.
Section 9 describes the military products offered by Altera, including the
Source Control Drawings (SCDs) for military-qualified EPLDs.
The section also contains an application brief about total-dose
radiation hardness of Altera EPLDs.
Section 10 provides application notes and briefs for engineers and
engineering managers who seek practical ways to reduce design
costs, improve design quality, and shorten design cycles.

IA/tera Corporation

iii

I

About this Dsts Book

Section 11 gives information about how to use Altera's Electronic Bulletin
Board Service and order Altera products. This section also
shows all EPLD package outlines, describes thermal
characteristics of EPLDs, explains how to select sockets for Jlead packages, and lists Altera sales offices, representatives,
and distributors.

W

For immediate assistance on technical questions, please call
Altera's Applications Hotline at:

1 (SOO) 800-EPLD

W

For information on product availability, pricing, and order status,
please contact your Altera Representative or Distributor. Phone
numbers and addresses of Altera Sales Offices, Representatives,
and Distributors are listed at the end of this data book.

W

Should you have questions that cannot be answered by your
Sales Representative or Distributor, please call Altera's Marketing
Hotline at:

1 (800) SOS-EPLD
or contact Altera by FAX at:

408-248-6924

Altera Corporation

I

Contents
I October 1990
About this Data Book ....................................................................................... iii
Product Index ................................................................................................... vii
Subject Guide ..................................................................................................... xi

Section 1

Introduction to Altera EPLDs

Section 2

EP-Series Classic EPLDs

Section 3

EPM5000-Series MAX EPLDs

Section 4

EPM7000-Series MAX EPLDs

Section 5

EPS-Series SAM and STG EPLDs

Section 6

EPB-Series EPLDs

Section 7

Operating Requirements for EPLDs

Section 8

Development Products

Section 9

Military Products

Section 10

Application Notes & Briefs

Section 11

General Information

I Altera Core.oration

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11

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vi

Product
Index
I October 1990
EPLDs

I Altera Corporation

EPB2001 .................................................................................................... 20,215
EPB2002A ................................................................................................. 20,215
EPM5016 .................................................................. 18,21,113,115,125,267,327
EPM5016-1 ........................................................................... 18,113,115,125,267
EPM5016-2 ........................................................................... 18,113,115,125,267
EPM5032 .................................................................. 18,21,113,115,131,267,327
EPM5032-1 ........................................................................... 18,113,115,131,267
EPM5032-2 ........................................................................... 18,113,115,131,267
EPM5064 ......................................................................... 18,21,113,115,137,267
EPM5064-1 ........................................................................... 18,113,115,137,267
EPM5064-2 ........................................................................... 18,113,115,137,267
EPM5128 ......................................................................... 18,21,113,115,143,267
EPM5128-1 ........................................................................... 18,113,115,143,267
EPM5128-2 ........................................................................... 18,113,115,143,267
EPM5130 .............................................................................. 18,113,115,149,267
EPM5130-1 ........................................................................... 18,ll3,115,149,267
EPM5130-2 ........................................................................... 18,113,115,149,267
EPM5192 .............................................................................. 18,113,115,192,267
EPM5192-1 ........................................................................... 18,113,115,192,267
EPM5192-2 ........................................................................... 18,113,115,192,267
EPM7015 ................................................................................................. 177,178
EPM7020 ................................................................................................. 177,178
EPM7025 ................................................................................................. 177,178
EPM7040 ................................................................................................. 177,178
EPM70SO ................................................................................................. 177,178
EPM7075 ................................................................................................. 177,178
EPM7100 ................................................................................................. 177,178
EPM71SO ................................................................................................. 177,178
EPM7200 ................................................................................................. 177,178
EPS448-20 .......................................................................................... 20,183,185
EPS448-25 .......................................................................................... 20,183,185
EPS448-30 .......................................................................................... 20,183,185
EPS464 ................................................................................................ 20,183,203
EPl800 ...................................................................................................... 22,268
EP1810-35 ............................................................................. 19,22,31,85,99,267
EP1810-40 ............................................................................. 19,22,31,85,99,267
EP1810-45 ............................................................................. 19,22,31,85,99,267
EP1830-20 ............................................................................. 19,22,31,85,95,267
EP1830-25 ............................................................................ 19,22,31,85,95,267
EP1830-30 .................................................................... ,........ 19,22,31,85,95,267
vii I

I Product Index
EPLDs
(continued)

Development
Tools

I viii

Data Book

I

EP320 .............................................................................. 19,22,31,33,45,267,327
EP320-1 ................................................................................ 19,22,31,33,45,267
EP320-2 ................................................................................. 19,22,31,33,45,267
EP330-12 ......................................................................... 19,22,31,33,41,267,327
EP330-15 .................................................................................... 19,22,33,41,267
EP600 ........................................................................................................ 22,268
EP61 0-25 ......................................................................... 19,22,31,49,67,267,327
EP610-30 ............................................................................... 19,22,31,49,67,267
EP610-35 ............................................................................... 19,22,31,49,67,267
EP630-15 ......................................................................... 19,22,31,49,63,267,327
EP630-20 ............................................................................... 19,22,31,49,63,267
EP640-12 ...................................................................................... 19,22,31,49,59
EP640-15 ...................................................................................... 19,22,31,49,59
EP900 ........................................................................................................ 22,268
EP910-30 ............................................................................... 19,22,31,71,81,267
EP910-35 ............................................................................... 19,22,31,71,81,267
EP910-40 ............................................................................... 19,22,31,71,81,267
8946901 ..................................................................................................... 22,269
8947601 ..................................................................................................... 22,269
8854801 ..................................................................................................... 22,269
8854901 ..................................................................................................... 22,269
8863501 ..................................................................................................... 22,269
8686401 ..................................................................................................... 22,269
PLAESW .............................................................................................. 24,27,260
PL-ASAP ............................................................................................. 24,27,256
PLCAD.:SUPREME ............................................................................ 24,25,227
PLI)5-ENCORE .................................................................................. 24,25,223
PLDS-MAX .......................................................................................... 24,25,225
PLDS-MCMAP ................................................................................... 24,25,233
PLDS-SAM .......................................................................................... 24,25,231
PLDS2 .................................................................................................. 24,25,229
PLE3-12A ............................................................................................. 24,27,257
PLEG1810 ............................................................................................ 24,27,258
PLEJ1810 .............................................................................................. 24,27,258
PLEG1830 ............................................................................................ 24,27,258
PLEJI830 .............................................................................................. 24,27,258
PLEJ2001 .............................................................................................. 24,27,258
PLED330 .............................................................................................. 24,27,258
PLEJ330 ................................................................................................ 24,27,258
PLES330 ............................................................................................... 24,27,258
PLED448 .............................................................................................. 24,27,258
PLEJ 448 ................................................................................................ 24,27,258
PLED5016 ............................................................................................ 24,27,258
PLEJ5016 .............................................................................................. 24,27,258
PLESS016 ............................................................................................. 24,27,258
A/tera Corporation

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I Data Book
Development
Tools
(continued)

IAltera Corporation

Product Index I

PLED5032 ............................................................................................ 24,27,258
PLEJ5032 .............................................................................................. 24,27,258
PLESS032 ............................................................................................. 24,27,258
PLEJ5064 .............................................................................................. 24,27,258
PLEG5128 ............................................................................................ 24,27,258
PLEJ5128 .............................................................................................. 24,27,258
PLEG5130 ............................................................................................ 24,27,258
PLEQ5130 ............................................................................................ 24,27,258
PLEG5192 ............................................................................................ 24,27,258
PLEJ5192 .............................................................................................. 24,27,258
PLEQ5192 ............................................................................................ 24,27,258
PLED610 .............................................................................................. 24,27,258
PLEJ610 ................................................................................................ 24,27,258
PLED630 .............................................................................................. 24,27,258
PLEJ630 ................................................................................................ 24,27,258
PLES630 ............................................................................................... 24,27,258
PLED910 .............................................................................................. 24,27,258
PLEJ910 ................................................................................................ 24,27,258
PLS-APOLLO ...................................................................................... 24,26,249
PLS-EDIF ............................................................................................. 24,26,238
PLS-MAX ............................................................................................. 24,25,163
PLS-MCKIT ......................................................................................... 24,25,124
PLS-SAM ............................................................................................. 24,25,207
PLS-SUPREME ................................................................................... 24,25,103

Ix

I

Subject
Guide
I October 1990
A+PLUS .................................................................................................. 26, 103
Altera Design Processor (ADP) .................................................. 107
Boolean Equation Entry ............................................................... 105
Functional Simulator (FSIM) ...................................................... 108
LogiCaps Schematic Capture .............................................. 104, 390
LogicMap II Programmer ............................................................ 108
State Machine and Truth Table Entry ........................................ 106
TTL MacroFunctions ............................................................ 168, 390
AC Timing Characteristics for EP-Series EPLDs ..................................... .431
Altera Hardware Description Language (AHDL) ........... 166, 361, 371,523
Address Decoder .................................................................................. 281, 374
Bar Code Decoder ........................................................................................ 417
Bus Controller ............................................................................................... 355
Cascading (SAM)
Addressed-Branch ........................................................................ 456
Horizontal ..................................................................................... 193
Master /Slave ................................................................................. 461
Vertical ................................................................................... 193, 453
Chip-Select Logic ......................................................................................... 281
CMOS EPROM Technology ...................................................................... 3, 11
Converters
ABEL2MAX ................................................................................... 236
EDF2CNF ....................................................................... 239, 240,250
PLD2EQN ...................................................................................... 236
SNF2EDF ............................................................................... 247, 253
SNF2GDF ............................................................................... 173, 239
Counter Design ............................................................................................. 389
Counters ................................................................................................ 376, 389
CRCGenerator ............................................................................................. 336
Design Entry
AHDL ..................................................................... 166, 361, 371,523
ASM ............................................................................................... 309
ASMILE ................................................................................. 186, 299
Boolean Equation .................................................................. 105, 475
Microcode .............................................................................. 186, 349
Schematic Capture ........................................................ 104, 165, 390
State Machine and Truth Table ........................................... 106, 401

I Altera Corporation

I Subject Guide

Data Book

I

Design Guidelines for EPM5000-Series EPLDs ........................................ 497
Development Software
A+PLUS ......................................................................................... 103
MAX+PLUS ................................................................................... 163
SAM+PLU5 ................................................................................... 2CJ7
Utility Programs ........................................................................... 235
Device
Erasure ........................................................................................... 220
Selection Guide ............................................................................... 17
Testing ................................................................................... 271,289
Digital Image Processing ............................................................................. 343
Direct Memory Access (DMA) ................................................................... 535
Dual Feedback .............................................................................................. 477
Dynamic RAM Control ................................................................ 287, 378,547
EDIF Netlist Interface .................................................................................. 238
Electronic Bulletin Board Service ............................................................... 563
Electrostatic Discharge .................................................................................. 15
Emulating Internal Buses ............................................................................ 521
EP-Series EPLDs ............................................................................................. 31
EPB-Series EPLDs ........................................................................................ 215
EPLD
Architecture ...................................................................................... 7
Delay Parameters ................................................................. 430, 482
Design Environment .................................................................. 5,23
Package Outlines .......................................................................... 563
Testing ................................................................................... 271,289
EPM-Series EPLDs ....................................................................................... 113
EPS-Series EPLDs ......................................................................................... 183
Estimating a [)esign Fit ............................................................................... 443
Expanded Memory ...................................................................................... 505
Finite Impulse Response (FIR) .................................................................... 351
Fitting a [)esign into an EP-series EPLD .................................................. .443
Frequency Divider ....................................................................................... 527
Graphics Controller ..................................................................................... 312
Input Reduction (SAM) ............................................................................... 465
Interface to Memory and Peripheral [)evices ........................................... 281
Internal Buses ............................................................................................... 521
Internal Nodes .............................................................................................. 511
Introduction to EPLDs ..................................................................................... 3
, Latch-up .................................................................................................. 14, 220
Latches IRegisters
Asynchronous ............................................................................... 397

I xii

Altera Corporation

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I Data Book

Subject Guide

I

Latches/Registers (continued)
D-type .................................................................................... 397,492
Expanders ...................................................................................... 491
SR ............................................................................................ 398,491
Synchronous ................................................................................. 494
LogiCaps Schematic Capture .............................................................. 104, 390
LogicMap II ..................................................................................................... 26

Macrocell Architecture .................................................................................... 8
MacroMunching ........................................................................................... 394
Master Programming Unit .......................................................................... 257
MAX+PLUS
AHDL ..................................................................... 166, 361, 371,523
Compiler ........................................................................................ 169
IJesign Guidelines ........................................................................ 497
Graphic Editor .............................................................................. 165
Memory Configuration ................................................................ 505
Programmer .................................................................................. 172
Simulator ....................................................................................... 170
Symbol Editor ............................................................................... 166
Text Editor ..................................................................................... 167
Timing Analyzer ........................................................................... 172
TTL MacroFunctions .................................................................... 168
Waveform Editor .......................................................................... 171
MCELL Buffer ............................................................................................... 500
Memory Optimization ................................................................................. 505
Metastability ................................................................................................. 289
Micro Channel .............................................................................................. 215
Microcode Memory ...................................................................................... 188
Mili tary Proci ucts ................................................................................. 267, 270
Multiway Branching (SAM) ........................................ 198, 311, 449, 450, 451
Operating Requirements for EPLDs .......................................................... 219
Ordering Information .................................................................................. 567
Package Options ............................................................................................. 17
Package Outlines .......................................................................................... 587
PAL/GAL Replacement .............................................................................. 277
PAL/PLA Integration .................................................................................. 327
Pattern Generation ....................................................................................... 297
Product Selection Guide ................................................................................ 17
Programming
with LogicMap II .................................................................. 108,212
withMAX+PLUSProgrammer .................................................. 172
Programming Adapters .............................................................................. 258
Programming Unit ....................................................................... 124,256,257

I Altera Corporation

xiii

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I Subject Guide

Data Book

I

Radiation Hardness ..................................................................................... 271
Sales Offices, Distributors & Representatives .......................................... 587
SAM+PLUS
ASM Assembly Language ................................................... 209, 309
ASMILE State Machine Input Language ........................... 208, 299
IJesign Entry ......................................................................... 185, 298
General IJescription ....................................................................... 26
SAM IJesign Processor (SOP) ..................................................... 210
SAMSIM Functional Simulator .................................................. 211
Security ........................................................................................................ 198
Shaft Encoder ................................................................................................ 331
Simulation
Functional
FSIM ....................................................................................... 108
SAMSIM ................................................................................ 211
Internal Nodes .............................................................................. 511
Timing .................................................................................... 170, 427
Virtual Logic Anal yzer (VLA) .................................................... 108
Waveform Editor .......................................................................... 171
SOFTBuffer .................................................................................................. 500
Source Control Drawing ............................................................................. 270
State Machine
A+PLUS ......................................................................................... 401
Altera Hardware IJescription Language (AHDL) .... 361, 371,523
Assembly Language (ASM) ........................................................ 209
Partitioning ................................................................................... 405
SAM+PLUS ................................................................................... 207
Simulation ..................................................................................... 516
State Machine Input Language (ASMILE) ........................ 186, 208
Sockets for EPLDs ........................................................................................ 583
Software Utilities .......................................................................................... 235
Synchronization Detector .................................................................... 379, 413
Synchronous Timing Generator ................................................................. 203
System Requirements .................................................................................. 237
Testing
Timing

................................................................................................. 271,289

EP-Series ........................................................................................ 427
EPM-Series .................................................................................... 479
EPS448 EPLD ................................................................................ 315
Thermal Resistance ...................................................................................... 582
Third-PartySupport .................................................................................... 261
Wait-State Generation ................................................................................. 283
Warranty ....................................................................................................... 260
Workstation Support ................................................................... 238, 249,261

I xiv

A/tera Corporation

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Contents
I October 1990
Section 1

Introduction to Altera EPLDs
Programmable Logic Overview ........................................................................ 3
Product Selection Guide .................................................................................. 17

IAltera Corporation

Page 1 I

D

Programmable Logic
Overview
I October 1990, ver. 1
Introduction

Data Sheet I
Programmable Logic Devices (also described as PLD, PAL, PLA, FPLA,
EPLD, EEPLD, LCA, and FPGA devices), combine the logistical advantages
of standard, fixed integrated circuits with the architectural flexibility of
custom devices. These devices allow engineers to electrically program
standard, off-the-shelf logic elements to meet the specific needs of their
applications. Proprietary logic functions can be designed and fabricated
in-house, eliminating the long engineering lead times, high tooling costs,
complex procurement logistics, and dedicated inventory problems
associated with custom Application-Specific Integrated Circuit (ASIC)
devices, such as gate arrays and standard cells.
The key to this "off-the-shelf ASIC" capability is CMOS EPROM technology,
which is used to create Erasable Programmable Logic Devices (EPLDs).
Altera has taken advantage of speed and density advances in CMOS
EPROM memory products to create sophisticated EPLDs that solve many
logic design problems.
Altera provides the broadest line of CMOS EPLDs in the industry, with
products ranging in density from hundreds to thousands of gates, offered
in a variety of packages with 20 to 100 pins. Larger EPLDs, with up to
20,000 gates and over 200 pins (the EPM7000 series), are currently under
development. These EPLDs, together with Altera development software,
enable system manufacturers to create custom logic functions for a wide
variety of applications. See Figure 1.
Figure 1. Altera User-Programmable Logic Families
EP-Series
EPMSOOO-Series

EP-Series
EPMSOOO-Series

Random
Logic

I Altera Corporation

Control
Logic

Page 3

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I Plogrammable Logic Overview

Data Sheet

I

EPLDs can be used to integrate complete printed circuit boards of TIL,
PAL, and FPGA devices into a single package. EPLDs are also valuable for
prototyping high-density custom devices, which enables designers to test
markets and evalua te systems before committing to expensive engineering
development cycles and tooling charges. For most of today's applications,
EPLDs not only ensure faster time-to-market, but also provide a lower
total cost than custom ASIC solutions.
Altera concentrates on creating high-performance device architectures
and easy-to-use, highly productive CAE software. Altera products meet
the demands of designers who require complete solutions to logic
integration that include both PAL speed and FPGA density. See Figure 2.
Figure 2. PLD Speed vs. Density

100

Usable
Speed
(teNT)
MHz

EPLD
Families

50

AHera offers several families of EPLDs that satisfy many common boardand system-integration needs. EPLD families are divided into two
architectural categories: the first provides maximum flexibility for generalpurpose logic replacement; the second is specialized for performing specific
system design tasks.

o

General-purpose EPLDs are available in a variety of integration
densities, ranging from PAL replacements to high-density devices
that integrate thousands of TIL and random logic gates. These EPLDs
are designated with the EP- and EPM- prefixes.
The EP-series architecture includes 20- to 68-pin EPLDs that
feature zero-standby power, propagation delays (tpo) of 12 ns, and
counter frequencies of up to 100 MHz.

I Page 4

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I Data Sheet

Programmable Logic Overview

I

The EPM5000-series Multiple Array MatriX (MAX) architecture
includes 20- to 100-pin EPLDs that combine the high speed and
ease-of-use of PAL devices with the density of FPGA devices.
High-density MAX EPLDs can consolidate 20 to 25 PAL packages
and over 100 TIL functions, while offering system clock rates of
50 MHz.
Altera is also developing the next generation of EPLDs-the EPM7000
series-that will provide integration densities of 1,500 to 20,000 gates,
with additional increases in system speed.

o

Function-specific EPLDs provide optimized integration for specific
system design tasks. They are classified on the basis of their system
design focus and are designated with the EPB- and EPS- prefixes.
EPB-series EPLDs are bus-oriented devices designed to integrate
all the required add-on card logic for a Micro Channel bus interface.
EPS-series EPLDs offer the logic and speed required for complex
control logic, state machines, and imaging and display
applications. EPS-series EPLDs include the Stand-Alone
Microsequencer (SAM) and Synchronous liming Generator (STG)
EPLDs.

EPLDs are offered in a variety of packages, including the dual in-line
package (DIP), J-Iead chip carrier aLCC), small-outline integrated circuit
(SOl C), quad flat pack (QFP), and pin-grid array (PGA). EPLDs are available
in windowed (erasable) ceramic packages for development, or one-timeprogrammable plastic versions for high-volume production requirements.

Software
Tools

Altera software products are developed together with the EPLD
architectures, so features are placed where they are most appropriate-in
either software or hardware. The result is efficient software tools that offer
familiar design entry methods and rapid design com pletion. (See Figure 3.)
With Altera's CAE development tools, users can take a logic circuit from
design entry to device programming in a matter of hours. Design processing
is typically completed in minutes, allowing several design iterations to be
completed in a single day.

Figure 3. EPLD Design Methodology: From Concept to Silicon In Hours

.. I

Design
Entry

3 minutes
to
1hour

I Altera Corporation

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.

..
5 seconds
to
15 minutes

3 hours

..

..

less than
1 minute

PageS

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I Programmable Logic Overview

Data Sheet

I

Altera software is available for PC-AT (or compatible), PS/2, and
workstation com pulers (Apollo, Sun, and IBM). Several design entry options
are available: hierarchical schematic capture (with basic gate and complete
TTL libraries), the Altera Hardware Description Language (AHDL), Boolean
equation, state machine, truth table, netlist, and microcoded assembly
language. (See Figure 4.) Design entry methods may be freely combined to
create a single EPLD design. Design processors perform minimization and
logic synthesis, design fitting (analogous to automatic place-and-route),
and generate programming data. Design verification via functional
simulation, timing simulation, and delay prediction for speed-critical paths
is also available. Hardware for programming EPLDs is offered by Altera
and a variety of third-party vendors.
Figure 4. Altera Design Environment
·, ........................................... .

l·

.l

~

Design Entry
Third-Party
Design
Entry

Altera
Hardware
Description
Language

~

Design Processing

-..

PLS-EDIF

: ..
I
+~PLS-APOLLOI

··,................................................
~

Design Verification ~

:

..

i.
:

..

Third-Party
Simulation

1
:~

r+ f++

MAX+PLUS

MAX+PLUS
Simulator

A+PLUS

A+PLUS
Simulator
(FSIM)

SAM+PLUS

SAM+PLUS
Simulator
(SAMSIM)

EPMSeries
(MAX)

Schematic
Capture
Boolean
Equation

4+

State Machine
Truth Table

State Machine
Assembly
Language

Table

: ..

~

...

...--..

Device
Programming

EPSSeries
. (SAM)

EPBSeries

MCMap

·................................................. ..................................................

IPage 6

-

EPSeries

:.............................................

Altera Corporation

I Data Sheet

Programmable Logic Overview

I

Software interfaces to other design tools are provided by Altera and thirdparty translators, and via industry-standard EDIF netlists. Many thirdparty compilers also support Altera EPLDs directly.

EPLD
Architecture

The following discussion of EPLD architecture is provided for interested
readers. Note, however, that the Altera approach to logic design eliminates
the necessity of mastering the inner complexities of EPLD architectures.
The user may work with familiar design entry tools (e.g., TIL functions or
a high-level state machine language), and the Altera software automatically
translates the design into the format required to fit the EPLD architecture.
For detailed architecture and pin-out descriptions for each device, refer to
individual EPLD data sheets in this data book.

Basic
Concepts

Altera general-purpose EPLDs provide dedicated input pins, userconfigurable I/O pins, and programmable flip-flop and clock options that
ensure maximum flexibility for integrating random logic functions.
Each EPLD also contains an AND array that provides product terms. A
product term is simply an n-input AND gate, where n is the number of
connections. EPLD schematics use a shorthand AND-array notation to
represent several large AND gates with common inputs. Figure 5 shows
three different representations of the same logic function. Circuit I is
presented in classic logic notation; circuit II has been modified to a sum-ofproducts notation; and circuit III is written in AND-array notation. A dot
represents a connection between an input (vertical wire) and one of the 8input AND gates. No dot implies no connection: the AND gate input is
unused and floats to a logic 1.

Figure 5. AND-Array Notation
Circuit I: Typical Circuit
11

*=AND

12----1

+=OR

13

Circuit II: Circuit 1drawn with complementary output
buffers

11 • 12.113 + 11 • 14

11---r-"""\
14---L-J

11 • 12 • 113 + 11 • 14

Circuit III: Circuit II with 8-input AND-gates in AND-array notation

11 • 12 ./13 + 11 • 14

11

12

11

12 13 14

13 14

I A/tera Corporation

Page

71

D

I Programmable Logic Overview

Dats Sheet

I

The 2 x 8 AND-array of circuit III can produce any Boolean function of four
variables (provided only two product terms are required) when expressed
in sum-of-products form. Any Boolean expression-no matter how
complex-can be written in sum-of-products form. Outputs of the two
AND gates in Figure 5 are called product terms (or p-terms).

Macrocell
Architecture

The fundamental building block of an Al tera EPLO is the macrocell. Each
macrocell consists of three parts (see Figure 6):
LJ
LJ

o

The logic array implements all combinatorial logic functions.
The programmable register provides 0, T, JK, or SR options (the
register can also be bypassed).
Programmable I/O allows each I/O pin to be configured for dedicated
input, output, or bidirectional operation.

Figure 6. The Macraeell
Logic Array

Register Options

110 Control

r-------------------- r---------------- r-------------

=-1
~
P
~~.
~~
.
.
:
.
:~
W···:··:~
i
c::>-l
;
!;
1:
'-"""--

,,

e>i

=-

::

~:

::

0- jI>-

c

::
: :

:'

c

. :.

' ..~
...................:.
:: ":

t ..................: :...................:

~p~ ~ ~: i~r·:··:~ ~~ :~
,

"---.JS=.............-~"

c::>-,
, ,
L ____________________ 1 L

,

Logic Array

,,

K

c

:
::
: :

.~..:.: =.=.:.~

R

c

:..:.:.:

:i

it. . . . . . . . .

i OUTPUT

.i

:,

:

,

:,

=,:,:,~,

L _____________ ,

The logic array consists of such a programmable-ANO/fixed-OR PLA
array. Inputs to the AND array come from the true and complement of the
dedicated input and clock pins, and from the macrocell and I/O feedback
paths.
For each macrocell, the logic array typically contains 10 product terms that
are distributed among the combinatorial and sequential resources. (See
Figure 7.) Connections are opened during the programming process.
Therefore, any product term may be connected to the true and complement
of any array input signal. When both the true and complement of any
signal are left intact, a logic low (0) results on the output of the product
term. If both the true and complement connection are open, a logical
"don't care" results for that input. If all inputs for the product term are
programmed opened, a logic high (1) results on the output of the product
term.

I Page 8

Altera Corporation

I

1

Programmable Logic Overview

Data Sheet

1

Figure 7. Detailed EPLD Macrocell Architecture
from
Inputs

from
1/0

from
Macrocells

Preset

II
Clear
Inputs C)-Cl;:::ttmt1~1

I

System Clock

Logic Array

Several product terms feed a fixed OR whose output connects to an
exclusive-OR (XOR) gate. The SEX:ond input to the XOR function is controlled
by a programmable resource (usually a product term) that allows the logic
array output to be inverted. Altera software uses this gate to implement
active-high or active-low logic, complex mutually exclusive and arithmetic
functions, or to reduce the number of product terms to implement a
function (by applying De Morgan's inversion). Figure 8 shows an OR
function that, in its current form, requires six product terms. By using the
"programmable" XOR gate and De Morgan's inversion, the OR function
can be transformed into a NAND function:

This inversion from OR to AND translates the equation and reduces the
number of fixed-OR terms required in the logic array. Altera software
automatically applies De Morgan's inversion and other logic synthesis
techniques to optimize the use of the logic array.

Programmable
Flip-Flops

I Altera Corporation

Programmable flip-flops are used to create a varietyoflogic functions that
use a minimum of EPLD resources. Each flip-flop can be programmed to
provide a conventional D-, JK-, T-, or SR-type function. MAX EPLD flipflops can also be configured as flow-through latches. If the flip-flop is not
required for macrocelliogic, it may be simply bypassed. Macrocell flip-

Page

91

IProgrammable Logic Overview

Data Sheet

I

Figure B. Logic Mlnlmlzat/on with Oe Morgan's Inversion

A§=>-

De Morgan's

B

~

-

Inversion

~

I

EPLD Implementation

+
A --. ....O:;.......~

B --[:~==~

c -C2::=====~
o
E
F

-[:i::=========::J
-[:2=:========:::::::J

flops also have an asynchronous Clear and Preset capability that allows
complete emulation of any TTL function.

Programmable
Clock

In general-purpose EPLDs (except the EP330 and EP320), each internal
flip-flop may be clocked from a dedicated system clock (also known as a
synchronous clock), any input or I/O pin, or any internal logic function.
For each flip-flop, a multiplexer selects either a pin or product-term source
for the clock, so that flip-flops can be clocked independently or in userdefined groups. EPLD registers are positive-edge-triggered with data
transitions that occur on the rising edge of the dedicated system clock.
When the clock is driven by a product term, flip-flops can be configured for
either positive- or negative-edge-triggered operation. In addition, productterm clocks allow gated-clock and clock-enable logic to be implemented.
However, system clock signals have faster c1ock-to-output delay times
than internally generated product-term clock signals.

1/0 Control
Block

I Page 10

The EPLD I/O control block contains a tri-state buffer controlled by a
macrocell product term, and drives the I/O pin (see Figure 9).1/0 pins
may be configured as dedicated outputs, bidirectional outputs, or as
additional dedicated inputs. Most EPLDs have IIdual feedback," whereby
the macrocell feedback is decoupled from the I/O pin feedback. Dual
feedback makes it possible to implement a buried function in the macrocell
while the I/O pin is used simultaneously as a dedicated input. Applications
that require many buried flip-flops (such as counters, shift registers, and

Altera Corporation

I

IData Sheet

I

p,.og,.ammable Logic Ovetvlew

Rgure 9. VO Control Block
The decoupled 110 control
block features dual feedback
to maximize use of the EPLD
pins.

from Macrocell

DE Control

from Macrocell

Macrocell
Feedback

- - - - - - - 0 .... 1 I/O Pin
Feedback

state machines or bus-<>riented functions) are easily accommodated by this
programmable I/O control block.

Zero-Power!
Turbo
Operation

CMOS technology generally implies lower power dissipation than older
bipolar technology. In fact, Altera pioneered true "zero-standby" power
operation. By using a unique input-transition detection scheme, most
EP-series EPLDs use only microam ps during quiescent periods. This feature
saves power in applications clocked at low to medium frequencies « 10
MHz). Each input is connected to a transition-detection circuit consisting
of an XOR gate, a delay element, and an OR gate. The trigger output of the
OR gate activates logic array power-up on any transition, allowing new
input conditions to propagate to EPLD outputs. The logic array is then
automatically powered down to await the next transition. The transitiondetection circui try adds an additional 30 to 40% delay to the EPLD input/
output path. Consequently, a programmable "Turbo Bit" is provided to
disable the input transition detection circuitry and permanently enable the
logic array, giving the user a choice of either extra speed or lower power
consumption. The EPLD also exhibits better system noise rejection
characteristics in the turbo mode, which should be used where noisy
environments are a problem. The Turbo Bit is included in the EPLD
programming file and is programmed in the same way as any other
EPROM bit.

Altera CMOS
EPROM
Technology

Until Altera invented the first EPLD in 1984 (the EP300), the only technology
used for Programmable Logic Devices (PLDs) was bipolar and fuse-based.
The active elements on these devices were constructed from traditional
bipolar transistors (i.e., TIL), with arrays of fuses providing programmable
interconnect structures. These fuse elements consisted of a variety of exotic
metal alloys and/ or polysilicon structures. However, all relied on opening
connections by passing large currents through their small geometries,
thereby physically destroying the fuses.
The melting process in bipolar PLD fuses is difficult to control and often
results in poor and unpredictable programming yields. Since the process is

I Altera Corporation

Page 11

I

II

I Programmable Logic Overview

Data Sheet

I

irreversible, guaranteed results are impossible. The power-hungry bipolar
technology also severely limits integration levels. Altera's pioneering efforts
have replaced bipolar technology with CMOS, and fuses with
reprogram mabIe EPROM bits. These bits are much smaller than fuses,
electrically programmable, and UV-erasable. EPLDs are fully factorytested, guaranteeing 100% programming yield at the customer site. CMOS
technology also provides low-power operation that allows higher
integration levels.
The EPROM cell operates via floating-gate charge injection. The
programming process consists of placing suffici~mt voltage (typically>12 V)
on the drain of the transistor to create a strong electric field and energize
electrons to jump from the drain region to the floating gate. Electrons are
attracted to the floating gate and become trapped when the voltage is
removed. If the gate remains at a low voltage during programming,
electrons are not attracted and the floating gate remains uncharged. Trapped
charge changes the threshold of the EPROM cell from a relatively low
value with no charge present ("erased") to a higher value when
programmed. Figure 10 shows a basic cross-section of the cell technology.
Rgure 10. CMOS EPLD Technology
Gate

First-Level
Polysilicon
(Floating)

Cross-Section

P-Substrate

EPROM Cell

EPROM

N-Channel

P-Channel

EPROM Threshold Shift

/
8

Not
Programmed
(1)

Contact

i

Area

_Poly
Select Line

Programmed
(0)

Current
through
Cell

Floating

Gate

Ground Diffusion

Vr 1 (Not Programmed) Vr 0 (Programmed)
Vokage (Vee) on gate of cell

Page 12

-.

Altera Corporation

I

I Data Sheet

Programmable Logic Overview

Within the EPLD's programmable array, a sense amplifier/comparator
circuit is placed at the end of each product-term line; by setting a reference
voltage into the circuit-halfway between the programmed and
unprogrammed levels-the state of the EPROM cells along the product
term is sensed and used to select the desired logic function. Low-threshold
cells with a logic "1" placed on their select gates (associated input) tend to
pull the product-term line down and cause the logic term to go to a "D."
Transistors with high thresholds do not conduct even when their gates are
at a logic 1, and effectively represent a no-connect. This technologypioneered with EPROM memory in the early 1970's-made it possible to
build Altera EPLDs that can be tested, programmed, and operated reliably.
Altera devices currently use state-of-the-art O.8-micron, CMOS EPROM
technology; work is underway to move to even smaller geometries. Because
the basic logic array consists of N-channel EPROM transistors, EPLD
characteristics are optimized to maximize performance of the N-channel
device. This approach minimizes overall input-to-output delays on the
chip.

EPROM Cell
Margin

To ensure reliable operation in user systems, all EPLDs undergo substantial
factory testing prior to shipment. Foremost among these tests are cellmargin tests, which guarantee the in-service retention of EPROM bit
programming. Cell-margin testing determines the amount of charge trapped
on the floating gate structure.
Charge loss occurs when electrons leak from the floating gate structure
over time, and results in a net reduction in programmed cell threshold.
Charge gain results from an accumulation of charge on the floating gate,
usually caused by electric fields produced by operating the EPLD. Since
charge loss and charge gain mechanisms can affect program retention,
Altera reliability evaluation includes EPLD burn-in at temperatures of up
to 2500 C for periods of a week or more. This burn-in period corresponds to
>100,000 years of operation at 700 C.

Figure 11. EPROM Cell Margin

t

t

Charge
Loss

"0"

Current
through

:: Program

Cell

i Margin:,

I

"

................................. : ......... )4 ••••••••••

:

::

--"

5.5 V

,

Vee

Voltage (Vcc ) on select gate - . . -

IAltera Corporation

"1"

Figure 11 illustrates the concept of cell margin. As
mentioned earlier, EPROM arrays depend on cell threshold
shifts for correct opera tion. Zero and One I-V characteristics
for the EPROM cell are shown. Program margin is a
measure of the spread between the actual device threshold
and the minimum required device threshold for correct
operation.
To calibrate cell margins, Altera EPLDs are subjected to
special test modes that allow EPROM-bit gate voltages to
be controlled externally. Cell margins are measured by
varying this voltage, a method that accurately monitors
cell charge and retention.

Page 13

I

II

I Programmable Logic Overview

Data Sheet

Figure 12 shows a typical programming cycle for Altera EPLDs. The
normal programming procedure consists of the following steps:

Programming

Figure 12. Programming Waveforms

~

___

i'~---------

~.!:.~ va~li~dM

__
dr_"_S____

Program

:

~:~

JPin 1
Data

va

IH
~~

Width

~_P~~~~t~~·~~1_.

1.

The programming pin (Vpp) is raised to the superhigh-input level (nominally 12.5 V).

2.

Rowand column addresses are placed on the
designated pins.

3.

Programming data is placed on the designated
pins.

4.

The programming algorithm is executed with a
sequence of 100-Jls programming pulses separated
by program verify cycles.

5.

Overprogram or margin pulses may be applied to
doubly ensure EPLD programming.

: ___+-_____

·Y:'-

Data in Stable
Pins 3to 10
Program

I

~
Out

.~ Verify

The programming operation is typically performed eight bits at a time on
either Altera-supplied or other approved programming hardware. Altera
EPLDs also feature a Security Bit (i.e., verify-protect bit) that can be
programmed to prevent any interrogation of the device's contents. This bit
can be set during the programming process to ensure EPLD design security.

Latch-Up

Parasitic bipolar transistors are present in the fundamental structure of
CMOS devices. Typically, the base-emitter and base-collector junctions of
these transistors are not forward-biased, so the transistors are not turned
on. Figure 13 shows a cross-section of a CMOS wafer and primary parasi tic
transistors. By connecting the P-type substrate to the most negative voltage
available on-chip (Vss) and the N-type well structure to the most positive
voltage on-chip (Vee), all junctions should, in theory, remain reversebiased. However, two factors can alter this ideal state.

Figure 13. Parasitic Bipolar Transistors In CMOS
Source of Latch-Up

vee

Page 14

As shown in Figure 13, parasitic resistors also
occur in the CMOS structure. These resistors
are of no concern as long as currents do not
flow through the structure laterally. But if
any of the associated diodes turn on for any
reason, I-R drops may occur in the structure.
The initial turn-on of these diodes usually is
the result of power-supply or I/O-pin
transients that exceed the limits of Vss and
Vee. These transients may be induced by
signal ringing and other inductive effects in
the system.

Altera Corporation

I

IData Sheet

Programmable Logic Overview

I

A problem may exist if parasitic structures begin to conduct, since the
effect is regenerative and reinforces itself until potentially destructive
currents flow. This is the silicon-controlled rectifier (SCR) effect called
"latch-up." As current flows through the parasitic transistor, the I-R drop
through the resistor increases, further forward-biasing the base-emitter
junction, as shown in Figure 13. The cycle continues until the current is
limited by drops in the primary current path. However, this current might
reach a level that permanently damages internal circuitry.
Altera components have been designed to minimize the effects oflatch-up,
including power-supply and I/O-pin transients. Under reasonable system
operating conditions, all EPLDs are guaranteed to withstand input voltage
extremes of between Vss-1 V and Vee + 1 V, as well as input currents of
100 rnA or less that are forced through the device pins. To minimize the
possibility of inducing latch-up, Altera recommends a few general system
design guidelines for power and input sequencing to the EPLD. For example,
voltages and logic inputs should be applied in the following order:
1.
2.
3.

VssorGND
Vee (+5 V)
Inputs

When removing power from the EPLD, the order should be reversed: first,
inputs are removed or taken low, then Vee is removed or lowered.
Simultaneous application of inputs and Vee to the device, which might
occur as a power supply ramps during power-up, should be safe. Care
should be taken to ensure that inputs cannot rise faster than supply under
extreme conditions.

Figure 14. Hot Socket Protection
Board

vee

1N4148
EPLD
Board Edge
Connector

.------.---Wr-......

Pin
AHera
- - - - 1 " " l EPLD

1N4148

Electrostatic
Discharge

IA/tera Corporation

In some applications, boards are "hot-socketed" in the
field. The circuitry shown in Figure 14 is recommended
to ensure that latch-up-inducing levels are not applied
to the EPLD under these conditions. Normally, this
circuitry is required only if the EPLD has inputs tied
directly to the edge connector. The diodes clamp the
inputs at acceptable levels and the series resistor further
limits the injection of current into the EPLD input and
clamp diodes. This interface provides maximum
protection.

Electrostatic discharge (ESD) can cause device failure when improper
handling occurs. EPLD handling during the programming cycle increases
exposure to potential static-induced failure. Voltages into the tens of
kilovolts can be generated by the human body during normal activity.
Wearing ground straps during device handling and grounding all surfaces
that come in contact with components reduce the likelihood of damage.

Page 15

1

I Programmable Logic Overview
Figure 15. EPLD Input Protection Structure

Substrate

(GND)

Oats Sheet

I

Altera components include special structures
that reduce the effects of ESO at the pins.
Figure 15 shows a typical input structure.
Diode structures as well as specialized fieldeffect transistors shunt harmful voltages to
ground before destructive currents will flow.
Altera EPLOs typically withstand ESO
voltages> 2 kV, and are thus safe under
normal handling condi tions.

Output Drive
Characteristics

The CMOS push-pull output stages used on Altera EPLOs provide good
AC and DC load-driving capability in a system environment. IOL and lOR
specifications for general-purpose EPLDs are guaranteed at 4 rnA to 24 rnA,
depending on the device. AC output characteristics are typically specified
with 35 pF output loads. Additional output capacitive loading affects the
device output delay. The timing parameter used is tpD (input-output
combinatorial delay). The incremental delay per picofarad of capacitance
is typically ~ 0.1 ns atroom temperature.

System
Noise

Large switching currents can flow through power supply and output pins
during high-performance operation. If a 50-pF capacitor is charged from
o to 5 V in 10 ns, a dynamic current of 24 rnA will flow. If 24 outputs on an
EPLO switch sim ultaneously (for exam pIe, in an EP91 0), the total transient
current can exceed 600 rnA! This current can severely degrade Vee supply
voltage due to the inductive properties of the device and system
environment. Figure 16 shows the distribution of typical inductances that
can contribute to the problem.

Figure 16. Board-Level Noise Problem
Vee

LOUT TRACE

Device
Output
Driver

1

i

Bypass
..............................:cap

Page 16

The key to controlling these inductive effects is to
adequately decouple the Vee supply to ground at each
EPLO with a suitable capacitor or combination of
capacitors. This capacitor can then act as a reservoir of
charge to supply the transient switching needs of the
device. It is recommended that a 0.2 JlF capacitor be
connected from each Vee pin to ground at the device.
High-quality capacitors with low internal and lead
inductance (monolithic ceramic or tantalum) should
be used, and leads must be kept short to limit series
inductance that degrades capacitor effectiveness.
Careful decoupling of the power supply is good design
practice.

Altera Corporation

I

Product Selection Guide
I October 1990, ver. 1
Introduction

This Product Selection Guide summarizes the range of available products
from AI tera:

o
o
o
o
o
o
o
o

General-purpose EPLDs
Function-specific EPLDs
Military-qualified EPLDs
Programmable logic development systems
Programmable logic software
Software warranty
Programming hardware
Programming adapters

II

For detailed descriptions of the Altera products listed here, refer to the
individual data sheets in this data book and to the Micro Channel Adapter
Handbook.

1

Altera Corporation

Page

171

I Product Selection Guide
EPM-Series
EPLDs

Table 1 provides information on the MAX (Multiple Array MatriX) generalpurpose family of EPLDs. MAX (or EPM-series) EPLDs are suitable for
register-intensive random logic, TTL, and PAL integration.

Table 1. General·Purpose EPAf-Series MAX EPLDs
EPLD
(1)

Package
(2)

Temp.
(3)

Speed
Option

tpD1

f MAX

(n8)

(MHz)

Active

Standby

(Registers)

Dedicated
Inputs

EPM5192
EPM5192
EPM5192
EPM5130
EPM5130
EPM5130
EPM5128
EPM5128
EPM5128
EPMS064
EPMS064
EPM5064
EPMS032
EPMS032
EPM5032
EPMS016
EPMS016
EPMS016

J,L,G,Q,W
J,L,G,Q,W
J,L,G,Q,W
G,Q,W
G,Q,W
G,Q,W
J,L,G,Q,W
J,L,G,Q,W
J,L,G,Q,W
J,L
J,L
J,L
D,P,J,L,S
D,P,J,L,S
D,P,J,L,S
D,P,J,L,S
D,P,J,L,S
D,P,J,L,S

C
C
C,I,M
C
C
C,I,M
C
C
C,I,M
C
C
C,I,M
C
C
C,I,M
C
C
C,I,M

-1
-2

25
30
35
25
30
35
25
30
35
25
30
35
15
20
25
15
17
20

62.5
SO.O
40.0
62.5
SO.O
40.0
62.5
SO.O
40.0
62.5
50.0
40.0
83.3
71.4
62.5
100.0
83.3
62.5

380
380
380
275
275
275
250
250
250
135
135
135
155
155
155
115
115
115

360
360
360
250
250
250
225
225
225
125
125
125
150
150
150
110
110
110

192
192
192
128
128
128
128
128
128
64
64
64
32
32
32
16
16
16

8
8
8
20
20
20
8
8
8
8
8
8
8
8
8
8
8
8

-1
-2
-1
-2
-1
-2
-1
-2
-1
-2

ICC3 (mA) ICC1 (mA) Macrocells

I/O

Number
of Pins

64 84; 100
64 84; 100
64 84; 100
64
100
64
100
64
100
68
52
52
68
68
52
28
44
44
28
28
44
16
28
16
28
16
28
20
8
8
20
20
8

Notes to Table 1:
(1)

(2)

(3)

I Page 18

Preliminary data is shown for some parameters. Consult individual device data sheets for
complete information.
Package configurations:
D:
Windowed ceramic dual in-line (CerDIP)
P:
One-time-programmable plastic dual in-line (POIP)
J:
Windowed ceramic J-Iead chip carrier (JLCC)
L:
One-time-programmable plastic J-Iead chip carrier (PLCC)
G:
Windowed ceramic pin-grid array (PGA)
S:
One-time-programmable plastic small-outline integrated circuit (SOIC)
Q:
One-time-programmable plastic quad flat pack (PQFP)
W: Windowed ceramic quad flat pack (WQFP)
C = Commercial (00 C to +70 0 C); I = Industrial/Automotive (-40 0 C to +85 0 C);
M = Military (_55 0 C to +125 0 C).

Altera Corporation

I

Product Selection Guide

1

Table 2 gives information on the "classic" family of general-purpose, zerostandby-power EPLDs. Classic (or EP-series) EPLDs are suitable for random
logic, TTL, and PAL integration.

EP-Series
EPLDs

Table 2. General-Purpose EP-Series Classic EPLDs

(1)

(2)

Temp.
(3)

Speed
Option

EP1830
EP1830
EP1830
EP1810
EP1810
EP1810
EP910
EP910
EP910
EP610A
EP610A
EP630
EP630
EP610
EP610
EP610
EP330
EP330
EP320
EP320
EP320

J,L,G
J,L,G
J,L,G
J,L,G
J,L,G
J,L,G
D,P,J,L
D,P,J,L
D,P,J,L
D,P,J,L,S
D,P,J,L,S
D,P,J,L,S
D,P,J,L,S
D,P,J,L,S
D,P,J,L,S
D,P,J,L,S
D,P,L,S
D,P,L,S
D,P
D,P
D,P

e
e
e,I,M
e
e,1
e,I,M
e
e,1
e,I,M
e
e
e
e,I,M
e
e,1
e,I,M
e
e,I,M
e
e
e,I,M

-20
-25
-30
-35
-40
-45
-30
-35
-40
-12
-15
-15
-20
-25
-30
-35
-12
-15
-1
-2

EPLD

Package

t PD1 f MAX
(ns) (MHz)
20
25

30
35
40
45
30
35
40
12
15
15
20
25
30
35
12
15
29
34
44

ICC3 (mA) I CC1 (mA) Macrocells

Active

62.5
0.15
50.0
0.15
41.7
0.15
40.0
0.15
35.7
0.15
33.3
0.15
41.7
0.10
37.0
0.10
32.3
0.10
83.3 130
83.3 130
83.0
0.15
62.5
0.15
47.6
0.10
41.7
0.10
37.0
0.10
125
75
100
75
45.5
0.15
40.5
0.15
30.3
0.15

Standby
200
200
200
180
180
180
80
80
80
130
130
90
90
60
60
60
75
75
30
30
30

Dedicated

(Registers)

Inputs

48
48

16
16
16
16
16
16
12
12
12
4
4
4
4
4
4
4
10
10
10
10
10

48
48
48
48
24
24
24
16
16
16
16
16
16
16
8
8
8
8
8

1/0

Number
of Pins

48
48

68
68
68
68
68
68

48
48
48
48
24
24
24
16
16
16
16
16
16
16
8
8
8
8
8

II

40;44
40;44
40;44
24;28
24;28
24;28
24;28
24;28
24;28
24;28
20
20
20

20
20

Notes to Table 2:
(1)

(2)

(3)

I Altera Corporation

Preliminary data is shown for some parameters. Consult individual device data sheets for
complete information.
Package configurations:
0: Windowed ceramic dual in-line (CerDIP)
One-time-programmable plastic dual in-line (plastic DIP)
P:
J:
Windowed ceramic J-lead chip carrier (JLCC)
L:
One-time-programmable plastic J-lead chip carrier (FLCC)
G:
Windowed ceramic pin-grid array (PGA)
s: One-time-programmable plastic small-outline integrated circuit (SOIa
C::: Commercial (0° C to +70° C); I ::: Industrial! Automotive (-40 0 C to +85° C);
M == Military (-55° C to +125° C).

Page

191

I Product Selection Guide
Table 3 provides information on the function-specific Stand-Alone
Microsequencer (SAM) and Synchronous Timing Generator (STG) EPLDs.
These EPS-series EPLDs are suitable for implementing high-performance
state machines, waveform generators, and control logic.

FunctionSpecific
EPLDs

Table 4 gives information on the Micro Channel bus interface (EPB-series)
EPLDs, which provide all the essential functions to interface a PS/2 add-on
card with the Micro Channel bus. (Refer to the Micro Channel Adapter
Handbook for detailed information on EPB-series EPLDs.)
Table 3. EPS-Series SAM and STG EPLDs
EPLD
(1)
EPS448
EPS448
EPS448
EPS464

Pkg.
(2)

Temp. Speed fMAX ICC2 (rnA) ICC1 (rnA) Microcode
(3) Option (MHz) Active Standby
EPROM

D,P,J,L
C
C
D,P,J,L
D,P,J,L C,I,M
J,L,Q,W C

-30
-25
-20

30
25
20

Branch
EPLD

Stack Dedicated
Inputs

140
95
448 x 36 768 p-term 15x 8
448 x 36 768 p-term 15x 8
140
95
140
95
448 x 36 768 p-term 15x 8
Preliminary Information-<:onsult factory

8
8
8
4

110 No. of
Pins
16
16
16
32

28
28
28
44

Table 4. EPB·Series Micro Channel Bus Interface EPLDs
EPLD
(1)
EPB2001
EPB2002A

Package
(2)

Description

Temperature
(3)

J,L
L,P

C
C

Number
of Pins

Single-chip interface adapter for PS/2 Micro Channel
DMA arbitration support chip for PS/2 Micro Channel

84
28

Notes to Tables 3 & 4:
(1)

(2)

(3)

I Page 20

Preliminary data is shown for some parameters. Consult individual device data sheets for
complete informa tion.
Package configurations:
0:
Windowed ceramic dual in-line (CerDIP)
P:
One-time-programmable plastic dual in-line (POlP)
J:
Windowed ceramic J-Iead chip carrier (JLCC)
L:
One-time-programmable plastic J-Iead chip carrier (FLCC)
Q:
One-time-programmable plastic quad flat pack (PQFP)
W: Windowed ceramic quad flat pack (WQFP)
C =Commercial (0 0 C to +70 0 C); I =Industrial! Automotive (-40 0 C to +85 0 C); M =Military
(-55 0 C to +125 0 C).

Altera Corporation

I

Product Selection Guide

I

Table 5 provides information on Altera's military-qualified MAX
(EPM5000-series) EPLDs; Table 6 gives information on military-qualified
classic (EP-series) EPLDs.

MilitaryQualified
EPLDs

Table 5. Military-Qualified EPM-Series MAX EPLDs
EPLD
(1)
EPM5128
EPM5128
EPM5064
EPM5032
EPM5016

Pkg. Assurance tpD1 fMAX
(2) Level (3) (ns) (MHz)
J
G

J
D,J
0

B
8838
8838
8838
8838

35
35
35
25
20

40.0
40.0
40.0
62.5
62.5

Icc3 (mA) Icc1 (mA) Macrocells Dedicated I/O Number Altera Mil.
Active

Standby

(Registers)

Inputs

350
350
225
225
175

300
300
200
200
150

128
128
64
32
16

8
8
8
8
8

52
52
28
16
8

of Pins

Drawing (4)

68
68

020-00827
020-00827
020-00968
020-00828
020-00967

44
28
20

Notes to Table 5:
(1)

(2)

(3)

(4)

I Altera Corporation

All military-qualified EPLDs are rated to military temperatures (-55 0 C to +125 0 C).
Preliminary data is shown for some other parameters. Consult individual device data
sheets for complete information.
Package configurations:
D:
Windowed ceramic dual in-line (CerDIP)
J:
Windowed ceramic J-Iead chip carrier (JLCC)
G:
Windowed ceramic pin-grid array (PeA)
Product Assurance Levels:
883B:
Processed to MIL-STD-883, current revision.
B:
Fully compliant with deviation to MIL-STD-883, current revision. (Consult
Altera for information on specific deviations.)
DESC:
DESC Standard Military Drawing (SMD). Consult Altera or DESC for
availability.
A Military Product Drawing (MPD) is prepared in accordance with the appropriate
military specification format. When a Source Control Drawing (SCD) is necessary, the
appropriate MPD is required for proper SCD preparation.

Page 21

II

Product Selection Guide

Table 6. Military-Qualified EP-Serles Classic EPLDs
EPLD
(1)
EP1810
EP1810
8946901 XX
8946901YC
EP1800
EP1800
8854901YC
8854902YC
EP910
EP910
EP900
EP900
8854801QA
8854801 XX
EP610
EP610
8947601 LX
8947601 XX
EP600
EP600
8686401 LA
8686401 XX
EP320
EP310
8863501RA

Pkg. Assurance tPD1 'MAX Icca (mA) Icc1 (mA) Macrocells
(2) Level (3) (ns) (MHz)
Standby (Registers)
Active

J
G

J
G

J
G
G
G
D

J
D

J
D

J
D

J
D

J
D

J
D

J
D
D
D

B
883B
DESC
DESC
B
883B
DESC
DESC
883B
B
883B
B
DESC
DESC
883B
883BX
DESC
DESC
8838
883BX
DESC
DESC
883B
883B
DESC

45
45
45
45
75
75
90
75
40
40
60
60
60
60
35
35
35
35
55
55
55
55
45
50
50

33.3
33.3
33.3
33.3
18.2
18.2
16.1
18.2
32.3
32.3
20.0
20.0
20.0
20.0
37.0
37.0
37.0
37.0
22.2
22.2
22.2
22.2
30.3
31.3
31.3

240
240
240
240
180
180
150
180
150
150
100
100
100
100
100
100
100
100
60
60
60
60
40

0.9
0.9
0.9
0.9

48
48

48
48
48
48

48
0.9
0.9

0.9
0.9
0.9
0.9

48
24
24
24
24
24
24
16
16
16
16
16
16
16
16
8
8
8

Dedicated
Inputs
16
16
16
16
16
16
16
16
12
12
12
12
12
12
4
4
4
4
4
4
4
4
10
10
10

L10

48
48
48
48

48
48
48
48
24
24
24
24
24
24
16
16
16
16
16
16
16
16
8
8
8

Number Altera Mil.
of Pins Drawing (4)
68
68
68
68
68
68
68
68
40
44
40

44
40
40
24
28
24
28
24
28
24
28
20
20

02D-00782
02D-00782

02D-00509
02D-00205

02D-00935
02D-00935
02D-00210
02D-00521

02D-00522
02D-00522

02D-00194
02D-00194

02D-00209
02D-00179

20

Notes to Table 6:
(1)

(2)

(3)

(4)

I Page 22

All military-qualified EPLDs are rated to military temperatures (-55 0 C to +125 0 C).
Preliminary data is shown for some other parameters. Consult individual device data
sheets for complete information.
Package configurations:
D: Windowed ceramic dual in-line (CerDIP)
J:
Windowed ceramic J-Iead chip carrier aLCC)
G:
Windowed ceramic pin-grid array (PGA)
Product Assurance Levels:
883B:
Processed to MIL-STD-883, current revision.
883BX:
Processed to MIL-STD-883, current revision with modified J-Iead package
dimension.
B:
Fully compliant with deviation to MIL-STD-883, current revision. (Consult
Altera for information on specific deviations.)
DESC Standard Military Drawing (SMD). Consult Altera or DESC for
DFSC:
availability.
A Military Product Drawing (MPD) is prepared in accordance with the appropriate
military specification format. When a Source Control Drawing (SCD) is necessary, the
appropriate MPD is required for proper SCD preparation.

Altera Corporation

I

Product Selection Guide

I

Figure 1 shows the overall design environment provided by Altera
development systems, software, hardware, and EPLDs.

Design
Environment

Figure 1. Altera Design Environment
Design Entry
Third-Party
Design
Entry

...

....

PLS-EDIF

r-+
r+-

Altera
Hardware
Description
Language

Design Verification

Design Processing

Third-Party
Simulation

j

~PLS-APOLLOl

II

.

l
H-+
...
r!-

K+

MAX+PLUS

:

.

MAX+PLUS
Simulator

EPMSeries

I

(MAX)

Schematic
Capture
Boolean
Equation

4-+

State Machine

A+PLUS

Truth Table

State Machine
Assembly
language

:.

SAM+PLUS
Simulator
(SAMSIM)

SAM+PLUS

I"
Table

...........................................

I A/tera Corporation

MCMap

EPSeries L.,

A+PLUS
Simulator
(FSIM)

:

r--+

Device
Programming

~

EPS: Series

i

(SAM)

j EPBj Series

.: ................................................. .:.............................................:

Page

231

I Product Selection Guide
Table 7 shows the software and hardware products available from Altera.
Programmable Logic Development Systems (with the PLDS- or PLeADprefix) are stand-alone combinations of hardware and software.
Programmable Logic Software packages (with the PLS- prefix) are
software-only products that may be used together with programming
hardware from Altera (e.g., PL-ASAP) or third-party manufacturers.

Development
Systems,
Software &
Hardware

Software

Table 7. Altera
Development Products

~



INPUT

g
110

110
INPUT
INPUT

110
0
Z



3

---

3

---

~

INPUT

110

INPUT

110

INPUT

110

INPUT

110

INPUT

110

110

INPUT

110

INPUT

110

INPUT

I/O

GND

INPUT

5
Q,

~

DIP

IAltera Corporation

Q,

0

z

CI

5
Q,

~

~

J-Lead

~

vee

INPUTIQJ(
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GND

LO
LO
LO
LO
1.0

LO
LO
LO
INPUT

sole

Page 41

EP330

Data Sheet

Absolute Maximum Ratings

I

I

Symbol

Note: See Operating Requirements for EPLDs in this data book.

Conditions

Parameter
Suepl~

Vcc

voltage

I Pr~ramming supel~ vOltage

I Vpp

I

Min

Max

Unit

With respect to GND

-2.0

7.0

V

See Note (1)

-2.0

14.0

V

1
1 -2.0
1_--.:.7~.0__:_----=V~_
1 VI
1 DC input voltage
I:-I-M!....AX----il·-DC-V--!-cc-o-rG.....;N~D-cu-rr-e-nt----il---------i~60
160
A

I DC outeut current, eer ein

1 lOUT

I PD

I Power dissieation

. ~25 --++800...;:2..;;..5--I----.,;.m:;.;;.wA~-

I
.

I T 8TG
1 Storage temperature
1 No bias
1__-6....:...:..5_.1; __+:.....;,1..:,.50:""--l-_o:.....;,C=--_
1:=T==-A:...::.M:B:===-=--il,·=A~m~b~ie:n~t_t-e:m:pe~r_a-t~ur~e~~~~~~~~~=il-_-u_-n_d~e-r_-b_ia~s~~~~~~~~~-=I__-6....:...:..5_.1,__+_1_35__ .....;C=--_
o

I

__

Recommended Operating Conditions
Parameter
I Symbol I
I Suppl~ vOltage
I Vcc

1 TA

I Input vOltage
I Output vOltage
I Operating tem~rature
I Operating tem~rature

1 Tc

1 Case temperature

1t R

I Input rise time

1 VI
1 Va
1 TA

I Input fall time

1t F

DC Operating Conditions
See Note (3)

Conditions

Min

I
I

I

For commercial use
For industrial use

1 For military use

5.25

V

0

Vcc

V

0

Vcc

V

0

+70

°C

-40

+85

°C

-55

+125

°C

20

ns

. See Note (2l

20

ns

Conditions

Min

IOH =-12mADC

VOH

High-level CMOS output voltage

IOH =-12mADC

VOL

Low-level output voltage

IOL =24 mA DC

Input leakage ament

V I = V cc or GND

~

Va = Vee or GND

-10

1_I. .,:C: .=C:. .:. .1_ _II_V.=,cc::::..-su....:..P...:....P...:..,ly_c_ur_re_n.....;t(:..,.st_an_d_b.:...:y}_1 V I = V CC or GND, No load

· I cC31. V CC supply current (active)
I

Max

-03

High-level TTL output voltage

. Tri-state output off-state current

I
Vee +0.3 I
08
I

Typ

2.0

1 Low-level input voltage

Page 42

4.75

See Note (2)

I

V OH

. I OZ

Unit

Vee = 5 V ± 5%, T A = 0° C to 70° C for commercial use
Vee = 5 V ± 10%, TA = --40° C to 85° C for industrial use
Vcc = 5 V ± 10%, Tc = -55° C to 125° C for military use

I Symbol I
Parameter
I High-level input VOltage
I VIH

18

Max

I VI =V ee or GND, No load,

V
V

O.5~

3.84

~

Unit

~~

.
40
45

+10

.

~

75

mA

75

mA

.

. f = 1 .0 MHz, See Note (4)

A/tera Corporation

I

I Data Sheet

EP330

I

Capacitance See Note (5)

I symbol'
Parameter
I C IN
I Input capacitance

Conditions
I
I V IN = 0v, f = 1.0 MHz

I-C---"-'OU'-T---I Output capacitance

I VOUT=

I

I

C elK

Clock pin capacitance

IN

Max

Unit

10
15
I 10

I

I

pF
pF

pF

vcc = 5 V ± 5%, TA = 0° C to 70° C for commercial use
Vee = 5 V ± 10%, TA = -40° C to 85° C for industrial use
Vee = 5 V ± 10%, Te = -55° C to 125° C for military use

AC Operating Conditions

EP3~-12 I EP3~-15 1 1
I Min I Max I Min I Max I Unit I

.--------------11

I

I Symbol I
I t PD1
I t PD2
I t PZX
I t PXZ
I

0v, f = 1.0 MHz
I V = 0V, f = 1.0 MHz

I~.
I

t 10

Parameter

1Input to non-registered output
I/O input to non-registered output
1Input to output enable
1Input to output disable
1

11/0 input pad and buffer delay

Conditions
C1=

35 pF

C1=

5pF, See Note (6)

11:-_11:~1231 __1: 1165

I

nnss I I I C I

g

1--1-1-2-I--I~I---;;-I
1 1 12 I 115 1 ns 1
1

1

1

1_ _1

1

I

ns 1

Synchronous Clock Mode

I

I_I

I: I

I~: I
I~: I

________;________ , EP3~-12 EP3~-15
I Symbol I
Parameter
Conditions
I Min I Max I Min I Max I Unit I
1f MAX 1Maximum clock frequency
-S-e-e-N-o-te-(-7)-------1 125 I
1100 1 1MHz 1
I

I~I Input setup time
I-t-H--I Input hold time

I

6
0

I

1

I--r;-I Clock high time

1

4

1

I t Cl I Clock low time
I t C01 1Clock to output delay
1t CNT 1Minimum clock period

1

I: I

I4 I
1 1 8 I I 10 I ns I
1 1 10 I I 12 1 ns I
I-f-=CN=T'--'I"-I-nt-er-n-al-m-a-Xi-m-'"um-fr-eq-u-e-ncy----'I--S-ee-N-o-te-(-4)-------1 100 I
I 83.3 I
I MHz I
Notes to tables:
(1) Minimum DC input is -0.3 V. During transitions, inputs may undershoot to -2.0 V
or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
(2) For all clocks: tR and tF = 20 ns.
(3) Typical values are for TA =25° C and Vee =5 V.
(4) Measured with a device programmed as an 8-bit counter.
(5) Capacitance measured at 25° C. Sample-tested only. Pin 11 (high-voltage pin during
programming) has maximum capacitance of 20 pF.
(6) Sample-tested only for an output change of 500 mV.
(7) The fMAX values represent the highest frequency for pipelined data.

IAltera Corporation

Page 43

EP330

Data Sheet

I

Product Availability
Availability

Grade
Commercial

(0° C to 70° C)

Industrial

(-40° C to 85° C)

Consult factory

(-55° C to 125° C)

Consult factory

I Military

EP330-12, EP330-15

Note: Only military-temperature-range EPLDs are listed above. MIL-STD-883-compliant
product specifications are provided in Military Product Drawings (MPDs), available from
Altera's Marketing Department by calling 1 (800) SOS-EPLD. These MPDs should be used
to prepare Source Control Drawings (SCDs). See Military Products in this data book.

Figure 9 shows outpu t drive characteristics for EP330 I/O pins and typical
supply current versus frequency for the EP330.
Figure 9. EP330 Output Drive Characteristics and Icc vs. Frequency
55mAr-------------------------~

100

101..

ci
~

I-

ci SOmA

~

~

§.

~

'E

§.

~

:;

Q)
~

Vee =5.0V
= 25° C

0
c(

Sa.
S

TA

0
0

0

30mA

a

2

3

4

5

Va Output Voltage (V)

I Page 44

40 mAL--------

>

()

10 KHz

1 MHz

100 MHz

Maximum Frequency

A/tera Corporation

I

EP320
Features

o
o
o
o

High-performance 8-macrocell EPLD
Combinatorial speeds with tpD = 30 ns
Counter frequencies up to 28.6 MHz
Pipelined da ta rates up to 45.5 MHz
Very low power
Icc = 3 rnA (typical) for an 8-bit counter at 1 MHz
Icc = 10 JlA (typical) in standby mode
Available in 20-pin windowed ceramic and plastic, one-timeprogrammable dual in-line packages (DIPs)
Macrocell flip-flops can be individually programmed for registered or
com bina torial opera tion

_Fi_gu_re_1_0_s_h_o_w_s_p_i_n_-D_u_ts_f_o_r_th_e_E_p_3_2_O_E_P_L_D_.__________

Figure 10. EP320 Pin-Out Diagram
Package outline not drawn to scale.

vee
110
110
1/0
1/0

110
1/0
1/0

INPUT

DIP

IAltera Corporation

Page 45

fJ

EP320

Data Sheet

Absolute Maximum Ratings

Note: See Operating Requirements for EPLDs in this data book.

Parameter

Symbol
vee

Min

Conditions

Supply voltage

With respect to GND
See Note (1)

Vpp

Programming supply voltage

VI

DC ineut vOltage

I MAX

DC Vee or GND current

'OUT

I

I DC oU!eut current, eer ~in
I Power dissipation

I

-2.0

I

-2.0

I

-2.0

I

-25

I

I

-80

Max

I
I
I

I
I

~5

7.0

I

Unit

I

V

13.5

V

7.0

V

+80

mA

+25

mA

I

400

mW

+150

DC

DC _
~T~AM=B~____•__
A_m_b_ie_nt_~_m~~~ra_ru_~
___________ ._U_n_d_e_rb_ia_s___________•________
•______________
~5
+135

Recommended Operating Conditions

~I

Parameter

IV;--I
I
I
VI

I v0

E
A

TA
Tc

It R

I tF

V IH

I V OH

Min

Conditions

4.75

See Note (2)

I

Input voltage

I Output voltage

I

I-o-~--!...ra-ti-ng--te..::m:....~-r-a-tu-re---------'I'-Fo-r-co-m-m-e-r-ci-al-u-se-----

~4.5)

Max

Unit

5.25 (5.5)

V

0

Vcc

V

0

Vcc

v

0

+70

DC

I O~rating tem~rature

I For industrial use

-40

+85

DC

I For military use

-55

+125

DC

I Input rise time

I See Note (3)

500

ns

Max

Unit

2.0

Vcc +0.3

V

-0.3

0.8

v

I Case tem~rature

I-I-np~u-t-m-ll-ti-m-e--------------~Ii-se-e-N-o-~--!...~~)--------- ________•._____________
__
500
ns

See Note (4)

I V IL

I

Supply voltage

DC Operating Conditions

Symbol

I

I

Vee = 5 V ± 5%, T" = 0° C to 70° C for commercial use
Vcc = 5 V ± 10%, TA = -40° C to 85° C for industrial use
Vee =5 V ± 10% Tc =-55° C to 1250 C for military use

Conditions

Parameter

I High-level ineut voltage

I Low-level input voltage

I High-level TTL output voltage

Typ

Min

I OH = -8 mA DC

v

2.4

I-V,.:OH::...:.-_____11•. . ;,H. . ;.igK,;.h.;. .-I;.;:. eve.:. .;. :. 1C..; ,.;. .;. ;M. .; ;.O. .; ;.S.,; o. . ;.ut:.!:.p.=,:ut. . ;,v;.;:. ol. . ;,ta,.2g.. .;,e___1~O~H~=_-4
__m
__
A_DC
_____1

3.84

I

I

V OL

Low-level oU!eut voltage

I Ol = 8 mA DC

I

, OZ

Tri-state output off-state current

V 0 = VCC or GND

~_I~

I

0 45

V

I

I~'

~'I~----_I_.,;;ln~lP~lu....;,tl...;;;.ea~k~a&gje~ru.;...rr...;;;.e.;...nt~------~-V~,-=-V..::ee~o_r_G_N_D___I~~~

.:. ; =~V.; ;.!c. .; c;. :.o;.;:. r. :. . :G~N.;.:;.D~_I!~I

_'CC
__1_ _ _-!-_V_c_c_s_U_pp_ly_ru
__rr_e_nt_(s_ta_n_d_by_)____!-=..;V.:;..'

Noload,SeeNote(5)

!-

ICC2

Vee supply rurrent

VI =Vee or GND

(non-rurbo mode)

No load, f = 1.0 MHz

10

I

I

150
JlA
~~

I

3

5 (15)

mA

18

30(40)

mA

See Note (6)

Vee supply rurrent

VI =Vee orGND

(turbo mode)

No load, f = 1.0 MHz
See Note (6)

Page 46

A/tera Corporation

I

IData Sheet

I

EP320

Capacitance See Note (7)

I

I
I
I

I

Parameter

I

Symbol

I

I Input capacitance
I Output capacitance

C IN
C OUT

I

CCLK

Conditions

V,N-OV, f -1.0MHz

I

Clock pin capacitance

AC Operating Conditions

VOUT= 0 V, f= 1.0 MHz

EP32O-1

EP320-2

Min

Min ,

Max
29

nOn_-registe_red

I'

t

PZX

I Input to output enable

t

PXZ

I

VO.input to nonregistered output

'Input to output disable

, C1

=SO pF

I

I

pF

10

pF

10

F

No;;!:bo

n

I~ fJ
I IMax'1_15__L:J
Min

Note (8)

1 44

1 30 1

1 35

I 45 1

15

1

I I 30 I

I 35

I 45 I

15

I~

15

I~

I~:t: ~:F I I I I 1 I I
35

30

Il-t1 0 - -1-~~-I~~P-utp-ada-ndb-uffe-r ---->--<--1
1

~

Max'

I 34

l

PD2

10

Vee = 5 V ± 5%, T A = 0° C to 70° C for commercial use
Vee = 5 V ± 10%, T A = -40° C to 85° C for industrial use
Vee = 5 V ± 10%,.Tc = -55° C to 125° C for military use

Parameters

I

I

V IN = 0 V, f = 1.0 MHz

ITiming
I
I
1:===SY=mb==oI=~:I:=====p=ara=me==te=r====~:I:==Co==nd=it=io=n=s
I,_t
PD1_1----l.:-,;.:~~~~:0
I =,I II II
,. t

~I~
nlt

Min

45

1 1 1 1 1 1

1

1

1

1-

1

0

ns

I

I I
ns

Synchronous Clock Mode
g
1_7i_im_in__p,_8_ra_me_te_"______;_ _ _ _ _1 EP320-1

I

1t

I
r

Symbol

Parameter

I

Conditions

I Min I~

'-f-M-A-x--!I"-Ma-Xi-m-um-cl-oc-k---!I'-No-te-(-1D-~- - ' 45.5"

I

frequency

su

I

Input setup time

I

22

l_t....:.H-'--__I,_ln....:...p_ut_ho_ld_t_im_e_ _ _,·_ _ _ _
ItCH

I t CL

t COt
I t CNT

I Clock high time

I Clock low time

Clock to output delay
I Minimum clock period

'I·

100

I

I

I 10 I

1

II'

,I.'

· f eNT

I' Internal maximum
frequency

I' Note (6)

1 28 .6 1

IAltera Corporation

II'.'

Min

EP320

40'

130.3

25'

133

12'
12

I

317
5

I

I ~!:bo I

I Max I Min I Max I

01

,I.'

1

I

I EP320-2

'0

'16
16

I

1201

1401
25 1

1 20

Note (8)

0

I Unit I
I~

~ ns
I 0 I~
I 0 'ns'
I 0 I ns I
251
olnsl
sol olnsl
1

0

I MHz 1

Page

471

EP320

Data Sheet

I

Notes to tables:
Minimum IX input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
(2) Numbers in parentheses are for military and industrial temperature versions.
(3) For all clocks: tR and tF =250 ns (100 ns).
(4) Typical values are for TA = 25° C and Vee = 5 V.
(5) When in non-turbo mode, an EPLD will automatically enter standby mode if logic
transitions do not occur (approximately 100 ns after the last transition).
(6) Measured with a device programmed as an 8-bit counter.
(7) Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for
dedicated clock inputs only. Pin 11 (high-voltage pin during programming) has a
maximum capacitance of 20 pF.
(8) See "Turbo Bit" in this data sheet.
(9) Sample-tested only for an output change of 500 m V.
(10) The fMAX values represent the highest frequency for pipelined data.
(1)

Product Availability

I
I Commercial
I Industrial
I Military

Availability

Grade

EP320-1, EP320-2, EP320

(0° C to 70° C)
(-40° C to 85° C)

EP320

(-55° C to 125° C)

EP320

Note: Only military-temperature-range devices are listed above. MIL-STD-883-compliant
product specifications are provided in Military Product Drawings (MPDs), available from
Altera's Marketing Department by caning 1 (800) SOS-EPLD. These MPDs should be used
to prepare Source Control Drawings (SCDs). See Military Products in this data book.

Figure 11 shows output drive characteristics for EP320 I/O pins and
typical supply current versus frequency for the EP320.

Figure 11. EP320 Output Drive Characteristics and Icc vs. Frequency
100 rnA , . - - - - - - - - - - -_ _ ___.
100

ci.

Turbo Mode

>.

I-

;(

ci.

80

~

.§.
E
~

:;

Vee =5.0V
TA = 25° C

;(

.§.

Vee =5.0V
TA = 25° C

60

<.)

:5
a.
:5
0

10 rnA

~

~

40

1.0 rnA

g
100 JlA

0

2

3

4

5

Vo Output Voltage (V)
Page 48

1 KHz

10 KHz 100 KHz 1 MHz 10 MHz 40 MHz

Maximum Frequency
Altera Corporation

I

EP600-Series EPLDs
High-Performance
16-Macrocell Devices

IOctober 1990, ver. 1
Features

DataSheet I

o
o
o
o
o
o
o
o

o
o
o
o
General
Description

High-density replacement for TIL and 74HC with up to 600 gates
EP630 and EP610 offer "zero power" (typically 20 JlA standby)
Very high speed (EP610A tpD = 12 ns)
Advanced CMOS EPROM technology to allow device erasure and
reprogramming
Asynchronous clocking of all registers or banked register operation
from two synchronous clocks
16 macrocells with configurable I/O architecture, allowing up to 20
inputs and 16 outputs
Individually programmable registers providing D, T, SR, or JK flipflops with individual asynchronous Clear control
100% generically testable to provide 100% programming yield
Programmable Security Bit for total protection of proprietary designs
A+PLUS software support featuring schematic capture, Boolean
equation, state machine, truth table, and netlist design entry methods
Available in space-saving windowed ceramic and plastic 24-pin,
300-mil DIP and 28-pinJ-Iead packages, or plastic 24-pin, 3OO-mil SOIC
packages
Extensive third-party software and programming support

Altera's EP600-series Erasable Programmable Logic Devices (EPLDs) can
implement up to 600 eqUivalent gates of 551 and MSI logic functions in
space-saving windowed ceramic or one-time-programmable (OTP) 24-pin,
300-mil DIP and 28-pin J-Iead (JLCC and PLCC) packages, or OTP plastic
24-pin, 300-mil SOIC packages. See Figure 1.
EP600-series EPLDs use sum-of-products logic that provides a
programmable-AND/fixed-OR structure. These EPLDs accommodate
combinatorial and sequential logic functions with up to 20 inputs and 16
outputs. Altera's proprietary programmable I/O architecture allows the
designer to program output and feedback paths for combinatorial or
registered operation in active-high and active-low modes.
EP600-series EPLDs can individually program D, T, SR, or JK flip-flop
operation for each output without sacrificing product terms. In addition,
each register can be individually clocked from any of the input or feedback
paths in the AND array. These features make it possible to simultaneously
implement a variety of logiC functions.

IAltera Corporation

Page 49 I

2

Data sheetl

EP600-Series EPLDs

Figure 1. Package Pin-Out Diagrams
5
g ~

..Jii:
0

0

~

0

~

5
~

Package outlines not drawn to scale.

g
VCC

3

2

1

28

27

110

INPUT

110

110
110

I/O

0

110
I/O

110
I/O

10

NC

11

21

1/0

I/O

110

I/O

110

I/O

110
110

110

110

NC
12

13

g 5
0.
~

14

15

0

0

(!l

(!l

z

Z

16

g
0

17

110

18

INPUT

g
5
0.

CLK2

~

J-Lead

DIP

vee

ClK1

INPUT

INPUT

1.0
1.0
1.0

1.0
1.0
1.0

1.0
1.0
1.0
1.0
1.0
INPUT
GND

1.0
1.0

1.0
1.0
1.0

INPUT

ClK2

sOle

J-Lead

DIP

sOle

Ceramic/Plastic

Ceramic/Plastic

Plastic

EP610A
EP630
EP610

EP610A
EP630
EP610

EP610A
EP630
EP610

The CMOS EPROM technology in EP600-series EPLDs can reduce active
power consumption to less than 40% of the power required by equivalent
bipolar devices, without losing speed. This reduced power consumption
makes the EP600-series EPLDs highly desirable for a wide range of
applications. Moreover, these EPLDs are 100% generically testable and
can be erased with UV light. Designs and design modifications can be
implemented quickly, eliminating the need for post-programming testing.
Logic is implemented with Altera's A+PLUS Development System, which
supports schematic capture, Boolean equation, state machine, truth table,
and netlist design entry methods. After the design is entered, A+PLUS
automatically translates it into logic equations, performs Boolean
minimization, and fits it into the EPLD. The device may then be
programmed in seconds at the designer's desktop to create customized
working silicon. In addition, extensive third-party support exists for design
entry, design processing, and device programming.

Page 50

Altera corporatio~

IData Sheet
EP600·
Series
EPLDs

EP60O-Serles EPLDs

The EP600 series includes the EP610A, EP630, and EP610 EPLDs. These
EPLDs are JEDEC-file-compatible, allowing a single JEDEC file to be used
for progamming any of the EPLDs.

EP610A
The EP610A is fastest member of the EP600 series. It has an input-to-nonregistered-output delay (tpo) of 12 ns, which is ideal for address decoding.
The EP610A offers a 36% faster clock-to-output delay (teo = 6 ns) than a
CMOS 22V10 and can easily integrate logic operating at today's faster
system speeds. The EP610A is fabricated on an ad vanced O.8-micron process,
and supports 16-bit counter frequencies of up to 83 MHz.

EP630
The EP630 is fast and offers a low-power standby mode. This EPLD can
implement a 16-bit counter at up to 83 MHz, and typically consumes 45
rnA when operating at 1 MHz. It offers 60% more logic and 6 more flipflops than the 22V10. It is fabricated on a 1-micron process, and is available
with maximum tpo values of 15 ns and 20 ns.

EP610
The EP610 combines high speed with low power. It can implement a 16-bit
counter at up to 40 MHz, and typically consumes 32 rnA when operating at
1 MHz. The EP610 is fabricated on a 1.2-micron process and is available in
all tempera ture ranges. Both MIL-STD-883B-compliant and DESC-approved
parts are available. The EP610 has maximum t po values of 25 ns, 30 ns,
35 ns, and 40 ns.

IA/tera Corporation

Page 51

EP600-5eries EPLDs

Da,. Sheet

I

EP600-series EPLDs use CMOS EPROM technology to configure
connections in a programmable-AND logic array. EPROM connections
are also used to construct a highly flexible programmable I/O architecture
that provides advanced functions for user-programmable logic.

Functional
Description

EP600-series EPLDs have 4 dedicated data inputs, 2 synchronous clock
inputs, and 16 I/O pins that can be configured for input, output, or
bidirectional operation on a macrocell-by-macrocell basis.
Figure 2 shows the EP600-series macrocell. Each macrocell contains 10
product terms for the following functions: 8 product terms are dedicated
to logic implementation; 1 product term is used for Clear control of the
internal register; and 1 product term implements either Output Enable or
an asynchronous Clock.
Figure 2. Logic Array Macrocell
0

4

1

5

Synchronous
Clock

7

8

10111,i!13'4'5'6'7'8'9 0 1

~. 4 5 ~'7 ~

931) 1

OEICLK

~333435 ~37 i!l39

vcc~

OE

~~

OElCLK

'")-

~

t!

-g

"'0

e
Cl.

1

t--<}-

2

t--<}-

4

~t>

t--<
~

5

H

6

110
Architecture
Control

t

...

.,....
~

1I0Pin

rJ-

H}-

7

'---"

-D--

CLEAR

~

~

~

~

~

)n nnCnUa1 un6nnna

2

3

4

5

6

7

8

9

Macrocell Feedback

I---

10 11 14 15 16 17 18 19 20 21 22 23

Figure 3 shows the complete block diagram of an EP600-series EPLD. The
internal device architecture has a sum-of-products (AND/OR) structure.
Inputs to the programmable AND array come from the true and
complement signals of the 4 dedicated data inputs and 16 I/O feedback
signals. The 4D-input AND array has 160 product terms distributed among
the 16 macrocells. Each product term represents a 40-input AND gate.
In the erased state, the true and complement of the AND-array inputs are
connected to the product terms. An EPROM control cell is located at each
intersection of an AND-array input and a product term. During
programming, selected connections are opened, allowing any product
Page 52

Altera Corporation

I

IData Sheet

EP6tJO-Serifl. EPLD.

Rgu~1E~&mQBlockDmgmm

Numbers in parentheses are br J-/ead packages.
40

1 (2)
2(3)

CLK1

INPU

INPUT

23 (27)

Il.K

3(4)

Macrocell9

Macrocell1

22(26)

Macrocell10

Macrocel12

21 (25)

••
•

••
•

Macrocell15

Macrocell7

Macrocell16

Macrocell8

Il.K

Kl
Alchiledure

4 (5)

Control

VO
9 (10)

Alchiledure

16(20)

Control

10(12)

15(18)

INPUT

11 (13)

C>..;;...;...:;..:....----{x::=t.._____--,c~----....J

I Altera Corporation

Pag,,53

Data Sheet

EP600-Series EPLDs

I

term to be connected to a true or complement array input signal with the
following results:

o
o
o

If both the true and com plement of an array input signal are connected,

the output of the AND gate is a logic low.
If both the true and complement of any array input signal are
programmed "open," a logic "don't care" results for that input.
If all inputs for a given product term are programmed "open," the
output of the corresponding AND gate is a logic high.

Two dedicated clock inputs (which are not available in the AND array)
provide the signals used for synchronous clocking of EP600-series internal
registers. Each signal is positive-edge-triggered and has control over 8
registers: CLJC! controls macrocells 9 to 16; CLJC2 controls macrocells 1 to
8. The programmable I/O architecture allows each of the 16 internal
registers to have a synchronous or asynchronous Clock.

I/O
Architecture

The EP600-series architecture provides each macrocell with over 50
programmable I/O configurations. Each macrocell can be configured for
combinatorial or registered output, with programmable output polarity.
One of four register types (D, T, JK, and SR) may be implemented in each
macrocell without additional logic. I/O feedback selection can be
programmed for registered or input feedback. The I/O architecture can
also individually clock each internal register from any internal signal.

OE/CLK
Selection

Figure 4 shows the two modes of operation provided by the OE/CLK
Select multiplexer. This multiplexer, which is controlled by a single EPROM
control bit, may be individually configured at each I/O pin.

Figure 4. DE/eLK Select Multiplexer
Mode 0:
OE,. Product-Term-Controlled
ClK ,. Synchronous

Mode 1:

OE. Enabled
ClK • Asynchronous

Synchronous
Clock

SyndYonous

Clock

vee
OE

AND
Array

OE

ClK

ClK

DATA

Maaocel
Ou~

Maaocel
110 Register

The register is clocked by the synchronous dock signa/, which is
ccmmon to seven other maaocells. The output is enabled by the logic
from the product term.

Page 54

Maaocel
110 Register

Bulter

The output is permanently enabled and the register is docked
by the product term, which aRows gated clocks to be generated
in EP600-series EPLDs.

A/tera Corporation

I

IData Sheet

EP600-Series EPLDs

In Mode 0, the tri-state output buffer is controlled by a single product
term. If the output of the AND gate is high, then the output buffer is
enabled. If the output is low, the output buffer has a high-impedance
value. In this mode, the macrocell flip-flop is clocked by its synchronous
Clock input signal (CL)(1 or CL)(2). In the erased state, the OE/CLK Select
multiplexer is configured to Mode O.
In Mode 1, the Output Enable buffer is always enabled, allowing the
macrocell flip-flop to be triggered from an asynchronous Clock signal
generated by the OE/CLK product term. This mode allows flip-flops to be
individually clocked from any of the AND-array input signals. With true
and complement signals in the AND array, the flip-flop can be configured
to trigger on a rising or falling edge. This product-term-controlled clock
configuration also allows implementation of gated clock structures.
Figure 5 shows waveforms for the following modes: combinatorial,
synchronous Clock, and asynchronous Clock.
Combinatorial Mode

Figure 5. Switching Waveforms
Numbers in parentheses are for
the EP610A EPLD.

Input or 110

_____________________J~~--------------------

Combinatorial Output

_____________________________~-------Ji~------------------

:.

t

PO

,:

.1

Combinatorial or Registered OutJ)ut

;~I------~':~-----------

High-I/Tlledance Tri-State

Valid Output

f

.1

Asynchronous Clear Output

•

------------------------------~~~------------Synchronous Clock Mode

t.!!...i i.
CLK1,CLK2

tCH

tf...j ~:

.:

--.J

:. tau

ltH

:

Inp~

~1~-~--~~I/O~ma-Y-C-ha-ng~~;:==~.~.4~~.r----I-n~-t-o-rl-~-~--~~-an-~--------

Outp~

_fro_m_m~g~ist_~_to_o_~~~_t_______
· __~tr--------------------

Valid

;. t
Valid

V,...----..'----

\\-_----JI.~------iN

COl.:

Asynchronous Clock Mode
tACH

-

t

ACL

Inp~

~~:'~=4'~~---'x.~---.i

Inp~

:.tA8U,l~
-:-In-p~-~~1I0:::-m-a-Y~ch-an-g-e--.t=t=X'--I~n~-t-o~rI~IO-may--c-:-ha-n-~----------

ValidOutp~

~(F_ro_m_m~~s_~_t_o_M~~_t)~_________~*r------------------------

Asynchronous Clock

Valid

:

t

ACOI

.~~-x==

:

:-.

t R & t F < 3 ns (2 ns)
Inputs are driven at 3 V for a logic high
and 0 V for a logic low. All timing
characteristics are measured at 1.5 V.

IAltera Corporation

Page 55

aY

EP60O-Ser/es EPLDs

Output!
Feedback
Selection

DataShHtl

Output configurations available with EP600-series EPLDs are shown in
Figure 6. Each macrocell can be individually configured with combinatorial
output or with any of the four register outputs. All registers have an
individual asynchronous Clear function controlled by a dedicated product
term. When this product term is a logic high, the macrocell register is
immediately loaded with a logic low. The Clear function is performed
automatically during power-up.
The combinatorial configuration has eight product terms ORed together
to generate the output signal. This configuration has the following
characteristics:

o
o
o

The Invert-Select EPROM bit controls output polarity.
One product term controls the Output Enable buffer.
The Feedback-Select multiplexer allows the user to choose I/O (pin)
feedback or no feedback to the AND array.

The D or T register has eight product terms ORed together that are
available to the register input. This configuration has the following
characteristics:

o
o
o
o

The Invert Select EPROM bit controls output polarity.
One product term controls asynchronous Clear.
The OE/CLK Select multiplexer configures the mode of operation to
Mode 0 or Mode 1.
The Feedback Select multiplexer allows the user to choose registered
feedback, I/O feedback, or no feedback to the AND array.

If the JK or SR register is selected, eight product terms are shared between
two OR gates. The outputs of the OR gates feed the two primary register
inputs. This configuration has the following characteristics:

o
o
o
o
o

The A+PLUS Development System optimizes the allocation of product
terms for each register input.
One product term controls asynchronous Clear.
The Invert Select EPROM bits control output polarity.
The OE/CLK Select multiplexer configures the mode of operation to
Mode 0 or Mode 1.
The Feedback Select multiplexer allows the user to choose registered
feedback or no feedback to the AND array.

Any I/O pin can be configured as a dedicated input by selecting no output
with I/O feedback. In the erased state, the I/O architecture is configured
for combinatorial active-low output with I/O feedback.

I Page56

A/tera Corporation

I

IData ShfHIt

EP60O-Series EPLDs
Combinatorial

Figure6.VO
Con"guratlons

va Selection
AND
Array

OutputIPoiarity
Combinatorial/High
Combinatorial/Low
None

Feedback
Pin, None
Pin, None
Pin

Feedback
SeIad

D Flip-Flop

va Selection
AND
Array

Output/Polwlty
D Register/High
D Register/Low
None
None

Fundion Table
Feedback

D

On

0"'1

D Register, Pin, None
D Register, Pin, None
D Register
Pin

L
L
H
H

L
H
L
H

L
L
H
H

TFlip-Flop

va Selection
AND
Array

Output/Polarity
T Register/High
T Register/Low
None
None

Fundion Table
Feedback

T

On

0"'1

T Register, Pin, None
T Register, Pin, None
T-Register
Pin

L
L
H
H

L
H
L
H

L
H
H
L

JK Flip-Flop

va Selection
Output/Polarity
AND
Array

JK Register/High
JK Register/Low
None

Function Table
Feedback
JK Register, None
JK Register, None
JK Register

J

K

On

0"'1

L

L
L
H
H
L
L
H
H

L
H
L
H

L
H
L
H

L
H
L
L
H
H
H
L

L
L
L
H
H
H
H

SR Flip-Flop

va Selection
AND
Array

40

Inputs

IAltera Corporation

Output/Polarity
SR Register/High
SR RegisterlLow
None

Function Table
Feedback
SR Register, None
SR Register, None
SR Register

S

R

On

0"'1

L
L
L
L
H
H

L
L
H
H
L
L

L
H
L
H
L
H

L
H
L
L
H
H

Page 57

EP600-8eries EPLDs

Functional
Testing

Data Sheet\

EP600-series EPLDs are fully functionally tested and guaranteed through
complete testing of each programmable EPROM bit and all internal logic
elements. A 100% programming yield is ensured. This testing process
eliminates problems associated with fuse-programmed circuits by allowing
test programming patterns to be used and then erased. The ability to use
application-independent, general-purpose tests, called generic testing, is
unique to EPLDs. AC test measurements are performed under the
conditions shown in Figure 7.
Figure 7. AC Test Conditions
Power supply transients can affect AC
measurements. Simultaneous transitions of
multiple outputs should be avoided for
accurate measurement. Threshold tests must
not be performed under AC conditions.
Large-amplitude, fast-ground current
transients normally occur as the device
outputs discharge the load capacitances.
When these transients flow through the
parasitic inductance between the device
ground pin and the test system ground, it can
create significant reductions in observable
input noise immunity.
Note: Numbers in parentheses are for the
EP610A EPLD.

----vee

Device input
rise and fall
times < 3 ns (2 ns)

Design
Security

EP600-series EPLDs contain a programmable design Security Bit that
controls access to the data programmed into the device. If this feature is
used, a proprietary design implemented in the EPLD cannot be copied or
retrieved. This feature provides a high level of design security by making
programmed data within EPROM cells invisible. The Security Bit, as well
as all other program data, is reset by erasing the EPLD.

Turbo Bit

The EP610 and EP630 EPLDs contain a programmable Turbo Bit, set with
the A+PLUS software, to control the automatic power-down feature that
enables the low standby-power mode. When the Turbo Bit is programmed
(Turbo = On), the low standby-power mode (lCCl) is disabled, making the
circuit less sensitive to Vcc noise transients created by the low-power mode
power-up / power-down cycle. The typical Icc vs. frequency data for both
turbo and non-turbo mode is shown in each EPLD data sheet. All AC
values are tested with the Turbo Bit programmed.
If the design requires low power operation, the Turbo Bit should be
disabled (Turbo = Off). In this mode, some AC parameters may increase.

To determine worst-case timing, values from the AC Non-Turbo Adder
specifications must be added to the corresponding AC parameter.
Page 58

Altera Corporation

I

EP610AI
o

Features

High-performance 16-macrocell EPLD
Combinatorial speeds with tpD = 12 ns
Counter frequencies up to 83.3 MHz
Pipelined data rates up to 83.3 MHz
A vailable in windowed ceramic and plastic one-time-programmable
chip carrier packages
24-pin DIP (ceramic and plastic)
28-pinJ-Iead (ceramic and plastic)
24-pin, 3OO-mil SOIC (plastic)
Macrocells can be individually programmed as D, T, JK, or SR flipflops, or for combinatorial operation.
Programmable Clock option allows independent clocking of all
registers.

o

o

o

Figure 8 shows the pin-outs for the EP610A EPLD.

Figure 8. EP610A Pin-Out Diagrams
Package outlines not drawn to scale.

ClK1
4

3

1

2

28

27

26

110

25

1/0

110

24

110

0

1/0

110
110
I/O

10

NC

11

23

110

22

110

21

1/0

NC
12

g

13

~
a.

~

14
0

z

(!)

15
0

z
(!)

16

~
-l

U

J-Lead

Altera Corporation

17

~
a.

18

g

INPUT
I/O

I/O

EP610A

VCC

INPUT

110
I/O

vee

ClK,

I/O

I/O

I/O

1.0
LO
1.0

1.0

110

110

1.0

1.0

110

1.0
1.0
1.0

I/O

110
INPUT

INPUT

GND

ClK2

INPUT

INPUT
1.0
1.0
LO
1.0
1.0
1.0

1.0

INPUT _ _ _ _ _ _ _....... ClK2
INPUT

GND

~

DIP

sOle

Page

591

IEP610A

Preliminary Data

Absolute Maximum Ratings
Symbol

Conditions

Min

Max

Unit

Supply voltage

With respect to GND

-2.0

7.0

V

Vpp

Programming supply voltage

See Note (1)

-2.0

13.5

V

VI

DC input voltage

-2.0

7.0

V

I MAX

DC V cc or GND current

-175

+175

mA

DC out~ut current,

-25

lOUT

Ip0

~er ~in

I Power dissipation

~
~

+25

mA

1000

mW

Storage temperature

No bias

-65

+150

Ambient temperature

Under bias

-65

+135

Min

Max

Recommended Operating Conditions

~I

Conditions

Parameter

~I Supply voltage
I
I Input voltage

I

~I
I
E I

I Output voltage

V0

TA

I

I For commercial use

Operating temperature

IT A

I For industrial use

Operating temperature

I For military use

T e l Case temperature

tF

4.75

5.25

V

0

Vee

V

0

Vee

V

0

+70

DC

-40

+85

DC

-55

+125

DC

I

~~----------

DC Operating Conditions

vcc = 5 V ± 5%, TA = OD C to 70° C for commercial use

See Note (2)

Vee
Vee

I Symbol I
VIH

I V Il

F
OH

V OL
II

Iloz

'II

CCl

Unit

1_I--'np'-u_t_ris_e_ti_m_e_ _ _ _ _ _ _. _ _ _ _ _ _ _ _ _ _ _ _ _. _ _25
__ __
ns__
i
I
r
Input fall time
ns
25

R

= 5 V ± 10%, TA = -40° C to 85° C for industrial use
= 5 V ± 10%, Tc =-55° C to 125° C for military use

Parameter

Conditions

High-level input VOltage

I Low-level input voltage

I High-level TTL output voltage
I Low-level output voltage

I Input leakage current

I
IloH

=-4 mA DC

~

Max

Unit

2.0

V cc +0.3

V

-0.3

0.8

V
V

2.4

II OL = 8 mA DC

I V I = V cc or GND

I Tri-state out~ut off-state current I V = Vee or GND
I V cc supply current (standby) I V I = Vee or GND
0

0.5

V

-10

+10

-40

+40

J!A
J!A

90

130

mA

90

130

mA

No load
II

CC31I Vee supply current

I' V I =V ee or GND, No load

~,_ _ _ _ _ _ _ _ _ _. f= 1.0 MHz,See Note (3)

I Psge60

I

Note: See Operating Requirements for EPLDs in this data book.

Parameter

vee

Data Sheet

A/tera Corporation

I

I Data Sheet

EP610A

Preliminary Data

I

Capacitance See Note (4)

I
1

I

Symbol

c IN

1

Parameter
Input capacitance

I-C---'O':"":"'U-T- - I Output capacitance

I

1

v IN = 0 V,

1

VOUT=OV, f=1.0MHz

v

cc
Vcc
Vcc

Unit

8

pF

8

pF

16

pF

use

= 5 V ± 10%, TA = -40° C to 85° C for industrial use
= 5 V ± 10%, Tc = -55° C to 125° C for military use
EP610A-10

I

EP610A-12

1

EP610A-15

I

I

I Conditions I Min I Max I Min I Max I Min I Max I Unit I

Parameter

I
11-_II'~10o11'--11:~12211-_11~155I:
I C 1 = 35 pF

I t PZX

Input to non-registered output
I/O input to non-registered output
Input to output enable

1 t PXZ

Input to output disable, See Note (5)I-C-1-=-5-P-F-1

I t CLR

Max

f = 1.0 MHz

= 5 V ± 5%, TA = 0° C to 70° C for commercial

1_ _ _ _ _ _ _ _ _ _ _ _ _ ,_ _ _ _1

I Symbol
I t PD1
I t PD2

Min

I V IN = 0 v, f = 1.0 MHz

I_C--'C=LK'-'--_ _ Clock pin capacitance

AC Operating Conditions

Conditions

I

Asynchronous output clear time

nnss

I:

fJ

1--'-1-0-1--1-1-2-1--1-1-5-I~I

1

Ic

1 = 35 pF

1 10

I

I

10

1

1 12

I

I

12

1

1 15

I

I

15

1 ns

I

ns

I

I

Synchronous Clock Mode

,-----------------I Symbol I
Parameter
I f MAX I Maximum frequency
I t su I Input setup time
I t H
I Input hold time
I t CH

I Clock high time

It
It

I Clock low time
I Clock to output delay

CL
C01

I t CHT
I f CNT

EP61~A-10 I

I Conditions

Min

See Note (6)

100
8

o
5

5

I Minimum clock period
1_ln_te_rn_a_1m_a_X_im_Um_fre--lq_Ue_nc-<.y_ _ 1 See Note (3)

100

EP610A-12

I Max I Min I Max
I I 83.3 I
I
I 8 I
I I o I
I I 6 I
I, 6 I, 6 I, 6
I 10 I I 12
I I 83.3 I

I EP610A-15 I I
I Min I Max I Unit I
I 83.3 I
I 10
I 0

I
I,
I

6
6

I 83.3

I MHz I

I
I
,

8

I

12

I

I~:
I~:

,

ns

I

I

ns

I

I
,

I MHz I

Asynchronous Clock Mode
EP610A-10

Symbol
f MAX

I

Parameter

, Conditions

'-M-a-xi-m-um-f-re-qu-e-nc-y----I See Note (6)

t ASU

1.....;.ln:..:.r:p=ut:....::s=et=up:....:ti=m~e_ _ _ _ _ I_ _ __

tACH

. Clock high time

I =:..:....:...;.:.:..=.....:;,;..:..:..=..------1·---Input hold time
I
t AH
----::=---.!,I____
I
_ _ _I·----

_t....!A=C=L_+I.....:c.....;.IOc...:..;Ck..:....;,lo..:....;,w..:....;,t:..;.;im.;.::,e_ _ _ _ _ _
t AC01

I Clock to output delay

t ACNT

. Minimum clock period

----::~"---.!I-~=-=-=c:...::..:....;='---

_f--:A=c=NT.!..-_I!.. . .;.ln;,;,; ,te; .;. rn;.;,; a; ;,. ;1m..:.;,;a=x.:.;,;.im=u;.;,;,m...:.:..fr=eq=ue;;.;..n=cYL-_1 See Note (3)

I Altera Corporation

I

EP61~A-12

Min' Max , Min
100

5
5
5
5

100

I
I
I
I
I

I 83.3
I 6
I 6
I 6
I 6

I Max
I

I
I
I
I
I

13

I EP61 OA-15 I I
I Min ,MaX IUnit I

I 71.4 I
I MHz I
I 6 I I ns I
I 6 I I ns I
I
I
I 115 I : I

~

I :: I I I I I ;~z I
83.3

12

71.4

14

Page 61

I

IEP610A

Preliminary Data

Data Sheet

I

Notes to tables:
(1)

(2)

(3)
(4)

(5)
(6)

The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
Typical values are for TA =25° C and Vcc =5 V.
Measured with a device programmed as a 16-bit counter.
Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for
dedicated clock inputs only. Pin 13 (high-voltage pin during programming) has a
maximum capacitance of 50 pF.
Sample-tested only for an output change of 500 mY.
The f MAX values represent the highest frequency for pipelined data.

Product Availability

I

I Commercial

I

Availability

Grade
Industrial

I Military

0

EP610A-12, EP610A-15

0

(0 C to 70 C)
(-40 0 C to 85 0 C)

Consult factory

(-55 0 C to 1250 C)

Consult factory

Note: Only military-temperature-range EPLDs are listed above. MIL-5TD-883-compliant
product specifications are provided in Military Product Drawings (MPDs), available from
Altera's Marketing Department by calling 1 (800) 5OS-EPLD. These MPDs should be used
to prepare Source Control Drawings (SCDs). See Military Products in this data book.

Figure 8 shows output drive characteristics for EP610A I/O pins and
typical supply current versus frequency for the EP610A.
Figure 9. EP640 Output Drive Characteristics and Icc vs. Frequency
150

100

101..

ci

>.

r-

<-

80

~

60

.§.
C

ci

~

:;

()

SCl.
S

Vcc =5.0V
Room Temp.

Vee =5.0V
Room Temp.

Q)

>

'+:1

40

0

«

0

0

100

ti
~

0

50

-2
20

100 MHz

Vo Output Voltage (V)

IPage 62

Maximum Frequency

Altera Corporation

I

EP6301
o

Features

o
o

o
o

High-performance 16-macrocell EPLD
Combinatorial speeds with tpD = 15 ns
Counter frequencies up to 83 MHz
Pipelined data rates up to 83 MHz
Very low power
Icc = 5 rnA (typical) for a 16-bit counter at 1 MHz
Icc = 20 tJA (typical) in standby mode
Available in windowed ceramic and plastic one-time-programmable
chip carrier packages
24-pin DIP (ceramic and plastic)
28-pin J-Iead (ceramic and plastic)
24-pin, 3OO-mil SOIC (plastic)
Macrocells can be individually programmed as D, T, JK, or SR flipflops, or for combinatorial operation.
Programmable Clock option allows independent clocking at all
registers.

Figure 10 shows pin-outs for the EP630 EPLD.

Figure 10. EP630 Pin-Out Diagrams
Package outlines not drawn to scale.

g

~
Q.

;:

~

u

u
U
>

...J

3

u
U
>
1

2

28

~

g

vee
27

26

INPUT

1/0

25

110

1/0

24

110

0

110
1/0
1/0
1/0

10

NC

11

21

110
110

110

110

110

110
110

1/0

110
1/0

EP630

110
NC

12

g

13

~

Q.

~

14

15

16

Altera Corporation

17

0

~

(!)

(!)

5 g

U

~

z

Z

...J

110

18

0

J-Lead

1

~
Q.

INPUT

CLK2

vee

ClK,

INPUT

INPUT

1.0
1.0
1.0
1.0
LO
1.0
LO
1.0

1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0

INPUT

INPUT

ClK2

GNO

Q.

DIP

sOle

Page 631

m

I EP630

Oats Sheet

Absolute Maximum Ratings

Symbol

I

Note: See Operating Requirements for EPLDs in this data book.

Parameter

vee

Suepl~

Vpp

Pr~ramming sueel~ vOltage

Conditions

vOltage

Min

Max

Unit

With respect to GND

-2.0

7.0

V

See Note (1)

-2.0

14.0

V

VI

DC input vOltage

-2.0

7.0

V

I MAX

DC Vee or GND current

-175

+175

mA

lOUT

DC OU!eut current, eer ein

-25

+25

mA

I

I p o l Power dissipation

I

I

1000

I

I

I

mW

li-T-S~T-G------li'-S-to-m-g-e-~-m~~--m-ru-~-----------i--N-O-bi-u------------i~I~I---o-c--~

I T AMB

. Ambient

tem~rarure

~~

Under bias

°C

Recommended Operating Conditions

Symbol

I

I Suppl~ vOltage
I Input voltage

I vee

I VI

I

I

Vo
TA

I Te

It R

I VOL
III
Iloz

IICCI

11CC3

I Page 64

4.75

5.25

V

I

0

I

Vee
Vee

I

0

+70

V

I

I

V

I

°C

+85

°C

I Case

I For military use

-55

+125

°C

See Note (2)

40

ns

I See Note (2l

40

ns

tem~rature

Vcc
Vcc
Vcc

I

High-level

in~ut

vOltage

Conditions

Min

I
I

I I OH =-4 mA DC

Typ

Max

2.0

Vee +0.3

-0.3

0.8

I
I

V
V

2.4

V

3.84

V
0.45

I Input leakage current

I

= Vee or GND

-10

+10

I

Vo= Vee orGND

-10

+10

I

High-level TTL outeut voltage

I Low-level output voltage

I Tri-state output off-state current

I

I I OL =4 mA DC
VI

VCC supply rurren! (non-turbo I VI·Vcc orGND

I VCC

supply ruffen!

(non-turbo mode)

V CC supply ruffen!

. (turbo mode)

I
I
I

I Unit

I High-level CMOS output voltage II OH =-2 mA DC

I

I
I

= 5 V ± 5%, T A = 0° C to 70° C for commercial use
= 5 V ± 10%, TA = -40° C to 85° C for industrial use
= 5 V ± 10%, Tc = -55° C to 125° C for military use

I Low-level input voltage

. standby)

IICC.

For commercial use

Parameter

I

Unit

-40

Symbol

I VOH

Max

I For industrial use

See Note (3)

I V OH

Min

I O~rating tem~rature

DC Operating Conditions

I VIL

I
I
I

Output VOltage

I Input rise time
I Input fall time

ItF

Conditions

0

. O~ratinQ tem~rature

ITA

VIH

I
I

Parameter

I

. I0

20

IVI =VCCorGND, No

JJA

150

=0, See Note (4)

V

J1A
J1A

I
load,

S

10

45

90

f = 1.0 MHz, See Note (5)

I

VI=Vcc orGND , No load,

. f = 1.0 MHz, See Note (5)

mA

I

I

mA

A/tera Corporation

I

Data Sheet

EP6301

capacitance See Note (6)

I

IC
IC

I

Symbol

I

IN

I Input capacitance
I Output capacitance

OUT

I

CCLK

Conditions

Parameter

I VIN =0 V,

I

VOUT=O V, f= 1.0 MHz

I t POl
It

Parameter

Conditions

, Input to non-registered output

EP630-15

I

C 1 = 35 pF

,

"
l_t.....,::c=LR=-=--_!'.. .;"A=sYr. .;. .;n=ch~ro:. ;. :n=ou=s. .:. ou=tp!:. .:u:. :. .tc:..:..:le=a~rt:..:...im...:..e_!_C_1:......=_3_5...:...P_F_ _

1 15

______

2

1t

10

I 110 input pad and buffer delay

I

Min

I

15

\

1 17
'\ 15
1 15

t PZX
1 t PXZ

EP630-20

I Max

Min

11/0 input to non-reg. output
I'
\ Input to output enable
1-ln-.!.p-ut-to-o-u..!..tP-ut-di-sa-b-le---'-C-1-=-5-pF-,-No-te-(-8)-1

PD2

Unit

10

pF

12

pF

20

pF

Vee = 5 V ± 5%, T A = 0° C to 70° C for commercial use
Vee = 5 V ± 10%, TA = -40° C to 85° C for industrial use
Vee = 5 V ± 10%, Tc = -55° C to 125° C for military use

;-I:_-_-_-_-~~=========~~~~~~~~~~-------~-----------=I

I Symbol I

I~x

I
I
I

= 1.0 MHz

f

, V IN =0 V, f = 1.0 MHz

Clock ein capacitance

AC Operating Conditions

Min

1 1

I Max
I

1
\'

I
I

Non-Turbo Adder

See Note (7)

20'

20

I~
I~
\

ns

\

I~

I

1 22 1
,'20"
20 1

I

20
20
20

"ns'
1 ns

I
I

I
I

20

1

20
2

1

1

I

I

ns

I~

0

Synchronous Clock Mode
1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _1

I Symbol I
f

t
t
t
t
t
t
f

MAX

su
H

Parameter

I Maximum frequency
setup time
I1 Input
Input hold time

EP630-15

I See Note (9)
,
,

I 83.3 I
"

9
0

6'

CL

I Clock low time

I

,

6'

COl

1 Clock to output delay

1

1

CNT

I Minimum clock period
I
I Internal maximum frequency I See Note (5)

I 62.5 I

,'

,-----,

CNT

EP630-20

1 Non-Turbo Adder 1

I Conditions IMin IMax IMin IMax I

I Clock high time

CH

1

I

I I
I 83.3 ,

12

I Unit

I

0

I MHz

,'

11
0 ,'

"

20
0

,'nns

I

8'

,

0

'ns

,

0

I

11

See Note (7)

I

8'

I

I I
I 62.5 I

13
16

I

I
,

0
0
0

s

'ns
I ns

I ns
I MHz

Asynchronous Clock Mode

- - - - - - - - - - - - - - - - - -"
1

Symbol

"

If
It
I t AH

Parameter

MAX

Maximum frequency

ASU

Input setup time

I tACH

I t ACL
I t ACOl

I t ACNT
I f ACNT

Conditions

See Note (9)

I

Clock high time

I
I

Clock low time
Clock to output delay

I

Minimum clock period

I A/tera Corporation

See Note (5)

Min

I

Max

I 71.4 I

I
I

Input hold time

Internal maximum frequency

1

EP630-15

6
6

7
7

1

1

EP630-20

Min

1

I 55.5 I

I

I

8

181

,

191

I

, 71.4 ,

15
14

I
I
I

9

1

I

I

I

I
I

Max

I Non-Turbo Adder 1

I
I
I

I

I

1201

I

155.51

18

I

I

See Note (7) I Unit
0
20

0
0
0
20

0
0

I

I

MHz
ns

I

I~
I~

I ns I
I nsl
I ns I
I~

Page 651

fJ

IEP63D

Data Sheet

I

Notes to tables:
(1)
(2)
(3)
(4)

(5)
(6)

(7)
(8)
(9)

Minimum DC input is -{).3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
For all docks: tR and tF =20 ns.
Typical values are for TA =25° C and Vcc = 5 V.
When in non-turbo mode, an EPLD will automatically enter standby mode if logic
transitions do not occur (approximately 100 ns after the last transition). The nonturbo standby current specification (lca) does not apply to the EP630-15 EPLD.
Measured with a device programmed as a 16-bit counter.
Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for
dedicated clock inputs only. Pin 13 (high-voltage pin during programming) has a
maximum capacitance of 50 pF.
See "Turbo Bit" earlier in this data sheet.
Sample-tested only for an output change of 500 mY.
The fMAX values represent the highest frequency for pipelined data.

Product Availability

I

I Commercial
I Industrial
I Military

Availability

Grade

EP630-15, EP630-20

(0° C to 70° C)
(-40° C to 85° C)

Consult factory

(-55° C to 125° C)

Consult factory

Note: Only military-temperature-range EPLDs are listed above. MIL-STD-883-compliant
product specifications are provided in Military Product Drawings (MPDs), available from
Altera's Marketing Department by calling 1 (800) SOS-EPLD. These MPDs should be used
to prepare Source Control Drawings (SCDs). See Military Products in this data book.

Figure 11 shows output drive characteristics for EP630 I/O pins and
typical supply current versus frequency for the EP630.
Figure 11. EP630 Output Drive Characteristics and Icc vs. Frequency
100mA

50

101..

ci..

>.
I-

.s<"

40

~
:::J

30

c:

~

I- 40mA

Vee
TA

U

S
a.
S
0

r-------------.....,

.s<"

=5.0 V
=25° C

Q)

.i!:

~g

20

10mA

Non- Turbo Mode

...3
150 I1A
2

3

4

5

Vo Output Voltage (V)

I Page 66

10 KHz

10 MHz

30 MHz

sO MHz

90 MHz

Maximum Frequency

Altera Corporation

EP6101
o

Features

High-performance 16-macrocell EPLD
Combinatorial speeds with tpD =25 ns
Counter frequencies up to 40 MHz
Pipelined data rates up to 47 MHz
Very low power
Icc = 3 rnA (typical) for a 16-bit counter at 1 MHz
Icc =20 ~ (typical) in standby mode
Available in windowed ceramic and plastic one-time-programmable
chip carrier packages
24-pin DIP (ceramic and plastic)
28-pinJ-Iead (ceramic and plastic)
24-pin, 3OO-mil SOIC (plastic)
Macrocell flip-flops can be individually programmed as D, T, JK, or
SR, or for combinatorial operation.
Programmable Clock option allows independent clocking at all
registers.

o
o

o
o

Figure 12 shows the pin-outs for the EP610 EPLD.
Figure 12. EP610 Pin-Out Diagrams
Package outlines not drawn to sea/e.

g

5 §

0
0

Q.

~

0
0

>

0

>

5
Q.

~

g
VCC

3

2

1

28

27

26

I/O

25

INPUT

I/O

I/O

110

0

\/0

110
I/O

110

10

NC

11

EP610

12

13

14

g 5 0z
Q.

~

15
0

Z

" "

16

I/O

23

\/0

110

22

I/O

110

21

I/O

110

20

I/O

19

NC

110

110

18

~
...J

5 g

0

~

J-Lead

A/tera Corporation

17

24

LO

110

LO
LO
LO

INPUT

Q.

INPUT

LO
LO
LO

110

CLK2

vee

Q.K1

INPUT

1.0
1.0
1.0
1.0
LO
1.0
1.0
1.0

1.0

INPUT

INPUT
Q.K2

GND

DIP

sOle

Page 67\

II

I EP610

Absolute Maximum Ratings

I

I

Data Sheet

Symbol

Note: See Operating Requirements for EPLDs in this data book.

I

Parameter

I

Conditions

Min

I

Max

Unit

7.0

V

13.5

V

vee

Sl:Ipply voltage

With respect to GND

-2.0

Vpp

Pr~rammin9 su~pl~

See Note (1)

-2.0

VI

DC

vOltage

-2.0

7.0

V

I MAX

DC V CC or GND current

-175

+175

mA

I lOUT

in~ut

DC output current,

I p o l Power dissipation
~I
~

voltage

I

~er ~in

-25

Storage temperature

No bias

-65

Ambient temperature

I. Under bias

-65

mA

+25

I

I

I :::
1000

I

mW

I--:-~--:

Recommended Operating Conditions

I

Parameter

Symbol

I vee

Su~~I~

, VI

Input VOltage

I Vo

Output VOltage

I TA

Operating temperature

For commercial use

O~rating

For industrial use

ITA
I Te
It R
It F

temperature

Case temperature

For military use

Input rise time

See Note (3)

In~ut

See Note (3)

fall time

See Note (4)

I

I

Symbol

Min

See Note (2~

voltage

DC Operating Conditions

I Max I
7S S
5.25 (5.5) I
4. t ) I
Vcc
0
Vee
I
0
I +70 I
-40
I +85 I

Conditions

-55

Parameter

Conditions

V

I

100 (50)

ns

I

I

100 (50)

I

·_V.....:;IL=--_ _ I_L_o_w_-le_v_e_1i....
np_u_tv_o_lta-=-e_ _ _-;·_ _ _ _ _ _ _I:
_V-'O"""'H'--_ _ . High-level TTL output voltage

:-1V_o=H"--_ _ 1 High-level CMOS output voltage

Min

I OH = -4 mA DC
II OH = -2 mA DC

-0.2

I

Input leakage current
I V It = Vee or GND
1_I..!::o:::..z_ _ _ '-T; .,;.r!;. .;i-s~ta.-,;.te. ;,;. ;.:ou:.§!.tP.:. . .u. :. :to:":":ff"':'-s:":":ta:"-'te-cu-rr-e-nt-I V = Vee or GND

°

'_1..:.....1_ _ _

I' Vee supply current (standby)
Vee supply current
(non-turbo mode)

Typ

I

Max

I

Unit

I

vee + 0.3

1

V

1

ns

1

I

II'

V I = VCC or GND'I
No load See Note (5)
VI =V ee or GND
No load, f = 1.0 MHz

I---I~~v

~-IVI

24
3.84

e ____ll._I...,:o=L_=_4_m_A_DC
I_V-,o=L_ _ _ I_L_o_w_-I_ev_e_1o_u..:.,tp_u_tv_o_lta...,:gc...
_ _ _1

I

I

1.~~~~~~~~~~~~~~-.il--2-.0--il-- - - I

1

ICC2

+125

V

v

Vee = 5 V ± 5%, TA = 0° C to 70° C for commercial use
Vee = 5 V ± 10%, TA = -40° C to 85° C for industrial use
Vee = 5 V ± 10%, Te = -55° C to 125° C for military use

I_V-'-I.:..:..H_ _ _ I_H_i.x.gh_-_le_ve_l_in'--pu_t_vo_lt_ag.....e_ _ _ _

· I CC1

I
I

Unit

-_11 0

1

I

I

I
II'

',

1

V

1

0.45

I

V

I

0
++ 11 0

I'

::

II'

1"1""'

0
'1

20

I'

150

I

jJA

3

10 (15)

mA

32

60 (75)

mA

I

See Note (6)

lee3

Vee supply current
(turbo mode)

VI =V ee or GND
No load, f = 1.0 MHz
See Note (6)

I Page 68

A/tera Corporation

I

I Data Sheet

EP6101

Capacitance See Note (7)
Symbol I----p-ar-a-m-et-er----'I---eo-n-d-iti-·o-ns---'--M-in-

I

IC
IC
IC

I Input capacitance

IN

IV
IV

IN

I Output capacitance

OUT

=0 V, f = 1.0 MHz

OUT

I Clock pin capacitance

elK

, t P02

11/0 input to non-reg. output

' t PZX

Iinputto output enable

, t PXZ

I Input to output disable

pF

--2-0--i---'-P-F-

I

Parameter

I Input to non-registered output

20

= 0 V, f = 1.0 MHz

1'---Tim-in-g-Pa-,,-ame-te-,,-s- - - - - - - - - - - 1 EP610-25

, t POl

Unit

VIN = 0 V, f = 1.0 MHz
20
Vee = 5 V ± 5%, T A = 0° C to 70° C for commercial use
Vee = 5 V ± 10%, TA = -40° C to 85° C for industrial use
Vee = 5 V ± 10%, Te = -55° C to 125° C for military use

°AC Operating Conditions

I SYmbol'

Max

pF

I

EP610-30 1 EP61~51:-N~-n~-!~-;bo-1

I

Conditions' Min' Max , Min' Max' Min Max'

1

I I 25 I

Note (8)

'unit

I 30

I

I 35

I

30

1 ns

I

I 27

I

I 32

I

I 37

I

30

I

I 25

I

I 30

I

I 35

I

30

I

I 25

I

I 35

I

30

1 37

1

30

I

I ns
I ns
I ns
I ns
1ns

I
I
I
I
I
I

I Min I Max I Min I Max I Min I Max I-N-ot-e-(8-~

Unit

I
I

1 47.61

MHz

C1 = 35 pF
C1 = 5 pF,Note (9)

I t CLR I Register clear delay
C1 = 35 pF
I t 10 1110 input pad and buffer delay I

I 30

I I 27 I

1 I

2

1 32

I I

2

I

I

I I

I

2

0

Synchronous Clock Mode
°

Timing Parameters

EP61 0-25

I Symbol ----Pa-ra-me-t-er--1

Conditions
Note (10)

1°

f MAX

Max. frequency pipelined data
Input setup time

t H

Input hold time

t CH

Clock high time

t CL

Clock low time

I 10 I

t COl

Clock to output delay

1

1 15

t CNT

Minimum clock period

I

I 25 I

Note (6)

1 Internal maximum frequency

1°

EP610-35

1°

Non-Turbo
Adder

-

t su

f CNT

EP610-30

I 21 I
I0 I
I 10 I
1 40.01

1 41.71

1 37.0 1

I

0

I 24 I I 27 I 1--3-0- I0 I I 0 I I 0
I 11 1 112 1 1--0 - I 11'

I

I 17

1 33.31

1

ns

I

'12'

,

0

ns
ns

1

1--0--

ns

I 20

I 30 I

I 35 I

1 28.6

I

0

1--0 - -

I

ns

,I

I

MHz

I
I

Unit

I

ns

Asynchronous Clock Mode

ITiming Parameters
I Symbol I

Parameter

I-c-o-nd-it-ion-s-I Min I

I-f-M-A-X-I~·-Ma-x.-fr-eq-U-en-cy-p-ipe-lin-ed-d-a-ta-I Note (10)
I t ASU

I Input setup time

1

I_t-=-A.:=H__~I__
In-,-pu_th_o_ld_tim_e_ _ _ _ _ 1
I tACH

1 Clock high time

I EP610-25 I EP610-30 I EP610-35
Max
Max I
I

I

I 47.61

1 Clock to output delay
1
I-t-=-A;;..;;;..CN;;;....;.T-~I--M-ini-m-um-cl-oc-k-pe-r-io-d---I

I f ACNT

1

Internal maximum frequency

I Altera Corporation

1 Note (6)

Adder

Max I-N-ot-e-(8-~-

I Min I

Min

I 41.71

I 37.0 I

I

0

0 18 1 I 8 1 1 8 1 1--3I 12

I

I 10 I

I-t-=-A==CL:..:.....-·I~--CI-OC-k-Iow"--t-im-e-----~I·---I 10

I t ACOl

1 Non-Turbo

I

I 12

I

I 11 I

I I 11
I 27 I

1
1 32
30

1_ _0_ _

ns
ns

I

I

ns

12

I

0

I 12 I 1 - - 0 - I I 37 I 30

I 33.31

I 28.6 I

I

0

I

MHz

1 12 1

I I 25 1 1 1 135 1--0- 1 40.0 1

I

II:

I
I

ns
ns
ns

I

I

MHz

Page 69\

I

2

I EP610

Data Sheet

I

Notes to tables:
(1)

The minimum OC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
(2) Numbers in parentheses are for to military and industrial temperature versions.
(3) For all clocks: tR and tF = 250 ns (100 ns).
(4) Typical values are for TA =25° C and V cc =5 V.
(5) When in non-turbo mode, an EPLD will automatically enter standby mode if logic
transitions do not occur (approximately 100 ns after the last transition). The nonturbo standby current specification (lea) does not apply to the EP610-25 EPLD.
(6) Measured with a device programmed as a 16-bit counter.
(7) Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for
dedicated clock inputs only. Pin 13 (high-voltage pin during programming) has a
maximum capacitance of 50 pF.
(8) See "Turbo Bit" earlier in this data sheet.
(9) Sample-tested only for an output change of 500 mV.
(10) The fMAX values represent the highest frequency for pipelined data.

Product Availability

I

Availability

Grade

I Commercial
I Industrial
I Military

EP610-25, EP61 0-30, EP610-35

(0° C to 70° C)
(-40° C to 85° C)

EP61 0-30, EP61 0-35

(-55° C to 125° C)

EP61 0-35

Note: Only military-temperature-range devices are listed here. MIL-STD-883-compliant
product specifications are provided in Military Product Drawings (MPDs), available from
Altera's Marketing Department by calling 1 (800) SOS-EPLD. These MPDs should be used
to prepare Source Control Drawings (SCDs). See Military Products in this data book.

Figure 13 shows the output drive characteristics for EP610 I/O pins and
typical supply current versus frequency for the EP610.
Figure 13. EP610 Output Drive Characteristics and Icc vs. Frequency
100 rnA , . . . - - - - - - - - - -_ _ _.....,
50

101..

ci.

~

«
.§.
'E

~
::l

Turbo Mode

~

40

~

Vee =5.0V

30

TA

0

S

~

«
.§.

=25° C

10mA

-Vee
TA

= 5.0 V
=25° C

.~

~o

20

1.0rnA

..9

0

..3
100j!A
2

3

4

5

Vo Output VoHage (V)

I Page 70

1 KHz

10 KHz 100 KHz 1 MHz 10 MHz 40 MHz

Maximum Frequency

Altera Corporation

I

EP900·Series EPLDs
High-Performance
24-Macrocell Devices

Data Sheet I

October 1990, ver. 1

o
o
o
o

Features

High-density replacement for TIL and 74HC with up to 900 gates
"Zero power" (consumes only microamps in standby mode)
High speed (EP910 tpD = 30 ns)
Advanced CMOS EPROM technology allowing devices to be erased
and reprogrammed
Asynchronous clocking of all registers or banked register operation
from two synchronous clocks
24 macrocells with configurable I/O architecture, allowing up to 36
inputs and 24 outputs
Individually programmable registers providing D, T, JK, or 5R flipflops with individual asynchronous Clear control
100% generically testable to provide 100% programming yield
Programmable Security Bit for total protection of proprietary designs
A+PLU5 software support featuring schematic capture, Boolean
equation, state machine, truth table, and netlist design entry methods
A vailable in 40-pin, 6OO-mil DIP and 44-pin J-Iead chip carriers
Extensive third-party support

o
o
o
o
o
o

o
o

AHera's EP900-series Erasable Programmable Logic Devices (EPLOs) can
implement up to 900 equivalent gates of 551 and M5I logic. These EPLDs are
available in a windowed ceramic or one-time-programmable (OTP) plastic
40-pin DIP and a 44-pinJ-lead chip carrier. See Figure 1.

General
Description

Figure 1. Package Pin-Out Diagrams

6

5

4

3

2

Package outlines not drawn to scale.

INPUT
INPUT
INPUT
I/O
I/O
I/O
110
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT

1 44 43 42 41 40

He

o

110
110
110
110
110
110

18 19 20 21 22 23 24 2S 26 27 28

~ ~~ ~~ ~~ ~ ~ ~ ~~ ~~ ~~ ~
J-Lead

I Altera Corporation

I

NC = no internal connection

DIP

GND

Page

711

fJ

I EP900-Serles EPLDs

Data Sheet

I

EP900-series EPLDs use sum-of-products logic that consists of a
programmable-AND/fixed-OR structure. These EPLDs accommodate
combinatorial and sequential logic functions with up to 36 inputs and 24
outputs.
Altera's proprietary programmable I/O architecture allows the designer
to program output and feedback paths for combinatorial or registered
operation in active-high and active-low modes.
EP900-series macrocells can be individually programmed for D, T, JK, or
SR flip-flop operation, or configured for combinatorial operation. In
addition, each register can be individually clocked from any of the input or
feedback paths in the AND array. These features make it possible to
simultaneously implement a variety of logic functions. For example, EP900series EPLDs are ideal for integrating several 20- and 24-pin PAL devices.
The CMOS EPROM technology in EP900-series EPLDs can reduce power
consumption to less than 20% of the power required by equivalent bipolar
devices, without losing speed. This reduced power consumption makes
EP9oo-series EPLDs desirable for a wide range of applications. Moreover,
these EPLDs are 100% generically testable and can be erased with UV light.
Designs and design modifications can be implemented quickly, eliminating
the need for post-programming testing.
Logic is implemented with Altera's A+PLUS Development System, which
supports schematic capture, Boolean equation, state machine, truth table,
and netlist design entry methods. After the design is entered, A+PLUS
automatically translates it into logic equations, performs Boolean
minimization, and fits it into the EPLD. The device may then be programmed
in minutes at the designer's desktop to create customized working silicon.
In addition, extensive third-party support exists for design entry, design
processing, and device programming.

IPage 72

Altera Corporation

I

Data Sheet

EP90D-Series EPLDs

Functional
Description

I

EP900-series EPLDs use CMOS EPROM technology to configure
connections in a programmable-AND logic array. EPROM connections are
also used to construct a highly flexible programmable I/O architecture
that provides advanced functions for user-programmable lOgiC.
EP900-series EPLDs have 12 dedicated data inputs, 2 synchronous clock
inputs, and 24 I/O pins that can be individually configured for input,
output, or bidirectional operation. Figure 2 shows the EP900-series
macrocell. Each macrocell contains 10 product terms for the following
functions: 8 product terms are dedicated to logic implementation; 1 product
term is used for asynchronous Clear control of the internal register; and 1
product term implements either Output Enable or an asynchronous Clock.

Figure 2. Logic Array Macrocell
Synchronous
Clock OEICLOCK

t vcc~I

OE

}-+----ll:::

(5 !CLK

2

3

4

5

&

7

a

8

10 11 12 13 14 15 l' 17 18 11 22 23 24 25 26 27 l!8 21 30 31 32 33 34

36 37 38 31

The block diagram of an EP900-series EPLD is shown in Figure 3. The
internal device architecture has a sum-of-products (AND-OR) structure.
Inputs to the programmable AND arra y come from the true and complement
signals of the 12 dedicated data inputs and the 24 I/O feedback Signals.
The 72-inputAND array has 240 product terms that are distributed equally
among the 24 macrocells. Each EP900-series product term represents a
72-input AND gate.
In the erased state, the true and complement of the AND-array inputs are
connected to the product terms. An EPROM control cell is located at each
intersection of an AND-array input and a product term. During the
programming process, selected connections are opened, allowing any

1

A/tera Corporation

Page

731

IEP90D-Serles EPLDs

Data Sheet

Figure 3. EP900-Serles Block Diagram

Numbers in parenth8S8S are for J-/ead packages.
72

1 (2)
2 (3)
3 (4)
4 (5)

39(43)
38(42)

37(41)

Macrocell13

Macrocel/1

Macrocell14

Macrocel/2

Macrocell15

Macrocel/3

Macrocel/16

Macrocell4

36(40)

5 (6)

35(38)

6 (7)

34(37)

7 (8)

33(36)

8 (9)

••
•

••
•
Macrocell21

Macrocell9

Macrocell22

Macrocell10

Macrocell23

Macrocel/11

Macrocell24

Macrocell 12

28(31)

13(14)

27(30)

14(15)

26(29)

15(16)

16(18)

25(28)

17(19) c!.!.!,,!::.::-----i::£:::::::1
18(20) c;.=.:::.::-----i::£:::::::1
C=::!::J-+--~~<:J
19(21) C:>~":'-'----i::C:::J
C:::3::J-+--~~<:J
'----------,,..--------' '-------,,---------'

24(27)
23(26)
22(25)
21 (24)

IPage 74

72

Altera Corporation

Data Sheet

EPSOO-Series EPLDs

I

product term to be connected to the true or complement of an array input
signal with the following results:

o

If both the true and complement of an array input signal are connected,

o

If both the true and complement of any array input signal are

o

If a1172 inputs for a given product term are programmed "open," the

the output of the AND gate is a logical low.
programmed "open," a logical "don't care" results for that input.
output of the corresponding AND gate is a logical high.

Two dedicated clock inputs (which are not available in the AND array)
provide the signals used for synchronous clocking of EP900-series internal
registers. Each signal is positive-edge-triggered and has control over 12
registers. CLJCl controls macrocells 13 to 24; CLlCZ controls macrocells 1 to
12. The programmable I/O architecture allows each of the 24 internal
registers to have a synchronous or asynchronous Clock mode.
EP900-series architecture provides each macrocell with over 50
programmable I/O configurations. Each macrocell can be configured for
combinatorial or registered output, with programmable output polarity.
Four register types (0, T, ]K, and SR) may be implemented in each macrocell
without requiring additional logic. I/O feedback selection can be
programmed for registered or input feedback. The I/O architecture can
also individually clock each internal register from any internal signal.

1/0

Architecture

Figure 4 shows the two modes of operation provided by the OE/CLKSelect multiplexer. This multiplexer, controlled by a single EPROM control
bit, may be individually configured at each I/O pin.

OE/CLK
Selection

Figure 4. OE/eLK Select Multiplexer
Mode 0:
OE .. Product Term Controlled
ClK = Synchronous

Mode 1:

OE .. Enabled
ClK .. Asynchronous

Synchronous
Clock

Synchronous
Clock

vee

vee

AND
Array

AND

Macrocel

110 Regis1er

The register is clocked by the synchronous clock signal, which is
common to seven other macrocells. The output is enabled by the logic
from the product term.

I A/tera Corporation

OE

Array

Maaocel

Macrocel
~
Buller

110 Regis1er

The oulput is permanently enabled and the register is clocked
by the product tenn, which a60ws gated clocks to be generated
in EP900-series EPLDs.

Page

751

IEP900-Series EPLDs

Dsts Sheet

I

In Mode 0, the tri-state output buffer is controlled by a single product term.
If the output of the AND gate is high, the output buffer is enabled. If the
output is low, the output buffer has a high-impedance value. In this mode,
the macrocell flip-flop is clocked by its synchronous Clock input signal
(CLXl or CLXZ). In the erased state, the OE/CLK Select multiplexer is
configured to Mode O.
In Mode 1, the Output Enable buffer is always enabled, so the macrocell
flip-flop can be triggered from an asynchronous Clock signal generated by
the OE/CLK product term. This mode allows flip-flops to be individually
clocked from any of the 72 AND-array input signals. With both true and
complement signals in the AND array, the flip-flop can be configured to
trigger on a rising or falling edge. This product-term-controlled clock
configuration also allows implementation of gated clock structures.
Figure 5 shows waveforms for the following modes: combinatorial,
synchronous Clock, and asynchronous Clock.
Combinatorial Mode

Figure 5. Switching Waveforms

~.'

Input or 1/0

Combinatorial Output

:.
Combinatorial or Registered Output

!

i·

High-Impedance Tri-State
Valid Output

:.

tpD

tpxz

tPZl(

(i-----..

tClR

Asynchronously Cleared Output

Synchronous Clock Mode
t

CH

t £..;:.

I:

~,--_--,I·-----iN

CLK1. CLK2

t au
Valid Input

Valid Output

Input or 1/0 may

t

CL

I:

v~-----.,----

~.t H.:

Changei.'-_---;·~i.r---:I:-npu-t-o-r1~/O~ma-y"":'ch-an-ge----

i~
_fr_~_r~~~ia_te_rt_o_oo~tpu_t_ _ _ _·_~ir------------Asynchronous Clock Mode

Asynchronous Clock Input

Valid Input

Input or 1/0 may change

Input or 1/0 may change
:

tAC01

:

=---:

Valid Output

from

r~ister to

ootput

x

r -----------------

t R &t F <3ns
Inputs are driven at 3 V for a logic high
and 0 V for a logic low. All timing
characteristics are measured at 1.5 V.

Ipage 76

Altera Corporation

I DataShHt
Output!
Feedback
Selection

EP9OO-Serles EPLD.I

Output configurations available with EP900-series EPLDs are shown in
Figure 6. Each macrocell can be individually configured with combinatorial
output or any of the four register outputs. All registers have an individual
asynchronous Clear function controlled by a dedicated product term.
When this product tenn is a logic high, the macrocell register is immediately
loaded with a logic low. The Clear function is performed automatically
during power-up.
The combinatorial configuration has eight product terms ORed together to
generate the output signal. This configuration has the following
characteristics:

o
o
o

The Invert Select EPROM bit controls output polarity.
One product term controls the Output Enable buffer.
The Feedback Select multiplexer allows the user to choose I/O (pin)
feedback or no feedback to the AND array.

The D or T register configuration has eight product terms ORed together
that are available to the register input. This configuration has the follOwing
characteris tics:

o
o

o

o

The Invert Select EPROM bit controls output polarity.
One product term controls asynchronous Clear.
The OE/CLK Select multiplexer configures the mode of operation to
Mode 0 or Mode 1.
The Feedback Select multiplexer allows the user to choose registered
feedback, I/O feedback, or no feedback to the AND array.

If the JK or SR register is selected, eight product terms are shared between
two OR gates. The outputs of the OR gates feed two primary register
inputs. This configuration has the following characteristics:

o
o
o
o
o

The A +PLUS Development System optimizes the allocation of product
terms for each register input.
One product term controls asynchronous Clear.
The Invert Select EPROM bits control output polarity.
The OE/CLK Select multiplexer configures the operation mode to
Mode 0 or Mode 1.
The Feedback Select multiplexer allows the user to choose registered
feedback or no feedback to the AND array.

Any I/O pin can be configured as a dedicated input by selecting no output
with I/O feedback. In the erased state, the I/O architecture is configured
for combinatorial active-low output with I/O feedback.

I Altera Corporation

Page

771

EP900-Series EPLDs

DatBShHt

Figure 6. VO Configurations
Combinatorial
/10 Selection
AND
Atray

OutputIPoiarity

CorrbinatoriallHigh
CorrbinatoriallLow
None

Feedback

Pin, None
Pin, None
Pin

D Flip-Flop
/10 Selection
AND
Array

Function Table
Feedback

D

an

a ....,

o Register, Pin, None
o Register, Pin, None
o Register

L
L
H
H

L
H
L
H

L
L
H
H

Output/Polarity

o Register/High
o Registerllow

None
None

Pin

TFlip-Flop
VO Selection

Output/Polarity

T Register/High
T Register/Low
None
None

Function Table
Feedback

T

an

a ....,

T Register, Pin, None
T Register, Pin, None
T-Register
Pin

L
L
H
H

L
H
L
H

L
H
H
L

JK Flip-Flop
VO Selection
AND
Array

Output/Polarity

JK RegisterlHigh
JK RegisterlLow
None

Function Table
Feedback

JK Register, None
JK Register, None
JK Register

J

K

an

a ...,

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

L
H
L
L
H
H
H
L

SR Flip-Flop
VO Selection
AND
Atray

OUipUtlPoiarity

SR RegisterlHigh
SR RegisterlLow
None

I Page 78

Function Table
Feedback

SR Register, None
SR Register, None
SR Register

S

R

an

a ...,

L
L
L
L
H
H

L
L
H
H
L
L

L
H
L
H
L
H

L
H
L
L
H
H

Altera Corporation

I

Data Sheet

Functional
Testing

EP900-Serles EPLDs

I

EP900-series EPLDs are fully functionally tested and guaranteed through
complete testing of each programmable EPROM bit and all internal logic
elements. A 100% programming yield is ensured. This testing process
eliminates traditional problems associated with fuse-programmed circuits
by allowing test programming patterns to be used and then erased. This
ability to use application-independent, general-purpose tests, called generic
testing is unique to EPLDs. AC test measurements are performed under
the conditions shown in Figure 7.

Rgure 7. AC Test Conditions

----vee
Power supply transients can affect AC
measurements. Simultaneous transitions of
multiple outputs should be avoided for
accurate measurement. Threshold tests must
not be performed under AC conditions.
Large-amplitude, fast-ground current
transients normally occur as the device
outputs discharge the load capacitances.
When these transients flow through the
parasitic inductance between the device
ground pin and the test system ground, it can
create significant reductions in observable
input noise immunity.

Design
Security

1 Altera Corporation

Device input
rise and fall
times < 3 ns

EP900-series EPLDs contain a programmable Security Bit that controls
access to the data programmed into the device. If this feature is used, a
proprietary design implemented in the device cannot be copied or retrieved.
This feature provides a high level of design securi ty by making programmed
data within EPROM cells invisible. The Security Bit, as well as other
program data, is reset by erasing the EPLD.

Page

791

I EP9OO-Serles EPLDs
Turbo Bit

DatBShHt

I

EP900-series EPLDs contain a programmable Turbo Bit, set with A +PLUS
software, to control the automatic power-down feature that enables the
low standby-power mode (lea). When the Turbo Bit is programmed
(Turbo = On), the low standby-power mode is disabled, making the circuit
less sensitive to Vee noise transients created by the low-power mode
power-up/power-down cycle. Typical Icc vs. frequency data for turbo
and non-turbo mode is shown in each EPLD data sheet. All AC values are
tested with the Turbo Bit programmed.
If the design requires low-power operation, the Turbo Bit should be
disabled (Turbo = Off). In this mode, some AC parameters may increase.
To determine worst-case timing, values from the AC Non-Turbo Adder
specifications must be added to the corresponding AC parameter.

IPage 80

Altera Corporation

I

EP9101
o

Features

High-performance 24-macrocell EPLD
Combinatorial speeds with tpD =30 ns
Counter frequencies up to 33 MHz
Pipelined data rates up to 41 MHz
Very low power
Icc = 6 rnA (typical) for a 24-bit counter at 1 MHz
Icc =20 JlA (typical) in standby mode
A vailable in windowed ceramic and plastic one-time-programmable
chip carrier packages
40-pinDIP
44-pinJ-Iead
Macrocell flip-flops can be individually programmed as D, T, JK, or
SR flip-flops, or for combinatorial operation.
Programmable Clock option allows independent clocking of all
registers.

o

o
o

o

Figure 8 shows the pin-outs for the EP910 EPLD.

Figure 8. EP910 Pin-Out Diagrams
Package outlines not drawn to sea/e.

vee
6

110

5

4

3

2

INPUT
INPUT
INPUT

1 44 43 42 011 olD

0

EP910

31

110
110
110

18 19 2D 21 22 23 201 25 26 27 28
g~~~i~!l1~~~g

~ ~ ~

c c

~ ~ ~ ~

110
110
110
110
110
110
110
110
110
110
I/O
I/O

110
110
I/O
110
110
I/O
110
INPUT
INPUT
INPUT
GNO

INPUT
INPUT
INPUT

NC =no internal connection

J-Lead

Altera Corporation

DIP

Page

811

fJ

IEP91D
Absolute Maximum Ratings

Note: See Operating Requirements for EPLDs in this data book.

vee

Supply voltage

With respect to GND

-2.0

Vpp

Programming supply voltage

See Note (1)

-2.0

~
I

VI

DC ineut VOltage

-2.0

I

I MAX

DC Vee or GND current

-250

lOUT

DC output current, per pin

-25

Conditions

Parameter

Symbol

Min

I p o l Power dissipation
rl_T...;:s...:..;TG=--_ _ 1 Storage temperature

_T.:;:AM~B===--_ _ I

Ambient temf)erature

1-1

7.0

7.0

V

I

1200

I No bias

I Under bias

-65

+150

-65

+135

I

V

mA

+250
+25

V

~

13.5

I

Unit

mA

mW

I
I

'C

I

Recommended Operating Conditions

I

Unit
I
I:-S-U-e-P-Iy-V-Ol-ffi-g-e-------!--S-ee-N-o-~-~-1------~4.~75~(4~.5~)_!-~~~4--~--

Symbol
vee

Conditions

Parameter

Min

Max

5.25 (5.5) I

V

~V~I----I!~ln~pu~t~v~ol~ffi~ge~-------!--__----------~o~--!-~~ I!.-~-­
I V
~V...;:o~---I!-O-ut~pu-t-v-O-lffi~g~e-------!-------------~o~__!-~~-!---~-Vee __
Vee

I

I Operating temf)erature

TT AA

---=-:~---I

1-.

1 T e l Case temperature

-=R----I Input rise time

1;---t

See Note (4)

I

Symbol

+70

-40

+85

For military use

-55

l~s: . : e:. .: e. .:. .N.:. :.o. :.:te. .!.(=.!.3)_ _ _ _ _ _______

1!_t~F____ I--ln'--pu-t-fa-lI-ti-m-e--------1

DC Operating Conditions

0

For industrial use

For commercial use

Of)erating temf)erature

VOH

1

VOL

loz
II CCt

Conditions

Min

°C

100 (50)
ns
--.!...-!..-!.---100 (50)
ns

Vee +0.3

V

0.8

V

I High-level TTL output voltage

2.4

IOH =-2 mA DC

3.84

Input leakage current

V I = Vee or GND
V 0 = Vee or GND

I Vcc supply current (standby)

V
V

I Ol =4 mADC

Tri-state output off-state current

VI

= Vee or GND

Vee supply current

VI =V ee orGND

(non-turbo mode)

No load, f = 1.0 MHz

Unit

2.0

1 High-level CMOS output voltage

I Low-level output voltage

-----,-------Max
Typ

-0.3
IOH =-4 mA DC

No load, See Note (5l
lee2

°C

Vee = 5 V ± 5%, TA = 0° C to 70° C for commercial use
Vee = 5 V ± 10%, TA = -40° C to 85° C for industrial use
Vee = 5 V ± 10%, Te = -55° C to 125° C for military use

I
Parameter
I High-level input voltage

~

°C

I

See Note (3)

I Low-level input voltage
1

+125

I
I
I
I

V

045

I~
-10

U

20

6

V

~~
~
20

mA

80 (100)

mA

See Note (6)

I

IPage 82

Vee supply current

VI =Vee or GND

(turbo mode)

No load, f = 1.0 MHz

45

See Note (6)

Altera Corporation

IData Sheet

EP910

I

Capacitance See Note (7)

I

Symbol

IC
IC
IC

OUT

'----pa-r-am-e-te-r----,

I Input capacitance
I Output capacitance
I Clock pin capacitance

IN

elK

I vIN = 0 v, f = 1.0 MHz

I

I Input to output disable

1 t CLR I Register dear delay
0 input pad and buffer delay
10

It

1"

I C1

I

=

I

35 pF

1 33

TImIng Parameters

I 33

1

I I
EP91 0-30

It

I 24 I

I

----I

I 0

I

I-t-=C:":;"NT'---+I-M-ini-m-um-d-oc'--k-pe-r"""';io-d- - - I
1 Internal maximum frequency

I

I Note (6)

Asynchronous Clock Mode

Symbol
f MAX

Maximum dock frequency

t ASU

Input setup time

t AH

Input hold time

tACH

Clock high time

t

Clock low time

ACL

t ACOl

Parameter

Clock to output delay

t ACNT 1 Minimum dock period

I f ACNT I Internal maximum frequency
I Altera Corporation

I

1 33.31

I

I TimIng ParamelBrs

I

I

1 43

1

I

1 38

I

1

1 3'

EP91().$

I

I 43

30
30

1

30

'3'

0

EP910-40

I

I
1
I
I

30
30

-c-on-d-It-io-ns-;I

I 15
15

0

ns

I 27 I
I 0 I

I 31
I 0

1'--30-I
0

Unit

1

I

II

1 25.0

I

I:~

21
I. 35 1
.

I 28.61

I
I

I

I--~-I
.____

24
0
. 40 1 - - 0 - -

I

I 31.31
I 10 I
I 15 I

'__0 _ _

II~I

---I

1 I 16 I

I
1---1

1331
1301

I 17 1
17 1

I

1381
/35/

ns

1

I

0

I
I

~: I
ns
ns
ns
MHz

EP910-40

I 29.41
I 10 I
I 15 I

1

I

MHz I

(8)

I Note (6) I 33.31

ns

I
1
I
I

I

I

I ~!;bo
Min I Max I Min I Max I Min I Max I Note

I 33.31
I 10 I
---I' 15 I

ns

Non-Turbo
Adder

I 32.3 I

EP910-30 1 EP910-35

Note (10)

ns
ns

1 ns

I

I 37.0 I

18
I. 30 I.

.----:==.!.-_!.._ _ _ _....:...-_ _ _ _ _ _ _ _.

1 f CNT

3

II :~ II I::I II

I-!-=:~:-I!-~-::_:_:-=i~_hti-:_e----I
I t COl I Clock to output delay

1

Note (8)

-I

1 41.71

I Input setup time
I-t-=H~-!I-I--'-np-ut-h-Old"':""t-im-e

1 38

I
I Unit I

I Conditions I Min I Max I Min I Max I Min I Max I-N-ot-e-(8-~

I--:f=-u-A-X-il'-M-a-xi-mu-m-c-Ioc-k-f-re-qu-e-ncy--I Note (10)

su

1

I I 30 I I 35 I 140 I
I I 30 I I 35 I I 40 I

= 5 pF,Note (9)
=35 pF

I

Parameter

pF

I_I~I_I~I_I~I

Synchronous Clock Mode

I Symbol I

pF

20

I Min I Max I Min I Max I Min I Max I

Conditions

1 C1

I t PD2 1"

pF

20

I-N~-~-!~-;oo-I

_ _ _ _ _ _1 EP910-30 1 EP91().$1 EP91 0-40

I t PXZ

Input to non-reg. output
0 input to non-reg. output

20

Vee = 5 V ± 5%, T A = 0° C to 70° C for commercial use
Vee = 5 V ± 10%, TA = -40° C to 85° C for industrial use
Vee == 5 V ± 10%, Tc = -55° C to 125° C for military use

I t PZX I Inputto output enable

1

Unit

I

V IN = 0 V, f = 1.0 MHz

I
I C1
I

t POl

1

Max

I

v, f = 1.0 MHz

VOUT= 0

AC Operating Conditions

I TImIng Plll'/JlllelBrs
I Symbol I
Parameter

~I

Conditions

1

I
I

I
1

Unit

I

MHz I

I

30
0

ns
ns

I
I

1
1

0
0

ns
ns

1
1

1431
1401

I 28.6 LI 25.0 I I

30
0
0

I
I
MHz I
ns
ns

Page 83

I

2

I EP910
Notes to tables:
The minimum DC input is~.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
(2) Numbers in parentheses are for military and industrial temperature versions.
(3) For all clocks: tR and tF = 100 ns (50 ns).
(4) Typical values are for TA =25° C and Vcc =5 V.
(5) When in non-turbo mode, an EPLD will automatically enter standby mode if logic
transitions do not occur (approximately 100 ns after the last transition). The nonturbo standby current specification (lea) does not apply to the EP910-30 EPLD.
(6) Measured with a device programmed as a 24-bit munter.
(7) Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for
dedicated clock inputs only. Pin 21 (high-voltage pin during programming) has a
maximum capacitance of 60 pF.
(8) See "Turbo Bit" in this data sheet.
(9) Sample-tested only for an output change of 500 mY.
(10) The fMAX values represent the highest frequency for pipelined data.
(1)

Product Availability
Grade

I

Availability

Commercial

(0° C to 70° C)

Industrial

(-40° C to 85° C)

EP910-35, EP91Q-40

(-55° C to 125° C)

EP91 0-40

I Military

EP91 0-30, EP91 0-35, EP91 0-40

Note: Only military-temperature-range devices are listed above. MIL-STD-883-compliant
product specifications are provided in Military Product Drawings (MPDs), available from
Altera's Marketing Department by calling 1 (800) SOS-EPLD. These MPDs should be used
to prepare Source Control Drawings (SCDs). See Military Products in this data book.

Figure 9 shows the output drive characteristics for EP910 I/O pins and
typical supply current versus frequency for the EP910.
Figure 9. EP910 Output Drive Characteristics and Icc vs. Frequency
100mA , - - - - - - - - - - - - - - _ _ .
50

ci
~

<"
g
E

~

Turbo Mode

101..
~ 10mA

40

....

30

~

Vee =5.0V
TA
25° C

=

:::::J

0
'5

Vee

TA

= 5.0 V
=25°C

- ; 1.0mA
.~

a.

~

0

-

o
o

'5

1ooJ.IA

0

10J.IA

2

3

4

5

Vo Output Voltage (V)

IPage 84

1 KHz

10 KHz 100 KHz 1 MHz 10 MHz 40 MHz

Maximum Frequency

Altera Corporation

I

EP1800-Series EPLDs
High-Performance
48-Macrocell Devices

I October 1990, ver. 1
Features

Data Sheet I

o
o
o
o
o

o
o
o
o
o
o
o
General
Description

Erasable, user-configurable LSI circuit capable of implementing up to
2,100 equivalent gates of conventional and custom logic
"Zero power" (typically 35 J.LA standby)
High speed (EPl830 !Po = 20 ns)
48 macrocells with configurable I/O architecture allowing up to 64
inputs and 48 outputs
Programmable clock option allowing independent clocking of registers
Individually programmable registers prOViding D, T, JK, and SR flipflops with individual asynchronous Clear control
Accepts popular TIL 551- and MSI-based macrofunction design inputs
TIL/CMOS I/O compatibility and full military capability
100% generically testable to provide 100% programming yield
A+PLUS software support featuring schematic capture, Boolean
equation, state machine, truth table, and netlist design entry methods
A vailable in 68-pin windowed ceramic and plastic one-timeprogrammable J-Iead and windowed ceramic PCA packages
Extensive third-party support

The EP1800-series Erasable Programmable Logic Devices (EPLDs) offer LSI
density, TTL-equivalent speed, and low power consumption. Each EPLD
can replace 20 to 30 551 and MSI packages. These EPLDs are available in 68pin windowed ceramic and plastic one-time-programmable J-lead and
windowed ceramic Pin Grid Array (PCA) packages. See Figure 1.
EP1800-series EPLDs are designed as LSI replacements for traditional lowpower Schottky TTL logic circuits and low-density Programmable Logic
Devices (PLDs). The speed and density of these EPLDs enable them to
implement high-performance, complex functions, such as dedicated
peripheral controllers and intelligent support chips. IC count and power
requirements are considerably reduced with EPl800-series EPLDs, thus
minimizing the total size and system cost and significantly increasing
reliabili ty.
EP1800-series architecture enables the designer to easily integrate designs
with conventional TTL 551 and MSI building blocks. Logic is implemented
with Altera's A+PLUS Development System, which supports schematic
capture, state machine, Boolean equation, and netlist design entry methods
and includes a library of standard TTL functions to facilitate integration.
A+PLUS also provides a library of optimized gate and flip-flop elements.
The A+PLUS Design Processor (ADP) automatically minimizes and

IA/tera Corporation

Page

8s1

2

Data Sheet I

EP1800-Series EPLDs

Figure 1. Package Pin-Out Diagrams

Package outlines not drawn to scale.

~ ~
~ ~
L()
L()

10
11

L()
L()

INPUT
INPUT

CLK111NPUT

vee
INPUT

CLK2IINPUT
INPUT
INPlJT
INPlJT

18

10
10
10

0

NPUT
QJ(04IN'UT

vee

....
-!
I

P

-[>0-

c::::>--JI

D-

..i'

I

c::>--'
I

I

C>-'
I

I

P 0-

jI>-

jI>-

nn
R±J...lR±J. .

j
. j 1/0 Pin
·t••••••••••••••••••••••• :.

........................····················1
..

I

C>--4

..

I

..

i

--------------------- --------------- ------------I

I

Figure 4 illustrates a simple logic function that can be implemented in a
single macrocell. This function implements all combinatorial logic in the
logic array, uses a JK flip-flop, and permanently enables the tri-state
buffer.
Figure 4. Sample Circuit
This figure shows a typical logic function implemented in a single maaoee/I.
Each EP1800-series maaoee/I can accommodate up to 40 equivalent gates.

t

Device
Inputs

l'i'~kA;,:~y'"

~===

II

t=::r ======::::;,

__ ._ .. _____ ._______ ._M~~~~!I.!! ....... _.... _.. _... _.. .

LOAD

Flip-Flop
Selection

t

ENT

110 Pin

ENP

DATAD

CLEAR

to other
Macrocells

IAltera Corporation

Page

891

DatsShHtl

EP1800-Serles EPLDs

EPl800-series EPLDs have 4 identical quadrants, each containing 12
macrocells. Internal bus structures in these EPLDs feed input signals into
the macrocells. Macrocell outputs drive the external pins and internal
buses.
Of the 48 macrocells, 36 are local (see Figure 5) and 16 are global macrocells
(see Figure 6). Local macrocells offer a multiplexed feedback path (with
pin or macrocell feedback) and drive the local bus in their quadrant. Global
macrocells feature two dedicated feedback paths: one feeds the local bus;
the other feeds the global bus. This process, called "dual feedback," allows
global macrocells to implement buried logic functions while the associated
I/Opinis usedasan input. Dual feedback ensures maximum I/O flexibility.

Figure 5. Local Macraeell
Quadrant
Synchronous

..

CIoQ(

Loca I Bus

GIobIBu
a
s
~

~

o!!

~

vee OEICLOCK

-tl~·

OElCLK

g
g
g
g

D-

CLEAR

41/1

•••

~

? 6
!

I

Global
Dedicated
Inputs
(16 Inputs)

IPage 90

c~

~
I

•••••

~

~

....

~ Q

Quadrant
A,B,C,D
Global
Feedback
(16 Macrocells)

I

~

Local Bus

"r

I

I

OE

I/O

Architecture
Control

t
10-

~

~

I/O Pin

Feedback

~

I

1

I

Quadrant
Local
Feedback
(12 Macrocells)

Altera Corporation

I

I Dsts Sheet

EPl800-Series EPLDs I

Figure 6. Global Macraeell
GlobaIBus

•

• •

Loc al Bus

Quadrant
Synchronous
Clock

•

OEICLK

~~
g
g
g
g

6
7

va

Architecture

Control

. . . >-t~r-C

1/0 Pin

D-

CLEAR

...

.....

~

}1

n

Global
Dedicated
Inputs
(16 Inputs)

....

~

1

\1\

'T

Local Bus

~~

Quadrant
A,B,C,D
Global
Feedback
(16 Macroce"s)

Global Bus

Quadrant
Local
Feedback
(12 Macrocells)

Both global and local macrocells have the same timing characteristics.
Delay pa ths are shown in Figure 7. Switching waveforms for EPl800-series
EPLDs are shown in Figure 8.

Figure 7. Macraeel/ Delay Paths

If the register is bypassed, the delay between the logic array and the output buffer is zero.
INPUT

Output
Delay

INPUT

'00

lxz
lzx

INPUT

1/0

110
Delay

Feedback
Delay
'FD

tID

IA/tera Corporation

Psge 91

I

EP1800-Serles EPLDs

DatsShHt
tPOl - tIN + tLAD+ too

Figure 8. Switching Waveforms
110 Pin

tR&tF<3ns

Inputs are driven at 3 V for a logic
high and 0 V for a logic low. All
timing characteristics are
measured at 1.5 V.

I

Input Mode. to.
tP02 - to + tIN + tLAD+ too
=+-=
------~:~~i------------------------------------­

_________~~~_+l----------------------------------------~

Input Pin

---------*~~!:------------------------------t LAD

.'

Logic Array Input

Logic Array Output

Output Pin

'.

---------~f.~---------+!-------------t CLR
.:

---------------------------~~.~----------------too
!I
Ii
_______________________________________
-Ji.--------Clock Mode
t~

Clock Pin

t

..c.i

liol-t_ _ _CH,;.;.;....__

___..J/

t CI.
ioI-it____
_____..c.i

N

t~

l.-

V~----i.N,-l

__

~

Clock into Logic Array

--------~V~---~,~------~/
t
/C

:I

Clock from Logic Array

Data from Logic Array

.:

v~----~,~

------------:-.-t-~--~itH:

____

~r____

_______~i~____'~r~i~=======================
l
t
FD

Register Output to Logic Array

-------------~*-------------System Clock Mode
t ~ :.
t CH

System Clock Pin

: tIN

System Clock at Register

:

--~i.~

tsu

t...;;CI.~~.:

i 4• :_ _ _

t ~ i1/~----~N\-i_____

: tICS

r '1 V

••

Data from Logic Array

I:

_____---l~r;----.. . .~

,'-----~/

ltH:

'--

__.~i.~-----------------------I"t .:

Output Mode
Clock from Logic Array

________---J/

'----

,'-____--J/

:

too:

===x==:j

i1::

~

Data from Logic Array

Output Pin

____________

--

x=l:.

t xz:

I1'--t-zx--:-------

~i..~-------~j,

~------

'High Impedance
Tn-State

Clock
Options
I Page 92

Each internal flip-flop in EPl800-series EPLDs can be clocked independently
or in user-defined groups. Each internal register may select its clock source
from a dedicated system clock pin or a product term within the macrocell.
Any input or internal logic function can be used as a clock.

A/tera Corporation

I

I Data Sheet

EP1800-Series EPLDs I

Product-term clock signals allow flip-flops to be configured for positive- or
negative-edge-triggered operation.
Four dedicated system clocks (CLXl to CLX4) also provide synchronous
or asynchronous clock signals to the flip-flops. One system clock is located
in each quadrant; each clock is connected directly to an EPl800-series
external pin. Synchronous clocks provide clock-ta-output delay times that
are faster than internally generated clock signals. Asynchronous pin-driven
clock signals are activated by inserting a clock buffer (eLXB) primitive
between the clock pin and the flip-flop clock input. When system clocks
are used, the flip-flops are triggered by the positive edge, i.e., data transitions
occur on the rising edge of the clock.

Functional
Testing

EP1800-series EPLDs are fully functionally tested and guaranteed through
complete testing of each programmable EPROM bit and all internal logic
elements. A 100% programming yield is ensured. These EPLDs allow test
programs to be used and then erased during early stages of production.
The ability to use application-independent, general-purpose tests-called
generic testing-is unique to EPLDs. The EPLDs also contain on-board test
circuitry that allows verification of functions and AC specifications for
one-time-programmable packages. AC test measurements are performed
under the conditions shown in Figure 9.

Design
Security

EP1800-series EPLDs contain a programmable Security Bit that controls
access to the programmed information. If this Security Bit is used, a
proprietary design implemented in the device cannot be copied or retrieved.
Since this option makes programmed data within EPROM cells invisible,
the designer has a high level of design security. The Security Bit, as well as
all other program data, is reset by erasing the EPLD.

Turbo Bit

All EP1800-series EPLDs contain a Turbo Bit, set with the A +PLUS software,
to control the automatic power-down feature that enables the low standbypower mode. When the Turbo Bit is programmed (Turbo = On), the low
standby-power mode (leCl) is disabled, making the circuit less sensitive to
Vee noise transients from the non-turbo mode power-up/power-down
cycle. The typical Icc versus frequency data for turbo and non-turbo mode
is shown in each EPLD data sheet. All AC values are tested wi th the Turbo
Bit programmed.
If the design requires low-power operation, the Turbo Bit should be
disabled (Turbo = OfO. When operating in this mode, some AC parameters
may increase. To determine worst-case timing, values given in the AC
Non-Turbo Adder specifications must be added to the AC parameter.

I Altera Corporation

Page

931

fl

EP1800-Series EPLDs

Data Sheet

Rgure 9. AC Test Conditions
Power supply transients can affect AC
measurements. Simultaneous transitions of
multiple outputs should be avoided for
accurate measurement. Threshold tests must
not be performed under AC conditions.
Large-amplitude, fast-ground current
transients normally occur as the device
outputs discharge the load capacitances.
When these transients flow through the
parasitic inductance between the device
ground pin and the test system ground, it can
create significant reductions in observable
input noise immunity.

IPage 94

_----vcc
to Test
System

Device input
rise and fall
times < 3 ns

Altera Corporation

I

EP1830i
o

Features

o
o
o
o

High-performance 48-macrocell EPLO
Combinatorial speeds with tpD =20 ns
Counter frequencies up to 50 MHz
Pipelined data rates up to 62.5 MHz
Low power
Icc = 20 rnA (typical) for four 12-bit counters at 1 MHz
Icc =50 J.LA (typical) in standby mode
A vailable in windowed ceramic and plastic one-time-programmable
chip-carrier packages
68-pinJ-lead (ceramic and plastic)
68-pin PCA (ceramic)
Macrocell flip-flops can be individually programmed as 0, T, JK, or
SR flip-flops, or for combinatorial operation.
Programmable Clock option allows independent docking at all
registers.

Figure 10 shows the pin-outs for the EP1830 EPLO.

Figure 10. EP1830 Pin-Out Diagrams
Package outlines not drawn to scale.

10
10

110
110
110
INPUT
INPUT
INPUT
ClK1/1NPUT

0

vee
ClK2JINPUT
INPUT
INPUT
INPUT
110
110
110
110

EP1830

~~~~~~~~~~~~~~~~Q

QQQQQQ~Q~QQQQQQQQ

"

10
NPUT
NPUT
NPUT

10

110 K

10

110 J

100

110 H

10

110 G

ClK~INPUT

vee
ClK3IINPUT
NPUT
NPUT
NPUT
10
10
10
10

100

GNO

F

10

110 E

10

110 0

10

110 C

100

110 B

~00000000

0·000000000
00
00
00
00
EP1830
0~
0~
Bouom
0·
0·
View
00
00
00
00
00
0000000000000
000000000
12345&78

Q Q

~ ~

i i
~ i

i i
IIi
~

d

J-Lead

I A/tera Corporation

•

10

10

110

10

110

10

110

10

100

GNO 110
10

110

10

110

10

110

10

110

11

!Ii! Q
~

!l

d

PGA

Page9s1

6

I EP1830

Data Sheet

Absolute Maximum Ratings

I

Symbol
vee

I

I
I
I

Parameter

Suepl~ voltage

VI

DC ineut VOltage

I MAX

DC Vee or GND current

lOUT

DC outeut current, eer ein

I

I TSTG

With respect to GND

Min

Max

Unit

-2.0

7.0

V

-2.0

14.0

V

-2.0

7.0

V

-300

+300

mA

-25

+25

mA

1500

mW

See Note (1)

I
I

I

-65

+150

°C

-65

+135

°C

Min

Max

Unit

4.75

5.25

V

, Input VOltage

0

Vee

V

I Output VOltage

0

Vee

V

Storage temperature

, Ambient temperature

TAMB

Conditions

I

I Power dissipation

Po

I

Note: See Operating Requirements for EPLDs in this data book.

I Pr~ramming suppl~ VOltage

Vpp

I

No bias

, Under bias

Recommended Operating Conditions

I

I

Symbol

I

I vee

I VI
I Vo

Parameter
Supply voltase

ITA

, Operatins temperature

ITA

, Operating

I Te

I Case temperature

I Input fall time

DC Operating Conditions
See Note (3)

Symbol

I

. Vee == 5 V
V ce = 5 V
Vec = 5 V

0

+70

°C

For industrial use

-40

+85

°C

For military use

-55

+125

°C

See Note (2)

50

ns

See Note (2)

50

ns

Max

Unit

Vee + 0.3

V

For commercial use

tem~rature

I Input rise time

ItR
,tF

I

Conditions

± SOlo, T A = 0° C to 70° C for commercial use
± 10%, T A = -40° C to 85° C for industrial use
± 10%, Te = -55° C to 125° C for military use

Parameter

I

Conditions

I

i

I-v-,H - - - ',--H-ig-h--Ie-v-e-'in-p-u-tv o - , t - a g - e - - - - ' - - - - - - - - I

I

V IL

I low-level input voltage

I

l-v....:.;o=-H---il·-H-i9-h--le-ve-1TT-'--l-ou-tP--'u<-tvo-I-ta-ge--I" IIOOHH :_

I

V OH

I VOL

I low-level output voltage

I~I

I

I
,I

I

2.0

I

-0.3

I

32.8.44

I ,:

"

I

I

Typ

0.8

V
,V
V

I

I

I

, High-level CMOS output voltage

~
I eel

~2 mmAA DCDC

Min

I I OL = 4 mA DC

In utleaka ecurrent
Tri-state out ut off-state current
Vee supply current (standby)

VI = Vee orGND

I

V 0 = Vee or GND
V I = Vee or GND

I

0.45

V

~~~~

~~~~

I

I

50

I

150

I

~

I

No load See Note (4)
I ee2

= Vee or GND

Vee supply current

VI

(non-turbo mode)

No load, f = 1.0 MHz

Vee supply current

VI

(turbo mode)

No load, f = 1.0 MHz

20

40

mA

150

200

mA

See Note (5)

I ee3

= Vee or GND

See Note (5)

Page 96

A/tera Corporation

I

IData Sheet

EP1830

I

Capacitance See Note (6)
Symbol
C,N
COUT
CCLK

I

Parameter

Conditions
I
I V IN = 0 V, f = 1.0 MHz

I Input capacitance

I
I

I

Output capacitance

I

Clock pin capacitance

H

ItCH

Register hold time
Clock high time

I~ :

~:::a~e

I tiCS

System clock delay

I t FD
I t CLR
t CHT

Feedback delay
Register clear delay

Unit

20

pF

I
I

VOUT= 0 V, f = 1.0 MHz

I

V,N=OV, f=1.0MHz

Max

I

20

I

25

I
I

pF

I

pF

Vee = 5 V ± 5%, TA. = 0° C to 70° C for commercial use
Vee = 5 V ± 10%, TA. = -40° C to 85° C for industrial use
Vcc = 5 V ± 10%, Tc = -55° C to 125° C for military use

AC Operating Conditions

It

Min

II

I'

88

I'

I'

0
11 0

I'

I'

1122

I'

I'

00

1----1 1 110 112 112 1151 ~
8

I
I
I

I
I
I

9

I
I

4
3

I
I

I
I

5

3

I
I

I
I

7
3

I
I

I I I I I I

Minimum clock period

0
-25

9

12

15

25

20

25

30

o

I'

nnss

I'

I:: 1
I
I

I

ns
ns
ns

I
I

I

ns

(register output feedback to
register ineut)

f
I

CHT

I'nternal maximum frequency

I See Note (5)

I 50

I

1ft CNT

IAltera Corporation

Page

971

Data Sheet

EP1830

I

Notes to tables:
(1)

(2)

(3)
(4)

(5)
(6)

(7)
(8)
(9)

The minimum IX input is -0.3 V. During transitions, inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
For all clocks: tR and tF =20 ns.
Typical values are for TA =25° C and Vcc =5 V.
When in non-turbo mode, an EPLD automatically enters standby mode if logic
transitions do not occur (approximately lOOns after the last transition). The nonturbo standby current specification (lca) does not apply to the EP1830-20 EPLD.
Measured with a device programmed as four 12-bit counters.
Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for
dedicated clock inputs only. Pin 19 (high-voltage pin during programming) has a
maximum capacitance of 160 pF.
See "Turbo Bit" earlier in this data book.
Sample-tested only for an output change of 500 mY.
The fMAX values represent the highest frequency for pipelined data.

Product Availability

I

I Commercial
I Industrial

I

Availability

Grade
(0° C to 70° C)

Consult factory

(-55 C to 125 C)

Consult factory

0

Military

EP1830-20, EP1830-25, EP1830-30

(-40 0 C to 85 0 C)
0

Note: Only military-temperature-range EPLDs are listed above. MIL-STD-883-compliant
product specifications are provided in Military Product Drawings (MPDs), available from
Altera Marketing by calling 1 (800) SOS-EPLD. These MPDs should be used to prepare
Source Control Drawings (SCDs). See Military Products in this data book.

Figure 11 shows output drive characteristics for EP1830 I/O pins and
typical supply current versus frequency for the EP1830.
Figure 11. EP1830 Output Drive Characteristics and Icc vs. Frequency
300mA
50

ci.

Turbo Mode

>.

150mA

r

<'
S
'E
~

::;

40

ci.

~

<'
S

30

Vee =5.0V
= 25° C

TA

Q)

0

'5
Q.
'5
0

loomA

.~

20

c(

10mA

()
()

0

1 rnA

2

3

4

5

Vo Output Voltage (V)

Page 98

10 KHz 100 KHz 1 MHz

10 MHz 40 MHz 60 MHz

Maximum Frequency

Altera Corporation

I

EP1810 I
o

Features

o
o
o
o

High-performance 48-macrocell EPLD
Combinatorial speeds with tpD = 35 ns
Counter frequencies up to 28.6 MHz
Pipelined data rates up to 40 MHz
Low power
Icc = 10 rnA (typical) for four 12-bit counters at 1 MHz
Icc = 35 J.LA (typical) in standby mode
Available in windowed ceramic and plastic one-time-programmable
packages
68-pin J-lead (ceramic and plastic)
68-pin PCA (ceramic)
Macrocell flip-flops can be individually programmed as D, T, JK, or
SR flip-flops, or for combinatorial operation.
Programmable Clock option allows independent clocking of all
registers.

Figure 12 shows the pin-outs for the EP1810.
Figure 12. EP1810 Pin-Out Diagrams
Package outlines not drawn to scale.

~

10
10
10
10
NPUT
NPUT
NPUT

53
52

vee

60
58
58

110
110
110

57

INPUT

5&

INPUT
INPUT
ClK1/INPUT

55

0

vee
ClK2JINPUT
INPUT
INPUT
INPUT

EP1810

110
110
110
110

51

so
48
.018

47
46

45

....

10

110 K

110

110 J

110

110 H

110

110 G

110

GNO F

ClJ(~INPUT

ClK3IINPUT
NPUT
NPUT
NPUT
10
10
10
10

110

110 E

100

110 0

110

110 C

100

110 B

~~~~~~~~~~~~~~~~~

QQQQQQQQ~QQQQQQQQ
C1

1

2

3

Q Q

2 2

..

5

i i
2 i

8

~

~

7

II

i i
!i

•

10

11

Q Q

2 2

d d
J-Lead

I Altera Corporation

PGA

Page 99

I

fI

EP1810

Data Sheet

Absolute Maximum Ratings
Symbol

Note: See Operating Requirements for EPLDs in this data book.

Parameter

I

Vpp

Pr~ramming suppl~

Conditions

I

Min

I With respect to GND
I

I soppll voltage

vee

vOltage

See Note (1)

Max

Unit

-2.0

7.0

V

-2.0

13.5

V

VI

I DC input voltage

I

-2.0

7.0

V

I MAX

I DC Vee or GND current

-300

+300

mA

lOUT

I DC OUte'Jt current, eer ein

I

Po

-25

I
I

Power dissieation
I Storage temperature

TSTG

mA

+25 .

mW

1500
-65

+150

°C

-65

+135

°C

Min

Max

Unit

4.75 (4.5)

5.25 (5.5)

V

0

Vee

V

0

Vee

V

I No bias

I Ambient temperature

T AMB

I

Under bias

Recommended Operating Conditions

I

Symbol

I vee

Parameter
I
I Suppl~ voltage

, VI

, Input voltage

I

Ivo

Output

, See Note (2)

volta~e

I Operating temperature

ITA

Conditions

I

For commercial use

0

+70

°C

'TA

I Operating temperature

For industrial use

-40

+85

°C

ITe

I Case temperature

For military use

-55

+125

°C

ItR

I Input rise time

100 (50)

ns

ItF

I Input fall time

100 (50)

ns

DC Operating Conditions
See Note (3)

Symbol

Vee = 5 V
Vee = 5 V
Vee = 5 V

± 5%, TA = 0° C to 70° C for commercial use
± 10%, TA = -40° C to 85° C for industrial use
± 10%, Tc = -55° C to 125° C for military use

,----p-a-ra-m-e-te-r----

-V-I-H---I High-level input voltage

_V-'I~L_ _ _I
o

, High-level CMOS output voltage

-v--'o=L...!...---1 Low-level output voltage

I Tri-state output off-state current

I oz

--_°

Vee supply current (standby)

lee2

Vee supply current
(non-turbo mode)

2.0

'TYP

I

I

I

~

=-4 mA DC

Max

, Unit

Vee + 0.3'

V

,
I

~-------v--l

II OH = -2 mA DC

'3.84

I

I

II OL = 4 mA DC

I

,

I

0.45

= Vee or GND
I V 0 = Vee or GND
1 V I = Vee or GND

,I

-10,'

I

+ 10

I

+10

No load See Note (4)

1

Min

10~---I~~v
IOH

_1-,-1_ _ _ I-I-np-ut-Ie-a-ka-ge-'-C-ur-re-nt--'<-----I V I

-1"";:;e=e'-1

I

--------,

Low-level input voltage

_V--,O=H...!...-_ _ High-level TTL output voltage
V OH

Conditions

= Vee or GND
No load, f = 1.0 MHz

VI

-1 0
°

°

1

1

35

°

150

1

I

V

I

I

V

I

I

I
°

~
~
~

1

I

I
°

1

10

30 (40)

mA

100

180 (240)

mA

See Note (5)

lee3

= Vee or GND

Vee supply current

VI

(turbo mode)

No load, f = 1.0 MHz
See Note (5)

Page 100

Altera Corporation

I

I Data Sheet

EP1810

I

Capacitanc. See Note (6)

I Symbol
I C,N
I COUT
, CCLK

Parameter
Input capacitance

V ,N =0 V, f

Output capacitance

VOUT= 0 V, f = 1.0 MHz

I Clock ~in capacitance

AC Operating Conditions

Vee
Vee
Vee

= 5 V ± 5%, T A = 0° C to 70° C for commercial use
= 5 V ± 10%, TA = -40° C to 85° C for industrial use
= 5 V ± 10%, Tc = ~5° C to 125° C for military use

I

TImIngParame/m'S

I Symbol I Parameter
It I

1 C 1 - 35 pF

It

IN

I Input pad and buffer delay I

,t

10

110 input pad and buffer delay

I t LAD

logic array delay

t 00
t zx

Output buffer and pad delay
Output buffer enable

ut

1 t XZ

OUtD buffer

d~~e

Maximum clock frequency

MAX

,Register setup time

I II :~:;::i~
II::: II ~:: ~hti:
tHS
tH

Register hold time

t

Clock delay

IC

I
I System clock delay
I t Fa I Feedback delay
I t I Register clear delay
tiCS

CLR

t

I

EP181G-40

Unit

20

_..:....pF_ _

20

pF

25

pF

IEP181~ I~!~~

40

1 t PD. 1 :,;:ut to non-registered

1

EP181 0-35

~
Max

I Conditions I Min I Max I Min I Max I Min I Max I
Input to non-registered output I
CI 35 CI I I~I

PD1

If
I t su

= 1.0 MHz

V IN = 0 V, f = 1.0 MHz

I

I"

Min

Conditions

CNT

LI 1__lj__1 1
40

I

1

'----1

7

50

I

I

7

I

I

7

I

I I 5 1 15 1
I
I I 19
'23
I 27 I
C
=
35
pF
' "
'I
I
5

1

1

I
1

I
I

1

~~:::~8)
See Note (9)

1
I
II
I
I
I

Note (7)

I

I

9

9

1

1 10

I

10

I'

I

11

11

I

1 1 CI I 1 I
9

I 40.0 1
, 10 I

11

to

, 35.71
'11

I

1 33.31

I

I 11 I

,

30
30
0
0

30
0

0

0
0

0

1

n
j'

Unit

I
Ia

fl g
ns

I

ns

1 ns

I

ns

1 ns

I

I
,
,

I

ns

I

ns

I

1

1 MHz 1

I

ns

,

I, 0U_
1_1_0I_I 0 I I
I
I I 1
I
II :: II I::I II I:: II II ~ I:
I
I I
o

ns

15

'17'

19

18

23'

27

I 1~--1-6---1-8-'
II 6 I I 6 1 I 7 1
I j;l
28
I 32 I
I

Minimum clock period

35

1

45

40

ns

0

30
0

-30
30

o

I
I
I

ns

,

ns

I
I

ns

I

ns

ns

(register output feedback to
r~ister

1 f CNT I

input)

~~t;:Tmaximum frequency

I Altera Corporation

1 See Note (5)

1

28 6
. 1

1

25 0
. 1

1

22 2
. 1

1_ _0_ _1 Miz I

Page 101

I

I EP1810

Data Sheet

I

Notes to tables:
The minimum IX input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
Numbers in parentheses are for to military and industrial temperature versions.
Typical values are for TA =25° C and Vcc =5 V.
When in non-turbo mode, an EPLD will automatically enter standby mode if logic
transitions do not occur (approximately 100 ns after the last transition). The nonturbo standby current specification (lea) does not apply to the EP1810-35 EPLD.
Measured with a device programmed as four 12-bit counters.
Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for
dedicated dock inputs only. Pin 19 (high-voltage pin during programming) has a
maximum capacitance of 160 pF.
See "Turbo Bit" earlier in this data sheet
Sample-tested only for an output change of 500 mY.
The fMAX values represent the highest frequency for pipelined data.

(1)

(2)
(3)
(4)

(5)
(6)

(7)
(8)
(9)

Product Avai/ability
G_r_ad_e__________ i__________

1_ _ _ _ _ _ _ _ _

I Commercial
I Industrial

I

Military

A_v_a_ila_b_il_i~___________

(0°Cto70°C)

EP1810-35,EP1810-45

(-40 0 C to 85 0 C)

EP181 0-40. EP1810-45

(-55 0 C to 1250 C)

EP1810-45

Note: Only military-temperature-range devices are listed above. MIL-STD-883-compliant
product specifications are provided in Military Product Drawings (MPDs), available from
Altera's Marketing Department by calling 1 (800) SO>EPLD. These MPDs should be used
to prepare Source Control Drawings (SCDs). See Military Products in this data book.

Figure 13 shows output drive characteristics for EP1810 I/O pins and
typical supply current versus frequency for the EP1810.
Figure 13. EP1810 Output Drive Characteristics and Icc vs. Frequency
50

~
;(

l00mA

101..

ci.

Turbo Mode

ci.
~
;(

40

§.
'E
~

:;
:;

Vee =5.0V
= 25° C

30

a.

10mA

Vee =5.0 V
= 25° C

TA

Q)

TA

()

:;

§.
>

~

0
c(

20

0
0

0

1.0mA

0

l00j.iA

2

3

4

5

Vo Output Voltage (V)

I Page 102

1 KHz

10 KHz 100 KHz 1 MHz 10 MHz 40 MHz

Maximum Frequency

Altera Corporation

I

PLS-SUPREME
Enhanced A+PLUS
Programmable Logic Software

I October 1990, ver. 1
Features

Data Sheet I

o
o
o
o
o

o

o
General
Description

High-level support for Altera's general-purpose EP-series EPLDs
Multiple design entry methods
LogiCaps schematic capture
Boolean equation and netlist
State machine and truth table
Complete symbol library of basic gates and over 120 TTL
macrofunctions
Support for user-defined macrofunctions with ADLIB software
Fast and efficient design processing to ensure rapid design cycles
Elimination of unused gates
Automatic pin and part assignments
SALSA logic minimization
Device Fitter to optimize EPLD resources
Functional simulation for quick design verification
Easy definition of inputs with state tables, vector patterns, or
predefined patterns
State table or graphic waveform output formats (on-screen or
hard-copy)
Access to buried nodes within the design
Used with IBM PS/2, PC-AT, and compatible computers

Altera's PLS-SUPREME (Enhanced A+PLUS Programmable Logic
Software), shown in Figure 1, is a com prehensive CAE system for designing
logic with the Altera EP-series (classic) EPLDs. PLS-SUPREME provides
multiple design entry methods, including LogiCaps schematic capture,
Boolean equation, state machine, truth table, and netlist design entry.
These entry methods may be combined, allowing the designer to "mix and
match" the entry methods that best suit each design. This package also
interfaces with several third-party design entry formats. (Contact Altera
Applications at 1 (BOO) BOO-EPLD for more information.)
A+PLUS includes the Altera Design Processor (ADP), which consists of
integrated modules that produce an industry-standard JEDEC file for
programming the EPLD. The ADP implements logic minimization,
automatic EPLD part selection, architecture optimization, and design fitting.
In addition, the ADP produces documentation that shows minimized logic
and EPLD utilization.
PLS-SUPREME also includes a functional sim ulator (FSIM) to verify designs,
and LogicMap II software to program EPLDs. (Altera programming

1

Altera Corporation

Page 1031

fl

I PL5-SUPREME

Data Sheet

I

Figure 1. A+PLUS Block Diagram
Design Entry

8:

..........................;

hardware is not included in PLS-SUPREME. Refer to the PLCADSUPREME or PL-ASAP data sheets for more information about products
that include hardware.} PLS-SUPREME software runs on an IBM PS/2,
PC/AT, or compatible computer and offers the most comprehensive support
available for Altera's classic EPLDs.

Design Entry

A+PLUS provides the following design entry methods: LogiCaps schematic
capture, Boolean equation, state machine, and truth table design entry.

LogiCaps Schematic Capture
Logic schematics are created with LogiCaps, which allows the user to
quickly construct a wide range of logic circuits. LogiCaps provides two
libraries that can be supplemented with libraries created by the user:

o
o
o
I Page 104

The A+PLUS Primitive Library includes basic logic gates and flipflops.
The A+PLUS TIL MacroFunction Library has more than 120 TTLequivalent macrofunctions, including counters, decoders, and
comparators. This library also includes A+PLUS-specific macrofunctions that are optimized for the Altera EPLD architecture (see Table 1).
User-defined libraries can be created easily with the Altera Design
Librarian (ADLIB), allowing custom development of new
macrofunction elements.
Altera Corporation

I

IData Sheet

PLS-SUPREME

I

Table 1. A+PLUS Afacrofunctions
Type

Available

Adders

7480,7482,7483,74183,8FADD

Comparators

7485, 74158, 74518, 8MCOMP

Converters

74184,74185

Counters

7493,74160,74161,74162,74163,74190,74191,74393, 74160T, 74161T, 74162T,
74163T, 7419OT, 74191T, 74192T, 74193T, 8COUNT, 4COUNT, 16CUDSLR, UNICNT2,
GRAY4

Decoders

7442,7443, 7444,7445,7446,7447,7448,7449,74138,74139, 74154,74155,74156

Flip-Flops

7470,7471,7472,7473,7474,7476,7478,74173,74174, 74175, 74273,74374

Frequency Divider

FREQDIV

Latches

7475, 7477, 74116, 74259, 74279, 74373, NANDLTCH, NORLTCH

Multipliers

74261, MULT2, MULT24, MULT4

Multiplexers

74147,74148,74151,74153,74157,74158,74298,21MUX

Parity Generators

74180, 74280

Shift Registers

7491,7494,7496,7499,74164,74165,74166,74178,74179, 74194, 74198,
BARRELST, UNICNT2

SSI Functions

7400,7402,7404,7408,7410,7411,7420,7421,7427,7430, 7432,7486, INHB, CBUF

Storage Registers

7498, 74278

fJ

True/Comp Element 7487
ALU

74181

LogiCaps features easy-to-use mouse and keyboard command entry. Tagand-drag editing with orthogonal rubberbanding, multiple zoom levels,
and a dual-window display mode simplifies schematic entry. (See
Figure 2.) Schematics can be printed on Epson FX- and LQ-series printers,
and HP7475A, and 7585B, and 7495A drafting plotters. An Altera Design
File (ADF) is generated when a design is saved and linked with other
design files or processed directly with the Altera Design Processor (ADP)
to generate a JEDEC file.

Boolean Equation Entry
The ADF syntax supports Boolean equation design entry and features freeform entry of all syntactical elements. Boolean equations need not be
entered with a minimized sum-of-products form because the ADP
automatically minimizes the equations before generating the JEDEC
programming file. ADF-format versions of the 120 macrofunctions used
with LogiCaps are also available. An ADF is created with any standard text
editor (in non-document mode). Once a design has been entered, it can be
linked with schematic or state machine files, or directly processed by
A+PLU5.

IA/tera Corporation

Page 105

I

Data Sheet

PLS-SUPREME

Figure 2. Schematic Design Entry
with Log/Caps

Bi .. _ B 5

B

I

9B

I

I

I

EPLD designs can be entered
in LogiGaps with popular
7400-series symbols from the
A+PLUS TTL MacroFunction Library.

1------74-.-8 .. -----1

~l. ~p.I==~1
L?_ ,._".......... __ ~!

a

I

,

.

ine

D.l .. ~ ..

State Machine and Truth Table Entry
State machine designs are entered in Altera's State Machine File (SMF)
format (see Figure 3). This high-level language description features IFTHEN statements, CASE statements, and truth tables. Outputs of state
machines maybe defined conditionally or unconditionally, allowing flexible
output structures to be merged with other portions of the design. SMF
syntax also allows multiple state machines to be defined in a single file.
Truth tables may also be used to specify random logic. Once a design has
been entered, A+PLUS automatically generates state equations and
transforms state machine descriptions, automatically choosing D or T
registers for the state variables to ensure the most efficient use of EPLD
resources.
Figure 3. State Machine Diagram and Partial State Machine File
tlACHIttE: dispenser
CLOCK:
CLK
STATES: [DROPCUP
[
S1
6
[
S2
1
[
S3
6

ICUPFULL

Page 106

POURDRtt)(]
6
6

]

1

]

]

S1:
IF COIttDROP THEft S2
" tto outputs "
S2:
S3
S3:
IF CUPFULL THEft S1

A/tera Corporation

I

I Data Sheet
Design
Processing

PLS-SUPREME

I

The Altera Design Processor (ADP) consists of a series of modules that
automatically transforms the design into a JEDEC file used to program the
EPLD. First, the design is "flattened" from high-level macrofunctions to
low-level gate primitives. Next, the ADP analyzes the complete logic
circuit and removes unused gates and flip-flops. This ''MacroMunching''
enables the designer to freely use high-level building blocks from the
macrofunction library without worrying about optimizing the logic.
When the ADP detects macrofunctions with unconnected inputs, it assigns
the following "intelligent" default values: active-high inputs default to
GND, active-low inputs default to Vee. Thus, the ADP enhances
productivity by automatically performing some of the designer's "busy
work."
The Translator module checks the design for logical completeness and
consistency. For example, it ensures that no two logic function outputs are
tied together and that all logic nodes have an origin. Also, if AUTO is
entered as the EPLD name, the Translator automatically selects the EPLD
best suited to the logic requirements of the design.
The Expander module expands the Boolean equations into sum-of-products
form, checks for evidence of combinatorial feedback, and removes
redundant factors from product terms.
Logic minimization of designs is performed by the Minimizer module.
Minimization tools include Boolean minimization with SALSA (Speedy
Altera Logic Simplifying Algorithm), which yields results that are superior
to other heuristic reduction techniques. The Minimizer uses algorithms
that select equations best represented by a complemented AND/OR
function. This feature reduces product-term demands generated by complex
logic functions. Moreover, for Altera EPLDs with programmable flipflops, the Minimizer determines which type of flip-flop yields the most
efficient solution and, if necessary, converts the architecture to D or T
flip-flops.
The fully minimized design is then transferred to the Fitter module. The
fitting routine relies on algorithms based on artificial intelligence software
techniques to place and route the logic into the specified EPLD. If a pin
assignment is specified, the Pi tter matches the request. If no pin assignments
are specified, the Fitter automatically finds the best fit for all pins.
Regardless of whether a fit is achieved, the Fitter generates a Utilization
Report (.RPT) that documents macrocell and pin assignments, input and
output pin names, and buried registers, as well as any unused resources.
Figure 4 shows an excerpt from an .RPT file. At the end of design
processing, the ADP generates an industry-standard JEDEC programming
file.

I Altera Corporation

Page 1071

6

I PLS-SUPREME
Rgure 4. Partial

Utilization Report
The Utilization Report
documents the EPLD
resources that have been
used.

Data Sheet

I

ALTERA Desi,n Processor Utilization Report
bevdis.rpt
1(1) FIT Uersion 7.8
7/2/98 23:56:49 39.16
••••• Desi,n i"ple"ented successfull~
Your "a"e
Your C~pan~
18/1/98
1.88

•EP338

.evera,e Dispenser Controller
Input files: bevdis.adf
ADP Options: "ini"ization
An&l!:lsis = Yes
OPTIO"S: TURBO

= 0".

= Yes,

SECURITY

Inversion Control

OFF

EP338
CLOCK
CUP FULL
COI"DROP
G"D
RESET
G"D
E"ABLE
G"D
G"D
G"D

-:1
-:2
-:3
-:4
-:5
-:6
-:7
-:8
-:9
-:18

28:19:18:17:16:15:14:13:12:11: -

UCC
G"D
G"D
G"D
G"D
G"D
DROPCUP
STROBE
POURDR"K
G"D

Simulation

Included in the PLS-SUPREME package is a Functional Simulator (FSIM),
which is a convenient and easy-ta-use tool for testing design logic before it
is committed to silicon. FSIM uses the JEDEC file generated by the ADP.
Input logic values with state tables, vector patterns, or predefined patterns
may be defined with any standard text editor. Design debugging is aided
with the BREAJC, FORCE, SAVE, and RESTORE commands; buried nodes
can also be accessed. Interactive simulation results are displayed either
graphically with the Virtual Logic Analyzer (VLA) or in a tabular format.
The results may be printed in either format with an Epson or compatible
printer. Figure 5 shows the output of the VLA. The designer can simulate
interactively from the keyboard, or an optional Command File may be
generated to perform batch-mode simulation.

Programming

LogicMap II programming software is included in the PLS-SUPREME
package. The software uses the Altera Super Adaptive Programming
(ASAP) algorithm, which significantly reduces the time required to program
an EPLD. LogicMap II uses the JEDEC file created by A +PLUS and Altera
programming hardware to program the target EPLD. LogicMap II also
reads and produces JEDEC files from programmed EPLDs and verifies
programmed devices.

I Page 108

Altera Corporation

I

I DatsShHt

I

PLS-SUPREME

Figure 5. Virtual Logic Analyzer Output
The VLA provides an interactive display of
simulation results.
-'~

__________________
~

~'-'L

______

I

____~!I~__________~r-L

........... ··-5-·· ........................................................... .
R"..,e: 5 to 48
11,...,: 'beudis.JED
Cycle: 4
Signal,,: 8

PLS·
SUPREME
Contents

o

o
Ordering
Information

1

Altera Corporation

Floppy disks containing all programs and files for A+PLUS software
for both PC-AT, PS/2, and compatible com puters
Altera Design Processor
LogiCaps schematic capture
Functional Simulator (FSIM)
LogicMapII
Documentation

PLS-SUPREME

Page 1091

Ir:I

Y

Notes:

Contents
I October 1990
Section 3

EPM5000-Series MAX EPLDs
EPM5000-Series MAX EPLDs: The Industry-Standard
Programmable Logic Family ......................................................... 113
EPM5016 to EPM5192: High-Speed, High-Density MAX EPLDs ............ 115
PLS-MAX: MAX+PLUS Programmable Logic Software ........................... 163

IA/tera Corporation

Page 111 I

EPM5000-Series
MAX EPLDs

The Complete Industry-Standard
Programmable Logic Family

.A. EPM5192
tpo = 25 ns

384-

.A. EPM5128
tpo= 25 ns

256-

DENSITY

.A. EPM5130
tpo = 25 ns

(Flip-Flops &
Latches)

128 -

.A. EPM5064 tpo = 25 ns
.A. EPM5032 tpo=15ns

64-

.A. EPM5016 tpo=15ns

do

Jo

do

-

USER 1/0

o The Altera EPM5000-series Multiple Array

o

EPMSOOO-series EPLDs provide lS-ns
combinatorial delays, counter frequencies
up to 100 MHz, pipelined data rates up to
100 MHz, and high-complexity designs
with true system-clock rates up to 66 MHz.

o

A full selection of packages is provided,
including DIP, SOIC, J-Iead, PCA, and QFP
formats in windowed ceramic and plastic
one-time-programmable versions.

o

Easily converts to custom-masked silicon
for very-high-volume production.
MAX EPLDs are supported with
MAX+PLUS PC- and workstation-based
design tools offering hierarchical
schema tic and Altera Hard ware
Description Language (AHDL) entry
methods, an efficient logic synthesis-based
compiler, and full timing simulator.

MatriX (MAX) EPLDs offers the industrys
most comprehensive family of programmable logic building blocks.

o Advanced MAX architecture provides the
speed, ease of use, and familiarity of PAL
devices with the density of programmable
gate arrays.

o
o

Modular family structure solves design
tasks from fast 20-pin address decoders to
lOO-pin LSI custom peripherals.
Non-volatile, reprogram mabie EPROM
technology aids prototype development.

o

o High sequential logic capacity provides
up to 384 registers plus latches.

o

Up to 66 product terms per output ensure
efficient design of complex state machines.

o

Exactly emulates all popular 7400-series
functions to facilitate conversion of
existing CMOS and TIL designs.

o

o

Logic compilation and automatic placeand-route of 600- to 7,SOO-gate designs is
performed in minutes.

Easily integrates multiple-package PAL
and PLA designs.

o

EDIF industry-standard workstation and
third-party CAE tool interfaces are
available.

IAltera Corporation

Page 113

EPM5016 to EPM5192
High-Speed, High-OenSitYJ
MAX EPLOs

I October 1990, ver. 1
Features

Data Sheet I

o
o
o
o
o
o

Com plete family of CMOS EPLDs solves design tasks ranging from fast
20-pin address decoders to loa-pin LSI custom peripherals.
The advanced MAX architecture combines the speed, ease of use, and
familiarity of PAL devices with the density of programmable gate
arrays.
EP5000-series EPLDs provide 15-ns combinatorial delays, counter
frequencies up to 100 MHz, pipelined data rates of 100 MHz, and highcomplexity designs with true system clock rates up to 66 MHz.
Available in a wide variety of packages, including DIP, SOIC, J-Lead,
PCA, and QFP formats in windowed ceramic and plastic one-timeprogrammable versions.
MAX+PLUS PC- and workstation-based development tools compile
large designs in minutes.
Industry-standard EDIF interfaces to workstation and third-party CAE
tools are available.

Figure 1 shows the EPM5000-series modular architecture.
Figure 1. EPM500O-Series Modular Architecture
EPM5192

Macrocells
Maximum Fip-Fiops
Maximum latches
Pins

I A/tera Corporation

16
21
32
20

32
42

64
28

64
84
128
44

128
168
256
100168

192
252
384

100'84

Page

1151

m

I EPM5016 to EPM5192: High-Speed, High-Density MAX EPLDs
Family

•

Highlight~

•

•

•

•

General
Description

Data Sheet

I

Multiple Array MatriX (MAX) architedure solves speed, density, and
design flexibility prob lems
Advanced macrocell array provides registered, combinatorial, or
flow-through latch operation.
Expander product-term array automatically provides additional
combinatorial or registered logic.
Decoupled I/O block with dual feedback on I/O pins allows
flexible pin utilization.
Programmable Interconnect Array provides automatic 100%
routing in devices with multiple LABs.
Each macrocell supports synchronous or asynchronous operation
of every macrocell, using single or multiple clocks per device.
EPM5000-Series Performance
Pipelined data rates up to 100 MHz
Counters as fast as 100 MHz
tpD performance from 15 ns to 25 ns
Advanced O.8-micron CMOS EPROM technology
EPMSOOO-Series Logic Density
16- to 192-macrocell devices
20- to 100-pin packages
32 to 384 flip-flops and latches
More than 32 product terms on a single macrocell
Product-term expansion on any data or control path
MAX+PLUS Design Tools
Design entry via unified, hierarchical schema tic capture and Altera
Hardware Description Language (AHDL)
Fast, automatic design processing with logic synthesis
Automatic device fitting, no hand editing needed
Hardware and software design verifica tion tools
Com piles a 16-bit counter in 34 seconds on a 16-MHz 386 com puter
EDIF interfaces to MAX+PLUS provide paths to Dazix, Valid Logic
Systems, Mentor Graphics, and other workstation-based CAE tools.

EPM5000-series Erasable Programmable Logic Devices (EPLDs) represent a
revolutionary step in programmable logic: they combine innovative
architecture and state-of-the-art process to offer optimum performance,
logic density, flexibility, and the highest speeds and densities available in
general-purpose reprogram mabIe logic. These EPLDs are high-speed, highdensity replacements for SSI and MSI TTL and CMOS packages and
conventional PLDs. For example, an EPM5192 replaces over 100 7400-series
SSI and MSI TIL and CMOS packages, integrating complete subsystems
into a single package, saving board area, and reducing power consumption.
These MAX EPLDs range in density from 16 to 192 macrocells. They are
divided into two groups: higher-speed MAX EPLDs (EPM5016 and
EPM5032) and higher-density MAX EPLDs (EPM5064, EPM5128, EPM5130,
and EPM5192). The higher-speed MAX EPLDs achieve system clock
frequencies of 66 MHz, and are capable of counter frequencies of 100 MHz.

I Page 116

Altera Corporation

I

I Data Sheet

EPM5016 to EPM5192: High-Speed, High-Density MAX EPLDs

1

Logic Array Blocks The EPMS016 and EPMS032 MAX EPLDs have a single
Logic Array Block (LAB). The EPMS064, EPMS128, EPM5130, and EPM5192
MAX EPLDs contain multiple LABs. Each LAB contains a macrocell array,
an expander product-term array, and a decoupled I/O block. Expander
product terms (expanders) are unallocated, inverted product terms that can
be used and shared by all macrocells in the LAB to create combinatorial and
registered logic. Thus, expressions requiring up to 66 product terms can be
implemented in a single macrocell. Signals in the higher-density devices are
routed between multiple LABs by a Programmable Interconnect Array
(PIA) that ensures 100% routability. This multiple array architecture enables
EPMSOOO-series EPLDs to offer the speed of smaller arrays with the
integration density of larger arrays.
Modular Architecture The modular architecture of MAX EPLDs provides
integration solutions over a wide range of logic densities. Migration from
one type of device to another is easy. For example, the EPMS128 and
EPMSl30 EPLDs have the same logic capacity, but have packages optimized
to handle different I/O requirements. Over the entire family, a wide range
of packaging options for both through-hole and surface-mount applications
is available. Plastic one-time-programmable (OTP) packages are available
for economical volume production.

Logic Design Entry Logic designs are created and programmed into
EPMSOOO-series EPLDs with the MAX+PLUS Development System.
MAX+PLUS is a complete CAE system offering hierarchical design entry
tools, automatic design compilation and fitting, timing simulation, and
device programming. The MAX+PLUS Compiler features advanced logic
synthesis algorithms, allowing designs to be entered in a variety of highlevel formats while ensuring the most efficient use of EPLD resources. The
combination of a flexible architecture and advanced CAE tools ensures
rapid design cycles so that a design may go from conception to completion
in single day. Interfaces to third-party tools are also available to allow
design entry and logic simulation on a variety of workstation platforms.

Functional
Description

EPMSOOO-series EPLDs use CMOS EPROM cells to configure logic functions
within the devices. MAX architecture is user-configurable to accommodate
a variety of independent logic functions, and the EPLDs can be erased for
quick and efficient itera tions during design development and debug cycles.

Logic Array
Block

EPMSOOO-series EPLDs contain from 1 to 12 Logic Array Blocks. Each LAB,
shown in Figure 2, consists of a macrocell array, an expander product-term
array, and an I/O control block. (The number of macrocells and expanders
in the arrays varies with each device.) Macrocells are the primary resource
for logic implementation, but if needed, expanders can be used to
supplement the capabilities of any macrocell. The expander product-term
array consists of a group of unallocated, inverted product terms. Flexible
macrocells and allocatable expanders facilitate variable product-term designs

1

Altera Corporation

Page 1171

II

I EPM5016 to EPM5192: High-Speed, High-Density MAX EPLDs

Data Sheet I

Figure 2. Logic Array Block
The LAB consists of a
maaocell array, an
expander product-term
array, and a decoupled
IIO b/ocl<. The flexibility
of the LAB ensures
high speeds and
efficient device
utilization.

110 Pins

~
~

g:g

••
•

~

without the waste associated with fixed product-term architectures. Thus,
PAL or PLA devices are easily integrated into MAX EPLDs. The outputs of
the macrocells feed the decoupled I/O block, which consists of a group of
programmable tri-state buffers and I/O pins. In the EPM5064, EPM5128,
EPM5130, and EPM5192, multiple LABs are connected by a Programmable
Interconnect Array (PIA).

Macrocells

The EPM5000-series macrocell, shown in Figure 3, consists of a
programmable logic array and an independently configurable register. This
register may be programmed for 0, T, JK, or SR operation; or as a flowthrough latch; or bypassed for purely combinatorial operation.
Combinatorial logic is implemented in the programmable logic array, which
consists of three product terms ORed together that feed one input of an XOR
gate. The second input to the XOR gate is also controlled by a product term
that makes it possible to implement active-high or active-low logic. The XOR
gate is also used for complex XOR arithmetic logic functions and for
De Morgan's inversion to reduce the number of product terms. The output
of the XOR gate feeds the programmable register, or bypasses it for purely
combinatorial operation. The logic array ensures high ,speed while
eliminating inefficient, unused product terms. Also, expanders can be
allocated to enhance the capability of the logic array.
Additional product terms, called secondary product terms, are used for
Output Enable, Preset, Clear, and Clock lOgiC. Preset and Clear product
terms drive the active-low asynchronous Preset and asynchronous Clear
inputs to the configurable flip-flop. The Clock product term allows each
register to have an independent Clock and supports positive- and negative-

I Page 118

A/tera Corporation

I

I DstsSheet

EPM5016 to EPM5192: High-Speed, High-Density MAX EPLDs I

Figure 3. EPMSOOO-Series Macrocell
Output Enable

System Clock

Preset

~
Array Clock

Programmable
Register

~":~~
I ~t-~':lli- I

to VO
Control
Block

Clear

~
Macrocell and 110 Feedbacks

<
y,

y,

11

~

ii

8-20
Programmable
32-64
Dedicated Interconnect Expander
Inputs
Signals Product Terms

Note: One
system clock
per LAB

o
o
o
o

Programmable flip-flop (0, T, JK, SR)
Registered or flow-through latch operation
Programmable Clock
Asynchronous Preset and Clear

edge-triggered operation. Macrocells that drive an output pin may use the
Output Enable product term to control the active-high tri-state buffer in the
I/O control block. These secondary product terms allow 7400-series TIL
functions to be emulated exactly.
The EPM5000-series macrocell configurability makes it possible to efficiently
integrate complete subsystems into a single device. All macrocell outputs
are globally routed within an LAB and also feed the PIA to provide efficient
routing of signal-intensive designs.

Clock
Options

Each LAB has two clocking modes: asynchronous and synchronous. Ouring
asynchronous clocking, each flip-flop is clocked by a product term. Thus,
any input or internal logic may be used as a clock. Systems that require
multiple clocks are easily integrated into EPM5000-series EPLDs.
Asynchronous clocking also allows each flip-flop to be configured for
positive- or negative- edge-triggered operation, giving the rnacrocell a high
degree of flexibili ty.
Synchronous clocking is provided by a dedicated system clock (eLX). This
direct connection provides enhanced clock-to-output delay times. Since
each LAB has one synchronous clock, all flip-flop clocks within it are
positive-edge-triggered from the CLX pin. If the CLX pin is not used as a
system clock, it may be used as a dedicated input.

IAltera Corporation

Page 119

I

I EPMS016 to EPM5192: High-Speed, High-Density MAX EPLDs

Expander
Product
Terms

Data Sheet

I

The expander product-term array (Figure 4) contains unallocated, inverted
product terms that enhance the macrocell array. Expanders can be used and
shared by all product terms in the LAB. Wherever extra logic is needed
(including register control functions), expanders can be used to implement
the logic. These expanders provide the flexibility to implement registerintensive and product-term-intensive designs for MAX EPLDs.

Figure 4. Expander Product Terms

to Macrocell Array and
Expander Product Term Array

Expander product terms are
unallocated logic that can be
used and shared by all
maaocells in an LAB.
Sharing allows efficient
integration of complex
combinatorial functions.

Macrocell and VO

Feedbacks

8-20
Programmable
32-64
Dedicated Interconnect Expander
Inputs
Signals Product Terms

Expanders are fed by all signals in the LAB. One expander may feed all
macrocells in the LAB or multiple product terms in the same macrocell.
Since expanders also feed the secondary product terms of each macrocell,
complex logic functions can be implemented without using another
macrocell. Expanders can be cross-coupled to build additional flip-flops or
latches.

1/0 Control
Block

Each LAB has an I/O control block (Figure 5) that consists of a userconfigurable I/O control function for each I/O pin. The I/O control block is
fed by the macrocell array. The tri-state buffer is controlled by a dedicated
macrocell product term, and drives the I/O pad.
Each MAX EPLD has dual feedback-one feedback path before and one
after the tri-state buffer- for every I/O pin. The tri-state buffer decouples
the I/O pins from the macrocells so that all registers within the LAB can be
"buried." Thus, I/O pins can be configured as dedicated input, output,
or bidirectional pins. In multiple-LAB MAX devices, I/O pins feed the PIA.

I Page 120

A/tera Corporation

I

I Dlltll Sheet

EPM5016 to EPM5192: High-Speed, High-Density MAX EPLDs

I

Figure 5. VO Control Block
The decoopled 110
control block features
dual feedback to
maximize use of device
pins.

I/O Pin

from Macrocell Arra

Macrocell
Feedback

110 Pin
Feedback

Programmable
Interconnect
Array

The higher-density EPMSOOO-series devices (EPMS064, EPMS128, EPMSl30,
and EPMS192) use a Programmable Interconnect Array (PIA) to route
signals between the various LABs. The PIA routes only the signals required
for implementing logic in an LAB, and is fed by all macrocell feedbacks and
all I/O pin feedbacks. Unlike channel routing in masked or programmable
gate arrays-where routing delays are variable and path-dependent-the
PIA has a fixed delay. Because the PIA eliminates skew between signals,
timing performance is easy to predict.

Timing
Model

Timing within EPMSOOO-series EPLDs is easily determined with MAX +PLUS
software or with the models shown in Figure 6. EPMSOOO-series EPLDs ha ve
fixed internal delays, that allow the user to determine the worst-case timing
delays for any design. For complete timing information, MAX+PLUS
software provides a timing simulator, a delay predictor~ and a detailed
timing analyzer.

I A/tera Corporation

Page 121

I

3

I EPM5016 to EPM5192: High-Speed, High-Density MAX EPLDs
Figure 6. Timing Models

Data Sheet

I

Multiple-LAB EPLDs

Design performance can be
predicted with these timing
models and the device
performance specifications.

Expander

INPUT
Input
Delay
tiN

r

--1[tI~~~}=~L~~~i~cA~rr~~~
Logic
Control Delay
tLItC

Array
Delay
tLItD

Output
Delay
tI/D
toal8
tLltTCH

110 Pin

too
txz

tzx

PIA
Delay

t Pl"

Single-LAB EPLDs

INPUT
Output
Delay
tI/D
toal8
tLltTCH

110 Pin

too
txz
tzx

The timing models shown in Figure 6 may be used together with the internal
timing parameters for a particular EPLD to derive timing information.
External timing parameters are derived from a sum of internal parameters
and represent pin-to-pin timing delays. Figure 7 shows the internal timing
waveforms for these devices. Refer to Application Brief 75 (EPM5000·Series
MAX EPLD Timing) in this data book for further information.

Design
Security

I Page 122

MAX EPLDs contain a programmable Security Bit that controls access to the
data programmed into the device. If this feature is used, a proprietary
design implemented in the device cannot be copied or retrieved. This
feature provides a high level of design security, since programmed data
within EPROM cells is invisible. The Security Bit that controls this function,
as well as all other program data, is reset by erasing the EPLD.
Altera Corporation

I

Dsts Sheet

EPM5016 to EPM5192: High-Speed, High-Density MAX EPLDs

Figure 7. Switching
Waveforms

Input Mode
i-tIN-i

In multiple LAB EPLDs, 110
pins used as inputs can
traverse the PIA

Input Pin

-----.*~---~i-!

_________________

i--tIO-...J

I/O Pin

-----.*~--___t.----------------­

i--tEXP~
Expander Array - - - - - - -...... :r----;..·- - - - - - - - - - - - -

tR& tF< 3 ns.

Inputs are driven at 3 V for a
logic high and 0 V for a logic
low. All timing characteristics
are measured at 1.5 V.

Delay
Logic Array
Input

X'-----+1-----------l-t/.AC, tLAD---!
-----------""""\v.:AIo..._ _ _ _ _......;.. _ _ _ _ _ __
tCOMB ~

~

L09i~~~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---JX~+-..,..----~too~
Output Pin _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
.

---li,.----

Asynchronous Clock Mode
tF~ j...

tR ~ i--tACH-l i--tACL-l

Clock Pin
Clock into
Logic Array

---V

'\

V
; V,...---""""\\Io..-----II

i+tlN ~

;-tiC

Clock from
Logic Array

tsu

.1.

----~*

.

tRD. tLATCH~

Register Output to
local LAB Log ic Array

tH

11

*~----~~~---------:"tCLR, tpRE ~

i+-tFD-1

~tFD

--------------~.--~:~--------~q---.

-------------~~~-------~~

_________________________

+:

:"tPIA

Register Output
to another LAB

\~----

---!

------------~V-------~\~-----I
!.

Data from
Logic Array

\\.-j- - - -

~x.~------------

System Clock Mode
System
Clock Pin

!+\'-1_ _ _ ___

System Clock
at Register

\~---

tF

~

Data from
Logic Array
Output Mode
Clock from
Logic Array

L~~~~~;

__--II

===x=X-=+r-=+i

CJ
: t xz

:----:

Output Pin

IAltera Corporation

\~---

I

\ ' - -_ _ _--J

• tRD • too •

t.·=============j..

. _

Xr - - - - - - : tzx .
~

State
/-fgh Impedance

~,...----

:\-._ _ __

Psge 1231

I

I EPM5016 to EPM5192: High-Speed, High-Density MAX EPLDs

Data Sheet

I

MAX EPLDs are fully functionally tested and guaranteed. Complete testing
of each programmable EPROM bit and all internal logic elements ensures
100% programming yield. AC test measurements are performed under the
conditions shown in Figure 8.
._---Vee

Figure 8. AC Test Conditions Power supply transients can affect AC
measurements. Simultaneous transitions of
multiple outputs should be avoided for
accurate measurement. Threshold tests
should not be performed under AC conditions.
Large-amplitude, fast-ground current
transients normally occur as the device
outputs discharge the load capacitances.
When these transients flow through the
parasitic inductance between the device
ground pin and the test system ground, it can
create significant reductions in observable
input noise immunity.
Note: Numbers in parentheses are for the
EPM5016.

to Test

Device input
rise and fall
times < 3 ns

Test programs may be used and then erased during early stages of the
production flow. This facility to use application-independent, generalpurpose tests is called generic testing and is unique among user-configurable
logic devices. EPLDs also contain on-board logic test circuitry to allow
verification of function and AC specifications once they are packaged in
windowless packages.

MAX+PLUS
Development
System

The MAX+PLUS Development System is a unified CAE system for
integrating designs into EPMSOOO-series MAX EPLDs. Designs can be
entered as logic schematics with the Graphic Editor or as state machines,
truth tables, and Boolean equations with the Altera Hardware Description
Language (AHDL). Logic synthesis and minimization optimize the logic of
a design. Design verification and timing analysis are performed with the
Simulator or the delay prediction feature. Errors in a design are automatically
located and highlighted in the schematic or text design file. Hosted on IBM
PS/2, PC-AT, or compatible machines, and workstations (e.g., Apollo, Sun,
IBM), MAX+PLUS gives the designer the tools to quickly and efficiently
create complex logic designs. Further details about the MAX+PLUS
Development System are available in the PLS-MAX Data Sheet.

Device
Programming

EPMSOOO-series EPLDs may be programmed on an IBM PS/2, PC-AT or
com patible com puter with an Altera Logic Programmer card, the PLE3-12A
Master Programming Unit, and an appropriate device adapter. These items
are included in the complete PLDS-MAX Development System or may be
purchased separately. EPMSOOO-series EPLDs may also be programmed
with third-party hardware (see the Third-Party Development & Programming
Support Data Sheet in this data book). Contact Altera or your programming
equipment manufacturer for more information.

IPage 124

A/tera Corporation

I

EPM5016I
o

Features

o
o
o
o
o
o
o
General
Description

Fast 20-pin MAX single-LAB EPLD
Combinatorial speeds with tpo = 15 ns
Counter frequencies up to 100 MHz
Pipelined data rates up to 100 MHz
16 individually configurable macrocells
32 expander product terms (expanders) that allow 34 product terms in
a single macrocell
Up to 21 flip-flops or 32 latches
Up to 10 input latches that can be constructed with cross-coupled
expanders
24-mA output drivers to allow direct interfacing to system buses
Programmable I/O architecture allowing up to 16 inputs and 8 outputs
Available in 20-pin windowed ceramic or plastic DIP, plastic J-Iead
(PLCC), and plastic 3OO-mil SOIC packages

The Altera EPM5016 (Figure 9) is a Multiple Array MatriX (MAX) CMOS
EPLD optimized for speed. It can integrate multiple 551 and MSI TTL and
74HC devices. In addition, it can replace any 20-pin PAL or PLA device with
logic left over for further integration.

Figure 9. EPM5016 Pin-Out Diagrams
Package outlines not drawn to scale.

INPUT

INPUT
INPUTICLK

g g
INPUT
INPUTIClK
110
110

110

VO

INPUT

INPUT

GND
1.0
110
INPUT
INPUT

GM>
1.0
1.0

INPUT
INPUT

INPUT

INPUT
INPUTICLK

INPUT

110

INPUT
0
0

0

>

z

INPUT
110

110

g

1.0
110

vee

Altera Corporation

z
(!j

INPUT

g

1

>

c

INPUT
INPUT

vee

sOle

0
0

110

vee

vee

GND

GND

110

110

110

110

INPUT

INPUT

INPUT

INPUT

g g

(!j

J-Lead

DIP

Page 1251

EJ

I EPM5016

Oats Sheet

I

Figure 10 shows output drive characteristics of EPM5016 I/O pins and
typical supply current versus frequency for the EPM5016.
Figure 10. EPM5016 Output Drive Characteristics and Icc vs. Frequency
180

200
IOL~

_ __

ci

....>.

<-

.§.
C
~

:s

0
~

a.

150
160

ci..

~
120

Vee = 5.0 V
Room Temp.

;(

120

Vee = 5.0 V
Room Temp.

§.
(I)

>

90

4=1

~

80

~

0
_0

0

60

0

30

100 Hz 1 K~z

Vo Output Voltage (V)

10-KHz 100 KHz 1 MHz 10 MHz 100 MHz

Maximum Frequency

The EPM5016, shown in Figure 11, contains 16 macrocells. The expander
product-term array for the EPM5016 contains 32 expanders. The I/O
control block contains 8 bidirectionalI/O pins that can be configured for
dedicated input, dedicated output, or bidirectional operation. All I/O pins
feature dual feedback for maximum pin flexibility.

I Page 126

Altera Corporation

I

OataSheet

EPM5016

I

Rgur. 11. EPM5016 Block Diagram
The EPM5016 has 16 maaocel/s and 32 expanders.
Numbers in parentheses are br the PLCC package.
11 (16)

In~t

.7-------------------4

12 (17)

In~t

.7-------------------4

19 (4) In~t

.>------------------4

20 (5)

L->-------------------t

In~t

~-----------------c~ m~t
I
N
T
E
R
C

In~t

~----------~----_<~~ In~t

o
MACROCELL4
MACROCELL6

1 (6)

InputICLK 2 (7)

N
N
E
C
T

MACROCELL 1

9(14)
10(15)

I/O 3(8)

MACROCELL3

I/O 4 (9)

MACROCELL5

I/O 7(12)

MACROCELL7

110 8(13)

MACROCELL 10

MACROCELL9

I/O 13(18)

MACROCELL 12

MACROCELL 11

I/O 14(19)

MACROCELL 14

MACROCELL 13

I/O 17(2)

MACROCELL 16

MACROCELL 15

I/O 18(3)

MACROCELL8

11

Expander Product Term Array (32)

IAltera Corporation

Page 1271

I EPM5016

Data Sheet /

Absolute Maximum Ratings

Symbol

Note: See Operating Requirements for EPLDs in this data book.

Parameter

Conditions

Min

Max

vee

Su~~I~ vOltage

With respect to GND

-2.0

7.0

Vpp

Pr~ramming su~~I~ vOltage

See Note (1)

-2.0

13.5

II

DC input voltage

I VI

I DC V cc or GND current

MAX

I

_'....::O:::::;uT..!....-_ _1 DC output current, per pin

I Storage temperature

I

-25

-65
T AMB
1 Ambient temperature
1 Under bias
I-T---'J=---li-J-u-nc-tio-n-te-m-'-p-er-at-ur-e-----I_u_n_d_er_b_ia_s_ _ _ _ _,_ _ __

I

I

Symbol

I

Parameter

mA
mW

+150

Conditions

Min

I

Max

I_u_n_it_l

V--"c;..=.e_ _ _1 Su~ply vOltage
1
4.75 (4.5)
5.25 (5.5) I_ _v~_!
VI
-,-np.......u'-'tv'-o-,ta-g-"'e-------I--------·!I--..:..:..:...~0J...;..;..;;L-1
Vee
1
V
1

I

J

V-':'o--- Output vOltage

1-1

T_A~_ _ _ _O; .J;pe;. . ; . ;. ; ;ra~tin.;.;i!g~te:;. ;.;m.;J.:pe. .:. ;r. .:. ;at:. ;:;.ur~e_ _ _ _ 1 For commercial use

:-1

T_A:.:.-_ _ _ _O~pe_ra_tin.....g_te_m......pe_r_at_ur_e_ _ _ _ 1 For industrial use

:-1

ITC

I For military use

Case temperature

tF

0

I

Vee

1--v--

I

0

1

+70

I_ _

I

--40

I

+85

1_ _

I

-55

I

+125

I

t....:..:R:......-_ _ _'n...l;.p...;...ut_ris_e_ti_me_ _ _ _ _ _ I .

1-1

I

25
1000

See Note (2)

1-1

1

I'.

Input fall time

1

o....;;c~_!
o_c__

I

1

°C

100

n-s - ;
II·.--

100

ns

DCOperatingConditions See Notes (2), (3), and (4)

Symbol

I

Parameter

Conditions

High-level input voltage

1 VIH

I LOW-level input voltage

I VIL

I V--'o=H"'--_ _
i-

1

High-level TTL output VOltage

1:-V-.,;o=L'---_ _1 Low-level output voltage

~I

I
I I OH = -12 mA DC
I

--I Vee supply current (standby)

i-'...!:c=e-1

I

Vee supply current

Unitl

Max

2.0

~

Vee +0.3

I

0.8

I

_2_.4__ •_ _ _ _ _ _ _1
1

-10
-40
1

I

I-V--',=-=-V-.=.c=-o-r-G-N-D-- - - - - --8-0e
V, = Vee or GND

v
v

:;: I ~

I OL = 24 mA DC

I 'nput leakage current
I V I = Vee or GND
'-.!.o-z---I-T-":ri--s-ta-te-o-":ut:!...p-ut-o-ff--st-at-e-cu-rr-en-t-I V 0 = Vee or GND

:-1

Typ

-{).3

1II

I

1

+135

1

Recommended Operating Conditions

V

mA

+150

-65

I No bias

I

-H

7.0
200

I

1p o l Power dissipation
1 T STG

-2.0

Unit

85

+40
110(150)
115 (175)

II

mllAA

I
I

I
II

mA

No load, f = 1.0 MHz
See Note (5)

Capacitance

1_ _
Sy_m_b_O_I_il_____p_a_ra_m_e_te_r____I_ _ _C_o_n_di_tio_n_s___,__M_in__i__M_a_x___U_ni_t_!

-C--=,N---il-_'n:.....pu_t_ca-'-p_aCl_·ta_n_ce_ _ _ _ _ _I_V.....:;IN:.!.-=_0_V,_f_=_1.0_M_Hz_ _i_ _ _--i_ _ _
10___-,p,-F__

I

._C_O=U=-:T_ _ _!I_O.. :. ;u; ;,:;tPL;. ;u. .:. ;tc;;;,:;a,J;.,pa.;;,;c:.,;.ita=n...:..;ce=--_ _ _ _ 1 VOUT =0 V, f = 1.0 MHz

I Page 128

1

12

pF

A/tera Corporation

I

I Data Sheet

EPM5016

AC Operating Conditions

See Note (4)

External Timing Parameters
Symbol

I t PDl

I

I t su

Parameter

1 C1

VO input to non-reg. output

1

I Setup time
Hold time

ItH
t ASU

C1

0

1

Asynchronous setup time

J

-

I

15
9

5

Asynchronous hold t i m e '

I EP~~016
I

,

5'

Max

MIn

15

6

I C1 =35 pF

Max

Min

= 35 pF
= 35 pF

Clock to output delay

~1

, t AH

EPMS016-1

I Conditions

1 Input to non-registered output
1

I

MIn

1_17_1_ _

Max

Unit

20

ns

I:I~'I'__:_1~'~~~_3~'~~~
'7'

'8

1

1

'--I

ns

I

ns

1

ns

t-='c'::":H-~li-C-IOC:'-"'k-h-i9-ht-im-e----'li----~--f6l-~1~8-i1--iI~n-s-i

!-I

I t CL

I Clock low time

1 _ _ _ _1

5

,

4

I tACH I Asynchronous clock high time
I t ACL I Asynchronous clock low time I
I t ACOl I Asynch. clock to output delay I C1 = 35 pF

I
I

I

I

I

15

I
I

I'

10

I'

6'

, t CHT
I f CHT

1
1

Minimum clock period
Internal maximum frequency

I

I t ACHT

1

Minimum asynch. clock period

I See Note (6) I

I f ACHT

I Max. intemal asynch. frequency I See Note (6)

1 100

1 f MAX

I Max. frequency; pipelined data I

1 100 I

I

100

,'.'

6

1

'5'
7

83.3

I

I

I

I
I

17

I

I

20

I'

12

" 62.5

I,

16

'9'

ns
1

I ns I
ns I
II MHz
,

1

'16

I~

, 83.3 1

I 62.5

1

1 MHz 1

, 83.3

1 62.5

1

1 MHz I

'10'

1

8

'7

'12

1

For information on internal timing parameters, refer to App. Brief 75 (EPMSOOO-Series MAX EPLD Timing).

I Internal ~ming Parameters

I Symbol I

I

_ _ _ _ EPM~16-1
I Conditions Min Max

I

Parameter

I

I EPM5916-2 I

I. t zx

, t xz

I Output buffer disable delay

, t EXP

I t LAD
, t LAC

, t OD

1

I

t su
t LA TCH
t RD
t COMB

tH
t

/C

t,CS

t FD
t PRE

,

=

I'

Register setup time
Flow-through latch delay

1 C1 = 5 pF

I

I Register hold time
I Clock delay
I System clock delay
I Feedback delay

I Register presettime

I

I

7

I'"

I

,

I

"

I

2

,
"

'5'

'5'

ns

I
I

'8'

'10

ns

,

I
I

I
I
I

5

7
5

1

,

6

I

1

5

I

I
I

I

6

I

0'

I

I

7'

I

5

9
7

I

I
I
I
I

ns

ns
ns

1

I

I~~

'8'

ns

I

ns

1

ns

I
I
I
1
I
1 I
. I
l' ' 1 '
I '9 I I
'8

1

,

I

I

7

1

"

1

8

I 6 I
I l'

I
I

8
2

ns
ns
ns

I
I

ns

ns

,

I
I
I
,
I
I
I

I

I

I

1

I

I

1

I

I

1

I

ns

I

I

I

1

3

I

I

6

I

I

6

1 ns

1

I.____1

_t-=C.=.LR.!..--_,-'R_eg...;;;..i_ste_r_cl_ea_rt_im_e_ _ _ _

IA/tera Corporation

1

I

I Register delay

I

1 4'
5
ns ,
--\------.-----.

I
I'

I Combinatorial delay

I~

I Min I Max I Min I Max I Unit I

I Input pad and buffer delay I
I I 4 I
11/0 input pad and buffer delay 1----' ' 4 '
, Expander array d e l a y '
I I 5 I
I Logic array delay
I
"
6 I
, Logic control array delay
I
I I 4 I
buffer and pad delay
1
'4 I
I Output
II C1 35 pF .
Output buffer enable delay
. 7 I

t IN
I t 10
I

EPM.5016

I

3

I

I 6

1~_6_1~'

Page 1291

3

I EPM5016

Oats Sheet

I

Notes to tables:
(1) Minimum IX input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load
conditions.
(2) Numbers in parentheses are for military and industrial temperature-range
versions.
(3) Typical values are for TA =25° C and Vcc =5 V.
(4) Vcc = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
Vcc = 5 V ± 10%, TA = -400 C to 85° C for industrial use.
Vcc = 5 V ± 10%, Tc = -55° C to 125° C for military use.
(5) Measured with device programmed as a 16-bit counter.
(6) This parameter is measured with a positive-edge-triggered clock at the register.
For negative-edge clocking, the tACH and tACL parameters must be swapped.

Product Avai/abl/ity

I
I

Grade

Availability
EPM5016-1, EPM5016-2, EPM5016

Commercial

(0" C to 70' C)

Industrial

(-40 0 C to 850 C)

EPM5016

(-55 0 C to 1250 C)

EPM5016

I Military

Note: Only military-temperature-range EPLDs are listed above. MIL-STO-883compliant product specifica lions are provided in Military Product Drawings (MPDs),
available from Altera Marketing by calling 1 (800) SOS-EPLD. These MPDs should
be used to prepare Source Control Drawings (SCDs). See Military Products in this data
book.

I Page 130

Altera Corporation

I

EPM5032i
o

Features

o
o
o
o
o
o

Fast 28-pin DIP or J-Iead single-LAB MAX EPLD
Combinatorial speeds with tpD = 15 ns
Counter frequencies up to 76 MHz
Pipelined data rates up to 83 MHz
32 individually configurable macrocells
64 expander product terms (expanders) that allow 66 product terms on
a single macrocell
Up to 42 flip-flops or 64 latches
Up to 21 input latches that can be constructed with cross-coupled
expanders
Programmable I/O architecture allowing up to 24 inputs and 16 outputs
Available in 28-pin windowed ceramic or plastic one-timeprogrammable DIP and J-Iead packages, as well as plastic 3OO-mil SOIC
packages

The Altera EPM5032 (Figure 12) is a Multiple Array MatriX (MAX) CMOS
EPLD optimized for speed. It can integrate multiple 551 and M51 TTL and
74HC devices. In addition, it can replace multiple 20-pin PAL or PLA
devices with logic left over for further integration.

General
Description

Figure 12. EPMS032 Pin-Out Diagrams
Package outlines not drawn to scale.
0

0
0

g g g

zc;,

>

INPUT

g g

INPUT

110
3

INPUT
INPUTlCI.K

INPUT
INPUT

1.0

1.0

I.<>

1.0

1.0
1.0

I.<>
I.<>

vee

vee

GND
I.<>

GNO

1.0

1.0
1.0

1.0

I.<>

I.<>
INPUT
INPUT

1.0

INPUT
INPUT

sOle

I Altera Corporation

2

1

28

27

26

110

I/O

25

110

INPUT

24

110

23

INPUT

vee

22

INPUT

GND

21

INPUT

110

20

INPUT

INPUT
INPUTICLK

110

110

0

INPUT

EPM5032

10

110

19

12

13

g g

15

14
0
0

>

0

Z

110

16

17

18

g g g

c;,

J-Lead

110
110

110
110

110

INPUT

INPUT

INPUT

INPUT

DIP

Page 131

IJ

Data Sheet

EPAf5032

I

Figure 13 shows output drive characteristics of EPM5032I/O pins and
typical supply current versus frequency for the EPM5032.
Rgure 13. EPM5032 Output Drive Characteristics and Icc vs. Frequency
240

100

ci

.-

>.

<'

200

80

ci

§.
E

~

:;

...

~
60

()

:J

a.

S

Vee =5.0V
Room Temp.

160

<'

Vee = 5.0 V
Room Temp.

§.
Q)

~

120

0

40

<

0

J:~

80

0

40

100 MHz

Vo Output Voltage (V)

Maximum Frequency

The EPM5032, shown in Figure 14, contains 32 macrocells. The EPM5032
expander product-term array contains 64 expanders. The I/O control
block contains 16 bidirectional I/O pins that can be configured for dedicated
input, dedicated output, or bidirectional operation. All I/O pins feature
dual feedback for maximum pin flexibility.

I Page 132

Altera Corporation

I

Data Sheet

EPM5032

Rgure 14. EPM5032 Block Diagram

The EPM5032 has 32 macrocells and 64 expanders. Numbers in parsntheses are
J-/ead packages.
Input

15 (22) Input

for

1(8)

InputICLK 2 (9)

16(23) Input
27(6) Input
28 (7) Input

I
N
T
E
MACROCELL4
MACROCELL6
MACROCELL8
MACROCELL 10
MACROCELL 12

Input

13(20)

Input

14(21)

R

110 3(10)

C

110 4 (11)

0
N
N
E

C
T

110 5(12)

I!O
Control

Block

110 6(13)
I/O 9(16)
110 10(17)
I/O 11 (18)

MACROCELL14
MACROCELL 16

I/O 12(19)

MACROCELL 18

110 17(24)

MACROCELL 20

110 18(25)

MACROCELL 22

I/O 19(26)

MACROCELL 24

110 20(27)

MACROCELL 26

11023(2)

MACROCELL 28

I/O 24(3)

MACROCELL 30

I/O 25(4)

MACROCELL 32

11026(5)

Expander Product Term Array (64)

IAltera Corporation

I

Page 133

IJ

EPM5032

Data Sheet

Absolute Maximum Ratings
Symbol
I

vee

Vpp
, V,

I I MAX

I lOUT
I Po
I TSTG
, T AMB

IT

J

Note: See Operating Requirements for EPLDs in this data book.

Parameter

I

With respect to GND

Pr~rammlng su~~I~ vOltage

See Note (1)

I DC input voltage
J DC V cc or GND current
I DC oU!eut current, ~er ~in

'Vo

11
11 e

A

1.

1A
tF

I Ambient temperature

Operating temperature

I
I

I

I

+135

I

V
V
mA

-65

Min
4.75(4.5)

,

I For industrial use

I

I

I

mA
mW

1500
+150

I,:.

,

Max

I

5.25(5.5)

0

I

0

,

Vee

0

,

+70

-40

I

I For military use

Input rise time
Input fall time

-55

I'.

I

V ee

+85

I

+125

',.

110000

See Notes (2), (3), (4)

Parameter

,--Co-n-dl-tlo-n-s--"--M-in-'-T-YP-

,-H-j9-h--I-ev-e-1in-p-ut-vo-I-ta-ge----'

I YOH

High-level TIL output voltage
LOW-level output voltage
Input leakage current
Tri-state output off-state current
Vee supply current (standby)
Vee supply current

V

°C

+150

, For commercial use

I Case temperature

LOW-level input voltage

lee3

7.0
300

I

~I

Under bias

I
I

, Y Il

I I,
Iloz
II ee1

7.0
13.5

Unit

-65

I

,--c-O-nd-iti-'O-ns---,

. Operating temperature

II

I
I,

I

l_o_u......
tP_ut_v_o_lta......g.....;e_ _ _ _ _ _ II_ _ _ _ _ _ _ _1

I

Max

See Note (2)

I Input voltage

I Symbol I
I Y Ol

-2.0

I

I Under bias

I

Junction temperature

DC Operating Conditions

I YI H

-2.0

I

No bias

~I Suppl~voltage

, TA

-2.0

-25

dissipation

Recommended Operating Conditions
~I
Parameter

I VI

I
I
I
I

I

. Storage temperature

I

Min

Conditions

Supply vol_

I Power

I

2.0

I

Max

,

Unit

I===v==:

I

V

'_ _V_ _:

I__o_c_ _,
I__o.....;c~_
I

°C

I--n-sns

I

-0.3

0.8

I

1:_I-=O~H_=_-4_m_A_DC
_ _ _i-_2_.4__i_ _ _ _ _ _ _ _

I I Ol = 8 mA DC
I V I = V cc or GND

I V 0 = Vee or GND
I V I = Vee or GND ,
V I = V cc or GND

Unit

-V-ee-+0.3 -!,--V---'

+10

-40

+40

I

120
125

I

V_--l

II,.._ _

0.45
-10

V

V

I

I

).LA
).LA

150 (200)

mA

155 (225)

mA

I

No load, f = 1.0 MHz

See Note (5)

Capacitance

I

Symbol

1_ _ _ _p_a_ra_m_e_te_r____ 1

I

I

Conditions

, c IN
Input capacitance
Y,N = 0 V, f = 1.0 MHz
,!-·-c:. ;:;. O;. :. . U;:. ;-T:. -_
.- -_-_-,-O
......u-tP-ut--'ca'-p-a-cit-a-nce-----, VOUT = 0 V, f = 1.0 MHz

I Page 134

Min

Max

Unit

10

pF

12

pF

Altera Corporation

I

I Data Sheet

EPM5032

AC Operating Conditions

See Note (4)

I External Timing Parameters

I Symbol I

Parameter

I Input to non-registered output

, t PD1

, Setup time

I t su
ItH

I Hold time

, t C01

1

1:::

Clocktooutputdelay

I~:~:~:ehOld time

, C1 = 35 pF

15

, C1 = 35 pF

15

I
1

0

I
7'

-A-S-yn-Ch-ro-n-ou-s-CI-Ock-hi-9h-t-im-e-il-----'

6

I

_A---,SY,--nC_h_ro_no_us_C_IOC_k_lo_w_tim_e_.il _ _ _ _ _I,'
Asynch. clock to output delay
'C1 = 35 pF

7

'I

I

Minimum clock period

I

'_f.--..:C=N:..:...T__ i_ln_te_rn_a_1m_ax_i_m_Um_f_req....:.u_e_nc....:.,.y__il_ _ _ _ _

I

I 76.9 I

'_t---!A=C=NT-=--+'_M_in_.a_s.:..-yn_Ch_._CIOC_k.:..-pe_ri_od_ _ _il_ _S_ee_N_o_te...;..(6-=-~_,

25

25

I~I

,

ns

,

1---;-'

15

I

0

,

'12'

I

7

I

15

1

9

I,

13

I

I

'13

I Max. internal asynch. frequency , See Note (6) ,
l=f:M:A:X:=~I:~=M=a=x.=fre=q=ue=n=ct=:P=ipe==lin=ed=d=a=ta=~:I~========1

I f ACNT

,

,

1

ns

,

'-1_12_1_ _ 1_1_5_1~1
'9

I tACH

I t CNT

-,-

~

20

'ns

1----IR+=I
~ l=l ~ I
1-, 7'
181
;1 _ _ _ _ _ '

6

t ACL
t AC01

10

1

r-...;;- ~MaX
~unitl
1

12

C1 =35pF

EPMS032

20

0

-C-IOC-k-IO....::..w-ti-me-----il-

I

Min

9

, t CL

I

EPMS032-2

Max

Min

1

-.;1-_As...;..y_nc_hr_on_o_us_s_etu...;.p_ti_m_e_ _

'_t....:.A=s=-u

EPMS032-1

I Conditions

I 110 input to non-reg. output

I t PD2

I

1

9'

20

I,

11

16

I

I~:

1 ns

I

16

1

I
,

'ns'

II'

25

II:

I

20

I

I~I__I~I__I

I

1

nnss
ns
MHz

1 20 I

ns

II'

I

I
I
I

76.9 ,

I 62.5 1

'50'

, MHz

83.3 I

I 71.4 .

I 62.5 I

I MHz I

For information on internal timing parameters, refer to App. Brief 75 (EPM5000-Series MAX EPLD Timing).

Internal Timing Parameters
Symbol
Parameter

,~N

t 10
. t EXP

1

I

I Conditions

Input pad and buffer delay
I I/O input pad and buffer delay

I Expander array delay

,

t

/C

tiCS

t FD
I t PRE
I t CLR

Output buffer disable delay
Register setup time
Flow-through latch delay

I Registerdelay

'Combinatorial delay
, Register hold time
, Clock delay

I 4 I
I 8'

I

Output buffer and pad delay
Output buffer enable delay'

t xz
t su
t LA TCH
t RD
t COMB
tH

I

I
I
I

I
I

6
4

I
I

I
I

9
7

I

7
7

Unit

I

I
I

I 15
I 10
I 7
I 5

I

I 11 I

I

I
I
I
I

ns
ns
ns
ns
ns

I
I
,
I
I

4
5
ns
, - - , - 7 - , - - ' - 8 - ' - - , - 1 - 1 - , - n - s-,

I

1

I
5

I

6

I
1

I

I

1

1

1

I

I

I
I

7

I
I

I

6

I

1

I

I

,

,

,

'Register preset time

I

1

I

I

I
5

I

, System clock delay

I A/tera Corporation

I

I

EPMS~32

I 5 I
I 10 I

I

, Feedback delay

I Register clear time

I

5

4

I C1 = 5 pF

t OD

EPMS032-2

I~ ~ Max Lfinl Max
I
I

'I

Logic array delay

t zx

Min

I
I
I
I C1 = 35 pF

t LAD
t LAC

Logic control array delay

EPMS032-1

5
5

I
I

I

1

I

I

1

1=1

I
9

8

ns

I

1_ _1_8_1_ _I_n_s_I

1

I

1 = 1 12

I
I

3
1

3

I

I

I
I

ns
ns

I

I

ns

I

1 ns

I

1_8_1 _ _1_1_0_1_ns_1

I

1 2

I

'1'

ns

I

1

ns

,

I

6

I

1 9

ns

I

6

1

I

1 3

I

9

1

I
I

ns

I
I

Page 1351

EJ

EPAf5032

DBta Sheet

I

Notes to tables:
(1)
(2)

(3)
(4)

(5)
(6)

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Numbers in parentheses are for military and industrial temperature versions.
Typical values are for TA =25° C and Vcc =5 V.
Vcc =5 V ± 5%; TA = 0° C to 70° C for commercial use.
Va:. =5 V ± 10%;TA =-400 C to 85° C for industrial use.
Vcc = 5· V ± 10%; Tc =-55° C to 125° C for military use.
Measured with device programmed as a 32-bit counter.
This parameter is measured with a positivEH!-

I-

~

.§.
C
~

:;

80

ci

60

0

5a.
5

Vee =5.0V
Room Temp .

150

Vee = 5.0 V
Room Temp.

?='
~

.§.

100

Q)

>

40

~

0
c(

0

0
0

50

0

1 KHz

Vo Output Voltage (V)

10 KHz 100 KHz 1 MHz 10 MHz 50 MHz

Maximum Frequency

The EPM5064, shown in Figure 17, consists of 64 macrocells equally di vided
into 4 Logic Array Blocks (LABs) that each contain 16 macrocells. Each
LAB also contains 32 expander product terms. The flexibility of the LABs
allows easy integration of any common PLD.
The EPM5064 has 8 dedicated input pins, one of which may be used as a
synchronous system clock that provides enhanced clock-to-output delays.
The device has 28 I/O pins that can be configured for input, output, or
bidirectional data flow. The I/O pins feature dual-feedback to allow any
macrocell to be buried. Two of the LABs have 8 I/O pins (ensuring high
speed for 8-bit bus functions) and the other two LABs have 6 I/O pins.

I Page 138

Altera Corporation

I

Data Sheet

EPM5064

I

Figure 17. EPMS064 Block Diagram
The EPM5064 has 64 maaocelJs
divided into 4 Logic Array Blocks.
9 Input

Input 35

11 Input

InpurCI< 34

12 Input

Input 33

13 Input

Input 31

Dedicated Inputs
System Clock
2 110 Pin

LAB 0
MACROCELL 66

I/O Pin 1

4 110 Pin

MACROCELL2

MACROCELL 55

I/O Pin 44

5 I/O Pin

MACROCELL3

MACROCELL 54

I/O Pin 42

6 110 Pin

MACROCELL4

MACROCELL 53

I/O Pin 41

7 I/O Pin

MACROCELL5

MACROCELL 52

I/O Pin 40

8 110 Pin

MACROCELL6

MACROCELL 51

I/O Pin 39

MACROCELL 50

I/O Pin 38

MACROCELL 49

I/O Pin 37

MACROCELLS
7·16

LABB

MACROCELLS

Programmable
Interconnect
Array
(PIA)

I/O Pin 30

15 VOPin

MAC ROC ELL 17

16 VOPin

MAC ROC ELL 18

17 VOPin

MAC ROC ELL 19

MACROCELL 36

110 Pin 28

18 110 Pin

MAC ROC ELL 20

MACROCELL 35

I/O Pin 27

I/O Pin 29

19 110 Pin

MAC ROC ELL 21

MACROCELL 34

110 Pin 26

20110 Pin

MAC ROC ELL 22

MAC ROC ELL 33

I/O Pin 24

22 I/O Pin

MAC ROC ELL 23

23 I/O Pin

MAC ROC ELL 24
MAC ROCELLS

MACROCELLS
39-48

25-32

IA/tara Corporation

Page 139

EJ

I EPM5064

Dsts Sheet

Absolute Maximum Ratings

I

Symbol

Iv

cc
V pp

Note: See Operating Requirements for EPLDs in this data book.

I

Parameter

I Supply voltage
I-p-rog..!...!...-Jra'--m-m-in......
g -SU-P-PIY-V-o-Ita-g-e

Min

Conditions

, With respect to GND

---I See Note (1)
I

Max

-2.0

7.0

-2.0

13.5

-2.0
7.0
Ii--V-'-'_ _ _ DC input voltage
1_'~M=AX:.!..-_ _!I_DC_V....:c=c:.....o_r_G_N_D_Cu_rr_en_t_ _ _ _ ,I_ _ _ _ _ _ _ _.!_ _ _ _!_ _400
__
,_,-=O=uT-=--_ _1 DC output current, per pin

I No bias

I Ambient temperature

I Under bias

Junction temperature

I Under bias

I-T---'S==-T-G---I Storage temperature

i-IT-J~---I

Recommended Operating Conditions

I

Symbol

-25

I

, P o ' Power dissipation
1 T AMB

25

~

I
I
,I

V

,

v

I

mA

,I

mA

2000

I

mW

--65

+150

I

DC

--65

+135

I

+150

I

Max

I

DC
DC

I
I
1

I

See Note (2)

I

Parameter

I

I

I

Conditions

Min

I

1

Unit

V--:::;. =.c_ _ _I-S-U-pp-IY-V-01-tag-e------+I--------1-4-.7-5-(4-.5-)I 5.25 (5.5) I - - v - - :
c

f-I

'I-v--,-,_ _ _llnput voltage
I
,
I Vo
-o--'u-tp-'-u-t-vo......l t - a g - e - - - - - - , : - - - - - - - - I '
T-A=------ Operating temperature

, For commercial use

i-,

, TA

Operating temperature

1 For industrial use

If-T-'c'-'-----

Case temperature

1

,t

Input rise time

I

R

,I

I Symbol

For military use

, eC3

,
V
I--v--:

-400

,I

++7a05

,I__D-=C:.....-_:

'-55

I

+125

1

1

100

I

100

Tri-state output off-state current

, V CC supply current (standby)

V cc supply current

I Va

0

C

l__n_s__,

I

o._a__li _ _V__:

-0.3

1

IVI

1

I--n-s--:

Min I Typ I Max
Unit
---!.--'·-V-c-c-+-0.-!,·---'
3
2.0
V

High-level TTL output voltage
, I OH = -4 mA DC
-L-o""W--le-v-el-o-ut-pu-t--'vo-Ita-g-e---><--I I OL = a mA DC

1-'---'1==--- Input leakage current
II eCl

I--c-o-n-di-ti-on-s--

High-level input voltage

,-V---'I":":L- - - Low-level input voltage

I-,-'-o-z---

Vee

I

---------,.

I V OH
, VOL

Vcc

1

See Notes (2), (3), (4)

Parameter

,. VI H

,

0

DC

,!-t......:F_ _ _ _ -I--'np-u-tf-al-It-im-e-------I
DC Operating Conditions

0

I_ _

1
1
V
1--0-.4-5- , I - - v - - '

2.4

V CC or GND

-10

I

= V CC or GND

-40

1--+-4-0--l. -.....
J.lA--:

=

I V I = V cc or GND
= V CC or GND
No load, f = 1.0 MHz

VI

90

95

,

+10

125 (200)
135 (225)

i

I

J.lA
mA
mA

See Note (5)

Capacitance

I

Symbol I
Parameter
I
Conditions
,-c-IN---II--'n-pu-t-ca-p-ac-ita-n-ce------, V IN = 0V, f = 1.0 MHz
I_C_O=U::..:T_ _ _,I_O_u_tP,-u_tc_a.....
pa_c_ita_n_ce_ _ _ _ _, VOUT = 0 V, f = 1.0 MHz

IPage 140

Min

.Max

Unit

10

pF

20

pF

Altera Corporation

I

I Data Sheet
AC Operating Conditions

See Note (4)

External Timing Parameters
Symbol

t PDl
t PD2
t su
t

H

t COl
t ASU
t

AH

t
t

CH

CL

tACH

t
t
t

CNT

f

CNT

I

C1

Min

=35 pF

1

I

30

I

1

1~_35_I_ns_1

I

1451

1

120

I

6

1

I

~I

:

EPM?064

IMax I Min IMax I Unit I
1551

l

ns

1251

Insl

1

1

101--- 0-I--I-o---I~
, I 14
I 16 I 1 20 I ns I
5

6
8

I

1

I

1

I

10

1

9

1 11

1=1

I

1

1 30

20

1=1

I

20

----150

I

ns

1

1 ns

1

1 16 1

25

Minimum clock period
Internal maximum frequency
Minimum asynch. clock period
See Note (6)
Max. internal asynch. frequency See Note (6)
50
Max. frequency; pipelined data _ _ _ _I 62.5

I

10

1 12.5

1 14 1

11

1
-C-1-=-35-P-F-1

8

I
I ns 1
lOI--12.5I--I-ns-1

8

----I

Asynchronous clock low time
Asynch. clock to output delay

1

EPM5964-2

I Max
1

15

I

ACOl

MAX

=35 pF
C1 =35 pF

I

I f ACNT
f

Min

1 C1

I

I t ACNT
1

EPMS064-1

I Conditions

Parameter

1 Input to non-registered output
1 1/0 input to non-reg. output
1 Setup time
I Hold time
Clock to output delay
1 Asynchronous setup time
Asynchronous hold time
1 Clock high time
Clock low time
Asynchronous clock high time

ACL

I

EPM5064

14

1

I

1 ns 1

1=1
1 35

ns

1

1 ns

1

25 1 = 1 30 1 ns I
1_4O_1__1~1__1~1
I
I

40

1 50

I

I 25

I

1

I 33.3'

1=1

40

30

I

E]

I

ns
, MHz I

1 = 1 MHz 1

For information on internal timing parameters, refer to App. Brief 75 (EPM5000-Series MAX EPLD Timing).

1 Internal Timing Parameters

I Symbol I

Parameter

I Conditions
--1'-----

EPM5064-1

Min

I-t-,N--"I--Inp-u-tp-ad-a-n-d-bu-ffe-r-de-Ia-y

1 t 10
1 t EXP

1 1/0 input pad and buffer delay 1
1 Expander array delay
1
'-t-"'L=AO'---'I--LO....:.9-iC-a-rra-y-de-=-la-y--"---·I'-- - - -

t LAC

1 Logic control array delay

1

'-t--=o=o=<----'I--O-"ut'--Pu-t-bu-ff-er-a-nd"":"'p-ad-d"":"'e-Ia-y- I C1

t ZX

1

Output buffer enable delay

1

=

35 pF

I

_t-=C=O=MB:.....-+I_c_om_b_in_at_or_ia_1d_e--'Iay'----_ _ _ll_ _ _ _ _ I
t H ' 1 Register hold time
1
1
-t-'-'lc--'I--C"""::lock'---de-la-y- - - - - ' 1 -

----I

1 = 1 6 1 = 1 9 1 ns 1
I
[14
I 20
1 ns 1
'--'-14-1--'-16-'--;;;-1

1 10

'--'-12-1--1-13-,-n-s-I

I

3

1

IAltera Corporation

1
1

1 14'

1 14

I

I

1 3 1--1-4-1--1-4-I-n-s-,
1-1- ' - - ' - 2- ' - - ' - 2-I-ns-,

I

I

I

1--'-8-'--1-10-1--I-n-s-I

I

6

I

t CLR
. t PIA

1

I

10 I
11
I 13
ns I
1-10-'--1-11-1--1-13-1--;;;-1

'I

1

I

1 6
1 12
1 12

i-t-!.P~R-E-+I-R-eg-is-te-r-pr-es-et=--ti-m-e---I
1 Progr. Interconn. Array delay

I

1--'-7-1--1-9-,-n-s-1

I

1 Register clear time

EPM5064

5

_t.....:.;lc=s'--_:I:_s...;;..y_ste_m_c_lock_de_la-'-y_ _ _+I_ _ _ _1
t FO
Feedback delay

I

I

1_ _1_5_'_ _1_5_1_ _1_6_I_n_s_I

-t-=x=z--'I--O-ut-pu-t-bu-ff-er-d-isa-b-Ie-d-ela-y--'I--C-1=-5p-F--,
t su
1 Register setup time
1
, 6
t LATCH 1 Flow-through latch delay
1
1
,-t-"'R'-'-'-O=':"--,'-R-e-gis-te-rd---'e'--Iay----'----I----"

I

I EPM5064-2

I1Max I Min IMax I Min IMax I Unit I

1 2 1
1
5'
I

I

5

I

I

1 ns 1
I ns I
'-1-6-1--'-1-8-I-ns-I
I

8

4

1

I

I

I

2

1
6

1 6

I 16

1

1 4

I 12

1

1=1

3

1

1

2
7

1

1 7

1 ns

I

1

1 20

1 ns

1

Page 141

I

I

I

I

I

1

ns
ns
ns

1

I

1

I EPM5064

Data Sheet

I

Notes to tables:
Minimum IX input is ~.3 V. During transitions, the inputs may undershoot to

(1)

(2)
(3)
(4)

(5)
(6)

-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
Numbers in parentheses are for military and industrial temperature-range versions.
Typical values are for T A = 25° C and Vee = 5 V.
Vee = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
Vee =5 V ± 10%, TA =-400 C to 85° C for ind ustrial use.
Vee =5 V ± 10%, Te =-55° C to 125° C for military use.
Measured with device programmed as a 16-bit counter in each LAB.
This parameter is measured with a positive-edge-triggered clock at the register. For
negative-edge clocking, the tACH and tAa. parameters must be swapped.

Product Availability
Grade

Availability

Commercial

(0° C to 70° C)

Industrial

(-400 C to 85° C)

EPM5064

(-55° C to 125° C)

EPM5064

I Military

EPM5064-1, EPM5064-2, EPM5064

Note: Only military-temperature-range EPLDs are listed above. MIL-STD-883-compliant
product specifications are proVided in Military Product Drawings (MPDs), available from
Altera Marketing by calling 1 (800) SOS-EPLD. These MPDs should be used to prepare
Source Control Drawings (SCDs). See Military Products in this data book.

I Page 142

Altera Corporation

I

EPM512S1
o
o

Features

o

o
o

General
Description

High-density 128-macrocell general-purpose MAX EPLD
256 shareable expander product terms that allow over 32 product terms
in a single macrocell
High-speed multiple-LAB architecture
tpD as fast as 25 ns
Counter frequencies up to 50 MHz
Pipelined data rates up to 62.5 MHz
Programmable 1/0 architecture allowing up to 60 inputs or 52 outputs
Available in 68-pin windowed ceramic or plastic one-timeprogrammable J-lead packages and in 68-pin windowed ceramic PCA
packages

The Altera EPM5128 is a user-configurable, high-performance MAX EPLD
that provides a high-density replacement for 7400-series 551 and MSI TTL
and CMOS logic. (For example, a 74161 counter uses only 3% of the EPM5128.)
The EPM5128 can replace over 60 TfLMSI and 551 components and integrate
multiple 20- and 24-pin low-density PLDs. Figure 18 shows the J-Iead and
PCA package diagrams for the EPM5128.

Figure 18. EPM5128 Pin-Out Diagrams
A quad flat pack (QFP) package is under development. Contact Altera Marketing for information. See
Table 1 in this data sheet for PGA package pin-outs. Package outlines not drawn to scale.

a

gggggg~iii§iggggg
110
110
110
110
110
110
GNO
110
110
110

vee

110
110
110
110
110
110

o
EPM5128

PIN 1

LO
LO
LO
LO
LO
LO

vee
110
LO
LO
GNO
LO
LO
LO
LO
LO
LO

K

0000@@@00
00000@0@000

~ 00
~~

~~

00
00
~:m
00
00
00
00000
c 00
00
00000000000
000000000
EPM5128

G

F

E

o

EPM5128

B
A

1

J-Lead

1

Altera Corporation

2

3

4

5

6

PGA

7

8

9

10

11

QFP

Page 1431

a

EI

I EPM5128

Data Sheet

I

Figure 19 shows output drive characteristics of EPM5128 I/O pins and
typical supply current versus frequency for the EPM5128.
Figure 19. EPM5128 Output Drive Characteristics and Icc vs. Frequency
400

100

IOL

ci
>.

I-

;(

.s
C
~

:;

80

ci

~
Vee =5.0V
Room Temp.

60

()

"5
Q.
"5 ..

300

;(

.s
(J)

>

Vee = 5.0 V
Room Temp.

200

+=I

0

40

«

0

0

.2

0

0.45

1

2

3

Vo Output Voltage (V)

100

10 KHz 100 KHz 1 MHz 10 MHz

so MHz

Maximum Frequency

The EPM5128 consists of 128 macrocells equally divided into 8 Logic Array
Blocks (LABs) that each contain 16 macrocells (see Figure 20). Each LAB
also contains 32 expander product terms. The EPMS128 has 8 dedicated
input pins, one of which may be used as a synchronous system clock. The
EPM5128 contains 52 I/O pins that can be configured for input, output, or
bidirectional data flow. Four of the LABs have 8 I/O pins, and the other 4
haveS I/O pins.

I Page144

Altera Corporation

I

I DataShHt

EPM5128

Rgure 20. EPM5128 Block Diagram
Numbers in parentheses are
packages.

for

32 (L4)

c::>
Input c::>
Input c::>

34(L5)

Input

PGA

.----

~ Input

1 (86) InputICLK
2 (A6)

LAB A

4 (A5)

5 (B4)
6 (A4)
7(B3)

8 (A3)
9 (A2)
10(B2)
11 (B1)

c---

~
~
~

13(C1)

~)'

MACROCELL 113

MACROCELLS

MACROCELLS

9-16

121-128

\7

28(L2)
29 (K3)

30 (L3)
31 (K4)

t

t

MACROCELL 100

{7

.....

...

,

MACROCELL 99

.A
~

...-L

MACROCELL 98

-"'"

...

....

,

MACROCELL 97

Programmable
Interconnect
Array
(PIA)

~
~
~

C--

IAltera Corporation

{7

59(C11)

f--CI 58

(C10)

- C 57(011)

:g

56(010)
55(E11)

~ 53(F11)

-C 52(F10)

MAC ROC ELL 82

:g
:g

h

....

....

MACROCELL 81

---iOJ 46 (J10)

MACROCELL 83

.A.

.....

h

...

.....

MACROCELLS

MACROCELLS

38-48

86-96

0

LAB F

MACROCELL 84

MACROCELL 35

c--

61 (810)
60(811)

102·112

MACROCELL 85

MACROCELL 34

MACROCELL 37

62 (A10)

MACROCELLS

MACROCELL 33

MACROCELL 36

tg

64 (A9)
63(89)

LABG

MACROCELL 18

MACROCELL 21

C-

\7

MACROCELL 101

LAB D

27(K2)

MACROCELL 116

MACROCELL 17

LABC

26(K1)

.....

MACROCELL 114

22-32

25 (J1)

MACROCELL 117

....
....

MACROCELL7

MACROCELLS

24 (J2)

.....

MACROCELL8

~

23 (H1)

....

MACROCELL 115

MACROCELL 20

22 (H2)

MACROCELL 118

.A

MACROCELL6

15(01)

21 (G1)

LABH

~
~

_h

MACROCELL5

~
~

'1'1

;--C 65(88)

...-L

~

35 (K6)

MACROCELL 119

MACROCELL4

C-

Input

MACROCELL2

MACROCELL 19

19(F1)

System Clock

36(L6)

MACROCELL 120

0-

18(F2)

,

Dedicated Inputs

66(A8)

Input

MACROCELL 1

14 (02)

17(E1)

,

MACROCELL3

LABB
12 (C2)

r:::::::

68(A7)

Input

t

t

0

51 (GIl)
49(H11)
48(H10)

47(Jll)

LAB E

MACROCELL 49

MACROCELL 72

MACROCELL 50

MACROCELL 71

- C 45(K11)

MACROCELL 54

MACROCELL 67

MACROCELL 55

MACROCELL 66

:g
:g
:g

MACROCELL 56

MACROCELL 65

- C 38(L7)

MACROCELLS

MACROCELLS

57-64

73-80

MACROCELL 51

h

....

MACROCELL 52
.A

MACROCELL 53

.....

....

MACROCELL 70

.....

MACROCELL 69
h

....

MACROCELL 68

44 (K10)
43 (UO)
42 (L9)
41 (K9)
40(L8)
39 (K8)

Page 145

II

Data Sheet

EPM5128

Absolute Maximum Ratings

·
I
I

Symbol

Note: See Operating Requirements for EPLDs in this data book.

I

Parameter

Conditions

Min

I With respect to GND

Vee

Supply voltage

V pp

Programming supply voltage

1

I

Max

-2.0

7.0

-2.0

13.5

-2.0

7.0

DC input voltage

I
I

I MAX

DC V cc or GND current

---------i----

500

lOUT

DC output current, per pin

_ _ _ _ _ _ _ __

25

Power dissipation

1----------1----

I VI
Po

T STG
T AMB

Storage tempe~ature
Ambient temperature

TJ

Junction temperature

Recommended Operating Conditions

I Symbol
I Vee

See Note (1)

I

I No bias

-25

i

I

I
I

DC
DC

Conditions

Min

Max

Unit

4.75 (4.5)

5.25 (5.5)

V

0

Vee

V

0

Vee

V

0

+70

DC

Operating temperature

For commercial use

Operating temperature

For industrial use

-40

+85

DC

Case temperature

For military use

-55

+125

DC

Input rise time

100

ns

Input fall time

100

ns

I

See Note (2), (3), (4)

Conditions

Parameter

I:_V-=OH'-'--_ _ I High-level TTL output voltage
1,_v-=oL=--_ _1 Low-level output voltage

I Input leakage current

I'---'Io-z---I Tri-state output off-state current

ICC3

DC

See Note (2)

I
I:_v-.!!::IL_ _ _I Low-level input voltage

II CC1

mW

1

I

+150

I:_v---,-,-IH"---_ _ High-level input voltage

I II

.

mA

I_uc:....n_d-'-er_b'--'ia....:,s_ _ _ __

Supply voltage

I

+150

V

l=:::j
I
I

Output voltage

Symbol

2500

I

+135

Input voltage

I

-65

.~

I""';u""';n=-d=-e':';':rb=-ia-s------ --..:;,.;;..-65

Parameter

DC Operating Conditions

I

I V cc supply current (standby)
V CC supply current

Min

Typ

2.0
-0.3
IOH =-4 mA DC

Max

I

Unit

Vec +0.3

I

V

0.8

1

___I

2.4

IOL =8mADC

0.45

V I = Vee or GND

-10

I V 0 = V CC or GND

-40

+10
+40

V

V

I

V

I
I

!!A
!!A

I V I = Vec or GND

150

225 (300) I

mA

V I = V CC or GND

155

250 (350)

mA

No load, f = 1.0 MHz

See Note (5)

Capacitance

I

Symbol

I C IN

I

Parameter

I Input capacitance

I

Conditions

I V IN = 0 V,

f = 1.0 MHz

I=C=:O:UT======I_o_u_t:.....pu_t_ca...:.p_a_ci_ta_nc_e_ _ _ _ _ _ 1 VOUT= 0 V, f = 1.0 MHz

Page 146

Min

Max

Unit

10

pF

20

pF

A/tera ~orporation

I

IData Sheet

EPM512S1

AC Operating Conditions

See Note (4)

ExtmnalTlmlng Paramelllfs

EPM5128-1

!-S_ym_bo_I_I-___
p_ar_ame_t_er_ _ _I_co_n_d_iti_on_s-l-_M_in-!I Max

I EPM5128-2 I
~I

I

EPM5128

I

I Min I Max

I Unit I

I

I

I

,-I

I

Max

1_3O_1__I_35_I_n_s_I

_t.....:;P-=D-=-1__!_In...;....pu_t_to_n_on_-r_eg,-is_te_red_ou_tp_u_t_I C1 = 35 pF
_25_
t PD2
I VO input to non-reg. output
I-C-1-=-3S-P-F--I---I 40
R=I
_t-=su=----_'_S_etu......;..p_tim_e_ _ _ _ _ 1
t H
I Hold time
l-t--=-C=-O-1-,-C-IOC-k-I-O-ou-tp-ut-d-ela-y---I Cl = 35 pF
I t ASU

I Asynchronous setup time

I

5

I

I

81

I Clock high time
I
I-C-IOC-k-Io-'-w-ti-me-----I
Asynchronous clock high time

1 t ACL

Asynchronous clock low time

I

1 t AC01

Asynch. clock to output delay

1 C1 = 35 pF

I t CHT
1 f CNT
1 t ACHT

Minimum dock period
Internal maximum frequency
Minimum asynch. dock period

I f ACHT
f MAX

Max. internal asynch. frequency 1 See Note (6)
Max. frequency; pipelined data

I

ns

I

6

I

I

8

I

I

ns

I

1-----sj--1sl~-1-0-I--I~

1 tACH

I

55

15 - - 20
25
~
0
0
I 0 I
I ns I
' - - / - 1 - 4-/--1-1-6-1--1-2O-1~
I

Ii-t--'A=H=----rI_A_sy_n_ch_ro_n_ou_s_hO_ld_ti_·m_e_ _ 1
I t CH
I t CL

I

45

I

I

8

I

1101
I 10 I

I 12.5
I 12.5

I
I

I
I

ns
ns

I
I

1

11

1

1 14

I

1

I

ns

1

I

I
I
I

I See Note (6)

I 50
1

I

I

9

I
I
I
I
1

20
20

I 40
1

ns 1
I
I 33.3
I MHz I
1-25-1--1-30-1----;;-1

I

I

I

11

40

I
I
I

30
25

I
I
I

16

I
I
I

25

1 50 1
62.5

I

1

14

1 33.3

1

I

35

I

30

I
I

I
I
I

ns

I

ns

I

I MHz I

1-50-1--1-4O-1--1~1

For information on internal timing parameters, refer to App. Brief 75 (EPM5000-Series MAX EPLD Timing).
1 Internal

Timing Parameters

I Symbol I
I t

Parameter

I EPM5128-1 1 EPM5128-2 1 EPM5128
1
1
I-c-o-n-di-Uo-n-s-!I Min I Max I Min I Max I~I Max I Unit I

I Input pad and buffer delay

I

I

5

I

t 10
1 t EXP
I t LAD
I t LAC
1 t OD
1 tzx

11/0 input pad and buffer delay

I

I

6

~1-6-1--I-g-l-n-s-I

1 Output buffer enable delay

I

. t xz
t su

1 Output buffer disable delay

I-C-1-=-S-PF--!1

IN

I

I Expander array delay
, Logic array delay

I
-----1

I Logic control array delay
1 Output buffer and pad delay

C1 = 35 pF

7

I - - I - g - I - n - s-I

1 12
1 12

1
1

1 14
1 14

1
I 20
I ns 1
1--1-16-I-n-s-I

1

I 10

1

1 12

1--,-13-I-n-s-I

1

1 5

1

1 5

1--'-6-,-n-s-I

1--1-10-1--1-11-1--'-13-1~
1 10

1

1 11

1--'-13-1----;;-1

1 8

1

1-10-1--I-n-s-1

1 Flow-through latch delay

I
I

1

t LA TCH

1

1 3

1

1 4

1

'4

1 ns

t RD
t COMB
tH
t /C

1 Register delay

I

1

1 1

1

1 2

1

1 2

1 ns

1 Combinatorial delay

,

1 Clock delay

1

t /cs

1 System dock delay

1

t FD

I Register setup time

I

1 Register hold time

I Feedback delay

I

t CLR

I Register clear time

I
I

----;-----1

I

I_t...:..p..=.;/A'---_,I __P_rOQ=.r_.l_nt_er_co_n_n._A_rra~y_de_la~y__,_ _ _ _ _1

IAltera Corporation

6

I

-t"':"P=-RE--il--R-eg-is-te-r-pr-es-et'-ti-m-e

I

I

I
6

3

I

I

I

1 14

1

I 2 I
I 1 I
15 1

I
8

1

4

I

I

I 10

I

1 16

1

I 18

1 2

I

I

3

I

ns

I

I

1

1
6

I

I

2
7

I

1

ns
ns

1

1

I

ns

I

I

ns

I

1

5

I

I

6

I

I 14

I

I 16

1

I

1

I

I

4

I 7
I 20

I

ns

I

I

ns

I

1 ns

I

Page 147

I

3

Data Sheet \

EPAl5128

Notes to tables:
(1) Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
(2) Numbers in parentheses are for military and industrial temperature-range versions.
(3) Typical values are for TA = 25° C and Vee = 5 V.
(4) Vee =5 V ± 5%, TA =0° C to 70° C for commercial use.
Vee = 5 V ± 10%, TA = -40" C to 85° C for ind ustrial use.
Vee =5 V ± 10%, Tc =-55° C to 125° C for military use.
(5) Measured with device programmed as a 16-bit counter in each LAB.
(6) This parameter is measured with a positive-edge-triggered clock at the register. For
negative-edge clocking, the tACH and tAo.. parameters must be swapped.

Product Availability
1_________G_r_ad_e__________!__________

I Commercial
I Industrial
I Military

(0° C to 70° C)

A_v_a_ila_b_il_i~__________~

EPM5128-1, EPM5128-2, EPM5128

(-40° C to 85° C)

EPM5128

(-55° C to 125° C)

EPM5128

Note: Only military-temperature-range EPLDs are listed above. MIL-STD-883-compliant
product specifications are provided in Military Product Drawings (MPDs), available from
Altera Marketing by calling 1 (800) SOS-EPLD. These MPDs should be used to prepare
Source Control Drawings (SCDs). See Military Products in this data book.

Table 1 shows the pin-outs for the EPM5128 PCA package.
Table 1. EPM5128 PGA Pin-Outs

Pin

Function

Pin

Function

Pin

Function

A2
A3
A4
A5
A6
A7
AS
A9
Al0
81
82
B3

110

B10
B11
C1
C2
C10
C11
01
02
010
011
El
E2
E10
El1
F1
F2
FlO
F11

I/O
I/O

G1
G2
G10
G11
H1
H2
Hl0
Hl1
Jl
J2
Jl0
Jll
K1
K2
K3
K4
K5
K6

I/O
VCC
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
Input

B4
B5

B6
B7
B8
B9

Page 148

I/O
I/O
I/O
Input
Input
Input

110
I/O
I/O
I/O
I/O
I/O
VCC
Input/ClK
GNO
1/0

I/O

110
I/O
I/O

110
I/O
I/O
I/O
I/O
I/O
GNO
VCC
I/O
I/O

110
1/0

I/O

Pin
K7
KS
K9
K10
K11
l2
l3
l4
l5
l6
l7
lS
19
L10

Function
VCC

110
I/O
I/O

110
I/O
I/O
Input
Input
Input
I/O
I/O

110
I/O

Altera Corporation

I

EPM51301
o
o

Features

o
o
o
o
o
o
General
Description

High-density 128-macrocell general-purpose MAX EPLD
128 macrocells optimized for pin-intensive applications, easily
integrating over 60 TIL M51 and 551 components
High pin count for 16- or 32-bit data paths
256 shareable expander product terms
More than 32 product terms in a single macrocell
128 additional latches provided bycross-couplingexpanders
All inputs can be latched without using macrocells
20 high-speed dedicated inputs for fast latching of 16-bit functions
Multiple LAB architecture ensuring high speeds
tpD as fast as 25 ns
Counter frequencies up to 50 MHz
Pipelined data rates up to 62.5 MHz
Synchronous clocking providing fast clock-to-output delays for busoriented functions
Programmable I/O architecture that allows up to 84 inputs or 64
outputs in a windowed ceramic PGA or QFP or plastic QFP package

The Altera EPM5130 is a user-configurable, high-performance MAX EPLD
that is optimized for pin-intensive designs. It provides a high-density
replacement for 7400-series 551 and MSI TIL and CMOS lOgic. Package pinout diagrams for the EPM5130 are shown in Figure 21.

Figure 21. EPM5130 Pin·Out Diagrams

See Table 2 in this data sheet for QFP pin-outs. Package outlines not drawn to scale.
g

iii i ~ i

g g

PIN 1

o

EPM5130

110

110

110

110

i/O

110

110

110

110

110

110

10

110

110

110

10

110

110

110

110

K

vee vee 110

H

110

110

G

110

GNO GNO F

110

110

110

110

110

GNDGND 110
110 110

10

110 vee vee

o

110

110

110

10

110

110

110

110

110

110

110

110

110

110

110

110

1

2

3

4

5

II

7

II

II

10 11

12 13

PIN51

QFP

PGA
l-

I Altera Corporation

I-

g g i~

~ i~

Q Q ~
~

0

~

I-

ez i
c:I

~

~

~

~~ ~~ ~~ ~~ Q

Psge149

I

II

I EPM5130

Data Sheet

I

The EPM5130 EPLD is available in a windowed ceramic pin grid array
(PCA) or 1oo-pin windowed ceramic or plastic one-time-programmable
quad flat pack (QFP) package.
A single EPM5130 can quickly integrate multiple 20- and 24-pin lowdensity PLDs and high-pin-count subsystems, such as custom DMA
controllers. In addition, it can handle a 32-bit data path application with
enough I/O to allow the required control signals to be implemented.
Figure 22 shows output drive characteristics of EPM5130 I/O pins and
typical supply current versus frequency for the EPM5130.
Figure 22. EPM5130 Output Drive Characteristics and Icc vs. Frequency
500

100

ci

>-

~

;(

80

ci

g

'E
~

:;

~
Vee =5.0V
Room Temp.

60

u

'5
a.

S

400

;(

g

Vee =5.0V
Room Temp.
300

Q)

>

~

0

40

«

0

200

0

..!:?

a

100

2

3

Va Output Voltage (V)

1 KHz

10 KHz 100 KHz 1 MHz 10 MHz

so MHz

Maximum Frequency

The EPM5130 consists of 128 macrocells equally divided into 8 Logic Array
Blocks (LABs), each containing 16 macrocells and 32 expander product
terms (see Figure 23). Expander product terms can be used and shared by
all macrocells in the device to ensure efficient use of device resources.
Because the LAB is very compact, the high speeds required by most I/O
subsystems are maintained.
The EPM5130 has 20 dedicated input pins that allow high-speed input
latching of 16-bit functions. One of these inputs can be configured as a
synchronous system clock to provide enhanced clock-ta-output delays for
bus-oriented functions. The EPM5130 also has 64 I/O pins, 8 in each LAB,
that can be configured for input, output, or bidirectional data flow. Dual
feedback on the I/O pins provides the most efficient use of device pin
resources.

I Page 150

Altera Corporation

I

EPM5130

IOatsShHt

Rgure 23. EPM5130
Block Diagram

9 (AID)

IIlIU

10 (B9)

Numbers in
parentheses are for
PGA packages.

IIlIU

11 (A9)

IIlIU

14 (A8)

IIlIU

2 (CI2)

110 Pin

3 (A13)

110 Pin

4 (812)

110 Pin

5 (A12)

110 Pin

6 (811)

110 Pin

7 (All)

110 Pin

8 (810)

110 Pin

23 (A4)

110 Pin

24 (84)

110 Pin

2S (Al)

110 Pin

26 (A2)

110 Pin

27 (83)

110 Pin

28(M)

110 Pin

29 (B2)

110 Pin

30 (81)

110 Pin

32 (Cl)

110 Pin

33 (02)

110 Pin

34(01)

110 Pin

35 (E2)

110 Pin

36(El)

110 Pin

39(Fl)

110 Pin

4O(G2)

110 Pin

110 Pin

42 (Gl)

110 Pin

4S (H3)

110 Pin

46 (Jl)

110 Pin

47 (J2)

110 Pin

48(1<1)

110 Pin

49(1<2)

110 Pin

50 (l1)

110 Pin

66(l7)

64 (N6)

~InPl'

67(N7)

20 (C6)

IIlIU ::::::-

<:JInPl'

70 (l8)

21 (AS)

IIlIU ::::::-

=InPl'

71 (N9)

IIlIU

8lnPl'

72

~

g:

..

~

..

LABB

t

System Clock

MACROCELL2

MACROCELL 119

.....

.A.

J-..

......

~


1'00"'=

....

~

~

MACROCELL 70
MACROCELL 69
MACROCELL 68
MACROCELLffl

MACROCELL 55

MACROCELL 66

MACROCELL 56

MACROCELL 86

MACROCELL5

MACROCELL5

57-64

73-60

:g
:g
:g
:g
:g
:g
:g
~

110 Pin

80 (MI3)

110 Pin

79 (MI2)

110 Pin
110 Pin
110 Pin
110 Pin

78 (NI3)

7S(Nll)

110 Pin

74 (Ml0)

110 Pin

73 (Nl0)

110 Pin

58 (M4)

110 Pin

57(N3)

110 Pin

56(M3)

110 Pin
110 Pin
110 Pin

55 (N2)

53 (Nl)

110 Pin
110 Pin

51 (Ml)

n(Mll)
76 (NI2)

54 (M2)

52 (L2)

Page 151

EJ

I EPM5130

Preliminary Data

Absolute Maximum Ratings

I

Symbol

I

I

I
I

Conditions

Min

Max

With respect to GND

-2.0

7.0

See Note (1)

-2.0

13.5

Parameter
Programming supply voltage

vpp

I

Note: See Operating Requirements for EPLDs in this data book.

Sueel~ voltage

vee

Data Sheet

V,

DC ineut voltage

I MAX

DC V cc or GND current

lOUT

DC output current, per pin

-2.0

1

I
I

--'Po:<.-_ _ _, Power dissieation

;-1

I_T..:sc..:..:TG=--_ _1 Storage temperature

7.0

I~I

2500

1

+150

1 No bias

-65

500
25

~
EE
mA

mW

1

0

C

---6-5--~'--o......;C~I_T-=.J_ _ _I_J_u_nc_tio_n_te_m.-.,p_e_ra_tu_re_ _ _ _ _,I._u_n_de_r_b_ias_ _ _ _ _._ _ _ I~1
C
'_T....:..;A::..:.:;MB=--_ _I_A_m_b_ie_nt_te_m->..pe_r_at_ur_e_ _ _ _ _I_u_n_de_r_b_ias_ _ _ _ _

0

Recommended Operating Conditions

I

Symbol

I

Parameter

Conditions

1

Min

Max

Unit

I

_vc=c"'-_ _I......;s~u""__'pp. . . .ly'_v;,...;;.0....;,;lta~g_e
.
_ _ _ _ _ _ _!I._ _ _ _ _ _ _ _ _ _
4_.7_5_,' _ _5......;.2....;,;5_1

V

;-1

~I_V~I_ _ _I_I~np_u_tv_O_lta~g_e_ _ _ _ _ _ _i'._ _ _ _ _ _ _ _ _ _ _ _O__i___V~c~c-I'

VV

1;-V_o~____I_o~u=tP....;,;ut:.....v,;,,;;o,.;,,;.lta=g~e_ _ _ _ _ _I_________. . . ;o=_________
V c=c_
I TA

I For commercial use

, Operating temperature

;-,T--'A:...:.....-----' Operating temperature

, For industrial use

0

+70

-40

+85

I

0

C

0

C

I

I

I TC
I Case temperature
For military use
-55
+ 125
1
0 c
I
:'t=R:======'-I:.....np....;,;u:.....tr....;,;is......;e~tim......;e~:.....-------!I·~~~~~---!-~~-!---100=--~

~It--'F_ _ _ _I-I--'np-u-tf-al-It-im-e--------I!·--------'----l---1oo--I~1

DC Operating Conditions

I
I

Symbol

vI H

IV

Vee

= 5 V ± 5 %, TA = 0° C to 70° C for commercial use,

1----p-a-ra-me-te-r----II.:--Co-n-di-ti-On-s-----li-----M_a_x__il._u_n_it~

'loW-level outeut voltage

I II

I Input leakage current

/i oz

I Tri-state output off-state current

1 I CC1

I V CC supply current (standby)

ICC3

V cc + 0.3

/ High-level input voltage

I low-level input voltage
I~__I High-level TTl outeut voltage
II

, VOl

See Note (2)

V CC supply current

1. _ _ _ _ _ _ _ _ _ _ _

II OH

I

l
I

V

______
O._8__ =.==v==:
i
i

=-4 mA DC

V

1,_I-"O=l-=-8-m-A-DC--~i---_i_-- _----'0....;,;.4;..;;,5__l._......;v_-i

I V I = V CC or GND

+10

I Vo V CC or GND
I V I = V CC or GND
=

VI

= V cc or GND

180

il

_~J!A~_

+40

,I_..L;;J!A"--_:

250

mA

275

mA

Max

Unit

10

pF

20

pF

No load, f = 1.0 MHz

See Note (3)

Capacitance
1_ _
Sy_m_b_O_I_,I,----p-a-ra-me-te-r____I

, C IN

I Input capacitance

I VIN = °V, f =1.0 MHz

,=C:O:U~T~-_-_-_-,:"-O--'u"--tP-u:.....tc=a=pa:.-c-ita..:...n:.....ce-----'

I Page 152

Conditions

VOUT=

°

V, f = 1.0 MHz

Min

Altera Corporation

I

IData Sheet
AC Operating Conditions
Externa~

Symbol

t P01
t PD2
t su
tH
t
t
t
t
t

C01
ASU

I

CL

tACH

1 t ACL

t

AC01

t

CNT

f

CNT

t

ACNT

f ACNT
f MAX

Vee

= 5 V ± 5 %, TA = 0° C to

Timing Parameters
Parameter

I

Input to noo-registered output
110 input to non-reg. output

I Setup time
I Holdtime

1 Clock to output delay

I Asynchronous setup time
Asynchronous hold time
Clock high time

AH
CH

Preliminary Data

I Clock low time

1 Asynchronous clock high time
1 Asynchronous clock low time

I Conditions

70° C for commercial use

EPM5130-1

1

Min

EPM5130-2

Max

Min

EPM5130

I
~
~

25

I

30

35

40

1 45

55

I
I C1 =35 pF 1
I
I
I
1
1

:

1
1

1
I'

I Asynch. clock to output delay

1
1 C1

1 Minimum dock period
jlnternal maximum frequency

I

1 Minimum asynch. dock period

1 See Note (4)

=35 pF

1

I Max. internal asynch. frequency 1 See Note (4)

I Max. frequency; pipelined data I

I~~=

20

0

0
14

I

6

1

1

6 1
8.

1
.

8

I

1

10

I

ns

I

ns

1

1

1 ns

1

10 1
12.5 .

1 ns
• ns

'-1_1_6_1 _ _1_20_1

5

8
11

I

I Unit

1 C1 =35 pF
15

1~

r~ ~Max

1 C1 = 35 pF

I

I

EPM5130

I

.

8

I
1

1

1 10
1 14

1
1 12.5 1
1 ns 1
1--1-1-6-I--I-n-s-I

9

i

I

11

1

50

I

I
I

40

I

1

1

1 40

1

I

14

I

I

ns

1

1~-25-I---30-I--'-35-I-n-s-I

I
I
1
I

I

1
50

20
20

1

I 62.5 I

I

_1__I_30_I~1
I 33.3 I
I MHz I
25 1
I 30 I ns I
1 33.3 I
1 MHz 1

1_25

I

50

'40

I

I MHz I

For information on internal timing parameters, refer to App. Brief 75 (EPM5000-Series MAX EPLD Timing).
I

I

Internal T~ming Parameters
Symbol
Parameter

I

I Conditions

I t IN
It

I Input pad and buffer delay 1
I 110 input pad and buffer delay ,I

1 t EXP

, Expander array delay

10

EP~130-1
Min

1

EPM5.130-2

1

EPM.5130

I

I

7

I

6

1

I
I

I
I

I

IMax I Min IMax I Min I M~x I Unit I
I

I

I

5

1

I

6.
12

9

9

I
I

ns
ns

' - ' _ 1 4 _ ._ _ ~'~1

_I

1 t LAO

logic array delay

1 12

'-1_14_1_ _1_16_I_n_s

1 t LAC

logic control array delay

I

1--=1 12

1

1 13

1 ns

1

I

I

I

1 ns

1

I t 00
I tzx

=35 pF

Output buffer and pad delay
Output buffer enable delay

C1

I t xz

Output buffer disable delay

C1 = 5 pF

1 t LATCH

Register setup time
Flow-through latch delay

I t su

1 t RO

t COMB
tH
t IC
t ICS
t FO
t PRE
t CLR

Register delay
Combinatorial delay

I

I

I

I 10 I

5

I

5

6

1--1-10-1--1-11-1--1-13-1~1

I
I
I
1

Register hold time

,

Clock delay

I

System dock delay

1

Feedback delay

1

Register preset time

1

_R_eg,,-i_ste_r_cle_a_rt_im_e_ _ _ _ - - - - - ; 1

_t~P.=...!IA _ _ _ P_rog...::<.-r._In_te_rc_on_n_.A_rr-,ay,--d_el--,aY~_'_ _ _ _ _
A/tera Corporation

10

JI

6

I
I

I

3

I

1
1 3

1

I

I 11 I

8

1
1 4

I
I

1

I

2
4

I

I 13

10

1

I

1 ns

I

ns

I

I

1-'

2
4

1

1

-I

1~-4-I-n-s
ns
ns

I

I

.

2

8
1
----w-I--I~I
~1-1-6-'--1-1-8-I~I
1 1 - 2-11-3-1~1

I
I

1

1

I

1

I

5

1

I

6

I

~I-n-s-I

1 16

I

1 20

6'
I'

14

2

I

ns

I

1_6_1__1_7_1~

1~_ _

1141

I

1 ns

Page 153

1

I

3

I EPM5130

DataShHtl
Notes to tables:
(1)

(2)
(3)
(4)

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
Typical values are for TA =25° C and Vcc =5 V.
Measured with device programmed as a 16-bit counter in each LAB.
This parameter is measured with a positiv~ge-triggered clock at the register. For
negative-edge docking, the tACH and tAc. parameters must be swapped.

Product Availability

Commercial
Industrial

I Military

I

Availability

Grade

EPM51~1,EPM51~2,EPM5130

(0° C to 70° C)
(-40° C to 85° C)

Consult factory

(-55° C to 125° C)

Consult factory

I

Note: Only military-temperature-range EPLDs are listed above. MIL-STD-883-compliant
product specifications are provided in Military Product Drawings (MPDs), available from
Altera Marketing by calling 1 (800) 5OS-EPLD. These MPDs should be used to prepare
Source Control Drawings (SCDs). See Military Products in this data book.

Pin-outs for the quad flat pack (QFP) are shown in Table 2.
Table 2. EPM5130 QFP Pin-Outs

Page 154

Pin

Function

Pin

Function

Pin

Function

Pin

Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

I/O
1/0
1/0
I/O
I/O
I/O
1/0
I/O
Input
Input
Input

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

I/O
1/0
1/0
I/O
I/O
1/0
1/0
I/O
1/0
I/O
I/O

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

1/0
1/0
1/0
1/0
1/0

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

1/0
1/0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

GND
GND
Input
Input
Input/ClK
Input
Vee
Vee
Input
Input
Input
I/O
I/O
I/O

GND
GND
I/O
I/O
I/O
I/O
Vee
Vee
I/O
I/O
I/O
I/O
I/O
I/O

110
1/0
I/O
Input
Input
Input

GND
GND
Input
Input
Input
Input
Vee
Vee
Input
Input
Input
I/O
1/0
I/O

GND
GND
I/O
I/O
I/O
I/O
Vee
Vee
I/O
I/O
I/O
I/O
I/O
I/O

A/tara Corporation

I

EPM5192I
o

Features

o
o
o
o

General
Description

192 macrocells for easy replacement of over 100 TIL devices and for
integration of complete logic boards into a single package
384 shareable expander product terms that offer flexibility for register
and combinatorial logic expansion
Multiple LAB architecture that ensures high speeds
tpD as fast as 25 ns
Counter frequencies up to 50 MHz
Pipelined data rates up to 62.5 MHz
Programmable I/O architecture allowing up to 72 inputs or 64 outputs,
and I/O tri-state buffers that facilitate connections to system buses
A vailable in 84-pin windowed ceramic and plastic one-timeprogrammable J-Iead packages; 84-pin windowed ceramic PCA
package; and 100-pin windowed ceramic and plastic one-timeprogrammable QFP packages

Altera's EPM5192 is a user-configurable, high-performance MAX EPLD
that provides high-density replacement for 7400-series S5I and MSI TIL
and CMOS logic. It is available inJ-Iead ceramic aLCC} and plastic (PLCC),
ceramic pin-grid array(PCA},andceramicand plastic quad flat pack (QFP)
packages (see Figure 24).
Because windowed packages are erasable, they may be used for quick and
efficient system prototyping. On the other hand, plastic one-timeprogrammable (OTP) packages provide a low-cost solution for volume
production.

Figure 24. EPM5192 Pin-Out Diagrams

110
110
110
110
110
110
GND
GND
110
110
110
110

vee

110
110
110
110
110
110
110
110

Tables 3 and 4 in this data sheet list the PGA and QFP package pin-outs.
Package outlines not drawn to scale.

PIN 1

110
110
110

~
~

0

EPM5192

00000000000
0000@@0<*>00
J0@
000
00
~cH00
00
~
000 EPM5192 000
~D F 000
Bottom
,...
... ,...,.,...,..
L

K

110

G

GNO

0~0

View

:
E

~ ~u~~.~~~.
000@0@@-

o

EPM5192

A

1

J-Lead

I Altera Corporation

2

3

•

5

6

PGA

7

8

9

10

11

QFP

Page 155 I

a

E.I

IEPM5192

Data Sheet

I

The EPM5192 can replace over 100 TIL 551 and M51 components and
integrate the logic contained in over 20 22V10 devices. In addition, it
accommodates other low-density PLDs of all sizes. These fea tures allow the
EPM5192 to easily integrate complete systems into a single device.
Figure 25 shows output drive characteristics of EPM5192 I/O pins and
typical supply current versus frequency for the EPM5192.
Rgure 25. EPM5192 OUtput Drive Character/stlcs and Icc vs. Frequency
500

100

ci.

~

<'
g
'E

~
~
0

5a.
5

400

80

ci.

Vee =5.0V
Room Temp.

~
60

Vee =5.0 V
Room Temp.

<'
g
Q)

£i0

40

c(

0

300

200

8

0

100

50 MHz

Vo Output Voltage (V)

Maximum Frequency

The EPM5192 consists of 192 macrocells equall y di vided into 12 Logic Arra y
Blocks (LABs) that each contain 16 macrocells and 32 expander product
terms (see Figure 26). Because each LAB is very com pact, high performance
is maintained and device resources are used efficiently.
The EPM5192 has 8 dedicated input pins, one of which can be used as a
system clock. The EPM5192 can mix synchronous and asynchronous clocking
in a single device, facilitating easy integration of multiple subsystems. It
also has 64 I/O pins that can be configured for inpu t, outpu t, or bidirectional
da ta flow, prOviding an interface to high-speed, bus-orien ted a pplica tions.

I Page 156

A/tera Corporation

I

IData Sheet

EPM5192

Figure 26. EPII5192
Block Diagram

l(A&) (91) InpuIICIk

Numbers in parentheses
are for PGA packages;
numbers in square
brackets are for OFP
packages.

2(AS)

4(CS) (96)
5 (A4)

(96)

6 (84)

(97)

7 (A3) (98)
8 (A2)

(99)

9 (83) (100)

Input

42(.16) (4G)

Inpil

LAB A

=-

~

MACROCELL 1
MACROCELL2

)g:

MACROCELL8
MACROCELLS
9-16

14(Cl) (8)
15 (02) (9)

18 (01) (10)
17 (El) (II)
20 (F2) (14)
21 (F3) (15)

g:
g:

System Clock

LABB

<'t

MACROCELL 183

.z......
,....

~

MACROCELL 182

~

MACROCELL 180

......-

IG==

MACROCELL 181

MACROCELL 179
MACROCELL 178

,

MACROCELL 177

,

MACROCELLS

MAC ROCELL 17

MACROCELL 19

Jo...
,....

MAC ROCELL 20

¢=

'""'-

......-

~

MACROCELL 183
MACROCELl 162
MACROCELL 181
MACROCELLS
186·176

<'t

+ <'t

+

MACROCELL 35
MACROCEll38

¢=

MACROCELLS

Programmable
Interconnect
Array
(PIA)

.A..

.....~

MACROCELL 147
MACROCELL 146
MACROCELL 146

23 (Gl) (17)
25 (Fl) (20)
26 (HI) (21)

g:
g:

<'t

MAC ROCELl 49

+ <'t

+
-v

¢=

MACROCELL 52

.A.

......-

=C>

MACROCELLS

28 (Jl) (23)
29 (1<1) (24)
30 (J2) (25)

31 (l1) (26)
32 (1<2) (27)
33 (1<3) (31)
34(l2) [321
35 (l3) (33)
36 (1<4) (34)
37 (l4) (35)
38 (.lS) (36)

g:
g:
g:
g:

g:

g:

MACROCELL 65

MACROCELL 130
MACROCELL 129

,

....

¢=

MAC ROCELL 88

~

...

.A..

===t>

MACROCELL 115
MACROCELl114
MACROCELL 113
MACROCELLS

89-80

117·128

MACROCELL 81

+

+

~

(74) (811)71

(73) (Cll) 70
(72) (010) 89

~
~

(71) (011)88
(70) (£9) ff1

(67) (Ell) 86
(86) (Fl1)84

MACROCELL 103

MACROCELL 84

-~
....

MACROCELL 86

...:;:=

....

.A..

==;:>

~
~

[86) (F9) 83
[64) (G9) 82
(81) (FlO) 59
(80) (Hll)58

tg

~

(59) (Hl0)57
(58) (J11)58
(57) (1<11)55

(58) (Jl0)54

LABG

MACROCELL 104

MACROCELL 82
MAC ROCELL 83

(75) (Cl0)72

LABH

MACROCELLS

~

~
~

133·144

MACROCELL 118

..J'o...

MACROCELLffT

MACROCELL 102
MACROCELL 101
MACROCELL 100

MACROCELL 88

MACROCELL 99

MACROCELLIrl

MACROCELL 98

MACROCELL 88

MACROCElL 'R

MACROCELLS

MACROCELLS
105·112

89-96

IA/tera Corporation

+

MAC ROCELL 88

LABF

MACROCELL 131

MACROCELLS

53-84

27 (H2) (22)

(810)74

(76) (All)73

LAB I

MACROCELL 132

Jo...

MACROCELl 51

<'t

(81) (B9) 7S

149-180

MAC ROCElL so

LABE

(83) (A9)77

{821 (Al0)78

MACROCELlS

37·48

22 (G3) (16)

(86) (A8)79

(84) (88)78

LABJ

MACROCELL 148

Jo".
'V"

(86) (88)80

LABK

21-32

MACROCELL 34

LABD

~

MACROCELLS

MAC ROCELL 33

~
~
~ enl
~

186·192

MACROCELL 184

MACROCELL 18

LABe

LABL

MACROCELL 184

MACROCELL6

IS

13 (81) [7)

•

MACROCELL5

11 (82)

•~

Dedicated ~Is

MACROCELl4

MACROCELL7

Ir!pI.f [421 (l7) 44

~ Ir!pI.f (41) (.17)43

MACROCELL3

(1)

g:
g:

~ Ir!pI.f (89) (C7) 83

--=

=:

10 (AI)

12(C2) (6)

~ Ir!pI.f (90) (C6) 84

Input ~

[921

41 (1<6) (39)

g:
g:
g:

-

=:;

~
~
~
~

(55) (1<10)53
(51) (l11)52

(50) (1<9) 51
(49) (l10)50

[48) (l9) 49
(47) (1<8) 48

(48) (L8) 47
(45) (l8) 46

Page 157

I EPM5192

Data Sheet

Absolute Maximum Ratings

I

I

Note: See Operating Requirements for EPLDs in this data book.

Conditions

Parameter

Symbol

vee

SU2J)/y volta~e

With respect to GND

See Note (1)

. Vpp

Programming supply voltage

I VI

DC input voltage

I I MAX

DC Vee or GND current

I lOUT
.

I

I

Min

I

Max

Unit

-2.0

7.0

V

-2.0

13.5

-2.0

7.0

500

DC output current, per pin

-25

I

I Storage temperature

25
2500

I No bias

I

_T--<.A=M=B--_I: Ambient temperature

I_T~J~

I
I

I Power dissipation

I Po
I T STG

I

Under bias

-65

+150

-65

+135

___~I~J=u~nc=no=n~m=m=p~er=at=ur~e__________u=n=d=er=b=ia=s_______,_______

+150

V

I

V

I

RR
I
I
mW

I

°C

I

I

°C

.

~

Recommended Operating Conditions

I

I

Symbol

I vee

Conditions

Parameter

I Supply voltage

II-T-,A~_ _--,I

For commercial use

Operating temperature

Min

Max

Unit

4.75

5.25

V

0

Vee

V

0

Vee

V

0

+70

°C

I T A l Operating temperature

For industrial use

-40

+85

°C

1 T e l Case temperature

For military use

-55

+125

°C

100

ns

I

I tA

Input rise time

l!-t....;....F_ _ _ _I_I........
np_u_t'_aI_It_im_e_ _ _ _ _ _ _ _ ,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_____
100
ns_ _,

DC Operating Conditions

I

~m~

See Notes (2), (3)

I-------p-M-a-me-t-w------II:--co-n-d-H-~-~--~---~---i~-M-a-x~1

I_V--!.I.w..H_ _ _1 High-level input voltage

I LOW-level input voltage

;-1V--=I.=. . L_ _ _

I_V-"O:.:...:H~_ _I High-level m

output voltage

II-V--'o=L:---_ _1 LOW-level output voltage

Vee + 0.3 I
I

I II

I Input leakage current

I VI = Vee or GND

IICC1

I Vee supply current (standby)

I Vo = Vee or GND
I-V-'I:""=-V-e'=e=-o-rG-N-D--'!---'!---

1_I~oz!':....-_ _ 1 Tri-state output off-state current
'CC3

Vee supply current

VI = Vee or GND

270

No load, f = 1.0 MHz

See Note (4)

Capacitance

I

Symbol

I

Parameter

I Input capadtance

I C OUT

I Page 158

I

Output capacitance

I
I

I

V

0.45

I

V

+ 10

I

+40
360

I
I

JlA
JlA

L

V

mA
mA

Max

Unit

V IN = 0 V, f = 1.0 MHz

10

pF

I VOUT=OV, f=1.0MHz

20

pF

Conditions

Min

V

0.8

1=I=O=H===-4==m=A=DC=====::===:==::~===~_l_ _ _ _1

I IOL = 8 mA DC

U~

A/tera Corporation

I

I Data Sheet
AC Operating Conditions

IExternal Timing Parameters
I Symbol I Parameter
, t P01

I t P02
I t su

I tH

I teo.

I t ASU
I t AH
ItCH

I t CL
I tACH
I t ACL
, t AC01

I tCNT
' f CNT
, t ACNT

, f ACNT

I f MAX

,

EPM5192
See Note (3)

I Conditions

Input to non-registered output , C1

= 35

pF

I 110 input to non-reg. output I C1 = 35 pF

II

Setup time

Holdtime

I
I

Clock to output delay

I

1

5

I

1 Clock low time
Asynchronous clock high time
Asynchronous clock low time
Asynch. clock to output delay 'C1 = 35 pF

1
1
1
1
1

,

I

1 Minimumclockperiod

I

I

I

I

6
8
8
11
9

1

Internal maximum frequency I
1 Min. asynch. clock period
See Note (5)
Min. internal asynch. frequ.
'See Note (5)
Max. frequency; pipelined data 1

I

I

50

I,'

1
1

I

,I

,I

nnss

I
I

1-4 -'-6-,1-1-6-1':-8-',:~,1

nnss

,I

I

20
0

1

25

1 8
1 10
1 10
1 14
11
1

1

20

I

I
1
1

I

I

20

I:

I

50 1
1 62.5 1

I,'

40

1 30
45

I

I,:

I

1

I
1
I
I
I

25
25

1 40'
50

I
I

I
I
I

1

1 30

I,"

33.3

I,'

35
30

1 33.3 1
40

I

I

205

1 10 1
112.51
1 12.5 1
1 16
14

1 30

I,'

1

I

1 35
55

I

I

I I
I Unit I

I

I 1"

I Clock high time

25
40

1~05,'

I Asynchronous hold time

I

I

I~

Cl =35pF

I Asynchronous setup time

I

~192-1
EPM5192-2
EPM5192
I Min I~I~I Max I~I Max

I

I

1 ns
ns

I

1 ns
ns
ns
ns
ns
ns

I
1
I
I
I

,

I

I
1
,

I

1 ns
I,'

MnHs

Z
I,

1 MHz

I

I

I MHz I

For information on internal timing parameters, refer to App. Brief 75 (EPM5000-Series MAX EPLD Timing).

I Internal Timing Parameters
I Symbol I Parameter
I t IN

I Input pad and buffer delay

Conditions

, t EXP

,
1 110 input pad and buffer delay
1 Expanderarraydelay
1

, t LAD
, t LAC

1 logic array delay
1 logic control array delay

, t

10

ItH
I t IC
I tiCS
I t FD
I t PRE
I t CLR
I t PIA

Min

7

I

I
I

1

Register hold time

1

Clock delay
clock delay

,

Progr. Interconn. Array delay

IAltera Corporation

12
10

I
1

I

I l'

I

I

Feedback delay
Register preset time
Register clear time

EPM5192

I

'9'

I

I

I

I

I

I

I

I

I

I

I

I

I

1 ns

,

I

14 1
16
ns
1-1-2-'--1-1-3-I~

I

,
1 5
5
6
ns
,--,-1-0-'---'-1-1-1--'-1-3-I~
,
'10 '--1-1-1-1--1-1-3-'---;-1
, 6 1
1 8 1--'-1-0-'--1---;-1
1
1 3 1--1--4-1--1--4-I-n-s

I Combinatorial delay
System

EPM5192-2

1 5 1
1
1
ns ,
1 6 1
1 6
1 9
ns
1 12 1--1-1-4-1--I~I-n-s-'

I

I t OD I Output buffer and pad delay I C1 = 35 pF
I t zx 1 Output buffer enable delay'
I t xz , Output buffer disable delay 'C1 = 5 pF
I t su 1 Register setup time
I t LArCH 1 Flow-through latch delay
, t RD
I Register delay
, t COMB

I
I
Ii
IMax I Min IMax I Min I Max I Unit I

EPM5192-1

1

I
,
,
1

I
6

3

1

-I

I

'2
2
ns
1--4- 1 - - ' - - 4-,-n-s-,

1 8

1

1 10 1

1 14 1
1 16 1
' 1 8 ' ns ,
1 2 ' - - ' - - 2- 1 - - ' - - 3-,---;-,
1

I
I

I

1
5
5
14

I
I
I

I

I
I
1

I

I

I
I

7

I

I

1 20

I

1 1
6
6 1
16

1

2 1 ns
ns
7 1 ns
ns

Page 159

I
I
,

I

I

B

IEPM5192

Data Sheet

I

Notes to tables:
(1)

(2)
(3)

(4)
(5)

Minimum DC input is ~.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
Typical values are for TA =25° C and Vee =5 V.
Vee = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
Vee =5 V ± 10%, TA =-400 C to 85° C for ind ustrial use.
Vee = 5 V ±10%, TA = -550 C to 1250 C for military use.
Measured with device programmed as a 16-bit counter in each LAB.
This parameter is measured with a positive-edge-triggered clock at the register. For
negative-edge clocking, the tACH and tAcL parameters must be swapped.

Product Availability

Grade
Commercial

Availability
EPM5192-1, EPM5192-2, EPM5192

(0° C to 70° C)

Industrial

(-400 C to 85° C)

Military

(-55° C to 125° C)

I

Consult factory

I

I

Consult factory

Note: Only military-temperature-range EPLDs are listed here. MIL-STD-883-compliant
product specifications are provided in Military Product Drawings (MPDs), available from
Altera Marketing by calling 1 (800) SOS-EPLD. These MPDs should be used to prepare
Source Control Drawings (SCDs). See Military Products in this data book.

Table 3 shows the pin-outs for the EPM5192 PCA package.
Table 3. EPM5192 PGA Pin-Outs

Pin

Function

Pin

Function

Pin

Function

Pin

Function

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B2

110
110
I/O
I/O
Input
Input/ClK
GNO
I/O
110
I/O
110
I/O
110
I/O
I/O
VCC
I/O
GNO
I/O

C2
C5
C6
C7
C10
C11
01
02
010
011
E1
E2
E3
E9
E10
E11
F1
F2
F3
F9
F10
F11
G1

1/0
110
Input
Input
I/O
I/O
110
I/O
110
I/O
GNO
GNO
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

G2
G3
G9
G10
G11
H1
H2
H10
H11
J1
J2
J5
J6
J7
J10
J11
K1
K2
K3
K4
K5
K6
K7

VCC
1/0

K8
K9
K10
K11
L1
l2
l3
l4
l5
l6
l7
la
19
L10
L11

110
110
110
I/O
110

B3

B4
B5
B6

B7
B8

B9
B10
B11
C1

I Page 160

1/0

I/O
I/O
I/O

IJO

GNO
GNO
I/O
IJO

I/O
I/O
I/O
I/O
1/0

Input
Input
110
110
110
I/O

1/0

110
I/O
GND
110
Input
I/O
I/O
I/O
I/O

1/0
1/0

GNO
Input
vec
Altera Corporation

I

I Dsts Sheet

EPM5192!

Table 4 shows the pin-outs for the EPM5192 QFP package (n.c. indicates
"not connected").
Table 4. EPM5192 QFP PIn-Outs

I Altera Corporation

Pin

Function

Pin

Function

Pin

Function

Pin

Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

1/0
n.c.
n.c.
n.c.
1/0
1/0
110
1/0
1/0
1/0
1/0

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

1/0
1/0
n.c.
n.c.
n.c.
1/0
//0
1/0
1/0
1/0
1/0

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

1/0
n.c.
n.c.
n.c.
1/0
1/0
1/0
1/0

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

1/0
I/O
n.c.
n.c.
n.c.
I/O

GND
GND
1/0
1/0
1/0
1/0
n.c.
vee
1/0
1/0
1/0
1/0
1/0
I/O

GND
GND
Input
Input
Input
Input
vee
n.c.
1/0
1/0
1/0
1/0
1/0
I/O

110
1/0
1/0

GND
GND
1/0
1/0
1/0
1/0
n.c.
vee
1/0
1/0
1/0
1/0
1/0
I/O

110
1/0
1/0

110
1/0

GND
GND
Input
Input
Input/elK
Input
vee
n.c.
1/0

110
I/O
1/0
1/0
1/0

Psge 161

!

PLS-MAX
MAX+PLUS Programmable
Logic Software

I October 1990, ver. 2

Data Sheet I

o
o

Features

o
o

o
o
o
o
o

Software support for MAX (Multiple Array MatriX) EPLDs
Hierarchical design entry methods for both graphic and text designs
Multi-level schematics and hardware language descriptions
Over 340 7400-series ITL and bus macrofunctions optimized for
MAX architecture
Altera Hardware Description Language (AHDL) for state machines,
Boolean equations, truth tables, arithmetic and relational operations
Delay prediction and timing analysis for graphic and text designs
Logic synthesis and minimization for quick and efficient processing
Compiler that compiles a 100% utilized EPM5128 in only 10 minutes
Automatic error location for schematics and AHDL text files
Interactive Simulator with probe assignments for internal nodes
Waveform Editor for entering and editing waveforms and viewing
simulation results
Used with IBM PS/2, PC-AT, or compatible machines
EDIF industry-standard workstation and third-party interfaces available
separately

The Altera PLS-MAX (MAX+PLUS Programmable Logic Software) package,
shown in Figure 1, is a unified CAE system for designing logic with Altera's
MAX family of EPLDs. PLS-MAX includes design entry, design processing,
timing simulation, and device programming support. It runs on IBM PS/2,

General
Description

Figure 1. MAX~PLUS Design Framework
f·D~·~i~·~··E~t~····························l

j
ism~

Hierarchical

-!!o-..-.-......_

User-defined
symbols

Hierarchical
AHDLfiles,
including

Boolean
Equations,
State Machines,

.................................................
~ Design Verification

Truth Tables
A+PLUS files

-....................................................:

I A/tera Corporation

t .....................................................................................:

Page 1631

IPLS-MAX

Data Sheet

I

PC-AT, and compatible computers and provides sophisticated tools to
quickly and efficiently create and verify complex logic designs.
PLS-MAX is a software-only package. PLOS-MAX (MAX+PLUS
Programmable Logic Development System) includes PLS-MAX software,
all hardware required to program MAX EPLDs, and an extended software
warranty (see the PLDS-MAX Data Sheet in this data book).
Designs may be entered with a variety of design entry methods. MAX+PLUS
supports hierarchical entry of both Graphic Design Files (GOFs) with the
MAX+PLUS Graphic Editor, and Text Design Files (TOFs) in the Altera
Hardware Description Language (AHOL) with the MAX+PLUS Text Editor.
The Graphic Editor offers advanced features such as multiple hierarchy
levels, symbol editing, and an extensive library of 7400-series devices and
basic SSI gates. AHOL designs may be mixed into any level of the hierarchy
or used stand-alone. AHOL is tailored especially for EPLD designs and
includes support for complex Boolean and arithmetic functions, relational
comparisons, state machines with automatic state variable assignment,
truth tables, and function calls.
MAX+PLUSalso includes the sophisticated MAX+PLUSCompiler, which
synthesizes and optimizes designs in minutes. The Compiler uses advanced
logic synthesiS and minimization techniques together with heuristic fitting
rules to efficiently place designs into MAX EPLOs. The Compiler creates a
programming file that the MAX+PLUS Programmer uses to program
MAX EPLDs with standard Altera programming hardware.
Simulations are performed with a powerful, event-driven timing simulator.
The MAX+PLUS Simulator interactively displays timing results in the
MAX+PLUS Waveform Editor. Hardcopy table and waveform output is
available. With the Waveform Editor, input vector waveforms may be
entered, modified, grouped, and ungrouped. The Waveform Editor can
also compare simulation runs and highlight the differences between them.
MAX+PLUS also provides features such as automatic error location and
delay prediction. If a design contains an error in a schematic or an AHDL
text file, MAX +PLUS flags the error and takes the user to the location of the
error in the original schematic or text file. Propagation delays of critical
paths can also be determined from within both the Graphic and Text
Editors with the delay prediction feature. After the source and destination
nodes are tagged, the shortest and longest timing delays are calculated.
MAX +PLUS software provides a seamless design framework that uses a
consistent graphical user interface throughout. This framework simplifies
all stages of the design cycle: design entry, processing, verification, and
programming. In addition, MAX+PLUS offers extensive on-line help.

I Page 164

Altera Corporation

I

1

Data Sheet

Design Entry

PLS-MAX

1

MAX+PLUS offers both graphic and text design entry methods. GDFs are
entered with the MAX+PLUS Graphic Editor; Boolean equations, state
machines, and truth tables are entered in the Altera Hardware Description
Language (AHDL) with the MAX+PLUS Text Editor. The ability to freely
mix graphic and text files at all levels of the design hierarchy, and to use a
top-down or bottom-up design method, makes design entry simple and
versatile. As the designer traverses the hierarchy, the Text Editor is automatically invoked for text files, and the Graphic Editor is invoked for schematics.
Once the user saves a text or graphic file, the Graphic Editor automatically
generates a symbol for this file. This symbol, and the design it represents,
can then be used as a subdesign in a higher-level schematic or in another
design.
MAX+PLUS also accepts third-party netlists from OrCAD, Viewlogic
Systems, and Data I/O (ABEL, FutureNet-DASH), as well as existing
EPLD designs implemented with Altera's and Texas Instruments' A+PLUS,
and Intel's iPLDS or iPLDS II systems.

MAX+PLUS
Graphic
Editor

The MAX+PLUS Graphic Editor (Figure 2) provides a mouse-driven,
multi-windowed environment in which commands are entered with popup menus or simple keystrokes. The Hierarchy Display window lists all
schematics used in a design. The designer navigates the hierarchy by
placing the cursor on the name of the design to be opened and clicking a
mouse button. The Total View window shows the entire design. By clicking
inside this window, the main work window is moved to the corresponding
area of the schematic. The Error Report window lists all warnings and
errors in the compiled design; selecting an error with the mouse highlights
the problem node and symbol. A design is entered in the main work
window, which can be enlarged by closing the auxiliary windows.

Figure 2. MAX+PLUS Graphic Editor
The Graphic Editor provides a mUltiwindowed, menu-driven environment.
Auxiliary windows can be closed to
increase work space.

I Altera Corporation

p~~~~~~ ~:::: :~~u~:
~~:~~~~: ~ ~:~~T'

Page 1651

I PLS-MAX

Oats Sheet

I

When entering a design, the user can choose from a library of over 300
7400-series and special-purpose macrofunctions that are all optimized for
MAX architecture. In addition, the designer can create custom functions
that can be used in any MAX+PLUS design.
Tag-and-drag editing is used to move individual symbols or entire areas.
Lines stay connected with orthogonal rubberbanding. Designs are printed
on an Epson FX-compatible printer; HP7475A, 7485B, and 7495A plotters;
or a Houston Instruments 695-compatible plotter.

MAX+PLUS
Symbol
Editor

MAX+PLUS
AHDL

The MAX+PLUS Symbol Editor enables the designer to create or modify a
custom symbol representing a GDF or TOF. It is also possible to modify
input and output pin placement on an automatically generated symbol.
A symbol represents a lower-level deSign, described by a GDF or TDP. The
lower-level design can be displayed with a single command that invokes
the Graphic Editor for schematics or the Text Editor for AHDL designs.
The Altera Hardware Description Language (AHDL) is a high-level,
modular language used to create logic deSigns for MAX EPLDs. It is
completely integrated into MAX+PLUS, so AHDL files may be created,
edited, compiled, simulated, and programmed from within MAX+PLUS.
AHDL supports state machines, truth tables, and Boolean equations, as
well as arithmetic and relational operations. It is hierarchical, so that
frequently used functions such as TTL and bus macrofunctions can be
incorporated into a design. it also supports complex arithmetic and relational
operations-such as addition, subtraction, equality, and magnitude
comparisons-with the automatically generated logic functions. Standard
Boolean functions, including AND, OR, NAND, NOR, XOR, and XNOR
are also included. Groups are fully supported so operations can be
performed on groups as well as on single variables. AHDL also allows the
designer to specify the location of resources (e.g., latches, flip-flops, and
pins) within MAX EPLDs. Together, these features enable complex designs
to be implemented in a concise, high-level description (see Figure 3).

Figure 3. AHDL
(Part 1 of 2)
AHDL allows complex
arithmetic and relational
operators to be described
in a few lines.

Page 166

TITLE "Ti"ed Add and Co"pare function.";
DESIGH IS "add_c"p" DEUICE IS "EPH5128-2";
FUHCTIOH 74161 (LDH,A,B,C,D,EHT,EHP,CLRH,CLX) RETURNS (QA,QB,QC,QD,RCO);
SUBDESIGH add_c"p (
a£? .81,
b£? .81,

~

inputs for adder/co"parator

c"pen,
clock,reset

:IHPUT;

resulU7 •. 81.
ehpse[3 .. 8l.
ellual,
less_than,
grtr_thn,
done

: OUTPUT;

A/tera Corporation

I

Data Sheet

I

PL5-MAX

Figure 3. AHDL (Part 2 of 2)
VARIABLE
titter
regi ster£? . B]
flag

74161;

DFF;
ttODE;

Yo
Yo

titter is 74161 counter
register is an octal FF

Yo

set up accuftUlate register

BEGItt
result[]
register[];
register[].clrn = reset;
register[].clk = clock;
register[] = a[] + b[];
flag = (register[] != B);
done = flag;
titter.enp = cttpen & flag;
titter.clk = clock;
titter.clrn = reset;
Yo elapse is the nuttber of clock

Yo this is the actual addition

Yo

set flag high if register is not ettpt9 Yo

Yo

Yo connect inputs for titter (74161)

Yo

it takes to do add

c~cles

elapse[3 .• B] = (titter.QA.titter.QB.titter.QC.titter.QD);
e~ual = ( a[] == b[]);
Yo the cottparator section
less_than
(a[] < b[]);
grtr_than = (a[] > b[]);

EttD;

MAX+PLUS
Text Editor

The MAX+PLUS Text Editor, shown in Figure 4, enables the user to view
and edit text files within the MAX+PLUS environment. Any ASCII text
file, including AHDL Text Design Files (TOFs), Vector Files, Table Files,
and Report Files, may be viewed and edited in the Text Editor.
The Text Editor parallels the Graphic Editor's structure with Hierarchy
Display and Total View windows for moving through hierarchy levels and
around the design. It also provides automatic error location. If an error is
found in a TOF during compilation, the Text Editor is automatically
invoked and the line of AHDL code where the error occurred is highlighted.

Figure 4. MAX+PLUS Text Editor

E

W!!!£>. . .App"W pp ....r:

.~

•

The Text Editor and AHDL offer such
features as hierarchical design entry
and automatic e"or location.

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::::.

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.**.-•••••
** ••• -.-•• -.-•• - ••• --••••••••••••••
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FUNCTION

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(
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da~~'ny

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c l • ..r
oin,

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INPUT'
OUTPUT;

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X
X
X

Input .erl&l ~It. to
on r •• j~g edge

Y~lld
cl.~r
~lr.~

~
Added
~ clock
.hould ~. ~ ••• rt.d •• ~ar
bi~. are clocked
in X

~ ::~!:i~~,~::r~~r::~~ ::!~:~ :~

VARIABLE

IAltera Corporation

carry

NODE.

~ull

~ul1 .. dd'

Y. hald. current carry

X

tn.~anc.

D#

.~a~u.

.acra#unc~lon

X
#ul1add X

Page 1671

I PLS-MAX
Macrofunction
Library

Data Sheet

I

The MAX +PLUS TIL MacroFunction Library contains the most commonly
used 7400-series devices such as counters, decoders, encoders, shift registers,
flip-flops, latches, and multipliers, as well as special bus macrofunctions,
all of which increase design productivity. The flexible architecture of MAX
EPLDs (which includes asynchronous Preset and Clear) ensures that true
TIL device emulation is achieved. Altera has also created special-purpose
bus macrofunctions for designs that use buses. All macrofunctions have
been optimized to provide the best speed and part utilization. Table 1 lists
some of the macrofunctions currently available.

Table 1. Sampling of TTL MacroFunctions
TTL Macrofunctions:
Adders:
ALU:
AND-OR Gates:
Comparators:
Code Converters:
Counters:
Decoders:
Encoders:
Frequency Divider:
Latches:
Multipliers:
Multiplexers:
Parity Generators:
Registers:
Shift Registers:
SSI Gates:
Storage Elements:
True/Camp Elements:

8FADD, 7480, 7482, 7483, 74183,74283, 74385
74181,74182,74381,74382
7452
8MCOMP, 7485, 74518, 74684, 74686,74688
74184, 74185
4COUNT, acOUNT, 16CUDSLR, GRAY4, UNICNT, 7493, 74160,
74161,74162,74163,74190,74191,74192, 74193, 74393 ...
7442, 7443, 7444, 7445, 7446, 7447, 7448, 7449, 74138, 74139,
74154,74155,74156 ...
74147, 74148
FREQDIV, 7456, 7457
INPLTCH, NANDLTCH, NORLTCH, 7475, 7477, 74116, 74259,
74279, 74373 ...
MULT2, MULT4, MULT24, 74261...
21MUX, 74151, 74153, 74157, 74158,74298 ...
74180, 74280
7470,7471,7472,7473,7474,7476,7478,74173,74174,74175,
74178,74273,74374 ...
BARRELST, 7491, 7494 ,7496, 7499, 74164, 74165, 74166, 74179,
74194,74198 ...
CBUF, INHB, 7400, 7402, 7404, 7408, 7410, 7411, 7420, 7421,
7427, 7430, 7432, 7486 ...
7498, 74278
7487, 74265

Bus Macrofunctions:
Adder:
Buffers:
Comparators:
Counter:
Latches:
Multiplexers:
Multipliers:
Parity Generators:
Registers:
Shift Registers:

IPage 168

8FADDB
74240B,74241B,74244B
8MCOMPB, 74518B
16CUDSRB
74373B, 74841B, 74842B
74151B
MULT4B
74180B,74280
74174B, 74273B, 74374B, 74821 B, 74822B, 74823B, 74824B,
74825B,748268
BARRLSTB, 74164B, 74165B

A/tera Corporation

I Data Sheet
Design
Processing

PLS-MAX

I

The MAX+PLUS Compiler processes designs in minutes (see Figure 5). It
offers several options that speed the processing and analysis of a design.
For example, the user can specify the degree of detail of the Report File, as
well as the maximum number of errors to be detected before processing
halts. The user may also select whether to extract a netlist file for simulation.

Figure 5. MAX+PLUS Complier

---- .-a-.
ON

The Compiler uses minimization,
logic synthesis, and heuristic fitting
algorithms to place designs into
MAXEPLDs.

.
@ t

.. ..

..

..

18 ~®®

The Compiler compiles a design in increments. If a design has been
compiled previously, only the new portion is compiled to reduce
compilation time. This ''Make'' facility is an automatic feature of the
Compiler.
The first module of the Com piler, the Com piler Netlist Extractor, extracts a
netlist from each file. At this time, design rules are checked for any errors.
If errors are found, the Graphic Editor or Text Editor is invoked after the
compilation, depending on whether the error occurred in a GDF or TOF.
The Error Report window displays the error and its location. The Compiler
Netlist Extractor also generates a Hierarchy Interconnect File (HIF) that
describes the hierarchy of the total design. This information is used by the
Database Builder, which flattens the hierarchical deSign, examines design
logic, and checks for schematic boundary connectivity and syntax errors.
The Logic Synthesizer module translates and optimizes the user-defined
logic for the MAX architecture. The design is first minimized with SALSA
(Speedy Altera Logic Simplification Algorithm). Any unused logic is
automatically removed. This module uses expert system synthesis rules to
factor and map logic within the multi-level MAX architecture. It then
chooses the approach that ensures the most efficient use of silicon resources.

I A/tera Corporation

Page 1691

I PLS-AIAX

DafaSheef

I

The next module, the Fitter, uses heuristic rules to place the synthesized
design into the chosen MAX EPLD. For MAX devices with a Programmable
Interconnect Array (PIA), the Fitter also routes the signals across this
interconnect structure, so the designer doesn't have to worry about
placement and routing issues. The Fitter issues a Report File (.RPT) that
shows how the design is implemented and which resources in the EPLD
are unused. The designer can then determine how much additional logic
may be placed in the EPLD.
Next, the Simulator Netlist Extractor optionally generates a Simulator
Netlist File (.SNF) that is used to perform timing simulation. Finally, the
Assembler creates a Programmer Object File (.POF) from the compiled
design that is used by the MAX+PLUS Programmer to program the target
EPLD.
The advanced synthesis and minimization techniques employed by the
Compiler allow designs to be placed within the MAX architecture in a
matter of minutes. For example, a 16-bit counter I shift register compiles in
less than 1 minute on a 16-MHz 386-based PC. The Compiler is equally
efficient when compiling complex designs. For example, 5 serially linked
multiplier ladder circuits that use 100% of the macrocells and 95% of all
expanders in an EPM5128 take only 10 minutes to compile on a 20-MHz
386-based PC.

Delay
Prediction
and Probes

MAX+PLUS includes powerful analysis tools to verify and analyze the
completed design. Delay prediction is performed interactively in the
Graphic Editor, Text Editor, or Simulator.
The delay prediction feature provides instant feedback on the timing of the
processed design. After selecting the start point and end point of a path,
the designer may determine the shortest and longest propagation delays of
speed-critical paths.
In addition, the designer can use probes to mark internal nodes in a design.
A probe is entered in a Graphic Editor schematic by selecting any node,
entering a command, and then assigning a unique name to define the
probe. This name is then used in the Graphic Editor, Simulator, and
Waveform Editor to identify the node.

MAX+PLUS
Simulator

The designer defines input stimuli with a straightforward vector input
language, or draws waveforms directly in the Waveform Editor.
The Simulator uses the Simulator Netlist File (SNF) extracted from the
compiled design to perform timing simulation with O.l-ns resolution.
Simulator commands are provided to halt the simulation based on userdefined conditions; to force and group nodes; and to detect glitches, setup
and hold violations, and unwanted oscillation. For example, if flip-flop

IPage 170

Altera Corporation

I

Data Sheet

PL5-MAXI

setup or hold times have been violated, the Simulator warns the user. Or, if
a pulse is shorter than the minimum pulse width specified, or if a node
oscillates for longer than the specified time, the Simulator issues a warning.
A Command File is used for batch operation, or commands may be entered
interactively.

MAX+PLUS
Waveform
Editor

The MAX +PLUS Waveform Editor, shown in Figure 6, provides a mousedriven environment for editing and viewing waveforms. It functions as a
logic analyzer, enabling the user to observe simulation results. Simulated
waveforms can be viewed and manipulated at multiple zoom levels.
Nodes can be added, deleted, and combined into buses. Buses can contain
up to 32 signals that are represented in binary, octal, decimal, or hexadecimal
format. Logical operators can also be used on pairs of waveforms, so that
waveforms can be inverted, ORed, ANDed, or XORed together.

Figure 6. MAX+PLUS Waveform Editor
With the Waveform Editor, input stimuli can
be entered and modified, and Simulator
outputs can be viewed and compared.

LEFT

I

RIGHT

I

FLASH
KIOHT-fUU'
0
L-R-DRI(-OR
RIGHT-O
0
o
RIGHT-H
RIOHT-I
o
LEFT-ORP
LEFT-I
o
LEFT-H
0
LEFT-D
IGN-LITE
0

I Altera Corporation

,.,.22..." :

6.229us

IONITIDN

·
·
·
·

..

~ I]

.. i· .-1- ... ~.l.~~~~~':1!".'! . ~~.~~ . ~·~~1!'~ .~~.-:~ -: ....
I

I

I

•
•

•

·,.

Page 1711

I PLS-MAX

Oats Sheet

I

The Waveform Editor includes sophisticated editing features to define and
modify input vectors. The designer uses the mouse and familiar commands
to create and copy waveforms, to repeat waveform patterns, and to move
and copy blocks of waveforms. For example, all or part of a waveform can
be compressed to simulate an increase in clock frequency.
The Waveform Editor can also compare and highlight the differences
between two different simulations. A user can simulate a design, observe
and edit the results, and then resimulate the design; the Waveform Editor
can then show the results superimposed on each other to highlight their
differences.

Device
Programming

PLS-MAX contains the MAX+PLUS Programmer software for programming
and verifying the MAX-family EPLDs. (Programming hardware and several
device adapters are provided with PLDS-MAX. See the PLDS-MAX Data
Sheet in this da ta book for details.) The MAX +PLUS programming software
drives the PC-AT or PS/2 add-on card and uses standard Altera
programming hardware. If the Security Bit of the device is off, the designer
can also read the contents of a MAX device and use this information to
program addi tional EPLDs.

MAX+PLUS

The MAX+PLUS Timing Analyzer (MTA) provides user-configurable
reports that help the designer to analyze critical delay paths, setup and
hold times, and overall system performance of any MAX EPLD design.
Critical paths identified by these reports can be displayed and highlighted.

Timing
Analyzer
(MTA)

The MTA calculates timing delays between multiple source and destination
nodes and creates a connection matrix that gives the shortest and longest
delay paths between all specified source and destination nodes (Figure 7).
The MTA also displays the detailed paths and delays between specified
sources and destinations.
The setup/hold option provides information on setup and hold
requirements at the device pins for all pins that feed the D, eLI, or ENABLE
inputs of flip-flops and latches. Critical source nodes can be specified
individually, or for all pins can be calculated. This information is then
displayed in a table with one set of setup and hold times per flip-flop or
latch.
The MTA also allows the user to print a com plete list of all accessible nodes
in a design, i.e., all nodes that can be displayed during simulation or delay
prediction.
All MTA functions can be executed in batch mode with an MTA command
file, so the user can specify all information needed to configure the output.

IPage 172

Altera Corporation

I

I Oats ShfHIt

I

PLS-MAX

Rgure 7. Delay Analysis Matrix
HAX+PLUS Ii"in,
Desi,n
Anal~sis

Anal~zer

Uersion 2.5

5/11/9.

PIge 1

: C: 'HAX_UORK'COU"TER
: Deh~ "atrix
Destination
out1
out2
out3
----------+-----------------------------------------+
inpl
28.'
15.' / 24.'
18.' / 46.'

Source

1
1
1
1
----------1-----------------------------------------1

--~~~---j!--;;:;----;-~;:;-;-;~-~~~:~~~~:!-i

::~~~::::j~~-::J ---f-::::::::-:-:::::::-::::-- I-----.
are not connected.
One number at an intersection
indicates that the two nodes
are connected by one path.

SNF2GDF
Converter

Two numbers at an intersection
indicate that the two nodes are
connected by roore than one path;
these numbers show the shortest and
the longest delay path.

The Simulator Netlist File-to-Graphic Design File (SNF2GDF) Converter
converts the MAX+PLUSSimulator Netlist File (SNF) into logic schematics
that contain basic gates and flip-flop elements. It uses the SNF's delay and
connection information to create a series of schematics that are fully
annotated with propagation delay and setup and hold information at each
logic gate. Certain speed paths of a design can be specified for conversion,
so the user can graphically analyze only those paths that are considered
critical. See Figures 8 and 9.
If the Altera Hardware Description Language (AHDL) is used, SNF2GDF
shows how the high-level description has been synthesized and placed
into the MAX architecture.

PLS-MAX
Contents
Ordering
Information

I Altera Corporation

o

o

Floppy disks containing all programs and files for MAX+PLUS
software for both PC-AT and PS/2 and compatible computers
Documentation

PLS-MAX

(supports both PC-AT and PS/2 formats)

Refer to the PC System Requirements Data Sheet in this data book for
information on system requirements and sample system configurations.

Page 173

I

PLS-MAX

Data Sheet I

Figure 8. Original Schematic File

:dRAKE: ....... · ......T

I

Figure 9. Schematic Converted and Annotated with SNF2GDF
This screen capture shows the schematic
for the compiled and converted
design, which displays delay information
and the results of logic synthesis.

~~~~(: . . . . . . . W. . . UT·

I Page 174

UIIZ 'liZHZ1

Altera Corporation

Contents
I Octobsr 1990
Section 4

EPM7000-Series MAX EPLDs
EPM7000-Series: High-Performance, High-Pin-Count MAX EPLDs ...... 177

1 A/tera

Corporation

Page 1751

EPM7000·Series Devices
High-Performance,
High-Pin-Count MAX EPLDs
Data Sheet I

October 1990, ver. 1

Features

o
o
o
o

Advance
Information

o
o
o
o
o
o
o

o

o
General
Description

A/tera Corporation

High-density, high-speed CMOS EPLDs with second-generation
Multiple Array MatriX (MAX) architecture
Advanced 0.8-micron double-metal CMOS EPROM technology
Complete EPLD series ranging from 1,500 to 20,000 gates
Fast, 15-ns pin-ta-pin logic delays with 70-MHz true system-clock
frequency (including interconnect)
Programmable "power saver" mode
44 to 208 pins available in PLCC, PGA, and QFP packages
User-defined I/O options for support of bus-interface functions
Enhanced Programmable Interconnect Array (PIA) that provides a
fixed delay from any internal source to any destination within the
EPLD
Advanced macrocell to efficiently place logic for optimum speed and
density
Programmable registers providing D, T, JK, or SR flip-flops with
individual Clear, Preset, and Clock controls
High pin-ta-Iogic ratio for I/O-intensive data path applications and
32-bit microprocessor support logic
Full software support for PC and workstation platforms (including
Apollo, Sun, and IBM) with Altera's software development
systems
Hierarchical schematic capture with over 340 TIL and custom
macro functions
Altera Hardware Description Language (AHDL) for Boolean
equation, state machine, and truth table design entry
Waveform entry
Logic synthesis and minimization
Device fitting within minutes
Full timing simulation
Automatic multi-chip partitioning and simulation
EDIF netlist interface for additional schematic capture and simulation
support

The EPM7000 series-Altera's next generation of erasable, high-density,
high-performance MAX EPLDs-provides a variety of solutions for generalpurpose logic integration. Ranging in gate density from 1,500 to 20,000
gates and supplied in packages from 44 to over 250 pins, the EPM7000
series offers up to 4 times the logic density and more than 3 times the
system clock speed of Field Programmable Gate Arrays (FPGAs). See
Figure 1.
Page 1771

n
11.1

I EPM700O-Series Devices

Data Sheet

I

Rgure 1. EPM7000-Serles EPLDs

300
•

•
•

200

Pins

•

100

EPM7025
•
•
•

•

•

EPM7200

EPM7150

EPM7100

EPM7075

EPM7050

EPM7040

EPM7020

EPM7015

5

10

15

20

Gat. Density
(In thousands)

EPM7000-series MAX EPLDs are based on a logic matrix architecture that
consist of modular Logic Array Blocks (LABs) connected with a
Programmable Interconnect Array (PIA). See Figure 2. The PIA provides a
connection path with a small fixed delay between all internal signal sources
and logic destinations. It has been carefully optimized so that device
performance can be accurately predicted early in the design phase, and
speed penalties for design changes can be avoided.
Macrocells within the LAB are optimized for efficient placement of logic
resources on the basis of speed and density requirements. These enhanced
macrocells support both combina torial and regis tered functions and allow
100% TTL emulation. Register options (D, T, JK, SR) and programmable
Clock control may be individually configured for each macrocell. The
EPM7000-series macrocell, together with a fast PIA, provides true system
clock rates of 70+ MHz, even with complex logic functions.
Logic designs are implemented in EPM7000-series EPLDs with Altera's
PC- and workstation-based development systems. Designs can be entered
using hierarchical schematic capture with TTL macrofunctions, as well as
using Boolean equations and state machines with the Altera Hardware
Description Language (AHDL). Waveform design entry is also supported.
Interfaces to third-party tools are available to allow design entry and logic
simulation on a variety of workstation platforms.

IPage 178

Altera Corporation

I

I Data Sheet

EPM7000-Series Devices I

Figure 2. EPM7000-Series Block Diagram

VO Control Block

,

Enhanced
macrocell
provides efficien t
placement of logic
for optimum
..........
speed and
density.

LAB

~
I/O
Control
Block

1-

--

r---

-+-

004-

-..

-..

LAB

LAB

!4-

~

004-

-..

-..

LAB

H

"

~
LAB

f4-

4-

~

~

LAB

LAB

-

f4-

0+-

----

~

LAB

V

V
VO
Control
Block

PIApr'OVides
fixeddelays
betweenail
logie
resou roes.

no.

LAB

f4f--

f4-

~

I
LAB

ILAB

va

T

LAB

t
LAB

Medium to
very high
count meets a
wide range 0 f
application
needs.

f4f--

H

-- ---

-+-

40-

LAB

LAB

T/~

~oControl Block

4-

----

EachL AB
/allows full
emulatian of
TTLfunetions.

I

-4-

T

\

LAB
"-----

·Coast toeoast"
logiedelays are
only 15 ns,
inc/udin9
interconnect.

~
EPM7000-series MAX
EPLDs have an
expandable, modular
architecture, from
1,500 to 20,000 gates.

A powerful compiler minImizes and synthesizes the design, then
automatically fits it into the most appropriate EPLD. If the design is too
large, the compiler automatically partitions the logic into two or more
EPLDs. The design may be verified with an integrated simulator, a full AC
timing simulator, and with an interactive waveform editor that speeds
waveform creation and debugging. Since the design is processed in minutes,
several iterations can be completed in a single day.

IAltera Corporation

Page 179

II

Notes:

Contents
I October 1990
Section 5

EPS-Series SAM & STG EPLDs
EPS-Series EPLDs: Synchronous State Machine & Waveform
Generation EPLDs .......................................................................... 183
EPS448 SAM EPLD: Stand-Alone Microsequencer .................................... 185
EPS464 STG EPLD: Synchronous Timing Generator ................................. 203
PLS-SAM: SAM +PLUS Programmable Logic Software ............................ 207

IAltera Corporation

Page 181 I

EPS-Series
EPLDs

SYSTEM
CLOCK RATE

(MHz)

50

Synchronous State Machine and
Waveform Generation EPLDs

.& EPS464 (STG)

-

.& EPS448 (SAM)

30 -

--

2~
USER 1/0

EPS448: Stand-Alone Microsequencer

EPS464: Synchronous Timing Generator

o

Provides efficient solutions for state
machines, bus- and memory-control
functions, graphics, and DSP algorithm
controllers.

o

Generates complex control timing
waveforms for all types of imaging
applications (CCDimagers, video displays,
optical disks, etc.).

o

On-chip reprogrammable microcode
EPROM up to 448 words deep
Prioritized, multi way branch control

o

Programmable architecture implements
NTSC, PAL, and SECAM synchronization
standards for TV/ video applications.
Powerful macrocell structure supports
complex waveform and state machine
designs.

o

o

15 x 8 stack for implementing
subrou tines, nested loops, branch control,
and other iterative functions

o

8-bit loop counter for timing and delay
loops

o
o
o
o

o
o

Programmable I/O supports up to 36
inputs and 32 outputs.

3D-MHz clock frequency

o

28-pin, 300-mil DIP or JLCC/PLCC
package
Vertically and horizontall y cascadable

"Quiet" outputs minimize output switching
noise.

o
o

SAM+PLUS development software:

o

50-MHz clock frequency
44-pin JLCC/PLCC or 44-pin plastic QFP
package options
Advanced development software support:

Altera State Machine
Language (ASMILE)

Input

Assembly Language (ASM)
SAM Design Processor (SDP)

Waveform design entry
Logic syntheSiS
Timing simulator

Functional Simulator (SAMSIM)

IA/tera Corporation

Page 183

I

EPS448 SAM EPLD
Stand-Alone Microsequencer

I October 1990, ver. 2

Data Sheet

o

Features

o
o
o
o
o
o

o
o

o
o

o

User-configurable ::>tand-Alone Microsequencer (SAM) for
implementing high-performance controllers
On-chip reprogram mabie microcode EPROM up to 448 words deep
15 x 8-bit stack
Loop counter
Prioritized multiway control branching
8 general-purpose branch-control inputs
16 general-purpose control outputs
Cascadable to expand the number of outputs or states
Low-power CMOS technology
Footprint-efficient packages: 28-pin, 3OO-mil DIP or JLCC/PLCC
30-MHz clock frequency
High-level software support with SAM+PLUS Development System:
Altera State Machine Input Language (ASMILE)
Assembly Language (ASM)
SAM Design Processor (SDP)
SAMSIM functional simulator

The EPS448 EPLD is a function-specific, user-configurable stand-alone
microsequencer (SAM). The on-chip EPROM of each EPS448 device (up to
448 words) is integrated with branch-control lOgic, a pipeline register, a
stack, and a loop counter. This generic microccxied architecture can
efficiently implement a broad range of high-performance controllers, from
state machines to waveform-generation applications.

General
Description

Figure 1. EPS448 Pin-Out Diagrams
Iii
ffl
!l!

!2

'Iii

~

C,)

~

d

F14

~

F13

!!!

F12
4
11

2

3

1

28

27

26

Fl1

16

5

F10
17

FOt

8

F02

9

F03

10

F04

11

0

21

FOg

elK

F15

F08

F14

GND

F13

F07

F12

EPS448

F11
12
It)

~

13

~
u..

14
f"-

0

u..

15
0

z

G

16
00
0

u..

J-Lead

I A/tera Corporation

I

17

g

u..

18
0

u::

F01

DIP

The EPS448 EPLD is available in
28-pin, 3OO-mil windowed ceramic
dual in-line packages (DIPs) and
in 28-pin ceramic J-Iead chip
carriers OLCCs). One-timeprogrammable plastic J-Iead
(PLCC) versions of the EPS448
EPLD are also available for volume
production. See Figure 1.
The 1.2-micron CMOS EPROM
technology allows the EPS448
EPLD to operate at 3D-MHz clock
frequency while still benefitting
from low CMOS power consumption. This technology also
Page 1851

n
a

I EPS448 SAM EPLD: Stand-Alone Microsequencer

Data Sheet

I

facilitates 100% generic testability, which eliminates the need for postprogramming testing.
Altera's SAM+PLUS software provides design entry, logic optimization
and functional simulation for EPS448 designs. With SAM+PLUS, designs
are entered in either state machine or microcoded format. The software
automatically performs logic minimization and design fitting. The design
can then simulate the design or program it directly to create customized
working silicon. Programming takes only a few minutes with standard
Altera programming hardware, LogicMap II software, and a PLED448 or
PLEJ448 adapter. New users can purchase the complete PLDS-SAM
Development System with programming hardware included; PLS-SAM is
a software-only package for existing Altera systems.

Applications

Ideal EPS448 applications include programmable sequence generators
(Le., state machines), bus and memory control functions, graphicS and DSP
algorithm controllers, and other high-performance control logic. EPS448
devices can be cascaded horizontally for greater output capabilities and
vertically for deeper microcode memory. See Application Brief 65 (Vertical
Cascading of EPS448 SAM EPLDs) in this data book for more information.

EPS448 as a State Machi ne
EPS448 architecture easily implements synchronous state machines. The
device's internal EPROM memory and pipeline register allow up to 448
unique states to be specified. Its branch-control logic allows single-clock,
multiway branching based on the 8 inputs, the current device state, and the
user-defined transition conditions. Design entry is simplified with the
Altera State Machine Input Language (ASMILE) supported by SAM+PLUS
software. This high-level language uses IF-THEN statements to define state
transitions and truth tables to define or tri-state the outputs on a state-bystate basis.

EPS448 as a Microcoded Controller
EPS448 architecture provides several advanced features that make the
device suitable for use as a complex microcoded controller. The EPS448
EPLD's 448-word on-chip EPROM is integrated with a microcode sequencer
consisting of branch-control logic, a stack, and a loop counter. The branchcontrol logic-fed by the 8 general-purpose inputs, the counter, the stack,
and the pipeline register-provides flexible, multi way microcode branch
capability in a single clock, enhancing throughput beyond that of
conventional controllers or sequencers.
For microcoded controllers, SAM+PLUS software offers the high-level
Assembly Language (ASM) design entry format. This language consists of
powerful instructions (i.e., opcodes) that easily implement conditional

IPage 186

Altera Corporation

I

I Data Sheet

EPS448 SAM EPLD: Stand-Alone Microsequencer

I

branches, subroutine calls, multi-level FOR-NEXT loops, and dispatch
functions (Le., branching to an externally specified address). For more
information, see "Instruction Set" later in this data sheet.

Functional
Description

As shown in Figure 2, the EPS448 EPLD consists of microcode EPROM, a
36-bit pipeline register, branch-controllogic, a 15 x 8-bit stack, and an 8-bit
loop counter.
The branch-control logic generates the address of the next state and applies
it to the microcode memory. The outputs of the microcode memory
represent user-defined outputs and internal control values associated with
the next state. These new values are clocked into the pipeline register on
the leading edge of the clock and become the current state. The new values
in the pipeline register-along with the counter, stack, and inputs-are
used by the branch-control logic to generate the new next-state address.
Figure 2. EPS448 Block Diagram
Clock

Reset

Inputs
(10 to 17)

Outputs
(FO to F15)

I Altera Corporation

Page 1871

[EPS448 SAM EPLD: Stand·Alone MicrosequenctN

Data Sheet

I

Microcode EPROM and Pipeline Register
The microcode EPROM is organized into 448 36-bit words, each of which
can be viewed as a single state location. Each of the 36 bits is divided into
the following categories:
F-field (16 bits)
Q-field (8 bits)
D-field (8 bits)

consists of user-defined outputs at device pins.
provides the next-state address.
is a general-purpose field used either as a constant or as
an alternative next-state address.
OP-field (3 bits) contains the instruction (opcode).
E-field (1 bit)
enables or tri-states the device outputs.

As shown in Figure 3, the microcode memory is organized as 255 addresses.
Addresses 0 through 191 contain a single 36-bit word, which is associated
with the desired next state. This state information is clocked into the
pipeline register on the rising edge of the clock, and the outputs become
valid one clock-to-output delay (teo) later.
Addresses 192 through 255 access 4 unique 36-bit words, each of which
corresponds to a different possible next state. (The extensions .0, .1, .2, and
.3 are added to the addresses to distinguish the four states.) These 64
addresses make up the multiway branch locations, and are used to perform
single-clock, four-way branching. Whenever the next-state address falls
within the multi way branch locations, the branch-control logic makes the
necessary l-of-4 selection based on the next-state address and user-defined
input conditions.
Figure 3. Microcode Memory and Pipeline Register
Address

Next·State
Address
from Branch
Control

8 --,.--

4
1-of-4
Branch Select
from Branch
Control

I Page 188

Clock----

A/tera Corporation

I

I Data Sheet

EPS448 SAM EPLD: Stand-Alone Microsequencer

1

Branch-Control Logic Block
The branch-control logic is the key to the high-performance sequencing
ability of the EPS448 EPLD. This block determines the next state to be
clocked into the pipeline register, based on the current status of the pipeline
register, the counter, the stack, and the eight input pins.
The branch-control lOgic is divided into two segments: the address
multiplexer and the branch-select logic. See Figure 4.

Figure 4. Branch-Control Logic

Zero Rag
from Counter

Opcode
3

Top-of-Stack
8

Inputs (10-17)
8

The address multiplexer provides the next-state address to the microcode
memory. The next-state address can come from the Q-field, the D-field, or
the top-of-stack. The selection is based on the instruction in the pipeline
register and the condition of the zero flag from the counter.
The branch-select logic is a programmable logic block with 768 product
terms, 16 inputs, and 4 outputs. It is used to perform a 2-, 3-, or 4-way
branch based on user-defined input conditions. When the next-state address
falls within the multiway branch range of memory-i.e., any address
greater than 191-the branch-select logic performs the necessary l-of-4
selection. When the next-state address is less than 192, no selection is
required and the branch-select logic is turned off.

I Altera Corporation

Page 1891

I EPS448 SAM EPLD: Stand-Alone Microsequencer

Data Sheet

I

The conditions controlling the multiway branch are defined by the user
with a simple IF-THEtt-ELSE format, as shown in the following example:

IF
ELSEIF
ELSEIF
ELSE

THEN
THEN
THEN

(cond3)
(cond2)
(cond1)

select
select
select
select

281.3
281.2
281.1
281.8

The conditions are prioritized so that if the first condition (Le., cond3) is met,
then microword 281.3 is selected and clocked into the pipeline register,
regardless of the results of cond2 and cond1.1f none of the conditions is
met, then microword 281.8 is clocked into the pipeline register.
The three conditional expressions are user-defined. They may contain any
logical equation that is based on the inputs and can be reduced to four
product terms, as shown in the following example:
11 .. /12 .. /14
.. /14 .. /15 .. /16 .. /17

+ 13
+ 18
+ 12

.. /14 .. /15

A unique set of 12 product terms is present in each of the 64 available
multiway branch locations for a total of 768 product terms. See Figure 5.
Figure 5. Branch Logic in a Multiway Branch Location
Programmable Logic

Priority Encoder

D

8
8
8D
D

~A

~V'I

(~

10

11

12

(~

~V'I

(f\

(V'I

13
14
Inputs

15

16

17

~A

3
30
0

Select .3

Select .2

Select .1

.-~

Select .0

IPage 190

~
Altera Corporation

EPS448 SAM EPLD: Stand-Alone Aficrosequencer 1

Data Sheet

The EPS448 EPLD is designed so that the number of available product
terms is always sufficient for a design. Prioritization provides an effective
product-term count of more than 12 per location. A tradeoff between the
number of product terms and the number of possible branches can be
made simply by placing identical state information in 2 locations, as
shown in Figure 6.
Figure 6. Multiway Branching vs. Product-Term Needs
4-Way Branch

3-Way Branch

Stack
The EPS448 stack is a Last-In First-Out (LIFO) arrangement that consists of
15 8-bit words. The top of stack may be used as the next-state address or
popped into the counter. Values may be pushed onto the stack from either
the D-field in the pipeline register or from the counter. Thus subroutines,
nested loops, and other iterati ve structures may be efficiently im plemented.
The logic levels on the 8 dedicated input pins may also be pushed onto the
stack to allow external address specification in a dispatch function or to
externally load the counter. See Figure 7.
The pushing or popping of the stack occurs on the leading edge of the
clock. The stack is "zero-filled" so that a pop from an empty stack will reset
all 8 bits to zero. On the other hand, a push to an alread y full stack will
write over the top-of-stack, leaving the other 14 values unchanged.
Figure 7. Stack
from dedicated input pins,
D-field, or counter

I Altera Corporation

8

===:;,

to counter or
microcode memory

Page 1911

Ii

I EPS448 SAM EPLD: Stand-Alone Aficrosequencer

Data

Shf;!j

Loop Counter
The EPS448 EPLD contains an eight-bit loop counter called count register
(CREG), which is useful for controlling timing loops and determining
branch.

Vee =5.0V

TA

I-

<"
~

25° C

ci

.§.
C

=

80

~
Vee = 5.0 V
Room Temp.

60

:5

()

S0S

40

0

20

.§.
Q)

«~
0
0

0

70mA

<"

SOmA

3OmAa...-__........____-'-____..L.._ _ _ _' - -_ _...............
0.45

1

2

Vo OUtput Voltage (V)

I Altera Corporation

100 Hz

1 KHz

10 KHz

100 KHz

1 MHz

10 MHz 30 MHz

Maximum Frequency

Page 199

I

EPS448 SAM EPLD: Stand-Alone Microsequencer

Data Sheet

I

Absolute Maximum Ratings Note: See Operating Requirements for EPLDs in this data book.

Symbol

Parameter

Conditions

Min

Max

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

V

Vpp

Programming supply voltage

See Note (1)

-2.0

14.0

V

V,

DC input voltage

-2.0

7.0

V

I MAX

DC V ee or GND current

-250

+250

mA

lour

DC output current, per pin

-25

Po

Power dissipation

+25

mA

1200

mW

TSTG

Storage temperature

No bias

~5

+150

DC

T AMB

Ambient temperature

Under bias

-10

+85

DC

Min

Max

Unit

Recommended Operating Conditions

Symbol

Conditions

Parameter

vee

Supply voltage

4.75 (4.5)

5.25 (5.5)

V

V,

Input voltage

0

Vee

V

Vo

Output voltage

0

Vee

V

See Note (2)

TA

Operating temperature

For commercial use

0

70

DC

TA

Operating temperature

For industrial use

-40

85

DC

Te

Case temperature

For military use

-55

125

DC

tR
tF

Input rise time

500 (100)

ns

Input fall time

500 (100)

ns

DC Operating Conditions See Note (2)
Vee = 5 V ± 5%, T A = 0° C to 70° C for commercial use
Vee = 5 V ± 10%, TA = -40° C to 85° C for industrial use
Vee = 5 V ± 10%, Te = -550 C to 1250 C for military use

Symbol

Parameter

Max

Unit

V1H

High-level input voltage

2.0

V CC +0.3

V

V IL

low-level input voltage

-0.3

0.8

V

VOH

High-level TIL output voltage

IOH=-8mADC

2.4

V OH

High-level CMOS output voltage

IOH=-4mADC

3.84

VOL

low-level output voltage

I OL = 8 (4) mA DC

I,

Input leakage current

V I = Vee or GND, Note (3)

loz

Tri-state output off-state current

V o=V CC or GND

ICC1

V CC supply current (standby)

V I=V CC or GND,
See Note (4), Note (5)

I CC3

V CC supply current (active)

No load, 50% duty cycle,
f = 20 MHz, See Note (4)

I Page200

Conditions

Min

Typ

V
V
0.45

V

-10

+10

-10

+10

JlA
JlA

60

95 (120)

mA

90

140 (200)

mA

A/tera Corporation

I

IData Sheet
Capacitance

I

EPS448 SAM EPLD: Stand-Alone Microsequencer
See Note (6)

Symbol

Max

Unit

CIN

Input capacitance

Parameter

V IN =0 V, f = 1.0 MHz

Conditions

Min

10

pF

COUT

Output capacitance

V OUT = 0 V, f = 1.0 MHz

1S

pF

CCLK

Clock pin capacitance

V IN =0 V, f = 1.0 MHz

10

pF

CRST

nRESET pin capacitance

7S

pF

AC Operating Conditions
vcc = 5 V ± 5%, T A = 0° C to 70° C for commercial use
Vee = 5 V ± 10%, TA = -40° C to 85° C for industrial use
Vcc

= 5 V ± 10%, Tc = -55° C to 125° C for military use

EPS44B·30

Symbol
f CYC

Parameter
Maximum frequency

Conditions

Min

=35 pF

30

C1

t CYC

Maximum clock cycle

ts

Input setup time

Max

EPS448·25

Min

40

33.3

Input hold time

tco

Clock to output delay

t cz

Clock to output disable or enable

t CL

Minimum clock low time

0
16.5

ns
ns
ns

0
22

20
12

Unit
MHz

50

20

16.5
11

Max

22

20

0
C1 =35pF

Min
20

25

16.5

tH

Max

EPS448·20

22

ns
ns

15

ns

t CH

Minimum clock high time

11

12

15

ns

t SUR

nRESET setup time

16.5

18

18

ns

t HR

nRESET hold time

5

5

5

ns

Notes to tables:
Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0
V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
(2) Numbers in parentheses are for military and industrial temperature versions.
(3) For 1.0 < VI < 3.8, the nRESET pin will source up to 200 J1A.
(4) Typical values are for TA =25° C, Vee =5 V.
(5) This condition applies when the present state is a single-way branch location.
(6) Capacitance is measured at 25° C. Sample-tested only.
(1)

Product Availability
Grade

Availability

Commercial

(0 0 C to 700 C)

Industrial

(-40 0 C to 850 C)

EPS448-20

Military

(-55 C to 125 C)

EPS448-20

0

EPS448-3O, EPS448-25, EPS448-20

0

Note: Only military temperature-range EPLDs are listed above. MIL-STD-883B-compliant
product specifications are provided in Military Product Drawings (MPDs), available from
Altera Marketing at 1 (800) SOS-EPLD. These MPDs should be used to prepare Source
Control Drawings (SCDs). See Military Products in this data book.

I Altera Corporation

Page2D1

I

EPS448 SAM EPLD: Stand-Alone Mlcrosequencer

Data Sheet

I

Figure 13 shows EPS448 timing and reset timing waveforms.

Figure 13. EPS448 Waveforms
If nRESET is held /ow for more than three clock edges, then the outputs associated with the boot
address (00 Hex) will remain at the pins until the third clock after nRESET goes high.

Timing Waveforms
:_

t F --+1

Clock
Input 10 to 17

tCYC

*- t Cl ---.:

.:

;...- t CH

~

4 .

~tsu~

~. Valid Input;

tR~

----i

~tH

j...-

\-----i'l-:.i.·-----..L

)(,--.------+------

?-tco~

Output FO to F15 -

--+:_----J~

!

____

r-""'-_tcz_-..c-l~

_ _ _ _ _ _...

Output FO to F15

High-Impedance

.

Mr--lttez~--.iC·i

Trl-State

Reset Timing Waveforms
Clock

---! 1-- ts~

~

1-- tlfl

nRESET \~~_ _ _ _~~i'--~----~-too-i

Output FO to F15

r-

~"----ln-va-Iid-O-ut-P-u-t---:.,X

"

Page 202

too ---eo1
F (00)

!

C1--

Counter and stack cleared

Altera Corporation

I

EPS464 STG EPLD
Synchronous Timing Generator

I October 1990, ver. 1
Features

Data Sheet I

o
o

Advance
Information

o
o

o
o

o

o

o

High-performance Synchronous Timing Generator (STG) EPLD is
ideally suited for custom waveform and state machine designs.
Generates complex control timing waveforms for all typesofimaging
and display applications: CCO imagers, video displays, optical disks.
Programmable architecture implements NTSC, PAL, and SECAM
synchronization standards for TV/video applications.
High-performance 50-MHz clock frequency
Programmable I/O supports up to 36 inputs and 32 outputs
"Quiet" output buffers and input buffers with 2S0-mV hysteresis for
noise immunity and reliable operation
Powerful macrocell structure
Modulo-n binary and Gray-code counters
Complex state machines
Multiple-product-term JK flip-flops for complex waveform
generation
Phase comparator and clock oscillator functions
Available in 44-pin, windowed ceramic JLCC, one-time-programmable
PLCC, and plastic QFP packages
Advanced software support featuring waveform design entry, Altera
Hardware Description Language (AHDL), compilation, and simulation

The Altera EPS464 Erasable Programmable Logic Device (EPLO) provides
an integrated solution for synchronous timing waveform-generation
applications. Each of the EPS464 outputs can generate cu stomized waveforms
to meet a variety of different system requirements. Possible applications
include TV /videosynchronization
signals (e.g., NTSC, PAL, SECAM,
Figure 1. EPS464 Pin-Out Diagrams
HOTV) as well as CCO timing
controllers, high-performance state
machines, and memory-and servocontrollers. The EPS464 EPLO is
packaged in a 44-pin, windowed
ceramicJ-Ieadchipcarrier(JLCC) a
one-time-programmable plastic
J-Iead chip carrier (PLCC), or a
44-pin plastic quad flat pack (QFP)
EPS464
package. See Figure 1.

General
Description

o
J-Lead

! A/tera Corporation

QFP

Page203!

5

I EPS464 STG EPLD

Data Sheet

I

The EPS464 EPLDcontains 32 I 10 pins that canbe independently configured
as dedicated outputs, dedicated inputs, or bidirectional pins. The EPS464
also contains 4 dedicated input pins, one of which may be programmed as
a synchronous system clock.
The EPS464 EPLDcontains 64 macrocells that are ideally suited for waveformsynthesis applications (Figure 2). The advanced macrocell structure of the
EPS464 device allows integration of com plex logic functions, with over 100
product terms available to anyone macrocell. Each of the 64 internal flipflopsmaybeprogrammedforD, T,JK,orSRoperation.JKandSRflip-flops
are well suited for pattern-generation applications, since simple set and
reset operations can be used to define the transi tions of output waveforms.
Each flip-flop can be clocked from either a fast system clock or a
programmable asynchronous clock.

Figure 2. EPS464 Block Diagram
Inputr=:>--e--------, r---------<----.1 Input
InputC>--+-------,

r-------+-~llnput

1/0

MACROC ELL 33
MACROCELL 34

MACROCELL2

I~

MACROCELL 35

MACROCELL 3

1/0

MAC ROC ELL 36

MACROCELL 4

1/0

MACROCELL 37

MACROCELL 5

1/0

MACROCELL 38

MACROCELL 6

1/0

MACROCELL 39

MACROCELL 7

1/0

MACROCELL 40

MACROCELL8

I~

MACROCELL 41

MAC ROC ELL 9

1/0

MACROCELL 42

MACROCELL 10

1/0

MACROCELL 43

MACROCELL 11

1/0

MACROCELL 44

MACROCELL 12

I~

MAC ROC ELL 45

MACROCELL 13

1/0

MAC ROC ELL 46

MACROCELL 14

1/0

MACROCELL 47

MACROCELL 15

1/0

MACROCELL 48

MACROCELL 16

1/0

MACROCELL 49

MACROCELL 17

1/0

MACROCELL 50

MACROCELL 18

1/0

MACROCELL 51

MACROCELL 19

1/0

MACROCELL 52

MACROCELL 20

1/0

MAC ROC ELL 53

MACROCELL 21

1/0

MACROCELL 54

MACROCELL 22

1/0

MACROCELL 55
MAC ROC ELL 56
MACROCELL 57

MACROCELL 25

MAC ROC ELL 58

MACROCELL 26

I~

MACROCELL 59

MACROCELL 27

1/0

MACROCELL 60

MACROCELL 28

1/0

MACROCELL 61

MACROCELL 29

1/0

MACROCELL 62

Page 204

I~
~--M~AC~R~OC~EL~L~~~-~~~I~
MACROCELL 23

1/0

~--M-AC~ROC-E-L-L-30---~~~I~

MACROCELL 63

MACROC ELL 31

1/0

MAC ROC ELL 64

MACROCELL 32

1/0

A/tara Corporation

I

I EPS464 STG EPLD

Dats Sheet

I

The EPS464 EPLO is programmed with Altera's development software. To
simplify design entry for waveform-generationapplications, a new graphical
waveform entry method is available to describe the necessary timing
waveforms. This wa veform entry method is used with the Altera Hardware
Description Language (AHOL), reducing the overall design time and
allowing modifications to be made within minutes. The logic is then
automatically synthesized "to implement the function specified by the
waveforms.

Principle of
Operation

Waveform-generation and state machine applications can be efficiently
implemented with the EPS464device.Outputwaveformsaredecoded from
internal counters and, optionally, from internal state registers to set (i.e.,
perform low-to-high transition) or reset (perform high-ta-Iow transition)
the specified waveform.
Figure 3 shows a sample EPS464 design in which the EPS464 generates
NTSC video-display waveforms and CCO timing control. Twenty of the
EPS464 macrocells are configured for counters (1 0 bits horizontal and 10bits
vertical), and 4 macrocells are used to implement a state machine. The
counters and state machine registers are then decoded by the EPS464
macrocells and connected to internal synchronous JK registers to set and
reset desired ou tput waveforms.

I A/tera Corporation

Page 205

I

I EPS464 STG EPLD

Data Sheet

I

Figure 3. Typical EPS464 Application

Video
Analog
Block

Out

CCD
Image

Sensor

I Page206

Altera Corporation

I

PLS·SAM
SAM+PLUS Programmable
Logic Software
Data Sheet I

, October 1990, ver. 2

Features

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o
General
Description

Development software for Altera's EPS448 Stand-Alone
Microsequencer (SAM) EPLDs
Altera State Machine Input Language (ASMILE)
Assembly Language (ASM)
User-definable macros
SAM Design Processor (SDP) that generates industry-standard JEDEC
files
SAMSIM interactive functional simulator with Virtual Logic Analyzer
(VLA) user interface
Disassembler for examination of assembly code during simulation
Full support for horizontal cascading of multiple EPS448 EPLDs
Runs on IBM PC-AT, and PS/2 computers (and compatibles)
Device programming with Al tera programming hardware

The Altera PLS-SAM (SAM+PLUS Programmable Logic Software) provides
a complete software solution for implementing state machine and
microcoded applications in Altera's EPS448 SAM EPLD. PLS-SAM is a
comprehensive, easy-to-use system that includes state machine and
assembly language design entry, design processing with the SAM Design
Processor (SDP), and design debugging with SAMSIM. The EPS448 EPLD
is programmed with Altera's LogicMap II software and programming
hardware. See Figure 1. PLS-SAM is a software-only package. PLDS-SAM
(Programmable Logic Development System) includes LogicMap II,
programming hardware, and a software warranty (see the PLDS-SAM:
SAM+PLUS Programmable Logic Development System Data Sheet for details).
The SDP accepts two forms of design entry-state machine and assembly
language-and automatically generates an industry-standard JEDEC file

Figure 1. SAM+PL US Block Diagram

I Altera Corporation

Page 207

I

B

I PLS-SAM

Oats Sheet I

for simulation and programming. SAMSIM is an interactive functional
simulator created especially to verify state machine and microcoded designs
implemented in EPS448 EPLDs.

Functional
Description

Designs are entered in either the Altera State Machine Input Language
(ASMILE) or the Altera Assembly Language (ASM). A standard text editor
is used to create the input file with either method. If ASMILE is used, the
State Machine File (SMF) is processed by a converter to produce an ASM
file. The various modules of the SOP then process the ASM file .. The SOP
produces three outputs: an industry-standard JEOEC file used to simulate
and program the EPS448 EPLO, an error log file, and a utilization report
file that shows how resources within the EPLO are used.
After the JEOEC file is created, the user can simulate the design with the
SAMSIM functional simulator, which provides an interactive designdebugging environment. SAMSIM's Virtual Logic Analyzer (VLA) provides
on-screen examination of input and output waveforms, and the
disassembler converts object code back into the original ASM source code
during simulation.
Horizontal cascading (Le., using multiple EPS448 EPLDs to increase the
number of outputs) is fully supported in design entry, processing,
simulation, and programming. Multiple EPS448 EPLDs are listed in a
single source file, but separate report and JEOEC files are created for each
device.
Finally, the EPS448 EPLO is programmed with LogicMap II software and
programming hardware. Users who alread y have an Altera development
system may use existing hardware together with the LogicMap II software
and PLED448 or PLEJ448 adapters to program EPS448 EPLDs. For new
users, PLDS-SAM includes all the programming hardware and software
required to program the EPS448 EPLOs with a PC-AT, PS /2, or com patible
system.

State Machine
Design Entry

SAM+PLUS software supports high-level state machine design entry
through ASMILE. A designer can use this language with any standard text
editor to create a file describing a state machine. The State Machine File-toAssembly Language file (SMF2ASM) Converter translates the SMF into an
equivalent ASM file before sending it to the SOP.
ASMILE provides a simple yet comprehensive means of converting a
conceptual state diagram into a simple text description. Figure 2 shows the
state diagram for a 68020 bus arbiter. Each circle represents a state, the
values within the circles represent the output values for that state, and the
expressions adjacent to the arrows represent the conditional branches
between states.

Page 208

A/tera Corporation

I

I Data Sheet

PL5-SAM

I

Figure 2. State Diagram for a 68020 Bus Arbiter

RIA

RAG-

TX-

Bus request input
Bus grant acknowledge input
Bus grant output
Tri-state control to bus-control logic
Don't care

Figure 3 shows the ASMILE description of the state machine shown in
Figure 2. The states and their respective outputs have been defined in the
States Section with a truth table, and the transitions between states have
been defined with simple IF-THEN constructs. Once this file is created, it
can be submitted to the SOP without any further modifications.

Assembly
Language
Design Entry

Direct ASM design entry is also available for those who prefer to use
EPS448 EPLDs for microcoded controller designs. This entry method
provides access to the advanced features of the EPS448 device, including
the on-chip stack and loop counter. Thirteen instructions directly control
such functions as multi way branching, subroutines, nested FOR-NEXT
loops, and dispatch calls (i.e., jumping to an externally specified address).
User-defined macros that allow users to define their own instruction
mnemonics are also available, providing a higher-level design entry
approach. Macros can also be used to define values for various output
fields so that the deSigner does not have to work at the binary level.
Figure 4 shows an example of an ASM file in which macros have been used
to define the seven new instructions GOTOSe through GOTOS6.

I Altera Corporation

Page 209

I

I PLS-SAM

Data Sheet

I

Rgure 3. State Machine File
DESIGHER HAt1E
COt1PAHY HAt1E
181'11'98

68828 Bus Arbitration Controller for EPS448 SAt1 EPLD
PART:
IHPUTS:
OUTPUTS:
t1ACHIHE:
CLOCK:

EPS448
REQUEST ACK
GRAHT TRISTATE
BUSARBITER
CLK

'" The state table defines the outputs for each state '"
STATES: [ GRAHT TRISTATE ]
S8
[
88]
11]
S1
[
S2
[
1
1
S3
[
1
1
S4
[
1
1
S5
[
8
1
S6
[
8
1
'" Transition specifications '"
S8: IF REQUEST*I'ACK THEN SI
IF AeK THEN S5
S8
S1: S2
S2: IF I'REQUEST *I'ACK +ACK THEH S6
'" It1PLIED ELSE '"
S2
S3: IF I'REQUEST THEH S6
IF REQUEST*I'ACK THEH S2
S3
S4: S3
S5: IF I'REQUEST*I'ACK THEN S8
IF REQUEST THEH S4
55
56: S5

END$

Design

Processor

The SDP takes an ASM file and creates an optimized ]EDEC file for the
target EPLD. This process includes the following steps:

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I Page 210

The user-defined macros are expanded.
The design is parsed, and any syntax or connection errors are listed in
an error log file.
The Boolean expressions that define the transition conditions are
minimized.
The design is fitted into the EPS448 EPLD and an industry-standard
]EDEC programming file is generated. A utilization report that shows
how the design is implemented in the EPS448 EPLD is also created.

Altera Corporation

I

IOats Sheet

PL5-SAM

I

Rgure 4. Assembly Language File
DESIG"ER "AME
COMPA"Y "AME
18/1/98
68828 Bus Arbitration Controller for EPS448 SAM EPLD
PART:
EPS448
I"PUTS: REQUEST ACX
OUTPUTS: GRA"T TRISTATE
MACROS:
GOTOS8
GOTOSI
GOTOS2
GOTOS3
GOTOS4
GOTOS5
GOTOS6

"[881
"[11]
"[111
"[11]
"[111
"[81]
"[81]

JUMP
JUMP
JUMP
JUMP
JUMP
JUMP
JUMP

S8"
SI"
S2"
S3"
S4"
S5"
S6"

PROGRAM:
X
BUSARBITER
X
X
CLX
X
8D: GOTOS8;
S8: IF REQUEST*/ACX THE" GOTOS1;
ELSEIF ACX THE" GOTOS5;
ELSE GOTOS8;
S1:
GOTOS2;
S2: IF /REQUEST*/ACX+ACX THE" GOTOS6;
ELSE GOTOS2;
S3: IF /REQUEST THE" GOTOS6;
ELSEIF REQUEST*/ACX THE" GOTOS2;
ELSE GOTOS3;
S4: GOTOS3;
S5: IF /REQUEST*/ACX THE" GOTOS8;
ELSEIF REQUEST THE" GOTOS4;
ELSE [811 JUMP S5;
S6: GOTOS5;
E"D$

SAMSIM
Functional
Simulator

I Altera Corporation

Once a design has been processed, it can be simulated with the SAMSIM
Functional Simulator. SAMSIM provides a comprehensive design
debugging environment. The Virtual Logic Analyzer (VLA) displays the
input and output waveforms interactively, providing multiple zoom levels,
split screens, and differential time displays (see Figure 5). The internal
sta te of the EPS448 EPLD, including the stack and counter, can be examined
and modified. An online disassembler can convert the actual object code
back into the original ASM source code.

Page 211

I

I PLS-SAM

Dsts Sheet I

Figure 5. Virtual Logic Analyzer Screen
1:1~~~~--~--~--~----------~--==---------=~

REQUEST

ACK

----.J

-----,L-__--'
----D~

___--lin

~6

______

L~nL-

________________

'L-

~

____~~~______~nL-

............. ·8···
Range: B to 74

~~

"aMe: 68B28ARB. JED

____~________~~
Cycle: 1

Signals: 11

Programming
Hardware &
Software

LogicMap II is the software used to program the EPS448 SAM EPLD. The
software fully calibrates the programming environment and checks out
the programming hardware (available in PLDS-SAM) when initiated.
Programming hardware consists of a software-configured Logic
Programmer card that occupies a half-card slot in the computer, a Master
Programming Unit (PLE3-12A, and a programming adapter. LogicMap II
works with this hardware to program and verify EPS448 EPLDs.

PLS-SAM
Contents

PLS-SAM is provided for existing owners of Altera programming hardware.
PLDS-SAM or PLDS-SAM/PS users receive all of the required programming
hardware and PLS-SAM software (see the PLDS-SAM Data Sheet for more
information).

o

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Ordering
Information

I Page212

Floppy diskettes containing all programs and files for SAM+PLUS
software for both PC-AT and PS/2 computers
Altera State Machine Input Language (ASMILE)
Assembly Language (ASM)
SAM Design Processor
SAMSIM Functional Sim ula tor
LogicMapII
Documentation

PLS-SAM

(supports both PC-AT and PS/2 formats)

A/tera Corporation

I

Contents
I October 1990
Section 6

EPB·Series EPLDs
EPB-Series EPLDs: Altera U ser-Configurable Micro Channel
Interface ............................................................................................ 215
~

IAltera Corporation

This section presents an overview of the EPB-Series EPLDs.
Complete data sheets and application notes and briefs about EPBSeries EPLDs are available in the Micro Channel Adapter
Handbook (April 1990).

Page213 I

EPB·Series
EPLDs

Altera User-Configurable
Micro Channel Interface

Micro Channel Bus

Programmable
POS 1/0 Lines

o

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Memoryl

DMA

1/0 Control

Handshake

100% Micro Channel-compatible
architecture eliminates design debug
problems and results in faster board design
time.
3O-mA power-supply current conserves
limited board power for memory, I/O,
and other essential ICs.
2S-ns address decoding supports highspeed, zero "wait-state" data transfers.
EPROM board ID POS registers eliminate
extra ID registers.
Programmable POS register I/O gives the
designer a choice of POS bits accessible on
board.
8 programmable chip-select outputs
eliminate the need for extra address
decoder PLDs and glue logic ICs.

IAltera Corporation

o
o
o
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o
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24 Micro Channel address inputs support·
full address decoding from the Micro
Channel bus.
Multiple I/O or address decode ranges
(up to 8 per chip-select output) provide
multiple addressing options for the
designer's board.
24-mA current drive outputs eliminate
extra buffer ICs.
Channel-check interrupt support enables
the board to use bus Non-Maskable
Interrupts for fast CPU interrupt response.
Optional 28-pin EPB2002A EPLD provides
DMA arbitration support.
Altera's MCMap Development System
simplifies Micro Channel design and
eliminates design errors.
Page 215

I

Contents
I October 1990
Section 7

Operating Requirements for EPLDs
Operating Requirements for EPLDs ............................................................ 219

IAltera Corporation

Page 217

I

Operating Requirements
for EPLDs

I October 1990, ver. 1
Introduction

Altera EPLDs combine unique architectures with an advanced CMOS
EPROM process that provides exceptional performance with low power.
Like any high-performance CMOS process, systems must be designed with
care to obtain maximum performance with minimum problems.

Operating
Conditions

Opera tion of Altera EPLDs at condi tions above those listed under Absol u te
Maximum Ratings" in the EPLD data sheets may cause permanent damage
to the devices. These ratings are stress ratings only. Functional operation of
the device at these conditions or at any other conditions above those indicated
in the operational sections of these data sheets is not implied. Exposure to
absolute maximum ratings conditions for extended periods of time may
affect device reliability. Altera EPLDs contain circuitry to protect device
pins from high-static voltages or electric fields; however, precautions should
be taken to avoid voltages higher than maximum-rated voltages.
II

For proper operation, input and output pins must be in the range GND <
(VIN or Your) < Vee. Unused inputs must be tied to Vee or GND. Unused
I/O pins should be tied to Vee or GND, or left unconnected ("reserved").
Specific requirements are given in the EPLD pin-out in the Report File
(utilization report) for a design. Each set of Vee and GND pins must be
connected directly at the device, with power supply decoupling capacitors
of at least 0.21lF connected between them. For effective decoupling, each
Vee pin should be separately decoupled to GND, directly at the device.
Decoupling capacitors should have good frequency response, such as the
response in monolithic-ceramic types.

Noise
Precautions

If more than 12 EPLDoutputpins are switching simultaneously, precautions
must be taken to minimize system noise. Certain board layouts can induce
switching noise into the system from high-speed devices due to transmissionline effects and radiated coupling. These effects can be minimized by using
printed circuit boards with embedded Vee and GND planes. They can also
be lessened by restricting trace length in a board to under eight inches. In
cases where long board trace~ or highly capaciti'le loads are impossible to
avoid, a small series resistance (10 to 30 n) usually lessens undershoot and
overshoot voltages if they cause a problem in a particular printed circuit
board layout.

Turbo Bit

Some EP-series EPLDs contain a programmable Turbo Bit, set with A+PLUS
software, to control the automatic power-down feature that enables lowstandby-power mode. When the Turbo Bit is programmed (Turbo = On),

I Altera Corporation

Page 219

I

I Operating Requirements for EPLDs
the low standby power mode (lCC1) is disabled, making the circuit less
sensitive to Vcc noise transients created by the low-power mode powerup/power-down cycle. Typical Icc versus frequency data for both turbo
and non-turbo mode is given in each EPLD data sheet. All AC values are
tested with the Turbo Bit programmed on.
If the design requires low-power operation, the Turbo Bit should be disabled
(Turbo = Off). In this mode, some AC parameters rnayincrease. To determine
worst-case timing, values from the AC Non-Turbo Adder specifica tions in
the EPLD data sheet must be added to the corresponding AC parameter.

Device
Erasure

Altera EPLDs begin to erase when exposed to lights with wavelengths
shorter than 4,000 A. Since fluorescent lighting and sunlight fall into this
range, opaque labels should be placed over the EPLD window to ensure
long-term reliability. The recommended erasure procedure for EPLDs is
exposure to UV light with a wavelength of 2,537 A. Required erasure times
assuming use of a lamp with a 12,000 ~W /cm 2 power rating are given in
the table below; some low-power erasers may take longer.
Part Number
EP320, EP610,EP910,EP1810, EPS448
EP640, EPB2001, EPM5016, EPM5032,
EPM5064, EPM5128, EPM5130, EPM5192
EP330, EP630,EP1830

Erasure Time
30 minutes
1 hour
2 hours

Altera EPLDs may be damaged by long-term exposure to high-intensity
UV light. Altera EPLDs may be erased and reprogrammed as often as
necessary if the recommended erasure exposure levels are used.

ESD and
Latch-Up
Protection

EPLD input, I/O, and clock pins have been designed to resist the electrostatic
discharge (ESD) and latch-up inherent in CMOS structures. Unless
otherwise noted, each of the EPLD pins will withstand voltage energy
levels exceeding 1,500 V, per method specified by MIL-STO-883C. The pins
will not latch up for input voltages in the range Vss-1 V to Vcc + 1 V with
currents up to 100 rnA. During transitions, the inputs may undershoot to
-2.0 V for periods less than 20 ns. Additionally, the programming pin is
designed to resist latch-up to the 13.5 V maximum device limit.

Power
Calculations

As with any CMOS device, power is a function of frequency and internal
node switching. To obtain the most accurate power information, current
consumption should be measured after the design is completed and the
EPLD is placed in the system.

Conclusion

If the precautions given in this data sheet are followed during system and
board design, Altera EPLDs should provide superior system performance
and design flexibility, regardless of design size or production volume.

IPage 220

Altera Corporation

Contents
I October 1990
Section 8

Development Products
PLDS-ENCORE: Complete Programmable Logic Development
System .............................................................................................. 223
PLDS-MAX: MAX+PLUS Programmable Logic
I>evelopment System ...................................................................... 225
PLCAD-SUPREME: Enhanced A+PLUS Programmable
Logic I>evelopmentSystem ........................................................... 227
PLDS2: Basic A+PLUS Programmable Logic
I>evelopment System ...................................................................... 229
PLDS-SAM: SAM+PLUS Programmable Logic
I>evelopment System ...................................................................... 231
PLDS-MCMAP: MCMap Programmable Logic
I>evelopment System ...................................................................... 233
AB73
Software Utility Programs ............................................................. 235
PC System Requirements ............................................................................... 237
PLS-EDIF: Bidirectional EDIF Netlist Interface to
MAX +PLUS Software ..................................................................... 238
PLS-APOLLO: MAX+PLUS Programmable Logic Software
for Apollo Computers .................................................................... 249
PL-ASAP: Altera Stand-Alone Programmer ............................................... 256
PLE3-12A: EPLD Master Programming Unit .............................................. 257
PLED/J/G/S/Q: PLED, PLEJ, PLEG, PLES & PLEQ
Programming Adapters ................................................................. 258
PLAESW-PC: Extended Software Warranty ............................................... 260
Third-Party I>evelopment & Programming Support ................................. 261

IA/tera Corporation

Page221 I

PLDS·ENCORE
Complete Programmable Logic
Development System

I October 1990, ver. 1
Contents

Data Sheet

o
o
o
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General
Description

I

PLS-MAX-MAX +PLUS Programmable Logic Software
PLS-SUPREME-Enhanced A+PLUS Programmable Logic Software
PLS-SAM-SAM+PLUS Programmable Logic Software
PL-ASAP-Altera Stand-Alone Programmer:
Software-controlled Logic Programmer interface card
PLE3-12A-EPLD Master Programming Unit
Programming adapters:
PLED5016 DIP
PLEJ5128 J-lead PLED1810 DIP
PLED5032 DIP
PLED610 DIP
PLED448 DIP
PLEJ5064J-Iead PLED910DIP
Sample EPLDs for evaluation
PLAESW-PC-12-Month Software Warranty and Update Service

PLDS-ENCORE is Altera's most comprehensive EPLD development
package. It supports design entry, logic optimization, and design verification
for all Multiple Array MatriX (MAX), EP-series, and Stand-Alone
Microsequencer (SAM) EPLDs.
MAX EPLD designs are implemented with PLS-MAX-MAX+PLUS
Programmable Logic Software. Designs can be entered with any
combination of hierarchical schematic files, and hierarchical text files

I Altera Corporation

Page 223

I

I PL05-ENCORE

DataShHt I

containing Boolean equations, state machines, and truth tables in the
Altera Hardware Description Language (AHDL). Over 300 7400-series and
special-purpose macrofunctions are available for design entry. MAX+PLUS
also includes a fast and efficient design compiler, automatic error location,
delay prediction, interactive timing simulation, timing analysis, and device
programming applications.
EP-series EPLD designs are implemented with PLS-SUPREME (Enhanced
A+PLUS Programmable Logic Software). PLS-SUPREME supports
schematic capture, Boolean equation, state machine, truth table, ahd netlist
design entry methods. It includes LogiCaps schematic capture, TTL
MacroFunction Library, Altera Design Librarian (ADLIB), State Machine
Entry, Altera Design Processor, Functional Simulator (FSIM), and
LogicMap II software.
SAM EPLD designs are implemented with PLS-SAM (SAM+PLUS
Programmable Logic Software). SAM+PLUS includes state machine and
microcode design entry, the SAM Design Processor, and the SAMSIM
Functional Simulator, providing an efficient logic development system for
SAM EPLDs.
The PLDS-ENCORE Development System includes all necessary
hardware-a Logic Programmer card, Master Programming Unit, and a
range of programming adapters-to program EPLDs at the designer's
desktop.
PLDS-ENCOREalsoincludesPLAESW-PC,a 12-month renewable warranty
that covers all PC-based Altera software, including PLS-MAX, PLS-SAM,
and PLS-SUPREME.1t provides automatic upgrades to each new version
of Altera software and guarantees software support for new EPLDs as they
are introduced. PLAESW-PC also provides a toll-free hotline and 24-hour
modem interface to Altera's Electronic Bulletin Board Service.
Individual PLDS-ENCORE components can be purchased separately.
However, PLDS-ENCORE provides a full range of EPLD logic development
support at a significant savings compared with the cost of purchasing each
individual software application separately.
See the individual data sheets for PLDS-ENCORE components (in this
data book) for additional information on Altera software and hardware.

Ordering
Information

IPage224

PLDS-ENCORE
PLDS-ENCORE/PS

(for IBM PC-AT and compatibles)
(for IBM PS/2 Models 50, 60, 70, 80, and
compatibles)

Altera Corporation

I

PLDS-MAX
MAX+PLUS Programmable
Logic Development System
Data Sheet I

I October 1990, ver. 1
Contents

o

PLS-MAX-MAX +PLUS Programmable Logic Software

o
o

PLE3-12A-EPLDMaster Programming Unit
Programming Adapters:
PLED5016 DIP
PLEJS064J-lead
PLEDS032 DIP
PLEJS128 J-lead
Sample EPLDs for evaluation
PLAESW-PC-12-Month Software Warranty and Update Service

o Software-controlled Logic Programmer interface card

o
o
General
Description

The Altera PLDS-MAX Development System is a unified CAE tool kit for
implementing designs in the MAX (Multiple Array MatriX) family of
EPLDs. PLDS-MAX, which includes MAX+PLUS software, provides a
comprehensive range of design entry, design processing, timing simula tion,
and device programming capabilities.
PLDS-MAX allows MAX designs to be completed rapidly and efficiently.
Designs can be entered with any combination of hierarchical schematic
files created with the MAX+PLUS Graphic Editor, and hierarchical text
files containing Boolean equations, state machines, or truth tables in the
Altera Hardware Description Language (AHDL). The MAX+PLUS
Compiler minimizes and synthesizes the design logic, and fits the design

I Altera Corporation

Page22s1

I PL05-MAX

OstsSheet I

into a targeted MAX EPLD. Processing is completed within minutes. The
MAX+PLUS Simulator provides full interactive timing simulation. To
simplify design verification, simulation inputs can be edited graphically in
the MAX +PLUS Waveform Editor. (For more information on MAX +PLUS
software, refer to PLS-MAX: MAX+PLUS Programmable Logic Software Data

Sheet.)
PLDS-MAX hardware consists of a Master Programming Unit, Logic
Programmer card, programming adapters, and a variety of device samples.
The MAX+PLUS Programmer uses this hardware and the programming
file created by the Compiler to translate design outputs into working MAX
EPLDs.
PLAESW-PC, a 12-month renewable warranty that covers all PC-based
Altera software, is included in PLDS-MAX. It provides automatic upgrades
to each new version of Altera software and guarantees software support
for new MAX EPLDs as they are introduced. PLAESW-PC also provides a
toll-free hotline and 24-hour modem interface to Altera's Electronic Bulletin
Board Service. (See PLAESW-PC: Extended Software Warranty Data Sheet for
further details.)
The optional PLS-EDIF package provides an interface between MAX+PLUS
and third-party CAE systems. For customers who already own Altera
programming hardware, PLS-MAX (MAX+PLUS Programmable Logic
Software) is available as a software-only enhancement to their current
system.

Ordering
Information

IPage 226

PLDS-MAX
PLDS-MAX/PS

(for IBM PC-AT and compatibles)
(for IBM PS/2 Models 50,60,70,80, and compatibles)

Altera Corporation

I

PLeAD-SUPREME
Enhanced A+PLUS Programmable
Logic Development System
Data Sheet I

I October 1990, ver. 1
Contents

o

o
o

o
o
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General
Description

I Altera Corporation

PLS-SUPREME-Enhanced A+PLUS Programmable Logic Software
and Documentation
A+PLUS Programmable Logic Software
Altera Design Processor (ADP)
LogicMap II device programming software
LogiCaps schematic capture software
TIL MacroFunction Library
Altera Design Librarian (ADLIB) software
State Machine Entry software
Functional Simulator (FSIM) software
Software-controlled Logic Programmer interface card
PLE3-12A-EPLD Master Programming Unit
PLED610 DIP programming adapter
PLED910 DIP programming adapter
PLEJ1810 J-lead programming adapter
Sample EPLDs: EP320DC, EP610OC, EP910OC, EP1810JC
PLAESW-PC-12-Month Software Warranty and Update Service

PLCAD-SUPREME provides basic A+PLUS software, additional software
applications for design entry and design verification, and programming
hardware that supports all Altera general-purpose EP-series EPLDs.

PBge227

I

I PLCAD-SUPREME

Da,. Sheet I

PLCAD-SUPREME offers four different methods of design entry: LogiCaps
schematic capture, state machine, Boolean equation, and netlist. Designers
can use over 100 functions from the A+PLUS TIL MacroFunction Library,
and design their' own macrofunctions with the Altera Design Librarian
(ADLIB). The Altera Design Pra:cessor optimizes the design and generates
aJEDEC file for EPLD programming. The Functional Simulator provides a
convenient method for testing the logical operation of the compiled design.
PLCAD-SUPREME also includes LogicMap II device programming
software, a Master Programming Unit, a Logic Programmer card, and a
variety of device samples and programming adapters. (For more
information on A+PLUS software and enhancements, refer to
PLS-SUPREME: Enhanced A+PLUS Programmable Logic Software Data Sheet.)
PLAESW-PC, a 12-month renewable warranty that covers all PC-based
Altera software, is included in PLS-SUPREME. It provides automatic
upgrades to each new version of Altera software and guarantees software
support for new EPLDs as they are introduced. PLAESW-PC also provides
a toll-free hotline and 24-hour modem interface to Altera's Electronic
Bulletin Board Service. (See PLAESW-PC: Extended Software Warranty Data
Sheet for further details.)
PLCAD-SUPREME provides a complete logic design capability for the full
range of Altera EP-series EPLDs at a significant savings compared with the
cost of purchasing the PLDS2 and PLS-SUPREME packages separately.
For customers who already own Altera programming hardware, PLSSUPREME (Enhanced A+PLUS Programmable Logic Software) is available
as a software-only package.

Ordering
Information

IPage228

PLCAD-SUPREME
PLCAD-SUPREME/PS

(for IBM PC-AT and compatibles)
(for IBM PS/2 Models 50, 60, 70, 80, and
compatibles)

A/tera Corporation

I

PLDS2
Basic A+PLUS Programmable
Logic Development System
Data Sheet !

October 1990, ver. 1

Contents

o
o
o
o
o

o
General
Description

A +PLUS Programmable Logic Software and Documentation
Altera Design Processor (ADP)
LogicMa p II device programming software
Softwarele Bib

11122221111111111
D03211198765432UI9876543218

765432187&5432187654321876543218
,8185.., r8184, r8183, ,8182,
DXXXXXXXXl CCCCCCCCCCC~lCXXXXXXXXXX

XBXXXlCCCC

8888888811

X8XXXlCCCC

I!!! 888888888

DXXXXlCXXXl CO CCceo CCCC:XXXXXlCXXXXX
relB5.., r811H-. re183.., re18Z..,
DXXXXXXXX)OO()O()O()O(l(XXXXXXXXXXX

X8XXXlCCCC

8118888888

DXXXXXXXXl CCCCCCCCCCC:XXXXXXXXXXX

O;.iif ••••• ;!;!;!;@mlmlmnnumu

~185..,

~111S..,
~185..,

rf'1B4-,

rf'1B4-,
rf'1B4-,

~183.., ~18z-,

~183,

r4'182..,

~183, ~182,

X8XXXlCCCC

888888888

DXXXXlCXXXlCCCCCCCCCCC~XXXXXXXXlOO(

X8XXXlCCCC

! ! ! B888888888

.... 185..., rf'UM--, .... 1113..., .... 182-,
DXXXXXXXX)OO()O()O()O(l(XXXXXXXXXXX

X8XXXlCCCC

8_.

~t85..,
~185..,

X8XXXlCCCC
u ... : ..- - .. t ,

8B88BB8811

to .........

rf'tB4-,

~183,

rfl18z-,

DXlClClClCXICXl CC: CCCCCCCC~XICICICICXICICXXX

rf'1B4-,

~183-, r~118z-,

DlClCXICXXXXlC CCCCCCCCcctxxxxxxxxxxx

Esc to exit

PLDS-MCMAP also includes PLAESW-PC, a 12-month renewable warranty
that provides automatic upgrades to each new version of MCMap software.
(See PLAESW-PC: Extended Software Warranty Data Sheet for further
details.)
For customers who already own Altera programming hardware,
PLS-MCKIT (MCMap Programmable Logic Software) is available as a
software-only enhancement to their current system.

Ordering
Information

I Page234

PLDS-MCMAP

(for IBM PC-AT and com patibles)

(Contact Altera Marketing for information on systems containing PS/2compatible hardware.)

A/tera Corporation

I

Software Utility Programs
I October 1990, ver. 2
Introduction

Application Brief 731
Altera provides a variety of software utility programs that complement the
MAX+PLUS, A+PLUS, SAM+PLUS, and MCMap development systems.
All programs are available via Altera's Electronic Bulletin Board Service
(BBS) from the EAU (Electronic Application Utilities) directory. The BBS
telephone number is (408) 249-1100; operation of the BBS is described in
this data book and Altera software manuals. These utility programs can
also be obtained by contacting Altera Applications at 1 (BOO) BOO-EPLD.
Customers outside North America can obtain copies of these programs
from their local Altera representative or distributor. All utility programs
operate on an IBM PC-AT or compatible, and on IBM PS/2 Model 50 or
higher computers with OOS version 3.1 or higher.

PAL2EPLD

(EAU002) The PAL2EPLD utility converts 20-pin PAL designs into EP320
or EP330 designs. It directly converts PAL JEDEC files into EP320/EP330
JEDEC files.

310-to-320/30
Converter

(EAUOO3) The EP310-to-EP320/EP330 JEDEC HIe Converter automatically
converts EP310 JEDEC files to EP320 /EP330-compatible JEDEC files.

LogiCaps
Plotter
Interface

(EAU004) An Al tera customer has written an interface program between
LogiCaps and Houston Instruments plotters. This EAU provides
information on how to obtain the interface program.

JEDPACK

(EAUOOS) The JEDPACK utility compacts the size of JEDEC files, freeing
up space on the computer's hard disk while retaining EPLDprogramming
information. This utility is handy for archiving A+PLUS-, SAM+PLUS-,
and MCMap-generated JEDEC files.

Address
Decoder

(EAU006) The DECODER utility automatically generates Boolean
equations for address decoding applications. The program accepts a userspecified address bus width with upper and lower address bounds. It
generates equations that can be placed into a MAX +PLUS-compatible Text
Design File (TOF) or an A+PLUS-compatible Altera Design File (ADF).

JEDSUM

(EAU007) The JEDSUM utility calculates the EPROM data checksum, the
file transmission checksum, and the number of programmed architecture

I Altera Corporation

Page23s1

-=-

r..

I Software Utility Programs

Application Brief

731

bits contained in the JEDEC file for an EP-series, EPB-series, or SAM EPLD.
The EPROM data checksum is often useful for documenting programming
files.

AVEC

(EAUOO8) The AVEC utility adds functional test vectors to EP-series
EPLD JEDEC files. AVEC translates the table output files generated by the
A+PLUS Functional Simulator into JEDEC-standard test vectors. Thirdparty programmers (e.g., Data I/O 29B and UniSite 40 machines) have
built-in hardware drivers that can apply these vectors to the programmed
EPLD. Note, however, that Altera EPLDs are 100% generically tested
before they leave the factory, so post-programming functional testing is
not required.

BACKPIN

(EAUOO9) The BACKPIN utility extracts the pin assignments-assigned
during design fitting--contained in an A +PLUS-generated JEDEC file and
places them into the corresponding LogiCaps schematic drawing. If the
Altera Design Processor (ADP) is set up to make pin assignments
automatically, BACK PIN can then place the ADP's pin assignments back
into the LogiCaps schematic drawing. The same pin assignments are then
retained even if additional changes are made to the circuit design.

LEF2ABEL

(EAU012) The LEF2ABEL utility translates a Logic Equation File (LEF)
generated by the Altera Design Processor (ADP) to ABEL format. A+PLUS
users may thus take advantage of theADP's SALSA Minimizer to generate
an optimized ABEL input file.

PAL2ADF

(EAU013) The P AL2ADF utility converts PALASM 1 or 2 files to the
A+PLUS- and MAX+PLUS-compatible ADF input format.

LCA2ADF

(EAU016) The LCA2ADF utility converts LCA design files for XC2CXX>and XC3000-series devices into the A+PLUS- and MAX +PLUS-compatible
ADF format. The new target device may be a larger-size Altera EPLD, such
as the EP1810, EPl830, EPMS064, EPMS128, EPMSl30, or EPMS192.

LEF2AHDL

(EAU017) The LEF2AHDL utility converts an A+PLUS-generated Logic
Equation File (LEF) to aMAX+PLUS-compatible Text Design File (TOF) in
the Altera Hardware Description Language (AHDL).

PLD2EQN

(EAU018) The PLD2EQN utility converts JEDEC files from a variety of
20- and 24- pin PAL and GAL devices (e.g., 16V8, 20V8, 22VIO, 16L8, 16R8,
2358) into the A+PLUS-compatible ADF and MAX+PLUS-compatible
AHDL Text Design File (TOF) formats. This utility allows users to combine
multiple PALs and GALs into a single Altera EPLD.

ABEL2MAX

(EAU019) The ABEL2MAX utility converts ABEL version 4.0 design files
(with the extension .TT2) into the MAX+PLUS-compatible Text Design
File (TOF) format.

IPage236

Altera Corporation

I

PC System Requirements
I October 1990, ver. 1

Data Sheet I

Introduction

All PC-based Altera Programmable Logic Development Systems,
Programmable Logic Software, and Software Utility Programs can be
installed in IBM PS/2 Model 50 or higher, PC-AT, or compatible computers.

Minimum
System
Configuration

0
0
0
0

0

IBM PS/2 Model 50 or higher, PC-AT, or compatible computer
OOS version 3.1 or higher
640 Kbytes of RAM
For MAX+PLUS only: 1 Mbyte of expanded memory with version 3.2
or higher of the Lotus/Intel/Microsoft (LIM) Expanded Memory
Specification
VGA, EGA, or Hercules Monochrome display (CGA is also supported
by A+PLUS, SAM+PLUS, and MCMap)
20-Mbyte hard disk
1.2-Mbyte 51 /4-inch or 1.44-Mbyte 3 1/2-inch floppy disk drive
3-button serial-port mouse or 2-button Microsoft-compatible serialport or bus mouse (plus a serial port for a serial-port mouse.)
Em pty card slot (full length) for programming card

Recommended
System
Configuration

0
0
0
0
0
0
0
0
0

IBM PS/2 Model 70 or higher, or 20-MHz or higher 386-based computer
OOS version 3.3
640 Kbytes of RAM
VGA graphics display
40-Mbyte hard disk
3 Mbytes Expanded Memory with LIM 3.2-compatible driver
1.2-Mbyte 5 1/4-inch or 1.44-Mbyte 3 l/2-inch floppy disk drive
Serial port and 3-button serial-port mouse
Empty card slot (full length) for programming card

Sample
Configurations

0

Compaq 386-20 with 3 Mbytes of RAM, the CEMM Expanded Memory
Manager, Compaq VGA display, and Mouse Systems 3-button serialport mouse
Wyse 386-16 with Intel Above Board 286, VEGA VGA card with NEC
MultiSync II monitor, and Logitech C-7 seri.al-port mouse
IBM PS/2 Model 80 with 4 Mbytes of RAM, IX>S version 4.01 Expanded
Memory Manager, Logitech Series 9 Mouse attached to pointing device
port, and EGA display
Everex 386-25 with extended memory configured as expanded
memory, Paradise VGA card, VGA display, and 2-button Microsoftcompatible bus mouse

0
0
0
0

0
0
0

I Altera Corporation

Page 237

I

PLS-EDIF
Bidirectional EDIF Netlist Interface
to MAX+PLUS Software

IOctober 1990, ver. 2
Features

Data Sheet

o
o
o
o
o
o
o

General
Description

Provides a bidirectional netlist interface between MAX+PLUS and
other major CAE software packages.
Supports the industry-standard Electronic Design Interchange Format
(EDIF) version 2 0 O.
Allows MAX EPLD designs to be created with workstation CAE tools
and transferred to MAX +PLUS for compilation; com piled designs can
be returned to the workstation for device- or system-level simulation.
Altera EDIF netlist reader imports EDIF netlists into MAX+PLUS.
Altera-provided Library Mapping Files (LMFs) convert basic gate and
many common TIL library functions from Dazix, Mentor Graphics,
Valid Logic Systems, and Viewlogic Systems CAE tools to equivalent
MAX +PLUS functions.
Altera EDIF netlist writer produces post-synthesis logiC and delay
information used during device- or board-level simulation with
popular CAE tools.
Runs on IBM PS/2, PC-AT, or compatible machines.

The Altera PLS-EDIF tool kit is a bidirectional EDIF netlist interface between
PC- or workstation-based CAE software packages and the Altera
MAX+PLUS Programmable Logic Development System. See Figure 1.

Figure 1. PL5-EDIF Workstation Interface
CAE Workstationl
PC Platform

Shading indicates items provided with PLS-EDIF.

PC Platform

• logic Entry
• Device Simulation
• Board Simulation

··_.................................................................................................
···
...
·
.
1

I Page 238

I

1

• logic Entry
• logiC Synthesis

• Device Simulation
• Programming

Lbtary Mapping Files

EDIF200

Altera Corporation

I

I Data Sheet

PLS-EDIF

I

PLS-EDIF (Bidirectional EDIF Netlist Interface to MAX+PLUS Software)
allows designers to enter and verify logic designs for Altera MAX EPLDs
with third-party CAE tools. The EDIF 2 0 0 netlist exchange format
provides a two-way bridge betweenMAX+PLUS and third-party schematic
capture and simulation tools. PLS-EDIF runs on an IBM PS/2, PC-AT, or
com patible computer.
Any CAE software package that produces EDIF 2 0 0 netlists can use the
PLS-EDIF interface to MAX+PLUS. EDIF netlists are imported into
MAX+PLUS with the EDIF JRsign File-to-Compiler Netlist File (EDF2CNF)
Converter. Library Mapping Files (LMFs) are used with EDF2CNF to map
library functions from third-party CAE tools to the MAX+PLUS library
functions. LMFs are provided for Dazix, Mentor Graphics, Valid Logic,
and Viewlogic software, but designers may create their own LMFs to map
any CAE software library.
After a design is imported into MAX+PLUS, it is compiled with the
sophisticatedMAX+PLUSCompiler, which uses advanced logic synthesis
and minimization techniques together with heuristic fitting rules to optimize
the design for MAX EPLD architecture. MAX devices are then programmed
with a Programmer Object File (POF) created by the MAX+PLUS Compiler
and standard Altera or third-party programming hardware.
EDIF netlists can be exported from MAX+PLUS with the Simulator Netlist
File-to-EDIF Design File (SNF2EDF) Converter. This converter generates
an EDIF output file from a compiled MAX+PLUS design. The EDIF file
contains the post-synthesis information used by CAE simulators to perform
device- or board-level simulation.
PLS-EDIF provides an open environment that allows designers to use
popular third-party CAE tools to crea te and sim ula te MAX EPLD designs.
The designer can use a preferred workstation schematic capture package
to enter a logic design, quickly convert it with EDF2CNF, and compile it
with MAX+PLUS. Likewise, designs compiled in MAX+PLUS and
converted with SNF2EDF can be transferred to a workstation for simulation.
Together, the PLS-EDIF netlist reader and writer (EDF2CNF and SNF2EDF)
allow MAX EPLD designs to be entered and simulated on the workstation
platform of choice.

I A/tera Corporation

Page 239

I

II
.-

I PLS-EDIF
EDF2CNF
Converter

Data Sheet

I

The EOF2CNF Converter generates one or more MAX+PLUS Compiler
Netlist Files (CNFs) from an EOIF file. For each CNF, a Hierarchy
Interconnect File (HlP) and a Graphic Design File (GOP) are also created.
See Figure 2. The CNF contains the logic and connectivity da ta for a design
file, while the HIF defines the hierarchical connections between design
files. The GOF is a token symbol that represents the actual design data in
the CNF. This symbol-and the underlying logic-may be used in a logic
schematic in the MAX+PLUS Graphic Editor.
Figure 2. EDF2CNF Block. Diagram

One or more Library
~ngFlesmay

be used as inputs.

One or more sets of
CNF, HIF, WId GDF
files are generated.

EOF2CNF can convert any EOIF 2 0 0 netlist with the following
characteris tics:

o

EOIF level B

o
o

view type NElLISl
cell type GENERIC

o keyword levelB

EOF2CNF gives designers the flexibility to design logic solely with
workstation CAE tools, or to mix design inputs from a variety of platforms
and software packages. For example, a workstation CAE schematic
converted with EOF2CNF may be combined with an Altera Hardware
Description Language (AHOL) state machine in MAX+PLUS. Designers
can choose the entry methods and platforms that best meet their needs.
Library Mapping Files (LMFs) are used with EDF2CNF to convert functions
of workstation CAE tools to equivalent MAX +PLUS functions. This direct
substitution is beneficial because MAX+PLUS functions are optimized for
both logic utilization and performance in MAX EPLO designs.

I Page 240

A/tera Corporation

I

I Data Sheet

PLS-EDIF

I

Workstation
Information

EDF2CNF has been specifically tested for use with the Dazix, Mentor
Graphics, Valid Logic Systems, and Viewlogic Systems CAE software
packages. LMFs for these products are also provided with the PLS-EDIF
tool kit.

Dazix

To design logic and create an EDIF file with Dazix software, the following
applications are required:
DACE (Dazix graphics editor)
DANCE and DRINK (Dazix compiler)
ENW version 1.0 (Dazix EDIF netlist writer)

o
o

Table 1 lists the Dazix basic functions that are mapped to MAX+PLUScompatible functions:
Table 1. Dazix Library Mapping File (Basic Functions)
Dazix Function
R#AND
R#ANDD
R#NAND
R#NANDD
R#NOR
R#NORD
R#OR
R#ORD
R1BUF
R11NV
R11NVD
R10CBUF
R10TBUF
R1TINV
R2XNOR
R2XOR
R3UAOI
R4AOI
R40AI
R8AOI
R13TNAND
R13TNANDD
RDFLOP
RDLATCH
RJKFlOP

I Altera Corporation

MAX+PLUS-Compatible Function
AND#
BNOR#
NAND#
BOR#
NOR#
BAND#
OR#
BNAND#
MCELL
NOT
EXP
SCLK
TRIBUF
TRINOT
XNOR
XOR
1A2NOR2
2A2NOR2
20R2NA2
4A2NOR4
TNAND13
TBOR13
DFF2
RDLATCH
JKFF2

(#=2,3,4,5,6,7,8,9)
(#=2,3,4,5,6,7,8,9)
(#=2,3,4,6,7,8,9,13)
(#=2,3,4,5,7,8,9,13)
(#=2,3,4,5)
(#=2,3)
(#=2,3,4,5)
(#=2,3,4,5)

II

Page 241

I

I PLS-EDIF
Mentor
Graphics

Dsts Sheet

I

To design logic and create an EDIF file with Mentor Graphics software, the
following applications are required:

o
o
o

NETED (Mentor Graphics graphics editor)
EXPAND (Mentor Graphics schematic file translator)
EDIFNET version 7.0 (Mentor Graphics EDIF netlist writer)

Table 2 lists the Mentor Graphics basic functions that are mapped to
MAX +PLUS-com patible functions:
Table 2. Mentor Graphics Library Mapping File (Basic Functions)
Mentor Graphics Function
AND#
aUF
DELAY
DFF
INV
JKFF
LATCH
NAND
NOR
OR
XNOR2
XOR2

I Page 242

MAX+PLUS-Compatible Function
AND#
SCLK
MCELL
DFF2
NOT
JKFF2
MLATCH
NAND#
NOR#
OR#
XNOR
XOR

(#=2,3,4,5,6)

(#=2,3,4,5 6,9)
(#=2,3,4,6,8,16)
(#=2,3,4,6,8)

Altera Corporation

I

IData Sheet
Valid Logic
Systems

PL5-EOIF

I

To design logic and create an EDIF file with Valid Logic Systems software,
the following applications are required:

o ValidGED (Valid Logic Systems graphics editor)
o Valid Compiler (Valid Logic Systems compiler)

o

GEDIFNET (Valid Logic Systems EDIF netlist writer)

Table 3 lists the Valid Logic Systems basic functions that are mapped to
MAX+PLUS-compatible functions:
Table 3. Valid Logic Systems Ubrary Mapping File (Basic Functions)
Valid Logic Systems Function

INV
LSOO
LS02
LS04
LS08
LS10
LS11
LS20
LS21
LS27
LS28
LS30
LS32
LS37
LS40
LS74
LS86
LS126
LS280
LS386

1 A/tera

Corporation

MAX+PLUS-Compatible Function

EXP
NAND2
NOR2
NOT
AND2
NAND3
AND3
NAND4
AND4
NOR3
NOR2
NAND8
OR2
NAND2
NAND4
DFF2
XOR
TRI
DFF2
XOR

Page

2431

I PL5-EDIF
Viewlogic
Systems

Data Sheet

I

To design logic and create an EDIF file with Viewlogic Systems software,
the following applications are required:

o
o

WorkView (Viewlogic Systems graphics editor)
EDIFNETI version 3.02 (Viewlogic Systems EDIF netlist writer)

Table 4 lists the Viewlogic Systems basic functions that are mapped to
MAX+PLU5-compatible functions:
Table 4. View/ogic Syst~s Ubrary Mapping File (Basic Functions)
Viewlogic Systems Function
AND#
ANDNOR22
BUF
DAND#
DELAY
DOR#
DXOR#
JKFFRE
MUX41
NAND#
NOR#
NOT
OR#
TRIAND#
TRIBUF
TRINAND#
TRINOR#
TRINOT
TRIOR#
UBDEC38
UDFDL
UJKFF
XNOR2
XNOR#
XOR2
XOR#

I Page 244

MAX+PLUS-Compatible Function
AND#
2A2NOR2
SOFT
DAND#
MCELL
DOR#
DXOR#
JKFFRE
MUX41
NAND#
NOR#
NOT
OR#
TAND#
TRIBUF
TNAND#
TNOR#
TRINOT
TOR#
DEC38
UDFDL
UJKFF
XNOR
XNOR#
XOR
XOR#

(#=2,3,4,8)

(#=2,3,4,8)
(#=2,3,4,8)
(#=2,3,4,8)

(#=2,3,4,8)
(#=2,3,4,8)
(#=2,3,4,8)
(#=2,3,4,8)
(#=2,3,4,8)
(#=2,3,4,8)
(#=2,3,4,8)

(#=3,4,8)
(#=3,4,8)

A/tera Corporation

I

1

Data Sheet

LMF Support
forTTL
Macrofunctions

PLS-EDIF

1

In addition to mapping the basic functions listed above, Altera-provided
LMFs map various TIL macrofunctions from Dazix, Mentor Graphics,
Valid Logic Systems, and Viewlogic Systems to their MAX+PLUScompatible equivalents. See Table 5.
Table 5. TTL Function Mappings In Altera-Provlded LJfFs

1

Altera Corporation

MAX+PLUS

Oazix

7442
DFF2
7483
7485
7491
7493
74138
74139
74139M
74151
74153
74153M
74157
74157M
74160
74161
74162
74163
74164
74165
74174
74174M
74181
74190
74191
74194
74273
74174M
74279MD
74279M
74280
74373
74373M
74374
74374M
74393M

LS42
LS74
LS83
LS85
LS91
LS93
LS138
LS139

LS151

-

Mentor Graphics

Valid Logic
Systems

Viewlogic
Systems

74LS42
74LS74A
74 LS83A
74 LS85
74LS91
74LS93
74LS138

LS42
LS74
LS83
LS85
LS91
LS93
LS138

74LS42
74LS74A
74 LS83A
74LS85
74LS91
74 LS93
74LS138

-

-

-

74LS139A
74LS151
74LS153

LS139
LS151

-

74LS139
74LS151
74LS153

LS153

-

LS153
LS157

-

-

-

LS160
LS161
LS162
LS163
LS164
LS165
LS174

74LS16OA
74LS161A
74LS162A
74LS163A
74LS164
74LS165
74LS174

-

-

LS181
LS190
LS191
LS194
LS273

74LS181
74LS190
74LS191
74LS194A
74LS273

LS279

-

LS280
LS373

74LS279
74 LS 280
74LS373

-

-

LS374

74LS374

-

74LS393

LS374
LS393

LS393

74LS157

-

LS160
LS161
LS162
LS163
LS164
LS165

LS174
LS181
LS190
LS191
LS194A

LS273

LS279
LS280

74LS157
LS157
74LS16OA
74LS161A
74LS162A
74LS163A
74LS164
74LS165
74LS174

74LS181
74LS190
74LS191
74LS194A
74LS273

-

-

74LS279
74 LS 280
74LS373

LS373

74 LS374

74LS393

Page

2451

I PLS-EDIF
Custom
Library
Mapping
Files

Data Sheet

I

Designers can map their commonly used workstation functions to
MAX+PLUS-<:ompatible equivalents by modifying an LMF or creating a
new one. If no equivalent function currently exists in MAX+PLUS, the
designer can create the function with the MAX+PLU5 Graphic Editor or
Text Editor and then map it in an LMF. Figure 3 demonstrates this process.

Figure 3. Creating a Library Mapping File
Step 1: Select a workstation function for mapping.
ADS

Y)------t=:=> Z

B

c.->--~----~~

Step 2: Design an equivalent circuit with the MAX+PLUS Graphic Editor.

ALIR_A8S
~HD2""

·

.•

.1. . . . . . . :
~HD2""

·

.

.

.NOR3····

..

::~~~~ ~~~: :~~~~~ :: : :

!'t• . • . . • . •

·

~HD2""

..

Step 3: Map the workstation function to the MAX+PLUS function in an LMF.

XUser

Librar~

Mapping FileX

BEGIN
FUNCTION ALTR_A85 (A_IN, B_IN, C_IN)
RETURNS (Z_OUT)
FUNCTION "A85" ("A", "B", "C")
RETURNS ("Z")
END

I Page 246

Altera Corporation

I

1

PLS-EDIFI

Data Sheet

SNF2EDF
Converter

The SNF2EDF Converter creates an industry-standard level 0 EDIF file
from a MAX+PLUS Simulator Netlist File (SNF). The SNF, which is
optionally generated during compilation of a MAX EPLD design, contains
all post-synthesis functional and delay information for the completed
design. This design-specific information is also contained in the EDIF
output file after conversion, so it can be integrated into a workstation
environment for simulation. The user can customize the output EDIF file
for various workstation environments with an optional command file that
renames certain constructs, or changes the EDIF level or keyword le:vel.
See Figure 4.
Rgure 4. SNF2EDF Block Diagram

Optional
Canmand
File

MAX+PLUS
Confi{JJralion
File

The EDIF output file may have one of two formats. The first format
expresses all delays with special EDIF property constructs. The second
expresses combinatorial delays with port-delay constructs and registered
delays as path-delay constructs-a format that is especially useful for
behavioral simulators. Both formats are shown in the example in Figure 5.
Figure 5. EDIF File Formats
Format 1: Combinatorial delays expressed with property constructs

instance xor2_S
( viewRef view1
( cellRef XOR2
propert~ TPD ( inte,er 28 ) ( unit TIME) ) )
Format 2: Combinatorial delays expressed with port-delay constructs

instance xor2_S
( viewRef view1
( cellRef XOR2
port Instance &1
( portDela~
( derivation CALCULATED
( dela~ ( e 28 -18 ) ) ) ) )

1

Altera Corporation

Page 2471

IPLS-EDIF
System
Requirements

Data Sheet I

0
0
0
0
0
0
0
0
0

PLS-EDIF
Contents

0

o
Ordering
Information

I Page 248

IBM PC-AT or compatible computers; IBM PS/2 models 50, 60, 70, 80
DOS version 3.1 or higher
640 Kbytes of RAM
1 Mbyte of expanded memory compatible with version 3.2 or higher
of the Lotus/Intel/Microsoft Expanded Memory Specification
VGA, EGA, or Hercules Monochrome display
20-Mbyte hard disk drive
1.2-Mbyte 5 1/4-inch or 1.44-Mbyte 3 1/:z-inch floppy disk drive
MAX+PLUS version 2.01 or higher
Workstation-to-PC network hardware and software with the ability to
transfer ASCII files
Floppy diskettes containing all PLS-EDIF programs and files for both
PC-AT and PS/2 computers
EDF2CNF Converter
SNF2EDF Converter
Library Mapping Files for Dazix, Mentor Graphics, Valid Logic,
and Viewlogic netlists
MAX+PLUS macrofunctions for Dazix, Mentor Graphics, Valid
Logic Systems, and Viewlogic Systems libraries
Sample files
Documentation

PLS-EDIF

(supports both PC-AT and PS/2 formats)

Altera Corporation

I

PLS·APOLLO
MAX+PLUS Programmable Logic
Software for Apollo Computers

I October1990, ver. 2

Features

Data Sheet

o

Software support for MAX (Multiple Array MatriX) EPLDs

o Runs on Apollo (Hewlett Packard) Series 3000, 3500, 4000, and 4500

o

o
o
o
o

General
Description

I

computers with Domain/OS SR 10.1 operating system
Supports hierarchical design entry for graphic and text designs
Schematic capture with Mentor Grapnics' NETED
Altera Hardware Description Language (AHDL) supporting state
machines, Boolean equations, truth tables, and arithmetic and
relational operations
Full Altera/Mentor Graphics cross-compatibility supplied via
bidirectional EDIF 2 0 0 netlist interfaces
MAX+PLUSCompiler provides logic synthesis and minimization for
efficient device utilization
Generates post-synthesis timing simulation data for use with Logic
Automation's SmartModel and Mentor Graphics' QuickSim simulator
Produces MAX EPLD programming files for use with an Altera PCbased programmer (PL-ASAP) or third-party programming hard ware

The Altera PLS-APOLLO package brings the popular MAX+PLUS
Development System to Apollo Series 3000, 3500, 4000, and 4500 computers
(see Figure 1). PLS-APOLLO includes AHDL design entry, bidirectional

Figure 1. PLS-APOLLO Design Framework

Shading indicates items provided with PLS·APOLLO.

Mentor Graphics

PLS-APOLLO

_ Schematic capture _ Device Slmulallon
_ EDIF Netllst Writer _ Board SImulation

_ AHDI.. Design Entry - logic Synthesis
-

EDlF Nellist Reader
EDiF Netllst Writer

MAX+PLUS TTL MacroFunction
Lbrary, including primitive
functions and over 300 TTL
and custom macrofunctions

I A/tera Corporation

Page 249

I

I~P_L_~_A_P_O_L_L_O___________________________________________________D_a_m~
EDIF netlist interfaces, Mentor Graphics library support, advanced logic
synthesis, and design fitting in the Apollo computer environment. Together,
PLS-APOLLO and Mentor Graphics software provide the tools to quickly
and efficiently create, compile, and verify logic designs for MAX EPLDs.

Design Entry

PLS-APOLLO supports both schematic and textual design entry options.
Hierarchical schematic designs are entered with the Mentor Graphics
NETED schematic capture program. Hierarchical Text Design Files (TOFs)
created in the Altera Hardware Description Language (AHDL) can be
used separately or mixed with NETED schematic designs. AHDL is tailored
especially for EPLD designs and supports com plex Boolean and arithmetic
functions, relational comparisons, multiple hierarchy levels, state machines
with automatic state variable assignment, and truth tables. AHDL designs
can also use over 300 primitives and TTL and custom macrofunctions from
the MAX +PLUS TTL MacroFunction Library.

EDF2CNF
Converter

NETED schematics are converted into EDIF 2 0 0 netlist files with the
Mentor Graphics EDIFNET netlist writer. PLS-APOLLO's EDF2CNF
Converter and Library Mapping File (LMF) then translate each EDIF
netlist into a MAX+PLUS-compatible format. (See Figure 2.) Library symbols
from the Mentor Graphics generic and LSTTL libraries are automatically
mapped to corresponding primitive and TTL functions in theMAX+PLUS
TTL MacroFunction Library. Table 1 shows the mappings provided in the
LMF. PLS-APOLLO users can add to these libraries or build their own
libraries by creating additional Logic Mapping Files. (See "Custom Library
Mapping Files" later in this data sheet.)
Figure 2. EDF2CNF Block Diagram

One or more Library
Mapping FI7es may
be used as inputs.

I Page250

One or more sets of
CNF and HIF files are
generated.

A/tera Corporation

I

I Data Sheet

I

PL5-APOLLO

Table 1. Mentor Graphics Library Mapping File (Basic and TTL Functions)
Mentor Graphics Generic Function

AND#
BUF
DELAY
DFF
INV
JKFF
LATCH
NAND#
NOR#
OR#
XNOR2
XOR2
Mentor Graphics LSTIL Function

74LS42
74LS74A
74LS83A
74LS85
74LS91
74LS93
74LS138
74LS139A
74LS151
74LS153
74LS157
74LS160A
74LS161A
74LS162A
74LS163A
74LS164
74LS165
74LS174
74LS181
74LS190
74LS191
74LS194A
74LS273
74LS279
74 LS 280
74LS373
74LS374
74LS393

MAX+PLUS Primitive Function (1)

AND#
SCLK
MCELL
DFF2
NOT
JKFF2
MLATCH
NAND#
NOR#
OR#
XNOR
XOR

(#=2,3,4,5,6)

(#=2,3,4,5 6,9)
(#=2,3,4,6,8,16)
(#=2,3,4,6,8)

MAX+PLUS TIL Macrofunction (1)

7442
DFF2
7483
7485
7491
7493
74138
74139M
74151
74153
74157
74160
74161
74162
74163
74164
74165
74174
74181
74190
74191
74194
74273
74279M
74280
74373
74374
74393M

Note:
(1)

I A/tera Corporation

Contact Altera Applications at 1 (800) 800-EPLD for the most
mappings.

up-to~ate

list of

Page251

I

I PLS-APOLLO

Data Sheet

MAX+PLUS

Compiler

I

PLS-APOLLO includes the sophisticated MAX+PLUS Compiler, which
synthesizes and optimizes designs for MAX EPLDs in minutes. (See
Figure 3.) The Compiler uses advanced logic synthesis and minimization
techniques together with heuristic fitting rules to efficiently place designs
into MAX EPLDs.

Rgure 3. MAX+PLUS CompIler
.TDFor.EDF

input design
file(s)

The Compiler offers several options to customize the processing and
analysis of a design. The user can set the degree of detail of the Report File
as well as the maximum number of errors to be detected before processing
halts. The user can also choose whether to extract a netlist containing postsynthesis timing information.
Designs are compiled in increments, so that if a design has been compiled
previously, only the new portion is extracted to save time. All errors
encountered during design processing are documented in an Error File
(.E:R:R).
The first module of the Compiler, the Compiler Netlist Extractor, extracts a
Compiler Netlist File (.CtlF) and a Hierarchy Interconnect File (.HIF) from
each file. At this time, design rules are checked for any errors. The Database
Builder module then converts the successfully extracted CNFs and HIFs
into a database to be used by the Logic Synthesizer module.
The Logic Synthesizer translates and optimizes the user-clefined logic for
the MAX architecture. The design is first minimized with SALSA (Speedy
Altera Logic Simplification Algorithm); unused logic is automatically
removed. The Logic Synthesizer module uses expert system synthesis
rules to factor and map logic within the multi-level MAX architecture,
choosing the approach that ensures the most efficient use of silicon resources.

I Page 252

Altera Corporation

I

I Data Sheet

PLS-APOLLO

I

The next module, the Fitter, uses heuristic rules to optimally place the
synthesized design into the chosen MAX EPLD. For MAX devices that
have a Programmable Interconnect Array (PIA), the Fitter also routes the
signals across the PIA, automatically handling all placement and routing
issues. The Fitter issues two files: a Report File (.RPT) that shows how the
design is im plemented in the EPLD and whether any unused resources are
available for additional logic; and a Fit File (.FIT) that preserves pin
assignments for optional future use.
The Simulator Netlist Extractor module optionally creates a Simulator
Netlist File (described later in this data sheet). Finally, the Assembler
creates a Programmer Object File (.POF) from the compiled deSign. The
MAX+PLUS Programmer uses this file with Altera or third-party
hardware to program the target EPLD.
The advanced synthesis and minimization techniques used by the Compiler
allow designs to be placed within the architecture in a matter of minutes.
For exam pIe, a 16-bit counter I shift register com piles in less than 1 minute.
The Compiler is equally efficient when compiling complex designs. For
example, a series of 5 serially linked multiplier ladder circuits that uses
100% of the macrocells and 95% of all expanders in an EPM5128 takes only
10 minutes to compile.
For more information on AHDL, the MAX+PLUS Compiler, and Altera
programming hardware, refer to the PLS-MAX: MAX+PLUS Programmable
Logic Software and PL-ASAP: Altera Stand-Alone Programmer data sheets in
this data book.

SNF2EDF
Converter

The Simulator Netlist Extractor of the MAX+PLUS Compiler optionally
creates a Simulator Netlist File (.SNF) that contains post-synthesis logic
and delay information for the compiled design. PLS-APOLLO's Simulator
Netlist File-to-EDIF Design File (SNF2EDF) Converter can then generate
an annotated EDIF 200 netlist output file with the same information. (See
Figure 4.) The Logic Automation SmartModel for MAX EPLDs can convert
this EDIF file into a behavioral model for use with the Mentor Graphics
QuickSimsimulator.

Figure 4. SNF2EDF Block Diagram

r ................._...........................:::.::]

I A/tera Corporation

Page 253

I

n.a

I PLS-APOLLO
Custom
Library
Mapping Files

Data Sheet

I

A designer can map his or her commonly used NETED functions to
MAX+PLUS equivalents by creating a new LMF. If no equivalent function
currently exists, the designer can create the function in an AHDL Text
Design File, and then map it in an LMF. Figure 5 demonstrates this process.
Figure 5, Creating a Library Mapping RI.
Step 1: Sslsct a Mentor Graphics function for mapping
A05

A

r->--........- - - - - f -....\ ____

z

B

c
Step 2: Design an equivalent circuit in the AIIera Hardware Description Language (AHDL)

TITLE "ALTR_A0S" ;
DESIGN IS "ALTR_ABS"
SUBDESIGN ALTR_ABS
(

A_IN. B_IN. C_IN : INPUT
Z_OUT : OUTPUT ;
)

VARIABLE
Xl. XZ. X3 : NODE
BEGIN
Z_OUT = !(XI I XZ I X3)
Xl
A_IN & B_IN
XZ
A_IN & C_IN
X3
B_IN & C_IN
END ;
Step 3: Map the Mentor Graphics function to the AHDL function in an LMF

%

User

Librar~

Happin, File %

BEGIN
FUNCTION ALTR_ABS (A_IN. B_IN. C_IN)
RETURNS (Z_OUT)
FUNCTION "ABS" ("A". "B". "C")
RETURNS ("Z")
END

I Page 254

A/tara Corporation

I

IDataShHt
System
Requirements

o
o
o

o
o
PLS-APOLLO
Contents

o

o
Ordering
Information

I Altera Corporation

I

PLS-APOLLO

HP Apollo Series 3000, 3500, 4000, or 4500 computer with 5+ Mbytes
of free disk space
Domain/OSSR 10.1 operating system
Quarter-inch cartridge (QIC-24, 9 track) 6O-Mbyte tape drive
Schem3tic capture and EDIF conversion software:
Mentor Graphics NETED version 7.0 (graphics editor)
Mentor Graphics EXPAND (schematic file translator)
Mentor Graphics EDIFNET version 7.0 (EDIF 2 0 0 netlist writer)
EDIF conversion and simulation software:
Logic Automation SmartModel for MAX EPLDs
Mentor Graphics QuickSim version 7.0
Quarter-inch cartridge tape (QIC-24, 9 track) containing all PLSAPOLLO programs and files:
EDF2CNF Converter
Library Mapping Files for converting Mentor Graphics-generated
EDIF 2 0 0 netlists
MAX+PLUS TTL MacroFunction Library
MAX+PLUSCompiler
SNF2EDF Converter
Sample files
Documentation

PLS-APOLLO

Page 255

I

PL-ASAP
Altera Stand-Alone Programmer

IOctober

1990.

Data Sheet

ver. 1

!

Contents

C1
C1
C1

Software 30 krad (Si) for 5.5 V operation,
and in excess of 40 krad (SO for 5.0 V operation. If, on the other hand, the
control gate is grounded during the irradiation, the total-dose radiation
tolerance is reduced to about 14 krad (SO for 5.5 V operation, and to about
18 krad (Si) for 5.0V operation. This behavior suggests that energetic holes
created in the bulk silicon by the radiation and attracted toward the
floating gate by its negative (programmed) charge are the dominant cause
of cell charge loss.
When the control gate of these EPROM cells is grounded during irradiation,
the worst-case result of about 14 krad (SO for 5.5 V operation is the best
estimate of the radiation tolerance of these products. Most radiationtolerance experiments on EPROM technologies include control gates that
are biased at Vcc during at least part of the irradiation.

EPM5000Series EPLDs

Tests for the EPM5000-series MAX EPLDs were performed at radiation
hardness to 6.5 krad (SO under worst-case Vce.
For the EPM5000 series, the EPM5032DC was used as the vehicle for
evaluation. The tests were conducted with a cobalt-60 isotope source with
a dose rate of 117 rad (SI)/s. All irradiation was performed at room
temperature (+25 0 C, ±3), while device-under-test (OUT) Vee was set to
+5.5 V. Nine input pins were pulled to Vee through 1-!dl resistors and three
were tied directly to GND. All output pins, were pulled up to Vee through
1-!dl resistors, while the reserved I/O pins were left open. These
specifications provided a realistic control-gate bias distribution for a typical
design.
Total-dose-induced functional failure thresholds are highly sensitive to
measurement voltage. Under the worst-case military power-supply range
(Vee = 5.5 V), the EPM5032 test devices function properly until total doses
in excess of 6.5 krad (SO are reached. For Vee = 5.0 V, proper functioning
occurs above 13.0 krad (Si) and 17.5 krad (Si) for Vcc = 4.5 V.
Timing parameters were measured using Vcc = 5.0 V. No significant change
in maximum operating speed or propagation-delay times occurred at
levels as high as 10 krad (SO.

I Page272

Altera Corporation

I

I Data Sheet
Conclusion

Total-Dose Gamma-Radiation Hardness of Altera EPLDs I

The differences in the test results between the EP600 and EPM5032 indicate
tha t actual device types used in a final design should be separately evaluated
to verify total-dose effects. The evaluation should include a complete
functional test at the expected operating supply-voltage extremes, as well
as extensive parametric measurements. More complex devices may show
greater increase in response to irradiation if additional features that have
not been checked in these test devices-such as the Programmable
Interconnect Array (PIA)-are included.
Programmed cell margin fell linearly with increasing total radiation dose.
Therefore, to maximize radiation hardness, it is important to program an
adequate cell margin into the EPLD before irradiation. Designers are
advised to use Altera-approved programming systems that provide
optimized cell programming.

IA/tera Corporation

Page 273

I

Contents
I October 1990
Section 10

Application Notes & Briefs
AN2

Replacing 20-Pin PAL and GAL Devices with
EP300-Series EPLDs ........................................................................ 277
AN3
Memory and Peripheral Interfacing with EP-Series EPLDs ...... 281
AN9
Metastabili ty Characteristics of EPLDs ........................................ 289
AN10A Design Entry for the EPS448 SAM EPLD .................................... 297
AN16 Integrating PAL and PLA Devices with the
EPM5032 MAX EPLD ..................................................................... 327
AN19 DSP /Imaging Applications with the EPS448 SAM EPLD ........ 343
AN20 Fast Bus Controllers with the EPM5016 MAX EPLD ................. 355
AN22 DesigningwithAHDL ................................................................... 371
ABB
Counter Design for EP-Series EPLDs ........................................... 389
Designing Asynchronous Latches for EP-Series EPLDs ............ 397
AB9
AB14A A+PLUS State Machine Design Entry .......................................... 401
State Machine Partitioning for EP-Series EPLDs ....................... .405
AB18
EP1810 EPLD as a Bar Code Decoder .......................................... 417
AB27
Timing Simulation for EP-Series EPLDs ...................................... 427
AB54
Estimating a Design Fit for EP-Series EPLDs ............................. .443
AB60
AB63 Multiway Branching with the EPS448 SAM EPLD ................... .449
Vertical Cascading of EPS448 SAM EPLDs ................................ .453
AB65
Input Reduction for the EPS448 SAM EPLD .............................. .465
AB66
AB71
A+PLUS Boolean Equation Design Entry ................................... .475
EPM5000-Series MAX EPLD Timing ........................................... 479
AB75
U sing Expanders to Build Registered Logic in
AB76
EPM5000-Series MAX EPLDs ...................................................... .491
AB77
Design Guidelines for EPM5000-Series MAX EPLDs ............... .497
Optimizing Memory for MAX+PLUS Software ......................... 505
AB78
AB79
Simulating Internal Nodes with MAX+PLUS Software ............ 511
ABB2
Emulating Internal Buses in General-Purpose EPLDs ............... 521
ABB3
Programmable Frequency Divider with the EP630 EPLD ......... 527
DMA Controller with the EPM5064 MAX EPLD ....................... 535
AB84
DRAM Controller with the EP1830 EPLD ................................... 547
AB85

ill
IAltera Corporation

Page27s1

Replacing 20-Pin
PAL and GAL Devices
with EP300-Series EPLDs
1

Application Note 21

October 1990, ver. 3

Introduction

Altera EP300-series Erasable Programmable Logic Devices (EPLDs) have
an I/O architecture that is user-configurable, allowing them to be
functionally and pin-ta-pin compatible with PALs and GALs. These EPLDs
have the following features:

o

o

o
o

Highly flexible user-configurable I/O architecture
"Zero power" (typically 10 to 40 JlA standby)
High speed (tpD = 12 ns) with "quiet" outputs
Directly replaces all common 20-pin PALs and GALs

EP300-series EPLDs can directly replace functions implemented with
20-pin PAL and GAL devices. The EP320 is optimized for low-power
applications, typically consuming 10 JlA when operating in standby mode.
The EP330 EPLD offers very high speed while taking advantage of the lowpower benefits of CMOS. Thus, EP300-series EPLDs offer significant power
savings over conventional fuse-programmable bipolar PALs and CMOS
GALs, and are also erasable and reprogrammable. These benefits, combined
with a highly flexible architecture, enable a single EP300-series EPLD to
replace a variety of other 20-pin Programmable Logic Devices (PLDs).

EP300-Series
Functional
Overview

EP320 and EP330 EPLDs, like PALs and GALs, implement sum-of-products
logic with a programmable-AND/fixed-OR logic array. These EPLDs
provide 10 dedicated inputs and 8 I/O pins. Each I/O pin can be
independently configured for input, output, or bidirectional operation (see
the EP300-Series EPLDs Data Sheet for more information).
The internal architecture of EP300-series EPLDs is divided into 8 macrocells,
each of which implements logiC with up to 8 product terms. An additional
product term controls Output Enable. Each product term represents a
36-input AND gate, whose inputs come from the true and complement
signals of the 10 input pins and 8 feedback paths. Altera's proprietary
programmable I/O architecture allows the deSigner to program output
and feedback paths for combinatorial or registered operation in activehigh and active-low modes.
Pin 1 may be used \0 directly clock all registers, or as an additional inputto
the AND array if no clocking is required. The EP300-series flip-flops are
positive-edge-triggered, i.e., data is registered on the rising edge of the
clock signal. During chip power-up, all registers are automatically reset to
zero.

/ Altera Corporation

Page277/

iIiI

I Replacing 20-Pin PAL and GAL Devices with EP300-Series EPLDs
PAL

Compatibility

Application Note 21

While PAL devices have fixed I/O architectures, the macrocells of EP300series EPLDs are based on a flexible, user-configurable I/O structure that
gives the designer freedom to configure macrocells for combinatorial or
registered operation in active-high or active-low modes. Figure 1 shows
the possible output modes, which can be configured on a macrocell-bymacrocell basis.
Rgure 1. EP30O-Ser/es VO Options
Combinatorial I/O

~]PIN_N'ME

.......

!~
···CO·IF······1PIN NAME

.

.

-

i........................J
Output with Pin Feecback

Output Only

~:"""·TltIN_NAME

i. . . . . . . . . . . .

Active-Low Output (Optional)

Registered I/O

c

C
l ••••••••••••••••••••••••••••••••••••

Output with Internal Feedback

Output Only

c
Active-Low Output (Optional)

Table 1 gives a detailed listing of proper I/O configurations to replace
many commonly used 20-pin PALs and GALs. Table 2 compares the Altera
EP300-series EPLDs with competitive PAL/GAL devices.

IPage 278

Altera Corporation

I

I Application Note 2

Replacing PAL and GAL Devices with EP300-Series EPLDs I

I Table 1. EP300-Series ConOguration for 2O-Pin PAUGAL Replacement
I
I

PAL Part
Number
10H8
10L8
12H6

I

I
I

I

L:J
14H4

I

14L4

I

16C1

16H2

16L2

16H8
and
16HD8
16L8
and
16LD8
16R4

16R6

16R8
16P8

16RP4

I

I
I

L:J
I

I

16RP8
16V8

I

I

EP3()()'Serte.
Pin Numbers
12 to 19
12 to 19
12
13 to 18
19
12
13 to 18
19
12 to 13
14 to 17
18t019
12 to 13
14 to 17
18 to 19
12 to 14
15
16
17 to 19
12 to 14
15 to 16
17 to 19
12 to 14
15 to 16
17 to 19
12
13 to 18
19
12
13 to 18
19
12 to 13
14 to 17
18 to 19
12
13 to 18
19
12 to 19
12
13 to 18
19
12 to 13
14 to 17
18 to 19
12
13 to 18
19
12 to 19
12 to 19

I Altera Corporation

II
I

I
I
I

EP3()()'Sertes
Macrocell Numbers
1 to 8
1 to 8
8
2to 7
1
8
2to 7
1
7 to 8
3 to 6
1 to 2
7 to 8
3to 6
1 to 2
6to 8
5
4
1 to 3
6to 8
4 to 5
1 to 3
6t08
4 to 5
1 to 3
8
2to 7
1
8
2to 7
1
7t08
3to 6
1 to 2
8
2 to 7
1
1 to 8
8
2t07
1
7to 8
3 to 6
1 to 2
8
2to 7
1
1 to 8
1 to 8

OutputlPolarlty

110 Configuration Mode

I
I

I

Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Combinatorial
Registered
Combinatorial
Combinatorial
Registered
Combinatorial
R~istered

Combinatorial
Combinatorial
Combinatorial
Combinatorial
Registered
Combinatorial

I

CombJHigh
CombJlow
None
CombJHigh
None
None
Com b Jlow
None
None
CombJHigh
None
None
CombJLow
None
None
Comb.lLow
CombJHigh
None
None
Comb.lHigh
None
None
Comb.llow
None
CombJHigh/Z
Comb.lHigh/Z
Comb.lHigh/Z

CombJlow/Z
CombJlow/Z
Comb.lLow/Z
Comb.lLow/Z
Reg.llowlZ

Comb.llow/Z
CombJLow/Z

Feedback

I

I

I
I
I

I
I

Reg.llow/Z
Comb.lLow/Z

I
I
CombJOption/Z I
R~.ILow/Z

Comb.lOptionlZ
Comb.l°etionlZ

CombJOption/Z
Reg.lOptionlZ

Comb.IOetion/Z

I

None
None
Pin
None
Pin
Pin
None
Pin
Pin
None
Pin
Pin
None
Pin
Pin
None
None
Pin
Pin
None
Pin
Pin
None
Pin
None
Comb.
None
None
Comb.
None
Comb.
Reg.
Comb.
Comb.
Reg.
Comb.
R~.

None
Comb.
None
Comb.
Reg.
Comb.

Combinatorial
Registered
Combinatorial

Reg.lOption/Z
Comb.l°etion/Z

Comb.
Reg.
Comb.

R~istered

R~.IOption/Z

R~.

Combinatorial
Registered

CombJReg.
°etiontZ

CombJReg.

Comb.lOption/Z

Page 279

I
I
I
I

I
I

I

I

11m
II

I
I

I Replacing 20-Pin PAL and GAL Devices with EP3oO-Series EPLDs

Application Note 2 I

Table 2. Comparison of EPLD and PAUGAL Features

EPLD

Feature

Array"l~ic

I

PAUGAL Device

EP300 Series

16L8

16R8

16V8

AND-OR

AND-OR

AND-OR

AND-OR

Inputs

17

16

10

17

Outputs

a

a

a

a

Array input lines

36

32

32

Product terms

72

64

64

a

n.a.

a

No

No

D-!Y..ee flip-floes

I

I

Reprogrammable

I

Output
Enable

Yes

I

~
I
I

I

a

Yes

Every output of the EP320 and EP330 has a tri-sta te buffer that is controlled
by a dedicated product term. When the product term is high, the output is
enabled. Since the Output Enable logic is implemented directly in the
AND array, it can be programmed active-high or active-low, or conditionally
asserted by any of the selected inputs and feedback paths.
Tri-state combinatorial outputs are implemented similarly in EP300-series
EPLDS and PAL/GAL devices. However, PALs and GALs use 1 of the 8
product terms in the macrocell to control the buffer, leaving only 7 product
terms for logic. In contrast, EP300-series EPLDs provide an additional
product term, allowing the 8-input OR gate to remain intact.
Registered PALs hard-wire the Output Enable function to pin 11, forcing
active-low operation. However, EP300-series EPLDs can connect the true
complement of pin 11 to the Output Enable product term, giving the
designer the ability to preserve exact compatibility or the flexibility to
configure the device for a particular system.

Design Tools

IPage 280

Logic is implemented with Altera's A+PLUS Development System, which
supports schematic capture, state machine, Boolean equation, and netlist
design entry methods. Logic schematics, created with LogiCaps, allow the
user to quickly construct a wide range of designs (see the PLS-SUPREME
Data Sheet in this data book). After the design is entered, A+PLUS
automatically translates it into logic equations, performs Boolean
minimization, and fits it into an Altera EP300-series EPLD. The device can
then be programmed in seconds at the designer's desktop to create
customized working silicon. Extensive third-party support also exists for
design entry, design processing, and device programming. Altera also
provides several free software utilities to quickly convert PAL and GAL
designs into EP300-series EPLDs. See Application Brief 73 (Software Utility
Programs) in the Development Products section of this data book, or contact
Altera Applications at 1 (BOO) 800-EPLD for more information.
A/tera Corporation

Memory and
Peripheral Interfacing
with EP-Series EPLDs
1

Application Note 31

October 1990, ver. 4

Introduction

Programmable Logic Devices (PLDs) have long been used for address
decoding and other microprocessor support functions. PLDs offer faster
decode times and require little PC board space. Erasable Programmable
Logic Devices (EPLDs) offer the additional benefits of significant power
savings and a more efficient debugging cycle.
This application note discusses the following subjects:

o Designing address decode and chip-select logic
o Wait-state generation

o

Dynamic RAM (DRAM) control

This application note shows how to interface the Intel 8086 (synchronous
data bus) and the Motorola 68000 (asynchronous data bus) to several
memory and peripheral devices with the EP610 and EP330 EPLDs.

Intel 8086
Solutions

This section describes how to use the EP610 EPLD with the Intel 8086
device.

Address Decoding
The circuit in Figure 1 shows an EP610 EPLD that provides chip-select
signals in a high-speed serial-data-line m ul tiplexer. This circuit is controlled
by an 8086 microprocessor program stored in a 2764 EPROM. A 6164 static
RAM stores data packets as they are assembled for transfer. Four serial
communication control (SCC) peripheral chips provide an interface between
the 8086 CPU and the serial data lines.
The EP610 in this design decodes the address lines of the 8086 into chipselect signals for the computer's peripherals (RAM, ROM, and seC). The
EP610's outputs follow the memory map shown in Table 1. The Boolean
equations in this table describe the memory map for a 16-bit address bus; a
more complicated memory map can be implemented by changing the
equations. An Altera utility program, called DECODER, automatically
derives equations for complicated memory maps. See Application Brief 73
(Software Utility Programs) in the Development Products section of this data
book for more information.

I Altera Corporation

Page281 I

1m

I Memory and Periphersllnterlacing with EP-Series EPLDs

Application Note 3

I

Figure 1. 8086-EP610 Interfacs
The EP610 EPLD controls the ROM, RAM, and sec chip-select logic, as well as the wait-state generation.
Syslem
Clock

ClK

8284

to lOW-speed
communications
transceivers and
lines

'-----it--!/CS

to high-speed
communications
transceivers and
lines

Table 1. Address Decode Memory Map Table
Signal
Low
High
Name Address Address

I Page 282

Equation

ROM

0000

1FFF

A15'. A14'. A13'

RAM

2000

3FFF

A15'. A14'. A13

SIOO

8000

OOFF

SI01

8100

81FF

A15. A14'. A13'. A12'. A11 '. A10'. A9'. A8'
A15. A14'. A13'. A12'. A11'. A10'. A9'. A8

SI02

8200

82FF

A15. A14'. A13'. A12'. A11'. A10'. A9. A8'

SI03

8300

83F.F

A15. A14'. A13'. A12'. A11 '. A10'. A9. A8

SI04

8400

84FF

A15. A14'. A13'. A12'. A11'. A10. A9'. A8'

Altera Corporation

I

I Application Note 3

Memory and Peripheral Interlacing with EP-Series EPLDs

I

Wait-State Generation
The EP610 also performs wait-state generation. It is inefficient to run a
microprocessor at the speed of its slowest peripheral chip. Instead, the
microprocessor is usually clocked at its top speed, and a wait-state generator
slows the microprocessor's bus cycles when the the slowest peripheral is
selected. A wait-state generator is typically implemented with a counter
and a handful of decode logic. Figure 2 shows the state table for an 8086
wait-state generator. To implement a wait state, the READY signal must be
driven low before the falling edge of T2. When accessing the ROM, the
EP610 asserts the READY signal low for one 8086 clock cycle (i.e., one wait
state). READY is asserted low for two clock cycles (Le., two wait states) if
the RAM is selected. For either wait state, a memory read or write (MR DC or
MUTC) and address latch enable (ALE) must be valid. Figure 3 shows the
EP610 logic required for both the address decode and wait-state circuits.
Figure 2. EP610 Wait-State Generation
To implement an 8086 wait state, the READY signal
must be /ow before the falling edge of T2.

One processor cycle (with one wait state)

System Clock

L

Memory Cycle
WAIT

READY

WO

W1

Device

STANDBY

L
H

L
L

RESET

WAIT1
WAIT2

H

H

RAM

State Name

! Altera Corporation

ROM

Page283!

IMemory and Peripheral InterfaCing with EP-Serles EPLDs

Application Note 3 I

Figure 3. EP610 Address Decode and Wait-State Generator Logic Schematic
A1S

~I

ROMS.A1S'·A14'·A13':
ROMS

INP

A14

~ r--::~~"":,,,,:,,:~"':"":":'"~~---------'
INP

I

RAMS .A1S'·A14' .A13;

INP

A11

~

I

S101.A1S ·A14' ·A13' 'A12' ·A11' 'A10' .A9'.AS';

·

.

··

I'''''']'' 1
~i/S'01
!......
i
~!/SI02
I"""
i
~i/S103

INP

SI01

OONF"

~
.-------------------,
INP
I SI02. A1S. A14'· A13'· A12'· A11'. A10'. A9'. AS;

SI02

j .. CONF ..

SI03

j"CONF"

A10~
INP

A9

.

RAMS !······]··CONF·l
~. RAM

A13~
A12

~"""]"OONj:""1/ROM

~.

~ I S103.A1S ·A14' ·A13' ·A12' ·A11' ·A10' ·A9 • AS';

INP
AS ~ ,--_ _ _ _ _ _ _ _ _ _ _ _ _- - ,
INP
SI04=A1S.A14'.A13'.A12'.A11'.A10'.A9.AS;

I

SI04

!·....·].. coNj:..·i

~1/s'04
r•••••••••••••••••••••• :

AND2
ALE CIN=P>--.--------r~r-_V_A_LlD~.
MRDC C=>--+---""""r'--"'"
INP
MWTC

c=>--+------I
INP

C

........................
ClK

c=>--+-~--~~--~--;~~~-~

INP
NOT

Motorola

68000
Solutions

IPage 284

Figure 4 shows a 68OOO-based system with an EP610 programmed as a
wait-state generator and address decoder. Wait states in a 68000 circuit are
easily generated by controlling the DTACK (Data Transfer Acknowledge)
signal. The clock pulses are counted by two or three flip-flops after the
assertion of one of the 68000' s data select lines, LDS and UDS. The flip-flops
then assert DTACK after a programmed count is reached. The programmed
terminal count depends on the speed of the selected peripheral device,
allowing different numbers of wait states for different peripherals.

A/tera Corporation

~plication Note 3

Memory and Peripheral Interfacing with EP-Series EPLDs

I

Figure 4. 68000-EP610 Interface
The EP610 implements both address decode and waitstate generation for RAM and ROM memory devices.
.--_ _ _ _---, External Reset

/RESET .....~~......

to ROM chip selects
to RAM chip selects

68000
IWR~--"'"

IUDS ~--......
ILDS~--"'"

IDTACK

from other
peripheral chips
or their wan-state
generators

.---~_.--~

IBERR

OOOOO-<>FFFF

ROM

10000-1 FFFF
2OOOO-2FFFF
3OOOO-3FFFF

RAM

4oooo-4FFFF

RAM

SOOOO-SFFFF

UNUSED

RAM

UNUSED

6oooo-6FFFF

ROM

ROM

70000-7FFFF

SET MODE 1

UNUSED

MOOED

MODE 1

Figure 5 shows the logic schematic for the EP610. The design provides two
chip-select signals, one for 256 Kbytes of DRAM (RAMENL) and the other
for 64 Kbytes of ROM (ROMENL). The EP610 asserts DTACK one clock cycle
after ROM is selected, providing the ROM with two wait states (UAIT2), two
clock cycles after a RAM read (UAIT4), and three clock cycles after a RAM
write (UAIT6).
As an added element of security, the 68OOO's bus error line (BERR) is
asserted if neither RAM nor ROM is selected and if the DTACKIN signal is
not asserted before the eighth wait state. This feature is useful in industrial
control applications, for example, to signal a controller fault or to reset the
system after a fault. This design requires only half of an EP610 EPLD for
implementation.

I A/tera Corporation

Page28s1

1m

[Memory and Peripheral Interfacing with EP-8erles EPLDs

Application Note 3

Figure 5. EP610 Address Decode and Walt-State Logic
As5?------lIAHi~~==~~;=~--------------------------~

A16

C)>------,

A17 c:::::>---...,
A18C:::::---""
A19

~-"-'---4"':'

mACKNLc:::::~NO~T___________~D~T~AC~K~N~__________________________- - ,
INP

WRITE

WRLc:::::>--_~

_______~R~~~D_ _ _ _ _ _ _- ,

ANoo

INP

··........................................
:

P

RORF

:

RAMEN

NOT

,...•.....•c ........................

STANDBY

.1.'"

CLKc:::::>---~~~----+~~---.

INP

WO

W1

Device

STANDBY

L

WAIT4

H
H

L
L

RESET

WAIT2

RAM READ

WAITS

L

H
H

State Name

IPage 286

ROM
RAM WRITE

Altera Corporation

I Application Note 3

Dynamic
RAM Control

Memory and Peripheral Interfacing with EP-Series EPLDs

I

DRAM circuits must generate the RAS, CAS, and L1R control signals for the
DRAMs, MAS (memory address select) for the address decoder, and a
DTACIC or READY line to acknowledge the data transfer to the CPU. DRAM
controllers connected to some 16-bit microprocessors may use either half
of the 16-bit bus for 8-bit transfers. In addition, DRAMs must be refreshed
by the DRAM controller, a DMA channel, or an interrupt-driven computer
software loop during each bus cycle or while in burst mode.
Figure 6 shows a DRAM controller design for the EP330 that handles all of
the above actions. The EPLD performs the following steps:
1.

Places half of the CPU address on the DRAM's address lines and
negates MAS.

2.

Asserts the RAS address strobe.

3.

a)
b)

Places the second half of the CPU address on the DRAM's address
lines (asserts MAS).
Asserts the DRAM's UR line if the bus transfer is a write opera tion.

4.

Asserts the CAS signal.

5.

Waits for the bus cycle to finish, then negates all signals.

An EP330 programmed with the design shown in Figure 6 remains in a
state with all signals negated (step 1 above) until a bus cycle is started with
RAMEN and UDS or LDS. The EP330 then cycles through the steps listed
above at a rate set by the clock, stopping at step 5 until the bus cycle ends
(Le., RAMEN, UDS, and LDS negate), and returning to step 1 to wait for the
next bus access.

I Altera Corporation

Page 287

I

,. Memory and p'!riehe~ral.lnterlacing with .EP~ries EPLDs

Application Note 3

Figure 6. EP330 Dynamic RAM Control
The controller's clock frequency must be exactly the same as the 68000 system clock.
NOR!

RAMEN

RAMCYCn

INP

REF

DRAM
Wtie

INP

DRAM
Column
Adctesa
Slrobe

NOT
WRL

WRITE

INP

.............................

NOT
IJDSl

AONF

INP

Memory
Adctesa

SeIec:I

DATASEL
LDSl

INP

··...........................................
:

~--l-L;r-Hr-tt-tt:--t>

BANKSEL

RORF

,..........................-...1"'"

:

...............1 ...,...

INP

DRAMAow
Address Slrobe

c~~-----------~==~~~~--+-~
INP

Page 288

Altera Corporation

I

Metastability
Characteristics
of EPLDs
Application Note 91

October 1990, var. 2

Introduction

This application note provides the following information:

o
o
o
o

Definition of metastability
Description of an experimental setup for metastability measurements
Metastability characteristics of Altera EPLDs
How to calculate MTBF numbers

The application note describes the problems associated with
synchronization of asynchronous signals, in particular, the phenomenon
of metastability in clocked flip-flop elements. To help the designer predict
and guarantee required mean-time-between-failure (MTBF) rates in circuits
targeted for Altera EPLDs, this application note also presents experimental
data for Altera EPLDs when the associated flip-flops are used in
asynchronous signal synchronizer applications. This information can then
be compared to data on standard TIL components, which is also provided.
Altera EPM5000-series MAX EPLD flip-flops show metastability
characteristics ranging from those of Advanced Low-Power Schottky (ALS)
TTL flip-flops to Fairchild Advanced Schottky (FAST) TTL flip-flops.
Altera's EP-series EPLD flip-flops show metastability characteristics that
are better than those of Low-Power Schottky (LS) TTL flip-flops.

Synchronization

Many designs require communication between asynchronously clocked
systems to be synchronized. Most systems are designed synchronously so
that all signal transitions within, and generated by, a system use an edge of
a master clock as reference. Synchronous systems also require synchronous
inputs to avoid race conditions, setup time violations, and other logic
problems. The goal, therefore, is to synchronize external inputs with each
system's local clock to ensure that operation and MTBF requirements for
the composite system(s) are met.
The edge-triggered flip-flop is frequently used to obtain synchronization.
Clocked by the system's master clock or a derivative, the flip-flop
synchronizes transitions on its data input with the clock, and outputs the
result to the system. Its output transitions are synchronous with its clock.
However, when asynchronous signals are synchronized, the minimum
timing requirements of the flip-flop cannot be guaranteed. For example, if
a signal changes at a flip-flop's data input from low to high at the same
time as the clock, the output state is ambiguous. Since the minimum setup

I A/tera Corporation

Page 289

I

m
aa:.-

1

Application Note

Metastability Characteristics of EPLDs

91

and hold times are not met, electrical parameters and logic functions are no
longer guaranteed. The combination of these logical! electrical uncertainties
manifests itself in a state known as metastability (see Figure 1).
Figure 1. Metastability Characteristics
5
Metastability
Point

0./0
/Q

a

Va

logic low

CMOS Flip-Flop

o

5
Volts
Flip-Flop Output
Switching Waveform

Metastability

A flip-flop is typically defined as a bistable element, with the /0 output at
logic high and the 0 output at logic low, or vice versa. However, the
description "bistable" is misleading, since a third stable state is possible
where both nodes are at identical voltages. This third state is called
"metastable," since the smallest disturbance will push the flip-flop in one
direction or the other. Although the flip-flop does eventually stabilize, it
hovers in a metastable state while /0 and 0 are both at equal
(indeterminate) logic levels.
Clocking a flip-flop while its data input is in transition-which may
happen during synchronization-can create such a metastable event. The
resulting indeterminate output logic levels can, in fact, produce
unpredictable results if allowed to propagate throughout the system. The
likelihood of encountering this metastable period depends on the width of
the window and the signal frequencies being synchronized. The following
experiments confirm this conclusion.
The basic equation for the MTBF of a synchronizer due to metastability
events is:
MTBF = [FCLOCK x FDATA x Ccl x e(-C2 XL1TI]-l
If this equation is plotted on semi-log graph paper, the MTBF / ~T
relationship appears as a straight line (Figure 2). In the equation shown
above, ~T represents the amount of settling time allowed for the flip-flop
to settle to a valid stable state.

I Page290

Altera Corporation

I

I Application Note 9

I

Metastability Characteristics of EPLDs

Rgure 2. Metastability Function & Effects of Parameters
109

Increasing
Frequency

-10 Years
8

10

-1 Year
107
-1 Month

~ 106 -1 Week
~

::::E 105

g>

-1 Day

...J

4

10

-1 Hour
103
102 -1 Minute
101 -10 Seconds
10°
10

20

30

40

50

60

70

Settling Time (£\T)

The constants C1 and C2 in this equa tion reflect particular characteristics of
the device and, more importantly, the process technology used to
manufacture it. Different devices fabricated on the same technology have
similar metastability characteristics. Device design tricks and optimiza tions
do not have a marked effect. Fundamental technology parameters such as
on-chip capacitances and inverter gain predominate.
The constant C1 linearly scales the MTBF equation. Therefore, the smaller
the value of Cl , the higher the MTBF. Cl affects the MTBF/ L\T curve in an
absolute sense, tending to translate it along the MTBFaxis.
The constant C2 affects the slope of the MTBF / L\ T plot. Therefore, it is a
measure of how quickly, in a relative sense, the flip-flop snaps out of
metastability. The steeper the relationship on the plot, the better the
settling.
The equation indicates that MTBF is a linear function of clock and data
frequencies. Results for other operating conditions can be predicted with
the data for a set of input frequencies.

Experiment
Setup

I Altera Corporation

To help evaluate the relationship between metastability-event frequency
and input-signal frequencies, the following experiment shows a means for
defining and measuring a metastability event. In this experiment, a flipflop is defined to be in a metastable state whenever its output voltage Q is
greater than Vn.. maximum and less than Vrn minimum for longer than
normal output transition times. For TTL levels, this state corresponds to 0.8
V < output voltage < 2.0 V.

Page291

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I Metastability Characteristics of EPLDs

Application Note

91

An experimental circuit for measuring a metastable event must include the
following items:

o

A Device Under Test (DUTI, i.e., the synchronizing device to be
evaluated

o

Two independent signal sources that act as local system clock and
data inputs

o

A way to compare the OUT's output to Vrn and V1L levels. Such a
comparison can be performed with dedicated comparator devices, or,
as shown in Figure 3, with inverters that have appropriate bias voltages
applied to the device grounds. The inverter arrangement is a veryhigh-speed arrangement-with a few nanoseconds delay, dependent
on logic family-and requires fewer power supplies than most
dedicated comparators.

Figure 3. Experiment Setup

a

FOATA

7-Segment LEOs
Metastability Event
Readout
FCLOCK

FCLOCK

FDATA - 1/2 FCLOCK _ _ _....J

DELTA CLOCK - - - . . . . ,

DUTa

I Page292

-~
Altera Corporation

I

I Application Note 9

Experiment
Results

I Altera Corporation

Metastability Characteristics of EPLDs

I

o

A means to strobe the comparators' outputs at variable delay times
from the OUT clock to detect a metastable event of a given duration.
As shown in Figure 3, strobing can be provided with an inverted
version of the OUT clock. By varying the width of the OUT clock
pulse, a variable delay between the two rising edges is obtained.

o

A counter that counts the metastable events. In this experiment, the
data measured is the number of metastability events as a function of
AT and length of observation. Length of observation divided by the
number of events gives an MTBF number. Plotting the data yields the
characteristic lines.

The experiments analyze not only Altera's EPLDs for metastability
characteristics, but also several other logic devices, including standard
TTL 7474 devices from LS, ALS, and FAST logic families. The plotted data
is shown in Figure 4. The results are summarized here:

o

Metastability characteristics of devices in a given family are Virtually
identical since these characteristics are technology-dependent rather
than individual device/ circuit-dependent.

o

MAX devices exhibit metastability characteristics that are substantially
better than those of EP-series devices because they are fabricated on a
faster O.B-micron double-metal process. The technology dependence
of flip-flop settling time is thus reinforced.

o

Altera's EPM5000-series MAX EPLDs exhibit metastability
characteristics that are equivalent to those of FAST-TIL series devices.
When integrating such designs, EPLD flip-flops may be used as
synchronizers with equivalent characteristics.

o

In cases where very fast settling time is required of a synchronizer,
AS-TTL logic still provides characteristics that are superior to highdensity solutions such as EPLDs.

o

Integrating multiple logic levels into a single EPLD, can often reduce
the need for rapid stand-alone settling times. This option is available
when isolated performance is not critical.

PBge293

I

1

Application Note

Metastability Characteristics of EPLDs

91

Rgure 4. Results of the Experiment
109
-10 Years

EP630

74ALS74

74F74
-1 Year
-1 Month
-1 Week

u.

~

:E 105 -1 Day

~

...J

104
-1 Hour
103
102 -1 Minute
101

-10 Seconds

10°
10

20

50
Settling Time (AT)

90
FeU( - 1 MHz
FoATA - 500 kHz

Vee

- 5 V Room Temp

Given the plotted data, the derivation of the two constants C1 and C 2 for the
MTBF equation is relatively easy. C2 defines the slope of the line. Once C2
is defined, C1 can be determined. When FOATA = 0.5 X FCl(xX (representing
a transition on every synchronizing clock edge), the equations reduce to

C1 = 2 x e(C2x~T) / MTBF x f2
Table 1 summarizes the values of C1 and C2 for Altera's EPLDs as well as
alternative devices. From these values, MTBF calculations can be made for
a particular system/ clock rate/ device combination.

I Page294

A/tera Corporation

I

I Application Note 9

Metastability Characteristics of EPLDs

I

Table 1. Metastability Equation Constants vs. Device

C1

Device
EP630
EP610
EP600
EP1810
EPMS016/EPMS032
EPM5064
74F74
74 LS74

3.081E+52
4.SS7E+12
1.916E+22
3.529E+38
4.981 E+20
4.747E+11
6.100E+21
5.270

C2
5.415
1.919
1.340
2.068
2.482
1.641
4.000
0.5081

The following example assumes use of an EPM5032 in a synchronizing
application and requires MTBF of one year (approximately 3x 107 seconds).
The system clock rate is 10 MHz, while the input to be synchronized has a
frequency of 2 MHz. To calculate the minimum settling time allowance
required to assure the specified MTBF, the constants shown below are
used for the EPM5032 to solve the metastability equation:
MTBF = [FCLOCK x FDATA X C1 x e(-C2 x,\T)]

-1

Settling time required is:
L\T = In [MTBF x FCLOCK x FDATA x C1 ] / C2

Substitution provides the following result:
In [3x107 x 1Ox1()6 x 2x1()6 x 4.981E+20] /2.482

L\T

=

In [2.989 x 1()41] / 2.482

=

95.5 / 2.482 = 39 ns

To ensure an MTBF of one year with an EPM5032, the application should
allow approximately 39 ns of settling time before the output of the EPM5032
synchronizing macrocell is evaluated or required to be stable elsewhere in
the system. Similar calculations can be made for any combination of
MTBFs and clock/data frequencies. Due to the logarithmic relationship
between MTBF and settling time, dramatic changes in MTBF can be obtained
from small changes in L\T. For exam pIe, if the MTBF requirement is increased
from ore year to ten years in the calculations shown above, the L\T allowance
need only be increased by 2 ns to 41 nsf Increased design margin is
relatively inexpensive and should be examined for each individual
application.

I Altera Corporation

Page 295

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I Metastability Characteristics of EPLDs
Conclusion

Application Note

91

Altera's EP-series EPLDs have metastability characteristics that make these
devices superior to standard LS-TIL flip-flops when used in synchronizer
applications. They also outperform typical low-power PAL devices
substantially. Characteristics of EPM5000-series MAX EPLDs offer
characteristics that are suitable for today's high-speed applications, and
make these devices superior to ALS-TIL. Given the required settling time,
any required MTBF may be predicted and obtained for circuits using
Altera EPLDs.
When designing synchronizer circuits, it is prudent to provide adequate
guardbands. Synchronization is probabilistic at best, and MTBF numbers
only show mean or average times taken over a large sample. A circuit may
have an MTBF of ten years, yet still has a probability of failure in its first
few minutes of use. In all high-reliability applications, the potential of a
metastable event can never be totally discounted.

I Page296

Altera Corporation

I

Design Entry
for the EPS448 SAM EPLD

I October 1990, ver. 1
Introduction

Application Note 1DA I
This application note describes design entry methods for the Altera EPS448
Stand-Alone Microsequencer (SAM) EPLD. The following subjects are
included:

o
o
o
o
o

An overview of the SAM+PLUS Development System used in entering,
compiling, simulating, and programming EPS448 designs
A discussion of applications suited for the EPS448 EPLD
Descriptions of the two entry languages supported by the EPS448
EPLD-the Altera State Machine Input Language (ASMILE) and the
SAM Assembly Language (ASM)
A 68020 microprocessor bus arbiter application example that
demonstrates ASMILE entry
A graphics controller application example that demonstrates ASM
entry and cascading of multiple EPS448 EPLDs in large designs

Figure 1 shows a block diagram of the EPS448 EPLD. (Refer to the EPS448
SAM EPLD: Stand-Alone Microsequencer Data Sheet in this data book for more
information.) A general knowledge of EPS448 architecture is assumed.

Figure 1. EPS448 Block Diagram

Outputs

(FO to F1S)

I Altera Corporation

Page 297

I

I Design Entry for the EPS448 SAM EPLD
SAM+PLUS
Development
System

Application Note 1DA

I

The SAM+PLUS Development System (Figure 2) provides an efficient PCbased method for entering and compiling EPS448 designs. SAM+PLUS
also allows interactive functional simulation for rapid verification of design
operation. PC-compatible programming hardware and LogicMap II
software allow EPLO programming right at the designer's desk. The
accelerated design process that SAM+PLUS provides is very helpful because
control logic is often difficult to design and design changes are common.

Figure 2. SAM+PLUS Development System

SAM+PLUS supports two design entry methods:

o
o

ASMILE - a state machine input language
ASM - a microassembly language

To create a design with either language, the designer first enters the design
file with any standard text editor. The file is then submitted to the SAM
Design Processor (SOP), which converts it to ASM format if it is in ASMILE
format. The SOP automatically minimizes transition equations in the ASM
file and generates a standard JEOEC file for simulating the design and
programming the EPS448 EPLO. The SOP also generates a Report File that
lists total resources consumed, absolute memory assignments of
microassembler instructions, and pin assignments.
The SAM Simulator (SAMSIM) provides functional testing of EPS448
designs, including multi-EPLO applications with horizontal cascading.
The Virtual Logic Analyzer (VLA) in SAMSIM provides the designer with
a graphical display of the simulation results. In addition, the designer may
print out a hard-copy waveform output file.

Choosing
EPS448
Applications

I Page29B

The EPS448 architecture supports high-performance synchronous control
applications. It has a classic Moore machine architecture, i.e., all outputs
are asserted synchronously with respect to the clock. All inputs must also
obey a required setup time (tsu) relative to the clock input.

Altera Corporation

I

I Application Note 1DA

Design Entry for the EPS448 SAM EPLD

I

Applications with the following characteristics are most likely to fit into a
single EPS448 EPLD:

o
o
o
o
o
o
o

Operating frequency of up to 30 MHz
Synchronous operation
Up to 8 control inputs exclusive of Clock and nRESET
Up to 16 control outputs
Up to 256 primary microcode locations
Up to 64 multiway-branch microcode locations
Transition expressions reducible to four product terms per IF-THE"
expression

Horizontal cascading is used to obtain more than 16 outputs in an EPS448
design. Similarly, EPS448 EPLDs may be vertically cascaded-sharing a
common output bus-if greater microcode depth is required. Horizontal
and vertical cascading may be used simultaneously to increase capacity in
both dimensions. For example, SAM +PLUS supports horizontal cascading
of up to 8 EPS448 EPLDs, for a total output count of 128 lines.

ASMILE

Syntax

The ASMILE file consists of the following sections (sections enclosed in
brackets are optional):

[Header]
PART:
INPUTS:
OUTPUTS:
[EQUATIONS:]
MACHINE:
[CLOCK:]
STATES:
Transition Specifications
END$
Note that the ASMILE input format is very similar to the State Machine
(SMF) format used with A+PLUS and Altera's EP-series EPLDs.
ASMILE files may be entered with any standard text editor in non-document
mode. (Format control characters inserted in document mode are interpreted
as syntax errors during compilation.) Filenames have the extension .SI1F.
The case of characters in the ASMILE file is significant. For example, the
names RUB and rwb are not the same. Comments enclosed in percent
symbols (Yo) may be inserted freely into the source code as shown in the
following example:
%

Header
Section
I Altera Corporation

This is a COMMent %

The Header Section contains design identification information. Typical
information includes the designer's name and company, date, design
number and revision, and other comments.
Page 299

I

I Design Entry tor the EPS448 SAM EPLD

Application Note 1DA

I

Part Section

The Part Section of the ASMILE file (keyword PART:) specifies the EPS448
EPLD as the target EPLD for the application.

Inputs
Section

The Inputs Section (keyword INPUTS:) defines all external inputs to the
design and optionally assigns pin numbers to the inputs. SAM+PLUS
automatically assigns any remaining pins. Pin assignments are specified in
the following format:

Only user-defined inputs can appear in the Inputs Section, e.g., the dedicated
Clock and nRESET inputs to the EPS448 EPLD are not included.

Outputs
Section

The Outputs Section (keyword OUTPUTS:) contains a list of all outputs
from the design and optional pin assignments. Output pin assignment
syntax is the same as for input pins.

Equations
Section

The Equations Section of the ASMILE file (keyword EQUATIONS:) is used
to define intermediate equations to be used later in the design. For example,
the following equation can be defined in the Equations Section:
E~entClk =

11 • /14 + 13 • 16 • /17

The designer can then use EYentClk inanIF-THEN statement later in the
file instead of entering the actual equation.

Machine
Section

The Machine Section of the ASMILE (keyword HACHINE:) file specifies a
state machine's name and the state, output, and transition definitions
required for the EPS448 EPLD. It has the following structure:
State machine declaration
Clock Subsection (optional)
States Subsection
Transitions Subsection

State Machine Declaration
This declaration gives the name of the state machine. It has the following
format:

Clock Subsection
The optional Clock Subsection (keyword CLOCK:) specifies the
synchronous clock source for the EPS448 EPLD.1t is used primarily for
documentation purposes.

I Psge3DD

Altera Corporation

I

I Application Note lOA

Design Entry for the EPS448 SAM EPLD

I

States Subsection
The States Subsection (keyword STATES:) specifies all states in the
machine and the outputs corresponding to the states. The States Subsection
has the following format:
STATES:

[output_na"e_l ... output_na"e_nl
[output_value_list]

state nill-Ie

The first line contains a list of output names enclosed in brackets and
separated by white space. Each subsequent line contains a state name
followed by a binary string enclosed in brackets, which specifies all output
values provided when the machine is in that state. For example:
STATES:

[

S8

[ 8 8 88]

ABC D ]

SI

[ 8 1 18]

S2
S3

[ 1 888 ]
[ 888 1 ]

This States Subsection specifies a machine with four outputs A, I, C, and D.
State S8 has all outputs low; S1 takes I and C to logic high; S2 has only
output A high; and S3 has only output D high.

Transitions Subsection
The Transitions Subsection in an ASMILE file (no keyword) has the
following format:
state_na"e:

transition_specification

Every state in the machine must have a transition specification that specifies
successor states with either unconditional (e.g., S8: S2) or conditional (IFTHEN) statements.
The first state name in the Transitions Subsection is defined as the initial
state of the machine coming out of reset. This state name has special
significance as an "inactive" or passive machine state. The position of other
transition specifications is not significant.
IF-THEN Statements
The EPS448 architecture implements the user-defined state transition
specifications in the branch-controllogic block. This block allows up to 64
complex branching expressions to be specified in a single machine. (Up to
192 unconditional state transitions can be specified for a single EPS448
EPLD.) Multiway branching is shown in Figure 3.

I Altera Corporation

Page301

I

!Ii'
11:.1

I Design Entry for the EPS448 SAM EPLD

Application Note 1DA

I

Rgure 3. EPS448 Mult/way Branch

Each IF-THEN statement may be a function of any of the eight EPS448
external inputs and may contain up to four product terms after logic
minimization. For most designs, these quantities should be sufficient.
However, a tradeoff between the number of branch destinations and the
number of product terms per destination can be made by pointing mul tiple
IF-THEN statements to the same destination. For example, the following
expression provides a three-way branch with up to eight product terms
available for the specification of transitions to state SI:
SB IF (condl) THEN SI
IF (cond2) THEN SI
IF (cond3) THEN S2
S3

Order of IF-THEN Statements
Order is importantin IF-THEN statements and can determine the machine
flow. Transition specifications need not be mutually exclusive in
expressions. For example, the following expression at first appears
ambiguous:
SB: IF 11 • 12 + 15 THEM SI
IF 15 • 16 + 14 • /13 THEN S2
IF 14 THEN S3
S4

If EPS448 inputs IS and 16 both become true during SB, either SI or S2
might be the next state. However, the EPS448 priority logic determines the
next state on the basis of transition order. Since the SI transition is
specified before the S2 transition, it is the next state entered. Similarly, if
14 * 1'13 becomes valid, S2 is the next state entered before S3. This
precedence-resolving ability is built into the EPS448 EPLD, which uses a
hardware priority-encoder to select the next-state transition. This capability
not only resolves conflicts, but can also be exploited in the design to
priori tize transitions.

I Page3D2

Altera Corporation

I

I Application Note 1DA

Design Entry for the EPS448 SAM EPLD

I

Default Transitions
Another feature of the IF-THEN syntax is the implicit default transition. In
the previous example, S4 is the next state entered if S1, S2, and S3 are not
selected. This feature can reduce design effort and resource requirements
substantially, since default transitions do not have to be defined as the
negation of non-default transitions. Such inverted expressions tend to
consume logic product terms or resources quickly. For example, the
following transition specification is valid in ASMILE:
S8: IF 11 • 12 + 15 • /17 + 18 THE" S1
IF 13 + /16 • 14 THEN S2
IF 12 • 13 • 14 • 15 • /17 THE" S3
S4

If the ASMILE syntax did not support default transitions, the default
transition, S4, would have to be explicitly defined as shown in the following

unminimized example:
IF /(11 • 12 + 15 • /17 + 18) • /(13 + /16 • 14)
• /(12 • 13 • 14 • 15 • /17) THE" S4

End Statement

Every ASMILE source file must terminate with the END$ statement.

ASMILE
Design
Example

A 68020 microprocessor bus arbiter state machine example is used to
illustrate ASMILE design entry. This example assumes knowledge of the
68020 bus exchange protocol. Table 1 shows the flow of the bus arbiter
control function. The state machine controls the handshakes between the
processor and the bus masters.
Table 1. Bus Arbiter Operation
States

IAltera Corporation

Processor and Requesting Bus Master Actions

SO

Bus master asserts request.

S1 & S2

Processor asserts grant.
Bus master arbitrates (if required) among multiple requests.
Bus master waits for completion of current cycle.

S6&S5

Next bus master asserts acknowledge (ACK).
Next bus master deasserts request.
Processor deasserts grant (waits for ACK to be deasserted).
Bus master performs bus operations.
Bus master deasserts ACK.

SO

Processor resumes operation.

S4&S3

Processor rearbitrates.

Page303 /

Design Entry for the EPS448 SAM EPLD

Application

Not. 1DA

I

Figure 4 shows a state machine diagram for the bus arbiter. The 68020based system runs at 25 MHz, and the bus arbiter machine runs with a
4O-ns clock cycle.

Rgure 4. Bus Arbiter State Machine Diagram
IAlA

RIA

RAGT X-

Bus request input
Bus grant acknowledge input
Bus grant output
Tri-state control to bus-control logic
Don't care

Three signal lines on a 68020 bus-IEQUEST, GIAttT, and
ACJCttOIolLEDGE-define the handshake required to arbitrate bus exchanges
between multiple bus masters. S8 represents the "normal," active state of
the processor; $1 and $2 correspond to the grant phase; $5 and $6 to the
acknowledge phase; and S3 and S4 to the arbi tration phase if requests are
pending at the end of the current bus exchange.
The file shown in Figure 5, 68828AIB.SMF, is the actual ASMILE file
entered for the state machine in Figure 4. In the Outputs and States
sections, output variables OS8 through OS6 are defined. Each variable is
valid only for one unique state. As the design is simulated, these variables
indicate the state of the machine.

Page3D4

Altera Corporation

I

I Application Note fDA

Design Entry for the EPS448 SAM EPLD

I

Rgure 5. 68020 Bus Arbiter State Machine RIB (68020ARB.SMF)
18/1/98 68828 Bus Arbiter for EPS448
X This description uses IF-THE" transition specifications X
PART:

EPS448

X Pin assisn"ents are optional X

I"PUTS: REQUEST ACX
OUTPUTS: GRA"T TRISTATE

OS8 OSI OS2 OS3 OS4 OS5 OS6

HACHI"E: BUSARBITER
CLOCX:
CLX
STATES
STATES:
S8
SI
S2
S3
S4
S5
S6

X

sives the output value "appins X
[GRA"T TRISTATE osa OSI OS2 OS3
[8
8
8
8
1
8
[1
8
1
8
1
8
[1
1
8
8
1
8
[1
1
8
8
8
1
[1
1
8
8
8
8
[8
8
8
1
8
8
[8
8
8
1
8
8

OS4
8
8
8
8
1
8
8

OS5
8
8
8
8
8
1
8

OS6]
8]
8]
8]
8]
8]
8]
1]

Transition Specifications follow X
S8: IF REQUEST*/ACX THE" SI
IF ACX THE" S5
S8
SI: S2
S2: IF /REQUEST*/ACX + ACX THE" S6
S2
S3: IF /REQUEST THE" S6
IF REQUEST*/ACX THE" S2
S3
S4: S3
S5: IF REQUEST THE" S4
IF /REQUEST*/ACX THE" S8
S5
S6: S5
Yo

E"DS

ASMILE
Design Entry
& Compilation

I Altera Corporation

The SAM Design Processor (SOP) is used to com pile the design. First, the
ASMILE file is automatically translated into an ASM file. Transition
equations are then au tomaticall y minimized, and "object code" is generated
for the EPS448 EPLO. Finally, a JEOEC programming file (.JED) is
generated. The JEDEC file can also be used as a design template in functional
simulation. A report file (.RPT) with the results of the compilation process
is also generated. Figure 6 shows key portions of this file.

Page3Dsi

Design Entry for the EPS448 SAM EPLD

Application Note 1DA

I

Figure 6. Bus Arbiter Report Rle (68020ARB.RPT) Excerpts
SAM Design Processor Utilization Report
Version 2.82 11/13/89
.* ••• Design i"ple"ented successfullg
IB/l/98 68828 Bus Arbiter for SAM
X This description uses IF-THE" Transition Specifications X
EPS448
RESERVED
G"D
G"D
G"D
G"D
CLOCX

vec

nRESET
G"D
G"D
REQUEST
ACX
RESERVED
RESERVED

.* •••

1
2
3
4
5
6
7
8
9
18
11
12

13
14

28
21
26
25
24
23
22
21
28
19

18
17

16
15

RESERVED
RESERVED
RESERVED
GRA"T
TRISTATE
OS8
OSI
G"D
OS2
OS3
OS4
OS5
056
RESERVED

DESIG" LISTING

PART:
EPS448
IttPUTS:
REQUEST@ll, ACX@12
OUTPUTS:
GRA"T@25, TRISTATE@24, OSB@23, OSl@22, OS2@2B, OS3@19, OS4@18, OS5@17, OS6@16
PINS:
DEFAULT:
[BBBBBBBBB]
PROGRAM:
[BBIBBBBBB] JUMP SB;
BD:
192D: SB: IF REQUEST • ACX' THE" [11BIBBBBB] JUMP SI;
ELSEIF ACX THE" [BIBBBBBIB] JUMP S5;
ELSE [BBIBBBBBB] JUMP SB;
ID:
51: [11BBIBBBB] JUMP S2;
193D: 52: IF REQUEST' + ACX THEN [BIBBBBBB1] JUMP S6;
ELSE [11BBIBBBB] JUMP 52;
194D: 53: IF REQUEST' THEN [BIBBBBBB1] JUMP S6;
ELSEIF REQUEST • ACX' THE" [11BBIBBBB] JUMP 52;
ELSE [11BBBIBBB] JUMP S3;
2D:
54: [ltBBBtBBB] JUMP 53;
195D: 55: IF REQUEST THE" [IIBBBBIBB] JUMP S4;
ELSEIF REQUEST' • ACX' THE" [BBtBBBBBB] JUMP SB;
ELSE [BIBBBBBtB] JUMP 55;
3D:
56: [BIBBBBBIB] JUMP S5;
EttD$

.*.** PART UTILIZATIO"
4/192 Unconditional Branches ( 2.B8x)
4/ 64 Conditional Branches
6.25~)
B Uarnings B Fatal errors
Page 306

Altera Corporation

I

I Application Note 10A
ASMILE
Design
Simulation

I

Design Entry for the EPS448 SAM EPLD

After a design has been successfully processed, the user can specify input
stimuli in a variety of formats and observe the EPLD response quickly and
effectively with the SAMSIM Functional Simulator. SAMSIM supports
both hard-copy and on-screen Virtual Logic Analyzer (VLA) output formals.
Split windows, multiple zoom levels, and delta time display are a few of
the capabilities of this interactive display mode.
SAMSIM supports both interactive and Command File input. Figure 7
shows a sim pIe inpu t Command File for the 68020 bus arbiter design. The
first line specifies the source JEDEC file. The next two lines contain logic
sequences for the two machine inputs. The PATTERN CREATE command
specifies a sequence of input logic levels to be applied to selected nodes.
The notation O*n, where n is an integer, is used to hold the indicated logic
value on the associated input for n clock cycles. The fourth line, SItiULATE
41, instructs SAMSIM to run the simulation for 41 clock cycles. The
interactive display is invoked in the last line with the VIE'" command.
Typically, Command Files are given the design name with the extension
.CtlD (in this case, 6S8Z8ARB.CtlD).

Figure 7. Bus Arbiter Command File for SAMSIM (68020ARB.CMD)
JEDEC 68B2BARB
PATTERN CREATE REQUEST
PATTERN CREATE ACX =
SIMULATE 41
UIE"

= (B)-3

1 1 1 1 (B)-12 1 1 1 liB B (1)-7 (B)-5
(B)-5 (1)-8 (B)-IB (1)-6 (B)-2 (1)-6 (B)-4

The following list describes other SAMSIM commands that are not used in
this example:
TRACE Dumps the entire state of the machine (inputs, outputs, internal
register, etc.) for each clock executed.
GROUP Specifies the logical grouping of signals for easy observation or
input vector specification.
SET

Modifies the values of the internal counter, stack, etc.

LINK

Logically links EPLD pins for simulation purposes.

RADIX

Defines the default radix for all SAMSIM commands. The radix
may be binary, hexadecimal, or decimal.

Figure 8 shows the VLA screen after running SAMSIM with the Command
File in Figure 7. The screen displays the input stimuli to the bus arbiter
design and the resulting state machine operation.

I A/tera Corporation

Page 307

I

!'r:I
l1l:I
1

Design Entry for the EPS448 SAM EPLD

Application Note fDA

I

Figure 8. VLA ScrHll for Bus ArbIter Design

1:1

-F'--------~------~~--------------------------~
REQUEST
ACK

GRAttT

TRISTATE
088

OSI
OSZ

--1

--.'-------"
__________
~

__--In

~n'-

__________________

~
~~

n

~

084
085

OSG

____

~~

________

~nL

____

~~~

1

______

~~

11

- - - - - - - - -- - - - -8- - - - - - - - - - -- - -- - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - -- - - - - - - --

Range: 8 to 74

"a.e: &882BARB.JED

Cycle:

Signals:

The initial input stimulus applied to the EPS448 design shows a
straightforward bus exchange between the 68020 and another bus master.
This exchange corresponds to the first REQUEST /GRANT /ACJC sequence.
Upon detecting a REQUEST, the 68020 asserts its TRISTATE line and
issues a GRANT pulse, allowing the new bus master to assume control. The
alternate bus master asserts ACJC when it detects that the bus has been
granted. When ACJC finally drops, the 68020 can resume control. The second
sequence involves not just a single initial REQUEST (bus master 1), but a
second REQUEST from another bus master (bus master 2) during the time
bus master 1 has control. As a result, the 68020 must generate a new GR ANT
pulse during S4 to S2, and hand over bus control to bus master 2 when bus
master 1 is finished (Le., when ACJC is dropped). When bus master 3 is
finished and no requests are pending, the 68020 finally takes control of the
bus again and TRISTATE goes low.

Page3D8

Altera Corporation

I

I Application Note 1DA
ASM Syntax

I

Design Entry for the EPS448 SAM EPLD

The ASM file consists of the following sections (sections enclosed in
brackets are optional):
[Header]

PART:
INPUTS:
OUTPUTS:
[PINS:]
[DEFAULT:]
[MACROS:]
[EQUATIONS:]
PROGRAM:
END$

ASM files may be entered with any standard text editor in non-document
mode. ASM is case-sensitive. It allows comments that are enclosed in
percent symbols (%). Filenames are terminated with the extension .ASH.

Header

The Header Section contains design identification information. Typical
information includes the designer's name and company, date, design
number and revision, and other comments.

Part Section

The Part Section of the ASM file (keyword PART:) specifies the EPS448 as
the target EPLD for the application. Multiple EPS448 EPLDs may be
specified for designs requiring more outputs than a single device can
supply. The SAM +PLUS software supports horizontal cascading of EPLDs
at a source code level. (See the EPS448 SAM EPLD: Stand-Alone
Microsequencer Data Sheet for more information.)

Inputs
Section

The single Inputs Section of the ASM file (keyword INPUTS:) defines all
external inputs to the design, as well as any required user pin assignments.
Pin assignments are specified in the following format:

Only user-defined inputs should appear in the Inputs Section. All design
inputs must be common in a horizontally cascaded design. A source file
can contain only as many inputs as a single EPS448.

Outputs
Section

The Outputs Section(s) of the ASM file (keyword OUTPUTS:) lists all
outputs from the design and pin assignments. Output pin assignment
syntax is the same as that of input pin assignments. If multiple EPS448
EPLDs are specified in the Part Section of the design file, multiple Outputs
Sections must be inserted in the ASM file, one for each EPS448 com ponen t.

Pins Section

The optional Pins Section (keyword P INS:) allows external variable names
to be mapped onto internal variable names. For example, an active-low
system signal called /UR might be entered into the transition specifications.
To keep the logical sense of such specifications clear, it is helpful to change
all active-low external signals to equivalent active-high names internally.

I Altera Corporation

Page3D9

1

Design Entry for the EPS448 SAM EPLD

Application Note 1DA

I

Defaults
Section

The optional Default Section (keyword DEFAULT:) specifies a default
output combination that can be used whenever the output string is not
explicitly defined in an instruction. In a single EPS448 specification, the
syntax is DEFAULT: [08 •••0nl, where 08••• 0n represents a binary string
corresponding to the n outputs specified for the EPS448 design. Default
output values are matched to output pins in the order in which they
appear in the Outputs Section. If multiple Outputs Sections appear in a
cascaded EPS448 application, the binary string is increased in width to
accommodate this change.

Macros
Section

The optional Macros Section (keyword tlACROS:) defines strings that can
be substituted universally throughout the ASM source code. Instruction
mnemonics may be redefined for efficiency or clarity, or binary output
strings may be redefined to have alphanumeric labels. An example of a
macro definition is REGI TOALU = "8181111881188888".
Embedded strings are not macro-substituted. To be recognized, macro
instances must be delimited by white space. For example, the macro
substitution REG = "8118" causes the string 8118 to be substituted into
[REG ALU OP] CONTINUE, but not into [:BREG4 AL OP] CONTINUE.

Equations
Section

The optional Equations Section of the ASM file (keyword EQUATIONS:)
defines intermediate equations to be used later in the design. For example,
an equation such as EventClk = 11 * /14 + 13 * 16 * /17 could be defined
in the Equations Section. The designer could then use EventClk in an IFTHEN statement, such as IF EventClk THEN JUtiP START instead of
entering the actual equation.

Program
Section

The Program Section of the ASM file (keyword PROGRAtI:) specifies the
sequence of instructions to be executed and the associated outputs required
from the EPS448 EPLD. The format of a basic instruction specification in
the Program Section is as follows:
label:

[Ou.tpu.t_spec] opcode;

The label is an optional alphanumeric string that can be used to identify
the instruction in branching expressions. [output_spec] represents an
actual numeric string (in binary, hexadecimal, or decimal format), a macro
substitution, or the character Z for tri-state (high-impedance) output pins.
Hexadecimal and decimal strings are defined by a string of valid digits of
correct length, followed by H or D, respectively. In horizontally cascaded
applications, each output is enclosed in brackets. The output specification
defined in the Default Section is assumed whenever it has length zero (Le.,
empty brackets ( [ ] ) imply the default output specification).

End Statement

Page 310

Every ASM source file must terminate with END$.

Altera Corporation

I

IApplication Note 10A
Multiway
Branch
Syntax

Design Entry for the EPS448 SAM EPLD

I

To specify multiway branching in the ASM file, a complex expression of
the following form is used:
IF
(expressionl) THEN
ELSEIF (expression2) THEN
ELSEIF (expression3) THEN
ELSE

[output_~.lue]

[output_~.lue]
[output_~.lue]
[output_~.lue]

(instructionl)
(instruction2)
(instruction3)
(instruction4)

For example, a complex instruction of this type might appe~r as follows:
IF

18-11-15-/17 + 13-14 + 16-/18 + /13-/11 THEN
[11118811188188800] CALL l.bell RETURNTO l.beI2;
ELSEIF 13-/12 + 15-16 + /10-14-11 THEN
[18110000011100011] LOADC 255 GOTO l.beI3;
ELSEIF 14-16-10 THEN
PUSH 15 GOTO l.beI4;
ELSE
[1111111100000001] PUSH1 GOTO 1.be15;

Each expression can be a function of any of the eight EPS448 external
inputs and can contain up to four product terms.
If more than four product terms are needed to define a transition from one
state to another, it is possible to trade off product-term counts for multiway
branch destinations. In the following example, expression1 and
expression2 could consist of four product-term expressions, resulting in
eight product terms that could be used to specify the transition to START:
IF
(expression1) THEN [] JUMP
ELSEIF (expression2) THEN [] JUMP
ELSEIF (expression3) THEN [] JUMP
ELSE
JUMP

START;
START;
NEXT1;
NEXT2;

Note the inherent priority scheme in the previous statements. The EPS448
architecture physically implements such a priority scheme in the branchcontrol logic block.

ASM
Opcodes

Thirteen easy-to-use micro-instructions (called opcodes) are built into the
ASM syntax. This compact instruction set allows the designer to take full
advantage of the advanced features of the EPS448 EPLD, such as the
counter and the stack. Three opcode examples are shown here. For a
complete list of opcodes, consult the EPS448 SAM EPLD: Stand-Alone
Microsequencer Data Sheet in this data book.
LOOPtiZ 
This opcode is useful for oneinstruction timing and delay loops. If the count register (CREG) is zero,
then the instruction at label2 is executed. Otherwise CREG is
decremented and the instruction at label1 is executed.

IA/tera Corporation

Page 311

!Ii'
11:.1

I Design Entry for the EPS448 SAM EPLD

Application Note 1DA

I

POPC GOTO 
In this opcode, the top-of-stack is popped into
CREG, and the instruction at label! is executed.
LOADC (constantl> GOTO 
This opcode loads CREG value
constantl, and executes the instruction at labell.

ASM Design
Example

A high-performance graphics controller may be used to show the design
process with ASM. In this application, two EPS448 EPLDs are horizontally
cascaded to generate the control outputs for a graphics subsystem. This
subsystem provides primitive graphics-drawing capability for a larger
microprocessor-based system.
Figure 9 shows a typical 8086 microprocessor-based system. Beneath the
address and data buses is the graphics subsystem to be controlled by the
EPS448 EPLDs. The graphics subsystem consists of the following primary
elements:

o
o
o

One 1-Mbyte, high-speed static-RAM video-frame buffer with
indi vid ual pixel-addressing ca pabili ty
Five 2901 bit-slice elements that are used to construct a 20-bit ALU /
da ta path engine
Two EPS448 EPLDs to provide overall control within the subsystem

This basic graphics engine is a user-microcodable design that can support
primitive graphics, such as lines, polygons, and conic sections. This example
discusses a single primitive drawing operation that draws circles of arbitrary
radii and origins into the frame buffer.
The pair of EPS448 EPLDs must be able to execute the following
subfunctions to serve as a controller for this subsystem:

o
o
o

o
o
o
o
o
o

IPage 312

Read commands issued by the main microprocessor
Transfer parameters associated with commands to the register file in
the 2901 bit slice elements
Initialize constant registers in 2901 bit slice elements to specified
values for the algorithm
Compute values for pixels on the circle as a function of the specified
radius for the first octant (assuming the circle origin is at (0,0»
Translate (x,y) coordinates into RAM addresses
Reflect circle pixel coordinates into the remaining seven octants
Translate pixel coordinates relative to their actual origin
Perform video-buffer write to all specified pixel addresses
Issue a done-interrupt to the main processor

Altera Corporation

I

IApplication Note 1DA

Design Entry lor the EPS448 SAM EPLD

I

Figure 9. EPS448 Graphics Engine
SO"S2
READY

00,,015

System

8086

Memory
AO to A19

System Address Bus

These activities are performed independently of the main microprocessor,
freeing it up for other tasks. These other tasks fall into two general categories:
controlling bus transfers between elements (registers, ALU, RAM, etc.)
and sequencing 2901 ALU computations that generate the pixel addresses
for drawing the circle.

Circle
Drawing
Algorithm

I Altera Corporation

An algorithm based on a methodology developed by Bresenham is used to
draw the circle. It uses the symmetry of a circle to calculate the circle points
in the first octant and to reflect those coordinates into the other seven
octants. (See Figure 10.) In other words, for a given pixel location (x,y), points
(-x,y), (x,-y), (-x,-y), (y,x), (-y,x), (y,-x), and (-x,-y) are drawn. After drawing
the first octant's points, only two possible choices exist for the next pixel
location: a horizontal move (Le., increment x) or a diagonal move (Le.,
increment x and y). The problem is deciding which of the two to pick next,
based on the current location.

Page313

I

!fit
l1l:I

I Design Entry for the EPS448 SAM EPLD

Application Note fDA

I

Rgure 10. Circle Symmetry

(-Y,X)

(Y,x)

(-X,-Y)

(-X,Y)

The basic algorithm is shown in Figure 11. The best match between the
actual pixel coordinates and the ideal circle points can be obtained by
checking an error term equal to the difference in distance from the circle's
center to each of the two next-pixel choices. The sign of the term indicates
which point will obtain the best fit.
Rgure 11. Circle Drawing Algorithm
procedure circle (radius, value
var x, ~, d
inteser ;
besin
x .- 8 ;
~
:= radius
d .- 3 -2 • radius
while x < ~ do besin
CircleDraw (x, ~, value);
if d

inteser

<8

then d := d + 4 • x + 6
else besin
d := d + 4 • (x ~ := !I - 1

x

end
if x
end

IPage3f4

~)

+ 18

end
.- x + 1

=~

then CircleDraw

(x,~,value)

Altara Corporation

I

I Application Note 1DA

Timing
Considerations

Design Entry lor the EPS448 SAM EPLD

I

EPS448 timing analysis is straightforward. All times are relative to the
synchronous clock input. The tsu parameter specifies the minimum setup
time for inputs to gain recognition at the next clock edge, while teo
specifies the clock-to-output delay for user
- 1
Done
- 1
Cn (2981)
- 1
Ur
- 1
ALE
- 1
Rd
- 1
RegRd
- 1

~

Inputs
C8-2
CMdAtt
Sign

- 3
- 1
- 1

Altera Corporation

I

I Application Note 1DA

Design Entry for the EPS448 SAM EPLD

I

Rgure 13. Clre" Drawing Routlns (CIRCDRAW.ASM) (Part 2 of 5)
I"PUTS: CB.Cl.C2.CMdAtt.Si,n
OUTPUTS: AB.Al.A2.A3.IB.ll.12.13.12.ll.IB.IS.14.13.18.17
OUTPUTS: 16.Rd.Ur.ALE.Re,Rd.OE.Cn.Done
DEFAULT: [BB8B 888B B8BB 888B I11B BIBBl
tlACROS :

CO"T = "CO"TI "UE"

" A & I Fields "
RadiusRe,
"8881"
Re,l
"8BB1"
Re,2 = "BBIB"
"B811 N
Re,3
Re,4
"B188"
Re,S
"BIB1"
"BI1B"
Re,6
"8111"
Re,7
Re,8
"188B"
Re,9 = "1881"
Re,18
"1818"
Re,l1
"lBll"
"1188"
Re,12

=

" Source Control "
AQ
"888"
AI
"B81"
ZQ
"BIB"
ZI
"811"
ZA
"18B"
DA
"lBl"
DQ
"liB"
DZ
"111"
" Function "
ADD
"888"
SUIR
"B81"
"818"
SUIS
OR
"Bll"
A"D
"18B"
"OTRS
"181"
EXOR
"l1B"
EX"OR
"111"
" Destination
QREG
"88B"
HOP
"B81"
RAttA
"BIB"
"Bl1"
RAttF
RAttQD
"lBB"
"181"
RAtiD
RAttQU
"11B"
RAtiU
"111"

Control

"

" Ius C~cle "
tteMUr
"18881 "
Re,Ur
"18811"
ALEc~c
"1118B"
"oC~c
"11888"

IA/tera Corporation

Page317

I

I Design Entry for the EPS448 SAM EPLD

Application Note 1DA

Rgure 13. Circle Drawing Rout/lIB (C1RCDRAW.ASM) (Part 3 of 5)
" t1isc "
Cn
:= "1"
nCn
:= "8"
Done := "1"
nDone := "8"
IQUATIOttS:
PROGRAt1:
" Processor Initializes: "
" 0 Load Coloreg, Radius, X8, Y8 "
" 0 Issues DrawCirc Co""and "
UAIT: IF ~dAtt.C8'.Cl'.C2' THEtt [] JUt1P DOlT
ELSE [] JUt1P UAIT ;
" t10ye para"eters fro" buffer to 2981 internal re9'isters "
" Radius -) Regl (Y) Yo
DOlT: [ Regl Regl AQ ADD ttOP RegUr nCn nDone
COtty
[ Regl Regl AQ ADD ttOP RegUr nCn nDone
COtty
Yo X8 -) Reg2 "

Reg2 Reg2 AQ ADD ttOP ttoC!lC nCn nDone
Reg2 Reg2 AQ ADD ttOP RegUr nCn nDone
Reg2 Reg2 AQ ADD ttOP RegUr nCn nDone

]
]
]

COttT
COttT
COttT

Yo Y8 -) Reg3 "
[
[

[

Reg2 Reg2 AQ ADD ttOP ttoC!lC nCn nDone
Reg3 Reg3 AQ ADD 1'I0P RegUr nCn nDone
Reg3 Reg3 AQ ADD ttOP RegUr nCn nDone

]
]
]

COttT
COI'IT
COttT

" Load constants to 2981 registers "
" 8 -) Reg4 (X) (AttD 8 & an!lthing giYes 8) Yo
[ Reg4 Reg4 ZB AttD RAt1F ttoC!lC nCn nDone ] COttT
" 3 -) Reg5 (d) Yo " Put "1" in Reg5 "
[ Reg4 Reg5 ZA ADD RAt1F ttoC!lC Cn nDone ] COttT
" Shift Reg5 up 1 to giYe 2 "
[ Reg5 Reg5 ZB ADD RAMU ttoC!lC nCn nDone ] COttT
Yo Uhile we haye it, preload 2 into Reg9 Yo

[ Reg5 Reg9 ZA ADD RAMF ttoC!lC nCn nDone ] COttT
Yo Incre"ent Reg5 to get 3 (whew!!) "

[ Reg5 Reg5 ZA ADD RAMF ttoC!lC Cn nDone ] COttT
" 6 -) RegB (const) - just shift 3 up one! "
Yo Load 1 in CRIG to setup for next instruction Yo
[ Reg5 RegB ZA ADD RAMU ttoC!lC nCn nDone ] LOADC ID
" 18 -) Reg9 (const) Yo
" Start b!l shifting Reg9 (now contains 2) up twice to get B
" Reg6 (Te"p register) Yo
SHIFTR9: [Reg9 Reg9 ZA ADD RAMU l'IoC!lC nCn nDone ]
LOOPttZ SHIFTR9

IPage 318

Yo

Altera Corporation

I Application Note 1DA

Design Entry for the EPS448 SAM EPLD

I

Rgure 13. Circle Drawing Routine (CIRCDRAW.ASM) (Part 4 of 5)
Incre"ent Re,' twice to ,et 18 ~
[ Re,' Re,' ZA ADD RAMF "oC~c Cn nDone ] CO"T
[ Re,' Reg' ZA ADD RAMF "oC~c Cn nDone ] CO"T

~

Initializin, done' - Be,in al,orit~ ~
d = 3 - 2-radius initiall~ ~
[ Regl Re,6 ZA ADD RAMU "oC~c nCn nDone ] CO"T
[ Re,S Reg6 AB SUBS RAMF "oC~c Cn nDone ] CO"T

~
~

~ If x >= ~ branch to finish up ~
OUTERLOOP: [ Reg4 Regl AB SUBS RAMF "oC~c Cn nDone 1 CO"T :
IF Sign THE" [] JUMP DrawEnd :

x Urite pixels, translate origin 8 reflect to all octants X
ELSE [] CALL CircPix
Test d sign: if >= 8, use POS X
[ Re,S Reg5 ZA ADD RAMF "oC~c nCn nDone ] CO"T
IF Sign THE" [] JUMP POS :

X

Co"pute d = d + 4-x + 6 X
First 4*x ~
ELSE [ Reg4 Reg6 ZA ADD RAMU NoC~c nCn nDone
[ Re,6 Re,6 ZA ADD RAMU NoC!:fc nCn nDone

X
X

X
[
[

Add 6 X
Reg8 Reg6 AB ADD RAMF NoC!:fc nCn nDone
Reg6 RegS AB SUBS RAMF "oC~c Cn nDone

]
]

]
]

CO"T
CO"T

CONT
JUMP IncX

= d + 4-(x-!:f) + IB ~
First X-!:f ~
POS:
Regl Reg6 ZA ADD RAHF NoC!:fc nCn nDone ] CONT :
[ Reg4 Reg6 AB SUBS RAMF NoC~c Cn nDone ] LORDC 10

X Co"pute d
~

Then 4*(x-~) ~
SHIFTR6:
[Reg6 Reg6 ZA ADD RAHU
LOOPNZ SHIFTR6

~

Add IB ~
[ Reg' Reg6 AB ADD RAMF
[ Reg6 RegS AB ADD RAMF

NoC~c

nCn nDone 1

~

NoC~c
HoC~c

nCn nDone 1 CO"T
nCn nDone ] COHT

Decre"ent !:f ~
[ Regl Regl ZA SUBR RAMF NoC!:fc nCn nDone ] CONT

~

Incre"ent x and repeat until x = ~ X
IncX:
[ Re94 Reg4 ZA ADD RAMF "oC!:fC Cn nDone ]
JUMP OUTER LOOP

~

Last pixel write / ends octant with x
DrawEnd:
[] Call CircPix
[] LOADC 160 :

~

=~

(45 degrees) X

Issue Done to processor for 16 clocks ~
DoDone:
[ Regl Regl ZA ADD RAHF "oC!:fC nCn Done]
LOOPNZ DoDone ONZERO UAIT :

~

X

IAltera Corporation

End Hain Routine

~

Page 319

I

I Design Entry for the EPS448 SAM EPLD

Application Note 1DA

Flgurs13. Clre" Drawing Routine (ClRCDRAW.ASM) (Part 5 of 5)
The CircPix routine reflect. the pixel into all octant. and
call. a routine that tran.late. the pixel relative to x8,~8;
calculate. the pixel addre •• a. addr = x + 9*1823; and runs the

~

"e"or~

c~cle.

ChcPix:

~

[ Reg4 Reg6 ZA ADD RAHF "OC9C nCn nDone ] CO"T
[ ~egl Regll ZA ADD RAHF "oC~c nCn nDone ]
CALL TRA"S ;

Reflect X to -X ~
[ Reg4 Reg6 ZA SUBS RAHF HoC9C Cn nDone ] CO"T ;
[ Regl Regl1 ZA ADD RAHF "OC9C nCn nDone ] CALL TRA"S

~

Swap X & y "
[ Regl Reg6 ZA ADD RAHF HoC9C nCn nDone ] CO"T ;
[ Reg4 Regll ZA ADD RAHF HoC9c nCn nDone ] CALL TRAHS

~

" Swap -X & y "
[ Reg4 Regl1 ZA SUBS RAHF HoC9C Cn nDone ] COHT ;
[ Regl Reg6 ZA ADD RAHF "oC9C nCn nDone ] CALL TRA"S
" Reflect Y "
[ Regl Regll ZA SUBS RAHF "oC~c Cn nDone ] CO"T ;
[ Reg4 Reg6 ZA ADD RAHF HoC~c nCn nDone ] CALL TRAHS
" Swap -Y & X y.
[ Regl Reg6 ZA SUBS RAHF HoC9C Cn nDone ] COHT ;
[ Reg4 Regll ZA ADD RAHF HoC9C nCn nDone ] CALL TRA"S
Y. Reflect -X, -Y Y.

[ Reg4 Reg6 ZA SUBS RAHF HoC9C Cn nDone ] CO"T ;
[ Regl Regl1 ZA SUBS RAHF HoC9C Cn nDone ] CALL TRAHS

& -Y Y.
[ Regl Reg6 ZA SUBS RAHF "OC9C Cn nDone 1 COMT ;
[ Reg4 Regl1 ZA SUBS RAHF "OC9C Cn nDone ] CALL TRA"S
[] RETUR" ;

Y. Swap -X

Y. The Trans routine translates relative to x8,98 and runs the
update c~cle Y.

"e"or~

TRA"S:

[Reg3 Regl1 AD ADD RAHF "OC9c nCn nDone ] CO"T ;
[ Reg2 Reg6 AB ADD RAHF "oC~c nCn nUone ] LOADC 18D
[ Regl1 Reg12 ZA ADD RAHF MoC9C nCn nDone ] CO"T ;

Y. Hultipl9 9 b9 1824 Y.

HULT1824:
Y. Subtract

DO"EI824:

[Regll Regll ZA ADD RAHU HoC9C nCn nDone
LOOP"Z HULT1824;
~ to effectivel9 "ultipl~ b~ 1823 ~
[Regl2 Regll AB SUBR RAHF HoC9C Cn nDone ] COHT

Y. Calculate address "

[ Reg6 Regl1 AB ADD RAHF

HoC~c

nCn nDone ] CO"T ;

Y. Urite pixel in buffer RAH Y.

RUHBUS: [ Regl1 Regll ZA ADD RAHF ALEc9C nCn nDone 1 CO"T ;
[ Regll Regll ZA ADD RAHF He"Ur nCn nDone 1 RETURH ;
E"Dt
IPage32D

Altera Corporation

I

I Application Note 10A

Design Entry for the EPS448 SAM EPLD

I

The algorithm shown in Figure 13 uses the 2901 operations along with
many of the internal addressing modes. Standard mnemonics have been
used for the various source, destination, and operation specifiers. These
control lines for 2901s are generated by the EPS448 EPLOs. The mnemonics
and resulting 2901 functions may be found in any standard 2901 data
sheet, available from many vendors.

ASM Design
Compilation

IA/tera Corporation

The SAM+PLUS Design Processor (SOP) must be invoked to compile the
CIICDIAU.ASti file shown in Figure 13. Compilation is an automatic
process that generates programming "object code" for the branch-control
logic and microcode EPROM blocks on the EPS448 EPLO. In this case, two
JEOEC13
programming files with the extensions .J D1 and .J D2 are genera ted, since
two EPLDs are required to implement the design. A Report File (with the
extension .IP1) is also generated during compilation. This file describes
the resources that have been used in the EPS448 EPLOs, pin assignments,
and absolute locations within the microcode assigned to the instructions
entered. Figure 14 shows the CIICDRAU.IPl file. Note the assigned pinouts for the two EPLDs as well as the substitution of absolute addresses for
logical labels.

Page321

I

IDesign Entry for the EPS448 SAM EPLD

Application Note 1DA

Rgure 14. Report Rle for Circle Drawing Routine (C/RCDRAW.RPT) (Part 1 of 3)
.* •• * Desi,n I"ple"ented Successtull~
x Circle Dr.win, Routine tor IPS448 x
IPS448
A8
HC
HC
HC
C8
CLOCK
UCC
RISIT
Cl
C2
C"dAtt
Si,n
I?
18

28
21
26
25
24
23
22
21
28
19
18

1

2
3
4
5

6
1

8
9

18
11
12
13
14

11

16
15

Al
A2
A3
88
81
82
83
GHD
12
11

18
15
14
13

IPS448

HC
HC
HC
HC
C8
CLOCK
UCC
RISIT
Cl
C2
C"dAtt
Si,n
HC
HC

18

28
21
26
25
24
23
22
21
28
19

11

18

12
13
14

11
16
15

1

2
3

4
5
6
1

8
9

HC
HC
HC
16
Rd
Ur
ALE
GHD
ResRd
OE
Cn
DOHE
HC
HC

* ••• * DISIGH LISTIHG
PART:

circdr.w.rpt

IPS448. IPS448

IHPUTS: C8. Cl. C2. C"dAtt. Si,n
OUTPUTS:
OUTPUTS:

A8. AI. A2. A3. 88. 81. 82. B3. 12. 11. 18. 15, 14. 13. 18, I?
16. Rd. Ur, ALE. Re,Rd. OE. Cn. Done

PIHS:
DEFAULT:
PROGRAtt:
BD:
192D:
UAIT:
10:
DOlt:

IPage 322

[888888BBBB88BBBBI11BBIBBl
[BBBBBBBBBBBBBBB8111BB1BBl JUttP UAIT;
IF C"dAtt • C8' • Cl' • C2' THEH
[BBBBBBB8BBBBBBBBll18BIBBl JUttP DOlT;
ELSE [B88BB8BBBBBBBBBBll1881BBl JUttP UAIT;
[88BIBB81BB8BB8BBIIBBl1881 JUttP 20;
A/tera Corporation

I Application Note 1DA

Design Entry for the EPS448 SAM EPLD

I

Rgure 14. Report Rle for Circle Drawing Routine (CIRCDRAW.RPT) (Part 2 of 3)
2D:
3D:
4D:
5D:
6D:
7D:
8D:
9D:
IBD:
llD:
12D:
13D:
14D:
15D:
SHIFTR9:
16D:
17D:
18D:
19D:
2BD:
OUTERLOOP:
193D:
21D:
194D:
22D:
23D:
24D:
25D:
POS:
26D:
27D:
SHIFTR6:
280:
29D:
3BO:
310:
IncX:
32D:
Dr.wEnd.:
33D:
34D:
DoOone:
35D:
CircPix:
360:
37D:
38D:
39D:
4BD:
41D:
42D:
43D:
44D:
450:
46D:

IA/tara Corporation

[BBB1BBB1BBBBBBBBllBBllBB]
[BB1BBB1BBBBBBBBB111BBBBB]
[BBIBBB1BBBBBBBBBI1BB11BB]
[BBIBBBIBBBBBBBBBI1BBIIBB]
[BB1BBB1BBBBBBBBBI11BBBBB]
[BB11BBllBBBBBBBBllBBllBB]
[BBllBBllBBBBBBBB11BBllBB]
[BIBBB1BBBI11BBBIIIIBBBBB]
[BIBBBIBI1BBBBBBII11BBBIB]
[BIB1B1B1BllBBBl1111BBBBB]
[BIBIIBBI1BBBBBBI111BBBBB]
[BIBIBIBI1BBBBBBI111BBBIB]
[BIBIIBBBIBBBBBI1111BBBBB]

JUMP 3D;
JUMP 4D;
JUMP 5D;
JUMP 6D;
JUMP 7D;
JUMP 8D;
JUMP 9D;
JUMP IBD;
JUMP llD;
JUMP 12D;
JUMP 130;
JUMP 14D;
LOAOC ID GOTO SHIFTR9;

[lBB11BB11BBBBB11111BBBBB]
[lBBllBB11BBBBBBll11BBB1B]
[lBBI1BB11BBBBBBI111BBBIB]
[BBBIBI1BIBBBBBIII11BBBBB]
[BIBIBI1BBBIB1BBI111BBBIB]

LOOPHZ SHIFTR9 OHZERO 16D;
JUMP 170;
JUMP 180;
JUMP 19D;
JUMP OUTERLOOP;

[BIBBBBBIBBIBIBBl111BBB1B] JUMP
IF Sisn THE"
[BBBBBBBBBBBBBBBB111BBIBB] JUMP
ELSE [BBBBBBBBBBBBBBBBlllBBIBBl
[BIBIBIBI1BBBBBBIIIIBBBBB] JUMP
IF Sisn THE"
[BBBBBBBBBBBBBBBBI11BBIBB] JUMP
ELSE [BIBBBIIBIBBBBBII111BBBBBl
[B11BB11B1BBBBB11111BBBBB] JUMP
[lBBBB11BBB1BBBB1111BBBBB] JUMP
[BllBBlB1BB1BBBBl111BBBBBl JUMP

1930;
Dr.wEnd;
CALL CircPix RETURHTO 21D;
1940;
POS;
JUMP 22D;
23D;
240;
IncX;

[BBB1BllB1BBBBBB1111BBBBBl JUMP 26D;
[BIBBBllBBBlB1BBll11BBB1Bl LOAOC lD GOTO SHIFTR6;
[BI1BBllBlBBBBBll111BBBBBl
[lBB1BI1BBBIBBBB1111BBBBB]
[Bl1BB1BlBB1BBBBll11BBBBB]
[BBBIBBBllBBBB1Bl111BBBBBl

LOOPHZ SHIFTR6 OHZERO 28D;
JUMP 290;
JUMP 3BD;
JUMP IncX;

[BIBBBIBB1BBBBBBll11BBBlBl JUMP OUTERLOOP;
[BBBBBBBBBBBBBBBBll1BB1BBl CALL CircPix RETURHTO 33D;
[BBBBBBBBBBBBBBBB111BBIBBl LOAOC 16D GOTO DoDone;
[BBB1BBBIIBBBBBBII11BBBB11 LOOPHZ DoDone OHZERO UAIT;
[BIBBBllBlBBBBBBl111BBBBBl
[BBBIIBI11BBBBBBI111BBBBBl
[BIBBBI1B1BSBIBBll11BBBlB]
[BBBllB111BBBBBB1111BBBBB]
[BBB1BllBlBBBBBB1111BBBBBl
[B1BB1Bl11BBBBBBl111BBBBBl
[B1BBIB111BBBIBBI111BBBIBl
[BBB1Bl1B1BBBBBBllllBBBBBl
[BBB11Bl11BBB1BB1111BBB1Bl
[B1BBBI1BIBBBBBBI111BBBBBl
[BBB1BIIB1BBBIBB1111BBB1Bl
[BIBB1Bl11BBBBBBll11BBBBBl

JUMP
CALL
JUMP
CALL
JUMP
CALL
JUMP
CALL
JUMP
CALL
JUMP
CALL

36D;
TRA"S
38D;
TRAHS
4BO;
TRAHS
420;
TRA"S
44D;
TRAHS
460;
TRAHS

RETURHTO 37D;
RETURHTO 390;
RETURHTO 410;
RETURHTO 43D;
RETUR"TO 45D;
RETURHTO 470;
Page 323

I

Design Entry for the EPS448 SAM EPLD

Application Note 1DA

I

Figure 14. Report File for Circle Drawing Routine (CIRCDRAW.RPT) (Part 3 of 3)
47D:
48D:
49D:
58D:
51D:
52D:
TRAI'IS:
53D:
54D:

[818881181888188111188818J
[88811811188818811118BB18J
[88B1811818BB1BBllllBBB1BJ
[81881811188818BllllBBB1BJ
[88888B8B88888B8Bll1BB188]

JUttP 48D;
CALL TRAI'IS RETURI'ITO 49D;
JUttP 5BD;
CALL TRAI'IS RETURI'ITO SID;
RETURI'I;

[881118118B1888BllllBBBB8J JUttP 53D;
[8818811B8818B8Bll11BB88BJ LOADC lBD GOTO 54D;
[1811118B18B88881111BBBBB] JUttP HULT1B24;

55D:

ttULT1824:
56D:
DO"E1824:
57D:
58D:
RU"BUS:
59D:

[18111Bl11B888811111BBBB8] LOOPI'IZ ttULT1B24 O"ZERO DO"E1824;
[11881811B81B81B11118BB1B] JUttP 57D;
[81181Bl1B81BB8BllllBBBBB] JUttP RU"BUS;
[IBll1BlllBBBBBB11111BBBBJ JuttP 59D;
[IBlllBll1B8BBBBlllBBB1BB] RETURI'I;

EI'ID$
••••• PART UTILIZATIO"

circdraw.rpt

59/192 Unconditional Branches (
3/ 64 Conditional Branches
(

38.73~)
4.69~)

xl Yarnings
8 Fatal errors

ASM Design
Simulation

ASM designs can be functionally simulated with SAMSIM. Figure 15
shows a sample Command File, called CIRCDRAU.CMD, that contains the
input stimuli for this circle drawing design. (Command Files are given the
design name with the extension .CMD.)
The first line specifies the name (without the extension) of the source
JEDEC file(s). The GROUP CREATE commam creates a group called CF with
three signals (CO, Cl, and C2). The group's input patterns can then be
specified in the PATTERN CREATE CF statement, rather than by entering
each signal's stimulus separately. The PATTERN CREATE command lists
the sequential values that the given input or group of inputs will take
during simulation. Hexadecimal format can be used to further streamline
group pattern entry. The notation ( )*n specifies that the enclosed stimulus
pattern should be repeated n times.
Rgure 15. Command File for SAMSIM (CIRCDRA W.CMO)
JEDEC CIRCDRAY
GROUP CREATE CF
CB Cl C2
PATTER" CREATE CF
(8H).2BB
PATTER" CREATE C"dAtt
(8).5 (1).2 (B).193
PATTER" CREATE Sign = (B)*2BB
TRACE CREATE CIRCDRAY.TRC
TRACE
SlttULATE 2BB
UIE"

=

=

=

0"

I Page 324

Altera Corporation

I

I Application Note 1DA

Design Entry for the EPS448 SAM EPLD

I

The TRACE CREATE command creates a trace buffer file CIRCDRALI. TRA
(shown in Figure 16). The state of the EPS448 EPLD is dumped into this file
after each simulation step. The Trace File includes such information as the
value on the top-of-stack, the counter value, and other internal information.
TRACE ott turns the trace process on and can be discontinued with a
TRACE OFF command later in the Command File. SIMULATE 200
specifies a 200-clock simulation to run. Finally, the VIELI command
enables interactive viewing of the results when simulation is finished.
Figure 16. SAMSIM Trace File (CIRCDRA W. TRA)
.UC=35D .MR=55D .CO=18D .SP=2D .TS=37D C8=8 Cl=8 C2=8 C"dRtt=8
Sign=8 MULTI824: 55D: [12288992D] LOOPNZ MULT1824 ;
.UC=36D .MR=55D .CO=9D .SP=2D .TS=37D C8=8 Cl=8 C2=8 C"dRtt=8
Sign=8 MULTI824: 55D: [12288992D] LOOPNZ MULT1824 ;
.UC=37D .MR=55D .CO=8D .SP=2D .TS=37D C8=8 Cl=8 C2=8 C"dRtt=8
Sign=8 MULTI824: 55D: [12288992D] LOOPNZ MULT1824 ;
.UC=38D .MR=55D .CO=7D .SP=2D .TS=37D C8=8 Cl=8 C2=8 CMdRtt=8
Sign=8 MULTI824: 5SD: [12288992D] LOOPNZ MULT1824 ;
.UC=39D .MR=S5D .CO=6D .SP=2D .TS=37D C8=8 Cl=8 C2=8 CMdRtt=8
Sign=8 MULTI824: SSD: [12288992D] LOOPNZ MULT1824 ;
.UC=48D .MA=SSD .CO=5D .SP=2D .TS=37D C8=8 Cl=8 C2=8 C"dAtt=8
Sign=8 MULTI824: 55D: [12288992D] LOOPNZ MULT1824 ;
.UC=41D .MA=55D .CO=4D .SP=2D .TS=37D C8=8 Cl=8 C2=8 C"dRtt=8
Sign=8 MULTI824: 5SD: [12288992D] LOOPNZ MULT1824 ;
.UC=42D .MA=SSD .CO=3D .SP=2D .TS=37D C8=8 Cl=8 C2=8 C"dAtt=8
Sign=8 MULT1824: SSD: [12288992D] LOOPNZ MULT1824 ;
.UC=43D .MA=S5D .CO=2D .SP=2D .TS=37D C8=8 Cl=8 C2=8 CMdAtt=8
Sign=8 MULT1824: SSD: [12288992D] LOOPNZ MULT1824 ;
.UC=44D .MA=SSD .CO=ID .SP=2D .TS=37D C8=8 Cl=8 C2=8 CMdAtt=8
Sign=8 MULTI824: 5SD: [12288992D] LOOPNZ MULT1824 ;
.UC=4SD .MR=55D .CO=8D .SP=2D .TS=37D C8=8 Cl=8 C2=8 C"dAtt=8
Sign=8 MULTI824: 5SD: [12288992D] LOOPNZ MULT1824 ;
.UC=46D .MA=56D .CO=8D .SP=2D .TS=37D C8=8 Cl=8 C2=8 CMdAtt=8
Sign=8 DONEI824: 56D: [13313586Dl CONTINUE
.UC=47D .MA=57D .CO=8D .SP=2D .TS=37D C8=8 Cl=8 C2=8 C"dAtt=8
Sign=8 57D: [7821824Dl CONTINUE ;

Figure 17 shows the Virtual Logic Analyzer (VLA) interactive output
screen that is displayed after SAMSIM has been run with the Command
File shown in Figure 15.

IA/tara Corpor.._a_tio_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_a_g_e_3_2_5----'1

I Design Entry for the EPS448 SAM EPLD

Application Note fDA

I

Rgure17. VLA Screen for Circle Drawing Routine

---Il
(ot)

BF

(ot)

IL

(~)

'" (3)

IH (3)
Rd

Wr

~~~~8888888
15484132h

h

~~~~::c:

II

8
8
8
8
1

r:e':

8888
132h

::ICce:

::~C((
~.(

~(~(

OO~~

~

::

-uuu

~

e8~8
18
8
D

u

Two types of output are displayed in Figure 17: single-signal waveforms
and group waveforms. CMdAtt is an example of a single-signal waveform
that corresponds to an EPLD input. AF corresponds to a group of four
signals, A8 to A3. For AF, the values in the group are displayed in a vertical
hexadecimal notation each time any signal in the group changes. (If an
explicit value is not displayed, it is the same as the previous time-step's
value.) By grouping common signals, much more information can be
displayed in a single screen than would otherwise be visible. In this
example, A, B, and I outputs are displayed in groups.
The simulation results correspond to approximately the first 40 clocks after
the graphics controller receives a CMdAtt, which signals the beginning of
a drcle-drawing operatipn. The 3 HegH d pulses correspond to reading the
circle's radius and (x,y) origin from the parameter register. The simple OE
pulse is the point where the CircP ix routine is first entered.
The VLA provides many useful features. For example, one command
allows the order of waveforms to be changed interactively; another allows
arbitrary signal groups to be constructed. An on-line HELP command
provides instant explanations of all commands. The VLA thus provides an
extremely flexible interactive design analysis.

Conclusion

I Page326

The EPS448 EPLD provides an efficient solution for sophisticated control
problems, such as the graphics controller and the 68020 bus arbiter. Other
suitable applications for the EPS448 EPLD include industrial-control,
graphics, disk controllers, and programmable sequence generators. The
PC-based SAM+PLUS software offers two flexible entry languages along
with powerful verification and debugging tools. This combination provides
a winning approach to control design.
Altera Corporation

I

Integrating PAL and
PLA Devices
with the EPM5032 MAX EPLD

I October 1990, ver. 2

Application Note 161

Introduction

The EPMS032 is a high-speed member of Altera's Multiple Array MatriX
(MAX) family of Erasable Programmable Logic Devices (EPLDs). Its highly
flexible architecture facilitates general-purpose logic design, and integrates
existing functions based on multiple TIL MSI, PLA, and PAL elements.
Other benefits include flexible logic utilization, advanced register control,
programmable I/O pins, and better system performance. Refer also to the
EPM5016 to EPM5192: High-Speed, High-Density MAX EPLDs Data Sheet in
this data book.

EPM5032 vs.
PAL and PLA
Architectures

The EPMS032 EPLD provides 28 pins and 32 macrocells, and may be
programmed to accommodate 64 latches or 42 flip-flops, in addition to
powerful combinatorial and control-logic functions. The device achieves
flip-flop toggle rates of over 80 MHz.
EPMS032 architecture allows it to emulate both PAL and PLA structures,
and to implement functions that are not possible with these devices. It
provides more than four times the integration density of traditional PAL
and PLA functions, while supporting complex state machine clock rates of
47 MHz (see Figure 1).

Figure 1. EPM5032 EPLD VS. PAL Devices

The EPM5032 has more than four times the fundional density of traditional PALs.

EP330.

EP630.
PAL7 ~
EPM501S.
60

Complex State
Machine Speed

PALD~

EPM5032 •

(MHz)

PALB~

40
PALA~

22V10-15
~

EP610

•

EP320A
20
PALQ~

22V10
~

3

2

4

5

Functional Density

I Altera Corporation

Page 327 I

I Integrating PAL and PLA Devices with the EPM5032 MAX EPLD

Application Note 161

The basic EPM5032 architecture is an evolution of the AND/OR array
structure that uses available logic far more efficiently than PAL or PLA
devices. Statistical analysis of hundreds of designs indicates that 70% of all
applications use no more than 3 product terms. The fixed-product-term
allocation of PALs usually wastes 5 of the 8 product terms. In contrast, the
MAX approach uses a streamlined, 3-product-term macrocell that may be
supplemented-when required-with as many as 64 additional expander
product terms. While PLA structures provide more flexible distribution of
logic capability, the cost is a considerable loss in performance.
Use of expander product terms increases the effective EPLD density and
permits higher integration levels than standard devices. Very complex
equations can be implemented ina single macrocell, leaving other macrocells
free to perform additional functions. Macrocells can also share expanders
to efficiently implement functions with common product terms (e.g., state
machines).
Expander product terms can also be used to create additional latches and
flip-flops. As many as 32 latches can be created without consuming
macrocell registers. Two expanders can be cross-coupled to form an SR
latch, and D registers and latches can be im plemented with other expander
configurations. Although these functions can be created in PAL devices,
additional macrocells would be required.
Figure 2 shows that a single EPMS032 can be used to replace multiple PLAs
plus a considerable amount of TIL glue logic in a variety of applications.

Figure 2. Using an EPM5032 EPLO to Replace PLAs and TTL Glue Logic
One EPM5032 EPLD (32 Macrocells) Replaces these Devices:
PLAs

Macrocells

PLS105 }
PLS15x
PLS16x

12

.:

16 (8 buried)

PLUS405

I

(Counter)
(Multiplexer)
(Comparator)

4

74178

(Shift Register)

4

I

2
4

·••

1"

Any Standard PLA

IPage32B

74161
74153
7485

18

GAL6001
PLC473

Macrocells

TIL

74180

I

+

(Parity Generator)

2

I
Added GlUe Logic

Altera Corporation

I

I Application Note 16

Replacing
7400 TTL
Devices

Integrating PAL and PLA Devices with the EPM5032 MAX EPLD

I

EPM5032 register and I/O features enable the EPLD to emulate 7400-series
TTL functions, and to replace programmable logic and associated discrete
TTL glue logic. Table 1 shows common TTL functions and their typical
EPM5032 device utilization.
Table 1. EPMS032 TTL Function Integration
The MAX+PLUS TTL MacroFunction library contains over
Function
Part
% Used
340 TTL-equivalent functions
to simplify entry of 74004-Bit Latch
7475
8%
series functions into a design.
4-Bit Mag.Comparator
7485
13%
Because MAX+PLUS auto- 8-Bit Shift Register
7491
19%
matically performs all design Dual 4:1 Mux
4%
74153
translation and optimization, Quad 4:1 Mux
5%
74157
74161
100k
function
is 4-Bit Binary Counter
a
TTL
74162
10%
implemented simply by 4-Bit Decade Counter
4-Bit Shift Register
100/0
74179
entering the symbol. The
9-Bit Parity Generator
74180
16%
macrocell
archi tecture
Octal Latch
74373
16%
provides true TIL emulation.
Since MAX+PLUS can also
merge schematic designs with
Boolean or sta te machine language descriptions when it compiles a design,
the designer can complete each section of a design with the most appropriate
entry method.

Replacing
PAL Devices

PAL circuits have a programmable-AND/fixed-OR structure. Each
macrocell generally includes 7 (e.g., 16L8) or 8 (e.g., 16R8) product terms.
Advanced PALs, such as the 22VI0, support a variable allocation of
product terms for macrocells, with as many as 16 product terms per
macrocell. However, sharing product terms between macrocells is not
possible, and product terms cannot be reallocated.
Figure 3 shows how the EPM5032 emulates a macrocell with a high
product-term count. The AND/OR logiC expression of a PAL can be
directly implemented with the EPM5032 macrocell. The expander product
terms provide product-term expansion if an individual application needs
more product terms. An EPM5032 macrocell can have as many as 64
product terms, far more than any existing PAL device. This architecture is
ideal for designs with multiple high product-term-count outputs and
common input Signals. For example, state machines, arithmetic logic circuits,
and complex combinatorial functions fit easily on MAX EPLDs such as the
EPM5032, but they are often impossible to design efficiently into PALs.
Existing PAL designs can be incorporated into any MAX+PLUS design
(Figure 4). Altera's PLD2EQN utility converts a standard PAL JEDEC file
into an Altera Hardware Description Language (AHDL) Text Design File
(TDp). Altera's ABEL2MAX utility translates an ABEL .ABL file into an
AHDL TDF. Both utili ties are available free from Altera's Electronic Bulletin

IAltera Corporation

Page 3291

!fit
l1:.li

I Integrating PAL and PLA Devices with the EPM5032 MAX EPLD

Application Note

161

Figure 3. Emulating High Product-Term-Count Macrocells
EPMS032 Macrocell

Conventional Macrocell

Output
Logic
Maaocell

.---.

Output
Logic

)---+-1 Maaocell

64

••
•

Board (see the Eledronic Bulletin Board Service Data Sheet in this data book
for more information). A TDF can be processed by the MAX+PLU5
Compiler, or the automatically-generated symbol representing the file can
be entered into a multiple-PAL design.
Figure 4. PAL and PLA Design File Conversion

Page 330

PLD2EQN and ABEL2MAX are free utility programs available from
Altera's Electronic Bulletin Board Service. AMAZE·format files can be
converted quickly to the Altera State Machine File (SMF) format.

A/tera Corporation

I

~plication Note

PAL Design
Example

Figure 5. Shaft Encoder

I

Integrating PAL and PLA Devices with the EPM5032 MAX EPLD

16

The Shaft Encoders section of AMD's PAL Device Handbook shows a
multiple-PAL/TTL implementation of a digital shaft encoder. The circuit
measures shaft rotation by counting and comparing pulses produced by a
pair of LEOs, a pair of photo sensors, and a rotating disk. The circuits are
divided into three major blocks. The first is a set of registers that accepts a
pair of 900 out-of-phase digital pulse trains as inputs, one from each
photosensor. The registers discriminate the phase difference between the
two signals and feed them into the decoder, the next block of the circuit.
The decoder converts the register outputs into an up-and-down signal to
control the final block, the counter. Outputs from the counter determine
the position and direction of shaft rotation. Figure 5 shows the circuitry
required: three PALs (16R4, 16R8, and 20X10) and two discrete TIL devices
(74193 and 74697). All five parts fit in a portion of a single EPM5032.

CLOCK

I

PHIO

v

PHI90

PAL 16R4

UP
DOWN

ISET
IOC

PHI90
X4

I

v

UPIOOWN

PAL 16R8

COUNT

ISET
IOC

X4

b;>

CO

to 03

Shaft
Encoder #2
74697
Up/Down
Counter

==C> co to Q3

J

CLOCK _ _ _ _ _ _-,
~~
I
PHI90

74193
Up/Down
Counter

I

CLOCK
PHIO

Shaft
Encoder #1

v

PAL20X10

~d
Encoder #3
----"".... COtoQ3

DATA+/LD - - - - - t
----yo""
ISET -----I....---r--....J
IOC _ _ _ _ _----',

The 16R4 (see Figure 5) implements a set of four registers for phase
discrimination, as well as decoding circuitry that produces UP and DOUN
control signals for a 74193 counter. Converting these functions from the
original PAL JEOEC files to an equivalent AHOL design file (see Design
File 1 later in this data sheet) is straightforward. Although the PAL design
includes a control signal (I'OC) for disabling the tri-state buffer outputs, it
is removed from the TDFbecause this signal is not needed in a completely
integrated design. The entire translation process takes just a few minutes.
The second PAL in the design (16R8) implements four discrimination
registers and decoding circuitry that outputs to a counter. However, the
decoded outputs are configured into UP I'DOUN and COUNT control
signals, and use a 74697 counter instead of a 74193. The design's PAL
JEOEC file translates into an TOF (see Design File 2 later in this data sheet),
and the I'OC control signal is left out. Translation takes only a few minutes.

IAltera Corporation

Page 331

I

I Integrating PAL and PLA Devices with the EPM5032 MAX EPLD

Application Note

161

The third PAL (20XIO) is more sophisticated. It implements register and
decoding functions as well as an up/down counter. Because this PAL
includes its own counter and some signals that actually appear on output
pins in the integrated design, the Output Enable control is left intact in the
TOF shown in Design File 3 later in this data sheet.
After the three PAL designs are converted into AHDL, the resulting TDFs
are opened with the MAX+PLUS Text Editor, and symbols representing
the TOFs are automatically created by MAX+PLUS. The symbols for the
74193 and 74697 macrofunctions are readily available in the MAX+PLUS
TIl. MacroFunction Library. As shown in Figure 6, the symbols representing
the PAL designs and the macrofunctions are entered with the MAX+PLUS
Graphic Editor and then connected to complete the design. This schematic
easily fits into a single EPMS032 after compilation.
Figure 6. MAX+PLUS Shaft Encoder Schematic
74193

PAL16R4

---<=:::>OA1

CLOCK

PHASEO

c:>...::..:.:....:~--.----­

~~~>OB1

PHASE90

~...=:..:~-+---+---­

~=~>oo1
~~~>OD1

DlV4

SET
OUTCNTL c:>...;;..;.;...;~-t---t--+--t-..,

vee

COUNTER
74697

- - - - t = : > OA2
~~~::>OB2
--'-<:::>002
~~~::>OD2

LOAD

I Page 332

INPUT

GND

Altera Corporation

I

~plication Note

16

Integrating PAL and PLA Devices with the EPM5032 MAX EPLD

I

Integration of these 3 PALs plus the 2 discrete counters required
29 macrocells and 29 expanders. Less than 90% of the EPMS032 is used, so
there is room left to implement additional lOgic.
Figure 7 shows the pin-out produced by the MAX+PLUS Compiler as part
of the Report File.
Figure 7./ntegrated Shaft Encoder
EPHS832

SET
GND RESERVED RESERVED

1

28

2
3
..

27

-

CLOCK
DIV1
DOWN

UP

Ii

6133 -

S

2S 26
2.. 23 -

VCC
GND

a

7

22

9

21 20 -

QB2

19

GlC1

18
17 1S
16

QC2
61D1
LOAD
OUTCNTL

6123 6113 6183 61D2

PHASE98 PHASE0 -

18
11
12
13
1 ..

61A1
61A2
QB1

VCC
GND

The EPMS032 provides increased performance by replacing multiple PAL
and PLA devices. The "single-chip solution" saves more board space than
standard devices and eliminates chip-to-chip delays incurred by designs
that require multiple PALs or PLAs. (See Figure 8.) For example, a PAL
design with 3 logic levels has an overall delay of 54 ns (three lS-ns
propagation delays and three 3-ns interconnect delays). The same design
can be im plemented in the EPMS032 with one level of expander logic and
one level of macrocelllogic for a total delay of 26 ns (including the 3-ns
interconnect delay to the next stage). This single-device implementation
provides faster speeds and better overall system performance.

IAltera Corporation

Page 3331

I Integrating PAL and PLA Devices with the EPMS032 MAX EPLD
Rgure 8. Replacing HighSpeed PALs with the
EPM5032-1

Fast PAL

Fast PAL

Signal In ~

Application Note

Modified
Signal

15 ns

15 ns

1

1

Interconnect
Delay

Interconnect
Delay

t

3ns

Total Delay: 54 ns

Fast PAL
Modified
Signal

t

161

Sig~alOut

15 ns

13ns

3ns

t

Interconnect
Delay

Total Delay: 26 ns

Replacing

PLAs

In addition to PAL and random ITL replacement, the EPMS032 can also
implement PLA architectures. Each PLA provides an additional
programmable array that allows variable product-term distribution.
Figure 9 shows a typical PLA structure that consists of a programmableAND array (containing 32 to 48 AND gates) feeding a programmable-OR
Figure 9. Traditional PLA Architecture
Logic Array

INPUT

r - - - - - - - -

IO~1

11 ~
12 ~

13~

-I
1

Programmable
AND

Feedbad(

:[)-

14~

15~1
16
17

~INPUT I

1

f·············································t

Programmable
OR
t -_ _OUT_P_UT-c:> F5
OUTPUT

t -_ _OUT:....:...-.cP....;;UT-C:> F3

OUTPUT
I - - - - - - C : : : > FO
INPUT

Output

CLOCK ~-----' Registers

I Page 334

Altera Corporation

I

IApplication Note 16

Integrating PAL and PLA Devices with the EPM5032 MAX EPLDJ

array. Each of the AND gates is fed by 8 to 12 input pins and feedback
signals, plus their complements. The OR array allows logical ORingof any
of the AND terms in the array. Typically, 8 to 12 programmed OR terms
feed either feedback combinatorial buffers, feedback registers, or output
pins.
ThePLA'sprogrammable-AND/programmable-ORstructureisemulated
with the expander product-term array, as shown in Figure 10. As in highproduct-term PAL applications, the unallocated product terms feed an
inverted AND gate in the macrocell to create an AND/OR-equivalent
NAND /NAND structure.

Figure 10. Emu/ating the PLA 's AND/OR Structure
Expander
Product Terms

MacrocelJ

~

•
•

•
I

I

Programmable

I
I
Programmable
NAND

NAND

As shown previously in Figure 4, existing PLAs can be incorporated into
EPM5032 designs. For this purpose, the PLA source files from Signetics,
which are usually written in the AMAZE language, must be converted to
the Altera State Machine File (SMF) format. AMAZE and SMF formats are
similar, so the source files can be quickly converted with a standard text
editor. Figure 11 shows AMAZE and SMF files of a state machine beverage
dispenser. Note the similarities in state and transition definition. After the
AMAZE source file is transformed into an SMF, the SMF2ADF and
ADF2CNF Converters provided with MAX+PLUS translate the SMF into
a MAX+PLUS-compatible CNF (see Figure 4). The MAX+PLUS Compiler
then processes the CNF.

I

IAltera Corporation

page33s1

IE

I Integrating PAL and PLA Devices with the EPM5032 MAX EPLD

Application Note

161

Figure 11. SMF vs. AMAZE File Formats
Altera SMF

Signetics AMAZE

IHPUTS:COIHDROP,CUPFULL
OUTPUTS: DROPCUP,POURDRHX
STATES: [DROPCUP POURDRHX]
Sl
[8
8]
S2
t1
8]
S3
[8
1]
Sl: IF COIHDROP THEti S2
S2:S3
S3: IF CUPFULL THEti Sl

STATE UECTORS
Sl = 88b;
S2 = 18b;
S3 = 81b;
ItiPUT UECTORS
[COltiDROP,CUPFULL]
OUTPUT UECTORS
[DROPCUP POUJlDJI"X]
OUT1 = 88b;
OUT2 = 18b;
OUT3 8lb;
TRAHSITIO"S
"HILE [S1]
IF [I'COltiDROP] THEti [Sll "ITH [OUTI]
IF [COII'IDROP] THEH [S2] "ITH [OUT2]
"HILE [S2] THEti [S3] "ITH [OUT3]
"HILI [S3]
IF [CUPFULL] THE" [SIJ "ITH [OUTI]

=

PLA Design
Example

A serial communications interface with a custom protocol is described in
Custom Communication Protocol-PLS105A, 157, 167, 168A of the Signetics
Sequencer Solutions manual. The design shown in Figure 12 consists of the
following three blocks, each of which is implemented in a Signetics PLA:
CJ
CJ

CJ

The Preamble Sequence Detector is a state machine that recognizes a
bit pattern that signals the beginning of a valid data block.
The Cyclic Redundancy Check (CRC) Controller is a state machine
that coordinates the loading of parallel-to-serial and serial-ta-parallel
shift registers and provides status of data and CRC transmissions.
The 5-bit CRC Generator detects errors.

As shown here, these three blocks are integrated withAltera'sMAX+PLUS
Development System, and the resulting design fits into a single EPM5032.
Preamble Sequence Detector This module is implemented in the Signetics
PLS167A. The Signetics AMAZE source file is transcribed into an SMF,
and the design fits into less than one third of an EPMS032.
CRe Controller A Signetics source file is converted into an SMF to
implement the CRC Controller. The Signetics implementation requires
100% register utilization of a PLS105A, while Altera's CRe Controller
implementation leaves plenty of the EPM5032 unused.
eRe Generator The schematic shown in Figure 12 is the CRC Generator.
It is submitted directly to MAX +PLUS for processing. This module requires
100% register utilization of a PLS157, but consumes less than 20% of the
EPM5032.

I Page 336

Altera Corporatiol I

I

IApplication Note 16

Integrating PAL and PLA Devices with the EPM5032 MAX EPLD

Figure 12. CRC Generator

SELTBUS C>'=-+-.....-I
SE~BUS

C>''''-=-+--+-----'

ClK

RESET

OECRC

INPUT

Integration is simplified with MAX +PLUS. Each of the three source files is
compiled separately with the MAX +PLUS Compiler, and the automatically
generated symbols that represent each module are entered with the
MAX+PLUS Graphic Editor. Appropriate connections are made between
the symbols to complete the design, and the final schematic is then submitted
to the MAX+PLUS Compiler (see Figure 13). The PLS105A, PLS157, and
PLS167A designs all fit into one EPM5032 (see Figure 14).

Conclusion

The EPM5032 offers better integration than PALs or PLAs and a flexible
architecture that supports a broad range of applications. A single EPM5032
typically replaces three to four conventional PLDs, and can also provide
extensive ITL integration. As shown in the design examples, one EPM5032
can be used in place of three PLAs or three PALs and two TIL devices.
Designs can be easily converted from PALs or PLAs to the EPMS032. The
EPM5032 also offers flexible logic utilization, advanced registers, better
control of I/O pins, and system performance benefits.

mJ

The design files used to generate the PAL Shaft Encoder and the PLA
Serial Communications Interface can be downloaded via modem with the
Altera Electronic Bulletin Board Service.

IAltera Corporation

Page 337

I

I

I Integrating PAL and PLA Devices with the EPM5032 MAX EPLD

Application Note

161

Figure 13. Serial CommunicatIons Interface
PREAMBLE
SERIN

_ _.-....:2!:!..!.!~::::::> SYNCERR

DETPRE

---:::::::..:.:~::::::>

SYNCPASS

CLEAR

---:::::::..:.:~::::::>

SYNCTIME

---=..;.;-=-r=>
---=..:..:...=...;..r=>

OERCV

CLK

CONTROL
DONE

•. I----+-.=.:..:...:::.:.j==> RESET
RDMODE
WRMOOE
REPEAT
DATATR

-++H-":::'=~=>

LD

-+-H-I-~~r:::::::::>

SHIFTEN

CRCGEN

SER_BUS~~IN~P~UT~

__~________________________________

SER_TR

The following files are available:
PAL Design Files: SHFTENC1.ADF, SHFTENC2.ADF, SHFTENC3.ADF
PLA Design Files: PREAMBLE.SMF, CONTROL.SMF, CRCGEH.GDF

Figure 14. Integrated Serial Communications Interface
EPMS032
SERIN
DETPRE

SYNC ERR

CLEAR

SYNC PASS

CLK

SYNCTlME

RDMODE

DONE

WRMODE

OERCV

REPEAT

RESET

DATATR
SER_BUS
SER3R

I Page 338

LD
.-~~~-­

--..;;..;..;..;....;..;;::::~

SHIFTEN
SER_OUT

Altera Corporation

I

IApplication Note 16

Integrating PAL and PLA Devices with the EPM5032 MAX EPLD

Design File 1. PAL 16R4-Equlvalent AHDL File
x PLDZEQ" version: 1.9 processed: Hon Oct 81 89:84:5S 1998 X
TITLE "logic frOM JEDEe file SHFT_O"E";
DESIG" IS "PALI6R4" DEVICE IS "auto";

x
PAL16R4
SEI
X

SUBDESIG" PAL16R4
(

eLK. PHIS. PH198. SET" : I"PUT;
DO~", 54. 53. SZ, 51. UP
: OUTPUT;
)

VARIABLE
down_din.
s4_fbk. s4_din.
s3_fbk. s3_din.
sZ_fbk. sZ_din.
sl_fbk. sl_din,
up_din : "ODE;
BEGI"

= TRI(down_din, Uee);
!down_din
PHI8 & PHI98 & sl_fbk & sZ_fbk & s3_fbk & !s4_fbk
I !PHIS & !PH199 & !sl_fbk & !sZ_fbk & !s3_fbk & s4_fbk
I
PHIS & !PH199 & sl_fbk & !sZ_fbk & !s3_fbk & !s4_fbk
I !PHIS & PHI99 & !sl_fbk & sZ_fbk & s3_fbk & s4_fbk;

DO~"

54
s4_fbk
!s4_din

TRI(s4_fbk, Uee);
DFF(s4_din, eLK, !G"D. !G"D);
!s3_fbk
.. ! SET";

53
s3_fbk
!s3_din

TRI(s3_fbk, Uee);
DFF performing each task. Data is pipelined between cells and
communicate with the outside world only at the boundary elements. Each
stage of the pipeline has its own data storage and does not use global
memory. This method of storage allows the cascaded processors to store
data between them, permitting new data to enter the pipeline while previous
data is processed. The critical performance factors of a systolic system are
the speed of the individual processors and the number of stages in the
pipeline.
To increase system throughput with better real-time performance, the
pipelined processors may also be expanded into a processor matrix by
adding parallel processors (see Figure 3). This method allows similar data
elements, such as blocks of pixels, to be processed synchronously,
multiplying overall system throughput. While this method improves system
performance using the speed processors, it complicates data management.

IAltera Corporation

Page34sl

I DSPRmaglng Applications with the EPS448 SAM EPLD

Application Not.

Rgure 3. Processor Matrix
A systolic array oonsists of a
number of pipelined and
parallel processing cells. The
EPS448 can be used to control
the system array and elements
within a particular cell

m

-

~

Data
Acquisition
Buffer

~n

,--

~

I

)-l- -

I
I
I

191

Display
Buffer

RAM

"

I

---------

The need for processor element speed has led to advances in processors
dedicated to DSP applications, such as the TMS320 family. Careful system
data flow design is just as critical to system performance, particularly in a
heavily pipelined system. Ideally, data should flow automatically" through
the system, without involving the PEs. By minimizing the housekeeping
overhead on the processor elements, this method maximizes useful imaging
cycles throughout the system.
lI

Both software and hardware can be used to control data flow between
processors. Software may be used to poll the status of the processors to
determine when they are ready to accept or generate data, if data rates are
slow enough. However, this method severely hampers system performance
and is being replaced by interrupt-driven approaches, even in systems less
dependent on data throughput. Another approach is the implementation
of hardware interrupts, which requires significant software overhead to
call and service interrupt routines and to restore the processor to its
original task. This overhead is m ul tiplied and becomes unacceptable when
a multi-processor DSP system is used.
An ideal system to significantly improve system performance uses the
processors exclusively for performing the necessary algorithms, without
wasting time for handshakes. Until the advent of high-performance
microsequencers, however, this approach was very costly because it
required large amounts of hardware to synchronize the processors. Since
EPS448 SAM EPLDs are microcoded, this technique can be implemented
with a sizable reduction in hardware and cost.

I Page346

Altera Corporation

I

I Application Note 19
Parallel
Data Flow
Control

DSPllmaglng Applications with the EPS448 SAM EPLD

I

To provide a "transparent" interface between processors, data buffers
(e.g., RAMs, FIFOs, and register files) are used to absorb the data output
by one processor, when the processors following it in the chain will not yet
accept incoming data. These data buffers ensure optimum system
performance. The parallel engine element shown in Figure 3 consists of
four parallel processors within a cell that share common input and output
FIFOs. This structure may be expanded in both the m and n directions to
yield proper performance for each individual application. EPS448 EPLDs
can be used not only to control data flow for the pipelined and parallel
rows, but also to control it within a particular cell.
Figure 1 shows one cell in this large array. This cell contains an input FIFO,
four processor elements (PEs), an output FIFO, and an EPS448
microsequencer that controls the data flow. Each PE shares input and
output FIFOs that absorb incoming and outgoing data. Within each FIFO,
a 74AS373 is connected to both input and output buses of each PE to latch
incoming and outgoing data.
The EPS448 EPLD distributes data to the PEs by controlling the writing
and reading functions of the 74AS373s, and performs error checking for
the system. It simultaneously supports all data transfers including full
error checking between the four processor elements, thus offloading this
data housekeeping from the DSP engines.
The first task in handling this data flow is to manage the FIFO read and
write cycles. Figure 4 shows the timing diagrams that represent the FIFO
processor and the EPS448 signals required for read and write cycles. The 2
in PE2RD, PE2IJR, G2, and /OC2 represents processor 2. The widely used
TMS32020 is shown, although any processor is suitable. This processor has
two output clocks, CLXOUT1 and CLXOUT2. Both output clocks have
200-ns periods, with CLXOUT2lagging by 50 ns. Another output from the
processor is /STRB, synchronized with CLXOUT2. Its rising edge
determines when a read or write is complete.
Other relevant processor outputs are the address and RI'IJ signals. These
signals are issu~d 20 ns before /STRB goes low. They are decoded to
generate PE2RD and PE2IJR, which are input signals to the EPS448, and
indicate that a read or write has been requested.

Read-Data
Timing

I A/tera Corporation

Processor 2 reads data in a two-phase cycle (see Figure 1). First, the
processorreads the data on its input latch: the output from the 74AS373(A)
is enabled, the processor reads this data, and the outputs are disabled. In
the second phase, data is read from the FIFO to the 74AS373(A). The entire
cycle begins on the falling edge of /STRB. The /OCA (which is a decode of
the processor's /STRB), RI'IJ, and address signals activate atthis time and
enable the outputs of 74AS373(A). The 74AS373(A) remains enabled until
the rising edge of /STRB. On this edge, the processor reads the data of
74AS373(A) and /OCA is deasserted, i.e., 74AS373(A) is disabled.
Page 347

I

1m
I

IDSPllmaging Applications with the EPS448 SAM EPLD
Figure 4. Data Flow
Timing
Th9S8 signals are
required for reading data
into the input FIFO and
writing data into the output
FIFO.

Processor
;..

CLKOUT1

100 ns

Application Note 19

.;

--;

.--L

t - j- - - - - ,

L----;::::::~___,

CLKOUT2 - - - - - '
STAB - - - - - - ,
20 ns l

--~<

ADDR. RlW

Valid (Read)

;H

;. 8

DATA

16.~ ~s.

PE2RD

r

,....----,
135 ns
L....-_ _....

60 ns

_____. . i·
.

;.

Valid (Write)

95 ns

('

I

L....-_ _....

)~------

55 ns 35 ns
Data

~ut )~------

tsu

PE2WR
SAMCLK
G2
IOC2

________________
FIFO

~r--l~

_________________
LJ

16.5 ns

. LJ;::

RDFIFO

Data Read Complete

16.5 ns 16.5 ns
WRFIFO - - - - - - - - - - - - - - - - - 2 - 5 - n s - - - - - - - - - - ' - 1 ·
-D-ata-W-ritt-e-n-

.....€3-<

DATA - - - - - - - - - - - - - - . :

LJ;::i-'

»)---------to FIFO

In Valid

74AS373(A)
~C~)

-----.~

_ _~

Once the processor has read the data, the EPS448 EPLD must refill the
74AS373(A). The EPLD inititates the read from the FIFO into 74AS373(A)
when it detects PE2RD on the rising edge of SAI1CLJC, 50 ns after /STRB
goes low. The EPS448 EPLD wai ts for one clock cycle until it drives /RF IFO
low. /RFIFO requests the FIFO to output a word. The input enable to the
74AS373(A), G, is also activated by the EPS448 EPLDat this time. /RFIFO
and G are actually asserted on the EPS448 pins, 16.5 ns after SAMCLJC
(clock-to-output delay). If the FIFO has access time of 25 ns, the output data
of the FIFO appears at the inputs of the 74AS373(A), 41.5 ns after PE2RD is
detected (16.5 + 25 ns). For 50 ns, the /RF IFO pulse is low. Data is valid at
74AS373(A) for 25 ns (50 ns RFIFO low, 25 ns FIFO access time), meeting
the setup time of 74AS373(A). On the rising edge of /RFIFO, the data is
latched into 74AS373(A).
This process requires two SAMCLJC signals (one detects PE2RD and one
asserts /RFIFO to the FIFO), and half the 200-ns processor cycle time. If
the FIFO is empty when the read is requested (i.e., EFl high), the EPS448
deactivates the processor's RDY signal and informs the system processor of
the error status. In a real system, the EPS448 EPLD may have a set of
routines to allow the processing element to recover dynamically from the
error. The EPS448 EPLD provides up to 448 microcoded states to support
this complex error recovery.

IPage 348

Altera Corporation

I

I Application Note 19

Write-Data
Timing

DSPllmaglng Applications with the EPS448 SAM EPLD

I

PE21.1R becomes active when the processor issues a write cycle. Figure 4
shows that after PE21.1R goes high, the inputs of 74AS373(B) are enabled
(since G is tied to PE2I.1R), and the latch is ready to accept a new data word.
To write data into the output FIFO, I'OCB and I'LiFIFO appear 16.5 ns (one
clock-output delay) after the clock following the detection of PE2L1R.
Processor 2 then takes (:ontrol of the FIFO data bus and begins the FIFO
read. After 50 ns, the /OCB and I'I.IF IFO are deasserted (i.e., go high), and
data from the 74AS373(B) is written into the FIFO.
The write process also requires two SAMCLJCs: one detects P E21.1R and one
asserts 1'1.1 to the FIFO. If the FIFO is full (FF2 high) at the time of the write
request, the EPS448 EPLD deactivates RDY to the processor and informs
the system processor of the error status.

Data Flow
Microcode

EPS448 subsystem control tasks include checking the processors for read
and write requests, servicing these requests, and checking for FIFO error
conditions. The SAM Assembly Language (ASM) is used to enter EPS448
designs (see Figure 5). This language consists of simple IF-THEN constructs.
Output specifications for any particular state are enclosed in brackets, and
appear in the same order in which they are placed in the Outputs section
(i.e., the first output in brackets represents I'RFIFO). Macros are used to
substitute text for commonly used output strings. For instance, IDLE
substitutes for G = 8 (inactive), RDY = 1 (active), and /OC = 1 (inactive). Data
flow control starts at the label PE1SRUC.
Figure 5. Data Flow Microcode for EPS448
OUTPUTS:
MRCROS:
PE1SRUC:
PEZSRUC:

RDPEZ:
YRPEZ:
PE3SRUC:
PE4SRUC:
SVSERR:
SV"CH:

IAltera Corporation

/RFIFO, /YFIFO, Gl, RDV1, /OC1, GZ, RDVZ,
/OCZ, ... , ERR
IDLE = 811
x Si"ilar to PEZSRUC x

...

1]
IF EFI + FFZ THE" [11 881 881
GOTO SVSERR;
x Processor not read~ x
8]
ELSEIF PEZRD THE" [11 IDLE IDLE
GOTO RDPEZ;
x Read~ to read X
8]
ELSEIF PEZYR THE" [11 IDLE IDLE
GOTO YRPEZ;
X Read~ to write ~
ELSE [11 881 881 .•. 8] GOTO SV"CH;
~ Error, need to s~nchronize X
[81 IDLE 111 •.• 8] GOTO PE3SRUC;
~ Read frOM input FIFO ~
[18 IDLE 818 ... 8] GOTO PE3SRUC;
~ Yrite to output FIFO X
~

~

Si"ilar to PEZSRUC
Si"ilar to PEZSRUC

~

wait for error conditions to clear
Stop processors, s~nch subs~ste" ~

~ Recover~,
~

~

~

Page 349

I

I DSPRmaglng Applications with the EPS448 SAM EPLD

Application Not. 19

I

The starting point for data flow control in PE1SRUC is the same as that of
the PE2SRUC subroutine used to detail processor read and write cycles.
One of four different states becomes active when PE2SRUC is called (this
label is reached when the first processor has been serviced). The first state
becomes active if the input FIFO is empty or the output FIFO is full (EFl +
FF2) at the label PE2SRUC. When this error condition takes place, the
processors' RDY signals are forced low, and a transition to SYSERR occurs.
This system error should not happen, since the FIFO depths should be
chosen according to worst-case data build-up. However, if either error
condition does occur, the user can customize the SYSERR subroutine to a
particular system. SYSERR can inform the main CPU of the subsystem
error and make the EPS448 EPLD clear the error status.
In the second state, if PE2RD is true, all outputs are static to prepare for the
performance of the required read cycle, assuming no error occurs at the
labeIPE2SRUC. The label RDPE2 becomes active on the next SAMCLJC, when
I'RFIFO and G2 become active. This state causes a read from the FIFO to
74AS373(A). On the next SAI1CLJC, a transition to PE3SRUC occurs when
processor 3 is serviced and all outputs relating to processor 2 are deactivated.
The third state occurs if PEZUR is true at the PEZSR UC label, which prompts
a write cycle to begin. All outputs remain static until SAMCLJC causes a
transition to the only state at the URPEZ label. This state's outputs force
I'UFIFO and I'OC low, allowing the processor to write data to the output
FIFO. On the following SAMCLJC, a transistion to PE3SRUC takes place when
processor 3 is serviced and all outputs relating to processor 2 are deactivated.
In the fourth state, neither error condition is true and both PE2RD and
PEZUR are inactive. This error condition informs the user that the processors
are not synchronized. The subsystem is designed so that the processor 2
lags behind processor 1 by 100 ns, which is the same time it takes to read or
write from processor 1. In addition, it is assumed that all processors in the
image-processing system execute instructions requiring the same amount
of time. If processor 1 has just read data, processor 2 should also be ready
to read data when PEZSRUC is reached. If processor 2 is not ready when
processor 1 finishes, a synchronization error has occurred, and all
processors' RDY signals are pulled low. A transition to SYNCH then takes
place, which resynchronizes the subsystem processors through a subroutine
created by the user.
The benefits of the EPS448 subsystem include the increased data throughput
and the consistent data flow from the input stage, through the processors,
to the output FIFO. The microsequencer provides data flow control, while
relieving the processors of synchronization and FIFO error condition
checking. The EPS448 EPLD runs at 20 MHz to allow four processor reads
and four processor writes to occur continually every 800 ns, generating an
output data word every 200 ns. (This is the same amount of time a
processor requires to perform one instruction.) Without the microsequencer,

I Page350

Altera Corporation

I

I Application Note 19

DSPllmaging Applications with the EPS44B SAM EPLD

I

each PE would require two additional cycles of overhead between the
generation of each data word to check for data at the input and output
FIFOs. A 3O-MHz EPS448 EPLD is also available to support faster processors
and subsystems that have more than four processors for each
microsequencer.

Other
Parallel
Processing
Control

Parallel approaches that require local neighborhood operations are also in
spatial operation techniques used for image enhancement. Calculations
are performed on a pixel and its nearest neighbors. If a 5 x 5 pixel area of an
image is to be analyzed, a 5 x 5 array of processors ideally would perform
the algorithm. The EPS448 EPLD controls the loading of the pixel words
into the processors. Five bits from the image's first line are loaded into the
top row of processors. The EPS448 EPLD counts through the unnecessary
pixels in the line following the neighborhood's pixels, the blanking pixels
beyond the edge of the screen, and the unnecessary pixels preceding the
active pixels in the second line. The EPS448 then enables the five pixels on
the second line into the second row of processors, and the process continues.
The EPS448 EPLD is well-suited to this application because it has an onchip counter and performs subroutine calls and looping.

FIR Filter
Implementation
with SAM

The finite duration impulse response (FIR) filter is a basic building block in
DSP applications. The EPS448 EPLD is ideal for creating an N-tap FIR
filter, and for using a Multiplier-Accumulator (MAC) for coefficient
generation (see Figure 6). An 8-tap FIR filter requires 8 data words and 8
coefficients as inputs to a MAC. The EPS448 EPLD can supply coefficients
to a MAC as fast as 30 MHz, enabling the device to act as a fast PROM in
delivering coefficients to the inpu t registers of the MAC. The EPS448 EPLD
also replaces the address counter and provides necessary control lines.

Figure 6. Selectable Coefficient Generation
The EPS448 acts as a
large EPROM plus address
logic for storing coefficient
values. Here a selectable
B-tap, 12-bit filter is
implemented with a 12 x 12
MAC.

I Altera Corporation

PO

12 x 12
MAC

Sum Out

P26

Page351

I

I DSPllmaglng Applications with the EPS448 SAM EPLD

Application Note 19

I

Figure 7 shows the signals necessary to interface the EPS448 toa 12x 12 bit
MAC that has 35-ns multiply-accumulate times.

Figure 7. Coefficient Generator Timing
The timing and signals
required for the 8-bit tap
filter, SEL, and LDCOEFF
are the necessary control
signals into EPS448
coefficients that are
available 165 ns after the
rising edge of each
EPS448 clock.

MAC
IME

16.5

-------~-t

XCLK - - - - - - - - - - '
COEFF1

COEFF2

COEFF3 COEFF

DATA------~
EPS448
ClK
LDCOEFF

~
001

SEL~~

_____________________

The EPS448 EPLD has 448 microcode addresses, each containing a 36-bit
word that consists of 20 internal control bits and 16 output bits. As a resul t,
the EPLD contains a 448 x 16 PROM and a stack that can implement a
448-waybranch in only 2 clock cycles. The EPS448 EPLDcan thus store and
quickly obtain access to coefficient tables of varying sizes to implement
multiple algorithms.
Figure 8 shows ASM code that allows the EPS448 EPLD to provide selectable
coefficient strings to implement eight-tap filters. If LDCOEFF from the first
instruction (If LDCOEFF ANDPUSHI 11111888) is true, the EPS448
inputs are ANDed with the constant 11111808, and the result is pushed
onto the EPS448 internal stack. This process guarantees that the three least
significant bits will be zeros. The remaining five input bits are the select
inputs that determine which coefficient table to access.
The clock after the ANDPUSHI is instructed to RETURN. This instruction pops
the top-of-stack, making it the next label (or address location) in the
EPS448. For instance, if the select inputs are 8BBIU, address BBB81BB8 *
11111888 = 8D (decimal) is off the stack and becomes the next label; if the
select inputs are 8B818, address 16D is the next label. In this example, the
11111888 mask forces a branch to an address that is a multiple of 8 (the
number of taps). If the number of taps is changed, the mask is also
modified. For example, if a 12-tap filter is required, the mask is changed to
11118188. For this 8-tap filter and select inputs 88B81, a transition occurs
after the RETURN command to address 8D on the clock. (Address 8D is the
address of the first coefficient table.)

I Page352

A/tera Corporation

I

I Application Note 19

DSPllmaging Applications with the EPS448 SAM EPLD

I

Figure 8. EPS448 Microcode for Coefficient Generator
Selects are 3rd, 4th, & 5th tor "ask

~

12 coetticients and

~

ItiPUTS:

54, 53, 52, 51, SB, LDCOEFF

OUTPUTS:

COEFFll ••• COEFFB, /"E

SELECT:

IF LDCOEFF [B ••• B 1]
" Select table
AtlDPUSHI IIIIIBBB GOTO TABLESEL;
ELSE [B .•• B 1] GOTO SELECT;
~ Uait tor LDCOEFF

"

TABLESEL:

[B ••• B 1] RETURtI;

~

~

8D:

[H4C
[OBS
[679
[D4B
[SIR
[D41
[RB9
[624
[9B4
[488

" HEX COEFFICIEtlTS, /"E

16D:

B]
B]
B]
B]
B]
B]
B]
B]
B]
B]

COtlTltlUE;
COtlTltlUE;
COtlTltlUE;
COtlTltlUE;
COtlTltlUE;
COtlTltlUE;
COtlTltlUE;
COtlTltlUE;
COtlTltlUE;
COtlTltlUE;

~

~

"e"or~

enable

Transition to selected table

"

After the transition to address aD, the first coefficient and memory enable
/ME are output. /ME enables the data memory and is ANDed with the
system clock to generate XCLlC, which clocks in the x data bits. XCLlC
requires a 15-ns data setup time and a 3-ns hold time. Since the coefficient
outputs arrive 15 ns before XCLlC, this condition is met. Hereafter, a new
12-bit coefficient is loaded into the x data input registers of the MAC on
every system clock.
When the last coefficient is supplied to the MAC, the FIR filter is
implemented, and the EPS448 issues a flag to the data source, informing it
that data should no longer be enabled. At this point, a transition to
SELECT occurs that provides access to the appropriate location in the
coefficient table, depending on the inputs. SELECT may access the same
set of coefficients or any other set in the table. Because the EPS448 EPLD
has 448 memory locations, 56 possible table locations can be accessed for
this 8-tap filter.
To choose the appropriate set of coefficients and to meet the setup time for
XCLlC, a 3-clock cycle latency occurs with this approach. (It occurs whether
there are 56 eight-tap filters, equal to 448 states, or 224 two-tap filters.) This
latency is possible because the EPS448 EPLD performs a 448-way branch in
only 2 clock cycles. After the third clock cycle, coefficient data hE:comes
available every clock cycle, or as fast as 30 MHz. This approach has
advantages over both FIFO and PROM approaches. Although data can be
written directly if FIFOs are used, very fast FIFOs (with access time of
35 ns) are very expensive.

I A/tera Corporation

Page 353

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IDSPllmaglng Applications with the EPS448 SAil EPLD

Application Note 19

I

Also, coefficients must be reloaded before being reused (which requires n
clock cycles, where n is the number of taps), or a retransmit feature must be
used. Retransmit slows the cycle time of a 35-ns FIFO to 120 ns.
The EPS448 EPLD provides advantages over PROMs, including power
savings, cost reduction, and integration. In addition, address counters that
are required with the PROM approach are unnecessary with the EPS448
EPLD. Also, if multiple PROMs are used because of filter length or width,
the PROM address counter must be buffered. Using multiple PROMs
consumes more board area because of the additional devices and the
routing of address lines. However, the EPS448 provides these benefits
while typically consuming 90 mA at 30 MHz.

Conclusion

IPage354

The programmable EPS448 architecture is ideal for implementing complex
designs typical of DSP systems. Because of its flexibility and high
performance, the EPS448 EPLD is well-suited for controlling data flow for
both parallel and pipelined systems, and for coefficient generation. Finally,
the EPS448 provides both low-power operation and high performance
(30 MHz).

Altera Corporation

I

Fast Bus Controllers
with the EPM5016 MAX EPLD
Application Note 20 I

October 1990, ver. 2

Introduction

Todays advanced microprocessors are capable of running in systems with
clock speeds up to 33 MHz. To realize the performance potential of these
microprocessors, their memory interfaces must be equally fast. Highperformance memory devices, however, are expensive. This cost/
performance tradeoff can be improved by using a combination of fast and
slow memories. To accommodate the slower memories, wait states are
added into the microprocessor bus cycle.
This application note describes how to integrate the wait-state and buscontrol logic into an Altera EPM5016 MAX EPLD; which is then integrated
into an 80386 microsystem design. The application note also describes how
to crea te and process the design with the MAX +PLUS Development System.

EPM5016
Overview

The EPM5016 is the fastest member of the MAX EPM5000-series EPLDs,
with propagation delays of 15 ns, system clock rates of 66 MHz, and counter
frequencies of 100 MHz. The EPM5016 can also drive 24 rnA, which allows
it to directly connect to buses. It is available in a windowed ceramic or
plastic 20-pin DIP, 20-pin PLCC, or 20-pin SOIC package, accommodating
designs with up to 15 inputs and 8 outputs. The EPM5016 architecture is
based on a single flexible Logic Array Block (LAB) that encompasses 3
components: the macrocell array, the expander product-term array, and the
I/O control block. See Figure 1.

Figure 1. EPMS016 Block Diagram
11 NpUTc=>---------I
12 I N P U T r : = > - - - - - - - - - I
19INPUTr:=>---------I
20 I N P U T . - - - - > - - - - - - - - - I

t---------<==:J INPUT
1-----~t_--c--lINPUTIClJ(

1------I----c---lINPUT
INPUT

2
9
10

MACROCELL1

1/03

MACROCELL4

MACROCELL3

110 4

MACROCELL6

MACROCELL5

110 7

MACROCELL8

MACROCELL7

110 8

MACROCELL 10

MACROCELL9

I/O 13
110 14

MACROCELL 12

MACROCELL 11

MACROCELL 14

MACROCELL 13

110 17

MACROCELL 16

MACROCELL 15

110 18

Expander Product Term Array (32)

I A/tera Corporation

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IFast Bus Controllers with the EPM5016 MAX EPLD

I

Application Note 20

The macrocell array contains 16 macrocells (see Figure 2). Each macrocell
has a programmable-ANO/fixed-OR array and a configurable register
that provides 0, T, JK, SR, or flow-through latch operation with independent
programmable clock options. Each macrocell also contains 3 product terms
for logic implementation. If necessary, the expander product-term array
can supply up to 32 additional product terms. Each expander product term
can be used and shared by any of the macrocells.
Figure 2. MAX Macrocell
Global Bus
OUtput Enable

System Clock

Preset

to 110
Control

Block

Clear

MacrOO811 and 1/0 Feedback

8

32

Dedicated
Inputs

Expander
Product Terms

The EPM5016 has 8 bidirectionalI/O pins with 24-mA output drivers to
allow direct interfacing to a variety of system buses. All of the I/O pins are
individually configurable for dedicated input, dedicated output, or
bidirectional operation. Each I/O pin has a dedicated feedback and a tristate buffer. Macrocells and I/O pins have separate feedbacks-a feature
called "dual feedback" -that enable the user to bury macrocelllogic and
retain the pins for inputs. For complete details about EPM5016 architecture
and timing, see the EPMS016 to EPMS192: High-Speed, High-Density MAX
EPLDs Data Sheet in this data book.
EPM5016 designs are created and programmed with Altera's MAX+PLUS
Development System. MAX+PLUS is a complete CAE system that offers
hierarchical design entry tools, automatic design compilation and fitting,
timing simulation, and device programming. The MAX+PLUS Compiler

I Page 356

A/tera Corporation

I

~cation Note 20

I

Fast Bus Controllers with the EPM5016 MAX EPLD

features advanced logic synthesis algorithms, allowing designs to be entered
in a variety of high-level formats while ensuring the most efficient use of
EPLD resources. The combination of flexible device architecture and
advanced CAE tools ensures rapid design cycles. A design can go from
conception to completion in a single day.

Bus
Controller
Functional
Description

Figure 3 shows the block diagram of an 80386 microsystem thatincorporates
peripheral logic, memory, and an 8259A interrupt controller. The EPM5016,
shown in the center of the diagram, serves as the system bus controller.
The EPM5016 decodes the 80386 status signals to control the peripheral
logic, i.e., the data transceiver, interrupt controller, and other external
logic. It also extends bus cycles by adding wait states to interface to slower
peripherals and memory devices.

Figure 3. 80386 Subsystem Block Diagram

r-------------------------------~~--------l=~~===C>~w~t
SELECT ~>--~

~~----~--~~~~----~~--~~DD
~~----~--~~~------~~--~~ONR

~------~------~------~~--~~p~

80386
(33 MHz)

D[0.. 15] DlllaBus

~=======UF===============================~==~~m~

The 80386 halts processing to allow wait states to be added into the .bus
cycle when the signal/READY is high. (The slash (/) indicates an activelow signal.) The EPM5016 bus controller tracks each bus cycle operation
and causes /READY to go high when wait states are needed. For example,
read operations from 200-ns EPROM memory in 33-MHz systems require
14 wait states.
The EPM5016 also decodes the bus control signals lORD (I/O read), lOUR
(I/O write), and ItiTA (interrupt acknowledge). The 24-mAoutputdrivers
on the EPM5016 eliminate the need to buffer these bus signals externally.

I Altera Corporation

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I Fast Bus Controllers with the EPM5016 MAX EPLD

Application Note 20

I

The 16 data signals originating from the 80386 are isolated from the system
data bus with two 74245 8-bit transceivers. The tri-state control on the
transceivers is provided by the signal /DEH from the EPM5016. The
direction signal is controlled directly by the Read/Write signal (U/R).
Two 74373s (8-bit latches) latch the 80386 address signals at the beginning
of the bus cycle to maintain a valid address throughout the cycle. The
latches are controlled by the 80386 signal/ADS. The high performance of
the EPM5016 easily supports the 33-MHz bus cycles. In fact, a 66-MHz (2 x
33-MHz) clock is used to clock the design for two reasons. First, ,lADS can
be connected directly ·to the address latches since the EPM5016 control
signals for the peripheral logic are active before the end of the first bus
cycle. Second, the wait-state generator offers greater granularity with
15-ns cycles than with 3O-ns cycles.

Bus
Controller
Interface
Signals

The design for the bus controller circuit requires 9 inputs: all 8 dedicated
inputs of the EPM5016 and 1 I/O pin. Five of the 9 inputs to the EPM5016
are signals from the 80386 microprocessor. The functions of these 5 signals
are given in Table 1. The other inputs are described subsequently.
Table 1. EPM5016 Input Functions
Input

Function

MIlO
WIR
DIC
A31
lADS

Memory or 1/0
Read or Write status
Data or Control status
Address bit 31 for memory mapping of the EPROM
Address data strobe indicating the beginning of the bus cycle

Systems that have functions set up for pipelining require external logic to
generate the signal ,IliA (next address). ,IliA feeds both the 80386 and the
EPM5016 bus controller. When ,IliA is activated, the 80386 places the next
address on the address signals so that they may be latched. Applications
that require pipelining receive minimal benefit from wait states. In such
cases, the ,IliA signal is used simply to disable the EPM5016.
/DRAMRDY is an externally generated signal that, when high, halts the
80386 by causing the /READY signal to be high. When /DRAMR DY goes low,
the 80386 continues processing.
The 66-MHz clock (CLK2), which is internal to the EPM5016, feeds a toggle
flip-flop to generate a divide-by-two signal (CLIC) that matches the 33-MHz
system clock signal. CLK tracks the microprocessor clock phase.
The last input signal, RESET, is connected directly to the Reset signal of the
microprocessor. RESET feeds the Preset or Reset of each register to set the
EPM5016 to the correct start-up state.

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I

I Application Note 20

Designing
with
MAX+PLUS

Fast Bus Controllers with the EPM5016 MAX EPLD

I

Figure 4 shows the MAX +PLUS-genera ted schematic for the bus controller
placed into the EPM5016. MAX+PLUS enables designs to be created with
up to eight levels of hierarchy. Any part of a design may be ei ther a text or
a graphic file. In this design, the four symbols with names BUS_ TRCK,
DECODE, "'AIT_CtlT, and TRAtI_CTL are text files designed with the
Altera Hardware Description Language (AHDL). AHDL allows designs to
be represented with behavioral description such as state machines,
arithmetic functions, comparator functions, or Boolean equations.

Figure 4. Bus Controller Schematic

RESET~~--....---

__- - - t - + - - - - - - - - - - - - - - - - - - - - - ,

MA~~------4---~+-­

MlIOC:::~-------+---+++-­

W/R

~~------4---+-++--...,

~C~~------4---+-++-~

~1C=~-------+---+++--

'---------------------{--:-> lORD
~----------------~C>IOWR

~------------------~~E~~

~--------------+-~~==================~--~~~
------t~ PIPE

'+-t-+---------------------------£:=>fDEN
fADS~~-----------------------------J

fDRAMRDYc:::~------------------------------------------__L~)----~~----t~fREADY

The top level of the design, shown in Figure 4, was created with the
MAX+PLUS Graphic Editor. The four symbols (whose underlying logic is
expressed in AHDL behavioral descriptions) were automatically created
by MAX+PLUS. When the symbols were created, inputs to the text files
became pinstubs on the left side of the symbol, and outputs became
pinstubs on the right. In this design, the BUS_ TRCI, TRAN_CTL, and
DE CO DE functional blocks are sta te machines. "'AIT _ CtiT is a counter with
synchronous Preload and Enable.

I Altera Corporation

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I

IE
I

I Fast Bus Controllers with the EPM5016 MAX EPLD
Design
Description

Application Note 20

I

Figure 5 shows the flow diagram for the bus controller. First, the 80386
causes /ADS to go low, indicating that a bus cycle has begun. /ADS then
causes BUS_ TRCK to activate the signal BUS_ACTIVE, which indicates that
the processor is in an active bus cycle. BUS_ACTIVE feeds the functions
DECODE and TRAtLCTL. The TRAN_CTL function then scans the 80386
control signals and enables the data transceiver buffers when they are
required. DECODE also scans the 80386 control signals and decodes them
into specific control signals (lORD, lOUR, EPRD, and INTA) that drive the
peripheral logic and the block function, "'AIT_CNT. "'AIT_CNT is a
loadable 4-bit counter that counts the required number of wait states for
bus cycles. When "'AIT_CNT finishes the wait state count, it causes
ti"e_dela!:l to go low, enabling DECODE to release the /READY signal and
finish the bus cycle.

Figure 5. Bus Controller Flow Diagram

/READY (Active)

(Enable transceiver,
/DEN goes active)

lORD, IOWR, EPRD,
or INTA (Active)
TIME_DELAY (Active) ' - -_ _ _ _ _~

BUS TRCK

I Page360

The BUS_ TRCK function is a state machine that determines when the
80386 is in a bus cycle. Figure 6 shows the state diagram for BUS_ TRCK.

A/tera Corporation

I

Application Note 20

Fast Bus Controllers with the EPM5016 MAX EPLD

I

Rgure 6. BUS_TRCK State Diagram

The AHDL description of BUS_ TRCJC is shown in Figure 7. BUS_ TRCJC
has two output signals: bus_active and pipe_active, of which only
b us_active is used in the top level of the design. The b us_active signal
Figure 7. BUS_ TRCK AHDL File
SUBDESIGM bus_trck
(

clk2,
Yo 88386 2x clock (66MHz) Yo
clk,
Yo 88386 33MHz clock
Yo
I'ads,
Yo low to begin bus c!jcles Yo
I'read!j,
Yo
Yo low to end bus c!jcles
reset:
Yo high to reset
Yo
IMPUT:
bus_actiue, Yo low during actiue bus c!jcles
Yo
pipe_act he: Yo low after pipelined bus c!jcles Yo
DUTPUT:
VARIABLE
bus_c!jcle

MACHIME DF BITS (bus[1 .. 81)
WITH STATES ( wait,
actiue,
pipelined ):

Yo define state Y.
Yo

bits and

Yo state na"es

Y.
Y.

BEGIM
DEFAULTS
bus_active = VCC:
Yo define signals to he Yo
pipe_actiue = VCC:
Yo
Yo nor"all!j high
EMD DEFAULTS:
hus_c!jcle.clk = clk2:
Yo state "achine runs at Yo
hus_c!jcle.reset = reset:
Yo 66 MHz
Y.
CASE ( hus_c!jcle ) IS
WHEM wait =>
Yo check for clk to
Y.
IF (!I'ads & clk) THEM Yo deter"ine phase
Y.
hus_c!jcle = active:
EMD IF:
WHEM acthe =>
IF (!I'read!j & I'ads & clk) THEM
hus_c!jcle = wait:
ELSIF (!I'read!j & !I'ads & clk) THEM
hus_c!jcle
pipelined:
EMD IF:
hus_actiue = GND;
Yo activate hus_actiue Yo
WHEN pipelined =>
IF (clk) THEN bus_c!jcle = actiue:
END IF:
pipe_actiue
GND:
EI'tD CASE:
END:

I Altera Corporation

Psge361

I

I Fast Bus Controllers with the EPM5016 MAX EPLD

Application Note 20

I

is active-low, indicating that the 80386 is executing a non-pipelined bus
cycle.
The state machine BUS_CYCLE is defined in the Internal Declaration
Section of the AHDL file. The register bi ts for the sta te machine are defined
as bus1 and busH with the bus format bus[1..8J, and the states are
defined as wait, active, and pipelined. MAX+PLUS automatically
generates the state assignments for each of these states during compilation.
After the BEGIti statement, the Clock and the Reset for the state machine
are defined with the statements bus_cycle.clk = clk2 and
bus_cycle.reset = reset. Next, the transition equations for the state
machine are defined with CASE and IF-THEti statements for the
conditional state transfers. When /ads goes low and CLX is high in the
state wai t, then the state machine changes to the state active, and the
signal bus_active goes low.

TRAN CTL

The TRAtI_ CTL sta te machine controls the Ou tput Enable of the data bus's
two 74245 data transceivers. See Figure 8.
Figure 8. TRAN_ CTL State Diagram

The AHDL file describing TRAtI_CTL, which is a single-bit state machine
called tran_en, is shown in Figure 9. When a non-pipelined bus cycle is
executed with the statement na & !bus_active, the 80386 control signals
are read by tran_en to determine whether the transceiver needs to be
enabled. The enable is released when the bus cycle is completed with the
statement bus_active & clk.

I Page362

A/tera Corporation

I

Application Note 20

Fast Bus Controllers with the EPM5016 MAX EPLD

I

Rgure 9. TRAN_ en AHDL Rle
SUBDESIGN tran_ctl
(

clk,
clk2,
I'na,
bus_acti.,e,
rec."
reset:
INPUT;

"
"
"
"
"
"

I'trLenable:
OUTPUT;

" low to enable io transcei.,er "

88386 clock
88386 2x clock (66HHz)
low to begin bus c~cles
low during acti.,e bus c~cles
low for reco.,er
high for reset of de.,ice

""
"
"
"
"

VARIABLE
tran_en

"ACHINE OF BITS ( tran )
UITH STATES (wait, enable);

BEGUt
tran_en.clk = clk2;
tran_en.reset = reset;
CASE ( tran_en ) IS
LlHENwait =>
IF (I'na & !bus_acti.,e & rec.,)
THEN tran_en = enable;
END IF;
" set /tri_enable high in the state wait"
/tri_enable = VCC;
LlHEN enable =>
IF (bus_acti.,e & clk)
THEN tran_en = wait;

DECODE

DECODE is a state machine that tracks the 80386 control signals to decode
the bus cycle. (See Figure 5 for the sta te machine diagram of DE CO DE.) The
AHDL file for DECODE is shown in Figure 10. The state machine io_state
has 10 states and uses 6 state registers (2 more than the required 4) because
all of the registers are used as outputs. The state register outputs are
defined in the Internal Declarations Section as binary numbers. (AHDL
allows all values to be represented in binary, octal, decimal, or hexadecimal
formats.)

The state machine io_state waits in its initial state called idle. When a
bus cycle occurs, i.e., bus_active goes low, the control signals from the
80386 are tested to see if wait states are required. If so, the state machine
moves to a state that deactivates /READY to the 80386 and waits for the
wait-state counter to time out. The signal til'1e_dela~, which is an output
from IoIAIT_CtlT, indicates' that the wait-state counter has completed
counting the required number of wait states. For example, a read from
EPROM would takethestatemachinetoepreadl, where it would waitfor
til'1e_dela~ to go high. When til'1e_dela~ goes high, io_state moves
to epread2 to enable the processor, and then returns to the idle state on
the next clock cycle.

I Altera Corporation

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1m
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Fast Bus Controllers with the EPM5016 MAX EPLD

Figure 10. DECODE AHDL Rle

Application Note 20

SUBDESIG" decode
(

ciU.

clk.
"'na.
.tio.
wr.
dc.
a31.
ti"e_delag.
bus_active.
reset:
I"PUT;
recv.
iord.
iowr.
eprd.
inta.
iordg:
OUTPUT;
VARIABLE io_state
I.lITH STATES

~
~

x
~

X
X
~

~
~

X

88386 Zx clock (66"Hz)
88386 c lock
low to begin bus cgcles
high for "e~rg. low for i"'o cgcles
high for write. low for read cgcle.
high for data. low for ctrl cgcle.
proces.or addre •• line A31
ti"e delag input
low during active bu. cgcle.
high for reset ot device

X low during tloat and recoverg
X
~
~
~

~

low
low
low
low
low

to read i"'o
to write i"'o
to read epro"s
tor interrupt acknowledge
to indicate readg

x
x
X
X
X
X
X
X

X
X
X
X
~
~
~

X

"ACHI"E OF BITS ( idS .. 8l
( idle
b"111111". " state
ioreadl = b"811111". " assigne"ents
ioreadZ = b"811181".
iowrite1
b"81111".
iowriteZ
b"111181" •
epreadl
b"118111".
epread2
b"118181" •
intackl
b"111811".
intackZ
b"111881" •
b"111118" );
recover

"
"

BEGI"
(iord.iowr.eprd.inta.iordg.recv) = io[l; x assign outputs x
io_state.clk = clkZ;
x to state
"
io_state.reset = reset;
X register bits x
CASE ( io_state ) IS
"HE" idle =)
IF ("'na & !bus_active & clk) THE"
IF (a31 & "io & dc & !wr) THEN
io_state = epreadl;
ELSIF (!a31 & !"io & dc & wr) THE"
io_state = iowritel;
ELSIF ('a31 & '"io & dc & !wr) THE"
io_state = ioreadl;
ELSIF (la31 & '"io & !dc & Iwr) THE"
io_state = intackl;
ELSIF ("io & !dc & wr) THE"
io_state = iowriteZ;
ELSE io_state = recover;
ErtD IF;
ErtD IF;
"HErt epreadl =)
IF (ti"e_delag) THErt io_state = epreadZ; ErtD IF;
"HErt epreadZ =)
IF (clk) THErt io_state = idle; ErtD IF;
"HEN iowritel =)
IF (ti"e_delag) THE" io_state
iowrite2; ErtD IF;
"HErt iowriteZ =)
IF (!"io & clk) THErt io_state
recover;
ELSIF ("io & clk) THErt io_state = idle; ErtD IF;
"HErt ioreadl =)
IF (ti"e_delag) THEN io_state = ioreadZ; ErtD IF;
"HErt ioreadZ =)
IF (clk) THE" io_state = recover; ErtD IF;
"HEN i ntackl =)
IF (ti"e_delag) THErt io_state = intackZ; ErtD IF;
WHErt intack2 =)
,
IF (clk) THErt io_state = recover; ErtD IF;
"HErt recover =)
IF (ti"e_delag & clk) THE" io_state = idle; ErtD IF;
ErtD CASE;
ErtD;

I PBge364

Altera Corporation

I

I Application Note 20

WAIT CNT

Fast Bus Controllers with the EPM5016 MAX EPLD

I

'-IAIT_CNT, shown in Figure 11, is a counter that generates the wait states
required to accommodate the slow hardware modules in the system. The
counter is idle when it is not counting wait states. The counter is activated
by iord, iowr, inta, or eprd,all of which originate from DECODE. Once
activated, the counter loads a preassigned value and begins to count until
the time-out count reaches zero. At that time, the signal ti"e_dela9 goes
low, releasing the bus for the next cycle.

Rgure 11. WAff_CNT AHDL RI.
CO"STA"T
CO"STA"T
CO"STA"T
CO"STA"T
CO"STA"T

11'0

EPRO"
RECOVER
TI"E_UP
IDLE

5;

= 1;

~

define constants

~

lB;
15;

B;

SUBDESIG" wait_cnt
(

clk2,
iord,
iowr,
eprd,
inta,
recy,
reset:
I"PUT;
ti"e_dela!j :
OUTPUT;

~ 8B386 CLX2
"
"
" low to read io
" low to write to
~
~ low to read EPRO"s
~
~ low for interrupt acknowledge"
" low during float and recoyer!j ~
" high to reset
"

VARIABLE
ti"er[3 .. B] : DFF;
BEGI"
ti"er[].clk = clk2;
ti"er[].clrn = 'reset;
" load counter "
IF (ti"er[] == IDLE) THE"
IF (Iiord
'iowr
'inta) THE" ti"er[] = I/O;
ELSIF ('eprd) THE" ti"er[] = EPRO";
ELSIF ('recy) THE" ti"er[] = RECOVER;
ELSE ti"er[] = IDLE;
E"D IF;
~ check to see if count is done"
ELSIF (ti"er[] == TI"E_UP) THE" ti"e_dela!j = VCC;
IF (iord & iowr & eprd & inta) THE" ti"er[] = IDLE;
ELSE ti"er[] = TIHE_UP;
E"D IF;
" count "
ELSE ti"er[] = ti"er[] + 1;
E"D IF;
E"D;

*

*

The constants at the beginning of the file shown in Figure 11 define the
different number of wait states required for each type of read/write
function. The constants are then included in the equations that are used to
load the timer. Constants allow descriptive names, rather than numbers, to
be placed into equations. For example, in Figure 11, EPROM is assigned the
value 1 in the Constant Section. When data is being read from EPROM, the
timer is loaded with this value. The cycle is completed once the counter has
reached 15 (14 clock wait states).

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I Fast Bus Controllers with the EPM5016 MAX EPLD

Application Not;2OJ

The conditional equations for the counter in "'AIT_CNT are created with
IF -THEN statements. The counter registers are defined in the Internal
Declarations Section with the statement tb-.er[3 .. Bl : DFF, which assigns
the names tbter3, tbter2, ti"erl, and ti"erB to four D-type flip-flops.
The statement ti"er = ti"er + 1 at the end of the AHDL file causes the
registers to count.

Compilation

Once the design for the EPMS016 
 198).

Simulation

I A/tera Corporation

Input vectors for simulation are created either in text format via a Vector
File, or in graphic format by drawing the waveforms in the MAX +PLUS
Waveform Editor. In the Vector File example shown in Figure 14, the input
vectors are defined to simulate a read from the EPROM.

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I Fast Bus Controllers with the EPM5016 MAX EPLD

Application Note 20

I

Figure 14. Vector File
GROUP CREATE ti"er

= IWAIT_cnT

66Iti"er3.Q
IWAIT_cnT 66Iti"er2.Q
IWAIT_cnT 66Iti"erl.Q
IWAIT_cnT 66Iti"er8.Q

OUTPUTS ClK READY EPRD DEn
ITRAn_CTl:59Itran_en
IIUS_TRCK:36Ibus_c~cle

IDECODE: 65 I io_state
ti"er
ClK ;
InpUTS RESET;
PATTERn
8>
1
lBB> B;
InpUTS ClK2;
InTERVAL 7.5;
START 2BB; STOP
PATTERn 1 B;

~

detine ClK2 to be 66

~HZ ~

5us;

~ detine static inputs ~
InpUTS W/R PA31 nA "/10 D/C DRA"RDY;
PATTERn
B>
B
1
1
1;

InpUTS ADS;
PATTERn
B> 1
.. 3B> B
..'B> 1;

The first statement in the Vector File, which begins with the word GROUP,
groups the timer bits together into a bus. The actual input vectors are easily
entered. The input RESET, for example, is defined to be a 1 for the first
100 ns, then 0 until the end of simulation. For the CLJC2 input, the
statement INTERUAL 7.5 defines the cycle transition time to be 7.5 ns. The
START and STOP commands define the period of time for the vector
pattern to repeat. The command PATTERN 1 B;causesCLJC2 to toggle. The
other input signals are similarly specified.
The outputs from simulation can also be viewed in either graphic or text
format. The MAX+PLUS Simulator automatically generates a graphic
Channel File that contains waveforms of simulation inputs and outputs,
which can be viewed and edited in the Waveform Editor. For example, if
some inputs must be changed for further simulation, the Channel File can
be edited graphically in the Waveform Editor and then submitted again to
the Simulator for further simulation.
Figure 15 shows the output waveforms generated by simulating with the
Vector File shown in Figure 14. The state machines are displayed with the
state names rather than the individual state bits in the waveforms.

IPage 368

Altera Corporation

I

Application Note 20

Fast Bus Controllers with the EPMSOt6 MAX EPLD

I

Rgure 15. Simulator Channel Rle
.229us

LEFT

I

•

I

..

J: •

RJ:OHT

1.

I

I

I

I

I

I

I

I

>c

1-:=;=~:=:=;---::Q=Il=-P----='~:

CUll.

..

---.s.: .....
.... ·1 . i·· -1- ... ~.l... h~.-:~,:,~.,!. ~~.~~. !'"·~t!'·~ .~~.-:~: ....

J: . . .
•

BRAKB

T ...

...J ..... I ·1·· ·1········ . . . . . . . . . . . . . . . . . . . '1'

..

.....

I

• . . .1.•

I

I·· .1 ..

... _

":::::::.
. . . . . . . . . . ..

....

t.~~~~ .~c:'~.~~.
I

·X

........

31.""

....~~ .......

Conclusion

The MAX architecture and the advanced MAX +PLUS software tools allow
designers to enter and fit a broad range of complex designs into the
EPMS016. In addition, the high-rlrive, 24-mA outputs of the EPMS016
allow direct connection to most system buses. As systems are being
challenged to run faster and faster, the EPMS016 rises to the occasion by
offering counter speeds up to 100 MHz. Complex state machines, such as
the bus controller shown in this application note, may be clocked up to 66
MHz, which is twice the speed of today's fastest processors.

References

Intel Corporation. 386 Microprocessor Hardware Reference Manual (1988).
Intel Corporation. 386DX Microprocessor Data Sheet (April 1989).

I A/tera Corporation

Page 369

I

Notes:

Designing with AHDL
I October 1990, VBr. 1
Introduction

Application Note

221

Text-based logic design has been greatly simplified by the introduction of
advanced behavioral languages that integrate very complex logic with
easy-to-understand text descriptions. The Altera Hardware Description
Language (AHDL) provides such powerful text-design support for Altera's
Multiple Array MatriX (MAX) family of EPLDs. AHDL incorporates the
benefits of earlier-generation text languages-such as ABEL, CUPL,
PALASM-and the Altera Design File (ADF) and State Machine File (SMF)
formats. With AHDL, Altera has gone beyond these languages by adding
features for specific applications, such as state machines, truth tables, and
IF-THEN-ELSE decision logic. AHDL allows any logic function to be
easily described, providing a comprehensive tool for text-based design.
AHDL is completely integrated into Altera's MAX+PLUS design
environment. AHDL designs can be created with the MAX+PLUS Text
Editor or any standard text editor. These text designs can be freely
combined with schematics in MAX deSigns. The MAX+PLUS Compiler
then performs logic syntheSiS and automatic fitting to use EPLD resources
most efficiently. A full timing simulator is also provided for rapid design
debugging. For more information on the MAX+PLUS development
software, refer to the PLS-MAX: MAX+PLUS Programmable Logic Software
Data Sheet in this data book.

AHDL
Constructs

AHDL provides several behavioral constructs that define the syntax for
different types of logic. This application note describes the following
AHDL constructs:

o
o
o
o

o

o
o

Groups
Logic, arithmetic, and comparison operators
Function prototypes
IF-THEN statements
CASE statements
Truth tables
State machines

Complex logic functions are easily implemented with AHDL constructs,
which allow any logic function to be described in a compact, readable
format. The features of these powerful constructs are discussed here.
Examples are given in "AHDL Design Examples" later in this application
note.

I Altera Corporation

PBge371 I

!I'iW
aa.:.

I Designing with AHDL

Application Note 22

I

Groups for Bus Designs
Groups in AHDL are analogous to buses in schematic capture designs. The
group construct allows a collection of bits to be treated as a single element.
AHDL groups may be defined with the following two notations:

o
o

A symbolic name followed by a range of decimal numbers enclosed
in brackets, e.g., data[15•.8l
A list of symbolic names separated by commas enclosed in
parentheses, e.g., (a~b~c~d)

I

Groups may be combined with other AHDL constructs to simplify
implementation of bus-oriented designs.

Logical, Arithmetic, and Comparison Operations
AHDL provides a complete set of logical, arithmetic, and comparison
operators. Any number of operators can be applied to define a node or
group of nodes. Operations may be performed on groups, single nodes,
numbers, and constants. The arithmetic operators can be used for functions
such as adders and counters; comparison operators allow decoding logic
to be implemented quickly. A complete list of AHDL operators is shown in
Table 1.

Table 1. AHOL Operators
Operator

!, NOT
&,AND
!&, NAND
I,OR
!tt, NOR
$, XOR
!$, XNOR
+

-

-

--

!=
<
<=
>
>=

I Page372

Function
One's complement
Logical AND
Logical NAND
Logical OR
Logical NOR
Exclusive OR
Exclusive NOR
Addition
Two's complement
Subtraction
Equal to
Not equal to
Less than
Less than or equal to
Greater than
Greater than or equal to

Example

!eor
bread & butter
a[3 •• 11 !& b[6•• 4]
trick I treat
here !ttthere
(a,b,c) $ data[2•• 8]
x2!$ x4
counU4•. 11 + 1
-datan•.8]
aU5 .•8] - b[31 •.16]
counU7 .•8] = 288
(a[] & MASX) != 8
(a[] + b[]) < c[]
cOl"lp[23 ••8ll<= H"ABCDEF"
counU] > MAXIMUM
addressU5 •• 14] >= 2

A/tera Corporation

I

I Application Note 22

Designing with AHDL

I

Function Prototypes for Hierarchical Text Design
A designs can incorporate ("call") another lower-level design with the
FUNCTION construct, which specifies the inputs and outputs of a lowerlevel function. The logic of a lower-level design may then be called any
number of times within an AHDL design. Any user-created schematic or
text design can be called with a function prototype. In addition, MAX +PLUS
provides a library of over 300 TIL and custom macrofunctions that also
can be integrated into AHDL.

IF-THEN and Case Statements for Conditional Logic
For conditional logic, AHDL provides both IF-THEN and CASE statements.
The IF-THEN statement describes conditional logic based on the evaluation
of one or more Boolean expressions. The keywords ELSE and ELSIF
prioritize the order in which conditions are evaluated.
The CASE statement is an alternative method for describing conditional
logic. It is more compact than the IF-THEN statement when multiple
conditions of a single Boolean expression are evaluated. For example, a
CASE statement can easily define logic based on the different possible
values of an address bus. The CASE statement is also especially helpful for
describing state machine transitions. The keyword OTHERS in a CASE
statement allows default operation when the group value is not specified
in one of the "'HEN clauses. Both the IF-THEN and CASE statements can be
nested for very complex conditional logic.

Truth Table for Decode Logic
The TABLE construct in AHDL decodes output values for a set of inputs.
The TABLE construct eliminates the need to extract Boolean expressions
from a function table; the table itself is directly implemented with the
construct. Functions that are intuitively represented with a truth tablesuch as BCD decoders, address decoders, and state machine transition
logic-can be entered wi th this construct.

State Machines for Control Logic
Control logic based on state machines is implemented with the MACHINE
construct. A designer simply defines state names and describes the state
transitions to implement a state machine. The MAX+PLU5 Compiler
automatically selects the most efficient register type (D or n and calculates
the next-state equations. The determination of the required number of
state bits and the assignment of these bits can also be automatic, or they can
be completely controlled by the deSigner. State transitions and state machine
outputs are easily described with CASE, IF-THEN, or TABLE constructs.

I Altera Corporation

Page 373

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1m
I

I Designing with AHDL

Application Note 22

I

A single design can contain any number of these AHDL constructs. This
flexibility enables a system designer to define a complete behavioral
description for any MAX EPLD design quickly and efficiently.

AHDL Design
Examples

The sample designs provided in this section show all AHDL keywords in
upper case and user-defined symbolic names in lower case. Consistent
formatting (e.g., indentation of IF-THEN and CASE statements) and
comments enclosed in percent symbols ("') are used to increase readability.
However, designers are free to use whatever formatting method suits
them.

Address
Decoders

EPLDs are commonly used to decode microprocessor address lines to
provide all system memory and I/O chip selects. I/O and memory mapping
for a generalized 16-bit microprocessor is shown in Figure 1. This system
contains a bank of ROM and a bank of RAM in memory space. I/O space
includes a print buffer and two serial ports.
Figure 1. 16-Bit Microprocessor Memory and VO Space
Memory Mapping

1/0 Mapping

H"FFFF"

H"FFFF"

Unused
H"AOOO"
Static RAM
H"SOOO"
Unused
H"4000"
Program ROM

-Serial Port 2
-Serial Port 1
- P r i n t Buffer

H"0370"
H"02DE"
H"02AE"

AHDL groups and comparison operators implement the address decoding
for this system. Grouped address lines can be treated as a single element,
which is then compared to the boundaries defined by the memory and I/O
mapping in Figure 1. Figure 2 shows an AHDL design that im plements the
address decoder.

IPage 374

Altera Corporation

I

[APPliCation Note 22

Designing with AHDL

I

Figure 2. Address Decodsr with Group Operations
SUBDESIG" decode (
K The SUBDESIG" declaration of AHDL defines the interface K
K to the logic function. Entering this section is
K

K

e~uiyalent

to entering input. output. and bidirectional K

K pins in a scheMatic.

K

addr[15 •• 8].M/io
rOM. raM. print. sp[Z .• I]

K
K
K
K
K
K
K
K

:I"PUT;
:OUTPUT;

The BEGI" ke~word Marks the beginning of the SUBDESIG"
bod~. The designer describes the behayior of the
function in this section. The MeMor~ Map in Figure 1
is described in the SUBOESIG" bod~ with AHDL cOMparison
operators. This exaMple is for a generalized 16-bit
Microprocessor s~steM. This function can be easil~
Modified to iMpleMent the address decoding for an~
Microprocessor-based s~steM.

rOl"l
raM
print
spl
spZ

M/io & hddr[]
M/io & (addr[]
& hddr[ ]
!M/io & (addr[]
!M/io & (addr[]
!M/iO & (addr[]

K
K
K
K
K
K
K
K

< H"4888");
< H"ABBB")
)=

H"BBBB");
H"8ZAE");
H"BZDE");
H"B378");

E"O;

Address decoders can also be described with the TABLE construct. Figure
3 shows the address decoder described in Figure 2 implemented with a
truth table.

Figure 3. Address Decoder with Truth Table
SUBDESIG" decode (
addr[15 .• B]. M/io
rOM. raM. print. sp[Z •• I]

TABLE
M/io.

1
1

B
B
B
E"D

I A/tera Corporation

addr[15 •• 8]

:I"PUT;
:OUTPUT;

=> rOM. raM. print. sp[];

• B"BBXXXXXXXXXXXXXX" =>
• B"IBBXXXXXXXXXXXXX" =>

• B"BBBBBBIBIBIBII1B"
• B"BBBBBBIBIIBIIIIB"
• B"BBBBBBIIBIIIBBBB"
TABLE;

=>
=>
=>

1 •
8 •

B •

B

1 •

B •
8 •

B •
B •

B •

8 •

8
1
8
B

• B"B8";
• B"BB";
• B"B8";
• B"Bl";

• B"18";

Page 375

I

I Designing with AHDL

Application Note 22

I

The choice of which method to use is up to the designer. The truth table
method provides a more compact format when the address range can be
decoded with one line in a table. The comparison operators provide
quicker and more intuitive integration when multiple lines of a table are
required. However, both methods produce the same results.

Counters

Almost every design requires at least one counter for timing or control
logic. EPLDs contain a superior mix of combinatorial and registered logic,
making them ideal for integrating counters.
The MAX+PLU5 ITL MacroFunction Library contains all of the common
TIL building blocks used to integrate counter logic. The hierarchical
features of AHDL allow easy integration of these ITL-equivalent counters.
Figure 4 shows an AHDL design that integrates two 74161 counters to
create an eight-bit counter. This design is easily modified to link several
74161s or other TIL counters. A counter of any width can be created by
linking the appropriate number of functions.
Figure 4. Eight-Bit Counter with Two 74161 Macrofunctlons
FUNCTION ?4161
(d.c.b.a.ldn.enp.ent.clrn.clk)
RETURNS (rco.~d.~c.~b.~a);

x The Function

Protot~pe defines the inputs and outputs of
x the ?4161 in the MAX+PLUS TTL MacroFunction Librar~.

SUBDESIGN ttl count (
c I k • Id. en. c I r. d [? •• 8]
cB. ~[?.8]

x
X

: INPUT;
:OUTPUT;

VARIABLE
c4 :NODE;
BEGIN
(c4.~[3 •• 8])

(cB.~[?

.8»

?4161(d[3 •• 8]. !Id. en. en. !clr. clk);
?4161(d[? .4]' !Id. en. c4. !clr. clk);

END;

Counters can also be described with the powerful operators and constructs
built into AHDL. Figure 5 shows a nine-bit counter that provides the same
load, hold, and count functions as the 74161.

IPage 376

Altera Corporation

~plication Note 22

Designing with AHDL

I

Rgure 5. Nine-Bit Counter with Load and Enable
SUBDESIG" ahdlcnt (
clk, Id, en, ch, dU •• Bl
~[8

:I"PUT;
: OUTPUT;

•. Bl

VARIABLE
count[8 •• Bl : DFF;

BEGI"

=
=

count[ 1. clk
clk;
!clr;
count[l.clrn
IF Id THE"
d[l;
count[l
ELSIF en THE"
count[l
counUl + 1;

=

ELSE
count[ 1

E"D IF;

= count[l;

= count[ 1;

~[l

E"D;

This example can be modified to integrate a counter of any width by
changing the width of the d[ J, fI[ J, and CQunt[ J groups. To incorporate
more counter functions, additional conditional logic may be specified.. For
exam pIe, adding count-down capability to the previous design requires an
additional input signal and a slight modification to the IF -THEN sta tement.
The modified. design is shown in Figure 6.
Figure 6. Nine-Bit Up/Down Counter with Load and Enable
SUBDESIG" ahdlcnt
clk, Id, en, clr, up/down. d[8 •• Bl
•• Bl

~[8

:I"PUT;
:OUTPUT;

VARIABLE
count[8 .. 81 :DFF;

BEGI"
count[l.clk
count[l.clrn

IF Id THE"
count[l

= clk;
= !clr;
= d[];

ELSI F en THE"
IF up/down THE"
count[l

ELSE
count[]

EtiDIF;

count[l + 1;

= count[l

- 1;

ELSE
count[]

count[];

E"D IF;
~[l

= count[];

E"D;

IAltera Corporation

Page 377

I

,

1

Application Note

Designing with AHDL

Arithmetic
Logic

221

AHDL provides arithmetic and comparison operators to create compact
arithmetic designs. A function frequently described in MAX EPLDs is an
integrator that stores the result of an adder and feeds the result back to the
adder. With this function, a series of numbers can be integrated into a sum.
Figure 7 shows an example of a 16-bit integrator. The 16-bit result is cleared
to zero when the clear input signal is high. Each clock adds the value
represented by the 8-bit bus (add[ ] ) to the previously calculated sum in a
bank of registers (resul t[ J ). The result is connected to the output signals
(SUM[ J).
Figure 7. 16-81t Integrator
SUBDESIG" 16int (
clock. add[7 .• B]. clear
su",US •• B]

I"PUT;
OUTPUT;

VARIABLE
DFF;

resultUS .. B]

BEGI"

=

result[].clk
clock;
result[].clrn = !clear;
result[]
result[] + add[];
su",[]
result[];

=

=

E"D;

DRAM
Controller
State Machine

Dynamic RAM devices (DRAMs) are useful for inexpensive, efficient,
high-density storage. However, DRAMs require controllers that ensure
proper operation. Part of the controller is typically based on a state machine
that controls the active-low row-address and column-address strobes and
select lines that select the row, column, or refresh addresses. Figure 8
shows an AHDL design that controls these signals (/ras, ;lcas, and s[ ]) for
a simple DRAM system.
This simple example of a DRAM controller-which uses state transitions
defined with CASE and IF-THEN statements-can be modified to create a
more complex controller. The implementation of an 8-Mbyte DRAM system
is described in "AHDL Top-Down Design Methodology" in this application
note.

I Page378

A/tara Corporation

I

I Application Note 22

I

Designing with AHDL

Figure 8. DRAM Controller State Machine
SUBDESIGN draM_sM (
clk, /reset, /Mre" refresh
/ras, /cas, sU .. B1

VARIABLE
control

: INPUT;
:OUTPUT;

MACHINE OF BITS (ras, cas, sel[I •. B1>
~ITH STATES (
B"BBBB",
idle
strobe_row
B"IBBB",
B"IIIB",
strobe_col
refresh_draM
B"IBll"

>;
BEGIN
X
X
X
X
X
X

~hen

a MeMor~ re,uest (/Mre,> is receiYed, the
controller generates a /ras, then switches Multiplexer
select and generates a /cas. ~hen a refresh is
re,uested, the controller actiyates /ras and waits for
refresh re,uest to be deasserted before going back to
the idle state.

=

X
X
X
X
X
X

control.clk
clk;
control.reset
!/reset;
CASE control IS
~HEN idle =)
IF refresh THEN
control
refresh_draM;
ELSIF !/Mre, THEN
control
strobe_row;
END IF;
~HEN strobe_row =)
control
strobe_col;
~HEN strobe_col =)
control
idle;
~HEN refresh_draM
IF !refresh THEN
control
idle;
END IF;
END CASE;
/ras
!control.ras;
/cas
!control.cas;
s[l
control.sel[l;

=

=
=

=
=

=

END;

Sync Detector
State Machine

IAltera Corporation

A truth table is also very efficient for representing state machine transitions.
Figure 9 shows a function that synchronizes a serial receiver to the incoming
data stream. This synchronization-detector state machine searches an
incoming serial data stream for a pattern of six successive 1s.

Page 379

I

mJ

I Designing with AHDL

Application Note 22

I

Figure 9. Synchronous Detector State Machine
SUBDESIG" s~nc_det
clock, data_in
s~nc

I"PUT.
OUTPUT.

)

UARIABLE
detect

ttACHI"E OF BITS <'1[2 •• 8])
WITH STATES <
zero.
one,
two,
three,
four,
five )

.

BEGI"
detect.clk
clock.
TABLE
detect, data_in
zero
1
one
1
one
8
two
1
two
8
three ,
1
three ,
8
four
1
four
8
five
1
five
8
E"D_TABLE.
E"D.

=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>

detect.
one
two
zero
three ,
zero
four
zero
five
zero
five
zero

s~nc.

B.
B.
B.
B.
B.
B.
B.
B.
B.
1.

B.

This design samples the incoming data stream and moves to the subsequent
state whenever the serial input is 1. Any 8 sampled in the stream causes
the state machine to make a transition back to state zero. The synchronous
signal is true whenever the machine is in state five (Le., five successive 1s
have been sampled) and the data_in is at 1.
State names are not assigned state values in this example because the
MAX+PLUS Compiler automatically determines an efficient set of statebit assignments. However, some state machines have state bits that are
used as outputs, in which case the state bit assignments must be explicitly
specified as shown in Figure 8.

MAX+PLUS
Text Editor

IPage 380

Any ASCII text editor may be used to create AHDL designs. However, the
MAX+PLUS Text Editor provides commands that specifically support
EPLD design. Like the MAX+PLUS Graphic Edi tor, the Text Edi tor provides
automatic error location. Whenever an error is detected during compilation,
an error message is generated and the line containing the error is highlighted.
Automatic error location allows the designer to quickly debug a text file for
syntax and electrical rule errors (e.g., outputs tied together).
A/tera Corporation

I

I Application Note 22

Designing with AHDL

I

The MAX+PLUS Text Editor also offers delay prediction, which allows a
logic designer to specify a signal path in an AHDL design for analysis. The
delay prediction command then reports the worst-case timing for the path.
For example, the worst-<:ase frequency of a state machine may be determined
by performing delay prediction on paths from state bit to state bit. These
error location and delay prediction features enable designers to quickly
create AHDL designs.

AHDL TopDown Design

The following four steps illustrate the top-down approach to AHDL design:
1.

Create a block diagram of the design. In this step, the major functions
and the communication between them are defined.

2.

Declare the inputs and outputs of the design. The required input,
output, and bidirectional signals can be determined from the block
diagram, and then declared in the AHDL Subdesign Section.

3.

Declare the major functions of the design. Each block of the diagram is
a major function that can be easily translated into AHDL variables.
These variables are declared in the Internal Declarations Subsection.

4.

Describe the major functions. The internal logic for each of the major
functions is implemented with AHDL constructs in the body of the
Subdesign Section.

Entering comments in the AHDL design file also enhances the readability
of an AHDL design.
The following example follows this top-down design method to create a
DRAM controller. This controller controls an 8-Mbyte DRAM system
organized in 32-bit words. Refer to Application Brief 85 (DRAM Controller
Using an EP1830 EPLD) for a complete operational description of this
design.

Step 1: Block Diagram
Figure 10 shows the block diagram of an 8-Mbyte DRAM controller. The
design controls all access to dynamic RAM organized on a 32-bit bus. The
controller interfaces directly to a microprocessor address and control bus
and a 20-MHz clock signal. Reset capability is also provided. This system
produces row address strobe (R AS), column address strobe (CAS), and the
dynamic RAM address. In addition, the controller provides the data strobeacknowledge (DSACX) to the processor. The controller consists of a refresh
timer, a refresh counter, an address multiplexer and a RAS / CAS generator.
The state transition diagram for the RAS/CAS generation is shown in
Figure 11.

I Altera Corporation

page381]

1m
I

Application Note 22

[DeSIgning with AHDL

I

Figure 10. Eight-Mbyte DRAM Controller
System Address
DRAM Address [9 .. 0)

Clock

IDSACK
lAS

IRAS(1..0)

SIZ[1..0)

/cAS(3 .. 0)

Figure 11. Stat. Transition Diagram for RAS/CAS Generator
Vasa lreUeq& !sa22&sa1 &saO
!/as&lreCreq&!sa22&sa1&!saO

Vasa lreCreq&sa22&sa1 &saO
Vas&!reCreq&sa22&sa1 & !saO
Vas&!reUeq&sa22&!sa1&saO

Vas&!reUeq&!sa22&!sa1&saO
!/as& lreUeq& !sa22& !sa1 & !saO

L-____-1======~======~ro IDLE

to

L __-=======~to IDLE

to =========--__:1

L -_ _ _ _ _ _ _ _ _ _ _...

I Page382

Vas&!reCreq&sa22&!sa1&!saO

ro IDLE

IDLE

!=============:!..____J

IDLE

ro

IDLE~--------------------~

Altera Corporation

I~A_P~P~/'_ic_a_h_o_n_H_o_'_e_2_2_____________________________________________D_e_s~/g~n_~_=n~_WnhAH~
Step 2: Declare the Inputs & Outputs
The interface to the DRAM controller can be determined from the block
diagram. The input and output declarations for this design are shown
below.
TITLE

"B-Hegab~te

DRAH Controller";

SUBDESIG" dra"_ctl
sa£22 .• 8].
clock.
sizell .• 8].
.las.
reset

da[9 •• 8].
.Idsack.
.Iras[1 •. 8].
.Icas[3 .. 8]

s~ste" address
28-HHz clock
size of "e"or~ operatiDn
address strobe
"aster reset

:I"PUT;

"
"
"
"
"

:OUTPUT;

" DRAH address
Yo data strobe acknowledge
" row address strobe
"colu"n address strobe

""
"
""
Yo
"
Yo

Step 3: Declare the Major Functions
Each block in the block diagram is a major function of the DRAM controller.
These major functions are declared as variables in the Internal Declarations
Section of an AHDL design:
UARIABLE
:"ODE;
" The address "ultiplexer is a purel~ co"binatorial
" function. It selects the row. colu"n. or refresh
Yo address based on the current c~cle. The yariable
Yo t~pe "ODE defines a general-purpose signal that
Yo allows inter"ediate logic to be defined.
ref_address[B •• 8]

counter that
The yariable

I Altera Corporation

Yo

Yo
Yo

"

:DFF;
:"ODE;

The refresh ti"er also re~uires a 9-bit
counter. This function also proyides a ti"eout
Yo signal that is assigned to t~pe "ODE.
Yo
Yo

"

:DFF;

Yo The refresh counter contains a 9-bit
Yo re~uires 9 registers to be declared.
Yo t~pe DFF defines a D-t~pe register.

ref _ ti"er[B •• 8]
ti"eout

Yo
Yo
Yo

1m

"

Yo
Yo

page3S3

1

Application Note 22

[ Designing with AHDL

I

ref_rell :DFF;
control :HACHINE OF .ITS(cas[3 .• Bl,ras[I •• Bl,dsack,ref>
WITH STATES (
."BBBBBBll",
idle
rowBoffB
."BBBBBlll",
."BBBBB111" ,
rowBoffl
."BBBBB111" ,
rowBoffZ
."BBBBBlll",
rowBoff3
."BBB1B1Bl",
rowBofrBs izl
."BBllB1Bl" ,
rowBoffBs izZ
."Bll1B1Bl" ,
rowBoffBs iz3
."1111B1Bl" ,
rowBoffBs iz4
."BB1BB1Bl",
rowBoffls izl
."BllBB1Bl" ,
rowBofflsizZ
."111BB1Bl" ,
rowBofflsiz3
."B1BBB1Bl",
rowBoffZsizl
."l1BBB1Bl" ,
rowBoffZsizZ
."IBBBB1Bl",
rowBoff3sizl
."BBBB1Bll" ,
rowloffB
."BBBB1Bll" ,
rowloffl
."BBBB1Bll" ,
rowloffZ
."BBBB1Bll" ,
rowloff3
."BBB11BB1" ,
rowlofrBsizl
."BB111BB1" ,
rowloffBsizZ
."BllllBB1" ,
rowloffBsiz3
."I1111BB1" ,
rowloffBsiz4
."BB1B1BB1",
rowlofflsizl
."BllB1BB1" ,
rowloffls izZ
."I11B1BB1" ,
rowlofflsiz3
."B1BB1BB1",
rowloffZsizl
8"l1BB1BB1" ,
rowloffZsizZ
8"IBBB1BB1",
rowloff3sizl
8"BBBB111B" ,
refreshB
8"BBBB111B" >;
refreshl

=
=

=

Yo
Yo
Yo
Yo

The RAS/CAS generator contains a latch for refresh
relluest and a state "achine na"ed control. The
state na"es are extracted fro" the state "achine
transition diagra".

Yo
Yo
Yo
Yo

Step 4: Describe the Major Functions
Each of the major functions is described with AHDL constructs. The
subdesign body of the AHDL design is shown below. Comments in this
section describe the operation of each function.

I Page384

Altera Corporation

I

IApplication Note 22

Designing with AHDL

I

BEGI"

y,y,----------------------------------------------------------y,
Address
y,
y,----------------------------------------------------------y,
y, The address "ultiplexer controls the address that is
Yo
connected to the
devices. During the idle state
y,
y, and the RAS-generation states. this "ultiplexer selects Yo
y, the row address (sa[21 •• 12). During the CAS-generation Yo
y, states. the colu"n address (sa[II •• 2) is selected.
Yo
~ultiplexer

DRA~

Y,

Y,

During refresh

c~cles.

the refresh address is selected.

Yo

IF ref THE"
da[8 •• H)
ref_address[);
ELSIF dsack THE"
dd]
sdl1. .2];
ELSE
da[]
sd21 •• 12];
E"D IF;

=

da[]

= address_"ux[];

Yo----------------------------------------------------------y,
Yo
Refresh Counter
y,
Yo----------------------------------------------------------y,
y, The refresh counter incre"ents the refresh address
y,
Yo refresh
The counter is initialized to zero
a
Yo
Yo reset signal.
y,
ever~

c~cle.

b~

ref_address[].clk
ref_address[].clrn
IF ti"eout THE"
ref_address[]
ELSE
ref_address[]
E"D IF;

= clock;
= !reset;
ref_address[] + 1;
ref_address[];

Yo----------------------------------------------------------Yo
Refresh Ti"er
Yo----------------------------------------------------------Yo
Yo A refresh c~cle is re~uired on all 512 rows ever~ 8 "So
Yo Yith a clock fre~uenc~ of 28 ~Hz. the nu"ber of c~cles

y,
y,

between refresh re~uests is 312. The refresh ti"er is a
free-running counter that counts fr~ 8 to 311. Refresh
Yo re~uest is generated when the counter is at 311.

Y,

y,
y,
y,
Yo

=
=
==
=

ref_ti"er[].clk
clock;
ref_ti"er[].clrn
!reset;
IF (ref_ti"er[]
MAX_REF_TIMER) THE"
ref_ti"er[]
H;
ti"eout
UCC;
ELSE
ref_ti"er[] = ref_ti"er[] + 1;
E"D IF;

=

I Altera Corporation

Page 385

I

1

Designing with AHDL

Application Note

221

X----------------------------------------------------------x
x
HAS/CAS Generator
X
x----------------------------------------------------------x
X
X
X
X
X
X
X
X
X
X
X

The HAS/CAS generator controls c~cling through the HAS.
CAS. and refresh c~cles. The HAS/CAS generator waits in
the idle state until either a refresh re~uest (refre~)
or an address strobe (/as) is received. Uhen a refresh
is received. /rasl and /rasB are asserted for two clock
c~cles. The first c~cle after /as is received. the
appropriate /ras is asserted. The next clock c~cle
asserts the appropriate /cas signals based on the offset
and size of the re~uest. The /dsack signal is also
asserted during this c~cle. The third c~cle deasserts
/ras. /cas. and /dsack. and returns to the idle state.

X
X
X
X
X
X
X
X
X
X
X

= clock;
= tiMeout .
I
& control.ref;
control.clk = clock;

ref_re~.clk

ref_re~

ref_re~

control.reset = reset;
CASE control IS
UHEti idle =>
IF ref_re~ THEti
control = refreshB;
ELSIF !/as & (sa[I .. B] == B)
IF sa22 THEti
control
rowloffB;
ELSE
control
rowBoffB;
EtiD IF;
ELSIF !/as & (sa[I •. B] == 1)
IF sa22 THEti
rowloffl;
control
ELSE
rowBofrt ;
control
EtiD IF;
ELSIF !/as & (sa[I .• B] == 2)
IF sa22 THEti
rowloff2;
control
ELSE
control
rowBoff2;
EtiD IF;
ELSIF !/as & (sa[I .. B] == 3)
IF sa22 THEti
rowloff3;
control
ELSE
control
rowBoff3;
EtiD IF;
EtiD IF;
UHEti rowBoffB =>
IF (size[] == 1) THEti
control = rowBoffBsizl;
EtiD IF;
IF (size[] == 2) THEti
control = rowBoffBsiz2;
EtiD IF;
IF (size[] == 3) THEti
control
rowBorfBsiz3;
EtiD IF;

1

Page386

THEti

THEti

THEti

THEti

Altera Corporation

1

IApplication Note 22

Designing with AHDL

IF 
1) THEN
IF 
IF (she[] == 1) THEN
control = rowBoffZs hi;
END IF;
IF 
IF (size[] == 1) THEN
control = rowBoff3sizl;
END IF;
"'HEN rowloffB =>
IF (size[] -- 1) THEN
control = row1offBsiz1;
END IF;
IF (size[] -- Z) THEN
control = row1offBs hZ;
END IF;
IF 
I) THEN
IF (s he[]
control = row1offts hi;
END IF;
IF (s he[] -- Z) THEN
control = rowloffts hZ;
END IF;
3) THEN
IF (s ize[]
control = rowlofflsiz3;
END IF;
"'HEN rowloffZ =>
IF (she[] -- 1) THEN
control = rowloffZsizl;
END IF;
IF 
IF (she[] -- 1) THEN
control = row1off3siz1;
END IF;
"'HEN refreshB =>
control = refresh1;

==

---

--

IA/tera Corporation

1m
Page 387

I Designing with AHDL

Application Note

WHEtt OTHERS
control

EttO CASE;
.... dsack
.... ras[]

.... cas[]

221

=)

= idle;

= !dsack
!ru[]
! cas[]

IttO;

Conclusion

AHDL allows the designer to describe any MAX EPLD design with a
variety of AHDL constructs and the MAX+PLUS TTL MacroFunction
Library. The MAX+PbUS Text Editor provides error location and delay
prediction to ensure error-free AHDL designs. MAX+PLUS provides a
hierarchical design environment to integrate multiple text and graphic
functions into a single design, so that each portion of a design can be
represented in the most intuitive form. AHDL designs are compiled with
the MAX+PLUS Compiler, which provides automatic logic minimization,
logic synthesis, and device fitting to guarantee efficient use of MAX EPLD
resources. In addition, MAX+PLUS provides a timing simulator and
advanced timing analyzer for design verification. AHDL, together with
Altera's MAX +PLUS Development System, provides unsurpassed entry,
processing, and verification for text-based designs.
For a copy of any of the sample designs shown in this application note,
contact Altera Applications at 1 (BOO) BOO-EPLD.

I Page388

Altera Corporation

I

---_.,

Counter Design
for EP-Series EPLDs
' - - - - - - - - - - _ . _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _..-

Ap,,-lication Brief ~J

October 1990, ver. 3

'-----------------------------------

Introduction

Counters--<>ften the most useful building blocks in digital design-are
easily constructed in EPLDs. This application brief discusses efficient
counter design for EP-series devices, using both schematic capture and
Boolean equation design entry methods. EP-series EPLDs can implement
binary, decade, and Gray-cod.e counters that include load, enable, clear,
and cascade options.

Choosing a
Flip-Flop

Toggle (T) flip-flops are used to build the simplest and most efficient
counters. The advantages offered by T flip-flops become apparent when
the two 8-bit binary counter designs shown in Figures 1 and 2 are compared.
The Altera Design File (ADF) counter in Figure 1 uses D flip-flops, which

Figure 1. Counter with 0 Flip-Flops
Counters that use Dnip-flops require an additional product term
for each successive Significant bit.

Figure 2. Counter with TFlip-Flops
Counters that use T flip-flops require only one product term for
each significant bit.

Alte ... Corpo ... tioll
EP61B
a-lIT IJ"ARY COU"TER \,11TH I FLIP-FLOPS

Alte ... Corporatioll
EPUB
a-lIT II"ARY COU"TEII \,11TH T FLIP-FLOPS

PART: EP61B
J "PUTS: E"AILE, RESET, ClOCK
OUTPUTS: OB, 01, 02, 03, 04, OS, 06, 07
"ETI.IORK:
EHAllE • I"P(E"AllE)
c n . IHP(RESET>
CK
• JHP(C10CK)
OB,08 • RORF(QI.,CK,C1R,,)
01,01 • RORF(01.,CK,C1R,,)
02,02 • RORF(02.,CK,C1R,,)
03,03 • RORF(03.,CK,C1R,,)
04,04 • RORF(04.,CK,C1R,,)
05,05 • RORF(05.,CK.Cn,,)
06,06 • 1I0RF(06.,CK,C1R,,)
07,07 .1I0IlF(07 •• CK,C11I,,)
EWATIOHS:
07. • .... OB • 07 + .... 01 • 07 + .... 02 • 07 + .... 03 • 07
+ .... 04 • 07 + .... 05 • 07 + .... 06 • 07 + .... EHAILE • 07
+ EHAnE • OB • 01 • 02 • 03 • 04 • 05 • 06 • /07:

PART: EP618
I HPUTS : E"AlI.E. IIESET, ClOCK
OUTPUTS: OB, 01, 02, 03, 04, os, 06, 07
HETI.IORK:
EHAllE • IHPCEHAllE)
c n . 1"'CRESET)
CK
• IHP(CLOCK)
OB,OB • RORF(Qlt,CK.C1II,,)
01,01 .1I0RF(0It,CK,CLII,,)
02,02 • RORF(02t,CK,CLR,,)
03,03 • RORF(03t,CK,CLR,,)
04,04 • 1I0RF(04t,CK,CLR •• )
05.05 • 1I0RF(05t,CK,CLR,,)
06,06 • 1I0RF(Q6t,CK,CLR,,)
07.07 • RORF(07t,CK,CI.R,,)
EWATIOHS:
07t • EHAI1E • OB • 01 • 02 • 03 • 04 • 05 • 06:

06. • .... OB • 06 + .... 01 • 06 + ....02 • 06 + .... 03 • 06
+ /04 • 06 + ....05 • 06 + ....EHAllE • 06
+ EHAnE • OB • 01 • 02 • 03 • 04 • 05 • .... 06:

06t • EHAII.E • 08 • 01 • 02 • 03 • 04 • 05:
05t • EHAILE • 08 • 01 • 02 • 03 • 04:
04t • EHAILE • 08 • 01 • 02 • 03:

05......OB • 05' + .... 01 • 05 + .... 02 • 05 + .... 03 • 05
+ /04 • 05 + ....EHAILE • 05
+ EHAI1E • OB • 01 • 02 • 03 • 04 • /05:

03t • EHAILE • 08 • 01 • 02:

04i • ....OB • 04 + .... 01 • 04 + .... 02 • 04 + .... 03 • 04
+ .... EHAnE • 04
+ EHAnE • OB • 01 • 02 • 03 .....04:

01t • EHAILE • 08:

03 ......OB • 03 + /01 • 03 + /02 • 03 + .... EHABLE • 03
+ EHAI1E • 08 • 01 • 02 .....03;

02t • EHAnE • OB • 01:

OBt • EHAILE:
EHI.

02. • .... OB • 02 + .... 01 • 02 + /EHAB1E • 02
+ !HAnE • 08 • 01 • .... 02:
01 ......OB • 01 + .... EHAI1E • 01 + EHABLE • OB .....01:
OB. • .... EHAnE • OB + EHABlE • .... OB:
EHI.

Altera Corporation

Page 389

I

I Counter Design for EP-Serles EPLDs

Application Brief 8

I

require an additional product term for each successive significant bit (in
the Equations Section). The most significant bit, Q7, rEquires 9 product terms.
The counter in Figure 2 uses T flip-flops. Each counter bit requires onl y one
product term. Thus, D flip-flops require significantly more gated logiC to
construct the equivalent counter function.
Altera EP-series EPLDs provide eight product terms per macrocell and
offer programmable D, T, JK, and SR flip-flops. Using D flip-flops, only a
seven-bit counter fits within each EPLD macrocell (the nth bit requires n+1
product terms). Counters built with T flip-flops can be any size, and still
only consume one product term per bit. Therefore, T flip-flops are generally
the best choice for counter design.

Designing
Counters with
LogiCaps &
Macrofunctions

I Page390

Altera's A+PLUS TIL MacroFunction Library provides 21 predefined MSI
counters, shown in Table 1. These counters range in function from decade
to binary, and include a variety of features such as load, clear, enable, and
cascade options. Some entries are TTL part numbers followed by a "T"
(e.g., 74163T), indicating that T flip-flops were used to implement the
counter. The library also includes some specially-designed A+PLUS
counters, such as BeOUtiT (cascadable 8-bit up/down counter), FREQDIU
(4-bit frequency divider), and GRAY4 (4-bit Gray-code counter).

Altera Corporation

I

I Application Brief 8

Counter Design for EP-5erles EPLDs

I

Table 1. Counter Macrofunctions
Name

Options

Type
Bits Decade Binary Gray

Up Down Load Clear Enable
tI'

tI'

tI'

7493

4

74160

4

tI'

tI'

tI'

tI'

tI'

74160T

4

tI'

tI'

tI'

tI'

tI'

74161

4

tI'

tI'

tI'

tI'

tI'

74161T

4

tI'

tI'

tI'

tI'

tI'

74162

4

tI'

tI'

tI'

tI'

tI'

74162T

4

tI'

tI'

tI'

tI'

tI'

74163

4

tI'

tI'

tI'

tI'

tI'

74163T

4

tI'

tI'

tI'

tI'

tI'

74190

4

tI'

tI'

tI'

tI'

tI'

74190T

4

tI'

tI'

tI'

tI'

tI'

74191

4

tI'

tI'

tI'

tI'

74191T

4

tI'

tI'

tI'

tI'

tI'

tI'

74192T

4

tI'

tI'

tI'

tI'

tI'

74193T

4

tI'

tI'

tI'

tI'

tI'

tI'

74393

4

tI'

tI'

tI'

tI'

tI'

tI'

GRAY4

4

4COUNT

4

tI'

tI'

tI'

tI'

tI'

tI'

8COUNT

8

tI'

tI'

tI'

tI'

tI'

tI'

FREQDIV

4

tI'

tI'

16

tI'

tI'

16CUDSLR

tI'

Macrofunction documentation, shown in Figure 3, provides a symbol
name, a function table, and an ADF declaration statement. If macrofunction
inputs are left unconnected, a default value (shown in Figure 3) is used. For
example, UCC is the default value for LDti. Worst-case macrocell
requirements are shown in the lower right-hand corner of the symbol (e.g.,
four macrocells for 4COUtlT). The ''Declaration'' line shows the ADF syntax
for the function. The function table shows the macrofunction operation
under all input conditions. The logic schematic in Figure 4 shows the gatelevel logic for 4COUtiT.

I Altera Corporation

Page 391

I

I Counter Design for EP-5erles EPLDs

Application Brief 8

I

Figure 3. 4COUNT Macrofunction Documentation
Altera Design File Declaration and Default Input Values

4COUNT Symbol

,··········;'COuNT"·········1

Name:

4COUNT (4-Bit Up/Down Counter
with Synchronous Load and
Asynchronous Clear)

Declaration:

4COUNT(CLRN,LDN,DNUP ,CIN,A,
B,C,D,CK,QD,ac,OB,QA,COUT)

(vee)
(GNO)
(GNO)
(GNO)
(GNO)
(VCC)

(vee)
(vee)

(LON = Load, Active Low;
CIN =Carry In; DNUP = Down/Up;
CLRN = Clear, Active Low;
CK = Clock; COUT =Carry Out)

(GNO)

1.u.····················;/·i

EP610, EP630, EP640, EP910,
EP1810, EP1830

EPLDs:

Worst-Case
Macrocell
Requirements

Input
Values

Default Signal Levels: GND - CK, A, B, C, 0
VCC - CLRN, LON, DNUP, CIN

4COUNT Function Table

Outputs

Inputs
CK
X

.r
.r
.r
.r
.r
.r

I Page392

LON CLRN ONUP CIN
X
L
H
H
H
H
H

L
H
H
H
H
H
H

X
X
X
L
H
H
L

X
X
L
H
H
H
H

0

C B A QO QC QB QA COUT

d

c

b

a

L
d

L

L

c

L
b
Hold

a

Count Down

H
L

IC~T~PI
L
L

H
L

X
X
X
L
L
H
H

A/tera Corporation

I

IApplication Brief 8

Counter Design for EP-Series EPLDs

I

Figure 4. 4COUNT Schematic File
AND2

CIN-P
DNUP

I

r····· .... ·NOTj:·l

·l

OR2

~T

LDN~~-.~+------------------------,

;

AND2

p

--r-~

XOR

.l

a~

T

~

·· =r.= ...

A--------~~------------------~~

l

c

l

~

.......... ..........:

aA
AND2

r········ ·NoTi=·l
l·
p
l.

OR2

---

;

AND2

T

~>
l
·

0-+

l

.-.=r...
~

l
.......... ..........:
c

aB

AND2

r········ NOTF·l
l·

OR2

;

AND2

p

T

l.

0-+

~>

~

·· =r.= ..
l

c

l

i. ..................... :

ac

AND2

t····················.
NOTF:

:

I

OR2
AND2

p

I

)..-I.--f--:"';-I T O - + -

~>
l

c

l
l

L.~ ....l

r----------*--------------------~~----------~-aD

,

a-f-+-+-+-----I AND6

.J

L..+-+-~I----a;ll

.......-+---0;

OR2

BAND6

'l----------.....

NOT

CLRN

CK----------------------------------------------------.. .
I Altera Corporation

Page 393

I

I Counter Design for EP-Ser/es EPLDs

MacroMunching

Application Brlef'l

MacroMunching, a logic synthesis feature of the A+PLU5 software,
automatically removes unused portions of a macrofunction. (See
PLS-SUPREME: Enhanced A+PLUS Programmable Logic Software Data Sheet
in this data book for a description of MacroMunching.) For example, if a
design requires only a 3-bit counter, 4COUtiT may still be used. By leaving
the extra counter bit QD unconnected, its flip-flop and related gated logic
are removed automatically from the design and do not consume any of the
EPLD's resources. A+PLU5 macrofunctions and the MacroMunching
capability make it easy to build counters of any size. Figure 5 shows a
13-bit counter that uses A+PLU5 macrofunctions.

Figure 5. 13-81t UplDown Counter
This counter is constructed by cascading two 8-bit counters. MaaoMunching automatically removes the unused bits.
01

02

01 ~----------~------~

D2

-+--------;~~-------,. 03

03

Q4

05

as
07

07 r::::::}---------'

08

~_------J

Q9

010

~_----J

011 ~-------.....I

I.--t--C>--C::>= 011

012 C J - - - - - - J
013 c : : : J - - - - - - '

1.--"';""'-1 >--£::>;

................................................ .;
LOAD

~_-------J

012

>--t:=>: 013
··"........................

~--.;-~

-J

ONUP L:.:.;I_ _ _ _ _ _

I Page394

RESET

LJ---------------'

CLOCK

L.,J-----------'
INP
Altera Corporation

I

I Application Brief 8
Designing
Counters
with Boolean
Equations

Counter Design for EP-Series EPLDs

Figures 6, 7, and 8 show ADFs for a 4-bit binary up counter (74161), a 4-bit
decade up/down counter (7419BT), and an 8-bit binary up/down counter
(8COUNT) with load, enable, and clear options. Other counters may be
designed with the Boolean equations given in these ADFs.

Figure 6. 4-Bit Binary Counter with Load and Clear

Figure 7. 4-Bit Up/Oown Oecade Counter with Load

Rltera Corporation
1BI'1I'9B
1.BB

Rltera Corporation
1BI'1I'9B
1.BB

B

R

EP61B
4-BIT BIHRRY UP COUHTER UITH SYHCHROHOUS LORD,
RSYHCHROHOUS CLERR

EP61B
4-BIT UPI'DOUN DECRDE COUNTER (7419BT)

PRRT:

PRRT:

EP61B

IHPUTS:
CLOCX

I'CLERR, I'LORD, EHP, EHT, R, B, C, D,

OUTPUTS:

INP(I'CLERR)
IHP(I'LORD)
IHP(EHP)
IHP(EHT>
IHP(U
R
IHP-----,

INP
NOT

ENABlEG

I Altera Corporation

...

~---"""--r-

INP

Page 397

I

I Designing Asynchronous Latches for EP-5eries EPLDs

Application Brief 91

Only one macrocell that uses combinatorial feedback is required to
implement the D latch in an EP-series EPLD. (MAX EPLD registers can be
configured as D latches.) This latch can be entered with the 74373
macrofunction or with gate-level logic in LogiCaps, as shown in Figure 1,
or designed with Boolean logic in an Altera Design File (ADF). An ADF for
the transparent D latch is given in Figure 2.

Rgure 2. Transparent DLatch Implemented In an Alters Design File
Altera Corporation
18/11'98

1.8

EPLD
TRAHSPAREHT D-TVPE LATCH
OPTIOHS:
PART:

TURBO=OH

AUTO

IHPUTS:

X AutOMatic part selection X

DATA,EHABLEG,OUTCHTL

OUTPUTS:

Q

HETIolORK:
DATA
IHP(DATA)
EHABLEG = IHP(EHABLEG)
OUTCHTL = IHP(OUTCHTL)
Q,Q = COIF(Qc,OE)
EQUATIOHS:
Qc = I'«/DATA*EHABLEG) + /(EHABLEG + Q»;
X Active high output X

OE

/OUTCHTL;

EHD$

Asynchronous
SR Latch

Asynchronous SR latches are constructed with either cross-coupled NOR
or NAND gates. For the NOR-NOR implementation, the output goes to a
logical one (high) if the Set (S) input is high. The output produces a logical
zero (low) if the Reset (R) input is high. Figure 3 gives symbolic
representations of an SR latch, the A +PLUS macrofunction symbol, function
table, and gate-level LogiCaps schematics.
Only one macrocell that uses combinatorial feedback is required to
implement this latch in an EP-series EPLD. The SR latch can be entered
with the 74279 macrofunction or with gate-level logic in LogiCaps, as
shown in Figure 3, or designed with Boolean logic in an ADF. See Figure 4
for an ADF that implements an SR latch.

I Page398

Altera Corporation

I

I Application Brief 9

Designing Asynchronous Latches for EP-Series EPLDs

I

Figure 3. SR Latch
Symbolic Representations
IS

Function Tables
S - - - - . . -.......

0-._-- 0
0---__- - / 0

IR-------i

XHlt----/O

R _ _ _--:1.'--")0-4...--- 0

NANDLATCH

IS

IR

L
L
H

L
H
L

Q

0
H
L

NORLATCH
S

R

L
L
H

L
H
L

Q

0
L
H

Log iCaps Schematics

Macrofunctions

r------ ---COiF---1
:___________________ ..J SA LATCH

IS

IA

r------ ---COiF----1

A

:___________ _______ ..J ASLATCH

S

Figure 4. SR Latch Implemented in an Altera Design File
Altera Corporation
18/1/98
1.8

EPLD
SR LATCH
OPTIOHS:
PART:

TURBO=OH

AUTO

IHPUTS:

S,R

OUTPUTS:

RSLATCH

HET&.IORX:
S = IHP(S)
R = IHP(R)
RSLATCH,Q = COIF(RSLATCHc,UCC)
EQUATIOHS:
RSLATCHc

/(/(S+Q)+R) ;

x HOR-HOR iMpleMentation

X

EHDS

I Altera Corporation

Page 399

I

1

Designing Asynchronous Latches lor EP-5erles EPLDs

Programmable
Polarity

Application Brief

91

Altera EP-series EPLDs offer superior flexibility to TIL devices for
specifying latch operation. For the transparent latch, the output polarity is
active high (Q = DATA when EtiABLEG is high) when the DATA input pin
drives the tlOT gate, as shown in the LogiCaps schematic in Figure 1. For
an active-low output (Q = I'DATA when EtiABLEG is high), it is necessary
to remove the inverter and connect the DATA input pin directly to the AtlD2
gate. In addition, the OUTCtlTL and EtiABLEG inputs can also be defined
as active high or active low. For example, connecting an inverter after the
EtiABLEG input pin causes the circuit to pass DATA when EttABLEG is low
and latch DATA when EtiABLEG is high.
For Altera EPLDs whose I/O pins do not support direct combinatorial
feedback (EP300-, EP600-, and EP900-series), input feedback can be
substituted to route the signal back into the AND array. For example, the
SR latch implemented with tlAtlD2 gates uses COIF I/O architecture (see
the LogiCaps schematic in Figure 3). When using the COIF primitive, the
output must always be enabled to ensure that the feedback path is connected
to the logic.

Page 400

A/tera Corporation

I

A+PLUS State Machine
Design Entry
Application Brief ~

I October 1990, ver. 2
Introduction

A+PLUS state machine design entry-supported by the PLCAD-SUPREME
and PLS-SUPREME development products-provides a high-level
approach for entering state machine designs. State Machine Files (SMFs)
can be created with IF-THEN or CASE statements and optional truth
tables. State machine entry can be used separately or together with LogiCaps
schematic capture, TIL macrofunctions, and Boolean equations for added
power.
The State Machine File (SMF) format is a superset of the Altera Design File
(ADF) format. Utis also similar to the ASMILE state machine entry language
available with the SAM+PLUS Development Software.) Users who are
unfamiliar with the ADF format should first read Application Brief 71
(A+PLUS Boolean Equation Design Entry) in this data book.

SMF Syntax,

State machine design files are created in the Altera SMF syntax with an
ASCII text editor (in non-document mode). The SMF is divided into
several sections, many of which are defined by a keyword. Each section is
described here. A sample SMF is shown in Figure 1.
During design processing, the A+PLUS State Machine Converter (SMV)
translates the SMF design file into a Boolean-equation-based ADF. The
Altera Design Processor (ADP) then processes the ADF, choosing the best
register (T or D) for each state variable. Finally, the ADP minimizes the
resulting logic, fits the design into an appropriate EPLD, and creates a
]EDEC file for device programming.

Header Section
The optional Header Section includes alll/bookkeeping" information, such
as design title, revision number, designer, and any other desired
information. It has no effect on design processing. This section has no
keyword.

Options Section
The Options Section (keyword OPTIONS:) controls the Turbo Bit and
Security Bit.

I Altera Corporation

page:¥!]

I A+PLUS State Machine Design Entry

Application Brief 14A

Rgure 1. Sample State Machine File (SMF)
Itera Corporation

Header
Section

18/11'98
1.88

EPill!1
Sa"ple State Machine File

{

Options ~PTIOHS:
Section

~

TURBO. OFF. SECURITY. 0"

Co""ents are enclosed in percent

~ s~"bols

~

~

Part
~ART: EPUI!I
Section
Inputs
Ii"PUTS: CLK. E". GOOD. "A I HCLI.
Section ~
I"PUTl. I"PUT2
~ Lhtin, a state variable [Q3J in ~
Outputs ~
~ the Outputs Section causes it to ~
Section ~UTPUTS: Q3. ADDL. OUT1. OUT2 ..~------ ~ t:r~:d~utPut instead of bein,
~

Ne~o~
Section

{ETAUDODRLK.:
RO"F (ADDLd. CLK. GHD. GHD. UCC)
OUT1 • COHF (OUTlc. UCC)
..~
__- - - - OUT2 • COHF (OUT2c. UCC)

Equ~tion~QUATIOHS:

L

Section

STCLR • "AIHCLR • EH: .......
----------

Machine :........r.:;
Section ~ACHIHE:

GOil

Clock -----.I CLOCK: CLK
SubsectionL
Clear
-----.I CLEAR: STCLI
SubsectionL
STATES: [ Q3
[
PU
8
START [ 1
DOIT1 [ 8
DOIT2 [ 8
[
8
GOT1
[
8
GOT2
[
8
EXIT

~~:!c,o{
Transitions
Subsection

l

..~
__- - - - - - - - - - -

~~
~

x The optional E'luations Section
defines internal nodes.
X Each state "achine "ust have
X a uni .. ue na"e. (An~ nu"ber of
X Machine Sections are allowed).
X

..
~
....- - - - - - - - - - - X

-TAB:

EH
8
1
1
1
1

Q8
X
B
8
1
1

The re'luired Clock Subsection

x defines the "achine's clock.

.....
~1----------- X

The optional Clear Subsection
X defines an as~nchronous Clear.

Q2

Q1

QI!I

8
8
8
8
8
8

8
8
8
8

8
8
8

1

1

1
1

8

8

8

Q1
X
8
1
8
1

~

~

x
X
X
X
X
~

X

x

X

X

~

1

PU: START ....~
. .- - - - - - - - - - - - "
START:
"
IF IHPUTI THEH DOIT1
~
IF IHPUT2 THEH DOIT2
DOIT1:
IF GOOD THEH GOTI
DOIT2
DOIT2:
IF GOOD THEH GOT2
DOITI
GOT1:
EXIT
OUTPUTS: ..~
__- - - - - - - - - - - - - - "
ADDL
"
GOT2:
"
EXIT
"
OUTPUTS: ~
"
IF EH THEH START

Truth Table
Section

The Network Section is used to
define all outputs that are not
also state variables.

OUT1c
1
8
1
1
1

OUT2c
1
1
1
1
B

~

The re'luired Transitions
Subsection specifies the
transitions for each state.

"
"
"

The Outputs Subsection specifies"
which internal nodes to activate"
in a ,iven state. The outputs
"
can be conditional or
"
unconditional.
"

" The optional Truth Table Section X
" allows truth table definition of "
" internal nodes.
X

End
-GHD.
StatementL:

Part Section
The Part Section (keyword PART:) specifies the target EPLD. If the AUTO
option is used, A +PLUS automatically selects the best EPLD for the design.
If pin assignments are specified in the SMF, the AUTO option is not
Page 402

Altera Corporation

I

I Application Brief 14A

I

A+PLUS State Machine Design Entry

available, since the assigned pins must necessarily correspond to a particular
EPLD and package.

Inputs Section
The Inputs Section (keyword INPUTS:) specifies all EPLD inputs for the
design. Pin numbers can be assigned by appending an "at" symbol (@) plus
the pin number to the end of the pin name.

Outputs Section
The Outputs Section (keyword OUTPUTS:) declares all outputs used in the
design. Pin assignments are made in the same way as input pins.

Network Section
The optional Network Section (keyword NETIJORK:) is used only to define
state machine outputs that are not also state variables. (SMV automatically
creates the network statements required for each input and each state
variable during file conversion.)

Equations Section
The optional Equations Section (keyword EQUATIONS:) uses the same
standard Boolean operators available for Boolean equation design entry
(AND = * or 8; OR = + or #; NOT = /, " or 0. Equations can be used to
define outputs that are not state variables. Intermediate equations are also
supported and may be used to define a transition condition or a clock for
the state machine.

Machine Section
The Machine Section (keyword MACHINE:) specifies the state machine name.
Several state machines can be included in the same file.

Clock Subsection
The Clock Subsection (keyword CLOCK:) defines the clock for the state
machine. The clock may come directly from an input pin (listed in the
Inputs Section), or it can be defined as an internal node within the design.
Internal nodes are defined by the Equations Section, the Truth Table
Section, or other state machines.

Clear Subsection
The optional Clear Subsection (keyword CLEAR:) defines a master
asynchronous clear for the state machine. The Clear signal may come
directly from an input pin or from any internal node within the design.

I Altera Corporation

Page 403

I

I A+PLUS State Machine Design Entry

Application Brief 14A I

States Subsection
The States Subsection (keyword STATES:) defines all machine states. Each
state name is listed in a column. The state variables of the machine are
enclosed in square brackets following the state names. Each state must be
assigned a unique combination of state variables.

Transitions Subsection
The Transitions Subsection (no keyword) defines the transition for each
state. Each state name,. followed by a colon (:), is listed in this section. The
state name is followed by a conditional IF-THEN or CASE statement, or an
unconditional transition. To ensure that no ambiguity exists if more than
one condition is true, the first IF-THEN or CASE statement has precedence
over all others. For unconditional transitions, only the name of the next
state is listed. If none of the conditions is true, and no unconditional
transition is specified, the machine state remains unchanged.
For example, when the machine shown in Figure 1 is in state START, and
INPUTl and INPUT2 are both 8, the next state is START.

Outputs Subsection
The optional Outputs Subsection of the Transitions Subsection (keyword
OUTPUTS:) follows the transition(s) for a state. When this section is used,
all node names that follow the OUTPUTS: keyword are set high during the
current state. An IF-THEN statement may be included to make the node a
function of both the current state and current input conditions.

Truth Table Section
The optional Truth Table Section (keyword T _ TAB:) provides another
method for defining internal nodes. Both sides of the table consist of
internal nodes. See Figure 1.

End Statement
All State Machine Files must end with the END$ statement.

Defining
Outputs from
the Machine

I Page404

Outputs from the state machine can consist of any internal nodes within
the design. Internal nodes are inputs, state variables, or nodes defined in
the Equations Section, Outputs Subsection, and Truth Table Section. By
listing a state variable name in the Outputs Section (i.e., the Outputs
Section that follows the Inputs Section, not the Outputs Subsection of the
Transitions Subsection), the state variable becomes an output. All other
internal nodes must be routed through the Network Section, where the
type of output architecture must be specified (Le., registered or
combina torial).
Altera Corporation

I

State Machine Partitioning
for EP-Series EPLDs

I October 1990, ver. 3
Introduction

Application Brief

181

State machine partitioning offers the following advantages:

o
o
o

Complex state machines are reduced to two or more simple state
machines.
Complex designs can be fit into EPLDs.
The designer is able to use a systematic approach when working with
state machine designs.

This application brief describes a systematic method for partitioning large,
complex state machines into two or more smaller and simpler linked state
machines. Partitioning is useful for implementing a state machine in an
Erasable Programmable Logic Device (EPLD) when the size of logic
equations (number of product terms) for the next-state decoder exceeds
the EPLD macrocell resources.
When a state machine is partitioned, the resulting design often requires a
larger number of state registers, which may reduce efficiency when the
design is implemented in silicon. However, although the number of state
registers increases, the equations for each register become smaller.
Consequently, the partitioned design may be placed into fixed-widtharray logic devices such as EPLDs.
Partitioning does not always reduce the size of the equations, especially for
smaller, "tightly connected" machines. The results depend on how the
machine is di vided, the complexi ty of dependent transi tion equa tions, and
the sta te assignments. Sometimes the designer must try different di visions
and state assignments to find the best implementation. The best solution,
however, is to use the A+PLUS State Machine Converter, with its highlevel language syntax for easy design inpu t and modification. See Figure 1.
Figure 1. A+PLUS State Machine Converter
Schematic Capture Files
Boolean Equation Files

I Altera Corporation

Page4os1

I State Machine Partitioning for EP-Series EPLDs

Selecting the
Partition

Application Brief

181

Figure 2 shows part of a state diagram that describes a complex state
machine with states S1 to S6. Each state represents a unique combination
of the state variables V1 to VtI. For example, S3 could represent the
combination V1*I'V2*I'V3*V4.
Rgure 2. State Machine before Partitioning
E1
to other
states

E2

E3
from other
states

E4

from other states
to other states

E5

The states are connected by directional arrows, marked with the symbolic
labels E1 to E5, that show possible transitions to and from states. These
labels represent arbitrarily complex or simple equations, which are normally
functions of state machine inputs that allow the state machine to respond
to external events.

Partitioning
the State
Machine

I Page406

The state machine can be split so that states S1, S2, S3 (and all states on the
left that are not shown in the diagram) become a separate machine. E1 to
E5 represent all transitions between the two halves of the diagram.
A line should be drawn so that it crosses all transitions between the two
halves of the machine. For each half of the machine, the other half should
be replaced with a new state, called an IDLE state. This state allows one
half of the state machine to be idle while the other half is busy. When a
transition between the two halves occurs, the half of the machine that is
currently active goes into the idle state, while the currently idle half
becomes active.

A/tera Corporation

I

I Application Brief 18

I

State Machine Partitioning for EP-Serles EPLDs

Figure 3 shows the sample machine after it has been partitioned. States SA
and SB are the idle states for each half. All transitions between the two
halves are routed to the idle states. Transitions leaving the idle states
depend on the original transition equation and the current state of the
opposite half. Equations for the idle states are simply the logical inverse of
the transitions leaving each idle state. Rules for partitioning a state machine
are shown in Figure 4.
Figure 3. State Machine after Partitioning
State Machine A

State Machine B

E2 *00
/(E2 *S6)
E1

E3+ E4

E5

Sample
Design

IAltera Corporation

r

Figure 5 shows a state diagram for part of a design that converts a
manchester-encoded serial data stream into a standard UART-compatible
serial data stream, and extracts information from the data. The state
diagram clearly shows the method and usefulness of state machine
partitioning.

Page 407

I

I State Machine Partitioning for EP-Series EPLDs

Application Brief 18 I

Figure 4. Rules for State Machine Partitioning
1.

Atransition leading into an idle state has the
same equation as the corresponding transition
from the original machine.

E1

E1

2.

A transition leading out of an idle state has the
same equation as the co"esponding transition
from the original machine, logically ANDed with
the state of the other half of the machine.

E2

E2·56

3.

Multiple transitions with the same source and
destination states can be replaced by a single
transition with an equation that is the logical OR
of the two original equations. This equation
co"esponds to two IF-THEN statements that
have the same destination in the State Machine
File (SMF), making SMF modification easier
when a design is partitioned.

4.

Idle states have a Ioopback or hold transition,
with an equation that is the logical inverse of all
equations for transitions leaving that state,
logically ORed together. The hold transition
automatically occurs when an ELSE transition for
a given state does not exist.

IPage 408

/(E2·56)

A/lera Corporation

I

Application Brief 18

State Machine Partitioning for EP-5eries EPLDs

Figure 5. Manchester Synchronization Detection State Diagram

o

I Altera Corporation

10

Page4os1

I State Machine Partitioning for EP-Series EPLDs

Application Brief 18

I

The Manchester synchronization detection design was minimized to
5 equations that have from 8 to 14 product terms. Figures 6 and 7 show the
non-partitioned design before and after design processing. In its current
form, this design will not fit into an EP-series EPLD.
Rgure 6. Manchester Synchronization Detection State Machine File before
Processing (Part 1 of 2)
PART:
EP910J
IMPUTS: D, CLK
OUTPUTS: Yo no outputs Yo
MACHIME: hdlSS30_state_Maehine
CLOCK: elk
Yo

STATES:
SU
SA
SB

sc

SD
SF
SI
SM
SO
SP
SQ
SS
ST
SU
COM
SAA
SBB
SCC
SDD
SFF
SII
SOO
SE
SG
SH
SJ
SK
SL
DAT

[
[
[

[

IPage 410

a
a
a

[

1

[

1

[

a
a

[

1

[

[

a

a
1
1
1

a
a

a
a
a
a

1
1
1
1
1

1

1

]
]

1
B

[
[

a
a

[

1

[

1

[
[

a
a

[

1
1
1

[

[
[

[

a
a
a

a
a
a

a
a
a
a
a

B

B

1
1
1

a
a

a

1
1

1

1

a

1

[

a

a
a

[

1

1

1

[

1

[

IF
IF
IF
IF
IF
IF

IF
IF

IF
IF

IF
IF

1

a

a
a
a
a
a
a
a
a
a

1

1
1
1

[

]

1
1
1
1
1

a

1
1

1

]

1

1

]

]

]

a

[

]

1

1

B

]
]

1

1

a

]
]

1

[
[

a
a
a
a
a
a

1

[

Yo

SU:
SCC:
SS:
COM:
SF:
SG:
SI:
SK:
SA:
SDD:
SU:
SB:

state assignMents Yo
SU4 SU3 SUZ SUI SUO

1
1
1
1
1

a

transitions
THEM
THEM
THEM
THEM
THEM
THEM
THEM
THEM
THEM
THEM
THEM
THEM

]
]
]

1

]

a

]

1
1
1
1
1
1

]

1

1
1
1
1
1
1

]
]
]

]
]
]
]

]

]
]
]
]

Yo

SA
SDD
SC
COM
S"
SK
SO
S"
SB
SFF
S"
SC

Yo
Yo
Yo
Yo
Yo
Yo
Yo

Yo
Yo
Yo
Yo
Yo

ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE

Yo
Yo

Yo
Yo
Yo
Yo
Yo
Yo
Yo

Yo
Yo
Yo

SAA
SM
COM
COM
SI
SJ
SM
DAT
S"
SQ
COM
S"
Altera Corporation

I

Application Brief 18

State Machine Partitioning for EP-5eries EPLDs

I

Figure 6. Manchester Synchronization Detection State Machine File before
Processing (Part 2 of 2)
SE:

so:

SH:
SAA:
SBB:
SP:
OAT:
SO:
SOO:
SI't:
SJ:
SFF:
ST:
SC:
SJI:
SQ:
SL:

IF

IF
IF
IF

IF
IF

IF
IF
IF
IF
IF

IF
IF
IF

IF
IF
IF

THEI't
THEI't
THEI't
THEI't
THEI't
THEI't
THEI't
THEI't
THEI't
THEI't
THEI't
THEI't
THEI't
THEI't
THEI't
THEI't
THEI't

S'"
SB
SX
S'"
S'"
SS
OAT
SG
SG
SP
OAT
SJI
COM
SE
SE
SU
OAT

K
K
K
K
K
K
K
K
K

"

K

"
Y.

"
Y.
Y.
Y.

ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE

K
K
K
K
K
K
K
K
K

"

K

"
"

Y.

Y.
Y.
Y.

SH
SQ
SL
SBB
sec
ST
OAT
SF
SBB
S'"
S'"
S'"
S'"
SD
SOO
ST
sec

EI'tD9

Figure 7. Minimized Logic Equation File (Part 1 of 2)
OPTIOI'tS:
PART:
II'tPUTS:
OUTPUTS:

TURBO = Ol't, SECURITY = OFF
EP91BJ
0, eLX
SU4, SU3, SUZ, SUI. SUB

I'tET"'ORX:
II'tP(elk)
elk
D = II'tP(D)
SU4
I'tORF(SU4.d,
SU3
I'tOTF(SU3.t,
SUZ
1't0TF---C>: D4

ot--i>---C::>;

IlIR

ot--f>---c:>:

ACT

ot--i>---C:>:

ERR

Synchronous Counter The bar code decoder uses the bar code header's
leading single-width black region to measure the width of a O. When the
light pen passes over th.e first black region, the synchronous counter begins
counting, and stops only when the light pen has completed reading the
first black region (Le., when it reads the beginning of the next white
region). The count value thus reflects the amount of time required to read
the width of a space or 0 bar. It takes twice the count value to read a 1 bar.

I Altera Corporation

Page419

I

!'r:W
1
~

1

EP1810 EPLD as a Bar Code Decoder

Application Brief

271

The count value samples the bar code data. Since the light pen's scanning
speed will vary slightly, the count value is only an approximate measure
of the width. Therefore, data should be sampled in the center of the black
and white regions rather than on the edges. The first sampling occurs in
the middle of the space following the leading black region, when the
synchronous counter reaches half of its synchronous value. Sampling is
achieved by bit-shifting the latched synchronous counter with a pair of
74157 multiplexers. The counter is reset, and the next sampling occurs
when it reaches the full synchronous value.
The values of data sam pIes correspond to the bar-encoded data. If a blackwhite region is read, the light pen has passed over a single-width black
region followed by a single-width white region, indicating a o. If a blackblack-white region is read, the light pen has passed over two adjacent
black regions followed by a white region, indicating a 1. If any other
combinations starting with black are read, or if two adjacent white regions
are read, the code is invalid.
The synchronous counter is implemented with macrofunctions from the
A+PLUS TIL MacroFunction Library (one 8COUtlT, two 74157s, and one
74273). The associated terminal-count circuitry includes basic gated logic
and an tlOCF primitive.
Byte Counter The byte counter counts the number of bits shifted in.
When a complete byte has been read, the byte counter signals the
microprocessor. The byte counter is implemented with a Gray-code
sequence, in which only one bit changes between any two count transitions,
ensuring that the outputs are glitch-free and preventing spurious outputs
from inadvertently interrupting the microprocessor. The byte counter has
an open-collector output to the microprocessor (ItiTEI) that is created by
connecting the input of a tri-state driver to ground and selectively enabling
the tri-state (TCtlT). Figure 3 shows the byte counter implemented in a
State Machine File (SMF).
Shift Register Input data is stored in a 74164 shift register. The shift
register clock is fed from the state controller state machine to ensure that
data is latched at the appropriate time. The 74164 outputs must be
buffered and connected to the microprocessor bus. The shift register is
implemented by a 74164 macrofunction and COtiF primitives.
Status Outputs Special outputs allow external devices to determine the
status of the bar code decoder. The status information consists of the open
collector COttF output and the SOttF and HOttF status flags.
A direction signal, DIH, is provided to compensate for backwards scanning
of a bar code. If inactive, the DIH signal indicates that the tail was read
before the header. In this instance, all data and checksum words are

IPage 420

Altera Corporation

I~

I Application Brief 27

EP1810 EPLD as

a BarCode Decoder I

Rgure 3. Byte Counter State Machine File
This eight-stage Gray-code counter uses the high-le¥eI State Machine File format
~ GRRY3
3 lIT GRAY counTER
PART: EPI81aJ
IHPUTS:
OUTPUTS:
nETwoRX:
EQUATIOns:

~

"ACHIHE: GRAY3
CLOCX: GCLX
CLEAR: synCCLR
STATES: [ G2 Cl ca ]
sa
[ a a a]
51

[a

all

S2
S3
S4
S5
S6

[B

1

1 1

[ B 1 B]
[liB ]
[1 1 1 1

[1
[1

S7

sa:
SI:
S2:
S3:
S4:
S5:

SI
S2
S3
S4
S5
S6

S6:
S7:

S7

~
~

all
a a 1

STATES "AXE unconDITIonAL
TRAnSITIon TO nEXT STRTE

~
~

sa

EHD$

reversed, and the microprocessor must make the compensating
transformations. The ability to read bar codes backwards and forwards
also permits them to be read upside down or from right to left.
The ACT signal indicates that a bar code is being scanned in. This signal is
useful for a variety of error handling or initialization tasks. For example, a
microprocessor may poll this signal and enter special routines dedicated to
bar code reading.
The ERR signal indicates that an illegal sequence of white and black
regions was encountered during the decoding process; perhaps the bar
code was unreadable or the scan rate was not uniform enough. The
microprocessor can use ERR to dump illegal reads without first computing
and comparing a checksum against the checksum byte passed to the
microprocessor by the bar code.
Controller State Machine The bar code decoder must determine if a
header is valid, and then convert the white and black bar code regions to
machine-readable data. It also coordinates activities of the synchronous
counter, shift register, byte counter, and status generation circuitry. This
;1

A/tera Corporation

Page421

I

I EP181D EPLD BS a Bar Code Decoder

Application Brlel27

I

coordination is best achieved with a centralized state controller state
machine, shown in Figure 4. (Figure 5 shows the corresponding SMF.)

Rgur.4. Bar Code Controller State Diagram
Bar code decoding is coordinated by the state controller. This diagram shows the behavior of the
BAReTL portion of the state controller.
PONER-UP

AN-ZERO

IPage 422

Altera Corporation

I.

I Application Brief 27

I

EP1810 EPLD as a Bar Code Decoder

The following control states are used:
I DLE The machine idles until the light pen reads a black region; then the
sync counter is started.

SYNC The synchronous counter counts while in this state. The machine
stays in this state until the light pen reads the first white region. The count
corresponds to the width of the first black bar.
LATCH The machine latches the count value into a holding register. For
the next count cycle, the control line BSEL shifts the count value to the
right by one bit. Subsequently, the synchronous count expires on every
modulus of the latched count, and triggers reading of the input stream.
HDR 1, HDR 2, FUD, REV, ERR The machine begins reading the rest of the
header bits. Two sequences are possible, depending on whether a 00
(forward) sequence or a 01 (backward) sequence is read. Any improper
reads cause the state machine to go to the ERR state. Direction status is
latched, depending on state FUD or REV. Once the header information is
read, data and checksum bytes are read into the shift register.
ACTl, ACT2, ACT3, ACT4 These four states are the active reading states.
The ACTl-ACT31oop indicates that a 0 was read. The ACTI-ACT2-ACT4
loop corresponds to reading of a 1. Reading stops when a long white space
is read, indicating the end of the bar code.
The controller is implemented in a State Machine File, shown in Figure 5.

Implementing
the Bar Code
Decoder

I Altera Corporation

Figure 2 shows a LogiCaps schematic of the bar code decoder. The
synchronous counter is im plemented by four macrofunctions (one BCOUNT,
two 74157s, and one 74273). Terminal-count circuitry consists of logic
and an NOCF primitive. The byte counter, GRAY3, is implemented in the
State Machine File GRAY3.SMF (Figure 3). The shift register is implemented
by combining a 74164 macrofundion with eight CONF primitives. The
status information module consists of a CONF configured as an open
collector output, and status flags implemented by SONF and RORF
primitives. The state machine controller is implemented in the State Machine
File BARCTL.SMF (Figure 5).

Page 423

I

IEP1810 EPLD as a Bar Code Decoder

Application Brief 27

Rgure 5. Bar Code Controller State Machine Rle
~ Jar Cod. Controller ~
PART: IP18l8J
INPUTS:
OUTPUTS:
"ITIoIORK:
IQUATIOHS:
DIRS '"' FIoID.
RCTI • !IDLE.
SY"CC1R = IDll • /1".
SY"CI" = IDLE.
IC1K • ACT2 + ACT3.
ISll '"' lATCH.

IIRR '"' IDlE.
IRRD. IRR • !ID1E.
SY"CUP • SYNC.
SY"C1RTCH = lRTCH.
TI"I '"' ACT2 + ACT3 + ACT4.

tlACHI"I: IRRCll
ClOCK: C1K
STRTES: [ Q3 Q2 Ql Q8 l
IDlE [ 8 8 8 8 l
SYNC [ 1 1 8 1 l
lATCH [ 1 1 I I I
HDRI [ 8 1 I I I
HDR2 [ 1 8 8 8 l
HDR3 [ 1 8 8 1 l
FWD
[ 1 8 1 8 l
REUI [ 8 1 1 8 l
REU2 [ 8 1 8 1 l
ACTI [ 8 8 I I I
RCT2 [ 8 1 8 8 l
ACT3 [ 8 8 8 1 l
RCT4 [ 8 8 1 8 l
ERR
[ 1 8 1 1 l
IDlE:
IF IN THE" SYNC
SYNC:
IF /1" THE" lATCH
lATCH:
HDRl
HDR1:
IF /IN • ZERO THE" HDR2
IF I". ZERO THE" ERR
HDR2:
IF I". ZERO THE" HDR3
IF /IN • ZERO THE" ERR
HDR3:
IF IN • ZERO THEN REUI
IF /IN • ZERO THE" FWD
FWD:
IF ZERO THEN RCTI
REU1:
IF IN • ZERO THEN ERR
IF /1" • ZERO THEN RIU2

ACT1:

IF IN • ZERO THEN RCTl
IF /IN • ZERO THEN IRR
IF IN • ZERO THEN RCT2
IF /IN • ZERO THEN RCT3

ACT2:
ACT3:
ACT4:

IF IN • ZERO THEN ERR
IF /IN • ZERO THEN RCT4
IF IN • ZERO THEN RCTI
IF /IN • ZERO THEN IDlE
IF I" • ZERO THE" ACTl
IF /IN • ZERO THE" IDlE

ERR:
IF ZERO THEN RCTl
END$

IPage 424

Altera Corporation

I

I Application Brief 27
Design
Processing

EP1810 EPLD as

a Bar Code Decoder

I

Three separate files in two different formats are used for design input.
LogiCaps generates the BAR.ADF file. BARCTL.SMF and GRAY3.SMF are
state machine files. The Altera Design Processor (ADP) of the A+PLUS
software processes the designs and links them at the same time, as long as
the designer enters all three filenames when the ADP issues the FILE NAME:
prompt.
The ADP then creates a JEDEC output file, BAR.JE D, for EPLD
programming. The utilization report generated by the ADP indicates that
the following resources are used: 41 of the 48 macrocells, 2 of the 17 inputs,
and only 34 percent of the available logic.

Design
Verification

The A+PLUS Functional Simulator (FSIM) simulates the design to ensure
proper operation. In this example, a serial input stream corresponding to a
valid bit stream is read by the design. It properly sequences through the
states, latches the data, and interrupts a processor. The simulation data is
shown in Figure 6.
Figure 6. Simulation Data
Simulation is driven with data input that emulates this sequence. Design behavior is monitored in
the Functional Simulator.
Encoded Bit

Simulation
Cycle

0

0

0

0

0

0

II1I1I1I1I1I

........ . . . . . . . . .
4 5 610 12 16 1820 22 262830 32 36 38 40 42 46 48 50 52 56 58 60

Store Store Store Store Store
"1"
"0"
"1"
"0"
"1"

•

Active
Flag
Set

IAltera Corporation

0

•

DIR
Flag
Set

Store
"0"

Store Store Store
"1"
"0"
"1"

.

Store
"0"

Interupt
to
Prooessor

Page 425

I

I EP1810 EPLD as a Bar Code Decoder

Application Brief

271

The controller state machine is verified by comparing the Q8 to Q3 outputs,
and the state table values in Figure 5. The actual simulation waveforms are
shown in Figure 7.

Figure 7. A+PLUS Functional Simulator Waveforms

Z
E

C
L
E

C
L
It

1
2
3

1!
_.!
-

4

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

Q
3

Q
1

Q
0

I
N
T
0

R
0

0
2

0
1

0
0

-

: -'
!

-_.

-_.
:: -'
_.-

! -'

!

- - -

! -'

i

I

._4 ,_'

-:::

!-:

!-:

!-

i

-:

!_,
.,-'

~:~

-:::

264
265
266
267
268

!-

,-'

"'-,

-, ,-' "'-, ,-' "'-, ,-'

--,

-:

!,_:
--,

271

~~~

::::

~~~

-:::

--,

,_4

z
z

274 !275
-:
276 !.271
-:

z

!_,

-

279 .,-'
280 "'-,

~H ~=;

IPage 426

0
3

: -'

254
255
256
257
258
259
260
261

284

0
5

! -'

~~~

278

0
7

.

~:::=:
250 --,
251

Q
2

--,

'I-'

-, r' r(

z
z
z

z
z

z
z

z

-

ii

Altera Corporation

I

Timing Simulation
for EP-Series EPLDs

I October 1990, ver. 4

Application Brief 541

Introduction

EPLDs integrate complex functions into single-chip solutions. After a
design is functionally correct, timing analysis should be completed to
ensure AC parameter compatibility. This application brief discusses the
timing delays in Altera EP-series EPLDs. It models the internal delay paths
inherent in every EPLD, shows their relationships to AC specifications
(shown in the EPLD data sheets), and presents worst-case values for these
parameters. Designers can model and simulate their own logic designs
once they understand how the A+PLUS software actually implements
logic designs in EPLDs.

Basic EPLD
Arch itectu re

To accurately model timing characteristics, a designer must understand
how logiC is im plemented in the EPLD. Most designs targeted for EP-series
EPLDs contain basic gates and TIL macrofunctions, which are emulated
by the EPLD's general macrocell structure. This macrocell structure consists
of an array of logiC in a programmable-AND I fixed-OR configuration,
with a programmable inverter (XOR), optional flip-flop, and feedback (see
Figure 1).

Figure 1. EP-Series EPLD Macrocell
Dedicated Inputs

Feedback Signals

~~~~~~~~~~~~~~~~~~~~
~

~

~ ~ ~

~~

,,> ,,>

~

~

~)

~

jI;

~

~

~

~

~

j\j)j\j

Fixed
OR
~

=r
=5=

}-

Programmable
AND-gates

I A/tera Corporation

Programmable
Inverter
XOR

.

~Reg.t.'

@ ItWO~'m
'Ii

Control alt

GND

1

F_I
MUX

Feedback
to other
macrocells

Page 427

I

I Timing Simulation for EP-5eries EPLDs

I

Application Brief 54

When modelling EPLD timing, the concept of "gate delay" is not a useful
measure. The EPLD logic array contains n-inpu t AND ga tes called product
terms (n is the number of connections). Depending on the logic
implemented, a single product term may represent one to several gate
equivalents.

AND/OR/XOR
Structure

The AND portion of the EPLD logic array consists of a group of AND
gates, each of which has a very large number of possible inputs that are
selected by EPROM bits. The EPROM bits serve as electrical switches. An
erased bit passes the input into the AND gate (switch on), while a
programmed bit cuts it off (switch off). All bits are initially erased.
The number of possible inputs to an AND gate varies from 36 (EP320) to 88
(EP1810). In EP300-series, EP600-series, and EP900-series EPLDs, every
dedicated input, its inversion, every macrocell feedback, and its inversion
are possible inputs to the AND gate. In EP1800-series EPLDs, which have
local and global busing, not every macrocell feedback is available at every
AND gate. (Restricting the number of feedbacks preserves the speed
characteristics of the device.) A significant portion of the component delay
is in the propagation through the array (described later in more detail).
The AND gates feed a fixed 8-input OR function, so named because the
AND functions are hard-wired into the OR gates, and cannot be
redistributed if they are left unused.
The OR gate feeds a programmable inverter (XOR), which is controlled by
a dedicated EPROM bit.

Designing
Explicitly for
EPLD
Architecture

The ANDjORjXOR structure can implement general logic structures in
either sum-of-products or product-of-sums form. However, since Altera's
A+PLUS software automatically translates the input design file into a
minimized Boolean form, designers are not necessarily aware of the
intermediate Boolean form. Nevertheless, it is still important for designers
to understand how Boolean logic is implemented in the array structure.
Figure 2 shows a single network of SSI functions and its corresponding
Boolean equation and. Karnaugh map. Figure 3 shows how a sum-ofproducts equation is formed by blocking adjacent product terms, and
ORing them together by programming appropriate connections. (If there
are more than 8 product terms, it is not possible to implement the logic in
a single AND JOR array of the type shown.) The product terms P4 through
P8 do not interfere because they are programmed out (a low logic level
results because both the true and complement of every signal are ANDed).
The archi tecture also supports product-of-sums lOgic-the ANDing of OR
functions-through De Morgan's inversion. Product-of-sums logic is
possible because both the true and complement forms of the inputs are

IPage 428

A/tera Corporation

I

Application Brief 54

Timing Simulation for EP-Series EPLDs

Figure 2. Sample Logic

12 11

11---1:..:~

12
13
14 ---&... . . .- - r - -

OUT = (11 * 12 * 13 * 14) + (112 */14) + (/12 */14) * (/12 ./13)

Figure 3. Sum-of-Products Logic

14 13
00
01
11
10

01

11

10

0

0

-.-0

0

0

0

(0

0

0

0

-~
1

~
0

P3

(1 1"'\

11

01

11

10

00

1

1

0

0

01

1

1

0

0

11

0

0

1

0

10

1

1

0

0

12 13 14

= /12 */14

P1 = 11 * 12 • 13 •
P4 .. P8= 0
P2

00

14 13

OUT

12 11
00

I

14
When transistor is on.
inversion is disabled

= /12 */13

GND

available to the AND array. Figure 4 shows how product terms are formed,
by grouping the zeros and setting the invert bit. In this case, there are more
product terms than in the sum-of-products form, but sometimes
De Morgan's inversion dramatically reduces their number.
Figure 4. De Morgan's Inversion
12 11
00

01

11

11

12

13 14

10

14 13
00
01
11
10

When transistor is off.
inversion is enabled
P1 = 14 • 13 */12

GND

I A/tera Corporation

Page 429

I

I Timing Simulation for EP-5erles EPLDs
EPLD Delay
Parameters

Application Brief 54

I

The propagation delay through the logic array (tLAD) is modelled as a
constant: A+PLUS logic minimization and the array structure of macrocells
make it unnecessary to do otherwise. Other elements in the timing model
are akin to those found in conventional logic: input and output delay
parameters (tIN, t lO, taD)' register parameters (tsu, t H, t CLR , tICS! tIC)' and
internal connection parameters (tFD ). Figure 5 shows the timing model for
EP-series EPLDs.
Input pad and buffer delay: the time required for the dedicated
input pin to drive the true and complement data input signals
into the AND array.
I/O input pad delay: the delay added to tIN for I/O pins that are
used as inputs.
taD

Output buffer and pad delay. In registered applications, taD is the
clock-to-output delay of the flip-flop. In combinatorial
applications, it is the delay from the output of the array to the
output pin.

txz

Active output to tri-state delay: the time between a high-to-Iow
transition on the enable input of the tri-state buffer to assertion of
a high-impedance value at an output pin.

tzx

Tri-state to active output delay: the time between a low-to-high
transition on the enable input of the tri-state buffer to assertion of
a high or low logic level at an output pin.
Logic array delay: the delay incurred as an input or feedback
travels through the AND/OR/XOR structure.

tsu

Register setup time: the internal setup time of the register inside a
macrocell, measured from the register data input until the register
clock.
Register hold time: the internal hold time of the register inside a
macrocell, measured from the register clock to the register data
input.

tCLR

Asynchronous register clear time: the time required for a low
signal to appear at the output of a register after the transition at
the input of the logic array.
System clock delay: the total delay incurred between the output
of the input pad and the clock input of the registers for dedicated
clock pins.

IPage 430

A/tera Corporation

I Application Brief 54

Timing Simulation for EP-Series EPLDs

I

Clock delay: the total delay incurred between the output of an
input pad or I/O pad and the clock input of a register, including
the time required to pass through the logic array.
Feedback delay. In registered applications, tFD is the delay from
the output of the register to the input of the logic array. In
combinatorial applications, it is the delay from the combinatorial
feedback to the input of the logic array.
Figure 5. EPLD Timing Model
System Clock Delay

tiCS

Register

AC Timing
Characteristics

The data sheet for each EP-series EPLD gives timing parameters that
characterize the AC operating specifications. These parameters are
measured worst-case values, derived from extensive performance
measurements and guaranteed by 100% testing. These AC characteristics
include tp01' tpo21 tpzx, tpxz, tCLR' tsu, tH , t C01' tCNT! t ASU' t AH, t AC01' and
tACNT ' Each parameter can be represented by a combination of the internal
delay elements described earlier in this application brief (see Figure 6).
tpOl

Propagation delay: the dedicated input to non-registered output
delay. tpOl is the time required for any dedicated input to
propagate through the combinatorial logic in a macrocell and
appear at the external EPLD output pin. This delay is the sum of
the input delay (tIN), array delay (tLAD), and output delay (taD)'
Propagation delay: the I/O pin input to non-registered output
delay. tpD2 is the time required for any I/O pin input to propagate
through the combinatorial logic in a macrocell and appear at the
external EPLD output pin. This delay is the sum of the I/O delay
(t IO)' input delay (tIN)' array delay (t LAD), and output delay (taD)'

tpzx

Altera Corporation

Tri-state to active output delay: the time required for an input
transition to change an external output from a tri-state (high
impedance) logic level to a valid high or low logic level. This
delay is the sum of the input delay (tIN)' array delay (t LAD ), and the
time to disable the tri-state buffer (t zx ).
Page431

I

Application 8rlel54

Timing Simulation lor EP-Serles EPLDs

I

Figure 6. EPLD Timing Equations
I

INPUT

r....

JCON~·)

~L_C_o_~_L~...:;:..·~_O_rial_...J~OUTPUT

RORF

too

,.....C...... .........t""'UT

I

...t FO•.•

I

b~OUTPUT
..........,

~

tLAD

_I_

tzx or txz

•I
.•t SUI
a·

tCNT -tFD+ tLAD+ tsu
tACNT .. tFD +tLAD+tsu

Corrbinatorial
L _ _L_o.::.gi_c_ _ •

INPUT

t LAD

_I
INPUT

tpzx .tIN+tLAO +tzx
tpxz .tIN+tLAO+txz

INPUT

INPUT

..

I.. tiN I

tCLR

_I_

too _I

l·

tlN

-I-

tLAO

INPUT

INPUT
INPUT

r····· ........... ....
~~~~

~

INPUT

~

r~UT

....... ....................
tAC01 =tIN+t'C+tOD

INPUT

INPUT

~1~.~___t~~~s~__-+,I~,~

__t~o~O~_~,1

tC01 =tlN+tICS+tOD

Page 432

A/tera Corporation

I

IApplication Brief 54

I

Timing Simulation for EP-Series EPLDs

Active output to tri-state delay: the time required for an input
transition to change an external output from a valid high or low
logic level to a tri-state (high-impedance) logiC level. This delay is
the sum of the input delay (tIN)' array delay (tLAo), and the time to
enable the tri-state buffer (txz).
Time to clear register delay: the time required for a low signal to
appear at the external output, measured from the input transition.
This delay is the sum of the input delay (tIN), register clear delay
(t CLR )' and the output delay (too).

tsu

Setup time on the register: the time data must be present at the
register before the system clock. This value is the difference
between the sum of input delay (tIN), array delay (tLAO), and
internal register setup time (tsu), and the sum of the input delay
(tIN) and the system clock delay (tICS)'
Hold time for the register: the time the data must be valid after
the system clock. This value is the difference between the sum of
the internal input delay (tIN), the system clock (tICS)' and the
internal register hold time (t H), and the sum of the input delay
(tIN) and logic array delay (tLAO)'

tcot

System clock to output delay: the time required to obtain a valid
output after the system clock is asserted on an input pin. This
delay is the sum of the input delay (tIN), the system clock delay
(tICS)' and the output delay (too)'

tCNT

System clocked counter period: the minimum period maintained
by a counter. This delay is the sum of the feedback delay (t FO)' the
logic array delay (t LAO)' and the internal register setup time (tsu).
Asynchronous setup time on the register: the time data must be
present at the register before an asynchronous clock. This value is
the difference between the sum of the input delay (tIN), array
delay (t LAO)' and the register setup time (t su), and the sum of the
input delay (tIN) and the clock delay (tIC)'

tAH

Altera Corporation

Asynchronous hold time for the register: the time the data must
be present after an asynchronous clock. This value is the difference
between the sum of the input delay (tIN)' the clock delay (tIe>, and
the hold time (tH ), and the sum of the input delay (tIN) and logic
array delay (tLAO)'

Page 433

I

1m
I

I Timing Simulation for EP-Series EPLDs

Application Brief 54

I

t AC01

Asynchronous clock to output delay: the time required to obtain
a valid output after a clock is asserted on a dedicated clock pin.
This delay is the sum of the input delay (tIN), the clock delay (tIC),
and the output delay (t OD )'

t ACNT

Asynchronous clocked counter period: the minimum period
maintained by a counter when it is asynchronously clocked. This
delay is the sum of the feedback delay (t FD), the logic array delay
(tLAD), and the register setup time (t su ).

Tables 1 through 4 show the internal delay parameters for all EP-series
EPLDs. It is also possible to calcula te the internal timing model parameters
by using the timing information in individual EPLD data sheets. In some
cases, the modeled result differs slightly from the data sheet specification,
because different guardbands are used to ensure compliance with the
specification when the EPLDs are tested during manufacturing. The model
does not account for the extended guardbanding of some data sheet
specifications. Although data sheets show maximum and minimum values,
the model results are considered to be "typical worst-case" performance.
Table 1. EP3OD-Series Timing Parameters
Parameter
(ns)

EP330-12

EP330-15

EP320-1

EP320-2

EP320

tIN

3

4

4

5

7

tlO

1

1

1

1

1

tLAD

6

7

20

22

26

too

3

4

5

7

11

tzx

3

4

6

8

12

txz

3

4

6

8

12

tsu

3

4

8

10

14

tH

0

0

10

10

10

tiCS

2

3

7

7

tFD

1

1

8

8

tiC
-~~=-;::: f-.

7

10

tCLR

I Page434

Altera Corporation

I

IApplication Brief 54

Timing Simulation for EP-Series EPLDs

I

Table 2. EP600-Series Timing Parameters
Parameter

EP640-12

EP640-15

EP630-15

EP630-20

EP610-25

EP61 0-30

EP61 0-35

I

(n5)

tiN

3

4

4

5

5

6

7

0

2

2

2

2

2

t 10

0

I

tLAD

4

6

6

9

14

17

19

I

too

5

5

5

6

6

7

9

tzx

5

5

5

6

6

7

9

txz

5

5

5

6

6

7

9

tsu

5

6

6

8

8

8

8

tH

5

6

6

8

12

12

12

tic

4

6

6

9

14

17

19

tiCS

1

2

2

3

4

4

4

tFD

1

1

1

1

3

5

8

t CLR

4

6

6

9

16

17

21

I

Table 3. EP900-Series Timing Parameters
Parameter

EP91 0·30

EP91 0·35

EP91 0·40

EP91 0·45

(n5)

IAltera Corporation

tIN

7

8

8

8

tlO

3

3

3

3

tLAD

16

19

22

25

tOD

7

9

10

12

tzx

7

9

10

12

txz

7

9

10

12

tsu

10

10

10

12

tH

15

15

15

17

tiC

16

19

22

24

tiCS

4

5

6

6

tFD

4

6

8

10

tCLR

19

22

25

28

Page 435

I

1

Timing Simulation for EP-5eries EPLDs

Application Brief

541

Table 4. EP1800-Series Timing Parameters
EP1830-20

EP1830-25

EP1830-30

EP1810-35

EP1810-40

EP1810-45

tiN

5

7

7

7

7

7

t 10

2

3

4

5

5

5

tLAD

9

12

15

19

23

27

too

6

6

8

9

10

11

tzx

6

6

8

9

10

11

txz

6

6

8

9

10

11

tsu

8

10

12

10

11

11

tH

8

10

12

15

17

18

tiC

9

12

15

19

23

27

tiCS

4

5

7

4

6

8

tFD

3

3

3

6

6

7

tCLR

9

12

15

24

28

32

Parameter

(n8)

Timing
Examples

In the following pages, four timing examples are presented to show how
internal delay paths are calculated.

Example 1: Simple Combinatorial Circuit
The sim pIe circui t shown in Figure 7 illustra tes circui t parti tioning into the
EPLD internal delay paths. It is a combinatorial design that uses no clock
or feedback. The timing restrictions are dependent only on the input,
array, and output delay elements.
The circuit consists of three inputs, gated logic, and one output that
together create three delay paths: input delay, array delay, and output
delay. All gated logic is incorporated into the AND/OR array. The
maximum time allowed for any input to propagate through the entire
circuit (from input pin to output pin) is the propagation delay t pD1 . The
worst-case tpDl is given in each EPLD data sheet. This propagation delay
always applies when combinatorial output logic is used:
tLOGIC

=tIN + tLAD + taD =tpDl

Example 2: Combinatorial Feedback
Figure 8 shows a simple design that contains combinatorial feedback, i.e., a
setofcross-coupledNORgates.Italsoshowshowthedesignisimplemented
with "flattened" primitives and partitioned into appropriate input, output,
1

Page436

Altera Corporation

I

I Application Brief 54

Timing Simulation for EP-Serles EPLDs

I

Rgure 7. Simple Combinatorial Circuit
tLOGIC

IBC=~------~~~L-J

INP

r····· . ···CON·F···1
:.......................1 LOGIC

Cc=~~t----------i....-...J

INP

array and feedback delay paths. The propagation delay is the maximum
combinatorial delay from input to output (path 1). If the output of the latch
is a logic 0 (Q low), and a logic 1 is applied to the Set input (8 high), the output
of the latch will go to a logic 1 (Q high) within one propagation delay. The
same principle is true if the latch is reset (R high, 8 low).
Path 2 is the hold time of the latch. To avoid any unwanted output glitches,
the asynchronous setup time of the latch must be observed. The pulse
width of either Reset (R) or Set (8) inputs must be long enough to ensure
that the feedback signal can return from the output primitive and stabilize

Figure 8. Cross-Coupled NOR Gates
LogiCaps Schematic

Primitive Implementation

NOR2

R - - - - - ' [ " - - . . . . ) 0 -___-

LATCH

>-4~=>:

LATCH

S ---1--'"

Delay Paths
LATCH

R
S

Path 1 =t IN + t LAD + t OD
Path 2 =tlO+ tIN + tLAD

I A/tara Corporation

Page 437 \

I Timing Simulation for EP-5erles EPLDs

Application Brief 54

I

the latch. The input pulse width must be greater than the time required for
the feedback signal to return to the AND array and propagate through the
gated logic. Otherwise, a high-to-Iow or low-to-high glitch may occur at
the output. Thus, input pulse width is greater than the sum of t lo, tIN, and
tLAD' In this case, (t IO + tIN) is the feedback delay because the COIF
feedback comes from the I/O pin.

Example 3: Synchronous Design
Figure 9 shows a synchronous design that uses three inputs, one clock
(common to both D flip-flops), gated logic, and one active-low output. The
flattened A+PLUS primitive implementation is partitioned to highlight the
delay paths. The design contains five inherent delays-dock delay, input
delay, array delay, feedback delay, and output delay-as well as setup and
hold time requirements on each of the registers. All gated logic, including
the inverter, is incorporated into the AND/OR array.
Path 1, which refers to the output register in the flattened schematic
(second D flip-flop), is the dock-to-outputdelay. Assuming the data satisfies
the setup time for the register, a rising-edge clock at the clock of the flipflop causes data residing on the D input to appear at the output pin, after
passing through the tri-state output buffer. The clock at the input pin is
delayed into the register dock input bya specific time period (tIN + tICS)' This
additional delay must be incorporated into the total clock-to-output delay.
Thus, the maximum delay is the sum of the input delay (tIN), the clock
delay (tICS)' and the output delay (t OD )'
The setup time is the time required for the input data to stabilize before the
triggering edge of the clock. The setup time for the EPLD internal flip-flops
has been modeled from the input, array, and clock delay paths, as well as
the actual register setup time. Path 2 specifies the setup time requirement.
The requirement for stable data at the flip-flop-the sum of the input, logic
array, and setup time-is the first term in the Path 2 equation. The clock is
delayed from the input pin to the clock input of the flip-flop by the sum of
the input delay and the clock delay. The setup time for the EPLD is the
difference between these quantities (as shown in the Path 2 equation). As
long as the setup time is obeyed at the external inputs, the circuit will
function properly.
The minimum internal counter period, tCNT' is governed by the internal
feedback path. tCNT (shown in Path 3) is the time required for a signal to
pass from the upper register to the lower register, and determines the
minimum internal clock period limit for the circuit. Once data is triggered
into the top register, the signal passes through a feedback delay (tFD) and
array delay (t LAD) before reaching the bottom register. It must then meet
the setup time of the register (t su). The sum of these delays represents the
minimum practical internal clock period. Therefore, circuits that depend

I Page438

Altera Corporation

I

I Application Brief 54

Timing Simulation for EP-Serles EPLDs !

Figure 9. Synchronous Design
LoglCaps Schematic
CLOCKc=>---------~------------------~

p

X ~>----ir--""""I
YC=>----i

01 XOR

NOT

P
0

~--~D

02

C
zc=>------------------~

Primitive Implementation

Delay Paths
CLOCK

x
Q2

Y

z
Path 1 =tIN+tICS+tOD
Path 2

= (t IN+ tLAD+ tsu) -

(tIN+ tiCS)

Path 3 =tFD+ tLAD + tsu

I Altera Corporation

page439!

I Timing Simulation for EP-5erles EPLDs

Application 8rlel54

I

only on internal signals can operate at the minimum clock period specified
by the teNT parameter.
Some circuit functions are dependent on both external and internal signals.
In this case, the maximum clock frequency is dependent on the input
delay, array delay, output delay, feedback delay, and clock delay.

Example 4: Asynchronous Clock
Figure 10 illustrates the asynchronous Clock feature in EP-series EPLDs.
This design is similar to Example 3 (Figure 9), with the exception that the
asynchronous clock option is implemented with the (:LJCB primitive.
Therefore, the tIC parameter is substituted for the corresponding tICS
parameter in Exam pIe 3. The timing pa ths reflect the change: the clock-tooutput delay (Path 1) and the setup time parameters (Path 2) are both
affected, but the internal feedback path (Path 3) is not.

I Page440

Altera Corporation

I

I Application Brief 54

Timing Simulation for EP-Serles EPLDs I

Figure 10. Asynchronous Clock Design
LogiCaps Schematic
CLOCK~~--------~------------

______~

xc=>-~r-""",

y

p

C::>-~L_.~

.»---~

C

D

0 t---c=::> 02

C

zc=>-----------------~

Primitive Implementation

CLOCK c..:>-----I >------------,

Delay Paths
CLOCK

x
Q2
y

z
Path 1 =tIN+ tiC + too
Path 2 = (t IN + t LAD + t su) - ( tiN + tie)
Path 3 =tFD+ tLAD + tsu

I Altera Corporation

Page441

I

Timing Simulation for EP-5erle. EPLDs

Application Brief

541

Macrofunction
Timing

A+PLUS software automatically flattens macrofunctions into low-level
EPLD architectural elements (primitives), which can be analyzed with the
timing model and techniques described in this application brief. Worstcase macrofunction timing can be obtained before the design is flattened
by applying the timing model to the macrofunction schematics given in the
ITLMacroFunctions manual.

Conclusion

To understand timing relationships in EP-series EPLDs, the internal delay
paths must be broken into meaningful microparameters that model portions
of the EPLD architecture. Accurate timing delay information can be obtained
by adding appropriate combinations of these microparameters (given in
Tables 1 through 4). Architectural information the parameters that apply
and how they are implemented is provided in individual EPLD data
sheets. The combination of these elements and the techniques described
herein allow any timing path within an EPLD to be estimated accurately.

Page 442

Altera Corporation I

Estimating a Design Fit
for EP-Series EPLDs
Application Brief 60 I

October 1990, ver. 2

Introduction

This application brief provides an estimation formula and worksheet to
determine which EP-series EPLD best suits a logic design. The following
steps are suggested for estimating a design fit:

a

a
a

Partitioning the design
Determining the timing specifications
Estimating a fit

Also included in this application brief are suggestions for design entry.
Familiarity with EPLD architecture and device characteristics is assumed.
Refer to individual data sheets in this data book for complete descriptions
of EP-series EPLDs.

Partitioning
the Design

The design must be partitioned into functional blocks. Major functional
blocks can be expressed with standard TIL functions for fast integration
into the desired EPLD. If the design requires multiple EPLDs, I/O
connections between the EPLDs should be minimized. The complete
schematic should be structured as a set of subsystems-such as counters,
shift registers, comparators, basic gates, and flip-flops-to facilitate design
entry.

Determining
Timing
Specifications

Knowledge of basic clock frequency and critical timing paths is necessary
to choose the appropriate EPLD. Critical timing paths are determined on
the basis oftotal propagation delay (tpo), maximum clock frequency (fCNT),
set-up time (tsu), and clock-to-output delay (teOl)' Refer to the individual
data sheets in this data book for AC specifications. See also Application Brief
54 (Timing Simulation for EP-Series EPLDs) in this data book.

Estimating
a Fit

The follOwing formula is used to determine which EP-series EPLD will fit
a logic design:
IP+OP+ BFF+MR=TM
where

I A/tera Corporation

IP = number inputs - total EPLD inputs
OP = number of output pins
BFF = buried flip-flops
MR = macrofunction requirements
1M = total number of macrocells required

Page 443

I

I Estimating a Design Fit for EP-5erles EPLDs

Application Brief 60

I

Input and Output Pins
The number of input pins (lP) is equal to the number of inputs in the
schematic minus the total EPLD inputs (shown in the Product Selection Guide
or individual data sheets). If IP is less than zero, enter zero in the formula.
This subtraction is necessary because I/O pins can also be used as inputs.
The number of output pins (OP) is equal to the number of outputs in the
schematic.

Buried Flip-Flops
The number of buried flip-flops (BFF) includes D, T, JK, or SR flip-flops
that do not drive output pins.

Macrocell Requirements
The lower right-hand corner of each symbol in the A+PLUS TTL
MacroFunction Library shows the maximum number of macrocells (MR)
needed to build the function. Some macrofunctions have no macrocell
specifications. They use only a portion of the logic array, so additional
logiC may be integrated before the entire macrocell is used.
Since basic combinatorial gates (NAND, OR, XOR, etc.) are implemented
in the EPLD logic array, they do not require an entire macrocell, and may
be excluded from the estimate.

Total Macrocells
Table 1 shows the number of available macrocells for various EP-series
EPLDs. If the total number of macrocells (TM) required by a design is
smaller than the number of available macrocells for a given ELPD, the
design will probably fit into that EPLD. Macrocell availability is also
found in the Product Selection Guide and individual data sheets.
Table 1. Total Macrocell Availability

I Page444

EPlD

Macrocells

EP1830
EP1810
EP910
EP640
EP630
EP610
EP330
EP320

48
48
24
16
16
16
8
8

Altera Corporation

I

I Application Brief 60

Estimating B Design Fit for EP-8erles EPLDs

I

Design Entry

Design fit is quick and simple with LogiCaps schematic capture and a
mouse. The A+PLUS Primitive Library contains functions to support all
possible EPLD architectures, including basic gates, flip-flops, and I/O
structures. Boolean equations may also be entered directly into the
schematic. TIL macrofunctions that allow high-level design entry are
available in the A+PLUS TIL MacroFunction Library. LogiCaps features
split windows; multiple zoom levels; orthogonal rubberbanding; automatic
tag-and-drag editing; and area editing, save, and load functions. Schematics
may be printed or plotted for hard~opy documentation.

Helpful Hints

A+PLUS offers the following features to facilitate design entry. For
additional information on design entry and guidelines, refer to the
MacroFunction Tutorial in the LogiCaps manual.

MacroMunching
The A+PLUS Design Processor (ADP) automatically removes any unused
logic within a macrofunction. This feature, called ''MacroM unching," allows
designers to use macrofunctions without the worry of losing design
efficiency. For example, if a 74374 octal register is used in a schematic, but
only six of the eight outputs are connected, the ADP automatically removes
the logic associated with the two unused outputs from the deSign. Thus,
the total macrocell count for the macrofunction is six rather than eight.

1/0 Architecture Compression
A+PLUS automatically compresses the architecture of I/O primitives.
Macrofunction outputs that drive I/O pins via a COliF primitive are
compressed inside the I/O structure of the EPLD. Therefore, any
macrofunction output that drives an I/O pin (COliF) should not be added
to the Macrofunction Requirements section (MR) of the estimation formula.

Input Default Values
Each macrofunction contains intelligent input default values (UeC or GliD).
If a macrofunction input is not used, it automatically defaults to either UCC
or GttD, so the user will not have to manually connect vee or GttD to
unused inputs. For example, an active-low Clear signal has an input
default value of VCC that always disables an unused function. Refer to the
ITL MacroFunctions manual for specific input default values.

Altera-Provided Macrofunctions
In addition to familiar TIL macrofunctions, the A+PLUS MacroFunction
Library also provides custom functions optimized for EP-series EPLD
architecture. These include counters such as SCOUttT, which uses T-type

I A/tera Corporation

PBge44sl

I Estimating a Design Fit for EP-5erles EPLDs

Application Brief 60

I

rather than D flip-flops. When implementing counters inside EPLDs,
macrofunctions similar to 8COUNT are recommended for most efficient
EPLD resource utilization.

Estimation
Example

The target EPLD for the sample circuit shown in Figure 1 is the EP610.
When the estimation worksheet shown in Figure 2 is completed, it shows
that the design will fit into the EP610 EPLD.
A blank estimation worksheet is provided at the end of this application
brief.

Figure 1. Sample Circuit
The target EPLD in this sample circuit is an EP610.

SELA c::::::~------------.;..-.
INP
SELB C::::::~-----------'
INP
CNTCLK

CLOCK '-'---11---';'-

~ ........ ~~~!.~~~.~~~~........;
CLR

~---e

r----~--f

________ • C

INP
7404

CNTCLK

I Page446

---+--

r---:--t

>--£=>:

E

~-------!--f

>--£=>:

G

Altera Corporation

I

I Application Brief 60

Estimating a Design Fit for EP-5erles EPLDs

I

Figure 2. Estimation Worksheet Example
This example uses an EP610 as the target EPLD

for

the sample circuit shown in Figure ,.

1. INPUT PINS

IP=

SELB

SELA

CLOCK

2. OUTPUT PINS

7

OP=

A

B

c

E

F

G

3. BURIED LOGIC

o

DFF=

BFF=

o

TFF=

4. TTL LOGIC
(MACROFUNCTIONS)

MF=

CLR

o

o
JKFF

=

o

SRFF ..

o

8

=0
7447 = 0

74153

FREQOIV =4

74160 = 4

5. TOTAL MACROCELLS

6. TARGET EPLD

EP1830
EP1810

TM = IP + OP + BFF + MF =

(Circle appropriate EPLD)

EP910

EP640

EP330

EP630

EP320

~
I A/tera Corporation

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I

I Estimating a Design Fit for EP-5erles EPLDs

Application Brief 60

I

Est/mat/on Worksheet

1. INPUT PINS

IP=

2. OUTPUT PINS

OP=

3. BURIED LOGIC

BFF=

OFF,.,

TFF ..

4. TTL LOGIC

JKFF-

SRFF-

MF=

(MACROFUNCTIONS)

s. TOTAL MACROCELLS

6. TARGET EPLD

EP1830
EP1810

TM

=IP + OP + BFF + MF =

(Circle appropriate EPLD)

EP910

EP640

EP330

EP630

EP320

EP610

I Page448

Altera Corporation

I

Multiway Branching
with the EPS448 SAM EPLD

I October 1990, ver. 2
Introduction

Application Brief 631
The EPS448 Stand-Alone Microsequencer (SAM) EPLD performs a fourway branch in a single clock cycle. This application brief describes two
processes:

a
a

How to perform multiway branching
How to access more than four product terms per branch

The application brief assumes a working understanding of the EPS448
architecture and the SAM Assembly Language (ASM) or Altera State
Machine Input Language (ASMILE).

Beyond
Four-Way
Branching

The EPS448 performs multiway branching in three different ways:

a
a
a

Linked branching
Dispatch routine
Counter-conditioned branching

linked Branching
Linked branching (shown in Figure 1) uses 2 clock cycles to perform
branching of up to 16 wa ys. On the first clock cycle, the machine completes
a 4-way branch to 4 intermediate states; on the second clock cycle, it
Figure 1. Linked Branching

Altera Corporation

Intermediate states can generate a 16-way branch in 2 clock cycles. In the first clock cycle, the
machine branches to 1 of 4 intermediate states (SA to SO). On the second clock edge, the machinp.
performs another 4·way branch to 1 of 16 states (AI to A4, 81 to 84, C1 to C4, 01 to 04).

Page 449

I

I Multlway Branching with the EPS448 SAM EPLD

Application Brief 63

I

finishes with a 4-way branch out of each of these intermediate states. The
result is a 16-way branch in 2 clock cycles. This method can be implemented
with either ASMILEor ASM design entry.
In applications running at low frequency, it may be possible to double the
EPS448 clock frequency, use linked branching, and give the appearance of
a multiway branch in a single system clock.

Dispatch Routine
The dispatch routine can perform any number of branches. Inputs are
pushed onto the stack in the first clock cycle and are used as the next-state
address in the second clock cycle. The ASM commands PUSHI or
ANDPUSHI push the inputs onto the stack, and the RETURN command
causes a branch to that address.
In the sample code shown in Figure 2, ANDPUSHI pushes the inputs onto
the stack after first masking them with the binary number BBBBIIIBB,
where input 17 is the most significant bit and input IB is the least
significant bit. Consequently, an even number between 0 and 14 (decimal)
is pushed onto the stack, matching the binary number for 13 12 11 B.
The RETURN command causes the top-of-stack to become the next
address. Since this value is an even decimal number between 0 and 14, an
8-way branch to one of these addresses is performed. To complete the
branch, the 8 even memory add resses between 0 and 14 must con tain the 8
potential next states. Instructions are placed in a particular memory location
Figure 2. Dispatch Routine

The dispatch routine performs an 8-way branch in 2 cIocI< cycles. On the first clock edge, the
number represented by the top-at-stack is used as the next address. Since 13, 12, and 11 can be
used to represent an even number between 0 and 14, each at these addresses is a potential next
state.

S8: [STATE8] ANDPUSHI 88881118B;
~ Push 13, 12. and 11 onto the stack

%

SI: [STATEl] RETURN;
~ JUMp to the top of stack %
8D:
2D:
4D:
6D:
SD:
18D:
12D:
14D:

I Page450

[OUT8] JUMP NEXT8;
[OUT2] JUMP NEXT2;
[OUT4] JUMP NEXT4;
[OUT6] JUMP NEXT6;
[OUTS] JUMP NEXTS;
[OUTI8] JUMP NEXTI8;
[OUTI2] JUMP HEXTI2;
[OUTI4] JUMP HEXTI4;

A/tera Corporation

I

I Application Brief 63

I

Multiway Branching with the EPS448 SAM EPLD

by using an absolute label instead of a relative label. Absolute labels must
represent a legal and unique memory location within the EPS448 EPLD.
Addresses and numbers specified with SAM+PLUS software must start
with a digit and end with H (hexadecimal), D (decimal), or B (binary). For
example, the instruction 4D: [OUT41 JUMP NEXT4 in Figure 2 is placed
in address 4D of the microcode. It is executed if 1'13*12*1'11 is true at the
end of the ANDPUSHI command because input 12 (high) translates to 4D.
The following list shows examples of absolute, relative, and illegal labels:
Absolute labels:
Relative labels:
Illegal labels:

18881B, 8F2H, 44D
F2H,44D
44, 8F2D, 18881H

Counter-Cond itioned Branchi ng
Counter-conditioned branching uses the counter as a flag and performs a
two-way branch with the LOOPNZ command, based on the value of the
counter. The two branched addresses can be multiway-branch addresses
that permit two additional four-way branches. This branching scheme
creates an eight-way branch in a single clock cycle, as shown in Figure 3.
The code in Figure 3 shows an example of the actual ASM syntax required.
The LOADC command at the S8label sets the counter to lor 0, based on the
current value of the 11 input. The next instruction, at label Sl, performs the
branch with LOOPNZ. Based on the value in the counter, the next state will
come from label ABCD or from label EFGH. Since both of these labels are in

Figure 3. Counter-Conditioned Branching

An 8-way branch can be performed in a single clock cycle if the counter has been
set as a flag. In the code shown here, LOADC sets the counter nag based on the
input condition 11. LOOPNZ performs a 2-way branch based on the flag to label
ABeD or EFGH, both of which are 4-way branch locations.

SH: IF 11 THE" [OUTSH] LOADC 1D;
ELSE [OUTSH] LOADC 8D;
S1: LOOPHZ ABCD OHZEHO EFGH;
ABCD: IF 15 THE" [OUTA] JUMP MEXTA;
ELSEIF 16 THEM [OUTB] JUMP MEXTB;
ELSEIF 17 THEN [OUTC] JUMP MEXTC;
ELSE [OUTD] JUMP "EXTD;
EFGH: IF IH THEM [OUTE] JUMP "EXTE;
ELSEIF 15 THEN [OUTF] JUMP NEXTF;
ELSEIF 13 THEN [OUTG] JUMP "EXTG;
ELSE [OUTH] JUMP "EXTH;

I A/tera Corporation

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I Multiway Branching with the EPS448 SAM EPLD

Application Brief

631

the multiway-branch block, the actual next instruction depends on the
input values. If the counter is set to 1 and input condition 1'18*15 is true,
then the next command will be JUMP NEXTF.

More Than
Four Product
Terms per
Condition

A design that runs out of product terms fora branch condition, or generates
the error message Predicate too long, can still be fitted after some
adjustments. For example, the first branch condition in the following
ASMILE code contains five product terms, while the second condition
contains only one:
START:

IF

IF
S2

15-18' +
IS-II' ..,:
15-12' +
15-13' +
15-14'
12-11-12*13*14

THE" SI
THE" S8

It is possible to make a tradeoff between the number of branches and the
number of product terms. The software automatically partitions the first
branch, so tha t there are actually two branches to Sl--one branch wi th four
product terms and another with one product term:
START:

IF

IF
S2

15*18' +
15-11' +
15*12' +
15*13'
15*14'
12*11*12-13*14

THE" SI
THE" SI
THE" S8

This approach reduces the number of possible branches to three. In cases
where all four branches are needed, reordering the branches may reduce
the number of product terms. Also, reordering may make better use of the
built-in prioritization of the EPS448 architecture, since the second branch
condition can assume that the first condition has failed. In the previous
example, the first condition can befadored into 15*1'<18*11*12*13*14>, and
the branch order can be rearranged so tha t the S8 branch is considered first.
Then the 51 branch condition can assume that the expression
18*11 *12*13*14 has failed and need not be tested. The following example
shows the previous code reordered, with one product term per condition
(a fourth branch may easily be added):
START:

Conclusion

I Page452

IF
IF
S2

18*11*12*13*14
15

THE" S8
THE" SI

The flexibility of the EPS448 architecture allows the designer to perform
muItiway branching in a number of ways. If more than four product terms
exist per condition, they may be reduced through partitioning and
reordering.

A/tera Corporation

I

Vertical Cascading
of EPS448 SAM EPLDs
I October 1990, ver. 2
Introduction

Application Brief 651
When an application requires more states or more microcode depth than a
single EPS448 EPLD can provide, i.e., more than 448 states or words,
multiple EPLDs can be cascaded vertically to accommodate the additional
states. This application brief describes how to vertically cascade EPS448
EPLDs by passing control from one EPLD to another. The method that best
suits a specific application depends on how the sequencer is most easily
partitioned. The following methods are examined:

o
o
o
o

Sim pIe vertical cascading
Addressed-branch cascading
Vertical subroutine calls
Master / sla ve cascading

This application brief assumes an understanding of the EPS448 EPLD and
a working knowledge of Altera's Assembly Language (ASM) syntax.

Simple
Vertical
Cascading

When EPS448 EPLDs are verticall y cascaded, the outputs of all the devices
are tied together, forming a tri-state output bus (see Figure 1). One EPLD at
a time controls the output bus; all others are disabled by tri-state buffers.
The controlling EPLD performs sequencing until it encounters a sequence
found in another EPS448. Then it tri-states its outputs, and the other
EPS448 takes control of the bus.
The simplest method of vertically cascading EPS448 EPLDs is to use one
input pin to signal to a device that it must take control of the output bus
(Figure 1). A control line to each EPS448 (e.g., nGOl) is pulled up through
a 1 K-,Q resistor. When the active EPS448 passes control to another EPS448,
it pulls down the appropriate nGO signal and jumps to an idle state where
its outputs are tri-stated. This configuration allows conditional JUMP
instructions between EPS448 EPLDs.

I Altera Corporation

Page 453

I

Application Brief

Vertical Cascading of EPS448 SAM EPLDs

651

Rgure 1. Vertical Cascading
lKn

When EPS448 EPLDs are
vertically cascaded, the outputs
are tied together. While one
EPS448 has control of the
output bus, the others are tristate-disabled. Each EPS448
has one input (e.g., nG01) that
enables it onto the bus.
EPS448#2

OulpUtBus

EPS448 #3

EPS448#4

Clock - 4 f - - + - + + - -

Figure 2 shows the timing associated with this simple vertical cascading.
Initially, EPS448 #4 has control of the output bus and EPS448 #1 is idle.
EPS448 #1 outputs are tri-stated during this period. To pass control,
EPS448 #4 brings the nGOl signal low to activate EPS448 #1. On the next
clock cycle-called the transition clock period-the outputs of both
EPS448 #1 and EPS448 #4 tri-state. EPS448 #1 becomes active and takes
control of the output bus. EPS448 #4 becomes idle on the following clock.
Both EPLDs are tri-state-disabled during the transition clock period. This
idle period prevents potential glitches (i.e., bus contention with the other
EPLDs) during transitions from high-impedance to a valid output, or vice

I Page454

A/tera Corporation

I

IApplication Briel 65

I

Vertical Cascading of EPS448 SAM EPLDs

Figure 2. Passing Control between EPLDs
To pass control between two EPLDs (EPS448 #4 and EPS448 #1). EPS448 #4 starts active (1).
then brings nG01 /ow (2) to pass control. On the next clock period, both EPLDs are disabled (3)
before EPS448 #1 takes control of the output bus (4).
Clock

I

I
EPS448 #4

Output Bus

ANY1

H

nG01

X
X

ANY2

X

z

l

X
X

Z
Z

X
X

z
z

EPS448 #1
Output Bus

Z

nG02

Z

f
(1)

~

Z

(2)

X

~

z
Z

X

~

ANY3

H

x:=
x:=
x:=
C

(4)

(3)

versa. Ouring this clock period, the control lines (nGOl to nG04) float
unless they are pulled up by the resistors.
In another method, shown in Figure 3, both EPS448 EPLDs drive the same
value (OUTl) on the output bus for the transition clock period. This method
removes the need for pull-up resistors, but it may introduce temporary bus
contention, possibly causing a current surge into the EPS448 EPLDs and
inducing noise or ground bounce elsewhere on the board. However, bus
contention does not impair EPLD operation.
Figure 3. Alternative to Passing Control
To avoid the clock cycle where the output bus is left floating. both EPLDs drive the same value
onto the bus for a single clock cycle.
Clock

r

I
EPS448 #4

Output Bus
nG01

ANY1

H

X
X

ANY2

L

X
X

OUT1

L

X
X

Z

c

Z

C

ANY3

C

H

C

1m

EPS448#1

IA/tera Corporation

Output Bus

Z

nG02

Z

X
X

z
z

X
X

OUT1

H

X
X

Page 455

1-

Vertical Cascading of EPS448 SAM EPLDs

Application Brief

651

Each of the EPS448 EPLDs must have its own design file (with the extension
.ASH or .SHF). A segment of the code used in EPS448 #1 is shown in
Figure 4. While the machine is inactive, it remains in IDLE with the
outputs disabled. When it receives an active-low nGOl signal from pin lNO,
it jumps to the label STAHT, takes control of the output bus, and holds
nG02 to nG03 high, preventing the other EPLDs from competing for
control of the output bus.

Figure 4. Assembly Language Code for Vertical Cascading
This ASM syntax is for EPS448 #t. This EPLD sits in the IDLE state until the nGOt signal from
pin INO goes /OW. It then jumps to START and takes control of the output bus. When EPS448 #t
is ready to give up control of the outputs, it jumps to QUIT and brings one of the three nGO lines
low to activate the next machine. Finally, it jumps back to the IDLE state.

MACROS:
HOLD
G02
G03
G04
OUTI
ANY3
ANY2

Yo F F
Yo B 1
" 1 1
" B 1
" 1 8
1 1
1 B
" 1 B

.

..
.

F F F F
2 3 4 5

F

Yo

15 Yo

1 "
1 "
1 "

B
1

B

BB 1

"

...........
...........
...........

B

"

1 "
1 "

Yo

INSERT DESIRED

Yo OUTPUT VALUES
Yo

FOR THESE STATES

Yo
Yo
Yo

PROGRAM:
IDLE: IF /INB THEN [Zl JUMP START;
ELSE [Zl JUMP IDLE;
START: [HOLD ANY3l CONTINUE;

QUIT:

IF IN3 * IN4 THEN [G02 ANY2l JUMP IDLE;
ELSEIF
IN3 THEN [G03 ANY2l JUMP IDLE;
ELSE
[G04 ANY2l JUMP IDLE;

When EPS448 #1 is ready to pass control to another EPS448 EPLD, it jumps
to QU IT and pulls the a ppropria te nGO control line low. For example, when
G02 is the output, the EPS448 #1 F88 output goes low, bringing the signal
nG0210w and "waking up" EPS448 #2 on the next rising edge of the clock.
In this example, QUIT is the label of a multiway branch instruction, so any
one of the other three EPS448 EPLDs can be the next one activated. After
activating the next machine, EPS448 #1 jumps to IDLE and waits to be
given control again.

AddressedBranch
Cascading
I Page 456

With an increasing number of EPS448 EPLDs, an addressed branching
configuration is more convenient (see Figure 5). A branch bus lies alongside
the output bus. Each EPS448 examines the branch bus, ~nd stays idle until
an address assigned to it appears on the bus. The EPS448 then takes control
of both buses. Since each EPS448 device has access to the branch bus, each
EPS448 can call anyone of the other EPS448 EPLDs.
Altera Corporation

I

I Application Brief 65

Vertical Cascading of EPS448 SAM EPLDs

I

Figure 5. AddressedBranch Cascading
In addressed-branch
cascading, each EPS448
EPLD wakes up when it sees
one of its assigned addresses
onlhe branch bus. Each
EPLD can recognize more
than one address. For
example, EPS448 #1 takes
control if it sees addresses 0,
1, or 2 on the branch bus.

OulpUtBus

Branch Bus

A single EPS448 EPLD can have several addresses assigned to it, with each
address corresponding to a different starting location in its microcode.
Thus, a Single EPLD can contain more than one block of independent
states. In such a case, each address on the branch bus corresponds to a
block of states within an EPLD.
The branch bus in figureS consists of three output bits (F88,F81,and F82)
that are paSSively pulled up by 1 K-Q resistors and controlled by the active
EPS448 EPLD. Values on the branch bus serve as branch addresses that
access discrete blocks of states. EPS448 #1 has been assigned branch
addresses 0, 1, and 2, each of which corresponds to a different sequence of
states within the EPLD. While EPS448 #1 has control of the output bus, it

I Altera Corporation

Page 457

I

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II!.

I Vertical Cascading of EPS448 SAM EPLDs

Application Brief 65\

drives the branch bus with the address of its current sequence so that other
machines are not activated. Only when it is ready to pass control, does it
drive a new value onto the branch bus. For example, when EPS448 #1
outputs the branch address 3, EPS448 #2 assumes control.
Figure 6 shows a portion of the ASM code required for EPS448 #1. This
code is similar to the code for simple cascading. While EPS448 #1 is idle, it
must look for any of its three possible branch addresses (BAB, BAl, and BA2)
to become valid. If one of these values appears on the branch bus, EPS448
#1 jumps to the start of the corresponding sequence (STARTB, STARTl, or
START2).

Figure 6. Assembly Language Code for Addressed·Branch Cascading
The addressed cascading shown in Figure 5 uses three input lines (INO to IN2) to address
different routines within a single EPLD. By specifying different addresses at the QUIT label, any
routine in any other device can be called.

MACROS:
GOB
Gal
G03
G03
G04
G05
GO?
AtlY2
AtlY3

Yo F
Yo B

"B
"B
"B
"B
"I

F F
1 2

"I

B B"
B I"
1 B"
1 I"
B I"
B I"

"I

1

"I
"B

F
3

F Yo
15 Yo

I"

B"
I"

EQUATI OtiS:
BAB = /ltl2*/ltll*/ltlB;
BAI
/ltl2*/ltll*ltlB
BA2 = /ltl2*ltll*/ltiB ;

ItiPUT ADDRESS DECODES
BRAtiCH ADDRESS B Yo
BRAtiCH ADDRESS 1 Yo
Yo BRAtiCH ADDRESS 2 Yo
Yo
Yo
Yo

Yo

PROGRAM:

IPage 458

IDLE:

IF BAB THEti [Zl JUMP STARTB;
ELSEIF BAI THEti [Zl JUMP START1;
ELSEIF BA2 THEti [Zl JUMP START2;
ELSE [Zl J~MP IDLE;

STARTB:

[GOB AtlY31 COtiTl tlUE ;

STARTI :

[Gal AtlY31 COtiTl tlUE ;

START2:

[G02 AtlY31 COtlTltlUE;

QUIT:

IF Itl5 * Itl6 THEti
ELSEIF Itl6 THEti
ELSEIF ItI? THEti
ELSE [GO? AtlY21

[G03
[G04
[G05
JUMP

AtlY21 JUMP IDLE
AtlY21 JUMP IDLE
AtlY21 JUMP IDLE
IDLE;

Altera Corporation

I

I Application Brief 65

Vertical Cascading of EPS448 SAM EPLDs

I

When EPS448 #1 is ready to give up control, it jumps to QUIT until it calls
the next address. Each branch calls a different routine by specifying a
different value on the branch bus. (Note that the Goe to GO? macros
correspond to binary branch addresses, i.e., Ge3 = ell.)

Vertical
Subroutine
Calls

The configurations discussed so far have used a JUMP function between
EPS448 EPLDs. However, it is possible to perform subroutine calls between
EPLDs. A subroutine call differs from a jump in that it must eventually
jump back to the machine that called it. The subroutine must be able to
recall the return address of the calling EPLD. The return address can be
stored on the EPS448 internal stack. Subroutines are most easily
implemented with the branch bus configuration (Figure 5).
The time required for passing control is illustrated in Figure 7. Before the
subroutine call, EPS448 #1 is in control of the bus and is executing the block

Figure 7. Timing of a
Vertically Cascaded
Subroutine
In a sample cascaded
subroutine call, EPS448 #1 calls
subroutine 5 'rom EPS448 #3 by
placing 5 on the branch bus.
Next, EPS448 #1 places its own
address (1) on the branch bus to
tell the subroutine where to
return. Finally, EPS448 #1
tri-states, and on the next clock
period, EPS448 #3 takes control
of the output bus. When
EPS448 #3 (address 5) is ready
to return, it puts the return value
(1) on the branch bus and then
idles.

Subroutine Call
EPS448 #1 (Routine 1)
Outputs

ANY1

Branch Address

X

ANY2

X

5

X

ANY3

X

X
X

z

X
X

Z

x=c
x=c

z
z

EPS448 #3 (Subroutine 5)
Outputs

Z

X

z

X

z

X

z

X ANY4

~

Branch Address

Z

~

Z

~

Z

~

z

f

CC

EPS448#3
reads
JUMP

EPS448 #3
stores
return
address

Dead
cycle

5

EPS448 #3
active

Subroutine Return
EPS448 #1 (Routine 1)
Outputs

Z

Branch Address

Z

X
X

z
z

X
X

z
z

X ANY10
X

~

x:::=c

EPS448 #3 (Subroutine 5)
Outputs
Branch Address

ANYB
5

Z

X

~

Z

X z

EPS448#1
reads
JUMP

I Altera Corporation

z

X ANY9 X

~

Dead
cycle

f

x=c
x=c

EPS448#1
active

Page 459 \

I Vertical Cascading of EPS448 SAM EPLDs

Application Brief 65

I

of states starting with 1 (branch address 1). It drives the branch bus with
the value 1 until it is ready to call a subroutine (branch address 5) within
another EPLD (EPS448 #3). To start the subroutine call, EPS448 #1 specifies
the address of subroutine 5 on the branch bus, which wakes up EPS448 #3.
EPS448 #1 then applies return address 1 so that EPS448 #3 can store the
return value on its internal stack. EPS448 #1 tri-states both the branch and
output buses on the next clock cycle. A "dead" clock cycle follows, after
which EPS448 #3 takes control of the output bus.
The syntax required for EPS448 #3 is shown in Figure 8. Note that after
EPS448 #3 reads its address, it still leaves its outputs tri-stated for two
more clock cycles. The AtlDPUSHI opcode is used to store the return
address in the stack by masking off inputs Itl3-Itl7. See Application Brief63
(Multiway Branching with the EPS448 SAM EPLD) for information on how
to use ANDPUSHI with dispatch routines.

Figure 8. Assembly Language Code for Vertically cascaded Subroutine
In this example, EPS448 #3 is used as a subroutine at the branch address 5. After it is called, it
stor85 the retum address on the stack with the ANDPUSHI command. The RETURN command
jumps to an absolute address, which puts the correct retum address onto the branch bus.

MACROS:

Y. OUTPUT VALUES FOR BRANCH BUS Y.
G08
"888"
GOI
"881"
GOZ = "818"
G03 = "811"
G04 = "188"
GOS = "181"
GOG = "118"
GO? = "111"
Y. OUTPUT BUS VALUES Y.

ANY3 = "18 ..• 1", ANYB

= "88 .•. 1",

ANY9

= "81 ... 8"

EQUATIONS:y. BRANCH ADDRESS INPUTS Y.
BAS = INZ*/IN1*INB;
Y. BRANCH ADDRESS SY.
PROGRAM:
Yo IDLE OR START THE SUBROUTINE Yo

IDLE:

IF BAS THEN [Z] ANDPUSHI ?H GOTO STARTG;
ELSE [Z] JUMP IDLE;

STARTS:

[Z] CO~TINUE;
[GOS ANY3] .CONTINUE;

Y. DEAD CYCLE Y.
Y. TAXE CONROL OF Y.
Y. OUTPUT BUS Y.

QUITS:

[GOS ANVB] RETURN;

Yo

SUBROUTINE RETURN Y.

JUMP TABLE (RESERVED LOCATIONS) Yo
BD: [G08 ANY9] JUMP IDLE;
Y. ALSO THE PO~ER-UP STATE
ID: [GOI ANY9] JUMP IDLE;
ZD: [GOZ AMY9] JUMP IDLE;
3D: [G03 ANY9] JUMP IDLE;
4D: [G04 ANY9] JUMP IDLE;
SD: [GOS ANY9] JUMP IDLE;
GD: [GOG ANY9] JUMP IDLE;
?D: [GO? ANY9] JUMP IDLE;
Y. ERROR CONDITION Y.

Yo

IPage 460

Yo

A/tera Corporation

I

I Application Brief 65

Vertlca' Cascading of EPS448 SAM EPLDs

I

To return from the subroutine, EPS448 #3 applies the return address
(branch address 1) on the branch bus for one clock cycle (see Figure 7).
EPS448 #1 reads this address and takes control of the output bus by
jumping to the Clddress at the top-of-stack. The RETURN opcode at the QUIT
label accomplishes this task. This address must be between 0 and 7 because
the inputs IN3 to IN7 are masked off when the ANDPUSHI opcode pushes
the return address onto the stack. In this example, the top-of-stack is 1, and
a jump to address lD (1 decimal) is performed. Address lD has the correct
output specification to signal EPS448 #1 to take control of the buses.
Finally, EPS448 #3 jumps back to IDLE.
With this approach, branch address 7 is unusable because it corresponds to
the default condition of all branch-address bits pulled up. If address 7D is
reached, an error has occurred and all cascaded EPS448 EPLDs must be
reset.
Ouring power-up, the EPLD starts in state BD. All machines jump to their
idle state on the next clock cycle, and the EPS448 that initiates control after
power-up jumps to its correct starting state.
After making the subroutine call, EPS448 #1 must go into a high-impedance
state and wait for the routine to finish. It can take this action in one of two
ways: it can return to its IDLE starting state; or it can stay in a separate
loop. In the first case, EPS448 #1 regains control by recognizing its address,
effectively restarting. In the second case, EPS448 #1 returns to the state it
was in when the call was made.

Master/Slave
Cascading

Another vertical cascading method is the master / slave configuration. See
Figure 9. A single EPS448 (the master) controls the overall sequencing by
calling routines within other EPS448 EPLDs (the slaves). The slaves are
cascaded with all but one of the outputs connected to the output bus. The
single output (FBB), called nDone in Figure 9, 5 passively pulled up through
the resistor. When an active slave EPLD has finished executing its routine,
it pulls the nDone line low. This action alerts the master that it should jump
to the next routine.
Any number of control lines can run from the master to a given slave
depending on the number of routines within the slave. For n control lines
the slave can have 2n-l routines. When all control lines are high, the slave
is idle. In this example, Slave #1 has two inputs and thus can contain up to
three routines. When both CONTROLB and CONTROLl are high, Slave #1
is idle. There is no limit to the number of slaves that can be added to this
system. Furthermore, unlike the branch bus method, the number of inputs
to the other EPLDs does not increase as more routines are added.

IAltera Corporation

Page461

1m

I

I

Vertical Cascading of EPS448 SAM EPLDs

Application Brief

651

Rgure 9. MasterlSlave Cascading
In a master/slave conliguration, one EPS448 EPLD ~he master) OOfltrois sequencing. It calls
routines from any number of slaves. The slaves signify that they are finished by pulling the
nDONE line low.

nDONE

a~-4--------------~~

Figure 10 shows the timing associated with the master/slave configuration.
Slave #1 originally has control of the output bus. It signifies that it is done
by pulling nDOtfE low. The Master responds by initiating the Slave #2
machine, which then takes over the output bus. (The output bus is undefined
for a single clock cycle.)

I Page462

Altera Corporation

I

I Application Brief 65

Vertical Cascading of EPS448 SAM EPLDs

I

Rgure 10. Timing 01 Master/Slavs Cascading
In the example o( mastertSiave cascading shown in Figure 9, Slave #1 starts with control o( the
output bus. nsignifies it is done by bringing nDONE /OW. The Master then initiates Slave #2 by
sending it an active starting address.
Clock

Master
To SLAVE'

IDLE

X

IDLE

X

IDLE

X

IDLE

X

IDLE

X

IDLE

To SLAVE2

IDLE

X

IDLE

X

IDLE

X

G02

X

IDLE

X

IDLE

ANY'

X

ANY2

X

ANY3

X

Z

X

z

X

Z

H

X

H

X

L

X

Z

X

z

X

Z

SIave'1
Output Bus

nDONE

Slave #2
Output Bus

Z

X

z

X

z

X

z

X

ANY4

X

ANY5

nDONE

Z

X

z

X

z

X

z

X

H

X

H

Final Tips on
Vertical
Cascading

CJ

Each technique for vertically cascading EPS448 EPLDs consumes
output and input pins from each device to accommodate control
passing. If needed, additional outputs can be created by horizontally
cascading EPLDs (see the SAM+PLUS Reference Guide for more
information). Additional inputs can be generated by multiplexing
several signals and reducing them to the eight inputs available with
the EPS448 EPLD. See Application Brief66 (Input Reduction for the EPS448
SAM EPLD) for more information on input reduction.

CJ

Partitioning-i.e., the process of dividing the code or state segments
among the multiple EPS448 EPLDs-is the most important step in
creating a vertically cascaded sequencer. Most large sequential
applications have natural divisions that indicate where partition
borders should fall. The general goal in partitioning is to create blocks
of sequences that fit within a single EPS448 EPLD, and to minimize
control transfers from one EPLD to another.

CJ

IA/tara Corporation

All Clock pins should be tied together, as should all Reset pins. Inputs
to different EPS448 EPLDs need not be tied together. In fact, it maybe
desirable for different sections or routines of the overall sequencer to
branch on the basis of different input signals.

Page 463

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II!.

I Vertical Cascading 01 EPS448 SAM EPLDs

IPage 464

Application Briel 65

I

o

In vertical cascading, the output lines from the resulting sequencer
originate at a tri-state output bus. The output bus signals should never
be connected to system Clock or Latch Enable inputs. As in any tristatable bus, the output bus of a cascaded EPS448 EPLD is not
guaranteed to be glitch-free during transitions from high-impedance
to output valid, or vice versa.

o

Only one EPLD may become active on power-up. All other EPLDs
should jump to IDLE, and therefore should have the following line in
their source files: BD: [Z] JUMP IDLE.

o

If every EPLD goes IDLE without first calling another EPLD (or
bringing nDOttE low), the system is deadlocked in an idle state. This
problem can be avoided with proper coding, or with a watchdog
timer implemented in one of the EPS448 EPLDs. The watchdog timer
counts to a final count value that corresponds to a fixed time period.
During normal operation, the other EPS448s periodically clear the
watchdog counter, preventing it from reaching its final count value.
Therefore, if the watchdog reaches its final count value, a system error
has occurred. The watchdog timer should then reset the system or
generate the appropriate system error status.

A/lera Corporation

I

Input Reduction
for the EPS448 SAM EPLD

I October 1990, ver. 2
Introduction

Application Brief 661
The EPS448 SAM EPLD provides eight dedicated inputs. Applications that
require more than eight inputs can use external logic to reduce the number
of signals while retaining the same sequencing function. This application
brief describes two techniques for reducing the number of inputs:

o Input multiplexing
o Input encoding
Both methods use an EP-series EPLD in front of the EPS448 device to
reduce the number of inputs to a maximum of eight. Input multiplexing
reduces the inputs based on the current state of the machine, while input
encoding does not use the current state at all (see Figure 1).
Figure 1. Input Reduction Methods

Input count can be reduced through multiplexing and
encoding.

Input Multiplexing
EPS448

Input Encoding

I Altera Corporation

Page 465

I

IInput Rflductlon lor the EPS448 SAM EPLD
Input
Multiplexing

Application Brief 66

I

Input multiplexing is the most flexible approach to input reduction. A
multiplexer transforms the system signals into eight outputs that connect
to the EPS448 inputs and are used for branch-control decisions. The EPS448
EPLD controls the multiplexer select lines based on the current state. Thus,
each state selects the set of inputs required to make the subsequent branch.
Figure 2 shows a sample state machine. It has 12 inputs (A to L), but only 8
(or fewer) are needed for a single 4-way branch.

Rgure 2. Input Multiplexing Example
This state machins rsquir9S 12 inputs, but fJ8V9r more than 8 for a single 4-way branch. Input
multiplexing performs 12-to-8 multiplexing to achieve the input reduction.

5B: 51
51: IF A ./8 THE" 51
IF A ./C THE" 52
IF A ./D THE" 53
54
52: IF A • E • /F THE" 54
IF 8 • F • /G THE" 51
IF C • G • /H THE" 5B
52
53: IF H • I • J • X • L THE" 54
IF A • H • I • J • X THE" 52
IF A • B • H • I • J THE" 5B
53
54: IF C • 8 • /H • J THE" 5B
IF A • D • /1 • X THE" 52
IF A + C + H + I THE" 53

Table 1 shows the inputs required by each of the branching states. This
table maps each state against the system inputs required to determine the
next state. Requirements are divided into three sets; each set contains
fewer than eight inputs. One set at a time is routed to the input pins of the
EPS448 EPLD.

Table 1. Inputs Required for Each State
System Inputs
Set

Set
Set
Set
Set

IPage 466

State

1
1
2
3

S1
S2
S3
S4

A

B

C

0

X
X
X
X

X
X
X
X

X
X

X

X

X

E

F

G

H

I

J

K

L

X

X

X

X
X
X

X
X

X
X

X

X

A/tara Corporation

I

I Application Brief 66

Input Reduction for the EPS448 SAM EPLD

I

State Sl requires four inputs to determine the next state. S2, S3, and S4 each
require seven inputs. Sl and S2 together still only require eight inputs (A
to H). State S8 does not require any inputs because it performs an
unconditional branch.
The input requirements, shown in Table 1, can be divided into three sets.
Set 1, required by states Sl and S2, consists of inputs A, I, C, D, E, F, G, and
H. Set 2, required by state S3, consists of inputs A, I, H, I, J, JC, and L. Set 3,
required by state S3, consists of inputs A, I, C, D, H, I, and J. The current
state determines which set o..f inputs is routed to the EPS448's inputs.
Figure 3 illustrates input multiplexing. Since inputs A, I, and Hare
included in all three of the input sets, they run directly into the EPS448
Figure 3. Input Multiplexing
This input reduction method requires multiplexing the many system signals (A to L) down to the 8 input pins of the EPS448 EPLD (10
to 17). Inputs A, B, and H run diredly into the EPS448 device. An EP610 EPLD takes the remaining 9 inputs and multiplexes them
down to 10 to 14. The multiplexers within the EP610 are entered with LogiCaps. SELECTO and SELECTt, which select the inputs
needed for the next transition, come from the EPS448 EPLD.
EP610

C

10

A
B

11

0

H

C

0
E

E
K
12

G

1

J
K

F
J

13

G

SELECTO
SELECT1

A/tera Corporation

Page 467

I

I Input Reduction lor the EPS448 SAM EPLD

Application Brief 66

I

EPLD (15 to 17). The other nine inputs are routed through an EP610 EPLD
and multiplexed down to the five remaining input pins (14 to un. Two
outputs from the EPS448 EPLD (SELECT8 and SELECT1), which depend
on the current state, feed the multiplexer select inputs on the EP610 and
direct the correct set of system signals to the EPS448 inputs.
The EP610 multiplexing circuitry can be created with A+PLU5 TIL
macrofunctions and LogiCaps schematic capture software. The nine system
signals (C, D, E, F, G, I, J, JC, and L) enter from the left, and the five inputs
for the EPS448 EPLD (I8 to 14) leave on the right.
Table 2 shows the resulting truth table for the inputs to the EPS448 EPLD.
Table 2. Input Multiplexing Truth Table
SELECT1

0
0
1
1

SELECTO

0
1
0
1

10

11

12

13

14

15

16

17

0
C
0
C

0

0
L
0

0
E

0
F

K
0

J
J

0
G
I
I

H
H
H
H

B
B
B
B

A
A
A
A

The State Machine File (SMF) for the EPS448 EPLD (Figure 4) must contain
references that map the 12 system signals to the appropriate EPS448 input
pin. The Equations Section performs this mapping by making each system
signal equal to a pin name. For example, Land D are both equal to input
pin 11, because--d.epending on the current state-the multiplexer places
one of these two signals a t pin 11.
The select lines for the EP610 multiplexer, SELECT8 and SELECT1, are
defined as outputs in the STATES section, together with all of the generalpurpose outputs. For example, S3 has outputs SELECT 1 = 1 and
SELECT8 =8, which corresponds to input set 2.

Input
Encoding

Like input multiplexing, input encoding also uses an EP-series EPLD to
map system signals to the eight input pins available with the EPS448
EPLD. Unlike the multiplexing method, however, input encoding completes
the input reduction without using the current state of the machine.
Input encoding is most frequently used for address decoding to enable a
sequencer to make a branch decision. This decision is based on the current
value of an address. For example, the EPS448 EPLD may need to sit in an
idle state until an eight-bit address reaches OF hex. If all eight address bits
were to go into the EPS448 device, no other input pins would be left for
additional branch conditions. Therefore, it is more efficient to run the eight
address bits into an EP610 device, which encodes the address down to a
single bit that notifies the EPS448 EPLD when the address equals OF hex.
Only one EPS448 input is consumed, leaving seven inputs for other uses. _

IPage 468

A/tera Corporation I

I Application Brief 66

Input Reduction for the EPS448 SAM EPLD

I

Rgure 4. Modified EPS448 State Machine Rle
The modified SMF for the EPS448 EPLD includes an Equations S8ction thai maps the system inputs to the aaual input pin used.
The SELECTO and SELECT1 outputs cause the proper inputs to be routed to the pins for the next branch.

PART:

IPS448

INPUTS:

10,11, IZ, 13, 14, A, I, H

OUTPUTS:
SILECT1, SELECT8, FOZ, F83, F84, F85, F86, F87, F88, F89, F18, Fll, FIZ, F13, F14, F15
)C The select lines !JO to the EP618
)C
IQUATIOHS:
The E~uations Section is used to "ap the
)C to the actual EPS448 input pi ns

)C

C

D
L
E
X
F

J
G
I

s~ste"

input pins

)C
)C

18;
11;
11;
IZ;
IZ;
13;
13;

14;
14;

I1ACHINE: EXAI1PLEZ
STATES:
S8
Sl
SZ
S3
S4

[SELECT1 SELECT8 F8Z F83 F84 F85 F86 F87 F88 F89 Fl8 Fll FlZ F13 F14 F15]
8
X X X X X X X X X X X X X X ]
8
[
8
X X X X X X X X X X X X X X ]
1
[
8
X X X X X X X X X X X X X X ]
1
[
1
X X X X X X X X X X X X X X ]
8
[
X ]
1
X
X X X X X X X X X X X X
1
[

S8: Sl
Sl: IFA ·/1 THEN Sl
IFA ·/C THEN SZ
IFA ·/D THEN S3
S4
SZ: IF A • E • /F THEN S4
IF I • F • /G THEN Sl
IF C • G • /H THEN S8
SZ
S3: IF H • I • J • X • L THEN S4
IF A • H • I • J • X THEN SZ
IF A • B • H • I • J THEN S8
S3
S4: IF C • B • /H • J THEN S8
IF A • D • /1 • X THEN SZ
IF A + C + H + I THEN S3
S4
lENDS

II

Altera Corporation

Page 469

I

IInput Reduction for the EPS448 SAM EPLD

Application Brie'66

I

Input encoding, however, can do much more than address decoding.
Anytime a group of inputs represents a single piece of information-such
as a board-level command, interrupt lines, or carry-out signals--input
encoding should be considered. In particular, input encoding is advised if
a group contains an illegal input combination, or an input combination
with several "don't care" values.
Table 3 shows the truth table for a state machine that issues a series of
commands to the EPS448 EPLD. The EPS448 executes a given sequence of
states for each command. The state machine contains 19 commands, each
of which is represented by a unique combination of 13 signals labeled A
through tI. The truth table shows the 13 signals and the corresponding
commands. If Ais 0, for example, then the command to the EPS448 EPLD is
called IDLE, regardless of the other 12 input values.
Table 3. Input Truth Table
F G H

1

J

K

L M

System
Command

Row 1#
(14 to 10)

X X X X X X X
0 X X X X X X
1 0 X X X X X
1 1 0 0 0 X X
1 1 0 0 0 1 X
1 1 0 0 1 0 X
1 1 0 0 1 1 X
1 1 0 1 X X 0
1 1 0 1 X X 0
1 1 0 1 X X 1
1 1 0 1 X X 1
1 1 1 0 X X X
1 1 1 0 X X X
1 1 1 0 X X X
1 1 1 0 X X X
1 1 1 1 X X X
1 1 1 1 X X X
1 1 1 1 X X X
1 1 1 1 X X X

X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

IDLE
ERROR
RESET
BACK1
RIGHT1
LEFT1
FORWD1
BACK2
RIGHT2
LEFT2
FORWD2
BACK3
RIGHT3
LEFT3
FORWD3
BACK4
RIGHT4
LEFT4
FORWD4

0
1
2
3
4
5
6

ABC

0
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1

D

E

X
X
X
X
X
X
X
0
X
1
X
0
X
1
X
X 0 0 X
X 0 1 X
X 1 0 X
X 1 1 X
X X X 0
X X X 0
X X X 1
X X X 1

0
1
0
1

7
8

9
10
11
12
13
14
15
16

17
18

Since the truth table contains only 19 rows,S bits (18, 11,12,13, and 14) can
uniquely define the current command. These 5 bits are the only inputs that
the EPS448 EPLD needs to make the branch decisions. With the resulting
input encoding, 5 inputs--instead of 13 as shown in the table-are required,
and the design easily fits into the EPS448 EPLD, with 3 inputs to spare.
Figure 5 shows how an EP610 accomplishes the input encoding. The 13
inputs (A to tI) go into the EP610 and are converted to five outputs (18 to
14) that connect to the EPS448 EPLD.

IPage 470

Altera Corporation

I

I Application Brief 66

I

Input Reduct/on for the EPS448 SAM EPLD

Rgure 5./nput Encoding
With input encoding, an EP610 EPLD compresses 13 syst8l1l inputs (A to 1.4) down to 5 inputs to
the EPS448 EPLD (10 to 14). Three input pins (15 to 17) are still available for general-purpose use.
A
B

c

EPS448

0
E
F
G
H

K

L
M

Altera's state machine entry language (provided with the A+PLUS
documentation) is the most convenient language for entering the EP610
truth table. Figure 6 shows the SMF that describes the truth table. The
Network Section indicates that the outputs (18 to 14) are combinatorial
outputs with no feedback (CONF). The Truth Table Section of the file lists
the 13 inputs (A to tI) and the corresponding outputs (18 to 14) for each
command. A+PLUS software translates the SMF into a standard JEDEC
file for programming the EP610 EPLD.
To further simplify design entry, the Equations Section of the EPS448
design file can define each of the commands in terms of the inputs 18 to 14
as shown by the three sample equations here:

ERROR
BACK
FORWD1

/14 */13 */12 */11 * 18;
/14 */13 */12 */11 * 18;
/14 */13 */12 */11 */18;

With these equations, branching within the EPS448 device can then be
expressed as follows:

S8: IF ERROR THEN Sl
IF BACK1 THEN S2
IF FORWARD1 THEN S3
S6

I Altera Corporation

Page 471

I

I Input Reduction lor the EPS448 SAM EPLD

Application Brle'66

I

Figure 6. Truth Table Entry for the EP610
Truth table entry is easy: the 13 inputs (A to M) are listed on the left, and the 5 outputs (10 to 14) are listed on the right
PART: EP618
INPUTS:
A, I, C, D, E, F, G, H, I, J, X, L, 11
OUTPUTS:
18, 11, 12, 13, 14
NET"ORX:
CONF(JB,)
CONF( 11,)
CONF(J2, )
CONF(J3, )
CONF(J4,)

IB

11
12

13
14

T_TAI:
SYSTEI1 INPUTS

'"
A
B
1
1
1
1
1

I
X
B
1
1
1
1

C
X
X
8
1
1
1

D
X
X
X
8
8
B

E
X
X
X
B
8
B

F
X
X
X
B
8
1

G
X
X
X
B
1
B

1

1

1

8

8

1

1

1
1
1
1
1

1
1
1
1

1
1
1
1

B
B
B

1
1
1
1

1
1
1
1

1

1

8

X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X

1
1

1
1
1
1
1

1
1

1
1

8

1

1

B

1

1

8

1
1
1
1
1

1
1
1

B
1
1
1
1

1
1

H
X
X
X
X
X
X
X
B
B
1
1
X
X
X
X
X
X
X
X

I
X
X
X
X
X
X
X
B

1
8

1
X
X
X
X
X
X
X
X

OUTPUTS

J
X
X
X
X
X
X
X
X
X
X
X
B
B

1
1
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
B
1
B
1
X
X
X
X

L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B
B
1
1

11
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

8
1
B
1

14 13 12

COI1MAND

'"

1 IB

'"
"
"
""
"
"
'"
'"
"'"
"
"
"
"
"
"
"
Yo

IDLE
ERROR
RESET
IACXl
RIGHTI
LEFTI
FORUDI
IACX2
RIGHT2
LEFT2
FORUD2
IACX3
RIGHT3
LEFT3
FORUD3
IACX4
RIGHT4
LEFT4
FORUD4

'"
"
"
"
"
'"
"'"
''""
"
'"
"
"
"
"
""
Yo

ENDS

IPage 472

Altera Corporation

I

I Application Brief 66
Final Tips

Input Reduction for the EPS448 SAM EPLD

o

I

Truth tables used for input encoding must not conflict with specified
output values. Such conflicts occur when an input combination satisfies
the input conditions for two rows in the table, but each specifies
different output values. Such conflicts are usually introduced by
injudicious use of don't care (X) values in truth table definitions.
Table 3 shows an example in
Table 3. Invalid Truth Table
which X values create
contradictory rows. If the input
A
B C
OUll
OUT2
combination (/A * B * C) were
0
X X
1
0
applied to the truth table, it
1
X
1
0
0
would satisfy the first row, which
1
X 0
1
1
specifies that OUTl should go
high, as well as the second row,
which specifies that OUTl should go low. Because OUTl has
conflicting val ues for this inpu t combina tion, the tru th table is invalid.

o

If an invalid truth table is used in an input-encoded EPS448 design,
undefined state transitions may occur. The SAM Design Processor
treats X entries as true (for minimization purposes), and therefore
does not check whether rows are free from output conflicts.
Consequently, the designer must verify that the truth table is valid
and contains only mutually exclusive input conditions. Otherwise,
inadequately defined outputs may cause incorrect state branching.

o Input encoding is more suitable than input multiplexing for speedcritical applications because it does not require any feedback from the
EPS448 EPLD. Input multiplexing, on the other hand, requires that
outputs leave the EPS448 device, propagate through an EP-series
EPLD, and still make the setup time of the EPS448 before the next
clock edge.

o

If inputs to an EPS448 SAM EPLD are asynchronous, they must be
synchronized by placing registers in front of the inputs. Since input
reduction typically places an EP-series EPLD in front of the EPS448,
synchronization is easily accomplished by using registered rather
than combinatorial outputs from the EPLD.

o Some applications may need to combine input encoding and input
multiplexing. For example, an address decode signal can be used as
one of the inputs to the multiplexers in Figure 5. When the proper state
arrives, the decode signal is routed to the input of the EPS448 EPLD.

IAltera Corporation

Page 473

I

!'r:W
II!.

Notes:

A+PLUS Boolean Equation
Design Entry
Application Brief 71 I

October 1990, ver. 2

Introduction

Boolean equations are a standard design entry method for low-density
programmable logic. Altera's A+PLUS software offers a Boolean equation
design entry method with simple syntax rules, standard logic operators,
and added enhancements tha t take ad vantage of the ad vanced archi tectures
of Altera EPLDs.

ADF Syntax

Boolean design files are created in the Altera Design File (ADF) syntax
with an ASCII text editor (in non-document mode). The ADF is divided
into sections, many of which are defined by a keyword. A sample ADF is
shown in Figure 1.

Figure 1. Sample Altera Design File (ADF)

i

Y::~ ~~~;an~

Header
Section

" COMMEI'ITS ARE EttCLOSED Itt PERCEttT SYMBOLS "

t~~~/9B

B

EP61B

Beverage Dispenser Controller

Options ~
Section ~PTlOttS:

TURBO

r~

Part
__
Section ----CART: EP61B
Inputs ----.r-;
Section ---CI'lPUTS: EI'IABLE@?

Out~uts -----loUTPUTS:

Section

OFF

4

!

" TURBO & SECURITY DEFAULT
" TO 'OFF'

"
"

COII'IDROP. CUPFULL. CLOCK

DROPCUP@15. STROBE. POURDRI'IK

---c

Network
Section

OFF. SECURITY

•

ttETUORK:
" ' - - - - - - - - - - " USER-ASSIGI'IED PII'I I'IUMBER
EttABLE = II'IP (EI'IABLE)
" CLOCK. CLEAR. AHD OUTPUT
" EHABLE OF ALL FLIP-FLOPS
COlttDROP = IttP (COlttDROP)
CAH BE COttTROLLED UITH
CUPFULL = IttP (CUPFULL)
,
" BOOLEAH-DERIVED SIGHALS.
CLOCK = II'IP (CLOCK)

r--- "

DROPCUP. DROP CUP

"
"
X

x
"

= RORF (DROPCUPd. CLOCK. HEUCYCLE. GttD. EHABLE)
= RORF (POURDRKd. CLOCK. HEUCYCLE. GND. EttABLE)

POURDRttK. POURDRI'IK

STROBE = COI'IF (STROBEc)
EQUATlOI'IS: .......
.._-----------

Equations
Section

DROPCUPd

=

CUPREADY
POURDRKd

= DROPCUP • /POURDRttK;
= CUPREADY + /CUPFULL •

STROBEe
ttEUCYCLE

=

TEMP

COII'IDROP • /DROPCUP • CUPFULL;

~
TEMP;

~ :TK~~~O::c~~~~It~EO~H~~:ED ~
x THE LIHE
'"
" INTERMEDIATE EQUATION
" OPTION

"'.v

,.

= CUPREADY

+ TEMP;
DROP CUP • POURDRI'IK;

= /DROPCUP

• POURDRttK;

End
-----fEItD$
StatementL

Altera Corporation

Page47S\

1m
I

I A+PLUS Boolean Equation Design Entry

Application Brief 71 I

ADFs can be processed indi vid uall y or combined wi th state machine, truth
table, schematic, and netlist files. The Altera Design Processor (ADP)
checks the syntax, performs logic minimization, fits the design into an
appropriate EPLD, and produces a JEDEC file for device programming.

Header Section
The optional Header Section of the ADF includes all ''bookkeeping''
information, such as design title, revision number, designer, and any other
desired information. It has no effect on design processing. This section has
no keyword.

Options Section
The Options Section (keyword OPTIONS:) controls the Turbo Bit and
Security Bit.

Part Section
The Part Section (keyword PART:) specifies the target EPLD. If the AUTO
option is used, A +PLUS automatically selects the best EPLD for the design.
If pin assignments are specified in the ADF, the AUTO option is not
available, since the assigned pins must necessarily correspond to a particular
EPLD and package.

Inputs Section
The Inputs Section (keyword INPUTS:) specifies all EPLD inputs for the
design. Pin numbers can be assigned by appending an "at" symbol (@ ) plus
the pin number to the end of the pin name.

Outputs Section
The Outputs Section (keyword OUTPUTS:) declares all output and
bidirectional pins used in the design. Output pin numbers are assigned in
the same way as input pins. (Bidirectional pins are never declared in the
Inputs Section.)

Network Section
The Network Section (keyword NETUORJC:) defines the programmable I/O
architecture of the EPLD and provides access to all advanced I/O
architecture features (e.g., programmable flip-flops).

IPage 476

Altera Corporation

I'

I Application Brief 71

A+PLU5 Boolean Equation Design Entry

I

Equations Section
The Equations Section (keyword EQUATIONS:) contains the Boolean
equations, which use standard operators (AND = * or &; OR = + or #;
NOT = /, " or!) to implement the desired function. Equations need not be
in sum-of-products form; parentheses are used to indicate grouping and
establish precedence. Intermediate equations are also supported to simplify
design entry.

End Statement
All Altera Design Files must end with the END$ statement.

Additional
Features

The ADF format can implement dual I/O feedback and active-low inputs
and outputs.

Dual Feedback
The dual-feedback capability of the EPl800-series global macrocells is
implemented by declaring the buried logic in the Outputs Section, and the
dedicated input in the Inputs Section. The following example shows a
buried register and input pin implemented with the same macrocell:
PART: EPl8l8
IHPUTS: DUALl@l8
OUTPUTS: DUAL2@l8
HETUORK:
DUALl = IHP(DUALl)
DUAL2 = HORF(DUAL2d.CLK.CLR.GHD)
EQUATIOHS:
DUAL2d

A· B + C;

EHD$

If Output Enable control is required, the following syntax is used:
PART: EP18l8
IHPUTS: DUALl
OUTPUTS: DUALl
HETUORK:
DUALl = IHP(DUALl)
DUALl. DUALlf = RORF(DUALld.CLK.CLR.GHD.OE)
EQUATIOHS:
DUALld
OE

IE

A. B + C;
D • E;

EHD$

I Altera Corporation

Page 477

I

I A+PLUS Boolean Equation Design Entry

Application Brief 71

I

Active-Low Inputs
Active-low inputs are specified by inverting the signal in either the Network
or Equations section.

o

Active-low input specified in the Network Section:
INPUTS: I'X

x The

"1'"

character has no lo,ical "eanin, in the X

X INPUT section X

NETI.IORK:
Xn = INP (l'X)
X = NOT(Xn)
X X is the internal active-low si,nal X

o

Active-low input specified in the Equations Section:
INPUTS: I'Y
NETI.IORK:
Yn = INP(I'Y>
EQUATIONS:
Y = I'Yn;
Yo Y is true when input si,nal I'Y is low Yo

Active-Low Outputs
Active-low outputs are specified by inverting the left-hand side of the
equation. If active-low outputs are required by a sequential function, the
feedback nodes must also be inverted. For example:
PART: EP638
INPUTS: CLOCK
OUTPUTS: I'QC. I'QB. I'QA. I'RCO
Yo The "1'" character has no lo,ical Meaning in the X
X OUTPUT section X
NETI.IORK:
CX
INP(CLOCX>
I'QA. QAf
RORF(QAd.CK ••• >
I'QB. QBf
RORF(QBd.CK ••• >
I'QC. QCf
RORF(QCd.CK ••• >
COttF(RCOc.)
I'RCO
Yo Unspecified arguMents in "RORF( •••••• >" assu"e Yo
Yo default values Yo .
EQUATIONS:
QA
I'QAf;
Yo Invert feedback nodes Yo
QB = I'QBf;
QC = I'QCf;
RCOc' = QC • QB • QA;
X Invert left-hand side of e.uation X
QCd'
QC· QA' + QC • QB' + QC·· QA • QB;
QBd'
QB. QA' + QB·. QA;
QAd'
QA' ;

ENDS

I Page47S

Altera Corporation

I

EPM5000-Series
MAX EPLD Timing
October 1990, ver. 2

Introduction

Application Brief

751

The advanced technology of Altera's Multiple Array MatriX Erasable
Programmable Logic Devices (MAX EPLDs) and the sophisticated
MAX+PLUS Development System have made CMOS programmable logic
much easier to use. Complex logic designs can be implemented with a
single EPM5000-series EPLD. In addition, the MAX+PLUS Simulator and
delay prediction feature can identify critical delay paths and find each
path's worst-case delays, which are the sum of discrete component delays
inherent in the EPM5000-series architecture.
This application brief discusses these internal delay paths, their relationships
to AC specifications (shown in the MAX EPLD data sheets), and the calculated
timing delays generated by MAX+PLUS. In addition, timing models for
analyzing delays calculated by the MAX+PLUS, and equations that are
used to calculate the delays are discussed.

MAX EPLD
Architecture
Basics

To accurately model timing characteristics, a designer must understand
how logic is implemented in a MAX EPLD. EPM5000-series architecture is
based on a flexible Logic Array Block (LAB), which consists of three parts:
the macrocell array, the expander product-term (expander) array, and the
I/O control block. The number of macrocells, expanders, and I/O control
blocks varies, depending on the device used. Large EPM5000-series EPLDs
contain multiple LABs that are interconnected by a Programmable
Interconnect Array (PIA). The PIA is fed by macrocell and I/O pin feedback,
and globally routes signals within devices containing more than one LAB.
All gated and registered logic is implemented in macrocells and expanders.
The expander product-term array and the macrocells contain product terms
that are n-input AND gates (where n represents the number of connections).
Depending on the implemented logic, a product term may be logically
equivalent to one or more gates. (Refer to the EPM5016 to EPM5192: HighSpeed, High-Density MAX EPLDs Data Sheet in this data book for more
informa tion.)

Macrocell
Array

The macrocell structure of EPM5000-series EPLDs, shown in Figure 1, has
been optimized to handle variable product-term requirements. Each
macrocell consists of a programmable-AND/fixed-OR array, an XOR gate,
a configurable register, and a number of inputs (varying from 80 to 152).
Together, they allow EPM5000-series EPLDs to integrate complex logic.
Combinatorial logic is implemented in the macrocell with three product
terms ORed together that feed the XOR gate. The second input to the XOR

Altera Corporation

Page 479

I

mJI

I EPM5000-5eries MAX EPLD Timing

Application Brief 75

I

Figure 1. Macraeell A"ay
Output Enable

System Clock

Preset

r---pRN"

Array Clock

I

y-~~~-

to 1/0
Control
Block

Clear

... Macrocell Feedback
So.

~

'"

~

"/I

I

Expander
Dedicated Programmable
Inputs
Interconnect Product Terms
Signals

1

Note: One
system clock
per LAB

Macrocell
Feedbacks

gate is also controlled by a product term, providing the ability to control
active-high or active-low logic. MAX+PLUS uses this gate to implement
complex, mutually exclusive-OR logic, or to apply De Morgan's inversion,
reducing the number of product terms required to implement a function.
The macrocell also includes additional product terms (secondary product
terms) that are used for Output Enable, Preset, Clear, and Clock logic. If
more product terms are required to implement a function, they can be
added to the macrocell from the expander product-term array.
The macrocell's AND array is an EPROM array; each product term
generated by the AND array is a function of the EPROM bits within the
array. The EPROM bits, initially erased, serve as electrical switches for the
array inputs. An erased bit enables an input to reach a product term, while
a programmed bit prohibits an input from reaching a product term. A
product term is thus a function of inputs connected by unprogrammed, 11\1
non-erased EPROM bits.
The configurable register within a macrocell can be programmed for 0, T,
JK, SR, or flow-through operation with independent, programmable Clock,
Reset, and Preset options. It can also be bypassed entirely for purely
com bina toriallogic.

I Page 480

Altera Corporation

I

I Application Brief 75
Expander
Product-Term
Array

EPM5000-Series MAX EPLD Timing I

Addi tional product terms, called expanders, rna y feed the macrocell array's
product terms to generate very complex Boolean logic. The expander
product-term array, shown in Figure 2, is a programmable AND array
with inversion. Expanders are fed by the dedicated input bus, the PIA, the
macrocell feedback, expanders themselves, and the I/O pin feedbacks. The
outputs of the expanders then go to each product term in the macrocell
array. Since these expanders also feed the secondary product terms of each
macrocell (Preset, Clear, Clock, and Output Enable), complex registercontrol functions can be implemented without using another macrocell.

Figure 2. Expander Product-Term Array
Expander product terms are unallocated resources that can be used for registered or combinatorial logic.

to Macrocell Array
and Expander Product
Term Array

Macrocell Feedback

Dedicated Macrocell
Inputs Feedbacks

Expander Programmable
Product Terms Interconnect
Lines

These expanders are used and shared by the macrocells, allowing com plex
functions to be easily implemented in a single macrocell. Expanders may
also feed other expanders, so that complex multi-level logic and input
latches can be implemented. As illustrated in Figure 2, the expander
product-term array contains an AND array followed by inversion. It may
supply from 32 to 64 additional product terms per LAB. Large MAX
EPLDs (EPMS192, EPMS130, EPMS128, and EPMS064) provide up to 32
expanders per LAB; smaller MAX EPLDs (EPMS032 and EPMS016) provide
64 and 32 expanders, respectively. Inputs into the expander product-term
array also vary from 144 to BO.

Altera Corporation

Page 481 I

ml

I EPM5000-Series MAX EPLD Timing

Application Brief 75

I

1/0 Control
Block

In the LAB, the I/O control block is separate from the macrocell array. It
contains programmable tri-state buffers and I/O pins with optional
feedbacks. Each I/O pin can be configured for dedicated input, dedicated
output, or bidirectional operation. The input of the tri-state buffer comes
from a macrocell within the associated LAB. The feedback path from the
I/O pin can feed other macrocells within the LAB, as well as the PIA.

Programmable
Interconnect
Array

The EPMS192, EPMSl30, EPMS128, and EPMS064 MAX EPLDs have
multiple LABs connected by a Programmable Interconnect Array (PIA)
that globally routes all signals. The PIA avoids interconnect limitations by
routing only the signals needed by each LAB, effectively solving any
routing problems that may arise in a design. In addition, the PIA has a
fixed delay from point to point. The PIA delay is constant because each
signal that feeds into the PIA has its own dedicated metal line with
multiple taps, one for each LAB. Undesired skews between logic signals,
which may cause glitches in internal or external logic, are eliminated.

EPLD Delay
Parameters

Internal delays within an EPLD are described by a number of AC parameters
(called microparameters) that refer to the actual internal delay within the
device. Figure 3 shows the timing model for single-LAB devices.

Figure 3. EPM5032 / EPM5016 Timing Model

r----+---II...

Expander Delay

tExP
Logic Array
Control Delay

Delay
Input

tIN

r-ll1E==~~tLA§C~~
.-++-t--t~

Logic Array Delay
tLAD

System Clock Delay

1/0
Delay

Register

Output
Delay

110 Pin

too

txz
tzx

Clock Delay
tiC

t,o

Figure 4 shows the timing model for multiple-LAB devices. Following is a
list of these microparameters and examples of how to predict timing
delays with equations that use them.

I Page 482

Altera Corporation

I

I Application Brief 75

EPM5000-Series MAX EPLD Timing I

Figure 4. EPM5192 / EPM5130/
EPM5128/ EPM5064 Timing Model

~

r---

~

~

Input
Delay

4N

~

E~"dwD.~ ~
IEXP

Logic Array
Control Delay

L...-

r---

~

PIA
Delay

IPRE

Logic Array Delay

~
IH

Register

!'"
~

Clock Delay

'IC

Output
Delay

'RO

'COMB
'LATCH

System Clock Delay
l:

Ir~

CLR

t LAC

t LAO

,

I

IICS

~~

'00
'XZ

Outpu

~

'ZX

~

Feedback Delay
'FO

110 Delay

1'0

-

tIN

Input pad and buffer delay. This delay directs the true and
complement input signals from the dedicated input pin into the
LAB. Within the LAB, the signals may propagate to any of four
arrays: expander product-term array, logic array, logic array control,
and clock array.

tlO

I/O input pad and buffer delay for I/O pins used as inputs. The tlO
delay value must be substituted for tIN for the EPM5032 and EPM5016.
When an I/O pin is used as an input, the tlO delay value must also be
added to tpIA to obtain the total delay from the I/O pin to the LAB
for the EPM5192, EPM5130, EPM5128, and EPM5064.

t EXP

Expander product-term array delay. This is the delay through the
AND-NOT structure of the expander product-term array. It is added
to the delay already present in the four arrays when expanders are
used, or added to itself when an expander feeds another expander.

tLAC Logic array control delay. This is the delay through the AND array
by Clear, Preset, and Output Enable signals, representing the time
required to propagate through the AND array to the CLRN and PRN
inputs to the register, and the OE signal to the tri-state buffer.
tCLR

Asynchronous register clear time, which represents the time required
to reset a register output to a logical low. It is the time the register
CLRN input is asserted low to the time the register output stabilizes
at logical low.

tPRE Asynchronous register preset time. This delay represents the amount
of time required to set a register output to a logical high. It is the time
the register PRN input is asserted low to the time the register output
stabilizes at logical high.
Altera Corporation

Page 483 I

1m
I

I EPMSOOO-Series MAX EPLD Timing

I Page 484

Application Brief 7511

tLAD

Logic array delay. This is the time a signal requires to propagate
through a macrocell's EPROM AND array, the three-input OR
gate, and the two-input XOR gate.

tICS

System clock delay. This is the delay from the dedicated clock pin
to a register's clock input.

tIC

Clock delay. This is the delay through a macrocell's clock product
term to the register clock input.

trD

Feedback delay. For the EPM5032 and EPM5016, this delay is the
propagation time from macrocell output to any of the LAB's four
arrays. For the EPM5192, EPM5130, EPM5128, and EPM5064, it is
the propagation time from a macrocell output to any of the LAB's
arrays, or the propagation time from a macrocell output to a PIA
input or other macrocells in the LAB.

tsu

Setup time required for a signal to be stable at the register input
before the clock's rising edge.

tH

Hold time required at the register input after the register clock's
rising edge to ensure that the register stores the input data.

tRD

Delay from the register clock's rising edge to the time that output
appears at the register output.

tCOMB

Combinatorial buffer delay, which is used only for combinatorial
logic. This is the delay from the time the logic array's XOR output
bypasses the programmable register to the time it becomes available
for the macrocell output.

tLATCH

Propagation delay through the latch from latch input to output.

taD

Output pad and buffer propagation delay from the macrocell
output through the tri-state output buffer to the output pin.

txz

Delay required for high impedance to appear at the output pin
after the output buffer's active-high enable control is brought
logically low.

tzx

Delay required for the macrocell output to appear at the output
pin after the output buffer's active-high enable control is brought
logically high.

tpIA

Programmable Interconnect Array delay for multiple-LAB devices.
This delay is used for EPM5192, EPM5130, EPM5128, and EPMS064
designs that use the PIA for routing. The PIA delay path starts
where the macrocell feedback or I/O delay path ends, and ends
where it enters the LAB and reaches any of its four arrays.
Altera Corporation

I

I Application Brief 75

EPM500D-Serles MAX EPLD Timing

I

Critical pin-ta-pin delays (denoted by a boldface t) are shown in Figure 5.
Figure 5. Critical Pln-to-Pln Delays
Notes:
1. If an 110 pin is used for an
input:
a. for EPM5032 and
EPM5016, substitute t,o
for tN,
b. for EPM5192, EPM5130,
EPM5128, and
EPM5064, substitute
I/O + tplA for tN,
2. If expanders are used for
complex logic, add IEXP to
the delay path.

~

~

Combinatorial
Logic

~-----1

L..------=---.I

,.. tIN

_, ..

too

tCOMB

tLAD

tP01 - t,N + tLAD + tCOMB

+ too

~ Combi~torial 11--__--.
~
Logic.
~
, ..

tIN _ ,_

txz or tzx

tLAC

tpxz. tpzx ... t,N + tLAC + (txz or tzx)

I Combin~torial ~

_

~
,.

tIN

_ 1•

~

LogiC
tLAC

_ ,.

~!

. ,..

too _,

tpRE. tCLA ... till + tLAC + (tpRE or tCLR ) + too

,.

tIN . , .

,..

tIN

tLAD

-I.

• ,•

tsu _,

t,CS

... ,

tsu = (t,N + tLAD ) - (till + tICS) + tsu

:=1
,.

,.

tIN . , .

tIN .,..

tLAD

_ ,_ tH

com~~ooal
t,CS

I

_,

r=O
_,

tH = (till + tICS) - (tIN + tLAD) + tH

Critical pin-ta-pin delay calculations are shown in Figure 6. The calculations
used to derive these values from the microparameters listed in the MAX
EPLD data sheets are shown for each path. These calculations assume that
a dedicated input pin is used.
If the input comes from an I/O pin, flO is substituted for the tIN value. For
multiple-LAB EPLDs that use an I/O pin as an input, flO + fPIA is
substituted for the tIN value. If an expander is used in the path at any time,
the t EXP value must also be added to the total delay path.

I Altera Corporation

Page 485

I

I EPM5000-Series MAX EPLD Timing

Application Brief 75

I

Figure 6. Critical Pin-Delay Calculations

=Q-i

Notes:
1. If an 110 is used for an input:
a for EPM5032 and
EPM5016, substitute tlO
fort",.
b. for EPM5192, EPM5130,
EPM5128, and EPM5064,
substitute t/O + tplA for t",.
2. If expanders are used for
complex logic, add tEXP to the
delay path.

Combinatorial
Logic

--=-----.I

tCNT
tACNT

'II

z

-

tLAO

fRD + tFD + tLAO + tsu
tRO + tFO + tLAO + tsu

..,

tIN _ , ..
tASU

= (tIN + tLAo) - (tIN + tIC) + tsu

tNt = (tIN + tIC) - (tIN + tLAo) + tH

0

,...

tIN
tAc01

I
..,

Combinatorial
Logic

= tIN

+ tIC + tRO

tIN
tCOl

Examples

-,= tIN

too

+ tOD

==Q--c>

c::>

,-

I ==Q--c>
a,1I _,_ a'
tRD

tIC

..

tICS

+ tICS

a' ..tRD_,,,tooa'

+ tRO + too

The MAX+PLUS Simulator and the delay prediction commands in the
MAX +PLUS Graphic Editor and Text Editor can identify timing delays for
any circuit. These delays may be separated into the microparameters
already described and are provided in the MAX EPLD data sheets.

Example 1: 4-to-1 Multiplexer
The design shown in Figure 7 represents a 4-to-l multiplexer, which is a
combinatorial circuit. The circuit consists of four data inputs, two select
controls, and one output. It is partitioned into four delay paths: input
delay, logic array delay, combinatorial buffer delay, and output delay.

I Page 486

Altera Corporation

I

1

Application Brief 75

EPM5000-5eries MAX EPLD Timing

Figure 7. 4-1 MUX Logic Timing

1

This circuit can be partitioned into 4 delay paths: input delay, logic affay delay,
combinatorial buffer delay, and output delay.

Input delay will be t", if only dedicated
inputs are used. If 110 pins are used, the
input delay will be t/O for the EPM5032 and
EPM5016, and t/O + tplA for the EPM5192,
EPM5130, EPM5128, and EPMS064.

81
/.:::.JI--""";

82
c:>--ri--i

The propagation delay for combinatorial
logic that bypasses the programmable
register is tcOMB' For output data, the
output pad and buffer delay is too- The
overall propagation delay is lpo1 for all
dedicated inputs and lpo2 when any 110 pin
is used for input.

The propagation delay from input pin to I/O pin is the sum of the input
delay, logic array delay, combinatorial buffer delay, and output delays:
tIN + tLAD + tCOMB + tOD' This worst-case delay is also known as tpOt (from
input pin to output pin) or as tp02 (from I/O pin to output pin). The
maximum tpOt and tpo2 values are shown in the individual MAX EPLD
data sheets, or may be determined with the follOwing equations.
For EPM5000-series EPLDs without a PIA:
tpOt

= tIN + tLAD + tCOMB + tOD

tp02

= tlO + tLAD + tCOMB + tOD

For EPM5000-series EPLDs with a PIA:
tpD2

= tlO + tPIA + tLAD + tcoMB + tOD

Example 2: 7483 TTL Macrofunction
The timing delays for macrofunctions subjected to logic synthesis can also
be analyzed. The synthesized logic equations can be obtained from the
"long" version of the Report File and have been structured so that a
designer can quickly determine the logic configuration. (Refer to Report File
in theMAX+PLUS User Guide.) For example, the equations for S1, the least
significant bit of the 7483 TTL macrofunction (a 4-bit full adder), are:
OUTPUT <_MC021 , UCC);
MCELL <_EQ026 $ C0);
Bl & Al'
B1' & A1 ;
1

Altera Corporation

Page

4871

!fit
11:.1

I EPAf5000-Series MAX EPLD Timing

Application Brief 75

Rgure 8. Adder Logic Timing

I

where SI is the output of macrocell 21
(_I1C821), which contains combinatorial
logic. The combinatorial logic,
I1CELL(_EQ826 $ C8), represents the
XOR of the intermediate equation
(_EQ826) and the carry-in (C8). In turn,
_EQ826 represents logic equivalent to
the XOR of inputs, Bland AI. See
FigureS.

A1
B1

co

Therefore, the timing delay for SI is tIN +
tLAD + tCOMB + taD' which is equal to t pD1 •

Example 3: 52 Adder Bit
For complex logic that requires expanders (represented here by _X ... ), the
expander-array delay, t EXP ' is added to the delay element. For instance,
S2, the second bit of the full adder, requires expanders. The equations are:
S2
_MC819
_EQ823
_X829
_X838
_X831
_EQ824
_X832
_X833

= _MC819;
MCELL( _EQ823 $ _EQ824
_X829 & _X838 & _X831;
EXP( !Bl & !Al ) ;
EXP( !Bl & !C8 ) ;
EXP( !Al & !C8 ) ;
_X832 & _X833;
EXP( !B2 & A2 ) ;
EXP( B2 & A2 ) ;

) ;

Using these equations, the logic structure can be mapped onto the MAX
architecture, as shown in Figure 9.
Figure 9. Adder Equation Mapped to EPMSOOO·Series MAX Architecture
.X029'
.X030'
.X031 ,

.X032'
.X033'

co

~_-'

A1

B1

A2.
B2

IPage 488

Altera Corporation

I

I Application Brief 75

EPM5000-Series MAX EPLD Timing

The overall delay for S2 is equivalent to tIN + tEXP + tLAD + tCOMB + t OD ,
which is equal to tEXP + t pD1 •

Example 4: Asynchronous 4-Bit Counter
The example shown in Figure 10 evaluates an asynchronous 4-bit counter.
The counter has one logic-controlled clock input (CLIO and the following
outputs: RCO, QD, QC, QB, and QA. In addition, it has five inherent delays
associated with registered logic (clock delay, input delay, array delay,
feedback delay, and output delay) as well as setup time and hold time
requirements for each register.
The propagation delay from input pin to the clock input of the register for
the least significant bit QA is tIN+ tIC (see Figure 10). If an I/O pin is used for
input, the propagation delay from the I/O pin to the register's clock input
is tlO + tIC, or tIO + tpIA + tIC for MAX EPLDs with multiple LABs. Since the
delay from register to output pin is tRD + t OD ' the total clock to output
delay is tIN + tIC + tRD + tOD for dedicated input to output; tlO + tIC + tRD +
tOD for I/O pin to output for EPM5000-series EPLDs with one LAB; or
tlO + tpIA + tRD + tOD for I/O pin to output for EPM5000-series EPLDS with
multiple LABs.
In addition, data input to the register must meet both setup and hold time
requirements. The internal setup time is the time needed for the input data
to stabilize before the triggering edge of the clock appears at the register
input. The external setup time is the difference between the sum of the
input, logic array, and setup time, and the sum of the input and clock
delay: (tIN + t LAD ) - (tIN + tIC) + tsu. When expanders are used, t ExP must
be added, and when I/O pins are used, tlO or (tlO + t pIA ) must be added. As
long as the external setup time is met at the inputs, the counter functions
properly.
The maximum internal counter frequency (fCNT) is the inverse of t CNT '
which is the worst-case delay for internal feedback. This frequency is the
minimum internal clock period at which the counter can operate correctly.
The delay is the sum of delay paths that the register feedback must
traverse before reaching a register input and meeting the internal setup
time: (t RD + tFD + tLAD + t su ). Once the clock triggers QB, data takes tRD
delay prior to appearing at the register output. The signal feeds back (tFD )
and flows through the logic array (t LAD). Finally, the signal reaches the
register QC and meets the setup time of the register (t su ).
When expanders are used, t EXP must be added as the signal passes through
the expander array before reaching the logic array. The tCNT delay
represents only internal circuit delays, while a circuit that depends on
external and internal signals must also account for input and I/O delays.

/ Altera Corporation

Page489/

I

I EPM500O-Series MAX EPLD Timing

Application Brief 75 I

Figure 10. Timing
Analysis of 74161

Counter
OUTPUT
~~--+-----C>

~~--

OA

OUTPUT
__----C> OB

OUTPUT
O~--~~-----C~OC

OUTPUT
QI---"**"---t:::::> aD

Conclusion

I Page 490

MAX+PLUS development tools offer the ability to determine timing delays
within MAX EPLDs. Delay prediction and simulation allow the designer
to analyze the delays for a given design. The designer may also wish to
hand-calculate these paths before entering the design. To understand
timing relationships in MAX EPLDs, the designer must think of the total
delay path in terms of the microparameters listed in the target EPLD data
sheet. From these AC values, it is easy to determine accurate timing delay
informa lion by adding up the appropria te combination of microparameters.
Altera Corporation

I

Using Expanders
to Build Registered Logic
in EPM5000-Series MAX EPLDs

I October 1990, ver. 2

Application Brief 76\

Introduction

EPMSOOO-series MAX EPLDs are high-density, user-configurable devices
with up to 192 macrocells. Each macrocell contains one register that can be
programmed for registered functions or bypassed for combinatorial
functions. Since applications sometimes require more registers than are
available in the macrocells, extra registers can be built with expander
product terms (expanders). Expanders are unallocated product terms used
to build complex combinatorial functions or latches and registers. This
application brief explains how and when to use expander latches and
registers, and describes timing considerations, specifically for an SR latch, a
transparent D latch, and a synchronous register. Familiarity with EPMSOOOseries MAX architecture and timing models is assumed.

Expander
Product
Terms

EPMSOOO-series architecture provides expanders with inverted outputs that
feed the logic array. Each expander is fed by the same inputs that feed the
macrocell: a global bus, macrocell feedbacks, other expanders, and I/O
feedbacks. Since expanders feed themselves, they can be used to build
latches and registers. Two expanders (EXP primitives) can be cross-coupled
to generate an SR latch, three can be used to build a transparent D latch, and
six can be used to build a synchronous D flip-flop with asynchronous Preset
and Clear. The expander circuits described here have been built into
macrofunctions to optimize performance. Each function is built with AND
gates and EXP primitives to optimize fitting.

Asynchronous
SR Latch

Figure 1 shows an asynchronous SR latch implemented with two expanders.
Since expanders are product terms with inverted outputs, the latch is a
NAND implementation that makes the Set and Reset terms active low. If
both inputs are simultaneously low, both outputs will become logic low
until one or both of the outputs go high again.
Figure 1. SR Latch Implemented with Expanders
EXP.1
IS

IR

I Altera Corporation

L-.._------i

t - - - - - - i .:>C)--*-----t"=:> IQ

Page 491

I

I Using Expanders to Build Registered Logic In EPM5000-Serles MAX EPLDs

Application Brief

761

The functional output of an SR latch is shown in Table 1. To implement the
latch with active-high inputs, as in a NOR latch, the inputs are inverted
with NOT primitives. AsynchTable 1. Functional Output of SR
ronous SR latches are often used to
Latch
debounce input-switching circuits
or to detect edges· in switching
Q
IS
IR
circuits.

SR Latch
Timing

H
H
00
Each expander has a timing delay
H
L
H
defined as t EXP' When im pleL
H
L
menting latches and registers with
H (1)
L
L
an expander, it is important to be
aware of the timing requirements
Note:
to ensure that the expander
(1) IS and IR low causes both Q
and IQ to be high.
functions properly. The hold time
for the SR latch shown in Figure 2 is
tHo A low signal at the S input must remain low long enough to propagate
through Expander 1 and Expander 2 to latch the input. The propagation
delay from the latch input to the latch output is teo. A low at the S input
must travel through Expander 1 and Expander 2 before the outputs 0 and
/0 become valid.

Figure 2. SR Latch Timing Model
IS c::::;~I:..:..:.NP-=U;..:..T_ _-I

IR

Expander
t - tEXPI

t--..----{~

OUTPUT

Expander
t - tEXP2

INPUT

a

IQ

SR Latch Timing Equations

tH
t

Transparent
D Latch

Page 492

co

tEXP1

+

tEXP2

2

* tExP

tEXP1

+

tEXP2

2

*

tExP

The transparent asynchronous 0 latch with EN (Enable) is implemented
with three expanders, as shown in Figure 3. This latch is comparable to a
74LS373, and is transparent while the EN signal is at a logic high. When EN
goes low, the input is latched until EN goes high again. This latch is
especially applicable for latching inputs from a bus. The functional
output of this latch is shown in Table 2.

Altera Corporation

I

IApplication Brief 76

Using Expanders to Build Registered Logic In EPMSOOO-Ser/es MAX EPLDs

I

Rgure 3. Transparent 0 Latch

EN
OUTPUT

;o.-e----l~

a

D

Transparent
D Latch
Timing

The timing paths for the transparent
asynchronous D latch are shown in
Figure 4. The tH value for this circuit
is 0 ns because the paths from the D
input and the Eft input have delays
equal to those of Expander 3, which
latches the result. The setup time,
tsu, requires the D input to go
through Expander 2 and Expander
3 to reach Expander 1 before it can
be latched. The delay through
Expander 2 and Expander 3 to the
output is teo.

Table 2. Functional Output of

oLatch
EN

0

Q

L

L

L

H

00
00

H

L

L

H

H

H

Rgure 4. Transparent 0 Latch Timing Model

EN

INPUT

.----:>----+---t

Expander
t= tExPt

"'---------'

Expander
t - tEXP3

D

INPUT

Expander
t- t EXP2

Transparent 0 Latch Timing Equations

tH

0

t su

tEXP2

+

tEXP3

t co

IAltera Corporation

Page 493

I

1

Using Expanders to Build Registered Logic In EPM5000-Serles MAX EPLDs

Synchronous
D Register

Application Brief

761

The function outputs for the synchronous 0 register are shown in Table 3.
A synchronous 0 register with asynchronous Preset and Clear (,1P and
,Ie) can be built with six expanders, as shown in Figure 5.
Table 3. Function OUtputs tor Synchronous Register
IC

IP

D

elK

Q

IQ

H

H

H

L

I

L

H

H

H

I

H

L

H

H

X

H

H

H

X

L

00
00

10 0

L

H

X

X

H

L

H

L

X

X

L

H

L

L

X

X

H

H

10 0

The state at the D input is clocked into the latch with a rising edge at the
clock input. Both the true and complement signals are available at the
output. This output remains latched until the next rising edge clock or
until the Preset or Clear is activated with a logical low signal. The Preset
and Clear can be made active high by placing NOT primitives in front of the
two signals. Using expanders as registers increases the total register count
by31 %. For example, the EPM5192 can have up to 60 registers implemented
with expanders, which gives it a total capacity of 252 registers.
Figure 5. Synchronous D Register with Preset and Clear

IC

EXP.1

INPUT

IP

INPUT

--~I>o-_~_-======r~~

cr-----r~~===L~r
I

__EXP.5
Do_-.._.£OUT~PUTb

Q

INPUT

CLK c::;>----+~~----I

o

Page 494

INPUT

A/tera Corporation

I

IApplication Brief 76

Using Expanders to Build Registered Logic in EPMSOOO-Series MAX EPLDs

,Synch ronous
,0 Register

The timing paths for the synchronous D register are shown in Figure 6.
Two different timing paths are determined by the D input, depending on
whether the input is high or low. The worst-case path is described here.
Before the input may be clocked, tH is one expander delay through
Expander 3. A valid path through Expander 4 and Expander 1 at the input
of Expander 2 is the worst case for f su. The time required for clock-tooutput (called t COl) has a worst-case path through Expander 3, Expander
6, and Expander 5 for both 0 and /0 to produce valid outputs. Both feLR
and fPRE have a delay path through Expander 5 and Expander 6 to produce
a valid output. The minimum time in which the register can be clocked in
a pipeline register is tCNT. In this case, tcNTis simply leol + tsu- The worstcase timing for the synchronous register is five expander delays.

'Timing

Figure 6. Timing Model for Synchronous 0 Register

INPUT

IP

INPUT
!C

OUTPUT

I - - -.......---c::> 10

INPUT

QK~----+~~--~

INPUT

o

Synchronous D Register Latch Timing Equations
H

tEXP2

or

tExP3

t su

tEXP1

or

tExP1

+

tEXP4

t

C01

tExP3

+

tExP6

or

tEXP2

+

tEXP5

t

CLR

tExP6

+

t

PRE

tEXP5

t

CNT

t

t

,IAltera Corporation

C01

tEXP

2

*

tExP

3

*

tEXP

tEXP5

2

*

tExP

+

tEXP6

2

*

tEXP

+

t su

5

*

tExP

+

tExP5

+

tExP6

Page 495

1m

Using Expanders to Build Registered Logic In EPMSOOO-Ser/es MAX EPLDs

Application Brief

761

Fitting
Expanders
into MAX
Designs

Expander latches and registers should be placed strategically within a
design to optimize fitting. Expanders are fed by three sources: inputs,
macrocell outputs, and other expanders. Complex logic should not feed
the inputs to expander registers, because other expanders are the only
source of this logic. Instead, registers driven by complex logic should be
placed in macrocells. On the other hand, registers that require additional
logic after the register should use expander registers, since the output
feeds directly into the logic within the macrocells.

Reference

All of the macrofunctions defined in this application brief are available via
modem from Altera's Electronic Bulletin Board Service (see the Electronic
Bulletin Board Service Data Sheet in this data book) or on disk from Altera
representatives. The files are named as follows: the SR latch is called
NANDLTCH.GDFI the transparent D latch is called EXPLATCH.GDF, and the
synchronous D register is called EXPDFF .GDF.

Page 496

Altera Corporation

I

I

I

Design Guidelines
for EPM5000-Series MAX EPLDs

1

October 1990, ver. 2

Introduction

Application Brief

771

MAX+PLUS software uses a combination of advanced logic synthesis
techniques and a heuristic fitter to efficiently map designs into MAX EPLDs.
The MAX+PLUS Compiler typically synthesizes even the most complex
designs in less than five minutes.
However, certain designs are more difficult to fit. These designs contain
very complex combinatorial logic or require more macrocells than are
available in the target EPM5000-series EPLD. The MAX+PLUS Compiler
uses logic synthesis techniques specifically developed to quickly fit these
designs. In most cases, MAX+PLUS can automatically fit even these complex
designs.
Sometimes designs require subtle modifications to enable the Compiler to
perform logic synthesis and obtain a fit. This application brief discusses
some of the synthesis techniques used to fit these complex designs and
explains the most common Compiler error messages.

Logic
Synthesis

The MAX+PLUS Compiler includes a Balancer program, which synthesizes
designs that require too many of a certain type of resource. The Balancer is
responsible for balancing the logical resources required by a design.
If a design contains too many macrocells for the specified MAX EPLD, the
Balancer can transform buried combinatorial macrocells into expander
product terms (expanders). It also resynthesizes designs containing too
many expanders by transferring logical expressions implemented on
expanders into macrocells. Up to three expanders may be transferred into
each macrocell. By balancing resource usage, the Compiler can fit designs
that originally require too many instances of a particular logical resource. In
this manner, most complex designs are automatically fitted.

1

Altera Corporation

Page 4971

I Design Guidelines for EPM500O-Series MAX EPLDs
Compiler
Messages

Application Brief

771

If a design is too large or complex, the Compiler generates an error
message specifying the problem and, if applicable, indicating the error
loca tion. The mos t common Com piler error messages relating to synthesis
and fitting of designs generally take one of the following forms:

o

Design requires too Man!;l  is the ratio
of macrocells in the design to the macrocells available on the EPLD.

o Logic too COMplex: for 1_NP_UT-.--t

INPUT

DCJ----------~~

--------------UI
If none of these techniques yields the desired fit, contact the Altera
Applications Department for assistance at 1 (BOO) BOO-EPLD. As a last
resort, logic may have to be removed from the design to achieve a fit into
the target device, or the design may have to be partitioned into two MAX
EPLDs. Call Altera's Applications Department for more information.

I Altera Corporation

page499!

1

Application Brief

Design Guidelines for EPMSOOO-5eries MAX EPLDs

Designing
Complex
Combinatorial
Functions

771

The MAX+PLUS Compiler generates error messages when a design's
combinatorial logic is too complex. This complexity can result from
cascading several combinatorial macrofunctions, such as adders and
com para tors, or from heavy use of XOR functions. Figure 2 shows complex
combinatorial logic caused by heavy use of the XNOR function.
To resolve Compiler errors related to complex combinatorial logic, one or
more SOFT or NCELL buffers can be inserted into a design to separate
complex combinatorial expressions. Placing a SOFT or I1CELL buffer
consumes a macrocell to im plement a portion of a complex logic expression.
The complex expressien is then distributed over two or more macrocells
and simplified. Thus, inserting SOFT or NCELL buffers in a design can
affect the timing of a design. However, proper placement of SOFT buffers
can significantly simplify a design, and therefore reduce the number of
expanders and the number of macrocells required by a design.
Figure 2. Complex Combinatorial Logic
This complex function results from heavy use of the XNOR function.
INPUT

XNOA

c::> INPUT
INPUT
INPUT

...,.

XNOA

XNOA

NAN08

,/.,

,."

r - -_ _ _ _ _ _-Ly--OU=.:.:.,TPU=TC>AEOBN

Placing
SOFT and
MCELL
Buffers

c::> INPUT
c::> INPUT

XNOA

INPUT
INPUT

XNOA

)

The best location for a SOFT buffer may not be obvious. Although the
Compiler error message specifies an error location, the identified node
name indicates the output of the complex expression, which is usually not
the correct location for a SOFT buffer. To find the best location, the logic
feeding the node must be analyzed to determine the cause of the expression's
complexity.
A SOFT buffer can be used to minimize the complexity of a combinatorial
expression. In Figure 3, the Compiler has flagged NODE_A as an
expression that is too complex. Since NODE_B has the same structure (and
thus the same complexity) as NODE_A, a SOFT buffer can be inserted at
NODE_CtosimplifythecomplexexpressionsofbothtlODE_AandNODE_B.

Page 500

Altera Corporation

I

I Application Brief 77

Design Guidelines for EPM5000-Series MAX EPLDs I

Figure 3. SOFT Buffer Minimizing Multiple Complex Expressions
Inserting a SOFT buffer at location NODE_ C reduces the complexity of the
logic for both NODE_A and NODE_B.
01

eLK

CJ~~------------~

l--'=':OUf:o.:...:....:PUf:...:..c::> OUf1

c::>.=....:::.:..-----...----------;>

8BITEQ

I--~~c>

OUf2

--place buffer here

Figure 4 shows an example where the SOFT buffer is best placed at the
location tlODE_D, as specified by the Compiler. The logic expression for
tlODE_D is an AND-OR function feeding the Clock input of a D register.
The Clock input has a single product term dedicated to it, and thus would
use a great number of expanders to implement the logic. By placing a
SOFT buffer at tlODE_D, the AND-OR function is efficiently implemented
in a macrocell, and the output of the macrocell feeds the Clock input of the
D register.
~igure 4.

SOFT Buffer Minimizing Complex Expression that Feeds a DFF Clock Input

The control functions for flipflops have a single dedicated
product term. Therefore,
complex functions on the flipflop Clock, Preset, and Clear
terms should be simplified with
a SOFT buffer. In this
example, the SOFT buffer
should be inserted at
NODE_D.

OFF
PRN

BOA6

OUTPUT
i-----c:>CHKFLG

t

place buffer here

Altera Corporation

Page 501

Design Guidelines for EPM5000-Series MAX EPLDs

Application Brief

771

The following suggestions for placing SOFT buffers should be used to
prevent and resolve compilation problems. Not only can fitting problems
be avoided if these suggestions are followed, but often a more efficient fit
will result, allowing additional logic to be integrated into the target EPLD.
The following four steps should be taken in order:
1.

The Design Guidelines section of the MAX+PLUS Graphi.c Editor
manual contains basic guidelines for designing efficiently with the
MAX architecture. This section should be read before any other steps
are taken.

2.

Complex combinatorial expressions feeding flip-flop controls and tristate buffers may be good locations for SOFT buffers. The Output
Enable tri-state input and the Preset, Clear, and Clock inputs to flipflops all have a single product term associated with them. If the
expression feeding a control input is complex or feeds multiple
locations, it may require a large number of expanders. Placing a SOFT
buffer will reduce the number of expanders used.

3.

Complex combinatorial outputs of macrofunctions may be good
locations for SOFT buffers if they do not feed a flip-flop input or an
I/O pin. These complex expressions may need to be isolated before
being routed into another macrofunction. Inputs to macrofunctions
may also be good locations for SOFT buffers if they are being fed by
complex expressions.
Figure 5 shows the outputs of two 7483 adders feeding an 8-bit
magnitude comparator. Both the adder and the comparator contain
complex logic, but placing SOFT buffers at tlODE_l through tlODE_8
significantly reduces the complexity of the overall function.

1

Page 502

Altera Corporation

1

Application Brief 77

Design Guidelines for EPM5000..series MAX EPLDs

Figure 5. SOFT Buffers Minimizing Complex Expressions that Feed an B-Bit Magnitude Comparator
Cascading complex combinatorial macrofunctions may sometimes require SOFT buffers. In this example, NODE_' through
NODE_8 require SOFT buffers.
7483

01
02

D3
04

AlTB

05

AEOB

06

AGTB

07
08

elK

GNO

4.

Complex combinatorial expressions that feed many different locations
may be good locations for SOFT buffers. If a complex expression feeds
multiple Logic Array Blocks (LABs), the logic associated with the
expression is duplicated in each LAB fed by the expression, and the
number of expanders is increased. Placing a SOFT buffer at the
complex combinatorial output reduces the number of expanders. The
Compiler's Report File contains a list of all duplicated expanders.
Figure 6 shows a design that has 1 output in each of the 8 LABs of an
EPM5128. The design consumes 5 expanders in each LAB, a total of 40
expanders. Inserting a SOFT buffer at ttODE_G, however, reduces the
number of expanders used to only 3.

The MAX+PLUS User Guide explains all Compiler error messages.
Additional help can be obtained by calling the Altera Applications
Department at 1 (BOO) BOO-EPLD.

I Altera Corporation

Page 503

I

I~----~~------------------------------------------------------------~--~

!r:I,
II:.

Design Guidelines for EPM5000-Series MAX EPLDs

Application Brief

771

Figure 6. SOFT Buffer Minimizing a Complex Expression that Feeds Multiple LABs
If a logical expression feeds multiple LABs, it may be a good place for a SOFT buffer. In this
example, inserting a SOFT buffer at NODE_G reduces the number of expanders from 40 to 3.

OUTPUT

o~~~------------~
01~~~---------------------1~--/

02~------------------------~~~

OUTPUT
03~------------------------~~--/

OUTPUT
04~-------------------------4~~

OUTPUT
~~-------------------------4~~

OUTPUT
06

OUTPUT
07

OUTPUT
08
CLK

Conclusion

I Page 504

CLAN

When Compiler error messages indicate that logic synthesis or design
fitting are not possible, the designer can use a variety of methods to help
achieve a fit. By adding or removing strategic I1CELL and SOFT buffers or
implementing registers and latches with expanders, complex designs can
be modified to fit into an EPMSOOO-series MAX EPLD.

Altera Corporation

I

Optimizing Memory
for MAX+PLUS Software
I October 1990, ver. 2

Application Brief

781

Introduction

Altera's MAX+PLUS Development System contains a Compiler and a
Simulator that efficiently utilize the memory resources available in pcbased (005) computer systems. Ifa system does notcontainenoughmemoty,
MAX+PLUS may issue out-of-memory error messages when implementing
large designs. A computer that contains more than 1 Mbyte of RAM may
also cause these error messages if the memory is not configured for optimum
use by MAX+PLUS. This application brief discusses the different types of
memory supported by DOS computers, how to determine the memory
configuration of a computer, and how to configure a computer to allow
even the most complex designs to be processed by MAX+PLUS.

Memory
Types

DOS-based computers may have three different types of memory:
conventional, expanded, and extended.

Conventional Memory
Conventional memory consists of the 1 Mbyte of memory directly
addressable by the 80286, 80386, or 80486 microprocessor running in real
mode (also referred to as 8086-emulation mode). Figure 1 shows how DOS
allocates conventional memory.
Figure 1. Allocation of Conventional
Memory in DOS-Based Computer Systems
1 Mbyte
System ROM and
Video Buffers

(TPA).
640 Kbytes

(Variable)

o

I Altera Corporation

Memory ranging from 640 Kbytes up to 1 Mbyte is used
for system ROM (device handlers) and expansion board
buffers. DOS and programs that run under DOS (e.g.,
MAX+PLUS) occupy the lower 640 Kbytes of
conventional memory. This area is further divided into
an operating system area and a transient program area

The operating system area contains the memory-resident
portion of OOS and all installed device drivers specified
in the COttF IG.SYS file. The amount of memory this
area consumes depends on the version of DOS, the
number of disk buffers, and the cumulative size of the
installed drivers. Minimizing the size of this area will
increase the memory available to the TPA, and therefore
to MAX+PLUS. The size of the operating system area,
when MAX+PLUS runs at peak efficiency, is typically
60 to 70 Kbytes.

Page 5051

1m
I

1

Optimizing Memory for MAX+PLUS Software

Application Brief

781

The TPA starts immediately above the operating system area and extends
up to the the installed RAM or the 640-Kbyte boundary, whichever is
smaller. All programs running under OOS are loaded into this area for
execution. For peak efficiency, MAX+PLUS requires 570 Kbytes of RAM
for the TPA. This area may also contain programs that run simultaneously
with MAX +PLUS. These programs, commonly referred to as background,
memory-resident, or TSR (terminate-and-stay resident) programs, occupy
memory that could otherwise be used by MAX+PLUS.

Expanded Memory
Expanded memory in 80286/80386/80486 OOS computers provides access
to additional memory beyond the 1 Mbyte of conventional memory. The
reqUired configuration for MAX+PLUS includes a minimum of 1 Mbyte of
expanded memory. An expanded memory subsystem consists of expanded
memory hardware and a resident driver program. The hardware is either
a memory expansion board plugged into an expansion slot or RAM located
on the computer motherboard. The driver program, called the expanded
memory manager (EMM), is installed via a device directive (device =
EMM.SYS) in the COIiFIG.SYS file. A specific EMM, supplied by the
expansion board manufacturer, must be used to ensure proper operation.
Figure 2 shows how the EMM makes expanded memory available to
a pplica tion software.
Figure 2. Expanded Memory Mapping
The expanded memory manager maps at least four 16-Kbyte pages at anyone time into a
contiguous 64-Kbyte page frame area in conventional memory.
Expanded Memory

Conventional Memory
1 Mbyte

(Configurable

Location)

,I
I

,III

640 Kbytes

1

Page 506

Altera Corporation

1

I Application Brief 78

Optimizing Memory lor MAX+PLUS Software

I

The EMM dynamically maps at least four 16-Kbyte pages of expanded
memory into a contiguous 64-Kbyte page-frame area in conventional
memory. The exact location of the page frame is user-configurable to avoid
hardware conflicts, and is typically placed in the upper 384 Kbytes of
conventional memory (system memory). Placing the page frame in the
lower 640 Kbytes will decrease the size of the TPA. Since MAX+PLUS
requires 570 Kbytes of TPA for peak efficiency, the page frame must be
placed in the upper 384 Kbytes to obtain the optimum configuration for
MAX+PLUS.
The 80286,80386, and 80486 machines use expanded memory differently.
Memory-mapping capabilities built into the 80386 and 80486 processors
allow them to use RAM as expanded memory with no additional hardware.
The 80286 does not have this capability, and requires expanded memory
hardware for the memory mapping function. Therefore, some extended
memory boards may not be compatible with 80286 machines. The user
should consult the board manufacturer for system compatibility information.

Extended Memory
Extended memory consists of RAM located above 1 Mbyte that can be
linearly addressed by 80286/80386/80486 computers running in protected
mode. DOS does not support extended memory except for ROM BIOS
routines, which allow extended memory to be used as RAM disks via the
IBM VDISK software. Since extended memory cannot be used to load and
execute programs, it also cannot be used to increase the usable memory for
MAX+PLUS. Methods for converting extended memory to expanded
memory are discussed later under the heading "Increasing Expanded
Memory for MAX+PLUS."

Determining
Memory
Configuration

The MAX+PLUS Altera Field Diagnostics (AFD) utility can determine the
memory configuration of a computer. This utility also tests Altera
programming hardware. AFD may be invoked by typing afd (Enter>
from the MAXPLUS directory. The computer's memory configuration is
displayed, as shown in Figure 3. The following four items appear under
MeMor~ Configuration:

o
o
o

o

NorMal refers to the amount of conventional memory installed for use
with DOS and programs under 005.
Avai la b 1e refers to the amount of normal memory in the TPA available
toMAX+PLUS.
Expanded refers to the amount of expanded memory available to
MAX+PLUS.
Extended refers to the amount of extended memory in the computer.

If Available is below 570 Kbytes or Expanded is below 1024 Kbytes,
MAX +PLUS may run out of memory.

IAltera Corporation

Page 5071

1m
I

I Optimizing Memory for MAX+PLUS Software

Application Brief 78

I

Figure 3. AFD Memory Configuration Screen
ALTERA Applications En,ineerin, Dia,nostics
Version 1.B
Nov B6 1989
B9:11:B9
Cop~ri,ht (C) 1986-1989 ALTERA Corporation
"S-DOS Version 3.3B
COMputer t~pe: AT or e,uivalent.
BIOS release date: '1B/1/98'
"eMor~ Confi,uation:
NorMal
64Bk b~tes.
Available
566k b~tes.
Expanded
2B48k b~tes.
Extended
1B84k b~tes.
BIOS revision: B.
"icroChannel not available.
s~steM confi,uration: Model: 252 sub-Model: 1

Increasing
Available
Memory for
MAX+PLUS

Available memory for MAX+PLUS can be increased by removing all
background programs and unnecessary device drivers. Removing
background programs frees the entire TPA for use by MAX+PLUS, while
removing device drivers decreases the size of the operating system area,
thereby maximizing TPA size. The following procedure describes how to
obtain the optimum configuration for MAX+PLUS and quickly switch
between configurations:
1.

Sa ve the current configura tion by copying the AUTOEXE C.B AT file to
OJUGINAL.BAT and the CONFIG.SYS file to OJUGINAL.SYS.

2.

Edit AUTOEXEC.BAT and CONFIG.SYS to remove background
programs and unneeded device drivers (EMM must not be removed).

3.

Reboot the system and run AID again to verify that available memory
has increased.

4.

Copy the edited AUTOEXEC.BAT to MAX.BAT and CONFIG.SYS to
MAX.SYS to save. the MAX+PLUS configuration that maximizes
available memory.

5.

Create a DOS batch file (SUITCH.BAT) to provide a means of
switching between the MAX+PLUS configuration and the original
configura tion.

Figure 4 shows SUITCH.BAT and possible MAX.BAT and MAX.SYS
configuration files.

IPage 508

Altera Corporation

I

I Application Brief 78

Optimizing Memory for MAX+PLUS Software

I

Rgure 4. SWITCH.SA 1, MAXSA 1, and MAX.SYS
SWITCH.BAT

c:
cd ,
Cop~

Cop~

XI.bat AUTOEXEC.BAT
CONFIG.SYS

xl.s~s

MAX.BAT

Path = c:'ic:,"axpIKsiC:,dosi
prol"'lpt $p$,
MAX.SYS

Deyice = EMM.SYS AT DOOO 258 ND
Files = 20
BKffers = 20

S,",ITCH.BAT is used to switch automatically to a desired configuration. By
typing swi tch "ax , MAX.BAT is copied to AUTOEXE C.BAT and
MAX.SYS is copied to CONF IG.SYS. The system may then be rebooted to
load the MAX+PLUS configuration. Typing switch original 

followed by a reboot switches back to the original configuration.
Note that MAX.BAT and MAX.SYS are examples; actual files may differ.

Increasing
Expanded
Memory for
MAX+PLUS

The amount of expanded memory available to MAX+PLUS may be
increased in four ways:

o
o
o

o

Configure MAX +PLUS to use all ofthe computer's expanded memory.
Reconfigure extended memory to expanded memory.
Emulate expanded memory with extended memory (80386 or 80486
only).
Add RAM to the computer.

During installation, MAX +PLUS is set to use all expanded memory present
in the computer. The OE (Options : Expanded "e"or~) command
described in Appendix B-MAX+PLUS Configuration File oftheMAX+PLUS
User Guide displays the current expanded memory available to
MAX +PLUS. If this value differs from the expanded memory reported by
AFD, the value may be increased to make all expanded memory in the
computer available to MAX+PLUS.

.1 Altera Corporation

Page 509

iII
I
I

I Optimizing Memory for MAX+PLUS Software

Application Brief

781

If the computer contains extended memory, it may be possible to reconfigure
this memory to be expanded. Some plug-in memory expansion cards or
system motherboards allow the memory to be divided between
conventional, expanded, and extended memory. Typically, the memory
on plug-in is configured via on-card dip switches or a setup program
supplied with the card. The system motherboard is usually configured
with the setup program supplied with the computer. If the computer
contains extended memory, the card or computer documentation may
provide information on configurability.
If the computer has extended memory that is not directly configurable, it
may be possible to emulate expanded memory with an appropriate device
driver. The memory-mapping capabilities of the 80386 and 80486 allow
generic device drivers to convert extended memory to expanded memory.
Two such drivers for 80386 machines are 386MAX from Qualitas, Inc. and
QEMM from Quarterdeck Office Systems. Because the interface to expanded
memory is hardware-dependent, however, generic drivers for 80286
machines are not available. The user should consult the computer
manufacturer for an appropriate device driver for an 80286 machine with
expanded memory capability on the system motherboard.
If the computer does not contain memory that can be used to provide
1 Mbyte of expanded memory, the user must add RAM in one of the
methods described in this application brief, and the associated EMM must
be installed to add expanded memory to the computer.

After increasing expanded memory, AFD should be run again to verify
that expanded memory has been installed properly. Entering the OE
(Options: Expanded MeMor~) command and updating the amount of
memory available then gives MAX+PLUS access to any newly installed
expanded memory.

Conclusion

To avoid out-of-memory messages when running MAX +PLUS, a computer
must be configured to provide 570 Kbytes of available program memory
and 1 Mbyte of expanded memory. Batch files, such as the ones shown in!
this application brief, allow quick loading of this configuration for operating
MAX+PLUS. If out-of-memory error messages persist, contact Altera's
Applications Department at 1 (BOO) BOO-EPLD for assistance.
I

I

I Page 510

A/tera Corporation

II

Simulating
Internal Nodes
with MAX+PLUS Software

I October 1990, ver. 2

,Introduction

Logic
Synthesis
Affects
Simulation

Application Brief 79

I

The MAX+PLUS Simulator and Waveform Editor allow designers to
graphically verify lOgiC, both at the EPLD pins and at nodes internal to the
device. This application brief discusses a variety of methods used to simulate
internal nodes with the MAX+PLUS software. First, it describes the four
ways of naming internal nodes. Next, it shows how to locate nodes within
state machines and combinatorial nodes. Finally, it describes how to identify
appropriate nodes and incorporate them into an input file to perform a
quick and thorough simulation.
Ouring compilation, the advanced algorithms in MAX+PLUS minimize
logic and perform logic synthesis to fit designs into MAX architecture. This
process implements the functionality of the design, but it may eliminate
some of the original nodes that defined the circuit. Consequently, not all of
the original nodes can be simulated. The nodes that can be simulated are
device inputs and outputs, MCELL buffers, and all of the nodes on registers
and latches. SOFT buffers and Til buffers can also be simulated if they are
not eliminated during logic synthesis.
Before simulating a MAX design, it is helpful to generate a History File that
contains a list of all nodes present in the synthesized design:

I Altera Corporation

1.

Invoke the Simulator and load the netlist for the design.

2.

Select FHC (File: Histor9 : Create) and type the name of the file.
Press  to create the History File (with the extension .HST).

3.

Select CNL (Control: Node: List), type *, and press (Enter). The
wildcard character (*) is used to list all nodes in the design that can be
simulated.

4.

Quit the Simulator and MAX+PLUS.

5.

Print the History File (.HST).

Page 5111

I Simulating Internal Nodes with MAX+PLUS Software

Nodes That
Can Be
Simulated

Application Brief 79

I

All nodes in the History File are assigned a name and defined to be of type
IN, I/O, or OUT. Nodes defined as IN correspond to EPLD inputs from
device pins; they have the same node names as the pins they represent.
Nodes defined as I/O are the I/O pins on the EPLD; they have the same
names as their corresponding input, output, or bidirectional pins. Nodes
defined as OUT are internal to the device; they have no direct pin connection.
Internal node names specify the location of a node within a design and
refer to primitives only. The section titled MAX+PLUS Primitives in the
MAX+PLUS Graphic Editor manual shows the complete list of primitives.
All primitives, except TITLE and OUTPUT, have a single output. Figure 1
shows a simple design with a single internal node fed by AliD2, and lists all
nodes that can be simulated.
Rgure 1. Nodes Available for Simulation
A

B

c:>

INPUT

=vcc

INPUT

vee

OUTPUT c>e
3

+

PrimitivelD

f

Node Name is :3

Type

Name

I/O
OUT
IN
IN

C

:3
A
B

The MAX +PLUS Graphic Editor assigns a unique identification number to
every symbol in a schematic. (This 10 is located at the lower left-hand
corner of the symbol.) The only internal node in Figure 1 is :3, defined as
type OUT. This node corresponds to the output of the AIiD primitive with
symbol 103.

Node Names
in Levels of
Hierarchy

Complex designs with multiple hierarchical levels use node names that
incorporate the hierarchical path of the node to define the location of an
internal node. Internal node names may take four forms, and the user may
use more than one of these forms for a particular internal node. However,
the History File lists each node only once using the highest-priority node
name found. The four kinds of node names, listed from highest to lowest
priority, are as follows:
Priority 1:
Priority 2:
Priority 3:
Priority 4:

Probes
Named nodes
Ports/pinstubs
Hierarchical pathnames

All internal nodes have hierarchical pathnames, and most may also be
specified with a port (stub) name. Nodes can be named and probes can be
assigned by the user to further simplify the process of locating and

IPage 512

Altera Corporation

Iii

I Application Brief 79

Simulating Intemal Nodes with MAX+PLUS Software 1

simulating the nodes. For an overview of internal node name syntax, see
"Hierarchical Node Names & Probes" in the Simulator Reference section of
the MAX+PLUS Simulator manual.
Figure 2 shows a hierarchical design example with two levels. The title of
each schematic file in a hierarchical design indicates which symbol it
defines. This design has four accessible internal nodes that feed the CLX,
CLRN, and D inputs to the register, and the register output.
Figure 2. Node Names In a Hierarchical Design
IFile: TOP

I

Symbol Name

DFF
PRN

D

CLOCKHI

CLOCKLOW

INPUT
vee

0

INPUT
vee

eLRN

INPUT
vee

INPUT
vee

Priority 4:
Hierarch ical
Pathnames

OlJTPUT

REG

PortlPinstub

14

Primitive ID

CLRN

0

Type

Name

Node

OUT
OUT
OUT
OUT

IREG_EN:61:16
IREG_EN:61:8
IREG_EN:61:15
IREG_EN:61:14

Register 0 input
Register clock
Register clear
Register output

All internal nodes can be identified by a hierarchical pathname, which
traces the path of the node through multiple levels of hierarchy with a
name of the following format:
: (s!lI'Ibol nal'le): (s!lI'IbollD) •.• : : (s!lI'IbolID)

The pipe (:) indicates that the symbol name following it is the name of a file
in a lower level of the hierarchy. The colon (:) precedes the symbol ID, which
provides further distinction between common symbols in the same level of
hierarchy. Thus, the hierarchical pathname for the clock of the register in

'I A/tera Corporation

Page 5131

iI!I

1

Simulating Internal Nodes with MAX+PLUS Software

Application Brief

791

Figure 2 is lREG_EtI:6l:8. This name defines the AtlD2 primitive (with
symbol 10 8) driving the CLX input, which is inside the symbol REG_EtI
(with symbol 10 6). Designs with multiple levels of hierarchy follow this
pattern, with a pipe (l) separating each level of hierarchy.

Priority 3:
Portsl
Pinstubs

Internal nodes connected to primitives that convert directly into "hard"
nodes (i.e., nodes that will not be eliminated by logic synthesis) use ports
as their internal node names. A port is an extension to the hierarchical
pathname that defines the specific input or output of the primitive. These
ports represent pins at a lower level of the design hierarchy. Ports consist
of a period (.) and a port name that follow a hierarchical pathname. For
example, the D input to the register in Figure 2 is lREG_EtI:6l:14.D. Table 1
shows all port names associated with the register in Figure 2. A list of all
primitives with ports can be found under the heading "Primitives" in
AHDL Elements in the MAX+PLUS AHDL manual.
Table 1. Port Names for the Register Shown In Figure 2

Priority 2:
Named
Nodes

Type

Name

Node

OUT
OUT
OUT
OUT
OUT
OUT
OUT

:5.0E
IREG_EH:61:14.CLlC
IREG_EH:61:14.CLRH
IREG_EH:61:14.D
IREG_EH:61:14.Q
IREG_EH:61:15.IH
IREG_EH:61:15.0UT

Tri-state control
Register clock
Register clear
Register D input
Register output
MCELL input
MCELL output

Hierarchical pathnames can be enhanced by using named nodes. Nodes
are named in a schematic by inserting text above a node, which causes the
symbol 10 to be replaced with the text. For example, the node feeding the
Clock in Figure 2 has the text CLX inserted above it. This name replaces the
symbol 108, changing the name of this internal node to lREG_EtI:6lCLX.
Figure 3. TDF with Named Nodes
TITLE "4-Bit Counter With A 74161";
FUI'tCTIOI't
74161(A,B,C,D,LDn,EI'tP,EI'tT,CLRn,CLX)
RETURI'tS (QA,QB,QC,QD,RCO);

SUBDESIGI't 4_bit
(

...

)

VARIABLE
counter: 74161;
BEGII't

Named nodes are automatically
created in AHDL Text Design Files
(TDFs) when variables are
assigned to nodes that can be
simulated. Figure 3 shows part of
a TDF with the variable counter
assigned to a 74161 counter in the
VARIABLE section. The default
node name of the first register's
output is l74161:33:0A. The node
name after making the variable
assignment is lCOUtiTERlOA.

I

I

EI'tD;

I Page 514

A/tara Corporation

I:

II Application Brief 79
!

Priority 1:

I,Probes

Simulating Internal Nodes with MAX+PLUS Software

I

Internal node names can be fully customized with probes in a logic
schematic. Probes are entered on primitives at any level of hierarchy. The
probe automatically connects to the output of the primitive to which it is
assigned. The following steps describe how to place a probe on the
appropriate primitive to connect to the clock node of the register in
Figure 2.
1.

2.

Open the REG_EN file.
Position the cursor on the AND2 symbol and type SPE (S9Mbol :
Probe: Enter).

3.

Type a name for the probe and press .

A pointer with the assigned probe name is attached to the primitive
output. During compilation, the probe name is put into the Simulator
Netlist File (SNF) in place of the hierarchical pathname. For example, in
Figure 2 a probe called D_INPUT placed on the NOT gate feeding the D
input to the register will produce the node name D_INPUT in the SNF, thus
eliminating all the hierarchy information for the node name.
MAX+PLUS allows the user to name internal nodes in a variety of ways.
The Simulator lists each node only once, using the simplest name for the
node. If the node has a probe attached to it, the node is listed under the
probe name. If not, the node is listed with a node name, or under a port
name if no node name exists. Finally, if no other higher-priority name
exists, the node is listed under its hierarchical pathname. Table 2 shows the
four ways of naming the D input to the register in Figure 2.
Table 2. Four Possible Names for 0 Input
Internal Node Name

Type of Name

D_INPUT

Probe

IREG_EN:61D_INPUT

Named node

IREG_EN:61:14.D

Port'Pinstub
Hierarchy path name

Description
Probe named D_U'IPUT placed
on NOT
Node feeding D input
D_IHPUT

IREG_EH:61:16

IA/tera Corporation

D input port
Hierarchical pathname of HOT
primitive feeding D input

Page 5151

I Simulating Internal Nodes with MAX+PLUS Software
Simulating
State
Machines

Application Brief 79

I!

Since state machines often control an entire design, simulation is especially II
useful for debugging state machines. Four items in a state machine may
need to be simulated: inputs, decoded outputs, state register bits, and
present states.
I

State Machine Inputs
State machine input lines feed combinatorial logic, which, in turn, feeds
the Dinputs to state register bits. However, state machine inputs can only
be simulated when they are fed by EPLD input pins or by hard nodes
within a design. To allow simulation of state machine inputs when these
inputs are fed by combinatorial logic, an tlCELL buffer should be placed in
front of all inputs to a state machine. The tlCELL is a hard node; therefore,
its outputs (Le., the inputs to the state machine) can be simulated. Note,
however, that inserting an tlCELL affects the timing of the state machine,
and tlCELL buffers should therefore be removed after simulation. This
technique is used to verify functionality, not timing.
To make the tlCELL more accessible during simulation, a probe with the
same name as the input to the state machine may be attached to the tlCELL
in the Graphic Editor.

Decoded Outputs
Decoded outputs are also combinatorial, and therefore may not allow
simulation. If decoded outputs do not feed hard nodes, such as tlCELL
buffers or output pins, then they cannot be simulated. As with state
machine inputs, decoded outputs may simulated if an tlCELL with a probe
on it is placed after the decoded outputs.

State Register Bits
State register bits are assigned names in a state machine declaration in the
VARIABLE section of an AHDL file. The syntax of this declaration is:
(naMe) : MACHINE OF BITS ( (state re!isters) )
~ITH STATES
«state aSSi!nMents) )

The Simulator extracts the state register names from the TDF to define the
register bits. A state machine in a lower level of a hierarchical design
incorporates the state machine name into the node name to distinguish it
from state machines at the same level. Figure 4 shows a TDF with a state
machine. If this machine is loaded into the top level of a schematic design,
the state register outputs for this design are :4_STATE:nIQ8 and
:4_STATE:n:Ql (where :n is the 10 for the symbol representing the state
machine).

IPage 516

A/tera Corporation

II

·1

Simulating Internal Nodes with MAX+PLUS Software

Application Brief 79

1

Figure 4. Text Design File with State Machine
TITLE "A Si"ple State Hachine";
DESIGH IS 4_state;
SUBDESIGH 4_state
(

elk. BUS[3 .. 8]
I"PUT;
: OUTPUT;
C"T[3 .. 8]. decode
UARIABLE
state

HACHI"E OF BITS (Q[1 •• 8])
~ITH STATES ( OHE. T~O. THREE.

FOUR );
BEGI"
state. elk = elk;
C"T[ ] = Q[ ];
CASE (state) IS
~HE" OHE =>
state = T~O;
decode = (JUS[]
~HE" T~O

h"A");

=>

state = THREE;
THREE =>
state = FOUR;
~HE" FOUR =>
state = O"E;
decode = (BUS[]
E"D CASE;
~HE"

h"7");

E"D;

AHDL state machines provide automatic state assignments. When this
feature is used, it is more useful to monitor the state name rather than the
individual state registers. The state name can be monitored easily in the
Waveform Editor by entering waveforms for the individual state register
bits and combining them into a bus with the same name as the state
machine. The waveforms have the associated state names displayed in a
text format inside the bus. Figure 5 shows the waveforms for the TOF in
Figure 4.

I

Altera Corporation

Page 5171

1

Simulating Internal Nodes with MAX+PLUS Software

Application Brief 79

I·

Rgure 5. State Names In the Waveform Editor

)(

Present States
There are three ways to set up the Waveform Editor to show the present
state of a state machine. The easiest is to use the default channel file that
automatically places the state machine bus in the Simulator Channel File
(.SCF). Another method is to enter the state machine name in an ASCII
Vector File (.VEC) by entering the state machine name (including its
hierarchy information) in the Outputs Section. The third method, entering
the state machine into a Simulator Channel File, requires these steps:
1.
2.

Enter the waveforms for the state register bits individually into the
Waveform Editor, with each node corresponding to a state register bit.
Group the nodes together and make the group name the same as the
name of the state machine.

Whichever method is used, the appropriate state information will appear
in the Simulator Channel File after simulation.

Simulating
Inaccessible
Combinatorial
Nodes

Some combinatorial nodes cannot be directly simulated. To simulate buried
combinatorial logic, the node should be fed into an tlCEll buffer, then a
probe should be placed on the NCEll and named. Next, the design should
be recompiled to generate an updated Simulator Netlist File. The NCEll
should be removed once the node is shown to be functionally correct.
Figure 6 shows a combinatorial circuit for a decoder with three enable lines
called Gl, G2AN, and G2BN. To activate the outputs, all three of the enable
lines feeding the BAND3 gate must be active. To simulate the combinatorial
logic in this design, an tlCEll may be placed in the circuit between the
BAND3 primitive and the NAND2 primitive. (The timing of the circuit will
change.) This technique should be used to verify functionality, not timing.

1Page

518

Altera Corporation

I

I Application Brief 79

Simulating Intemal Nodes with MAX+PLUS Software

I

Figure 6. Placing an MCELL for Simulation of Combinatorial Logic
NOT

Finding
Nodes

G2AN

C:::~~----d

G2BN

L-...;>-"-'-"';"';"'---....I

Once all nodes that can be simulated have been identified, it may be useful
to find their locations in the schematic or text file. The LNF (Line: Node:
Find) command in both the Graphic Editor and the Text Editor helps
locate nodes that have hierarchical node names:
1.

Type LNF (Line: Node: Find).

2.

Type the internal node name and press .

The schematic or file containing the node is then loaded and the node is
highlighted.
A quick way to find a node is to use the LNF (Line: Node: Find)
command within the schematic that contains the node. For example, ifLNF
(Line: Node: Find) is selected while the file REG_EN is displayed, the
prompt line displays IREG_EN:6, which is the hierarchy path that leads to
the current file. Typing  1:8  then highlights the AND2 gate.
H a node is identified with a probe, only the probe name must be entered.

Using
Internal

Nodes in
Simulation

Nodes can quickly be placed into a Simulator Channel File or Vector File
for simulation. Internal nodes are added to the Outputs Section of a Vector
File by importing the names from the node list in the History File. Figure 7
shows an example of a Vector File created from a History File node list
with I/O pins and internal nodes grouped together to form buses.
The Waveform Editor automatically creates a default Simulator Channel
File that contains the device I/O pins, internal nodes with probes, and
nodes associated with state machines. Additional nodes that need to be "-",
simulated can be appended to this file.

11:.1

IA/tera Corporation

Page 5191

I Simulating Internal Nodes with MAX+PLUS Software

Application Brief 79

I

Figure 7. Creating Groups In a Vector File from an Internal Node List
--- "ODE LIST --T!lpe
I"
I"
I"
I"
I"
I"
I"
I/O
I/O
I/O
I/O
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

Conclusion

IPage 520

UECTOR FILE

"al'le

GROUP CRERTE B_BUS

'" B3 B2 Bl B8;

CLOCK
DIR
S
D8
Dl
D2
D3
B8
Bl
B2
B3

GROUP CRERTE D_BUS

'" D3 D2 Dl D8;

GROUP CRERTE I"T_BUS

:21ttUX:91 5
I 21ttUX:12 :5
I 21ttUX: 18 :5
I 21ttUX: 11 :5;

:5
:6
:7
8

21ttUX:9:
21ttUX:12
21ttUX: 18
21ttUX: 11

5
:5
:5
:5

The MAX +PLUS Simulator incorporates many features. With the Graphic
Editor's probe capability and the integrated Altera Hardware Description
Language (AHDL), all nodes that can be simulated are easily identified.
Additionally, both AHDL Text Design Files and Graphic Design Files use
a parallel method to identify internal nodes, making simulation quick and
simple.

Altera Corporation

Emulating Internal Buses
in General-Purpose EPLDs

I October 1990, ver. 2

Application Brief

821

,Introduction

Altera's general-purpose (EP- and EPMSOOO- series) EPLDs allow internal
buses to be emulated by using logic to replace tri-state functions. A series
of simple 2-to-l multiplexers can create buses with two sets of input
signals. 4-to-l (and larger) multiplexers can create buses with three or
more sources. Multiplexing also saves device resources and helps to
eliminate timing and loading problems. This application brief describes
how to use multiplexers for different bus configurations and explains the
benefits of this approach.

Two-Source
Bus
Configurations

Figure 1 shows the simplest bus configuration, a one-bit bus created by
connecting the outputs of two tri-state buffers to a single line. The function
table shows the possible states of the bus. When tri-state buffer A is
enabled, the input to that buffer (ItlA) appears on the bus. When tri-state
buffer B is enabled, the input to that buffer (ItlB) appears on the bus. If
neither buffer is enabled, the bus is in a high-impedance, or floating, state.
Note that buses are often tied high with a pull-up resistor to prevent them
from floating.
Figure 1. One-Bit Bus
Two tri-state buffers can create a simple bus.
Bus Line

OEA-----.
INA---I

TRI A
OEB------,

INB---I

INA

OEA

INB

OEB

BUS LINE

X

0

X

0

Z or 1

X

0

0

1

0

X

0

1

1

1

0

1

0

0

1

1

X
X

0

1

TRI B

Figure 2 shows two AND gates and an OR gate that emulate the tri-state
functions of Figure 1. Each AND gate has a data input (INA or ItlB), and a
select input (SELA or SELB) that represents the original Output Enable
control. The function table shows that the AND/OR logic exactly emulates
the original tri-state functions if one of the two outputs is always selected.
If neither output is selected, the output of the AND/OR logic is low.

Altera Corporation

Page 521

I

1m
I

I Emulating Internal Buses in General-Purpose EPLDs

Application Brief 82 I

Figure 2. AND/OR Logic Emulating Tri-Statlng Functions
Bus Line

SELA --l~~r-""""I

INA----f

SELB-'--....:..-r-""""I
INB---~_~

INA

SELA

INB

SELB

BUS LINE

X
X
X
0

0
0

0
1

0

1

1

X
0
1
X
X

0
1

0

1

1

0

0

0

1

The select controls are mutually exclusive, since only one input is ever
enabled onto a bus at any given time. Therefore, they can be encoded into
a single input by making SELA the common select input, and then feeding
the inverse of this signal into the previous SELB input. Figure 3 shows that
these steps transform theANO/OR logic into a typicaI2-to-1 multiplexer.
The multiplexer functions in the same way as the AND lOR logic in Figure
2, except that the two select signals have been encoded into a single line.
Figure 3. Multiplexer Created with AND/OR Logic and Select Controls
Encoded select
lines transform
the AND/OR logic
from Figure 2 into
a multiplexer.

AND2
SEL --e----fr-""'"
INA - + - - - - f L....
OUTPUT

INB---~

INA

INB

SEL

OUTPUT

X

0

0

0

X

1

0

1

0

X

1

0

1

X

1

1

Additional2-to-1 multiplexers, all controlled by a common select signal,
can create wider buses. One multiplexer is necessary for each bit of the bus.
For example, Figure 4 shows eight 2-to-1 multiplexers emulating a bytewide bus.

Buses with
Three or
More
Sources

Larger multiplexers with multiple select inputs can emulate buses with
more than two sources, Figure 5 shows how a 4-to-1 multiplexer can create
a bus with up to four sources. Figure 5 also includes a truth table with the
proper encoding for the select inputs. This type of multiplexer can also
implement buses with two or three sources.
Additional multiplexers with shared select lines can create buses with
nearly any width. For example, five 4-to-1 multiplexers can create a 5-bitwide bus with two, three, or four sets of inputs.

IPage 522

Altera Corporation

I Application Brief 82

Emulating Internal Buses in General-Purpose EPLDs I

Figure 4. Eight 2-t0-1
Multiplexers Emulating a ByteWide Bus

Figure 5. 4-t0-1 Multiplexer Implementing a Bus with Up to Four Sources
-----------_ ................... __ ............................. --.
AN03
INA

21 MUX

INAo
INBO
SEL

OUTO

INB

----:-++---+---(.~

OUTPUT

INC ---j.-+-+---+-t-t~
INAI
INBI

OUTI

INO

---~-+---+-t-t---.J

SEll ----:--++-i

INA2
INB2

SEL2

OUT2

~-""';>O----'

...............................................................
4:1 Multiplexer

INA3
INB3

INA4
INB4

INAS
INBs

INA

INB

INC

INO

SEL2

SEL1

OUTPUT

X

X

X

0

0

0

0

X

X

X

1

0

0

1

X

X

0

X

0

1

0

X
X

X

1
X

X

0

1

1

0

X

1

0

0

X

1

X

X

1

0

1

0

X
X

X
X

X
X

1

1

0

1

1

1

OUT3

OUT4

OUT5

1
INA6
INB6

OUT6

INA7
INB7

OUT7

'Implementing
Bus
Functions
with AHDL

I A/tera Corporation

For MAX+PLUS users, the Altera Hardware Description Language (AHDL)
provides a quick alternative to graphic schematic entry for implementing
bus functions with multiplexing. AHDL files can generate buses with
nearly any number of inputs and of nearly any width.
For exam pIe, Figure 6 shows the lines of AHDL code required to create an
eight-bit bus with three sources. The data inputs are A7 to A8, B7 to BB, and
C7 to C8. The two select inputs, SELl and SEL2, can be treated as an
encoded group in AHDL. These select lines control which set of input
signals is connected to the outputs through a series of simple IF-THEN
statements.

Page 523

I

IEI

1 Emulating

Application Brief 82 I·

Internal Buses In General-Purpose EPLDs

Figure 6. AHDL implementation of Eight-Bit Bus with Three Sources

SUBDESIGN BUSMUX (
A[? .8],
B[? .8],
C[? .8],
SEL[1 .. 8]: INPUT;
OUT[?.8]: OUTPUT;
BEGIN
IF (SEL[]==8> THEN
IF (SEL[]==1> THEN
IF (SEL[]==2> THEN

>
OUT[]=A[]; END IF;
OUT[]=B[]; END IF;
OUT[]=C[]; END IF;

END;
By adding data inputs (e.g., D[7 .. Bl), this file can be easily modified to
create a bus with more sources. For multiplexers with more than four data
inputs, one more bit must also be added to the SEL group (e.g., SEL[2 .•Bl)
for each factor-of-two increase in the number of data inputs. For example,
a seven-input multiplexer requires three select bits.
The width of the bus can be varied by changing the input and output group
widths. For example, the declaration A[S ..Bl creates a 5-bit-wide set of A
inputs.
For more information on AHDL syntax, refer to Application Note 22
(Designing with AHDL).

Why Emulate
Tri-State
Functions?

Using multiplexing to emulate tri-state functions saves macrocells and I/O
pins for applications that would otherwise require a bus external to the
EPLD. Figure 7 shows a 4-to-l multiplexer in a single macrocell that
emulates a bus line with four sources. With conventional tri-stating
techniques, the same function requires four macrocells and I/O pins, as
shown in Figure 8. Multiplexing saves three macrocells and I/O pins if the
switching functions are implemented with the product terms inside the
macrocell, instead of with tri-state buffers and I/O pins external to the
macrocell.
Figure 7. 4-t0-1 Multiplexer in a Single Macrocell
.......................................................................................................

I J~
~

IPage 524

4"M~

M~~

I

.................................................................................................:
Altera Corporation 1 ,I

Application Brief 82

Emulating Internal Buses in General-Purpose EPLDs

I

Figure 8. 4-t0-1 Multiplexer Implemented with Traditional Tri-State Logic
A four-source bus that uses tri-stating requires four macrocells and 110 pins.
External
Bus Line

,.............................................................
1
: OEA

1 INA

Macrocell A 1
:

~ A ;1---'"

L......................:.~~ ............................... j
...............................................................
1

Macrocell B 1

lOEB - - ' ]

1

f"IllTPllT

1 INB ~ B :.......----e
:
\

TRI

:

............................................................... ;

r····································~~;~~ii·C"··l

: OEC

1

INC

~C

:

----e

;l-:

t.......................:.~~ ............................... j
r····································~;~~ii·D···;

: OED -----"]
IND

1

f"Il ITPIIT

~

:

0

----e

:;...1

L......................:.~~...............................1

Emulating tri-stated buses with logic eliminates timing hazards such as
bus contention, which occurs when two or more tri-state outputs are
simultaneously enabled onto a single bus line. This condition (usually
unintended) can cause an unpredictable logic level to propagate if multiple
buffers are driving high and low at the same time. The select controls for
simple AND JOR logic (shown in Figure 2) can both be enabled at the same
time, but the result will be a known logic level. The select controls can
never be enabled at the same time if they are encoded, as in the true
multiplexer configurations (Figure 3).
The only potential timing hazard for a multiplexer configuration is output
glitchingcaused by input Signal skew. EPLD architecture minimizes skew
difficulties and glitching is seldom a problem in actual designs. However,
the designer must exercise care when driving edge-sensitive logic from
multiplexer outputs.
Replacing tri-stated buses with logic reduces capacitive loading limitations.
High fan-outs to traditional buses create high capacitive loads that slow
bus bandwidth. Macrocells and feedback paths in EPLDs have constant
delays, regardless of the number of signals entering the macrocell. If
control logic is implemented with multiplexers, internal bus loading is not
a problem.

I Altera Corporation

Page 525

I

~

11:.1

IEmulating Internal Buses In General-Purpose EPLDs
Conclusion

IPage 526

Application Brief 82

I

Although Altera's general-purpose EP- and EPMSOOO-series EPLDs do not
have internal tri-state capabilities, the tri-state function can be emulated
with multiplexing. The multiplexing technique allows designers to create
buses of nearly any size in the EPLD. Multiplexing also provides the
additional benefits of saving device resources, and eliminating timing and
loading problems.

Altera Corporation

I

Programmable
Frequency Divider
with the EP630 EPLD
Application Brief

October 1990, ver. 2

831

Introduction

AHera's EP630 EPLD combines the industry-standard EP600-series
architecture with advanced 1.0-micron CMOS EPROM technology to
produce a high-speed (tpD = 15 ns) 24-pin EPLD. This application brief
com pares the EP630 EPLD wi th the 22Vl 0 device, focusing on archi tecture
and design support. An example that illustrates important EP630 features
is also included.

Architecture

The EP630 EPLD and the 22VI0 device have several features in common:
both are available in a 24-pin package, both generate Boolean logic
expressions with a sum-of-products array, and both process Boolean
functions through macrocells (see Figure 1).
However, the two devices differ in important ways:

o

The most obvious difference is the number of macrocells offered: the
EP630 EPLD contains 16 macrocells, the 22VI0 contains only 10.

o

All EP630 macrocells contain a programmable flip-flop that can be
configured for D, T, JK, or SR operation, thus substantially increasing
its fleXibility. In contrast, the 22VI0 has a fixed D flip-flop architecture.
For example, a 10-bit counter implemented in a 22VI0 requires 10
product terms to generate the tenth bit, while the same counter in an
EP630 EPLD requires only a single product term for each bit when the
internal registers are configured for T flip-flop emulation.

o

The EP630 registers are individually configured to clock from a global
or asynchronous clock, while all of the 22VI0 registers are clocked
from a single global clock source.

o

The EP630 EPLD has 128 equally distributed product terms, 8 per
macrocell. In addition, individual product terms are added to the
Clear and Output Enable inputs of each EP630 macrocell, giving the
designer much greater flexibility. The 22VI0 has variable productterm distribution and contains anywhere from 8 to 16 product terms
per macrocell.

o Maximum clock frequency for the EP630 EPLD is 83 MHz; for a CMOS
22VI0, it is 80 MHz.

o
Altera Corporation

An EP630 requires 90 rnA current; a 22VI0 requires 130 rnA current.
Page 5271

!'r:t
1.1.:.1
l

I Programmable Frequency Divider with the EP630 EPLD

Application Brief 83

I

Figure 1. Macrocel/s In the EP630 EPLD and the 22V10 Device
EP630 Macrocell
Synchronous

OE/ClOCK

Clock

Select

vee

OE

OE/ClK
ClK

AND
ARRAY

Programmable

Flip-Flop Type

CLEAR
~---------------+----------------~MUX

22V10 Macrocell

r····~:····g:·~·~·~·~r.c.~~~r~r~·~~~········i
>-~

__--i1D
o-e----IO

r--:-----I> C1

SS

1S

MUX
T

G1

l1

AR = Asynchronous Reset
SS = Asynchronous Set

;.

IPage 528

S1

............................................................................ :

Altera Corporation

I

I Application Brief 83

Programmable Frequency Divider with the EP630 EPLD

I

Table 1 summarizes these features.
Table 1. EP630 EPLD VB. 22V10
Features
Speed:
tpo
teNT
Macrocells
Programmable Clocks
Programmable Flip-Flops
Zero Power

EP630

22V10

15 ns
83 MHz
16
Yes
Yes
Yes

15 ns
80 MHz
10
No
No
No

The EP630 architecture provides greater register density and flexibility
than the 22VIO, allowing more logic to be incorporated. For example,
Figure 2 shows a programmable frequency divider, a common application
forPLDs.
Figure 2. Programmable Frequency Divider
vee

--;..---+-i-+-;f-(·························I

CLEAR

INP

CLOCK c=>-++~",""",

NOT
~----,~~..,.

C

FDIV

CJ----------...J

B~~----------~
A~~------~-----------J

ENABLE ~~-------------------------------------l

I

Altera Corporation

Page 529

I

IProgrammable Frequency Divider with the EP630 EPLD

Application Brief 83

I

This frequency divider accepts a frequency, divides it by powers of two
(21, 22, 23, ... ), then produces a selected output frequency based upon
frequency-select inputs. Frequency division is accomplished by three
cascaded frequency dividers, each receiving a clock from either an input or
the previous frequency divider. The divider frequencies are connected to
two 74157 multiplexers, each of which routes a selected clock-defined by
the select address (A~B~C)-to its output. Finally, a single frequency is
chosen by the 2-to-1 multiplexer, which is implemented with gates.

The EP630
Solution

The EP630 is a better choice than the 22V10, both for hardware
implementation and for software design entry.
As Figure 3 shows, the EP630 EPLD easily integrates the programmable
frequency divider into a single device to produce the selected frequency
FDIV. On the other hand, the 22VI0 device is not well suited to this
application. Since it contains only 10 macrocells, two 22VI0 devices are
needed to implement the 12-bit counter. Device A must function as a IO-bit
counter; its outputs 08 to 09 must supply part of the input to device B.
Device B is clocked by 09 forming a ripple counter to create the two most
significant bits of the 12-bit counter function. Frequency-select inputs to
device B control the clock output multiplexer that ultimately produces the
selected frequency, FDIV.
Figure 3. EPB630 VS. 22Vl0 as Programmable Frequency Divider
ClK
ClR

ClK
ClR

A

22Vl0

B

A

0O--Q9

C
D
Solution 1
09

A
B
C

22Vl0 ~--- FDIV

B

D

The logic design for the EP630 EPLD is entered, compiled, verified, and
programmed with the Altera Programmable Logic User System (A+PLUS).
Design entry is simple with LogiCaps schematic capture. LogiCaps provides
access to over 100 Altera-supplied TIL macrofunctions (see Figure 2),
which speed up design entry for designs such as this programmable
frequency divider, allowing the designer to enter and connect the
appropriate TIL macrofunctions. The Altera Design Processor provides

I Page530

A/tera Corporation

I

I Application Brief 83

Programmable Frequency Divider with the EP630 EPLD

I

algorithms that automatically fit the programmable frequency divider into
the EP630, and produces a standard }EOEC file to program the device.
During compilation, A+PLUS automatically performs logic reduction,
configures the data paths within the macrocells, and chooses the best flipflop configuration (0, T, }K, or SR). The result is a working design produced
quickly and efficiently.
The 22VI0 design, on the other hand, is entered with Texas Instruments'
Prologic PLO compiler (shown in Figure 4). Since Prologic is a text-based
entry language, each counter and multiplexer must be expressed as a
separate Boolean function. This is a time consuming, error-prone task.

Conclusion

Together, the EP630 EPLD and A+PLUS software offer the ideal solution
for implementing a programmable frequency divider in a single device.
Figure 4. Frequency Divider File Created with Pr%gic (Part 1 of 4)
Li sting 1:

Device A

title < Device:
Application:
Source:
include

PALZZU18
1Z Bit Progra""able Frequenc~ Divider:
Designer Nane
9/89)

pZZv1B:

/W

specif~

that target device is PALZZU1B

define
define

= pin1

/W

cn

define input pins

= pinZ

define
define
define
define
define
define
define
define
define
define

Q8
Q1
QZ
Q3
Q4
QS
Q6
Q7
Q8
Q9

= pin14

/W

define output pins

/w

CLK

Q1.d
QZ.d

W/

w/

w/

= pin1S
= pin16

= pin17
= pin18
= pin19
= pinZ8
= pinZ3
= pinZZ
= pinZ1

define equations to inplenent lower 18 bits of counter

Q8.d

Device A

= ! (QB.q) & !CLR
= (!Q8.q & Q1.q
= (!QB.q & QZ.q

w/

Q8.q & Q1.q) & !CLR ;
!Q1.q & QZ.q I Q8.q & Q1.q & !QZ.q) & !CLR

Q3.d = (!Q8.q & Q3.q
!Q1.q & Q3.q
!QZ.q & Q3.q
Q8.~

Q4.d

= (!Q8.q

& Q1.~ & QZ.q &

!Q3.~)

& !CLR

& Q4.q

!Q1.q & Q4.q
!QZ.q & Q4.q
!Q3.q & Q4.q
Q8.~ & Q1.q & QZ.q & Q3.~ & !Q4.q) & !CLR

Altera Corporation

Page 531

I

Application Brief 831

Programmable Frequency Divider with the EP630 EPLD

Figure 4. Frequency Divider File Created with Prologie (Part 2 of 4)
QS.d

= (!QB.~
I

& QS.~

& QS.~
I !Q2.~ & QS.~
I !Q3.~ & OS.~
I !04.~ & OS.~
I OB.~ & Q1.~ & 02.~

Q6.d

!Q1.~

= ('OB.~

& Q3.~ & 04.~ &

!OS.~)

& !CLR

& 06.~

I !01.~ & 06.~
I !02.~ & Q6.~
I ! 04. ~ & 06. ~

& 06.~
& 06.~
I OB.~ & 01.~ & 02.~ & 03.~ & 04.~ & OS.~ &
= ('OB.~ & 07.~
!03.~
!OS.~

07.d

!01.~

& !CLK

!06.~)

& 07.q:

& 07.q
!03.~ & 07.q:
!04.~ & 07.q:
!OS.q: & 07.q:
!06.~ & 07.q:
OB.~ & 01.~ & 02.q: & 03.~ & 04.~ & OS.q: & 06.~ &
!02.~

08.d ::

(!OB.~

!07.~)

& !eLR

& 08.~

!01.'I & 08.~
!02.'I & 08.~
!04.'I & 08.~

& oa.~
& oa.q:
& oa.~
!07.'I & 08.~
OB.'I & 01.'1 & 02.~ & 03.'1 & 04.q & OS.q & Q6.q & 07.'1 & !08.'I> &
!03.~

!OS.~
!06.~

!CLR ;
(!OB.~

09.d

& 09.~

!01.'I & 09.~
!02.1 & 09.1
!04.~ & 09.q:
!03.1 & 09.q:
!OS.'I Ii 09.q:
!06.1 & 09.q:
!07.q: & 09.q:
!Oa.1 & 09.~
!OB.~ & 01.q: Ii
!Q9.~) & !CLK

,,-QB.oe

per"anentl~

= 1;
OS.oe = 1 ;

,,-OB define
~;

OS =

Page 532

~;

02.~

& 03.~ & 04.~ & OS.q: & 06.~ & 07.~ & oa.'I &

-"

enable all counter outputs
1;
01.oe
1;
OZ.oe
03.oe :: 1;
06.oe = 1 ;
1;
08.oe ::1;
07.oe

outputs as actille high
q:;
QZ
01
06 = ~;
07 =

-"

~;

~;

03
08

~;

'I;

04.oe
09.oe
Q4
09

1;
1;

~;
~;

Altera Corporation 1

Application Brief 83

I

Programmable Frequency Divider with the EP630 EPLD

Rgure 4. Frequency Divider File Created with Prologic (Part 3 of 4)
/w define so"e test
test_~ectors < /w

C

that counter is working
Q8
Q3
QZ
Q1
pin!? pin16 pin1S pin14;
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
H
L
1
H
1
L
H
L

C

1

e
C

L
L

C

H

c
e
e
e

H

C

~ectors

to
CLR

pin1
c

pinZ
1
1

C
C
C
C

c
e
C

Listing Z:
title

<

De~ice

~erif~

CLJC

1
H
H

H

L
1

L

H
H

L
L
L
L

..

H

L

H

H

H
1

L

H

H

L

H

H
H

H
H

H
H

H

L
L

L
L

1

/
/
/

H

Device B

Di~ider:

' .... S9
/w

pZZ~1B;

specif~

)

that target device is PRLZZII1B */

define
defi ne

CLJC
CLR

= pin1
= pinZ

/* clock input is fro" Q' on de~ice A
/* clear goes to pin 2 on both de"ices

define
define
define
define

A
B

pin3
pin4
pinS
pin6

,I"
,I"

D

../

..
..

L
L

PRIZZII1B
12 lit Progra""able Frequenc~
ZHSB and Hultiplexing Control

Application:

e

8

..

L

L

..
..
..

.
..
.
..

9 ../
18 /
/* 11 */
/* 1Z /
/* 13 .. /
/
14 */
/W
1S W/
/
B */
/*RESET"/

H

Source:

define
define
define
define
define
define
define
define
define
define

QB
Q1
QZ
Q3
Q4
QS
Q6
Q?
QS
Q9

define
define

Q1B
Qll

pin19
pinZB

define

FDIII

= pin1S

select inputs for
Select Input
/*
ABCD = B

,I"
,ItI

pin?
pinS
pin9
pin1B
pin11
pin13
pin14
pin1S
pin16
pin1?

,ItI

~ltipluing

Q Output
di~ided b~

2

4

Z

8 .. etc

define counter inputs fro" device A

/w define Z MSB of 1Z bit counter

;
;

/w

;

Q18.d

!(Q1B. 'I)

QU.d

(!Q1B.f{ & Q11.q

&

outputs

1

di~ided

WI'
WI'
WI'

",I
til'
tI/
til'
til'

-,I

output */

/w define equations to i"ple"ent 2 MS. or counter

Altera Corporation

/*RESETw/
/*RESET"/
/
1 w/
/W
/
Z
/w 3 .. /
/
/* 4
/W
/
S
/w 6 .. /
/
/*
?

H
1

H
H
H

W/

*/

I

De~ice:

include

properl~

til'

!CLR
Q18.q & Q11.q) & !CLR

Page 533

I

Application Brief

Programmable Frequency Divider with the EP630 EPLD

831

Rgure 4. Frequency Divider File Created with Prologic (Part 4 of 4)

".

,.

derille e.uations to control
fDI"

Oil

01
02
03
04
05
06
O?

08
09
0111.1
011·1

I
I

I
I
I
I
I

I
I
I
I
I

'A

'"'"
'"'"'"
'"A

I
I

I
I
I
I
!" I
I
I
II I
II I
II I

~ltiplexing

I

I
I. I
I
I
I
I
I
I
I
I

II

,.

•
•••
,.

,.,.

'I

I

,e
,e
e
e
,e
,e
e
e
,e
Ie
e
e

I

I
I
I
I
I
I
I
I
I
I
I

or Dutputs ."

'D
I
II
I
'I
I
!I
I
'I
I
'D
I

",.

"III

".1"was used on terMS
are internal feedbacks

III"

."

". perManently enable all outputs ."
0111.oe = 1. 011.oe = 1.
'IIV.oe = 1;
". define outputs as active high ."
018 = 1.
011 = 1.

Page 534

A/tera Corporation

I

DMA Controller
with the EPM5064 MAX EPLD
October 1990, ver. 1

I

Introduction

Application Brief

84\

A Direct Memory Access (DMA) controller can increase the performance
of a peripheral subsystem by coordinating data transfer between peripheral
and subsystem memory. A DMA controller is useful when a design requires
data transfer rates that are too fast for a microprocessor. DMA can be used
by a disk-drive controller to quickly transfer large blocks of data, by highspeed serial subsystems to maintain communications link bit rates, and by
dedicated graphics processors that update images stored within video
memory.
DMA controllers can be implemented in several ways. Standard off-theshelf DMA controllers are available (e.g., Am9517A/8237A), providing a
single-chip, application-specific solution. However, these controllers may
be unsuitable due to speed, power consumption, or protocol requirements.
For example, the Am9517A transfers data at 2.5 Mbytes per second and
requires a specific set of control commands, which is normally not available
with standard DMA controllers.
If higher performance or custom functions are required, a DMA controller
can be implemented with discrete TIL components (e.g., the 7400 series).
This approach supports custom DMA protocols and tailored performance,
but has a number of drawbacks: TIL logic consumes high power, requires
a large amount of PC board space, and the high component count and
power dissipation reduces overall system reliability.

Erasable Programmable Logic Devices (EPLDs) offer the ideal solution,
integrating the advantages of the standard off-the-shelf DMA controller
with the higher performance and flexibility of the TIL approach. This
application brief illustrates how a DMA controller implemented in an
Altera EPM5064 EPLD achieves data transfer rates of up to 20 mega words
per second between peripheral and subsystem memory.

EPM5064
Overview

The EPM5064 is a user-configurable, high-performance, high-density MAX
EPLD. It offers a fast 25-ns input-to-output combinatorial delay and
50-MHz 16-bit counter frequencies. This EPLD is offered in 44-pin
windowed ceramic and plastic J-Iead chip carrier packages that have
8 dedicated inputs and 28 bidirectionalI/O pins. Commercial, industrial,
and military temperature-range versions are available.
The EPM5064 contains 64 macrocells, each with a register that can be
programmed for D, T, JK, SR, or flow-through latch operation, or bypassed
entirely for purely combinatorial functions. All macrocell registers also

,I

Altera Corporation

Page53sl

!'it
I.a

I DMA Controller with the EPM5064 MAX EPLD

Application Brief 84

I.

include asynchronous Clear and Preset controls. The macrocells are grouped
into 4 Logic Array Blocks (LABs), each containing 16 macrocells and 32
expander product terms. Expander product terms are freely allocatable
product terms that can be used and shared by any macrocell in the LAB.
A Programmable Interconnect Array (PIA) routes signals between the
various LABs. The PIA, which is fed by the 281/0 pins and 64 macrocell
feedbacks, provides the resources necessary to ensure 100% signal
routability. A fixed interconnect delay across the PIA eliminates skew and
provides consistent, predictable performance. For more information on
device architecture, refer to the EPMS016 to EPMS192: High-Speed, HighDensity MAX EPLDs Data Sheet in this data book.
Figure 1 shows a DMA controller that supports the Microprocessor Unit
(MPU), a peripheral, and the memory block of a peripheral subsystem.

DMA
Process

Figure 1. Sample Peripheral Subsystem with an EPM5064 DMA Controller
A peripheral subsystem can be designed
any custom bus protocol with a custom
EPLD DMA controller.

Address

ADDR[19 ..0)

Select

Subsystem

Memory

for

Subsystem

Microprocessor ~~...

Unit

Peripheral

Unit

Figure 2 shows the timing associated with the DMA control signals. A
custom-designed DMA controller in an EPM5064 can improve performance
of the peripheral subsystem by providing faster data transfers than are
possible with the MPU alone. Using a DMA controller also frees the MPU
to perform other tasks.

I Page536

Altera Corporation

I

I Application Briel 84

DMA Controller with the EPM5064 MAX EPLD

I

Figure 2. Generic DMA Timing
CLK

7,/ /

-.-II

OMARa _ _

Peripheral
Interface

Subsystem
[
MPUor
Microcontroller
Interface

OMACK

-----------------~~

OMARO

~Memory to Peripheral Read

.

7,

//

BR -----------.11

-JI

BG _ _ _ _ _ _

//

7/

OS

To start the OMA process, the MPU must first select and initialize the
OMA controller; then it must write the starting and ending addresses and
the control information to the controller. The control data indicates whether
the transfer addresses should be incremented or decremented.
After initialization, the peripheral starts the DMA transfer by asserting the
DMARQ (OMA request) input to the controller. DMARD (OMA read),
another input from the peripheral, indicates the direction of the DMA
transfer. When DMARD is high, the current DMA cycle is a memory-read
cycle; when it is low, it is a memory-write cycle.
After" DMAR Q and DMAR D are asserted, the DMA controller asserts the BR
(bus request) input to the MPU . The MPU then drives BG (bus grant) high
and releases control of the buses. The DMA controller asserts DMACJC
(DMA acknowledge) to inform the peripheral that it controls the buses,
and the DMA cycle can begin.

I Altera Corporation

Page 537

I

1m
I

I DMA Controller with the EPM5064 MAX EPLD

Application Brief

841

To perform the DMA transfer, the control and address buses must transfer
data between peripheral and subsystem memory. DS (data strobe) is a
control bus signal, driven by the DMA controller, that strobes the data
between the peripheral and subsystem memory during the DMA transfer.
The DMA controller simultaneously drives MEMRD (memory read) with
the same logic level as DMAR D and the address bus with the desired
memory address. MEMRD indicates whether a transfer is a read (MEMRD
high) or write (MEMRD low) operation.
On each clock cycle during the DMA transfer, the peripheral writes a new
data word on the bus or reads a data word off the bus until all data words
have been transferred. On every rising edge of DS, the DMA controller drives
a new address, thus transferring a single data word. This process is called
the "burst" mode of DMA transfer.
After the transfer is complete, the DMA controller bus signals are tristated, and bus control is returned to the MPU. The controller negates BR
to inform the MPU that it is finished with the bus. Simultaneously, the
address (A[II ••8]), DS, and MEMRD signals are tri-stated. When the MPU
regains bus control, it resumes execution from its previous state.

EPM5064
DMA

Controller

The DMA controller subsystem is implemented with an EPM5064 EPLD
and an external 74LS373 byte-Wide address latch. This configuration
supports a 20-bit address bus; wider buses can be supported with additional
external address latches. The 74LS373 latches the upper 8 bits of the DMA
transfer address from the subsystem data bus, while the lower 12 bits are
generated by the EPM5064. The lower 12 bits allow DMA transfers of up to
4 K words without processor intervention. The EPM5064 controls the
external address latch from the LDHIGH (load high-order address) and
ENLTCH (enable address latch) signals. LDHIGH loads the upper address
bits from the data bus into the address latch. EtiL TCH enables the latch to
drive its contents onto the address bus.
Figure 3 shows the functional block diagram of the EPM5064 as a DMA
controller. The design consists of three basic blocks: a bus interface unit
(BUS_ltlT), a DMA control state machine (DMA_SM), and an address
generator (ADDR_GEtI). Both BUS_ltlT and ADDR_GEN are hierarchical and
contain other lower-level functions.
MAX+PLUS, Altera's software development tool for MAX EPLDs, supports
hierarchical design entry. MAX+PLU5 allows designs to be entered as
schematics with the Graphic Editor or as text files with the Text Editor and
Altera Hardware Description Language (AHDL). The MAX+PLU5 package
also includes a powerful compiler and timing simulator to provide a
complete CAE system for the most complex deSigns. The EPM5064 DMA
controller design, created in MAX +PLUS, consists of Graphic Design Files
(CDFs) and Text Design Files (TDFs). For example, BUS_ItlT and
ADDR_GEN are GDFs, while DMA_SM is a TDF.

I Page538

A/tera Corporation

1

I Application Brief 84

OAfA Controller with the EPAf5064 MAX EPLO

I

Figure 3. DMA Controller Block Diagram
DMARD

CLK
DATA[7 .. 0)
ICS
AO
AIW
AS

-~~c:::::> AD(11..0)
-~~~DS
-~~c:::::> MEMRD
--=~C> ENLTCH

...

c:~~-

-~-------t~~~ ~~CK

ws

BG

OMARQ
L...-._ _ _ _ _ _ _ _ _ _ _ _ _ _

Bus Interface

--==~

LOHIGH

Figure 4 shows iUS_I1iT, the portion of the design that implements the
bus interface unit. The decoder, shown in the upper left corner of the
figure, uses MPU signals to control data flow within the design. The
74244B, which is the functionalequivalentofa TIL 74244 octal buffer, isan
I/O buffer that supports the bidirectional data bus DATA[7 ••S1. The
input/ control registers receive all inputs from the data bus; the output/
status registers store information to be read onto the data bus. REG_SEL
selects data from one of the two output/status registers to appear at the
I/O buffer. Together, the resources in this design support the following
operations:

o
o

Initialization of the EPMS064 DMA controller
Write and Read operations

Initialization
The subsystem MPU communicates with the bus interface unit to select
and initialize the EPM5064. The MPU must first address the DMA controller
by driving /CS (chip select) low. A write operation is started when AS and
R/LI select one of the input/control registers and LIS (write strobe) is
asserted. For example, when A8 is zero, R/LI is zero .. and LIS has a rising
edge, the eight bits of the data bus are written into input/control
Register 1.

I A/tara Corporation

Page 539

I

I DUA Controller with the EPM5064 MAX EPLD

Application Brief

841

Figure 4. Bus Interface Unit Diagram

r----------------==.:.:::..:....c:::::> LDHIGH
OutputlStalus Reg 1

po----;;.;;,;,CJ ADSTAT[11 ..0J

AO [::;)-::;;:::.;.--ANI L:>~"---ICS [ : : ; ) - - - - - - - -

......c t-'="':~:J CLK

---+--~~::J

RS

c:::Ji':;":;";~---L~
_---~E=>

m

ERR

~~~~ru~T

ADCTRL[11..0)

____________~_____-+___~~

---~~~~LD~AM
----->~~::> DNUP
---~~::-;,.c:::> ACTIVE
-----.-:~::..!..C::> RST

Table 1 shows the bus interface decoding scheme for the MPU signals.
Table 1. Bus Interface Decoding Scheme

I Page540

RS

WS

ICS

.r
.r

L
L

L
L

.r.r

L
L
L
L

RIW

AO

H

H

H

L

L
L

H
L

Action

Read output/status register 1
Read output/status register 2
Write input/control register 1
Write input/control register 2

Altera Corporation

I

IApplication Brief 84

OAfA Controller with the EPM5064 MAX EPLO

I

Write Operation
After selecting the proper register and asserting US, the MPU writes the
least significant byte of the starting address, A[? •• 8l, into input! control
Register 1. Then A[11 ••8l and the MPU control signals ACTIVE (DMA
active), LDSTART (load starting address), DNUP (down up), and RST
(reset) are written into input/control Register 2. ACTIVE and LDSTART, the
input signals to the state machine, indicate that the starting address is tobe
transferred to the ADDR_GEN block. The DNUP signal specifies whether the
DMA address will be decremented (DNUP high) or incremented (DNUP
low). RST, the final MPU signal, reverts the DMA control state machine to
the initial state.

Read Operation
During the DMA process, the MPU may read either of the output/status
registers for the current DMA address or DMA controller status. The least
significant byte of the DMA address, stored in output/status Register 1, is
fed by the ADDR_GEN block. Output/status Register 2 receives the most
significant nibble, A[11..8l, and the status Signal, ERR (error). The ERR
Signal, which comes from the DMA control state machine, indicates an
error condition during a DMA cycle. The REG_SEL function selects which
output/ status register feeds the I/O buffer. The I/O buffer is controlled by
RS (read strobe) and provides the tri-stating necessary to ensure proper
bidirectional operation.

DMA Control
State
Machine

Figure 5 shows the state diagram of DMAC_SM, the DMA control state
machine. The state machine consists of five states: INIT, LOAD, START,
TRANSFER, and ERROR. The state machine design file entered with AHDL,
DMAC_SM, is shown in Figure 6. AHDL supports Boolean equations, truth
tables, IF-THEN statements, and CASE statement constructs, thatfacilitate
state machine design. DMAC_SM.TDF uses an IF-THEN statements to
describe the state transitions.

INIT
DMAC_SI1 is in the INIT state at power-up. While in this state, the MPU
enables the DMA controller. After the ACTIVE and LDSTART inputs are
asserted, the machine proceeds to the LOAD state.

LOAD
When the LOAD state is entered, LDCTR (load counter) drives the starting
address into ADDR_ CNT. The MPU deasserts LDSTART after it has written
the ending address to the DMA controller. The peripheral then activates
DMARQ. When LDSTART is low and DMARQ is high, the machine enters the
START state. DMARQ must remain asserted until the transfer is complete.

I Altera Corporation

Page541

I

Application 8rl.184 1

DMA Controller with the EPMS064 MAX EPLD

Rgure 5. DMA Control State Diagram
TC

RST

RST

IOMARa

TC

IOMARO & ITC

Figure 6. DMA_SM. TOF (Part 1 of 2)
TITLE

EPH5864 DHA Control State Hachine;

Yo

State Hachine Inputs

CLX

:II1PUT;
:II1PUT;
DHARQ
:INPUT;
ACTIVE :INPUT;
:II1PUT;
RST
LDSTART :II1PUT;
: INPUT;
TC

DG

Yo

ERR
DHACX
DR
LDCTR

Page 542

Yo subs~stel'l clock
Yo bus grant
Yo DHA reCfuest
Yo actiyate inithlization
Yo reset error condition
Yo load starting address
Yo terl'linal count

State Hachine Outputs
: OUTPUT
: OUTPUT
: OUTPUT
: OUTPUT

Yo

Yo
Yo
Yo
Yo

se'luence

Yo
Yo
Yo
Yo
Yo
Yo
Yo

Yo

error condition
DHA acknowledge
bus reCfuest
load counter

~
~

~
~

Altera Corporation

I

IApplication Brief 84

DMA Controller with the EPM5064 MAX EPLD

Rgure 6. DMA_SM. TDF (Part 2 of 2)
VARIABLE
SYSCLX
x

x declare

: HODE;
define

~achine

c~cle

clock

s~ste~

with 4 state bits ,[3 .. B] X

c~cle
:HACHIHE
OF BITS ( ,[3 •. B] )
WITH STATES (INIT
LOAD
StARt
TRANSFER
ERROR

BBBBB" ,
BBBB1" ,
BIBBB" ,
BIIBB" ,
BBBIB"

);

BEGIN
SYSCLX = SCLX(CLOCX);
c~cle.CLX
C~CIe

.RESET

SYSCLX;
RSt;

BR
DHACX
ERR
LDCTR
X

CASE

X use
X

X

s~ste~

state
state

clock

~achine
~achine

clock
reset

X use state bits as outputs
X outputs of state ~achine

define state transitions X

c~cle IS
WHEN INIT =>
IF (ACtiVE 8 LDSTARt) tHEN
EHD IF;

c~cle=LOAD;

WHEN LOAD =>
IF (!ACtIVE) tHEN c~cle=INlt;
ELSIF (DHARQ 8 !LDSTARt) THEN
END IF;

c~cle=StARt;

WHEN StART =>
IF (!DHARQ) THEN c~cle=ERROR;
ELSIF (BG) tHEN c~cle=TRANSFER;
END IF;
UHEN tRAHSFER =>
IF (tC) tHEN c~cle=INlt;
ELSIF (!DHARQ) THEN c~cle=ERROR;
END IF;
UHEN ERROR =>
IF (RST) tHEN
END IF;

c~cle=INIT;

END CASE;
END;

I Altera Corporation

Page 543

I

DMA Controller with the EPM5064 MAX EPLD

Application Brief

841

START
In the START state, DI1AC_SI1 outputs BR to acquire control of the
subsystem buses from the MPU. The MPU then sends BG to the state
machine in response to BR.1f the peripheral deasserts DI1ARQ while in this
state, the machine makes a transition to the ERROR state. Otherwise,
DI1AC_SI1 proceeds to the TRAHSFER state when BG goes high.

TRANSFER
DI1AClC is asserted in the TRAHSFER state, indicating that theADDR_GEH
block will begin generating the DMA transfer addresses. The state machine
is reset after receiving the TC (terminal count) signal from ADDR_GEtt.1f
DMARQ is deasserted before TC is true, DMAC_SM again enters the ERROR
state. This condition may occur, for example, if a system power failure
disrupts the DMA process.

ERROR
The ERROR state occurs when a DMARQ low input is received in the START
or TRANSFER state. The RST input of the machine must be asserted to
clear the error condition. The state machine then returns to the INIT state.

DMA
Address
Generation

Figure 7 shows the schematic block diagram of ADDR_GEtt, which
contains three lower-level functions: ADDR_CHT, EHD_COMP, and
OUT _BUF. ADDR_CNT is a loadable counter that generates the lower 12
bits of the DMA transfer addresses. END_COMP compares the current
address with the ending address and terminates the DMA transfer when
the last address is reached. OUT _BUF enables the current DMA transfer
address onto the address bus.
The address range is determined by the starting and ending addresses
read from the MPU. Depending on the system convention, the addresses
maybe generated in increasing or decreasing order. With 12 bits, variable
address ranges up to 4 K words are achievable. When the last address has
been reached, the state machine is reset and the DMA controller may be
initialized for a new DMA transfer.

Control Signals
LDCTR, DtiACI, and DHUP are control inputs from the DMA control state
machine. When lDCTR is asserted and ClI has a rising edge, the 12-bit
starting address is loaded into ADDR_CHT. The ADDR_CHT counter begins
counting when lDCTR is deasserted and DMAClC is asserted. DHUP is from
the bus interface unit AND determines the count direction. When DHUP is
high, the current address is incremented; when DHUP is low, the address is
decremented.
Page 544

Altera Corporation

III

·I Application Brief 84

DMA Controller with the EPM5064 MAX EPLD

I

Figure 7. ADDR_GEN
ADIN[11..0]

...._ _ _ _ _ _ _ _ _.!:!!:L!L!::!.I.!.c:::> ADFB(11 ..0]

lDCTR
DNUP

mMCK
ClK
---.,!::!!:!...!~C> AD(11..0)

-----+------2~!Ic:::> TC

~~------------------========~------~~~=> ENITCH
~----------------------------------~~=>

DMARD

DS

C=~~------~>~------------------------------------~~t=> ~MRD

Output Signals
MEMRD, EtiLTCH, DS, and TC are outputs of ADDR_GEti. The MEMRD
signal, which indicates the direction of DMA transfer, is driven onto the
control bus when DMA begins. EtiL TCH enables the external latch driving
the high-order address onto the address bus. DS provides the gating signal
that the peripheral uses to strobe the next valid address. Ouring a DMA
transfer, DS follows the subsystem clock; otherwise, it is tri-stated. When
the required addresses have been generated, the TC signal becomes active,
signifying that the DMA transfer is complete.
'I
1'1

A/tera Corporation

Page 545

I

---------'----------------------------------------------------------------=<------'.

L-.

Application Brief

DMA Controller with the EPM5064 MAX EPLD

Performance

841

Figure 8 shows the critical timing parameters for the DMA controller:
tDKAV (DtlACX to first valid address), tAVAZ (last address valid to next
address valid), tAVAV (address valid to next address valid), tat 110 Pin

m~tC:~----1--C~:::::::::::::
~~tC:~----1--C~:::::::::::::
m~tC=>---~~~::::::::::::=

::::::::::::~~--1----<::JI~t
::::::::::::~~--1----<::J

~~tC:~----1--C~:::::::::::::
~~tc:~----t--c~:::::::::::::
~~tC:~----1--C~:::::::::::::

::::::::::::~~--t---<::Jlnput

InputlCLKl c:~----.-C~:::::::::::::
InputlCLK2 C:~----,..-C~:::::::::::::

Pin

Input
::::::::::::3~--t---<::J Input
::::::::::::3~--.---<::J InputJCLK4
::::::::::::~~--,..---<::J InputJCLK3
::::::::::::3~--t----<::J,nput

::::::::::::~~--t---<::Jlnput

110 Pin
I/O Pin
I/O Pin
I/O Pin
110 Pin
110 Pin
110 Pin
110 Pin
110
110 Pin
110
Pin

110
110
110
110
110
110
110
110
110
110
110

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

I/O Pin

Pin

Pin

1/0

I!IDl
I!IDl

Altera Corporation

Pin
Pin

Pin
Pin
Pin

Global Macrocells

Local Macrocells

Page 549

Application Brief 85

DRAM Controller with the EP1830 EPLD

I

Addressing DRAM through multiplexed address pins requires two steps:1
1.

The row address is placed at the DRAM address pins and I'RAS is
asserted, latching the row address of the desired memory location.
The column address is placed on the DRAM address pins and I'CAS is
asserted, latching the column address of the desired memory location.

2.

The slash character (I') indicates that the signals are active-low. The
memory location with the latched row and column addresses can then be
written to or read from. When the I'RAS and /CAS pins of the DRAM are
deasserted, the memory transfer is completed.
Logic is required to control the memory transfer and refresh cycles in
DRAM designs. The EP1830 design described in this application briel
implements the logic necessary to control the multiplexing of the row,
column, and refresh addresses; to generate the /1 AS and /CAS signals; and
to initiate the required refresh cycles. Each location must be periodicall}
refreshed to ensure memory integrity. The RAS-onlyrefresh method, whid
is used for this application, places a refresh address on the DRAM addres~
pins and asserts ,.lIAS.
Figure 2 shows a block diagram of a 68030-20-based DRAM subsystem
The microprocessor accesses memory with a programmable DRAN.
controller implemented with an EP1830 EPLD. The subsystem contaim
8 MBytes·of DRAM. A 32-bit bus transceiver controls the direction of thE
data bus, and an octal bus driver buffers the DRAM control signals.

68030 DRAM
Subsystem

Figure 2. 68030-20-8ased DRAM Subsystem
80 MHz

~-----I

Microprocessor

68030-20

Reset

(20 MHz)

Dynamic RAM

Master

(SMbytes)

EP1830

TC511001 )( 64

RESET ....~--+-.
ClOCK/'4---..........

A(23 .. 0)J------I~
lAS

~

1-----"

___~ A{9 •. 0)

74244

S l Z o l - - - - -. .

IRASl

Buffer )( 2 I----t~ IRASO

S I Z 1 1 - - - - -. .

I----t~
I----t~
I----t~

IOSACKl

ICAS3

ICAS2
ICASl

--~____~--~~ICASO

RlWi----------------...--------------------+-iIWRlTE

D{31"O) . .----~1

DIR

74245

. .------~~ D{31..0)

Transceiver )( 4

I Page550

A/tera Corporation ."

·1

Application Brief 85

,DRAM
,Configuration

DRAM Controller with the EP1830 EPLD

I

Sixty-four Toshiba TC511001AP 1-Mbyte DRAMs provide the memory in
this system. The organization of the DRAM devices on the 32-bit bus of the
68030 microprocessor is shown in Figure 3. The memory is broken into
2 rows and 4 columns, requiring 2 /RAS and 4 /CAS signals for control.
Each row and column location has 8 DRAM devices, each providing
1 Mbyte of DRAM. The DRAM controller generates I'RAS and I'CAS
signals to address individual DRAM locations. One memory-transfer
operation can address 1, 2, 3, or 4 bytes of information by selecting the
appropriate number of columns.

'Figure 3. DRAM Memory Organization
Column 1

DRAM
Operation

Column 2

Column 3

Column 4

DRAM is accessed when the microprocessor issues a memory request or
when the DRAM controller initiates a refresh operation. Both operations
are controlled by the DRAM controller implemented with the EP183O. The
DRAM controller provides the DRAM and the 68030 with the following
signals.

Microprocessor-Initiated Memory Transfer Cycle
The 68030 initiates a memory request by placing a DRAM address on the
address bus A[31..8l and asserting I'AS (Address Strobe). The size of the
data transfer is indicated by the SIZI and SIZ8 control signals. The
decoded signals are shown in Table 1.

.1 Altera

Corporation

Page 551

!r:.1
~

I DRAM Controller with the EP1830 EPLD

Application Brief 85'·
..-

Table 1. Data Transfer Size
SIZ1

SIZO

L
H

H
L
H
L

H
L

:

Transfer Size (Bits)

8
16
24
32

The DRAM controller responds to the memory request by placing the row
address on the DRAM address lines A[9 .. 8l; then the appropriate row I
address strobe /RASx is asserted. Next, the column address is placed on
the same address lines, and from up four /CASx column address strobes
are generated. The DRAM controller indicates that the DRAM access is
completed by asserting one or both of the data select acknowledge signals
(/DSACJCl and /DSACJ(8). These signals also indicate the width of the
data port being accessed. The decoded signals are shown in Table 2.
Table 2. Port Width
IDSACK1

IDSACKO

Accessed Port Width (in bits)

H
H
L
L

H
L
H
L

Insert Wait States

8
16
32

Because this DRAM subsystem has a 32-bit port, the DRAM controller can
drive /DSACJCl and /DSACJC8 with a common signal, /DSACJC. The
microprocessor deasserts /AS to indicate that the memory transfer is,
complete. The DRAM controller thendeasserts /RAS, /CAS, and /DSACJC ..
The timing for this memory access operation is shown in Figure 4.

DRAM Controller-Initiated Refresh Cycle
Each address location" in a DRAM device must be refreshed (within a
period of time specified by the DRAM manufacturer) to ensure data
integrity. When a refresh cycle is required, the DRAM controller places the
refresh address on A[8 .. 8l and asserts all /RASx signals, refreshing all
address locations with a row address equal to the refresh address. (Only 9
of the 10 address lines are needed for refresh cycles because each DRAM
device contains 512 rows.) After the /RASx lines have been asserted for at
least the specified minimum time, they are deasserted. This RAS-only
refresh cycle is the method used by the DRAM controller in this application
brief. The timing for the refresh operation is shown in Figure 4.

I Page 552

Altera Corporation

II,~

I Application Brief 85

DRAM Controller with the EP1830 EPLD I

Rgure 4. Memory Transfer Cycle and DRAM Refresh Cycle
Memory Transfer Cycle
Clock

---.J

L

L...J
~----------------~/
~

__________________________ ______
~x~

xColumn Address X~____

_ _ _ _ _ _ _ _ _---J

~--------------~/
,'-_ _ _....J/
,____....J!

IOSACK

DRAM Refresh Cycle

L...J

Clock

ORAM[8 .. 0]
JRASx

L

____________~X~______R_ef_re_sh_A_~_r_es_s______Jx~______
,

!

ICASx

IOSACK

The DRAM controller generates all signals necessary to control these
operations. If a memory and refresh request are received at the same time,
the refresh operation is given priority. If a refresh request is received
during a memory cycle, the cycle is completed before the refresh operation
is finished. The EP1830 EPLD can integrate the entire DRAM controller
while operating at the speeds of the microprocessor and DRAM devices.

DRAM
Controller
II Altera Corporation

!'r:W
I.I!.

Figure 5 shows a block diagram of the DRAM controller, implemented in
the EP1830 with four functional blocks: the RAS/CAS generator (state
machine), the refresh timer, the refresh address counter, and the address
multiplexer. Each function is designed separately, and the symbols are
Page553

I

I DRAM Controller with the EP1830 EPLD

Application Brief

851

Figure 5. B-IIbyte DRAM Controller
System Address
DRAM Address [9 ..0)

Clock

IDSACK

lAS

IRAS{1 .. 0)

SIZ[1..0)

ICAS{3.. 0)

Reset

automatically generated by the A+PLUS software. The operation of each
functional block is described here.

RAS/CAS Generator
The RASjCAS generator is a state machine that generates the DMA
controller's /RAS, /CAS, and /DSACX signals (Figure 6). The generator
uses the State Machine File (SMF) format that integrates control logic in
Altera's EP-series EPLDs. This state machine has 18 states and 9 state bits.
The value of the state bits for each state is shown in the States Subsection of
the design. The States Subsection is followed by the Transitions Subsection,
which defines state machine transitions with IF-THEN statements.

Figure 6. RAS/CAS Generator State Machine File (Part 1 of 3)
PART: MACRO
ItIPUTS:
A22 Al Ae
SIZI size
AS
CLX
RQREF
OUTPUTS:
RASI RAse RAS
CAS3 CAS2 CASI CAse
DSACX REF
tlETYORX:
RAsa
RASI

I Page554

II
l
i

COtlF(RASe,)
COtlF(RAS1,)

III

Altera Corporation

I

I Application Brief 85

DRAM Controller with the EP1830 EPLD

I

Rgure 6. RAS/CAS Generator State Machine Rle (Part 2 of 3)
EQUATIOrtS:
RAsa'
RAS1'
"ACHlrtE:
CLOCK:

MeMDr!l

CLK

STATES:
BEGirt
IDLE
RASxa
RASd
RASx2
RASx3
RASxCax1
RASxcax2
RASxCax3
RASxCax4
RASxClx1
RASxClx2
RASxCh4
RASxC2x1
RASxC2x2
RASxC3x1
REFa
REF!
BEGirt:

(RAS a A22') + REF';
 4). The HAS signal remains asserted during this cycle. The
/CAS signals asserted are based on the starting column and the size of the
transfer. /DSACX is also asserted during this cycle, indicating that the data
is valid. Once I'AS is deasserted, the state machine goes back to the IDLE
state.
When the refresh timer sends a refresh request, the state machine goes
from IDLE to REFO. The I'HASl and /RASO signals are asserted to refresh
both rows of the memory configuration. During the next clock cycle, the

IPage 556

Altera Corporation

I"

I Application Brief 85

DRAM Controller with the EP1830 EPLD I

Rgure 7. RASiCAS Generator State Diagram

state machine goes to state REF1, while I'RAS8 and I'RASl remain
asserted. This state ensures the 90-ns minimum RAS period during the RASonly refresh cycle. The machine then goes to the IDLE state at the next clock
cycle, and the I'RASx signals are deasserted. The state bits 08 and 01 are
used to distinguish states with otherwise equivalent state values.

Refresh Timer
Figure 8 shows the refresh timer. Each of the DRAM devices described in
this application brief has 512 rows that must be refreshed at least once
every 8 ms. Since each request refreshes one row, a request must be issued
once every 15.6 Jls (8 ms/512 rows). With a clock frequency of 20 MHz, a
refresh request should be issued every 312 clock cycles (15.6 Jls x 20 MHz).
The refresh timer is a free-running counter that counts from 0 to 311 and
back to O. Two signals are generated when a refresh is reqUired: the first is
an unlatched signal that is true whenever the counter is at 311; the second
sets a latch that represents a refresh request to the RAS/CAS generator
whenever the counter is at 311. The latch is cleared when the RAS/CAS
generator acknowledges the request with the REF state bit.

Altera Corporation

Page557 I

iII
I

Application Brief 85

DRAM Controller with the EP1830 £PLD

II

Figure B. Refresh Timer

NOT

;" •... 'CONi":

:................1

ROW

AN012

REF

CREF
INP

c:>-===========:::tt------'

CLK
INP
CLR INP

IPage 558

Altera Corporation

II

i

I Application Brief 85

DRAM Controller with the EP1830 EPLD I

Refresh Address Counter
The refresh address counter increments through the 512 rows that need to
be refreshed. It is a 9-bit up-counter with Enable. The counter is enabled by
the refresh timer when a refresh is required. Each refresh cycle refreshes
the row address equal to the value of the counter. See Figure 9.
Rgure 9. Refresh Address Counter
ENC>-~--------H

elK

IAltera Corporation

INP

C>--+----.-~

IN!'

Page 559

I DRAM Controller with the EP1830 EPLD

Application Brief 85

I

Address Multiplexer
The address multiplexer decodes the state of the RAS/CAS generator state
bits to determine the address for the DRAM devices. During the IDLE and
RASxn states, the row address (A[21_121) is selected. During the RASnCxm
states, the column address (A[11..21) is selected. During the REFe and REF1
states, the refresh address from the refresh address counter is selected.

Top-Level Schematic
The four separate deSigns are integrated in the schematic (see Figure 10).
A+PLUS allows text- and schematic-based designs to be combined into a
single design, enabling the user to represent each major function of the
design in the most intuitive form. The design is then processed by the
Altera Design Processor (ADP) and simulated with the A+PLUS Functional
Simulator (FSIM). Thus, the entire process of entering. processing. verifying,
and programming a design is completed with Altera's A+PLUS
Development System.

Conclusion

IPage 560

The EP1830 EPLD is ideal for integrating custom subsystem functions or
other PLD devices, including the custom DRAM controller described in
this application brief. The DRAM controller application only requires a
clock speed of 20 MHz, although the EP1830 is ca pable of running counters
at 50 MHz. TogetherwithA+PLUSdesign tools, the EP1830effectivelyand
quickly reduces board space, lowers power, and increases system reliability.

A/tera Corporation III!:

I Application Brief 85

DRAM Controller with the EP1830 EPLD I

Figure 10. DRAM Controller Schematic
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2

A21
A20
A19
A18
A17
A16
A15
A14
A13
A12

CLOCK

/cASO
ICAS1

RESET
INP

/cAS2
/cAS3

AD

A1
A22
lAS

SIZO
SIZ1

Altera Corporation

L. ..............l

IRAS1

Page561 I

ill

Contents
October 1990

~ection

11

General Information
Electronic Bulletin Board Service ................................................................. 565
Ordering Information .................................................................................... 567
EPLD Package Outlines ................................................................................. 569
Thermal Resistance (OC/W) .......................................................................... 582
AB46 Selecting Sockets for J-Lead Packages .......................................... 583
Sales Offices, Distributors & Representatives ............................................. 587

iII
lItera Corporation

Page 563

I

Electronic Bulletin
Board Service
October 1990, ver. 1

Introduction

Altera provides an Electronic Bulletin Board Service (BBS) for continuous
access to up-to-date EPLD and development tool information, electronic
application notes and briefs, data sheet updates, customer newsletters,
and useful utility programs. The BBS also supports file transfers to and
from the Altera Applications Engineering Department. Owners of A+PLUS
and MAX+PLUS software may refer to their user manuals for detailed
information on using the BBS.
The telephone number for the BBS is (408) 249-1100. To connect to the BBS
via modem, the following equipment and configuration are required:

Modem Number:
(408) 249-1100

o
o
o

Baud rate of 1200 or 2400
Bell Standard 212A or compatible modem
Data format: 8 data bits, 1 stop bit, no parity

The following file transfer protocols are supported:

o
o
o
.ogging On

Xmodem (Checksum)
Xmodem-CRC (CRC)
Ymodem (lK-Xmodem)

o
o
o

Ymodem-G (lK-Xmodem-G)
ASCII (Non-Binary)
Kermit

After the BBS connection has been established, the user may choose between
graphic (for EGA or VGA displays) or non-graphic display mode. The user
is then prompted for his or her name; a new user may also choose a
password. Each name and password are recorded for future log-ons.
A series of screens appears automatically: the Altera News screen, the
Personal Mail screen, and the Settings screen. The Main Menu, from which
all functions are accessed, appears next. The most commonly used functions
are: F)ile Directories, U)pload a File and D)ownload a File. On-line help is
available with the H)elp Functions command. The F)i1e Directories
command displays a list of directories containing files that can be
downloaded. (Uploaded files are stored in a private directory.)

:ile
,Jploading

The File Upload service is available for uploading files that require analysis
or correction by an Altera Applications Engineer. All files that are uploaded
to the Altera BBS are automatically stored in a private directory. When a
file is uploaded, the file description should include the name of the Altera
Applications Engineer who has been asked to examine the file.

IAltera Corporation

page56sl

ill

I Electronic Bulletin Board Service
File
Downloading

Files may be copied from the following six directories:
1. From-Altera File Directory
This directory is a general directory for downloading files from Altera
Applications, for example, after a problem or question has been analyzed.
2. Engineering Application Briefs
This directory contains Electronic Application Briefs (EABs) and Notes
(EANs), which provide up-to-date information on using Altera EPLDs
effectively.
3. Engineering Application Utilities
This directory contains Electronic Application Utilities (EAUs) that
complement Altera software and aid EPLD design. Three commonly used
utilities are described below. A full description of all available utilities is
given in Application Brief73 (Software Utility Programs) in this data book.
PLD2EQN The PLD2EQN utility converts common PAL/GAL/PLA
JEDEC files to Altera Hardware Description Language (AHDL) files thai
are compatible with the MAX +PLUS software. This utility can also producE
an Altera Design File (ADF) that is compatible with A+PLUS software.
JED SUM The JEDSUM utility calculates the EPROM data checksum,
file transmission checksum, and the number of programmed architecturE
bits contained in an EPLD JEDEC file.
AVEC The AVEC utility adds functional test vectors to EP-series EPL[
JEDEC files. AVEC translates the table output files generated by thE
A+PLUS Functional Simulator's functional vectors. Third-part)
programmers (e.g., Data I/O 29B and UniSite 40 machines) have built-ir
hardware drivers that can apply these vectors to a programmed EPLD.
4. Altera Customer Newsletters
This directory contains Altera newsletters that provide current news or
EPLDs and development tools, and "Question and Answer" pages tha'
answer many common questions asked by Altera customers.
5 & 6. A+PLUS and MAX+PLUS Macrofunction Exchange Libraries
I

These directories are used to publicly exchange A+PLUS and MAX+PLUSI'I
macrofunctions. Customers may download any macrofunctions in thi~
directory. Macrofunctions that have been uploaded to be shared wit~
other users are also placed here by the system operator ("Sysop").

IPage 566

Altera Corporation III

Ordering Information
October 1990, ver. 1

IOrderin g
'IEPLDs

Figure 1 shows how an EPLD part number is constructed. For information
on specific package, grade, and speed combinations, refer to individual
EPLD data sheets or the Product Selection Guide in this data book, or
telephone the Altera Marketing Department at (408) 984-2800.
MIL-STD-883-compliant product specifications are provided in Military
Product Drawings (MPDs) that are available on request from Altera
Marketing. These MPDs should be used for the preparation of Source
Control Drawings (SCDs).

Figure 1. EPLD Package Ordering Codes
EP 610 D M 8838 -1
----FAMILY SIGNATURE - - - - - - - - '
EP:
General-purpose "classic" EPLD
family
cPS:
SAM and STG EPLD families
EP8:
Micro Channel EPLD family
EPM:
MAX EPLD family

L

lEVICE TYPE --------~
~P:
310, 320,330,600,610,630,610A,
910, 1800, 1810, 1830
:PS:
448, 464
:P8:
2001, 2002A
:PM:
5016,5032,5064,5128,5130,5192
.lACKAGE TYPE _ _ _ _ _ _ _ _ _.....J
):
).
I:
_.

L

SPEED GRADE
See Product Selection Guide or individual EPLD data
sheets in this data book for speed/product
relationships (e.g., -1, -2, -30, -45, or blank)

MILITARY PROCESSING
8838
Processed to MIL-ST0-883, current revision
8838X Processed to MIL-ST0-883, current revision
8838-1 Processed to MIL-ST0-883, current revision
Fully compliant with deviation to MIL-STD-883,
8
current revision (consult Altera on specific
deviations)
DESC Standard Military Drawing (SMD)
5962

~---

Windowed ceramic dual in-line (CerDIP)
One-time-programmable plastic dual in-line (PDIP)
Windowed ceramic J-Iead chip carrier (JLCC)
One-time-programmable plastic J-Iead chip carrier (PLCC)
3: Windowed ceramic pin-grid array (PGA)
.): One-time-programmable plastic small-outline integrated
circuit (SOIC)
:J: One-time-programmable plastic quad flat pack (POFP)
N: Windowed ceramic quad flat pack (WOFP)

OPERATING TEMPERATURE
C: Commercial (0° C to +70° C)
I: Industrial/Automotive (-40° C to +85° C)
M: Military (-55° C to +125° C)

fxamples:
EP1810GI-40

EP1810 in a windowed ceramic pin-grid array package, industrial temperature range,
-40 speed grade (tpD1 = 40 ns).

EPM50320M883B

EPM5032 in a windowed ceramic dual in-line package, MIL-STO-8838-qualified.

EPS448LC-25

EPS448 in a plastic J-Iead chip carrier package, commercial temperature range, -25
speed grade ('MAX = 25 MHz).

Altera Corporation

Page

5671

I Ordering Information
Ordering
Software &
Hardware

Altera development systems, software, and hardware should be ordered
by the designations given in the Product Selection Guide in this data book.
Table lUsts the part numbers for programming adapters. Refer to individual
data sheets in this data book for detailed information on software and
hardware products.
Table 1. EPLD Adapter Support
EPLD
EP330

!

Package

Part Number

DIP
J-Lead

PLED330
PLEJ330
PLES330
PLED610
PLEJ610
PLED630
PLEJ630
PLES630
PLED910
PLEJ910
PLEJ1810
PLEG1810
PLEJ1830
PLEG1830
PLED448
PLEJ448
PLED5016
PLEJ5016
PLESS016
PLED5032
PLEJ5032
PLESS032
PLEJ5064
PLEJS128
PLEGS128
PLEGS130
PLEOS13O
PLEJS192
PLEGS192
PLEOS192
PLEJ2001

sOle
EP600/61 0
EP600/61 0/630/61 OA

DIP
J-Lead
DIP
J-Iead

sOle
EP9001910
EP1800/1810
EP 18001181 011830
EPS448
EPM5016

DIP
J-Iead
J-Iead
PGA
J-Iead
PGA
DIP
J-Iead
DIP
J-Iead

sOle
EPM5032

DIP
J-Iead

sOle
EPMS064
EPM5128
EPMS130
EPMS192

EPB2001

IPage 568

J-Iead
J-Iead
PGA
PGA
OFP
J-Iead
PGA
OFP
J-Iead

I

Altera Corporation . 1

EPLD Package Outlines
Data Sheet

October 1990, ver. 1

Introduction

I

This data sheet provides package outlines for all Altera EPLDs. Table 1
shows the type of packages, lead materials, and lead finishes available.
Table 1. EPLD Packages
Package Type

Package
Code

Lead
Material

Ceramic dual in-line

0

Alloy 42

Solder dip over tin flash (Military)

Plastic dual in-line

P

Copper

Solder dip (60/40)

Ceramic J-Iead

J

Alloy 42

Solder dip (60/40)

Plastic J-Iead

L

Copper

Solder plate (60/40)

Ceramic pin-grid array

G

Alloy 42

Gold over nickel plate
Solder plate (60/40)

Lead Finish

Matte tin plate

Plastic small-outline IC

S

Copper

Ceramic quad flat pack

W

Alloy 42

Matte tin plate

Plastic quad flat pack

a

Copper

Solder plate (60/40)

Package outlines are listed here in ascending size order. The dimensions
shown are nominal with a tolerance of ± 0.020 in. (0.51 mm) unless
otherwise indicated. Maximum lead coplanarity is 0.004 in. (0.10 mm).
20-Pin Ceramic Dual In-Line Package (CerDIP)
For military-qualified product see case outline D-8 in Appendix C of MIL-M-38510.
WINDOW

.005
MIN

.210
.110

.035--L~~1
T
]"

.015

-I I~~

~Altera

Corporation

-II.020
.016

SEATING
PLANE

ill

.145
.065-:125
.050

Page 569

I

I EPLD Package Outlines

Data Sheet

2O-Pin Plastic Dual In-Line Package (PDIP)

I

.055
.045

1 t-

11=

pw,l::::::::]

1.035 - - - - I .170
1.025
.140

. 145
.125

.;--------------~~ ~
I .
- - +---L

t

-I.100Iasc

-II.020

t

SEATING
PLANE

.135
.125

.016

2O-Pin Plastic J-Lead Chip Carrier (PLCC)

j-

SEE

DETAIL

__ /

..L----f,r-.:.l ,~,

Ua"

~

f
.430
.390

DETAIL

"a"

20-Pin Plastic Small-Outline IC (SOIC)

IPage 570

Altera Corporation II~

I Data Sheet

EPLD Package OuUines

I

24-Pin Ceramic Dual InLine Package (CerDIP)
For military-qualified
product, see case outline
0-9 in Appendix C of
MIL-M-38510.

.320
~

.210
.170

.035-.!..~~1
.I"

.015T

~4-Pin Plastic DIP

-I.100I-

-II-.020

BSC

.016

'" "
flBB\\~

SEATING

:-tl T·oos
J

PLANE

.145

-:125

.065
.050

.395
.365

.055
.045

1 t-

11:3

PIN,t::::;:::::!1
1.240

.170
.140

.'45[~r---------'

:i25
.020
MIN

~4-Pin Plastic

~.020
TYP.

J~-t *~ ~E:~'~
~ ~ or- To
}35
:i25
1

BSC

.016

Small-Outline IC (SOIC)
-.614
~9

"

I

,

I

:D~ ::::::::::
PIN ' __

.037 i
.... I

~

:11

.. TVP

J1nJU1QD r.lAD nrld.:JSEATING ,..

J l.-

~ ~

.~

.014
.019

TYP

.050

.012

TVP

=".,.!,X ":1
I

.104

-

Altera Corporation

50

.003

TVP

J [f=0"-8

0

ill

TYP

PLANE
::

Page571

I

I EPLD Package Outlines
28-Pin Ceramic DIP

WINDOW

Data Sheet

I

Altera Corporation

I·~.

28

.150 X .250~_~1

.005
MIN.

1+----

1A60

-----t

1.440

.210

28-Pin Plastic DIP

.055
.045

28-Pin Plastic Small-Outline IC (SOIC)
I

I

.697
•713

--

•

I

:D~ ::::::::::::

PIN 1

IPage 572

:11

Data Sheet

EPLD Package Outlines

I

28-Pin Ceramic J-Lead Chip Carrier (JLCC)
For military-qualified product, see case outline in Altera Military Product Drawing 020-00194_

Ti=\

""_1_-t----,f---....LWINDOW

.032 L-*-IFt._
.028 -r-*-tr-tI-

.495 .465
.485 .430

::~I

.050
.030
.120
.090

.495
.485

-

.440
.380

DETAIL "8"

28-Pin Plastic J·Lead Chip Carrier (PLCC)

.021

.430

3

=jl
-

-~
.485

4T

_Il.1

.028

.010

.008

ll-·~MI~

J

t

.025 MIN

.120
.090

.180
.165

.020R MIN

ill

DETAIL "8"

I

Altera Corporation

Page 573

I

I EPLD Package Outlines

Data Sheet

4O-Pin Ceramic Dualln-Line Package (CerDIP)
For military-qualified produc~ see case outline D-5 in Appendix C of M/L-M-38510.

•005
MIN.

.220
.180

'035-L~==============.~1
]"

.015T

-l I.100
BSC

.020

-:016

SEATING
PLANE

.145
.125

.065
.050

40-Pin Plastic Dual In-Line Package (PDIP)
.055
.045

PIN 1

1+--------

2.070
2.058

I

-----------1.

.175
.165

~

.1551]

~

J

.020
MIN

IPage 574

:m.

--1 J
t
t

~

1JBSC

-i;-:016

.1~

.120

SEATING
PLANE

~L.MO~
.610

A/tera Corporation

I

I

I Data Sheet

EPLD Package Outlines

44-Pin Ceramic J-Lead Chip Carrier (JLCC)

r

"~~IX45D
II

For military-qualified product, see case outline
J-tt in Appendix C of MIL-M-385tO.

~

PIN1

I

SEE
DETAIL

/__ /"S"

----t-

.&g5 .665
.685 .630

I

WINDOW

.500
REF-==----

-++t----+-

.580

71

:L

t

.050
.030

_

.050

ssc

.000RMIN

J

.190
.155

.120

-

.090

DETAIL UB"

"iTI_

J4-Pin Plastic J-Lead Chip Carrier (PLCC)
PIN

1--=-O_______..L

.695 .656
.685 .650

.656
.650
.&g5
.685

~

.010
.008
.025 MIN
.050

.120
.090

ssc

MIN
.165

iD

DETAIL "S"

Altera Corporation

Page 575

I

I EPLD Package Outlines

Data Sheet

I'

68-Pin Ceramic J-Lead Chip Carrier (JLCC)
For military-quali6ed product see case outline C-J2 in Appendix C of MIL-M-38510.
.CM5X45"~

SEE

PIN 1

'\

r

WIN DOW

/

1115 .965

985.930

(1(
~LJ

.BOO

REF

.840
.880

~it------

:==:j

.050
-.030
.050

8SC

.985

.120
-.080
.190
.155

DETAIL "8"

I Page 576

Altera Corporation

!:I~

'i

I Data Sheet

EPLD Package Outlines

I

68-Pin Plastic J-Lead Chip Carrier (PLCC)
.045 x

PIN 1

I~

45°\
'Y

0

.

.885
.985

.958
.850
.995
.985

~~~

-'-

.950

•

DETAIL "8"

is-Pin Ceramic Pin-Grid Array (PGA)
For military-qualified product, see case outline in Altera Military Product Drawing 020-00205.

[t

.1401~

1.120~

.115

1.080

.610
.600

I

.095_
.075

.185
r.175

WINDOW

@

.070 DIA. TYP.
A1

iD
'A/tera Corporation
Page 5771
.I--------------------------------____________________________________________
~.

I EPLD Package Outlines

Data Sheet I:
SEE
DETAIL

84-Pin Ceramic J-Lead Chip Carrier (JLCC)

r

045145"\

WlNDOW

1

/.

1--_ _ _ _ 1.200

1.180

~

-r----T

r
~:r

~:~:~I

,.._/"8"

l

I

1.140
1.080

......----

~I

il

JL
.050

8SC

j

..!.I -

.050
.030

-

.120
.090

I- I

.110

_

.155

.020R MIN

I Page 578

Altera Corporation II~

II Data Sheet

EPLD Package Outlines

'84-Pin Plastic J-Lead Chip Carrier (PLCC)

.048
.042

PIN

.045 x 4 5 ° \

SEE
DETAIL

"B"

1\

~

0

~

1.158
1.150
.195
_1_
1.185

.048

1-

T
~
1.090

1.000
REF.

IrJrJrJrJl

.1

1.158
1.150

.

.

1.195
1.185

I

1

.016

.JL

-

.050
BSC

.025 MIN
.120

-.090
.02ORMIN

.1110
.165 -

'4-Pin Ceramic Pin-Grid Array (PGA)
1.120

-

.140-1-1

.'::~

1.080
.715
.705

r

WINDOW

I

r r:::
'-.005.

.715
.705

o

.070 DIA. TYP.

A1

L

:::tr. . .

EF.

;4ltera Corporation

Page 579

I

I EPLD Package Outlines

Data Sheet

LJ

Ii"

100-Pin Ceramic Pin-Grid Array (PGA)

CtI
I

1.340
1·390
.715
.705

I

I /V

.140-j~

.; ~I. f- r:::

1.215

1.185

WINDOW

'-.OO5R

I

8jV

.715
.705

L
D>

.070 DIA. TYP•

.055j IL
.045

~!:.008 REF.

100-Pin Ceramic Quad Flat Pack (WQFP)
1.50
1.00

PIN 1

/.--,

,
\

I~

SEE
DETAIL

"B"

n401a40 ~~~-I-------4------- __~==___
noo 1aoo

WINDOW

I Page 580

Altera Corporation i:II

I Oats Sheet

EPLo Package Outlines

I

fOO-Pln Plastic Quad Rat Pack (PQFP)
PIN 1

,

I

/-'-,

'\
SEE
, !...- DETAIL

"8"

-L
t,30
-L,I5BSC

t
~

20. •

23.00 1tUO

DETAIL "B"

ill
I

Altera Corporation

Page 581

I

Thermal Resistance
(Oe/W)
IOctober 1990, vsr. 1
Introduction

Data Sheet

I

Table 1 gives thermal resistance data for Altera EPLOs. All thermal
characteristics are measured using the Temperature Sensitive Parameter
(TSP) test method described in MIL-STD-883C, Method 1012.1. Thermal
resistance values were measured with the package soldered into a PC board
(excluding 24-pin CerOIP and POIP, which were socket-mounted), at 25 OC
ambient temperature with no backplane or heat sink, and are accurate to
±5°C/W.
Table 1. Thermal Resistance
Number of Pins

Package

20

CerDIP
PDIP
PLCC
SOIC
CerDIP
PDIP
SOIC
CerDIP
PDIP
JLCC
PLCC
SOIC
CerDIP
PDIP
JLCC
PLCC
JLCC
PLCC
PGA
JLCC
PLCC
PGA
WQFP
PQFP
PGA

24
28

40
44

68

84

100

9JA (0 CIW)

9JC (0 CIW)

62

17
14
27
25
8
11
25
24

65

103
90
64
64

92
52
62
72
85
90
40

46
68

49
47
41
43

24
38

18
30

48

16

40

16
27
25
7
19
16
14
7
15
5
6
15
5
8
13
4

Note: The formula for detennining ~x is ~ = ITJ - TA)/PD, where TJ = die junction
temperature; TA =ambient temperature; and PO =power being dissipated in the device causing
a temperature rise at the die junction. TJ is determined by characterizing the relationship
between the forward-biased voltage and temperature of the isolation diode between the power
and ground pins of the Ie

IPage 582

Altera Corporation 11

Selecting Sockets for
J-Lead Packages
1

Application Brief

October 1990, ver. 3

Introduction

461

EPLDs solve many of the problems designers face today. They offer low
costs, low power, high reliability, and most importantly, high integration
density. Altera offers windowed ceramic and plastic J-lead chip carrier
aLCC/PLCC) versions of many EPLDs to further reduce the "real estate"
demands of a system. These small packages are generally intended for
surface mounting. This application brief discusses the following topics:

o
o
o
o

Types of sockets available for J-Iead EPLDs
Criteria for selecting burn-in or production sockets
Carrier boards for use with wire-wrap panels and J-Iead packages
Results of Altera's evaluation of 68-pin production sockets for use
with windowed ceramic J-lead EPLDs

Despite recent advances, the acceptance of surface-mounting technology
has been slow, although considerable research and use have proved its
feasibility. Most industrial applications still use traditional through-hole
soldering. Surface-mount assembly places unique demands on the
development and manufacturing processes: it requires different CAD
symbols for PC board layout, different test and reliability procedures for
buried vias within PC boards, and a different soldering process for
production (vapor phase versus wave solder). Bonding EPLDs to a PC
board also removes the possibility of convenient erasure and
reprogramming, which are particularly important during development.
A popular compromise that preserves the advantages of J-Iead packages
without the complications of surface mounting is to socket the J-lead
EPLD. Conventional mounting techniques can then be used, either by hole
soldering to a PC board or by mounting in a socketed carrier board for wire
wrap.

Mechanical
'Considerations
I

A/tera Corporation

There are two distinct types of sockets: burn-in and production sockets.
Burn-in sockets are zero-insertion-force sockets. Since they will not deform
the device's leads, they are the preferred carrier for an EPLD during the
prototyping phase of a design. Older-model burn-in sockets had the
disadvantage of being significantly larger than production sockets; newer
burn-in sockets are now available with dimensions similar to those of
production sockets. Using a burn-in socket during prototyping is the best
way to prolong the life of a windowed ceramic EPLD.

PBge583

I

ill

I Selecting Sockets for J-Lead Packages

Application Brief 46

I

Once a design enters the production phase, cost becomes a major concern.
Low-cost production sockets, designed to hold a device permanently and
securely, are widely available. Obviously, they must exert a reasonable
force on the leads to prevent the device from popping out. After several
insertions, this force can deform the leads, and eventually the leads can
short out or fail to make contact, making the EPLD unusable. Therefore,
Altera strongly recommends using a burn-in socket during the design and
development phases.
Production sockets must be chosen carefully. If the EPLD needs to be
removed many times for reprogramming, low-insertion-force sockets that
will not significantly deform the device pins for as many as ten insertions
are preferable. For high-stress environments (e.g., G-forces, thermal shock,
humidity), sockets with high insertion forces and optional retention clips
are available. To further reduce the possibility of deforming device pins,
most manufacturers of high-quality sockets include a stand-off inside the
socket that prevents a device from being forced too far into a socket and
becoming bent.

Socket
Evaluation

Altera has tested several production sockets for use with 68-pin windowed
ceramic J-lead EPLDs. Each socket underwent three tests:
1.

The change in the gap between the corner pins of each device was
measured before and after each of 10 insertions.

2.

Each pin of the socket was wired in series and tested for open or short
circuits lasting longer than 10 J.1S. This opens-and-shorts test was
performed while the socket was attached to a vibration block. The
amplitude of vibration was 3.0 mm peak-to-peak at a frequency that
varied from 10 Hz to 55 Hz to 10Hz, in I-min. cycles for 2 hours. The
ambient temperature was 70° C for this test. The vibration test was
performed on all three axes at a temperature of 70° C.

3.

The actual point of contact between the socket pin and the device lead
was photographed to determine the direction of the forces between
them and the amount of surface contact.

Of the seven sockets tested, only four passed; three sockets failed thel,.
opens-and-shorts test. Table 1 shows a ranked list of the sockets thatl
passed. Ranking was determined primarily by each socket's ability toll~l
maintain the EPLD's pin integrity after multiple device insertions. For
more information about these socket tests, call Altera Applications
Engineering at 1 (BOO) 800-EPLD.

I Page584

Altera Corporation

I

II Application Brief 46

Selecting Sockets for J-Lead Packages

I

Table 1. SummaI}' of 68-Pln Production Socket Analysis
Vendor and Part Number
Augat Inc.
PCS-068A-1
In/Cannon Corporation
LCS-68-2
3MfTextooi Corporation

2-0068-06234-070-038-0n
AMP,lnc.
821574-1

Comments
Least pin deformation. Contact force has a
downward component. No retainer clip option.
Low pin deformation. Contact force has a
downward component. Has a retainer clip option.
Moderate pin deformation. Contact force is lateral.
Has a retainer clip option.
Moderate pin deformation. Contact force has a
downward component. No retainer clip option.

Vendors may prOvide additional information about their products, such as
material selection, prevention of solder ingress during wave soldering, or
lead shape. Altera recommends qualifying sockets, just as with other
components, before committing to a particular vendor.
Table 2 shows the contact distance for Altera EPLDs. These measurements
should be used to select a socket (preferably with internal stand-offs) for
use with Altera EPLDs.
Table 2. EPLD Contact Distances
EPLD (1)
EPB2001J, EPM5192J
EPB2001 L, EPM5192L
EP181OJ, EP1830J, EPM5128J
EP1810L, EP1830L, EPM5128L
EP910J, EPM5064J
EP910L, EPM5064L
EP610J,EP630J,EP610AJ
EPM5032J, EPS448J
EP610L, EP630L,EP610AL
EPM5032L,EPB2002AL,EPS448L
EP330L, EPM5016L

Pin Count

Contact Distance (mils)
Minimum

Maximum

84
84
68
68
44
44
28

1180
1185

1200
1195

985

995

985
685

995
695

685

695

485

495

28

485

495

20

385

395

Note:
(1)

J =Ceramic J-Iead chip carrier (ILCC); L =Plastic J-lead chip carrier (PLCC).

iD
I

Altera Corporation

pages8s1

1 Selecting Sockets

Application Brief

for J-Lead Packages

Packaging
Options for
Wire-Wrap
Applications

461 :

Wire-:wrap applications require a through-hole mount compatible with
the J-lead package. The sockets specified do not typically mechanically
conform to most wire-wrap panels. Wire-wrap cards have machine
receptacles in rows with l00-mil spacing between receptacles and 300-mil
spacing between rows.
Carrier boards provide an effective way to bridge the gap. Mounting a
socket to a carrier board provides the convenience of wire wrap with only
a small real estate penalty. Some carrier boards have Signal routing with
shorter paths or 45-degree bends to minimize signal reflection.

Manufacturers

Table 3 lists corporate offices of several socket and adapter manufacturers.
Contact the appropriate vendor for additional information.
Table 3. Manufacturers
Company
AMP, Inc.

Product
Production Sockets

Augat, Inc.

Telephone Number
(800) 522-6752
(800) 999-9863

ITT/Cannon Corporation

(714) 757-8221

3MfTextool Corporation

(800) 225-5373

i

3MfTextooi Corporation

Test and Burn-In

(800) 225-5373

AMP, Inc.

Sockets

(800) 552-6752

Carrier Boards and

(408) 982-0660

Emulation Technology, Inc.
Emulation Technology. Inc.

I

(408) 982-0660
Wire Wrap Adapters

Information in this application briefis based on information provided to Altera by
various vendors, and is believed to be accurate. Altera assumes no liability for the
use of third-party products mentioned in this publication.

I Page586

Altera Corporation

III!

Sales Offices,
Distributors
& Representatives

I October 1990
Altera U.S.
Sales Offices

CALIFORNIA
(CORPORATE HEADQUARTERS)
Altera Corporation
2610 Orchard Parkway
San Jose, CA 95134-2020
TEL: (408) 984-2800
FAX: (408) 248-7097
SOUTHERN CALIFORNIA
Altera Corporation
17100 Gillette Avenue
Irvine, CA 92714
TEL: (714) 474-9616
FAX: (714) 474-7355
GEORGIA
Altera Corporation
1080 Holcomb Bridge Road
Bldg. 100, Suite 300
Roswell, GA 30076
TEL: (404) 594-7621
FAX: (404) 998-9830

MASSACHUSETTS
Altera Corporation
945 Concord Street
Framingham, MA 01701
TEL: (508) 626-0181
FAX: (508) 879-0698
NEW JERSEY
Altera Corporation
981 U.S. Highway 22
Suite 2000
Bridgewater, NJ 08807
TEL: (908) 526-9400
FAX: (908) 526-5471
TEXAS
ALTERA CORPORATION
Signature Place
14785 Preston Road
Suite 550
Dallas, TX 75240
TEL: (214) 233-1491
FAX: (214) 233-1493

ILLINOIS
Altera Corporation
200 W. Higgins Road
Suite 322
Schaumburg, Il 60195
TEL: (708) 310-8522
FAX: (708) 310-0909

Altera
International
Sales Offices

UNITED STATES
(CORPORATE HEADQUARTERS)
Altera Corporation
2610 Orchard Parkway
San Jose, CA 95134-2020
USA
TEL: (408) 984-2800
TLX: 888496
FAX: (408) 248-7097
BELGIUM
(EUROPEAN HEADQUARTERS)
Altera Europe
25, Avenue Beaulieu
1160 Bruxelles
Belgium
TEL: (32) 2-660.20.77
TlX: (886) 27087901(AWAlB)
FAX: (32) 2-660 52 25

I Altera Corporation

FRANCE
Altera France
72-78 Grande Rue
92310 savres
France
TEL: (33) 1.45.34.3787
FAX: (33) 1.45.34.0109
GERMANY
AlteraGmbH
Ismaninger StraBe 21
8000 MOnchen 80
West Germany
TEL: (49) 89/413.00.6-14
TLX: (841) 5213250
FAX: (49) 89/470.62.84

Page587!

ISales Offices, Distributors & Representatives
Altera
International
Sales Offices
(continued)

North American
Distributors

JAPAN
Altera Japan K.K.
Ichikawa Gakugeidai Building
2nd Floor
12-8 Takaban 3-chome
Meguro-ku, Tokyo 152
Japan
TEL: (03) 716-2241
FAX: (03) 716-7924

UNITED KINGDOM
Altera UK
21 Broadway
Maidenhead, Berkshire
England SL6 1JK
TEL: (44) 628-32516
TLX: (851) 94016389 (TIME G)
FAX: (44) 628-n0892

Alliance Electronics
Anthem
Future Electronics (Canada only)
Pioneer-Standard Electronics
Pioneer Technologies Group
Lex Electronics
Semad (Canada only)
Wyle Laboratories

u.S. Sales
Representatives

ALABAMA
Montgomery Marketing, Inc.
1910 Sparkman Drive
Huntsville, AL 35816
(205) 830-0498

CALIFORNIA (continued)
QuadRep Southern, Inc.
4 Jenner Street, Suite 120
Irvine, CA 92718
(714) 727-4222

ARIZONA
Tusar
6016 E. Larkspur
Scottsdale, AZ 85254
(602) 998-3688

QuadRep Southern, Inc.
7585 Ronson Road, Suite 100
San Diego, CA 92111
(619) 560-8330

ARKANSAS
Technical Marketing, Inc.
3320 Wiley Post Road
Carrollton, TX 75006
(214) 387-3601
CALIFORNIA
Exis, Inc.
11223 Welty Lane
Auburn, CA 95603
(916) 885-3062
Exis, Inc.
2860 Zanker Road, Suite 108
San Jose, CA 95134
(408) 433-3947

COLORADO
Lange Sales, Inc.
1500 W. canal Court, Bldg. A, Suite 100
littleton, CO 80120
(303) 795-3600
CONNECTICUT
Technology Sales, Inc.
237 Hall Avenue
Wallingford, CT 06492
(203) 269-8853
DELAWARE
BGR Associates
Evesham Commons
525 Route 73, Ste.100
Marlton, NJ 08053
(609) 983-1020

QuadRep Southern, Inc.
28720 Roadside Drive, Suite 227
Agoura, CA 91301
(818) 597-0222

I Page588

Altera Corporation

I

Sales Offices, Distributors & Representatives
DISTRICT OF COLUMBIA
Robert Electronic Sales
5525 Twin Knolls Road, Suite 325
Columbia, MD 21045
(301) 995-1900

LOUISIANA
Technical Marketlng,lnc.
2901 Wilcrest Drive, Suite 139
Houston,TX n042
(713) 783-4497

FLORIDA
EIR,lnc.
1057 MaItland Center Commons
MaItland, FL 32751
(407) 660-9600

MAINE
Technology Sales, Inc.
332 Second Avenue
Waltham, MA 02154
(617) 890-5700

GEORGIA
Montgomery Marketing, Inc.
3000 Northwoods Pkwy., Suite 110
Norcross, GA 30071
(404) 447-6124

MARYLAND
Robert Electronic Sales
5525 Twin Knolls Road, Suite 325
Columbia, MO 21045
(301) 995-1900

IDAHO
lange Sales, Inc.
5440 Franklin St., Suite 110
Boise, 10 83705
(208) 345-8207

MASSACHUSETlS
Technology Sales, Inc.
332 Second Avenue
Waltham, MA 02154
(617) 890-5700

Westerberg & Associates, Inc.
12505 NE Bel-Red Road, Suite 112
Bellevue, WA 98005
(206) 453-8881

MICHIGAN
Rathsburg Associates, Inc.
34605 Twelve Mile Road
Farmington Hills, MI 48331
(313) 489-1500

ILLINOIS
AEM,lnc.
11520 St. Charles Rock Road, Suite 131
Bridgeton, MO 63044
(314) 298-9900

I

MINNESOTA

cahill, Schmitz & cahill, Inc.
315 N. Pierce
St. Paul, MN 55104
(612) 646-7217

oasis Sales Corporation
1101 Tonne Road
Elk Grove Village, Il 60007
(708) 640-1850
INDIANA
Electro Reps, Inc.
7240 Shadeland Station, Suite 275
Indianapolis, IN 46256
(317) 842-7202
IOWA
AEM,lnc.

4001 Shady oak Drive
Marion,lA 52302
(319) 3n-1129
KANSAS
AEM,lnc.
8859 long Street
lenexa, KS 65215
(913) 888-0022
KENTUCKY
Electro Reps, Inc.
7240 Shadeland Station, Suite 275
Indianapolis, IN 46256
(317) 842-7202

IA/tera Corporation

MISSISSIPPI
Montgomery Marketing, Inc.
3000 Northwoods Parkway, Suite 110
Norcross, GA 30071
(404) 447-6124
MISSOURI
AEM,lnc.
11520 St. Charles Rock Road, Suite 131
Bridgeton, MO 63044
(314) 298-9900
MONTANA
Lange Sales, Inc.
1500 W. Canal Court, Bldg. A, Suite 100
littleton, CO 80120
(303) 795-3600
NEBRASKA
AEM, Inc.
4001 Shady oak Drive
Marlon, IA 52302
(319) 3n-1129
NEVADA
Exls, Inc.
2860 Zanker Road, Suite 108
San Jose, CA 95134
(408) 433-3947

III
Page 589

I Sales Offices, Distributors & Representatives

u.s. Sales
Representatives
(continued)

NEVADA (continued)
Tusar
6016 E. larkspur
Scottsdale, AZ 85254
(602) 998-3688

OHIO
The lyons Corporation
4812 Frederick Road, Suite 101
Dayton, OH 45414
(513) 278-0714

NEW HAMPSHIRE
Technology Sales, Inc.
332 Second Avenue
Waltham, MA 02154
(617) 890-5700

The lyons Corporation
4615 W Streetsboro Road
Richfield, OH 44286
(216) 659-9224

NEW JERSEY
BGR Associates
Evesham Commons
525 Route 73, Sulte100
Marlton, NJ 08053
(609) 983-1020
ERA,lnc.
354 Veterans Memorial Highway
Commack, NY 11725
(516) 543-0510
NEW MEXICO
Nelco Electronlx
3240 C Juan Tabo Blvd. NE
Albuquerque, NM 87111
(505) 293-1399
NEW YORK
ERA, Inc. (New York Metro)
354 Veterans Memorial Highway
Commack, NY 11725
(516) 543-0510
Technology Sales, Inc.
205 N. McKinley Avenue
Endicott, NY 13760
(607) 257-7070
Technology Sales, Inc.
470 Perinton Hills Office Park
Fairport, NY 14450
(716) 223-7500
Technology Sales, Inc.
145 Oakwood lane
Ithaca, NY 14850
(607) 273-1188
NORTH CAROLINA
Montgomery Marketing, Inc.
P.O. Box 520
Cary, NC 27512
(919) 467-6319
Montgomery Marketing, Inc.
1200 Trinity Road
Raleigh, NC 27607
(919) 851-0010
NORTH DAKOTA
cahill, Schmitz & cahill, Inc.
315 N. Pierce
St. Paul, MN 55104
(612) 646-7217

I Page590

The lyons Corporation
248 N. State Street
Westerville, OH 43081
(614) 895-1447
OKLAHOMA
Technical Marketing, Inc.
3320 Wiley Post Road
carrollton, TX 75006
(214) 387-3601
OREGON
Westerberg & AsSOciates, Inc.
7165 SW Fir Loop
Portland, OR 97223
(503) 620-1931
PENNSYLVANIA
BGR Associates
Evesham Commons
525 Route 73, Suite100
Marlton, NJ 08053
(609) 983-1020
The lyons Corporation
4812 Frederick Rd., Ste. 101
Dayton, OH 45414
(513) 278-0714
PUERTO RICO
Technology Sales, Inc.
Ediflcio Rail 219
San German, PR 00753
(809) 892-4745
RHODE ISLAND
Technology Sales, Inc.
332 Second Avenue
Waltham, MA 02154
(617) 890-5700
SOUTH CAROLINA
Montgomery Marketing, Inc.
1200 Trinity Road
Raleigh, NC 27607
(919) 851-0010
SOUTH DAKOTA
cahill, Schmitz & cahlll,lnc.
315 N. Pierce
St. Paul, MN 55104
(612) 646-7217

Altera Corporation

I

Sales Offices, Distributors & Representatives
TENNESSEE
Montgomery Marketing, Inc.
1910 Sparkman Drive
Huntsville, Al 35816
(205) 830-0498

VIRGINIA
Robert Electronic Sales
5525 Twin Knolls Road, Suite 325
Columbia, MD 21045
(301) 995-1900

TEXAS
Technical Marketing, Inc.
3320 Wiley Post Road
carrollton, TX 75006
(214) 387-3601

WASHINGTON
Westerberg & Assodates, Inc.
12505 NE Bel-Red Road, Suite 112
Bellevue, WA 98005
(206) 453-8881

Technical Marketing, Inc.
2901 Wllcrest Drive, Suite 139
Houston, TX n042
(713) 783-4497

WEST VIRGINIA
Robert Electronic Sales
5525 Twin Knolls Road, Suite 325
Columbia, MD 21045
(301) 995-1900

Technical Marketing, Inc.
1315 sam Bass Cirde, Suite B-3
Round Rock, TX 78681
(512) 244 2991
UTAH
lange Sales, Inc.
1864 S. State, Suite 295
Salt lake City, UT 84115
(801) 487-0843
VERMONT
Technology Sales, Inc.
332 Second Avenue
Waltham, MA 02154
(617) 890-5700

Canadian Sales
Representatives

,International
Distributors

IAltera Corporation

WISCONSIN
Cahill, Schmitz & Cahill, Inc.
315 N. Pierce
St. Paul, MN 55104
(612) 646-7217
oasis Sales Corporation
1305 N. Barker Road
Brookfield, WI 53005
(414) 782-6660
WYOMING
lange Sales, Inc.
1500 W. Canal Court, Bldg. A, Suite 100
littleton, CO 80120
(303) 795-3600

BRITISH COLUMBIA
Kaytronics
#102-4585 Canada Way
Burnaby, BC V5G 416
Canada
(604) 294-2000

ONTARIO (continued)
Kaytronics
300 March Road, Suite 603
Kanata, Ontario K2K 2E2
Canada
(613) 564-0080

ONTARIO
Kaytronics
331 Bowes Road, Unit 1
Concord, Ontario l4K 1J2
Canada
(416) 669-2262

QUEBEC
Kaytronics
5800 Thimens Boulevard
Ville St. laurent, Quebec H4S 1S5
Canada
(514) 745-5800

ARGENTINA
VEL S.R.l.
Virrey Cevallos 143
Piso 8, Of. 41
10n Buenos Aires
Argentina
TEL: (54) 1-40-102512525
(54) 1-45-714On163
(54) 1-46-2211
TLX: (390) 18605 (VEL AR)
FAX: (54) 1-45-2551

AUSTRALIA
Veltek
22 Harker Sf.
Burwood, Victoria 3125
Australia
TEL: (61) 3-808-7511
FAX: (61) 3-808-5473

ill
Page 591

Sales OffICflS, Distributors & Rept'lJsentlltiVfls

International
Distributors
(continued)

AUSTRIA

HONG KONO

Hltronlk
St.-Velt-Gasse 51
1130 Wlen
Austria
TEL: (43) 222-824-199
TLX: (847) 134404 (HIT)
FAX: (43) 222-828-557-285

RTI Industries
A19, 10IF, Profldent Ind. Centre
6 Wang Kwun Road
Kowloon
Hong Kong
TEL: (852) 3-7957421
FAX: (852) 3-7957839

BELGIUM

INDIA

D&D Electronics
Vile OIympiadefaan 93
2020 Antwerpen
Belgium
TEL: (32) 3-827-7934
TLX: (846) 73121 (DDELEC BU)
FAX: (32) 3-828-7254

BRAZIL

capricorn Systems International
No. 3306, First Floor
10th 'A' MaIn Road
33rd Cross, 4th Block
Jayanagar, Bangalore 560 011
India
TEL: (91) 812-640661
TLX: (953) 08458162 (SRIS IN)
FAX: (91) 812-643608

Unlao Digital COM E REP
Rua Texas No. 622-Brooklin
SAo Paulo SP CEP 04551
Brazil
TEL: (55) 11 533-0967
(55) 11 611-1256
TLX: (391) 11-37230 (BRVC)
FAX: (55) 11 533-6780

capricorn Systems International
1340 Tully Road, Suite 308
San Jose, CA 95122
USA
TEL: (408) 294-2833
TLX: 71499n29 (CAPCNUI)
FAX: (408) 294-0355

DENMARK

ISRAEL

E.V. Johanssen Elektronlk AlS
Tltangade 15
2200 Koebenhavn N
Denmark
TEL: (45) 31.83.90.22
TLX: (855) 16522 (EVICAS OK)
FAX: (45) 31.83.92.22

Vectronics ltd.

60 Medinat Hayehudim Street
P.O. Box 2024
Herzlia B 46120
Israel
TEL: (972) 52-556-070
TLX: (922) 342579 (VECO IL)
FAX: (972) 52-556-508

FINLAND

Ylelselektroniikka Of
P.O. Box 73
Luomannotko 6
02201 Espoo
Finland
TEL: (358) 0-452-1622
TLX: (857) 123212 (YLEOY SF)
FAX: (358) 0-452-3337

FRANCE
Tekelec Alrtronlc SA
Cite des Bruy~res
Rue Carle Vemet
92310 5evres
France
TEL: (33) 1.45.34.75.35
TLX: (842) 204552 (TKLEC A F)
FAX: (33) 1.45.07.21.91

GERMANY
Electronic 2000
Vertrlebs-AG
Stahlgruberring 12
8000 Manchen 82
West Germany
TEL: (49) 89142001-0
TLX: (841) 522561 (ELEC D)
FAX: (49) 89142001-209

Page 592

Active Technologies
147-16 181st Street
Jamaica, NY 11413
USA
TEL: (718) 244-0909
FAX: (718) 244-0912

ITALY
Inter-Rep S.pA.
Via Orbetello 98
10148 Torino
Italy
TEL: (39) 11129191
TLX: (843) 221422 (IR TO I)
FAX: (39) 11/2165915

JAPAN
Japan Macnlcs Corporation
Hakusan High-Tech Park
807 Hakusan-Cho, Midori-Ku
Yokohama 226
Japan
TEL: (81) 45-939-6140
FAX: (81) 45-939-6141

Altera Corporation

I

Sales Offices, Distributors & Representatives
JAPAN (continued)
Paltek Corporation
3-8-18 Yoga
Setagaya-Ku
Tokyo 158
Japan
TEL: (81) 3-707-5455
TLX: (781) 02425205 (PALTEK J)
FAX: (81) 3-707-5338
KOREA
MJL Korea, Ltd.
Samwhan Camus Bldg.
17-3 Youido-Dong
Yeungdeungpo-Ku
Seoul 150-010
Korea
TEL: (82) 2-784-8000
TLX: (787) 28907 (MJL)
FAX: (82) 2-784-4644
MJL Corporation - USA
622 Rosedale Road
Princeton, NJ 08540
USA
TEL: (609) 683-1700
TLX: 843457 (MJL MORV)
FAX: (609) 683-7447 ,
LATIN AMERICA
Intectra
2629 Terminal Boulevard
Mountain View, CA 94043
USA
TEL: (415) 967-8818
TLX: 345545 (INTECTRA MNTV)
FAX: (415) 967-8836
NETHERLANDS
Koning en Hartman
1 Energieweg
2627 AP Delft
Netherlands
TEL: (31) 15609906
TLX: 38250 (KOHA NL)
FAX: (31) 15619194
NORWAY
Eltron AlS
Aslakveien 20 F
0753 Oslo 7
Norway
TEL: (47) 2-500650
TLX: (856) 77144 (ELTRO N)
FAX: (47) 2-502777
SINGAPORE
Impact Sound PTE
65 Upper Paya Lebar Road 03-01
Guang Ming Ind. Bldg., 1953
Singapore
TEL: (65) 2914953, (65) 2817244
TLX: (786) 39142 (IMPACT RS)
FAX: (65) 2812786

I A/tera Corporation

SINGAPORE (continued)
auadRep Marketing (S) Pte Ltd
5611 North Bridge Road
#02-10 Eng Cheong Tower
Singapore 0719
TEL: (65) 2949998
FAX: (65) 2911213
SPAIN
Selco
Paseo de la Habana, 190
28036 Madrid
Spain
TEL: (34) 1-326-4213
TLX: (831) 45458 (EPAR E)
FAX: (34) 1-259-2284
SWEDEN
Nordisk Elektronik AB
Torshamnsgatan 39
7th Floor
16493 Kista
Sweden
TEL: (46) 8.703.46.30
FAX: (46) 8.703.98.45
SWITZERLAND
StolzAG
TafernstraBe 15
5405 Baden-Dattwil
Switzerland
TEL: (41) 56.84.90.00
TLX: (845) 825088 (SAG CH)
FAX: (41) 56.83.19.63
TAIWAN
Galaxy Far East Corp.
8F-6 390, Sec. 1
Fu Hsing S. Road
Taipei
Taiwan
TEL: (886) 2-7057266
TLX: (785) 26110 (GALAXYER)
FAX: (886) 2-7087901
UNITED KINGDOM
Ambar Cascom Ltd.
Rabans Close
Aylesbury, Bucks HP193RS
England
TEL: (44) 296 434141
TLX: (851) 837427 (AMBAR G)
FAX: (44) 296 29670
Thame Components Ltd.
Thame Park Road
Thame,Oxfordshire OX93UQ
England
TEL: (44) 844 261188
TLX: (851) 837917 (MEMECG)
FAX: (44) 844 261681

ill
Page 593

I

Notes:

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Altera Corporation
261 0 Orch~rd Parkway
San Jose, CA 95134·2020
(408)984·2800 Telex 888496
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