1990_Brooktree_Graphics_and_Image_Products_Application_Handbook 1990 Brooktree Graphics And Image Products Application Handbook

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Graphics and Imaging Products/Application Literature
Cross Reference List
Product Number

. Application Note Number

Btl0l ...................................................... 1,2,3,6, 10, II, 12
BtlOI/883 .................................................. 1,2,3,6, 10, 11, 12
Btl02 ...................................................... 1,2,3,6, 10, II, 12
Btl02/883 .................................................. 1,2,3,6, 10, 11, 12
Btl03 ...................................................... 1,2,3,6, 10, 11, 12
Btl06 ...................................................... 1,2,3,6, 10, 11, 12
Btl07 ........................................................ 1,2, 3, 10, 11, 12
Btl09 ........................................................ 1,2, 3, 10, 11, 12
Bt208 ............................................................... 3, 10, 13
Bt251 ..................... .. ........................................ 3, 10, 14
Bt253 ............................................................... 3, 10, 15
Bt281 .................................................................... 19
Bt424 ................... . . . . ........................................ 4, 11, 12
Bt431 ............................................................... 4, 11, 12
Bt438 .................................................................. 11, 12
Bt438/883 .............................................................. II, 12
Bt439 ................................................................. II, 12
Bt450 .................................................. 1,2,3,4,6,7, 10, II, 12
Bt451/1/8 .......................................... 1,2,3,4,6,7,8,10, 11, 12, 16
Bt453 .................................................. 1,2,3,4,6,7, 10, II, 12
Bt453/883 ............................................... 1,2,3,4,6,7, 10, 11, 12
Bt454 ................................... . .............. 1,2,3,4,6,7, 10, II, 12
Bt458/883 ............................................ I, 2, 3, 4, 6, 7, 10, 11, 12, 16
Bt459 ............................................. 1,2,3,4,6,7,8, 10, 11, 12, 18
Bt460 ............................................... I, 2, 3, 4, 6, 7, 10, 11, 12, 18
Bt461/462 .............................................. 1,2,3,4,6,7, 10, 11, 12
Bt468 .................................................. 1,2,3,4,6,7, 10, II, 12
Bt471/6/8 ........... .... ........................... 1,2,3,4,5,6,7,9, 10, II, 12
Bt473 ................................................ 1,2,3,4,5,6,7, 10, II, 12
Bt474 ................................. .. ............. 1,2, 3, 4, 5, 6, 7, 10, 11, 12
Bt475/477 ........................................... 1,2,3,4,5,6,7,9, 10, 11, 12
Bt479 .............................................. 1,2,3,4; 5, 6, 7, 9, 10, 11, 12
Bt492 .................. . ................................... 1,2,3,4, 10, 11, 12
Bt604 ................................................................. 11, 17

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580· (800) VIDEO IC
TLX: 383596· FAX: (619) 452-1249

GRAPHICS
AND

IMAGING

APPLICATIONS

PRODUCTS
HANDBOOK

1 990

Introduction
Application Notes
Article Reprints
Industry Standards
Sales Offices

•
•
•
•

GRAPHICS
AND

IMAGING

PRODUCTS

APPLICATIONS

HANDBOOK

1 990

Thank you for your interest in Brooktree products.
commitment is to provide a steady stream of
innovative products that offer the highest quality,
lowest cost/performance solutions and back them
with comprehensive support services. These
include timely and accurate technical information
and
responsive,
experienced
applications
assistance.
OUf

At Brooktree, listening to customer's requirements
is what we do first. Solving customer's problems
is what we do best.

iii

Brooktree reserves the right to make changes to its products or specifications to improve performance, reliability, or
manufacturability. Information furnished by Brooktree Corporation is believed to be accurate and reliable. However, no
responsibility is assumed by Brooktree Corporation for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by its implication or otherwise under any patent or
patent rights of Brooktree Corporation.
Copyright © 1990 Brooktree Corporation (all rights reserved)
This handbook was published using ReadySetGo!, AutoCAD, Cricket Draw, and Cricket Graph on a Macintosh
computer and LaserWriter II. ReadySetGo! is a trademark of Manhattan Graphics, Inc .. LaserWriter is a trademark of
Apple Computer, Inc. Cricket Draw and Cricket Graph are trademarks of Cricket Software, Inc. AutoCAD is a
registered trademark of Autodesk, Inc.
VIDEODAC, RAMDAC, WindowVu, and VideoNet are trademarks of Brooktree Corporation. Brooktree is a
registered trademark of Brooktree Corporation. Personal System!2 and PS/2 are registered trademarks of ffiM.
Macintosh is a licensed trademark of Apple Computer, Inc. IMS is a registered trademark of Inrnos Limited.

GRAPHICS
AND

IMAGING

PRODUCTS

APPLICATIONS

HANDBOOK

1 990

Introduction
Application Notes
Article Reprints
Industry Standards
Sales Offices

1- 1

Introduction

1-2

INTRODUCTION

Brooktree's Application Engineering Department is a
responsive tearn that provides a diverse range of technical
product support services. Our customers benefit from
these services throughout their product's life cycle; initial
design evaluation. prototype development, qualification
and production.
We recognize the importance of customers having access
to technical product information during a critical design
phase to assure time-to-market design success. Several
factory-direct access channels. such as the fax. telex and
the toll-free telephone numbers, are printed on the front
page of all technical product literature. The Technical
Hotline (800 VIDEO IC) provides immediate access to
technical personnel regarding a product question or
literature inquiry. Other services include on-site design
support or factory analysis of any issues you may have.
This Applications Handbook contains information to
support you throughout your design effort. This
information is compiled in sections which include
application notes. article reprints and a summary of
relevant industry standards.

Application Notes
Application notes provide transfer of technical
information which is critical for correct operation or use
of a product The information may cover several levels of
a product application, ranging from specific device use to
system use techniques. Application notes are written to
respond to product applications. provide solutions to
recurring field difficulties. or clarify correct design
techniques. New application notes are continually
produced to meet new product applications.
Other Brooktree publications. such as the product
databook and datasheets. contain application sections
reflecting the latest information specific to a particular
product.

1-3

Industry Standards
Industry trends will continue to push VLSI technology to
incorporate more functionality into a system. This growth
will evolve into VLSI subsystems that meet established
protocol standards. Brooktree recognizes the importance
of standards that support open architecture. Protocol
standards provide a vital link between the software and
hardware. reducing development time and system cost.
The Industry Standards section contains several standards
relevant to the transmission. manipUlation and display of
images.
The Electronic Industry Association (EIA)
publishes bulletins. recommendations. and standards
applicable to broadcast television and display systems.
The electrical specifications for display standards such as
RS330. RS343A. RS170. and RS170A are reproduced in
this section.
The International Telecommunications Union (ITU) is the
governing body of several committees, including the
Consultative Committee of International Radio (CCIR).
The recommendation CCIR 601-1 dermes the digital
encoding standards for television signals while report
CCIR 624-1 lists the electrical specifications for universal
worldwide broadcast television signals.
A reference address list of other standard publishing
organizations and agencies is furnished at the end of the
this section. The standards in this section have been
reproduced with written permission from the authoritative
governing body.

1-4

GRAPHICS
AND

IMAGING

PRODUCTS

APPLICATIONS

HANDBOOK

1 990

Introduction
Application Notes
Article Reprints
Industry Standards
Sales Offices

2-1

•

Application Notes

2-2

TAB L E

CON TEN T S

AN· 1

Getting the Best Perfonnance From Video Digital-to-Analog Converters ....... 2 - 5

AN·2

VIDEODAC Essentials ........................................ 2 - 9

AN·3

Comparison of RS-343A. RS-170, and PAL Video Levels ................ 2-15

AN·4

Using the Overlay Palettes on Brooktree RAMDACs .................... 2 - 19

AN·5

Expanding VGA Graphics With the
Bt471/475/476/477/478 Family .................................. 2 - 21

AN·6

Troubleshooting Your Brooktree CMOS VIDEODAC or RAMDAC . . . . . . . . . . 2 - 29

AN·7

RAMDAC Initialization ....................................... 2 - 33

AN·8

Building a4K Lookup Table with the Bt457 .......................... 2 - 37

AN·9

Bt471/475/476/477/478 Power Saving Features ....................... 2 - 39

AN-IO

Support Components ......................................... 2 - 43

AN·11

Mixed Signal Layout Considerations ............................... 2 - 49

AN ·12

Analog Signal Interface Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 57

AN ·13

Bt208 Evaluation Module Operation and Measurements . . . . . . . . . . . . .. .... 2 - 65

AN ·14 Bt251 Evaluation Module Operation and Measurements . . . . . . . . . . . . . . . . .. 2 - 75
AN·I5

Bt253 Evaluation Module Operation and Measurements. . . . . . . . . . . . . . . . .. 2 - 85

AN·I6

Bt451/457/458 Evaluation Module
Operation and Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2 - 97

AN ·17

Bt604/605/606 Evaluation Module Operation and Measurements . . . . . . . . . . .. 2 - 109

AN ·18 Pixel Interleaving Benefits of the Bt459 ..................... "...... 2 - 121
AN·I9

Bt281 Real-Time Color Space Converter and Corrector .................. 2 - 127

2-3

•

Application Notes

2-4

APPLICATION

NOT E

Getting the Best Performance from
Video Digital-to-Analog Converters
When using high speed analog and digital logic,
proper component selection, hardware, and printed
circuit board layout become paramount in obtaining
stable and noise-free performance.

The digital and analog ground plane areas should be
connected at the lowest impedance source.

Power Planes

Because VIDEODACs and RAMDACs contain part
digital and part analog circuitry, the analog output
signal is subject to degradation from power supply
noise, ground loops, radiated pickup and magnetic
coupling. The mixture of digital and analog circuitry
often requires unique solutions due to the harmonic
content of the waveforms. This application note will
provide guidelines for both the design engineer and
the printed circuit board designer to obtain the best
performance from a VIDEODAC or RAMDAC.

It is good design practice for dense PCB layout with
high speed logic to include a power plane layer to
minimize voltage drops, aid power supply decoupling
and improve noise margins.
For best DAC performance, the power plane should be
separated into two areas, designated as analog and
digital power, which lay on top of the analog and
digital ground planes, respectively. The digital power
plane will supply power to all digital logic on the
board and the analog power plane will supply all
power pins of the DAC, together with power for any
reference circuitry.

For additional and more detailed product-specific
layout considerations, refer to the individual product
datasheets.

It is important that portions of the digital power
plane area do not overlay portions of the analog
ground plane area and that portions of the analog
power plane area do not overlap portions of the
digital ground plane.
This will prevent PCB
plane-to-plane noise coupling. Finally the analog
and digital power plane areas should be tied together
at a single point with a wire through a ferrite bead
(such as Fair-Rite part no. 2743001111).

Ground Planes
In designing a board with high speed TTL logic, one
should always use a ground plane under digital signal
traces to minimize radiated noise and crosstalk.
Best performance from VIDEODACs is obtained by
separating this ground plane into two separate areas
(designated as digital ground and analog ground), with
at least a 1/8" gap between the areas. The digital
ground plane should encompass the area under all the
digital logic including signal traces leading up to the
DAC but excluding any ground pins on the DAC. The
analog ground plane area should include all ground
pins on the DAC, all reference circuitry (external
reference if used, current setting resistors, etc.), the
output traces and output connector(s).

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580 • (800) VIDEO IC
TLX: 383596' FAX: (619) 452-1249

Power and ground return connections from the board
to an external power supply should be made to the
digital power and ground areas to minimize the DC
current flowing through the ferrite beads connecting
the analog and digital areas together.

2-5

•

Broddree®

AN-l

To minimize data undershoot, ringing, and resultant
data feedthrough noise, interconnect distances should
be kept as short as possible to the DAC inputs (less
than 3 inches). Data feedthrough noise is also
proportional to edge speed, so in lower speed
applications, use of lower speed logic will reduce data
related noise on the DAC output. Also, one should
avoid running long clock lines to the DAC since this
is another source of noise pickup.

Supply Decoupling
Printed Circuit Boards
A four layer sandwich structure, with power and ground
planes inside the board and signals on the top and
bottom of the board, provides good high frequency
decoupling by virtue of the distributed capacitance
between the power and ground planes.

Finally, in some applications, use of parallel
termination resistors at the DAC inputs can reduce
digital noise. The terminating resistors, if used,
should be the low inductance film type and should be
connected to the digital ground and power planes.

The addition of 0.1 IlF ceramic capacitors at a density
of one cap per one or two square inches is usually
enough for lower frequency decoupling. For best DAC
performance, a 0.1 IlF ceramic capacitor should be
placed as close to each DAC power pin as possible for
bypassing the analog power and ground plane areas.
For operation beyond 75 MHz, a 0.1 IlF ceramic
capacitor paralleled with a 0.001 IlF chip capacitor is
recommended.

Analog Inputs
The DAC should be located as close as possible to its
output connector(s) to minimize noise pickup on the
analog output traces. It is usually more difficult to
control the characteristic impedance on boards,
though minimizing the output line length will
minimize reflections due to impedance mismatch.
DAC reference circuitry should be kept close to the
DAC to avoid stray pickup. DAC output signals
should overlay the analog ground plane and not the
analog power plane to maximize high frequency
power supply rejection.

If the display has "ghosting" problems, additional

capacitance in parallel with the power supply and
CaMP capacitors may fix the problem.

Breadboards
In breadboards with a ground plane and point to point
wiring for power, best DAC performance is achieved
with chip capacitors in the 0.01 IlF to 0.1 IlF range
connected between the power pins and ground (see
discussion about sockets on next page). Also, in
breadboards with point to point power wiring, a
ferrite choke such as Ferroxcube part no.
VK20019/4B should be placed between the DAC
power pins and the power source for the digital logic.
Breadboards with a prefabricated ground plane should
have this plane cut into analog and digital areas as
indicated in the earlier discussion on ground planes.

It is important to note that while DACs contain
circuitry to reject power supply noise, this rejection
decreases with increasing frequency. As an example,
with a 0.01 IlF compensation capacitor, the power
supply rejection on CMOS DACs flattens out to 20 dB
at frequencies around 1 KHz. This means that if the
user powers the DAC from a 20 KHz switching power
supply with 100 mV of noise at 20 KHz and
harmonics, about 10 mV of this supply noise will be
on the DAC output. If the designer does not use linear
supplies, close attention should be paid to reducing
supply noise and one should consider using a three
terminal regulator for DAC power.

Signal Interconnect
Digital Inputs
The digital input signals to the DAC should be
isolated from the analog output(s) analog reference
inputs to the DAC. Also, the digital input signals
should run over the digital ground and power plane
areas of the board (see earlier discussion on power and
ground planes).

2-6

AN-!

Bypass Capacitors

Avoiding Latch-Up

Probably the single most important external
components which affect the noise performance of a
DAC, are the capacitors used to bypass the power
supplies.

Latch-up is a common concern with CMOS devices
where power supply differentials or sequences can
induce the CMOS device to draw excessive current.
Observe the following precautions to avoid latch-up
in CMOS devices:

It is important to realize that the high frequencies
generated by the logic will not be filtered by most
capacitors. At these frequencies, most capacitors
look like inductors. For example, a 0.1 J.1F capacitor
with 1/4 inch of lead length will self resonate at
around 10 MHz, beyond this frequency it will look
inductive. Therefore, the criterion for measuring the
effectiveness of a given bypass capacitor is to note
its lead inductance. In addition, bypass capacitors
should be installed in printed circuit boards with the
shortest leads possible, consistent with reliable
operation.

1. Tie all VAA pins together at the package pins.
2. Hold all logic inputs low until power to the device
has settled to the specified tolerance. Avoid DAC
power decoupling networks with large time constants
which could delay VAA power to the device.
Latch-up can be prevented by assuring all VAA pins
are at the same potential, and that the VAA supply
voltage is applied before the signal pin voltages. The
correct power-up sequence assures that any signal pin
voltage will never exceed the power supply voltage
by more than +O.5v.

Probably the most effective capacitor is the
distributed capacitance between power and ground
planes. However, this capacitance is usually too
small to sustain large current surges without excessive
voltage change. Ceramic chip capacitors are the next
most effective for bypassing applications and are
highly recommended. The drawback to using chip
capacitors in PCB applications is their tendency to
crack during high shock or wide temperature ranges.

ESD Considerations
Correct ESD sensitive handling procedures are required
to prevent device damage which can produce
symptoms of catastrophic failure or erratic device
behavior with somewhat "leaky" inputs.

Attenuation Beads

The third most effective capacitor type is the radial
lead ceramic capacitor.
Distributed capacitor
inductance must be balanced by a large-value tantalum
or electrolytic capacitor.

Ferrite beads are recommended to suppress
interference due to the fast switching times of the
DACs and decoupling noise on the power plane from
getting to the DAC output. Some recommended
attenuation beads are Ferroxcube part no.
VK200l9-4B, Fair-Rite part no. 2743001111, and
Philips part no. 431202036690. Figures 1 and 2 are
the impedance and typical damping curves for several
Ferroxcube brand wide band chokes.

In summary, there is no one right answer to
bypassing which will suit all applications. However,
the principle to keep in mind is that bypassing
capacitors in conjunction with the distributed power
supply plane inductance will determine the
effectiveness of the decoupling.

Analog Output Protection
CMOS VIDEODACs and RAMDACs have no intrinsic
protection on the analog outputs against high energy
discharges, such as those from monitor arc-over or
from "hot-switching" AC-coupled monitors.
The diode protection circuit shown in Figure 3 can
prevent latch-up under severe discharge conditions
without adversely degrading analog transition times.
The IN4148/9 are low capacitance, fast switching
diodes, which are also available in multiple-device
packages
(FSA250X or FSA270X) or
surface-mountable pairs (BAV99 or MMBD7001).

2-7

•

AN-l

~\t! _J~
1000

m/~

Zln)

VK 20010138

500

VI< 20019148

200
40

120

I I

100

160

200

240

FREOUENCY (MHz)

Figure 1. Impedance Curves of
Wide-Band Chokes.

Bn.,
, I~V"

V
/

-0

i"o. ['0...

c
/. '/. /.
./

I--

itT

~---'"

A: c= 1500pI(VK2001914B)
So c = 1500 pf (1!1( 200201~)

I-- c, C= 550 pi (1!1( 200201";'
I-- 0: c= 55Opt(VK20019!4B)
I-40

120

'~t

160

200

240

FREOUENCY IMHz)

Figure 2. Typical Damping curves for
VK Chokes with Additional Parallel
Ceramic Capacitors.

VAA

IN4148/9
VIDEO
OlITPUT --~t---- TO MONITOR
FROMDAC
IN4I48/9
AGNDOR
GND

Figure 3.

Output Protection Circuit.

2-8

APPLICATION

NOT E

VIDEODAC Essentials
A raster based graphics display terminal is comprised
of a graphics controller, a frame buffer to hold the
refresh data, optional color look-up tables,
VIDEODACs, and a CRT monitor. The VIDEODAC
subsystem has special requirements and performance
parameters that will define the overall quality of the
graphics presentation.

one VIDEODAC. The interface to the computer
system is the graphics display controller. The
graphics controller generates all the timing and
interface signals to the video RAM, the color lookup
tables, the VIDEODACs and the deflection circuitry
for the CRT.
The new generation of monolithic integrated circuits
includes the color lookup RAM and the DAC, either as
a single group or as a triple RAM and DAC
combination (RAMDAC).

A simplified block diagram of a color graphics
terminal using a color lookup table and three
VIDEODACs is shown in Figure 1. A monochrome or
black and white monitor will use one lookup table and

FRAME BUFFER MEMORY
CONTROL

ADDRESSIDATA

'lYPICAL

SERWlZED

GRAPlflCS

VIDEO DATA

CON'IROu.ER
CHIP

2561t8

RAM

RO-R7

256X8

80-87

RAM
256X8

RAM

lOR

RED

100

GREEN

lOB

BWE

00-07

BtlOI
VIDEODAC

CURSOR

REFWlIITB
SYNC·
BLANK·

SYNC-

BLANK'
a.ocK

GROUND

;~
R2

FSADJUST , . - - - - J

lOR
lOG
(SYNC

VIDEO
CONNECTOR

lOB

Figure 3.

Typical Connection Circuit.

Glitch Impulse
Glitch impulse is a term used to define the area under
the voltage·time curve of a single DAC step until the
level has settled out to within the specified error band
of the fmal value (the linearity error). Glitch impulse
is important where subtle level changes can produce
significant transients, and is different from settling
impulse which involves large amplitode changes.

Depending on the type of internal logic design in the
DAC. the glitch energy can be very low « 50 pV-sec)
for a segmented architecture to as much as 250 pV-sec
for a R-2R network. For many DACs. maximum
glitch energy will occur when a transition is made
between segments (which have the worst switching
skew), where the count goes from 0111 1111 to 1000
0000. This is where all the internal registers will
change and the current sources are tuming on and off.
Low glitch energy is necessary to avoid pixel color
change or blurred pixels across lite CRT. Figure 4
shows a typical DAC output glitch.

r--- ItA111ID IIRRC)R BAND

Figure 4.

DAC Output Glitch.

2 -12

AN-2

In a video system, if the glitch energy is sufficiently
low and consistent across all codes, it will be
integrated over a period of time and will have no effect
on the CRT screen. Other glitches generated by the
DAC such as data feedthrough and DAC-to-DAC noise,
may have a cumulative affect since the wavefonns may
not be repetitive. Therefore, good design practices in
PC board design include power supply decoupling, and
avoidance of running digital signal lines near the
DAC analog circuitry and output to the monitor. A
suggested component placement is shown in Figure

5.
DAC-to-DAC skews greater than 1/4 pixel interval
can result in perceiVed color shift and resolution loss.

Figure 5.

Rise/Fall Times
How fast a DAC output can switch from one voltage
step to the next voltage step is measured from the
10% to 90% transition of the output waveform. In
video applications, the faster the DAC the smaller
this number will be. For a 30 MHz DAC, 3 to 10 ns
would be typical, while for a 125 MHz DAC, 1 to 3 ns
would be common. For very high speed DACs in the
250 MHz or greater speed range, rise and fall times
under 1 ns are necessary. The output voltage slew rate
is also a function of the load capacitance/termination
and the addition of small values of capacitance can
some times be used to reduce overshoot and ringing
when very fast DACs are used. DAC rise/fall times are
at least twice as fast as the monitor they drive to avoid
degradation of the convolved transition time.

50%

Typical Evaluation Module.

Settling Time
Settling time is a measurement of how fast a DAC
output voltage from the mid-transition, settles to the
desired value within an error band (e), typically ± 1/2

LSB.
In video applications, settling time is of moderate
importance, since the CRT phosphors are being
excited and the eye will not respond to the very small
differences in light intensity of the pixel on the
screen. Settling times greater than a pixel interval
result in loss of color rendition or palette resolution.

Settling time is an important parameter if the DAC is
being used in an instrumentation environment where
it is necessary to have very accurate voltages as the
input code is changed. Figure 6 describes both
rise/fall time and settling measurements.

-------1
RATEDSETIUNG
BAND

10% - - - - - - - /
RISE/FAU.

TIME

Figure 6.

Rise/Fall Time and Settling Measurements.

2 -13

•

Broddree~

AN-2
D1

-VEE

Figure 7.

Typical R·2R DAC Network (4·Bit DAC).

DAC Internal Architecture

Figure 7 illustrates a typical R-2R DAC network. An
improved type of circuit architecture, called a segmented
DAC, offers low glitch energy and no trimming of resistors
to obtain the needed accuracy. The segmented DAC utilizes
the fact that monolithic transistors and resistors of the
same geometry can match closely to each other and that
cumulative geometry errors can be effectively averaged over
the monolithic device area.

To generate the individual current steps, the simplest
form of a DAC will use an R-2R summing resistor
network. For an 8-bit DAC, eight current sources are
used in a binary fashion to generate 256 output steps.
While a minimal number of components are used, the
weaknesses of this design are: 1) the resistor ladder
tolerances are critical, 2) the individual current steps
range from large to small values, and 3) the
temperature tracking of resistor pairs. Due to device
tolerances, in order to obtain less than ± 1 LSB
integral linearity error and ± 1 LSB of differential
linearity error, it is necessary to match the resistors
by laser trimming resistor links.

Some segmented DACs may use 256 individual current
source transistors or a combination of segmentation for the
higher order bits and an R-2R network for the lower order
bits where speed, tolerance and area determines the
partition. Figure 8 shows a fully segmented DAC circuit
topology.

SEGMENT DECODER

~~r---~::~::::;:::++::::;:::~::~~

Figure 8.

Segmented DAC Topology (2.Bit DAC).

2 -14

lOurlOur

APPLICATION

NOT E

Comparison of NTSC, PAL
and SECAM Video Formats
waveform (blanked video signal) and is defined as
having 100 IRE units. The black to blank level
(typically referred to as the setup) is used to shut off
the beam during the retrace time and varies between
the formats. The total amplitude is about 140 IRE
units (143 IRE units for PAL and SECAM) from sync
tips to reference white for monochrome, with a
saturated subcarrier.

There are several international standards for
specifying the amplitude and video components of a
waveform for use with television and video monitors
which use a subcarrier for color or chrominance
information.
In North America and Japan, the NTSC format is the
standard, while PAL and SECAM video formats are
used in Europe. A comparison of the various video
levels is shown in Table 1 for reference, and Figure 1
is a drawing of a composite video waveform. The
newer international standards specify a voltage
amplitude of 0.714 volts between the blanking level
and the white level for the video portion of the

An older standard known as RS170A is also used in
the United States and differs from RS343A level for
the voltage level from blank to white. The RS 170A
blanked video level is 1.00 volts as compared to the
RS343A, PAL, and SECAM levels of 0.714 volts.

WHITB LEVEL

BLACK LEVEL

BLANK LEVEL

-L________________

Figure 1.

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580 • (800) VIDEO IC
TLX: 383 596· FAX: (619) 452-1249

_______________________ SYNC LEVEL

Composite Video Waveform.

2 - 15

•

AN-3

Rather, three separate signals (red, green, and blue)
are generated, each containing intensity and blanking
information. Typically, only the green channel
contains sync information.

The monochrome version of the RS170A standard
(RS 170) does not have a subcarrier for color or
chrominance information.
The sync levels (40 IRE units for NTSC and 43 IRE
units for PAL and SEC AM) are sufficiently close
enough in tolerance that the 40 IRE levels of
Brooktree's VIDEODACs and RAMDACs will meet the
PAL and SECAM tolerance.

To assist users who need to determine the output
current when terminated into 75-ohm and 37.5-ohm
(doubly-terminated 75-ohm) loads. a comparison
chart is shown in Table 1. Brooktree DACs are
specified to drive doubly-terminated 75-ohm loads.
while many competitor DACs can only drive a
singly-terminated 75-ohm load and develop the
proper video output voltage level.

The RS343A standard is commonly used for computer
graphics, and of the four standards previously
mentioned, it and RS 170 are the only ones that do not
use a subcarrier for color or chrominance information.

NTSC
RS-343A*

NTSC
RS-170*

NTSC
RS-170A**

PAL**

SECAM**

Video Output
Levels

IRE Units

Blank to White
Blank to Black
Blank Level
Blank to Sync

100 IRE
7.5±5IRE

Blank to White
Blank to Black
Blank Level
Blank to Sync

100 IRE
7.5 ± 2.5 IRE

Blank to White
Blank to Black
Blank Level
Blank to Sync

100 IRE
7.5 ±2.5 IRE

Blank to White
Blank to Black
Blank Level
Blank to Sync

100 IRE
oIRE

Blank to White
Blank to Black
Blank Level
Blank to Sync

(75-ohm load)

rnA (typ.)
(37.5-ohm load)

0.714 ± 0.1
typo 0.054
0
- 0.286 ± 0.05

9.52
0.714
0
- 3.81

19.04
1.43
0
- 7.62

1.0 ± 0.05
typo 0.075
0
typo - 0.4

13.33
1
0
- 5.33

26.67
2
0
- 10.67

1.0 ± 0.05
typo 0.075
0
typo - 0.4

13.33
1
0
- 5.33

26.67
2
0
- 10.67

typo 0.714
Ov
Ov
typo - 0.307

9.52
0
0
- 4.09

19.04
0
0
- 8.19

typo 0.714
o to 0.049
0
typo - 0.307

9.52
0
0
- 4.09

19.04
0
0
- 8.19

Volts

typo 40 IRE

40±5IRE

typo 43 IRE
100 IRE
Ot07IRE
typo 43 IRE

*no color or chrominance subcarrier -- requires three channels for ROB.
**uses color or chrominance subcarrier -- Btl02 is suggested VIDEODAC.

Table 1.

Comparison Of Video Formats.

2 - 16

rnA (typ.)

AN-3

Other items of interest when comparing the various video formats are the number of lines per frame. field frequency.
and normal video bandwidth:

RS170A

PAL

SECAM

525

625

Field frequency

Luminance Bandwidth (MHz)

4.2

Chrominance Subcarrier (MHz)

3.58

4.43

4.3 to 4.4

Chrominance Bandwidth (MHz)

0.5 to 1.5

1.3

Number of lines per frame

Table 2.

Comparison of Video Formats.

This can be improved by asserting sync information
through an external current sink rather than through
the DAC data bits. Figure 2 shows a circuit using a
transistor array (3227) biased off a negative supply
voltage. The delay through the external sync switch
should roughly match that through the DAC including
any pipeline delays. Fast CMOS switches (4316
type) can perform the same function using resistor
summing (rather than current summing). with some
attendant degradation in output impedance match or
return loss (3% or 30 dB is common for industrial
grade. while 10% or 20 dB suffices for consumer
applications ).

Since chrominance subcarrier formats generate output
levels between blank and sync levels (to generate
color burst information during the back porch time).
the sync and blank control inputs to most DACs
cannot be used in such applications. The 20 IRE gap
between sync and the most negative color burst level
represents a 15% loss in gray scale range just to
encode the sync.

DAC

SYNC"
(TIL)

MBOOI

Figure 2.

External Sync Circuit for NTSC RS170A, PAL, and SECAM.

2 - 17

•

AN-3
Component Analog Video Formats
In recent yean, the trend has been toward component
analog video (CAV) formats, much like the RGB
format of most computer graphics systems.

The BetaCam and MIl are the popular Sony and
Matsushita formats respectively, each of which come
in 3 or 2 wire versions and involve the Component
Time Division Multiplexed (CTDM or CTCM)
nomenclature in the latter case.

The major video equipment CA V formats currently in
use are summarized in Table 3 at a standard color
saturation level of 75%, which is the common "legal"
limit to the chrominance subcarrier's amplitude range
in the NTSC format.

The Society for Motion Picture and Television
Engineers (SMPTE) and the European Broadcasting
Union (EBU) have adopted their own color difference
formats in order to remove brand name association.
Most CA V formats sample the color difference
components at half the rate or bandwidth of the
luminance signal (the common 4:2:2 hierarchy, not
to be confused with the RS-422 interface). Most CAY
formats have no use for the 7.5 IRE setup used in
NTSC, which represents a 7.5% loss in dynamic
range. Hence, the newer CAV standards (GRB and
SMPTE/EBU) call for no setup pedestal.

GRB is the matrix decoded version of NTSC with sync
added to all three channels, which may be extended to
700 m V gray scale at 100% saturation with a PLUGE
offset for monitor black/white adjust. Reversal of the
non-complex RGB to GRB format is consistent with
the green signal corresponding to the Y or luminance
signal in the other color difference (B - Y and R - Y)
formats.

Format

Video Output
Function

Signal Amplitude
(Volts)

Comments

GRB

G,R,B
Sync

+ 0.700

at 100% saturation, 0% setup
three wire = (G + sync), (R + sync), (B + sync)

Y
Sync
R-Y,B-Y

+ 0.714

BetaCam*

MIlt

SMPfE

- 0.300

at 75% saturation, 7.5% setup on Y only
three wire =(Y + sync), (R - Y), (B - Y)

- 0.286
± 0.350

Y
Sync
CTDMR-Y
CTDMB-Y
Sync

+ 0.714

at 100% saturation, 7.5% setup On Y only
two wire =(Y + sync),
CTDM [ (R - Y), (B - Y + sync) 1

- 0.286
± 0.350
± 0.350
- 0.630

+ 0.700

Y
Sync
R-Y
B-Y

at 100% saturation, 7.5% setup On Y only
three wire =(Y + sync), (R - Y), (B - Y)

- 0.300
± 0.324
± 0.324

Y
Sync
CTCMR- Y
CTCMB-Y
Sync

+ 0.700

at 75% saturation, 7.5% setup on Y only
two wire = (Y + sync),
CTCM [ (R - y), (B - Y + sync) 1

- 0.300
± 0.350
± 0.250
- 0.650

+ 0.700

Y
Sync
PB
PR

at 100% saturation, 0% setup
three wire = (Y + sync), PB, PR

- 0.300
± 0.350
± 0.350

*Trademark of Sony Corporation.
tTrademark of Matsushita Corporation.

Table 3.

Popular Component Analog Video Output Formats.

2 - 18

APPLICATION

NOT E

Using the Overlay Palettes
on Brooktree RAMDACs
What are Overlay Palettes?

Generating Overlay Information

Brooktree RAMDACs usually include an overlay
palette, consisting of one or more registers, in
addition to the normal color palette RAM. For triple
RAMDACs, each overlay register contains 12 or 24
bits of color information (for triple 4-bit or triple
8-bit D/A converters, respectively). For single
RAMDACs, each overlay register contains 8 bits of
color information (assuming an 8-bit D/A converter).

Overlay information may be generated by using
additional bit planes in the frame buffer, which are
interfaced directly to the overlay inputs of the
RAMDAC. Thus, the designer is able to keep the
graphics data and overlay data in separate memory,
simplifying software and increasing graphics
performance.

If a VLSI graphics processor is used. the cursor output
may be connected to the one of the overlay inputs of
the RAMDAC.
Thus, whenever the graphics
controller outputs cursor information, the appropriate
overlay register is automatically selected. Additional
bit planes or external hardware may still be used for
menus, grids, alphanumeric overlays, etc., by using
any other overlay inputs of the RAMDAC.

To support the overlay palette, besides the normal
pixel input ports, the RAMDACs have palette
selection inputs, OLx. These inputs specify, on a
pixel basis, whether color information is to be
provided by the color palette RAM or one of the
overlay registers.

Why are Overlays Useful?
Some high performance graphics systems implement
hardware cursors using discrete or VLSI logic. Again,
the cursor information may interface directly to one of
the overlay inputs of the RAMDAC. Additional bit
planes or hardware, connected to the other overlay
inputs may be used for any additional overlay
functions. Four bits of overlay can emulate an
enhanced graphic adaptor window atop the main
graphics image.

In many instances, the graphics application software
is primarily concerned with the generation and
manipulation of images in the frame buffer. The
system software, on the other hand, is usually
responsible for cursor movement, menu insertion and
deletion, and user messages, with minimal concern
about the graphics image.
The use of one or two additional bit planes for
overlays enables the system software to control user
interface graphics independently of the graphics
image. Graphics performance is improved, as the
image in the frame buffer need not be modified each
time the cursor is moved or a menu is displayed or
removed. The problem of cursor avoidance during the
image drawing process is also solved by
implementing the CUrsor using an overlay approach.

Summary
Overlays provide a means of simplifying the
implementation of user interface mechanisms such as
cursors, menus, and any type of graphics or text
information that is to be displayed independent of the
main graphics image.
The separation of system user interface software and
graphics generation software will usuaJly increase
graphics performance and simplify software
interfacing to the graphics system.

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580 • (800) VIDEO IC
TLX: 383596· FAX: (619) 452-1249

2 - 19

•

AN-4

2 - 20

APPLICATION

NOT E

Expanding VGA Graphics With the
Bt471/475/476/477/478 Family
The IBM Personal System/2 introduces graphics
display versatility to personal computer software and
calls for more versatile digital-to-analog converters
to take advantage of the greater software power. The
Bt4711475/476/477/478 family of pin compatible
RAMDACs support the basic capabilities of the IBM
hardware as well as several added performance features
which help differentiate board-level products in the
compatible PC and expansion board markets.

C. A fully synchronous read-mask feature eliminates
the need to externally synchronize the MPU write
strobe to the pixel clock.
D. Support of both sync and MPU read-back on the
Bt471, Bt475, Bt477, and Bt478 provides direct
compatibility with RS-343 monitors without
sacrificing future software system or self testing
capabilities. The IMS® G171 device offers one or the
other of these features, but not both, in one unit.
Selectable setup levels (0 or 7.5 IRE) allow the user to
optimize the retrace intensity for each monitor
assuring international hardware compatibility. The
Bt475 and Bt477 include on-chip comparators on the
analog outputs for diagnostic capability, eliminating
the need for external analog comparators.

The Bt47x family features more palette colors, higher
speeds, overlay planes, simultaneous composite
video and read-back, and surface mount packaging.
These features afford the board designer flexibility and
component savings for positioning his product in a
dynamic marketplace.

Performance Features

E. The Bt47x family also offers a choice of more
stable voltage references, or a cheaper current
reference that is 100% compatible with the existing
PS/2 hardware. The Bt475 and Bt477 offer an on-chip
voltage reference, or the option of using an external
voltage or current reference.

Enhancements to the IBM hardware implementation
(based on their Video Graphics Array) include:
A. Programmable choice of 262 thousand or 16.7
million color palette. On the Bt477 and Bt478 , a
single pin programs the length of the palette word to
be either 6 or 8 bits per color channel. For business
graphics or false color renderings 6 bits is adequate,
but for presentation graphics of subtly shaded
objects, 8 bits per channel is now standard on most
Computer Aided Engineering (CAE) workstations and
the Apple Macintosh II.
More precise color
segmentation can compensate for monitor
inconsistencies (such as gamma effect) and reduce the
"cartoon" appearance of color-limited palettes.

F. More robust output capability for driving doubly
terminated cables greater distances (or looped through
more monitors) with crisper transitions and lower
reflection "ghosts". Brooktree guarantees linearity in
terms of peak errors (not RMS) under
doubly-terminated conditions. The coaxial medium
between the DAC output and the monitor input calls
for superior pulse fidelity to reduce amplitude ringing
and monitor mistermination which can make pixels
appear fuzzy, jittery or to have shadows.

B. A 4-bit overlay port on the Bt471, Bt475, Bt477
and Bt478 makes special effects, such as cursors,
borders, or even full EGA windows easy to implement
on pixel-by-pixel boundaries, without the additional
microprocessor burden of updating the pixel read
mask for special effects.

G. An efficient 44-pin PLCC surface mount package
occupies less board area than the 28-pin DIP
counterpart. The lower PLCC prome improves power
supply feedthrough and grounding as well by lowering
package inductance 50%.
H, The Bt476 offers a pin-compatible solution to
the IMS G176, and is available in both the 44-pin
PLCC and the 28-pin DIP package.

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580· (800) VIDEO IC
TLX: 383596· FAX: (619) 452-1249

2 - 21

•

AN·5

Implementing Enhanced Graphic
Overlays

The use of a read mask in the IMS GI71 to generate
special effects is fully supported (internally
synchronous) in the Bt47x family, but its update rate
is limited by the MPU write cycle time of 3 to 4 pixel
clocks. This means that the mask effect will appear
no finer than several pixels on the screen. This may
save palette RAM size but prohibits high resolution
overlays such as an EGA style window over a large
part of the viewing screen. In situations where pixel
frequency must be agile and independent of the MPU
clock, the synchronous buffering of the Bt47x family
prevents corruption of the palette contents,
something that can occur with asynchronous IMS
G 171s when the pixel clock is not locked to the MPU
clock.

The PS/2 graphics format is distinguished by its
higher vertical resolution, variable frame rate, and its
8-bit pixel architecture. To take advantage of
multi-frequency monitors, the mM 8514A resorts to
interlacing at higher resolutions to provide near
megapixel displays at a reasonable price, supporting
interlaced 1024 x 768 resolution at a 43.5 Hz refresh
rate.
Since interlacing compromises display
phosphor response to reduce flicker, faster pixel rates
are desirable to achieve 60 Hz refresh rates without
flicker or smearing. Non-interlaced 60 Hz formats of
1024 x 768 or 1024 x 1024 can be supported by the
80 MHz Bt47x family.

The four overlay inputs to the color palette can be
loaded and invoked in the same manner as the standard
palette. An additional register select pin (RS2) is
provided for loading and reading back the overlay
values. In the read mode the overlay inputs override
the PO - P7 pixel inputs, so any unused pixel and
overlay inputs should be tied low. This parallel
palette access simplifies cursor or cross hair
generation to where a single chip (such as the Bt431)
can manage this function with direct connection to
the overlay inputs of the Bt471, Bt475, Bt477, or Ihe
Bt478.

The non-interlaced formats keep the full 640 pixel
horizontal resolution of the previous eGA, EGA and
PGC formats while giving the preferred 4:3 aspect
with 480 vertical lines at a frame rate of 60 to 70 hertz
(320 x 200 with pixel replication). The 8-bit pixel
word size provides for 256 simultaneous colors from a
palette of 262K colors (6 bits per channel) or 16.7
million colors (8 bits per channel with the B t477 or
Bt478).
As the power of the VGA to do complex graphic
operations in real time becomes fully supported by
the software industry, it will be possible to mix
various formats on screen to create sophisticated
windows, cursors and overlays. The independent
palette access provided by the overlay ports on the
Bt471, Bt475, Bt477, and Bt478 will enable parallel
generation of graphic effects without imposing
additional MPU limitations.

With proper synchronization and raster scaling
through the feature connector common on EGA cards,
direct superposition of an EGA image over a VGA
display is possible without burdening the VGA
interface.
This mUlti-path approach to high
resolution windows is inherently faster and more
interactive than software driven techniques and
compares wilh hardware window features found on the
more sophisticated graphics systems processors. This
technique can be done on a pixel-by-pixe1 or
bit-by-bit basis so that the full resolution capability
of the multi-frequency monitor can be used.

VAA
OPA

~--------~'-~llUW
COMP

VREP

VAA

TL43lC
(8-PIN so PKG.)

Figure 1.

Bt47x

External Current Reference.

2 - 22

Broddree~

AN-S

Suitable References

Optimum Termination

The quality of the image produced by the DAC can
depend on the stability and regulation of its reference.
The Bt47x SMD family offers the user a choice of
current or voltage references so that either drop-in
compatibility or optimum performance can be
provided. The 28-pin DIP version of the Bt476
supports only the current reference mode and is 100%
compatible with the IMS G176.

The analog interface between the RAMDAC and the
display monitor must have transmission line
properties to assure proper pixel definition on the
display. Where TTL monitors can tolerate pulse
ringing and cable echoes due to their binary nature,
analog displays must settle to within 1% amplitude
accuracy well within the pixel duration to render 6- or
8-bit color values faithfully. Double termination of
the coaxial cable with the characteristic impedance of
the cable is desirable since it lowers the lumped
time-constant at the DAC node and attenuates signal
reflections from the monitor (or loop through nodes),
which can produce pixel smearing or ghosting with
cables longer than 2 meters.

The Bt47x SMD family uses the voltage reference in a
closed feedback loop control circuit which provides
each individual current cell with a stable voltage
reference. This common voltage reference can be
externally decoupled at the compensation pin to
minimize noise disrurbance due to current switching.
The combination of closed-loop stability, direct
reference decoupling, and compatibility with low
temperarure coefficient voltage references gives the
Bt47x family superior amplitude stability and noise
immunity. This results in cleaner images on the
graphics display monitor.

A lower termination resistance at the DAC node
neutralizes the connector and cable capacitance but
forces the DAC to put out as much as 30 rnA to produce
Iv peak to peak at the monitor input. A lower tilJ:Ie
constant produces faster transitions and settling,
which means crisper pixels on the display with truer
color rendition.

Figure 1 shows a typical current reference circuit for
the Bt47x family. These components are available in
surface mount packages, but notice the current
reference approach requires 2 additional passive
components. The simplest 4 rnA current reference
available, a Motorola MCL1304 or Siliconix CR430
type JFET device, offers only ± 15% to ± 25%
accuracy, which would only be tolerable in
analog-EGA applications or where the monitor
contrast adjustment could compensate.

Figures 2 and 3 depict the 64 code steps of the IMS
GI71 and Bt471 driving a 75-ohm doubly-terminated
load. A Tektronix 2465 scope (300 MHz BE) was used
in the expanded sweep mode to highlight the
mid-scale glitch that occurs during the binary 31 to 32
code transition. The characteristic 1/4 - 1/2 - 3/4
scale glitches of the IMS G 171 are evident on the 700
mV amplitude waveform.
The expanded scale is calibrated to give graticule
square areas of 500 pV-sec (100 mV ... 5 ns). The
mid-scale glitch of the IMS G171 consists of clock
feedthrough with an approximate impulse area
approaching 120 (12 LSB-ns) pV -sec, while the
Bt471 mid-scale glitch area is less than 50 pV-sec.
Clock feedthrough produces little visible aberration
on the monitor since it represents an equal amount of
energy every pixel. However, glitch impulse may be
visible when it exceeds 1 LSB/BW monitor, since it
occurs only on specific code transitions.

Setup and Sync
While the mM-PC graphics standards have always
provided for separate TTL synchronization lines,
traditional analog monitors work with composite
synchronization super-imposed on the green video
channel. The Bt471/475/471/478 devices provide
composite sync on all channels by asserting a low
pulse on the SYNC* pin, which turns off an internal
40 IRE pedestal on each video channel.

Resolution

Blank assertion in the composite format is more
reliable (from a noise standpoint) if a 75 IRE pedestal
distinguishes the black and blank voltage levels. This
setup level provides for blacker-than-black CRT beam
retraces which reduce visible retrace lines on bright
displays. For this reason a selectable setup pedestal
is provided to optimize the sync and blank interface
for most multi-frequency analog monitors and various
international raster video formats (NTSC, PAL,
SECAM, CCIR, etc).

The Bt477 and Bt478 offers an upgrade path to 8 bits
of resolution in the same pin compatible package as
the Bt471, Bt475, and Bt476. Figures 4 and 5 show a
comparison between 6 bits and 8 bits of resolution for
a 3D solid model.

2 -23

•

AN-S

The gray scale shading is limited and annoying to the
eye on the 6-bit rendering, offering only 64 shades.

The 8-bit image offers 256 gray shades and fine
shading. The 8-bit photo clearly shows the smooth
shading required for 3D modeling or professional slide
presentations.

Figure 2.

IMSG171 Output Waveform.

Figure 3.

Bt4711478 Output Waveform.

2 - 24

AN-5

•
Figure 4.

I·Bit Resolution Example.

Figure 5.

B·Bit Resolution Eample.

2-25

AN-5

Packaging
Note the internal chip capacitor in the
specially-tooled 28-pin DIP package of the IMS
G171. The chip capacitor mounted in the cavity
serves to compensate for the DIP package inductance.
This is less effective in terms of glitch suppression
than the inherently lower inductance of the 44-pin
PLCC package.

The IMS GI71 is photographed side by side with the
Bt47x in Figure 6. The Bt47x is shown in the ceramic
44-pin package and occupies considerably less area
than the IMS GI71 in the 28-pin DIP.

Figure 6.

Packaging Comparison.

PC Board Layout Tips
taken to limit supply noise at the DAC (in the
bandwidth of the analog channel. typically the pixel
rate) to 10 times the amplitude of the least significant
bit.

Printed wiring board design considerations for analog
output devices can be more critical than for pure
digital. Four-or-more layer boards are better for lower
power and ground noise as well as for segregating the
analog outputs and reference from the digital inputs.
This becomes even more important as speed
migration from 25 MHz to 75 MHz dictates faster
devices which generate more power supply spikes and
radiation. Migrating from 6 bits per channel to 8 bit
quantization compounds the need for low inductance
power and ground returns if true color rendition and
low electromagnetic emissions are to be achieved.

Multiple ground planes make it possible to isolate the
DAC current return to the system supply from other
digital circuitry while maintaining low plane-to-plane
potentials which affect the digital noise margins and
contribute to electromagnetic emissions. It is
desirable to reduce DAC ground noise to less than 10
m V during the active display line for clean looking 6and 8-bit displays.

The effect of supply and ground noise and digital
edges on the palette DAC is to produce
image-dependent artifacts on the display which are
especially perceptible when images are superimposed.
Even the best CMOS DACs couple about 10% of any
supply noise to the analog output. Care should be

2 - 26

AN-5

Performance Comparision Chart
Bt475/471

Bt476

Bt477/478

IMSG171

YES

Number of Displayable Colors

256 + 15

256

256 + 15

256

Maximum Number of Bit Planes

12 (8 +4)

12 (8 + 4)

IBM PS/2 Compatible

Total Palette Size

256K

256K or 16M

256K

Frequency (MHz)

35/50/66/80

35/50/66

35/50/66/80

35/50

Palette Read-Back

YES

Voltage or Current

Current

Optional Internal Reference

YES

RS-343A and CCIR Standards

YES

Analog Output Comparators

YES

Power Down Capability

YES

m
m

YES

m
m
m
m

Integral Linearity

0.25 LSB (0.4%)

0.5 LSB (1%)

1 LSB (0.4%)

0.5 LSB (1%)

Differential Linearity

0.25 LSB (0.4%)

0.5 LSB (1%)

1 LSB (0.4%)

monotonic

75 pV-sec

200 pV-sec

Sync on Video
Full Scale Reference

Glitch Impulse
Overlay Capability

YES

Rise/Fall Time

3ns

3 ns

8 ns**

Fully Static

Req. Constant Clock***

Memory Technology
Compatible Family

YES

Almost*

Monolithic

YES

On Board Chip Cap

Surface Moumable

YES

44-pin PLCC

Package

or 28-pin DIP

28-pin DIP
or 32-pin PLCC

*Due to limited number of pins in the !NMOS pin-out, trade-offs have been made between products. For example, the pin that
allows the color palette to be read in the IMS G171/3/6 is used for SYNC in the IMS G170/2/4 thereby inhibiting the ability
to read back the color palette on the later parts. Also, the 6-bit data used in the IMS G 170/1/2/3 can not be used directly with
the 8-bit IMS G 174/6 because the 6 bits are located in the LSBs and would result in an output 1/4 the brightness. Brooktree
has a 6/8-bit pin that allows 6-bit code written for either the Bt471/475/476 or the IMS GI70/1/2 to run on the 8-bit
Bt477/478. Comparisons are based on the Brooktree Bt471/476/478 specification sheet L478001 Rev. L, Bt475/477
specification sheet L477001 Rev. B. and the IMS G171 specification sheet 42-1008-00 dated April 1987.
**Single 75-ohm termination, Bt47x family rated for 75-ohm doubly-terminated loads.
***Pseudo-static RAM cell
Personal System!2 and PS/2 are registered trademarks of IBM. Macintosh is a licensed trademark of Apple Computer, Inc.
IMS is a registered trademark of Inmos, Limited.
2 - 27

•

AN-5

2 - 28

APPLICATION

NOT E

Troubleshooting Your Brooktree
CMOS VIDEODAC or RAMDAC
Power Supply Considerations

Decoupling Capacitors

Brooktree devices offer power supply rejection,
however, this noise rejection decreases with
frequency. Therefore, the noise on the power pins
must be kept to a minimum. In particular, about 10%
of any frequency components over about 1 MHz will
be coupled onto the output. The VREF and CaMP
pins should be checked to assure noise is minimized.
This can be accomplished by keeping PCB and lead
lengths to decoupling capacitors short and wide.
Decoupling VREF and CaMP pins to VAA is vital to
reducing switching noise and overshoot on the DAC
output.

One of the most common problems is choosing the
proper power supply decoupling capacitors and
keeping the leads short enough. Refer to
recommended capacitor types in individual datasheets.
All capacitors exhibit a self-resonant point at which
they no longer look like capacitors, but inductors.
This resonant point is a function of frequency,
capacitor material, lead length, and the PCB trace
length of the power and ground traces where the
capacitor is soldered. Above self resonance, a
capacitor looks like a series resonant inductor (with
approximately 1 nH per 0.1 inch of lead length).

Another useful technique is to mount a three terminal
regulator close to the power supply pins to provide
immunity to power supply transients, and use the fact
that the regulator will provide excellent power supply
ripple rejection. When operating from a switching
supply with greater than 100 m V of noise, a two stage
VAA decoupling filter is advisable. A CLC pie filter
combination ahead of the attenuator bead should have
a time constant value much less than the switching
frequency to be effective. When using a VAA filter,
ensure that V AA power is applied before the inputs to
prevent latch-up.

For example, a 0.1 ~F ceramic radial lead capacitor
with 1/4 inch leads generally resonates around 10
MHz. A 0.01 ~F ceramic radial lead may resonate
around 40 to 60 MHz while a 0.01 ~F ceramic chip
capacitor may resonant around 400 MHz.
As power supply transient frequencies approach the
resonant point, the capacitor offers less effective
filtering. At resonance, it is neither a capacitor nor
inductor. Past resonance, it becomes an inductor and
may exhibit transmission line effects.
To overcome these problems, the parallel connection
of a 0.1, 0.01, and 0.001 ~F capacitors will generally
overcome the most difficult transients. For the lower
frequencies, a 10 ~F tantalum capacitor is the best
choice, mounted near the power and ground pins.

The DAC can have significantly more noise than is
seen on the supply bus. Always probe the power
supply signals with an oscilloscope probe at the
device pins. Probe ground (AC coupled) less than one
inch from DAC ground. Measure VREF noise relative
to VAA.

Brooktree Corporation
9950 Bames Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580 • (800) VIDEO IC
TLX: 383596· FAX: (619) 452-1249

2 - 29

•

Broddree~

AN-6

Attenuator Beads

ESD and Latchup Considerations

The purpose of the ferrite attenuator beads is twofold.
First, they isolate fast transients (i.e., less than 1 ns)
on the regular PCB power plane from the device. They
will reduce any fast transients and act as increasing
AC resistance with frequency. These frequency vs.
impedance characteristics are diagramed in
Application Note 1. Therefore, a decoupling capacitor
close to the bead and the DAC power pin for long lead
length is needed. Second, the ferrite beads also
isolate high-frequency noise generated by the
VIDEODAC or RAMDAC from being coupled back
onto the main PCB power plane.

Correct ESD handling procedures are required to
prevent damage which can produce symptoms of
catastrophic failure or an erratic device behavior with
somewhat leaky inputs.
Latch-up can be prevented by assuring all VAA pins
are at the same potential, and that the VAA supply
voltage is applied before the signal pin voltages. The
correct power-up sequence assures that any signal pin
voltage will never exceed the power supply voltage
by more than -to.5v.

No Video Information
Experience has found that the ferrite beads are usually
not required where the video bandwidth is less than
one tenth the time constant of the logic. As an
approximation, if the clock rate is less than 10 MHz,
beads are usually not necessary but become
increasingly important for frequencies above 50 MHz.

Verify that all power pins have the correct voltage. If
a constant DC output is generated, it indicates that the
DACs are probably not functioning correctly. The
voltage on the VREF pin should be checked flIst to
verify that the external voltage reference (if used) is
operational. Decoupling of VREF to VAA near the
DAC is vital to reduce switching noise on the DAC
output.

Many of Brooktree's devices have signal edges on the
order of 2 or 3 ns, which produce harmonic
components in the 300 MHz to 500 MHz range. The
beads attenuate these components from the PCB
supply planes.

The voltage on FS ADJUST should be very close to
the VREF voltage. If the device contains an on-chip
reference, the measured voltage at the FS ADJUST pin
should be approximately equal to the specified
internal reference voltage. Offsets of greater than 10
m V may indicate damage to the internal op-amp.

When using Surface Mount Technology (SMT) beads,
watch the current rating. Bipolar DACs may use
ferrite breads on their power pins for stability, while
CMOS DACs are for noise rejection. Attenuator beads
in the DAC ground return must have tens of ohms of
resistance at high frequency to be an effective
attenuator. However, this can produce ground
potentials of greater than the intrinsic noise margin
when DAC currents are greater than 100 mAo
Therefore, ground beads are not recommended for
DACs with dynamic currents of greater than 100 rnA.

The COMP pin must be coupled to VAA through a
ceramic capacitor and the lead lengths kept to an
absolute minimum. The voltage on the COMP pin is
nominally 3v to 4v. A voltage close to Ov or 5v
indicates a bad COMP capacitor, a COMP trace shorted
to power or ground, or a bad device. The output traces
for video information should be checked for shorts to
power and ground supplies.

Digital Input Considerations
The control, pixel, overlay input setup and hold times
should be verified. To ensure reliable operation over
the full temperature and power supply range, the
CLOCK input should be buffered by a single dedicated
buffer that assures fast edges with glitch free levels.

Some of the newer TTL logic families have very fast
rise/fall times. It is possible for these fast transients
to couple onto the analog outputs, resulting in
excessively noisy analog signals.
Possible solutions are to put a 33 to 100 ohm
limiting resistor in series with the digital inputs at
their source, or use a resistor terminating network
(220/330 ohm) at the expense of additional power. A
slower logic family, such as ALS, LS, may be used if
possible to reduce the input rise/fall times where pixel
rates are less than 25 MHz. Noise on three-state lines
should be avoided through termination.

2 - 30

AN-6

Incorrect Analog Output Information

Nonlinear Gray Scale Analog Output

If sync and blank infonnation are output, but they are
not the correct levels, verify the RSET resistor value,
the voltage on VREF and FS ADJUST (they should
match), and the output load. When looking at the
voltage levels on the video outputs, the oscilloscope
probe must have 75-ohm termination, to form the
other termination of the doubly-tenninated 75-ohm
load.

If the gray scale video appears to be nonlinear or
compressed at one end of the gray scale, the
compliance limits of the device are probably being
exceeded.
Voltage levels on the analog outputs outside the
compliance limits forces the DACs to operate in a
nonlinear fashion. The greater the exceeded voltages,
the more nonlinear the D/A operation will be.
Incorrect output loading, a wrong value for the RSET
resistor, or an incorrect reference voltage are the
primary causes.

If the sync and blank levels are correct, the analog
section of the device is probably operational, and the
problem is probably the microprocessor or pixel data
interface.

Noisy Analog Output
Ensure that all of the control registers and color
palette RAM are properly initialized following
power-up. T)le contents of the control registers and
RAM may be read back by the MPU to verify their
contents. The chip select or chip enable input should
always be a logical one, except when the MPU is
accessing the device.

Excessively noisy analog outputs indicates that either
the power supply pins, the COMP pin, or the VREF
input have an excessive amount of power supply
noise that is not being decoupled, or there is
excessive undershoot/overshoot on the digital inputs.
Refer to Application Note 1 or contact the Brooktree
technical hotline for further assistance at:
1 (800) VIDEO Ie

2 - 31

•

AN·6

2 - 32

APPLICATION

NOT E

RAMDAC Initialization
Note: 40H in the command register configures the
device as follows:

Brooktree RAMDACs need to be initialized through
the microprocessor port after power-on. The
initialization procedure differs slightly depending on
how many control registers the RAMDAC contains.
Using the Bt458 as an example, Figure 1 shows the
four control registers, pixel port (fast port), MPU port
and bus control (slow port), and the DAC outputs. The
microprocessor initializes the Bt458 through the MPU
port.

·4:1 mux
• Enable color palette RAM
• Blink rate = 16/48
• Blink disable
• Forces overlay inputs to logical zero
Repeat the control register sequence using the
following values to initialize the other command
registers. Set R/W* and strobe CE* after every line.

Bt458 Initialization Procedure
1.

Initialize the control registers:

• Write 0,0 to Cl,CO
• Put 06H on data bus
• Pull R/W* low
• Strobe CEO
• Write 1,0 to Cl,CO
• Put 40H on data bus
• R/W* low, Strobe CE*

set to write address
register
address of command
register
write mode
write address to address
register
set to write command
register
data to command
register
write to command
register

C1.CO

DataBus

·0,0
• I, 0
·0,0
• 1,0
·0,0
• 1,0

04H

FFH
05H
OOH
07H
OOH

PIXEL

; write read mask address
; FF hex to read mask register
; write blink mask address
; 00 hex to blink mask
; write test register address
; 00 hex to test register

R
G

COLOR

ADDRESS

CE" R/W" Cl CO

Figure I.
Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580 • (800) VIDEO IC
TLX: 383596· FAX: (619) 452-1249

DATA BUS

Bt458 Ports.

2 - 33

•

AN-7
2. Write the color palette starting with location 00
hex. Set R/W* and strobe CE* after every line.
Cl,CO
• 0, 0
• 0, 1
• 0, 1

• 0, 1

Data Bus
OOH

rrH
ggH
bbH

; write palette address OOH
; write red value (hex)
; write green value (hex)
; write blue value (hex)

Cl,CO

Data Bus

• 0, 1
• 0, 1
• 0, 1

rrH
ggH
bbH

; write red value (hex)
; write green value (hex)
; write blue value (hex)

3. To read back the palette or control registers, use
the same sequencing but set R/W* high.
4. To write/read the overlay palette; set Cl,CO to 1,1
and continue as in step 2.

Note: At this point, the palette address pointer
auto-increments to address 01H. One must rewrite the
address pointer to access locations other than 01H.

This application note explains a basic program flow
for initializing a Bt458 RAMDAC. The Brooktree
databook contains further information concerning
operation of this and other RAMDACs.

2 - 34

AN-7
Bt458 INITIALIZATION PROGRAMMING SEQUENCE
TABLE OF OPERATIONS
STEP CE*

Command
Register

R/W* Cl

D7 D6 D5 D4 D3 D2 Dl DO

OOMMENT

,j,

WRITE ADDRESS REGISTER

DATA 06H INTO ADDRESS REGISTER

,j,

POINT TO CONTROL REGISTER

DATA40HINTOCONfROLREGISTER

,j,

WRITE TO ADDRESS REGISTER

Read

DATA 04H TO ADDRESS REGISTER

Mask

,j,

POINT TO READ MASK

DATA FfHTO READ MASK

WRITE TO ADDRESS REGISTER

't"

0
X

DATA 05H TO ADDRESS REGISTER

-l-

POINT TO BllNKMASK

DATA OOH TO BLINK MASK

,j,

WRITE TO ADDRESS REGISTER

DATA 07HTO ADDRESS REGISTER

,j,

POINT TO TEST REGISTER

DATA OOH TO TEST REGISTER

,j,

WRITE TO ADDRESS REGISTER

DATA OOH TO ADDRESS REGISTER

,j,

POINf TO PALETI'E RED

't"

0
X

-l-

,j,

WRITE TO ADDRESS REGISTER

DATA OOH TO ADDRESS REGISTER

,j,

POINT TO OVERLAY PALETI'E 0

,j,

9
Blink
Mask

Test
Register

Write
Color
Palette

Read
OVLO

31
32

RED VALUE
X

DATA TO RED PALEITE
X

GREEN VALUE
X

DATA TOGREENPALEITE
X

RED VALUE AVAILABLE

RED VALUE
X

GREEN VALUE
X

BLUE VALUE

2 - 35

POINf TO PALETI'E BLUE
DATATOBLUEPALETI'E

BLUE VALUE

POINfTO PALEITE GREEN

POINT TO OVERLAY PALETI'E 0
GREEN VALUE AVAnABLE

POINTTO OVERLAY PALETI'E 0
BLUE VALUEAVAnABLE

•

AN-7

2 - 36

APPLICATION

NOT E

Building a 4K Look-up Table
with the Bt457
Palette Applications

The address bus is presented to the RAMs by way of
two F244 devices. These provide an output enable
such that during a display, the F374s are always
enabled and the F244s are disabled. The same address
would be provided to each of the look-up table;>.

The need for a 4K look-up table for graphics is found
in such applications as medical imaging, solids
modeling and electronic publishing. A discrete
implementation using three Bt457 single channel
RAMDACs, twenty-four 4K x 4 static RAMs and
miscellaneous MSI circuitry is all that is needed to
implement this application.

The MPU data interface is a bit different. First, a
bidirectional bus is needed so that the data stored in
the color palette can be read back by the MPU. For
this reason F245 devices are used. Second, each of the
ROB channels is provided with its own 8-bit data bus.
By using a 32-bit bus the red, green, and blue palettes
can be written simultaneously. A counter can be
included to generate the addresses so that the 4K
addresses can be auto-incremented. The direction of
the data bus is determined by the value on the RD*
line. Eight bits are also needed for the RAMDAC MPU
interface.

The circuitry for one of the three channels is shown in
Figure 1. This would be duplicated for each of the red,
green and blue channels. Each channel interfaces to
the twelve plane frame buffer with two F374 devices.
Four sets of 12-bit pixels are supplied to the registers
from the frame buffer. Since the ROB planes use the
same address, these registers can be used for all three
channels.
The register's outputs are sent to the address inputs of
the 4K x 4 static rams. Eight of these are needed for
each of the three channels. The output data is then
input into another set of F374 registers. The data has
now been reduced to eight bits, which are used as pixel
data. Four sets (A-D) of 8-bit pixel data are provided
to the pixel inputs of the DACs for color generation.
This provides 4:1 multiplexing of the Bt457 input.

If direct color generation is needed, the Bt457 palette
wouldn't be used as a look-up table, and the pixel
address would be the same as the data. If gamma
correction, or any other image transformation is
needed, then the RAMDAC would need to be
programmed accordingly.

Mapping the Bt457 internal LUT RAM allows the
pixel data to be used as 8-bit data for the D/A
converter, or the Bt457 RAMs can be programmed so
that gamma correction, image manipulation or window
palette switching can be performed.

The limiting factor in building the 4K solution
discretely is the overall performance of the video
generator. The screen resolution is directly related to
the speed of the MSI circuitry and the static RAMs.

Performance

The delay of the pipelines is as follows:

MPU Interface
F374 Clock to Q
10 ns
Static RAM access(read) 20 ns
F374 Setup Time
2 ns
Interconnect delay
4 ns

The microprocessor interface to the color palette is
provided by a 12-bit address bus and an 8-bit data bus
for each of the channels.

Total delay

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580 • (800) VIDEO IC
TLX: 383596· FAX: (619) 452-1249

2 - 37

36 ns

•

Broddree~

AN-8
True Color Application

Because 4: 1 multiplexing is used, the time for each
pixel generated is 36/4 = 9 ns. This corresponds to a
clock frequency of 111 MHz.
With this
implementation a 1280 x 1024 resolution system
(with 60 Hz refresh) can be achieved. To increase the
performance of the system, use of faster VRAMs (33
MHz), or a 2:1 mUltiplexing between the VRAMs and
LUT is required.

A true color (36 plane) system can be achieved by
multiplexing data from a frame buffer with the LUT
output as shown in Figure 1. The F374 outputs would
be disabled via True Color Select, and the true color
data would be enabled on the red, green and blue
channels.

An 8:1 LUT architecture could also be used. This would
require mUltiplexing the output of the LUT to the
Bt457 and also a significant cost increase due to a
doubling in the amount of SRAMs. Another approach
to increase the resolution of the system is to use faster
RAMs as they become available. By using SRAMs
with a 15 ns access time, the given architecture can
achieve a video rate of 129 MHz.

Using the Brooktree Bt457 RAMDAC, a 4K color
palette system can be created with the use of standard
MSI products and CMOS static RAMs. The 4K palette
provides enough simultaneous color for modeling
applications and medical imagery. It can be easily
implemented using the methods described in this
application note.

This information is intended for
stimulating design interest and has not
been breadboarded.
Brooktree accepts no
liability for designs contained in this
application note. All users are cautioned
to verify their own design.

1'0- Pll (0)

PO-P7(O)

(10)741'374
(6)74244
(4)74245
(8)20ns4Kx4
Static RAMs

True Color Select

CS·

Figure 1.

MPU

ADDR

DATA

4K Look-up Table Solution using the Bt457.

2 - 38

NOT E

APPLICATION

Bt471/476/478 Power Saving Features
Various circuit configurations will allow significant
savings in power requirements when used with the
Bt471/476/478. Laptop computers which support
VGA graphics capabilities represent an application
that can benefit from utilizing these power saving
configurations. Battery-operated portable laptops use
liquid crystal displays which do not require the VGA
RAMDAC to be active, therefore the Bt4711476/478
power saving modes can be used to reduce supply
requirements and extend battery life.

To eliminate the full scale output current and
associated supply current to the DACs, open circuit the
RSET resistor or pull the COMP pin up to VAA. Figure
1 shows a circuit for pulling the COMP pin to VAA.
The 0.1 ~F capacitor acts as a bypass capacitor
between the V AA and COMP pins. This capacitor
should be mounted as close as possible to the
RAMDAC, with the leads kept short. The P-channel
MOSFET with the source connected to VAA turns on
when the gate voltage drops below four volts. The
output of the 74HC03 open drain NOR gate pulls up
through a 2K-ohm resistor to VAA. A logical one at
the input to the NOR gate turns the DACs off.

The Bt4711476/478 may be powered down in the
following ways:
RegistersIMemory
Power Down Mode
Accessible
VREF - shut down the DACs
IREF - shut down the DACs
Stop the clock

Shutting down the DACs typically cuts the supply
current by forty percent. For the Bt471, each DAC
outputs three times the current flowing through the
RSET resistor. To get a DAC output current of 21 rnA,
the current through RSET must be 7 rnA (the actual
value will be slightly less to achieve the 19.05 rnA
value specified in the databook). When the DACs are
shut off, the total current saved will be 3 x 21 = 63
rnA.
At nominal supply voltage and room
temperature, the Bt471/476/478 typically requires
160 rnA. The power down current is therefore 160 - 63
=97mA.

Yes
Yes
No

VREF Power Down Mode
The VREF implementation provides an order of
magnitude improvement in amplitude stability and
noise immunity over an IREF implementation. For
this reason, using a voltage reference is recommended
over a current reference.

C aut ion:
Brooktree guarantees linearity
specifications for output voltages up to 1.6 volts and
for output currents down to one half of full scale.

Siliconix alternate sources:

Philips #BS250
Topaz #VPI06
BS250 Typical Parameters:
IDSS@ vas =Ov= -O.5mA
vaS@ID=l rnA =- 2.75v
BVDSS @ vas = Ov = - 20v

DACON=O
DACOFF= 1

Figure 1. DAC Shutdown Using
the COMP Pin.
Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580 • (800) VIDEO IC
TLX: 383596· FAX: (619) 452-1249

2 - 39

Brodrtree®

AN·9
IREF Power Down Mode

Stopping the Clock

For systems using a reference current (IREF), shut
down the DACs by open circuiting IREF. Like the
VREF mode above, the IREF current is proportional to
the DAC output current. Figure 2 shows a circuit for
supplying a constant current to the IREF pin. Drive
the base of the NPN transistor with a low TTL logic
signal to turn the DACs off. In the power down mode,
the RAMDAC is fully register/memory compatible.
Powering down the Bt471/476/478 typically cuts the
supply current by forty percent and also saves the
IREF current. For the Bt471 as discussed in the
previous section the supply current is 160 - 63 - 7 = 90
rnA.

This mode is useful in applications where the designer
does not need register compatibility or active video.
The Bt471/476/478 static RAM does not require
clocking to retain memory data. With the DACs on,
this power-down mode saves about 10 mAo Shutting
off the clocks with the DAC powered down saves 2 to 3
mA. See Figure 3.

lREF
Bt471/476/47

RSET

0.1 4.7

y
VAA

OUT
LM317
TO·92PKG
ADJ
":"

RSET =

1.4V
!REF

Figure 2. Open Circuit IREF.

1HREE-STATE
PIXEL CLOCK
74AS244

Figure 3. Clock Stopper Circuit.

2 -40

TIL INPUT
O=DACOFF
l=DACON

AN-9
Summary

Bt475/477 Power-Down RAMDAC

This application note shows several methods to reduce
power consumption on Brooktree's Bt471/476/478
RAMDACs. Designers will find these power savings
useful in laptop computers with VGA graphics
capabilities.
System designers may use the
Bt471/476/478 power-down capabilities to
differentiate their products and improve performance.

Brooktree has developed the Bt475 (6-bit) and Bt477
(8-bit) power-down RAMDACs specifically for laptop
applications. The Bt475/477 feature software
controlled power-down capabilities, reducing standby
supply current to as low as 1 rnA with register
compatibility.
The Bt475 and Bt477 are
pin-compatible with the Bt471/476/478 RAMDACs,
facilitating drop-in replacement.
Also included on the Bt475/477 are on-chip analog
output comparators, on-chip voltage reference, and
circuitry to prevent "sparkling" when the MPU
accesses the color palette RAM during active video.

This
information
is
intended
for
stimulating design interest.
Brooktree
accepts no liability for designs contained
in this application note.
All users are
cautioned to verify their own design.

2 - 41

AN·9

2 - 42

APPLICATION

NOT E

Support Components
Brooktree's Technical Hotline has received many requests for assistance in identifying and locating components used
with Brooktree products. Brooktree's databook and datasheets recommend components that are not always available
in all areas. The following is a list of suggested manufacturers and components that will assure optimum performance
of Brooktree products.

Crystal Oscillators
Many of the Brooktree CMOS RAMDACs require a positive ECL differential clock. Common 10K and lOOK ECL
crystal oscillators powered from +5 volts will provide this positive clock.
The following crystal oscillators come in a 14 pin DIP outline package. Pin 7 is ground, pin 14 is +5V, pin 8 is the
clock output, and when a complementary output is available, it is on pin 1.

Manufacturer/
Supplier
Monitor Products
502 Via Del Monte
Oceanside, CA 92054
(619) 433-4510

Model/Part
Number

Description
For 10K ECL clocks to 200 MHz, case floating,
· open
emitter output,

970EA

970EAl

·
·

970T
Vectron Laboratories, Inc.
166 Glover Ave.
Norwalk, CT 06850
(203) 853-4433
In the U.K.:
Lyons Instruments
(099-24) 67161
Fox Electronics
6225 Presidential Court
Fort Myers, FL 33907
(813) 482-7212
Conner-Winfield
1865 Selmarten Road
Aurora, IL 60505
(312) 851-4722

CO-633
CO-450

For ECL clocks to 200 MHz
For lOOK complementary ECL clocks from 5- 400
MHz

F5L

FlIOO

·
·
·
·

ECLA-l
ECLA-2
S15R6
S17R6

Brooktree Corporation
9950 Bames Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580 • (800) VIDEO IC
TLX: 383 596 • FAX: (619) 452-1249

For 10K ECL clocks to 200 MHz, case floating,
complementary open emitter outputs.
For TTL clocks to 80 MHz.

2 - 43

For lOKH ECL clocks to 200 MHz - Pin 7 (case
ground) is an option
For TTL clocks to 80 MHz

For 10K, 8-150 MHz, case tied to pin 14
For lOOK, 8-150 MHz, case tied to pin 14
For TTL, 0° to 70° C, 256 KHz-80 MHz
For TTL, 55° to 125° C, 256 KHz-80 MHz

•

AN-to
Ferrite Beads
Decoupling the power to Brooktree's products through a ferrite bead is recommended to prevent power supply noise
from being coupled into the video outputs. Use of a ferrite bead is also recommended for suppressing interference
caused by the fast switching times of the DACs.
Ferrite beads have a very low impedance at low frequencies which increases at higher frequencies. Refer to AN-! for a
typical impedance curve. Beads are selected for their impedance at a standard frequency of 100 MHz, typical.

Manufacturer/
Supplier

Model/Part
Number

Fair-Rite Products
Corporation
P.O.Box J
Wallkill, NY 12589
(914) 895-2055
In the U.K.:
Apex Inductive Devices
(01) 903-2944

2743001111

Description

· Surface mount, 89 ohms @ 100 MHz

2743021446

TDK Corporation
4711 West Golf Road #300
Skokie, IL 60076
(312) 679-8200

CB30-1210

Ferroxcube
5083 Kings Hwy
Saugerties, NY 12477
(914) 246-2811
Canada: (416) 561-9311

5659065-3B

Axial lead, 71 ohms@ 100 MHz

· Surface mount, 52 ohms @ 100 MHz
· Axial lead, 85 ohms @ 100 MHz
· 38 ohms@ 100 MHz

BF45-4001

2 - 44

AN·tO
Sockets
For high speed operations and proper heat dissipation, it is generally recommended that Brooktree products be
soldered directly to the PC board. However, when prototyping or operating at clock rates less than 50 MHz, or where
some degradation of performance is acceptable, sockets can be used. The following is a listing of commonly
requested sockets.

Manuracturer/
Supplier
AMP Inc.
Harrisburg, PA 17105
(717) 564-0100
Canada: (416) 475-6222
U.K.: 44-1-954-2356
W. Germany: 49-6103-7090
Japan: 81-3-404-7171

Model/Part
Number

Descr.lptlon

641444-2
641746-2

• 28 pin, surface mount
28 pin, solder tail

·
·

641343-2
641747-2

·
··
··

641345-2
641749-2
643151-2
643066-2

Burndy Corporation
P.O. Box 5200
Richards Ave.
Norwalk, CT 06856
(203) 838-4444

68 pin, surface mount
68 pin, solder tail
84 pin, surface mount
84 pin, solder tail

QILE28P-41OT

QILE44P-41OT

• 44 pin, solder tail

28 pin, solder tail

·
·
·

84 pin, solder tail

PLCC-28-P-T

28 pin

PLCC-44-P-T

44 pin

PLCC-68-P-T

• 68 pin

PLCC.:84-P-T

QILE68P-410T
QILE84P-41OT
QlLEXI'-1

McKenzie Technology
44370 Old Warm Springs Blvd
Fremont, CA 94538
(415) 651-2700

44 pin, surface mount
44 pin, solder tail

2 - 45

68 pin, solder tail

PLCC Removal tool

84 pin

•

AN-to
Sockets (continued):
The following sockets are recommended for use with Brooktree's PGA packages.

Manufacturerl
Supplier

Model/Part
Number

Description

Augat
33 Perry Ave.
Attleboro, MA 02703
(617) 222-2202
U.K.: (0908) 67665
W. Germany: (089) 576085
Japan: (03) 465-8457

PPS069-2A1130-L

Robinson Nugent, Inc.
800 East Eighth St.
New Albany, IN 47150
(812) 945-0211
Switzerland: (066) 229822

PGA-068CM3-S-TG

Yamaichi
U.S. Distributers:
Nepenthe
2471 East Bayshore Rd.
Suite 520
Palo Alto, CA 94303
(415) 856-9332
McKenzie Technology
44370 Old WarmSprings Blvd
Fremont, CA 94538
(415) 651-2700

PPS084-2AI212-L
PPS 132-2AI414-L
PPSI45-2AI521-L

· 69 pin PGA, for 68 pin PGA package*
· 84 pin PGA*

· 145 pin PGA*
· 68 pin PGA*

IC93-10803-G4

*PGA package to PC board
standoff distance: 0.166"

84 pin PGA*

PGA-084AM3-S-TG
PGA-132AM3-S-TG

132 pin PGA*

*PGA package to PC board
standoff distance : 0.175"

· 84 pin PGA*
*PGA package to PC board
standoff distance: 0.236"

PGA69H003Bl1130T
PGA84H003B 1-

1212T
PGA132H003Bl-

1414T
PGAI45H003Bl-

1521T

2 - 46

· 69 pin PGA, for 68 pin PGA package·
84 pin PGA*

· 132 pin PGA·
· 145 pin PGA*

·PGA package to PC board
standoff distance: 0.165"

AN-tO
1.2V Voltage References
To meet RS170/RS343 tolerances, Brooktree DACs require a voltage reference of 1.2V ± 5%. The following devices
meet this requirement.

Manufacturer/
Supplier

Model/Part
Number

National Semiconductor
2900 Semiconductor Drive
Santa Clara, CA 95051
(408) 721-5000

LM385Z-1.2

Motorola Semiconductor
Products
5005 East McDowell Road
Phoenix, AZ 85008
(602) 244-7100
Japan: (03)440-3311
Hong Kong: 0-223111
U.K.: 0296-35252
W. Germany: (089) 92720

LM385Z-1.2

Maxim Integrated Products
510 North Pastoria
Sunnyvale, CA 94086
(408) 737-7600

ICL8069

Harris Semiconductor
2450 Walsh Ave.
Santa Clara, CA 95051
(408) 996-5000

ICL8069

Description

•

2 -47

AN-lO
Video Buffers
Brooktree's DACs are intended to drive transmission Jine loads, for which most monitors are rated. Transmission
line cable lengths greater than 10 meters can attenuate and distort high frequency pulses. Booster buffers can
compensate for some cable distortion but must have 6-12 dB voltage gain into the cable load to be effective. Select
buffers with ± 30 rnA drive, 2 - 4 volt output swing, and full power bandwidth greater than that of the monitor. When
selecting a buffer, consider the thermal and supply voltage requirements. Note: Buffers usually require supply
voltages greater than 5 volts.

Manufacturer'
Supplier

Model/Part
Number

Elantec
1996 Tarob Court
Milpitas, CA 95035
(408) 945-1323
U.K.: 0844-68781

EL2003

Harris Semiconductor
2401 Palm Bay Road
Palm Bay, FL 32905
(305) 724-7418

HA-5033

Comlinear Corporation
4800 Wheaton Drive
P.O. Box 20600
Fort Collins. CO 80522
(303) 226-0500

Description

· 3dB/50 MHz Unity Gain into 50

·
·
·

EL2020
EL2030

3dB/50 MHz Gain ~ 1 into 50 Q
120 MHz, Unity Gain
3dB/50 MHz Unity Gain into 50 Q

HAI-2542

3dB/50 MHz Gain 2 into 150 Q

CLC400/1

3dB/2oo MHz Gain 2 into 100 Q

Other Components
Metal film resistors are recommended for use with Brooktree's products because of low temperature coefficients and
low current noise.
For assistance in locating other components. call the Brooktree Technical Hotline at 1 (800) VIDEO IC.

2 -48

APPLICATION

NOT E

Mixed Signal Layout Considerations
Digital logic PCB design practices that rely on the
logic noise margins to assure correct operation are
not adequate to obtain the full performance advantage
of Brooktree's family of mixed signal products. The
coexistence of digital and analog circuitry requires
special layout techniques to assure reliable operation
and preserve analog signal fidelity.

Figure I b shows a split ground plane which reduces
the digital ground return currents from mixing with
the analog ground currents. This technique is
recommended by Brooktree to achieve optimum
isolation of the analog circuitry. The two sections
should connect at the edge connector which is the
point of lowest impedance.

The goal for a well designed, ltigh-speed mixed-signal
PCB layout is to reduce the noise generation sources
and isolate the analog circuitry from these sources.
This application note will show PC-VGA layout as an
example, but these techniques apply to other
high-speed designs.

Figure Ic is a method used when isolation is needed
but the analog components must be placed away from
the edge connector. Analog ground current flows out
of the isolated analog area and over a portion of the
digital ground plane on its way to the edge connector.
This localization method reduces the intermixing of
digital and analog currents but does not completely
isolate them.

Power Supply Planes

Power plane layout techniques are illustrated in Figure
2. Figure 2a shows a solid power plane which can be
used when minimal power switching noise exists.

A well designed power distribution network is critical
to eliminating logic switching noise that could be
coupled into the analog outputs. Since the power
system is common to all circuitry, noise reduction and
isolation techniques must be used. Common isolation
techniques include separate ground and power planes
with each plane partitioning the analog and digital
circuitry into separate areas.

VIDEO

In mixed signal designs, a multilayered board can use
separate planes as sltields to isolate the analog traces
from the noise sources. Noise sources come from
power supply and digital switching.
The
recommended technique to isolate digital switching
noise is to separate the digital and analog signal
planes with the ground plane. This also provides a
clean analog signal return path from the video output
connector to the chassis ground at the edge connector
that preserves signal fidelity.

a) SOUDGROUND

VIDEO

b) SPLIT

Figure 1a shows a solid ground plane. This technique
is usually satisfactory when the DAC can be placed
close to the edge connector. This prevents excessive
digital currents from inducing noise aberrations in the
analog ground.

VIDEO

c) LOCAUZED

Figure 1.
Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580 • (800) VIDEO IC
TLX: 383 596· FAX: (619) 452-1249

2 - 49

Ground Planes,

•

AN-II
Power Supply Decoupling

In Figure 2b. the digital plane feeds the analog plane
through a ferrite bead. This technique is recommended
to isolate the analog section from digital switching
noise of the clocks and memory management
circuitry. The ferrite bead isolates the digital
switching noise from the analog circuitry. The
analog circuitry noise is also isolated from the power
supply. The blocking results in a potential difference
across the bead when one plane contains large
amounts of high frequency current. Typical values are
zero to 20 mV for a 25 to 80 MHz frequency range. Do
not use an inductor in place of a ferrite bead. Inductors
may form a tuned circuit with the RAMDAC and its
package parasitic. This can result in a resonance at
operating frequencies causing oscillations on the
video output. The recommended ferrite bead (Fair-Rite
2743001111) in Brooktree's databook looks similar
to a low pass filter with 71 ohms impedance at 100

The switching of logic gates and clock drivers that
charge and discharge distributed capacitive loads are
the major source of switching noise that is coupled
into the supply system. The proper technique is to
adequately decouple the high current driver devices
such as buffers or clock generators. The magnitude of
the coupling levels can be determined with Equation
1.
I =CLdV Idt where I =dQ/dtandQ=CV

Equation 1.
A typical clock transition rise time of 2 ns with an
output transition of 4v will require a peak transient
current of 200 rnA from the supply bus. Assume a
maximum supply bus drop of 100 mV can be tolerated.
Solving Equation 1 for the coupling capacitor yields a
value of 0.004 ufo Decoupling capacitors should be
placed on all high current high speed devices and
placed as close as possible to the power and ground
pins.

MHz.
Figure 2c shows an analog plane in the shape of a star
or tree. This type of supply plane reduces plane to
plane coupling. Use this type of analog supply when
the analog plane must overlap digital ground or signal
paths. The same is true for digital supply overlapping
analog ground or signals. Plane to plane overlap
forms a capacitance that acts as a bypass for high
frequency signals. The shape of the plane is not as
important as reducing the capacitance in the overlap
areas with cutouts. The fmal result may consist of
solid plane and cutout areas with traces. Whichever
method is used to split the digital and analog area, the
desired result is the same: digital noise is isolated
from the analog circuitry.

Transmission Lines
All signal traces should be evaluated to assure adequate
termination exists to prevent unwanted signal
reflections that are manifested as "ringing". A
knowledge of the mechanism that causes signal
overshoot and undershoot is required to assure
prevention. This general model applies to most
signal line cases. Consider the driver in Figure 3 at
point A with an output impedance of Ro is driving a
line with a characteristic impedance of Z00 The line
length has a delay time Tp that is the time required for
the signal at point A to propagate to point B. The
load at point B has an impedance of RL.
Two cases will be considered for this example. In one
case the signal edge rate (rise or fall time) is fast
compared to the line delay time Tp. The signal arrives
at point B after time Tp and electrically has an
impedance change from the line Zo to the load RL.

~ i~
-v-nlr)

======r-i ~

----,~'r$_I-rv-

0) STAR OR TREB

Figure 2. Power Planes.

Figure 3. Signal Transmission Line.

2 - 50

AN-II
This impedance change can be expressed as a
reflection coefficient (p) at the load point B, and is a
function of the line impedance and the load impedance:

micros trip line with a dielectric constant of fiberglass
epoxy (Er = 4.7) would have a propagation delay time
of approximately 1.75 ns/ft.
T p = 1.017

..J (0.475 Er + 0.67) ns/ft.

Equation 4.

Equation 2.
Assuming that RL equals Zo and the load impedance
matches the line impedance, the reflection coefficient
at point B is equal to zero. This condition assures that
no portion of the signal is reflected and that the line is
matched or terminated. For values of RL close to Zo
the reflections at point B can be made very small.

If the signal rise time T r is much shorter than the line
delay time T p' and the load reflection coefficient is
non-zero, reflections will appear as overshoot and
undershoot. The solution is to shorten the line length
such that the delay time T d will allow all the reflected
energy to occur within the signal rise time at point A.

Assume that RL does not equal Zo and a portion of the
signal energy is reflected back to the source point A.
Then at time two T d, the reflected signal energy
(determined by Equation 2) arrives al point A. The
electrical impedance is again a ratio of the line
impedance, Zo, and the driver output impedance, Ro.
This impedance change can be expressed as a
reflection coefficient (p) at the source point A that is a
function of the line impedance and the driver output
impedance:

Some general guidelines can be used to determine when
interconnections are short enough to be treated as
lumped. Analog signals are much more sensitive to
transmission line effects since preserving signal
fidelity and reducing distortion is the goal. For analog
signals, a rise time to delay time ratio of 8: 1 or greater
is necessary before transmission line effects need to be
considered. Digital signals are much less sensitive,
ratios of 4: 1 for threshold sensitive signals such as
clocks can be used. Otherwise a 2:1 ralio will give an
acceptable signal undershoot. The following table
relates the logic family type edge rates to the maximum
lumped line length that reflections can be tolerated
without termination.

Equation 3.
Logic
Family

This signal is then reflected from the source to the load
and will continue reflections until the coefficients
ratio and line resistance slowly degrade the signal
strength. This case illustrates that a mismatch or
unterminated line leads to overshoot and undershoot of
the signal, commonly known as "ringing".

TIL
AS
F
S
FACI'
ALS

Signal Rise Time
The signal rise time must be evaluated with respect to
the line length and propagation line delay time (Tp) to
determine if the transmission line effects can be
ignored. The propagation delay time is a function of
several parameters that are unique for media such as
cables, circuit-board trace type, and backplane
connections. For PCB traces, the line width, spacing,
thickness and dielectric constant all affect the delay
time. Equation 4 can be used to calculate the line
propagation delay time for a micros trip trace. A

Trise (ns)

Line length(in)

4
1
2
1.6
3
6

9
2.3
5.5
4
6.5
14

Notes: Trise is defined from 10% to 90% of
amplitude. The line length assumes a 4: 1 ratio
between Tr and Tp.

Table 1.

2 - 51

Unterminated Line Lengths
vs. Logic Types.

•

AN-II
Series Terminated Lines

illustrates an electrical model of two signal traces that
are closely coupled.

Overshoot and "ringing" can be controlled by using
series dampening or· series termination techniques.
Series dampening is done by placing a small resistor
(10 - 750) in series with the line (see Figure 4).

Figure 6. Crosstalk Coupling Model.
The signal on line CD is capacitively coupled into
line AB through the mutual capacitance, Cm, and the
mutual inductance, Lm.
Equation 5 gives an
approximation of the crosstalk coupled using the
ratio of the line CD load capacitance to the line AC
mutoal capacitance.

Figure 4. Series Terminated Line.
The resistor sllould be placed close to the driver output
impedance and the value chosen such that the total
impedance of Ro and Rs is equal to the line impedance
Zoo The reflection coefficient at point C is large since
there is no termination, but the reflection coefficient
at ·point B is zero since Zo = Ro + Rs. Advantages of
series termination are less power consumption and
only one resistor is required. Disadvantages are the
slower propagation delay of the signal with slower
edge rates and a resistance load that could limit fan out
due to current limiting.

dVc= dVs (CM/(CM+CL»

Equation S.
For a voltage transition (Vs) of 4V, a load capacitance
(CL> of 100pf and a mutual coupling capacitance (CM)
of Ipf, the approximate coupled voltage due to the
capacitive effects would be 40 mY. Clock lines
should be routed at a 90 degree angle to signal lines to
prevent PCB coupling through these parasitic
capacitances and dynamic ground currents.

Parallel Terminated Lines
Parallel termination is two resistors placed at the load
that form an equivalent Thevenin circuit. The
Thevenin resistance is equal to the line impedance, Zo,
and the Thevenin voltage is approximately equal to
the load threshold voltage. Figure 5 shows a parallel
terminated line. The reflection coefficient at point B
is zero since R1 in parallel with R2 is equal to the line
impedance, Zo. Advantages of parallel termination are
the signal edge rates are not slowed as in the series
termination. Sharper signal edges are achieved at the
expense of increased power consumption.

Clock and Data Feedthrough
Feedthrough noise is any noise that is coupled
through the RAMDAC into the analog output and
appears as visible aberrations on the screen. The
most common sources of this type of noise occur at
the pixel data and/or clock inputs. Improper
termination of these input signal lines can result in
"ringing" noise in the analog output.
Clock feed through is a repetitive noise that usually is
caused by fast edge rates. Parallel termination can
limit the clock excursion about the threshold and
reduce the edge rate. Series termination can also be
used at the clock source to reduce rise times that cause
undershoot.

Figure

Parallel Terminated Line.

Data feedthrough is a data dependent phenomena that
usually occurs d\lting simultaneous switching of data
inputs. These data inputsusu.ally are driven by high
speed bipolar logic that often places extreme
switching current demand on. the RAMDAC input
buffers. To reduce the ·effects of data feedthrough, the
power and ground should be adequately bypassed and a
robust ground return path to chassis ground provided.

Signal Crosstalk
When signal traces are routed in close parallel,
capacitive and inductive coupling between the two
lines exists. The amount of signal amplitUde that is
coupled is determined by several parameters. Figure 6

2 - 52

AN-II
Series termination of the pixel inputs is also a
solution. Another method to slow down the edge
speed without series terminating every pixel input
line is to increase the characteristic impedance of the
stripline to the pixel inputs. This has the effect of
rounding edges and attenuating high frequency
components. If high frequency components cannot
be eliminated at the device inputs, sometimes they
can be eliminated at the outputs with band limiting
techniques.

determined by the pulse width while the edge rate
determines the second comer frequency, F2. The range
between F; and F2 is bounded by an envelope of - 20
dB per decade slope. Beyond F2 the magnitude of the
signal power decreases by - 40 dB per decade. For the
case of a single pulse, the frequency domain looks the
same but the vertical units change from volts for a
repetitive pulse, to volt-seconds for a single pulse. In
Figure 7, the fundamental frequency, FO, lies between
FI and F2.
The integer multiples of FO are the
harmonics reducing in magnitude, but usually
contributing more to EMI.

The CRT is a band limited analog receiver which will
reject the high frequency harmonics on the analog
output. Since the CRT bandwidth increases with
increasing screen resolution, techniques must be
employed to control the high-frequency feedthrough
noise. Methods for controlling feedthrough are to
add passive or active fIlters to the analog outputs.

The noise in a system not only affects the system and
peripherals connected to it, but it can also be
transmitted in the form of electromagnetic
interference (EMI). Many of the techniques for
reducing noise sources will also directly apply to
reducing EM!.

(A)

EMf
So far this application note has discussed how to
separate digital and analog noise and how to reduce
digital noise. In today's office or home with many
electronic devices, EMI must be below specified
limits so neighboring electronic devices will not be
disturbed. The FCC has set limits such as class B
emissive radiation standards which apply to
equipment manufactured for home or office use.
CISPR/VDE and MIL-STD 461 are other
specifications which define EMI standards.

FO= liT = FUNDAMENTAL FREQUENCY
PI =l/(!>;·Tw)
F2=1/(!>;.TR)
(B)

Figure 7.
Time Domain and Corner Frequency

Any circuit component that transmits a signal on any
path other than the intended route is considered a
source of EMI. EMI sources come from active or
passive components, signal
traces, or
interconnections.

Reducing EMf
Various practices incorporated into the design process
will provide a greater possibility of an acceptable EMI
profile in the finished product. This saves the trouble
of an EMI fix which can be more expensive, time
consuming, and less effective than implementing EMI
procedures from the beginning of a design.

EMI emissions are dependent on frequency because
the signal wavelengths decrease with respect to the
size of potential radiating elements on the PCB. This
will also increase the radiated EMI power. To get an
idea of how higher order harmonics increase with
edge rates, consider Figure 7.

As mentioned in the previous section, higher
frequencies result in greater radiated power. This is
because the ratio of wavelength to antenna length
determines radiated power for simple dipoles. Other
types of antennas and radiation patterns are beyond the
scope of this application note and will not be

The high end of the frequency domain is determined
by the signal edge rate. Slowing down edge rates will
not only reduce circuit noise, it will reduce the
radiated power. The first comer frequency, FI, is

2 - 53

•

AN·ll
Containing EMI

considered.
By reducing the length of
interconnections, the wavelength to antenna ratio is
changed and radiated power is reduced. For this reason,
keep package leads as short as possible. For the same
reason, axial lead capacitors are not as good as radial.
Any conductive element on the board is a potential
antenna.

Containing the area of EMI requires absorbing or
reflecting the radiation already emitted and
propagating. Absorbing radiation increases with
thickness, conductivity, permeability and frequency.
Reflection increases with surface conductivity and
wave impedance.

Bypass capacitors, mentioned earlier for noise
reduction, are an effective method of reducing EMI.
The purpose of bypass capacitors is to shunt high
frequencies to ground. Liberal use should be made of
bypass capacitors in any EMI sensitive design.

Two ways of containing radiation are EMI fences and
boxes. EMI fences surround the radiating components
and are usually anchored to the ground plane. For cards
plugging side by side into a backplane, this
effectively creates a box if all cards have full power
and ground planes. EMI fences are used where the
frequency is not high enough to pass through the
holes in the fence. The fence holes should be less than
half the wavelength of the frequency to be blocked.
The smaller the hole, the better the block. The circuit
enclosure can also be covered with conducting material
to create an absorbing, reflecting shield. This is an
expensive alternative and should be used as a last
resort. Cables and connectors leaving the box must
also be considered as possible sources of EM!.

Signal traces also act as antennas. Long, thin traces
are more resistive than wide traces, and thin traces
become inductive at higher frequencies.
Table 2
shows the impedance of several PCB traces.
At higher frequencies, trace impedance increases.
Above about 10 kHz the impedance becomes mainly
reactive. This affects EMI in two ways. Increased
impedance tends to induce voltage differentials in
signal traces. A potential difference may raise a
particular point close to a threshold, allowing coupled
EMI from another portion of the circuit to cause
misoperation. Another effect of a long thin trace is
inductive impedance at higher frequencies, acting
increasingly like an antenna.

Frequency
5KHz
50KHz
500KHz
5 MHz
50 MHz

w=1
1=30
1=3
0.0170
0.0190
0.0870
0.8610
8.61Q

Table 2.

0.1720
0.2150
1.30
12.90
1290

1=3

In the case of mixed signal graphics PCB boards,
consider the video connector and cable. The line from
the DAC output to monitor input is a source of
possible EMI radiation. If this link acts like an
antenna rather than a transmission line, EMI will
result. An important consideration is impedance
matching. Match the impedances on the end of the
transmission line to reduce reflections that could cause
standing waves. Eliminating standing waves reduces
the transmission line's ability to act like an antenna.

w=lO
1=30

0.0010
0.0040
0.0430
0.4380
4.380

0.0190
0.0880
1.21Q
8.660
86.60

PCB Trace Impedances.

Notes: Widths and Lengths are in mm. Trace thickness
is 0.03 mm. Dielectric constant is for epoxy fiberglass.

2 - 54

AN-11
References

Figure 8 shows a common RAMDAC output system.
The cable should be coaxial so that all magnetic fields
cancel. The outer conducting sheath should be
connected to the outer conducting shell of the
connector. The outer conducting shell should be
connected to the analog ground plane of the circuit
card. Some difficulties may arise if the system
enclosure is isolated from circuit ground. This can be
handled by using connectors that will be electrically
isolated from the enclosure when mounted.

Brooktree Corporation
• Application Note 1 - Getting the Best Performance
from Video Digital-to-Analog Convertors
• Application Note 2 - VIDEODAC Essentials
• Application Note 6 - Troubleshooting Your
Brooktree CMOS VlDEODAC or RAMDAC
• Motorola MECL System design handbook
• Signetics HCMOS Designers Guide
• "Designer's Guide to Transmission Lines and
Interconnections" - (EDN, 6/23/88)

75
Zo=75

• White, Donald R.I., "EMI Control in the Design of
Printed Circuit Boards and Backplanes",
Interference Control Technologies, Inc., 1982.

Figure 8. Common Output System.

• Mardiguian, Michel, "Interference Control in
Computers and Microprocessor-Based
Equipment", Don White Consultants, Inc., 1984.

Conclusion

• White, Donald, R.I., "A Handbook Series on
Electromagnetic Interference and Compatibility",
Interference Control Technologies, Inc., 1973.

Mixed signal graphics boards require special layout
consideration as dot clocks increase with higher screen
resolutions. The added picture sophistication reflects
the need for added board sophistication including
increased number of layers, use of strip lines on the
board, and coax off the board. One must design with
EMI reduction techniques from the beginning even
though the expense might be higher and there may be a
learning curve. In the long run there is less risk and
frustration, and the product will likely get to market
faster.

2 - 55

•

AN-II

2 - 56

APPLICATION

NOT E

Analog Signal Interface Techniques
The interconnection and transmlSSlOn of high
bandwidth analog video requires special consideration
to assure preservation of the signal fidelity and
compliance with EMI regulations. The high frequency
bandwidth of computer generated graphics must be
adapted to the limited bandwidth of a display or
routing device without severely compromising the
crispness of a digitally derived image.

pulse aberration (overshoot and reflections) unless
cable properties (characteristic impedance and
shielding) are controlled to minimize standing waves
and radiation (which government agencies
discourage in commercial products). While coaxial
cable can deliver 90 - 95% of incident low frequency
power to a destination several hundred feet away, it is
still a dispersive medium which can significantly
attenuate high frequency energy. We shall examine
how the qUality of the coaxial cable and some simple
buffer circuits can affect the quality of the computer
graphic display.

This Application Note will discuss several topics
which relate to the preservation of video signal
fidelity and will state a specific case to outline the
advantages and disadvantages of each method. The
following topics will be discussed:

Coaxial cables and fittings are commonly supplied in
characteristic impedances of 50 or 75 ohms, with 75
ohms being preferred for low loss and low cost
applications of broadband consumer video systems.

The frequency limitations of coaxial cable
transmission line media.
Correct techniques and use of analog filtering for
noise and emission suppression.
Common monitor synchronization problems when
interfacing with various video signal sync
formats.
Considerations for implementing broadband
analog video mUltiplexing or routing.

The electrical attenuation characteristics of a coaxial
cable for a low frequency signal are a function of the
center conductor resistance, which can be minimized
with special conductive plating. The high frequency
loss is affected by the dielectric loss (which
increases linearly with frequency) and "skin effect"
losses according with Equation 1.

The scope of applications will range from PC-VGA
signals (35 MHz - 50 MHz) to the Megapixel
Workstation class video signals (100 MHz - 200
MHz). The techniques outlined can be scaled down to
traditional NTSC-type video or scaled up to
super-display (>200 MHz) signal applications.

a = (0.434/ Zo)(l/ d + I /0) ,I freq
Note: a = Attenuation (db/100ft)

Equation 1.
The coaxial dimension d (outer diameter of the center
conductor) and dimension D (inner diameter of the
sheath) are maintained at a ratio of about 3.6 for a 75
ohm impedance cable. For smaller values of D in
Equation I, we see that a smaller diameter cable will
have a greater high frequency attenuation. This
frequency dependent characteristic transforms in the
time (or pulse) domain to Equation 2.

How far can it be coaxed?
For transmission distances exceeding the
quarter-wavelength of the highest frequency
component of the signal, a controlled· impedance coax
medium is required to preserve signal fidelity at the
destination (usually a display or distribution
amplifier). A typical 30 MHz bandwidth VGA display
monitor with a one meter cable (4 - 6 ns propagation
time vs. 9 ns quarter wavelength) is vulnerable to

Vo=Vi(l-erf(K xL/4R,It)
Note: Propagation delay component removed

Equation 2.
Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580 • (800) VIDEO IC
TLX: 383 596 • FAX: (619) 452-1249

2 - 57

•

AN-12

An analysis of the complementary error function (erf)
will show a rounded contour such that the response
time to 90% of full amplitude is 28.8 times the
response time to 50% or mesial point. This is why
cables are sometimes rated for 50% rise time, which
can be extrapolated to 90% rise time by the 28.8
multiplier. From Equation 2 it can be seen that rise
time degrades as the square of the cable length (L),
rather than the root-sum-squares model that would·
apply for a cascade of elements with Gaussian pulse
characteristics (e.g. single pole filters, amplifiers
and CRT phosphors). This means that fatter cables
make for sharper pulses over longer distances. The
accuracy of the pulse settling is limited by the high
frequency impedance match (5 - 10% if tested for
return loss) which also affects the overlunder shoot of
the dampened pulse.

at 25 MHz to a 2 dB loss at 100 MHz. Applying the
acceptable criteria of 2 dB cable loss at a 100 MSPS
pixel clock frequency, one arrives at acceptable
lengths of cable for the various generic types listed in
Table 1. Other bandwidth requirements can be
determined by scaling according to the square root of
the pixel frequency.
Some cable manufacturers may offer special versions
with better loss ratings, but they should be tested for
impedance match better than 20% (or return loss
exceeding 20 dB). The use of smaller 50 ohm coax
(such as RGSS or RGl74) runs the risk of 20% of the
signal bouncing off the 75 ohm monitor, producing
ghosts (see Equation 3) and potentially greater
radiation due to standing waves.

While there are no prev ailing standards for
computer graphic transmission systems (such as
RS250B for 5 MHz RS170A video), one can arrive at a
criteria for acceptable frequency dependent attenuation
by reasoning that the cable should not compound the
zero-order-hold (also referred to as sinx/x roll-off)
attenuation at the Nyquist frequency (half the sample
rate) to where the monitor's gamma-dependent
phosphor intensity is reduced more than 10%.
RS2S0B tolerates 1 dB roll-off in the luminance
bandwidth of 3 MHz corresponding to 320 lines of
horizontal resolution (after aspect correction), which
extrapolates to 48 MHz for a 1280 line,
non-interlaced display requiring at least a 96 MSPS
DAC clock (more typically 107 MSPS due to monitor
retrace time requirements). Typical display monitors
in this class have small signal (<100 mY) bandwidth
of 100 MHz and slew-rate-limited 10%/90% rise times
of 5 ns. The energy delivered to the screen phosphor
at the 50 MHz Nyquist frequency is less than one
fourth that delivered at much lower frequencies
(assuming the monitor roll-off rejects higher-order
harmonics). The convolution of a 5 ns monitor rise
time with the sinx/x function produces a half-power
frequency of about 25 MHz, so by the
square-root-of-frequency cable attenuation
characteristic one can relate a 10% (1 dB) attenuation
Cable Type
RG179
RGS9
RG6
RGll

Table 1.

Diameter

@l00MHz

-2 dB Reach

0.100"
0.242"
0.275"
0.405"

9 dBllOO'
3 dBl100'
2 dB1100'
1.5 dB1100'

22 feet
67 feet
100 feet
133 feet

Cable type

liS.

Equation 3.

Reflected Voltage.

When considering different transmission media for
very long runs (such as fiber-optics), a similar
analysis can be applied assuming the transducers
have Gaussian characteristics which can be convolved
approximately by root-sum-squaring the individual
rise-times and limiting power loss to 10% at a quarter
of the pixel clock frequency. For non-Gaussian
components or stronger gamma effects, the
calculation of delivered pulse power would be
appropriate using analytical representation or
non-linear simulation tools. Note that systems with
excess dynamic range (such as 1.4 V compliance with
an MSB to spare) can compensate for all these
frequency dependent effects given the higher order
computational power to predict intensity frequency
and pre-compensate the data to the DAC.

Preserving the Fidelity
Techniques to compensate for coax cable attenuations
include signal compensation by pre-emphasizing the
pulses with peaking buffers before transmission.
While precise compensation for cable attenuation is
best implemented in passive RLC networks,
amplifiers with up to 6 dB of gain peaking at the high
frequency limit (.3SI is practical)
can approximately compensate for cable losses. Such
peaking produces overshoot on the analog edges but
also serves to compensate for the sin xIx (zero-order
hold function) attenuation effect for spectral
components near the Nyquist frequency limit (half the
sample clock rate).

loss I length

2 - 58

AN-12

One simplistic implementation of a peaking buffer
(Figure 1.) for a CMOS palette DAC is just a common
base PNP stage between the DAC output and the load
resistor. The drawback of this circuit is that the Hfe
linearity of the MRF536 dominates the overall
integral linearity, with the net integral linearity
being 1 - 3%. Fortunately the non-linearity is hidden
in the black region and is alleviated by the 7.5 IRE
set-up pedestal bias. The DAC output node may be
outside its rated compliance range (usually 1.2 - 1.5
V) without limiting the overall linearity. The riselfall
times of 1.0 - 1.5 ns are slightly better than that of
commercial boxed distribution amplifiers with
peaking (such as the INUNE 2085) which exhibit
about 3 ns transition times with a minimum gain of 2
at 150 MHz. The linearity and pulse fidelity
parameters must be convolved with the monitor
amplifier characteristics (which may include some
gamma correction) to arrive at an overall channel
fidelity figure. If linearity better than 1% is required,
then consider using monolithic or hybrid operational
amplifiers from Comlinear, National, Harris
Semiconductor, or Burr-Brown which usually require
dual supplies, and have full-power (>1 Vpp) bandwidth
at least half the pixel frequency (to preserve
information in the Nyquist Bandwidth). Peaking for
cable compensation is achieved by introducing a pole
in the feedback network. This must be limited and
checked to assure stability margin with possible
mis-termination, such as cable faults or capacitive
monitor loading.

1.2V

Figure 1.

200 feet of R06 (where 20 - 40pF of emitter-base
capacitance reduces the edge speed 1.0 - 2 ns) as
shown in Figure 4.

Filter with Care
Where cables can be considered constant group delay
filters, with low shape factors tu pass a wide spectrum
of frequencies, the display monitor amplifier
generally constitutes a multi-pole pulse filter, with a
slew rate limited rise time for full scale transitions and
a slightly higher 3 dB bandwidth for small (<10%)
signals. Constant group delay filters (or Bessel) are
desirable for passing pulses to preserve reasonable
overshoot with their large harmonic content.
However, they have shape factors which rolloff
gradually with frequency and are less effective at
reducing undesirable high frequency noise. In raster
graphics applications, noise arises from the digital
signals getting on the analog channel to produce data
related foreshadows (generally within 10 pixels of
sharp picture transitions), bleed-through with
overlaid images, or signals beyond the monitor's
bandwidth which aren't visible yet radiate under FCC
restriction. Frequency selective pulse filtering can be
used to limit the video transmitted to the important
spectral content, while maintaining perceived
horizontal resolution and picture intensity within
government agency restrictions.
Figure 5 depicts four different filter pulse responses
using simple pi filter topologies, as driven by a 1.5
ns palette edge. The first is a 3-pole Bessel filter
using discrete LC components optimized for 100
MHz/ 3 dB attenuation (about 12 dB @ 200 MHz).
which exhibits a 3.8 ns rise time with about 10%
peak-peak ring. The other three responses correspond
to ferrite bead filters with successively greater
impedance (60 - 100 ohms) at 100 MHz, and
corresponding 8 - 16 ns rise times (the slowest
representing a monolithic chip with distributed LC
characteristics). While any of the ferrite beads would
provide acceptable fidelity on a 25 MSPS VOA
graphics channel, even the smallest bead would induce
significant intensity dimming on a 65 MSPS pulse.
The discrete 3 pole Bessel filter shown in Figure 6
(115 nH followed by 47 pF for 100 MHz), passes the
full power in the Nyquist spectrum (50 MHz) while
reducing by half any energy at the hannonics of the
palette's TTL drivers above the sample clock
frequency. By reducing the pulse edge rate from 1.5 to
3.8 ns, the Bessel filter further diminishes the effect
of reflections off the monitor since their input
impedance is largely reactive above the rated
bandwidth. These reflections can produce "ghosts"
whose after-shadow is dependent on the cable length.

Peaking Buffer.

The effects of cable attenuation are illustrated in
Figure 2. Staggered traces depict the 1.2 ns rise time
from a Bt458 being rounded to 1.5 ns after 60 feet of
R06 cable; to 8 ns after 100 feet; and to 13 ns after
200 feet. The DC component is down 15% after 200
feet, which is the nominal amplitude tolerance of
RS330!343 video. The INLINE 2085 ROB amplifier
can restore the pulse rise time to 3.7 ns (OK for 100
MSPS) after 70 feet of R06 (Figure 3). The common
base stage delivers sub-four nanosecond edges after

2 - 59

•

Broddree®

AN-12

Figure 2.

Figure 3.

Cable Attenuation

Sub-four Nanosecond Edges

2 - 60

AN-12

Figure 4.

Rise Time Restoration.

Figure 5.

Filter Pulse Response.

2 - 61

•

AN-12

35 kHz, prescribes four possible combinations of H/V
sync polarities depending upon the screen display
mode (EGAlTextlGfx/HiRes).
For maximum
compatibility with VGA monitors and self-test
conditions, there should be no composite sync or
offsets on the analog channels since the monitors
will give precedence to the TTL sync signals when
present. With VGA controllers, where all the raster
timing parameters and signal polarities are
programmed, care must be taken to compensate in
software for time skews between the buffered sync
channels and the pipelined palette channels, which
can affect horizontal screen placement by several
pixels. When interfacing to monitors prone to give
precedence to composite sync information on the
analog channels, it may be best to inhibit any
separate sync channel signals. It is furthermore
prudent to maintain wide back porches (Blank period
after Sync) in the horizontal retrace since most
monitors clamp their amplifiers in that interval.

Keeping the Video in Sync
Modern multi-raster monitors can be tolerant of
diverse scanning frequencies yet be sensitive to
parameters such as separate sync channels, sync
polarities, and some of the more elaborate analog
synchronization signals employed in HDTV
equipment. Normal RS343A analog video prescribes
composite sync on the green channel, which is
usually generated by the palette DAC with the same
propagation time and level accuracy as the active
pixel video. The display device is usually internally
AC coupled and must detect the synchronization pulse
to correctly perform internal DC restoration by
clamping its amplifiers to a specific level when the
video waveform is at a prescribed level in the retrace
interval (usually the back porch interval following
the sync tip). DACs which generate composite sync
on the Red, Green, and Blue channels (to serve
multiple displays or to provide channel gain reference
levels for AGC processing) can confuse some
monitors which get separate sync timing, giving rise
to color imbalance or poor black level stability.
Sync signal polarities which vary with the generator's
display format (such as VGA) usually affect the
display size and degree of overscan, but can create
havoc with monitor requirements for clean porches for
clamping. The following discussion will cover
situations where the sync generated by the palette
DAC must work in concert with other channels to
achieve stable raster display.

The newer HDTV production formats rely on more
elaborate composite synchronization signals known
as Tri-Level Sync. In this scheme the sync detector
threshold is dynamically set near the Blank level,
such that sync pulses swing +/-300 mV around the
Blank level. DACs tailored for RS343 composite
sync do not have explicit input controls to generate
sync levels above Blank, so adapting these DACs to
the SMPTE 240M standard requires mapping sync into
the data range or current summing a switched 8 rnA
sync source into the 37.5 ohm load. With a palette
DAC, one CLUT location can be defined as the
positive-going sync pulse, but for conventional
DACs the circuit shown in Figure 7 is a solution. The
Sync Hi control should be registered or pipelined to
match the DAC's internal register propagation time
within IOns to reduce glitches near the sync trigger
level. This adds about 12 rnA to the DAC supply
current, of which 8 rnA is switched between ground
and the video termination. The sync rise time is less
than 50 ns or four clock cycles (75 MSPS).

While traditional RS170/343 video camera formats
are quite specific about horizontal and vertical
synchronization pulse polarity, due in part to the
delicacy of interlaced timing, the newer
non-interlaced computer formats take advantage of
separate synchronization channels with independent
polarities to tailor the display presentation to a
multitude of screen resolutions. The mM VGN8514
standard, while maintaining a raster frequency of 31 -

115nH

Figure 6.

100 MHz Bessel FUter.

2 - 62

AN-12

Sharing the Medium

combine high speed CMOS DAC outputs to achieve
greater resolution, but the DAC's compliance range
must accommodate the extra diode drop as well as any
offset current in the shared terminator. Combining
multiple DACs usually entails significant switching
glitches which should be counteracted by drop-shadow
masking (software) or precise clock timing
compensation. Note also that varying pixel pipeline
delays through the palette(s) may produce horizontal
position offsets, where monitor sync signals are
provided through separate digital channels.

It is common to multiplex other analog signals into
the video channel as an analog overlay technique or
where mUltiple palettes must share the same monitor.
Analog overlays require mUltiplexing at the pixel
clock rate, while analog sharing is done during
graphic mode switching (like from VGA resolution to
very high resolution). The two situations call for
different component technologies whose cost is
strongly dependent on the mUltiplexing rate, and
driving low impedance transmission lines with
minimal loss yet full channel bandwidth. The nature
of current output DACs as fast current switches makes
them easy to tie outputs together with the caveat that
the resultant higher parasitic capacitance can produce
some aberrations on fast pulse edges.

Solid-state multiplexors fabricated in CMOS or DMOS
technologies generally have an RDS-Coff time
constant of about 200 picoseconds, which for 75 ohm
applications connotes 3 dB of insertion loss with
worse than 60 dB isolation above 10 MHz. A
Siliconix Si2400 (representative of DMOS FETs of
requisite size) switches in less than IO ns but requires
negative channel bias. The best power FET or
optoFet will have 12 - 30 ohms of on-resistance with
8 - 20 pF of associated drain capacitance. When
placed in series with a CMOS DAC output, this will
satisfy compliance requirements but will effectively
double the DAC's output capacitance and transition
times.

Situations arise where it may be cost effective to use a
relatively slower palette DAC for lower resolution
modes, with common connections to a high
performance palette sharing a multi-frequency
monitor. The inactive DAC can be virtually shut off
by asserting SynclBlank inputs, but the slower DAC
presents an extra 15 - 20 pF of parasitic capacitance
load which can degrade the rise time of the high
performance palette when it is active. Placing low
barrier Schottky diodes (such as HP lN6263) in series
with the DAC's slower outputs (see Figure 8), isolates
its loading when it is inactive. The one disadvantage
is that its fall time degrades to about 4 ns (useable to
about 65 MSPS). This approach can be used to

GaAs switches and diode bridges are inherently faster
at greater expense and with special interface
considerations. The Mini-Circuits KSW series of
GaAs switches are rated for 1 dB of 50 ohm insertion
loss with 50 dB of isolation at 200 MHz and less than

vcc-

DISABLE'"
SYNC'" -::Lr--:::Ll:-BLANK'"

BT471

lN6263

SYNCHHI
(REGISTERED)

( \ __ .seamY

ILL V __ ~ +300mV
- ...... '" OmV

SYNUI'"

BT458

75
SYNC"
DISABLE'"

Figure 7.

Tri-level Sync

Figure 8.

2 - 63

Sync Solution

•

AN-12

5 ns switching driven by 0/-8 V controls. In the diode
arena, the HP5918/38/58 series and Metelics
MSS-30/40/50/60 series of beam-lead devices must be
driven by fast complimentary current sources/sinks to
achieve fast switching, but they have a channel time
constant of under 10 picoseconds. Special ratings for
diode on resistance at >10 mA may be necessary for
direct coax interface, or a modified bridge which
substitutes complimentary emitter followers for the
output diode pair can provide high-current voltage
drive in much the same fashion as LH002-type buffers
(from National, Harris, Precision Monolithics, and
Elantec). The Harris/RCA CA3019 diode array is an
inexpensive alternative, useable for signals up to 100
MHz with 2.6 dB loss. (See references)

Note the DAC output must swing more positive than
in typical VGA applications, to overcome the 25%
signal loss through the buffer. Transition times will
be slowed (10 ns) slightly and any circuitry which
detects output levels must take the diode offset into
account.

!REF

Special Situations

700mVPP

SosmA'
75

Particular palette DACs may have unique
characteristics which deserve special attention. For
instance, DACs with compliance ranges substantially
greater than the required video amplitude can readily
interface to inexpensive distribution amplifiers to
drive multiple monitors simultaneously. Other DACs
may have RS 170A-type Blank-Black setup pedestals
which create problems for PAL or Component Analog
Video equipment.
Some simple examples will
illustrate how subtle modification to the DAC signal
can extend its utility without severely compromising
its fidelity.

Figure 9. VGA Distribution Amplifier.

DACs with RS 170/343A Blank-Black setup levels
generally cannot drive PAL or CAV video equipment
which require Black at Blank level. For these DACs
the easiest solution is to mask the setup current into
the sync tip (a 7% tip boost, still within specs) by
placing a latch with a Clear function (such as 74273)
in the data path. By asserting Blank via the latches
Clear pin, rather than through the DAC, and by tying
the DAC's Blank* and Sync* inputs together (asserted
by composite Sync), the 7.5 IRE setup pedestal will
appear on the Sync tip rather than in the grey scale
range.

In limited bandwidth (e.g. VGA resolution)
applications where the cable propagation time
(usually 1.5 ns/foot) is less than a quarter of the pixel
interval and about equal to the DAC rise time, several
monitors can be driven by a simple emitter-follower
distribution amplifier which uses just +5 V and modest
back-termination in each feed to maintain load
isolation. Figure 9 illustrates how the 1.5 V
compliance range of the Bt478 palette is enough to
accommodate the 600 m V emitter-base drop through a
2N2222 buffer with 22 ohm resistor in each output.
The 25 ohm source impedance represents a better
standing wave ratio (2.25) than most VGA boards,
which mimic the IBM 150 ohm source termination
(3: 1 VSWR). Linearity of the buffer is improved with
higher transistor beta, the use of Setup and Sync
pedestals, or multiple loads (up to the thermal
limitations of the transistor) which reduce the
emitter-base source impedance variation with current.

References
Motorola RF Data Book (MRF536)
Motorola Small Signal Data Book (MPQ3546)
Hewlett Packard Microwave/RF Catalog
Inline, Inc Product Guide (213) 690-6767
Belden Cable Catalog
Harris Linear Data Book
National Linear Data Book
• Comlinear Data Book (303) 226-0500
Burr-Brown Integrated Circuits Data Book
BV Engineering, Filter Programs (714) 781-0252
Wigington/Nahman "Transient analysis of coaxial
cables considering skin effect" Proceeding IRE,
Vol. 45 No.2 Feb., 1957 p166-174 .
• Harris/RCA CA3019 Datasheet, ICAN 5299

2 - 64

APPLICATION

NOT E

Bt208 Evaluation Module

Operation and Measurements
Introduction
The internal voltage reference of the Bt208 is fed back
to the positive reference input, giving a VREF+ of 1.2
volts. A 200 ohm resistor is connected from VREF to
ground to provide a resistive load as specified in the
Bt208 datasheet.

The Bt208EVM is a two layer printed circuit board for
the evaluation of the Bt208. The EVM features a
socketed Bt208, an SMA input connector, and a
48-pin DIN connector.
In combination with a customer-designed driver
board, the EVM board can be used to evaluate the
Bt208, or for testing at incoming inspection.

The Bt208EVM allows the user to make modifications
in the circuit to suit individual needs. The positive
reference voltage circuitry can be modified to provide
for an externally controlled, variable voltage
reference. To use the internal 1.2 volt voltage
reference to provide a variable REF+, remove jumper
C and install a jumper in location D. Also, R7 should
be replaced by a 300 ohm resistor, and a 100 ohm
trimpot should be installed in location R6. In this
configuration REF+ can be varied from 1.2V to 0.9V.

Driver Boards
The driver board is a user configured custom designed
circuit that connects to the Bt208EVM by a 48 pin
DIN input connector. The driver .board should provide
all clock and control signals to the Bt208, as well as
the ability to receive the digitized outputs. All input
signals should conform to the Bt208 datasheet
specifications.

The Bt208EVM also has empty locations on the
printed circuit board for buffers and amplifiers. These
locations are intended for manufacturing test only,
and are not required.

Operation

With the Bt208EVM, the user can make a variety of
measurements and compare these against the datasheet
specifications. Parameters such as Signal to Noise
Ratio, Output Delay, Integral Linearity and
Differential Linearity may be measured and verified.

To operate the Bt208EVM, video and control signals
must be supplied by the customer. If a video signal of
known configuration (i.e. a wedge, or ramp signal) is
supplied to the Bt208EVM, the digitized output can
be reconstructed using a DAC and compared to the
input signal to determine correct operation.

AC Measurements

The Bt208EVM will digitize a standard RS-170A,
RS-343, or PAL video signal whose range is 1.2 volts
peak-to-peak or less. If the input signal contains a
chroma subcarrier, a chroma trap should be inserted in
front of the digitizer to remove any chroma
information. To AC couple the video signal, remove
the jumper at U2 and replace it with a 0.1 IlF
capacitor. Also, jumper the level pin on the Bt208 to
either ground or Yin.

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580· (800) VIDEO IC
TLX: 383596· FAX: (619) 452-1249

SNR
Signal to Noise Ratio is defined as the ratio of the
amplitude of a desired signal at any point to the
amplitude of noise signals at that same point. SNR in
digitizers can also be described as the amount of noise
and distortion introduced by the digitization process.

2 - 65

•

AN-13

Bt208 has a typical value of ± 1/4 LSB Differential
Linearity with a maximum value of ± 1 LSB.

There are many methods that can be used to evaluate
the SNR of a flash converter, or digitizer. One method
that is well suited for use with the Bt208EVM is the
Best Fit Sine Wave method.

Performance Measurements

The Best Fit Sine Wave method uses a sine wave of
known amplitude and frequency as the signal to be
digitized. An input clock is chosen such that the
sample points on the sine wave will not repeat until a
given number of samples later. In the configuration to
be outlined, 4096 samples will be taken before the
same point is reached on the sine wave.

This section will illustrate measurement examples of
Signal to Noise Ratio and Linearity. The signal to
noise measurements require that a driver board be built
which will facilitate the storage of 4096 samples of
digitized data. This data can then be fed to a program
which can calculate the SNR from the sampled data
(Equation 1).

These 4096 samples are then used to reconstruct one
period of a sine wave. Since the 4096 samples are
never repeated, they can be used to construct a sine
wave with greater resolution than a simple
reconstruction at the clock frequency. This
reconstructed sine wave is then compared against the
ideal sine wave that was input into the Bt208. Any
errors in the reconstructed sine wave will be due to
distortion and noise, and may be used to determine the
Signal to Noise Ratio of the Bt208.

To measure and plot the Integral and Differential
Linearity of the B t208, the driver board must contain
circuitry similar to that of Figure 1. This figure shows
a closed loop system that can be used to measure
voltage and step values. These values can then be used
in Equation 2 and Equation 3 to plot the Integral and
Differential Linearity, respectively.

AC Characterization

Data Output Delay

Signal to Noise Ratio can be measured in a variety of
ways. Many of the methods require expensive
equipment and precision waveforms. The method we
will be showing is very simple to implement, and will
give an accurate SNR value.

Data output delay in the Bt208 is the time from the
rising edge of the sample clock to valid data on the
pixel outputs. The Bt208 has a maximum output delay
of 25 ns. This delay may be seen on an oscilloscope
by triggering the oscilloscope on the rising edge of
the pixel clock, and determining the time required for
the pixel outputs to change.

As mentioned earlier, the Best Fit Sine Wave method
will be used. This involves sampling a known sine
wave at a frequency such that no two of the 4096
samples taken will be on the same point of the sine

DC Measurements

wave.

Linearity

Once the data has been sampled and stored it may be
fed to a series of software functions. The first function
must be one to reorder the samples to make one period
of a sine wave. This function must know the frequency
of the sampled sine wave, the frequency of the sample
clock, the number of samples and the starting point of
the input array. With this information, the software
can take the input array and restructure it to appear as a
single cycle of a sine wave. Once this has been
accomplished, the output array can be passed to the
next section of software.

Linearity can be broken down into two measurements:
Integral Linearity and Differential Linearity.
Integral Linearity is the maximum deviation from a
straight line that has been best fit to the data points
of the input-output transfer function. Linearity is
normally expressed as a fraction of an LSB or as a
percentage of full scale. The Bt208 has a typical value
of ± 1/2 LSB, with a maximum value of ± 1 LSB. One
LSB is approximately 0.4 % of full scale.

Once the data has been reordered, a sine wave must be
fit to these data points. An algorithm to fit a sine
wave to a set of data points is discussed in the IEEE
Standard for Waveform Recorders (1057-1988).
Section 4.1.3.1 An algorithm for three parameter
(known frequency) least squared fit to sin wave data
presents an algorithm to fit a sine wave to a set of data

Differential Linearity is the maximum deviation of
any bit size from its theoretical value 1 LSB over the
full conversion range. For example, a Differential
Linearity of ± 1/2 LSB demands that each step be 1
LSB ± 1/2 LSB. A Differential Linearity of < 1 LSB is
the maximum allowed for monotonic operation. The

2 - 66

AN-13

threshold value. A simple DVM can then be used to
measure the output of the integrator to obtain the
analog voltage required to generate the specified
digital output.

points, given the number of samples and the
frequency. A series of sums are computed which will
yield a set of values that give the amplitude of the
reconstructed sine wave, and the RMS error of the data
from the ideal sine wave.

The voltages corresponding to each threshold value
from 0 to 254 should be recorded to be used in
computing and plotting the Integral and Differential
Linearity of the Bt208.

With the amplitude and RMS error, the SNR of the
Bt208 can be calculated. Equation 1 gives the formula
for computing the SNR given amplitude and RMS
error.

Plot Integral Linearity as:
SNR = 20 LOG lO«Amplitude * SQR(2»/(2*E RMS ))

For I

= 1 to 253:
I

Equation 1.

IL(I)

= 100*( 254

DC Characterization

VOLT (I) - VOLT (0) )
- VOLT(254 ) -VOLT (0)

Equation 2.

The Integral and Differential Linearity of the B t208
may be measured quite easily with the Bt208EVM. The
circuit shown in Figure 1 uses a closed loop system to
obtain data points which can be plotted to measure the
Integral and Differential Linearity of the Bt208.

Plot Differential Linearity as :
For I = 1 to 254:

( VOLT(I)-VOLT(I-l)
DL(I) = 100' VOLT (254) VOLT (0) - 254

The Threshold Select lines, 10 through 17, are used to
set the desired output of the Bt208. These lines may
be driven with a simple DIP switch arrangement. The
chosen threshold value is presented to the two 4-bit
comparators, which measures it against the digitized
output of the Bt20S. The comparators will then raise
or lower the analog input voltage until the digitized
value out of the B t208 is equal to the selected

Equation 3.
Typical plots for Integral Linearity and Differential
Linearity are shown in Figures 2 and 3. IL and DL are
expressed as a percentage of full scale in these plots.

2 - 67

•

BfUd{tree@

AN -13

.SV

arr"',CEP'"

74LS04

Te'

7J!RO OF BT20I

I'll'

CLOCK

PO
PI
74F269

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40
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110
120
130
140
150
160

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ALL CAPACITORS ARE IN MICROFARADS.

ALL RESISTORS ARE IN OHMS, 1/4'.1.

Jl
lb
P6L
20
P3L
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40
SPARE
SPARE
50
SPARE
60
70
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8b
SPARE
9b
SPARE
lOb
ZERO
l1b
5VA
12b
+5VA
13k! - +5VD
14b
+5VD
15b
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16b
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2e
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7c
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12e

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14e
15e
16e

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10. - DO

BT251 PLCC

la
P7L
20
P4L
30
PIL
4a
SPARE
5a
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SPARE
6a
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7a
8a
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DE
CLAMP
lOa
110
5VA
120
+5VA
130. - +5VD
140
+5VD
150
DGND
160
DGND

D3
D6
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RES
RES
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SPARE

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SPARE

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+5VD

DGND
DGND

Ib -

2b
3b
4b
5b
6b
7b
8b
9b
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llb
12b
13b
14b
15b
16b

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NOTES' UNLESS OTHERWISE SPECIFIED

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Figure 5.

Assembly Diagram.

B ROOKTREE

V3
BT251

V2
R3
R4
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84 2510 003

Silkscreen Layer.
2 - 82

REV

[

Broddree®

AN -14

BROOKTREE CORP

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2 - 83

•

AN-14

BROOKTREE CORP

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84 2510 003

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2 - 84

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APPLICATION

NOT E

Bt253 Evaluation Module

Operation and Measurements
programmed to detect sync on one of the VIDO video
sources. In most applications sync will be present on
the green channel, but that is not required.

Introduction
The Bt253EVM is a multi-layer printed circuit board
that contains three SMA connectors (RGB inputs),
circuitry for software controllable reference levels for
each color, and two 48-pin DIN connectors.

To program the Bt253, the AO - A2 lines are used to
specify which register is being accessed. These
control lines are latched into the Bt253 on the faIling
edge of RD" or WR". During a read cycle data is valid
40 ns after RD" is asserted. During a write cycle the
WR" line must be asserted for a minimum of 50 ns,
with data valid IOns before the rising edge of WR *.
Data is latched into the Bt253 on the rising edge of
WR*. MPU operations are asynchronous to the pixel
clock.

In combination with a customer-designed driver
board, this EVM board can be used to evaluate the
Bt253, or for testing at incoming inspection.

Driver Boards
The driver board is a user configured custom designed
circuit that connects to the Bt253EVM by a 48-pin
DIN input connector. The driver board should provide
all clock and control signals to the B t253, as well as
the ability to receive the digitized outputs. All input
signals should conform to the Bt253 datasheet
specifications.

The Bt253 control register must be programmed for
the appropriate digitization mode. Four modes are
supported: 8 bit pseudo color, 8 bit true color, 15 bit
true color, and 24 bit true color. See Table 1 for
output configuration.
Once the Bt253EVM is programmed for its
environment, video can be sampled and digitized. The
reference voltages used in the digitization process are
under the control of DACs in the Bt253. The reference
voltages can be varied by changing the values in the
lOUT data registers of the Bt253. These registers may
be written to or read from at any time, and are not
initialized.

Operation
The Bt253EVM provides SMA connectors for the
Red, Green, and Blue video input signals. The video
input signals are DC coupled to the Bt253. In this
configuration the level inputs for each of the three
colors should be left floating. It should be noted that
RS-170 signals have the potential to be offset as
much as 2V from ground. This should be taken into
consideration when attempting to digitize an RS-170
video signal. Since the B t253 allows for the
connection of two vidco sources per color, the
control register must be programmed to digitize the
VIDO video signal. In addition, the B t253 allows for
multiple sync sources, syncO, sync!, and all video
channels. The Bt253EVM must therefore be

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580 • (800) VIDEO IC
TLX: 383 596· FAX: (619) 452-1249

The lOUT registers specify the output current on the
IOUTO through IOUT5 output pins. The six MSBs of
data are used to drive the DACs. DO and 01 (the two
LSBs) must be programmed to be a logical zero.
To ensure linearity, the Bt253 must be periodically
zeroed. Asserting ZERO during each horizontal retrace
period is convenient, and will keep the linearity of
the Bt253 in spec. It should be noted that the Bt253

2 - 85

•

AN-1S

should have ZERO asserted for at least 1000 clock
cycles (cumulative) to initialize the comparators to
the rated linearity. In normal video applications this
will be transparent due to the number of scan lines
that will have occurred before using the Bt253.

AC Measurements
SNR
Signal to Noise Ratio is defined as the ratio of the
amplitude of a desired signal at any point to the
amplitude of noise signals at that same point. SNR in
digitizers can also be described as the amount of noise
introduced by the digitization process.

The video signal is sampled on the falling edge of the
sample clock, with an aperture delay of IOns. The
data is valid 40 ns after the rising edge of the sample
clock. The data is then fed to a transparent latch
before reaching the DIN connector. The user should
determine when the data will be valid out of the
transparent latch for the clock frequency being tested.

There are many methods that can be used to evaluate
the SNR of a flash converter, or digitizer. One method
that is well suited for use with the EVM is the Best Fit
Sine Wave method.

24-Bit
True
Color

15-Bit
True
Color

8-Bit
True
Color

8-Bit
Pseudo
Color

Output
Pins

Mode
(00)

Mode
(01)

Mode
(10)

Mode
(11)

R7
R6
R5
R4
R3
R2
Rl
RO

0
R7
R6
R5
R4
R3
G7
06

R7
R6
R5
G7
06
05
B7
B6

G7
06
05
04
G3
02
01
00

G7
06
05
04
G3
02
01

G7
06
05
04
G3
02
Gl

05
04
G3
B7
B6
B5
B4
B3

R7
R6
R5
G7
06
05
B7
B6

07
06
05
04
03
02
01
GO

B7
B6
B5
B4
B3
B2
Bl
BO

0
0
0
0
0
0
0
0

R7
R6
R5
G7
06
05
B7
B6

G7
06
05
04
G3
02
Gl
00

Table 1.

Color Output Configurations.

2 - 86

AN-1S

With the Best Fit Sine Wave method, a sine wave of
known amplitude and frequency is used as the signal to
be digitized. An input clock is chosen such that the
sample points on the sine wave will not repeat until a
given number of samples later. In the configuration to
be outlined, 4096 samples will be taken before the
same point is reached on the sine wave.

Performance Measurements
This section will illustrate measurement examples of
Signal to Noise Ratio and Linearity. The signal to
noise measurements require that a driver board be built
which will facilitate the storage of 4096 samples of
digitized data. This data can then be fed to a program
which can calculate the SNR from the sampled data
(Equation I).

These 4096 samples are then used to reconstruct one
period of a sine wave. Since the 4096 samples are
never repeated, they can be used to construct a sine
wave with greater resolution than a simple
reconstruction at the clock frequency. This
reconstructed sine wave is then compared against the
ideal sine wave that was input into the Bt253. Any
errors in the reconstructed sine wave will be due to
noise, and may be used to determine the Signal to
Noise Ratio of the Bt253.

To measure and plot the Integral and Differential
Linearity of the B t253, the driver board must contain
circuitry similar to that of Figure 1. This figure shows
a closed loop system that can be used to measure
voltage and step values. These values can then be used
in Equation 2 and Equation 3 to plot the Integral and
Differential Linearity, respectively.

AC Characterization

Data Output Delay

Data output delay in the B t208 is the time from the
rising edge of the sample clock to valid data on the
pixel outputs. The Bt208 has a maximum output delay
of 25 ns. This delay may be seen on an oscilloscope
by triggering the oscilloscope on the rising edge of
the pixel clock and determining the time required for
the pixel outputs to change.

DC Measurements

wave.

Linearity
Once the data has been sampled and stored it may be
fed to a series of software functions. The first function
must reorder the samples to make one period of a sine
wave .. This function must know the frequency of the
sampled sine wave, the frequency of the sample clock,
the number of samples. and the starting point of the
input array. With these pieces of information, the
software can take the input array and restructure it to
appear as a single cycle of a sine wave. Once this has
been accomplished, the output array can be passed to
the next section of software.

Linearity can be broken down into two measurements.
Integral Linearity and Differential Linearity.
Integral Linearity is the maximum deviation from a
straight line that has been best fit to the data points
of the input-output transfer function. Linearity is
normally expressed as a fraction of an LSB or as a
percentage of full scale. The Bt253 has a typical value
of ± 1(2 LSB, with a maximum value of ± 1 LSB.
Differential Linearity is the maximum deviation of
any bit size from its theoretical value I LSB over the
full conversion range. For example, a Differential
Linearity of ± 1/2 LSB demands that each step be I
LSB ± 1/2 LSB. A Differential Linearity of < 1 LSB is
the maximum allowed for monotonic operation. The
Bt253 has a typical value of ± 1/4 LSB Differential
Linearity with a maximum value of ± I LSB. One LSB
is approximately 0.4% of full scale.

2 - 87

•

AN-1S

yield a set of values that give the amplitude of the
reconstructed sine wave, and the RMS error of the data
from the ideal sine wave.

DC Characterization
The Integral and Differential Linearity of the Bt253
may be measured quite easily with the Bt253EVM. The
circuit shown in Figure 1 uses a closed loop system to
obtain data points which can be plotted to measure the
Integral and Differential Linearity of the Bt253.

With the amplitude and RMS error, the SNR of the
Bt253 can be calculated. Equation 1 gives the formula
for computing the SNR, given amplitude and RMS
error.

The Threshold Select lines, IO through 17, represent
the desired output of the Bt253. These lines may be
driven with a simple DIP switch arrangement. The
chosen threshold value is presented to the two 4-bit
comparators, which measures it against the digitized
output of the Bt253. The comparators will then raise
or lower the analog input voltage until the digitized
value out of the Bt253 is equal to the selected
threshold value. A simple DVM can then be used to
measure the output of the integrator to obtain the
analog voltage required to generate the specified
digital output.

SNR = 20 WG lO «Amplitude * SQR(2»/(2*E RMS ))

Equation 1.

+5V

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74LS04

TC'
PE'

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ZERO OF BT253

CLOCK

+5V
74F269

DO
D1
D2
D3

BO
B1
B2
B3

74LS85

AO
Al
A2
A3

10
11
12
13

U/D'

(O)A>B (O)AB (l)AB (O)A=B
Q'

74LS32

VINOF BT253
K

Figure 1.

Integral and Differential Linearity Measurement Circuit

2 - 88

AN-1S

Schematic Diagram (Figures 4 & 5)

The voltages corresponding to each threshold value
from 0 to 254 should be recorded to use in computing
and plotting the Integral and Differential Linearity of
the Bt253.

The Bt253 Evaluation Module schematic shows the
pixel outputs of the Bt253 connected directly to the
inputs of a 74F373. By only driving one TTL load with
each output, less ringing is present on the digital
outputs. This will help the B t253 keep noise down to a
minimum.

Plot Integral Linearity as:
For I = 1 to 253:

Assembly (Figures 6 & 7)

VOLT(I) - VOLT(O) )
I
(
!L(I) = 100* 254 - VOLT (254) - VOLT (0 )

Figure 6 shows the Bt253EVM as it is shipped to the
customer. The silkscreen layer is shown in Figure 7.
This provides a more detailed view of the board. Note
should be taken of the proximity of the decoupling
capacitors to the Bt253.

Equation 2.
Plot Differential Linearity as :
For I

= 1 to 254:

Signal Interconnect Plane (Figures 8 & 9)

The digital traces are separated from the analog arl,'a as
much as possible to prevent coupling. The analog
signals are kept in the analog area to reduce noise.

VOLT(I) - VOLT (I - 1)
(
DL(I) = 100* VOLT(254) _ VOLT(O) - 254

Equation 3.

Power Plane (Figure 10)

Typical plots for Integral and Differential Linearity
are shown in Figures 2 and 3. IL and DL are expressed
as a percentage of full scale in these plots.

The analog and digital power planes are combined at a
point with a ferrite bead (Ll). The analog power area
underlays the analog signals to reduce noise.

Ground Plane (Figure 11)

PCB Construction

The analog and digital ground areas are separated using
tub isolation. They are connected as close as possible
to the power and ground connector to reduce noise.

The Bt253EVM board is an epoxy fiberglass board
constructed with four 1 oz copper layers: VAA, 2
signal planes, and ground. The Bt253EVM design is
outlined with a schematic diagram giving the
component values and the DIN I/O connections, the
assembly diagram of component placement, and the
PCB artwork film.
The PCB artwork is provided for evaluation purposes
only. These layouts should not be considered ideal,
and have not been tested for FCC compliance. The
following descriptions highlight critical component
placement and considerations.

2 - 89

•

AN-iS

I-

It:

a
w

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Figure 2.

Typical IL Plot.
2 - 90

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lb
2b
3b
4b
5b
6b
7b
8b
9b
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11b
12b
13b
14b
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16b

lb
2b 3b
4b
Sb 6b
7b 8b

9b
lOb 11b
12b
13b 14b
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R6l
R3l
ROl
G5l
G2L
B7l
B4l
B1l
GCLK
ZERO
5VA
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DGND
DGND
J2
D1
D4
D7
AO
CSYNC
oEl3
SPARE
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2e
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7e
8e
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13c
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7e
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11e
12e
13e
14e
15e
16e

R5l
R2L
G7L
G4l
Gil
B6l
B3l
BOl
BClK
RCLK
5VA
+5VA
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+5VD
DGND
DGND
D2
D5
RD
Al
DEll
VIDIN
SPARE
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SPARE
SPARE
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DGND

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R29
lK

RO
Rl
R2
R3
R4
R5
R6

; DE
U5 VCC
4 lD 74F373 lQ
7 2D
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8 3D
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5
6
9
12
15
16
19

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9
12
15
16
19
11

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AN-1S

Assembly Diagram.

Figure 6.

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Silkscreen.

2 - 94

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84 253(1) (1)(1)2 [

AN-IS

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84 253Q) Q)Q)2

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Signal Interconnect Plane.

BROOKTREE

84 253Q) Q)Q)2

Signal Interconnect Plane.
2 -95

[

•

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2530 002

Power Plane.

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Figure 11.

Ground Plane.
2 - 96

2530 002

APPLICATION

NOT E

Bt451/457/458 Evaluation Module
Operation and Measurements
applications where three Bt457s would be used. When
installed in the EVM the Bt457 can only be used to
evaluate gray scale applications. It can not be
connected to other Bt457EVM boards to provide 24
bit true color.

Introduction
The Bt451EVM is an evaluation circuit board for the
Bt451, Bt457, and Bt458 pin/software compatible
RAMDACs. The EVM features an 84-pin PGA socket,
voltage reference circuitry, SMA output connectors
and a 96-pin DIN input connector.

Bt458
The Bt458 overlay registers and color palette RAM
outputs are 24 bits wide and drive three 8-bit
VIDEODACs. This allows the Bt458 to be used in
pseudo-color applications where a larger addressable
palette address is required. In this case the palette is
16 million colors.

In combination with a customer-designed driver
board, this EVM can be used to evaluate the
RAMDACs, or test at incoming inspection.

Features
The B t451 EVM can be used to exercise all of the
functionality of the respective RAMDACs. 'fhe on
chip features include programmable blink rates, bit
plane masking and blinking, and selectable pixel
mUltiplexing. Each of these features are controlled by
a driver board supplied by the user.

Driver Board
The driver board is a user-configured custom-designed
circuit that connects to the 96-pin DIN input
connector of the EVM and provides stimulus to the
RAMDAC. The input signals drive and timing
specifications should conform to the Bt451/7/8
datasheet.

The RAMDACs also include a 256 location dual port
color palette RAM, and 4 dual ported overlay
registers. The word length of the color palette,
overlay registers, and output structure are different for
each of the RAMDACs.

Driver board designs vary a great deal, dependent upon
the measurement and accuracy required. Designs can
provide an interface with existing test equipment or a
custom design to facilitate multiple parameter
characterization.

Bt451
The color palette RAM and overlay registers of the
Bt451 are 12 bits wide, and drive three 4-bit
VIDEODACs. This structure allows for pseudo-color
applications with 256 displayable colors out of a
palette of 4096.

Designing a driver board for the multiplexed
pixel/overlay inputs requires a multiplexer interface
so that pixels are presented to the RAMDAC at the
load clock rate. Composite video sync and blank
timing generation can be accomplished with a PAL
device.

Bt457

The block diagram of a general purpose driver board is
shown in Figure 1. The microprocessor interface port
can be used to upload the palette and overlay RAMs,
and address the RAMDAC internal registers.

The Bt457 is a single channel version of the Bt458. It
has a 256 X 8 color palette, and four 8-bit overlay
registers. The Bt457 is aimed at 24 bit true color

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580 • (800) VIDEO IC
TLX: 383 596 • FAX: (619) 452-1249

2 - 97

•

AN-16
r--

RAm
SELECf

VIDEO
TIMING

MODI!
SELI!Cf

PATIERN
COUNTERS

J
CLK, a..K"'. LD*

pO·P7(A·E)

MUX
01.0 • OLl (A·E)

PALETTE
COUNTERS

I/O
TIMING

i!:

CO,Cl.RIW, CE"

I
Figure 1.

'--

Driver Board Block Diagram

Operation

Since the EVM board may be used to test the Bt451.
the Bt457. and the Bt458. the user may wish to
evaluate more than one part. To remove the RAMDAC
without damaging it or the EVM board. a PGA
extraction tool. such as the Augat TX8136. should be
used. To prevent latch-up when inserting a device
into the EVM. power must be off to assure that no
inputs will exceed the VAA by greater than + O.5V.
Note: Signals to the EVM should be at a logical low
level until power to the EVM has stabilized.

The EVM board contains a 100 ohm trimpot in series
with a 470 ohm resistor to provide a variable RSET
value. RSET is used to set the full scale output current,
and thus the full scale output voltage, of the DAC. The
relationship between RSET and the full scale output
current on lOG or lOUT for the Bt457 is:
RSET (ohms) = 11,294 * VREF(v) / lOG (mA).
The full scale current on lOR and lOB for the Bt451
and Bt458 is:
lOR. lOB (mA) = 8.067

DO·D7

MUX

MPU
INTBRPACB

I
~

SYNC., BLANK'"

I
f--

CLOCK
GENERATOR

The Bt451EVM has been optimized for analog fidelity
and thus can be used to measure a variety of DC and AC
parameters from the Bt45117 /8 datasheet
specifications. Parameters such as Video output
levels, Pixel Rise. Fall and Settling times. Glitch.
Feedthrough. Prop Delay, PSRR and others can be
measured and verified. The measurement equipment
accuracy and proper measurement technique must be
considered for each parameter setup to assure
consistent and accurate results.

* VREF (v) / RSET (ohms)

With the trimpot all the way off. the RSET value is
470 ohms, giving a full scale lOG of 29.31 mAo
typical. Full scale lOR and lOB would be equal to
20.94 mAo typical. With the trimpot fully on. the
RSET value would increase to 570 ohms. giving a full
scale lOG of 24.17 mA and a full scale IOR/IOB of
17.26 mAo

DC Measurements

The FS ADJUST pin on the RAMDAC should be equal
to the voltage on the VREF pin. VREF should be
equal to approximately 1.235V, the nominal output
voltage of an LM385BZ-1.2 voltage reference. The
COMP pin should have a voltage equal to
approximately 3V.

RS343 Levels
A video ouptut waveform that conforms to RS343
compatible levels has the green channel output
voltage set to + 1.0V with the sync and blank pins
enabled. This is done by adjusting the RSET trimpot.
For a 75-ohm doubly-terminated load the total RSET
value is 523 ohms. Using a Vref of 1.234V and a total

2 - 98

AN·16

RED,BLUE

GREEN

19.05

0.714

26.67

1.000

-,----"',---------------~;;;:__---- WHfIll LEVEL

1.44

0.054

9.05

0.340

-+-------t------(----------- BLACK LEVEL

0.00

0.000

7.62

0.286

-t-------'--,;---r--'-----------

7.5 IRE

BLANK LEVEL

40 IRE

0.00

0.000

-L_ _ _ _ _ _ _ _

~~-L

_ _ _ _ _ _ _ _ _ _ _ _ SYNC LEVEL

Note: 75-ohm doubly-terminated load, RSET = 523 ohms. VREF = l.235v, RS343A levels and tolerances
assumed on all levels.

Figure 2.

Composite Video Output Waveform

load impedance of 37.5 ohms. Figure 2 shows the
typical output current and voltage values for a
RS343A composite video signal.

ideal RAMDAC is changed by 1 count. the output
should change by 1/255 (full-scale output - zero-scale
output). A deviation of this step size is a Differential
Linearity Error.

The measured video signal output peak-to-peak
amplitude for the green channel will be l.Ov ± 0.05
volts. The red and blue video signal will have a
peak-to-peak amplitude of 0.714v ± 0.1 volts. The
measured sync level should be 0.286v ± 0.05 volts
and a measured blank level of 0.054 ± 0.018 volts.
The intensity or grey scale range is the difference in
output from blank to white. These values should
measure 0.660 ± 0.018 volts on all channels.

AC Measurements
Rise. Fall and Settling Time
The RAMDAC output signal rise and fall times are
measured from the 10% to 90% points of the
transition output waveform. Settling time is a
measure of how fast the RAMDAC output settles from
the 50% point to within a ± 1/2 LSB value. These
Rise. Fall and Settling time waveform measurement
points are defmed in Figure 3.

Linearity
Integral Linearity Error is the maximum deviation of
the output from a straight line passing through the
end points. This value is expressed in LSBs or percent
of the grey scale range. If the code into the RAMDAC
is at any value (N). the output voltage should be N /
255 of the full-scale output. The maximum deviation
from that output value to the straight line value is the
Integral Linearity Error.

50%

-------1

RATED SETIIlNG
BAND

10% - - - - - - - /

RISE/FALL

Differential Linearity Error is the maximum difference
between the actual step size and an ideal step size. The
ideal step size is from an ideal converter with the same
end points as the devices tested. If the code for an

TIME

Figure 3.

2 - 99

Rise/Fall and Settling Time.

•

AN-16

The RAMDAC output ramp signal is shown in Photo 1
with the sync and blank enabled. The input codes are
counting at an LSB code step from 0 to 255 and
repeating. The total grey scale range is 0.66 ± 0.018
volts. The LSB value for a 0.66 volts grey scale range
that has 256 discrete levels is approximately 2.5 mY.

Performance Measurements
This section will illustrate measurement examples of
linearity and pixel rise/fall and settling times. The
Linearity measurements can be made with a ramp
output that will provide a step change equal to the LSB
value. The ramp output signal is generated by
providing 256 discrete input code changes to the
pixel inputs. The pixel rise/fall time measurements
are performed with an output signal that exercises the
pixels on and off. This output signal is generated by
providing input code values that change by single or
multiple bits and repeats.

For the data shown in Table 1, the value measured for
code 255 is 0.716205Y. The value measured for code
o (Black level), is 0.053952Y. This value includes
the setup, or blank pedestal, for the RED channel of
the Bt451n18.
Differential Linearity is measured with an input code
that increments by the LSB value and is applied to the
pixel inputs. The output is measured for each discrete
input code step and recorded. The output values
measured for each input code step are then put into
Equation 2 for a calculation of the worst case error
value in LSBs.

These measurements were made with a 1 GHz Sampler
BW oscilloscope using a 75-ohm doubly-terminated
coaxial cable connection. The driver board is clocked
at a pixel rate of 100 MHz.

DC Characterization
Integral Linearity Error is measured with an input code
that increments by the LSB value and is applied to the
pixel inputs. The output is measured for each discrete
input code step and recorded. The output values
measured for each input code step are then put into
Equation 1 for a calculation of the worst case error
value in LSBs.

Differential Linearity = ( ( ( Yout (code) - Yout
(code-I» * 255) / (Yout (256) - Yout (1») - 1

Integral Linearity = «Yout (code) - Yout (0» Ideal (code» * 255 / (Yout (256) - Yout(I»

AC Characterization

Units are LSBs

Equation 2.

Output rise/fall time measurements can be taken when
a single or mUltiple input code change pattern is
repeatedly applied to the pixel inputs. This burst or
multi-burst pixel pattern is used to exercise the
RAMDAC output switching transition. The pixel
burst code pattern is shown in Photo 2 with the sync
and blank enabled.

Grey Scale Range = difference in output from black to
white
LSB = Grey Scale Range I (2**n - 1)
Units are LSBs

Equation 1.

The output pixel burst signal that is shown in Photo 3
is enlarged such that calibrated measurements can be
made on the pixel switching characteristics. The DAC
rise time value is 2 ns and the fall time value is 3 ns.
These values indicate a good response time for a 20 ns
pixel width.

2 - 100

AN-16

Step

Measured

ILError

DLError

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

0.053952
0.056544
0.059054
0.061645
0.064240
0.066824
0.069336
0.071926
0.074344
0.076935
0.079445
0.082035
0.084621
0.087211
0.089725
0.092316
0.095618

0
-0.00195
-0.03547
-0.03781
-0.03861
-0.04364
-0.07640
-0.07912
-0.14807
-0.15041
-0.18394
-0.18666
-0.19092
-0.19364
-0.22563
-0.22797
0.04346

0
-0.00195
-0.03352
-0.00233
-0.00079
-0.00503
-0.03275
-0.00272
-0.06895
-0.00233
-0.03352
-0.00272
-0.00426
-0.00272
-0.03198
-0.00233
0.27143

Table 1.

Photo 1.

RAMDAC Output Ramp.

2 - 101

•

Bmddree®

AN-16

Photo 2.

Pixel Burst Code Pattern.

Photo 3.

Rise/Fall Time.
2 - 102

AN-16

PCB Construction

Signal Interconnect Plane (Figure 7)

The Bt451EVM board is an epoxy fiberglass board
with four copper planes for power, ground, and signal

Digital traces are separated from the analog area to
prevent coupling. The analog signals overlay the
analog ground area to reduce noise.

interconnects.

Ground Plane (Figure 8)

The following descriptions highlight critical
component placement and considerations for
modification of this information to your application
environment.

The analog and digital ground areas are shorted
together at Jumper (J2). The analog areas (signal,
power or ground) do not overlay any of the digital
areas (signal, power or ground) to reduce signal and
power coupling noise.

Schematic Diagram (Figure 4)
Parallel termination (R 1/R2) is used on CE* to reduce
noise sensitivity. The clock lines use a balanced
termination (R9) to reduce the common mode noise.
Jumper (J2) is shorted.

Power Plane (Figure 9)
The analog and digital power areas are combined at a
point with ferrite bead (Ll). The analog power area
underlays (Figure 10) the analog signals to reduce
noise.

Assembly (Figure 5 & 6)
The board silkscreen is also provided in Figure 6.
Pixel parallel termination (RNI-RNS) sockets are
provided to reduce data feedthrough.

Signal Interconnect Plane (Figure 10)
Camp chip capacitor (C14) is used for reduced lead
inductance and to allow close placement to the Camp
pin. The RGB output traces are short and of equal
length to reduced noise pickup and signal reflections.

2 - 103

•

AN-16

w'"
oro

<
n

CO RN1-A
RNI-9

R/l.JlIE RN2-8

DO
DI
D2
D3
D4
D5
D6
D7
elK,*,

"C1Z <1- r-:l f::- r-;'i

wn
w-

~~
L.

iii

~~
w:;:

RNI-4
RN2-5
RNl-5

RN2-6
RNI-6
RN2 7
RNI-7
RN2-8

0
0

BLANK*
SYNC_

~~ >,·.t" .f,,.",
4

;3,.
v

Ul",

Ul"

Ul(Xl

()

DO
DI
D2
D3
D4
]4 D5
A4 D6
]5
D7
l8
CLK*

POB
POC
POD
POE
PIA
PIB
PIC
PID
PIE
P2A
P2B
P2C
P2D
P2E
P3A

0~~~

~"
";0

C3
B2
E3
A2
A3

POA

""'

'"
z

GI
G2
HI
H2
~I

J2
KI
U
K2
l2

RN4-7
RN3-6
RN4-6
RN3-5
RN4-5
RN3-4
RN4-4

RN3-3
RN4-3
RN3 2
RN4-2
RN6-2
RN5-2
RN6-3
RN5-3
RN6-4
RN5-4
RN6-5
RN5-5
RN6-6
RN6 8
RN5 8
RN6-9
RN5-9
RN6-2
RN7-2
RN8-3
RN7 3
RN8 4
RN7-4
RN8-5
RN7-5
RN8-6
RN7-6
RN8-7
RN7-7
RN8-8
RN7-8
RN8-9
RN7-9
RN2-4

K3
MI
l3
M2
~
M3
M8
ClK
l4
M4
19
BLANK' P3B
MIO SYNC_ P3C l5
M5
l7 VDDO P3D
l6
M7 VDDl
P3E
Mil
A7 VDD2 P4A
UO
P4B
CI2
VAAO P4C UI
Cll
VAAl
KID
P4D
A9 VAA2
MI2
P4E
KIl
P5A
Ll2
AI2
P5B
COMP
KI2
CIO
P5C
VREF
JIl
P5D
JI2
P5E
810
FSADJ P6A HIl
HI2
P6B
M6
GI2
P6C
Gil
]6
P6D
A6 VSS2 P6E Fl2
BI2
FlI
AGNDO P7A
Bll AGNDl P7B EI2
Ell
P7C
DI2
P7D
]9 IDR
DIl
P7E
Al
OlOA
C2 RNl-3
AlO
OlOB
IDG
OlOC BI RN2-3
RNI-2
DLOD CI
D2 RN2-2
All IDB
OlOE
OUA D1 RN3-9
E2 RN4-9
DUB
OLIC EI RN3-8
DUD FI RN4-8
F2 RN3-7
DUE
1119 RN6-7
lD-

ClK

gw
~r"

]7 CO
A8
CI
B8
R/I.J*
A5

POA
POB
POC
POD
POE
PIA
PIB
PIC
PID
PIE
P2A
P2B
P2C
P2D
P2E
P3A
P3B
P3C
P3D
P3E
P4A
P4B
P4C
P4D
P4E
P5A
P5B
P5C
P5D
P5E
P6A
P6B
P6C
P6D
P6E
P7A
P7B
P7C
P7D
P7E
OlOA
OlOB
OlOC
DLOD
OlOE
DUA
DLIB
DLIC
DUD
DUE
lD_

la
2a
3a
4a
5a
6a

- GND
- GND
GND
- VCC
- VCC
- VCC

~~
8a 9a -

lao. -

lla
12a
13a
14a
15a
160.
170.
18a
19a
20a
210.
22a
23a
24a
25a
26a
270
280
290
300
310.
320

- P7A
- P6C
P5E
P5B
- P4D
- P4A
- elK_
- ClK
- P3C
P2E
- P2B
PID
PIA
POC
- OLlE
OLlB
OlOD
- OlOA
- D2
D5
- CDIE
CI

4. RNI-RNB PIN 10 TO

P7B
P6D
P6A
P5C
P4E
P4B
LD*
BlANK<
P3D
P3A
P2C
PIE
PIB
POD
POA
OUC
OlOE
OlOB
D1
D4
D7
R/\J*

GND
GND
GND
VCC
VCC
VCC
SPARE
SPARE
SPARE
SPARE
P7C
P6E
P68
P5D
P5A

17c -

lIE

"<-,
l8e -

19c -

20e
21c
22e
23e
24e
25e
26e
27e
28e
2ge
30e
31c
32c

P2A
PIC
- POE
- POB
DUD
OUA
- OlOC
- DO
- D3
D6
- CO

vee.

RNI-RN8 PIN 1 TO GND.

3. ALL CAPACITOR VALUES ARE IN MICROFARADS.
2. R6-R'3 ARE SURFACE MOUNT CHIP RESISTORS.
1, ALL RESISTOR VALUES ARE IN OHMS.

NOTES, UNLESS DTHERIiISE SPECIFJEO.

Schematic Diagram.

2 - 104

7b
8b
9b
lOb
llb
12b
13b
14b
15b
16b
17b
18b
I b
20b
21b
22b
23b
24b
25b
26b
27b
28b
2%
30b
31b
32

Ie
2e
3e
4e
5e
6e
7e
8e
ge
IDe
lle
12e
13e
14e
15e

5. ON RNI-RN8 THERE IS A .01 CAP TO P'w'R AND GND,

Figure 4.

Ib
GND
2b
GND
3b - GND
4b - VCC
5b - VCC

AN-16

("""'\

'iZ/',

V,<,,""

•••..•.

~~~ t:C

....

~~~

SSS

1;11;11;1

•••••••

Figure 5.

-c::J-

•

III

IIII

Assembly Diagram.

R1
R2

I /

GRN
1A

12A

~OOU

~ I~

,~ 00__R_~_:___ O""C-B_

12 M
N=-7_ --::R-:-

RN6

BT'I51 PGA EVM
8'1 '1510 00'1 REV 0
32

3(/')

C1 •
0

RNS

C11::J
rlOt;2

C~OU
1(])

B1
A1

B ROOKTREE
BT451

CORP

PGA EVM BO 84 4510 0040
Figure 6.

Silkscreen Plane.
2 -105

AN-16

.....
.....••~
......

CORP

BROOKTREE CORP
BT451

PGA EVM BO 84 4510 0040

Figure 7.

Signal Interconnect Plane.

.-•

,-,

-1-'

••

:.~:

::
::
::
::

'~I~

'.'. ,!.:..•••••••••
.........'i'••••••••••-::'..-.
.. .
0:••••••••

, -

_'
-:'.••••••••••••••••••••••••••••• ---i
•••••••••••••••••••••••••••••
•••••••••••••••••••••••••••••

BROOKTREE CORP
BT451

PGA EVM BO 84 4510 0040
Figure 8.

Ground Plane.
2 - 106

AN-16

..•••• .
••
..••.,-••••••:.
,.-••-

I...U_'

••••••

••
••
••
••
••
, -

...........
.................
-. ,..
.
:.
... ...

-.(._ .

.-,':-...

.........................
::::::::::::::::::::::::::1 :::
~---

BROOK TRE E [ORP
BT451

PGA EVM BO 84 4510 0040
Figure 9.

Power Plane.

--,

••
•
•••
•1.1:r:J:~:J: •• • ••.:J-

ilil.

• •••••••

•••••••••••••••

BROOK TRE E [ORP
BT451

PGA EVM BO 84 4510 0040

Figure 10.

Signal Interconnect Plane.
2 - 107

•

AN-16

2 - 108

APPLICATION

NOT E

Bt604/60S/606 Evaluation Module
Operation and Measurements
Introduction

Operation

Placing edges accurately in time has been the domain
of analog specialists.
With the advent of
mixed-signal high-performance devices, this function
has evolved from analog biasing of transistors for
variable control over timing functions, to digital
control with precise steps and programmed response.

The EVM requires a single -5.2 volt power supply and
ground which should be input to connector 11 at the
VEE and GND points respectively. The -2 volts
shown on connector 11 is the output of voltage
regulator VR3.
SWI and SW2 (Figure 5) set the counters to count up,
count down, load, or hold. If external control of the
counters is desired, then the counter data and the
counter control pins SWI and SW2 may be input
through connector 11.

Accurate edge placement using digital control depends
on the accuracy of the components, the layout of the
board, and interconnections between components.
Driving these changes are Brooktree's line of timing
verniers, or programmable delay lines.
The
following discussion centers around the operation of
the Bt604 and how to use the evaluation board to
make meaningful measurements.

Trig, Trig* and Tout, Tout* are accessed through 50
ohm SMA connectors. Under normal operation it is
recommended that a true differential signal be applied
to the Trig and Trig* inputs. The Trig and Trig* input
lines are terminated with a 50 ohm resistor to -2 volts
on the board. There is a position for ground
termination .which requires removing and resoldering
R5 andR6.

Description
The Bt604EVM is an evaluation circuit board for the
dynamically programmed timing edge vernier. The
board contains circuitry to exercise the delay span
range under internal or external control.

The clock for the 1OH136 counters can either be input
through connector 11 or through the supplied SMA
connector. This input line is not terminated, but may
be terminated with a 50 ohm resistor to -2 volts on
the EVM board, or on a separate control board
connected to 11.

The PCB is designed as a low noise 50 ohm
environment. Th~ signals are 10KH logic compatible
and are terminated into a -2V load. All input trigger
and output signals are differential ECL to minimize
crossover error. The basic circuitry consists of the
Bt604, two MCI0H136 4-bit binary counters, and the
circuitry associated with current sink transistors Ql
andQ2.

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580 • (800) VIDEO IC
TLX:383 596 • FAX: (619) 452-1249

The circuitry associated with Q 1 and Q2 enables the
user to connect Tout and Tout* directly to either 50
ohms to ground (oscilloscope termination), or 50
ohms to -2 volts (ECL termination). For oscilloscope
termination, switch SW4 should be in the ON
position, thus turning on current sinks Ql and Q2.
For ECL termination, SW4 should be in the OFF
position. The control of SW4 is also available at
connector 11, if external control is desired.

2 - 109

•

AN-I7

Additional controls for the Bt604 include the
adjustment of Tspan using trimpot R8. Adjusting the
trimpot allows the user to set Tspan from 3.9 to 40
ns. Figure 1 shows the span adjustment in relation to
the minimum output (propagation) delay and the fixed
width output pulse. Input CE* is controlled through
switch SW3 and/or connector n.

T·DELAY

TSPAN

Linearity for the timing vernier can be a
multi-dimensional problem, where linearity vs. Tspan
and Trigger rate are important. Adding another
dimension to the error specification is the sensitivity
of delay changes to changes in trigger rate, given a
specific Tspan setting. Ideally, the timing vernier
delay should be independent of input trigger rate at
any code, but this is never the case. In reality the
delay will vary slightly as the input trigger frequency
is swept. The characteristic can be described by
specifying the range of trigger rate, under a specific
Tspan where the output delay changes less than some
number of LSBs of delay. To make testability
economically feasible, the Bt604 linearity is tested
under a specific Tspan and Trigger rate. However, it is
characterized under many combinations of Tspan and
Trigger rate.

FIXED PULSE
WIDTII

MIN

TRIGGER
POINT

TMIN

Figure 1.

TMAX

Pulse Timing
Figure 2a is a plot of the linearity of the Bt604 at
frequencies of 20 to 100 MHz. The delay span of the
device under test is 5.0 ns. Each linearity curve is
normalized to its own endpoints for each partiCUlar
frequency. Each curve is a plot of delay integral
linearity for all codes, code 0 on the left, 255 on the
right. The values present on the plot for each
frequency are worst case deviations from the endpoint
determined straight line, in picoseconds.

Performance Measurements
This section will illustrate measurement examples of
linearity, the primary parameter indicating the
performance of the part. The Bt604EVM board may
also be used to measure propagation delay, pulse
width, setup and hold times, and all DC current and
voltage measurements.

Examining this type of plot yields information about
how frequency affects the linearity of the ramp, ramp
reset times and DAC settling times. Because the
fixture hardware is stable with frequency, one can also
determine what effects are present for absolute time
over frequency. Figure 2a has each linearity curve
normalized to its own endpoints so variations in
Tspan and absolute time are not evident.

Static vs. Dynamic Operation
In order to understand the important performance
criteria of the Bt604, it is best to separate the
specifications into two categories: Static Operation
and Dynamic Operation. In static operation, the
vernier input data changes less frequently than the
input trigger rate. In dynamic operation, the vernier
data changes at the same rate as the input trigger
(timing on-the-fly).

Figure 2b plots the same linearity curves as Figure 2a,
with all curves referenced to the endpoints of the 20
MHz measurements. The values that appear at the ends
of the linearity curves are the variations from the 20
MHz endpoints, expressed in picoseconds. The points
furthest from the horizontal line are the worst case
deviation from ideal linearity, based on normalization
to the 20 MHz plot. Linearity, time offsets, and span
variations over frequency for all codes can be seen,
making this a valuable tool for testing and
characterizing programmable delay elements.

Static Operation
Linearity
The vernier should be specified in terms of how linear
the delay is as a function of input data code. Integral
Linearity Error (ILE) and Differential Linearity Error
(DLE) will have the same definition as in data
converters, but applied to the time domain. ILE is
defined as the worst case deviation over all data codes
of programmed delay, as compared to the ideal
end-point to end-point straight line of delay. DLE is
the worst case deviation of LSB increments of delay
compared to the ideal LSB increment of delay. Both
are specified in terms of LSBs of error.

2 - 110

AN-17

""~::;::::;:::

. . .'. . '. . . . . '. '.....................'. . '. . '. '. . . . . . . '. '...........,...........,. ,.................,. . . . ,. . ,. ,......,. . . ,. . . . . . _. . . . .". . . . '·. . . '7

~.-.~~~~-.- - -..--...,..,..,...-.......r-~-..,./

70-·. . . . ,. . . . . . ·. . . . .·. . ,. . . . . . . . . . . . . . . ,. . . . . . ,·. . . ,·,...,. . . . ". . . . . . . . . . . . . . . . . . . . . ."". . . . . . . . . ,., . . . . . . . . . . . . . . . ,. ". . . . . . . . . ,;::::»'
~,..~_ _ _..-"............."..._·./'~____r./,......r..........."-JV,

' ' =:::;:::.:::::::;'. . ' '. .' . ' . . . '. ' . '. . ' . .'. . .

40 ~:::::::::::::"""."''' ..

Span:4998 pS

';;:;:;::;;;:;::;;~

30 -.~" . . ". '. '. "'='''. '. . . . . . . ' ' ...'. '. . . . ' ' ' . . . . . . . .' . . . . . . ,",. ,. . . ,. . . .,. ". . . ,'. . ". . .". . . ". . . . . . . . . . . . .". ,""":;;:::="""""""""'... each 1ine
60 pSec
20-~~""

............". '. "....·...... '......·'..............""" . . '. "" . ,...... , ,. ,',,........ , ..,',...,............,. , . ,....'. . . ,', . . ,. ,. "',",'-

Figure 2a.

Endpoint Linearities.

....~v_........______....-.
."....-..'--""J
90 .. ' ' . . . ''''~., . . ' ' '."." . . '''''''''''''~. . ''''''.".,.''',,::~.~I11~::'r.~·.....~'~~=9W~..""".~"r:."'."."""""'.."~"".""...~...

-""'

80 ~:-:..~-::::.:.~,~~~.:c::::~~(,,::.c::.=:c:.::::::::::::::':..c:::::::::=:::::::::::.~:::..:~::::::::~_. ,_H~r:oa~H~req
70 ::':~;:,~,.--,~-~~:" . . '''''''. ::::::::::::::::::::::~:::::::::::::::':::::.::::::::::~::. ,
Span:5000 pS

20 ..""""=,;:<;::;;::;;=::::::::;;::::" .......... '........'.............."
~

Figure 2b.

... " .• "'''m .. '''''' .. '' ••• ,'''''_._,,, ... ,, ..... ,, .. ,''',,·,'',,·,,,,·,, .. ,,''''''''''' .. ""'~

All Data Normalized to 20 MHz Endpoints.
Static Linearity Over Frequency

2 - 111

•

AN-I7

Dynamic Characterization

Measuring Dynamic Performance

Once the linearity of the device has been determined,
one can test for dynamic performance. The test
involves two steps. First the device is set to a specific
Tspan and forced to count down the four MSB bits.
The counter is clocked at the trigger rate to ensure
on-the-fly timing. The output of the device is
connected to a high speed digital oscilloscope such as
the HP54120T, required to observe picosecond
resolutions. With the persistence on the scope turned
up to infmity, one can view the 16 individual output
pulses as the counter is clocked through its states
(on-the-fly). Next, by incrementing the counter
slowly, one can observe the same 16 output pulses,
which are overlaid on the pulses generated under the
previous on-the-fly condition. Figure 3a is a printout
of a Bt604 clocked at 100 MHz with the four MSBs
decrementing on-the-fly. Figure 3b is a printout of the
same device, this time incrementing all codes at 100
MHz. The prior linearity experiment shows how
linear the device is under static conditions, so any
difference observed between the overlaid pulses is the
error attributed to the dynamic performance of the
device. This simple, yet effective, experiment yields
extremely valuable data.

Best dynamic performance (data changing each clock
cycle) is obtained with an input trigger pulse width of
2 ns to 3 ns and a data setup time of 5 ns to 6 ns.
When SWI and/or SW2 are set to count down (DEC),
maximum trigger rate with 5 ns Tspan is 100 MHz (10
ns clock period). With 4 ns Tspan the maximum
trigger rate is 111.11 MHz (9 ns clock period).
When SWI and/or SW2 are set to count up (INC), to
avoid violating the specification for output pulse
spacing (when the counters wrap around maximum
delay to minimum delay) the maximum trigger rate
with 5 ns Tspan is 71.42 MHz (14 ns clock period)
and with 4 ns Tspan the maximum trigger rate is
76.92 MHz (13 ns clock period).
When the Bt604 data input pins are driven from an
external source (via connector II) with the counters in
pre-set (LOAD) mode, ensure that changing delay from
a higher to lower value does not violate the output
pulse spacing specification.
Figure 4 illustrates a suitable evaluation test setup.
The 8 ns delay on Trig and Trig*, in conjunction with
the typical 3 ns propagation delay through the
counters, results in a setup time of 5 ns. Setup time
may be adjusted by choosing appropriate cable
lengths for clock, Trig and Trig*.
A small cooling fan is recommended.

HP54120

OSCILLlSCOPE

OUT OUTO
TRIG

TRIG
.-----IC1ock

-2v

Bt604

EVM
A
......----{fR·IG

POWER
SUPPLY

+SV(lOOmA)
-5.2V (500 mAl
-2V(100 mA)

'--------'

Figure 4.

Dynamic Measurement Setup

2 - 112

TRIGO
B

950

AN-17
r···'· .. ·········..·..··r·........

: ......
!j............ " .........,!:...........

••• . . ••••••

T-· .. ··..·············T .. ········· ..·"·"· ..T······· .... ·······.. ···~ .. ······ .. ··.....................................;.......................

' 'l
H ..........

o!-........

L.·6~1":. S·j·QHii. . ·n·5. ·..
Ch. 2
Tll'1ebase

·.. ····1 ....······ .. ····.. ·· .. ;···.. ,

...... ········.. 1···· .................,........

'j'.....····....···· ...."i···.. ·····,,··,··········

...

. ....:

i ................... ,: ..........................,'. .....,..... ...............,..............'
.. ........,.............................................,:

i ..................... ,... ·· .......... · ..

'·'j·iL·0'3'efijj'··n·s. ·....L.................... ,......···..·..···.. ·..··'...j·I3":..5·j00
Offset
Delay

21010.10 I'IVolts/div
51010 ps/dlV

-i.5IZJIZJ

Volts

36.1031010 ns

lOOMHz DECREMENTING 4MSBs OVERLAYED WITH STATIC MSBs
Figure 3a.

Ch. 2
Tll'1ebase

21010.10 I'IVolts/dlv
i .010 ns/dlv

Offset
Delay

Figure 3b.
Dynamic Linearity
2 .. 113

-i .51010

Volts

37.441010 ns

•

AN·17

PCB Construction
The Bt604EVM board is an epoxy fiberglass board
with five 1 oz. copper planes for power, ground,
termination and signal interconnects.
The
Bt604EVM design is outlined with a schematic
diagram giving the component values and the DIN I/O
connections, the assembly diagram of component
placement, and the. PCB artwork film. The PCB
artwork is provided for evaluation purposes only.
These layouts should not be considered ideal, and have
not b~ tested for FCC compliance. The following
descriptions of the figures highlight critical
component placement and considerations.

Schematic Diagram (Figure 5)
The component schematic diagram shows
terminations for DO - D7 signals from the 40-pin DIN
connector. All interconnecting signal lines on the
board are 50 ohm terminated into -2V.

Assembly (Figure 6 & 7)
Figure 6 shows the Bt604EVM as it is shipped to the
customer. The silkscreen layer is shown in Figure 7.
This provides a more detailed view of the board.

Signal Interconnect Plane
(Figure 8 & 12)
The digital traces are 50 ohm transmission lines for
all signal interconnects. DC signal traces may not be
50 ohms.

Power and Ground Planes
(Figure 9, 10 & 11)
The board uses solid power and ground planes. The
-2V plane is split with a subplane for -5.2V. The
-5.2V plane is the larger plane in Figure 10.

2 - 114

VEE-r
1
3

GND

--29

~
~'
;::

....

;.-.
IV

'"
'"S'!

;:,.

;:,

-2V

11
13
15
17
19
21
23
25
27
29
31
33

10
12
14
16
18
20
22
24
26
28
30
32
34

L---4--_4-.___O_4__

TRUTH TABLE
U1,U2
U1,U2
Sl
S2
,
SW1,SW2 SW1,SW2 1
POS. 1 POS. 2

05
04

-2V

(:;'

0
S'
OQ

VEE

01
DO
CLK
07
06

VEE

-=-

OFF
ON
OFF
ON

OFF
ON
ON
OFF

I LOAD

HOLD
INC
DEC

[[J-

illD _

illTI-~-}50
-2V

CONNECT AS CLOSE
TO PI N AS POSSIBLE

O~O:A~ 50
-2V

3~V fOPTIONAL

CONNECT AS CLOSE
TO PIN AS POSSIBLE

[!ill-lE!] =

-2V

lED -IE[] =
1

CONNECT AS CLOSE TO PIN AS POSSIBLE

50
OPTIONAL

R5.R6

-2V

-2V
VEE~

C7,Cl1

CONNECT AS CLOSE
TO PIN AS POSSIBLE

NOTES: UNLESS OTHERWISE SPECIFIED
1. RESISTOR VALUES ARE IN OHMS, CAPACITOR VALUES ARE IN MICROFARADS.
ALL 50 OHM RESISTORS AND ALL CAPACITORS ARE SURFACE MOUNT DEVICES.
"OPTIONAL" RESISTORS ARE NOT INSTALLED.

-=-

Z
•
~

B> OFF= EXTIERNAL TERMINATION TO -2V, ON= EXTERNAL TERMINATION TO GND.

-...J

•

AN-17

Figure 6.

Assembly Diagram.

CR10C;1 C:t OS
:-:C:J-

--c:IJ--

Te1

I -

1 2

3.
MCl (l)Hl 36P

T7-

T11

I
T[4

CLOCK

T12

<,\,

-'C:J-

[2rzJ

TOUT
[B

[14

III I

[12

[15
T1 5

El_ R

TC811 6

T1.

Figure 7.

TR IG

Silkscreen.

2 - 116

[16

VR 3
[7

-[[=:J-CR3

[11

c=Jl-C9

SW3

TCS T13-

Tgl41

r(s

CR2

:[[3~

VR2

B g [17
[19
Ql
E 1'[18/
';t0Rl1
R3
/
Ll A9
B
I

(

TOUT QR1.

----[==:J-

SWl

MCl1'l.lH136P

VR1
R2

L
W4

TR IG
R7

----[==:Jc=J1
R8

84 6040 QlQ)l A
8T604 EVM

AN-17

~.-=l
.
·
1[00\:'[,..
..
F~"I!:
;-_
~~~
,.-_
r: ..... ••••
~
,. ~ •
:
- . ~

. .. .....

•
.
.
~'~.~~~"ilL. ·
&;:-'n~l ~~.:~m~\

1''"-~~~
~ I ..•••
• ••

I.:.

••

•

KTREE

[ORP . • _

BR00-:.J

PAD MASTER

Figure 8.

Signa I Interconnect.

..
•
.:.
..
• •
........
• ••• ••• • •
..........
..• . • .. • .
..;.

.:. I I. It .~ I •
:.

.:.

.......
... '.. .
.:.

.•:.

..
..
.tC

'.'

:-• . . .~. Iii l1li":. ..-.:.

.. I
••••1•• ·:· '.'

-.:. •

: ::

•••••••...-

••

·~I

tI .:.1...:.. •
...:.
I"~..
.:.

•

'.'

.:.

Figure 9.

Ground Plane.
2 - 117

•

AN-17

• •• It ·1
I I.
':.
••
• •••••••• • •
••••••••
•
• .:.
.:.
• ••••
.:. i
.:::
1
•••
•
.:.

.tC

•••••
••

•

...
... .

'.'

,.".,

.....
,
..
H•
••

•

'.'

I I

••
•
•••
••

Figure 10.

..::...

Termination Plane (-2 Volts) .

•
•
•
•
..• .......
•• . •••
• •
••
•
••
•
•· .... • • • • •••••
•••
.. . .. :- t a " ..
••
I I.:. .. I I

• ••••••••

·· ............,.. ,.
:

:~::~:

• :. ·.1
• ••• ••

.II!.

..
.... .. ...

'.'

•••••

'. .:.:...

...
•••
'.'

Power Plane (VEE

2·118

I -; ••

••

Figure 11.

.:
.:.

= -5.2

••••

• •

Volts).

AN·17

•

·• .:

••
••
••
••

L:..
PAD

•

••
••
••
••
••
••
••
••
••
••
••

00
00

I••

0°

~·
0

•
•• • ••
•••
••

MASTER

Figure 12.

Signal Interconnect.

2 - 119

••

00 • • •

•
•••

..:.J

•

AN-17

2 - 120

APPLICATION

NOT E

Pixel Interleaving Benefits
of the Bt459
The added 90 ns are due to precharge. When
back-to-back accesses are made to the same memory
chip, the designer must allow 80 ns of precharge from
the rising edge of RAS * to the next falling edge of
RAS*, which would start the next memory cycle. If
many repeated accesses are made to the same device, a
large time penalty in the form of precharge would
have to be paid. In frame buffer applications where
many vector operations are to be performed, this
situation can impact system performance.

As the speed of microprocessors increases, a greater
percentage of operating time is spent waiting for
memory based transactions. This is becoming
increasingly obvious in video applications.
As more designers incorporate dedicated, high speed
processors and busses for frame buffer control and
manipulation, the demand for faster memories
increases. Current memory technology has brought
the access time of VRAM down to 100 ns. While this
is fast compared to memories of only a few years ago,
it presents a problem to the memory or frame buffer
designer. This problem is due entirely to the
difference between Access time and Cycle time.
Access time is the time required from the falling edge
of RAS* to valid data, and is typically 100 ns. Cycle
time is the time required from the falling edge of
RAS* to the next falling edge of RAS*, and is much
greater. In a typical 256K X 4 VRAM, the cycle time
for a 100 ns part is 190 ns (Figure 1).

VIH--

RAS·
VIL _ _
VIH _ _

In many frame buffer applications, pixels are stored
sequentially in memory. That is, pixel 0 of line 0 is
stored in address 0, pixel 1 of line 0 is stored in
address 1, and so on. If the frame buffer uses four
banks of VRAM to mUltiplex the pixels, as would be
the case in a 1024 X 1024 frame buffer using the
Bt459, every fourth pixel would be stored in the same
bank of VRAM. This arrangement causes the pixels to
line up vertically in memory (Figure 2). In this

~-'~-\

tRC
-----tRAS

CAS·
VIL _ _

/ 7

t RC - Read or Write cycle time = 190 nS

t RAS - RAS pulse width = 100 ns
t RP - RAS precharge time = 80 nS

Figure 1.
Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580 • (800) VIDEO IC
TLX: 383 596· FAX: (619) 452-1249

VRAM Cycle Timing.

2 - 121

•

AN-18

0,0

0,1023
ABCDABCDABCD .. ,
ABCDABCDABCD.. .
ABCDABCDABCD .. .

usually configured, a precharge penalty will be
incurred in 25% of the cases, as the next pixel
addressed will be in the same chip in two out of eight
cases, In the worst case, a vertical line drawn from one
point to another, precharge would be incurred between
every cyc1e_ The designer then faces a problem:
increasing the speed of the frame buffer when current
memory technology forces a large time penalty in
vector based operations.
The solution lies in memory architecture. By
reorganizing the memory, the need for precharge can
be greatly reduced. By taking advantage of pixel
interleaving, the designer can arrange memory so that
no two adjacent pixels are stored in the same memory
chip. One method of interleaving pixels is shown in
Figure 4.

ABCDABCDABCD...

1023,0

0,0

1023,1023

Figure 2.

0,1023
ABCDABCDABCD .. .
CDABCDABCDAB.. .
ABCDABCDABCD .. .

4:1 Multiplexed Frame Buffer.

configuration, pixel 0 of line 0 is stored in the same
chip as pixel 0 of line I, pixel 0 of line 2, pixel 0 of
line 3 and so on, As this memory arrangement uses
four banks of pixels, this situation repeats itself
every four pixels.
This type of memory arrangement can cause problems
in vector operations. In a vector operation, the
processor operates on the memory from point a to
point b. For example, to draw a line from one point to
another, memory is accessed on a pixel-by-pixel
basis. When one pixel is accessed, the next pixel
accessed will most likely be one of eight adjacent
pixels (Figure 3). This means that as frame buffers are

CDABCDABCDAB...

1023,0

Figure 4.
A

Figure 3.

1023.1023

Pixel Interleaved Frame Buffer.

If the method of interleaving shown in Figure 4 is
implemented, a vector operation would never
encounter a situation where a precharge penalty would
be incurred for accessing an adjacent pixel. In the
worst case scenario (a vertical line), considerable time
is saved_ A vertical line of 10 pixels would, under
normal frame buffer architecture, have 720 ns of
precharge penalty when using a 100 ns VRAM. When
pixel interleaving is implemented, the same vertical
line would not require any precharge_ This would mean
a time savings of over 40%, and a corresponding
system performance improvement.

Pixel Alignment.

2 - 122

AN-IS

r-------r========::;===========

PB(7,0)
PA(7:0)
PC(7")

PD(7,O)

RAS

BANKO

~.I

BANKl

BANK 2

BANK 3

SIO

CAS 1
CAS 2
CAS 3

~ ~
0(7,0)

0(3'"0)

[BVENJ

0(23,16)

I I

Figure 5.

[BVENJ
~

rom>l

I I

1024 X 1024 X 8 Frame Buffer Block Diagram.

Interleaving the frame buffer presents some issues,
however. Frame memory is no longer sequential.
Pixels are stored out of sequence. Raster based
operations now need to track the image to sort out the
interleaved pixels, unless some method can be devised
to make the interleaving transparent.

as 1024 pixels by 1024 lines, the actual organization
of the memory is 2048 pixels by 512 lines. This
means that new data is shifted into the VRAM shift
registers every two lines.

The two LSBs of the address, ADO and ADI, are not
driven on the host bus. Rather, BHE (Byte High
Enable) lines, are decoded from ADO and ADI and
driven to signify which bytes are active on the bus.
There are four BHE lines, BHEO through BHE3. BHEO
controls data lines DO through D7, BHEI controls D8
through D15, and so on.

Since the pattern of the interleaving is regular, and in
this method repeats every two lines, it is very easy to
sort in hardware. The frame buffer can be made to
appear sequential to software. Pixel interleaving can
be added to current systems with no software intpact.
The drawback to this is the requirement for extra
hardware. For a frame buffer in a 32 bit host system,
eight data transceivers would be required to interface
the frame buffer to the host system. An additional
transceiver would be needed for each bank of VRAM.
While the number of transceivers has been doubled,
this cost in hardware is offset by the increased system
speed.

The address to the memory is composed of a pixel
address, and a line address. The frame buffer address of
1024 pixels by 1024 lines is converted to 2048
pixels by 512 lines for use as RAS and CAS addresses
to the VRAM.
To make the interleaving transparent to the software,
the data must be routed to the appropriate VRAM.
ADIO determines the frame buffer line. ADIO is low
for even, or non interleaved lines, and high for odd
lines, which have pixel interleaving. ADIO, in
conjunction with the BHE lines, can be decoded to
enable the appropriate transceivers, and can be used to
drive the appropriate CAS lines to the VRAM.

As is shown in Figure 5, to implement a 1024 X 1024
X 8 bit frame buffer using this interleave scheme,
eight 256K X 4 VRAMs are required. The frame buffer
pixels are stored in four banks, labeled 0 through 3.
This means that while the frame display is organized

2 - 123

•

AN-1S

In addition to pixel interleaving, the Bt459 supports
block mode operation in 4:1 and 5:1 pixel
multiplexing. Block mode operation allows the
Bt459 to latch pixels of various bit depths. In block
mode, the B t459 will latch pixels of 8 bits per pixel,
4 bits per pixel, 2 bits per pixel, and I bit per pixel.
Table I shows the order in which pixels are displayed
when in block mode. The combination of pixel
interleaving and block mode operation make the
Bt459 ideally suited for high resolution CAD/CAM
applications, as well as scientific workstation
applications.

The Bt459 has the ability to decode interleaved pixels
in the frame buffer for added system performance. The
pixel data may be latched into the B t459 according to
anyone of four available interleaving fonnats, and be
displayed in the proper order. The Bt459 may also be
programmed to accept various forms of pixel
interleaving, as well as different pixel multiplexing
fonnats.
To specify the method of interleaving, the interleave
register of the Bt459 must be programmed. The
interleave register fields CR30 - CR37 specify the
format of the interleave, the first pixel to be displayed
on a line that is panned, overlay interleave enable,
and underlay interleave enable. See Table 2 for the
Bt459 interleave register specifications.

I Bit per Pixel
(RAI - RA7 = 0)
RAO=

2 Bits per Pixel
(RA2 - RA7 = 0)
RAI,RAO=

4 Bits per Pixel
(RA4 - RA7 = 0)
RA3 -RAO=

8 Bits per Pixel
RA7 -RAO=

P7A
P6A
:
POA
P7B (4:1)
P6B (4:1)
:
POB (4:1)
P7C (4:1)
P6C (4:1)
:
POC (4:1)
P7D (4:1)
P6D (4:1)
:
POD (4:1)
P7E (5:1)
P6E (5:1)
:
POE (5:1)

P7A,P6A
P5A,P4A
P3A,P2A
PIA, POA
P7B, P6B (4:1)
P5B, P4B (4:1)
P3B, P2B (4:1)
PIB, POB (4:1)
P7C, P6C (4:1)
P5C, P4C (4:1)
P3C, P2C (4:1)
PIC, POC (4:1)
P7D, P6D (4:1)
P5D, P4D (4:1)
P3D, P2D (4:1)
PlO, POD (4:1)
P7E, P6E (5: I)
P5E, P4E (5:1)
P3E, P2E (5:1)
PIE, POE (5:1)

P7A, P6A, P5A, P4A
P3A, P2A, PIA, POA
P7B, P6B, P5B, P4B (4:1)
P3B, P2B, PIB, POB (4:1)
P7C, P6C, P5C, P4C (4:1)
P3C, P2C, PIC, POC (4:1)
P7D, P6D, P5D, P4D (4:1)
P3D, P2D, PlO, POD (4:1)
P7E, P6E, P5E, P4E (5:1)
P3E, P2E, PIE, POE (5:1)

P7A, P6A, P5A, P4A, P3A, P2A, PIA, POA
P7B, P6B, P5B, P4B, P3B, P2B, PIB, POB (4:1)
P7C, P6C, P5C, P4C, P3C, P2C, PIC, POC (4:1)
P7D, P6D, P5D, P4D, P3D, P2D, PlO, POD (4:1)
P7E, P6E, P5E, P4E, P3E, P2E, PIE, POE (5:1)

Note: Each line represents one pixel cJockcycle. A column represents One LD* cycle loading new PO - P7 data. All entries
with "4:1" descriptor are also valid for 5:1 mode.

Table 1.

Block Mode Operation (RA

2 -124

Color Palette RAM Address).

AN-IS

Interleave Register
This register may be written to or read by the MPU at any time and is not initialized. CR30 corresponds to data bus
bit DO. The interleave register is for support of frame buffer systems configured for interleave operation.

CR37 - CR35

Interleave select
(000)
(001)
(010)
(011)
(100)
(101)
(110)
(111)

These bits specify the order in which the pixels are to be
output, as shown in Table 3. The order is repeated every
LD* cycle for a given scan line. Thus, if the output
sequence is DABC, it is that sequence for all pixels on
that scan line.

0 pixels
1 pixel
2 pixels
3 pixels
4 pixels
reserved
reserved
reserved

The phrase "repeats every x" in Table 3 means that the
output sequence repeats every x scan lines. Thus, for 4: 1
mUltiplexing and a 1 pixel interleave select, ABCD
would be repeated every 4th scan line.
In the 1: 1 input multiplex mode, a value of 0 pixels
(000) must be specified.

CR34 - CR32

(000)
(001)
(010)
(011)
(100)
(101)
(110)
(111)

CR3l

These bits are used to support panning in the Y direction
with an interleaved frame buffer. Due to the interleave
capability, it is necessary to specify the value of the
first pixel on the first scan line following a vertical
retrace. The pixel {E} selection is only used in the 5:1
multiplex mode.

First pixel select
pixel {A}
pixel {B}
pixel {C}
pixel {D}
pixel {E}
reserved
reserved
reserved

These bits are ignored in the 1: 1 multiplex mode.

Overlay interleave enable
(0) interleaving disabled
(1) interleave enabled

CR30

Underlay enable
(0) underlay disabled
(1) underlay enabled

This bit specifies whether or not OLD - OL3 and OLE are
to be interleaved or not. If interleaving is enabled, the
interleave factor and first pixel selection are the same as
for PO - P7. If interleaving is disabled, pixel {A} is
always output flIst and no interleaving occurs.

If command bit CR22 is a logical zero, this bit is used to
enable or disable the underlay from being displayed. If
CR22 is a logical one, this bit is ignored.
If the underlay is enabled (and CR22 is a logical zero),
the OLE inputs function as follows: If OLE ~ 0, PO - P7
data is displayed. If OLE ~ I, the underlay is displayed if
PO - P7 ~ 0, if PO - P7 ot 0 then normal pixel data is
displayed. The underlay uses overlay color 0 to provide
underlay color information.

Table 2.

Interleave Register Field Definitions.

2 - 125

•

AN-1S

5: 1 mUltiplexing

4:1 multiplexing

interleave
select

output
sequence

scan line
number

output
sequence

scan line
number

ABCDE

each line

ABCD

each line

ABCDE
BCDEA
CDEAB
DEABC
EABCD

n
n+l
n+2
n+3
n+4
(repeats every 5)

ABCD
BCDA
CDAB
DABC

n
n+l
n+2
n+3
(repeats every 4)

ABCDE
CDEAB
EABCD
BCDEA
DEABC

n
n+l
n+2
n+3
n+4
(repeats every 5)

ABCD
CDAB
ABCD
CDAB

n
n+l
n+2
n+3
(repeats every 2)

ABCDE
DEABC
BCDEA
EABCD
CDEAB

n
n+l
n+2
n+3
n+4
(repeats every 5)

ABCD
DABC
CDAB
BCDA

n
n+l
n+2
n+3
(repeats every 4)

ABCDE
EABCD
DEABC
CDEAB
BCDEA

n
n+l
n+2
n+3
n+4
(repeats every 5)

invalid

Table 3.

Interleave Operation (First Pixel Select

2 - 126

Pixel A).

APPLICATION

NOT E

Bt2S1 Real-Time Color Space
Converter and Corrector
and blue planes of the frame buffer can each drive their
own DAC, which in turn directly drives the ROB
inputs of the color monitor. Therefore, the choice of
the ROB color space for a frame buffer simplifies the
architecture and the design and building of the buffer
interface to the display DAC.

Introduction
A color space is a mathematical representation of a
set of colors from which a specific color may be
selected. Different applications may require different
color spaces. The choice of color space depends on
the source of the image, the operations to be
performed on the image once it is acquired, and the
type of output device the image will be displayed on.

Another reason for the popularity of ROB is due to the
considerable amount of research and experimentation
that has been performed to characterize the human
visual system using this color space. If ROB is
chosen as the color space, this research can be utilized
when designing other aspects of the imaging system.

The RGB Color Space
The red, green, and blue (ROB) color space is widely
used throughout graphics and imaging. Red, green
and blue are the three primary additive colors and are
represented by a three dimensional, Cartesian
coordinate system (see Figure 1). With additive color
primaries, equal values of all three components must
be added to a black surface to create white.

The NTSC Color Space
The National Television Standards Committee (NTSC)
developed a technique to broadcast color images in the
same bandwidth occupied by a black and white image,
without obsoleting the black and white television
receiver. The result was a color space that defined
intensity and color separately.

The ROB color space is the most prevalent choice for
frame buffers because a color CRT uses red, green and
blue guns to create the desired color. The red, green

The intensity, or luminance (Y) component, was
defined as the black and white portion of the image.
The intensity component of the color space allows
color transmissions to be displayed on a black and
white receiver with minimal loss of detail, thereby
meeting one of the goals of the NTSC.

RED I'---t---'--o('

The color portion of the image is divided into two
components, I and Q, which could then be used to
Quadrature Amplitude Modulate (QAM) an RF carrier.
Essentially, I and Q are two orthogonal vectors which
specify a point of color, as shown in Figure 2. Values
of I and Q represent a vector which can also be
represented by the magnitude (vector magnitude R in
Figure 2) and theta (vector angle I'l in Figure 2). The
magnitude is also referred to as the saturation of a
color, and the angle is the hue or tint of a color. With

BLUE
BLACK
Figure 1. The RGB Color Space
Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121-2790
(619) 452-7580· (800) VIDEO IC
TLX: 383 596· FAX: (619) 452-1249

2 - 127

•

AN-19
+1

a reduction of the amount of storage required over the
full bandwidth ROB components. For real world
images, an NTSC buffer can be less expensive and
require less board area than a comparable ROB buffer.

-Q

Selecting the Color Space

The ROB color space is not the most efficient when
dealing with real world images. All three components
need to be of equal bandwidth to represent all of the
colors contained in the space defined by the cube (see
Figure 1) since any point within the cube has the same
probability of occurring as the next. The result of this
is an image buffer that has the same resolution and
pixel depth for each color. Selecting ROB as the color
space may also be a drawback if the image will be
operated on after acquisition. It is more efficient to
filter an image in the YIQ space once, than to apply
the same filter three separate times, one for each color
in the ROB space. To determine the "color" of a
certain pixel, it would be necessary to read all three
components out of the buffer and process them to
obtain the desired answer.

-I

Figure 2. The NTSC, I and Q
Color Space
the color carrier frequency at 3.579545 MHz, this
combined signal could then fit within the existing
broadcast television bandwidth.
The equations to convert between ROB and NTSC are:
Y = 0.30(RED) + 0.59(OREEN) + O.l1(BLUE)

The NTSC color space is more efficient than ROB at
representing real world images for two primary
reasons. First, luminance and chrominance of an
image exist separately. This facilitates quick and
efficient image processing algorithms. Second, due to
the fact that the chrominance bandwidth is reduced, the
size of the image buffer can be reduced in resolution
and pixel depth.

I = 0.60(RED) - 0.28(OREEN) - 0.32(BLUE)
Q = - 0.21(RED) - 0.52(OREEN) + 0.31(BLUE)
and to convert from YIQ to ROB are:
RED = Y + 0.96(1) + 0.62(Q)

A system that is designed using ROB can take
advantage of a large number of existing software
routines since the ROB color space is the prevalent
choice for frame buffers. The backend of the image
buffer (DACs and other circuitry) may be easier to
implement than NTSC, especially when driving an
ROB monitor.

OREEN = Y - 0.272(I) - 0.647(Q)
BLUE = Y - 1.108(I) + 1.705(Q)
One should notice from the equations for I and Q that I
and Q can be represented by negative numbers. This
is of no consequence when mathematically converting
from one space to the other, but may pose a problem
for the designer. The system software that must be
provided and the video backend of the imaging system
must allow negative numbers to exist.

An NTSC image buffer may be the choice if the
application requires manipulation of the image. Since
the luminance component of the image explicitly
exists, operations such as filtering are more efficient
since the luminance value does not need to be
calculated by the CPU.

One result of the NTSC specifications is that the two
chrominance components be bandwidth limited to 1.5
MHz for R-Y and 500 KHz for B-Y. This can be
accomplished with no perceived loss of image detail
because the eye is less sensitive to color than it is to
black and white.
Since the bandwidth of the
chrominance components is reduced, the sampling
rate of I and Q can also be reduced thereby resulting in

Most of the inexpensive image sources that exist
today are NTSC, which implies that the front end of an
NTSC buffer would be simpler to design than a front
end to an ROB buffer for an NTSC source. Supporting
both color spaces gives the best of both worlds, since
the image can be represented to optimize CPU
processing.

2 - 128

Broddree

AN-19

look-up tables are provided in the input path before
matrix conversion. This allows the input data to be
modified prior to color conversion. Performing the
look-up transformation before the color space
conversion is a requirement for gamma correction of
the source image data.
To support image buffers that utilize the reduced
chrominance bandwidth, the Bt281 contains linear
interpolation filters. These filters can be used on the
bandwidth-limited chrominance channels to
reconstruct the missing values and provide full
bandwidth inputs to the conversion matrix. This is
important if the chrominance inputs to the Bt281 are
utilizing the bandwidth reduction allowed by the
NTSC specifications, and the output of the Bt281 is
required to be full bandwidth ROB.

The solution to the correct selection of a color space
is provided with the Bt281 Color Space Converter and
Corrector. The Bt281 allows an imaging system to
optimize a particular color space for a particular
application. The input to the Bt281 is a set of three
color primaries from any color space, such as ROB,
NTSC, YUV, YCrCb and others, with the result being
a set of three color primaries in the desired color
space.

Conversion and Correction
The Bt28! can be used to implement a completely
flexible color space imaging system. As shown in
Figure 3, the input to the system can be any color
space provided by the imaging source. The video data
is digitized by the Bt253 Triple Digitizer and is then
converted by the first Bt28! to the required color
space required for CPU processing. For display, the
image in the frame buffer is routed through the second
Bt281 and is converted to ROB so that it can be
displayed easily with a Bt473 True-Color RAMDAC.

The Bt281 coefficients for the 3 x 3 matrix multiplier
are programmable over a range of -4.00 < = X < =
3.996. The designer is not hindered by being limited
to only ROB to NTSC conversions. An imaging
system can lie programmed to use any color space that
meets the input/outPut requirements, and a completely
different color space for storage and manipUlation.
Since coefficients are programmable and are not fixed
to any particular color standard, the Bt281 can also be
used for sophisticated color correction algorithms and
image enhancement in real-time.

The Bt281 Color Space Converter and Corrector can
accept inputs at a clock rate of 36 MHz, making the
part ideal for real-time applications. Three 256 x 8

VIDEOTlMING

AND DRAM
CONTROL

R
VIDEO

YIQ. YIN.

BUS3

Y/R-Y(B-Y

AID

BT281

FRAME
BUFFER

BT281

BT473
RAMDAC

G
B

Figure 3. Typical color space convertor system
2- 129

•

AN-19

Summary
Imaging systems need to be designed so that they are
flexible enough to support different color spaces.
This is becoming a requirement because no one color
space is optimum for satisfying the requirements of
image processing, reduced image storage, graphics
and interfacing with input/output devices. The Bt281
Color Space Converter and Corrector gives an image
system the flexibility to use any color space, in
real-time, that is optimum for the application.

2 - 130

GRAPHICS
AND

IMAGING

PRODUCTS

APPLICATIONS

HANDBOOK

1 990

Introduction
Application Notes
Article Reprints
Industry Standards
Sales Offices

3-1

•

Article Reprints

3-2

TAB L E

CON TEN T S

AR-l "Trailblazing Architecture Creates 8-Bit VIDEODAC That Clips Along at
75 MHz" (Electronic Design, 6/27/85) .............................. 3 - 5

AR-2 "Racehorse RAM Spurs Sharper Color Graphics"

(Electronic Products, 9/16/86) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 - 7

AR-3 "125 MHz CMOS IC Supplants Numerous ECL Parts, Drive Million-Pixel

CRTs" (Electronic Design, 9/5/85) ................................. 3 - 13

AR-4 "Octal DAC Chip's Interface Meets Processor Bus Directly"

(Electronic Design, 9/4/86) ...................................... 3 - 21

AR-S "Video Palette Raises Color Ante to 1024 Separate Hues"

(Electronic Design, 8/20/87) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 - 27

AR-6 "Imaging Chip Holds Three 15 MHz 8-Bit ADCs"

(Electronic Design, 2/9/89). . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 - 31

AR-7 "How to Drive 4-Mpixel Displays" (Electronic Design, 3/89) ................ 3 - 37

3-3

•

Article Reprints

3-4

Article Reprints

Ele
ro,,~ ~ '''''''''''filcDesl·
.'''~,~
gn
..,,". .

.., .." . " ...,,'" -

NE'v'VSFRONT

devices nor any form of trimming. Until now. digital-toanalog converters. regardless of
their speed. fabrication process.
or the number of chips. have used
some combination of ratiomatched resistors. capacitors. or
transistors. as well as some form
of trimming.
The first CMOS video converter arrived only a year ago.
However. its 24-MHz update
rate. 7-bit accuracy (8-bit resolution). and glitch energy of
300 pV-s cannot compete with
this chip's 75-MHz update or its
true 8-bit resolution for use in
many of the high-end engineer- .
ing workstations.
With this chip. input data can
be pipelined at the front end of
the converter. because the few
nanoseconds of delay are inconsequential to the user-the display changes seem instantaneous. The typical gate delay with

Trailblazing architecture
creates 8-bit video DAC
that clips along at 75 MHz
Pipelined logic, segmented current sources,
and an innovative TTL-to-CMOS buffet' are
the building blocks in a video converter.

rue 8-bit resolution at 75
MHz can now be had in a
CMOS digital-to-analog
converter. The formula for this
unprecedented achievement is a
pair of architectural innovations
combined with two new circuit
designs.
Pipelined decoding logic and
almost completely segmented
conversion stages are the architectural elements. They team up

with two circuit designs: a single
MOS-transistor current source
and a buffer that shifts rapidly
from TTL to CMOS levels. Together. these ingredients make
possible the higher resolution
called for by the next generation
of color CRTs.
Moreover. the converter. developed by Brooktree Corp. (San
Diego. Calif.). requires neither
ratio-matched passive or active

Digital. to-analOg

Plpellned decoder

converter

~
Threshold

Set
Data

Data

63 lines
<>-----I8

{

OSY"_C_ _.j

Input dala

Data

buffer.

2 lines

Reference WMe

10% Overbright

6 MSBs

sources

T~~~~tn8s

Blank
Control

63 equal
current

or segments

2 binaryweighted
current

sources

'--r---I

2 LSBs

Clock

1. In Brooktr..•• video digltal-to-analog converter. plpalining end .egmentation yield 75-MH:r: word rete.
with I-bit re.olution and en accuracy 01 ± ". LSB.

3-5

•

Article Reprints
TECHNOLOGY NEWS
NEWSFRONT
the 3-lLm process is 3 ns; in fact, to
achieve the settling time of under
12 ns, no more than four gate delays are allowed in series in the
8-to-65-line decoder (Fig. 1).
The three sets of pipelined,
synchronous decoding latches
(registers) employ over 130 Dtype flip-flops. Yet the process
lets the chip fit into a 0.3-in.-wide
DIP of 24 pins (ELECTRONIC DESIGN, June 13, p. 177).
Most switch sequentially

The decoder furnishes 65 controllines for the high-speed
CMOS current switches, which
connect the single-transistor current sources to the analog output.
As the binary code to the input
increases, 63 of these lines
sequentially switch in the 63 .
equal current sources, or segments.
Those, in turn, combine to form
the 6 MSBs. The two additional

lines from the decoder switch in a
pair of binary-weighted current
sources (1121 and 1/41) to form the
2 LSBs.
Typically, circuits converting
TTL input levels into CMOS logic
levels (on a CMOS chip) incorporate an input inverter buffer
with a strong n-channel transistor and a weak p-channel device. Although that approach
turns in fast fall times, it comes
in with poor rise times and
cannot handle 75-MHz signals.
Therefore R"~ lktree developed a
bufft
that level-shifts
2.5 to
. , USIng only a 2-kn resistor and a 0.5-mA tracking
current source (Fig. 2).
The technique also compensates for the effects of temperature change. What's more, it
permits transistors in the buffer
circuit to be identical with the
rest of the transistors on the
chip.
Frank GoodertQU{Jh .
Voo

TTL~level

CMOS-level

input

output

2. At 75 MHz, the converter needs only a resistor and a
current source to change TTL levels into CMOS levels.

Electronic DeeigR • June 27. 1985

3-6

Article Reprints

•

3-7

Article Reprints
Product Details

Racehorse RAM spurs
sharper color graphics
Fastest-ever color-palette RAM IC
uses ECL and pipelining to
bring new economies to high-resolution display
Jeff Teza, Director of Product Marketing, and Wylie Plummer, Sr.
Design Engineer, Brooktree Corp., San Diego, CA

peed is the most outstanding
characteristic of Brooktree's
newest plpelined static RAM,
the 256 x 8-bit Bt402. At 4,ns, its
cycle time is the shortest in the industry. That kind of performance is
crucial to the memory's intended use
as a color palette in superhigh-resolution color graphics systems; for
superhigh resolution these days
means around 3 million pixels,
which have to be scanned at a speed
of 250,MHz.
In this application it also helps
that the Bt402 is cascadable, includes 3 x 8 bits of RAM (dubbed
Sidecar) for graphics overlays, and
is fully compatible with the Btl08
and the (new) Btl09 8-bit video
DI A converters. Furthermore, its
advanced ECL circuitry makes it directly compatible with lOOK ECL.
A 10K version, the Bt401, is also
available.
The video RAM does, however,
have one notable limitation: it does
not write as quickly as it reads. Its

applications are therefore limited to
those in which the read cycle time
sets the speed criterion. This is true
of-but not limited to-graphics
systems.
Applications galore
For example, automatic test
equipment (ATE) needs fast pattern-generation RAM to send short,
fast bursts of data to the device under test. Another case in point is microcode storage in CPUs. In "soft
systems," microcode is typically
loaded when the system is booted
and then accessed at fairly high
rates. In most CPU (and especially
mainframe) architectures, the microcode can be pipelined out from
static RAM storage. Still other examples are telecommunications and
general digital signal-processing jobs
like high-speed waveform synthesis,
in which data is written slowly but
read in high-speed bursts.
But the video graphics arena, with
its need for fast color palette RAMs,

3-8

is definitely the hottest application
for the Bt402 (see box, "The quest
for speed in computer graphics").
The RAM's 4-ns cycle time qualifies
it for use in graphics systems that.
operate at update rates of up to 250
MHz. In fact, an interleaved. pair
can through a latched multiplexer
handle 360 MHz, which is necessary
for 2 x 2-Kbit resolution, or 4 million pixels. And, the 3 x- 8-bit Sidecar RAM comes in handy for such
overlay displays as cursors, grids,
and other graphic elements. (For
non-graphics applications, another
version of the Bt402 comes without
the Sidecar RAM.)
Because its output buffers can be
tri-stated, the Bt402 can be cascaded
in depth. So, two Bt402s can be employed to build a 512 x 8-bit color
palette, four for a 1,024 x 8-bit palette and so on. Sixteen of the devices can build a 4,096 x 8-bit palette
before serious speed degradation
occurs in the cycle time.
With" its inputs and outputs

Article Reprints
with a lot of additional circuitry, including interleaving, l00422s or the
newer 4-ns 100474s can be rigged for
fast cycle times. But this approach
gets complicated.
For instance, a 1,536 x 1,280-pixel
system with a 4,096-color palette and
speed of 165 MHz would require no
fewer than 192 of the 100422s, not to
mention the attendant glue logic.

latched on chip, the Bt402 cascades
without the delays imposed by externallatches (see Fig. 1). Two additional control signals, DX and QX,
are used to synchronize the output
data with the rest of the control signals, such as sync and blank. The
DX input is latched on the rising
edge of the clock and appears on the
QX output three clock cycles later.

used. For this complex, expenaive
approach, a proliferation of chips
must be avoided to reduce the number of traces. But, because so many
100422s are needed to achieve 250MHz performance, the real estate
becomes very tight and more stringent production tolerances must be
maintained. Down the line, board
yield can become an issue, and so

CIOCK

CLOCK

00-07

VEE

GNO

Fig. 1. The pipelined 8t402 color palette RAM includes OX and QX control
signals that m~ntain synchronization between data and control signals. The
feedthrough (FT) pin enables the user to select either pipelined or nonpipelined operation,depending on system speed requirements.

In speed and cascadability, the
Bt402 far outruns that old workhorse
of the video scene, the 100422. This
256 x 4-bit RAM has given dependable performance in color palette applications. But, it is grossly inefficient at implementing the 150 to 360MHz graphics designs of tomorrow.
For one thing, the 100422 is only
4 bits wide. But in an RGB color
system, an 8-bit-wide color palette is
essential to the smooth shading of
3-d solids. (The human eye can perceive about 9 bits of green, 7 or 8
bits of red, and 7 or 8 bits of blue.)
For another, the 100422, like most
other static RAMs but unlike the
Bt402, relies on external latches.
These add 2 to 3 ns to its cycle time
-and 3 ns is about the entire cycle
time allowed a color palette at the
high end of the video speed spectrum.
And third, the 100422 starts out
with a cycle time of 7 ns. Of course,

With a 256-color palette and 250MHz updating, such a system still
requires the use of four l00422s per
channel-two to get up to speed and
two more to achieve 8 bits of brightness. And to the dozen 100422s must
be added the nontrivial circuitry
needed for interleaving (see Fig. 2).

Another level required
Worse yet, in a 360-MHz system
implemented with 1004228, another
level of interleaving would be required: eight RAM chips per channel. The faster 100474 would still require interleaving to allow adequate
setup and propagation delays in a
latched (pipelined) system.
Such system complexity is especially to be avoided at speeds of 150
MHz and more because it complicates pc-board design. Frequently,
the controlled-impedance techniques
of strip line board design must be

3-9

can power Consumption and rent dissipation. Clearly then, neither the
100422 nor the 100474 offers the
most elegant design solutions for
high-resolution systems.
All of the features of the Bt402
combine to reduce the chip counts of
color palette designs. In a threechannel color graphics system, three
Bt402s per channel can replace the
dozen 100422s. The new RAM's 4-ns
cycle time makes a speed of 250
MHz practical by eliminating the
interleaving (see Fig. 3). A 360MHz system does, however, involve
interleaving two Bt402s, but if
1004228 are used instead, the design
would once again take on the apPearance of a bird's nest of RAMs.
By offering a 4: 1 reduction in chip
count, the Bt402 now makes highresolution, high-speed displayappli.
cations.far easier to design and much
less costly. Moreover, the glue logic
needed is negligible, power. supply
costs are cut, less heat is generated,
and pc-board design is simplified.
To achieve additional design economies, a high-performance static
RAM like the Bt402 should be used

•

Article Reprints
Integrated Circuits
elK 1 _ _ _ _....:::::...M::::H.::.z_ _ _ _ _..,
elK 2 _ _ _ _ _1::;25::. .: :;MH.: .z_ _ _ _ _..,

MHz

100155

Fig. 2. The 4-blt-wlde, 7-ns 100422
video RAM is basic to this 250-MHz,
256-co/or lookup table. A threechannel RGB color system needs
three such circuits. And an 8-bit
graphics overlay function capable
of 250 MHz adds four more 100422s
plus glue logic to every channel.

100155

CHIP COUNT PER CHANNEL
Device
100155 mux
100422 RAM
Set/reset latch
EeL/TTL leveltranslators
Glue logic
Total

Without
overlay

With
overlay

3
21

with complementary, high-performance Of A converters-like the
200-MHz, 300-MHz, and faster Bt108s. Interleaved Bt402s linked with
top-end Btl08s can provide a 360MHz pipelined channel-the fastest
track yet to 2,048 x 2,048 pixels.
The Btl08 is an 8-bit, multifunc-

tion video Of A converter designed
primarily for high-performance,
high-resolution color graphics applications up to 400 MHz. (The Btl08300 is for 300-MHz operation, the
Btl08-200 for 200 MHz, and still
faster Btl08s are being selected by
the factory for special customers.)
Implemented in bipolar technology,
its unique bias circuitry enables operation with either of the standard
lOOK or 10K ECL power supplies
(respectively -4.5 and 5.2 V). And,
although it is a video 01 A converter,

3 -10

its video control signals can be easily
disabled for nonvideo applications.
For display applications, the Bt108 generates an RS-343-A compatible output and can drive either a
doubly term~ted 75-0 or 50-0 c0axial cable directly. It is available in
a 24-pin OIP or 32-pin ftatpack.
A fully segmented 01 A converter
architecture would have 2- current
sources-an expensive circuit that is
rarely justified. The Btl08 instead
employs a partially segmented architecture incorporating proprietary
Brooktree techniques. It therefore
operates with low glitch energy, so
that maximum differential and linearity errors are only ± 'h LSB over
the range of -25' to +85'C.
The partially segmented architecture employs a sophisticated decoding scheme for routing bit currents
to the output. Precision component
ratios are eliminated, and so are the
switching transients that arise when
sources are turned on and off.

Article Reprints
Integrated Circuits

ClK-iI15OMiiiZ----;:==:;-------r----,
r---r'--fDI

01
SEl

Fig. 3. The 8-bit-wide 8t402 video
RAM with Its 4-ns cycle time and
on-chip graphics overlay RAM
creates a dramatically simpler
250-MHz, 256-color lookup table
than the one In Fig. 2.

1,1 MUX

100155

READ
ADDRESS

CHIP COUNT PER CHANNEL

lOOI55

Device

WRITE ADDRESS --+.-.....
DIR

Without
overlay

l00155mux
Bt402RAM
ECl/TTL leveltranslators

l~D----_+-------~_t_r_+_;~

WE----------'
DATA

With
overlay
3
3

----:~-----'

Another sensible video RAM and
DI A converter combination is the

Bt402 plus BU09. The new BU09
triple 8-bit video DI A chip is an
ECL version of its pioneering BUOI
CMOS predecessor. It is rated up
to 200 MHz and so can handle resolutions of up to 1,536 x 1,280 pixels.
Thus, it is ideally suited to midrange graphics display applications

like the current generation of CADI
CAM systems. These today employ
1,280 x 1,024-pixel resolutions and
typically use 125-MHz DI As.
The BI109, like the BUOS, offers
pipelined operation to ensure synchronization of the sync, blank, and
reference white inputs with the digital input data. It also uses a partially
segmented architecture to achieve

Total

the same maximum differential and
linearity errors and is compatible
with 10K ECL logic. It generates
an RS-343-A compatible output and
can drive doubly terminated 75-0
coax directly.
0

The quest for speed In computer graphics
The ultimate goal in video graphics is a
display with the quality of a 35-mm
photograph. Such quality entails a screen
resolution of 4,096 x 4,096-bit pixels and
requires an update rate of 600 MHzway beyond the reach of currently available CRTs, RAMs or video 01 A converters. Instead, the state of the art now has
designers grappling with 2,048 x 2.048
resolutions and a 360-MHz update rate.
This level of display clarity must become affordable for critical applications.
Air traffic control systems, for instance.
could benefit from easier-to-interpret
high-resolution displays. In military systems. large sets of data should be displayed very clearly so as not to fatigue
the eyes and give rise to human error.

In high-performance workstations. only
high-resolution displays can do justice
to the detail of intricate drawings.
As always, the success of such systems hinges on the price'performance
ratios of their constituent ICs and CRTs.
A 2.048 x 1,500-pixel or 2.048 x 2,048pixel color graphics display typically involves some type of static RAM for the
color lookup table, coupled with video
D/A converters, all running at speeds
ranging from 250 to 360 MHz. Today,
the only technology that can provide
these speeds at all economically is ECL.
Even so. ECl components generally
sell for twice to three times as much as
equivalent TTL functions. Clearly then.
improved and lower-cost components are

essential for the next generation of highperformance displays and other pipelined
data systems.
That's where the two new Brooktree
ECl chips come in-the Bt402 video
RAM with its maximum cycle time of
4 ns and 256 x 8-bit density and the
compatible BI109 triple 8-bit O/A.

Reprinted From ELECTRONIC PRODUCTS Magazine - September 16, 1986
645 Stewart Ave., Garden City, NY 11530 • @ 1986 Hearst Business Communications, Inc. -::::.

3 -11

•

Article Reprints

3 - 12

Broddree®

Article Reprints

•

3 -1.3

Article Reprints

DESIGN ENTRY
125-MHz CMOS IC supplants
numerous ECl parts, drives
million-pixel color CRTs
A graphics subsystem on a chip cures high-speed
headaches by packing three 4-bit d-a converters,
two palettes, two interfaces, and more.

he high-resolution
images and rainbow
of colors displayed
by today's most advanced
graphics systems represent
a difficult and complex job
of engineering. As definition and number of shades
soar, so does the data rate,
and with it climb the problems of designing with discrete ECL components. Although several integrated
circuits have simplified laying ou t and assem bling
graphics systems, none has
explicitly aimed at eliminating the intrinsic troubles of working with powerhungry ECL circuitry.
Mike Brunolli, Keith Jack, and Dale Roark
Brooktree Corp.
Mike Brunolli designs ICs for Brooktree, San Diego,
Calif, and specializes in fast CMOS memories. He received a BS in electrical and compnter engineering
from the University of California at Davis.
As an applications engineer at Brooktree, Keith Jack
does product planning and works with customers. He
holds a BSEE from Tri-State University in Indiana.
Dale Roark is a product manager for computer graphics chips, and plans long-term strategy. He earned a
BS in compnter science from the University of Utah.

Stepping into the picture
with just that purpose is
the first member of a
graphics IC family: the
Bt451 RAMDAC. The
CMOS chip operates at 125
MHz and consolidates the
functions of most, if not all,
the ECL components typically found in a high-performance graphics system.
It replaces 20 to 30 mostly
EeL parts and eliminates
the board layout, power
supply, and dissipation
problems inextricably
linked to that high-speed
technology. It also solves
the interface problem of
ECL-to-TTL translation
that plagues graphics (see "In Pursuit of the Perfect
Picture," p.134).
Specifically intended to form the core of a highperformance display (1280 by 1024 pixels) for a
graphics workstation, the chip contains a 256-color
dual-port palette (look-up table), an overlay palette,
and a trio of 4-bit digital-to-analog converters that
are noteworthy for their low glitch energy and high
linearity (ELECTRONIC DESIGN, June 27, p. 37). In addition, it carries logic for masking bit planes and
blinking colors, plus a microprocessor interface.
Because the chip's high-speed circuitry has multi3 - 14

Article Reprints
DESIGN ENTRY
Cover: 125-MHz graphics chip
plexed inputs, all but two of its I/O signals can function at 25-MHz TIL levels. Only its differential clock
input must meet the 125-MHz requirement for high
resolution, and even that signal is powered from a
TIL supply. As an added benefit, the chip is highly
testable, with critical sections available to the system bus. Finally, the 84-pin (pin-grid array) device
runs on a single dc supply of 5 V and consumes no
more than 1.5 W.
Blossoming graphics

As computer graphics and imaging systems have
evolved from medium-resolution displays of 512 by
512 pixels to high-resolution screens that resolve
1280 by 1024 pixels, data rates have jumped more
than an order of magnitude, from 10 MHz to over 100.
At the same time, color capability has blossomed
from simple schemes that delivered 8 hues and called
for 3 bit planes to complex designs that furnish 256
shades, employ 8 bit planes, and incorporate color
palettes and 125-MHz d-a converters.
At the latter level of performance, designers have
had to reach for expensive and difficult-to-use ECL
Clock

Clock

Blank

Voo

devices to build much of a system's display-refresh
and special-effects circuitry. TTL-compatible memories and d-a converters are simply too slow. Even
though ECL may add up to only a small part of the
overall system, it requires a separate -5.2-V dc power supply and TTL-to-ECL level-shifting components. Also, special layout rules must be followed and
steps must be taken to dissipate heat. And despite
their speed, ECL RAMs must be doubled up and multiplexed to match the fastest output rates. Because
they are not dual-ported, image updating and refreshing must be carefully juggled to avoid clashes.
To solve these problems, the CMOS graphics chip
supplies the high-speed functions that are typically
reserved for ECL components (Fig. 1). Its multiplexed TTL-level ports simultaneously accept either
four or five pixels, each comprising eight bits of color
and two of overlay data. Consequently, the chip's
dual-port color palette of 256 by 12 bits paints frames
of up to 256 colors from 4096 possible hues. The
4-by-12-bit overlay palette, also dual-ported, offers
four options for supplementing the original image
with messages and cursors. In addition, read- and

Digital
ground

Analog

Full~scale

ground

adjustment

V ref

Compensation

40
Pixel Data

~+-I-.o

lOB

Overlay Data

gus control
logic

R/W

1. Included among the major functional blocks of the Bt451 RAMDAC are three 4-bit d-a converters, TTLcompatible pixel input latches and multiplexers, and read- and blink-mask logic. On-chip pipelining ensures
operation at 125 MHz and CMOS technology guarantees dissipation of 1.5 W.

3 - 15

•

Article Reprints

blink-mask registers give designers the ability to
control the pixel data on a plane-by-plane basis. On
the output, three 4-bit segmented d-a converters supply a signal compatible with RS-343-A specifications
to directly drive a monitor through doubly terminated 75-Q coaxial cable.
By reading the information for several pixels at a
time and multiplexing it internally, the chip cuts the
125-MHz data rate of the frame buffer to an input
rate of 25 MHz or less. Within the chip, the signals
are pipelined at each stage. If an 8-ns pipelined
throughput within a particular stage is not possible
with conventional techniques, then extra measures
are taken. In the palette, for example, these measures include high-speed sense amplifiers and individually dual-ported RAM cells. Consequently, the
chip sustains the 125-MHz pixel output rate needed
for high resolution.
The internal multiplexers can be programmed to
operate at either 5:1 or 4:1. As a result, the Load Control signal (LD), which latches all video data on its
rising edge, runs at I/s or 1/4 of the pixel clock rate
(Fig. 2).

Video data consists of color, overlay, blank, and
sync inputs, which all run at 25 MHz. The clock input
is the only external signal that runs at the full pixel
data rate of 125 MHz. It consists of the complementary ECL signals, Clock and Clock. The phase
relationship between the two clock signals and LD is
automatically adjusted by the chip so that the setup
and hold times of the video data can with confidence
be made relative to Load Control only.
Minimized with multiplexers

The chip's programmable multiplexers let designers build a frame buffer with the minimum number of memory chips. When 5:1 multiplexing is
picked, the external video frame for a display of
1280 by 1024 pixels can be assembled from just five
dynamic RAMs (256k by 1 bit apiece) for each bit
plane. Alternatively, the 4:1 setting creates a
1024-by-1024-pixel display from four such RAMs.
Static column and dual-ported video dynamic RAMs
are both suitable candidates for a frame buffer, provided that they meet the 25-MHz data rate.
Once the pixel data is latched into the chip, subse-

Pixel and

overlay data,
Sync, and Blank

"""'f"'''''

2. In the video 1/0 timing, pixel and overlay data, as well as the Sync and Blank signals
are loaded by the rising edge of the 25-MHz LD input. Internally, the pixel data is multiplexed and processed at 125 MHz; Palette pixel data generates the analog outputs for
red, green, and blue (lOR' 100' and loa).

3 -16

Article Reprints
DESIGN ENTRY
Cover: 125-MHz graphics chip
quent clock cycles move it first to the read-mask logic
and then to the blink-mask logic on its way to addressing the color palette. In the read-mask logic, a
register's contents is ANDed with bit-plane data to
determine if a particular plane will address the color
palette. In that way, logical layers can be selectively
turned on and off. Such control is useful in applications in which particular logical layers are associated
with physical bit planes, as in circuit and IC design.
Similarly, the blink-mask register specifies which
planes will blink at one of four rates selected by a
command register. An internal counter, which is incremented by the video blanking signal, determines
the base frequency from which the blinking rate is
calculated. '

A color palette is an essential part of a high-performance graphics system, enabling all pixels of one
color to be changed to another without updating the
bit map. In the graphics chip, the aforementioned
eight color bits and two overlay bits respectively
address one of 256 12-bit options in the color palette
and one of 4 12-bit options in the overlay palettes.
The 12 bits of color information selected from 1 of the
2 palettes are then pipelined to the three 4-bit d-a
converters.
Two modes exist for selecting the four overlay addresses. The first includes the color palette as a possible choice; the second does not.
In the first arrangement, the initial overlay address is ignored, and the two Overlay Control bits

In pursuit of the perfect picture
A range of challenges, most having to do with high
data rates, confronts designers of high-resolution
bit-mapped graphics systems. For instance, the output data path of a 1280-by-1024-pixel color display
demands a searing 125-MHz clock rate. The requisite high-speed circuitry, which mixes ECL and TTL
components, makes board layout critical, since care
must be taken to prevent clock noise and hold down
propagation delays.
High-speed parallel-to-serial conversion is a must
if the 8-ns a pixel video-data rate demanded by high
resolution is to be met. The frame buffer for a bitmapped system is typically implemented with dynamic RAMs because it needs so much memory.
Conventional dynamic RAMs, however, have relatively slow cycle and access times. Consequently,
video data must be read from the frame buffer in
parallel and serialized by ECL components. That
need to serialize data has given rise to the video
RAM, essentially a dynamic RAM with an on-chip
shift register. All the same, to achieve a 125-MHz
pixel rate still requires ECL multiplexers, TTL-toECL interface logic, and control circuitry.
Although only a small portion of the video-timing
logic may need to operate at the pixel clock rate, it
still needs fast circuits to control the CRT monitor
and to refresh the display and the frame buffer's
dynamic RAMs. Typically, the logic must also arbitrate accesses to the frame buffer by the system
microprocessor and various memory refresh operations. Depending on how the frame buffer's memory is configured, logic may be needed to translate the
address and data signals' as well.

Creating cursors and overlays is another troublesome task in bit-mapped graphics that frequently
necessitates ECL interface components. There are
several ways to add cursor and overlay information
to the video data, but whatever the approach the end
result must modify the displayed colors pixel by
pixel. Software solutions, additional bit planes, and
dedicated hardware are three possibilities. Also,
cursor and overlay information can be merged with
the video data at the input to a color palette RAM
by addressing additional memory or dedicated locations within the palette. Alternatively, that data
can be added at the output of a palette by forcing
the d-a converters to a specific color.
Since it must operate at the pixel-data rate, the
color palette itself is a natural for ECL and ECL-toTTL translation logic. Even if multiple palettes are
multiplexed to avoid working with such logic, ECLto-TTL translation is still required at the color
palette's interfaces to the d-a converters and to the
system microprocessor.
The output of the color palette is fed to three
high-speed d-a converters, one each for driving the
CRT's red, blue, and green color guns. Depending on
the system, a pixel has four, six, or eight bits dedicated to each d-a converter, and therefore to each
color. Operating at up to 125 MHz, the converters
need an ECL interface as well as other high-speed
circuitry to drive terminated coaxial cable. Moreover, each converter must generate signals that are
compatible with RS-343-A, exhibit low glitch energy, and produce low differential and integral linearityerrors.

3 -17

•

Article Reprints

(aLl and OL 2 ) select the second, third, and fourth
overlay addresses. When the overlay bits are set at
00, a pixel's color is picked by the eight bits addressing the color palette; when the overlay bits are set at
01, 10, or 11, the pixel color data is ignored and the
color comes from overlay location one, two, or three,
respectively. In addition, the timing of the overlay
control bits matches that of the pixel data. Thus the
source of the control bits can be either extra planes in
the frame buffer or cursor- and character-generation
circuits.
Attention getter

The second mode ignores pixel port data altogether and accesses only the overlay palette. Specifically, any existing image is removed and the first
overlay address becomes the source of the background color. The mode is invoked by setting a
command-register bit. It is useful when messages
that need immediate attention must be flashed to the
screen, such as the panic messages displayed before a
system shuts down. It also is handy for developing
graphics software. In the latter case, the graphics
source code for an image can overlay the image itself.
To do so, an external character-generator chip set is
attached to the overlay port and accessed directly by
the system microprocessor.

Regardless of the source of the four bits each of
red, green, and blue color data, their target (once every clock cycle) is the same: three 4-bit d-a converters. Each converter has a segmented architecture, in
which a sophisticated decoding scheme routes current either to an analog output or to a return line.
The architecture eliminates transients that typically
result from switching current sources on and off.
Steering identical current sources in that way
guarantees monotonicity and low glitch energy. Further, temperature and power supply variations are
stabilized by an internal op amp. Differential and integrallinearity errors are guaranteed to be less than
± 1116 LSB and ± 1/8 LSB, respectively, over a temperature range of -25° to +S5°C.
The chip's video timing signals, Blank and Sync,
also control the converters' current sources and are
TTL-compatible. Asserting Blank overrides the converters' inputs and forces their outputs to the blanking level (Fig. 3). Sync, which switches off the current
of the green converter only, does not override any
data inputs and so should be asserted only during the
blanking period. If Blank and Sync are not used, they
should be connected to Vee through pull-up resistors.
On the system side, the chip's microprocessor interface eliminates the need for external address and
data multiplexers. Eight data bits carry information

Standard RS-343-A levels

Red, Blue

Green

(mA)

(V)

(rnA)

19.05

0.714

26.67 1.000

(V)

1.44

0.054

9.05

0.34

+ - - - - - + - - - - f - - - - - - - - ~~~~~~~:I

0.00

0.000

7.62

0.286

+------L.-.,--.-....I---------- Blank level

0.00

0.000

.L-_ _ _ _ _ _--'-_'--_ _ _ _ _ _ _ _ _ Sync level

3. The graphics chip conforms to the RS-343-A video standard, and is able to drive
doubly terminated 75-0 coaxial cable directly. The d-a converters, which feature a
fully segmented architecture, produce the video output waveforms by sourcing
current into an external load.

3 - 18

Article Reprints
DESIGN ENTRY
Cover: 125-MHz graphics chip
between the graphics chip and a processor, and control inputs Co, C}, and CE specify the interaction.
Among the possible interactions are reading or
writing to a palette, and accessing control registers
(Fig. 4).
When the microprocessor is reading or writing to a
palette, the chip's address counter holds the address
of the specific palette entry and selects whether it is
red, green, or blue. The counter's 8 MSBs use binary
values and choose the specific entry. The 2 LSBs work
in modulo three to access one of three color registers.
For example, when a new color is being written to the
palette, its red and green values are temporarily
stored in two of the registers, so that during the write
cycle for its blue value, all 12 bits of color information
can be written to the palette at once. Conversely,
when the microprocessor is reading the color values,
it accesses a palette location and the red, blue, and
green data is put onto the 8-bit data bus 4 bits at a
time.
Not only is the chip dual-ported by virtue of its separate pixel and microprocessor ports, but every RAM
cell of a palette is dual-ported as well. Therefore, if a

palette location is updated (through the microprocessor port) at the same time that it is being read
by the pixel port, the maximum disturbance is held to
a single pixel. Subsequent reads are guaranteed to
produce the updated information. That feature eliminates the color streaks that frequently occur when a
palette entry is updated asynchronously to the display-refresh timing. It also does away with the circuits needed to restrict updating operations to the
retrace time.
Inslant access

Another valuable feature obviates the need for
extra test circuits to verify that the chip and its surrounding system are operating as intended. Usually,
the high speed of the video output, compared with
that of the system microprocessor, requires an intervening layer of multiplexers to diagnose any
probems between the bit plane and the output converters. In contrast, all of the chip's internal test registers, as well as the palettes, are accessible at all
times through the microprocessor port. By writing to
one of several test registers, the processor can in-

Read cycle (00 -0 7 )

Write cycle (Do-D7)

4. The graphics chip is designed to appear like a typical peripheral device to a microprocessor, which can read to or write from all internal registers and RAM locations at
any time. The dual-ported color palette lets the processor access and modify color information without significantly disturbing the displayed image.

3 - 19

•

Article Reprints

to read the frame buffer.
The video timing logic is responsible for generating the differential clock signal, LD, Sync, and
Blank. It must also arbitrate access to the frame
buffer and refresh the dynamic RAMs, if they are
used. Finally, it must generate the cursor if one or
two additional frame buffers are not allocated for
that purpose. As noted, only a small portion of the
video logic must run at 125 MHz.
The logic can send out up to five consecutive cursor
pixels at 25 MHz and can then connect directly to the
graphics chip's TTL inputs. To do that takes only two
ECL devices: a 125-MHz oscillator and a 3-bit counter, which divides the oscillator's frequency by 5.
Such a small number of ECL chips can be connected to the system's 5-V dc supply, instead of a
separate -5.2 V dc source. The graphics chip is
designed to accept differential clocks generated
that way. 0

dividually read each output converter's input.
Applications typically call for a minimum of interface logic. As mentioned, the chip requires five dynamic RAMs for each plane of a display comprising
1280 by 1024 pixels; four dynamic RAMs for 1024 by
1024 pixels. Up to 10 planes are possible: eight for color and two for overlay information. The RAM outputs drive the chip directly (Fig. 5).
The same outputs also drive the data bus, letting
the microprocessor read the buffer memory. If
25-MHz dual-ported video RAMs are used, the processor should be able to access the frame buffer about
98% of the time. If static column RAMs are employed, however, the processor should access the frame
buffer only during the retrace interval to avoid disturbing the display. Alternatively, double-buffered
bit planes can be used.
The advantage of using static-column RAMs for
each bit plane is that the memory row refresh cycles
occur only during the display's horizontal retrace intervals. Consequently, during the display time, video
data can be read from the frame buffer as fast as the
RAM can supply it. As long as the memory has a
maximum static-column access time of 40 ns or less,
no external multiplexers or shift registers are needed

Clock. Clock

Video-timing

logic

Control Address Data

Frame buffer memory,
1280 X 1024 X 8 blls
(40 256k XI
dynamic RAMs)

Cursors

BI451 RAMDAC

Microprocessor
Interface

RJYi.
CE COt C 1 0 0 -0 7

f-o Red

f-o Green

f-o Blue

.. 2
Dala
A ddress
Control

5. In a typical system built around the graphics chip, most of the highspeed Eel components are eliminated. The frame buffer and videotiming logic connect across 25-MHz TTL interfaces. Only the clock line
and the chip's internal circuitry (highlighted) run at the 125-MHz pixel
rate.

3 - 20

Article Reprints

DESIGN ENTRY
ELECTRONIC DESIGN EXCLUSIVE

Octal DAC chip's interface
meets processor bus directly
Jeff Teza, Keith Jack, and Chuck Stanley
Brooldree Corp., 9950 Barnes Canyon Rd., San Diego, CA 92121; (619) 452·7580.

Cutting the number of components in a system
down to the absolute minimum is the goal of every
design engineer. As chips have evolved from discrete units, through small- and medium-scale integration to the present large- and very large-scale
circuits, the number of parts needed in any system
has fallen sharply. Integration of components also
lets computers control analog outputs through multiple digital-ta-analog converters.
Applications of this useful arrangement include
the generation of programmable dc reference levels and waveEight DACs arranged
forms for electronic test
in four symmetrical
equipment; waveform
pairs get instructions
generation for multistraight from a microchannel control sysprocessor, simplifying
tems; and provision of
multiple waveforms for
designs with promusic synthesizers and
grammed signals.
pattern generators.
Such hardware applications have until now been handled by dual or
quad 8- and 12-bit d-a converters-the highest
density commercially available in that kind of chip.
However, these dual and quad circuits did not always interface easily with microprocessors to generate programmable signals. Integration has now
moved forward again, however, in the development
of the industry's first monolithic octal 8-bit d-a converter chip. Fabricated in CMOS, the Btl 10 is
TTL-compatible and connects thr~ugh a normal
bus directly to standard microprocessors, without
any peripheral interface circuitry-which greatly
simplifies system design.
The new chip includes an on-board voltage reference, and needs only a few passive components to
decouple and set up its full-scale output. (The designer has the option of using an external reference
voltage.) The chip's eight converters are set out in
pairs for tracking and thermal symmetry. The
members of each pair track each other closely,
Reprinted from ELECTRONIC DESIGN - Septembe, 4, 1986

which makes possible the construction of d-a converters with more than eight bits of resolution.
The chip's usefulness derives from its unusual
internal architecture (Fig. I). Eight bits are routed
through an address-controlled multiplexer into one
of the latches on the rising edge of the Write control
input, WR. The latches in turn statically feed the
selected converter's decoder. Each converter has 63
major on-chip current cells and three minor current
cells (Fig. 2). The major cells connect with the
most-significant 6-bit decoder, the minor cells with
the least-significant 2-bit decoder. With a 4: I current ratio, the cells' outputs add up to the total current output for any given state.
INTERNAL ARCHITECTURE

Each pair of converters lies symmetrically on
either side of the chip's axis, one being the mirror
image of its partner. This arrangement enhances
tracking and matching as a function of variations in
the manufacturing process-any variation affects
each one of a pair in exactly the same way. The
chip's design and architecture trades off the size of
the chip against differential and integral nonlinearities.
Monotonicity is crucial to the operation of any
d-a converter. If a converter chip is truly monotonic, its analog output signal increases with any
increase in the input binary code. The Btl 10 main-

3 - 21

•

Article Reprints
ANALOG TECHNOLOGY

provides a stable reference voltage to drive each pair of
converters.
Each of the BtllO's eight converters offers ± I-LSB
differential and integral non-linearity at temperatures
from 0° to 70°C. Power dissipation is typically 150 mW
at a IO-MHz update rate, far less than for bipolar and hybrid d-a converters. The chip features typical full-scale
converter-to-converter matching of 2% between all eight
converters, and 5-ppm tracking between any two pairs.

tains its monotonicity and low glitch energy through identical current sources and by current-steering their outputs. While ladder-type converter designs depend for
their monotonicity on precision resistors with ratios held
to tight tolerances, the segmented architecture of the
Bt II O's eight converters does away with any need for such
precision. The converters route their bit currents to either
lout or AGND through proprietary decoding networks,
which perform a "thermometer" type of decoding and increase the converter's output by one LSB as its input increments in binary.
The BtlIO's on-chip voltage reference is a conventional
bandgap design supplying a 1.2-V output with a typical
50-ppm drift as temperature varies. The low-offset internal amplifiers that set up the full-scale output are similar
to those used for precision op amps. The amplifiers are
unconditionally stable and their low output impedance
Vref

l!1

OUTPUT LOADING

The output current source of each converter is designed
to drive a virtual ground and provides a maximum load
capacitance of 20 pF. The output impedance has a relatively flat characteristic from 0 to 10 MHz for driving op
amps. When feeding into a 50-0 resistive load with lO-pF
capacitance, the 10-ns maximum output rise/fall time is

v's, compensation

loutt

lout5

Full-scale
AdjuSt3

Full-scale
Adjust,

Compensation3

Compensation,

lout 6

101.112

IOU17

IOUl3

Full-scale
AdjuSt4

Full-scale

Adjust::!

Compensation4

Compensation2

I"""

lOUIS

1. The 8t110'$ eight d-a converters are arranged In
lour pairs lor close tracking and thennal symmetry.
The converters connect- directly to a standard microprocessor bus Without any need lor extemal perlpherallnterface circuitry.

2. Each d-a converter In tne 8t110 uses a current
source scheme lor decoding, with 63 major current
cells connected to the mosl-slgnillcant 6-blt decoder
and three minor current cells connected to the leastslgnillcant 2-bil decoder.

3 -22

Article Reprints
faster than that for many commercial op amps.
Converter-to-converter crosstalk, important when the
Bt I 10 generates several independent precision voltages, is
typically - 46 dB at a 200-kHz update.
The chip addresses any of its eight converters by incorporating a TTL-compatible microprocessor interface
with a bidirectional 8-bit data bus (Do 0 7 ), Chip Select
input (CS), Read input (RO), Write input (WR), and
three bits of address data (Ao-A,). Hitching the chip to
an I ntel or Moturula microprocessor is easy; the microprocessor addresses the converters directly, as though the
chip were a memory-mapped device (Fig. 3a).
When loading data into anyone of the converters, the
microprocessor operates just as though it addressed a
memory location and wrote a data byte to it. Each converter has its own address and can be loaded independently, allowing the microprocessor to manage up to eight

analog channels at once, and to change the status of all the
converters with only eight writes.
The microprocessor can also read back the input to the
converters, and thus need not store copies of those inputs
in its memory. The chip can be loaded in 80 ns-made up
of 30 ns address setup, 25 ns WR active, and 25 ns WR
high (Fig. 3b). Settling time for the converters is 100 ns.
ANALOG INTERFACING

The eight converter outputs (I",,, I , ) are high impedance current sources providing up to I mA with an output
compliance of - 1.0 to + 1.2 V. An external op amp can
be connected to the chip's outputs to provide any higher
voltages and limit output speed. A faster op amp can
create problems, since the user then needs experience in
high-frequency design in order to avoid parasitic oscillations in the circuit, along with problems caused by poor
Transimpedance amplifiers

r-------,

I
I

1-0
1-0
1-0

lout 2

Btll0

octal
a·bit DAC
Ground

10Ul 3

lou! 4
lout 5

1-0

IOU16

1-0

lout 7

(

Ferrite bead

)

lout 8

1-0
_______J1-0

Analog ground plane

bUS:i:;;;;~SF±::::::::::

Microprocessor
control
Microprocessor
data bus

Microprocessor address bus

(a)

30 ns

50 ns

.I.

~
RD.WR

WR active 25 ns

"'--

25 ns
WR high

40 ns
0 0 -0 7 (Read)

0 0 -0 7 (Write)

20 ns

15 ns

I I

loul 1-8

Timing intervals not to scale

(b)

3 - 23

3. A microprocessor addressing the 8t110 treats it like a
memory location. Each d-a
converter has its own address and can be loaded
with data independently (a).
Loading can be accomplished in 80 ns, the limiting
cycle consisting of 30 ns
address setup, 25 ns WR active, and 25 ns WR high (b).

•

Article Reprints
DESIGN ENTRY • Oclal IC DAC

ANALOG TECHNOLOGY

layout of the components and the wiring.
Among op amps that perform well with the Btl I 0 are
the HA-2539 and HA-5033 for fast settling time and
wide bandwidth, the 1435 for medium performance, and
the LM318 for a good compromise between speed and
bandwidth at less than I M Hz. Most op amps with acceptable offset drift and stability are suitable for dc applications. Output to a maximum of about ± I V can also be
achieved by terminating the Bt I 10 with a resistor.
ON-BOARD REFERENCE

The on-chip voltage reference (V cor 001) can supply a
stable voltage to the V"r i" input over a specified temperature range. This reference, along with a resistor to ground
on the Full-scale Adjust pin, sets the full-scale output of
each pair of converters. The resistor value is determined
as follows:
R

,,'

= 1000 (V'''i")
(1001)

where R", is in ohms, V cor is in volts, 10"' is in milliamperes.
If more than one BtllO is used, the Veer 0"' of one can
drive up to three Veer i" inputs of the others. Although
the Bt II O's on-chip reference is adequate for most
applications, an external 1.2- V reference such as the
LM385Z-1.2, with a drift of no more than 50 ppm, will
improve stability across variations in temperature.
Each pair of converters shares a reference amplifier
(Full-scale adjust 1-4) that controls their output current.
Because of the close tracking within each pair of con-

verters the chip can be configured for a range of requirements. The close tracking is especially important when a
pair of converters is to function as one high-resolution
unit, or is used as an a-d converter with a successiveapproximation register.
The Bt II O's speed and high level of integration make it
ideal for multi-DAC applications. Because the chip can be
updated to 10-MHz, disk-drive testing-which requires
millisecond or microsecond timing waveforms-is a natural application. A disk-drive tester with a Btl 10 can generate such analog waveforms as stepper pulses and multifrequency-modulated data signals, and can simulate the
necessary timing signals.
MULTI-DAC DESIGNS

An engineer designing an analog I/O board for data
acquisition or control will also find the Bt I \0 useful. The
chip economically adds eight analog outputs to a printed
circuit board. It takes up little space on the board, and its
built-in microprocessor interface connects handily with
the board's bus.
In the design of programmable function generators, the
chip can produce the necessary sinewaves, squarewaves,
and nonlinear functions. Greater than 8-bit resolution is

Ao-A,~ r---;==~---;::::::=::::::'--=-;::::=~I
WR

2.Sk

4. Two DACs on the 8t110 can serve as a window comparator and provide high-low threshold
voltages. Output is high inside the window and low above the high limit or below the low limit.
One practical application for this circuit is as part of a pin receiver card in automatic test
equipment. where a matched pair of converters determines the threshold limits.

3 - 24

Article Reprints
often needed in such cases, and can be achieved by adding
the outputs of two pairs of converters. The scheme has the
added advantage-of reducing the even-ordered harmonic
content of any sine or cosine wave generated by the chip---similar to the harmonic reduction from analog push-pull
amplifiers.
A digital potentiometer based on the Bt II 0 will also
show significant improvement in performance over mechanical devices, since the dirt, wear, and other problems
affecting mechanical potentiometers is eliminated. Substitution of d-a circuits makes calibration of voltmeters,
oscilloscopes, sig.1al generators, and similar equipment
fully programmable.
Where, for example, a potentiometer is used as a voltage divider, an 8-bit converter can provide a linear 255:1
voltage-control range-enough to be a fine adjustment
for many linear functions. Using the Btl 10, any adjustment takes place entirely under the control of the microprocessor. Although a d-a converter is more expensive
than a potentiometer, the extra cost is made up in increased system reliability, simplified operation, and lower
assembly costs.

ditional circuitry may be needed to null any offsets, but
the fine converter can be loaded with binary values in order to trim the voltage output and achieve 12-bit accuracy
during calibration cycles. The BtllO's paired d-a converters make possible a stable 12-bit converter over a
range of temperatures. 0

Jeff Teza is Brooktree's director ofproduct marketing.
A cofounder of the company, he was its first design engineer. He holds a BEE from State University of New
York at Stony Brook, Long Island, and recently graduatedfrom the University of California, San Diego, executive program for scientists and engineers.
Keith Jack joined Brooktree a year ago as an applications engineer after experience designing microcomputer systems and VLSI with Burroughs and Rockwell
International. He holds a BSEE degree from Tri-State
University. Angola, Ind.
Chuck Stanley is Brooktree's applications engineering manager. With 14 years experience in integrated
circuit and hardware design, both digital and analog,
he holds a BEE from Georgia Institute of Technology,
Atlanta.

AUTOMATIC TESTING

Generating multiple de voltage levels and/or analog
waveforms for automatic test equipment (ATE) is something the Bt II 0 does well. The close tracking and matching between the chip's individual converters make it possible to program high-low-level limit comparators in ATE,
with repeatability over time and variations in temperature
(Fig. 4).
Using the chip to build four 12-bit reference d-a converters gives the system designer important economies in
integration. In the testing of Ies or printed-circuit boards,
dc reference levels (logic-high and logic-low) must be
generated to test the device's input. In this type of automatic test equipment application, 12 digital bits are
often needed to obtain 6-m V resolution over a ± 12-V
range.
During a power-up check of hardware for automatic
test equipment, the Bt II 0 can be tweaked as necessary to
calibrate hundreds of circuits against a single a-d reference circuit. When resolution drifts away from the reference level, adjustment of the converter input involved will
yield the correct 12-bit value through direct writes from a
microprocessor.
One Bt II 0 can also provide four calibrated 12-bit references (Fig. 5). The coarse d-a converter creates 256 major steps, all filled by the fine converter (fine d-a current is
resistively split by the ratio of two resistors tied to the op
amp's negative input). The resistor ratio forming the current divider should be chosen to bleed current into the op
amp's negative input.
This current level is directly related to the amount of
data overlap between the coarse and fine converters. Ad-

•
5. When the B1110's matched pairs 01 d-a converters
are teamed up, each pair can serve as a 12-bil reference converter, sharing four overlapping bits. The
eight LSBs contribute to the fine adjust and the eight
MSBs to the coarse adjust. One chip can thus provide four calibrated references,

3 - 25

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3 - 26

Article Reprints

•

3 - 27

Article Reprints

DESIGN INNOVATION

Video palette raises color ante
to 1024 separate hues
Thanks to a CMOS RAM d-a converter, a palette
of 1024 colors alternates with one supplying 256
colors to yield true color at 135-MHz speeds.
NICOLAS MOKHOFF
Imagine having 1024 different :;01ors to choose from to paint a computer-generated object on your
screen. Now visualize another object within a window of that display-defined by a separate 256color palette. To top it off, consider
the}mage quality when you operate
the tl\vo palettes at 135 MHz. That is
what you can expect in the first of
Brooktree's new crop of CMOS
RAM digital-to'analog converters
(RAMDACs).
With the Bt461 converter, the
company's designers have considerably improved on the previous part,
the 84-pin Bt458 (ELECTRONIC DESIGN, June 26, 1986, p. 131). In
comparison, the Bt461 converter,
housed in a 132-pin grid array, has
two more address inputs that expand the addressability of the primary color palette to 1024 by 8 bits;
five new address inputs for the alternative palette of 256 by 8 bits; and
another five new address inputs for
a larger (32 by 8) overlay palette
(Fig. I).
This expansion carries a sacrifice,
however. While the earlier part had
three 8-bit d-a converters at the output stage, the Bt461 unit accommodates but one 8-bit converter. As a
result, when the 461 converter goes
to work as a single-chip in a monochrome system, only 256 shades of
gray are possible. In a color system
built with three Bt461s and 10
planes, though, 1024 colors can be
displayed out ofa possible 16.8 mil-

lion. And Brooktree has pumped up
the top clock speed to 13 5 MHz to
ensure a comfortablt; screen refresh
rate.
Future members of the converter
family will house three d-a converters to accommodate single-converter color systems. "The 132-pin grid
package was chosen to allow for future compatible RAMDACs," says
product manager Lauren Schlicht.
"Our current CMOS process uses
1.5-,..m design rules, but future
RAMDACs will be designed using
1.2-,..m rules, and later, I-,..m rules.
Those parts will be able to address
color palettes of up to 4096 by 8 and
incorporate three 8-bit converters in
the same I 32-pin package."

Meanwhile, the new converter's
features make possible sophisticated graphics in 1280-by-I024-pixel
images. Besides giving the user control over alternative palettes, the 8bit d-a converter also supplies a
third palette---a 32-by-8 color overlay. Thus, the designer can run
EGA graphics through the overlays
without interference from main
workstation graphics.
"We have found that users want
to design their graphics to best suit
their needs without worrying about
EGA," says Schlicht. "The 32-word
overlay color palette accommodates
the full 4 bits of EGA and still has I
bit left over for something like the
cursor display."
Often the graphics application
software chiefly generates and manipulates images in the frame buffer.
The system software is usually reponsible for cursor movement,
menu insertion and deletion, and
user messages, with minimal con-

ElectroniC Design. August 20.1987

3 - 28

Article Reprints
DESIGN INNOVATION •

Cover: RAM d-c converter

cern about the graphics image.
Using three to five additional bit
planes for overlays enables the system software to control user interface graphics independently of the
graphics image. Using 32 overlay
words (32 by 8 bits) gives the designer maximum flexibility for deciding
what should run through the overlays. Multiple-color cursors, text,
grids, and windows can be run
through the overlay ports and kept
separate from the main frame buffer.
The multiple pixel ports and internal programmable multiplexers
(3:1,4:1, or 5:1) enable TTL-compatible interfacing with incoming
data lines up to 45 MHz to the frame
buffer, while maintaining the 135MHz video data rate. The programmable multiplexers allow designers
to build a frame buffer with the fewest possible memory chips.
After considering user needs, designers came up with Bt461's two
switchable palettes, which are
aimed at the high-resolution graphics becoming more and more common in personal computers and
workstations. With two separate

palettes that can be switched on a
per-pixel basis, the designer can
control multiple windows with
completely different color palettes
(Fig. 2). In addition, true color (8bit) windows within a complete
graphics environment are possible.
PIXEL BY PIXEL

The 256-color palette can be used
for lookup table bypass by sending
data directly to the d-a converters or
can be used to correct the gamma
strength of a true-color input. Thus,
true-color input from a CD ROM or
another external source can be displayed in a window. Or users can
switch color graphics from the
frame buffer and CD ROM input
pixel by pixel. Alternatively, the
256-color palette can be used as 256
words of overlay as long as data is
multiplexed with regular pixel input
lines.
Another sought-after feature,
pixel panning, allows the user to
shift the data being displayed on the
screen. As the data is being output
from the frame buffer, the user
wants to display the subsequent pixels as if they were the first pixel out

of the buffer, thereby panning the
display. Using a multiplexed RAMDAC, where the Sync and Blank information is loaded every four or
five pixels, panning is difficult.
The Bt461, however, can be programmed to "slide" the Sync and
Blank signals. This information is
latched in the cycle before it is needed. Then the Sync and Blank signals
can occur after anyone of the four
or five pixels is loaded in the following cycle. This feature allows the
user to load Sync and Blank signals

Camp

[5
PLL

PO-Pg
lout

Alt

OLc·OL4
Sync
Blank

1. 8rooktree's single-channel RAM d-a converter contains three different color palettes from which a designer can extract 1024 colors from up to 16.8 million possible shades. A Pll output synchronizes multiple
8t461 converters with sub-pixel resolution.
3 - 29

Article Reprints
Cover: RAM d-a converter

DESIGN INNOVATION •

at any pixel-without operating the
inputs at pixel speeds.
Built into the Bt461 converter is
compensation for output skews
from the d-a converters, which
could cause inferior-looking graphics on the display. Most converter
manufacturers leave the skew problems to the system designer to solve.
The Bt461 supplies a phase-lock
loop (PLL) output, which is a positive-going current that can be pro-

2. In a system, window-management hardware would use the
higher order pixel address bits
(P9 and P8) and the five alternate palette select inputs to
choose between five unique 256
by 8 color palettes without reloading the color palette RAM.

ill

8t439

Sync chip

Oscillator

[j)

elK/elK

I
~esses
PO-Pg

Frame

'---

buffer

grammed to be active during Sync
or Blank. This signal can then genlock or synchronize clock signals
between chips or to an external sync
source, without having to strip the
Sync or Blank out of the Composite
Video out signal. This saves on extra
hardware and ensures a distortionfree analog output.
Brooktree is developing a separate clock-generator chip (Bt439) to
allow three PLL signals as inputs
and move the clock inputs to the
RAMDAC (Fig. 3). It will support
the3:l, 4:1, and 5:1 input multiplexing of the 461 converter, synchronize them to sub-pixel resolution,
and will optionallly set the pipeline
delay of the converter to eight clock
cycles. This synchronization chip
then, with the Bt461 converter, synchronizes the three-channel processors within one-quarter-pixel time
(about I ns at 135 MHz).
Sub-pixel synchronization is
suppported through the PLL output. Essentially, PLL gives a signal
to show the converter's amount of
analog output delay, relative to the
clock signal. The CMOS process
and the analog output delay variation from device to device makes

40 or

lo~

ill
2 or 4

Red

lD
elK/elK

PO- P9

8t461
RAM d·a converter

Pll

40 or 50

~
2

PO-P g

'--2

40 or 50

PO- P9

lout

Green

lD
elK/elK
8t461
RAM d·a converter

t
lD
elK/elK

Pll
lout

Blue

8t461
RAM d·a converter

Pll

3. In a color system buill around three 8t461 converters, 16.8 million
shades of color are possible. With 10 planes (10 bits per color) 1024
colors can be displayed simultaneously by having the pixel data inputs (PO-P9 ) tied to the three devices. A new sync chip (8t439) is expected to synchronize the d-a converter outputs to within a 1-ns skew.
3 - 30

this necessary. The Bt439 compares
the phase of PLL signals generated
by up to four Bt461s and adjusts the
phase of clock signals to each 461 to
minimize PLL phase difference.
Because the 461 is the first in a
family of software and pin-to-pin
compatible converters, Brooktree
designers have incorporated an
identification register on board that
allows each part to identify itself.
This helps accommodate future designs and software, which can utilize any member of the family. In
each system, the microprocessor
driving the 461 converter discern
the size of the palette and whether
the part is a single-channel or multiple-channel one. The ID register lets
the microprocessor determine the
type ofRAMDAC in use.
Just as with the company's other
RAMDACs, the 461 supports a
standard microprocessor bus interface, giving the microprocessor direct access to the internal control
registers and color palettes. Users
have two ways to write and read color data to and from the device. In
the normal mode, color data is loaded in each write cycle and is output
each read cycle. In the RGB mode,
color data is loaded during red,
green and blue write cycles and output using corresponding read cycles.
At the output video stage, a programmable setup of either 0 or 7.5
IRE (video output signal ratio)
opens the part up for European applications since the zero setup is required by the European PAL video
standard. The Bt461 generates a
RS-343A compatible video signal,
used by high-end workstations and
most PCs, and can directly drive a
doubly terminated 75-D coaxial
line, without requiring external
buffering. 0

Article Reprints

•

3 - 31

Article Reprints
COVER FEATURE

THE FIRST TRIPLE FLASH ANALOG-TO-DIGITAL
CONVERTER-AND THE FIRST WITH A LOOKUP
TABLE-JETS 8-BIT IMAGES AT 15 MHz.

IMAGING CHIP HOLDS THREE
15·MHz 8·BIT ADCs
FRANK GOODENOUGH
ost systems designed to digitally
capture video TV
images, be they
for PCs or for TV
studio special-effects equipment,
RAM
contain
lookup tables between their flash analog-to-digital
converters and their digital signal
processor. These RAMs perform
real-time data manipulation prior to
storing the data for processing or
analysis. Such manipulation includes
inverse gamma correction, contrast
enhancement such as thresholding,
data inversion, and creation of a nonlinear transfer function for the a-d
converter. In addition, most of these
systems employ not one but three
converters, one each for the red,
green, and blue signals. And many
systems must be capable of handling
multiple video and/or synchronizatiori inputs.
If you're designing such systems,
Brooktree, creator of the first triplecolor-palette digital-to-analog converter, or RAMDAC, has just made
your job easier. They've come up
with two host-controllable a-d converter systems on a chip. Dubbed
, . "image digitizers" by Brooktree, the
CMOS Bt251 and Bt253 are true
firsts. The 251 is intended for blackand-white applications; its cohort for
color.
At the core of the Bt251 lie two circuits: an 8-bit flash a-d converter caReptntad with permission ""'" ELEC11IONIC DESIGN - February 9, 1989

3 - 32

Copyrigh11989 VNU Business Publications. inc.

Broddree®

Article Reprints

COVER: 8-BIT, 15-MHZ
IMAGE DIGITIZERS
pable of sampling video signals be·
yond 6 MHz at more than 15 megasamples per second (MSPS) and a
256-x-8-bit RAM lookup table (Fig.

.IIT. 15-MHz IIC WlTRlOOIUP TUlE

1).

Synchl1lllil'

r------·--------- -----l

atiano.1 I

VID" o+-t-t-+-+--t
VIO, o-t--~H-.j
VIa, 04-----4'4----1
VIO, O+-----4~·1

~==;-',-----,

1. BROOKTREE'S Bt251 IMAGE DIGITIZING 8-BIT nash eonverler
sports an oo-ehip lookup table, a rour-ehannel video inpul mulliplexer, a de rererenee, and 1
SYDC stripper, all under conlrol or 1 h..I microproces..r.

RIPlf 8-11T.15-MHz FlaSH IIC

2, THE Bt253 COWR IMAGE DIGITIZER rrom Brooklree has Ihree 8-IIil,

150MHz nash anllor-\01liptal eonverters. Oulpul rO(lll&I, inpul multiplexer, SYDC siripper,
·Ind sil diptaHo-anlloc c.. verie.. are undcr h..l-microproc....r coolrol.

3 - 33

The Bt253, on the other hand, can
boast of having not one but three 8bit flash converters (Fig. 2). With
this chip you can grab red, green,
and blue video signals simultaneously. The flash trio is followed by output-format logic that lets you select
(through the host) 24-, 15-, or 8-bit
true-color or 8-bit pseudo-color data
formats.
A 24-bit true-color format uses all
8 bits from the three converters; 15·
bit true-color uses each converter's 5
most-significant bits (MSBs); 8-bit
true-color uses the 3 MSBs. In an 8·
bit pseudo-color format, an 8-bit
gray scale is produced by one converter and the colors are added by
the CPU.
Both of these chips hold enough
pc-board-size-slashing, power-cutting, design-time-trimming bells and
whistles to build a carousel-{!alliope
and all. The chips include such functions as input multiplexers, synchronization strippers, dc-restoration circuits, and an on-chip reference
which, with associated circuits, provides variable gain and offset. All
these features, like the lookup table
on the Bt251 and the formatting logic on the Bt253, are under host-pro·
cessor control.
According to Brooktree, these
chips were designed for imaging applications. However, many engineers designing multichannel, highspeed data-acquisition systems (especially for DSP applications) would
jump at the opportunity to get three
flash converters for $17.33 each; especially if the converters need less
than 200 mW each and together take
up less than 1.2 by 1.2 in. of pc-board
space. And at $39 each (a price that
includes the multiplexer and reference), the Bt251 flash converter
should find some general-purpose
applications too.
Performance figures for the two
chips are eye openers (see the table).
Let's start with the input multiplex·
ers. The Bt251 gives you four oneline inputs (VID,,-VID,,); the Bt253 a

•

Article Reprints
COVER: 8-BIT, 15-MHZ
IMAGE DIGITIZERS
pair of three-line (RGB) inputs
(RVID", RVID" GVID", GVID"
BVID", and BVID,). You externally
connect the multiplexer outputs to
the flash converter inputs (V in for
the 251, Ri", Gin, and Bin for the 253).
The input impedance of the converters is 1 M(1 shunted by about 15 pF,
leading Brooktree to recommend insertion of buffer amplifiers-such
as the EL2020 from Elantec of Milpitas, Calif.-between multiplexer
outputs and flash inputs. The amplifiers can also be used to adjust video
gain if required.
Because most standard TV video
signals are ac-coupled and must be
dc-restored with a clamp before digitizing, on-chip clamp circuits are provided for both devices. The Clamp
signal, a logical one, restores the video to the voltage on the Level pin,
which is nominally at ground. If the
video is dc-coupled, you can either
float the Level pin or connect it to the
video input; or you can wire the
Clamp signal to a permanent logicalzero point.

SIX DACs IN A Row
If you've been examining the
block diagram of these chips, you're
surely wondering what a flash a-d
converter is doing with a flock of onboard 6-bit d-a converters (only two

on the Bt251). Silicon costs money.
You'll notice that each d-a converter
takes an input from the chip's 1.2-V
bandgap reference, and that the d-a
converters' outputs are tied to the
Reference+ and Reference- pins of
the converters through external op
amps. These inputs drive, respectively, the top and bottom of their reference-divider resistance strings. Having variable, rather than fixed, references allows the converters to perform both gain and offset
adjustments.
Full-scale current from the d-a
converters is 10 mAo Thus a voltage
from 0 to 1 V is developed across the
op amp followers' 100-(1 input resistors. Resolution is 15 mV per leastsignificant bit. Most standard video
signals run from about 700 mV to 1
V. For maximum accuracy, the d-a
converter driving the top of the divider circuit should be programmed to
the value of the maximum expected
input voltage, but no more than 1.2
V.
The second d-a converter trims the
offset voltage at the bottom of the
divider. The top of the ladder should
be operated between 0.7 and 1.2 V;
the bottom between 0 and 0.5 V. The
minimum input video signal for 8-bit
resolution is 0.7 V. By modifying the
circuits between the output stage of

the d-a converters and the reference
divider, resolution may be increased
or decreased. For example, decreasing the value of the resistor between
a converter's output stage and
ground increases resolution. In
many applications, changing the reference voltage precludes the need
for a variable-gain amplifier for the
video signal.
For all practical purposes, the
CMOS flash converters' comparator
offset voltage must be repeatedly zeroed. With the exception of these
Brooktree converters, comparator
zeroing is automatically performed
every clock cycle. But with a proprietary Brooktree architecture, zeroing need only be performed when required. For example, when digitizing
TV or any other kind of raster-scan
signals, comparator offset-voltage
zeroing can be done during the retrace time of each line.

FLASHY STRIPPERS
For those working with one of the
standard TV video formats (RS-170,
RS-170A, RS-343A, RS-330, PAL or
SECAM), these chips provide synchronization strippers. Anyone of
the input lines to either chip can be
selected through multiplexers to be
fed into the synchronization stripper
circuit. Additionally, either of two

81251 AND 81253 SPECifiCATIONS

..........,

COnditions:REF+ = 1V. REF- = O,REFUnits

REF+ (top)
REF- (bottom)

Integral linearity error
Differential linearity error
Input resistance

Input capacitance
Input resistance

Reference divider resistance
Differential gain error
Differential phase error

Conversion rate
Multiplexer switching time

Full-power input bandwidth
Ams signal·to·noise ratio
Fin = 4.2 MHz
FIR = 4.2 MHz

Fin = 2.15 MHz
Fin = 2.75 MHz
Supply vollage
Supply current

REF+, T = O"to70·C, Vs = 4.75to52SV

TypIca'

0.7
0
Bits
l5Bs
l5B,
Mn
pF
n

"I;mlllll
1.2

0.7

Video input signal
VoHage on reference inputs

Resolution

~ ¥in $

Mlnl...um

1
·0

1.2
0.5
8
±1
±1

15
50

Clamp = logic 1
Clamp = logic 1
Clamp = logic 0

'000

'I,

Degrees
MHz

HIO

MHz
dB
dB
dB
dB
V

Sampling ,ate = 10.7 MHz

43
42

Sampling rate = 14.32 MHz
Sampling rale = 6.75 MHz
Sampling rate = 13.5 MHz

41
4.75

5
120

3 -34

5.25

Article Reprints

COVER: 8·BIT, 15·MHZ
IMAGE DIGITIZERS

separate synchronization inputs
(Synco and Sync j ) can be selected by
the Bt253's host. Thus synchronization information can be recovered
from one signal while a second signal
is being digitized-which is useful
for systems with red, green, blue,
and synchronization video interfaces.
The Synchronization signal from
the mUltiplexer circuit to the stripper

circuit is ac-coupled through a O.l-/LF
capacitor. An internal clamp circuit
ensures that the tip of the synchronization signal is at 1 V, regardless of
the amplitude or dc offset of the video signal. In this circuit, the video is
compared to 1.1 V-lOO mV above
the desired sync-tip level. As long as
the input signal to the stripper is less
than 1.1 V, its output will be a logical
zero.
The two flash converter chips support a standard digital microprocessorinterface (Do-D7' RD, WR, ~ and
Aj , plus A2 for the Bt253 flash converter). In the Bt251 flash converter,
an internal 8-bit address register, in
conjunction with Ao and A j , specifies
which control register or RAM location the microprocessor is accessing.
All registers and RAM locations may
be written to or read by the microprocessor at any time. The address register increments after each write cycle, facilitating read-modify-write
operations. D

3 - 35

•

Article Reprints

3 - 36

Broddree®

Article Reprints

IMAGING AND GRAPHICS

How to Drive
4-Mpixel
Displays

viation, medical instruments, and imaging beg fur color graphics displays with greater size and resolution
than what is offered by 19· 1280 x 1024 display subsystems. Although the graphics controllers and monitors that
support 4-Mpixel displays cost as much as $100,000, this price is
expected to drop. Sony, Hitachi, and Mitsubishi have demonstrated 26· to 30· color monitors capable of2K x 2K resolution.
In fact, Sony is already shipping its 30· monitor fur $40,000; in
18 months the price of that monitor will likely fall to just $10,000.
The impetus behind this decreased price and increased
availability is the fact that designers can now build controllersfur just $IO,ooo-using off-the-shelfECL and VRAMs. The use
of these standard parts removes the cost-prohibitive burden of using semicustom ICs in low-volume applications.

by Dana Wilcox, Wyle Plummer,
and Dennis Galloway,
Brooktree Corp.,
San Diego, CA

Controllers Head for the Sun
Many 2K x 2K display controllers to be introduced this year will

Designers can now build
2K x 2K (4 Mpixels)
color gmphics display
controllers with off-theshelfICs. Fast I-Mbit
VRAMs, multibit shift
registers, andDACscan
be. used to mpidly implement the back ends of
such controllers.

be based around the Sun-3/4 CPUs. These9U-based VME controllers can display full2K x 2K images with a number ofdifferent bit-planes. Controller specifications dictate design
characteristics. Both VLSI ICs and CMOS I-Mbit VRAMs must
be used to fit on a 9U board. To meet the $10.000 price constraint,
the controller must utilize off-the shelfICs.
Such graphics subsystems can be partitioned into fuur functional blocks: a front..:nd graphics processor, a frame buffer, the
back..:nd display circuitry, and the monitor. Figure 1 shows the
functional blocks of a graphics subsystem and the bandwidth
associated with each partition. Color and monochrome display
subsystems include the same basic blocks. In color systems,
however, more planes of memory are included in the frame buffer
and three DACs are needed to drive the RGB guns ofthe CRt.
In operation, an on-board graphics processor accepts commands from the host CPU, processes the commands, and controls the frame buffer and back..:nd circuits. The graphics processor is used to write image data into the display frame buffer.

figura 1: Build yourown2K IC 2K graphlcscontraller. Shown hera ora thefunctlonal partitions of a graphkssystem as _II as the bandwidth associated with
each partition.
.

3 -37

•

Article Reprints

3 - 38

Broddree®

Article Reprints
IMAGING AND GRAPHICS

Four 256K x 4-bit VRAMs comprise
DATA,
ADDRESS ANO
each plane ofthe buffer in a 4-Mpixel
CONTROL
display subsystem. Single bit-per-plane
111VIDE
~7~rrRAM
CLOCK
monochrome displays require a single
plane. Figure 3 shows a single plane of
I
memory and the frame-buffer organiza'7," ,PS ,1'4
"5",4",3",2
P.J.P2 ," ,I'll
1111,',D, ". '"
,
tion. Monochrome displays with grayscale as well as color displays require a
: 256K
:
14
frame buffer with multiple planes. Every
plane of memory includes I bit of infor'OM'
mation pertaining to each pixel.
Each plane of a frame buffer outputs a
1
I 1
I 1
I 1 S~~IE~~ER I
16-bit word (representing 16 pixels) on
every clock cycle. Here, shift registers
I I I I
I
on-board the 256K x 4 VRAMs are used
ATAOUT
22.SMHz D 5 D4 3 02
to output the data. A typical I-Mbit
VRAM can shift data at speeds up to 33
figure 3. A slngla plane'" memory Ina planar frame-buffer organlzatlan. CaIar
MHz. In a 4-Mpixel display, a 22.5-MHz
display cantralle,. require .uch frame buffer. ta be designed with multiple
clock provides the output bandwidthplane.. Each planewlll autputa l6-bltward for ....ry clackcyole.
multiplied by 16, the clock ultimately
provides the 360-MHz bandwidth required 10 drive a 4-Mpixel monilOr. One way 10 achieve this 16x
data and provides an 8: I bandwidth increase to 180 MHz.
multiplication involves splining the frame-buffer output inlO even
Likewise, four pairs ofS-bit shift registers handle even aJid odd
pixel inputs from the four frame-buffer planes dedicated to the
and odd channels. Bit 0 (of each word) represents an even pixel,
bit I ~presents an odd pixel, and so on. Figure I shows the data
overlay image.
flow split into two 8-bit streams and input into two separate
Off-tha-Shelf Ie Solutions
multitap video shift registers. The shift registers accept an 8-bit
parallel input and shift the data out I bit at a time. The 8: I ratio
Figure S shows a.hack-end 2K x 2K graphics controller design
provides an 8 x speed increase to 100 MHz in both the even and
implen\ented with two off-the-shelfVLSI ICs from Brooktree.-...
Bt424 and Bt492.ln the Bt424 design. a 40-bit multitap shift
odd Qutput channels.
The multiplexed input to a Brooktree RAMDAC'provides the
register is used 10 shift video data. The part can acCept 40 inputs
fina12 x speed iilcrease. The RAMDAC combines both even aJid
and provide five outputs. It can also be programmed 10 operate as
odd pixel data streams and generates the 360-MHz signal. Shift
a single shift regist~r of up to 40 bits, two .\6- or 20-bit shift
registers, color LUTs, aJid DACs make up the hack~ circuitry.
registers, five 8-bit shift registers. or four 10-bil shift registers.
Five Bt424 shift registers are required 10 handle the 12 words of
Designing the Board
data available on each memory cycle. Working in parallel, these
In 2K x 2K display controllers, the final system application will
ICs implement 24 8-bit shift registers and output duall80-MHz
dictate both the choice of graphics processor and the frame buffer
data streams. These dual data streams represent even and odd
design. In this example, the frame buffer consists of a planar
pixel data. Overlay data streams are wired in a Illgical-OR 10 the
organization with 8 bits/pixel and single buffering. This type of
design also includes four planes of overlay image memory. The
Q4
032·039
overlay buffer provides a method of adding a color cursor or
D24-D31
03
016-023
02
selectively masking parts of an image for X Windows
applications.
EVEN PIXELS
D14
D15
Four I-Mbit VRAM chips define a single plane; the I2-plane
D14
D12
D10
D13
system requires a total of 48 memory chips. Each plane produces
D6
D12
16 bits of data per clock cycle. Thus, the frame buffer produces a
D6
011
QI r---- 180 MHz
DO
DIO
total of 192 bits (12 words). Typically, the shift register clock input
D2
09
B1424
DO
D6
FRAME
10 the VRAM will be around 22.5 MHz. Output from each
MULnrAP
BUFFER
VIDEO
memory plane is split into even and odd pixel data streams.
PLANE 1
SHIFT
015
D7 REGISTER
Figure 4 shows how a single plane connects 10 a shift register 10
013
D6
Oil
D6
generate a 180-MHz data stream. Because the frame buffer
DO
D7
D3
employs a planar architecture, each word of data from a plane
O.
02
oor---- 180 MHz
contains a single bit (plane) of 16 different pixels output from the
03
01
DI
DO
frame buffer.
ODDPIXEl..S
Sixteen (8 for even pixels. 8 for odd pixels) 8-bit shift registers
are required to accept the eight individual words from the eight
image planes. These shift the data out so that the combined dual
figure 4. Cannectlng Image planes ta shift registers. I" this
8-bit outputs of the shift registers represent all eight planes of
diagram, a single Image planelscannected ta a multltap
single odd and even pixels. The shift-register operation orders the
vIdea reglsterta praduce a 18C1-MHz data stream.

J. ,1 J, ,l

1.11 !

!!! !

!!t, l

3 - 39

•

Article Reprints

IMAGING AND GRAPHICS

g~~~~:~ ~t:~~:

---rr

OVERLAY PLANE 2 ~
OVERLAY PLANE 1

EVEN
PIXELS

IMAGE PLANE 6
IMAGE PLANE 7
IMAGE PLANE 6
IMAGE PLANE 5
IMAGE PLANE 4

81492

RAMDAC

81424

PAD·
PA7

•

81424

PBD·

•

81424

•

IMAGE PLANE 3 ~

:::g~ ~t:~~ ~

ODD
PIXELS

OVERLAY PLANE 2
OVERLAY PLANE 1
IMAGE PLANE 8
IMAGE PLANE 7
IMAGE PLANE 6

!""CArl

OVERLAY PlANE 4 ----,.!....-.
OVERLAY PLANE 3 ----,.!....-.

~
~

P87

81424

IMAGE PLANE 5 ~ 032·039
024·031
>J
016·023
IMAGE PLANE 2 ----,.!....-. 08-015
IMAGE PLANE 1 ~ DO-07

:::g~ ~t:~~;

81492

03
Q2
01

RAMDAC

~
~

81424

Figure 5: Completing the design. Combining fast l-Mblt
.VRAMs with four Brooktree Bt424 shift registers and three

Bt492 RAMDACs allows designers to build 2K- lC 2K- lC
12-bit display controllers with oH-the-shelf parts.

3 -40

Article Reprints

four lower-order bit, of each pixel. Therefore. an overlay enable
signal can override the normal image.

RAMDACRole
Both the even and odd pixel data streams feed three Bt492 RAMDACs. Each RAMDAC accept' the dual data stream into separate
color LUT.,. Output, of the dual LUT., are then combined by a 2:1
on-board multiplexer. This multiplexer outputs an B-bit
360-MHz stream of data to the on-chip DAC driving the CRT.
The RAMDAC also accept' an overlay input associated with each
byte received. Dual on-chip 16 x Boverlay memory overrides the
normal color LUT when the overlay input is active. The lower 4
bits of the pixel data input provide the index into the overlaymemory lUT.
Eight planes of image memory can be used to display 256 colors. However. the 256 x BlUTs offer a palette of 16.BM. Thus.
the Bt424 and 8t492 can be used to implement true-color display
systems. For example. a design that includes eight planes of
memory per color in the frame buffer can display 16.BM colors
out of a palette of 16.BM.
Using eight planes per color also requires a set of shift registers
dedicated to each color. with each set of shift registers feeding
separate RAMDACs. Such designs therefore require triple the
number of VRAM and shift register ICs compared to the example here. Interconnections of the fmme buffer. shift registers. and

RAMDACs. however. will remain the same.
VlSI ECL les offer several advantages. In the example
shown. five shift-register ICs were used. Other available ECL
shift registers only handle B bits. Therefore. similar designs
would require 36 shift-register ICs. Using the Brooktree 8t424
results in lower parts cost. more board space. and a simpler
layout. 8rooktree's Bt492 RAMDAC features dual lBO-MHz inputs. an on-board multiplexer to increase bandwidth to 350
MHz. the lBO-MHz dual-color LUTs. and a 350-MHz DAC.
Implementing the controller with the 8t424 and Bt492 provides a clear cost advantage over controllers implemented with

semicustom ICs. Functional features key to 2K x 2K display
systems include support for a 16-color overlay function used to
implement X Windows and TTL interfucing. Furthermore. both
ICs can be used in nongraphics applications. Brooktree's 8t424
can serve as a general-purpose fast ECl shift register while the
8t492 can be used as a 512- X B-bit transcendental DAC for synESD,
thesizing sinusoids.

REPRINTED WITH PERMISSION ESD MAGAZINE 3/89. 1900 WEST PARK DRIVE SUITE 200, WESTBOROUGH, MA 01581

3 -41

•

3 - 42

GRAPHICS
AND

IMAGING

PRODUCTS

APPLICATIONS

HANDBOOK

1 990

Introduction
Application Notes
Article Reprints
Industry Standards
Sales Offices

4-1

Industry Standards
This collection of international standards provides
concise descriptions of some common video and image
transmission formats. Each document contains the
essential signal and coding parameters necessary for
the designer who must interface to transmission
protocols.

Component Analog equipment usually has individual
hardware requirements and has not been widely adopted
by standards agencies, although manufacturers usually
provide specific parameters in their literature. The
newest HOTV production standards (such as SMPTE
240M) present some unique interface requirements (like
Tri-Level Sync), but are not yet universally accepted
and, hence, not included. For the international
equipment designers, the CCIR 624 report summarizes
the fourteen television formats to be found worldwide.

The Electronic Industry Association (EIA) publishes
bulletins, recommendations and standards applicable to
broadcast television and display systems. The RS-170
monochrome standard, which was updated to the
composite chrominance subcarrier "A" version,
describes the common video interface for NTSC format
television. The RS-330 and RS-343 standards describe
camera interfaces for raster scan formats ranging from
525 lines to 1024 lines; the parameters are also widely
applied to component ROB computer graphics
interfaces.

With the advent of digital video transmission, the
problems 'of conflicting video formats came together in
the CCIR 601 recommendation, which also described
desirable filtering limits. This was the basis for the 01
(SMPTE) Digital Component Video Tape Recorder
interface, which has evolved into the lower cost
Composite Digital Video Tape Recorder interface 02
(SMPTE 244M). The serial transmission of CCIR 601
protocol digital video has been covered in CCIR 656,
but adoption of uniform coding schemes for DC noise
tolerance has not resulted in wide standardization.

The International Telecommunications Union (ITU) is
the governing body of several committees, including
the Consultative Committee of International Radio
(CCIR). The recommendation CCIR 601-1 defmes the
digital encoding standards for television signals,
report CCIR 624-3 lists the electrical specifications for
worldwide broadcast television signals.

Other agencies that publish relevant standards are the
European Broadcast Union (EBU), the Society of
Motion Picture and Television Engineers (SMPTE), and
the Institute of Electronic and Electrical Engineers
(IEEE). An address reference list of these agencies is
provided at the end of this section.

4-2

TAB

CON TEN T S

EIA RS-343A ..................................................... 4 - 5
EIA RS-330 ..................................................•... 4 - 11
EIA RS-170 .............................•........................ 4 - 15
EIARS-170A ..................................................... 4-21
CCIR Recommendation 601-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 25
CCIR Report 624-3 ................................................. 4 - 37
Reference Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . 4 - 65

•

4-3

Bnxidree~

Industry Standards

4-4

Industry Standards
ELECTRICAL PERFORMANCE STANDARDS FOR
HIGH RESOLUTION MONOCHROME
CLOSED CIRCUIT TELEVISION CAMERA
(From EIA Standard RS-343 and Standards Proposal No. 1025 formulated under the cognizance of
EIA Committee TR-17 on Closed Circuit Television.)

INTRODUCTION

The Electrical Performance Standards for High Resolution Monochrome Closed Circuit Television Equipment given here
represent, it is believed, the best agreement between the members of the Closed Circuit Television Committee, who drafted these
Standards, consistent with the rapidly developing state-of-the-art.
The Standards consist of (1) Definitions, (2) Minimum Standards, and (3) Methods of Measurement, for those parameters believed
to be of importance.
These Standards are intended to apply only to locally generated signals; that is, signals generated in the camera itself or at a
nearby point where control can be exercised over picture qUality.
This Standard is written to encompass equipment which operates in the range from 675 tol023 scanning lines with a field rate of
60 hz, interlaced 2:1. It is understood that special requirements may require different line numbers. It is recommended that one of
the following be considered to satisfy particular requirements: 675, 729, 875, 945, or 1023 lines.
The tolerance on any line number in this specification shall be ± 1%.

CAMERA OUTPUT - VIDEO

Definition - The camera output terminals are defined as the junction between the camera or switching facilities and the line
feeding either a transmission system or a visual display. The camera output signal is that signal which appears across the camera
output terminals.
In this document any reference to camera output refers to the output of the camera channel whether it is a single unit or a
multi-unit system.
The standard signal which will be discussed below is the signal which appears across the output terminals of the camera when
they are connected to the standard load impedance.
The signal which appears across the line feeding either a transmission system or a visual display may be different from the
standard signal. This is because the circuit may be equalized on an overall transmission basis and not with a view to keeping the
input impedance of the line a specified value.
Under these conditions monitoring measurements made at the output terminals of the camera must be properly interpreted.

2.1

Impedance

Definition - The complex ratio of voltage to current in a two terminal network, expressed in ohms.
Reprinted with the prior authorization of the Electronic Industries Association (EIA) as. copyright holder from Electrical
Performance Standards for High Resolution Monochrome Closed Circuit Television Camera. The choice of material to be excerpted
has been made by Brooktree and,therefore, does not affect the responsibility of the EIA.
4-5

RS-343-A

Industry Standards
Minimum Standard - The standard load impedance of the camera output shall have a value of 75 ohms ± 5% over the frequency
range of 0 to 10 MHz and shall be connected for single-ended operation.
Method of Measurement - It is recomennded that the load impedance for the camera be measured by means of impedance bridges
capable of an accuracy of ± 1% in the vicinity of 75 ohms.

2.2

Direct Current in Output

Minimum Standard - The open-circuit DC voltage of the camera output shall not exceed 2 volts. The short-circuit DC current shall
not exceed 2 milliamperes. These DC values are presumed to be independent of the output signal.
Method of Measurement - The open-circuit DC voltage should be measured with a voltmeter of at least 20,000 ohms per volt. The
short-circuit DC current should be measured with a milliammeter of, at most, 10 ohms internal resistance.

2.3

Polarity

Definition - The sense of the potential of a portion of the signal representing a dark area of a scene relative to the potential of a
portion of the signal representing a light area. Polarity is stated as "black-negative" or "black-positive".
Standard - The standard polarity of the output of the camera shall be black-negative.
Method of Measurement - It is recommended that signal polarity be measured by means of an oscilloscope of known deflection
polarity.

2.4

Composite Picture Signal*

*Measurement of signal levels shall be made in accordance with 58 IRE 23.S1, IRE Standards on Television: Measurement of
Luminance Signal Levels, 1958 or latest revision thereof. This standard defines the levels of a Television signal in terms of IRE
units. Reference white level is + 100 IRE units; blanking level is 0 IRE units; sync level is - 40 IRE units. Thus the
peak-to-peak level of a signal extending from reference white to sync tip is 140 IRE units.

RS-343-A

4-6

Industry Standards
Composite Picture Signal - The signal which results from combining a blanked picture signal with the sync signal.
Blanked Picture Signal - The signal resulting from blanking a picture signal. (This signal mayor may not contain
setup. (A blanked picture signal with setup is commonly caIled a non-composite signal.)

Level (in television)
Signal amplitude measured in accordance with specified techniques.

A specified position on an amplitude scale applied to a signal waveform.
Standard - It shall be standard that the blanked picture signal with setup (non-composite), as measured from blanking level to
reference white level across the standard load impedance of the camera, be 0.714 ± 0.1 volt (100 IRE units).
It shall be standard that the synchronizing signal as measured across the standard load impedance of the camera be 0.286 ± 0.05
volts (nominally 40 + IRE units).
It shaIl be standard that the setup be 7.5 ± 5 IRE units (2.5% to 12.5% of the blanked picture signal).

Method of Measurement - It is recommended that the signal voltage output of the camera be measured by means of an
oscilloscope capable of measuring such a signal with an accuracy of ± 2% of the actual value over the voltage range of 0.2 to 1.5
volts. The oscilloscope should incorporate a linear scale having a zero line which can be aIligned with blanking level and
divisions extending to at least 100 in the white direction and to at least 50 in the black direction. Some means of calibration
should be provided so that signal level measurements can be made in volts as well as in IRE units.

4-7

RS-343-A

Industry Standards

HIGH RESOLUTION TV SYSTEM PARAMETERS

Fundamental Generated Frequency (MHz) (8)
(2)

(3)

(4)

(5)

Lines! Active
Frame Lines

Ver.
Res
Rv

tha

KHz

~secs

675
729
875
945
1023

425
475
575
600
650

20.25
21.87
26.25
28.35
30.69

49.38
45.72
38.09
35.27
32.58

(1)

624
674
809
874
946

RhMhz (6)
~secs

42.38
38.72
31.09
28.27
25.58

Rh =Rv (9)

= 800 lines

4:3(7)

1: 1

4:3

1: 1

4:3

1: 1

4:3

1: 1

63.6
58.1
46.6
42.4
38.4

84.8
77.4
62.2
56.5
51.2

6.69
8.18
12.3
14.1
16.9

5.01
6.13
9.25
10.6
12.7

12.6
13.8
17.2
18.9
20.8

9.44
10.3
12.9
14.1
15.6

15.7
17.2
21.4
23.6
26.1

11.8
12.9
16.1
17.7
19.5

Vertical Blanking = 1250 ~secs nominal.
Horizontal Blanking = 7 ~secs nominal.

NaJES:
1.
2.
3.
4.
5.
6.
7.
8.
9.

Active Lines = Lines! Frame less those occurring during vertical blanking.
Vertical Resolution = Active Lines times KelJ Factor (0.7). Vertical Resolution rounded to nearest 25 lines.
fh = Horizontal scanning frequency.
th '" Total horizontal line time.
tha = Total active horizontal line time (th - 7 ~secs.)
Rh!MHz = Lines of horizontal resolution per MHz of bandwidth.
Aspect Ratio.
Fundamental generated frequency required to provide indicated resolution in lines per picture height.
Fundamental generated frequency required to provide horizontal resolution equal to vertical resolution.

RS-343-A

= 1000 lines

4-8

Industry Standards
COMPOSITE VIDEO WAVEFORM
HIGH RESOLUTION MONOCHROME TELEVISION CAMERA
TO

I I
I-H-I

i
I
I

12S0±IS~

I
I

I--+A-+-I
t

I
I

1_7.~X_1
MIN

1 I
1
.7SpS - I i - 6.O)IS - I
1
MIN
-------_ 1 1
1

~la

-a-I-

__ _ _________ .

tr------Tf-- --~r---1~--

I I -~------- --------.

1__

·T.;~-

---

T- -,,
,

=,,-

~--i-2SpSMIN

OREF

BACK PORCH

, 2.75±.25pS

FRONT PORCH

FIGURE 1

NOTES:
1. 6 = 0.714 ± 0.1 volt (100 IRE Units)
2. a = 0.286 (40 IRE Units) nominal.

12. Rise and fall times of vertical blanking and vertical
sync pulse, measured from 10% to 90% amplitudes, shall
be less than 5~/s.
13. Tilt on vertical sync pulse shall be less than O.la.
14. If horizontal information is provided during the vertical sync pulse it must be at 2H frequency and as shown
in the optional vertical blanking interval waveform.
15. B - vertical serration = 2 ± .5Ws measured between
the 90% amplitude points. Rise time measured from 10%
to 90% amplitudes shall be less than O.I~/s.
16. If equalizing pulses are used in the vertical blanking
interval waveforms they shall be 6 in number preceding
and following the vertical sync pulse, be at 2H frequency
and 1/2 the width of H sync pulse.
17. It is reconunended that for proper interlace the time
duration between the leading edge of vertical sync and
the leading edge of horizontal sync be a multiple of H/2.

3. Sync to total signal ratio (a/(6 + a) ) = 28.6 ± 5%
4. Blanking = 7.5 ± 5 IRE Units (2.5% to 12.5% of B)
5. Horizontal Rise Times measured from 10% to 90%
amplitudes shall be less than O.I~/s.
6. Overshoot on horizontal blanking signal shall not
exceed 0.02B at beginning of front porch and 0.05B at
end of back porch.
7. Overshoot on sync signal shall not exceed 0.056.
8. TO = start of vertical sync pulse.
9. T 1 = start of vertical blanking.
10. Tl =TO +0
- 250 Ws
11. A - vertical sync pulse = 125
tween 90% amplitude points.

± 50~/s measured be4-9

RS-343-A

Industry Standards

RS-343-A

4 -10

Industry Standards
ELECTRICAL PERFORMANCE STANDARDS FOR
CLOSED CIRCUIT TELEVISION CAMERA 525/60 INTERLACED 2:1
(From Standards Proposal No. 900 Formulated under the cognizance of
EIA Committee TR-17 on Closed Circuit Television.)
1.

Introduction

The Electrical Performance Standards for Closed Circuit Television Camera given here represent, it is believed, the best
agreement between the members of the Closed Circuit Television Committee, who drafted these Standards, consistent with the
rapidly developing state-of-the-art.
(The term "camera" as used in this document may include a single or multiple unit camera chain.)
The Standards consist of (I) Definitions, (2) Standards, and (3) Methods of Measurement, for those parameters believed to be of
importance.
These Standards are intended to apply only to locally generated signals; that is, signals generated in the camera itself or at a
nearby point where control can be exercised over picture quality. They are not intended to apply to equipment described by EIA
Standard, RS-170, Electrical Performance Standards - Monochrome Television Studio Facilities, November 1957, or revision
thereof.

CAMERA OUTPUT - VIDEO

Definition - The camera output terminals are defined as the junction between the camera or switching facilities and the line
feeding either a transmission system or a visual display. The camera output signal is that signal which appears across the camera
output terminals.
The standard signal which will be discussed below is the signal which appears across the output terminals of the camera when
they are connected to the standard load impedance.
The signal which appears across the line feeding either a transmission system or a visual display may be different from the
standard signal. This is because the circuit may be equalized on an overall transmission basis and not with a view to keeping the
input impedance of the line a specified value.
Under these conditions, monitoring measurements made at the output terminals of the camera must be properly interpreted.

2.1

Load Impedance

Definition - The complex ratio of voltage

current in a two terminal network, expressed in ohms.

Standard - The standard load impedance of the camera output shall have a value of 75 ohms ± 5% over the frequency range of the
camera and shall be connected for single-ended operation.
Method of Measurement - It is recommended that the load impedance for the camera be measured by means of impedance bridges
capable of an accuracy of ± 1% in the vicinity of 75 ohms.

2.2

Direct Current in Output

Standard - The open-circuit DC voltage of the camera output shall not exceed ± 2 volts. The short-circuit DC current shall not
exceed 2 milliamperes. These DC values are presumed to be independent of the output signal. (These values chosen are to
facilitate interconnection of various pieces of equipment in the system.)
Reprinted with the prior authorization of the Electronic Industries Association (EIA) as copyright holder from Electrical
Performance Standards for Closed Circuit Television Camera 525160 Interlaced 2:1. The choice of material to be excerpted has
been made by Brooktree and, therefore, does not affect the responsibility of the EIA.

4 - 11

RS-330

Industry Standards
Method of MeasuremenJ - The open-circuit DC voltage should be measured with a voltmeter of at least 20,000 ohms per volt. The
short-circuit DC current should be measured with a milliammeter of, at most, 10 ohms internal resistance.

2.3

Polarity

Definition - The sense of the potential of a portion of the signal representing a dark area of a scene relative to the potential of a
portion of the signal representing a light area. Polarity is stated as 'black-negative" or "black-positive".
Standard - The standard polarity of the output of the camera shall be black-negative.
Method of Measurement - It is recommended that signal polarity be measured by means of an oscilloscope of known deflection
polarity.

2.4

Composite Picture Signal·

Definitions:
Picture Signal - The signal resulting from the scanning process.
Sync Signal - The signal employed for the synchronization of scanning.
Sync Level - The level of the peaks of the sync signal.
Blanking Level - That level of a composite picture signal which separates the range containing picture information
from the range containing synchronizing information. (This term should be used for controls performing this
function.)
Black Peak - A peak excursion of the picture signal in the black direction.
White Peak - A peak excursion of the picture signal in the white direction.
Reference White Level - The picture signal level corresponding to a specified maximum limit for white peaks.
Reference Black Level - The picture signal level corresponding to a specified maximum limit for black peaks.
Setup - In television, the ratio between reference black level and reference white level both measured from blanking
level. It is usually expressed in percent. (This is equivalent to the difference in level between reference black level and
blanking level, expressed in IRE units).
Composite Picture Signal - The signal which results from combining a blanked picture signal with the sync signal.
B ranked Picture Signal - The signal resulting from blanking a picture signal. (This signal mayor may not contain
setup. A blanked picture signal with setup is commonly called a non-composite signal.)
Level (in television) - Signal amplitude measured in accordance with specified techniques.
A specified position on an amplitude scale applied to a signal waveform.
Standard - It shall be standard that the blanked picture signal with setup (non-composite), as measured from blanking level to
reference white level across the standard load impedance of the camera, be 0.714 ± 0.1 volt (100 IRE units).
It shall be standard that the synchronizing signal as measured across the standard load impedance of the camera be 0.286
volts (nominally 40 + IRE units).

± 0.05

*Measurement of signal levels shall be made in accordance with 58 IRE 23.S1, IRE Standards on Television: Measurement of
Luminance Signal Levels, 1958 or latest revision thereof. This standard defines the levels of a television signal in terms of IRE
units. Reference white level is + 100 IRE units; blanking level is 0 IRE units; sync level is - 40 IRE units. Thus the
peak-to-peak level of a signal extending from reference white to sync tip is 140 IRE units.

RS-330

4 -12

Industry Standards
It shall be standard that the setup be 7.5

± 5 IRE units (2.5% to 12.5% of the blanked picture signal).

Method of Measurement - It is recommended that the signal voltage output of the camera be measured by means of an
oscilloscope capable of measuring such a signal with an accuracy of ± 2% of the actual value over the voltage range of 0.2 to 1.5
volts. The oscilloscope should incorporate a linear scale having a zero line which can be aligned with blanking level and
divisions extending to at least 100 in the white direction and to at least 50 in the black direction. Some means of calibration
should be provided so that signal level measurements can be made in volts as well as in IRE units.

SECTION 25 PICTURE FIDEliTY - DELETED
2.6

SYNC SIGNAL TOLERANCE

Definition - It shall be standard that the synchronizing signal waveform at the output of the picture line amplifier conform with
the drawing, Figure #1, Composite Video Waveform, 525/60 Interlaced 2:1.
Standard - It shall be standard that the time of occurrence of the leading edge of any horizontal pulse "N" of any group of twenty
horizontal pulses not differ from "NH" by more than O.OOlH where "H" is the average interval between the leading edges of
horizontal pulses as determined by an averaging process carried out over a period of not less than 20 or more than 100 lines.
It shall be standard that the frequency of horizontal and vertical scanning pulses not vary from the values established by the
standards of frame frequency and number of scanning lines by more than ± 1% regardless of variations in frequency of the power
source supplying the camera.

Method of Measurement - It is recommended that pulse amplitudes be measured in peak-to-peak volts. This can be done
satisfactorily with an oscilloscope and a calibrated comparison signal. Accuracy of measurement should be at least ± 2%. The
time of rise is the time required for changing from 10 percent to 90 percent of normal amplitude. The time of decay is the time
required for changing from 90 percent to 10 percent amplitude. Peak pulse width shall be the width measured at 90 percent
amplitude. Base pulse width shall be the width measured at 10 percent amplitude. Pulse interval measurements shall be made
between corresponding 10% points on the pulses. The width of the vertical pulse, as well as the phase relationship between this
pulse and the other blanking and synchronizing pulses can be determined by the "pulse cross" method. To do this a monitor is
synchronized in such a manner that the vertical blanking bar appears horiiontally near the center of the picture and the
horizontal blanking bar appears vertically through the center of the picture. A substantial increase iii vertical deflection
amplitude of the monitor allows details to. be seen more easily.
The allowable variations in timing between successive hor.izontal pulses is measured in terms of percent of a horizontal scanning
period. This can be measured on the same monitor used to indicate the "pulse cross" if the horizontal scanning has automatic
frequency control with a sufficiently long time constant to give substantially constant frequency over a period of 20 lines.
Accuracy of measurement will depend on the maximum amount of horizontal scanning available, the resolution of the cathode ray
tube, and the wave front steepness of the pulses supplied to the grid of the cathode ray tube.
A frequency or a frequency deviation meter with an accuracy of ± 0.1 cycle at 60 cycles or ± 25 .cycles at 15,750 cycles can be used
for measuring either the frame frequency or the line frequency of the output signal from the picture line amplifier.

4 -13

RS-330

Industry Standards
COMPOSITE VIDEO WAVEFORM
525/60 INTERLACED 2:1
T,

I I
1- H-l-----+----

12S0±11X¥S - - - - - - - - - - -

i- -1
A

~
I

,---- I

FIGURE 1

NOlES:
11. A - vertical sync pulse = 150 ± 50j.L/s measured between 90% amplitude points.
12. Rise and fall times of vertical blanking and vertical
sync pulse, measured from 10% to 90% amplitudes,
shall be less than 5j.L/s.
13. Tilt on vertical sync pulse shall be less than 0.1
14. If horizontal information is provided during the
vertical sync pulse it must be at 2H rate and as shown in
the optional vertical blanking interval waveform.
15. B - vertical serration = 4.5 ± .5j.L/s measured between the 90% amplitude points. Rise times measured
from 10% to 90% amplitudes shall be less than O.3j.L/s.
16. If equalizing pulses are used in the vertical blanking interval waveform they shall be 6 in number prececding the vertical sync pulse and be at 2H rate.

1. B = 0.714 ± .1 volt (100 IRE Units).
2. a = 0.286 (40 IRE Units) nominal.
3. Sync to total signal ratio (al(B + a)) = (28.6 ± 5)%.
4. Blanking = 7.5 ± 5 IRE Units (2.5% to 12.5% of B).
5. Horizontal Rise times measured from 10% to 90%
amplitudes shall be less than O.3j.L/s.
6. Overshoot on horizontal blanking signal shall not
exceed 0.02B at beginning of front porch and 0.05B at
end of back porch.
7. Overshoot on sync signal shall not exceed 0.05B.
8. TO = start of vertical sync pulse.
9. T 1 = start of vertical blanking.
10. T1 =TO +0
- 250 j.L/s

RS-330

4 -14

Industry Standards
ELECTRICAL PERFORMANCE STANDARDS
MONOCHROME TELEVISION STUDIO FACILITIES
(From Standard TR-135 and Standards Proposal Nos. 475 and 536formulated under the cognizance
of EIA Engineering Committee TR-4 on Television Transmitters)
1.

INTRODUCTION

The Electrical Performance Standards for Monochrome Television Studio Facilities given here represent, it is believed, the best
agreement between the members of the Television Studio Facilities Sub-committee, who drafted these Standards, consistent with
the rapidly developing state of the art.
The Standards consist of (1) Deftnitions, (2) Minimum Standards, and (3) Methods of Measurement, for those parameters believed
to be of importance.
These Standards are intended to apply only to locally generated signals; that is, signals generated in the studio itself or at a
nearby point where control can be exercised over picture quality.

PICTURE LINE AMPLIFIER OUTPUT

Definition - The picture line amplifter output terminals are dermed as the junction between the studio facility and the line feeding
either a relay transmitter, a visual transmitter, or a network. The picture line amplifter output signal is that signal which appears
across the picture line amplifter output terminals.
The standard signal which will be discussed below is the signal which appears across the output terminals of the picture line
amplifier when they are connected to the standard load impedance.
The signal which appears across the line feeding either a relay transmitter, a visual transmitter, or a network may be different
from the standard signal. This is because the circuit may be equalized on an overall transmission basis and not with a view to
keeping the input impedance of the line a specifted value.
Under these conditions monitoring measurements made at the output terminals of the picture line amplifter must be properly
interpreted.

2.1

Impedance

Definition - The complex ratio of voltage to current in a two tenninal network, expressed in ohms.
Minimum Standard - The standard load impedance of the picture line amplifter shall have a value of 75 ohms
frequency range of 0 to 4.5 Me and shall be connected for single-ended operation.

± 5% over the

The internal impedance of the picture line amplifter shall be 75 ohms ± 10% at those frequencies where the impedance of the
output condenser (if used) may be neglected. The time constant of the internal impedance combined with the standard load
impedance shall be 0.1 second or greater.

Method of Measurement - It is recommended that the load impedance for the picture line amplifter be measured by means of
impedance bridges capable of an accuracy of ± 1% in the vicinity of 75 ohms.
The internal impedance of the picture line amplifter should be measured by the resistance variation method. This measurement
should be made at the standard output level of the amplifter. The load impedance should be varied from 75 ohms to 50 ohms
approximately.

Reprinted with the prior authorization of the Electronic Industries Association (EIA) as copyright holder from Electrical
Performance Standards - Monochrome Television Studio Facilities. The choice of material to be excerpted has been made by
Brooktree and, therefore, does not affect the responsibility of the EIA.

4 - 15

RS-170

Industry Standards
2.2

Direct Current in Output

Minimum Standard - The open-circuit DC voltage of the picture line amplifier output shall not exceed 2 volts. The short-circuit
DC current shall not exceed 2 milliamperes. These DC values are presumed to be independent of the output signal.
Method of Measurement - The open-circuit DC voltage should be measured with a voltmeter of at least 20,000 ohms per volt. The
short-circuit DC current should be measured with a milliammeter of. at most, 10 ohms internal resistance.

2.3

Polarity

Definition - The sense of the potential of a portion of the signal representing a dark area of a scene relative to the potential of a
portion of the signal representing a light area. Polarity is stated as "black-negative" or "black-positive".
Standard - The standard polarity of the picture line amplifier shall be black-negative.
Method of Measurement - It is recommended that signal polarity be measured by means of an oscilloscope of known deflection
polarity.

2.4

Composite Picture Signal*

Definitions:
Picture Signal - The signal resulting from the scanning process.

Sync Signal - The signal employed for the synchronization of scanning.
Sync Level - The level of the peaks of the sync signal.
Blanking Level - That level of a composite picture signal which separates the range containing picture information
from the range containing synchronizing information.
B lack Peak - A peak excursion of the picture signal in the black direction.
White Peak - A peak excursion of the picture signal in the white direction.
Reference White Level - The picture signal level corresponding to a specified maxintum limit for white peaks.
Reference Black Level - The picture signal level corresponding to a specified maximum limit for black peaks.
Setup - In television, the ratio between reference black level and reference white level both measured from blanking
level. It is usually expressed in percent.
Composite Picture Signal - The signal which results from combining a blanked picture signal with the sync signal.
Blanked Picture Signal - The signal resulting from blanking a picture signal.
Level (in television) - Signal amplitude measured in accordance with specified techniques.
A specified position on an amplitude scale applied to a signal waveform.
Minimum Standard - It shall be standard that the picture signal, as measured from blanking level to reference white level across
the standard load impedance of the picture line amplifier, be 1.0 ± 0.05 volt.

*A level of.70 volts for color 1V applications has received preliminary approval. Where monochrome equipment is used in the
same studio facilities with color equipment. it is expected that both will be adjusted to the.70 volt level. Where monochrome
equipment is used by istelf, it may be desirable to continue with the 1.0 volt level that has been standard for some time. The primary intent in reaffirming the 1.0 volt standard is to provide assurance that new monochrome equipment will function properly
when used with earlier types of monochrome equipment.

RS-170

4 -16

Industry Standards
It shall be standard that the synchronizing signal as measured across the standard load impedance of the picture line amplifier be
40 ± 5% of the picture signal.
It shall be standard that throughout a given transmission the synchronizing signal be maintained constant within ± 4% as
measured across the standard load impedance of the picture line amplifier. This variation may take place on a long time basis
only and not during successive cycles. The allowable amplitude variation over one frame should be considerably smaller.
The amplitude of blanking level referred to the AC axis of the signal at the picture line amplifier output shall not vary more than
± 5% of the sync signal amplitude during one field. The AC axis of the signal shall be determined by averaging the signals over
one field. The sync amplitude is designated as "a." in the dtawing entitled "Picture Line Amplifier Standard Output".
It shall be standard that the minimum setup be 7.5

± 2.5%.

Method of MeasuremenJ - It is recommended that the signal voltage output of the picture line amplifier be measured by means of
an oscilloscope capable of measuring such a signal with an accuracy of ± 2% of the actual value over the voltage range of 0.2 to
2.0 volts. The oscilloscope should incorporate a linear scale having a zero line which can be alligned with blanking level and
divisions extending to at least 100 in the white direction and to at least 50 in the black direction. Some means of calibration
should be provided so that signal level measurements can be made in volts as well as sync and other measurements in percent of
picture signal. The oscilloscope amplifier characteristics should be such as to introduce negligible measurement errors due to
low frequency distortion or overshoot. In order to provide the minimum band-width consistent with satisfactory readings of
levels it is recommended that the amplitude response at 3 megacycles be minus 6 plus 2 minus 3db relative to the response at low
frequencies, and that the rise time be approximately 0.175 microsecond without overshoots.

SECTION 2.5 PICTURE FIDELITY - DELETED
2.6

SYNC SIGNAL TOLERANCE

Definition - It shall be standard that the synchronizing signal waveform at the output of the picture line amplifier conform with
the dtawing "Picture Line Amplifier Standard Output".
M iniumum Standard - It shall be standard that the time of occurrence of the leading edge of any horizontal pulse "N" of any group
of twenty horizontal pulses not differ from "NH" by more than O.OOIH where "H" is the average interval between the leading
edges of horizontal pulses as determined by an averaging process carried out over a period of not less than 20 or more than 100
lines.
It shall be standard that the rate of change of frequency of recurrence of the leading edges of the horizontal sync pulses appearing
in the picture line amplifier output be not greater than 0.15 percent per second, the frequency to be determined by an averaging
process carried out over a period of not less than 20 or more than 100 lines, such lines not to include any portion of the vertical
blanking signal.
It shall be standard that the frequency of horizontal and vertical scanning pulses not vary from the values established by the
standards of frame frequency and number of scanning lines by more than ± 1% regardless of variations in frequency of the power
source supplying the television station.
It shall be standard that the rate of change of frequency and the time interval between successive pulses that has been made
standard for the horizontal synchronizing pulses appearing across the output of the picture line amplifier also be standard for the
horizontal scanning of the pickup tube.
Method of MeasuremenJ - It is recommended that pulse amplitudes be measured in peak-to-peak volts. This can be dolle
satisfactorily with an oscilloscope and a calibrated comparison signal. Accuracy of measurement should be at least ± 2%. The
time of rise is the time required for changing from 10 percent to 90 percent of normal amplitude. The time of decay is the time
required for changing from 90 percent to 10 percent amplitude. Peak pulse width should be the width measured at 90 percent
amplitude. Base pulse width should be the width measured at 10 percent amplitude. The width and the time of rise or decay of
pulses should be measured in fractions of the horizontal or vertical scanning period. Pulse interval measurements should be made
between corresponding points on the pulses. This can be done with a suitable oscilloscope having timing pulses at appropriate
frequencies synchronized with the horizontal trace of the oscilloscope. The accuracy of the timing measurements should be
within O.OOlH for horizontal frequency pulses and 0.0001 V for vertical frequency pulses. The number of equalizing pulses, the
width of the vertical pulse, as well as the phase relationship between these pulses and the other blanking and synchronizing

4 -17

RS-170

Industry Standards
pulses can be determined by the "pulse cross" method. To do this a monitor is synchronized in such a manner that the vertical
blanking bar appears horizontally near the center of the picture and the horizontal blanking bar appears vertically through the
center of the picture. A substantial increase in vertical deflection amplitUde of the monitor allows details to be seen more easily.
The rate of change of frequency of the horizontal and vertical sync pulses should be measured in per cent per second. No
satisfactory method seems to be available at the present time to measure this quantity accurately. It is believed possible,
however, that a satisfactory instrument somewhat similar to a frequency deviation meter can be built to serve this purpose.
The allowable variations in timing between succesive horizontal pulses is measured in terms of percent of a horizontal scanning
period. This can be measured on the same monitor used to indicate the "pulse cross" if the horizontal scanning has automatic
frequency control with a sufficiently long constant to give substantially constant frequency over a period of 20 lines.
Accuracy of measurement will depend on the maximum amount of horizontal scanning available, the resolution of the cathode ray
tube, and the wave front steepness of the pulses supplied to the grid of the cathode ray tube.
A frequency or a frequency deviation meter with an accuracy of ± 0.1 cycle at 60 cycles or ± 25 cycles at 15,750 cycles can be used
for measuring either the frame frequency of the line frequency of the output signal from the picture line amplifier.
The phasing of the vertical blanking signals from two separate sources can be checked on an oscilloscope or a picture monitor
by locking in the oscilloscope sweep with one signal and observing the other.

RS-170

4 - 18

Industry Standards
MONOCHROME TELEVISION PICTURE LINE AMPLIFIER
STANDARD OUTPUT
(VISUAL TRANSMITTER INPUT SIGNAL WAVEFORM)

SYNC SIONALAMPLTI1JDB a. SHAlLBH HBlD CONSTANT Wl1lUN

±4-' DURlNG'llIANSMISSION
P=I.o±o.o5VOLTS
,,=0.4p±o.OSP

HORlZONTAL

DRAWINGS NOT TO SCALE

BLANKING
(PEDBSTAI4
PULSE
-BOTTOM OP PICTURE

- - - - - VERTICALBIANXING(PBDBSTAL)PULSEO.07SV±.ODSVSEENOTBS3.tS -----I-TOPOPPICTURB

---1 r---1_102SH+H-_TI
II
I

-0
--3_

~iLuhUTunIT1hrp-~

DBTAILBETWEEN
A-A IN 2

•

RISE TIME AND PALL TIME OPALL PULSBS o.OO3H MAX.
(SEENOTB7)

NOTES:
1. H = time from start of one line to start of next line.
2. V = tinle from start of one field to start of next field.
3. Leading and trailing edges of vertical blanking
(pedestal) should be complete in less than 0.1H.
4. Leading and trailing edges of horizontal blanking
(pedestal) shall be steep enough to preserve minin1um
and maximum values of durations under all conditions
of picture content.
5. All tolerances and limits shown in this drawing are
permissible only for long - time variatons.
6. Equalizing pulse area shall be between 0.45 and 0.5
of the area of a horizontal sync pulse.

7. All rise and decay times shall measure between 0.1
and 0.9 amplitude reference lines.
8. The overshoot on blanking (pedestal) signal shall
not exceed 0.028 at the beginning of the front porch
and shall not exceed 0.058 at the end of the back porch.
The overshoot on sync signals shall not exceed 0.0511Any other extraneous signals on the blanking
(pedestal) signal shall not exceed .0213.
9. For setting aspect ratio, the horizontal blanking
(pedestal) duration should be set to O.175H at the 0.58
point.
10. Rise time and decay time of horizontal blanking
shall not exceed 0.OO3H.

4 -19

RS-170

Industry Standards
MONOCHROME TELEVISION PICTURE LINE AMPLIFIER
STANDARD OUTPUT
(VISUAL TRANSMITTER INPUT SIGNAL WAVEFORM)

f4\

\.:..J

DBTAILBE1WEEN
B-BIN2

BLANKING
(pEDESTAL)

LEVEL
0.1 ex

f5\

\:/

DETAn.BIITWEEN
C·CIN3

O,l78HMAX

o.sp

SEE NOTE 9

O.02HMIN
BLAN KING

SBENOl'B4

--T --

-t

_ _- -

(pEDESTAL)

.065"
MIN

1---1 -O.oo3HMAX I

O.OO3HMAX -

O.07SH ± .OOSH

__ J_'!:~~
--

LEV EL

o.lP
O.lp

-------

O.la.

RISETIMEAND DECAY TIME OF AlL PULSES O.OO3H MAX.
(SEE NOTE 7)

RS-170

4 - 20

Industry Standards
COLOR TELEVISION STUDIO
PICTURE LINE AMPLIFIER OUTPUT
RS 170 A
EIA TENTATIVE STANDARD

TIME

l.S~SEC±O.I~SEC

COLOR FIELD I

--------1

VERTICAL BLANKING INTERVAL = 20H +H
-0

START OF
FIELD ONE
PRE-EQUALIZING I
VERTICAL SYNC
I POST-EQUALIZING
- PULSE INTERVAL - I - PULSE INfERVAL - I - PULSE INTERVAL -

-H-

REFERENCE SUBCARRIER
PHASE, COLOR FIELD I

COLOR FIELD II
-------+----VERTICALBLANKING INTERVAL

O.SH -

STARTOF
FIELD TWO

-r---------

X
REFERENCE SUBCARRIER
PHASE, COLOR FIELD II
COLOR FIELD III

--------I---VERTICALBLANKING INTERVAL

--+---------

T1 +2V

START OF
FIELD THREE

COLOR FIELD IV
-------+----VERTICALBLANKING INTERVAL

-r---------

T1 +3V

REFERENCE SUBCARRIER
PHASE, COLOR FIELD IV

START OF
FIELD FOUR

4 - 21

RS-170-A

Industry Standards
COLOR TELEVISION STUDIO
PICTURE LINE AMPLIFIER OUTPUT
RS 170 A
EIA TENTATIVE STANDARD

DETAIL Y-Y

IRE

~~EL

--100

~~EL-~
4

BLANKING LEVEL

~
-20

SYNC LEVEL

-40
FRONT

SYNC

PORCH

4.7pSEC

1.5pSEC

O.lpSEC

SYNC TO SETUP 9.4pSEC %O.lpSEC

DETAILX·X

1----IRE
BLANKING
LEVEL

II ----~I

0.511 _

,..-------,
4.7pSEC %O.lpSEC

VERTICAL SERRATION

-20
-40

DETAILZ-Z

SO%BURST
AMPLl11JDE
_n-=14)

.. '/
LBADINGEDGE
OPSYNC

RS-170-A

5.3pSEC
%O.lpSEC(19CYLBS)
(NOTES 7,13)

- - - - 9CYCLBS - - - -

4 -22

Industry Standards
COLOR TELEVISION STUDIO
PICTURE LINE AMPLIFIER OUTPUT
RS 170 A
EIA TENT ATIVE STANDARD

NOTES:
1. Specifications apply to studio facilities. Common
carrier, studio to transmitter and transmitter
characteristics are not included.

9. Tolerance on sync level, reference black level ( set
up ) and peak to peak burst amplitude shall be ± 2 IRE
Units.

2. All tolerances and limits shown in this drawing
permissible only for long time variations.

10. The interval beginning with line 17 and extending
through line 20 of each field may be used for test, cue
and control signals.

3. The burst frequency shall be 3.579545MHz ± 10Hz.
11. Extraneous synchronous signals during blanking
intervals, including residual suhearrier, shall not exceed
1 IRE Unit. Extraneous non-synchronous signals
during blanking intervals shall not exceed 0.5 IRE
Unit. All special purpose signals (VITS,VIR,etc.) when
added to the vertical blanking interval are excepted.
Overshoot on all pulses during sync and blanking,
vertical and horizontal, shall not exceed 2 IRE Units.

4. The horizontal scanning frequency shall be 2/445
times the burst frequency (one scan period (H) =
63.556J.L sec).
5. The vertical scanning frequency shall be 2/525
times the horizontal scanning frequency ( one scan
period (V) = 16.783J.L sec ).
6. Start of color fields I and III is defined by a whole
line between the first equalizing pulse and the
preceding H sync pulse. Start of color fields II and IV is
defined by a half line between the first equalizing pulse
and the preceding H sync pulse. Color field I: that field
with positive going zero-crossings of reference
subcarrier most nearly coincident with the 50%
amplitude point of the leading edges of even numbered
horizontal sync pulses. Reference subcarrier is a
continuous signal with the same instantaneous phase
as burst.

12. Burst envelope rise time is 0.3J.L sec + 0.2J.L sec 0.1J.L sec measured between the 10% and 90% amplitude
points. Burst is not present during the nine line
vertical interval.

7. The zero - crossings of reference subcarrier shall be
nominally coincident with the 50% point of the
leading edges of all horizontal sync pulses. For those
cases where the relationshop between sync and
subcarrier is critical for program integration, the
tolerance on this coincidence is ± 40' of reference
suhearrier.

14.The end of burst is defined by the zero-crossing
(positive or negative slope) that follows the last half
cycle of subearrier that is 50% or greater of the burst
amplitude.

13. The start of burst is defined by the zero-crossing
(positive or negative slope ) that precedes the first half
cycle of subcarrier that is 50% or greater of the burst
amplitude. Its position is nominally 19 cycles of
subcarrier from the 50% amplitude point of leading edge
of sync. (See detail7:Z)

15. Monochrome signals shall be in accordance with
this drawing except that burst is omitted, and fields III
and IV are identical to fields I and II respectively.

8. All rise times and fall times unless otherwise
specified are to be 0.14J.L sec ± 0.02J.L sec measured
from 10% to 90% amplitude points. All pulse widths
are measured at 90% amplitude points, unless otherwise
specified.

16. Occasionally, measurement of picture blanking at
20 IRE Units is not possible because of scene content
as verified on a picture monitor.

4 - 23

RS-170-A

Broddree

Industry Standards

RS-170-A

4 - 24

Industry Standards
Rec.

601·1

SECTION 11F: DIGITAL METHODS OF TRANSMITTING TELEVISION INFORMATION

Recommendations and Reports
RECOMMENDATION 601-1

ENCODING PARAMETERS OF DIGITAL TELEVISION FOR STUDIOS'
(Question 25/11, Study Programmes 25G/11, 25H/11)
(1982-1986)
TheCCIR,
CONSIDERING
(a)

that there are clear advantages for television broadcasters and programme producers in digital studio standards
which have the greatest number of significant parameter values common to 525-line and 625-line systems;

(b)

that a world-wide compatible digital approach will permit the development of equipment with many common
features, permit operating economies and facilitate the international exchange of programmes;

(c)

that an extensible family of compatible digital coding standards is desirable. Members of such a family could
correspond to different quality levels, facilitate additional processing required by present production
techniques, and cater for future needs;

(d)

that a system based on the coding of components is able to meet some, and perhaps all, of these desirable
objectives;

(e)

that the co-siting of samples representing luminance and colour-difference signals (or, if used, the red, green
and blue signals) facilitates the processing of digital component signals, required by present production
techniques,

UNANIMOUSLY RECOMMENDS
that the following be used as a basis for digital coding standards for television studios in countries using the 525-line
system as well as in those using the 625-line system:
1•

Component

coding

The digital coding should be based on the use of one luminance and two colour-difference signals (or, if used, the red,
green and blue signals).
The spectral characteristics of the signals must be restricted to eliminate aliasing. When using one luminance and two
colour-difference signals as defined in Table I, this can be achieved by using filters as defined in Annex III, Figs. I and
2. When using E'R, E'G, E'B signals or luminance and colour-difference signals as defmed in Table II of Annex I, the
characteristics defined by Fig. 1 of Annex III will apply.

Note - The values shown for the luminance filter, used when sampling at 13.5 MHz, given in Fig. 1 of Annex III should
be considered as provisional. Administrations are requested to perform urgent studies to confirm these values.

*
Main digital television terms used in the Recommendation are defined in Report 629.
Reprinted with the prior authorization of the International Telecommunications Union (ITU) as copyright holder from
Recommendations and Reports of the CCIR, 1986. The choice of material to be excerpted has been made by Brooktree and,
therefore, docs not affect the responsibility of the ITU.
4 - 25

CCIR-601-1

Industry Standards
2•

Extensible family of compatible digital coding standards
The digital coding should allow the establishment and evolution of an extensible family of compatible digital coding
standards.
It should be possible to interface simply between any two members of the family.
The member of the family to be used for the standard digital interface between main digital studio equipment, and for
international programme exchange (i.e. for the interface with video recording equipment and for the interface with the
transmission system) should be that in which the luminance and colour-difference sampling frequencies are related in
the ratio 4: 2: 2.

In a possible higher member of the family the sampling frequencies of the luminance and colour-difference signals (or,
if used, the red, green and blue signals) could be related by the ratio 4 : 4 : 4. Tentative specifications for the 4 : 4 : 4
member are included in Annex I (see Note).
Note - Administrations are urgently requested to conduct further studies in order to specify parameters of the digital standards for
other members of the family. Priority should be accorded to the members of the family below 4 : 2 : 2. The number of additional
standards specified should be kept to a minimum.
3•

Specifications applicable to any member of the family

3.1
Sampling structures should be spatially static. This is the case, for example, for the orthogonal sampling structure
specified in § 4 of the present Recommendation for the 4: 2: 2 member of the family.
3.2
If the samples represent luminance and two simultaneous colour-difference signals, each pair of colour-difference
samples should be spatially co-sited. If samples representing red, green and blue signals are used they should be co-sited.
3.3
The digital standard adopted for each member of the family should permit world-wide acceptance and application in
operation; one condition to achieve this goal is that, for each member of the family, the number of samples per line specified for
52S-line and 62S-line systems shall be compatible (preferably the same number of samples per line).

Encoding parameter values for the 4 : 2 : 2 member of the family

The following specification (Table 1) applies to the 4 : 2 : 2 member of the family, to be used for the standard digital
interface between main digital studio equipment and for international programme exchange.

CCIR-601-1

4 - 26

Industry Standards
TABLE I - Encoding parameter values for the 4: 2: 2 member of the family
525-line, 60 fieldls (1)
systems

Parameters

L Coded signals: Y, CR, CB

These signals are obtained from gamma pre-corrected signals, namely: E'y,
E'R - E'y, E'B - E'y (Annex II, § 2 refers)

2. Number of samples per total line:
- luminance signal
- each colour-difference signal
(CR, CB)
3. Sampling structure

625-line, 50 fieldls (1)
systems

864
432

858
429

Orthogonal, line, field and frame repetitive. CR and CB samples co-sited with odd (1st, 3rd,
5th, etc.) Y samples in each line.

4. Sampling frequency
- luminance signal
- each colour-difference signal

13.5 MHz (2)
6.75 MHz (2)
The tolerance for the sampling frequencies should coincide with the tolerance for the line
frequency of the relevant colour television standard

5. Form of coding

Uniformly quantized PCM, 8 bits per sample, for the luminance signal and each colourdifference signal

6. Number of samples per digital active
line:
- luminance signal
-each colour-difference signal

720
360

7. Analog-to-digital horizontal timing
relationship:
- from end of digital active line to 16 luminance clock periods

12 luminance clock periods

OR
8. Correspondence between video
signal levels and quantization levels:
- scale

o to 255

- luminance signal

220 quantization levels with the black level corresponding to level 16 and the peak white
level corresponding to level 235. The signal level may occasionally excurse beyond level
235

- each colour-difference signal

225 quantization levels in the centre part of the quantization scale with zero signal
corresponding to level 128

9. Code-word usage

Code-words corresponding to quantization levels 0 and 255 are used exclusively for
synchronization. Levels 1 to 254 are available for video

(1) See Report 624, Table 1.
(2) The sampling frequencies of 13.5 MHz (luminance) and 6.75 MHz (colour-difference) are integer multiples of 2.25 MHz, the lowest
common mUltiple of the line frequencies in 525/60 and 625/50 systems, resulting in a static orthogonal sampling pattern for both.

4 - 27

CCIR-601-1

Industry Standards
ANNEX I
TENTATIVE SPECIFICATION OF THE 4 : 4 : 4 MEMBER OF THE FAMILY
This Annex provides for information purposes a tentative specification for the 4 : 4 : 4 member of the family of
digital coding standards.
The following specification could apply to the 4 : 4 : 4 member of the family suitable for television source equipment and high quality video signal processing applications.

TABLE II - A tentative specification for the 4 : 4: 4 member of the family

525-line. 60 fieldls
systems

Parameters

1. Coded signals: Y. CR. CB or R. G. B

These signals are obtained from gamma pre-corrected signals. namely: E'y. E'R E'y. E'B - E'y or E'R. E'G. E'B

2. Number of samples per total line for
each signal

3. Sampling structure

858

864

Orthogonal. line. field and frame repetitive. The three sampling structures to be
coincident and coincident also with the luminance sampling structure of the 4 : 2 :
2 member.

4. Sampling frequency for each signal

5. Form of coding

625-line. 50 field/s
systems

13.5 MHz

Uniformly quantized PCM. At least 8 bits per sample

6. Duration of the digital active line expressed in number of samples

At least 720

7. Correspondence between video signal
levels and the 8 most significant bits
(MBS) of the quantization level for each
sample:
- scale

o to 255

- R. G. B or luminance signal (1)

220 quantization levels with the black level corresponding to level 16 and the peak
white level corresponding to level 235. The signal level may occasionally excurse
beyond level 235

- each colour-difference signal (1)

225 quantization levels in the centre part of the quantization scale with zero signal
corresponding to level 128

(1) If used.

CCIR-601-1

4 - 28

Industry Standards
ANNEX II
DEFINITION OF SIGNALS USED IN THE DIGITAL CODING STANDARDS
1.

Relationship of digital active line to analogue sync. reference
The relationship between 720 digital active line luminance samples and the analogue aynchronizing references for
625-line and 525-line systems is shown below.

TABLE III

525-line,
60 fieldfs
systems

122T

16 T

nOT

I
OH
(leading edge ofline syncs.,
half-amplitude reference)
I
625-line,
50 fieldfs
systems

I
I
I

Digital active-line
period

Next line

I
OR
I
I

132T

12 T

nOT

I
I
I

T: one liminance sampling clock period (74 ns nominal).
The respective numbers of colour-difference samples can be obtained by dividing the number of luminance samples by
two. The (12, 132) and (16, 122) were chosen symmetrically to dispose of the digital active line about the permitted
variations. They do not form part of the digital line specification and relate only to the analogue interface.

Definition of the digital signals Y, CR, CB, from the primary (analogue) signals E'R, E'G and
E'B
This section describes, with a view to defining the signals Y, CR, CB, the rules for construction of these signals from
the primary analogue signals E'R, E'G and E'B. The signals are constructed by following the three stages described in §
2.1,2.2 and 2.3 below. The method is given as an example, and in practice other methods of construction from these
primary signals of other analogue or digital signals may produce identical results. An example is given in § 2.4.

2.1

Construction of luminance (E 'y) and colour·difference (E 'R' E 'y) and (E 'B - E'y) signals
The construction of luminance and colour-difference signals is as follows:
E 'y = 0.299 E R + 0.587E'G

+ 0.114 E'B

(See Note)

whence:
(E 'R - E 'y) = E'n - 0.299E'R - 0.587E 'G - 0.114E 11
= 0.701E 1R - 0.587E 1G - 0.114E 1B

and:
(E 'B' E 'y) =E 'B - 0.299E R - 0.587E 'G - 0.114E 'B
= - 0.299E 'R - 0.587E 'G + 0.886E B

Note - Report 624 Table II refers.
4 - 29

CCIR-601-1

Industry Standards
Taking the signal values as normalized to unity (e.g., 1.0 V maximum levels), the values obtained for white, black and
the saturated primary and complimentary colours are as follows:

TABLE IV

Condition

Ell

E'G

EII-E'y

EB-E y

White

1.0

Black

1.0

0.299

0.701

- 0.299

Green

1.0

0.587

- 0.587

Blue

1.0

0.114

- 0.114

0.886

1.0

0.886

0.114

- 0.886

1.0

0.701

- 0.701

0.299

1.0

0.413

0.587

0,587

Red

Yellow
Cyan
Magenta

Construction of re-normalized colour-difference signals (E'CR· and E'CB )

2.2

Whilst the values for E 'y have a range of 1.0 to 0, those for (E

11 - E 'y ) have a range of + 0.701 to - 0.701 and for (E 'B

- E 'y ) a range of + 0.886 to - 0.886. To restore the signal excursion of the colour-difference signals to unity (i.e.

+ 0.5

to - 0.5), coefficients can be calculated as follows:

=(0.5/0.701) =0.713; KB =(0.5/0.886) =0.564

Then:

E1CR = 0.713 (E 'B - E 'y ) = 0.500 E'R - 0.419E 'G - 0.081E 'B
and:

E'CB = 0.564 (E

B-E 'y ) = - 0.169E 'R

- 0.331E 'G + O.5ooE B

where E'CR and E'CB are the re-normalized red and blue colour-difference signals respectively (see Notes 1 and 2).

Note 1. - The symbols E'CR and E'CB will be used only to designate re-normalized colour-difference signals, i.e. having the same
nominal peak-to-peak amplitude as the luminance signal E 'y , thus selected as the reference amplitude.
Note 2. - In circumstances when the component signals are not normalized to a range of 1 to 0, for example, when converting
from analogue component signals with unequal luminance and colour-difference amplitudes, and additional gain factor will be
necessary and the gain factors KR ,KB should be modified accordingly.

CCIR-601-1

4 - 30

Industry Standards
2.3

Quantization

In the case of a uniformly-quantized 8-bit binary encoding. 28 • i.e. 256. equally spaced quantization levels are
specified. so that the range of the binary numbers available is from 0000 0000 to 1111 1111 (00 to FF in hexadecimal
notation). the equivalent decimal numbers being 0 to 255. inclusive.
In the case of the 4 : 2 : 2 system described in this Recommendation. levels 0 and 255 are reserved for synchronization
data. while levels 1 to 254 are available for video.
Given that the luminance signal is to occupy only 220 levels. to provide working margins. and that black is to be at
level 16. the decimal value of the luminance signal. Y. prior to quantization. is:
Y = 219 (E 'y) + 16.

and the corresponding level number after quantization is the nearest integer value.
Similarly. given that the colour-difference signals are to occupy 225 levels and that the zero level is to be level 128.
the decimal values of the colour-difference signals. CR and CB • prior to quantization are:
CR = 224 [0.713 (E'R - E'y )] + 128

and:
CB = 224 [0.564 (E'B - E 'y )] + 128

which simplify to the following:
CR

= 160

(E 'R - E 'y )] + 128

= 126

(E 'B - E'y )] + 128

and:

and the corresponding level number. after quantization. is the nearest integer value.
The digital equivalents are termed Y. CR and CB .
2.4

Construction of Y. CR. CB via quantization of E ·R. E'G. E 'B

In the case where the components are derived directly from the ganuna pre-corrected component signals E 'R • E 'G • E 'B •
or directly generated in digital form. then the quantization encoding shall be equivalent to:
E'RD (in digital form)

= int (219 E 'R) + 16

E 'GD (in digitalform) = int (219 E 'G) + 16
E 'BD (in digital form) = int (219 E 'B ) + 16

Then:
Y = (77 / 256) E 'RD + (150 / 256) E 'GD + (29 /256) E 'BD
CR = (131/256)E 'RD - (110/256) E 'GD - (21 / 256) E 'BD

+ 128

CB =-(44/256)E'RD -(87/256)E'GD +(131/256)ESD +128

4 - 31

CCIR-601-1

Broddree®

Industry Standards

taking the nearest integer coefficients, base 256. To obtain the 4 : 2 : 2 components Y, CR, CB ,low-pass filtering
and sub-sampling must be perfonned on the 4: 4 : 4 CR, CB signals described above. Note should be taken that slight
differences could exist between CR ,CB components derived in this way and those derived by analogue filtering prior to
sampling.

CCIR-601-1

4 - 32

Industry Standards
ANNEX III
FILTERING CHARACTERISTICS
50
40

OdB

30
20

12 dB

o
0

5.75 6.75

13 f14

13.5

FREQUENCY (MHz)

a ) Template for insertion loss I frequency characteristic

~'~C~====~"-1lL"
00.05 .:::::.::.:.:.:.:••:.:.:• :••:.:.:••:.::.:••:••:.:.:.:•: ••:.:.:.;.: 0

FREQUENCY (MHz)

5·············6
5.5+

t5.75

b) Passband ripple tolerance

ooooooooooooo..::..o.....................::o..oo.o.::.00

FREQUENCY (MHz)

5.75

c) Passband groupodelay tolerance

FIGURE 1 Specification for a luminance or RGB signal filter
used when sampling at 135 Mllz
0

Note.

The lowest indicated values in b) and c) are for 1 kHz (instead of 0 MHz).

4 33
0

CCIR0601 01

Broddree

Industry Standards

30~-4---+--~--+--4---+--~--+1~.~~-+--~--+-~~-+--~

W~-4---+--~--+--4~""m"-+--~--~rn-4~-+--~--+-~~-+--~

ilim
6dB

o~@@~g@~~~~wrnr~=-L-+-JL~~~t-J
o

2.75

3.375

6.75

FREQUENCY (MHz)

a) Template for insertion loss I frequency characteristic

0.1

0.5

---------------------------------.11
----------------------------------,0.02

O.OldB

-0.5
-0.1 '-------L------~----___r_I

3
2.75

FREQUENCY (MHz)

b) Passband ripple tolerance

~~~~EIh~
2
FREQUENCY (MHz)

3 dB LOSS FREQUENCY

c) Passband group-delay tolerance

FIGURE 2 - Specification for a colour-difference signal filter used when sampling at 6.75 MHz

Note. - The lowest indicated values in b) and c) are for 1 kHz (instead of 0 MHz).
CCIR-601-1

4 - 34

Industry Standards
60

~ h;; 55dB

50
~

~ f%%'

I""""'·'·

SEENOTE3-,
30

m~
I

".""""""",

6df

2.75 3.375

t t

6.25 6.75

FREQUENCY (MHz)

a) Template for insertion loss I frequency characteristic

I!E----i
2

O.ldB

2.75
FREQUENCY (MHz)

b) Passband ripple tolerance

FIGURE 3 - Specification for a digital jiIJer for sampling-rate conversion
from 4 : 4 : 4 to 4 : 2 : 2 colour-difference signals
Notes to Figs. 1, 2 and 3:
Note 1. - Ripple and group delay are specified relative to their values at 1 kHz. The full lines are practical limits and the dashed
lines give suggested lintits for the theoretical design.
Note 2. - In the digital filter, the practical and design limits are the same. The delay distortion is zero, by design.
Note 3. - In the digital filter (Fig. 3), the amplitude I frequency characteristic (on linear scales) should be skew:symmetrical
about the half-amplitude point, which is indicated on the figure.
Note 4. - In the proposals for the filters used in the encoding and decoding processes, it has been assumed that, in the post-filters
which follow digital-to-analogue conversion, correction for the (sin xix ) characteristic of the sample-and-hold circuits is provided.

4 - 35

CCIR-601-1

Industry Standards

CCIR-601-1

4 - 36

Industry Standards
SECTION llA:

CHARACTERISTICS OF SYSTEMS FOR MONOCHROME AND COLOUR TELEVISION
Recommendations and Reports
Report 624-3
CHARACTERISTICS OF TELEVISION SYSTEMS
(1974 - 1978 - 1982 - 1986)

The following Tables, given for information purposes, contain details of a number of different television systems in
use at the time of the XVIth Plenary Assembly of the CCIR, Dubrovnik, 1986.
A list of countries and geographical areas, and the television systems used, are given in Annex I.
Specifications of the SECAM IV colour television system, which is still under consideration, are given in Annex II.

•
Reprinted with the prior authorization of the International Telecommunications Union (ITU) as copyright holder from
Recommendations and Reports of the CCIR, 1986. The choice of material to be excerpted has been made by Brooktree and,
therefore, does not affect the responsibility of the ITU.

4 - 37

CCIR-624-3

T ABLE I - Basic characteristics of video and synchronizing signals.

System

~
.:.,

Characteristics

Item

B,G

D,K

Rec.472
(2)

r.t.l

Number of lines per picture (frame)

Field frequency, nominal value
(fields/second) (3)

525

625

60
(59.94)

C/.)

3(a)

Line frequency fH and tolerance when
operated non-synchronously
(Hz) (3) (;)
Maximum variation rate of line
frequency valid for monochrome
transmission (%/s )(1) (8)

-I>-

'"
00

4(10)

Nominal
levels
of the
composite
video signal
(see Fig. 1)
(%)

15 625
15750
15 625
15 625
15625
15 625
15625 (5)
15 625(5)
15 625
(15734.264
± 0.15%
± 0.02% ± 0.0001% ± 0.02%
± 0.02%
± 0.02%
± 0.02%
± 0.02%
± 0.0003%) (±O.00014%) (±o.oOOl %) (±0.0001%)
(6)
(±0.0001%) (±O.OOOl%) (±0.0001%) (±0.0001%)

0.15 (9)

0.05

blanking level
(reference level)

peak-white level

100

synchronizing level

-40

-40
(-43)

-43

7.5 ± 2.5

0-7

difference between black
and blanking level
peak level including
chrominance signal

(0)
120

133

133 (11)

115 (12)

Assumed gamma of display device for
which pre-correction of monochrome
signal is made

2.2

Nominal video bandwidth (MHz)

4.2

Line synchronization

see Table 1-1

Field synchronization

see Table 1-2

[

o (colour) o (colour)
0-7 (mono.) 0-7 (mono.)
115 (12)

5.5

r.t.l

o +5
4l

124 (12)

(14)

2.8 (13)

5.0 or
5.5 or
6.0

J
18

Industry Standards
Notes for previous page:
(1) The values in brackets apply to the combination

NIPAL used in Argentina.

(2) Figures are given for comparison.
(3) Figures in brackets are valid for colour transmission.
(4) In order to take full advantage of precision offset when the interfering carrier falls in the sideband of the upper video range
(greater than 2 MHz) of the wanted signal a line-frequency stability of at least 2 x 10-7 is necessary.

(5) The exact value of the tolerance for line frequency when the reference of synchronism is being changed requires further study.
(6) When the reference of synchronism is being changed, this may be relaxed to 15 625

± 0.02%.

(1) These values are not valid when the reference of synchronism is being changed.
(8) Further study is required to defme maximum variation rate of line frequency valid for colour transmission. See in this regard
[CCIR, 1978-82). In the UK this is 0.1 Hz/s [CCIR, 1982-86b).
(9) The values used in Japan are ± 0.1.

(10) It is also customary to define certain signal levels in 625-line systems, as follows:
Synchronizing level - 0
Blanking level
- 30
Peak white-level
- 100
For this scale, the peak level including chrominance signal for system D, KJSECAM equals 110.7. (See [CCIR,
1982-86a].)
(11) Value applies to PAL signals.
(12) Values apply to SECAM signals. For programme exchange the value is 115.
(13) Assumed value for overall gamma approximately 1.2. The gamma of the picture tube is defined as the slope of the curve
giving the logarithm of the luminance reproduced as a function of the logarithm of the video signal voltage when the brightness
control of the receiver is set so as to make this curve as straight as possible in a luminance range corresponding to a contrast of
at least 1/40.

(14) In Recommendation 472, a gamma value for the picture signal is given as approximately 0.4.

4 - 39

CCIR-624-3

Industry Standards

c
- .... -- .... -- .... _2.

(a) NTSC and PAL systems

______ .... __ .. __2

(b) SECAM system

FIGURE 1 - Levels in the composite signal and details of line-synchronizing signals
blanking level

4 difference between black and blanking levels

2 peak white-level

5 peak-to-peak value of burst

3 synchronizing level

6 peak-to-peak value of colour sub-carrier
7 peak level including chrominance signal

CCIR-624-3

4 -40

Industry Standards
TABLE 1-1 - Details of line synchronizing signals (see Fig. 1)
Durations (measured between half-amplitude points on the appropriate edges) for various system

Symbol Characteristics

Nominal line period

Line-blanking interv al

Interval between time datum (011) and back edge
of line-blanking signal (~s)

Front porch

Synchronizing pulse

Build-up time (10 to 90%) of the edges of the
line-blanking signal (~s)

Build-up time (10 to 90%) of the
line-synchronizing pulses (~s)

(~s)

M(l)

N(2)

B,G,H.I,D,K.KI.L
(sec also Rec. 472)

63.492
(63.5555)

64 (3)

10.2 tol1.4
(10.9 ± 0.2)

10.24 to 11.52
(12 ± 0.3)

12 ± 0.3 (4)

8.9 to 10.3
(9.2 to10.3)

8.96 to 10.24
(10.5)

10.5 (5)

1.27 to 2.54
(1.27 to 2.22)

1.28 to 2.56
(1.5 ± 0.3)

1.5 ± 0.3 (4) (6)

4.19 to 5.71
(4.7 ± 0.1)

4.22 to 5.76
(4.7 ± 0.2)

4.7 ± 0.2

<= 0.64
«= 0.48)

<= 0.64
(0.3 ± 0.1)

0.3 ± 0.1

<= 0.25

<= 0.25
(0.2 ± 0.1)

0.2 ± 0.1(1)

(I) Values in brackets apply to M/NTSC.

e) The values in brackets apply to the combination NIP AL used in Argentina.
e) In France, and the countries of the OIRT, the tolerance for the instantaneous line period value is ± 0.032 ~s.
(4) In 625-line countries using Teletext System B as specified in the Annex to Recommendation 653 to reduce the possibilities of
data loss, the following values are preferred [CCIR, 1982-86c and dJ:
a) line blanking interval: 12

+ 0.0 ~s
- 0.3

b) front porch: 1.5 + 0.3 ~s

- 0.3
(5) Average calculated value, for information. For system I the value is 10.4 [CCIR, 1982-86bJ.
(6) For system I, the values are 1.65 ± 0.1.

c?)

For system I. the values are 0.25 ± 0.05.

4 - 41

CCIR-624-3

Industry Standards
FIGURE 2- Details of field-synchronizing waveforms
FIGURES 2.1 - Diagrams applicable to all systems except M

SECOND FIELD

FIRST FIELD

SEE FIG. 2-1c

FIGURE 2.la - Signal at beginning of each first field

A IiA
I

AiI

I
I

A A A A A A A A A A A

I
I
I

I
I

I-!
FIRST FIELD

SEE FIG. 2-1c

SECOND FIELD

FIGURE 2.1b - Signal at beginning of each second field

Note 1. -- !>(!.!> indicates an unbroken sequence of edges of line-synchronizing pulses throughout the field-blanking period_
Note 2. -- At the beginning of each first field. the edge of the field-synchronizing pulse. OV. coincides with the edge of a
line-synchronizing pulse if I is an odd number of half-line periods as shown.
Note 3. -- At the beginning of each second field. the edge of the field-synchronizing pulse. OV. falls midway between the edges of two
line-synchronizing pulses if I is an odd number of half-line periods as shown.

CCIR-624-3

4 -42

Industry Standards

-- - -- -

- - - -BLANKING LEVEL

-..J

H/2

- - - . _ SYNCLEVEL

H/2

(The durations are measured to the half-amplitude points on the appropriate edges)

FIGURE 2.lc - Details of equalizing and synchronizing pulses

4 - 43

CCIR-624-3

BroddreeQP

Industry Standards
FIGURE 2· Details of field· synchronizing waveforms
FIGURES 2.2· Diagrams applicable to system M

SECOND FIElD

FIRST FIElD 1

SEE FIG. 2-2c

FIGURE 2.la - Signal at beginning of each first field

FIRST FIElD

SECONDFIElD i - - - i

SEE FIG. Z,2c

FIGURE 2.2b - Signal at beginning of each second field

Note 1. -- MIl indicates an unbroken sequence of edges of line-synchronizing pulses throughout the field-blanking period.
Note 2. -- Field-one line numbers start with the first equalizing pulse in Field 1, designated DEl in Fig. 2.2a.
Note 3. -- Field-two line numbers start with the second equalizing pulse in Field 2, one-half-line period after
CCIR-624-3

4 -44

in Fig. 2.2b.

Industry Standards

IIr--~~----------- ~GUMa

- - - - - - - - SYNCUMa

q
H/2

FIGURE 2.2c - Details of equalizing and synchronizing pulses

4 -45

CCIR-624-3

Industry Standards
TABLE 1-2 - Details of field synchronizing signals (see Fig. 2)
Durations (measured between half-amplitude points on the appropriate edges) for various systems

Symbol

Characteristics

B,G,H,I,D,K,Kl,L
(see also Rec. 472)

Field period (ms)

16.667 (2)
(16.6833)

Field-blanking period (for H and a,
see Table I-I)

(19 to 21)

(19 to 25)H +a

25H+a

H+a(3)

(25H+a)

<= 6.35

<= 6.35
(0.3 ± 0.1)

0.3 ± 0.1

/ (4)

Build-up time (10 to 90%) of the edges of
field-blanking pulses (l1s)

k(4)

Interval between front edge of field-blanking
interval and front edge of first equalizing
pulse (l1s)

(1.5 ± 0.1)

Duration of first sequence of equalizing pulses

Duration of sequence of synchronizing pulses

311

311
(2.511)

2.511

Duration of second sequence of equalizing
pulses

311
(2.511)

2.511

Duration of equalizing pulse (j1s)

(2.3 ± 0.1) (6)

2.30 to 2.56
(2.35 ± 0.1)

2.35 ± 0.1

Duration of field-synchronizing pulse (l1s)

27.1
(nominal value)

26.52 to 28.16
(27.3)

27.3 (1)
(nominal value)

Interval between field-synchronizing
pulses (j1s)

(4.7 ± 0.1)

3.84 to 5.63
(4.7 ± 0.2)

4.7 ± 0.2 (8)

Build-up time (10 to 90%) of synchronizing
and equalizing pulses (j1s)

<= 0.25

<= 0.25
(0.2 ± 0.1)

0.2±0.1 (9)

3±2(5)
(systems B/SECAM,
G/SECAM, D, K, Kl and L
only; no ref. in Rec. 472)

2.5H

(2.5 H)

(1) The value in brackets apply to the combination N/PAL used (5) This value is to be specified more precisely at a later date.
in Argentina.
(6) The following specification is also applied in Japan: an
(2) The value in brackets applies to the M/NTSC system.
equalizing pulse has 0.45 to 0.5 times the area of a linesynchronizing pulse.
(3) The following values are used in Japan:
(1) For system I : 27.3 ± 0.1.
0.07v + O.Olv for colour transmission.

-Ov

O.05v =+00.03v for monochrome transmission,

(8) For system I: 4.7 ± 0.1.

where v is the field period.

(9) For system I : 0.25 ± 0.05.

- v

(4) Not indicated in the diagram.

CCIR-624-3

4 -46

TABLE II - Characteristics of video signal for colour television

Colour television system
Characteristics
Item

B,D,G,H,

MJPAL

M/NTSC

N/PAL
2.1

2.2

2.3

...
:!:i
2.4

x
0.67
0.21
0.14

Assumed chromaticity
coordinates (ClE, 1931)
for primary colours of
receiver

Red
Green
Blue

Chromaticity coordinates
for equal primary signals
ER=EG=EB

Illuminant C

I/PAL

0.33
0.60
0.06

(2)
x=0.310
y = 0.316

Illuminant 065

x = 0.313
Y = 0.329

(3)

Assumed ganuna value of the
receiver for which the
primary signals are
(4)
pre-corrected

(2)

2.2

2.8

E'y = 0.299 ER + 0587 E'G + 0.114 E'B

Luminance signal

Chrominance signals
(Colour-difference)

x
0.64
0.29
0.15

(5)

E'R' E'G and E'B are ganuna - pre-corrected primary sigoals

2.5

N/PAL(l)

Red
Green
Blue

0.33
0.71
0.08

B, 0, G, H, K, KI,
L/SECAM

EI = - 0.27(EB -Ey)
+ 0.74(E'R -E'y)
E'Q = 0.41(E'B -E'y)
+ 0.48(ER -E'y)

(6)

E'U = 0.493(E'B - E'y)

D'R = -1.9(E'R-E'y)

E'V = 0.877(E'R - E'y)

DB = 1.5(E'B-E'y)

gOO

2.6

Attenuation of
colour-difference signals

dB MHz
{
< 3at1.3
Ef
>= 20 at 3.6

()

0..

...'"

{
EQ

dB MHz

E'U {

< 2 at 1.3

E~ {<=3 at 1.3

E'V

> 20 at 3.6

< 2 at 0.4
< 6 at 0.5
<= 6 at 0.6

>=20 at4

~R{ <=3 at 1.3
DB

>= 30 at 3.5
Low frequency
pre-correction not
taken into acount

(I)

.:..,

dB MHz

E'U < 3 at 1.3
E'V

> 20 at 3.6

en
...,.

a
0..
00

(')
(')

s-o..

Colour television system

:;:;

Characteristics
Item

2.7

M/NTSC

M/PAL

B,D,G,H,
N/PAL

B, D, G, H, K, KI,
L1SECAM

l/PAL

For sinusoidal signals:
V'R*=ABF (f )V'R

Low Frequency
pre-correction of colour
difference signals

ViJ*=ABF (f )viJ
ABP(f)= 1+ j(flfJ)
1 + j(f{3fJ)
f = signal frequency
(kHz)
fl = 85 kHz

N/PAL(l)

r:/}

~
CIJ

...-I-

0..

r:/}

(8)
(See Fig. 6 for the
amplitude response)

2.8
.I>.I>-

Time-coincidence error
between luminance and
chrominance signals (J.ls)

< 0.05
Excluding
pre-correction for
receiver response

2.9

EM=E'y + G cos 2rt

Equation of composite
colour signal

EM=E'y+

EM = E'y + E'U sin2rtf,c' ± E'vcos 2rtf,c'

+E'Q sin(2rtf sc' + 33 ')+
+E'/ cos(2rtfsc' + 33 ')

where:

where:
E' y, see item 2.4
E'U and E'V, see item 2.5

E'y, see item 2.4
E'Q and Ej, see item 2.5
f sc see item 2.11
(See also Fig. 4a)

2.10
'-----

Type of chrominance
sub-carrier modulation
- - - - - - - _ .. _---_ .. _-

f sc, see item 2.11
The sign of the E'V component is the same as that of the
sub-carrier burst (changing for each line)
(see item 2.16 and Fig. 4b)

Suppressed-carrier amplitude-modulation of two sub-carriers in quadrature

(fOR' +MOR fa V'R* dt)

or EM= E'y +G cos 2rt
(fOB'+MoR JiOV'B*dt)

alternately from line to
line where:
E'y, see item 2.4
fOR and fOR, see item 2.11
~fOR

and MOB,
see item 2.12
V'R* andV'B*' see item 2.7
G, see item 2.13
Frequency modulation

~
~

Colour television system
Characteristics
Item

2.11

M/NTSC

Chrominance sub-carrier
frequency
(a)nominal value and
tolerance (Hz)
(b)relationship between
chrominance sub-carrier
frequency f se
and line frequncy fH

MJPAL

B,D,a,H,
N/PAL

3579545 ± 10 3 575 611.49 ± 10 4 433 618.75 ± 5

B,D, a, H, K, KI,
4'SECAM

N/PAL(I)

fOR = 4 406250 ± 2000

3 582 056.25 ± 5

I/PAL
4 433 618.75 ±
(9) (10)

fOR = 4250000 ± 2000
(11)

= 455 f

909

fse=-;r-fH

f se=

e135

1) f H
-4- + 625

Unmodulated sub-carrier
at beginning of line
282fHlorfoR

1) fH

f le= (917
-4-+ 625

272 fHlor fOB (12)

.j>.

2.12

Nominal
deviation
0'*= 1

Bandwidth of chrominance
sidebands (quadrature
modulation of
sub-carrier) (kHz)

+620
f se

-1300

+570

+600
f se

f se

-1300

(14)

+1066

+620

f se

- 1300
AfaR

(15)

Frequency deviation of
chrominance sub-carrier
(frequency modulation of
sub-carrier) (kHz)

Maximum
deviation

AfOB

(15)

280± 9
(± 14)

+350 ± 18
(±35)
-506±25
(± 50)

230±7
(± 11.5)

+506±25
(± 50)
- 350± 18
(± 35)

- 1300

~
en

C/)
i

.-I'

a
0..

'"
,0

n
n
.....
o,
",
.$>.
.:.,

Colour television system
Characteristics
Item

2.13

MJPAL

M/NTSC

Amplitude of chrominance
G=
su b-carrier

E' 2+ E'
I

G=J E'

B.D.a.H.

N/PAL
2+ E'

B. D. a. H. K. KI.

IJPAL

N/PAL(l)

IJSECAM

CI.l

1+ j16F
G=M01+j1.26F

C/.)
.-t-

where the peak-to-peak
amplitude. 2M00 is
23 ± 2.5% of the
luminance amplitude
(between blanking level
and peak-white)

=r
g§

CI.l

fO
f

F=---

where fo =4286 kHz
and fo is the instantaneous

sub-carrier frequency .
The deviation of
frequency fo. from its
nominal value due to
misalignment of the
circuits concerned should
not exceed ± 20 kHz.
(See Fig. 7 for the
amplitude response)

.$>.

2.14

Synchronization of
chrominance sub-carrier

(g) Start of sub-carrier
burst (see Fig. 1a) (l1s)

Sub-carrier burst on
blanking back porch
14.71 to 5.71 (5.3
nominal) at least
0.38 115 after the
trailing edge of line
synchronization signal

(h) Duration of sub-carrier 12 23
3 11
burst (see Fig. 1a) (115)
± ::y~leS)

Sub-carrier burst on blanking back porch

5.8 ± 0.1
after epoch ~

5.6 ± 0.1 after epoch ~

(18)

2.52 ± 0.28
(9 ± 1 cycles)

2.25

± 0.23

(10 ± 1 cycles) 1

12.51 ± 0.28 1
(9 ± 1 cycles)

Colour television system
Item

Characteristics
M/NTSC

B,D,G,H,
N/PAL

MJPAL

JJPAL

2.15 Peak-to-peak value of
chrominance sub-carrier
burst
(see Fig. la) (19)

4/1 0 of difference
between blanking
level and peak
white-level ± 10%

3{1 of difference between blanking level and peak
white-level ± 10% For systems and I, the tolerance is ± 3%
(16)(17)
(16)

2.16 Phase of chrominance
sub-carrier burst
(see Fig la)

1800 relative to
(E'B - E'y) axis

135 0 relative to E'U axis with the following sign (see Fig. 4b)

.,.

(see Fig. 4a)
IntheNTSC
sequence of four
colour fields,
field 1 is identified
with Note (20)
(see also Fig. 5c)

N/PAL(I)

!
~

Field Number (21)
1
Line

Burst blanking sequence (see Figs. 5a and 5b)

ill IV I

ill IV

....

even
odd

2.17 Blanking of chrominance
sub-carrier

B, 0, G, H, K, K1,
L/SECAM

11 lines of
Following each
equalizing pulse and field-blanking
.also during the broad interval:
260 to 270
synchronizing
522 to 7
pulses in the
259 to 269
field-blanking
223 to
8
interval
(see Fig. 5b)

~
~

.:.,

9 lines of the field-blanking interval:
lines 311 to 319 inclusive
6 inclusive
623 to
310 to 318 inclusive
5 inclusive
622 to
(See Fig. 5a)

(a) from leading edge of
line-blanking signal up
to i = 5.6 ± 0.2 (J.Ls)
after epoch OR,
i.e. during c + i
(see Fig. Ib) (13)
(b) During field-blanking
interval, excluding
frame identification
signals, or, in
countries where this is
possible, during the
whole of the
field-blanking interval
(See item 2.18)

CI.l

CZl
.....,..

§
0-

a
CI.l

n
:U>

N/PAL(I)

(ZJ

en
.-I'

S.
(ZJ

Shape 01 video signals
corresponding to
identification signals:
For lines D'R - Trapezoid
with linear variation from
beginning of line
on 15 ± 51ls from 0 up to
level + 1.25 and then
constant at the level
+ 1.25 ± 0.06 (±0.13)
(See Fig. 8)

!
~

---

------

Colour television system
Item

Characteristics
M/NTSC

MJPAL

B,D,G,H,
N/PAL

IJPAL

B, D, G, H, K, KI,

I../SECAM
For lines D'B - Trapezoid
with linear variation from
the beginning of the line
on 18 ± 6 I1s (20 ± 10118)
from 0 down to level
-1.52 and then constant at
the level
-1.52 ± 0.07 (± 0.15)
(see Fig. 8) (IS)

N/PAL(I)

~
~

Peak-to-peak amplitude of
identification signals:
For lines DIB:
500±5OmV
For lines DIR:

.;..
V\

540+ 4OmV
-5OmV
if amplitude of luminance
signal (between blanking
level and peak white)
equals 700mV

Maximum deviation during
transmission of
identification signals
(kHz):
For lines D'R:
+350 ±18 (±35)
For lines D'B:

-350 ±18 (±35)
(IS)

~
..,

CIJ

en
f""'Io

a
0CIJ

•

Industry Standards
(1) These values apply to the combination N/PAL used in Argentina. Only those values are given in this colunm which are
different from the values given in the colunm B, G, H, N/PAL.
(2) For SECAM systems and for existing sets, it is provisionally allowed to use the following chromaticity coordinates for the
primary colours and white:

x
Red
Green
Blue
White

0.67
0.21
0.14
0.310

y
0.33
0.71
0.08
0.316 (C- white)

(3) In Japan, the chromaticity of studio monitors is adjusted to a D-white at 9300 K.
(4) The primary signals are pre-corrected so that the optimum quality is obtained with a display having the indicated value of
gamma.
(5) In certain countries using the SECAM systems and in Japan it is also permitted to obtain the luminance signal as a direct
output from an independent photo-electric analyser instead of from the primary signals.
(6) For the SECAM system, it is allowable to apply a correction to reduce interference distortions between the luminance and
chrominance signals by an attenuation of the luminance signal components as a function of the amplitude of the luminance
components in the chrominance band.

(7) This value will be defined more precisely later.
(8) The maximum deviations from the nominal shape of the curve (sec Fig. 6) should not exceed
from 0.1 to 0.5 MHz and ± 1.0dB in the frequency range from 0.5 to 1.3 MHz.

± 0.5 dB

in the frequency range

(9) When the signal originates from a portable of overseas source the tolerance on the frequency may be relaxed to
Maximum rate of variation of I,e: 0.1 Hz/s.

±5

Hz.

(10) This tolerance may not be maintained during such operational procedures as "genlock".
(11) A reduction of the tolerance is desirable.
(12) The initial phase of the sub-carrier undergoes in each line a variation defined by the following rule:
From frame to frame: by 0°: 180°: 0°: 180°: and so on, and also from line to line in either one of the following two patterns:
0°: 0°: 180°: 0°: 0°: 180°: and so on,
or 0°: 0°: 0°: 180°: 180°: 180°: and so on.
(13)

I.e ± 1300 kHz is adopted in the People's Republic of China.

(14) The unity value represents the amplitude of the luminance signal between the blanking level and the peak white-level.
(15) Provisionally, the tolerances may be extended up to the values given in brackets.
(16) During transmission of a monochrome programme of significant duration, in order to ensure satisfactory operation of
colour-killers in receivers, all signals having the same nominal frequency as the colour sub-carrier that appears in the
line-blanking interval, should be attenuated by at least 35 dB below the peak-to-peak value of the burst given in item 2.15,
column 3 of Table II, and shown as Item 5 in Fig.1.
(17) The value given in Note (16) is accepted on a tentative basis.
(18) Transmitter pre-correction for receiver group delay is not included.
(19) For the use of automatic gain control circuits, it is important that the burst amplitude should maintain the correct ratio with
the chrominance signal amplitude.

CCIR-624-3

4 - 54

Industry Standards
(20) Field 1 of the sequence of four fields in the NTSC video signal is dermed by a whole line between the first equalizing pulse
and the preceding horizontal synchronizing pulse and a negative-going zero-crossing of the reference sub-carrier nominally at
the 50% point of the first equalizing pulse. The zero-crossing of the reference sub-carrier shall be nominally coincident with the
50% point of the leading edges of all horizontal synchronizing pulses for programme integration at the studio.
(21) Field 1 of the sequence of eight colour fields is defined as that field, where the phase q> E'u of the extrapolated EU component
(see item 2.5 of Table IT) of the video burst at the hall amplitude point of the line synchronizing pulse of line 1 is in the range

-90o <=q> E U<90°.
(22) The value of the tolerance will be dermed more precisely later.
(23) The line identification method is preferable, because it will enable agreements to be reached subsequently on the suppression
of frame identification signals in international programme exchanges. In the absence of such agreements, signals meeting the
SECAM standard are regarded as comprising such identification signals.
In France, a decree of 14 March 1978 specified that colour TV receivers placed on sale on or after 1 December 1979 must use the
line identification method of decoding [CCIR, 1982-86cl.
(24) The order in which the identification signals DR* and DB* appear on the four fields of a complete cycle given in Fig. 9 is in
conformity with Recommendation 469-1.

•

4-55

CCIR-624-3

TABLE III - Characteristics of the radiated signals (monochrom£ and colour)
(')

Item

'"~

w
1

Characteristics

Nominal
radio-frequency channel
bandwidth (MHz)

N(I)

B,G

B:7
G:8

D,K

gOO

.-T

Sound carrier relative to
vision carrier (MHz)

Frequency Nearest edge of channel
spacing (See relative to vision
Fig. 10)
carrier (MHz)
Nominal width of main
sideband (MHz)

+4.5 (2)

+4.5

+ 5.5
± 0.001
(3), (4), (5)

+ 5.5

+ 5.9996
± 0.0005

+ 6.5
± 0.001

+ 6.5

- 1.25

4.2

5.5

0.75

1.25

0.75

1.25

20 (-1.25)
42 (- 3.58)

20 (-1.25)
42 (-3.5)

20 (- 2.7)
30 (- 4.3)
ref.: 0 (+ 0.8)

15 (- 2.7)
30 (- 4.3)
ref.: 0 (+ 0.8)

0..

a
00

,...-.j>.

'"
6

Nominal width of
vestigial sideband
(MHz)
Minimum attenuation of vestigial
sideband (dB at MHz)(I)

20 (-1.25) 20 (-1.75) 20 (-3.0) 20 (-1.25)
20 (-3.0) 20 (-3.0) 30 (-4.43) 30 (-4.33
± 0.1)
30 (-4.43)

(1)
7

C3F neg.

C3F pos.

synchronizing
level

100

blanking level

72.5 to
77.5

72.5 to 77.5
(75 ± 2.5)

75 ± 2.5

72.5 to
77.5

76±2

75 ± 2.5

30±2

difference between
black and
blanking level

2.88 to
6.75

2.88 to 6.75

o to 2
(nominal)

o to 7

0
(nominal)

o to 4.5

peak-white level

10 to 15

10 to 12.5 10 to 12.5
10 to 15
(10 to 12.5) (10) (12)

20±2

10 to 12.5
(13) (14)

10 to 12.5

100 (= 110)
(15)

Type and polarity of vision
modulations

Levels in the
radiated signal
(% of peak
carrier)

(8) (9)

- - - _... _-

(10)

(11)

I
Item

Characteristics

N(I)

B.G

D.K

L
A3E

Type of sound modulation

F3E

Frequency deviation (kHz)

±25

±50

Pre-emphasis for modulation ijJ.s)

Ratio of effective radiated powers of
vision and sound (16)

10/1 to 5/1
(17)

10/1 to 5/1

20/1 to 10/1
(3) (18) (19)

5/1 to 10/1

5/1
10/1 (20)

10/1 to 5/1
(21)

10/1

Pre-correction for receiver
group-delay characteristics at
.medium video frequencies (ns)
(see also Fig. 3)

1 MHz O± 100
1 MHz O± 100
1MHzO± 60

(22)

(238)

+60

- 170
(nominal)

(23b)

(22)

10/1

-..I

Pre-correction for receiver
group-delay characteristics at colour
subcarrier frequency (ns) (see Fig. 3)

-170
(nominal)

-170

gen

a
0-

Industry Standards
(1) The values in brackets apply to the combination NIPAL used in Argentina.
(2) In Japan, the values + 4.5

± 0.001

are used.

(3) In the Federal Republic of Germany a system of two sound carriers is used, the frequency of the second carrier being 242.1875
kHz above the frequency of the first sound carrier. The ratio between vision Isound e.r .p. for this second carrier is 100/1. For
further information on this system see Report 795. For stereophonic sound transmissions a similar system is used in Australia
with vision/sound power ratios being 20/1 and 100/1 for the first and second sound carriers respectively.
(4) New Zealand uses a sound carrier displaced 5.4996 MHz from the vision carrier.
(5) The sound carrier for single carrier sound transmissions in Australia may be displaced 5.5
carrier.

± 0.005 MHz from

the vision

(6) In some cases, low-power transmitters are operated without vestigial-sideband filter.

(I) For B/SECAM and G/SECAM: 30 dB at - 4.43 MHz, within the limits of ± 0.1 MHz.
(8) In some countries, members of the OIRT, additional specifications are in use:
(a) not less than 40 dB at - 4.286 MHz ± 0.5 MHz,
(b) 0 dB from -0.75 MHz to + 6.0 MHz,
(c) not less than 20 dB at ± 6.375 MHz and higher;
Reference: 0 dB at + 1.5 MHz.
(9) In the People's Republic of China, the attenuation value at the point (- 4.33

± 0.1) has not yet been determined.

(10) Australia uses the nominal modulation levels specified for system I.
(11) In the People's Republic of China, the values 0 to 5 have been adopted.
(12) Italy is considering the possibility of controlling the peak white-level after weighting the video frequency signal by a
low-pass filter, so as to take account only those spectrum components of the signal that are likely to produce inter-carrier noise
in certain receivers when the nominal level is exceeded. Studies should be continued with a view to optimizing the response of
the weighted filter to be used.
(13) The USSR has adopted the value 15 ± 2%.
(14) A new parameter "white level with sub-carrier" should be specified at a later date. For that parameter, the USSR has adopted a
value of 7 ± 2%.
(15) The peak white-level refers to a transmission without color sub-carrier. The figure in brackets corresponds to the peak value
of the transmitted signal, taking into account the colour sub-carrier of the respective colour television system.
(16) The values to be considered are:
- the r .m.s. value of the carrier at the peak of the modulation envelope for the vision signal. For system L, only the luminance
signal is to be considered. (see Note (15) above);
- the r.m.s value of the urunodulated carrier for amplitude-modulated and frequency-modulated sound transmissions.
(17) In Japan. a ratio of 1/0.15 to 1/0.35 is used. In the United States, the sound carrier e.r.p. is not to exceed 22% of the
authorized vision e.r.p.
(18) It may be that the Austrian Administration will continue to use a 5/1 power ratio in certain cases, when necessary.
(19) Recent studies in India [CCIR, 1982-86f] confirm the suitability of a 20/1 ratio of effective radiated powers of vision and
sound. This ratio still enables the introduction of a second sound carrier.
(20) The ratio 1011 is used in the Republic of South Africa.
(21) In the People's Republic of China, the value 1011 has been adopted.

CCIR-624-3

4 - 58

Broddree®

Industry Standards

(22) In the Federal Republic of Gennany and the Netherlands the correction for receiver group delay is made according to curve B
in Fig. 3a). Tolerances are shown in the table under Fig. 3a). From [CCIR, 1966-69] it is learned that Spain uses curve A. The

OIRT countries using the B/SECAM and G/SECAM systems use a nominal pre-correction of 90 ns at medium video frequencies.
In Sweden, the pre-correction is 0 ± 40 ns up to 3.6 MHz. For 4.43 MHz, the correction is - 170 ± 20 ns and for 5 MHz it is 350 ±
80 ns. In New Zealand the pre-correction increases linearly from 0 ± 20 ns at 0 MHz to 60 ± 50 ns at 2.25 MHz, follows curve A
of Fig. 3a from 2.25 MHz to 4.43 MHz and then decreases linearly to - 300 ± 75 ns at 5 MHz. In Australia, the nominal
pre-correction follows curve A up to 2.5 MHz, the decreases 0 ns at 3.5 MHz, - 170 at 4.43 MHz and -280 at 5 MHz. Based on
studies on receivers in India, the receiver group delay pre-equalization proposed to be adopted in India at 1 MHz, 2 MHz, 3 MHz,
4.43 MHz and 4.8 Mhz are + 125 ns, + 150 ns, + 142 ns, - 75 ns, and - 200 ns respectively.
(238) Not yet determined. The Czechoslovak Socialist Republic proposes

+ 90 ns (nominal value).

(23b) Not yet determined. The Czechoslovak Socialist Republic proposes + 25 ns (nominal value).

4 - 59

CCIR-624-3

Industry Standards
120

r-..

-40

-80

-120

-160
-170

t!i

-200

-----

----- -----

-----

-240

:1\

-280

:
:

-320

: B

-360

-400

-440

4.43

3.58

Frequency (MHz)
(a) BIPAL and GlPAL systems
(See Table III (22»

(b) MIPAL and MINISC systems

FIGURE 3 - Curve of pre-correction for reciever group delay characteristics
Nominal values and tolerances (ns)

CCIR-624-3

Frequncy (MHz)

Curve A

CurveB

0.25
1.00
2.00
3.00
3.75
4.43
4.80

+30± 50
+ 60± 50
+60±50
O± 50
- 170 ± 35
- 260 ± 75

+5±0
+ 53 ±40
+90±40
+75 ±40
0±40
- 170 ± 40
-400±90

4 - 60

Industry Standards

0.877 (E'R - E'y)

E'I \
\

B
_ _ _ _ _ _ _ _T-_ _'--_ _ _ _ 0.483 (E'B- E'V)

B: phase of the burst

(a) NTSC system

0.877 (E'R - E'y) = EV

_ _ _ _----,~-_+-_ 0.483 (E'B - E'V) = EU

A : phase of the burst in odd lines of the first,
second, fifth and sixth fields and in even lines of
the third, fourth, seventh and eighth fields.
B : phase of the burst in even lines of the first,
second, fifth and sixth fields and in odd lines of
the third, fourth, seventh and eighth fields.

(b) PAL system

FIGURE 4 - Chrominance axes and phase of the burst

4 - 61

CCIR-624-3

Industry Standards

Oy
I
I
I
I

308

309

311

310

312

313

314

315

316

317

318

319

320

I
621

622

623

624

625

308

309

310

311

312

313

314

315

316

317

318

319

320

III

621

{

622

623

624

625

I
I
I
I
I
I
I
I
I
,I

III

FIGURE 5a - Burst blanking sequence in the B, G, Hand [IPAL systems

Oy:
I, II, III, IV:

B:
C:

CCIR-624-3

field-synchronizing datum.
first and fifth, second and sixth,
third and seventh. fourth and
eighth fields (see item 2.16 of
Table II)
phase of burst; nominal value + 135·
phase of burst; nominal value - 135·
burst-blanking intervals

4 - 62

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

r----

Industry Standards

Oy
I
I
I

1 519

1 520

1 521

522

523

1 524

1 525

nnnnr

B
D

257
F

259

1 258

260

1 261

1 262

263

264

1 265

266

267

1 268

269

270

519

521

520

272

III

271

522

523

524

525

1 268

1 269

F
N

1 257

258

259

260

1 261

1 262

263

1 264

1 265

1 266

1 267

1 270

271

1 272

I
I
I
I
I
I
I

r--

III
N

FIGURE 5b - Burst blanking sequence in the MIPAL system

Oy:
I, II, m, IV:

A:
B:
C:

field-synchronizing datum
first and fifth, second and sixth,
third and seventh, fourth and
eighth fields (see item 2.16 of
Table II
phase of burst; nominal value + 135°
phase of burst; nominal value - 135°
burst-blanking intervals

4 - 63

CCIR-624-3

Industry Standards

CCIR-624-3

4 -64

Industry Standards
Sources for Consumer Electronics Standards
CCIR

The International Radio Consultive Committee
International Telecommunications Union
Place Des Nations
CH-1211 Geneva
20 Switzerland
(011) 4122 730 5800

ccm

The International Telephone and Telegraph Consultive Committee
International Telecommunications Union
Place Des Nations
CH-1211 Geneva
20 Switzerland
(011) 4122 730 5851

EBU

European Broadcasting Union
The Technical Center of the EB U
32, Avenue Albert Lancaster
B-1180 Brussels
Belgium

EIA

Electronic Industries Association
1722 Eye Street, NW Suite 440
Washington, DC 20006
Headquaters:
(202) 457 4936
Standards:
(202) 457 4966

IEEE

Institute of Electrical and Electronics Engineers
Headquarters:
345 East 47th Street
New York, NY 10017
(212) 705 7900
Standards Offics:
(IEEE Service Center)
P.O. Box 1331
Piscataway, NJ 00855
(201) 981 0060

SMPfE

Society of Motion Picture and Television Engineers
595 W. Hartsdale Ave.
White Plains, NY 10607
(914) 761 1100

4 - 65

4 - 66

GRAPHICS
AND

IMAGING

PRODUCTS

APPLICATIONS

HANDBOOK

1 990

Introduction
Application Notes
Article Reprints
Industry Standards
Sales Offices

5- 1

•

Sales Offices

5-2

Sales Offices

Brooktree Sales Offices
Eastern US Office

Northeastern US Offices

Northwestern US Office

Brooktree Corporation
2000 Regency Parkway, Suite 144
Cary, NC 27511
Contact: Bruce Bradford
(919) 467-7418
FAX: (919) 460-9858

Brooktree Corporation
7 Buckskin Drive
Westboro, MA 01581
Contact: Paul Feldman
Contact: Alan Germain
(508) 870-5999
FAX: (508) 870-5897

Brooktree Corporation
4701 Patrick Henry Drive
Building 12
Santa Clara, CA 95054
Contact: Paul Van Eynde
(408) 732·0923
FAX: (408) 927-9273
Contact: David Kern
(408) 247-1469
FAX: (408) 748-1163

Western US Offices

European Offices

Asia-Pacific Office

Brooktree Corporation
21 Andalucia
Irvine, CA 92714
Contact: Stuart Friedman
(714) 756-0801
FAX: (714) 756-0820

Brooktree Corporation
17 Farm Place
London, W8 7SX
United Kingdom
Contact: Lauren Schlicht
44 (1) 792 2450
FAX: 44 (1) 792 2363

Brooktree Corporation
Kowa Building No.9, 4th Floor
1-8-10 Akasaka, Minato-ku
Tokyo 107
Japan
Contact: Jerry Coan (Japan)
Contact: Dennis Packard (Asia-Pacific)
(813) 588-0414
FAX: (813) 505-4120

Brooktree Corporation
1557 W. 208th St. #A
Torrance, CA 90501
Contact: John Somoza
(213) 320-7427
FAX: (213) 320-7506
Brooktree Corporation
5 Santa Elena
Rancho Santa Margarita, CA 92688
Contact: Marc SUltzbaugh
(714) 589-2404
FAX: (714) 589-2289

Brooktree Corporation
Kronstadter Str. 9
D8000 Munchen 80
West Germany
Contact: Reiner Pohl
49 (89) 937520
FAX: 49 (89) 9302123

Die Sales I Nonstandard Packages
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 31810-2696
(407) 298-7100
FAX: (407) 290-0164

5-3

•

5-4

Brooldree~
Bl"Ookt."ee COI"pOl"atioll
9950 Bames Canyon Road
San Diego, CA 92121-2790
Telephone (619) 452-7580
1 (800) VIDEO-IC
l
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date : 2013:08:14 21:03:22-08:00
Modify Date : 2013:08:14 22:12:43-07:00
Metadata Date : 2013:08:14 22:12:43-07:00
Producer : Adobe Acrobat 9.55 Paper Capture Plug-in
Format : application/pdf
Document ID : uuid:3f67bf80-24bb-234d-bf9a-c155a655c6f2
Instance ID : uuid:8771d31e-d392-a640-aa45-c07db20e0e38
Page Layout : SinglePage
Page Mode : UseNone
Page Count : 259

EXIF Metadata provided by EXIF.tools

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