1990_Burr Brown_Integrated_Circuits_Data_Book_Supplement_33b 1990 Burr Brown Integrated Circuits Data Book Supplement 33b
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-. ::s ;- - ... co -g ;- - Q. ...nn_. -_ ..c_. ~ CIt .. Q. g - g 0" - BURR-BROWN ~ integrated circuits data book supplement volume 33b o o en c - _'tJ~ - 'tJ CD 3 CD a ~-- Operational Amplifiers Instrumentation Amplifiers Isolation Amplifiers Model Index Models with ·S· page numbers are in this supplement. Other models are In Burr-Brown Integrated Circuits Data Book Volume 33. ACF2101 ................... S5-6 AD515 ........................ 2-13 AD632 .......................... 5-6 ADC71 .................... S9.1-4 ADC72 ....................... 9.1-4 ADC76 .................. S9.1-12 ADC80AG ............... 9.1-20 ADC80H .................. 9.1-28 ADC80MAH-12 ... ;... 9.1-36 ADC84 ..................... 9.1-44 ADC85H .................. 9.1-44 ADC87H .................. 9.1-44 ADC574A ................ 9.1-52 ADC600 ................... 9.2-89 ADC601 ................ S9.2-83 ADC603 ................ S9.2-99 ADC604 .............. S9.2-119 ADC614 .............. S9.2-134 ADC674A ................ 9.1-62 ADC700 ................ S9.1-2O ADC701 .............. S9.2-137 ADC774 ................ S9.1-32 ADC803 ................. 9.2-124 ADCS04 ................... 9.1-78 ADC7802 ............ 89.2-153 ADS574 ................ S9.1-42 AD8602 ................ S9.1-51 ADS774 ................ S9.1-42 ADSS07 ................ S9.1-59 ADSS08 ................ 89.1-59 ADS7800 .............. 89.1-72 CMP100 ................... 85-14 DAC63 ................... 6.2-135 DAC65 ................... 6.2-143 DAC70BH .................. 6.1-5 DAC71 ..................... 6.1-13 DAC71-CCD ............ 6.1-21 DAC72BH .................. 6.1-5 DAC80 ..................... 6.1-Zl DAC80P .................. 6.1-27 DAC85H .................. 6.1-35 DAC87H .................. 6.1-35 DAC667 .................. S6.1-5 DAc700 ...........:....... 6.1-43 DAC701 ................... 6.1-43 DAC702 ................... 6.1-43 DAC703 ................... 6.1-43 DAC705 ................... 6.1-53 DAC706 ...............:... 6.1-53 DAC707 ................... 6.1-53 DAC708 ................... 6.1-53 DAC709 ................... 6.1-53 DAC710 ....... ;........... 6.1-65 DAC711 ................... 6.1-65 DAC725 ................... 6.1-72 DAC729 ................... 6.1-BO DACSll ................... 6.1-90 DACS12 ................. 6.2-146 DACS13 .................. 86.1-7 DAC1200KP-V ........ 6.1-99 DAC1201KP-V ...... 6.1-103 DAC1600 ............... 6.1-108 DAC7541A ............ 6.1-112 DAC7545 ............... 6.1-120 DAC7BOO .............. S6.1-17 DAC7801 .............. 86.1-17 DAC7B02 .............. 86.1-19 DACS012 ............... 6.1-127 DIV100 ....................... 5-10 DSP-SYS603 ......... S14-28 DSP-SYS701 ......... S14-32 DSP101 ................... S14-4 DSP102 ................... S14-4 DSP201 ................. S14-16 DSP202 ................. S14-16 HI-506A ........................ 7-3 HI-507A ........................ 7-3 HI-508A ...................... 7-13 HI-509A ...................... 7-13 INA10l ....................... 3-11 INA102 ..................... 83-10 INA103 ..................... 83-22 INA104 ....................... 3·34 INA105 ....................... 3-45 INA106 ....................... 3-57 INA110 ....................... 3-65 INA117 ..................... 83-36 INA120 ..................... 83-50 IS0100 ......................... 4-8 IS0102 ....................... 4-20 180103 ....................... 84-8 IS0106 ....................... 4-20 180107 ..................... 84-16 180108 ..................... 84-24 180109 ..................... 84-24 IS0113 ..................... 84-32· IS0120 ....................... 4-44 IS0121 ....................... 4-44 IS0122P .................. 84-40 IS0212P .................. 84-51 LOG100 ...................... 5-18 MPCSOO ..................... 7-23 MPC801 ..................... 7-30 MPY100 ..................... 5-26 MPY534 ..................... 5-34 MPY600 ................... 85-25 MPY634 ..................... 5-41 OPAllHT ................... 2-17 OPA21 ........................ 2-21 OPA27 ........................ 2-Zl OPA27HT ................... 2-39 OPA37 •• :..................... 2-27 OPA37HT ................... 2-39 OPA77 ..................... S2-13 OPA10l ...................... 2-43 OPA102 ...................... 2-43 OPA111 ...................... 2-55 OPA121 ...................... 2-66 OPAl2B ...................... 2-72 OPA156A ................... 2-80 OPA177 ................... 82-13 OPA201 ...................... 2-86 OPA356A ................... 2-80 OPA404 ...................... 2-94 OPA445 .................... 2-104 OPA501 .................... 2-109 OPA5" .................... 2-1,7 OPA512 .................... 2-122 OPA541 ................... S2-22 OPA550 .................... 2-135 OPA600 .................... 2-137 OPA602 .................... 2-145 OPA603 ................... S2-30· OPA605 .................... 2-152 OPA606 .................... 2-158 OPA620 ................... 82-42 OPA621 ................... 82-58 OPA627 ................... 82-74 OPA633 ..................;.2-176 OPA637 ................... S2-74 OPA660 ................... S2-88 OPA675 ................... S2-90 OPA676 ................... S2-90 OPA1013 ............... 82-104 OPA2107 .................. 2-193 OPA2107 ............... 82-114 OPA2", .................. 2-,95 OPA2541 .................. 2-205 OPA2604 ............... 82-122 PCM53P ................ 6.2-152 PCM54 .................. 6.2-164 PCM55 .................. 6.2-164 PCM56P ................ 6.2-172 PCM58P ................ 6.2-180 PCM60P ............... 88.2-27 PCM61P ............... 86.2-35 PCM83P .u.~ 86.2-39 PCM64P ................ 6.2-194 PCM66P ............... 86.2-27 PCM75 .................. 9.2-136 PCM78P .............. S9.2-165 PCM1700P ......... 89.2-183 PCM1750P ......... S9.2-187 PGA100 ...................... 3-85 PGA102 ...................... 3-93 PGA200 .................... 3-1 03 PGA201 .................... 3-103 PGA202 ................... 83-60 PGA203 ................... 83-60 PWRXXXX ................. 14-1 .......... PWS725 .....................4-65 PWS726 ..................... 4-65 PWS727 ................... 84-62 PWS728 ................... 84-62 PWS740 ..................... 4-76 PWS745 ................... 84-69 PWS750 ................... 84-71 RCV420 .................... 3-111 RCV420 ................... 83-71 REF10 ........................ 5-49 REF10l ...................... 5-55 REF102 .................... 85-37 REF200 ...................... 5-63 SDM862 ..................... 11-3 SDM863 ..................... 11-3 SDM872 ..................... 11-3 SDM873 ..................... 11-3 SHC76 .......................... 8-3 SHC85 .......................... 8-7 SHC298 ...................... 8-11 SHC298A ................... 8-11 SHC600 ...................... 8-18 SHC601 ...................... 8-22 SHC702 ................. 9.2-118 SHC702 .............. S9.2-137 SHCS03 ...................... 8-26 SHC804 ...................... 8-26 SHC5320 .................... 8-32 UAFll ........................ 5-74 UAF21 ........................ 5-74 UAF41 ........................ 5-82 UAF42 ...................... S5-45 VFC32 ........................ 10-3 VFC42 ...................... 10-12 VFC52 .........:............ 10-12 VFC62 ...................... 10-18 VFC100 .................... 10-26 VFC101N ................. 10-41 VFC110 .................... S10-3 VFC121 .................. S10-11 VFC320 ..........:......... 10-54 XTR100 .................... 3-114 XTR101 .................... 3-126 XTR103 .................... 83-83 XTR104 .................... 83-85 XTR110 .... :............... 3-139 700 .............................4-86 700U ...........................4-86 710 ............................. 4-68 722 ............................. 4-92 724 ............................. 4-96 3507J ........................ 2-213 3506J ........................ 2-215 3550 Series .............. 2-217 3551 Series .............. 2-221 3553 ......................... 2-225 3554 ............ :............ 2-229 3571 ......................... 2-237 3572 ......................... 2-237 3573 ......................... 2-243 3580 ......................... 2-247 3581 ......................... 2-247 3582 ......................... 2-247 3583 ......................... 2-251 3584 ......................... 2-255 3606 ......................... 3-150 3627 ......................... 3-158 3650 .........................4-100 3652 ......................... 4-100 3656 ......................... 4-108 4085 ........................... 5-94 4104 ......................... 5-100 4115 4127 4302 4341 4423 ......................... 5-100 ......................... 5-102 ......................... 5-109 ......................... 5-115 ......................... 5-119 Individual product data sheets for models not listed here are available from your local Burr-Brown salesperson or representative. See the listing on the Inside back cover. How To Use This Book If you know the MODEL NUMBER, Use the Model Index on the INSIDE FRONT COVER. If you know the PRODUCT TYPE, Use the TABBED TABLE OF CONTENTS on page v. Or, use the SELECTION GUIDE TABLES at the front of each tabbed section. If you want NEW MODELS, Use the Model Index on the INSIDE FRONT COVER or the SELEC· TION GUIDE TABLES at the front of each tabbed section. New models contained in this supplement are shown in boldface; for other models see Burr-Brown Integrated Circuits Data Book Volume 33. Contact your local Burr-Brown salesperson or representative for information on new models. If you want a PRICE, If you are in the USA, see the USA PRICE LIST, Section 16. If you are outside the USA, contact your local Burr-Brown salesperson or representative. If you want MILITARY components, Contact your local Burr-Brown salesperson or representative. See INSIDE BACK COVER. If you want DIE, Contact your local Burr-Brown salesperson or representative. See INSIDE BACK COVER. LI-376 ©1990 Burr-Brown Corporation Printed in USA Burr-Brown Corporation International Airport Industrial Park Mailing Address: PO Box 11400 Tucson, AZ 85734 . Tel: (602) 746-1111 FAX: (602) 889-1510 Street Address: 6730 S. Tucson Blvd. Tucson, AZ 85706 • • Twx: 910-952-1111 Cable: BBRCORP • Telex: 066-6491 The infonnation provided herein is believed to be reliable; however, BURRBROWN assumes no responsibiiity for inaccuracies or omissions. BURRBROWN assumes no responsibility for the use of this infonnation, and all use of such infonnation shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits or products described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. Burr-Brown Integrated Circuits Data Book Supplement Volume 33b BURR - BROWN® 11511511 For Immediate Assistance, Contact Your Local Salesperson About Burr-Brown Burr-Brown Corporation is a leading designer and manufacturer of precision microcircuits and microelectronic-based systems for use in data acquisition, signal conditioning, measurement, and control. We make our products for customers who pursue business success in the same way we do - through worldwide competition based on high performance, high quality, and high value. Our customers include OEMs, sophisticated end-users, systems integrators, and VARs who demand an extra measure of performance for their products and operations. COMPANY FACTS iv ~ Founded in 1956. ~ Corporate headquarters: Tucson, Arizona, USA. ~ 1450 employees. ~ Manufacturing and technical facilities: Tucson; Livingston, Scotland; Atsugi, Japan. ~ Sales and distribution subsidiaries in Austria, Belgium, England, France, Germany, Italy, Japan, the Netherlands, Sweden, and Switzerland; 19 international sales representative organizations worldwide. ~ Superior customer service from more than 300 sales and service staff worldwide. ~ 800+ high-performance products. Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) UNDERSTANDING COMPONENT MODEL NUMBERS vii WHERE TO GO FROM HERE: BURR-BROWN SALES & SERVICE ix BURR-BROWN TECHNICAL LITERATURE * * OPERATIONAL AMPLIFIERS INSTRUMENTATION AMPLIFIERS Amplifiers, Transmitters, Receivers ISOLATION PRODUCTS Isolation Amplifiers, Isolation Power Supplies ANALOG CIRCUIT FUNCTIONS Multipliers/Dividers, Log Amps, RMS-to-DC, Multifunction Converters, References DIGITAL-TO-ANALOG CONVERTERS 6.1-lnstrumentation; 6.2-Audio, Communications, DSP ANALOG MULTIPLEXERS * SAMPLE/HOLD AMPLIFIERS * .. - * * ANALOG-TO-DIGITAL CONVERTERS 9.1-lnstrumentation; 9.2-Audio, Communications, DSP VOLTAGE-TO-FREQUENCY CONVERTERS DATA ACQUISITION COMPONENTS * SURFACE MOUNT COMPONENTS * ACCESSORIES * m * * * DSP AND OTHER BURR-BROWN PRODUCTS CROSS-REFERENCE INFORMATION * PRICE LIST (USA ONLY) .. See Burr-Brown Integrated Circuit Data Book Volume 33 * m Or, Call Customer Service at 1-800-548-6132 (USA Only) Understanding Component Model Numbers Most Burr-Brown component products in this book have model numbers in the following form: ADC 80 M A H -12 /QM I Quality Designator (optional) Additional Performance Information (optional) Package Designator Performance Gmdeffemp Range Designator Additional Performance Infornlation (Second Genemtion, Improved Performance, etc.), 1 or 2 Letters (optional) Model Sequence Designator, 2 to 4 digits Product Type Prefix Exceptions: Second-source products are marked as similarly to the original vendor's part number as possible. Some products designed for digital audio and signal processing applications have model numbers as follows: PCM 58 P -J I Performance Gmdeffemp Range Designator I Package Designator Model Sequence Designator, 2 to 4 digits Product Type Prefix Burr-Brown Ie Data Book Supplement, Vol. 33b vii For Immediate Assistance, Contact Your Local Salesperson Product Type Prefixes Product Type Prefix Description Amplifiers OPA INA PGA ISO Operational Amplifier Instrumentation Amplifier Programmable Gain Amplifier Isolation Amplifier Analog Circuit Functions MFC MPY DIV LOG Multifunction Converter Multiplier Divider logarithmic Amplifier Frequency Products VFC UAF Voltage-to-Frequency Converter Universal Active Filter Conversion Products ADC ADS DAC DSP SDM SHC AID Converter AID Converter with SampleJHold DIA Converter Products Tailored Especially for Digital Signal Processing Multiplexer AID and DIA Converters for Audio and Digital Signal Processing System Data Modules SampleJHold PWS PWR REF XTR RCV Power Supply Power Supply Reference Transmitter· Receiver MPC PCM Miscellaneous Performance Gracie and Temperatura Range Deslgnatora o·Cto 7O·C (Commercial) Increasing Parametric Performance Temperatura Range to +8500 'II -o5°C to +125·C (Industrial) (Military) ~5"C H A R J K L(best) B S C (best) T(best) NOTE: (1) For some industrial products this may be -40·C to 8S·C. Package Deslgnatora M P G U N L o H viii Metal (hermetiC) Plastic DIP (nonhermetic) Ceramic (hermetic or nonhermetic) SOIC PLCC Ceramic Leadless Chip Carrier Die Ceramic hermetic Quality Deslgnatora Burr-Brawn's a program a aM or 10M Burr-Brawn's a program with Military Visual Criteria BI or B Bum-In Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) Where To Go From Here: Burr-Brown Sales & Service The Burr-Brown Integrated Circuits Data Book Supplement Vol. 33b contains an extensive variety of new precision microcircuits. These have been introduced since the January 1989 publication of the 13oo-page Burr-Brown Integrated Circuits Data Book Vol. 33. which is available free upon request from your local salesperson or by calling 1-800-548-6132 (USA only). With both books, you will have an up-to-date collection of product data sheets on all commercial Burr-Brown IC parts. ABOUT THIS BOOK All Burr-Brown models are listed in Selection Guide tables at the beginning of each tabbed section. With these tables you can quickly compare specs among different models and choose the best part for your design. Complete product data sheets for items in bold are in this book, starting on the referenced page. Items not in bold are in the larger IC Data Book. Data sheets are arranged alphanumerically, so if you know the name of the part you can find it quickly. Or, use the Model Index on the insidefrontcover. There you'll find models in this book in bold and arranged alphanumerically, along with models indexed from the larger IC Data Book. Throughout this book the prefix'S' designates page numbers for the Data Book Supplement. SUPERIOR CUSTOMER SERVICE Burr-Brown gives you the best customer service in the industry - whether you need additional technical literature. technical assistance from factorytrained applications engineers, to place an order, or to return products. For immediate assistance with any of the following, contact your local BurrBrown salesperson or representative. See the inside back cover. Or, in the USA call our Customer Service Center at 1-800-548-6132. Technical Literature - In addition to individual data sheets, Burr-Brown has an extensive library of other useful publications. A brief summary: IC Data Book. Vol. 33 (1/89); Power Sources Handbook. Vol. 2 (8/90); reliability reports, application notes and handbook, UPDATE. Design Update, our applications engineering newsletter. We also offer a comprehensive product selection guide on a PC diskette. The same information is available via our Electronic Bulletin Board Service (see below). Burr-Brown IC Data Book Supplement. Vol. 33b ix For Immediate Assistance, Contact Your Local Salesperson Other Technical Information -Application engineers are available during working hours to help you with product selection, design advice, troubleshooting, documentation, etc. Call customer service at 1·800·548·6132 (USA only). Electronic Bulletin Board Service - Computer-based information system offers up~to-date product announcements, application notes/suggestions, software/utilities (for example, pSPICE models), tech support message center, and E-mail. Available 24 hours per day at no charge, except for toll call. Use these settings: 300/1200/2400 8-N-l; XMODEM file transfer. BBS number is (602) 741-3978. Placing Orders - You can place orders via telephone, FAX, mail, TWX, or Telex with any authorized Burr-Brown field sales office, sales representative, or our Tucson headquarters. A complete list of sales offices is on the inside back cover of this book. For more information about placing an order, contact your local Burr-Brown salesperson or representative. See the inside back cover. Or, call customer service at 1·800·548·6132 (USA only). If the products you want are readily available off the shelf, you can pay for them with your VISA or MasterCard. For more information, call customer service at 1-800·548·6132. Prices and Quotations - Prices in this book (USA only) are USA OEM prices and are subject to change. Price quotations made by Burr-Brown or its authorized field sales representatives are valid for 30 days. Delivery quotations are subject to reconfirmation at the time of order placement. For more information about pricing, contact your local Burr-Brown salesperson or representative. Or, call customer service at 1·800·548·6132 (USA only). Returns and Warranty Service -When returning products for any reason, contact Burr-Brow~ prior to shipping for authorization and shipping instructions. For complete instructions, contact your local Burr-Brown sales office or representative. In the USA, call our Customer Service Center at 1·800·548·6132. Please ship returned units prepaid and supply the original purchase order number and date, along with an explanation of the malfunction. Upon receipt of the returned unit and your RMA number, Burr-Brown will verify the malfunction and inform you of the warranty status, cost to repair or replace, credits, and status of replacement units where applicable. x Burr-Brown Ie Data Book Supplement. Vol. 33b 2 OPERATIONAL AMPLIFIERS APPLICATION GROUPS Burr-Brown operational amplifiers are listed in eight applications groups described below. This helps you determine and select the best operational amplifier available for a design. Instrumentation amplifiers and isolation amplifiers are described in Sections 3 and 4 respectively. LOW DRIFT Low drift operational amplifiers are best suited for applications where accuracy must be preserved over a substantial temperature range. These amplifiers are optimized to minimize the initial input offset voltage and input offset voltage change with temperature. Input offset drifts from 0.1 ~V to 5~VrC are available within this group. rc LOW BIAS CURRENT Low bias current operational amplifiers consist of FET input designs. This group includes amplifiers with input bias currents from O.OlpA to 5OpA. Applications with large feedback resistances or large source resistances (long time constants, integrators, current sources, etc.) and buffer applications will benefit by the use of low bias current amplifiers. LOW NOISE This group contains low noise bipolar and FET input operational amplifiers. Burr-Brown units offer guaranteed noise spectral density, 100% tested. In applications such as low noise signal conditioning, light measurements, radiation measurements, photodiode circuits or low noise data acquisition, the fully characterized and tested voltage noise performance of these units allows the designer to truly bound noise errors. Burr-Brown Ie Data Book Supplement. Vol. 33b 2-1 For Immediate Assistance, Contact Your Local Salesperson WIDEBAND Wideband operational amplifiers have bandwidths greater than SMHz. This group also contains fast settling and high slew rate amplifiers. These amplifiers reduce phase errors at high frequencies and accurately reproduce complex waveforms. These amplifiers are well suited for pulse, video, fast settling, and multiplexing applications. HIGH VOLTAGE Amplifiers in this group are designed to provide large output voltage swings and to operate on wide ranges of supply voltage. Output voltages from ±10V and ±14SV (up to 290V, single supply) are available in this applications group. These amplifiers provide good frequency response and performance in other parameters. Most models have electrically isolated packages and automatic thermal sensing and shutdown. All units have PET inputs to minimize bias current errors when the amplifier is used with the large resistances usually found with high-voltage amplifiers. HIGH CURRENT These amplifiers provide output currents from ±lA to ±lOA. They are used with small load resistances, coax cable driving, and with power booster applications. Many units have self-contained thermal sensing and shutdown to automatically protect the amplifiers from overheating and damage. All of these units have electrically isolated packages. UNITY-GAIN BUFFER (POWER BOOSTER) Unity-gain buffer amplifiers have a wide variety of applications. They are used to boost the output current capability of another amplifier, buffer an impedance that might load a critical circuit or to be an input impedance converter from an input thai must not be loaded. These amplifiers may also be used inside the feedback loop of another operational amplifier to form a current~boosted composite amplifier. SPECIAL PURPOSE Special purpose op amps provide features or performance that don't fit conventional categories. These include op amps specified for very wide temperature range and devices with sWitchable inputs. OPERATIONAL AMPLIFIERS SELECTION GUIDES The following Selection Guides show parameters for the high grade. Refer to the Product Data Sheet for a full selection of grades. Models shown in boldface are new products introduced since publication of the previous Burr- Brown IC Data Book. 2-2 Burr-Brown IC Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) LOWDRIFf Low offset voltage drift vs temperature performance in both FET and bipolar input types is obtained by our sophisticated drift compensation techniques. First, the drift is measured and then special laser trim techniques are used to minimize the drift and the initial offset voltage at 25°C. Finally, "max drift" performance is retested for conformance with specifications. Boldface =NEW LOW DRIFT OPERATIONAL AMPLIFIERS (SSI1V/oC) Description FET Wideband Dual FET Model Frequency Res~onsa Unity Slew Gain Rate (MHz) (V/J.ls) Rated Qutput, min Temp (±V) (±mA) Rangel' l Pkg Page No. 0.1 0.25 0.1 0.25 0.25 1 2 1 2 1 20 50 20 50 ±D.OOl 110 104 110 104 120 16 16 50 50 2 45 40 100 100 2 11.5 11.5 11.5 11.5 11 30 30 30 30 5 Ind Ind Ind Ind Ind T().99 DIP T()'99 DIP TO-99 52-74 52-74 S2-74 52-74 2-55 OPAl56M 2 OPA356M 2 OPA602M 0.25 OPA602P, U 0.5 OPA606M 0.5 5 5 2 5 5 0.05 0.05 ±.001 ±.002 ±0.01 94 94 100 6 6 6.5 6.5 13 14 14 28 24 35 10 10 10 10 12 5 5 15 15 5 Mil Com Ind Ind Com TO-99 T0-99 TO-99 DIP,SOIC T0-99 2-80 2-80 2-145 2-145 2-158 0.5 0.5 2.8 5 ±D.004 0.006 114 80 2 5 2 15 11 11 5 10 Ind Ind 0.15 2 20 123 0.8 OA 13 5 OPA177Z,P 0_01 OPA177S 0.06 OPA77Z,P 0.025 OPA27J,Z 0.025 0.1 1.2 0.3 0.6 1.5 2.B 2.0 ±40 134 126 134 120 0.6 0.6 0.6 8 0.3 0.3 0.3 1.9131 12 12 12 12 10 10 10 16.6 Ind Ind Ind Mil OPA37J,Z 0.025 0.6 ±40 120 63(21 11.9131 12 16.6 Mil OPA27P, U OPA37P, U 0.100 0.100 1.8 1.8 ±80 ±80 117 117 8 63121 1.9131 11.91'1 12 12 16.6 16.6 Com Com OPA627M OPA627P OPA637M OPA637P OPAlllM OPA2111M OPA2107P Low Power OPA1013 (Dual) Single Supply Operation Bipolar Offset Voltage, Bias Open max Currant Loop At Temp (25°C), Gain, 25°C, Drift, max min (±mV) (±!lVrC) (nA) (dB) 92 88 2-195 T0-99 DIP, SOIC S2-114 Com DIP, T()'99 .S2-104 DIP SOIC DIP T0-99, DIP T0-99, DIP DIP,SOIC DIP,SOIC S2-13 S2-13 S2-13 2-27 2-27 2-27 2-27 2-27 2-27 NOTES: (1) Com = DoC to +70°C, Ind a -25°C to +U5°C, Mil = -55°C to + 125°C. (2) Gain-bandwidth product for OPA37~ . Ay - 5 min. (3) Typical. LOW BIAS CURRENT Our many years of experience in designing, manufacturing and testing FET amplifiers give us unique abilities in providing low and ultra-low bias current op amps. These amplifiers offer bias currents as low as 75fA (75 x to-ISA) and voltage drift as low as IJ,lVrC. With offset voltage laser-trimmed to as low as 250J,lV, the need for expensive trim pot adjustments is eliminated. Burr-Brown Ie Data Book Supplement, Vol. 33b 2-3 12 au .--Do.. I! ...CC II. Z 5 au 0 Do 0 For Immediate Assistance, Contact Your Local Salesperson Boldface = NEW LOW BIAS CURRENT OPERAnONAL AMPLIFIERS (~pA) Description FET Offset Voltage, Bias max Current Temp (25"C), At 25·C, Drift, max (±mV) (±pV"C) (PA) Model Open Frequency Loop Response Gain, 'Unity Slew min Gain Rate (dB) (MHz) (VIps) ,Rated' OU!2Ut,mln (±V) (±mA) Page , Temp Rangel'l Pkg TO·99 TOo99 DIP T0-99 DIP 2·55 S2-74 52-74 52074 52-74 No. 11 12 12 11.5 11.5 ,5 30 30 50 2 45 40 100 100 30 Ind Ind Ind Ind Ind 94 94 10 40 6.5 14 12 12 12 12 Ind Ind T0-99 T0-99 2-43 2-43 110 88 1 0.35 3 1 10 ,10 5 5 Com Com TO-99 TO-99 2·72 2-13 2 2 5 2 2 15 11 11 11 5 5 10 Ind Com Ind 92 88 6.4 6.4 35 35 12 11.5 5 5 Ind DIP Com DIP,SOIC ±5 ±10 1 2 110 106 92 88 2 2 6.5 6.5 2 2 28 24 11 11 10 10 5 5 15 15 2-66 Com T0-99 Com DIP. SOIC 2-66 Ind 2·145 TO·99 Ind DIP. SOIC 2·145 5 ±10 10(21 ±25 100 90 13 12 35 30 12 11 5 5 OPA111M OPA627M OPA627P OPA637M OPA637P 0.25 0.1" 0.25 0.1 0.25 1 1 2 1 2 Low Noise OPA101M OPA102M 0.25 0.25 UllracLow Bias Currenl OPA128M AD515H DuaiFET ±1 20 20 50 120 110 104 110 104 5 5 -10 -10 0.5 1 5 25 ±O.075 0.075 OPA2111M OPA2111P OPA2107P 0.5 2 0.5 2.8 15 5 ±4 ±15 6 114 106 . 80 QuadFET OPA404G OPA404P. U 0.75 2.5 3(21 ' 5(2) ±4 ±12 Low Cost OPA121M OPA121P. U OPA602M OPA602P 2 3 0.25 0.5 10 10 2 5 Wideband OPA606M OPA606P 0.5 3 50 2 16 16 50 30 Com Com 'T0-99 2·195 DIP 2·195 DIP, S2-114 SOIC S2-114 TC>-99 DIP 2·94 2-94 2·158 2·158 NOTES: (1) Com .. O·C 10 +70·C. Ind = -25·C 10 +85·C. Mil ~ -55·C to + 125·C. (2) Typical. LOW NOISE Now both FET and bipolar input op amps are offered with guaranteed low noise specifications. Until now the designer had to rely on "typical" specs for his demanding low noise designs. These fully characterized parts allowa truly complete error budget calculation. Boldface = NEW LOW NOISEOPERAnONAL AMPLIFIERS (Very LoweJ Description Model Bipolar Noise Bias Offset Voltage Current Voltage, max at 10kHz, (25·C), at Temp 25·C max max Drift (nVl~) (PA) (±mV) (±11V,.C) Frequency Open Response Loop Slew Gain, Gain Rate, min BW min (dB) (MHz) (V/1lS) Rated , Ou!eut, min Temp (±V) (±mA) Range''' OPA27J.Z 3.8 ±40nA 0.025 0.6 120 8 1.9121 12 16.6 Mil OPA37J. Z 3.8 ±40nA 0.025 0.6 120 63 11.9121 12 16.6 ' Mil OPAl77Z,P OPAl77S OPA77Z,P 10 10 1.5 2.8 2.0 0.01 0.06 0.025 0.1 1.2 0.3 134 126 134 0.6 0.6 0.6 0.3 0.3 0.3 12 12 12 10 10 ,10 11 Ind Ind Ind Pkg Page No. TO-99. 2·27 DIP TO-99. 2·27 DIP DIP 52-13 SOIC S2-13 DIP 52-13 (Continued on next page) 2-4 Burr-Brown feData Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) Boldface = NEW LOW NOISE OPERAllONAL AMPUFIERS (Very Lowe,.) (Continued) Noise Bias Offset Voltage Current Voltage. max at 10kHz. (25°C). at Temp max max 25°C Drift Description Model (nVNHz) (pA) (±mV) (±JIVlOC) Frequency Open Response Loop Slew Gain. Gain Rate. BW min min (dB) (MHz) (V/Jls) Rated Output. min Temp (±V) (±mA) Range('1 Pkg Page No. 2-43 2-43 Wide Bandwidth OPA101M OPA102M 8 8 -10 -10 0.25 0.25 5 5 94 20 40 5 10 12 12 12 12 Ind Ind T0-99 T0-99 FET OPAlllM OPA602M OPA627M OPA627P OPA637M OPA637P 8 12(21 5.4 6.2 5.4 6.2 ±1 1 20 50 20 50 0.25 0.25 1 0.25 1 0.25 1 2 0.8 2 0.8 2 120 92 110 104 110 104 2 6.5 16 16 50 50 1 28 45 40 100 100 11 10 11.5 11.5 11.5 11.5 5 15 30 30 30 30 Ind Ind Ind Ind Ind Ind T0-99 T0-9 T0-99 DIP T0-99 DIP Low Cost OPA27P.U OPA37P, U 4.5 4.5 ±80nA 0.100 ±80nA 0.100 1.8 1.8 117 117 8 63 1.9121 11.9121 10 10 16.6 16.6 DuaiFET OPA2111M OPA2111P 8 6(21 ±4 ±15 0.5 2 2.8 15 114 106 2 2 11 11 5 5 Ind Com T0-99 2-195 DIP 2-195 Dual Audio OpAmp OPA2604 10 100 2 5 100 10 12 20 Ind DIP. S2-122 SOIC 52-122 94 15 2-55_ 2-145 S2-74 S2-74 S2-74 S2-74 Com DIP, SOIC 2-27 Com DIP, SOIC 2-27 NOTES: (1) Ind = -25°C to +85°C. Mil = -55°C to +125°C. Com = O°C to +70·C. (2) Typical. IIII -- I&. .A.... I! cC ....cC Z -5 0 UNITY·GAIN BUFFER (POWER BOOSTER) These versatile amplifiers boost the ouput current capability of another amplifier; buffer an impedance that might load a critical circuit; and may be used inside the feedback loop of another op amp to fonn a current-boosted. composite amplifier. Currents as high as ±200mA are available with speeds of 2000V/J.lS. Description Model 0 Boldface = NEW UNITY-GAIN BUFFER OPERAllONAL AMPUFIERS Rated Output. min (±V) (±mA) III A. Frequency Responses Input -3dB Full Power Slew Rate Gain Impedance Temp (MHz) (MHz) (VIV) (0) RangeUI (V/J.lS) Pkg Page No. High 3553AM Performance 10 200 300 32 2000 =1 10" Ind T0-3 2-225 Low Cost 11 80 275 65 2500 =1 1.5 xlO" Ind T0-8,DIP 2-176 4 8 700 550 2000 =1 10' Ind DIP.SOIC S2-88 OPA633H, P Transcon- OPA660 ductance Amp and Buffer NOTE: (1) Ind = -25°C to +85°C. Burr-Brown Ie Data Book Supplement, Vol. 33b 2-5 For Immediate Assistance, Contact Your Local Salesperson WIDE BANDWIDTH Design expertise in wideband circuits combines' with our fully developed technology to create cost-effective. wideband op amps. Burr-Brown highspeed amplifiers also offer outstanding DC performance specifications. WIDE BANDWIDTH OPERATIONAL AMPLIFIERS ~MHz) Frequency Response Slew Gain Rate t,. BW min ±O.1% (MHz) (V/J!s) (ns) Comp Description Model FET Dual OPA156M OPA356M OPA602M OPA602P, U OPA2107 Dual Audio OPA2604 OpAmp OPA606M OPA606P OPA627M OPA627P OPA637M OPA637P 3554M 3551 3550 Bipolar 3507 CurrentFeedback OPA603P Rated Output, min (±Y) (±mA) Offset Voltage, max At Temp Drift 25°C (±mY) (±J!vrC) Open Loop Gain, min Temp (dB) RangeC1l Page No. Pkg 6 6 6.5 6.5 5 10 10 28 24 15 1.5118 1.5118 SOO 600 1118 int int int Int Int 10 10 10 10 11 5 5 15 15 10 2 2 0.25 0.5 0.5 5 5 2 5 5 94 94 92 88 82 10 25 2 Int 10 20 1 5typ 82 300 ext 10 30 0.5 5 9S(3) Ind DIP 2-152 1118 1118 400 400 300 300 120 int int Int Int G>5 G>5 ext 12 11 11.5 11.5 11.5 11.5 10 5 5 30 30 30 30 100 0.5 3 0.1 0.25 0.1 0.25 1 5(2) 10(2) 1 2 1 2 15 100 90 110 104 110 104 100 Com Com Ind Ind Ind Ind Ind T0-99 TO-99 T0-99 DIP T0-99 DIP T0-3 2-158 2-158 S2-74 S2-74 S2-74 S2-74 2-229 400 ext 10 10 50(2) 88 Com T0-99 2-221 400 int 10 10 50(2) 88 Com T0-99 2-217 200 ext 10 10 10 30(2) 83 Com TO-99 2-213 50 NA 10 75 5 8typ NA Ind DIP ,S2-30 300(3) 200, A=1000 13 25 12 20 16 45 16 40 50 100 50 100 1700, 1000 A=10oo 50, 250 A=10 20, 100 A=1 OPA605M Boldface = NEW 20, A=10 80 50 1000 (G=1 to 50) Mil T0-99 2-80 2-80 Com T0-99 2-145 Ind T0-99 Ind DIP, SOIC 2-145 Ind,MII DIP, S2-114 T0-99, S2-114 SOIC 82-114 Ind DIP, 82-122 TO-99 S2·122 Transcon- OPA660 ductance Amp and Buffer. 700 2000 25 NA 4.0 20 20 50 NA Ind DIP, SOIC S2-88 QuadFET S.4 S.4 28 24 SOO SOO int int 11.5 11.5 5 5 0.75 2.5 3(2) 5(2) 92 88 Ind DIP Com DIP, SOIC 2-94 2-94 inti» Injl3) 12 12 16.S 16.S 0.025 0.025 O.S O.S 120 120 Mil TO-99. DIP Mil T0-99, DIP 2-27 2-27 OPM04G OPA404P, U Low NOise OPA27 Bipolar OPA37 1.912) 8,A=1 63,A=5 11.9(2) Low Noise OPA101M FEr OPA102M 20, A=100 40, A=100 Fast Settling 5000, A=1000 OPASOOM 5 2.5J!s Int 12 12 0.25 5 94 Ind TO-99 2-43 10 1.5J!s Int 12 12 0.25 5 94 Ind T0-99 2-43 500 80 ext 9 180 4 40 86 Ind DIP 2-137 (Continued on next page) 2-6 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) WIDE BANDWIDTH OPERATIONAL AMPLIFIERS (~5MHz) (Continued) Description Model Frequency Response Slew Gain Rate t,. BW min ±O.l% (MHz) (V/Jls) (ns) Comp Rated Output, min (±V) (±mA) Boldface = NEW Offset Voltage, max At Temp Drift 25°C (±mV) (±JlVlOC) Open Loop Gain, min Temp (dB) Range") Pkg Page No. Com,MII DIP, SOIC Com,MII DIP, SOIC S2-42 S2-42 S2-48 S2-48 Very Fast OPA620 200 175121 10 Int 3 15Q121 0.5 8121 55 Settling Precision OPA621 500, A=10 350121 15 Int 3 15Q121 0.5 12121 55 Very Fast Settling Switched Input OPA675G 3000, A=16 3000, A=16 240 15 ext 2.1 30121 5 65 Com,MII DIP S2-90 240 15 ext 2.1 30121 1 5 65 Com,MII DIP S2-90 8.A-l 63, A=5 1.9(') 11.9(') int Int(3) 12 12 16.6 16.6 0.100 0.100 1.8 1.8 117 117 Low Cost OPA676G OPA27P.U OPA37P. U Com DIP, SOIC 2-27 Com DIP, SOIC 2-27 Description High Power Model OPA501M OPA511M OPA512BM OPA512SM OPA541M OPA541AP 26 22 35 35 35 30 OPA2541M 3573M 35 20 Wideband 3554M 10 100 High Voltage 3584M 3583M 3582 3581 3580 OPA445BM 145 140 145 70 30 35 15 75 15 30 60 15 Buffer 3553M OPA633 10 11 200 80 (Dual) Boldface = NEW Offset Voltage, Bias max Current Rated Output, At Temp (25°C), . 25°C min Drift max (±V) (±mA) (±mV) (±JlV/OC) (PA) Frequency Res~onse Unity Gain (MHz) Slew Rate (V/Jls) 1.35 1 2.5 2.5 lOA SA lOA 15A SA SA 5 10 6 3 1 10 40 65 65 40 30 40 20nA 40 30 20 50 50 1 1 4 4 1.6 1.6 SA 1 10 30 65 50 40nA 1.6 1 15 50 3 3 3 3 10 3 25 25 25 25 30 10 50 15 30()l5) 33'S) 2A(4) Open Loop Gain Temp (dB) Rangel') Pkg Page No. 2-109 2-117 2-122 2-122 S2-22 S2-22 Ind Ind T0-3 T0-3 T0-3 T0-3 T0-3 Power Plastic TO-3 T0-3 100 Ind TO-3 2-229 150 30 20 20 15 10 126 118 118 112 106 100 Com Ind Com Com Com Ind TO-3 TO-3 T0-3 T0-3 T0-3 T0-99 2-255 2-251 2-247 2-247 2-247 2-104 2000 2500 NA NA Ind Ind T0-3 DIP 2-225 2-176 98 91 110 110 90 90 Ind Ind Ind Mil Ind Ind 2.6 90 94 1700c') 1200 20 20 20 20 50 50 20") 5 5 5 5 2 200 35JlA 300 275(5) 6 6 8 2-205 2-243 NOTES: (1) Com - O°C to +70°C, Ind = -25°C to +85°C, Mil = -55°C to + 125°C. (2) Gain-bandwidth product. (3) 2A peak. (4) SA peak. (5) Typical. Burr-Brown Ie Data Book Supplement, Vol. 33b .--a... IE ...CC I I. NOTES: (1) Com _ O°C to +70°C, Ind = -25°C to +85°C, Mil = -55°C to +125°C. (2) Typical. (3) G _ 5 min for OPA37. HIGH VOLTAGE, HIGH CURRENT OPERATIONAL AMPLIFIERS IIII 2-7 Z 0 5 W a. 0 For Immediate Assistance, Contact Your Local Salesperson SPECIAL PURPOSE These op amps offer specialized performance or function, including devices with wide temperature range, low quiescent current, and switched inputs. Bolclface = NEW SPECIAL PURPOSE OPERATIONAL AMPURERS Description Very Fast Settling Model Offset Voltage, Bias Open max Current Loop At Temp (25·C), Gain, 25·C, Drift, max min (±mV) (±!lVrC) (nA) (dB) OPA675G OPA676G 5 5 35"" 35"" 65 65 Frequency Res~nse Unity Slew Gain Rate (MHz) (V/jlS) 1iP 1iP Rated OU!l!!!!J min (±V) (±mA) 350 350 2.1 2.1 30 30 Page Temp Range''' Pkg Com, Mil Com, Mil DIP S2-90 DIP' 92-90 No. NOTES: (1) Com - O·C to +70·C, MiI- -65·C to +125·C. (2) -3dB BW at Gain of +10VN. Models STILL available but not featured In this book Model Description 3329/03 3500 3501 3510 Hybrid Power Booster Low Bias Current Op Amp Low Bias Current Op Amp Low Drift Op Amp Low Drift Op Amp Low Drift Op Amp Low Bias Current OpAmp .Low Drift FET Op Amp Low Bias Current Op Amp FET Input Op Amp Wide Temp Op Amp Low Bias Current Op Amp Low Bias Current Op Amp Demo Kit for IS01 02 Demo Kit for 150106 3521 3522 3523 3527 3528 3542 OPA37HT OPA103 OPA104 DEM102 DEM106 Recommanded Newer Model OPA633 OPA27 OPA111 OPA27 OPA111 OPA111 OPA128 OPA111 OPA128 OPA12112) OPA11HT OPA128 OPA128 Equivalency") FIE FIE PIP FIE PIP PIP PIP PIP PIP PIP PIP PIP PIP NOTES: (1) PIP - Pin for Pin. A true second source. FIE. Funclional Equivalent. Very similar function, very similar performance, but not pin for pin. C/P ;. Closest Part. Similar function, similar performance, but significant differences exist. (2) Supply Range for OPA121 is ±5V to ±18V (instead of ±5V to ±2OV). 2-8 Burr-Brown Ie Data Book Supplement. Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) OPERATIONAL AMPLIFIERS GLOSSARY COMMON·MODE INPUT IMPEDANCE Effective impedance (resistance in parallel with capacitance) between either input of an amplifier and its common, or ground terminal. COMMON-MODE REJECTION (CMR) When both inputs of a differential amplifier experience the same commonmode voltage (CMV), the output should, ideally, be unaffected. CMR is the ratio of the common-mode input voltage change to the differential input voltage (error voltage) which produces the same output change. IIII --.... CMR (in dB) =20 10g)O CMV/Error Voltage Thus a CMR of 80dB means that IV of common-mode voltage will cause an error of 100llV (referred to input). I I. A- S COMMON-MODE VOLTAGE (CMV) That portion of an input signal common to both inputs of a differential amplifier. Mathematically it is defined as the average of the signals at the two inputs: z~ o i III A- o COMMON·MODE VOLTAGE GAIN Ratio of the output signal voltage (ideally zero) to the common-mode input signal voltage. COMMON·MODE VOLTAGE RANGE Range of input voltage for linear, nonsaturated operation. DIFFERENTIAL INPUT IMPEDANCE Apparent impedance, resistance in parallel with capacitance, between the two input terminals. FULL POWER FREQUENCY RESPONSE Maximum frequency at which a device can supply its peak~to-peak rated output voltage and current, without introducing significant distortion. GAIN-BANDWIDTH PRODUCT Product of small signal, open-loop gain and frequency at that gain. Burr-Brown Ie Data Book Supplement. Vol.33b 2-9 For Immediate Assistance, Contact Your Local Salesperson . INPUT BIAS CURRENT DC input current required at each input of an amplifier to provide zero output voltage when the input signal and input offset voltage are zero. The specified maximum is for each input. INPUT BIAS CURRENT vs SUPPLY VOLTAGE Sensitivity of input bias current to power supply voltages. INPUT BIAS CtiRR~NT vs TEMPERATURE Sensitivity of input bias current to temperature. INPUT CURRENT NOISE Input current that would produce, at the output of a noiseless amplifier, the same output as that produced by the inherent noise generated internally in the amplifier when the source resistances are large. INPUT OFFSET CURRENT Difference of the two input bias currents of a differential amplifier. INPUT OFFSET VOLTAGE DC input voltage required to provide zero voltage at the output of an amplifier when the input signal and input bias currents are zero. INPUT OFFSET VOLTAGE vs SUPPLY VOLTAGE (PSR) Sensitivity of input offset voltage to the power supply voltages. Both power supply voltages are changed in the same direction and magnitude over the operating voltage range. INPUT OFFSET VOLTAGE vs TEMPERATURE (DRIFf) Rate of change of input offset voltage with temperature. At Burr.,.Brown, this is the change in input offset voltage from +25°C to the maximum specification temperature, plus the change in input offset voltage from +25°C to the minimum specification temperature, this quantity is divided by the specified temperature range. INPUT OFFSET VOLTAGE vs TIME The sensitivity of input offset voltage to time. 2-10 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) INPUT VOLTAGE NOISE Differential input voltage that would produce, at the output of a noiseless amplifier, the same output as that produced by the inherent noise genemted internally in the amplifier when the source resistances are small. MAXIMUM SAFE INPUT VOLTAGE Maximum voltage that may be applied at, or between, the inputs without damage. OPEN·LOOP GAIN Ratio of the output signal voltage to the differential input signal voltage. - 12 w .--a... I I. OPERATING TEMPERATURE RANGE Temperature range over which the amplifier may be safely operated. ~ OUTPUT RESISTANCE Open-loop output source resistance with respect to ground. o = iw POWER SUPPLY RATED VOLTAGE Normal value of power supply voltage at which the amplifier is designed to operate. a. o POWER SUPPLY VOLTAGE RANGE Range of power supply voltage over which the amplifier may be safely operated. QUIESCENT CURRENT Current required from the power supply to operate the amplifier with no load and with the output at zero volts. RATED OUTPUT Peak output voltage and current that can be continuously, simultaneously supplied. SETTLING TIME Time required, after application of a step input signal, for the output voltage to settle and remain within a specified error band around the final value. Burr-Brown Ie Data Book Supplement, Vol. 33b 2-11 For Immediate Assistance, Contact Your Local Salesperson SLEW RATE Maximum rate of change of the output voltage when supplying rated output current. SPECIFICATION TEMPERATURE RANGE Temperature range over which "versus temperature" specifications are specified. STORAGE TEMPERATURE RANGE Temperature range over which the amplifier may be safely stored, unpowered. UNITY-GAIN FREQUENCY RESPONSE Frequency at which the open-loop gain becomes unity. 2-12 Burr-Brown Ie Data Book Supplement. Vol; 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) OPA177 OPA77 ..... ......... 2 o Precision OPERATIONAL AMPLIFIER FEATURES APPLICATIONS 12 III • • • • • PRECISION INSTRUMENTATION I I. LOW OFFSET VOLTAGE: 10llV max LOW DRIFT: O.1IlV/oC HIGH OPEN·LOOP GAIN: 130dB min LOW QUIESCENT CURRENT: 1.SmA typ --.... • DATA ACQUISITION A. • TEST EQUIPMENT • BRIDGE AMPLIFIER • THERMOCOUPLE AMPLIFIER • REPLACES INDUSTRY·STANDARD OP AMPS: OP·07, op·n, Op·1n, AD707, ETC. S DESCRIPTION The OPA177 and OPA77 precision bipolar op amps feature very low offset voltage and drift. Laser-trimmed offset, drift and input bias current virtually eliminate the need for costly external trimming. Their high performance and low cost make them ideally suited to a wide range of precision instrumentation. The low quiescent current of the OPA 177 and OPA77 dramatically reduce warm-up drift and errors due to thermoelectric effects in input interconnections. They provide an effective alternative to chopper-stabilized amplifiers. The low noise of the OPAI77 and OPA77 maintains accuracy. OPAI77 and OPA77 performance gradeouts are avail; able. Packaging options include 8-pin plastic DIP, 8pin ceramic DIP, and SO-8 surface-mount packages. Vo 6 +In soan 3O-JV\I\,--+-_-'-l 500n ~no-JV\I\'--~~_-_r-_ _ _~ InIemaUonaI AlrpaII hluslrlal Park • Mailing Addr88I: PO Il0l114011 • TUcIan, AZ 85'/34 • S - ~ 6730 S. TUcIan Blvd. • TucIon. AZ 85lII6 Til: (602) 746-1111 • "":9111-952-1111 • CabIl:BBRCORP • TeIII:1I6H481 • FAX:(602)_1510 • InInadIllllPraduclInlO:(aao)54&6132 PDS-l081 Burr-Brown Ie Data Book Supplement, Vol.33b 2-13 o = 5 III A. o For Immediate Assistance, Contact Your Local Salesperson OPA177 SPECIFICATIONS ELECTRICAL AI Va~ ±15V, T._ +25OC unless otherwise noted. OPAI77E PARAMETER OFFSET VOLTAGE Inpul 0IIse1 Voltage Long·Term Inpul OIfse~" Voltage Stability OIfset Adjustment Range Power Supply Rejection Ratio CONOmON Rp= 20kn Va=:I;3V to ±18V IIIN INPUT IMPEDANCE Input Resistance IHz,to 100Hz.' 1Hz to 100Hz Differential ModeP' Common Mode MAX 4 0.2 10 125 I ±1.5 85 150 4.5 26 45 200 Vcu~ ±13V ±13 130 ±14 140 OPEN-LOOP GAIN laJge-Slgnai Voltage Gain f\:< 2kQ Vo='±IO\llSl 5000 12000 RL :< 10kn f\:<2kQ f\:< Ikn ±13.5 ±12.5 ±12 ±14 ±13 ±12.5 60 Open-Loop Output Reslstanos FREQUENCY RESPONSE Slew Rate Closed-Loop Bandwidth POWER SUPPLY Power ConsumptIon Supply Current f\:< 2kQ G=+I lIS 0.3 0.5 INPUT VOLTAGE RANGE Common·Mode Input Rangel" Common-Mods Rejection OUTPUT Oulput Voltage SWing MIN :1;3 120 INPUT BIAS CURRENT Input OIfset Current Input Bias CUrrent NOISE Input Noise Voltage Input Noise Current OPAI77F TYP 0.1 0.4 Va_ ±15V, No Load Va- :l;3V, No Load V. = :t15V, No Load · ·· · ·· · ·· 0.3 0.6 40 3.5 1.3 60 4.5 2 10 0.03 20 0.1 OPAI77G TYP MAX 10 0.3 25 ·· ·· ·· ·· ·· · ·· ·· ·· ·· · MIN 110 1YP MAX UNRS 20 0.4 60 IlV IlViMo · ·· 1.5 ±2 · mV dB 120 2.8 ±2.8 ·· · 18.5 · lIS ·· ·· nA nA nVnns pAnns MO GO V dB VlmV 2000 6000 ··· ·· ·· · ··· · ·· ·· · ··· mW mW mA 40 0.3 20 0.7 100 1.2 IlV IlVI'C V V V 0 Vips MHz ELECTRICAL At Va_ ±15V, -40'C S T. S +85OC, unless otherwise noted OFFSET VOLTAGE Input OIfset Voltage Average Input OIfset Voltage DriftC" Power Supply Rejection Ratio V.-:I;3V to±18V 120 INPUT BIAS CURRENT Input 0Ifset CUrrent Average Input OIfset Current DrifII" Input Bias CUrrent Average Input Bias Current DriftC" INPUT VOLTAGE RANGE Common-Mode Input Range Common·Mode Rejection OPEN-LOOP GAIN laJge-5lgnai Voltage Gain OUTPUT Oulput Voltage Swing POWER SUPPLY Power ConsumptIon Supply Current ±13 Vou. ±13V 125 1.5 25 0.5 8 ±4 25 ±13.5 120 140 2000 6000 RL :<2kQ ±12 ±13 Va_ ±15V, No Load V.- ±15V, No Load 110 0.5 1.5 f\:<2kQ, Vo-±IOV 60 2 IS 0.1 75 2.5 120 ·· ·· · · · ·· · · ·· 106 ·· · 2.2 40 · 40 · ·· lIS IS · 110 · 1000 4000 · · ·· dB 4.5 nA 85 pAJOC ±6 60 pAJOC · nA V dB VImV V ·· mW mA • Same as specIfcatIon for product to lelt. NOTES: (I) Long-Tenn Input OIfseIVoItage StablUty relers to the averaged trend nne of V08 YO time overextendedperiodsaflertheflrst30 deys of operation. excluding the Initial hour of operation, changes In Vos during the first 30 operating deys are typically less than 2)LV. (2) Sample tested. (3) Gueranteed by design. (4) Gueranteed by CMRR test condition. (5) To Insure high open·loopgain throughout the±IOV outputrange, A"", Is tested at-IOV S Vo S OV, OV S Vo S +IOV, and-IOV SVoS +IOV. (6) OPI77EZ and OPI77FZ: TCVosls 100% testad. (7) Gueranteed by end-POint limits. 2-14 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) OPA77 SPECIFICATIONS ELECTRICAL At Vs =:l:t5V. T. =+25'C untess otherwise noted. OFFSET VOLTAGE Input OIIset Voltage Long-Term Input Offset Voltage Stability'" Offset Adjustment Range Power Supply Rejection Ratio CONOmON MIN R"",,=20kn V. = ±3V to :l:18V INPUT BIAS CURRENT Input Offset Current tnput Bias Current NOISE Input Noise Voltage Input Noise Voltage Denslty Input Noise Current Input Noise Current Density O.IHzto 10Hz.' ,= 10Hz·' ,= 100Hz·' ,= 1000Hz"' O.lHz to 10Hz '.10Hz ,= 100Hz ,= 1000Hz INPUT VOLTAGE RANGE Common Mode Input Range Common-Mode R8j.ectlon - :1:13 OUTPUT Output Voltage Swing V... =:l:13V POWER SUPPLY Power Consumption 10 0.3 25 ±3 0.7 3 0.3 1.2 1.5 ±2 0.35 8.5 7.5 7.5 0.6 18 13 11 :1:14 0.1 5000 12000 f\;.I0k0 R,1 . z o .a off Z ~ ..... i--'i-' 0: 0.1 5 saO III Do 0.01 100 10k lk 100 10 lOOk BandWidth (Hz) MAXIMUM OUTPUT SWING VB FREQUENCY 32 ~ \ ~ f iii i 10k POWER CONSUMPTION VB POWER SUPPLY 100 ~=~111 28 .. 24 lk Frequency (Hz) RL =2kn I /' c -a 20 E 16 i /' 10 ,,/ - c 8 12 ...m 84 "'- o , J I r1 lk 10k lOOk 1M Frequency (Hz) Burr-Brown Ie Data Book Supplement, Vol.33b o 10 20 30 40 Total Supply Voltage (V) 2-19 o For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) T. = +25'<:. V. = ±15V unless otherwise noted. MAXIMUM OUTPUT VOLTAGE YS LOAD RESISTANCE 20 IIII Positive Output ~ 15 g - - il E 10 i :::e OUTPUT SHORT-CIRCUIT CURRENT YS TIME ..... Negative 0u1Dut I) t/sc Isc- .1 5 I o 100 15 lk 10k o 2 3 4 Time from Output Being Shorted (min) Load Resistance to Ground (11) APPLICATIONS INFORMATION The OPAI77 is unity-gain stable. making it easy to use and free from osciliations in the widest range of circuitry. Applications with noisy or high impedance power supply lines may require decoupling capacitors close to the device pins. In most cases 0.1 JJ.F ceramic capacitors are adequate. The OPAI77 has very low offset voltage and drift. To achieve highest performance. circuit layout and mechanical conditions must be optimized. Offset voltage and drift can be degraded by small thermoelectric potentials at the op amp inputs. Connections of dissimilar metals will generate thermal potential which can mask the ultimate performance of the OPA 177. These thermal potentials can be made to cancel by assuring that they are equal in both input terminals. I. Keep connections made to the two input terminals close together. 2. Locate heat sources as far as possible from the critical input circuitry. 3. Shield the op amp and input circuitry from air currents such as cooling fans. OFFSET VOLTAGE ADJUSTMENT The OPAl77 and OPA77 have been laser-trimmed for low offset voltage and drift so most circuits will not require extemal adjustment. Figure I shows the optional connection of an external potentiometer to adjust offset voltage. This adjustment should not be used to compensate for offsets created elsewhere in a system since this can introduce excessive temperature drift. 2-20 1 ~ ?-20kO 0-_.....£12 -".8 Y'N VOPA177">---ovOOT 0-_ _--'3'4+ + Trim Range Is approximately ±3.0mV FIGURE 1. Optional Offset Nulling Circuit. INPUT PROTECTION The inputs of the OPAl77 and OPA77 are protected with soon series input resistors and diode clamps as shown in the simplified circuit diagram. The inputs can withstand ±JOV differential inputs without damage. The protection diodes will. of course. conduct current when the uiputs are overdriven. This may disturb the slewing behavior of unity-gain follower applications, but will not damage the op amp. NOISE PERFORMANCE The noise performance of the OPAI77 and OPA77 is optimized for circuit impedances in the range of 2k{l to SOW. Total noise in an application is a combination of the op amp's input voltage noise and input bias current noise reacting with circuit impedances. For applications with higher source impedance. the OPA627 PET-input op amp will generally provide lower noise. For very low impedance applications, the OPA27 will provide lower noise. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) R, " (a) Conventional op amp wilh eXlemal bias currenl cancellation reslslDr. No bias currenl cancellation resislDr needed (b) OPA177wilh no external bias curren! cancellation resiSlDr. 12 III FIGURE 2. Input Bias Current Cancellation. INPUT BIAS CURRENT CANCELLATION The input stage base current of the OPAI77 is internally compensated with an equal and opposite cancellation current. The resulting input bias current is the difference between the input stage base current and the cancellation current. This residual input bias current can be positive or negative. When the bias current is cancelled in this manner, the input bias current and input offset current are approximately the same magnitude. As a result, it is not necessary to balance the DC resistance seen at the two input tenninals (Figure 2). A resistor added to balance the input resistances may actually increase offset and noise. -it I I. :& c o = 5 III A. o Burr-Brown Ie Data Book Supplement, Vol. 33b 2-21 For Immediate Assistance, Contact Your Local Salesperson BURR-BROWN@ OPA541 IE:lE:lI High Power Monolithic OPERATIONAL AMPLIFIER FEATURES APPLICATIONS • POWER SUPPLIES TO ±40V • MOTOR DRIVER .. • SERVO AMPLIFIER • OUTPUT CURRENT TO 10A PEAK • PROGRAMMABLE CURRENT LIMIT • SYNCHRO EXCITATION • INDUSTRY·STANDARD PINOUT • .AUDIO AMPLIFIER • PROGRAMMABLE POWER SUPPLY • FET INPUT • TO·3 AND LOW·COST POWER PLASTIC PACKAGES DESCRIPTION The OPA54I is a power operational amplifier capable of operation from power supplies up to ±40V and continuous output currents up to 5A. Internal current limit circuity can be user-programmed with a single extemal resistor, protecting the amplifier and load from fault conditions. The OPA541 is fabricated using a proprietary bipolar/FET process. Pinout is compatible with popular hybrid power amplifiers such as the OPA511, OPA512 and the 3573. The OPA541 uses a single current-limit resistor to set both the positive and negative current limits. Applications currently using hybrid power amplifiers requiring two current-limit resistors need not be modified. The OPA54I is available in an II-pin power plastic package and an industry-standard 8-pin T0-3 hermetic package. The power plastic package has a copper-lead frame to maximize heat transfer. On the TO3 package, the case is isolated from all circuitry, allowing it to be mounted directly to a heat sink without special insulators. Current Sense Output Output Drlve External -Vo • IlaDIng Addre.: PO Box 11400 • TucIon, AZ 85734 • SIraet Add...., 6730 S. TUctan Blvd. • TUctan, AZ 85708 • 1Wx:91I1-95Z·1111 • ClbIl:B8RCORP • TellX:~ • FAX:(&02)889-1510 • ImmIdIalllProdUCIInlO:(8OO)54H13Z ~lanIIt AllpGrllnduatrlll Park Tel: (&02)74&-1111 PDS·737D 2-22 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service al 1-800-548-6132 (USA Only) SPECIFICATIONS .. ELECTRICAL At Te= +25'C and V.= ±35VDC unless otherwise noted. nDA'" .AU/AD PARAMETER INPUT OFFSET VOLTAGE Vos vs Temperature vs Supply Vollage YS CONDmONS MIN Specified Temperature Range V•• ±10V to ±V.... Power lilt TYP MAX :t2 :t20 :t2.5 :t20 ±10 ±40 ±10 i60 4 50 ±1 :1:30 5 MIN INPUT OFFSET CURRENT les Specified Temperatura Range INPUT CHARACTERISTICS Common·Mode Voltage Range Common-Mode Rejection Input Capacitance Input Impedance, DC GAIN CHARACTERISTICS Open Loop Gain at 10Hz Gain-Bandwidth Product OUTPUT Voltage Swing Specified Temperature Range Vou= (I±V,J- 6V) 90 97 1.6 '0 = 5A, Continuous ±(IV.I- 5.5) ±(IV.I- 4.5) ±(IV.I-4) 9 ±(IV.I- 4.5) ±(JV.I - 3.6) ±(JV.I - 3.2) 10 6 10 55 2 10= 0.5A Current, Peak Phase Margin POWER SUPPLY Power Supply Voltage, ±V. Current, Quiescent THERMAL RESISTANCE OPA541AP: 9., (Juctlon-to-Case) 9., 9... (Junctlon-to-Amblent) OPA541AMlBMiSM: 9., (Junction-to-Case) 9., 9~ (Junction-to-AmbIent) TEMPERATURE RANGE TCASE R, = ell, Vo = 20Vrrns 2V Step Specified Temperature Range, G • 1 Specified Temperature Range, G >10 Specified Temperature Range, f\ = ell 3.3 SpecIfied Temperatura Range ±10 45 ·· ·· ·· 40 AC Output f > 60Hz DC Output No Heat Sink 2.5 3 40 AC Output f > 60Hz DC Output No Heat Sink 1.25 1.4 30 AM,BM,AP SM · SOAI" :1:30 20 -45 :1:35 25 UNITS If) ±C.1 ±15 ±1 :tOO mV IIVI'C IIVN IIV1W 0 · ·· ±(IV.I- 3) 113 5 1 R,=6ll lo::l2A AC PERFORMANCE Slew Rate Power Bandwfdth Settling Time to 0.1% CapacItive Load ±(IV,J-6) 95 MAX ·· ·· · · BIAS CURRENT I. TYP · · ·· · ·· pA nA Tn dB MHz V V V A · · ·· VIi'S kHz i'S nF · · · ±35 pA V dB pF ··· ±40 Degrees V mA 'CIW 'CIW 'CIW ·· ·· 1.5 1.9 +85 · · -55 · +125 'CIW 'CIW 'CIW 'C 'C • Speclficalion same as OPA541AMlAP. NOTE: (1) SOA Is the Safe Operating Araa shown In F1111 III I 90 .s. E i OPEN·LooP GAIN AND PHASE YO FREQUENCY ----- ~ L..-- ~ 0.6 20 30 ~ ...... ....VV --- --- 40 - ;E -- ~ ~+25'C . / I-"" .-" 5 Tc =+125°C 50 60 70 )_ 4 3 I ,.,... ~ ~2 / o 80 (+V.)-Vo 90 +V. + I-V.I (V) Burr-Brown Ie Data Book Supplement, Vol. 33b o ,/' .-" - 2 r- 3 .,;- ~~ ----. 456 lour V .-" V V I-V.I-IVol 7 8 9 10 (A) 2-25 0 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) T. ~ +25"C. v. _±35VDC unless oth8lWlse noled. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 _ _ _ VOLTAGE NOISE DENSITY vs FREQUENCY l k . m a. ._ O.OI~• •~.M. 10 ~~~~~WW~~~~~WL~~~ 1 lk 100 10 10k 0.001 lOOk L-.I...I.~.I.W..~..J..L.l.WII.L......l...u.l.oWII,"-I-..L.J...IJJWI 10 lk Frequency (Hz) 100 Frequency (Hz) 10k lOOk CURRENT LIMIT vs RESISTANCE LIMIT vs TEMPERATURE CURRENT LIMIT vs RESISTANCE LIMIT 10 10 Power Plastic - Power Plastic at-25"C Power Plastic al ..as"C -T0-3 " I':~ - _ NOTE: These are averaged values. -lour Is typically higher. II II +Iilliliiii 0.1 0.01 T0-3 al-25"C ~ Io>lo T().3 at ..as"C ~ ~~ . 10% - NOTE: These are averaged values. - -lour Is typically higher. liiT,'11111 - 0.1 10 RCL 10% +Iittilil~ 1O"iiillll 0.1 0.01 ~l~. f't'l 0.1 10 RCL (n) (n) COMMON-MODE REJECTION vs FREQUENCY DYNAMIC RESPONSE 120 110 11\ 100 Io 80 60 2-26 I I V " 70 50 I " iii' :!!. 90 10 G. 1. c" • 4.711F \ \ \ f'w r- I\. 100 lk 10k Frequency (Hz) lOOk 1M Time (IJ1S1d1v1s1on) Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) INSTALLATION INSTRUCTIONS POWER SUPPLIES The OPAS41 is specified for operation from power supplies up to ±40V. It can also be operated from. unbalanced or single power supplies as long as the total power supply voltage does not exceed SOY. The power supplies should be bypassed with low series impedance capacitors such as ceramic or tantalum. These should be located as near as practical to the amplifier's power supply pins. Good power amplifier circuit layout is, in general, like good high frequency layout. Consider the path of large power supply and output currents. Avoid routing these connections near lowlevel input circuitry to avoid waveform distortion and oscillations. CURRENT LIMIT Internal current limit circuitry is controlled by a single external resistor, RCL' Output load current flows through this external resistor. The current limit is activated when the voltage across this resistor is approximately a base-emitter turn-on voltage. The value of the current limit resistor is approximately: AM,BMSM AP = 0.S09 _ 0.057 R CL I IUMI R = 0.S13 _ 0.02 CL lIuMI Because of the intemal structure of the OPAS41, the actual current limit depends on whether current is positive or negative. The above RcLgives an average value. For a given Rw +Ioor will actually be limited at about 10% below the expected level, while -lOUT will be limited about 10% above the expected level. The current limit value decreases with increasing temperature due to the temperature coefficient of a base-emitter junction voltage. Similarly, the current limit value increases at low temperatures. Current limit versus resistor value and temperature effects are shown in the Typical Performance Curves. Approximate values for RCL at other temperatures may be calculated by adjusting RCL as follows: AR CL = -2mV X (T - 25) IIUM1 The adjustable current limit can be set to provide protection from short cirCuits. The safe short-circuit current depends on power supply voltage. See the discussion on Safe Operating Area to determine the proper current limit value. to SA, but rrns current would be 3.5A, and a current limiting resistor with a lower power rating could be used. Some applications (such as voice amplification) are assured of signals with much lower duty cycles, allowing a current resistor with a low power rating. Wire-wound resistors may be used for ~L Some wire-wound resistors, however, have excessive inductance and may cause loop-stability problerns. Be sure to evaluate circuit performance with resistor type planned for production to assure proper circuit operation. 1ft f. 0- HEAT SINKING Power amplifiers are rated by case temperature, not ambient. . temperature as with signal op amps. The maximum allowable power dissipation is a function of the case temperature as shown on the power derating curve. All points on the power derating slope produce a maximum internal junction temperature of + 150°C. Sufficient heat sinking must be provided to keep the case temperature within safe bounds for the maximum ambient temperature power dissipation. The thermal resistance of the heat sink required may be calculated by: T CASE - T AMBIENT 8 lIS PD (max) = Commercially available heat sinks often specify their thermal resistance. These ratings are often suspect, however, since they depend greatly on the mounting environment and air flow conditions. Actual thermal performance should be verified by measurement of case temperature under the required load and environmental conditions. No insulating hardware is required when using the TO-3 package. Since mica and other similar insulators typically add approximately 0.7°C/W thermal resistance, their elimination significantly improves thermal performance. See BurrBrown Application Note AN-S3 for further details on heat sinking. On the power plastic. package, the metal tab is connected to -Vs' and appropriate actions should be taken when mounting on a heat sink or chassis. SAFE OPERATING AREA The safe operating area (SOA) plot provides comprehensive information on the power handling abilities of the OPA541. It shows the allowable output current as a function of the voltage across the conducting output transistor (see Figure I). This voltage is equal to the power supply voltage minus the output voltage. For example, as the amplifier output swings near the positive power supply voltage, the voltage across the output transistor decreases and the device can safely provide large output currents demanded by the load. Since the full load current flows through RCL' it must be selected for sufficient power dissipation. For a SA current limit on the TO-3 package, the formula yields an ~L of o.lOsn (0.143n on the power plastic package due to different internal resistances). A continuous SA through o.losn would require an RCL that can dissipate 2.62SW. Short circuit protection requires evaluation of SOA. When the amplifier output is shorted to ground, the full power supply voltage is impressed across the conducting output transistor. The current limit must be set to a value which is safe for the power supply voltage used. For instance, with Vs ±3SV, a short to ground would force 35V across the conducting power transistor. A current limit of I.SA would be safe. Sinusoidal outputs create dissipation according to rms load current. For the same RCL' AC peaks would still be limited Reactive, or EMF-generating, loads such as DC motors can present difficult SOA requirements. With a purely reactive Burr-Brown Ie Data Book Supplement, Vol.33b 'Ii"" ~ 2-27 For Immediate Assistance, Contact Your Local Salesperson APPLICATIONS CIRCUITS SAFE OPERATING AREA 10 I To. +25°C To. +85"'C I - - To =+125"0 r-.. '" AP,AM Induc:llve or Bi'~M L Load 0.1 10 EMF-Generadng 100 IVs-Vourl (V) ~O;lpF 10pF 1+ FIGURE 1. Safe Operating Area. load, output voltage and load current are 90° out of phase. Thus, peak output current occurs when the output voltage is zero and the voltage across the conducting transistor is equal to the full power supply voltage. See Burr-Brown Application Note AN-I23 for further infonnation on evaluating SOA. * FIGURE 2. Clamping Output for EMF-Generating Loads. ot35V O.lpF ~ REPLACING HYBRID POWER AMPUFIERS The·OPA541 can be used in applications currently using various hybrid power amplifiers, including the OPA50l, OPASII, OPA512, and 3573. Of course, the application must be evaluated to assure that the output capability and other perfonnance attributes of the OPA541 meet the necessary requirement. These hybrid power amplifiers use two current limit resistors to independently. set the positive and negative current limit value. Since the OPAS41 uses only one current limit resistor to set both the positive and negative current limit, only one resistor (see Figure 4) need be installed. If installed, the resistor connected to pin 2 (1"0-3 package) is superfluous, but it does no hann. Rz 101<0 v.., 0--+-1 R, 2.5I J 10 Jg ~11~~1!!!~~1~1110 ~ 10 100 lk 10k Frequency (Hz) 2-36 ~ ~ J 10 :~'. "~. tr-...ffirnllt. .itmttltlt1ittffI)llFttr,rMm=::J::I:1:I:W!I .. E Jg 8 ~'III"IIII:uln,"~tlllll~ml~II:' j 10 100 lk 10k lOOk Frequency (Hz) Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C unless otherwise noled. LARGE-SIGNAL OUTPUT vs FREQUENCY LARGE-SIGNAL OUTPUT vs FREQUENCY 5 25 I vs =±5V Vs =±15V ~ l>" ~ " 20 '\ 15 1\ R = 1500 10 .. R =750 \ 0 5 o o 100 1k 10k lOOk 1M 10M 100 100M 10k 1k lOOk 1M 10M IIII 100M -.-.. Frequency (Hz) Frequency (Hz) I I. A. OPEN-LOOP TRANSIMPEDANCE vs FREQUENCY 1111 o ~sl_I~15~ Vs =±5V I IIII~ "if V =±15V l!! -45 1111 ri VS =±5V ~ o ~ ~ ill= -90 !!l .c: 102 lk 10k lOOk 1M 10M 100M lG 100 lk 10k Frequency (Hz) . a ~ 80 60 OPEN-LOOP OUTPUT IMPEDANCE 5 C Vs =±15VL 45 N /' - c5 co .3 "8! "- 40 I'\. 20 f'. "co" lOOk 1M 0 -45 V 100M o 1G ~ 0 0 8c- 1. -90 100M Frequency (Hz) Burr-Brown Ie Data Book Supplement, Vol. 33b 60 ~ N c- 10M I ~ -- 40 " c0 .3 . 8- 20 " 1\ Vs -±5V ..8! C 45 .c: "N 0 5 B0 co " ~ C: V t.- -45 100k 1M .3 C: 8-" o 10k 90 111111 ~ S ~ 0 o 10k 10M 80 .c: N 1M OPEN-LOOP OUTPUT IMPEDANCE 90 111111 '\ 100k Frequency (Hz) ~ B- III A. -180 100 -c -2 i ~ "--135 S ~ OPEN-LOOP PHASE vs FREQUENCY 10M -90 100M Frequency (Hz) 2-37 For Immediate Assistance, Contact Your Local Salesperson _I - - -...- - ~ I 0.05% AGain _I I 0.0625· Af) • .....- - - - - - - - - - - - - - 2 0 0 IRE Full S C a l . - - - - - - - - - - - - - -.... M.asured wlih Rohd. & Schwarz Differential Gain/Phase Meter. Rohde & Schwarz SPF2 Video Signal Generator Rohd. & Schwarz PVF Differential GainlPhase Meter FIGURE 1. Video Differential GainJPhase Performance. LARGE·SIGNAL PULSE RESPONSE .- SMALL·SIGNAL FREQUENCY RESPONSE Input +6 100pF ~ ~: . ~ .,.'500 ::;j;: '" .,. Vs - ±15V Output -3 II I I J ~~ SOP. O~F ~ CL ';'20;:11=:: 10RF f- NOTE: Feedback resistor valu. c-- lOOk s,elef'1 i~r;,~uced r~ki~gi , 1M 10M 100M Frequency (Hz) FIGURE 2. Dynamic Response- Inverting Unity-Gain. 2-38 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) LARGE·SIGNAL PULSE RESPONSE SMALL·SIGNAL FREOUENCY RESPONSE Input +26 +23 Oulput +17 1--+++++tI-tF9Fi==\-J-H+II--+--H~+l-H +14 10M 1M lOOk 100M Frequency (Hz) FIGURE 3. Dynamic Response, Gain = +10. APPLICATIONS INFORMATION For most circuit configurations, the OPA603 current-feedback op amp can be treated like a conventional op amp. As with a conventional op amp, the feedback network connected to the invening input controls the closed-loop gain. But with a current-feedback op amp, the impedance of the feedback network also controls the open-loop gain and frequency response. Feedback resistor values can be selected to provide a nearly constant closed-loop bandwidth over a very wide range of gain. This is in contrast to a cdnventional op amp where circuit bandwidth is inversely proponional to the closedloop gain, sharply limiting bandwidth at high gain. Figures 4a and 4b show appropriate feedback resistor values versus closed-loop gain for maximum bandwidth with minimal peaking. The dual venical axes of these curves also show the resulting bandwidth. Note that the bandwidth remains nearly constant as gain is increased. With control of the open-loop characteristics of the op amp, dynamic behavior can be tailored to an application's requirements. Lower feedback resistance gives wider bandwidth, more frequency-response peaking and more pulse response overshoot. The higher open-loop gain resulting from lower feedback network resistors also yields lower distonion. Higher feedback network resistance gives an over-damped response with little or no peaking and overshoot. This may be beneficial when driving capacitive loads. Feedback network impedance can also be varied to optimize dynamic performance. To achieve wider bandwidth, use a feedback resistor value somewhat lower than indicated in Figure 4. EXTENDING BANDWIDTH For gains less than approximately 20, bandwidth can be extended by adding a capacitor, CF, in parallel with a lower value for RF. The optimum gain-setting resistor value in this case is far lower than those shown in Figure 1. For ±ISV operation, select RF with the following equation: Burr-Brown Ie Data Book Supplement, Vol. 33b BANDWIDTH AND FEEDBACK RESISTOR vs INVERTING GAIN 60 ¥ ::Il ~ 52.5 I III ......... ....... 45 _ ! " 37.5 51 is 30 12w - I I. :::i 3k S o 5 'I"RF '~I~I I--..... I ~ 750 G=~ 'I -10 -1 1.5k -I'-- -100 Voltage Gain (VN) (4a) ¥ ::Il ;; 52.5 !:ii III o 37•5 3k 30 P 1 9: li ., .!I ~ ...... G> 2k 1'--.. . lk G=l+~, R, fl o 4k II~ 1 o w ~III 45 ~ z a. BANDWIDTH AND FEEDBACK RESISTOR vs NONINVERTING GAIN 60 a. .I J 225k§: 10 II: i {f 0 100 Voltage Gain (VN) (4b) FIGURE 4. Feedback Resistor Selection Curves. RF (0) =30 • (30 - G) for Vs =±ISV For example, for a gain of 10, use RF = 6000. Optimum values differ slightly for ±SV operation: RF (0) = 30· (23 - G) for Vs = ±SV 2-39 For Immediate Assistance, Contact Your Local Salesperson C F will range from I pF to IOpF depending on the selected gain, load, and circuit layout. Adjust C F to optimize bandwidth and minimize peaking. Figure 5 shows bandwidth which can be acheived using this technique. Typical values for this capacitor range from IpF to IOpF depending on closed-loop gain and load characteristics. Too large a value of C F can cause instability. UNITY·GAIN OPERATION As Figure 4b indicates, the OP~603 can be operated in unity gain. A feedback resistor (approximately 2.8kO) sets the appropriate open-loop characteristics mid resistor ~ is omitted. Just as with gains greater than one, the value of the feedback resistor (and capacitor if used) can be optimized for the desired dynamic response and load characteristics. Care should be exercised not to exceed the maximum differential input voltage rating of ±6V. Large input voltage steps which exceed the device's slew rate of lOOOV/J1s can apply excessive differential input voltage. CIRCUIT LAVOUT With any high-speed, wide-bandwidth circuitry, careful circuit layout will ensure best performance. Make short, direct circuit interconnections and avoid stray wiring capacitance-especially at the inverting input pin. A component-side ground plane will help ensure low ground impedance. Do not place the ground plane under or near the inputs and feedback network. Power supplies should be bypassed with good high-frequency capacitors positioned close to the op amp pins. In most cases, a O.OIIlF ceramic capacitor in parallel with a 2.21lF solid tantalum capacitor at each power supply pin is adequate. The OPA603 can deliver high load current-up to 150mA peak. Applications with low impedance or capacitive loads demand large current transients from the power supplies. It is the .power supply ·bypass capacitors which must supply these current transients. Larger bypass capacitors such asl~F solid tanuilum capacitors may improve performance in these applications. VOLTAGE GAIN VB FREQUENCY 30 G ~ 20, R = 22011, C•• 8pF 20 iii" :Eo c ~., 10 j' 0 ~ -10 40 G.l0.R • 56011. C•• 3pF I I I 111111 111111 I I II I I II G=2.~ .820I1.~ \ -3pF ~=~ - \ - --.. R -1 r- II, G.l+if 1M \ lG 10M 100M Frequency (Hz) FIGURE 5. Bandwidth Results with Added Capacitor c;.. APPLICATIONS CIRCUITS VlNo----I +15V I>-----.---<>Vo ,~~~ -15V FIGURE 6. Offset Voltage Adjustment. V..,o------1 POWER DISSIPATION High output current causes increased internal power dissipation in the OPA603. Copper leadframe construction maximizes heat dissipation compared to conventional plastic packages. To achieve best heat dissipation, solder the device directly to the circuit board and use wide circuit board traces. Solder the unused pins, (l~ 5 and 8) to a top-side ground plane for improved power dissipation. Limit the load and signal conditions depending on maximum ambient temperature to assure operation within the power derating curve. The OPA603 may be operated at reduced power supply voltage to minimize power dissipation. Detailed specifications are provided for both ±15V and ±5V operation. (a) Varying Inverting Input Z changes dynamic response. lIeD G--l0 >-_--oVo V. :ov· Max Ba_ -V· Reduced ~ (b) FIGURE 7. Controlling Dynamic Performance. 2-40 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) C R V,N V,N lIon R lIon C l00pF S CD Vo I 2 -:- 0 2·pole Butterworth LP I->dB = 10MHz I =_1_ ->dB 2lt RC FIGURE 8. Low-Pass Filter - IOMHz. Ga70 r7I\ :eal0M~ 22~ea R 112fe Ie FIGURE 10. Bandpass Filter - 2-12 K RC III 21e .-u::a... S IOMHz. 2-pole Butterworth HP I->dB = 1MHz 1 f-3dB z~ a-;-Rc' FIGURE 9. High-Pass Filter - IMHz. >-+-~-oVo V, R L ;, 150n lor±10V Oul o 5 IU This composite amplifier uses the OPA603 current·leedback op amp to provide extended bandwidth and slew rate al high closed·loop gain. The feedback locp Is closed around the composite amp. preserving Ihe precision Input characteristics 01 the OPA627J637. Use separate power supply bypass capacllOtS lor each op amp• • Minimize capacitance at this node. GAIN (VIY) A, OPAMP 100 1000 OPA627 OPA637 R, II, R, R. -3dB SLEW RATE (n) (kO) (0) (kn) (MHz) (VI",,) SO.5111 4.99 49.9 4.99 20 12 1 1 15 11 700 500 NOTE: (1) Closeslll2% value. FIGURE II. Precision-Input Composite Amplifier. Burr-Brown Ie Data Book Supplement, Vol. 33b 2-41 a. o For Immediate Assistance, Contact Your Local Salesperson BURR-BROWN® OPA620 IE:lE:lI Wideband Precision OPERATIONAL AMPLIFIER FEATURES APPLICATIONS • LOW DISTORTION • FAST SETTLING: 25ns (0.01%) • GAIN-BANDWIDTH: 200MHz • HIGH-SPEED SIGNAL PROCESSING • ADC/DAC BUFFER • ULTRASOUND • PULSE/RF AMPLIFIERS • HIGH-RESOLUTION VIDEO • UNITY-GAIN STABLE • LOW OFFSET VOLTAGE: ±100flV • SLEW RATE: 250V/flS • LOW DIFFERENTIAL GAIN/PHASE ERROR • ACTIVE FILTERS • a-PIN DIP AND SOIC PACKAGES AND DIE DESCRIPTION The OPA620 is a precision wide band monolithic operational amplifier featuring very fast settling time, low differential gain and phase error, and high output current drive capability. The OPA620 is internally compensated for unity-gain stability. This amplifier has a very low offset, fully symmetrical differential input due to its "classical" operational amplifier circuit architecture. Unlike "current-feedback" amplifier designs, the OPA620 may be Non-Inverting Input 3 Inverting 2 used in all op amp applications requiring high speed and precision. Low noise and distortion, wide bandwidth, and high linearity make this amplifier suitable for RF and video applications. Short-circuit protection is provided by an internal current-limiting circuit. The OPA620 is available in plastic, ceramic, sOle packages, and die form. Two temperature ranges are offered: ooe to +70oe and -55°C to +125°e. Output Stage 6 Output Input 4 -Vee International Alrportlndustrlal Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (602)746·1111 • Twx: 910·952·1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (602) 889-1510 PDs·snc 2-42 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) SPECIFICATIONS ELECTRICAL At V co = ±SVDC, R, = 1000, and T. = +25'C unless othelWise noted. ,,0, PARAMETER CONDITIONS INPUT NOISE Voltage:lo = 100Hz 10= 1kHz fo= 10kHz 10= 100kHz 10 = 1MHz to 100MHz I. = 100Hz to 10MHz Current: 10= 10kHz to 100MHz MIN vc• = OVDC T" = TMIN to TMAX ±V" = 4.5V to 5.5V MAX ±200 50 60 15 30 V c• = OVDC 0.2 2 Open-Loop 15111 1111 V'N = ±2.5VDC, Vo= OVDC OPEN-LOOP GAIN, DC Open-Loop Voltage Gain ~,= 1000 =500 FREQUENCY RESPONSE Closed-Loop Bandwidth (...,'JdB) Gain-Bandwidth DiNerential Gain DiNerential Phase Harmonic Dlstortion(2) Full Power Response(2) Slew Aate Overshoot Settling Time: 0.1 % 0.01% Phase Margin Rise Time (2 ) Gain = +1VN Gain = +2VN Gain = +5VN Gain = +10VN Gain = +10VN 3.58MHz, G = +1VN 3.58MHz, G = +1VN G = +2VN, I = 10MHz, Vo= 2Vp-p Second Harmonic Third Harmonic Vo = 5Vp-p, Gain = +1VN Vo = 2Vp-p, Gain = +IVN 2V Step, Gain = -IVN 2V Step, Gain = -IVN 2V Step, Gain = -IVN RATED OUTPUT Voltage Output Output Resistance Load Capacitance Stability Short Circuit Current POWER SUPPLY Rated Voltage Derated Performance Current, Quiescent TEMPERATURE RANGE Specification: KP, KU, KG, LG SG Operating: KG, LG, SG KP,KU ±3.0 65 ±a.5 75 50 48 60 58 11 27 175 Gain = +1VN Gain = +1VN. 10% to 90% V0 = 100mVp-p; Small Signal -Vo = 6Vp-p; Large Signal R, = 1000 R, = 500 1MHz, Gain = +1VN Gain = +1VN Continuous ±Vcc ±Vcc 10 ·· ·· ·· ·· · -60 -55 · 2 22 ±2.8 ±2.5 ·· 5 21 a · ·· · ·· ·· ··· ±3.0 ±a.o 0.Q15 20 ±150 4.0 = OmADC Ambient Temperature · 300 100 40 20 200 0.05 0.05 -61 -65 16 40 250 10 13 25 60 6.0 23 · · · +70 -65 -65 Ambient Temperature --25 MIN 55 V c• = OVDC 0 OPA620LG MAX · ±lmV ±8 OFFSET CURRENT Input Offset Current INPUT VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection TYP ·· ·· ·· BIAS CURRENT Input Bias Current INPUT IMPEDANCE Differential Common-Mode MIN 10 5.5 3.3 2.5 2.3 8.0 2.3 R,=OO OFFSET VOLTAGE'" Input Offset Voltage Average Drift Supply Rejection TYP TYP ··· ·· ·· ·· MAX nVlfHZ nVlfHZ nVlfHZ nVlfHZ nVI{Hz !'V, rms pAlfHZ ±tOO ±SOO !'V !,VI"C dB · 25 JlA · ·· · ·· · ·· JlA kO II pF MOllpF 70 V dB 55 53 dB dB ·· ·· · ·· ·· ·· · MHz MHz MHz MHz MHz % Degrees ·· % ns ns Degrees · ns ns ·· ··· ·· · · · · · · · · -65 +125 +85 dBc<" dBc MHz MHz VII'S ·· ·· +125 +125 UNITS V V 0 pF rnA VDC VDC mA 'C '0 '0 '0 8JA KG, LG,SG KP KU 125 90 100 125 'CIW 'CIW 'CIW • Same specifications as for KP/KU, Burr-Brown Ie Data Book Supplement, Vol. 33b 2-43 "2 CD 0 IIII ......-:IE ...CC A. Z -5 0 III A. 0 For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS (cont) ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS) At Vee =±5VDC, RL = loon, and T. =T"~ to T... unless otherwise noted. OPA620KPIKU PARAMETER TEMPERATURE RANGE Specification: KP, KU, KG, LG SG CONDmONS MIN Ambient Temperature 0 TYP OPA620KGISG MAX +70 TYP · TA=TMlNtoTMo\IC ±Vee = 4.5V to S.SV 45 Ve• = OVDC is 40 OFFSET CURRENT Input Offset Current Ve• = OVDC 0.2 S ±2.S 60 ±3.0 75 OPEN LOOP GAIN, DC Open-Loop Voltage Gain RL = lOOn RL = 50n 46 44 60 58 RATED OUTPUT Voltage OUlput RL = loon RL = 50n ±2.6 ±2.5 ±3.0 ±3.0 POWER SUPPLY Current, Quiescent .. 21 10= OmADC · ·· ·· 25 MIN TYP · ·· ·· ·· · MAX · '\'125 · ·· ±B 60 BIAS CURRENT Input Bias Current V" = ±2.SVDC, Vo = OVDC OPA620LG MAX · -5S OFFSET VOLTAGE'" Average Drift Supply Rejection INPUT VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection MIN 50 ·· 'C 'C p.Vf'C dB · · · · · ·· ·· ·· · · · · · UNITS 3S p.A p.A 65 V dB 52 50 dB dB V V rnA • Same specifications as for KPIKU. NOTES: (1) Offset Voltage specifications are also guaranteed with units fully warmed up. (2) Parameter Is sample tested. (3) dBc = dB refered to carrier-Input signal. ABSOLUTE MAXIMUM RATiNGS ORDERING INFORMATION Basic Model Number _ _ _ _ _ _ _ _ ~....J Performance Grade Code K, L = O'C to +70'C S = -55'C to +125'C J Lel - P~eCode--------------------__------~ G = a·pln Ceramic DIP P = 8-pln Plastic DIP U = a·pin Plastic SOIC Supply ..............................................................................................±7VDC Internal Power DissipatiOn'" ....................... See Applications Information Differential Input Vollage ............................................................. Total Vco Input Voltage Range ................................... See Applications Information Storage Temperature Range: KG, LG, SG ................... -65OC to +150'C KP.KU ........................... -4000 to +125'C Lead Temperature (solderfng, lOs) .............................................. +3000c (soldering. SOIC 3s) ...................................................................... +2600c Oulput Short Clrcutt to Ground (+25'C) ............... Continuous to Ground Junction Temperature (TJ ) ............................................................ +17500 NOTE: (4) Packages must be derated based on specilied 9 JA' Maximum TJ must be observed. PIN CONFIGURATION (S·PIN DIP) Top View No Internal Connection 8 Inverting Input Non-Inverting Input Negative Supply (-Vee) 2-44 No Internal Connection Positive Supply (+Vccl Output 4 5 No Internal Connection Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) MECHANICAL G Package - 8-Pln Ceramic r::-: A :-::1 OJ DIM A B C D F G H J K L M N R '-Pin 1 Seating Plane INCHES MIN MAX .405 .375 .245 .251 .140 .170 .015 .021 .045 .060 .100 BASIC .098 .008 .012 .150 .290 .320 15' 0' .009 .060 .125 .175 - - MILUMETERS MIN MAX 9.53 10.28 622 6.38 3.56 4.32 0.38 0.53 1.14 1.52 2.54 BASIC 2.49 0.20 0.30 3.80 7.37 8.13 15' 0' 0.23 1.52 3.18 4.45 NOTE: Leads In true poslUon wl1hln 0.01(0.25mm) Rat MMC at seating plane. o &'f CD 2 o - - 12 III 0 nO~ll 1 P - ~ DIM A A. B B. C E, J Pin 1 -.a.-... I I. P Package - a-Pin Plasllc DtP 0111 E E. ••eA L INCHES MIN MAX .155 .200 .050 .020 .014 .020 .045 .065 .008 .012 .370 .400 .300 .325 .240 .260 .100 BASIC .300 BASIC .125 .150 MIWMETERS MIN MAX 3.94 5.08 0.51 1.27 0.51 0.36 1.14 1.65 0.20 0.30 9.40 10.16 7.62 8.26 6.10 6.60 2.54 BASIC 7.62 BASIC 3.18 3.81 DIM l2'" IX P Q. S11) INCHES MIN MAX 0 .030 IS' 0' .015 .050 .040 .075 .015 .050 MILUMETERS MIN MAX 0.00 0.76 IS' 0' 0.38 1.270 t.91 1.02 0.38 1.27 (1) Not JEOEC Std. (2) e, and e. applies In zone L" when unit installed. NOTE: Leads In true position wi1hin 0.01- (0.25mm) R at MMC at seating plane. 2 ....C C Z 0 i III a. 0 U Package - 8-Pln SOIC ~:.~ DIM A A. B B. C D 11 J1 Pin 1 Identifier l(~n1UJLH ~ ~j' crt G 0-1 lelA I\bJ G H J L M N INCHES MIN MAX .201 .185 .178 .201 .146 •162 .130 .149 .054 .145 .015 .019 .050 BASIC .018 .026 .008 .012 .220 .252 10' 0" .000 .012 MILUMETERS MIN MAX 4.70 5.11 4.52 5.11 3.71 . 4.11 3.30 3.78 1.37 3.69 0.38 0.48 1.27 BASIC 0.46 0.66 0.20 0.30 5.59 6.40 10' 0' 0.00 0.30 NOTE: Leads In true position within 0.01" (O.25mm) R at MMC at seating plane. f'I-- L---I-' Burr-Brown Ie Data Book Supplement, Vol. 33b 2-45 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES At V" = ±5VDC, R, = 10011, and T, = +25'C unless otherwise noted. c ~ Ul Av= +1VN CLOSED-LOOP SMALL-SIGNAL BANDWIDTH .81 OPEN·lOOP FREQUENCY RESPONSE +4 III .c "- iil BO :Eo 0 t"-.. c ~ 60 :::: 1l. ~ 40 g c. .§ ,~ase Gain 20 ! Phase Margin =60' 0 -20 lk 10k lOOk 1M 10M 1'\ +2 -45 0 -90 iii :Eo -2 c -135 -4 -180 -6 III III 10M 1M c ill \ -45 ~\ :--;, +2 o 1M 10M -90 -135 '\ ti i'I~' -2 -180 100M -ifI' \ U v 1111 ~\ iil :Eo +18 ~ +16 open-Lorf mi e IpU~\m. +14 -45 1\\ -90 .......... \ 10M 1M 100M Frequency (Hz) Av= +1VN CLOSED-LOOP BANDWIDTH vs OUTPUT VOLTAGE SWING Av= +2VN CLOSED-LOOP BANDWIDTH vs OUTPUT VOLTAGE SWING 8 !\ ~ N , 10k lOOk 1M Frequency (Hz) 10M -180 lG r"I \ I -135 R~ =IJJ! r'\ 2-46 " 1111: +12 lG R~~~l lk -180 lG Frequency (Hz) 8 -135 ' 100M \ 1111 +20 n-Loop PhaSj -90 " ~\ A v,,+10VNCLOSED-LOOP SMALL-SIGNAL BANDWIDTH +24 +22 r- 6O i\ Frequency (Hz) Ace IJ,41 -. mn lG Av = +2VN CLOSED·LooP SMALL-SIGNAL BANDWIDTH +B ~ Open-Loop Phase Frequency (Hz) +10 ~ -9 100M Ao.. '; -rfli OJ C:I \ 100M 'I'-- o lG lk 10k lOOk 1M 10M 100M lG Frequency (Hz) Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES (CO NT) At Vee =±5VDC, R, = lOOn, and T,'= +25'C unless otherwise noted, TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY vs SOURCE RESISTANCE Av= +10VN CLOSED-LOOP BANDWIDTH vs OUTPUT VOLTAGE SWING 100 R~! ~oJ ~:> ... \ z & ~ 1\ ~~ lk 10k lOOk 1M 10 .s .~ ~ o l- 10M t::::: 100M Rs ~~ =lkn Rs = 500nl As = loon Rs'lon' 1 III I I 0.1 lG 100 lk 10k lOOk 10M 1M 100M Frequency (Hz) Frequency (Hz) IIII --.... a. I I. VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs TEMPERATURE INPUT CURRENT NOISE SPECTRAL DENSITY 3.1 100 2.9 I fo = 100kHz l¥;;: 10 .s :> .s 5l z .~ 2.5 ~ " i z ~ () 0.1 100 lk 10k lOOk 1M 10M 2.2 1.7 -50 -25 0 +25 +50 +75 +100 Frequency (Hz) Ambient Temperature ('C) INPUT OFFSET VOLTAGE WARM-UP DRIFT INPUT OFFSET VOLTAGE CHANGE DUE TO THERMAL SHOCK +125 +1000 +100 -=" o = - Voltage Noise 1.9 -75 100M :;; -=. +50 § +500 C> iii .<: .<: () () N'" 0 " 1;; .l!! -50 1;; .l!! 0 f ~ -500 (5 (5 -100 -1000 0 2 3 4 5 6 Time from Power Tum-on (min) Burr-Brown Ie Data Book Supplement, Vol_ 33b S ~tNoise .. '0 :;; I " "~ I'j::::~ @2.8 -1 0 +1 +2 +3 +4 +5 Time from Thermal Shock (min) 2-47 ia. III o For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) AI v'" = ±5VDC. f\ = loon. and T. = +25°C unless otherwise noted. YS BIAS AND OFFSET CURRENT INPUT COMMON·MODE VOLTAGE 25 « a 0.8 20 c :: 15 " 0 j,. ~ ,...- J~ ID -- - ~ Bias purrent Q) 10 0.6 V ~ ~ « a « a ;g c " ;g 0 c 0.4 0 ~ 0.2 BIAS AND OFFSET CURRENT vs TEMPERATURE 21 ~ " ~ 0.8 18 , 15 ~~rrent ""- 12 "'-0;;;:: -2 -t 0 +1 +3 +2 ~ 20 ~ 0 -g -50 -25 0 +25 o ~O +75 -+100 +125 COMMON·MODE REJECTION vs FREQUENCY POWER SUPPLY REJECTION vs FREQUENCY m 80 :s r" 6 60 Vo=OVDC 40 -75 Ambient Temperature (OC) 60 l 9 -+4 m 80 I Offset Current ~ ~ Common-Mode Voltage (V) :s \i r" I' "S a: 40 icil '" ~ I ·20 10k lOOk 1M 10M 100M ~ i"" 1~ 0 lG V- PS ~ 20 r-- 1 ·20 lk 5i l5 /: 0 -'l - ~ 0.41o 0.2 'jtCrm -4 0.6 tk 10k lOOk Frequency (Hz) 1M 10M 100M lG Frequency (Hz) COMMON·MODE REJECTION vs INPUT COMMON·MODE VOLTAGE SUPPLY CURRENT vs TEMPERATURE 80 25 « Va 23 .§. C = OVDC ;g " 21 (9 t In 60 19 V r- V t7 ~ -4 -'l -2 ~ 0 ~ ~ Common·Mode Voltage (V) 2-48 V ........ l-- +3 -+4 ~ -75 ~O -25 0 +25 ~O +75 +100 +125 Ambient Temperature (OC) Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES (CONT) At Vee = ±5VDC, R, = 1000, and T. = +25'C .unless otherwise noted. o LARGE-SIGNAL TRANSIENT RESPONSE SMALL-SIGNAL TRANSIENT RESPONSE ~ CD 2 +50 o ~ f" i o 0 -50 o 25 o 50 100 200 12 w Time (ns) Time (ns) -a. IL ..l I :[ ~" .~ ~ a.l1% 60 40 UJ 20. ;' V ~ >~ ./ ./ ./' ,,/ G=-WN 120 V ;' :[ 100 "E i= i -,l! -,'3 -4 I, -6 --- 60 20 -7 -6 -9 -10 a 2.0 "CLR 0 ci II:, PSR....~ 60 ~KAoL UJ J 50 'K~l --::-- 1.5 - 1.0 8 6 0.5 - .-.:: --- ::::::: -7 -- Gain-Bandwidth K :- Slej Rate 40 -75 -50 -25 0 +25 +50 +75 +100 +125 Temperature ('C) Burr-Brown Ie Data Book Supplement. Vol.33b -75 -50 -25 0 +25 +50 o = 5 a. w 0.1% 4 FREQUENCY CHARACTERISTICS vs TEMPERATURE A oL , PSR, AND CMR vs TEMPERATURE 80 CD 70 ~ Output Voltage Change (V) Closed-Loop Gain (VN) :ElI: ::;; ,../ .......... ~ 0.01% 40 Of -5 ./ 80 o -1 S 140 ./ ,,/ ---- ---- ---- 160 V Vo =2VStep 80 . .I SETTLING TIME vs OUTPUT VOLTAGE CHANGE SETTLING TIME vs CLOSED-LOOP GAIN 100 +75 +100 +125 Temperature ('C) 2-49 o For .Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) At Vee = ±5VDC. R, = lOOn. and T, = +25'C unless otherwise noted. NTSC DIFFERENTIAL GAIN vs CLOSED-LOOP GAIN 0.5 I Il I ~~~8M~ l II I e. :>--,/ - " Vo =OVtol.4V"" / 0.2 ~. J1! i5 Lo=Oltoo.~ 0.1 k: I 2 3 4 5 .......- 6 ~ ...- ........-- gj .r: "- ~ 8 ~ 0.2 c 9 2 10 V. 21 ~ ........ f- - ~ f- - k' - t" -50 is() -60 J: -70 I '31 r 1M I 21 .>--r-- ...... 1---:- 5 -60 ~ .g 0 E Vo =Lo2!1V= ~ " I i!! I I . 0.3 Cl !! 1=3.58MHz RL = 7sn(Two Back-Terminated Outputs) 0.4 .~ NTSC DIFFER.ENTIAL PHASE vs CLOSED-LOOP GAIN 1.0 2Vp-p ~ "..<" T .......-::;:::J.-"21c>--- '31 .......- O.l25Vp-p O.25Vp-p 0.5Vp-p I 1Vp-p 2Vp-p +5 +10 -90 +5 +10 +lS -20 -15 -10 -5 o +15 Power Output (dBm) Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) APPLICATIONS INFORMATION DISCUSSION OF PERFORMANCE The OPA620 provides a level of speed and precision not previously attainable in monolithic form. Unlike current feedback amplifiers, the OPA620's design uses a "Classical" operational amplifier architecture and can therefore be used in all traditional operational amplifier applications. While it is true that current feedback amplifiers can provide wider bandwidth at higher gains, they offer many disadvantages. The asymmetrical input characteristics of current feedback amplifiers (i.e. one input is a low impedance) prevents them from being used in a variety of applications. In addition, unbalanced inputs make input bias current errors difficult to correct. Bias current cancellation through matching of inverting and non-inverting input resistors is impossible because the input bias currents are uncorrelated. Current noise is also asymmetrical and is usually significantly higher on the inverting input. Perhaps most important, settling time to 0.01 % is often extremely poor due to intemal design tradeoffs. Many current feedback designs exhibit settling times to 0.01% in excess of 10 microseconds even though 0.1 % settling times are reasonable. Such amplifiers are completely inadequate for fast settling 12-bit applications. The OPA620's "Classical" operational amplifier architecture employs true differential and fully symmetrical inputs to eliminate these troublesome problems. All traditional circuit configurations and op amp theory apply to the OPA620. The use of low-drift thin-film resistors allows intemal operating currents to be laser-trimmed at waferlevel to optimize AC performance such as bandwidth and settling time. as well as DC parameters such as input offset voltage and drift. The result is a wide band, high-frequency monolithic operational amplifier with a gain-bandwitdth product of 200MHz, a 0.0 I % settling time of 25ns, and an input offset voltage of 10011V. WIRING PRECAUTIONS Maximizing the OPA620's capability requires some wiring precautions and high-frequency layout techniques. Oscillation, ringing. poor bandwidth and settling, gain peaking, and instability are typical problems plaguing all high-speed amplifiers when they are improperly used. In general, all printed circuit board conductors should be wide to provide low resistance, low impedance signal paths. They should also be as short as possible. The entire physical circuit should be as small as practical. Stray capacitances should be minimized, especially at high impedance nodes, such as the amplifier's input terminals. Stray signal coupling from the output or power supplies to the inputs should be minimized. All circuit element leads should be no longer than 1/4 inch (6mm) to minimize lead inductance, and low values of resistance should be used. This will minimize time constants formed with the circuit capacitances and will eliminate stray, parasitic circuits. Tcnon~ Grounding is the most important application consideration for the OPA620, as it is with all high-frequency circuits. Oscillations at frequencies of 200MHz and above can easily occur if good grounding techniques are not used. A heavy ground plane (20z copper recommended) should connect all unused areas on the component side. Good ground planes can reduce stray signal pickup, provide a low resistance, low inductance common return path for signal and power, and can conduct heat from active circuit package pins into ambient air by convection. CD 2 o Supply bypassing is extremely critical and must always be used, especially when driving high current loads. BOth . . power supply leads should be bypassed to ground as close as possible to the amplifier pins. Tantalum capacitors (lJlF to 10JlF) with very short leads are recommended. Although not required, a parallel O.01JlF ceramic may be added if desired. Surface mount bypass capacitors will produce excellent results due to their low lead inductance. Additionally, suppression filters can be used to isolate noisy supply lines. PropIII erly bypassed and modulation-free power supply lines allow I I. full amplifier output and optimum settling time performance. I! Points to Remember I) Don't use point-to-point wiring as the increase in wiring inductance will be detrimental to AC performance. However, if it must be used, very short, direct signal paths are required. The input signal ground return, the load ground return, and the power supply common should all be connected to the same physical point to eliminate ground loops, which can cause unwanted feedback. 2) Good component selection is essential. Capacitors used in critical locations should be a low inductance type with a high quality dielectric material. Likewise, diodes used in critical locations should be Schottky barrier types, such as HP50822835 for fast recovery and minimum charge storage. Ordinary diodes will not be suitable in RF circuits. 3) Whenever possible, solder the OPA620 directly into the PC board without using a socket. Sockets add parasitic capacitance and inductance, which can seriously degrade AC performance or produce oscillations. If sockets must be used, consider using zero-profile solderless sockets such as Augat part number 8134-HC-5P2. Alternately, Teflon standoffs located close to the amplifier's pins can be used to mount feedback components. 4) Resistors used in feedback networks should have values of a few hundred ohms for best performance. Shunt capacitance problems limit the acceptable resistance range to about I ill on the high end and to a value that is within the amplifier's output drive limits on the low end. Metal film and carbon resistors will be satisfactory, but wirewound resistors (even "non-inductive" types) are absolutely unacceptable in high-frequency circuits. 5) Surface mount components (chip resistors, capacitors, etc) have low lead inductance and are therefore strongly recommended. Circuits using all surface mount components E. t. Du POOl de Nemours & Co. Burr-Brown Ie Data Book Supplement, Vol. 33b o w 2-51 .--a... S o = 5 III a. o For Immediate Assistance, Contact Your Local Salesperson with the OPA620KU (SOIC package) will offer the best AC performance. The parasitic package inductance and capacitance for the SOIC is lower than the both the Cerdip and 8lead Plastic DIP. 6) Avoid overloading the output. Remember that output current must be provided by the amplifier to drive its own feedback network as well as to drive its load. Lowest distortion is achieved with high impedance loads. INPUT PROTECTION Static damage has been well recognized for MOSFET devices, but any semiconductor device deserves protection from this .potentially damaging source. The OPA620 incorporates on-chip ESD protection diodes as shown in Figure 2. This eliminates the. need for the user to add external protection diodes, which. can add capacitance and degrade AC performance. 7) Don't forget that these amplifiers use ±5V supplies. Although they will operate perfectly well with +SV and-S.2V, use of ±lSV supplies will destroy the part. 8) Standard commercial test equipment has not been designed to test devices in the OPA620's speed range. Benchtop op amp testers and ATE systems will require a special test head to successfully test these amplifiers. 9) Terminate transmission line loads. Unterminated lines, such as coaxial cable, can appear to the amplifier to be a capacitive or inductive load. By terminating a transmission line with its characteristic impedance, the amplifier's load then appears purely resistive. 10) Plug-in prototype boards and wire-wrap boards will not be satisfactory. A clean layout using RF techniques is essential; there are no shortcuts. OFFSET VOLTAGE ADJUSTMENT The OPA620's input offset voltage is laser-trimmed and will require no further adjustment for most applications. However, if additional adjustment is needed, the circuit in Figure I can be used without degrading offset drift with temperature. Avoid external adjustment whenever possible since extraneous noise, such as power supply noise, can be inadvertently coupled into the amplifier's inverting input terminal. Remember that additional offset errors can be created by the amplifier's input bias currents. Whenever possible. match the impedance seen by both inputs as is shown with R3. This will reduce input bias current errors to the amplifier's offset current, which is typically only 0.2J,1A. >-.Jw'--.....- j OL ~~ I"-"hase r-. Phase ~ Margin -50' -20 10k lOOk --45 +8 -90 :!!. +4 c 1M 10M 100M 'iii Cl -135 +2 -180 0 ~ ~ 1-3dB - 500MHz "- -...! __ Ope~-LoOP Phase \ -90 10M 100M I--t-++-I+-II,:;I'-3dTI'l-B_=,;.10r°:;:.M,:..:H:,:-Z+-PI*l--'rt-t-++++HI --45 ~~Open-LoO Phase \ ' +10 1--t--t='M"Htt-l--f-+++~±\-'l--t-++++HI-90 \~ 1--t-+t+HtI-I--t-+-H-~+t--\lirl"'tt++HI -135 ~ iiimi +6 '--....L..-'-.L..l-U-L.I.I.-....L..-'-.L..L.u.J.J..LL......J..lLL...L..J...I.J>I..U -lS0 1M 10M lG 100M +24 il 1111 +22 rfri +20 AoL I~! 1- 50MHZ':::t-, ~+1S I'-... ~Iil ~ Cl +16 -90 ~~ Oper-L'l0\' ~mi +14 111I +12 1M 10M -180 100M lG Frequency (Hz) A v = +2VN CLOSED-LOOP BANDWIDTH vs OUTPUT VOLTAGE SWING Av= +5VN CLOSED-LOOP BANDWIDTH vs OUTPUT VOLTAGE SWING s ~~O~ t~Wo 1\ r\ I 2 ~ lOOk 1M Frequency (Hz) 2-62 -135 ~ PMisr Frequency (Hz) 10k -180 lG Av= +10VN CLOSED-LOOP SMALL-SIGNAL BANDWIDTH c +12 lk I Frequency (Hz) +14 S. 8 -135 iI~-50It 1M r----I---r-r-I"M"n"I" 1..---r-,-,-T'TT'm":---"-'-'-T"T'TT'!1 ~ J o \ II :1 -2 1--t-+t+HtI-I--t-+++I+H-\--I--t-++++HI ! . ffir ,/AoL ~ 1--f-Li-++HtI-I--f--/.;±+I+H'H',-I--t-++++HI 0 RIL OL ........... "}. lG Av= +5VN CLOSED-LOOP SMALL-SIGNAL BANDWIDTH +16 j :..,.....-- ~"' Frequency (Hz) +18 eli Aoc ',# I'rm iii" Gal';;'t'-. lk II :1 +8 0 " c ;E +10 10M 100M " \ .. o lG lk 10k lOOk 1M 10M 100M lG Frequency (Hz) Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES (CONT) At Vee ~ ±5VDC. R, = 100n. and T, = +25°C unless otherwise noted. TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY vs SOURCE RESISTANCE Av= +10VN CLOSED-LOOP BANDWIDTH vs OUTPUT VOLTAGE SWING 100 RLI ~ ~oJ As = 1kn t\ ~:> i' '0 10 :--,t"< R~=500n .. .s ~ z ~s'~on Rs = 100n " C> J!! g ~~ 1k 10k 100k 1M 10M 100M 1111 0.1 1G 100 1k 10k 100k 10M 1M IIII 100M Frequency (Hz) Frequency (Hz) INPUT CURRENT NOISE SPECTRAL DENSITY VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs TEMPERATURE -a..-.. I I. L¥ < S 10 .~0 3.1 3.1 100 ~ " , 2.8 '~ :> .s .s" z " J§' z E "~ g 0 1- 10= 100kHz 2.5 2.8 ~ntNoise ~I::::::", 2.5 - Voltage Noise !l ! -!z E 2.2 2.2 1.9 1.9 ~ I o = 5 a. III 0.1 100 1k 10k 100k 1M 10M 100M -75 -50 Frequency (Hz) ~ 0 +25 +50 +100 +75 +125 Ambient Temperature (OC) INPUT OFFSET VOLTAGE CHANGE DUE TO THERMAL SHOCK INPUT OFFSET VOLTAGE WARM-UP DRIFT +200 -25 ;-----;--.,.---r-----;--.,.---, +1500 ~ " <: .<: 0'" " J§' g +100 " Iii C> +750 C> ;~ J§' g N -100 ;; ~ 5 0 -750 -1500 2 3 4 5 6 Time From Power Tum-On (min) Burr-Brown Ie Data Book Supplement, Vol. 33b -1 0 +1 +2 +3 +4 +5 Time From Thermal Shock (min) 2-63 o For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) At Vcc = ±5VDC. R, = 100n. and T. = +25°C unless otherwise noted. BIAS AND OFFSET CURRENT BIAS AND OFFSET CURRENT vs TEMPERATURE YO INPUT COMMON-MODE VOLTAGE 28 < a c III '" ! 0.8 23 -- Biaspurrent 18 0 24 ~ ;-- --- v V 0.6 V c 0.4 ~ 13 < a § 0 V j 0.2 15 0.8 -~Z: 21 ~ c III '" 18 15 -2 -1 0 +1 :I!l 0.2 0 / +3 ...2 +4 -75 -50 f 0: j• ~ i ..... Vo=OVDC +50 " iJl 60 ..... r--. ~ 0 {f -,20 10k 100k 1M +100 +125 V"PS ~ 20 1m 0 lill -,20 1k +75 ~ 0: 40 20 IS +25 iD 80 :E. 40 o a POWER SUPPLY REJECTION vs FREQUENCY r--r-- 60 -,25 Ambient Temperature (OC) COMMON-MODE REJECTION vs FREQUENCY c o 12 Common·Mode Voltage (V) iD 80 :E. § o Offset Current a -3 !c ;; 'Oietcufnt 8 -4 0.4 ~ (. 0 ! 0.6 10M 100M lG lk 10k lOOk Frequency (Hz) 1M 10M 100M lG Frequency (Hz) COMMON-MODE REJECTION YO INPUT COMMON-MODE VOLTAGE SUPPLY CURRENT YO TEMPERATURE 80 ~ t " 0: I 32 75 < 29 S. Vo= OVDC C !l: 70 ,.." 26 0 I '" J 65 60 23 -- 20 -5 -4 -3 -2 -1 a ... 1 +2 Common-Mode Voltage (V) 2-64 . . . .V V ...... I-- ~ I-- +3 +4 +5 -75 -50 -,25 0 +25 +50 +75 +100 ...125 Ambient Temperature (OC) Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES (CONT) At Vee = ±5VDC. R, = loon. and T. = +25'C unless otherwise noted. LARGE·SIGNAL TRANSIENT RESPONSE SMALL·SIGNAL TRANSIENT RESPONSE 25 o 50 Vo =2V Step 60 140 0.1, E g> ~ .....- ...- - 40 20 V V "- /'" .,.s / " F E G=-2VN 100 ./ 80 l--- ~ en 60 ..>"" 40 L---::. f---< 20 0.1% -3 -2 -5 -4 -6 -7 -6 -6 0.1% -10 o III D. o 6 FREQUENCY CHARACTERISTICS vs TEMPERATURE A OL • PSR. AND CMRvs TEMPERATURE 2.0 in 70 :9- 1.5 CMR -- CD a: PS~--.... :E 60 -~ "- Q. cl 5 --- Output Voltage Change (V) 80 « 4 2 Closed·Loop Gain (VN) a: en ... V 0.01% CI .....- ......... z~ o 120 o -1 () D. 001 80 ~ en ..--.... S 160 1 '" F Itau SETTLING TIME vs OUTPUT VOLTAGE CHANGE SETTLING TIME vs CLOSED·LOOP GAIN 100 r 200 100 nme(ns) Time (ns) 50 - " 1ii > 1.0 .~ ..> 12CD a: AOL 0.5 Settlinrnme / ~ "- l siew Rate - ".. L--- / c - - Gain.B';"dwldth o 40 -75 -50 -25 0 +25 +50 +75 +100 +125 Temperature ('C) Burr-Brown Ie Data Book Supplement. Vol. 33b -75 -50 -25 0 +25 +50 +75 +100 +125 Temperature ('C) 2-65 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) At Vee = ±5VDC, RL • 1000, and T" D +25°C unless othelWise noted. NTSC DIFFERENTIAL pHASE vs CLOSED-LOOP GAIN NTSC DIFFERENTIAL GAIN vs CLOSED-LOOP GAIN 0.5 I h3.58MHz . I I RL = 75n(Two Back-Terminated Outputs) 0.4 l<= '0; I ~ I I 0.3 Vo ~ OVto 2.1V Cl ~\!! 1I J 1.0 I I Vo = OV to 1.4V0.2 ~. ~ ~ c 0.1 "'\;. a 2 3 I I I 4 5 6 7 -V 9 8 if. "iii I 0.4 I-",-+--+''-+--+--+~'''''''''-I--I---::I r--+--r~~~~~~T---t-~~ 02 o LEt=E:~DJU 1 4 3 2 5 6 7 9 SMALL-SIGNAL HARMONIC DISTORTION vs FREQUENCY LARGE-SIGNAL HARMONIC DISTORTION vs FREQUENCY .I / ~ -60 10 G =+2VN Vo = 2Vp-p RL = son "U -40 / ~ c 0 'f! -50 ./ ,/ ~ is -70 2I).- .~ -60 V~ ~ 31 below nOi~fl Iloor -30 lOOk m" 0 E j! -60 1M 10M 100M r -70 -SO lOOk ~ ill> ..... 1-' 10M Frequency (Hz) Frequency (Hz) 1MHz HARMONIC DISTORTION vs POWER OUTPUT 10MHz HARMONIC DISTORTION vs POWER OUTPUT -40 100M -30 G =+2VN RL .son Ie = 10MHz G =+2VN RL = 50n Ie = lMHz t~~- f.-- .......V :--J -- 0.25Vp-p I 0.5Vp-p 2VP"fJ +5 +10 -100 -20 -15· ./ -10 .....v y V t~ I 1Vp-p -5 Power Output (dBm) - --V V 21", 31 below noise floor I 0.125Vp-p 2-66 8 Closed-Loop Gain (VN) RL = son '"c: :E. :I: I I I -30 "U -50 '1 +---t---/ Closed-Loop Gain (VN) G =+2VN Vo =0.5Vp-p (J I 1-"'-+-- 0.6 10 -40 ~ I RL = 75n (Two Back-Terminated Outputs) m yo=oyto0y""""" ~"~ .. I. 1=3.58MHz 0.8 O.l25Vp-p O.25Vp-p -90 +15 -20 -15 -10 -5 0.5Vp·p6 p - p o +5 2Vp-p +10 +15 Power Output (dBm) Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) APPLICATIONS INFORMATION DISCUSSION OF PERFORMANCE The OPA621 provides a level of speed and precision not previously attainable in monolithic form. Unlike current feedback amplifiers, the OPA621's design uses a "Classical" operational amplifier architecture and can therefore be used in all traditional operational amplifier applications. While it is true that current feedback amplifiers can provide wider bandwidth at higher gains, they offer many disadvantages. The asymmetrical input characteristics of current feedback amplifiers (i.e. one input is a low impedance) prevents them from being used in a variety of applications. In addition, unbalanced inputs make input bias current errors difficult to correct. Bias current cancellation through matching of inverting and non-inverting input resistors is impossible because the input bias currents are uncorrelated. Current noise is also asymmetrical and is usually significantly higher on the inverting input. Perhaps most important, settling time \0 0.01 % is often extremely poor due to internal design tradeoffs. Many current feedback designs exhibit settling times to 0.01 % in excess of 10 microseconds even though 0.1 % settling times are reasonable. Such amplifiers are completely inadequate for fast settling 12-bit applications. The OPA621's "Classical" operational amplifier architecture employs true differential and fully symmetrical inputs to eliminate these troublesome problems. All traditional circuit configurations and op amp theory apply to the OPA621. The use of low-drift thin-film resistors allows internal operating currents to be laser-trimmed at waferlevel to optimize AC performance such as bandwidth and settling time, as well as DC parameters such as input offset voltage and drift. The result is a wideband, high-frequency monolithic operational amplifier with a gain-bandwidth product of 500MHz, a 0.01% settling time of 25ns, and an input offset voltage of 100~V. WIRING PRECAUTIONS Maximizing the OPA621's capability requires some wiring precautions and high-frequency layout techniques. Oscillation, ringing, poor bandwidth and settling, gain peaking, and instability are typical problems plaguing all high-speed amplifiers when they are improperly used. In general, all printed circuit board conductors should be wide to provide low resistance, low impedance signal paths. They should also be as short as .possible; The entire physical circuit should be as small as practical. Stray capacitances should be minimized, especially at high impedance nodes, such as the amplifier's input terminals. Stray signal coupling from the output or power supplies to the inputs should be minimized. All circuit element leads should be no longer than 1/4 inch (6mm) to minimize lead inductance, and low values of resistance should be used. This will minimize time constants formed with the circuit capacitances and will eliminate stray. parasitic circuits. Grounding is the most important application consideration for the OPA621. as it is with all high-frequency circuits. Os- cillations at frequencies of 500MHz and above can easily occur if good grounding techniques are not used. A heavy ground plane (20z copper recommended) should connect all unused areas on the component side. Good ground planes can reduce stray signal pickup, provide a low resistance, low inductance common return path for signal and power, and can conduct heat from active circuit package pins into ambient air by convection. Supply bypassing is extremely critical and must always be used, especially when driving high current loads. Both power supply leads should be bypassed to ground as close as possible to the amplifier pins. Tantalum capacitors (IIJF to 101JF) with very short leads are recommended. Although not required, a parallel 0.011JF ceramic may be added if desired. Surface mount bypass capacitors will produce excellent results due to their low lead inductance. Additionally, suppression filters can be used to isolate noisy supply lines. Properly bypassed and modulation-free power supply lines allow full amplifier output and optimum settling time performance. IIII -.-.. I I. A. Points to Remember 1) Don't use point-to-point wiring as the increase in wiring inductance will be detrimental to AC performance. However. if it must be used, very short, direct signal paths are required. The input signal ground return, the load ground return, and the power supply common should all be connected to the same physical point to eliminate ground loops, which can cause unwanted feedback. 2) Good component selection is essential. Capacitors used in critical locations should be a low inductance type with a high quality dielectric material. Likewise, diodes used in critical locations should be Schottky barrier types, such as HP50822835 for fast recovery and minimum charge storage. Ordinary diodes will not be suitable in RF circuits. 3) Whenever possible, solder the OPA621 directly into the PC board without using a socket. Sockets add parasitic capacitance and inductance, which can seriously degrade AC performance or produce oscillations. If sockets must be used. consider using zero-profile solderless sockets such as Augat part number 8134-HC-5P2. Alternately, Teflon'" standoffs located close to the amplifier's pins can be used to mount feedback components. 4) Resistors used in feedback networks should have values of a few hundred ohms for best performance. Shunt capacitance problems limit the acceptable resistance range to about lIill on the high end and to a value that is within the amplifier's output drive limits on the low end. Metal film and carbon resistors will be satisfactory, but wirewound resistors (even "non-inductive" types) .are absolutely unacceptable in high-frequency circuits. 5) Surface mount components (chip resistors, capacitors, etc) have low lead inductance and are therefore strongly recommended. Circuits using all surface mount components with the OPA621KU (SOIC package) will offer the best AC performance. The parasitic package inductance and capaciTcRon3 E. T. On PenH de Nemours & Co. Burr-Brown Ie Data Book Supplement. Vol. 33b 2 2-67 :E CC o = 5 III A. o For Immediate Assistance, Contact Your Local Salesperson tance for the SOIC is lower than the both the Cerdip and 8lead Plastic DIP. 6) Avoid overloading the output. Remember that output current must be provided by the amplifier to drive its own feedback network as well as to drive its load. Lowest distortion is achieved with high impedance loads. 7) Don't forget that these amplifiers use ±5V supplies. Allhough they will operate perfectly well with +5V and -5.2V, use of ±15V supplies will destroy the part. 8) Standard commercial test equipment has not been designed to test devices in the OPA62l's speed range. Benchtop op amp testers and ATE systems will require a speCial test head to successfully test these amplifiers. 9) Terminate transmission line loads. Unterminated lines, such as coaxial cable, can appear to the amplifier to be a capacitive or inductive load. By terminating a transmission line with its characteristic impedance, the amplifier's load then appears purely resistive. 10) Plug-in prototype boards and wire-wrap boards will not be satisfactory. A clean layout using RF techniques is essential; there are no shortcuts. OFFSET VOLTAGE ADJUSTMENT The OPA62l's input offset voltage is laser-trimmed and will require no further adjustment for most applications. However. if additional adjustment is needed, the circuit in Figure I can be used without degrading offset drift with temperature. Avoid external adjustment whenever possible since extraneous noise, such as power supply noise, can be inadvertently coupled into the amplifier's inverting input terminal. Remember that additional offset errors can be created by the amplifier's input bias currents. Whenever possible, match the impedance seen by both inputs as is shown with R3. This will reduce input bias current errors to the amplifier's offset current. which is typically only 0.2J,lA. 20kn >-.Jw'--....- 2 250 8 G=+5VN 0.1 1/ j V <" E III G=+2VN 100 lk lOOk 10k 1M 10M 100M c: ~ 0 :s!! ~,g Frequency (Hz) FIGURE 3. Small-Signal Output Impedance vs Frequency. OPA621 maintains very low closed-loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain is decreasing with frequency. o +Isc .§. 200 ~ 0; 0.01 150 l-- I..--" K I'-r--. ~ -Isc r--r-- t--t-- 100 '" 50 -75 -50 -25 +25 +50 +75 +100 +125 Ambient Temperature (·C) THERMAL CONSIDERATIONS The OPA621 does not require a heat sink for operation in most environments. The use of a heat sink, however, wilI [ I 1.0 ~ c: ~ 0.8 Cl 0.6 :i :;; Cerdip / Package 3: 0 "- 0.4 0; E g .5 ~ " ""~ 0.2 o o +25 +50 +75 +100 +125 and the junction-to-ambient thermal resistance, 9JA , of each package. The variation of short-circuit current with temperature is shown in Figure S. CAPACITIVE LOADS The OPA621's output stage has been optimized to drive resistive loads as low as SOO. Capacitive loads, however, will decrease the amplifier's phase margin which may cause high frequency peaking or osciIIations. Capacitive loads greater than lSpF should be buffered by connecting a small resistance, usually SO to 2S0, in series with the output as shown in Figure 6. This is particularly important when driving high capacitance loads such as flash AID converters. I Plastic. SOIC Packages - +150 Ambient Temperature (·C) (As typically 50 to 250) FIGURE 4. Maximum Power Dissipation. reduce the internal thermal rise and wiII result in cooler, more reliable operation. At extreme temperatures and under full load conditions a heat sink is necessary. See "Maximum Power Dissipation" curve, Figure 4. The internal power dissipation is given by the equation P D= PDQ + P DL' where PDQ is the quiescent power dissipation and P DL is the power dissipation in the output stage due to the load. (For±Vcc= ±SV, PDQ = lOVx 28mA= 280mW, max). For the case where the amplifier is driving a grounded load (RL) with a DC voltage (±VOUT) the maximum value of P DL occurs at ±VOUT = ±Vcc/2, and is equal to P DL' max = (±Vccf/4RL' Note that it is the voltage across the output transistor, and not the load, that determines the power dissipated in the output stage. When the output is shorted to common PDL = SV X ISOmA = 7S0mW. Thus. P D= 280mW + 7S0mW:; lW. Note that Burr-Brown Ie Data Book Supplement, Vol. 33b IIII -~ I I. FIGURE S. Short-Circuit Current vs Temperature. 1.2 .. FIGURE 6. Driving Capacitive Loads. In general, capacitive loads should be minimized for optimum high frequency performance. Coax lines can be driven if the cable is properly terminated. The capacitance of coax cable (29pF/foot for RG-S8) wiII not load the amplifier when the coaxial cable or transmission line is terminated in its characteristic impedance. 2-69 S ~ o = 5 a. III o For Immediate Assistance, Contact Your Local Salesperson COMPENSATION The OPA621 is stable in inverting gains of ?-2VN and in non-inverting gains ?+2VN. Phase margin for both configurations is approximately 50°. Inverting and non-inverting gains of unity should be avoided. The minimum stable gains of +2VN and -2VN are the most demanding circuit configurations for loop stability and oscillations are most likely to occur in these gains. If possible, use the device in a noise gain greater than three to improve phase margin and reduce the susceptibility to oscillation. (Note that, from a stability standpoint, an inverting gain of -2VN is equivalent to a noise gain of 3.) Gain and phase response for other gains are shown in the Typical Performance Curves. The high-frequency response of the OPA621 in a good layout is flat with freql1ency for higher-gain circuits. However, low-gain circuits and configurations where large feedback resistances are used, can produce high-frequency gain peaking. This peaking can be minimized by connecting a small capacitor in parallel with the feedback resistor. This capacitor compensates for the closed-loop, high frequency, transfer function zero that results from the time constant formed by the input capacitance of the amplifier (typically 2pF after PC board mounting), and the input and feedback resistors. The selected compensation capacitor may be a trimmer, a fixed capacitor, or a planned PC board capacitance. The capacitance value is strongly dependent on circuit layout and closed-loop gain. Using small resistor values will preserve the phase margin and avoid peaking by keeping the break frequency of this zero sufficiently high. When high closed-loop gains are required, a three~resistor attenuator (tee network) is recommended to avoid using large value resistors with large time constants. SETTLING TIME Settling time is defined as the total time required, from the input signal step, for the output to settle to within the specified error band around the final value. This error band is expressed as a percentage. of the value of the output transition, a 2V step. Thus, settling time to 0.01 % requires an error band of ±2oo!!V centered around the final value of 2V. Settling time, specified in an inverting gain of two, occurs in only 25ns to 0.01% for a 2V step, making the OPA621 one of the fastest settling monolithic amplifiers commercially available. Settling time increases with closed-loop gain and output voltage change as described in the Typical Performance Curves. Preserving settling time requires critical attention to the details as mentioned under "Wiring Precautions." The amplifier also recovers quickly from input overloads. Overload recovery time to linear operation from a 50% overload is typically only 30ns. In practice, settling time measurements on the OPA621 prove to be very difficult to perform. Accurate measurement is next to impossible in all but the very best equipped labs. Among other things, a fast flat-top generator and high speed oscilloscope are needed. Unfortunately, fast flat-top genera~ tors, which settle to 0.01 % in sufficient time, are scarce and expensive. Fast oscilloscopes, however, are more commonly available. For best results a sampling oscilloscope is recommended. Sampling scopes typically have bandwidths that are greater than IGHz and very low capacitance inputs. They also exhibit faster settling times in response to signals that would tend to overload a real-time oscilloscope. Figure 7 shows the test circuit used to measure settling time for the OPA621. This approach uses a 16-bit sampling oscilloscope to monitor the input and output pulses. These waveforms are captured by the sampling scope, averaged, and then subtracted from each other in software to produce the error signal. This technique eliminates the need for the traditional "false-summing junction," which adds extra parasitic capacitance. Note that instead of an additional flat-top generator, this technique uses the scope's built-in calibration source as the input signal. I pF to 4pF (Adjust for Optimum Settling) o to +2V. f = 1.25MHz JL VIN~ +5VDC NOTE: Test fixture built using all surface·mount components. Ground plane used on component side and entire fixture enclosed in metal case. Both power supplies bypassed with IO"F Tantalum II O.OI"F c~ramlc capacitors. It is directiy connected (without cable) to TIME CAL trigger source on Sampling Scope (Data Precision's Data 61 00 with Model 640· I plug·in). Input monitored with Active Probe (Channell). To Active Probe (Channel 2) on sampling scope. FIGURE 7. Settling Time Test Circuit. 2-70 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) DIFFERENTIAL GAIN AND PHASE Differential Gain (DG) and Differential Phase (DP) are among the more important specifications for video applications. DG is defined as the percent change in closed-loop gain over a specified change in output voltage level. DP is defined as the change in degrees of the closed-loop phase over the same output voltage change. Both DG and DP are specified at the NTSC sub-carrier frequency of 3.S8MHz. DG and DP increase with closed-loop gain and output voltage transition as shown in the Typical Performance Curves. All measurements were performed using a Tektronix model VM700 Video Measurement Set. DISTORTION ~ r-- c: :@ -50 * -70 2f is .11 c: P r--:::- '" :I: \ ...::: -80 3f -90 L G=+2VN / 0 § o :1 45 40 "0 35 a. 30 . I en -- PSR :E- g ~ 0: +Vs PSRR637 627 40 ..... a. POWER-SUPPLY REJECTION AND COMMON-MODE REJECTION YS TEMPERATURE POWER-SUPPLY REJECTION YS FREQUENCY S z~ o ~r-... ............. ~ ::E 5 w (,) 110 20 o 100 10 lk 10k lOOk 1M 105 -75 10M a. -50 -25 Frequency (Hz) 0 25 50 75 100 125 Temperature (OC) SUPPLY CURRENT YS TEMPERATURE OUTPUT CURRENT LIMIT YS TEMPERATURE 100 80 ;( 7.5 ;( §. §. 1: 60 " !!! .3 -r-- 7 t - j 40 ::> 20 -25 0 25 50 75 100 125 Temperature (OC) Burr-Brown Ie Data Book Supplement, Vol_ 33b .! -~ ~Vo=+10V- .I -r-- -.;:::: ~ r- --: ~ -ILatV o =-10V- I - - I o -50 - -..;; c:--. :--- 'I--ILalVo = ~V 0 6 -75 r-- 1!1 ::> en 6.5 ./ I- (,) ~ +ILatV o = OV -75 -50 -25 o 25 50 Temperature (OC) 75 100 1~5 2-79 o For Immediate Assistance, Contact Your Local· Salesperson TYPICAL PERFORMANCE CURVES (CONT) T. = +25'C, v, = ±15V unless otherwise noted. OPA637 GAIN·BANDWIDTH AND SLEW RATE YS TEMPERATURE OPA627 GAIN·BANDWIDTH AND SLEW RATE YS TEMPERATURE 60 24 160 120 Slew Fiate i'--I'--. r--..... "'- I- I'-I'- -00 -25 0 25 50 75 !"N 100 c:. ii a: a ~ 80 55 ~ 100 ........... ell 140 -...... ........... 60 120 ~ a: j 100 80 40 50 125 u; ~ --- -- -- GBW OJ ~ , I' ~ ;0 --- I -........... .c ~ I'- GBW 8 -75 - Slew Rate u; -75 -00 -25 25 0 Temperature ('C) 50 75 100 125 Temperature ('C) OPA637 TOTAL HARMONIC DISTORTION + NOISE YS FREQUENCY OPA627 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 0.01 0.1 ~ z lz + 0.001 + 0 ~ r= I- 0.0001 G~+50 Measurement BW: 80kH 1 . " 0 . 0 0.001 = 10 0.0001 ......................." -____............................................'-U......_~ 20 100 1k 10k 20k 20 100 1k 10k 20k Frequency (Hz) Frequency (Hz) INPUT BIAS CURRENT INPUT BIAS AND OFFSET CURRENT ys JUNCTION TEMPERATURE vs POWER SUPPLY VOLTAGE 10k ~ I. ~ ::; a. .E TO.99 Z- C 100 I.) NOTE: Measured fully warmed·up. / /... 1k .;.; 10 ..... 1ooL- Plastic......~ DIP,Sq!9> los ,c:;... // 0.1 -QO 2-80 -25 0 50 75 100 25 Junction Temperature ('C) 125 150 o ±4 rQ-99 with 0807HS Heat Sink ±6 ±8 ±10 ±12 ±14 ±16 ±18 Supply Voltage (±Vs ) Burr-Brown feData Book Supplement, Vol. 33b Dr, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, Vs = ±15V unless otherwise noted. INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE 1.2 INPUT OFFSET VOLTAGE WARM-UP vs TIME 50 I IlJyln~ ~Ua! I I , Common·Mode Ran e ~ 25 " ~ .. .c 0 " , ~ -25 Beyond Unear Common-Mode Ranoe 0 111I11111111 0.8 -15 0 f -50 o -5 -10 10 15 2 0 Camman·Made Valtage (V) 5 4 3 IIII Time From Power Tum·On (Min) -I I. ~ IlL S SETTL1NG TIME vs CLOSED· LOOP GAIN MAX OUTPUT VOLTAGE vs FREQUENCY 100 30 - Error Band: ~O.OI% == f= PA637 io / OPA627 5 ,Y " OPA637 r?l~t627 '- .......... o I 0.1 lOOk 1M 10M -1 100M ~~ I u;- .s 1000 _ RF lS" ..JL -'5V + "E 2kQ SEITLING TIME vs LOAD CAPACITANCE 3 OPA627 R, 2kQ I ~2 ~2kQ C. 6pF "E '" ;;; "'" ;:: ~ '"" o -1000 Closed-Loop Gain (VN) SEITLiNG TIME vs ERROR BAND 1500 -100 -10 Frequency (Hz) III IlL I / el- I Error Band: -±0.01"1o 500 I 1 /' V Y 1 ;:: .S; OPA637 G=-4 ~ :::-OP~27 G=-1 .-:::: ~ roo- 0 0.001 0.01 0.1 10 Error Band ("10) Burr-Brown Ie Data Book Supplement, Vol_ 33b o 150 200 300 400 500 Load Capacitance (PF) 2-81 For Immediate Assistance, Contact Your Local Salesperson APPLICATIONS INFORMATION The OPA627 is unity-gain stable. The OPA637 may be used to achieve higher speed and bandwidth in circuits with noise gain greater than five. Noise gain refers to the closed-loop . gain of a circuit as if the non-inverting op amp input were being driven. For example, the OPA637 may be used in a non-inverting amplifier with gain greater than five, or an inverting amplifier of gain greater than four. OFFSET VOLTAGE ADJUSTMENT The OPA627/637 is laser-trimmed for low offset voltage and drift. so many circuits will not require external adjustment. Figure 3 shows the optional connection of an external potentiometer to adjust offset voltage. This adjustment should not be used to compensate for offsets created elsewhere in a system (such as in later amplification stages or in an AID converter) because this could introduce excessive temperature drift. When choosing between the OPA627 or OPA637, it is important to consider the high frequericy noise gain of your circuit configuration. Circuits with a feedback capacitor (Figure 1) place the op amp in unity noise-gain at high frequency. These applications must use the OPA627 for proper stability. An exception is the circuit in Figure 2, where a small feedback capacitance is used to compensate for the input capacitance at the op amp's inverting input. In this case, the closed-loop noise gain remains constant with frequency, so if tLle closed-loop gain is equal to five or greater. the OPA637 may be used. 10kQ 101M!} Potentiometer (100k!} preferred) 6 -VS ±10mV Typical Trim Range FIGURE 3. Optional Offset Voltage Trim Circuit. NOISE PERFORMANCE Some bipolar op amps may provide lower voltage noise performance, but both voltage noise .and bias current noise contribute to the total noise of a system. The OPA627/637 is unique in providing very low voltage noise and very low current noise. This provides optimum noise performance over a wide range of sources, including reactive source impedances. This can be seen in the performance curve showing the noise of a source resistor combined with the noise of an OPA627. Above a 2kn source resistance, the op amp contributes little additional noise. Below lkn, op amp noise dominates over the resistor noise, but compares favorably with precision bipolar op amps. FIGURE 1. Circuits with Noise Gain Less than Five Require the OPA627 for Proper Stability. c R, ~ 1 = CIN + eSTRAY C2=~ R2 FIGURE 2. Circuits with Noise Gain Equal to or Greater than Five May Use the OPA637. 2-82 CIRCUIT LAYOUT As with any high speed, wide bandwidth circuit, careful layout will ensure best performance. Make short, direct interconnections and avoid stray wiring capacitanceespecially at the input pins and feedback circuitry. The case connection (pin 8 of TO-99 metal package only) should be connected to an AC ground for lowest possible pickup of external fields. While DC ground would be the most likely choice, pin 8 could also be connected to either power supply. (The case is not internally connected to the negative power supply as it is with most common op amps.) For lowest possible input bias current. the case may be driven as a guard-see Input Bias Current section. Pin 8 of the plastic DIP and SOIC versions has no internal connection. Power supply connections should be bypassed with good high frequency capacitors positioned close to the op amp pins. In most cases O.lJ.lF ceramic capacitors are adequate. The OPA627/637 is capable of high output current (in Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1.. 800·548·6132 (USA Only) excess of 4SmA). Applications with low impedance loads or capacitive loads with fast transient signals demand large currents from the power supplies. Larger bypass capacitors such as IllF solid tantalum capacitors may improve dynamic performance in these applications. INPUT BIAS CURRENT Difet fabrication of the OPA627/637 provides very low input bias current. Since the gate current of a FET doubles approximately every 10°C, to achieve lowest input bias current, the die temperature should be kept as low as possible. The high speed and therefore higher quiescent current of the OPA627/637 can lead to higher chip temperature. A simple press-on heat sink stich as the Burr-Brown model 807HS (TO-99 metal package) can reduce chip temperature by approximately ISoC, lowering the IB to one-third its warmed-up value. The 807HS heat sink can also reduce lowfrequency voltage noise caused by air currents and thermoelectric effects. See the data sheet on the 807HS for details. Temperature rise in the plastic DIP and SOIC packages can be minimized by soldering the device to the circuit board. Wide copper traces will also help dissipate heat. The OPA627/637 may also be operated at reduced power supply voltage to minimize power dissipation and temperature rise. Using ±5V power suppiies reduces power dissipation to one-third of that at ±ISV. This reduces the IB of TO99 metal package devices to approximately one-fourth the value at ±ISV. Leakage currents between printed circuit board traces can easily exceed the input bias current of the OPA627/637. A circuit board "guard" pattern (Figure 4) reduces lealaige effects. By surrounding critical high impedance input circuitry with a low impedance circuit connection at the same potential, leakage current will flow harmlessly to the lowimpedance node. The case-connection (TO-99 metal pack- age only) may also be driven at guard potential to minimize any leakage which might occur from the input pins to the case. The case is not internally connected to -Vs' Input bias current may also be degraded by improper handling or cleaning. Contamination from handling parts and circuit boards may be removed with cleaning solvents and deionized water. Each rinsing operation should be followed by a 30-minute bake at 8SoC. Many FET-input op amps exhibit large changes in input bias current with changes in input voltage. Input stage cascode circuitry makes the input bias current of the OPA627/637 virtually constant with wide common-mode voltage changes. Th~s is ideal for accurate high input-impedance buffer a p P I i - " cations. PHASE-REVERSAL PROTECTION The OPA627/637 has internal phase-reversal protection. Many FET-input op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This is most often encountered in non-inverting circuits when the input is driven below -12V, causing the output to reverse into the positive rail. The input circuitry of the OPA627/637 does not induce phase reversal with excessive commonmode voltage, so the output limits into the appropriate rail. OUTPUT OVERLOAD When the inputs to the OPA627/637. are overdriven, the output voltage of the OPA627/637 smoothly limits at approximately 2.SV from the positive and negative power supplies. If driven to the negative swing limit, recovery takes approximately SOOns. When the output is driven into the positive limit, recovery takes approximately 6lJ.S. Output recovery of the OPA627 can be improved using the output clamp circuit shown in Figure S. Diodes at the inverting input prevent degradation of input bias current. . Buffer """'-0 Out -;;;:6__ Ino-;NVL~--------~f, ~6_1---0 Out Casell) Board Layout for Input Guarding: Guard lOp and bottom of board. Alternate-use Teflon' standoff for sensitive Input pins. 8 To Guard Drive Teflon> E.I. du Pont de Nemours & Co. NOTE: (1) Case connected to pin 8 on TO·99 package only-see text FIGURE 4. Connection of Input Guard for Lowest lB' Burr-Brown Ie Data BookSupplement. Vol. 33b 2-83 I!III -:::i... IlL S o = 5 III IlL o For Immediate Assistance, -Contact Your Local Salesperson (2) HP 5082-2811 Diode Bridge BB: PWS740-3 1kD ZO, : 10V IN961 v,o-"\Af\t-_-; >-4----_-0 Vo Clamps output atVo=±11.5V FIGURE 5. Clamp Circuit for Improved Overload Recovery. CAPACITIVE LOADS As with any high-speed op amp, best dynamic performance ean be achieved by minimizing the capacitive load. Since a load capacitance presents a decreasing impedance at higher frequency. a load capacitance which.is easily driven by a slow op amp can cause a high-speed op amp to perform poorly. See the typical curves showing settling times as a function of capacitive load. The lower bandwidth of the OPA627 makes it the better choice for driving large capacitive loads. Figure 6 shows a circuit for driving very large load capacitance. This circuit's two-pole response can also be used· to sharply limit system bandwidth. This is often useful in reducing the noise of systems which do not require the full bandwidth of the OPA627. INPUT PROTECTION The inputs of the OPA627/637 are protected for voltages between +Vs + 2V and -Vs - 2V. If the input voltage can exceed these limits. the amplifier should be protected. The diode clamps shown in Figure 7a will prevent the input volta~e from exceeding one forward diode voltage drop beyond the power supplies-well within the safe limits. If the input source can deliver current in excess of the maximum forward current of the protection diodes, use'a series resistor, Rs' to limit the current. Be aware that adding resistance to the input will increase noise. The 4n V/-.JHz theoretical thermal noise of a 11<0 resistor will add to the 4.5nV/ ..JHz noise of the OPA627/637 (by the square-root of the sum of the squares), producing a total. noise of 6nVJ-.JHz. Resistors below 1000 add negligible noise. Leakage current in. the protection diodes can increase the total input bias current of the circuit. The specified maximum leakage current for commonly used diodes such as the lN4l48 is approximately 25nA-more than .a thousand times largerthan the input bias current of the OPA627/637. Leakage current of these diodes is typically much lower and may be adequate in. many applications. Light faliing on the junction of the protection diodes can dramatically increase leakage current. so common glass-packaged diodes should be shielded from ambient light. Very low leakage can be achieved by using a diode-connected FET as shown. The 2N4117 A is specified at 1pA and its metal case shields the jnnction from light. Sometimes input protection is required on I/V converters of inverting amplifiers (Figure 7b). Although in normal opera~ tion •.the voltage at the summing junction will be near zero (equal. to the offset voitage of the amplifier), large input transients may cause this node to exceed 2V beyond the power supplies. In this case, the summing junction should be protected with diode clamps connected to ground. Even with the the low voltage present at the summing junction, common signal diodes may have excessive leakage current. Since the reverse voltage on these diodes is clamped, a diode-connected signal iransistorcan be used as an inexpensive low leakage diode (Figure 7b)_ / 0 Optional Rs· 0: IN4148 - 25nA Leakage 2N4117A-1pA Leakage (a) G=+1 BW,,1MHz 1 - - - - - - - - --I : G= 1+!:!E At: I Rt I I I - Optional Gain - I I : __G.!l~::1 _____: o (b) NC For Approximate Butterworth Response: CF= 2RoCL RF f RF»Ro FIGURE 7. Input Protection Circuits. 1 ->dB = 2n~1). % C. ct FIGURE 6. Driving Large Capacitive Loads_ 2-84 Burr-Brown ICData Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) LARGE·SIGNAL RESPONSE SMALL·SIGNAL RESPONSE When used as a unily·gain buffer. large common·mode input voltage steps produce transient variations In input-stage currents. This causes the rising edge to be slower and falling edges to be faster than nominal slew rates observed in higher-gain circuits. ~I + G= 1 o 12 III OPA627 -ii:~ FIGURE 8. OPA627 Dynamic Perfonnance. G = +1. S LARGE·SIGNAL RESPONSE ..I ;I o ia. III o 6pP When driven with a very fast input step (left). common·mode transients cause a slight variation in input stage currents which will reduce output slew rate. If the input step slew rate is reduced (right). output slew rate will Increase slighijy. G--1 'NOTE: Optimlm value will depend on circuit board layout and stray capacitance at the Inverting Input. FIGURE 9. OPA627 Dynamic Perfonnance. G =-1. Burr-Brown Ie Data Book Supplement, Vol. 33b 2-85 For Immediate Assistance, Contact Your Local Salesperson OPA637 LARGE-SIGNAL RESPONSE OPA637 SMALL-SIGNAL RESPONSE 4pF· soon ·NOTE: Optimum value will depend on circuit board layout and capacitance al Inverting Input . FIGURE 10. OPA637 Dynamic Response, G = 5_ Error Out 2kn High Quality Pulse Generator >-~-o±5V Out -15V OPA627 OPA637 RI • R{ 2kn 500n C, Error Band (0.01%) 6pF 4pF ±O.5mV ±O.2mV NOTE: C, is selected for best settling time performance depending on test fixture layout. Once optimim value Is determined, a fixed capacitor may be used. FIGURE 11. Settling Time and Slew Rate Test Circuit. 2-86 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) -In Gain = 100 CMRR= 116dB Bandwidth .IMHz 0------1 1------------------, 2I Input Common-Mode Ran~e =±5V I I I I I I 31 3pF 25kU 25kU I I INAI05 Differential Amplifier I I I 16 25kll L_________ ... In I5 Outpul I I I ~5~~ _____ : 0------1 DifferenUal Voltage Gain = I ... 2R, IRa FIGURE 12. High Speed Instrumentation Amplifier, Gain III = 100_ .--a... I I I. -In Gain = 1000 CMRR = 116dB Bandwidth = 400kHz 0------1 1-----------------Input Common-Mode Range = ±IOV 10m +In RG 3pF 2I 10kO I I I I I I 31 INAI06 Differential Amplifier : 10kll 100kU 5 o = 5 a. Output ~--------- 0--------1 Differential Voltage Gain = (I + 2R, IRa) FIGURE 13. High Speed Instrumentation Amplifier, Gain II o • 10 = 1000. This composite amplifier uses the OPA603 current-feedback op amp to provide extended bandwidth and slew rate at high closed-loop gain. The feedback loop is closed around the composite amp. preserving the precision Input characteristics 01 the OPA627/637_ Use separate power supply bypass capacitors for each op amp. >-+--~-oVo R," 1500 lor±IOV Out ·Minimize capacitance at this node. GAIN (VN) 100 1000 A, R, R, R, R, ~dB OPAMP (0) (kll) (0) (kO) (MHz) SLEW RATE (VIps) OPA627 OPA637 50.5111 49.9 4.99 4.99 20 12 IS II 700 500 NOTE: (I) Closest 112"10 value. FIGURE 14. Composite Amplifier for Wide Bandwidth. Burr-Brown Ie Data Book Supplement, Vol.33b 2-87 For Immediate Assistance, Contact Your Local Salesperson BURR-BROWN@ IESIESII • OPA660 ADVANCE INFORMATION SUBJECT TO CHANGE Wide OPERATIONAL AMPLI FEATURES iTanscondtlctance of the OTA can be adjusted resistor, allowing bandwidth, quiesand gain tradeoffs to be optimized. buffer stage provides 700MHz bandwidth and 2000V/J.IS slew rate. When combined with the OTA section, the OPA660 can be interconnected as a current-feedback amplifier. Used as basic building blocks, . the OPA660 can simplify the design of complex signal processing stages in video systems, communications equipment and high-speed data acquisition circuitry. The OPA660 is packaged in SO-8 surface-mount, and 8-pin plastic DIP packages and is specified for the industrial temperature range. 10 Transfer Characteristics international Airport industrial Park • Mailing Addrasa: PO Box 11400 • TUcson, AZ 85734 • Street Addresa: &730 S. Tucson Blvd. • Tucson, AZ 85706 T81:(602)746-1111 • Twx: 91Q.952·1111 • Cable:BBRCORP • T.lex:0&H491 • FAX: (602)889-1510 ' Immediate Product Info: (BOO) 546-&132 PDS·1072 2-88 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL Typical at 10 = 20mA. Vs = ±5VDC. T A = +25'C. R, = soon unless otherwise specified. PARAMETER CONDInONS UNITS OTA TRANSCONDUCTANCE Transconductance = OV 75 200 OPEN LOOP GAIN Qpen Loop Gain mAN dB 60 Initial ±20 vs Temperature vs Supply (tracking) vs Supply (non-tracking) vs Supply (non-tracking) 0 CD CD 2 0 mV I'VI'C dB dB dB OTA NONINVERTING INPUT BIAS CURRENT Initial I1A vs Temperature nAl'C vs Supply (tracking) vs Supply (non-tracking) vs Supply (non-tracking) nAN nAN nAN I1A Qulput Bias Current vs Temperature nAl'C vs Supply (tracking) vs Supply (non-tracking) vs Supply (non-tracking) I'AIV I'AIV I'AIV OTAOUTPUT Current QUlput Qulput QUlput mA V nllpF BUFFER OFFSET Initial ±20 mV I'VI'C dB dB dB IIII --... a. II. :E C ~ Z 0 5 III ±3 nAl'C ±750 ±1500 ±SOO 1 Harmonic Distortion Slew Rate Settling Time 0.1 % Rise Time (10% to 90%) Vo =±2.5V 3.5BMHz. at 0.7V 3.5BMHz. at 0.7V 2nd Harmonic 3rd Harmonic 5V Step 2V Step Va = 100mVp-p 5V BUFFER RATED OUTPUT Voltage Qulput Current QUlput Gain ±4.00 8 0.96 R, =5k!.l Qulput Impedance POWER SUPPLY Rated Voltage Derated Performance Burr-Brown Ie Data Book Supplement, Vol.33b 1 nAN nAN nAN Mn I 5 nVNHz 700 550 0.1 0.1 -65 -90 2000 25 1 2 MHz MHz % Degrees dB dB ±4.15 15 0.975 0.99 B 2 V mA VN VN VII'S ns ns ns n ±5 ±4.5 I1A ±5 10 ±5.5 V V 2-89 a. 0 For Immediate Assistance, Contact Your Local Salesperson BURR - BROWN® OPA675 OPA676 IElElI Wideband Switched-Input OPERATIONAL AMPLIFIER FEATURES APPLICATIONS • FAST SETTLING: 9ns (1%) • WIDE BANDWIDTH: 185MHz (Ay • PROGRAMMABLE-GAIN AMPLIFIER =10) • FAST 2-INPUT MULTIPLEXER • LOW OFFSET VOLTAGE: ±250JlV • SYNCHRONOUS DEMODULATOR • TWO LOGIC SELECTABLE INPUTS • PULSEIRF AMPLIFIERS • FAST INPUT SWITCHING: 6ns (TTL) • VIDEO AMPLIFIERS • 16-PIN DIP PACKAGE • ACTIVE FILTERS DESCRIPTION due to its "classical" operational amplifier circuit architecture. Unlike "current-feedback" amplifier designs, the OPA675/676 may be used in all op amp applications requiring high speed and precision. The OPA675 and OPA676 are wideband monolithic operational amplifiers with two independent differential inputs. Either input can be selected by an external logic signal. The OPA675 is compatible with ECL logic while the OPA676 is TIL compatible. Both amplifiers are externally compensated and feature very fast input selection speed: ECL = 4ns, TIL = 6ns. This amplifier features fully symmetrical differential inputs Low distortion and crosstalk make these amplifiers suitable for RF and video applications. The OPA675 and OPA676 are available in KG (O°Cto +70°C) and SG (-55°C to+125°C) grades. All grades are packaged in a 16-pin DIP. Input A Output Compensation InputB + TIL: OPA676 Eel: OPA675 internatIOnal Airport industrial Park' • lIaning Address: PO Box 11400 • Tucaon, AZ 85734 • Street Address: 6730 S. Tucson BlVd. • Tucaon, AZ 85706 Tel: (602) 746-1111 • Twx: 9111-952·1111 • Cable: BBRCORP Telex: 66-6491 • FAX: (602) 889-1510 PDS·SMA 2-90 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL ..... At Vee = ±5VDC, R, = 150n, and T, = +25'C unless otherwise noted. JG/SG PARAMETER CONDITIONS INPUT NOISE'" Voltage: fa = 10Hz fo= 100Hz fo= 1kHz 10 = 10kHz fa = 100kHz f. = 10Hz 10 10MHz Current: fa = 10Hz to 1MHz OFFSET VOLTAGE'" Input Offset Voltage Average Drift Supply Rejection BIAS CURRENl''' Input Bias Current MIN TYP KG _~A_X_ JLA 5 · JLA Ve.= OVDC 0.8 INPUT IMPEOANCE''' Differential Common·Mode INPUT VOLTAGE RANGE'" Common-Mode Input Range Common-Mode Rejection · V'N = ±O.5VDC, Vo = ±1.25V OPEN LOOP GAIN, DC'" Open-Loop Voltage Gain FREQUENCY RESPONSE Closed-Loop Bandwidth Crosstalk Harmonie Distortion: 10MHz Full Power Response SlewAate SeWing Time: 1% 0.1% 0.01% ·· 4KI12 10'115 Gain=+2VN Gain=+5VN Gain = +10VN Gain=+50VN Gain = +10VN, f = 100kHz f=lMHz f= 10MHz f= 100MHz G = +10VN, R,= son, Vo= O.5Vp-p Second Harmonic Third Harmonic Vo = 2.5Vp-p, Gain = +10VN Gain=+10VN 75 :1:2.5 100 65 70 85 · -61 -73 25 44 Gain = +10VN 0.625V Output Step 350 9 15 25 ECL: OPA675 TTL: OPA676 4 6 · · V dB " 30 240 dB MHz MHz MHz MHz dBC·' dBC dBC dBC dBC dBC MHz · · V/JLS ns ns ns INPUT SELECTION'. Transition Time 50% in to 50% Out DIGITAL INPUT TTL Logic Levels: V" V," I" I~ ECL Logic Levels: V" V," I" I," RATED OUTiPUT Voltage OUlput logie "LO" Logic"HI" logie "LO', V" =OV Logic "HI", v~ = +2.7V Lagle "LO" Logle"HI" Lagle "LO", V" = -1.6V Logic "HI", V," = -1.0V 1\ = 150n R, = 50n Current Oulpul Oulput Resistance Load Capacilance StabiliJy Short Circuit Current 1MHz, Open Loop, Cc = 5pF Gain=+2VN Continuous to G~d 0 +2.0 -0.05 1 -1.81 -1.15 -SO -SO :1:2.1 +1.25 -0.95 :1:2.6 +l.B -1.1 ±30 5 50 +45 -25 ns ns +0.8 +5 -0.2 20 -1.475 -0.88 -100 -100 · " -1.0 ·· ··· ·· · ·· ·· " JLA V V JLA JLA rnA " " V V mA V V V " " · " n pF rnA rnA " Same specifications as for JG. Burr-Brown Ie Data Book Supplement. Vol. 33b Ie CD 2 0 I1M -II. nllpF nllpF ·· ·· ·· ·· 100 145 185 60 -100 -SO -68 ...,"35 200 nW.JHZ nW.JHZ nW.JHZ nW.JHZ JLVrms pAl.JHZ 30 23 70 OFFSET CURRENT'" Input Offset Current nV/.JHZ 35 Ve.= OVDC :1:250 ±1 UNITS JLV JLVI'C dB :l:2mV ±10 65 MAX ±lmV ±5 ±500 ±3 86 Ve.= OVDC T,,=Tl,IlNtoTMAX TYP ·· ·· · 27 10 3.8 2.6 2.4 7.9 2.7 R,=on ±Vcc = 4.5V to 5.5V MIN 2-91 ~ A. Ii C ~ C Z 0 5 1M A. 0 For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS (cont) ELECTRICAL At v,, z ±5VDC, f\ ~ t500, and TA = +25'C unless otherwise noted. JGISG PARAMETER CONDmONS MIN ±Vcc ±Vcc 4.5 TYP KG MAX POWER SUPPLY Rated Voltage Derated Performance Current, Quiescent 5 10 = OmADC 22 6.5 30 TEMPERATURE RANGE Specilication Ambient TempJG, KG SG Ambient TempJG, KG, SG Operating: 8", 0 -55 -55 +70 +125 +125 125 MIN TYP MAX · · · · · · · UNITS VDC VDC rnA 'C 'C 'C 'CIW • Same specifications as for JG. ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS) At V,, a ±5VDC, R, = 1500, and TA = TUN to TMAX unless otherwise noted. KG JGISG PARAMETER TEMPERATURE RANGE SpeCification OFFSET VOLTAGE Average Drift Supply Rejection CONDITIONS MIN Ambient TempJG, KG SG -55 TYP 0 T,,=TuwtoTMAX ±V" = 4.5V to 5.5V 60 MAX MIN +70 +125 · :b3 85 ±10 V,. = OVDC 29 50 OFFSET CURRENT Input Offset Current V,. = OVDC 0.8 10 INPUT VOLTAGE RANGE Common·Mode Input Range Common-Mode Rejection V.. = ±O.5VDC, V0 = ±1.25V OPEN LOOP GAIN, DC Open-Loop Voltage Gain DIGITAL INPUT TTL logic Levels: V. V~ I" I'H ECl logiC Levels: V" V.. I. I'H RATED OUTPUT Voltage Oulput POWER SUPPLY Current, Quiescent logic "LD" Logic"Hr logic "W, V. = OV logic "HI", V~ = +2.7V logic "W logic "HI" logic "LO", V. =-1.6V Logic "HI", V~ = -1.0V R, =1500 R,=500 10 = OmADC ±1 65 BIAS CURRENT Input Bias Current 65 60 68 63 -lI.08 5 -1.81 :"1.15 -50 -50 ±2.0 +1.25 -lI.8 ±2.5 +1.6 -1.0 25 ·· ·· · 'C 'C ±5 69 p.VI'C dB p.A p.A V dB dB · · · ·· ·· ·· -lI.9 35 UNITS · · · · · ±2.3 80 +0.8 +5 -lI.4 50 -1.475 -lI.88 · MAX · ±2.0 60 0 +2.0 TYP ·· · · · V V rnA p.A V V p.A p.A V V V rnA • Same specifications as for JG. NOTES: (1) Specifications are for both inputs (A and B). (2) dBC = Level referred to carrier-input slgnai. (3) Switching time from application of digital logic signal to input signal selection. 2-92 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) MECHANICAL G Package -l6-Pln Hermetic DIP t['J-j DIM A C 0 F G F_II_ H J K r H- n m r L M N ~ \1r=rlK m INCHES MIN MAX .790 .810 .105 .170 .015 .021 .048 .060 .100 BASIC .070 .030 .008 .012 .120 .240 .300 BASIC 10' .025 .060 NOTE: Leads in true position within 0.01" (0.25mm) R at MMC at seating plane. Pin MILUMETERS MIN MAX 20.07 20.57 2.67 4.32 0.38 0.53 1.22 1.52 2.54 BASIC 0.76 1.78 0.20 0.30 3.05 6.10 7.62 BASIC 10' 0.64 1.52 numbers shown for reference only. Numbers may not be marked on pacJ ~ 6 " 4 2 o 10 Frequency (MHz) 2-94 , o + Frequency (MHz) 8 0.3 + Frequency (MHz) iii' 12 :s Gain 12 9 20 18 ~=-139.5" III 15 -90 o 0.3 BW = 186.6 MHz Cc =6.5pF iii' 18 -45 I\. 10 24 CI> -"", 15 27 'U ~ ~ 25 30 BW = 60.6 MHz 20 100 A., = +10VN CLOSED·LOOP SMALL SIGNAL BANDWIDTH 50 Gain II 10 A., = +SOVN CLOSED-LOOP SMALL SIGNAL BANDWIDTH II 'I Frequency (MHz) Frequency (MHz) Cc.= none 'I / x-70 10 / L 1/ 0.1 40 /21 f~O -60 45 J 31/ c J :I: -70 I-- ~ f31' / / 1/ f -60 I I Gain =+10VN R,= lkQ Vo=2.5Vp-p 100 9 • 8 7 .o -45 -90 135 Cc = 35pF BW = 100.3MHz +=-92.S' II Gain ~ iii' 6 '" 4 -45 3 -90 2 -135 :s 'iii Cl 5 ~ , o -180 1000 0 0.3 1\ 10 100 -180 1000 Frequency (MHz) Burr-Brown Ie Data Book Supplement, Vol. 33b Or, CaU Customer Service at 1-800-548-6132 (USA Only) TYPICAL PERFORMANCE CURVES (cont) lMHz HARMONIC DISTORTION vs POWER OUTPUT -20 -30 -40 5MHz HARMONIC DISTORTION vs POWER OUTPUT -20 I I I - = = Av +10VN (20dB) Ce 6.5pF RL = son Ie = lMHz ~ I -30 I- -40 I- f- Av = +10VN (20dB) Cc = 6.5pF RL = son Ie = 5MHz ,, I g -50 21 -'" 31 -80 O.125Vp-p -90 -20 -15 O.25Vp-p -10 o.svp-p -5 -80 +5 +10 +15 -20 ,,, - Av = +10VN (20dB) Ce = 6.5pF RL =50n Ie = 10MHZ .... -40 -90 -20 ~ .~ ~ o O.2SVp-p -15 -10 o.svp-p -5 0 +5 +10 -70 -20 " 5 I.;" O.25Vp.p -90 +15 z~ o 10'. /31 -15 O.5Vp-p +5 III A. 2VJ>' IV..;' o -10 +10 Power Output (dBm) Power Output (dBm) CHANNEL-TO·CHANNEL CROSSTALK vs FREQUENCY 2.5MHz SMALL-SIGNAL HARMONIC DISTORTION SPECTRUM +15 o -10 E V Gain = +10VN V"" = SOOmVp-p- ' - f\ = son -20 ~ '" -30 !i;-40 ~ 0.-50 ! i'" -105 -80 -70 10 100 1000 Frequency (MHz) i -80 -90 2 4 6 8 10 12 Frequency (MHz) Burr-Brown Ie Data Book Supplement, Vol. 33b ..--.... ~ A "f/ ./ IIII A. ~ O.12SVp:p 2VJ>' IV..;' ~ -120 0.3 +15 ,. , .... "" , """- " -66.3dB -75 -90 2VJ>' +10 It 21 ~ -60 ~ -30 <) I- :s ~ llci~J~HZ -15 ~ +5 Av = +10VN (2OdB) Cc = 6.5pF RL =50n Ie = 20MHZ -80 O.125Vp:p "" lV..p -10 g -50 31 .JI' rl- -80 -60 -15 L L -' -30 ;JI7 . 21 -70 -20 I " -45 '""" O.5~p -90 20MHz HARMONIC DISTORTION vs POWER OUTPUT ~ -60 6 :s '" 31 10MHz HARMONIC DISTORTION vs POWER OUTPUT i.~ ". I'Z Power Output (dBm) 50 o -- 21 .". ." Power Oulput (dBm) -40 O.25Vp-p O.125Vp-p 2VJ>' -20 -30 lil is -70 ./ IV..p 0 " ~ -60 ..., .. II :s 2-95 o For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (cont) OPEN ·LooP GAIN. CMR AND PSR vs TEMPERATURE NOMINAL FREQUENCY COMPENSATION vs NOISE GAIN 35 ,, 110 ia: ~ ~ ...... 2 3 4 5 6 810 20 Noise Gain (VN) i"'" 70 -- I I P~ Ace I I I 60 o 1 1 C~R I- 90 ~ 80 ~ - 100 30 50 70 100 THEORY OF OPERATION An OPA675 simplified circuit is shown in Figure 1. It is a "classical" high-speed op-amp architecture with one important exception - the amplifier has two ECL logic selectable differential input stages. An appropriate differential ECL logic signal on A and A (labeled B Select) will tum on either Q5 or Q6, steering operating (tail) current to either differential input pair QI and Q2 or Q3 and Q4. The input pair receiving the tail current operates as a conventional op-amp input stage while the de-selected input pair receiving no tail current appears as an open circuit. The de-selected inputs have only a few pF parasitic capacitance and in the off condition exhibit only a very low leakage (bias) current of about lOOpA. Two feedback networks can be connected to each input separately allowing a wide range of circuit applications. The feedback network connected to the se- 50 -50 -25 o +25 +50 +75 +100 +125 Temperature (·C) lected input operates in a normal op amp fashion while the feedback network connected to the de-selected input is totally inactive, appearing only as an additional load to the amplifier's output stage. The switched-input op amp (SWOP AMP) circuit of the OPA676 is basically the same as the OPA675 but a TTL compatible level shifter (Figure 2) has been added to its input selection logic circuit. Standard TTL (OPA676) and ECL (OPA675) logic levels may be applied. to each input selection circuit but only 350mV is typically required to switch between inputs. This logic input sensitivity allows simpler high-speed logic driver circuitry and it minimizes digital noise coupling into adjacent wide band analog circuitry and allows single ended ECL inputs to be used with VDD applied to the other input. Out FIGURE 1. OPA675 Simplified Circuit Diagram. 2-96 Burr-Brown Ie Data Book Supplement. Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) The OPA675 and OPA676 are designed to be frequency compensated by a single capacitor connected from pin 5 to ground. Recommended compensation is shown in Typical Perfonnance Curves. A small variable capacitor may be trimmed for best bandwidth. settling time. and gain peaking. This amplifier is designed for optimum perfonnance in gains of 5VN to 20 VN but it can also be used over a far wider range of gains with excellent results. Closed-loop gain/phase (Bode) plots are shown in the Typical Perfonnance Curves. OFFSET TRIM Input offset voltage is low enough for many video applications. If desired. offset voltage can be trimmed with a lill potentiometer connected to +Vcc' Trimming offset voltage in this manner will effect both input A and input B; independent control of input offset will require that trim adjust current be summed into one or both inputs. This technique is shown in a few applications circuits on the pages to follow. +Vcc ECLO_-t-_-, Out TTL In ECL Threshold -= -= FIGURE 2. Internal OPA6761TL Logic Level Shifter. Iw --... I I. a- S ~ z o i III a- o FIGURE 3. 1% Settling Time. FIGURE 4. OPA675/676 Settling Time Test Circuit. FIGURE 5. OPA676 Input Selection Time. Input A to B. FIGURE 6. OPA676 Input Selection Time. InputB toA. Burr-Brown Ie Data Book Supplement, Vol. 33b 2-97 For Immediate Assistance, Contact Your Local Salesperson APPLICATION TIPS Wideband amplifier circuits require good layout techniques to be successful. The use of short, direct signal paths and heavy (20z copper recommended) ground planes are absolutely necessary to achieve the performance level inherent in the OPA6751676. Oscillation, ringing, poor bandwith and settling, gain peaking, and instability are typical problems that plague all high-speed amplifiers when they are used in poor layouts. The OPA675 and OPA676 are no different in this respect - any amplifier with a gain bandwith product of a few GHz requires some care be taken in its application. 11<0 Tektronix SG503 8 ToScope RL 100n Points to remember: I. Use a heavy copper ground plane on the component side ·of your PC board. This provides a low inductance ground and it also conducts heat from active circuit package pins into ambient air by convection. 2. Bypass power supply pins directly at the active device. The use of tantalum capacitors (1 to IO(lF/IOV) with very short leads is highly recommended. Supply pins should not be left unbypassed. FIGURE 7. OPA676 Input Selection Transition Time Test Circuit. FIGURE 8. OPA675 Input Selection Time. Input A to B. FIGURE 9. OPA675 Input Selection Time. Input B to A. 11<0 10MHz 'VJ---..JV'N'--- ---"-j 50mVp·p 8 JL 3MHz ECl To Scope MC10105 ~ 2 11<0 300n 300n -5.2V FIGURE 10. OPA675 Input Selection Transition Time Test Circuit. 2-98 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) 4990 OffselTrim -5V To 500 Oscilloscope or Spectrum +5V 10kn 49.90 =49.90 Analyzer 5kn 49.90 100 TTL ~ 4990 Input: JU +2.BV +O.4V TTL rise and fall lime = IOns 12. Terminate transmission line loads. Unterminated lines, such as coaxial cable, can appear to the amplifier to be a capacitive or inductive load. By terminating a transmission line with its characteristic impedance, the amplifier's load then appears as a purely resistive impedance. 13. For clean, fast input selection the logic input pins should be terminated with appropriate resistors. Resistors should be connected from input selection pins to ground plane with short leads. Failure to terminate long lines will result in ringing and poor high frequency switching. 14. Plug-in prototype boards and wire-wrap boards will not be satisfactory. A clean layout using RF techniques is required; there is no shortcut. Frequency = 1MHz FIGURE 11. OPA676 Carrier Feedthrough and Switching Transient Test Circuit. 3. Signal paths should be short and direct. Feedback resistors, compensation capacitors, termination resistors, etc should have lead lengths no longer than 1/4 inch (6cm). 4. Surface mount components (chip resistors, capacitors, etc) have low inductance and are therefore recommended. Parasitic inductance and capacitance should be avoided if best performance is to be achieved. 5. Resistors used in feedback networks should have values of a few hundred ohms for best performance. Shunt capacitance problems limit the acceptable range to about lill or on the high resistance end and to a value that is within the amplifier's output drive limits on the low end. Metal film and carbon compensation resistors will be satisfactory. 6. Wirewound resistors (even "non-inductive" types) are absolutely unacceptable in high frequency circuits. 7. Avoid overloading the output. Remember that output current must be provided by the amplifier to drive its own feedback network as well as to drive its "load." Lowest distortion is achieved with high impedance loads. 8. 9. PC board traces for signal and power lines should be wide to reduce impedance or inductance. Don't forget that these amplifiers use ±5V supplies. Although they will operate perfectly well with +5V and -5.2V, the use of ±15V supplies will result in destruction. 10. Standard commercial test equipment has not been designed to test devices in the OPA675/676 speed range. Benchtop op-amp testers and ATE systems will require a special test head to successfully test these amplifiers. II. High-speed amplifiers can drive only a limited amount of capacitance. If the load exceeds 10 to 20pF consider using a fast buffer or a small resistor to isolate the capacitance from the amplifier's output. Capacitive loads will cause loop instability if not compensated for. Burr-Brown Ie Data Book Supplement, Vol. 33b FIGURE 12. OPA676 Switching Transient. Top Trace: TIL Input (2V/cm). Bottom Trace: Amplifier Output (2mV/cm). Input B Offset Voltage has been Trimmed to Match Input A Offset Voltage. 1MHZ TTL CARRIER FEEOTHROUGH vs FREQUENCY O~-+--+-~--~--r--+--+-~--~~ E -10~-+--+-~--~--r--+--+-~--~~ '"E ~O~-+--+-~---r--r--+--+-~---r~ I::~-+--+-~--~--~-+--+-~--~~ .c -So .. -60 ~ 0 -70 -60 0 2 4 Frequency (MHz) B 10 FIGURE 13. Carrier Feedthrough from IMHz TTL Logic. Offset Trimmed for Maximum Carrier Rejection 2-99 2 For Immediate Assistance, Contact Your Local Salesperson 31SO 20n -= 301n +5V 500 Input 49.90 TIL Input 500 ~ 1 Oulput 49.90 ~ + 2.2~F I 20n -= -= 12pF 10V' -5V Output 30m -= •~antalu; 20n 301n Bandwidth ~ FIGURE 14. OPA676 Used As A Conventional Op-Amp: A IOdB Gain Wideband Video Amplifier with 50n Input/Output Impedance. ~200MHz FIGURE 15. Very Fast Programmable Gain Amplifier with Voltage Gains of + I VNand +16VN (OdB and 24dB). 3 I L Differential Input 6 2 200n 1 200n lOOn 2 lkll loon TIL 3 lkll -= Out lkll -= 3 I L Differential Input -= -= 100n 2 2000 2 loon 1kll 200n 2 6 3 FIGURE 16. High Input Impedance Differential Input Multiplexer with Gain of 30VN (30dB). 2-100 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) 400 2000 -5V 51<0 +5V 4.991<0 9090 90.90 TIL In oIn __ 500 ---------+----~ 500 RForlF Out 49.90~ 100 -= -= = FIGURE 17. Synchronous ModulatorlDemodulator with Carrier Balance Trim (Gain = ±5VN). 1000 1000 = 9090 12IU 1000 = FIGURE 20. Receiver Noise Blanker: A Wideband Gated Video Amplifier. +5V Offset Trim ADC603 51.10 45 -= Signal Input 383 0 Offset Trim Analog Common ·5V 590 = Input FIGURE IS. Programmable-Gain +2VN (6dB) or +SVN (lSdB) Buffer Amplifier for FIoating-Point Conversion. In 1 46 • Tantalum Gain Select (TIL) 1000 >=+--=45'--1 Signal - 4120 Analog Common -= -= Input Select (TIL) • Tantalum FIGURE 21. Multiplexed Input + l6VN Gain (24dB) Buffer Amplifier. 11<0 1000 +o---~w-.., 11<0 Output = 11<0 +0--"",,"1'-....1 In2 1000 1000 -=- -= lkO FIGURE 19. Differential Input Multiplexer with Gain of IOVN (2OdB). Burr-Brown Ie Data Book Supplement, Vol. 33b S 383 0 +5V ADC603 46 -ii:~ 2-101 o = 5 IU A. o For Immediate Assistance, Contact Your Local Salesperson (Carrier Suppression) Offset Trim +5V 51<0 -5V 455kHz Carrier Input 4.991<0 90.2n 909n 11<0 11<0 Ion OlffECL 8 1.51<0 49.9n 50n .--.~vvv-~ RF .". Out 455kHz BP Filter" 11<0 11<0 loon 1.51<0 -= -= 909n • Murata Erie CFS455C -= FIGURE 22. Single Sideband Supressed Carrier Generator. Out c. Voltage Gain (VN) R, (n) (n) (PF) +2 +5 +10 200 49.9 22.1 200 200 200 35 16 6.5 Voltage Gain (VN) R, (n) R, (n) (pF) +2 200 75 28 20 10 200 226 196 301 309 35 22 10 3 0 R" FIGURE 23. Programmable-Gain Amplifier. In 1 OUt +4 In 2 +8 +16 +32 c. FIGURE 24. Two-Input Multiplexer (with gain). 2-102 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) In Voltage Gain (VN) ±2 ±5 ±10 At A, A, A, Co (0) (0) (0) (0) (pF) 100 40 20 200 200 200 200 50 25 200 200 225 35 16 6.5 FIGURE 25. Synchronous ModulatorlDemodulator (with gain). 12 w -~ I&. ~ o = 5 w A. o Burr-Brown Ie Data Book Supplement, Vol. 33b 2-103 For Immediate Assistance, Contact Your Local Salesperson OPA1013 Precision, Single-Supply DUAL OPERATIONAL AMPLIFIER FEATURES APPLICATIONS • • • • • • • • • • • • • SINGLE POWER SUPPLY OPERATION INPUT VOLTAGE RANGE TO GROUND OUTPUT SWINGS NEAR GROUND LOW QUIESCENT CURRENT: SOOJ.IA max LOW Vos: 150l1V max LOW DRIFT: 211VI"C max LOW los: O.SnA max LOW NOISE: 0.55I1VP-P, 0.1 Hz to 10Hz PRECISION INSTRUMENTATION BATTERY-POWERED EQUIPMENT BRIDGE AMPUFIERS 4-20mA CURRENT TRANSMITTERS VOLTAGE COMPARATOR DESCRIPTION 'lbe OPAIOl3 dual operational amplifier provides precision performance in single power supply and low power applications. It is laser trimmed for low offset voltage and drift. greatly reducing the large errors common with LM324-type op amps. Input offset current is also trimmed to reduce errors in high impedance applications. The OPAIOl3 is characterized for operation at both +5V (single supply) and ±15V power supplies. When Simplified Clrcuft (Hall of Dual) operated from a single supply, the input commonmode range includes ground and the output can swing to within 15mV of ground. Completely independent biasing networks eliminate interaction between the two amplifi~ven when one is used as a comparator. The OPAIOl3 is available in 8-pin plastic DIP and metal TO-99 packages, specified for the O°C to 700C and -55°C to 125°C temperature ranges. ~~----~~----~----------~--------~v+ 8 2nd Gain Stage 4000 Out 1.7 tIIIrnIUanIl AIrport Indllllrlli Parte • IIaIIng Addr1a: PO 80111400 • Tucson, AZ 85734 • SIIIIt AddmI: &730 S. 'IIICIan IIIvtI. • Tucson, AZ 857D& T.t (&OZ) 746-1111 • TwI:81H5Z-1111 • ClbIl:BBRCORP • T.llx:CI&H481 • FAX:(60Z) ....1510 • mntdilllPnlductInlO:(8IIO)54HI32 PDS-IOS9A 2-104 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL V•• :l:15V, Ve•• OV, T•• +25"C unless o1herwlse noled. PARAMETER C') CONDmON UNITS Input OIIset Voltage OPA1013CN8 Time StabiliJy Input Offset Current Input Bias Current Voltage Noise, BW. 0.1 to 10Hz Noise DenslJy, f = 10Hz '.lkHz Current Noise CenslJy, f. 10Hz Input Resistance: Differential Input Resistance: Common·Mode Open·Loop Voltage Gain 100 Va· :l:l0V, f\. 21<0 Va· :l:l0V, f\ = 60011 Common·Mode Input Range Common-Mode Refection Power Supply Refection Channel SeparaOon Voltage Output Slew Rale OUlescent Current (por amplifier) V, = +5V/oV, Ve• Veu. +t3.5 to -15V V. = :1:2 to :l:18V Va • :l:l0V, f\ • 21<0 f\ -21<0 1.5 0.8 +13.5 -15 100 103 123 :1:13 0.2 0.4 :1:0.045 8 0.55 28 25 0.12 400 5 3.1 2.1 +13.8 -15.3 117 120 140 :1:14 0.35 :1:0.35 :1:0.8 20 70 1.2 0.5 +13.5 -15 97 100 120 :1:12.5 0.2 :1:0.5 :1:50 :1:200 0.5 :1:0.08 7 0.55 28 25 0.12 300 4 2.9 1.9 +13.8 -15.3 114 117 137 :1:14 0.35 :1:0.35 :1:1.5 30 IlV IlV IlVlMo nA nA IlVp-p nVl.JHi nVl.JHi OPA1013A111AC CONDmON MIN Input onset Voltage MAX ±8D :1:250 Va. 5mV to4V RL Ii:I Mil GO VlIlV VlIlV V V dB dB dB V Vf\Is :1:0.55 mA MIN 1YP MAX UNItS :l:9D ±45D ±25D :1:950 :1:2.0 5D IlV IlV nA nA VlIlV +3.5 D Voltage Output Low Low Low :1:1.3 35 :1:0.3 10 D.l 5000 Common-Mode Input Range High High OUlescent Current (por amplifier) :1:0.2 9 0.1 No Load f\ • 60011 to Ground 1.... =lmA No Load R, = 6000 to Ground 4 3.4 +3.8 -0.3 15 5 200 4.4 4 0.31 +3.5 0 25 10 35D 4 3.4 0.45 +3.8 -0.3 15 5 200 4.4 4 D.33 D.5 V V mV mV mV V V mA UNItS 25 10 35D T. = -SS"C to +125"C, V•• :l:15V, Ve•• DV unless otherwise noled. OPA1013AM PARAMETER CONDmON MIN Input OIIset Voltage Va =- +5IOV, Vo = +1.4V T" .. 100°C V... O.IV, T. = 125"C V.. = OV, T. = 125"C Input Offset Voltage Crift Input OIIset Current V. = +5IOV, Va. +1.4V Input Bias Current Open-Loop Voltage Gain Common·Mode Refection Power Supply Refection Voltage Oulput Va Low Va High Oulescent Current (per amplifier) = = V. +5JOV, Va +1.4V Va = :l:l0V, R, = 2kQ V.. = +13 to -14.9V V•• :I:2 to:l:18V R, = 21<0 V•• +5IOV, R,. 6000 V•• +5IOV, R, _ 8000 0.5 97 100 :1:12 3.2 V. = +5IOV, Va. +1.4V Burr-Brown Ie Data Book Supplement, Vol. 33b o :!III I I. ~ ~ OPA1013111C1DNB TYP OPA1D13DN8 Input OIIset Current Input Bias Current Open·Loop Voltage Galn o pM'Hi =OV, Va =+1.4V, T•• +2S"C unless o1herwlse noled. PARAMETER .... 2 OPA101311 TYP MAX TYP MAX ±80 :1:300 :l:llD ±55D IlV :1:70 :1:100 :1:200 0.4 :1:0.3 :1:0.8 7 11 2.0 114 117 :1:13.8 8 3.8 :1:0.38 0.34 :i45O :1:75 :1:150 :1:300 0.5 :1:0.4 :1:0.9 9 15 2.0 113 118 :1:13.8 8 3.8 :1:0.38 0.34 :1:750 :1:750 :1:1500 2.5 :1:5.0 :l:1D 45 120 "V IlV IlV IlVfOC nA nA nA nA V/t1V dB dB V mV V mA mA IIIN ±45D :1:900 2.0 :1:2.5 ±8 30 80 0.25 94 97 :1:11.5 15 3.1 :1:0.8 D.55 18 :1:0.7 0.65 2-105 o = 5 III a. o For Immediate Assistance, Contact Your Local Salesperson· SPECIFICATIONS T•• OOC \0 +700c, v, • :t15V, V.,.. fN unless oIherwlse noted. OPA1DI3AC PARAMETER CONDITION ..N Input Offset Voltage OPAlO13DN8 V, = +5IOV, Vo =+1.4V OPA1013DN8 OPA11!13C1DN8 TYP MAX :t55 :12010 0.3 2 :to.2 :to.4 7 10 2.5 118 119 :t13.9 6 3.9 :to.36 0.32 :tl.5 :t3.5 25 55 OPA1013DN8 Input Offset CUrrent V•• +5IOV, Vo. +1.4V Inpul Bias Current Open-Loop Vollage GaIn Common·Mode Rejection Powar Supply Rejecllon Vollage 0u1pUl Vo Low Vo High Qulascenl Current (per ampIffier) V•• +5IOV, Vo. +1.4V Vo • :tl0V, f\ • 2kD Veo =+13 \0 -15V V, • :12 \0 :t18V f\ -2kD V, • +5IOV, R, • 8000 V, • +5IOV, f\ • 6000 1 98 101 :t12.5 3.3 V, • +5IOV, Vo - +1.4V TYP MAX UNn8 :180 :MOD :tlDDO :t570 :t1200 2.5 5 :12.8 :t8 38 p.V p.V ' IlV p.V p.vrc IlVrc nA nA nA nA V/IlV dB dB V mV V rnA rnA :I23D :tll0 :1280 0.4 0.7 :to.3 :to.S 9 13 2.2 113 116 :t13.9 8 3.9 :to.37 0.34 :t35O :t75 Input Offset Voltage Drift MIN 0.7 94 97 :t12.0 13 3.2 :to.55 0.50 90 13 :to.8 0.55 MECHANICAL H PacIcage - Metal TO-99 -ADIM II B C D E F G H J K L M N INCHES MIN MAX .335 .310 .305 .335 .165 .185 .016 .021 .010 .040 .010 .040 .200 BASIC .028 .028 .500 .034 .045 .110 .160 1oILUMEI£RS liN MAX 8.51 9.40 7.75 8.51 4.19 4.10 0.41 0.53 0.25 I.CI! 0.25 1.02 5.06 BASIC 0.71 0.86 0.74 1.14 12.7 2.79 4.06 (0.25mm) Rat MMC at seating plane. PIn numbenl shown lor retarence only. Numbo", may not be marIced on pacIcage. - 45· BASIC 45· BASIC .095 2.41 .IDS NOTE: Leads In true position wIIhIn 0.01" 2.67 N8 Paclalga - &-PIn Plastic DIP DIM 1\. INC lIES MIN MAX .200 .050 ~020 B. .065 C D'" E ~0'2 .. E. e. .400 .300 .325 .240 .260 .1001 IASIC .3001 IASIC .125 2-106 .150 liN IMAX 3.94 0.51 ..0.35. 1.14 .0.2It 9.40 10.16 7.62 8.26 8.10 8.60 2.54 ASIC 7.62 IASIC 3.1R 3.81 INCHES MlLUMETERS loIN MAX MIN MAX IP 0 .030 0.00 0.76 15· 15· C1 OD OD P .015 .DSO 0.35 1.270 Ilt .040 .075 1.02 1.91 SCI' .015 .DSO 0.35 1.27 (1)Na1 JEDECStd. (2) el and e. 8IlIJIIes In zone L, when una InsIaIIed. NOTE: Leads In true posl1lon whhln 0.01" (O.25mm) R at MMC at seating plane. DIM Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) CONNECTION DIAGRAMS N8 - PlasUe Package - Top View H- TO-99 Metal - Top View ...'o" ... 2 o V- IIII ORDERING INFORMATION MODEL PACKAGE TEMPERATURE RANGE OPA1013CN8 OPA1013DN8 Plastic DIP Plastic DIP O'C 10 +70'C O'C to +70'C OPA1013ACH OPA1013CH OPA1013AMH OPA1013MH TO-99 TO-99 TO-99 TO·99 Metal Metal Metal Metal .-.. i S O'C to +70'C . O'C to +70'C -QS'C to + 12S'C -QS'C to + 12S'C o = 5 Ie ABSOLUTE MAXIMUM RATINGS Power Supply Voltage .......................................................................±22V Differential Input Voltage ...................................................................±30V Input Voltage ...................................................................... V+ to (V-) -QV Output Short Circuit (T. = 2S'C) ............................................. Continuous Operating Temperature: OPA1013AM. OPA1013M ............................................... -QS to +12S'C OPA1013AC. OPA1013C. OPA1013D ................................. 0 to +70'C Storage Temperature ......................................................... -43S to +IS0'C Lead Temperature (solderlng. lOs) ............................................... +300'C Burr-Brown Ie Data Book Supplement. Vol_ 33b o 2-107 For Immediate Assistance, Contact Your Local Salesperson TY~CALPERFORMANCECURVES = +25°C unless otherwise noted. TA 10 Vs =1±15V_ 200 :> a ~ 100 " f r--- r-.... 0 J!l -100 0 -200 -- 6 Representative Devices -50 o -25 25 75 50 r-. -Vs .±15V,-55OCI01257~ - f Rs I I 1il ~ 1s; I I'\. ./ -" 0.1 125 """" V ~~ V0 = ±15V, 25°0.: I 1k 3k 10k 30k 100k 300k 1M 3M Temperature ("C) Balanced Source Resistor (llj OFFSET VOLTAGE vs TIME COMMON-MODE REJECTION RATIO vsFREQUENCY ~ ex: c 0 &l Metal T0-99 H Package ~ Piastlc DIP Nj Package :::;; "8 100 ~ ...... --- 80 ~VoJ'5V Vs=5V10~ 60 40 .!, 0 E E 20 V 0 0 ~ ~ ., 0 o 3 2 10M 120 i'i'i ~ A ~ . :: V s .5V10V, 25°C 0.01 100 I Vo = ±15V o $ '•. w~,-wc.,~ Q) ~ 1il »- OFFSET VOLTAGE vs BALANCED SOURCE RESISTANCE OFFSET VOLTAGE vs TEMPERATURE 5 4 10 lk 100 10k Time After Power On (Minutes) Frequency (Hz) POWER SUPPLY REJECTION RATIO vs FREQUENCY 0.1 Hz TO 10Hz NOISE ~ lOOk 1M \ 120 ~ i'i'i ~ 100 ~ ex: c ~ Q) '" ex: i " Ii; , ~ ~ 80 POSitiV~ 60 Supply ±2~ to ±~BV ,ilil JJ. .~ ~ 40 II'rl v' ,H ..~I.lL1 I~'''' rr,II' ,tlol ILAM JiLt r.lU .. LI TI I'llI' IJI ~IT IJ'I'1 If'r , ~ Ul ~ - Vol = Negative Supply 20 Q. o 0.1 10 100 1k Frequency (Hz) 2-108 10k lOOk 1M o 2 4 6 8 10 Time(s) Burr-Brown Ie Data BookSupplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES TA = (CONT) +25°C unless otherwise noted. ... o CW) 200 Vs - ±2V to ±1BV l¥l¥ ~ ~ r-..... ~ Current Noise 100 ::J "5 jj "5 ·s zZ CD " i~ ;g8 2 1BO o 160 ~~ 300 ff ... 10Hz VOLTAGE NOISE DISTRIBUTION NOISE DENSITY vs FREQUENCY 1000 140 120 100 E BO Z 60 :I 30 40 Voltage Noise 20 0 10 10 1 100 20 10 1k 30 40 60 50 Voltage Noise Density (nVNHz) Frequency (Hz) -ii:~ INPUT BIAS CURRENT SUPPLY CURRENT vs TEMPERATURE 2: 460 Vs =±15V 420 i3. ~ 340 {} i 300 ell 260 o -25 25 .J......--""" Vs =5V10V.", ----- ,.- ~ -50 ...- -- -- 3BO it i vs COMMON-MODE VOLTAGE V ....... ~ 10 j 5 ~ 0 i I \ \ -10 0 -5 Temperature ('C) « -ll.B Vs =5VIOV S. ~ -0.6 8 ~ J. -ll.4 - - - ~ c:-I--- ....... - .v:- -25 ~. ~ s. I-- :I {} ~ ....... I VCM =OV « E CD -20 I: gj iii Vs = ±15V ~ -15 Vs Vs = 5V10V -10 '\.. S -5 -50 ::::=- ·±2·r, I...:::::::;; ~ ~±15V l- I 0 -25 -25 -20 INPUT BIAS CURRENT vs TEMPERATURE -ll.2 o -15 ~o VCM = OV E A. Input Bias Current (nA) INPUT OFFSET CURRENT vs TEMPERATURE -1 IU ~I'-. {} 125 100 o Vs =5V10V -5 ~ o -15 75 \\ o = i Vs =±15V .: -10 50 I 15 Ii; « i' o 25 50 75 100 125 Temperature ('C) Burr-Brown Ie Data Book Supplement, Vol.33b -50 -25 IIU o 25 50 75 100 125 Temperature ('C) 2-109 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C unless otherwise noted. OUTPUT SATURATION AND SINK CURRENT vs TEMPERATURE 10 F +V-SVIo30V I-- D> c 1! 40 V=OV ISINK = 10mA ~ C ~ i"= " II> 0 D> ~ is'NK = SmA I - C 0 is'NK = lmA 0.1 o -2S 2S -20 8 g' -30 --=== :i! .5-40 U) -50 7S SO "5 s- Io'NK=O -50 25'C l~'C I I -10 .J: 100 125'C ;.-- 2S'C f- -5S'C ;.-- o 125 2 VOLTAGE GAIN vs LOAD RESISTANCE VOLTAGE GAIN vs FREQUENCY 140 Vo =+10VwithV.=±lSV Vo =20mV to 3.SV with V. /I (2) .L. i.-" '" f > I' Vs = ±lSV '~ '~ eo V. = sv/OV 40 ~ 20 (5) 0 (~l III If)" I lOOk 100 .5 C!l C L =100pF_ .... ~ iD :E- 80 tP---/ /" (41 r....... 100 ;;- V I-- 120 Sv/ V (11 3 Time (Minutes) Temperature ('C) 10M Vs =±lSV -55'C U) \;'NK = 10~A 0.01 - OUTPUT SHORT CIRCUIT CURRENT vs TIME 10 1; ~ is'NK = 100~A II> 30 20 " .t: " ~ 0 " ~ ~ SO lk ~ ~ -20 0.01 10k ~ 10 0.1 Load Resistance to Ground (n) 100 lk 10k lOOk F\ 1M 10M Fnequency (Hz) NOTES: (1) T. = -5S·C. V, = ±lSV. (2) T. = +2S·C. V, = ±lSV. (3) T. = 12S·C. V. =±lSV. (4}T. = +2S'C. V. = Sv/OV. (S) T. = -SS'C. V. = Sv/OV. (6) T. = 12S'C. V, = Sv/OV. GAIN AND PHASE vs FREQUENCY CHANNEL SEPARATION vs FREQUENCY 80 VOM =OV 20 iD :E- c 'n; C!l 10 ,""" '"""'- " Gain i" 0 I"'" V. = ~v/OV > fL Vs=±lSV r-. r-. ""'- f'~\.. laO I.V s =±1 SV 180 V. = Sv/OV "'-t-- 0.1 \ m ~ e." :c "" II> "gj .J: 200 11. 1\ 220 240 10 Frequency (MHz) 2-110 140 Phase ,--::::::I=::::::::-r--,,:;--:;;::;---, 100 120 ::--..... ~ -10 = 10OpF 160 ~14O i 120 ~ 100 1---+-- ~ 1---+----+- Umtted by i!l ~ 80 pln-Io·pln 60 L__ _-l..._ _~_...;ca=paco=·tan=c&:..__L_....;:"__' 10 100 lk 10k lOOk 1M Frequency (Hz) Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) TYPICAL PERFORMANCE CURVES (CONT) ...o ell) LARGE SIGNAL TRANSIENT RESPONSE Vs. ±15V, G. +1 SMALL SIGNAL TRANSIENT RESPONSE = ±15V, G D +1 v. ... 2 o IIII ..--.... A. S LARGE SIGNAL TRANSIENT RESPONSE Vs -SVlOV,G- +1, RL .4.7kVI05V SMALL SIGNAL TRANSIENT RESPONSE v•• 5V10V, G _ +1, RL. 60011 10 Ground io i III Input. OV to 4V Pulse Input = OV to 100mV Pulse A. o LARGE SIGNAL TRANSIENT RESPONSE V•• 5V/oV, G - +1, No Load COMPARATOR RISE RESPONSE TIME· IOmV, 5mV, 2mV Overdrives Output (V) Input(mV) Input_ OV 10 4V Pulse Burr-Brown Ie Data Book Supplement, Vol. 33b V.=5V/oV. 2-111 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) COMPARATOR FALL RESPONSE TIME 10mV. 5mV. 2mV Overdrives OulputM Input(mV) INPUT PROTECTION APPLICATIONS INFORMATION The circuitry of the OPAl013 is protected against overload for input voltages ranging from the positive supply voltage to 5V below the negative supply voltage (below ground in single supply operation). No external protection circuitry is required. as it is with other common single-supply op amps. The OPAl013 is unity-gain stable. making it easy to use and free from oscillations in the widest range of circuitry. Follow good design practice by bypassing the power supplies close to the op amp pins. In most cases 0.1 J1F ceramic capacitors are adequate; Furthermore. the OPAl013 is free from phase-reversal problems common with other single-supply op amps. When the inputs are driven below ground (or below the negative power supply). the output polarity remains correct. SINGLE POWER SUPPLY OPERATION The OPA 1013 is specified for operation from a single power· supply. This means that linear operation continues with the input terminals at (or even somewhat below) ground potential. When used in a non-inverting amplifier. OV input must produce OV output. In practice. the output swing is limited to approximately l5mV above ground with no load. Output swing near ground can be optimized when the output load is connected to ground. If the output must sink current. the ability to swing near ground will be diminished. The output swings to within approximately 200mV of ground when sinking lmA. COMPARATOR OPERAnON The OPAl013 functions well as a comparator. where high speed is not required. Sometimes. in fact. the low offset and docile characteristics of the OPAl013 may simplify the design of comparator circuitry. The two op amps in the OPAl013 use completely independent bias circuitry to avoid interaction when the inputs are over-driven. Driving one op amp into saturation will not affect the characteristics of the other amplifier. The outputs of the OPAl013 can drive one TIL load. Quiescent current remains stable when the inputs are overdriven. J O-lmAln ~ >""'t"---,NV'---t I~ ~ O-ImAOUl N channel enhancemem MOSFET Supel18x. SIIIconIx. Motorola. etc. or 2x2N2222 5000 To Ground or-Vs FIGURE 1. Precision Current Mirror. 2-112 Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1-800-548-6132 (USA Only) ";....o V, a; o Input common-mode range extends to approximately l501nVabove V- supply -limited V. by OPA1013 output swlng_ IUI FIGURE 2. Instrumentation Amplifier. -I I. ~ A. S >-II-'-<~ V, Input o = 5 Vo Vo .Va -V, V._n::.~=t::;=t==.J V- UI A. o Input common-mode range extends to approximately 200mV below V- supply. FIGURE 3. Instrumentation Amplifier. V+ VI _______ (+100lnV) ~ ___ ~ _______ HOOmV) I I I I I I -LJ-- Output lkn V, NOTE: V, must sink 1DOpA. FIGURE 4. Window Comparator. Burr-Brown Ie Data Book Supplement. Vol. 33b 2-113 For Immediate Assistance, Contact Your Local Salesperson BURR-BROWN 8 OPA2107 IE:lE:lI Precision Dual Oifet ® OPERATIONAL AMPLIFIER FEATURES APPLICATIONS • VERY LOW NOISE: 8nVl{fii at 10kHz • DATA ACQUISmON • DAC OUTPUT AMPLIFIER • LOW Vas: 500JlV max • LOW DRIFT: SJlV/oC max, • LOW 18: SpA max • FAST SETTI.ING nME: 2J.lS to • OPTOELECTRONICS • HIGH-IMPEDANCE SENSOR AMPS • HIGH-PERFORMANCE AUDIO CIRCUITRY 0.01% • MEDICAL EQUIPMENT, CT SCANNERS • UNITY-GAIN STABLE DESCRIPTION r------1~--O+Vs The OPA2107 dual operational amplifier provides precision D/~ perfonnance with the cost and space savings of a dual op amp. It is useful in a wide range of precision and low-noise analog circuitry and can be ' used to upgrade the perfonnance of designs currently using BIFE~type amplifiers. (8) The OPA2107 is fabricated on a proprietary dielectrically isolated (Dlfet) process. This holds input bias currents to very low levels without sacrificing other important parameters. such as input offset voltage. drift and noise. Laser-trimmed input circuitry yields excellent DC perfonnance. Superior dynamic perfonnance is achieved, yet quiescent current is held to under 2.5mA per amplifier. The OPA2107 is unitygain stable. Output (1,7) ' - - - " - - - -........- - - 0 -Vs (4) The OPA2107 is available in plastic DIP. metal TO99. and sOle packages. Industrial and Military temperature range versions are available. 01"". BUIT-Brown Corp. BIFET" National Scmicmcluctor InlamllIonaI Airport Induslrlal PIrIe • IlaIDng Addna: PO Box 11400 • TucIan, AZ 85734 • SIrHI Add....: &7311 S. Tucsan Blvd. • TucIan, AZ 857U6 T":(&02)746-1111 .....:81H5z.1111 • ClbIe:BBRCORP • TeIn:CJ6&.6481 • FAX:(&02)1IIJ9.1510 • 1mmIdIatllI'radul:tInlo:(8OO)54Nl32, PDS-863A 2-114 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) SPECIFICATIONS TA ... +25°0, Va'" ±15V unless otherwise noted. LSII, IoP,AU PARAMETER OFFSET VOLTAGE'" Input Offset Voltage Over specilled Temperature sMGrade Average D~n Over Specified Temperature Power Supply Rejection INPUT BIAS CURRENl''' Input Bias Current Over Specified Temperature sMGrade Input Offset Current Over Specified Temperature SMGrade INPUT NOISE Voltage: I a 10Hz 100Hz 1= 1kHz I. 10kHz BW=O.1 to 10Hz BW = 10 to 10kHz Current: 1= 0.1 Hz thru 20kHz BW =O.IHz to 10Hz ,= CONDmON MIN Va.- OV V.=±10to±18V 80 OPEN-LOOP GAIN Open-Loop Voltage Gain Over Specified Temperature SMGrade DYNAMIC RESPONSE Slow Rate SeWing TIme: 0.1% 0.01% Galn'Ban 50kn!2J -,25 +85 -25 +85 +150 ~5 .. · ·· VIlIS · ·· · · · TEMPERATURE RANGE Specification INA102AU Operation Storage kHz kHz kHz kHz kHz · POWER SUPPLY Ouiescent Current kHz kHz kHz kHz ·· . · · 0 -25 lIS lIS lIS lIS lIS lIS . . +70 -,25 +85 +85 -55 +125 V V !iA 'C 'C "C 'C ·Speclflcatlon same as for INA102AG. NOTES: (1) The internal gain set resistors have an absolute tolerance of ±20%; however, their tracking is 50ppm1'C.1\, will add to the gain error gains other than I, 10, 100 or 1000 are set externally. (2) At high temperature, output drive current is limited. An external buffer can be used If required. (3) Adjustable to zero. n PIN CONRGURATION ABSOLUTE MAXIMUM RATINGS 16 OIIset Adjust OIIset Adjust xl0 Gain +In x 100 Gain -In Supply ................................................................................................±18V Input Voltage Range ...........................................................................±Voo Operating Temperature Range ........................................ -,25'0 to +85'C Storage Temperature Range: Oeramlc .......................... ~5'C to +150'0 Plastic, SOIC ................. -55'C to +125'C Lead Temperature (soldering, lOs) ............................................... +300'C Output Short-Circuit Duration ................................. Continuous to Ground Filter +Vcc xl000 Gain Sense Output Gain Sense Common Gain Set 9 CMRTrim -Vee ORDERING INFORMATION MODEL INA102AG INAI02CG INAI02KP INAI02AU 3-12 PACKAGE TEMPERATURE RANGE Ceramic DIP Ceramic DIP -,25'0 to +85'C -,25'C to +85"C O'C to +70'C -,25'0 to +85"C Plastic DIP Plastic SOlO Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) MECHANICAL ,]J G Package - 16-Pln Ceramic DIP ~I_t[~,~' ~ N} t ~I -\[~ 1__11- -I 1-Csea~ng H- 0 G M1UIMETERS MIN MAX 20.07 20.57 4.32 2.67 0.38 0.53 1.22 1.52 2.54 BASIC 1.78 0.76 0.20 0.30 3.OS 6.10 7.62 BASIC 10' 0.64 1.52 NOTE: Leads In true position within 0.010· (O.25mm) RatMMCat seating plane • M N INCHES MIN MAX .790 .810 .IOS .170 .015 •021 .048 .060 .100 BASIC .030 .070 .008 .012 .120 .240 .300 BASIC 10' .025 .060 DIM A A, B B, C D F G H J K L M N P INCHES MIN MAX .740 .BOO .725 .785 .230 .290 .200 .250 .120 .200 .015 .023 .030 .070 .100 BASIC 0.20 I .050 .008 .015 .070 .150 .300 BASIC IS' 0' .010 .030 .025 .050 MILLIMETERS MIN MAX 18.80 20.32 18.42 19.94 5.85 7.38 5.09 6.36 3.OS 5.09 0.38 0.59 0.76 1.78 2.54 BASIC 0.51 I 1.27 0.20 0.38 1.78 3.82 7.63 BASIC IS' 0' 0.25 0.76 1.27 0.64 NOTE: Leads In true position within DIM A C D F G H J K ~\,~\ -j-J 1_ L-.J \..--M L S ::iz - - Plane P Package - 16-Pln Plastic DIP 0.010" (0.25mm) R at MMC at seating plane. IIII -U. ~ ~ Z - o !; I- Z III :IE Ii U Package -16-Pln SOIC II~ ~ ~ /'S s ~ ~I DIM A A, B B, C D G H J L M N rr ~ Pin ~ 1 Identifier g g g gg g g JI J'~~-D~~rn]~2: ~ I~~ INCHES MIN MAX .400 .416 .388 .412 .286 .302 .268 .286 .093 .109 .015 .020 .0.50 BASIC .022 .038 .008 .012 .421 .391 5'lYP .000 .012 MIWMETERS MIN MAX 10.16 10.57 9.86 10.46 7.26 7.67 7.26 6.81 2.36 2.77 0.38 0.51 1.27 BASIC 0.56 0.97 0.20 0.30 9.93 10.69 5'lYP 0.00 0.30 NOTE: Leads In true position within 0.010· (O.25mm) R at MMC at seating plane• !Q"J L Burr-Brown Ie Data Book Supplement, Vol. 33b if I 3-13 I;; z - For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES At +25"C and in circuit 0' Figure· 2 unless otherwise noted. GAIN YO FREOUENCY COMMON-MODE REJECtiON YO SOURCE IMBALANCE 80 120 iii :s. r: Ilnl ...... III 100 0 g m II: "8" :s. ·Iii (!) ~ G=10 20 60 G=1 o 0 40 10k lk lOOk 1M 100 10 ! ;; 30 ~ ~ 20 " 10 S S Ii'" V'N =20Vp-p all Source Imbalance .r: () o lk / a 2 QUIESCENT CURRENT vs SUPPLY 800 Vo .10V (no load) - 5 , " 400 II 1 -5 300 200 1\ / 0 ~ Vo -0 RL .10ka CL = 1000pF ;;;:1'000 ~ ±5 ::J I G=1 ±10 0500 i 4 STEP RESPONSE ~ 600 a 3 ±15 900 700 1M Time(ms) 1000 E lOOk V Frequency (Hz) a 10k lk ..-- ~ ~' r-... <" ... 40 " f tt~ 100 "- WARM-UP DRIFT vs TIME I..l.d! ibb 10 F'-> 50 G =,1000 40 O.1Vrms Frequency (Hz) COMMON-MODE REJECTION vs FREQUENCY I'-- r-... 1% Error IIIIII Source Resistance Imbalance (ll) 120 ~ III 0 100 ... III 0 E E • ...... G= 100 iii 40 80 Vwr G~~WJI 80 \ -10 ~ 100 a a -15 ±5 ±10 Supply Voltage (V) 3-14 ±15 ±20 o 2 345 6 7 8 Time (ms) Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) TYPICAL PERFORMANCE CURVES (CONT) At +25'C and in circuit of Figure 2 unless otherwise noted. SETTLING TIME vs GAIN to PEAK·PEAK VOLTAGE NOISE vs GAIN ? ~ RL = 10kll C L = 1000pF CIl - z 0.01% 0.1 i-': J , W 10 0.1% 0.Q1 10 1000 100 10 Gain (VN) INPUT NOISE VOLTAGE vs FREQUENCY 1000 POWER SUPPLY REJECTION vs FREQUENCY 10 :s :s. 100 Ii g 100 III 100 125 @ , "'- "... I- 75 ,,~ r--. :--.... EX: G=1 .~ I G= 10 z :--.... 50 § G = 100, G = 1000 .Q. IIIII IIIIII 10 1 10 100 lk 25 I I flll ::G~ G4n~ o 10k IIIIII Gain = 1000 "- G~ CIl li; I Z Gain (VN) 1000 '" "!:'::':': As =0 See 1"P:'~tif~~ ~f'on II ~ 'P' As = lMll 14.= 100kll - . I .- B 500kll r" ~ ~ " 7ut: ~ 100 ;:: I l!Iandwidth = 1Hz to 1MHz , > /.~ i 1000 1 10 Frequency (Hz) lk 100 10k 12 w --.... I I. A- Iz 52 ... = w Z Frequency (Hz) 2 i DISCUSSION OF PERFORMANCE I;; z - INSTRUMENTATION AMPLIFIERS Instrumentation amplifiers are differential-input closed-loop gain blocks whose committed circuit accurately amplifies the voltage applied to their inputs, They respond mainly to the difference between the two input signals and exhibit extremely high input impedance, both differentially and common-mode. The feedback network of this instrumentation amplifier is included on the monolithic chip. No external resistors are required for gains of 1. 10. 100. and 1000 in the INA 102. An operational amplifier. on the other hand. is an open-loop. uncommitted device that requires external networks to close the loop. While op amps can be used to achieve the same basic function as instrumentation amplifiers. it is very difficult to reach the same level of performance. Using op amps often leads to design tradeoffs when it is necessary to amplify low-level signals in the presence of common-mode voltages while maintaining high-input impedances. Figure 1 shows a simplified model of an instrumentation amplifier that eliminates most of the problems associated with op amps. Burr-Brown Ie Data Book Supplement. Vol. 33b 80 = eA + aa eA = G(e, - e,) = Ge. e. = G(e, + 8,)/2 Ge," CMRR = CMRR Gain Set Gain set Is pin-programmable for xl, xl0, xl00, xl000 In the INM02. FIGURE 1. Model of an Instrumentation Amplifier. 3-15 For Immediate Assistance, Contact Your Local Salesperson THE INA102 A simplified schematic of the INAlO2 is shown on the first page. A three-amplifier configuration is used to provide the desirable characteristics of a premium performance instrumentation amplifier. In addition, INAlO2 has features not normally found in integrated circuit instrumentation amplifiers. The input buffers (AI and A z) incorporate high performance, low-drift amplifier circuitry. The amplifiers are connected in the noninverting configuration to provide the high input impedance (10IOn) desirable in instrumentation amplifier ap.plications. The offset voltage, and offset voltage versus temperature, are low due to the monolithic design, and improved even further by state-of-the-art laser-trimming techniques. The output stage (A3) is connected in a unity-gain differential amplifier configuration. A critical part of this stage is the matching of the four 20k.{l resistors which provide the difference function. These resistors must be initially well matched and the matching must be maintained over temperature and time in order to retain good common-mode rejection. All of the internal resistors are made of thin-film nichrome on the integrated circuit. The critical resistors are lasertrimmed to provide the desired high gain accuracy and common-mode rejection. Nichrome ensures long-term stability and provides excellent TCR and TCR tracking. This provides gain accuracy and common-mode rejection when the INA102 is operated over wide temperature ranges. USING THE INA102 Figure 2 shows the simplest configuration of the INAI02. The output voltage is a function of the differential input voltage times the gain. A gain of I, 10, 100, or lOOO is selected by programming pins 2 through 7 (see Table I). Notice that for the gain of 1000, a special gain sense is provided to preserve accuracy. Although this is not always required, gain errors caused by external resistance in series with the low value 40.04n internal gain set resistor are thus eliminated. Other gains between I and 10, lO and 100, and 100 and 1000 can also be obtained by connecting an external resistor between pin 6 and either pin 2, 3, or 4, respectively (see Figure 6 for application). G = I + (40lRo) where Ro is the total resistance between the two inverting inputs of the input op amps. At high gains. where the value of Ra becomes smail, additional resistance (i.e., relays or sockets) in the Ro circuit will contribute to a gain error. Care should be taken to minimize this effect. OPTIONAL OFFSET ADJUSTMENT PROCEDURE It is sometimes desirable to null the input and/or output offset to achieve higher accuracy. The quality of the potentiometer will affect the results; therefore. choose one with good temperature and mechanical-resistance stability. The optional offset null capabilities are shown in Figure 3. R4 adjustment affects only the input stage component of the offset voltage. Note that the null condition will be disturbed when the gain is changed. Also. the input drift will be affected by approximately 0.311lVrC per 100llV of input offset voltage that is trimmed. Therefore. care should be taken when considering use of the control for removal of other sources of offset. Output offset correction can be accomplished with AI' R I• Rz, and~, by applying a voltage to Common (pin 10) through a buffer amplifier. This buffer limits the resistance in series with pin 10 to minimize CMR error. Resistance above o.ln will cause the common-mode rejecti!ln to fall below 100dB. Be certain to keep this resistance low. It is important to not exceed the input amplifiers' dynamic range. The amplified differential input signal and its associated common-mode voltage should not cause the output of Al or Az to exceed approximately ±12V with ±15V supplies. GAIN CONNECT PINS 1 10 100 1000 6t07 2to6and7 3t06and7 4 to 7 and separately 5 to 6 TABLE I. Pin-Programmable Gain Connections. ±15mV adjustment at ~e output. Output Output Offset Adjust +15VDC 10ka R, R3 1""'\""'-<:: 100ka lMn -15VDC lka FIGURE 2. Basic Circuit Connection for the INAI02. 3-16 FIGURE 3. Optional Offset Nulling. Burr-Brown 1C Data Book Supplement, Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) or nonlinear operation will result. To protect against moisture, especially in high gain, sealing compound may be used. Current injected into the offset pins should be minimized. 200 CMR Adjust OPTIONAL FILTERING The INA 102 has provisions for accomplishing filtering with one external capacitor between pins I I and 13. This singlepole filter can be used to reduce noise outside the signal bandwidth, but with some degradation to AC CMR. When it is important to preserve CMR versus frequency (especially at 60Hz), two capacitors should be used. The additional capacitor is connected between pins 8 and 10. This will maintain a balance of impedances in the output stage. Either of these capacitors could also be trimmed slightly, to maximize CMR, if desired. Note that their ratio tracking will affect CMR over temperature. ..g CC Z - OPTIONAL COMMON-MODE REJECTION TRIM Procedure: 1. Connect'CMV to both Inputs. 2. Adjust potentiometer for near zero at the output. FIGURE 4. Optional Circuit for Externally Trimming CMR. The INA 102 is laser-adjusted during manufacturing to assure high CMR. However, if desired, a smaIl resistance can be added in series with pin 10 to trim the CMR to an improved level. Depending upon the nature of the internal imbalances, either positive or negative resistance value could be required. The circuit shown in Figure 4 acts as a bipolar potentiometer and allows easy adjustment of CMR. 12 III --~ I I. +15V v +15V ~ Shield Z o e, = = ., III INA102 replaces classical three-op-amp InstrumentaUon amplifier_ 11 i I;; FIGURE 5. Amplification of a Differential Voltage from a Resistance Bridge. z +15V Transducer or Analog Signal Noise (60Hz Hum) SCUT a G (Ae,.) G = 1 + (40k/[R. + R,]) R. = (40k - R.,[G -l])/(G -1) R, a 4.4kil. 404Sl. or 400 In gains of 10.100. or 1000 respecUvely_ -15V Note: Gain drift will be higher than that specified with Internal resistors only. FIGURE 6. Amplification of a Transformer-Coupled Analog Signal Using External Gain Set. Burr-Brown Ie Data Book Supplement, Vol. 33b 3-17 For Immediate Assistance, Contact Your Local Salesperson TYPICAL APPLICATIONS Many applications of instrumentation amplifiers involve the amplification of low-level differential signals from. bridges and transducers such as strain gages, thermocouples, and RTDs. Some of the important parameters include commonmode rejection (differential cancellation of common-mode offset and noise, see Figure I), input impedance,. offset K voltage and drift, gain accuracy, linearity. and noise. The INAJ02 accomplishes all of these with high precision at surprisingly low quiescent current. However. in higher gains (> I 00). the bias current can cause a large offset error at the output. This can saturate the output unless the source impedance is separated. e.g., two 500kn paths instead of one IMrl unbalanced input. Figures 5 through 16 show some typical applications circuits. +15VDC +15VDC , , - r - - - . -15VDC G= 100 3 xl0 7 loon Digital IN914 Cold Junction Compensation +15VDC 6 4990n 15kn -15VDC -15VDC lMn 100kn 1----+---"IVv---~ Zero Adjust Up-Scale Burn·Qut Indication -15VDC -15VDC FIGURE 7. Isolated Thermocouple Amplifier with Cold Junction Compensation. +15VDC 11 '"'+ "E 0 E 0 0 ~ Note that xl000 gain sense has not been used to facilitate simple switching. .5 0 §! .'" 722 Isolation Power Supply S z = o -15VDC 0"0 §!Il§! "'~'" +0 "i ~ I- -=- 8 Z III I! FIGURE 10. Precision Isolated Instrumentation Amplifier. i Inz - r - - - - - , l Channel f Select ...-----1 1Gain f Select Control logic CP CE e3 1 e, • As shown channels 0 and 1 may be used for au,to offset zeroing. and gain calibratJon respectively. FIGURE 11. Multiple Channel Precision Instrumentation Amplifier with Programmable Gain. Burr-Brown Ie Data Book Supplement, Vol. 33b 3-19 For Immediate Assistance, Contact Your Local Salesperson !:~ -40 0 40 V'N (mV) FIGURE 12. 4mA to 20mA Bridge Transmitter Using Single Supply Instrumentation Amplifier. +15V +15V +15V 10kll 10kll Input Protection: 0 ~ xl0 xl00-:Gain Select FDH300 (Low Leakage) FIGURE 13. Programmable-Gain Instrumentation Amplifier Using the INA102 and PGAI02. e'N Ground Resistance FIGURE 14. Ground Resistance Loop Eliminator (INA102 senses and amplifies VI accurately). 3-20 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) +1SV g :cz - -1SV +1SV IIII .--.. -1SV Overall Gain = Aeou,JAe,. = 200 .• I I. FIGURE 15. Differential Input/Differential Output Amplifier (twice the gain of one INA). C +1SV z -=: 0 11 5, 16 52 1/2 DG5043CJ ...Z 8 1/2 DG5043CJ S. •i III 6 80UT Iiiz -1SV - 200~s O - -......--------------------~----' Control All switches shown In logic '0" switch state. - -1SV CONTROL S, S, S, S. S, MODE 1 o Closed Open Closed Open Open Closed Open Closed Closed Open Signal Amplification Auto-Zeroing HGURE 16. Auto-Zeroing Instrumentation Amplifier Circuit. Burr-Brown Ie Data Book Supplement. Vol. 33b 3-21 For Immediate Assistance, Contact Your Local Salesperson BURR-BROWN@ INA103 1-=--=-1 Low Noise, Low Distortion INSTRUMENTATION AMPLIFIER FEATURES APPLICATIONS • LOW NOISE: 1nV/VHZ • LOW THD : <0.002% typ 20Hz-20kHz, G 1 to 100 • HIGH QUALITY MICROPHONE PREAMPS (REPLACES TRANSFORMERS) = = • HIGH GBW: 100MHz at G 1000 • WIDE SUPPLY RANGE: ±9V to ±25V • HIGH CMRR: >110dB • BUILT-IN GAIN SETTING RESISTORS: G = 1, 100 • MOVING-COIL PREAMPLIFIERS • DIFFERENTIAL RECEIVERS • AMPLIFICATION OF SIGNALS FROM SOURCES SUCH AS: Strain Gages (Weigh Scale Applications) Thermocouples Bridge Transducers • UPGRADES AD625 DESCRIPTION The INA103 is an extremely low noise, low distortion monolithic instrumentation amplifier which is especially suitable for amplification of low level signals in audio systems. Input circuitry provides near-theoretical limit noise performance for 2000 source impedances. A unique distortion-cancellation network in the input stage reduces THD to extremely low levels. The INA 103 iseliually well-suited to preamplification and signal conditioning applications where low noise is required. In many cases, transformer coupling can be replaced by the INA103 to reduce cost and improve perforinance in signal conditioning systems. The wide supply range (±9V to ±25V) of the "INA 103 increases its versatility. A copper lead frame in the plastic DIP package assures excellent thermal performance. The INA103 pin configuration is compatible with the AD625. In many applications, the INA103 can replace the AD625 for improved performance. The INA103 is available in 16-pin DIP packages specified for the commercial (plastic DIP) and industrial (ceramic DIP) temperature ranges. Offset Offset Null Null 3 -Input -Gain Sense -flo +Galn Sense 2 +Input I +Gain Drive V+ V- international Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • St!eet Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (602) 746-1111 • Twx: 910.952·"11 • cable: BBReORP • relex: 0SU491 • FAX: (602)8119-1510 • Immedlela Product Info: (800) 548-6132 PDS·1016A 3-22 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL All specifications at TA = +25'C, Vs = ±15V and f\ = 2kn, unless otherwise noted. INA103AG PARAMETER CONDITIONS GAIN Range 01 Gain MIN 1 GaIn Equation II) G Gain Error, DC G = 1 G = 100 Eq. Gain Temp. Co. G = 1 G = 100 Eq. Nonlinearity, DC G = 1 G = 100 ±10V Output ±10V Output ±10V Output I TYP I ·61 o ./' ~ o" Iz V ±15 / ±10 '" ±S ±5 - .= / /' ±10 Z ±15 III ±20 ±25 Power Supply Voltage (V) = -z MAX COMMON·MODE VOLTAGE vs OUTPUT VOLTAGE ~ CD 16.5 ~ " 't:I 0 11 :::;; c0 E IS 5.5 (.) 5.5 11 16.5 22 Output Voltage (V) Burr-Brown Ie Data Book Supplement. Vol. 33b IE i 22 , - 12 III ±25 ~ TEMP RANGE - /' " PACKAGE CC Z V / ±15 " ±10 ~ ORDERING INFORMATION ..s INPUT VOLTAGE RANGE vs SUPPLY ±25 -Gain Drive 3-25 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) At T" = +25°C, Vs = ±15V unless otherwise noted. OFFSET VOLTAGE vs TIME FROM POWER UP (G=I00) OUTPUT SWING vs LOAD RESISTANCE 20 ±16 .. ~ ±12 f ±8 I ~ " 0 ±4 ~ V/ ,----,----r---r---r-----, 10 u; ;? .. " ~ ti II 0 -10 FS!G'=-I---I---t----t-----I ±o o 200 800 600 400 lk INPUT BIAS CURRENT vs TEMPERATURE ~ 2.50 ~ 2.45 ~ 2.40 o :; ~ 6 ...... !'-.. 2.55 :; i % 0 0 Time 3-26 5 4 lime (min) INPUT BIAS CURRENT vs SUPPLY 2.60 3 2 Load Resislance (n) (~s) lime (~s) Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) TYPICAL PERFORMANCE CURVES (CONT) AI T. = +25'C. V, = ±15V unless otherwise nOled. LARGE SIGNAL TRANSIENT RESPONSE (G=I) LARGE SIGNAL TRANSIENT RESPONSE (G= 100) B ... C Z Time(~s) Time (~s) 12 III SETTLING TIME vs GAIN (0.1%. 20V STEP) --.... SETTLING TIME vs GAIN (0.01%. 20V STEP) 10 IL 10 A. " E 6 F g> 4 2 ~ /v r- l- V CIl o 100 1 1000 10 (!) 60 50 G = 1000 40 30 G= 100 - II l¥:;z -- 100 '" .~. 10 0 z - -{JO ....... I=:::: -40 -SO lk 10k 1000 lOOk 1M 10M :E - 10 G- \0 G= 100 G=500 G=1 000 lk 100 10k Frequency (Hz) Burr-Brown Ie Data Book Supplement, Vol. 33b III ~ Ji; G=1 - r= !is G=1 100 100 Z .s t- III 10 to- NOISE (RTI) vs FREQUENCY t-.. II 10 0 = lk G= 10 -10 -20 - Gain SMALL·SIGNAL FREQUENCY RESPONSE 70 i o Z Gain 20 V o 10 fg / Z ~ 2 I-"" ~ v ...a 3-27 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) At T, ~ +25'C. V. =±15V unless otherwise noted. THO + N vs FREOUENCY CMR vs FREQUENCY 140 ~1W iii' 120 la. ,.," 100 a; te "" 80 " 60 0 ~ ~0 E E 40 0 20 0 l~ ~~ O.I~_~~ l z ~+ ~ If'" o . O I O . G . = I O O O• G=I 0.001 G= 10 II I 10 100 Ik 10k lOOk G = 10 0.0001 L.....J.....J...I..u..w._J.....j...J..I..I.J.I..u..........J....I..LJ.................. 10 10k 20k 100 Ik Frequency (Hz) 1M Frequency (Hz) V+ POWER SUPPLY REJECTION vs FREQUENCY 140 iii' la. t20 " .~., " te 100 ~ a. 60 " 140 G= 10 G~I' iii' r-., la. g" .... I"- 80 0 ~ '"~ 40 0. 20 0 r- G= 10 =10 V- POWER SUPPLY REJECTION vs FREQUENCY G=I I 120 .... r-., G=II 100 a; 80 i 60 =I !c. I"r-., '" 40 Q. 20 ~ ~ i' ~ ~ l"- ~ i' I'~ ~ I' 0 10 100 Ik 10k lOOk 10 1M 100 Frequency (Hz) Ik lOOk 10k 1M Frequency (Hz) THO ... N vs LOAD THO + N vs LEVEL 0.1 G _1 = 20Vp-!i: 1=lkHz VOIJ'( e z + o ~ I-1kHz "- 0.1 ~ 0.01 z + :r: " 0.010 0 l- 0.001 I--. G=I ...... 0.001 0.0005 0.0001 -60 -45 -{l0 -15 o 15 200 400 800 lk Output Amplitude (dBu) 3-28 Burr-Brown Ie DataBook Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES At T" = +25°C, (CO NT) Vs = ±15V unless otherwise noted. CCIF IMD vs FREQUENCY CCIF IMD vs AMPLITUDE e ...sC 0.1 Z 0 :l! G= 000 u.. 0.010 (3 u G= 00 ~~~~~,~~~~~~~~~ 0.0001 -60 -50 -40 -30 -20 -10 0 10 0.001 G= 0 G= 0.0001 20 10k 2k 20k Frequency (Hz) Output Amplitude (dBu) - 12 III .--A-.. SMPTE IMD vs FREQUENCY SMPTE IMD vs AMPLITUDE I I. 5 l~ I ......... ;§ ......... "'- 0.1 en 0 :l! G= 100 w 0"::; I! e G -1000 ~ 0 0.1 w "::; I'.... i'.... G=l ......... en z I 0- 0.010 c 100 F==G 0.010 - '==G~10 0 f--- G =l G= 10 I'. 0.001 0.0005 -60 -50 -40 -30 -20 -10 0 --7 10 G-l0 0.001 0.0005 20 Output Amplitude (dBu) 10k 2k 20k Frequency (Hz) ... = Z '111 I! :::) II: Inz - Burr-Brown Ie Data Book Supplement, Vol. 33b 3-29 For Immediate Assistance, Contact Your Local Salesperson DISCUSSION OF PERFORMANCE A simplified diagram of the INA103 is shown on the first page. The design uses a current feedback architecture which can be thought o( as a classical three-op-amp instrumentation amplifier. The input stage (AI and Az) incorporates widebandwidth, low noise, low drift amplifier circuitry. The unity-gain difference amp removes the common-mode signal from this input stage output signal, giving a single-ended output referred to the potential at the reference pin. The Gain vs Frequency performance (shown in the Typical Performance Curves) illustrates the advantage of the circuit topology used in the INAI03: bandwidth remains nearly constant over gain ranges from 1 to 100. This yields a gainbandwidth product (GBW) of>I00MHz at G = 1000. Gainrelated errors are greatly reduced due to this high GBW. A distortion cancellation input stage and improved output stage reduce THD + N to less than 0.002% from 20Hz to 20kHz. The output can drive 200n loads with no crossover distortion (at 1kHz). These performance advantages make the INAI03 ideal for instrumentation amplifier applications which require low noise, excellent dynamic and· spectral response, and wide bandwidth. BASIC POWER SUPPLV AND SIGNAL CONNECTIONS Figure 1 shows the proper connections for power supply and signal. Supplies should be decoupled with IJ.IF tantalum capacitors as close to the amplifier as possible. To avoid gain and CMR errors introdliced by the external circuit, connect grounds as indicated, being sure to minimize ground resistance. Resistance in series with the reference (pin 7) or the sense (pin 11) will degrade CMR. Also, to maintain stability, avoid capacitance from the output to the gain set, offset adjust, and input pins. A suggested PC board layout is shown in Figure 2. FIGURE 2. Suggested PC Board Layout for INAI03. (Not Available from Burr-Brown). OFFSET ADJUSTMENT As with aU instrumentation amplifiers, voltage offsets occur in both the input and output stages of the INAI03. Inputreferred voltage offsets are multiplied by the overall gain of the IA. Output-referred offsets are multiplied by the gain of the output stage (usually gain = I). Input and output voltage offsets are actively laser-trimmed to near zero at the factory; Applications which require user voltage offset adjustment can employ one of the methods discussed below. Output voltage offset can be adjusted using the null pins on the INAI03, as shown in Figure 3. Although the null pins primarily adjust the output offset, they also have a small effect on the input offset. For ImV of output offset change, the input offset will change approximately 1J.lV. Also, offset adjustment using the null pins will change the offset voltage drift of the INAI03. For ImV of offset change, the output offset drift changes by 3j1VfC. The change in input offset drift is negligible. 13 t.V'N Ro :>--'-"-_OVOIJT 14 6 2 Offset Adjust Range ~ ±2SOtnV. FIGURE 1. Basic Circuit Configuration. 3-30 FIGURE 3. Offset Adjustment Circuit. Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service aI1·800·548·6132 (USA Only) For output voltage offset adjustment with no effect on voltage offset drift or input voltage offset. use the circuit shown in Figure 4. The INAI03 has no trim pins for input offset adjustment. However. in AC coupled applications. input offset adjustment can be accomplished using the circuit shown in Figure 5. The circuit shown in Figure 6 will provide automatic DC restoration for the Figure 5 circuit. The low frequency rolloff of this circuit is a function of the IA gain. (3dD = gain/(12' 1t. R· C). Galn~ 100VN (4OdS) 0-1 ~-'-"-l -In A 100kO C Z ~H-'-'-I - 100kli(1) The circuit shown in Figure 7 can also be used for Vos adjustment in floating source applications as long as the source impedance is greater than lOn. If the source impedance is less than lOn. the offset range may not be adequate to trim out the maximum input-referred Vos of the INAI03. s... 2kll -:- NOTE: (1) 100kllis max recommended value. Use smaller value if possible. FIGURE 6. Automatic DC Restoration. Gain = IVN (OdS) IIII .--aa.... Gain = 100VN (4OdS) Floating Source As> lOll (e.g .. Microphone) Ii c z o NOTE: (1) 50kO A. 100kO pot is max recommended value. Use smaller values in this ratio il possible. '112 AEF200 E z UI Ii FIGURE 7. Input Offset Adjustment for Floating Source. FIGURE 4. Output Offsetting. Gain~IOOVN (4OdS) NOTE: (I) 50kll A. 100kO pot is max recommended value. Use smaller values In this ratio if possible. GAIN SE.LECTION Gain selection is accomplished by strapping together the appropriate pins on the INA 103. Table I shows possible gains from the internal resistors. To use the internal feedback resistors. connect pin 13 to pin 15. and pin 2 to pin 6. Keep the connections as short as possible to maintain accuracy. Gains other than 1 and 100 can be set by adding an external resistor. Ro. as shown in Figure 8. Gain accuracy is a fUflction of resistor matching. For internal gains. accuracy is as shown in Table I. For external Ro. accuracy is a function of the external resistor accuracy. internal feedback resistor accuracy (typically 0.1%) and interconnection resistance (typically O.ln). The equation for choosing Ro is shown below: R _ 6kn G - G-I where G is the gain value in VIV. FIGURE 5. Input Offset Adjustment for AC-Coupled Inputs. 1 100 CONNECT PIN 14 TO GAIN ACCURACY (%) None Pin 2 0.01 0.1 TABLE I. Internal Gain Connections. Burr-Brown Ie Data Book Supplement, Vol. 33b 3-31 ::) a: Iiiz - For Immediate Assistance" Contact Your Local Salesperson >-"'-+--.-.OVom R. (ll) NOTE: R. 10rG = 100 Is available Internally, see text. 3.16 10 31.6 100 316 1000 10 20 30 40 50 60 2774 667 196 60.6' 19 6 FIGURE 8. Gain Setting Using External Resistor, (a) AC625 G = 1, V" = ±15V, R, = 600ll Oulput Stage Gain ~ (R, II 12k) + R, + R, (R,1I12k) OUTPUT STAGE GAIN R, and II, II, (kill (lll 2 5 10 lk 1.2k 1.2k 6320 2.4k 273ll FIGURE 9, Gain Adjustment of Output Stage. (b) INA1D3 G = 1, V~ =±15V, R, = 600ll A common problem wnh many Ie op amps and instrumentation ampliliers is shown in (a). Here, the amplifie(s input is driven beyond its linear common mode range, lorcing the oulput 01 the amplifier Into !he supply ralls. The oulput then "folds back", i.e., a more positive input voltage now causes the oulput 01 !he amplifier to go negative. The INA103 has protection circuitry to preVent fold·back, and as shown in (b), limits cleanly. FIGURE 10. INAI03 Overload Condition Performance. COMMON-MODE INPUT RANGE For low distortion, the differential input signal and its common-mode voltage must not cause the input amplifiers' outputs to exceed their linear output range (See Max CommonModeVoltage vs Output Voltage curve). This can be avoided by reducing the input stage gain and increasing the output stage gain as shown in Figure 9, This is also useful for increasing total gain. Galn=1VN (Od8) Unlike some instrumentation amplifiers, the INAI03 will limit cleanly under overload conditions. See Figure 10. OPTIONAL COMMON-MODE REJECTiON TRIM The INA 103 is laser-adjusted during !I1anufacturing to assure high CMR. However, if desired, the circuit shown in Figure II may be used to trim the CMR. Note that an approximate +0.2% gain error is induced. . 3-32 FIGURE II. Optional Circuit for Externally Trimming CMR. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) OUTPUT SENSE An output-sense terminal allows greater accuracy in connecting the load. By attaching this feedback point at the load, IR drops due to load currents are eliminated since they are inside the feedback loop. Proper connection is shown in Figure 1. When more output current is needed, a power booster can be placed within the feedback loop as shown in Figure 12. Buffer errors are. reduced by the loop gain of the output amplifier. v. Inductive source impedances may cause the INAI03 to oscillate. Placing a 470pF capacitor from each input to ground will prevent oscillation in such rare instances. Typical audio applications I!sing twisted pair or coax generally do not require these capacitors. APPLICATIONS Many applications of instmmentation amplifiers involve the amplification of low-level differential signals from bridges and transducers such as strain gages, thermocouples, and RTDs. Some of the important parameters include commonmode rejection (differential cancellation of common-mode offset and noise), input impedance, offset voltage and drift, gain accuracy, linearity and noise. The INAlO3 accomplishes all of these with high precision. In addition, the INAI03 has been designed to provide extremely low noise and distor::::; for dynamic applications such as microphone preamplifiers in professional-quality mixing consoles. FIGURE 12. Current Boosting the Output. INPUT IMPEDANCE AND PROTECTION CONSIDERATIONS As with any low noise circuit, careful layout and power supply bypassing is necessary to prevent the coupling of noise sources into the INAlO3 through the power supply or from EMI radiation. A return path for the input bias currents must always be provided. A resistor from the input to common will properly bias floating sources such as transformers, thermocouples, and AC-coupled inputs. This resistor should be high enough in value to prevent loading the source. The input bias currents flowing through these resistors will introduce a commonmode voltage to the amplifier, and caution should be exercised to assure that this common-mode voltage, in addition to the input signal, does not cause the input amplifiers to saturate. (See Common-Mode Input Range, above). It is often necessary to decouple the input of the INAl03 from the source (for example, in audio mixing systems where the INAlO3 may be placed on a buss). In this case, series resistors may be used to decouple the input. The source impedance presented to the INAlO3 should be as low as possible, to minimize DC errors and noise which may result due to the input bias current of the INAI03. In addition, resistor values should be chosen to limit the input current to the INA103 to lOrnA. While it is unlikely such currents would result from a signal input, should one power supply rail be lost due to a power supply failure or other system fault, it is possible for large currents to flow from the other power supply to ground through the input stage. Setting ROECOUPLE ~ 2500 should be adequate to provide this protection. Figure 13 shows a circuit with a decoupled and protected input. A graph is included to assist in choosing the best resistor values. Although the INAlO3 contains internal 3ill feedback resistors to set input stage gain, external feedback resistors can be used, as shown in Figure 14. For gains other than I or 100, it is possible to improve gain accuracy and gain temperature 'P' C Z I!III .-ii:.. A. :I c z o TOTAL INPUT NOISE ys OECOUPLING RESISTANCE 100 ~ NOTE: If ROECOUPLE > 2kn use INA110. l!;;; .s 1= - / ... = Z 10 III !5. :I .~ z :::) II: -I--' 1 10 100 10k lk lOOk RDECOUPLE 11 RaIAS (O) Gain ~ 1000VN (6OdB) ROECOUPLE R.IAS FIGURE 13. Input Decoupling and Protection. Burr-Brown Ie Data Book Supplement, Vol. 33b B 3-33 I; Z For Immediate Assistance, Contact Your Local Salesperson coefficient by using matched external feedback and gain set resistors (the internal feedback resistors can have SOppm/"C TCR). Other amplifiers, such as the AD625, have no internal feedback resistors. When using the INAI03 to replace the AD62S in existing circuits, the external feedback resistors 15 13 &V'N Flo 14 6 2 2R. G=1+R; present in the existing circuit may be used (see Figure 14), or the circuit may be modified to take advantage of the INAI03's internal resistors. The INAI03 input amplifiers are current feedback type. The value of the feedback resistors affects the dynamic performance and stability. Feedback resistors less than 2.S1d1 may result in instability. Feedback resistors larger than 31d1 will result in reduced gain bandwidth and increased noise. For example, feedback resistors of 201d1 will increase the gainof-lOOOinputreferred-noise of the INAI03 from InVNHzto 1.SnVr/Hz. Figure IS is one way to make a microphone preamplifier with the INAI03. This circuit is designed to allow the microphone to be phantom powered, and also allows for a 20dB pad on the input. The DC restoration circuit using the OPA627 has a low frequency cutoff of l.S9Hz, and automatically removes DC offsets from the amplified output signal. Figures 16 through 19 show other applications circuits. NOTE: AD625 equivalent pinout. FIGURE 14. Use of External Resistors for Gain Set. 47pF/63V + +46V 1 Phantom Power 240n 47ka 6.akn "::" >---'"'-+--_-oVOUT 100ka 47pF/63V FIGURE IS.Microphone Preamplifier with Provision for Phantom Power Microphones. , 1~-7\ ! \ 10ka \ '/ 11 &V'N VOUT ,; ! , \ I "- 10ka I \ ;>..1 loon OPA602 Shield driver minimizes degradation of CMR due to cfostributed capacItanc:e on the. Input lines. FIGURE 16. Instrumentation Amplifier with Shield Driver. 3-34 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) s,.. CC Z - Gain = 100VN (4Od8) FIGURE 17. Gain-of-1OO INA103 with FET Buffers. IIII .--.. S Z I&. A. o - ... = Gain = 100VN (4Od8) Z III 15 i FIGURE 18. Bridge Amplifier. Iiiz - Gain = l00VN (4OdB) Moving Magnet Cartridge 150pF (Note 1) 7.32kn Gain = 10VN (2OdB) 1001<0 23.7kn 23.7kn NOTES: (1) Load Rand C per cartridge manufacturer's recommendations. (2) Use metal film resistors and plastic film capac~ors. (3) Bypass ±Vs adequately. FIGURE 19. RIAA Phono Preamplifier. Burr-Brown Ie Data Book Supplement, Vol.33b 3-35 For Immediate Assistance, Contact Your Local Salesperson INA117 IiRR-BROWN8 E51E5II High Common-Mode Voltage DIFFERENCE AMPLIFIER FEATURES APPLICATIONS • COMMON-MODE INPUT RANGE: ±2OOV (Vs ±15V) • CURRENT MONITOR • BATTERY CELL-VOLTAGE MONITOR • PROTECTED INPUTS: ±5OOV Common-Mode ±500V Differential • GROUND BREAKER • INPUT PROTECTION • SIGNAL ACQUISITION IN NOISY ENVIRONMENTS = • UNITY GAIN: 0.02% Gain Error max • NONLINEARITY: 0.001% max • FACTORY AUTOMATION • CMRR: 86dB min DESCRIPTION The INA1l7 is a precision unity-gain difference amplifier with very high common-mode input voltage range. It is a single monolithic Ie consisting of a. precision op amp and integrated thin-film resistor network. It can accurately measure small differential voltages in the presence of common-mode signals up to ±200V. The INAIl7 inputs are protected from momentary common-mode or differential overloads up to ±500V. In many applications. where galvanic isolation is not essential. the INA 117 can replace isolation amplifiers. This can eliminate costly isolated input-side power supplies and their associated ripple. noise and quiescent current. The INAll7's 0.001% nonlinearity and 200kHz bandwidth are superior to those of conventional isolation amplifiers. The INA 117 is available in 8-pin plastic mini-DIP and S0-8 surface-mount packages. specified for the ooe to +700 e temperature range. The metal TO-99 models are available specified for the -25°e to +85°e and -55°e to +125°e temperature range. lntamalional AIrport IndUllrIal Parle • IIIRIng Addrea: PO Box 11400. • TUcIOn, AZ 85734 • SlnIet Add....: 6730 S. TIIcaI Blvd. • Tuclan, AZ 857IJIj T81: (6021 746-1111 • 1Wx:11D-tsz.1111 • Cable:BBRCORP • TeIex:06H481 • FAX: (6021 889-1510 • _IaIaProductlnlo:(800)54IIf132 PDS·748D 3-36 Burr-Brown Ie Data Book Supplement. Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL At T. = +25'C. V, = ±15V unless otherwise noted. INAI17AM. SM PARAMETER CONDmONS MIN GAIN InitiaJ l1 ) Error vs Temperature Nonlinearity (21 OUTPUT Rated Voltage Rated Current Impedance Current Limit Capacitive Load INPUT Impedance Voltage Range Common-Mode Rejection 0' DC AC.60Hz vs Temperature. DC AM. BM. p. KU SM OFFSET VOLTAGE Inilial KU Grade (SO-8 Package vs Temperature vs Supply 10 ~ +20mA. -5rnA Vo = 10V Ve• = 400Vp-p T. = T.... to T..... MAX I 0.01 2 0.0002 0.05 10 0.001 10 +20. -5 12 0.01 1~900013 To Common Stable Operation Differential Common·Mode Differential Common·Mode. Continuous TYP 800 400 ±IO ±2D0 VOLTAGE :: = O.OIHz to 10Hz = 10kHz DYNAMIC RESPONSE Gain Bandwldlh. ~B Full Power Bandwidth Slew Rate Settling Time: 0.1% 0.01% 0.01% POWER SUPPLY Rated Voltage Range Quiescent Current TEMPERATURE RANGE Specification: AM. BM. P. KU SM Operation Storage TYP INAll1P. KU MAX MIN TYP ·· ·· · · · · ·· · ·· · ·· ··· · ·· ·· · · · ·· ·· · · · ·· · · · ·· · · ·· ·· · ·· · ·· · ·· ·· · ·· · · ·· ·· 0.02 V rnA n 75 75 60 90 dB dB 1000 8.5 74 40 90 25 550 200 30 2 2.6 6.5 10 4.5 ±15 ±5 1.5 -,25 -55 -55 -55 · 2000 20 80 200 ±18 2 +85 +125 +125 +150 0 -,25 -40 !lV !lV !lVrC dB !lV/mo !l"m. nV Hz kHz kHz V/j1S j1S :: ·· V V rnA +70 'C +85 +85 'C 'C 'c 'Specilicallon same as lor INAI17AM. NOTES: (1) Connected as difference amplifier (see Figure 1). (2) Nonlinearity Is the maximum peak deviation from the best-fit stra1ghtllne as a percent 01 ful~scaJe peak-IO-peak oUlpul (3) With zero source Impedance (see discussion 01 common-mode rejection In AppIicaIlon Information section). (4) Includes effects 01 amptifIar's Input bias and offset currents. (5) Includes effects 01 amplifiefs Input current noise and thermal noise contribution of resistor netwcrk. Burr-Brown Ie Data Book Supplement, Vol.33b Z kn kn V V 66 60 1000 ... :c ..... rnA pF dB dB RTO·' Derated Performance Vo= OV VN % ppml"C % 94 94 600 Vo = 10V Step Vo = 10V Step Ve• = 10V Step. V';'" ~ OV · · 86 66 120 Vo = 20Vp-p UNITS 80 80 RTO·' TA = TUIN to TMAX V. = ±5V to ±18V MAX 70 66 vs Time ~IJ!NOISE INA117BM MIN 3-37 IW -I I. ~ A- Ii CC Z 0 - ... = w Z Ii ::» ~ IiiZ - For Immediate Assistance, Contact Your Local Salesperson MECHANICAL M Package - Metal 1'0-99 -ADII.! A 8 C D E F 0 H J K L I.! N yl INCHES MIN MAX .335 .370 .305 .335 .165 .165 .016 .021 .010 .040 .010 .040 .200 BASIC .028 .034 .045 .500 .110 .160 45°BASIC .095 .IOS .029 - MlWMElERS MIN MAX 8.51 9.40 8.51 7.75 4.19 4.70 OAI 0.53 1.02 0.25 0.25 1.02 5.08 BASIC 0.71 0.88 0.74 1.14 12.7 2.79 4.06 45" BASIC 2.41 2.67 NOTE: Leads In lrUe position within 0.01" (O.25mm) Rat MMC at seating plana. Tab Is pin 8. - P Package -lJ.Pln PlastIc DIP P- DIM A A. 8 8. C E. ~nl J I~ i kF. ~=1i1 J--1 }1~~1ift l :8. 'f S - ex LA, a. '-- 8 E .045 .006 .370 .300 .065 .012 0400 .325 EI 240 260 81 .100 BASIC .300 BASIC .125 .150 0(11 . INCHES MAX .155 .200 .020 .050 .014 .020 MIN 8A L MlWMETERS MAX 3.94 5.08 0.51 1.27 0.36 0.51 1.14 1.65 0.20 0.30 9.40 10.16 7.62 826 6.10 8.60 2.54 BASIC 7.62 BASIC 3.18 3.81 MIN DIM UO> ex P QI 8(11 INCHES MIN MAX .030 0 15" 11' .015 .050 .040 .075 .015 .050 MIWMETERS MIN MAX 0.00 0.76 15° 11' 0.36 1.270 1.02 1.91 0.36 127 (I) NOI JEOEC Sill. (2) al and a. applies In zone I, whan unft Installed. NOTE: Leads In lrUe position within 0.01" (O.25mm) R 81 MMC at seating plane. C Seating ~a . U Package - 8-Pln SOIC ~:.~ DIM A AI fl 8 81 C D 0 H J1 Pin I Identlliar l(~nIU JL H ---1 J L telA l\bj ~1' o..J \.Jf f''---L---lf M N INCHES MIN MAX .165 .201 .178 .201 .148 .162 .130 .149 .145 .054 .015 .019 .050 BASIC .D18 .026 .012 .D08 220 .252 111' 11' .000 .012 MlWMETERS MIN MAX 4.70 5.11 4.52 5.11· 3.71 4.11 3.30 3.78 1.37 3.69 0.36 DAB 1.27 BASIC DAB 0.66 0.20 0.30 5.59 6.40 11' 111' 0.00 0.30 NOTE: Leads In lrUa posIllon within 0.01" (O.25mm) R at MMC at seating plane. G 3-38 Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1-800-548-6132 (USA Only) PIN CONAGURATION Metal T().99 1NA117AM, BIoI, 8M Top View Tab Plastic DIP and INAl17P, KU sole Top View ,..... ~ Z V- Case Inlamally connOCled 10 V-. Make no connecllon. IIII --a. ABSOLUTE MAXIMUM RATINGS I I. Supply Vollage ...................................................................................±22V Input Voliage Range, COntinuous ................................................... ±200V Common-Mode and Differential, lOS ........................................... ±500V Operating Telf1l8rawre M Metal TO-99 Package .................................................-5510 +125'<: P Plastic DIP and U 50-8 ................................................ -40 to +85'<: Storage TernperaWre M Package ....................................................................... -65 to + 125'C P Plastic DIP and U 50-8 ................................................ -40 to +85'C Lead Ternperawre (soldering, IDs) ............................................... ..aoo'C Output Short Circuit to Common ........................,.................... Continuous ~ S z o - ... = ORDERING INFORMATION Z YODEL INA117P INA117KU INAI17AM INA117BM INA117SM PACKAGE TEMPERATURE RANGE Plastic DIP 50-8 SUrface-Mount T0-99 Metal T0-99 Metal T0-99 Metal O'C to +70'C O'C to +7O'C -25'<: to +85'<: -25'C to +85'C -65'C to +125'<: •i III t;; z - TYPICAL PERFORMANCE CURVES T. = +25'<:, V. = ±15V unless otherwise noted. COMMON-MODE REJECTION vs FREQUENCY 100 POWER SUPPLY REJECTION vs FREQUENCY 100 INA117 M iii" :2. 90 " .2 11 I " IIor 0 80 a; I II: ~ 70 i:. 60 E E 0 0 50 1 MS, U \. 2 0 ... II: 90 80 - V+ ,"- 70 :J J 40 .... '" 8: UI " ,! .IJ~I ~ ,"- 60 50 " ~ 40 20 100 lk 10k lOOk 2M Frequency (Hz) Burr-Brown Ie Data Book Supplement. Vol_ 33b 1 10 100 lk 10k Frequency (Hz) 3-39 For ·lmmelJiate Assistance; Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) T•• +25"C. v•• ±15V unless otherwise noted. POSITIVE COMMON-MODE VOLTAGE RANGE lIS POSITIVE POWER SUPPLY VOLTAGE TAI • i ~1+2J"C Max RatIng • 200V _1 _1 _ _ ~ ~~ ~ 50 d ::;:: r 5 ..ks..c NEGATIVE COMMON-MODE VOLTAGE RANGE lIS NEGATIVE POWER SUPPLY VOLTAGE , j,~~lJ :' " , ~: :"f~ ~ "" ~~ , -f-f~~ -v•• -5V 10 -20V I 15 10 20 -15 -10 PoshJve Power Supply Voltage M Negative Power Supply Vollage M SMALL SIGNAL STEP RESPONSE SMALL SIGNAL STEP RESPONSE c,,-O -20 CL-l000pF LARGE SIGNAL STEP RESPONSE 3-40 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) APPLICATION INFORMATION V- V+ Figure I shows the basic connections required for operation. 7 4 Applications with noisy or high impedance power supply lines may require decoupling capacitors close to the device pins. The output voltage is equal to the differential input voltage between pins 2 and 3. The common mode input voltage is rejected.. C z Internal circuitry connected to the compensation pin 8 cancels the parasitic distributed capacitance between the feedback resistor. R2• and the IC substrate. For specified dynamic performance. pin 8 should be grounded or connected through a O.lI1F capacitor to an AC ground such as V+. -15V t- op 6 - L--r:B:---+.--t:::------'+15V 5 +15V (a) 1~ -L TantalUmT+-::-+ 2 r-~~-----~....L:---. R,4 R:. 7 380kll + l l~F IIU Tantalum V- 380kll 2 6 3 -ii:~ 7 4 380kll 380kll Iz V. 6 -... = 3 o V. Z IU FIGURE 1. Basic Power and Signal Connections. IE COMMON-MODE REJECTION Common-mode rejection (CMR) of the INA I 17 is dependent on the input resistor network. which is laser-trimmed for accurate ratio matching. To maintain high CMR. it is important to have low source impedances driving the two inputs. A 75.0 resistance in series with pin 2 or 3 will decrease CMR from 86dB to 72dB. Resistance in series with the reference pins will also degrade CMR. A 4.0 resistance in series with pin I or 5 will decrease CMRR from 86dB to 72dB. Most applications do not require trimming. Figures 2 and 3 show optional circuits that may be used for trimming offset voltage and common-mode rejection. TRANSFER FUNCTION Most applications use the INAIl7 as a simple unity-gain difference amplifier. The transfer function is: i (b) I;; z Offsel adjustmenlls regulaladInsensitive to power supply variations. - V- FIGURE 2. Offset Voltage Trim Circuits. Some applications. however. apply voltages to the reference terminals (pins I and 5). A more complete transfer function is: Vo = V3 - V2 + 19-V, - IS-VI Vs and V I are the voltages at pins 5 and 1. VO=V3- V2 V3 and V2 are the voltages at pins 3 and 2. Burr-Brown Ie Data Book Supplement, Vol. 33b 341 For Immediate Assistance, Contact Your Local Salesperson MEASURING CURRENT The INA 117 can be used to measure a cunent by sensing the voltage drop across a series resistor, Rs' Figure 4 shows the INAII7 used to measure the supply cunents of a device under test. The circuit in Figure 5 measures the output current of a power supply. If the power supply has a sense connection, it can be connected to the output side of Rs to eliminate the voltage-drop error. Another common application is current-to-voltage conversion as shown in Figure 6. v- v- (+2OOVmax) +v. 7 4 Re· 2 38OkO 3 38OkO v+ 4 7 Device UIIIer Tesl v7 4 (4OOVmax) __ H oflsal adjust Is also required. COMect to offset circuit. figure 2. "No! needed HR. Is less than 200 -see text. FIGURE 4. Measuring Supply Currents of Device Under Test. FIGURE 3. CMR Trim Circuit. v- v+ 4 7 Power Supply Out :Il!OOVrnax Ssnse - 2 380kQ 3IIOkn -I :Rs 6 /1 - I OptionaiLoad --- Ssnss COMection (see text) ·Not needed ff R. Is lass !han 20n ~ text. -:- FIGURE S. Measuring Power Supply Output Current. 3-42 Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Cuslomer Service at 1·800·548·6132 (USA Only) V. (:t200V max) 380kll "'..." As 250n C z - 410 20rnA Vs (:t200V max) (a) "Not 00_11 Rs is less than 20n -see taxt. 2 380kll 380k1l IIII 6 Vo a-tVto-5V -.-a... I I. Iz 4to20mA o - (b) As = ~ "Not needed HR. I. less than 20n -see taxt. 250n Vo a Wto5V III 15 ::::I Vs (:t200V max) (e) 8 a: Iiiz 5 - "Not n~ HR.is less than 20n -see text 41020rnA 2 380kIl 38Ok1l As 250Q 6 Vs (:t200V max) (eI) "Not n~ II Rs Is less than 20n -see taxt. FIGURE 6. Current to Voltage Converter. Burr-Brown Ie Data Book Supplement. Vol. 33b 3-43 For Immediate Assistance, Contact Your Local Salesperson In all cases, the sense resistor imbalances the input resistor matching of the INA 117, degrading its CMR. Also, the input impedance of the INAl17 loads Rs' causing gain error in the voltage-to-current conversion. Both of these errors can be easily corrected. The CMR error can be corrected with the addition of a compensation resistor,1\:, equal in value to Rs as shown in Figures 4, 5, and 6. If Rs is less than 200, the degradation in CMR is negligible and 1\: can be omitted. If Rs is larger than approximately 21en, trimming Rc may be required to achieve greater than 86dB CMR. This is because the actual INA1l7 input impedances have 1% typical mismatch. If Rs is more than approximately 1000, the gain error will be greater than the 0.02% specification of the INA 117. This gain error can be corrected by slightly increasing the value of Rs' The corrected value, Rs', can be calculated by- , ~ Rs· 3801en Example: For a I VIrnA transfer function, the nominal, uncorrected value for Rs would be lien. A slightly larger value, Rs' = 1002.60, compensates for the gain error due to loading. . The 3801en term in the equation for Rs' has a tolerance of ±25%, so sense resistors above approximately 4000 may require trimming to achieve gain accuracy better than 0.02%. Of course, if a buffer amplifier is added as shown in Figure 7, both inputs see a low source impedance, and the sense resistor is not loaded. As a result, there is no gain error or CMR degradation. The buffer amplifier can operate as a unity gain buffer or as an amplifier with noninverting gain. Gain added ahead of the INAll7 improves both CMR and signal-ta-noise. Added gain also allows a lower voltage drop across the sense resistor~ The OPAl013 is a good choice for the buffer amplifier since both its input and output can swing close to its negative power supply. = 3801en- Rs -15V v, +15V 4 2 Y, Y, -;!1V \0 +10V +15V ~V\o-36V Ground -;!OV \0 ~1V 7 380kn 380kQ 6 -15V • Or connect as buffer (R, • 0, omit R,I. -Vx Op amp power can be derived with voltage- dropping zener diode" -vx power Is ralaUveiy COOSIMI. IV,I ~ (5 \0 38V) + Vz e.g. "Vz = SOV then Vx= ~5V \o-86V f ........... ReguIa1ed power for op amp allows -Vx power 10 vary over wide range. Vx • -30V \0 -;!GOV O.OlpF or V- 4 V+ 7 6 FIGURE 7. Current Sensing with Input Buffer. 3-44 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1~BOO·54B·6132 Figure 8 shows very high input impedance buffer used to measure low leakage currents. Here, the buffer op amp is powered with an isolated, split-voltage power supply. Using an isolated power supply allows full ±200V common-mode input range. (USA Only) these resistors produces approximately 5SOnVr/Hz noise. The internal op amp contributes virtually no excess noise at frequencies above 100Hz. Many applications may be satisfied with less than the full 200kHz bandwidth of the INAII?ln these cases, the noise can be reduced with a low-pass filter on the output. The twopole filter shown in Figure 9 limits bandwidth to 1kHz and reduces noise by more than 15:1. Since the INAIl? has a I/f noise comer frequency of approximately 100Hz, a cutoff frequency below 100Hz will not further reduce noise. NOISE PERFORMANCE The noise perfonnance of the INAII? is dominated by the internal resistor network. The thermal or Johnson noise of ±200Vmax Isolated OCIOC Converter 9kn lkn t--VVV~~~~--1.~ ______-r__ '0; and 0, are each a 2N3904 transistor 3 380kn :cz - 12 III -a. I I. . .I 380kn Iz 6 3801<0 .... +15V -r~ ~ : ~ ..... ~ 2 .,.. o base-collector junction (emitter open). = = 21.11<0 8 5 III :E i FIGURE 8. Leakage Current Measurement Circuit. Inz v4 V. 2 - C. 380kn 0.02pF 380kn A, 6 V3 11.Okn 3 BUTT'ERWORTH 8 5 LOW-PASS I 200kHz 100kHz 10kHz 1kHz S100Hz'" See Application Bulletin AII-017 for other filters. OUTPUT NOISE (mVp-p) 1.8 1.1 0.35 0.11 0.05 R llkn llkn llkn llkn C NoFIltar 11.31<0 10apF 11.31<0 lnF 11.31<0 10nF 11.31<0 0.1"" C 20apF 2nF 20nF 0.2JIF NOTE: (1) Since the INAl17 has a 111 noise comer frequency of approximately 100Hz. bandwidth reducIIon below this frequency will not s1gnllicanUy reduce noise. FIGURE 9. Output Filter for Noise Reduction. Burr-Brown Ie Data Book Supplement, Vol. 33b 345 For Immediate Assistance, Contact Your Local Salesperson v+ v- 7 4 380Jcn 380kll GAIN It, 1\ (VN) (kQ1 (kQ1 112 1/4 115 1.05 3.18 4.22 20 20 20 FIGURE 10. Reducing Differential Gain. FIGURE II. Summing Vx in Output. (8) ReIer \0 ApplicatIon BuUe\In ABO()10 lor details. 6 V. 2 Rt Rz 3801cQ 3801cQ INA117 8 5 l00pF -::- flo 8 V, 5kQ 3 R7 101cQ Vour .Va -v. -Va 120. flo INA117 8 5 l00pF -::- flo R. 51cQ 10kll -::- (bl FIGURE 12. Common-Mode Voltage Monitoring. 346 Burr-Brown feData Book Supplement, Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) +9V 7 V. 2 380kn 380kn 7 Vcw Range'll +5OV 10 +200V (V. = :l9V) 25kn 6 ... :cz t- V, (a) Vo.V, -V, INA117 -3V > Va > -6V swap A. pins 2 and 3 lor +4V > Va > 3V. 4 - -:-'dV 12 1M +9V .--a... 7 I I. 380kn ~o-~~~~~~--~~-, 7 VeM Range = -12V 10 +200V (V•• :l9V) :IE 25kn 6 C z (b) 8 5 OV> Va > -6V swap A. pins 2 and 3 lor +4V > Va > OV. 4 1M 3.3V :IE -'dV 2 ::::a II: I;; - 380kn 380kn Z ~~~~~,N~-,--~--~~~ Vc. Range • :t200V (V. = :l9V) 25kn 3 5 380kn V, o-+-"'-:~...N\I'-+--- 'OJ Cl ~ 10 100 .,./ -(;=1 10 IN J 100 lk 10k lOOk 1M ,/ a 10M 10 100 Frequency (Hz) 1000 Gain (VN) IIII I ~" or " 0: " 'C 0 ::E 0 40 0 0 II -40 ....... G=11O 100 lk iii' 120 " U or " 0: 100 i en" " 1-...... . . . r-. r-. 80 60 r- " ............ ? ...... > G=10 niI !I/l" 40 ~ 0 0.. k III 100 lk 20 10 100 .. I ill E ~ ...... 10k - INPUT BIAS AND OFFSET CURRENT vs TEMPERATURE 20 15 " a; 10 'C 1' . . . ...... I;; z 0 8 5i " lOOk - IB ..... '" III .!!l ......" ..... r- '[ los .5 o 1M Frequency (Hz) Burr-Brown Ie Data Book Supplement. Vol. 33b -75 -50 -25 0 +25 +50 +75 I! Ii .s ±Vs ...... lk 100k 10k Source Resistance Imbalance (12) IG = 100 1'< ...... ...... ... = Z 1M lOOk IJ~IJoo: 1-- - o 10k POWER SUPPLY REJECTION vs FREQUENCY 140 o ........ Frequency (Hz) 0 r-... G=l I 10 :Eo l1U GJJ.lIJJW ..... C 0 E E ILUo!, -< r-.. > ..... r-.. ..... :-r-.. ..... R~G= 100 i(t r-.. r-.. I'-.... 1'-1>:-~liS ~O G=t I 80 I I. vs SOURCE RESISTANCE IMBALANCE 160 iii' 120 :Eo ....--.. S z COMMON· MODE REJECTION COMMON·MODE REJECTION vs FREQUENCY 160 +100 +125 Ambient Temperature (OC) 3-53 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) T. = +25'C. Vs = ±15V unless otherwise noted. SLEW RATE vs TEMPERATURE QUIESCENT CURRENT vs TEMPERATURE 3 «§. -- 2.8 ~ E 2.6 !!!:> (.) ~ 2.4 ~ ....- ~ 0.8 ~ " ~ 0.4 :,.....--- ~ / ,,/ -- Ou!put OpAmp 02 2.2 2.0 -75 / 1ii II: M 8 :,.....--- 0.6 o -50 -25 0 +25 +50 +75 +100' +125 Ambient TemperalUre ("C) -75 -50 -25 0 +25 +50 +75 +100 +125 Ambient TemperalUre ("C) INPUT· REFERRED NOISE G .1000 CURRENT LIMIT vs TEMPERATURE 35 « §. .~ ::J 30 ........... 25 E ~ :> (.) 20 15 -75 -50 '" -25 a.:",ut OpAmp r--.... 0 ""'- ""'+25 +50 +75 .......... ""'- +100 +125 Time (2s/ Division) Ambient Temperature ('C) G=l LARGE·SIGNAL TRANSIENT RESPONSE G = 1 Time (20)151 Division) Time (20)lSI Division) SMALL-5IGNAL TRANSIENT RESPONSE 3-54 Burr"Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) TYPICAL PERFORMANCE CURVES (CONT) T, = +25'C. v, = ±15V unless otherwise noted. SMALL-SIGNAL TRANSIENT RESPONSE G-l00 LARGE·SIGNAL TRANSIENT RESPONSE G = 100 o ":cz - Time (5115i Division) Time (10115i Division) APPLICATION INFORMATION Figure I shows the basic connections required for operation of the INAI20. Applications with noisy or high impedance power supply lines may require decoupling capacitors close to the device pins as shown. The differential input voltage is applied to pins 16 and 3. The output is referred to the output common reference terminal. pin 18. This terminal must have a low-impedance connection to ground. A resistance of In or greater in series with the common terminal could degrade common-mode rejection beyond the specified value. SETTING THE GAIN Gains of I. 10. 100 or 1000 can be configured by interconnecting the gain-set pins as shown in the table of Figure I. These pin-strapped gains provide best gain accuracy and drift because they are determined by the ratios of accurately trimmed and matched on-chip resistors. Digital gain control can be achieved using an analog multiplexer as shown in Figure 2. Since the switches are in series with the high impedance gain-sense connections. pins 4 and 15. their series resistance does not significantly affect gain error or drift. Gain error at G = I is slightly higher than with direct pin connections shown in Figure 1. The gain is selected with a two-bit address. Ao and A" The Multiplexer Enable control is directly connected to V+ since a logic "low" on this line would cause the input amplifiers to run open-loop. 'Other gains may be set by connecting an external resistor. Ro. as shown in Figure 3a. Gain accuracy using an external gain-setting resistor is a function of Ro and the internal 20kn resistors. The internal resistors are typically within ±0.2% of nominal value and their drift under ±8Oppm/"C. Inaccuracy and drift of Ro will contribute additional gain error and drift. Figure 3b snows an external gain-setting resistor connected in parallel with internal resistors. By forming a portion of the Burr-Brown Ie Data Book Supplement. Vol. 33b effective Ro with internal resistors. gain accuracy and drift can be somewhat improved. Connections available on the INAI20 allow all input stage gain-setting resistors to be provided externally. A custom precision resistor network could be connected to provide the highest accuracy and lowest gain drift for non-standard gains. Impedance of this external network should be made close to that of the internal network for best performance. OFFSET TRIMMING Many applications require no external offset voltage trimming. Figure 4 shows optional circuits for trimming offset voltage. Since the INAI20 has two amplification stages. the offset voltage is comprised of two componentsthe input stage offset and output stage offset. The input stage offset is equal to the combined offset of op amps AI and ~. This input stage offset dominates at high gain. When used in gains of 100 to 1000. it is often sufficient to adjust the input stage offset with a potentiometer connected to pins 6 and 7 as shown. Connect both inputs to ground and adjust for OV at the output. pin 1. Do not use pins 6 and 7 to trim offset voltage at G = I or to correct for offset in devices following the INAI20 since this can cause excessive offset voltage drift. At G = I. offset is dominated by the output stage. Output stage offset can be trimmed by applying a correction voltage at the output reference terminal. pin 18. Low impedance must be maintained at this node to preserve the high CMR of the INAI20. This is achieved by buffering the trim voltage with an op amp as shown. At intermediate gains it may be necessary to provide both input stage and output stage offset adjustments. Again. ground both inputs. Connect a jumper between pins 9 and II (temporarily connects the INAI20 in high gain) and adjust RI for OV at the output. pin 1. Then disconnect the jumper and adjust the output offset control for OV output. 3-55 IIII .-IlL.. Iz it o = ~ III :E i Inz - For Immediate Assistance, Contact Your Local Salesperson GAIN CONNECT 1 10 100' 1000 4-5 4-5 4-8 4-8 14-15 11-14-15 11-14 11-14 10-15 9-15 '-----.MI'--_---l1-'1c;;.8., Output Ground Reference -:- 'G = 100, shown at right 17 13 FIGURE 1. Basic Connection_ HI-S09A Multiptexer At, 7 16 A, 6 15 --=- 5 4 13 8 1 17 4 -f5V +VIN A, loa GAIN L L L H H H L 1 10 100 1000 H FIGURE 2_ Digital Gain ControL 3-56 Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) V+ RG= 40kO G-l 0 W :c 8 Ra= 8160 fo,G=50 Z Vo 10 11 14 15 16 (a) +VIN -V'N 13 17 12 IU .--a... V- I I. V+ 2 C z - 0 ... = R, Z IU Vo 44kn 2 G=l+ R,II4440 :) a: 1100 Ii; 500 Z FIGURE 3. External Gain-Setting Resistors. INPUT BIAS CURRENT RETURN PATH The input impedance of the INAl20 is extremely highapproximately 1010n. This does not mean, however, that no current flows in the input terminals. The input bias current of the INA120 is typically ±lOnA (it can be either polarity). High input impedance means that this input bias current changes very little with varying input voltage. Input circuitry must provide a path for this input bias current if the INA I 20 is to function. Figure 5 shows various provisions for an input bias current path. Without an appropriate current path. the inputs will float to a potential which Burr-Brown Ie Data Book Supplement, Vol. 33b exceeds the common-mode range of the INA120 and the input amplifiers will saturate. INPUT PROTECTION The inputs of the INA 120 are protected for input voltages up to 2V beyond the power supply voltages. If the input can exceed these conditions, input clamp diodes should be provided as shown in Figure 6. Rs may not be required if the input cannot supply more than 100rnA. If the input can supply larger currents, choose Rs according to the maximum source Voltage. limiting current to under 100rnA. 3-57 For Immediate Assistance, Contact Your Local Salesperson Input Stage Offset Adjustment for High Gains (see text). V,N + 1 100~A , 112 REF200 ~ 100~A 112REF200 17 VOutput Offset Adjustment for low gains (see text). V- FIGURE 4. Offset Adjustment Circuits. Microphone. Hydrophone etc. A, used to limit Input current to 100mA. Thermocouple V- FIGURE 6. Input Protection Circuit. ·bias current return. FIGURE 5. Providing an Input Bias Current Path. 3-58 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) r -_ _--.:1:.:::0o:.0V-=--....:6~ REF102 o '":cz - K ISA TYPE MATERIAL E Chromel SEEBECK COEFFICIENT (IlVI"C) R, (R,= 1000) R, (R, + R, =10011) 58.5 3.48k 56.2k Constantan J 50.2 4.12k 64.9k K Chromel Alumel 39.4 5.23k 80.6k T Copper 38.0 5.49k 84.5k Iron Constantan NOTES: (1) -2.1mVI"C at 200!lA. (2) R, provides down·scale bum-out Indication. 12 III -.-.. Constantan I I. FIGURE 7. Thennocouple Amplifier With Cold Junction Compensation. II. Iz V+ o - ... = Z III :E i I;; - z V2 2200 3 FIGURE 8. Guard Drive Circuit. Burr-Brown Ie Data Book Supplement, Vol. 33b 3-59 For Immediate Assistance, Contact Your Local Salesperson BURR-BROWN@ PGA202/203 IEalEalI Digitally-Controlled Programmable-Gain INSTRUMENTATION AMPLIFIER FEATURES APPLICATIONS • DIGITALLY PROGRAMMABLE GAINS: DECADE MODEL-PGA202 GAINS OF 1, 10, 100, 1000 BINARY MODEL-PGA203 GAINS OF 1, 2, 4, 8 • DATA ACQUISITION SYSTEMS • AUTO-RANGING CIRCUITS • DYNAMIC RANGE EXPANSION • LOW BIAS CURRENT: 50pA max • TEST EQUIPMENT • REMOTE INSTRUMENTATION • FAST SETTLING: 2!lS to 0.01% • LOW NON-LINEARITY: 0.012% max • HIGH CMRR: 80dB min • NEW TRANSCONDUCTANCE CIRCUITRY • LOW COST DESCRIPTION The PGA202 is a monolithic instrumentation amplifier with digitally controlled gains of I, 10, 100 and 1000. The PGA203 provides gains of I, 2, 4, and 8. Both have TIL or CMOS-compatible inputs for easy microprocessor interface. Both have FET inputs and a new transconductance circuitry that keeps the bandwidth nearly constant with gain. Gain and offsets are laser trimmed to allow use without any external components. Both amplifiers are available in ceramic or plastic packages. The ceramic package is specified over the full industrial temperature range while the plastic package covers the commercial range. Front End and Logic Circuits t--+-~'N\,.--.--t Ao A, Covered by Digital Common u.s. PATENT #4.883.422 International Airport industrial Park • ...Dlng Address: PO Box 11400 • TUcson, AZ B5734 • Street Add"SS: 6730 S. TUcson BlVd. • TUcson, AZ 85706 Tol:(602)746-1111 • Twx: 91H52·1111 • cable:BBRCORP • Telex:Q66.6491 • FAX: (602) 889-1510 • ImmedIateProductlnfo:(800)54H132 PDS·tOO6A 3-60 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL At +25"C. Vc. =±15V unless otherwise noted. fill PARAMETER GAIN Error 121 CONDITION G < 1000 G = 1000 G < 1000 G = 1000 G < 100 G = 100 G = 1000 Nonlinearity Drift vs Temperature Stability vs Time RATED OUTPUT Voltage Over Specified Temperature Current Impedance ANALOG INPUTS Common-Mode Range Abolule Max Voltage '" Impedance. Differential Common-Mode OFFSET VOLTAGE (Rn) Initial Offset at 25°C 141 MIN Iiourl S5mA See Typical Perf. Curve IVOUT Is 10V ±10 ±5 ±10 MAX 0.05 0.1 0.005 0.01 3 10 25 0.25 1 0.015 0.05 10 100 200 ±13 G= 1 G = 10 G = 100 G = 1000 SO 86 ~~. ±(0.3 + 3/G) ±(2 + 10/G) 25 10+ 250/G ±(1 + 10/G) ±(10 + 80/G) 10 640 5 320 50 3200 25 1600 1.7 12 ~~:;A~~~110 10Hz Density at ,., 32 400 G < 1000 G = 1000 G < 1000 G = 1000 Full Power Bandwidth Slew Rate Settling Time (0.01%'" Overload Recovery TIme 10 In g~:~A~o~~~~ange Input Low Threshold ,., !~~~~ ~~ Current Voltage Input I Current POWER SUPPLY Rated Voltage Voltage Range Quiescent Current RANGE Specification Operating ~:rage G < 1000 G = 1000 G < 1000 G = tOOO MAX ··· ·· ·· ·· · · · UNITS 'Yo % % 'Yo ppml"C ppml'C 'Yo/Month ·· · ·· ·· ·· · · I ±(1+ 20/G) · ·· ·· ··· · ~gll~~ mV IlViMonth IlVN ~~ dB dB dB dB kHz kHz kHz kHz ·· ·· ±15 · ±IS · 85 125 150 ·· · 6.5 ·· · · · · · · · 0 -25 -40 · VII'S I'S I'S I'S I'S ·· · · I1A · V V mA 70 85 100 'c V V ~ 'C 'C 'CIW • Same as the PGA202l203AG NOTES: (I) All specifications apply to both the PGA202 andlhe PGA203. Values given foragaln of 10 are the same for again of Sand other values may be interpolated. (2) Measured with a 10k load. (3) The analog inputs are Internally diode clamped. (4) Adjustable to zero. (5) VNO."RT" (5) Threshold voltages are referenced to Digital Common. (7) From input change or gain change. Burr-Brown Ie Data Book Supplement, Vol.33b A. IW -.-.. I I. A. pA pA nVY~ ·· ·· a V V · ·· 15 2 n IlVI'C ~~~ ~ V V mA ±10 · ±(0.5+ 5/G) ±(5+ 40/G) · ·· TVP nVY~ 10 100 MIN · 2.4 -25 -55 -65 ·· ·· · Vcc - B O.S 10 ±6 · · ·· · 1000 250 400 100 20 2 10 5 10 -Vee 0.15 0.5 0.012 0.025 5 50 100 · ~gg/~ 100 110 120 120 INPUT NOISE Noise Voltage 0.1 to 10Hz Noise Density at 10kHz '" MAX 0.05 0.08 0.005 0.01 · 1611i tNPUT BIAS CURRENT Initial Bias Current: at 25'C at 85'C Initial Offset Current: at 25'C at 85'C COMMON MODE n~~~ ..u .. :AnO TVP · · ±Vcc 10SV"S15 DYNAMIC Frequency Response MIN · ±12 ±9 ±10 0.5 No Damage vs Temperature Offset vs TIme Offset vs Supply TVP =..J (VNNPUT)' + (VNOU,",,,/Gain)'. 3-61 :IE CC Z 0 - = :IE Z W ::t II: IiiZ - For Immediate Assistance, Contact Your Loca/Salesperson MECHANICAL G Package -l4-Pln Plaatlc Package ,{::::::U I' D . "I DIM A . A, B B, C D E Plnl/ E, 8' SA L "'aP" Q, sm MILUMETERS INCHES MIN MAX MIN MAX .120 .160 3.048 4.064 .015 .065 .381 1.651 .014 .020 .355 .508 .065 1.270 1.651 .050 .008 .012 .203 .304 .745 .770 18.923 19.558 .300 .325 7.620 8.255 .240 260 6.096 6.604 .100 BASIC 2.540 BASIC 7.620 BASIC .300 BASIC .125 .150 3.175 3.810 .030 0 .762 0 C!' 15 C!' 15' .050 1.270 .050 .065 1.270 2.159 .065 .090 1.651 2286 NOTE: Leads In true posItion withIn 0.01" (O.25mm) R at MMC at seating plane • (1) a, and eA apply In zona L, when unIt Is Installad. (2) Not per JEDEC. G Package -l4-Pln Hermetic DIP DIM A C D F G H J K L M N INCHES MIN MAX .670 .7tO .065 .170 .015 .021 .045 .060 .100 BASIC .070 .025 .008 .012 .120 240 .300 BASIC lC!' .009 .060 MIWMETERS MIN MAX 17.02 18.03 1.65 4.32 0.38 0.53 1.14 1.52 2.54 BASIC 0.64 1.78 020 0.30 3.05 6.10 7.62 BASIC 10' 1.52 0.23 NOTE: Leads In true pos/tion withIn 0.01" (O.25mm) R at MMC at seating plane. PIn numbers shown for reference only.. Numbers may nol . be marked on package . ORDERING INFORMATION GAINS PACKAGE TEMPERATURE RANGE OFFSET VOLTAGE MAX (mV) PGA202KP PGA202AG PGA202BG 1,10,100,1000 1,10,100,1000 1,10,100,1000 Plastic DIP Ceramic DIP Ceramic DIP 0'CIo+70'C -25'C to +85'C -25'C to +85'C ±(1 +20IG) ±(1 + 10IG) ±(O.5+ 5IG) PGA203KP PGA203AG PGA203BG 1,2,4,8 1,2,4,8 1,2,4,8 Plastic DIP Ceramic DIP Ceramic DIP O'Cto +70'C -25'C to +85'C -25'C to +B5'C ±(1 + 20/G) ±(1 + 10/G) ±(0.5 + 5IG) MODEL PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS DigItal Common A, -Vee +Vcc V= VOUTSense Filter A Vo.Adjust -V'N 3-62 RlterB Supply Voltage .......................................................................; ........... ±18V Intemal Power Dissipation ..................................................; .......... 750mW Analog and DIgital Inputs ...................................................... ±(Vcc + 0.5V) Operating Temperature Range: G Package ............................................................... -55'C to +l25'C P Package ................................................................-40'C 10 +100'0 Lead Temperature (soldering, lOs) .................................................. 300·C Output Short Circuit Duration ...............................................~... Continuous Junction Temperatura ....................................................................... 175'C 9 .. Ves Adjust +VIN Burr-Brown Ie Data Book Supplement. Vol.33b Dr, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES T, = +25"C. v, = ±15V unless oillerwise noted. GAIN YS FREQUENCY GAIN ERROR YS FREQUENCY 80 60 ~ 40 \ 1i'i" :g. c:: 'iii Cl 20 ..... ~ 0 -20 -40 10 103 10' 10' 10' 10· 107 1~ 10 10· 10" Frequency (Hz) Frequency (Hz) .. IIII CMRR vs FREQUENCY JJ 120 i£ 80 ~ 40 III 1 G= O( !J' p ... G_l0 II: ~~U-~~~ww~~~~~~~ 1 10 1~ 1~ 1~ 1~ ~ z o r- - G=l ... = o -40 -itI I. PSRR vs FREQUENCY 160 Z -40 1 1~ 10 103 10' III 10· I! Frequency (Hz) Frequency (Hz) i INPUT NOISE vs FREQUENCY 10 Burr~Brown Ie Data 102 103 Frequency (Hz) Inz - OUTPUT NOISE YS FREQUENCY 10' 10' Book Supplement, Vol. 33b 10 10' 103 10' 10· Frequency (Hz) 3-63 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) TA = +25'C. V•• ±15V unless otherwise noted. BIAS CURRENT va POWER SUPPLY QUIESCENT CURRENT va POWER SUPPLY 10 r----,----.,---.. . . ---.... 12 <" g ..9 6~--~====~===t==~ 4 r------+------+-----~--'-----~ ----- 11 8 r------+------+-----~------~ i I i 2 ~-----+------+-----~------, 10 9 ~ ~ 8 7 o o 6~--~----~---~-----~ 12 15 18 OUTPUT SWING va POWER SUPPLY INPUT RANGE vs POWER SUPPLY ./ 8 4 V / / 15 / TA • +25'C / 5 V ,./ V 12 9 15 18 6 15 12 9 Power Supply (±V) SETTLING TIME va FILTER CAPACITOR OUTPUT SWING vs LOAD 10 10 I o / 8 ~ V /' 'iii' .. f a 6 E 1= 4 /' UJ 2 -4 500 1000 Load (0) 18 Power Supply (:tV) 15 3-64 / TA =_25°C o 6 o " ./ 10 o 5 18 Power Supply (±V) 16 12 15 12 9 6 Power Supply (:tV) 1500 2000 o ./ V 10 20 Filter Capacitor (pF) 30 Burr-Brown Ie Data Book Supplement. Vol. 33b Dr, Call Customer Service at 1·800·548·6132 (USA Dnly) TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, Vs = ±15V unless otherwise noted. QUIESCENT CURRENT vs TEMPERATURE INPUT BIAS CURRENT vs TEMPERATURE 10 10' 8 / 6 <" ,/ £4 ..., V 2 0 -50 -25 o 25 75 50 100 -50 -,25 o Temperature ('C) 25 50 75 100 Temperature ('C) IIII CURRENT LlMITv. TEMPERATURE 20 .--.. I I. SLEW RATE vs TEMPERATURE 25 25 I'--.. ............. ............... ~ I'--..r--. IlL. - 20 fil -...... ............... a: ~ 15 15 ~ - Z o - = I- 10 -50 -25 o 25 50 75 100 10 -50 Z o 25 50 Temperature ('C) Temperature ('C) OUTPUT SWING vs TEMPERATURE LARGE SIGNAL RESPONSE 75 100 12 5 10 ~ Inz - V ./ /' 8 6 -50 o 25 50 75 100 Temperature ('C) Burr-Brown Ie Data Book Supplement, Vol. 33b :I i 14 ~ III lJlS/Oiv 3-65 For Immediate Assistance, Contact Your Local Salesperson TY~CALPERFORMANCE CURVES (CONT) T, = +25'C. Vee =±15V unless otheowlse nOled. SMALL SIGNAL RESPONSE lps/Dlv FIGURE I. Basic Circuit Connections. DISCUSSION OF PERFORMANCE A simplified diagmm of the PGA202/203 is shown on the first· page. The design consists of a digitally-controlled, differential transconductance front end stage using precision FET buffers and the classical transimpedance output stage. Gain switching is accomplished with a novel current steering technique that allows for fast settling when changing gains. The result is a high performance. programmable instrumentation amplifier with excellent speed and gain accuracy. The input stage uses a new circuit topology that includes FET buffers to give extremely low input bias currents. The differential input voltage is converted into a differential output current with the transconductance gain selected by steering the input stage bias current between four identical input stages differing only in the value of the gain setting resistor. Each input stage is individually laser-trimmed for input offset. offset drift and gain. OFFSET ADJUSTMENT Figure 2 shows the offset adjustment circuits for the PGA202/ 203. The input offset and the output offset are both sepamtely adjustable. Notice that because the PGA202/203 change between four different input stages to change gain. the input offset voltage will change slightly with gain. For systems using computer autozeroing techniques. neither offset nor drift is a major concern. but it should be noted that since the input offset does change with gain. these systems should perform an autozero cycle after each gain change for optimum performance. In the output offset adjustment circuit. the choice of the buffering op-amp is very important. The op-amp needs to have low output impedance and a wide bandwidth to maintain full accumcy over the entire frequency range of the PGA202/203. For these reasons we recommend the OPA602 as an excellent choice for this application. The output stage is a differential transimpedance amplifier. Unlike the classical difference amplifier output stage. the common mode rejection is not limited by the resister matching. However. the output resistors are laser-trimmed to help minimize the output offset and drift. BASIC CONNECTIONS Figure I shows the proper connection~ for power supply and signal. The power supplies should be decoupled with II1F tantalum capacitors placed as close to the amplifier as possible for maximum performance. To avoid gain and CMR errors introduced by the external components. you should connect the grounds as indicated. Any resistance in the sense line (pin 11) or the VREF line (pin 4) will lead to a gain error. so these lines should be kept as short as possible. Also to maintain stability. avoid capacitance from the output to the input or the offset adjust pins. 3-66 +Vcc V,N vour 10kO lOOkO 1000 -Vee FIGURE 2. Offset Adjustment Circuits. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) GAIN SELECTION OUTPUT SENSE Gain selection is accomplished by the application of a 2-bit digital word to the gain select inputs. Table I shows the gains for the different possible values of the digital input word. The logic inputs are referred to their own separate digital common pin, which can be connected to any voltage between the minus supply and 8V below the positive supply. The gains are all internally trimmed to an initial accuracy of better than 0.1 %, so no external gain adjustment is required. However, if necessary the gains can be increased by the use of an external attenuator around the output stage as shown in Figure 3. Recommended resistor values for certain selected output gains are given in Table II. An output sense has been provided to allow greater accuracy in connecting the load. By attaching this feedback point to the load at the load site, IR drops due to the load currents are eliminated since they are inside the feedback loop. Proper connection is shown in Figure 1. When more current is required, a power booster can be placed in the feedback loop as shown in Figure 4. Buffer errors are minimized by the loop gain of the output amplifier. PGA202 A, 0 0 1 1 "0 1 0 1 >--+---<::> vour PGA203 GAIN ERROR 1 10 100 1000 0.05% GAIN ERROR 1 0.05% 0.05% 0.05% 0.05% 0.05% 2 0.05% 0.10% 4 8 I!au TABLE I. Software Gain Selection. OUTPUT GAIN R, R, 2 5kll 2kll 1kll 5kll Bkll 9kll 5 10 TABLE II. Output Stage Gain Control. >-=*-_--0 Vour R, ii: FIGURE 4. Current Boosting the Output. i OUTPUT FILTERING The summing nodes of the output amplifier have also been made available to allow for output filtering. By placing matched capacitors in parallel with the existing internal capacitors as shown in figure 5, you can lower the frequency response of the output amplifier. This will reduce the noise of the amplifier, at the cost of a slower response. The nominal frequency responses for some selected values of capacitor are shown in Table 3. ~ z o ...z = au III i I;; z - FIGURE 3. Gain Increase with Buffered Attenuator. COMMON-MODE INPUT RANGE Unlike the classical three op-amp type of circuit, the· input common-mode range of the PGA202/203 does not depend on the differential input and the gain. In the standard three op-amp circuit, the input common-mode signal must be kept below the maximum output voltage of the input amplifier minus 1/2 the final output voltage. If, for example, these amplifiers can swing ±12V, then to get 12V at the output you must restrict the input common-mode voltage to only 6V. The circuitry of the PGA202/203 is such that the commonmode input range applies to either input pin regardless of the output voltage. FIGURE 5. Output Filtering. CUTOFF FREQUENCY C,ANDC, 1MHz 100kHz 10kHz None 47pF 525pF TABLE 3. Output Frequency vs Filter Capacitors. Burr-Brown Ie Data Book Supplement, Vol. 33b 3-67 For Immediate Assistance, Contact Your Local Salesperson INPUT CHARACTERISTICS Because the PGA202/203 have FET inputs, the bilis currents drawn through input source resistors have a negligible effect on DC accuracy. The picoamp currents produce no more than microvolts through megohm sources. The inputs are also internally diode clamped to the supplies. Thus, input filtering and input series protection are easily achievable. I I I A return path for the input bias currents must always be provided to prevent the charging of any stray capacitance. Otherwise the amplifier could wander and saturate. A lMQ to IOMQ resistor from the input to common will return floating sources such as thermocouples and AC-coupled inputs (see Applications Section, Figures 8 and 9.) I I I :~VOUT I I I I 102 . I I I I DYNAMIC PERFORMANCE The PGA202 and the PGA203 are fast-settling FEr input programmable gain instrumentation amplifiers. Careful attention to minimize stray capacitance is necessary to achieve specified performance. High source resistance will interact with the input capacitance to reduce speed and overall bandwidth. Also to maintain stability, avoid capacitance from the output to the input or the offset adjust pins. FIGURE 6. Isolated Programmable Gain Instrumentation Amplifier. Applications with balanced source impedance will provide the best performance. In some applications, mismatched source impedances may be required. If the impedance in the negative input exceeds that in the positive input, stray capacitance from the output will create a net negative feedback and improve the stability of the circuit. If, however, the impedance in the positive input is greater, then the feedback due to stray capacitance will be positive and instability may result. The degree of positive feedback will, of course, depend on the source impedance imbalance as well as the board layout and the operating gain. The addition of a small bypass capacitor of about 5 to 50pF directly across the input terminals of the PGIA will generally eliminate any instability arising from these stray capacitances. CMR errors due to the source imbalance will also be reduced by the addition of this capacitor. The PGA202 and the PGA203 are designed for fast settling in response to changes in either the input voltage or the gain. The bandwidth and the settling times are mostly determined by the output stage and are therefore independent of gain, except at the highest gain of the PGA202 where other factors in the input stage begin to dominate. 1-+-+----._0 VREF 10V fit 10kO R2 lkO FIGURE 7. Auto Gain Ranging. APPLICATIONS In addition to general purpose applications, the PGA202/203 are designed to handle two important and demanding classes of appiications: inputs with high source impedances, and rapid scanning data acquisition systems requiring fast settling time. Because the user has access to output sense and , output common pins, current sources can also be constructed with a minimum-of external components. Some basic application circuits are shown in Figures 6 through 14. lpF 0-----1 t--.-----"i vlN lpF 0-----1 H-_.----.!...I lMO Gain Control FIGURE 8. AC-Coupled Differential Amplifier for Frequencies above O.16Hz. 3-68 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) FIGURE 9. Floating Source Programmable Gain Instrumentation Amplifier. FIGURE 11. Programable Differential In/Differential Out Amplifier. OPA27 ! R VIN R Gain Control RL VOUT 2000 :IE 10kO lOUT = (AV,,)(G)(1130k + 1/R) FIGURE 10. Programmable Current Source. .--A... I I. 10kO \ lOUT IIU c z o OPA27 - Gain Control FIGURE 12. Low Noise Differential Amplifier with Gains of 100, 200, 400, 800. ... = Z IU :E i V'N A, A, A, A, GAIN 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 1 2 4 8 10 20 40 80 100 200 400 800 1000 2000 4000 8000 0 1 0 1 0 1 0 1 0 1 0 1 i- FIGURE 13. Cascaded Amplifiers. Burr-Brown Ie Data Book Supplement, Vol. 33b 3-69 For Immediate Assistance, Contact Your Local Salesperson Differential Multiplexer • • Burr-Brown HI-507A Sampling AID Converter ADS808 DATA Bus • • MicroProcessor Control Bus FIGURE 14. 8-Channel Differential Data Acquisition System. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) BURR-BROWN@ RCV420 I~~I Precision 4mA to 20mA CURRENTLOOPRECEWER FEATURES APPLICATIONS • COMPLETE 4-20mA TO O·5V CONVERSION • INTERNAL SENSE RESISTORS • PROCESS CONTROL • INDUSTRIAL CONTROL • PRECISION 10V REFERENCE • FACTORY AUTOMATION • BUlLT·IN LEVEL·SHIFTING • ±40V COMMON·MODE INPUT RANGE • DATA ACQUISITION • SCADA • 0.1% OVERALL CONVERSION ACCURACY • RTUs • HIGH NOISE IMMUNITY: 86dB CMR 12 w • ESD • MACHINE MONITORING DESCRIPTION The RCV420 is a precision current·loop receiver de· signed to convert a 4-20mA input signal into a 05V output signal. As a monolithic circuit. it offers high reliability at low cost. The circuit consists of a premium grade operational amplifier. an on-chip precision resistor network. and a precision lOY reference. The RCV420 features 0.1 % overall conversion accuracy. 86dB CMR._ and ±40V common-mode input range. The circuit introduces only a 1.5V drop at full scale. which is useful in loops containing extra instrument burdens or in intrinsically safe applications where +Vee transmitter compliance voltage is at a premium. The lOY reference provides a precise lOY output with a typical drift of 5ppm!'C. The RCV420 is completely self·contained and offers a highly versatile function. No adjustments are needed for gain. offset. or CMR. This provides three important advantages over discrete. board·level designs: 1) lower initial design cost, 2) lower manufacturing cost, and 3) easy, cost-effective field repair of a precision cir· cuit. Rei In -vee Rev I. Rev Out '"'"--.,-....... . , 7 Ref Noise Reduction Rev Com Rei Com InternatiOnat Airport Induslrlal Park • MaHing Address: PO Box 11400 Tol:(602)746-1111 • Twx: 91Q.952-1111 • Cable:BBRCORP • • TUcson. AZ 85734 • Slreet Address: 6730 S. Tucson Blvd. • Tucson. AZ 85706 Telex:Q66.6491 • FAX: (602) 741-4395 • Immediate Productlnlo: (BOO) 54H132 PDS-837B Burr~Brown Ie Data Book Supplement. Vol. 33b 3·71 .-ii:A-.. S Z o :-; = w :E i I;; z - For Immed/ate Ass/rtance, Contact Your Local Sal"perron SPECIFICATIONS ELECTRICAL T a +25·C and ±Vcc = ±15V unless otherwise noted. RCV420AG CHARACTERlsnCS MIN GAIN Initial Error vsTemp Nonlinearity'" OUlPUT Rated Voltage (10 =+IQmA. -5mA) Rated Current (Eo = 10V) Impedance (Differential) Current Umlt (To Common) Capacitive Load (Stable Operation) INPUT Sense Resistance Input Impedance (Common Mode) Common Mode Voltage CMR~' vs Temp (DC) (T. = T.... to T....,.) AC60Hz OFFSET VOLTAGE (RYO) '" Initial vsTemp vs Supply (±11.4V to ±18V) vsTlme 10 +10.-5 MAX 0.3125 0.025 15 0.0002 0.1 50 0.002 74.25 75 2D0 72 66 80 76 74 10 90 200 OUlPUT NOfSE VOLTAGE fe =0.1 Hz to 10Hz fo= 10kHz 50 800 DYNAMIC RESPONSE Gain Bandwidth Full Power Bandwidth Slew Rate Seltllng ilme (0.01 %) 150 30 1.5 10 9.995 POWER SUPPLY Rated Voltage Range'" Ouiescent Current (Va =OV) TEMPERATURE RANGE SpecHlcation Operation Storage . SpeclflCat,on same as RCV420AG. 1 50 80 0.05 50 10.005 ±4 5 0.0002 0.0002 15 5 vsTemp~' 86 80 2D +10.-2 ±15 ±11.4 3 -2q -55 -65 · ±18 4 +85 +125 +150 · · ·· · RCV420KP MAX ·· · · · 70 90 94 ·· · ·· ·· ·· ·· ·· ··· · 25 · 0.025 25 · ·· · ·· · ·· ·· · ··· · 0.025 MAX 0.15 · · 9.99 · ·· ·· · · · 0 -25 -40 ·· ·· ·· ··· · · · 0.075 · VirnA %olspan ppml"C %01 span a kn V dB dB dB mV IJ.VfOC dB ·IJ.V/mo %ofspan ppm of spanl"C 1J.Vp-...e. nVNHz kHz kHz V/IJ.S IJ.S 10.01 V % ppmI"C %/V %lrnA ppmlkHr IJ.Vp-p mA ·· V V rnA +70 ·C ·C ·C · · UNITS V rnA II rnA pF ·· · · TYP 0.05 · · 94 MIN 0.05 25 ·· ·· 75.75 eo TYP · ·· ±40 0.01 10 vs Supply (±II.4V to ±18V) vs Output Current (10 .0 to +10mA) vsilme Noise (0.1 Hz to 10Hz) Output Current MIN ·· 12 0.01 +49 .. -13 1000 ZERO ERROR'" Initial vsTemp VOLTAGE REFERENCE Initial Trim Range(5' RCV420BG TYP +85 +85 NOTES: (1) Nonlinearity is the max peak deviation from best fit straight line. (2) With 0 source Impedance on Rev Com pin. (3) Referred to output with alllnpulS grounded including Ref In. (4) With 4rnA Input signal and Voltage Reference connected (includes Vos' Gatn Error. and Voltage Reference Errors). (5) External trim sfighUy effects drift. (6) The "box method" Is used 10 specify output voltage drift vs temperature. (7) t" Ref = SmA. 10 Rev = 2mA. 3-72 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) MECHANICAL G Package -Iii-Pin Hermetic DIP ~~[']-j F-"~1) --N. H_I,__ ~ ,E:ng ,_ L-' \...--M ~Plnl ., II- D J DIM A C D F G H J K L M N INCHES MAX MIN .790 .Bl0 .105 .170 .015 .021 .060 .048 .100 BASIC .030 .070 .012 .00B .120 .240 .300 BASIC 10' .025 .060 MILUMETERS MIN MAX 20.07 20.57 4.32 2.67 O.3B 0.53 1.22 1.52 2.54 BASIC 1.78 0.76 0.30 0.20 6.10 3.05 7.62 BASIC 10' 0.64 1.52 NOTE: Leads In true position within 0.01· (O.25mm) Rat MMC at seating plane. Pin numbers shown for reference only. Numbers may not be marked on package. INCHES MIN MAX .740 .800 .725 .785 .230 290 .200 .250 .120 .200 .Ot5 .023 .030 .070 .100 BASIC 020 .050 .008 .015 .070 .150 .300 BASIC 0' IS' .010 .030 .025 .050 MILUMETERS MIN MAX 18.80 20.32 18.42 19.94 5.85 7.38 5.09 6.36 3.05 5.09 0.38 0.59 0.76 1.78 2.54 BASIC 0.51T 127 0.20 0.38 1.78 3.82 7.63 BASIC IS' 0' 025 0.76 1.27 0.64 NOTE: Leads In true poSition within 0.010· (0.25mm) Rat MMC at sealing plane. \ G Plane P Package -Iii-Pin Plastic DIP DIM A A. B B. C D F G H J K L M N p IIII -:::i I I. '~" Z = = o III PIN CONFIGURATION -In I IE ABSOLUTE MAXIMUM RATINGS 16 +Vcc Revf. RcvOut Supply ••••••••••••••••••••.••••••.•••••.•.••.•...••..••••.••......................................... cJ22V Input Current. Continuous .................................................................40mA Input Current Momentary. 0.1 s .............................. 250mA. 1% Duty Cycle Common Mode Input Voltage. Continuous ........................................ ±40V Lead Temperature (soldering. lOS) ................................................ +300'C Oulput Short Circuit to Common (Rev and Ref) ....................... Continuous Rev Com Ref Com Ref In Ref Out Ref Noise Reduction 7 Reff. RefTrim 8 NC Burr-Brown Ie Data Book Supplement. Vol. 33b 3-73 i r;; z - For Immediate Assistance, Contact Your Local Salesperson ORDERING INFORMATION MODEL PERFORMANCE GRADE PACKAGE RCV420AG RCV420BG RCV420KP -25'C to +S5'C -25'C to +85'C O°C to +70°C tS·Pln Hermetic DIP tS·Pln Hermetic DIP tS·Pln Plastic DIP TYPICAL PERFORMANCE CURVES T,,= +25°C, ±Vcc = 15V unless otherwise noted. STEP RESPONSE NO LOAD SMALL SIGNAL RESPQNSE NQLOAD SMALL SIGNAL RESPONSE RL =~. CL = tOOOpF POWER·SUPPLY REJECTION vs FREQUENCY COMMON·MODE REJECTION vs FREQUENCY -100 -94 m -so -100 11111111I l' ruimr -80 '\ RCV420AG, P ~ a: ::E 0 -60 -90 iil +Vcc (f) -60 i'- -40 "Vee '\ '\ -40 10 tOO lk Frequency (Hz) 3-74 I'i'-j\ :e. a: a. ii t-f'; 10k tOOk 10 100 lk tOk lOOk Frequency (Hz) Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) THEORY OF OPERATION Refer to the figure on the first page. For 0-5V output with 420mA input, the required transimpedance of the circuit is: VOUT/IIN = 5V/16mA = O.3125V/mA. To achieve the desired output levels, OV for 4mA and 5V for 20mA, the output of the amplifier must be offset by an amount: Vos =-(4mA)(0.3125V/mA) = -1.25V. The input current signal is connected to either +In or -In, depending on the polarity of the signal, and returned to ground through the center tap, <;. The balanced input-two matched 750 sense resistors, Rs-provides maximum rejection of common-mode voltage signals on <; and true differential current-to-voltage conversion. The sense resistors convert the input current signal into a proportional voltage, which is amplified by the differential amplifier. The voltage gain of the amplifier is: AD = 5V1(16mA)(750) = 4.1667VN. The tee network in the feedback path of the amplifier provides a summing junction used to genemte the required-l.25V offset voltage. The input resistor network provides highinput impedance and attenuates common-mode input voltages to levels suitable for the operational amplifier's commonmode signal capabilities. shifting. If the Ref In pin is not used for level shifting, then it must be grounded to maintain high CMR. GAIN AND OFFSET ADJUSTMENT Figure 2 shows the circuit for adjusting the RCV420 gain. Increasing the gain of the RCV420 is accomplished by inserting a small resistor in the feedback path of the amplifier. Increasing the gain using this technique results in CMR degradation, and therefore, gain adjustments should be kept as small as possible. For example, a 1% increase in gain is typically realized with a 1250 resistor, which degmdes CMR by about 6dB. A decrease in gain can be achieved by placing matched resistors in pamllel with the sense resistors, also shown in Figure 2. The adjusted gain is given by the following expression VOUT/IIN = 0.3125 x Rx/(Rx + Rs)' A 1% decrease in gain can be achieved with a 7.5kO resistor. It is important to match the parallel resistance on each sense resistor to maintain high CMR. The TCR mismatch between the two external resistors will effect gain error drift and CMR drift. There are two methods for nulling the RCV420 output offset voltage. The first method applies to applications using the internal 10V reference for level shifting. For these applica- BASIC POWER SUPPLY AND SIGNAL CONNECTIONS Figure 1 shows the proper connections for power supply and signal. Both supplies should be decoupled with I J.lF tantalum capacitors as close to the amplifier as possible. To avoid gain and CMR errors introduced by the external circuit, connect grounds as indicated, being sure to minimize ground resistance. The input signal should be connected to either +In or -In, depending on its polarity, and returned to ground through the center tap, <;. The output of the voltage reference, Ref Out, should be connected to Ref In for the necessary level 2 .--.. II . .I A. ~ Z :1:0.5% Gain Adjustment -In Cr 10kll' AevOul +In 10ka' o - ... = Z II • Typical values. See lext. ::& ::) II: J;; FIGURE 2. Optional Gain Adjustment. Z lIN - 12 +In 3 4-20mA Cr 2 -In 1 Aelln .--_ _ _ _ _-1-15.., Aev '. As AevOut AelOut As 10 L-...,..._~-, 13 Aev Com 8 7 VOUT (CHiV) Aella AelT~m Ael Noise Aeductlon 5 Ael Com FIGURE I. Basic Power Supply and Signal Connections. Burr-Brown Ie Data Book Supplement, Vol. 33b 3-75 For Immediate Assistance, Contact Your Local Salesperson tions, the voltage reference output trim procedure can be used to null offset errors at the output of the RCV420. The voltage reference trim circuit is discussed under "Voltage Reference." When the voltage reference is not used for level shifting or when large offset adjustments are required, the circuit in Figure 3 can be used for offset adjustment. A low impedance on the Rcv Com pin is required to maintain high CMR. ZERO ADJUSTMENT Level shifting the RCV420 output voltage can be achieved using either the Ref In pin or the Rcv Com pin. The disadvantage of using the Ref In pin is that there is an 8:1 voltage attenuation from this pin to the output of the RCV420. Thus, use the Rev Com pin for large offsets, because the voltage on this pin is seen directly at the output. Figure 4 shows the circuit used to level-shift the output of the RCV420 using the +15VDC 100kfl I---<..-INv-< 100kn Rev Com pin. It is important to use a low-output impedance amplifier to maintain high CMR. With this method of zero adjustment, the RefIn pin must be conneeted to the Rev Com pin. MAINTAINING COMMON-MODE REJECTION Two factors are important in maintaining high CMR: (1) resistor matching and tracking (the internal resistor network does this) and (2) source impedance. CMR depends on the accurate matching of several resistor ratios. The high accuracies needed to maintain the specified CMR and CMR temperature coefficient are difficult and expensive to reliably achieve with discrete components. Any resistance imbalance introduced by external circuitry directly affects CMR. These imbalances can occur by: mismatching sense resistors when gain is decreased, adding resistance in the feedback path when gain is increased, and adding series resistance on the Rcv Com pin. The two sense resistors are laser-trimmed to typically match within 0.01 %; therefore, when adding parallel resistance to decrease gain, take care to match the parallel resistance on each sense resistor. To maintain high CMR when increasing the gain of the RCV420, keep the series resistance added to the feedback network as small as possible. Whether the Rcv Com pin is grounded or connected to a voltage reference for level shifting, keep the series resistance on this pin as low as possible. For example, a resistance of 200· on this pin degrades CMR from 86dB to approximately 8OdB. For applications requiring better than 86dB CMR, the circuit shown in Figure 5 can be used to adjust CMR. 1kn -:- -15VDC FIGURE 3. Optional Output Offset Nulling Using External Amplifier. PROTECTING THE SENSE RESISTOR The 75Q sense resistors are designed for a maximum continuous current of 40mA, but can withstand as much as 250mA for up to O.ls (see absolute maximum ratings). There are several ways to protect the sense resistor from overcur- Use 10V Reffor + and 10V Ref with INA105 for-. Va = (0.3125)(I'N) + VZERO Procedure: 1. Connect CMV to C,.. 2. Adjust potentiometer for near zero at the output. -10V 2000 CMR Adjust t-_'VVIr-<~'> 100kfl FIGURE 4. Optional Zero Adjust Circuit. 3-76 FIGURE 5. Optional Circuit for Externally Trimming CMR. Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) rent conditions exceeding these specifications. Refer to Figure 6. The simplest and least expensive method is a resistor as shown in Figure 6a. The value of the resistor is determined from the expression Rx = Vcc /40mA - 750 and the full scale voltage drop is VRX =20mA x Rx for a system operating off of a 32V supply Rx = 7250 and VRX =14.5V.ln applications that cannot tolerate such a large voltage drop, use circuits 6b or 6c. In circuit 6b a power JFET and source resistor are used as a current limit. The 2000 potentiometer, Rx' is adjusted to provide a current limit of approximately 30mA. This circuit introduces a 1-4V drop at full scale. If only a very small series voltage drop at full scale can be tolerated, then a 0.032A series 217 fast-acting fuse should be used, as shown in Figure 6c. VOUT a)Rx aVcc /40mA-75n RESISTOR NOISE IN THE RCV420 The output voltage noise of the RCV420 is dominated by the thermal noise generated in the resistor network. Figure 7 shows the model for calculating resistor noise in the RCV420. The expression for resistor noise is: IIII b) Rx set for 30!,!A current limit at 25"C. -.... it eirms) =..J2ltKTRB where: K = Boltzman's constant (JfK) Do T = Absolute temperature (OK) R =Resistance (0) B = Bandwidth (Hz) At room temperature, this noise becomes: eN = 1.3 x 1O-10 ...JR X Z o - . = c) f, is O.032A. Uffleluse Series 217 fast·acting fuse. (VNHZ) The four noise sources in Figure 7 are: e NI = 1.3 x 10-10 -fIf, eN2 = 1.3 x 10-10 -JR, e N3 = 1.3 ~ >---oVOUT 10-10 ~ Z See Application Bulletin AB·OI4 for other protection circuits. III Ii FIGURE 6. Protecting the Sense Resistors with a) Resistor, b) JFET, c) Fuse. eN4 = 1.3 X 10-10 ..JR: - Referred to output, eNOl = eNI (AD) R. eN02 = em (~) eND3 = eN3 (R/R3) eN04 =eN4 [(R, + R6)/R,1 (AD) where AD is the differential voltage gain of amplifier. Adding as the root of the sums squared: II.5kn lkn >--t----~o aNO eND =..J(eNOI~ + eNO/ + eNQ)2 + eN042) eND at a 150kHz bandwidth = 0.35mVrms = 2.lmVp-p with a crest factor of 6 (statistically includes 99.7% of all noise peak occurrences). FIGURE 7. Resistor Noise Model. Burr-Brown Ie Data Book Supplement, Vol. 33b i Iiiz 3-77 For Immediate Assistance, Contact Your Local Salesperson VOLTAGE REFERENCE The RCV420 contains a precision lOY reference. Figure 8 shows the circuit for output voltage adjustment. Trimming the output will change the voltage drift by ;:Ipproximately -In +In +--e~~~~-oV"EF . ±400mV adjustment at output of reference. and :t:50mV adjustment at output of receiver if reference is used for level shifting. FIGURE 8. Optional Voltage Reference External Trim Circuit. • 1mA O.OO7ppm/"C per mV of trimmed voltage. Any mismatch in TCR between the two sides of the potentiometer will also affect drift, but the effect is divided by approximately 5; The trim range of the voltage reference using this method is typically ±400mV. The voltage reference trim can be used to trim offset errors at the output of the RCV420. There is an 8:1 voltage attenuation from Ref In to RCV Out. and thus the trim range at the output of the receiver is typica1ly±5OmV. The highfrequency noise (to 1MHz) of the voltage reference is typically ImVp-p. When the voltage reference is used for level shifting. its noise contribution at the output of the receiver is typically 125~Vp-p due to the 8: 1 attenuation from Renn to RCV Out. The reference noise can be reduced by connecting an external capacitor between the Noise Reduction pin and ground. For example. a O.IJlF capacitor reduces the high-frequency noise to about 200~Vp-p at the output of the reference and about 25~ Vp-p at the output of the receiver. APPLICATIONS The RCV420 is ideally suited for applications requiring precise current-to-voltage conversion and high CMR. The following figures show several typical application circuits. 2kG TypeJ - + 510 Zero 200 Adjusl -Vee -=- -15V FIGURE 9. RCV420 Used in Conjunction with XTRI0lto Form a Complete Solution for 4-20mA Loop. 3-78 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Cuslomer Service al 1·800·548·6132 (USA Only) +In VA F-t----1>----Q (0-5V) 4-20mA -In CT 15.9kO -:15.9kO -Vee -15V FIGURE 10. 4-20mA to 0-lOY Conversion With Second-Order Active Low-Pass Filtering (t3dB = 10Hz). 12 IU ~lmA R, -IP. ,---_.-------- -""-<>---0 VOIJT (0-5V) vCUT = 0.3125 (I, - I,) Max Gain Error = 0.1% (RCV420BG) FIGURE 13. Differential Current-to-Voltage Converter. >..l!t......-oVOIJT (0-5V) -ReM and RG are used to provide a first order correction of CMR and Gain Error, respectively, Table 1 gives typical reSistor values for R"", and R. when as many as three RCV420s are stacked, Table 2 gives typical CMR and Gain Error with no correction, Further Improvement In CMR and Gain Error can be achieved using a 500kll potentiometer for R"", anq a 100n potentiometer for RG, RCV420 Re. (kQ) R.(n) 1 2 3 co 200 67 0 7 23 v00f = 6.25V - (0.3125) (I",) TABLE I, Typical Values for ReM and Ro' FIGURE 14. 4-20mA to 5-OV Conversion. RCV420 CMR(dB} GAIN ERROR % 1 94 68 62 0,025 0.075 0.200 2 3 TABLE 2. Typical CMR and Gain Error Without Correction. FIGURE 12. Series 4-20mA Receivers. 3-80 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) +Vcc 11 RCV420 h. 2N6551 10 VOUT 10V Reference 8 Optional Trim' VOUT (G-5V) .,t; 20kn' ~ , If not used, subsUtute fixed 20kn resistor. r-----------,_ FIGURE 17. IOV with Output Current Boosted to 100mA max. +40V (max) 11 VOUT (G-SV) RCV420 10 200n' 10V ±100mA Reference 20kn Optional Trim 5 7 'R X ) = Rsf (ILMA)( 16mA -1 ' Use carbon resistor. 7 FIGURE 18. IOV with Output to Source/Sink IOOmA. 12 w .--a... S z I I. -o FIGURE 15. Power Supply Current Monitor Circuit. ... = w Z 4-20mA :IE :::) II: Inz - , Use carbon resistor. FIGURE 16. 4-20mA Receiver with Output Current Boosted to±l00mA. Burr-Brown Ie Data Book Supplement. Vol. 33b 3-81 For Immediate Assistance, Contact Your Local Salesperson ...15V 16 -15V 4 300kO RCV420 99kO 92kO AT&T LH1191 Solid-Stat. Relay O.57V 6040 4700 J 6.95V 22.9kn 1~F Overrange Underrange Output Output - See Application Bulletin 14 for more details. FIGURE 19. 4-20mA Current Loop Receiver with Open Line and Overrange Detection Logic Outputs_ 3-82 Burr-Brown Ie Data Book Supplement,Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) ~. BURR-BROWN@ 1-==--==-1 XTR103 r\~~' ADVANCE INFORMATION .... , ...,. CW) ...a: o SUBJECT TO CHANGE = FEATURES • INTEGRAL SENSOR EXCITA LINEARIZATION !w • LOW ZERO ERROR: 101lA • LOW SPAN " .....I'OL'I'O.:".., • HIGH POWER 120dB • HIGH COI\~MQ 100dB reliable. low-cost solution for Detection (RTD) signal conconsists of a high accuracy amplifier (lA), a voltage-controlled source. dual-matched precision current RTD linearization circuitry. Dielectric laser-trimmed thin film resistors guaranof performance which is both difficult and el>~,emilve to reliably achieve with discrete components. Internal nonlinearity correction of RTD sensors eliminates the need for additional analog or digital signal processing. The XTRlO3 is housed in both 16pin plastic and sOle packages, and is also available in die form. • r-----t---~---tl-l. .--o +vcc I T • ..,. 'Optional Reverse Polarity Protection • Diode may be placed In either position; series connection increases minimum compliance voltage. .. RLm provides RTO nonlinearity correction. Rz Optional Zero Adjust L-_~~_~~~ +-_____ ___ ~ __ ~ __ ~~~ IntemallonaIAlrportlndustrlaIPark.MalilngAddress:POBoxl14OO·Tucson.AZ85734.SlreetAddress:6730S.TUcsonBlvd..Tucson.AZ 85706 Tel: (602) 746-1111 • Twx: 911).952·1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (602) 889·1510 • immediate Product Info: (600) 548-6132 PDS·to6S Burr-Brown Ie Data Book Supplement, Vol. 33b 3-83 ..--.... AS Z o - = I- Z III :IE i I;; z - For Immediate Ass/stance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL At T. = +25'C, Vee= +24V, and 2N2222 external transistor. PARAMETER OUTPUT Current Full Scale Output Current Error Current Umlt Noise (to 1kHz) Load Resistance l1 ) ZERO Initial Error'" vs Temperature vs Supply Voltage vs Common·Mode Voltage UNITS CONDInONS At rnA 20 22 50 40 Unear Operation Derated Performance M,. = 1V, Rs = Infinite rnA 25 o 750 20mA IIA rnA "Vp-p IIA efl = 0, Rs = Infinite ppml'C ppmN ppmN SPAN Output Current Equation Span Equation Untrimmed Error'" vs Temperature Nonlinearity: Ideallnpu~" Sensor Inp~" Hysteresis Dead Band AN % ppml'C % % % % INPUT Voltage Range Impedance: Differential V GO GO Common·mode Offset Voltage vs Temperature vs Supply Bias Current 25 0.5 IlV "VI"C dB nA nAI"C nA nAPC V dB 100 CURRENT Magnitude Accuracy :)VI'"''''''-':: rnA vs Temperature vs Supply vsTIme Compliance Voltage Match 0.5 100 0.25 50 Vcc-5 0.1 20 10 50 10 10 1 25 Specification Operating Storage % ppml'C ppmN ppmlmo. V % ppmi'C ppmN ppm/mo. MO 9 40 V -40 -<10 -55 85 85 'C 'C 'C 125 NOTES: (1) The transmitte(s maximum load resistance depends on Vco and is determined by the equation: A,,,,,,,= (Vcc- 9V) I lOMAX' (2) Zero Error Includes current source errors. (3) Can be adjusted to zero. (4) Best fit span nonlinearity wllh an ideal voltage input. (5) Best fit, corrected span nonlinearity with a PTl00 RTD input operated from -200'C to +850'C. 3-84 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Cuslomer Service al 1·800·548·6132 (USA Only) --" BURR-BROWN@ IE:lE:lI , ., . XTR104 l ''''"', .. :.) ADVANCE INFORMATION SUBJECT TO CHANGE .. ~ o II: = Precision 4mA to 20mA TWO-WIRE STRAIN E TRANSM FEATURES • INTEGRAL SENSOR EXCITATION LINEARIZATION IIII --... I I. Go reliable, low-cost solution for gauge bridge signal conditionof a high accuracy instrumen(IA), a voltage-controlled output cura precision 5V reference, and bridge circuitry. Dielectric isolation and laserthin film resistors guarantee a level of perwhich is both difficult and expensive to achieve with discrete components. Internal nonlinearity correction of bridges eliminates the need for additional analog or digital signal processing. The 'XTRI04 is housed in both l6-pin plastic and sOle packages, and is also available in die form. r-----~----4r----~~~~+v~ 'OptIonal Reverse Polarity Protection 'Diode may be placed In either position; serle. dlode'lncreases minimum compliance voltage. "±LIN may be Interchanged to compensate for positive or negative linearity errors of sensor; RUN provides sensor nonlinearity correction. Optional Zero Adjust L-----+---------------------~----------~~--~----~Io~ Intomatlonal Airport Induslrlal Park ' MaIHngAddross:POeoxll400 ' Tucson,AZ85734 ' Street Address: 6730 5. TUcson Blvd. ' TUcson,AZ 85706 Tel: (602) 746-1111 ' Twx: 91D-952·1111 ' cable:BBRCORP , Tol8x:066-6491 ' FAX: (602) 889-1510 ' ImmedIateProductlnlo:(800)54UI32 POS·l066 Burr-BrownIe Data Book Supplement, Vol. 33b 3-85 Iz - o =c ~ III Ii i I;; z - For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL AtT.= +25"<:. Vee = +24V. and 2N2222 external transistor. PARAMETER Full Scale Output Current Error Current Umit Noise (10 1kHz) Load Resistance'" 0 UNITS CONDmONS OUTPUT Current Unear Operation Derated Performance 4e.. = tV. 1\= InflnHe rnA rnA 25 ZERO Initial Erro,,"' vs Temperature vs Supply Voltage vs Common-mode Voltage At J1A rnA IlVp-p 0 Rs= 25n ~ 24V. 10= 20mA o 750 e" = O. R. = Infinite J1A ppml"C ppmN ppmN SPAN Output Current Equation Span Equation Untrimmed Error'" vs Temperature Nonlinearity: Ideal Inpu~" Sensor Inpu~" Hysteresis Dead Band IW % ppml"C % % % % fNPUT Voltage Range Impedance: Differential Common-mode Offset Voltage vs Temperalure vs Supply Bias Current V GO Gn 25 0.5 "V IlVI"C dB nA nAl"C nA nAl"C V 100 VOLTAGE Magnitude Accuracy vs Temperature vs Supply vs Load vsTIme Load Resistance dB V 0.20 50 5 50 10 0.1 25 % ppmI"C ppmN ppm/rnA ppm/mo. n 2500 POWER SUPPLY 9 40 -40 -40 -05 85 85 V 125 Vco and Is determined by Ihe equation: 1\... = (Vco - 9V) 110""" (2) Zero Error Indudes voltage (4) BeSl lit span nonlinearity wilh an ideal voltage input. (5) Best fit. corrected span nonlinearity wiIh a l00mV full- rre,~ist,ance dlepends on 3-86 Burr-Brown Ie Data Book Supplement, Vol. 33b .:/::- ....... . .. ......... ~::~, ...:.................... . ISOLATION PRODUCTS WHAT IS AN ISOLATION AMPLIFIER? An isolation amplifier is a device with the primary function of providing ohmic isolation (breaking the ohmic continuity of an electrical signal) between the input signal/circuitry and the output of the amplifier. It usually consists of an input operational amplifier or instrumentation amplifier followed by a unity-gain isolation stage. The sole purpose of the unity-gain isolation stage is to completely isolate the input from the output of the device. Ideally, the ohmic continuity of the input signal is broken (at the isolation barrier) yet accurate signal transfer without any attenuation is achieved across the unity-gain isolation stage. An important feature of an isolation amplifier is that it has a completely floating input which helps eliminate cumbersome connections to source ground. Figures I and 2 show typical isolation amplifier applications. The isolationmode voltage V1SO is the voltage that exists across the isolation barrier. The contribution of the output-referred error caused by V1SO is (V,So/lMRR) x Gain where IMRR is the Isolation Mode Rejection Ratio. VSIG is the differential input signal and VeM is the common-mode voltage. Leakage Current is the current that flows across the isolation barrier with some specified isolation voltage applied between the input and the output. 4 CHARACTERISTICS OF ISOLATION AMPLIFIERS Following is a discussion of some characteristics and terms unique to isolation amplifiers. COMMON·MODE VOLTAGE AND ISOLATION VOLTAGE Some manufacturers (other than Burr-Brown) treat common-mode voltage and isolation voltages synonymously in describing the use and lor specifications of isolation amplifiers. It is important to understand the significance of these terms and the difference between them. Burr-Brown Ie Data Book Supplement, Vol. 33b 4-1 For Immediate Assistance, Contact Your Local Salesperson When the input common is grounded, the differential input signal VD (see Figure I) can be floated by the amount VCM above the input ground. VCM is the common-mode voltage (CMV) and is generally ±lOV, limited by the CMV rating of the input stage amplifier. In applications involving higher systems common-mode voltages, the input common terminal is not grounded and the common-mode voltages are referenced across the isolation barrier to the output common terminal. Isolation Barrier -Error Input Common ~ +----1+ VI9IJ . "IMRR inAIV Figure 1. Typical Isolation Amplifier, Current (Input) Mode. The isolation voltage VISO shown in Figure 1 is the potential difference between the input common and the output common terminals. The isolation voltage rating describes the amount of voltage that the isolation barrier can withstand without breakdown. This feature of the isolation amplifier allows two distinct ground connections to be made when necessary. It allows the isolation amplifier to be used in applications involving very high commonmode voltages and in applications of breaking ground loops. Many applications involve a large "system common-mode voltage." In such applications, the isolation amplifier's input common terminal is not connected to any ground but the output common terminal is connected to the system ground. In such a case, the term VCM shown in Figures 1 and 2 becomes negligible and VISO determines the safe limit for the system common-mode voltage. In this manner, the isolation amplifier can accommodate common-mode voltages of 2000V or more. 4-2 Burr-Brown Ie Data Book Supplement, Vol; 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) Isolation Barrier VPSD IMRR" Error ~ ~--------------~+ Output Common Input Common "IMRRinVN .. Figure 2. Typical Isolation Amplifier, Voltage (Input) Mode. COMMON-MODE REJECTION AND ISOLATION REJECTION Isolation-mode rejection (IMR) is another term that some other manufacturers refer to as common-mode rejection (CMR). The preceding discussion on the common-mode voltage and isolation voltage helps recognize the difference between CMR and IMR. The CMR is the measure of the input stage amplifier's ability to reject common-mode input signals (common-mode with reference to the output common) while transmitting the differential signal across the isolation barrier. The isolation-mode rejection ratio (IMRR) is defined by the equations shown in Figures 1 and 2. Thus, understanding the IMR capability of isolation amplifiers allows their meaningful use in applications requiring very high common-mode rejection ratios such as l00dB to l4OdB. ISOLATION VOLTAGE RATINGS, TEST VOLTAGE It is important to understand the significance of the continuous derated isolation voltage specification and its relationship to the actual test voltage applied to the unit. Since a "continuous" test is impractical in a product manufacturing situation (implies infinite test duration) it is generally accepted practice to perform a production test at a higher voltage than the continuous rating for some shorter length of time. The important consideration is then the relationship between actual test conditions and the continuous derated minimum specification." There are several rules of thumb used throughout the industry to establish this relationship. For most isolation amplifiers, Burr-Brown has chosen a very Burr-Brown Ie Data Book Supplement, Vol. 33b 4-3 For Immed/ate Ass/stance, Contact Your Local Salesperson conservative one: VTEST =(2 X VCONTINOUSRATINO) + l000V. This relationship is appropriate for conditions where the system transient voltages are not well defined. * Where the real voltages are well defined or where the isolation voltage is not continuous, the user may choose to use a less conservative derating to establish a specification from the test voltage. Beginning with the introduction of the IS0120 and IS0121, new introductions are being tested for partial discharge. To accommodate poorly defined transients, the part under test is exposed to a voltage 1.6 times the continuous rated voltage and must display a partial discharge level of SSpC in a 100% production test. This method is described in detail in the ISO 120 data sheet. APPLICATIONS OF ISOLATION AMPLIFIERS When one or more of the following conditions/requirements are present in an application, an isolation amplifier would generally be the right choice as a signal conditioning device: • When ohmic is~lation between the signal source and the output is a requirement (isolation impedance between the input and the output is >10MQ). • When common-mode noise and voltage rejection requirements >l00dB. are • When is necessary to process· signals in the presence of, or riding on, high . common-mode voltages (CMV» lOY). In general, most applications can be broadly categorized irito the following four types: • Amplifying and measuring low level signals in the presence of high common-mode voltages. • Breaking ground loops and/or eliminating source ground connections. The isolation amplifier provides full floating input, eliminating the need for connections to source ground, and thus allowing twO-wire hook-up to the signal sources. • Providing an interface between medical patient monitoring equipment and the transducer/devices that may be in physical contact with the patients. Such applications require high isolation voltage levels and very low leakage currents. • Providing isolation protection to electronic instruments/equipment. Large common-mode voltages occasionally cause· hazardous electronic faults. The low leakage currents and high isolation voltage capabilities of isolation amplifiers help protect instruments ag~inst damage caused by such faults. *Reference National Electrical Manufacturers Association (NEMA) Standards Parts ICS 1-109 and ICS I-III. 4-4 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) Isolation amplifier perfonnance requirements vary significantly, depending on the type of requirement. In applications where bandwidth and speed of response are more important than gain accuracy and linearity, the optically or capacitively coupled amplifiers will be the best choice. For applications where gain accuracy and linearity are key parameters, Burr-Brown's family of transfonner or capacitively coupled amplifiers are the suitable choice. ISOLATION AMPLIFIERS SELECTION GUIDES The following Selection Guides show parameters for the high grade. Refer to the Product Data Sheet for a full selection of grades. Models shown in boldface are new products introduced since publication of the previous Burr-Brown IC Data Book. - Burr-Brown IC Data Book Supplement, Vol.33b 4-5 For Immediate Assistance, Contact Your Local Salesperson Boldface = NEW TRANSFORMER-COUPLED AMPLIFIERS Isolation Voltage (V) Pulse Cont Test, Peak Peak Isolation ModeRelectlon,typ DC 60Hz (dB) (dB) ±3500 ±BOOO 160 125 0.5 Low Cost IS0212P±1060 ±1697 SelfPowered 160 115 2 Descrlp Model High 3656G Isolation Voltage VoltLeakage Current Iso Gain Nonage Bias Ext atTest Imped- . linearity Drift Current±3dB Iso Freq Power Page Voltage ~ max typ (±11VI"C) (j1A) (0) (PF)(%) (%) max max (kHz) Req Templll No. I 10'" 6 ±D.05 ±D.03 5+ 100nA (1000lG,) 30 10'· 12 ±D.025±O.015 ±30 50nA (±30/G.) No Ind 4-108 No Com S4-51 NOTES: The package forthe 3656G is a DIP. the package for the IS0212P is a SIP. (1) Ind =-25°C to+85°C Com = O°C to +70°C. OPTICALLY COUPLED AMPLIFIERS Descrlp Model Isolation Isolation Leakage VoltBias Iso Gain Non- age Ext VoI!!aeM ModeRe- Current Pulse! lectlon, typ atTest ImpactDrift Current ±3dB Iso linearity DC 60Hz Voltage ~ max typ (±11Vl°C) Cont Test, Freq Power Page Peak Peak (dB) (dB) (j1A) (0) (PF) (%) (%) max max (kHz) Req Tempi') No. Balanced 3650G Current Input ±2000 ±SOOO 140 120 0.25(2) 10'" 1.8 ±D.05 ±D.02 Balanced 3652G ±2000 ±5000 140 120 0.25(2) 10'" 1.8 ±D.1 ±0.05 146(3) 10813) Low Drift 150100P 750 WideBW 2500 0.3 10'" 2.5 0.07 0.02 5 10nA 15 Yes!» Ind 4-100 25 50nA 15 Yes Ind 4-100 4(3) 10nA 60 Yes Ind 4-8 NOTE5: All packages are DIPs. (1) Ind = -25°C to +05°C. (2) At 240V/60Hz. (3) RIN = 101<0. Gain = 100. Boldface = NEW CAPACITOR COUPLED, HERMETICALLY SEALED AMPLIFIERS Isolation Isolation Leakage VoltVoltage (V) Mode Re- Current Iso Gain Nonage Bias Ext PulSil lactlon, typ at Test Impedlinearity Drift Current ±3dB Isol Cont Test, DC 60Hz Voltage --'!!!!!.!.- max typ (±I1VI"C) Freq Power Page (%) max max (kHz) Req Tempi') No. Peak Peak (dB) (dB) (j1A) (0) (PF) (%) I Descrip Model 1500VAC 150102B ±2121 ±4000 160 120 Isolation 150120B ±2121 ±35351") 160 115 IS0122P ±2121 ±3394 160 140 1.0 0.5 0.5 10" 10" 10" 6 ±D.003 ±D.002 ±250 1001lA 2 ±D.02 ±D.005 ±150 501lA 2 ±D.02 ±D.DOS ±200 501lA 70 60 50 Yes Yes Yes 3500VAC 150106B ±4950 ±8000 160 130 Isolation 150121 B ±4950 ±5600(2) 160 115 1.0 0.5 10" 10" 6 ±D.025 ±0.007 ±250 1001lA 2 ±D.01 ±D.005 ±150 501lA 70 60 Yes Yes Ind 4-20 Ind 4-44 Coml3l S4-4Q Ind Ind 4-20 4-20 NOTE5: All packages are DIPs. (1) Ind .. -25°C to +S5°C. Com .. O°C to +70°C. (2) Partial discharge voltage. (3) Not Hermetic. 4-6 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) Boldface = NEW ISOLATION POWER SUPPLlESI') Description Isolation Voltage (V) Pulsel Cant Test Peak Peak Model Leakage Input Current Voltage 240VAC Isolation 60Hz Imeedance {VDC) min max (JtA) (0) (pF) Current, Sensitivity Balanced Loads On All To Input Outeuts {mAl Change Rated Maxi') (VIV) Templ2) Pkg Single ±15V Output 700 700U PWS725A PWS726A 1500 2000 2121 4950 4200 5000 4000 8000 10 10 7 7 18 18 18 18 1 1 1.2 1.2 10'· 10'· 10'2 10'2 5 3 9 9 ±3-30 ±3-30 ±15 ±15 ±SO ±SO ±40 ±40 1.08 1.08 1.15 1.15 Ind Ind Ind Ind Dual±15V Output 722 PWS727 PWS728 4950 1060 1060 8000 1700 1700 5 10 4.5 16 18 5.5 1 1.5 1.5 10'· 10" 10" 6 8 8 ±3-40 ±15 ±15 ±SO ±3o ±30 1.13 1.15 3.2 Ind Com Com Quad±15V 710 Output 1000 3100 10 18 10'· 8 ±9.5 ±SO 1.08 Ind Mod Quad±8V Output 1000 3000 5 16 10'· 6 ±3-16 ±SO 0.63 Ind Mod Multiple PWS740 2121 Output (1-8) PWS74511) 1060 PWS750 1060 4000 1700 1700 7 4.5(5) 4.5(5) 20 1816) 18(6) 10" 10" 10'2 3 8 8 3013) ±1S ±15 60(3) 3D 30 1.20 Ind Ind Ind 724 1.5 1.5 1.5 (7) (7) Page No. 4-86 4-86 4-65 4-65 Mod Mod DIP DIP Mod 4-92 Mod 54-62 Mod 54-62 4-88 - Sysl4) 4-96 Comp54-69 Comp54-71 NOTES: (1) See complete Product DataSheetforfull specifications, especially regarding output current capabilities. (2) Ind =-25°C to +85°C. Com = O°C to +70°C. (3) Per channel. (4) 1 TO-3 driver per 8 channels, plus 2 DIPs per channel. (5) 5Voperation. (6) 15Voperation. (7) 5V operation: 3.2; 15V operation: 1.15. (8) PWS745-1 driver may also be used with PWS740 and PWS750 components. Boldface = NEW CAPACITOR-COUPLED ISOLATION AMPLIFIER, WITH POWER Description Isolation Isolation Voltage (V) Mode RePulse/ jection,t~ Cant Test, DC 60Hz Model Peak Peak (dB) (dB) Leakage Current Iso ImpedatTest ance Voltage (0) (pF) (ItA) VoltGain NonBias age linearity Drift Current ±3dB Freq Page max typ (±IlV/oC) (kHz) Tempi') No. (%) (%) max max I 1500VAC IS0103 Input Power 2121 3394(2) 160 130 1.0 10'2 11 0.0250.01 400") SOItA 20 Ind 1500VAC IS0113 Output Power 2121 3394(2) 160 130 1.0 10'2 11 0.020.012 4001') 501tA 20 Ind 54-32 2500VAC IS0107 Input Power 3535 160 100 1.2 10'2 13 0.025 0.01 400") SOItA 20 Ind 54-16 BODO 54-8 NOTES: All packages are DIPs. (1) Ind = -25°C to +85°C. (2) Partial discharge voltage. CAPACITIVELY COUPLED VOLTAGE-TO-FREQUENCY CONVERTER Descrip Model 1500Vrrns IS0108 3500Vrrns IS0109 Isolation Voltage (V) Pulse/ Cont Test Peak Peak 2121 3394(2) 4950 7918121 Leakage Current atTest Voltage (IlA) Isolation Iml!!!dance (0) (PF) Boldface Non-linBias Operating earlty at Current Freq 1MHz max max (typ) (JtA) (MHz) = NEW External Isolation Power Page Tempi') No. Req 0.3typ 10" 3 0.01 250 3 Yes Ind 54-24 0.3typ 10'2 3 0.01 250 3 Yes Ind 54-24 NOTES: Package is DIP. (1) Ind = -25°C to +85°C. (2) Partial discharge voltage. Burr-Brown Ie Data Book Supplement, Vol. 33b 4-7 U) ~ ~ a ~ a. Z 0 S 0 U) For Immediate Assistance, Contact Your Local Salesperson BURR-BROWN@ 150103 11E:I1E:I1 Low-Cost, Internally Powered ISOLATION AMPLIFIER FEATURES APPLICATIONS • SIGNAL AND POWER IN ONE DOUBLE·WIDE (0.6") SIDE·BRAZED PACKAGE • MULTICHANNEL ISOLATED DATA ACQUISITION • ISOLATED 4-20mA LOOP RECEIVER AND POWER' • 5600Vpk 'TEl:n VOLTAGE • 1500Vrms CONTINUOUS AC BARRIER RATING • POWER SUPPLY AND MOTOR CONTROL • GROUND LOOP ELIMINATION • WIDE INPUT SIGNAL RANGE: -10Vto +10V • WIDE BANDWIDTH: 20kHz Small Signal, 20kHz FuJI Power • BUILT·IN ISOLATED POWER: ±10V to ±18V Input, ±50mA Output +Vc Sense Y'N Vour -Vc Com 1 Gnd 1 • MULTICHANNEL SYNCHRONIZATION CAPABILITY (TTL) • BOARD AREA OIllLY 0.72In.2 (4.6cm 2) Com 2 -Vcc. Sync' +VCC2 +VCCl PsGnd -Vee1 Rectifiers Filters Oscillator Driver Enable Gnd2 DESCRIPTION The ISOl03 isolation amplifier provides both signal and power across an isolation barrier. The ceramic non-hermetic hybrid package with side-brazed pins contains a transformer-coupled DC/DC converter and a capacitor-coupled signal channel. Extra power is available on the isolated input side for external input conditioning circuitry. The converter is protected from shorts to ground with an internal current limit, and the soft-start feature .limits the initial cunents from the power source. Multiple-channel synchronization can be accomplished by applying a TTL clock signal to paralleled Sync pins. The Enable con- trol is used to tum off transformer drive while keeping the 'signal channel demodulator active. This. feature provides a convenient way to reduce quiescent cunent for low power applications. The wide .barrier pin spacing and internal insulation allow for the generous 1500Vrms continuous rating. Reliability is assured by 100% barrier breakdown testing that conforms to UL1244 test methods. Low barrier capacitance minimizes AC leakage cunents. These specifications and built-in features make the ISO I 03 easy to use, as well as providing for compact PC board layouts. international Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. TUcson Blvd. • TUcson, AZ 85706 Tel: (602) 746-1111 " Twx:911J.952·1111 • Cable:BBRCORP • Telex: 066-6491 • FAX:(602)889-1510 • Immediate ProducUnfo: (800) 54H132 PDS-IOO4A 4-8 Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1-800-548-6132 (USA Only) SPECIFICATIONS ELECTRICAL AI T. = +25'C and Veo> = ±15V, ±15mA oUlpulcurrenl unless otherwise noted. IS0103B ISOI03 PARAMETER ISOLATION Rated Continuous Voltage'" AC,60Hz DC Test Breakdown, 100% AC, 60Hz Isolallon·Mode Rejection Barrier Impedance Leakage Currenl GAIN Nominal Initial Error Gain vs Temperature Nonlinearity INPUT OFFSET VOLTAGE Innial Offsel vs Temperature vs Power Supplies vs Oulput SuPPly Load StGNAL INPUT Voltage Range Resistance CONOInONS MIN TMIN to TMAlC Tl,IlNtoTu.u 1500 2121 5657 IDs 1500Vrms, 60Hz 2121VDC 240Vrms, 60Hz 130 160 10"119 I VOR -IOV to 10V V.=-5VIo5V 1 ±O.12 ±SO ±O.026 ±O.009 VeE,. ±10V 10 ±18V ,= Oto±SOrnA ±20 ±300 0.9 ±O.3 Oulput Voltage in Range SIGNAL OUTPUT Voltage Range Current Drive Ripple Voltage, 800kHz Carrier 4000/4.7nF (See Figure 4) Cepacltive Load Drive Voitage NOise FREQUENCY RESPONSE Small Signal Bandwidth Slew Rate SeWingllme POWER SUPPUES Rated Voltage, VCO> Voltage Range Input Current Ripple Current C,,= I"F Rated Output Voltage OUlput Current Single Load Regulation Une Regulation Oulput Voltage vs Temperalure Voltage Balance Error. ±Vce, Voltage Ripple (800kHz) Coo- lfl.F Oulput Capacitive Load Sync Frequency TYP ±IO ±15 200 ±IO ±5 ±12.5 ±20 25 5 1000 4 MAX ·· 2 10 = ±15rnA No Filter ±14.25 Balanced Load Balanced Load No Extemal Capacitors TEMPERATURE RANGE Specification Operating Storage 1.25 -25 -25 -25 1.6 IIA ±60 ±SOO ±100 · ±250 · ·· ±15.75 ±SO IDa 1 2 +85 +85 +125 · · · ·· · ·· · ·· ··· · ·· · · ··· ··· ··· · · · UNITS Vrms VDC Vpk dB dB nil pF ±O.15 ±SO ±O.025 ±18 +90/--4.5 60 3 ±15 ±15 30 0.3 1.12 2.5 0.05 50 5 ·· ·· · MAX ±O.O8 ±20 ±O.018 ±15 ±IO TYP ±O.3 ±IOO ±O.05 20 1.5 75 0.1%, -10/10V TTL. 50'10 Duty Cycle MIN · VN %FSR ppml'C %FSR %FSR V mA mVp-p mVp-p 0k fl. kHz VIlIS lIS ·· ·· · · V V mA rnAp-p mAp-p V rnA mA 'Yo/mA VN mVFC % mVp-p mVp-p fl.F MHz 'C 'C 'C NOTE: (I) Conforms to UL1244 test methods. 100% tested at 1500Vrms for 1 minute. Burr-Brown Ie Data Book Supplement, Vol. 33b 0 - en mV fl.VFC mVN mVirnA V kn · .. (") 0 4-9 I!U ::) a 0 II: Do. Z -5 en 0 0 For Immediate Assistance, Contact Your Local Salesperson MECHANICAL ,_.---A----' G Package - 24-Pln Ceramic DIP 24 13 g 1 JB Pin 1 Identifier ~1-=-----=--=--=---=,12 - DIM A 8 C D F G H J K L N INCHES MIN MAX 1.180 1.220 .580 .600 .310 .370 .016 .020 .D40TYP .IODBASIC .044 .056 .009 .012 .165 .185 .600 .620 .040 .060 MlWMETERS MIN MAX 29.97 30.99 14.73 15.24 7.ffl 9.40 0.41 0.51 I.02TYP 2.548ASIC 1.12 1.42 0.23 0.30 4.19 4.70 15.24 15.75 1.02 1.52 NOTE: Leads In true position within 0.01" (O.25mm) R at MMCatseating plane. Pin numbers shown for reference only. Numbers may not be marked on package. .-- F 1 0 H H f- L.J L G ~~~Ht+i .JL ~ D Seating Plane ABSOLUTE MAXIMUM RATINGS --J 1-1.--L---.l,1 PIN CONFIGURATION Supply Without Damage ....................................................................±18V V~, Sense Voltage ............................................................................. iMV Oom 1 to Gnd 1 or Com 2 to Gnd 2 .............................................. ±200mV Enable, Sync ............................................................................ OV to +V.C2 Continuous Isolation Voltage ..................................................... 1500Vrms V",,, dv/dt ....................................................................................... 20kVlIIS Junction Temperature ....................................................................... 150·C Storage Temperatura ...................................................... -25·0 to +125'C Lead Temperature,IOs ..................................................................... 300·0 Qulput Short to Gnd 2 Duration ................................................ Continuous ±V••• to Gnd I Duration ........................................................... Oonllnuous "Operation requires this pin be groundad or driven with TTL levels. 4-10 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) TYPICAL PERFORMANCE CURVES T, = +2S"C. v", = ±ISVDC. ±ISmA output current unless otheJWise noted. IMRILEAKAGE vs FREQUENCY RECOMMENDED RANGE OF ISOLATION VOLTAGE 10m 10k~~_ ~2.1k~ lk j :5E :g lOOp ~ g ~ 1m ::> <.> J.." 100 ~ lap ...." 1;; ."Oil !!l E ~ 10 lp ~ '" :;: lk 10k lOOk 1M Isolation Voltage Frequency (Hz) DISTORTION vs FREQUENCY GAINIPHASE vs FREQUENCY 10 3 / l + -3 :!!. -6 .~ V II 0.1 ::tr 0.03 -9 20 lk 100 10k 20k .lll" 0 > 0 ) ~ :I 0 -10 -20 o / \ 50 ~ 13 .<: 0.. 180 225 300 lk 3k 10k 30k lOOk ISOLATED POWER SUPPLY LOAD REGULATION AND EFFICIENCY 20 10 5!' e. Small Signal Frequency (Hz) LARGE SIGNAL TRANSIENT RESPONSE C> i e w 135 -15 100 Frequency (Hz) ~ 90 \\ -12 JI 0.01 45 \ Cl Vo =20Vp·p 0 ---.:: ~ ,\\ m Vg =2Vp·p 0.3 0 F -45 0 3 z .. 10M Isolation Voltage Frequency (Hz) .:a' ~ 17 60 16 45 15 30 ~ '5 > :; ~ 100 Time (~s) 15 14 13 0 a 0 10 20 20 40 30 60 40 80 50 100 ±V CCI Supply Output Current (rnA) Burr-Brown Ie Data Book Supplement, Vol. 33b U m 1) ~" .." ~ Q. :; 0 4-11 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) T•• +25'C, v.co • ±15VDC, ±15mA output current unless oihelWlse noted. ISOLATION POWER SUPPLY VOLTAGE vs TEMPERATURE ISOLATED POWER SUPPLY LINE REGULATION 19 2 18 i/ 17 r ±15mA Load 16 /' 15 E V 14 ;:; ::;" ~ ./ 1.12VN 13 ./ 12 ./ 11 - ,...- -1 /' 10 9 9 10 11 12 13 14 15 16 17 18 -2 -25 19 +V cc• (V) o 25 '" 50 t-..... 75 100 Temperature ('C) ISOLATED SUPPLY VOLTAGE AND Vos vs SYNC FREQUENCY ! 5 250 2.5 125 S S- f!! > 0 0 g > 20 150103. (2) Bypass supplies as shown In Figure 1. Channel 2 '--+-....:------0 VOUTZ Additional Channels FIGURE 7. Synchronized-Multichannel Isolation. Burr-Brown Ie Data Book Supplement, Vol. 33b 4-15 For Immediate Assistance, Contact Your Local Salesperson BURR-BROWN® 150107 IE:lE:lI High-Voltage, Internally Powered ISOLATION AMPLIFIER FEATURES APPLICATIONS • SIGNAL AND POWER IN ONE TRIPLE-WIDE PACKAGE • MULTICHANNEL ISOLATED DATA ACQUISITION • 8000Vpk TEST VOLTAGE • BIOMEDICAL INSTRUMENTATION • 2500Vrms CONTINUOUS AC BARRIER RATING • POWER SUPPLY AND MOTOR CONTROL • GROUND LOOP ELIMINATION • WIDE INPUT SIGNAL RANGE: -10V to +10V • WIDE BANDWIDTH: 20kHz Small Signal, 20kHz Full Power 150107 BLOCK DIAGRAM /,-...c:=,-t • BUILT-IN ISOLATED POWER: ±10V to ±18V Input, ±SOmA Output V,N • MULTICHANNEL SYNCHRONIZATION CAPABILITY (TTL) Sense VOUT +VCC1 '--rc=--I Com 2 ' - - - - ; -Vee. \r--",==;,-t +SV:' Gndl Enable Com 1 -Vee1 L"":'-===:::iY Gnd2 DESCRIPTION The IS0107 isolation amplifier provides both signal and power across an isolation barrier. The ceramic side-brazed hybrid package contains a transformercoupled DCIDC converter and a capacitor-coupled signal channel. Extra power is available on the isolated input side for external input conditioning circuitry. The converter is protected from shorts to ground with an internal current limit, and the soft-start feature limits the initial currents from the power source. Multiple-channel synchronization can be accomplished by applying a TIL clock signal to paralleled Sync pins. The Enable con- trol is used to tum off transformer drive while keeping the signal channel demodulator active. This feature provides a convenient way to reduce quiescent current for low power applications. The wide barrier pin spacing and internal insulation allow for the generous 2500Vrms continuous rating. Reliability is assured by 100% barrier breakdown testing that conforms to UL544 test methods. Low barrier capacitance minimizes AC leakage currents. These specifications and built-in features make the ISO 107 easy to use, as well as providing for compact PC board layouts. international Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson BlVd. • Tucson, AZ 85706 Tel: (602) 746-1111 • Twx: 91H52·1111 • cable: BBRCORP • Telax: 066-6491 • FAX: (602) 1189-151D • immediate Product Info: (1/00) 548-6132 PDS-8988 4-16 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Cuslomer Service al 1-800-548-6132 (USA Only) SPECIFICATIONS ELECTRICAL T. = +25'C and VCO2 = ±15V, ±15rnA output current unless otherwise noted. ISOLATION Rated Continuous Voltage 1'1 AC,60Hz DC Test Breakdown, AC, 60Hz Isolation-Mode Rejection uw .. w ••• w ..~ MtN TuINtoTIrMX 2500 3500 8000 TUIN to Tw,x lOs 25OOVrms, 60Hz 2121VDC TYP MAX UN1T5 Vrms VDC Vpk dB dB 100 160 10"11 13 1.2 2 n!t GAIN Nominal Initial Error Gain vs Temperature Nonlinearity .... 0 1 ±O.1 ±SO ±O.OI VN %FSR ppml'C %FSR 'P ±O.25 ±120 ±O.O25 INPUT OFFSET VOLTAGE Initial onset vs Temperature vs Power Supplies ±20 ±150 ±2 Barrier Impedance Leakage Current tNPUT Voltage Range Resistance 240Vrms, 60Hz Veco ~ ±10V to ±18V Output Voltage In Range SIGNAL OUTPUT Voltage Range Current Drive Ripple Voltage, 800kHz Carrier (See Figure 4) Capacitive Load Drive Voltage Noise RESPONSE Small Signal Bandwidth Slew Rate Settling TIme POWER SUPPUES Rated Voltage, Vee. Voltage Range Input Current Ripple Current Load Regulation Une Regulation Output Voltage vs Temperature Voltage Balance Error, ±Vcc. VoHage Ripple Output Capacitive Load (See Figure 1) Sync Frequency ±15 200 V kn ±10 ±S ±12.5 ±20 20 1000 4 V rnA mVp-p pF I1VNHz 20 1.5 75 kHz Vips I1S ±15 V V mA mAp-p mAp-p V mA mA 0.1%, -10/10V ±10 lo=±15rnA No Filter ±14.25 Balanced Load Single Balanced Load No External Capacitors TTL, 50% Duty Cycle TEMPERATURE RANGE Specification Operating Storage mV I1VI"C mVN ±10 c", ~ ll1f Rated Output VoHage Output Current ±SO ±400 1.25 -25 -25 -25 ±18 +75/-4.5 10 3 ±15 ±15 30 0.5 1.18 10 0.05 10 1.6 ±15.75 ±SO 100 - = a U ::J 0 II: A. %/mA 1 2 VN mVI"C % mVp-p I1F MHz +85 +85 +125 'C 'C 'C NOTES: (1) Conforms to Ul544 test methods. 100% tested at 2500Vrms for 1 minute. Burr-Brown Ie Data Book Supplement, Vol. 33b 0 U) 4-17 Z 0 5 0 U) For Immediate Assistance, Contact Your Local Salesperson MECHANICAL P Package - S2·Pln Plastic DIP A-----' DIM A B C D F G H J K L N MIlliMETERS INCHES MIN MAX MIN MAX 1.580 1.620 40.13 41.15 .8BO .900 22.35 22.88 .310 .370 7.rT 9.40 0.51 .016 .020 0.41 .000TYP 1.00TYP .100 BASIC 2.54 BASIC .044 .058 1.12 1.42 .009 .012 0.23 0.30 .125 .1eo 3.1e 4.57 .900 .920 22.86 23.37 .040 .060 1.02 1.52 NOTE: Leads In true posI1Ion within 0.01' (O.25mm) Rat MMC at seating plane. Pin numbers shown lor reference only. Numbers may not be markad on package. --J I---L--~~I ABSOLUTE MAXIMUM RATINGS Supply Without Damage ....................................................................±1 BV V~, Sense Voltage .............................................................................:t50V Com 1 to Gnd I or Com 2 to Goo 2 ...........................................±2oomV Enable, Sync ...........................................................................OV to +VCC2 Continuous Isolation Voltage .................................................... 2500Vrms V""" dv/dt ......................................................................................20kV/ps Junction Temperature ...................................................................... 150'C Storage Temperature ..................................................... ~·C to +125'C Lead Temperature, lOs ...............;.............................. :......: ............. 3OO·C Output Short to Gnd 2 Duration .............................................. Continuous ±Vcc. to Goo 1 Duration .......................................................... Continuous PIN CONFIGURATION NC 32 NC Goot VIN -Vcc. 4 29 Com t Com2 13 20 -VCC2 Sync' VOUT Sense Gnd2 +VCC2 16 17 Enable 'Operation requires thai this pin be grounded or driven with TIL levels. 4-18 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Cuslomer Service al 1-800-548-6132 (USA Only) TYPICAL PERFORMANCE CURVES T" = +25°C, VCC2 = ±15VOC, ±15mA output current unless otherwise naled. RECOMMENDED RANGE OF ISOLATION VOLTAGE IMRILEAKAGE vs FREQUENCY 10k 120 :[ 3.Sk <:.. ., iii &100 lk I> c 0 . 100 0 i ......... i--" :::; 60 C .!I! E i ~ 10 J1l 40 :::; lmA ~~ -- ......... Leakage at 80 a: -g Vi--" ......... C>K 100 lk lOOk 10k 10~ ~ '" V~ 100 Isolallon Vollage Frequency (Hz) iii &54 ,V c40 lOOk Gain o -.:::::: ~ '\.\ \\ o 45 Phase -VCC2 ............ .......... ~" i' ~ go 20 '" J -9 '~ -12 o 100 '"'" GAINIPHASE vs FREQUENCY ...... j 10k lk ...... 12 15 1: 1~ 3 .I.CC2I - .g 10k lk -15 100 lOOk Supply Modulation Frequency (Hz) C ;; 90 m .. 135 Q. ~ 180 225 300 lk 3k 10k 30k lOOk Small Signal Frequency (Hz) ISOLATED POWER SUPPLY LOAD REGULATION AND EFFICIENCY LARGE SIGNAL TRANSIENT RESPONSE 20 60 T8 Balanced Load Efficiency ?: 10 ( CI> ~ g 0 J :; So 0 " -10 -20 o ?: ., 16 '\ 50 lime (~s) .. f !l lsolallon Voltage Frequency (Hz) PSRR vs FREOUENCY 60 S ~ 0" 100nA 10 1M 100pA 240Vnns 20 10 ... ......... 1-- 2500 Vrrns 't-- .~., c 10mA 1~~kag~~1 i ' t-- II~~I " 45 '" ~ ... ~:; 14 .. ~ u 30 c So 0 B " w ~ 12 ... 100 Burr-Brown Ie Data Book Supplement, Vol. 33b 15 10 20 30 40 20 40 60 80 ±Vcc. Supply OuTpul Currenl (mA) 4-19 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES T•• +25'C. Vccz. ±15VDC. ±15mA outpUt current untess otherwise noted. ISOLATED POWER SUPPLY VOLTAGE vs TEMPERATURE ISOLATED POWER SUPPLY LINE REGULATION 19 2 18 V 17 ;E ./ :!:15mALoad 16 15 ./ 1 ij ~ 14 +I ./ 1.J8VN' / ./ 13 12 ." 11 10 1/ 9 9 10 -1 V 11 -2 12 13 14 15 16 17 18 19 / ""'- ~~ V -25 +VCC2(V) v o 25 50 Temperature (OC) 75 100 ISOLATED SUPPLY VOLTAGE AND Vos vs SYNC FREOUENCY 50 2.5 I-----+-----,~+_---_I 25 i :;;- ~ 0 I-----+~~--+_---_I 0 ~ .§. ~1-4-1"'\I~---o 13 : -:- *"4.7nF FIGURE 4. Ripple Reduction. MULTICHANNEL SYNCHRONIZATION Synchronization of multiple IS0107s can be accomplished by connecting pin 19 of each device to an external TfL level oscillator, as shown in Figure 6. The PWS7S0-1 oscillator is convenient because its nominal synchronizing output frequency is 1.6MHz, resulting in a 800kHz carrier in the IS0107 (its nominal unsynchrOriized value). The open collector outpu~ typically switches 7.SmA to a 0.2V low level so that the external pull-up resistor can be chosen for different pull-up voltages as shown in Figure 6. The number of channels synchronized by one PWS7S0-1 is determined by the total capacitance of the sync voltage conductors. They must be less than l000pF to ensure TTL level switching at 800kHz. At higher frequencies the capacitance must be proportionally lower. Customers can supply their own TfL level synchronization logic, provided the frequency is between 1.25MHz. and 2MHz, and the duty cycle is greater than 25%. 4-22 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Cuslomer Service al 1-800-548-6132 (USA Only) .15V .... o ... IC, 0 1.02,0. a, 0, Rl' Rzo R3 A". As IC,. IC, Bypass IC, Bypass ·Burr-Brown PIN -15V OPA2111· 2N3904 2N7000 lN4l48 l%.lI2W 1%.22100 1.0"F 0.1J1F FIGURE 5. ECG Amplifier with Right Leg Drive, Defibrillator Protection, and E.S.U. Blanking. R NOTES: (1) PWS750-1 can sync >20 180107s. (2) Bypass supplies as shown In Figure 1. VOUT1 ~+-~--------~Voon Additional Channels FIGURE 6. Synchronized-Multichannel Isolation. Burr-Brown Ie Data Book Supplement, Vol. 33b 4-23 a- For Immediate Ass/stance, Contact Your Local Salesperson BURR-BROWN@) IS0108 IS0109 11E5I1E5I1 Isolated VOLTAGE-TO-FREQUENCY CONVERTER FEATURES • LOW JmER AT HIGH FREQUENCY: 200ppm (rms) at 1MHz • ISOLATED VFC IN HERMETIC DIP • VOLTAGE REFERENCE OUTPUT: 5VDC • MULTIPLEXED OUTPUT CAPABILITY • HIGH-VOLTAGE AC RATING: IS0108: 1500Vrms IS0109: 3500Vrms APPLICATIONS • HIGH TRANSIENT IMMUNITY: 10kVlJlS • LOW BARRIER LEAKAGE CURRENT: 0.51lA • ISOLATED AID CONVERTER • BIOMEDICAL DATA ACQUISITION • TRUE INPUT INTEGRATING (NOISE REDUCTION) • PROCESS CONTROL • INDUSTRIAL DATA ACQUISITION • HIGH LINEARITY AT HIGH FREQUENCY: 0.01% at 1MHz· DESCRIPTION The ISOI08 and ISOlO9 provide a high-speed VFe and isolated coupler in a hermetic DIP package. This represents a new function for diverse applications requiring both AID conversion and galvanic isolation. The input VFC transmits a differential digital signal across the isolation barrier through matched 1pF ceramic capacitors built into the 24-pin single-wide (ISO 108) and 4O-pin double-wide (ISOI09) packages. Excellent transient immunity is provided by the barrier capacitor matching, patented sense amp design, and laser trimming. Extra features include a voltage reference useful for offsetting and calibration, and a TTL-compatible enable input that provides for multiplexing multiple VFC outputs. -In VREF COS -vCC1 Enable Gnd2 InternatlonalAfrporttndustrlalPark • IlalilngAddress:POBol114OG • Tucsan,AZ8S734 • StreetAddreIll:6730S. TUcsan81vd. • TUcIon,AZ 857116 rei: (602) 746-1111 • 1WI:91Q.95Z,1111 • cable:BBRCORP • TeJex:06H491 • FAX:(602188!1-1510 • ImmedIattProducllnlo:(8OOI54H132 PDS-84IA 4-24 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL At TA, =+25°C and ±VCCI =±15V, VCC2 =5V unless otherwise noted. 150108.109 PARAMETER ISOLATION Rated Continuous Voltage ISOt08: AC. SOHz DC IS0109: AC. SOHz DC Partial Discharge Tes~" IS0108 IS0109 Transient Immunity wlo Signal Loss Barrier Impedance Leakage Current, SOHz Isolation Mode Rejection. SOHz TRANSFER FUNCTION Voltage-to-Frequency Mode Gain Error Linearity Error Gain Drift PSRR Input Current Range!:!1 CONDITIONS MIN to TMAX to Tw.x TMIN to TMAlI' TMIN to TMAX t500 2t21 3500 4950 TMIN TMIN TYP MAX Vrrns VDC Vrms VDC 2500Vrrns 5S00Vrms 10 10'113 0.3 130 240Vrms 2500Vrrns UNITS 5 5 pC pC kVlI1S OllpF 0.5 IlA dB OPEN COLLECTOR OUTPUT V",I,," Fall TIme REFERENCE VOLTAGE Accuracy Drill Output Current Umit PSRR Output Impedance POWER SUPPLY Voltage Range Quiescent Current 0 ii0 .... 0 - en "~I FSR= lMHz FSR= lMHz FSR= lMHz Vc" = ±8V to ±18V O·FSOutput 0.01 0 5 0.025 100 0.1 250 % % ppml"C '%N IlA INTEGRATOR OP AMP Vos Vos Drill I, V"", Range Output Current Umit ca 35 20 RL=2kn -0.2 3 100 100 +Vcc,-4 20 0.25 0.1 50 0.4 1 4.97 5 10 20 0.5 0.4 5.03 50 30 lOUT = 10mA V,," = 20V RL = 4700. CL = 500pF VCI~ = ±8V to ±18V =0 to 10mA ±VCC1 . ±8 +VCC2 4.5 mV tJ.VI"C nA V mA ±18 20 +Veel I-Veel +14/-14 +171-17 +VC~ +11 +17 V V mA mA +85 +125 +150 'C 'C 'C Operating Storage -25 -55 -55 NOTES: (1) Conforms to VDE884 test methods. Tested at 1.S x rated voltage: PD :S5pC. (2) R~= 40kn. Cos = 150pF. (3) V~ = I~ x R~. ABSOLUTE MAXIMUM RATINGS Supply Without Damage ....................................................................±20V -In, Cos .............................................................................................. ±Veel Enable ...................................................................................... Gnd 2Ncc, V.SF' Va to Gnd 1 ........................................................................ Contlnous fo Sink Current ................................................................................... 50mA Continuous Isolation Voltage: IS0108 ................................................................................. 1500Vrms IS0109 ................................................................................. 3500Vrms Barrier Transient. dVidt ................................................................. 20kV/I1S Junction Temperature ..................................................................... + 150'C Storage Temperature IS0108. 109 .............................................................. -55'C to +150'C Lead Temperature. lOs .................................................................. +300'C Burr-Brown Ie Data Book Supplement. Vol. 33b Z S en 0 0 TEMPERATURE RANGE Specification ~ D a. V ppml'C mA mVN 0 ±15 '5 Co) ~ V IlA ns 1 = 4-25 For Immediate Assistance, Contact Your Local Salesperson MECHANICAL 150108 - 24-Pln Single-Wide Hermetic Dip A [:]: 124 23 20 21 Pin 1 2 3 4 :[:]J 16 15 14 131 10 11 12 DIM A B C D F G H J K L N INCHES MlWMETERS MiN MAX MIN MAX 1.190 1.210 30.23 30.73 7.11 7.62 .280 .300 .140 .185 4.70 3.56 .016 .020 0:41 0.51 .030 .050 0.76 1.27 .100 BASIC 2.54 BASIC .035 .065 0.89 1.65 .009 .012 0.23 0.30 4.19 4.70 .165 .185 .300 BASIC 7.62 BASIC .040 .060 1.02 1.52 NOTE: Leads In lNe pcsltlon within 0.01" (O.25mm) R at MMC at seating plane. Pin numbers shown lor reference only• Numbers may not be marked on package. R I-L--I 150109 - 4O-Pln Double-Wide Hermetic DIP '~--------------A--------------~'1 r4O 21 I[JI DIM A []I C D F G H J K 20 L M N INCHES MlWMElERS MIN MAX MIN MAX 1.980 2.020 50.29 51.31 .115 .175 2.92 4.45 .015 .021 0.38 0.53 .035 .060 1.52 0.89 .100 BASIC 2.54 BASIC .070 0.76 1.78 .030 .008 .012 0.20 0.30 .120 .240 3.05 6.10 15.24 BASIC .600 BASIC 10' 10' .025 .060 0.64 1.52 NOTE: Leads In lNe position within 0.01" (O.25mm) R at MMC at seating plane. Pin numbers shown lor reference onlY. Numbers may not be marked on package. PIN CONFIGURATION Top View IS0108 -In IS0109 24 -In Gndl 40 Cos Gnd2" Gnd2" NC 10 NC Gnd2 4-26 Cos +VCC1 DG Enable 12 13 +VCC2 Gnd 1 Vo Vo +VCC1 DG "NOTE: Not required. not Intemally connected to pin 12 (150108). or pin 20 (150109). use lor optimum transient immunity. Gnd2" Gnd2" NC 10 Enable NC Gnd2 20 21 +VCC2 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) TYPICAL PERFORMANCE CURVES T" = +25°C. Vs = ±15V unless otherwise noted. OUTPUT PULSE WIDTH AND FULL-SCALE FREQUENCY vs EXTERNAL ONE-SHOT CAPACITANCE OUTPUT RESPONSE vs CAPACITIVE LOAD 10· 107 10 3 10· 10- 2 10' 10 10· 'N ;S il' c 0;- 3< ~ a> .'!.! a> " .ta> " "- a 'lij u ~ 103 OS lL 0.1 10 10· 103 102 Time (ns) 10' Cos (pF) LINEARITY vs INPUT GAIN ERROR vs TEMPERATURE 0.01 0.5 lL:: r-... 1kHz 1\ \ f'f::::: r-- I'-l-J-- ::;;. 10kHz......... 0.25 r V !-::::v V OOkHz V r<~ r....... 0.5 ff ~ 0.25 a ~ (!l 3 4 567 9 -C_5 10 a -25 RECOMMENDED RANGE OF ISOLATION VOLTAGE 5k iii" I ....~ 120 " ;: a> ~0 '" ~ 100 to- 0: 1l Operational Region 100 j 10 r-. 20 lk 10k lOOk 100 140 130 c "- IS0108 lk 85 IMRR vs FREQUENCY Nonspecllied Operalion Re Ion 2.1k 75 25 Temperature (OC) 10k :e. c V 1/ 100kHz V ,N (V) IS0109 lMHz --- -C.25 -C.75 -C.o15 2 r--- 3MHz (Scale-) lMr a V J 1M 10M Isolation Voltage Frequency (Hz) Burr-Brown Ie Data Book Supplement, Vol. 33b 10 100 ik 10k lOOk 1M Isolallon Voltage Frequency (Hz) 4-27 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) T. = +25°C. v, = ±15V unless otherwise nOled. FREQUENCY COUNTER REPEATABIUTY vs COUNTER GATE TIME 0.001 ~ 0.0006 ~ ~ :g 0.0004 I'- i" I III fFS =100kHz. 0,. = C. -17 400 =2nF -18 " J :we 1 300 f. g- t-- ~ 1iI (;' l5 JITTER vs FULL SCALE FREQUENCY 500 fJ.s= 1 MHz. Cos = 150~ 0.0002 V ./ 200 -19 a: ! ~ 100 o 0.0001 lms 10ms lOOms lk IS THEORY OF OPERATION A CHARGE BALANCE CONVERTER The ISO 108/109 uses a charge-balance technique to achieve high accuracy. The heart of this technique is an analog integrator formed by an operation amplifier, feedback capacitor, and input resistor. The integrator's output voltage is proportional to the charge stored in the capacitor. An input voltage develops an input current of VIN/RIN' which is forced to flow through the integrator capacitor. This current causes the integrator output voltage to ramp negatively. When the output of the integrator ramps to OV, the comparator trips, triggering the one-shot. This connects the reference current to the integrator input during the one-shot period, T os' .This switched current causes the integrator output to ramp positively until the one-shot period ends. Then the cycle starts again. The oscillation is regulated by the balance of the current (or charge) between the input current and the time-averaged reset current. The equation of current balance is: lIN = IREF • Duty Cycle VrnlRJi.I = IREF • fOUT • Tos' where Tos is the one-shot period and fOUT is the oscillation frequency. Integrator 1M 10M CONNECTIONS AND BASIC OPERATION External connections to the IS0108 and IS0109 are made as shown in Figure 2. The transfer function of the VFC is fo [MHz] = (20OpF)(40k)/(Cos + 5OpF)(RJN)' For a 10V full scale input, RIN = 401d1 for optimum performance; adjustment of Cos then determines full~scale frequency as shown in performance curve Output Pulse Width and Full-Scale Frequency vs External One-Shot Capacitance. The fullscale frequency is typically 3MHz with Cos =OpF. Selection of the external resistor and capacitor type is important. Temperature drift of an external input resistor and oneshot capacitor will affect temperature stability of the output frequency. NPO ceramic capacitors will normally produce the best results. Silver-mica types will result in slightly higher drift, but may be adequate in many applications. A low-temperature coefficient ftIm resistor should be used for RJN' The integrator capacitor serves as a "charge bucket," where charge is accumulated from the input, VIN' and that charge is drained during the one-shot period. While the size of the bucket (capacitor value) is not critical, it must not leak. Capacitor leakage or dielectric absorption can affect the linearity and offset of the transfer function. High-quality ceramic capacitors can be used for values less than 0.01~. Use caution with higher value ceramic capacitors. High-K ceramic capacitors may have voltage nonlinearities than can degrade overall linearity. Polystyrene, polycarbonate, or mylar film capacitors are superior for high values. External integrator capacitor CF detennines the integrator output voltage swing. It is recommended only for full-scale frequencies of 100kHz and below; in these cases, use C; Cos' Decreasing the value of C F will increase the peak-to-peak output swing, decrease jitter, but also decrease overrange capability. = Outpul I HTosl r--'l1oUT----j fOUT FIGURE 1. Basic Charge-Balance Waveforms. 4-28 lOOk Full Scale Frequency (Hz) Time The value of RL depends on the pull-up voltage, output capacitance, and full scale frequency. The maximum output current is lOrnA to assure a 0.4V maximum logic Low. Therefore, choosing ~ for 10mA output current results in the lowest rise-time for a given capacitive load. If a low fullscale frequency is used, a larger pull-up resistor will reduce Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) G) o ~ o.... o V,N I V REF (1) Enable open or TTL high. (2) Optional ollseting resistor. (3) Minimize stray capacitance other than desired Cos • (4) Optional gain adjust (5) Optical for best transient immunity. Oulput 4FIGURE 2. IS0108/109 Connection Diagram. power dissipation without sacrificing perfonnance. The effect of load capacitance (CL ) is shown in perfonnance curve Output Response vs Capacitive Loads. ENABLE PIN The Enable pin can be left open or tied to a TfL high level for continuous output. A TfL low level applied to this pin will tum off the open collector output device. This feature allows multiple outputs to be tied together for one multiplexed output line. Individual ISOVFCs are selected one at a time with the Enable control. A multichannel ISOVFC system is shown in Figure 3. The 7442 BCD to 10 output decoder selects the active channel output. This is more accurate and convenient than switching sensitive input lines. BCD Input (Channel Select) ChannelSiDeccder FIGURE 3. Multichannel Isolated Data Acquisition with Single Serial Output. Burr-Brown Ie Data Book Supplement, Vol. 33b REFERENCE VOLTAGE Figure 2. Note (2) shows a use of the reference voltage output to offset the input of the ISOVFC so that bipolar inputs can be accepted. Buried zener reference circuitry is used for low noise and excellent temperature drift. Output current is specified to 10mA and current-limited to approximately 20mA. Excessive or variable loads on VREF can decrease frequency stability due to internal heating. Low level input signals should be amplified before the ISOVFC. MEASURING OUTPUT FREQUENCY To complete an integrating AID conversion. the output frequency of the ISOI08 and ISOI09 must be counted. Simple frequency counting is accomplished by counting output pulses for a reference time (usually derived from a crystal oscillator). This can be implemented with counter/timer peripheral chips available for many popular microprocessor families. Many micro-controllers have counter inputs that can be programmed for frequency measurement. Since fOUT is an open-collector device. the negative-going edge provides the fastest logic transition. Clocking the counter on the falling edge will provide the best results in noisy environments. Alternately, a Schmidt trigger may be used on the rising edge. Frequency can also be measured by accurately timing the period of one or more cycles of the VFC's output. Frequency must then be computed since it is inversely proponional to the measured period. This measurement technique can provide higher measurement resolution in shon conversion times. It is the method used in most high-perfonnance laboratory frequency counters. It is usually necessary to offset the transfer function so OV input causes a fmite frequency out. Otherwise the output period (and therefore the conversion time) approaches infmity. See Figure 4 and application note AN-130 for funber details on counting techniques. 4-29 !! For Immediate Assistance, Contact Your Local Salesperson +1SV FF2 +SV Countermmer 8254 o C a Gate CK Gate V 1SOpF ~ Convert (Not all components shown for clarity.) FIGURE 4. Isolated NO Conversion System Using Ratiometric Counting and Microprocessor Interface. FREQUENCY NOISE Frequency noise (small random variation in the output frequency or "jitter") limits the useful resolution of fast frequency measurement techniques. Long measurement time averages the effect of frequency noise and achieves the maximum useful resolution. The ISOI08 and ISOI09 are designed to minimize frequency noise and allow improved useful resolution with short measurement times. The performance curve Frequency Count Repeatability vs Counter Gate Time shows the effect of noise as the counter gate time is varied. It shows the one standard deviation (lcr) count variation (as a percentage ofFS counts) versus counter gate time. ISOLATION BARRIER VOLTAGE The performance of the ISOI08 and IS0109 under conditions of isolation barrier voltage modulation is indicated in performance curve IMRR vs Frequency. An example is for a IMHz full scale frequency and 1500Vrms, 60Hz barrier voltage; the output frequency is modulated -13OdB R.T.I. = ±67Hz or ±67ppm. This linear modulation occurs up to the transient immunity limit of I OkV1J.lS as indicated on performance curve Recommended Range of Isolation Voltage. Above this level the output is interrupted and/or toggled by the barrier transients. Even under this condition, normal operation resumes as soon as the transient subsides. Over 20kV1J.lS can be tolerated in this mode without damage to the integrated circuits or to the ceramic high-voltage barrier. HIGH VOLTAGE TESTING Burr-Brown Corporation has adopted a partial discharge test criterion that conforms to the German VDE0884 Optocou- 4-30 pier Standards. This method requires the measurement of minute current pulses (<5pC) while applying ~2500VIl1Ill (lS0108) or 5600Vrms (IS0109), 60Hz high-voltage stress across every device's isolation barrier. No partial discharge may be initiated to pass this test. This criterion confirms transient overvoltage (1.6 x V RA~ protection without damage to the ISOVFC. Life-test results verify the absence of failure under continuous rated voltage and maximum temperatUre. This new test method represents the "state of the art" for nondestructive high voltage reliability testing. It is based on the effects of non-uniform fields existing in heterogeneous dielectric material during barrierdegnidation. In the case ofvoid non-uniformities, electric field stress begins to ionize the void region before bridging the entire high voltage barrier. The transient conduction of charge during and after the ionization can be detected externally as a burst of O.OIJ.lS0.1J.lS current pulses that repeat on each AC voltage cycle. The minimum AC barrier voltage that initiates partial discharge is defmed as the "inception voltage." Decreasing the barrier voltage to a lower level is required before partial discharge ceases and is defined as the "extinction voltage." We have designed and characterized the package to yield an inception voltage in excess of 2500Vrms for the ISO 108 and 5600Vrms for the ISOI09 so that transient overvoltages below this level will not cause any damage. The extinction voltage is above 1500Vrms for the ISOI08 and 3500Vrms for the ISOI09, so that even overvoltage-induced partial discharge will cease once the barrier voltage is reduced to the rated level. Older high voltage test methods relied on applying a large enough overvoltage (above rating) to catastrophically break down marginal parts, but not so high as to damage good ones. Our new partial discharge testing gives us more confidence in barrier reliability· than breakdown/no breakdown criteria. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service al 1·800·548·6132 (USA Only) CD o Right Leg i..o !! 1>--..N1J'----.,.....,fI/iIJ'-< NOTE: Diodes are IN414B. I!u +VCC2 ::» a ~ a. z :JURE 5. Serial TIL Output EeG Amplifier. o S o !! lURE 6. PLL Analog Isolator with High (IOkV/IJ.S) Transient Immunity. Burr-BrownIe Data Book Supplement, Vol.33b 4-31 For Immediate Assistance, Contact Your Local Salesperson BURR-BROWN@ IS0113 I-=--=-I Low-Cost, High-Voltage, Internally Powered OUTPUT ISOLATION AMPLIFIER FEATURES DESCRIPTION • SELF-CONTAINED ISOLATED SIGNAL AND OUTPUT POWER The ISOl13 output isolation amplifier provides both signal and output power across an isolation barrier in a small double-wide DIP package. The ceramic nonhennetic hybrid package with side-brazed pins contains a transformer-coupled DC/DC converter and a capacitor-coupled signal channel. • SMALL PACKAGE SIZE: Double-Wide (0.6") Sidebraze DIP • CONTINUOUS AC BARRIER RATING: 1500Vrms Extra power is available on the isolated output side for driving external loads. The converter is protected from shorts to ground with an internal current limit, and the soft-start feature limits the initial currents from the power source. Multiple-channel synchronization can be accomplished by applying a 1TL clock signal to paralleled Sync pins. The Enable control is used to tum off transformer drive while keeping the signal channel modulator active. This feature provides a eonvenient way to reduce quiescent current for low power applications. • WIDE BANDWIDTH: 20kHz Small Signal, 20kHz Full Power • BUILT-IN ISOLATED OUTPUT POWER: ±10V to ±18V Input, ±50mA Output • MULTICHANNEL SYNCHRONIZATION CAPABILITY • BOARD AREA ONLY 0.72In.2 (4.6cmZ) APPLICATIONS The wide barrier pin spacing and internal insulation allow for the generous l500Vrms continuous rating. Reliability is assured by 100% barrier breakdown testing that conforms to ULl244 test methods. Low barrier capacitance minimizes AC leakage currents. • 4mA TO 20mA VII CONVERTERS • MOTOR AND VALVE CONTROLLERS • ISOLATED RECORDER OUTPUTS • MEDICAL INSTRUMENTATION OUTPUTS • GAS ANALYZERS These specifications and built-in features make the ISOl13 easy to use, and provides for compact PC board layout. ~-;~========~::]+~ Sense , VIN -Vee. Com 1 Sync' Duly Cycle Demodulator t:=;:====-~~"1-~_ VOUT La:::======::::::==l Gnd 2 -Ve ~-r------"'L-..1 +VCC2 Enable Rectifiers. Filters Gnd 1 Ps Goo -Vcco 'Ground If not used InternatIOnal Airport Industrial Park • Mailing Address: PO Box 11400 • TUcaan, AZ 85734 • Street Address: 6730 S. Tucaan Blvd. • Tucaan, AZ 857116 Tel: (602) 746-1111 • Twx: 910.952·1111 • cable: BBRCORP • Telex: 066-6491 • FAX: (602) 1189-1510 • Irnrnedlate Product Info: (800) 548-6132 PDS-844A 4-32 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548~6132 (USA Only) SPECIFICATIONS ELECTRICAL At T, ~ +25'C and Vee. ~ :l:15V. :l:15mA output current unless otherwise noted. IS0113B IS0113 PARAMETER ISOLATION Rated Continuous Voltage AC.60Hz DC Test Breakdown, 100% AC, 60Hz Isolation-Mode Rejection Barrier Impedance Leakage Current GAIN Nominal Initial Error Gain vs Temperature Nonlinearity INPUT OFFSET VOLTAGE InUiai Offset vs Temperature vs Power Supplies vs Output SuPPly Load SIGNAL INPUT .Voltage Range Resistance CONDITIONS MIN TM~ to T_ 1500 2121 5657 TML'II toTp,wc lOs 1500Vrms, 60Hz 2121VDC Load Regulation Une Regulation Output Voltage vs Temperature Voltage Balance. :l:Vce, Voltage Ripple (800kHz) Output Capacitive Load Sync Frequency ·· TYP VV;.-10V to 10V =-5V to 5V 1 :1:0.3 :1:60 :1:0.05 :1:0.02 :1:0.5 :1:100 :1:0.1 :1:0.04 :1:20 :1:0.03 :1:0.012 :1:60 :1:500 :1:100 Vi:'==tO to :l:18V ,=OtO:l:50mA :1:20 :1:300 0.9 :1:0.3 Output Voltage In Range :1:10 :1:15 200 :1:10 :1:5 :1:12.5 :1:20 25 5 1000 4 · ·· :1:15 :1:18 :1:10 lo=:l:15mA No Filler C'N= lp.F :1:14.25 Balanced Load Single Balanced Load No External Capacitors CEXT = lp.F TTL, 50% DUty Cycle TEMPERATURE RANGE Specification Operating Storage 1.25 -25 -25 -25 +90/-4.5 60 3 :1:15 :1:15 30 0.3 1.12 2.5 0.05 50 5 1.6 :1:15.75 :1:50 100 · · 1 2 · +85 +85 +125 ·· · ·· · ·· ··· · ·· · · · ·· ·· · '·. ·· · UNITS Vrms VDC Vpk dB dB nllpF · 20 1.5 75 0.1%, -10/10V MAX · 2 4001ll4.7nF (See Figure 4) Rated Output Voltage Output Current MIN 240Vrms, 60Hz Capacitive Load Drive Voltage Noise POWER SUPPLIES Rated Voltage. Veco Voltage Range Input Current Ripple Current MAX 130 160 10" 119 1 SIGNAL OUTPUT Voltage Range Current Drive Ripple Voltage. 800kHz Carrier FREQUENCY RESPONSE Small Signal Bandwidth Slew Rate Settling Time . TYP IIA · :1:50 :1:0.05 :1:0.02 :1:250 VN %FSR ppml"C %FSR %FSR V rnA rnVp-p rnVp-p pF p.VI.JHZ kHz Vlp.s p.s · ·· V V mA mAp-p mAp-p V mA mA %/mA VN rnVI'C % mVp-p mVp-p I1F MHz 'C 'C 'C NOTE: (1) Conforms to ULI244 test methods. 100% tested at 1500Vrms for 1 minute. Burr-Brown Ie Data Book Supplement. Vol. 33b 0 - U) mV p.VI'C mVN mVimA V kn · .... .... CW) 4-33 I!C) ~ a 0 II: A. Z 5 0 0 U) For Immediate Assistance, Contact Your Local Salesperson MECHANICAL 24-Pln Double-Wide DIP 1-'- ' - - - A - - - - - i ' l 24 13 1 J B K" Pin 1 Identifier ~1~~12 I- H L-l L G HH~~+ -lL ~ D PIN CONFIGURATION NC Gnd 1 Y,N 21 4-34 12 NOTE: Leads In true position within 0.01" (0.25mm) Rat MMC at seating plane. Pin numbers shown for reference only. Numbers may not be marked on package• ~, Seaung Plane --J i----L---l.1 ABSOLUTE MAXIMUM RATINGS Enable PsGnd J K L N MIlliMETERS MIN MAX 29.97 30.99 14.73 15.24 7.87 9.40 0.41 0.51 1.02TYP 2.54 BASIC 1.12 1.42 0.23 0.30 4.19 4.70 15.24 15.75 1.02 1.52 ! I'--' 9 F G H INCHES MIN MAX 1.180 1.220 .580 .600 .310 .370 .016 .020 .000TYP .100 BASIC .044 .056 .009 .012 .165 .185 .600 .620 .040 .060 -F l- Gnd2 DIM A B C D Com 1 Supply WIthout Damage ••.•.•••...•..•.•••.••.•.••••..••.••.•.••..•.•••..••••.••.••.••.••.• :t18V VN , Sense Voltage .............................................................................:I:50V Com to Gnd (ellher Input or output) ..............................................:I:200mV Enable, Sync .......................................................................... Gnd to +Vee• Continuous isolation Vollage ..................................................... 1500Vrms V'SO. (Mdt •..••.•..•••.••••••.•.•••,............................................................. 2OkVIps Junction Temperature •••••.••••••.•••.•..••....•••..••.•.••.•••.••.•••••.•••••.•••••••••• +150'C Storage Temperatura ...................................................... 45·C to +125·C Lead Temperature.l0s ................................................................... +300"C Output Short to Gnd Duration .................................................. Continuous :tVee, to Gnd 2 Duration ••.•..••••.•.••.•..•••••.••••..•••••.••.•..••.•..•••••••••• Continuous Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) TV~CALPERFORMANCECURVES T. =+25'C,Voc • = ±15VDC, ±15rnA output current unless otherwise noted. IMRILEAKAGE vs FREQUENCY RECOMMENDED RANGE OF ISOLATION VOLTAGE 140 10k.1iii1Jll ~ 2.1k 0; lk ~ 8 ~ .5" 10 .~ 120 ~ 110 .. '8 100~A c: 90 100 lk 10k lOOk 1M "" 100 ::;; 10M lk 100 DISTORTION vs FREQUENCY 3 II 0 / ~ + Vo =2Vp-p I 11111 :I: 0.1 1== I -3 90 -6 " Phase\ -6 135 -12 180 lk 100 10k Frequency (Hz) "0 0 ;; g. " \ r -5 j -10 !i if J 10k 16 45 ;; 15 g. 30 f 6 '- l r;.,c 13 .. w u ~ 14 15 +1 13 -15 o 25 50 75 100 lime (~s) 0 0 100 ±Vce. Supply Output Current (rnA) Burr-Brown Ie Data Book Supplement, Vol. 33b Z 0 0 60 .. ~ A. 5 -en lOOk 17 ~ \ \ lk ISOLATED POWER SUPPLY LOAD REGULATION AND EFFICIENCY LARGE SIGNAL TRANSIENT RESPONSE f Ul Small Signal Frequency (Hz) 15 5 c ~ -15 100 10 45 = ::» a (,) 0 Gain '\ \ 'iiI C!l ,/" 11111 10 ~ iii' :s Vo _ ~?Vp-p 0.01 ~ 100nA lOOk 10k GAIN/PHASE vs FREQUENCY 10 ez !! Isolation Voltage Frequency (Hz) Isolation Voltage Frequency (Hz) 0 o l~A I....... "" 10 .. C') 10~A " ~ .!!l 1;j '" ~ > ! O Leakage at 240Vrms 0 E a >- I lrnA 130 ,g" ~ 100 ~ lOrnA I"- 1'- I~I~ 4-35 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) T. =...25°C,Vcc, =±15VDC, ±15mA ou1put curr~nt unless otherwise noted, ISOLATION POWER SUPPLY VOLTAGE vs TEMPERATURE ISOLATED POWER SUPPLY LINE REGULATION 19 I 18 V" 17 g ~ /' ±15mALoad 16 ~ 2 ./ 15 14 ~ ,/ 1.12VN 13 ,/ 12 J /' /' 11 0 -------+ -V~,>_---------~ NOTES: (1) Enable = pin open or TTL high. (2) Ground sync if not used. (3) L, supply voltage ripple filter. a 10pH to reduce ripple current. (4) Lo = 10pH. Co = 0.1 -10pF. OpUonal FIGURE 1. Signal and Power Connections. THEORY OF OPERATION The block diagram on the front page shows the isolation amplifier's synchronized signal and power configuration, which eliminate beat frequency interference. A proprietary 800kHz oscillator chip, power MOSFET transfonner drivers, patented square core wirebonded transfonner, and single chip diode bridge provide power to the output side of the isolation amplifier as well as external loads. The signal channel capacitively couples a duty-cycle encoded sigrniI across the ceramic high-voltage barrier built into the pack- VOUT FIGURE 2a. Gain Adjust. VOUT IV 21 : I SIGNAL AND POWER CONNECTIONS Figure 1 shows the proper power supply and signal connections. All power supply pins should be bypassed as shown with the 7t filter for +VCCI' an option recommended if more than ±ISmA are drawn from the isolated supply. Separate rectifier output pins (±Vco) and amplifier supply input pins (±Vc) allow additional ripple filtering and/or regulation. The separate input common pin and output sense are low current inputs tied to the signal source ground, and output load, respectively, to minimize errors'due to IR drop in long conductors. Otherwise, connect Com 1 to Gnd I, and Sense to V OIIT at the IS0113 socket. The enable pin may be left open if the ISOI13 is continuously operated. If not, a TTL low level will disable the internal DC/DC converter. The Sync input must be grounded for unsynchronized operation while a 1.2SMHz to 2MHz TTL clock signal provides synchronization of multiple units. OPTIONAL GAIN AND OFFSET ADJUSTMENTS 2 v~ ! ~ age. A proprietary transmitter-receiver pair of integrated circuits, laser trimmed at wafer level, and coupled through a pair of matched "fringe" capacitors, results in a simple, reliable design. R, Gain = 1 + (R,IA. + R,1200k) FIGURE 2b. Gain Setting. Burr-Brown Ie Data Book Supplement, Vol. 33b Rated gain accuracy and offset perfonnance can be achieved with no external adjustments, but the circuit of Figure 2a may be used to provide a gain trim of ±O.S% for the values shown. Greater range may be provided by increasing the size of Rl and R2' Every 2k!l increase'in Rl will give an additional 1% adjustment range, with ~ 20 IS0113s. (2) Bypass supplies as shown in Figure 1. FIGURE 7. Synchronized-Multichannel Isolation. Burr~Brown Ie Data Book Supplement, Vol. 33b 4-39 For Immediate Assistance, Contact Your Local Salesperson BURR-BROWW IS0122P IElElI Precision Lowest Cost ISOLATION AMPLIFIER FEATURES APPLICATIONS • 100% TESTED FOR HIGH-VOLTAGE BREAKDOWN • INDUSTRIAL PROCESS CONTROL: Transducer Isolator, Isolator for Thermocouples, RTDs, Pressure Bridges, and Flow Meters, 4mA to 20mA Loop Isolation • RATED 1500Vrms • HIGH IMR: 140dB at 60Hz • GROUND LOOP ELIMINATION • BIPOLAR OPERATION: Vo= ±10V • SINGLE-WIDE 16-PIN PLASTIC DIP • EASE OF USE: Fixed Unity Gain Configuration • POWER MONITORING • PC-BASED DATA ACQUISITION • 0.020% max NONLINEARITY • ±4.5V to ±18V SUPPLY RANGE • TEST EQUIPMENT • VENDING MACHINES • MOTOR AND SCR CONTROL DESCRIPTION The IS0122P is a precision isolation amplifier incorporating a novel duty cycle modulation-demodulation technique. The signal is transmitted digitally across a 2pF differential capacitive barrier. With digital modulation the barrier characteristics do' not affect signal integrity, resulting in excellent reliability and good high frequency transient immunity across the barrier. Both barrier capacitors are imbedded in the plastic body of the package. v~ o-_-,,15!.J The IS0122P is easy to use. No external components are required for operation. The key specifications are 0.020% max nonlinearity, 50kHz signal bandwidth, and 200J.lVt'C Vos drift. A power supply range of ±4.5V to ±18V and quiescent currents of ±4.5mA on VS1 and ±5.0mA on VS2 make these amplifiers ideal for a wide range of applications. 9 -v" ...v.. Gnd International Airport industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (602) 746-1111 • TWx: 91CH152·1111 • Cable: BBRCORP • Telex: 06U491 • FAX: (602) 889-1510 • Immediate Product Inlo: (SOD) 548-6132 PDS-8S7C 4-40 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS AtT... = +25°C. VS1 '" VS2 =±15V. and RL = 2kQ unless othelWise noted. MIN vv ..u ••• v •• ~ ".nAMCIC. ISOLATION Voltage Rated Continuous AC 60Hz 100% Te5t lll Isolation Mode Rejection Barrier Impedance LeakaiJe Current at 60Hz GAIN Nominal Gain Gain Error Gain vs Temperature Nonlinearity MAX UNITS O.S VAC VAC dB nllpF JlArrns 1500 2400 1s. Spc PO 60Hz 140 10"112 0.18 V.. = 240Vrrns Vo =±10V 1 ±D.05 ±10 ±D.008 INPUT OFFSET VOLTAGE InHial Offset vs Temperature vsSupply Noise OUTPUT Voltage Range Current Drive Capacitive Load Drive Ripple Voltage"1 ±D.50 ±D.020 ±SO VN %FSR ppml"C %FSR ±12.5 200 V kn ±10 ±5 ±12.5 ±20 0.1 V mA 20 mVp-p 50 2 kHz VlIlS 50 350 150 IlS IlS IlS 0 ':1;15 V V mA mA Z 0 ±4.5 ±S.O v'" Ilf ±18 ±7.0 ±7.0 70 0 -25 -25 85 85 100 9", ·C ·C ·C oelW NOTES: (I) Tested at 1.6 X rated. fali on SpC partial discharge. (2) Input Range is ±1 OV independent of input±Vs ,' (3) Ripple frequency is at carrier frequency (500kHz). CONNECTION DIAGRAM ABSOLUTE MAXIMUM RATINGS Supply Voltage ...................................................................................±18V V............................;....;......................................................................±100V Continuous Isolation Voltage .................:................................... 15OOVrrns Junction TempiiratiJre·............................................~ ......................... +150·C Storage Temperature ... :.................................................................... +85·C Lead Temperature (soldering. lOs) ................................................ +3oo·C Qulput Short to Common ......................................................... Continuous Top View Burr-Brown Ie Data Book Supplement. Vol. 33b •- ±10 ±4.5 TEMPERATURE RANGE Specllication Operating Storage 0 ±2 4 Vo =±10V POWER SUPPUES Rated Voltage Voltage Range Quiescent Current: V51 .. ('I ('I mV INI'C mVN IlVNHz ±5 ±200 INPUT Voltage Range'" Resistance FREOUENCYRESPONSE Small Signal Bandwidth Slew Rate. Settling Time 0.1% 0.01% Overtoad Recover Time TYP 2 4-41 I!U ~ Q a: Do -S •0 For Immediate Assistance, Contact Your Local Salesperson MECHANICAL r ~'~1] P Package-Single-Wide 16-Pln PlasDe DIP DIM A A. B B. C D· J.j P ~Pln1 --.J ->jFI- ... 1 13 . I'-G -0 UV.u. C UK~ \ ..JI.- T D SeaDng Plane 10- H F FL~ G H .ft J K L M N p INCHES MIN MAX .740 .800 .725 .785 .230 .290 .200 .250 .120 .200 .015 .023 .030 .070 .100 BASIC 0.20 .050 .015 .008 .070 .150 .300 BASIC 15' D' .010 .030 .025 .050 MIWME1ERS MIN MAX 18.80 20.32 18.42 19.94 5.85 7.38 5.09 6.38 3.05 5.09 0.38 0.59 . 0.76 1.78 2.54 BASIC 0.51 1.27 D.20 0.38 1.78 3.82 7.63 BASIC 15' 0' 0.25 0.76 0.64 1.27 NOTE: Leads In true poshlon wllhln 0.01" (O.25mm) R at MMC al saaDng plane. Pin numbe,s shown for reference only. Numbers may nol be marked on package. TYPICAL PERFORMANCE CURVES T. = +25'C. v, = ±15V unless otherwise nOled. SINE RESPONSE (1= 2kHz) SINE RESPONSE (f=20kHz) +10 +10 . ~ Ii !$ ~ 0 i -10 0 ~ s 8 i " 0 500 -10 0 1000 TIme(llS) STEP RESPONSE . +10 +10 ~ i~ 0 S. ~ -10 0 0 500 TIme(llS) 4-42 0 S ~ 0 100 STEP RESPONSE ~ f 50 TIme(llS) 1000 -10 0 50 100 TIme(llS) Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES T. =+25'C. V. =±15V unless o\helWise noted. ISOLATION VOLTAGE vs FREQUENCY IMR vs FREQUENCY 160 .. ~ '0 > Ik 'j'. 120 iD :s " 0 itil., ..... 140 2.lk ..... 100 0: 2! &'II &'II i'j'. IDa 80 .... ..... 0.. o 60 0 40 100 Ik 'lOOk 10k 1M 10M 100M 10 IDa Frequency (Hz) , iD i'i\ i\ 0: " I51 +VS1 ' +VS2 -VS1·-Vsz \ 0 lOa Ik 10k lmA 1500Vrms 8 IOO11A \ f IOIIA 20 10 1M lOrnA 40 0.. lOOk 100mA :s 0: en 10k Ik Frequency (Hz) ISOLATION LEAKAGE CURRENT vs FREQUENCY PSRR vs FREQUENCY 60 54 lOOk 240Vrms ~ " IlIA HII O.IIIA 10 1M 100 Frequency (Hz) Ik 10k lOOk 1M Frequency (Hz) SIGNAL RESPONSE TO INPUTS GREATER THAN 250kHZ E III 0 250 -10 200 -20 150 !! ., -30 100 11. -40 50 'C ::? ) :; ,.. 0 ::J 0 500kHz 1MHz ~ I.5MHz Input Frequency (NOTE: Shaded area shows aliasing frequencies !hat cannot bp removad by a low-pass filter at the outpull Burr-Brown Ie Data Book Supplement, Vol. 33b - U) 4-43 FOI Immediate Assistance, Contact YOUI Local Salesperson THEORY OF OPERATION The ISOl22P isolation amplifier uses an input and an output section galvanically isolated by matched IpF isolating capacitors built into the plastic package. The input is duty-cycle modulated and transmitted digitally across the barrier. The output section receives the modulated signal, converts it back to an analog voltage and removes the ripple component inherent in the demodulation. Input and output sections are fabricated, then laser trimmed for exceptional Circuitry matching common to both input and output sections. The sections are then mounted on opposite ends of the package with the isolating capacitors mounted between the two sections. MODULATOR An input amplifier (AI, Figure 1) integrates the difference between the input current (Vn/200kO) and a switched ±l 00J.tA current source. This current source is implemented by a switchable 2001lA source and a fixed loollA current sink. To understand the basic operation of the modulator, assume that VIN = O.OV. The integrator will ramp in one direction until the comparator threshold is exceeded. The comparator and sense amp will force the current source to switch; the resultant signal is a triangular waveform with a 50% duty cycle. The internal oscillator forces the current source to switch at 500kHz. The resultant capacitor drive is It complementary duty-cycle modulation square wave. VOUT pin equal to VIN' The sample and hold amplifiers in the output feedback loop serve to remove undesired ripple voltages inherent in the demodulation process. BASIC OPERATION SIGNAL AND SUPPLY CONNECTIONS Each power supply pin should be bypassed with 1!1F tantalum capacitors located as close to the amplifier as possible. The internal frequency of the modulator/demodulator is set at 500kHz by an internal oscillator. Therefore if it is desired to minimize any feedthrough rtoise (beat frequencies) from a DC/DC converter, use a 1t filter on the supplies (see Figure 4). ISOl22P output has a 500kHz ripple of 2OmV, which can be removed with it simple two pole low-pass filter with a 100kHz cutoff using a low cost op amp. See Figure 4. The input to the modulator is a current (set by the 200kO integrator input resistor) that makes it possible to have an input voltage greater than the input supplies, as long as the output supply is at least ±15V. It is therefore possible when using an unregulated DC/DC converter to minimize PSR related output errors with ±5V voltage regulators on the isolated side and still get the full ±1OV input and output swing. An example of this application is shown in Figure 10. CARRIER FREQUENCY CONSIDERATIONS DEMODULATOR The sense amplifier detects the signal transitions across the capacitive barrier and drives a switched current source into integrator A2. The output stage balances the duty-cycle modulated current against the feedback current through the 200kO feedback resistor, resulting in an average value at the The ISO 122P amplifier transmits the signal across the isolation barrier by a 500kHz duty cycle modulation technique. For input signals having frequencies below 250kHz, this system works like any linear amplifier. But for frequenCies above 250kHz. the behavior is similar to that of a sampling amplifier. The signal response to inputs greater than 250kHz performance curve shows this behavior graphically; at input Isolation Barrier FIGURE 1. Block Diagram. 4-44 Burr~Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) frequencies above 250kHz the device generates an output signal component of reduced magnitude at a frequency below 250kHz. This is the aliasing effect of sampling at frequencies less than 2 times the signal frequency (the Nyquist frequency). Note that at the carrier frequency and its harmonics, both the frequency and amplitude of the aliasing go to zero. ISOLATION MODE VOLTAGE INDUCED ERRORS IMV can induce errors at the output as indicated by the plots of IMV vs Frequency. It should be noted that if the IMV frequency exceeds 250kHz, the output also will display spurious outputs (aliasing), in a manner similar to that for VIN > 250kHz and the amplifier response will be identical to that shown in the Signal Response to Inputs Greater Than 250kHz performance curve. This occurs because IMV -induced errors behave like input-referred error signals. To predict the total error, divide the isolation voltage by the IMR shown in the IMR vs Frequency curve and compute the amplifier response to this input-referred error signal from the data given in the Signal Response to Inputs Greater than 250kHz performance curve. For example if a 800kHz 100DVrms IMR is present, then a total of [( -60dB) + (-30dB)] x (IODOV) = 32mV error signal at 200kHz plus a IV, 800kHz error signal will be present at the output. HIGH IMV dV/dt ERRORS As the IMV frequency increases and the dVIdt exceeds 1OOOVIllS, the sense amp may start to false trigger, and the output will display spurious errors. The common mode current being sent across the barrier by the high slew rate is the cause of the false triggering of the sense amplifier. Lowering the power supply voltages below ±15V may decrease the dVIdt to 500V/Ils for typical performance. HIGH VOLTAGE TESTING Burr-Brown Corporation has adopted a partial discharge test criterion that conforms to the German VDE0884 Optocoupier Standards. This method requires the measurement of minute current pulses (<5pC) while applying 2400Vrrns, 60Hz high voltage stress across every IS0122 isolation barrier. No partial discharge may be initiated to pass this test. This criterion confirms transient overvoltage (1.6 x 1500Vrrns) protection without damage to the ISOI22. Lifetest results verify the·absence of failure under continuous rated voltage and maximum temperature. This new test method represents the "state of the art" for nondestructive high voltage reliability testing. It is based on the effects of non-uniform fields that exist in heterogeneous dielectric material during barrier degradation. In the case of void non-uniformities, electric field stress begins to ionize the void region before bridging the entire high voltage barrier. The transient conduction of charge during and after the ionization can be detected externally as a burst of 0.01O.llls ~u~ent pulses that repeat on each AC voltage cycle. The mmtmum AC barrier voltage that inititates partial discharge is defined as the "inception voltage." Decreasing the barrier voltage to a lower level is required before partial discharge ceases and is defmed as the "extinction voltage." We have characterized and developed the package insulation processes to yield an inception voltage in excess of 2400Vrrns so that transient overvoltages below this level will not damage the ISOI22. The extinction voltage is above 1500Vrms so that even overvoltage induced partial discharge will cease once the barrier voltage is reduced to the 1500Vrrns (rated) level. Older high voltage test methods relied on applying a large enough overvoltage (above rating) to break down marginal parts, but not so high as to damage good ones. Our new partial discharge testing gives us more confidence in barrier reliability than breakdown/no breakdown criteria. Isolation Barrier ,, ,, , :,, , ,,, V'N ,, Gnd ,,, ,, .!, ., -v" Gnd +v~ FIGURE 2. Basic Signal and Power Connections. Burr-Brown Ie Data Book Supplement. Vol. 33b FIGURE 3. Programmable-Gain Isolation Channel with Gains of 1,10, and 100. 4-45 ..o ~ ~ - II) 4 For Immediate Assistance, Contact Your Local Salesperson Isolation Barrier 131<0 100pF V~ IS0122P Gnd FIGURE 4. Optionaln: Filter to Minimize Power Supply Feedthrough Noise; Output Filter to Remove 500kHz Carrier Ripple. r-----------------, This Section Repeated 49 Times. I I I I e,= 12V I I I I e,= 12V I I L_ I I I I I ---r-----------~ ,.----'----, I Control Section Charge/Discharge I Control '--_---._ _--' I I I I L _________I FIGURE 5. Battery Monitor for a 600V Battery Power System. (Derives Input Power from the Battery.) 4-46 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at I Thermocoup.le R. -:- +15V-15V +15V-15V -:+15V Isothermal Block with lN414S'" lMQ (USA Only) 10.0V -----,7'" \ 1-800~548-6132 ISOI22P R, R, , ,,, ,, ,,, ,, 100Q ISA TYPE -:I ~---------------------------------: _______ ~:':u~~:~~_~~':U!~~~~u~t_________ J) ... E J NOTE: (1) -2.1mVI"C at2.001lA K T MATERIAL Chromel Constantan Iron Constantan Chromel Alumel Copper Constantan SEEBACK COEFFlCIENT !\1V1'C) (R.= 100Q) R" .R, (R, + R = 100Q) 5S.5 3.48k!l 56.2k!l 50.2 4.12k!l M~k!l 39.4 5.23k!l SO.6k!l 3S.0 5.49k!l 84.5kO FIGURE 6. Thermocouple Amplifier with Ground Loop Elimination, Cold Junction Compensation, and Up-scale Bum-out. lmA r------_-----.....- - -.... +V.~15V on PWS740 lmA i i +V R,= 100Q RTD (PT100) ~ 7 10 R, =2.5k!l 2mA 16 ~S V"", OV·5V -V L----_+----c.. Gnd L-------.......- - - - - _ - - . . · - V . a - 1 5 V on PWS740 FIGURE 7. Isolated 4-20mA Instrument Loop. (RTD shown.) Burr-Brown Ie Data Book Supplement, Vol.33b 4-47 FOI Immediate Assistance, Contact YOUI Local Salesperson 2kll 10kll Roo IS0122P +V (V,> V,=V,(R" +R..> '----------t=-f-t-'---------o Roo ToPWS74()"1 ToPWS740·1 FIGURE 8. Isolated Power Line Monitor. 4-48 Burr~Brown Ie Data Book Supplement, Vol. 33b Dr, Call Customer Service at 1-800-548-6132 (USA Only) Channell. ~ 1S0022P ~ 15 V" V"" 8 9 16 H7¥' V ~~ 4 1 1 PWS740-2 20llH 10llF 1 ~-~ 4 B I 6 i2 3 5 6 >-- - en PWS740-3 PWS740·3 3 o ~n-- 4 I +1 w O.3J1F O.3~ Channel 2 (Same as Channell.) . 16 2 11 3 3 UJvJ --rrr-tbrl5 PWS740-2 6 --< 6 5 PWS740-1 4 3 -=- Channel 3 (Same as Channel 1.) Channel 4 (Same as Channell.) FIGURE 9. Three-Port, Low-Cost. Four-Channel Isolated. Data Acquisition System. Burr-Brown Ie Data Book Supplement, Vol. 33b .. w 4-49 For Immediate Assistance, Contact Your Local Salesperson +1SV Vwr To PWS74D-2.-1 NOTE: The Input supplies can be subregulated to ±SV to reduce PSR related errors without reducing the ±10V Input range. FIGURE 10. Improved PSR Using External Regulator. 4-50 Burr-Brown Ie Data Book Supplement, Vol. 33b Dr, Call Customer Service at 1-800-548-6132 (USA Only) BURR-BROW~ IElElI ~ IS0212P IS0212KP ...w W o Low Cost, Two-Port Isolated, Low Profile ISOLATION AMPLIFIER FEATURES APPLICATIONS • 12·BIT ACCURACY • LOW PROFILE (LESS THAN 0.5" HIGH) • INDUSTRIAL PROCESS CONTROL: Transducer Channel Isolator for Thermocouples, RTDs, Pressure Bridges, Flow Meters • SMALL FOOTPRINT • EXTERNAL POWER CAPABILITY (±8Vat 5mA) !! • 4mA TO 20mA LOOP ISOLATION • MOTOR AND SCR CONTROL • GROUND LOOP ELIMINATION • ANALYTICAL MEASUREMENTS • "MASTER/SLAVES" SYNCHRONIZATION CAPABILITY • INPUT OFFSET ADJUSTMENT • LOW POWER (75mW) • SINGLE 12V OR 15V SUPPLY OPERATION • POWER PLANT MONITORING • DATA ACQUISITIONITEST EQUIPMENT ISOLATION • MULTIPLEXED SYSTEMS WITH CHANNEL TO CHANNEL ISOLATION DESCRIPTION Isolation Barrier The IS0212P signal isolation amplifier is a member of a series of low-cost isolation products from BurrBrown. The low-profile SIL plastic package allows PCB spacings of 0.5" to be achieved, and the small footprint results in efficient use of board space. To provide isolation, the design uses high-efficiency, miniature loroidal transformers in both the signal and power paths. An uncommitted input amplifier and an isolated external bipolar supply ensure the majority of input interfacing or conditioning needs can be met. The IS0212P accepts an input voltage range of ±5V for single ISV supply operation or ±2.SV for single 12V supply operation. Offset Adjust 8 Ollset 7 Adjust -lIP 0-=-3_-1 I I I I : [ [ 3 8 OIP High I I I +VP o-:---~ . ! 37 OIPLow I I 4 _--, '. 0-:-- +vss, Out Com 1 0=---1-\ : DC/DC Converter +Vcc Com 2 -vss , Out Clack Out '---"""0 Clack In lntImatlonal Allpott Induslrlal Park • MaHing Address: PO Bor 11400 • Tucson, AZ 85734 • street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Til: (602) 74601111 • Twx: 911).952-1111 • cable: BBRCORP • Teler: 116U491 • FAX: (602) 889-1510 • Immediate Product Inlo: (600) 548-6132 PDS·881B Burr-Brown Ie Data Book Supplement, Vol. 33b 4-51 For Imm,diat, Ass/stane" Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL At T. +25'C and Vee. +15V unle•• otherwise nOted. IS0212JP PARAMETER ISOLATION Voltage Rated Continuous AC,60Hz DC 100% Test (AC, BOHz) Isolation·Mode ReJection'" AC DC Barrier Resistance Barrter CapaCitance Leakage Current GAIN Initial Error Gain vs Temperature Nonlinearity'" INPUT OFFSET VOLTAGE Initial Offset vs Temperature vs Power Supply'" Adjuslment Range CONDmONS T". to T"", T".to T""" Partial Discharge Is: <5pC V"". Rated Continuous 60Hz MIN a 1200 liS 160 10'0 12 1 ±1 20 0.04 OUTPUT Voltage Range Ripple Voltage '" FREQUENCY RESPONSE Small Signal Bandwidth Full Signal Bandwidth ISOLATED POWER OUTPUTS Voltage Outputs (±Vss ,) ", vs Temperature vs Load Current Output ", (Both Loaded) (One Loaded) POWER SUPPLIES Rated Voltage Voltage Range 'Si Quiescent Current TEMPERATURE RANGE SpecHicatlon Operating TYP 1.6 ·· ±2 50 0.05 0.015 2 · ±5 Out Hi to Out Lo Min Load = 1Mn f =,0 to 100kHz f=Oto5kHz ±5 No Load · · 8 0.4 lIP = IVp·p, -3dB G=1 liP = 10Vp-p, G=1 0.025 ±7.S±7.5JG ·· 50 '4 Rated Operation G=1 ·· ·· · ±20 1 · ±B 90 15 No Load 4.3 0 -25 % FSR'" ppmFSR %FSR mV fJ.VI"C mVN mV nA nA V ·· mVp-p mVrms · kHz ··· 5 8 11.4 IIArms Hz -S Rated Performance dB dB n pF IlArms V 200 ±7.5 UNITS Vrms · ±30±301G ±1.5 Vee = 14V to 16V MAX Vrms VDC ±10 ±101G OV INPUT CURRENT Bias OIIset INPUT Voltage Range '" MIN ·· · 750 -BV to +5V VIN ... IS0212KP MAX 1060 VISO = 240Vrms, 60Hz VISO a 240Vrms, 50Hz Vo TYP 16 7 +70 +85 · ·· · · VDC mVI"C mVimA ·· ·· ~ · rnA rnA V V rnA "C 'C ·Same as IS0212JP. NOTES: (1) Isolatlon·mode rejection is the ratio of the change In output voltage to a change In Isolation barrier voltage. It Is a function of frequency. (2) FSR = Full Scale Range = ,10V. (3) Nonlinearity Is the peak deviation of the output voltage from the best-iii straight line. "is expressed as the ratio of deviation to FSR. (4) Power Supply Rejection is the change In V,,",Supply Change. (5) At Vee a +11.4V, Input voltage range = ±2.5V min. (6) Ripple Is the residual component of the barrier cerrler frequency generated internally. (7) Derated at Vee = +11.4V. 4-52 Burr-BrownIe Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) MECHANICAL P Package --38-Pln Plastic SIP DIM A B C D E F G H J K L M N I .... jL~ PIN CONFIGURATION f, 4 0 +V.., 6 0 Offset Ad/ust 8 0 - INCHES MIN MAX 2.220 2.246 0.415 0.463 0.295 0.325 0.050TYP 0.195TYP 1.500TYP 0.188TYP 0.100TYP 0.1 00 TYP 0.125TYP 0.018TYP 0.010TYP 0.08 NOTE: Leads In true position within 0.01" (0.25mm) R at MMC at seating plane. - ABSOLUTE MAXIMUM RATINGS BaHam View Com 1 2 0 MILLIMETERS MIN MAX 56.39 57.05 10.54 11.76 7.49 8.26 1.27TYP 4.95TYP 38.1 0 TYP 4.78TYP 2.54TYP 2.54TYP 3.18TYP 0.46TYP 0.25TYP 2.03 Supply Voltage Without Damage ......................................................... laV Continuous Isolation Voltage Across Barrier ................................ 750Vnns Storage Temperature Range ............................................. -25'C to 100'C Lead Temperature (soldering. lOs) ................................................ +300'C Amplifier Output Short-CIrcuit Duration ................. Continuous to Common Output Voltage HI or La to Com 2 ................................................... :I;Vcc 12 I) 1 +I/P 0 3 -VP 0 5 -Vas I 0 7 Offset Ad/ust u = a ::::» a ID. Com2 32 0 0 Clock Out 34 0 o/P High 38 0 z o 31 +V"" o 35 Clock In o 37 o/P Low 5o - (I) ORDERING INFORMATION MODEL PACKAGE OPERATING TEMPERATURE RANGE IS0212JP IS0212KP Plastic SIP Plastic SIP -25'C to +85'C -25'C to +85'C Burr-Brown Ie Data Book Supplement, Vol. 33b 4-53 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES TA • +25'C, Vs = ±15V unless otherwise noted, 51ne Response (I ~ 2kHz, Sine Response (I = 200Hz) +500 +5k------r----~~------~----~ ~ f 0 I 1_---\,---r--+--+_--\---~___J'--__1 ~r-----~~----~----~~----~ V IN = ±5V, J I 0 I-----~--'-----~-----+------~ I--+--+----r'---~--I.____-+--_/_--~ ~001_----~------+_----~~----__1 G= 1 o +5 l 5 o 10 500 1000 TIme (ms) TIme(~s) Step Response (I = 200Hz) Step Response (I. 2kHz) t--,,---+----,r-+_....,.---t------r--I +500 I------+-------+-------t-----~ ~ " ~ ~ O/---t--t---I----r--t--l---+---\ o g 1_--t--+----t-+---4r--~--+___1 ~OO r------+-------+-------t-----~ V,N • ±5V, G • 1 V,N = ±D.5V, G = 1 o 5 o 10 500 Time (ms) LINEARITY YS CLOCK-IN RATE IMR va FREQUENCY 100 85 80 75 " 90 80 70 iii' :a 65 ~ 60 a: ~ 70 w 50 g I\.. f "<= 55 ::::; 50 60 L ............ f""'.... 40 30 20 i"" 45 . / '" - ./ 10 0 40 lk 10k lOOk 1M Frequency (Hz) 4-54 1000 TIme (ps) 10M 100M ~ 40 ~ 90 ro 90 90 100 Clock-In Rate (kHz) Burr-Brown Ie Data Book Supplement, Vol. 33b Or, CallCuslomer Service al 1-800-548-6132 (USA Only) OPTIONAL OFFSET VOLTAGE ADJUSTMENT In many applications. the untrimmed input offset voltage will be adequate. For situations where it is necessary to trim the offset. a potentiometer can be used. See Figure I for details. It is important to keep the traces to the offset adjust pins as short as practical. because noise can be injected into the input op amp via ·this route. TYPICAL PERFORMANCE CURVES (CONT) TA a +25'C. V. a :l:15V unless otherwise noted. GAIN ERROR ys CLOCK·IN RATE 0 12' U) u.. -0.5 ~ -1 .~ -1.5 j (!J -2 / V / ~ INPUT PROTECTION 0 !! ~2.5 30 If the IS0212P is used in systems where a transducer or sensor does not derive its power from the isolated power W available from the device. then some input protection must ... be present to prevent damage to the input op amp when the W IS0212P is not powered. A resistor of 5kn should be included to limit the output impedance of the signal source. Where the op amp is configured for an inverting gain. then R'N of the gain setting network can be used. Fornon-inverting configurations. a separate resistor is required. Neglecting this . . point may als.o lead to problems when powering on the ~ IS0212P. 40 50 60 80 70 90 100 Clock·ln Rata (kHz) DISCUSSION OF SPECIFICATIONS The IS0212P is intended fOl applications where isolation and input signal conditioning are required. Best signal-tonoise perfonnance is obtained when the input amplifier gain setting is such that the fa pin has a full scale range of ±5V. The bandwidth is internally limited to typically 1kHz. making the device ideal for use in conjunction with sensors that monitor slowly varying processes. To power external functions or networks. 5mA at ±8V typical is available at the isolated port. LINEARITY PERFORMANCE. The IS0212P offers non-linearity perfonnance compatible with 12-bit resolution systems (0.025%). Note that the specification is based on a best-fit straight line. 3 5k!l -liP USING :J:VSSl TO POWER EXTERNAL CIRCUITRY The DC/DC converter in the IS0212P runs at a switching frequency of 25kHz. Internal rectification and filtering is sufficient for most applications at low frequencies or with no external networks cOMected. The ripple on ±VSSI will typically be IOOmVp-p at 25kHz. Loading the supplies will increase the ripple unless extra filtering is added externally; a capacitor of IIJF is nonnally sufficient for most applications. although in some cases 101JF may be required. Noise introduced onto ±VSSI should be decoupled to prevent degraded perfonnance. 4 Q-_-,J\N--_..,1 +VP Y,N Voor 2 Com 1 Out 6 Out Offset ~~ 5 7 lOOn 31 O.lpF 111 ~ Input Ground Plane '*' Output Ground Plana NOTES: (1) Optional voltage offset adjust components. (2) 1OpF decoupling to be used with external loads connected. FIGURE 1. Power Supply and Signal COMections Shown for Non-Inverting. Unity G.ain Configuration. Burr-Brown Ie Data Book Supplement, Vol. 33b U ::t Iz o S i '. -VSSI -VSSI = a 4-55 For Immediate Assistance, Contact Your Local Salespel'$on THEORY· OF OPERATION The IS0212P has no gaivanic connection betwee~ the. input and output. The analog input signal referenced to the input common (Coml)is multiplied by the gain of the input amplifier and accurately reproduced at the output. The output section uses a differentiai design so either the Hi or Lo pin may be referenced to the output common (Com 2). This allows simple input signal inversion while maintaining the high impedance input configuration. A simplified diagram of the IS02l2P is shown in Figure 2. The design consists of a DC/DC converter, an uncommitted input operational amplifier, a modulator circuit and a demodulator circuit. Magnetic isolation is provided by separate transformers in the power and signal paths. The DC/DC converter provides power and synchronization signals across the isolation barrier to operate the operational amplifier and modulator circuitry. It also has sufficient capacity to power external input signal conditioning networks. The uncommitted operational amplifier may be configured for signal buffering or amplification, depending on the application. The modulator converts the input signal to an amplitudemodulated AC signal that is magnetically coupled to the demodulator by a.·miniature transformer providing the signal-path isolation. The demodulator recovers the input signal from the modulated signal using a synchronous technique to minimize noise and interference. ABOUT THE BARRIER For any isolation product, barrier integrity is of paramount importance in achieving high reliability. The IS02l2P uses· miniature toroidal transformers designed to give maximum isolation performance when encapsulated with a high-dielectric-strength material. The internal component layout is designed so that circuitry associated with each side of the barrier is positioned at opposite ends of the package. Areas '. ISOLATION VOLTAGE RATINGS Because a long term test is impractical in a manufacturing situation, the generally. accepted practice is to perform a production test at. a high voltage for some shorter time. The relationship between actual test voltage and the continuous derated maximum specification is an important one. Historically, Burr-Brown has chosen a deliberately conservative one: VTFSr:= (2 XACrms continuous rating) + lOOOV for ten seconds, followed by a test at rated ACrms voltage for one minute. This choice was appropriate for conditions where system transients were not well defined. Recent improvements in high voltage stress testing have produced a more meaningful test for determining maximum permissible voltage ratings, and Burr-Brown has chosen to apply this new technology in the manufacture and testing of the IS0212P. PARTIAL DISCHARGE When an insulation defect such as a void occurs within an insulation system, the defect will display localized corona or ionization during exposure to high voltage stress. This ionization requires a higher applied voltage to start the discharge and a lower voltage to' extinguish it OIice started. The higher start voltage is known as the inception .voltage and the lower voltage is called the. theextiriction voltage. Just as the total insulation system has an biception voltage, so do the individual voids. A voltage will build up across a void until its inception voltage is reached. At this point, the void will ionize, effectively shorting itself out. This action redistributes electrical charge within the dielectric and is known as partial discharge. If the applied voltage; gradient across the device continues to rise. another partial discharge. cycle 4 Off Adjust 7 -lIP 3 38 +UP Off Adjust where high electric fields can exist are positioned in the center of the package. The result is that the di.electric strength of the barrier typically exceeds 3kVrms. OIP High Demodulator 37 8 O/PLow 31 +v"" 50kHz +VSS1 O/P 6 JlJ 34 35 -VSS1 O/P Coml· 5 32 ClockOUl Clock In Com 2 2. FIGURE 2. Simplified Diagram of Isolation Amplifier. 4-56 Burr-Brown ICData Book Supplement. Vol.33b Or, CaU Customer Service at 1-800-548-6132 (USA Only) begins. The importance of this phenomenon is that if the discharge does not occur, the insulation system retains its integrity. If the discharge begins and is allowed to continue, the action of the ions and electrons within the defect will eventually degrade any organic insulation system in which they occur. The measurement of partial discharge is both useful in rating the devices and in providing quality control of the manufacturing process. The inception voltage of these voids tends to be constant, so that the measurement of total charge being re-distributed within the dielectric is a very good indicator of the size of the voids and their likelihood of becoming an incipient failure. The bulk inception voltage, on the other hand, varies with the insulation system and the number of ionization defects. This directly establishes the absolute maximum voltage (transient) that can be applied across the test device before destructive partial discharge can begin. passed to Com 2 with a O.lJ.1F ceramic capacitor as close to the device as possible. Short leads will minimize lead inductance. A ground plane will also reduce noise problems. If a low impedance ground plane is not used, signal common lines, and either DIP High or DIP Low pin should be tied directly to the ground at the supply and Com 2 returned via a separate trace to the supply ground. To avoid gain and isolation mode (IMR) errors introduced by the external circuit, connect grounds as indicated in Figure 3. Layout practices associated with isolation amplifiers are very important. In particular, the capacitance associated with the barrier. and series resistance in the signal and reference leads, must be minimized. Any capacitance across the barrier will increase AC leakage and, in conjunction with ground line resistance. may degrade high frequency IMR. Measuring the bulk extinction voltage provides a lower, more conservative, voltage from which to derive a safe continuous rating. In production, it's acceptable to measure at a level somewhat below the expected inception voltage and then de-rate by a factor related to expectations about the system transients. The isolation amplifier has been extensively evaluated under a combination of high temperatures and high voltage to confirm its performance in this respect. The ISD212P is free of partial discharges at rated voltages. Cexr 1 Cexr. I- CEXT2 ( II I _Com 2 _...JL _ -Vee +Vcc INSTALLATION AND OPERATING INSTRUCTIONS POWER SUPPLY AND SIGNAL CONNECTIONS As with any mixed analog and digital signal component, correct decoupling and signal routing precautions must be used to optimize performance. Figure I shows the proper power supply and signal connections. Vee should be by- Burr-Brown Ie Data Book Supplement, Vol. 33b CEXTl --; 1- __ 1 Power Com I Input o.~---' Common W !! and R have a direct effect. ----~ PARTIAL DISCHARGE TESTING IN PRODUCTION Not only does this test method provide far more qualitative information about stress withstand levels than did previous stress tests, but it also provides quantitative measurements from which quality assurance and control measures can be based. Tests similar to this test have been used by some manufacturers such as those of high voltage power distribution equipment for some time, but they employed a simple measurement of RF noise to detect ionization. This method was not quantitative with regard to energy of the discharge and was not sensitive enough for small components such as isolation amplifiers. Now, however, manufacturers of HV test equipment have developed means to measure partial discharge, and VDE; the German standards group, has adopted use of this method for the testing of optc-couplers. To accommodate poorly defined transients, the part under test is exposed to a voltage that is 1.6 times the continuous rated voltage and must display <5pC partial discharge level in a 100% production test. w has minimal effect on lotal IMR. I +1 I I ..o Supply e a ~ ~ Go Z o VISO ")------1 FIGURE 3. Technique for Connecting Com I and Com 2. VOLTAGE GAIN MODIFICATIONS The uncommitted operational amplifier at the input can be used to provide gain, signal inversion, active filtering or current to voltage conversion. The standard design approach for any op-amp stage can be used; provided that the full scale voltage appearing on fa does not exceed ±5V. If the input op-amp is overdriven, ripple at the output will result. To prevent this, the feedback resistor should have a minimum value of lOW. Also, it should be noted that the current required to drive the equivalent impedance of the feedback network is supplied by the internal DC/DC converter and must be taken into account when calculating the loading added to ±VSS1 ' Since gain inversion can be incorporated in either the input or output stage of the ISD212P, it is possible to use the input amplifier in a non-inverting configuration and preserve the high impedance this configuration offers. Signal inversion at the output is easily accomplished by connecting DIP High to Com 2 instead of DIP Low. 4-57 S o !! FOI Immediate Assistance, Contact YOUI Local Salesperson ISOLATED POWER OUTPUT DRIVE CAPABILITY On the input side of the IS0212P, there are two power supplies capable of delivering 5mA at ±8V tapowerexternal circuitry. When using these supplies with external loads, it is recommended that additional decoupling in the form of 10J.lF Umtalurrt bead capacitors be added to improve the voltage regulation. Loss of linearity wi11 result if additional filtering is not used with an output load. Again, power'dissipated in the feedback loop around the input op amp must be subtracted from the available power output at ±Vss I. If the IS02)2P is to be used in mUltiple applications, care should be taken, in the design of the power distribution IS0212Ps are synchronized. It network, especiaIly when is best to use a weIl decoupled distribution point and to tilke power to individual IS0212Ps from this point ina star arrangement as shown in Figure 4. all Power In Because the frequencies of several IS02l2Ps can be marginaIly different, "beat" frequencies ranging from a few Hz to a few kHz can exist in multiple amplifier applications. The design of the IS02l2P accommodates "internal synchronous" noise, but a synchronous beat frequency noise wi11 not be strongly attenuated, especially at very low frequencies if it is introduced via the power, signal, or potential grounding paths. To overcome this problem in systems where several IS02l2Ps are used, the design aIlows'synchroniztion of each oscillator in a system to one frequency. Do this by forcing the timing node on the internal osci11ator with an external driver connected to Clk In. See Figure 5. The driver maybe an external component with Series 4000 CMOS characteristics, or one of the IS0212Ps in the system can be used as the master clock for the system. See Figure 6 and 7 for connections in multiple IS0212P installations. Track Resistance/Inductance ClOCk o-i-I---'--r---...,...-t In 39kll Clock o-+-~".=.,~ Out FIGURE 4. Recommended Decoupling and Power Distribuc tion. FIGURES. Equivalent Circuit, Clock Input/Output. Inverters are CMOS. NOISE Output noise is generated by residual components of the 25kHz carrier that have not'been removed from the signal. This noise may be reduced by adding an output low pass filter (see Figure 8). The filter time constants should be set below the carrier frequency. The output from the IS0212P is a switched capacitor aiJd requires a high impedance load to prevent degradation of linearity. Loads ofless'than lMQ wi11 cause an increase in noise at the carrier frequency and will appear as ripple in the output waveform. Since the output signal power is generated from the input side of the barrier, decoupling of the ±Vss 1 outputs wiIl improve the signal to noise ratio. SYNCHRONIZATION, OF THE INTERNAL OSCILLATOR The IS02l2P has an internal osci11ator and associated timing components, which can be synchronized, incorporated into the design. This aIleviates the requirement for an external high-power clock driver. The typical frequency of osci11ation is 50kHz. The internal clock will start when power is applied to the IS0212P and Clk In is not connected. 4-58 OV +15V Sync, FIGURE 6.0sci11ator Connections for Synchronous Operation in Multiple IS02l2P InstaIlations. CHARGE ISOLATION When more than one IS0212Pis used in synchronous mode, the charge which is returned from the timing capacitor (220pF in Figure 5) on each transition of the clock becomes Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) low height (0.43" (I Imm» and small footprint (2.5" X0.33" (57mm X 8mm) ) make it the solution of choice in 0.5" board spacing systems and in all applications where board area savings are critical. The IS0212P operates from a single + 15V supply and offers low power consumption and 12-bit accuracy. On the input side, two isolated power supplies capable of supplying SmA at ±8V are available to power external circuitry. As .. .;; ::;; . ~ > ril '"!t J!! UI '"..1; iii ... > ril APPLICATIONS FLEXIBILITY '00 ~ FIGURE 7. Isolating the Clk Out Node. significant. Figure 7 illustrates a method of isolating the "Clk Out" clamp diodes (Figure 5) from this charge. A 22kQ resistor (recommended maximum to use) together with the 39kQ internal oscillator timing resistor (Figure 5) forms a potential divider. The ratio of these resistors should be greater than 0.6 which ensures that the input voltage triggers the inverter connected to "Clk In". If using a single resistor, then account must be taken of the paralleled timing resistors. This means that the 22kQ resistor must be halved to drive two IS0212Ps, or divided by 8 if driving 8 IS02I 2Ps to insure that the ratio of greater than 0.6 is maintained. The series resistors shown in Figure 7 reduce the high frequency content of the power supply current. APPLICATIONS The IS0212P isolation amplifier, together with a few low cost components, can isolate and accurately convert a 4-to20mA input to a ±10V output with no external adjustment. Its In Figure 8, the IS0212P's +V", isolated supply powers a REF200 to provide an accurate 100J,LA current source. This current is opposed by an equal but opposite current through the 75kQ feedback resistor to establish an offset of -7.5V at I., = OmA. With I., =4-to-20mA, the output is -5 to +5V. The ratio of the 75kQ and 3.12kQ resistors assures the correct gain. The polarity of the output can be reversed by simply reversing the OIP HI and OIP LO pins. This could be used in the Figure 8 circuit to change the -5V to +5V output to a +5V to -5V output range. The primary function of the output circuitry is to add gain to produce a ± I OV output and to reduce output impedance. The addition of a few resistors and capacitors provides a low pass filter with a cut-off frequency equal to the full signal bandwidth of the IS0212P, typically 200Hz. The filter response is flat to IdB and rolls off from cut off at -12dB per octave; - The accuracy of the REF200 and external resistors eliminates the need for expensive trim pots and adjustments. The errors introduced by the external circuitry only add about 10% of the IS0212P's specified gain and offset voltage error. S.BnF (10%) +15V 100kn 100kll (5%) (5%) { 4mA to 20mA } -10V10 +10V { 4mA to 20mA } -5Vto +5V NOTE: All resistors are 0.1 % unless otherwise stated. FIGURE 8. Isolated 4-20mA Current Receiver with Output Filter. Burr-Brown Ie Data Book Supplement, Vol. 33b 4-59 For· Immediate Assistance, Contact Your Local Salesperson 99.9kll +15V VOUT • e.g., strain gauge, pressure transducer, RTD, gas detection and analysis. FiGURE 9. Instrument Bridge Isolation Amplifier. +15V 100kll . 250kll Siemens BPW21 ,-VISO" OPAI28J FIGURE /0. Photodiode Isolation Amplifier. +15V lkll lMn IN914 K-type Down-5cale Burnout Indication , r----------------------------------------~ : : Ground Loop Through Conduit \ : : ------------------------------------------ FIGURE II. Thermocouple Amplifier with Ground Loop Elimination, Cold Junction Compensation and Down-Scale Bum-Out. 4-60 . Burr-BrownlCData BookSupplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) 10011n +15V V D ~ 50mV (FB) OC _ _ or _ _ 90kn 3-Phase V-Connected Power Transformer FIGURE 12. Isolated Current Monitoring Applications. +15V 200~A! 1t05V r-----------------~---4 PT100 -200'C to 850'C FIGURE 13. Isolated temperature Sensing and Amplification. Burr-Brown Ie Data Book Supplement, Vol.33b 4-61 For Immediate .Assistance, Contact Your Local Salesperson BURR-BROWW • IElElI I PWS727 PWS728 ", . \', t LtH\' ':.' i< " >1>, Isolated, Unregulated DC/DC CONVERTERS FEATURES APPLICATIONS • 100% TESTED FOR HIGH VOLTAGE BREAKDOWN • INDUSTRIAL PROCESS CONTROL • COMPACT (28-pin DIP) • POINT-OF-USE ANALOG POWER • GROUND LOOP ELIMINATION • 5V OR 15V INPUT OPTIONS • SYNCHRONIZABLE (TTL) DESCRIPTION The PWS727 is a DC/DC converter which uses minimal PC board space and converts a single input 10 to 18VDC to bipolar voltages of the same value as the input. The PWS728 converts a 4.7 to 6VDC to bipolar voltages three times the value of the input. The converters are capable of providing ±15mA (PWS727) or ±12mA (PWS728) at rated voltage and up to BOmA. it possible to minimize the transformer size. The transformer is composed of a split bobbin isolation transformer using a ferrite core and is encapsulated in a plastic package, allowing a higher isolation voltage rating. The design minimizes high frequency radiated noise on the output by using a ground plane directly under the high frequency components. The PWS727 and PWS728 use a high-frequency (800kHz nominal) surface mount oscillator that makes Sync 2 ~~+--o~~~>-~~~ -vo 16 17 TTLour InputGnd • Use a 10V zener on PWS728 to prevent input spikes overstressing the diode bridge. 27 15 Enable OulputGnd TTLIN (Typical Connection) international Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (602) 746-1111 • Twx: 911).952-1111 • cable: BBRCORP , • Tucson, AZ 85734 • Street Address: 6730 S. TUcson BlVd. • TUCICIII, AZ 857116 Telex: 066-6491 ' FAX: (602)8JI9.1510 • Immedlala Product Info: (8DO)54&of132 P05-987 4-62 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL At Y'N aI5VOC. Output Load. ±15mA .(PWS727) and T•• +25'C unless otherwise noted. Or Vw a 5VOC. Output Load _±12mA (PWS728) and T•• +25'C unless otherwise noted PWS727 PARAMETER ISOLATION Voltage Rated Continuous AC 60Hz 100% Tes¥" Barrier Impedance Leakage Current at 60Hz CONDmONS MIN 60Hz. 1s. <5pC PO 750 1200 OUTPUT Rated Output Voltage Current Regulation (single ended load change) Sensitivity Balance Ripple Voltage OUlput Switching Noise Oulput Voltage Temp Coefflclent Sync Sync Frequency'" 10"118 1 VISO a 240Vrms. 60Hz INPUT Rated Voltage VoHage Range Current Current Ripple CurrentUmit TIt,..I H I, VH V. Frequency Range TIL"ur·lo.. TVP PWS728 MAX MIN 55 2.5 18 65 4.5 · 2.0 .8 2.5 15 +10 = 7.5 -15mA. -10= 15mA V",= 10to 18 V 15.0 15 6 130 110 7.5 -1 14.25 · 5 250 10 1 MAX · 1.5 15 10 TVP ·· ·· · · · 15.75 30 · 12 TEMPERATURE RANGE SpeclRCailon ~~:~on 15 V V MHz mA 30 VOC mA 1.13 3.8 VN mV mVpp mVpp 25 800 · 201140 875 vrc · 70 85 85 · knllpF kHz · ·C ·C ·C NOTE: (1) Tested at 1.6 x rated. fallon 5pC partial discharge leakage current on 5 succasslve pulses. (2) Nominal with pin 17 grounded. ORDERING INFORMATION PIN CONFIGURATION Basic Model Number _ _ _ _ _ _ _ _ _ _ _ PWS727I PWS728. Sync ABSOLUTE MAXIMUM RATINGS Supply Voltage ..................................................................................... 18V Continuous Isolation Voltage ....................................................... 750Vnns Junction Temperature ..................................................................... +150·C Storage T~mperature ......................................................................... 85·C Lead Temperature (Solder. lOs) ...................................................... 3000C Oulput Short to Common ......................................................... Continuous Max Load. Sum of Both Outputs ....................................................... SOmA NC Vo Burr-Brown Ie Data Book Supplement. Vol.33b OulputGnd NC NC NC TIL... InputGnd TIL"." +V" Enable ... = j:: ~ en f IIA mVimA loading 0 -40 -40 V V mA mAp·p mAp-p nA 135 10 20 .05 725 Vrms Vrms nllpF IlAnns 45 15 At Switching Frequency >800kHz UNITS 4-63 = a C,) :::a ia. Z -S 0 For··lmmediate Assistance, Contact Your· Local Salesperson MECHANICAL 0 DD 1 go j 28-Pln Double - Wide DIP '" 000 A 0 o DIM A B C G H K L "' 000.0 . D 0000 INCHES MIN MAX 1.440 1.460 .690 .710 .390 .410 .100 BASIC ,020 BASIC .190 .210 .600 BASIC NOTE: Leads in true position within 0.01" (O.25mm) R a1 MMC a1 seating plane. MILUMETERS MIN MAX 36.58 37.08 17.53 16.03 9.91 10.41 2.54 BASIC 0.51 BASIC 4.83 5.33 15.24 BASIC C ~~==~~~;?-I K ---.-l TYPICAL PERFORMANCE CURVES T. =+25OC, V~ =15VDC, ILOAD = ±15mA (PWS727),'or v,. = 5VDC, output load = ±12mA (PWS728) unless otherwise noted. PWS728 LINE REGULATION 5.4 5.3 V 5.2 ~ 5.1 > 5.0 ~ 4.9 ~ S / / 4.8 V . PWS727 LINE REGULATION 18 / ~ ./ 15 ~ 14 .s 13 > ~ ,/' ....,/ 12 ./ 11 / 4.6 I 16 / / 4.7 / .17 L '" V V ... 10 13 14 15 16 17 18 10 11 12 13 14 15. 16 17 18 ±VOUT (V) ±VOUT (V) OUTPUT RIPPLE VOLTAGE PWS727 AND PWS728 LOAD LINES 50 20 1\\ \\ ,\. ~ 5 :? +t l \.\ ......... - PWS727 """~ /' ~ ./ 20 ....... 10 ........... PWS728 o 10 o 5 10 15 Load (mA) 4-64 Ripple Frequency = Oscillator Frequency 30 ~ 15 .i 40 20 25 30 0.0 0.2 0.4 0.6 0.8 1.0 Finer Capacitance (~F) Burr-Brown Ie Data Book Supplement,Yol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES (CONT) THEORY OF OPERATION TA = +25'C. v," =15VDC, leo,. =±15mA (PWS727). or Vw =5VDC. output load = ±12mA (PWS728) unless otherwise noted. The PWS727 and PWS728 are composed of the PWS750 building blocks which are assembled along with some standard components to build an isolated push pull DC/DC converter. EFFICIENCY/LOAD CURVE 80 PWS7~ 70 ~ 60 II ~ lii ~ 50 w / 40 30 o / IV / / to 5 --- ./' L PWS727 AND PWS728 PIN FUNCTIONS -....... V /" ......... 15 ""'- V PWS727 20 25 30 Load Current (±mA) OUTPUT VOLTAGE DRIFT WITH A ±15mA LOAD 15.5 15.25 !=; >0 15.0 ~ v "" '-. 14.75 14.5 -25 o 25 50 75 100 Temperature ('C) TIL IN SIGNAL DUTY CYCLE 100 . 75 g, 0 ~ 50 0 1f. 25 0 0 1.5 2 2.5 Load Current (±mA) Burr-Brown Ie Data Book Supplement, Vol.33b TILIN is used to optionally control the frequency of the oscillator with an external TIL level frequency source. The input frequency must be twice the desired driver frequency, since there is an internal divide by 2 circuit to produce a 50% duty cycle output. The input duty cycle can vary from 12% to 95%, (see the Typical Performance Curves). When in the free running mode the TTLIN pin must be tied to ground. TTLoUT is used to synchronize the outputs of multiple PWS727s and/or PWS728s to minimize beat frequency problem. s if desired. A standard open collector output is pro- _ vided, therefore a 330 to 3.3W resistor will be necessary, depending on the amount of stray capacitance on the TILIN line. A maximum of 8 PWS727s or PWS728s can be connected without the use of an external TIL buffer. Connect the TILOUT of a master unit to the TTLIN of the slave units. An Enable pin is provided so that the driver can be shut down to minimize power use if required. A TIL low applied to the pin will shut down the driver within one cycle (1.251lS). A TIL high will enable driver outputs within one cycle. The TTLoUT will still have an 800kHz signal when a master driver is disabled, so other synchronized drivers will not be shut down. The pin can be left open for normal operation. The +VIN pin supplies power to the converter. The VD pin connects the power to the transformer through the internal overcurrent sense resister. The other end of the overcurrent sense resister is tied to +VIN' A 0.3!JF bypass capacitor must be connected to the VD pin to reduce the ripple current through the shunt resistor, otherwise false current limit conditions can occur due to ripple voltage peaks. During overload conditions the output drive shuts off for approximately 80j.lS, then turns back on for 20llS, resulting in a 25% power up duty cycle. If the overload condition still exists, then the output will shut off again. When the fault or the excessive load is removed, the converter resumes normal operation. The Sync pin can be used to synchronize the internal oscillator of an IS0120 to the operating frequency of the converter. The Sync pin is connected directly to the secondary of the transformer, so an 800kHz square wave of twice the output magnitude is present. Minimum pc board trace length should be used to minimize loading the transformer. When making the connection to the IS0120, a simple frequency divider circuit (see Figure 3) is necessary to match the 400kHz nominal frequency required by the IS0120. If this function is not used, leave the pin disconnected. 4-65 ~ For Immediate Assistance, Contact Your Local Salesperson +5V Ref· _---1.!r--=.:..I-.-=7 ~p \\ Can be up to 100 feet for remote sensing. I FF1 401<0 Bus I I a- -15V_-----+ +15V _ _ _ _ __;-_+ ~ Com_.....:..----l-+--. t 12·bit "nearity, 20~ conversion time Is possible with this circuit High Voltage ~arrier 12 T O.3~F NOTE: See page 276 of the Burr·Brown Handbook 01 Unear Applications lordetalls olthe counter operation. ~. . FIGURE.!. Isolated Integrated NO, ~onverSion System Using Ratiometric Counting and Microprocessor Interface. Operating . from a Single 5V Supply. O.3~F O.3~F 10~F 10~F +V'N 14 ,.-='----, r--112)!8...,.,_____-.J : RLoad +Vo . 26 , O.3~F 1'2:.:.7_ _ _ _ _ _-,-_ _ _- - . Output Gnd Input Gnd TTL IN Regulated Vo = R, + R. • VREF R. FIGURE 2. Regulated Output Using the Enable Pin to Cycle the Converter Output On and Off. '. 4-66 '. . Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) l000pF 1: 11000pF '& Response Signal In 21 Response Signal Out 24 4 -v Gnd o---- IOOmA) are needed to tum on the gates. ~~ If the total output current drawn by all the channels exceeds 2S0mA. then it will be necessary to circumvent the current limit circuit by leaving the VD pin of the PWS7S0-lU open. and connect the VD pin of the PWS7S0-2U directly to the supply. 5V OPERAl10N With SV operation. the transformer winding current ratio is 3:1. therefore generating much greater currents in the primary. The input ripple voltage will be larger. so an input pi filter will be necessary to isolate the converter noise from the rest of the circuit. For example. when the output is ±lSmA the input current will be at least 120mA. OUTPUT CURRENT RAl1NG The PWS7S0-1 U oscillator contains soft start circuitry to protect the FErs from high inrush currents during tum on. The internal input current limit is 250mA peak to prevent thermal overload of the MOSFETs. The maximum output rating is ±30mA. Total current. which can be drawn from each isolation channel. is the total of the power being drawn froni both the +V and -V outputs. For example. if one output is not used. then maximum current can be drawn from the other output. In all cases the maximum current that can be drawn from any individual channel is: 1+loUTI + !-IOUT1 < 60mA It should be noted that many analog circuit functions do not simultaneously draw equal current from both the positive and negative supplies. When mUltiple channel operation is used. the maximum current of all channels must be reduced to prevent the overcurrent limit to trip. Alternately. bypass the overcurrent by ______JL-!3r---------~~~~ O.3pF 1~H ----------------------------------------------, ~-J~ry'-~----~Hh ~O~D 5 User Option O.3pF G PWS750-2U PWS750-3U O.3pF J 6l-+-~-o-Vo O3PF • G L-====~ Output Gnd Duplicate lor Up to 8 Channels FIGURE 3. MOSFET Driver Booster Circuits. Burr-Brown Ie Data Book Supplement, Vol. 33b 4-77 For Immediate Assistance, Contact Your Local Salesperson leaving the VD pin of the PWS750-1 U open and connecting the VD pin of the PWS750-2U directly to the supply. HIGH VOLTAGE TESTING Burr-Brown Corporation has adopted a partial discharge test criterion that confonns to the German VDE0884 optocoupIer standard. This method requires that less than 5pC partial discharge crosses the isolation barrier with 1200Vnns 60Hz applied. This criterion confinns transient overvoltage (1.5 X 750Vrms) protection without damage to the PWS750-2U or PWS750-4U. Life test results verify the absence of high voltage breakdown under continuous rated voltage and maximum temperature. The minimum AC barrier voltage that initiates partial discharge above 5pC is defined as the "inception voltage." Decreasing the barrier voltage to a lower level is required before partial discharge ceases; this.is known as "extinction voltage." We have developed a package insulation system to yield an inception voltage greater than 1200Vnns so that transient voltages below this level will not damage the isolation barrier. The extinction voltage is above 750Vnns so that even overvoltage-induced partial discharge will cease once the barrier voltage is reduced to the rated value. Previous high voltage test methods relied on applying a large· enough overvoltage (above rating) to break down marginal units. but not so high as to permanently damage good ones. Our partial discharge testing gives us more confidence in barrier reliability than brealcdownlno brealcdown criteria. PWR75O-1U 16~_ 7 9 Vwr 10 2 PWS750-2U 2 7 4 PWS75O-2U 1 3 2 PWS7511-2U ~7r--~-l--h-r--r71 2 1 4 3 PWS75O-3U PWS75O-3U Jl vwr~ 1S0122P 1S0122P FIGURE 4. Four-Channels of ±IOV Signallsolalion with Channel-to-Channellsolation. 4-78 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) 10~H 4 7. 3 T 5V 6 3 7 2 PWS750-3U PWS75G-IU 16 S T 14 O.3~F ~ O.3~F 6 14 } Powerlor 3 O.3~F PWS75o-3U ~ I 7 Powarlor { oUlput circuitry 2 Input signal condllloning circuitry 6 o---t--+-----, V.. :tl0V FIGURE 5. A Complete ±lOV Signal Acquisition System Operating From a Single 5V Supply. H7F T07-14-3.5 I~F -- leomA 3Tums TN0604 +5V o 7 G VD PWS75G-IU s 3 O.3~F 14 ~ Gnd ~ T1l.ln 47pF FIGURE 6. A PWS750 Driver Can Be Used to Boost the Input Voltage to 15V to Power a PWS726 From a 5V Supply. Burr-Brown Ie Data Book Supplement, Vol. 33b 4-79 For linmediateAssistance, Contact Your Local Salesperson Power for ~UI signal conditioning circuits -v +V Vour:l:l0V 0-.....-< 10pH +Vo 7. 5V PWS75CJ.3U PWS75O-1U 6 -Yo -:- O.3I1F G.3pF I G 3 5 4 8 3 7 2 4 PWS75CJ.3U -:- -:- FIGURE 7. Powering the Internally Powered ISOl03 Isolation Buffer From a Single 5V Supply. Two Power Channels Are Necessary to Provide the SOmA Nominal for the +V of the ISOl03. 10pH PWS740-2 +VJN 0-+--,7.~ PWS75O-1U I°.3pF 2N70G8 _ 16 - D G Ou1put Goo FIGURE S. l500VAC Isolation Using PWS740-2 Transformer. 4-80 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) 2N7010 T 7 G 0 16 -:PWS75O-1U 2N7010 T G 0 S -:- O.3pF r---- ------------------------------, Dupllcata lor up to 8 Channels PWS750-2U 10pH 5 4 3 6 :;!; +Vo PWS75HU O.3pF 7 6 -VO - 0u1put • Gild ____________________________________ JI FIGURE 9. FET Pair Driving Up to Eight·Channels. Burr-Brown Ie Data Book Supplement, Vol. 33b 4-81 ANALOG CIRCUIT FUNCTIONS Analog circuits act as building blocks with which to perform a variety of instrumentation, computation, and control functions. They provide a broad range of versatile, proven, and ready to use computational functions for the designer to use in developing simple or complex systems. The analog circuit functions include multipliers, dividers, multifunction converters, true rms-toDC converters, logarithmic amplifiers, voltage and window comparators, peak detectors, precision oscillators, and filters. The multifunction converters also provide multiply, divide, square root, exponentiation, roots, sine, cosine, arctangent, vector magnitude rms-to-DC and logarithmic amplifier functions. 5 . The availability of these relatively complex functions as precise, versatile, easy-to-use, low-cost building blocks has broadened the scope of practical analog circuit systems and greatly simplified analog circuit designs. The names of most analog circuit functions are self-explanatory and describe the main functions they perform. The functions are used mostly for processing and/or conditioning of analog signals, and for simulation of algebraic and/or trigonometric analog computations. The variety of applications these functions are effectively used for is limited only by the designer's creative imagination. Some of the interesting applications for which analog circuit functions have found wide acceptance are listed in the table on the following page. Burr-Brown Ie Data Book Supplement, Vol. 33b 5-1 For Immediate Assistance, Contact Your Local Salesperson Types of Application Recommended Analog Cln:ult Function Analog simulation Algebraic and trigonometric computations Power series approximation, function fitting and linearizing Analog wave shaping Multiplier, Divider, Multifunction Converter, Logarithmic Amplifier, OscIllator veo and AGC applications Multiplier, Divider Vector computation Power and energy measurements Modulation and demodulation Signal compression Log-antilog-log ratio computations Ught-related measurements Analog signal conditioning Instrumentation and control systems Test equipment Transducer excitation Signal reference Alarm circuits Bang-bang control applications Control of limit stops Analog memory and peak detection Multifunction Converter, Multiplier Multiplier, rms-to-DC Converter Multiplier, Divider logarithmic Amplifier logarithmic Amplmer Logarithmic Amplifier All circuit functions All circuit functions All circuit functions Oscillator Oscillator Voltage,and Window Comparators Voltage and Window Comparators Voltage and Window Comparators Peak Detection ANALOG CIRCUIT FUNCTIONS SELECTION GUIDES The Selection Guides show parameters for the high grade. Referto the Product Data Sheet for a full selection of grades. Models shown in boldface are new products introduced since publication of the previous Burr-Brown IC Data Book. MULTIPLIERS/DIVIDERS You can select accuracy from 0.25% max and up from this complete line of integrated circuit multipliers. Most provide full four-quadrant multiplication. All are laser-trimmed for accuracy-no trim pots are needed to meet specified perfonnance. These compact models bring the cost ofhigb perfonnancedown to acceptable levels. 5-2 Burr-Brown IC Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) Boldface = NEW MULTIPLIERSIDIVIDERS Error at +25·C max(%) Temp CoeH Feedthrough (my) Offaet Voltage (mY) Temp Rangell) Pkg Page No. 70 Ind TO-100 5-26 3MHz Com T0-100 5-34 10MHz Ind DIP 85-25 2 10MHz Ind T0-100 5-41 0.3% 25 10MHz Ind 0.15 15 50 Ind Model Transfer Function MPY100 [(X,-X.) (Y,-Y.) 110] + Z. ±a.5 O.ooa 30 7 MPY534 [(X ,-X.) (Y,-Y.) 110] + Z. ±a.25 0.008 0.05% 2 MPY600AP [(X,-l'a) (V,-YJ /2J + Z. ±O.25 0.02 2 5 MPY634M [(X,-X.) (V,-V.) 110] + Z. ±a.5 0.015 0.15% MPY634P,U [(X,-X.) (V,-Y.) /10] + Z. ±2.0 0.03 [(X,-X.) (Y,-Y.) /10] + Z. ±a.5 0.01 AD632 (%I·C) 1% BW (kHz) DIP,SOIC 5-41 T0-1oo 5-6 NOTE: (1) Com - O·C to +70·C, Ind - -25·C to +85·C. SPECIAL FUNCTIONS This group of models offers many different functions that are the quick, easy way to solve a wide variety of analog computational problems. Most are in integrated circuit packages and are laser-trimmed for excellent accuracy. SPECIAL FUNCTIONS Temp Range(l) Pkg Page No. Ind DIP 5-109 Optimized for log ratio of current inputs. Specified over six decades of input (1nA to 1mAl, 55mV total error, 0.25% log conformity. Com DIP 5-18 A more versatile part that contains an internal reference and a current inverter. 1% and 0.5% accuracy. Com Function Model Description Comments MullHunction Converter 4302 y(Z/X)m This function may be used to multiply, divide. raise to powers, take roots and form sine and cosine functions. K Log (1,11.) Plastic Package. LOG 100 Logarithmic Amplifier 1 -J T T 2 0 4127G 4341 E (t)dt IN K Log (I,IIREF) Switched Integrator ACF2101 This Is a dual, Integrating, Includes HOLD and translmpedance amplifier that RESET switches and converts an Input current to an output multiplexer. output voltage by Integrating the current for a uaer determined period V =_.l. Ii dt OUT c IN of time. Eliminates large feedback reSistor of traditional I to V converters. DIP 5-102 Ind DIP 5-115 =» Ii!- U ~z C Ind DIP, SOIC 85-14 DIP S5-6 NOTE: (1) Com _ O·C to +70·C. Ind. -25·C to +85·C. Burr-Brown Ie Data Book Supplement, Vol. 33b U Z a Propagation delay: 5ns, Ind max for 100mV overdrive A dual comparator with high common-mode Input range. Latched ECl outputs, ±5V supplies. ... ...-=» Some extemal trimmlng required. Lower cost In plastic package. CMP100 Z II. True rms-to-DC conversion based on a log-antilog occupational approach. Pin compatible with 4340. HighSpeed Window Comparator. ATE Pin Receiver •52 5-3 For Immediate Assistance, . Contact Your Local Salesperson DIVIDERS Using a special log/antilog committed divider design overcomes the major problem encountered when trying to use a multiplier in a divider circuit. Outstanding accuracy is maintained even at very low denominator voltages. DIVIDERS Model Transfer Function Input Range DIV100P 10 x N/D 250mV to 10V Accuracy D=250mV max""') Temp Coeff (%PC) 0.5% BW (kHz) Rated Oulput,mln Temp RangeU) Pkg No. 0.25 0.2 15 ±10V.±5mA Ind DIP 5-10 Page NOTE: (1) Ind .. ,..-25°C io +85°C. FREQUENCY PRODUCTS This group of products consists of precision oscillators and active filters for both signal generation and attenuation. Both fixed frequency and userselected frequency units are available. FREQUENCY PRODUCTS Boldface =NEW Temp Range") Pkg No. Com DIP 5-119 These filters provide a complex Add only resistors to determine pole Ind pole pair. Based on state variable location (frequency and Q). Easily Ind approach, low-pass, hlgh-pass, cascaded for complex filter responses.lnd and bandpass oulputs are available. DIP DIP DIP S5-45 Function Model Description· Comments Oscillator 4423 Very low cost in plastic package. Provides resistor-programmable quadrature outputs (sine and cosine wave outputs simultaneouslyavailable). Frequency range: 0.002Hz to 20kHz. Frequency stability: 0.01 %l"C. Quadrature phase error: ±D.1"•. Universal Active Filter UAF42 UAF41 UAF21 Page 5-82 5-74 NOTE: Com = O°C to +70"C. Ind .. -25°C to +85°C. 5-4 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) VOLTAGE REFERENCE These products are precision voltage references that provide a +1OV output. The output can be adjusted with minimal effect on drift or stability. Boldface = NEW VOLTAGE REFERENCE MIn Output (mA) Model Output (V) REF10M REF101M ±10.00 ±O.OOS ±1 0.00 ±D.OOS 10 10 REF102M REF102P,U ±10.00 ±D.OO25 ±10.00 ±D.GOS 10 10 MaxDrHt (ppml"C) 2.5 5 Power Supply (V) (mA) Temp Rangel') Pkg Page No. +13.5135 +13.5135 4.5 4.5 Com Com T0-99 TO·99 5-49 5·55 +11A/36 +11A/36 1A 1A Ind,MII Ind T()'89 DIP;SOIC 85-37 85-37 NOTE: (1) Com. O"C to +70°C. Ind - -25°C to +8SoC. MiI- -55°C to +12SoC. Boldface = NEW CURRENT REFERENCE Output I (JlA) MaxDrHt Compliance (ppml"C) REF200M,P, Dual U 100±D.S 2.SVto 40V 25 Model Comments Includes 0.5"10 accurate current mirror Temp Range(') Ind Page Pkg DIP, To-99, SOIC 5·63 5-63 NOTE: (1) Ind = -25°C to +8Soc. Burr-Brown Ie Data Book Supplement, Vol. 33b 5-5 For Immediate Assistance, Contact Your Local Salesperson ACF2101 ADVANCEINFORMAnON SUBJECT TO· CHANGE Low NQise, Dual SWITCHED INTEGRATOR FEATURES • INCLUDES INTEGRAnON CAPACITOR, RESET AND HOLD SWITCHES, AND OUTPUT MULnPLEXER • LOW NOISE: 10~Vrrns • LOW CHARGE TRANSFER: • LOW DROOP: 2nVl~ supplies. the , , supplies up to ±18VDC. plastic DIP and SOIC DItIIP Burr-Brown Corp. InIemItlonllAlrparllndUltrlllPl/lc ' IIII1ngAddrns:POBcnrI1400 • r-,AZ85734 ' SlllltAdchll:mas. r-1IIId. ' r-,AZ 8I1I1II TIl:(802)746-1111 , Twx:81M52-1111 ' CIbII:B8RCORP ' Tlln:1JII&.f4I1 ' FAX:(802).'5'0 ' mmedlIIIl'laduclWo:(8IIO)I4M13Z PD5-I078 5-6 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL _ +25'C, V+- +5V, V-_-15V,lntemaIC. CONDntONS INPUT RANGE Inpul Current Range Switched Input Direct Input UNITS o +100 +1 o jIA rnA INPUT IMPEDANCE Switched Input Hold Switch OFF Hold Switch ON Direct Input ..; GO kn o HOLDSWITCH Hold Switch mV OFFSET VOLTAGE Input Offset Voltage Average Drift II. mV ~ p'vrc Logic Family V.. (Logic 1 • Switch OFF) V. (Logic 0 • Switch ON) I.. I. Switching Speed Switch ON Switch OFF V V jIA jIA ns ns V OUT =-liCII I N dt· V V/J1S 5 3 1 V/J1S J1S J1S 5 J1S J1S 100 0.5 20 50 100 2 MODES OF OPERATION Switch Integrate Mode Hold Mode Reset Mode Hold ON Reset OFF OFF ON ON/OFF pF 2 % ppmrc GO kn OFF (Logic 1 _ OFF, Logic 0 • ON) Burr-Brown Ie Data Book Supplement. Vol.33b 5-7 .For Immediate Assistance,. Contact. Your Local Salesperson ELECTRICAL (CONT) TA - +2500. v+ - +5V, V---ISV,lnlemal c- lOOpF, UNRS Voltage Output Range CUnnt Output. Direct Output Shon Clrcun CUnnt Direct Output Switched Output OuIput Impedance Direct Output SwItched Output Select Swltc:h ON Select SwIt::h OFF Loed Capacitance Stability Direct Output Swltc:hed Output +0.1 :!:5 -10 V rnA :125 :!:5 rnA rnA n . 0.1 nil pF 250nS 10011 5 GnllpF Nonlinearity Channel Separation Op ArrlI Bias Current Hold Mode Droop Integral8 .Mode Droop Voltage Offset Value Temperature Coefftclent Power mV l1V1oo dB I1Vnns joVnns I1Ynns 0.1 0.1 I I pC terC mV I1VfOC 0.1 0.1 I I pC terC mV I1VI"i:: 0.1 0.1 I I pC terC mV +5,-15 +4.5 -10 For Dual For Dual SpecIfication OperaUon Storage Thermal Resistance . Junction to AmbIent 12 3 -40 -40 -40 V +18 -18 V· V IS 4 rnA rnA +85 00 00 00 OCIW +125 +125 40 NOTES: (I) FSR Is Full Scale Range - lOV (0 to -IOV). (2) Total noise Is nns 10taI 01 noise for the modes of operation used. (3) Includes noise from aD modes of operation. (4) capacitance of sensor connecllld to ACF2101 Input; C -integration capacitance. (5) Errors ClllBI8d when the Internal switches are driven from one mode to another. (6) The charge transfer Is O.IpC; for an Inlagratlon cepacltance 01 lOOpF, the resull8nt charge oIIseI voltage error Is ImV. c.. - ORDERING INFORMATION MODEL PACKAGE SPECIFIED TEMP. RANGE ACF210lBP ACF210lBU Plastic DIP Plastic SOIC -4OOC to +65OC -4OOC to +85OC 5-8 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) MECHANICAL P Package - 24-Pln Single Wide Plastic DIP I-'----A ----'1 DIM A B INCHES MIN MAX 1.125 1.255 .250 .290 MIWMETERS MIN MAX 28.58 31.88 &.35 7:37 C D E F G .150 .170 .010 .OBO .100 BASIC .050 .070 4.32 2.03 2.54BAStC 1.27 1.78 DIM H J K INCHES MIN MAX .018 .020 .125 NlA :300 BASIC 3.81 L D.25 M N .oos 15· .015 P .010 .Q3O 0" MIWMETERS MIN MAX 0041 0.51 3.18 NlA 7.82 BASIC o· 0.20 0.25 15· 0.38 0.78 NOTE: Leads In bUe posIIIon wHltln 0.01" (0.25mm) R al MMC at seating plane. Pin numbers relerence only. ... o ; IL ~ NOTE: Leads In bUe posIUon within 0.01" (O.25mm) R at MMC at seaUng plane. Pin numbers shown lor reference only. Numbers may not bemarkadon package. •g Z t; Z :) IL l- S iCo) a 9 i OutpulShort Power Operating Teml08"ttura Storage Temperature to +125·C Junction Temperalure ................. :................................................... +15O"C Lead Temperature (soldering; 1Os) ................................................ +3OO"C Burr-Brown Ie Data Book Supplement, Vol. 33b 5-9 For Immediate Assistance, Contact Your Local Salesperson PIN CONFIGURATION Top View Figure la iIIu:stralles."t tion. Figure I b iIIustn'!es capacitors and input Leakage currents between easily exceed the input circuit board "guard" surrounding critical low impedance Leakage will . Figure 3 guard critical should also be Improper handling or tamination from handling removed with cleaning solvents and de-ionized water. -L -=- v+ These points musl be connected to a common ground point or a ground plane. Power Supplies The ACF2101 can operate from supplies that range from +4.SV and -IOV to ±18V. Since the output voltage integrates negatively from ground. a positive supply of +SV is sufficient to attain specified performance. Using +SV and ISV power supplies reduces power dissipation by one-half of that at ±ISV. 5-10 FIGURE la. Basic Circuit Connections. Power supply connections should be bypassed with good high-frequency capacitors. such as I~ solid tantalum capacitors. positioned close to the power supply pins. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) MODES OF OPERATION The three basic modes of opemtion of each integmtor are controlled by the Hold and Reset switches. In Integmte mode. the output voltage integmtes negatively toward -IOV. In Hold mode. the output voltage remains at the present value. except for output droop. In Reset mode. the integmtion capacitor is discharged and the output voltage is driven to analog common. See Figure 4. .. o Z; II. ~ Board Layout Showing "Guard" Tmces for Input. Both top and bottom of board should be guarded. Cap 0-11-;"'--1 In Sw In O-I--i-- -101-.--'-----;-+-+-+--...... o-I-O-~t '-'"'"..,... ,n..L..r. Sw OUI Com o-t---+----' ~~I------'-----;oiI~; RESET ONI-._ _ _ _ _ _ _ _ _ FIGURE 2. Switch Control Lines on One Channel of Two in ACF2101. ~:: ----l _ _ _ _...... MODES OF OPERATION FIGURE 4. Modes of Opemtion. Burr-Brown Ie Data Book Supplement, Vol. 33b 5-11 For Immediate Assistance, Contact Your Local Salesperson SwrrCHES Each integrator includes four switches: a Hold switch. a Reset switch. and two OIitput Select switches. See Figure 2. Hold and Reset SWhches 1be Hold switch is intended for low voltage applications. and care must be taken to insure that no more than lOOmV are applied across the switch when it is in the off state. To use the Hold switch. connect the input current to the "Sw In" pin. The Hold switch disconnects the input current. and holds the output voltage at a fixed level. For direct input. connect the input current to the "In" pin that bypasses the Hold switch and connects directly to the input summing junction. If the Hold switch is not used. the switch should be in the off mode and the "Sw In" pin should be connected analog common. integration capacitor. it must be carefully selected. An external integration capacitor should have low voltage coefficient. temperature coefficient. memory. and leakage current. The optimum selection depends upon the requirements of the specific application. Suitable types include NPO ceramic. polyearbonate. polystyrene. and silver mica. If the internal integration capacitor is not used, the CAP pin should be connected to common. NOISE The Reset switch is used to discharge the integration tor before the start of a new integration period. Select SwItches 1be two Select switches can be used to when multiple integrators are Figure 5 shows a number ofl...... r '" I U II ~ into an NO converter.1be ~W""W".,,.,,,:""'"'' by the S~lect switch "on" resi~ance~,of output capacitance. The ACF2101 output intercomections to c cap In Sensor Ro. EXTERNAL CAPACITOR An external integration capacitor may be used instead of or in addition to the intemallOOpF integration capacitor. Since the transfer function depends upon the characteristics of the 5-12 Swln Ow Com SwCom -:......- - - - - - - - - - - - - - - - - -.... FIGURE 6. Capacitance of Circuit at Input of Integrator. Burr-Brown Ie Data Book Supplement. Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) Therefore. for very low CIN • the Integrate noise will approach 10JiVnns. The total noise when in the Hold mode after proceeding through Reset and Integrate modes is calculated as shown below. Total Noise= J ~ I e nl 2 +e nH 2 + enR 2 If only the Integrate and Reset modes are used. the total noise is the nns sum of the noise of the two modes as shown below. t ChalliS ~''''''''''''''''''''''''-''-'''+ lmV" ..-..---•....-...-.....-... ----\.::~.:~;. ..; DYNAMIC CHARACTERISTICS Fntquency Response o The ACF2101 switched integrator is a sampled controlled by the sampling frequency (fs). which dominated by the integration time. Input signals' Nyquist frequency (fs/2) create errors by the sampled frequency bandwidth. The bandwidth of the switched integrator istic at fs/2.25 and a null at fs and etc. This characteristic is often '. ' interference. II. ~ to the integration capacitor is Therefore. the charge offset error larger integration capacitors. The charge transfer results in a 1mV charge when using the 1000F internal integration offset voltage will change linearly with the capacitance. That is. 50pF will result in a 2mV offset and 200pF in a 0.5mV charge offset. 0 iii" !!. III i J ~ -00 -40 -50 1110T Charge Charge from the logic control inputs to the integration capacitor when the switches change mode. Careful printed circuit must be used to minimize external coupling from digital to analog circuitry and the resulting charge transfer. Charge transfer results in a DC charge offset error voltage. The ACF2IOt switches are compensated to reduce charge transfer errors. Since the ACF2101 switches contribute equal and opposite charge for positive and negative logic input transitions. the total error due to charge transfer is determined by the switching sequence. For each switch. a logic transition Burr-Brown Ie Data Book Supplement, Vol. 33b Droop Droop is the change in the output voltage over time as a result of the bias current of the amplifier. leakage of the integration capacitor and leakage of the Reset and Hold switches. Droop occurs in both the Integrate and Hold modes of operation. Careful printed circuit layout must be used to minimize external leakage currents as discussed previously. The droop is calculated by the equation: Droop=~ C where C is the integration capacitance in farads and the result is in volts per second. For the internal integration capacitance of I OOpF. the droop is calculated as: 200 x 10" IS -12 = 2mV/s or 2nV/Jis 100 x 10 Droop increases by a factor of 2 for each lOoC increase above 25°C. Droop= 5-/3 For Immediate Ass/stance, Contact Your Local Salesperson BURR-BROWN@ CMP100 IE55IE55II HIGH-SPEED WINDOW COMPARATOR ATE PIN RECEIVER FEATURES APPLICATI9NS' • PROPAGATION DELAY: 5ns max, 100mV Overdrive • ATE PIN RECEIVER • WINDOW COMPARATOR • THRESHOLD DETECTOR • COMMON MODE INPUT RANGE:±12V • INPUT IMPEDANCE: 1201<0 112pF • OUTPUTS: latchable, 10k ECl Compatibl~ • COMPLETE: No External Parts Required • TEMPERATURE RANGE: "';'25°C to +85°C • PACKAGES: 16·Pln Plastic DIP, 16-lead Plastic SOIC DESCRIPTION CMPlOO is II high-speed dual comparator designed for receiver. It is also use as an automatic test system useful in a wide variety of analog threshold detector and window comparator applications. Pm CMPlOO. has two reference inputs and one analog input which is common to both comparators. All inputs are attenuated by a voltage divider to provide high common mode voltage operation. The analog input attenuator is R-C tuned' to optimize operation, with high-speed input waveforms. The reference input attenuators are not RcC: tuned, Each attenuator network is followed by a buffer amplifier ahead of the comparator circuits. Complementary ECL output stages are capable of driving 500 terminated transmission lines to a -2V pull-down voltage. In addition,latch-enable inputs are provided for each comparator, alloWing operation as a sampling comparator. . CMPlOO is available as an industrial temperature range de~ic~, ":'25°C to +85°C, and is packaged in a 16-pin plasiiC DIP and.in a 16-lead plastic SOIC. c' international Airport industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. TUcsan Blvd. • Tucson, AZ 85706 Tel: (602)746-1111 • Twx: 91J1.952·1111 • Ceble:BBRCOIIP • Telex:1J66.6491 • FAX: (602) 889-1510 • ImmedIaleProductlnlo:(800)54Ul32 PDS·I075 5·14 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL T. = 25'C and at rated supplies: V+ = +5V, V- = -5.2V unless otherwise noted. CMP100AP, AU PARAMETER MIN TYP MAX UNITS ANALOG INPUlS DiHerentiai Input Voltage Range Common Mode Voltage Range Resistance Reference Inputs: VREF1 • VREF2 45 Analog Input Capacitance, All Inputs """",r= V V 24 ±12 90 60 120 2 75 150 10 20 10 250 ±10 ±10 kll kll pF CH""",,, ~"'" """ ACCURACY Input Offset Voltage, Vos'" Common Mode Error Voltage Offset Drill Power Supply Sensitivity of 100 "".0(: ~ ~:i!~~ RESPONSE TIME Propagation Delay, t,,"'" 100mV Overdrive, latch Disabled 0 0 A. mV .... mVN Ilvrc IlVN IlVN :E U 3.6 5 ns , Range) DIGITAL SIGNALS'" (Over, Inputs (latch Controls) logic Levels: V,H -1.1 -1.5 50 5 V" I," (V, -1.W) I" (V, -1.5V) OU!puts (Balanced) Logic Levels: v"'- (SOn Load to -2V) (SOn Load to -2V) VO" POWER SUPPLY = = -1.5 -1.1 V V iJ.A iJ.A V V fI) Z g ... '" Supply Voltage V+ VSupply Current'" V+ V- +4.75 -5.45 +5 -5.2 VDC VDC +30 +40 mA -40 -50 460 mW -25 +85 'c -65 +150 'C Power Olsslpation(6) 360 TEMPERATURE RANGE Specification Storage +5.25 -4.95 U Z :::) rnA ...- II. :::) NOTES: (1) Defined as half the magnitude between low-to-hlgh and hlgh-to-Iow lransHion input voltages. (2) See section on 'Measuring CMP100 Performance~ (3) See "Discussion of Specifications' for exact conditions. (4) 10k ECL compatible. (5) Maximum supply current is specified at typical supply voltages. (6) Maximum Power Dissipation is calculated with typical supply voltages and maximum currents. Note that dissipation in the oU!pUt transistors from driving son ECL loads will increase the total power dissipation by about SOmW. ' ABSOLUTE MAXIMUM RATINGS V+ to Digital Common and Power Common ...................................... +6V V- to Digital Common and Power Common ....................................... -6V (V+) - (V-) ........................................................................................... 12V Digital Inputs to I;ligital Common Differential .........................................................................................±4V Common Mode ......................................................................... V- to V+ Differential Analog Input Voltage ....................................................... ±25V Package Power Dissipation ........................................................... 7S0mW Storage Temperature .•.••••..••...••.•..•...•...••..••..•.•.•..•••..•••.• -6O'C to + 15O'C Lead Temperature (soldering, 105) •••.•••.••••••••.••••••••••..••••.•••.••••••••• +300'C Stresses exceeding those listed above may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may aflect device reliability. Burr-Brown Ie Data Book Supplement, Vol. 33b PIN DEFINITIONS PIN NAME DESCRIP110N 1,15 2,3 4 5 6,7 8,10 9 11 12 13 14 16 LE2,J:..E2 LATCH or UNLATCH comparator 1 oulputs ECL ou!puts 01 comparator 2 Relum lor comparator cln:ults Return for ECL oUiput uanslstor currents ECL oulputs of comparator 1 LATCH or UNLATCH comparator 2 oU!puts Positive Supply Voltage, +5V Relerence Voltage lor comparator 1 Analog Signal input 02,02 DCOM PWRCOM 01,01 LEI, LEI V+ VREF1 Analog In ACOM VREF2 V- U -a:: "~ U = Return lor Analog In, V... " V.... Relerence voltage lor comparator 2 Negative Supply Voltage: (ECL Supply, -5.2V) 5-15 For Immediate Assistance, Contact Your Local Salesperson MECHANICAL P Package -IS-Pin Plastic DIP I' 'I .{ ::": :JIH A Pin 1 MILUMETERS MIN MAX 18.80 20.32 18.42 19.94 5.85 7.38 5.09 6.36 3.05 5.09 0.38 0.59 0.76 1.78 2.54 BASIC 1.27 0.51 0.20 0.38 I.76J 3.82 7.63 BASIC 0" 15° 0.25 0.76 .64 1.27 NOTE: Leads In IlIIe position within 0.01" (O.25mm) R al MMC at saadng plane. P INCHES MIN MAX .740 .800 .72JJ .785 .230 .290 .200 .250 .120 .200 .015 .023 .030 .070 .100 BASIC 0.20 .050 .008 .015 .070 .ISO .300 BASIC 0° 15° .010 .030 .025 .OSO DIM A At B Bt C D G H J L M N INCHES MIN MAX .400 .416 .3SS .412 .286 .302 .268 .286 .093 .109 .015 .020 .050 BASIC .022 .038 .008 .012 .391 .421 SOlYP .000 .012 MlWMETERS MIN MAX 10.18 10.57 9.86 10.46 72i1 7.67 6.81 7.26 2.36 2.77 0.38 0.51 1.27 BASIC 0.56 0.97 0.20 0.30 9.93 10.69 5°lYP 0.00 0.30 NOTE: Leads In true. position within 0.01". (O.25mm) R at.MMC at seating plane. DIM A At B Bt C D . F G H J K L M N P Package -IS-Pin SOIC II~ ~ .~ ~ :t~ ~ ~ ~II .,.-- Pin I Identifier ~ ~ ~ ~ ~ ~ ~ ~ J" lr J1 1:n~nnnnrl.1 tc G 0-11- LN t I,J f ilj L .1"1 ORDERING INFORMATION MODEL CMP100AP CMP100AU 5-/6 PACKAGE 16-Pin DIP 16-LeadSOlc Burr-Brown ICData Book Supplement, Vol.33b Or, Call Customer Service at 1-800-548-6132 (USA Only) TYPICAL PERFORMANCE CURVES T, =2S'C and at rated supplies: V+ =+5V. V- =-S.2V unless otherwise noted. PROPAGATION DELAY vs OVERDRIVE PROPAGATION DELAY vs AMBIENT TEMPERATURE 21 " .s E .!3 18 _ 15 .s. '" .m o 12 4 3 ,g " '" 2 l5 19 l 1 ov j __ l-1~~~;;v--f--t ( 6 Il. 3 o o VREF1 = VREF2 o 100 200 o -ISOns 1--150ns--l 200mV ... +VOD 300 500 400 o -30 Overdrive (mV) 30 60 CI ov 90 Ambient Temperature ('C) CJ POWER SUPPLY CURRENT vs AMBIENT TEMPERATURE 60 - ~~ I- - I-- I- ........I- :k ~ ~ I- r- I- ........ ........ r- +5V o -30 -10 10 50 30 70 90 AmblenlTemperature ('C) RESPONSE TO"A 3ns ANALOG INPUT PULSE ~ ~ .§ §. ~ 0 I I I I Q => 9=> 0 Q I I I I :"""/ ' I I I I I I I I I I I 400 :> .§. 200 V :; Co .5 0 '" -200 0 Oi <" -400 Analog In,/ V: I G- Il NOTE: Propagation Delay vs Overdrive is shown for two amplitudes of Input pulse: from -200mV ... +Voo (0.2nVlns slew rate) and -tV ... +Vo, (tV/ns slew rate). For an inverse input wavefoon: from +tV ... -Yo, and from +200mV ... -Yo,' propagation delays Identical 10 those above are produced. ~ ~ ........... 2.76ns I I ~ ~ - /' / ~ """ I I j, I I I Time (InsJdiv) Burr-Brown Ie Data Book Supplement, Vol. 33b 5-17 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) T. = 25"<: lind at rated supplies: V+ = +5V. V- =...J5.2V unless otherwise noted. RESPONSE TO A 2ns LATCH ENABLE PULSE ~ I I I ~ E 0 ~ I ~ I I " 0 ~0 I I 400 g D- O i~ -200 f \ /1 \ \ :; .5 \ I I -400 ,r ~ ,..;- ,../ I I ~~LOL 200 Q \V- I 0 :;- I I a \ '-- ~ I I J" , I \ If I I Analog In I I \'I \ LE Tome (5ns/div) SETUP TIME. Is I I I I I I I . I I I I I I I I .1 I '\/ /\. "' a a 400 ! ! ,- r-.... 200 0 / ~ :g -200 < / V \! . /1 ,/ ~ I -400 Analog In ~ ts""-l \.... Tome (2ns/div) ,/ ~ ~ E 0 0 ~ I :- r-3.5ns- I I I I I - I 0 400 :;- g 200 :; ~ ~ :g -200 < 0 -400 ~ I J I I ~ \ /V . ,..v I: \ I'--- LE CAPTURING A NARROW ANALOG PULSE ./'.... I ----- ./: I ~ -: '\1/ a A I I a I I I I I \" \ "J. '\~ Analog In LE Tome (2ns/div) 5-18 Burr-Brown feData Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) DISCUSSION OF SPECIFICATIONS The propagation delay of the CMPIOO is virtually identical for negative going and positive going analog input edges. Differential Propagation Delay (Skew), ANALOG INPUT Offset Voltage, Vos The value of the the comparison threshold for V REF lor V REF 2 = OV. Vos and maximum drift vs temperature of Vos are guaranteed. Propagation Delay Dispersion Propagation Delay Dispersion is the variation in propagation delay versus input overdrive. Note that propagation delay may also be a function of input slew rate and of the previous level. Common Mode Error As V REF varies over its range, there is a small gain error which manifests itself as a change in the comparison level. Common mode error drifts typically -15IlV/"C. The input waveform for the propagation delay specification is illustrated in the first typical performance curve, Propagation Delay vs Overdrive. The Propagation Delay listed in the Electrical Specifications table is specified using an input waveform with lOOmV overdrive, a previous level of -200mV and a slew rate of 200V/!lS. A typical propagation delay curve is also shown for a previous level of -I V. The outputs are not latched for this specification. DYNAMIC PERFORMANCE Figure 1 illustrates the following analog and logic performance definitions. Input to Output High Propagation Delay, tpDH tpOH is the propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of an output (Q output) Low-to-High transition. Output logic is not latched for this definition. Input to Output Low Propagation Delay, tDlFF tDlFF is the difference in propagation delay from one comparator to another. The skew between each half of one CMPIOO is no greater than 200ps. Overdrive Overdrive is the voltage by which the input exceeds VREF ±Vos' Minimum Set·Up Time, tpDL tpOL is the propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of an output (Q output) High-to-Low transition. Output logic is not latched for this definition. ls ts is the minimum time before the positive transition of the Latch Enable (LE) that an analog input signal change must be present in order to be acquired and held at the outputs. LE, LE, 0, Q, V AEF1 Is Analog In OV VREF2 ---\--- O2 LE2 FIGURE I. Analog and Logic Timing Definitions. Burr-Brown Ie Data Book Supplement, Vol. 33b 5·19 .. o o a. Ii u For Immediate Assistance, Contact Your Local Salesperson The ts perfonnance of CMPlOO is illustrated in the Typical Perfonnance Curves. Minimum Hold Time, tH tH is the minimum time after the positive transition of the Latch Enable (LE) thtlt an analog input signal change must remain unchanged in order to be acquired and held at the outputs. tH = 0 for CMPlOO. LOGIC PERFORMANCE DEFINITIONS Latch Enable to Output High Delay, t DLOH t oLoH is the propagation delay of latch logic circuits measured from the 50% point of the Latch Enable signal (LE) High-to-Low transition to the 50% point of an output (Q) Low-to-High transition. Latch Enable to Output Low Delay, t DLoL tOLOL is the propagation delay of latch logic circuits measured from the 50% point of the Latch Enable signal High-toLow transition to the 50% point of an output (Q) High-toLow transition. Minimum latch Enable Pulse Width, tpw tpw is the minimum time that the Latch Enable (LE) must be High in order to acquire and hold an input signal change. The actual timing perfonnance of CMPIOO is illustrated in the Typical Perfonnance Curves. OPERATING CONSIDERATIONS INPUT VOLTAGE THE lATCH FUNCTION The latch function is used for sampling the state of the outputs and holding them until the output can be processed. Figure I shows a timing diagram for differential input latch enable controls, LE and LE. The latches of the CMPIOO are transparent type latches. If LE is Low (LE is High), the Q outputs indicate the sign of the' input difference voltage. When LE goes High (LE Low), the comparator outputs are held at the current state. When the analog input signal passes through the reference level, the comparator output Q changes, after a time of tpoH or tpOL ' However, if the output is to be latched, the input signal must have crossed the threshold for a time ts (set-up time) before the rising edge of LE occurs in order to capture the correct output state. On the other hand, in order to capture a correct output state just before it changes, it is necessary to maintain that output state for tH, (hold time) after the rising edge of LE. tH = 0 for CMPlOO. A minimum latch pulse width of tpw is needed to capture the state of narrow pulses. See the Typical Perfonnance .Curves for an example of sampling a narrow pulse. 10k ECl lOGIC If the latching function is not used, the Latch Enable inputs (LEI and LEz) should be returned to an ECL High voltage (-O.SV) or to Digital Common (OV). LEI and LEz should be returned to an ECL Low level (-I.8V), to an ECL bias voltage (-1.3V) or to the -2V son load pull-down power supply. Connecting an ECL input to -5.2V may create a marginal transistor emitter-base breakdown situation over the ambient temperature range and is not recommended. Input reference voltages V REF I and V REF Z may vary from -12V to +12V. The frequency-compensated analog input network can also swing from -12V to +12V. If a single (non-differential) ECL logic input is used, connect the complementary input to an ECL bias voltage (-I.3V). Care must be taken to be sure that the Maximum Differential Input Voltage is not exceeded. That is, the voltage between Analog In and V REF I or between Analog In and VREF Z must not exceed ±25V. If this voltage is exceeded by I or 2 volts, even momentarily, emitter-base voltage breakdown of the input transistors will occur and cause a pennanent shift of the offset voltage, Vos' to an out-of-spec value. However, the CMPIOO will continue to function and will not be destroyed. 100k ECl lOGIC The negative power supply, V-, of the CMPIOO can be operated at -4.5V. The common mode input range of the analog and reference inputs will be reduced to +12V to -7.5V. Output levels are not affected by changing the Vpower supply voltage to -4.5V. Input voltages to the CMPIOO of uncontrolled magnitude may occur during system power-up. Take care to assure that the Absolute Maximum Differential Input Voltage is not exceeded during power-up. DRIVING SOURCE IMPEDANCE An apparenfslow response of the CMPlOO may be due a combination of high source impedance and stray capacitance to ground at the analog input. An R-C combination of lill source resistance and IOpF to ground results in a IOns'time constant-more than double the typical response time of the CMPlOO. 5-20 TTL INPUTS The operating common mode range of a logic input is -2V to +2V. Thus one can bias the logic inputs to use them with TTL inputs if the High input level is maintained below +2V. In this case, the complementary logic input should be biased at the TTL threshold of +1.4V. LEVEL SHIFTING ECl to TTL The ECL outputs can be translated to TTL using a Motorola MClOl25 Quad ECL-TTL translator. The logic delay tOLDH and tOLDL and the propagation delay \POL and tpOH will be increased by the delay of the translator. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) INSTALLATION solution for preserving dynamic perfonnance and reducing noise coupling into sensitive circuits. TERMINATING ECl OUTPUTS The best perfonnance will be achieved with the use of proper ECL tenninations. Such a configuration is illustrated in Figure 3. The open-emitter outputs of the CMP 100 are designed to be tenninated through son resistors to -2V or any other equivalent termination. If high-speed ECL signals must be routed more than a few centimeters, MicroStrip or StripLine techniques may be required to insure proper transition times and prevent output ringing. When passing power through a connector, use every available spare pin for making power supply return connections, and use some of the pins as a Faraday shield to separate the Analog and Digital Common lines. POWER SUPPLY SELECTION Linear power supplies are preferred. Although switching power supply nns specifications may appear to indicate low noise output, voltage spikes generated by switchers may be hard to filter. Their high-frequency components may be extremely difficult to keep out of the power supply return system. If switchers must be used, their outputs must be carefully filtered and the power supply itself should be shielded and located as far away as possible from precision analog circuits. PRINTED CIRCUIT lAYOUT CONSIDERATIONS Power Supply Wiring Use heavy power supply and power supply common (ground) wiring. A ground plane under the part is usually the best Power Supply Returns (ACOM, DC OM and PWRCOM) For best perfonnance, connect ACOM (pin 13) and DCOM (pin 4) to the ground plane under the comparator. PWRCOM. (pin 5), which is connected to the collectors of the ECL outputs, can be returned by separate printed circuit trace but its inductance should be kept low to avoid ringing. Do not connect ACOM and DCOM together at the end of a long printed circuit trace and then run a single wire to the power supply. To use separate ACOM and DCOM return printed circuit traces, connect a IJlF to 47JlF tantalum capacitor between DCOM and ACOM pins as close to the package as possible. Power Supply Bypassing Every power supply line leading into the comparator must be bypassed to the Common pins. The bypass capacitor should be located as close to the comparator package as possible and tied to a solid return, preferably to the ground plane under the device. If the capacitors are not close enough to the package, DC resistance and inductance may be above acceptable levels. Use tantalum capacitors with values of from IJlF to lO!!F. Parallel them with smaller ceramic ca- o 52 a. :IE u en z 52 t; z Ii! +SV 16.60 16.60 ~ - r-_-+_-,,16V1.6I1o,.-_-+_1.J\,6!1..611v0_~ l- S To 500 Scope tl -u c:J 66.50 .----.---0 9 c 66.50 = -S.2V FIGURE 2. Circuit for Evaluating Analog Propagation Delay, tpDH ' tpDL ' Burr-Brown Ie Data Book Supplement, Vol. 33b 5-21 For Immediate Assistance, Contact Your Local Salesperson pacitors for high frequency filtering if necessary. Electrolytic capacitors are not recommended because their high frequency response is poor. Separate the Analog and Digital Signals Digital signal paths entering or leaving the layout should have minimum length to minimize crosstalk to analog wiring. Stray capacitive feedback from digital outputs to the analog input may cause the outputs to appear fuzzy well after the outputs have changed. Keep analog signals as far away as possible from digital signals. If they must cross, cross them at right angles. CoaXial cable may be necessary for analog inputs in some situations. MEASURING CMP100 PERFORMANCE if overcompensated. If the probe ground lead is too long,the output may appear distorted and oscillatory. Use probes With short (less than one inch) ground straps or use a coaxial cable connection instead of a probe. Do not use Xl or "straight" probes. Their bandwidth is 20MHz or less and capacitive loading is high. The best method is to use 50n matched terminations as shown in Figures 2 and 3. MEASURING PROPAGATION DELAY Figure 2 shows a circuit configuration used for evaluating propagation delay. It uses 50n matched terminations between the instruments and the CMPIOO for best signal integrity. An HP8130A Pulse Generator is used for the analog input and for the latching signals. The oscilloscope is an HP54503A SOOMHz Digitizing Oscilloscope. nlis setup was used to generate the dynamic performance wavefo!11lS in the Typical Performance Curves section. USING AN OSCILLOSCOPE Oscilloscope probes should be matched to the oscilloscope. Use an oscilloscope with at least 400MHz bandwidth. Be sure the probe compensation is adjusted properly. Improper compensatiori will result in apparent overshoot and! or ringing if undercompensated, and an apparent slow edge MEASURING LOGIC TIMING Figure 3 shows the circuit configuration used for evaluating logic propagation delay. The logic input LEI has been added to the circuit of Figure 2. '+sv From SOll Generator + rP Il~F -:- VREF1 It FromSOll Generator ~-:- 16.6ll n 16.6ll 49.90 16.6ll 16.6ll 16.60 16.6ll -:- ~ -:- To SOll ~ Scope 12 16.6ll CMP100 49.9ll To SOll Scope ~ Analog In 16.6ll 16.6ll To SOll Scope VREF2 14 -:- 66.50 66.50 16.6ll ACOM 13 +----f'---o -S.2V FIGURE 3. Circuit for Evaluating Logic Timing. 5-22 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) CMP100 APPLICATIONS ATE PIN RECEIVER A typical ATE pin receiver application using CMP100 is illustrated in Figure 4. The reference inputs. VREF 1 and VREF2 are driven by D/A conveners (Figure 5) while analog input is driven directly from the device under test (DUT). WINDOW COMPARATOR Because of its high speed. the CMPIOO can be used to make timing measurements on modest-speed digital or high-speed analog waveforms. When the outputs of the CMPIOO are combined with a NOR gate. a true window comparator function is iinplemented. Refer to gate G3 of Figure 6. The output pulse width generated by an input signal passing through the reference levels can be measured. This could be for a rise-timelfall-time measurement (setting the reference levels at 10% and 90% of the signal height) of a modest speed digital waveform. or for the width (and hence the value) of aM analog ramp moving between two values from an integrating type signal detector. PULSE RECOVERY The window comparator function can also be used to reconstruct pulses that have been degraded. Positive and/or negative reference levels can be set up to detect both High and Low levels of the pulse. A plot of the response of CMPIOO to a narrow pulse with VREFI OV is shown in the Typical Performance Curves section. = Device Under Test DETECTING TRANSIENTS CMPIOO can be connected to Detect and Hold transient occurrences above and below threshold voltages set by VREF 1 and VREF 2 as illustrated in Figure 6. The outputs of comparator I and comparator 2 are fed back to their LE inputs in order to self-latch their outputs. The Reset control is used to "unlock" the outputs after the transient occurrence has been read. The output NOR gate G3 combines CMP100 outputs into a single-output window comparator function. FIGURE 4. Typical ATE Pin Receiver Application. +10V 1---------1 : INA10S 12 1 1 1 3: 1 1 1 1___ - """''':'-''-0 0 , Eo = E,/E•• ±O.OI% a; o. ~~~-oa; >-t~.;::..:.~ D/A control circuitry omitted for clarity. FIGURE 5. Dual DAC7802 (12-bit pon). DAC7801 (8-bit pon) or DAC7800 (serial pon) D/A Conveners Supply Reference Inputs to the CMPI00. For higher resolution use DAC725. dual 16-bit D/A convener. Burr-Brown Ie Data Book Supplement, Vol.33b 5-23 0 $I a. I! C) For Immediate Ass/stance, Contact Your Local Salesperson WIDE· BAND AMPLIFIERS Note that the transient being detected must remain above VREF 1 (or below VREF 2) longer than the propagation delay of the CMPIOO plus the propagation delay of gates GI and G2. FOR ANALOG INPUT SIGNAL CONDITIONING In a component test application the analog input of the CMPIOO is usually driven directly from the OUT output. Other applications may requm: a high-speed buffer or voltage gain ahead of the CMPIOO. Recommended wide-bandwidth amplifiers are Burr-Brown OPA603 for up to ±IOV signals, or OPA620/0PA621 for very wide-band ±3V signals. A high speed instrumentation amplifier such as the Burr-Brown INA II 0 can be used for common mode rejection. In an application where only one polarity of transient needs to be captured, comparator 2 (not latched) can be used as the source of the Reset control signal to unlock comparator I based on a c\ifferent threshold condition (defined by VREF2) on the analog input signal. This connection will stretch the transient occurrence for the time the VREF 2 condition is present. --~---'VREF' +5V ~---FVREF2 + I..,.. ..,.. 1PF LE, 10 @ Q, 8 Analog In 1Z 7 6 49.9n CMP100 ..,.. 2 VREF2 Co 3 14 15 LE. ACOM -1.2V 13 133n +-+---'249n J -5.2V O.1pF :r O.1pF 1pF ..,.. r All 49.9n "l"a Reset "O"a Ready -2V Reset FIGURE 6. CMPIOO Used to Detect and Hold Transient Occurrences on the Output Pulse of a Device Under Test, or Out-ofLimits Conditions in a Process-Variable Monitoring Application. 5-24 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) BURR-BROWN@ MPY600 IE:lE:lI Wide Bandwidth SIGNAL MULTIPLIER o o = & IE FEATURES APPLICATIONS • WIDE BANDWIDTH: 75MHz - Current Output 30MHz - Voltage Output • MODULATOR/DEMODULATOR • VIDEO SIGNAL PROCESSING • CRT GEOMETRY CORRECTION • LOW NOISE • LOW FEEDTHROUGH: -SOdB (5MHz) • CRT FOCUS CORRECTION • VOLTAGE·CONTROLLED CIRCUITS • GROUND-REFERRED OUTPUT • LOW OFFSET VOLTAGE DESCRIPTION The MPY600 is a wide-bandwidth four-quadrant signal multiplier. Its output voltage is equal to the algebraic product of the X and Y input voltages. For signals up to 30M Hz, the on-board output op amp provides the complete multiplication function with a low-impedance voltage output. Differential current outputs extend multiplier bandwidth to 7SMHz. The MPY600 offers improved performance compared to common semiconductor modulator or multiplier circuits. It can be used for both two-quadrant (voltagecontro\1ed amplifier) and four-quadrant (double-balanced) applications: While previous devices required cumbersome circuitry for trimming, balance and levelshifting, the MPY600 requires no external components. A single external resistor can be used to program the conversion gain for optimum spurious-free dynamic range. When used as a modulator, carrier feedthrough measures -{lOdB at SMHz. X, X2 :l>J Multiplier Core . • ~--------olp X Y, Y2 ~ ~ + /--f-- _ _ _ _ _-OIN - 0 Ry = loon Ry =2oon Ry =Qpen 11111 -10 ForX= -20 1M 10M 100M Frequency (Hz) Burr-Brown Ie Data Book Supplement, Vol. 33b tv I IIII -20 lOOk 'r--" Ry =500n 0 > 10k ~ Ry = 500 ::5 -10 ...... lAy = 18n 20 :E- i"'I 'iii C VOLTAGE OUTPUT FREQUENCY RESPONSE 10k !-OOk 1M 10M 100M Frequency (Hz) 5-27 For Immediate· Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (CONT) T, =+25'C. Vs =±5V unless otherwise noted.. NOISE FIGURE vs Ry RESISTANCE VOLTAGEOUTPUT PHASE SHIFT vs FREQUENCY 35 100 IIII1 30 ~"~500 10 c; e.'" ~ iii 25 l2. / IL '"m .c n. ~ e :> !!2> 20 1.0 z~ 0.1 15 10 0.01 5 lk lOOk 10k 1M VOLTAGE OUTPUT FEEDTHROUGH vs FREQUENCY II II V x= 1V X-Input Nulled Y-Input OdBm r'\. 10 V 1\ > V i: ·iii (!) 5 I~-Input OdBm III r- a 100 lk 10k II III I IIII -100 lQ "" Y-Input Nulled V -80 10k 1M lOOk 10M 100M Frequency (Hz) Rv Resistance (0) o 10000 1000 Y- CHANNEL GAIN ys Fly RESISTANCE 15 ,. 0 100 10 Ry Resistance (Il) I'... > 1 100M Frequency (Hz) 20 [ 10M CURRENT OUTPUT HARMONIC DISTORTION vs FREQUENCY CURRENT OUTPUT FEEDTHROUGH ys FREQUENCY -30 II -40 X= 1V V Y= OdBm V I 2f 3f .; -70 -80 10k lOOk 1M Frequency (Hzj : 5-28 10M 100M 10k lOOk 1M 10M 100M Frequency (Hz) Burr-Brown ICData Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES T" = +25°C. Vs (CO NT) =±SV unless otherwise noted. VOLTAGE OUTPUT HARMONIC DISTORTION ys FREQUENCY CURRENT OUTPUT HARMONIC DISTORTION vs INPUT POWER -30 0 II -40 -20 X= 1V Y= OdBm 0~ -50 ..... ' 0- !II -40 " is -80 ~ g 1: I~ 10MH~ 0 .f! 2 .9 -60 is 21/ 1\ ;/ -70 10k lOOk V -100 1M 10M 100M -80 -50 /'" / 21 ,/ / -80 ~ -80 Y/ V ,/ a.:; V V / -40 Frequency (Hz) -30 -20 V o o -10 0 10 20 Input Power (dBm) = IlL I: VOLTAGE OUTPUT HARMONIC DISTORTION vs INPUT POWER INPUT-REFERRED DYNAMIC RANGE vs INPUT POWER 0 -20 ;[ :g. " 1: -20 1~5MHzl -40 0 ~ -80 -80 -100 -80 ./ ./ ./ -50 -40 ./ -30 -20 7 V / V; ~ -10 ./ V 0- !II :g. "a -40 " -80 tn CI Z a: V .~ o ~Z ~ c 0 10 -80 20 -80 -80 Frequency (Hz) ::I o -20 -40 20 40 S ~ u -a OUTPUT-REFERRED DYNAMIC RANGE vs INPUT POWER INPUT-REFERRED DYNAMIC RANGE vs INPUT POWER .; .. " 40 ldB Compre~n pt ic 20 e- o !II :g. -20 ~ 0 Q. 1=> 0 -40 -80 Gain =30dB / !/ LV' --jRy 0 . / V r 0"#/ // I. "J~ -80 ..........V' -100 -100 ' - _ - ' - _ - ' - _ - - '_ _.J.....<_-'-~-'-...;:..___' -140 -120 -100 -80 -80 -40 -20 o Input Power (dBm) Burr-Brown Ie Data Book Supplement, Vol. 33b -120 -120 / -100 -80 -80 j/ V -40 II. l- Input Power (dBm) 1kHz Noise Floor -20 o 20 Power In (dBm) 5-29 For Immediate Assistance, Contact Your Local Salesperson POWER SUPPLIES The MPY600 may be operated from power supplies from ±4.75V .to ±8V. Operation from ±5V supplies is recommended. Since input and output levels are ±2V. larger supply voltage is not required for full output voltage swing. Furthermore. power dissipation can be minimized by using lower power supply voltage. Power supplies should be bypassed with good high-frequency capacitors such as ceramic or solid tantalum. TYPICAL PERFORMANCE CURVES (CONT) T" = +25°C, Vs = ±5V unless otherwise noted. OUTPUT·REFERRED DYNAMIC RANGE vs INPUT POWER 40 I 20 E Ol :E- -20 ~ -40 ~ -60 0 I Ry = ooJ -60 -100 V I a. 8 ---f IL L 1dB Compresion pI Gain = OdB /"" -120 -100 /"" / r J;fj- r----- /1 oll 92dB / -60 -40 -20 0 20 40 Input Power (dBm) DIVIDER RESPONSE vs FREQUENCY 60 111111111 40 111111111 N V y =0.2VDC ~ 20 i:: 'iii 2V 111111111 111111111 10k lOOk 1M 10M 100M Frequency (Hz) VOLTAGE OUTPUT SQUARER FREQUENCY RESPONSE 5 a iII :E;;; ....... " -5 > § -10 > -15 -20 10k lOOk 1M Frequency (Hz) 5-30 - Y2 ) 1_ -voJ-O Solving for V0 yields the transfer function of the circuit. V y =2VDC' -20 An intuitive understanding of the transfer function can be gained by analogy to an op amp. Assuming that the openloop gain is infinite. any output voltage can be created by an infmitesimally small quantity with the brackets. An applications circuit can be analyzed by assigning circuit voltages to the X. Y and Z inputs and Setting the bracketed quantity equal to zero. [ (XI -X 2)· (Y I , I\. 111111111 (!) (Zt- Z 2)] For example. in the basic multiplier connection (Figure 1). ZI = V0 and ~ = O. Setting this equal to zero: vy =o.02VDC ;:: -Y2) where A = open-loop gain of the output amplifier (typically 7OdB). X. Y. Z are differential input voltages- ±2V max. V I -80 Vo=A[(XI-X2)2~YI ",~1 1kHz Noise Floor TRANSFER FUNCTION The open-loop transfer function of the MPY600 is: 10M 100M The X input is specified for ±1 V full-scale differential input. X inputs up to ±2V provide useful operation with somewhat reduced accuracy and distortion performance. The Y input is rated for ±2V full-scale input. The Y input gain (and therefore its full-scale range) can be varied with an external resistor connected to the Ry terminals-see "Modulator/ Demodulator." Full-scale inputs (X = ±IV. Y = ±2V) produce a ±1 V output. The differential inputs. XI' JS. and YI' Y z• make it easy to trim offset voltage. The trim voltage is applied to the JS or Yz input. which is otherwise grounded (see X z input. Figure 5). Polarity of the input signals can be reversed by interchanging the inputs (reversing the connections XI and JS. for instance). The unused current outputs (pins 15 and 16) must be grounded (or loaded-see discussion on current outputs). The output amplifier is operated in unity gain. The output voltage can be increased (for small input signals) by placing the internal output op amp in higher gain (Figure 2). This reduces bandwidth and increases output offset voltage errors. Burr~Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) Vo= (X, -X.)· (Y, -Y.) +z. 2V Vo:±2V. FS R, Vy:±2V.FS 16 1 Vo 2 Z, 3 Z. 4 Y, 5 Ry (NC) 12 NC 5 Ry (NC) 12 6 Ry (NC) 11 NC 6 Ry (NC) 11 (NC) 14 ":'" Vy:±2V. FS X, 13 Z, 3 Z. 4 Y, (NC) 14 ":'" X, 13 MPY600 MPY600 7 2 o o 7 V. Y. +5V ":'" = +Vs +50V'--_ _ _":'"_-"-I+VS A. I! Vx:±W.FS FIGURE I. Basic Multiplier Connection. FIGURE 2. Adjusting the Scale Factor with Feedback. CURRENT OUTPUT The current output connections of the MPY600 can achieve wider bandwidth multiplier operation (Figure 3). The current output is determined by the X and Y inputs only. so applications which use the Z input to modify the transfer function (e.g., divider and square-root modes) cannot be used. A full-scale input of ±1 V on the X and ±2V on the Y inputs produces a 2mA differential current at the current outputs. This consists of approximately 2.SmA quiescent current ±lmA signal current on each output. The current outputs may be used to drive any load impedance which maintains the voltage on the current outputs within their compliance range. This compliance limit is approximately 2.SV from the power supply voltages. The current outputs and voltage output may be used simultaneously, if desired. Output capacitance and stray capacitance at the current output terminals will limit the multiplier bandwidth. This makes large output resistors (greater than approximately IkO) impractical. The current outputs can be used to drive 500 or 750 loads directly. The circuit shown in Figure 4 uses the current outputs to drive an external OPA621 op amp configured as a currentdifference amplifier. It operates in a noise gain of 3.5. The OPA621 is stable in a noise gain of two or greater and has a SOOMHz gain-bandwidth product. It achieves the full bandwidth performance of the MPY600. R J determines the transfer function gain. R, provides a proper load to optimize high-frequency effects. R. is made equal to the parallel combination of R J and R3• Burr-Brown Ie Data Book Supplement, Vol.33b •52z Ip IN ~VO -::p ~:~: 7\.j" -w - ---- 1.5mA ---- -- Vo I Vy:±2V.FS Vo Ip 2 Z, IN . (NC) l- U Z ::» II. 3 Z. 4 V, 5 Ry (NC) 12 6 Ry (NC) 11 X, ":'" 14 13 MPY600 7 V. +5V ":'" 8 v. U C5 ~ X. 10 -Vs 9 Z C ":'" --5V V :±W. FS Ip-IN = (X, -::» II! I- -x" )(v, -Y.) mA FIGURE 3. Current Output Connection. 5-31 For Immediate Assistance, Contact Your Local Salesperson +5V r-~~----+-----~ 1 Vo Ip 16 2 Z, IN 1 5 -{x, -x. 4 3 Z. Vy:±2V, FS 4 (NC) X, V, 13 MPV600 5 Vo = 14 Ry (NC) 12 6 Ry (NC) 11 R3 2000 0.1~ R~') 1430 ..JSV NOTE: (1) R. = 7 -:- +5V O.I~F V. 8 +VS :c X. )(V, -Yo) 2V. (500/R,) R, !lAo 10 -Vs 1--"--_>------o..JSV 9 -:- FIGURE 4. 75MHz DC-Coupled Multiplier. MODULATOR/DEMODULATOR The balanced modulator or demodulator shown in Figure 5 uses the basic multiplier configuration. It shows the offset of the X input trimmed to null carrier feedthrough. It also illustrates the use of Ry to change the gain of the Y input. This can be used to optimize the spurious-free dynamic range for a given input level. The Y input is optimized for ±2V inputs. For lower input signals, the Y input can be programmed for higher gain by connecting an external resistor to the Ry terminals. The conceptual diagram in Figure 6 reveals why varying the Y-channel gain can yield improved dynamic range. The Ry selection curve in Figure 5 shows the optimum value of Ry for a given Y-input signal level. DIVIDER OPERATION The MPY600 can be configured as a divider as shown in Figure 7. Numerator voltage is applied to the Z inputs; denominator voltage is applied to the X inputs. Since the feedback connection is made to a mUltiplying input, the 5-32 effective gain of the output amplifier varies as a function of the denomimitor input. This causes the bandwidth to vary with denominator (see Typical Performance Curves for divider bandwidth performance). Accuracy in divider operation is approximately 3% for a 10:1 denominator range. Errors grow large and will eventually saturate the output as the denominator voltage approaches OV. SQUARE-ROOT CIRCUIT The circuit in Figure 8 provides an output voltage proportional to the square-root of the input (for positive input voltages). Diode D. prevents latch-up if the input should go negative. The circuit can be configured for negative input and positive output by reversing the polarity of both the X and Y differential inputs. The output polarity can be inverted by reversing the X input polarity and the diode. Accuracy can be improved by trimming the offset at the Z input. Burr-BrownIe Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) Vo= ±1/2E,. Ec Sin (col) Modulation Input±EM 1 Vo Ip 2 Z, IN 3 Z. 4 V, (NC) X, -:- 14 13 MPY600 RTERM 500 5 Ry (NC) 12 6 Ry (NC) 11 7 V2 Ry -:- R, X2 10 -:8 +Vs -Vs o 100 -:R2 lkO 9 +5V o = -5V -5V Carrier Input Ec Sip",t II. +5V :Ii Carrier Null DOWN-CONVERTER TWO-TONE RESPONSE RTERM 500 -5 VALUE OF Rv FOR MAXIMUM DYNAMIC RANGE r---,---,--r--,--..--;.-,.--,--,--, -15 vs INPUT lEVEL -:-'Ok_~~ RL -5dBm Marker A 100kHz -74.46dB -25 -35 -+---1l--I---!l--+-+--t--I _ -G ~l-+-+--t-~--1~-#-+--+-+---I E !£-55f--+-+---+--ti--,I--It-i--+-+-i -65 -75 ,""'-_'----'_--'-_....1-_-'-_-'----' -45 -40 -3S -30 -25 -20 -15 -'0 Input Power leval (dBm) 1-+-1-+-1+-+-1+-+-+--+-1 I-+-I-+-ft-\-+---Jl++-+--+-I -65~~~~~~~~~ ~ -95 ~~ L-~ __ L-~ __ L-~ __L-~__L-~~ lMHz 2-Tone. -5dBm. 10MHz Input down converted to lMHz V = -5dBm at 10.05MHz + -5dBm at 9.95MHz X = 15dBm at 9MHz FIGURE 5_ Balanced Modulator_ Vz Vo=-2V; ~~ Ip 16 G= 1 _ Vz:±2V.FS 2 Z, 3 Z. V y ~'- -,"Co", + _G ±2V. FS 1) Constant Noise Level 2) Constant Clipping Level Vy :Ot02V.FS 4 V, 5 Ry (NC) 12 6 Ry (NC) 11 7 V. (NC) X, 13 RX V-Channel Gain Varies Inversely with Ry -:- FIGURE 6. Variable Y-Channel Gain-Conceptual ModeL X. 10 -:- 8 +Vs Vx:±1V. FS -Vs -5V +5V Bandwidth varies with denominator voltage. See Typical Perfonnance Curves. FIGURE 7. Divider Circuit_ Burr-Brown Ie Data Book Supplement. Vol.33b l- S i- ! 14 MPY600 Denominator ±2V: Rv = 00 ±100V: R, = 0 !iII. "9 IN Numerator 0-=:0Ulput 52 t; u X-Channel has Constant Gain Vx ±1V. FS I 5-33 For Immediate Assistance, Contact Your Local Salesperson D, RL 10kO (required) lN914 t-4IIIf--'-l1 Vo I. 16 2 Z, Y,N: 0 10 2V 0----+-I--"-l3 IN 1 z. (NC) 14 X, 4 Y, ~ Vo I. 16 ~ Z, IN 15 ~ Z. V,N :±W. FS 13 4 MPY600 Y, X, MPV600 ":'" NC5 Ry (NC) 12 NC 6 Ry (NC) 11 L -_ _7,Y2 Vx :±W. FS (NC) X2 10 -Vs 9 +5V ~ NC2 Ry (NC) ~ NC...2. Ry (NC) r!.!- ~ Y2 X2 10 -= -~+Vs -5V ~ -Vs -'= 9 -5V +5V VINMIN BW "'2V' 25MHz FIGURE 8. Square-Root Circuit. Vo = A, A2 cos (8) R, lkn 1 V, =A,Sln(rol) Vo = (1 ±112Em) E\: Sin (0)1) 4 I. 16 Vo 1 Vo I. 16 2 Z, IN 15 3 Z. 4 Y, I~ 1 2 Z, 3 FIGURE 9. Squaring Circuit. Z. (NC) 4 Y, X, Modulation Inpul ±Em 14 5 Ry 6 Ry (NC). 7 Y2 12 11 X, 13 5 Ry (NC) 12 6 Ry (NC) 11 7 Y. X. 10 X2 10 +5V ":'" -Vs +5V 14 MPY600 13 MPY600 (NC) (NC) Car~er -5V E\: Input Sin (rol) V,=A,Sln(rol+lI) FIGURE 10. Phase Detector. 5-34 FIGURE 11. Linear AM Modulator. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) +5V Vo Carrier C Inpul O.D1~F o:::::-----j I Modulation lson Vo Ip 16 ..l. Z, IN 15 ,.!. ~f- A, C 0.01~F 3 Z. 4 Y, ..!. Ay (NC) ell- ..!. Ay (NC) r-!1 7 Y. 0:- (NC) A 1 Vo Ip 2 Z, IN l~n 16 X, r1i 13 A lkn MPY600 Z. 3 Vy 4 (NC) 14 A lkn Y, X, 13 s= 10V MPV600 NC 5 Ay (NC) 12 NC 6 Ay (NC) 11 7 Y. X. 10 B +Vs -Vs 9 X. 10 8 +Vs -Vs o o = A lkn D. :IE 9 R, 0:- +5V loon Ro loon -Lc. TO.l~F ..L -5V Maximum peak-to·peak signal ampliWde = V. - 5V for both Inputs and the oulput. 0:- FIGURE 12. 25MHz Multiplier with Improved Load Driving Capability. FIGURE 13. Single-Supply Balanced Modulator. X Vo=II2(X +Y ) Y 0---1. Vo Ip f1!L- ~ Vo Ip --.-£ z, INr1i- ~ z, INJL ,---2 Z. r1i 3 Z. 4 Y, t1L- r- 4 Y, (NC) X, MPY600 r Ay (NC) pg ~ Ay (NC) rll 2- Y~ X. B +Vs -Vs L----l +5V X, MPY600 11- r1L 9 (NC) -5V +5V ..li...- r.1! .E- ~ -2. Ay (NC) .ll -i Ay (NC) r-!1 ~ Y. X. V. -V. 8 ~ r-1L 9 -5V FIGURE 14. CRT Focus Correction. Burr-Brown Ie Data Book Supplement, Vol. 33b 5-35 · For Immediate Assistance, Contact Your Local Salesperson Vo = XI2 (X'12 + Y'I2) (X"2 + Y '12) Vo Ip~ r1 Vo Ip~ ~ Z, 1Nc1L .......g z, 1Nr!L- o-l .-2 x z, (NC) 4 Y, X, r1i ~ Z, 13 4 Y, MPV600 2 13 (NC) ~ 2- Ay (NC) ~ I~ Ry INC) ~ ..§. Ry (NC) rllr!!!- r--?- x, r!!!- Y, Io:!!: +Vs -Vs ~ Vo Ip ~ INc1L Z, ~ z, (NC) v 4 x, Y, ~ r!!- r!-i ~ Ry ...§. Ry ~ V. crft. Vs x. 7 Y, f nr 9 +5~ Vs 1 Vo Ipr!L- z, 1Nr!L- ~ J -Vs ~ Z, 4 13 (NC) x, V, MPY600 -:- rli MPY600 +5V ~ x, Ry 12- r- (NC) ~V Vo = YI2(X'I2+Y '12) rli 13 MPY600 r1! ...§ Ry (NC) ~ r!1- ...2 Ry (NC) ~ x. r!!!- >----,-Z Y. (NC) (NC) -VS +5V r2-o -5V _~ +VS +5V x. t-!!!---Vs 9 .= ~. FIGURE 15. CRT Geometry Correction. 5-36 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) REF102 BURR-BROWN@) 11E5I1E5I1 Precision VOLTAGE REFERENCE s... L FEATURES APPLICATIONS • +10V ± O.0025V OUTPUT • VERY LOW DRIFT: 2.5ppm/oC max • PRECISION-CALIBRATED VOLTAGE STANDARD • EXCELLENT STABILITY: 5ppm/1 OOOhr typ • D/A AND AID CONVERTER REFERENCE • EXCELLENT LINE REGULATION: 1ppmIV max • ACCURATE COMPARATOR THRESHOLD REFERENCE • EXCELLENT LOAD REGULATION: 10ppm/mA max • DIGITAL VOLTMETERS III II: • PRECISION CURRENT REFERENCE • TEST EQUIPMENT • PC-BASED INSTRUMENTATION • LOW NOISE: 5!1Vp-p typ, O.1Hz to 10Hz • WIDE SUPPLY RANGE: 11.4VDC to 36VDC • LOW QUIESCENT CURRENT: 1.4mA max • PACKAGE OPTIONS: HERMETIC TO-99, PLASTIC DIP, SOIC, DIE DESCRIPTION Trim 5 v+ 2 The REFI02 is a precision IOV voltage reference. The drift is laser-trimmed to 2.SppmfC max (CM grade) over the industrial temperature range and SppmfC max (SM grade) over the military temperature range. The REFlO2 achieves its precision without a heater. This results in low-power, fast warm-up, excellent stability, and low noise. The output voltage is extremely insensitive to both line and load variations and can be externally adjusted with minimal effect on drift and stability. Single supply operation from ll.4V to 36V and excellent overall specifications make the REFl02 an ideal chl'Jice for demanding instrumentation and system reference applications. The REFl02 is also available in die form. 4 Noise Common Reduction InlernaUonal Airport Industrial Park • Mailing Address: PO Box 11400 • TUcson. AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (602) 746·1111 • Twx: 910-952·1111 • Cable: BBRCORP • Telex: 066·6491 • FAX: (602) 889-1510 • Immediate Product Info: (800) 548-6132 PDS·900B Burr-Brown Ie Data Book Supplement, Vol.33b 5-37 For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL AIT, = +25'C and V. = +15V power supply unless otherwise noted. REF102AIR PARAMETER OUTPUT VOLTAGE InRlai CONDITIONS MIN T,=25'C 9.99 TYP vs Temperature (1) REF102CM REF102BIS MAX MIN 10.01 10 9.995 TYP MAX MIN 10.0OS 5 9.9975 TYP MAX UNITS 10.0025 2.5 V ppmI"C vs Supply (Une Regulation) V.= 11.4Vto 36V 2 1 1 ppmN I, = OmAto+l0rnA I, = OmA to -limA T,= 25' 20 40 10 20 10 20 ppmlmA ppm/rnA vs Output Current (Load Regulation) vs Time M Package p. U Packages.' 5 20 Trim Range {31 · · · ±3 NOISE (0.1 Hz to 10Hz) 5 OUTPUT CURRENT +10. -li INPUT VOLTAGE RANGE +11.4 QUIESCENT CURRENT WARM-UP TIME ,. +36 +1.4 (lOUT = 0) (To 0.1%) 15 TEMPERATURE RANGE Specification REF102A. B. C REF102R.S -25 -li5 · . · ·· +85 +125 · · · · · ·· · ppml1000hr ppml1000hr % ILVP-P rnA ·· · V mA ILS 'C 'C 'Specificatlons same as REF102AIR. NOTES: (1) The "box" method is used to specify output voRage drift vs temperature. See the Discussion of Performance section. (2) Typically 5ppmIl000hrs alter 168hr powered stabilization. (3) Trimming the offset voltage affects drift slightly. See Installation and Operating Instructions for details. (4) With noise reduction pin floating. See Typical Performance Curves for details. ORDERING INFORMATION MODEL'" PACKAGE TEMP RANGE MAX INITIAL ERROR(mV) MAX DRIFT (ppmI"C) REF102AU REF102AP REF102BP REF102AM REF102BM REF102CM REF102RM REF102SM SOIC Plastic DIP Plastic DIP Metal TO·99 Metal T0-99 Metal T0-99 Metal T0-99 MetalT0-99 -25 to +85'C -25 to +85"C -25 to+85'C -25to+85'C -25 to +85"C -25 to+85'C -li5 to +125'C -Q5 to + 125'C ±10 ±10 ±10 ±10 PIN CONFIGURATIONS ±5 ±5 ±10 ±10 ±5 ±5 ±2.5 ±10 ±2.5 ±10 ±5 ±5 ABSOLUTE MAXIMUM RATINGS Top View P,U Package NC 0 8 Noise Reduction V+ 2 7 NC 3 6 VOIIT NC Com 4 5 Trim Input Voltage ...................................................................................... +4OV Operating Temperature P.U ..................................................................................-25"C to +85"C M ...................................................................................-55"C to + 125'C Storage Temperature Range P.U ..................................................................................-40·C to +85'C M ...................................................................................-65"C to +150'C Lead Temperature (soldering. lOS) ................................................ +300"C (SOIC 3s) ......................................................... +2SO"C Short-Clrcuft Protection to Common or V+ ............................... Corftlnuous MPllckage Noise Reduction Common 5-38 Burr-BrownIe Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) MECHANICAL M Package - Metal TQ-99 -A- DIM A B C D E F G H J K L M N INCHES MIN MAX .335 .370 .335 .305 .165 .185 .016 .021 .010 .040 .010 .040 .200 BASIC .028 .034 .029 .045 .500 .110 .160 45" BASIC .095 .105 - MILUMETERS MIN MAX 8.51 9.40 7.75 8.51 4.70 4.19 0.41 0.53 1.02 0.25 0.25 1.02 5.08 BASIC 0.71 0.86 1.14 0.74 12.7 4.06 2.79 45" BASIC 2.67 2.41 NOTE: Leads in true position within 0.01" (0.25mm) R at MMC at seating plane. Pin numbers shown for reference only. Numbers may not be marked on package. - II . Seating Plane C'I o,... --0 II. IU a: P Package - S-Pln Plastic OIP DIM A AI B B, C OIl' E EI el eA L INCHES MIN MAX .155 .200 .020 .050 .014 .020 .045 .065 .008 .012 .370 .400 .325 .300 .240 .260 .100 BASIC .300 BASIC .125 .150 MILUMETERS MIN MAX 3.94 5.08 1.27 0.51 0.36 0.51 1.14 1.65 0.20 0.30 9.40 10.16 7.62 8.26 6.10 6.60 2.54 BASIC 7.62 BASIC 3.18 3.81 DIM 1.201 a P 01 Sill INCHES MIN MAX .030 0 O· 15· .015 .050 .040 .075 .015 .050 MILUMETERS MIN MAX 0.76 0.00 15· O· 0.38 1.270 1.02 1.91 0.38 1.27 (I) Nol JEDEC Std• (2) el and eA applies in zone L, when unn installed• NOTE: Leads in true poSition within 0.01" (0.25mm) Rat MMC at seating plane. U Package - S-Pln sOle ~:I~ II J1 Pin 1 Identifier tt~nlU JL H m~ LTl j !! G O..J C tJA )(\,J DIM A AI B BI C D G H J L M N INCHES MAX MIN .185 .201 .201 .178 .146 .162 .130 .149 .054 .145 .015 .019 .050 BASIC .018 .026 .008 .012 .220 .252 O· 10· .000 .012 MILUMETERS MIN MAX 4.70 5.11 5.11 4.52 3.71 4.11 3.30 3.78 1.37 3.69 0.48 0.38 1.27 BASIC 0.46 0.66 0.20 0.30 6.40 5.59 O· 10· 0.00 0.30 NOTE: Leads in true posilion within 0.01" (0.25mm) R at MMC al seating plane . ~L-L---I' Burr-Brown Ie Data Book Supplement, Vol. 33b 5-39 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES TA = +25°C. V5 = +15V unless otherwise noted. L TIme (10ms/dlv) TIme (5jlS/div) Power Tum-On Power Turn·Qn POWER SUPPLY REJECTION vs FREQUENCY LOAD REGULATION 130 +1.5 120 iii :5!. ;;;- " ~ ·ar ". i' g> 100 a: z. 0. .<: 0 ......... ~ f !L 70 <5 ........... :> U) S B- 0 r....... +0.5 60 -0.5 -1_0 -1.5 100 1k a -5 10k Frequency (Hz) QUIESCENT CURRENT vs TEMPERATURE RESPONSE TO THERMAL SHOCK 1_6 300 a ~ 00 ' - T, a I'--- = +~5.C 1.4 " ~ 0 1.2 15 30 --r-- I-- r--..... " I" 0 II Time(s) 5-40 <" .§. ____ REF102CM Immersed in +85·C Fluorinert Bath 00 +10 Output Current (mA) +600 - ----- - ~ a " 80 90 0. +1.0 .§. 110 45 1.0 ---I--I-- ~ 0_8 60 -75 -50 -25 0 +25 +50 +75 +100 +125 Temperature ("C) Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) TYPICAL PERFORMANCE CURVES (CONT) TA = +2S QC. Ys = +15V unless otherwise noted. TYPICAL REF102 REFERENCE NOISE 2kll 20n o 4 ~ 2 " ~ g " -2 z -4 .~ w Noise Test Circuit. o .... ... Low Frequency Noise (Is Idiv) (See Noise Test Circuit) III THEORY OF OPERATION Refer to the diagram on the first page of this data sheet. The lOY output is derived from a compensated buried zener diode DZ,• op amp AI' and resistor network RI-R•. Approximately S.2V is applied to the non-inverting input of Al by DZ I. R I• R2 , and R, are laser-trimmed to produce an exact lOY output. The zener bias current is established from the regulated output voltage through R•. Rs allows usertrimming of the output voltage by providing for small external adjustment of the amplifier gain. Because the TCR of Rs closely matches the TCR of R I, R, and R3 ' the voltage trim has minimal effect on the reference drift. The output voltage noise of the REFI02 is dominated by the noise of the zener diode. A capacitor can be connected between the Noise Reduction pin and ground to form a low-pass filter with R6 and roll off the high-frequency noise of the zener. DISCUSSION OF PERFORMANCE The REFI02 is designed for applications requiring a precision voltage reference where both the initial value at room temperature and the drift over temperature are of importance .to the user. Two basic methods of specifying voltage reference drift versus temperature are in common usage in the industry-the "butterfly method" and the "box method." The REFI02 is specified with the more commonly used "box method." The ··box" is formed by the high and low specification temperatures and a diagonal. the slope of which is equal to the maximum specified drift. Since the shape of the actual drift curve is not known, the vertical position of the box is not exactly known either. It is, however, bounded by VUPPER BOUND and VLOWER BOUND (see Figure I). Figure I uses the REFlO2CM as an example. It has a drift specification of 2.5ppm/"C maximum and a specification temperature range of -25°C to +S5°C. The "box" height, VI to V2, is 2.75mV. Burt-Brown Ie Data Book Supplement, Vol. 33b +10.00275 ~ l!l. ~ > 8~ - REF102BM VUPPER BOUND - - - - - - - - - II: - - VI ~----------------~ VNOMINAL +10.0000 V2 ~ ________________- - J +9.99725 -y L -25 REF102BM VLOWER BOUND I I I 0 . +25 +50 +85 Temperature (OC) FIGURE 1. REFI02CM Output Voltage Drift. INSTALLATION AND OPERATING INSTRUCTIONS BASIC CIRCUIT CONNECTION Figure 2 shows the proper connection of the REFI02. To achieve the specified performance, pay careful attention to layout. A low resistance star configuration will reduce voltage errors, noise pickup, and noise coupled from the powersupply. Commons should be connected as indicated being sure to minimize interconnection resistances. OPTIONAL OUTPUT VOLTAGE ADJUSTMENT Optional output voltage adjustment circuits are shown in Figures 3 and 4. Trimming the output voltage will change the voltage drift by approximately O.OOSppm/"C per mV of trimmed voltage. In the circuit in Figure 3, any mismatch in TCR between the two sections of the potentiometer will also affect drift, but the effect of the d TCR is reduced by a factor of five by the internal resistor divider. A high quality potentiometer, with good mechanical stability, such as a cermet, should De used. The circuit in Figure 3 has a minimum trim range of ±300mV. The circuit in Figure 4 has less range but provides higher resolution. The mismatch in TCR between 5-41 For Immediate Assistance, Contact Your Local Salesperson (2) to the figure on the first page of the data sheet) and attenuates the high-frequency noise generated by the zener. Figure 5 shows the effect of a IIJ.F noise reduction capacitor on the high frequency noise of the REF102. R6 is typically 7kQ so the filter has a -3dB frequency of about 22Hz. The result is a reduction in noise from about 8001lVp-P to under 200ll Vp-p. If further noise reduction is required, use the circuit in Figure 14. (2) NOTES: (I) Lead resistances here of up to a few ohms have negligible effect on performance. (2) A resistance of 0.1 n in series with these leads will cause a I mV error when the load current Is at its maximum of lOrnA. This results in a 0.010/. error of 10V. NO CN FIGURE 2. REFI02 Installation. }'V+ ...h IpF .I. Tantalum 12 Vour 6 REF102 .f' -::- VlRlM 5 20kn Output Voltage Adjust +10V FIGURE 5. Effect of IIJ.F Noise Reduction Capacitor on Broadband Noise «(3dB = IMHz). APPLICATIONS INFORMATION Minimum range (±300mV) and mlmimal degradation of drift. FIGURE 3. REF102 Optional Output Voltage Adjust. High accuracy, extremely low drift, outstanding stability, and low cost make the REFI02 an ideal choice for all instrumentation and system reference applications. Figures 6 through 14 show a variety of useful application circuits. iV+ V+ (1.4V 10 26V) 2 d!lpF .I. Tantalum 12 Vour 6 REF102 VlRlM 5 REF102 As ',Mn 6 +10V .~ 20kn Output 1.4mA < ~ -I L ) < S.4mA Adjust +-4'-----------<>_10VOut R. ~Voltage l Ii. ..- -15V V+ (1.4VI026V) a) Resister Biased -10V Reference ...----,,2,,--.., Higher resolution. reduced range (typically ±25mV). FIGURE 4. REFI02 Optional Output Voltage Fine Adjust. Rs and the internal resistors can introduce some slight drift. This effect is minimized if Rs is kept significantly larger than the 50k!} internal resistor. A TCR of lOOppmf'C is normally sufficient. A, REF102 2kn _ _.flflf\-_ _6:..j 10V C, 1000pF 4 :>-......- - " - - - - 0 -IOV Out OPTIONAL NOISE REDUCTION The high-frequency noise of the REF102 is dominated by the zener diode noise. This noise can be greatly reduced by connecting a capacitor between the Noise Reduction pin and ground. The capacitor forms a low pass filter with R6 (refer 5-42 Il) Precision -IOV Aeference. . See AB·004 for more detail FIGURE 6. -IOV Reference Using a) Resistor or b) OPA27. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) V+ V+ 220n >-'+--0 +10V IL 2N2905 - 2 4 RI ... Vee - 10V IL tTYPi 6 REF102 1-'6'--_ _1---0 +10V 4 +10V REF102 IL IL - 4 al -20mA < IL < +20mA (OPA27 also Improves transient Immunity) b) -SmA < IL < +100mA ..t c) I 'I""" IL(MINI a I L,TVP, +10mA -SmA =IL(TYp) "o...... FIGURE 7. +IOV Reference With Output Current Boosted to: a) ±20mA. b) +\QOmA. and c) IL (1Yp) +lOmA. -SA. +15V III IE: 2 ---, 350n Strain Gauge !lrldge REF102 4 >--0.Vovr 100 6 357n 112W -15V FIGURE 8. Strain Gauge Conditioner for 3S0n Bridge. V+ 2 V+ 2 1-"-<,..-------------<> +10V REF102 1"6'--_ _ _ _ _--, L~JJ~:;::=~M_==lJ4-o -10V Out R Out LOAD Can be connected to ground or -vs. lour = 10V • R" lkll R See AB·005 for more details. FIGURE 9. ±IOV Reference. Burr-Brown Ie Data Book Supplement. Vol.33b See AS·002 for more details and I Sink Circuit FIGURE 10. Positive Precision Current Source. 5-43 For Immediate Assistance, Contact Your Local Salesperson V+ ,:1.4V to 56V 2 ~6::...., REF102 REF102 4 IHA10S 4 2 REF102 _ _ _ _ _ _ _ _ _ _--o+10V +30v 6 >r+_-o+5V 3 +20V 6 1 1 _____ J1 1 4 12 REF102 FIGURE 13. +5V and + lOY Reference. +10V 6 V+ 2 1. 6 NOTES: (1) REF102scan be stacked to obtain voltages in multiples 01 1OV. (2) The supply voltage should be between 10n + 1.4 and 10n + 26 where n is the number 01 REF102s. (3) Output current 01 each REF102 must not exceed its rated oulput current 01 +10. -SmA. This includes the current delivered to the lower REF102. FIGURE II. Stacked References. REF102 (1) 2kll Vour , flo 2kn 4 -=V+ 2 V+ 2 REF102 (2) 6 REF102 2 4 , -=- 1 ,,'5 ,,'6 ,, - - - ___ 1 3 +10V Out --------, tHA10S VOlIr2 +5V 4 -SV Out V+ 2 6 REF102 (H) 4 VourH 2kll VRE.F = (vo, + VOl ..•.vOJr N) N eN = 511Vp-p (1= 0.1 Hz 10 1Mhz) .IN See AB-003 lor more details. -=FIGURE 12. ±5V Reference. 5-44 FIGURE 14. Precision Voltage Reference with Extremely Low Noise. Burr-Brown Ie Data Book Supplement. Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) BURR-BROWN® UAF42 IEaEaI ADVANCE INFORMATION SUBJECT TO CHANGE UNIVERSAL FEATURES • VERSATILE FUNCTION LOW·PASS, HIGH·PASS BAND·PASS, BAND·REJECT • SIMPLE DESIGN PROCEduRE· • ACCURATE FREQUE ·······NP Q INCLUDES ON-CHIP? CAPACITORS to the other three) can be used rm. ,add.itiolnal stages, or for special filter types such figured for a band-pass filters. log architecture tegrators. The inte'graltors pacitors trimmed difficult problems tight tolerance, and elliptic. classical topology of the UAF42 forms a continuous filter, free from the anomalies and switching noise associated with switched-capacitor filter types. The UAF42 is available in a 14-pin plastic DIP and sidebrazed ceramic packages, specified for the -25°C to +85°C temperature range. Band·Pass Out Gnd Low·Pass Out v+ v- International Airport Industrial Park • Mailing Address: PO Box 11400 Tucson, A1. 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, A1. 85T06 Tel: (602) 746-1111 • Twx: 910.952·1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (602) 889·1510 • Immedlale Product Info: (800) 548-6132 PDS·J070 Burr-Brown Ie Data Book Supplement, Vol. 33b 5-45 For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS T. = +25'C. V. = ±15V unless otherwise noted. PARAMETER FILTER PERFORMANCE Frequency Range Frequency Accuracy vs Temperature Maximum 0 Maximum (0 • Frequency) Product o vs Temperature o Repeatability UNITS CONDmON kHz % %/C o to 100 0.01 500 500 0.01 0.025 10 (f,· 0) < 10' (f,· 0) < 10' (f,· 0) < 10' Offset Voltage. Low-Pass Output Resistor kHz o/oI'C ±5 OFFSET VOLTAGE'" Inpul Offset Voltage vs Temperature %!'C % mV % mV fl.VI'C dB vs Power INPUT BIAS CURRENT'" Input Bias Current Input Offset Current pA pA NOISE'" Input Voltage NOise NOise Density: f = 10Hz f = 10kHz Voltage Noise: BW = 0.1 to 10Hz Input Bias Current Noise Noise Density: f = 10kHz nVNHZ nVl,HZ fl.Vp-p fANHz V dB 10"112 10" 116 90 ±11 120 dB 10 VI(J.S ·4 0.0004 MHz % ±11.5 ±25 mA V ±15 ±6 -25 -55 -40 -{;O Thermal Resistance. 8,.• 100 V V ±18 ±7 mA +85 +125 'C 'C +125 +150 'C 'C 'CJW NOTES: (I) Specifications apply to uncommitted op amp. A4. The three op amps Iorrning the filter are identical to A4 and are tested as a complete HRer. 5-46 Burr-Brown Ie Data Book Supplement, Vol. 33b DIGITAL-TO-ANALOG CONVERTERS Burr-Brown offers a broad variety of Digital-to-Analog (D/A) converter products engineered to meet the most critical requirements for stability and reliability. General purpose instrumentation D/As range in resolution from 12 to 18 bits. These models include industry standard products-many originated by Burr-Brown-as weIl as more complete, higher accuracy solutions. BurrBrown's products are carefuIly designed and manufactured to minimize product variations, making them ideal for test equipment, process control, and other industrial and analytical applications. 6 PCM D/A converters are designed and tested to deliver excellent dynamic performance. The resolutions of these products are 16 and 18 bits. Typical applications are compact disc players, digital frequency synthesis, and telecommunications systems. High-speed D/A converters offer very fast settling current output. Models are available with TTL or ECL logic inputs. These products are ideal for very high frequency synthesis and control systems. Burr-Brown Ie Data Book Supplement. Vol. 33b 6-1 For Immediate Assistance, Contact Your Local Salesperson DIGITAL·TO·ANALOG CONVERTERS SELECTION GUIDES The Selection Guides show parameters for the high grade; Refer to the Product Data Sheet for a fuII selection of grades. Models shown in boldface are new products introduced since publication of the previous Burr-Brown IC Data Book. Boldface = NEW INSTRUMENTATION DIGITAL-TO-ANALOG CONVERTERS Description Settling Time Resolution Linearity Model (Bits) Error (%FSR) (Jls) Output Range Temp Range(t) Pkg(2) Q,BI(3) Screen Page No. Com DDIP BI 6.1-S0 DDIP DDIP DDIP DDIP, SO a,BI a,BI a,BI a,BI 6.1-43 6.1-43 6.1-43 6.1-43 Very High Resolution DAC729 lS ±0.00075 5 ±lmA,-2mA; +5V,+10V,±5V,±10V General Purpose DAC700 DAC701 DAC702 DAC703 16 16 16 16 ±0.OO15 ±0.0015 ±O.OO15 ±0.OO15 1 S 1 S -2mA +10V ±lmA ±10V Low OLE Around Zero DAC71 0 DAC711 16 16 ±0.0015 ±0.0015 Styp S typ ±lmA ±10V Com Com DDIP DDIP 6.1-65 6.1-65 Lowest Cost DAC1600 16 ±O.003 Styp ±10V Com DDIP 6.1-1 OS Bus Interface: 16-Bit Parallel SeriaVS-bit Parallel SeriaV8-bit Parallel Dual,Ser.tS-bit Par. DAC707 DAC708 DAC709 DAC725 16 16 16 16 ±O.003 ±O.003 ±O.OO3 ±O.003 S 1 S 8 Industry Standard, DAC70BH General Purpose DAC71 16 16 ±0.003 ±O.003 1 S DAC72BH 16 ±O.003 Industry Standard DAC7541A Ind. Std. wtlatch DAC7545 12 12 ±O.012 ±O.012 1 2 Dual w/Bus Interface: Serial Input DAC7800 S-bit Port Interface DAC7801 12-bit POrllnterfaceDAC7802 12 12 12 ±O.012 ±O.012 ±O.012 0.8 0.8 0.8 12 ±D.OD6 4 12 12 12 ±O.006 ±D.OD6 ±O.o1S 12 ±O.012 12 12 ±O.012 ±O.012 Flexible Bus Interface: Industry Standard DAC667 Pinout DACSll Small, Low Cost DAC813 Lowest Cost DAC1201 Industry Standard, DACSO General Purpose DAC85H DACS7H Com, Com, Com, Com, Ind, Ind, Ind, Ind, Mil Mil Mil Mil DDIP DDIP DDIP DDIP a,BI a,BI a,BI BI 6.1-53 6.1-53 6.1-53 6.1-72 Ind Com DDIP DDIP BI BI 6.1-5 6.1-13 Ind DDIP BI 6.1-5 OtolmA Oto lmA Com,lnd, Mil Com,lnd,MiI DDIP,SO DDIP,SO a,BI BI 010 lmA Oto1mA Oto1mA Com Com Com DIP, SO DIP,SO DIP,SO SS.1-17 SS.1-17 S6.1-19 DIP,SO SS.1-5 Com, Ind, Mil ±10V ±lmA,-2mA Com, Ind, Mil ±5v, ±10v, + 10V Com, Ind, Mil ±10V Com,lnd ±lmA,-2mA ±lmA,-2mA; +10V,±10V ±2.5V, ±5V,±10V Com, Ind, Mil +5V, ...10V 4 ±5V, ±10V, +10V Com,lnd, Mil 4 ±5V, HOV, ...10V Com, Ind, Mil 4typ ±5V,±10V,+10V Com 0.3, ±lmA, -2mA; +5'1. 3 typ +10'1. ±5V, ±10V 6.1-112 6.1-120 DDIP,SO DIP,SO DDIP BI 6.1-90 S6.1-7 6.1-103 Com DDIP BI 6.1-27 Ind Mil DDIP DDIP a,BI a,BI 6.1-35 6.1-35 NOTES: (1) Temperature Range: Com = O·C to +70·C,lnd = (-25°C to +S5·C) or (--40·C to +S5°C), Mil m-55·Cto +125°C. (2) DIP = 0.3" wide DIP, DDIP = 0.6" wide DIP, SO = small outline surface mount (3) a indicates that optional reliability screening is available for the model. BI indicates that an optional 160 hour burn-in is available for the model. 6-2 Burr-Brown IC Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) AUDIO AND COMMUNICATIONS DIGITAL-To-ANALOG CONVERTERS Boldface = NEW Model Resolution (Bits) MaxTHD+N (Vour =FS) Output Range Input Format Power Supply (V) PCM53 16 -88dB (JP) -92dB(KP) ±10V.±1mA Parallel ±15.+5 DDIP 600 6.2-152 PCM54 16 -82dB(HP) -88dB (JP) -92dB(KP) ±3V.±1mA Parallel ±5to±12 DDIP 300 6.2-164 PCM55 16 -82dB (HP) -88dB (JP) ±3V.±1mA Parallel ±5 SO 125 6.2-164 PCM56 16 -82dB (P) -88dB (P-J) -92dB (P-K) ±3V.±1mA Serial Latched ±5to±12 DIP 260 6.2-172 PCM60 16 -82dB(P) -86dB (P-J) 2.8Vp-p, 2-Channel Serial Latched +5 SO 50 56.2-27 PCM66 16 -82dB(P) 2.8Vp-p, 2-Channel Serial Latched +5 SO 50 56.2-27 PCM1700 18 -82dB (P) -88dB (P-J) -92dB(P-K) ±3V, ±O_67mA Serial Latched ±5 DDIP 380 59.2-183 PCM58 18 -92dB (P) -94dB (P-J) -96dB (P-K) ±1mA Serial Latched +5.-12 DDIP 400 6.2-180 PCM61 18 -82dB(P) -88dB (P-J) -92dB(P-K) ±3V,±1mA Serial Latched ±5to±12 DDIP 200 56.2-35- PCM63 20 -88dB(P) -92dB (P-J) -86dB(P-K) ±2mA Latched ±5 DDIP 200 56.2-39 PCM64 18 -96dB ±1mA Parallel +5.-15 DIP 400 6.2-194 NOTES: Packagel') Power Dissipation (mW) Page No. (1) DIP = 0.3" wide DIP, DDIP = 0.6" wide DIP. SO = Small Outline Surface Mount. :2W Ii: = Z 0 U "9c z CI ~..I i! -"-a Burr-Brown Ie Data Book Supplement, Vol. 33b 6-3 For Immediate Assistance, Contact Your Loca/Salesperson Boldface =NEW DIGITAL SIGNAL PROCESSING DIGITAL·TO-ANALOG CONVERTERS Resolution Model (Bits) Signal. to-Noise + Distortion Ratio (dB) Linearity Error (%FSR) Settling TIme (I1S) Output Range DSP-Compalible Digital Interface (Single-DSP201. DuaI-DSP202): DSP201 18 ±D.D06 ±3V 86, tOUT =2kHz DSP202 18 ±D.D06 ±3V 86, tOUT =2kHz Ultra-Fast Settling. ECL Input: DAC6S 12 ±C.012 12 ±0.012 DAC63 40ns SOns ±1.2V. ±6.3SmA ±SmA. 0 to -10mA ±C.SV. Oto +1.5V with internal resistor Ultra-Fast Settling. TTL Input: DAC812 12 ±0.012 SOn!! ±SmA. 0 to -10mA ±O.SV. 0 to -1.5V with internal resistor NOTES: 70. fOUT = 1MHz Total Harmonic Distortion Temp (dB) Rangelll Pkg(2) Page No. -80 -80 Ind Ind DDIP DDIP 514-16 514-16 -68 Com Ind DDIP 6.2-143 DDIP 6.2-135 Ind DDIP 6.2-146 (1) Com = O·C 10 +70·C. Ind - (-2S·C to +8S·C) or (-40·C to +8S·C). (2) DDIP. 0.6" wide DIP. MODELS STILL AVAILABLE BUT NOT FEATURED IN THIS BOOK DAC10HT DAC90BG DAC90SG DACSOOP-CBI-V DAC800P-CBI-1 DAC80o-CBI-V DAC80o-CBI-1 DAC8S0-CBI-V DAC8S0-CBI-1 DAC8S1-CBI-V DAC8S1-CBI-1 6-4 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) BURR-BROWN® DAC667 1-=:1-=:11 ADVANCE INFORMATION SUBJECT TO CHANGE FEATURES • MONOTONICITY ",u',..n,""~ TEMPERATURE • • ·~K •• "'"',." ..'n t(f1j",d:na: (pI"evi:g. \!. :.!l~ stored in adjacent latches) from ., the D/A latch. This feature avoids ··'·<,>,}>,{""'~""Vy,,,;,,".l.I""'!l output values while using an interface computer instructions. The digital the DAC667 is minimized by the lack ''Q(,.high-iInpt!dalnce pins to pick up noise and by the use separate digital supply and ground pins (+Vo and . DCOM). The DAC667 is specified to ±l/4LSB maximum linearity error (B and K grades) at 25°C and ±l!2LSB maximum over the temperature range. All grades are guaranteed monotonic over the specification temperature range. The DAC667 is available in two performance grades and in plastic and ceramic package types. 20VSpan 5kll u .~ a z o -~ 10V Span 5kll IIII Ii:III ft o Sum Jet VOUT 12 III AGnd Bip Off Il ~ II: Inlernatlanal Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson. AZ 85734 • Street Address: 6730 S. TUcson Blvd. • Tucson, AZ 85706 Tel: (602) 746-1111 • Twx: 910-952·1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (602) 889·1510 • Immediate Product Info: (800)548-6132 PDS·IORO Burr-Brown Ie Data Book Supplement. Vol. 33b 6.1-5 Inz - For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL TA = +25"C. +Vcco -VEE = ±12V or ± 15V and load on Vrur = 5kr.llo ground unless otherwise noted. UNITS PARAMETER DIGITAL INPUT Resolution logic Levels. TTL Compalible VH T.~ V, 'H• I,. 12 Bits 2 2 +5.5 +0.8 10 5 VDC VDC pA pA ±1I4 ±112 to T... +2.0 +0 VH = 5.5V VL = 0.8V ACCURACY (+V... -Va = ±12V or ± 15V) Uneartty Error at 25"C T" .. TUIN 10 TMAX Differential Unearity Error T" .. TMIN to TMAX Gain Error'" Unipolar Offsel Erro~" Bipolar Offsel E~" ±1/4 LSB LSB LSB LSB % LSB DRIFT (OVer SpecIfication Temperalure Range) Dlfferenllal Unearily Gain (Full Scale). TA • 25"C 10 T... or T... Unipolar Offsel. TA = 25"C to T.~ or T..... Bipolar zero. = 25"C to lIS lIS lIS Vips v V mA mA V mA 10 10 ppm of FSJ% of FSJ% ±16.5 V V 15 11 mA mA ±12. ±15 10 7.5 o -25 -65 -65 +70 +85 +125 +150 ~;~~f~~1:;~ trim potenllomeler. (2) FSR means Full Scale Range and is 20V for the ±10V range. ABSOLUTE MAXIMUM RATINGS +V"" to Power Ground .................................................................. O to +18V -vco to Power Ground ................................................................... 0 to -18V Diglial Inputs (pins 11-15, 17-28) to Power Ground ........... -1.0V to +7.0V Exlemal Voltage Applied to BPO Span Resislor ...............................: ±18V Ref In 10 Reference Ground ................................................................. ±12V Bipolar Offsel to Relerence Ground .................................................... ±12V 10V Span Resistor 10 Raference Ground ............................................ ±I2V 20V Span Resistor to Reference Ground ............................................ ±24V Ref Out, Vrur (Pins 6, 9) ........................ Indefinila Short to Power Ground 6.1-6 Ref Out VOJT (Pins 6. 9) ........................................ Momentary Short 10 +V· Power DiSSipation ........................................................................... l000mW Leed Temperature (soldering IDs) ................................................... +3OO"C Max Junction Temperalure ................................................................. 165·C Thermal Resistance, II...: Plastic DIP ............................................ 130·C/W Thermal Resistance, 11,..: Ceramic DIP ........................................... 850CfW NOTE: Stresses above those listed under "Absolute Maximum RatIngs" may cause pennanenl damage to the device. Exposure 10 absolute maximum conditions for extended periods may affect device reliabiUty. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (IlSA Only) BURR-BROWN@ DAC813 IEaEaI ADVANCE INFORMATION SUBJECT TO CHANGE Microprocessor-Compatible 12-81T DIGITAL-TO-ANALOG CONVERTER FEATURES vener with voltage output operational amplifier. Fast switches and laser-trimmed thin-film resistors .. , "'" . a highly accurate, fast D/A ., . • ±1/2LSB NONLINEARITY OVER TEMPERATURE • GUARANTEED MONOTONIC OVER TEMPERATURE • LOW POWER: 270mW max • DIGITAL INTERFACE DOUBLE BUFFERED: 12 AND 8 + 4 • SPECIFIED AT ±12V AND . SUPPLIES failure . . ±1/2LSB maximum Iin±1/4LSB (K, B grades). 0.3" wide ceramic DIP :cifi,catillntemperature range), 28DIP and 28-lead plastic SO (O°C I1M Ii: E o u r-~W\'----o ~ SPO a z o +--'W\r----o 20V span :-; f2 1M +--A.J\I\r---o 20V span Converter Ie InIernatlonalAlrportlndustrlalParlc • IlalilngAddress:POBoII1400 • TUC8CH1,AZ8S734 • S1reet Address: 6730 S. 'lllcsanBlvd. • Tucaon,AZ 85706 Tel:(602)746-1111 .......:9111-952·1111 • C8ble:BBRCORP • Telel:Q66.&I91 • FAX: (602)1189-1510 • ImmedIateProducUlIo:(IIIID)54U132 PDS·1077 Burr-Brown Ie Data Book Supplement, Vol. 33b 6.1-7 Ii! zIii - For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL T a +25'C. • :Iol2V or :Io15V and load on PARAMETER unless otherwise noted. CONDITIONS DIGITAL INPUT Resolution Codes") Digilal Inputs Over Temperature Aanget'l V" V. DATA Blis WR. Resel. LDAC. LMSB. USB UNITS 12 BIts +5.5 VOC VDC pA pA pA pA USB. BOB +2 o I". V" a I•• V... .... V" a • +0.8 :1010 :1010 :1010 :1010 +2.7V +GAV +2.7V +G,4V ACCURACY Unearily Error Differential Unearlty Error Gain Erro~" Unipolar Offsel Erro~" Bipolar Zero Erro~~ Monotonlclly Power Supply Senslllvlly: +Vee -Vee DRIFT GaIn Unipolar 0fIse1 Bipolar Zero . Unearlly Error Over Temperature Range Over Range SETTLING l1ME'" (To W~hin :to.OI% FSR of Final 5kllIiSOOpF For Full Scale Range Change ps ps ps Vips V V Oulput Current Oulput Impedance Short Circuit to Common rnA n V rnA 2 :1010 Indefinile POWER SUPPLY VoRage: +Vee -Vee Current: +Vco -Vee Potential at DeeM with Power Dissipation TEMPERATURE RANGE Speclflcation: J. K A.B Storage: J. K A.B +15 -15 10 -5 -3 225 0 ~ -60 -65 :t4O ±25 n ppmI"C +16.5 -16.5 13 -6 +3 270 VDC VOC mA +70 +85 +100 +150 'C 'C 'C 'C rnA V mW 'Same as specification for DAC813AH. JP. JU. NOTES: (1) USB. Unipolar Straight Binary; BOB. Bipolar Offset Binary. (2) TIL and 5V CMOS compatible. (3) SpecifIed with 5000 Pin 6 to 7. Adjustable to zero with ex1emallrlm potentiometer. (4) Error allnput code ooO",x for unipolar mode. FSR • 10V. (5) Error at Input code 800.... for bipolar range. Specified with loon Pin 6 to 4 and with soon pin 6 to 7. See paga 9 for zero adjustment procedure. (6) FSR means Full Scale Range and Is 20V for the :IoIOV range. (7) Maximum represents the 30 limit Not 100% tested for this paramater. (8) AI the major carry. 7FFHEX to 8OO1EX and 800.... 10 7FFHEX' (9) Tha maximum voltage al which ACOM and DCOM may be separaled without affecting accuracy speclflcatlons. 6.1-8 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) MECHANICAL H Package - 0.3" 28-Pln Hermetic DIP 1-~-8------ A -------15-1'1 14 INCHES MIN MAX DIM A 1.388 lA12 B .300 .320 C 0 F G J K .160 .016 .020 .050 BASIC .095 .IOS .009 .012 .125 .180 .290 .310 .040 .060 L N - I.IIWMETERS MIN MAX 35.26 35.86 7.62 8.13 4.06 0.41 0.51 1.27 BASIC 2.67 2.41 0.23 0.30 3.18 4.57 7.37 7.87 1.02 1.52 - NOTE: Leads In !rUe position wllhln 0.01" (0.25mm) Ret MMC et sealing plane. Pin numbers shown for reference only. Numbers may not be marked on package. Metal lid connected to-Vee' P Pac:IaIge - 0.3" 28-P1n PlasUc DIP ~----------A-----------~ o III Ii: E DIIoI A B C 0 G H J L 1.1 N INCHES MIN MAX .700 .716 .286 .302 .093 .109 .016 BASIC .050 BASIC .022 .038 .Q09 .012 .398 .414 5°TVP .000 .012 MIWMETERS MIN MAX 17.78 18.19 7.26 7.67 2.36 2.77 0.41 BASIC 1.27 BASIC 0.56 0.97 0.20 0.30 10.11 10.52 5°TVP 0.00 0.30 NOTE: Leads In !rUe position wllIlln 0.01· (O.25mm) R at MMC at sealing plane. Pin numbers shown for reference only. Numbers may not be marked on package. o() ~ a z o =c ...z II :IE i Inz - Burr-Brown Ie Data Book Supplement, Vol. 33b 6.1-9 For Immediate Assistance, Contact Your Local Salesperson MINIMUM TIMING DIAGRAMS PIN DESCRIPTIONS (Load Drst rank from Data Bus: i:6Ac. 1) I _ _ _ _-..II--->4Ons - , ThIs point Is Internally connected to +V. and Is a decoupllng point only. Separate bypass cepacltore will minimize Intemal dlgltalleedthrough to analog I LLSB,LMsB signals. Connect PIn 2 or Pin 3 to Pin 9 (Vour) fOr a 20V FSR. Connect both to Pin 9 fOr a 10V FSR. -- DBll-DBO >Ons Bipolar offset Connect to Pin 6 (VlEFour) through loon resistor or 200n potentiometer lor bipolar operaUon. Analog common, ±V00 supply rewm. +10V reference output WRITE CYCLE" Connected to VlEFour through a lkn gain edJuslll1ent potenUometer or a soon resistor. Analog supply Input, nominally +12V 10 +15V referred 10 ACOM. LDAC Data Bit 9. Data BR 10. Data BR 11. Data Bit 12, MSB, poslUve true. Power DIssIpation ............................................................................. 750mW Lead TemperaWre (80Ide~ng. lOs) ..................................................+3OO·C Max Junction TemperaWre ...............................................................+I65·C Thermal Reslstanoe, 9....: Plastic DIP and SOIC .......................... I30'CIW Caramlc DIP .......................................... 65'c/w NOTE: Stresses above those listed under·AbsoIute Maximum Ratings· may cause permanenl damage to the device. Exposure 10 absolUID maximum conditions lor extended periods may aHeet device reliability. +V.. to ACIJM ,.....".....".......: -Vee 10 +Vco 10 -VDC : ......" ......" ...... ACOM10 DCOM Digital Inputs (Pins External Voltage Applied VlEFour ...........".......".........."......."........... Vour ORDERING INFORMATION MODEL DAC813JP DAC813JU DAC613KP DAC613KU DAC813AH DAC613BH 6.1-10 PACKAGE TEMPERATURE RANGE PlastIc DIP Plastic SOIC Plastic DIP Plastic SOIC CeramIc DIP CaramlcDIP 0'010+70'0 0'010+70'0 O'C10 +70'C O'CIo+7O'O -25'0 10 +65'0 -25'CIo+65'C UNEARITY ERROR,MAX AT+25'C ±II2LSB ±II2LSB ±1I4LSB ±lI4LSB ±II2LSB ±1I4LSB GAIN DRIFT (ppml'C) 30 30 20 20 30 20 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Cuslomer Service al 1·800·548·6132 (IJSA Only) TYPICAL PERFORMANCE CURVES T. m +25'C. Vco m ±15V unless OIherwise nOled. DIGITAL INPUT CURRENT va INPUT VOLTAGE POWER SUPPLY REJECTION vs POWER SUPPLY RIPPLE FREQUENCY 'lk • • IUlij! -;~ I!' ... 2'0 100 ~ I 10 ~E 0 1--h..-+-.....-t--+118SIl~_-t--I-...-I-11--1 i ffi! II. .e j B 100 Ik 10k lOOk a 1M Frequency (Hz) CHANGE OF GAIN AND OFFSET ERROR vs TEMPERATURE r---...,...---r----,r---rl' 0.1 0.05 I----I----t---+"'DOJ""'--'-----=- ~ ~ ~ g 10 > 0 i B ::I ~ 0 100p jE 3Vrms 6Vrms -90 10p IIII1 -95 1p II -100 -75 -50 -25 +25 +50 +75 +100 +125 10 100 1k TemperalUre ('C) CHANNEL·TO-CHANNEL ISOLATION vs FREQUENCY iii' 0 -30 -10 -50 l! -80 m \ -50 ...E-iii 0 FEEOTHROUGH vs FREQUENCY -20 -40 -70 '" -90 -100 ./ -110 , 11\ -20 1'\ iii' -30 J:: -40 E- ~ co ::0 -50 l! ~ II> -60 IL -70 CD '" '" ". -80 ./ -90 -100 -120 lk 10k 100k 10M 1M 1k Frequency (Hz) CFI=~J +20 +10 iii' ~ -10 ECl PSRR vs FREQUENCY cFI=W 60 I 50 \ ~. OAC Loaded wlOs .......... r-..... E- o: 30 0: CF= 10pF Ie 20 10 -40 0 .......,: ...... OAC Loaded w/1s.... 10k 100k Frequency (Hz) 1M 10M :"" IIIIJI -10 -50 6.1-22 JJ 1111 II IIII f::::::: .... iii'40 -30 ·1k 10M 1M lOOk 70 ~ -20 10k Frequency (Hz) FREQUENCY RESPONSE +30 0 100k 10k Frequency (Hz) 1k 10k 100k 1M Frequency (Hz) Burr-Brown Ie Data Book Supplement, Vol. 33b Dr, Call Customer Service at 1·800·548·6132 (USA Dnly) DISCUSSION OF SPECIFICATIONS RELATIVE ACCURACY This term, also known as end point linearity or integral linearity. describes the transfer function of analog output to digital input code. Relative accuracy describes the deviation from a straight line after zero and fulI scale errors have been removed. DIFFERENTIAL NONLINEARITY Differential nonlinearity is the deviation from an ideal I LSB change in the output when the input code changes by I LSB. A differential nonlinearity specification of I LSB maximum guarantees monotonicity. GAIN ERROR Gain error is the difference between the fulI-scale DAC output and the ideal value. The ideal fulI scale output value for the DAC7802 is -(4095!4096)V REF' Gain error may be adjusted to zero using external trims as shown in Figures 3 and 5. OUTPUT LEAKAGE CURRENT The current which appears at lOUT A ahd loUT B with the DAC loaded with alI zeros. OUTPUT CAPACITANCE This is the parasitic capacitance measured from lOUT 10UTB to AGND. A or CHANNEL-TO-CHANNEL ISOLATION The AC output error due to capacitive coupling from DACA to DACB or DACB to DACA. MULTIPLYING FEEDTHROUGH ERROR The AC output error due to capacitive coupling from VREF to loUT with the DAC loaded with all zeros. OUTPUT CURRENT SETTLING TIME The time required for the output current to settle to within ±O.OI % of final value for a fulI scale step. DlGITAL-TO-ANALOG GLITCH ENERGY The integrated area of the glitch pulse measured in nanovoltseconds. The key contributor to digital-to-analog glitch is charge injected by digital logic switching transients. DIGITAL CROSSTALK Glitch impulse measured at the output of one DAC but caused by a fulI scale transition on the other DAC. The integrated area of the glitch pulse is measured in nanovoltseconds. CIRCUIT DESCRIPTION Figure 1 shows a simplified schematic of one half of a DAC7802. The current from the VREF A pin is switched between lOUT A and AGND by the CMOS FET switch for that bit. This circuit architecture keeps the resistance at the VREF A pin constant so the reference could be provided by either a voltage or current, AC or DC, positive or negative polarity, and have a voltage range up 10 ±20V. Burr-Brown Ie Data Book Supplement, Vol. 33b AGND DBll OB10 DB9 (MSB) DBO (LSB) FIGURE 1. Simplified DAC Circuit. APPLICATIONS POWER SUPPLY CONNECTIONS The DAC7802 is designed to operate on VDO = +5V ±IO%. For optimum performance and noise rejection, power supply decoupling capacitors CD should be added as shown in the application circuits. These capacitors (lJ.IF tantalum recommended) should be located close to the DAC7802. AGND and DGND should be connected together at one point only, preferably at the power supply ground point. Separate returns minimize current flow in low level signal paths if properly connected. Output op-amp analog ground should be tied as near to the AGND pin of the DAC7802 as possible. WIRING PRECAUTIONS To minimize the AC feedthrough when designing a PC board for the DAC7802, great care should be taken to minimize capacitive coupling between the V REF lines and the lOUT lines. Similarly, capacitive coupling between DACs may compromise the channel-to-channel isolation. Coupling from any of the digital control or data lines might degrade the glitch and digital crosstalk performance. Whenever possible, solder the DAC7802 directly into the PC board without a socket. Sockets add parasitic capacitance (which can degrade AC performance as described) and resistance (which may impact the DC accuracy). AMPLIFIER OFFSET VOLTAGE As with all precision CMOS MDACs, the output amplifier used with the DAC7802 should have low input offset voltage to preserve the transfer function linearity. The voltage output of the amplifier has an error component which is the offset voltage of the op-amp multiplied by the "noise gain" of the circuit. This "noise gain" is equal to (; was used to calculate MTTF at an ambient temperature of 25°C and 85"C. These test results yield MTTF of 2.5E+7 hours at 25°C and 2.6E+5 hours at 85°C. Additional tests such as PCT have also been performed. Reliability reports are available upon request. Control circuitry omitted lor clarity. A1. A2 OPA602 or 112 OPA2107. UNIPOLAR CONFIGURATION Figure 2 shows the DAC7802 in a typical unipolar (twoquadrant) multiplying configuration. The analog output values versus digital input code are listed in Table 11. The operational amplifiers used in this circuit can be single amplifiers, such as the OPA602, or a dual amplifier such as the OPA2107. Cl and C2 provide phase compensation to minimize settling time and overshoot when using a high speed operational amplifier. If an application requires the DAC to have zero gain error, the circuit shown in Figure 3 may be used. Resistors R2, and R4 induce a positive gain error greater than worst case initial negative gain error for a DAC7802KP. Trim resistors R I and R3 provide a variable negative gain error and have sufficient trim range to correct for the worst case initial positive gain error plus the error produced by R2 and R4. FIGURE 3. Unipolar Configuration with Gain Trim. BIPOLAR CONFIGURATION Figure 4 shows the DAC7802 in a typical bipolar (fourquadrant) multiplying configuration. The analog output values versus digital input code are listed in Table m. The operational amplifiers used in this circuit can be single amplifiers such as the OPA602, a dual amplifier such as the OPA2107, or a quad amplifier like the OPA404. CI and C2 proY-ide phase compensation to minimize settling time and overshoot when using a high speed operational amplifier. The bipolar offset resistors R5-R7 and Rg.;..RIO should be ratio-matched to 0.01 % to ensure the specified gain error performance. If an application requires the DAC to have zero gain error, the circuit shown in Figure 5 may be used. Resistors R2 and R4 induce a positive gain error greater than worst case initial negative gain error for a DAC7802KP. Trim resistors Rl and R3 provide a variable negative gain error and have sufficient trim range to correct for the worst case initial positive gain error plus the error produced by R2 and R4. 12-BIT PLUS SIGN DACS For a bipolar DAC with 13 bits of resolution, two solutions are possible. As shown in Figure 6, the addition of a precision difference amplifier and a high speed JFET switch provides a 12-bit plus sign voltage-output DAC. When the switch selects the op-amp output, the difference amplifier serves as a non-inverting output buffer. If the analog ground side of the switch is selected; the output of the difference amplifier is inverted. Another option, shown in Figure 7, also produces a 12-bit plus sign output without the additional switch and digital control line. FIGURE 2. Unipolar Configuration. 6.1-24 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) +5V Voo R, 20kO VREFA R2 20kO R3 10kO Control circuitry omitted for darity. A1-A4, OPA602 or 112 OPA2107. R. 20kO VREFB FIGURE 4. Bipolar Configuration. Rs +5V 20kO 12 III Ii E o u ~ a z o -~ I"" Z III :IE FIGURE 5. Bipolar Configuration with Gain Trim. i 5 - Burr-Brown Ie Data Book Supplement, Vol. 33b 6.1-25 For Immediate Assistance, Contact Your Local Salesperson +15V 2 , - - - - - - -.....- - t REF102 INA105 Control circuilly omitted for clarity. A1 OPA602 or 112 OPA21 07. FIGURE 6. 12-Bit Plus Sign DAC. +15V 2 6 . - - - - - - -.....--1 REF102 +5V >-"*-t-o ±10V 13 Bits INA105 Control circuitry omitted for clarity. A1. A2 OPA602 or 112 OPA2107. FIGURE 7. I3-Bit Bipolar DAC. 6.1-26 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) BURR-BROWN® PCM60P PCM66P IESIESII 16-Bit CMOS Monolithic Audio DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • LOW COST 16-BIT 2-CHANNEL CMOS MONOLITHIC D/A CONVERTER G SINGLE SUPPLY +5V OPERATION The PCM60P/66P is a low cost, dual output 16-bit CMOS digital-to-analog converter. The PCM60P/66P features true glitch-free voltage outputs and requires only a single +5V supply. The PCM60P/66P doesn't require an external reference. Total power dissipation is less than 50rnW max. Low maximum Total Harmonic Distortion + Noise (-86dB max; PCM60P-J, PCM66P-J) is 100% tested. Either one or two channel output modes are fully user selectable. e 50mW POWER DISSIPATION • GLITCH-FREE VOLTAGE OUTPUTS • LOW DISTORTION: -86dB max THO + N • COMPLETE WITH REFERENCE ., SERIAL INPUT FORMAT The PCM60P/66P comes in a space-saving 24-pin plastic SOIC package. PCM60P/66P accepts a serial data input format and is compatible with other BurrBrown PCM products such as the industry standard PCM56P. • SINGLE OR DUAL DAC MODE OPERATION • PLASTIC 20-PIN SOIC PACKAGE (PCM66P) .. PLASTIC 24-PIN SOIC PACKAGE (PCM60P) ~ o() ~ a A. Vee (+5V) Reference ~ V REF io AcoM SDMSEl lRDAC -ti - lCHOut lRClK VOUT WDClK ClK () RCHOut Z ::J DATA DcoM :& :& Inlernallonal Airport Industrial Par. • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85T06 Tel: (602) 746-1111 • Twx: 910-952·1111 • cable: BBRCORP • Telex: 06H491 • FAX: (602) 889-1510 • Immediate Product Info: (BOO) 548-6132 PDS·1051A Burr-Brown Ie Data Book Supplement. Vol. 33b 6.2-27 o() . o a ~ - For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL All specifications at 25'C. and +V" = +5V unless otherwise noted. PCM60PI66P AND PCM60P-JI66P-J PARAMETER CONDITIONS MIN TYP RESOLUTION DYNAMIC RANGE MAX UNITS t6 Elits 96 dB INPUT DIGITAL INPUT Logic Family Logic Level: VIH V" TTL Compatible CMOS 11-1 = +40J,1A max +5.25 0.8 +2.4 0 I, =-40~ max Data Fonnat Input Clock Frequency V V Serial BTC'" 8.5 MHz DYNAMIC CHARACTERISTICS TOTAL HARMONIC DISTORTION + N'" PCM60PI66P: I = 991 Hi (OdB)'" I = 991 Hz (-20dB) f = 991 Hz (-80dS) PCM60p·J/66P.J: f = 991 Hz (OdS) f = 991 Hz (-20dB) f = 991Hz (-8Odb) fs = 176.4kHz[41 Is Is fs fs fs -88 -88 -28 -92 -88 -28 = 176.4kHz = 176.4kHz = 176.4kHz = 176.4kHz = 176.4kHz CHANNEL SEPARATION -82 -86 dB +85 +80 dB dB dS dB dB dB TRANSFER CHARACTERISTICS ACCURACY Gain Error Gain Mismatch Bipolar Zero Error5) Gain Drift Wann·up Time IDLE CHANNEL SNR'" ±2 VO 0 o0 0 0 0 0 0 0 0 0 0 0 ~u -9 =_'- 0 0 0 0 0 0 0 o~ G >=>I< --''--0 J J J l M N INCHES MIN MAX .614 .630 .610 TYP .328 .346 .331 TYP .098 .012 .020 .048 .054 .075 .tl5 .0039 .010 .478 .453 o· TYP .0039 MIWMETERS MIN MAX 15.60 16.00 15.5 TYP 8.33 8.80 8.4 TYP 2.50 0.3D 0.50 1.17 1.37 1.91 2.92 0.1 0.26 11.5 12.1 0" TYP 0.10 NOTE: leads In true position within 0.01" (O.25mm) R at MMC at seatlng plane. ----1 ~ --- ~L lseating Plane C 1 CD !! o CD :IE P Paclcage - 2O-Pln Plastic SOIC PCM66P () A. - - · .. ---·--··-A .. - ......- ........- ... -. DIM A A. B 8. C D G H J L M N INCHES MIN MAX .502 .518 •495 .518 .266 .3D2 .270 .285 .093 .108 .015 .019 .D50BASIC .026 .034 .008 .012 .390 .422 0" 10" .000 .012 MIWMETERS MIN MAX 12.75 13.18 12.57 13.16 7.26 7.87 7.24 6.86 2.38 2.74 0.38 0.48 1.27 BASIC 0.66 0.86 0.20 0.30 9.91 10.72 10" 0" 0.00 0.30 NOTE: leads In true position within 0.01" (O.25mm) R at MMC at seatlng plana• I 8 ~ UTI-rD-TImrmJ;TII~~~.-.-. ~~,JC=~_/ --i G:- --- -~D ···Se~tingPlane a A. !.--L-·-··-~ B io ABSOLUTE MAXIMUM RATINGS DC Supply Voltage ............................................................................. ±1 ov Input Voltage Range ...........................................................-aV to +5.2SV Power Dissipation ............................................................................ 50mW Operatlng Temperature .....................................................-aO·C 10 +70"C Storage Temperature ...................................................... -60·C to +100·C lead Temperature (soldering. 10s) ................................................ +300·C ORDERING INFORMAnON _ __________~pc~M~60~P~/pc~M~~P Basic Modal Number P: Plastfc Perfonnance Grade Code :It I -::» !; u z :IE :IE o() -oa Burr-Brown Ie Data Book Supplement. Vol.33b 6.2-29 ~ For Immediate Assistan~e, PCM60P PIN ASSIGNMENTS PIN PCM66P PIN ASSIGNMENTS DESCRIPTION MNEMONIC LRCLK WDCLK CLK DATA NC NC 9 10 11 12 13 14 15 16 LeftiRlghl Clock Word Clock Clock Inpul Data Inpul No Connection No Connection Digital Common Analog Common No Connection Left Channel V<>If Output Common Righi Channel V.. +Vcc Analog Supply +Vcc Analog Supply Reference Decouple No Connection 17 VREF Sense 18 19 20 21 22 23 24 Voltage Reference +Vcc Analog Supply +Vcc Analog Supply +Vcc Digital Supply No Connection Single DAC Mode LeftiRlghl DAC Select 1 2 3 4 5 6 7 8 Contact Your Local Salesperson PIN I 2 3 4 5 6 7 0"", Acou 8 NC LCH Out V"", R CH Out 9 10 11 12 +Vcc 13 +Vcc CREF 14 15 16 17 18 19 20 NC V,,,,SENSE V,El' +Vcc +Vcc +Vcc DESCRIPTION MNEMONIC LefllRighl Clock Word Clock Clock Inpul Data Inpul No Connection Digital Common Analog Common Left Channel V<>If OutpUl Common RIghi Channel Vasr Analog Supply Analog Supply Reference Decouple Reference Sense Reference Output Analog Supply Analog Supply Digital Supply Single DAC Mode LeftiRight DAC Setect LRCLK WDCLK CLK DATA NC 0 .... Acou LCH Out V_ R CH Out +V.. +V.. CAEF V"" SENSE VAEF +V.. +Vcc +Vcc SDM SEL LRDAC NC SDM SEL LRDAC THEORY OF OPERATION The PCM60P/66P is a dual output, 16-bit CMOS digital-toanalog audio converter. The PCM60P/66P, complete with internal reference, has two glitch-free voltage outputs and requires only a single +5V power supply. Output modes using either one or two channels per DAC are user selectable. The PCM60P/66P accepts a serial data input format that is compatible with other Burr-Brown PCM products such as the industry standard PCM56P. ONE DAC TWO-CHANNEL OPERATION Normally, the PCM60P/66P is operated with a continuous clock input in a two-channel output mode. This mode is selected when SDM SEL is held low· (single DAC mode select). Refer to the truth table shown by Table I for exact control logic relationships. Data for left and right channel output is loaded alternately into the PCM60P/66P while the control logic switches the left and right output amplifiers between the appropriate· integrate and hold modes. Data word latching is controlled by WDCLK (word clock) and channel selection is made by LRCLK (left/right clock). Figure 1 shows the timing for the single DAC two-channel mode of operation. The block diagram in Figure 2 shows how a single DAC output provides switched output to both integrate and hold amplifiers. Output between left and right channels in this mode is not in phase. See Figure 3 for proper connection of the PCM60P/66P in the two-channel DAC mode. SDMSEL LRDAC LRCLCK· WDCLK SERIAL DATA WORD INPUT LEFT CHANNEL OutPUT RIGHT CHANNEL OutPUT 0 0 0 0 X X X X 0 0 1 1 0 1 0 1 Right Righi Left Left Hold Integrate Hold Hold Hold Hold Hold Integrate 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 Inhibited Inhibited Left Left V.",. V""" VCOM VCOM Hold Hold Integrale Integrale 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 Righi Right Inhibited Inhibited V.",. VCOM V_ V"", Hold Hold Integrate Integrate PIN FUNCTIONS NOTE: Positive edge of CLK (P3) latches LRCLK (PI). WDCLK (P2). and DATA (P4). TABLE I. PCM60P/66P Logic Truth Table. 6.2-30 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TWO CHANNEL PER DAC OUTPUT MODE P3 (CLK) P2(WDCLK) lJlIl ~ ~ Pl (LRCLK) ~ P4(DATA) JJD Pl0 (LCH OUT) Hold ____~_____--'I Load Right Channel Data ~ Integrate L Load Left Channel Data L ~ L Hold =>-==== Pl0 (LCH VOUT ) P12 (RCH OUT) ~~ ~ Hold Integrate co L !! o =>-==---- P12 (RCH VOUT ) CO :I Co) NOTES: Single DAC Mode Select =0; LJR DAC Select = X; WDCLK =50% duty cycle; Serial Data Is read In MSB flrstwlth BTC coding (MSB = Bit 1). & SINGLE CHANNEL PER DAC OUTPUT MODE P3 (CLK) Both DACs ~ ~ ~ Pl (LRCLK) Both DACs ~ I P4(DATA) Both DACs JJD P12 (RCH OUT) RlghtDAC ~ P2(WDCLK) Both DACs Load Right DAC Data 8 ~ a Load Left DAC Data I ~ ~ Hold Integrate io L Iiiu =>-== P12 (RCH VOUT) RlghtDAC P12 (RCH OUT) LeftDAC I JlflJlJ1JlJlJlJ ~ L L lJ1Jl ~ ~ Hold P12 (RCH VOUT ) LeftDAC Integrate - L z =>-== :» :I :I NOTES: Single DAC Mode Select = 1; LJR DAC Select =0 (Left DAC) or 1 (Right DAC). oCo) o- FIGURE 1. PCM60P/66P Timing Diagram. Burr-Brown Ie Data Book Supplement, Vol. 33b 6.2-31 a ~ For Immediate Assistance, Contact Your Local Salesperson 16-BIID/A LCH Vour Converter SDMSEL +-'-----<0 VCOM RCH Vour FIGURE 2. PCM60P/66P Block Diagram. PCM60P PCM66P LRDAC IMode Select I 24 SDMSEL NC +Vcc +Vcc +ycc LCHOut C3 VCOM +Vcc R CH Out +Ycc RCHOut 13 + O.IpF 3.3pF FIGURE 3. PCM60P/66P Connection Diagram. TWO DAC TWO-CHANNEL OPERATION In phase, two-channel output can be obtained by using two PCM60P/66Ps and choosing the single DAC mode (setting SDM SEL high). With the use of a high or low input level on LRDAC (P left/right DAC select), each DAC can have its right channel output dedicated to either left or right data input with no additional input signals being required to latch the appropriate data from an alternating L/R data word input 6.2~32 stream. In the single DAC mode, the PCM60P/66P's left channel output is disabled and held at + VCOM' In this mode both DACs share common inputs for DATA, CLK. WDCLK. and LRCLK. Otherwise circuit connection is the same as the two-channel DAC mode, with the exception of LRDAC whose level selects whether the single DAC will output dedicated left or right channel data. Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1-800-548-6132 (USA Only) into an analog type distortion analyzer. Figure 4 shows a block diagram of the production THD + til test setup. INTEGRATE AND HOLD OUTPUT AMPLIFIERS The PCM60P/66P incorporates integrate and hold amplifiers on each output channel. This allows a single, very fast DAC 10 feed both amplifiers and reduce circuit complexity. It also serves to block the output glitch from the DAC to the individual channel outputs and effectively makes the PCM60P/66P outputs "glitch-free." The PCM60P/66P is a single +5V supply device with a voltage output swing of 2.8Vp-p. The outputs swing asymmetrically around VCOM (+VCC- 2.33V). See Table II for exact input/output relationships. Since true CMOS amplifiers are used on the PCM60P/ 66P, the load resistance on the outputs should not be less than lookn and the capacitive loads should not exceed loopF. For maximum low-distortion performance, output buffer amplifiers should be considered. DIGITAL INPUT Binary Two's Complement (Hex) In terms of signal measurement, THD + N is the ratio of Distortion RMs + NoiseRMsiSignalRMs expressed in dB. For the PCM60P/66P, THD + N is 100% tested at three different output levels using the test setup shown in Figure 4. It is significant to note that this circuit does not include any output deglitching circuitry. This means the PCM60P/66P meets even its -6OdB THD + N specification without use of external deglitchers. ABSOLUTE LINEARITY Even though absolute integral and differential linearity specs are not given for the PCM60P/66P, the extremely low THD + N performance is typically indicative of 14-bit to 15-bit integral linearity in the DAC depending on the grade specified. The relationship between THD + N and linearity, however, is not such that an absolute linearity specification for every individual output code can be guaranteed. ANALOG OUTPUT Vollage (V) Vwr Mode DAC Oulput (V) 7FFF 0000 8000 2E5B +FS BPZ -FS +3.5629443 +2.1629871 +0.7630299 +2.6700000 VCOM IDLE CHANNEL SNR Another appropriate spec for a digital audio converter is idle channel signal-to-noise ratio (idle channel SNR). This is the ratio of the noise on either DAC output at bipolar zero in relation to the full scale range of the DAC. The output of the DAC is band limited from 20Hz to 20kHz and an Aweighted filter is applied to make this measurement. TABLE II. PCM60P/66P Input/Output Relationships. DISCUSSION OF SPECIFICATIONS TOTAL HARMONIC DISTORTION + NOISE OFFSET, GAIN, AND TEMPERATURE DRIFT The PCM60P/66P is specified for other important parameters such as channel separation and gain mismatch between output channels. And although the PCM60P/66P is primarily meant for use in dynamic applications, typical specs are also given for more traditional DC parameters such as gain error, bipolar zero offset error, and temperature gain drift. The key specification for the PCM60P/66P is total harmonic distortion plus noise. Digital data words are read into the PCM60P/66P at four times the standard audio sampling frequency of 44.lkHz or 176.4kHz for each channel, such that a sine wave output of 991Hz is realized. For production testing, the output of the DAC goes to a programmable gain amplifier to provide gain at lower signal output test levels and then through a 20kHz low pass filter before being fed Io u ~ a Use 400Hz High-Pass Filter and 30kHz Low-Pass Filter Meter SeUings Binary Counter t Distortion Meter (Shiba Soku Model 725 or Equivalent) Digital Code (EPROM) Programmable Gain Amp OdBto SOdB Parallel-to-Serial Conversion ! ~ - t Timing Logic LamhELle 0g LOW-PASS FILTER CHARACTERISTIC _ m -20 :!2. -40 DUT (PCM60P/66P) Clock I II a. Low-Pass Filter (Toko APQ-25 or Equivalent) t " ~ 4>0 4>0 -100 -120 1 10' 10' 10' 10' lOS Frequency (Hz) ur z o - = i () :::t II! II! ou Sampling Rate = 44.1 kHz x 4 (176.4kHz) Output Frequency = 991 Hz oa FIGURE 4. THD + N Test Setup Diagram. Burr-Brown Ie Data Book Supplement, Vol. 33b B 6.2-33 = For Immediate Assistance, Contact Your Local Salesperson TIMING CONSIDERATIONS The data format of the PCM60P/66P is binary two's complement (BTC) with the most significant bit (MSB) being first in the serial input bit stream. Table II describes the exact input data to voltage output coding relationship. Any number of bits can precede the 16 bits to be loaded, as only the last 16 will be transferred to the parallel DAC register on the first positive edge of CLK (clock input) after WDCLK (word clock) has gone low. All inputs to the PCM60P/66P are TTL level cornpatible. WDCLK DUTY CYCLE WDCLK is the input signal that controls when data is loaded and how long each output is in the integrate mode. It is therefore recommended that a 50% (high) duty cycle be maintained on WDCLK. This will ensure that each output will have enough time to reach its fmal output value, and that the output level of each channel will be within the gain mismatch specification. Refer to Figure I for exact timing relationships of WDCLK to CLK and LRCLK and the outputs of the PCM60P/66P. The WDCLK can be high longer than 50%, as long as setup and hold times shown in Figure 5 are observed and the time high is roughly equivalent for both left and right channels. SETUP AND HOLD TIMES The individual serial data bit shifts, the serial to parallel data transfer, and left/right control are triggered on positive CLK edges. The setup time required for DATA, WDCLK, and LRCLK to be latched by the next positive going CLK is 15ns minimum. A minimum hold time of 15ns is also required after the positive going CLK edge for each data bit to be shifted into the serial input register. Refer to Figure 5 for the timing relationship of these signals. MAXIMUM CLOCK RATE The 100% tested maximum clock rate of 8.47MHz for the PCM60P/66P is derived by mUltiplying the standard audio sample rate of 44. 1kHz times eight (4X oversampling times two channels) times the standard audio word bit length of 24 (44.1kHz X4 X 2 X 24 = 8.47MHz). Note that this clock rate accommodates a 24-bit word length, even though only 16 bits are actually being used. "STOPPED·CLOCK" OPERATION The PCM60P/66P is normally operated with a continuous clock input signal. If the clock is to be stopped between input data words, the last 16 bits shifted in are not actually shifted from the serial register to the latched parallel DAC register until the first clock after the one used to input bit 16 (LSB). This means the data is not shifted into the DHC latch until the start of the next 16-bit data word input, unless at least one additiona~ clock accompanies the 16 used to serially shift in data in the first place. In either case, the setup and hold times for DATA, WDCLK, and LRCLK must still be observed. INSTALLATION The PCM60P/66P only requires a single +5V supply. The +5V supply, however, is used in deriving the internal reference. It is therefore very important that this supply be as "clean" as possible to reduce coupling of supply noise to the 6.2·34 P3 (ClK) P4 (DATA;.,)_ _ _./ '1f--+--r '-___ P2{WDCLK) Pl (lRCLK) ----': 15nsmin FIGURE 5. PCM60P/66P Setup and Hold Timing Diagram. outputs. If a good analog supply is available at greater than +5V, a zener diode can be used to obtain a stable +5V supply. A 100JlF decoupling capacitor as shown in Figure 3 should be used regardless of how good the +5V supply is to maximize power supply rejection. All grounds should be connected to the analog ground plane as close to the PCM60P/ 66P as possible. FILTER CAPACITOR REQUIREMENTS As shown in Figure 3, CREF and VREF SENSE should have decoupling capacitors of O.IJlF (C4 ) and 10JlF (Cs) to +Vcc respectively with no· special tolerance being required. To maximize channel separation between left and right channels, 5% 300pF capacitors (C2 and C3 )' between VCOM and left and right channel outputs are required in addition to a 5% 31lF capacitor (C,) between VCOM and +5V. The ratio of 10k to 1 is the important factor here for proper circuit operation. Placement of all capacitors should be as close to the appropriate pins of the PCM60P/66P as possible to reduce noise pickup from surrounding circuitry. APPLICATIONS Probably the most popular use of the PCM60P/66P is in applications requiring single power supply operation. For example, the PCM60P/66P is ideal for automotive compact disk (CD) and digital audio tape (DAT) playback units. To use a more complex bipolar DAC requiring ±5V supplies in the +12V application, for example, would require driving a stable "floating" ground and regulating the +12V to +IOV. The single supply CMOS PCM60P/66P would only require a +5V zener diode to regulate its 50mW max supply. The outputs could be AC coupled to the rest of the circuit for perfectly acceptable high dynamic performance. The PCM60P/66P is ideal in any application requiring a minimum of additional circuitry as well as ultra-low-power CMOS performance. Of course, the PCM60P/66P is the D/A converter of choice in any application requiring very low power dissipation. Portable battery powered test and measurement equipment requiring very low distortion digital to analog converters would be an ideal application for the CMOS PCM60P/66P with its 50mW max power dissipation. Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) BURR - BROWN® PCM61P IE':IElI See Also PCM1700P Oual18-Bit 01A Converter Pg.9.2.183 Serial Input 18-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER .. FEATURES DESCRIPTION • 18·BIT MONOLITHIC AUDIO D/A CONVERTER The PCM61P is an IS-bit totally pin compatible per· formance replacement for the popular I6-bit PCM56P. With the addition of two extra bits. lower max THO + N (-92dB; PCM6IP-K) can be achieved in audio applications already using the PCM56P. The PCM6IP is complete with internal reference and output op-amp and requires no external parts to function as an IS·bit OAC. The PCM6IP is capable of an S-tirnes oversampling rate (single channel) and meets all of its specifications without an external output deglitcher. IE u The PCM61P comes in a small. reliable 16-pin plastic DIP package that has passed operating life tests under simultaneous high temperature. high humidity and high pressure testing. I (9 LOW MAX THD + N: -92dB Without Exter· nal Adjust o 100% PIN COMPATIBLE WITH INDUSTRY STD 16·BIT PCM56P II GLITCH FREE OUTPUT OF ±3V OR ±1mA • CAPABLE OF 8X OVERSAMPLING RATE INVourMODE • COMPLETE WITH INTERNAL REFERENCE AND OUTPUT Op·AMP • RELIABLE PLASTIC 16·PIN DIP PACKAGE CD IlL 8 E a Iur z o !; VREF MSBAdj RF Clock lour SJ Latch Enable Vour Data -uz ::::» :E :E Jntema1JonaI AIrpcrllnduSlrJaI Pa'" • lIalllng Address: PO Box 11400 • Tucson, AZ 85734 • Street AddruI: &73G S. TUcIOn Blvd. • Tucson, AZ 857tI6 Tel: (602) 746-1111 • Twx: 91H52·1111 • cable: BBRCORP • Telex: Jl66.6491 • FAX: (602) 8119-1510 • Immediate Ptoduct Info: (602) 746-7270 PDS·972A Burr-Brown Ie Data Book Supplement, Vol. 33b 6.2-35 o u. o a Si For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL All Specifications at 25'C. and +Vcc =+5V unless otherwise noted. PCM61 PIP-J/P-K CONDITIONS PARAMETER MIN TYP RESOLUTION DYNAMIC RANGE MAX UNITS 18 bits dB 108 INPUT DIGITAL INPUT Logic Family Logic Level: +2 0 Viii Vc I," I. nJcMos compinble +Vcc Viii = +2.7V V. =+O.4V Data Format Input Clock Frequency DYNAMIC CHARACTERISTICS Total Harmonic Distortion + NIt) PCMSIP f = 991Hz (OdB)'" f = 991 Hz (-20dB) f = 991 Hz (-SOdB) PCMSlp·J f = 991 Hz (OdB) f = 991 Hz (-2OdB) f = 991 Hz (-SOdB) PCM61P-K f = 991 Hz (OdB) f = 991 Hz (-2OdB) f 991 Hz (-SOdB) = fDLE CHANNEL SNR +0.8 V V +1 -SO J1A J1A 16.9 MHz -82 -68 -28 dB dB dB -88 -74 -{l4 dB dB dB -92 -74 dB dB dB Serial BTC" Without MSB Adjustments fs = 17S.4kHzI"1 fs = 17S.4kHz fs = 176.4kHz -88 -74 fs = 17S.4kHz fs = 17S.4kHz fs = 176.4kHz -94 =17S.4kHz =17S.4kHz =17S.4kHz -98 -80 -40 fs fs fs -{34 -76 -{lS 20Hz to 20kHz at BPZ<" -{34 112 dB ±2 ±30 0/0 mV 0/0 ppm of FSRI'C ppm of FSRI'C TRANSFER CHARACTERISTICS ACCURACY Gain Error Bipolar Zero Error Differential Linearity Error Total Drift'" Bipolar Zero Drift Warm·up Time ±a.OOl ±25 ±4 O'Cto 70'C O'C to'70'C minute 1 MONOTONICITY 16 bits ±3 V mA Il mA k!l ANALOG OUTPUT Voltage: Output Range Output Current Output Impedance Current: Output Range Output Impedance SETILING TIME Voltage: SV Step 1 LSB Slew Rate Current: 1mA Step lmA Step Glitch Energy ±8 0.1 ±1 1.2 ±SO%. ±30% To ±a.oos% of FSR 1.5 1. 12 lOll to loon load 250 lk!lload 350 Meets all THO + N specs without external deglitching llS llS V/llS ns ns POWER SUPPLY REQUIREMENTS'" ±V" Supply Voltage Supply Current: +1" +Icc -Icc -Icc Power DisSipation TEMPERATURE RANGE Specification Operating Storage ±4.75 +Vcc = +5V +Vcc =+12V -Vee = -5V -V" =-12V ±V" =±5V ±Vcc =±12V 0 -{l0 -60 ±5 +10 +12 -25 -27 175 475 ±13.2 +17 -{l5 2S0 +70 +70 +100 V mA mA mA mA mW mW 'c 'C 'c NOTES: (1) Binary Two's Complement coding. (2) Ratio of (Distortion,MS + Nolse'MS)/Signal,MS' (3) D/A converter output frequency/signal level. (4) D/A converter sample frequency (4 x 44.1kHz; 4 times oversampling). (5) Bipolar zero. using A·weighted filter. (S) This is the combined drift error due to gain, offset. and linearity over temperature. (7) All positive and all negative supply pins must be tied together respectively. 6.2-36 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (liSA Only) MECHANICAL P Package - 16-Pfn Plastic DIP I' 'I ,{ ::~: ::hi A Pin 1 DIM A AI B BI C D F G H J K L M N P PIN ASSIGNMENTS -v. 2 3 4 5 6 7 B 9 10 11 12 13 14 15 16 LOG COM +VL NC CLK LE DATA -VL VQUT RF SJ ANA COM IQUT MSBADJ TRIM +V. INCHES MIN MAX .740 .800 .725 .785 .230 .290 .200 .250 .120 .200 .015 .023 .030 .070 .100 BASIC 0.20 .050 .015 .008 .070 .150 .300 BASIC 0' IS' .010 .030 .025 .050 MlWMETERS MIN MAX 18.80 20.32 18.42 19.94 5.85 7.38 5.09 6.36 3.05 5.09 0.38 0.59 0.76 1.78 2.54 BASIC 0.51 1.27 0.20 0.38 1.78 3.82 7.63 BASIC 0' IS' 0.25 0.76 0.64 1.27 NOTE: Leads In true position within 0.01· (0.25mm) R at MMC at seaUng plano. ... CONNECTION DIAGRAM Analog NegaUve Supply Laglc Common Laglc PasiUva Supply No Connection Clock Input Latch Enable Input Serial Data Input Laglc NegaUve Supply Voltage Qu1put Feedback Resistance Summing JuncUon Analog Common Current Qulput MSB Adjustment Tennlnal MSB Trim·pot Tennlnal Analog Positive Supply CD == () A- Io ABSOLUTE MAXIMUM RATINGS DC Supply Voltages ......................................................................±16VDC Input Laglc Voltage ..............................................................-lV to V.I+VL Power Dissipation .......................................................................... 850mW Operating Temperature Range ......................................... -25"C to +70'C Storage Temperature Range .......................................... -eO'C to +t 00"C Lead Temperature (soldering. 10 seconds) .................................. +3oo'C () ~ a NOTE: (1) MSB error (Bipolar Zero differential linearity error) can be adjusted to zero using the extamal cin:ult shown In figure 4. . a fa TABLE I. PCM61P Input/Output Relationships. DIGITAL INPUT A- U» o ANALOG OUTPUT Binary Two's Complement (BTC) DAC Qulput VoitageM VQUTMode Current (mA) IQUT Mode lFFFF Hex 00000 Hex 3FFFF Hex 20000 Hex +FS BPZ BPZ-1LSB -FS -0.99999237 0.00000000 +0.00000763 +1.00000000 +2.9999nll 0.00000000 -0.00002289 -3.00000000 !iu -z ::) == == o() oa ::) Burr·Brown Ie Data Book Supplement, Vol. 33b 6.2-37 c For Immediate Assistance, Conlact Your Local Salesperson Pf6 (Clock) lJU1JLfl p18(Data)~ Pf7 (Latch Enable) lL--LL___.,-___ _ _ _ _ _ _---J/ L NOTES: (1) If clock is stopped between Input of f8·blt data words,latch enable (LE) must remain low until after the first clock of the next 18·bltdata word stream. (2) Data format is binary two's complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Letch enable (LE) must remain low at least one clock cycle after going negatlv9. (4) Latch enable (LE) must be high for at least one clock cycle before going negative. FIGURE 2. PCM6lP Timing Diagram. MSB ERROR ADJUSTMENT PROCEDURE (OPTIONAL) :"->25ns ...-.: X'--_M_SB_---'> Clock, Input: : :....... >25n8 ~~ ....... >25ns ~1 />5ns To statically adjust DLE at BPZ, refer to the circuit shown in Figure 4 or the PCM61P connection diagram. :_>60ns _ _ /' . ~........ _ _"'-;-_ _ _ _ _ _, . :....>15ns~ Letch ,: \: : E~.:1 /: :_> One Clock Cycie _ : _ > One Ciock Cycle _ : : : . FIGURE 3. PCM6lP Setup and Hold Timing Diagram. MAXIMUM CLOCK RATE The maximum clock rate of 16.9MHz for the PCM61P is derived by mUltiplying the standard audio sample rate of 44.lkHZ times sixteen (l6X oversampling) times the standard audio word bit length of 24 (44.lkHz x 16 x 24 = l6.9MHz). Note that this clock rate accommodates a 24-bit word length, even though only 18 bits are actually being used. 470kll The MSB error ofthe PCM61P can be adjusted to make the differential linearity error (DLE) at BPZ essentially zero. This is important when the signal output levels are very low, because zero crossing noise (DLE at BPZ) becomes very significant when compared to the small code changes occurring in the LSB portion of the converter. 100kll 200kll ,Trim15~1-Vs MSBAdjUst14~ , Differential linearity error at bipolar zero and THD are guaranteed to meet data sheet ,specifications without any external adjustment. However, a provision has been made for an optional adjustment of the MSB linearity point, which makes it possible to eliminate DLE error at BPZ. Two procedures are given to allow either static or dynamic adjustment. The ,dynamic procedure is preferred because of the difficulty associated with the static method (accurately measuring 16bit LSB steps). After allowing ample warm-up time (5-10 minutes) to assure stable operation of the PCM6IP, select input code 3FFFF hexadecimal (all bits on except the MSB). Measure the output voltage using a 6-1/2 digit voltmeter and record it. Change the digital input code to 00000 hexadecimal (all bits off except the MSB). Adjust the 100kQ potentiometer to make the output read 22.9JlV more than the voltage reading of the previous code (a ILSB step = 22.9JlV). A much simpler method is to dynamically adjust the DLE at BPZ. Assuming the device has been installed in a digital audio application circuit, send the appropriate digital input to produce a -6OdB level sinusoidal output, then adjust the 100kQ potentiometer until a minimum level of distortion is observed. FIGURE 4. MSB Adjust Circuit. 6.2-38 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) BURR-BROWN® PCM63P 11::11::11 Colinear ™ 20-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • COL/NEAR 20·BIT AUDIO DAC • NEAR·IDEAL LOW LEVEL OPERATION The PCM63P is a precision 20-bit digital-to-analog converter with ultra-low distortion (-96dB max with a full scale output; PCM63P-K). Incorporated into the PCM63P is a unique Colineardual-DAC per channel architecture that eliminates unwanted glitches and other nonlinearities around bipolar zero. The PCM63P also features a very low noise (1l6dB max SNR; Aweighted method) and fast settling current output (200ns typ, 2mA step) which is capable of 16-times oversampling rates. • GLlTCH·FREE OUTPUT • ULTRA LOW -96dB max THD + N (Without External Adjustment) • 116dB SNR min (A·Weight Method) • INDUSTRY STD SERIAL INPUT FORMAT • FAST (200ns) CURRENT OUTPUT (±2mA; ±2% max) Applications include very low distortion frequency synthesis and high-end consumer and professional digital audio applications. • CAPABLE OF 16x OVERSAMPLING • COMPLETE WITH REFERENCE +5V AAalog +5V Digital -5V Analog -5V Digital Upper 82 Adj Lower 82 Adj io PCM63P Col/near 20·8it DAC () ~ a Clock Latch Enable Input Shift Register and Control Logic A- U) a Data }-+-----f 6 >-_,flfll'-l 5 4 io lOUT Bipolar Offset Current Offset Decouple !i()- -:::»z :IE :IE Reference Decouple Servo Decouple Collnearn'. Burr-Brown Corp. International Airport Indusklal Park ' Mailing Address: PO Bo.114OO Tel: (602)746-11t1 ' Twx: 910-952·1111 ' Cable: BBRCORP , Potenliometer Voltage Analog Common Digital Common Tucson, AZ 85734 ' Street Address: 6730 S. TucsOn Blvd. • Tucson, AZ 85706 Telex: 065-6491 ' FAX: (602) 889·1510 ' knrnedlate Product Info: (800)548-6132 PDS·1083 Burr·Brown Ie Data Book Supplement, Vol. 33b 6.2-39 o() . o -a ~ For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL All specifications at 25'C and ±VA and ±V. = ±5V. unless otherwise noted. PCM63P, PCM63P-J, PCM63P-K PARAMETER CONDITIONS MIN RESOLUTION 20 DYNAMIC RANGE. THO + N at -aOdB Referred to Full Scale PCM63P PCM63p·J PCM63p·K 96 100 104 DIGITAL INPUT Logic Family Logic Level: V~ VIL +2 0 V'H = +2.7V VOL = +O.4V I'H III Data Format Input Clock Frequency TOTAL HARMONIC DISTQRTlON + N"'. Without Adjustments PCM63P fs = 352.BkHzI4) f = 991 Hz (OdB)'" f = 991 Hz (-2OdB) f. = 352.8kHz f = 991 Hz (-aOdB) Is = 352.8kHz PCM63p·J I = 991 Hz (OdB) Is = 352.8kHz I = 991 Hz (-20dB) Is = 352.8kHz I = 991Hz (-SOdB) Is = 352.8kHz PCM63p·K I = 991 Hz (OdB) I. = 352.8kHz I = 991 Hz (-20dB) Is = 352.8kHz f = 991 Hz (-aOdB) Is = 352.8kHz ACCURACY Level Linearity Gain Error BIpolar Zero at -~OdB Signal Level ErrorS) Gain Drift Bipolar Zero Drift Warm·up Time IDLE CHANNEL SNRto, O'C to 70'C O'C to 70'C MAX 20Hz to 20kHz at BPZl7, dB dB dB 100 104 108 r~1 ±1.96 2mA Step V V +V. 0.8 +1 -SO Serial. MSB First. BTCt" 30 IlA IlA 25 MHz -92 -80 -40 -88 -74 -36 dB dB dB -96 -82 -92 -76 -44 -40 dB dB dB -100 -88 -48 -96 -82 -44 dB dB dB ±D.3 ±1 ±10 25 ±1 ±2 dB % mV ppml'C ppm 01 FSRI'C Minute 4 +116 UNITS Bits 1 POWER SUPPLY REJECTION ANALOG OUTPUT Output Range Output Impedance Internal RFEEDBACK Settling Time Glitch Energy TYP +120 dB +86 dB ±2.00 670 1.5 200 No Glitch Amund Zero ±2.04 rnA ±5 10 -35 225 ±5.50 15 -45 300 V rnA rnA mW +70 +85 +100 'C 'C 'C n kn ns POWER SUPPLY REQUIREMENTS tVA' ±V. Supply Voltage Range +IA• +1. Combined Supply Current -I,. -I. Combined Supply Current Power Dissipation TEMPERATURE RANGE Specification Operating Storage ±4.SO +VA' +Vo = +5V -V,. -V. =-SV tV,. ±V. = ±5V 0 -40 -a0 NOTES: (1) Binary Two's Complement coding. (2) Ratio 01 (Distortion"",. + NoiseRMS) I Signal.... (3) D/A converter output lrequency (signal level). (4) D/A converter sample frequency (8 x 44.1 kHz; 8x oversampling). (5) Offset error at bipolar zem. (6) Measured using an OPA27 and 1.5kn feedback and an A-welghted filter. (7) Bipolar Zero, 6.2-40 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) MECHANICAL P Package - 28-Pln Plastic DIP --------0---------1 DIM A'" -j AI'II o E, o B B, C 0'" E Ell') e, e, PIN ASSIGNMENTS INCHES MIN MAX .169 .200 .015 .070 .015 .020 .015 .055 .008 .012 1.380 1.455 .600 .625 .485 .550 .100 BASIC .600 BASIC MILLIMETERS MIN MAX 4.29 5.08 0.38 1.78 0.38 0.51 0.38 1.40 0.20 0.30 35.05 36.96 15.24 15.88 12.32 13.97 2.54 BASIC 15.24 BASIC DIM L 12 a 0, 5, INCHES MIN MAX .10(1 .200 MILLIMETERS MIN MAX 2.54 5.06 .000 .030 0.00 0.76 0° .020 .040 W .070 .080 0° 0.51 15° 1.76 2.03 1.02 (1) Not JEDEC Standard NOTE: Leads in lrue position within 0.01" (0.2Smm) Rat MMC at seating plane. Pin numbers shawn for reference only. Numbers may not be marked on package. ABSOLUTE MAXIMUM RATINGS PtN DESCRIPTION PI P2 P3 P4 PS P6 P7 PB P9 Pl0 Pll P12 P13 P14 PIS P16 P17 PIB P19 P20 P21 P22 P23 P24 P2S P26 P27 P26 Servo Amp Decoupling Capacitor +SV Analog Supply Voltage Relerence Decoupling Capacilor Oflset Decoupling Capacitor Bipolar Offset Current Output (+2mA) DAC Current Output (0 to -4mA) Analog Common Connection No Connection Feedback Resistor Connection (I.SkO) Feedback Resistor Connection (I.Skn) -SV Digital Supply Voltage Digital Common Connection .5V Digital Voltage Supply No Connection No Connection MNEMONIC CAP +VA CAP CAP BPO lOUT ACOM NC RF, RF, -Vo DCOM +Vo NC NC No Connection NC No Connection NC DAC Data Clock Input CLK No Connection NC DAC Data Latch Enable LE DAC Data Input DATA No Connection NC Optional Upper DAC Bit-2 Adjust (-4.29Vt UB2 Adj Optional Lower DAC Bit-2 Adjust (-4.29Vt LB2 Adj Bit Adjust Relerenee Voltage Tap Hl.52V)· VPOT No Connection NC No Connection NC -SV Analog Supply Voltage -VA ·Nominal voltages at these nodes assuming ±V.; ±Vo = ±5V. +V,. +Vo to ACOM/DCOM ......................................................... ov to +BV -VA' -Vo to ACOM/DCOM ......................................................... OV to-8V -v,. -Yo to +V•• +Vo .............................................................. OV to +16V ACOM to DCOM ...............................................................................±O.SV Digital Inputs (pins lB. 20. 21) to DCOM ................................ -IV to +Vo Power Dissipation .......................................................................... SOOmW Lead Temperature. (soldering. lOs) .............................................. +300°C Max Junction Temperature .............................................................. 165°C Thermal Resistance. 6". ............................................................... 70°CIW NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. 8 !I a I,,; z o -tc -u:::»z ORDERING INFORMATION MODEL PACKAGE TEMPERAlURE RANGE MAXTHD+N, ATOdB PCM63P PCM63P-J PCM63P-K Plastic DIP Plastic DIP Plastic DIP O°C to +70°C O°C to +70°C O°C to +70°C -86dB -92dB -96dB Ii :IE :IE o u. o a :::» c - Burr-Brown Ie Data Book Supplement, Vol. 33b 6.2-41 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES All specifications at 25'C and ±V. and ±Vo = ±5.0V. unless othelWise noted. 16·BIT LEVEL LINEARITY (Dithered Fade to Noise) THO + N vs FREQUENCY -40 8 -60 I rtl tfBr -60 ,I a;- a;- 6 :E. 4 ! ...J :E. z+ , 0 :z: ~ E \. -100 ,B 100 -2 c ~ ·s -4 " 0 I -120 20 0 ,g -20dB I- 1k -& -8 -120 10k " -70 -80 -90 16·BIT MONOTONICITY -SOdB SIGNAL SPECTRUM (100Hz Bandwidth) -60 -80 -100. :E. 0.5 ~ D> J!! ;g N. .5 -100 OUlput Signal Level (dB) a;- :> -110 OUlput Frequency (Hz) 1.5 .s "'~, 2 iii 1- 0 120 ~ -0.5 11. -140 -1 -1.5 8.83msldiv 4k 8k 12k 16k 20k 1600 2000 Frequency (Hz) -90dB SIGNAL (10Hz to 20kHz Bandwidth) -11OdB SIGNAL (10Hz to 20kHz Bandwidth) 40 :> 20 a ! i 0 -20 400 Time (~s) 6.2-42 800 1200 Time (~s) Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) THEORY OF OPERATION DUAL-DAC COL/NEAR ARCHITECTURE Digital audio systems have traditionally used laser-trimmed, current-source DACs in order to achieve sufficient accuracy. However even the best of these suffer from potential lowlevel nonlinearity due to errors at the major carry bipolar zero transition. More recently, DACs employing a different architecture which utilizes noise shaping techniques and very high oversampling frequencies, have been introduced ("Bitstream", "MASH", or I-bit DACs). These DACs overcome the low level linearity problem, but only at the expense of signal-to-noise performance. and often to the detriment of channel separation and intermodulation distortion if the succeeding circuitry is not carefully designed. The PCM63 is a new solution to the problem. It combines all the advantages of a conventional DAC (excellent full scale performance, high signal-to-noise ratio and ease of use) with superior low-level performance. Two DACs are combined in a complementary arrangement to produce an extremely linear output. The two DACs share a common reference and a common R-2R ladder to ensure perfect tracking under all conditions. By interleaving the individual bits of each DAC and employing precise laser trimming of resistors. the highly accurate match required between DACs is achieved. This new, complementary linear or dual-DAC Co/inear approach. which steps away from zero with small steps in both directions, avoids any glitching or "large" linearity errors and provides an absolute current output. The low level performance of the PCM63P is such that real 20-bit resolution can be realized, especially around the critical bipolar zero point. Table I shows the conversion made by the internal logic of the PCM63P from binary two's complement (BTC). Also. the resulting internal codes to the upper and lower DACs (see front page block diagram) are listed. Notice that only the LSB portions of either internal DAC are changing around bipolar zero. This accounts for the superlative performance of the PCM63P in this area of operation. DISCUSSION OF SPECIFICATIONS DYNAMIC SPECIFICATIONS Total Harmonic Distortion + Noise The key specification for the PCM63P is total harmonic distortion plus noise (THD + N). Digital data words are read into the PCM63P at eight times the standard compact disk audio sampling frequency of 44. 1kHz (352.8kHz) so that a sine wave output of 991Hz is realized. For production testing, the output of the DAC goes to an I to V converter, then to a programmable gain amplifier to provide gain at lower si"nal output test levels, and then through a 40kHz low passefilter before being fed into an analog type distortion analyzer. Figure 1 shows a block diagram of the production THD + N test setup. For the audio bandwidth. THD + N of the PCM63P is essentially flat for all frequencies. The typical performance curve, "THD + N vs Frequency", shows four different output signal levels: OdB, -20dB. -40dB, and -60dB. The test signals are derived from a special compact test disk (the CBS CD-I). It is interesting to note that the -2OdB signal falls only about lOdB below the full scale signal instead of the expected 20dB. This is primarily due to the superior lowlevel signal performance of the dual-OAC Colinear architecture of the PCM63P. '" CD J! U a. In terms of signal measurement, THD + N is the ratio of DistortionRMs + Noise RMs / SignalRMs expressed in dB. Fo: the • • • • PCM63P, THD + N is 100% tested at al.1 t~ee speclfie.d.=W", output levels using the test setup shown In FIgure I. It IS _ _ _ significant to note that this test setup does not include any output deglitching circuitry. All specifications are achieved without the use of external deglitchers. 111. Dynamic Range Dynamic range in audio converters is specified as the measure of THO + N at an effective output signal level of -6OdB referred to OdB. Resolution is commonly used as a theoretical measure of dynamic range, but it does not take into account the effects of distortion and noise at low signal levels. The ,,; ANALOG OUTPUT INPUT CODE (20-blt Binary Two's Complement) LOWER DAC CODE (19·blt Straight Binary) UPPER DAC CODE (19-blt Straight Binary) +Full Scale +Full Scale - 1LSB Bipolar Zero + 2LSB Bipolar Zero + 1LSB Bipolar Zero Bipolar Zero - 1LSB Bipolar Zero - 2LSB -Full Scale + 1LSB Full Scale 011...111 011...110 000•.. 010 000... 001 000...000 111 •.. 111 111 ... 110 100... 001 100.•.000 111...111 + lLSB' 111...111 + lLSB' 111...111 + lLSB' 111...111 + lLSB' 111 .•. 111 + lLSB' 111... 111 111 ... 110 000 ..• 001 000 ... 000 111...111 111 ... 110 000 .. .010 000•.. 001 000 ... 000 000 ... 000 000 ... 000 000.•. 000 000... 000 tiu- Z :::t J! J! 'The extra weight of 1LSB is added at this point to make the transfer function symmetrical around bipolar zero. TABLE I. Binary Two's Complement to Colinear Conversion Chart. Burr-Brown Ie Data Book Supplement, Vol, 33b Z o o u. o a ~ - 6.2-43 For Immediate Assistance, Contact Your Local Salesperson Use 400Hz High-Pass Filter and 30kHz Low-Pass Filter Meter Settings Low-Pass Filter 40kHz 3rd Order GICType Programmable Gain Amp OdB to 60dB Distortion Analyzer (Shiba Soku Model 725 or Equivalent) Binary Counter t - Digital Code (EPROM) Parallel-to-Serial Conversion .J 1 11 TIming Logic :-- OUT (PCM63P) Clock Latch Etle ItoV Converter OPA627 i Sampling Rate =44.1 kHz x 8 (352.8kHz) Output Frequency = 991 Hz FIGURE I. Production THD + N Test Setup. Colinear architecture of the PCM63P, with its ideal perfonnance around bipolar zero, provides a more usable dynamic range, even using the strict audio definition, than any previously available D/A converter. the code for bipolar zero while the output of the DAC is band-limited from 20Hz to 20kHz and an A-weighted filter is applied. The idle channel SNR for the PCM63P is typically greater than l20dB, making it ideal for low-noise applications. Level Linearity Deviation from ideal versus actual signal level is sometimes called "level linearity" in digital audio converter testing. See the "-9OdB Signal Spectrum" plot in the Typical Performance Curves section for the power spectrum of a PCM63P at a -9OdB output level. (The "-9OdB Signal" plot shows the actual -90dB output of the DAC). The deviation from ideal for PCM63P at this signal level is typically less than ±O.3dB. For the "-llOdB Signal" plot in the Typical Perfonnance Curves section, true 20-bit digital code is used to generate a -IIOdB output signal. This type of performance is possible only with the low-noise, near-theoretical perfonnance around bipolar zero of the PCM63P's Co/inear DAC circuitry. A commonly tested digital audio parameter is the amount of deviation from ideal of a 1kHz signal when its amplitude is decreased from -6OdB to -120dB. A digitally dithered input signal is applied to reach effective output levels of -12OdB using only the available l6-bit code from a special compact disk test input. See the "16-Bit Level Linearity" plot in the Typical Performance Curves section for the results of a PCM63P tested using this l6-bit dithered fade-to-noise signal. Note the very small deviation from ideal as the signal goes from -60dB to -IOOdB. DC SPECIFICATIONS Idle Channel SNR Another appropriate specification for a digital audio converter is idle channel signal-to-noise ratio (idle channel SNR). This is the ratio of the noise on the DAC output at bipolar zero in relation to the full scale range of the DAC. To make this measurement, the digital input is continuously fed 6.2-44 Monotonicity Because of the unique dual-DAC Co/inear architecture of the PCM63P, increasing values of digital input will always result in increasing values of DAC output as the signal moves away from bipolar zero in one-LSB steps (in either direction). The "16-Bit Monotonicity" plot in the Typical Perfonnance Curves section was generated using 16-bit digital code from a test compact disk. The test starts with 10 periods of bipolar zero. Next are 10 periods of alternating lLSBs above and below zero, and then 10 periods of alternating 2LSBs above and below zero, and so on until lOLSBs above and below zero are reached. The signal pattern then begins again at bipolar zero. With PCM63P, the low-noise steps are clearly defined and increase in near-perfect proportion. This perfonnance is achieved without any external adjustments. By contrast, sigma-delta C"Bitstream", "MASH", or I-bit DAC) architectures are too noisy to even see the first 3 or 4 bits change Cat 16 bits), other than by a change in the noise level. Absolute Linearity Even though absolute integral and differential linearity specs are not given for the PCM63P. the extremely low THD + N perfonnance is typically indicative of 16-bit to 17-bit integrallinearity in the DAC. depending on the grade specified. The relationship between THO + N and linearity. however. is not such that an absolute linearity specification for every individual output code can be guaranteed. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) Offset, Gain, And Temperature Drift Although the PCM63P is primarily meant for use in dynamic applications, specifications are also given for more traditional DC parameters such as gain error, bipolar zero offset error, and temperature gain and offset drift. sixteen times (16x oversampling) the standard audio word bit length of 24 bits (44.1kHz X 16 X 24 = 16.9MHz). Note that this clock rate accommodates a 24-bit word length, even though only 20 bits are actually being used. The maximum clock rate of 25MHz is guaranteed, but is not 100% final tested. The setup and hold timing relationships are shown in Figure 3. DIGITAL INPUT Timing Considerations The PCM63P accepts TTL compatible logic input levels. Noise immunity is enhanced by the use of differential current mode logic input architectures on all input signal lines. The data format of the PCM63P is binary two's complement (BTC) with the most significant bit (MSB) being first in the serial input bit stream. Table II describes the exact relationship of input data to voltage output coding. Any number of bits can precede the 20 bits to be loaded, since only the last 20 will be transferred to the parallel DAC register after LE (P20, Latch Enable) has gone low. All DAC serial input data (P21, DATA) bit transfers are triggered on positive clock (P18, CLK) edges. The serial-toparallel data transfer to the DAC occurs on the falling edge of Latch Enable (P20, LE). The change in the output of the DAC coincides with the falling edge of Latch Enable (P20, LE). Refer to Figure 2 for graphical relationships of these signals. "Stopped Clock" Operation The PCM63P is normally operated with a continuous clock input signal. If the clock is to be stopped between input data words, the last 20 bits shifted in are not actually shifted from the serial register to the latched parallel DAC register until Latch Enable (LE, P20) goes low. Latch Enable must remain low until after the first clock cycle of the next data word to insure proper DAC operation. In any case, the setup and hold times for Data and LE must be observed as shown in Figure 3. Data Input Clock Input Latch - - J Enable Maximum Clock Rate A typical clock rate of 16.9MHz for the PCM63P is derived by mUltiplying the standard audio sample rate of 44.1kHz by ~ >One Clock Cycl FIGURE 3. Setup and Hold Timing Diagram. DIGITAL INPUT ANALOG OUTPUT CURRENT OUTPUT VOLTAGE OUTPUT (With External Op Amp) 1,048,576LSBs ILSB 7FFFFHEX OOOOOHEX Full Scale Range NA +Full Scale Bipolar Zero Bipolar Zero - I LSB -Full Scale 4.00000000mA 3.81469727nA -1.99999619mA O.OOOOOOOOmA +0.00000381 rnA +2.00000000mA 6.00000000V 5.72204590IlV +2.9999942SV O.OOOOOOOOV -o.OOOO0572V -3.00000000V FFFFFHEX 80000 HEX u ~ a TABLE II. Digital Input/Output Relationships. PIS (Clock) P21(Data) MSB P20 (Latch Enable) P6(lourl Do B ur z lJ1JlJ1Jl JlJ1flJUlflJUUl ~ io o -ti u -z ~ LSB lL_L!____ _ _ _ _ _1 L >-<== ------>< :) NOTES: (I) If cloCk is stopped between Input of 20·bit data words, Latch Enable (LE) must remain low until after the first clock cyde of the next 20-bit data word stream. (2) Data format is binary two's complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge, (3) Latc~ Enable (LE) must remain low at least ana clock cycle after going negative. (4) Latch Enable (LE) must be high for at least one clock cycle bafore going negative. (5) lOUT changes on negative gOing edge of Latch Enable (LE). o u. o -a FIGURE 2. Timing Diagram. Burr-Brown Ie Data Book Supplement. Vol. 33b I! I! 6.2-45 ~ For Immediate Assistance, Contact Your Local Salesperson INSTALLATION desired. Use of the MSB adjustments will only affect larger dynamic signals (between OdB and -6dB). This improvement comes from bettering the gain match between the upper and lower DACs at these signal levels. The change is realized by small adjustments in the bit-2 weights of each DAC. Great care should be taken, however, as improper adjustment will easily result in degraded performance. In theory, the adjustments would seem very simple to perform, but in practice they are actually quite complex. The first step in the theoretical procedure would involve making each bit-2 weight ideal in relation to its code minus one value (adjusting· each potentiometer for zero differential nonlinearity error at the bit-2 major carries). This would be the starting point of each lOOill potentiometer for the next adjustment. Then, each potentiometer would be adjusted equally, in opposite directions; to achieve the lowest fullscale THD + N possible (reversing the direction of rotation POWER SUPPLIES Refer to Figure 4 for proper connection of the PCM63P in the voltage-out mode using the internal feedback resistor. The feedback resistor connections (P9 and PIO) should be left open if not used. The PCM63P only requires a ±5V supply. Both positive supplies should be tied together at a single point. Similarly, both negative supplies should be connected together. No real advantage is gained by using separate analog and digital supplies. It is more important that both these supplies be as "clean" as possible to reduce coupling of supply noise to the output. Power supply decoupiing capacitors should be used at each supply pin to maximize power supply rejection, as shown in Figure 4, regardless of how good the supplies are. Both commons should be connected to an analog ground plane as close to the PCM63P as possible. FILTER CAPACITOR REQUIREMENTS As shown in Figure 4, various size decoupling capacitors can be used, with no special tolerances being required. The size of the offset decoupling capacitor is not critical either, with larger values (up to lOO~F) giving slightly better SNR readings. All capacitors should be as close to the appropriate pins of the PCM63P as possible to reduce noise pickup from surrounding circuitry. -VA 28 f--------------, 24 f - - - -.....--.J\IV'--' LB2 Adj MSB ADJUSTMENT CIRCUITRY Near optimum performance can be maintained at all signal levels without using the optional MSB adjust circuitry of the PCM63P shown in Figure 5. Adjustability is provided for those cases where slightly better full-scale THD + N is FIGURE 5. Optional Bit-2 Adjustment Circuitry. PCM63P I~F O.I~F -SV CAP -VA +5V +VA NC 28 ~ NC O.I~F Vpor BPO ±3V q LB2Adj UB2Adj O.I~F NC -:- DATA LE 14 RF, NC -Vo CLK DCOM NC +Vo NC NC NC 15 FIGURE 4. Connection Diagram. 6,2-46 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) for both if 110 immediate improvement were noted). This procedure would require the generation of the digital bit-2 major carry code to the input of the PCM63P and a DVM or oscilloscope capable of reading the output voltage for a one LSB step (5.72I!V) in addition to a distortion analyzer. A morc practical approach would be to forego the minor correction for the bit-2 major carry adjustment and only adjust for upper and lower DAC gain matching. The problem is that just by connecting the MSB circuitry to the PCM63P. the odds are that the upper and lower bit-2 weights would be greatly changed from their unadjusted states and thereby adversely affect the desired gain adjustment. Just centering the IOOkQ potentiometers would not necessarily provide the correct starting point. To guarantee that each lOOkQ potentiometer would be set to the correct starting or null point (no current into or out of the MSB adjust pins), the voltage drop across each corresponding 330kQ resistor would have to measure OV. A voltage drop of ±1.25mV across either 330kQ resistor would correspond to a ±ILSB change in the null point from its unadjusted state (ILSB in current or 3.81nA x 330kQ = 1.26mV). Once these starting points for each potentiometer had been set, each potentiometer would then be adjusted equally, in opposite directions, to achieve the lowest full-scale THD + N possible. If no immediate improvement were noted, the direction of rotation for both potentiometers would be reversed. One direction of potentiometer counter-rotations would only make the gain mismatch and resulting THD + N worse, while the opposite would gradually improve and then worsen the THD + N after passing through a no mismatch point. The determina- tion of the correct starting direction would be arbitrary. This procedure still requires a good DVM in addition to a distortion analyzer. Each user will have to determine if a small improvement in full-scale THD + N for their application is worth the expense of performing a proper MSB adjustment. APPLICATIONS The most common application for the PCM63P is in highperformance and professional digital audio playback, such as in CD and DAT players. The circuit in Figure 6 shows the PCM63P in a typical combination with a digital interface format receiver chip (Yamaha YM3623), an 8x interpolating digital filter (Burr-Brown DF1700P), and two third-order low-pass anti-imaging filters (implemented using Burr-Brown OPA2604APs). Using an 8x digital filter increases the number of samples to the DAC by a factor 'of 8, thereby reducing the need for a higher order reconstruction or anti-imaging analog filter on the DAC output. An analog filter can now be constructed using a simple phase-linear OlC (generalized immittance converter) architecture. Excellent sonic performance is achieved using a digital filter in the design, while reducing overall circuit complexity at the same time. Because of its superior low-level performance, the PCM63P is also ideally suited for other high-performance applications such as direct digital synthesis (DDS). I0 • u ~ a A- U) a .. U) z -=: -uz 0 ~ :IE :IE u0. -a 0 Burr-Brown Ie Data Book Supplement. Vol.33b 6.2-47 -c~ 0- N .i:.. 00 :!l 0 c: .SV ::0 .SV m ?' en 4.1~F 4.1~F lb ill 0 .SV ;l> tf+ 11.1"" <= ~ a "~ tf+ Digital Interface Format Receiver Interleaved Digital ~ Input o· \l ~ 4.1~F O.1~F e: 0 ;l> "0 "0 .SV 9A~D BGO 12 2 llR 15 281 ... ~ -:~ 5i" a =.iii' BGO 26 -=: WCK 25 DOL 24 DA 11 CD ::to. Burr-Brown Yamaha YM3623 1OpF~ Vour Right . ex Interpolation 28 ? ±3V I 10PF~ 100pF DF1700P r;;' 114141R 11t i;' l:I ~ !D ~ ttl l:I l::: ~ ~ to ti ~ Q ttl ~ t'-l {j ";;j "';:s ~ :- ~ ~ ~ ;;:: .... :: E Q tOATA ~ 18 ClK 20 lE ~ -=~ CD Burr-Brown PCM63P ~ :- Vom Left i;' 5; () ~ ±3V - A 1. A 2 • A 3.A4= Burr-Brown OPA2604AP, or equivalent. = Or, Call Customer Service at 1-800-548-6132 (USA Only) ANALOG-TO-DIGITAL CONVERTERS The Burr-Brown Analog-ta-Digital (AID) converter product line offers a broad selection of devices that enable you to choose the perfonnance and price range ideally suited for your application. For example, the highperfonnance 12-bit ADC80, which converts to 12-bit accuracy in 25J.ls, was originated by Burr-Brown in 1975 and has become an industry standard. The recently introduced ADC603 is a 12-bit, lOMHz AID converter that offers the industry's highest perfonnance for RF signal processing applications. A high-resolution converter, the ADC76, converts 16 bits to ±O.003% absolute accuracy in only 15J.ls and is packaged in a 32-pin triple-wide dualin-line package. Another perfonnance category is total harmonic distortion for audio digital recording. All devices are complete and fully specified, with a track record of high reliability proven both in the field as well as in internal qualification testing. Burr-Brown Ie Data Book Supplement, Vol. 33b 9 9-1 For Immediate Assistance, Contact Your Local Salesperson ANALOG·TO·DIGITAL CONVERTERS SELECTION GUIDES The Selection Guide shows parameters forthe high grade. Refer to the Product Data Sheet for a full selection of grades. Models shown in boldface are new products introduced since publication of the previous Burr-Brown IC Data Book. Boldface = NEW INSTRUMENTATION ANALOG·To.DIGITAL CONVERTERS Description Modal Conversion TIme or / Sampling NMC Resolution Linearity Input Rate Reso(Bits) Error (%FSR) Range (V)I'I (j1s) lullon Temp RangalZl Pkg(31 Q, B,41 Page Screen No. 9.1-72 Data-Bus Inlerface ADC700 16 ±O.oo3 5,10,20UIB 17 14 MlI,lnd,Com TDIP Industry Sid Pinouts ADC71 ADC76 16 16 ±O.oo3 ±O.oo3 5; 10,20U/B 5,10,20U/B 50 17 14 14 Ind,Com Ind,Com TDIP TDIP Sampling 574 Type ADS574 12 ±O.012 10,20, U/B 40kHz 12 Ind Sampling 774 Type ADS774 12 ±O.O12 10,20, U/B 100kHz 12 Sampling, Interface ADS7800 12 ±O.012 10,20B 333kHz High-Accuracy, ADS7802 4-Channel, AutoCalibration, Sampling 12 ±O.012 010+5 Industry Sid Pinout and Interface ADC574A ADC674A ADC774 12 12 12 ±O.012 ±0.012 ±O.012 10,20UlB 10,20UlB 10,20U/B Sampling Sampling ADS807 ADS808 12 12 ±O.012 ±O.012 10,2OU/B 100kHz 10,20 U/B 100kHz Medium Speed Monolithic ADC80AG ADC80MAH 12 12 ±O.012 ±O.012 5,10,20UlB 5.10,20UlB Medium Speed ADC84KG ADC85H 12 12 ±O.012 ±O.012 Mil Temperature Range ADC87H 12 Serial Output ADC804 12 - S9.1-4 S9.1·12 DIP,DDIP SO - S9.1-42 Ind DIP,DDIP SO - S9.1-42 12 Com,lnd DIP SO - S9.1-72 8.5 12 Ind DDIP,PLCC 25 15 12 12 12 MiI,lnd,Com MiI,lnd,Com MiI,lnd,Com DDIP DDIP DDIP BI BI BI 12 12 MlI,lnd,Com Mll,lnd,Com DDIP DDIP BI S9.1-59 BI S9.1-59 25 25 12 12 Ind Ind TDIP TDIP BI BI 9.1-20 9.1-36 5,10,20U/B 5,10,20U/B 10 10 12 12 Ind Com TDIP TDIP BI 9.1-44 ±0.012 S,10,20U/B 10 12 Mil TDIP ±O.O12 5,10,20U/B 17 12 MiI,lnd,Com DDIP 8 -S9.1-153 9.1-52 9.1-62 9.1-32 Q, BI 9.1-44 Q 9.1-44 Q, BI 9.1-78 NOTES: (1) U/B Indicates the input voltage range for the model: U .. unipolar, B co Bipolar. (2) Com .. O·C to +70·C, Ind .. -2S·C to +85·C, Mil .. -5S·C to +12S·C. (3) DIP .. 0.3" wide DIP, DDIP .. 0.6" wide DIP, TDIP .. 0.9" wide DIP, PLCC .. Plastic Leaded Chip Carrier, SO co Small Outline Surface Mount. (4) Q indicates optional reliability screening Is available for this model. BI indicates that an optional 160 hour bum-in is available for this model. 9-2 Burr-Brown IC Dala Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) Boldface = NEW AUDIO, COMMUNICAnONS, DSP ANALOG-TO-DIGITAL CONVERTERS Description Resolution Model (Bits) Linearity Error, max(%FSR) Conversion Time Input or Sampling Range Rate THD (V) (dB, typ) fils) Temp Range(1) Qt,) Page No. Pkgl2) Screen ADC701 High Accuracy, High Resolution 16 ±O.003 10V/20V 1.5 94w/SHC702 Com TDIP Sampling, ADC614 High-Resolution ADC603 14 ±O.OO3 ±1.25 5MHz 76 Com DIP 59.2-134 12 ±O.018 ±1.25 10MHz 68 Com,MII DIP S9.2-99 High Spurious-Free Range ADC604 12 ±O.024 ±1.25 5MHz 83 Com DIP S9.2-119 ADC803 ADC601 12 12 ±O.012 ±O.012 10V/20V 10V/20V 1.5 1.0 NA 7OW/SHC802 Ind,MiI Com TDIP TDIP 9.2-124 S9_2-83 ADS&02 12 ±O.03 10V/20V 1MHz 66 Com TDIP S9.1-51 Sampling Typlcel Linearity Error nmeor Input Sampling THD+N Range Rate dB,max (V) (V.. =±FS) (1lS) - 59.2-137 ... CJ -= a CI Description Model Resolution (Bits) High Performance PCM75 16 15-Bit 14-Bit ±2.5,±5 ±10V 17 -84(J) -88 (K) Parallel or Serial TDIP 9.2-136 Low Cost PCM78 16 14-Blt ±3 5 -88 Serial DDIP S9.2-165 Dual PCM1750 18 14-Blt ±2.75 5 -90 (P) Serial DDIP S9.2-187 Single Channel DSP10l 18 14-Blt ±2.75 5 -90 Serial DDIP Sl4-4 Dual Channel DSP102 18 14-Blt ±2.75 5 -90 Serial DDIP Output Format Pkg(1) Page No.le) NOTES: (1) DIP = 0.3" wide DIP, DDIP R 0.6" wide DIP, TDIP = 0.9" wide DIP, PLCC a Plastic Leaded Chip Carrier, SO a Outline Surface Mount. Burr-Brown Ie Data Book Supplement, Vol. 33b I!UI Ii:UI I0 9-3 0• I• CI ... 0 C Z C For Immediate Assistance, Contact Your Local Salesperson ADC71 NEW HERMETIC PACKAGE!· 16-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION • 16-BIT RESOLUTION • ±0.0030/0 MAXIMUM NONLINEARITY • COMPACT DESIGN: 32-pln Hermetic Ceramic Package The ADC71 is a low cost, high quality, 16-bit successive approximation analog-to-digital converter. It uses laser-trimmed ICs and is packaged in a convenient 32pin hermetic ceramic dual-in-line package. The converter is complete with internal reference, clock, comparator, and thin-film scaling resistors, which allow selection of analog input ranges of ±2.5V, ±5V, ±IOV, 0 to +5V, 0 to +lOV and 0 to +20V. • CONVERSION SPEED: 5011S max • LOW COST Data is available in parallel and serial form with corresponding clock and status output. All digital inputs and outputs are TIL-compatible. Power supply voltages are ±15VDC and +5VDC. Reference 1----<> Parallel Digital Output Ref oui (+6.3V) } Input Range ' - - - - - 0 0 Select 1-------......--------0 Comparator In 1 - - - - - - - - - - - - - - 0 Clock OUt '---------------------0 Status International Airport industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (602) 746-1111 • Twx: 911).952'1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (602) 889-1510 • Immediate Product Info: (800) 548-6132 PDS·I060 9.1-4 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL At +25'C and rated power supplies unless otherwise noted. ADC71A, B ADC71J, K MIN MODEL TYP ......n"mn.. MAX 1"fP MIN 16 INPUlS ANALOG Vollage Ranges: Bipolar Unipolar logic Loading POWER SUPPLY :t15VDC +5VDC ±a.1 ±a.05 ±a.1 V V 10 50ns wide (r ~In) trailing .q~ I ±a.2 ±a.l ±a.2 TTLLoed ±a.l ±a.2 ±a.l ±a.2 ±a.OO3 ±a.008 ±a.OO3 ±a.006 ±112 ~ rl· to'O" Ini!ales .convel1llo~) ±a.1 ±a.05 :t112 ±a.003 ±a.003 IIU leO leO leO 5 DIGrrAL'" TRANSFER CHARAC'TERISlICS ACCURACY Gain Erro~" 0IIse~": Unipolar Bipolar Unearlty Error: K. B J. A Inherent Quantization Error Differential Unearlty Error Bits 2.5 2.5 5 10 (:onvert Comml nd Positive UNITS 16 1±2.5~ :15. :t10 O:to +5. 0 to +1C o to +20 ±2.5. :15. :t10 to +5. 0 to +lp. o to +20 Input Impedance (Dlrec1 Input) o to +5V. ±2.5V o to +IOV. :I5.0V o to +20V. :tl0V MAX 0 % %oIFSRI'I %oIFSR %oIFSR %oIFSR LSB %oIFSR sENsmvrrv 0.003 0.001 CONVERSION TIME'" 14 Bits WARM-UP TIME 50 5 DRIFT Gain :t10 ±2 :t6 ±2 OIIset Unipolar Bipolar Unearlty No Missing Codes Temp Range J. A (13·Bits) K. B (I4-Blts) 0 0 %O~~~=~: 0.003 0.001 :t5 :t3 +70 +70 JIS -25 -25 INTERNAL REFERENCE VOLTAGE Max Extemal Current with No Degradation 0' Specs Temp Coalfielent POWER SUPPLY REQUIREMENlS Power Consumption Rated VollagB. Analog Rated Vollage. Digital Supply Drain + 15VDC Supply Drain -15VDC SuPPly Drain +5VDC TEMPERATURE RANGE Specification ~or;~ng (Deraled Specs) a C Z -...~ 0 Z ppmI'C ppm 01 FSRI'C ±2 :t10 ±2 ppm 0' FSRI'C +85 'C +85 'C ppm 01 FSRI'C :E =a: I;; Z OUTPUT DIGITAL DATA (All Codes Complemenlary) Parallel OUlput Codes"': Unipolar Bipolar Oulpul Drive Serial Data Code (NAZ) Oulput Drive Slatus Status OuIpUt Drive Clock OuIpUt Drive FrequencY<" Co» IU min · :t15 :t4 :tl0 %01 50 · I CSB COB. CTC.' 2 mLoads · CSB.COB Logic 6.0 2 During Con lerslon 2 2 280 6.3 6.6 2 8.0 · 8.3 ±200 :tl0 :t11.4 +4.75 655 :t15 +5 +10 -28 +17 0 -25 -55 :t18 +4.75 +15 ·· -35 +20 +70 +85 +125 -25 -55 -55 655 ·· ··· mLoads 2 mLoads mLoads kHz 6.8 V ±200 PP~C ·· · mW VDC VOC () mA mA mA +85 +125 +125 'C 'C 'C NOTES: (1) CMOSITTL compatible. I.e.. logIC "0· a 0.8V. max Logic "I· = 2.0V. min lor Inputs. 'or digital outpUts logic "0" = +o.4V. max logIC "I· • 2.4V mIn. (2) Adjustable to zero. (3) FSR means Full Scale Range. 'or example. un~ connected 'or :tl0V range has 20V FSR. (4) Conversion time may be shortened with ·Short Cycle" sellor lower resolution. see "Additional Connec1ions Required" section. (5) See Table I. CSB· Complementary Siraight Binary. COB • Complementary Offset Binary. CTC • Complementary Two's Complement. (6) CTC coding obtained by Inverting MSB (Pin 1). Burr-Brown Ie Data Book Supplement, Vol. 33b ...r- 9.1-5 a C For Immediate Assistance, Contact Your Local Salesperson MECHANICAL G Package - 32-Pln Hermetic DIP 1----- A -----'1 32 17 -1 DIM A B C 0 F B G ~~ls_1 H J K L N INCHES MIN MAX MILLIMETERS MIN MAX 1.580 1.620 40.13 41.15 .880 .900 22.35 22.86 .138 .186 3.51 4.72 .016 .020 0.41 0.51 .040TYP 1.02TYP .100 BASIC 2.54 BASIC .056 1.12 1.42 .044 .009 .012 023 0.30 .165 .185 4.19 4.70 .900 .920 22.86 23.37 .040 .060 1.02 1.52 NOTE: Leads in true position within 0.01" (0.25mm) A al MMC al sealing plane. Pin numbers shown for reference only. Numbers may nol be marked on package . ~-J 1_._ _ ABSOLUTE MAXIMUM SPECIFICATIONS +V" 10 Common ...................•.....•...•...•...•.....•.....•....•......•••...•. 010 +IS.5V -V" 10 Common ....•....••.....••..............•......•.......•.•..•..•.•..•...... OV 10 -IS.5V +V" to Common ................•.......••..•..........•..••.....•.•••••.......•.••...•. OV 10 +7V Analog Common 10 Digllal Common ..••......•..................•..............•... ±0.5V Logic Inputs 10 Common •..........••.•..•.....•...•...........••.................... OV 10 V" Maximum Power Dissipation ....................................................... 1000mW Lead Temperalure (1 Os) ..................................................................300'C L ----I ORDERING INFORMATION MODEL TEMP RANGE NONLINEARITY ADC71JG ADC71KG ADC71AG ADC71BG O'C 10 +70'C O'C to +70'C -25'C 10 +B5'C -25'C 10 +B5'C ±O.OOS% FSR ±O.OO3%·FSR ±O.OOS% FSR ±O.OO30/. FSR PIN CONFIGURATION (MSB)BilI Convert Command Bil3 +5VDC Supply Bil4 Gain Adjusl BitS +15VDC Supply BilS Comparalor In Bil7 Bipolar OIIsel BilB IOV Bil9 20V BillO Rei 0u1S.3V Billl Analog Common Bil12 -15VDC Supply (LSB lor 13 bijs) Bil13 (LSBlor 14bi1S) Bil14 9.1-6 ShortCycJe Bit 2 ClockOul Digital Common BillS Sialus BillS SerialOul Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Cuslomer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES GAIN DRIFT ERROR ("to OF FSR) vs TEMPERATURE POWER SUPPLY REJECTION vs SUPPLY RIPPLE FREQUENCY +0.10 i +O.OS 1? >"' +0.06 ~ +0.04 '5 ~ +0.02 5 0.04 ."'" c .c 0.02 ~ 0.01 g €0 -0.04 'm -0.06 ,ij -o.OS u. (!) -0.10 -25'C -15VDC 'V / U w -0.02 c 0.1 0.06 l;; 0.006 c. ~ O'C +25'C +70'C +S5'C 15VDC~ 0.OQ4 ffi 0.002 ~ 0.001 .10 Temperature ('C) 100 lk Frequency (Hz) +5V~7 10k lOOk I E I Co) ~ DISCUSSION OF PERFORMANCE The accuracy of a successive approximation AID converter is described by the transfer function shown in Figure 1. All successive approximation AID converters have an inherent Quantization Error of ±1/2 LSB. The remaining errors in the AID converter are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling networks, power supply rejection, and reference errors. In summary, these errors consist ofil)itial errors including Gain, Offset, Linearity, Differential Linearity, and Power Supply Sensitivity. Initial Gain and Offset errors may be adjusted to zero. Gain drift over temperature rotates the line (Figure I) about the zero or minus full scale point (all bits Off) and Offset drift shifts the line left or right over the operating temperature range. Linearity error is unadjustable and is the most meaningful indicaior of AID converter accuracy. Linearity error is the deviation of an actual bit transition from the ideal transition value at any ~ ~:; o~ :iii g 0000 ... 0001 TIMING CONSIDERATIONS Offset 1000 ... 0001 Error, 1111 ... 1110 1111 ... 1111 Table I shows the LSB, transition values, and code definitions for each possible analog input signal range for 12-, 13and 14-bit resolutions. Figure 5 shows the connections for 14-bit resolution, parallel data output, with ±1OV input. e.NOff 'See Table I for Digital Code Definitions. FIGURE 1. Input vs Output for an Ideal Bipolar Converter. AID Burr-Brown Ie Data Book Supplement, Vol. 33b ... Z III I: i i and'" Two binary codes are available on the ADC7l parallel output; they are complementary (logic "0" is true) straight binary (CSB) for unipolar input signal ranges and complementary offset binary (COB) for bipolar input signal ranges. Complementary two's complement (CTC) may be obtained by inverting MSB (Pin 1). I----...;..~,..__,--l 1000 ... 0000 _ ~ The timing diagram (Figure 2) assumes an analog input such that the positive true digital word 1001 1000 IDOl 0110 exists. The output will be complementary as shown in Figure 2 (0110 011101101001 is the digital output). Figures 3 4 are timing diagrams showing the relationship of serial data ~ to clock and valid data to status. PARALLEL DATA 0111 ... 1 1 0 I h 0111 ... 1110 0111. .. 1111 The ADC7l is monotonic, assuring that the output digital code either increases or remains the same for increasing analog input signals. Burr-Brown guarantees that these converters will have no missing codes over a specified temperature range when short-cycled for 14-bit operation. DEFINITION OF DIGITAL CODES 0000 .•• 0000 :... level over the range of the AID converter. A Differential Linearity error of ±1/2 LSB means that the width of each bit step overthe range of the AID converteris I LSB, ±1/2 LSB. 0Z 9.1-7 For Immediate Assistance, Contact Your Local Salesperson Conven Command!') Inlemal Clock Status (EOC) "0" MBS Bil2 BI13 Btt4 Bil5 Bil6 Bil7 Bil8 Bil9 Bill0 Bitll Bil12 Bil13 Bil14 BII15 Bil16 Serial Data OUI '1" -'1"---------------------------------------------===] ~=~="~:;------------------~------------------------~r--===] r__ ===] L..J ==]r----------------.~r,,-l'-'-----------------------------===] L.j"1" ===] I ===]1 L-j"1" ·r----,L--Jr J _________ i- I~" "1" '0" ---- ~r,,-l"------------------- :::]1 ===] ===]..==] === In/nl M~BI J 1"0" L.J"1"· _________________________________ "0" ~I='o='~~----~r-- r__ I~" 2 '1" 3 I 4 "0" "1" 5 6 "0' "1" 7 I "1" 8 UJ '1" "0" 10 I 11 "1" "1" lJil13l ~' "1' ~"'" ~ 14 "0" "0" "1" NOTES: (1) The conven command musl be alleasl50ns wide and musl remain low during a conversion, The conversion is inltiated by the "trailing edge" of Ihe conven command. (2) 57J1S for 16 bits. FIGURE 2, ADC71 Timing Diagram, Seria,_ Oul • ~ I ~,------- "-----.LL___~~~__ , Bil16 '-4O·125n$ I Clock Oul Binary (BIN) Outpul Defined As: Designation Trans"ion Values MSB LSB 000 ... 000(4) 011 •.. 111 111 ... 110 , FIGURE 4. Timing Relationship of Valid Data to Status. INPUT VOLTAGE RANGE AND LSB VALUES Code One Leasl Significanl Bil(LSB) 4O-125ns~ Status FIGURE 3. Timing Relationship of Serial Daia to Clock. Analog Inpul Voltage Range I~ I,- FSR ""F n n n =12 = 13 =14 +Full Scale Mid Scale -Full Scale ±10V ±5V ±2.5V to +10V 010 +5V 010 +20V COBI" orCTC"' COB'" orCTC" COB'" orCTC!2J eS8(31" eS8(3) CSB'" .§Y.... 10\1 5V 1.22mV 61Ol1V 30511V 20V 2' 4.BSmV 2.44mV 1.22mV +5V--"lI2LSB +2.5V o +II2LSB +20V--3I2LSB +10V o +1/2LSB 10V 20V 2' 4.88mV 2.44mV 1.22mV 2.44mV 1.22mV 610l1V 2' 1.22mV 610l1V 30511V +10V--3I2LSB 0 -10V +lI2LSB +5V--312LSB 0 ...JfjV +lI2LSB +2.5V--3I2LSB 0 -2.5V +II2LSB "F o F 2.44mV 1,22mV 610l1V . + 10V--312LSB +5V o +1/2LSB 2T NOTES: (1) COB =Complementary OHsel Binary. (2) Complementary TWo's Complemenl~ned by inverting the mosl significanl bil MSB (pin 1). (3) CSB =Complementary Straighl Binary. (4) Voltages given are Ihe nominal value for transition 10 the code specified. TABLE L Input Voltages, Transition Values, LSB Values, and Code Definitions. 9.1-8 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) MSB r;'-''2 r------~---~~ :J. Dotted Unes Are External ~ Connections F- Offset Convert Command From Adjust Control logic §ot--...,11--::27::o::-kU=----....::...----~---------~, +5VDC ~91----+--"VI/I.r---'1 2e/-------:--:::-:-::---t--~t---_t--__.--__.---,-~ ~ I Gain I.SMU r--~f---"'V\tv-,l 1--'2€ 7 := ADC71 ~9 ~ ~ Bipolar ~ Offset ~ NC Adjust +15VDC I+ ::;:: I~F IOkUto IOOkU ~------t----+---.~ :~~~: ~ ~~ 2.4/-----------1----t----t----t---~ ±IOV ~ --·I~:~------------------+------r----+---~~~ ~f_-------------+--.......- - +....... -r_I!...~F_t-, -15VDC I I I ~ _J NC I E F-::" ~ ~ O.Q1~P ~f_-+-I---< ,.§.. ~ D I ~ I~F Igf E 8 S z o !; l __ ~I-------------~-----__, ~f_-----~ Slaws Qulput to ~ ~ ~~------------~~ NC ~ Digital CommonV Control Logic Analog -::- Common 'Capacltor should be connected even If external gain adlust IS not used. FIGURE 5. ADC71 Connections for: ±IOY Analog Input, 14-Bit Resolution (Short-Cycled), Parallel Data Output. SERIAL DATA Two straight binary (complementary) codes are available on the serial output line: CSB and COB. The serial data is available only during conversion and appears with MSB occurring first. The serial data is synchronous with the internal clock as shown in the timing diagrams of Figures 2 and 3. The LSB and transition values shown in Table I also apply to the serial data output except for the CTC code. +15VDC (a) I.SMU ' Z 7 1 - - - - - ' \ M - - - - - ; ; IOkU to IOOkO Offset Adjust Comparator In Iiiz +15VDC The ADC71 is specified to provide critical performance criteria for a wide variety of applications. The most critical specifications for an AID converter are linearity, drift, gain and offset errors. This ADC is factory-trimmed and tested for all critical key specifications. ISOkn 'Z7't-M'lr-T-'\M----.......; IOkU to IOOkU Offset Adjust Comparator In 22kn FIGURE 6. Two Methods of Connecting Optional Offset Adjust with a 0.4% of FSR of Adjustment. Gain Adjust 270kn 29j---1r--'\M----.......; lT O.OI~F ~ IOkO to IOOkU Gain Adjust -15VDC POWER SUPPLY SENSITIVITY Burr-Brown Ie Data Book Supplement. Vol. 33b ....,.. () +15VDC 22 Changes in the DC power supplies will affect accuracy. The power supply sensitivity is specified for ±D.OO3% of FSR! %dYs for±15Y supplies and ±O.OOI % of FSR/%dg for +5 supplies. Normally; regulated power supplies with 1% or less ripple are recommended for use with this ADC. See Layout Precautions, Power Supply Decoupling and Figure 8. - -15VDC GAIN AND OFFSET ERROR Initial Gain and Offset errors are factory-trimmed to typically ±D. I % ofFSR (typically ±O.05% for unipolar offset) at 25°C. These errors may be' trimmed to zero by connecting external trim potentiometers as shown in Figures 6 and 7. III i (b) DISCUSSION OF SPECIFICATIONS ...Z :E -15VDC ISOkn IIII Ii: Analog Common FIGURE 7. Connecting Optional Gain Adjust with a 0.2% Range of Adjustment. 9.1-9 a c For Immediate Assistance, Contact Your Local Salesperson . ~ +5VDC Digital I I ~ I~F I~FI + .. -15VDC Analog Common Camp In 22 I~Fl [ill ~ Common ... +15VDC FIGURE 8. Recommended Power Supply Decoupling. LAYOUT AND OPERATING INSTRUCTIONS LAYOUT PRECAUTIONS Analog and digital common are not connected internally in the ADC7l but should be connected together as close to the unit as possible, preferably to a large plane under the ADC. If these grounds must be run separately, use wide conductor patterns and a 0.0 1J.IF to 0.1J.IF non-polarized bypass capacitor between analog and digital commons at the unit. Low impedance analog and digital commons returns are essential for low noise performance. Coupling between analog inputs and digital lines should be minimized by careful layout. The comparator input (Pin 27) is extremely sensitive to noise. Any connection to this point should be as short as possible and shielded by Analog Common patterns. POWER SUPPLY DECOUPLING The power supplies should be bypassed with tantalum capacitors as shown in Figure 8 to obtain noise free operation. These capacitors should be located close to the ADC. INPUT SCALING The analog input should be scaled as close to the maximum input signal range as possible in order to utilize the mal\imum signal resolution of the AID converter. Connect the input signal as shown in Table II. See Figure 9 for circuit details. Input Signal Range Output Code ±10V ±5V ±2.5V Oto +5V a to +10V a to +20V COBorCTC· COB orCTC· COBorCTC· CSB CSB CSB Connect Pin 26 To Pin Connect Pin 24 To 27 27 27 Input Signal Open Pin 27 Pin 27 Open Input Signal 22 22 22 ·Obtained by inverting MSB pin 1. TABLE II. ADC7l Input Scaling Connections. 9.1-10 Connect Input Signal To Pin 24 25 25 25 25 24 ~ .,,- ~V+ B~~~ REF Offset FIGURE 9. ADC71 Input Scaling Circuit. OPTIONAL EXTERNAL GAIN AND OFFSET ADJUSTMENTS Gain and Offset errors may be trimmed to zero using external gain and offset trim potentiometers connected to the ADC as shown in Figure 6 and 7. Multiturn potentiometers with l00ppmf'C or better TCRs are recommended for minimum drift over temperature and time. These pots may be any value from 10k!) to lOOk!). All resistors should be 20% carbon or better. Pin 29 (Gain Adjust) and Pin 27 (Offset Adjust) may be left open of no external adjustment is required. ADJUSTMENT PROCEDURE OFFSET - Connect the Offset potentiometer (make sure R\ is as close to pin 27 as possible) as shown in Figure 6. Sweep the input through the end point transition voltage that should cause an outputtransition to all bits Off ~ 0.06 .5 0.04 0.1 '" ~ 0.02 1 ~8. 1111!1111111111111~lili5iV~Dclll ~.04 0.006 0.01 l; 0.004 .li ~.08 II: ~ ~.12 -25 +85 +25 'l;f1Y11f ' 11111111'" 11111111 0.001 10 100 lk 10k lOOk Frequency (Hz) Temperature ('C) THEORY OF OPERATION The accuracy of a successive approximation AID converter is described by the transfer function shown in Figure 1. All successive approximation AID converters have an inherent quantization error of ±1/2LSB. Theremaining errors in the AID converter are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling networks, power supply rejection, and reference errors. In summary, these errors consist of initial errors including Gain, Offset, Linearity, Differential Linearity, and Power Supply Sensitivity. Initial Gain and Offset errors may be adjusted to zero. Gain drift over temperature rotates the line (Figure I) about the zero or minus full scale point (all bits Off) and Offset drift shifts the line left or right over the operating temperature range. Linearity error is unadjustable and is the most meaningful indicator of AID converter accuracy. Linearity error is the deviation of an actual bit transition from the ideal transition value at any level over the range of the AID converter. A differential linearity error of ±1/2LSB means that the width of each bit step over the range of the AID converter is lLSB, ±1/2LSB. 0000 ... 0000 • I ~~ 0000 ... 0001 0011 ... 1100 0011 ... 1110 0111 ... 1111 k c------'J?I"-\::---,l!H--I os 1000 ... 0000 Offset 'iii 1000 ... 0001 Error", ~ I The ADC76 is also monotonic, assuring that the output digital code either increases or remains the same for increasing analog input signals. Burr-Brown also guarantees that this converter will have no missing codes over a specified temperature range when short cycled for 14-bit operation AIIB'tsOff '--'~-il .,.Off T - Analog Input .,.On l I +FSRI2-1 LSB 'See Table I for Digital Code Definitions. FIGURE I. Input vs Output for an Ideal Bipolar AID Convener. Burr-Brown Ie Data Book Supplement. Vol.33b i 8 S z - o Iii... Z TIMING CONSIDERATIONS III IE The timing diagram in Figure 2 assumes an analog input such that the positive true digital word 1001 1000 1001 0110 exists. The output will be complementary as shown in Figure 2 (0110 0111 0110 1001 is the digital output). Figures 3 and 4 are timing diagrams showing the relationship of serial data to clock, and valid data to status. DIGITAL CODES Parallel Data _ Two binary codes are available on the ADC76 parallel output: they are complementary (logic "0" is true) straight binary (CSB) for unipolar input signal ranges, and complementary offset binary (COB) for bipolar input signal ranges, Complementary two's complement (eTC) may be obtained by inverting the MSB (pin 1). Table I shows the LSB, transition values, and code definitions for each possible analog input signal range for 12-, 13and 14-bit resolutions. Figure 5 shows the connections for 14-bit resolution, parallel data output, with ±lOV input. I 1111 ... 1 1 1 0 " 1111 ... 1111 I I I E !.'!!!', lJ.J.l-I!jf 0002 ff! . I Serial Data Two straight binary (complementary} codes are available on the serial output line: CSB and COB. The serial data is available only during conversion and appears with MSB occurring first. The serial data is synchronous with the internal clock as shown in the timing diagrams of Figures 2 and 3. The LSB and transition values shown in Table I also apply to the serial data output except for the eTC code. 9.1-15 i I;; -z • For Immediate Assistance, Contact Your Local Salesperson Maximum Throughpul TIme!'} _ _ _ _ _ _ _ _ _ _ _ _..., Convert Command!1} Internal Clock Slalus (EOC) "0" MBS Bil2 Bil3 Bil4 Bil5 Bil6 Bil7 BilS Bil9 Bill0 Billl 8it12 Bil13 Bil14 Bil15 Bil16 Serial Data Oul "1" =:J·~----~L__J~"-1·-·--------------------------------------------- ~~~~J .~ !'O" ___-1·r:==:J~"0~"~----------------------~r- r- :::J :::J :::J :::J :::J :::J :::J :::J :::] :::J ::::IntH M~BI L-J "1" r-----------------~L__J~"-1·-·-------------------------------- "0" U"l" I "0" L__J'1" r L--J '-l'-------------------1"0" U"l" rr- 1"0" 1'0" 2 I '1" 3 I 4 "1" ·0" 6 "1" "0" 7 8 '1" "1" 10 I W ~:"'T'"~11~Lill131 14 '1" ·0" "0" "1" '0" "1' b+-=m._ '0" "1" NOTES: (1) The convert command musl be alleasl50ns wide and musl remain low during a conversion. The conversion is inilialed by Ihe "trailing edge' of Ihe convert command. (2) 171'S for 16 bils. FIGURE 2. ADC76 Timing Diagram. ,, Serial Oul ~Ii 1.- 40 125"S }-____________________ J Bil16 + Clock Oul FIGURE 3. Timing Relationship of Serial Data to Clock. BINARY (BIN) OUTPUT Analog Inpul Voltage Range , FIGURE 4. Timing Relationship of Valid Data to Status. INPUT VOLTAGE RANGE AND LSB VALUES Defined As: Code Designation One Leasl Significanl BII(LSB) _ 4O-125ns ---jl~.i,_ Status FSR o to +IOV o to +5V o to +20V orCTC(21 eSB(3) CSB'~ CSB'" 5V 10V 5V ±lilV ±5V ±2.5V COB'" orCTC'· COB!!! COB'" or CTC'. 20V 10V F 20V To 2' 2' 2' 2' 2' n = 12 n = 14 4.88mV 2.44mV 1.22mV 2.44mV 1.22mV 610llV 1.22mV 610liV 305(1V 2.44mV 1.22mV 610llV 1.22mV 610llV 30511V 4.SSmV 2.44mV 1.22mV +Full Scale Mid Scale -Full Scale +10V-312LSB 0 -10V +lI2LSB +5V-312LSB 0 -5V +lI2LSB +2.5V-3I2LSB 0 -2.5V +lI2LSB +10V-312LSB +5V o +lI2LSB +5V-3I2LSB +2.5V o +lI2LSB +20V-312LSB +10V o +lI2LSB n'C: 13 Transition Values MSB LSB 000 ... 000'" 011 ... 111 111 ... 110 NOTES: (1) COB = Complementary Offsel Binary. (2) Complementary Two's Complemenl-obtalned by inverting the moS! significant bil MSB (pin 1). (3) CSB = Complemenlary Stralghl Binary. (4) Voltages given are Ihe nominal value for transllion to the code specified. TABLE I. Input Voltages, Transition Values, LSB Values, and Code Definitions. 9.1-16 Burr~Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) 2kll MSB F.1: r---------- ~ ~ ~ ~ ~ ~ ~9 ~ ~ ~ DottedUnes Are Extemar Connections r-1_ADC76 Ta ~ r-- II I Il __ ~-NC ~ ~ 13- ~ ~ IV ~ G .,- O.o1~P Convert Command From I 1 Control logic +5VDC 270kn ~ I 1.SMn Bipolar Offset ~ I 10knto lOOkn GaIn Adjust i ~l~F Offset Adjust 'ftkl~F 10knlO lOOkn Iw Ii: Anarog Input ±10V Anar og l~F + "T'" ~ ; l~F _ Common / " 19 Io -15VDC Digital fa ~ +15VDC ~Cammon Status OUiput 10 SerialOut . Control logic u ~ Capacitor should be !Xlnnected even II extemal gain adjust Is not used• FIGURE 5. ADC76 Connections for: ±lOV Analog Input, 14-Bit Resolution (Shon-Cycled), Parallel Data Output. z o -tc DISCUSSION OF SPECIFICATIONS The ADC76 is specified to meet critical performance criteria for a wide variety of applications. The most critical specifications for an AID convener are linearity, drift. gain and offset errors. and conversion speed effects on accuracy. This ADC is factory-trimmed and tested for all critical key specifications. GAIN AND OFFSET ERROR Initial Gain and Offset errors are factory-trimmed to typically ±o.1 % of FSR (±o.05% for unipolar offset) at 25°C. These errors may be trimmed to zero by connecting external trim potentiometers as shown in Figures 10 and II. POWER SUPPLY SENSITIVITY .... z DIFFERENTIAL LINEARITY ERROR Differential linearity describes the step size between transition values. A differential linearity errorof±o.OO3% ofFSR indicates that the size of any step may not vary from the ideal step size by more than 0.003% of Full Scale Range. LINEARITY ERROR Burr-Brown Ie Data Book Supplement, Vol.33b i Inz - ACCURACY VERSUS SPEED In successive approximation AID converters, the conversion speed affects linearity and differential linearity errors. Conversion speed and its effect on linearity and differential ~ linearity errors for the ADC76 are shown in Figure 6. ~ 0.01 r---,---,---,..---,..---, Changes in the DC power supply voltages will affect accuracy. The ADC76 power supply sensitivity is specified at ±o.OO3% of FSR/%Vs for the ±15V supplies and ±o.OOI5% of FSR/%Vs for the +5V supply. Normally. regulated power supplies with I % or less ripple are recommended for use with this ADC. See Layout Precautions, Power Supply Decoupling. and Figure 7. Linearity error is not adjustable and is the most meaningful indicator of AI D convener accuracy. Linearity is the deviation of an actual bit transition from the ideal transition value at any level over the range of the AID convener. w IJ CD ..... u a c 0.001 '--_ _.1..-_ _.1..-_ _.1..-_ _.1..-_--' 10 11 12 13 14 15 Conversion 11me (~) FIGURE 6. Linearity Versus Conversion Time. 9.1-17 For Immediate Assistance, Contact Your Local Salesperson LAYOUT AND OPERATING INSTRUCTIONS LAYOUT PRECAUTIONS Analog and digital common are not connected internally in the ADC76, but should be connected together as close to the unit as possible, preferably to a large plane under the ADC. If these grounds must be run separately, use a wide conductor pattern and a O.OIIlF to O.IIlF nonpolarized bypass capacitor between analog and digital commons at the unit. Low impedance analog and digital common returns are essential for low noise performance. Coupling between analog inputs and digital lines should be minimized by careful layout. The comparator input (pin 27) is extremely sensitive to noise. Any connection to this point should be as short as possible and shielded by Analog Common or ±15VDC supply patterns. POWER SUPPLY DECOUPLING The power supplies should be bypassed with tantalum or electrolytic capacitors as shown in Figure 7 to obtain noise free operation. These capacitors should be located close to the ADC. ~ +5VDC ~ 1 I ~ Digital ~ ~ l~F ~ -:- ~V+ B~~ REF Offset FIGURE 8. ADC76 Input Scaling Circuit. OUTPUT DRIVE Normally all ADC76 logic outputs will drive two standard TTL loads; however, if long digital lines must be driven, external logic buffers are recommended. INPUT IMPEDANCE The input signal to the ADC76 should be low impedance, such as the output of an op amp, to avoid any errors due to the relatively low input impedance of the ADC76. If this impedance is not low, a buffer amplifier should be added between the input signal and the direct input to the ADC76 as shown in Figure 9. ,.. -15VDC I '"] Analog . Common l~Fl [ill ~ Common Comp In Analog Input Signal Conneetto Pin 24 or Pin 25 >-4--_ 10Ma • +15VDC To Star (Meeting POint) Ground FIGURE 7. Recommended Power Supply Decoupling. FIGURE 9. Source Impedance Buffering. INPUT SCALING OPTIONAL EXTERNAL GAIN AND OFFSET ADJUSTMENTS Gain and Offset errors rnay be trimmed to zero using external gain and offset trim potentiometers connected to the ADC as shown in Figures 10 and 11. Multiturn potentiometers with IOOppm/"C or better TCRs are recommended for minimum drift over temperature and time. These pots may be any value from lOill to l00ill. All resistors should be 20% carbon or better. Pin 29 (Gain Adjust) and pin 27 (Offset Adjust) may be left open if no external adjustment is required; however, pin 29 should always be bypassed with O.oIIlf to Analog Common. The analog input should be scaled as close to the maximum input signal range as possible in order to utilize the maximum signal resolution of the AID converter. Connect the input signal as shown in Table II. See Figure 8 for circuit details. INPUT SIGNAL RANGE OUTPUT CODE ±10V ±5V ±2.5V oto +5V o to +10V o to +20V COB orCTC' COB orCTC' COB orCTC' CSB CSB CSB ~Obtained CONNECT PIN 26 TO PIN CONNECT PIN 24 TO 27 27 27 22 Input Signal Open Pin 27 Pin 27 Open Input Signal 22 22 by inverting MSB pin 1. TABLE II. ADC76 Input Scaling Connections. 9.1-18 CONNEC INPUT SIGNAL TO PIN 24 25 25 25 25 24 ADJUSTMENT PROCEDURE Offset-Connect the Offset potentiometer (make sure R, is as close to pin 27 as possible) as shown in Figure 10. Sweep the input through the end point transition voltage that should cause an output transition to all bits off ~ Off), Figure 1. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) OPTIONAL CONVERSION TIME ADJUSTMENT +15VDC (a) 1.8Ma Zlf-----~M------> 10kntol00kn Offset Adjust Comparator In -15VDC +15VDC Rl 180kn 180kn Zlf-'VV'V-...,.---'\N\-----S 10kn to 100kn Offset Adjust Comparator In 22kn (b) -15VDC FIGURE 10. Two Methods of Connecting Optional Offset Adjust. +15VDC Gain Adjust The ADC76 may be operated with faster conversion times for resolutions less than 14 bits by connecting the Short Cycle (pin 32) as shown in Table III. Typical conversion times for the resolution and connections are indicated. 16 15 14 13 12 Connect Pin 32 to Resolution (Bits) Open Pin 16 Pin 15 Pin 14 Pin 13 Typical Conversion Time 17~ 16~ 15~ 13~ 12~ TABLE III. Short Cycle Connections for 12- to 16-Bit Resolutions. Clock Rate Control may be connected to an external multitum trim potentiometer with a TCR of±10ppm/"C or less as shown in Figure 12. The typical conversion time versus the Clock Rate Control voltage is shown in Figure 13. The effect of varying the conversion time and the resolution on Linearity Error and Differential Linearity Error is shown in Figure 6. 270kn : tMV ?' 10kn to l00kn Gain Adjust 231-----I~ 5kn -15VDC FIGURE 11. Connecting Optional Gain Adjust. Table 20 - "'a"E ;= 0 15 .~ " 0 0 r details the transition voltage levels required. 10 2 CONVERT COMMAND CONSIDERATIONS Convert command resets the converter whenever taken high. This insures a valid conversion on the first conversion after power-up. 4 Control Voltage on Pin 23 (V) FIGURE 13. Conversion Time vs Clock Rate Control Voltage. Convert command must stay low during a conversion unless it is desired to reset the converter during a conversion. Burr-Brown Ie Data Book Supplement. Vol. 33b •i IU Inz Typical " ~ ...Z FIGURE 12. Clock Rate Control, Optional Fine Adjust. Gain-Connect the Gain adjust potentiometer as shown in Figure 11. Sweep the input through the end point transition voltage; that should cause an output transition to all bits on E'N On. Adjust the Gain potentiometer until the actual end point transition voltage occurs at EIN On. E o u -~ Internal Clock Frequency Adjust Analog Common Adjust the Offset potentiometer until the actual end point transition voltage occurs at EIN Off. The ideal transition voltage values of the input are given in Table 1. ~ z o +15VDC Clock Rate Control 12 IU 9.1-19 For Immediate Assistance, Contact Your Local Salesperson BURR-BROWN@ ADC700 IE:lE:lI 16-Bit Resolution With Microprocessor Interface AID CONVERTER FEATURES The clock oscillator is current-controlled for excellent stability over temperature. Gain and Zero errors may be externally trimmed to zero. Analog input ranges of OVto +5V, OV to+lOV, OV to +20V,±2.5V,±5V, and ±lOV are available. • COMPLETE WITH REFERENCE, CLOCK, 8·BIT PORT MICROPROCESSOR . INTERFACE • CONVERSION TIME: 17J.1s max • LINEARITY ERROR: ±O.003% FSR max The conversion time is 17J.1S max for a 16-bit conversion over the three specification temperature ranges. • NO MISSING CODES TO 14 BITS OVER TEMPERATURE After a conversion, output data is stored in a latch separate from the successive approximation logic. This permits reading data during the next conversion, a feature that provides flexible interface timing, especially for interrupt-driven interfaces. • SPECIFIED AT ±12V AND ±15V SUPPLIES • OUTPUT BUFFER LATCH FOR IMPROVED INTERFACE TIMING FLEXIBILITY • PARALLEL AND SERIAL DATA OUTPUT • SMALL PACKAGE: 28·Pin DIP DESCRIPTION The ADC700 is a complete 16-bit resolution successive approximation analog-to-digital converter. The reference circuit, containing a buried zener, is laser-trimmed for minimum temperature coefficient. Data Ready Serial Data Status Strobe Data is available in two 8-bit bytes from'ITL-compatible three-state output drivers. Output data is coded in Straight Binary for unipolar input signals and Bipolar Offset Binary or Twos complement for bipolar input signals. BOB or BTC is selected by a logic function available on one of the pins. The ADC700 is. available in commercial, industrial and military temperature ranges. It is packaged in a hermetic 28-pin side-braze ceramic DIP. Serial Data Successive Approximation Register Parallel Data international Airport industrial Park • Mailing Address: PO Box 11400 • TUcson, AZ 85734 • Street Address: 6730 s. TUcson Blvd. • Tucson, AZ 85706 Tel: (602)746-1111 • Twx: 91IJ.952·1111 • cable:BBRCORP , Telex: 1166-6491 • FAX: (6D2) 889-151D • ImmedlateProducttnfo:(8DO)54UI32 PDS·856A 9.1·20 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL T, = 25'C and at rated supplies: V" = +5V, +Vee = +12Vor+15V, -Vee =-12Vor-15V unless otherwise noted, An,..,n" 'u" U'D" CHARACTERISTICS MIN TYP MAX Dcc>n, "T,n .. MIN TYP 1S ANALOG INPUTS Voltage Aanges Bipolar Unipolar Impedance (Direct Input) OV to +5V, ±2.5V OV to +10V, ±SV OV to +20V, ±10V Oto ±2,5, ±S, ±10 o to +10, 0 MAX UNITS · Bits ·· +20 V V · 2.5±10/0 5±1% 10±1% kn kn kn DIGITAL SIGNALS (Over Specilication ,empe~a1Ure Aange) Inputs Logic Levels/!) VH V" IH (V, _ +2.7V) I" (V, = +0.4V) Outputs Logic Levels VOL (I", = -1.SmA) V,," (I,," = +20pA) I Oa~ Outputs ~nly, High Z +2,0 0 V V +5.5 +0.8 ±10 ±20 +0.4 +2.4 pA pA · · 10 Gain Error:!) Zero Erro(3 ) Bipolar Zero Unipolar Zero Noise at Transitions (a"p-p) Power Supply Sensitivity ±C.l ±C.OOS ±0.012 ±C.2 ±C.l ±C.OS ±C.OOl ±C.2 ±C.l ±0.003 ±c.coa ±C.OOS ·· · ±C.C015 ±C.0015 ±C.OOOS +Vcc -Vee Voo ±8 ±1S ±5 ±2 ±1 ±10 ±4 ±a 0 -25 -55 I TIME 1S bits +70 +85 +12S 15 17 5 OUTPUT DATA CODES'" Unipolar Parallel Bipolar Parallel'" Serial Output (NAZ) +Vcc · Current!S} +Vcc -Vee Voo Power Oissipation TEMPERATURE RANGE Specification J, KGrades A, BGrades A, S Grades Storaoe = 0 U a C nA -. · +1S -1S +5.25 +10 -28 +17 645 +15 -35 +20 7S5 'Same specs as ADC700JH, AH, AH. Burr-Brown Ie Data Book Supplement. Vol. 33b 0/0 of FSA %ofFSR %ofFSR Z ppml"C ±2 +70 +85 +125 +150 Z III Ii ppm of FSAI"C ppm of FSAI"C ppm of FSAI"C a: I; Z 'C 'C 'C · JlS min · · · · ·· ~ ::;) ·· +15 -15 +5 0 -25 -55 -65 0/0 of FSA'" %ofFSA 0/0 %FSR/%Vcc %FSR/%Vcc %FSR/%VOD · USB BTC,BOB USB, BOB +11.4 -11.4 +4.75 · · POWER SUPPLY REQUIREMENTS Voltage Aange -Vee Voo IiIII 0 ACCURACY Unearity Error Differential Unearity Error WARM-UP TIME a: III V V 'n"...,,~cn CHAR".. , cn,,,, ,.." DRIFT (Over Specification Temperature Aange: Gain Drift Zero Drift Bipolar Zero Unipolar Zero Unearity Drift No Missing Codes Temperature Aange JH (1a·bit), KH (14-bit) AH (1a·bit), BH (14 bit) AH (13·bit), SH (14-bit) U) 0 ~ U a C · · · VDC VDC VDC rnA rnA rnA mW 'C 'C 'C 'C 9.1-21 For Immediate Assistance, Contact Your Local Salesperson TIMING SPECIFICATIONS'· V DD ;:: +5V. +Vcc = +12V or +1SV, -Vee = -12Vor-15V unless otherwise noted. LIMIT AT PARAMETER LIMIT AT T,,= 0, +70°C LIMIT AT T,,= 25°C -25'C. +85'C TA :: -55°C, +125°C UNITS ns, min ns, max ns, min ns, min lIS. max CS to WR Setup time WR to Status delay WR pulse width CS to WR Hold time 600 1150 210 360 0 0 145 40 0 17 650 1250 200 400 0 ns. max .Q!.ta Ready to Status time WR to first Serial Data Strobe First Serial Data to first Serial Data Strobe Last Serial Data Strobe to Status Status to WR Setup time 0 0 50 0 0 58 0 0 66 ns. min ns, min ns, max 70 81 95 ns, max 40 40 50 0 0 40 45 60 0 0 40 50 65 0 0 ns, min ns, max ns, max ns, min 60 70 70 81 80 95 DESCRIPTION CONVERSION AND SERIAL DATA OUTPUT nMING 0 110 40 0 15 550 1100 250 310 0 t, t, t, t, t, t, t, t, t, t" 0 130 40 0 17 Conversion time ns, max ns, min ns, max ns. min PARALLEL DATA OUTPUT TIMING t" t" t m " t" t" t,a,al t" t" !:!!!EN~ RD Setup time CS 10 RD Setup time High Byte Data Valid after Ri5 C, = 20pF (High Byte bus ~s time) High Byte Dala Valid after RD C, = 100pF (High Byte bus access time) AD pulse width Data Ready delay from RD (HBEN asserted) Data H~ time after RD (bus relinquish time) RD to CS Hold time RD to HBEN Hold time ns.mln RESETnMING t" t" ns. max Data Ready low delay from Reset Status low delay from Reset ns, max NOTES: (1) TTL. LSTTL. and 5V CMOS compatible. (2) FSR means Full Scale Range. For exemple. unltconnacted for±1 OV range has 20V FSR. (3) Externallyadjustable to zero. (4) See Table I. USB - Unipolar Straight Binary; BTC - Binary Twos Complement; BOB - Bipolar Offset Binary; NRZ - Non Return to Zero. (5) Max supply current is specified at rated supply voltages. (6) All input control signals are specified with t"•• = t,w. = 5ns (10% to 90% of SV) and timed from a voltage level of l.av. (7) t" Is measured with the load circuits of Figure 1 and defined as the time required for an oulput to cross 0.8V or 2.4V. (8) t" is defined as the time required for the data .lines to change 0.5V when loaded with the cirCUits of Figure 2. MECHANICAL H Package - 28-Pln Ceramic DIP 1-'-----A----_,! DIM A B C 0 F G H J K l N ~ TI INCHES MIN MAX 1.435 t.465 .610 BASIC .160 .205 .015 .019 .045 .055 .100 BASIC .055 .095 .009 .012 .125 .1SO .600 BASIC .040 .060 MIlliMETERS MIN MAX 36.45 37.21 15.49 BASIC 4.06 5.21 .38 .48 1.14 1.40 2.54 BASIC 1.40 2.41 .23 .30 4.57 3.18 15.24 BASIC 1.02 1.52 NOTE: Leads in true position within 0.01' (O.25mm) R at MMC at seating plane. Pin numbers shown for reference only. Numbers may not be marked on package . Chamfer~- Pin 1 Identifier L c: - I I - - - .-. C ~K Seating Plane 9.1-22 t D--II- G-- Burr-Brown Ie Data Book Supplement, Vol. 33b Or, CaU Customer Service al 1-800-548-6132 (USA Only) ORDERING INFORMATION MODEL TEMPERATURE RANGE LINEARITY ERlloR (%FSR) ADC700JH ADC700KH ADC700AH ADC700BH ADC700RH ADC700SH O'Cto 70'C O'C t070'C -25'C to +B5'C -25'C to +B5'C -55'C to + 125'C -55'C 10 + 125'C ±O.OOS ±0.OO3 ±O.OOS ±O.OO3 ±O.006 ±O.OO3 ABSOLUTE MAXIMUM RATINGS +VDO to Digital Common .............................................................. ov to +7V +Vee to Analog Common .......................................................... OV to +1 BV -Vee to Analog Common .•..•....•.••..••.••.••.••.•••.••.••.•••••••••••.••..•..•.• OVto-1BV Digital Common to Analog Common ........................................ -IV to +1V Digital Inputs to Digital Common .•..•.......•....••....•..••.•••• - h,'-- _______ _Serial Data ~ o !; ~ III :I i I; z - _______________ Start of Conversion and Serial Data Output Timing. o 2 () a c CS RD Parallel Data ----------1--41. Data Ready ADC700 Parallel Output Timing, Burr-Brown Ie Data Book Supplement, Vol.33b '/, For Immediate Assistance, Contact Your Local Salesperson PIN CONFIGURATION 5kll Comparator In Bipolar OIIset 5kll 1 20VAange 2 1---'lN\r--I 10VAange Gain Adjust Analog Common MSB LSB +Vcc ~ ~ 4 1------' Digital Common Voo BrCEN DB151DB7 DBl41DB6 DBl31DB5 HBEN Serial Data I ....'::==+===~ ... ____ Successive -IApproxlmation Aegister Data Latch DBl21DB4 3·State Drivers DB111DB3 Data Aeady DB10JDB2 Status DB9IDBl . Serial Data Strobe Clock and Clock logic 15 DB6IDBO All internal control lines not shown. Aefer to Figures 4 and 5 for OIIset and Gain Adjust connections. DESCRIPTION AND OPERATING FEATURES The ADC700 is a 16-bit resolution successive approximation AID converter. Parallel digital data as well as serial data is available. Several features have been included in the ADC700 making it easier to interface with microprocessors and/or serial data systems. Several analog input ranges are available. Some of the key operating features are described here. More detail is given in later sections of the data sheet. Refer to the block diagram above. RESET The ADC700 has a Reset input that must be asserted upon power-up or after a power interruption. This initializes the SAR, the output buffer register and Data Ready flag. Since .microprocessor systems already use a power-on reset circuit, the same system reset signal can be used to initialize the ADC700. PARALLEL DATA The parallel data output is available through an 8-bit port with 3-state output drivers. High byte and low byte are selected by HBEN (pin 10). A buffer/latch is included between the successive approximation register (SAR) and the 3-state drivers. This feature permits more flexible interface timing than is possible from : most successive approximation converters. The "old" word can be read during the next conversion. A Data Ready flag (pin 12) is asserted when a "new" word is 9.1-24 in the buffer register. The Data Ready flag goes low ("0") when the most significant byte (high byte) is read. If the "old" word is not read, or if only the least significant byte (low byte) is read, Data Ready is not reset. The next conversion output will overwrite the data latch when the conversion is complete. The Data Ready flag remains high. Refer to timing diagrams in the Specifications section. SERIAL DATA Sixteen-bit serial data output is available (pin 11) along with a serial output strobe (pin 14). This serial data strobe is not the internal SAR clock but is a special strobe for serial data consisting of 16 negative-going edges (during conversion) occurring about 2000s after each serial data bit is valid.. This feature eases the interface to shift registers or through optccouplers for applications requiring galvanic isolation. STATUS The familiar Status (or Busy) flag, present in successive approximation AID converters, is available (pin 13) and indicates that a conversion is in progress. Status is valid lIOnS after assertion of the convert command (WR low). Status cannot be used as a sample-hold control because there is not enough time for the sample-hold to settle to the required error band before the ADC700 makes its first conversion decision. CHIP SELECT CS (pin 9) selects the ADC700. No other functions can be implemented unless CS is asserted. WR (pin 7) is the startof-conversion strobe. RD. strobes each output data byte, selectee! by HBEN (pin 10), to the 3-state drivers. Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TWOS COMPLEMENT DATA CODE Most Significant Bit, MSB BTCEN (pin 23) is a logic function that implements the Binary Twos Complement output code for bipolar (+ and -) analog input signal operation. This feature is compatible with twos complement arithmetic in microprocessor math algorithms. That binary digit that has the greatest value or weight. The MSB weight is FSR/2. Resolution An N-bit binary-coded AID converter resolves the analog input into 2N values represented by the 2N digital output codes. INTERNAL CLOCK The ADC700 has a self-contained cIock to sequence the AID logic. The clock is not available externally. An external l6-pulse strobe (pin 14) is brought out to clock serial data only. Use of ADC700 with external clock is not possible. INTERNAL VOLTAGE REFERENCE The ADC700 has an internal low-noise buried-zener voltage reference. The reference circuit has been drift compensated over the MIL temperature range using a laser irim algorithm. The reference voltage is not available externally. DISCUSSION OF SPECIFICATIONS ACCURACY Linearity Error, Integral linearity Error (ILE) Linearity Error is defined as the deviation of actual analog input values from the ideal values about a straight line drawn through the code mid-points near positive fulI scale (at + VFS -lLSB) and at Zero input (at I/2LSB below the first code transition, i.e. at Zero) or, in the case of bipolar operation, near minus full scale (at 1/2LSB below the first code transition, i.e. at -V FS)' Despite the definition, however, code transitions are easier to measure than code midpoints. Therefore linearity is measured as the deviation of the analog input values from a line drawn between the first and last code transitions. Linearity Error specifications are expressed in % of FulI Scale Range (FSR)_ ADC700KH ILE is ±O.OO3% of FSR which is 1/2 LSB at 14-bits_ BASIC DEFINITIONS Differential Linearity Error (DLE), No Missing Codes Refer to Figure 3. for an illustration of AID converter terminology and to Table II in the Calibration section. Differential Linearity Error is defined as the deviation in code width from the ideal value of 1LSB. If the DLE is greater than -lLSB anywhere along the range, the AID will have at least one missing code. ADC700KH is specified to have a DLE of±O.006% of FSR, which is ±ILSB at 14 bits. ADC700KH is specified to have no missing codes at the 14bit level over specified temperature ranges. Full Scale Range, FSR The nominal range of the AID converter. For ADC700, the FSR is 20V forthe OV to +20V and the-lOY to +IOV input ranges or IOV for the OV to + IOV and -5V to +5V input ranges. Least Significant Bit, LSB Gain Error The smallest analog input change resolved by the AID converter. For an AID converter with N bits output, the input value of the LSB is FSR(2-N). The deviation from the ideal magnitude of the input span between the first code midpoint (at -VFS + l/2LSB, for bipolar operation; at Zero for unipolar operation) to the last code midpoint (VFS -lLSB). As with the linearity o---..t-::r--o DBN . 3ka T ~:~n D~ ck ck ~DGND DGND\1 A) High·Zlo VOH (13) and VOl. to VOH (10). B) Hlgh-Z to VOk (13 ) arid VOH 10 VOk (I.). FFFH Gain FFEH Error FFDH S 802,. ~ 801 H ~ 800H .-+______--.--+-!'--_ _ _-!.._--'-I o 7FFH FIGURE 1. Load Circuits for Access Time. ot---t-t-::r--o DBN 3kU T10pF DGND\1 A) VOH 10 High-Z. ~' Offsel Error I I ShiftsTheUne F, T 10pF \1 DGND B) VOk to High-Z. FIGURE 2. Load Circuits for Output Float Delay. Burr-Brown Ie Data Book Supplement, Vol. 33b :~~ ~ "r:-::~ __ 000 H 112LSB Zero (-Fun Scale) I I -t _ Zero .., Transition) I I ~~ : (Bipolar Zero) I I _ _~I~'_~'~~-~-~ I-Zero (-Full-Scale -t t112LSB Calibration TranSition) Analog Input -! 3r.!LSB +Fun-Scale Calibration Transition I- +Fun Scale FIGURE 3_ Transfer Characteristic Terminology. 9.1-25 IIII Ii: Io u ~ z o 5 ...Z III Il i i- For Immediate Assistance, Contact Your Local Salesperson measurements, code transition values are the locations actually measured for this spec. The ideal gain is VFSR -2LSB. Gain Error is expressed in % (of reading). See Figure 3. Gain Error of the ADC700 may be trimmed to zero using external trim potentiometers. . Offset Error Unipolar Offset Error-The deviation of the actual codemidpoint value of the first code from the ideal value located al I/2LSB below the ideal first transition value (i.e. at zero volts). Bipolar Offset Error-The deviation of the actual codemidpoint of the first code from the ideal value located at I/2LSB below the ideal first transition value located at -VFS +1/2LSB. Again, transition values are the actual measured parameters. Offset and Zero errors of the ADC700 may be trimmed 10 zero using external trim potentiometers. Offset Error is expressed as a percentage of FSR. Bipolar Zero Error-The deviation of the actual midscale-code midpoint value from zero. Transition values are the actual measured parameter and it is 1/2 LSB below zero volts. The error is comprised of Bipolar Offset Error, 1/2 the Gain Error, and the Linearity Error of bit 1. Bipolar Zero Error is expressed as a percentage of FSR. Power Supply SensItivity Power Supply Sensitivity describes the maximum change in the full-scale transition value from the initial value for a change in each power supply voltage. PSR is specified in units of %FSR/% change in each supply voltage. Power Supply WIrIng Use heavy power supply and power supply common (ground) wiring. A ground plane is usually the best solution for preserving dynamic performance and reducing noise coupling into sensitive converter circuits. When passing converter power through a connector, uSe every available spare pin for making power supply return connections, and use some of the pins as a Faraday shield to separate the analog and digital common lines. Power Supply Returns (Analog Common and Digital Common) Connect Analog Common and Digital Common together right at the converter with the ground plane. This will usually give the best performance. However, it may cause problems for the system designer. Where it is absolutely necessary to separate analog and digital power supply returns, each should be separately returned to the power supply. Do not connect Analog Common and Digital Common together and then run a single wire to the power supply. Connect a 1 to 47!J.F tantalum capacitor between Digital Common and Analog Common pins as close to the package as possible. Power Supply Bypassing Every power-supply line leading into an AID converter must be bypassed to its common pin. The bypass capacitor should be located as close to the converter package as possible and tied to a solid ground-connecting the capacitors to a noisy ground defeats the purpose of the bypass. Use tantalum capacitors with values of from IO!J.F to lOO!J.F and parallel them with smaller ceramic capacitors for high frequency filtering if necessary. The major effect of power supply voltage deviations from the rated values will be a small change in the Gain (scale factor). Power Supply Sensitivity is also a function of ripple frequency. Figure 4 illustrates typical Power Supply Sensitivity performance of ADC700 versus ripple frequency. Separate Analog and Digital SIgnals Digital signals entering or leaving the layout should have minimum length to minimize crosstalk to analog wiring. Keep analog signals as far away as possible from digital signals. If they must cross, cross them at right angles. Coaxial cable may be necessary for analog inputs in some situations. INSTALLATION Shield Other Sensitive Points The mo~t critical of these is the comparator input (pin 1). If this pin is not used for offset adjustment, then it should be surrounded with ground plane or low-impedance power supply plane. If it is used for offset adjustment, the series POWER SUPPLY SELECTION Linear power supplies are preferred. Switching power supply specifications may appear to indicate low noise output, but these specifications are rms specs. The spikes generated in switchers may be hard to filter. Their high-frequency components may be extremely difficult to keep out of the power supply return system. If switchers must be used, their outputs must be carefully filtered and the power supply itself should be shielded and located as far away as possible from precision analog circuits. 0.1 1/ -Vee LAYOUT CONSIDERATIONS Because of the high resolution and linearity of the ADC700, system design problems such as ground path resistance and contact resistance become very important. For a l6-bit resolution converter with a +IOV Full-Scale Range, lLSB is 1531lV. Circuit situations that cause only second- or thirdorder errors in 8-, 10-, or 12-bit AID converters can induce first-order errors in 16-bit resolution devices. 9.1-26 +vcc +voo I ~ / ~ 0.001 1 10 100 1k 10k 100k Frequency (Hz) FIGURE 4. Power Supply Rejection Ripple vs Frequency; Burr-Brown Ie Data Book Supplement. Vol.33b Or, Call Customer Service al 1·800·548·6132 (USA Only) resistor and potentiometer should be located as close to the converter as possible. The Gain Adjust (pin 4) is an input that has a relatively high input impedance and is susceptible to noise pickup. The Gain Adjust pin should be bypassed with a O.OIIlF to O.l!1F capacitor whether or not the gain adjust feature is used. If the 20V Analog input range is used (pin 28), the 10V Range input (pin 27) may need to be shielded with ground plane to reduce noise pickup. ANALOG SIGNAL SOURCE IMPEDANCE The input impedance of the ADC700, typical of most successive approximation AID converters, is relatively low (2.5kQ to lOill). The input current of a successive approximation A/D converter changes rapidly during the conversion algorithm as each bit current is compared to the analog input current. Since the output impedance of a closed-loop amplifier or a sample-hold amplifier increases with frequency and, in addition, the amplifier must settle to the required accuracy in time for the nex.t comparison/ decision after such a disturbance, care must be taken to select the proper driving amplifier. Unfortunately, high-accuracy operational amplifiers tend to have low bandwidth, while wide-band amplifiers tend to have lower accuracy. One solution is to use a wide-band but perhaps less precise amplifier. Another solution is to add a wide-band buffer amplifier such as the Burr-Brown OPA633 inside the feedback loop of a slower (but precision) amplifier, Figure 5. This reduces the output impedance at high frequencies yet preserves the accuracy at low frequencies. When a sample/hold is needed, a high-linearity, high-speed sample/hold such as the Burr-Brown SHC76 should be used to drive the ADC700. ANALOG INPUT RANGES The analog input circuits of the ADC700 can be connected to accept unipolar or bipolar input signals. These ranges and connections are tabulated in Table I. Circuit connections are shown in Figures 6 and 7. Gain and offset adjustments are described in the calibration section. To operate the ADC700 with a range that gives other convenient values for the LSB, the input resistor may be increased or decreased slightly without seriously affecting the Gain Drift of the converter. Since the input resistors of the ADC700 are within ±2% from unit to unit, this can be consistently done with a fixed series or parallel resistor. The ADC700 can then be calibrated using the Gain and Offset adjustments described in the calibration section. For example, using the ±lOV input range, one can decrease the range slightly by paralleling the 10kQ input resistor (pin 28 to pin I) with a 610kQ metal film resistor to achieve a 300llV LSB instead of the nominal standard 305.175781lV binary LSB. OPTIONAL EXTERNAL GAIN AND OFFSET TRIM Gain and Offset Error may be trimmed to zero using external Gain and Offset trim potentiometers connected to the ADC700 as shown in Figures 6 and Figure 7. A calibration procedure in described in the Operating Instructions section. Multiturn potentiometers with lOOppm/"C or betterTCR are recommended for minimum drift over temperature. These potentiometers may be any value from lOill to lOOill. All resistors should be 20% carbon or better. Pin 1 (Comparator In) and pin 4 (Gain Adjust) may be left open if no external adjustment is planned; however, pin 4 should always be bypassed with O.OIIlF or larger to Analog Common. OPERATING INSTRUCTIONS CALIBRATION Offset and Gain may be trimmed by external Offset and Gain potentiometers. Offset is adjusted first and then Gain. Calibration values are listed in Table II for all ADC700 input ranges. Offset and Gain calibration can be accomplished to a precision of about ±l/2LSB using a static adjustment procedure described below. By summing a small sine or triangular wave voltage with the accurate calibration voltage applied to the analog input, the output can be swept through each of the calibration codes' to more accurately deteimine the transition points listed in Table II. NOTE: The transition points are not the same as the code midpoints used in the static calibration example. OFFSET ADJUSTMENT, 14-BIT RESOLUTION EXAMPLE Static Adjustment Procedure (At Code Midpoints) OV to +10V Range-Set the analog input to +lLSB 14 = 0.00061 V. Adjust the Offset potentiometer for a digital output of 0004A" Set the analog input to +Full Scale -2LSB 14 = +9.9987V. Adjust the Gain potentiometer for a digital output of FFFCH" For a half-scale calibration check, set the analog input to +5.OOOOV and read a digital output code of 80000 , INPUT SIGNAl. RANGE AID OPAlll OPA27 OPA633 Analog ' - - _........ Common FIGURE 5. Wideband Buffer Reduces Output Impedance at High Frequencies. Burr~Brown Ie Data Book Supplement. Vol. 33b ±10V ;;;V ±2.5V OVIo+5V OVto+l0V OV10 +20V OUTPUTCOOE BTCEN= 1 BTCEN=D aDa aOB aOB usa usa USB arc BTC aTC - CONNECT PIN 2 TO PIN CONNECT PIN 28 TO PIN CONNECT SIGNAl. TO PIN 1 1 1 26 26 26 InPul Signal Open Pin 1 Pin 1 Open Inpul Signal 28 27 27 27 27 28 TABLE I. ADC700 Input Range Connections. 9.1 -27 12 w Ii: E S z o -...~ oC) Z •i W I;; z o 2C) S For Immediate Assistance, Contact Your Local Salesperson VOL1AGE(V) ANALOG INPUT RANOE :1:10 :1:5 :1:2.5 010+20 010+10 010+5 U1 10V Re1erence 0 Re1erence OUtput IntImaUonaI AIrport tndulllrtal Parte • llalling Addreaa: PO 80111400 T.t(602)746-1111 .....:911H52·1111 • CabIe:BBRCORP Tucson, AZ 8S734 • Street Addle..: 6730 S. Tucson Blvd. • Tucson, AZ 851116 • Talel:06U481 • FAX: (602) 8119-1510 • ImmedtataProdUC1bt1o:(8OtI)sa.6132 PDS-83S8 9.1-32 Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL T. - +25'C, Vee. +12V or+15V, VEE. -12V or-15V, V,,)(.. _ +5V unless otherwise specified. An,..,..,., .a. 4DC77L11f, ADC774SH MIN PARAMETER TYP MAX " ....n ....nn.. A",..,..,.."a MIN A"""""."~, TYP 12 ADC774TH MAX UNITS · Bits INPUTS ANALOG Voltage Ranges: Unipolar Bipolar Impedance: 0 to +IOV, ~V ±IOV, OV to +20V DIGITAL (CE, CS, RIC, A", 1218) Over TemporabJre Range Voltages: logic I logic 0 Current Capacitance " __ ,~v .. ~ 4.7 9.4 to +10, 0 to ~,±IO 5 10 5.3 10.6 +5.5 +0.8 +2 -0.5 -5 +2~ 0.1 5 +5 ·· ·· · ·· ·· ·· ·· ··· V V kn kn V V pA pF 12 ±112 · %oIFSO' BIts LSB ±112 :1314 LSB LSB :to.47 :to.7S :to.22 :to.S :to.37 :to.S :to.12 %0.25 %ofFS %ofFS %oIFS %ofFS Bits :1:10 ~ ~ ±2.S :1:1 ppml'C ppmJ"C LSB ppml'C LSB LSB ppmJ"C ppml'C LSB LSB 12 ±2 :1:10 ±2 ~ :1:1 ±2 ±4 :1:45 :1:50 :1:25 :1:25 :1:9 ±20 :1:10 ~ :1:1 :1:1 ±2 ±2 :1:112 5 7.5 LSB LSB LSB ±I ±I II CONVERSION nME '''''' B-BkCycle 12-BitCycle · · ±4 :to.25 11 POWER SUPPLY SEHSmVITY Change in Full-Scale Calibration +13.SV < Vee < +16.SVor +11.4V < Vee < +12.6V -16.SV < VEE <-13.5Vor-12.6V < VEE <-11.4V +4.SV < V,OGlC < +S.SV · 5.3 8 · ·· LSB LSB LSB lIS lIS OUTPUTS INTERNAL REFERENCE VOLTAGE Voltage Source Current Available lor E> Bipolar Offset DBl 10VRange DBO(LSB) 20VRange 15 Digital Common ORDERING INFORMATION MODEL ADC774JP ADC774KP AOC774JH AOC774KH AOC774SH AOC774TH 9,1-34 PACKAGE (DIP) TEMPERATURE RANGE Plastic Plastic Ceramic Ceramic Ceramic Ceramic O'C to 750C O'C to 750C O'C 10 750C OOC 10 750C -55'C to 125'C ~OCto125'C UNEARITY ERROR MAX (T_TOT..,J :l:1LSB :l:II2LSB ±ILSB ±II2LSB ±lLSB :t3I4LSB Burr-Brown Ie Data Book Supplement, Vol, 33b Or, Call Customer Service al 1·800·548·6132 (USA Only) MECHANICAL P Package - 28-Pln Plaatlc DIP I'~ r) 0 DIM AI'I AI ('I B B, C 0111 0 E, L ~ 'I ,n, ,n, ,n, ,n, ,n, ,n, D,n, ,n, ,n, ,n, ,n, ,n, E ., Ell!' ~'u''u''u''u''u''u''u''u''u''u''u''u' Pin' 14 o. INCHES MIN MAX .169 200 .015 .070 .015 .020 .055 .015 .OOB .012 1.3BO 1.455 .625 .600 .465 .550 .100 BASIC .BOOBASIC MIWMETERS MIN MAX 4.29 5.08 0.3B 1.7B 0.38 0.51 0.38 1.40 0.20 0.30 35.05 36.96 15.24 15.88 12.32 13.97 2.54 BASIC 15.24 BASIC DIM L 12 a Sill INCHES MIN MAX .100 .200 .000 0' .040 .030 IS' .OBO MIWMETEAS MIN MAX 5.0B 2.54 0.00 0.76 IS' 0' 1.02 2.03 (I) NoIJEDEC SUmdard NOTE: Leads In lrue position within 0,01" (O.25mm) R at MMC at seating plane. Pin numbers shown for referenca only. Numbers may nOl be marked on package. ~~i.~ :~~ l ~ I --I{ L. _ e. _ A, Seating Plane'-8 u ~ H Package - O.S" Wide 28-Pln HermaUc DIP I-I"-----A 28 'I 15 D 0, F DIM A C 0 F G H J K '4 L M N INCHES MIN MAX 1.386 1.414 .115 .175 .015 .021 .035 .060 .100 BASIC .036 .064 .012 .OOB .120 .240 .BOOBASIC 10' .025 .060 - MIWMETERS MIN MAX 35.20 35.92 2.92 4.45 0.53 O.3B 0.B9 1.52 2.54 BASIC 0.91 1.63 0.20 0.30 3.05 6.10 15.24 BASIC 10' 0.64 1.52 NOTE: Leads In true position within 0.01" (O.25mm) R al MMC at saating plane. Pin numbers shown lor referenca only. Numbers may not be marked on package. z o !ii....Z III Ii i i- ~ ABSOLUTE MAXIMUM RATINGS Vex; to Digllal Common ........................................................... OV to +16.5V V.. to Digilal Common "" ...... ' ................................................ OV to -16.5V V,oac to Digital Common ............................................................ OV 10 +1V Analog Common 10 Q.iIIital Com.!""n~ .................................................. ±1V Controllnpuls (CE. CS, A", 1218, RIC) to Digital Common ................................................ -o.5V to V'ODIC +C.5V Analog Inputs (Ref In, BipolarOHset,10V,,) to Analog Common ...................................................................... ±16.5V 20V.. to Analog Common ...................................................................±24V Ref Out ........................................................... Indefinite Short to Common, Momentary Shori to Vcc Max Junction Temperature .............................................................+I65'C Power Dissipation ........................................................................ 1000mW Lead Temperature (soldering, lOs) ... " ............................................ +300'C Thermal Resistance, 8..: Ceramic ................................................. 50'CIW Plastic ................................................. 100'C/W CAunON: These devices are sensitive to electrostatic discharge. Appropriate I.C. handling procscluras should be followed. Burr-Brown Ie Data Book Supplement. Vol. 33b ~ Io e1- a 12 III 9.1-35 For Immediate Assistance, Contact Your Local Salesperson DISCUSSION OF SPECIFICATIONS out the range. Thus. every input code width (quantum) must have a finite width. If an input quantum has a value of zero (a differential linearity error of -ILSB). a missing code will occur. LINEARITY ERROR Linearity error is defined as the deviation of actual code transition values from the ideal transition values. Ideal transition values lie on a line drawn through zero (or minus full scale for bipolar operation) and plus full scale. The zero value is located at an analog input value I/2LSB before the first code transition (OOOHEX to OOIHex)' The full-scale value is located at an analog value 3/2LSB beyond the last code transition (FFEaex to FFFHex) (see Figure I). ADC774KP. KH. and TH grades are guaranteed to have no missing codes to 12-bit resolution over their respective specific;:ation temperature ranges. UNIPOLAR OFFSET ERROR An ADC774 connected for unipolar operation has an analog input range of OV to plus full scale. The f1l'St output code transaction should occur at an analog input value I/2LSB above OV. The unipolar offset temperature coefficient specifies the change of this transition value versus a change in ambient temperature. FFF BIPOLAR OFFSET ERROR FFE AID converter specifications have historically defined bipolar offset as the first transition value above the minus fullscale value. The ADC774 specifications. however. follow the terminology defined for the 574 converter several years ago. Thus. bipolar offset is located near the midscale value of OV (bipolar zero) at the output code transition 7FFHEX to FFD i' e- 802 801 J ~ 7FF .!Z' Q 7FE 800 / 002 : II II II II I I / 800HEX• Bipolar offset error for the ADC774 is defined as the deviation of the actual transition value from the ideal transition value located I/2LSB below OV. The bipolar offset temperature coefficient specifies the maximum change of the code transition value versus a change in ambient temperature. (Bipolar I I Midscale Offset-' : -(Bipolar Transacllon): I Zero) 001 000 I I II =11- -11- 112~ (- Full Scale) ~~UII Scale 112LSB caribratlon Transition) 312LSB I---J + Full Scale + Full carlbratlon Scale Transition Analog Input FULL SCALE CALIBRATION ERROR FIGURE 1. ADC774 Transfer Characteristics Terminology. Thus. for a converter connected for bipolar operation and with a full-scale range (or span) of 20V (±IOV). the zero value of -lOY is 2.44mV below the first code transition (OOOHex to 001 Hex at -9.99756V) and the plus full-scale value of + I OV is 7.32mV above the last code transition (FFEaex at +9.99268) (see Table I). POWER SUPPLY SENSmVITY NO MISSING CODES (DIFFERENTIAL LINEARITY ERROR) A specification which guarantees no missing codes requires every code combination to appear in a monotonically increasing sequence as the analog input is increased through- BINARY (BIN) OUTPUT Analog Inpul Voltage Range One Least Significant B~ (LSB) The last output transition (FFEaex to FFFHex ) occurs for an analog input value 3/2LSB below the nominal full-scale value. The full-scale calibration error is the deviation of the actual analog value at the last transition point from the ideal value. The full-scale calibration temperature coefficient specifies the maximum change of the code transition value versus a change in ambient temperature. Electrical specifications for the ADC774 assume the application of the rated power supply voltages of +5V and ±12V or ±15V. The major effect of power supply voltage deviatons from the rated values will be a small change in the full- INPUT VOLTAGE RANGE AND LsB VAWES Dellned •• :t10V ~ o to +10Y FSR 20V lOY lOY o to +20V 20V 2- 2- "'F 2- "'F n.8 n=12 78.13mV 4.88mV 39.06mY 2.44mV 39.06mY 2.44mV 78.13mV 4.88mV + Full·Scale carlbratlon Midscale Calibration (Bipolar Offset) Zero carlbration (- Full·Scale Callbrallon) + 10V - 3/2LSB 0-I/2LSB -lOY + I/2LSB ..sV-3/2LSB 0-I/2LSB -5V + I/2LSB +10V - 3/2LSB +5V-l/2LSB 010 +1/2LSB +10V - 3/2LSB :tl0V - I/2LSB 010 +II2LSB Output Transition Values FFE,..x 10 FFFlEX 7FFlEX 10 800HEX OOOHEX 10 001_ TABLE I. Input Voltages. Transition Values. and LSB Values. 9.1-36 Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1·800-548-6132 (USA Only) scale calibration value. This change, of course, results in a proponional change in all code transition values (i.e., a gain error). The specification describes the maximum change in the full-scale calibration value from the initial value for a change in each power supply voltage. TEMPERATURE COEFFICIENTS The temperature coefficients for full-scale calibration, unipolar offset and bipolar offset specify the maximum change from the +25°C value to the value at TMIN or T MAX • QUANTIZATION UNCERTAINTY Analog-to-digital conveners have an inherent quantization error of ±1/2ILSB. This error is a fundamental property of the quantization process and cannot be eliminated. CODE WIDTH (QUANTUM) Code width, or quantum, is defined as the range of analog input values for which a given output code will occur. The ideal code width is ILSB. INSTALLATION LAYOUT PRECAUTIONS Analog (Pin 9) and digital (Pin 15) commons are not connected together internally in the ADC774, but should be connected together as close to the unit as possible and to an analog common ground plane beneath the convener on the component side of the board. In addition, a wide conductor pattern should run directly from Pin 9 to the analog supply common, and a separate wide conductor pattern from Pin IS to the digital supply common. Analog common (Pin 9) typically carries +8mA. If the single-point system common cannot be established directly at the converter; a single wide conductor pattern then connects these two pins to the system common. In either case, the common return of the analog input signal should be referred to Pin 9 of the ADC. This prevents any voltage drops that might occur in the power supply common returns from appearing in series with the input signal. If the 20V analog input range is used (etiher bipolar or unipolar), the IOV range input (Pin 13) should be shielded with ground plane to reduce noise pickUp. If the bipolar offset input (Pin 12) is not used to externally trim the unipolar offset as shown in Figure 2, connect it to Analog Common (Pin 9). Coupling between analog input and digital lines should be minimized by careful layout. For instance, if the lines must cross, they should do so at right angles. Parallel analog and digital lines should be separated from each other by a pattern connected to common. If external fu II scale and offset potentiometers are used, the potentiometers and associated resistors should be located as close to the ADC774 as possible. If no trim adjustments are used, the fixed resistors should likewise be as close as possible. Burr-Brown Ie Data Book Supplement, Vol. 33b POWER SUPPLY DECOUPLING Logic and analog power supplies should be bypassed with 10llF tantalum type capacitors located close to the converter to obtain noise-free operation. Noise on the power supply lines can degrade the converter's performance. Noise and spikes from a switching power supply are especially troublesome. ANALOG SIGNAL SOURCE IMPEDANCE The signal source supplying the analog input signal to the ADC774 will be driving into a nominal DC input impedance of either 51dl or 101dl. However, the output impedance of the driving source should be very low, such as the output impedance provided by a wideband, fast-settling operational amplifier. Transients in NO input current are caused by the changes in output current of the internal D/A convener as it tests the various bits. The output voltage of the driving source must remain constant while furnishing these fast current changes. If the application requires a sample/hold, select a sample/hold with sufficient bandwidth to preserve the accuracy or use a separate wideband buffer amplifier to lower the output impedance. 12 III Ii: E o () ~ Z RANGE CONNECTIONS The ADC774 offers four standard input ranges: OV to + IOV, OV to +20V, ±5V, and ±IOV. If a IOV input range is required, the analog input signal should be connected to Pin 13 of the converter. A signal requiring a 20V range is connected to Pin 14. In either case the other pin of the two is left unconnected. Full-scale and offset adjustmens are described below. To operate the converter with a IO.24V (2.5mV LSB) or 20,48V (5mV LSB) input range, insert a 1200 1% metalfilm resistor in series with Pin 13 for the 10.24V range, or a 240n 1% metal-film resistor in series with pin 14 for the 20.48V range. Offset adjustments are still perfomed as described below. A fixed metal-film resistor can be used because the input impedance of the ADC774 is trimmed to typically less than ±2% of the nominal value. CALIBRATION OPTIONAL EXTERNAL FULL-SCALE AND OFFSET ADJUSTMENTS Offset and full-scale errors rnay be trimmed to zero using external offset and full-scale trim potentiometers connected to the ADC774 as shown in Figures 2 and 3 for unipolar and bipolar operation. CALIBRATION PROCEDUREUNIPOLAR RANGES If adjustment of unipolar offset and full scale is not required, replace R. with a son, I % metal-film resistor and connect Pin 12 to Pin 9, omitting the adjustment network. If adjustment is required, connect the converter as shown in Figure 2. Sweep the input through the end-point transition voltage (OV + I/2LSB; + 1.22mV for the 10V range, +2.44mV for the IOV range) that causes the output code to be DBO ON 9.1-37 - o I; ~ III I! Ii! i- For Immediate· Assistance, Contact Your Local Salesperson l!2LSB above the minus full-scale value (-4.9988V for the ±5V range. -9.9976V for the ±IOV range). Adjust R. for DBO to toggle ON and OFF with all other bits OFF. To adjust fullscale. apply a DC input signal which is 3!2LSB below the nominal plus full-scale value (+4.9963V for ±5V range. +9.9927V for ±IOV range) and adjust Ra for DBO to toggle ON and OFF with all other bits ON. +Vcc Full·Scale Adjusl ,:.01 Tl00~ -Vee CONTROLLING THE ADC774 Bipolar Offsel Analog Common FIGURE 2. Unipolar Configuration. (high). Adjust potentiometer R. until DBO is alternately toggling ON and OFF with all other bits OFF. Then adjust full scale by applying an input voltage of nominal full-scale value minus 3!2LSB. the value which should cause all bits to be ON. This value is +9.9963V for the IOV range and + 19.9927V for the 20V range. Adjust potentiometer R2 until bits DBI-DBII are ON and DBO is toggling ON and OFF. CALIBRATION PROCEDURE-BIPOLAR RANGES If external adjustments of full-scale and bipolar offset are not required. the potentiometers may be replaced by son. I % metal-film resistors. If adjustments are required. conitectthe converter as shown in .Figure 3. The calibration procedure is similar to that described above for unipolar operation. except that the offset adjustment is performed with an input voltage which is Bipolar 0IIse1 ~-'\JMr-...-I Adjusl The Burr-Brown ADC774 can be easily interfaced to most microprocessor systems and other digital systems. The microprocessor may take full control of each conversion. or the converter may operate in a stand-alone mode. controlled only by the RiC input. Full control consists of selecting an 8- or 12-bit conversion cycle. initiating the conversion. and reading the output data when ready-choosing either 12 bits all at once. or 8 bits followed by 4 bits in a left-justified CS. AD' RiC. and CE) format. The five control inputs are all TIUCMOS-compatible. The functions of the control inputs are described in Table II. The control function truth table is listed in Table III. (IUS. Read footnote 5 to the Electrical Specifications table if using ADC774 to replace the HI774. STAND-ALONE OPERATION For stand-alone operation. control of the converter isaccomplished by a single control line connected to In this mode ~. and Au are connected to digital common and CE and 12{8 are connected to VLOGIC (+5V). The output data are presented as 12-bit words. The stand-alone mode is used in systems containing dedicated input ports which do not require full bus interface capability. Ric. Conversion is initiated by a high-to-low transition of I!!.C. The three-state data output buffers are enable when RIC is high and STATUS is low. Thus. there are two possible modes of operation; conversion can be initiat~ with either positive or negative pulses. In either case the RIC pulse must remain low for a minimum for sOns. Figure 4 illustrates timing when conversion is. initiated by and RIC pulse which goes low and returns to the high state during the .conversion. In this case. the three-state outputs go to the high-impedance state in response to the falling edge of RIC and are enable for external access of the data after completion of the conversion. Figure 5 illustrates the timing when conversion is initiated by a positive RIC pulse. In this mode the output data from the previous conversion is enable during the positive portion of RiC. A Dew conversion is started on the falling edge of RiC. and the three-state outputs return to the high-impedance state until· the next occurrence of a high RIC pulse. Timing specifications for stand-alone operation are listed in Table IV. FULLY CONTROLLED OPERATION Analog Common FIGURE 3. Bipolar Configuration. 9.1-38 Conversion Length Conversion length (8-bit or 12-bit) is determined by the state of the Au input. which is latched upon receipt of a conversion start transition (described below). If Au is latched high. the Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) PIN DESIGNAnON DEFINmON FUNCTION CE (Pin 6) Chip Enable (active high) Must be high ('I") to either InlUate a conversion or read outpUt data. 0-1 edge may be used to InlUate a conversion. i5S (Pin 3) Chip Select (active low) RIC (Pin 5) ReadIConvert ("1"~ read) ("0" = convert) Must be low ("0") to either InlUata a conversion or read outpUt data. 1-0 edge may be used to Inmate a conversion. Must be low ('0") to Initiate either a or 12-bit conversions. 1-0 edge may be used 10 Inmate a conversion. Must be high ('I") to read output data. 0-1 edge may be used to InlUate a read operaUon. A, (Pin 4) Byte Address Short Cycle In the start-convert mode, Ag selects 8-blt (Ag. 'I") or 12-blt (Ag • "0") conversion mode. When reading output data In two a-bit bytes, Ag = "0" accesses a MSBs (high byte) and Ag = "I" accesses 4 LSBs and trailing "Os" (low byte). 121ii (Pin 2) Data Mode Select ("1". 12 bits) ("0" = a bits) When reading output data, 1218 = 'I" enables all 12 outpUt bits simultaneously. 121f. "0" will enable the MSB's or LSB's as determined by the Ag line. I: TABLE II, ADC774 Control Line Functions. CE CS RIC 0 x x X 1 0 0 X i i 1 1 1 1 1 1 1 J. J. 0 0 0 0 0 121ii x J. J. X X X X X X X 1 1 1 1 0 0 0 0 0 0 A, OPERAnoN X X None None Initiate 12-blt conversion Initiate 8-bit conversion Initiate 12-bit conversion Inmate a-bit conversion Initiate 12-blt conversion Initiate a-bit conversion Enable 12-blt outpUt Enable a MSBs only . Enable 4 LSBs plus 4 trailing zeros 0 1 0 1 0 1 X 0 1 RiC 't"" f..., t". '100.. PARAMETER Low RIC Pulse Width STATUS Delay fro,!! RiC Data Valid After RIC Low STATU!!, Delay Aller Data Valid High RIC Pulse Width Data Access Time MIN E ---itiRL~I. ..J ..... + -~-I STATUS DB11-DBO FIGURE 4. ~~oo Data Valid :t:- +j'- l c - t~ I__ Hlgh-Z State Data Valid RIC Pulse Low-Outputs Enabled After Conversion. TABLE III. Control Input Truth Table. SYMBOL 12 III 8 ~ z o -ti I-i Z III TYP 50 200 25 150 :E := MAX UNITS 375 150 150 II: ns ns ns ns ns ns Iiiz - TABLE IV. Stand-Alone Mode Timing, FIGURE 5. conversion continues for 8 bits. The full I2-bit conversion will occur if Ao is low. If all 12 bits are read following an 8-bit conversion. the 3 LSBs (DBO-DB2) will be low Oogic 0) and DB3 will be high (logic I), A. is latched because it is also involved in enabling the output buffers, No other control inputs are latched. CONVERSION START The convener is commanded to initiate a conversion by a transition occurring on any of three logic inputs (CE. CS. and RIC) as shown in Table III. Conversion is initiated by the last of the three to reach the required state and thus all three may be dynamically controlled. If necessary. all three may change state simultaneously, and the nominal delay time is the same regardless of which input actually stans conversion. If it is desired that a panicular input establish the Burr-Brown Ie Data Book Supplement. Vol.33b RIC Pulse High-Outputs Enabled only While RIC Is High. actual stan of conversion. the other two should be stable a minimum of sOns prior to the transition of that input. Timing relationships for stan of conversion timing are illustrated in Figure 6. The specifications for timing are contained in Table V. The STATUS output shows the current stale of the convener by being in a high state only during conversion. During this time the three-state output buffers remain in a high-impedance state, and therefore data cannot be read during conversion. During this period additional transitions of the three digital inputs which control conversion will be ignored. so that conversion cannot be prematurely terminated or restaned. However. if A. changes state after the beginning of conversion. any additional stan conversion transition will latch the new state of Ao. possibly causing an incorrect conversion length (8 bits versus 12 bits) for that conversion. 9.1-39 For Immediate Assistance, Contact Your Local Salesperson PARAMETER SYMBOL ""'!"'c Issc" r..., t..., t,.., t..., I,w; Ie STS Delay from CE CE Pulse WIdth ~ to CE Setup time CS_IOW during CE high ~ to CEsetup RIC low during CE high A" to CE setup A" valid during CE high Conversion time 12-b1t cycle at 25'C o to +75'C -55'C to +125'C IHI" cyda at 25'C o to +75'C -55"C to +1,25'C ..N 50 50 50 50 50 0 50 TYP MAX 60 30 20 20 0 20 200 B 8.5 9 5 ns 118 118 118 118 118 118 118 20 7.5 UNRS 5.3 5.7 6 jill jill jill jill jill jill Read Mode t". t,., t". t..., t..,. t",. t.t,.." t"" AI:cass time from CE Data valid altar CE low 2!!IpUi float dalay CS_to CE setup ~to CE setup CS vatid altar CE low RiC high after CE tow A" valid after CE low STS delay after data valid 75 150 35 25 100 0 50 0 0 0 50 ns 118 150 ns ns ns '118 ns 150 375 118 118 TABLE V. Timing Specifications. CE------44~-----~~------.~------- ~----'n--~~------------------ S~------~----~ FIGURE 6. Conversion Cycle Timing. CE -------'I ~--~r_+----------~~r_---- ~------~--------~--~r_--~---- FIGURE 7. Read Cycle Timing. READING OUTPUT DATA After conversion is initiated, the output data buffers remain in a high-impedance siate until the following four logic cOnditions are simultaneously met: RIC high, STATUS low, CE high. and CS low. Upon satisfaction of these conditions, the data lines are enabled according to the stale of inputs 12/ '8 and Au. See Figure 7 and Table V for timing relationships and specifications. 9.1-40 In most applications the IUS input will be hard-wired in either the high or low condition, although it is fully TTLand CMOS-compatible and may be actively driven if desired. When 1218 is high, all 12 output lines (i)BO-DBll) are enabled simultaneously for full data word transfer 10 a 12-bit or 16-bit bus. In this situation the A. stale is ignored Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) fonnats of the two S-bil bytes are shown in Figure S. The design of the ADC774 guarantees that the Ao input may be toggled at any time with no damage to the converter; the outputs which are tied together as illustrated in Figure 9 cannot be enabled at the same time. In the majority of applications. the read operation will be attempted only after the conversion is complete and the STATUS output has gone low. In those situations requiring the earliest possible access to the data. the read may be started as much as (tnn + tHS ) before STATUS goes low. Refer to Figure 7 for these timing relationships. When 12/8 is low. the data is presented in the fonn of two S-bit bytes. with selection of the byte of interest accomplished by the state of Ao during the read cycle. Connection of the ADC774 to an S-bit bus for transfer of left-justified data is illustrated in Figure 9. The Ao input is usually driven by the least significant bit of the address bus. allowing storage of the output data word in two consecutive memory locations. When Ao is low. the byte addressed contains the SMSBs. When Au is high. the byte addressed contains the 4LSBs from the conversion followed by four logic zeros which have been forced by the control logic. The left-justified Word 2 E Processor o() Converter FIGURE S. 12-Bit Data Fonnat forS-Bit Systems. \..J p r AD J 1218 STATUS DBll (MSB) ~ Z r;-f- -~ o 1= 27 1= 26 r; L... IIII Ii: 1= 25 1= 24 1= 23 1= 22 1= 21 1= Ao Address Bus ADC774 Ji III Data Bus J! i Iiiz - 20 1= 19 1= 18 DBO(LSB) Digital Common 1= 17 1= ~ ~'l FIGURE 9. Connection to an S-Bit Bus. Burr-Brown Ie Data Book Supplement, Vol. 33b 9.1-41 For Immediate Assistance, Contact Your Local Salesperson BURR-BROWN@ ADS574 ADS774 l.a.al ADVANCE INFORMAnON SUBJECT TO CHANGE Microprocessor-Compatible CMOS Sampling ANALOG-TO-DIGITAL CONVERTERS FEATURES DESCRIPTION • COMPATIBLE WITH ADC574A, ADC674A AND ADC774 SOCKETS • COMPLETE SAMPUNG A to D's WITH REFERENCE, CLOCK AND MICROPROCESSOR INTERFACE • FAST ACQUISITION AND ADS774 at 8118 max ADS574 at 25118 max • EUMINATE NEED FOR SAMPLE/HOLD IN MOST • GUARANTEED AC AND PERFORMANCE maximum (including set at 8J1S maximaximum for the sampling function is who want to eliminate the in existing designs. ADS774 are available in commerand military (-55°C to +125°C) require +5V, with -12V or -15V optional, on usage. No +15V supply is required. are available in 0.3" or 0.6" wide 28-pin plastic hermetic DIPs. in 28-pin SOICs. and in die form . ....--_ _.... Status ConlrDl InpulS InIImaJIOnaI »paot IndUllrIaI...... • llallng Add-= PO Il0l11400 TucIan, liZ. 85734 • SIrIII Adena: 81311 S. TucIan aMI. • TucIan, liZ. 857118 Til: (&0217*1111 • Twl:81H52-1111 • ClbIa:BIRCORP • 1'IIII:1I6H481 • FAX:(602)88Io151D • ImmIdIaJaPraduclInlO:(ICIOI54HI32 PDS-973A 9.1-42 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) SPECIFICATIONS ELECTRICAL T•• T... to T_, Voo. +5V, v" • -15V to +5V sampling frequency 01 40kHz on ADS574 and 117kHz on ADS774; unlass otherwise specified. PARAMETER Voltage Ranges: Unipolar Bipolar Impedance: ADS574: o to +10V, :l5V ±10V, OV to +20V ADS774: o to +10V,:I5V ±10V, OV to +20V V V o to +10, 0 to +20 :15, ±10 17.5 70 25 110 kn kn 32.5 150 kn kn 8.75 35 DIGITAL (CE, T"N to TUAX Voltages: Logic 1 logic 0 Current POWER SUPPLY SENSITIVITY Change In Full·Scale Calibration +4.75V < Voo < +5.25V Burr-Brown Ie Data Book Supplement, Vol, 33b I Co) a C ±4 LSB LSB LSB %oIFS~' Bits LSB ±112 :l:f.lI4 LSB LSB ±O.37 ±O.5 ±O.12 ±O.25 %ofFS %ofFS %ofFS %ofFS BIIs 12 Unipolar Max Change Bipolar Offset Max Change: J, K S, T Full·Scale Calibration Max Change: J, K Grades S, TGrades Ii: 0 DC ACCURACY At+2S'C Unearity Error Unipolar Offset Error (adjustable to Bipolar Offset Error (adjustable to Full-&:ale Calibration Error "' (adjustable to No Missing Codes Inherent Quantization T... to T_ Unearity Error: AC ACCURACY Q, (F... 10kHz lot F... 20kHz for Spurious Free Tolal Harmonic Slgnal·ta-Nofse I 12 III 76 -72 -75 71 70 :15 ±2.5 ±2 ±2 ±1 :15 ±1 ±4 ±45 ±2 ±25 ;t9 ±5 ±10 ±10 ±20 ±112 Z 0 !ii... Z III Il ~ a: I;; Z dB dB dB dB ppmI'C LSB ppmI'C LSB LSB ppml'C LSB LSB LSB 9,1-43 ~ ~ I"'" ~ For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS (CONT) ELECTRICAL T•• T.... to T.... , Voo. +5V, VEE. -15V to +5V sampling frequency 01 40kHz on AOS574 and 117kHz on ADS774: unless otherwise specIfled. UNRS PARAMETER CONVERSION TIME (Including Acquisition Time) ADS574 I.., + Ie al 25'C: 8·BIICycie 12·Blt Cycle 12·BH Cycle. T"N 10 T""" AOS574 lAO + Ie al25°C: 8·BH Cycle 12·BiI Cycle 12·BH Cycle, T"N 10 T.... SAMPUNG DYNAMICS Sampling Rate AOS574 AOS774 al 25°C AOS774, T"N to T""" Aperture Delay, lAP With V" • +5V With V" = OV 10 -15V ADS574 AOS774. Aperture Uncertainly (Jitter) With V" = +5V With V" = OV to -15V AOS574 AOS774 16 22 22 18 25 25 5.5 7.5 5.9 8 8.5 8 kHz kHz kHz 40 125 117 ns ps, rms ns, rmS ns,nns 8 V V pA pF V mA V.., +5.5 +20 0 -55 +15 -t3O 85 75 100 V V mA mA mA mA ISO mW mW +70 +125 'C 'C 'Same Specification as or AOS774JElJP/JUISFISH. NOTES: (1) With fixed son OUT to REF IN. This parameter Is also adjustable to zero at +25'C. (2) FS In this specIIIcation table means Full Scale Range. That Is, lor a ±10V Input . FS means 20V: lor a 0 to +10V range, FS means 10V. (3) Based on using VEE = +5V, which starts a conversion Immediately upon a convert command. Using V" • OV to -15V makes the AOS5741ADS774 emulate standard ADS574 operation. In this mode, the Intemal sarnpien101d acquires Ihe input signal after receiving the convert command, and does not assume that the Input level has been stable before the convert command anIves. (4) Using Intemal relerenos. (5) V" Is optional, and Is only used to set the mode lor the Intemal samplelhold. When VEE. -15V,Iu. -lmA typ: when VEE. OV, I... ±SpA typ: when VEE = +5V, 1,. = +167pA typo 9.1-44 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) MECHANICAL E Package - 0.3" Wide 2II-Pln Plastic DIP -;-a-.--.-.---- A ------~1;"11 ........... )0 III _... _~ pi"\., ".,., ..n.. .,.,.,."""'- ~ ...,., ..n.. ~ '-L o 14 DIM A B D E F G H J K M N P MIWMETERS INCHES MIN MAX MIN MAX 1.255 1.355 31.88 34.42 6.88 7:J7 .270 .290 .150 .170 3.81 4.32 •010 .060 0.25 2.03 .IDOBASIC 2.54 BASIC •045 .055 1.14 1.40 0.51 .016 .020 0.41 3.18 .125 NlA NlA 7.62 BASIC :JDOBASIC 15' 0' 15' 0' .008 .015 0.20 0:J8 .020 .040 0.51 1.02 NOTE: Leads In true position within 0.01· (0.25mm) Rat MMC al seating plane. Pin numbers shown for reference only• Numbers may nol be matked on package• IIII Ii: Io () ~ Z NOTE: Leads In true position within 0.01· (O.25mm) R al MMC al seating plane. Pin numbers shown for reference only. Numbers may nol be matked on package. -...ti o Z III I! ::::. II: iDIM A C D F G H J K L M N Burr-Brown Ie Data Book Supplement, Vol.33b INCHES MIWMETERS MIN MAX MIN MAX US8 1.414 35.20 35.92 .115 .175 2.92 4.45 .015 .021 0:J8 0.53 .035 .080 0.89 1.52 2.54 BASIC .IDOBASIC .038 .084 0.91 1.83 .008 .012 0.20 O:JO .120 .240 3.05 8.10 .6DOBASIC 15.24BASJC 10' 10' .025 .080 0.64 1.52 - NOTE: Leads In true position wlthln 0.01· (O.25mm) R at MMC at seating plane. Pin numbers shown for reference only. Numbers may nol bematkedon package. - 9.1-45 For Immediate Assistance, Contact Your Local Salesperson MECHANICAL P Package - 0.6" Wide _In Plasttc DIP r - - - - - - - - D ---------1 1'28 DIM All) A,ltl o o B Bt C DOl E E111) at aA INCHES MlLUMETERS MIN MAX MIN MAX .169 .200 4.29 5.08 .015 .070 0.38 1.78 0.51 .015 .020 0.38 .015 .055 0.38 lAO .008 .012 0.20 0.30 1.380 1.455 35,05 36.96 ,600 .625 15.24 15.88 .485 .550 12.32 13.97 .100 BASIC 2.54 BASIC .600 BASIC 15.24 BASIC DIM ...L a SOl INCHES MIN MAX .100 .200 .000 .030 0" IS" .040 .080 MIWMETERS MIN MAX 2.54 5.08 0.00 0.76 15' 0" 1.02 2.03 (1) NoIJEDEC Slandlllf NOTE: Leads In lrue posllion wflhln 0.01" (O.25mm) R at MMC at seating plane. Pin numbers shown lor relerence onIy. Numbers may not be marked on package. NOTE: Leads In lrue position within 0.01" (O.25mm) Rat MMC at seating plane. Pin numbers shown lor reference only. Numbers may net be marked on package. MODEL ADS574JE ADS574KE ADS574JP ADS574KP ADSS74JU ADS574KU ADSS74SF ADSS74TF ADS574SH ADS574TH ADS774JE ADS774KE ADS774JP ADS774KP ADS774JU ADS774KU ADS774SF ADS774TF ADS774SH ADS774TH 9.1-46 0.6" Ceramic DIP 0.6" Ceramic DIP 0.3" PlaStic DIP 0.3" Plastic DIP 0.6" Plastic DIP 0.6" Plastic DIP SOIC SOIC 0.3" CeramiC DIP 0.3" Ceramic DIP 0.6" Plastic DIP 0.6" Plastic DIP TEMPERATURE RANGE UNEARITY ERROR OOCto70'C 0'<: to 70"C OOCto70'C 0"Cto700c OOCto70"C 0'Cto70"C -6S'C to 125'C -65'<: to 125'C -65'<: to 125'C -6S'<: to 125'<: OOCto700c O"C to 70"C O"C to 70"C O"C to 70"C OOCto700c' OOC to700c -6S'C to 125'C -6S"C to 125'<: -65'C to 125'C -6S'C to 12S'<: ±ILSB ±II2LSB ±ILSB ±II2LSB ±ILSB ±II2LSB ±ILSB ±II2LSB ±ILSB ±II2LSB ±ILSB ±II2LSB ±ILSB ±II2LSB ±ILSB ±II2LSB ±ILSB ±II2LSB ±ILSB ±II2LSB Burr-Brown feData Book Supplement; Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) CONNECTION DIAGRAM I!... Ii: Io U &:l C Z o -t.i i- Z III :IE i t;; z - 2" 39.06mV 2.44mV ..sV-3/2LSB O-I/2LSB -5V+ I/2LSB +10V-3/2LSB +5V-II2LSB Oto+l/2LSB + 10V - 3/2LSB ±IOV -II2LSB Oto +II2LSB high ("I") to either Initiate a conversion or read output data. 0·1 edge may be used to 'InJUate a conversion. CS(Pln3) Must be low ("01 to either Inillate a conversion or read output data. I.., edge may be used to Initiate a conversion. RtC(Pln 5) Must be low ("0") to Initiate either 8- or 12-b1t conversions. I.., edge may be used to Initiate a conversion. Must be high ("11 to read output data. 0-1 edge may be used to initiate a read operetion. Ao(Pln4) 12Iir (Pin 2) Byte Address Short Cycle In the star1-convert mode. Ao selects B-blt (Ao. "11 or 12-11lt (Ao ."0") conversion mode. When reading oulput data In \WO a·blt bytes. Ao."O" accesses a MSBs (high byte) and Ao. "I" accesses 4 LSBs and trailing "Os" (low byte). Data Mode Select ("1".12 blls) ("0". a bits) When reading OUlput data. 12Iii • "I" enabies 01112 output bits simultaneously. 12Iir. "0" will enable tho MSBs or LSBs as determined by the Ao line. TABLE II. Control Line Functions. Burr-Brown Ie Data Book Supplement, Vol. 33b 9.1-47 For Immediate Assistance, Contact Your Local Salesperson CE CS RIC 1z.i A" OPERATION 0 X X t t X 1 0 0 X X X 1 1 1 1 1 1 1 0 0 0 0 0 X X 0 1 0 1 0 1 X 0 1 None None Initiate 12-bIt conversion Inillata 8-bIt conversion °lnillata 12-b1t conversion InillatB 8-bIt conversion Inillata 12-bIt conversion Inillate 8-bIt conversion Enable 12-bR oulpUl Enable 8 MSBs only Enable 4 LSBs plus 4 lra1llng zeroes X 0 0 0 0 ... ... X X X X X 1 1 1 1 0 0 TABLE III- Control Input Truth Table. Low RIC Pulse Wkfth STS Delay 110m RiC Data Valid Aller RiC Low High RiC Pulse WICfth Data Access Time TABLE IV. Stand-Alone Mode Timing. (T" = ns ns ns ns ns ns ns 75 35 150 100 0 150 ns ns ns ns ns ns 25 ns ns ns UNITS 1..,+1" 16 .... 1 ... 101_ 400 ps ps ps ps 5.5 1000 150 375 ns TABLE VI- 9.1-48 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) FFF. FFE" FFD. ! 802. 801. :i1l 800• 0 7FF. .2' IIII 7FE" 002. lie 001. E 000. o () ~ FIGURE 1. ADS574/ADS774 Transfer Z o Ie...- ...:Ez i I; z R/CPulse Low-OutputsEnabled AfterConver- ........ FIGURE 5. RiC Pulse High - Outputs Enabled Only While Ric Is High. : • • • • • ..1 FIGURE 3. Bipolar Configuration. Burr-Brown Ie Data Book Supplement, Vol. 33b 9;1-49 - For Immediate Assistance, Contact Your Local Salesperson CE IttEC CS RiC Ao StablS DBll-DBO enough dme to acquire the Input signal before converting. 9.1-50 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service al 1-800-548-6132 (USA Only) BURR-BROWN@ ADS602 IE:lE:lI ItIII Ii: 12-Bit 1MHz Sampling ANALOG-TO-DIGITAL CONVERTER Io u ~ FEATURES APPLICATIONS • LOW LINEARITY ERROR • DIGITAL SIGNAL PROCESSING • SAMPLE RATE: 1MHz • INPUT RANGES: ±5V, OV to +10V • HIGH-SPEED DATA ACQUISITION SYSTEMS • COMPLETE SUBSYSTEM: Contains Sample/Hold and Reference • MEDICAL INSTRUMENTATION • 32-PIN CERAMIC DIP PACKAGE • TEST AND IMAGING SYSTEMS -...ti • WAVEFORM ANALYZERS III z o • ANALYTICAL INSTRUMENTATION Z DESCRIPTION :IE The ADS602 is a high-speed successive approximation analog-to-digital converter with internal sample/ hold amplifier. This unique design utilizes a bipolar technology with on-chip thin film resistors to preserve analog accuracy and a high-speed CMOS chip to perform digital logic control. Outstanding linearity. noise. and dynamic range are achieved by this converter design. The ADS602 is thoroughly tested for dynamic performance. The ADS602 is complete with internal reference. clock. and comparator and is packaged in a 32-pin ceramic DIP. Sample rate is set at the factory to IMHz. Performance is guaranteed with no missing codes over the input voltage. power supply. and operating temperature range. The gain and offset errors are laser trimmed to specification. Optionally they rnay be externally adjusted to zero. The user can switch between unipolar (OV to +lOY) and bipolar (±5V) operation through one digital logic level input. All digital input and output are TfL-compatible. Power supply requirements are ±15V and +5V. - Parallel Digital Output ' - - - - - 0 Slatus 1kll w o Ic Convert Inpul SamplelHold Command international Airport lnduSlrla1 Park • MalllngAddress:POBoxll400 • TUcsan,AZ85734 • Street Address: 6730 S. TucsanBIvd. • Tucson,AZ 8571J6 Tel: (602) 746-1111 • 1WX:91C1-952-1111 • cable:BBRCORP • T.lex:06U491 • FAX: (602)889-1510 • IrnmedIa18Productlnfo:(IIOO)54N132 PDS·I054 Burr-Brown Ie Data Book Supplement. Vol. 33b Iiiz Output codes are available in complementary binary for unipolar inputs and complementary offset binary for bipolar inputs. ro~====~L-__-Lr~------OCom~oo Analog VIM Signal i 9.1-51 For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL T..... +25"<:. 1MHz sampling rate. ±Vee = ±15V. +V•• = +5V. and 6-mlnute warm-up In a nonnaI convection environment unless otherwise noted. ADS602KG ADS602JG PARAMETER CONDmONS MAX TYP MIN RESOLunON MIN TYP 12 ANALOG CHARACTERISTICS INPUTS Voltage Ranges: Bipolar Unipolar Input Resistance Input Capacitance 'u Full Scale (FSR) Full Scale (FSR) ''''' -5 +5 +10 0 1 5 ·· 10 ·· MAX · ·· · UNI1S Bits V V kO pF TRANSFER CHARACTERISTICS STAne ACCURACY Gain Error ...., Input Offset Error" ": Unipolar Bipolar Integral Unearily Error Dlfferendal Unearily Error No Missing Codes Power Supply Rejection of Offset and Gain ±D.2 ±D.l ±D.l 1.2 1.2 Guaranteed ±D.0036 ±D.DOl A±Vcc -=:1:.10% lJ.±V.. =,±lO% CONVERSION CHARACTERISllCS Sample Rate Power Supply Rejection of Conversion TIme WIthout User Adjustment lJ.+V.. =±5% DC ±D.3 ±D.8 ±D.8 1.5 1.5 ±D.l 0.5 0.5 1M ±1 0.9 0.9 ±D.2 ±D.4 ±D.4 1.25 1.25 %01 FSR %ofFSR % of FSR LSB LSB · ·· %FSRI%Vee %FSRI%V.. ·· ·· · · · sampleSis nsl%VDD DYNAMIC CHARACTERISTICS (The sampling frequency If,) = 1MHz and the Input signal level • -o.5dB. unless otherwise staled.) Differendal Unearily Erro~" Spurious Free Dynamic Range Total Harmonic Distortlon~' Two-Tone Interrnodulation Distortion ... ~ S1gnal-Io-Noise and Distortion (SINAD) Ratio Signal-Io-Nolse Ratio (SNR) Analog Input Bandwidth (-3dB) Small Signal Fun Power fe = 460kHz. 68% of All Codes 99% of All Codes 100% 01 All Codes fe = 10kHz fe =460kHz fe • 10kHz fe = 460kHz = 90kHz and 110kHz (-6.5dB) fe ·10kHz fe ·460kHz fe • 10kHz fe = 460kHz 0.35 0.6 1.2 -74 0.25 0.5 0.9 -86 -68 -73 -79 -83 -70 -72 -2OdB Input OdB Input 16 4 logic Low logic High Logic Low TTL-Compalible CMOS 0 +0.8 +2 +V.. -150 High Level When Converting logic Low. lao. = 3.2mA logic High. I"" = -1 mA TTL1..mpadble ICMOS +0.1 +0.4 +2.7 +4.9 17 Low Level When Data Valid r. -n 71 70 63 84 71 67 70 67 · 1.25 -76 -70 -75 -70 72 67 73 69 ·· LSB LSB LSB dB dB dBc dBc dBc dB dB dB dB MHz MHz DIGITAL CHARACTERISTICS INPUT logic Family Convert Command logic Voltages Convert Command Currents Convert Command OUTPUT logic Family Bits 1 through 12. Staius Inlemal Clock Frequency Status I I I I I I POWER SUPPLY REQUtREMENTS Supply Voltages: +V" -V" +VDD Supply Currents: +1" Operating OperaUng -Icc +IDD Power Consumption Thermal Resistance. B",'" .. • Speccflcation same as ADS602JG . OperaUng +14.25 -14.25 +4.75 +15 -15 +5 28 -110 60 2.3 8.7 +15.75 -15.75 +5.25 30 -140 80 2.8 ·· · · · · · · ··· ·· ·· ·· · · ··· ·· · ·· ··· ·· · ··· ··· · V V pA V V MHz V V mA mA mA mA W 'c/w Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS (CONT) ELECTRICAL (FULL TEMPERATURE SPECIFICATIONS) ±vcc ~ ±15V, +V•• a +5V, and 6·mlnute wann·up In a normal conveCllon environment unless otherwise noted. ADS602KG ADS602JG PARAMETER '10M""",,, U"" RANGE ~, .~_r~n V"KnKv.~n.~ ''''" .._ CONDmONS MIN TeAS, 0 STATIC ACCURACY Gain Error leI Input Offset Error "': Unipolar Bipolar Integral Unearlty Error Dlfferenllal Unearlty Error No Missing Codes Power Supply RejeCllon of Offset and Gain ..n"",,.. , ""'''''''''' Sample Rale Power Supply Rejecllon 01 ConversIon Tlme DYNAMIC vnKnKV. ~~ .. ~ WlthoUI User Adjustmenl t;. +V••• ±5% Spurious Free Dynamic Range Tolal Harmonic Dislortion Two-Tone Inlermedulation Distortion In Signal·to·Nolse and Distortion (SINAD) Ratio Slgnal·to·Nolse Rallo (SNR) Analog Inpul BandWldlh (-3 -50 o :E!- i Samples: 4096 fSAMP'LES: 100000.00Hz Fund: 47973,63Hz THO: -73.3439dB SNR: 6B.2132dB -20 4096 100000.00Hz 23999.02Hz 2497S.S9Hz -7S.BSI4dB THD iD .. I- -50 I BO ~Nk :E!o :r ~ AOSBOB a: z -80 1 edge may be used to Initiate a conversion. Chip Select (Active Low) Must be low ("0") to either Initiate a conversion or read output data. 1->0 edge may be used to Initiate a conversion. RiC (Pin 5) ReadIConvert ("1"= read) ("0" =convert) Must be low ("01 to Initiate either 8- or 12- bit operation. 1->0 edge may be used to Initiate a conversion. A,(Pin4) Byte Address ShortCycle In the start·convert mode. A,selects 8- bit (A, a "11 or 12-blt (A,= "0") conversion mode. When reading oulput data In 2 8·blt bytes. A,a "0" accesses 8 MSBs (high byte) and A,a "I" accesses 4 LSBs and trailing zeros (low byte). 12/8 (Pin 2) Data Mode Select ("I" =12 bits) ("0" =8 bits When reading output data. 1218= "I" enables all 12 output bits simultaneously. 1218 a "O"wlll enable the MSBs or LSBs as determined by the A, line. as (Pin 3) Must be high ("1") to read oulput data. 0·>1 edge may be used to Initiate a read operation. IIII Ii: TABLE II. ADS807/808 Control Line Functions. CE CS RIC 1218 A, OPERATION 0 X 0->1 0->1 1 1 1 1 1 1 1 X 1 0 0 1->0 1·>0 0 0 0 0 0 X X 0 0 0 0 1·>0 1·>0 1 1 1 X X X X X X X X 1 0 0 X X 0 1 0 1 0 1 None None Hold & Initiale 12-bit conversion Hold & IniUale 8-blt conversion Hold & Initiate 12-bit conversion Hold & InlUate 8-blt conversion Hold & Initiate 12-blt conversion Hold & InlUate 8-blt conversion Enable 12·bit output Enable 8 MSBs only Enable 4 LSBs plus 4 trailing zeros X 0 1 TABLE III. Control Input Truth Table. Ric_ Conversion is initiated by a High-to-Low transition (Hold/ Convert) of RiC. This transition commands the sample/bold to Hold and the converter logic to start the conversion. The Sample-To-Hold settling time is so short that the sample/bold is fully settled to the required accuracy before the first successive approximation AID decision occurs. ~ b tos DB11·DBO 1_-_ I "- - - - ; } - - !,.DR I;:::! !"s ~D~a~ta~V~aI~id~)1~__H~i9_h_~_S_ta_te__~( -. ~Data---Va-II-d----- Z Ric The three-state data output buffers are enabled when is High and Status isLow _Thus, there are two possible modes of operation; conversion can be initiat~ with either positive or negative pulses. In either case the RIC pulse must remain low for a minimum of sOns_ Figure 6 illustrates timing when the Hold/Convert command is initiated by an RIC pulse which goes Low and returns to the High state during the conversion. In this case, the three-state outputs go to the high-impedance state in response to the falling edge of RIC and are enabled for external access of the data after completion of the conversion. Figure 7 illustrat~ the timing when Hold/Convert is initiated by a positive RIC pulse. In this mode the output data from the previo~ conversion is enabled during the positive portion of RIC. A new conversion is started on the falling edge of RIC, and the threestate outputs return to the high-impedance state until the next occurrence of a high RIC pulse. Timing specifications for stand-alone operation are listed in Table IV. Output Enables After MIN SYMBOL PARAMETER !,.... tos !"DR Low RIC Pulse Width t,.. tDOR RIC Pulse Low - z o !; III !,.RH FIGURE 6. 8 ~ eX means Don't Care.) STAND·ALONE (NO BUS INTERFACE) OPERATION For stand-alone operation, control of the converter is accomIn this mode plished by a single control line connected to CS and Ao are connected to digital common andCE and 1m are connected to Vee (+SV)_ The output data are presented as 12-bit words_ The stand-alone mode is used in systems containing dedicated input ports which do not require full bus interface capability_ Status i Rig STS Delay from Data Valid After RIC Low STS DeJ!ly After Data Valid High RIC Pulse WIdth Data Access Time TYP MAX UNITS 200 ns ns ns 50 25 115 150 150 375 ns ns 150 ns TABLE IV. Stand-alone Mode Timing_ Conversion. Burr·Brown Ie Data Book Supplement, Vol.33b 9.1-69 :IE i Iiiz - For Immediate Assistance, Contact Your Local Salesperson As with stand-alone operation described above, sample/hold Acquisition Time must be provided before the next Hold/ Convert command. RiC Status !,.," L.!D~ n( High'Z DBll·DBO ' L !,..,_, ~) High·Z State Data vali~ >----.;,,;;;;:~==---- CE FIGURE 7. Ric Pulse High"---Output Enables Only While Ric Is High. Note that, unlike the RIC command input timing for nonsampling NO converters such as the ADC574N674A{774, a time period (Acquisition Time) must be allowed for the sample/hold amplifier to acquire the next sample. This time period, occurring immediately after the conversion is complete (Status goes Low), is IJlS typical (1.5JlS maximum) for acquisition to ±O.OI % of Full Scale Range for a lOY analog input change from the previous held value to the next. FULLY CONTROLLED OPERATION Throughput Period The throughput period, reciprocal of the sampling rate, (S-bit or 12-bit) is determined by the state of the An input, which is latched upon receipt of a Hold/Convert start transition (described below). If Ao is latched High, the conversion continues for S bits. The full l2-bit conversion will occur if Ao is Low. If all 12 bits are read following an S-bit conversion, the 3LSBs (DBO-DB2) will be Low (logic 0) and DB3 will be High (logic 1). Ao is latched because it is also involved in enabling the output buffers. No other control inputs are latched. Conversion Start The converter is commanded to initiate a Hold/Convert operatio!!...by a trans!!!on occurring on any of three logic inputs (CE, CS, and RIC) as shown in Table III. Conversion is initiated by the last of the three logic inputs to reach the required state and thus all three may be dynamically controlled. If necessary all three may change state simultaneously, and the nominal delay time is the same regardless of which input actually starts the operation. If it is desired that a particular input establish the actual start of operation, the other two should be stable a minimum of 50ns prior to the transition of that input. Timing relationships for start of operation timing are illustrated in Figure S. The specifications for timing are contained in Table V. The Status output indicates the current state of the converter by being in a high state only during conversion. During this time the three-state output buffers remain in a high-impedance state, and therefore data cannot be read during conversion. During this period additional transitions of the three digital inputs which control conversion will be ignored, so that conversion cannot be prematurely tenninated or restarted. However, if Ao changes state after the beginning of operation, any additional Hold/Convert transition will latch the new state of Ao' possibly resulting in an incorrect conversion length (S-bits vs. l2-bits) for that conversion. 9.1-70 FIGURE S. ConverSion Cycle Timing. ,READING OUTPUT DATA After operation is initiated, the output data buffers remain in a high-impedance state until the following four logic conditions are simultaneously met: RIC High, Status Low, CE High and CS Low. Upon satisfaction of these conditions the data lines are enabled according to the state of inputs I2,iS and An. See Figure 11 and Table V for timing relationships and specifications. SYMBOL PARAMETER Conversion Mode STS Delay from CE t.,. CEPulseWod1I1 !,... CS to CE Setup time' r... CS low during CE high t,..., RiC to CE setup t".; RIC low during CE high t,.,. A, to CE setup t..c A, valid during CE high ,",C Conversion time plus Ie Acquisition time 12-bit cyc:Ie 8·bncycle MIN 50 50 50 50 50 0 50 TYP MAX UNITS 60 30 20 200 ns ns ns ns ns ns ns ns 20 0 20 20 6 10 6.5 lIS lIS 75 150 ns ns 150 ns ns ns 9 Read Mode \,. !,.. t", t." t... 't,." 't", Access time from CE Data valid after CE low Output float delay CS to CE setup RiC to CE setup CS valid aftei CE low RiC high after CE low A, valid after CE low STS delay after data valid 25 50 0 35 100 0 ns ns 0 0 50 115 150 375 ns ns NOTE: Specifications are at +25"C and measured at 50% level of transitions. TABLE V. Timing Specifications. Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1-800-548-6132 (USA Only) In most applications the 12,iii input will be hard-wired in either the High or Low condition, although it is fully TIL-and CMOS-compatible and may be actively driven if desired. When 12/8 is High. all 12 output lines (DBO-DBll) are enabled simultaneously for full data word transfer to a 12-bit or 16-bit bus. In this situation the state of Ao is ignored. Word 1 Processor DB7 DBa Converter DB11 DB10 DBS DB4 DB3 DB2 OBI DBO DB9 DBS DB7 DB6 DBS DB4 DBO Word 2 When 12/8 is Low, the data is presented in the form of two 8bit bytes. with selection of the byte of interest accomplished by the state of Ao during the Read cycle. Connection of the ADS807/808 to an 8-bit bus for transfer of left-justified data is illustrated in Figure 9. The Ao input is usually driven by the least significant bit of the address bus. allowing storage of the output data word in two consecutive memory locations. Processor DB7 DB6 Converter DB3 DB2 DBS DB4 DB3 DB2 OBI OBI DBO 0 0 0 0 FIGURE 10. l2-Bit Data Format for 8-Bit Bus Syslem. When Ao is Low. the byte addressed contains the 8MSBs. When Ao is High. the byte addressed contains the 4LSBs from the conversion followed by four logic zeros which have been forced by the control logic. The left-justified formats of the two 8-bit bytes are shown in Figure 10. The design of the ADS807/808 guarantees that the Aa input may be toggled at any time with no damage to the converter; the outputs which are tied together as illustrated in Figure 9 cannot be enabled at the same time. C2L..J In the majority of applications the Reaa operation will be attempted only after the conversion is complete and the Status output has gone Low. In those situations requiring the earliest possible access to the data, the Read operation may be started as much as (too max + tas max) before Status goes Low. Of course. Acquisition Time must be allowed for the samplel hold before the next Hold/Convert operation is initiated. Refer to Figure II for these timing relationships. ~ :1; t... ~ -t. r... 1,.." '".. RiC 1"•• '"'" ~ STS DBll·DBO '"" f--I Hjg!J·Z 10. I 8 S z H f ~ - o ~ ...IeZ III J - - '". ,--oalaVa~ I. r... !J 2 ,rA,r 4 S1alus DB11 (MSB) 12m I-27 25 24 Address Bus Da1a Bus 23 ADS8071808 22 21 20 19 18 DBO (LSB) 17 16 Dlgllal Common 15 1 FIGURE 9. Connection to an 8-bit Bus. Burr-Brown Ie Data Book Supplement, Vol. 33b i - 28 28 A, Ii I;; z FIGURE 1L Read Cycle Timing. '-" IIII Ii: 9.1-71 For Immediate Assistance, Contact Your Local Salesperson BURR - BROWN® . ADS7800 .,r.~ 'I.···:1 . IEaEaI . c, •• ·.··.·c . . ., . . . , • ., 12-Bit 3Jls Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION • 333k SAMPLES PER SECOND • STANDARD ±10V AND ±5V INPUT RANGES The ADS7800 is a complete 12-bit sampling NO converter using state-of-the-art CMOS structures. It contains a complete 12-bit successive approximation NO converter with internal sample/hold. reference. clock. digital interface for microprocessor control; and threestate output drivers. • DC PERFORMANCE OVER TEMP: No Missing Codes 1/2LSB Integral Linearity Error 3/4LSB Differential Linearity Error • AC PERFORMANCE OVER TEMP: 72dB Signal-to-Noise Ratio SOdB Spurious-free Dynamic Range -SOdB Total Harmonic Distortion • INTERNAL SAMPLE/HOLD, REFERENCE, CLOCK, AND 3-STATE OUTPUTS • POWER DISSIPATION: 215mW max • PACKAGE: 24-Pin Single-wide DIP 24-Lead SOIC The ADS7800 is specified at a 333kHz sampling rate. Conversion time is factory set for 2.70118 max over temperature. lind the high speed sampling input stage insures a total acquisition and conversion time of 3118 max over temperature. Precision. laser-trimmed scaling resistors provide industry-standard input ranges of ±5Vor±IOV. AC and DC performance are completely specified. Two grades based on linearity and dynamic performance are available to provide the optimum price/performance fit in a wide range of applications. The 24-pin ADS7800 is available in plastic and sidebraze hermetic 0.3" wide DIPs. and in an SOIC package. It oPerates from a +5V supply and either a -12V or-15V supply. The ADS7800 is available in grades specified over O°C to + 70°C and -40°C to +85°C temperature ranges. BUSY 0u1put La1c:hes ±10V'N :t5V'N 2V And Three Tlvae S1I118 Parallel D~V81S 0u1put De1a S1aIe Bus Reference CuI In18rnaIIOnaI »part IndUllrla1 Parle • !lining Add..., PO Box 11400 • ' - . AZ 115134 • s.. AddreII: 6730 S. lUcIan Blvd. • ' - . AZ I1571III TIt (602) 74&-1111 • Twx:'11H52-1111 • CIbII:88RCORP • Tllu:CJ66.84II. FAX:(602) ....1510 • ImmIdIalaPnlductWO:(8OII)54H132, PDS-1018 9.1-72 Burr~Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) SPECIFICATIONS ELECTRICAL T, ~ T." 10 T..... Sampling Frequency. fs• =333kHz. -Vs =-15V. V, • ..sV. unless otherwise specified. ."""'......" .. ",u PARAMETER CONDmONS MIN TYP MAX MIN TYP MAX ANALOG INPUT Voltage Ranges Impedance THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate ±IOV Range :t5V Range 4.4 2.9 Conversion Alone IAcquisition + Conversion B.I 5.4 2.5 2.6 2.7 3.0 380 333 DC ACCURACY Full Scale Error '" Full Scale Error Drift trrtegral Unearity Error Differential Unearily Error No Missing Codes Bipolar Zero '" Bipolar Zero Drift Power Supply Sensitivity ±IOVl:t5V 6.3 4.2 ±112 ±112 ±I 74 :: = 47kHz 67 68 =- 47kHz 77 -77 -77 n -74 -74 70 71 69 70 13 150 130 150 1.9 DIGITAL INPUTS Logic Levels V. V," I, 2.0 10 -0.3 +2.4 2.1 +0.8 ..s.3 -5 +5 ISIM(= 1.6mA IIIQURCE = 50011A 0.0 +2.4 ±D.I POWER SUPPUES Rated Voltage -V, Vs (V.. and V••) Current -Is I, Power Storage · 0.1 INTERNAL REFERENCE VOLTAGE Voltage Source Current Available lor Extemal Loads TEMPERATURE RANGE Specification · I fN = 47kHz I.. = 47kHz I.., = 24.4kHz (-&lB) I", = 28.5kHz (-&lB) -IIA +4.75 JP/JU/KP/KU AHlBH 0 -40 -65 · V kn kn lIS lIS kHz ±D.35 % ±112 ±314 ppml'C LSB'" LSB ±2 LSB Ciu uarantee d ±4 SAMPUNG DYMNAMICS Aperture Delay Aperture Jitter Transient Response ., Overvoltage Recovery'~ I" DIGITAL OUTPUTS Data Format Data Coding Va. V"" I'EAMAOE (High-Z State) · · ±I ±I Transition Noise '" Signal 10 (NOise + Distortion) Ratio Signal 10 NOise Ratio (SNR) · ±D.50 -18.5V < -V. < -13.5V -12.6V < -V, < -11.4V +4.75V < Vs < +5.25V AC ACCURACY Spurious-Free DynamiC Range Total Harmonic Distortion Two·tone Intermodulation Distortion · · ·· ·· 6 ~ UNIlS Bits 12 · · -16.5 ..s.25 3.5 18 135 6 25 215 +70 +85 +150 ·· -77 -77 73 ·· ·· ·· · ·· ·· LSB LSB LSB LSB • ·· · ·· ··· · ·· E 0 U ~ Z 0 - !; l- dB dB III V IIA Z S ::) a: IiiZ - V V IIA IIA 0 0 V V IIA V V rnA mA mW 'c 'C 'C • Same as specification lor ADS7800JP/JUJAH. NOTES: (I) Adjustable to zero with external poterrUometer. (2) LSB means Least Significant Bit. For ADS7800. ILSB = 2.44mV for the :t5V range. ILSB = 4.86mV lor the ±IOV range. (3) Nalse was characterized over temperature near full scale. OV. and negative full scale. O.ILSB represents a typical rrns level 01 noise at the worst case. which was near iuD scale Input at +125'C. (4) All speciflCBtions In dB are relerred to a lull-scale Inpul. e~er ±IOV or ±5V. (5) For full·scale step Inpul. 12-1111 accuracy atteIned In specified time. (8) Recovers 10 specified perlormance in specified time alter 2 x F. Input overvaltage. Burr-Brown Ie Data Book Supplement, Vol. 33b ~ dB'· dB dB ns ps.rrns ns ns ·· · ·· · ±112 72 ··· · Parallel. 12-b~ or B-I>III4-lIIt Binary Offset Binary +0.4 +5.0 :t5 -15 ..s.0 80 -80 -80 ·· ppmrc 12 III 9.1-73 I! tI) a C For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES +V. - +5V. -V•• -15V. and T•• +25'C. unless othelWlse notBd. All pIoIs use 1024 point FFTs. FREQUENCY SPECTRUM (10kHz I.. ) FREQUENCY SPECTRUM (50kHz I.. ) o ~------.-------------------, 0 I... 10kHz 1.. _50kHz -20 H f - - - - - - - - I8AMPUNO = 330kHz -20 1-----+----1......... = 330kHz T._25'C T,,_25°C iii'-40 iii' -40 ~---~---------~ ~-60 i-60 .. ., ~ ~ co ~-60 ~ -60 ~---~----r-----~ -100 -120 0 50 100 Frequency (kHz) 150 165 50 SIGNALJ(NOISE + DISTORTION) vs INPUT FREQUENCY AND AMBIENT TEMPERATURE 100 Frequency (kHz) 150 165 SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY AND AMBIENT TEMPERATURE 75 95 ~ ~" iffi: 65 10 ~~ r" ~~ 50 ~~ ~ I" • b ~ II 65 150 10 Input Frequency (kHz) 150 50 Input Frequency (kHz) SIGNALJ(NOISE + DISTORTION) vs FREQUENCY AND AMPlITUDE 80 OdB - SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY AND NEGATIVE SUPPLY VOLTAGE 95 III ...... iJ~ r--... II "I :--. .....-V._-15V -2OdB I"- ,\ -4OdB \ ~OdB o 10 Input Frequency (kHz) 9.1-74 50 150 10 50 150 Input Frequency (kHz) Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) MECHANICAL H Package - 24-Pln Side Braze ceramic ------------A------------ DIM A B C D F G J K L N 12 INCHES MIN MAX 1.188 1.212 .300 .320 .160 .016 .020 .000TVP .095 .105 .009 .012 .170 BASIC .290 .310 .040 .060 - MILUMETERS MIN MAX 30.18 30.78 7.82 8.13 4.06 0.41 0.51 127TVP 2.41 2.67 0.23 0.31 4.32 BASIC 7.37 7.87 1.02 1.52 - NOTE: Leads In 1rue position within 0.01" (0.25mm) Rat MMC at seating plane. Pin numbers shown for reference only. Numbers may not be marked on package. 2III ~ Io u ~ MECHANICAL z P Package - 24-P1n Pt,aattc DtP .------------A----------_ DIM A B D E F G H J K M N '-,, I '-' I I 'Plnl P INCHES MIN MAX 1.125 1.255 .2SO .290 .150 .170 .010 .080 .100 BASIC .050 .070 .016 .025 .125 .300 BASIC 0' 15° .008 .015 .010 .030 MILUMETERS MIN MAX 28.58 31.88 6.35 7.37 3.81 4.32 .25 2.03 2.54 BASIC 1.27 1.78 0.41 0.64 3.18 7.63 BASIC 15° 0' 0.20 0.38 .25 .76 NOTE: Leads In 1rue posiUon within 0.01" (O.25mm) R al MMC at seating plane. -... o !; Z III II i Iiiz - MECHANICAL Bl B PI 1 DiM A Al 8 81 C D G H J L M N INCHES MILLIMETERS MIN MAX MIN MAX .602 .618 15.29 15.70 .595 .618 15.11 15.70 .286 .302 7.28 7.67 .270 .285 6.86 7.24 .093 .108 2.36 2.74 .015 .019 0.38 0.48 .050 BASIC 1.27 BAStC .028 .034 0.66 0.88 .008 .012 0.20 0.30 .390 .422 9.91 10.72 10' 0° 10° 0° .012 0.00 0.30 .000 NOTE: Leads in 1rue position within 0.01" (0.25mm) R at MMC at seating plane. r----------.-t. J~uu~~uum-1 L It C H G N Burr-Brown Ie Data Book Supplement, Vol. 33b 9.1-75 o o ; For Immediate Assistance, Contact Your Local Salesperson PIN ASSIGNMENTS PIN. NAME 1 2 3 INI IN2 REF 4 5 6 7 8 9 10 11 12 13 14 15 16 t7 AGND Dll Dl0 DB D7 D6 D5 D4 DGND 18 HBE 19 RIC D9 D3 D2 Dl DO 20 CS 21 BUSY 22 -V. 23 24 V.. V.. ABSOLUTE MAXIMUM RATINGS DESCRIPTlON -V. to ANALOG COMMON ............................................................-16.5V V.lo DIGITAL COMMON .................................................................... +7V Pin 23 (V.. ) to Pin 24 (V.. ) ............................................................ ±O.3V ANALOG COMMON to DIGITAL COMMON ....................................... ±1 V ControllnpulS 10 DIGITAL COMMON ............................ -0.3 to V. + O.3V Analog Inpul Voltage .......................................................................... ±20V Maximum Junction Temperature ..................................................... 160'C Internal Power Dissipation ............................................................. 750mW Lead Temperature (soldering, 10s) ................................................ +30O'C Thermal Resistance, 8... : PlastIc DIP ................................................................................ I00"CIW SOIC ......................................................................................... l00"CIW Ceramic ....................................................................................... 50"C1W ±10V Analog Input. Connected to GND Ior;f5V range. ;f5V Analog Inpul Connected to GND lor ±10V range. +2V Relerence Oulpul Bypass to GND wilh 22111' 10 47111' Tanlalum. Buller lor extemalloads. Analog Ground. Connect I!, pin 13. Data BII". MOSI Slgnlllcanl BII (MSB). DataBH 10. Data BH 9. DataBH8. Data BII 7 H HBE Is LOW; I£1N H HBE Is HIGH. Data BI16 H HBE Is LOW; LOW II HBE Is HIGH. Data BI1511 HBE Is LOW; LOW II HBE Is HIGH. Data BI1411 HBE Is LOW; LOW II HBE Is HIGH. Digital Ground. Connect 10 pin 4. Data BI13 II HBE Is LOW; Data Billl II HBE Is HIGH. Data BI1211 HBE Is 1£1N; Data Blll0 II HBE Is HIGH. Data Bill II HBE Is LOW; Data BI19 II HBE Is HIGH. Data BII 0 II HBE Is LOW. Leasl SlgnHicant BII (LSB); Data Bit 8 II HBE Is HIGH. High Byte Enable. When held LOW, data oulpul as ·'2bHs In parallel. When held HIGH, lour MSBs presented on pins 14-17, pins 9-12 ouIpul LOWs. Musl be LOW to Initiate conversion. ReadlConvert. Failing edge Initiates conversion when CS Is LOW, HBE Is 1£1N, and BUSY Is HIGH. Chip Select Outputs In HI-Z state when HIGH. Must be I£1N to initiate conversion or read data. Busy. OUlpuI LOW during conversion. Data valid on rising edge In Convert Mode. Negative Power Supply. -12V or -15V. Bypass to GND. Positive Digital Power Supply. +5V. Connect to pin 24, and bypass to GND. Positive Analog Power Supply. +5V. Connect 10 pin 23, and bypass to GND. PIN CONFIGURATION INI VSA IN2 -Vs BUsY cs RiC HBE DO Dl D6 D2 D5 D3 D4 DGND ORDERING INFORMATION: Integral Error (LSB) Signal-to(NaIIl8+DlatarUon) RaUa (dB min) ADS7800JP ADS7800KP ±1 ±112 67 69 Oto +70 oto +70 Plastic DIP Plastic DIP ADS7800JU ADS7800KU ±1 ±112 67 69 010 +70 Oto +70 PlastlcSOIC PlasticSOIC ADS7800AH ADS7800BH ±1 ±112 67 69 -40 to +85 -40 to +85 CeramIc DIP Ceramic DIP Unearlty Model SpecHlcaUon Temperatura Rangel'C) Package CAUTION The ADS7800 is an ESD (electrostatic discharge) sensitive device. The digital control inputs have a special FET structure. which turns on when the input exceeds the supply by 18V, to minimize ESD dan1age_ However, permanent dan1age may occur on unconnected devices subject to high energy electrostatic fields. When not in use, devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed. 9.1-76 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) THEORY OF OPERATION The ADS7800 combines the advantages of advanced CMOS technology (logic density, stable capacitors, and good analog switches) with Burr-Brown's proven skills in lasertrimmed thin-film resistors to provide a complete sampling analog-to-digital convener. A basic charge-redistribution successive approximation architecture convens analog input voltages into digital words. Figure I shows the operation of a simplified three bit charge redistribution A-to-D. Precision laser-trimmed scaling resistors at the input divide standard input ranges (±lOV or ±5V for the ADS7800) into levels compatible with the CMOS characteristics of the internal capacitor array. OPERATION BASIC OPERATION Figure 2 shows the simple hookup circuit required to operate the ADS7800 in a ±10V range in the Conven Mode. A conven command arriving on pin 19, RiC, (a pulse taking pin 19 LOW for a minimum of 4Ons) puts the ADS7800 in the hold mode, and a conversion is staned. Pin 21, BUSY, will be held LOW during the conversion, and rises only after the conversion is completed and the data has been transferred to the output latches. Thus, the rising edge of the signal on pin 21 can be used to read the data from the conversion. Also, during conversion, the BUSY signal puts the output data lines in Hi-Z states and inhibits input lines. This means that pulses on pin 19 are ignored, so that new Iw ~ io u ~ z o Iii- Convert Command t...r 1-----, FIGURE 1. 3-Bit Charge Redistribution A-to-D. While in the sampling mode, the capacitor array switch for the MSB capacitor (SI) is in position "S", so that the charge on the MSB capacitor is proponional to the voltage level of the analog input signal, and the remaining array switches (Sz and S3) are set to position "R" to provide an accurate bipolar offset from the reference source REF. At the same time, switch Sc is also in the closed position to auto-zero any offset errors in the CMOS comparator. When a conven command is received, switch SI is opened to trap a charge on the MSB capacitor proponional to the input level at the time of the sampling command, switches Sz and S3 are opened to trap an offset charge, and switch Sc is opened to float the comparator input. The charge trapped on the capacitor array can now be moved between the three capacitors in the array by connecting switches SI' Sz and S3 to positions "R" (to connect to REF) or "G" (to connect to GND) successively, changing the voltage generated at the comparator input node. The first approximation connects the MSB capacitor via switch SI to REF, while switches Sz and S3 are connected to GND. Depending on whether the comparator output is HIGH or LOW, the logic will then latch SI in position "R" or "G", and moves on to make the next approximation by connecting Sz to REF and S3 to GND. 'Yhen the three successive approximation steps are made for this simple convener, the voltage level at the comparator will be within I/2LSB of GND, and the data output word will be based on reading the positions of SI' Sz and S3' Burr-Brown Ie Data Book Supplement, Vol. 33b w = IE i! Ii; z - 011 (MSB) OataOul DO (LSB) FIGURE 2. Basic ±10V Operation. conversions cannot be initiated during a conversion, either as a result of spurious signals or to shon-cycle the ADS7800. In the Read Mode, the input to pin 19 is kept normally LOW, and a HIGH pulse is used to read data and initiate a on pin 19 conversion. In this mode, the rising edge of will enable the output data pins, and the data from the previous conversion becomes valid. The falling edge then puts the ADS7800 in a hold mode, and initiates a new conversion. Ric The ADS7800 will begin acquiring a new sample ~ as the conversion is completed, even before the BUSY output rises on pin 21, and will track the input signal until the next conversion is staned, whether in the Conven Mode or the Read Mode. 9.1-77 For Immediate Assistance, Contact Your Local Salesperson For use with an 8-bit bus, the data can be read out in two bytes under the control of pin 18, HBE. With a LOW input on pin 18, at the end of a conversion, the 8 LSBs of data are loaded into the latches on pins 9 through 12 and 14 through 17. Taking pin 18 HIGH then loads the 4 MSBs on pins 14 through 17, with pins 9 through 12 being forced LOW. . CONTROLLING THE ADS7800 The ADS7800 can be easily interfaced to most microprocessor-based and other digital systems. The microprocessor may take full control of each conversion, or the ADS7800 ma..! operate in a: stand-alone mode, controlled only by the RIC input. Full control consists of initiating the conversion and reading the output data at user command, transmitting data either all 12-bits in one parallel word, or in two 8-bit bytes. The three control inputs (CS, RiC and HBE) are all 'ITL/CMOS compatible. The functions of the control lines are shown in Table II. CS FIGURE 3. Acquisition and Convl:rsion Timing. SYMBOL PARAMETER 1_ BUSY delay lrom RIC BUSY Low Aperture Delay Aperture Jitter Conversion TIme t" I" <11" Ie MIN TYP MAX UNns 80 2.5 150 2.7 ns 13 150 2.47 JIS RIC HBE BUSY OPERA11ON 1 0 0 X 1J.o 1 X 0 0 1 1 1 0 0 0 X 1 1J.o 0 X 1 1 1 X 1 1 1 0 None - Oulpu\S In HI·Z State. Holds SIgnal and Initiates Conversion. 0uIput Three-State Bullers Enabled once Conversion has finished. Enable H~Byte In 8-bi1 Bus Mode. Inhibit Start 01 Conversion. None - 0u1pu\S In HI·Z Stale. Conversion In Progress. Outputs HI-Z State. New Conversion Inhibited until Present Conversion has Finished. TABLE II. Control Line Functions. ns ps.rms 2.70 JIS TABLE I. Acquisition and Conversion Timing. ANALOG INPUT RANGES The ADS7800 offers two standard bipolar input ranges: ± IOV and ±5V. If a ±IOV range is required, the analog input signal should be connected to pin I. A signal requiring a ±5V range should be connected to pin 2. In either case, the other pin of the two must be grounded or connected to the adjustment circuits described in the section on calibration. (See Figures 4 and 5, or 10 and II.) For stand-alone operation, control of the ADS7800 is accomplished by a single control line connected to RiC. In this mode, CS and HBE are connected to GND. The output data are presented as 12-bit words. The stand-alone mode is used in systems containing dedicated input ports which do not require full bus interface capability. Conversion is initiated by a HIGH-to-LOW transition on RiC. The three-state data output buffers are enabled when RIC is HIGH and BUSY is HIGH. Thus, there are· two possible modes of operation: conversion can be initiated with either positive or negative pulses. In either case, the RiC pulse must remain LOW a minimum of 4Ons. ±10Vn-_ _-I InpUI'" ~1 ADS7800 :t5V Input FIGURE 4. ±IOV Range Without Trims. 9.1-78 ADS7800 2 FIGURE 5. ±5V Range Without Trims. Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) Figu1!. 6 illustrates timing when conversion is initiated by an RIC pulse which goes LOW and returns HIGH during the conversion. In this case (Conven Mode), the three-state outputs go into the Hi-Z state in response to the falling edge of RIc' and are enabled for external access of the data after completion of the conversion. SYMBOL Iw t DBC t,. I•• .6t"p t" loa. loa I. '.+1" t,.,. t,. t" 1". .t".. t,.. Figure 7 illustrates the timing when conversion is initiated by a positive RIC pulse. In this mode (Read Mode). the output data frorn the previous conversion is enabled during the HIGH ponion of RIC. A new conversion statts on the falling edge of and the three-state outputs return to the Hi-Z state until the next occurrence of a HIGH on RIC. Ric. PARAMETER MIN TYP RIC Pulse Wldih BUSY delay frOm RiC BuSY LOW Aperture Delay Aperture JII18r Conversion TIme BuSY Irom End 01 Conversion BuSY Delay alter Data Valid AcqulslUon TIme Throughput TIme Valid Data Held Alter RiC LOW or HBE LOW belore RIC Falls or HBE LOW alter RIC Falls Data Valid frOm CS LOW. RiC HIGH. and HBE In Desired Stata (Load. 10OpF) Valid Data Held Alter RiC Low Delay to HI·Z Sta1e alter RiC Falls or CS Rises (3kQ Pullup or Pulldown) 40 10 80 2.5 13 150 2.47 100 76 130 2.6 50 5 0 65 60 50 as as 25 20 25 25 20 MAX 150 2.7 UNITS ns ns I1S ns PS. nns 2.70 200 300 3.0 150 150 I1S ns ns ns I1S ns ns ns ns ns ns 12 III Ii E o u ~ z o -'C TABLE III. Timing Specifications (TMIN to TMAX ). !2III I! --~--~~---~--~Ir---~ Converter Mode Convert Data BUS FIGURE 6. Conven Mode: i Iiiz - Convert H~ZStata HI·ZStale RIC Pulse LOW - Outputs Enabled After Conversion. o o ; RIC Converter MOde Data BUS Convert 100 HI·Z Sta1e ~ ~~=-and~~~ Data Ie ___________ . HI·Z Sta1e x=x HI·Z State FIGURE 7. .Read Mode: RIC Pulse HIGH- Outputs Enabled Only When RIC is High. Burr-Brown Ie Data Book Supplement, Vol.33b 9.1-79 For Immediate Assistance, Contact Your Local Salesperson CONVERSION START A conversion is initiated on the ADS7800 only bya negative transition occurring on RiC, as shown in Table I. No other combination ofstates or transitions will initiate a conversion. Conversion is inhibited if either CS or HBE are IDGH, or if BUSY is LOW. CS and HBEshould be stable a minimum of 25ns prior to the transition on RiC.Timing relationships for start of conversion are illustrated in Figure 8. The BUSY output indicates the current state of the converter by being LOW only during conversion. During this time the three-state output buffers remain in a Hi-Z state, and therefore data cannot be read during conversion. During this period, additional transitions on the three digital inputs (CS, RiC and HBE) will be ignored, so that conversion cannot be prematurely terminated or restarted. FIGURE 9. Read Cycle Timing. CALIBRATION CSor HBE OPTIONAL EXTERNAL GAIN AND OFFSET TRIM Offset and full-scale errors may be trimmed to zero using external offset and full-scale trim potentiometers connected to the ADS7800 as shown in Figures 10 and 11. If adjustment of offset and full scale is not required, connections as shown in Figures 4 and 5 should be used. BUSY Data Bus -----1-'1'---------Ex1emal :tl0V Input Gain Adjust ADS7800 1000 2 FIGURE 8. Conversion Start Timing. INTERNAL CLOCK The ADS7800 has an internal clock that is factory trimmed to achieve a typical conversion time of 2.47J1S, and a maximum conversion time over the full operating temperature range of 2.7J1S. No external adjustments are required, and with the guaranteed maximum acquisition time of 300ns, throughput performance is assured with convert pulses as close as 3~s. READING DATA After conversion is initiated, the output buffers remain in a Hi-Z state until the following three logic conditions are simultaneously met: RiC is HIGH, BUSY is HIGH and CS is LOW. Upon satisfaction of these conditions, the data lines are enabled according to the state of HBE. See Figure 9 and Table III for timing relationships and specifications. +5V R, lOkn BIpolar Zero Adjust 6.65kQ 3 4 10k 49.90 5 6 -15V 7 FIGURE 10. ±lOV Range With External Trims. Extenial GaIn Adjust - :l:5V.[;."1 Input R. 1000 zero 4 Adjust R, 101cQ 5 3O.1kll 301Q 101cQ ~15V ADS7800 3 +5V Bipolar 1 2 , '\ 7 6 7 FIGURE 11. ±5V Range,With External Trims. 9.1-80 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (IlSA Only) INPUT VOLTAGE RANGE AND LSB VALUES Input Voltage Range Dellned As: Analog Input Connected to Pin Pin Connected to GND One Least Slgnllicant Bit (LSB) ±tOV 1 2 ±5V 2 1 FSAl2" 20VI2" 4.BBmV 10VI2" 2.44mV FFEH to FFFH +Full Scale +10V-312LSB +9.9927V +SV-312LSB +4.9963V 7FFH to BOOH Mid Scale (Bipolar Zero) -Full Scale OV-1/2LSB -2.44mV -tOV+t/2LSB -9.9976V -5V+t/2LSB -4.99BBV OUTPUT TRANSI110N VALUES OOOH to OOtH OV-II2LSB -t.22mV TABLE IV. Input Voltages, Transition Values. and LSB Values. CALIBRATION PROCEDURE First. trim offset. by applying at the input (pin I or 2) the mid-point transition voltage (-2.44mV for the ±lOV range. -1.22mV for the ±5V range.) With the ADS7800 converting continually. adjust potentiometer R. until the MSB (D II on pin 5) is toggling alternately HIGH and LOW. Next adjust full scale. by applying at the input a DC input signal that is 312LSB below the nominal full scale voltage (+9.9927V for the ±lOV range. +4.9963V for the ±5V range.) With the ADS7800 converting continually. adjust R2 until the LSB (DO on pin 17) is toggling HIGH and LOW with all of the other bits HIGH. LAYOUT CONSIDERATIONS Because of the high resolution and linearity of the ADS7800. system design problems such as ground path resistance and contact resistance become very important. ANALOG SIGNAL SOURCE IMPEDANCE The input resistance of the ADS7800 is 6.3kn or 4.2kn (for the ±IOV and ±5V ranges respectively.) To avoid introducing distortion, the source resistance must be very low, or constant with signal level. The output impedance provided by most op amps is ideal. Pins 23 (Vso) and 24 (VSA) are not connected internally on the ADS7800. to maximize accuracy on the chip. They should be connected together as close as possible to the unit. Pin 24 may be slightly more sensitive than pin 23 to supply variations, but to maintain maximum system accuracy, both should be well isolated from digital supplies with wide load variations. To limit the effects of digital switching elsewhere in a system on the analog performance of the system, it often makes sense to run a separate +5V supply conductor from the supply regulator to any analog components requiring +5V. including the ADS7800. Burr-Brown Ie Data Book Supplement, Vol.33b The Vs pins (23 and 24) should be connected together and bypassed with a parallel combination of a 6.8j1F Tantalum capacitor and a 0.1j1F ceramic capacitor located close to the converter to obtain noise-free operation. (S~ Figure 2.) The -Vs pin 22 should be bypassed with a I j1F tantalum capacitor. again as close as possible to the ADS7800. Noise on the power supply lines can degrade converter performance. especially noise and spikes from a switching power supply. Appropriate supplies or filters must be used. The GND pins (4 and 13) are also separated internally, and should be directly connected to a ground plane under the converter if at all possible. A ground plane is usually the best solution for preserving dynamic performance and reducing noise coupling into sensitive converter circuits. Where any compromises must be made. the common return of the analog input signal should be referenced to pin 4, AGND. on the ADS7800. which prevents any voltage drops that might occur in the power supply common returns from appearing in series with the input signal. z o -...!C ...15z i I;; z - Coupling between analog input and digital lines should be minimized by careful layout. For instance, if the lines must cross, they should do so at right angles. Parallel analog and ~ digital lines should be separated from each other by a pattern ~ connected to common. If external full scale and offset potentiometers are used. the potentiometers and related resistors should be located as close to the ADS7800 as possible. REFERENCE BYPASS Pin 3 (REF) should be bypassed with a 22j1F to 47J.lF tantalum capacitor. A rated working voltage of 2V or more is acceptable here. This pin is used to enhance the system accuracy of the internal reference circuit, and is not recommended for driving external signals. If there are important system reasons for using the ADS7800 reference externally, the output of pin 3 must be appropriately buffered. 9.1~81 o o I! § For Immediate Assistance, Contact Your Local Salesperson "HOT SOCKET" PRECAUTION Two separate +5V Vs pins, 23 and 24, are used to minimize noise caused by digital transients. If one pin is powered and the other is not, the ADS7800 may "Latch Up" and draw excessive current. In normal operation, this is not a problem because both pins will be soldered together. However, during evaluation, incoming inspection, repair, etc., where the potential of a "Hot Socket" exists, care should be taken to power the ADS7800 only after it has been socketed. MINIMIZING "GLITCHES" Coupling of external transienis into an analog-to-digital convener can cause errors which are difficult to debug. In addition to the discussions earlier on layout considerations for supplies, bypassing and grounding, there are several other useful steps that can be taken to get the best analog performance out of a system using the ADS7800. These potential system problem sources are panicularly imponant to consider when developing a new system, and looking for the causes of errors in breadboards. First, care should be taken to avoid glitches during critical times in the sampling and conversion process. Since·the ADS7800 has an intemal sample/hold function, the signal that puts it into the hold state (RiC going LOW) is critical, falling as it would be on any sample/hold amplifier. The edge should be sharp and have minimal ringing, especially during the 20ns after it falls. Ric 9.1-82 Although not normally required, it is also good practice to avoid glitching the ADS7800 while bit decisions are being made. Since the above discussion calls for a fast, clean rise and fall on Ric, it makes sense to keep the rising edge of the conven pulse outside the time when bit decisions are being made. In other words, the conven pulse should either be shon (under lOOns so that it transitions before the MSB decision), or relatively long (over 2.75JlS to transition after the LSB decision). Next, although the data outputs are forced into a Hi-Z state during conversion, fast bus transients can still be capacitively coupled into the ADS7800. If the data bus experiences fast transients during conversion, these transients can be attenuated by adding a logic buffer to the data outputs. The BUSY output can be used to enable the buffer. Naturally, transients on the analog input signal are to be avoided, especially at times within ±2Ons of RiC going LOW, when they may be trapped as pan of the charge on the capacitor array. This requires careful layout of the circuit in front of the ADS7800. Finally, in multiplexed systems, the timing on when the multiplexer is switched may affect the analog performance of the system. In most applications, the multiplexer can be switched as scion as Ric goes LOW (with appropriate delays), but this may affect the conversion if the switched signal shows glitches or significant ringing at the ADS7800 input. Whenever possible, it is safer to wait until the conversion is completed before switching the multiplexer. The extremely fast acquisition time and conversion time of the ADS7800 make this practical in many applications. Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) BURR - BROWN® ADC601 IElElI IIU Ii: Io 12-Bit 900ns ANALOG-TO-DIGITAL CONVERTER FEATURES APPLICATIONS • FAST CONVERSION: gOOns • DIGITAL SIGNAL PROCESSING • CAN BE SHORT-CYCLED • INPUT RANGES: ±5V, ±10V, Oto-1DV • HIGH-SPEED DATA ACQUISITION SYSTEMS • HIGH SIGNAUNOISE RATIO: 68dB • MEDICAL INSTRUMENTATION • ANALYTICAL INSTRUMENTATION u ~ ur z o tiu -:::»z • LOW IMD: 75dB • PARALLEL AND SERIAL OUTPUT • TEST AND IMAGING SYSTEMS • 32-PIN CERAMIC DIP PACKAGE • WAVEFORM ANALYZERS DESCRIPTION with no missing codes over the full input voltage, power supply, and operating temperature range. The gain and offset errors are laser trimmed to specification. Optionally they may be externally adjusted to zero. The ADC601 is a high-speed Duolithic™ (two chips) successive approximation analog-to-digital converter. This unique two-chip desigo utilizes a bipolar technology with on-chip thin film resistors to preserve analog accuracy and a high-speed CMOS chip to perform digital logic control. Outstanding linearity, noise, and dynamic range are achieved by this converter desigo. The ADC601 has been tested with several sample/hold amplifiers and distortion results are documented in this data sheet. The ADC601 is complete with internal reference, clock, and comparator and is packaged in a 32-pin ceramic DIP. Conversion time is set at the factory to 90Ons. Serial and parallel output performance is guaranteed Internal scaling resistors are provided for the selection of analog signal input ranges of±5V, ±IOV andOV to -lOY. The ADC60l's input is specifically designed to be easily driven with minimal disturbance to the driving amplifier. All digital inputs and outputs are TIL-compatible. Power supply requirements are ±15V and +5V. ____r~-----O Input} Range Select 0-,/\1\1'-+ Comparator In -a o SI iu ~ Convert CommMd Parallel Digital Output Clock Rate Control Clock Out L - - - - - - o Status ' - - - - - - - 0 Serial Out 0----+ '--_--'""~ Comparator DuoUthic'Dl Burr-Brown Corporation International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson. AZ 85734 • Street Address: 6730 S. TUcson Blvd. • TUcson, AZ 85706 Tel: (602) 746-1111 • Twx: 910.952·1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (602) 889-1510 • tmmedlate Product Info: (SOD) 54H132 PDS·867B Burr-Brown Ie Data Book Supplement, Vol. 33b 8. Output codes are available in complementary binary for unipolar inputs and bipolar offset binary for bipolar inputs. l'rr=====~-L Bipolar Offset Ii Ii 9.2-83 For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL TCASE =+25'C. 900n. conversion time. ±V.. = ±lSV. +VDO =+SV. and 6-minute warm-up in a normal convection environment unless otherwise noted. ADC601JG PARAMETER CONDITIONS MIN TYP RESOLUTION ADC601KG I I MIN MAX TYP 12 I I MAX UNITS Bits ANALOG CHARACTERISTICS INPUTS Voltage Range.: Bipolar Unipolar Impedance: -10V to OV. ±5V ±10V Full Scale(FSR)"'.' Full Scale(FSR)""2) ·· ·· ±5.±10 Oto-l0 1.4 2.4 V V kll kll TRANSFER CHARACTERISTICS ACCURACY Gain Error<31 Input Offset Erro~": Unipolar Bipolar Integral Unearlty Error Differential Unearlty Error No Missing Codes Power Supply Rejection 01 Offset and Gain 990ns Conversion Time 990ns Conversion Time 990ns Conversion Time 990ns Conversion Time 990n. Conversion Time ±C.08 ±C.12 ±C.08 A +V•• = ±5% Il-Vcc=±5% .L\ +Voo= ±5% ±O.0036 ±O.OOOS ±O.OOl ±C.SS ±1.2 ±C.8 ±O.024 ±O.024 · ±C.2 ±C.S ±C.25 ±O.012 ±O.012 · GUjteed % %oIFSR %oIFSR %oIFSR %oIFSR %FSRtYoV•• %FSR?I.V•• %FSRtYoV" DIGITAL CHARACTERISTICS INPUT logic Family Convert Command Logic Vollage. Convert Command Currents logic Low Logic High logic low Logic High 0 +2 Convert Command TTL~ompaJle CMJ +0.81 : 1 1 +VDD -1 SO -lS0 High Level When Converting CONVERSION TIME Factory Set Power Supply Rejection 01 Conversion Time Without User Adjustment 0.9 ±1 o +VoD=±5% ·· 1 V V JIA JIA ps ns/%VDD OUTPUT Logic Family Bits 1 through 12. Serial. Status. Clock Out Logic Low. Icc. = 3.2mA Logic High. I"" = -1 rnA +2.7 Internal Clock Frequency Status TTL-Compatible CMOS +0.4 +0.1 +4.9 13 Low Level When Data Valid I I . · I ·· · V V MHz DYNAMIC CHARACTERISTICS COl.~' Te.ted using Sample/Hold Amplilier SHC804 and ADC601 (See Typical Performance Curves) Differential Unearity Error I. = 10kHz: 68.3% 01 All Code. 99.7% 01 All Codes 100% 01 All Code. O.S 0.8 1.0 Total Harmonic Distortion 1,= 10kHz. I, = 10kHz. I, = 100kHz. I, = 250kHz. I. = SOOkHz. -70 -74 -72 -70 Two-Tone Intermodulation Distortion(7) Signal-ta-Noise and Distortion (SINAD) Ratio Signal-to-Noi.e Ratio (SNR) I. = 500kHz 1,= 1MHz I, = 500kHz I, = 500kHz I, = 1MHz 0.4 0.6 0.7 ·· ··· · ~8 I, = 11 kHz and 15kHz. I, = SOOkHz I. = 50kHz and SSkHz. I. = SOOkHz I. = 90kHz and 110kHz. I, = 500kHz -79 -78 -77 · · 9.2-84 dBc dBc dBo dBc dBc dBc dBc dBc I, = 100kHz. I, = 500kHz I. = 250kHz. I, = 500kHz I, =500kHz. I, = 1MHz 67 66 65 dB dB dB I, = 100kHz. I, =SOOkHz I. = 250kHz. I, = 500kHz I, = 500kHz. I, = 1MHz 69 68 67 dB dB dB · PERFORMANCE OVER TEMPERATURE Gain Input Off.et: Unipolar Bipolar Internal Unearity Error Differential Unearity Error No Missing Code. Conversion Drift LSB LSB LSB TMlNtoTw.x to TMAl( TUIN to TMAl( 0.9ps Conversion Time TM~ to TMAX 0.9ps Conversion Time T_ to TMAX 0.9ps Conversion Time T"'" to TMAX' TUIN ±10 ±2 ±3 ±C.02 ±O.02 2 ±30 ±7 ±10 ·· ·· · · ±O:015 ±O.015 GUiteed · ppm 01 FSRJOC ppm 01 FSRJOC ppm 01 FSRJOC %oIFSR %oIFSR nsJOC Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) SPECIFICATIONS (cont) ELECTRICAL TCASE a +25'C. 900ns conversion lime. ±vco a ±15V. +VDD a +5V. and B-mlnute warm·up In a normal convection envlronmenl unless otherwise nOled. ADC601JG PARAMETER CONDmONS I MIN TYP +14.25 -14.25 +4.75 +15 -15 +5 5.4 -65 53 1.3 25 I ADC601KG MAX I MIN POWER SUPPLY REQUIREMENTS Supply Voltages: +V" -Vee +Voo Supply Currenls: +1" -Ice +100 Power Consumption Thermal Resistance. 8", Nominal ±V"and +V" TYP , +15.75 -15.75 +5.25 7.0 68.9 1.7 0 --25 MAX , , , , , , -M.5 TEMPERATURE RANGE'" Specification Operating I , , +70 +85 , , , , , , , , I UNIlS V V V rnA mA rnA W 'CIW 'C 'C , Same specifications as for ADC601JG. NOTES: (1) Over or under range on the analog Inpul resulls In constanl maximum or minimum digital output (2) FSR = Full Scale Range. (3) Adjustable to zero. (4) Dynamic tesls are performed using SHC804 with ADC601 unless otherwise specified. Performance may vary depending upon choice of samplelhold. (5) See Typical Performance Curves. (6) dBc. level referred to carrier Input signal. OdS; f, a Inpul!requency; f•• sampling frequency. (7) IMD 10 referred 10 the larger 01 the two Inpullesl signals. II referred 10 Ihe peak envelope signal (-OdB). the Intermodulation products will be 6dB lower. For example. unll connected for±10V has 20V FSR. (8) Temperature ranges refer 10 case temperature. Thermal resistance was measured on a small (5' diameter) handwired drcuil board; with Ihe lesl devica In a (zero Insertlon force) sockel. Tharmal resistance will be lower lithe ADC601 Is soldered Inlo the PC board. a ground plane Is used directly undemeath the package. multiple PC board layers are used. or forced air cooling Is employed. Use heal sinking II necessary to keep the case al spedlled and operating lemperatures. E o u ~ oz tiu o -z ~ MECHANICAL :E :E H Package - 32-Pln llermeUc DIP ---A----'I 1-' M1WMETERS MIN MAX 40.13 41.15 2235 2286 3.51 4.72 0.41 0.51 1.02lYP 2.54 BASIC 1.12 1.42 0.23 0.30 4.19 4.70 L INCHES MIN MAX 1.580 1.620 .880 .900 .138 .186 .016 .020 .040lYP .100 BASIC .044 .056 .009 .012 .165 .185 .900 .920 N .040 1.02 DIM A B C D F G H J K + .060 NOTE: Leads In true position within 0.01" (O.25mm) R al MMC at seating plane. Pin numbers shown for reference only. Numbers may nol be marked on package. o u. o a ~ - 2286 23.37 1.52 § I u a 1 _ _ L _ _...r.1 tC The Information provided herein Is believed 10 be reliable; however. BURR·BROWN assumes no responsibility for Inaccurades or omissions. BURR·BROWN assumes no responsibility for the use of this Information, and all use 01 such Information shall be entirely althe usefs own risk. Prices and specifications are subject to change withoul notice. No palen! rights or licenses 10 any of the circulls described herein are Implied orgranled 10 any third party. BURR·BROWN does nol authorfze or warrant any BURR·BROWN product for use in life support devices andlor syslems. Burr-Brown Ie Data Book Supplement. Vol. 33b Iau Ii: 9.2-85 For Immediate Assistance, Contact Your Local Salesperson PIN CONFIGURATION (MSB) Bit 1 32 Common (Analog) NC(I) B"2 Bit 3 -Vcc (-lSV) Analog Bit 4 Bipolar Offsel Currenl BilS Common (Analog) Bil6 Ground Sense Comparator Input +V cc (+SV) Digital Common (Digital) 10V Inpul SerialOul 20VInpul Status -Vee (-1SV) Analog Bil7 +Vcc (+5V) Digltal(2) BI18 Common (Digital) Bil9 +Vcc (+1SV) Analog Bil10 Clock Rate Conlrol BI111 Convert Command BII12 ClockOul (1) NC = No inlemal connection. Any voltage may be connected 10 pin 31. however. (2) Pin 22 musl be very cleanly decoupled 10 keep digital noise oul of the analog circuits. PIN DEFINITIONS PIN NUMBER DESIGNATION 1-6 and 11-16 9 10 Bi1110B"12 SerialOul Slalus 17 ClockOul 18 Convert Command 19 24 25 26 27 29 Clock Rale Control 20V Inpul 10Vlnpul Comparalor In Ground Sense Bipolar Offset Currenl DESCRIPTION 12-bil parallel outpul data capable of sinking 3.2mA. 12-bil serial data OUtpul synchronized with the negative edge of each appropriate clock cycle. Conversion slalus strobe Is high during data conversion; low when paralleldala is valid. Negalive edge may be used to latch parallel data. however. appropriate latch sel-up time must be prOvided. Refer 10 t.... ln the ADC60111mlng diagram. Negative edge indicates when serial data Is valid. Altar convert command goes )1igh. fisl cycle clocks bit 1 (MSB). The clock continuas 10 run whan convert command is high and resets low with convert command. High transilion starts conversion; and should remain high during conversion. Low will resel clock and SAR logic. Maybe usedto Increaseclockspeed.bylnOreaslnglheposillva portion of the clock. High Is normaloperation. 20V Inpul range allows ±1 OVp-p analog Inpul signal. Short to ground when nol used. 1OV inpul range allows 0 10 -1 OVp-p or ±5Vp-p Inpul range. Only used in bipolar moda when Ills connected 10 bipolar offsel pin through short lead with low resistance. Ground Sanse pin. (See lexl for usa). Bipolar offsel currenl short 10 comparator In Ihrough very short lead with very low resistance for bipolar operation. Short to ground for unipolar operation. ABSOLUTE MAXIMUM RATINGS ±V" ..........•....•..•..••••..••.•.•.••.••.••..•••••.••..••..•.•.•••..•.•..•.••.•..•••.••.•.•..••.•.•.±18V +VDO ..................................................................................................... +7V Digital Inputs •.••••••..••.••.....•.....••..•....•..•.•..•..•...•••••..•.••.••.•••..•..••.••.••.••• +S.SV Analog Inputs ......................................................................................±Vcc Comparator Input ............................................................... -3.7V 10 +0.7V Case Temperature ......................................................................... +12S'C Junction Temperatura .................................................................... +16S'C Slorage Temperature ...................................................... -6S'C 10 +150'C ORDERING INFORMATION ADC601 () G Basic Model Number Performance Grade Code - - - - - - - - - - - - ' J. K: O'C to +70'C Case Temperature Package Code - - - - - - - - - - - - - - - - - - ' G: Ceramic DIP ===r- T Slresses above thase ratings may permanently damage the device. 9.2-86 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES ±Vee - ±15V. +VDD =+5V. 15-mlnule warmup. and Te =-I25'C. unless otherwise noted. All dynamic perfonnance curves are 4096-polnt FFTs. TOTAL HARMONIC DISTORTION I. = 1MHz. Ie = 10kHz - USING ADC601 AND SHCS04 TWO-TONE INTERMODULATION USING ADC601 AND SHC804 o 12 III 0 Ii: -20 -20 Ie - -a.5dB =-77dB 31: • -79dB --------------------·21 41e • ~4dB 51 .-92dB THD = -74dB 1,_ 500kHz ----------------- I". 11kHz (-a.5dB) ---1.. _15kHz (-6.5dB) iii' --40 :e. -8 a -60 .!l ~ E 'Ii. -100 -100 -120 -120 o 125 250 375 0 500 50 TOTAL HARMONIC DISTORTION I. = 500kHz. Ie = 10kHz - USING ADC601 AND SHCS04 o :eCD 41e _ -9OdB 5Ie =-91dB THD = -76dB -8 -60 .!l ~ i ~ -100 -100 -120 -120 62.5 125 187.5 250 0 50 100 150 200 Frequency (kHz) TOTAL HARMONIC DISTORTION I. _ 500kHz. le= 10kHz - USING ADC601 AND SHC5320 TWO-TONE INTERMODULATION USING ADC601 AND SHC804 250 o ~--------------------------~ -20 Ie - -a.5dB 1,_5OOkHz I" = 90kHz (-6.5dB) .----I". 110kHz (~.5dB) 41e - -96dB ----------------- 2fe --l02dB 5Ie =-9OdB 31e = ~OdB THD = -79dB iii' --40 :eCD -60 ~O -100 -100 -120 -120 0 62.5 125 187.5 250 Frequency (kHz) Burr-Brown Ie Data Book Supplement, Vol. 33b :IE :IE o u. o -$I Ie Frequency (kHz) -20 io -ti u -:»z I.-500kHz ----------- I" • 50kHz (-6.5dB) ----lco • 55kHz (-6.5dB) :e- o .!l 250 TWO-TONE INTERMODULATION USING ADC601 AND SHC804 iii' --40 -60 0 i" 200 -20 Ie - -a.5dB ------------------ 2fe =-94dB 31e = ~OdB iii' --40 1 150 0 -20 ".~ 100 Frequency (kHz) Frequency (kHz) 8 ~ o 50 100 150 200 250 Frequency (kHz) 9.2-87 For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (cont) ±V",= ±15V, +VDD= +5V, Rs- son, 15-minute warmup, end T. z +25'C, unless otherwise noted. DIFFERENTIAL NONLINEARITY HISTOGRAM <1 Hz RAMP INTEGRAL NONLINEARITY HISTOGRAM <1Hz RAMP 2r------,----,---.,..-----, 2 -- ......... ,.1. o.Iol. .... ..d ,...,.....,. -1 ~------+-------+-------~----~ ~ L-_ _ o ~ ___ 1024 ~ __ ~ 2048 ___ 3072 -1 ~ o 4095 1024 Codes 3072 2048 4095 Codes CONVERSION TIME vs CLOCK RATE CONTROL VOLTAGE 20 ~ 15 \ \ "'" ~ > 10 J!l a: '" " ~ 5 ~ 0 0.0 0.2 0.4 0.6 Conversion Time - 0.8 1.0 1.2 (~s) THEORY OF OPERATION The ADC601 is a successive approximation analog-todigital converter as shown on the front page of this product data sheet. A common problem with other successive approximation ND converters is input current transients caused by the D/A converter's switching. This requires a fastsettling amplifier to drive the input and to provide a low source impedance at high frequency. To minimize this problem, the ADC60l's comparatoris connected in a differential mode, greatly reducing the input transients, In addition, the input voltage scaling resistors reduce the voltage that is applied to the + input of the comparator. For best performance, a fast settiing wideband sample/hold amplifier such as Burr-Brown's SHC804 is stilI recommended to drive the ADC601. The small signal settling time of this amplifier should be less than lOOns if sampling rates approach I MHz, The accuracy of a successive approximation analog-todigital converter is described by the transfer function shown in Figure I. All successive approximation AID converters 9.2-88 111 ... 111 ~ 8CQ 111...110 100...010 0 8- 100...001 :; 9::I 0 ~ c 100... 000 011 ... 111 011 ... 110 000... 001 000...000 EINOn ! Analog Input rF:R) E'N Off (+F:R -lLSB) 'See Table I for digl1a1 code definitions. FIGURE 1. Input vs Ouput for an Ideal Bipolar AID Converter. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) have an inherent quantization error of ±II2LSB. The remaining elTOIll in the NO converter are combinations of analog errors due to the linear circuitry matching and tracking properties of the ladder and scaling networks, power supply rejection, reference errors and the dynamic errors of the OAC and comparator. Initial gain and offset errors may be adjusted to zero, gain drift over temperature rotates the transfer function (Figure I) about the zero point, and offset drift shifts the transfer function left or right over the operating temperature range. Linearity error is not adjustable, but it is the most meaningful indicator of NO converter accuracy. Integral linearity error is the deviation of an actual bit transition from the best fit straight line transfer function of the NO converter. A differential linearity error of ±II2LSB means that the width of each bit step over the range of the NO converter is ILSB, ±112 LSB. The ADC601 is guaranteed to have no missing codes over its specified temperature range. ACCURACY VS CONVERSION TIME In successive approximation NO converters, the conversion time affects integral and differential linearity error. Conversion time effects on linearity and differential linearity error for the ADC60 I are shown in the Typical Performance Curves. INSTALLATION AND OPERATING INSTRUCTIONS BASIC CONNECTION The basic connection for the AOC601 'is shown in Figure 2. It is shown connected for ±5V bipolar input operation. Refer to Table I for other connections. INTERFACING Because the ADC601 is a high-speed converter, it must be driven from an amplifier source that has low impedance at high frequency. The SHCS03, SHC804, and SHC5320 are specifically designed to give accurate, stable results. At ihe ADC601 output, the digital lines should be buffered by a latch such as the 74LS574. These three-state drivers can then connect directly to the data bus. Each pair of these pins must be connected together externally. The connection between the digital supply pins and the connection between the digital common pins must be as short as possible. The analog and digital commons are not connected together internally in the ADC60l. u ~ ur z -oti -== () Z :E :E GROUND LOOPS Figure 4 illustrates the interaction that occurs between the analog and digital grounds when an ADC is connected into a test circuit. This interaction is created by ground loops. The circuit shows how ground loops are created when the AOC tester combines digital and analog portions of the circuit together. In this case, the loop is between the analog test signal generator and the digital circuitry that detects the AOC code. Here the digital ground connection between the AOC and the tester is in parallel with the analog grounds. Some of the digital current is diverted into the analog signal return, which creates a code-dependent error signal due to the resistance in the analog signal return. This error distorts the linearity measurement and induces hysteresis. It can be substantially reduced if the analog and digital ground effects are isolated from each other in the ADC tester. The best method is to use a low resistance, low inductance ground plane. POWER SUPPLY DECOUPLING Each power supply pin should be bypassed with a IjlF or 150jlF tantalum capacitor as shown in Figure 2. These capacitors should be located close to the ADC. Ceramic O.OljlF bypass capacitors have been provided internally for more effective bypassing and need not be added externally. Burr-Brown Ie Data Book Supplement, Vol. 33b E o A special analog ground called "ground sense" (shown in Figure 3) has been provided to eliminate the voltage drop that' would otherwise be in the ground return of the internal R-2R ladder. Measuring the input signal with respect to the sense terminal (pin 27) makes the measurement independent of the connection impedance between the sense terminal and the analog common, pin 28. This sense pin must be connected to analog common as close to the input signal source as possible or connected to the ground plane. Low impedance analog and digital common returns are essential for low noise performance. To minimize coupling between analog and digital circuits on a layout, special attention should be taken to ensure that the clock noise on the +5V supply line does not couple into the analog inputs. LAYOUT PRECAUTIONS The ADC601 has two pins for analog common, two pins for digital common, and two pins for each power supply input. ~ GROUND SENSE The ADC601 is a high-speed anaIog-to-digital converter that requires more attention to circuit board layout than general purpose, lower speed NO converterS. The wideband AOC601 comparator input (pin 26) is very sensitive to noise. Any connection to this point should be as short as possible and shielded by analog common or±15VDC supply patterns. The clock output (pin 17) is sensitive to stray capacitance, and capacitance on this pin could alter the clock wave shape. IIII Connecting all commons to a ground plane close to the ADC601 is the best method to minimize noise and dissipate heat as shown in Figure 3. ou . o -a ~ lID ADDITIONAL DECOUPLING A lOOpF capacitor may be placed on Clock Rate Adjust (pin 19) to ground in order to reduce noise on the clock. Up to 30pF may be placed on Comparator In (pin 26) without degrading conversion accuracy at Nyquist frequencies. 9.2-89 • For Immediate Assistance, Contact Your Local Salesperson +5 VOC -15V +15V +15 VOC -15 VDC +5V lTL Octal Latch with 3-State Output +5V 22 24 9 Bit 1 Analog Input 0 0 13 1-'-_ _=25"1 10V In Bipolar Offset Current SHC804 Comp In 11 SampleJHold Command Blt2 2 8 00 Blt3 3 7 0 Blt4 4 0 74LS 6 05740 BitS 5 50 +20V In Hold Ground Sense Commons a Blt6 6 3-State Control. ADC601 External Convert Command Blt7 11 ><~ ap 4 18 Convert - - - - = f Command ___2""lB 9 0 a 5 0 a BItS 12 l4LSI23 14 Blt9 13 15 ~--r----t--t-----~10~Starus Bltl0 14 Bit 11 15 Digital 16 = Analog and Digital Ground Plane '-_:-crom_m-::0::-1nrs_ _ _-;:;r-;:;r_-' • All supply bypass capacitors are 1~F tantalum, S 21 unless otherwise specHled. V 4 D (1) In the circuit shown above, the rising edge of the external Convert Pulse Initiates the Hold mode of the SHC804. Assuming a user.provlded convert Pulse with a 50% duty cycle, the 74LSI23 one-shot provides a short pulse for the convert command (pin IS) on the ADC801. The actual one-shotUme chosen, by saWng the R-C on the one-shot, should be just long enough to allow for adequate track-la-hold selliing time. For best I.L. perfonnance, It Is recommended that the one-shot time be less than 400ns, but at least 50ns. FIGURE 2. Basic Connecti9n Diagram in Bipolar Operation and Dynamic Test Circuit. 24 +20V In 12-Blt Digital Output .L = Analog and Digital V 28 Ground Plane FIGURE 3. Analog and Digital Grounds, and Analog Input Sense_ 9.2-90 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) Any daIa oUlpUt pin Digital Ground CUmlnt -·V/.. 8 Digital' Ground Resistance +5V PC Can! Ground 25 Analog Analog Input Signal "- . Ground Currenl U) 27 EXTERNAL SYSTEM Z o -~ -z ::. Analog' Ground Resistance , Ground plane reduces resistance to negligible values. U FIGURE 4. Ground Loop Interaction Between Analog and Digital Grounds when ADC Is Connected. POWER SUPPLY SENSITIVITY INPUT IMPEDANCE Changes in the DC power supply voltages will affect accuracy. Normally. regulated 'power supplies with 1% or less ripple are reconunended for use with this ADC. Power supply decoupling. shown in Figure 2. helps to keep ripple low. Switching power supplies should be used with caution. EMI/RFI filters such as BNX()()2 made by Murata/Erie Company. Canada give good results with switching supplies. If external gain adjust is not used, the source impedance driving the ADC601 should be low (such as the output of an op amp) to avoid gain errors due to the relatively low input impedance of the ADC601. INPUT RANGE SCAUNG The analog input can be scaled to an appropriate input signal range by proper pin connections to the NO converter. Connect input signals as shown in Table I. Input Range Output Code CannIct PInZ9 To CClllIIICI Gain ±IOV BOB 26 Signal CCIIIIIICI Pin 24 To CannIct Pin 25 To Yes 40Qresislcrin series wiIh inpuI signal Gail AdjUSI PoIel1lllmel8r 110 Inpul Signal Anatlg Common Yes Gain Adjust PoIenIiomeIer 100 resistor In series will inpuI signal 110 Anatlg Common InpuI Signal GainMiUSI PoIemlomel8r 100 resisIcr In series wiIh input signal Adjust or BTC' ±5V BOB 26 or BTC' OlD-IOV csa Anatlg Common Yes If the source impedance is not low, a buffer amplifier can be added between the input signal and the ADC601 inputs. BIPOLAR OFFSET CURRENT The bipolar offset current provided in the ADC601 on pin 29 is for use only in bipolar operation where pins 26 and 29 are connected together. Pin 29 should be grounded for unipolar operation. To prevent noise interference, this output should not be used for any other purpose; make no other connection to pin 29. OUTPUT DRIVE All ADC60l data outputs will drive two standard TTL loads or 10 low-power Schottky TTL loads. If long digital lines must be driven, external logic buffers are required. The clock output is sensitive to capacitive loading and should be buffered if high capacitive loads are being driven. PARALLEL AND SERIAL OUTPUT Parallel and serial output may be used simultaneously, however proper buffering is essential. This will avoid excessive loading which can interfere with proper operation. , ObIaIned by Inverting MSB (pIn I) externally. TABLE I. ADC601 Input Scaling Connections. Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-91 Ii Ii o u. o a ~ - For Immediate Assistance, Contact Your Local Salesperson POWER DISSIPATION The ADC601 dissipates approximately 1.3W. The package has a junction-to-case thennal resistance (Blc) of 25°C/W and a case-to-ambient thennal resistance (eCA) of 22°C/W in a nonnal convection environment. For operation above +85°C a heat sink is recommended. This should contact the bottom of the ADC60 I for best results. See electrical specification table notes. OPTIONAL EXTERNAL GAIN AND OFFSET ADJUSTMENTS Gain and offset errors may be trimmed to zero using external trim potentiometers as shown in Figures 5, 6, and 7. For sufficient adjustment range, a series resistor must be connected to the analog input pin as specified in Table I. Multiturn potentiometers with 100ppmfC temperature coefficient are recommended for minimum drift. All fixed resistors should be ±1% metal film. If the Offset adjust is not used, pin 26 should be left open except for bipolar operation when it is connected to pin 29. If Gain adjust is not used, the unused input (pin 24 or 25) ,must be grounded to meet specified ,gain accuracy. ' Adjustment Procedure Analog Input Voltage Range ±10V BOBcl1 orBTC'" ±5V Ola-10V BOB orBTC CSB'~ 4.88mV 2.44mV 2.44mV -10V + 112LSB -5V+ 112LSB -10V +3I2LSB -1I2LSB -1I2LSB -5V+ 112LSB +10V-3I2LSB +5V -312LSB -1I2LSB Cede Designation One Least Significant Bit (LSB) Transition Values MSBLSB'" 000... 000 000...001 011 ... 111 100... 000 111 ... 110 111 ... 111 = = NOTES: (1) BOB Bipolar Offset Binary. (2) BTC Binary Two's Complement (Obtained by Inverting the mastslgnlflcant bit (pin 1). (3) CSB 0 Complementary Straight Binary. (4) Voltages given are the nominal value for the transition from the next lower code. TABLE II. Input Voltages, Transition Values, LSB Values, and Code Definitions. +1SVDC 10kntoSOkn Offset Adjust Bipolar ~ For bipolar offset, connect the offset potentiometer and resistors as shown in Figure 5. Sweep the input through zero and adjust the offset potentiometer until the transition from 0 III 1111 III to 1000 0000 0000 occurs at -II2LSB. For gain, connect the gain potentiometer as shown in Figure 6. Sweep the input through the end point transition voltage, which should cause an output transition from 000 ... 000 ... to 000 ... 001. Adjust the gain potentiometer until this transition occurs at the correct end point transition voltage as given in Table II. OPTIONAL CLOCK RATE CONTROL The clock is factory-set for a conversion time between BOOns and 900ns. By use of the optional clock rate control shown in Figure 7, the 12-bit conversion time can be typically adjusted down to 700ns. It can also be used, if desired, to get slightly higher speed or to assure maximum conversion time at elevated temperature. If the clock rate control is not used, Pin 19 should be left open or bypassed with lOOpF capacitor. Conversion time versus clock rate control voltage is shown in the Typical Perfonnance Curves. More positive voltage on clock rate control increases speed of conversion. Voltage of less than I V may cause the clock to stop. \7 100ka: Co Refer to Table II for LSB voltages and transition values. For unipolar offset, COnnect the offset potentiometer and resistorsas shown in Figure 5. Sweep the input through the' end point transition voltage, from III.. .110 to Ill.. .111. Adjust the offset potentiometer until the actual end point transition voltage occurs at -1/2LSB. Unipolar :"6~IY" 29"6~IY": 26 mparator In -15VDC FIGURE 5. Optional Offset Adjust. 40n Input ) Signal (a) IW J Lf 25 10Vln 10n Input ) Signal (b) 24 20Vln 1OOnGain Adjust 1# 2S 10Vln 200n Gain Adjust J Lf 24 20VIn FIGURE 6. Optional Gain Adjust: (a) ±IOVBipolar Operation, (b) ±15V Bipolar or 0 to -IOV Unipolar Operation +1SVDC ~1~~~-------------19 ClOCk Rate Adjust" Clock Rate Control 2.49kn FIGURE 7. Optional Clock Rate Control. 9.2-92 Burr-BrownIe Data Book Supplement, Vol.33b Or, Call Customer Serllice at 1·800·548·6132 (USA Only) 1. When power is first applied. the status of the ADC601 will be undetermined. A convert command must be applied to initialize the ADC601. EXTERNAL SHORT CYCLE The ADC601 may be short-cycled for fewer bits of resolution at faster conversion speeds. The short cycle circuit (Figure 8) works by having the 74LS 165 shift register count the clock pulses out of the ADC which correspond to the ADC bit becoming valid. The shift register will output a negative going pulse when the progmmmed 74LS165 input is shifted to the serial output Q-not. The negative pulse then resets the R-S flip/flop to a low and brings convert comand low. thus stopping the ADC conversion. At the time the ADC stops converting. status goes low which initiates a pamllel load to the shift register. thus progmmming it for the next conversion. The R-S flip/flop made from the 74LSOO nand gates and the other 2 nand gates act as gating for the reset pulse from the shift register. For short-cycling from 9 to 11 bits, cascade two 74LS165s together. 2. The convert command must be low at least sOns prior to the rising edge that starts a conversion. 3. The clock runs continuously when the initial convert command goes high and whenever the convert command is high thereafter. It does not run when convert command is low. The 74LSI65 shift register is progmmmed on inputs A-G to short cycle the ADC60 I on a given bit. For the circuitshown, input A will short cycle the ADC on bit 7. input B on bit 6. etc to input G short cycling on bit 1. All shift register inputs should be tied to GND except the input corresponding to the desired short-cycle bit. which should be tied high. To disable short cycling completely. tie all shift register inputs to ground. I 5. Parallel Output Data: The successive approximation register (SAR) is reset after the leading edge of the first clock period in the conversion cycle. The MSB is set to logic "0" and all other bits are set to logic "1". The bits are determined in succession starting with the MSB, Bit I, as shown in Figure 9. Each bit will be valid after its corresponding clock pulse. ~ 6. Status goes high after the rising edge of the first clock pulse and goes low after all 12 bits are valid. TIMING CONSIDERATIONS 7. Bit 12 will become valid before status goes low; a new conversion may be initiated anytime after the output data has been read. 8. The converter may be restarted during a conversion. If a convert command is held at zero for a minimum of sOns. the SAR will be reset and a new conversion will start on the next rising tmnsition regardless of the state of the converter prior to the convert commands being received. The following are some important points to consider on the ADC601 timing. The times given are typical unless otherwise noted. Nominal maximum and minimum times are also given in Figure 9. ~ 4. The clock is started by a rising tmosition of the convert command. In most applications the rising edge of the Convert Command may be used to strobe pamllel data out of the ADC601 directly. It is recommended that all outputs are buffered if large capacitive loads are being driven. The timing diagmm (Figure 9) shows the relationship between the convert command. clock and outputs. The digital output word uses positive logic for bipolar operation and complementary logic for unipolar opemtion. IIU Figures 10,11. and 12 are digital oscilloscope displays of the actual pulse shapes and relationships. 8 ur z -ti o -:::»z () I! I! o u oa ~ § C) a c 17 7 +15V 22 14 0 ~ ____________~3~e ~~1~ ADC601 I I I 20 +15V 23 -15V 30 18 cc : ____ !4~~ _____ : FIGURE 8. External Short Cycle Circuit. Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-93 For Immediate Assistance, Contact Your Local Salesperson -.:;:r1-4Convert Command I U -, tReSET II Star! Conversion "N" Serial Out Clock Out Status __ ________________ r ~~I~~~~~~~--------------~",~,------_~~"I~~ "-I --1<:1 ~ U !:I ~I~~~~_~ Data Invalid SYMBOL PARAMETER MINIMUM Clock Period Clock Pulse High Clock Pulse Low Conversion TIme Serial to Clock Out Delay 0 Start to Status High Delay Data Valid to Status Low Delay 0 Convert Command Low 50 CC to First Clock Pulse t" t CPH tCPL tcONV t,e tSBH tasl t~ESET t, "N" Data Valid TYPICAL 100 60 40 850 --J MAXIMUM UNITS ns ns ns ns ns ns ns ns ns 1tlS 5.5 13.0 3.0 400 24 NOTE: logic timing limits: T. = +25°C and +125°C. unless otherwise specified FIGURE 9. ADC60I Logic Timing Diagram. 'I ',. - : 10.75ns : 5 t--' "":"" :!. -..: ' :-:" ':' " ~,<"";",, ~"": ~I'" '\ " 'I • 'I • • • , , , • •••:- ••• ~I ••. :- . . • : {_ •• :• • . . ~ . . . .;•••. ~ . • . .:. . • • •: • • • 'I • • , , • • I ~ 0 ~ • ., 'I ' . 5 " 'I "'" , 'I 'I : : . . . . . . (b) • .,., . 'I 'I ~ ··········1'·········." ........................... .• , 'I • 'I • • , • , 1ii '0 ·········:1···· ..' ····• ... :,.... ~• .... •~ ... ~• .... •~ ... ~• • 'I is :1 ' '1' I••," • • • • • • • • " " " ••• •••• . . . . . :1 :I ' , , , , . 'I ' 'I ' , , , • • · ...:.... ~ I· .. .; .... ; ·1· .. :••.• ~ •... :.....:.... :.... -: > 0 ~ • 'I 'I • 'I 'I ~ ' , " 'I :1 ~ • • CD , f 'I 'I : I TIme (5nsldiv) FIGURE 10. (a) Convert Command, (b) Status. , •• , ..... I" . , , (a) ,, ~ " , '" " I' 1" ., 'I " . ~ . ' ~ ....;...:.; ... :.... ~ .... :··l .. ... ~ ... ~ .... ~ ....: . . : i : . I: I' 'I ' I' , , , · ...;...,. ;. ... ;.... ; -... ;. '1- . ~ .. I·;···· .; .... :- . -..; , ~ "I' • I' " • 'I' " I•••• ' "t" •••••••• ' ", ••••••I ' , ..... , . . . .. • •••••• '1' ,•• , ...... , I' " , 'I' I' , , , "I' • I ' I' I' I' 'I' I' • ••• " • '1' •••• roo ........... , , ............. , ......... , .. . • 'I' ~ , ' . ' " · ...;. ... q'I... .; .... . -I' .. ;.... .... ;.... .... :.....; , " ' I , • "J';""';"" ·.. ·;- .. V:J··r.... ~·· .. ~· ~ .. i·~ .. ·~ .... ;l;N·~ " · ...:- .. - :t .. -:- ... :'l' I . -:- ..." . -. " -;.... -:" .... :- ... -: :: '1'1" l," "';,, ",:,' : ··1·:·····;···· ,. , ......... :. ·t:-···;····;· .. : • ~ ~ "":,, , ,;, , I' l' I' •• ... .;... :r"':-"': 1-' -:.... ~ ... -:.....;. .. .;.....: 'I 'I 'I'" +--f-22.94,- : 24.80 ~ . ns . }:........ :..1·· ns' ~.~ ... ~ ... . ....;•• -I- (a) , o '1' " I' I' • , " " I,' I I' 'I' 'I • I' I' ,.,' : I: " " ....;.. '1';" ." .... ; ... -;..:.. ~ .. i-:" I : , , (b) , ...:, ... ';', ....;, TIme (20nsldiv) NOTE: The Serial Data Output is Synchronized with the Negative Edge of Each Appropriate Clock Cycle. FIGURE 11. (a) Clock, (b) Serial Out. DIGITAL CODES Parallel Data Two binary codes are available on the ADC601 parallel output; straight binary (logic "0" true) for unipolar input signal ranges and bipolar offset binary (logic "1" true) for bipolar input signal ranges. Binary two's complement may be obtained for bipolar input ranges by inverting the MSB. It should be noted that for unipolar input ranges -IOV is full scale. Serial Data (NRZ) ADC60I serial data operation is· guaranteed to match the parallel data. If an optoisolator is used to eliminate ground .connections, buffer the output with an appropriate TTL line driver. It is recommended that all outputs be buffered if large capacitive loads are being driven. Table II shows the LSB, transition values, and code definitions for each possible analog signal range. 9.2-94 Burr-Brown Ie Data Book Supplement, Vol, 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) (SNR) or the more severe signal-to-noise-anddistortion ratio (SIN AD), and intennodulation Distortion (IMD). 5 11----,;..--,........ (a) (b) 011--;.-...... TIme (2nS/div) FIGURE 12. (a) Status. (b) Bit-12 Data. TESTING OF THE ADC601 Careful test fixture design is required to accurately test the ADC601. Proper grounding. correct routing of analog and digital signals and power supply bypassing are crucial in achieving successful results. High-frequency layout techniques and copper ground planes are recommended. ANALOG-TO-DIGITAL CONVERTER TEST TECHNIQUE A very effective way of detennining the DC perfonnance of an ADC is by using the "servo loop method." A block diagram of this technique is shown in Figure 13. This measurement system automatically locates the analog voltage that causes the digital output to alternate between the desired code and the adjacent code. A computer is programmed to place the desired code on the I/O bus which is one input to the digital comparator. The other input to this comparator is the digital output of the ADC. Depending upon the results of this comparison. the integrator is directed to change its output until an equilibrium state is achieved. in where the comparator and the ADC digital wunl~ are equal. Once in equilibrium. the DVM measures the analog input to the ADC and transmits the infonnation to the computer via an IEEE488 bus. The test program checks all the desired code combinations. verifying the perfonnance of the ADC. Test time will range from 10 seconds to several minutes depending on the speed of the test program, sellling time of the DVM. and number of codes to be checked. A typical test setup for performing high-speed FFf testing of analog-to-digital converters is shown in Figure 14. Highly accurate phase-locked signal sources allow high resolution FFf measurements to be made without using window functions. By choosing appropriate signal frequences and sample rates. an integral number of signal frequency periods can be sampled. As no spectral leakage results, a "rectangular" window (no window function) can be used. This was used to generate the typical FFT perfonnance curves shown in the Typical Perfonnance Curves. If generators cannot be phase-locked and set to extreme accuracy, a very low side-lobe window must be applied to the digital data before executing an FFf. A commonly used window such as the Hanning window is not appropriate for testing high perfonnance converters; a minimum four-sample Blackman-Harris window is strongly recommended.(I) To assure that the majority of codes are exercised in the ADC601 (12 bits). a 4096-point FFf is taken. If the data storage RAM is limited. a smaller FFT may be taken if a sufficient number of samples are averaged (ie. a IO-sample average of 512-point FFfs). IMD two-tone testing shown in Figure 15 is referenced(3) to the larger of the test signals fl or f2" Five "bins" either side of peak are used for calculation of fundamental and harmonic power. The "0" frequency bin (DC) is not included in these calculations as it is of little importance in dynamic signal processing applications. DynamIc Performance Definitions I. Signal-to-Noise-and-Distortion(2) Ratio (SINAD): 1010 Sinewave Signal Power gNoise + Harmonic Power (first nine harmonics) 2. Signal-to-Noise Ratio (SNR): 10 log Sinewav~ Signal Power NOIse Power 3. Total Harmonic Distortion (THO): 10 I Harmonic Power (fIrSt nine harmonics) og Sinewave Signal Power 4. Intennodulation Distortion (IMD): 101 og IMD Product Power (RMS sum; to fifth order) S'Ignal Power . Smewave DYNAMIC PERFORMANCE TESllNG The ADC601 is a very high perfonnance converter and careful attention to test techniques is necessary to achieve accurate results. Spectral analysis by application of a fast Fourier transfonn (FFf) to the ADC digital output will provide data on all important dynamic perfonnance parameters: total harmonic distortion (THD). signal-to-noise ratio Burr-BrownIe Data Book Supplement, Vol. 33b 5. Spurious-Free Dynamic Range (SFDR): 10 10 Sinewave Signal Power g Largest Power Product 9.2-95 IIU Ii:IU = 8 ~ ur z -otc u -z ~ :E :E o . o a ~ u - For Immediate Assistance, Contact Your Local Salesperson FIGURE 13. Servo Loop Ana10g-to-Digita1 Tester. HP3325A Frequency Synthesizer n +2.8V -.J l.J +O.2V Convert Command o Phase-Locked HP3325A Frequency Synthesizer ADC601 and SHCS04 TTL Latches 74LS574 HP330 Series 9000 Computer FIGURE 14. Block Diagram of FFT Test for THO, SNR, and SINAD. HP3325A Frequency Synthesizer n +2.8V -.J l.J +0.2V Convert Command o Phase·Locked ADC601 and SCH804 TTL Latches 74LS574 HP330 Series 9000 Computer FIGURE 15. Block Diagram of FFT Test for Two-Tone IMD. MAJOR POINTS TO CONSIDER Attention to test set up details can prevent errors that contribute to poor test results, Important points to remember when testing high performance converters are: voltage will not overrange the ADC and "hard limit" on signal peaks. Overrange peaks will, however, just result in a constant full-scale digital output. 1. The ADC analog input must not be overdriven. Using a signal amplitude slightly lower than FSR will allow a small amount of "headroom" so that noise or DC offset 2. Two-tone tests can produce signal envelopes that exceed FSR. Set each test signal to slightly less than -6dB to prevent "hard limiting" on peaks. 9.2-96 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) 3. Low-pass filtering (or bandpass filtering) of test signal generaton; is absolutely necessary for THD and IMD tests. An easily buill LC low-pass filter (Figure 16) will eliminate harmonics from the test signal generator. Figures 17 and 18, have bandwidths beyond those required for the ADC601; therefore, they have even beller performance at SookHz. These combinen; are always goo4 additions to high-speed engineering labs. 4. Test signal generaton; must have exceptional noise per- 8. A very low side-lobe window must be used for FFT calculations if generaton; cannot be phase-locked and set to exact frequencies. A minimum four-sample Blackman-Harris window function is recommended.(I) formance (beller than -ISSdBc/Hz) to achieve accurate SNR measurements. Good generaton; together with fifthorder elliptical bandpass filten; are recommended for SNR tests. Narrow bandwidth crystal filten; can also be used to filter generator broadband noise but they should be carefully tested for operation at high levels. S. The analog input of the ADC601 should be driven by a low output impedance SIH amplifier such as a SHCS04. Short leads are necessary to prevent digital noise pickup. 6. A low-noise (jitter) clock signal (convert command) generator is required for good ADC dynamic performance. A poor generator can seriously impair good SNR performance. Short leads are necessary to preserve fast TTL rise times. 7. Two-tone testing will require isolation between test signal generators to prevent IMD generation in the test generator output circuits. An active summing amplifier using an OPA600 is shown in Figure 18. This circuit will provide excellent performance from DC to SMHz with hannonic and intermodulation distortion products typically better than -7OdBc. A passive (hybrid transformer) signal combiner can also be used (Figure 17) over a range of about 0.1 MHz to 30MHz. This combiner's port-toport isolation will be =4SdB between signal generaton; and its input-output insertion loss will be ..(jdB. Distortion will be better than -8SdBc for the powdered-iron core specified. Avoid ferrites. The circuits shown in 9. Digital data may be latched into an external TTL 12-bit register by the status falling edge before the next convert command level. Latches should be mounted on PC boards in very close proximity to the ADC601. Avoid long leads. 10. Do not overload the data output logic. These outputs are designed to drive two TTL loads. IIII Ii:III = 8 S 11. A well-designed, clean PC board layout will assure proper operation and clean spectral response. Proper grounding and bypassing, short lead lengths and separation of analog and digital signals and ground returns are particularly important for high frequency circuits. Multilayer PC boards are recommended for best performance, but a two-sided PC board with large, heavy (20z-foil) ground planes can give excellent results, if carefully designed. = !ii- 12. Prototyping "plug-boards" or wire-wrap boards will not be satisfactory. Request layout application notes from Burr-Brown. Ii I! NOTES: 1. "'On dtc Usc of Windows for Hannonic Analysis with the Dism:IC Fourier Transronn:' Fredric 1. Harris. Proceeding. of the IEEE. Vol. 66, No. I, Janulll)' 1978. pp 51-83. 2. SINAD test includes hannonics whereas SNR docs not include these imponanl spurious products. 3. Ir IMD is n:CcmICCd to peak envclope power. distonion will be oC 6dB bettcr. o -z::» () o() . o -a ~ 50Q 50Q In~ c g ~ Out 10 tums 1124 AWG blfilar wound on Amidon FT SO-43 toroid cora. son @---, I .,] Ou1pUl J 9th Order O.5dB Ripple Tchebychav Low-Pass Filler ... son ~ In Attenuation at 2X cutoff frequency. 9OdB. ~ 49.9n CutoH frequency. -&lB frequency; to convert cutoff frequency to -O.5dB frequency. multiply all LC values by 0.98997. Culoll Freq. C, (MHz) (pF) C. (pi') C. (PF) C, (pF) 5.0 1134.6 17292 1765.6 1729.2 2.5 2269 3458 3531 3458 1.25 4538 6917 706Z 6917 0.625 9077 13.833 14.125 13.833 0.50 11.346 17.292 17.656 17.292 C, r, r, r, r, (pF) ( H) (H) ( H) ( H) 1134.6 2.056 2216 2216 2269 4.11 4.43 4A3 4538 8.23 8.86 8.86 9077 16.45 17.73 17.73 11.346 20.56 22.16 22.16 2.056 4.11 823 BandwIdth: - 1MHz to • 30MHz In-to-In Isolation: • 45dB al5MHz In-to-Out Loss: 6dB II II II II II i() • ~ SOil©! In .,] FIGURE 17. Passive Signal Combiner. 16.45 20.56 FIGURE 16. Ninth-Order Hannonic Filter. Burr-BrownIe Data Book Supplement, Vol. 33b 9.2-97 For Immediate Assistance, Contact Your Local Salesperson lkn lkn In ~n~ Optional transmission line back· termination resistor; Increases Insertion loss by 6dB. 49.9n __ 1_~ 8 I 49.9n I I I L_~_J 50n~ In ~ ~n ~ Oulpul lkn Bandwidth: 00 to 70MHz Insertion La..: OdB FIGURE 18. Active Signal Combiner. 9.2-98 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) BURR-BROWN® ADC603 IE5IE5II 12 III ~ Io u 12-Bit 10MHz Sampling ANALOG-TO-DIGITAL CONVERTER ~ •oZ FEATURES APPLICATIONS • HIGH SPURIOUS-FREE DYNAMIC RANGE • SAMPLE RATE: DC to 10MHz • HIGH SIGNALJNOISE RATIO: 68.2dB • DIGITAL SIGNAL PROCESSING tiu -z • RADAR SIGNAL ANALYSIS • TRANSIENT SIGNAL RECORDING • HIGH SINAD RATIO: 66dB • LOW HARMONIC DISTORTION: -69.6dBc • LOW INTERMOD. DISTORTION: -n.7dBc ~ • FFT SPECTRUM ANALYSIS • HIGH-SPEED DATA ACQUISITION • COMPLETE SUBSYSTEM: Contains Sample/Hold and Reference • IR IMAGING SYSTEMS • DIGITAL RECEIVERS .SIGINT, ECM, AND EW SYSTEMS • 46-PIN DIP PACKAGE • DoC TO +70°C AND-55°C TO +125°C • DIGITAL OSCILLOSCOPES I! I! o . o a ~ u - DESCRIPTION The ADC603 is an high performance analog-to-digital converter capable of digitizing signals at any rate from DC to lO megasamples per second. Outstanding spurious-free dynamic range has been achieved by minimizing noise and distortion. Complete static and dynamic test results are furnished with each KH and SH grade unit at no additional cost. The ADC603 is a two-step subranging ADC subsystem containing an ADC, sample/hold amplifier, voltage reference, timing, and error-correction circuitry in a 46-pin hybrid DIP package. Logic is TIL. Two temperature ranges are available: to +70°C (JH, KH) and -55°C to +125°C (RH, SH). ooe (II) o CD u a c Signal Input Sample! Hold MSB Flash Encoder Digital-to Analog Flash Converter Encoder LSB Digital Error Corrector Digital OuIput (Adder) international Alrparllnduslrlal Park • lIaDlng Address: PO Box 11400 • TUcson, AZ 85734 • Slnet Add...., 6730 S. TUcWI Blvd. • Tucson, AZ 857D6 T81: (602) 746-1111 • Twx: 9111-!l52-1111 • CabIa:BBRCORP • Telax:06U491 • FAX: (6021 8119-1510 • ImmeclIalaProdllCllnfD:(IIOO)548-6132 PDS-86SB Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-99 For. Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL To - +25'C, 10MHz sampling rate, R•• son, ±Vcc. ±1SV, +VDD' = +SV, -Vccs. -5.2V, and IS-minute wannup In convection environment, unless otherwise noted. ADC603KH ADCB03JH PARAMETER CONDmoNS MIN I TYP I MAX INPUTS ANALOG Input Range Inputlmpadance Input Capacitance DIGITAL Logic Family Convert Command Pulse WIdIh TRANSFER CHARACTERISTICS Full Scale SI8II Conversion 1= Conversion Period 9.2-100 +1.25 . DC Logic selectable I. 4.9MHz: 68.3% 01 all Codas 99.7% of all Codes 100% 01 all Codes 1.-9.99MHz· I. = 9.99MHz I. = 8.006MHz f•• 9.99MHz 1._9.99MHz TVP Operating Operating I ±O.1 0.5 0.25 0.3 0.4 Guaranteed ··· · 10M DC " 2 or 3 Convert Command Periods Bits . ·· I UNns 12 V Mn pF . ns 0.8 0.5 I 0.5 0.65 0.75 %FSR'" %FSR LSB LSB LSB LSB ±O.07 ±O.07 ±O.03 ±O.03 %FSR/% %FSR/% %FSR/% o/oFSR/% 10M Semplesls · 0.3 0.75 I 1.25 0.5 0.6 0.9 LSB LSB LSB -72 -«3 -74 -68 dB -68 -61 -65 -69.6 -72.1 -64 -70 -68 dBd" dBc -75 -67 -77.7 -71 dBc 65 67 62 68 66 68.5 dB dB 63 66 67 68 -5 9 66 69· 68.2 70.1 dB dB 70 40 80 50 30 -.20dB Input OdB Input Operating I TTL CompaUble POsitijEdge 1-20 • MAX 60 64 2x Full-Scale Input Logic selectable Logic LO, ""- - -3.2rnA Logic HI, I"" = 16O!1A Data Out to DV Ia. = -6.4rnA, 50% In to 50% Out I ±O.2 I ±O.2 0.75 0.75 0.3 0.4 1 0.5 Guaranteed ±O.03 ±O.04 ±O.O04 ±O.01 IJ.+Vcc ·±10% IJ.-Vcc ·±10% IJ. +VCCI= ±10% IJ.-Vccs·±10% Spurious Free DYnamic Range I = 5MHz (-Q.5dB) Total Harmonic DIS\ortion~'(THD) I = 5MHz (-Q.5dB) 1= 100kHz Two-Tone Intermodulation Distortion"'.' 1= 2.2MHz (-6.5dB) I = 2.SMHz (-6.5dB) Slgnal-to-Nolse and Distortion (SINAD) Ratio 1= 5MHz (-Q.5dB) I = 100kHz (-Q.5dB) Signal-to-Noise Ratio (SNR) I = 5MHz (-Q.5dB) I- 100kHz (-Q.5dB) Aperture Delay 11me Aperture Jitter Analog Input Bandwld1h (-3dB) Small Signal Full Power Overload Recovery 11me EOC Delay 11me Trl-StaIB EnabkllDisabie 11me Data Valid Pulse WIdth POWER SUPPLY REQUIREMENTS Supply Voltages: +Vcc -Vcc +VOOt -VOO2 Supply Currents: +Icc -Icc +1"., -I_ Power Consumption 10 I. 200Hz DC I. 200Hz I • 200Hz: 68.3% 01 all Codes 99.7% 01 all Codes 100% 01 all Codes CONVERSION CHARACTERISTICS Sample Rate Plpallne Delay OUTPUTS Logic Family Logic Coding Logic Levels -1.25 1.5 5 No Missing Codes Power Supply Rejection DYNAMIC CHARACTERISTICS Differential Unaarity Error I 12 RESOLU11ON ACCURACY Gain Error InputOHse\ Inlegral Unearity Error Differential Unearity Error MIN ·· ·· · +9 20 ns psnns 140 MHz MHz ns TTL Compatible Two's Complement or Inverted Two's Complement +0.3 +0.8 0 +0.3 +0.5 0 +3.5 +2A +3.5 +2.4 +5 +5 5 35 5 35 100 37 100 37 20 45 20 60 60 45 +14.25 -14.25 +4.75 -4.95 +15 -15 +5 -5.2 +60 -60 +280 -565 6.1 +15.75 -15.75 +5.25 -5AS +14.25 -14.25 +4.75 -4.95 +15 -15 +5 -5.2 +60 -60 +280 -565 6.1 +15.75 -15.75 +5.25 -5A6 +80 -60 +330 -630 V V ns ns ns V V V V rnA rnA rnA rnA W Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS) ±V"". ±15V, +VDO' • +5V, -V.... -5.2V, R". 50n, 15-mlnute warmup, and Tc • TlIN to T""" unless otherwise nOted. ADC603JH MIN TEMPERATURE RANGE Specilicatlon ""'''DA''V Gain Error Input Offset Inlegral unear Error DIHerenllal Unearlty Error No Missing Codes Power Supply Rejection T_ DYNAMIC' Differential Unearlty Error Spurious Free Dynamic Range'" Total Harmonic Dlstortlon~' I • 5MHz (-o.5dB) I. 100kHz Two-Tone Intermodulation Distortion I. 2.2MHz (-6.5dB) I • 2.5MHz (-6.5dB) SIgnal-to-Noise and Distortion (SINAD) Ratio I. 5MHz (-o.5dB) I. 100kHz (-o.5dB) Slgnal·to·Nolse Ratio (SNR) 1= 5MHz (-o.5dB) I. 100kHz (-o.5dB) Aperture Delay Time Aperture Jilter Analog Input Bandwidth (-3dB) Small Signal Full Power Oveiload Recovery Time OUTPUTS logic Levels EOC Deley Time TrI-5la1e Enable/Disable TIme Data Valid Pulse Width TYP ±C.4 ±C.4 0.75 0.4 0.5 0.75 3uarantee ±C.D4 ±C.05 ±C.0D4 ±C.D2 &+Vcc ·±IO% &-V",,_±IO% & +V"",. ±10% &-V.... ±10% 0.5 1 1.25 I TYP ·· 1.5 1 0.6 0.3 0.4 0.6 I MAX UNRS · OC 1 0.5 1.25 0.6 0.75 1 %FSR %FSR LSB LSB LSB LSB ±C.08 ±C.08 ±C.05 ±C.05 %FSRI% %FSRI% %FSRI% %FSRI% 10M Samplesls 3u~tee ·· DC ~ 1.5 -60 Is ·9.99MHz -67 -69 -58 -62 -68.8 -69.5 -62 -67 dBc dBc Is. 8.006MHz -72 -64 -74.4 -68 dBc ~ LSB LSB LSB dB I IIII IiIII ~ 0 U a :c. II) Z 0 -= U Z :::) :IE :IE 0 . U I. =9.99MHz I•• 9.99MHz 57 65 62 66 60 64 67 68 -6 10 40dBInput DdB Input 2X Full·Scale Input logic LO, I", a -3.2mA logic HI, lcoo a 160pA Data DUlto DV Ia. • -6.4mA, 5D% In to 50% Out Operating -I"" +1001 II) -I"", (1) Power Consumption MIN 0.4 0.6 0.7 -72 70 40 60 0 +2.4 5 +0.3 +3.5 20 45 35 42 POWER SUPPLY Supply CurrenlS: +Icc ADC603KH MAX 10M DC I. 4.9MHz: 68.3% 01 all Codes 99.7% 01 all Codes 100% 01 all Codes I. 5MHz H).5dB) I +70 O 1.2OOHz DC I-200Hz I • 200Hz: 66.3% 01 all Codes 99.7% 01 all Codes 100% 01 all Codes CONVERSION ..n ........ ' g>,,, , ''''' Sample Rale I OperaUng +65 -61 +285 -570 6.1 61 64 65.4 64 66 66 69.5 dB dB 66.5 ·· dB dB ns psrms +10 2D +0.8 +5 100 60 ·· · · · ·· ·· ·· ·· · +0.5 · ·· +80 -80 +333 -630 V V ns ns ns . mA mA mA mA W • Same specifications as ADC803JHlRH. NOTES: (1) FSR: Ful~Scale Range. 2.5Vp-p. (2) UnllS with tested and guaranteed distortion speciflcallons are available on special order-lnqulre. (3) dBC = level referred to carrier-Input signal. DdB); F • Input frequency; F. _ sampling frequency. (4) IMD Is referred to the larger 01 the \WO Inpullesl signals. II referred to the peak envelope signal (-OdB), thelntermodulation products wiD be 6dB lower. (5) SFDR tested at temperature lor K grade only. (6) Pins 3 and 30 (analog) typically draw 80% 01 the total +5V current. Pin 21 (digital) typically draws 20%. (7) Pin 6 (analog) typically draws 45% 01 the total-5.2V currenL Pin 31 (digital) typically draws 55%. Burr-Brown Ie Data Book Supplement, Vol, 33b . :::) MHz MHz ns 50 30 -a 0 9.2-101 CII) 0 CD U a C For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL To. +25"C, 10MHz IIIIft1IIInII rate, R,.. 600, :IoV... :Io15V, +V.... +5V, -V.... -6.2V, and 15-mInUle _up In convacdon environment, unle8a 0Ih8lWlSa noted. PARAIIErER ·CONDITIONS Full scale V MQ Stall Conversion I. ConV8lSlon Perlod GainEnor ns 10 %FSR'1J %FSR '.2OOHz Input Offset Inlegral linearity Error Dllfenlnllal linearity Enor DC 200Hz ,. 200Hz:68.3% 0' all codes 99.7% 01 an codes 100% 01 all codes 'a LSB . ·LSB lSB LSB No MIssIng Codes Power Supply Refection LSB LSB LSB Torat Hannonlc ,. 5MHz HI.5dB) 100kHz Two-Tone t_2.2MHz '.2.5MHz ~ dBc:l'l dBc -71 dBc -64 'a -77.7 62 64 66 66.5 64 66.2 70.1 66 70 40 90 . dB dB +9 dB dB ns 20 psnna MHz MHz 50 30 140 ns V V ns +V.. -V.. +V.., -V... Supply Currents: +t.. OperaUng -14.25 +4.75 -4.95 Operating -15 +5 -5.2 +60 -15.75 +5.25 -6.46 -14.25 +4.75 -4.95 -15 +5 -6.2 +60 -15.75 +5.25 -6.46 +90 -60 -1330 -I.. -60 -60 +t... +260 -I..,. -665 +290 -665 6.1 6.1 -e3O V V V V rnA rnA rnA rnA W • Same specllicalions 9.2-102 Burr~Brown ICData Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS) ±V",,_±15V, Gain Error InputOHset Integral Unear Error Differential Unearlly Error I- 200Hz DC I. 200Hz I. 200Hz: 68.3% Of all codas 99.7% 01 all codas 100% 01 all codes :ID.4 :ID.4 0.75 0.4 0.5 0.75 ±2 ±2 0.6 0.3 0.4 0.6 ±1.5 ±I 1.25 0.8 0.75 I %FSR %FSR LSB LSB LSB LSB No Missing Codas Power Supply RaJact10n IIII Ii:III I0 () a C. In Z CHARACTERIsncS -t; - 0 Total Harmonic Distortion.' I. 5MHz (-Q.5dB) I. 100kHz Two-Tone Intermodulation Distortion I • 2.2MHz (-6.5dB) I • 2.5MHz (-6.5dB) Signal-1o-Nolse and Distortion (SINAD) Rallo I • 5MHz (-Q.5dB) I • 100kHz (-Q.5dB) Signal-to·NoIse 1.5MHz I. ApeI\Ure dBc dBc dBc U Z ~ •• . 0 dB dB dB dB 68 69.5 +10 20 ns psrms () -a 0 ~ C MHz MHz 50 30 ns 20 +0.3 +0.8 +3.5 35 42 45 +5 V V 100 60 ns ns ns +0.5 +65 +80 -61 +285 -570 6.1 -60 +333 -630 mA mA mA mA w • Sarne (2) Units with tested and guaranteed distortion spacll1c61Ions are available on spacIaJ ordar-lnqu1re. (3) dBC .Ieval F•• sarnp1lng frequency. (4) IMD Is ralarred to the 1arger 01 the IWO Input test signals. II referred to the will be 8dB lower. Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-103 C') 0 CD () a C For Immediate AS$istance, Contact Your Local Salesperson MECHANICAL H Package - Metal and Ceramic 1-'- - - A ----·11 24l 46 I r DIM A B C 0 J F B Pin 1 deslgnalor marked on bottom H K L M ~-;-~23 N , I 1----1 C f-l-tnnnnnnnTn~ ~[ t H- 1- FJ L -IL 0 SlandoH (4 PI) Se:ung Plane PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Common (Case) NC +VIlO' (+5V) Analog. SlHOu1 AlDin -V_(-5.2V) Analog NC NC Blll(MSB) BII2 BII3 BII4 BII5 BII6 BII7 BII8 BII9 Blll0 Bllll Bit 12 (LSB) +VIlO' (+5V) Dlgllal Data Valid Output Common (Digital) 9.2-104 I f MILUMETERS INCHES MAX MIN MAX 2.420 60.20 61.47 1.560 1.610 39.62 40.89 .200 .260 5.08 6.60 .018 Oia BASIC 0.46 Oia BASIC .100 BASIC 2.54 BASIC 0.75 .115 1.91 2.92 .150 .190 3.81 4.83 1.300 BASIC 33.02 BASIC 10" 10" .040 .060 1.02 1.52 MIN 2.370 NOTE: Leads In 1rUe poslllon wllhln 0.01" (O.25mm) R ar MMC al seating plane. Pin numbers . shown for reference only. Numbers may not be marked on package. - I M....t-' I-L~ ORDERING INFORMATION 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 Common (Analog) Analog Signal In +Vcc (+15V) Analog -Vee (-15V) Analog NC NC NC' DNC DNC Gain Adjusl Offsel Adjusl Common (Analog) +Vcc (+15V) Analog -Vee (-15V) Analog Common (Analog) -VD02 (-5.2V) Digital +V"'" (+5V) Analog 1 Pipeline Dalay Selecr o Pipeline Dalay Selecl Output logic Invert Common (DIgIlal) Tri-St8te ENABLE Convart Command In ADC603 () H BaslcM~alNumber------------------==r---" T Perfonnance Grado Coda - - - - - - - - - - - - - - - - - - -.... J, K: 0"0 to +7O"C Case TemparalUre R, S: -55"0 to +125"0 Case Temperature P~eCoda---------------------------~ H: Metal and Caramlc ABSOLUTE MAXIMUM RATINGS ±Vcc ;...............................................................................................±16.5V +V.., ................................................................................................... +7V ~~·i;;p;;i·:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;,~ logic Input ...........................................................................-o.5V to +VDOt Case Tamparature ......................................................................... +125"0 Junction Temperature .................................................................... +165"C Storage Temperature ...................................................... -65"C 10 +165°C srrasses above these ratings may pennanantly damagelha device. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) TYPICAL PERFORMANCE CURVES ±Vco= ±15V, woo, = +5V, -V"",= -5.2V,I\= 50n, 15-mlnute warmup, and Tc= +25"C, unless olherwlse nOled. All plots are 4096 point FFTs. , ,, ,, TWO-TONE IMD vs TEMPERATURE SIGNAL-TO·NOISE RATIO vs TEMPERATURE 74 ~72 ~ a: , " -668 ., i i~~O ~~~+-+-+-+-~~~9-~~-r~ I--I--I--f--f--f--f-~-::I;;.'"'F-'/-t--t--t-+-+--I 'c~ 100kHz 70 -78 ~ 'c~ 5~HZ z 66 £ -76 ~~-I-+""T~-r-r-+-+-I-I-I-II-I--I ~ -74 ~t-t-t-t-I-II-H ',.2.2MHz I-~ .go U)64 = 2.5MHz •_ ' ......PLE = 8.006MHz " -72 .......---'---',---'--' '"-'"-'"-i--i--&......Ji--&......J&......J1 -70 62 -50 -74 o o Case Temperature rC) 50 75 25 Case Temperature ("C) TOTAL HARMONIC DISTORTION YS TEMPERATURE ANALOG INPUT BANDWIDTH -25 25 50 75 100 ~O 125 1-1-- '2 -25 100 125 - ,, - m0 8. -1 ••o . u :s! o~ t~ E -50 o -7 ~ ~2 -25 0 25 50 75 100 125 Case Temperatun, ("C) Burr-Brown Ie Data Book Supplement, Vol. 33b ur z ~ i~ 8l ~ U Z ~-2 'c=5MHz u - - E- Io o !; 2 iii 1 I - ~.. ~ lbJ~t:;.:, 'c= 100kHz I!III Ii: 0.1 10 100 Frequency (MHz) 9.2·105 -a ~ For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES ±Vco = ±15V, +V00. = +5V, -v002 = -5.2V, R,,= SOO, 10MHz sample rate, 1&-mlnulO warmup, anclTe = +25"0, unless otherwise noted. All plots are 4096-polnt FFTs. 5MHz HARMONIC DISTORTION 100kHz HARMONtC DISTORTION 0..,.....--------------------------, O~----------------------------, -10 -10 A1iased Harmonics Ie -o.4dB 21e -7B.4dB 31e -80.9 ------------------t--, Data Valid TIH Command l Signal Input NO CONVERTER Gain Adjust FIGURE I. ADC603 Block Diagram-A 1\vo-Step Subranging Architecture. Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-107 - a ~ For Immediate Assistance, Contact Your Local Salesperson Internal timing circuits (ECL logic is used internally) supply all the critical timing signals necessary for proper operation of the ADC603. Some noncritical timing signals are also generated in the digital error correction circuitry. Timing signals are laser-trimmed for both pulse width and delay. EeL logic is used for its speed, low noise characteristics and timing delay stability over a wide range of temperatures and power supply voltages. Basic timing is derived from the output of a three-stage shift register driven by a synchronized 20MHz oscillator. The convert command pulse is differentiated to allow triggering by pulses from as narrow as IOns to as wide as 80% duty cycle. The ADC603 timing technique generates a variable width StH gate pulse which is determined by the conversion command pulse period minus a fixed 67ns AOC conversion time. AOC603 conversion rates are therefore possible somewhat above the 10MHz specification, but StH acquisition time is sacrificed and accuracy is rapidly degraded. Converters with guaranteed operation at 10.24MHz sample rate are available on special order. The output of the MSB and LSB encoders are read into separate 7 -bit latches. The latched MSB. data, along with the latched LSB data, is then read into a 14-bit latch after the leading edge of the LSB strobe and before being applied to the adder, where the actual error correction takes place. These latches eliminate any critical timing problems that could result when the converter is operated at the maximum conversion rate. The function of the digital error correction circuitry is to assemble the 7-bit words from the two flash encoders into a 12-bit output word. A data valid (OV) pulseis also generated which is used to indicate when output data can be latched into an external register. This OV pulse is delayed 6ns after the output data has settled to allow sufficient set-up time for an external TTL data latch. A high-speed latch such as a 74F174 is recommended. The 14-bit register output is then sent to a 12-bit adder where the final data output word is created. The MSB data forms the HP3325A Frequency Synthesizer 0-l.ocked HP3325A Frequency Synthesizer n most significant seven bits of a 12-bit word, with the last five bits being assigned zeros. In a similar fashion, the LSB data from the least significant bits forms the other input to the adder, with the first five bits being assigned zeros. As two 12bit words are being added, the output of the adder could exceed 12 bits in range; however, the final data output is only a 12-bit word, so a means of detecting an overrange is included to prevent reading erroneous data. The converter data output is forced to all ones for a full-scale input or overrange. The data output does not "roll-over" if the converter input exceeds its specified full-scale range of ±1.25V. DISCUSSION OF PERFORMANCE DYNAMIC PERFORMANCE TESTING The AOC603 is a very high performance converter and careful attention to test techniques is necessary to achieve accurate results. Spectral analysis by application of a fast Fourier transform (FFT) to the ADC digital output will provide data on all important dynamic performance parameters: total harmonic distortion (THO), signal-te-noise ratio (SNR) or the more severe signal-to-noise-and-distortion ratio (SINAO), and interrnodulation distortion (IMO). A typical test setup for performing high-speed FFT testing of anaIog-to-digitai converters is shown in Figure 2. Highly accurate phase-locked signal sources allow high resolution FFT measurements to be made without using window fum:tions. By choosing appropriate signal frequencies and sample rates, an integral number of signal frequency periods can be sampled. As no spectral leakage results, a "rectangular" window (no window function) can be used. This was used to generate the typical FFT perfoimance curves shown on page 5. If generators cannot be phase-locked and set to extreme accuracy, a very low side-lobe window must be applied to the digital data before executing an FFT. A commonly used window such as the Hanning window is not appropriate for testing high performance converters; a minimum four-sample Blackman-Harris window is strongly recommended.(1) To +2.8V -1 L.J +O.2V Convert Command ADC603 Under Test TIl latches 74F174 HP330 Series 9000 Computer FIGURE 2. Block Diagram of FFT Test for THO, SNR, and SINAO. 9.2-108 Burr-Brown Ie Data Book Supplement. Vol. 33b or,Call Customer Service at 1·800·548·6132 (USA Only) 1. The ADC analog input must not be overdrlven. Using a signal amplitude slightly lower than FSR will a1\ow a small amount of "headroom" so that noise or DC offset voltage will not overrange the ADC and "hard limit" on signal peaks. assure that the majority of codes are exercised in the ADC603 (12 bits). a 4096-point FFT is taken. If the data storage RAM is limited. a smaller FFT may be taken if a sufficient number of samples are averaged (i.e., a IO-sample average of 512point FFTs). 2. Two-tone tests can produce signal envelopes that exceed FSR. Set each test signal to slightly less than -6dB to prevent "hard limiting" on peaks. 3. Low-pass filtering (or bandpass filtering) of test signal generators is absolutely necessary for THD and IMD tests. An easily built LC low-pass filter (Figure 4) will eliminate harmonics from the test signal generator. Dynamic Performance Definitions I. Signal-to-Noise-and-Distortion(l) Ratio (SINAD): 10 log Sinewave Signal Power Noise + Harmonic Power (first 9 harmonics) 4. Test signal generators must have exceptional noise performance (better than -155dBC/Hz) to achieve accurate SNR measurements.(') Good generators together with fifthorder elliptical bandpass filters are recommended for 2. Signal-to-Noise Ratio (SNR): 10 log Sinewave Signal Power Noise Power In~ 10 log Harmonic Power (first 9 harmonics) Sinewave Signal Power 9th Order O.5dB Ripple Tchebychev Low·Pass Filler 10 log Highest IMD Product Power (to 5th order) Sinewave Signal Power Attenuation at 2X QllOff frequency s 9OdB. CU11IfF FREQ. C, C, Cs C, IMIIzI [pF) IPFI IPFI (pFl 1134.6 1729.2 1765.6 5 2.5 2269 3458 3531 1.25 4538 6917 7062 0.625 9077 13,833 14.125 APPLICATION TIPS Attention to test set-up details can prevent errors that contribute to poor test results. Important points to remember when testing high performance converters are: n S ur z :IE :IE Cutoff frequency = -3dB frequency: 10 convert cutoff frequency to -o.5dB frequency. multiply all LC values by 0.98997. IMD is referenced(3) to the larger of the test signals f, or f2• Five "bins" either side of peak are used for calculation of fundamental and harmonic power. The "0" frequency bin (DC) is not included in these calculations as it is of little importance in dynamic signal processing applications. ..J l.J 8 () 4. Intermodulation Distortion (IMD): HP3325A Frequency SynthesJzer E -o~ -::»z son 3. Total Harmonic Distortion (THD): Iau Ii 1729.2 3<158 6917 13.833 c" L, IJdII L, Lo (J!III La IJIIII 1134. 2.056 2.216 2.216 2269 4.11 4.43 4.43 4538 8.23 8.86 8.86 9077 16.45 17.73 17.73 2.056 4.11 8.23 16.45 1pF) IJ!III FIGURE 4. Ninth-Order Harmonic Filter. +2,8V +D.2V Convert 0-Locked Command ADC603 Under Test TTl Latches 74F174 HP330 Series 9000 Computer FIGURE 3. Block Diagram of FFT Test for Two-Tone IMD. Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-109 o u. o -a 51 For Immediate Ass/stance, Contact Your Local Salesperson lkLl +15V OptIonal 1I'8I1SII11ssion nne back-termlnaJlon resistor; Increases Insertion loss by 6dB. lkll ~1 In ___L_, 52.3n = ~1 : I 49.9n I : I lIeD l _____ .JI ~50D output In = = = ~ 10pF125V + BandwIdth: DC to ~ 70MHz Insertion Loss: OdB Tantalum -15V FIGURE 5. Active Signal Combiner. SNR tests. Narrow-bandwidth crystal filters can also be used to filter generator broadband noise, but they should be carefully tested for operation at high levels. 5. The analog input of the ADC603 should be terminated directly at the input pin sockets with the correct filter terminating impedance (5on or 750), or it should bC driven by a low output impedance buffer such as an OPA675/676, OPA620/621, or OPA600. Short leads are necessary to prevent digital noise pickup. 6. A low-noise Gitter) clock signal (convert command) generator is required for good ADC dynamic performance. A poor generator can seriously impair good SNR performance. Short leads are necessary to preserve fast TIL rise times. 7. Two-tone testing will require isolation between test signal generators to prevent IMD generation in the test generator output circuits. An active summing amplifier using an OPA600 is shown in Figure 5. This circuit will provide excellent performance from DC to 5MHz with harmonic and intermodulation distortion products typically better than -70dBC. A passive (hybrid transformer) signal combiner can also be used (Figure 6) over a range of about O.IMHz to 30MHz. This combiner's port-to-port isolation will be =45dB between signal generators and its inputoutput insertion loss will be =6dB. Distortion will be better than -85dBC for the powdered-iron core specified. Avoid ferrites. 8. A very low side-lobe window must be used for FFr calculations if generators cannot be phase-locked and set to exact frequencies. A minimum four-sample BlackmanHarris window function is recommended.(I) 9. Digital data must be latched into an external TIL 12-bit register by the Data Valid output pulse or by using the convert command pulse (Figures II, 12, 13, and 14). Latches should be mounted on PC boards in very close proximity to the ADC603. Avoid long leads. 10. Do not overload the data output logic. These outputs are designed to drive 2 TIL loads. Do not connect ADC603 9.2-110 10 turns 1124 AWG blfllarwound on Amidon FT 50--43 toroid cora. 49.9D 5~ @-......--.JW----
V "Tantalum 45 Signal Input 46 Analog Common -=- FIGURE 9. Differential Input Buffer Amplifier (Gain =-1 VI V). Burr-Brown Ie Data Book Supplement, Vol. 33b ADC603 ~, Triax Input 6 -=- -">V "Tantalum 45 Signal Input 46 Analog Common -=- FIGURE 10. Differential Input Buffer Amplifier (Gain =- 2VN). 9.2-111 " 0 CD U a cC For Immediate Assistance, Contact Your Local Salesperson ParalielO.OlpF Ceramlcand lpF Tanlalum (All) F E -5.2V -15V +15V +5V + + t-31; -6i-4'2'43"33 Signal +5V QO .------'-1 D1 01 r--"'" 44 .34 30 3 21 11 In In ,----,00 MSB D2 Q2 OJ 74F174 D3 10 Q4 12 15 14 1 35 32 +5V ADC603 26 25 23 -= -= CC DV 24 22 LSB ~IL .. -L. 16 -= 15 16 17 18 19 20 00 QO Dl 01 Q2 OJ 74F174 D3 TILDaIa 0UIput 2 D2 11 13 14 Q4 D5 CC>---~---------------" Q4 as 10 12 15 LSB Hex LaICh AGURE II. Interface Circuit-Digital Output Strobed by Convert Command. Supply connection shown: power supplies and grounds shared by analog and digital pins using common ground plane (recommended circuit). 9.2-112 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) Parallel O,01~F Ceramlcand 1~F Tantalum (All) F E -5.2V -15V +15V +5V CO .----,01 01 r--~02 02 1-31+-l6-42+-43 ....33 44 34 30 3 21 11 j-llL--....I 03 74F174 03 10 04 04 12 OS 05 15 +5V ADC603 32 26 -= MSB I 8 S io DV 35 25 23 'l1 28 29 ~ 16 . - - - - - ' ' - 1 00 s~~al (O.:----=;;,.:~I~n~"-""~';';O';;.;!.;;;;~M~S~B -= Iau +5V + TTLDala ClIJlpul - 15 16 17 18 19 CC DV 24 LSB 20 03 13 14 04 OS i 02 02 22 cc)----' !Cu Ql 74F174 03 Q4 05 10 =IE 12 15 :IE LSB o . o a ~ u Hex latch - FIGURE 12. Interface Circuit-Digital Output Strobed by Data Valid Pulse. Supply connection shown: power supplies and grounds shared by analog and digital pins using connnon ground plane. Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-113 For Immediate Assistance, Contact Your Local Salesperson Nanoseconds Convert Command DalaOu1put Pin 28 s High Pin 29 = High Dala OulpUl Pln28= Low Pin 29 = High ~~i, Validi P<: :X:~i: , Invalid' : DaIaN-3 : Data, Valid 'DataN-2' Invalid : Data, ~~i : ~ I I : Internal SamplelHold Command : I 41'4-t:~ I -S,<,.-l : I I : Valid : , DalaN-l : Valid ' 'DataN-l Invalid: Dala' : , i ~: i~·: I I I I I : : : : : : : I I I : I I : I ! I I I I I IX , Valid DalaN SamD~ ~ Sam~e;lr--~--~,--~--i Hold i~.,...... Hold ,~s+J i Hold I I Invalid: Data' :X:~: tcH (4): : r ?<: :X:~: Valid , DaIaN-2: I I ! I r NOTES: (1) 1,;,. =Delay Ume lrom Convert Command to Invalid Dala. Typical value = 4Ons. Independent of conversion rate. (2) t".. = Delay Ume from Convert Command to Valid Data. Typical value = 93ns. Independent of conversion rate. (3) The SS symbol IndicaleS the portion 01 the wavefonn that will '"stretch our at lower conversion rates. (4) 10.. = Delay Ume from Convert Command to the Intemal hold. Typical value - 60s. Independent of conversion rale. (5) r".., = dala set· up time. This depends on conversion rate and may be calculated by: tosu = t~ -lew FIGURE 13. Convert Command Strobe Timing. Nanoseconds o 20 40 60 80 100 120 140 160 180 200 220 240 260 ++++++++++++-1-+ Convert Command -r~~~i'~~~~~i'~~~~~~ Start Conversion N ' Start Conversion : N+2, ~ tc~L(1) ~: : I I I I• Data Valid Strobe OulpUl I : " I I i : fcOH(2) ~~): : : : 'Valid: Dala N - 1 I : Invalid Data I I I I I I +1':~ • , I : xJ ~~~ Valid: Data N, Invalid, D~1a I: I I I I I I xJ ~~?< Valid Data N + 1 : I : ~~ : SfJ"obe I N+1 I --...J t-t-+ tc~ (5) Inlemal SamplelHold Command I I I : Sfrobe I N tcvO(4) ! ~ ~~~ I • rj'>'J,:1 : Invalid: Data : I I I I• DalaOutput Pin 28 = High Pin 29 = Low Start Conversion: N+l, I I : I I i : , I I ~~ Sample ~~ Sample. r-;---t>~ : Hold ., : c;::=:::,J : Hold : ~ : Hold , --}J , NOTES: (1) """ = Delay Ume from Convert Command to the failing edge of Dala Valid Sfrobe. Typical value = 85ns. Independent of conversion rate. (2) t""., = Delay time from Convert Command to the rising edge of Dala Valid Strobe. Typical value = 135ns. Independent of conversion rale. (3) If Conversion "N" Is the first conversion. then there is no Sfrobe N·l. and the Dala Valid Strobe Signal will simply be high unUl t"",. after the first Convert Command. (4) t ow = delay time from Convert Command to Valid Dala. Typical value = 12Ons. Independent of conversion rate. (5) 10.. = Delay lime from Convert Command to Internal Hold Command. Typical valua = 6ns. Independent of conversion rale. (6) The SS symbollndicales the portion of the wavefonn that will '"streich our at lower conversion rales. FIGURE 14. Data Valid Strobe Timing. 9.2-114 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) 'e: 4.99MHz 'e: 0.009MHz 2.047 2.047 1.535 1.535 1.023 1.023 N" 0.511 N" 0.511 -0.512 :li ;; -0.001 ...;; -0.001 "0 -0.512 "(3 0 12 III J: -1.024 -1.024 -1.536 -1.536 -2.046 -2.046 0 0.256 0.512 0.768 1.024 Ii: E 0 0.256 Sample (kHz) - ~ r------------,=,....------, 1.535 1.535 1.023 1.023 0.511 ;; -0.001 - 1------+--------""*--1 0.768 1.024 ~ -1.024 -1.024 -1.536 -1.536 -2.046 L..._ _ _ _ _ _ _ _ _ _ _ _ _ _J 0 0.256 0.512 0.768 1.024 Sample (kHz) HISTOGRAM TESTING SPECTRUM ANAL VZER TESTING A beat-frequency technique (Figure 17) can be used to view digitized waveforms on an oscilloscope and, with care, this technique can also be used for testing high-speed ADC dynamic characteristics with an analog spectrum analyzer. Burr-Brown Ie Data Book Supplement, Vol.33b IE IE o(,) . o a - FIGURE 15. Digitized Sine Waves (fs = lOMHz). Histogram testing is used to test differential nonlinearity of the ADC603. This system's block diagram (the same for FFT testing and waveform digitizing) is shown in Figure 2 and histogram test results for a typical converter are shown in Figure 16. Note that low-frequency differential nonlinearity is I/2LSB and it shows virtually no degradation near the Nyquist limit of 5MHz; there are no missing codes present and the peak nonlinearity does not exceed lLSB. Histogram testing is a useful performance indicator as the width of all codes can be determined. io (,) 8 -0.512 DIGITIZING INPUT WAVEFORMS The response of the ADC603 is illustrated by the digitized waveforms of Figure 15. The 4.99MHz sine wave near the Nyquist limit is virtually identical to much lower frequency sine wave input. The under-sampled 19.999MHz sine wave illustrates the ADC603 's excellent analog input full-power bandwidth. c -ti -:::»z 0.511 ;; -0.001 8 -0.512 -2.046 I-.-=~-------------' 0.256 0.512 0.768 1.024 Sample (kHz) 8 a 'e: 19.99MHz 2.047 . . . . - - - - - - - - - - - - - - - - - , 'e: 9.99MHz 2.047 0.512 Sample (kHz) In this method a test signal is digitized by the ADC603 and the output digital data is latched into an extemallatch by the converter Data Valid output pulse driving a divide-by-N counter. The buffered ECL{fTL level translator latch drives a 12-bit video-speed DAC which reconstructs the digital signal back into an analog replica of the ADC603 input. This analog signal, including distortion products and noise resulting from digitization, can then be viewed on an ordinary analog RF spectrum analyzer. It is important to realize that the distortion and noise measured by this technique include not only that from the ADC603, but also from the entire analog-to-analog test system. Nonlinearity of the reconstruction circuit must be very low to measure a high performance ADC, and this places severe requirements on the ADC, deglitcher, and buffer amplifiers. Using a high-speed video DAC63 in the analog reconstruction circuit allows excellent test circuit linearity to be achieved. Clocking the DAC (demodulating) at felN allows a longer DAC settling time and keeps linearity high in the digital-toanalog portion of the test circuit. Spectrum analyzer dynamic range can be a limiting factor in this method. To increase dynamic range, a sharp notch filter can be used to attenuate the high-level fundamental frequency. Attenuating 9.2-115 SI For Immediate Assistance, Contact Your Local Salesperson DIFFERENTIAL LINEARITY ERROR Is = 100kHz DIFFERENTIAL LINEARITY ERROR Is =5MHz 2 2 1.5 1.5 0.5 m ~ 0.5 m 0 ~ -0.5 0 -0.5 -1 -1 -1.5 -1.5 -,2 -,2 0 819 1638 2457 3276 4095 Code 0 Sampling Rate = 10MHz 619 1638 2457 3276 4095 Code FIGURE 16. lOO!diz a.!ld 5MHz Differentia! Linea.rity. fN"Olch: HP6557A ~ HP;;90A Analyzer :~lte~J 50n Specttum FIGURE 17. Analog-to-Analog Spectral Analysis by Beat-Frequency Techniques. the high-level fundamental signal allows the analog spectrum analyzer to be used on a more sensitive range without genemting distortion products within its front end. Note that even though the signal is demodulated at a frequency of sample rateIN. the distortion products still maintain a correct frequency relationship to the fundamental. While this analog technique can give good performance. it cannot exclude some distortion products unavoidably generated within the analog reconstruction portion of the test system. For this reason. the digital FFT technique is capable of more accumte high-speed analog/digital converter dynamic performance measurements and is the preferred method of testing high-performance AID converters. 9.2-116 TIMING The ADC603 genemtes all necessary timing signals internally. There are two methods for reading output data, offering three selectable levels of data pipeline delay as described below. Convert Command Timing Option (pin 29 :: HI) With this option. the Convert Command signal is used both for initiating a new conversion and for reading valid data from a previous conversion. This method is most useful in synchronous systems where data samples are taken continuously. See Figure 13 for timing relationships. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) Pin 28 is used to control the amount of pipeline delay. If pin 28 is held LO, then output data "N - 2" will be valid on the rising edge of Convert Command "N:' If pin 28 is held HI, then output data "N - 3" will be valid on the rising edge of Convert Command "N:' These timing relationships are valid at any conversion rate up to IOMHz. At rates approaching IOMHz, however, the data setup time before the rising Convert Command edge may become as short as 6ns. Therefore, the use of high-speed TIL latches such as the 74F174 hex flip-flop is recommended to capture the data. If slower latches must be used, then the setup time can effectively be improved by adding several nanoseconds of delay between the Convert Command and the latch clock signal. Data Valid Timing Option (pin 29 =LO) With this option, data from conversion "N" becomes valid after a fixed delay from the rising edge of Convert Command "N:' The delay is approximately 135ns, at which time the Data Valid strobe signal will rise. This signal may be connected directly to the clock input of the user's data latch. See Figure 18 for timing relationships. Pin 28 must be left HI at all times when using the Data Valid timing option. The advantages of this method are that no subsequent conversions are required in order to read the data, and the data is available as soon as possible after the start of conversion. Therefore, the Data Valid option is most useful in systems where the ADC may be operated asynchronously, or where the very first data latch output after power-up must represent a valid conversion. Note that because the delay is fixed at approximately 135ns independent of conversion rate, the Data Valid pulse will overlap into the next conversion at rates. above 7.4MHz. This does not preclude proper operation at any rate up to 10MHz. DATA OUTPUT NOTES: I. FAST'" App/lcalions Handbook, 1987. Fain:hild Semiconductor Corp. 2. Fairchild Advanced CMOS Technology, Technology Seminar Notes. 1985. 3. "Impedance Matching Tweaks Advance CMOS IC Testing", Gerald C. Co., Ekctronlc Design, April, 1987. 4. "Grounding for Electromagnetic Compatibility'" Jen)' H. Boogar. Des/gn News. 23 February, 1987. OFFSET AND GAIN ADJUSTMENT The ADC603 is carefully laser-trimmed to achieve its rated accuracy without external adjustments. If desired, both gain error and input offset voltage error may be trimmed to zero with external potentiometers (Figure 23). Trim range is typically 2%; large offsets and gain changes should be made elsewhere in the system. Using an input buffer amplifier allows a convenient point for injecting large offset voltages and making wide gain adjustments. If offset and gain trim is not used, pins 36 and 37 should be left unconnected. THERMAL REQUIREMENTS The ADC603 is tested and specified over a temperature range of O°C to +70°C (1, K grade) and -55°C to +125°C (R, S grade). The converters are tested in a forced-air environment with a 10 SCFM air flow. With a small heat sink (Figure 24) the ADC603 can be operated in a normal convection ambient-air environment if submodule case temperature does not exceed the upper limit of its specification.(l) High junction temperature can be avoided by using forcedair cooling, but it is not required at moderate ambient INPUT VOLTAGE Output logic inversion can be accomplished by programming pin 27. Binary Two's Complement or Inverted Binary Two's Complement output data formats are available (Table II). The ADC603 output logic is TIL compatible. The tri-state output is controlled by ENABLE pin 25. For normal operation, pin 25 will be tied LO. A logic HI on pin 25 will switch the ouput data register to a high-impedance state (Figure 20). Output OFF leakage current IOZL and IDZII will be less than 50JIA over the converter's specified operating temperature range. Tri -state output should be isolated from noisy digital bus lines, since the noise can couple back through the OFF data register and create noise in the ADC. (Exact Csnter of Code) +FS (+1.25V) +FS -ILSB (+1.2494V) +FS -2LSB (+1.2488V) +3I4FS (+0.9375V) +II2FS (+D.625y) +1I4FS (+D.3125V) +tLSB (+StOllY) Bipolar Zero (OV) -ILSB (~10llY) -1/4FS (-ll.3125V) -II2FS (+D.625V) -3/4FS (-ll.9375V) -{FS -1 LSB) (-I.2494V) -FS BInary Two's Complement (BTC) Pln27=LO MSB LSB 100000000000" 100000000000 100000000001 100111111111 101111111111 110111111111 111111111110 111111111111 -000000000000 000111111111 001111111111 010111111111 011111111110 011111111111 MSB LSB 011111111111" 011111111111 011111111110 011000000000 010000000000 001000000000 000000000001 000000000000 111111111111 111000000000 110000000000 101000000000 100000000001 100000000000 DIGITAL INPUTS Logic inputs are TIL compatible. Open inputs will assume a HI logic state; unused inputs may be allowed to float or they may be tied to an appropriate TIL logic level. DATA LATCHED BY CONVERT COMMAND DATA LATCHED BY DATA VAUD STROBE N-1 PIN NUMBER ~ I N-2 28 29 HI HI I LO HI HI LO TABLE I. Pipeline Delay Selection Logic. Burr-Brown Ie Data Book Supplement, Vol. 33b TABLE II. Digital Data Output Logic Coding. ENABLE Input Pin 25 L: P~~O O~ ] Hlgh 37n5 j Impedance [ : V 8 37n5 Fpedance FIGURE 22. Digital Data Tri-State Output. 9.2-117 12 III ~ I 8 ~ io -~ - U Z ••o . ~ u - o a ~ For Immediate Assistance, Contact Your Local Salesperson temperatures. Thermal resistance of the ADC603 package is: 91C 4.8°C{W, measured to the underside of the case. = MIL-STD-883 MElltOO, CONomON SCREEN NOTES: t. "Maximizing Heat Transfer from PCBs", Machine Design, March 26. 1987. Jeilong ClIung. ENVIRONMENTAL SCREENING The inherent reliability of a semiconductor device is controlled by the design, materials, and fabrication of the device ~it cannot be improved by testing. However, environmental screening can eliminate the majority of those units which would fail early in their lifetimes (infant mottality) through the application of carefully selected accelerated stress levels. Burr-Brown offers environmentally screened versions of our standard military temperature range products, designed to provide enhanced reliability at moderate cost. The screening illustrated in Table III is performed to selected methods of MIL-STD-883. Reference to these methods provides a convenient way of communicating the screening levels and basic procedures employed; it does not imply ccnforrna...-"1cc to any other military standards or to any methods of MILSTD-883 other than those specified. Burr-Brown's detailed procedures may vary slightly, model-to-model, from those in MIL-STD-883. SCREENING LEVEL Visual requirements only (par 3.1 through 3.1.8) Intemal Visual 2017 Electrical Test Burr·Brown Test Procedure High Temperature Stor· age (Stabilization Bake) 100S 24hr, +125OC 10 cyctes, -.Q5°C to -125°C Temperature Cycling 1010 Constant Acceleration 2001,A 2000G; Y Axis Only Bum·ln 1015,0 lSOhr, +125°C TJ , No POA Hermetlclty, Gross Leak 1014,C Bubble Test Only, Preconditioning Omitted Final Electrical Burr-Brown Test Procedure Extemal Visual 2009 TABLE III. Optional Screening Row. 3830 51.10 3e:m +5V ADC603 +15V ~+-_45=-t Signal Input ,.---:::::: 10kll AOC603 37 -15V 48 +15V = Analog Common '---:;;:,Okll = -15V I RGURE 19. Optional Gain and Offset Trim. "Tantalum RGURE 21. A Multiplexed-Input Buffer Amplifier (Gain = +16VN), 46·pln package 1 - - - - - - 2.3" - - - , - - - - 1 0.35" 0.35" 1.S" r 1-~---@ O·l ___ +-___________...... Heat sink #0808HS conducts heat lrom bottom 01 package Into copper ground plane. (Mounting screws and nuts not Included with 0808HS.) 0.12" diameter and CSK 82" 0.235" + 0.005" - 0 dlametsr" (2 places) 0.09" "1 I NOTES: 1.Material: S061-T6a1umlnum. 2. Finish: nickel plate. 3. Deburr and break all sharp edges. FIGURE 20 .. Heat Sink Transfers Heat from the DIP Package into a Copper Ground Plane. 9.2-IJ8 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·BOO·54B~6132 (USA Only) BURR - BROWN® ADC604 IElElI IIII Ii: Io u 12-Bit 5MHz Sampling ANALOG-TO-DIGITAL CONVERTER ~ io FEATURES APPLICATIONS • 83dB SPURIOUS-FREE DYNAMIC RANGE • DIGITAL RECEIVERS • SAMPLE RATE: DC to 5MHz • HIGH SIGNAUNOISE RATIO: 68.6dB • RADAR SIGNAL ANALYSIS • FFT SPECTRUM ANALYSIS • LOW HARMONIC DISTORTION: -83dBc • LOW INTERMOD. DISTORTION: -83dBc • RF INSTRUMENTATION • MAGNETIC RESONANCE IMAGING • SWEPT-POWER FFT TESTED (KH) • SIGINT, ECM, AND EW SYSTEMS !iiu- -z ::) III III o u. o a ~ • COMPLETE SUBSYSTEM: Contains Sample/Hold and Reference - • 46-PIN DIP PACKAGE • O°C TO +70°C DESCRIPTION The ADC604 is a high perfonnance 12-bit analog-todigital convener designed for spectrum analysis applications. Outstanding spurious-free dynamic range has been achieved by minimizing noise and distonion. Complete static and dynamic test results are furnished with each KH grade unit at no additional cost. The ADC604 is a two-step subranging ADC sub-system containing an ADC, sample/hold amplifier, voltage reference, timing, and error-correction circuitry in a 46-pin hybrid DIP package. Logic is TIL. This convener is pin-compatible with Burr-Brawn's 12-bit lOMHz ADC603. ...o CD u ~ Signal Input Sample! Hold Rash Dlgltal·to Analog Flash Encoder Converter Encoder MSB LSB Digital Error Corrector (Adder) Digital Output international Airport industrial Park • lIalilng Addr...: PO 1IolI11400 • TUcson, AI 85734 • street Addr...: 6730 S. Tucson Blvd. • Tucson, AI 85706 Tel: (602) 746-1111 • Twx: 911).952-1111 • cable: BBACORP Telex: 6H491 • FAX: (602) .1510 PDS·1052 Burr-Brown Ie Data Book Supplement. Vol. 33b 9.2-119 For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL Te. +25'<:, 5MHz sampling rate, R•• SOO, ±Vee. ±15V, +V•••• +5V, -V"",. -5,2V, and l5-mlnute warmup In con\l8Clton environment, unless otherwise noted. ADC804JH PARAMETER CONDmONS MIN ADC804KH MAX TYP RESOLUTION MIN TYP 12 MAX UNITS 12 Bits INPUTS ANALOG Input Range Input Impedance Input Capacitance DIGITAL logic Family Convert Command Pulse Width Full Scale -1.25 +1.25 1.5 5 Start Conversion t • Conversion Period · · ·· TTl Compatible Positive Edge 1-20 · I . 10 V MO pF ns TRANSFER CHARACTERISTICS ACCURACY Gain Error Input 0IIseI Integral Unearlly Error Dillemntial Unearlty Error No Missing Codes Power Supply Rejection I '=8kHz DC I f=e~H: 0.75 0.5 Guaranteed ±a.03 , = 8kHz: 100% 01 all Codes IJ. +Vcc. ±IO% IJ.-Vcc. ±IO% IJ.+V""•• ±IO% IJ.-V.o,=±IO% ±a.1 ±2 ±2 ±a.2 ±a.2 ±a.04 ±a.004 I I 0.5 0.4 Guaranteed 1.0 ·· ·· ±a.1 ±a.1 ±a.07 ±a.07 ±a.01 CONVERSION CHARACTERISTICS Sample Rate Pipeline Delay ±I · ! . 1 DC 1 5M I, 2 or 3 Convert Command Periods logic Selectable ±a.75 I 0.75 · ··· · %FSR'" %FSR LSB LSB %FSRI% %FSRI% %FSRI% %FSRI% Samplesls DYNAMIC CHARACTERISTICS<" Differential Unearlty Error Harmonic Distortion (HD) , • 2.00MHz (-o.5dB) I = 8kHz (-0.5<18) Two-Tone Intermodulation Distortlon'~ , • 2.20MHz (-5.5dB) , = 2.30MHz (-6.5dB) Spurious-Free Dynamic Range (SFDR) , • 2.00MHz (-o.5dB) 1= SkHz (-0.5<18) Slgnal·to·NoIse Ratio (SNR) , = 2.00MHz (-o.5dB) I = 8kHz (-o.5dB) Aperture Delay Time Aperture Jitter Analog Input BandwIdth (-{ldB) Small Signal Full Power Overload Recovery Time ,. 2MHz: 100% 01 all Codes 0.6 1.5 0.5 1.0 LSB '.=4.99MHz -80 -83 -75 -79 -83 -80 -$ -82 dBc<" dBc '. =4.99MHz -80 -75 -83 -80 dBc ' •• 4.99MHz 75 79 SO 83 '.=4.99MHz 84 65.5 -20 67 70.5 -5 9 40 20 60 30 205 -2OdB Input OdB Input 2x Fun·Scale Input SO 82 83 86 dB dB 65 66.5 68.6 71.5 dB dB ns psrms ·· ··· +20 20 400 ·· OUTPUTS logic Family Logic Coding Logic Levels EOC Delay T1me TrI-5tate Enable/Dlsable Time Data Valid Pulse WIdth Logic Selectable logic "LO" .... = -{l.2mA logic 'HI' I... = 16011A Data Out to DV .... = -6.4mA, 50% In to 50% Out 0 +2.4 .I J I I J Operating -Vee +VODt -V... Supply Currents: +Icc -Icc +1"•• Operating • same specifications as AOC604JH. 9.2,120 +15 -15 +5 -5.2 +15.75 -15.75 +5.26 -5.46 +60 Operating +2S0 -565 6.1 7.0 ··· · MHz MHz ns I I ·· I ·· I · · · -80 -ID02 Power Consumption +14.25 -14.25 +4.75 -4.95 · TTl Compatible Two's Complement or Inverted Two's Complement +O.S+0.3 +0.5 +3.5 +5.0 See TIming Diagram: figure 15 I 37 I 100 I I I See Timing Diagram: figure 15 POWER SUPPLY REQUIREMENTS Supply Voltages: +Vcc ·· ·· ·· ·· ·· ·· · +60 -80 +330 -630 · V V ns V V V V mA mA mA mA W Burr-Brown Ie Data Book Supplement, Vol. 33b SPECIFICATIONS (CONT) ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS) ±v,,= ±15V. +v," = +5V. -v,,,. -5.2V. f\= 50n. 5MHz sampling rate. 15-mlnute warmup. and T, • TU " 10 T...". unlass o!herwlse nolad. Iw ~ ACCURACY Gain Error Input OIIset Integral Unear Error Differential Unearity Error No Missing Codes Power Supply Rejection Differential Unearlty Error Harmonic Distortion (HD) I = 2.ooMHz (-o.5dB) I. 8kHz Two-Tone Intermodulation Dlstortion'~ I. 2.20MHz (-6.5dB) I = 2.30MHz (-6.5dB) Spurious-Free Dynamic Range (SFDR) 1= 2.00MHz (-o.5dB) I = 8kHz (-o.5dB) Signal-IO-Noise Ratio (SNR) 1= 2.ooMHz (-o.5dB) I = 8kHz (-o.5dB) Aperture Delay Time Aperture Jitter Analog Inpul Bandwld!h (-3 I.2mA logic 'HI'. I,., • 160pA Data Qui 10 DV Ia. = -6.4mA, 50% In 1050% Oul Supply Currents: +1" 1.5 %FSR %FSR LSB LSB ±2 ±2 Operating -8 10 77 80 LSB 80 83 dB dB 68 70 dB dB ns psrms +25 20 MHz MHz 60 30 220 ns o +0.5 +2.4 +3.5 +5.0 See F --------------------------------t---, TIH l Command r---------., Digital Output 12 IU Ii:IU ~ 8 ~ Signal •o- Input Z !C() TraclclHold -::»z AID Converter :E :E Gain Adjusl o FIGURE 1. ADC604 Block Diagram-A Two-Step Subranging Architecture. A "remainder" or coarse conversion-error voltage is generated by resistively subtracting the DAC output from the output of the samplelhold amplifier. Before the second (LSB) conversion, the ··remainder" is amplified by a wide band fast-settling two-input amplifier with a gain of 32VN. To prevent overload on large amplitude transients, the active input is switched off to blank the amplifier input from the beginning of the StH acquisition time to the end of the MSB encoder update time. Internal timing circuits (ECL logic is used internally) supply all the critical timing signals necessary for proper operation of the ADC604. Some noncritical timing signals are also generated in the digital error correction circuitry. Timing signals are laser-trimmed for both pulse width and delay. ECL logic is used for its speed, low noise characteristics and timing delay stability over a wide range of temperatures and power supply voltages. Basic timing is derived from the output of a three-stage shift register driven by a synchronized 20MHz oscillator. The convert command pulse is differentiated to allow triggering by pulses from as narrow as IOns to as wide as 80% duty cycle. The ADC604 liming technique generates a variable width StH gate pulse which is determined by the conversion command pulse period minus a fixed 135ns ADC conversion time. ADC604 conversion rates are therefore possible somewhat above the 5MHz specification but S/H acquisition time is sacrificed and accuracy is rapidly degraded. Con- Burr-Brown Ie Data Book Supplement, Vol. 33b . () verters with guaranteed operation at 5.12MHz sample rate are available on special order. The output of the MSB and LSB encoders are read into separate 7-bitlatches. The latched MSB data, along with the latched LSB data, is then read into a 14-bitlatch after the leading edge of the LSB strobe and before being applied to the adder, where the actual error correction takes place. These latches eliminate any critical timing problems that could result when the converter is operated at the maximum conversion rate. The function of the digital error correction circuitry is to assemble the 7-bit words from the two flash encoders into a 12-bit output word. A data valid (DV) pulse is also generated to indicate when output data can be latched into an external register. This DV pulse is delayed 6ns after the output data has settled to allow sufficient set-up time for an external TTL data latch. A high-speed latch such as a 74FI74 is recommended. The 14-bit register output is then senttoa 12-bit adder where the fmal data output word is created. The MSB data forms the most significant seven bits of a I2-bit word, with the last five bits being assigned zeros. In a similar fashion, the LSB data from the least significant bits form the other input to the adder with the first five bits being assigned zeros. As two 12bit words are being added, the output of the adder could· exceed 12 bits in range; however, the final data output is only a 12-bit word, so a means of detecting an overrange is included to prevent reading erroneous data. The converter 9.2-125 o -a ~ For Immediate Assistance, Contact Your Local Salesperson data output is forced to all ones for a full-scale input or overrange. The data output does not "roll-over" if the converter inpui exceeds its specified full-scale range of ±1.25V. DISCUSSION OF PERFORMANCE DYNAMIC PERFORMANCE TESTING ADC604is a very high dynamic range converter and careful attention to test techniques is necessary to achieve accurate results. Spectral analysis by application of a, fast Fourier transform (FFf) to the AOC digital output will provide data on all important dynamic performance parameters: harmonic distortion (HO). signal-to-noise ratio (SNR). spurious-free dynamic range (SFDR). swept power response. and intermodulation distortion (IMD). A typical test setup for performing high-s.,eed FFf testing of analog-to-digital converters is shown in Figure 2. Highly accurate phase. . locked !<;ignat so~!'Ces ano\\' high resclution FFT measurements to be made without using window functions. By choosing appropriate signal frequencies and sample rates. an integral number of signal frequency periods can be sampled. As no spectral leakage results. a "rectangular" window (no window function) can be used. This coherent sampling method was used to generate the typical FFf performance curves shown on page 6. The ratio of the sampling frequency to the signal frequency must be a non-rational number. If generators cannot be phase-locked and set to extreme accuracy. a very low side-lobe window must be applied to the digital data before executing an FFf. A commonly used window such as the Hanning window is not appropriate for testing high performance converters; a minimum four-sample Blackman-Harris window is strongly recommended.(1) To assure that the majority of codes are exercised in the ADC604 (12 bits). a 4096-point FFf is taken. If the data storage RAM is limited. a smaller FFf may be taken if a sufficient number of samples are averaged (ie. a 10-sample average of 512 point FFfs). DYNAMIC PERFORMANCE DEFINITIONS' I. Spurious-free dynamic range (SFOR): sinewave signal power , 10 log h'gh '. or spunous .. I est harmonlc signaI power 2. Signal-to-noise ratio (SNR): 10 log sinewave signal power total noise power 3. Harmonic distortion (HO): highest harmonic power (to ninth harmonic) 10 log sinewave signal power 4. Intermodulation distortion (IMO): highest IMO product power (to fifth order) IOlog , . . I smewave signa power 9.2-126 IMD is referenced to the larger of the test signals fl or f2• not to full-scale range (FSR). The "0" frequency bin (DC) is not included in these calculations as it is of little importance in dynamic signal processing applications. APPUCATION TIPS Attention to test set-up details can prevent errors that contrib,ute to poor test results. Important points to remember when testing high performance converters are: I. The ADC analog input must not be overdriven. Using a signal amplitude slightly lower than FSR will allow a small amount of "headroom" so that noise or DC offset voltage will not overrange the ADC and "hard limit" on signal peaks. Z. 'l\vo-tone tests can produce signal envelopes that exceed FSR. Set each test signal to slightly less than -6dB to prevent "hard limiting" on peaks. 3. Low-pass filtering (or bandpass filtering) of test signal geoemto!S is absolutely nece:;:;a..l- for aCCiiiate tests. Au easily built LC low-pass filter (Figure 4) will eliminate harmonics from the test signal generator. 4. Test signal generators must have exceptional noise performance (better than -155dBc/Hz) to achieve accurate SNR measurementsl4) Good generators together with fifthorder elliptical bandpass filters are recommended for SNR tests. Narrow bandwidth crystal filters can also be used to filter signal generator broadband noise, but they should be carefully tested for low-distortion operation at high signal levels. 5. The analog input of the AOC604 should be terminated directly at the input pin sockets with the correct filter terminating impedance (SOn or 75n) or it should be driven by a very low distortion buffer amplifier with low output impedance, such as an OPA62 I or equivalent. Short leads «I inch) are necessary to prevent digital noise pickup. 6. A low phase noise (jitter) clock signal (convert command) generator is required for good ADC dynamic performance. A poor generator can seriously impair good SNR performance. Short leads are necessary to preserve fast TTL rise times. 7. Two-tone testing will require high isolation between test signal generators to prevent IMD generation in the test generator output circuits. A passive (hybrid transformer) signal combiner can be used (Figure 5) over a range, of about O.IMHz to 30MHz. This combiner's port-to-port isOlation will be ~5dB between signal generators and its input-output insertion loSs will be ..6dB. Distortion will be better than -85dBc for the powdered-iron core specified. Avoid ferrites. 8. A very low side-lobe window must be used for FFr tests if generators cannot be phase-locked and set to exact frequencies to perform coherent sampling measurements. A minimum four-sample Blackman-Harris window function is recommendedl l) 9. Digital data must be latched ,into an external TTL I2~bit register by the Data Valid output pulse or by using the Convert Command pulse (Figures 10 and II). Latches Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) HP3325A Frequency Synthesizer n .J l...J +2.8V +O.2V Convert Command HP3325A Frequency Synthesizer HP330 Sertes9000 Computer ,, , -or- : ___ I _~ Crystal Filter u FIGURE 2. Block Diagram of FFf Test for HD. SNR. SFDR and Swept-Power Test. HP3325A Frequency Synthesizer n .J l...J ~ io , [§D' I IIII ~ ur z +2.8V +0.2V o Convert Command o Locked Analogr---''---, Input HP330 Sertes9000 Computer -~ -:::»z () :E :E 500 o() oa ~ FIGURE 3. Block Diagram of FFf Test for Two-Tone IMD. 50n 500n Out La I C~ I= I 9th Order O.5dB Ripple Tchebychev Low·Pass Filter Attenuation at 2X cutoff frequency D OOdB. Cutoff frequency -3dB frequency; to convert cutoff frequency to frequency. multiply all LC values by 0.98997. BandwidIh: -1 MHz 10 - 30MHz In·to-In IsolaUon: 45dB at 5MHz In·to-Out Loss: 6dB 49.9n SOO In ~ 49.90 49.90 II II II II II • 10 turns #24 AWG blfilar wound on Amidon FT 50-43 toroid core. D ~.5dB Culon c, c, l, I, I, l, (pF) (pF) ( H) ( H) ( H) ( H) 2269 3458 3531 3458 2269 4.11 4.43 4.43 4538 6917 7062 6917 4538 8.23 8.86 8.86 9077 13.833 14.125 13.833 9077 16.45 17.73 17.73 4.11 8.23 16.45 Freq. (MHz) C, C, (pF) (pF) 2.5 125 0.625 c, (pF) 50n©-J.. In -= FIGURE 5. Passive Signal Combiner. FIGURE 4. Ninth-Order Harmonic Filter. Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-127 For Immediate Assistance, Contact Your Local Salesperson should be mounted on PC boards in very close proximity to the ADC604. Avoid long leads. 10. Do not overload the data output logic. These outputs are designed to drive two TIL loads but a lighter load will minimize the amplitude of digital switching transients. Do not connect ADC603 data output pins directly to a noisy digital bus;,use external three-state logic for noise immunity. II. A well-designed. clean PC board layout will aSsure proper operation and clean spectral response!5)(6) Proper grounding and bypassing. short lead lengths and separation of analog and digital signals. and the use of ground planes are particularly important for high frequency circuits. Multilayer PC boards are recommended for best performance. but a two-sided PC board with large. heavy (20z-foil) ground planes can give acceptable results. if it is carefully designed. 12. Prototyping "plug-boards" or wire-wrap boards will NOT be satisfactory. There are no shortcuts. 13. Roatinginputscan minimize ground-loop noise. A simple common-mode choke (balun) shown in Figure 6 and 7 or a differential amplifier (Figure 8 and 9) can reduce analog input noise. 14. Connect analog and digital ground pins of the ADC604 directly to the ground plane. In our experience. connecting these pins to a common ground plane gives the best results. Analog and digital power supply commons should be tied together at the ground plane. Adding power supply and ground-return filteringO) is optional and may improve noise reduction. NOTES: 1.'"On lhc Usc of Windows for Hanoonie Analysis with the Diseretc Fourier Transfonn': Fredric J. Hani•• Proceedings of 1M 1£££. Vol. 66. No. I. January 1978. pp 51-83. 2. SFDR test includes hannonics and non-hannonic spurious pmducts. 3. If IMD is referenced to peak envelope power. distonion will be of 6dB better. 4. ''Test Report: FFr Ch..-eri7.atico of B.IT-Brown ADCIiOOK': Signal Conversion Ltd.• Sw...... Wales. U.K. 5. M£eL Sys_ Design HtJIIdbooIr.. 3n1 Edition. Motorola Corp. 6. Motorola MECL. Motorola Corp. 7. Murata·Eric BNXOO2001. HISTOGRAM TESTING Histograms are used to test differential nonlinearity of the ADC604. This system's block diagram (the same for FFI' testing and waveform digitizing) is shown in Figure 2 and histogram test results for a typical converter are shown in the Typical Performance Curves. Note that low-frequency differential nonlinearity is under 1I2LSB and it shows virtually no degradation near the Nyquist limit of 2.SMHz; there are no missing codes present and the peak nonlinearity does not exceed 3/4LSB. Histogram testing is a useful performance indicator as the width of all codes can be determined. SWEPT·POWER FFT TESTING ADC604 converters are comprehensively tested to assure their conformance with Burr-Brown specifications. As this converter is designed for spectral-analysis applications. all important dynamic parameters are FFI' tested. including a 9.2-128 swept-power response measurement on KH-grade devices. AID converter spurious signal levels typically show a variation with input signal power. To insure that these spurs remain at an acceptable level over the whole range of input signal amplitudes. a point-by-point measurement of worstcase spurious signal levels (harmonic or non-harmonic) is made as the input signal level is stepped by IdB from an over-driven amplitude down to the ADC noise level. To minimize measurement error due to noise. eight FFl's are averaged to generate each data point. Plotting these data points results in the curve labeled "Spurious-Free Dynamic Range vs Input Power Level" shown in the '!ypical Performance Curves on page 5. Each ADC604KH is supplied with FFI' plots and a swept-power test plot. Units with guaranteed swept-power performance are available on special order. TIMING The ADC604 generates all necessary timing signals internally. There :...--= ,-.,vo tncL'icds for reading ouipui data, olier.. ing three selectable levels of data pipeline delay as described below: (1) Convert Command timing option (pin 29 = HIGH)With this option. the Convert Command signal is used both for initiating a new conversion and for reading valid data from a previous conversion. This method is most useful in synchronous systems where data samples are taken continuously. See Figure 13 for timing relationships. Pin 28 is used to control the amount of pipeline delay. If pin 28 is held LOW. then output data "N - 2" will be valid on the rising edge of Convert Command "N'~ If pin 28 is held HIGH. then ,output data "N - 3" will be valid on the rising edge of Convert Command "N". These timing relationships are valid at any conversion rate up to SMHz. At a conversion rate ofSMHz. the data setup time before the rising Convert Command edge is about sOns. ' (2) Data Valid timing option (pin 29 = LOW)- With this option. data from conversion "N" becomes valid after a fixed delay from the rising edge of COnvert Command "N". The delay is approximately 165ns. At about t = 185ns. the Data Valid strobe signal will rise. This strobe signal may be connected directly to the clock input of the external data latches. providing a data setup time of approximately 2Ons. See Figure 14 for timing relationships. Pin 28 must be left HIGH at all times when using the Data Valid timing option. The advantages of this method are: (a) no subsequent con~ versions are required in order to read the data (ie, single-shot conversion capability). and (b) the data is available as soon as possible after the start of conversion. Therefore, the Data Valid option is most useful in systems where the ADC may be operated asynchronously. or where the very first data latch output after power-up must represent a valid conversion. DATA OUTPUT Output logic inversion can be accomplished by programming pin 27. Binary Two's Complement or Inverted Binary Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) 1\vo's Complement output data format are available (Table 11). The ADC604 output logic is TIL compatible. The tri-state output is controlled by ENABLE pin 25. For normal operation, pin 25 will be tied LO. A logic HI on pin 25 will switch the ouput data register to a high-impedance state (Figure (6). Output OFF leakage current I07.L and 107J1 will be less than 5~ over the converter's specified operating temperature range. Tri-state outputs must not be connected directly to a noisy digital bus, as this noise can be coupled into the converter's analog input. DIGITAL INPUTS Logic inputs are TIL compatible. Open inputs will assume a HI logic state; unused inputs may be allowed to float or they may be tied to an appropriate TTL logic level. NOTES: I. FAST'" Appl/catlons Handbook. 1987. Fain:hild Semiconductor Corp. 2. Fairchild Advanced CMOS Technology. Tcchoology Seminar Notes, 1985. 3. "Impedance Matching Tweaks Advance CMOS IC Testing': Gerald C. Cox. Elec· tronic Design. April. 1987. DATA LATCHED BY CONVERT COMMAND N-3 N-2 N-l 28 29 HI HI LO HI HI LO OFFSET AND GAIN ADJUSTMENT The ADC604 is carefully laser-trimmed to achieve its rated accuracy without external adjustments. If desired, both gain error and input offset voltage error may be trimmed over a very small range with external potentiometers (Figure 17). Trim range is typically only 0.1 %; larger offsets and gain changes should be made elsewhere in the system. Using an input buffer amplifier allows a convenient point for injecting large offset voltages and making wide gain adjustments. If offset and gain trim is not used. pins 36 and 37 should be left unconnected. THERMAL REQUIREMENTS The ADC604 is tested and specified over a temperature range of O"C to +70°C in a forced-air environment with 500 LFPM air flow. With a small heat sink (Figure 18). the ADC604 can be operated in a normal convection ambient-air environment if submodule case temperature does not exceed the upper limit of its specification.(l) High junction temperature can be avoided by using forcedair cooling, but it is not required at moderate ambient temperatures. Thermal resistance of the ADC604 package is: 81C = 4.8°C/W measured to the underside of the case. DATA LATCHED BY DATA VAUD STROBE PIN NUMBER 3. "Orounding for E1ectromagnelic Compatibilily': JellY H. Boogar. D"lgn New•• February 23. 1987. NOTES: TABLE I. Pipeline Delay Selection Logic. I. "Maximizinglleat ThIIIsfcr from PCUs': Machine Design. Mmh 26. 1987. Jcilong ChWlS. DIGITAL DATA OUTPUT LOGIC CODING BINARY TWO'S COMPLEMENT (BTC) PIN 27" LO INVERTED BINARY TWO'S COMPLEMENT (BTC) PIN 27" HI +FS (+1.25V) +FS -ILSB -o3'4FS +112 FS 011111111111 011111111110 000111111111 001111111111 100000000000 100000000001 111000000000 110000000000 +1 LSB Bipolar Zero -1 LSB 000000000000 111111111111 111111111110 111111111111 000000000000 000000000001 -112 FS 101111111111 100111111111 100000000001 100000000000 010000000000 011000000000 011111111110 011111111111 INPUT VOLTAGE -314 FS -FS-1LSB -FS (-1.25V) LSB MSB MSB ADC804 Signal Inpul (0:----, Signal ......................,., Inpul Analog Common -= R T- Cable TermlnaJlon I~ LSB FlGURE 6. Floating-Input Balun Transformer. TABLE II. Digital Data Output Logic Coding. Amidon FT 50-43 Powdered Iron Core 1 2 2 2~2 Impedance = 1:1 #26 AWG BHDar Wound FIGURE 7. Balun Transformer Windings. Burr-Brown Ie Data Book Supplement. Vol. 33b 9.2-129 12 UI Ii: i 8 ~ •-o Z ~ - () Z ~ 2 2 o () . o a SI For Immediate Ass/stance, Contact Your Local Salesperson 499D 150D +5V +5V ADC604 'MO; 45 Twinax no! TrIax Input Signal Input Input 46 -= Analog Common -= • Tantalum .JfJV FIGURE 8. Differential Input Buffer Amplifier (Gain = -IVN). F .JfJ.2V -15V +15V Parailelo.ol~F Ceramlcend 1~F Tantalum (All) ADC604 45 Signal Input 48 Analog Common • Tantalum .JfJV FIGURE 9. Differential Input Buffer Amplifier (Gain =; -2VN). +5V +5V + + 16 EI-31-+-6+-4-12;-43"33 44 34 30 3 21 DO CO Dl Ql D2 Q2 D3 74F174 03 Signal ":>--==""'1 In In .. MSB 10 D4 Q4 12 D5 Q5 15 +5V ADC604 -= TILDa1a Ou1pul 15 27 28 29 CC DV 24 LSB 16 17 18 19 DO CO Dl Ql 20 D2 D3 22 13 14 Q2 74F174 03 D4 Q4 D5 Q5 cc}-----+---------------------------~ 10 12 15 LSB He. latch FIGURE 10. Interface Circuit...,....Digital Output Strobed by Convert Command. Supply connection shown: power supplies and grounds shared by analog and digital pins using common ground plane. (Recommended circuit) 9.2-130 Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1-800-548-6132 (USA Only) Parailelo.oWF Ceramic and I~F Tantalum (All) F E -5.2V -15V +15V +5V +5V + 1-3l+-6i-4-i2-43"33 44 34 30 3 21 S~~aI [o:--=~ 28 29 = 00 01 01 MSB D2 02 0374F17403 In D4 04 os 05 DV = +5V ADC604 32 26 25 23 27 = IIII Ii: 16 IX) 10 E 12 15 8 ~ TTL Data Output •-o 15 16 17 Z 18 19 LSB CC DV 24 ~ 20 - 10 22 13:...j D4 L..-_ _..:: 12 04 14 c,) 05 15 CC)--_...J Z LSB ::) I! I! Hex Latch FIGURE 11. Interface Circuit-Digital Output Strobed by Data Valid Pulse. Supply connection shown: power supplies and grounds shared by analog and digital pins. using common ground plane. Analog Power SLIlPlIas ~----~~,-----~ -5.2V +5V Analog Analog +15V Analog Parallel O.OI~F Ceramlcand + 1~F Tantalum (All) SI~~aI fcom -5.2V +5V Com +15V Com -15V -15V Analog tC. Co~ oCo) . o a ~ - ParailelO.OlpF Cerarnlcand lpFTantaium (All) 6 42 Signal 45 •o In ADC604 46 CD Co) 31 ~ 21 ~ ~+ v = Analog Ground Plane -5.2V Digital +5V Digital . . = Digital Ground Plane lCom -5.2V +5V v co~ v~ Analog Gniund Plana ... ~ DIgital Ground Plane DIgltal Power ~ FIGURE 12. Power Supply Connections with Separate Analog and Digital Power Supplies and Ground Planes. Burr-Brown Ie Data Book Supplement, Vol. 33b FIGURE 13. Power Supply Connections with Separate Analog and Digital Power Supplies and Ground Planes with Noise Filtering 9.2-131 For Immediate Assistance, Contact Your Local Salesperson Nanoseconds Data Output Pin 28. High Pin 29. High i 1 :Valld Data N-3j Data Output Pin 28. low Pin 29. High ~~: i xRxx*xx: . : Invalid : : Valid Data : N-2: I Data I I I I Intarnal SamplelHoid Command : , , : : -I' I I I I '(4): - t I-IcH , , ~~: i X$xxXXX: :Valid Data : Invalid: N-1' Data I : :, I-IcH I i )O;OOOp OdoooGxxx 'Valid : Data N + I I i I I -t I-IcH I ! : •I ': : ~I: ~~! Valid Data N : .. I : fl' I : ~s;ui,pJeN+l~SampleN~~1 ---T-J ; Hold N i ~TJ i HOIO N + 1 i "-r---f)Ti--I I tCDl.: ": ~ : ,: : : Start Conversion' t N+2 : .. I : lelD: xXxxXxxxx~: -II-IcHiS) I -;1 t~1) Valid: : Data N -I I N losu(7) I I : I. -r.t-f- : : I I : : Strobe! I --.. : tCDl.: I ~tCIDC, DataOu1pUl Pin 28. High Pln29.Low I tCDL(1)---f-.-I: : Intemal Sampie/Hold Command ~ -+- : invalid: : Data: I I : : I I : HoIdN'+2 I L I I NOTES: (I) 1"... a delav time from Convert Command 10 Iile failing edge of Data Valid strobe. Typical value • I~ns. Independent of conversion rate. (2) t".... delay timefrom Convert Command 10 the rising edge of Data Valid strobe. Typical value ~ 185ns.lndependentofconverslon rate. (3) 1"... delay time from Convert CommandlO Invalid Data. Typical value. 65ns.lndependent ofconversion rate. (4) tew. delay timefrom Convert Command 10 Valid Data. Typical Value. 165118. Independent of conversion rate. (5) ..... delay time from Convert Command 10 the Intemal hold command. Typical value • ens. Independent of conversion rate. (6) The \\ symbollndicaleS the portion of the waveform thet will "s1J8lch our at lower converslon rates. (7) .... ~ data setup time. Typical value • 20ns. Independent of COIW8ISIon rate. FIGURE 15.. Data Valid Strobe Timing. 9.2-132 Burr-BrownIe Data Book Supplement. Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) t +ISV Offset T~m 101<0 ENAiiLE HI Input Pin 25 LO J Data HI High Impedance Output OFF Pins 9-20 LO 37n8 36 -16V 37 +ISV ADC604 37n8 ActIve T~m Gain FIGURE 16. Digital Data Tri-State Output. .' •••••• ---::.;;::::--..~ •••;;.o:•••• , Lead Sockets for 18m" Diameter Pins Heat Sink l0808HS Conducts heat from bottom of package Into copper ground plane. Mounting screws and nuts not Included with 0808HS. 101<0 -15V FlGURE 17. Optional Gain and Offset Trim. r~ I-B-I .- t f 0.57S'- 1.150' ~ r-@ ~ '" lr !iiu Z ::::I 15 15 NOTES: 0.120" Diameter and CSK 82" 0.235" +O.OOS' -0' Dtametar (2 Places) E 8 S i- 0.090' @ /' IIU Ii (1) Mate~aI: 6061·T6 aluminum. . (2) Finish: nlckel-plate or Irridite. (3) Deburr and break all sharp edges. FIGURE 18. Heat Sink Transfers Heat from the DIP Package into a Copper Ground Plane. 8. o a ~ - . o CD u a c Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-133 For Immediate Assistance, Contact Your Local Salesperson ADC614 IIRR-BROWN8 IE5IIE5II ADVANCE INFORMATION SUBJECT TO CHANGE 14-Bit 5MHz Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES • SPURIOUS-FREE DYNAMIC RANGE: 85dB • SAMPLE RATE: DC to 5MHz • HIGH SIGNAUNOISE RATIO: 78dB • LOW HARMONIC DISTORTION: • COMPLETE SUBSYSTEM: Sample/Hold and Rel'ere,nce • DIP PACKAGE' • O°C TO +70°C The subranging ADC suban ADC, sample/hold amplifier, timing, and error-correction cirDIP package. Logic is TIL. Temrange available: OOC to +70°C. LSB Flash Encoder Digital Error Corrector Digital OuIpUl (Adder) lnternalianli AIrpOrt InduSlrlaI Park • IIaDing Address: PO Bol114OO • TUcsan, AZ 85734 • SIreeI Addrua: 6730 S. TUcDI Blvd. • T - . AZ l151li6 Tel: (602} 746-1111 • TwI:911H52·1111 • ClbIe:BBRCORP • T.lel:06H481 • FAX: (602) 8811-1510 • ImmadIl1l ProduCllnlo: (100) 54M132 POS·I085 92-134 Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL Tc. +25'C. 5MHz sampling rate. R•• SOD. ±VC4 • ±15V. +V.., - +5V. -V.." • -5.2V. and 15·mlnute warmup In convection environment. unless otherwise noted. CONDmONS Full Scale +1.25 -1.25 1.5 5 Start Conversion t • Conversion Period V MO pF m Compatible Positive Edge 10 Gain Error Input Offset Integral Unearity Error Differential Unearlty Error IIII Ii: E 8 S io ,-. MIssing Codes Power Supply Refection U Z :) :E :IE LSB LSB dBc'" dBc -as dBc dBc TBD TBD dB dB 74 .78 -5 2 dB dB 70 40 TBD 8. = ~ o ns ps rrns MHz MHz ns ... CD () ~ NOTES: (I) FSR: Full-Scale Range = 2.5Vp-p. (2) Units with tested and guaranteed cflStortion specifications will be available. (3) dBc = level referred to carrier· input signal (= OdB); F -Input frequency; F._ sampling frequency. (4) IMD Is referred to the larger of the two Input lesl signals. II referred to the peak envelope signal (= OdB). the Inlerrnodulalion products will be 6dB lower. Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-135 For Immediate Assistance, Contact Your Local Salesperson MECHANICAL H Package - Metal and Cenlmlc 1-'--- A ----'1 241 48 Ir DIM A B C D J B Pin 1 designator marked on bottom ~-l-~23 F H K L M N MIWMETERS INCHES MIN MAX MIN MAX 2.370 2.420 60.20 61.47 1.560 1.610 39.62 40.89 .200 .260 5.08 6.60 .018 DIa BASIC 0.46 DIa BASIC 2.54 BASIC .100 BASIC 0.75 .115 1.91 2.92 4.83 .150 .190 3.81 1.300 BASIC 33.02 BASIC 100 10' .040 .G6O 1.G2 1.52 - NOTE: Leads In true position within 0.01" (O.25mm) R at MMC at seating plane. Pin nurmers shown lor reference only. NuntJers may not be marked on padcage. - PIN ASSIGNMENTS 1 2 3 4 Common (Case) DNC . +VIlO1 (+5V) Analog SIH Out 5 AID In 6 7 8 -V... (-5.2V) Analog Bit 13 Bn 14 (LSB) BH 1 (MSB) BH2 9 10 11 12 13 14 15 16 17 18 BH3 BH4 BH5 BH 22 Bn' BH8 BH9 Bn 10 BH 11 Bit 12 +Voo, (+SV) Date Valid 23 Common 19 20 21 9.2-136 ......................................................................................... ±5V .~~!!.;:;:~::;. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-.~ . ..:.".....v ~I~~ .' ................................................................... :+I65·C Storage Temperature ................................................;.... ~ to +165"C Stresses above these ratings may permanently damage the device. Burr-Brown Ie Data Book Supplement. Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) ADC701 SHC702 BURR - BROWN® IElElI IMPROVED SPECIFICATIONS NEW FEATURES FEATURES • CONVERSION RATE: to 512kHz over temp • MEDICAL IMAGING • NO MISSING CODES AT 16 BITS • SPURIOUS·FREE DYNAMIC RANGE: 107dB • SONAR • PROFESSIONAL AUDIO RECORDING • LOW NONLINEARITY: ±O.0015% • SELECTABLE INPUT RANGES: ±5V, ±10V, to +i0V, 0 to +5V, -i0V to 0 • AUTOMATIC TEST EQUIPMENT ~ = (,) Z :::) :E :E • HIGH PERFORMANCE FFT SPECTRUM ANALYSIS • ULTRASOUND SIGNAL PROCESSING • HIGH SPEED DATA ACQUISITION • REPLACES DISCRETE MODULAR ADCs • METAL AND CERAMIC DIP PACKAGES DESCRIPTION The ADC701 is a very high speed 16-bit analog-todigital converter based on a three-step subranging architecture. Outstanding dynamic performance is achieved with the SHC702 companion sample/hold amplifier. Both devices use hybrid construction for applications where reliability, small size, and low power consumption are especially important. Excellent linearity and stability are assured through use of a new ultra-precise monolithic D/A converter and a low-drift reference circuit. Custom monolithic op amps provide very high bandwidth and low noise in all sections ofthe analog signal path. Logic is CMOS/TTL compatible and is designed for maximum flexibility. 1kO Analog Inpul O-l--'WIr-~--o<>--"""'-l Buffer OUIPUI 0-.....- - - . . , ....--.J'--., Buffer Input L -_ _ _ _ _- \ -_ _ _ _ _ _- - - ' Sample/Hold Command -+-_-+__---' L -_ _ _ _ _ Convert Command International Airport Industrial Park • lIalilng Address: PO Box 11400 Tucson, Ja. 85734 Tel: (602)746-1111 • Twx: 910-952·1111 • Cable: BBRCORP Street Address: 6730 S. Tucson Blvd. • Tucson, Ja. 85706 FAX: (602) 889-1510 Telex:~1· PDS·S77A Burr-Brown Ie Data Book Supplement, Vol. 33b I io APPLICATIONS • LOW POWER DISSIPATION: 2.8W Typical Including Sample/Hold ~ 8 16-Bit 512kHz SAMPLING AID CONVERTER SYSTEM o 12 w 9.2-137 o(,) . o -a ~ For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL (ADC701 ONLY) TA :: +25°C, 500kHz sampling rate, ±Vcc:: ±15V, ±VODI =±5V. +V OD2 :: +5V. and five minute warmup in" a convection environment, unless otherwise noted. ADC701KH ADC701JH PARAMETER CONDmONS MIN TYP MIN MAX RESOLUTION TYP MAX UNITS Bits IS INPUTS ANALOG Voltage Ranges Unipolar Bipolar o to +5V Range o to +10V, -10 to 0, %5V Ranges ±10V Range All Ranges Resistance Capacitance DIGITAL Logic Family Convert Command Pulse Width Start Conversion t :: Conversion Period I I I · ·2.45 4.9 9.B 50 I o to +5, 0 to +10, -10 to 0 %5,±10 2.5 2.55 5.1 5 10 10.2 5 I ·· ·· TTL-Compatible CMOS Rising Edge t-50 I I I • V V k.Q k.Q k.Q pF I I · ns TRANSFER CHARACTERISTICS ACCURACY Gain Error<'1 Power Supply Sensitivity 01 Gain Input Offset Error''' Power Supply Sensitivity of Offset Integral Linearity Error'" Differential Linearity Error'" No Missing Codes Noise o to +10V Range ±10V Range All Ranges, All Supplies o to +10V Range ±10V Range All Ranges, All Supplies RSOUACE · ±D.03 ±D.l ±0.03 ±D.l ±D.005 ±D.l ±1 ±3 %5 ±10 ±D.OOS· ±D.l ±D.003 ±D.OO2 ±D.OOOS ±O.OOI2 · · %IV mV mV %FSRIV ±D.0012 %FSR(3! iuara.ntej CONVERSION CHARACTERISTICS Sample Rate Conversion Timel'" Unadjusted Unadjusted 512 1.5 DC 1.45 % % %FSR iuarantej O.S s son · LSB rrns ·· · kHz ~ OUTPUTS +rL-COm~tible CM~ I DIGITAL Logic Family Data Coding Logic "0" Levels (VOl.) Logic "1" Levels (VCH ) Data Valid Setup Time Before Strobe INTERNAL REFERENCE Voltage Current Available to External Loads Unipolar Ranges Bipolar Ranges IOI.S3.2mA I"" S BOllA Both Edges Straight Binary Offset Binary 0.4 4 2B 0.1 4.9 37 RLOAD~ 51<0 +9.995 2 +10.000 5 +10.005 · Operating +14.25 -14.25 +4.75 -4.25 +4.25 +15 -15 +5 +15.75 -15.75 +5.25 · ·· ·· I ·· · .. V V ns V mA POWER SUPPLY REQUIREMENTS Supply Voltages:+V" -Vee +VODI -VOOI ·+V002 Supply Currents: +1" -Icc +1001 Operating -1001 +1002 Power Dissipation Nominal Voltages -5 -5 +5 25 33 45 37 133 1.95 +5.25 30 45 55 50 150 2.3 · ··· · ·· ·· ·· · · V V V V V mA mA mA mA mA W PERFORMANCE OVER TEMPERATURE Specification Temperature Range Gain Error Input Offset Error T. Min to T. Max All Ranges All Unipolar Ranges .All Bipolar Ranges +15 ±10 ±1 ±1 ±D.2 ±D.05 Integral Linearity Error''' Differential Lin.earily Error 21 I TY~cai I No Missing Codes Reference Output Drift Drift of Conversion Time Sample Rate Unadjusted Unadjusted DC +55 ±15 %5 %5 +4 512 0 · ·· · r:tej +70 ·· · ±D.5 ±D.3 ·· 'C ppml'C ppm FSRI"C ppm FSRI"C ppml"C ppml'C ppml'C nsPC kHz • Same specifications as ADC701JH. 9.2-138 Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Ser"ice at 1·800·548·6132 (USA Only) SPECIFICATIONS ELECTRICAL (SHC702 ONLy) T" = +25°C. 500kHz sampling rate, ±Vcc =±15V, +VDDI =+SV, and five minute warmup in a convection environment. unless otherwise noted. MIN TYP MAX UNITS IIII ±IO.25 0.98 ±II I 3 1.02 V k1l pF III SHC702JM PARAMETER CONDIllONS INPUTS (Wilhout Input Buffer) ANALOG Vollage Range Aesistance Capacitance DIGITAl. Logic Family Input Loading I LSITL 2 I LSITL Loads n",,~r~n ~n"n"~.~n.~""" ACCURACY Gain Gain Error RsoURCE = on RSOUACE Unearity Error DYNAMIC "n"n"", ~"'''' """ Acquisition lime lOV~~e~:o ±ISOI1V 5V Step to ±ISOI1V to ±I5011V Sample-to' Hold Settling lime'" Aperture Delay Time Aperture Uncertainty (Jitter) Slew Rate Small Signal Bandwidth Full-Power Bandwidth ". "th , Rejection V~=±IOV Hold Mode, lOVp-p Square Wave Input RUlA. " Ik1l DC DYNAMIC CHARACTERISTICS Slew Rate Full-Power Bandwidth Settling lime V'N=±IOV RsouRCE:S 10kO ±IO.25 Operating -Vee +VODI Current: +Icc Di~~J~tiOn 25 I ±II I I Indefinite 0.01 I ns ns ns ns psrms VIlIS MHz MHz % V mA 0.1 n 10" 113 ±2 ±O.3 ±II ±I5 ±I.5 nlipF pA mV V 20 35 570 1.7 VIlIS kHz ±15 ±20 Indefinite mA +13.5 -13.5 +4.75 +15 -15 +5 33 18 5 790 F\c•• = on "'" ±3 ±5 ±2 VN % %FSR mV mV I1VIIIS %FSR %FSRN 0 U a C.. U) Z -~ - 0 U Z ::) I! I! 0 U . -a 0 ::) Operating Nominal Vollages )15. +16.5 -16.5 +5.25 40 25 10 950 V V V mA mA mA mW +70 ±S "C ppml"C I1VI"C I1V1"C I1VIIIS I1VfC :()VEfI. ".m,.~n. ,un" SpeCification Temperature Range SamplelHold Gain Error SamplelHold Offset Error SamplelHold Charge Offset Error Droop Rate Buffer Offset .Error = -C V.. =±IOV 10V Step to_ ±15011V OUTPUT Output Current Short Circuit Protection Power ±IO.25 ±40 ALOAD=OQ INPUT BUFFER CII"n"",,,n,,,,,,,,,,, INPUT Impedance Bias Current Offset Voltage Voltage Range ±O.I 600 500 120 20 10 150 3.1 2 0.001 V,. =±1V OUllPUT Vollage Range Output Current Short Circuit Protection Output Impedance Voltage: +Vcc on Sample Mode Sample Mode Sample/Hold Mode, RsoURCE S 50n Hold Mode SamplelHold Mode Offset Plus Charge Offset All Supplies Offset Error Charge Offset (Pedeslal) Error Droop Rate Dynamic Nonlinearity Power Supply Sensitivity POWER SUPPLY == -I ±O.02 ±O.OO03 ±O.5 ±O.5 ±O.2 ±O.0005 ±O.003 ~ T. Min to T. Max ASOUACE = on RSOURCE .s: 50n RSOURCE S 50.0 RsoURCE .s: 10kO a ±1 £10 ±10 ±3 ±ao ±SO ±SO ±15 NOTES: (I) Adjustable to zero. Tested and guaranteed fora to +IOV and ±10V ranges only. (2) Peak-to-peak based on 99.9"10 of all codes. (3) FSR means fullscale range and depends on the Input range selected. (4) ADC conversion time is defined as the time that the Sample/Hold must remain In the Hold mode; i.e., the duration of the SamplelHold command. This time must be added to the Sample/Hold acqusition time to obtain the total system throughput time. (5) Given for reference only - this time overlaps with the ADC701 conversion time and does not affect system throughput rate. Burr-Brown Ie Data Book Supplement, Vol. 33b 9,2-139 "...U 0 ..Ie Z !! U a -C For Immediate Assistance, Conlact Your Local Salesperson SPECIFICATIONS ELECTRICAL (COMBINED ADC701/SHC702) T.= +25·C, 500kHz sampling rate, ±Vee= ±15V, ±V,,,= ±5V, +V,,,,= +5V, and five minute warmup in a convection environment, ±5V Input range unless othelWise noted. PARAMETER Sample Aate Dynamic Nonlinearity Total Harmonic Distortion (THO) CONDITIONS MIN Unadjusted DC TYP MAX UNITS 512 kHz %FSR % ±a.002 Spurious·Free Dynamic Aange (SFDA) Two·Tone Intermodulation Distortion (IMD) f," = 20kHz Hl.3dB) fw = 199kHz (-O.2dB) fw 20 kHz (-O.3dB) 199kHz (-12dB) f, = 195kHz (~.5dB), f, 200kHz (~.5dB) f, = 195kHz (-12.5dB), fF, 200kHz (-12.5dB) fw 5kHz (-O.5dB) Operating = 'w = = Signal·to·Noise·Aatio (SNA) Total Power Dissipation = = 0.00068 0.0078 107.1 93.8 % dB dB dBC dBC dB ~1.4 ~6.2 93 2.8 W 3.25 ADC701 MECHANICAL 1-------- ---------1'1 H Package- Metal and Ceramic A c ~ INCHES DIM MIN MAX A 2.075 2.115 B 1.080 1.100 C .t45 .175 D .018TYP F .040 lYP .100lYP G H .093 .103 .020 BASIC J K 205 BASIC .900 BASIC L N .015 J .035 +J MILLIMETERS MIN MAX 52.71 53.72 27.43 27.94 4.45 3.68 0.46lYP t.02lYP 2.54 TYP 2.36 2.62 0.51 BASIC 521 BASIC 22.86 BASIC 0.38 0.89 NOTE: leads in true position within 0.01" (O.25mm) Rat MMC at seating plane. Pin numbers shown for reference only• Numbers may not be marked on package. r I+-I.--L---I,I ADC701 PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Bit 119 (Bit 1 = MSB) Bit 2110 Bit 3111 Bit 4112 Bit 5113 Bit 6114 Bit 7115 Bit 8/16 Clip Detect Output +VD02 (+5V) Digital Common (Digital) Data Strobe High/Low Byte Select Convert Command Sample/Hold Control'" Common (Digital) Common (Digital) Clock Adjust Common (Digital) +V'02 (+5V) Digital 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 ADC701 ORDERING INFORMATION -V'D' (-5V) Analog Common (Analog) +V," (+5V) Analog Reference (Gain) Adjust +10V Reference OUtputl21 Common (Reference) DNC Common (Analog) +10V Aeference Inpu~. Input 0 III =r_-' ( ) H T Basic Model Number -.,._ _ _ _ _ _ _ _ Performance Grade Code _ _ _ _ _ _ _ _ _ _ _....1_ K: O·C 10 +70·C Ambient Temperature J: +15·C to +55·C Ambient Temperature Package Code - - - - - - - - - - - - - - - - - - ' H: Metal and Ceramic Inpute (1 ) Common (Signal) InputBII) ADC701 ABSOLUTE MAXIMUM RATINGS =.._....._.._ ..._......__......_..._.__.__._.. _._....._......_...__.__......_±18V (nputA(1) ±V -Vee (-15V) Analog Common (Power) +Vcc (+15V) Analog ±VD01 ' +VCO2 _.~._. __ ONC'·' Offset Adjust Offset Adjust NOTES: (1) Aefer to Input Connection Table. (2) Reference Input is normally connected to Aelerence Output, unless an external 1OV reference is used. (3) Sample/Hold Control goes high to activate Hold mode. (4) DNC = Do Not Connect. 9.2-140 ADC701 .NN.N. _ _ _ • __ • _ _ _ _ _ • _ _ _ _ _ N _ _ _ _ _ RR.H _ _ ._._±7V. +7V Analog Input ........................................................................................ ±veo Logic Input ............................................................. -O.5V to (+VD'" + O.3V) Logic Output ................................................................................... ±25mA Cese Temperature ........................................................................ +150·C Junction Teinperature ................................................................... +165·C Storage Temperature ...................................................... ~5·C to +165·C Power Dissipation .................................................................................3W Stresses above these ratings may permanenUy damage the device. Burr-Brown Ie Data Book Supplement. Vol.33b Or. Call Customer Service at 1·800·54B~6132 (USA onlv] ADC701 OUTPUT CODING NOMINAL INPUT VOLTAGE TO ADC701 (Multiply by -1 lor SHC702 Input Voltage) OUTPUT CODE (1 = logic High) LSB CUP DETECT INPUT LEVEL (Exact Center 01 Code) G-l0V RANGE (ILSB. I53ItV) ±10V RANGE (1 LSB • 30SltV ±5V RANGE (ILSB. 153ItV) Underrange -FS -FS + lLSB <-76ItV < -10.0001S3V < -S.000076V OV +IS3~V -10V -9.99969SV -SV -4.999B47V 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1 0 0 -3f4FS -lf2FS -1f4FS +1.2SV +2.SV +3.7SV -7.SV -SV -2.SV -3.75V -2.SV -1.25V 0010 0000 0000 0000 01000000 0000 0000 0110000000000000 0 0 0 -ILSB Mid-Scale +ILSB +4.999847V +SV +5.000153V -30SItV OV +30SItV -IS3ItV OV +153ItV 0111111111111111 1000 0000 0000 0000 1000000000000001 0 0 0 +1f4FS +lf2FS +3f4FS +6.2SV +7.5V +8.75V +2.5V +5V +7.5V +1.2SV +2.5V +3.7SV 1010 0000 0000 0000 1100 0000 0000 0000 1110 0000 0000 0000 0 0 0 +FS -2LSB +FS -ILSB Overrange +9.999695V +9.999847V > +9.999924V +9.99939V +9.999695V > +9.999B47V +4.999695V +4.999B47V > +4.999924V 1111111111111110 1111111111111111 1111111111111111 0 0 1 MSB 12 au Ii: E 8 S io -Iii -u:::»z SHC702 MECHANICAL M Package- Metal I INCHES MAX DIM MIN A 1.365 1.385 .79 .810 C .170 .250 D .016 .021 G .100 BASIC H .125 .150 K .150 .300 L .600 BASIC R .080 I .110 I A CJJ e \ . Denotes pin 1 MILUMETERS MIN MAX 34.67 35.18 20.07 20.57 4.32 6.35 0.41 0.53 2.54 BASIC 3.18 3.81 3.81 7.62 15.24 BASIC 2.03 2.79 R SHC702 PIN ASSIGNMENTS 1 2 3 4 5 6 7 B 9 10 11 12 SamplefHold Oulput Nell) NC NC NC NC NC NC +Vo" (+SV) Analog Common (Digital) Hold Inpu~" Hold Inpu~" 24 23 22 21 20 19 18 17 16 15 14 13 R NOTE: Leads in true position within 0.01" (O.25mm) R at MMC at seating plane. Pin material and plating composition conlorm to method 2003 (solderability 01 MIL-STD-BB3 (except paragraph 3.2) Ii Ii ou . o -a LCJ··········· y 1 . 12 ~ 2;4 •••••••••• 1~ SHC702 ORDERING INFORMATION +Vee (+ISV) Analog Common (Power) -Vee (-15V) Analog Common (Analog) NC NC NC Buffer Amp Inpu~" NC Common (Signal) Buffer Amp Output Analog Input NOTES: (1) Hold mode is activated only when pin 12 is low and pin 11 is high. For normal use with ADC701, pin 12 is grounded and pin 11 is connected to ADC701 Sample/Hotd control (ADC701 pin 15). (2) lithe buffer amp is not used, pin 17 should be grounded. (3) NC = No Internal Connection. Burr-Brown Ie Data Book Supplement, Vol. 33b SH C70 Basic Model Number _ _ _ _ _ _ _ _ _:T_ _J 2 f M Performance Grade Code J: O'C to +70'C Ambient Temperature Package Code - - - - - - - - - - - - - - - - - ' M: Melal SHC702 ABSOLUTE MAXIMUM RATINGS ±V~_--.---------.-----.-----....-------------±18V _~w w. _ _ _ .+7V +VODl _____ w _ _ _ .w _ _ _ • _ _ _ _ _ _ _ _ _ _ _ _ Analog and Buffer Inputs .................................................................... ±Vcc Outputs ........................................................... Indefinite Short to Common Logic Inputs ........................................................... -O.5V to (+Voo, + 0.3y) Case Temperature ........................................................................ +150'C Junction Temperature ................................................................... +165'C Storage Temperature ...................................................... 09S'O to +16S'O Power Dissipation .............................................................................. I.5W Stresses above these ratings may permanentiy damage the device. 9.2-141 For Immediate Assistance, Contact Your Local Salesperson TYPICAL DYNAMIC PERFORMANCE (ADC701/SHC702) FULL-SCALE SINEWAVE RESPONSE. liN =20kHz FULL-SCALE SINEWAVE RESPONSE. fiN = 100kHz 0 0 -20 -20 -40 -40 iii :!!. -60 iii :!!. -60 '0 2 " E '" "0. Ci. ...E ...~ -60 2 -100 V -120 -eo -100 -120 Frequency (kHz) Input Frequency Fundamenlal -0.3 dB 2nd Hannonic -107.5 dB 3rd Harmonic -111.5 dB Frequency (kHz) 19.9890136719 kHz 4th Harmonic -115.6 dB 5th Harmonic -111.2 dB 6th Harmonic -124.5 dB Input Frequency -0.7 dB Fundamental 2nd Harmonic -61.4 dB 3rd Harmonic -69.4 dB TWO-TONE INTERMODULATION RESPONSE. fiN = 195kHz and 200kHz FULL-SCALE SINEWAVE RESPONSE. fiN = 200kHz 0 0 -20 -20 -40 -40 iii :!!. -60 iii :!!. -60 l..." E 199.005126953 kHz 4th Harmonic -111.5 dB 5th Harmonic -97.0 dB 6th Harmonic -112.5 dB '" '0 ~E -60 ... -100 -120 -60 -100 -120 50 100 150 200 250 50 Frequency (kHz) Input Frequency Fundamenlal -0.5 dB 2nd Hannonic -89.1 dB 3rd Harmonic -90.5 dB 100 150 200 250 Frequency (kHz) 100.982666016 kHz 4th Harmonic -102.5 dB -110.2 dB 5th Harmonic -106.8 dB 6th Harmonic f, f, 1> ',+12 2> ',-12 Frequency 1 Frequency 2 -6.8 -6.3 -67.7 -68.8 dB dB dB dB 194.976806641 kHz 199.981689453 kHz -96.0 3> '1+2f2 4> 2ft +f2 -96.8 -104.9 5> f,-21, -109.0 6> 2',-12 dB dB dB dB NOTE: For figures above. sampling rate = 500.0000000000kHz. 16.384 point FFT. non-windowed.· Noise floor limited by synthesized generators. DIFFERENTIAL NONLINEARITY OF ALL CODES. 19.6 MILLION SAMPLES 2.--------,-------, 10 ~ ..J 0 Z c -1 -2 0 32767 65535 Codes 9.2-142 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) THEORY OF OPERATION The ADC701 uses a three-step subranging architecture, meaning that the analog-to-digital conversion is performed in three passes which constitute coarse, medium and fine approximations of the input signal. Refer to Figures I and 2 for simplified block diagrams of the system. Before the input signal is presented to the ADC, it must be sampled with high linearity and low aperture error by the sample/hold amplifier. In the SHC702, the sampling switch is placed at the summing junction (virtual ground) of a high speed FET amplifier (Figure I). This arrangement maintains constant charge injection independent of the signal amplitude, which is critically important for good linearity performance. The sampling switch itself is a high speed DMOS FET whose gate is driven from a fast-slewing control signal, thus minimizing the time aperture between the fully closed (sample mode) and the fully open (hold mode) states of the switch. The signal voltage is held across the feedback capacitor, forcing the op-amp to maintain a constant output voltage for the duration of the AID conversion. Feedthrough from the input, already low due to the MOSFET's low capacitance, is further reduced by clamping the summing point to ground with another FET. The ADC70 I input voltage is converted to a current through the input scaling resistors (Figure 2), and this current is applied to the summing junction (virtual ground) of error amplifier AI. The current output of the DAC (0 to 2rnA) is also applied to the summing point. If bipolar operation is selected, the 10V reference output is applied to input D, creating a IrnA offset current which sums with the input current. IIII Ii: I lkf.l 8 ~ Analog 0-.....,,'1"-.......-..--...., Input io Hold -~ - U FIGURE 1. Simplified Block Diagram of the SHC702. Z :) Ii Ii Ref Out Ref Input In C Input D Input Input A B o u... o a ~ - High Speed PGA ADC Output Convert Command Hold Command Data . Strobe FIGURE 2. Simplified Block Diagram of the ADC701. Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-143 For Immediate Assistance, Contact Your Local Salesperson At the beginning of each conversion, the DAC is reset to midscale so that its output current is exactly lmA. This ImA is subtracted from the input signal current. The difference current flows through Rf and appears as an error voltage at the output of AI' During the first pass, the programmable gain amplifier (POA) is set to unity gain, which matches the error voltage range to the input range of the flash ADC. The error signal is digitized to 7-bit resolution by the flash ADC, creating a coarse approximation of the digital output value, which is then applied to the DAC. Since the DAC output is now approximately equal to the input signal current, the remaining difference current flowing through Rf is small-ideally less than 1/128 of full scale, which is due to the built-in quantizing uncertainty of the 7bit flash ADC. However, other sources of error (e.g., integral and differential nonlinearity of the flash ADC, gain and offset of the PGA, settling and noise errors throughout the signal path) cause the possible error range to be significantly greater. In fact, the ADC701 is designed to handle remainder signals up to 1/32 of full scale, which is four times the "ideal" value. Therefore, the PGA is set during the second pass to a gain of 32, allowing the small remainder signal to match the full range of the flash ADC. This is again digitized to 7-bit resolution and added to the previous result to create the "medium" approximation of the input signal. Because the full-scale range of the flash represents 1/32 of the input signal's full range, the 7-bit flash output is shifl:ed right by 5 bits before being added to the original 7-bit "coarse" result, creating a 12-bit word. There is an overlap of two bits because the two least significant bits of the first-pass result correspond to the two most significant bits of the secondpass result. This overlap in the adder is called "digital error correction"-the mechanism that allows nonideal remainders from the first pass to be corrected in the second pass. The 12-bit approximation is applied once again to the DAC, causing the remaining difference current to become yet smaller. For the third pass, .the PGA's gain is increased by another factor of 32, and the remainder is again digitized by the flash ADC. At this point in the conversion, all of the necessary data has been latched and it is no longer necessary to hold the analog' signals from the sample/hold or the DAC. From a systems perspective, the conversion is now complete because the sample/hold is released to begin acquiring the next input sample and the DAC is reset to mid-scale for the next conversion. Meanwhile, the final result from the flash is added to the previous 12-bit result. Again there is a two-bit overlap to allow for error correction. The adder output is monitored to prevent a digital "rollover" condition, so that the ADC clips properly at the signal extremes. The upper sixteen bits of the final adder result are stored in the ADC's output register, ready to be presented in byte-sequential form at the eight output data lines. The overrange or "clip" condition can also be detected externally by monitoring pin 9. Refer to the section on ADC701 Digital I/O for further detail. 9.2-144 INSTALLATION AND OPERATING INSTRUCTIONS TheADC701/SHC702 combination is designed to be easy to use in a wide variety of applications, without sacrificing flexibility of the analog and digital interface. SHC702 INTERFACE The connection diagram (Figure 3) shows the basic hookup. At the SHC702 input, the user may opt to connect the builtin FET buffer amplifier. The buffer is most useful in multichannel applications where the signal bandwidth is less than 100kHz. In those applications, it serves to isolate the multiplexer output from the Ikn input impedance of the sample! hold. For higher frequency applications and for any system that does not require the very high impedance, the best results (lowest noise and distortion) will be achieved by driving the SHC702's analog input directly. If the buffer is not used, its input should be grounded to avoid random noise pickup and saturation of the buffer op-amp. Only two connections are required between the SHC702 and the ADC701: SHC702 analog output to ADC701 input(s) and the .digital Hold Command from the ADC701 to the SHC702. As always, it is best to avoid routing these analog and digital lines along parallel traces. Although the placemeni of the SHC702 relative to the ADC is not extremely critical, one good approach is to mount the SHC along one end of the ADC package as shown in Figure 4. This minimizes the length of the interconnections and keeps the digital lines well away from sensitive analog signals. ADC701 INPUT CONNECTIONS The ADC input network has four separate terminals, allowing many different input ranges. These should be connected as indicated in Table I. Most users will take advantage of the ADC70l's built-in reference circuit, which has very low noise and excellent temperature stability. To use the internal reference, it is only necessary to connect pin 36 (Reference Output) to pin 32 (Reference Input). To use an externailOV reference (to cause the ADC gain to track a system reference, for example), pin 36 is left unconnected and the external reference is applied to pin 32. If required, the ADC701 will typically accommodate a five to ten percent variation in the IOV reference. External references should have very low noise to avoid degrading the excellent signal-to-noise ratio (SNR) of the ADc701. INPUT RANGE CONNECT V.. TO CONNECT Ref In TO o to +10V ±10V ±5V -10V 10 0 010 +5V Inpul A and Inpul D Inpul A .. Inpul A and Inpul B Input A and Inpul B Inpul Band Inpul C Inpul D Inpul D Inpul C and Inpul D - TABLE I. ADC701 Input Connection Table. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) Connect for Buffered Input 17 ~ ,\",~ 0--<, ~ Connect for ) ...".113 V'N(11 Direct Input -& 'U-- +15V -15V +5V +15V -15V +5V Hold Buffer Output Hold 32 Input Ref 0 In 36 Ref Out 37 Ref Adj 35 39 Ref Com V 33 25 29 Analog Signal Power Commons Com Com Start Co nvert ~ I 8 1 I-'-- ~ -Common-15 21] 23 ur z ~ Optional Offset Adjust SOOlQ(6} 30kO 31 E Analog Output 12[10] Optional Gain Adjust 20kn ~ r---- SHC702 Analog Input =Analog Ground Plane (5) Iw 11 Buffer Input +15V -15V +5V -5V +15V -15V +5V -5V -!;o -::t 'r 221 2J Offset Adjust OHsel> Adjust () Z InputA(21 ~ InputB 2B I-- :IE :IE o() ADC701 Convert Command In Sample/Hold Command Out Bit 1/9 Bit 2110 Bit 3111 Bit Bit 4112 5/13 Bit Bit 6114 7/15 Bit Data 8116 Strobe 1 2 3 4 6 8 5 7 12 Hlghllow Byte Clock -Digital Common- Select Adj +5V Clip Detect 9 131 I Octal Flip-Flop 74 :: HC '~ +5V ,_______________________ 1_. 1 - - < ', ._J ___, I I I I I 0 ,,-<:.... ....,.--1> ')... 574 Optlonal(4) a ~ +5V ~ lkO Optional Clock Adjust 74HC574 o- 10~ 181 L J.J • I ~ I ,"'II (31 ......: : : I I I , : b b b b b b b b l------::I:::r:~:::r::r::f::I:::r~----.J ~-t-J Bit Bit Bit Bit Bit Bit Bit Bit 12345678 Bij 9 Bit 10 Bit 11 Bit Bit 1213 Bit 14 Bit 15 Bit 16 Clip Detect (Latched) NOTES: (1) For lowest distortion at high Input frequencies the non-buffered opUon should be used. If the buffer Is not used. Its Input should be grounded. (2) Shown connected for ±5V Input range. Refer to Input Connection Table for other options. (3) If the Clip Detect feature Is used. then the signal may be latched with a simple 0 type flip-flop as shown. See the section on ADC701 DlgltalliO for additional applications Infonnatlon. (4) The second octal flip-flop Is recommended but optional-It provides added dlgilal signal Isolation and bufferlng. and also pennlts three-state logic output compatibility. (5) All commons should be connected to the analog ground plane. Refer to the section on "Power and Ground Connections: (6) The Offset Adjust circuit shown provides an adjustment range of approximately ±D.2S% FSR. AGURE 3. ADC701/SHC702 Connection Diagram. Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-145 For Immediate Assistance, Contact Your Local Salesperson OFFSET, GAIN AND CONVERSION SPEED ADJUSTMENTS (OPTIONAL) Adjustment of the reference voltage is the most straightforward way to adjust the ADC gain. For the internal reference, this is accomplished by connecting a 20ill potentiometer as shown in Figure 3. This will provide a gain trim range of about ±3%. It is also possible to use external series or parallel resistance in the input network, but that is more cumbersome and usually wiII degrade the gain stability over temperature due to tempco (temperature coefficient) mismatches among the resistors. ADC offset may be adjusted by connecting a 500ill potentiometer to pins 21 and 22, with the wiper connected through a series 30kQ resistor to ground as shown in Figure 3. This wiII provide an offset trim range of approximately ±0.25% FSR. For a larger trim range of offset or gain, it is recommended that trims be accomplished elsewhere in the system. The Clock Adjust input (pin 18) is intended primarily for small adjustments of the conversion time. However, this will rarely be necessary because the ADC701 is guaranteed to convert up to 512kHz over the specified temperature range without external clock adjustment. POWER AND GROUND CONNECTIONS Experience with testing and applying the ADC701 shows that it wiII perform well in most board layouts, provided that appropriate care is taken with grounding and bypassing. Power supplies may be shared between the ADC70l, SHC702 and other analog circuitry without difficulty. It is recommended that each power pin be locally bypassed to the ground plane with a high quality tantalum capacitor of at least IIJ.F. If at all possible, power should be derived from well-regulated linear supplies-switching power supplies will require much more effort for proper decoupling and are not recommended for this or any high performance wideband analog system. The +5V Digital supply pins, though not as sensitive to noise as the +5V Analog pin, should nonetheless be kept as quiet as possible. If the system digital supply is noisy, then it is best to use the system +5V analog supply for all of the +5V connections on the ADC70l and SHC702 rather than trying to separate them. If only one +5V supply is available and it is shared with other system logic, then extra bypassing and/ or supply filtering may be required. The -5V supply will operate with any voltage between -4.75 and -6V. If -5V is not available from the system supplies, then an industry-standard 7905 regulator may be used to derive -5V from the -15V supply. All ground pins on both the ADC701 and the SHC702 should be connected rlirectly to a common ground plane. This is true for both analog and digital grounds. However, it is also helpful to recognize where tile digital ground currents flow in the. system,and to provide PC board return paths for 9.2-146 potentially troublesome digital currents in adrlition to the ground plane connections. For example, the ADC701 output data lines will sink current (statically and/or dynamically) when in the low state. This current comes from the power supply that runs the interface logic, and so must return to that supply's ground. If the ground termination is placed such that this digital current will flow away from the ADC70l, then the existing ground plane will suffice to carry the current. On the other hand, if the ground termination must be placed such that the rligital current flows across the ADC or SHC layout, then it would be advisable to break the analog ground plane under the package (to stop the flow of current across the package) and to provide a separate trace (several centimeters wide) on another PC board layer to carry the digital return current from pins II and 19 to the termination point. If the ADC701 must interface into a fairly noisy digital environment, then another approach is to keep the first layer of latches and/or buffers connected to the ADC701 power and ground planes, so that the ADC itself is connected to "quiet" circuits with short return paths. This transfers the interface problem to the outputs of the latches, where it can be managed with less impact on the analog components. PHYSICAL INSTALLATION The packages may be soldered directly into a PC board or mounted in low-profile machined pin sockets with good results. Use of tail (long lead length) sockets, adapters or headers is not recommended unless a local ground plane and bypass capacitors can be mounted directly under the packages. In a room-temperature environment or inside an enclosure with moderate airflow, the ADC701 and SHC702 normally do not require heat-sinking. However, to keep the devices running as cool as possible, it is helpful to install a thin heattransfer plate under the packages to conduct heat into the ground plane. The plate may be made from metal (copper, aluminum or steel) or from a special heat-conductive material such as Sil-Pad(l). The Sil-Pad material has the advantage of being electrically insulating and somewhat pliable, so that it wiII tend to distribute pressure evenly and conform to the package--an advantage in systems where the board may be flexed or subjected to vibration. PC BOARD LAYOUT EXAMPLE Figure 4 is an example of a printed circuit layout that integrates the ADC701 and SHC702 into a four-layer PC board. The layout shown includes jumper options to set the ADC input range, and shows placement of the optional offset and gain adjust potentiometers. Note that. the ground plane layer is on the component (top) side, which shields the components from digital signals on other layers and provides the possibility of using a simple heat sink plate as described above. Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customsr Service at 1·800·548·6132 (USA Only) LAYER 1 (TOP) - ANALOG GROUND PLANE LAYER 2 -±15V POWER PLANES 12 III Ii: Io u ~ io !iu- -z ::) :I :I LAYER 3 - ±5V POWER PLANES o u. o a LAYER 4 (BOTTOM) -SIGNAL LAYER - Analog o o 0 SI Inpul 0 00000000000 OOOOOOOOuOHold Command o~~IJ~lJo I ~ DO 0-000 _ _ ADC Dala Ou1pu1S 00 FIGURE 4. Example of Four-Layer PC Board Layout. Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-147 For Immediate Assistance, Contact Your Local Salesperson ADC701 DIGITAL 1/0 OPTIONS FOR STROBED OUTPUT Refer to the timing diagram, Figure 5. The conversion process is initiated by a rising edge on the Convert Command input. This will immediately bring the sample/hold command output to a logic high state (Hold mode). After the ADC701 conversion is completed (approxiinately 1.5~s after the convert command edge), the Sample/Hold Command falls to a low state, enabling the sample/hold to begin acquisition of the next input sample. However, the ADC701 internal clock continues to run so that the output data may be processed. There are two methods of reading data from the ADC: 1. Strobed Output-This will usually be the easiest and fastest method. The data are presented sequentially as high and low bytes of the total16-bit word. The sequence High-Low or Low-High is controlled by the state of the High/Low Byte Select input. The first byte is valid on the rising edge of the Data Strobe output; the second byte is valid on the falling edge. 2. Polled output-With this method, data strobes will occur as described above, but they are ignored by the user. Instead, the user waits until the Data Strobe output falls, and then manually selects high and low output data by means of the High/Low Byte Select input. This polJing procedure may be carried out during the subsequent ADC conversion cycle, but two precautions must be observed: First, the user should avoid switching the High/Low Byte Select immediately before or after the next convert command. This will prevent digital switching noise from coupling into the system at the instant of analog sampling. Second, the poIling sequence must be completed before the ADC begins to strobe out data from the subsequent conversion. There are several ways in practice to implement the logic interface. Figure 3 shows the simplest configurations. In order to convert the ADC701's byte-sequential data into 16-bit parallel form, the minimum requirement is for one single octal flip-flop, such as a 74HC574 or equivalent. This wilIlatch the first byte on the rising edge of the ADC70l Data Strobe. Then the second byte becomes valid, and all 16 bits may be strobed to the outside system on the falling edge of the Data Strobe. For better noise isolation of the ADC701 from the digital system, or if full three-state capability is required for the 16 output lines, a second octal flip-flop can be added as shown in the dashed lines of Figure 3. This will also require an inverter to convert the falling Data Strobe edge into a rising clock edge for the second flip-flop IC. If it is desirable to have all 16 output lines change simultaneously (for example when driving a D/A converter), then a third octal flip-flop (not shown in Figure 3) may be added to re-latch the output ofthe first byte. By driving that device's clock also from the inverted Data Strobe, fully synchronous switching of the 16 output bits will be achieved. USING THE CLIP DETECT OUTPUT The ADC70l provides a built-in Clip Detect signal on pin 9 which indicates an ADC overrange or underrange condition. The Clip Detect signal is only valid when the High Byte becomes valid as shown in Figure 5. Therefore, the simplest way to latch the Clip Detect signal is to provide an extra flipflop which is clocked on the same strobe edge as the High Byte flip-flop. Such a setup is illustrated in Figure 3. The Clip Detect signal remains at logic 0 under normal conditions, and indicates a clip condition by rising to a logic 1. Start Conversion Start Conversion N+l N ADC70t Convert Command (CC) :::;: Hold Command to SHC702 50nsmin~ I - CC to Hold delay 18ns typ Hold Mode 1.45~s - Data Outputs for Pin 13 = Low Low Byte, (4) DataN-l Data Outputs for Pin 13 = High High Byte.(3) DataN-l typ ~ ·I~ ·I~ X X Low Byte,(4) DataN X High Byte,(3) DataN High Byte. (3) DataN X Low Byte,(4) DataN '.55~s typ ~f Sample Mode I Data Slrobe Oulput ·r 50nsmin i (1) ~ I (1) 110ns_ typ NOTES: (1) Setup TIme 28ns min. 37ns typo (2) Hold Time 30ns min. 73ns typo (3) High Byte refers to ADC bits 1-8. the most significant 8 bits. Also, the Clip Detact signal on pin 9 is valid simultaneously with High Byte. (4) Low Byte refers to ADC bits 9-16, the least significant bits. FIGURE 5. ADC701 Interface Timing Diagram. 9.2-148 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) The latched version of Clip Detect may be used to generate an interrupt to the user's system computer, which would then launch a sePlice routine to generate the appropriate alarms or corrective action. Another possible application would be to stretch the pulse using a monostable so that it would be easily visible when driving an LED warning lamp. In some systems, it may be desirable to provide separate latched outputs for Underrange and Overrange. These conditions may be separately detected by using simple logic to implement the boolean equations: Underrange = Clip Detect AND Anybit Overrange = Clip Detect AND Anybit where "Anybit" is anyone of the data output bits. The Underrange and Overrange signals would then be latched into two separate flip-flops. A simple solution using a single '74 dual flip-flop and a single '00 quad NAND provides enough logic to implement the logic equations, with a spare NAND gate left over to use for creating the inverted Data Strobe signal. USING THE ADC701 AT MAXIMUM CONVERSION RATES The ADC701 is guaranteed to accept Convert commands at a rate of DC to 512kHz over the specified operating temperature range. At a conversion rate of 500kHz, the total throughput time of 21lS allows for the 1.51lS ADC conversion time plus 500ns for the digital output timing and sample/hold acquisition time. If the user tries to exceed the maximum conversion rate by a large amount, the Convert Command of conversion N+ I will occur before the Data Strobe has fallen from conversion N. In such a situation, the ADC70 I will simply ignore every other Convert command so the actual conversion rate will become half of the Convert command rate. Otherwise, the conversion will proceed normally. Note that the ADC timing slows down at high temperatures, so the frequency at which this occurs will vary with temperature-although it is still guaranteed to be greater than 512kHz over the specified temperature range. Another consideration for operation at very high rates is that the sample/hold acquisition time becomes shorter as the conversion rate is increased. Users will note that the available acquisition time becomes less than 550ns at rates above 500kHz, which is less than the typical SHC702 acquisition time for a 10V step to 150).1V accuracy. However, the signal degradation is gradual as the acquisition time is shortenedeven at 512kHz, there is enough time to acquire a 5V step to better than 500).1V. Also, most signal processing environments do not contain full-power signals at the Nyquist frequency, but rather show a rolloff of signal power at high frequencies. If the ability to acquire extremely large input changes at extremely high conversion rates is of paramount importance, the user may elect to use a Burr-Brown model SHC803 sample/hold instead-it is pin compatible with the SHC702 and provides much faster acquisition time at the expense of some extra noise and higher distortion at low input frequencies. Burr-Brown Ie Data Book Supplement, Vol. 33b TESTING THE ADC701/SHC702 The ADC701 and SHC702 together form a very high performance converter system and careful attention to test techniques is necessary to achieve accurate results. Spectral analysis by application of a Fast Fourier Transform (FFT) to the ADC digital output is the best method of examining total system performance. Attempts to evaluate the system by analog reconstruction through a D/A converter will usually prove unsatisfactory; assuming that the static and dynamic distortions of the D/A can be brought below the required level (-IIOdB), the performance will still be beyond the range of presently available spectrum analyzers. Even when the analysis is done using FFT techniques, several key issues must be addressed. First, the parameters of the FFT need to be adequate to perform the analysis and extract meaningful data. Second, the proper selection of test frequencies is critical for good results. Third, the limitations of commercial signal generators must be considered. These three points are addressed in later sections. Finally, the test board layout must follow the recommendations discussed on pages 8 through 10. DYNAMIC PERFORMANCE DEFINITIONS E o u ~ io -ti u -z :E :E 10 I Harmonic Power (first 9 harmonics) og Sinewave Signal Power ou . o a ~ 2. Signal-la-Noise Ratio (SNR): - _S,-in_e_w-::-a:-v-::-e_S-:i",gn_a_I_P_o_w_e_r Noise Power 3. Intermodulation Distortion (IMD): I O Iog ~ ::::» 1. Total Harmonic Distortion (THD): 10 log IIU IMD Product Power (RMS sum; to 3rd order) . . Smewave SIgnal Power 4. Spurious-Free Dynamic Range (SFDR): Power of Peak Spurious Component 10 log - -__- - - ' - - -__-~Sinewave Signal Power IMD is referred to the larger of the test signals f1 or f2-not to the total signal power, which would result in a number approximately 6dB "better:' The zero frequency bin (DC) is not included in these calculations-it represents total offset of the ADC, SHC and test equipment and is of little importance in dynamic signal processing applications. FFT Parameters Accurate FFT analysis of l6-bit systems requires adequate computing hardware and software. The FFT length (number of points) should be relatively large-at least 4K and preferably 16K or larger. There are several reasons for this: I. The converter itself has 64K codes. Ideally, the test would guarantee that all codes are tested at least once. Practically 9.2-149 For Immediate Assistance, Contact Your Local Salesperson speaking, however, that would require immensely long FFfs (»64K points) or averaging of a large number of smaller FFfs. By using an FFf length of 4K or greater and proper selection of the test frequencies, a very good statistical picture of the ADC performance will be obtained which shows the effect of any defects in the transfer function. 2. The noise floor of the output spectrum is not low enough if less than 4K points are taken. Shoner FFfs have fewer bins to cover the output spectrum, so a larger fraction of the total system noise appears in each bin. Although the SNR of the ADC701/SCH702 system is in the range of -93dB, the noise level of the available generators may increase the total measured noise power to -80dB. Every doubling of the FFT length will spread the noise power among twice as many bins, resulting in a 3dB reduction of the spectral noise floor. In order to resolve spurious components that are at the level of -l1OdB, an average noise floorofless than"'-113dB would be barely adequate. This requires at least 2048 bins in the output halfspectrum, corresponding to a 4K-point FFf. Even at this level, it will be difficult or impossible to separate higher order harmonics in the ADC701 response from the average noise level, indicating that longer FFfs are desirable. 3. Following the guidelines for test frequency selection which are outlined in the next section, it becomes clear that longer FFfs allow a much wider choice of test frequencies without concern for sophisticated data windowing or code coverage problems. Besides the consideration of FFf length, it is imponant to realize that the FFf calculations must be performed with high-precision arithmetic. The use of 32-bit fixed or floating point calculations will generally be inadequate because the noise floor due to calculation errors alone will interfere with the ADC performance data. Unfonunately, this consideration precludes the use of most DSP accelerator boards and similar hardware. In order to preserve the full dynamic range of the ADC output, it is best to use standard 64- or 80-bit arithmetic. To avoid excessively long calculation times, the FFf algorithm should be written in an efficiently compiled language and make use of techniques 'such as trigonometric look-up tables in software and dedicated floating-point coprocessors in hardware. There are several commercial software packages available from Burr-Brown and others that meet these requirements. SELECTION OF TEST FREQUENCIES The FFf (and any similar nsp operation) treats the total time-domain record length as one cycle of an infinitely long 9.2-150 periodic signal. Therefore, if the end of the sampled record does not match up smoothly with'the beginliing, the output spectrum will contain serious errors known as leakage or truncation errot2'. This well-known problem is usually handled by applying a windowing function to the time-domain samples, suppressing the worst effects of the mismatch. However, the most often used windows such as Hanning, Hamming, raised cosine, etc., are completely inadequate for 16-bit ADC testing. More sophisticated functions such as the four-sample Blackman-Harris window(3) will provide much better results, although there still will be obvious spreading of the spectral lines. ' The most successful approach is to eliminate the need for windowing by properly selecting the test signal frequency (or frequencies) in relatiQII to the ADC sampling frequency(4). If the time sample contains exactly an integer number of cycles, then there is no mismatch or truncation error. Another point to consider is that the sampling frequency should not be an exact integer mUltiple of the signal frequency, which would tend to reduce the number of different ADC codes that are tested and also tend to artificially concentrate quantization error in the harmonics of the test signal. Both of these criteria are met by choosing an FFf length which is a power of two (the most standard and fastest to compute) and choosing a test frequency which causes an exact odd integer number of cycles to appear in the time record. In software, this selection can be accomplished very easily: I. Determine the desired sampling frequency fs' 2. Determine the desired input signal frequency fAPPROX' 3. Determine the FFf length N, which should be a power of 2 (e.g., 4096 or 16384). 4. Divide fAPPROX by fs' multiply the quotient by N, and round the result to the nearest odd integer. This is M, the number of cycles in the time record. 5. Multiply M by fs and divide by N to obtain the exact input signal frequency fACTUAL' SIGNAL GENERATOR CONSIDERATIONS To suppress leakage effects, the calculated ratio of fs to fACTUAL must be precisely maintained during the test. This requirement is met easily by the use of synthesized signal generators whose reference oscillators can be locked together. Other possible approaches include external phase locking of non-synthesized generators and direct digital synthesis techniques. If it is not possible to use phase-locked sigDals, then a Blackman~Harris window may be used as mentioned previously. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) Another key issue is the purity of both the signal and sampling frequency generators. The sampling clock's phase noise (jitter) will act as another source of SNR degradation. This is not serious as long as the jitter is random and the noise sidebands contain no sharp peaks. The HP3325 synthesizer is suitable for this purpose. The input signal generator will require more attention because its distortion will usually be greater than that of the ADC701/SHC702. Presently, the lowest distortion synthesized generator is the Briiel & Kjrer Model 1051 (or 1049). This is suitable for testing the system in the audio range. The upper frequency limit of the B&K synthesizer is 200kHz. Above 20kHz, the distortion becomes a limiting factor, and low-pass filters must be inserted into the signal path to reduce the harmonic and spurious conteD!. As noted previously, the combined noise contributions ofthe signal generator and sampling clock generator far exceed the HP3325A Frequency Synthesizef n -.J L.J SNR of the ADC70l/SHC702 itself. The SNR has been measured separately by applying a highly filtered sinewave to the input, resulting in typical SNR performance of -93dB. However, the filters employed to achieve this low-noise test stimulus are found to cause reactive loading of the signal source which results in increased distortion. Therefore it is best to separate the tests for SNR from those for THD and IMD, unless a suitably pure and low-noise signal can be generated. Figures 6 and 7 show block diagrams of FFT test setups for the ADC701 and SHC702, summarizing the placement of the major components discussed above. The Typical Dynamic Performance section shows typical results obtained from testing the ADC701/SHC702 at a 500kHz conversion rate, using 16K samples for the FFT analysis. () Z :) ADC701 & SHC702 Under Test I! I! HP330 Series 9000 Computer FIGURE 6. FFT Test Configuration for Single-Tone Testing. HP3325A Frequency Synthesizer n -.J L.J +2.BV +0.2V Phase-Locked Brilet& Kj",r Type lOSt Convert Command Synthesizer ADC701 & SHC702 Under Test Briiel&Kj",r Type 1051 Synthesizer HP330 Series 9000 Computer FIGURE 7. FFT Test Configuration for Two-Tone (Intermodulation) Testing. Burr-Brown Ie Data Book Supplement, Vol. 33b ~ !; Convert Command Brilel& Kj",r Type 1051 Synthesizer () io +2.BV +0.2V Phase· Locked Iw Ii:w iE o 9.2-151 o() . o a ~ - For Immediate Assistance, Contact Your Local Salesperson HISTOGRAM TESTING The FFf provides an excellent measure of harmonic and intermodulation distortion. Low-order spurious products are primarily caused by integral nonlinearity of the SHC and ADC. The influence of differential linearity errors is harder to distinguish in a spectral plot-it may show up as highorder harmonics or as very minor variations in the overall appearance of the noise floor. converter. In practice 10 to 20 million samples will demonstrate good results for a 16-bit system and expose any serious flaws in the DL performance. If the memory incrementing hardware can keep pace with the ADC701. then 20 million samples can be accumulated in well under one minute. The last figure on page six shows the results of a 19.6 million point histogram taken at an input frequency of 1kHz. A more direct method of examining the differential linearity (DL) performance is by using the popular histogram test method (5). Application of the histogram test to the ADC701/ SHC702 is relatively straightforward. though once again extra precision is required for a 16-bit system compared to 8or 12-bit systems. Basically. this means that a very large number of samples are requited to build an accurate statistical picture of each code width. If a histogram is taken using only one million points. then the average number of samples per code is less than fifteen. This is inadequate for good statistical confidence. and the resulting DL plot will look considerably worse than the actual performance of the NOTES: 9.2-152 1. Available from Bergquist. 5300 Edina Industrial Blvd.• Minneapolis. MN 55435 (612) 835·2322. 2. Brigham, E. Oran. The Fast Fourier Transform, Englewood Oirfs, NJ.: PrenticeHall. 1974. 3. Harris, Fredric J. "On the Use of Windows for Hannonie Analysis with the Discrete FDuricrTransfonn'~ Proceedings o/the IEEE. Vol. 66, No. I. January 1978, ppSl83. . t 4. Halbert. Jocl M. and Belcher. R. Allan, "Selection of Test Signals for nSP·Based Testing of Digital Audio Systems': Journal of the Audio Engineering Society. Vol. 34. No. 718. JulylAuguSl. 1986. pp 546-555. S. "Oynamic Tests for AID Converter Pcrfonnancc". Application Note AN·133. BurrBrown Corporotion. Thcson. AZ, 1985. Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) BURR-BROWN@) ADC7802 IElElI IIII Ii: E 8 ~ Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER DESCRIPTION • TOTAL UNADJUSTED ERROR S1/2LSB OVER FULL TEMPERATURE RANGE • AUTOCAL: No Offset or Gain Adjust Required The ADC7802 is a monolithic CMOS 12-bit NO convener with internal sample/hold and four-channel multiplexer. An autocalibration cycle, occurring automali cally at power on, guarantees a total unadjusted error within ±1/2LSB over the specified temperature range, eliminating the need for offset or gain adjustment. The SV single-supply requirements and standard CS, RD. and WR control signals make the pan very easy to use in microprocessor applications. Conversion results are available in two bytes through an 8bit three-state output bus. • UNIPOLAR INPUTS: OV to 5V • MICROPROCESSOR-COMPATIBLE INTERFACE The ADC7802 is available in a 28-pin plastic DIP and 28-lead PLCC, fully specified for operation over the industrial -40"C to +8So C temperature range. • FOUR-CHANNEL INPUT MULTIPLEXER •. LOW POWER: 10mW plus Power Down Mode • SINGLE SUPPLY: +5V • FAST CONVERSION TIME: 8.511S Including Acquisition . .INTERNALSAMPL~HOLD .----""--~cs calibration Mlcrocontroller and Memory AO AI Control RD Logic WR SFR L...._ _..r---v AINO AINI AIN2 Analog Multiplexer Capacitor Array Sampling ADC AIN3 Three-5ta1e InpuUOulpul B-BR Data Bus Inllrn8lIanII A1rpcx1l11dustrll' Parle • IlaIRng AddruI: PO Box 11400 • TucIan, AZ 85734 • Stne\ Addrus: 673Q S. TUcIOn Blvd. • TucIan, AZ 857011 TeJ:(&02) 746-1111 • 1Wx:91M52'I111 • cable:BBRCORP • Telu:CI6Ji.6491 • FAX:(&02)8JI9.1510 • JmmedIallPradUclInlo:(BOO)54H132 PDS·IOSOA Burr-Brown Ie Data Book Supplement, Vol. 33b = -ti o FEATURES 9.2-153 - CJ Z ::3 :IE :IE o CJ tS a ~ - For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL V•• Vo. V",,+. 6V:t5%; V.~ Vo" V...+; V....-. AGND. DGND • OV; CLK • 2MHzextemalwl1h 50% duty cycle. T•• -10'0 10 +85'0. alter calibratiOn cycle alany temperatura; unless oIherwise specified. ADC7802IIP/ADC1802BN CONDITIONS PARAMETER MIN TYP RESOLUTION ANALOG INPUT VolJage Input Range Input Capacitance On S_ BIas Current 011 StaJa Bias Current V..+_5V. Vf&-.OV 0 MAX UNrr& 12 Bi1B 5 V pF nA nA nA 50 100 10 100 T._25'C T•• -10'0 10 +85'0 On Resistance Muldplexer 011 Resistance Multiplexer Channel Sepemllon 2 10 92 500Hz REFERENCE INPUT For Specliled Performance: V....+ V...For Deratad Performance: '" V",,+ 5 0 V....+SV. 2.5 0 v.F- Input Referance Current ntROUGHPUT TIMING Conversion TIme WIth ExtemaI Clock (Including Multiplexer Seltllng Time and AcquisitiOn Time) WIth InJamal Clock UsIng Recommended Clock ComponenlS Analog SIgnal BandwIdth ~J len Mn dB 10 V...+.5V. V...-.OV V. 1 100 8.5 17 CLK • 2MHz. 50% Duly C}de CLK - 1MHz. 50% Duly C}de CLK _ 500kHz. 50% Duty Cycle T•• +25'C T•• -IO'C 10 +85'0 34 10 10 8 Mulliple_ SeHllng TIme 10 0.01% Multiplexer Aocess Time ACCURACY Total Adjusted Enor.PJ Aft Channels Dlfferantial Nonlinearity No Missing Codes GalnEnor Gain EnorDrift OIIsetEnor 0IIse1 Error DIIIt Channel-to-Channel Mismatch Power Supply Sensitivity DlGrrAL JNPUTS An Pins Other Than CLK: V. VI< Input Current ns 460 20 :1:112 :1:112 . :1:1/4 All Channels Between Calibration C}des AU Channels Between Callbrellon C}des :1:1/4 :1:0.2 :1:1/4 V•• V o. 4.75V to 5.25V :1:1/8 O.B 2.4 1 10 O.B T•• +25'C. V". 0 10 Vo T•• -10'0 10 +85'C. V" _ 0 10 Vo 3.5 10 1.5 100 Power Down Mode (03 In SFR HIGH) POWER SUPPUES Supply Voltage for SpedJled P8Iformance: V. Vo Supply Curref!!: I. t" Power Dissipation Power Down Mode TEMPERATURE RANGE Speclflc8tiOn Storage LSB LSB ",_I.6mA 1......,.200JIA Hlgh·ZS_. V"",-OVtoVo Hlgh·Z StaJa 0.4 4 4.75 4.75 V.~Vo :1:1 15 4 ~1c.!!!!?UI ~ns HIGH or LOW WR. AD.es. BUSY - HIGH See Table III. Page 9 -10 -65 5 5 1 1 10 50 LSB ppmI'C :1:0.2 "- DlGrrAL OUTPUTS V... V... Leakage Current Oulpul Capacitance ns GuaranJaed CLK Input: V. VI< I., I., JIS JIS JIS JIS .JIS Hz mVlJlS 500 Sl8WRate~J V V V V JIA 5.25 5.25 2.5 2 LSB ppmI'C LSB LSB V V JIA JIA V V JIA mA nA V V JIA pF V V mA mA mW JlW +85 +150 '0 '0 NOTES:(I) For(V,..+)-IVIEF-) as lowas2.5V. Ihetotalerrorwilitypicallynotexceed:l:l LSB. (2) Fastarslgnalscan be accurate\y convertedbyuslnganextamalsamplel hold In front of the ADC7802. (3) Alter c:aIibraIIon cycle. without extamaI adjustment Includes gain (fuD scale) error. oHset error. Intagral nonllnealfly. d1Jferendal nonlinearity. and drift. 9.2-154 Burr-BrownIe Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES V. a Vo a V"'F+ a 5V. V"'F- a AGND a OV. T. a +25'C. unless olherwise specified. CODE TRANSITION NOISE CHANNEL SEPARATION va FREQUENCY 100 iD Eo It5 ~i r-- :-No: ~ V/ ~ -5; oo Channel AIN3'/ Channel AINI Channel AINO/ ~60 I ~100 I I I 40 i 20 o 1 10 100 1000 Frequency of 5Vp-p Signal an Channel AIN2 (kHz) 50 :f ~+ J oo \ 0.5 0.75 0.25 Analog Input Voltage - Expected Code Center (LSBs) POWER SUPPLY REJECTION va FREQUENCY ~ r---.. "- 50 g 6 4 ~i 2 go r\ Ill> .!!! ~ 25 ~~ i 0.6 0.4 ~ ;..... E .f/} o ~ ... ~ :IE :IE 8. 0.1 0.1 0.2 0.4 0.6 2 Input Frequency (kHz) 4 6 10 10 0.1 1.1 o a ~ - 1000 INTERNAL CLOCK FREQUENCY vs RClOCK 1.15 ~ 100 Frequency (kHz) INTERNAL CLOCK FREQUENCY va TEMPERATURE 10 ............... /l' 1.05 Ra.ocK ......... i o - VO 0.2 UI ~ U Z / ~.yA 1 OJ ... f8: .... .il OJ ¥ E 8 S •o-z !; - i\ 10 . . . . r-. ! IU 25 SIGNAU(NOISE + DISTORTION) va INPUT FREQUENCY 75 = Ii: '\\ 75 I a - 70kn ............... ............ 0.95 III .......r-. I'........ ............... 0.9 -50 -25 0.1 o 25 50 AmbIent Temperature ('C) 75 100 10 100 RCLOCI( (kll) lk ORDERING INFORMATION MAXIMUM MODEL ADC7602BN ADC7802BP TOTAL ERROR,LSB SPECIACATION TEMPERATURE RANGE,'C PACKAGE ±112 ±112 -40 to +65 -40 to +85 PLCC Plastic DIP Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-155 For Immediate Assistance, Contact Your Local Salesperson MECHANICAL P Paclcage - 2II-PIn Plastic DIP '-·28------- D -------,-5-1" r INeIlES MAX 1M 4; ,,'" E, .485 .55 Jt:lI= A~-I \L , - DIM L INliHES MAX MIN .100 .000 .200 t. .030 a 0" 15° .020 .070 0. 5, .040 .080 (1) NotJEDEC SIandanI. ,., "" A, MIN IMAX 12.3 2.54 lAS 15.248A! MIWMETERS MIN MAX 2.54 5.D8 0.00 0.78 0" 15° 0.51 1.78 1.02 2.03 NOTE: Leads In true position wllhln 0.01' (O.25mm) R al MMC alaealing plane. Pin numbers shown for reference only. Numbers may nol be marked on package. - ~ e,_ N Package - 28-Pln Plaatle LCC M A A, DIM ,!,~,.., \....:Pln 1 identifier ~ I r N j B,B ABSOLUTE MAXIMUM RATINGS V. to Analog Ground ............................................................................ 6.5V Vo to Digital Ground ............................................................................ 6.5V Pin V. to Pin Vo ................................................................................. :lO.3V Analog Ground to DIgi1a1 Ground ..................-..................................... :l:1V Control Inputs to Digital Ground .................................... -o.3V to Vo + O.3V Analog Input Voltage to Analog Ground ....................... -o.3V to Vo + 0.3V Maximum Junction Temperature ...................................................... I5OOC Internal Power Dlaslpation .............................................................. 875mW Lead Temperature (soldering. lOS) ................................................ +3IJOOC Thermal Resls1ance. 8...: Plastic DIP ............................................. 75"CIW PLCC ...........,......................................... 75°CIW 9.2-156 A At 8 8, C D E F G K M N P INCHES MIN MAX 0.450 0.460 0.450 0.460 0.450 0.460 0.450 0.460 0.165 0.180 0.013 0.023 0.390 0.430 0.026 0.032 0.50 BASIC 0.015 0.025 0.485 0.495 0.485 0.495 0.100 0.110 MIWMETERS MIN MAX 11.43 11.68 11.43 11.68 11.43 11.68 11.43 11.68 4.19 4.57 0.33 0.68 9.91 10.92 0.66 0.81 lZ18ASIC 0.38 0.64 12.32 12.57 12.32 12.57 2.54 2.79 NOTE: Leads In true position within 0.01' (O.25mm) R at MMC at seating plane. Pin numbers shown for reference only. Numbare may nol be marked on package. THEORY OF OPERATION ADC7802 uses the advantages of advanced CMOS technology (logic density. stable capacitors. precision analog switches. and iow power consumption) to provide a precise 12-bit anaIog-to-digitaI converter with on-chip SaI\1pling and four-channel analog-input multiplexer. The input stage consists of an analog multiplexer with an address latch to select from four input channels. Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) The converter stage consists of an advanced successive approximation architecture using charge redistribution on a capacitor network to digitize the input signal. A temperaturestabilized differential auto-zeroing circuit is used to minimize offset errors in the comparator. This allows offset errors to be corrected during the acquisition phase of each conversion cycle. Linearity errors in the binary weighted main capacitor network are corrected using a capacitor trim network and correction factors stored in on-chip memory. The correction terms are calculated by a microcontroller during a calibration cycle. initiated either by power-up or by applying an external calibration signal at any time. During conversion. the correct trim capacitors are switched into the main capacitor array as needed to correct the conversion accuracy. This is faster than a complex digital error correction system. which could slow down the throughput rate. With all of the capacitors in both the main array and the trim array on the same chip. excellent stability is achieved. both over temperature and over time. For flexibility. timing circuits include both an internal clock generator and an input for an external clock to synchronize with external systems. Standard control signals and threestate input/output registers simplify interfacing ADC7802 to most micro-controllers. microprocessors or digital storage systems. Finally. this performance is matched with the low-power advantages of CMOS structures to allow a typical power consumption of IOmW. OPERATION BASIC OPERATION Figure I shows the simple circuit required to operate ADC7802 in the Transparent Mode. converting a single inpul channel. A convert command on pin 20 (VIR) starts a conversion. Pin 22 (BUSy) will output a LOW during the +5V NC 1 SFR V. AINO AGNO 0·5V "- Inpul AINI AIN2 AI AIN3 +5V . AO VR.... CLK VREJ'"" BUSY OGND HBE •o Z VD WFi BUSY : Dala Bil7 07 cs LOW : Dala Bit 6 06 AD Read Command LOW : Data Bit 5 05 DO DalaBitO I D IaB·tS (LSB) : a I I I LOW Da(~~~)l1 : Dala Bit 4 ! 04 01 03 02 Dala Bit 1 : Dala Bit 9 I Dala Bit 3 _____ ~----- 14 L-______~~ 15 Dala Bil2 : Dala Bit 10 -----~----- HBE Inpull HBE Input LOW ! HIGH HBE Input: HBE Input HIGH I LOW -:::t Z :E :E o u. o a ~ - FIGURE 1. Basic Operation. PIN CONFIGURATIONS N Package - 28-Pln Plastic LCC P Package - 28-Pln Plastic DIP -uti TopVlow TopVlow SFR 1 28 V. AGNO CAL AI AO CLK U HBE BUSY WR HBE cc RO 05 DO 03 01 14 15 Ie CLK 06 D4 AO V... + C' I~ 02 Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-157 a For linmediateAssistance,Contact Your Local Salesperson conversion process (including sample acquisition and conversion). and rises only after the conversion is completed. The two bytes of output data can then be read using pin 18 (RD) and pin 21 (HBE). . STARTING A CONVERSION A conversion is initiated on the rising edge of the WR input, with valid signals on AO. A I and CS. The selected input channel is sampled for five clock cycles. during which the comparator offset is also auto-zeroed to below 1/4LSB of error. The successive approximation conversion takes place during clock cycles 6 through 17. Figures 2 and 3 show the full conversion sequence and the timing to initiate a conversion. CALIBRATION A calibration cycle is initiated automatically upon power-up (or after a power failure). Calibration can also be initiated by the user at any time by the rising edge of a minimum lOOnswide LOW pulse on the CAL pin (pin 26). or by setting DI HIGH in the Special Function Register (see SFR section). A calibration command will initiate a calibration cycle. regardless of whether a conversion is in process. During a calibnition cycle. convert commands are ignored. . Calibration takes 168 clock cycles. and a normal conversion (17 clock cycles) is added automatically. For maximum accuracy. the supplies and reference need to be stable during the calibration procedure. To ensure that supply voltages and reference voltages have settled and are stable. an internal timer provides a waiting period of 42.425 clock cycles between power-uplpower-failure and the start of the calibralion cycle. . READING DATA Data from the ADC7802 is read in two 8-bit bytes. with the Low byte containing the 8 LSBs of data. and the High byte containing the 4 MSBs of data. The outputs are coded in straight binary (with OV =000 hex. 5V =FFF hex). and the data is presented in a right-justified format (with the LSB as the moSt right bit in the 16-bit word). Two read operations are required to transfer the High byte and Low byte. and the bytes are presented according to the input level on the High Byte Enable pin (HBE). PIN ASSIGNMENTS PIN. NAME DESCRlP110H I SFA SpecIal Funcdon Register. When connected to a microprocessor address pin, allows access 10 speclalfunc:tJons lllrough DO to 07. Seellle a8C1fons discussing lIIe SpecIal Funcdon Register•• not used, connect 111 OOND. ThIs pin has an 1n18ma1 puR-down. 21115 AINO111 AIN3 6 7 v...+ v...- Negative voIlage reference In(iul. Normally OV. Digilal ground. DONO a OV. a DONO 9 Vo 10 to 17 DO to 07 10 07 11 12 13 14 15 16 17 06 05 D4 03 D2 01 DO .Analog InpulS. Channel 0 to channel 3. Posl1lve voltage reference Input Normally +5V. Must be S V•• logic supply voltage. Vo = +5V. MUSI be S V. and applied after V•• Data Bus Inpul/Ou1pul Pins. Nonnally used to read oUIpUI data. See s8C1fon on SFR (Special Function RegIster) for oIher uses. When SFR Is LOW, lIIese function as Ionows: Data B. 7 UHBE Is LOW; U HBE Is HIGH. acts as converter status pin and Is HIGH during conversion or calibration. goes LOW after the conversion Is completed. (Acts as an Inverted BUSY.) DaJa B. 6 UHBE Is LOW; LOW If HBE Is HIGH. DaJa B. 5 UHBE Is LOW; LOW UHBE Is HIGH. DaJa B. 4 If HBE Is LOW; LOW If HBE Is HIGH. Data B. 3 If HBE Is LOW; Data B. 11 (MSB) If HBE Is HIGH. Data B.2 If HBE Is LOW; Data Bit 10 UHBE Is HIGH. Data 1 UHBE Is LOW; Data B. 9 If HBE Is HIGH. DaJa B. 0 (LSB) UHBE Is LOW; DaJa B. a UHBE Is HIGH. a. 18 RD Read lI1'Ul ActIve LOW; used IIIl'11ad lIIe data oUIpUIs In combination with CS and HBE. 19 CS Chip Select Input. ActIve LOW. 20 WR Write Input. ActIve LOW; used to s1l!!!..! OOW conversion and 111 select an analog channel via address Inputs AO and Al In combination willi CS. The minimum WR pulse LOW wIdIh Is lOOns. High Byte Enable. Used 10 select high or low data oUIpUI byte In comblnallon with CS and RD. or to select SFR. 21 HBE 22 BUSY 23 CLK Clock Inpul For Intemallexternal cIoek operation. For extemal clock operalion, connect pin 23 to a 74 HC-c:ompatlble clock source. For Internal clock operation. connect pin 23 per !he clock operation description. 24 to 25 AOIIIAl Address Inputs. Used to select one of four analog Inpul channels In combination with CS and WR. The address InpulS are laIChed on lIIe rising edge of WR or CS. AI AO Selected Channel LOW LOW AINO LOW HIGH AlNl HIGH LOW AIN2 HIGH HIGH AIN3 26 CAL Callbrallon Inplll A calibration qcIe Is In~ted when CAL Is LOW. The minimum pulse wIdIh of CAL Is lOOns. II not used, connect to Vo' In this case calibration Is only initiated at power on, or with SFA. This pin has an Internal pull-up. 27 AGND 28 V. 9.2-158 BUSY Is LOW during conversion or calibration. 'IiUSV goes HIGH after !he conversion Is completed. Analog Ground. AGND. OV. Analog Supply. V•• .oV. MUSI be 2: Voand VIV+' Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) The bytes can be read in either order. depending on the status of the HBE input. If HBE changes while CS and RD are LOW. the output data will change to correspond to the HBE input. Figure 4 shows the timing for reading first the Low byte and then the High byte. TRANSPARENT MODE This is the default mode for ADC7802. In this mode. the conversion decisions from the successive approximation register are latched into the output register as they are made. Thus. the High byte (the 4 MSBs) can be read after the end of the ninth clock cycle (five clock cycles for the mux settling. sample acquisition and auto-zeroing of the comparator. followed by the four clock cycles for the 4MSB deci- ADC7802 provides two modes for reading the conversion results. At power-up. the converter is set in the Transparent Mode. 234 5 6 17 7 18 CLK ,, '------------------+_--------------4--------WR~, Multiplexer Sellling. Successive BUSY Approximation Conversion Offset Auto Zeroing and Sample Acquisition : "\ ' \~~i------------------+_--------------~~u FIGURE 2. Converter Timing. J,~, ~~~t2====.-'.L 1--'-. WRorCAL BUSY SFR AO.Al FIGURE 3. Write Cycle Timing (for initiating conversion or calibration). BUSY CS 1;~I---Io-~i RD / / SFR - I\. HBE 00·07 _t,r- }~-- 1,,- I\,. HI·ZStale -- t'3 t=. ,. I - '\ 1'2~ I t14.~ Low Byte Data ) - - t" -V - HI·Z t=. t'3 ( - r1,. ~ \,I .. High Byte Data FIGURE 4. Read Cycle Timing. Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-159 For Immediate Assistance, Contact Your Local Salesperson sions.) The complete 12-bit data is available after BUSY has gone HIGH. or the internal status flag goes LOW (07 when HBE is HIGH). LATCHED OUTPUT MODE This mode is activated by writing a HIGH to DO and LOWs to 01 to 07 in the Special Function Register with CS and WR LOW and SFR and HBE HIGH. (See the discussion of the Special Function Register below.) In this mode. the data from a conversion is latched into the output buffers only after a conversion is complete. and remains there until the next conversion is completed. The conversion result is valid during the next conversion. This allows the data to be read even after a new conversion is started. for faster system throughput. nMING CONSIDERAnONS Table I and Figures 3 through 8 show the digital timing of ADC7802 under the various operating modes. All of the critical parameters are guaranteed over the full-4O"C to +85"C operating range for ease of system design. SYMBOL PARAMETER '" I, es to WR Selup Time ~J t, t, WR or CAL Pulse WIdth OS to WR Hold TIme '" WR 10 BUSY PropagaUon Delay AO. AI. HBE. SFR Valid to WR Setup TIme AO. AI. HBE. SFR Valid to WR Hold Time BUSY 10 OS Setup Time OS to RD Setup 1lme ~J AD Pulse WIdIh es to AD Hold Time ~J HBE. SFR to RD Setup TIme HBE. SFR to AD Hold Time AD to Valid Data (Bus Access TIme) PI AD to HI-Z Delay (Bus Release TIme) PI RD to HI-Z Delay For SFR '" Data Valid to WR Setup TIme Data Valid to WR Hold Time ..Is Is t, Is Is ~, I" 1,. 1" 1" 1" 1" 1" SPECIAL FUNcnON REGISTER (SFR) An internal register is available. either to determine additional data concerning the ADC7802. or to write additional instructions to the converter. Access to the Special Function Register is made by driving SFR HIGH. Table II shows the data in the Special Function Register that will be transferred to the output bus by driving HBE HIGH (with SFR HIGH) and initiating a read cycle (driving RD and CS LOW with WR HIGH as shown in Figure 4.) The Power Fail flag in the SFR is set when the power supply falls below about3V. The flag also means that a new calibration has been started. and any data written to the SFR has been lost. Thus. the ADC7802 will again be in the Transparent Mode. Writing a LOW to 05 in the SFR resets the Power Fail flag. The Cal Error flag in the SFR is set when an overflow occurs during calibration. which may happen in very noisy systems. It is reset by starting a calibration. and remains low after a calibration without an overflow is completed. MIN TYP MAX UNrrs 0 100 0 20 0 20 0 0 100 0 50 0 0 0 ns ns ns ns ns ns ns ns 0 0 50 150 0 0 0 0 ns ns ns 80 90 20 100 20 ns ns ns ns ns 150 180 60 ns NOTES: (1) AIIlnpulcontrol signals are specified with ..... = 1,,,,. 20ns (10% to 90% 015V) and Umed from a voltage level 01 t.6V. Data Is timed from V... VL • V"" orVoo.' (2) The lmamal AD pulse Is perlonned by a NOR wiring 01 CS and RD. The Inlllmal WR pulse Is performed by a NOR wiring 01 CS and WR.(3) Figures 7 and 8 show the measuremenl circuits and pulse clagrams for tasting transitions to and from HI·Z staIIIs. TABLE I. Timing Specifications (CLK CS }t,I WR 'I.. r-Is-l .. = IMHz external. TAo =-40°C to +85°C). ,,,{ es 1-10- RD SFR I~ HBE 1" I Valid Data V,H VIL 1,. 1,7 I- FIGURE 5. Writing to the SFR. 9.2-160 - - 1" I~ 00·07 "- Ie -l -t,o=< 00-07 - I,. r 'I- - I,. I-- - I,. ~ ~ ~I'.""""'}.- SFRData FIGURE 6. Reading the SFR. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) Writing a HIGH to 03 in the FSR puts the ADC7S02 in the Power Down Mode. Power consumption is reduced to 50l1W and 03 remains HIGH. To exit Power Down Mode. either write a LOW to 03 in the SFR. or initiate a calibration by sending a LOW to the CAL pin or writing a HIGH to 01. During Power Down Mode. a pulse on CS and WR will initiate a single conversion. then the ADC7S02 will revert to power down. Table III shows how instructions can be transfetred to the Special Function Register by driving HBE HIGH (with SFR HIGH) and initiating a write cycle (driving WR and CS LOW with RD HIGH.) The timing is shown in Figure 3. Note that writing to the SFR also initiates a new conversion. will increase beyond this point. Input signals slewing faster than SmVfI1s can degrade accuracy. This is a result of the high-precision auto-zeroing circuit used during the acquisition phase. For applications requiring higher signal bandwidth. any good external sample/hold. like the SHC5320. can be used. INPUT IMPEDANCE ADC7S02 has a very high input impedance (input bias cutrent over temperature is 100nA max). and a low 50pF PIN FUNCTION DESCRIPTION DO Mode StalUs If LOW. Transparent Mode enabled lor data lalches. II HIGH, Latched Output 01 02 03 D4 05 CAL Flag If HIGH, cafibraUcin cycle In progress. Power Down StalUs If HIGH, In Power Down Mode. POWER FAIL Flag If HIGH, a power supply failure has occurred. (Supply IeII below 3V.) 06. CAL ERROR Flag If HIGH. an OV8r11OW accured du~ng 07 BUSY Flag caIiI,allon. If HIGH, conversion or cafibraUon In progress. Mode enabled. CONTROL LINES Table IV shows the functions of the various control lines on the ADC7S02. The use of standard CS. RD and WR control signals simplifies use with most microprocessors. At the same time. flexibility is assured by availability of status infonnation and control functions. both through the SFR and directly on pins. INSTALLATION . Reserved lor lactory use. Reserved lor lactory use. IIo -~ -z U NOTE: These data are tranlerred to the bus when a reed cycle Is Initialed with SFA and HBE HIGH. Reading the SFR with SFR HIGH and HBE LOW INPUT BANDWIDTH ::::» Is reserved lor lactory use at this lime, and will yield unpredlc:table data. From the typical perfonnance curves. it is clear that ADC7S02 can accurately digitize signals up to 500Hz. but distortion Enables Transparent Mode 10, Data Lafl:hes. Enables Lalched OuJput Mode 10, Data Lafl:hes. Initiates Calibra110n CvcJe. Resets Power FaIIlJag. Activates Power Down Mode Ii Ii TABLE II. Reading the Special Function Register. cs/wR SFRlHBE DO 01 03 D5 D7 D21D41D6 LOW LOW LOW LOW LOW HIGH HIGH HIGH HIGH HIGH LOW HIGH X X X X X HIGH X X LOW LOW LOW LOW HIGH X X X LOW X LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW ou o -a ~ NOTES: (1) In Power Down Mode, a pulse on CS and WR will Initiate a sIngle conversIon, then the ADC7802 will revert to power down. (2) X means II can be either HIGH or LOWwithout aIIectIng this action. Writing HIGH to 02, 03, D4 or 06, or writing with SFR HIGH and HBE LOW, may ,esullin unpredictable behavior. These modes are reserved lor lactory use at this time. TABLE III. Writing to the Special Function Register. III cs RO WR SFR "BE CAL BUSY OPERATION X X 1 0 0 0 0 0 0 0 X X X 1 0 0 1 0 X X X X X X 0 0 0 1 1 X X X X 0 1 1 Ofl 1 1 1 0 0 1 X 0 X 1 X X 1 X X X Initiates calibration c:ycIe. convarsJon or caIi>raIIon In process. Inhibits new conversion lrom starting. None. OuJputs In HJ.Z State. Initiates conversion. Low byte corrverslon results OU1put on data bus. High byte conversion results OU1put on data bus. W~te to SFR and rising edge on WR Initiates conversion. Contents 01 SFR OuJpul on date bus. Reserved lor Iactory use. Reserved lor lactory use. (UnpredJctabJe data on data bus.) Ofl 1 1 1 0 1 0 0 1 1 X 1 1 1 1 1 1 TABLE IV. Control Line Functions. Burr-Brown Ie Data Book Supplement. Vol. 33b 9.2-161 For Immediate Assistance, Contact Your Local Salesperson input capacitance. To ensure a conversion accurate to 12 bits, the analog source must be able to charge the SOpF and settle within the first five clock cycles after a conversion is initiated. During this time, the input is also very sensitive to noise at the analog input, since it could be injected into the capacitor array. In many applications, a simple passive low-pass filter as shown in Figure 9a can be used to improve signal quality. In this case, the source impedance needs to be less than Skn to keep the induced offset errors below I/2LSB, and to meet the acquisition time of five clock cycles. The values in Figure 9a meet these requirements, and will maintain the full power bandwidth of the system. For higher source impedances, a buffer like the one in Figure 9b should be used. INPUT PROTECTION The input signal range must not exceed ±VREF or VA by more than O.3V. The analog inputs are intemally clamped to VA' To prevent damage to the ADC7802, the current thai can flow into the inputs must be limited to 20mA. One approach is to use an external resistor in series with the input filter resistor. For example, a Ikn input resistor allows an overvoltage to lOV without damage. REFERENCE INPUTS A IOJ.1F tantalum capacitor is recommended between VREF+ and VREF- to insure low source impedance. These capacitors should be located as close as possible to the ADC7802 to reduce dynamic errors, since the reference provides packets of current as the successive approximation steps are carried out. VREf+ must not exceed VA' Although the accuracy is specified with VREF+ = SV and VREF- = OV, the converter can function with VREF+ as low as 2.SV and VREF-as high as IV. As long as there is at least a 2.SV difference between VREF+ and VREf-' the absolute value of errors does not change significantly, so that accuracy will typically be within ±ILSB. (l/2LSB for a SV span is 61 OJ1V, which is lLSB for a 2.SV span.) The power supply to the reference source needs to be considered during system design to prevent VREF+from exceeding (or overshooting) VA' particularly at power-on. Also, after power-on, if the reference is not stable within 42,425 clock cycles, an additional calibration cycle may be needed. POWER SUPPUES The digital and analog power supply lines to theADC7802 should be bypassed with 10J.1F tantalum capacitors as close 5V ADC7802 Output ADC7802 Output I3kO ~ Jc. :rF I 31<0 Test Test Polm CL polm (a) Load ClrcuR (a) Load ClrcuR Output "Outpm Vo Enable G~----~~~------ __ VD vD ---;:::::::-"'ok- Enable ____ G~------~~~----------- v(lH -------1----;-1., ---+-------------- G~ VOL ---+-----rr -----j--:--H-------(b) From HIGH to HI·Z. G.- lOpF (b) From LOW to H~Z. C. - 10pF Output VD Output VD Enable Enable Gnd VD VOL G~ ---"':1 X,,-O_'8_V___ - (e) From HI-Z to LOW. CL • 50pF FIGURE 7. Measuring Active LOW to/from Hi-Z State. 9.2-162 1~ . "q~:-t.-------72.4V G~ - - - - - - - - - - -..... (e) From HI·Z to HIGH. ~ • SOpF FIGURE 8. Measuring Active HIGH to/from Hi-Z State. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) to the part as possible. Although ADC7802 has excellent power supply rejection. even for higher frequencies. linear regulated power supplies are recommended. Care should be taken to insure that V0 does not come up before VA' or permanent damage to the part may occur. Figure 10 shows a good supply approach. powering both VA and Vo from a clean linear supply. with the IOn resistor between VA and V0 insuring that V0 comes up after VA' This is also a good method to further isolate the ADC7802 from digital supplies in a system with significant switching currents that could degrade the accuracy of conversions. GROUNDING To maximize accuracy of the ADC7802. the analog and digital grounds are not connected internally. These points should have very low impedance' to avoid digital noise feeding back into the analog ground. The VREf- pin is used as the reference point for input signals. so it should be connected directly to AGND to reduce potential noise problems. EXTERNAL CLOCK OPERATION The circuitry required to drive the ADC7802 clock from an external source is shown in Figure Ila. The external clock must provide a 0.8V max for LOW and a 3.SV min for HIGH. with rise and fall times that do not exceed 200ns. The minimum pulse width of the external clock must be 300ns. Synchronizing the conversion clock to an external system clock is recommended in microprocessor applications to prevent beat-frequency problems. as shown in the typical performance curves. Therefore. use of an external clock source is preferred in many applications where control of the conversion timing is critical. or where multiple converters need to be synchronized. APPLICATIONS BIPOLAR INPUT RANGES Figure 12 shows a circuit to accurately and simply convert a bipolar ±5V input signal into a unipolar 0 to SV signal for conversion by the ADC7802. using a precision. low-cost complete difference amplifier.INAI05. Figure 13 shows a circuit to convert a bipolar ±IOV input signal into a unipolar 0 to SV signal for conversion by the ADC7802. The precision of this circuit will depend on the matching and tracking of the three resistors used. To trim this circuit for full 12-bit precision. R2 and R3 need to be adjustable over appropriate ranges. To trim. first have the ADC7802 converting continually and apply +9.9927V (+IOV -1.5LSB) at the input. Adjust R3 until the ADC7802 output toggles between the codes FFE hex and FFF hex. This makes R3 extremely close toRI. Then.apply-9.9976V (-IOV + O.SLSB) at the input. and adjust R2 until the ADC7802 SFR CAL CLK BuSY OGNO WR The clock generator can operate between 100kHz and 2MHz. With R = IOOkn. the clock frequency will nominally be 800kHz. The internal clock oscillators may vary by up to 20% from device to device. and will vary with temperature. 14 Analog HBE 07 CS 06 AD 05 DO D4 01 03 02 15 loon Input ~ ToADC7802 '6 22nF v R..... (Nonnally OV) Ion FIGURE 10. Power Supply and Reference Decoupling. (a) Passive Low Pass Filler Analog Input ~~PA27 1 74HC'CO~tible Clock Source ToADC7802 '6 VREf""(NonnallyOV) (b) ActIve Low Pass Filler FIGURE 9. Input Signal Conditioning. Burr-Brown Ie Data Book Supplement, Vol. 33b I CLK ' To ADC7802 Pin 23 (a) Exlemal Clock Operation + C I R +5V ~ T~A0C7802 PI023 Z ::I - AI AO Figure 11b shows how to use the internal clock generating circuitry. The clock frequency depends only on the value of the resistor. as shown in "Internal Clock Frequency vs RCLDCK" in the Typical Performance Curves section. -u o u. o a ~ AGND INTERNAL CLOCK OPERATION o = -ti Ii! Ii! V. Note that the electrical specification tables are based on using an external 2MHz clock. Typically. the specified accuracy is maintained for clock frequencies between O.S and 2.4MHz. . 'CLOCK (In Hz) • 10"/R (b) Internal Clock Operation FIGURE 11. Internal Clock Operation. 9.2-163 For Immediate Assistance, Contact Your Local Salesperson output toggles between 000 hex and 001 hex. At each trim point, the current through the third resistor will be almost zero, so that one trim iteration will be enough in most cases. More iterations may be required if the op amp selected has large offset voltage or bias currents, or if the +SV reference is not precise. This circuit can also be used to adjust gain and offset errors due to the components preceding the ADC7802, to match the performance of the self-calibration provided by the converter. INTERFACING TO MOTOROLA MICROPROCESSORS Figure 14 shows a typical interface to Motorola microprocessors, while Figure 15 shows how the result can be placed in register DO. Conversion is initiated by a write instruction decoded by the address decoder logic, with the lower two bits of the address bus selecting an ADC input channel, as follows: INA105 r 1 ~V 25110 2 251<0 5 L~ 25110 Input 25kO V read instruction to ADC-ADDRESS as follows: MOVEP.W $000 (ADC-ADDRESS), DO This puts the 12-bit conversion result in the DO register, as shown in Figure IS. The address decoder must pull down ADC_CS at ADC-ADDRESS to access the Low byte and ADC-ADDRESS +2 to access the High byte. INTERFACING TO INTEL MICROPROCESSORS Figure 16 shows a typical interface to Intel. A conversion is initiated by a write instruction to address ADC_CS. Data pins DOO and DOl select the analog input channel. The BUSY signal can be used to generate a microprocessor interrupt (INT) when the conversion is completed. A read instruction from the ADC_CS address fetches the Low byte, and a read instruction from the ADC_CS address +2 fetches the High byte. +5V (v...+) H~ 010SV 6 MOVE.W DO, ADC-ADDRESS The result of the conversion is read from the data bus by a loADC7802 :tl0V Input Rt 10110 Ro 0105V lOADC7802 Ro -:- 3 ) ..sV (VRE...) FIGURE 12. ±SV Input Range. FIGURE 13. ±lOV Input Range. AI·A23 \ - - - - - - - - - : : - - - (AO·A19) Intel Microprocessor Based Systems MC6S000 (MC6S008) _ AS BACK 1 - - - - - - - 1 Riii 1-.....-1 8085 8086188 801861188 80286 8031 8051 iii 1 - - - - - - - 1 Wii 1 - - - - - - 1 ADC7802 FIGURE 14. Interface to Motorola Microprocessors. 31 FIGURE 16. Interface to Intel Microprocessors. 2423 FIGURE 15. Conversion Results in Motorola Register DO. 92-164 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) BURR - BROWN® PCM78P IElEElI IIII ~ III o = C) 16-Bit Audio a C. ANALOG-TO-DIGITAL CONVERTER FEATURES APPLICATIONS • LOW COST/HIGH PERFORMANCE 16·BIT AUDIO A/D CONVERTER • DSP DATA ACQUISTION Io • TEST INSTRUMENTATION • SAMPLING KEYBOARD SYNTHESIZERS • FAST 5115 MAX CONVERSION TIME (4115 TYP) • DIGITAL AUDIO TAPE • BROADCAST AUDIO PROCESSING • VERY LOW THD+N (TYP -88dB AT FS; MAX-82dB) :::) I! Ii o u. o • TELECOMMUNICATIONS • ±3V INPUT RANGE • TWO SERIAL OUTPUT MODES PROVIDE VERSATILE INTERFACING -tc -uz - • COMPLETE WITH INTERNAL REFERENCE AND CLOCK IN 28·PIN PLASTIC DIP D ~ • ±5V TO ±15V SUPPLY RANGE (600mW POWER DISSIPATION) DESCRIPTION The PCM78P is a low-cost 16-bit ND converter which is specifically designed and tested for dynamic applications. It features very fast, low distortion perfonnance (4J.1S/-88dB THD+N typical) and is complete with internal clock and reference circuitry. The PCM78P is packaged in a reliable, low-cost 28-pin plastic DIP and data output is available in user-selectable serial output fonnats. The PCM78P is ideal for digital audio tape (DAT) recorders. Many similar applications such as digital signal processing and telecom applications are equally well served by the PCM78P. The PCM78P uses a SAR technique. Analog and digital portions are efficiently partitioned into a highspeed, bipolar section and a low-power CMOS section. The PCM78P has been optimized for excellent dynamic perfonnance and low cost. Audio Input CD l"- I! C) Convert Command Do Status PDS·989A Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-165 For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL Tc= +25°C. +Voo= +5V. and ±Vcc = ±12V, and one minute warm·up in convection environment. unless otherwise noted.. PCM78P PARAMETER CONDITIONS TYP MIN MAX UNITS 16 Bits +3 V kO RESOLUnON INPUT/OUTPUT ANALOG INPUT Inpul Range Inpul Impedance DIGITAL INPUT/OUTPUT Logic Family Logic Level: V1H V" VOH V",- -3 1.5 TTL Compatible CMOS I" = -t40~ I, = -100~' IOH = 2TTL Loads 101. = 2TTL Loads Data Format Conven Command Pulse Width "I l~' o +2.4 +0.8 . . +0.4 Serial BOB or B C Negative Edge I') 25 CONVERSION nME J 50 4 J V V V V ns 5 I1S DYNAMIC CHARACTERISTICS SIGNAL-TO-NOISE RAnO (SNR)'" , = 1kHz (OdB) I = 10kHz (OdB) fs = 200kHzlTCONY = 41J.S{31 BW = 20kHz BW = 100kHz 80 dB TOTAL HARMONIC DISTORnON" f = 1kHz (OdB) f = 19kHz (OdB) I = 10kHz (OdB) 1 = 90kHz (OdB) Is = 200kHzlTOONV = 4118 :BW = 20kHz BW = 20kHz BW = 100kHz BW = 100kHz -91 -90 -90 -89 dB dB dB dB TOTAL HARMONIC DISTORnON + NOISE'. 1 = 1kHz (OdB) 1 = 1kHz (-2OdB) f = 1kHz (-8OdB) 1= 19kHz (OdB) f = 10kHz (OdB) 1 = 90kHz (OdB) Is = 200kHzlT00", = 411S BW = 20kHz BW = 20kHz BW = 20kHz BW = 20kHz BW = 100kHz BW = 100kHz dB(4) 90 . -88 -74 -34 -87 -82 -82 -68 .:al dB dB dB dB dB dB TRANSFER CHARACTERISncS ACCURACY Gain Error Bipolar Zero Error Differential Linearity Errqr Integral Linearity Error Missing Codes DRIFT Gain Bipolar Zero O'C 10 +70'C O'C to +70'C POWER SUPPLY SENSITIVITY +Vcc -Vee +Voo ±2 ±20 ±D.002 ±0.003 None % mV %01 FSR'" %oIFSR ±25 ±4 ppml'C ppm 01 FSRI'C ±D.008 ±D.003 ±D.003 %FSRI'IoV" 14 Bitsl') %FSR/O/OVcc %FSRl%Voo POWER SUPPLY REQUIREMENTS Voltage Range: +V0' +4.75 -4.75 +4.75 -Vee +Voo Current: +Vcc +Vcc -Vee -Vee +VOD Power Dissipation = +12V = -12V +15.6 -15.6 +5.25 V V V mA mA mA mW +70 +100 +85 'C 'C 'C +15 -21 +7 575 +VOD = +5V ±Vee = ±12V TEMPERATURE RANGE Specification Storage Operating 0 -50 -25 NOTES: (1) When conven command is high, converter is in a haltlreset mode. Actual conversion begins on negative edge. See detailed text on timing lor conven command description when using external clock. (2) Ralio 01 Noise rmslSignal rms. (3) 1= Inpul Irequency; Is =sample lrequency (PCM78P and SHC702 in combination); BW = bandwidth 01 oulput (based on FFT or aclual analog reconstruction using a 20kHz low·pass Iilter). (4) Referred to input signal level. (5) Ratio 01 Distortion rmsiSignal rms. (6) Ratio 01 Dislortion rrns + Noise rrnslSignal rrns. (7) FSR: Full·Scale Range = 6Vp-p. (8) Typically no missing Codes al 14-bil resolution. 9.2-166 Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) MECHANICAL P Package - 28-Pln Plastic DIP ------- D -------1 INCHES MIWMETERS MIN MAX MIN MAX A"' .169 .200 4.29 5.08 A,II, .015 .070 0.38 1.78 0.51 B .015 .020 0.38 B, .015 .055 0.38 1.40 .012 . 0.20 0.30 C .008 OtIJ 1.380 1.455 35.05 36.96 E .600 .625 15.24 15.88 E,ll/ .485 .550 12.32 13.97 2.54 BASIC .100 BASIC 0' 15.24 BASIC o. .600 BASIC DIM -1 E, o o DIM L Lz a Q, S, INCHES MIN MAX .100 .200 .000 .030 15° 0° .020 .070 .040 .080 MILLIMETERS MIN MAX 5.08 2.54 0.76 0.00 0° 15° 0.51 1.78 2.03 1.02 (1) Not JEDEC Standard NOTE: Leads In true poslUon within 0.010 (O.25mm) R at MMC at seating plane. Pin numbers shown lor relerence only. Numbers may not be markad on package. IIII ~ E 8 S •o-z ~ INPUT/OUTPUT RELATIONSHIPS DtGITAL OUTPUT ANALOG tNPUT CONDITION BTC BOB +2.999908V + Full Scale -Full Scale Bipolar Zero Zero·l LSB 7FFF Hex 8000 Hex 0000 Hex FFFF Hex FFFF Hex 0000 Hex 8000 Hex 7FFF Hex ~.OOOOOov o.OOOOOOV -Q.000092V +V= to Analog Common ..........................................................0 to +16.SV -V= to Analog Common ........................................................... 0 to·~16.SV -V DO to Analog Common ......................................................, ........ 0 to +7V Analog Common to Digital Common ................................................ ±ll.SV Logic Inputs to Digital Common ..................................-O.3V to V" + O.SV Analog Inputs to Analog Common ..................................................:!:16.SV Lead Temperature (soldering, 108) ••••.••••••••••••••••••.••••••••••.••••••••••••• +3000C Stresses above these ratings may pennanentiy damage the device. PIN ASSIGNMENTS -vee 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MSB Adjust +VOD No Connection Comparator Common MSB BTC/BOB Select Status Clock Out R,C, R,P2 S""" +VOD S""" External Clock IntlExt Clock Select ShonCycle Conven Command S""" Latch SOU" Clock Digital Common +Vcc V"" Relerence Decouple Analog Common Relerence Out Speed Up Analog Signal Input (1.5Kn Impadance). Analog power supply (-5V to -15V). Intemal adjustment point to allow adjustment 01 MSB major carry. Power connection lor comparator (+5V). No internal connection. Comparator common connection. Connect to ground. Parallel output 01 bit 1 (MSB) invened. Two·s complement (open) or straight binary (grounded) data output lonnat selection. Output signal held high until conversion is complete. Internal clock output generated Irom RC network on pins 11 and 12 (also present when external clock is usad lagging external clock by -24ns and same duty cycle). RC connection point used to generate internal clock. Sets clock high time. See text lor detailsRC connection point used to generate internal clock. Sets clock low time. See text lor details. Internal shift register containing the previous conversion result. (Altemate latchad data output mode). Power connection lor +5V logic supply. Primary real·time data output synchronized to clock oUl Extemal clock input point (internal clock must be disablad). Selects either Internal or external clock mode (lOW = internal; open = external). Terminates conversion at less than 16·bits (open for 16-bit mode). See text lor details. Starts conversion process (can optionally be generated Internally). LalChes previous conversion result lor readout (must be Issued with the S""" clock to Initiate lalCh and an internal command). Used to read out Internally la!chad data from previous conversion. Digital grounding pin. Analog supply connection (+5V to +15V). Voltage output (-2.5V) lor optional adjustment 01 MSB transition. Reference decoupling point Analog grounding pin. 2V relerence out. Should not be used except as shown In connection diagram. Connection point lor a capacitor to speed .relerence settling. See text lor details. NOTE: Analog and digital commons are connectad internally. Burr-Brown Ie Data Book Suppil.'ment. Volo 33b -:::»z C) ABSOLUTE MAXIMUM RATINGS 9.2-167 I! I! 8. -oa ~ Fa; Immediate Ass/stance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES T,. = +25°C, Vee = ±15V unless otherwise noted. BIPOLAR GAtN ERROR as % FSR 25"C; N =33 UNITS 18 " - - - " - - " T BPZ ERROR vs TEMPERATURE 10mV 9mV 8mV I - 7mV w 6mV SmV ~ 4mV --- '. ./ "" """' ./ ./ V 16 14 12 10 8 6 3mV 4 2mV 2 lmV o 0 o -25 25 70 -.40 -.35 125 -.45 PSRR at +FS INPUT 0.012 0,01 0.008 0.006 0.004 " *' 0.002 ~+Vcc *' -0.0020 .,,-0.004 -0,01 -25 o V - 0.01 .......... Voo ~ ,-Vee 0.008 ! '" 0.006 *' 0.004 ./" /+Vee .-'............ 0.002 70 o -25 125 ------ 70 25 125 Temperature (OC) Temperature (OC) Iss vs SUPPLY VOLTAGE VREF vsTEMP 2.002 21 2.000 1.998 ~ '<.I oo - o 25 -.SO 0.012 ...... ./ .r"-..... f-"" . / -o.ocia -.55 PSRR at -FS INPUT - -Vee "- -0.006 -.50 %FSR Temperature (OC) 1.996 V ~ 1.994 > - 1.992 1.99 1.988 -25 ./ - 16 15 o -Vee ~ / +Vcc 14 25 Temperature (OC) 9.2-168 / 20 / 70 125 4 6 8 10 12 14 16 Supply Voltage Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES (cont) T" = +25°C. Vee = ±15V unless othelWise noted. DIFFERENTIAL NONLINEARITY al-25'C INTEGRAL NONLINEARITY al-25'C 7.00 1.40 6.00 1.20 5.00 4.00 en '" ..J 1.00 I'- I I\. 3.00 "- ""- / 2.00 '"~ 1/ 1.00 0.80 0.60 0.40 t- V / \ II \ / / -1.00 1 () a C 0.00 2 3 4 5 6 7 8 1 9 10 11 12 13 14 15 16 2 3 4 I!III Ii: io / 0.20 0.00 -- - / ..- :0- f-' - 5 6 7 8 9 10 11 12 13 14 15 16 Major Carry Bil Number Major Carry Bil Number io -:::»z !; 1.40 1\ 4.00 lD '" 1\ 2.00 \ 1.00 0.00 1.00 i'- til ~ \ -1.00 / 1.20 \ 3.00 ..J ....... -- -- \IJ 0.80 l- V- I- V / ........ 0.20 ....... V 0.00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 o . o ..... -a 7 8 9 10 11 12 13 14 15 16 Major Carry Bil Number INTEGRAL NONLINEARITY a125'C DIFFERENTIAL NONLINEARITY 81 25'C 5.00 1.40 4.00 r\ I 1,\ 3.00 2.00 1.00 6 I 1\ 0.00 \ II -1.00 f\. 1.20 V 1.00 " til ........ ........ ~ r-... l - r--. r-.... -2.00 / 0.80 '/" 1\ 0.60 J 0.40 .... V- - ..... v J \ V 0.20 '/" 0.00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Major Carry 811 Number Burr-Brown Ie Data Book Supplement, Vol.33b 1 2 3 4 5 6 7 :& :& () V Major Carry Bit Number '" I ..- ..... 0.60 0.40 ........ -2.00 en ..J () DIFFERENTIAL NONLINEARITY al0'C INTEGRAL NONLINEARITY aIO'C 5.00 8 9 10 11 12 13 14 15 16 Major Carry BII Number 9.2-169 ~ For Immediate Assistance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES (cont) T. =+25'C. Vcc = ±15V unless otherwise noted. Histograms done with conversion time =8ps. INTEGRAL NONLINEARITY at70'C 7.00 '6.00 :- 5.00 III ~ DIFFERENTIAL NONLINEARITY at70'C 1.80 1/,\ \ 1.60 \ 1.40 I\ 1.20 4.00 !\ 3.00 m ~ "-1'- 2.00 1.00 0.80 0.40 :-- ,.- ~ r"o.. \I \ V / 0.60 1.00 I lit _\ '-i1 r- - 0.20 0.00 0.00 1 3 2 4 5 7 6 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Major Carry Bit Number Major Carry Bit Number INTEGRAL NONLINEARITY at 125'C DIFFERENTIAL NONLINEARITY at 125'C 2.50 3.00 2.00 ~ 1.00 \ \ 0.00 '" -1.00 ~ -2.00 2.00 ......... i........ I-- b-t-. \ \ \ ..;3.00 -4.00 -5.00 - "- '\ 1.50 m ~ V 1.00 1 1\ 1\ 0.50 -6.00 -7.00 V V - 0.00 1 2 3 4 5 6 7 8 1 9 10 11 1213 14 15 16 2 3 4 5 6 /\ J 7 a \,1 9 10 11 12 13 14 15 16 Major Carry Bit Number Major Carry Bit Number INTEGRAL NONLINEARITY ERROR (tol4-Bit LSB) DIFFERENTIAL NONLINEARITY ERROR (to 14-Bit LSB) 1.50 r - - - - - r - - - - r - ' - - - . . . , - - - - , 2.00 1.00 I - - . ' - - - - - t - - - - ! - - - - + - ' - - - - - I 1.50 0.50 HIr.-~.~t;;_____.li;;;;:-:t----+-'----I 1.00 0.00 -0.50 m ~ I----t-~-'-I. 0.50 -1.00 1----t----!--'--'---PR"'-'H1'I 0.00 I----+----t----+---'---I -0.50 -1.50 -2.00 L-_ _-.1._ _ _....L.._ _ _...l.-_ _- - ' -8192 -4096 0.000 BIN 9.2-170 4096 8192 -1.00 -8192 -4096 0.000 4096 8192 BIN Burr-Brown Ie Data Book Supplement. Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES (cont) T, =+25°C, Vee =±15V unless otherwise noted. SPECTRAL RESPONSE, I,"' 1kHz SPECTRAL RESPONSE, 0 Input Frequency 976.6Hz Fund: -o.07dB 6th: -135.02dB -87.BOdB THO: -87.IOdB 2nd: 3rd: -97.43dB SNR: BI.05dB 4th: -102.35dB SINAO: BO.09dB 5th: -107.BSdB -20 m E. " -40 -60 "C .~ '" '" ::; m ., E. -40 -60 "C .~ -80 '" '" ::; -100 -80 U -100 -120 25 50 75 100 25 50 Frequency (kHz) SPECTRAL RESPONSE, -40 -60 "C ~ ~ ::; 75 100 t," • 1kHz m E. " ~ '"'" ::; -80 -100 -120 -60 Z ~ :IE :IE 0 U 0 .. -80 -a -100 -120 25 50 75 100 ~ 25 Frequency (kHz) 50 75 100 Frequency (kHz) SPECTRAL RESPONSE, t,"' 1kHz SPECTRAL RESPONSE, \. • 20kHz 0 -20 m ., E. Fund: 2nd: 3rd: 4th: 5th: -40 -60 "C a '2 -80 '" -100 CI ::; Input Frequency 976.6Hz -60.06dB 6th: -IOB.COdB -109.ISdB THO: -42.15dB -10B.3IdB SNR: 21.73dB -134.66dB SINAO: 21.69dB -114.73dB ~O m E. " ~ ~ ::; -120 I---~ Fund: 2nd: -40 I---~ 3rd: 4th: -60 5th: Input Frequency 19970.7Hz -li9.9edB 6th: -IIO.lldB -109.09dB THO: -41.6OdB -124.49dB SNR: 21.93dB -116.40dB SINAO: 21.SSdB -112.ISdB -80 -100 -120 25 50 75 100 Frequency (kHz) Burr-Brown Ie Data Book Supplement, Vol. 33b Z 0 U Input Frequency 19970.7Hz Fund: -19.94dB 6th: -107.32dB 2nd: -105.69dB THO: -72.S1dB 3rd: -95.9OdB SNR: 61.60dB 4th: -106.7IdB SINAO: 61.2SdB -97.57dB 5th: -40 • - SPECTRAL RESPONSE, I•• 20kHz -20 a C. -ti Frequency (kHz) Input Frequency 976.6Hz Fund: -20.07dB 6th: -110.06dB 2nd: -IOS.36dB THO: -76.75dB 3rd: -100.44dB SNR: 61.79dB 4th: -I I 1.52dB SINAO: 61.65dB 5th: -102.06dB -20 m " IIII Ii:III I0 20kHz Input Frequency 19970.7Hz Fund: -o.OBdB 6th: -101.44 -+-1.--- PCM78P 5 9 8 X: Off 5 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X 0 X 0 X X X 0 0 0 X X X X 0: On FIGURE II. Short Cycle Circuit. CC~~________________________~ 1/ __ __ I ' - - - - - 'I Status ~r---------:J F - - - - - ' Conversion Time r------~ F----~ {J- {J- L L L FIGURE 12. Short Cycle Operation Timing. Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-177 CD r0- :& () A. For Immediate Assistance, Contact Your Local Salesperson w c:r:: :=J fX H LL Z o H f- ([ :=J -.J ([ > W 0... S- ?~~ ON; ,"', SI+ ',,(= 17-----_"-":·;SI- :. CIL·::: f""- L U 0... FIGURE 13a. Recommended PC Board Layout. 9.2-178 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Serllice at 1-800-548-6132 (USII UIII1I (T') ..... FIGURE I3b. Recommended PC Board Layout. Burr-Brown Ie Data Book Supplement, Vol.33b 9.2-17~ I For Immediate Assistance~ Contact Your Local Salesperson If Short Cycle is not held low until the next convert command is issued, the Status line will go high in synchronization with Short Cycle. This is because the operation of the Status line becomes invalid after Short Cycle is asserted. An example of the Short Cycle operation is shown in Figure 12. In those systems where a user may not be using a continuous external clock, it is necessary to assure that a faIling edge of external clock occurs after short cycle goes low. This is because conversion actually stops on the first faIling edge of external clock after Short Cycle goes low. ANALOG CIRCUIT CONSIDERATIONS Layout Precautions Analog and Digital Common are connected internally in the PCM78, and should be connected together as close to the unit as possible, preferably to a large ground plane under the ADC. Low impedance analog and digital common returns are essential for low noise performance. Coupling between analog inputs and digital lines should be minimized by careful layout. The input pin (pin I) and the MSB adjust pin (pin 3) are both extremely sensitive to noise; digital lines should be kept away from these pins to avoid coupling digital noise into the sensitive analog circuitry. Figure 13 shows a recommended PCB layout for the PCM78. Power Supply Decoupling The power supplies should be bypassed with tantalum or electrolytic capacitors as shown in Figure 14 to obtain noise free operation. These capacitors should be located as close to the ADC as possible. Bypass the IJ.lF electrolytic capacitors with O.OIJ.lF ceramic or polystyrene capacitors for improved high frequency performance. decoupling capacitor should range from O.IIlF to 4.7J.lF; larger values can cause reference settling problems which may manifest themselves as missing codes. This capacitor should be as close to the PCM78 as possible, to minimize the potential for coupling noise into the device; with a good board layout it may be best to leave this capacitor out of the circuit altogether, as the extra lead length may only cause more noise in the reference. Pin 27 is a decoupling point to ground, as well as the output of the 2V reference. This point should not be used to supply reference voltage to external circuitry unless it is buffered. A 2.21lF capacitor is recommended, and the capacitor used here should not exceed 4.7IlF. Pin 28, the Speed Up pin, allows a capacitor to be connected to ground to facilitate reference settling. This does not speed up the conversion time, but it does reduce odd order harmonic distortion. As with the. decoupling capacitor on pin 25, this may also contribute to noise; if harmonic content is most important in an application, this capacitor (O.IJ.lF IOIlF) should be connected. In all other cases, it is best to leave the capacitor out of the circuit. Input Scaling The analog input should be scaled as close to the maximum input signal range as possible in order to utilize the maximum signal resolution of the AID converter. The DAC inside the PCM78 has a ±2mA range, and the nominal ±3V input is scaled by a 1.5ill resistor. In order to scale to other ranges, see Table I for recommended scaling resistor values, connected as shown in Figure IS. INPUT RANGE ±10V ±5V I R I 8.2kn 3.3kn NOTE: R values shown assume use of lk trim pot to adjust for scale accuracy. TABLE I. PCM78 Input Scaling Resistor Values. +Vcc ~~ ~~~ 23 4 t+Voo .±L .l~F ~OI~F PCM78 PCM78 'Use to trim for exact scaling. Use trim pot with temperature coefficient of 100ppmf'C or better. FIGURE IS. PCM78 Input Scaling Circuit. INPUT IMPEDANCE .OI~ ~J; H -Vee FIGURE 14. Recommended Power Supply Decoupling. Reference Decoupllng and Speed Up In order to assure the lowest noise operation of the PCM78, the reference may be bypassed by three different capacitors. Pin 25 is a decoupling point for the reference to -Vcc' The 9.2-180 The input signal to the PCM78 should come from a low impedance source, such as the output of an op amp, to avoid any errors due to the dynamic input impedance that a successive-approximation converter presents to the the outside world because of the changing currents in this circuit during conversion as the converter steps through its approximations. If the driving circuit output impedance is not low, a buffer amplifier should be added between the input signal and the direct input to the PCM78 as shown in Figure 16. Burr-Brown Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) SO~l PCM76 Clk Out ~ ______________~IDR 1-------.....------~IClk A +5V +5V lMS3:!lC25IC3O r-+--~IFSR PCM78P FIGURE 16. Buffer Amplifier for PCM78 Input. MSB Adjustment Differential Linearity errors at bipolar zero and THD are guaranteed to meet data sheet specifications without any external adjustment. However, a provision has been made for an optional adjustment of the MSB linearity point which makes it possible to eliminate DLE error at BPZ. This is important when the signal level is very low, because zero crossing noise (DLE at BPZ) becomes very significant when compared to the small codes changes occurring in the LSB portion of the converter. The PCM78 is laser trimmed for best performance at the factory without the MSB adjust circuitry installed; if better performance can be obtained it would be by the addition of the MSB adjust circuitry shown in Figure 17. The best method of adjusting the MSB is by using a real time FFT routine to monitor the levels of odd order harmonics when a sine-wave is being digitized by the PCM78. Adjusting the potentiometer in Figure 17 will allow the user to reduce the magnitude of odd-order harmonics. An alternate method is to recontruct the data out of the PCM78 through a DAC, and measure THD+N on a conventional distortion analyzer. Adjust the potentiometer for minimum THD+N. -v cc 200kO 220KO V pOT Status IIII Ii: o = a () FIGURE 18. PCM78 Interface to TMS32OC25{C30 DSP Processors. SO~l \---------------_1 RXD Clk Out \-------_-------1 AXC +5V PCM78P C ur z - o !; +5V DSP56001 r--±---IFSA - () Z ~ Status NOTE:FSM= Bit Mode ••o . () FIGURE 19. PCM78 Interface to Motorola DSP56001 nsp Processor. SOUTt Data In o is ~ 2r-----~~------~~----{:~ ~~,~ ClkOut PCM18P FIGURE 17. MSB Adjust Circuit. ICK DSP32C IlD APPLICATIONS INFORMATION NOTE:Setfcr l&Si:exIemaI A typical digitization circuit, used on the demonstration board available for the PCM78, is shown in Figure 21. The connections and part values shown in this ~ircuit have been optimized for the best THD+N performance at a 200kHz sample rate. ILD.ICKMSB bllist The PCM78 may be interfaced to many popular digital signal processors, such as the TMS320, DSP56001, and the DSP32. Suggested interface circuits for these processors are shown in Figures 18-20. Burr-Brown Ie Data Book Supplement, Vol. 33h FIGURE 20. PCM78 Interface to AT&T DSP16 & DSP32C Processors. 9.2-181 ....CD •a. () 10 N ..... I ~ ,'5 I' LIP, 2.,.F'\7 ~ ~ ... ." Q if Reconstructed ";;":~ 0u1pU1 = CD Q. ~" CD· 61 8 :Do = R, ;;;" ;r 3ldl :::a C"a CA, IN4148IN4t48 +5 ~CD ~ +5 Q ea $:: :::a ~ s"", b:, ~ c::: ~ ?=5 Q C"a ~ Sea QJ C I') QJ err .;: ~ t.o:l I CD SmMo~ __+-__________________________________________________- - J ~ :- ~ :- v.. ~ C"a ,5 ~ ~ -... .... ;r FIGURE 21. Schematic for Demonstration Board (DEMI122). ~ Q :::a Or, Call Customer Service at 1-800-548-6132 (USA Only) BURR-BROWN® PCM1700P IE:lE:lI ADVANCE INFORMATION SUBJECT TO CHANGE Dual 18-Bit M DIGITAL-TO-A •-o Z FEATURES ti - () and voltage supplies. The an internal reference even greater THD dissipati
One Clock Cycle _ _ _ > One Clock Cycle_ FIGURE 1. PCM1700P Setup and Hold Timing Diagram. T PCM1700P ( ) Basic Model Number P: Plastic Perfonnance Grade Code - - - - - - - - - - - - - ' ==-r-- ABSOLUTE MAXIMUM RATINGS DC Supply Voltages .....•.....•..••.............•........•.......•.....•••..•......•...• ±7.5VDC Input Logic Voltage .................................................................. -W to +Vcc Power Dissipation ....•...•.....•..................•..•••..••..•.......•....•...•••.••.•..•• 500mW Operating Temperature ...•..••........•..•.••..•.•..•••.•..••..•....•..••.. -25'C to +70'C Storage Temperature •....•••.••.••••••••.•..•.•.•...••••...••..•.•..••..•• -60'C to +100'C Lead Temperature (soldering. lOs) ................................................ +300'C Burr-Brown Ie Data Book Supplement, Vol. 33b P13 (Clock) I fl n n n n n n n n n n n n UUUUI..JUUUUUUUUL P12~~ Data(L)~~ MSB LSB P16~ Data(R)~ P15 (Latch Enable) ~ :E :E o u. o a ~ - Input/Output Relationships. ____ -ti u -z ~ LSB l L...J.I_ __ ____~7L FIGURE 2. Timing Diagram. 9.2-185 o ...f!:E ua. For Immediate Assistance, Contact Your Local Salesperson +5V~~--~--------------~--------------------~~ FIGURE 3. Vour (R) NOTES: (1) Low TCR resistors such as Vishay. FIGURE 4. Current Output Connection Diagram. 9.2-186 Burr-Brown Ie Data Book Supplement. Vol.33b Or, Call Customer Service at 1-800-548-6132 (USA Only) BURR-BROWN® PCM1750P IElElI 12 IU ADVANCE INFORMATION SUBJECT TO CHANGE Ii: E o () Dual CMOS 18ANALOG-TO- ~ oz -o~ () true cosiiniple/ho'id amplifiers for also comes complete reIl:q;~lce. Total power dissipation is using ±5V voltage supplies. Hannonic Distortion + Noise (tested. The very fast PCM1750P oversampling rates on both input i¢lii sinlUl\;aneously, providing greater freedom to in selecting input anti-aliasing filters. • COIIIIPL.ETES'WITHiINTI:RNIALREF:ER··.. { outputs serial dam in a format that is .. compatible with many digital filter chips and comes packaged in a space saving 28-pin plastic DIP. r;;:~=:=J--+-o Clock ~~~~-I-o Convert SIH MSBAdj Righi o-t-=-=::==~~============~_..J International Airport industrial Park • Mailing Address: PO 80111400 • Tucson, AZ B5734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (602)746-1111 • TWx: 9111-952·1111 • CabIe:BBRCORP • Telel:06H491 • FAX: (602) 889-1510 • ImmadIaIaProductlnla:(IIDD)54U132 PDS·I084 Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-187 Z :::) Ii Ii o() tS -a ~ For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL At 25'C, ancl±Vcc= ±5.0V and +Voos +5.0V unless olherwlsa noted. Where relevant, specifications apply to both Iell and rightlnputloUlpUt channels. CONDITIONS ANALOG tNPUT Input Range Input Capacitance Aperture Time Aperture Jitter Full Power BandWidth DIGITAL INPUT/OUTPUT Logic Family Logic Level: V V. V"" VOl Data Format Convert Command Convert Command Pulse Width dB~1 ACCURACY Gain Error Gain Mismatch Bipolar zero Erro~" BPZ Error Mismatch BPZ Differential Unearlly Unearity Error -88 -68 -28 dB dB dB f2 ±D.S f2 ±3 ±D.002 ±D.003 ±5 % % mV mV %ofFSR"I %ofFSR minute 100 20 250 ppmI'C ppm of FSRI'C ±5.00 +28 -13 ±5.25 V rnA rnA 210 300 mW ±1 Warm-up Time ±4.75 SpecIfication Operating Storage 'C 'C 'C NOTES: (1) Binary Two's Complement coding. (2) Ratio of Slgn",-/ Noise.... from20 Hz to 20kHz. (3) AID converter sample frequency (4 X 48kHz; 4 times oversampllng per channel). (4) AID converter Input frequency/signal level (on both Iell and right channels).(5) Relered 10 Input signal level. (6) Ratio 01 (DiSlOrtio,,+ Noise....) / Signal..... (7) Extemally adjustable to zero error. (8) Differential non·linearlly at bipolar major cartY input code. Measured in 16-bit LSB's. Adjustable to zero error. (9) Full Scale Range. 9.2-188 Burr-Brown Ie Data Book Supplement, Vol, 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) MECHANICAL P Package - 28-Pln Plastic DIP r------- A ------; NOTE: Leads In lrue poslUon wllIlln 0.01" (0.25mm) R al MMC al seating plane. Pin numbers are shown lor raleranca only. Numbers may nol be marked on package. Case: Plasllc Welghl: 4.3 grams (0.1502.) . (I) Z o -~ () Z ;::) :IE :IE o() . o is ~ o ...:IEIe () a. -:h- - CoMect directly to ground plane Burr-Brown Ie Data Book Supplement, Vol. 33b 9.2-189 For Immediate Assistance, Contact Your Local Salesperson 64 1 2 3 4 5 6 7 8 9 1011 1213141516 'Optional Digital Filter P11 (CONVERT) ~'--_____......;._ _..;...._~_ _ :1 :---:--:---:--~fL :3 :19 P4 (EXT ClK IN) P3 (SOUT l) P12(SOUTR) FIGURE I. JIIIJlUl/'-'UI!1UP:l', T5 T6 T7 T8 T9 TCONV (64. TREF) TREF (Sample Rate /64) DESCRIPTION Convert Command High SIH Acquisition nme Convert to Clock time Mester Clock Input Clock High Clock Low Data Hold nme Data Setup nme Data Valid Time Conversion Throughput nme Ext Digital Alter Clock MIN 25 420 281 211 25 75 10 120 4.5 70 33 486 326 244 33 67 154 5.2 8t 50 1302 9n 50 50 100 1212 20.8 326 UNITS %ofT4 ns ns ns %ofT4 %ofT4 ns ns ns lIS ns FIGURE 2. Setup and Hold Timing Diagram. 9.2-190 Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1-800-548-6132 (USA Only) VOLTAGE-TO-FREQUENCY CONVERTERS Voltage-to-frequency converters provide a simple, low-cost way of converting analog signals into digital form. They provide an important alternative to other analog-to-digital conversion techniques. Their integrating input properties make them an appropriate choice when operating in noisy environments. The combination of high accuracy and linearity, low temperature drift, and monotonicity often provides performance characteristics unattainable with other techniques. Since an analog quantity represented as a frequency is inherently serial data, it is easily handled in large multi-channel systems. Frequency information can be transmitted over long lines with excellent noise immunity using low cost digital line transmitters and receivers. Isolation can be accomplished with optical or transformer couplers without loss in accuracy. Outputs from multiple VFCs can be gated to common counter circuitry with simple digital logic. Low-cost isolation is obtained when a VFC is used together with DC/DC converter and a single optical coupler. Burr-Brown monolithic voltage-to-frequency converters provide industrystandard performance and reliability in such applications as precision test and measurement equipment, data acquisition systems, communications equipment, and process control. Burr-Brown Ie Data Book Supplement, Vol. 33b 10-1 For Immediate Assistance, Contact Your Local Salesperson VOLTAGE-TO-FREQUENCY CONVERTERS SELECTION GUIDE The Selection Guide shows parameters for the high grade. Refer to the Product Data Sheet for a full selection of gmdes. Models shown in. boldface are new products introduced since publication of the previous Burr-Brown IC Data Book. Boldface = NEW VOLTAGE·TO-FREQUENCY CONVERTERS Description Model (V) Linearity, max ("IoofFSR) Tempco, max (ppm of FSRI"C) Temp Rangel" Userselected 500kHz, max Userselected ±a.Ol at 10kHz ±O.OS at 100kHz 7Styp ±100 Frequency Range (kHz) V.. Range Pkg Page Com Ind DIP,SOIC TO-l00, LCC 10-3 10-3 Low-Cost Monolithic VFC32P,U VFC32M, L Low-Cost Complele VFC42 VFCS2 01010 010100 010+10 010+10 ±a.Ol ±O.OS ±100 ±lS0 Ind Ind DIP DIP 10-12 10-12 Precision Monolilhic VFC62 VFC320 User" selecled Userselected 1MHzmax ±a.002 all OkHz ±0.002 at 10kHz ±20 ±20 Ind Ind DIP, TO-l00 LCC 10-18 10-54 SynochroVFC100G nized Monolilhic Clock Programmed 2MHzmax 010 +10 0.1 al1MHz ±so Ind DIP 10-26 VFC101N Clock Programmed, 2MHzmax 010 +10, Oto +S, .010+8, -5lo+S ±a.02 al100kHz ±40 Ind PLCC 10-41 HighPerformance VFC110 Userselected 4MHzmax Ota +10 ±a.os at 1MHz ±SO Ind DIP, LCC S10-3 Single Supply, Low Power VFC121 User· selected 1.SMHzmax . User· selected ±a.03.at 100kHz ±40 Ind DIP S10-11 NOTES: (1) Com = O°C 10 +70°C, Ind = -2SoC 10 +8SoC. 10-2 Burr-Brown IC Data Book Supplement, Vol. 33b. Or, Call Customer Service at 1-800-548-6132 (USA Only) BURR-BROWN@ VFC11 0 1-=--=-1 High-Frequency VOLTAGE-TO-FREQUENCY CONVERTER FEATURES APPLICATIONS • HIGH-FREQUENCY OPERATION: 4MHz FS max • INTEGRATING AID CONVERSION 12 III Ii: E o u • PROCESS CONTROL • VOLTAGE ISOLATION • VOLTAGE-CONTROLLED OSCILLATOR • EXCELLENT LINEARITY: ±O.02% typ at 2MHz • PRECISION 5V REFERENCE tz III • FM TELEMETRY • DISABLE PIN ~ (J • LOW JITTER III II: DESCRIPTION II. The VFC II 0 voltage-to-frequency converter is a thirdgeneration VFC offering improved features and performance. These include higher frequency operation, an on-board precision 5V reference and a Disable function. The precision 5V reference can be used for offsetting the VFC transfer function, as well as exciting transducers or bridges. The Enable pin allows several VFCs' outputs to be paralleled, multiplexed, or simply to shut off the VFC. The open-collector frequency VOUT Comparator 12 11 ~ III Internal input resistor, one-shot and integrator capacitors simplify applications circuits. These components are trimmed for a full-scale output frequency of 4MHz at IOV input. No additional components are required for many applications. ~ ~ The VFCIIO is packaged in plastic and ceramic 14:pin DIPs. Industrial and military temperature range gradeouts are available. 8 V IN • output is TTL/CMOS-compatible. The output may be isolated by using an opto-coupler or transformer. fOUT 2 1--'VI1Ir-~......-I Input Common 14 1-----1--1 7 Digital Ground ' - - - - - - - - - 1 5 Enable 4 13 3 6 -Vs Analog Ground 5V Cos InternatIOnal AIrpart Industrial Park • Mailing Address: PO Bax 11400 Tel: (602) 746-1111 • Twx: 9111-952·1111 • cable: BBRCORP • • TUcson, AZ 85734 Street Address: 6730 S. TUcson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (602) 889-1510 • Immediate Product Infa: (SOD) 5~132 PDS·86IA Burr-Brown Ie Data Book Supplement, Vol. 33b 10-3 For Immediate Assistance, Contact Your Loeal Salesperson SPECIFICATIONS At T. =+25·C and V, =±15V unless otherwise noted. VFC110AGlSGIAP VFC110BG PARAMETER CONDITIONS VOLTAGE-TO-FREQUENCY OPERATION Nonlinearity''': I" = 100kHz 1,,= lMHz 1,,=2MHz IFS= 4MHz Gain Error. I = 1MHz Gain Orift. I = 1MHz Relative to VREF PSRR INPUT FuJI Scale Input Current 1,- (Inverting Input) 1,+ (Non-Inverting Input) Ves Ves Drift Coo - 2.2nF. RN - 44kn Cos • l5OpF. RN • 40kQ Cos· 56pF. RON· 34kQ Cos - (Int). RN • (Int) Cos • 15OpF. RN • 40kQ SpeclflQd Tel1)p Range Specified Temp Range V.=±8Vto±18V ENABLE INPUT VHOH (I"", Enabled) VUlW (lOUT Disabled) 0.01 0.05 MAX UNITS 0.01 0.05 0.1 %FS %FS %FS %FS % ppml"C ppml"C %IV 0.1 · · 500 60 35 -0.2 5 No Oscillations +Vs-4 20 10 ·· -5 ±SO -5 +V. · · 3 · ·· 15 5 2 5 20 5.03 20 10 2 0.4 · · 0.1 1 POWER SUPPLY Voltage. ±V, Current ±8 TEMPERATURE RANGE Specilied AG. BG.AP SG Storage AG.BG.SG AP · -25 -55 -55 --40 ±15 13 ±18 16 +85 +125 +150 +125 · ·· · ·· · ·· ·· nA nA mV "VfOC V mA nF 10 I1A mV V ·· · 4.97 I1A 100 0.4 0.1 1 25 25 One Pulse 01 New Frequency Plus 1flS To Specified Unearity lor a FuJI-Scale Input Step Specified· Temp Range Specified Temp Range · 20 ·· 10=Oto 10mA V. = ±8V to ±18V ShortCircutt · 100 100 0.05 Specified Temp Range f\ =2kQ TYP ·· 50 'HIGH 10-4 0.005 0.01 0.02 1 MIN 5 50 I",. • Same specilications as VFCll OBG. NOTE: (1) Nonlinearity measured from MAX 3 COMPARATOR INPUT I, (Input Bias Current) Trigger Vollage Input Vollage Range REFERENCE VOLTAGE Vollage Vollage Drift Load Regulation PSRR Current Limit TYP 250 15 250 INTEGRATOR AMPLIFIER OUTPUT Oulput Vollage Range Oulput Current Drive Capacitive Load OPEN COLLI'CTOR OUTPUT Va Low ILEAKAGE Fall TIme Delay to Rise Settling Time MIN · · 50 · ·· · ·· V . I1A ns ns V ppmfOC mV mVIV mA V V I1A I1A V mA ·C ·C ·C ·C tv to 10V Input. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA. Only) MECHANICAL P Package -14-Pln Plastic DIP ,{::::::u 1 'I D $l fl Pin,'" a, E e. A, ~ A -:1"' t.:, --II_B a L Seating C DIM A A, B B, C D E E, eL e. L 12" a P Q, S'" INCHES MILLIMETERS MIN MAX MIN MAX .120 .160 3.048 4.064 .015 .065 .381 1.651 .014 .020 .355 .508 .050 .065 1.270 1.651 .008 .012 .203 .304 .745 .770 18.923 19.558 .300 .325 7.620 8.255 .240 .260 6.096 6.604 2.540 BASIC .100 BASIC 7.620 BASIC .300 BASIC .125 .150 3.175 3.810 .762 0 .030 0 O· 15 o· 15' .050 1.270 .050 .085 1.270 2.159 .085 .090 1.651 2.286 NOTE: Leads In true position within 0.01" (0.2Smm) Rat MMC at seating plane. (1) e, and e. apply in zone L, when unit Is installed• (2) Not per JEDEC. Z! III ~ E o() G Package -14-Pln Hermetic DIP DIM A C 0 F G H J K L M N INCHES MIN MAX .710 .670 .065 .170 .015 .021 .045 .060 .100 BASIC .025 .070 .012 .008 .120 .240 .300 BASIC 10' .009 .060 MILUMETERS MIN MAX 17.02 t8.03 1.85 4.32 0.38 0.53 1.14 1.52 2.54 BASIC 0.64 1.78 0.20 0.30 3.05 6.10 7.62 BASIC 10' 0.23 t.52 NOTE: Leads in true position within 0.01" (0.25mm) R at MMC at seating plane. Pin numbers shown lor relerence only. Numbers may not be marked on package. t zIII ~ G III a: IL I olI III PIN CONFIGURATION ABSOLUTE MAXIMUM Top View 14 V,N Input Common Analog Common +SVREF Out VOUT Comparator In -Vs Enable NC Digital Ground 7 fOUT ~ RATlNG~ Power Supply Voltages (+V. to-V,) ................................................. 40V lOUT Sink Current ............................................................................. SOmA Comparator In Voltage ........................................................... -5V to +V, Enable Input ........................................................................... +V, to-V. Integrator Common-Mode Voltage .................................. -1.SV to +I.SV Integrator Differential Input Voltage ................................ +O.SV to -o.SV Integrator Out (short-circuit) ..................................................... Indefinite VREF Out (short-circuit) .............................................................. looeOnite Operating Temperature Range G Package .................................................................-5S'C to +12S'C P Package ................................................................... -40'C to +8S'C Storage Temperature G Package .................................................................-60·C to +IS0'C P Package ................................................................. -40'C to +12S'C Lead Temperature (soldering. lOs) ............................................ +300'C ORDERING INFORMATION MODEL VFCll0AG VFCll0BG VFCll0SG VFCll0AP PACKAGE TEMPERATURE RANGE Ceramic DIP Ceramic DIP Ceramic DIP Plastic DIP -2S'C to +BS'C -2S'C to +BS'C -5S'C to +12S'C -2S'C to +BS'C Burr-Brown Ie Data Book Supplement. Vol_ 33b 10-5 ~ ......o ~ For Immediate Ass/stance, Contact Your Local Salesperson TYPICAL PERFORMANCE CURVES At T. = +25'C, V. = ±15V unless otherwise noted • FULL-SCALE FREQUENCY vs EXTERNAL ONE-SHOT CAPACITOR . FULL-SCALE FREQUENCY vs EXTERNAL ONE-SHOT CAPACITOR 18 10M . ~ ....... ~ 1M 14 )10 " lOOk ~ ., E R'N =40kO 8 id 6 8 4 l.-' - 10 + I--""" §. 12 I., ~ --- 16 « 10 - 2 o 10k 10pF 100pF InF 10nF -50 lOOnF o -25 Extemal One-Shot Capacitor REFERENCE VOLTAGE vs REFERENCE LOAD CURRENT' > 125 1000 5 ~ 100 75 TYPICAL FULL SCALE GAIN DRIFT vs FULL SCALE FREQUENCY 5.01 ~ 25 50 Temperature ('C) l"- I-- - I-- 4.99 4.98 AGrade, SG rade I. BGrede Short Circuit I-CurrentUmij 4.97 I 4.96 o 2 4 8 10 12 14 16 Output Current (mA) 18 20 10 10k 22 10M 1M lOOk Full Scale Frequency (Hz) FREQUENCY COUNT REPEATABILITY vs COUNTER GATE TIME JITTER vs FULL SCALE FREQUENCY 500 0.001 O_OOOS 400 E ~ II 300 V f-"" 100 ~ 0.0004 !!l 0.0002 l o I-17 "- i' "" fFS = 100kHz I'- lOOk 1M Full Scale Frequency (Hz) 10M Jitter is the ratio of the I (J value of the distribution of the period (1IfOUT , max) to the mean of the period. I l-18 ,., II i :5a: 19 fFS = IMHz I II 0.0001 10k 10-6 0.0006 Jg ./ ~ ~ 200 ~ ~ Ims lOOms 10ms Is Time This graph describes the low frequency stability of the VFCll0: the ratio of the I" point of the distribution of I 00 runs (where each mean frequency came from 1000 readings for each gate time) to the overall mean frequency. Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES (CONT) T. A +25'C. V. A ±15V unless othelWlse noted. NONLINEARITY vs INPUT VOLTAGE ~ 0.02 W .~ " :5 en u. ~ ~ 0.8 I--- l-- '0 & e NONLINEARITY vs FULL SCALE FREQUENCY / 0.01 \ 'FS A4MHz o ~ - / """=:::::~ ~ -0.01 0.6 0.4 \ 0.2 0 V 234 6 Input Voltage (V) 7 C w 'iij t: 9 0.1 2> " 'Iii / c ?J0 "c Z -0.4 en u. -0.6 N :J: ::; -0.8 -1 o '0 !; ::J 'FS = lMHz -0.02 12' If '0 ~ 2> -0.2 !-"'" 12' en u. / 0.01 12 III 1! ! " Ii: 0.001 10 10' 10· Full Scale Frequency (Hz) E o u OPERATION Figure I shows the connections required for operation at a full-scale output frequency of 4MHz. Only power supply bypass capacitors and an output pull-up resistor, Rpu' are required for this mode of operation. A OV to IOV input voltage produces a OHz to 4MHz output frequency. The internal input resistor, one-shot and integrator capacitors set the full-scale output frequency. The input is applied to the summing junction of the integrator amplifier through the 25kf.l internal input resistor. Pin 14 (the non-inverting amplifier input) should be referred directly to the negative side of VIN' The common-mode range of the integrating amplifier is limited to approximately - I V to + I V referred to analog ground. This allows the non-inverting input to Kelvin-sense the common connection of VIN' easily accommo- dating any ground-drop errors. The input impedance loading VIN is equal to the input resistor-approximately 25kf.l. tz III OPERATION AT LOWER FREQUENCIES The VFCllO can be operated at lower frequencies simply by limiting the input voltage to less than the nominal IOV fullscale input. To maintain a IOV FS input and highest accuracy, however, external components are required (see Table I). Small adjustments may be required in the nominal values indicated. Integrator and one-shot capacitors are added in parallel to internal capacitors. Figure 2 shows the connections required for 100kHz full scale output. The pne-shot capacitor, Cos' should be connected to logic ground. The one-shot connection (pin 6) is not short-circuit protected. Short-circuits to ground may damage the device. ::) G III ...a:• e• III ~ ~ NC 10 11 Rpu 680n .---+-_--0 'OUT ..fi! 0104MHz o 010 +10V > 13 • Nominal Values (±20%) 3 6 NC NC Analog Ground FIGURE I. 4MHz Full-Scale Operation. Burr-Brown Ie Data Book Supplement, Vol. 33b 10-7 For Immediate Assistance, Contact Your Local Salesperson The integrator capacitor's value does not directly affect the output frequency, but determines the magnitude of the voltage swing on the integrator's output. Using a CINT equal to Cos provides an integrator output swing from OV to approximately 1.5V. COMPONENT SELECTION Selection of the external resistor and capacitor type is important. Temperature drift of an external input resistor and oneshot capacitor will affect temperature stability of the output frequency. NPO ceramic capacitors will normally produce the best results. Silver-mica types will result in slightly higher drift, but may be adequate in many applications. A low temperature coefficient film resistor should be used for RIN • The integrator capacitor serves as a "charge bucket," where charge is accumulated from the input, VIN' and that charge is drained during the one-shot period. While the size of the bucket (capacitor value) is not critical, it must not leak. Capacitor leakage or dielectric absorption can affect the 4MHz 2MHz lMHz 500kHz 100kHz 50kHz 10kHz PULL-UP RESISTOR The VFC II 0' s frequency output is an open -collector transistor. A pull-up resistor should be connected from fOUT to the logic supply voltage, +V L. The output transistor is On during the one-shot period, causing the output to be a logic Low. The current flowing in this resistor should be limited to SmA to assure a 0.4V maximum logic Low. The value chosen for the pull-up resistor may depend on the full-scale frequency and capacitance on the output line. Excessive capacitance on fOUT will cause a slow, rounded rising edge at the end of an output pulse. This effect can be minimized by using a pullup resistor which sets the output current to its maximum of SmA. The logic power supply can be any positive voltage up to +Vs. ENABLE PIN EXTERNAL COMPONENTS FULL-SCALE FREQUENCY, f,. linearity and offset of the transfer function. High-quality ceramic capacitors can be used for values less than 0.01J.IF. Use caution with higher value ceramic capacitors. High-k ceramic capacitors may have voltage nonlinearities which can degrade overall linearity. Polystyrene. polycarbonate, or mylar film capacitors are superior for high values. R.. Cos C", 34kn 40kn 5Bkn 44kn BBkn 44kn 56pF ,150pF 330pF 2:2nF 2.2nF 22nF 2nF 10nF O.I"F O.I"F If left unconnected, the Enable input will assume a logic High level. enabling operation. Alternatively, the Enable input may be connected directly to +Vs. Since an internal pull-up current is included, the Enable input may be driven by an open-collector logic signal. . • Use internal component only. The values given were determined empirically to give the optimal performance, taking into consideration tradeoffs between linearity and jitter for each given full scale frequency of operation. The capacitors listed were chosen from standard values of NPO ceramic type"capacitors while the resistor values were rounded off. Larger CINT values may improve linearity. but may also increase frequency noise. A logic Low at the Enable input causes output pulses to cease. This is accomplished by interrupting the signal path through the one-shot circuitry. While disabled, all circuitry remains active and quiescent current is unchanged. Since no reset current pulses can occur while disabled, any pOsitive input voltage will cause the integrator op amp to ramp negatively and saturate at its most negative output swing of approximately -O.7V. TABLE 1. Component Selection Table. ' R'N 10nF 12 NC 2 14 13 3 NC Cos 2.2nF High = Enable Low~ Disable FIGURE 2. 100kHz Full-Scale Operation. 10-8 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) PRINCIPLE OF OPERATION The VFCII0 uses a charge-balance technique to achieve high accuracy. The heart of this technique is an analog integrator formed by the integrator op amp, feedback capacitor Coo' and input resistor RIN • The integrator's output voltage is proportional to the charge stored in C INT • An input voltage develops an input current of VIN/RIN' which is forced to flow through Coo' This current charges C 1NT, causing the integrator output voltage to ramp negatively. When the output of the integrator ramps to OV, the comparator trips, triggering the one-shot. This connects the reference current, IREF' to the integrator input during the one-shot period, Tos' This switched current causes the integrator output to ramp positively until the one-shot period ends. Then the cycle starts again. The oscillation is regulated by the balance of current (or charge) between the input current and the time-averaged Effect of OV --~~~--------~~-t------ fOUT 12 III reset current. The equation of current balance is lIN = IREF • Duty Cycle ~ VIN/RIN = IREF • fOUT • To where To is the one-shot period and fOUT is the oscillation frequency. Io () When the Enable input receives a logic High (greater than +2V), a reset current cycle is initiated (causing fOUT to go Low). The integrator ramps positively and normal operation is established. The time required for the output frequency to stabilize is equal to approximately one cycle of the final output frequency plus IllS. Using the Enable input, several VFCs' outputs can be connected to a single output line. All disabled VFCs will have a high output impedance; one active VFC can then transmit on the output line. Since the disabled VFCs are not oscillating, they cannot interfere or "lock" with the operating VFC. Locking can occur when one VFC operates at nearly the same frequency as--or a multiple of--a nearby VFC. Coupling between the two may cause them to lock to the same or exact multiple frequency. It then takes a small incremental input voltage change to unlock them. Locking cannot occur when unneeded VFCs are disabled. REFERENCE VOLTAGE The VREF output is useful for offsetting the transfer function and exciting sensors. Figure 3 shows VREF used to offset the transfer function of the VFCllO to achieve a bipolar input voltage range. Sub-surface zener reference circuitry is used for low noise and excellent temperature drift. Output current is specified to lOrnA and current-limited to approximately 20rnA. Excessive or variable loads on VREF can. decrease frequency stability due to internal heating. MEASURING THE OUTPUT FREQUENCY To complete an integrating AID conversion, the output frequency of the VFCllO must be counted. Simple frequency counting is accomplished by counting output pulses for a reference time (usually derived from a crystal oscillator). r;Z III ~ G III ~ II. e•• III ~ g +5V 12 R, + Y'N .---1-------0 R. fOUT ......o 2 NC 14 -:- ~ 4 -15V 5V FIGURE 3. Offsetting the Frequency Output. Burl'-Bl'ovm Ie Data Book Supplement, Vol. 33b 10-9 For Immediate Assistance, Contact Your Local Salesperson This can be implemented with counter/timer peripheral chips available for many popular microprocessor families. Many micro-controllers have counter inputs that can be programmed for frequency measurement. standard deviation (10) count variation (as a percentage of FS counts) versus counter gate time. Since fOUT is an open-collector device, the negative-going edge provides the fastest logic transition. Clocking the counter on the falling edge will provide the best results in noisy environments. The VFClIO can also be connected as a frequency-tovoltage converter (Figure 4). Input frequency pulses are applied to the comparator input. A negative-going pulse crossing OV initiates a reference current pulse which is averaged by the integrator op amp. The values of the oneshot capacitor and feedback resistor (same as RJN) are determined with Table I. The input frequency pulse must not remain negative for longer than the duration of the one-shot period. Figure 4 shows the required timing to assure this. If the negative-going input frequency pulses are longer in du'ration, the capacitive coupling circuit shown can be used. Level shift or capacitive coupling circuitry should not provide pulses which go lower than -5V or damage to the comparator input may occur. Frequency can also be measured by accurately timing the period of one or more cycles of the "FC's output. Frequency must then be computed since it is inversely proportional to the measured period. This measurement technique can provide higher measurement resolution in short conversion times. It is the method used in most high-performance laboratory frequency counters. It is usually necessary to offset the transfer function so OV input causes a finite frequency out. Otherwise the output period (and therefore the conversion time) approaches infinity. FREQUENCY NOISE Frequency noise (small random variation in the output frequency) limits the useful resolution of fast frequency measurement techniques. Long measurement time averages the affect of frequency noise and achieves the maximum useful resolution. The VFCllO is designed to minimize frequency noise and allows improved useful resolution with short measurement times. The typical curve "Frequency Count Repeatability vs Counter Gate Time" shows the effect of noise as the counter gate time is varied. It shows the one This frequency-to-voltage converter operates by averaging (filtering) the reference current pulses triggered on every falling edge at the frequency input. Voltage ripple with a frequency equal to the input will be present in the output voltage. The magnitude of this ripple voltage is inversely proportional to'the integrator capacitor. The ripple can be made arbitrarily small with a large capacitor, but at the sacrifice of settling time. The R-C time constant of Coo and RJN determine the settling behavior. A better compromise between output ripple and settling time can be achieved by adding a low-pass filter following the voltage output. , . . - - W l r - - _ - o VOIJT = 0 to 10V Long Pulses OK ~ FREQUENCY-TO-VOLTAGE CONVERSION 12kn liN o--j I--+~-..., C 'NT ~----~+---~-4~ "1nF 12 2,2kn 11 10 ~~~NC 1---'111~--<1-~ 2 ~ 1/10lFs max T~;:" 14 7 13 -v; 3 NC 6 7 FIGURE 4. Frequency-to-Voltage Conversion. 10-10 Burr-Brown Ie Data Book Supplement. Vol.33b Or, Call Customer Service at 1-800-548-6132 (USA Only) BURR-BROWN® VFC121 I~~I 1!w Precision Single Power Supply VOLTAGE-TO-FREQUENCY CONVERTER FEATURES APPLICATIONS • SINGLE SUPPLY OPERATION: +4.5V to +36V • ANALOG SIGNAL TRANSMISSION ~ ~ o u • INTEGRATING AID CONVERSION • fa = 1.5MHz max • LOW NONLINEARITY: 0.03% max at 100kHz, 0.1% max at 1MHz t; zw • PHASE-LOCKED LOOP VCO • GALVANICALLY ISOLATED SYSTEMS :» • HIGH INPUT IMPEDANCE CJ • VOLTAGE REFERENCE OUTPUT • THERMOMETER OUTPUT: 1mV/oK II: w II. I DESCRIPTION The VFCl2l is a monolithic voltage-to-frequency converter consisting of an integrating amplifier, voltage reference, and one-shot charge pump circuitry. High-frequency complementary NPNjPNP circuitry is used to implement the charge-balance technique, achieving speed and accuracy far superior to previous single power supply VFCs. The high-impedance input accepts signals from ground potential to Vs - 2.5V. Power supplies from 4.5V to Integrator Out Ground Sense 36V may be used. A 2.6V reference voltage output may be used to excite sensors or bias external circuitry. A thermometer output voltage proportional to absolute temperature eK) may be used as a temperature sensor or for temperature compensation of appJications circuits. Frequency output is an open-collector transistor. A disable pin forces the output to the high impedance state, allowing multiple YFCs to share a common transmission path. Comparator In VREF Disable Cos International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85106 Tel: (602) 746-1111 • Twx: 910·952-1111 • Cable: BeRCORP • Telex: 066-6491 • FAX: (602) 889-1510 • Immediate Product Inlo: (800) 548-6132 PDS-971A Burr-Brovm Ie Data Book Supplement, Vol. 33b 10-11 olI W ~ ~ For Immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL AlT. ~ +25'C. Vs = +5V. and R" = Skn unless otherwise noted. VFC121BP VFC121AP PARAMETER CONDITIONS ACCURACY Nonlinearity: I,. = 100kHz f",= lMHz Gain Error: f,. = 100kHz Gain Drift: f", = 100kHz MIN Co, 1200pF. C,,,, =2700pF Cos 6SpF. C,,,, =270pF Cos 1200pF. C,,,, = 2700pF TMIN TYP 0 V,-2.5 10 'BIAS TM1N OPEN COLLECTOR OUTPUT V.., '?ULLUP VpuLLUp :::: 5V, 'LEAKAGE Fall Time Delay to Rise Settling Time to TMA)[ = 10mA = 4700 2.59 2.6 Vs = +5V to -t36V R, = 100kn 0.8 IBIAS ·· 100 'HIGH TA = +25°C TM1N to TMAX 2.9 · I"", =2V 4.5 TEMPERATURE RANGE Specified Storage -25 -40 • Same specification as VFCI21AP. NOTE: (1) One pulse of new frequency piuS IllS. ·· · I1A ns ns · 5 7.5 V ppml'C mV mV V · I1A V V · V V I1A I1A 10 10 V,,,,, = O.SV POWER SUPPLY Voltage Current V V MO nA I1V "VI'C mV mVI'K O.S VH1GH 50 29S 1 2 (Disabled) · 400 %N V · +1 2.6 DtSABLE INPUT V"~" (Disabled) V,,,,, · 2.61 100 10 10 Short Circuit Protected 2.9 0 THERMOMETER VT V, Slope %FS %FS %FS ppml'C ppml'C · COMPARATOR INPUT Trigger Voltage Input Voltage Range 0.03 0.1 '" 10 = 0 to 10mA INTEGRATOR AMPLIFIER OUTPUT Output Voltage Range 300 SOO UNITS 40 40 0.4 1 100 100 RpULLUP To specified linearity for full scale input step REFERENCE VOLTAGE Voltage Voltage Drift Load Regulation PSRR Current limit Vs -2 100 150 300 10 MAX · 10 SO 100 0.025 PSRR Vo, Vos Drift TYP 0.05 to TM,\)( INPUT Minimum Input Voltage Maximum Input Voltage Impedance MIN 0.1 +Vs = +5V to -t36V Relative to VR.EF MAX ·· 36 10 +85 +125 ·· ·· ·· V rnA 'C 'C ORDERING INFORMATION MODEL PACKAGE LINEARITY ERROR,MAX (I, = 100kHz) VFC121AP VFC121BP Plaslie DIP Plastic DIP 0.03% 10-12 0.05% TEMPERATURE RANGE -25'C to +65'C -25'C to +65'C Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) MECHANICAL P Package - 14-Pln PlaSlic DIP ,{::::::u I I 0 Plnl/ ~:t;:::;:;::;;:::;:::;::~, -~-Ill -II_B L DIM A A, B B, C D E E, I''! a e, .A L Lt" a P D, C Seating Sl21 PIN CONFIGURATION INCHES MIlliMETERS MIN MAX MIN MAX .120 .160 3.048 4.064 .015 .065 .381 1.651 .014 .020 .355 .508 .050 .065 1.270 1.651 .008 .012 .203 .304 .745 .770 18.923 19.558 .300 .325 7t:~D .240 .260 6.096 ~ 6.604 .100 BASIC 2.540 BASIC .300 BASIC 7.620 BASIC .125 .150 3.175 3.810 .762 0 .030 0 15 0' IS' 0' 1.270 .050 .050 .085 1.270 2.159 .065 .090 1.651 2.286 NOTES: Leads In Ifue position wilhin 0.01(0.25mm) R al MMC at seating plane. (1) e, and e. apply In zone L, when unills installed . (2) Not per JEDEC. 12w Ii: ~ o () PIN CONFIGURATION Top View NC 14 Disable Not Connected fOUT 2 Disable Input logic Low for normal operation. Input logic High to disable the VFCI21. Has internal pulldown, for normal operation if not connected. 3 VT Temperature compensation voltage proportional to absolute temperature. Typically 29BmV at room temperawre (298'1<). with a change of 1mV per 'C ('K). +Vs VT -VIN GndSense +VIN IntOut Camp In NC 7 4 Gnd Sense Defines ground for the Internal voltage reference. 5 Cos One-shot capacitor is connected between here Gnd and ground to set full scale output frequency. VFlEF ABSOLUTE MAXIMUM RATINGS Power Supply Vollage (+V,) ................................................................. 40V fOOT Sink Current ................................................................................ 20mA Comparator In Voltage .......................................................... - r-- ~ 1\ 2.56 \\ 2.54 -0.1 1.8 2.58 NOTE: The VR_F outpulls shon-<:ircuit protected. ~~ 1.6 107 10· Full·Scale Frequency (Hz) 0.04 ~ 10 5 10' External One·Shot Capacitor (pF) 2 2.S2 o 2 4 6 8 10 12 14 16 18 20 Output Current (rnA) Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) TYPICAL PERFORMANCE CURVES (CONT) At T, - +25'C. V, - +5V. and R.. - 81dl unless otherwise noted. FULL SCALE GAIN DRIFT vs TEMPERATURE QUIESCENT CURRENT vs TEMPERATURE 10 r---,.---r---,--....,..---,.--r----::I 6 9.5 I--+---l---+---+--/-""F--I 5 ~91----j--t---I---+-"""-I--+----1 ~ 8 I -L' 8.5 ,....,.,.-":-:::-:,--+----,~.~_I_-+_--I--__1 8 I--+-~~ "--i--+----1---+---\ J"{FS- 1.5MHz /j IFSalM~ -Z L IFSa500rHZ -.....;.::::: s;;;:- IFS-200rHZ --..::: - :!Ii: IF. - 1001kHZ IU 7.5 - IFSal0fZ -25 o o 25 50 75 100 o -25 125 Ambient Temperature ('C) 25 50 Ambient Temperature ('C) 100 75 E o (,) THEORY OF OPERATION for the duration of the one-shot period, Tos' This switched current causes the output of the integrator to ramp negative. The VFCl2l uses a charge-balance technique to achieve high accuracy. The basic architecture is shown in Figure I. An analog integrator at the front end, consisting of a precision op amp and a feedback capacitor, C INT, provides a true integrating approach for improved noise immunity. Use of the non-invening input of the op amp for the analog input provides a high input impedance to the user. When the one-shot times out, the output of the VFC121 is reset High, the one-shot is reset, and IREF is switched to the output of the integrating op amp. (This causes the output of Integrator Output (pin 10) lCUT (pin 14) FIGURE 2. Timing Diagram. 9 13 2 Comparator VIN o--t----,,11'-1---If--I R'N 3 5 ICes FIGURE I. VFCI21 Architecture. Burr-Brown Ie Data Book Supplement, Vol. 33b " IU IL When the output of the integrator ramps to VREF' the comparator trips, driving the output of the VFCl2l Low, and triggering the one-shot. The tripping of the comparator also connects the reference current, IREF' to the integrator input 12 :::) II: The integrator's output is proponional to the charge stored on Coo plus the analog input voltage. An input voltage, VIN' forces a current through RIN of VIN/RIN' which also flows through CINT• This current through Coo causes the integrator output to ramp positive. (Refer to the timing diagram in Figure 2.) 10 t zIU 10-15 o• lI IU ~ ~ For Immediate· Assistance, Contact Your Local Salesperson Ground (Optional) C INT =2700pF 9 12 VIN = Oto+2V VpULLUP 2 13 RpuLI.. up Comparator 14 11 lOUT RBIAS =8kn = Oto 100kHz (Optional) 1-----I : RTRJM RIN =8kn : I I I ------- 5 ::r: Cos = 1200pF FIGURE 3. 2V Full Scale Input, 100kHz Full Scale Output. the integrating op amp to see a constant current, reducing errors that might occur if the load were unbalanced.) In this state, the output of the integrator resumes a positive ramp, restarting the cycle. The output frequency is regulated by the balarice of current (or charge) between the current VtNlRtN and the time-averaged reset current. The size of the integrating capacitor, CtNT, determines the slew rate of the integrator, and thus how far down the integrator ramps during the one-shot period, but has no effect on the output frequency of the VFCI21. The reference voltage used internally is generated from a bandgap reference, which is actively trimmed to achieve the low drift characteristics of the VFCI21. To maximize flexibility of designs using the VFC121, both the bandgap reference voltage and a thermometer voltage are available externally. INSTALLATION AND OPERATING INSTRUCTIONS BASIC OPERATION The VFC121 allows users a wide range of input voltages and supply voltages, and easy control of the full scale output frequency. The basic connections are shown in Figure 3, with components that generate a 100kHz output with a 2V full scale input. For other input and output ranges, the full scale input voltages and full scale output frequencies can be calculated as follows: The full scale input current of 250JlA was chosen to provide a 25% duty cycle in the output frequency. The VFC121 is designed to give optimum linearity under these condi.tions, but other current levels can be used without significantly degrading linearity. By reducing RtN , the integrating current is increased, increasing the positive ramp rate of the integra- 10-16 tor output. Since the one-shot period is unchanged, the duty cycle of the output increases. Stray capacitance at the Cos pin typically adds about 60pF to the capacitance of the external Cos. which accounts for the adjustment in the above .equation. This usually becomes negligible as the required output frequency is reduced. and Cos is increased. RB1AS is included in the circuit in Figure 3 to compensate for the effects of bias currents at the input of the integrating op amp. It is optional in most applications, but when needed. RRIAS should equal RtN • Table 1 indicates standard external component values for common input voltage ranges and output frequency ranges. COMPONENT SELECTION Selection of the external resistor and capacitor type is important. Temperature drift of the external input resistor and oneshot capacitor will affect temperature stability of the output frequency. NPO ceramic capacitors will normally produce the best results. Silver-mica types will result in slightly higher drift, but may be adequate in many applications. A low temperature coefficient film resistor should be used for RtN • The integrator capacitor, CtNT, serves as a "charge bucket," where charge accumulation is induced by the input, VtN' and repeatedly reduced during the one-shot period. The size of FULL SCALE INPUT RANGE (V) R. + R",.. (kO) 2 5 10 20 40 8 FULL SCALE OUTPUT FREQUENCY (kHz) Cos (pF) C",(pF) 1500 1000 500 250 125 25 22 68 180 470 1000 4700 150 270 470 1000 2200 10,000 NOTE: Higher oUlput frequencies can be achieved by reducing R~. TABLE 1. Standard External Component Values Burr-BrownIe Data BookSupplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) the bucket (the capacitor value) is not critical, since it primarily determines how far b.elow VREF the output of the integrator ramps during the one-shot period. At the same time, the capacitor used must not leak since capacitor leakage or dielectric absorption can affect the linearity and offset of the transfer function. High-quality ceramic capacitors can be used for values less than O.OI11F, but caution should be used with higher value ceramic capacitors. High-k ceramic capacitors may have voltage non-linearities which can degrade overall linearity. Polystyrene, polycarbonate, or mylar film capacitors are superior for higher capacitance values. During the one-shot period, the output of the integrator is ramping down. To prevent the integrating op amp from being saturated at its minimum output of 0.8V, Coo should be kept at lea~t 1.7 x Cos' OUTPUT FREQUENCY ADJUSTMENT The full scale output frequency of the VFCI21 can be adjusted using a trim-pot, R,-RIM in Figure 3, in series with R1W For optimum drift vs temPerature, a low temperature coefficient fixed resistor of approximately 90% of the calculated RIN requirement should be used in series with a trimpot approximately 20% of the size of the calculated RIN • The low-drift fixed resistor contributes most of the final RIN resistance, so that the effect of higher drift from the trim-pot is attenuated in the total RIN • PULL-UP RESISTOR The VFCI21 's frequency output is an open-collector transistor. A pull-up resistor should be connected from fOUT to the logic supply, +VL • The output transistor is On during the one-shot period, causing the output to be logic Low. The current flowing in this resistor should be limited to lOrnA to assure a 0.4 V maximum logic Low. The value chosen for the pull-up resistor may depend on the full-scale frequency and capacitance on the output line. Excessive capacitance on fOUT will cause a slow, rounded rising edge at the end of an output pulse. This effect can be minimized by using a pullup resistor which sets the output current to its maximum of 10mA. The logic power supply can be any positive voltage up to +36V. ENABLE PIN If left unconnected, the Enable input wiJI assume a logic Low level, enabling the output stage, Alternatively, the Enable input may be connected directly to ground. This pin can also be driven by standard TTL or CMOS logic. A logic High at the Enable input causes output pulses to cease. This is accomplished by interrupting the signal path through the one-shot circuitry. While disabled, all circuitry remains active and quiescent current is unchanged. Since no reset current pulses can occur while disabled, any positive input voltage will cause the integrator op amp to ramp positive and saturate at its most positive output swing of approximately VREF + 0.7V. When the Enable input receives a logic Low (less than 0.8V), a reset current cycle is initiated, (causing fOUT to go Burr-Brown Ie Data Book Supplement, Vol. 33b Low). The integrator ramps negatively and normal operation is established. The time required for the output frequency to stabilize is equal to approximately one cycle of the final output frequency plus IllS. Using the Enable input, the outputs from several VFCs can be connected to a single line. All disabled VFCs will have a high output impedance; one active VFC can then transmit on the line. Since disabled VFCs are not oscillating, they cannot interfere or "lock" with the operating VFC. Locking can occur when one VFC operates at nearly the same frequency, or a multiple, as a nearby VFC. Coupling between the two may cause them to lock to the same frequency or an exact multiple~ It then takes a small incremental input voltage change on one of the VFCs to unlock them. Locking cannot occur when unneeded VFCs are disabled. APPLICATION INFORMATION OPERATION FROM 10kHz TO 210kHz The VFCI21 is designed to provide an output frequency starting at OHz for a OV input and increasing linearly to the full scale output frequency, fFS ' at the full scale input voltage, VFS ' For applications where low level inputs, near OV, are critical, it may be inconvenient to have an output frequency approaching OHz. Figure 4 shows a circuit which transforms a OV to 2V input level into output frequencies from 10kHz to 210kHz, by placing a resistor divider network between the input source and the VREF output of the VFC 121. This produces a positive voltage at + VIN when the input to the circuit is grounded. This circuit makes use of the high input impedance at +VIN' The transfer function of this circuit is: VIN = foUT -I0kHz 100kHz Iw ~ E o() liz W ::::t CJ W II: II. • e I W ~ V To trim the circuit, first apply 2V to the analog input, and adjust RI to give a full scale output frequency of 2 10kHz. Then apply OV to the analog input, and adjust Rz until the output frequency is 10kHz. For absolute precision, it may be necessary to make several iterations trimming RI and ~. In most cases, one iteration will be enough, since the effect of ~ on . . full scale output frequency is attenuated by the divider net• ~ OV to 2V +VIN 10kHz to 210kHz 4.99kO four -V'N Integrator R2 10ka Out 121ka Comparator In -= 2.6V VREF Cos a 1000pF Cos VFC121 J NOTE: Use 1% metal film fixed resistors. Cermet" trim pots. and NPO ceramic capacitors. FIGURE 4. Offsetting the Output Frequency. 10-17 For Immediate Assistance, ContaclYour Local Salesperson work, which sees only a 0.6V total delta at full scale (2.6V at VREF niinus 2V full scale input) a~ compared with a 2.6V delta at a OV input level. USING THE VFC121 THERMOMETER VOLTAGE Because of the high input impedance of the VFC121(which results from using the non-inverting input to the integrating op amp), it is relatively simple to use a standard multiplexer in front of the VFC121. One of the possible reason to multiple" the input to the VFCl21 is to use it to track temperature changes in the operating environment of the electronics in a system, in addition to using the VFC 121 in its norinaJ mode to measure an analog signal. Figure 5 shows a way to do this. In this circuit, the normal analog input signals to be multiplexed through the VFC121 have a full scale voltage of2V, and generate a full scale output frequency of 100kHz. To measure the electronics system temperature, the user selects the multiplexer channel connected to the thermometer voltage on pin 3. A measured output frequency froni the VFCl2l, with the multiplexer on channelS, now corresponds to the temperature of the electronics as follows: Output Frequency - 13,650 Temp (0e) = - - - - - - - - 50 HI-508A VFC121 IN1 Out IN2 IN3 cm RIN = ; 2700pF 8kn IN4 +VIN -V,. lOUT Integrator Out INS Comparator In INS Cos = 1200pF Cos IN7 2.SV IN8 vT J FIGURE 5. Measuring System Temperature. 10-18 Burr-Brown Ie DatdBook Supplement. Vol.33b DSP-RELATED AND OTHER BURR-BROWN PRODUCTS Burr-Brown's world of digital signal processing solutions emphasizes ease of use and ranges from DIP-packaged analog input and analog output components all the way to complete DSP-based systems. The product line includes development and code generation software, dedicated processors, and analog I/O products. Easy-to-use and cost efficient, these products carry the user all the way from simulation to integration. Other DSP design and integration tools are currently in development. If you need to find the shortest route from DSP development to integration, call a Burr-Brown applications engineer at 1-800-548-6132. 1 Burr-Brown Ie Data Book Supplement, Vol. 33b 14-1 For Immediate Assistance, Contact Your Local Salesperson ANALOG DSP COMPONENTS AND TEST SYSTEMS Function Model Description Analog-toDigital Converters DSP101 DSP102 Digitel-toAnalog Converters DSP201 DSP202 Analog Input DSP Test Systems DSP-SYS603 DSP-SYS701 Sample Rate Resolution Package Page 200kHz Low-cost, high resolution A-to-D with zero-chip interface to DSP IC's from ADI, AT&T, Motorola and TI Two channel, low-cost, high resolution 200kHz A-to-D wHh zero-chip Interface to DSP IC's from ADI, AT&T, Motorola and n 16/18 bits 28-pln DIP S14-4 16/18 bits 28-pln DIP S14-4 Low-cost, high resolution D-to-A 500kHz with zero-chip Interface to DSP !C's from ADI, AT&T, Motorola and TI Two channel, low-cost, high resolution 200kHz D-to-A with zero-chlp interface to DSP IC's from ADI, AT&T, Motorola and TI 16/18 bits 28-pinDIP S14-15 16/18 bits 28-pin DIP S14-15 10MHz 12-bits S14-27 500kHz 16-blts Hardware and Software Hardware and Software Complete test system including A-to-D box, digital buffer, DSP processor, and software, designed to run on a PC Complete test system -including A-to-D box, digital buffer, DSP processor, and software, designed to run on a PC S14-31 DSP PROCESSOR BOARDS Model ZPB32 ZPB32-HS ZPB34-001 ZPB34-002 ZPB34-003 ZPB34-004 ZPB3201 ZPB3202 ZPB3211 ZPB3212 Processor Quantity Speed (ns) SRAM (KB) Board Form 1024 FFT Execution Time (ms) AT&T DSP32 AT&T DSP32 AT&T DSP32C AT&T DSP32C AT&T DSP32C AT&T DSP32C AT&T DSP32 AT&T DSP32 AT&T DSP32C AT&T DSP32C 1 1 1 1 1 1 1 2 1 2 250 160 80 80 80 80 160 160 80 80 64 64 64 192 320 576 64 128 64 128 PC PC PetAT PetAT PC/AT PC/AT VME6U VME6U VME6U VME6U 8.9 5.7 3.2 3.2 3.2 3.2 5.7 5.7 3.2 3.2 FIR Filter Tap Execution Time (ns) IIR Bi-Quad Riter Execution Time (J1s) 250 160 80 80 80 80 160 160 80 80 1.25 0.8 0.4 0.4 0.4 0.4 0.8 0.8 0.4 0.4 Page CALL 1-800- 5486132 for more Information {i, DSP ANALOG 110 SYSTEMS Model ZPB100 ZPBll00 ZPB2100 ZPD100l ZPD1002 ZPB1003 14-2 Form PC Board PC Board PC Board Extemal Box Extemal Box Extemal Box Max Analog Analog Number Conversion Input Output of Rate Channels Channels Bits (kHz) lor 2 lor 2 1 1 lor 2 16 16 16 16 12 16 8 150 150 150 10MHz 500kHz AntiAliasing Filter 300Hz-3kHz User Specified Smoothing Filter OHz-3kHz On-Board Sample Rate Generator Page 8kHz 75Hz-150kHz CALL 1-800- 548- User Specified 4.8kHz-150kHz 6132 for more Information. Burr-Brown Ie Dolo Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) DOS-BASED DSP SOFlWARE Model Function Page ZPA1000 Emulates (3) test instruments for signal analysis: oscilloscope, spectrum and histogram analyzers DSP Algorithm developmenVsimulation DSP Algorithm developmenVcode generation for DSP321DP32C AT&T DSP32132C Assembler AT&T DSP32-CC ·C·Compiler Momentum Data's Filter Design CALL 1-800- ZPMSQ-001 (DSPlay) ZPM32 (DSPlay XL) ZP032 ZP033 ZPOFDAS1/DAS2 Burr-Brown Ie Data Book Supplement, Vol. 33b 548- 6132 for more Information 14-3 For Immediate Assistance, Contact Your Local Salesperson BURR-BROWN@ DSP101 DSP102 11E5I1E5I1 ADVANCE INFORMATION SUBJECT TO CHANGE DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS FEATURES DESCRIPTION • ZERO·CHIP INTERFACE TO STANDARD DSPICs:AD,AT&T,MOTOROLA,~ • SINGLE CHANNEL: DSP101 • DUAL CHANNEL: DSP102 Two Serial Outputs or Cascade 32·BitWord • SAMPUNG RATE TO • DYNAMIC SPIECIFIC.ATION! Signall(Noise Spurious-Free Dvrlamlc THD=-92dB are packaged in stanDIP packages. Each is grades to match applica- ---Chmn8lBD~---i I Channel B User Tag In : 8·BR Samlpling ADC : I I Channel B on DSP102 Only :I _______________________________________________________ 1n1an1l1ona1 AlipCHllndUllrla1 Perk • IIIlIlng AddrHa: PO Il0l11400 • Tuc8on, AZ 85734 • S - AddrHI: &730 S. TUcIOll Blvd. • Tuc8on, AZ 851D6 Tel: (6G2) 746-1111 • 1'111:9111-952·1111 • ClbIe:BBRCORP • Telex:06H491 • FAX:(&02)88f.1510 • InrnIdIaleProductlnfo:(IIO}54a.613Z PDS·I068 14-4 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) SPECIFICATIONS ELECTRICAL T._ DOC to 7DoC, sampling frequency, fs Q 160kHz, V.+ a V. =+5V, V.- _ -5V, 12.288MHz crystaf oscillator, unless olherwlse specified. DSP101KP DSP1D2KP DSP1D1JP DSP102JP PARAMETER CONDmONS ANALOG INPUT Vollage Range Impedance Capacitance THROUGHPUT SPEED Complete Cycle Throughput Rate V kn pF ±2.75V 1 20 Acquisition + Conversion 5 lIS kHz 200 AC ACCURACY "' Signal to (Noise + Distortion) dB"' dB dB dB dB dB Total Hannonle Distortion Spurious·Free Dynamic Range Signal to Noise Ratio (SNR) DC ACCURACY Gain Error t31 Gain Error Mismatch ", Integral Unearity Error Differential Linearity Error No Missing Codes Bipolar Zero Error '" Bipolar Zero Mismatch '" Power Supply Sensitivity % % % % Bits mV mV dB dB SAMPUNG DYNAMtCS Aperture Delay Aperture Jitter Transient Response Overvoltage ns ps,nns lIS lIS Logic V V V. V" OSCI Clock Data Transfer Frequency Duty Cycle Conversion Clock Frequency Duty Cycle DIGITAL OUTPUTS Format Coding logie Levels (Except V... VOlt OSC2 Conversion Drive POWER Rated Voltage V.+ V.V. Power Consumption Supply Currenl 1.+ 33 MHz % 5 MHz % 40 Serial; MSB first; 16118-1111 and Cascaded 32-1111 Mode Binary Two's Complement +~4 o +2.4 Can be used ±:!rnA +4.75 -5.25 +4.75 o -55 I I drive V V oscillator. rnA +5 -5 +5 250 +5.25 -4.75 +5.25 400 30 -13 10 1.I. TEMPERATURE RANGE Specification Storage 12 60 V V V mW rnA mA mA +70 +125 'C 'C NOTES: (1) All dynamic specifications are based on 2048·poinl FFTs, using coherenl sampling. (2) All specifications In dB are refenred to a full-scale Input ±2.75Vp-p. (3) Adjustable to zero with extemal potentiometer. Burr-Brown Ie Data Book Supplement, Vol. 33b 14-5 For Immediate Assistance, Contact Your Local Salesperson MECHANICAL P Package - 28-Pln Plastic DIP 11~'~28------- D - - - - - - - 1 5...·~1 r E, ,1'1 MIWMETERS MIN MAX 2.54 5.08 U .000 .030 0.00 0.78 a 0' .040 15° .080 0' 1.02 15° 2.03 L ,," o INCHES MIN MAX .100 .200 DIM ~M o S, E, '" 8' 8. .485 ~ .100 I .600 , I 12.32 13.97 2.54 >'\SIC 15.2411AS1C (1) NoIJEDEC Standard. NOTE: Leads In true position wilhln 0.01" (0.25mm) R at MMC at seaHng plane. Pin numbers shown lor reference only. Numbers may not be marked on paclcage. Power. Clock In. '"'D:~~~=~C~~Iock;:"IOut. Can drive multiple rl to synchronize conversion. Select Synch Fonnalln. If HIGH, SYNC will be active High. If LOW, SYNC will be active low. See timing dlagram (FIgure 1). Oscillator Point 1 IniExtemai Clock In. If using extemal clock, drive wIIh 74HC logic levels. Oscinator Point 2 Out Provides drive lor crystal oscillator. Make no electrlcal connection If using external clock, SYNC 16 17 18 14-6 XCLK TAG 19 20 SOUT 21 CONV 22 23 24 25 26 27 26 DGND CAP REF AGND Data Synchronization Out. Acllve High when SSF Is HIGH; active low when SSF Is LOW. Data Transfer Clock In. No Connection. User Tag In. Data clocked Into Ihls pin Is appended to Ihe conversion results on SOUTo See timing dlagram (FIgure 1). No Connection. Serial Data Out MSB first Binary Two's Complement Ionnat Convert Command In. FaiUng edge puts converter Into hold state, Inltiates conversicn, and transmits previous conversion results to DSP IC wllh appropriate SYNC pulse. Digital Ground. No Connection. No Connection. No Connection. Bypass C8pacItor. Reference Bypass. Ground. Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) DSP102 PIN CONFIGURATION VPOTA DSP102 PIN ASSIGNMENTS 28 AGND MSBA VOSA VA + DSP102 DGND VPOTA VINA MSBA VOSA v.V.+ DGND DGND Vo CLKIN CLKOUT 12 SSF 13 esCl Oscillator Point 1 In I External Clock In. II using external clock. drive with 74HC logic levels. OSC2 Oscillator Point 2 Out. Provides drive lor crystal oscillator. Make no eledrlcal connactlon II using external clock. DGND \b CLKIN CLKOUT Channel A Trim Relerence Out. Channel A Analog In. Channel A MSB Adjust In. Channel A ves Adjust In. -SV Analog Power. +5V Analog Power. Digital Ground. Digital Ground. +5V Digital Power. Conversion Clock In. Conversion Clock Out. Can drive multiple DSP102s to synchronize conversion. Select Synch Fonnat In. If HIGH. SYNC will be active High. II LOW. SYNC will be active Low. See timing diagram (Figure 1). 1 2 3 4 S S 7 8 9 10 11 Data SSF OSCI OSC2 14 Into this pin of SOUTA. In. Falling edge puts converter state. Initiates conversion. and transmits conversion results to DSP IC wHh appropriate SYNC pulse. Select cascade Mode In. II HIGH. DSP102 transmits a 32·bit word on SCUTA. with the first bits being data on Channel A. II LOW. DSP102 transmits data lor both channels simultaneously. Channel B ves Adjust In. Channel B MSB Adjust In. Channel B Analog In. Channel B Trim Reference Out. Reference Bypass. Analog Ground. Burr-Brown Ie Data Book Supplement, Vol. 33b .... ~ 00 :!! 0 c:: ~ ':.'~ !"'" "~I..-- 0 til "'tI " .----------~::--- 0 -I 8. Sl"'tI -·.!nrnrn'nr ... SYNC ~ SYNC (SSF-I.CM) 5i 5i ... SOUTMI ~: TAOMI 0 12 ~{JJ.ULJ_LLL .; .CD ~ -l CD :.. C!Q :=iii;;- xeLK CONY ~ ~ ~1'=iT!lJtll/ll/ll/l/IJ/IJ/lr ~ &' b:I s:: SCUTA '~.nl"'"' ~ ;;- I~ ~ =i 6" ~ ...c:::r- ~ ~ () g, ~ [ ~ .~ l ~ ~ :--- ~ I:l'- c::a ~ t" t" .. t, r. t, r. r. 1,. In 1" ~. 1" Convert Command LOW Time Convert Period (CASC • LOW on DSP102) Convert Period (CASC • HIGH on DSP102) SYNC Active Delay alter Convert Failing Edge SYNC LOW to HIGH Delay from XCLK Rising; SYNC HIGH 10 LOW Delay from XCLK Rising; SOUTAIB Data Valid Delay from XCLK Rising; SOUTAIB Data Valid After from XCLK Rising; TAGAIB Data Setup before XCLK Rising TAGAIB Data Hold after XCLK Rising OSCI Period."' Duty Cyde 50% ± 10% CLKOUT Period. Duty Cycle 33% ± 10% CLKIN Period. Duty Cycle 33% ± 20% c.. • 50pF c.. • 50pF c.. • 50pF c.. = SOpF - -=;} 15 15 15 10 20 0 667 67 31" 200 ~ iii' 2~ ~-t40 I 2000 CD ns ns ns ns ns ns NOTES: (I)When using a DSP IC In a 16-bft mode. these data bits will be Ignored by the processor. (2) t".., must be at leasl 72 times faster than !he conversion rate. (~, I. ~ 72 1,,) c::a ~ Or, Call Customer Service at 1·800·548·6132 (USA Dn/y) TIL Bit Clock Digital Signal Processor IC DSP101 CLKR ±2.75V Analog Input 2 VIN DATA iN DSP201") XCLK DATA OUT SYNC VOUT ±3V Analog Output SYNC E ::» a iA. Z ~ ...• II: II: ...::»II: ...0Z II: IU TMS320C30 a Z CLKR-o C FSR-o A. B DR·O NOTE: Serial pori 0 programmed lor 32-bit data. FIGURE 4. Using DSPI02 with TMS32OC30 in Cascade Mode. Burr-Brown Ie Data Book Supplement. Vol.33b 14-9 For Immediate Assistance, Contact Your Local Salesperson DSP202(3) DSP102 r'---t--i CLKR-Q CLKR-l 1=----1 OR-O :t2.75V Analog Input Channel A :t2.75V Analog Input Channel S 2 VINA r----iDR·l VINB VOUTA tflV Analog 0uIput Channel A tflV Analog 0uIput ChannelS (2) Sample raIB on DSP102 ai1d DSP202 may diller. (3) DSP32C may be used In this mode. lor lull descrlplion of this DAC. and Output System with TMS32OC30 in Cascade Mode. 14-10 Burr~Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) I DSP10l XCLK SYNC :t:2.75V Analog Inpul -t VIN SOUT TILBi! Clock 16 i I 15 20 TMS320C25 XCLK FSX TXD SSF ~+5V CONY 21 Conversion Rate Generator NOTES: (1) TM532OC25 FSA extemal. 16-bll data. FIGURE 7. Using DSPIOI with TMS320C25. FIGURE 8. UsillgJ;ISP11Q DSP32C ~~----~-------; ~K ~~------------~ I~ ~~------------~ DATA IN NOTE: (1) DSP32C programmed for MSB bit first 16-b1t data. FIGURE 9. Using DSPIOI with DSP32C. Burr-Brown Ie Data Book Supplement, Vol.33b 14-11 For Immediate Assistance, Contact Your Local Salesperson DSPl02 -+______-;ICK ~16~____ ~~-------------;I~ ±2.75V Analog Input Channel A ±2.75V Analog Input Channel B VINA J-=~-------------; DATA IN VINB FIGURE 10. Using DSP202 with DSP32C in ADSP-2101 !=------1~----__f SCLK-o '--------I SCLK-l ~--t===1 RFS-l I.. RFS-l F------------__f OR-O 1-'-'------------1 DR-I FIGURE 12. Using DSPI02 with ADSP-210I. 14-12 Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) I TIL Bit Clock DSP101 ADsp·2105 XCLK SOUT t2.75V Analog Input -2.. I 16 SCLK 20 DR 15 RFS VIN SYNC SSF fE.-o+5V CONV 21 Conversion Rate Generator FIGURE 13. Using DSPIOI wilh ADSp·2I05. ~ + FIGURE Burr-Brown Ie Data Book Supplement, Vol. 33b = Analog Ground = Digital Ground For Immediate Assistance, Contact Your Local Salesperson DSP102 Analog '"pUIA FIGURE 15. DSP102 Input Buffering. 14-14 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) DSP102 FIGURE 17. DSP102 CO~lvenlionClOi~Rq~ircuit. Burr-Brown Ie Data Book Supplement. Vol.33b For Immediate Assistancet . Contact Your Local Salesperson BURR-BROWN@ DSP201 DSP202 1-=--=-1 DSP-Compatible Single/Dual DIGITAL-TO-ANALOG CONVERTERS FEATURES DESCRIPTION • ZERO·CHIP INTERFACE TO STANDARD DSP ICs: AD, AT&T,MOTOROLA, TI The DSP201 and DSP202 are high perfonnance digital-to-analog converters designed for simplicity of use with modem digital signal processing lCs. Both are complete with all interface logic for use directly with DSP lCs. and provide analog output .voltages updated at up to 500kHz. • SINGLE CHANNEL: DSP201 • DUAL CHANNEL: DSP202 Two Serial Inputs or Cascade from Single 32·BltWord • SAMPLING RATE TO 500kHz • DYNAMIC SPECIFICATIONS: Slgnall(Nolse + Distortion) = 9OdB; THD=-92dB • USER SELECTABLE 16-BIT OR 18-BIT DATA WORDS Convert Command The DSP201 offers a single complete voltage output channel. accepting either 16 bits or 18 bits of input data. and can be driven by 16-bit. 24-bit, or 32-bit serial ports. The DSP202 offers two complete voltage output channels, with either two separate input ports, or a mode to drive both output channels from a single 32-bit word. Both the DSP20 I and DSP202 are packaged in standard, low-cost 28-pin plastic DIP packages. Each is offered in two perfonnance grades to match application requirements. Latch Enable Reset SelecI Sync Fonnal 18-BIIOAC ConlrOl logic Analog Vollage OulpUl Channel A Selecl Word LengIh (16118) Channel A Oala In r--Sync BhCIock 1 1 1 1 - ______ 11 ------------------- I 18-BftOAC Channel B Oala In Channel B on DSP2D2 Only C8scade I ~ -----------, Analog Vollage : OulpUl : ChannelB I I I I I I I _________________________________________________________________ 1 ___IanaIAIrparIIndullrIllIParll • uamngAddrHs:POBoxll400 • Tuc8on,AZ85734 • SII88IAddress:6730S. Tuc8onBIvd. • TUCIDII,AZ 85706 Tel: (&02) 746-1111 • 1\n:tl0f52.1111 • CabIe:BBRCORP • Telex:06H491 • FAX: (602) 888'1510 • mnedIaleProducllnfo:(8DO)548-6132 PDS·I067 14-16 Burr~Brown Ie Data Book Supplement, Vol. 33b Dr, Call Customer Service at 1-800-548-6132 (USA Dnly) SPECIFICATIONS ELECTRICAL T,_ O'C 10 70'C. Outpul Updale Frequency. I•• _ 400kHz. V,+ a V.+ • ..sV. V,- a V.- -..JfJV. unless olherwlse speclilad. DSP201JP DSP202JP PARAMETER CONDmONS MIN TYP RESOLUTION ntROUGHPlIT SPEED '" Update Rale DSP202 In Cascade Mode AC ACCURACy .... Signal to (Noise + DlslOI1lon) Ratio Total Harmonic Distortion Channel Separation on DSP202 DC ACCURACY Integral Nonlinearity Error Differential Nonlinearity Error Bipolar Zero Error ~I Bipolar Zero Error Drill Bipolar Zero Mismatch ") Gain Error") GaIn Error Drill GaIn Error Mismatch ") Digital Faadlhrough Power Supply Sensitivity DIGITAL INPUTS Formal Coding Logic Levels VL V.. Data Transfer Clock Frequency Duly Cycle D~;AL OllTPUlS TEMPERATURE RANGE SpecificalJon storage MIN 108 f\.3750 :h'l 0.1 f\.3750 ±8 CASC a LOW on DSP202 CASCaHIGH 500 300 'CUTa 1kHz lCUT a 1kHz (~OdB) 10kHz lCUT= 1kHz 1kHz 10 100kHz 82 'OUT. 'OUT. 80 86 30 86 -90 105 iO.OO6 iO.OO6 ±10 20 5 1 100 1 -105 DSP202 Channels DSP102 Channels ENABLE. HIGH ..JfJ.l -''--~ :==t=r.=tzmllll7 ':.':. I " :: SYNC(~ ~ SYNC (SSF. LOW) !3 N ::l e. CD Q. ENiiBLE"' r ::I qq SINAIB . q--------------------------------- ,:,;y. Bh16 X XBit 16'· (LSB) Bit 17'· i;;' == i;' :::a c, ...... ~~, == =i ~ ?5 o I:l is' b:l ~ Bft 16(lSB) (eASC. HIGH) I. INTERVAL I, t, til Ie I Ie Ie 1" 1" {j ~ :- ~ I::r XCLK period; DUly C~1e 50% ±10% Convert Command LOW Time Convert Period (CASC • LOW on DSP202) Convert Period (CASC • HIGH on DSP202 SYNC Active Delay after Convert Failing Edge) SYNC LOW to HIGH Daisy from XCLK Rising; SYNC HIGH to LOW Delay from XCLK Rising; ENABLE Setup befons Convert Failing Edge'" ENABLE Hold after Convert Falilng Edge") SINNS Data Sslup befons XCLK Rising SINNS Data Hold after XCLK Rising t, t, t, - -- Bit 1 (MSB) Chamol A Dala MIN c.. •SOpF c.. • SOpF 83 50 24 40 I, -040 -I UNITS ns ns 21, 15 15 50 50 20 0 ~ ~ ns ns ns ns ns ns ns ---------- -- NOTES: (1) Normally ded LOW so thai previously transmitted data Is used to update DAC oulpUl on failing edge of CONY. HIGH prevents the DAC from being updated, (2) Optional data bits. ClOCked Into DAC register only HSWLIsLOW. mm , ~ :::a i;' ~ ;;:: Bft 16(lSB) MAX . .. ..'~~ .. . ." Channel B Data DESCRIPTION ~ '.':~ ·. .·,.... ·, '.: CONV SINAIB 'C ,:' =HIGH) XCLK t!t, iii' CD ::. -------------- ------------------------------------- (CASe. LOW on DSP202) DSP202 Cascade Mocle (CASC b:l ....~ '1 5; r0- c::. ~ ~ iii -=f;J CD = Or, Call Customer Service at 1·800·548·6132 (USA Only) rl DlgllalSlgnal Processor IC DSP10l' XCLK ~ VIN SOUT ~ TTLBII Clock 16 CLKR 20 DSP201 12 XCLK 13 DATA OUT DATA IN XCLK SIN VOUT ~ :t3V Analog 0u1pU1 :t2.75V Analog Inpul SYNC 15 SYNC 11 SYNC SSF rB-'SSF CONY "SWL~ I Conversion Rate I 21 I DSP PROCESSOR 15 I Generator SERIAL I/O WORD SYNC FORMAT Active Low Active High ActIve High' Active High Active High DSP32C, DSP16 DSP56001 DSP56001 TMS32OC251C30 ADSP210112105 SYNC ·SSF-!... SSF 16 24 16 16 16 Bits Blls Blls Bits Bits SWL CONY 'SSF "SWL LOW HIGH HIGH HIGH HIGH HIGH LOW HIGH HIGH HIGH 'See Burr-Brown DSP101l102 product data shee' for full description 0/ Ihls ADC. FIGURE 2. Analog Input and Analog Output System. I DSPI1 TTLBII Clock 1" TXCLK SYNC DATA TXCLK SYNC SYNC 13 SINA VOUTA 14 SINB VOUTB 15 CONY 9 Sync Format-Input o--!... rI--- DATA Data Lenglh XCLK 11 16 -= DSPII2 DSP202 o--!!!17 -=8 - +5Vo-!:.. r!!r!-- :t3V Analog 0uIput from DSP #2 CASC SSF SWL ENABLE RESET DIGITAL SIGNAL PROCESSOR Conversion Rate Generalor :t3V Analog Oulpul from DSP #1 SYNCFORMAT DATA LENGTH AT&T DSP32C AT&T DSP16 DSP56001 logic 0 logic 1 logic 1 TMS32OC25 logic 1 16-811, logic 1 16-BII, logic 1 16-BlI, logic 1 24-BII, logic 0 16-Bft, logic 1 FIGURE 3. DSP202 with Dual DSP Ies. Burr-Brown Ie Data Book Supplement, Vol, 33b For Immediate l Assistance, Contact Your Local Salesperson TTLBh Clock J- TMS32OC30 DSP202 12 cu " MSB first data FIGURE 13. Using DSP201 with ADSP-2105. DSP201 AGNO -5V +5V vA+ VPOT -5V MSB 3.3kn ves +5V Offset Adjust l00kn -5Vo-./IIV'-O +5V AGNO -5V DGNO DGNO 14 15 FIGURE 14. DSP201 Power Supply Connections and Adjust Circuits. 14-26 Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Customer Service at 1·800·548·6132 (USA Only) DSP202 -flY ChannelB l00kll AGND -fN +5V 3.3kll VA+ +5V +5V VOSA AGNDA VD- -flY DGND DGND 15 14 FIGURE 15. DSP202 Power Supply Connections and Optional Offset Voltage Adjustment. Opllonal MSB Adjust Circuit Channel B 1001<11 DSP202 -flVo-~r---------~ 28 l00kll Optional MSB Adjust Circuli Channel A 100kll I -......---------vw-o -flY l00kll MSBA 14 FIGURE 16. DSP202 Optional MSB Adjust Circuit. Burr-Brown Ie Data Book Supplement, Vol. 33b 15 .. I 14-27 For Immediate Assistance, Contact Your Local Salesperson liElEII RR- B ROWN8 DSP-SYS603 ,PC-Based Design/Testl Evaluation System for the ADC603 BENEFITS/FEATURES • COMPLETE SYSTEM "READY-TO-USE" WITH YOUR PC • HIGH PERFORMANCE ADC603 ANALOG INPUTS (12-BIT ACCURACY 10MHz SAMPLING RATE) • 64K WORD 10MHz DIGITAL BUFFER PC BOARD • HIGH PERFORMANCE FLOATING POINT DSP PROCESSOR (AT&T WE«J DSP32C) III RUNS UNDER MS/DOS ON IBM«J AT OR COMPATIBLE • DSP DEVELOPMENT SOFTWARE INCLUDED (DSPLAY XLTM) • COMPLETE ADC TEST/EVALUATION SOFTWARE INCLUDED the DSP-SYS603 can be used to analyze the performance of the ADC603 in specific applications. As a test instrument, it can be used to establish and measure specification profiles for certifying device system performance. As a development system, the DSP-SYS603 can receive direct analog signals and use them as inputs for the DSP processor. APPLICATIONS • DEVICE EVALUATION/CHARACTERIZATION • SYSTEM DESIGN/DEVELOPMENT • HIGH PERFORMANCE INSTRUMENTATION • REAL-TIME SIGNAL PROCESSING ALGORITHM DEVELOPMENT • MEDICAL IMAGING Analog signals are converted at up to 10MHz with true 12bit accuracy. The digital input is transferred to a DSP processor where, using DSPlay XL development software, signal processing algorithms may be easily designed and implemented. Furthermore, using the Dynamic Signal Analysis software that is provided, the system may be used as a high performance digitizing scope, spectrum analyzer or histogram analyzer. Thus, the system can be used as a test instrument for assisting in the design of new products or the troubleshooting of circuitry. It may also be used as a receiving inspection station for testing hard-to-evaluate high performance analog-to-digital converters at time of receipt for manufacturing. • SONAR • HIGH PERFORMANCE FFT SPECTRUM ANALYSIS • HIGH SPEED DATA ACQUISITION • ULTRASOUND SIGNAL PROCESSING • I&Q PROCESSING • ADC TESTING • FATIGUE ANALYSIS • NON-DESTRUCTIVE TESTING The DSP-SYS603 has two configuration options. Each system is made up of a combination of the following components best suited for specific applications: • SCIENTIFIC RESEARCH DESCRIPTION The DSP-SYS603 Design System for the high performance ADC603 provides the user a ready-to-use solution for evaluation, test, and development purposes. As an evaluation tool, • External Box with single or dual-channel ADC603 Converter(s) • 64K Word Digital Input Buffer Board(s) • AT&T DSP32C Processor Board with 576K SRAM • DSPlay XL Real Time DSP Development Software • Dynamic Signal Analysis Thst Software PDS-I011 14-28 Burr-Brown Ie Data Book Supplement, Vol.33b Or, Call Customer Service at 1-800-548-6132 (USA Only) These system components are described below. More detailed descriptions can be provided upon request. ANALOG SIGNAL INPUT BOX (ZPD1OO2) The single or dual-channel external input box contains one or two ADC603s and drivers to provide high performance analog input into the system. The ADC603 is a 12-bit IOMHz sampling analog-to-digital converter. COMPUTER PLATFORM The system is designed to operate in an IBM PC/AT environment with an EGA or VGA monitor and MicrosoftO!> Mouse. Although the standard system does not include the computer platform, a factory supplied computer (IBM ATcompatible) is available as an option. If the computer is purchased, all of the components are tested as a complete system, and shipped from the factory as a "ready-to-use" instrument. (Contact Customer Support at 1-800-548-6132 for price and delivery information for the complete system including the computer platform.) DSP PROCESSOR BOARD (ZPB34-004) The DSP processor board provided with the system (ZPB34004) uses an AT&T DSP32C processor. This processor is capable of 25MFLOPS and is able to perform a 32-Bit multiply/accumulate instruction in 8Ons. The board has 576KB of local SRAM and buffered high-speed (I0MBits per second) serial I/O ports. DIGITAL INPUT BUFFER (ZPB6064) Due to the high speed sample rate of the ADC603, the system includes a digital input buffer board. This high speed card will capture, and subsequentially transfer, up to 65,536 words of data. Buffer size is set through the PC I/O port for 32 to 65,536 words with a word being 16 bits of digital information on either the ECL or TTL input signal at speeds from near DC to IOMHz. Input data capture can be controlled by the Trigger function which can be either an external (ECl/ITL) signal or a PC I/O control byte. Post trigger data capture can be set for I to maximum buffer size minus one. A second digital input buffer can be installed and slaved to the first card. The two boards can be triggered and clocked independently or simultaneously. When both buffers are full, the data can be serially transferred as 32-bit words (two concatenated 16-bit words). This feature can double the effective capture speed or allow two independent 16-bit input paths. DYNAMIC SIGNAL ANALYSIS SOFTWARE (ZPA100) At the heart of the system is the Dynamic Signal Analysis software which transforms the PC into a complete test and evaluation instrument, capable of analyzing data in time and frequency domain as well as producing linearity measurements. The software allows the PC to operate as any of three Burr-Brown Ie Data Book Supplement, Vol.33b test instruments: digitizing scope, spectrum analyzer and histogram analyzer. As a digitizing scope, the user may view, measure and analyze incoming data in the time domain. Operating as a spectrum analyzer, FFrs are used for viewing, measuring or analyzing incoming data in the frequency domain. Direct readout of harmonic content, THO, SNR, THD + SNR, DC offset, and spurious-free dynamic range is possible through spectrum analysis. Functioning as an histogram analyzer, the user may display histograms, differential non-linearity (DNL), and integral non-linearity (INL). For convenience, the software is completely mouse-driven allowing the user to zoom, pan, move markers, use display lines, or change parameters with simple mouse movements. Setup save and load features are also included. DSP DEVELOPMENT SOFTWARE (ZPM32) A second integral piece of software provided for real-time development is DSPlay XL. Supplied with over 100 block functions, DSPlay XL uses F10WgramsTM (block diagrams of an application) to develop algorithms which are executed on the system's DSP processor. Once designed and verified, the executable code can be saved and ported to any DSP system using the AT&T DSP32 or DSP32C processors. HIGH PERFORMANCE WORKSTATION CONRGURATIONS As an integrated system, the state-of-the-art development and evaluation tools described above form a user-friendly, yet extremely powerful, workstation environment for realtime DSP applications. Since the applications for DSP are varied, two configurations for the high performance development system are offered. Single Channel Analog Input System (DSP-SYS603-001) Description The DSP-SYS603-OO1 is the basic system for acquiring and working with single input analog signals at the 12-bitlOMHz sampling rate of the ADC603. For applications where it is necessary to evaluate the incorporation of an ADC603 into a current design or design under development, the -001 system allows the user to analyze the effects of the high performance of the ADC603. Furthermore, this analysis can be accomplished with little more effort than making the appropriate connections and establishing the proper system setup. In addition to design support, the DSP-SYS603 may be used as the test software to characterize the performance of the _ user's system. A third application for the workstation is to take advantage of the development software in order to design DSP circuits that will enhance the performance of the user's system. DSP-SYS603 software will allow the user to not only develop the DSP algorithms, but will port the executable code to any DSP32C processors for continued use within the user's system. 14-29 ~ &"J 0 • >"I R For Immediate Assistance, Contact Your Local Salesperson 1 1 1- - - - - - _I High-5peed Serial 1 1 1 1 L..-_--' 1 1 1 1 FIGURE I. Single Channel Analog Input System. Dual Channel Analog Input System (DSP·SYS603-002) Description The -002 system configuration is designed for applications where simultaneous sampling is required. Included in this system is an analog input box with dual ADC603s along with two digital input buffer boards. As a dual input system configuration, independent high resolution samples can be taken simultaneously, then passed to the respective buffer board, where the two inputs are concatenated to form one 32-bit word for transfer to the DSP board for analysis and processing. DSP Processor Board Memory: ........................... 64KB 0 Wait State 512KB I Wait State Clock Rate: .......................49.152MHz Addressing: ....................... 1/0 Port Address OXO-OX3FF I/O Mapped 16 Ports Interrupts: ......................... Selectable IRQ3-7,9-12,14,15 Serial I/O: ......................... Buffered Differential Line Drivers and Receivers Terminated in 1000 Serial 1/0- Internal: .......... 6.IMBitsts DSP Development Software Over 100 DSP and related block functions in the following categories: Non_linear Arithmetic O_scope Data Spectrum Filter Trigonometric Generator Window Input_Output Measure file suBgram Execution times for several common functions: 1024 Point Complex FFT .. 3.8ms 128 Tap FIR Filter ............. 8Ons X 128 Second Order I1R Section .. 8Ons X5 Dynamic Signal Analysis Software Software performs instrumentation functions for: Digitizing Scope Spectrum Analyzer Histogram Analyzer Configuration Hardware Requirements; IBM AT Compatible 640K memory Math Co-processor Mass Storage - Hard disk and one floppy drive Monitor - EGA or VGA Printer (optional) - IBM graphics printer, HP Laser jet printer or compatibles Software Requirements PC/MS-DOS Versions 3.0 or higher FIGURE 2. Dual Channel Analog Input System. Digital Input Buffer Sample Rate: .................... IOMHz max (externally supplied) Data Format Out: ............. Buffered Differential line drivers Base I/O Address: ............ 1/0 Port Address OXO-OX3FF I/O Mapped 4 Ports 14-30 SUPPLIED ACCESSORIES Power Supply for the Analog Input Box Power Connectors Connection Cables DSP Development Software Manual Dynamic Signal Analysis Software Manual DSP-SYS701 User's Manual Burr-Brown Ie Data Book Supplement, Vol. 33b Or, Call Cuslomer Service al 1-800-548-6132 (USA Only) SPECIFICATIONS PARAMETERS INPUlS Analog Input Range tnput Impedance Digital logic Family Convert Command PulsoWodth Trigger Pulse Width TRANSFER CHARACTERlSnCS Accuracy Gain Error Conversion Characteristics Samp/eRato Dynamic Characl8~stlcs Slgnal-to·NoIse Rallo (SNR) CONDITIONS MIN TYP -1.25 MAX +1.25 50 UNRS V n TTL PosltiveEdge 10 t·20 ns Posltive Edge ns 20 :to.l '-200Hz DC '_100kHz ',_9.99MHz 68 70.' -1.95 -0.98 20 45 :tl %FSR '0 MHz dB OUTPUTS logic Family - DiHarentlal ECl logic coding - Two·s Complement logic Levels- LogIc"LO" LogIc"Hr Data Valid Pulse Widlh OPTIONAL CONFIGURED HARDWARE SYSTEM, INCLUDES HIGH PERFORMANCE 386PC Burr-Brown will provide, as an option, an entire test/evaluation system including the required configuration hardware and software. With the purchase of this option, the system is configured and tested prior to shipment. Thus, the customer will receive a complete tum-key test/evaluation system for the ADC603. The configuration hardware will be a high performance, 386 computer (without printer). For details of the exact computer specifications to be used at the time of shipment, contact your sales representative. -'.63 -0.81 60 V V ns ORDERING INFORMATION To order, please specify: DSP-SYS603-oo1 .......... Single Channel Analog Input System DSP-SYS603-oo2 .......... Dual Channel Analog Input System with Digital Input Buffers DSP-SYS603-XXXA ....• Analog Input System including Configured Hardware System FOR MORE INFORMATION For more information contact Applications Engineering at 1-800-548-6132. AowOram'IM Burr·Brown Corp. OSPIay XL'IV Burr·Brown Cotp. Microsoft- Microsoft Corp. WE" DSP32C AT&T Corp. IBM' PC IBM Corp. Burr-Brown Ie Data Book Supplement. Vol. 33b For Immediate Assistance, Contact Your Local Salesperson DSP-SYS701 PC-Based DesignlTestl Evaluation System for the ADC701 BENEFITS/FEATURES • COMPLETE SYSTEM "READY-TO-USE" WITH YOUR PC • HIGH PERFORMANCE ADC701 ANALOG INPUTS (16-BIT ACCURACY 500kHz SAMPLING RATE) • 64K WORD 10MHz DIGITAL BUFFER BOARD FOR THE PC • HIGH PERFORMANCE FLOATING POINT DSP PROCESSOR (AT&T WE«> DSP32C) FOR THE PC • RUNS UNDER MS/DOS ON IBM«> AT OR COMPATIBLE • DSP DEVELOPMENT SOFTWARE INCLUDED (DSPLAY XLTM) ation, test, and development purposes. As an evaluation tool, the DSP-SYS701 can be used to analyze the performance of the ADC70 I in specific applications. As a test instrument, it can be used to establish and measure specification profiles for certifying device system performance. As a development system, the DSP-SYS701 can receive direct analog signals and use them as inputs for the DSP processor. • COMPLETE ADC TEST/EVALUATION SOFTWARE INCLUDED APPLICATIONS • ADC701 EVALUATION/CHARACTERIZATION • SYSTEM DESIGN/DEVELOPMENT • HIGH PERFORMANCE INSTRUMENTATION • REAL-TIME SIGNAL PROCESSING ALGORITHM DEVELOPMENT • MEDICAL IMAGING Analog signals are converted at up to 500kHz with true 16bit accuracy. The digital input is transferred in real time to a DSP processor where, using DSPlay XL development software, signal processing algorithms may be easily designed and implemented. Furthermore, using the Dynamic Signal Analysis software that is provided, the system may be used as a high performance digitizing scope, spectrum analyzer or histogram analyzer. Thus, the system can be used as a test instrument for assisting in the design of new products or the troubleshooting of circuitry. It may also be used as a receiving inspection station for testing hard-to-evaluate high performance analog-to-digital converters at time of receipt for manufacturing. • SONAR • HIGH PERFORMANCE FFT SPECTRUM ANALYSIS • HIGH SPEED DATA ACQUISITION • ULTRASOUND SIGNAL PROCESSING • I&Q PROCESSING • ADC TESTING • FATIGUE ANALYSIS • NON-DESTRUCTIVE TESTING The DSP-SYS701 has three configuration options. Each system is made up of a combination of the following components best suited for specific applications: • SCIENTIFIC RESEARCH DESCRIPTION The DSP-SYS70l Design System for the high performance ADC701 provides the user a ready-to-use solution for evalu- • • • • • External Box(es) with ADC701 Converter 64K Word Digital Input Buffer Board(s) AT&T DSP32C Processor Board with 576K SRAM DSPlay XL Real Time DSP Development Software Dynamic Signal Analysis Test Software PDS·10I2 14-32 Burr-Brmi'n Ie Data Book Supplement. Vol. 33b Or, Call Customer Service at 1-800-548-6132 (USA Only) These system components are described below. More detailed descriptions can be provided upon request. test instruments: digitizing scope, spectrum analyzer and histogram analyzer. ANALOG SIGNAL INPUT BOX (ZPD1003) As a digitizing scope, the user may view, measure and analyze incoming data in the time domain. This external input box contains an ADC701 and the necessary clock and drivers to provide high performance analog input. The ADC701 is a 16-bit 500kHz analog-to-digital converter. Included in the box is a companion sample/hold amplifier that provides outstanding dynamic performance. Operating as a spectrum analyzer, FFfs are used for viewing, measuring or analyzing incoming data in the frequency domain. Direct readout of harmonic content, THD, SNR, THD + SNR, DC offset and spurious-free dynamic range is possible. COMPUTER PLATFORM The system is designed to operate in an IBM PC/AT environment with an EGA or VGA monitor and Microsoft~ Mouse. Although the standard system does not include the computer platform, a factory supplied computer (IBM ATcompatible) is available as an option. If the computer is purchased, all of the components are tested as a complete system, and shipped from the factory as a "ready-to-use" instrument. (Contact Customer Support at 1-800-548-6132 for price and delivery information for the complete system including the computer platform) DSP PROCESSOR BOARD (ZPB34-004) The DSP processor board provided with the system uses an AT&T DSP32C processor. This processor is capable of 25MFLOPS and is able to perform a 32-bit multiply/accumulate instruction in 8Ons. The board has 576KB of local RAM and buffered high-speed (IOMBits per second) serial I/O ports. DIGITAL INPUT BUFFER (ZPB6064) In the event that an application may require that the data be buffered, two configurations of the system include a digital input buffer board. This high speed card will capture, and subsequentially transfer, up to 65,536 words of data. Buffer size is set through the PC I/O port for 32 to 65,536 words with a word being 16 bits of digital information on either the ECL or TTL input signal at speeds from near DC to 10MHz. Input data capture can be controlled by the Trigger function which can be either an external (ECLlITL) signal or a PC I/O control byte. Post trigger data capture can be set for I to maximum buffer size minus one. A second digital input buffer can be installed and slaved to the first card. The two boards can be triggered and clocked independently or simultaneously. When both buffers are full, the data can be serially transferred as 32-bit words (two concatenated 16-bit words). This feature can double the. effective capture speed or allow two independent 16-bit input paths. DYNAMIC SIGNAL ANALYSIS SOFTWARE At the heart of the system is the Dynamic Signal Analysis software which transforms the PC into a complete test and evaluation instrument, capable of analyzing data in time and frequency domain as well as producing linearity measurements. The software allows the PC to operate as any of three Burr-Brown Ie Data Book Supplement, Vol. 33b Functioning as an histogram analyzer, the user may display histograms, dynamic linearity (DNL), and integral linearity (INL). For convenience, the software is completely mousedriven, allowing the user to zoom, pan, move markers, use display lines, or change parameters with simple mouse movements. Setup save and load features are also included. DSP DEVELOPMENT SOFTWARE (ZPM32) A second integral piece of software provided for real-time development is DSPlay XL. Supplied with over 100 block functions, DSPlay XL uses F10WgramsTM (block diagrams of an application) to develop algorithms which are executed on the system's DSP processor. Once designed and verified, the executable code can be saved and ported to any DSP system using the AT&T DSP32 or DSP32C processors. HIGH PERFORMANCE WORKSTATION CONFIGURATIONS As an integrated system, the state-of-the-art development and evaluation tools described above form a user-friendly, yet extremely powerful, workstation environment for realtime DSP applications. Since the applications for DSP are varied, three configurations for the high performance development system are offered. Single Channel Analog Input System (DSP-SYS701001) Description The DSP-SYS701-001 is the basic system for acquiring and working with single input analog signals at the 16-bit 500kHz sampling rate of the ADC701. For applications where it is necessary to evaluate the incorporation of an ADC701 into a current design or design under development, the -001 system allows the user to analyze the effects of the high performance of the ADC701. Furthermore, this analysis can be accomplished with little more effon than making the appropriate connections and establishing the proper system setup. In addition to design suppon, the DSP-SYS701 may be used as the test software to characterize the performance of the user's system. A third application for the workstation is to . . . take advantage of the development software in order to - ' design DSP circuits that will enhance the performance of the .. user's system. DSP-SYS701 software will allow the user to not only develop the DSP algorithms, but will pon the executable code to any DSP32 or 32C processors for continIn ued use in the user's system. ~ 2 ~ 14-33 B For Immediate Assistance, Contact Your Local Salesperson Hlgh·Speed Serial FIGURE I. Single Channel Analog Input System. Single Channel Analog Input System With Digital Input Buffer (DSP-SYS701-o02) Description In certain applications that entail complicated post-processing. there may be a need for the capture of larger buffers. Simply stated. larger amounts of data can be captured in real-time. and stored. for post collection analysis. This configuration is designed for pre-trigger data analysis. such as that required in material testing. fatigue analysis. and scientific research. II L-_ _-, I I - - - - - - - - - - - High-Speed Serial FIGURE 2. Single Channel Analog Input System with Digital Input Buffer. Dual Channel Analog Input System (DSP-SYS701-o03) Description The -003 system configuration is designed for applications where simultaneous sampling is required. Included in this system are two analog input boxes along with two digital input buffer boards. As a dual input system configuration. independent high resolution samples can be taken simultaneously. then passed to the respective buffer board. where the two inputs are concatenated to form one 32-bit word for transfer to the DSP board for analysis and processing. Digital Input Buffer Sample Rate: .................... IOMHz max (externally adjustable) 14-34 FIGURE 3. Dual Channel Analog Input System. Data Format Out: ............. Differential line drivers. WE AT&T DSP32 serial format Base 110 Address: ............4 locations OXO - OX3FF DSP Processor Board Memory: ........................... 64KB 0 Wait State 512K I Wait State Oock Rate: ...................... .49.l52MHz Addressing: ....................... 110 Mapped 16 Ports Interrupts: ......................... Selectable IRQ3-7.9- I 2.14.15 Serial I/O: ......................... Buffered Differential Line Drivers and Receivers Terminated in loon Serial 1/0- Internal: .......... 6.lMBitsis DSP Development Software Over 100 functions in the following categories: Arithmetic suBgram Data Non-linear Filter O_scope Generator Spectrum Input_Output Trigonometric fiLe Window Measure Execution times for several common functions: 1024 Point Complex FFT .............. 3.8ns 128 Tap FIR Filter ......................... 8Ons x 128taps Second Order IIR Section .............. 80ns x 5 Dynamic Signal Analysis Software Software performs instrumentation functions for: Digitizing Scope Spectrum Analyzer Histogram Analyzer Configuration Hardware Requirements: IBM AT Compatible 640K memory Burr-Brown Ie Data Book Supplement. Vol.33b Or, Call Customer Service at 1·800·548·6132 (USA Only) SPECIFICATIONS PARAMETER DYNAMIC CHARACTERlSnCS Sample Rate Dynamic Nonlinearity Toial Harmonic Dlstortlon (THO) CONDmONS MIN Unadjusted DC =20kHz(~.3dB) I~ Slgnal·to·Nolse·Ratio (SNR) I.. = , 99kHz(~.2dB) IN 20kHz(~.3dB) I~ 199kHz(-I2dB) I, 195kHz(-(I.5dB) I, = 200kHz(-8.5dB) I, = 195kHz(-12.5dB) I, = 200kHz(-12.5dB) IN = 5kHz (~.5dB) INPUTS Analog Input Range Jumper Selectable Spurious·Free Dynamic Range Two·Tone IntermOdulaUon Distortion = = = MAX UNITS 500 iO.002 0.00068 0.0078 107.1 93.8 -81.4 kHz O/OFSR 0/0 0/0 dB dB dBc -86.2 dBc 93 dB TYP 0 -10 -5 -10 0 Inpullmpedance Digiial Logic Family Convert Command Pulse Width V V V V V 10 10 5 0 5 600 II I-50 ns TTL PosiUveEdge Math Co-processor Mass Storage - Hard disk and one floppy drive Monitor - EGA or VGA Printer (Optional) - IBM graphics printer, HP Laser jet printer or compati bles 50 Connection Cables DSP Development Software Manual Dynamic Signal Analysis Software Manual DSP-SYS701 User's Manual ORDERING INFORMATION Software Requirement PC/MS-DOS Version 3.0 or higher. Optional (Configured Hardware System), Includes High Performance 386 PC Burr-Brown will provide, as an option, an entire test/evaluation system including the required configuration hardware and software. With the purchase of this option,the system is configured and tested prior to shipment. Thus, the customer will receive a complete turnkey test/evaluation system for the ADC701. The configuration hardware will be a high performance, 386 computer (without printer). For details of the exact computer specifications to be used at the time of shipment, contact your sales representative. SUPPLIED ACCESSORIES Power Supply for the Analog Input Box Power connectors Burr-Brown Ie Data Book Supplement. Vol.33b To order, please specify: DSP-SYS701-001 .......... Single Channel Analog Input System DSP-SYS701-002 .......... Single Channel Analog Input System with Digital Input Buffer DSP-SYS701-003 .......... Dual Channel Analog Input System with Digital Input Buffers DSP-SYS701-XXXA ..... Analog Input System Including Configured Hardware System FOR MORE INFORMATION For more information contact Applications Engineering at 1-800-548-6132. FlowOramT'M Burr·Brown Corp. DSPIay XL'" BUIT·Brown Corp. DSPccd'" BUIT·Brown Corp. WE" DSP32C AT&T Corp. IBM" PC IBM Corp. BURR-BROWN USA SALES OFFICES & SALES REPRESENTATIVES IUIIII...... IIOIIUIIIIDE IWIIQIIAIITElIS Inl~rrational Airport Ind Pari< 1EY1IDA'~ ~:~Q Bllr-8rown Corporallon Sull,6 Suile 106 600 E. Allamanle Dr. ~:~~~ ~;~'IsFl 32701 FAX: (407)1I3CHl627 ==~"tn Sull,274 28731 Roadside Dr. 91301 991-8544 or 496-7581 991-7872 FAX: N. largo. Fl 33543 ~~('Jf~~~Js - _IIIIII'SIIIIIE Corporallon Btrr-8rown Corporalion SUile3C r.,\i'~~~~~1803 _IA Burr·Brown Corporation SuilelO8A 2121 S. MiliA.... Tempe. A7. 85282 Tel: (602) 966-4601 FAX: (602) 966-5065 AIUIAIISAS Burr-Brown Corporation Suile5lll.lB·4 11910 Gre,nville Ave. Dallas. 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