1990_Fujitsu_Static_RAM_Products 1990 Fujitsu Static RAM Products

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High-Speed CMOS SRAMs
High-Speed SiCMOS SRAMs
Low-Power CMOS SRAMs
Application-Specific SRAMs
High Temperature Range SRAM Products
CMOS SRAM Modules

EI
lID
lEI

-ImI

lOll
ID

Quality and Reliability

..

Ordering Information
Sales Information
Appendices - Design Information
/

IDII

OJ

FUJITSU

Static RAM Products
1990

Data
Book

Fujitsu Limited
Tokyo. Japan
Fujitsu Microelectronics. Inc.
San Jose. California. U.S.A.
Fujitsu Mikroelectronik GmbH
Frankfurt. F.R. Germany
Fujitsu Microelectronics Asia PTE Limited
Singapore

Copyright© 1990 Fujitsu Microelectronics, Inc., San Jose, California
All Rights Reserved.
Circuit diagrams using Fujitsu products are included to illustrate typical semiconductor applications. Information sufficient for
construction purposes may not be shown.
The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu
Microelectronics, Inc. assumes no responsibility for inaccuracies.
The information conveyed in this document does not convey any license under the copyrights, patent rights or trademarks
claimed and owned by Fujitsu Limited, its subsidiaries, or Fujitsu Microelectronics, Inc.
Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice.
No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior
written consent of Fujitsu Microelectronics, Inc.
This document is published by the Publications Department, Fujitsu Microelectronics, Inc.,
3545 North First Street, San Jose, California, U.S.A. 95134-1804; U.S.A.
Printed in the U.S.A.
Edition 1.0

Contents and Alphanumeric Product List
SRAM Products

Introduction -

SRAM Products ........................................ vii

Section 1 - High-Speed CMOS SRAMs MB81C67-35/-45/-55
MB81 C68A-25/-30/-35
MB81 C69A-25/-30/-35
MB81C71A-25/-35
MB81C74-25/-35
MB81C75-25/-35
MB81 C78A-35/-45
MB81C79A-35/-45
MB81C81A-35/-45
MB81 C84A-35/-45
MB81C86-55/-70
MB8289-25/-35

At a Glance ...................... 1-1

CMOS 16384 x 1 bit SRAM ....................... 1-3
CMOS 4096 x 4 bits SRAM ...................... 1-15
CMOS 4096 x 4 bits SRAM ...................... 1-27
CMOS 65536 x 1 bit SRAM ...................... 1-39
CMOS 16384 x 4 bits SRAM ..................... 1-51
CMOS 16384 x 4 bits SRAM ..................... 1-61
CMOS 8192 x 8 bits SRAM ...................... 1-73
CMOS 8192 x 9 bits SRAM ...................... 1-87
CMOS 262144 x 1 bit SRAM .................... 1-101
CMOS 65536 x 4 bits SRAM ................... 1-113
CMOS 65536 x 4 bits SRAM . . . . . . . . . . . . . . . . . . . . 1-123
CMOS 32768 x 9 bits SRAM .................... 1-131

Section 2 - High-Speed BiCMOS SRAMs MB82B001-25/-35
MB82B005-25/-35
MB82B006-25/-35
MB82B71-15/-20
MB82B74-15/-20
MB82B75-15/-20
MB82B79-15/-20
MB82B81-15/-20
MB82B84-15/-20

Section 3 - Low-Power CMOS SRAMs MB8464A -80/ULL
-10/ULL. -15/ULL
MB84256 -10/ULL
-121ULL. -15/ULL
MB84256A-70/ULL
-10/ULL. -15/ULL
MB84F256-25
MB841000-80/-10/-12/L

At a Glance ....................

2-1

BiCMOS 1048576 x 1 bit SRAM ................... 2-3
BiCMOS 262144 x 4 bits SRAM .................. 2-11
BiCMOS 262144 x 4 bits SRAM .................. 2-19
BiCMOS 65536 x 1 bit SRAM .................... 2-27
BiCMOS 16384 x 4 bits SRAM ................... 2-37
BiCMOS 16384 x 4 bits SRAM ................... 2-45
BiCMOS 8192 x 9 bits SRAM .................... 2-55
BiCMOS 262144 x 1 bit SRAM ................... 2-65
BiCMOS 65536 x 4 bits SRAM ................... 2-73

At a Glance ...........................

3-1

CMOS 8192 x 8 bits SRAM ....................... 3-3
CMOS 32768 x 8 bits SRAM ..................... 3-15
CMOS 32768 x 8 bits SRAM ..................... 3-25
CMOS 32768 x 8 bits SRAM ..................... 3-35
CMOS 131072 x 8 bits SRAM with Data Retention .... 3-47

iii

Contents and Alphanumeric Product List (Continued)
SRAM PRODUCTS

Section 4 -Application Specific SRAMs MB81 C51-25/-30
MB81 C79B-35/-45
MB8279RT-20/-25
MB8287-25/-35
MB8421-90/-121L
MB8422-90/-121L
M B8431-90/-121ULL
M B8432-90/-121ULL

At a Glance . ....................

CMOS 2048 x 8 bits SRAM ...................... 4-69

Section 5 - Wide Temperature Range SRAM Products MB81C68A-45W
MB81C78A-45W
MB81C79A-45W
MB8464A-10W/-15W

CMOS 4096 x 4
CMOS 8192 x 8
CMOS 8192 x 9
CMOS 8192 x 8

Section 6 - CMOS SRAM Modules MB85402-30/-40
MB85403-40/-50
MB8541 0-30/-40
MB85414-30/-40
MB85420-40/-50

4-1

CMOS 512 x 411024 x 2 TAG RAM ................. 4-3
CMOS 8192 x 9 bits SRAM ...................... 4-19
CMOS 8192 x 9 bits STRAM ..................... 4-31
CMOS 32768 x 8 bits SRAM with PE .............. 4-43
CMOS 2048 x 8 bits SRAM ...................... 4-55

bits
bits
bits
bits

SRAM
SRAM
SRAM
SRAM

At a Glance ...........

5-1

....................... 5-3
...................... 5-11
...................... 5-23
...................... 5-35

At a Glance ...............................

6-1

CMOS 16384 x 16 bits SRAM Module .............. 6-3
CMOS 262144 x 8 bits SRAM Module ............. 6-11
CMOS 65536 x 8 bits High Speed SRAM Module .... 6-19
CMOS 16384 x 32 bits High Speed SRAM Module ... 6-27
CMOS 252144 x 8 bits High Speed SHAM Module ... 6-35

Section 7 - Quality and Reliability -

At a Glance ..........................

7-1

Quality Control at Fujitsu ................................................... 7-3
Quality Control Processes at Fujitsu .......................................... 7-4

At a Glance . ..........................

8-1

IC Product Marking .......................................................
IC Ordering Code (Part Number) ............................................
IC Package Codes .......................................................
IC Module Ordering Code (Part Number) ......................................
IC Module Package Codes .................................................
Wide Temperature IC Ordering Code (Part Number) .............................
Wide Temperature IC Package Codes ........................................

8-3
8-3
8-3
8-4
8-4
8-5
8-5

Section 8 - Ordering Information -

Iv

Contents and Alphanumeric Product List (Continued)
SRAM PRODUCTS

Section 9 - Sales Information -

At a Glance . .............................

9-1

Introduction to Fujitsu ..................................................... 9-3
Integrated Circuits Corporate Headquarters - Worldwide .......................... 9-7
FMI
Sales Offices for North and South America ............................. 9-8
FMI
Representatives - USA ............................................. 9-9
FMI
Representatives - Canada ......................................... 9-11
FMI
Representatives - Mexico .......................................... 9-11
FMI
Representatives - Puerto Rico ...................................... 9-11
FMI
Distributors - USA ............................................... 9-12
FMI
Distributors - Canada ............................................. 9-16
FMG
Sales Offices for Europe ........................................... 9-17
FMG
Distributors - Europe ............................................. 9-18
Sales Offices for Asia and Australia .................................. 9-20
FMA
FMA
Representatives - Asia ............................................ 9-21
FMA
Distributors - Asia and Austraila ..................................... 9-22

Section 10 - Appendices - Design Information ......................... 10-1
Appendix 1. Design Applications. Internally timed RAMs build fast writeable
control stores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

Appendix 2. Application Note: Separate Data Inputs and Outputs SRAMs Provide New
Architectural Solutions for System Designers . . . . . . . . . . . . . . . . . . . . . . . 10-7

Appendix 3. Application Handbook: The Effective Design of CMOS-based
Caches in CISC- and RISC-based Architectures ................... 10-27

v

Contents and Alphanumeric Product List (Continued)
SRAM PRODUCTS

Alphanumeric List of Fujitsu Part Numbers
MB81C51-25/-30 ............ 4-3

MB81C67-35/-45/-55 . . . . . . . .. 1-3
MB81C68A-25/-301-35 ...... 1-15
MB81C68A-45W ............ 5-3
MB81C69A-25/-301-35 ...... 1-27
MB81C71A-251-35 ......... 1-39
MB81C74-25/-35 . . . . . . . . . .. 1-51
MB81C75-25/-35 . . . . . . . . . .. 1-61
MB81C78A-35/-45 ......... 1-73
MB81C78A-45W ............ 5-11
MB81C79A-35/-45 ......... 1-87
MB81C79A-45W ........... 5-23
MB81C79B-35/-45 ......... 4-19
MB81C81A-35/-45 ........ 1-101
MB81C84A-35/-45 ......... 1-113
MB81C86-55/-70 . . . . . . . . .. 1-123
MB8279RT-201-25 . . . . . . . . .. 4-31
MB8287-25/-35 ............ 4-43
MB8289-25/-35 ........ . .. 1-131
MB82B001-251-35 . . . . . . . . . .. 2-3
MB82B005-251-35 ........... 2-11
MB82B006-25/-35 .......... 2-19
MB82B71-151-20 ........... 2-27

vi

MB82B74-151-20 ............
MB82B75-151-20 ............
MB82B79-151-20 ............
MB82B81-151-20 ............
MB82B84-15/-20 ............
MB8421-901-121L ...........
MB8422-901-121L ...........
MB8431-901-121ULL .........
MB8432-901-121ULL .........
MB8464A-10W/-15W ........
MB8464A-80IULL. -10IULL.

2-37
2-45
2-55
2-65
2-73
4-55
4-55
4-69
4-69
5-35

-15IULL ........... 3-3
MB84256A-70IULL. -10IULL.
-121ULL. -15IULL .. 3-25
MB84256 -1 OIULL. -121ULL.
-15IULL ........... 3-15
MB84F256-25 .............. 3-35
MB841000-801-101-121L ...... 3-47
MB85402-30/-40 ............. 6-3
MB85403-401-50 ............ 6-11
MB85410-30/-40 ............ 6-19
MB85414-30/-40 ............ 6-27
MB85420-40/-50 ............ 6-35

Introduction

Page

ix

Fujitsu's Static RAM Products

vii

Introduction

viii

Static RAM Data Book

Fujitsu's Static RAM Products
Introduction
Fujitsu manufactures a wide range of integrated circuits that
includes linear products, microprocessors,
telecommunications circuits, ASICs, high-speed ECl logic,
power components (consisting of both discrete transistors
and transistor arrays), and both static and dynamic RAMs.
The static RAM product line offers devices for use in a wide
range of applications. These memories are manufactured to
meet the high standard of quality and reliability that is found
in all Fujitsu products.
This data book includes product information on the following
SRAM products:

High-speed CMOS SRAMs
Fujitsu's high-speed CMOS SRAMs offer the advantages of
low power diSSipation, low cost, and high performance.
Features include TTL compatibility and a separate
chip-select pin that simplifies multipackage systems design.

High-speed BiCMOS SRAMs
Advanced SiCMOS technology adds ultra-fast access times
to CMOS low power dissipation in Fujitsu's new family of
static RAMs. Most devices feature an automatic power-down
mode and are generally available in small outline packages
with J-Ieads (SOJ).

Low-speed CMOS SRAMs
Our low-power CMOS SRAMs are ideally suited for use in
microprocessor systems and other applications where fast
access time and ease of use are required. The memories
use asynchronous circuitry and may be maintained in any
state for an indefinite period of time.

Application-Specific SRAMs
To address the system needs of cache memory chips,
Fujitsu's application-specific memory line includes both
cache TAG RAM and high-speed static RAM, as well as port
RAMs for muHiprocessor systems.

Ix

Fujitsu's Static RAM Products

(Continued)

WIde Temperature Range SRAMs

For applications requiring MIL-STD-883 processing, Fujitsu
offers a selection 01 high-performance, TTL-compatible
CMOS static RAM products. All of these devices operate in
the 'W" temperature range, generally 55° to 125°C. (See
product specifications lor specific temperature range.)
CMOS SRAM Modules

Fujitsu manufactures a complete family 01 reliable CMOS
static RAM memory modules lor those applications requiring
high density and large memory storage capability. Fujitsu's
family of memory modules are pin-compatible with JEDEC
standards.

x

Section 1

High-Speed CMOS SRAMs Maximum
Acc...s
Time (ns)

Page

Device

1-3

MB81C67-35

-45
-55
1-15

MB81 C68A-25

-30
-35
1-27

MB81 C69A-25

Ata Glance

Capacity

Package
Options

35
45
55

16384 bits
(16384w x lb)

20-pin Plastic
DIP
20-pin Ceramic DIP
2(}-pad Ceramic LCC

25
30
35

16384 bits
(4096w x4b)

2(}-pin
20-pin

Plastic
DIP,ZIP
Ceramic DIP

16384 bits
(4096w x 4b)

20-pin
20-pin

Plastic
DIP
Ceramic DIP

-35

25
30
35

1-39

MB81C71A-25
-35

25
35

65536 bits
(65536w x 1b)

22-pin Plastic
DIP
24-pin Plastic
LCC
22-pad Ceramic LCC

1-51

MB81C74-25
-35

25
35

65536 bits
(16384w x 4b)

22-pin Plastic
DIP
22-pad Ceramic LCC

1-51

MB81C75-25
-35

25
35

65536 bits
(16384w x 4b)

24-pin
24-pin

1-73

MB81C78A-35
-45

35
45

65536 bits
(8192w x8b)

28-pin Plastic
DIP, FPT
32-pad Ceramic LCC

1-87

MB81C79A-35
-45

35
45

73728 bits
(8192w x 9b)

28-pin Plastic
DIP, FPT
32-pad Ceramic LCC

1-101

MB81C81A-35
-45

35
45

262144 bits
(262144w x lb)

24-pin Plastic
DIP, LCC
24-pin Ceramic DIP
24-pad Ceramic LCC

1-113

MB81C84A--35
-45

35
45

262144 bits
(65536w x 4b)

24-pin

1-123

MB81C86-55

55
70

262144 bits
(65536w x 4b)

28-pin Ceramic DIP
32-pad Ceramic LCC

25
35

262144 bits
(32768w x 9b)

32-pin

-30

-70
1-131

MB8289-25
-35

Plastic
Plastic

Plastic

Plastic

DIP
LCC

DIP, LCC

DIP, FPT

1-1

..

Hieh-speed CMOS SRAMs

..

1-2

Static RAM Data Book

MB 81C67-35
MB 81C67-45
MB 81C67-55
March 1986
Edition 2.0

16,384 WORDS x1 BIT HIGH SPEED
CMOS STATIC RANDOM ACCESS MEMORY
The Fujitsu MB 81 C67 is 16,384 words x 1 bit static random access memory
fabricated with a CMOS silicon gate process. All pins are TTL compatible and
a single 5 volts power supply is required.
CERAMIC PACKAGE
CERDIP
DIP-20C-C03

For ease of use, chip select (CS) permits the selection of an individual package
when outputs are OR·tied, and automatically power down the MB 81 C67. All
devices offer the advantages of low power dissipation, low cost, and high performance.

• Organization: 16,384 words x 1 bit
• Static operation: No clocks or refresh required
• Fast access time: 35 ns max. (MB 81C67-35)
45 ns max. (MB 81 C67-45)
55 ns max. (MB 81C67-55)
• Single +5 V supply, ±10% tolerance
• Separate data input and output
• TTL compatible inputs and output
• Three-state output with OR-tie capability
• Chip select for simplified memory expansion, automatic power down
• All inputs and output have protection against static charge
• Standard 20-pin DIP package (Suffix: CZ, Suffix: P)
• Standard 20-pad Leadless Chip Carrier (Suffix: TV)
• Pin compatible with Fujitsu MB 8167A

CERAMIC PACKAGE
LCC-20C-FOl

PLASTIC PACKAGE
DIP-20P-MOl

PIN ASSIGNMENT

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating

Symbol

Value

Unit

Supply Voltage

Vcc

-0.5 to +7.0

V

Input Voltage on any pin
with respect to GN D

V 1N

-3.5 to +7.0

V

Output Voltage on any pin
with respect to GND

VOUT

-0.5 to +7.0

V

Output Current

lOUT

±50

mA

PD

1.2

W

T B1AS

-10 to +85

°c

Power Dissipation
Temperature under Bias
Storage
Temperature

I Ceramic

I Plastic

TSTG

-65 to +150
-45 to +125

V"

A,Ao I AI3
t~1~t_ol~9J

:; H
~: ~j

f:~ ~I'~

TOP VIEW

As ?~

t~: :~o
~1_4 As

Dour ~J

~~3 Al
r9T\-oT,-,T'-2~

°c

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATI NGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

WE

C5DIN
GNO

This devic.e contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised

that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit.

1-3

..

1IIIIIIIIIIIIIIIIIIIIIIImlllllllllllllllllllilim

FUJITSU

11111111111111111111111111111~lllmlllllllllllllll

MB 81C67-35
MB 81C67-45
MB 81C67-55

..

Fig. 1 - MB 81C67 BLOCK DIAGRAM

A'2----------II......-I~---I

-----vee

A'3-------1;~~====~
AO ----------II.A~---I
A,

-GNO
CELL ARRAY
128 ROWS
128 COLUMNS

ROW
SELECT

-------t~======l

COLUMN 1/0 CIRCUITS

DOUT

COLUMN SELECT
INPUT
DATA
CO NT.

TRUTH TABLE
CS

WE

MODE

OUTPUT

POWER

H

X

NOT SELECTED

HIGH-Z

STANDBY

L

L

WRITE

HIGH-Z

ACTIVE

L

H

READ

DOUT

ACTIVE

CAPACITANCE ITA = 2SoC, f = 1 MHz)
Parameter
Input Capacitance (V IN
CS Capacitance (Ves

= 0 V)

Output Capacitance (V OUT

1-4

= 0 V)

Typ

Max

Unit

C IN

5

pF

Ces

7

pF

COUT

8

pF

Symbol

= 0 V)

MB 81C67-35
MB 81C67-45
MB 81C67-5 5

lilllllll!IIII!1111111111111111111111111111111111111

FUJITSU
II111111I1111111111111111111111111111111111111111111

..

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter

Symbol

Min

Typ

Max

Unit

5.0

5.5

V

Supply Voltage

Vee

4.5

Input Low Voltage

V'L

-3.0'

O.B

V

Input High Voltage

V ,H

2.2

6.0

V

Ambient Temperature

TA

0

70

°c

*-3.0V Min. for pulse width less than 20ns. (V ,L Min ~ -1.0 V at DC level)

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)

Test Condition

Parameter
I nput Leakage
Current

V ,N

~

0 V to Vcc

Symbol

Min

Typ

Max

Unit

III

-2.0

2.0

JlA

I LO

-2.0

2.0

JlA

Output Leakage
Current

CS~V'H'

Active Supply

Current

CS ~ V,L, lOUT ~ 0 mA
V ,N ~ V,L or V ,H

Icc1

25

40

mA

Operating Supply
Current

CS ~ V,L, lOUT ~ 0 mA
Cycle ~ Min, CL ~ 0 pF

ICC2

35

60

mA

ISB1

2

15

mA

IS82

15

25

mA

0.4

V

Standby Supply
Current

VOUT~OVtoVcc

CS :;; V cc - 0.2 V
V ,N :;; Vee -0.2 V or
V'N~O.2V

StandbY Supply
Current

CS ~ V ,H

Output Low
Voltage

IOL

16 mA

VOL

Output High
Voltage

IOH ~ -4 mA

V OH

~

2.4

V

1-5

1IIIIIIIIIIIIImlmlilimmmlllllllllllllllili

FUJITSU
1IIIIIIIIIIIIIIIIIIIImlllllllllllllllllllllllllili

MB 81C6 7-35
MB 81C67-45
MB 81C67-55

..

AC TEST CONDITIONS

Input Pu lse Levels;

0.6 V to 2.4 V

Input Pulse Rise And Fall Times;

5 ns

Timing Measurement Reference Levels;

Input ; 1.5 V
Output; 1 .5 V

Output Load;

Fig.2

Load I

Load II

2V

2V

T,on

T,on

~DOUT

~DOUT

1

I

30 pF (Including Scope
and jig capacitance)

s pF

(Including Scope
and jig capacitance)

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE *1
Parameter

Read Cycle Time' 2

tRC

Address Access Time 3
Chip Select Access

MB 81C67-45

MB 81C67-55

Min

Min

Unit
Max

45

35

tAA
t ACS

Max

Max
ns

55

35

45

55

ns

35

45

55

ns

tOH

5

5

5

ns

Chip Selection to Output in Low-Z' s

tLZ

5

5

5

ns

Chip Deselection to Output in High-Z's

tHZ

0

Chip Selection to Power Up

tpu

0

Chip Deselection to Power Down

tpo

Output Hold from Address Change

Note:

1-6

Time' 4

MB 81C67·35
Min

Symbol

25

0

25

30

0

30

40

ns
ns

0

0

50

ns

"1 WE is high for Read cycle.
*2 All Read cycle are determined from the last address transition to the first address transition of the next address.
*3 Device is continuously selected, CS = V 1L .
*4 Address valid prior to or coincident with CS transition low.
*5 Transition is measured at the point of ±500mV from steady state Voltage.

MB 81C67-35
MB 81C67-45
MB 81C67-5 5

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

..

READ CYCLE TIMING DIAGRAM"'2
READ CYCLE: ADDRESS CONTROLLED' 3
tRC

ADDRESS

\~

'IV

II\.

I'
tAA

tOH_

DOUT

PREVIOUS DATA
VALID

DATA VALID

READ CYCLE: CS CONTROLLED*4
1--------tRC------~

HIGH-Z

DOUT

tpu

ICC

50%

IS8

~

Note:

*,

*2
*:3
*4
*5

: Undefined

WE is high for Read cycle.
All Read cycle are determined from the last address transition to the first address transition of the next address.
Device is continuously selected, CS ~ V'L.
Address valid prior to or coincident with CS transition low.
Transition is measured at the point of ±500mV from steady state voltage.

1-7

..

1lllmlllllllllllllllmlllll~mlllllllmlllllll
FUJITSU

1l l l l l l l l l l l l l lml l l l ml l~1 1 1

MB 81C67-35
MB 81C67-45
MB 81C67-55

WRITE CYCLE'1'2
Parameter

Symbol

MB 81C67-35
Min

Max

MB 81C67-45

MB 81C67-55

Min

Min

Max

Max

Write Cycle Time '3

twc

35

45

55

ns

Chip Selection to End of Write

tcw

30

35

50

ns

Address Valid to End of Write

tAW

30

35

50

ns

Address Setup Time

tAs

0

0

0

ns

Write Pulse Width

twp

20

25

30

ns

Data Valid to End of Write

tow

20

20

25

ns

0

0

ns

Write Recovery Time

tWR

0

Data Hold Time

tOH

0

Write Enable to Output in High-Z'4

twz

Output Active from End of Write '4

tow

ns

0

0

0

25

0

25

0

30

ns

0

25

0

25

0

30

ns

WRITE CYCLE TIMING DIAGRAM*1*2
'WRITE CYCLE: WE CONTROLLED'3

1 - - - - - - -t w c - - - - - - - - - 1
ADDRESS

I-----tcw,----~

~-----tAW'------

,o.~
DOUT

HIGH-Z

~

: Undefined

Note: *1 CS or WE must be high during address transition.
*2 If CS goes high simultaneously with WE high, the output remains in high impedance state.
*3 All Write cycle are determined from the last address transition to the first address transition of next address.
*4 Transition is measured at the point of ±500mV from steady state voltage.

1-8

Unit

MB 81C67-35 11111~~~~m~~~~~~llm~~~m~~IMI
MB 81C67-45 FUJITSU
MB 81C6 7-5 5 1~lllmlllllllllllllllll~llllllmlllll~~111111

..

WRITE CYCLE TIMING DIAGRAM*!*2

WRITE CYCLE: CS CONTROLLEO'3
~---------------twc--------------~

ADDRESS
~~tA~S-+----------tcw--------~~

f-------twp-----I

tow----1----I
DATA VALID

DOUT

_________

~H~IG~H~-Z~ ;~---~H~IG~H~-~Z----------------------------___
tL__

~

Note: *1
*2
*3
*4

: Undefined

CS or WE must be high during address transistion.
If CS goes high simultaneously with WE high, the output remains in high impedance state.
All Write cycle are determined from the last address transistion to the first address transition of next address.
Transition is measured at the point of ±500mV from steady state voltage.

1-9

..

1111111111111111111111111111111111111111111111111111

FUJITSU
111111111111111111111111111I11I111111I11111111111111

MB 81C67-35
MB 81C67-45
MB 81C67-55

TYPICAL CHARACTERISTICS CURVES
Fig. 3 - NORMALIZED ACCESS TIME
VS. SUPPLY VOLTAGE

Fig. 4 - NORMALIZED ACCESS TIME
VS. SUPPLY VOL TAG E
W

W

:;:

:;:

~

~

W

0

-0..

-0..

5.5

0.5':-7_ _ _ _="=-_____='
4.5
5.0
5.5
V ee. SUPPLY VOLTAGE (VI

1-10

MB 81C67-3 5
MB 81C67-45
MB 81C67-55

Fig. 9 -NORMALIZED POWER SUPPLY CURRENT
vs. AMBIENT TEMPERATURE

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

Fig.10-NORMALIZED POWER SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
10

a:
W

;:

Vee = 5.5V

a:

o0..

w

;:f-

fOZ

:i'z

~ ~ 1.ol----f"""";::--+---1I----j

OW

:;;U

..JU

::Ja:
«::J
a:>
O..J
zo..
N!3 0.91----+--+----If"oo..--j
uoo

.S'

a:

w

Na:
_::J

«>
a:o.
00..
z ::J
oo

:;; ..J

"''"

u
u

O.B 0~--;2.f;;0--4-;tO;----;!6;;-0-~BO

20
40
60
BO
100
T A. AMBIENT TEMPERATURE (OC)

T A. AMBIENT TEMPERATURE (OC)

Fig. 11 - NORMALIZED POWER SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
Vee

Fig. 12 -OUTPUT VOLTAGE
vs. OUTPUT CURRENT
3.4r-----,-------,
T A = 25°C

~ 5.5V

a:

~

;:f-

w
C!l

W

Oz

0.. W

o a:
wa:
N::J
::Ju
«>

/

2

V

:;;..J

gj ~

1

./

~..J
o

~

>
f-

::J

0.

f-

::J

o

Zoo
N

:i:

o
>

"''"

o

2.60~-------:-5----~10

20
40
60
BO
100
T A • AMBIENT TEMPERATURE (OC)

IOH. OUTPUT CURRENT (rnA)

Fig. 14 -NORMALIZED POWER SUPPLY CURRENT
vs. FREQUENCY

Fig. 13 -OUTPUT VOLTAGE
vs. OUTPUT CURRENT

loB

0.4

C!l

«

TA = 25°C

TA= 25°C

~
w

a:
w

Vee = 4.5V

:i'z
w
Oa:
wa:

f-

f-

~::J

..JU 1.0

0.2

«>
:;;..J
a:o.
00.
z::J
CI)

::J
0.
f-

::J

0

j

Vee = 5.5V

;:f- 1.4

0.3

..J
0

>

Vee= 4.5V

0.1

N
u

0

>

0.6

r--

.S'

0.2
20
IOL. OUTPUT CURRENT (rnA)

1

V
10
f. FREQUENCY (MHz)

100

1-11

..

MB 81C67-35
MB 81C67-45
MB 81C67-55

1IIIIIIIIIIIIIIIIIIIIIIIIIIImllllllllllllllllllili

FUJITSU
1111111111111111111111111111111111111111111111111111

Fig. 15 -NORMALIZED ACCESS TIME
VS. LOAD CAPACITANCE

Fig. 16 - NORMALIZED ACCESS TIME
VS. LOAD CAPACITANCE
w
:;;

~

w

0l
1.3 I- A = 25 C
Vee= 4.5V

:;;
j:

'"'"wu

j:

'/

1.2

u

«
0

w

/

1.1

N

:::;

«
:;;

1.0

a:

0

z

.."..

V

w
u
u

./

Vee = 4.5V

1.2

«

V

N

1.1

:::;

«
:;;
a:

r'

1.0

0

z

"'
u

a

:!50

100

I-~A = 250lC

0

w

.( 0.9

:!-

1.3

(I)
(I)

150

200

C L • LOAD CAPACITANCE (pF)

V

0.9

a

-50

:...--r-----

100

150

200

CL. LOAD CAPACITANCE (pF)

PACKAGE DIMENSIONS
(Suffix: CZ)
20·LEAD CERAMIC (CERDIP) DUAL IN·lINE PACKAGE
(CASE No.: DIP·20C·C03)

I

R .02510.641
REF

.28417.211
.30217.671

1-.31317.95)

'325ru~;:::----+_..L

.940 123.881
1.000 125.4)
.01410.361

.09012.29)
.11012.791
.900122.86IREF

© 1986 FUJITSU LIMITED D2000B$-3C

1-12

.015(0.381
.02310.58)

Dimensions in inches
(millimeters)

MB B1C67-35 il l l l l l l l l l l l l l l l l l l l l l l l il
MB 81C67-45 FUJITSU
MB 81C67-55
1111111111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS
(Suffix: TV)
20-PAD CERAMIC (FRIT SEAL) LEADI:ESS CHIP CARRIER
(CASE No.: LCC-20C·F01)

n

. . 11

R.00810.20ITYP
120PLCSI

.420110.671
.435111.051

.33518.511
TYP
.25016.351

.02510.641

JP

TYi'i_
I-

t-

.087512.221
TYP

L-__~~~~~~

.28017.11)
.29517.491

1.10012.541
MAX

.~~~1.271

~~~

.04511.141
TYP

Dimension in
inches (millimeters)
©1985 FUJITSU LIM ITED C2Q003S-1 C

1-13

..

1IIIIIIIIIIIIIIIIIIIIIIIImllllllllllllillmili

FUJITSU
I111111111111111111111111111111111111111111111111

MB B1C67-35
MB 81C67-45
MB 81~7-55

PACKAGE DIMENSIONS
(Suffix: P)

20-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP·20P-M01)

-fF=:::::::::==,.l,15 o MAX

.29017.371
.31017.871

.05011.27IMAX

.03410.861
.04611.161

.17214.36IMAX

.11813.0IMIN
.10012.541

TYP
©1986 FUJITSU LIMITED D200Q5S·1C

1-14

Dimensions in
inches (millimeters)

11111111111111111111111111111111111111111111111111111111111111111

FUJITSU

CMOS 16384-BIT
STATIC RANDOM
ACCESS MEMORY

MB81C68A-25
MB81C68A-30
MB81C68A-35

11111111111111111111111111111111111111111111111111111111111111111
January 1988
Edition 2.0

4K x 4 (16,384-BIT) STATIC RANDOM ACCESS
MEMORY WITH SUPER HIGH SPEED AND
AUTOMATIC POWER DOWN
The Fujitsu MB 81C68A is 4096 words x 4 bits static random access memory
fabricated with a CMOS silicon gate process. The memory utilizes asynchro·
nous circuitry and all pins are TTL compatible and a single 5 volts power
supply is required.
A separate chip select (CS) pin simplifies multipackage systems design. It per·
mits the selection of an individual package when outputs are OR-tied, and
furthermore on selecting a single package by CS, the other deselected packages

CERAMIC PACKAGE
CERDIP
(DIP·20C-C03)

automatically power down.
All devices offer the advantages of low power dissipation, low cost, and high

performance.
•

•
•

Organization: 4096 words x 4 bits
Static operation: No clocks or timing strobe required
Fast access time: tAA ~ tAcs ~ 25 ns max. (MB 81C68A-25)
tAA ~ t ACS ~ 30 ns max. (MB 81C68A-30)

•
•
•

tAA ~ t ACS ~ 35 ns max. (MB 81C68A-35)
Low power consumption: 385 mW max. (Active)
138 mW max. (Standby, TTL level)
83 mW max. (Standby, CMOS level)
Single +5V supply ±1 0% tolerance
TTL compatible inputs and outputs
Three-state outputs with OR-tie capability

•

Chip select for simplified memory expansion, automatic power down

•
•
•

All inputs and outputs have protection against static charge
Standard 20-pin DIP (Suffix -P(plastic)/Suffix: -Z(cerdip))
Standard 20-pad LCC (Suffix: -TV)

•

Standard 20-pin ZIP

•

PLASTIC PACKAGE
(DIP-20P-M01)

PLASTIC PACKAGE
(ZIP-20P-M01)

PIN ASSIGNMENT

(Suffix: -PSZ)

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating

Symbol

Value

Unit

Supply Voltage

Vee

-0.5 to +7

V

Input Voltage on Any Pin with
respect to G N D

V'N

-3.5 to +7

V

Output Voltage on Any I/O Pin
with respect to GND

V OUT

-0_5 to +7

V

Output current

lOUT

±20

mA

Power dissipation

Po

1.0

W

Temperature under Bias

T BIAS

-10 to +85

°c

Storage Temperature

IICERAMIC
PLASTIC

NOTE:

T STG

-65 to +150
-45 to +125

(

liJ liJ liJ ~ ,.~'L @J C'J l"J @Jl'D~
r-;JJil888RRRRR

°c

Permanent device damage may occur if ABSOLUTE MAXIMUM
RATI NGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposu'e to absolute maximum rating conditions for extended
periods may aHect device reliability.

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit.

1-15

1IIIIilllmllmmlllllll!lilmllllmmlm~11
f'U,JITSU
11111111111111111111111111111111111111~mllmlll

MB81C68A-25
MB81C68A-30
MB81C68A-35

..

Fig. 1 - MB 81C68A BLOCK DIAGRAM

----<>Vc c

...

AS

··

j?

128 x 128
MEMORY CELL
ARRAY

·

ROW
SELECT

Ag

----OGN D

f-

f-

.. .

..,i?

.....,i?

1/0 CIRCUITS
1/0,

=

~
~

INPUT
DATA
CONTROL

COLUMN
SELECT

~

~
~ VI

~

o--::fJ-

1:D
--j

AO

IIII

POWER
DOWN
CIRCUIT

A,

~

~

11

A2

A3

A11

it
....,
L

re=

-

TRUTH TABLE
CS

WE

MODE

1/0

POWER

H
L
L

X
L
H

NOT SELECTED
WRITE
READ

HIGH-Z
DIN
DOUT

STANDBY
ACTIVE
ACTIVE

CAPACITANCE (TA = 25°C. f = 1 MHz)
Parameter

1-16

Symbol

Typ

Max

Unit

Input Capacitance (V IN = 0 V)

C IN

5

pF

es Capacitance (V cs = 0 V)

C

cs

6

pF

I/O Capacitance (V 1/0 = 0 V)

CliO

7

pF

MB81C68A-25
MB81C68A-30 FUJITSU
MB81C68A-35

1111111111111111111111111111111111111111111111111111

I111111111111111111111111111111111111111111111111111

..

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND}

Symbol

Min

Typ

Max

Unit

Supply Voltage

Vee

4.5

5.0

5.5

V

Input Low Voltage

V'L

-2.0'

0.8

V

Input High Voltage

V'H

2.2

6.0

V

Ambient Temperature

TA

0

70

°c

Parameter

Note:

* -2.0V Min. for pulse width less than 20 ns. IV'L Min = -0.5V at DC level I

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted I

Test Condition

Parameter
Input Leakage
Current

V'N = 0 V to Vee

Output Leakage
Current

V'/O = 0 V to Vee

Active lOCI Supply
Current

V'N = V'L or V'H

CS = V'H,

lOUT = 0 mA CS = V'L,

Symbol

Min

Typ

Max

Unit

ILl

-10

10

I1A

I Lo

-10

10

I1A

leel

25

50

mA

lee2

40

70

mA

or V'N~ Vee - 0.2V

ISBl

0.5

15

mA

Standby Supply Current

CS= V'H

ISB2

10

25

mA

Output Low Voltage

IOL=8mA

VOL

0.4

V

Output High Voltage

IOH = -4 mA

V OH

Operating Supply
Current

Standby Supply Current

CS =

V'L
lOUT = 0 mA, Cycle = Min

CS = Vee

- 0.2V, V'N ~ 0.2V

2.4

V

1-17

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImlllllllili

FUJITSU
1111111111111111111111111111111111111111111111111111

MB81C68A-25
MB81C68A-30
MB81C68A-35

..

AC TEST CONDITION

o V to 3.0

Input Pulse Levels:
Input Pulse Rise and Fall Times:
Timing Reference Levels:

Output Load:

V

5 ns (TransIent Time between 0.8 V and 2.2 VI
Input
Output:

1.5 V
1.5 V

Fig.2
5.0 V

~

480

n
C L = 30 pF

DOUT--.------l

CL = 5 pF for tLZ, tHZ. tow and twz

1

lIo",d'"9
Soop' 'Od1
Jig Capacitance)

CL

255

n

AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)
READ CYCLE*1

Parameter

MB 81C68A·25

MB 81C68A·30

Min

Min

MB 81C68A·35

Symbol

Unit
Max

Max

30

Max

35

ns

Read Cycle Time

tAC

Address Access Time *2

tAA

25

30

35

ns

Chip Select Access Time *3

t ACS

25

30

35

ns

Output Hold from Address Change

tOH

3

3

3

ns

Output Hold from CS

t OHC

0

0

0

ns

Chip Selection to Output in LOW_Z*4

tLZ

5

5

5

ns

Chip Deselection to Output in High·Z<4

tHZ

Power Up from CS

tpu

Power Down from CS

t pD

Note:

1-18

*1
*2
*3
*4

25

Min

13

10

0

WE is high for Read cycle.
Device is continuously selected, CS = V'L
Address valid prior to or coincident with CS transition low.
Transition is specified at the point of ±50o' mV from steady state voltage.

25

ns
ns

0

0
20

15

30

ns

MB81C68A-25
MB81C68A-30
MB81C68A-35

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

READ CYCLE TIMING DIAGRAM"'

READ CYCLE: ADDRESS CONTROLLED'2
f-------tRC--------I

ADDRESS

f----tAA----1

tOH

PREVIOUS
DATA VALID

DATA OUT

DATA VALID

READ CYCLE: CS CONTROLLED'3
f-------tRC-------j

HIGH-Z

DATA OUT ---4-~=~-r

."~-SUPPLY
CURRENT

Note:

IS8

5~

....;;.:~ _ _ _- J

ICC

", WE is high for Read cycle.
"2 Device is continuously selected, CS = V'L
"3 Address valid prior to or coincident with CS transition low.
"4 Transition is specified at the point of ±50D-mV from steady state voltage.

1-19

..

Ilm~ll~mllllllllmlllmllll~mlml~11111 MB81C68A-25
I'"UJITSU

MB81C68A-30

1IIIIIIIImlllml~mlll~~llmllllllllllllll MB81C68A-35

WRITE CYCLE*h2
Parameter
Write Cycle Time

MB 81C68A-25

MB 81C68A-30

MB 81C68A-35

Min

Min

Min

Symbol

Unit
Max

Max

twc

25

30

35

ns

Chip Selection to End of Write

tcw

20

25

30

ns

Address Valid to End of Write

tAw

20

25

30

ns

Address Setup Ti me

tAs

0

0

0

ns

Write Pulse Width

twp

20

25

30

ns

Data Setup Time

tow

13

15

15

ns

Write Recovery Time

tWR

2

2

2

ns

Data Hold Time

tOH

0

0

0

ns

Output High-Z from WE *3

twz

Output Low-Z from WE*3

tow

10
5

13

15
5

5

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE: WE CONTROLLED*1*2
I--------twc---------jl

ADDRESS

DATA IN
t WZ ' 3

--j
~

tow~
HIGH·Z

1/

DATAOUT--------------------------+V~--~~~--_i~t::::::::::
Note: *1 CS or WE must be high during address transitions.
*2 If CS goes high simultaneously with WE high, the output remains in a high impedance state.
*3 Transition is specified at the point of ±500 mV from steady state Voltage.

1-20

Max

ns
ns

MBB1C68A-25 -.~.
MB81C68A-30 FU.JITSU
MB81C68A-35 !~lm~llll!m~IIIIIII~~I!~I!~

..

WRITE CYCLE TIMING DIAGRAM

CONTROLLED- 1 *2

WRITE CYCLE: CS

r----------------twc--------------__~
ADDRESS
~------------tAw------------~

tAS

r-~--~---------tcw----------~

f------twp--_~

DATA IN
t

LZ

-3

~twZ*3

DATAOUT------------~~------~----~HI~G~H~~----------------------------

Note:

*1 CS or WE must be high during address transitions.
*2 If CS goes high simultaneously with WE high, the output remains in a high impedance state.
*3 Transition is specified at the point of ±500 mV from steady state voltage.

1-21

..

MB81C68A-25
MB81C68A-30
MB81C68A-35

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

TYPICAL CHARACTERISTICS CURVES
Fig.3 OPERATING SUPPLY CURRENT
¥s. SUPPLY VOLTAGE
(!l

Fig.4 OPERATING SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
(!l

z

2

~
a:

1.2

't:~C

TA = 25°C

WI-

~ ~
Oa:
wa:

lee2

1.1

N::>

~~

1.0

:....J

~~

2 "'0.9

~
U

.9

0.8

.9

V
4.5

/

l/

~

1.2

~ ~
oa:
wa:

1.1

~
2

1.4

~~

1.0

:'...J

gj~

2", 0.9
N
u

U

5.0
5.25
5.5
4.75
Vee. SUPPLY VOLTAGE (V)

ISB2

TA = 25'C

/.

":11-2

~ ~1.2

V

N::>

~ ~ 1.0

:....J

~~
z

C/)O.8

N
III
J!l

m

~

~

./

I SBI

leel

0.8

.9

Fig.6 STANDBY SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
Vee = 5.5V

>-

~

~ ~

wa:
N::>
:::;u
..:>:'...J

2.0

z~

Vee = 5.5V

;: !z 1.5

o

~
f:

1.8

TA = 25'C
Vee = 5.5V
V 1N = VIHiVIL_ I--

i?!z
~~

..:>-

...J...J

a1.0

1.4

t:! ~ 1.0

":<1.

:.n.
gs ~ 0.6

<1.

~ ~ 0.5

-

Fig.8 OPERATING SUPPLY CURRENT
vs. FREQUENCY

wa:

:....J

r
Vee

25
50
75
100
TA • AMBIENT TEMPERATURE ('C)

~ ~

"'w
oa:

i,....--

V

z

N

N

III

~

0

o

25
50
75
100
TA • AMBIENT TEMPERATURE ('C)

1-22

-

i--

4.75
5.0
5.25
5.5
Vee. SUPPLY VOLTAGE (V)

CS=VIH

= GNO or

5

0.6

2

J!l

VIN

Z
":1I-z

Fig.7 STANDBY SUPPL Y CURRENT
VS. AMBIENT TEMPERATURE

a:

'cs = Ve'e

10

~t

V
4.5

j

50
75
100
o
25
TA • AMBIENT TEMPERATURE ('C)

J!l

>'"o

~~
"-

.9

wa:

~

'N ::>

Fig.5 STANDBY SUPPLY CURRENT
VI. SUPPLY VOLTAGE

>-

lcC=5}V

a:

WI-

0.2
5

10

50 100

f. FREQUENCY (MHz)

MB81C68A-25 1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImllmlll~III~1
MB81C68A-30 FUJITSU
MB81C68A-35 1llllllllllllllllllllllllm~llllllllllllllllllml

..

TYPICAL CHARACTERISTICS CURVES (Cont'd)
Fig.9 "H" LEVEL OUTPUT VOL TAGE
vs. "H" LEVEL OUTPUT CURRENT
w
~ 3.6

:;
o

>

3.4

Fig. 10 "L" LEVEL OUTPUT VOLTAGE
VI. "L" LEVEL OUTPUT CURRENT
~ 0.4

........

I-

::>

0..

I-

ep·2

TA = 25'C
Vee = 5.0V

TA=25'C /
Vee = 5.0V

~

~ 0.3

I'--- r----.....

I-

::>
0..

!;

.............

...J

0.2

o

...J

W

>

W

~ 3.0

~ 0.1

;c

...J

~ a

.:i: 2.8
o

>

,j

oJ

o
2.5
5.0
1.5
10
IOH. ··H·· LEVEL OUTPUT CURRENT (mA)

10
o
5
15
20
IOL. ··L·· LEVEL OUTPUT CURRENT (mA)

Fig. 11 ACCESS TIME vs. SUPPL Y
VOLTAGE
w

:;;

f=

Fig. 12 ACCESS TIME vs. AMBIENT
TEMPERATURE
w

~ 25'C r--

TA

1.2

:;;

f=

!jl

U

~ 1.1

"-1'-....

o

w

N

:::; 1.0

a::

Vee = 4.5V

w

U

«

1.2

!jl

w

:;;

L

~

L

I

~ 0.9

~ 1.1

ow

..............

~

«

r--

:;;

a::

V

V

V

~ 0.9

!1

!1«

«
0.8
«

~.

~.

j

1-

«

4.5

1.0

4.15
5.0
5.25
5.5
Vee. SUPPLY VOLTAGE (V)

0.8
o
25
50
15
100
TA • AMBIENT TEMPERATURE ('C)

Fig. 13 ACCESS TIME vs. LOAD
CAPACITANCE
w

:;;

f=

1.4

!jl

r-

TA = 25'C
Vee - 4.5V

w

~ 1.2

ow

N

:::; 1.0

'/

./

U

V

./

«

:;;

a::

~ 0.8
II>
U

«

~0.6
j
o
100
200
300
400
CL • LOAD CAPACITANCE (pF)

1-23

-

MB81C68A-25
MB81C68A-30
il l l ~1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MB81C68A-35

1IIIIIIIIIIIIIIIIIImlllllllllllllllllllllllllllili

FUJITSU

PACKAGE DIMENSIONS
(Suffix: -Z)
20-LEAD CERAMIC (CERDIP) DUAL IN-LINE PACKAGE
(CASE No.: DIP-20C-C03)

~g~:

R.02510.641
REF

rr=t
I

+0.36

17.32_0.10' .319,.006
(S.tO±O.lSI

c.----- .950~:~~~

.30017.621TYP

_ _ _ _ _-1

(24.13~~:~~1

.050{1.27)MAX

.100t.Ol0
12.54'0.251

Dimensions in
inches (millimeters)

© FUJITSU LIMITED 1986 D20006S·4C

(Suffix: -PI
20·LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-20P-M01)

.300'.010
(7.62±O.25)

.17214.361MAX

.11813.0lMIN
.100(2.54)

TYP

I
Dimensions in
inches (millimeters)

©FUJITSU LIMITED 1986 020005S·2C

1-24

MB81C68A-25
MB81C68A-30 FUJITSU
MB81C68A-35

1111111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111111

..

PACKAGE DIMENSIONS
(Suffix: ·PSZ)
20·LEAD PLASTIC ZIGZAG·IN·LlNE PACKAGE
(CASE NO.: ZIP·20p·M01)
.112±.008
(2.85±0.2)

INDEX
'32SJ26)MAX

d
.010±.002
(0.25±0.05)

-

-

.OSO(1.27)TYP

©FUJITSU LIMITED1986

Z20001S·3C

.020±.004
(0.SO±0.10)

:;t~

.118(3.0)MIN

1_

~

l· l 00(2.S4)TYP

Dimensions in
inches (millimeters)

1-25

..

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~IIIIIIIIIIIIIIII
FUJITSU
1IIIIIIIIIImllllillmllllillmllllllllllllili

MB81C68A-25
MB81C68A-30
MB81C68A-35

(Suffix: -TV)
AeA7 VCCAa

:.~t~J-2gJ1!:
AS

ji

~-~ Ag

A3

~1

~~

A2

~~

~:

j-O,

AI

~J

~~

1'02

~ ~J

~1? A IO

AO ~J

A"

~~ 1103

CERAMIC PACKAGE
LCC
(LCC-20C-F01)

r9TioTliTi2~

CD I W'E"L04
ONO

2O.pAD CERAMIC IFRIT SEALI LEADLESS CHIP CARRIER

ICASE No.: LCC-2OC·F01'

• Shape

1-26

n' PIN NO.1 IIIIDEX:

D,men.."n,n
SubJecll"c~angewlthoul

nol'ce

,ncheslrn,II"'>llers)

MB81C69A-25
MB81C69A-30
MB81C69A-35
January 1988

Edition 2.0

4K x 4 (16,384-BIT) STATIC RANDOM ACCESS MEMORY
WITH SUPPER HIGH SPEED
The Fujitsu MB 81C69A is 4096 words x 4 bits static random access memory
fabricated with a CMOS silicon gate process. The memory utilizes asynchronous circuitry and all pins are TTL compatible and a single 5 volts power
supply is required.
A separate chip select (ts) pin simplifies multipackage systems design. It per·
mits the selection of an individual package when outputs are OR-tied.
All devices offer the advantages of low power dissipation, low cost, and high
performance.

• Organization: 4096 words x 4 bits
• Static operation: No clocks or timing strobe required
• Fast access time: tAA = 25 ns max, tAcs = 15 ns max (MB 81C69A-25)
tAA = 30 ns max, t ACS = 18 ns max (MB 81C69A-30)
tAA = 35 ns max, tACS = 20 ns max (MB 81C69A·35)
• Low power consumption: 385 mW max. (Active)
• Single +5V supply ±10% tolerance
• TTL compatible inputs and outputs
• Three-state outputs with OR-tie capability
• Chip select for simplified memory expansion
• All inputs and outputs have protection against static charge
• Standard 20-pin DIP (Suffix: -P(plastic)/Suffix: -Z(cerdip))
• Standard 20-pad LCC (Suffix: -TV)

CERAMIC PACKAGE
CERDIP
(DIP-20C-C03)

PLASTIC PACKAGE
(DIP-20P-MOl )

PIN ASSIGNMENT
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating

Symbol

Supply Voltage

Vee

Input Voltage on Any Pin
with respect to GND

V ,N

Output Volage on Any I/O Pin
with respect to GND

V OUT

Output current

lOUT

Power dissipation

Po

Temperature under Bias

TslAs

Storage Temperature

ICERAMIC
IPLASTIC

Value

Unit

A,

Vee

-0.5 to +7

V

A6

As

As

A9

A4

AtD

A3

A"

A2

1/°1

At

1/0 2

-3.5 to +7
-0.5 to +7
±20

V

mA

1.0

W

-10 to +85

°c

-65 to +150
T STG

V

AD

lio 3

cs

1/0 4

GND

WE

°c

-45 to +125

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

This device contains circuitry to protect the

inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit.

1-27

..

1~~~~II~lmm~IIIIII~lil MB81C69A-25
FUJITSU

MB81C69A-30

11111~~~mllllmlllml~llmliil~!il~1 MB81C69A-35

..

Fig. 1 - MB 81C69A BLOCK DIAGRAM

...J

A4
A5

~

A6

.J

~VC

C128x 128
MEMORY CELL
ARRAY

o
0

ROW
SELECT

A7

0

-

As
Ag

0

J.

AlO

c

-----oGN D

0

0

J
I/O CIRCUITS

I/O,

'"

~

1/03

~

1/04

CS

WE

=

~

1/02

INPUT
OATA
CONTROL

COLUMN
SELECT

~

~

YI

A,

~

if,

1 1

IIII

£

if,

A2

A"

rit

~

~

-

TRUTH TABLE
CS

WE

MODE

I/O

H
L
L

X

NOT SELECTED
WRITE
READ

HIGH·Z
D,N
DOUT

L
H

CAPACITANCE ITA = 25°C, f = 1 MHz)
Unit

C 'N

5

pF

= 0 V)

Ccs

6

pF

=0

C,iO

7

pF

Input Capacitance (V IN

CS Capacitance

(VC§

I/O Capacitance (V 1/0

1-28

Typ

Max

Symbol

Parameter

=0

V)

V)

MB81C69A-25 1~lm~mlllllllllllllmmlmllllllllllmlllll
MB81C69A-30 FUJITSU
MB81C69A-35 1llllm~mlllllllllmllllllmlllllmllllllml

..

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter

Symbol

Min

Typ

Max

5.0

5.5

V

Unit

Supply Voltage

Vcc

4.5

Input Low Voltage

V IL

-2.0'

0.8

V

Input High Voltage

V IH

2.2

6.0

V

Ambient Temperature

TA

0

70

°c

Note:

* -2.0 V Min. for pulse width less than 20 ns. (V IL Min. = -0.5 Vat DC level)

DC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)
Parameter

Test Condition

Symbol

Min

Typ

Max

Unit

Input Leakage Current

V IN = OV to Vcc

ILl

-10

10

IlA

Output Leakage Current

CS = V IH , Vila = OV to Vcc

I LO

-10

10

IlA

CS = V IL •
Active Supply Current

lOUT = 0 rnA

ICCl

25

50

rnA

Icc2

40

70

rnA

0.4

V

V IN = V IL or V IH

Operating Supply Current

CS= V IL
lOUT = 0 rnA, Cycle = Min

Output Low Voltage

IOL = 8 rnA

VOL

Output High Voltage

IOH = -4 rnA

VOH

2.4

V

1-29

1llllllllmllllllmllllmll~lllllmllllllmlll MB81C69A-25
FUJITSU

MB81C69A-30

Ilmlllll~lllllllllllllmllllllll~~~llm~l~ MB81C69A-35

..

AC TEST CONDITION

o V to 3.0 V

Input Pulse Levels
Input Pulse Rise and Fall Times:
Timing Reference Levels:
Output Load:

5 ns (Transient Time between 0.8 V and 2.2 V)
Input : 1.5 V
Output: 1 .5 V

Fig.2
5.0V

CL

DOUT----~~----~

(Including Scope and
Jig Capacitance)

= 30 pF

C L = 5 pF for tLZ. tHz, tow and twz

IlCL

255

n

AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)
READ CYCLE"1

Parameter

M881C69A-25

MB 81C69A-30

Min

Min

MB 81C69A-35

Symbol

Unit
Max

Max

Min

Max

Read Cycle Time *2

t RC

Address Access Time *3

tAA

25

30

35

ns

Chip Select Access Time *4

tACS

15

18

20

ns

Output Hold from Address Change

tOH

3

3

3

ns

Output Hold from CS

t OHC

0

0

0

ns

Chip Selection to Output in Low-Z*5

tLZ

0

0

0

ns

Chip Deselection to Output in High-Z' 5

tHZ

Note: "1
*2
*3
*4
*5

1-30

25

30

10

ns

35

13

15

WE is high for Raed cycle.
All read cycles are determined from the last address transition to the first address transition of next cycle.
Device is continuously selected, CS = V'I.:.Address valid prior to or coincident with CS transition low.
Transition is specified at the point of ±500mV from steady state Voltage with Load n in Fig. 2.

ns

MB81C69A-25
MB81C69A-30
MB81C69A-35

1111111111111111111111111111111111111111111111111111

FUJITSU
11111I1111111111111111111111111111111111111111111111

..

READ CYCLE TIMING DIAGRAM"1

READ CYCLE: ADDRESS CONTROLLED
1 - - - - - - - - tRc--"2=------------1

ADDRESS

tOH

OATA OUT

PREVIOUS
DATA VALID

DATA VALID

READ CYCLE: CS CONTROLLED'3
'2

1---------tRC---'----------I
ADDRESS

1----tAA--~-I

DATA OUT _.....:H.;.:,IG;;:,:H..;.,.Z"--_ _ _-(

Note:

DATA VALID

HIGH·Z

* 1 WE is high for Read cycle.
*2
*3
*4
*5

All read cycles are determined from the last address transition to the first address transition of next cycle.
Device is continuously selected, CS = V 1L •
Address valid prior to or coincident with CS transition low.
Transition is specified at the point of ±500 mV from steady state voltage with Lead II in Fig. 2.

1-31

..

MB81C69A-25
MB81C69A-30
~~llllmlllllmlllm~lllllmlmlmllllll MB81C69A-35

1111111111111111111111111111111111111111111111111

FWITSU

WRITE CYCLE'1'2
p.arameter
Write Cycle Time*3

MB 81C69A-25

MB 81C69A-30

MB 81 C69A-35

Min

Min

Min

Symbol

Unit
Max

Max

30

35

20

25

30

ns

20

25

30

ns

0

0

0

ns

twp

20

25

30

ns

tow

13

15

15

ns

Write Recovery Time *4

tWR

2

2

2

ns

Data Hold Time

tOH

0

Output High-Z from WE*5

twz

twc

Chip Selection to End of Write

tcw

Address Valid to End of Write

tAW

Address Setup Time

t AS

Write Pulse Width
Data Setup Time

Output Low-Z from WE*5

tow

25

Max

0

ns

0

10
5

ns

13
5

15
5

ns
ns

WRITE CYCLE TIMING DIAGRAM '1"2
WRITE CYCLE: WE CONTROLLED

f - - - - - - - - t wc· 3- - - - - - - - j

AODRESS

f------tAW-----~
;--+~---twP,--~-

DATA IN

twzi

towi.

DATAOUT __________________________~pt---_H~I~G~H-~Z--~--~~:~~:~~:~~:~~::_
Note: *1
*2
*3
*4
*5

1-32

If CS are in the READ Mode during this period, I/O pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
If CS goes high simulatneously with WE high, the output remains in high impedance state.
All write cycle are determined from last address transition to the first address transition of the next address.
tWR is defined from the end point of WRITE Mode.
Transition is specified at the point of ±500mV from steady state voltage, with Load IT in Fig. 2.

MB81C69A-25
MB81C69A-30
MB81C69A-35

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImili

FUJITSU
1111111111111111111111111111111111111111111111111

..

WRITE CYCLE TIMING DIAGRAM

WRITE CYCLE:

CS

CONTROLLED'!'2

~----------------twC~*3~----________~

ADDRESS

~------------tAw------------~

'AS

~~~~---------ICW----------~

~----IWp>-----~

IOW> _ _ _-+-_t-=O:o:H--I

DATA IN

DATA VALID

t LZ *5

C-

tWZ *5

DATAOUT ____________~~---__~~~H~I~G~H-~Z__- - - - - - - - - - - - - - - - - - - - - -____

Note: *,
*2
*3
*4
*5

If CS are in the READ Mode during this period, I/O pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
If CS goes high simultaneously with WE high, the output remains in high impedance state.
All write cycle are determined from last address transition to the first address transition of the next address.
tWR is defined from the end point of WRITE Mode.
Transition is specified at the point of ±500mV from steady state voltage with Load IT in Fig. 2.

1-33

1111111111111111111111111111111111111111111111111111

MB81C69A-25

FUJITSU MB81C69A-30
1111111111111111111111111111111111111111111111111111

..

MB81C69A-35

TYPICAL CHARACTERISTICS CURVES
Fig. 3 OPERATING SUPPLY CUR RENT
vs. SUPPLY VOLTAGE

'"z~

1.2

0:
WI-

~ ffi

N:J

:::;"
c( > 1.0
:;;...J

gs~

Z (1)0,9

§
~
~

0.8

Jl

_

~
4.5

V

>
~

~~

3.4

3 .2

1.0

~

~~ 0.9
(I)

~
~

r--..

r--..... ~

...J
W

:::;
..:

~~

0:

0

z
N
u

~
~

u:

...J

~

.:i: 2.8

~

~

~

.:.

o
2.5
5.0
7.5
10
10H. "H" LEVEL OUTPUT CURRENT (mAl

V

Fig. 8 ACCESS TIME vs. SUPPLY
VOLTAGE

Fig. 9 ACCESS TIME vs. AMBIENT
TEMPERATURE
1.2
Vee =4.5V

!Il
w

" 1.1
~
C

/

W

1.0

:;;

V

.,/

0:

'-.....

c

w

N

:i 1.0

~

..:
:;;
0:

~ 0.9

..:

~.

j

4.5

4.75
5.0
5.25
5.5
Vee. SUPPLY VOLTAGE (VI

Fig. 10 ACCESS TIME VS. LOAD
CAPACITANCE
w

TA = 2SoC
i=1.4 )-Vee - 4.5V

13

"~ 1.2
c

W
N

:i 1.0

./

/'

V

./

..:
:;;

g
:f-

~O.8

..

.. 0.6

:fo
25
50
75
100
TA • AMBIENT TEMPERATURE (OCI

r----

0.8

1)

1)

-.............

1)

0.8

~ 0.9

:f-

"~ 1.1

/

:;;

:;;

~
..:

/

TA = 25°C I--

13

o
10
15
20
10L' "L" LEVEL OUTPUT CURRENT (mAl

W

f=

5
10
50 100
f. FREQUENCY (MHzl

w
:;;
;:: 1.2
TA -25°C /
Vee = 5.0V

~ 0.1

,/

-

0.2

Fig. 7 "L" LEVEL OUTPUT VOLTAGE
vs. "L" LEVEL OUTPUT CURRENT

~

~ 3.0

0.6

(j

0.2

-

-

1.0

:;;

:'ICC1

~

>

1-34

c

N

25
50
75
100
TA. AMBIENT TEMPERATURE (OCI

5c

VIN "" V1H/VIL_

1.4

w

~ 0.3

...........

TA '" 2SoC
Vee =5.5V

0

~ 0.4
TA· 25°C
Vee - 5.0V

1.8

0:

0.8

Jl

4.75
5.0
5.25
5.5
Vee. SUPPLY VOLTAGE (VI

~

..
W

:;;...J

Fig. 6 "H" LEVEL OUTPUT VOLTAGE
vs. "H" LEVEL OUTPUT CURRENT

I!:

5

co:
wo:

N:J

Z

~
w
~ 3.6

'::;
c

'"z
Vee" 5.5V·

~ffil.1

V

Fig. 5 OPERATING SUPPLY CURRENT
vs. FREQUENCY

1.2

0:
WI-

ICC2

1.1

co:
wo:

'z~"

I~(

TA - 25°C

Fig.4 OPERATING SUPPLY CURRENT
vs. AMBIENT TEMPERATURE

o
100
200
300
400
CL • LOAD CAPACITANCE (pFI

MB81C69A-2 5 1111111~lml~lllm~~lllllmlll~lm~~~I~
MB81C69A-30 FUJITSU
MB81C69A-35 1111111111111111111111111111111111111111111111111111

..

PACKAGE DIMENSIONS
CERAMIC DIP (Suffix: -ZI
20-LEAD CERAMIC (CERDIPI DUAL IN-LINE PACKAGE
(CASE No_: DIP-20C-C031

~:~~:
17.32~~:~~)

R.02510.64)

REF

~~~_ .950~:~~~ _~~__~---j
124.13~~:~~)

Dr

.319±.006
18.10±0.15)

Lb1~-----t-----L

.OSOI1.27)MAX

.100±.010
12.S4±0.25)

© FUJITSU LIMITED 1986 D20Q06S-4C

Dimensions in
inches (millimeterS)

1-35

..

m~~~II~I~M~llmllll~III~II~11 MB81C69A-25
FUJITSU MB81C69A-30

Iml~II~liillmnilllill~ MB81C69A-35

PACKAGE DIMENSIONS
PLASTIC DIP(Suffix: -PI
20-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No_: DIP-20P-M01)

INDEX-I

I
-.l
1-------.970~:~~(24.64~~:!:)1----~.-l1
()
/""

.260±.010
(6.60±0.25)

.300±.010
(7.62±0.25)

(EJECTOR MARK)

.034~OOI2
(0.86~~·30)

.172(4.36)MAX

.118(3.0)MIN
.100(2.54)

TYP
©FUJITSU LIMITED 1986 D20005S-2C

1-36

Dimensions in
inches (millimeters)

MB81C69A-25 mlllll~lllmlllllmlllllllllllllllll~III~~1
MB81C69A-30 FUJITSU
MB81C69A-35 11~lm~III~~ml~III~~~lm~lll~i~!1

..

PACKAGE DIMENSIONS
CERAMIC LCC (Suffix: -TV)

A,

A,
A,
A,

A,
CERAMIC PACKAGE
(LCC-20C-F01)

rg 1; (iT 1-1112~
B /WE'I/04
GND

2O-PAD CERAMIC (FRIT SEAL) LEADLESS CHIP CARRIER
(CASE No.: LCC-20C-F01)

'PIN NO.1 INOEX

\

R .012(0.30)TVP
14 PLCS)

b

.050±.006
.045(1.14)TVP (1.27±0.15)
065(1 65)TVP
.150(3.81)
TVP
.
.
.100(2.54)MAX

.050±.006
(1.27±0.15)
.045(1.14)
TVP

.195(4.95)
TVP

Dimension in

* Shape of PIN NO.1 INDEX: Subject to change without notice.

inches (inillimeters)

©FUJITSU LIMITE01987 C20003S·1C

1-37

High-speed CMOS SRAMs

..

1-38

Static RAM Data Book

1111111111111111111111111111111111111111111111

1111111

FUJITSU

CMOS 65,536-BIT
STATIC RANDOM
ACCESS MEMORY

MB81C71A-25
MB81C71A-35

11111111111111111111111111111111111111111111111111111111111111111

February 1988
Edition 2.0

65,536 WORDS X 1 BIT HIGH SPEED
CMOS STATIC RANDOM ACCESS MEMORY

D

The Fujitsu MB 81C71A is 65,536 words x 1 bit static random access memory
fabricated with a CMOS technology.
It uses fully static circuitry throughout and therefore requires no clocks or
refreshing to operate.
The MB 81C71A is designed for memory applications where high performance,
low cost, large bit storage and simple interfacing are required.
MB 81C71A is compatible with TTL logic families in all respects; input, output
and a single +5 V supply.
•

PLASTIC PACKAGE
DIP·22P·M04

Organization: 65,536 words x 1 bit

• Static operation: No clocks or refresh required
•

Fast access time: tAA = tACS = 25 ns (MB 81C71A·25)
tAA = t ACS = 35 ns (MB 81C71A·35)

•

Single +5 V supply ±10% tolerance

•

Separate data input and output

• TTL compatible inputs and output

PLASTIC PACKAGE
LCC-24P-M02

• Three·state output with OR·tie capability
• Chip select for simplified memory expansion, automatic power down
•

All inputs and output have protection against static charge

PIN ASSIGNMENT

• Standard 22·pin DIP (300 mil) (Suffix: P)
Vee

• Standard 22·pad LCC (Suffix: CV)
• Standard 24'pin SOJ (300 mil) : (Suffix: PJ)
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Symbol

Value

Unit

Supply Voltage

Vcc

-0.5 to +7

V

A,

Input Voltage on any pin
with respect to G ND

V ,N

-3.5 to +7

V

'-____rcs

Output Voltage on any pin
with respect to GND

VOUT

-0.5 to +7

V

Output Current

lOUT

±50

mA

Power Dissipation

PD

1.0

W

-10to+85

°c

Rating

Temperature Under Bias
Storage
Temperature

D,.

TB1AS

Ceramic

-65 to +150

°c

TSTG
Plastic

-45 to +125

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

This device contains circuitry to protect the
inputs against damage due to high static volt-

ages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit.

1-39

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

MB81C71A-25
MB81C71 A-35

..

Fig. 1- MB 81C71A BLOCK DIAGRAM

AO-------------c~====~

Al--------~~========~

----vee

Ag ---------I~=========1 ROW
- - - - SE LECT

CELL
ARRAY

-GND

128 ROWS
512 COLUMNS

•

A12-------~~=====1
A13--------c:~========1
A14--------------{~=====1

D, N - - - - - - - - I

t-----DOUT

COLUMN 110 CIRCUITS
INPUT
DATA
CONT.

COLUMN SELECT

TRUTH TABLE

CAPACITANCE (TA

MODE

OUTPUT

POWER

CS

WE

H

X

NOT SELECTED

HIGH-Z

STANDBY

L

L

WRITE

HIGH-Z

ACTIVE

L

H

READ

DOUT

ACTIVE

= 25°C,f= 1 MHz)
Value

Parameter

Unit

Symbol
Typ

aVI
a VI
Output Capacitance (V OUT = a VI
1-40

Max

Input Capacitance (V,N =

C'N

7

pF

CS Capacitance (V cs =

C cs

7

pF

C OUT

7

pF

MB81C71A-25
MB81C71A-35

Ilmlllllm~~mml~lm~mmlmlll~~~1
FUJITSU
1111111111111111111111111111111111111111111111111111

..

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Value
Parameter

Symbol

Unit
Min

Typ

Max

5.0

5.5

V
V

Supply Voltage

Vee

4.5

Input Low Voltage

V IL

-2.0·

0.8

Input High Voltage

V IH

2.2

6.0

V

Ambient Temperature

TA

0

70

°c

• -2.0 V Min, for pulse width less than 20 ns. (VIL Min = -0.5 V at DC Level)

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Value
Parameter

Test Condition

Symbol

Unit
Min

Typ

Max

Input Leakage Current

VIN = 0 V to Vee
Vee = Max.

ILl

-10

10

p.A

Output Leakage Current

CS= V IH ,
VOUT = 0 V to 4.5 V
Vee = Max.

I LO

-10

10

p.A

Operating Supply Current

CS = V IL , Vee = Max.
DOUT = Open,
Cycle = Min.

lee

80

mA

Standby Current

Vee = Min. to Max.
CS~ Vee -0.2 V
V IN ~0.2 Vor
VIN ~ Vee -0.2 V

ISB!

10

mA

Standby Current

Vee = Min. to Max.
CS= V IH

ISB2

20

rnA

Output Low Voltage

IOL = 16 rnA

VOL

0.45

Output High Voltage

IOH = -4 rnA

V OH

Peak Power on Current

Vee = 0 V to Vee Min.
CS = Lower of Vee or
V IH Min.

Ipo

V
V

2.4

30

mA

1-41

1111111111111111111111111111~lllllllllllllllllmll
FUJITSU

MB81C71A-25

11111111111111111111111111111~lllllmlllllllllllll MB81C71A-35

..

Fig. 2 - AC TEST CONDITIONS
• Input Pulse Levels:
• Input Pulse Rise And Fall Times:
• Timing Measurement Reference Levels:

0.6 V to 2.4 V
5 ns
Input: 1.5 V
Output: 1.5 V

• 0 utput Load:
5.0 V

;.
480

n

DOUT-----,r-----~

(Including Scope and
Jig Capacitance)

I1

CL

Load I: CL =30 pF
Load IT: CL = 5 pF for 'LZ. 'HZ. 'ow and 'wz

$,255n
~

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE*l
Parameter
Read Cycle Time *2

MB 81C71A·25

MB 81C71A·35

Min

Min

Symbol
tRC

Unit
25

Address Access Time *3
Chip Select Access Time*4*5
Output Hold from Address Change

tOH

5

Chip Selection to Output in Low·Z· 6 *7

35

ns

tAA

35

ns

tACS

25

35

ns

tLZ

5

tHZ

0

Chip Selection to Power Up Time

tpu

0

Chip Deselction to Power Down time

tpD

1-42

Max

25

Chip Deselection to Output in High·Z*6'7

Note: * 1
'2
*3
*4
*5
*6
*7

Max

ns

5

ns

5
10

0

15

ns

0
20

ns

30

WE is high for Read cycle.
All Read cycles are determined from the last address transition to the first address transition of next cycle.
Device is continuously selected. CS = V IL.
Address valid prior to or coincident with CS transition low.
Chip deselection for a finite time is less than t RC prior to selection.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is measured with specified loading Load n in Fig. 2.

ns

1lllllllllllllmlmlllmlllllmlll~mlmlllll
MB81C71A-25 FUJITSU
MB81C71 A-35 1111~lllllllmlllllllllllll~~mlllllllllllilll

..

READ CYCLE TIMING DIAGRAMo 1 °2
READ CYCLE: ADDRESS CONTROLLEDo3
r.-------------tRC--------------~

ADDRESS

1---------tAA------J

DATA OUT

PREVIOUS DATA
VALID

DATA VALID

READ CYCLE: CS CONTROLLEDo405
1--------------tRC--------------~

1--------tACS---------I

DATA OUT _ _~r.._;.H;.;.IG;;.H;.;.-;;.Z--<

HIGH-Z
DATA VALID

ICC
158

~Undofinad

Note: * 1
*2
*3
*4
*5
*6
*7

&;I

Don't Car.

WE is high for Read cycle.
All Read cycles are determined from the last address transition to the first address transition of next cycle.
Device is continuously selected, CS = V IL'
Address valid prior to or coincident with CS transition low.
Chip deselection for a finite time is less than tRC prior to selection.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is measured with specified loading Load II in Fig. 2.

1-43

..

1IIIIIIIIm~IIII~II~~I~~~~~~~~lmll
FUJITSU MB81C71A-25
111111111111111111~11~IIIOOII~IIIIII!lllm MB81C71A-35

WRITE CYCLE*h2
Parameter

MB 81C71A-25

MB 81C71A-35

Min

Min

Symbol

Unit
Max

Max

Write Cycle Time*3

twc

25

35

ns

Chip Selection to End of Write

tcw

20

30

ns

Address Valid to End of Write

tAW

20

30

ns

Address Setup Time

tASl

0

0

ns

Address Setup Time

tAs2

0

0

ns

Write Pulse Width

twp

20

30

ns

Data Valid to End of Write

tow

15

20

ns

tWR

2

2

ns

Write Recovery Time
Data Hold Time

tOH

2

Write Enable to Output in High-Z*4*5

twz

0

Output Active from End of Write*4*5

tow

0

2
10

0

ns
15

0

WRITE CYCLE TIMING DIAGRAM' 1 "2
WRITE CYCLE: WE CONTROLLED
r-----------------twC"~3~------------~
ADDRESS

~::~I~

___________________________________________________J

tOH

tow,----+~--o-l

DATA VALID

DATA IN

DATA OUT

~ Undefined
Note: *1
*2
*3
*4
*5

1-44

CS or WE must be high during address transitions.
If CS goes high simultaneously with WE high, the output remains in high impedance state.
All Write cycles are determined from the last address transition to the first address transition of next cycle.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is measured with specified Load II in Fig. 2.

ns
ns

1111111111111111111111111111111111111111111111111111

MBB1C71A-25
MBB1C71A-35

FUJITSU
1111111111111111111111111111111111111111111111111111

..

WRITE CYCLE TIMING DIAGRAM "'2
WR ITE CYCLE:

CS CONTROLLED '3
i----------------twc-------------<-j

ADDRESS
tAS2

~---+

__--------tcw--------__

~

1---------tAw---------~+-t:-W-R-J

o-----t wp ------1

f-1
..

--------------~

DATA IN

DATA VALID

HIGH-Z

DATAOUT--_

~

Note: *1
*2
*3
*4
*5

Undefined

o

Don't Care

CS or WE must be high during address transitions_
If CS goes high simultaneously with WE high, the output remains in high impedance state_
All Write cycles are determined from the last address transition to the first address transition of next cycle_
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is measured with specified Load II in Fig. 2.

1-45

..

1~~~~lml~~II~II~IIIIIII~i~llllmm
FUJITSU

MB81C71A-25

m~~~M~~mll~~I~~~OO~~OOOOID MB81C71 A-35

TYPICAL CHARACTERISTICS CURVES
Fig. 3 - OPERATING SUPPLY CURRENT
VS. SUPPLY VOLTAGE

Fig. 4 - OPERATING SUPPLY CURRENT
vs. AMBIENT TEMPERATURE

TA = 25"C

"zf=

;::1wz

o..W
oa:
Oa:
w::::l
NU

1.2

Cycle min.

1.1
1.0

:J~ 0.9
«0..
:20..
a:::::l
0'" 0.8

"zf=

./

/

1.2

«I- 1.1

V

~~

Oa:
w::::l
NU

1.0

::i:J
«0.

/'

0.9

:20..

a:::::l

0'" 0.8
z

.:;

.:;

.2

.2

o 25 50 75 100
T A , AMBIENT TEMPERATURE (oC)

4.5

5.0
5.5
Vee. SUPPLY VOLTAGE (V)

Fig. 5 - STANDBY SUPPLY CURRENT
VS. SUPPLY VOLTAGE
>-

TA

CD

= 25°C

«

1.2
1.1

«u 1.0

.,

0.9

'"''''
.!!J
0.8

>-

~

/

Vee = 5.5V

CD

o

~s82

lnl-

:2>a:-,
00..
zo..
.::::l

Fig. 6 - STANDBY SUPPLY CURRENT
VS. AMBIENT TEMPERATURE

1581

0

Oz
wW
Na:
-a:
-'::::l

--

!liz

z

z

Vee = 5.5V
Cycle min.

z
«

1.2

fil iii

1.1

lnl-

V

~~

;t

a

~~

1.0

~ 8::

0.9

J!'

0.8

.::::l
.,'"''''

~

~

1582 -

f:::::T

-

1581

1

;;;
.!!J

o 25 50 75 100
T A , AMBIENT TEMPERATURE (oC)

5.5
4.5
5.0
Vee. SUPPLY VOLTAGE (V)

Fig. 7 -

"zf=

;::1wz
o..W
oa:
oa:
w::::l
NU

1.8 -

.:;

TA = 25°C
Vee = 5.5V
VIN = VIHiVlL

1.4
1.0

::i~ 0.6
«0..
:20..

a:::::l
0'"
z

OPERATING SUPPLY CURRENT
VS. FREQUENCY

0.2

-

/

.2

5 10

50100

t, FREQUENCY (MHz)

1-46

1111111111111111111111111111111111111111111111111111

MB81C71A-25
MB81C71 A-35

FUJITSU
1111111111111111111111111111111111111111111111111111

..

TYPICAL CHARACTERISTICS CURVES (Cont'd)
Fig. 9 - "L" LEVEL OUTPUT VOLTAGE
vs. "L" LEVEL OUTPUT CURRENT

Fig. 8 - "H" LEVEL OUTPUT VOLTAGE
vs. "H" LEVEL OUTPUT CURRENT
TA = 25°C
Vee = 5.0V

4.0

!;

6;;

!;

3.8

a.
f-

3.6

'-....1'-.,

...J;;:;

~...Jf-~

: <3
r' >

.......

3.4

TA = 25°C
Vee = 5.0V

0.4
0.3

a.
f:::J0>
...J;;:;
wt:J

i'--

G; ~

.......

...J...J

,

0.2

i

V

0

a

:' >

3.2

V

O. 1

..J

.J

o

2.5

5.0

7.5

.J

10

o

IOH. "H" LEVEL OUTPUT CURRENT (rnA)

TA = 25°C

w
:J w

1. 1

~ ~ 1.0

Vee = 4.5V

Cl

l"- i'--..

/

1.1

w

N

.............

~ m0.9
~~

:J w
q::>: 1.0
:>:-

V

a:f000

.............

zoo
,w

0.9

.,0

/" '"

uo

:J.q:

0.8

: 1.0
:>:-

V

V

a:f-

~,w
~

0.9

.,0

uo

:J. q:

0.8

-- .. ~"

U

°c

-45 to +125

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATI NGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximulTi rated voltages to this high impedance

circuit.

1-51

11111111~I~Bnlmm
FUJITSU

MB81C74-25

~~~!n~llllllnil~IMil~i MB81C74-35

..

Fig. 1 - MB 81C74 BLOCK DIAGRAM

...

AO

~

---0

-

~

L
~

128x128x4
MEMORY CELL
ARRAY

•

ROW
SELECT

•
•

vee

- - - 0 GND

f-

.;t

• • •
COLUMN
I/O CIRCUITS

I/O,

f=

~
......

~

.....

1/03

INPUT
DATA
CONTROL

COLUMN
SELECT

~

~

jg
"1

r r

-it

~ ~~ ~ ~ ~

A6 A7

As As

~

6

A,o A11 A'2

11II

rr-

TRUTH TABLE
POWER
DOWN
CIRCUIT

CAPACITANCE

CS

WE

MODE

1/0

POWER

H

X

NOT SELECTED
WRITE
READ

HIGH-Z
DIN
DOUT

STANDBY
ACTIVE
ACTIVE

L

L

L

H

(TA· 25°C. f = 1 MHz)

Parameter

1-52

~

~

I

Symbol

Min

Typ

Max

Unit

I/O Capacitance (VIIO = OV)

CliO

7

pF

Input Capacitance (V IN = OV)

C IN

7

pF

1111111111111111111111111111111111111111111111111111

MB81C74-25
MB81C7 4-35

FUJITSU
1111111111111111111111111111111111111111111111111111

..

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter

Symbol

Min

Typ

Max

Unit

Vcc

4.5

5.0

5.5

V

Input Low Voltage

V,L

_2.0'1

0.8

V

Input High Voltage

V,H

2.2

6.0

V

TA

0

70

°c

Supply Voltage

Ambient Temperature
'1

-2.0 V Min. for pulse width less than 20 ns. (V ,L min. = -0.5 V at DC level)

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Symbol

Max

Unit

ISB1

10

rnA

ISB2

20

rnA

Active Supply Current

Icc1

60

rnA

Operating Supply Current

Icc2

80

rnA

Cycle = Min., lOUT = 0 rnA

Input Leakage Current

ILl

-10

10

IJA

V ,N = OV to Vcc

Output Leakage Current

I LiIO

-10

10

IJA

CS = V ,H , V ,/O

Output High Voltage

V OH

2.4

V

IOH = -4 rnA

Output Low Voltage

VOL

0.4

V

IOL =8mA

-Standby Supply Current

Min

.-- -----._-

Test Conditions

CS ~ Vcc-O.2V, V ,N ~0.2V
or V ,N ~ Vcc-0.2V
CS = V ,H
lOUT = 0 rnA. CS = V,L.
V ,N = V ,L or V ,H

I

= OV to Vce

Note: All voltages are referenced to GND

Fig. 2 - AC TEST CONDITIONS
•

Output Load
+5V

•

Input Pulse Levels:

0 V to 3.0 V

•

Input Pulse Rise & Fall Times:

5 ns (Transient between 0.8 V and 2.2 V)

•

Timing Reference Levels:

Input:
Output:

1.5 V
1.5 V

R1

*

Including Scope and Jig Capacitance

R2

CL

Load I

480,n

255,n

30pF

Load II

480,n

255,n

5 pF

R1

Parameters Measured
except tCLZ' tCHZ, tWLZ' and t WHZ
tCLZ, tCHZ, 1WLZ' tWHZ

1-53

..

1111111~mlllll~~mlll~llmlllllmllllmll

m.;mim;I~1 =::~~~t~g
AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)
READ CYCLE' 1
MB 81C74·35

MB 81C74·25
Symbol

Parameter

Min

Max

25

Min

Max

35

Unit
ns

Read Cycle Time

tRC

Address Access Time '2

tAA

25

35

ns

CS Access Time '3

t AcS

25

35

ns

Output Hold from Address Change

tOH

5

5

ns

Output Hold from CS

t OHC

3

3

ns

Chip Selection to Output Low·Z'4'5

tCLZ

5

5

ns

Chip Deselection to Output High.z'4 '5

tCHZ

Power Up from CS

tpu

Power Down from CS

tpD

10

15

20

30

READ CYCLE TIMING DIAGRAM"
READ CYCLE 1'2

ADDRESS

-€
___=;-~.-_-=-=_~_tOH=I_
=-tAA

DOUT

PREVIOUS DATA VALID

~

DATA VALID

.

~

READ CYCLE: CS CONTROLLED'3
~------------tRC------------~

DOUT

SUPPLY
CURRENT

f--"~---ICc--,--~-tPo~
Undefined:

Note:
'1
*2
*3
*4
*5

1-54

HIGH-Z

DATA VALID

IlO!I

Don't Care:

WE is high for Read cycle.
Device is continuously selected, CS = V 1L .
Address. valid prior to or coincident with CS transition low.
Transition·is measured at the point of ±500 mV from steady state voltage.
This Parameter is specified with Load II in Fig. 2.

III

ns
ns

0

0

ns

MB81C74-25
MB81C74-35

mmmlmllllllll~~mllml~mlmllllllill
FUJITSU
1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImili

..

WRITE CYCLE"'

MB 81C74-25

MB 81C74-35

Symbol

Parameter

Unit
Min

Max

Min

Max

Write Cycle Time '2

twe

25

35

ns

Address Valid to End of Write

tAW

20

30

ns

Chip Select to End of Write

tew

20

30

ns

Data Valid to End of Write

tow

13

17

ns

Data Hold Time

tOH

2

2

ns

Write Pulse Width

twp

20

30

ns

Address Setup Time

tAS

0

0

ns

Write Recovery Time

tWR

2

2

ns

Output High-Z from WE'3 '4

tWHz

Output Low-Z from WE'3'4

tWLZ

10
10

0

0

15

ns

15

ns

WRITE CYCLE TIMING DIAGRAM

WRITE CYCLE I: WE CONTROLLED"'2
twe
ADDRESS
tWR-

tew

tAW
twp

i---tAS

tow
HIGH-Z

tOHHIGH-Z

DATA VALID
I----tWHZ

!--tWLz

DOUT
Undefined:

Note:
*1
*2
*3
*4

a

If CS goes high simultaneously with WE high, the output remains in high impedance state.
All write cycle are determined from last address transition to the first address transition of the next address.
Transition is measured at the point of ±500 mV from steady state voltage.
This parameter is specified with Load n in Fig. 2.

1-55

11~1~~Hlml~IIII~111
FUJITSU

i!III!UiHIIIIIII~1

..

MB81C74-25
MB81C74-35

WRITE CYCLE II: CS CONTROLLEOo,o2

ADDRESS

HIGH·Z

Don't Car.: •

Note:
'1 If CS goes high simultaneously with Wi: high, the output remains in high impedance state.
*2 All write cycle are determined from last address transition to the first address transition of the next address.

1-56

1IIIIIIIIImllllllllllllllllillmlmlillmmm

MB81C74-25
MB81C74-35

FUJITSU
1111111111111111111111111111111111111111111111111111

..

TYPICAL CHARACTERISTICS CURVES
Fig. 3 - OPERATING SUPPLY CURRENT
VS. SUPPL Y VOLTAGE

Cl

z

TA

i=

:;;

1.0

0:-'

~~

0.9

.2

0.8

",'"
u

ou

V

V

/

Fig. 4 - OPERATING SUPPLY CURRENT
VS. AMBIENT TEMPERATURE

0:

~ee2

Vee

w

1.2

@~

1.1

~~

NO:

:::;:;)

~ ~

1.0

~~

0.9

.2

0.8

o 25 50 75 100
TA • AMBIENT TEMPERATURE (OC)
Fig. 6 - STANDBY SUPPLY CURRENT
vs. AMBIENT TEMPERATURE

1.2

~~82

1.1

~~

a

~~

~ &:

1.0
0.9

.:;)

N",

IC

.1!'

0.8

>0

/

/

TA = 25°C

IC

IS81

1:;; ...

~

le~

o

.2

TA = 25°C

fil a'i

~ ~e2

",'"
u

Fig. 5 - STANDBY SUPPLY CURRENT
VS. SUPPLY VOLTAGE

~

~

0:-'

4.5
5.0
5.5
Vee. SUPPLY VOLTAGE (V)

>IC
o

= 5.5V

z

1.2

"'oz...

1.1

...
-

1.0

~

0-'

zl>.
0.9
I>.

~

~82- f---

.:;)

~'"

.!f}

.......
IS81

0.8

iii

III

.!f}

.!f}

o

4.5
5.0
5.5
Vee. SUPPLY VOLTAGE (V)

25

50

75

100

TA • AMBIENT TEMPERATURE (oC)

Fig. 7 - OPERATING SUPPLY CURRENT
VS. FREQUENCY
Cl

z

i=

1.8

I----

TA = 25°C
Vee = 5.5V
V'N

= V'HiV'L

.

1.0

/

0.6

0:;)

z'" 0.2

'u"

.2
5

10

50 100

f. FREOUENCY (MHz)

1-57

..

1111~~lllmlllllllll~OOIIIIIIIIIIIIIIII~m~

Ilmm~~liill~1 =::l~~::~g
TYPICAL CHARACTERISTICS CURVES (Cont'd)
Fig. 9 - "L" LEVEL OUTPUT VOLTAGE
VI. "L" LEVEL OUTPUT CURRENT

Fig. 8 - "H" LEVEL OUTPUT VOLTAGE
VI. "H" LEVEL OUTPUT CURRENT

3.8

TA = 25"c
Vee = 5.0V

TA = 25'C
vee = 5.0V
0.4

I-

::;)

1=

3.6

::;)-

0>

I:J
I-

,~

.. ;:;; 3.4

.......

wc!)

1;;<

.. ~ 3.2

f~

0.3

Q.

::;)-

o~

r--....~ .......

0.2

"w
wc!)

....
:'>
1;;~

0.1

1/

: 0

3.0

.::.
~

o

2.5

5.0

7.5

10

IOH. "H" LEVEL OUTPUT CURRENT (mA)

Fig. 10 - ACCESS TIME
VOLTAGE

VS.

SUPPLY

0

Vee =4.5V
1.2

1.1

"-

N

:::i w

<::.

1.0

0",
Z

13

0.9

~g
$<

0.8

" --

0

w

./

1.1

N

:::i w

<::.
::.a: I-

""'-

1.0

0",
Z'"
.w

0.9

$0<

0.8

V

1/

!j8

.(

.(

$

:J.
4.5

5.0

5.5

Vee. SUPPLY VOLTAGE (V)

o 25 50 75 100
TA.AMBIENTTEMPERATURE ('C)

Fig. 12 - ACCESS TIME ¥s. LOAD
CAPACITANCE

1.2
0

w

TA = 25'C
vee = 4.5V

1.1

N

:::i w
1.0

<::.
::.a: I-

...V

I-""

V

0",

Z'" 0.9

u..~

ou
$<

0.8

.(

$0

1-58

V

o 5 10 15 20
IOL. "L" LEVEL OUTPUT CURRENT (mA)

TA = 25'C

::.a: I-

"'"

Fig. 11 - ACCESS TIME VI. AMBIENT
TEMPERATURE

1.2

S

",

V

o 50 100 150 200
CL • LOAD CAPACITANCE (pF)

1111111111111111111111111111111111111111111111111111

MB81C74-25
MB81C7 4-35

FUJITSU
1111111111111111111111111111111111111111111111111111

..

PACKAGE DIMENSIONS
(Suffice:

-PI
22-LEADS PLASTIC DUAL IN-LINE PACKAGE
(CASE No_: DIP-22P-M04)

n

~

(EJECTOR MARKI

---1
~

I

.100(2.541

.300±.010
(7.62±0.251

.260±.010
(6.6±0.251

.010±.002
(0.25±0.051

I

TYP
Dimensions in
inches (millimeters)
©FUJITSU LIMITED 1986 D22008S-3C

1-59

..

1IIImllll~llllllllllmlllllllllmllllllllll~11
FUJITSU MB81C74-25
11111111111111111111111111~llllllllllllllllllmlll MB81C74-35

PACKAGE DIMENSIONS
(Suffice: -CV)
22-PAD CERAMIC (METAL SEAL) LEADLESS CHIP CARRIER
(CASE No.: LCC-22C-A01)

'PIN NO.1 INDEX

/
6

R.012(0.30)TYP
(4 PLCS)
.085(2.1

.495±.010
(12.57.0.25)

R.008(0.20)TYP
(22PLCS)

.045(!:.1~

.065(1.65)
TYP

.050 •. 006
(1.27.0.15)

TYP
.083(2.11)

MAX
*Share of PIN NO.1 INDEX: Subject to changed without notice.

© FUJITSU LIMITED 1987 C22002S·2C

1-60

Dimensions in
inches (millimeters)

MB81C75-25
MB81C75-35
February 1988
Edition 2.0

16K x 4 BIT (6S,S36-BIT) HIGH SPEED STATIC RANDOM
ACCESS MEMORY WITH AUTOMATIC POWER DOWN
The Fujitsu MB 81C75 is
memory fabricated with a
.asynchronous circuitry and
period of time. All pins are
is required.

a 16,384-words by 4-bits static random access
CMOS silicongate process. The memory utilizes
may be maintained in any state for an indefinite
TTL compatible, and a single 5 volts power supply

The MB 81C75 is ideally suited for use in microprocessor systems and other
applications where fast access time and ease of use are required. All devices
offer the advantages of low power dissipation, low cost and high performance.
• Organization: 16,384 words x 4 bits
Fast access time: tAA = t ACS = 25 ns max. (MB 81 C75-25)
tOE = 10 ns max.
tAA = t ACS = 35 ns max. (M8 81C75-35)
tOE = 15 ns max.

PLASTIC PACKAGE
DIP-24P-M03

• Completely static operation: No clock required
• TTL compatible inputs/outputs
• Three-state output

PLASTIC PACKAGE
LCC-24P-M02

• Common data input/output
• Single +5 V power supply ±10% tolerance
•

Low power standby: 440 mW max. (Active)
55 mW max. (Standby, CMOS level)
110 mW max. (Standby, TTL level)

PIN ASSIGNMENT

• Standard 24-pin DIP (300 mil): Suffix: P
• Standard 28-pad LCC
: Suffix: CV
• Standard 24-pin SOJ (300 mil): Suffix: PJ
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating

Symbol

Value

Unit

Vce

-0.5 to +7.0

V

Input Voltage

Y'N

-3.5 to +7.0

V

Output Voltage

VOUT

-0.5 to +7.0

V

Output Current

lOUT

±20

mA

Supply Voltage

Power Dissipation

Po

Temperature Under Bias

TBIAS

1.0

W

-10 to +85

°c

V"
A,
A"
A,
A,

A"
An

A,

A"
1104
I{03

1/02

Storage
Temperature
Range

Ceramic

-65 to +150
TSTG

Plastic

1/01

°c

We

-45 to +125

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

This device contains circuitry to protect the
inputs against damage due to"high static'voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit.
----------------------~

1-61

..

Mllmi~~~~II~~i~1

m.i:•• :::~~~:~~

..

Fig. 1 - MB 81C75 BLOCj< DIAGRAM

to.

AO

-----avec
f-

.

ROW
SELECT

----oGND

12Bx 12Bx4
MEMORY CELL
ARRAY

rto.

AS

L • • • J
to.

COLUMN

1/0 CIRCUITS
1/0 1

f::::

~

......

1/0 2

~

COLUMN
SELECT

INPUT
DATA
CONTROL

~

~UliJ~~~

~

I

~FD-

:f~
Y

POWER
DOWN
CIRCUIT

.t

AG

IIII

!? ?
A7 As

?

Ag Al0AllA12

~
~

~

rf--

TRUTH TABLE
CS

WE

OE

1/0

POWER

H

X

X

NOT SELECTED

MODE

HIGH Z

STANDBY

L

H

H

OUTPUT DESABLE

HIGH-Z

ACTIVE

L

H

L

READ

DOUT

ACTIVE

L

L

X

WRITE

DIN

ACTIVE

CAPACITANCE (TA =25°C, f =1 MHz)
Value
Parameter

Symbol

Unit
Min

110 Capacitance (V I/O

= 0 V)

Input Capacitance (V IN

1-62

= 0 V)

Typ

Max

CI/O

7

pF

C IN

7

pF

111111111111111111111111~lllllllllllllllllllmllll

~::l~~:~~ IIIIII~I.III

..

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Value

Symbol

Parameter

Unit

Min

Typ

Max

Vcc

4.5

5.0

5.5

V

Input Low Voltage

V 1L

-2.0'

0.8

V

Input High Voltage

V 1H

2.2

6.0

V

Ambient Temperature

TA

0

70

°c

Supply Voltage

• -2.0 V Min, for pulse width less than 20 ns. (V 1L Min = -0.5 V at DC Level)

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Test Conditions

Value

Symbol
Min

Max

Unit

CS ~ Vcc - 0.2 V, V 1N ~ 0.2 V
or V IN ~ V cc - 0.2 V

ISBl

10

CS= V IH

ISB2

20

Active Supply Current

CS = V IL , V IN = V IL or
VIH , lOUT = 0 mA

ICCl

60

Operating Supply Current

Cycle = Min., lOUT = 0 mA

Icc2

80

Input Leakage Current

V IN - 0 V to Vcc

III

-10

10

p.A

10

p.A

0.4

V

Standby Supply Current

mA

Output Leakage Current

CS = V IH , VI/O = 0 V to Vcc

I Li/o

-10

Output High Voltage

IOH = -4 mA

VOH

2.4

Output Low Voltage

IOL =8mA

VOL

mA

V

Note: All voltages are referenced to GND
Fig. 2 - AC TEST CONDITIONS

•

•
•
•

Output Load

Input Pulse Levels:
Input Pulse Rise & Fall Times
Timing Reference Levels

0 V to 3.0 V
5 ns (Transient between 0.8 V and 2.2 V)
Input: 1.5 V

Output: 1.5 V
+5V

Rl
DOUT
(110)

r

cL.l

R2
Rl

.,7"

.. Including Scope and Jig Capacitance

R2

CL

Load I

480.0

255.0

30pF

Load II

480.0

255.0

5pF

Parameters Maasu red
except tCLZ, tCHZ' tWLZ, tWHZ.
tOLZ and tOHZ

tCLZ. tCHZ, tWLZ. tWHZ. tOLZ

and tOHZ

1-63

mlml~~m~~mm~~~llllmllmmmm
FUJITSU

MB81C75-25

Illm~llllmllllmlll~llllml~~11111111111 M881C75-35

..

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.!
READ CYCLE*'
Parameter

MB 81C75-35

MB B1C75-25

Symbol

Min

Max

25

Min

Max

35

Unit

Read Cycle Time

tRC

Address Access Time*2

tAA

25

35

ns

CS Access Time *3

tACS
tOE

25

35

ns

OE Access Time *3

10

15

ns

Output Hold from Address Change

tOH

5

5

ns

Output Hold from CS

to HC

3

3

ns

CS to output Low-Z*4*5

tCLZ

5

5

ns

OE to Output in Low-Z*4 *5

tOLZ

0

0

ns

ns

CS to Output High-z· 4 *5

tCHZ

10

15

ns

OE to Output High-Z*4*5

tOHZ

10

15

ns

Power Up from CS

t pu

Power Dwown from CS

tpD

0

0
20

ns
30

READ CYCLE "tIMING DIAGRAM"
READ CYCLE 1'2

~ f-:~ =~=~=~=~=~=~=~=-t_A=_A=A:=D=~D=~R=~E=_:~R_':-C-I;~.:_L~_ID~_-=~- =~- =~- =~--=~-·~E

ADDRESS

____

DOUT

J(.

PREVIOUS DATA VALID

____tO_H=:j,.--DATA VALID
--.JIl-

READ CYCLE II '3

""'"

DOUT

~~_~-_-___-_-_-_-___-_-_-A~D~D~R~E_~R_SC_V~A~L~ID~~~~~~~~~~~~~_________________

HIGH-Z

HIGH-Z

=,r-

SUPPLY - - - - - -tPu --1 50-%-------------CURRENT
______________
ICC
~ Undefined
Note: *1
*2
*3
*4
*5

1-64

o

Don"teare

WE is high for Read cycle.
Device is continuously selected, CS=V'L' OE=V'L'
Address valid prior to or coincident with CS transition low.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

ns

~~~~lm~~III~~lm~lm~~~~m~~

MB81C75-25 FUJITSU
MB81C75-35 ml~~~~~~~~~lml~mlm~m~~~~~1

..

WRITE CYCLE*1
Parameter

Symbol

MB 81C75·25

Unit
Min

Write Cycle Time'2

MB 81C75·35

Max

Min

Max

twc

25

35

ns

Address Valid to End of Write

tAW

20

30

ns

Chip Select to End of Write End of Write

tcw

20

30

ns

Data Valid to End of Write

tow

13

17

ns

Data Hold Time

tOH

2

2

ns

Write Pulse Width

twp

20

30

ns

Address Setup Time

t AS

0

0

ns

Write Recovery Time

tWR

2

2

ns

Output High·Z from WE*3*4

tWHZ

Output Low·Z from WE*3*4

tWLZ

10
0

20

0

15

ns

30

ns

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE I: WE CONTROLLED· 1 •2

ADDRESS

HIGH·Z

HIGH·Z

HIGH·Z

~ Undefined

l1li Don't Car.

Note: '1 If CS goes high simultaneously with WE high, the output remains in high impedance state.
'2 All write cycle are determined from last address transition to the first address transition of the
next address.
'3 Transition is measured at the point of ±500mV from steady state voltage.
'4 This parameter is specified with Load n in Fig. 2.

1-65

IU~IIUMlillli
FWI"I'SU

11111. ._

..

MB81C75-25
MB81C75-35

WRITE CYCLE H: CS CONTROLLED"'2

ADDRESS

I&:gJ

Undefined

•

Don'tCa..

Note: *1 If CS goes high simultaneously with WE high, the output remains in high impedance state.
*2 All write cycle are determined from last address transition to the first address transition of the
next address.

1-66

1111111111111111111111111111111111111111111111111111

MB81C75-25
MB81C75-35

FUJITSU
1111111111111111111111111111111111111111111111111111

..

TYPICAL CHARACTERISTICS CURVES
Fig.4 - OPERATING SUPPLY CURRENT
vs. AMBIENT TEMPERATURE

Fig. 3 - OPERATING SUPPLY CURRENT
VS. SUPPLY VOLTAGE

Vee = 5.5V
t?

1.2

t?

Z

1.2

F
~I-

1.1

F
..:
a:

IwZ
oa:
Oa:
w:>
NU
:::i>-

1.1

Z

wZ
oa:
Oa:
w:>
NU
:::i~
":0.
:l10.
a::>
000
Z

o.W

o.W

1.0
0.9

..:-'

:l1~
a::>
000
Z
U

0.8

U
.2

1.0
0.9

--

.2
5.0

4.5

5.5

0
25
75
100
50
T A • AMBIENT TEMPERATURE (oC)

Fig.6 - STANDBY SUprLY CURRENT
VS. AMBIENT TEMPERATURE

Fig. 5 - STANDBY SUPPLY CURRENT
VS. SUPPLY VOLTAGE
>-

TA

III

= 25°C

>-

ISB1

Vee

III

0

..:
!;il-

..

leel
0.8

Vee. SUPPLY VOLTAGE (V)

Z

_

0

Z

1.2

OZ 1.1
Na:
-a:
-':>
..:u
1.0
:l1>a:-,
00.
zo. 0.9
.:>
<"00
.!!'
0.8

..:
!;il-

1.2

..:u

1.0

= 5.5V

---- - -

_.

OZ 1.1
WW
Na:
-a:
-':>

WW

:l1>a:-,
00.
zo. 0.9
.:>
<"00
.!!'
0.8

"'

ISB1

"'

iii

"'

.!!'

.!!'
4.5
5.5
5.0
Vee. SUPPL Y VOLTAGE (V)

Fig. 7 -

t?
Z

a:
WIOw
oa:
wac
N:>

TA = 25°C
Vee = 5.5V
VIN = VIHiVlL

1.4 -

~--I--'

1.0 - - --~-'I---

::J~ 0.6

~~

OPERATING SUPPLY CURRENT
VS. FREOUENCY

1.8 _

F
..:

o.z

0
75
25
50
100
TA. AMBIENT TEMPERATURE (oC)

----+---1-----1

-7

_

a: 0.
t-0:>
Z 00 0.2 1-----+~-+__+__-_t__t____1
N
()

.2
5

10

50100

f. FREQUENCY (MHz)

1-67

..

1lllmllllllllllllllllmllllllllllllllllm~11111
FUJITSU
1IIIIIIIIIIIIImllllllllllllllllllllllllllllllllili

MBB1C75-25
MBB1C75-35

TYPICAL CHARACTERISTICS CURVES (Cont'd)
Fig.8 - "H" LEVEL OUTPUT VOLTAGE
vs. "H" LEVEL OUTPUT CURRENT

Fig. 9 - "L" LEVEL OUTPUT VOLTAGE
vs. "L" LEVEL OUTPUT CURRENT

TA =25°C

3.8f---+~_e::.::e'-r=_5_.0__
V+--+_ ..-t_

,..
,..:J

3.6f---+-+--+--+-+-----

""-

3.4

:J-

------ / - -

3.2/----1--1--

0>

~~
>CJ
w..:

~ .......

-'~

,

3.0 r----

0.3

0.

...... ~

--- 1----

~

o

2.5

5.0

7.5

0.2
0.1

0

~>

---- 1-'---

- - --

---

0.4

0

1--'

I

-----1--

~----t

[7

./

f---t---~ ~.

I---~~-

.J

10

TA = 25°C
Vee = 5.0V

o

5

10

15

20

IOL' "L" LEVEL OUTPUT CURRENT (rnA)

IOH. "H" LEVEL OUTPUT CURRENT (rnA)

Fig. 11-ACCESS TIME vs. AMBIENT
TEMPERATURE

Fig. 10 - ACCESS TIME vs. SUPPLY
VOLTAGE

Vee = 4.5V
Cl

::-=~t-;~
1.0-V

1.2

w
N

:::;

..:

1.1 f----f'''--+-

:;;w
"':;;

~ ~

L -

1.0

w~

~~

0.9

0.9 - - - / - - - - - .---1-----+---1

0.8

0.81---+--+--+----I----+----I

~..:

:f-

o

4.5
5.0
5.5
Vee, SUPPLY VOLTAGE (V)

Fig. 12 -

Cl

1.4

ACCESS TIME vs. LOAD
CAPACITANCE

TA = 25°C
Vee =4.5V
-~---

--

w
N

:::;

..:

z,..

1.0

~u

OW
.U
~..:

0.8

:f-

0.6

w~

V

--

./

1.2

:;;w

"':;;
0-

~

~I-- I---

tAA, tACS

-t-

1--- f - -

.(

:f-

1-68

25

50

75

100

TA , AMBIENT TEMPERATURE 1°C)

o
50
100
150 200
C L , LOAD CAPACITANCE (pF)

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~IIIIIII

MB81C75-25 FUJITSU
MB81C75-35 11111111111111111111111111111111111111111111111m~

..

PACKAGE DIMENSIONS
(Suffix: P)
24-LEADS PLASTIC DUAL-IN-LlNE PACKAGE
(CASE No.: Dlp·24p·-M03)

r- ""'"
I

INDEX-2-

(

._. ---tr

MAX

I

.300'.010
17 .62+0.251

__ J

,(llQ;',(lO?.J
!O 75+0 051

Dimensions in
(millimeten)

;nche~
(f)

FUJITSU LIMITED 1987 D24017S-2C

1-69

IIMIm_1

~.M_~ =::~~~t~~
PACKAGE DIMENSIONS
(Suffix: ·PJ)

24-LEAD PLASTIC LEADED CHIP CARRIER
(CASE No.: LCC-24P·M02)

,- e:

~11

I

o
~F~EAEIFNEDEMXEAEAEA69696969~~
.050±.005
(1.27±0.13)

!"~
I

I--

.091(2.31 )
NOM

.550(13.97)REF

•. 615±.005(15.62±0.13)

'1-

005
(8.64±0.13)
.273±.020
(6.93±0.51 )

.300(7.62)

.025(0.64)
MIN
.144(3.66)
M AX

M

032(0.81 )MAX

Details of "AU part

.102(2.60)
NOM

~ I
* : This dimensiQn

includes resin protrusion. (Each side: .006(O.15)MAX-l
019111 FUJITSU LIMITED C24062S-1C

1-70

.017±.004
• (0.43±0.1 0)

Dimensions in
inches (millimeters).

1111111111111111111111111111111111111111111111111111

:::~~~:~i IIIW:IIDI_II

..

PACKAGE DIMENSIONS

(Suffix: CV)

... . :.'. .
(;j)
.

NC

ASNUVCC NC

"

".

CERAMIC PACKAGE
LCC-28C-A03

28-PAD CERAMIC (METAL SEAL) LEADLESS CHIP CARRIER
(CASE No_: LCC-28C-A03)

·PIN NO.1 INDEX

/

II

.550±.010
113.97±0.25)

I

.460(11.68)
TYP

.400(10.16)
TYP
R.008(O.20)TYP
(28PLCS)

.350±.010
(8.89±0.25)
.083(2.11)MAX

TYP
TYP

·Shape of PIN NO.1 INDEX: Subject to change without notice.

.04511.14)
TYP

Dimensions in inches
and (millimeters)

© FUJITSU LlMITED1987 C28009S·1C

1-71

Hiflh-speed CMOS SRAMs

..

1-72

Static RAM Data Book

MB81C78A-35
MB81C78A-45
November 1987
Edi1ion 2.0

64K·BIT (8192x8) HIGH SPEED CMOS STATIC RANDOM
ACCESS MEMORY WITH AUTOMATIC POWER DOWN
The Fujitsu MB 81 C78A is 8192 words x 8 bits static random access memory
fabricated with a CMOS process. The memory utilizes asynchronous circuitry
and may be maintained in any state for an indefinite period of time. All pins
are TTL compatible and a single 5 volts power supply is required.
A separate chip select (CS1 ) pin simplifies multi package systems design. It
permits the selection of an individual package when outputs are OR·tied,
and furthermore on selecting a single package by CS1 , the other deselected
packages automatically power down.

PLASTIC PACKAGE
DIP·28P·M04

All devices offer the advantages of low power dissipation, low cost, and high
performance.
• Organization: 8192 words x 8 bits
• Static operation: No clock or timing strobe required
• Fast access time: tAA = tACS1 = 35 ns max. (MB 81C78A-35)
tAA = tACS1 = 45 ns max. (MB 81C78A-45)
• Low power consumption: 495 mW max. (Operating)
138 mW max. (Standby, TTL level)
83 mW max. (Standby, CMOS level)
• Single +5V supply, ±10% tolerance
• TTL compatible inputs and outputs
• Three·state outputs with OR·tie capability
• Chip select for simplified memory expansion, automatic power down
• All inputs and outputs have protection against static charge
• Standard 28'pin Plastic DIP package (Suffix: -P-SK)
• Standard 28·pin Bend type Plastic Flat package (Suffix: ·PF)
• Standard 32-pad Leadless Chip Carrier (Suffix: ·CV)

PLASTIC PACKAGE
FPT-28P.M02

CERAMIC PACKAGE
LCC·32C·A02
PIN ASSIGNMENT

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Value

Unit

Supply Voltage

Vce

-0.5 to +7

V

Input Voltage on any pin
with respect to GND

V1N

-3.5 to +7

V

Output Voltage on any I/O
with respect to GND

VOUT

-0.5 to +7

V

Rating

Symbol

lOUT

±20

Power Dissipation

Po

1.0

W

Temperature Under Bias

T S1AS

-10 to +85

'c

I PLASTIC
ICERAMIC

Vee

N.c'Wi~

mA

Output Current

Storage
Temperature

N.C

,01",01,4

i.~l~~~~1 ~3:13_'1J?.:

-40 to +125
TSTG

-65 to +150

'c

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATI NGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

~r4ri5116" 1T18rI9i:!O~
'/02 "ssNC, 1/05110&
'/OJ
I/O.

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit.

1-73

..

1IIIIImwlllllllllllll~IIIW~lllllmmm
FUJITSU MB81C78A-35
1111111111111111111111111111111111111111111111111

MB81C78A-45

..

Fig. 1 - MB 81C78A BLOCK ElIAGRAM

I--

I--

·
·
·

·
·
·

ADDRESS
BUFFER

ROW
DECODER

-

--Vee
-GND
256x32x8
MEMORY CELL
ARRAY

-

0

. .

I

dS4

.

I

I/O GATE
&
COLUMN DECODER

ADDRESS
BUFFER

. . .

I

JS4

J

OE
BUFFER

r--CS

DATA I/O BUFFER

~

1 11

111 11

TRUTH TABLE
SUPPLY
CURRENT

I/O
STATE

CS,

CS 2

WE

OE

MODE

H

X

X
X

IS8

HIGH·Z

L

X
X

STANDBY

L

DESELECT

Icc

HIGH·Z

L

H

H

H

HIGH·Z

H

H

L

DOUT DISABLE
READ

Icc

L

Icc

DOUT

L

H

L

X

WRITE

Icc

DIN

CAPACITANCE (TA = 2SoC, f = 1MHz)
Parameter

1-74

Symbol

Typ

Max

Unit

Input Capacitance (V IN = OV) (CS" CS2 , OE, WE)

C I,

7

pF

Input Capacitance (V IN = OV) (Other Inputs)

C I2

6

pF

I/O Capacitance (VI/o = OV)

CliO

B

pF

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImillmlllllili

MB 81C78A-35
MB 81C78A-45

FUJITSU
1IIImllillmlllllillmllllllllllllllllllllili

..

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Symbol

Min

Typ

Max

Unit

Supply Voltage

Vee

4.5

5.0

5.5

V

Input Low Voltage

V'L

-2.0'

0.8

V

Input High Voltage

V'H

2.2

6.0

V

Ambient Temperature

TA

0

70

°c

Parameter

• -2.0V Min. for pulse width less than 20 ns. (V'L Min = -0.5V at DC level)

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Symbol

Min

Max

Unit

Test Condition

Input Leakage
Current

ILl

-10

10

p.A

V'N = OV to Vee

Output Leakage
Current

I LO

-10

10

p.A

CS 1 = V'H or CS2 = V'L or WE = V'L or
OE = V'H, VOUT = OV to Vee

Operating Supply
Current

lee

90

rnA

CS 1 = V'L
I/O = Open, Cycle = Min

ISB1

15

rnA

Vee = Min to Max. CS1 = Vee-0.2V
V'N ~0.2V or V'N ~ Vee-0.2V

15B2

25

rnA

CS 1 = V'H

Output Low
Voltage

VOL

0.4

V

IOL =8mA

Output High
Voltage

V OH

V

IOH = -4mA

Peak Power·on
Current

Ipo

Standby Supply
Current

2.4

50

rnA

Vee = OV to Vee Min.
CS 1 = Lower of Vee or V'H Min.

1-75

IlmllllmllllmlmllWiiml~llmWl
FUJITSU

MB81C78A-35

1lllllmlllmmllllmilmlmm~lllmlll MB81C78A-45

..

AC TEST CONDITIONS

Input Pulse Levels:

O.6V to 2.4V

Input Pulse Rise And Fall Times:

5ns (Transient time between O.8V and 2.2V)

Timing Measurement Reference Levels:

Input:
Output:

1.5V
1.5V

Fig. 2
Output Load II.

Output Load I.
For all except tLz, tHz, twz, tow,
to LZ , and toHz.

5V

5V

4800.

4800.
DOUT-_-~

D OUT - - ; - -........

2550.

1-76

255!l

1IIIImm~~~II~mlllmllllllmlllm~11111

MB81C78A-35 FUJITSU
MB81C78A-45 1IIIIIImmm~~lmm~~~ilmllllll

AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted. I
READ CYCLE'1
MB 81C78A·35
Parameter

MB81C78A·45
Unit

Symbol
Min

Max

Min

Max

45

ns

Read Cycle Time

t Rc

Address Access Time '2

tAA

35

45

ns

CS 1 Access Time '3

t ACS1

35

45

ns

CS2 Access Time '3

t ACS2

15

20

ns

Output Hold from Address Change

tOH

OE Access Time

tOE

Output Active from CS 1 '4 '5

t LZ1

5

5

ns

Output Active from CS 2 '4 '5

t LZ2

3

3

ns

Output Active from OE'4'5

tOLZ

3

3

ns

Output Disable from CS 1 '4 '5

t HZ1

20

25

ns

Output Disable from CS 2 '4'5

t HZ2

20

25

ns

Output Disable from OE'4'5

tOHZ

20

25

ns

35

3

ns

3
15

20

ns

Note: *1

WE is high for Read cycle.
*2 Device is continuously selected, CS 1 = V 1L , CS2 = V 1H and OE = V 1L .
*3 Address valid prior to or coincident with CS 1 transition low, CS 2 transition high.
*4 Transition is specified at the point of ±500mV from steady state voltage.
*5 This parameter is specified with Load II in Fig. 2.

1-77

1IIIIImillmlllllllllllllllllllllllllillmlllili

FUJITSU MB81C78A-35
1IIImll~~IIIIIIIIII~lllllmlllllllllllllllllll MB81C78A-45

..

READ CYCLE TIMING DIAGRAM'1

READ CYCLE I: ADDRESS CONTROLLED'2

ADDRESS

DATA OUT

READ CYCLE

PREVIOUS DATA VALID

n:

DATA VALID

CS 1 , CS2 CONTROLLED'3

ADDRESS

CS1

I/O

III : Don't Care
Note: "1
*2
*3
*4
*5

1-78

I8XI :Undefined

WE is high for Read cycle.
Device is continuously selected, CS1 = V'L, CS2 = V'H and OE = V'L'
Address valid prior to or coincident with GS 1 transition low, CS 2 transition high.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load in Fig. 2.

n

1111111111111111111111111111111111111111111111111111

MB81C78A-35 FUJITSU
MB81C78A-45 1IIIIIIIIIIIIIIIIIIIIIIm~~lllllllllmlmllllll

WRITE CYCLE"

MB B1C7BA-35
Parameter

MBB1C78A-45

Symbol

Unit
Min

Max

Min

Max

Write Cycle Time '2

twe

35

45

ns

CS, to End of Write

t ew ,

30

40

ns

CS 2 to End of Write

tew2

20

25

ns

Address Valid to End of Write

tAW

30

40

ns

Address Setup Time

tAs

0

0

ns

Write Pulse Width

twp

20

25

ns

Data Setup Time

tow

17

20

ns

Write Recovery Time '3

tWR

3

3

ns

Data Hold Time

tOH

0

0

ns

-"'4"'5

Output High-Z from WE

twz

Output Low-Z from WE'4's

tow

Note:

*1
*2
*3
*4
*5

20

15
0

0

ns
ns

ff CS, goes high simultaneously with WE high, the output remains in high impedance state.
All write cycles are determined from the last address transition to the first address transition of next address.
tWR is defined from the end point of Write Mode.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

1-79

1IIImll~iIRmllll!~H
FUJITSU MB81C78A-35
mlliWII~II~~!11U MB81C78A-45

..

WRITE CYCLE TIMING DIAGRAM'

WR ITE CYCLE I: CS" CS2 CONTROLLED

cs,

I/O

III : Don't Care

Nota: *,
*2
*3
*4
*5

1-80

~ : Undefined

If OE, CS" and CS2 are in the READ Mode during this period, I/O pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
All write cycle are determined from the last address transition to the first address transition of next address.
tWR is defined from the end point of WR ITE Mode.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImlllillmlili

MB81C78A-35
MB81C78A-45

FUJITSU
1111111111111111111111111111111111111111111111111

..

WRITE CYCLE TIMING DIAGRAM"

WRITE CYCLE II: WE CONTROLLED
~_________________ twc~'2~__~__________~

cs,

tow

I/O

tOH

DIN VALID

I8lSI : Undefined

Nota: *1
*2
*3
*4
*5

If OE, CS" and CS2 are in the READ Mode during this period, I/O pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
All write cycles are determined from the last address transition to the first address transition of next aduress.
tWR is defined from the end point of WR ITE Mode.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

1-81

llllllllllllllll~lmlllllllll~llllllllllllll~l~
FUJITSU

MB81C78A-35
MB81C78A-45

1IIIIIIIIIIIIIIIImlllmmll!lmllllllllllll~1

..

Fig. 4 - NORMALIZED ACCESS
TIME VB. AMBIENT TEMPERATURE

Fig. 3 - NORMALIZED ACCESS
TIME VB. SUPPLY VOLTAGE

oW

oW

«

:::;

«

1.2

:;
0::

~ w1.1

tAeSt'
tOE
01'": en 1.0 r,ACS2
Olen

w~

-

........

~~1.0

r---

uu

~~0.9

$.i:
$-

5.0

5.5

020406080
T A • AMBIENT TEMPERATURE (OC)

Fig. 5 - NORMALIZED POWER SUPPLY
CURRENT VB. AMBIENT TEMPERATURE

Fig. 6 - NORMALIZED POWER SUPPLY
CURRENT VB. AMBIENT TEMPERATURE

I
Vee = 5.5V

Vee

ffi

1.2

"-z

~ 1.1

~~

;i

U1.0

~~
~ ~0.9

'-..

"-00::i:ii 1.1

iii

""',

Wo::

~::>

-- -

...I

r--

u1.0

~~

gj R: 0.9

........

z::J

en

~

.(1)

~

0.8

0.8

020406080

T A • AMBIENT TEMPERATURE (oC)

Fig. 7 - NORMALIZED POWER SUPPLY
CURRENT VB. SUPPLY VOLTAGE
0::

~

TA =125oC I

1.2

"-

o~

~o::
...10::

~1ho
Z R: 0.9
N::>

~{/)

iii
~

0.8

/

ISB 1(DC)
ISB2 = Cycle min.

w w 1.1

gj~

i'.

020406080

T A • AMBIENT TEMPERATURE (OC)

ISB2

//

V

/'

V

ISB1

V
4.5

5.0

5.5

Vcc. SUPPLY VOLTAGE (V)

1-82

~ 5.5V

1.2

~I-

01-

fil

~A~ tAeS2. tOE

0.8

Vee. SUPPLY VOLTAGE (V)

0::
~

-

~

U)W

~

4.5

/

01-

0.8

<
$-

~

~ w1.1

uu
~~0.9

~

I

0::

(l)W

$-

~4.5V

1.2

:;

~A'

w~

Vee

N

T A =25°C

N

:::;

1111111111111111111111111111111111111111111111111111

MB81C78A-35 FUJITSU
MB81C78A-45 1IIIIIIIIIIIIIImllllllllllllllllllll~ml~~ml

Fig. 9 - NORMALIZED ACCESS
TIME vs. LOAD CAPACITANCE

Fig. 8 - NORMALIZED POWER SUPPLY
CURRENT vs. SUPPLY VOLTAGE

I

°

w

ffi

1.2

~ ~

1.1 - - - I - - - ---

~t-

wO:

~~

-' u 1.0

~~
~ ~

Z::J

0.9

,m

2

0.8

V

TA = 25°C
Vee = 4.5V

::;;

I

TA = 25 C
I--Icc::: Cycle min.

V
7

V'

i= 1 6

-

~

.

w
tl1.4

<

C
:!J 1.2

.-10-

::;

<
::;;

II:

V

1.0

V

a
Z

.;:0.8

~
4.5

w
::;;

i=

5.0

°

5.5

200

C L • LOAD CAPACITANCE (pF!

Fig. 10 - NORMALIZED ACCESS
TIME VS. LOAD CAPACITANCE

Fig. 11 - NORMALIZED ACCESS
TIME VS. LOAD CAPACITANCE

w
::;;

TA = 25°C
Vee =4.5V

~

TA = 25°C
Vee = 4.5V

V

1.6

m 1.6
m
w

m

~1.4

~1.4

.IV

w

U

U

C

-"""I.-

:!J 1.2

::;

<

~

~ 1.0

V

a

/

:!J 1.2

::;

<

/

~ 1.0

V

V

a

a
Z

100

Vee. SUPPLY VOLTAGE (V)

Z

,0.8

N°·8

iii

rn
u
~

u

~
100

°

200

100

°

C L • LOAD CAPACITANCE (pF)

200

C L • LOAD CAPACITANCE (pF!

Fig. 12 - NORMALIZED POWER
SUPPL Y CURRENT VS. FREQUENCY

or

ffi

1.4

~t-

~ ~1.2

TA = 25 C
Vee= 5.5V
V IN = VIN/VIL

~~
_::J
-' U

~~

@5

1.0

to.a

z::J

m

U
.E 0.6

-'

V

/

10
f. FREQUENCY (MHz!

1-83

..

1111111111111111111111111111111111111111111111111111

FUJITSU
1IIIIIIIIIIIIIIIIIIIIIIIIIIIImlllllllllllllllllili

MBB1C7BA-35
MBB1C7BA-45

PACKAGE DIMENSIONS
PLASTIC DIP (Suffix: P·SK)

,-------------------------------------------------------------------,
28·LEAD PLASTIC DUAL·IN·LlNE PACKAGE
(CASE No.: DIP·28p·M04)
I

J. 15'MAX

-~-=·----·--Tr

.30oI7.62)TYP

.010±.002
10.25'0.05)

...--.; I- ··.05011.27)MAX

.034.. ~1210.86~~3)

II
I

-J _..

018±.003
10.46<0.08)

(f) FUJiTSU LIMITED 1986 D28018S-2C

1-84

~1·207(5.25)MAX

. ·_1·-:=1·",,,·,",,
.02010.51 )MIN

DImensions In
inches (millimeters)

1lllllllllllllllllllllllllllllmlllllllllmm~11

MB81C78A-35 FUJITSU
MB81C78A-45 1IIIIIIIm~~~IIIIIIIII~lmlllllllll~l~mlll

..

PACKAGE DIMENSIONS
PLASTIC FPT (Suffix: -PFI
28-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-28P-M021
O(O)MIN

~,oo'"

1

View "A"

.339±.00S
(S.6±0.2)

INDEX

d

~nr~~~~~rrr~

J

.465±.012
(11.8tO.3)

.402±.012

J'"

.006t.002
(0.15tO.05)

.00S(0.1S)
MAX
.027(0.6S)
MAX

.110(2.S)MAX

OClnn nnn nnn nOn

b A D .096±.006
(2.45±0.1S)

-1 r~S;1.;7)~P" -=J ~g.~~f -

Dimensions in
inches (millimeters)

©FUJITSU LIMITED 1987 F28011S·2C

1-85

..

·lllml.~I~~mllllm

pwrrsv
mmOOililllllmllill1

MB81C7BA-35
MB81C78A..45

PACKAGE DIMENSIONS
CERAMIC LCC (Suffix: ·CVI
32·PAD CERAMIC (METAL SEALI LEADLESS CHIP CARRIER
(CASE No.: LCC·32C-A021

'PIN NO.1 INOEX

.065(1.65)
TYP

C.040( 1.02)TVP
(3PLCS)

.045(1.14)
TVP
.085(2.16)

MAX

.360(9.14)TVP
C.015(0.38)TVP

I

.050 •. 006
(1.27.0.15)

.300(7.62)TVP

• Shape of PIN NO.1 INOEX: Subject to change without notice.
@FUJITSU LIMITED 1987 C32011S·3C

1-86

Oimensions in inches
(millimeters)

MB81C79A-35
MB81C79A-45
Novenber 1987

12K-BIT (8192x9) HIGH SPEED CMOS STATIC RANDOM
ACCESS MEMORY WITH AUTOMATIC POWER DOWN

Edition 2.0

The Fujitsu MB 81C79A is 8192 words x 9 bits static random access memory
fabricated with a CMOS process. The memory utilizes asynchronous circuitry
and may be maintained in any state for an indefinite period of time. All pins
are TTL compatible and a single 5 volts power supply is required.
A separate chip select (CS,) pin simplifies multipackage systems design. It
permits the selection of an individual package when outputs are OR·tied,
and furthermore on selecting a single package by CS" the other deselected
packages automatically power down.

PLASTIC PACKAGE
DIP·28P·M04

All devices offer the advantages of low power dissipation, low cost, and high
performance.
• Organization: 8192 words x 9 bits
• Static operation: No clock or timing strobe required
• Fast access time: tAA = tACS' = 35 ns max. (MB 81C79A·35)
tAA = tAcs, = 45 ns max. (MB 81C79A·45)
• Low power consumption: 495 mW max. (Operating)
138 mW max. (Standby, TTL level)
83 mW max. (Standby, CMOS level)
• Single +5V supply, ±10% tolerance
• TTL compatible inputs and outputs
• Three·state outputs with OR·tie capability
• Chip select for simplified memory expansion, automatic power down
• All inputs and outputs have protection against static charge
• Standard 28'pin Plastic DIP package (Suffix: ·P·SK)
• Standard 28'pin Bend type Plastic Flat package (Suffix: ·PF)
• Standard 32·pad Leadless Chip Carrier (Suffix: ·CV)

PLASTIC PACKAGE
FPT·28P·M02

CERAMIC PACKAGE
LCC·32C·A02

PIN ASSIGNMENT

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Value

Unit

Vcc

-0.5 to +7

V

VIN

-3.5 to +7

V

Output Voltage on any I/O
with respect to GN D

VOUT

-0.5 to +7

V

Output Current

mA

Rating
Supply Voltage
Input Voltage on any pin
with respect to GN D

Symbol

lOUT

±20

Power Dissipation

Po

1.0

W

Temperature Under Bias

T BIAS

-10to+85

·C

Storage
Temperature

I PLASTIC
ICERAMIC

-40 to +125
TSTG

DC

-65 to +150

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RA TI NGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

This device contains circuitry to protect the
inputs against damage due to-high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit.

1-87

..

m~~m~OO~lmlmmmli~lllmlllllll
FUJITSU
1IIIm~~lmlmmllll~mll~llim~lllmli

MB81C79A-35
MB81C79A-45

-

Fig. 1 - MB 81C79A BLOCK DIAGRAM

-

-

·
·
·

ADDRESS
BUFFER

·
·

ROW
DECODER

-

-Vee
-GND

256x32.9
MEMORY CELL
ARRAY

·
-

. . .

I

JS*

I

I/O GATE
&
COLUMN DECODER

ADDRESS
BUFFER

. . . I

I

JS*

BUFFER

DATA I/O BUFFER

CS

~,

111111111

ds

I/O,

1/03
1/05
1/07
1/0 9
1/04
1/02
1/06
I/OS

TRUTH TABLE
CS,

CS2

WE

OE

MODE

H

X

X
X

X
X

STANDBY

H
L

DOUT DISABLE
READ

X

WRITE

L

L

L

H

L

H

H
H

L

H

L

DESELECT

SUPPLY
CURRENT

Si~~E

158
Icc
Icc
Icc
Icc

HIGH·Z
HIGH·Z
HIGH·Z
DOUT
DIN

CAPACITANCE (T A = 25°C. f = 1MHz)
Parameter

1-88

Symbol

Typ

Max

Unit

Input Capacitance (V IN = OV) (CS,. CS2 • OE. WE)

CI,

7

pF

Input Capacitance (V IN = OV) (Other Inputs)

C I2

6

pF

I/O Capacitance (Vila = OV)

CliO

8

pF

111!lllllllllllliimllmll~mllllllllllmllllll
FUJITSU

MB81C79A-35
MB81C79A-45

11111~IIIIIIIII~mmllllll~~~llllml~111111

..

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Symbol

Min

Typ

Max

Unit

Supply Voltage

Vee

4.5

5.0

5.5

V

Input Low Voltage

V'L

-2.0'

0.8

V

Input High Voltage

V'H

2.2

6.0

V

Ambient Temperature

TA

0

70

°c

Parameter

• -2.0V Min. for pulse width less than 20 ns. IV,L Min = -0.5V at DC level)

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Symbol

Min

Max

Unit

Test Condition

Input Leakage
Current

III

-10

10

Il A

Output Leakage
Current

I Lo

-10

10

Il A

CS, = V'H or CS2 = V'L or WE
OE = V ,H , VOUT = OV to Vee

Operating Supply
Current

lee

90

mA

CS, = V ,L
I/O = Open, Cycle

ISB'

15

mA

Vee = Min to Max. CS, = Vee-0.2V
V'N ~0.2Vor V ,N ~ Vee-0.2V

ISB2

25

mA

CS,

= V'H

Output Low
Voltage

VOL

0.4

V

IOL

= SmA

Output High
Voltage

V OH

V

IOH

= -4mA

Peak Power·on
Current

Ipo

mA

Vee
CS,

= OV to Vee Min.
= Lower of Vee or V ,H

Standby Supply
Current

2.4

50

I

V ,N

= OV to Vee
= V'L

or

= Min

Min.

1-89

11111111~~~lmllllllllillll~mllllllmlllll
FVJITSU

MB81C79A-35

m~~llmllllmlll~~~IIII~~~I~~~~1 MB 81C79A-45

..

AC TEST CONDITIONS

Input Pulse Levels:

O.6V to 2.4V

Input Pulse Rise And Fall Times:

5ns (Transient time between O.BV and 2.2VI

Timing Measurement Reference Levels:

Input:
Output:

1.5V
1.5V

Fig. 2
Output Load I.

Output Load

n.

For all except tLZ, t HZ , twz, tow,
t OLZ , and tOHZ'

5V

480n
DOUT

255fl

1-90

---.----<
255n

III~~~I~II~~III~~III!II~III~IIIII~I

MB81C79A-35 FUJITSU
MB8l C79A-45 1~~lllml~i~I~!~~ml~~~I!!~lill~

..

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)

READ CYCLE'1
MB 81C79A·35
Parameter

MB 81C79A45

Symbol

Unit
Min

Max

Min

Max

45

t RC

Address Access Time' 2

tAA

35

45

ns

CS 1 Access Time '3

t ACS1

35

45

ns

CS2 Access Time '3

t ACS2

15

20

ns

Output Hold from Address Change

tOH

OE Access Time

tOE

Output Active from CS 1 '4 '5

t LZ1

5

5

ns

Output Active from CS2 '4 '5

t Lz2

3

3

ns

Output Active from OE'4'5

tOLz

3

3

ns

Output Disable from CS 1 '4 '6

t HZ1

20

25

ns

Output Disable from CS2 '4'5

tHZ2

20

25

ns

Output Disable from OE'4'5

tOHZ

20

25

ns

Note: "1
*2
*3
*4
*5

35

ns

Read Cycle Time

3

3
15

ns
20

ns

WE is high for Read cycle.
Device is continuously selected, CS1 : V 1L , CS2 : V 1H and OE: V 1L .
Address valid prior to or coincident with CS 1 transition low, CS 2 transition high.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load IT in Fig. 2.

1-91

1~1111~lIiumlll
FUJITSU
1~IHI!I~lllllllli~

..

MB81C79A-35
MB81C79A-45

READ CYCLE TIMING DIAGRAM'1

READ CYCLE I: ADDRESS CONTROLLED'2

ADDRESS

DATA OUT

READ CYCLE

PREVIOUS DATA VALID

n:

CS,. ~ CONTROLLED'3

ADDRESS

1/0

DOUT VALID

~ : Undefined

Note: *1
*2
*3
*4
*5

1-92

•

WE is high for Read cycle.
Device is continuously selected, CS 1 = V 1L , ~ = V 1H and OE = V 1L •
Address valid prior to or coincident with CS 1 transition low, CS2 transition high.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load n in Fig. 2.

: Don't Car.

l~mllmm~~~mloo~lmlllll~OO~~~1

MB81C79A-35 FUJITSU
MB81C79A-45 Imllll~~ml~~~~~~~lllllmlll~~~~m

..

WRITE CYCLE"
MB 81C79A-35
Parameter

MB 81C79A-45

Symbol

Unit
Min

Max

Min

Max

Write Cycle Time '2

twe

35

45

ns

CS, to End of Write

t ew ,

30

40

ns

CS 2 to End of Write

tew2

20

25

ns

Address Valid to End of Write

tAW

30

40

ns

Address Setup Time

tAs

0

0

ns

Write Pulse Width

twp

20

25

ns

Data Setup Time

tow

17

20

ns

Write Recovery Time '3

tWR

3

3

ns

Data Hold Time

tOH

0

0

ns

Output High-Z from WE'4'5
-*4·5

Output Low-Z from WE
Note: *1
*2
*3
*4
*5

15

twz
tow

0

20
0

ns
ns

If CS, goes high simultaneously with WE high, the output remains in high impedance state.
All write cycles are determined from the last address transition to the first address transition of next address.
tWR is defined from the end point of Write Mode.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load IT in Fig. 2.

1-93

-

F WITSU

111111.-0

..

MB81C79A.. 35
MB81C79A-45

WRITE CYCLE TIMING DIAGRAM"

WRITE CYCLE I: CS1 , CS2 CONTROLLED

I/O

~ : Undefined

Note:

*,
*2
*3
*4
*5

1-94

. : Don'tea..

If OE, CS1 , and CS2 are in the READ Mode during this period, I/O pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
All write cycle are determined from the last address transition to the first address transition of next address.
tWR is defined from the end point of WR ITE Mode.
Transition is specified at the point of ±500inV from.steady state voltage.
This parameter is specified with Load n in Fig. 2.

Illmllllll~~lllmlllmlll~~~~llmll!ll~

MBB1C79A-35 FUJITSU
MBB1C79A-45 1111~11111~lllmlllllll~!~~m~~~~M~1

..

WRITE CYCLE TIMING DIAGRAM"

WRITE CYCLE II: WE CONTROLLED

cs,

CS2

110

DIN VALID

1881 : Undefined

Note: *1
*2
*3
*4
*5

III :Don't Care

If OE, CS" and CS2 are in the READ Mode during this period, I/O pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
All write cycles are determined from the last address transition to the first address transition of next address.
tWR is defined from the end point of WR ITE Mode.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load IT in Fig. 2.

1-95

~~lllllllmlll~~mlil~IIIIIII~1111111111111

MB81C79A-35

FUJITSU

1111111111~ml~lmll~~~III~~IIIII~~im MB81C79A-45

..

Fig. 3 - NORMALIZED ACCESS
TIME VS. SUPPLY VOLTAGE

Fig. 4 - NORMALIZED ACCESS'
TIME VS. AMBIENT TEMPERATURE
C

C

w

W

TA=125°C

N

:::;

«

«

1.2

:;

a:
~ wl.l
w;;!l

01-

":gj

f/lw
uu

\.

w;;!l

tAest,'
tOE
~
1.0 r-tACS2

r--:

~

0.8

~A~ tAeS2. tOE

0.8

.(
4.5

5.0

!-

5.5

020406080
T A. AMBIENT TEMPERATURE (OC)

Fig. 5 - NORMALIZED POWER SUPPLY
CURRENT VS. AMBIENT TEMPERATURE

Fig. 6 - NORMALIZED POWER SUPPLY
CURRENT VS. AMBIENT TEMPERATURE

Vee! 5.5V

a:

Vec

ffi

~ I- 1.2
o-z

S ~1.1
~~

Ul.0

~~
~ ~0.9

'"
.; 0.8

~ 5.5V

1.2

~I-

Q..

'-..

--

--

ffi 1.1

Ca:
wa:

'" '"

!::l::::>
-' u 1.0

~~

r-

gs g; 0.9
z.. ~

2

0.8

020406080

TA =1 25oC I

w

~

1.'2

0-

C!Z
W wl.l

IS81 (DC)
15B2 "" Cycle min.

!::la:
-'a:

~i:ho
gs~

z g; 0.9
~~

.!!J

iii
.!!J

0.8

I'-.

T A • AMBIENT TEMPERATURE (oC)

Fig. 7 - NORMALIZED POWER SUPPLY
CURRENT VS. SUPPLY VOLTAGE

a:

"-

020406080

T A • AMBIENT TEMPERATURE (oC)

IS82

//

~

1/

J
~

IS81

/

5.5
5.0
4.5
Vcc. SUPPLY VOLTAGE (V)

1-96

r--

/

uu

~~0.9
Iii

Vee. SUPPLY VOLTAGE (V)

~

/

01-

",1.0
",,,,
",w

~.

j

;t

t»_

a:
~w1.1

~~0.9

!-~

1.2

:;

tAA.

l

Vee = 4.5V

N

:::;

1111111111111111111111111111111111111111111111111111

MB81C79A-35
MB81C79A-45

w
:;

ffi

1.2

~f-

~ tlj

~~

:Ell

1.1

: :; a
~~

~ it
z::J

.'"

1l

1.0

0.9
0.8

V

V

V

i=
~

V

..

Fig. 9 - NORMALIZED ACCESS
TIME vs. LOAD CAPACITANCE

Fig. 8 - NORMALIZED POWER SUPPLY
CURRENT vs. SUPPLY VOLTAGE
TA =125°Cl
Icc Cycle min.

FUJITSU
1111111111111111111111111111111111111111111111111111

T A =25°C
Vee = 4.5V

16

.

w

tl

<

1.4

C

_i--

~ 1.2

:J

V

<

:; 1.0

~

I!:

o
z

.;:0.8

j
4.5

w
:;

i=
rJ)

5.0

o

5.5

Fig. 10 - NORMALIZED ACCESS
TIME VS. LOAD CAPACITANCE

Fig. 11 - NORMALIZED ACCESS
TIME VS. LOAD CAPACITANCE
w

T A =25°C
Vee =4.5V

:;

i=

1.6

TA -25°C
Vee =4.5V

~

'" 1.6

",V

'"w
u
:i 1.4

1.4

C

~ 1.2

L...-V

<

~ 1.0

V
,/

C

........ ~

~ 1.2

:::;

:::;

<

,/

~ 1.0

V

o

o
z

z

·0.8

",0.8

§
j

200

C L • LOAD CAPACITANCE (pFI

~
u

:i

100

Vee. SUPPLY VOLTAGE IV}

'"

u

j

o

100

o

200

C L • LOAD CAPACITANCE (pF)

100

200

C L • LOAD CAPACITANCE (pFI

Fig. 12 - NORMALIZED POWER
SUPPL Y CURRENT VS. FREQUENCY
TA = 25°C

ffi

1.4

~f-

~ ~1.2

I

Vee= 5.5V
V 1N = VINiVlL

wI!:

t:!~

..J

U 1.0

~~
:5z::Jt 0.8
U '"
..y 0.6

~

V

7

10
f. FREQUENCY (MHz)

1-97

~~.nl~~II~i~i
FUJITS11
111~~i!lmllliM~M~11

..

MB81C79A-35
MB81C79A-45

PACKAGE DIMENSIONS
PLASTIC DIP (Suffix: P-SK)
28-LEAD PLASTIC DUAL-IN-L1NE,PACKAGE
(CASE No_: DIP-28P-M04)

,~':':"l: :~,,:cr:M:'::: :0: : ]3~~
1.392~:~~~f35.36~~:;)

1

.300(7.62)TVP

.010±.002
(O.25±0.05)

.1

.050(1.27)MAX
c;::].207(5.25)MAX

-+-l.118(3.0)MIN
.100(2.54)
TVP

I

©1986 FUJITSU LIMITED D28018S·2C

1-98

.020(0.51 )MIN

Dimensions in
inches (millimeters)

~~I~~~~I~lllm~IIIIII~~~lllil~111

MB81C79A-35 FUJITSU
MB81C79A-45 11~~lmlllllllllllll~~II!~lm~~m!111

..

PACKAGE DIMENSIONS
PLASTIC FPT (Suffix: ·PF)
28·LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT·28p·M02)
O(O)MIN
(STAND OFF)

f

J

.339'.008
(8.6'0.2)

d

INDEX

.465'.012
(11.8'0.3)

~::;:;:::;:;::::;:;:::;::;::;:;=n=;:;:::;:;=;:;:::;:;:=;::;~

1

.402'.012

J'"

.006'.002
(0.15.0.05)

Jdllttn:rTJlJ1J1Qri.nP.n__~D

b

--l

A

T..050(1.27)TYP

J

View "A"

.008(0. 181

MAX
.027(0.68)

MAX

.096'.006
(2.45'0.15)

ig~~',;g~

© 1987 FUJITSU LIMITEDF28011S·2C

Dimensions in
inches (millimeters)

1-99

~~~~Mlm~~lm~I~~~I~m~~m~
FUJITSU
~~~~~~~~I~~~MOO~II~OO~~~~

..

MB81C79A-35
MB81C79A..45

PACKAGE DIMENSIONS
CERAMIC LCC (Suffix: -CV)
32-PAD CERAMIC (METAL SEAL) LEADLESS CHIP CARRIER
(CASE No _: LCC-32C-A02)

'PIN NO.1 INDEX

.065(1.65)
TYP

C.040(1.02)TYP
(3PLCS)

.045(1.14)
TYP
.085(2.16)

MAX

.360(9.14)TYP
C.015(0.38)TYP

I

.050±.OOS
(1.27±0.15)

.300(7.62)TYP

* Shape of PIN NO.1 INDEX: Subject to change without notice.
@FUJITSU LIMITED 1987 C32011S·3C

1-100

Dimensions in inches
(millimeters)

MB81 C81 A-3S
MB81 C81 A-4S

..

May 1988
Edition 1.0

262,144 WORDS x 1 BIT HIGH SPEED CMOS STATIC
RANDOM ACCESS MEMORY
The Fujitsu MB81C81A Is 262,144 words x 1 bit static random access memory
fabricated with a CMOS technology.
Since MB81C81A consists of NMOS cells and CMOS peripherals, It Is packaged In 300
mil DIP and reached low power dissipation such as 550 mW.
It uses fully static circuitry and therefore requires no clocks or refreshing to operate.
The MB81C81A Is designed for memory applications where high performance, low cost,
large bit storage and simple InterfaCing are required.

PLASTIC PACKAGE

{D"-"''-~

MB81C81A Is compatible with TTL logic families In all respects; Input, output and a
single +5 V supply.
• Organization: 262,144 words x 1 bit

CERAMIC PACKAGE
(DIP-24C-A08)

• Static operation: No clocks or refresh required
• Fast access time: 35 ns max. (MB81C81A-35)
45 ns max. (MB81C81A-4S)
• Single +5V supply

:Il 0% tolerance

• Separate data Input and output
• TTL compatible Inputs and output
PLASTIC PACKAGE
(. LCC-2414102 )

• Three-state output with OR-tie capability
• Chip select for simplified memory expansion, automatic power down

LCC-24C-A02, See page 11

• All Inputs and output have protection against static charge

PIN ASSIGNMENT

• 300 mil width 24-pln Dual In-Line Package
(Sufflx: Plastic DIP; P-SK, Ceramic DIP; C-SK)
24 pad LCC (Suffix: CV)
24 pad SOJ (Suffix: PJ)

DIP, SOJ

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating

Symbol

Value

Unit

Supply Voltage

Vcc

-0.5 to +7

V

Input Voltage on any pin with to aND

VIN

-3.5' to +7

V

Output Voltage on any pin with to aND

VOUT

-0.5 to +7

V

Output Current

lOUT

±20

mA

Power Dissipation

Po

1.0

W

Temperature under Bias
Storage Temperature

=

L CERAMIC
I PLASTIC

TelAs

-10 to +85

·C

TSTG

-65 to +150
-45 to +125

·C

, DC: min. -0.5 V
NOTE:
Permanent device damage may occur If the above Absolute Maximum
Ratings are exceeded. Functional operation should be restricted to the
conditions as detailed In the operational sections of this data sheet. Exposure
to absolute maximum rating conditions for extended periods may affect
device reliability.

AlB
A17
A13
A12
All
A14
AtB
Ato
A9
DOUT

Vcc
Ao
Al
A2

A3
A4

WI:

A7
As
As
As
DIN

aND

~

This device contains circuitry to protect the
Inputs against damage due to high static
voltages or electric fields.
However. It Is
advised that normal precautions be taken to

~V:!1m~::'~::~~,f!g:~o':1~Tig~:~~!~:

circuit.

Copyright @1988 by FUJITSU LIMITED and Fujitsu Microelectronics, Inc.

1-101

1~~I~~III~~I~I~llllllmlllllllllmm
FUJITSU

Imll~ml~~~mlmlll~M~lml~lmmm

M881C81A-35
M881 C81 A-45

Fig. 1 - MB81C81A BLOCK DIAGRAM

AO
Al

Vee

A2
CELL
ARRAY

GND

COLUMN 1/0 CIRCUITS

DOUT

A3
A4

~~~======I

ROW

256 ROWS
1024 COLUMNS

SELECT

As
As
A7

DIN
INPUT
DATA
CONT.

WE

COLUMN SELECT

TRUTH TABLE

CAPACITANCE

-

WE

Mode

Output

Power

H

X

Not Selected

Hlgh-Z

Standby

L

L

Write

Hlgh-Z

Active

L

H

Read

DouT

Active

.-

(TA - 25°C f -1 MHZ)

Parameter

Symbol

Typ

Max

Unit

Input Capacitance (VIN = 0 V)

CIN

6

pF

Cs

cOs

8

pF

COUT

8

pF

Capacitance (VCs = 0 V)

Output Capacitance (VOUT = 0 V)

1-102

OS

11111111111111111111111111111111111111111111111

FUJITSU

MB81C81A-35
MB81C81A-45

11111111111111111111111111111111111111111111111

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter

Symbol

Typ

Max

Unit

5.0

5.5

V
V

Supply Voltage

Vee

4.5

Input Low Voltage

VIL

-0.5"

0.8

Input High Voltage

VIH

2.2

6.0

V

70

·C

Ambient Temperature
"

Min

TA

0

..

-3.0 V Min. for pulse WIdth less than 20 ns.

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Test Condition

Parameter

Input Leakage Current

VIN = 0 V to Vee
Vee = Max.
CS

Output Leakage Current

Power Supply Current

Standby Current

Symbol

Min

Typ

Max

Unit

III

-10

10

I1A

ILO

-50

50

I1A

= VIH,

VOUT = 0 Vto 4.5 V
Vee = Max.
CS = VIL,
lOUT = 0 mA
Vee = Max.
Cycle = Min.

MB81 C81 A-45

100
mA

lee
120

MB81 C81 A-35

Vee = Min. to Max.
CS~Vee -0.2 V
VIN:'- 0.2 V or
VIN ~ Vee - 0.2 V
Vee = Min. to Max.
CS = VIH

ISB1

15

ISB2

30

0.4

mA

Output Low Voltage

IOL

= 16 mA

VOL

Output High Voltage

IOH

= -4 mA

VOH

Peak Power on Current' 1

Vee = 0 to Vee Min.
CS = Lower of Vee or
VIH Min.

Ipo

V
V

2.4

30

mA

"' A pull-up resistor to Vee on theCS input Is required to keep the device deselected; otherwise, power-on current
approaches Icc active.

1-103

II~~~~~~~~~~~IMMI~~II~~
FUJITSU

~~I~~~I~~III~~I~I~~III~~~III~I~~

MB81C81A-35
MB81C81A-45

AC TEST CONDITIONS

..

Input Pulse Levels:

0.6 V to 2.4 V

Input Pulse Rise and Fall Times:

5 ns

Timing Measurement Reference Levels:

Input:
VIL = 0.8 VIVIH = 2.2 V
Output: VOL = 0.8 VIVOH = 2.2 V

Output Load:

Fig. 2

DOUT

(Including Scope and Jig)
CL: 30 pF for all except tHZ, twz, tLZ and tow.
5 pF for tHZ, twz, tLZ and tow.

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)

Read Cycle Time

*1

tRC

35

Address Access Time
Chip Select Access Time

tACSl

*2

Output Hold from Address Change

tOH

5

tLZ

5

tHZ

0

Chip Selection to Power Up time

tpu

0

to Power Down

tpo

Chip Selection to Output In Low-Z

*3

Chip Deselectlon to Output In Hlgh-Z

Chip

*3

45

ns

35

45

ns

35

45

ns
ns

5

ns

5
20

0

25

ns
ns

0
35

45

*1 All Read cycles are determined from the last valid address transltlonlng to the first address transltlonlng of next cycle.
*2 Addesses valid prior to or coincident with CS transition low.
* 3 Transition Is measured at the point of ± 500 mV from steady state voltage with specified load In Figure 2.

1-104

ns

I I I I I I I I I I I I I I I ~I I I I I I I I I I I
MB81C81A-35
MB81 C81 A-45

FUJITSU
111111111111111111111111111111111111111111111111111111

READ CYCLE TIMING DIAGRAM

..

READ CYCLE: ADDRESS CONTROLLED '1 '2

ADDRESS

DATA OUT

Valid

Previous Data
Valid

Data Valid

READ CYCLE: ~ CONTROLLED '2

ADDRESS

Hlgh-Z

DATA OUT

Icc
Iss

--

b '~l

Data Valid

----~-

50%

~
'1
'2
'3

'4

: Undefined

ELI: Don't Care

CS Is Low.
WE Is high for Read cycles.
transition Is measured at t500mV from ste~ state voltage with specified load in Fig. II.
Addresses valid prior to or coincident with CS transition low.

1-105

..

~~ill~~~II~IIOOII~I~~~~
FUJITSU
mlllillli~~~~IIIIIOOIOOI~~i~~

MB81C81A-35
MB81C81A-45

AC CHARACTERISTICS

(Continued)
(Recommended operating conditions unless otherwise noted.)

Write Cycle Time

two

35

45

ns
ns

30

40

tAW

30

40

ns

tAS2

0

0

ns

Write Pulse Width

twp

25

30

ns

Data Valid to End of Write

Address Valid to End of Write

tow

20

25

ns

Write Recovery Time

tWR

5

5

ns

Data Hold Time

tOH

0

Write Enable to Output In Hlgh-Z

*1

twz

0

Output Active from End of Write

*1

tow

0

20

0
0

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE: WE CONTROLLED *2
~------------------two--------------------~

ADDRESS

DATA IN

DATA OUT

. *1 Transition Is measured at the point of ±500 mV from steady state voltage.
* 2 CS or ~ must be high during address transition.

1,;,,106

25

ns
ns

MB81C81A-35
MB81 C81 A-45

11111111111111~1~~~I~III~lm~I~IIIIII~111111
FUJITSU
1111111111111~lllllllllllllilllllll~I~!~lilll~

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE:

CS CONTROLLED

..

'1
'2

~---------------twc~------------~

Valid

ADDRESS

~-----------tAW----------~
~--------tcw--------~

~-----tDw

DATA IN

DATA OUT

____ ~ ___________
~<: ~~

~

m

: Undefined

H~19_h-_Z_____________

f2l: Don't Care

'1

~ OR

'3

Transition Is measured at :t500mV from steady state voltage with specified load In Fig. II.

must be high during address transitions,

'2 All write cycle are determined from last valid address transltlonlng to the first address transltlonlng of next cycle.

1-107

1IIIWIIIIMIIIMWlilmllllllM
FUJITSU
IIIIIIIIMIIIIIIWWmllMWIIW

MB81C81A-35
MB81C81A-45

PACKAGE DIMENSIONS

..

24-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-24P-M03)

.300 •. 010
(7.62.0.25)

.010 •. 002
(0.25.0.05)

.172(4.36)MAX

.118(3.0)MIN
.100(2.54)
TYP

I. .1

.018>.003
(0.46>0.08)

.020(0.51 )MIN
Oimensions in
inches (millimeters)

© FUJITSU LIMITEO 1987 D24017S·2C

11111111111111111111111111111111111111111111111

MB81C81A-35
MB81 C81 A-45

FUJITSU
11111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS (Continued)

..

24-LEAD CERAMIC(CERDIP) DUAL IN-LINE PACKAGE
(CASE No: DIP-24C-A08)

__ -:."":.~"

1." "
U

"""'=;=O:~'l

to

~

'~"''''1JJ::::: :~~ ]~~;~, ~=*I=~

.300±.010
17.62±0.251

I

1.187+.012
130.15±0.301

.1

l.olo±.002
10.25±0.051

.05011.27IMAX

.018~:gg~

10.46~g:~~1
1.100127.94IREF
Dimensions in
inches (millimeters)
©FUJITSU LIMITED 1986 D2403OS·2C

1-109

1II111II1II1111II1II11111m~IIOO1IIII11IIII
FUJITSU
1lIIlllMIIIIIIIIIIIIII~lllmllllllllill

MB81C81A-35
MB81 C81 A";'45

PACKAGE DIMENSIONS (Continued)
24·LEAD PLASTIC LEADED CHIP CARRIER
(CASE No.: LCC·24P·M02)
~

I

o

'''1""

~D~

I~ t-.09112.311
NOM

.550(13.97IREF

•. 615±.005(15.62.0.131

I .

.025(0.641
MIN
.144(3.661
MAX

Details of "A" partM032(0.81IMAX

'=r-~~~'*rFl:nFnFnFnFnFn~\h
'-1
Q

005

(8.64± 0.131
.273±.020
(6.93.0.511

.300(7.621

.050 •. 005
(1.27±0.131

.102(2.601
NOM

.004(0.101

1
'II: This dimensiQn includes resin protrusion. (Each side: ,Q06(O.15)MAX.

1-110

)11

I

I.I;o;:Fr:r-FFFIFND;::E;=;Xe=;e=;e=;""'i9""'i9""'i9""'i9'ff?1_T

01988 FUJITSU LIMITED C240629·1C

e:

I

. I <
---I. .017±.004
• (o.43±0.1 01

Dimensions in
inches (millimeters)

11111111111111111111111111111111111111111111111

MB81C81A-35
MB8l C8l A-45

FUJITSU
11111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS (Continued)

A12
All
A14
A15
A,a
A9

l:~
.J

..

A13 An A16 Vee Ao

;; II

Ii

'2

U
1

4 -;

U
24

j
2322 ~:

Ii

Al

21 L. A2

5
6
7

20 [: A3
:1
TOP
19 r: A4
:1
VIEW
18 [: A7
:1 8
17 r: A6
:1 9
16 [: As
DOUT :1 10
11 12 13 14 15
n n n n n

M

GND CS DIN A8

CERAMIC PACKAGE
(LCC-24C-A02)

24-LEAD CERAMIC LEAD LESS CHIP CARRIER
(CASE No.: LCC-24C-A02)
.260(6.60)
TYP
A.012(0.30)TYP
(4PLCS)

I_
I

.045( 1.14)
TYP

~~---+--t

~
INDEX

n

.085(2.16)
TYP

,5501.010
(13.9710.25)

A.008(0.20)TYP
(28PLCS)

.350±.010
(8.89±025)
• Shape of PIN NO.1 INDEX: Subject to change
without notice.

e

.045(1.14)
TYP
.065(1.65)
TYP
.083(2.11)
MAX

FUJITSU LIMITED 1987 C24012S.1C

TYP
Dimension in
inches (millimeters)

1-111

High-speed CMOS SRAMs

..

1-112

Static RAM Data Book

00

October 1989

FUJITSU

Edition 4.0

DATA SHEET

MB81 C84A-351-45
CMOS 256K-BIT HIGH SPEED SRAM

..

65,536 WORDS x 4 BITS HIGH SPEED STATIC RANDOM
ACCESS MEMORY WITH AUTOMATIC POWER DOWN
The Fujitsu MBa 1C84A is a 65,536-words by 4-bits static random access memory labricated
with a CiviOS siiicon-gsl8 process. To maKe power dissipation tower, peripherai Circuits
consist 01 CMOS technology, and to obtain smaller chip size, cells consist 01 NMOS
transistors and resistors. MBal C84A has 300mil plastic DIP and 300mii plastic small ouUine
J-lead (SOJ) as package option. Tha memory utilizes asynchronous circuiUy and requires
+5V power supply. All pins are TTL compatible.
The MBal C84A is ideally suitad lor use in lalge computer systems and other applications
where last access time, large capacity and ease 01 use are required. All dellices oller the
advantages 01 low power dissipation, low cost and high parformance.
•

•

Organization: 65,536 words x 4 bits
1M = lACs = 35ns max.(MB81 C84A-35)
Fast access time:
1M =lACS =45ns max. (MBal C84A-45)
Completely static operation: No clock required

•

TTL compatible inputs/outputs

PLASTIC PACKAGE
DIP-24P-M03

• ThrelrState output

PLASTIC PACKAGE
LCC-24P-M02

•

Common data input/output

•

Single +5V power supply, ±10% tolerance

•

Low power standby: 660mW max. (Active)
165mW max. (Standby, TTL level)
83mW max. (Standby, CMOS level)

•

Standard 24-pin PLASTIC DIP package (300mil): Suffix -P-SK

•

Standard 24-pin PLASTIC SOJ package (300mil): Suffix -PJ

PIN ASSIGNMENT

ABSOLUTE MAXIMUM RATINGS (see NOTE.)
Rating

Symbol

Value

Unit

At5

va;

IoIJ

At.

At

At3

A2

At2

AS

Att

A4

AtO

Supply Voltage

Va;

-0.5 to +7.0

V

Input Voltage

VIN

-3.0 to +7.0

V

AS

Output Voltage

VOUT

-0.5 to +7.0

V

AS

Output Current

lOUT

±20

mA

PD

1.0

W

Temperature Under Bias

TBIAS

-10 to +85

OC

Storage Temperature Range

TSTO

-45 to +125

OC

Power Dissipaiton

NOTE:

Permanent dellice damage may occur il the above Absolute Maximum
Rallne. are exceeded. Functional operation should be restricted to the
conditiOns as detailed in the operational sections 01 this data sheet. Exposure to
absolute maximum rating conditions lor extended periods may allect dellice
reliability.

A1

1103

AIJ

1/02

OND

We

IIOt

::'~ueCO::,'"i~~~~

=:-

~="r.l~:

However, k II acMIed that normal precaudons be taken 10
avoid application 01 any vollage hlghot' Ihan maxllTlJm rated
voIag.. to this high Irrpodanoo drcun.

Culok Pro™ 10 a trademark of FUJrrsU LIMITED

Copyrlght~1II!7 Ill' FUJITSU LIMITED and Fullsu MlcrooIodronlc:o, Inc.

1-113

MB81 C84A-35
MB81 C84A-45

Fig. 1 - MB81C84A BLOCK DIAGRAM

..

- - 0 Vee
Ao

---0

GND

•

Al
A2

A3

ROW
SELECT

MEMORY CELL ARRAY
x 256 COLMNS x 4

•

256 ROWS

AI.

A5

•

As

A7

•

•
VO,

o---~==I

V02

o---~c::=1

1103

o---~==I

110.

o-----tdc::=1 BUFFER
I/O

•

COLMUN & I/O CIRCUITS

COLMUN SELECT

CsO-_....cIr,

A9

As

AlO A11

A12 A13 A14 A15

TRUTH TABLE

POWER
CIRCUIT

MODE
H

x
H

OUTPUT

POWER

NOT SELECTED

HIGH-Z

STANDBY

WRITE

HIGH-Z

ACTIVE

READ

OOUT

ACTIVE

CAPACITANCE (TA= 2soC,f: 1MHz)
Parameter

=OV)
Input Capacitance (VilS =OV)
Input Capacitance (VIN =OV)

Output Capacitance (VIJO

1-114

Symbol

Max

Unit

CoUT

Min

8

pF

CCS

8

pF

CIN

6

pF

Typ

MB81 C84A-35
MB81 C84A-45

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Symbol

Min

Typ

M••

Supply VOltage

P.r.m....

Vro

4.5

5.0

5.5

V

Ambient Temperature

TA

0

70

·C

n,.. ,..u

A 1:1 A

Unit

"'TE:I:II~TI"'~

U V VI I _ n _ v ..... J .. I~ •• v~

(Recommended operating conditions unless otherwise noted.)
Par.meter

Symbol

Min

Max

Unit

Te.t Condllton

Standby Supply Current

IS91

15

mA

Vro = Min. to Max.
15§ = Vro - 0.2V

Standby Supply Current

IS92

30

mA

VIN = Y,N or VIL
15§ = VIH, Vro = Min. to Max.

Operating Supply Current

lro

120

mA

Cycle = Min., lOUT = OmA, CS = V,L

Input Leakage Current

III

-10

10

!IA

V,N=OtoVro

Output Leakage Current

ILVO

-50

50

!IA

CS = VIH, VOUT = 0 to Vro

Input Low Voltage

V,L

-2.0'1

O.B

V

S.O

V

Input High Voltage

VIH

2.2

Output High Voltage

VOH

.24

Output Low Voltage

VOL

0.4

V

IOH=-4mA

V

IOL=BmA

Note: All voltages are referenced to GND
'1 -2.0V Min. for pulse width less than 20 ns. (VL min. = -<><~1'"-

___

~

D_AT_AV_A_LlD_ _ _

~

Undefined

'!wwl

Don'l Car.

Nole: '1 ~ or~ must be high during address transitions.
'2 If CS goes high simultaneously with WE high, the output remains in high impedance state.
'3 All Write cycle timings are referenced from the last valid address to the first transitioning address.
'4 If CS is in the READ mode during this period, 110 pins are in the output state so that the input signals of opposite phase to the
outputs must nol be applied.

1-118

MB81 C84A-35
MB81 C84A-45

TYPICAL CHARACTERISTICS CURVES
Fig. 3 - OPERATING SUPPLY CURRENT
VS. SUPPLY VOLTAGE

Fig. 4 - OPERATING SUPPLY CURRENT
VS. AMBIENT TEMPERATURE

b::1

,

u-

:.!l~

/'

f.O

tllill
....

::i--'


0C/)

V

.........

0.9

........... r-

Z

0.8

4.5

5.0

5.5

020408080

TA, AMBIENT TEMPERATURE (DC)

Vee, SUPPLY VOLTAGE (V)

Fig. 5 - STANDBY SUPPLY CURRENT
VS. SUPPL Y VOLTAGE

>m
0
z

I

~
o

TA _ 25"C

Z

f.2



1.f

~~

1.0

.

0.9

;;;

0.8

--'0

a:Q.
0Q.
z::>
";C/)

Fig. 6 - STANDBY SUPPLY CURRENT
VS. AMBIENT TEMPERATURE

!!l

.......... t::7'
/'

j51-

IS82

/

l.?: ~

vcd_

5.0V

1.2

C/)Z

fiJ~
~gj

IS8f

1.1

--'0

~~

~&
Z:::l

.

";C/)

1.0

~

~

"-

0,9

!!l

IS82

~ISB1

a.•

!!l
4.5

5.0

20

5.5

40

80

80

TA, AMBIENT TEMPERATURE (DC)

Vee, SUPPLY VOLTAGE (V)

Fig. 7 - OPERATING SUPPLY CURRENT
VS. FREQUENCY

TA~25"C

Cl

~

1.4

vee- 5.0V

VIN _ 2.4VIO.6V

~I­

wffia:

1.2

:.!l~

f.O

Q..

Oa:
0::>

~~

O.S

Jf

a.•

a:::::>
0C/)
z

V
t-""

5

10

50

100

f, FREQUENCY (MHz)

1-119

MB81C84A~35

MB81 C84A-45

TYPICAL CHARACTERISTICS CURVES (Continued)
Fig. 8-"H" LEVEL OUTPUT VOLTAGE
vs. "H" LEVEL OUTPUT CURRENT

'-.....

4.0

f:::l
Q.

f-

5~

3.8

We>

3.6

--'w

t1ij5
--'--,
it:§2

3.4

:£

g

Fig. 9 - "L" LEVEL OUTPUT VOLTAGE
vs. "L" LEVEL OUTPUT CURRENT

~A-25J

VCC-5.0V -

"

"

0.4

!;
Q.
!;
_
--'W

........

~

0.3

We>
Wf-

>e(

0.2

--'--'

~g

0.1

g

-6

-4

10

Fig. 11 - ACCESS TIME

I

l

Vcc _5.0V

TA-25"C
1.2

cW

C

~i=

~ ..........

;/

~W 1.1

~~

lACS

~

gj

~~
ZW

1.0

!jO

0.9

g~

0.9

i

0.8

i

0.8

-0

:se(

4.6

r--;::

5.0

./'

1.0

-0

5.5

20

Fig. 12 - ACCESS TIME

I

I

TA _ 25"C
VCC_5.0V

c

W

~W

1.1

~ gj
zw

1.0

~~

0.9

~~

40

60

80

TA, AMBIENT TEMPERATURE (OC)

vs. LOAD CAPACITANCE
1.2 -

~S

/'

'/

ZW

Vee, SUPPLY VOLTAGE (V)

,V

...... ...........~-

-0

0.8

o

50

100

150

200

CL, LOAD CAPACITANCE (pF)

1-120

20

vs. AMBIENT TEMPERATURE

1.2

1.1

15

IOL, "L" LEVEL OUTPUT CURRENT (rnA)

Fig. 10- ACCESS TIME
vs. SUPPLY VOLTAGE

--'::;;

'/

v

"

L

-6

IOH, "H" LEVEL OUTPUT CURRENT (rnA)

W
t::!W

I

TL25"C
VCC-5.OV

O{ ------t-A-Av-A-L-
D--------------~

~

tRC"2

A,.,""
DOUT

,-:..

-=

==.-1.

PREVIOUS DATA VALIll)()(

DATA VALID

tOH~

~

READ CYCLE II: CS CONTROLLED"4
ADDR ESS

~~-:-:.-:.-:.-:.-:.-:.-:.-:.-:.-:.-V--A--L--I-D-=-tR-C--_-_-_-_-_-_-_-_-.:_-.:_-_-_-.:;(..J_____

DOUT

SUPPLY

CURRENT_I~SB~_______

DATA VALID

ICC
~ : Undefined

Note: *1
*2
*3
*4
*5

1-126

ns

WE is high for Read cycle_
All Read cycle timings are referenced from the last valid address to the first transitioning address.
Device is continuously selected, CS = V IL'
Address valid prior to or coincident with CS transition low.
Transition is specified ±500mV from steady state voltage with specified load II in Fig. 2.

ns

1111111111111111111111111111111111111111111111111

MB B1CB6-55
MB 81C86-70

FUJITSU
1111111111111111111111111111111111111111111111111

..

WRITE CYCLE"'2
MB 81C86-55
Parameter

MB 81C86-70

Symbol

Unit
Min

Max

Min

Max

!

\A!:-:~:: !>J'~!~ T!~~· 3

t·,t.;~

!i!i

70

Address Valid to End of Write

tAW

45

50

Chip Select to End of Write

tcw

45

50

ns

Data Valid to End of Write

tDW

25

30

ns

Data Hold Time

tDH

5

5

ns

Write Pulse Width

twp

30

35

ns

Address Setup Time

t AS

5

5

ns

Write Recovery Time '4

tWR

5

5

Output High-Z from WE's

twz

0

25

Output Low-Z from WE's

tow

5

30

ns
ns

ns

0

25

ns

5

35

ns

WRITE CYCLE TIMING DIAGRAM'!'2
WRITE CYCLE I: WE CONTROLLED

DOUT

I8:EI : Undefined
Note: *1 CS or WE must be high during address transitions.
*2 If CS goes high simultaneously with WE high, the output remains in high impedance state.
*3 All Read cycle timings are referenced from the last valid address to the first transitioning address.
*4 tWR is defined from the end point of WR ITE Mode.
*5 Transition is specified ±500mV from steady state voltage with specified load in Fig. 2.

n

1-127

m~llllmllllmml~~lllmlllll~~mllrnll
FUJITSU MB 81C86-55

1IIIIIIIIIIIIIIIImllmlllllllllllll~~II~~ml MB 81C86-70

..

WRITE CYCLE II: CS CONTROLLEO'!'2
~

_______________

twc~'3~

______________

~

ADDRESS

f-------twP,-----.,

J-------tow-----<-<
DATA VALID

High-Z

DOUT

~ : Undefined

Note: *,
*2
*3
*4
*5

1-128

CS or WE must be high during address transitions.
If CS goes high simultaneously with WE high, the output remains in high impedance state.
All Write cycle timings are referenced from the last valid address to the first transitioning address.
tWR is defined from the end point of WR ITE Mode.
Transition is specified ±500mV from steady state voltage with specified Load n in Fig.2.

1111111111111111111111111111111111111111111111111

MB 81C86-55
MB 81C86-70

FUJITSU
1111111111111111111111111111111111111111111111111

..

PACKAGE DIMENSIONS
(Suffix: -C)

28-LEAD CERAMIC (METAL SEAL) DUAL IN-LINE PACKAGE
(CASE No.: DIP·28C-A07)

I

.05011.271
REF

.590114.991

~==+j=]~'

INDEX
AREA

.00810.201
.01210.301

~
~ Ul

f

---.J I

.20015.08IMAX

r=;..---t

.12013.051
-----f.---l.15013.811

.09012.291
.11012.791

.04611.171
.05411.371

--II

.01510.381
.02310.581

.04011.021
.06011.531

.1300133.02IREF
©19S6 FUJITSU LIMITED D28019S-1C

Dimensions in

inches (millimeters)

1-129

..

,llllllllllllllllllllllllllllmlllllllllllllllll
FUJITSU
1111111111111111111111111111111111111111111111111

MB 81C86-55
MB 81C86-70

PACKAGE DIMENSIONS
(Suffix: ·CV)

32·PAD CERAMIC (METAL SEAL) LEADLESS CHIP CARRIER
(CASE No.: LCC-32C-A02)

'PIN 1 INDEX

.360(9.14)TVP
C.015(O.38)TVP

/

nhf-l----~
.445(11.30)
.460(11.68)
.300(7.62)TVP

Dimensions in inches
(millimeters)

*Shape of Pin 1 index: Subject to change without notice
©1985 FUJITSU LIMITED C32011S

1-130

MB8289-25
MB8289-35
April 1989
Edition 1.0

32K X 9-BIT STATIC RANDOM ACCESS MEMORY
WITH PARITY GENERATOR AND CHECKER
The Fujitsu MB8289 is 32768 words X 9 bits high speed static random access
memory with parity generator and checker, fabricated with CMOS technology.
this device is assembled in 300 mil DIP and has such small power dissipation
as 605mW max.
All pins are TTL compatible and single 5 volt power supply is required.
A separate chip select (CS,) pin simplifies multipackage systems design. It
permits the selection of an individual package when outputs are OR·tied,
and furthermore on selecting a single package by CS, the other deselected
packages automatically power down.
All devices offer the advantages of low power dissipation, low cost, and high
performance.
•

Organization: 32768 words x 9
bits
• Static operation: no clocks or
timing strobe required
• Fast access time:
tAA = tAcs, = 25ns max,
tAcS2 = 14nsmax (MB8287-25)
tAA =t ACS , =35ns max,
tACS2 = 15ns max (M 88287·35)
• Low power consumption:
715mW max. (Operating) for 25ns
605mW max. (Operating) for 35ns
138mW max. (TTL Standby)
83mW max. (CMOS Standby)
• Single +5V supply ±10% tolerance

PLASTIC PACKAGE
(OIP·32P-M02)

•

TTL compatible inputs and outputs
• Three-state outputs with OR-tie
capability
• Chip select for simplified memory
expansion, automatic power down
• Internal parity generator and
checker.
• All inputs and outputs have pro·
tection against static charge
• Standard 32·pin DIP package
(300 mil): (Suffix: P-SK)
• Standard 32'pin FPT package
(450 mil): (Suffix: PF)

PLASTIC PACKAGE
(FPT-32P-M02)

PIN ASSIGNMENT

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating

Su pply Vol tage
Input Voltage on any pin
with respect to GN D

Symbol

Value

Unit

Vcc

-0.5 to +7

V

V ,N

-3.5 to +7

V

Output Voltage on any I/O
pin with respect to GND

V OUT

-0.5 to +7

V

Output Current

lOUT

±20

mA

Power Dissipation

Po

1.0

W

Temperature Under Bias

T sJAS

-10 to +85

·C

Storage Temperature Range

TSTG

-45 to 125

·C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATI NGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

A5

vcc

A4

As

A3

A7

~

As

A,

Ag

Ao
A'2
A '3

A,o
A"

A'4

CS,

N.C.

DE

WE

CS2

1/09

1/0 ,
1/02
1/0 3
1/04

liDs
1/07
1/0 6
1/05

GND~~______~_GNDQ

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi·
mum rated voltages to this high impedance
circuit.

1-131

..

1!11~lm~~~~lmlll~I~OOlli~ml
FUJITSU

MB8289-25

OOI~lmlllllill~ll~nlliMllinm MB8289-35

..

Fig. 1 - MB8289 BLOCK DIAGRAM

~Vcc

-GND
ROW
DECODER

ADDRESS
BUFFER

I/O GATE
&
COLUMN DECODER

ADDRESS
BUFFER

-GNDQ

MEMORY CELL ARRAY
256 x 128x9

r---------------L-~------------_T..J

Cs,~---,-"""

I/0,

CS2--,----,L

1/°3
1/°2

1/°5
1/04

1/°7
1/06

I/O g
I/OB

TRUTH TABLE

CAPACITANCE

(TA

CS,

cs,

WE

DE

SUPPLY CURRENT

I/O STATE

H

x

X

X

STANDBY

Is,

HIGH·Z

L

L

X

X

DESELECT

Icc

HIGH·Z

L

H

H

H

DouT DISABLE

Icc

HIGH·Z

L

H

H

L

READ

Icc

DOUT

L

H

L

X

WRITE

Icc

D,"

MODE

= 25°C, f = 1MHz)

Parameter

Max

Unit

VIN =OV

CI ,

8

pF

Input Capacitance (Other Input)

VIN = OV

C I2

7

pF

I/O Capacitance

VI/O = OV

CliO

8

pF

Input Capacitance (CS"

1-132

Condition
C~,

OE, WE)

Symbol

Min

Typ

1111111111111111111111111111111111111111111111111111

MB8289-25
MB8289-35

FUJITSU
1111111111111111111111111111111111111111111111111111

..

RECOMMENDED OPERATING CONDITIONS
(Referenced to GNDI
Symbol

Min

Typ

Max

Supply Voltage

Parameter

Vee

4.5

5.0

5.5

V

Ambient Temperature

TA

0

70

°c

Unit

DC CHARACTERISTICS
(Recommended operating conditions unless otherside noted'!
Parameter

Symbol

Test Conditions
CS,
V 1N

IS82

CS, = V 1H

lee

lOUT = OmA. CS 1 = V1L
Cycle = Min.

Standby Supply Current

I
I

Operating Supply
Current
Input Leakage Current

Output Leakage current

Min

Vec-0.2V
Vec-0.2V or V 1N ~ 0.2V

V 1N ~0.2V

25ns
35ns

Z
Z

158 ,

V 1N

I Lilo

CS, = V 1H = or C~ = V 1L or
WE = V 1L or OE = V 1H •
VI/a = OV to Vee

Unit

15

mA

25

mA

130
mA

110

= OV to Vee

ILl

Max

-5

5

p.A

-5

5

p.A

Input Low Voltage

V 1L

-2.0'1

O.S

V

Input High Voltage

V 1H

2.2

6.0

V

Output High Voltage

V OH

IOH = -4mA

Output Low Voltage

VOL

IOL = SmA

0.4

V

2.4

V

Note: ., -2.0V Min. for pulse width less than 20ns. (V 1L min. = -0.5V at DC level)
All voltages are referenced to GND.
Fig. 2 - AC TEST CONDITIONS
•

Input Pulse Levels:

O.6V to 2.4V

•

Input Pulse Rise & Fall Times:

3ns (Transient between O.BV and 2.2V)

•

Timing Reference Levels:

•

Input:

V 1L "" O.SV, V 1H == 2.2V

Output:

VOL"" O.BV, V OH "" 2.2V

Output Load:
+5V

1

DOUTo-----~----~

0/01

r

C '1

Load I

480n

255n

30pF

Load II

480n

25sn

SpF

*1 Including Scope and Jig Capacitance

Parameters Measured

except tLZ, tHZ' twz. tow. tOLZ and tOHZ

J
J

I
1-133

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

MB8289-25
MB8289-35

AC CHARACTERISTICS
READ CYCLE"

(Recommended operating conditions unless otherwise noted)
MB8289-25
Parameter

MB8289-35

Snymbol

Unit
Min

Max

25

Min

Max

Read Cycle Time

t RC

Address Access Time '2

tAA

25

35

ns

CS, Access Time*3

t Acs ,

25

35

ns

C~ Access Time*3

t ACS2

14

15

ns

OE Access Time

tOE

12

14

ns

Output Hold from Address Change

tOH

3

3

ns

Output Active from CS, '4'5

tLZ'

5

8

ns

Output Active from C~ '4'5

tLZ2

2

3

ns

Output Active from OE'4'5

tOLZ

2

3

ns

Output Disable from CS, '4 '5

tHZ1

1

15

1

15

ns

Output Disable from C~ '4'5

tHZ2

1

15

1

15

ns

Output Disable from OE'4'5

tOHZ

1

15

1

15

ns

35

ns

..

Note: *1
*2
*3
*4
*5

1-134

WE is high for Read Cycle.
Device is continuously selected, CS, = V1L , C~ = V 1H and OE = V 1L .
Address valid prior to or coincident with CS, transition low, C~ transition high.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

~lmllllllmlml!llllllllllmlmlllll~~11

MB8289-25 FUJITSU
MB8289-35 ~lllllllllllmllllll~lllllllmlll~~~lllmlll

..

READ CYCLE TIMING DIAGRAM"1
READ CYCLE: ADDRESS CONTROLLED*2

. - - - - - - - t R c - - - - - -....·~1

...
1

VALID

ADDRESS

DATA OUT

PREVIOUS DATA VALID

READ CYCLE: CS1 , C~ CONTROLLEO*3

ADDRESS

1/0

VALID

HIGH-Z

•

: Don't Core

~

: Undefined

Nota: "1 WE is high for Read Cycle_
*2 Oevice is continuously selected, CS 1 = VIL , ~ = VIH and OE = VIL •
*3 Address valid prior to or coincident with CS1 transition low, C~ transition high.
*4 Transition is specified at the point of ±500mV from steady state voltage.
*5 This parameter is specified with Load II in 'Fig. 2.

1-135

..

1IIIIIIIIIIIIIIIIIImll l l lWl l l l l il mm

FUJITSU

MB8289-25

IIIIIIIIIIIIIIIII~IIIIIIII~I~~~I~IIIII~~II MB8289-35

AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted)

WRITE CYCLE·1
MB8289-25
Parameter

MB8289-35

Symbol

Unit
Min

Max

Min

Max

Write Cycle Time '2

twc

25

35

ns

Address Valid to End of Write

tAw

18

28

ns

CS1 to End of Write

tCWl

16

26

ns

C~

tCW2

13

20

ns

Data Setu p Ti me

tow

8

12

ns

Data Hold Time

tOH

0

0

ns

Write Pulse Width

twp

15

20

ns

Write Recovery Time '3

tWR

0

0

ns

Address Setup Time

t AS

0

0

ns

Output Low-Z from WE'4'5

tow

0

0

ns

Output High-Z from WE'4'5

twz

0

to End of Write

Note: *1
*2
*3
·4
*5

1-136

8

0

14

ns

If CS goes high simultaneously with WE high. the output remains in high impedance state.
All Write Cycles are determined from the last address transition to the first address transition of next address.
tWR is defined from the end point of Write Mode.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig_ 2.

11111111~~mllllllllllllllllllllm~lmlll!~1

MB8289-25 FUJITSU
MB8289-35 11~~~~mlll~~~~~~~lm~~MI~1

..

WRITE CYCLE TIMING DIAGRAM *1,*6,*7
WRITE CYCLE No.1 (WE CONTRORRED)

ADDRESS

Cs1

1/0

l1li :
Note: *,
*2
*3
*4
*5

Don't el..

~:

Undefined

If CS goes high simultaneously with WE high, the output remains in high impedance state.
All Write Cycles are determined from the last address transition to the first address transition of next address.
tWR is defined from the end point of Write Mode.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

1-137

mll~~~I~II~~III~mlm~~~m~~
FWITSU
IllmlmmIOO~~g~OO~~m~

MB8289-25
MB8289-35

WRITE CYCLE TIMING DIAGRAM *1,*6,*7
WRITE CYCLE No.2 (CS 1 , CS2 CONTROLLED)

ADDRESS

CSI

WE

110

•

Note: *1
*2
*3
*4
*5

1-138

: Don't Care

~: Undefined

If CS goes high simultaneously with WE high, the output remains in high impedance state.
All Write Cycles are determined from the last address transition to the first address transition of next address.
tWR is defined from the end point of Write Mode.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

1111111111111111111111111111111111111111111111111111

MB8289-25
MB8289-35

FUJITSU
1111111111111111111111111111111111111111111111111111

..

PACKAGE DIMENSIONS
32-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP·32P-M02)
15°MAX

.~_l

t

..-F-

.30017.62)

j

Tr

.010+.0021
1O.25±0.05)

1~)1
J~.20715.25)MAX
MAX

-0

IJ I Ilf If U

I•• 1.10012.54) ~ ~
TYP

11.27~g.30)

-0

--il ..

018±.003
10.45±0.OS)

=P12513.1S)MIN
.02010.511
MIN
Dimensions in
inches (millimeters)

© 1988 FUJITSU LIMITED D32009S-1C

1-139

~~~llm~~mlml~~lmlllmllm~~ool
FUJITSU MB8289-25
11111~IIWIWIIW~~OOIW~lllmll~~ .. MB8289-35

PACKAGE DIMENSIONS (continued)
32·LEAD PLASTIC SMALL OUTLINE PACKAGE
(CASE No.: FPT·32P·M02)

.- l-

I

f

O(O)MIN
(STAND OFF)

I

.339 •. 008

.402±.0 12
110.20'0.30)

"[r

.031 •.008
1(0.80>0.201

......

~

TYP

.006>.002
(0.15>0.05)
.098(2.501

if .

--u
.006(0.15)

!-l-

MAX

Detail of "A" part

.~

.007(0.18)
MAX

.750(19.05)REF

.027(0.68) Dimensions in
MAX

© 1988 FUJITSU LIMITED F32004$-1C

1-140

inches (millimeters)

Section 2

High-S~eed

BiCMOS SRAMs -

I

At a Glance

I

Maximum

I Page

Access

Package
Options

I

Device

TIme (ns)

Capacity

2--3

MB828001-25

1048576 bits
(1048576w x lb)

28-pin

Plastic

Lee

--35

25
35

2-11

MB828005--25
--35

25
30

1048576 bits
(262144w x 4b)

28-pin

Plastic

Lee

2-19

MB82BOO6-25

25
35

1048576 bits
(262144w x 4b)

32-pin

Plastic

Lee

15
20

65536 bits
(65536b x lb)

22-pin Plastic
24-pin Plastic

Lee

-20

15
20

65536 bits
(16384w x 4b)

22-pin Plastic
DIP
22-pad Ceramic Lee

2-45

MB82B75-15
-20

15
20

65536 bits
(16384w x 4b)

24-pin Plastic
DIP, Lee
28-pad Ceramic Lee

2-55

MB82B79-15

15
20

73728 bits
(8192w x 9b)

28-pin

Plastic

DIP, FPT

-20
2-65

MB82B81-15
-20

15
20

262144 bits
(262144w x 1b)

24-pin

Plastic

DIP,

Lee

2-73

MB82B84-15

15
20

262144 bits
(65536w x 4b)

24-pin

Plastic

DIP,

Lee

--35
2-27

MB82B71-15

-20
2--37

MB82B74-15

-20

DIP,

Lee

2-1

Ell

High-speed BiCMOS SRAMs

2-2

Staffe RAM Data Book

cO

October 1989
Edition 1.0

FUJITSU

DATA SHEET

MB82B001-251-35
1M BIT HIGH SPEED BI-CMOS SRAM
1,048,576 WORDS X 1 BIT HIGH SPEED BI-CMOS
STATIC RANDOM ACCESS MEMORY
...., ... __ ..... "' ........ ,........ ............ _v. . "'v,
___....-' ;::,__'" , un ;, ..•.c;u..,.....____
'.\;Q. ....u
,.~

,~

.L·~_

~

lilt;!' '--UJIl;::'U IYIUOc;.UV'V I .;:> I ,V-'U."""

.-l_~

___________

.~_L-'

__ .. _.....I

ICU .......... ,1 0l........ 'U;:.., 111<:1"'V'1 IU ...

••• :a.L

.... 'u,

a Bi-CMOS process technology. To make power dissipation lower and high speed, peripheral
circuits consist of Bi-CMOS technology, and to obtain smaller chip size, cells consist of NMOS
transistors and resistors.
The memory utilizes asynchronous circuitry and may be maintained in any state for an indefinite
period of time. All pins are TTL compatible, and a single 5 volts power supply is required. The
MB82BOOl has 400mil plastic small ouHine J...jead(SOJ) as package option.
The MB82BOOl is ideally suited foruse in dataprocessing systems and other applications where
fast access time and ease of use are required. All devices offer the advantages of low power
dissipation, low cost and high peformance.

•

Organization: 1,048,576 words x 1 bit

•

Static operation: No clocks or refresh required

•

Fast access time:

•

Single +5V(±10%) power supply with low current drain

25ns max. (MB82BOOl-25)
35ns max. (MB82BOOl--35)

Active operation = 120mA max.
Standby operation = 15mA max. (CMOS level)
Standby operation = 25mA max. (TTL level)
•

Separate data input and output

•

TTL compatible inputs and output

PLASTIC PACKAGE
LCC-28P-M05

•

Chip select for simplified memory expansion, automatic power down

•

All inputs and output have protection against static charge

•

400 mil width 28-pin SOJ package (Suffix: -PJ)

PIN ASSIGNMENT

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating

Symbol

Value

Unit

Supply Voltage

Vee

...{l.5 to +7.0

V

Input Voltage on any pin with to GND

V IN

...{l.5 to +7.0

V

Output Voltage on any pin with to GND

V OUT

...{l.5 to +7.0

V

Power Dissipation

PD

Output Current

lOUT

1.0

W

±20

mA

Temperature under Bias

T BIAS

-10 to +85

Storage Temperature

TSTG

-40 to +125

NOTE:

A
A
A
A
A
A

Itc

NC

A
A
A
A
A
A

A
A
A
A
~

A
A
A
A

WE
GND

NC

llJII
CS

°c
°c

Permanent device damage may occur if the above Absolute Maximum
Ratings are exceeded. Functional operation should be restricted to the
condibons as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.

J~~~~C;u~:aih~~r~!~~ t~::: :r8 !~~~'~d:~

However, it is advised that normal precautions be taken to
avoid application of any voll:age higher than maximJm rated
voll:ages to this high i~ance circuit.

Copy'~ht© 1989 FUJITSU LIMITED

2-3

MB82BOO1-25
MB82BOO1-35
Fig. 1 -

MB82BOO1 BLOCK DIAGRAM

Ao
A,

Vee

•

A2

GND

A3
A.

CELL
ARRAY

•

ROW
SELECT

512 ROWS

2048 COLUMNS

As

•

As
A7
As

•
DIN

•

•

COLUMN I/O CIRCUITS
INPUT
DATA
CONT.

WE

DOUT

COLUMN SELECT

TRUTH TABLE

CS

WE

Mode

H

X

Not Selected

L

L

L

H

Output

Standby

Write

High-Z

Active

Read

DOUT

Active

CAPACITANCE

eTA

Legend: H = High level
L = Low level
X = Don't Care

=25°C f =1 MHZ)

Parameter

2-4

Power

High-Z

Symbol

Typ

Max

Unit

Input Capacitance (VIN = 0 V)

CIN

6

pF

CS Capacitance (VCS = 0 V)

Ccs

7

pF

Output Capacitance (VOUT = 0 V)

COUT

7

pF

MB82B001-25
MB82B001-35

PIN DISCRIPTION
Symbol

Pin name

Symbol

Pin name

AO to AS

Address Input

WE

Write Enable

DIN

Data Input

Vee

PowerSupply(+10%)

DOUT

Data Output

GND

Ground

CS

Chip Select

NC

No Connect

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter

Symbol

Supply Voltage

Vee

Ambient Temperature

TA

Min

Typ

Max

Unit

4.5

5.0

5.5

V

70

°c

0

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Test Condition

Symbol

Min

III

VOUT = OV to Vcc
Vee = Max.

ILO

CS = VIL, lOUT _ OmA
Vee ~ Max VIN ~ VII or VI_
Vee = Max., CS = VIL
Cycle = Min., lOUT = OmA
Vee = Min. to Max.

lec,

VIN = OV to Vee
Vee = Max.

Input Leakage Current

Typ

Max

Unit

-1

1

IJA

-1

1

IJA

CS = VIH,
Output Leakage Current

Active Supply Current

Standby Current

CS

~Vce...{J.2V

VIN

~

50

80
mA

le02

80

120

ISB'

2

15

Vce - 0.2V or VIN ., 0.2V
mA

Vee = Min. to Max.
Cs=VIH

ISB2

Output Low Voltage

IOL= 16 mA

VOL

Output High Voltage

IOH = -4 mA

VOH

Vee = OV to Vee Min .
CS = Lower of Vee or
VIH Min.

Ipo

.,
Peak Power on Current
Input Low Voltage

VIL

Input High Voltage

VIH

10

25
0.45

...{J.5'2
2.2

V
V

2.4

50

mA

0.8

V

6.0

V

'I A pull-up resistor to Vrx; on the CS input is required to keep the device deselected; otherwise, power-on current approaches Icc active.
'2 -3.0 V Min. for pulse width less than 20 ns.

2-5

MB82B001-25
MB82B001-35
AC TEST CONDITIONS

•

Input Pulse Levels:

0.6 Vlo 2.4 V

•

Input Pulse Rise and Fall Times:

3 ns (0.8V to 2.2V)

.. Timing Reference Levels:
•

Input:
Output:

Output Load:

VIL = 0.8, VIH = 2.2 V
VOL = 0.8, VOH = 2.2 V

Fig. 2
5V

DoUI~-------'r-------------~

"Including Scope and Jig capacitance

Parameters Measured
excepttLZ, tHZ, tOW and tWZ
tLZ tHZ tOW and tWZ

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Symbol

IRe

25

1M

Chip Selection 10 Output in Low-Z

"5 "6

ILZ

5

1HZ

2

Chip Selection 10 Power Up time

IPU

0

Chip Deselection 10 Power Down

!Po

Chip Deselection 10 Output in High-Z

'11'5 ·6

35
35

ns

25

35

ns

5
15

2

ns

15

20

ns
ns

0

"1 WE is high for Read cycle.
"2 All Read cycles are determined fr~ the last address transition 10 the first address transition of next cycle.
"3 Device is continuously selected, CS=VIL,-"4 Address valid prior 10 or coincident with CS transition low.
"5 Transition is measuned at the point of ±50OmV from steady state voltage.
"6 This parameter is measured with specified Load II in Fig. 2.

2-6

ns

25

30

ns

MB82B001-25
MB82B001-35

READ CYCLE TIMING DIAGRAM
READ CYCLE: ADDRESS CONTROLLED 'I '3

'2

ADDRESS

DATA OUT

Previous Data
Valid

Data Valid

READ CYCLE: Cs CONTROLLED 'I '4

ADDRESS

~~
.: ;, :..•';'.:.,•:."'.,?:. t_val------"~~'------t1.,.,:.:.,
.• .,: .•:•. .• ; :,: :;': ; '; :,;
~;...<",,»,<>
1 - - - - - tACS -----iot

DATA OUT

Icc

ISB

~

: Undefined

lZ3 :Don't Care

'I WE is high for Read cycle.
'2 All Read cycles are determined fr~ the last address transition to the first address transition of next cycle.
'3 Device is continuously selected, CS=VIL~
'4 Address valid prior to or coincident with CS transition low.

:5

Tr~nsition

is measured at the I'0int of ±500mV from steady state voltage.

2-7

MB82B001-25
MB82B001-35

AC CHARACTERISTICS

(Continued)
(Recommended nn.. r~ltln" conditions unless otherwise noted.)
Parameter

Write Cycle Time '3

\We

25

35

Chip Selection to End of Write

tcw

16

26

Address Valid to End of Write

lAW

18

28

ns

ns
ns

Write Pulse Width

20

Data Valid to End of Write

tow

10

15

ns

Write Recovery Time

twR

o

0

ns

toH

o

twz

o

tow

o

Data Hold Time
Write Enable to Output in High-Z
Output Active from End of Write

'4 '5
'4 '5

0
10

0

15

0

ns

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE: WE CONTROLLED '1 '2

'3

~-------------------twc~------------------~

ADDRESS

Valid
~----------- tew -------~

~------twp-----~

DATA IN

DATA OUT
'1 Caw WE must be high during addren,.transitions.
'2 If CS goes high simultaneously with WE high, the output remains in high impedance state.
'3 All Write cycles are determined from the last address transition to the first address transition of next cycle.
'4 Transition is measured at the point of ±500mV from steady state voltage.
, This
me i m au
ith
ified
dll' i

2-8

ns

: Don't Care

MB82B001-25
MB82B001-35
WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE: CS CONTROLLED '1 '2

'3

~----------------twc ~------------R--~
Valid

ADDRESS

--t~--~ tWR

---t-

to:..
...----------------------------

-------,!

A-W- ----------------------------

14-0------

t~u.

------..l

1_;.----------

~-------twp------~

toi----

tow

DATA IN

DATA OUT

____

~.

~( ~------------H~i9~h--Z-----------~

:Undefined

E2J :Don't Care

'1 C&..!lr WE must be high during addreWransitions.

'2 If CS goes high simultaneously with WE high, the output remains in high impedance state.
'3 All Write cycles are determined from the last address transition to the first address transition of next cycle.
'4 Transition is measured at the point of ±50OmV from steady state Voltage.
'5 This parameter is measured with specified Load II in Fig. 2.

2-9

MB82B001-25
MB82B001-35

PACKAGE DIMENSIONS
28-LEAD PLASTIC LEADED CHIP CARRIER
(CASE No_: LCC-28P-M05 }
,....,....,r-. _ _ . _ _ _ _ _ _ _

,-

F)l
.368±.020
(9.35±0.51 )

'.089(2.25)
NOM

-

_~J';j;
f--

005
0.13)

.025(0.64)
MIN
.140(3.55)

MAX

"A"

.032(0.81)

MAX
Details of" A" part

a

.004(0.10)

* This dimension includes resin protrusion.
.'988 FUJITSU LIMITED C28065S·1C

2-10

(Each side:.006(0.15)MAX.)

Dimensions in
inches (millimeters)

cP

October 1989
Edition 1.0

FUJITSU

DATA SHEET

MB82B005-251-35
1M BIT HIGH SPEED BI-CMOS SRAM
262,144 WORDS x 4 BITS HIGH SPEED BI-CMOS
STATIC RANDOM ACCESS MEMORY
Bi-CMOS process technology. To make power dissipation lower and high speed, peripheral
circuits consist of ~MOS technology, and to obtain smaller chip size, cells consist of N MaS
transistors and resistors.
The memory utilizes asynchronous circuitry and may be maintained in any state for an indefinite
period of time. All pins are TIL compatible, and a single 5 volts power supply is required. The
MB82B005 has 400mil plastic small out-line J-Iead(SOJ) as package option.
The MB82B005 is ideally suited for use in datapracessing systems and other applications where
last access time and ease of use are required. All devices offer the advantages of low power
dissipation, low cost and high peformance.

•

Organization: 262,144 words x 4 bits

•

Static operation: No clocks or refresh required

•

Fast access time:

•

Single +5V(±10%) power supply with low current drain

25ns max. (MB82B005-25)
35ns max. (MB82B005-35)

Active operation = 120mA max.
Standby operation = 15mA max. (CMOS level)
Standby operation = 25mA max. (TIL level)
•

Common deta input and output

•

TTL compatible inputs and outputs

PLASTIC PACKAGE
LCCo28P-MOS

•

Chip select for simplified memory expansion, automatic power down

•

All inputs and output have protection against static charge

•

400 mil width 28-pin SOJ package (Suffix: -f>J)

PIN ASSIGNMENT

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating

Symbol

Value

Unit

Supply Voltage

Vrx;

-C.5to+7.0

V

Input Voltage on any pin with to GND

Y,N

-C.S to +7.0

V

Output Voltage on any pin with to GND

V OUT

-C.5to +7.0

Power Dissipation
Output Current

Po
lOUT

1.0

±20

V

W
mA

Temperature under Bias

T BIAS

-10 to +85

·C

Storage Temperature

TSTG

-40 to +125

·C

NOTE:

Permanent device damage may oocur H the above Absolute Maximum
R.tI~. are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affecl device
reliability.

A
A
A
A
A
A
A
A
A
A

t~

..A

[~
if
GND
..Qli
DE

28
'Z1
26

10
2
3
4
5

25
24

8
7
B

23

TOP

VIEW

9
1110
12
13
14

22

~I
19

0

J~:'::-h~:r::~

'tc
A
A
A
A
A
A
A
NC
1104

1103

1102
:~ ~ .IIW

:: J WE

-=

~ =1::'

However, • is advised that normal precautions be taken to
avoid appicalion of any voltage higher than maxinum rated
voIIages to this high inpedanoo citoult.

Copyright© 1_ FUJITSU LlMIlCD

2-11

MB82BOO5-25
MB82BOO5-35
Fig. 1 - MB82B005 BLOCK DIAGRAM

Ao
A,

Vee

•

A2

GND

A3
A.

CELL
ARRAY
512 ROWS
512COLUMNS
x4

•

ROW
SELECT

As

•

As
A7
As

•
VOl

•

•

COLUMN I/O CIRCUITS

V02

INPUT
DATA
CONTROL

V03

COLUMN SELECT

va.
Ag
CS
OE

A,o

A"

A'2 A'3

A,.

A

'5

A,s

A17

WE
POWER
DOWN
CIRCUIT

TRUTH TABLE
CS

WE

OE

Mode

110

Power

H

X

X

Not Selected

High-Z

Standby

L

H

H

Output Desable

High-Z

Active

L

L

X

Writte

DIN

Active

L

H

L

Read

DouT

Active

Legend: H = High level
L = Low level
X = Don't Care

CAPACITANCE (TA =25°C f =1 MHZ)
Parameter

2-12

Symbol

Typ

Max

Unit

Input Capacitance (VIN = 0 V)

CIN

6

pF

Cs Capacitance (Vl!!\ = 0 V)

cCs

7

pF

Output Capacitance (VOUT = 0 V)

CoUT

7

pF

MB82BOO5-25
MB82BOO5-35

PIN DISCRIPTION
Symbol
AOtoA17
1/01 to 1/04
OE
CS

Pin name
Address Input
Data InputlOutput
Output Enable
Chip Select

Symbol
WE
Vee
GND
NC

Pin name
Write Enable
Power SupplyLt 10%)
Ground
No Connect

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter

Symbol

Supply Voltage

Vee

Ambient Temperature

TA

Min

Typ

Max

Unit

4.5

5.0

5.5

V

70

°c

0

'1:4

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Test Condition

Symbol

Min

Typ

Max

Unit

Input Leakage Current

VIN = OV to Vee
Vee = Max.

III

-1

1

J.IA

Output Leakage Current

Cs = VIH, or OE=VIH
VOUT = OV to Vee
Vee = Max.

ILO

-1

1

J.IA

CS = VIl, lOUT - OmA
Vee _ Max V,N _ VI' Dr V"
Vee = MaX., CS = V,L
Cycle = Min., lOUT = OmA
Vee = Min. to Max.

Actiw Supply Current

Cs~Vee~.2V
VIN

Standby Current

~

leel

50

80
mA

1CC2

80

120

1591

2

15

Vee - 0.2V or VIN :s; 0.2V
mA

Vee = Min. to Max.
Cs=VIH
Output Low Voltage

IOL=8mA

VOL

Output High Voltage

IOH =-4 mA

VOH

Vee = OV to Vee Min.
CS = Lower of Vee or
VIH Min.

IPO

'1

Peak Power on Current
Input Low Voltage

VIL

Input High Voltage

VIH

'1 A

pul~up

10

1592

25
0.4

2.4

V

50
~.5'2

2.2

V

mA

0.8

V

6.0

V

resistor to Vcc on the CS input is required to keep the device deselected; otherwise, power-on current approaches Icc actiw.

'2 -3.0 V Min. for pulse width less than 20 ns.

2-13

MB82BOO5-25
MB82BOO5-35
AC TEST CONDITIONS
•

Input Pulse Levels:

0.6 Vto 2.4 V

•

Input Pulse Rise and Fall Times:

3 ns (0.8V to 2.2V)

•

Timing Reference Levels:

Input:
Output:

•

Output Load:

VIL = 0.8, VIH = 2.2 V
VOL,= 0.8, VOH = 2.2 V

Fig. 2
5V

R1

R2
Parameters Measured
except tCLZ, tCHZ, IOLZ, 10HZ, lOW and tWZ
tCLZ tCHZ tOLZ 10HZ lOW and tWZ
'Including Scope and Jig capacitance

AC CHARACTERISTICS
(Recommended operating condHlons unless otherwise noted.)
Parameter

Read Cycle Time '2

lAC

Address Access Time '3

fAA

25

35

ns

lACS

25

35

ns

10

15

ns

Chip Select Access Time

'4

25

Output Enable Access Time

ns

35

Output Hold from Address Change

ns

Chip Selection to Output in Low-Z

'5'6

\cLl

5

Chip Selection to Output in High-Z

'5'6

\cHZ

2

5
15

Output Enable to Output in

2

Output Enable to Output in High-Z ·5"*6

10HZ

0

Chip Selection to Power Up time

IPU

0

Chip Deselection 10 Power Down

IPO

15

0
0

ns
ns

0

'1 WE is high for Read cycle.
'2 All Read cycles are determined from the last address transition to the first address transition of next cycle.
'3 Device is continuously selected, C§..VIL ~=VIL.
'4 Address valid prior to or coincident with CS transition low.
'5 Transition is measured at the point of ±50OmV from steady state voltege.
'6 This parameter is measured with specified Load II in Fig. 2.

2-14

15

15

ns
ns

MB82BOO5-25
MB82BOO5-35
READ CYCLE TIMING DIAGRAM
READ CYCLE: ADDRESS CONTROLLED '1 '3
'2
~--------------tRC--------------~

~~,.,..,...,..,..

Valid

ADDRESS

-

Data Valid

DATA OUT

READ CYCLE: CS CONTROLLED '1 '4

ADDRESS

~""-'_====val_~~'_----,~$
~-------t~s--------~

DATA OUT

Icc

ISB

jg8I : Undefined

12:3 :Don't Care

'1 WE is high lor Read cycle.
'2 All Read cycles are determined fr.Q!!) the iU! address transition to the first address transition of next cycle.
'3 Device is continuously selected, CS=VIL..Q.E=VIL.
'4 Address valid prior to or coincident with CS transition low.
Transition is me~ured at the ~int of '!=500mV from steady state voltage.

:5

2-15

MB82BOO5-25
MB82BOO5-35

AC CHARACTERISTICS (Continued)
(Recommended

conditions unless otherwise noted.)

Parameter

Write Cycle Time '3

!We

25

35

ns

Address Valid to End of Write

lAW

18

28

ns

0

twP

15

20

Data Valid 10 End of Write

tow

8

12

ns

Write Recovery Time

twR

0

0

ns

Data Hold Time

IDH

0

0

ns

twz

0

tow

0

Write Enable 10 Output in High-Z
OUtput Active from End of Write

'4 '5

'4 '5

_

0

8

14

ns

0

WRITE CYCLE TIMING DIAGRAM

WRITE CYCLE: WE CONTROLLED '1 '2

'3

~------------------twc~----------------~~
ADDRESS

Valid

\4------------ tew ------------...-j

\4-------twp------~

DATA IN

t~44~

_____H~i9~h_-Z_________~

~

2-16

: Undefined

ns

E2J :Don1 Care

MB82BOO5-25
MB82BOO5-35
WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE: CS CONTROLLED '1 '2
'3

~-----------------twc ~--------------~
ADDRESS

DATA IN

DATA OUT

High-Z

~

<: ~________________H_~~h_-_Z
~

'1 C&.lIr WE must be high during

: Undefined

'· ,
lZl
.•,••••.•<

:

_____________

Don't Care

add~nsitions.

'2 If CS goes high simultaneously with WE high, the output remains in h~h impedance state.
'3 All Write cycles are determined from the last address transition to the first address transition of next cycle.
'4 Transition is measured at the point of ±500mV from steady state Voltage.
'5 This parameter is measured with specified Load II in Fig. 2.

2-17

MB82BOO5-25
MB82BOO5-35

PACKAGE DIMENSIONS
28-LEAD PLASTIC LEADED CHIP CARRIER'
(CASE No.: Lcc.28P·MOS I

.., ........................................ -

I ...

I

o

r

~1
.368±.020
(9.35±0.51)

.400(10.16)

~UUUUUUUUUUUU=-1

.:' .725'.005(18.42±0.13)

,- F

J"

J"~"j;

OOS
0.13)

~

•
.089(2.25)
NOM

1-

-

.025(0.64)
MIN
.140(3.55)

MAX

"A"

.032(0.81)

MAX
Details of" A" part

.650(16.51) REF
01. FWfTSU LIMITED C28065S·1C

2-18

* This dimension includes resin protrusion.
(Each side:.006(0.15)MAX.)

Dimensions in
inches (millimeters)

00

November 1989
Edition 1.1

FUJITSU

DATA SHEET

MB82B006-251-35
1M BIT HIGH SPEED BI-CMOS SRAM
262,144 WORDS X 4 BITS HIGH SPEED BI-CMOS
STATIC RANDOM ACCESS MEMORY
The Fujitsu MB82BOO6Is 262.144woras x 4 DilS staticranciom access memury IC:f,uli\.oclLt,u "~u\ Q
Bi-CMOS process technology. To make power dissipation lower and high speed, peripheral
circuits consist of Bi-CMOS technology, and to obtain smaller chip size, cells consist of NMOS
transistors and resistors.

The memory utilizes asynchronous circuitry and may be maintained in any state for an indefinite
period of time. All pins are TIL compatible, and a single 5 volts power supply is required. The
MB82B006 has 400mil plastic small out-line J-lead(SOJ) as package option.

T.B.D.

The MB82BOO6 is ideally suited for use in dataprocessing systems and other applications where
fast access time and ease of use are required. All devices offer the advantages of low power
dissipation, low cost and high peformance.
•
•

Organization: 262,144 words x 4 bits
Static operation: No clocks or refresh required

• Fast access time:
•

PLASTIC PACKAGE
LCC-32P-MXX

25ns max.(MB82Boo6-25)
35ns max.(MB82BOO6-35)
Single +5V(±10%) power supply with low current drain
Active operation = t20mA max.
Standby operation = 15mA max. (CMOS level)
Standby operation = 25mA max. (TIL level)

PIN ASSIGNMENT
(TOP VIEW)

•
•
•
•
•

Separate data input and output
TIL compatible inputs and outputs
Chip select for simplified memory expansion, automatic power down
All inputs and output have protection against static charge
400 mil width 32;>in SOJ package (Suffix: -PJ)

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating

Symbol

Value

Unit

Supply Voltage

Vee

-{l.5 to +7.0

V

Input Voltage on any pin with to GND

V ,N

-{l.5 to +7.0

V

Output Voltage on any pin with to GND

V OUT

-{l.5 to +7.0

V

Power Dissipation

PD

1.0

W

Output Current

lOUT

±20

mA

Temperature under Bias

T BIAS

-10 to +85

"C

Storage Temperature

Tsm

--40 to +125

"C

NOTE:

Permanent device damage may occur if the above Absolute Maximum
Ratings are exceeded. Functional operation should be restricted to the
condibons as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability .

NC

Vee

A

A

A
A

A

A

A

A

A

A
A
A
A
A
A
14

A
A
NC
11
12

13
CS
GND

J~~du~~aj~~~~!~

A

01
02
03

04
WE

t::; !r8 ~'::t~av~\~~~

However. It is advised that nannal precautions be taken to
avoid application of any voltage higher than maximum rated
voltages 10 this high Irrpedance circuit.

Copyrlgh.©' 989 FUJITSU LIMITED

2-19

MB82BOO6-25
MB82B006-35
Fig. 1 - MB82BOO6 BLOCK DIAGRAM

Vee

•

GND
ROW
SELECT

CELL
ARRAY
512 ROWS
512COLUMNS
x4

•
•

•

•
11-------1

12-------;
13-------1

•
01

•
INPUT
DATA
CONTROL

02

COLUMN VO CIRCUITS

03
•
04

14-------1
COLUMN SELECT

POWER
DOWN
CIRCUIT

TRUTH TABLE

cs

WE

Mode

Output

Po_

H

X

Not Selected

High-Z

Standby

L

H

Read

DOUT

Active

L

L

Write

High-Z

Active

Legend: H = High level
L= Low level
X = Don't Care

CAPACITANCE (TA =25°C f =1 MHz)
Parameter

2-20

Symbol

Typ

Max

Unit

Input Capacitance (VIN = 0 V)

CIN

6

pF

OS Capacitance (VCS = 0 V)

Ccs

7

pF

Output Capacitance (VOUT = 0 V)

COUT

7

pF

MB82BOO6-25
MB82BOO6-35

PIN DISCRIPTION
Symbol

Pin name

Symbol

Pin name

AO to A17

Address Input

WE

Wrila Enable

11 to 14

Data Input

Vee

PowerSupp~LT10%)

01 to 04

Data Output

GND

Ground

CS

Chip Select

NC

No Connect

RECOMMENDED OPERATING CONDITIONS
,(Referenced to GND)

I

I

Parameter

Symbol

Supply Voltage

Vee

Ambient Temperature

TA

I

I

I

I

Min

Typ

Max

Unit

4.5

5.0

5.5

V

70

°c

0

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Test Condition
VIN = OV to Vee
Vee = Max.

Input Leakage Current

Symbol

Min

Typ

Max

Unit

III

-1

1

~

Vour = OV to Vee
Vee = Max.

ILO

-1

1

~

Cs = VIL, lOUT- OmA
Vee ~ Max .. VIN ~ VIL or VIH
Vce = Max., CS = VIL
Cycle = Min., lour = OmA

leel

IC02

SO

120

Vee = Min. to Max.
CS ~ Vee -O.2V

ISBl

2

15

Cs=VIH
Output Leakage Current

Active Supply Current

VIN

Standby Current

~

50

SO
mA

Vee - 0.2V or VIN S 0.2V
mA

12f; = Min. to Max.
CS=VIH

ISB2

Output Low Voltage

IOL=SmA

VOL

Output High Voltage

IOH - -4 mA

VOH

Vee = OV to Vee Min.
= Lower of Vee or
VIH Min.

IPO

·1

Peak Power on Current

CS

Input Low Voltage

VIL

Input High Voltage

VIH

10

25
0.4

2.4

V

50
-0.5"2
2.2

V

mA

O.S

V

6.0

V

"I A pull-up resistor to Vcc on the CS input is required to keep the device deseleclad; otherwise, power-on current approaches Icc active.
"2 --.'3.0 V Min. for pulse width less than 20 ns.

2-21

MB82BOO6-25
MB82BOO6-35
AC TEST CONDITIONS
•

Inpul Pulse Levels:

0.6 Vto 2.4 V

•

Inpul Pulse Rise and Fall Times:

3 ns (O.BV to 2.2V)

•

Timing Reference Levels:

Input:
Output:

•

OutpUI Load:

VIL = O.B, VIH = 2.2 V
VOL = O.B, VOH = 2.2 V

Fig. 2
5V

R1
~I~----~--------~

R2

Load I
Load"

Rl
4800
4800

R2
2550
2550

Parameters Measured
excepllLZ, 1HZ, tOW and IWZ
ILZ tHZ tOW and tWZ

CL
30pF
5pF

"Including Scope and Jig capacltanoa

AC CHARACTERISTICS
(Recommended ODl!ratt'na condHlons unless otherwise noted.)
Parameter

Read Cycle Time "2

tRe

Address Access Time "3
Chip Select Access Time

"4

Output Hold from Address Change

lAcs

IOH

ns

35

25
25

35

ns

25

35

ns

5

5

ns
ns

5

2
Chip Seleclion to Power Up time

!PU

Chip Deselection to Power Down

!PO

15

2

o

o
20

"I WE is high for Read cycle.
"2 All Read cycles era determinad from the last address transition to the first address transition of next cycle.
"3 Devioa is continuously selected, CS=VIL,,"4 Address valid prior to or coincident with CS transition low.
"5 Transition is measured at the point of ±5OOmV from steady slate voIlage.
"6 This parameter is measured with specifiad Load II in Fig. 2.

2-22

15

ns
ns

30

ns

MB82BOO6-25
MB82BOO6-35
READ CYCLE TIMING DIAGRAM
READ CYCLE: ADDRESS CONTROLLED "1 "3

Valid

ADDRESS

DATA OUT

Previous Data
Valid

Data Valid

READ CYCLE: CS CONTROLLED·1 ·4

"2

~--------------tRC------------~
ADDRESS

Valid

~------- tACS -------~

DATA OUT

Icc

ISB

a

:Undefined

EZJ :Don't Care

WE

·1
is high for Read cycle.
"2 All Read cycles are determined from the last address transition to the first address transition of next cycle.
"3 Device is continuously seiectad, CS:VIl,-·4 Address valid prior to or coincident with CS transition low.
·S Transition is measured at the point of ±5OOmV from steady state voltage.
·S This parameter is measured with specified Load II in Fig. 2.

2-23

MB82BOO6-25
MB82BOO6-35

AC CHARACTERISTICS

(Continued)
(Recommended oDl~ratllna conditions unless otherwise noted,)
Parameter

Write Cycle TllTle '3

!We

25

ns

35

ns
lAW

18

28

ns

lAS

0

0

ns

Data Valid to End of Write

1DW

10

15

ns

Write Recovery Time

twR

0

0

ns

0

0

Address Varsd to End of Write

write Enable to Output in High-Z
Output Active from End of Write

'4 '5
'4 '5

_

IWZ

0

tow

0

10

0

15

0

ns

WRITE CYCLE TIMING DIAGRAM

WRITE CYCLE: WE CONTROLLED 'I '2

'3

~-----------------twc~--------------~~
ADDRESS

VaUd
...- - - - - - - tew

-------.t

14----- twp

------.j

DATA IN

DATA OUT

a

:Undefined
'I ~ WE must be high during addra.u..transitions.
'2 II CS goes high simultaneously with WE high, the output ramains in high impedanca state.
'3 All Write cycles are determined from the last addrass transition to the first addrass transition 01 next cycle.
T~sition is me!lSured at the J?Oint 01 =!=50OmV fro~ steady state voltage.

:4

2-24

ns

: Don't C819

MB82BOO6-25
MB82BOO6-35
WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE: CS CONTROLLED "I "2

"3

~---------------t~ ~------------~
Valid

ADDRESS

~---------------~

tAW

I,

-----------.-t..

/4---------tcw

---------i

1------

twp ------t

DATA IN

Valid

High-Z
DATA OUT

11-;....--------

<:

~ ________
~

~

:Undefined

H_i~9h_-_Z_ _ _ _ __

f2J :Don't Care

"I C~ WE must be high during addreUjransitions.
"2 II CS goes high simultaneously with WE high, the output remains in high impedance state.
"3 Ali Write cycles are determined from the last address transition to the first address transition of next cycle.
"4 Transition is measured at the point of ±500mV from steady state voltage.
"5 This parameter is measured with specified Load Ii in Fig. 2.

Aft Rights Reserved. Circuit diagrams utUizlng Fujlt&u prodUds are included as a means of
iHustrating typcaI semiconductor applications. Co~ Information suflk:lem for
COrIstl'Udion purposes Is noI necessarflyglven. The information contained In this document
has been carefully checked and 16 believed to be reliable. However, Fujitsu auumes no
responsibility for inaccuracies.

The Information contained In this document does not convey any licenae under the
ccpyrlgtu, patent rights or tradamarks claimed and owned by Fujitsu. Fujitsu reserves the
right to change products or specllcatlons whhout notice. No part of this pLbllcatlon may be
cq:>Ied or repf'oduced In any form or by any means, or transferred to any third party without

prior written consent of Fujitsu.

2-25

High-speed BiCMOS SRAMs

2-26

Static RAM Data Book

OJ

TS28G-A89Z
December 1989

FUJITSU

DATA SHEET

M882871-151-20
64K BIT HIGH SPEED BI-CMOS SRAM
65,536-WORD X 1-BIT Bi-CMOS HIGH SPEED
STATIC RANDOM ACCESS MEMORY
The FUjitsu Mt::382t:S/lIS a bb,o:.itiworas oy 1 bits SIalic random au;t::::i:S 111t:IIIUIY idi.llil.A;l~C'Jw·;u\CI.

CMOS silicon gate process. To make power dissipation lower and high speed, peripheral
circuits consist of Bi-CMOS technology, and to obtain amaller c h" size, cells consist of NMOS
transistors and resistors.
MB82B71 has 300mii plastic DIP, leadless chip carrier (LCC) and 300mil plastic small out-line
J-lead (SOJ) package as package option. The memory utilizes asynchronous circuitry and
requires +5V power supply. All pins are TIL compatible.
The MB82B71 is ideally suited for use in large computer and other applications where fast
access time, large-<:apacity and ease of use are required.
All devices offer the advantages of low power dissipation, low cost high performance.
•
•
•

•

•
•
•
•
•

Organization: 65,536 words x 1 bit
Static operation: No clocks or refresh required
Fast access time:
tAA=tACS=15ns max.(MB82B71-15)
tAA=tACS=20ns max.(MB82B71-20)
Single=5V(+ 10%) power supply with low current drain:
Active operation=120mA max.
Standby operation=15mA max.(CMOS level)
Standby operation=30mA max.(TIL level)
Bi-CMOS peripheral
TIL compatible inputs/outputs
Three-state output
300 mil width 22-pin plastic Skinny 01 P package (Suffix: -P-SK)
300 mil width 24-pin plastic SOJ package (Sullix: -PJ)

PLASTIC PACKAGE
DIP-22P-M04

PLASTIC PACKAGE
LCC-24P-M02
PIN ASSIGNMENT
Vee

A,
A,
A,
A.
A"
A"
A,.
A.

• 22-pad lead less Chip Carrier package (Suffix:-CV)
• Pin compatible with MB81C71A

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating

Symbol

Supply Voltage
Input Voltage on

any pin with to GND

Output Voltage on

any pin with to GND

Power Dissipation

VIN

-0.5 to +7.0

V

Vuo

-0.5 to +7.0

Po
lOUT

Temperature under Bias

TSIAS

NOTE:

I

Plastic

I

Ceramic

Unit
V

Output Current

Storage Temperature

Value
-0.5 to +7.0

Vcc

Tsm

1.0
±20

we

0,.

V

W
rnA

-10 to +85

fC

-40 to +125

·C

-65 to +150

Permanent device damage may occur if the above Absolute Maximum
Ratings are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.

J~~:n:;o~ai~~~r~~~ 1~~~: ~re !~ric ':~d!~
However•• Is advised that normal precautions be taken to
avoid application of any voltage higher than maxirrum rated
voltages to this high irrpedance circu_.

Copyrlghl© '989 FUJITSU LIM ITED

2-27

MB82B71-15
MB82B71-20
Fig. 1 - MB82B71 BLOCK DIAGRAM

T.B.D

CAPACITANCE {Ta=25°C, f=1MHz)

MB82B71-15
MB82B71-20

PIN DISCRIPTION
Symbol

Symbol

Pin name

Pin name

Address input.

WE

Write Enable.

DIN

Data input.

vee

Power Supply(+5V+lO%).

DOUT

Data output.

GND

Ground.

AO to Al5

,

,

r.~

.

r.hin

,

,

~~ll3ort-.

,

TRUTH TABLE
es

WE

H

X

NottSelected

High-Z

Standby

L

L

Write

High-Z

Active

L

H

Read

DOUT

Active

Mode

Legend: H=High level,

Output

L=Low level,

Power Supply Current

X=Don't care

RECOMMENDED OPERATING CONDITIONS
Referenced to GND)
Parameter

Symbol

Min

Typ

Max

Supply Voltage

vee

4.5

5.0

5.5

Ambient Temperature

TA

0

70

Unit
V

°e

2-29

MB82B71-15
MB82B71-20

DC CHARACTERISTICS
Recommended operatiDJt conditions otherwise noted.}
Parameter

Test Conditions

Symbol

Min

Max

Unit

Input Leakage Current

VIN=GND to VCC
VCC=max.

ILl

-5

5

l1A

Output Leakage Current

VOUT=GND to VCC
CS=VIHor WE=VIL

ILI/O

-5

5

l1A

Operating Supply Current

CS=VIL, DOUT=Open
Cycle=min.
VCC-min. to max.
CS=VCC-0.2V, VINSO.2V
or VI~VCC-0.2V

ICC

120

mA

ISB1

15

mA

CS=VIH
VCC=min. to max.

ISB2

30

mA

Standby Supply Current
Standby Supply Current
Input High Voltage

VIH

2.2

6.0

V

Input Low Voltage

VIL

*1
-0.5

0.8

V

2.4

Output High Voltage

IOH=-4mA

VOH

Output Low Voltage

IOL=8mA

VOL

V
0.4

V

VCC=GND to 4.5V
CS=Lower of VCC or
IPO
50
mA
VIH min.
Note: *1 -2.0V min. for pulse w1dth less than 20ns.
*2 The CS input should be connected to VCC to keep the device deselected.
Peak Power-on Current *2

Fig. 2 - AC TEST CONDITIONS
0.6V to 2.4V
• Input Pulse Levels:
• Input Pulse Rise & Fall Time: 1ns(Transient between 0.8V and 2.2V)
Input: VIL=0.8V, VIH=2.2V
• Timing Reference Levels:
Output: VOL=0.8V, VOH=2.2V
• Output Load
5V
480Q
Dout

o-------.-----~

255Q

* Including Scope and jig capacitance
Parameters measured
t tLZ, tHZ tOW and tWZ
tHZ, tOW and tWZ

2-30

MB82B71-15
MB82B71-20

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE
Parameter

Symbol

Read Cycle Time
Address Access Time
ICS Access Time
Output Hold from Address Change
Output Low-Z from ICS

tRC
tAA
tACS
tOH
tLZ

Gu.t:VuL: ~:lgh-Z fJ..vw /C3

~n'"

Power Up from ICS
Power Down from ICS

tPU
tPD

MB82B71 15
Max
Min
15
15
15
3
3
0

0
15

MB82B71 20
Min
Max
20
20
20
3
3
iG
0
15

Unit
ns
ns
ns
ns
ns
ns

ns
ns

READ CYCLE TIMING DIAGRAM *1
READ CYCLE ·3

ADDRESS

PREVIOUS DATA VALID

DoUT

READ CYCLE: CS CONTROLLED·4

ADDRESS

..{"":::::~~~~--~~---------tR_c::::::::::::::,,-~--+l1f'i)mN.)@i~WN.t)ii£W

HIGH-Z
DoUT

SUPPLY

W~~

ICC _ _ _ _ _

__________

r-~:o1~~

~

~

Note: *1
*2
*3
*4
*5

HIGH-Z

~:::::_IP_D::_-_-_-1.~-50-'%--

Undefined

~

InfH

Don't Care

WE is high for Read cycle.
Device is continously selected, CS=VIL.
Address valid prior to or coincident with CS transition low.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

2-31

MB82B71-15
MB82B71-20
WRITE CYCLE

Parameter
Wr ite Cyc 1e Time
Address Valid to End of Write
ICS to End of Write
Data Setup Time
Data Hold Time
Write Pulse Width
Write Recovery Time
Address Setu~ Time
Output Low-Z from lWE
Output High Z from lWE

Symbol
tWC
tAW
tCW
tDW
tDH
tWP
tWR
tAS
tOW
tWZ

MB82B71-15
Max
Min
15
12
12

MB82B71-20
Min
Max
20
17

17

4

9

0
11

2
16

1
0
0

0
0

3

6

8

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

WRITE CYCLE TIMING DIAGRAM

WRITE CYCLE I:

ADDRESS

WE

CONTROLLED

1l1i~~::::::::::::::::::::::::::::::::::::::::::~

DIN

lWZ"4~

__

-><...,....X--,"'I:"'X-.,.X~~X--.,..X~l'"O:X~"'I:"'><1-,+...p
DoUT

~

toW"4j

..

HIG_H-_Z-~

Undefined

lmawl

Don" Car.

Note: *1 If CS goes high simultaneously with WE high, the output remains in high
impedance state.
*2 All Write cycle are determined from last address transition to the first
address transition of the next address.
*3 Transition is measured at the point of ±500mV from steady state voltage.
*4 This parameter is specified with Load II in Fig. 2.

2-32

MB82B71-15
MB82B71-20
WRITE CYCLE TIMING DIAGRAM (Continued) '1'2'4
WRITE CYCLE II: CS CONTROLLED '1'2

~~s=l
cs

~

~

IWP

r--

:S:>~
.~
ADDRESS VALID~{1l~..tt;<;;

~~------------------------------~~~~~
~-------------·tcw--------------~-twR~

1~----------------tAw-----------------;

,

htAS----t~---------twp--------_;

1,..-------

~---.tDw------+_-tD~

+-____-{~

_ _.....;H.;.;I.;;G;..;.H•.;;Z_ _

'It.

DATA VALID

HIGH-Z

/I

1\

~twLZI.
HIGH-Z

~

Undefinad

o

~~XX'7l:."")()~

Don'tea..

Note: *1 If CS goes high simultaneously with WE high, the output remains in high
impedance state.
*2 All Write cycle are determined from last address transition to the first
address transition of the next address.
*3 Transition is measured at the point of ±500mV from steady state voltage.
*4 This parameter is specified with Load II in Fig. 2.

2-50

MB82B75-15
MB82B75-20

WRITE CYCLE

n:

CS CONTROLLED· 1 • 2
~-------------------twc--------------------~

ADDRESS

~~~~~________________:A~D:D:R~E~S:S~V~A~L~ID~______________j
~-----------------tAW----------------~

tWR

_____________

---tAS·~·-+14.~------------tcw--------------~;-_~_~_~

~--------------twp--------------~

tOH
~---------tow--------~~~~

HIGH-Z

DATA VALID

HIGH-Z

I8ZI Undefined

Note: *1 If CS goes high simultaneously with WE high, the output remains in high
impedance state.
*2 All Write cycle are determined from last address transition to the first
address transition of the next address.

2-51

MB82B75-15
MB82B75-20

PACKAGE DIMENSIONS
24-LEADS PLASTIC DUAL-IN LINE PACKAGE
(CASE No. :DIP-24P-M03)

I

INDEX·l

.260'.010
(6.60.0.25)

~~~~~~~~~

.300±.010
(7.62±0.25)
.

.010'.002
(0.25±0.05)

.1

~
lr I I lr lr 1
.100(2.54)
TYP

I I

.:.J ~ --11
(1.27~g·50)

.01S'.003
(0.46.0.0S)

,1 m "",."
.11S(3.Q)MIN

.020(0.51lMIN
Dimensions in
inches (millimeters)

© FUJITSU LIMITED 1987 D24017S-2C

24-LEAD PLASTIC LEADED CHIP CARRIER
(CASE No.: LCC·24p·M02)

,.- F

iFf]

005
(8.64 • 0.13)
. 273'.020
(6.93.0.61 )

I~~

I r-

.050'.005
(1.27'0.13)

.025(0.64)
MIN

.091(2.31)
NOM

.550(13.97)REF

•.615'.005(15.62.0.13)
Details

.144(3.66)
MAX

of pa,tG0

32 (0.Sl )MAX

"A"

.102(2.60)
NOM

r:::::'"-r-::::=::-1
L.:::...L..;;';';;:;';"":...I

* : This dimensiQn includes resin protrusion. (Each side: .006(O.15)MAX.)
• 1l1li9 FUJITSU LIMITED C24Il62S·1C

2-52

•

I

I

.017<.004

--1 • (0.43'0.10)

Dimensions in

inches (millimeters) .

MB82B74-15
MB82B74-20
PACKAGE DIMENSIONS

He
.... NC Vee NC

~l!~'~~~J '\
A,7

~]

I.wJ

A,

~~
A5 ~
"4

!J

,A,3!~

TOP VIEW

r~

Ne

~!5 ~
~2~ A'3
~~3 A,O
~2.? All

"2 ~~

~~' AI'2

~, ~?~
B ~J

t~ :~~~
t~~ LIO;
113.,.1'51'6117'

i5lG~~C~/O,

CERAMIC PACKAGE
LCC-28C-A03
28-PAD CERAMIC (METAL SEAL) LEADLESS CHIP CARRIER
(CASE No.: LCC-28C-A03)

·PIN NO.1 INDEX

/

n

.550±.010
113.97'0.25)

.350'.010
18.89.0.251

·Shape of PIN NO.1 INDEX: Subject to change without notice.

Dimensions in inches
and (millimeters)

C) FUJITSU LIMITED 1987 C28009S-1C

2-53

High-speed SiCMOS SRAMs

2-54

Static RAM Data Book

cO

TS24B-E89Y
Nov. 1989

FUJITSU

DATA SHEET

M882879-15-20

72K BIT HIGH SPEED BI-CMOS SRAM
8, 192-WORD x 9-BIT Bi-CMOS HIGH SPEED
STATIC RANDOM ACCESS MEMORY

J~~\\• •&.~1

lhe rUJltSU Mt:S82t:S/':J IS a H,l ~t! words by Ij OilS Static ranaom access memory iauricaLtfO wiuJ a

-

CMOS silicon gate process. To make power dissipation lower and high speed. peripheral
circuits consist of Bi-CMOS technology. and to obtain amaller chip size, cells consist of NMOS
transistors and resistors.
M882B79 has 300mil plastic DIP and plastic flat (SOIC) as package option. The memory utilizes
asynchronous circuitly and requires +5V power supply. All pins are TIL compatible.
The M882B79 is ideally suited for use in large computer and other applications where fast
access time. large-capacity and ease of use are required.
All devices offer the advantages of low power dissipation, low cost high perforrnance.
•
•
•

•

•
•
•
•
•

PLASTIC PACKAGE
FPT-28P-M02

Organization: 8,192 words x 9 bits
Static operation: No clocks or refresh required
Fast access time:
tAA=tACS1=15ns max./ tACS2=IOE=8ns max. (M882B79-15)
tAA=tACS1=20ns max./ tACS2=IOE=IOns max.(M882B79-20)
Single=5V(+ 10%) power supply with low current drain:
Active operation=120mA max.
Standby operation=15mA max.(CMOS level)
Standby operation=2SmA max. {TIL level)
Bi-CMOS peripheral
TIL compatible inputs/outputs
Three-state output
300 mil width 28--pin plastic Skinny DIP package (Suffix: -P-SK)
450 mil width 28--pin plastic SOP package (Suffix: -PF)

PLASTIC PACKAGE
DIP-28P-M04
PIN ASSIGNMENT
(TOP VIEW)

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating

Symbol

Value

Unit

Supply Voltage

Vee

--C.Sto +7.0

V

Input Voltage on any pin with to GND

VIN

--C.S to +7.0

V

Output Voltage on any pin with to GND

VIJO

--C.S to +7.0

V

VCC

A4
AS

WE

A6
A7

CS2
A2

A8

AI

A9
AIO
All

AO

AI2
1/01

DE
A3
CSI

Power Dissipation

Po

1.0

W

1102

1109
1108

Output Current

lOUT

±20

mA

1103
1104

1107
1106

Temperature under Bias

TalAs

-IOto +85

·C

GND

1105

Storage Temperature

TSTG

-40 to +125

·C

NOTE:

Permanent device damage may occur if the above Absolute Maximum
RaUn\ls are exceeded. Functional operation should be restricted to the
condibons as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.

!~~~u:o:ih~~~% ~~: :r8 !'::t~,:~:~

However. ~ is advised that norma! precautions be taken to
avoid application of any vohaga highat than maxil'T'l.1m rated
voltages 10 this high ln1)Qdanca circuil.

Copyrigh,© 1989 FUJITSU LIMITED

2-55

MB82B79-15
MB82B79-.20
Fig. 1 - MB82B79 BLOCK DIAGRAM
AO

0-

Al

0-

A2

0-

A3

0-

A4

0-

AS

0-

A6

0-

A7

0-

-

I-+--OVCC
+--OGNDQ
+---<>GND

Ell

Address
Buffer

Row
Decoder

-

r--

L - - CS*

A8

0-

A9

0-

AlO

0-

All

0-

A12

0-

256 x 32 x 9
Memory Cell Array

I

l
I/O Gate
&

Address
Buffer

Column Decoder

T
CS*
0-

Buffer

I/O Buffer

~

CS

0-

'Lcs
CSI
CS2

1

cs

~

1/01 1/03 1/05 1/07 1/09
1/02 1/04 1/06 1/08

CAPACITANCE ("Ta=25°C, f=1MHz)
Symbol
Parameter
I/O Capacitance (VI/O-OV)
CliO
Input Capacitance(VIN-OV) (lCSl, CS2 IWE, 10E) CIl
Input Capacitance(VIN=OV) (Other inputs)
CI2

2-56

Min Typ

Max
8
7
6

Unit
pF
pF
pF

MB82B79-15
MB82B79-20

PIN DISCRIPTION
Pin name

Symbol

Symbol

Pin name

Address input.

WE

Write Enable.

Data input/output.

VCC

Power Supply(+5V+10%)

CS1

Chip Select 1-

GND

Ground.

CS2

Chip Select 2.

GNDQ

Ground for

Output Enable.

NC

No Connection.

AO to A12
1/01 to Ij09

out~ut.

TRUTH TABLE
Mode

WE

CSl

CS2

OE

X

H

X

X

Standby

High-Z

Standby

X

L

L

X

Not selected

High-Z

Active

H

L

H

H

"Dout disable

High-Z

Active

H

L

H

L

Read

Data out

Active

L

L

H

X

Write

Data in

Active

Legend: H=High level,

L=Low level,

I/O pin

Power Supply Current

X=Don't care

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage

VCC

4.5

5.0

5.5

V

Ambient Temperature

TA

0

70

DC

2-57

DC CHARACTERISTICS

dit·10ns

(Recommend e d operat1.Ilg

COD

0 the rwi se

not e d .)

Test Conditions

Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Supply Current
Standby Supply Current

MB82B79-15
MB82B79-20
Symbol

Min

Max

Unit

VIN=GND to VCC
VCC=max.
VI/O-GND to VCC
CSl=VIH or CS2=VIL or
WE=VIL or OE=VIH

ILl

-10

10

l1A

ILIIO

-10

10

l1A

CSl=VIL, I/O=Open
Cycle=min.
VCC-min. to max.
eSl=Vee-0.2V, VINSO.2V
or VI~VCe-0.2V

ICC

120

mA

ISBI

15

mA

CSl=VIH

ISB2

25

mA

Input High Voltage

VIH

2.2

6.0

V

Input Low Voltage

VIL

*
-0.5

0.8

V

2.4

Output High Voltage

IOH=-4mA

VOH

Output Low Voltage

IOL=8mA

VOL

V
0.4

V

vee=GND to 4.5V
eSl=Lower of VCC or
IPO
50
mA
VIH min.
Note: *1 -2.0V m1n. for pulse w1dth less than 20ns.
*2 The CSI input should be connected to vce to keep the device deselected.
Peak Power-on Current *2

Fig. 2 - AC TEST CONDITIONS
0.6V to 2.4V
• Input Pulse Levels:
• Input Pulse Rise & Fall Time: 3ns(Transient between 0.8V and 2.2V)
Input: VIL=0.8V, VIH=2.2V
• Timing Reference Levels:
Output: VOL=0.8V, VOH=2.2V
• Output Load
5V

·

.....
~

Dout "

CL*~

I

480Q

~ 255Q
~

rtT,

* Including Scope and jig capacitance
1 Load I

I Load II
2-58

Parameters measured
1 CL
1
1
1 30pF . 1 except tLZ, tHZ, tOW, tOLZ and tOHZ 1
I 5pF I tLZ, tHZ, tOW, tOLZ and tOHZ
1

MB82B79-15
MB82B79-20

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE ~'1
MB82B79 15
MB82B79 20
Parameter
Symbol
Min
Max
Min
Max
Read Cycle Time
tRC
15
20
Address Access Time *2
tAA
15
20
jCS1 Access Time *3
tACS1
15
20
tACS2
8
CS2 Access Time
10
tOE
8
JOE Access Time
10
Output Hold from Address Change
tOH
3
3
tLZ1
3
Output Low-Z from ICS1 "/,,+,"5
3
')~4-!'5
Output Low-Z from CS2
tLZ2
2
2
1:4-':'':>
Output Low Z trom lUI!.
t:016
~
Output High-Z from ICS1 '1'4""5
tHZ1
8
10
Output High-Z from CS2 ""4,':5
tHZ2
8
10
Output High-Z from IOE ,"4""5
tOHZ
8
10

"

READ CYCLE TIMING DIAGRAM

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

'~1

READ CYCLE I: ADDRESS CONTROLLED >"3

(CSl=OE="L")

ADDRESS

DOUT

READ CYCLE II: CSl, CS2 CONTROLLED *4

ADDRESS

C$2

-{'4-{:5
tOHZ
DOUT

Data Valid

o :Don't care
Note: *1
*2
*3
*4
*5

tQJ :Undefined

IWE is high for Read cycle.
Device is continuously selected, CS=OE=VIL.
Address valid prior to or coincident with CS transition low.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.
2-59

MB82B79-15
MB82B79-20
WRITE CYCLE *1
Parameter

Symbol

Write Cycle Time
Address Valid to End of Write
J_CSI to End of Write
CS2 to End of Write
Data Setup Time
Data Hold Time
Write Pulse Width
/CS1,/WE
Write Recovery Time*2

tWC
tAW
tCWl
tCW2
tDW
tDH
tWP
tWRl
tWR2
tASI
tAS2
tOW
tWZ

csa

ICS1,/WE
CS2
Output Low Z from /WE *31'4
Output High-Z from /WE *3*4

Address Setup Time

MB82B79-15
Min
Max
15
10
10

MB82B79-20
Min
Max
20
15
15
8
10
3
10
3
5
0
2
0
10

6

7
3
8

3
5
0
2
0
8

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

WRITE CYCLE TIMING DIAGRAM *1
WRITE CYCLE I: WE CONTROLLED

If--------Address

tWC

--------~

~~~-';.#~]I,.;;,::o:..'''-;-",-''''J

~--------------------------------~~~~~--

tAW

*2

-----------~I~tWRl~

CSl

I

rlE------ tCW2
CS2

---~I

-~-':"'''~~~'''''~~4
~~~~-~~·"t.J1

~ tAS1~

_______________+-"IE---

tWP

\
~ tDH~

*3*4
IE- tWZ -;

I/O

E-tDW

_ _ _ _ _ _ _ _ _ _---IYJ~)----(X Data Valid

[J:Don't care

*3*4
tOW-,l

(X}--==
@:Undefined

Note: *1 If CSl, OE and eS2 are in the READ Mode during this period, I/O pins
are in the out put state so that the input signals of opposite phase to
the outputs must not be applied_
*2 tWR is defined from the end point of WRITE Mode.
*3 Transition is measured at the point of ±500mV from steady state voltage.
*4 This parameter is specified with Load II in Fig. 2.

2-60

MB82B79-15
MB82B79-20
WRITE CYCLE II: CSl CONTROLLED

IE--------

tWC

--------41

*2
tAW -------')jE-tWRl--3

IE-

t~

i.1E---_ __

\ \ ':to

tCWl

I

I

r~---

tCW2

---~I

CS2

-:-_ _ _ _ _ _ _ _--,~-- tWP

J

...:.:.:. . .:.---- .......: ... :

tE-

*3*4

IE- tWZ-}
I/O

tDH~

Data Valid

D

:Don't care

WRITE CYCLE III:

"3*4
tOW--3

tE-tDW

___________--'X-"-'!'0r-

..

i

-- ----.-

I

tCW2

tAJ ~

/

CS2

,

tWP

-.

•
.,";31:4
~

tE-tDW

'jJ., ~ Data Valid

I/O

*Notes:

... tDH-l

tWZ->

See Write Cycle I

D

:Don't care

*3'~4

tOW--3

rxr- ~
I/Q!l :Undefined
2-61

MB82B79-1S
MB82B79-20

PACKAGE DIMENSIONS
PLASTIC DIP (Suffix: P·SK)
28·LEAD PLASTIC DUAL·IN·LINE PACKAGE
(CASE No.: DIP·28P·M04)

,~:,:~: :~':~M:K: :::0: : ]J~
I

1.392~:g~~(3S.36~g:~)

I

x======l::;::,!lsoMAX

.300(7.62)TVP

.010'.002
(0.25'0.05)

,.OSo(1.27)MAX

.100(2.54)
TVP

I

@19S6 FUJITSU LIMITED D2S01SS·2C

2-62

.01S'.003
(0.46.0.0S)

Oimensions in
inches (millimeters)

MB82B79-1S
MB82R79-20

PACKAGE DIMENSIONS
PLASTIC FPT (Suffix: ·PFJ
28·LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT·28P·M02J

f.

f@f"
JJ

.339 •. 008

INDEX

d

J

(8.6'0·~;65'.012
(11.8>0.3)

.024(0.6)

~~~~~~nr~
.006,.002
(0.15:0.05)

.008(0.18)
MAX
.027(0.68)
. MAX

.110(2.S)MAX

C) 1987 FUJITSU LIMITED F28011S·2C

Dimensions in

inches (millimeters)

2-63

High-speed SiCMOS SRAMs

Static RAM Data Book

OJ

TS281-A89Z
December 1989

FUJITSU

DATA SHEET

M882881-151-20
256K BIT HIGH SPEED BI-CMOS SRAM
262,144-WORD X 1-BIT Bi-CMOS HIGH SPEED
STATIC RANDOM ACCESS MEMORY
The Fujitsu MB82B81 is a 65,536 words by 1 bits statiC random access memory tacncaleO Wltn a
CMOS silicon gate process. To make power dissipation lower and high speed, peripheral
circuits consist of Bi-CMOS technology, and to obtain amaller Ch~ size, cells consist of NMOS
transistors and resistors.
M882881 has 300mil plastic DIP and 300mil plastic small ouHine J-/ead (SOJ) package as
package option. The memory utilizes asynchronous circuitry and requires +5V power supply. All
pins are TIL compatible.

PLASTIC PACKAGE
DIP-24P-M03

The MB82B81 is ideally suited for use in large computer and other applications where fast
access time, large-capacity and ease of use are required.
All devices offer the advantages of low power dissipation, low cost high performance.
•
•
•

•

•
•
•
•
•

Organization: 262,144 words x 1 bit
Static operation: No clocks or refresh required
Fast access time:
tAA=tACS=15ns max.(MB82B81-15)
tAA=tACS=20ns max.(MB82B81-20)
Single=5V(+10%) power supply with low current drain:
Active operation=120mA max.
Standby operation=15mA max.(CMOS level)
Standby operation=30mA max.(TIL level)
Bi-CMOS peripheral
TIL compatible inputs/outputs
Three-state output
300 mil width 24-pin plastic Skinny DIP package (Suffix: -P-SK)
300 mil width 24-pin plastic SOJ package (Suffix: -PJ)

PLASTIC PACKAGE
LCC-24P-M02
PIN ASSIGNMENT
(TOP VIEW)

• Pin compatible with MB81C81A

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating
Supply Voltage

Symbol

Value

Unit

AI2
All
AI4
A15

A3
A4
A7

AIO

A6

A9
DOUT

WE

AS
A8
DIN

GND

Cs

Vee

-0.5 to +7.0

V

Input Voltage on any pin with to GND

V,N

-0.5 to +7.0

V

Vvo

-0.5 to +7.0

V

Power Dissipation

Po

1.0

W

Output Current

lOUT

Temperature under Bias

TSIAS

-10to +85

fc

Storage Temperature

TSTG

-40 to +125

'c

±20

mA

Permanent device damage may occur if the above Absolute Maximum
Ratings are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.

Copyrighl© 1989 FUJITSU

Vee

AO
AI

AI3

Output Voltage on any pin with to GND

NOTE:

AI6

A17

A2

This device contains circuitry to prated the inputs against

damage due 10 high Itatic voltages or electric fields.
Howaver, iI Is advised that normal precautions be taken to

avoid application of any vollage higher than maximJm rated
voltages to this high i1Jl)edance circuit

LIMITED

2-65

MB82B81-15
MB82B81-20
Fig. 1 - MB82B81 BLOCK DIAGRAM

AO
~VCC

Al
~GND

A2

Row
Select

A3

266 x 256 x 4

Memory Cell Array

A4
AS

A6

A7

Column

1/010-----;
1/020-------1

&

1/030------1

I/O Circuits

1/04.0-----;

I/O
Buffer
Column Select

Power Down
Circuit

CAPACITANCE {Ta=25 °C, f=1MHz)

2-66

MB82B81-15
MB82B81-20

PIN DISCRIPTION
Symbol

Symbol

Pin name

AO to A17

Pin name

Address input.

WE

Write Enable.

DIN

Data input.

VCC

Power Supply(+5V±10%).

DOUT

Data output.

GND

Ground.

TRUTH TABLE
es

WE

H

X

L
L

Output

Power Supply Current

Not Selected

High-Z

Standby

L

Write

High-Z

Active

H

Read

DOUT

Active

Mode

Legend: H=High level,

L=Low level,

X=Don't care

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter

Symbol

Min

Typ

Max

Supply Voltage

vec

4.5

5.0

5.5

Ambient Temperature

TA

0

70

Unit
V

°c

2-67

MB82B81-15
MB82B81-20

DC CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
Parameter

Test Conditions

Symbol

Min

Max

Unit

Input Leakage Current

VIN=GND to VCC
VCC=max.

ILl

-5

5

llA

Output Leakage Current

VOUT=GND to VCC
CS=VIH or WE=VIL

ILI/O

-5

5

llA

Operating Supply Current

CS=VIL, DOUT=Open
Cycle=min.
VCC-min. to max.
CS=VCC-0.2V, VINSO.2V
or VI~VCC-0.2V

ICC

120

rnA

ISBI

15

rnA

CS=VIH
VCC=min. to max.

ISB2

30

rnA

Standby Supply Current
Standby Supply Current
Input High Voltage

VIH

2.2

6.0

V

Input Low Voltage

VIL

*1
-0.5

0.8

V

2.4

Output High Voltage

IOH=-4rnA

VOH

Output Low Voltage

IOL=8rnA

VOL

V
0.4

V

VCC=GND to 4.5V
CS=Lower of VCC or
IPO
50
rnA
VIH min.
Note: *1 -2.0V min. for pulse w1dth less than 20ns.
*2 The CS input should be connected to VCC to keep the device deselected.
Peak Power-on Current *2

Fig. 2 - AC TEST CONDITIONS
• Input Pulse Levels:
0.6V to 2.4V
• Input Pulse Rise & Fall Time: Ins (Transient between 0.8V and 2.2V)
• Timing Reference Levels:
Input: VIL=0.8V, VIH=2.2V
Output: VOL=0.8V, VOH=2.2V
• Output Load
5V
480n
Dout

o-------~----~

25512

* Including Scope and jig capacitance

tWZ

2-68

MB82B81-15
MB82B81-20

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE
Parameter

Symbol

Read Cycle Time
Address Access Time
/CS Access Time
Output Hold from Address Change
Output Low-Z from /CS

tRC
tAA
tACS
tOH
tLZ

Ont-nllT 1-H o-h-7. .frnm

Irs,

I tPU
I tPD

MB82B8l-20
Min
Max
20
20
20
3
3

R

-t-H7

I Power Up from /CS
I Power Down from /CS

READ CYCLE TIMING DIAGRAM

MB82B8l-l5
Min
Max
15
15
15
3
3

I
I

0

Unit
ns
ns
ns
ns
ns

1n

nc

15

ns
ns

0

I

15

*1

READ CYCLE ·3

""'$
DOUT

~'"'I"-==========_IR_C'_22-_-_-_-_-_-_-_-8---1. 4~:;;rt
PREVIOUS DATA VALID

•. •.

i ..••••••••••.••.••..•••............

DATA VALID

READ CYCLE: CS CONTROLLED·4

ADDRESS

HIGH-Z

HIGH-Z
DOUT

SUPPLY

~M~T

Icc _ _ _ _ _

F'::'?--_---------~:===::-IP-D--------~1.--I-50-'%-~~

~

~

~

Undefined

1;·.1

Don'l Care

Note: *1 WE is high for Read cycle.
'~2 All Read cycle timings are referenced from the last valid address
to the first transitioning address.
*3 Device is continously selected, CS=VIL.
'~4 Address valid prior to or coincident with CS transition low.
*5 Transition is measured at the point of ±500mV from steady state voltage.

2-69

MB82B81-15
MB82B81-20
WRITE CYCLE

Parameter
Write Cycle Time
Address Valid to End of Write
ICS to End of Write
Data Setup Time
Data Hold Time
Write Pulse Width
Write Recovery Time
Address Setup Time
Output Low-Z from IWE
Output High-Z from IWE

Symbol
tWC
tAW
tCW
tDW
tDH
tWP
tWR
tAS
tOW
tWZ

MB82B81-15
Min
Max
15
12
12
4
0
11

1
0
0

MB82B81-20
Min
Max
20
17
17
9

2
16
3
0
0

6

8

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

WRITE CYCLE TIMING DIAGRAM *1

WRITE CYCLE I: WE CONTROLLED

ADDRESS

DIN

Dour

~

Undefined

Iw&1I

Don't Care

Note: *1 CS Or WE must be high during address transitions,
*2 If CS goes high simultaneously with WE high, the output remains in high
impedance state,
*3 All Read cycle timings are referenced from the last valid address to
first transitioning address,
*4 Transition measured at ±500mV from steady state voltage with specified
load in Fig. 2.

2;...70

MB82B81-15
MB82B81-20
WRITE CYCLE TIMING DIAGRAM (Continued) ·1·2·4
WRITE CYCLE 11: CS CONTROLLED "1"2

ADDRESS
...

--------IAW--------~
lAS

......- - - - - leW -----~

CS

~-----~p-----~

mH?

DIN

. I~-" 1DW~
?()X<)X<)X()X<)X<~~------DA-~-V-AL-,D----~
~

Note:

Undefined

Im@1

Don'tCare

"I ~ or "WI: must be high during address transitions.
"2 If CS goes high simultaneously with WE high, the output remains in high impedance slate.
"3 All Write cycle timings are referenced from the last valid address to the first transitioning address.

2-71

MB82B81-15
MB82B81-20

PACKAGE DIMENSIONS
(Suffix:-P-SK
24-LEADS PLASTIC DUAL-IN LINE PACKAGE
(CASE No.:DIP-24P-H03)

~=======1~1soMAX
.300(7.62)

TYP

.010t.002
(0.2StO.osl

.050(1.271
MAX
.100(2.5411 1

.018t.003
(0.46tO.081

TYP
C)1~88

Dimensions In
inches (millimeters)

FUJITSU LIMITED D24017S·3C

24-LEADS PLASTIC SOJ PACKAGE
CASE No.: LCC-24P-H02)
,.-

111
"1 ~~.

0::::;

005
(8.64: 0.131
.273'.020
(6.93tO.51 )

i)J.
.0SOt.00S
11.27:0.131
.5S0(13.97IREF

I-

.091{2.31I
NOM

.02S(0.64)
MIN

.144(3.661
MAX

••615'.005(15.62±0.13)

~nnnlffiimnnn nn
• : This dimension Includes resin protrusion. (Each side: .006(0.15)MAX.)
01_ FUJITSU UMITED C24052S·1C

2-72

'Oimensions in
inches (,millimeters)

11111111111111111111111111111111111111111111

fUJITSU

CMOS 262144-BIT BI-CMOS
STATIC RANDOM ACCESS MEMORY

MB82B84-15
MB82B84-20

11111111111111111111111111111111111111111111

TS268-B893
256K-BIT(65,536 X 4) Bi-CMOS HIGH SPEED STATIC
March 1989
RANDOM ACCESS MEMORY WITH AUTOMATIC POWER DrO~WN~________~
The Fujitsu MB82B84 is a 65,536-words by 4-bits static
random access memory fabricated with a CMOS silicon
gate process. To make power dissipation low~r and high
speed, peripheral circuits consist of Bi-CMOS technology, and to obtain smaller chip size, cells consist
MB82B84 has 300mil plastic DIP and plastic small outline J-Iead(SOJ) as package option. The memory utilizes
asynchronous circuitly and requires +5V power supply.
All pins are TTL compatible.

p::O'\J p,~r1GI:

PLASTIC PACKAGE

DIP-24P-H03

The MB82B84 is ideally suited for use in large compute
and other applications where fast access time, large
capacity and ease of use are required.
All devices offer the advantages of low power dissipation, low cost high performance.
PLASTIC PACKAGE
LCC-24P-M02

• 65,536 words x 4 bits organization
• Fast access time:
tAA=tACS=15ns max (MB82B84-15)
tAA=tACS=20ns max.(MB82B84-20)
• Bi-CMOS peripheral
• TTL compatible inputs/outputs
• Completely static operation: No clock required
• Three-state output
• Common data input/output
• Single=5V(±10%) power supply with low current drain
Active operation
= 120mA max.
Standby operation = 15 mA max. (CMOS level)
Standby operation = 25 mA max. (TTL level)
• Standard 24-pin plastic DIP package : Suffix -P-SK
• Standard 24-pin plastic SOJ package : Suffix -PJ
• Pin compatible with MB81C84A

ABSOLUTE MAXIMUM RATINGS

(See
Rating
Symbol
Supply Voltage
VCC
Input Voltage
VIN
Output Voltage
VI/O
Output Current
lOUT
Power Dissipation
PD
Temperature Under Bias
TBIAS
Storage Temperature Range TSTG

Note)
Values
-0.5 to +7.0
3.5 to +7.0
-0.5 to +7.0
±20
1.0
-10 to +85
-40 to +125

Unit
V
V

PIN ASSIGNMENT
(TOP VIEW)

A15
AO
Al
A2
A3
A4
A7
A6
AS
A8
CS
GND

C
C
C
C
C
C
C
C
C
C
C
C

I '-'24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10 15
11 14
12 13

:JVCC
:JA14
:JA13
:JA12
:JA11
:JAI0
:JA9
:J 1/04
:J 1/03
:J 1/02
:J 1/01
:JWE

V

mA
W

uc

(DIP & SOJ Package)

~C

This device contains circuitry to protect the

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

inputs against damage due to high static volt·
ages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi.
mum rated voltages to this high impedance
circuit.

2-73

MB82B84-1.5
MB82B84-20
Fig. 1. - MB82B84 BLOCK DIAGRAM

AO
~VCC

A1
~GND

A2

Row
Select

A3

256 x 256 x 4
Memory Cell Array

A4
A5
A6

A7

Column

1/010-------1
1/02,0-------1

&

1/03,0-------1

I/O Circuits

1/04.0-------1

110
Buffer

Column Select

Power Down
Circuit

CAPACITANCE (Ta=25°C. f=l.MHz)
Parameter
I/O Capacitance (VI/O=OV)
Input Capacitance(V/CS=OV)
Input Capacitance(VIN-OV)

2-74

Symbol
CI/O
C/CS
CIN

Min

Typ

Max
8

6
5

Unit
pF
pF
pF

MB82B84-15
MB82B84-20

PIN DISCRIPTION
Symbol

Pin name

AO to A15
1/01 to 1/04
CS

Symbol

Pin name

Address input.

WE

Write Enable.

Data input/output.

VCC

Power Supply(+5V±10%).

Chip Select 1.

GND

Ground.

TRUTH TABLE
CS

WE

Mode

H

X

Standby

L

L

L

H

Power Supply Current

I/O pin
High-Z

Standby

Write

DIN

Active

Read

DOUT

Active

Legend: H=High level,

L=Low level,

X=Don't care

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter

Symbol

Min

Typ

Max

Supply Voltage

VCC

4.5

5.0

5.5

Ambient Temperature

TA

0

70

Unit
V

°c

2-75

DC CHARACTERISTICS

MB82B84-15
MB82B84-20

.

(Recommend e d operat1llg condi·
t~ons oth erw~se noted )

Parameter

Test Conditions

Symbol

Min

Max

Unit

Input Leakage Current

VIN=GND to VCC
VCC=max.

ILl

-5

5

pA

Output Leakage Current

VI/O=GND t~VCC
CS=VIH or WE=VIL

ILI/O

-5

5

pA

Operating Supply Current

CS=VIL, I/O=Open
Cycle=min.
VCC-min. to max.
CS=VCC-0.2V, VINSO.2V
or VI~VCC-0.2V

ICC

120

mA

ISBI

15

mA

ISB2

25

mA

Standby Supply Current
Standby Supply Current

CS=VIH
VCC=min. to max.

Input High Voltage
. Input Low Voltage

VIH

2.2

6.0

V

VIL

*1
-0.5

0.8

V

2.4

Output High Voltage

IOH=-4mA

VOH

Output Low Voltage

IOL=8mA

VOL

V
0.4

V

VCC-GND to 4.5V
CS=Lower of VCC or
IPO
50
mA
VIH min.
Note: *1 -2.0V min. for pulse w~dth less than 20ns.
*2 The CS input should be connected to VCC to keep the device deselected.
Peak Power-on Current *2

Fig. 2 - AC TEST CONDITIONS
• Input Pulse Levels:
0.6V to 2.4V
• Input Pulse Rise & Fall Time: 3ns(Transient between 0.8V and 2.2V)
• Timing Reference Levels:
Input: VIL=0.8V, VIH=2.2V
Output: VOL=0.8V, VOH=2.2V
• Output Load
5V
48012
Dout

o-------.-----~

25512

* Including Scope and jig capacitance

2-76

MB82B84-15
MB82B84-20

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE
Parameter

Symbol

Read Cycle Time
Address Access Time
ICS Access Time
Output Hold from Address Change
Output Low-Z from ICS

tRC
tAA
tACS
tOH
tLZ
t!!Z
tPU
tPD

Gu~Eu.t: }I~g~-Z

f:=:;=:: /CS

I Power Up from ICS
I Power Down from ICS

READ CYCLE TIMING DIAGRAM

MB82B84-15
Min
Max
15
15
15
3
3

MB82B84-20
Min
Max
20
20
20
3
3
10

II

0

I
I

Unit

0
15

15

I
I

ns
ns
ns
ns
ns
ns
ns
ns

*1

READ CYCLE I .3
ADDRESS

DOUT

HIGH·Z

HIGH·Z

DOUT

SUPPLY
CURRENT

DATA VALID

I tPu~- - - - - - - - - - - r---:-tPo~
__ _
Icc---~--:----~

Icc

Undefined: ~

Don't Car.:

50%

D

Note: *1 WE is high for Read cycle.
*2 All Read cycle timings are referenced from the last valid address
to the first transitioning address.
*3 Device is continous1y selected, CS=VIL.
*4 Address valid prior to or coincident with CS transition low.
*5 Transition is measured at the point of ±500mV from steady state voltage.

2-77

MB82B84-15
MB82B84-20
WRITE CYCLE
Parameter

Symbol

Write Cycle Time
Address Valid to End of Write
/es to End of Write
Data Setup Time
Data Hold Time
Write Pulse Width
Write Recovery Time
Address Setup Time
Output Low-Z from /WE
Output High Z from /WE

tWC
tAW
teW
tDW
tDH
tWP
tWR
tAS
tOW
tWZ

MB82B84-l5
Max
Min
15
10
10
7
3

MB82B84-20
Min
Max
20
15
15
10

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

3

8
2
0
0

10
2
0
0
8

10

WRITE CYCLE TIMING DIAGRAM *1
WRITE CYCLE I: WE CONTROLLED
~------------------twC·3-------------------.,

__

ADDRESS ~~~______________________________________~}-:~.s~~·~1~:~~~'

I--------tcw--------<-I ~

r-------~-------tAw--------------~

f--tAS,---I

t - - - - - twp

------lj,--___________

\\\
r--tOW-i--tOH.11111111111Y

DOUT

YYll~11

DATA VALID

XXXXXX

:=:

~
Undefined:

~

Don't Care:

0

Note: *1 CS or WE must be high during address transitions.
*2 If CS goes high simultaneously with WE high, the output remains in high
impedance state.
*3 All Read cycle timings are referenced from the last valid address to
first transitioning address.
*4 Transition measured at ±500mV from steady state voltage with specified
load in Fig. 2.
*5 If es is in the Read Mode during this period, I/O pins are in the
output state so that the input signals of opposite phase to the outputs
must not be applied.

2-78

MB82B84-1S
MB82B84-20

WRITE CYCLE II: CS CONTROLLED*'*2
~----------------twC·3----------------~

~-------------tAW--------------~

tWR

~tAS1J-·~----tcw----~,,,,-,,,-_ _ _ __

~------tow--------i ~

)(.xxxxxxxxxxxxxxX)

Undefined:

DATA VALID

~

Note: *1 CS or WE must be high during address transitions.
*2 If CS goes high simultaneously with WE high, the output remains in high
impedance state.
*3 All Read cycle timings are referenced from the last valid address to
first transitioning address.
*4 Transition measured at ±500mV from steady state voltage with specified
load in Fig. 2.
*5 If CS is in the Read Mode during this period, I/O pins are in the
output state so that the input signals of opposite phase to the outputs
must not be applied.

2-79

MB82B84-15
MB82B84-20

PACKAGE DIMENSIONS
24-LEADS PLASTIC DUAL-IN LINE PACKAGE
(CASE No.:DIP-24P-H03)

.300±.010
(7.62±0.25)

.010±.002
(0.25±0.05)

.172(4.36)MAX

.118(3.0)MIN
.100(2.54)1
T'fP

.018±.003
(0.46±0.08)

.020(0.51 )MIN
Dimensions in
Inches (millimeters)

e FUJITSU LIMITED 1987 0240175·2C

24-LEAD PLASTIC LEADED CHIP CARRIER
(CASE No.: LCCo24P·M02)

___ ......... ,....,...,,...,,..,,...,,..,t""'I

INDEX

0

dI .... '-' ........................
.050±.005
(1.27±0.13)

~

'Jl

I

'3J. 005
(8.64± 0.13)
.273±.020
(6.93±0.51)

.300(7.62)

J

I~~

I r--

.09112.31)
NOM

.550(13.97)REF

.025(0.64)
MIN
.144(3.66)
MA x

•. 615±.005(15.62±0.13)
Details of "A" P8rt9032(0'81)MAX
.102(2.60)
NOM

'-="-""=::-1

~.!...::.:=::...J

* : This dimensiQn includes resin protrusion. (Each side: .006(O.15)MAX.)
0111B8 FUJITSU LIMITED C240!i2S-1C

2-80

~

I

.017±.004
(O.43:tO.l0)

?r!c~:~S:;;'~:li~eters).

Section 3

Low Power CMOS SRAMs I
Uaxlmum

At a Glance

Acce..
Page

Device

3-3

MB8464A~LL

-I01ULL
-151ULL
3--15

MB84256-10/ULL
-121ULL
-151ULL

3--25

MB84256A-7OIULL

-101UlL
-121ULL
-151UlL

TIme (ns)

Capsdty

Package
Options

80

65536 bits
(8192wx 8b)

28-pin Plastic
DIP, FPT
32-pad Ceramic Lee

100
120
150

262144 bits
(32768w x Bb)

28-pin Plastic
DIP, FPT
32-pad Ceramic Lee

70
100
120
150

262144 bits
(32768w x 8b)

28-pin

Plastic

DIP, FPT

100
150

3-35

MB84F256--25

250

262144 bits
(32768w x 8b)

28-pin

Plastic

DIP, FPT

3--47

MB841 ()()(H!()/l
-lOlL
-121L

80

1048576 bits
(131072w x 8b)

32-pin

Plastic

DIP, FPT

100
120

3-1

Low Power CMOS SRAMs

3-2

Static RAM Data Book

11111111111111111111111111111111111111111111111111111111111111111

FUJITSU

CMOS 65536-BIT
STATIC RANDOM
ACCESS MEMORY

MB B464A·80/80L/80LL
MB 8464A.l 0/1 OL/l OLL
MB 8464A.15/15L/15LL

11111111111111111111111111111111111111111111111111111111111111111

March 1987
Edition 2.0

8,192 WORDS x 8 BIT CMOS STATIC RAM WITH
LOW POWER AND DATA RETENTION
The Fujitsu MB S464A is a S192-word by S-bit static random access memory
hhrir.~tp.rl

with

;t

loMOS sillicon Qate orocess. The memory utilizes

asvnchro~

nous circuitry and may be maintained in any state for an indefinite period of
time. All pins are TTL compatible, and a single 5 volts power supply is required.
The MB 8464A is ideally suited for use in microprocessor systems and other
applications where fast access time and ease of use are required. All devices
offer the advantages of low power dissipation, low cost, and high performance.
•
•

•
•
•
•
•
•

•

•
•
•
•

Organization: S192 words x S bits
Fast access time: SO ns max. (MB 8464A-SO/SOLISOLL)
100 ns max. (MB 8464A-l0/l0Lll0LL)
150 ns max. (MB 8464A·15/15L115LL)
Completely static operation: No clock required
TTL compatible inputs/outputs
Three-state output
Common data input/output
Single +5V power supply, ±10% tolerance
Low power standby: llmW max. (MB B464A·SO/l0/15)
0.55mW max. (MB 8464A-SOLll0Ll15L)
0.55mW max. (MB S464A-SOLLll0LLl15LL)
Data retention current: lmA max. (MB B464A-SO/l0/15)
251lA max. (MB 8464A-SOLll0Ll15L)
21lA max. at O°C to 40°C
(MB S464A-SOLLll0LLl15LL)
Data retention: 2.0V min.
Standard 2S-pin DIP (300mil width) (Suffix: P-SK)
(600mil width) (Suffix: P)
Standard 2S-pin bend-type Flat package (450mil width) (Suffix: PF)
Standard 32-pad LCC (Suffix: CV)

PLASTIC PACKAGE
DIP-28P-M02

PLASTIC PACKAGE
DIP-28P-M04

o

PLASTIC PACKAGE
FPT-28P-M02

CERAMIC PACKAGE
LCC-32C-A02

PIN ASSIGNMENT

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Symbol

Rating

Value

Unit

-0.5 to +7.0

V

Supply Voltage

Vee

Input Voltage

-0.5* to Vee+0.5

V

Output Voltage

VIN
V OUT

-0.5 to Vcc+0.5

V

T-emperature Under Bias

T BIAS

-10 to +S5

°c

A,
,~,

Storage Temperature
Range

ICERAMIC
I PLASTIC

TSTG

-65 to +150

~.;

9:

A,

H!;

Ao

Tl,

Ne I"

°c

-45 to +125

liD, GND 110. 110"
liD.,

*-2.0V for pulse width less than 20ns.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

NC

110.,

This device contains circuitry to protect the

inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-

mum rated voltages to this high impedance
circuit.

3-3

1IIIIIIIIIIImlillmllllllllllllllllllllllllilim

MB 8464A-80/80L/80LL

IWI~I~I;III

:: ::~::: ~ ~~~ ~t~~ ~tt

Fig. 1 - MB 8464A BLOCK DIAGRAM

- - - 0 Vee

'---

~

----0 GND

256 x 32 x 8

ROW
DECODER

ADDRESS
BUFFER

MEMORY CELL
ARRAY

-

'---

l

ics

I
1/0 GATE
&

ADDRESS
BUFFER

COLUMN DECODER

res

I

I

-

DATA 1/0 BUFFER

BUFFER
~

/cs

CS

1111 1 111

TRUTH TABLE
CSI
H

CS2

OE

WE

MODE

SUPPLY CURRENT

1/0 PIN

X

X
X

NOT SELECTED

IS8

HIGH·Z

NOT SELECTED
DOUT DISABLE

IS8

HIGH·Z

H

Icc

HIGH·Z

Icc
Icc

DOUT

X

L

X
X

L
L

H
H

H
L

L

H

X

READ

H
L

WRITE

DIN

CAPACITANCE (TA = 25°C, f = 1MHz)
Parameter
I/O Capacitance

(V IIO = OV)

Input Capacitance (V IN = OV)

3-4

Symbol

Min

Typ

Max

Unit

CliO

8

pF

C IN

6

pF

MB 8464A-IO/IOL/IOLL

:= ::::::~ gj~ gtj~ gtt

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Symbol

Min

Typ

Max

Unit

Supply Voltage

Vee

4.5

5.0

5.5

V

Input Low Voltage

V IL

-2.0'

O.B

V

Input High Voltage

V IH

2.2

Vee+ 0.3

V

Ambient Temperature

TA

0

70

°c

Parameter

*-2.0 V Min for pulse width less than 20 ns. (V IL Min. = -0.3 V at DC level)

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
MB 8464A·
80/10/15

Symbol

Parameter

Min

Max

MB 8464A·80L/BOLL
10L/l0LL/15L115LL Unit
Min

Test Condition

Typ

Max

l/LA

0.1

rnA

CS 2 ~ 0.2V, CS, ~ Vee-0.2V
(CS 2 ~ 0.2V or CS 2 ~ V ee -0.2V)

19B ,

2

ISB2

3

3

rnA

CS, = V IH or CS 2 = V IL

Active Supply Current

lee1

50

50

rnA

CS, = V IL , CS 2 = V IH
V IN = V IH or V IL , lOUT = OmA

Operating Supply Current

lee2

60

60

rnA

Input Leakage Current

ILl

-1

1

-1

-1

/LA

V IN = OV to Vee

Output Leakage Current

I Lila

-2

2

-2

2

/LA

Vila = OV to Vee
CS, = V IH or CS2 = V IL or
OE=V IH orWE=V IL

Output High Voltage

V OH

Output Low Voltage

VOL

Standby Supply Current

2.4

2.4
0.4

0.4

Cycle = Min., Duty = 100%
lOUT = OmA

V

IOH = -1.0mA

V

IOL = 2.1mA

Note: All voltages are referenced to GND

Fig. 2 - AC TEST CONDITIONS

< Output Load>
+5V

• Input Pulse Levels:
• Input Pulse Rise and Fall Times:
• Timing Reference Levels:

0.6V to 2.4V
5ns (Transient Time between 0.8V and 2.2V)
Input:
V IL = 0.8V, V IH = 2.2V
Output: VOL = 0.8V, V OH = 2.0V
DOUT
(I/O)

• Output Load:
Parameters Measured

Load I 1.8Kn
Load" 1 .8Kn

990n

100 pF

990n

5 pF

tCLZ. tOLZ. tCHZ. tOHZ. tWLZ and tWHZ

o-----1r-----t
I
C L'

!

*Including jig and stray capacitance

3-5

IIWIIIIIIWIIIIIIIIIIWIIIIWIIIIIWIIIIIIIIII

MB 8464A.BO/80L/80LL

FUJITSU
1111111111111111111111111111111111111111111111111111

::

::::::

~ ~~~ ~t~~ ~tt

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
READ CYCLE

Symbol

Parameter

MB 8464A80/80l/80LL

MB 8464A10/10l/10LL

MB 8464A15/15l/15LL

Min

Min

Min

Max

100

tRC

150

Address Access Time

tAA

80

100

150

ns

CS, Access Time

tAC'

80

100

150

ns

CS2 Access Time

tAC2

80

100

150

ns

Output Enable to Output Valid

tOE

55

ns

Output Hold from Address Change

tOH

10

10

10

ns

Chip Select to Output Low-Z"

tCLZ

10

10

10

ns

Output Enable to Output Low-Z"

tOLZ

5

Chip Select to Output High-Z"

tCHZ

35

35

40

ns

tOHz

30

35

40

ns

45

35

5

ns

5

ns

READ CYCLE TIMING DIAGRAM'2
READ CYCLE I

'3

,o,,'~ ~t--_;-=-=='O=H=-='A-A----'R-: -- -,__--..~~___
1 x x1
DOUT

PREVIOUS DATA VALID

~

_

_

X

DATA VALID

READ CYCLE il*4

ADDRESS

~

-------~tRC--------I-I

_ _

----JX"'---_

1--- - - - ' A A - - - - 1

CS,

OE

DOUT

Note: *1
*2
*3
*4

3-6

Unit

Max

Read Cycle Time

Output Enable to Output High-Z"

80

Max

Transition is measured at the point of ±500mV from steady state voltage_
WE is high for Read Cycle_
Device is continuously selected, CS, = OE = V'L, CS2 = V'H'
Address vaild prior to or coincident with CS, transition low, CS 2 transition high.

MB 8464A-SO/80L/80LL

I I I I I I I I I I I I I I I I I ~I I I I I I I I

:: ::~::: ~ ~~~ ~t~~ ~tt IIIU~I~III;IIII

WRITE CYCLE

Parameter

...

".

-

VWlllC

'-"-

-,

-

vy\..lt

Symbol

..,.."--'''"1;;

'we

MB 8464A·
80/80L/80LL

MB 8464A·
10/10L/l0LL

MB 8464A·
15/15L/15LL

Min

Min

Min

Max

on

.nn

60

80

Address Valid to End of Write

tAW

Chip Select to End of Write

tew

60

Data Valid to End of Write

tow

30

Data Hold Time

tOH

Write Pulse Width

twp

Address Setup Time

t AS

Max

I

.en

Unit

Max

I

-".

100

ns

80

100

ns

35

40

ns

5

5

5

ns

60

70

90

ns

0

0

0

ns
ns

Write Recovery Time

tWR

10

10

10

Write Enable to Output Low·Z"

tWLZ

5

5

5

Write Enable to Output High·Z"

tWHz

30

ns

35

40

ns

WRITE CYCLE TIMING DIAGRAM *2

WRITE CYCLE I: WE CONTROLLED
'we
ADDRESS

I

~

'AW
~'WR--I
1///. / / / / / / / / / / / / / / / / / / / / 1/// / / / / / / //

cs,
CS2

'\'\'\\. !'\. '\. '\.

'ew

i

r/ / / / / / / / / / /
'ew

I
/////// F

l"'-'\\.\.\.\.'\.\.\.\.\.
'WP

I--'AS--j
WE

,'\.'\.'\.
r--'owHIGH·Z

~

DOUT

~

HIGH·Z

DATA IN VALID
tWHZ "

~."
tWLZ

HIGH·Z

I

Note: *1 Transition is measured at the point of ±500mV from steady state voltage.
*2 If OE, CS, and CS 2 are in the READ Mode during this period, I/O pins are in the output state so that the
input signals of opposite phase to the outputs must not be applied.

3-7

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

MB 8464A-BO/80L/80LL
0.1 0 / 0
: : ::::::

~ 5/~ 5b~ 5~~

WRITE CYCLE II: CS, CONTROLLED"'
twc

I

ADDRESS

tAW

////

////////////////////
~

tcw

////

/////

t---tWR-

CSt
tcw
CS2

\.\.\.\.\.\.\.\.\.\.

//////
twp

-//

"" "

/

/////

r-toW-~tDH

HIGH-Z

HIGH-Z

DATA IN VALID

~'3
HIGH·Z

tWHZ*3

~

HIGH-Z

DOUT

WRITE CYCLE III: CS 2 CONTROLLED"2
twc

I

ADDRESS

tAW

/// ////

/////

/////////

//

///LL

tcw

CS,

\.\.\.\.

\.\.

////

~

tcw

/////

-twR-

CS2

twp
WE

""'" '"

////

r---

HIGH-Z

HIGH-Z

'3

////

~tOH

DATA IN VALID
tCLZ

DOUT

tow -

HIGH-Z

tWHZ -3

~

HIGH-Z

Note: '1 If OE, CS2 and WE are in the READ Mode during this period, I/O pins are in the output state so that the
input signals of opposite phase to the outputs must not be applied.
*2 if OE, CS, and WE are in the READ Mode during this period, I/O pins are in the output state so that the
input signals of opposite phase to the outputs must not be applied.
*3 Transition is measured at the point of ± 500mV from steady state voltage.

3-8

MB S464A.SO/SOL/SOLL

:: ::::::~ ~;~ ~b~ ~~~

1111111111111111111111111111111111111111111111111

FUJITSU
1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImlllllili

DATA RETENTION CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Parameter
Data Retention Supply Voltage

Symbol

Min

V OR

2.0

Typ

Max

Unit

5.5

V

1.0

mA

1.0

25

tJA

1.0

2.0

tJA

Standard
Data Retention
Supply Current'2

L·Version

lOR

LL.Version '3
Data Retention Setup Time

tORS

Operation Recovery Time

tR

Note: *2 CS2 controlled: V OR = 3.0V, CS 2
CS, controlled: V OR = 3.0V, CS,

~
~

O.2V
VOR-O.2V (CS 2

~

0

ns

tRe

ns

O.2V or CS 2 ~ VoR -O.2V)

*3 VDR=3.0V, TA=O°C to 40°C

DATA RETENTION TIMING
DATA RETENTION I: CS, CONTROLLED

4.5V

<:5,

4.5~t

\_-----.:.~- - - - - j

Vee

r-

DATA RETENTION MODE

tDRS -

tRi

~1!J"".2""v"'r-\lr-""

<:5,

n,.
. . .~f.,2
. .......2V,..,

~ VDR-O.2~

DATA RETENTION II: CS 2 CONTROLLED
i------DATA RETENTION MODE-----j

4.5V

Vee

4.SV

\ '- _ _ _ _ _ _
V_
OR _ _ _ _ _ .JI

3-9

mllllllllllillmllllllllllllllllllllllm~m MB 8464A-80/80L/80LL

1111• •111 :: :::::: ~ g~~ gt~~ gtt

PACKAGE DIMENSIONS
(Suffix: PI
28·LEAD PLASTIC DUAL·IN'LlNE PACKAGE
(CASE No.: DIP·28p·M021

I

.543±.010

INDEX

1~========:::::S;;;::;==:::::;-;z:'==========jIJ"'"

.600(15.24)TVP

f------l.407~:~~~(35.73~~:~)-----.1

Dimensions in
inches (millimeters)

© 1986 FUJITSU LIMITED D28006S·2C_

3-10

MB 8464A.BO/BOL/80LL

1111111111111111111111111111111111111111111111111

:: ::::::~ g:~ g~:~ g~~ IIIII~;III
PACKAGE DIMENSIONS
(Suffix: P·SK)
28·LEAD PLASTIC DUAL·IN·LlNE PACKAGE
(CASE No.: DIP·28P·M04)

,::,::i;: :~,,:cr: .:,: :: :0: : ]5"~~
1.392~~~~(35.36~~:;)

I

.100(2.54)
TYP

I

©1986 FUJITSU LIMITED 02B018$-2C

I

.300(7.62)TYP

.010±.002
(0.25±0.05)

.018±.003
(0.46±0.08)

Dimensions in
inches (millimeters)

3-11

MB 8464A-80/80L/80LL
FUJITSU MB 8464A-l Oil OLll OLL
mlllllllllllllllllllillmllllrnlillmllllill MB 8464A-15/15L/15LL

1IIIIIIIIIIIIIIIIIIIIIIIImmlllllllllllllllili

PACKAGE DIMENSIONS
(Suffix: PF)
28-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-28P-M02)
OIO)MIN
ISTAND OFF)

1

View "A"

.339±.008
18.6±0.2)

INDEX

d

~=n=;:;:::;::;=r=r=n=r;:=n==n=iT=n=;:;~

J

.465±.012
111.8±0.3)

.402±.012

~ ..,

I

--I
f----

© 1987 FUJITSU LlMITEDF28011S-2C

3-12

J'"

.006±.002
10.15.0.05)

.00810.18)
MAX
.02710.68)
MAX

.11012.8)MAX

Dimensions in
inches (millimeters)

MB 8464A-BO/BOl/BOll
MB 8464A-l 0/1 Ol/l Oll
MB 8464A-15/1 5l/15ll

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS
(Suffix: CV)
32-PAD CERAMIC (METAL SEAL) LEADLESS CHIP CARRIER
(CASE No_: LCC-32C-A02)

'PIN NO.1 INDEX

C.040(1.02)TYP
(3PLCS)

.360(9. 14)TYP
C.015(0.38)TYP

l

.460(11.68)
TYP

.400(10.16)J
TYP

-.l

.065(1.65)
TYP

I
.085(2.1~

MAX

.050+.006
(1.27±0.15)

.300(7.62)TYP

Dimensions in inches

(millimeters)

* Shape of PIN NO.1 INDEX: Subject to change without notice.
©1987

FUJITSU LIMITED C32011S-3C

3-13

Low Power CMOS SRAMs

..

3-14

Static RAM Data Book

MB 84256-10/10LllOLL
MB 84256-12112L/12LL
MB 84256-15/15L/15LL
August 1986
Edition 2.0

256K-BIT (32,768 x 8) CMOS STATIC RANDOM ACCESS
MEMORY WITH DATA RETENTION AND LOW POWER
The Fujitsu MB 84256 is a 32,768-word by 8-bit static random access memory fabricated with a CMOS silicon gate process. The memory utilizes asynchronouse circuitry and may be maintained in any state for an indefinite period of
time. All pins are TTL compatible, and a single +5 volts power supply is reo
quired.
The MB 84256 is ideally suited for use in microprocesser systems and other
applications where fast access time and ease of use are required. All devices
offer the advantages of low power dissipation, low cost and high performance.

•
•
•
•
•
•
•

•
•
•
•

32,768 x 8 bits
Organization:
Fast access time: 100 ns max. (MB 84256·10/10L/l0LL)
120 ns max. (MB 84256·12/12L/12LL)
150 ns max. (MB 84256·15/15L/15LL)
Completely static operation: No clock required
TTL compatible inputs/outputs
Three·state outputs
Single +5V power supply, ±10% tolerance
Low power standby:
CMOS level: 5.5 mWmax. (MB84256-10/12/15)
0.55 mW max. (MB 84256·10L/l0LL/12L/12LL/
15L/15LL)
TTL level:
16.5 mW max. (MB 84256·10/10L/l0LL/12/12L/12LL/
15/15L/15LL)
Data retention: 2.0V
Standard 28'pin DIP (600 mil) (Suffix: ·P)
Standard 28'pin Bend·type Plastic Flat Package (450 mil) (Suffix: -PF)
Standard 32·pad LCC (Suffix: ·CV)

PLASTIC PACKAGE PLASTIC PACKAGE
DIP·2BP-M02
FPT·28p·M02

o

CERAMIC PACKAGE
LCC·32C·A02

PIN ASSIGNMENT

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating

Symbol

Value

Unit

Supply Voltage

Vee

-0.5 to +7.0

V

Input Voltage

V 1N

-0.5 to Vee+0.5

V

Output Voltage

VOUT

-0.5 to Vec+0.5

V

Temperature Under Bias

T slAs

-10 to +85

°c

Storage
Temperature Range

-65 to +150

CERAMIC

°c

TSTG
PLASTIC

-40 to +125

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATI NGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-

mum rated voltages to this high impedance
circuit.

3-15

!UMlml~i~II~~~~im . MB
FUJITSU

1~~!I~~mll~IMOO~lil~!

84256.10/10L/lOLL
MB 84256.12/12L/12LL
MB 84256.15/15L/15LL

Fig. 1 - MB 84256 BLOCK DIAGRAM

r--

r--

·

ADDRESS
BUFFER

ROW
DECODER

·
·

----aVcc
--DGND

512x64x8
MEMORY CELL
ARRAY

.
.
r-

f---

..

0---ADDRESS
BUFFER

.

1

Ics

.

1

1/0 GATE &
COLUMN DECODER

lcs

. . .

I

OE
BUFFER

I
r--- CS

DATA 1/0 BUFFER

lcs

111111 11

TRUTH TABLE

cs

SUPPLY
CURRENT

OE

WE

MODE

H
L

X

X

NOT SELECTED

IS8

1/0 PIN

HIGH·Z

H

H

DOUT DISABLE

HIGH·Z

L

L

H

READ

L

X

L

WRITE

ICC
ICC
ICC

DOUT
DIN

CAPACITANCE (TA = 25°C, f = 1 MHz)
Parameter

I/O Capacitance

(V I/O = OV)

Input Capacitance (V IN = OV)

3-16

Symbol

Min

Typ

Max

Unit

CliO

8

pF

C IN

7

pF

MB 84256.10/1OL/10LL Ilmllllllllmllmlllllmllllllllllllm!11111
MB 84256.12/12L/12LL FUJITSU
MB 84256.15/15L/15LL 1IIIIIImlllllllllllllmlm~~mlm~m~1111

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Symbol

Min

Typ

Max

Unit

Supply Voltage

Vcc

4.5

5.0

5.5

V

Input Low Voltage

V IL

-2.0 •

o.a

V

Input High Voltage

V IH

2.2

Vcc+ 0.3

V

Ambient Temperature

TA

0

Parameter

70

°c

• -2.0 V Min. for pulse width less than 20 ns. (V IL Min = -0.3 V at DC level)

DC CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
Parameter

MB 84256-10/12/15

Symbol

Min

MB 84256-10L/l0LL/
12L/12LL/15LI15LL

Max

Min

Unit

IS81

1

0.1

IS82

3

3

Active Supply
Current

ICCl

45

45

Operating Supply
Current

ICC2

70

70

Input Leakage
Current

ILl

-1

1

-1

1

p.A

Output Leakage
Current

I LI/O

-1

1

-1

1

p.A

Output High
Voltage

VOH

Output Low
Voltage

VOL

Standby Supply
Current

mA

2.4
0.4

0.4

CS:;:':Vcc- 0.2V
CS = V IH
CS

mA

2.4

Test Conditions

Max

~

V IL , V IN = V IH or V IL

IOUT~OmA

Cycle ~ Min.,
Duty ~ 100%, lOUT ~ 0 mA
V IN ~ OV to Vcc
VI/O ~OVtoVcC,CS=VIH'
OE~VIH orWE~VIL

V

IOH

~

-1.0 mA

V

IOL

~

2.1 mA

Note: All voltages are referenced to GND
Fig. 2 - AC TEST CONDITIONS
+~v

?>R1
°OUT
(1101

'~i

>
.:R2

•
•
•
•

Input Pulse Levels:
Input Pulse Rise & Fall Times:
Timing Reference Levels:

0.6V to 2.4V
5ns (Transient between o.av and 2.2V)
V IL ~ o.av, V IH ~ 2.2V
Input:
Output: VOL = o.av, V OH ~ 2.0V

Output Load

* Including Jig and stray capacitance

7fT
Load I

R,
R2
l.BKn 990n

Load II l.BKn 990n

Parameters Measured
CL
100pF except tCLZ. tOLZ. tCHZ. tOHZ. tWLZ and tWHZ
5pF tCLZ. tOLZ. tCHZ, tOHZ. tWLZ and tWHZ

3-17

MB 84256.10/1OL/10LL
MB 84256.12/12L/12LL
MB 84256!!\15/15L/15LL

AC CHARACTERISTICS
IRecommended operating conditions unless otherwise noted.)
READ CYCLE"
Parameter

Symbol

Read Cycle Time
Address Access Time'2
CS Access Time'3
Output Enable to Output Valid
Output Hold from Address Change
Chip Select to Output LoW·Z'4'5
Output Enable to Output LOW·Z'4'5
Chip Select to Output High.Z'4'5
Output Enable to Output High·Z'4'5

t RC
tAA
t AcS
tOE
tOH
tCLZ
tOLZ
tCHZ
tOHZ

MB 84256·10/
10L/l0LL
Min
Max
100
100
100
40
20
10
5
40
40

MB 84256·12/
12L/12LL
Min
Max
120
120
120
50
20
10
5
40
40

MB 84256·15/
15L/15LL
Min
Max
150
150
150
60
20
10
5
50
50

READ CYCLE TIMING DIAGRAM"
READ CYCLE I: ADDRESS CONTROLLED'2
-----------------tRC------------

-----'\~
' ="'"~

_______~

ADDRESS - - - " " " / ' " - - - - - - - - - - - - - - - - - - - " " " \ j r o - - -

DOUT

PREVIOUS DATA

V~

X~
X

1'---DATA VALID

READ CYCLE II: CS CONTROLLED'3
r-------------------tRC----------------~:1~

ADDRESS - - - " ' \ ,..------------------"""'\~~--

DOUT

IKZI : Undenfinad
Note: * 1
*2
*3
*4
*5

3-18

WE is high for Read cycle.
Device is continuously selected, CS = OE = V'L.
Address valid prior to or coincident with CS transition low.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

MB 84256-10/10L/l0LL
MB 84256-12/.12L/12LL
MB 84256-15/15L/15 LL

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImllllllllllllllili

FUJITSU
1111111111111111111111111111111111111111111111111111

WRITE CYCLE"'2
Parameter

Symbol

Write Cycle Time'3

twe

Address Valid to End of Write
Chip Select to End of Write

tAW
tew
tow

Data Valid to End of Write
Data Hold Time

tOH
twp

Write Pulse Width

MB 84256-10/
10l/10LL
Min
Max
100

MB 84256-12/
12l/12LL
Min
Max
120

MB 84256-15/
15l/15LL
Min
Max
150

80
80
40

B5
85

100

0

Address Setup Time
Write Recovery Time'4
WE to Output Low-Z'5'6

tWR

60
0
5

tWLZ

5

WE to Output High-Z'5'6

tWHz

tAs

45
0

ns
ns

100
50

ns
ns
ns
ns

70

0
90

0
5

0
5

5

5

ns

ns
ns

40

40

Unit

50

ns

WRITE CYCLE TIMING DIAGRAM'1'2

WRITE CYCLE I: WE CONTROLLED
twe '3
ADDRESS

-

II

X

).
tAW

~~

r-tWA:J

tew

~j

////////
twp

_lAS,

},.\.

WE

I - - - t o w - f----tOHi
HIGH-Z

~tWHZ'5'6
DOUT

HIGH-Z

DATA VALID

XXXXXXXXX

I--twLZ~

HIGH-Z

XXx.
~

Note: '1
*2
*3
*4
*5
*6

: Undefined

If OE, CS are in the READ Mode during this period, I/O pins are in the output state so that the input signals of
opposite phase to the outputs must not be applied.
If CS goes high simultaneously with WE high, the output remains in high impedance state_
All write cycle are determined form last address transition to the first address transition of the next address.
tWA is defined from the end point of WR ITE Mode.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

3-19

I I I I I I I I I I I I I I I ~I I I I I I I I I I MB 84256.1O/10L/l0LL

1l1i~~I~I;;I~11

::

::~~::~:j~:~j~:~~

WRITE CYCLE II:

cs

CONTROLLED'P2
'we

ADDRESS

'3

1

~

I{
I

'AW

IDI

~

-'WR~

'ew

'WP
~\\

1\ \ \

////////
' D W - !---'DH-

HIGH-Z

DOUT

HIGH-Z

DATA VALID

tCLZ "5"6

HIGH-Z
I

~tWHZ·5.6

X X

HIGH-Z

~

Note: *1
*2

*3
*4
*5

*6

3-20

: Undefined

If OE, CS are in the READ Mode during this period, I/O pins are in the output state so that the input signals of
opposite phase to the outputs must not be applied.
If CS goes high simultaneously with WE high, the output remains in high impedance state.
All write cycle are determined from last address transition to the first address transition of the next address.
tWR is defined from the end point of WRITE Mode.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

MB 84256.10/10L/l0LL
MB 84256.12/12L/12LL
MB 84256.15/15L/15LL

1lllllllllllllllllllmlllllllllllllllmllmlm~
FUJITSU
IIIIII1111111111111111111111111111111111111111111111

DATA RETENTION CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)

Parameter

Symbol

Data Retention Supply Voltage 1

V OR

Min

Max

2.0

5.5

Standard
Data Retention '2
Supply Current

L-Version

Unit
V

1
lOR

mA

50

p.A

5

LL-Version '3
Data Retention Setup Time

tORS

0

ns

Operation Recovery Time

tR

t RC

ns

Note: *1 CS~ V oR -0.2V
*2 V OR =3.0V,CS~VOR-0.2V
*3 V OR = 3.0V, TA = 40°C
DATA RETENTION TIMING

DATA RETENTION

VCC

?~~
&if \
2.2V

____ ____
DATA RETENTION MODE

~~~

,,"W',"

,f---~JL,"~

~
2.2V

3-21

MB 84256.10/10L/l0LL
MB 84256.12/12L/12LL
1IIIIIIIIIIIIIImllllllillmllllllillmllllili MB 84256.15/15L/15LL

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImlllllili

FUJITSU

PACKAGE DIMENSIONS
(Suffix: PI
28-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-28P-M02)

l

.533113.55)

INDEX

1~========:::::S:;;::::===;Z:::.=========iI]·~'
1.389135.28)
1.415135.93)

.590114.99)
.610115.49)

I

.ll62(1.58)MAX

-t--L

W19514.96)MAX

.10012.54)

11813.00)MIN

I

TYP

.02010.511MIN
Dimensions in
inches (millimeters)

© 1986 FUJITSU LIMITED D28006S-1C

3-22

MB 84256.10/10L/l0LL
MB 84256.12/12L/12LL
MB 84256.15/15L/15LL

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS
(Suffix: PF)
28-LEAD PLASTIC FLAT PACKAGE
(CASE No_: FPT-28P-M02)
O(O)MIN
(STAND DFF)

VIEW A

_709(18.0)MAX

..J

.004(0.1)
.008(0.2)
.110(2.8)
MAX

0.07(0.18)
MAX
.027(0.68)
MAX

kfbrn n riM n n Mnn nn D:?g~g:~l

---.J. 1- -- -- -- --- - -.050(1.27)
TYP

--11.·014(0.35)
.022(0.55)

Detail of "A" part
<91985 FUJITSU LIMITED F28011S-1C

Dimensions in
inches (millimeters)

3-23

MB 84256-10/10L/lOLL
FUJITSU MB 84256-12/12L/12LL
111111~lllmllllllllllllllllllllllllllllllllmlll MB 84256-15/15L/15LL

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImlllllili

PACKAGE DIMENSIONS
(Suffix: CV)
3Z·PAD CERAMIC (METAL SEAL) LEADLESS CHIP CARRIER
(CASE No.: LCC-3ZC·AOZ)

'PIN 1 INDEX

/

.04011.02)TVP
13PLCS)

C.Q151O.38)TVP

O,~

.560114.22)

.445111.30)
.460111.68)
.30017.62)TVP

Dimensions in inches

(millimeters)

*Shape of Pin 1 index: Subject to change without notice
©1985 FUJITSU LIMITED C32011S

3-24

111111111111111111111111111111 ~~~~~~~~~~MB84~2~56~A-7~0!7~OL~!7~OL~L~

fUJITSU

CMOS 262 .. 144-BIT STATIC
RANDOM ACCESS MEMORY

MB84256A-IO/IOL/IOLL
MB84256A-12/12L/12LL

111111111111111111111111111111 ~~~~~~~~~~MB~84~25~6A-~15~/1~5L/~15~LL~
TS256-B889
Sept. 1988

256K-BIT (32,768x8) CMOS STATIC RANDOM ACCESS
MEMORY WITH DATA RETENTION AND LOW POWER
The Fujitsu MB84256A is a 32,768-word by 8-bit static random
access memory fabricated with a CMOS sillicon gate process.
The memory utilizes asynchronous circuitry and may be maintained in any state for an indefinite period of time. All
pins are TIT. compatible, and a single +5V power supply is
required.
The MB84256A is ideally suited for use in microprocesser
systems and other applications where fast access time and
ease of use are required. All devices offer the advantages
of low power dissipation, low cost and high performance.
• Organization: 32,768 x 8 bits
• Fast access time:
70 ns max. (MB84256A-70/70L/70LL)
100 ns max. (MB84256A-10/10L/10LL)
120 ns max. (MB84256A-12/12L/12LL)
150 ns max. (MB84256A-15/15L/15LL)
• Completely static operation: No clock required
• TIT. compatible inputs/outputs
• Three state outputs
• Single +5V power supply, ±10% tolerance
• Low power standby :
CMOS level:
5.5 mW max. (MB84256A-70/10/12/15)
0.55 mW max. (MB84256A-70L/70LL/10L/10LL/
12L/12LL/15L/15LL)
TIT. level·
16 5 mW max (MB84256A-70/70L/70LL/10/10L/
10LL/12/12L/12LL/15/15L/15LL)
• Data retention: 2.0V min.
Standard 28-pin DIP (600mil) (Suffix: P)
Standard 28-pin DIP (300mil) (Suffix: P--=SK)
Standard 28-pin Bend-type FPT (450mil) (Suffix: PF)

··
·

ABSOLUTEMAXIMUM RATINGS
Rating
Supp_!y Voltage
Input Voltage
Output Voltage
Temperature. under Bias
Storage Temperature

VCC
VIN
VItO
TBIAS
TSTG

Value

PLASTIC PACKAGE
DIP-28P-M04

PLASTIC PACKAGE
FPT -28P-M02

PIN ASSIGNMENT
pvcc

2.
27
2. A 13
2. ~A.

A'4C 1

A"
A,

3

AS'

4

pm
P

2

A,( 5

(see NOTE)

Symbol

PLASTIC PACKAGE
DIP-28P-M02

A.[ 6

Unit

-0.5 to +7.0
-0.5 to VCC+0.5
-0.5 to VCC+0.5
-10 to +85
-40 to +125

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

V
V
V

uc
"c

A,e 7
A,c •
All 9
Ao' 10

TOP

view

2'
23
22
21

20

pA.

P
pOE
PA,O
pes
A 11

" PUO,
PliO,

lIo,~ 11

I.

12
"°2
I/Ole 13

I. PIIOS

GNQ

IS

1.

17

PIIOs

PliO.

This device contains circuitry to protect the
inputs against damage due to high static volt~
ages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi~
mum rated voltages to this high impedance
circuit.

3-25

'I!UIIIIiUnll

MB84256A-70!70L!70LL
FUJITSU MB84256A-I0/I0L/I0LL
MB84256A-12/12L/12LL
11110111110101 MB84256A-15/15l/15LL

Fig. 1 - HB84256A BLOCK DIAGRAH
AO
Al
A2
A3
A4
AS
A6
A7

ADDRESS
BUFFER

ROW
DECODER

•

256 x 128 x 8
MEMORY CELL ARRAY

•

VCC

-----<)

GND

•

•
CS

A8
A9
AlO
All
A12
A13
A14

-----<)

•

ADDRESS
BUFFER

I/O GATE &
COLUMN DECODER

•
•

CS

•

•

•

OE
BUFFER

DATA I/O BUFFER

CS

WE

CS

Cs

---t>o--@

1/01 1/03
1/05
1/07
1/02
1/04 1/06
1/08

TRUTH TABLE

CS
H
L
L
L

CAPACITANCE

OE

WE

X

X

H

H
H
L

L
X

SUPPLY
CURRENT
ISB
ICC
ICC
ICC

I/O PIN
High-Z
High-Z
DOUT
DIN

(TA=25°C. f=lHHz)

Parameter
I/O Capacitance (VI/O=OV)
Input Capacitance (VIN=OV)

3-26

MODE
Not Selected
DOUT Disable
Read
Write

Symbol
CI/O
CIN

Min

Typ

Max
8
7

Unit
pF

pF

MB84256A-70/70l/70ll
MB84'256A-I0/I0l/I0ll
MB84256A-12/12l/12ll
MB84256A-15/15l/15ll

RECOMMENDED OPERATING CONDITION
(Referenced to GND)
Parameter
Supply Voltage
Ambient Temperature

Symbol

Min

Typ

Max

Unit

VCC
TA

4.5
0

5.0

5.5
70

V
YC

DC CHARACTERISTICS
i'
(Recommend e d operatJ.IJg condt10ns
ath erw1se note d . )

Parameter

Symbol

MBB4256A70/10/12/15
Min

Standby Supply
Current
Active Supply
Current
70
Operating I
Supply
1-10/12/15
Current
Input Leakage
Current

Max

MBB4256A 70L/70LI
/10L/10LL/12L
Unit
/12LL/15L/15LL
Min
Max

Test Condition

ISB1

1

0.1

mA

CS~VCC-0.2V

ISB2

3

3

mA

CS=VIH

ICC1

55

55

mA

BO

BO

ICC2

70

70

-1

ILl

Output Leakage
Current

ILI/O

Input High Voltage

VIH

-1

2.2
-3.0
2.4

1

-1

1

-1

VCC
+0.3
O.B

2.2

1
1

VCC
+0.3
O.B

mA

lID

VIN-VIR or VIL
CS=VIL, IOUT=OmA
Cycle-Min.
Duty=100%
IOUT=OmA

J.lA

VIN=OV to VCC

J.lA

VI/O-OV to VCC
CS=VIH
OE=VIH or WE=VII

V

ic
V
Input Low Voltage
VIL
-3.0 *
Output High Voltage
VOH
2.4
V IOH--1.0mA
Output Low Voltage
VOL
0.4
0.4
V IOL=2.1mA
Note: All voltages are referenced to GND.
*: -3.0V min. for pulse width less than 20 ns. (VIL min. = -0.3V at DC level.)

Fig. 2 - AC TEST CONDITIONS
+5V

• Input Pulse Levels: 0.6V to 2.4V
• Input Pulse Rise & Fall Times:
5ns (Transient between O.BV and 2.2V)
• Timing Reference Levels
Input:
VIL=O.BV, VIH=2.2V
Output: VOL=O.BV, VOH=2.0V
• Output Load

DOUT
(I/O)
R2

7'rr

*

Including Jig and stray capacitance

I
I R1
I R2 I CL I
Parameters Measured
I
I Loadl I 1. BK\2 I 990\2 I 100pF I except tCLZ, tOLZ, tCHZ, tOHZ, tWLZ and tWHZ I
I Load2 I 1. BK\2 I 990\2 I 5pF I tCLZ, tOLZ, tCHZ, tOHZ, tWLZ and tWHZ
I

3-27

!1~ml~III~II!II~1
FUJITSU
!I~I~I~II!IIIDI

MB84256A-70/70L/70LL
MB84256A-I0/I0L/I0LL
MB84256A-12/12L/12LL
MB84256A-15/15L/15LL

AC CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
READ CYCLE *1
MB84256A
MB84256A
MB84256AMB84256ASymbo 70/70L/70LI 10/10L/101l 12/12L/1211 15/15L/15LI Unit
Parameter
Max
Min
Min
Max Min
Max
Min
Max
Read Cycle Time
100
tRC
70
120
150
ns
Address Access Time *
tAA
70
100
120
150
ns
CS Access Time *3
Output Enable to
Output Valid
Output Hold from
Address Change
Chip Select to
Output Low-Z *4*5
Output Enable to
Output Low-Z *4*5
Chip Select to
Output High-Z *4*5
Output Enable to
Output High-Z *4*5

tACS

70

100

120

150

ns

tOE

35

40

50

60

ns

tOH

20

20

20

20

ns

tCLZ

10

10

10

10

ns

tOLZ

5

5

5

5

ns

tCHZ

25

40

40

50

ns

tOHZ

25

40

40

50

ns

READ CYCLE TIMING DIAGRAM *1

ADDRESS
DOUT

PREVIOUS DATA V~

X X

DATA VALID

READ CYCLE 2: CS CONTROLLED *3
ADDRESS _ _

DOUT

~~~....,-:~_-::~_-::~_-==tAA===_-~=~~=::::t+jR-C--_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-~q+j'___ _

HIGH-Z

tOE
tOLZ
~: Undenfined

Note: *1 WE is high for Read cycle.
*2 Device is continuously selected, CS=OE=VIL.
*3 Address valid prior to or coincident with CS transition low.
*4 Transition is measured at the point of ±500mV from steady state voltage.
*5 This parameter is specified with Load 2 in Fig. 2.

3-28

~~~llllllllilli~~llilllllll MB84256A-70/70L/70LL
FUJITSU MB84256A-I0/I0L/I0LL
MB84256A-12/12L/12LL
I111111I1111111111111I111111

MB84256A-15/15L/15LL

WRITE CYCLE *1*2

MB84256AMB84256AMB84256AMB84256ASymbol 70/70L/70LI 10/10L/10LI 12/12L/12LI 15/15L/15LI Unit
Max
Min
Min
Max
Min
Max
Min
Max
100
120
150
tWC
70
ns

Parameter
Write Cycle Time *3
Address Valid to
End of Write
Chip Select to
End of Write
Data Valid to
End of Write
Data Hold Time
Write Pulse Width
Address Setup Time
Write Recovery Time
*4
WE to Output Low-Z
*5*6
WE to Output High Z
>"5*6

tAW

50

80

85

100

ns

tCW

50

80

85

100

ns

tDW

25

40

45

50

ns

tDH
tWP
tAS

0
50
0

0
60
0

0
70
0

0
90
0

ns
ns
ns

tWR

5

5

5

5

ns

tWLZ

5

5

5

5

ns

tWHZ

25

40

40

50

ns

WRITE CYCLE TIMING DIAGRAM *1*2

WRITE CYCLE 1: WE CONTROLLED
tWC
ADDRESS
tWR

tAW

t E - - - - - - - tCW
------------~~~

- - - - - - - ; o . j Jr--r--r-'--'~...--:,.......,~

t-E-----

tWP ----;..;

Jr---------

tDW ----....;
DATA VALID

DIN
DOUT

HIGH-Z
~ : Undenf ined

Note: *1
*2
*3
"'4
*5
*6

If OE, CS are in the READ Mode during this period, I/O pins are in the
output state so that the input signals of opposite phase to the outputs
must not be applied.
If CS goes high simultaneously with WE high, the output remains in high
impedance state.
All write cycle are determined from last address transition to the first
address transition of the next address.
tWR is defined from the end point of WRITE Mode.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is specified with Load 2 in Fig. 2.

3-29

1II0IIIIIIlIINlii

MH84Z~6A-70/70L/70LL

IIUliIII!liDII!1

MB84256A-15/151,./15lL

FUJITSU MB84256A-I0/10L/I0lL
MB84256A-12/12l/12lL

WRITE CYCLE TIKING DIAGRAM *1*2

WRITE CYCLE 2: CS CONTROLLED
tWC
ADDRESS

=>

~
I

tAW

~

_tWR

tCW

N

V

I

tWP

""" """
'\

DOUT

*2

*3
*4
*5
*6

3-30

V////////

~tDW-

HIGH-Z

DIN

Note: *1

'\

tCLZ

tWHZ

HIGH Z \ ,

~

r X X

-

-tDH~

DATA VALID

HIGH Z

HIGH Z
~ : Undenfined

If OE, CS are in the READ Mode during this period, I/O pins are in the
output state so that the input signals of opposite phase to the outputs
must not be applied.
If CS goes high simultaneously with WE high, the output remains in high
impedance state.
All write cycle are determined from last address transition to the first
address transition of the next address.
tWR is defined from the end point of WRITE Mode.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is specified with Load 2 in Fig. 2.

nl~I!~liIli!~m MB84256A-70/70L/70LL

FUJ ITSU

InmllnlollmmmlDI
IIIH IIUIUWII
HII

MB84256A-IO/IOL/IOLL
MB84256A-12/121,../12LL
MB84256A-15/15L/15LL

DATA RETENTION CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
Symbol
Parameter
Data Retention Supply Voltage *1
Data Retention I MB84256A-70/10/12/15
I MB84256A 70L/10L/12L/15L
Supply
Current *2
I MB84256A-70LL/10LL/12LL/15LL
Data Retention Setup Time
Operation Recovery Time

VDR

Min

Max

1.0
1.0

5.5
1.0
50
5.0 *

2.0

!DR
tDRS
tR

Typ

0
tRC

Unit
V
mA

J.IA
ns
ns

Note: *1 CS~VDR-0.2V
*2 VDR=3.0V, CS~VDR-0.2V
*3 VDR=3.0V, TA=40DC
DATA RETENTION TIMING

DATA RETENTION

Data Retention Mode
VCC

r t:~:J-----------~------------t~ ~
tR

--r-r--r-:%---,

77712.2;-

CS~VDR-O. 2V

jr---~--:1:--T"-r-<2.2V } \ \ \

3-31

8111111111

MB84256A-70/70l/70ll

0101161111111

MB84256A-12/12l/12ll
MB84256A-15/15l/15ll

FUJITSU MB84256A-IO/IOl/IOl-l

PACKAGE DIMENSIONS
28-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-28P-M02)

I

.543 •. 010

INDEX

I~========::::~==:::;~==========~IJ~'"

.600115.24)TYP

1------1.407::~~~135.73:~:~)-----l1
.062(1.58)MAX

.100(2.54)

TYP

I
Dimensions in
inches (millimeters)

e>

1985 FUJITSU LIMITED D28005S·2C

3-32

MB84256A-70j70Lj70LL
MB84256A-I0/I0L/I0Ll
MB84256A-12/12L/12LL
1D!i!~lllnll~1 MB84256A-15/15l/15LL

UI!Dlmmmm
FUJITSU

PACKAGE DIMENSIONS
Suffix: P-SK

28-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-28P-M04)

,::,:~: :~,,:cr:M:': : : :0: : )s·~~
I

1.392~:~~~(3S.36~~:;)

.034~OOI2 (0.86~g·3)

I

~======::;l~ls.

MAX

.300(7.62)TYP

.010t.002
(0.2S<0.OS)

I

~.207(5.2S)MAX
=P.11813.0)MIN
.1OO(2.S4)
TYP

I

01986 FUJITSU LIMITED D28018S·2C

.02010.51 )MIN

Dimensions in
inches (millimeters)

3-33

111111!IUIIIO MB84256A-70/70L/70LL

MB84256A-IO/IOL/IOLL
MB84256A-12/12L/12LL
Ilnl~lImnl!ll MB84256A-15/15L/15LL

FUJITSU

PACKAGE DIMENSIONS
28-LEAD PLASTIC FLAT PACKAGE
. (CASE No.: FPT-28P-M02)

O(O)MIN
(STAND OFF)
1

~'00811

View"A"

(8.6.0.2)

~dffin=IN=rDrE;;Xm=rr=n=TFn=rr=nm=rTt I';':r ~~J'"
.669+.010 (17.75+ 0 .25 )
-.008
-0.2

.402'.012

.006 •.002
(0.15.0.05)

I
_

e

1987 FUJITSU LIM ITED F2801 lS·2C

3-34

.008(0.18)
MAX
.027(0.68)
MAX

.110(2.8)MAX

Dimensions in
inches (millimeters)

cO

TS258-C89Y
Nov. 1989

FUJITSU

DATA SHEET

MB84F256-25
CMOS 256K BIT LOW POWER SRAM
32,768-WORD x 8-BIT FULL CMOS STATIC RANDOM
ACCESS MEMORY WITH DATA RETENTION
The Fujitsu MB84F256 is a 32,76B-word by 8-4>it static random access memory. Fabricated
with full CMOS circuit, MB84F256 realizes extremely low data retention current compared with
that of MB84256, which can allows MB84F2S6 to use non-volatile memory using a back up
battery.
The MB84F256 has 600mil 2B-pin plastic DIP package and 28-pin plastic SOP package as
package option.
The device suits for application where, low and wide supply voltage and low power
comsumption are required.

•
•
•

•

•
•
•
•

PLASTIC PACKAGE
FPT-28P-M02

Organization: 32,768 words x 8 bits
Static operation: No clocks or refresh required
Fast access time:
250ns max. @Vcc=5V
2000ns max. @Vcc=3V
Low power comsumption:
Vcc=3V: 5.0~A (CMOS standby)
0.5mA (TIL standby)
20mA (Active)
Vcc=5V: 10~ (CMOS standby)
2mA (TIL standby)
40mA (Active)

PLASTIC PACKAGE
DIP-28P-M02
PIN ASSIGNMENT

Data retention voltage: 2.0V min.
Full CMOS
600 mil width 28-pin plastic DIP package (Suffix: -P)
450 mil width 28-pin plastic SOP package (Suffix: -PF)

(TOP VIEW)

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating

Symbol

Value

Unit

Vcc

-{l.5 to +7.0

V

VIN

-{l.5 to VCC+0.3

V

Output Voltage on any pin with to GND

VIJO

-{l.S to VCC+0.3

Power Dissipation

Po

1.0

W

Output Current

lOUT

±20

mA

Temperature under Bias

TSIAS

-IOta +85

Storage Temperature

TSTCl

-40 to +125

Supply Voltage
Input Voltage on

NOTE:

any pin with to GND

V

°c
°c

Permanent device damage may occur if the above Absolute Maximum
Ratlnljls are exceeded. Functional operation should be restricted to the
condi~ons as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability .

A14
A12

WE

VCC

A7

A13

A6

A8

A5

A9

A4
A3
A2

or:

All
Al0

AI
AO

Cs

1101

1107

1102
1103

1106
1105
1104

GND

1108

This device contains circuitry to protect the Inputs against
damage due to high static wltages or electric fieSds.
However, It Is advised that nomal precautions be taken to

avoid application of any voltage higher than maxirrum rated
voltages to this high lfTll8dance cIICUIt.

Copyrigh'© 1989 FUJITSU LIMITED

3-35

MB84F256-25

Fig. 1 - MB84F256 BLOCK DIAGRAM
A3
A4
AS
A6

VCC
--oGND

--0

ADDRESS
BUFFER

~~

ROW
DECODER

512 x 64 x 8
MEMORY CELL ARRAY

A12
A13
A14
CS
AD

Al
A2
A9
A10
All

I/O GATE &
COLUMN DECODER

ADDRESS
BUFFER

CS
OE"

BUFFER

DATA I/O BUFFER

CS

WE'

CS

"CS --J>o-@)

TRUTH TABLE
~
ITt
_H

X
H

L
L
L

CAPACITANCE

L
X

WE'

MODE
Not Selected
DOUl DlSable
Kead
Wrlte

X
H
H

L

sUppLy
CURRENT
ISB
ICC

I/O PIN
High-Z
High-Z

UUUI
U1N

lL;L;
lL;l

(TA=2S0C. f=lHHz)

Parameter'
110 Capacitance (VI/O=OV)

Input Capacitance (VIN-OV)

3-36

1/01
1/03 1/05
1/07
1/02
1/04
1/06
1/08

Symbol

ClIO
eIN

Min

Typ

Max
8
7

Unit
pF
pF

MB84F256-25

RECOMMENDED OPERATING CONDITION
(Referenced to GND)
Parameter

Symbol

Supply Voltage

VCC

Ambient Temperature

TA

Min

Typ

Max

2.2
4.0
0

3.0
5.0

3.6
5.5
70

Unit
V
C

DC CHARACTERISTICS

(RecODDDended operating conditions otherwise noted.)
Supply
Parameter
Symbol
Voltage
Min
Max
VCC (V)
5.0
2.2V to 3.6V
ISBI
4.0V to 5.5V
10.0
Standby Supply
2.2V to 3.6V
0.5
ISB2
4.0V to 5.5V
2.0
Active Supply
2.2V to 3.6V
5.0
rCC1
Current
4.0V to 5.5V
10.0
Operating Supply
2.2V to 3.6V
20.0
ICC2
Current
4.0V to 5.5V
40.0
InputnLeakage
2.2V to 3.6V
0.5
ILl
Current
4.0V to 5.5V
1.0
Output Leakage
2.2V to 3.6V
0.5
ILl/O
Current
4.0V to 5.5V
1.0
Input High
2.2V to 3.6V VCCxO.8 VCC+0.3
VIH
Voltage
VCC+0.3
4.0V to 5.5V
2.2
Input Low
2.2V to 3.6V
0.3
0.3
VIL
4.0V to 5.5V
-0.3
0.6
Volta&e
Output High
2.2V to 3.6V
2.0
VOH
Voltage
4.0V to 5.5V
2.4
Output Low
2.2V to 3.6V
0.3
VOL
Voltage
4.0V to 5.5V
0.4
Note:

Unit

Condition

pA

CS~VCCxO.9V

mA

CS=VIH

mA
mA
lolA
lolA

VIN=VIH or VIL
IOUT=OmA, CS=VIL
Cycle=Min
Duty=100%,IOUT=OmA
VlN=OV to VCC
VI/O-O to VCC,CS=VIF
OE=VlH or WE=VlL

V
V
V
V

IOH--0.5mA
IOH- 1.0mA
IOL- 1.0mA
IOL- 2.1mA

All voltages are referenced to GND.

3-37

MB84F256-25

AC CHARACTERISTICS TEST CONDITIONS
Parameter
Input Pulse Leve"!
Input Pulse
Rise & Fall Times
Timing Reference
Level

Supply Voltage
VCC (V)
2.2V to 3.6V
4.0V to 5.5V
2.2V to 3.6V
4.0V to 5.5V

Conditions
VIH=VCC, VIL-OV
VIH-2.4V VIL-O.5V
5 ns (Transient between O.3V and VCCxO.8)
5 ns (Transient between O.7V.and 2.2V)
Input: VIH=VCCxO.8, VIL-O.3V
Output: VOH=VCCxO.7 VOL=O.4V
Input: VIH=2.2V, VIL-O.7V
Output: VOH=2.2V, VOL=O.8V
VL-3.0V
VL=5.0V

2.2V to 3.6V
4.0V to 5.5V
2.2V to 3.6V
4.0V to 5.5V

Output Load

Fig. 2 - AC TEST CONDITIONS
VL
Rl

DOUT
(I/O)
R2

*

Including Jig and stray capacitance.

Parameters Measured
exce t tCLZ tOLZ, tCHZ, tOHZ, tWLZ and tWHZ
tCLZ, tOLZ, tCHZ, tOHZ tWLZ and tWHZ

3-38

MB84F256-25

AC CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
READ CYCLE *1

Parameter

Symbol

VCC=
2.2V to 3.6V
Min
Max

vcc=
4.0V to 5.5V
Min
Max

2000

250

Unit

Read Cycle Time

tRC

Address Access
Time *2

tAA

2000

250

ns

CS Access Time *3

tACS

2000

250

ns

tOE

500

100

ns

Output Enable to
Output Valid
Output Hold from
Addresss Change
CS to Output Low-Z
*4*5
Output Enable to
Output Low-Z
*4*5
CS to Output High-Z
*4*5
Output Enable to
Output High-Z
*4*5
Note: *1
*2
*3
*4
*5

ns

tOH

100

50

ns

tCLZ

70

30

ns

tOLZ

100

20

ns

tCHZ

40

tOHZ

100
100

5

50

ns

50

ns

iii

WE is high for Read cycle.
Device is continuously selected, CS=OE=VIL.
Address valid prior to or coincident with CS transition low.
Transition is measured at the following points from steady state voltage .
• VCC=2.2V to 3.6V: ±200mV
• VCC=4.0V to 5.5V: ±500mV
This parameter is specified with Load 2 in Fig. 2.

3-39

MB84F256-25

READ CYCLE TIMING DIAGRAM *1
READ CYCLE 1: ADDRESS CONTROLLED *2

DOUT

PREVIOUS DATA Vruof

X X

DATA VALID

READ CYCLE Z: CS CONTROLLED *3

ADDRESS

_~__
: =_--=-~tAA~-=-~=
___
tRC_ _ _ _~q_

DOUT
Undenfined

it is high for Read cycle.
Device is continuously selected, CS=nt=VIL.
Address valid prior to or coincident with CS transition low.
Transition is measured at the following points from steady state voltage .
• VCC=2.2V to 3.6V
±200mV
• VCC=4.0V to 5.5V
±500mV
*5 This parameter is spec fied with Load 2 in Fig. 2.

Note: *1
*2
*3
*4

3-40

MB84F256-25

AC CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
WRITE CYCLE *1*2

vcc-

VCC=
2.2V to 3.6V
Min
Max

4.0V to 5.5V
Min
Max

tWC

2000

250

ns

tAC

1500

200

ns

tCW

1500

200

ns

tDW

800

100

ns

Data Hold Time

tDH

0

0

ns

Write Pulse Width

tWP

1000

150

ns

Address Setup Time

tAS

0

0

ns

tWR

0

0

ns

30

10

ns

Parameter

Symbol

Write 'Cycle Time *3
Address Valid to
End of Write
Chip Select to
End of Write
Data Valid to
End of Write

Write recovery Time
*4
to Output Low Z
WE
*5*6
to Output High-Z
WE
*5*6
Note: *1
*2
*3
*4
*5
*6

tWLZ
tWHZ

100

50

Unit

ns

If DE, CS are in the READ Mode during this period, I/O pins are in the
output state so that the input signals of opposite phase to the outputs
must not be applied.
If CS goes high simultaneously with WE high, the output remains in high
impedance state.
All write cycle are determined from last address transition to the first
address transition of the next address.
tWR is defined from the end point of WRITE Mode.
Transition is measured at the following points from steady state voltage .
• VCC=2.2V to 3.6V: ±200mV
• VCC=4.0V to 5.5V: ±500mV
This parameter is specified with Load 2 in Fig. 2.

3-41

MB84F256-25

AC CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
WRITE CYCLE TIMING DIAGRAM *1*2
WRITE CYCLE 1: WE CONTROLLED

tWC
ADDRESS
tWR

tAW

lID

te"------- tCW -------""'1 J.--r--r-/"C,.--::,.......,..--,-

-------i-.....-, '"'0----- tWP - - - " " ' I J.-------tDW--~

DIN
DOUT

HIGH-Z

tWHZ

DATA VALID

HIGH-Z
~ : Undenfined

Note: *1

If'OE, CS are in the READ Mode during this period, I/O pins are in the
output state so that the input signals of opposite phase to the outputs
must not be applied.
*2 If CS goes high simultaneously with WE high, the output remains in high
impedance state.
*3 All write cycle are determined from last address transition to the first
address transition of the next address.
*4 tWR is defined from the end point of WRITE Mode.
*5 Transition is measured at the following points from steady state voltage.
o VCC=2.2V to 3.6V:
±200mV
• VCC=4.0V to 5.5V: ±500mV
*6 This parameter is specified with Load 2 in Fig. 2.

3-42

MB84F256-25

AC CHARACTERISTICS
(Recommended operating conditions otherwise noted.)

WRITE CYCLE TIMING DIAGRAM

*1*2

WRITE CYCLE 2: CS CONTROLLED

tWC
ADDRESS

~

M
I
tAW

~

tCW

hi

jE-tWR

V

-

I

tWP

"'-"'-"'- " "'-"'-"'-'\
DIN
DOUT

Note: *1

*2
*3

*4
*5

*6

~_ tDW

HIGH Z
tCLZ

HIGH

V////////

tWHZ

Zlx~

- - ~tDH
DATA VALID

--+j

HIGH Z

HIGH Z
~ : Undenfined

If OE, CS are in the READ Mode during this period, I/O pins are in the
output state so that the input signals of opposite phase to the outputs
must not be applied.
If CS goes high simultaneously with WE high, the output remains in high
impedance state.
All write cycle are determined from last address transition to the first
address transition of the next address.
tWR is defined from the end point of WRITE Mode.
Transition is measured at the following points from steady state voltage .
• VCC=2.2V to 3.6V: ±200mV
• VCC=4.0V to 5.5V: ±500mV
This parameter is specified with Load 2 in Fig. 2.

3-43

MB84F256-25

DATA RETENTION CHARACTERISTICS

(ReCOlllDellded operating conditions otherwise noted.)
Parameter

Symbol

Min

Max

Unit

Data Retention Supply Voltage *1

VDR

1.1

5.5

V

Data Retention Supply Current *2

IDR

1.0

llA

Data Retention Setup Time

tDRS

Operation Recovery Time

tR

Note: *1
*2
*3

0

ns

tRC *3

ns

VDR+0.3~CS~VDRxO.9

VDR=1.8V, VDR~CS~VDRxO.9
tRC: Read Cycle

DATA RETENTION TIMING
DATA RETENTION

Data Retention Mode
VCC

VrC7~J-----------~~---------jt·:~~
--"7--r--r-±---..

ZZZ1vccx~. 8V*

VDR+O. 3~CS~VDRxO . 9V

* VIH=2.2V min. at VCC=4.0V to 5.5V

3-44

_rlr------:l::-~-..--.....-~
VCCxO. 8V*T'\\\

MB84F256-25

PACKAGE DIMENSIONS
(Suffix: P

28-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-28P-M02)

.600(15.24)TYP

INDEX

.100(2.54)
TYP

I

01988 FUJITSU LIMITED D28OO6S-2C

Dimensions n
inche& (millimeters)

3-45

MB84FZ56-Z5

PACKAGE DIMENSIONS
28-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-28P-M02)

.11012.80) MAX
ISEATED HEIGHT)
CliO) MIN

ISTAND OFF)

.402±.012
110.20±O.30)

""'-.--+ .031 ± .008

10.80±0.20)

II

"A"

r

.006±.002
10.lS±0.OS)
-D-;~ils ~f'i':-

part --:
I

I

1----.650116.51) R E F - - - - l

.. 1998 FUJITSU LIMITED

3-46

F28011~

.00710.18)
MAX
.02710.68)
I
____________
JI
MAX
Dimensions in

inches (mllilTl8lers)

IIIIIIIIIIIIIIIIIIIIIIIIIIIIII~~~~~~~~~~~~
CMOS L048.576-BIT STATIC
MB841000-80/80L

fUJITSU

MB841000-10/10L
MB841000-12/12L

RANDOM ACCESS MEMORY

1111I1I1II11I1I11II1I11I1I1I1I~~~~~~~~~~~d
TS279-A89X
Oct. 1989

1M-BIT (131,072x8) CMOS STATIC RANDOM ACCESS
MEMORY WITH DATA RETENTION AND LOW POWER
The Fujitsu MB841000 is a l3l,072-word x 8-bit static random
access memory fabricated with a CMOS sillicon gate process.
The memory utilizes asynchronous circuitry and may be maintained in any state for an indefinite period of time. All
pins are TIL compatible, and a single +5V power supply is
required.
The MB841000 is ideally suited for use in microprocesser
systems and other applications where fast access time and
ease of use are required. All devices offer the advantages
of low power dissipation, low cost and high performance.

PLASTIC PACKAGE
(DIP-32P-M01)

• Organization: 131,072 x 8 bits
• Fast access time:
80 ns max. (MB841000-80/80L)
100 ns max. (MB84l000-l0/l0L)
120 ns max. (MB841000-12/12L)
• Complete static operation: No clock required
• TIL compatible inputs/outputs
• Three state outputs
• Single +5V ±10% power supply
• Low power standby :
CMOS level: 5.5 mW max. (MB841000-80/10/12)
1.1 mW max. (MB84l000-80L/10L/12L)
TIL level : 16.5 mW max. (MB841000-80/80L/10/l0L/12/12L)

PLASTIC PACKAGE
(FPT-32P-M03)

• Data retention: 2.0V min.
• Standard 32-pin DIP (600mil) (Suffix: P)
• Standard 32-pin FPT (525mil) (Suffix: PF)

ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Bias

VCC
VIN
VI 0
TBIAS
TSTG

TOP VIEW

Ne

vee

Al6
Al4
AIZ

e5Z
'iI(

A7

Al3

A6

AS

AS

(See NOTE)
Value

PIN ASSIGNMENT

A4
A3
AZ
Al
AD

Unit

-0.5 to +7.0
-0.5 to VCC+0.5
-0.5 to VCC+0.5
-10 to +85
-40 to +125

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS .are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

1/01
I/OZ
1/03

V
V
V

GNO

AIS

A9

All
ilE
AID

BI

l/OS
1/07
1/06
l/OS
l/OS

C

C
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance

Circuit.

3-47

RIUIIIIII

MB84100D-SO/SOl

FUJITSU MB84100D-10/10l

••1_ MB841000-12/1ZL
Fig. 1 - HB841000 :PLOCK DIAGRAM

-'-<>VCC

AS

A6
A7
A8

IDI

-'-<>GND

ADDRESS
BUFFER

A12
A13
A14
A15
A16

ROW
DECODER

•
CS

AO
Al
A2
A3
A4

512 x 16 x 8 x 16
MEMORY CELL ARRAY

ADDRESS
BUFFER

•

•

I/O GATE &
COLUMN DECODER

A9
All
CS

OE
BUFFER

DATA I/O BUFFER

Wi
CS

CS1~
CS
CS2

3-48

1/01 1/03 1/05 1/07
1/02 1/04 1/06 1/08

CS

!~l~~~~~~~~~i!~l~~~!

MB841000-80/80L
MB841000-10/10L
11~~~~I~~~~~II~~~~~! MB841000-12/12L

FUJ ITSU

RECOMMENDED OPERATING CONDITION (Referenced to GND)
Symbol

Min

Typ

Max

Unit

Supply Voltage

vee

4.5

5.0

5.5

V

Ambient Temperature

TA

0

70

°e

Parameter

FUNCTION TRUTH TABLE
SUPPLY
CURRENT

eS1

eS2

DE

WE

MODE

H

X

X

X

Not Selected

ISB

High-Z

X

L

X

X

Not Selected

ISB

High-Z

L

H

H

H

DOUT Disable

ICC

High-Z

L

H

L

H

Read

ICC

DOUT

L

H

X

L

Write

ICC

DIN

I/O PIN

CAPACITANCE (TA=25°C. f=1MHz)
Parameter

Symbol

Min

Typ

Max

Unit

I/O Capacitance (VI/O=OV)

CI/O

10

pF

Input Capacitance (VIN=OV)

CIN

8

pF

3-49

1I11~111~llil~~I~~I~1 MB841000-80/80L
FUJITSU MB841000-10/10L
i~~I~I~li~~I~~~lln MB841000-12/12L

DC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)
Symbol

Test Condition

Parameter

MBB41000
-80/10/12
Min
Max

MBB41000
-BOL/10L/12L
Min
Max

Unit

CS2S0.2V or
ISB1

CS1~VCC-0.2V

Standby ·Supply
Current

CS1=VIH or CS2=VIL

Ell

1

0.2

ISB2

3

3

mA

ICC1

5

5

mA

ICC2

BO

BO

mA

(with CS2S0.2V
or CS2~VCC-0.2VJ

VIN-VIH or VIL,
Active Supply
CS1=VIL, CS2=VIH
Current
IOUT=OmA
Operating Supply Cyc1e=Min.
Current
Duty=100% IOUT=OmA
Input Leakage
VIN=OV to VCC
Current
VI/O-OV
to VCC
Output Leakage
CS1=VIH or CS2=VIL
Current
or OE=VIH or WE=VIL
Input High
Voltage
Input Low
Voltage
Output High
IOH=-1.0mA
Voltage
Output Low
IOL=2.1mA
Voltage

mA

ILl

-1

1

-1

1

'IIA

ILI/O

-2

2

-2

2

'IIA

VIH

2.2

VCC+0.3

2.2

VCC+0.3

V

VIL

-0.3*

O.B

-0.3*

0.8

V

VOH

2.4

VOL

2.4
0·.4

V
0.4

V

Note: All voltages are referenced to GND.
*: -3.0V min. for pulse width less than 20 ns. eVIL min. = -0.3V at DC level.)

Fig. 2 - AC TEST CONDITIONS

Outpu.t Load

• Input Pulse Levels: 0.6V to 2.4V
• Input Pulse Rise & Fall Times:
5ns (Transient between O.BV and 2.2V)
• Timing Reference Levels
Input:
VIL=O.BV, VIH=2.2V
Output: VOL=O.BV, VOH=2.0V

+5V
R1
DOUT
(I/O)

1
CL*

r

R2

*

Including Jig and stray capacitance

I
I R1 I R2 I CL I
Parameters Measured
I
I Load1 I l.BKQ I 990Q I 100pF I except tCLZ, tOLZ tCHZ, tOHZ tWLZ and tWHZ I
l Load2 J 1. BKQ I 990Q I 5JlF 1 tCLZ, tOLZ, tCHZ, tOHZ, tWLZ and tWHZ
I

3-50

MB841000-80/80L
MB841000-10/10L
MB841000-12/12L

AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)

READ CYCLE *1
Parameter

Symbol

MBS41000-S0/S01 MBS41000-10/101 MBS41000-1'2/121
Min

Max

Min

Max

100

Unit

Max

120

Read Cycle Time

tRC

Address Access Time

tAA

SO

100

120

ns

CSl Access Time

tACI

SO

100

120

ns

CS2 Access Time

tAC2

SO

100

120

ns

tOE

35

40

50

ns

Output Enable to
Output Valid
Output Hold from
Address Change
Chip' Select to
Output Low-Z ~t2*3
Output Enable to
Output Low-Z *2*3
Chip Select to
Output High-Z *2*3
Output Enable to
Output High-Z *2*3
Note: *1
*2
*3

SO

Min

ns

tOH

10

10

10

ns

tCLZ

10

10

10

ns

tOLZ

5

5

5

ns

tCHZ

30

35

40

ns

tOHZ

30

35

40

ns

WE is high for Read cycle.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is specified with Load 2 in Fig. 2.

3-51

MB841000-80/80l
MB841000-10/10l
MB841000-12/12L

AC CHARACTERISTICS

{Recommended operating conditions unless otherwise noted.}

READ CYCLE TIMING DIAGRAM *1
READ CYCLE I: ADDRESS CONTROLLED *2
ADDRESS
DOur

tt-t-OH-~---tA-A--t_R_C::::~::!::::::::::::::::::::::::::::~.",=====
PREVIOUS DATA V.u.n1<

X X

DATA VALID

READ CYCLE 2: CS1, CS2 CONTROLLED *3
ADDRESS

_Jt+--_E= = _ t R C-=-=~q_
11-._:--- tAA---~

CS2

DOur
~ : Undefined

Note: *1 WE is high for Read cycle.
*2 Device is continuously selected, CS1=OE=VI~ CS2=VIH.
*3 Address valid prior to or coincident with CS1 transition low, CS2 transition high.

3-52

!!I~~II!IIIIIII!I!!!illl~11I MB841000-80/80L
FUJITSU MB841000-10/10L
~IIIII~~II!I!!!~!!!!I!III MB841000-12/12L

AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)

WRITE CYCLE *1*2
Parameter

Symbol

MB841000-80/801 MB84l000-l0/l0I MB841000-l2/l2I
Min

Max

Min

Max

Min

Unit

Max

tWC

80

100

120

ns

tAW

60

80

85

ns

tCW

60

80

85

ns

tDW

30

40

45

ns

Data Hold Time

tDH

0

0

0

ns

Write Pulse Width

tWP

50

60

70

ns

Address Setup Time

tAS

0

0

0

ns

tWR

5

5

5

ns

tWLZ

5

5

5

ns

Write Cycle Time *3
Address Valid to
End of Write
Chip Select to
End of Write
Data Valid to
End of Write

Write Recovery
Time '/'4
Write Enable to
Output Low-Z *5*6
Write Enable to
Output High-Z *5'/'6
Note: *1
*2
*3
*4
*5
*6

tWHZ

30

35

40

ns

If OE, CSI and CS2 are in the READ Mode during this period, I/O pins are
in the output state so that the input signals of opposite phase to the
out~ts must not be applied.
If CSl goes high or CS2 goes low simultaneously with WE high, the output
remains in high impedance state.
All write cycle are determined from last address transition to the first
address transition of the next address.
tWR is defined from the end point of WRITE Mode.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is specified with Load 2 in Fig. 2.

3-53

lilU!IIHllli

MB841000-80/80L

FUJITSU MB841000-10/10L
li~lilnmllilill MB841000-12/12L
AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)

WRITE CYCLE TIMING DIAGRAM *1*2
WRITE CYCLE 1: WE CONTROLLED
ADDRESS

CS2

DIN
DOUT

K:8J :
Note: *1
*2

3-54

Undefined

I~ OE, CSI and CS2 are in the READ Mode during this period, I/O pins are
in the output state so that the input signals of opposite phase to the
out~ts must not be applied.
__
If CSI goes high or CS2 goes low simultaneously with WE high, the output
remains in high impedance state.

MB841000-80/80l
MB841000-10/10l
MB841000-12/12l

AC CHARACTERISTICS

(Recommended operating conditions nnless otherwise noted.)

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE 2: CS1 CONTROLLED *1
ADDRESS

CS2

DIN
DOUT

K:ZI : Undefined
Note: *1

If DE, CS2 and WE are in the READ Mode during this period, I/O pins are
in the output state so that the input signals of opposite phase to the
outputs must not be applied.

3-55

1i1!1!lililllli!i!

MB841000-80/80l
MB841000-10/10l
1I1~li~li~i~!I!1I MB841000-12/12l

FUJ ITSU

AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE 3: CS2 CONTROLLED *1
tWC
ADDRESS

3

M
tAW

/ / / / / / / / / / / / / / / / / / / / / / / / V///
tCW

"" ""

CS1

V//// / / /

~'\

CS2

tWR

tCW

r-tWP

""""

///////

r'\ " " '\

r-=--:-_ tDW

DATA VALID

HIGH Z

DIN

tCLZ

DOUT

HIGH-Z

~

tDH-"""1

HIGH Z

tWHZ

x"Xl>

HIGH-Z
~ : Undefined

Note: *1

3-56

If OE, CS1 and WE are in the READ Mode during this period, I/O pins are
in the output state so that the input signals of opposite phase to the
outputs must not be applied.

MB841000-80/80L
MB841000-10/10L
MB841000-12/12L

DATA RETENTION CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Symbol

Min

Data Retention Supply Voltage

VDR

2.0

Data Retention
I MB841000-80/10/12
Supply Current *1 I MB841000-80L/10L/12L

IDR

Data Retention Setup Time

tDRS

Operation Recovery Time *2

tR

Note: *1

Typ

Max

Unit

5.5

V

0.5
0.1 *2

rnA
rnA

0

ns

tRC

ns

VCC=VDR=3.0V
CS2~VDR-0.2V or
(at CS2 CONTROLLED)
tRC: Read Cycle Time
CS1~VDR-O.2V,

CS2~0.2V

(at CS1 CONTROLLED)

CS2~0.2V

*2

DATA RETENTION TIMING

CSl CONTROLLED

Data Retention Mode

VCC

4.

5jv"~ _______

r '""s

--,.--r-,--=lz-----.

222!12.2V'

m_'{P'?m _________

CSl~VDR-O. 2V

j0v

LtR~

_r--+-2.2V

T@

CS2 CONTROLLED

VCC

CS2

3-57

IIIIIIIIIOIUI

MB841000-80/80l
MB841000-10/10l
111111111111111 MB841000-12/12l

FUJITSU

PACKAGE DIMENSIONS
(Suffix: P)
32-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No.: DIP-32P-MOI)

-,----.."..IiIiiiIiiiil==+

.032~g12

.Q10~:886..

(0.82~g·30)

.050(1.27)
MAX

(0.25~g:6jl

.100(2.54)
TYP

© 1988 FUJITSU LIMITED D32007S-1 C

3-58

1 5' MAX

.018~:gg~
(0.45~g:6~
Dimensions in
inches (millimeters)

i!~i~II~~III~~II~~11
FUJ ITSU

MB841000-80/80l
MB84100D-IO/IOl
1!~lllilll~I~I~IIIII! MB841000-12/12l

PACKAGE DIMENSIONS
(Suffix: PF)

32-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-32P-M03)
.098 MAX

.5

o

o

r

.00e>.002
(0.20>0 OS)

hpore~nnn2nnnn~
I
I
,=1=004(0.10)

.

.750(19.05) REF

01989 FUJITSU LIMITED F32008S-2C

Dimensions in inches
(millimeters

3-59

Low Power CMOS SRAMs

3-60

Static RAM Data Book

Section 4

Application Specific SRAMs -

At a Glance

Maximum

Access

Package
Options

I

Page

Device

Time (ns)

Capacity

4--{)3

MOO1C51-25

25
30

64-pin

Ceramic PGA

28-pin

Plastic

DIP, FPT

-45

35
45

2048 bits
512 x 4-way or
1024 x 2-way
73728 bits
(8192wx9b)

4-.'31

MOO279RT-20
-25

20
25

73728 bits
(B192w x 9b)

32-pin

Plastic

DIP, FPT

4-43

MOO2B7-25
-.'l5

25
35

262144 bits
(3276Bw x Bb)

32-pin

Plastic

DIP, FPT

4-.55

MOO421-90/L

-12/L
MBB422-90/L
-12/L

90
120
90
120

163B4-bits
(204Bw x Bb)

4B-pin
52-pin
54-pin

Plastic
Plastic
Plastic

DIP
DIP
FPT

MOO431-90IULL
-12/ULL
MBB432-90IULL
-12/ULL

90
120
90
120

153B4-bits
(204Bw x 8b)

4B-pin
52-pin
54-pin

Plastic
Plastic
Plastic

DIP
DIP
FPT

-30
4-19

4--09

MOO 1C79B--35

lEI

4-1

Application Specific SRAM

lID

4-2

Static RAM Data Book

111111111111111111111111111111111111111111111111111111111111111

TAG RANDOM
FUJITSU CMOS
ACCESS MEMORY

MB81C51-25
MB81C51-30

111111111111111111111111111111111111111111111111111111111111111

November 1988
Edition 1.0

CMOS TAG RANDOM ACCESS MEMORY
The Fujitsu MB81C51 Is 512 entry x 4 way/l024 entry x 2 way TAG Random Access
Memory (TAG RAM) fabricated with a CMOS teohnology.
MB81 C51 has been developed aiming to be used In an easily handled cache system with
the other DATA RAMs (ex. MB81C79A). Especially this device offers the advantages on
designing compact and high performance cache system which will be used In a system
adopting 32-blt CPU.

• Organization:

512 Entry x 4 Way or
1024 Entry x 2 Way

• Fast acoess time:

25/30 ns max from Address Inputs
18 n8 max from Compare Data Inputs

• Power Consumption: 1100mW max.
• Single +5 V supply ±10,," tolerance
• TTL compatible Inputs and outputs
LCC-68P-M02
(PLASTIC PACKAGE)

• LRU (Least Recently Used) Replacement LogiC
• Purge Function (All-purge & Partial-purge)
• Internal Parity Generator/Checker
• 64 pin Pln-Grld-Array (Suffix: CR)
• 68 pin Plastic LCC (Suffix: PO)

ABSOLUTE MAXIMUM RATINGS (See NOTE
Rating

Symbol

Value

Unit

Supply Voltage

Vcc

-0.5 to +7.0

V

Input Voltage on any pin with
respect to GND

VIN

-3.0 to +7.0

V

Output Voltage on any pin with
respect to GND

VOUT

-0.5 to +7.0

V

Output Current

lOUT

±20

mA

Power Dissipation

Po

1.5

W

Temperature under Bias

TBIAS

-10 to +85

·C

-65 to +125

·C

-45 to +125

·C

Ceramic
Storage Temperature

TSTG
Plastic

NOTE:

Copyright

Permanent device damage may occur If the above Absolute Maximum
Ratings are exceeded. Functional operation should be restricted to the
conditions as detailed In the operational sections of this data sheet. Exposure
to absolute maximum rating conditions for extended periods may affect
device reliability.

@

PGA-64C-A02
(PIN GRID ARF'lAY)

This device contains circuitry to protect the
Inputs against damage due to high static
voltages Of electric fields.
However, It Is
advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high Impedance
circuit.

1988 FWITSU LIMITED

4-3

.Iml. .
FUJITSU

~111~ml~III~OOIIII~IIIOOIII

MB81C51-25
MB81 C51-30

Fig. 1 - MB81C51 BLOCK DIAGRAM 1

ENTRY

t-t-AO

..

0-

•
•
•

ADDRESS
BUFFER
&
DECODER

••
•

-----

~
y

AS

PARITY
GENERATOR

•
•
•
•
TD19

0-

\r

U"'' OU'
COM"',,"' ~ I

D
A
T
A

~J
PARITY
CHECKER

.

~

'-

r-

HIT INFJ.
REPLACE INFO.
TAG
DATA
BUFFER

f-f---

"'" ;.. .

J

MPX &
OUTPUT CONTROL

~

....... ~
HIT IRE PLACE
INFO.

4-4

I'r-

REPLACE INFO.

T
A
/,-G

0-

•

A

y

PARITyrF
DATA

TOO

512 ENTRY
X 6 BIT

Vti'r

PU

;..

MEMORY CELL

"

0-

-0

--"'.

MEMORY CELL
512 ENTRY
X 23 BIT
X4 WAY

•
•

lEI

~

PURGE
BUFFER

"'"

;..
OUTPUT CONTROL

~
PARITY ERROR

;.-

LRU
LOGIC

NEW LRU DATA

VCC
GND

11111111111111!lllll!IIII!11111111111111!11!1!1,,!III!1111111

FUJITSU

MB81C51-25
MB81C51-30

Fig. 2 - MB81C51 BLOCK DIAGRAM 2

TOO - TD19
MHENBL Vee EXTH

20

MHiT
COMPARE
& VALIDITY
CHECK

88

HiT

HITOI
REPO
HIT1!
REP1

AO - AS

HIT21
REP2

6

HIT31
REP3
HCO!
RCO
HC11
RCl

PeAR
SET(}------------~~--~l

SBO

RLATCH

CAPACITANCE

(TA

SBl

SBLK

H!R

.

=25°C f =1 MHZ)

Parameter
Input Capacitance (VIN = OV)

Symbol
CIN

Typ

Max

Unit

10

pF

4-5

lEI

MB81C51-25
MB81C51-30

PIN ASSIGNMENT
64 PIN PIN GRID ARRAY(PGA-64C-A02)

..

BOTTOM VIEW

PIN FUNCTION
Pin No.

4-6

Function

Pin No.

Function

Pin No.

Function

1

N.C.

23

A4

45

2

MHIT

24

AS

46

T09

3

HITO/REPO

25

A7

47

Vee

4

HIT2/REP2

26

A9

48

T013

5

HIT3/REP3

27

N.C.

49

T015

6

TOO

28

N.C.

50

T017

7

T02

29

PINV

51

T019

8

EXTH

30

SBlK

52

AO

9

MHENBl

31

SBl

53

A2

T06

10

N.C.

32

INH

54

GNO

11

T07

33

INVl

55

AS

12

T08

34

SET

56

A8

13

T010

35

H/R

57

PURGE

14

TOll

36

HIT

58

MODE

15

T012

37

HCO/RCO

59

VINV

16

T014

38

HC1!RCl

60

SBO

17

T016

39

HIT1/REPl

61

Vee

18

T018

40

GNO

62

WRITE

19

N.C.

41

TDl

63

RlATCH

20

N.C.

42

T03

64

PERR

21

Al

43

T04

22

A3

44

TD5

MB81C51-25
MB81C51-30

PIN ASSIGNMENT

68 PIN PLCC(PLASTIC LEAD CHIP CARRIER)

nnnnririnnnnnnnnnnn
10 C

P
P
P
P
psa
P55
P54
P53
60

11C

59

12 C

0

13 C

58
57

14 C
15 C
16 C
17 C
18 C

D52

19 C

::J 51

20 C

::J 50

21 C

::J 49

0

22C
23 C
24 C
25
26

FUJITSU

C
C

::J 48
::J 47

~46

D45
::J44

~nHHH~ ~~!;l ~ ~ ~n~ ~ ~ ~ ~ ~
TOP VIEW

PIN FUNCTION (continued)
Pin No.

Function

Pin No.

Function

Pin No.

Function

1

GND

24

TD17

47

PINV

2

TDO

25

TD18

48

SBLK

3

TD1

26

TD19

49

SBO

4

TD2

27

N.C.

50

SB1

5

TD3

28

N.C.

51

INH

6

EXTH

29

N.C.

52

Vee

7

TD4

30

AO

53

INV

8

N.C.

31

A1

54

WRITE

N.C.

32

A2

55

SET

10

9

MHENBL

33

A3

56

RLATCH

11

TD5

34

A4

57

H/R

12

TD6

35

GND

58

PERR

13

TD7

36

A5

59

HIT

14

TD8

37

A6

60

HCO/RCO

15

TD9

38

A7

61

N.C.

16

TD10

39

A8

62

N.C.

17

TD11

40

A9

63

HClIRC1

18

Vee

41

N.C.

64

MHIT

19

TD12

42

N.C.

65

HITO/REPO
HIT1/REP1

20

TD13

43

N.C.

66

21

TD14

44

PURGE

67

HIT2/REP2

22

TD15

45

MODE

68

HIT3/REP3

23

TD16

46

VINV

4-7

:1111~1111111111111111111111111111:1!1!1!1!11!!:!;i

FUo1lTSU
111111111!llillllllllll!IIII!IIII:lll:!111111!11111:

MB81C51-25
MB81C51-30

PIN DESCRIPTION
OUTPUTS

INPUTS

lEI

HIT

HIT OUTPUT. "NOR" OF HITO TO HIT3

HCn/RCn

CODED OUTPUTS OF HIT OR REPLACE INFORMATION In: 0 - 1 )

HITn/REPn

UNCODED OUTPUTS OF HIT OR REPLACE INFORMATION In: 0 - 3 )

PERR

PARITY ERRQR

MHIT

HIT OUTPUT MODIFIED BY MHENBL AND EXTH

MODE

MODE SELECTION
MODE: 1 : 512 Entry x 4 Way
MODE : 0 : 1024 Entry x 2 Way

AO-A9

ADDRESS INPUTS IA9 Is not used for 4 way)

TDO-19

TAG INFORMATION INPUTS

PURGE

ALL-PURGE TIMING PULSE

INVL

PARTIAL-PURGE. V-BIT FORCED TO "0".
LRU IS REVERSIVELY UPDATED

SBLK

ENABLE WAY-SELECTION EXTERNALLY AT REPLACEMENT AND INVALIDATION

SBO, SB1

EXTERNAL WAY-ADDRESS INPUTS

WRITE

WRITE CYCLE SIGNAL

SET

TIMING PULSE
Write: Registrate TAG, V-bit "H", LRU update
Read : LRU updated
PARTIAL PURGE; LRU reversively update, V-bit "L"

INH

ALL FUNCTIONS EXCEPT PURGE ARE INHIBITED

H/R

OUTPUT SELECTION
H/R : 1 : Hit Information
H/R : 0 : Replace Information

RLATCH

LATCH CONTROL FOR REPLACE INFORMATION

PINV

USE FOR "TESTING" ONLY IGENERALLY "W)

VINV

USE FOR "TESTING" ONLY IGENERALLY "W)

MHENBL

ENABLE MHIT OUTPUT

EXTH

FORCE MHIT OUTPUT TO "L"

FUNCTION TABLE
1) BASIC FUNCTION (Any combination except below are inhibited.)
Input

Control Info.

TAG Info.

INH

PURGE

SET

WRITE

INVL

L

H

X

X

X

H

H

H

X

X

H

H

H

H

H

1f
1f

H
L

H

X

L

H

X

X

H

H

1f

H

L

TAG

P bit

V bit

Function Mode

N-CNG

N-CNG

N-CNG

INHIBIT3

N-CNG

N-CNG

N-CNG

N-CNG

TAG READ

N-CNG

N-CNG

N-CNG

N-CNGl
or UP-D

TAG READ

TOO to TD19

SET

H

UP-D

TAG WRITE

UNDEFINED

UNDEFINED

L IAII)

INCLZ

ALL PURGE

N-CNG

N-CNG

N-CNG/.L2

N-CNG 1
or RUP-D

PARTIAL PURGE

N-CNG

X : "W or "L"
N-CNG : No Change
INCLZ : INITIALIZE
UP-D : Up Dated
RUP-D : Reverslvely Updated
1. When SBLK : "L" and no-HIT, then LRU Is no change IN-CNG).
2. When SBLK: "L" and!!.Q:HIT,.!!:I~!l'y-Bit Is no change IN-CNG).
3. During INHIBIT mode, HIT and PERR outputs are "H" but the other outputs are "L".

4-8

LRU
LRU

MB81 C51-25
MB81C51-30

FUJITSU

2) OUTPUT PIN FUNCTION
Internal Info. 1. 2

Input

Output

Mode

A9

hltO!
repO

hltl!
repl

hlt2!
rep2

hit3!
rep3

HITO!
REPO

HIT1!
REPl

HIT2!
REP2

HIT3!
REP3

HCO!
RCO

HCll
RCl

Hii'

3!

H

X

L

L

L

L

L

L

L

L

L

L

H

H

X

H

L

L

L

H

L

L

L

L

L

L

4

H

X

L

H

L

L

L

H

L

L

H

L

L

W

H

X

L

L

H

L

L

L

H

L

L

H

L

A

H

X

L

L

L

H

L

L

L

H

H

H

L

Y

L

L

L

X

L

X

L

L

L

L

L

L

H

L

L

H

X

L

X

H

L

L

L

L

L

L

2

L

L

L

X

H

X

L

L

H

L

L

H

L

W

L

H

X

L

X

L

L

L

L

L

L

L

H

A

L

H

X

H

X

L

L

H

L

L

H

L

L

Y

L

H

X

L

X

H

L

L

L

H

H

H

L

Mode

X: "H" or "L"
1. Internal Information. repO to rep3 are determined by on-chip LRU logic when SBLK = "L". When SBLK = "H", the internal
Information are determined by external signal of SBO & SB1.
2. Correct operation Is not guaranteed If 2 ways or more become HIT at the same time.
3. Output of HIT Is valid when H!R = "H".

3) PARTIAL PURGE (INVL

= "L")

INPUT

INTERNAL INFO.

PURGE BLOCK

HIT

BLOCK

SET

MODE

A9

SBLK

SBO

SBl

0

1

2

3

0

1

2

3

H

X

L

X

X

L

L

L

L

-

-

-

-

H

X

L

X

X

H

L

L

L

Q

-

H

X

L

X

X

L

H

L

L

-

Q

-

-

--uLRU

MODE

---

-

RUP-D
RUP-D

Q

-

-

Q

RUP-D

A

-

RUP-D

Y

4

H

X

L

X

X

L

L

H

L

-

H

X

L

X

X

L

L

L

H

-

H

X

H

L

L

X

X

X

X

Q

H

X

H

H

L

X

X

X

X

-

Q

-

-

H

X

H

L

H

X

X

X

X

-

Q

-

RUP-D

H

X

H

H

H

X

X

X

X

-

-

Q

RUP-D

L

L

L

X

X

L

X

L

X

-

-

-

L

L

L

X

X

H

X

L

X

Q

-

-

RUP-D

L

L

L

X

X

L

X

H

X

-

Q

L

L

H

L

L

X

X

X

X

Q

-

-

-

-

RUP-D

Q

-

RUP-D

-

-

---

A

-

RUP-D

Y

RUP-D

RUP-D

--RUP-D

L

L

H

L

H

X

X

X

X

-

L

H

L

X

X

X

L

X

L

L

H

L

X

X

X

H

X

L

L

H

L

X

X

X

L

X

H

-

-

RUP-D

H

H

H

L

X

X

X

X

-

Q

-

Q

L

-

RUP-D

H

H

H

H

X

X

X

X

-

-

-

Q

RUP-D

L
Note:

Q

W

2

W

Correct operation Is not guaranteed If 2 ways or more become HIT at the same time.

4-9

OOOOMIM.OO~III~II~I~IIIIIII!!~1

Illmll;I••1 ~~~~g~~=~g
-

4) PARITY ERROR & V BIT'

..

( "'! 0 to 3)

pe"

v"O

v,,1

PE"

L

L

L

L

---

L

L

H

H

HIT

L

H

L

H

HIT

L

H

H

L

HIT

H

L

L

L

--HIT

HIT '''fo.2

H

L

H

H

H

H

L

H

HIT

H

H

H

H

HIT

pen
vnO/vnl
PEn

Internal parity error of way "n"
Duplicate validity bits.
Determined by the following equation.
PEn

= (vnO + vnl)

• pen + (vnO

0

vnl)

1. PERR Is "NOR" of PEO to PE3
2. Output Information when Internal "HIT" is valid .

BASIC FUNCTIONS
TAG READ
A comparison between the TAG Input data (TDO-19) and the
contents of the 'addressed location is performed. If both data
are the same, that Is 'FOUND". Then HIT will be "LOW' and
outputs of Hen, HITn Indicate hilled" Associative way". In the
case of "NOT-FOUND". the TAG RAM will specify the "way',
which should be replaced, by using the LRU logic automatically.
The replacement Information will be presented at the outputs of
RCn and REPn by forcing the H/R Input into 'LOW". These
signals will be latched and used for the data Memory move-In
operation.

ALL PURGE
By asserting PURGE Input "LOW" , the V -bit are reset and LRU
logic Is Initialized.
In this operation, the contents of each TAG and Its parity will
not be Identified.

PARTIAL PURGE
The partial purge operation Is performed by

iNVL.

"LOW" and

SET pulse Input.
TAG WRITE
When 'NOT-FOUND' Is occurred, the TAG-RAM also should
be updated. The write operation Is performed by WRi'fE
'LOW" and SET pulse Input. The TAG data will be written Into
the proper 'way' by the Internal LRU logic.
TAG-WRITE mode, V-bit (Validity bit) and the parity are set,
and LRU logic Is updated.
On the other hand, it will be able to specify the 'way"
externally by using SBLK, SBO and SBI Inputs.

4-10

The V-bit, which Is specified by the address Inputs, will be
reset, and LRU logic will be reversively updated.

MB81C51-25
MB81C51-30

RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol

FUJITSU

(Referenced to GND)

Min

Typ

Max

Unit

5.0

Supply Voltage

Vee

4.5

5.5

V

Input Low Voltage

VIL

-0.5'

0.8

V

Input High Voltage

VIH

2.2

6.0

V

Ambient Temperature

TA

0

70

·C

Note:
'-3.0V min. for pulse width less than 20nB.

lEI

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Input Leakage Current
Operating Supply Current
Output Low Voltage
Output High Voltage

Test Condition

=0 V to Vee
OOUT =Open, Cycle = min.
IOL =8mA
IOH =-4mA

VIN

Symbol

Min

Max

-10

10

JJ,A

Ice

200

mA

VOL

0.4

V

ILl

VOH

2.4

Unit

V

4-11

~llllllllllllm~IIIII~IIIIIIIIOOIIIIIIIII
FUJITSU

1IIIIil!III~IIIIIIIII!IIOOII~111111111

MB81C51-25
MB81 C51-30

Fig. 3 - AC TEST CONDITION
INPUT PULSE LEVELS

O.OV to 3.OV

INPUT PULSE RISE AND FALL TIMES:

5ns (Transient time between O.8V and 2.2VJ

TIMING REFERENCE LEVELS

Input
: 1 .5\1.
Output : 1 .5V

OUTPUT LOAD:

5.0V

-,•

4800

'>

2550

•

lEI

AC CHARACTERISTICS

4-12

MB81C51-25
MB81C51-30

Parameter

Symbol

MBS1C51-25
Min
Max
50

FUJITSU

MBS1C51-30
Min

Max

50

Unit

Write Cycle Time

twe

Address Valid to RCn, REPn

tAR

Address Setup Time for SET

tAS

25

25

ns

35

ns
40

ns

TAG Data Setup Time for SET

tTS

25

25

ns

SET Pulse Width

tsw

20

20

ns

SET Recovery Time

tSR

5

5

ns

RlATCH Setup Time

tRLS

10

10

ns

SBlK, SBO, SBl Setup Time for SET

tSBS

25

25

SBlK, SBO, SBl Setup Time for PCn, REPn

tSBR

PCn, REPn Hold Time for SBlK, SBO, SBl

tSH

0

0

ns

SBlK Hold Time

tSBH

5

5

ns

PINV, VINV Setup Time for SET

tiS

25

25

ns

PINV, VINV Recovery Time for SET

tlR

5

5

ns

25

ns
25

ns

..

4-13

OOIIIII~llllllljllllll!IIIIII~llilIIIIOOI
FUJITSU

MB81 C51-25

illllll~IIIIOOIIIIOOIIIIIIIIIIIIIIIIIII MB81 C51-30

TAG READ CYCLE (MOli= "W or "L",
"L",INH="W)

AO - A9

TOO - TD19

H/R

HiT,

HCn, HITn
(Note 1)

RCn, REPn
(Note 2)

MHENBL,
EXTH

RLATCH
(Note 5)

SBLK

SBO, SB1
(Note 6)

Notes 1:
2:
3:
4:
5:
6:

4-14

Valid at H/R = "W .
Valid at H/R = "V.
LRU Is updated atSEl = "L",
Replace latched at RLATCH = "W ,
Valid at SBLK = "L",
Valid at SBLK = "W.

PuRGE = "H", WRi'i'E =
,

"H",

iiiiiiL = "W, PiNv =

"H" or "L", iiiNV = "H" or

MB81C51-25
MB81C51-30

TAG WRITE CYCLE (MODE

= "H"

or "L",

'P'i:ii'iGE = "H", WRii'E = "L", iN\iL = "H",

INH

FUJITSU

= "H")

AO - A9

H/R

RCn, REPn

•

EI

TOO - TD19

RLATCH
(Note 3)

SBLK

SBO, SB1
(Note 4)

D
Notes 1,
2,
3,
4.

Don'tCare

Reglstrate TAG , V-bit "H", LRU update.
Replace latched at RIAfCH = "H".
Valid at SBLK = "L",
Valid at SBLK = "H".

4-15

IIIIIIIIIII~II.IIIIIIIIIIIIIIIIIIIIIIIIII
FUJITSU
mlll~OOIIlI~IIIHIM~III~

MB81C51-25
MB81 C51-30

=
=

=

=

PARTIAL PURGE CYCLE (MODE "H" or.::1:....PUi'iGE "W, WRITE "W, 'iiiiV[
RLATCH "l", PINV "W or "l", VINV "W or "l")

=

=

= "l",

H/R

= "W

or "l",

iiiiH ="W,

AO - A9

TOO - TD19
(Note 1)

SBlK

SBO, SBl
(Note 3)

•

Don't Care

Notes:
1. Valid at SBlK = "l".
2. lRU Is reverslvely updated, V-bit "l" .
3. Valid at SBlK = "W.

All purge (SET = "W, OTHER CONTROL INPUTS ARE "H" or "l")

(

AO - A9

f---1\

tppw

tPR

I/'
tAPe

4-16

INPUT VALID

II!IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII1111111111

MB81C51-25
MB81 C51-30

FUJITSU
111111111111111111111I11111111111111111111111111111111111I1I11111

PACKAGE DIMENSIONS
68-LEAD PLASTIC LEADED CHIP CARRIER
(Oase No. : LOO-68P-M02)

.169~gg~(430~gn)

990± 005
(2515±0 13) SQ_~
953± 003
r-----(24 21 ±O 08) S Q - - i

®
@

CD@

.800(20.32) REF--i

1 06 ~gf~(270 ~g~~)

I

.I!.P I

.I

@

INDEX

Details of "A" part

(R.037(0.95)) TYP.

8.: LEAD No.

i .931±.020 (23.65±0.51)
© 1989 FUJITSU LIMITED C68052S-1C

R.030(0.75) TYP

~

I

--------------------~

Dimensions in
inches (millimeters)

4-17

1IIIIIIIIIIIIIIIIIIIIIIImllllllllllllllllllili

FUJITSU MB81C51-25
111111~IOOI~III~IIIII~IIIIIIIIIIIM· MB81 C51-30

PACKAGE DIMENSIONS

continued

64-LEAD CERAMIC (METAL SEAL) PIN GRID ARRAY PACKAGE
(CASE No.: PGA-64C-A02)

.050(1.27)DIA TYP

INDEX A

lEI

\

h

D

.100±.010
(2.54±0.25)

1

/

~I@~o-o-o-o-o-o-o-o~@
000

o

1.032~:~~~

0

TYP
1.032+. 018
-.012

0

o

0

o

0

o

0

0

0

o

0

0

@

.018~·~~~(0.46~~:~~)DIA

.050~:~~~(1.27~~:~~)

sa
.210(5.33)
MAX

©1988 FUJITSU LIMITED R64008S.2C

0

.900(22.86)

u

J"" '.""0 ~

000

.

134+.016(340+0.41)
-.014' -0.36

Dimensions in
inches (millimeters)

4-18

OJ

October 1989
Edition 1.0

FUJITSU

DATA SHEET

MB81C79B-351-45
CMOS 72K-BIT HIGH SPEED SRAM
8192-WORDS X 9-BIT HIGH SPEED CMOS STATIC
RANDOM ACCESS MEMORY WITH AUTOMATIC
POWER DOWN
The Fujitsu MB81 C79B is 8192words x 9bits static random eccess memory fabricated with a
CMOS process. Because of 9 bit organization, this devioe is convenient to be used for parity
check function and also this device has two fast column addresses, therefore MB81 C79B is
very suitable to used as cache buffers. To make power dissipation lower, peripheral circuits
consist 01 CMOS 1Bchnoiogy,and to obtain smaller chip size, cells consisit 01 NMOS
transistors and resistors. All pins are TTL compatible and a single 5 volts power supply is
required.
All devioes offer the advantages 01 low power dissipation, low cost and high performance.
• Organization: 8192words x 9bits
• Static operation: No clock or timing strobe required
Fast acoess time: t...=t..cs,=35ns max, 1oe=10ns max.
All, A 12 acoess time=12ns max. (MB81C79B-35)
t...=t..cs,=45ns max, 1oe=15ns max.
A11, A 12 acoess time=l5ns max. (MB81C79B-45)
• Low power consumption: 550mW~()peration)
138mW TtL Standby)
83mW ( MOS Standby)
Single +5V supply, ±10% toleranoe
TTL compatible inputs and outputs
• Thre&-sta1B inputs and outputs
Chip selects lor simplified memory expansion, automatic power down
• All Inputs and outputs heve pro1ection against static charge
Standard 28-pin 300mil Plastic DIP pacllage (Suffix: -P-SK)
Standard 28-pin 450mil Gun wing flat package (Suffix: -PF)

ABSOLUTE MAXIMUM RATINGS (see NOTE)

PLASTIC PACKAGE
DIP-28P-M04

PLASTIC PACKAGE
FPT-28P-M02

PIN ASSIGNMENT

,.'"
,.

os,

,.

A,

A,

Rallng
Supply Voltage

Symbol

Value

Unit

Vo<;

-<1.5 to +7

V

Input Voltage on any pin with respect
toGND

V'N

~cf~6Voltage on any 110 with respect

VOUT

Output Current
Power Dissipation

lOUT
PD

-3.5 to +7
-<1.5 to +7
±20

V
V
mA

1.0

W

Temperature Under Bias

T....

-10 to +85

·C

Storag Temperature

Tsre

-40 to +125

·C

NOTE:

Vee
WE
A,

A,

A,

A"

OE'

A"

A,

A"
I/O,

CS,
110,

110,

110,

110,

110,

I/O,

110,

GNO

110,

Permanent devioe damage may occur if the above Abaolute Maximum
Rallng. are exceeded. Functional operation should be restricted to the
conditiOns as detailed in the operational sections ollhis data sheet. Exposure to
absolU1e maxlmum rating conditions for extended periods may affect device
reliability.

CopyrlghiO 11188 by FWITSU LIMITED

4-19

MB81C79B-35
MB81 C79B-45

Fig. 1 - MB81C79B BLOCK DIAGRAM

-

-

ADDRESS
BUFFER

Js-

..

·
·
-·

-

-Vee

•
ROW
DECODER

-GND
256x32x9
MEMORY CELL
ARRAY

•

-

·

.

I.

.I

1/0 GATE

ADDRESS
BUFFER

&

COLUMN DECODER

.

I•

ds-

.I

BUFFER

DATA I/O BUFFER

ds

bbbbbbbbJ

Cs,

---.~~,

Cst

---.--"'"'1------.J

1/0,

Va.

VQ,

1/0.

Va.

Vo.

~

VCr

IIOa

CS

1/0.

TRUTH TABLE
CS,
H
L
L
L
L

Cst WE
X
L
H
H
H

X
X
H
H
L

OE
X
X
H
L
X

MODE
STANDBY
DESELECT
Dour DISABLE
READ
WRITE

ctUJ'J'J-JT

S.f~E

I..
Icc
Icc
Icc
Icc

HIGH-Z
HIGH-Z
HIGH-Z
DOUT
D'N

• Fast address

.

CAPACITANCE (T'A= 25° C f = 1MHz)
Parameter
Input Capacitance (V,N=OV) (CS" Cs., OE, WE)

Symbol

Input Capacitance (V,N=OV) (Other Inputs)

C"
C,•

VO Capacitance (V.,,=OV)

ClIO

4-20

Typ

Max

Unit

7

pF

8

pF

8

pF

MB81 C79B-35
MB81 C79B-45

RECOMMENDED OPERATING CONDITIONS
Referenced to GND)
Parameter

Min

Typ

Max

Unit

Vee

4.5

5.0

5.5

V

VOL

-2.0·

0.8

V

Input High Voltage

V'H

2.2

6.0

V

Ambient Temperature

T.

0

70

·C

Supply Voltage
Input Low Voltage

Symbol

• -2.OV Min. for pulse width less than 2Ons. (V .. Min=-O.5V at DC level)

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Parameter

Symbol

Min

Max

Unit

Test Condltlon

Input Leakage Current

lu

-10

10

~

V'N=OV to Vcc

Output Leakage Current

ILO

-10

10

~

CS,=V'H or CS,=V'L or WE=V'L or
OE=V'H, VOUT=OV to Vee

Operating Supply Current

Icc

130

mA

CS,=V'L
1/000pen, Cycle=Min

ISB1

15

mA

Vee=Min to Max. CS,=Vee-O.2V
V'N5fJ.2V or V'N2Vcc-O.2V

Is..

25

mA

CS,=V'H

Output Low Voltage

VOL

0.4

V

IOL=8mA

Output High Voltage

VOH

V

IOH=-4mA

Peak Power-on Current

IPO

Standby Supply Current

2.4

50

mA

Vcc=OV to Vee Min.
CS, =Lower of Vee or V'H Min.

4-21

MB81C79B-35
MB81C79B-45

AC TEST CONDITIONS
Input Pulse Levels:

O.6Vto 2.4V

Input Pulse Rise And Fall Times:

Sns (Transient time between O.8V and 2.2V)

Timing Measurement Reference Levels: Input: 1.SV
Output:1.SV

Fig. 2

..

Output Load I.

Output Load II.

For all except Iu. 1Hz. twz. low. Iou. and 10HZ.

For Iu. 1Hz. Iwz. low. 1012. and 10Hz.

SV

SV

4800

Dour

Dour
30pF

(Including Scope
and Jig Capacitance)

4-22

T
m

SpF
(Including Scope
and Jig Capacitance)

2550

T
m

MB81 C79B-35
MB81 C79B-45

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE"
Parameter

Symbol

Read Cycle Time

t..c

Address Access Time "

....

CS, Access Time "

CS2 Access Time

·3

MB81C79B-35

MB81C79B-45

Min

Min

Max

Unit
Max

ns

45

35

35#1

45#2

ns

1.-.CS1

35

45

ns

t.-.CS2

15

20

ns

ns

Output Hold from Address Change

IoH

OE Access Time

IoE

Output Active from CS, "'5

Iu,

5

5

ns

Output Active from Cs, "'5

tu.

2

2

ns

Output Active from OE "'5

b.z

2

2

ns

Output Disable from CS, "'5

1Hz,

20

25

ns

Output Disable from CS," '5

IH"

20

25

ns

Output Disable from OE "'5

10HZ

20

25

ns

Note: '1
'2
'3
'4
'5
#1
#2

3

3

15

10

ns

WE is high for Read cycle.
Device is continuously selected, CS,=V L , Cs,=VIH and OE=VIL•
Address valid prior to or coincident with CS, transition low, CS, transition high.
Transition is specified at the point of ±500mV from steady state Voltage.
This parameter is specified with load II in Fig. 2.
A11, A12 address access time is 12ns max.
A11, A12 address access time is 15ns max.

4-23

MB81C79B-35
MB81C79B-45

READ CYCLE TIMING DIAGRAM "
READ CYCLE I: ADDRESS CONTROLLED

'2

:~: _I_I_· · · ·_?_· · · _:_~'-_E-V_-I_O~U-S- -D~A-T-A~t. . -V-A~L:-ID~- =~- =~_t. c~: .;:-i~ ~ ~D~A~T~A~V~A~LI~'~_! ll~_.
_•••••

___

READ CYCLE II: CS" Cs, CONTROLLED "

'"""~ ..,I4~'-::::::::::::::t...._.::.::::::::::;_t..c
•

lID

_________

~1I.·.

Cs,

I/O

~ : Undefined
Note: '1
'2
'3
'4
'5

4-24

WE is high for Read cycle,
Device is continuously selected, CS,=VIL, C5,=V'H and OE=V L
Address valid prior to or coincident with CS, transition low, CS2 transition high,
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

I:

Don't Care

i •••••

MB81 C79B-35
MB81 C79B-45
WRITE CYCLE·'
Parameter

Symbol

MB81C79B-35

MB81C79B-45

Min

Min

Max

Unit

Max

Write Cycle TIme "

!we

35

45

ns

es, to End 01 Write

lew,

30

40

ns

Cg. to End of Write

lew.

20

25

ns

Address Valid to End of Write

t..w

30

40

ns

Address Setup TIme

t..s

0

0

ns

Write Pulse Width

fwp

20

25

ns

Data Setup TIme

low

17

20

ns

Write RecoV9f}' TIme "

twR

3

3

ns

Data Hold TIme

IoH

0

0

ns

Output High-Z from WE "'s

Iwz

Output Low-Z from WE "'s

low

Note: 'I
'2
'3
'4
'5

-

15

0

20

0

ns

ns

-

If Cs, goes high simultaneously with WE high. the output remains in high impedance state.
All write cycles are determined from the last address transition to the first address transition of next address.
twR is defined from the end point of Write Mode.
Transition is specified at the point of ±500mV from steady state Voltage.
This parameter is specified with Load II in Fig. 2.

4-25

MB81 C79B·35
MB81C79B·45

WRITE CYCLE TIMING DIAGRAM "
WRITE CYCLE I: CS" Cs., CONTROLLED
ADDRESS

Cs.,

1/0

~

: Undefined

III:

Don't Care

Note: '1 If OE, CS" and Cs., are in the READ Mode during this period, I/O pins are in the output state so that the input signals of
opposite phase to the outputs must not be applied.
'2 All write cycles are determined from the last address transition to the first address transition of next address.
'3 twR is defined from the end point of WRITE Mode.
'4 Transition is specified at the point of ±500mV from steady state voltage.
'5 This parameter is specified with Load II in Fig. 2.

4-26

MB81 C79B-35
MB81 C79B-45
WRITE CYCLE TIMING DIAGRAM

'1

WRITE CYCLE II: WE CONTROLLED

ADDRESS

Cs.

1/0

~: Undefined
Note:

"I
"2
"3
"4
"5

I :

Don't Care

If OE, CSt, and Cs. are in the READ Mode during this period, I/O pins are in the output state so that the input signals of
opposite phase to the outputs must not be applied.
All write cycles are determined from the last address transition to the first address transition of next address.
tw.. is defined from the end point of WRITE Mode.
Transition is specified at the point of ±500mV from steady state Voltage.
This parameter is specified with Load II in Fig. 2.

4-27

MB81C79B-35
MB81 C79B-45

PACKAGE DIMENSIONS
28-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. : DIP-28P-M04)

1.392~g?~(35.36~8:~g)

1

,:~::~:

..

'I

:0::::::: :0:: ]5!g:~'1::

11034~i?12

[ 1050~i?12

(0.86~g30)

(1.27~g·30)

.050(1.27)
MAX

© 1988 FUJITSU LIMITED D28018S-2C

4-28

Dimensions in
inches (millimeters)

MB81 C79B-35
MB81 C79B-45

PACKAGE DIMENSIONS
2B-LEAD PLASTIC FLAT PACKAGE
.11O(2.S0) MAX
(Case No. : FPT -28P-M02)
~---+(-'-S'-'EA'::":T:::'ED-"--'-HE-IG-H-T)
0(0) MIN

~~'''"&W'''.'''8l:'~

l

cf

INDEX

(STAND OFF)

---:Q

·465±.012
(11.S0±0.30)

.402±.012
(10.20±O.30)

.339±.008
(S.60±0.20)

!ffi=m::::n==n=n=n=;::r::;=r=n=n=n=n=:;~ _1

-"""_--l..
1==11

TYP

..
"A"

,j
I

:

'
I,

031 ± OOS
(0 80±0 20)

lID

006± 002
(0 15±O 05)

i D-;~iTs ~f'j';- pa;-t - -1
:

.008(0.20)

:

I

I

I

I

I

I

I

f - - - - - .650(16.51) REF---..,

.024(0.60)

I

-+-1f-'...:..00~7~(0.18)

I
I
I

MAX
.027(0.68)

I

----~~~----j
© 1988 FUJITSU LIMITED F28011S-3C

Dimensions in

inches (millimeters)

4-29

Application Specific SRAMs

4-30

Static RAM Data Book

MB8279RT-20
MB8279RT-25

FUJITSU
11111111111111111111111111111111111111111111111111111111111111111

March 1989
Edition 2.0

72K-BIT (8192 x 9) SYNCHRONOUS CMOS STATIC
RANDOM ACCESS MEMORY WITH AUTOMATIC
POWER DOWN
The Fujitsu MB8279RT is a B,192-words by 9-bits synchronous static random
access memory fabricated with a CMOS silicon gate process.
Write operation is initiated by internal write pulse generator, which is driven
by the clock signal given through the CLK pin therefore external control
of write pulse width is not necessary. Compared to the traditional RAM,
MB8279RT drastically improves the system level cycle time because signal
skews are not necessarily concerned.

..

PLASTIC PACKAGE
DIP-32P-M02

The MB8279RT has a 32-pin plastic skinny DIP package and 32-pin plastic
flat package as ·package options.
All pins are TTL compatible, and a single +5V power supply is required.
• 8,192 words x 9 bits organization
• Fast access time:
tACL = 20ns max. /
t AcS2 = tpE2 = 10ns max.
(MB8279RT-20)
tACL = 25ns max. /
tACS2 = tpE2 = 12ns max.
(MB8279RT-25)
• Registered addresses, CS" WE
and Data inputs
• Write cancel function by asynchronous CS2 pin
• On-chip write pulse generator
• On-chip parity checker

•
•

•
•
•
•

CMOS peripheral
Single = 5V (±10%) power supply
with low current drain
Active operation = 120mA max.
Standby operation = 30mA max.
Common data inputs/outputs
TTL compatible inputs/outputs
Three-state data output and open
drain parity error output
Standard 32-pin plastic DIP
package: (Suffix P-SK)
Standard 32-pin plastic flat
package (Suffix PF)

PLASTIC PACKAGE
FPT-32P-M02

PIN ASSIGNMENT
(TOP VIEW)
A3

vcc

A4

A2

A5
A6

A,
Ao
CLR
CLK

A7

ABSOLUTE MAXIMUM RATINGS (See NOTE)

As
Rating

Symbol

Value

Unit
V

Supply Voltage

Vcc

-0.5 to +7.0

Input Voltage

V IN

-3.5 to +7.0

V

Output Voltage

VI/O

-0.5 to +7.0

V

Output Current

lOUT

±20

mA

Power Dissipation

Po

1.0

W

Temperature Under Bias

T BIAS

-10 to +85

Storage Temperature Range

TSTG

-40 to 125

°c
°c

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

INH

CS,
WE
CS 2

PE
I/0 g
II0s
1/0 7
I/0s
GNDQ

This device contains circuitry to protect the
inputs against damage due to high static volt-

ages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit.

4-31

1IIImllillmlilimmmllllllllllilimmilm

FUJITSU
1111111111111111111111111111111111111111111111111111

MB8279RT-20
MB8279RT-25

Fig. 1 - MB8279RT BLOCK DIAGRAM

-

AO 0 - -

r---0

AI 0 - -

vee

--<>GND Q
A2 0 - --<>GND
A3 0 - -

ROW
DECODER

256 x 32 x 9
MEMORY CELL ARRAY

A4 0 - -

..

AS 0 - A6 0 - -

ADDRESS
REGISTER

A7 0 - -

-

t--

I

AS 0-Ag 0 - I/O GATE
&
COLUMN DECODER

A 10 0 - A11 0-A12 0--

CLR

CSI 0--

CONTROL
REGISTER

-

WE 0 - -

CONTROL
BUFFER

CS 2

CLK
INH

WRITE
PULSE
GENERATOR

0-

-

DIN REGISTER
&
I/O BUFFER
PARITY
CHECK

r--

111 1

11

:=:r-->-

1/0 1 1/03 1/0 5 1/0 7 I/Og
I/O
I/O 4 I/O 6 I/O

1
PE

CAPACITANCE ITa =25°C, f = lMHz)
Parameter

Symbol

Min

Typ

Max

Unit

I/O Capacitance (Vila = OV)

CliO

B

pF

Input Capacitance (V IN = OV)

CIN

6

pF

4-32

1111111111111111111111111111111111111111111111111111

MB8279RT-20 FUJITSU
MB8279RT-25

1111111111111111111111111111111111111111111111111111

PIN DESCRIPTION
Symbol

Pin name

Input/
Output

Function

-

ClK

Clock

Input

Address, CS, and WE are fetched at the rising edge of
the ClK, and DIN is fetched at falling edge of the ClK.

INH

Inhibit

Input

While INH = "H", a low level of ClK is disabled.

ClR

Clear

Input

When ClR = "l", the contents of CS, and WE register are
cleared to standby.

Ao to A'2

Add ress In put

Input

Synchronous address inputs.

CS,

Chip Select 1

Input

Synchronous Chip Select 1 (CS,) input.
(This pin can be used as power down.)

C~

Chip Select 2

Input

Asynchronous high-speed Chip Select 2 (CS2 ) input.
(This pin can be used as write cancel.)

WE

Write Enable

Input

Synchronous Write Enable (WE) input.

I/O, to I/Og

PE

Data Input/Output

Input/
Output

Data inputs/outputs.
(Synchronous data inputs/Asynchronous data outputs)

Parity Error

Output

Asynchronous parity error output: PE output remains
High-Impedance state through undefined area.

GNDQ

Ground for Output

-

GND

Ground for Others

-

Power Supply

Vee

+5V ±10% power supply.
Ground for output circuits.
Ground for other circuits.

TRUTH TABLE
ClR

CS,

CS2

WE

l

X

X

H

H

H

PE OUTPUT PIN

SUPPLY CURRENT

MODE

I/O PIN

X

STANDBY

HIGH-Z

HIGH-Z

STANDBY

X

X

STANDBY

HIGH-Z

HIGH-Z

STANDBY

l

l

X

CHIP DISABLE

HIGH-Z

HIGH-Z

ACTIVE

H

l

H

H

READ

DouT

FiE

ACTIVE

H

l

H

l

WRITE

DIN

HIGH-Z

OUTPUT

ACTIVE

legend: H = High level, l = low level, X = Don't care.
Notes: CS, and WE are input at the rising edge of the ClK.
PE output remains High-Impedance state through undefined area.

4-33

IlIlmlllllllllllllllllllllllllllllllllllllllllllli

FUJITSU
1111111111111111111111111111111111111111111111111111

MB8279RT-20
MB8279RT-25

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)

Parameter

lEI

Symbol

Min

Typ

Max

Unit

Supply Voltage

Vee

4.5

5.0

5.5

V

Ambient Temperature

TA

0

70

·C

DC CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
Parameter

Test Conditions

Symbol

Max

Unit

Standby Supply Current

CS, = V 1H

Iss

30

mA

Operating Supply Current

CS, = VIL. 1/0 = Open
Cycle = min.

lee

120

mA

Input Leakage Current

V 1N = GND to Vee

ILl

-10

10

/J. A

Output Leakage Current

CS, =V 1H

I Ll/O

-10

10

/J. A

Input Low Voltage

V 1L

-2.0*'

0.8

V

Input High Voltage

V 1H

2.2

6.0

V

V OH

2.4

V OUT

Output High Voltage

IOH

or C5:2 = V 1L
= GND to Vee

=-4mA

DouT

IOL = SmA

PE

IOL = 16mA

Output Low Voltage

Peak Power-on Current *2

Vee =GND to 4.5V
CLR = GND

V

VOL

0.4

V

Ipo

90

mA

Note: *1 -2.0V Min. for pulse width less than 20ns,(V 1L = -0.3V at DC level)
*2 The CLR input should be connected to GND to keep the device deselected.

4-34

Min

1~111~111~~~lllllllllllmllllmlll~~~III~

MB8279RT.20 FUJITSU
MB8 279RT.25 1~lmlllmli~~~~IIIII~~IIII~~~M~~

Fig. 2 - AC TEST CONDITIONS
•
•

INPUT PULSE LEVELS:
TIMING REFERENCE LEVELS:

•

OUTPUT LOAD

0.6V TO 2.4V
INPUT:
V IL ~ o.av, V IH = 2.2V
OUTPUT: VOL = 0.8V, VOH = 2.2V

5V

5V

..

280[1

PEo---------~-----J

DOUTo---------~----~

"INCLUDING JIG AND STRAY CAPACITANCE.

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)

READ CYCLE
Symbol

Parameter

I
.1

When no uses PE
Read Cycle Time
When uses PE
Clock "H" Level Pulse Width
Clock "L" Level Pulse Width
Input Setup Time
Input Hold Time
Clock Access Time

DOUT
PE

CS:! Access Ti me

DouT
PE

CS:! to Output Low-Z

DouT
PE

CS:! to Output High-Z

DouT
PE

Output Hold from Clock

DouT
PE

Output Hold from CS:!

DouT
PE

tRC
t RC
tCLH
tCLL
ts
tH
t AcL
tPE
t ACS2
tpE2
t LZ2
tpLZ2
tHZ2
t pHZ2
tOH
tpH
tOH2
t pH2

MB8279RT·20
Max
Min
20
25
8
8
4
2
20
25
10
10
2
2
2
8
2
8
2
2
2
2

MB8279RT·25
Min
Max
25
30
10
10
4
2
25
30
12
12
2
2
10
2
10
2
2
2
2
2

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

4-35

mmll!illllll~~~~ln!
FUJITSU MB8279RT-20
lil.I!IH!i~!~iiUI MB8279RT-25

READ CYCLE TIMING DIAGRAM
READ CYCLE (lNH

= L, CLR = HI
1----tCLH

eLK

ADDRESS

cs,

DATA 110

Note 1: PEQutput remains High·lmpedance state through undefined area.

4-36

tcLL-----i

1IIIIIIIIml~~~~~mllmllmlllllml~m

MB8279RT-20 FUJITSU
MB8279RT-25 IIII!IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~

WRITE CYCLE
Symbol

Parameter

Write Cycle Time
Clock "H" Level Pulse Width

MB8279RT-20
Min

Max

MB8279RT-25
Min

Max

Unit

twc

20

25

ns

tCLH

8

10

ns

10

ns

tCLL

8

Input Setup Time

ts

4

4

ns

Input Hold Time

tH

2

2

ns

tcs

2

2

ns

tCH

8

10

ns

tos

0

0

ns

tOH

6

6

ns

tHZ

2

8

2

10

ns

tpHZ

2

8

2

10

ns

tLZ

2

2

ns

tpLZ

2

2

ns

Clock "L" Level Pulse Width

CS:, Setu p Ti me
CS2 Hold Time
Data Setup Time
Data Hold Time
CLK to Output High-Z

CLK to Output Low-Z

DOUT

PE
DouT

PE

CLOCK INHIBIT TIMING
Parameter

Symbol

MB8279RT-20
Min

Max

MB8279RT-25
Min

Max

Unit

Clock Inhibit Setup Time

tCLIs

2

2

ns

Clock Inhibit Hold Time

tCLIH

2

2

ns

Clock Enable Setup Time

tCLES

2

2

ns

Clock Enable Hold Time

tCLEH

0

0

ns

REGISTOR CLEAR TIMING
Parameter
Clear Pulse Width
Clear Hold Time
Clear Recovery Time
Clear to Output High-Z

MB8279RT-20
Symbol

Min

Max

MB8279RT-25
Min

Max

Unit

tCAw

7

7

ns

tCAH

10

10

ns

tCAA

10

10

tCRHZ

2

8

2

ns
10

ns

4-37

m~~lmlmlllllm~I~!IIIII~~mlli~~11
PUJITSU MB8279RT..20
Ilmli~~ii~limilliIMml~~iil!IMB8279RT..25

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE (lNH = L, CLR = HI

ClK

ADDRESS

lEI

CS,

DATA 110

Note 1: When

4-38

CS:!

= H level, write· operation is excuted and when C~ = L level, write operation is cancelled.

1111111111111111111111111111111111111111111111111111

MBB279RT-20 FUJITSU
MBB279RT-25

1111111111111111111111111111111111111111111111111111

CLOCK INHIBIT TIMING DIAGRAM
CLOCK INHIBIT

CLK

tCLIH

INH

lEI
REGISTER CLEAR TIMING
REGISTER CLEAR

CLK

DATA liD +~~-++-~---=~-------

- ---

4-39

1IIIIIImlllllllllllllllllllllllllllllllllllllllili

FUJITSU MB8279RT-20
111111111~lmllllllmlll~IIII~llllmllml~11 MB8279RT-25

EXAMPLE OF MB8279RT BASIC FUNCTION

CLK

~ VZ. . . . .

~V/~/!1"'--:-~.V1~!--'-':J1"'"""":-'E
.....

V,,"",",,-7

ADDRESS -,--:-1............ !I1.........,..B...&....<..VZ-,,-,-7I1..&.....;-c

cs,

1 W/;1 V!/;1

~JI1 V7

VIII1 VlIl1, VlIi1 lZZ

WE

j [11///1

DATA I/O

--i------i----f

STANDBY
CYCLE

V/Zi1

READ
CYCLE

WRITE
CYCLE

WRITE CANCEL
FUNCTION

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImlllllllllllilim

MB8279RT-20
MB8279RT-25

FUJITSU
1111111111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS
32·LEAD PLASTIC DUAL IN·LlNE PACKAGE
(CASE No.: DIP·32P·M02)
15°MAX

~l

.010+.002T
(0.25±0.051

lEI

,~.207(5.25IMAX

.

1/

1_ .1.

100(2.54)
TYP

I I If

If If

~ ~
(1.27~g.301

~ I•.018±.003
(0.45±0.081

=P.

125 (3.18IMIN

.020(0.511
MIN
Dimensions in
inches (millimeters)

© 1988 FUJITSU LIMITED D32009S-1C

4-41

Imlllllmllllllmlllllllllllmllllmm~11111
FUJITSU

MB8279RT-20

1IIIIIIIImlllllmIIIOO~~~~~I~!lmll MB8279RT-25

PACKAGE DIMENSIONS (continued)
32-LEAD PLASTIC SMALL OUTLINE PACKAGE
(CASE No.: FPT-32P-M02)

r

""""

f

l-

O(O)MIN
(STAND OFF)

I

.339±.008

.402±.0 12
(10.20±O.30)

«~[r
~

-

--J

TYP

I

.031±.008

"A"

(0.80±0.20)

...1.
.006±.002
1O.15±0.05)
.098(2.50)
MAX

Detail of "A" part

.750(19.05)REF
© 1988 FUJITSU LIMITED F32004S·1C

4-42

.007(0.18)
MAX
.02710.68) Dimensions in
MAX
inches (millimeters)

MB8287-25
MB8287-35
March 1989
Edition 2.0

32K x a-BIT STATIC RANDOM ACCESS MEMORY
WITH PARITY GENERATOR AND CHECKER
The Fujitsu MB8287 is 32768 words x 8 bits high speed static random access
memory with parity generator and checker, fabricated with CMOS technology.
To obtain smaller chip, cell consists of NMOS transistors and resistors therefore
this device is assembled in 300 mil DIP and has such small power dissipation
as 605mW max.
All pins are TTL compatible and single 5 volt power supply is required.
A separate chip select (CS,) pin simplifies multipackage systems design. It
permits the selection of an individual package when outputs are OR·tied,
and furthermore on selecting a single package by CSt the other deselected
packages automatically power down.
All devices offer the advantages of low power dissipation, low cost, and high
performance.
• Organization: 32768 words x 8
bits
• Static operation: no clocks or
timing strobe required
• Fast access time:
tAA ~ tACS1 ~ 25ns max,
tACS2 ~ 14ns max (MB8287-25)
tAA ~ t ACSl ~ 35ns max,
tACS2 ~ 15ns max (MB8287·35)
• Low power consumption:
715mW max. (Operating) for 25ns
605mW max. (Operating) for 35ns
138mW max. (TTL Standby)
83mW max. (CMOS Standby)
• Single +5V supply ±10% tolerance

PLASTIC PACKAGE
(DIP-32P-M02)

• TTL compatible inputs and outputs
• Three-state outputs with OR·tie
capability
• Chip select for simplified memory
expansion, automatic power down
• Internal parity generator and
checker.
• All inputs and outputs have pro·
tection against static charge
• Standard 32·pin DIP package
(300 mil): (Suffix: P-SK)
• Standard 32·pin FPT package
(450 mil): (Suffix: PF)

PLASTIC PACKAGE
(FPT-32P-M02)

PIN ASSIGNMENT
As
A.4
A3
A2
Al
Ap
A12
A13
A14
OE
CS 2

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating

Symbol

Value

Unit

Supply Voltage

Vcc

-0.5 to +7

V

Input Voltage on any pin
wi th respect to G ND

V1N

-3.5 to +7

V

Output Voltage on any 1/0
pin with respect to GND

VOUT

-0.5 to +7

V

Output Current

lOUT

±20

Power Dissipation

Po

1.0

W

Temperature Under Bias

T B1As

-10 to +85

DC

Storage Temperature ·Range

TSTG

-45 to 125

DC

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Ag
A10
Al1

N.C.

CS1

1/°1
1/°2
1/°3

WE
II0s
1/07
I/Os
1/°5
1/°4

GNO

GNOQ

PE

mA

VCC
As
A7
As

This device contains circuitry to protect the

inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-

mum rated voltages to this high impedance
circuit.

4-43

1IIIIDlIDIllIDImmliliOOll liliMI

. FUJITSU
llllllllllllllllillmllilimmllllllllillil

MB8287-25
MB8287-35

Fig. 1 - MB8287 BLOCK DIAGRAM
~Vcc

MEMORY CELL ARRAY
256 x 128x8
(11O DATAl

ROW
DECODER

ADDRESS
8UFFER

256 x 128
(PARITY DATAl

I/O GATE
&
COLUMN DECODER

ADDRESS
BUFFER

-GND

1-------L,~"7"i~---r-r-..,J

PARITY
CONTROLr-_~~_ _ _~_--'

1/01

1/03
1/02

1/05

1/04

1/07
1/06

I/OS

TRUTH TABLE

CAPACITANCE

CS,

WE

OE

SUPPLY CURRENT

1/0, PE STATE

H

X

X

X

STANDBY

Is.

HIGH·Z

X

X

DESELECT

Icc

HIGH·Z

H

H

DOUT DISABLE

Icc

HIGH·Z

H

L

READ

Icc

DouT

X

WRITE

Icc

D'N

MODE

(TA = 25°C, f = 1MHz)

Parameter

Condition

Symbol

Min

Typ

Max

Unit

VIN = OV

C I1

8

pF

Input Capacitance (Other Input)

VIN = OV

C I2

7

pF

I/O Capacitance (with PEl

Vila = OV

CliO

8

pF

Input Capacitance (CS1 ,

4-44

CSt

C~,

OE, WE)

11111111111111111111111111111111111111111111111~~1
FUJITSU

MB8287-25
MB8287-35

1111111111111111111111111111111111111111111111111111

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter

Symbol

Min

Typ

Max

Supply Voltage

Vee

4.5

5.0

5.5

V

Ambient Temperature

TA

0

70

°c

Unit

DC CHARACTERISTICS
(Recommended operating conditions unless otherside noted)
Parameter

Symbol

Test Conditions

Max

Unit

IS81

CS1 ~ Vee-0 .2V
V ,N ~ Vee-0.2V or V ,N ~ 0.2V

15

mA

IS82

V ,N ~0.2V
Cs1 = V ,H

25

rnA

Icc

lOUT = OmA.
Cycle = Min.

Standby Supply Current

Operating Supply
Current

I

25ns

I

35ns

Input Leakage Current

= OV to

Min

130

Cs 1 = V,L

110

rnA

ILl

V ,N

Vee

-5

5

J.i.A

Output Leakage current

I Lilo

CS 1 = V ,H = or CS2 = V ,L or
WE = V ,L or OE = V,H •
VI/O = OV to Vee

-5

5

J.i.A

Input Low Voltage

V ,L

-2.0'1

0.8

V

Input High Voltage

V ,H

2.2

6.0

V

Output High Voltage

V OH

Output Low Voltage

VOL

0.4

V

= -4mA
IOL = 8mA
(V ,L min. = -0.5V at DC level)

2.4

IOH

Note: "1 -2.0V Min. for pulse width less than 20ns.
All voltages are referenced to GND.

V

Fig. 2 - AC TEST CONDITIONS
•

Input Pulse Levels:

0.6V to 2.4V

•

Input Pulse Rise & Fall Times:

3ns (Transient between O.8V and 2.2V)

•

Timing Reference Levels:

Input:
V,L = 0.8V. V,H = 2.2V
Output: VOL = 0.8V. VO H = 2.2V

•

Output Load:

+5V

'I DOUT
!IIOI

1

o----~--4

r

C '2

PE pin is included.
*2 Including Scope and Jig Capacitance

*1

li'rr

R1

R2

J

CL

Load I

480n

255n

I

30pF

Load II

480~n~_L-_25~5_n__IL-_5~p_F__L-I__t~Lz~._t~H~z.~t~w~z~.t~o~w~.~tO~L=Z~.~tO~H=Z~.~tp~H~z~a_nd~tp~O_H=Z_____-"

I
I

Parameters Measured

except tLz. tHZ' twz. tow. tOLZ. tOHZ. tpHZ and tpOHZ

4-45

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

MB8287-25
MB8287-35

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)

READ CYCLE*'
MB8287-25
Parameter

Unit
Min

Max

Min

Max

35

Read Cycle Time

t RG

Address Access Time '2

tAA

25

35

ns

CS 1 Access Time '3

t AGS1

25

35

ns

C~ Acces Time '3

t AGS2

14

15

ns

OE Access Time

tOE

12

14

ns

Output Hold from Address Change

tOH

3

3

ns

Output Active from CS1 '4'5

t LZ1

5

8

ns

Output Active from Cs, '4'5

t LZ2

2

3

ns

Output Active from OE'4'5

tOLZ

2

3

ns

Output Disable from CS1 '4' 5

tHz1

1

15

1

15

ns

Output Disable from C~ '4'5

tHz2

1

15

1

15

ns

Output Disable from OE'4'5

tOHZ

1

15

1

15

ns

Parity Error Access from Address'2

tAPA

28

40

ns

Parity Error Access from CS1 '3

tAPGS1

28

40

ns

Parity Error Access from Cs, '3

t APGS2

14

15

ns

Parity Error Access from OE

t APOE

12

14

ns

Parity Error Hold from Address Change

tpOH

3

Parity Error Disable from Address Change '4'5

tPHZA

1

20

1

25

ns

Parity Error Disable from CS1 '4 '5

t pH Z1

1

15

1

15

ns

Parity Error Disable from Cs, '4'5

t pHZ2

1

15

1

15

ns

Parity Error Disable from OE'4'5

tpOHZ

1

15

1

15

ns

Note: *1
*2
*3
*4
*5

4-46

MB8287-35

Symbol

-

25

ns

3

WE is high for Read Cycle_
Device is continuously selected, CS1 = VIL, C~ = V IH and OE = VIL.
Address valid prior to or coincident with CS1 transition low, CS2 transition high.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

ns

1111111111111111111111111111111111111111111111111111

MB8287-25 FUJITSU
MB8287-35

1111111111111111111111111111111111111111111111111111

READ CYCLE TIMING DIAGRAM*1
READ CYCLE: ADDRESS CONTROLLED*2

I--------'RC--------i
VALID

ADDRESS

i-----'AA-----i
DATA OUT

PREVIOUS DATA VALID

EI

READ CYCLE: CSt, C~ CONTROLLED*3

,oo"'~ =>{=~-=-t=AA~-___i~.I-V::-D--_-_-_----"TT";:TT7'7'T:rr7'7'T:rT

·~t~~t~w~R~1i:_ _ ___
.1- tOH f.I
! . Hlgh-Z

t w P - - -..

I+--

tow

K

Data Valid

i~

cisssss\\\\
Hlgh-Z

Write Cycle No.2 (CS Controlled) 1,2,3

I-

twe ================~.t.1_____
Address---""*,...---------------------~)[r--.

I_

____

I

lAW

I

•

"'is,,"tAS H
i

tew

i

~I:
--------i.~Irr,r'T'l~:'T'TlrT7'TTT7

I-

I .

tlZzmlllOWl

twp

.... tWR:;j"
•

~\~STS~SS~STS~ssns~~~~~s~s~S\ns~Si
DIN

DOUT

High Z

+r;- - - - - - - - -

: :

~

: :

~

r--

.

i

tLZ

.~ twt'~

-------+r-----lC~WXXXX&XXXXf

~

to\ll'

_,_

tOH-..i

_-I Hlgh-Z
);

Data Valid!

~

tow4

~

Hlgh-Z
Legend:

1m Don't Care

~

~

Undefined

NOTES:
1. The Write Enable (WE) signal must be high during an address transition.
signals are In the Read Mode, the associated 110 pins are In the output
2. If the Output Enable (OE) and Chip Select
state; accordingly, Input signals of opposite phase must not be applied to the outputs.
3. If CS goes high prior to or coincident with the low-to-hlgh transition of WE, the output remains In high-Impedance state.
4. This parameter Is specified at a point ~ 500 mV from steady-state voltage with an output capacitance of 5 pF.

les)

4-61

111~IM~MI~IOOIMMIIIMII
FUJITSU

1IIIIIIIOOlllillll~IOOIOOIIIIIIIIOOII

..

MB8421 122-90
MB8421/22-90L
MB8421/22-12
MB8421/22-12L

Data Contention Cycle No. 1 (Address Controlled)" 2:

f13~~::SLRI-)_ _ _oJ*'
\--tAPS

1'------------;

Address L = Address R

!

oJi,

Address R _ _ _ _ _ _ _ _
(Address L)

Address L

=:'. Address

R

I+- tSDA_1:

i---tsAA-1

:
:
,
!
:,,

,

!

:,,

J.r-------

--------------------~~
:

'

Data Contention Cycle No. 2 (CS Controlled)" 3:

~

Address L = Address R

j.-- tAPS---*!

:

;,

- - - - - - - - - -.....~

Address L = Address R

j.-- tSAC --i;;

L-----..i
rtSDC~
:
:

+'------------.Jt
NOTES:
,. In case of dual-access at the same memory location. the port that accesses the RAM first sets the

2.
3.

4-62

Chip Select {CS) signal must be low before or coincident with an address transition.
Address is valid prior to or coincidence with the high-to-Iow transition of

Cs .

BUSY

flag HIGH.

MB8421 122-90
MB8421/22-90L
MB8421 122-12
MB8421/22-12L

1111111111111111111111111111111111111111111111111111111111111111

FUJITSU
11111111111111111111111111111111111111111111111111111111111111111

AC CHARACTERISTICS
Parameter

Interrupt Cycle 'Timing
Address R
W
(Address L) _ _--'PZ

r

7FE (7FF)

f- -J
tAS

-----~~~

~,,-_ _ _ _ _ _ _ _ _ __
_""'_

tWA-j

____~1~---L---------------------

lEI

_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-=~'--7-FE-(-7F-F-)

~~J~::s LR)~======::===:+-it-

WEL
(WE A )

DEL
(OE A )

-----

!

~tWR~

:

:

/lllITmzzlllo;)vmZZZZVlmJlllM
.
,

I

:

I:'
.:

f

I

\\\\\\\\\\\\\\\$\\\\\\\\\\\\\\\\\\\\\\\\\$,

I-

t'NS-/

- -------------11'----___ :

:

'lk

::

iI---

tiNA

r-:

i'

I----

tINA----.j

Legend:

NOTE:

--!

::

~

Undefined

MB8421 only.

4-63

1 1 1~l il l~l l i~I~l l l il ~lil il il l l l~I~1 1 ~:~:~ ~ ~~~=~gL
FUJITSU

1~111~111111~11~111~11111111111111~111111~llilll~

MB8421/22-12
MB8421/22-12L

AC CHARACTERISTICS (Continued)
DATA RETENTION PARAMETERS & TIMING

Yee

lEI

:

-------4-.5-Y'""~--

I--

Cs

llllf. \

tORS

------i

Data Retention Mode
_ _ _ ..Y~

___ ___ )

l~_______
4.5Y

i---- t R _ 1

Cs~ Ycc-0.2Y

I,....-....;~....
\.....,\\,...S....S'"'S\

: 2.2Y

2.2Y·
Legend:

~

NOTE: Yee = YDR = 3Y
eS L & eSR ~ Yee - 0.2

AC TEST CONDITIONS
Input Pulse Levels: 0 to 3. OY
Input Pulse Rise & Fall Times: t R. tF= 5ns
12500

Timing Reference Levels: 1. 5Y
Output Loads:

110

4-64

5750

BUSY

-----4

..!...

INT

7750

NOTE: Includes Jig and stray capacitance.

_~+5Y

50pF
llNotS)

Undefined

MB8421/22-90
MB8421 122-90L
MB8421/22-12
MB8421 122-12L

111111111111111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS
48-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE NO.: DIP-48P-M02)

2372:+:g?~(6025 :+:g~g)

-,
0

II

II

034:+:J>20
(0.865:+:g· 5O)

l1li

"'

.050:+:J>20
(1.27:+:g· 5O )

~""'.~'
.118(3.00) MIN

.050(1.27)
MAX

100(2.54)

TYP

.018±.003
(0.45 ± 0.08)

.020(0.51) MIN

Dimensions in

© 1988 FUJITSU LIMITED D48003S-3C

inches (millimeters)

4-65

II~IIIIIII~IIIIIIIIIIIIIIIIIIIIIIIII
FUJITSU
111111111111111111111111111111111111111111111111111111

MB8421 122-90
MB8421/22-90L
MB8421/22-12
MB8421/22-12L

PACKAGE DIMENSIONS Continued
64 LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-64P-M01)
.132(3.35) MAX
(SEATED HEIGHT)
.002(0.05) MIN

I (STAN DOFF)

~

J
.642±.016
(16.30±0.40)

.736±.016
(18.70±0.40)

.472(12.00)

-Lr
11

II

"A"

.006±.OO2
(0.15 ± 0.05)

"8"

~~~_.I,

I I _70~8:6~0~;5) I "l!
'C_,

~.878±.016(22.30±0.40)~

© 198B FUJITSU LIMITED F64005S-6C

4-66

Dimensions in
inches (millimeters)

MB8421/22-90
MB8421/22-90L
MB8421 122-12
MB8421/22-12L

IIIIII~I~~IIIIIIOO~IIIMIW~I
FUJITSU

IOOII~IOOIIIIII~IIIIIIII~IIIIII~11111

PACKAGE DIMENSIONS Continued
52-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-52P-M01)

~1~~-~~~:~1~'86~0~~~gO=1~~(4~7'2~S~~~g~~g~)~~~~~1
f.S43±.010
L¥i'im=;;=;:;=rn=;m=;;=;:;=n=;:;m=n=r=iTTi=n=rrn=iTTi=n=rrn=r=rI"

J"'"

III

Q.207(S.2S) MAX
'-f--1.118(3.00) MIN
.070±.007
(1.778±0.18)

.020(0.Sl) MIN

1.750(44.4S} REF

© 1988 FUJITSU LIMITED D52002S-2C

Dimensions in
inches (millimeters)

4-67

Application Specific SRAMs

4-68

Static RAM Data Book

cP

October 1989
Edition 1.0

FUJITSU

DATA SHEET

AliJ8431/32-90~90Ll-90LLI-121-12L1-12LL

CMOS 16K-BIT DUAL PORT SRAM
2K X 8-BIT CMOS DUAL PORT STATIC RANDOM
ACCESS MEMORY
The Fujitsu MB8431132 are 2K words x 8 bits Duel pelt high;lerformance-stalic Random
Access Memories (SRAMs) fabricated in CMOS. The SRAMs use esynchronous circu~s;
Ihus no eX1l9maI clockes are required.
The MB8431 and MB8432 provide !he user wilh two separalaly contorolled I/O poIts wilh
independent address. Chip select ~). Wrile Enable ~). Output Enable iQt) and 110
functions.

DIP-52P-M01
(MB8431)

This arrangement permits independent access to any memory location for either a Raad or
Wr~ operation - a usefulleature for shared data processing app6cations. These devices
have lin automatic power-down feature controlled by (CS).
To avoide data contantion on Ihe same address, a (~ input is provided for address
arbitration; In addition, MB8431 utilizes (1IiITi tlag which allows communication between
syslems on either side of !he RAM.
801h devices use a single +5volt power supply and all pins are TTL-
~4Bon
DOUT--"'-~

30P;[

!including Scope
and Jig Capacitance)

5-14

T
h

>
~4Bon
DOUT--'--~

(Including Scope

5PFl
T

and Jig Capacitance)

Tfr

1111111111111111111111111111111111111111111111111111

FUJITSU

MB81C78A-45-W IIIIIIIIIIIIIII~IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)

READ CYCLE"

MB81C78A·45-W
Parameter

Symbol

Unit
Min

Max

Read Cycle Time

tRC

Address Access Time '2

tAA

45

ns

tACS'

45

ns

CS2 Access Time '3

t ACS2

20

ns

Output Hold from Address Change

tOH

_.-

CS, Access Time

45

'3

-

OE Access Time

ns

3

20

tOE

Output Active from CS,

ns

ns

t LZ '

5

ns

Output Active from CS2 '4 '5

t LZ2

0

ns

Output Active from OE '4 '5

tOLZ

0

ns

Output Disable from

'4 '5

CS, '4 '5

Output Disable from CS2 '4 '5
Output Disable from

Note: *1
'2
*3
'4
*5

OE'4 '5

t HZ '

25

ns

tHZ2

25

ns

tOHZ

25

ns

WE is high for Read cycle.
Device is continuously selected, CS, = V 1L , CS2 = V 1H and OE = V 1L .
Address valid prior to or coincident with CS, transition low, CS2 transition high.
Transistion is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

5-15

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

MBB1C78A-4S-W

READ CYCLE TIMING DIAGRAM"

READ CYCLE I: ADDRESS CONTROLLED'2

f - - - - - - - - - t A C:------.....,
ADDRESS

DATA OUT

READ CYCLE II:

PREVIOUS DATA VALID

CS"

CS2 CONTROLLED'3

ADDRESS~~~r---------------------------------------~r""'f"'"

1/0

m:
Note: *1
*2
*3
*4
*5

5-16

Don't Care

~ : Undefined

WE is high for Read cycle.
Device is continuously selected, CS, = V'L, CS2 = V'H and OE = V'L'
Address valid prior to or coincident with CS, transition low, CS 2 transition high.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

1111111111111111111111111111111111111111111111111111

FUJITSU

MB81C78A-45-W

1111111111111111111111111111111111111111111111111111

WRITE CYCLE"

MB81C78A-45-W
Parameter

Symbol

Unit
Min

Max

Wirte Cycle Time '2

twc

45

ns

CS, to End of Write

tcw,

40

ns

CS2 to End of Write

tCW2

25

ns

Address Valid to End of Write

tAW

40

ns

Address Setup Time

tAS

2

ns

Write Pulse Width

twp

25

ns

Data Setup Time

tow

20

ns

Write Recovery Time '3

tWR

3

ns

Data Hold Time

tOH

3

ns

Output High-Z from WE'4'5

twz

Output L:ow-Z from WE'4'5

tow

Note: *1
*2
*3
*4
*5

20
0

ns

ns

If CS, .goes high simultaneously with WE high, the output remains in high impedance state.
All write cycles are determined from the last address transition to the first address transition of next address.
tWR is defined from the end point of Write Mode.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

5-17

~~~~I~I~~II~MIIII~~~~i~
FUJITSU

~lim~~lm~~~~~lml~~il~ MB81C78A-45-W

WRITE CYCLE TIMING DIAGRAM:'

WRITE CYCLE I: CS" CS2 CONTROLLED

~-tA,S~-r----------tcw,----------+--'W!R~~

cs,

CS2

110

m :Don't Clr.
Note: *1
*2
*3
*4
*5

5-18

I8XI :Undefined

If CE, CS" and CS2 are in the READ Mode during this period, I/O pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
All write cycle are determined from the last address transition to the first address transition of next address.
tWR is defined from the end point of WRITE Mode.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load IT in Fig. 2.

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIm

FUJITSU

MB81C78A-45-W

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImlillmllili

WRITE CYCLE TIMING DIAGRAM·'

WRITE CYCLE II: WE CONTROLLED
~________________ twC~·2~____________~~

1--------------tAW-------------+o--tW-R---:·!"::i3

cs,

tow

1/0

tOH

DIN VALID

c::J :Don't Care

Note:

*,
*2
*3
*4
*S

1881 :Undefined

If OE, CS" and CS 2 are in the READ Mode during this period, I/O pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
All write cycles are determined from the last address transition to the first address transition of next address.
tWR is defined from the end point of WRITE Mode.
Transition is specified at the point of ±SOOmV from steady state voltage.
This parameter is specified with Load n in Fig. 2.

5-19

~~~m~moollmlllll~~~lllmll~mlml
FUJITSU

1IIIIImllllmllm~~~~I~mll~~~~I~~ MB81C78A-45-W

PACKAGE DIMENSIONS
28-I..£AD CERAMIC (METAL SEAL) DUAL IN-LINE PACKAGE
(CASE No.: DIP·28C-A08)

0° to gO

_.::.::::,,1

"~"l :1~: ,:~: ~[ ~ ~ ~13~1
REF

INDEX
AREA

I

(3S.S6±0.S1 )

Tf
J

.300±.010
(7.62±0.2S)

t

t

.010±.002
(0.2S±0.OS)

.2oo(S.08)MAX
.134'.014
(3.40.0.36)
.018::885

.1oo±.010
(2.54±0.25)

(0.46:8:M)

.050±.010
(1.27±0.25)

1.300(33.02)REF
© 1987 FUJITSU LIMITED D28020S-2C

5-20

Dimensions in
inches (millimeters)

MB81C78A-45 -w

1~llllmlllllllll~lml~mmlllllllllm~m
FUJITSU
Iml~lllllml~~~~I~~~~~lllml~MI~

PACKAGE DIMENSIONS (continued)
CERAMIC LCC (Suffix: -CVI
32-PAD CERAMIC (METAL SEALI LEADLESS CHIP CARRIER
(CASE No.: LCC-32C-A021

'PIN NO.1 INDEX

.36019.14)TVP
C.01510.38)TVP

I

.06511.65)
TVP

MAX

.050i.006
11.27±0.15)
.30017.62)TVP

* Shape of PIN NO.1 INDEX: Subject to change without notice.
© 1987 FUJITSU LIMITED C32011S'3C

Dimensions in inches
(millimeters)

5-21

Wide Temperawre Range SRAMs

5-22

Stalk;

RAM Data Book

MB81C79A-45-W
September 1988
Edition 1.0

12K-BIT (8192x9) HIGH SPEED CMOS STATIC RANDOM
ACCESS MEMORY WITH AUTOMATIC POWER DOWN
The Fujitsu MB81 C79A-W is 8192 words x 9bits static random access memory
fabricated with a CMOS process_ The memory utilizes asynchronous circuitry
and may be maintained in any state for an indefinite period of time. All pins
are TTL compatible and a single 5 volts power supply is required.
I

A separate chip select (CS,) pin simplifies multipackage systems design. It
permits the selection of an individual package when outputs are OR-tied,
and furthermore on selecting a single package by CS" the other deselected
packages automatically power down.

CERAMIC PACKAGE
DIP-28C-AOS

All devices offer the advantages of low power dissipation, low cost, and high
performance.

• Organization: 8192 words x 9 bits
• Static operation: No clock or timing strobe required
• Fast access time: tAA; tACS' ; 45 ns max_ (MB81C79A-45-W)
• Low power consumption: 660 mW max. (Operating)
165 mW max. (Standby, TTL level)
110 mW max. (Standby, CMOS level)
• Single +5V supply, ±10% tolerance
• TTL compatible inputs and outputs
• Three-state outputs with OR-tie capability
• Chip select for simplified memory expansion, automatic power down
• All inputs and outputs have protection against static charge
• Standard 28-pin Ceramic DIP package (Suffix: -C)
• Standard 32-pad Leadless Chip Carrier (Suffix: -CV)

CERAMIC PACKAGE
LCC-32C-A02

PIN ASSIGNMENT

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating

Symbol

Value

Unit

Supply Voltage

Vee

-0.5 to +7

V

Input Voltage on any pin
with respect to GND

V IN

-0_5 to +7

V

Output Voltage on any 1/0
with respect to GND

VOUT

-0.5 to +7

V

Output Current

lOUT

±20

mA

Power Dissipation

Po

1.0

W

Temperature Under Bias

T BIAS

-65 to +135

°c

:f4~i5~16:'-7-r,ir.~19i:iO~

I/03VSStv.C 1/0,110,
110.
110.

Storage
Temperature

TSTG

-65 to +150

°c

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

This device contains circuitry to protect the
inputs against damage due to-high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum, rated voltages to this high impedance

circuit.

5-23

li~~I~III~IIOOmm~IOO!~1
FUJITSU

II~OOI~m~~~IOO~~I~ MB81C79A-45-W

Fig. 1 - MB 81C79A BLOCK DIAGRAM

f--

·
·
·

ADDRESS
BUFFER

f---

-Vee

·
·
·

ROW
DECODER

-GND

256 x 32 x 9
MEMORY CELL
ARRAY

-

-

1 . . .

Js*

I

110 GATE
&
COLUMN DECODER

ADDRESS
BUFFER

. . .

I

JS*

BUFFER

I
f - - cs

DATA 1/0 BUFFER

Js

111111111

110 1
1/03
1/05
1/07 .1/0 9
1/06
II0 a
1/02
1/0 4

TRUTH TABLE
CS 1

CS 2

WE

OE

SUPPLY
CURRENT

I/O
STATE

H

X

X

X

STANDBY

ISB

HIGH-Z

L

L

'x

X

DESELECT

Icc

HIGH-Z

L

H

H

H

Icc

HIGH-Z

L

H

H

L

DOUT DISABLE
READ

Icc

DOUT

L

H

L

X

WRITE

Icc

DIN

MODE

Max

Unit

C I1

7

pF

Input Capacitance (V 1N = OV) (Other Inputs)

Cl2

6

pF

I/O Capacitance (V IIO = OV)

CliO

B

pF

Parameter

Input Capacitance (V IN = OV) (CS 1 • CS2 •

5-24

Symbol

DE. WE)

Typ

1IIIIIIImllllllllll~IIII~IIIII~ml~mll~111
FUJITSU

MB8le79 A-45 -w 1~~lllllllmllllllll~mm~I~~~~lm~I~1

RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage

Vee

4.5

5.0

5.5

V

Input Low Voltage

V ,L

-0.5

0.4

V

Input High Voltage

V ,H

2.6

6.0

V

Ambient Temperature

TA

-55

+125

°c

Parameter

* -2.0V Min. for pulse width less than 20 ns. (V ,L Min = -0.5V at DC level)

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Symbol

Min

Max

Unit

Test Condition

Input Leakage
Current

ILl

-10

10

p.A

Y'N

Output Leakage
Current

I Lo

-10

10

p.A

CS, = V ,H or CS2 = V ,L or WE
OE = V ,H • VOUT = OV to Vee

Operati ng Supply
Current

Icc

120

mA

CS, = V ,L
1/0 = Open, Cycle

158 ,

20

mA

Vee = Min to Max. CS, = Vee-0.2V
Y'N ~ 0.2V or Y'N ~ Vee-0.2V

1582

30

mA

CS,

= V ,H

Output Low
Voltage

VOL

0.45

V

IOL

= SmA

Output High
Voltage

V OH

V

IOH

= -4mA

Peak Power-on
Current

Ipo

Standby Supply
Current

2.4

50

mA

= OV to Vee
= V ,L

or

= Min

Vee = OV to Vee Min.
CS, = Lower of Vee or V ,H Min.

5-25

lil~l~i~iMi~III~III~iilll~li
J:"WITSU

ilmlil~iUiiiM.ilml~iiOO MB81C79A-45-W

AC TEST CONDITIONS

Input Pulse Levels:

OV to 3.0V

Input Pulse Rise And Fall Times:

5ns (Transient time betweenO.4V and 2.6V)

Timing Measurement Reference Levels:

Input:
Output:

1.5V
1.5V

Fig. 2
Output Load

Output Load I.

n.

For all except tLz, t HZ , twz, tow,
toLz, and toHz.

~

5V

>
-j;.

~

48011

DOUT - - . - - - 4

d, '$>

DOUT

30P
(Including Scope
and Jig Capacitance)

5-26

T
h

_

48011

r

>
-j;.
T
"T1r

5pF-L
25511

(Including Scope
and Jig Capacitance)

25511

1~1~lli~IIII!IIIII.

rWITSV

MBB1C79A-45-W ~IIIIIUlIU_

AC CHARACTERISTICS

(Recommended operating condition. unless otherwise noted.)

READ CYCLE"'

MBSI C79A·45-W
Parameter

Symbol

Unit
Min

Max
ns

45

Read Cycle Time

tRC

Address Access Time '2

tAA

45

ns

CS, Access Time '3

tACS'

45

ns

C~ Access Time '3

tACS2

20

ns

Output Hold from Address Change

tOH

OE Access Time

tOE
-

Output Active from CS,

-4-5

3

ns

20

ns

tLz,

5

ns

Output Active from CS2 '4 '5

t LZ2

0

ns

Output Active from OE '4 '5

tOLZ

0

ns

Output Disable from CS, '4 '5

tHz,

25

ns

Output Disable from CS2 '4 '5

tHZ2

25

ns

Output Disable from OE'4'5

tOHZ

25

ns

Note: *,
*2
*3
*4
*5

WE is high for Read cycle.
Device is continuously selected, CS, = V 1L , CS2 = V 1H and OE = V 1L .
Address valid prior to or coincident with CS, transition low, C~ tra~sition high.
Transistion is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load n in Fig. 2.

11111111111111~~IIIIIIIIIII~~llmllllllllll~~
FUJITSU

~m~~mllmllllll~II~~I~III~~~III~~~ MB81C79 A-45-W

READ CYCLE TIMING DIAGRAM"

READ CYCLE I: ADDRESS CONTROLLED'2

f--------tRc--------i
ADDRESS

~~---------------/r~~~~

f-----tAA---~
DATA OUT

PREVIOUS DATA VALID

READ CYCLE IT: CS,. CS2 CONTROLLED'3

AO"~ ~ ~- =~- =~- =~- t-A- A-~-~- =~- =- -=~- :~-t-Rc- - :- - :- - : - :- - :- -,.:-~:~k;-~l
cs,

1/0

____,r-o----tACS'----I

DOUT VALID

Ea :Don't Care
Nota: *1
*2
*3
*4
*5

5,,;,28

1881 :Undefined

WE is high for Read cycle.
Device is continuously selected. CS, = V 1L • CS2 = V 1H and OE = V 1L .
Address valid prior to or coincident with CS, transition low. CS 2 transition high.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load IT in Fig. 2.

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImmOOI

FUJITSU

MB81C79A-45-W

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImlllillmimii

WRITE CYCLE"'

MB81C79A·45·W
Parameter

Unit

Symbol
Min

Max

Wirte Cycle Time' 2

twc

45

ns

CS, to End of Write

tCWl

40

ns

CS2 to End of Write

tCW2

25

ns

Address Valid to End of Write

tAW

40

ns

Address Setup Time

tAS

2

ns

Write Pulse Width

twp

25

ns

Data Setup Time

tow

20

ns

Write Recovery Time' 3

tWR

3

ns

Data Hold Time

tOH

3

ns

Output High·Z from WE' 4 ' 6

twz

Output Low·Z from WE' 4 ' 6

tow

20

0

ns

ns

Note: "1 If CS, goes high simultaneously with WE high, the output remains in high impedance state.
"2 All write cycles are determined from the last address transition to the first address transition of next address.

"3 tWR is defined from the end point of Write Mode.
"4 Transition is specified at the point of ±500mV from steady state voltage.
*5 This parameter is specified with Load n in Fig. 2.

5-29

m~I~~~~~~lmllll~lllllmlllllm~~I~1
FUJITSU

Im~~mllm~llillll~~llllm~~~I~~ml

MB81C79A-45-W

WRITE CYCLE TIMING DIAGRAM"

WRITE CYCLE I: CS,. CS2 CONTROLLED
~

_________________ twc'_2______________

~

~--------------tAW----------~~

~r----------tcw,--------~~

I/O

o:

Don't Car.

Note: '1

'2
*3

'4
*5

5-30

IZ:8I :Undefined

If OE. CS,. and C~ are in the READ Mode during this period. 1/0 pins are in the outP\lt state so that the input
signals of opposite phase to the outputs must not be applied.
All write cycle are determined from the last address transition to the first address transition of next address.
tWA is defined from the end point of WR ITE Mode.
Transition is specified at the point of ±500mV from steady state voltage.
This parameter is specified with Load n in Fig. 2.

111111111111111111~llllllllllllmlllllllllll~~~
FUJITSU

MB81C79A-45-W 1111111111111111111111~~lllmlllllmlllllllmll

WRITE CYCLE TIMING DIAGRAM"

WRITE CYCLE II: WE CONTROLLED
._ _ _ _ twC~·2'--_ _

ADDRESS

cs,

tDW

110

DIN VALID

o :
Note: *,

tOH

Don't Care

1821 :Undefined

If OE, CS" and CS2 are in the READ Mode during this period, I/O pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.

*2 All write cycles are determined from the last address transition to the first address transition of next address.
*3 tWR is defined from the end point of WRITE Mode.

*4 Transition is specified at the point of ±500mV from steady state voltage.
*5 This parameter is specified with Load U in Fig. 2.

5-31

lil~~~lmlll~lllllllllmlllll~il~il
FUJITSU

~~OO~~U~II~!~III. MBB1C79A-45-W

PACKAGE DIMENSIONS
28-LEAD CERAMIC (METAL SEAL) DUAL IN-LINE PACKAGE
(CASE No.: DIP-28C-A08)

0° to gO

__ -::::::~l

r

TT

I

.300 •.010
25 )

(7.62

!(0.25±0.05)
.010±.002

.200(5.0B)MAX
.134±.014
(3.40±0.36)

.0IB~:gg3

.1 00±.01 0
(2.54±0.25)

(0.46~g:6~)

.050'.010
(1.27'0.25)

1.300(33.02)REF
© 1987 FUJITSU LIMITED D28020S-2C

5-32

Dimensions in
inches (millimeters)

1111111111111111111111111111111111111111111111111111

FUJITSU

MB81C79A-45 -W 11~llmllllllm~~lmlllllllllml~III~~~11

PACKAGE DIMENSIONS (continued)
CERAMIC LCC (Suffix: -CV)
32-PAD CERAMIC (METAL SEAL) LEADLESS CHIP CARRIER
(CASE No _: LCC-32C-A02)

'PIN NO.1 INDEX

C.040(1.02)TYP

.360(9. 14)TYP

~LCS)

C.0151O.38)TYP

l

.460(11.68)
TYP

.400(10'16)J
TYP

~

.450~:~~~

.045(1~

.065(1.65)
TYP

TYP
.085(2.16)

MAX

I

.050±.006
(1.27±0.15)

.300(7.62)TYP

* Shape of PIN NO.1 INDEX: Subject to change without notice.
© 1987 FUJITSU LIMITED C32011S-3C

Dimensions in inches
(millimeters)

5-33

Widll T!!I!I!f1!!I!IIIf Range SBAMs

5-34

Static RAM Data Book

00

October 1989
Edition 1.0

FUJITSU

DATA SHEET

MB8464A-10-WI-15-W
CMOS 64K-BIT LOW POWER SRAM
S,192WORDS X SBIT CMOS STATIC RAM WITH LOW
POWER AND DATA RETENTION
The Fujitsu MB8464A is a 8192-word by &-bit stalic random access memory fabric:al8d with

a CMOS silicon gal8 process. The memory utilizes asynchronous circuitry and may be
maintained in any stal8 for an indefinil8 pariod of time. All pins are TIL compatible. and a
single 5volts power supply is required.
The MB8464A is ideany suil8d for use in microprocessor Bysl8ms and other applications
where fast access time and ease of use are required. All devices offer the advantages of low
power dissipation. low cost, and high performance.
•

Organization: 8192 words x 8 bits

•

Fast access time: lOOns max. (MB8464A-10-W)
150ns max. (MB8464A-I5-W)

•

Complel8ly static operation: No clock required

Ceramic Package (6OOm1l)
DIP-28C-A07

Ceramic Package (300m II)
DIP-28C-AOB

o

• TIL compatible input/output

Ceramic Package

•

Thre&-stal8 output

•

Common data input/output

•

Single +5V power supply. ±10% tolerance

LC~C-A02

PIN ASSIGNMENT
28
Veo
NC ~ 1
27
WE
All
2

•

Low power standby: llmW max.

•

Data rel8ntion: 2.0V min.

At
At

•

28-pin Ceramic package (300mil width)
(600rnil width)

•

32-pad Leadess Chip Carrier

28
2S

At

s

23

At

7

22

Symbol

Value

Unit

At
A,

0
10

110,
110,
110,

TOTO

-65 to +150

"C

Temperature Under Bias

T....

-65 to +125

"C

Supply Voltage

V""

~.5to+7.0

V

Input Voltage

T'N

~.5to

Output Voltage

Voon

~.5

NOTE:

Vet; +0.5

to V"" +0.5

V
V

20

19
18
17
18
15

11

12
13
14

OND

Storage Temperature Range

24

8 TOPYEW 21

At

ABSOLUTE MAXIMUM RATINGS {see NOTE~
Radng

3
4
5

A,

cs,
At
At
A"
OE
A"

cs;
IIDto
110,

IIDto
lIDo

va.

.,"~c"'(, WE...

. ....
Ao

2fFVtA

.4A3..

7·

At" .:tllo~

TOP VIEW

A,

.. ,i':
NO

110,

'110

u.

Permanent deVIce damage may occur If the above Absolute Maximum
Rat~. are exceeded. Functional operation should be restricted to the
condliOns as detailed in the operational sections of this data sheet. Exposure to
absolula maximum rating conditions for eXlended periods may affect device
reliability.

Qulclc prom •• ' _ 0 1 FUJITSU LIMITED
Capyrlgllt. ,9l1li by FUJITSU LIMlllOD

5-35

MB8464A·1D-W
MB8464A·15-W

Fig. 1 - MB8464A BLOCK DIAGRAM

r-

A..
An

··
·•

At.

A.
A.
A7

ADDRESS
BUFFER

Ao

r•
ROW
DECODER

ct

--oGND

··

256x32x8

MEMORY CELL
ARRAY

•
r-

r-

As

- - 0 Vcc

···

ADDRESS
BUFFER

.... 1

I

110 GATE
&

COLUMN DECODER

.... I

I

CTS
BUFFER

DATA 110 BUFFER

ct

! ! ! bbb! !

TRUTH TABLE
CSt cs,. OE WE
H

X

X

L
H
H
H

L
L
L

C~U::~~T

MODE

X
X

X NOT SELECTED
X NOT SELECTED

I..
lsa

H
L

H
H
L

Icc

X

DOUT DISABLE
READ
WRITE

~

CS

1/0 PIN

HIGH-Z
HIGH-Z
HIGH-Z
DOUT
DIN

Icc

Icc

CAPACITANCE (TA=25°C,f=1MHz)
Max

Unit

110 Capacitance (Vvo=OV)

Parameter

Coo

10

pF

Input Capacitance (V'N=OV)

C'N

7

pF

5-36

Symbol

Min

Typ

MB8464A-10-W
MB8464A-15-W

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage

Vee

4.5

5.0

5.5

V

Input Low Voltage

V'L

~.3·'

0.6

V

Input High Voltage

V'H

2.4

Vee+0.3

V

Ambient Temperature

T.

-55

+125

"C

01 -3.0V min. for pulse width less than 20ns. (V'L min.=-

-50

50

II-'

VIIO=OVIo Vee
CSI =V" or CS2=V'L or ~=V'H or WE"=V'L

Output Hligh voltage

VOH

2.4

V

IOH-I.0mA

Output Low voltage

VOL

V

IOL=2.1mA

0.4

Fig. 2 - AC TEST CONDITIONS
< Output Load >
+5V
: 0.4V to 2.6V
: Sns (Transition Time ba\ween 0.6V and 2.4V)
: Input: V'L=O.6V. V'H=2.4V
Output:VOL-O.BV. V",,=2.0V

• Input Pulse Lawls:
• Input Pulse Rise and Fall Times:
• Timing Reference Lawls:

Dout

• Output Load:

(I/O)

R,

Ra

CL

Load I

I.BKn

990Kn

l00pF

Load II

I.BKa

990Kn

5pF

Parameters Measurad
except!eLZ. IoLZ. !eHZ. lettz. Iwtz and lwHz
!ell. IoLZ. !eHZ. 10HZ. IwLZ and tw.z

:F

R,

:~

Ra

o------e-------.
CLo

l

I

-..=

o Including jig and stray capacitance

5-37

MB8464A-10-W
MB8464A-15-W

AC CHARACTERISTICS
(Recommended operating condHlons unless otherwise noted)
READ CYCLE
Parameter

MB8464A-1O-W

Symbol

Min

MB8464A-1S-W

Max

IIln

IRC

Address Access Time

t...

100

150

CS 1 Access Time

100

150

CS2 Access Time

t..c,
t..c.

100

150

Output Enable to Output Valid

10.

45

Output Hold from Address Change

IoH

10

10

Chip Select to Output Low-Z 'I

lou

10

10

Output Enable to Output Low-Z 'I

5

Chip Select to Output Hig~Z 'I

lou
IeHZ

Output Enable to Output Hig~Z 'I

10HZ

..

100

lIax

Read Cycle Time

150

60

5
40

50

40

50

'I TranSition IS measured at the POint of ±500mV from stady state voltage.

READ CYCLE TIMING DIAGRAM
READ CYCLE 1"2)

AOO"~ =1;::======IoH===-i:""==========.;;r------'~J<--­
PREVIOUS DATA VALID

DATA VALID

READ CYCLE 11"

.'

ADDRESS=i

t...
I

I

l'iI.

t..c,

I

t--lcHZ-

IeLZ

..k'I"
~

CS"

A
~

t..c.

i---IeHZ-

IeLZ-

li

A

1.':=

Dour

Note:

5-38

HIGH-Z

I---IoHz-

10.
IoLZ-

1) WE is high for Read Cycle.
2) Device is continuously selected, CS,=OE=V,L, Cs"=V'H.

X

)l

DATA VALID

HIGH-Z

MB8464A-10-W
MB8464A-15-W
WRITE CYCLE
Symbol

Par.m ....
Write Cyde Time

MB8464A-1D-W

MB8464A-15-W

Min

Iotln

M.x

!we

100

150

Address Valid to End of Write

t..w

80

100

Chip Select to End of Write

lew

80

100

Data Valid to End of Write

lew

40

50

Data Hold TIme

lett

5

5

Write Pulse Width

!w.

80

100

Address Set Up Time

t..s

0

0

Write Rec:ovmy Time

twA

10

10

Write Enable to Output Low-Z·l

!wLZ

5

Write Enable to Output High-Z·l

!wHZ

..

M.x

5
40

50

·1 Trans,uon IS measured at the point of ±500mV from stady state Voltage.

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE I (WE CONTROLLED)

ADDRESS

two

~

I[

i--1wA-

t..w

lew

lew
Cs,.

-t..s-l

!w.

l'
t--Iew-

HIGH-Z

-IoH

- r
twHz1l

Dour

Note:

--t

DATAINVAUD

)( )( X )( X )( )(

HIGH-ZL ....

"1

HIGH Z

)( )( )(

1) If OE, CS, and Cs,. are in the READ Mode during this period, I/O pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.

5-39

MB8464A-1Q-W
MB8464A-15-W
WRITE CYCLE II (CS, CONTROLLED)

!we

ADDRESS~

I[

t..w
OE

~

lew

-!wR-

CS,

lew
Cs.,

!w.
WE

~ low -

HIGH Z

D'N

hz')
DoUT

lot- toH

DATA IN VALID

HIGH Z

!wHZ')

-t

HIGH Z

--t

HIGH Z

WRITE CYCLE III (Cs., CONTROLLED)
Iwc

ADDRESS~

~

~

t..w
OE

lew
CS,

t..s

Cs.,

lew

-!wR-

!w.
WE

t---

HIGH Z

D'N

hz"
Dour
Nole:

5-40

HIGH-Z

low lot- toH
DATA IN VALID

--t

HIGH Z

twHZ 2)

HIGH--Z

1) If OE, Cs., and WE are in the READ Mode during this period, 1/0 pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
2) If OE, CS, and WE are in the READ Mode during this period, 1/0 pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.

MB8464A-10-W
MB8464A-15-W

DATA RETENTION CHARACTERISTICS
Recommended o):)eratlng conditions unless otherwise noted)
Parameter

Symbol

Min

Typ

Max

2.0

5.5

V

0.5

mA

Data Retention Supply Voltage "1

VDR

Data Retention Supply Current "2

lOR

Data Retention Setup lime

10...

Operation Recovery Time

'"

0

ns

tRC

ns

DATA RETENTION TIMING
DATA RETENTION I (Cs., CONTROLLED)

V~
Cs.,

___

r-.. j~~----:=::-:~=----~~t ·-----j

~V

DATA RETENTION"

(C8,

CS,SO.2V

j

CONTROLLED)

~

~

~
Note:

"1 Cs.,
CS,
"2 Cs.,
CS;

controlled:
controlled:
controlled:
controlled:

DATA RETENTION MODE

~

~

t

_________ ~~ _________~
J

cs,~VD~.2V

r-

YAYf--

'"

~

Cs.,SO.2V
CS,~VDR -O.2V

(Cs.,SO.2V or Csr-VDR -O.2V)
VDR=3.0V. Cs.,SO.2V
VDR=3.0V. CS;~VDR ...{J.2V (CS,gl.2V or CS""VDR -O.2V)

5-41

MB8464A·1D-W
MB8464A·15-W

PACKAGE DIMENSIONS
32·PAD CERAMIC (METAL SEAL) LEADLESS CHIP CARRIER
(CASE No.: LCC·32C·A02)

'PIN NO.1 INDEX

.360(9.141TYP
C.O 15(0.381 TYP

t:/----·-l

--T
I

i

.460(11.681
TYP

.400110.16i
TYP

I

n-l=l!=+=='=--- J
.06511.651
TYP

MAX

.... Shape of PIN NO.1 INDEX: Subject to change without notice.
©1988 FUJITSU LIMITED C32011S'3C

5-42

Dimensions in inches
(millimeters)

MB8464A-10-W
MB8464A-15-W

PACKAGE DIMENSIONS (Continued)
28·LEAD CERAMIC (METAL SEAL) DUAL IN·LlNE PACKAGE
(CASE No.: DIP·28C·A07)

,
... _-;.-;.:1

~~
~I C= r. . .:; : ; ; ;: ;: :; ; ;: :; ;: :; ; ;=:; ; ;: ~
AREA

~

1

"'.' 1' ' ' . . . ===l=II="Of

_I

1.400±.014
135.36±0.361

.010±.002
10.2S±0.051

1~'06111'S51~

lI

+
I.1 .....
"'L.Ol
0

~

12.S4±0.2SI

.600±.010

.595±.010

.....................--l.

"'h.......

~I

l

'y

1 0° to gO

!

!

-.-l .200IS.OSIMAX

I

+
.050_.004
11.27±0.101

II .00S+·
06 I
---l~
-.003
10.46~g:~1

~
I

.134±.014
13.40±0.361

050+ 010
{1.27~O.2SI

.1300133.02IREF
© 1988 FUJITSU LIMITED 028019S-2C

Dimensions in
inches (mill,meters)

5-43

MB8464A-1D-W
MB8464A-15-W

PACKAGE DIMENSIONS (Continued)
2S-LEAD CERAMIC (METAL SEAL) DUAL IN-LINE PACKAGE
(CASE No_: DIP-2SC-AOS)

0° to gO

__.:",,1

"00"1 ~~:,;.; :~[ ~ ~ ~138~1

Tf

REF

INDEX

AREA

.300 •.010
0 .25 )

1 (7.61

I

t(0.25.0.05)
.010'.002

(35.56.0.51 )

1~'060(1'52)MA:

i i .100+.010
I

~ Ul

(2.54.0.25)

.05O±.010
(1.27.0.25)

-1

.200(5.08)MAX

-r--

.134'.014
(3.40±0.36)

--J I .018~:ggg

(0.46~g:I,~)

]

-.050-.+-.0-10-'(1.27.0.25)

1.300(33.02)REF

© 1988 FUJITSU LIMITED D2S020S-2C

5~44

Dimensions in
inches (millimeters)

Section 6

CMOS SRAM Modules -

At a Glance

Maximum
Page

Device

6-3

MB85402-30
--40
MB85403A--40
--60

6-11

A_••
TIme (n.)
30
40

6-19

MB85410--30
--40

6-27

MB85414--30
--40

40
50
30
40
30
40

6-35

MB85420--40
--60

40
50

Package
Capeclly

Options

262144 bils
(16384w x 16b)
2097152 bits
(262144w x 8b)

36-pin

Ceramic SIP

44-pin

Ceramic SIP

524288 bits
(65536wx8b)

60-pin Plastic

ZIP

524288 bits
(16384w x 32b)
or
(32768w x 16b)

64-pin

Plastic

ZIP

2097152 bits
(262144w x 8b)

60-pin

Plastic

ZIP

6-1

CMOS SRAM Modules

6-2

Static RAM Data Book

IIIIIIIIIIIIIIIIIIIIIIIIIIIIII~~~~~~~~~~~

FUJITSU

16K x 16 CMOS SRAM MODULE

MB85402-30
MB85402-40

IIIIIIIIIIIIIIIIIIIIIIIIIIIIII~~~~~~~~~~~~
TS255-B88Y
Nov. 1988

CMOS 16,384 Words x 16-Bit STATIC
RANDOM ACCESS MEMORY MODULE
The Fujitsu MB85402 is a fully decoded, CMOS Static
random access memory module
comprised
of four
MB8lC75 devices mounted on a 36-pin ceramic board.
Organized as four 16K x 4 devices, the MB85402 is optimized for those applications requiring high speed,
high performance, low power and high density.
A separate output enable function provides maximum
control for those systems where bus contention may
be a problem.
• Organized as 16,384 x l6-bit Words
• Memory : MB8lC75, 4 pcs
• Access Time: 30 ns max (MB85402-30)
40 ns max (MB85402-40)
• Low Power Dissipation
Standby: 220 mW max (CMOS level)
440 mW max (TTL level)
Active : 1760 mW max
• Single +5V Power Supply, ±10% Tolerance
• Automatic Power Down
• TTL Compatible Input/Output Pins
• 3-State Output
• 36-Pin 100 MIL Ceramic DIP/SIP

ABSOLUTE MAXIMUM RATING

CERAMIC PACKAGE
MTP-36C-COl
PIN ASSIGNMENT
TOP VIEW

1

(See NOTE.)

Rating

Symbol

Value

Supply Voltage

VCC

-0.5 to +7.0

V

Input Voltage

VIN

-3.5 to +7.0

V

Output Voltage

VOUT

-0.5 to +7.0

V

Short Circuit
Output Current

lOUT

±20

Power Dissipation

PD

4.0

Temperature
under Bias

TBIAS

-10 to +85

DC

Storage
Temperature

TSTG

-65 to +150

DC

Unit

mA

W

NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods lJ1ay affect device reliability.

DQo
DQl Z
DQZ
DQ3 4
AO 5
Al 6
A2 7
A3 S
A4 9
AS 10
A6 11
A7 12
DQ4
DQ5
DQ6
DQ7
"CS
GND

36
35
34
33
32
31
30
29
2S
27
26
25
24
23
22
21
20
19

Vee
DQ15
DQ14
DQ13
DQ12
GND
Al3
A12
All
AID
Ag
AS
DQll
DQIO
DQg
DQS
WE:

Dr

ThiS device contains circuilrY to protect the
inputs against damage due to·high static vol1·
ages or electric fields. However. it is advised
thai normal precautions be taken to avoid
application of .anv voltage higher than maxi·
mum rated voltages to this high impedance
circuit

6-3

DI

Illi!II~I~llIllii
FUJITSU
1IIIi!li!l~nIIUl

MB85402-30
MB85402-40

Fig. 1 - BLOCK DIAGRAM
AO-13

cs
Ci
WE

CHIP 0

DQO

CHIP 1

DQ2
D~

DQ4
D~

CHIP 2

DQ6
D~

DQ8
DV

CHIP 3

DQI0
D~

DQ12
D~l

DQ14
D~3

Fig. 2 - BLOCK DIAGRAM for EACH MEMORY
Aa
- - - 0 Vee

;-

ROW
SELECT

----oGND

128x128x4
MEMORY CELL
ARRAY

··
·

l-

...
COLUMN
1/0 CIRCUITS

"
~

"
f-:J"

1/02

~

"

~

;0-

I
=D- pi I

::iao

i5E
WE

Y

POWER
DOWN
CIRCUIT

6-4

§
COLUMN
SELECT

INPUT
DATA
CONTROL

~~
Aa

L LL d

A7

~L

Aa Aa

fL

A,a An A'2

~-

~u

illi~~!I~i~!~lllilll

FUJITSU

MB85402-30
MB85402-40

1~lli~~~i~~m~1D

CAPACITANCE

(TA=25 D C, f=1MHz)

Parameter

Typ

Symbol

Max

Unit

Input1Capacitance (VIN=OV)

CIN

50

pF

I/O Capacitance (VIIO=OV)

CliO

15

pF

FUNCTIONAL TRUTH TABLE
ADDRESS

~DE

~

B

STANDBY

DON'T CARE

VIH

READ

VALID

VIL

VIH

OUTPUT DESABLE

VALID

VIL

WRITE

VALID

VIL

DE

POWER

I/O

DON'T CARE DON'T CARE

HIGH-Z

STANDBY

VIL

DOUT

ACTIVE

vIH

vIH

HIGH-Z

ACTIVE

VIL

DON'T CARE

DIN

ACTIVE

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter

Symbol

Supply Voltage

VCC

Supply Voltage

GND

Operating Temperature Range

TA

Value
Min
4.5

Typ

5.0

Max
5.5

25

V
V

0

0

Unit

70

DC

6-5

1I111I~lillilillll
FUJ ITSU
I~IIIII!I;!I!IIII

M885402-30
MB85402-40

DC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted)
Parameter (conditions)

Symbol

INPUT LEAKAGE CURRENT
(VIN=OV to VCC)

OUTPUT LEAKAGE CURRENT
(CS=VIH, VOUT=OV to VCC)

Min

Value
TvP

Max

Unit

ILl

-40

40

}1A

lLO

-10

10

}1A

CMOS level

ISBI

40

mA

TTL level

ISB2

80

mA

ICCI

240

mA

(IOUT=OmA, tCYCLE=Min.)

ICC2

320

mA

INPUT HIGH LEVEL

VIH

2.2

6.0

V

INPUT LOW LEVEL*l

VIL

-0.5

0.8

V

OUTPUT HIGH LEVEL (IOH=-4mA)

VOH

2.4

OUTPUT LOW LEVEL (IOL=8mA)

VOL

STANDBY POWER SUPPLY CURRENT
ACTIVE POWER SUPPLY CURRENT

(CS=VIL, IOur=OmA, VIN=OV or VCC)

OPERATING POWER SUPPLY CURRENT

V
0.4

Note: *1 -2.0V level with a maximum pulse width of 20ns.

Fig. 2 - AC TEST CONDITIONS
• Input Pulse Levels

OV to 3.0V

• Input Rise and Fall Times

5ns (Transient between 0.8V and 2.2V)

• Timing Reference Levels

1.5V (Input and Output)

• Output Load

:
+5V

.,...
Rl

R2

Load I

48012

25512

30pF

Load II

48012

25512

5pF

'>Rl

?

R2

6-6

V

~11~~lllllm~II~IIIII~~11
FUJITSU
l~il~~!~II~~~lllil~i~i

MB85402-30
MB85402-40

AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)

READ CYCLE *1

Parameter

Symbol

Read Cycle Time
Address Access Time *"
CS Access Time *3
DE Access Time *'
Output Hold from Address ChaIlJ?:e
Output Hold from CS
CS to Output Low-Z *4*'
OE to Output Low-Z *4*"
CS to Output High-Z *4*"
DE to Output High-Z *.*.
Power Up from CS
Power Down from CS

t:RC
t:AA
t:ACS
""DE
""OH
t:OHC
t:CLS
t:OLZ
""CHZ
""OHZ
t:PU
tpD

MB85402-30
Max
Min
30
30
30
13
5
3
5
0
13
13
0
25

MB85402-40
Min
Max
40
40
40
15
5
3
5
0
15
15
0
30

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

READ CYCLE TIMING DIAGRAM *1
READ CYCLE 1'2

ADDRESS

==~--=~"'; -=P~" '-~: -:~- IO~:U~:S~: D~: A~-T=~A=~v-I~: A-l_A~_I-:~_-DR~ _-E: -R:S'-C li~: -l~_ID~_-=~_-=~_-=D~-A~-T~-A~-V=-':~_:_D_:':O_:"-~O';"-:H;.;,t

_
DOUT

__

READ CYCLE IT'3

on"~,,,

~~~~~~~~~~~~~_A-_D-_D-_R-E_~_:C_V~A~l~I-D_-_-_-_-_-___-_-_-_-_.~~...;.,~-_._~______

HIGH-Z

HIGH-Z

SUPPLY
- - - -- - - --'PU3
-----CURRENT __________
50%- - - - - ICC
~

Note: *1
*2
*3
*4
*5

Undefined

WE is high for Read cycle.
Device is continuously selected, CS=VIL, OE=VIL'
Address valid prior to or coincident with CS transition low.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 2.

6-7

1I~111~!II~llill~1
FUJITSU
1~I!iilii~~I!I~~li

MB85402-30
MB85402-40

AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)

WRITE CYCLE *1
Parameter

Symbol

Write Cycle Time *"
Address Valid to End of Write
CS to End of Write
Data Valid to End of Write
Data Hold Time
Write Pulse Width
Address Setup Time
Write Recovery Time
Output High-Z from WE *a*_
Output Low-Z from WE *3*_

"WC
T.AW
T.CW
T.DW
tDH
T.WP
T.AS
T.WR
tWHZ
tWLZ

MB85402-30
Min
Max
30
25
25
13
2
25

MB85402-40
Max
Min
40
35
35
17
2
35
0

0

2

2
13
25

15
35

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE I: WE CONTROLLEO·'·2
~--------------------twc-------------------.~

ADDAESS~.~~----------------~A~D~D:A;ES;'S~V;'A~L~ID~--------------~U:~~~~
~-------------tcw'------------+--tWR

~--------------tAW-------------~
--~-----------twP------~

1,------------

----------~

1-----tow-----t--tOH
HIGH-Z

DATA VALID

HIGH-Z

DOUT
~ Undefined

Note: *1

El Don"t Care

If CS goes high simultaneously with WE high, the output remains in high
impedance state.
*2 All write cycle are determined from last address transition to the first
address transition of the next address.
*3 Transition is measured at the point of ±500mV from steady state voltage.
*4 This parameter is specified with Load II in Fig. 2.

6-8

MB85402-30
MB85402-40

AC CHARACTER I STI CS

(Continued)
(At recommended operating conditions unless otherwise noted.)

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE IT: CS CONTROLLEO·'·2

i----------twc-----------l
ADDRESS

~r---------------A-D-D-R-ES-S-V-A-l-ID--------------~Ir-j~;t-~~,~~~~~~
;0~~~~i:
~--------tAw------------~

--tAS-l.lr-------------tcw

~------------twp----------~

1~------tow------l--t...!:O:.:.:H:._j
HIGH·Z

~

Note: *1
*2

HIGH·Z

DATA VALID

Undefined

a

Don't Care

If CS goes high simultaneously with WE high, the output remains in high
impedance state.
All write cycle are determined from last address transition to the first
address transition of the next address.

\ 6-9
\

IIIIIIUIOIIU
FUJ ITSU

MB85402-30
MB85402-40

n~DI~nllDll

PACKAGE DIMENSIONS
(Suffix: CVCT)

36-LEAD CERAMIC MODULE
(Case No. : MTP-36C-col)
1.779±.OSO
(4S.18± 1.27)
.070(1.78) REF.

.4S0(11.43) REF.

I
.030±.020
(0.76±0.Sll

.300(7.62) MAX .

.090(2:29) REF.

o

rJ

oI

o
I

.018::gg~

h(0"".4""'6;-:-+~0.7.10<­

.SOO(12.70) MAX.

.010±.002
(0.2S±0.OS)
.100±.010
(2.S4±0.2S)

.OSO±.OOS
(1.27±0.13)
1. 700(43.1 S) REF.

.134±.02S
(3.40±0.64)

I
--l

I1-'(""2.~54;':;'±'i:0.""38"')
.100±.01S
-

-0.08)

.050(1.27) MAX.

Ie: ~ ~~~~~:::::~~~~~ t: :'
.080(2.03) REF.

NOTE

© 1988 FUJITSU LIMITED M36003S- 2C

6-10

1. Dimension in inches and
(millimeters).

IIIIIIIIIIIIIIIIIIIIIIIIIIIIII~~~~~~~~~~~

FUJITSU

256K

X

8 CMOS SRAM MODULE

MB85403A-40
MB85403A-50

IIIIIIIIIIIIIIIIIIIIIIIIIIIIII~~~~~~~~~~~
TS261-A88V
Nov. 1988

CMOS 262.144 Words x 8-Bit STATIC
RANDOM ACCESS MEMORY MODULE
The Fujitsu MB85403A is a fuily decoded, CMOS static
random access memory
module
consists of eight
MB81C81A devices mounted on a 44-pin ceramic board.
Organized as eight 256K x 1 devices, the MB85403 is
optimized for those applications requiring high speed,
high performance, large memory storage, and high
density.
• Organized as 262,144 x 8-bit Words
• Memory : MB81C81A, 8 pcs
• Access Time: 40 ns max (MB85403A-40)
50 ns max (MB85403A-50)
• Low Power Dissipation
Standby: 660 mW max (CMOS level)
1320 mW max (TTL level)
Active : 5280 mW max
• Single +5V Power Supply, ±10% Tolerance
• Automatic Power Down
• Dual Chip Select (x8 or x4 organization)
• TTL Compatible Input/Output Pins
• 3-State Output
• 44-Pin 100 MIL Ceramic Twin SIP (TSIP)

CERAMIC PACKAGE
MTP-44C-C02

PIN ASSIGNMENT
TOP VIEW

GND

DOUTO

ABSOLUTE MAXIMUM RATING
Rating

vee
DOOT7
DIN7

(See NOTE.)

AD

Symbol

Value

Supply Voltage

VCC

-0.5 to +7.0

V

Input Voltage

VIN

-3.5 to +7.0

V

VOUT

-0.5 to +7.0

A1

Unit

A2

Output Voltage
Short Circuit
Output Current
Power Dissipation

A3

DOOTG

V

DIm

A4

A11

A7

NC

ICSA

lOUT

±20

mA

DOOT2
DIN2

PD

Temperature
'under Bias

TBIAS

Storage
Temperature

TSTG

8.0
-10 to +85

W
DC

A14

NOTE: Permanent deVice damage may ooeur If ABSOLUTE MAXIMUM
RATINGS are exceeded. F,unctional operation should be restricted to

the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

DOOT5
DINS
GND

AG

A1D

AS

A9

DIN3

DC

/lIE
/CSB

A15

DOOT3

-65 to +150

DING

A12

vee

AB
D0IlT4

DIN4
GND

This device contains circuitry to protect the
inputs against damage due to high static volt·
ages or electric fields. However. it is advised
that normal precautions- be taken to avoid
application- of any voltage higher than maxi-

mum rated voltages to this high impedance
circuit.

6-11

1IIIil~iiil~lillil
FUJITSU

MB85403A-40
MB85403A-50

1!IIIiI~iI~in~1n

Fig; 1 - BLOCK DIAGRAM
AO-17

~
~
WE

"
~

Chip 0

Chip 4

Chip 2

-

-

.0 _0

'---

Chip 1

.0 _0

.0 _0

Chip 3

'--

(,
(,
DINl DOUTl

Chip S

'---

'----

.0 _0

DIN4 DOUT4

DIN2 DOUT2

'--

'---

-

-

DINO DOUTO

Chip 6

(,
(,
DIN3 DOUT3

DIN6 DOUT 6

'----

Chip 7

'---

0 (,
DINS DOUTS

(,
(,
DIN7 DOUT7

Fig. 2 - BLOCK DIAGRAM for EACH MEMORY
~o---l~==l
--Vee
--GNO

A3---{~==I

ROW

CELL ARRAY
(256 ROWS x 1024 COLUMNS)

COLUMN 1/0 CIRCUIT
COLUMN SELECT

6-12

DOUT

~~IIIII~~I~ii!~i~II~llli

FUJ ITSU

~~~IIIIIII!I!II~lllml~III!~!

MB85403A-40
MB85403A-50

Parameter

Typ

Symbol

Max

Unit

Input Capacitance (except CSA. CSB)

CIN

100

pF

Input Capacitance (CSA+CSB)

CCS

120

pF

Output Capacitance

COUT

20

pF

FUNCTIONAL TRUTH TABLE
MODE

ADDRESS

CSA

CSB

WE

INPUT

OUTPUT

POWER

STANDBY

DON'T CARE

VIH

VIH

DON'T CARE

HIGH-Z

HIGH-Z

STANDBY

WRITE

VALID

VIL

VIL

VIL

DIN

HIGH-Z

ACTIVE

READ

VALID

VIL

VILo

VIR

HIGH-Z

DOUT

ACTIVE

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter

Symbol

Supply Voltage

VCC

Supply Voltage

GND

Operating Temperature Range

TA

Value
Min

Typ

Max

4.5

5.0

5.5

25

V
V

0
0

Unit

70

°c

6-13

!lil~I~I~I~UI~nl
FUJ ITSU
il~!lllliI~II!il11i1

MB85403A-40
MB85403A-50

DC CHARACTERISTICS
(Recommended operating,conditions unless otherwise noted)
Parameter (conditions)

INPUT LEAKAGE CURRENT
(VIN=OV to Vcc)

OUTPUT LEAKAGE CURRENT
(CS=VIH. vour=ov to VCC)

STANDBY POWER SUPPLY CURRENT

Value

Symbol

Min

TVl>

Max

Unit

ILl

-80

80

].IA

110

-so

so

].IA

CMOS level

ISB1

120

mA

TTL level

ISB2

240

mA

ACTIVE POWER SUPPLY CURRENT

MB8S403A-40

(CS=VIL. Iour=OmA)

MB8S403A-SO

PEAK POWER ON SUPPLY CURRENT

960
mA

ICC

800
240

mA

2.2

6.0

V

VIL

-O.S

0.8

V

OUTPUT HIGH LEVEL (IOH=-4mA)

VOH

2.4

OUTPUT LOW LEVEL (IOL=16mA)

VOL

(CS=Lower of VCC. or VIR)

Ipo

Input High Level

VIH

Input Low Level *1

V
0.4

Note: *1 ,-3.0V min. for pulse width less than 20ns.

Fig. 3 - AC TEST CONDITIONS
• Input Pulse Levels

0.6V to 2.4V

• Input Rise and Fall Times

Sns

• Timing Reference Levels
• Output Load

6-14

:
RL

CL

Load I

10012

30pF

Load II

10012

SpF

V

IIIIIIIII~II~IIII~III!II~I~~!~
FUJITSU
i~~!illllllllllllll!II!IIIII~

MB85403A-40
MB85403A-50

AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)

READ CYCLE *1
Parameter

MB85403A-40
Min
Max
40
40
40
5
5
0
25
0
40

Symbol

Read Cycle Time *<
Address Access Time
CS Access Time *3
Output Hold from Address Change
CS to Output Low-Z *"*5
CS to Output HiJ!:h-Z *"*"
Power Up from CS
Power Down from CS

READ CYCLE TIMING DIAGRAM

'1:RC
'1:AA
'1:ACS
'1:0H
'1:LZ
'1:HZ
'1:PU
'1:pD

MB85403A-50
Min
Max
50
50
50
5
5
30
0
0
50

Unit
ns
ns
ns
ns
ns
ns
ns
ns

~,1

READ CYCLE I: ADDRESS CONTROLLED

I-------<.oc - - - - - - - 1
b~=<==,

.

~

VALID

DATA VALID

DOUT PREVIOUS DATA VAll

READ CYCLE II: eli CONTROLLED

1-------.0c

------;

VALID

DATA VALID

~

Note: *1
*2
*3

*4
*5

Undefined

o

.P:t

Don'tearl

WE is high during Read cycle.
Device is continuously selected. CS=VIL' _
Address valid prior to or coincident with CS transition low.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 3.

6-15

i!~lli~III~~!~!li~!1

FUJITSU

!il!~II!~il~i!~~lil

MB85403A-40
MB85403A-50

AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)

WRITE CYCLE *1
Parameter

Symbol

Write Cycle Time *<
Address Valid to End of Write
CS to End of Write
Data Valid to End of Write
Data Hold Time
Write Pulse Width

~WC

~AW
~CW

~DW

~DH

l:WP
~ASl

Address Setup Time

~AS2

Write Recovery Time
Output High-Z from WE *,*Output Low-Z from WE *'*.

~WR

l:WZ
~OZ

MB85403A-40
Min
Max
40
35
35
25
0
25
5
0
5
0
25
0

MB85403A-50
Max
Min
50
45
45
30
0
30
5
0
5
0
30
0

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE: WE CONTROLLED

VALID

DOUT

~

Note: *1

Undefined

(f!iI

Don't car.

If CS goes high simultaneously with WE high, the output remains in high
impedance state.
*2 All write cycle are determined from last address transition to the first
address transition of the next address.
*3 Transition is measured at the point of ±500mV from steady state voltage.
*4 This parameter is specified with Load II in Fig. 3.

6-16

II~i!ili!!II!I~!1I
FUJ ITSU
i~I~I!li!i~ililin

MB85403A-40
MB85403A-50

AC CHARACTER I STI CS

(Continued)
(At recommended operating conditions unless otherwis.e noted.)

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE: CS CONTROLLED

VALID

ADDR

VALID

HIGH-Z
DOUT - - -

~

Note: *1
*2

Undefined

~ Don'tea..

CS

or WE must be high during address transitions.
All write cycle are determined from last address transition to the first
address transition of the next address.

6-17

10111160011
FUJITSU

!mIlllHOnRII

MB85403A-40
MB85403A-50

PACKAGE
(Suffix: C~~~fNSIONS
44-LEAD CERAMIC D
(Case No'
UAL IN-LINE
•• MTP-44C-C02)

1!~1r>'\.>1.\\1."'''~~

MODULE

,269.85%1.27)
7s6~.Q'iQ

3QO(]. 62ltlAX.
~~.L-

I

NOTE
I. Dimension I n .nches
.
and (m! (I'Imeters)~

6-18

'

cO

October 1989
Edition 1.0

FUJITSU

DATA SHEET

MB85410-301-40
64K X 8 CMOS SRAM MODULE
CMOS 65,536 WORDS x S-BIT HIGH SPEED STATIC
RANDOM ACCESS MEMORY MODULE
The Fujitsu MB85410 is a fully decoded, CMOS static random access memory module
consists of eight MB81C71A devices mounted on a 6O-i>in plastic board.
Organized as eight64K x 1 devices, the MB85410 is optimized for those applications
requiring high speed, high performance, large memory storage, and high density.
•

Organized as 65,536 x 8-bit Words

•

Memory: MB81C71A, S pes

•

Access Time: 30 ns max (MB85410-30)
40 ns max (MB85410-40)

•

Low Power Dissipation
Standby: 440 mW max (CMOS level)
880 mW max (TIL level)
Active : 3200 mW max

•

Single +5V Power Supply, ±10% Tolerance

•

Automatic Power Down

•

Dual Chip Select (xS or x4 organization)

•

TIL Compatible Input/Output Pins

•

~tate Output

•

Decoupling Capacitor: .22J.1F, Spes

•

6(}..Pin Plastic(FR-4) ZIP

PLASTIC PACKAGE
MZP-60P-P02

PIN ASSIGNMENT
TOP VIEW

co
AO

A2

A4
AS

vss

ABSOLUTE MAXIMUM RATINGS (see NOTE.)
Rating
Supply Voltage

Symbol
Vee

Value

Unit

-{l.5 to +7.0

V

Input Voltage

V IN

-3.5 to +7.0

V

Ouput Voltage

V OUIT

-{l.5 to +7.0

V

Output Current

lOUT

±SO

Power Dissipation

Po

S.O

mA
W

Storage Temperature
NOTE:

T BIAS

-10 to +85

°C

T STG

-45 to +125

°C

Permanent device damage may occur if the above Absolute Maximum
Ratln\ls are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability .

NC

10
12
14
18
18

D2

20
22

Q2

24

WE

28

NC
081

30

NC
NC
vee

28

D4

32
34
38
38

Q4

40

A8
Al0
A12
A14
NC

42
44
48

NC
NC

48
50
52
54
58
58

vss

80

DB

as
Temperature under Bias

vss
POl (OPEN)

PDO (GNO)
NC
vee
DO

•11
13
15
17

01
al
NC
Al
A5
A7

21

00

23

29

a3
vee
NC
NC

31

~2

25
27

33

35

NC
NC

37

os

39

as
vss
A9
All
A13
A15

41
43

45
47
49
51

D7

53
55

a7
vee

57

NC
NC

59

OIl

AS

,.

This device oontains ciI'OJltry to protect the inputs against
damage due to high static voltages Of eklctric fields. H0'W8V9r. It
is advised that normal precautloos be taken to avoid application
of any voltage higher than maximum rated vohages to this high
ifTl)8dance drcull:.

6-19

MB8541D-30
MB8541 0-40
Fig. 1 - BLOCK DIAGRAM

-...
-

I- ADD .

.... ADD.

-- CS

Chip 0

-,... CS

6 6

'-I-

6 6

DIN2 DOlJT2

DINO DOllTO

-- ADD.

-- ADD.

Chip 1

CS
WE

6 6

'-,... CS

Chip 6

CS
WE

WE

6 6

6 6

DIN4 D0UT4

DINe D0UT8

-- ADD.

Chip 3
"--

I- ADD .

Chip 4

WE

WE

-

.... ADD.

Chip 2

_ChipS
" - - CS

CS
WE

-- ADD.
Chip 7
i...--

WE

6 6

6 6

CS

WE

6 6

Fig. 2 - BLOCK DIAGRAM FOR EACH MEMORY

Ao

_Veo

Al

-GND

A2 ------t~==~ ROW·
Ag

SELECT.

AI2~§
A 13

----l

AI4------t~==~

6-20

•

ARRAY

CELL
(128 ROWS x 512 COLUMNS)

MB8541 0-30
MB8541D-40

CAPACITANCE
(1A = 25° C, f= 1MHz)
Perameter

Symbol

Typ

Max

Unit

Input Capacitance, Address and WE

C IN ,

80

pF

Input Capacitance, CS, and CS2

C IN2

40

pF

Input Capacitance, 0 IN

CII3

10

pF

Output Capacitance, 0 OUT

COOT

10

pF

Output

Power

FUNCTIONAL TRUTH TABLE
Mode

Add .....

a,

a.

WE

Input

Stanclly

Don't Care

V IH

V IH

Don't Care

High-Z

High -Z

Stanclly

Write

Valid

V IL

V IL

VII.

DIN

High-Z

Active

Read

Valid

V IL

V IL

VH

High-Z

DOUT

Active

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Value
Parameter

Unit

Symbol

SUpply Voltage

Vee

SUpply Voltage

GND

Operating TemperabJre Range

TA

Min

Typ

4.5

5.0

Max

5.5

0
0

25

V
V

70

"C

6-21

MB8541D-30
MB8541D-40

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Valuaa
Paramaler (conditione)

Symbol

Unh

Min

Typ

Max

Input Laakage Current (V IN = OV to V cc )

III

-80

80

I'-'

Output Leakage Current (CS = V IH ,VOIIT= OV to Vcc)

I LO

-10

10

I'-'

CMOS level

ISSl

80

rnA

TIL level

I_

160

rnA

Icc

640

rnA

IPO

240

rnA

Standby Power Supply Current

Active Power Suppry Current (CS = VIL ' lOUT = OmA)

Peak Power on Supply Current (CS = Lower of Vcc , or VIH

)

Input High Level

V IH

2.2

6.0

V

Input Low Level' 1

V IL

~.5

0.8

V

Output High Level (l0H = - 4mA)

VOH

2.4

Output Low Level (IOL= 16mA)

VOL

V
0.4

Nole : • 1 - 2.0V min. lor pulse width less than 2Ons.

Fig. 3 - AC TEST CONDITIONS
• Input Pulse lewis
• Input Rise and Fall Times
• Timing Reference Lewis
• Output Load:

: 0.6V to 2.4V
: 5ns(Trensieni between 0.8V and 2.2V)
: 1.5V (Input and Output)

.z~V

~

4800
CL

Dour(Q)

(Including Scopo and
JIg~IIanco)

6-22

i'C

;..
,,~

255n

Loadl

30pF

Loadn

5pF

V

MB8541D-30
MB8541 0-40

AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)

READ CYCLE
P.ram.....

Symbol

Read Cycle Tome " 1
Address Access Tome
CS Access Time" 2
Output Hold from Address Change

lAC
1M

CS to Oulput Low-Z "3" 4

ILZ
1 Hz

CS to Oulpul High-Z

MB8S41~0

Min
30

"3" 4

Power Up from OS
Power Down !rom CS

I PU
Ipo

MB8S4111-40
Min
Max
40

30

lACS
IOH

Max

40
40

30

5
5
0

5
5
0

10

15

0

0
20

30

Unh
ns
ns
ns
ns
ns
ns
ns
ns

READ CYCLE TIMING DIAGRAM
READ CYCLE: ADDRESS CONTROLLED

ADDRESS

DATA VALID

DATA OUT

READ CYCLE: CS CONTROLLED
----~

~------------I~------------~

~--------

HIGH-Z

DATA OUT

_____tP::c
____

tP~
Icc

----------

ISB

--------

50%

.1

"":

~

Undaflned

Don'tea,.

Note: "1 Device is conlinuously selectlld, CS - VII.'
" 2 Address valid prior to or coincident with CS transition low.
"3 Transition is measured allha point 01 ± 500mV from slBedy stale voltage.
"4 This parameter is specified wilh Load n in Fig. 3.

6-23

MB8541 ()..30
MB8541 0-40

AC CHARACTERISTICS (Continued)
(At recommended operating conditions unless otherwise noted.)

WRITE CYCLE'1
Parameter

Symbol

Write Cycle lime • 2

lwe

Address Valid \0 End of Wrile

lAW
lew
IDH
Iwp

~ \0 End of Wrile
Data Hold lime

Write Pulse Width
Data Valid \0 End of Write

Outout Hiah--Z from WE ' 3' 4
Outpul Low-Z from WE ' 3' 4

Unll
ns
ns

35
35
2
30
20
0

t WR
twz

0
0
2
0

n.
ns
ns

0
2
0

ns
ns

low

0

tow
I AS2

Write Recovey Time

MB8541!1-4O
Min
Max
40

25
25
2
20
15

tAS1

Address Setup lime

MB85410-30
Min
Max
30

10

ns
ns

ns

15

ns

0

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE: WE CONTROLLED
~--------------------twe--------------------~~

ADDRESS

~------------------tAW------------------~--

DATA IN

-.~

HIGH-Z--!

I/o.--rlt++--{>--!

6-28

I- ADD.

128 k 128 II; 4
MEMORV CELL
ARRAY

---oGND

!1~III~i~~I~I~~!~1

FUJ ITSU

MB85414-30
MB85414-40

i~~~~~~~~!I~i~l~n~

Parameter

Symbol

Typ

Max

Unit

Input Capacitance, ADDRESS

CINI

80

pF

Input Capacitance, CS

CIN2

30

pF

Input Capacitance, WE and OE

CIN3

80

pF

Input Capacitance, 1/0

CliO

12

pF

FUNCTIONAL TRUTH TABLE
MODE

ADDRESS

CS

WE

liE

POWER

I/O

STANDBY

X

VIH

X

X

HIGH-Z

STANDBY

OUTPUT DISABLE

VALID

VIL

VIH

VIH

HIGH-Z

ACTIVE

WRITE

VALID

VIL

VIL

X

HIGH-Z

ACTIVE

READ

VALID

VIL

VIH

VIL

DOUT

ACTIVE

X can be either VIH or VIL'

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter

Symbol

Supply Voltage

VCC

Supply Voltage

GND

Operating Temperature Range

TA

Value
Min
4.5

Typ

5.0

Max
5.5

25

V
V

0
0

Unit

70

°c

6-29

IIli!iI~Ulililil
FUJITSU

IIIU~~m!lnlln

MB85414-30
MB85414-40

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Parameter (conditions)

Value

Symbol

INPUT LEAKAGE CURRENT
(VIN=OV to VCC)

OUTPUT LEAKAGE CURRENT
(CS=VIH, Vour=OV to VCC)

Min

TvP

Max

Unit

ILl

-BO

BO

].lA

110

-10

10

pA

CMOS level

ISB1

BO

mA

TIL level

ISB2

160

mA

ICC1

4BO

mA

(Cycle=Min., IOur=0mA)

ICC2

640

mA

Input High Level

VIH

2.2

6.0

V

Input Low Level *1

VIL

-0.5

O.B

V

OUTPUT HIGH LEVEL (IOH=-4mA)

VOH

2.4

OUTPUT LOW LEVEL (IOL=BmA)

VOL

STANDBY POWER SUPPLY CURRENT
ACTIVE POWER SUPPLY CURRENT
(CS=VIL, IOur=OmA)

OPERATING SUPPLY CURRENT

V
0.4

Note: *1 -2.0V min. for pulse width less.than 20ns.

Fig. 3 - AC TEST CONDITIONS
• Input Pulse Levels
• Input Rise and Fall Times
• Timing Reference Levels
• Output Load

OV to 3V
Sns (Transient between O.BV and 2.2V)
1.SV (Input and Output)

:
4BOQ

Dour{Q) 0---.,----+
2SSQ

(Including Scope and
Jig Capacitance)

6-30

CL
Load I

30pF

Load II

SpF

V

1~111~~II~IIIIII~IIII!li~!~
FUJITSU
i!~~~i~~~~~I!~~~I~i!

MB85414-30
MB85414-40

AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)

READ CYCLE
Parameter

Symbol

Read Cycle Time
Address Access Time
CS Access Time *2
OE Access Time *2
Output Hold from Address ChanQe
Output Hold from Output Disable
CS to Output Low Z *3*4
OE to Output Low-Z *3*4
CS to Output High-Z *3*4
OE to Output HiQh Z *,*4
Power Up from CS
Power Down from CS
*1

"RC
ToAA
LACS
"LOE
ToOH
tOHC
LCLZ
"LOLZ
ToCHZ
1.0HZ
"LPU
TopD

MB85414-30
Mln
Max
30
30
30
15
5
3
5
0
10
10
0
20

MB85414-40
Mln
Max
40
40
40
20
5
3
5
0
15
15
0
30

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

READ CYCLE TIMING DIAGRAM
READ CYCLE I

: : '~'~'"i~'~:~-~ IO~-U~-S~-D~-A-T~-A~-v-t-:-A-:~-I:~-D~-R=-E-:_:-'-i~ ,'=-L=-ID=- ~=- ~=- ~D=-A=-T-A~ -~:~-:-~-':-to_":t
O-'
READ CYCLE II

ADDRESS ____~.~~-:---------:-:-:-:-:A:D:D:R::-:-~:A:L:ID::::::::::o-i)k_._______________

DOUT

HIGH·Z

SUPPLY
- - - - - - - tpU3
----------------CURRENT ________________
50%
ICC
18:81 Undefined
Note: *1
*2
*3
*4

o

Don't Car.

Device is continuously selected, CS=VIL. __
Address valid prior to or coincident with CS transition low.
Transition is measured at the point of ±500mV from steady state voltage.
This parameter is specified with Load II in Fig. 3.

6-31

Ullil~!II~iil~~ii

FUJITSU

IiliUl~!il!I~Uil

MB85414-3D
MB85414-4D

AC CHARACTERISTICS
(At recommended

WRITE CYCLE *1

oper~ting

conditions unless otherwise noted.)

Parameter

Symbol

Write Cycle Time *2
Address Valid to End of Write
CS to End of Write
Data Hold Time
Write Pulse Width
Data Valid to End of Write
Address Setup Time
Write Recovery Time
Output Hb:h-Z from WE *,*q
Output Low-Z from WE *,*q

"tWC
tAW
"tCW
tDH
"tWP
"tDW
tAS

"WR
"WHZ
"tWLZ

MB85414-40
Min
Max
40
35
35
2
30
20
0
2
15
30
0

MB85414-30
Max
Min
30
25
25
2
20
15
0
2
10
0
20

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE I: WE CONTROLLED
~--

__--------------___ twc--------------------"

ADDRESS~~~________________A_D_D_R_E_SS__V_A_LI_D________________-JI':~~~':~'~~l,~~~t~~~~'~:,

1----------t Cw'---------1--t wR~----------------_tAW----------------~

~~As--~~-----------twp------------l,---------------

,

HIGH-Z

~

xxXXXX

~ Undefined

Note: *1

HIGH-Z

DATA VALID

HIGH-Z

H1f!'l!il

!--twLz1

~~..,..x>r'7t'"

Don't Care

If CS goes high simultaneously with WE high, the output remains in high
impedance state.
*2 All write cycle are determined from last address transition to the first
address transition of the next address.
*3 Transition is measured at the point of ±500mV from steady state voltage.
*4 This parameter is specified with Load II in Fig. 3.

6-32

!11~~~IIII~!~~~lli~iill
FUJ ITSU

111~~~i~~~i~~~i~iii

MB85414-30
MB85414-40

AC CHARACTERISTICS

(Continued)
(At recommended operating conditions unless otherwise noted.)

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE IT: CS CONTROLLED
twc

ADDRESS

.
11M

ADDRESS VALID

..

tAW

tWR
tcw

--tAS

\-

K.

-

twp

. -.. ~:::\
~~

"~

:.:.::

tOH

tow

HIGH-Z

DATA VALID

~

Undefined

HIGH-Z

I~ I Don't Care

6-33

ImUllilllil~11I
FUJ ITSU

I!IIIIIIIIIIIIU!

MB85414-30
MB85414-40

PACKAGE DIMENSIONS
(Suffix: PJPZ)

64-LEAD PLASTIC MODULE
(Case No. : MZP-64P-POI)

INDEX

C .050

.271 REF.

_.350(8.89} MAX.

MAX .

. 134+.016
-0.361
.010+.004
-.002
(0.25+0.10
-0.05)
.100±.012
(2.54±0.30)

NOTES
1. Dimension in inches and
(millimeters).

© 1989 FUJITSU LIMITED M64DD6S - 3C

6-34

2. Pin No.1: Back side.

cO

November 1989
Edition 1.0

FUJITSU

DATA SHEET

MB85420-401-50
256K X 8 CMOS SRAM MODULE
CMOS 262,144 WORDS X 8-BIT HIGH SPEED STATIC
RANDOM ACCESS MEMORY MODULE
The Fujitsu MB85420 is a fully decoded, CMOS static random access memory module
consists of eight MB81C81A devices mounted on a 6O-ilin plastic board.
Organizad as eight 256K x 1 devices, the MB85420 is optimizad for those applications
requiring high spead, high performance, large memory storage, and high density.
•

Organizad as 262,144 x &-bit Words

•

Memory: MB81C81A, 8 pes

•

Access TIme: 40 ns max (MB85420-40)
50 ns max (MB85420-50)

•

Low Power Dissipation
Standby: 660 mW max (CMOS level)
1320 mW max (TTL level)
Active : 5280 mW max (MB85240-40)
4400 mW max (MB85420-50)

•

Single +5V Power Suppry, ±10% Tolerance

•

Automatic Power Down

•

PLASTIC PACKAGE
MZP~P-P02

PIN ASSIGNMENT
TOP VIEW

DO

• TTL Compatible InpuVOutput Pins

co

• 3-State Output

A9
AI.
A12

•

.22~F, Spes

A17

VSS

OO-Pin Plastic(FR-4) ZIP

D2

• Upgrade version of MB85410

Symbol

Value

Unit

Vee;

-C.5to +7.0

V

Input Voltage

V ,N

-3.5 to +7.0

V

Output Voltage

-C.5to +7.0

V

24

NC

D4

32
34
36
38

Q4

40

AD

42
44
46
48
50
52

NC

AS

A2

Output Current

lOUT

±2O

mA

A7

NC

Power Dissipation
Temperature under Bias
Storage Temperature
NOTE:

Po

8.0

W

T BIAS

-10 to +85

°C

T STO

-45 to +125

°C

Permanent device damage may occur if the above Abaolute Maximum
Ratln!;!. are exceadad. Functional operation should be restrictad to the
condillOns as detailad in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extendad periods may affect device
reliability.

18
20
22
26
26
30

vee;

Vour

,.

D2

CSI

Supply Voltage

10
12
I.

WE
A4

ABSOLUTE MAXIMUM RATINGS (see NOTE.)
Rating

POI (GNO)
NC
01
al

vee;

Dual Chip Select (x8 or x4 organization)

• Decoupling Capacitor:

vss

PDO(OPEN)
NC

D6

as

54

NC
NC

56

VSS

80

59

11
13
15
17
19
21
23
25
27
29

NC

1m

AID
Al1
A13
AI.
D3
a3

vee;
A15
NC

31
33
35
37

~
NC
NC

39
41
43
45
47
49
51
53
55
57
59

a5

os

vss
AI
A5

A3
AS
07
Q7

vee;
NC
NC

This device contains cirruitry to protect the Inputs against
damage due to high static YOlag8& or electric fields. However, it
II advised that normal precautions be taken to avoid application
of any voltage higher than rnax:imum rated ~agas

to this high

lf11)8dance circuit.

6-35

MB85420-40
MB85420-50
Fig. 1 -

BLOCK DIAGRAM

.....

.- ADD.
' - I-

Cs
WE

L....

--

--

Chip 2

Cs
WE

Chip 4
WE

WE

6 6

6 6

DIN2 DouT2

D'N< DouT•

-

Cs

Chip 3
~

WE

Cs
WE

6 6

DINI Doull

-

ADD.

6 6

-

Chip 6

..... r- Cs

6 6
ADD.

I- ADD.

Cs

DINO DouTO

Chip 1
'---

I- ADD .

.... ADD.

Chip 0

ADD.
Chip 5

6 6

D'N6 DOUT6

L....

ADD.
_Chip 7

Cs

' - - - CS

WE

WE

6 6

6 6

Fig. 2 - BLOCK DIAGRAM FOR EACH MEMORY

ImI

Ao
A,

-Vee

A2

-GND

A3

------"t~==:::1

ROW

A. _ _ _ _ _ _""t~===lSELECT
A5
A6
A7

D'N

WE

OS

6-36

CELL ARRAY
(256 ROWS xl024 COLUMNS)

MB85420-40
MB85420-50

CAPACITANCE
Paramet.,

Max

Unit

C IN ,

70

pF

C IN2

45

pF

Input Capacitance, D IN

C IN3

9

pF

Outout Capacitance, D OUT

COUT

12

pF

Output

Power

Input Capacitance, Address and
Input Capacitance,

05,

Symbol

WE

and CS 2

Typ

FUNCTIONAL TRUTH TABLE
Mode

Addr..a

cs.

CS.

'WE

Input

Standby

Don't Care

V IH

V IH

Don't Care

High-Z

High-Z

Standby

Write

Valid

V il

V il

V il

DIN

High-Z

Active

Read

Valid

V il

V il

V IH

High-Z

DOUT

Active

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Value
Parameter

Unit

Symbol

Supply Voltage

Vex;

Supply Voltage

GND

Operating TemperalUre Range

TA

Min

Typ

4.5

5.0

Max

5.5

0
0

25

V
V

70

"C

6-37

MB85420-40
MB85420-50

DC CHARACTERISTICS
(Recommended operating condltlpns unless othelWlse noted)
Values
Parameter. (Conditions)

Symbol

Unit
Min

Typ

Max

Input Leakage Current (V IN = OV to Vee)

III

-ao

80

j.iA

Output Leakage Current (CS = V IH ,Vour= OV to Vee)

ILO

--50

50

j.iA

CMOS level

I SB'

120

rnA

TIL level

I SB2

240

mA

960

rnA

800

mA

240

rnA

Standby Power Supply Current

~ve Power SupplY Current

(CS = VIL , I our= OmA)

MB85420-40
lee
MB85420--50

Peak Power on Supply Current (Cs = Lower of Vee, or VIH )

IPO

Input High Level

V IH

2.2

S.O

V

Input High Level' ,

V 1L

~.5

0.8

V

Output High Level (ICH = - 4mA)

VCH

2.4

Output Low Level (I OL= lSmA)

VOL

V
0.4

Note: • , - 3.0V min. for pulse width less than 2Ons.

Fig. 3 - AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
o Timing Reference Levels
o Output Load:
o
o

6-38

: O.SV to 2.4V
: 5ns
: VIL!VOL = 0.8V, V IHNOH = 2.2V

RL

CL

Load I

lOon

30pF

LoadTI

loon

5pF

V

MB85420-40
MB85420-50

AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)

READ CYCLE
Symbol

Paramater

Address Access TIme

I RC
1M

CS Access Time' 2
OUlpul Hold from Address Change

100

Read Cycle TIme' 1

MB85420-40
Min
Max

40
40

CS to Oulpul Low-Z • 3 • 4

ILZ
1 HZ

Power Up from CS

I PU
I PD

Power Down from CS

50

40

lACS

~ to Oulpul High-Z • 3' 4

M B8542(h';O
Min
Max
50

5
5
0

5
5
0

20
40

ns
ns

50

ns
ns

25

ns

50

ns
ns

ns

0

0

Unit

READ CYCLE TIMING DIAGRAM
READ CYCLE I: ADDRESS CONTROLLED

ADDRESS

DATA VALID

READ CYCLE n: CS CONTROLLED
(4-------
 R C - - - - - - - i

ADDRESS

VALID

HIGH-Z

HIGH-Z

:: -------.:'::~-------------IP-:-C
~

CS

Undefined

Ittl

Don'l Care

Note: • 1 Device is conlinuosly selected,
= V1L .
• 2 Address valid prior to or coincidenl with

CS Iransilion low.

Transilion is measured allhe poinl of ± 500mV from steady state voltage.
• 4 This parameter is specified with Load n in Fig. 3.

•3

6-39

MB8542D-40
MB85420-50

AC CHARACTERISTICS (Continued)
(At recommended operating conditions unless otherwise noted,)

WRITE CYCLE "1
MB8S420-40
Min
Max

Symbol

Parameter

MB8S420-00
Min
Max

Unh

Write Cycle lime '2

twe

40

50

Address Valid to End of Write

tAW

35

45

'l5§ to End of Write

tew

35

45

Data Valid to End of Write

tow

20

25

ns
ns

Data Hold lime

tOH
twp

0

0

ns

30

35

ns

tAS1

5

5

ns

0
5

0

ns

Write Recovery lime

1AS2
I WR

5

ns

Outoul Hiah-Z from WE '3"

Iwz

0

OutPUt Low-Z from WE '3"

tow

0

Write Pulse Width
Address Setup lime

ns
ns

25

0

20

ns
ns

0

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE: WE CONTROLLED

ADDRESS

VALID

~--------------tew------------~*

~-----------------tAW----------------~

~

Undefined

IMdEl

Note: '1 Ifll§ goes high simultaneously with WE high. the outpul remains in high impedance state.
'2 All write cycIa are determined from last address transition to the first address transition of the next address.
'3 Transition is measured at the paint of ± SOOmv from steady state voltage.
'. This paramater is spec:ified with Loed n in Fig. 3.

6-40

Oan', Care

MB85420-40
MB85420-50

AC CHARACTERISTICS (Continued)
(At recommended operating conditions unless otherwise noted.)

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE: CS CONTROLLED

~----

ADDRESS

___________

t~

________________

~

VALID

1-"----------- tAw------------tr-l

DIN

o OUT

HIGH-Z
---_

~

Undellned

IIIi;1

Don't Care

6-41

MB8542D-40
MB85420-50

PACKAGE DIMENSIONS
(Suffix: -PJPZ)
50-LEAD PLASTIC MODULE
(Case No. : MZP-60P-P02)

If

,.OO".'"~
l l_ _-'1,,---,..........."lffiII'""_ _i!':'IIr__""l!'!I..._ _'"!'!'r+__
3_50,(S.S9) MAX. 11111

INDEX

.0IS+.007
-.003
(0.45+0.'-8.050+ .012 - O.OS)

.050±.Q10
(1.27±0.25)

-H-I--(""1.-';2""7+g~~

.loo±.OIO
(2.54±0.25)
1.450(36.S3) REF.
. 150±.020
(3.S1 ±0.50)

-0.25)
.250(6.35) REF.

3.150(SO.01) REF ..

.134+.016
-.014
(3.40+0.41
-0.36)
.010+.004
-.002
(0.25+0.10
--0.05)
.100±.012
(2.54±0.30)

NOTES

© 1989 FUJITSU LIMITED M60006S-3C

6-42

1. Dimension in inches and
(millimeters).
2. Pin No.1; Back side

Section 7

Quality and Reliability -

I

At a Glance

P...e

7-3
7-4

Quality Control at Fujitsu
Quality Control Processes at Fujitsu

III

7-1

Quaory and ReliabHiry

1-2

Static RAM Data Book

Static RAM Data Book

Quality and Reliability

Quality Control at Fujitsu

Bullt·ln Quality and Reliability

Fujitsu's integrated circuits work. The reason they work is
Fujitsu's single-minded approach to buiit-in quality and reliability,
and its dedication to providing components and systems that
meet exacting requirements allowing no room for failu're.
Fujitsu's philosophy is to build quality and reliability into every
step of the manufacturing process. Each design and process is
scrutinized by Individuals and teams of professionals dedicated
to perfection.
The quest for perfection does not end when the product leaves
the Fujitsu factory. it extends to the customer's factory as well,
where integrated circuits are subsystems of the customer's final
product. Fujitsu emphasizes meticulous interaction between the
individuals who design, manufacture, evaluate, sell, and use its
products.
Quality control for all Fujitsu products is an integrated process
that crosses all lines of the manufacturing cycle. The quality
control process begins with Inspection of all incoming raw
materials and ends with shipping and reliability tests following
final test of the finished product. Prior to warehousing, Fujitsu
products have been subjected to the scrutiny of man, machine,
and technology, and are ready to serve the customer in the
deSignated application.

7-3

Static RAM Data Book

Quality and ReHabiHty

Quality Control Processes at Fujitsu

P~

Inspection of Incoming Malarial
Chackftema
Wafer Processing
Inspection of Wafers,
Masks, Packages, Piece
DiffusiorVIon Implanlation
Parts, Chemicals, Etc
Wafer Surface Inspection and
Photoatching
Sample Tests of Thickness,
Surface Resislance, Diffusion
Depth, Electrical Parameters, and Doping
Wafer Surface and Pallem Inspection
Passivation (Insulating Layer Formation)
Wafer Surface Inspection,
Monitor Test of Film Thickness
Probing Test
Wafer Surface Inspection,
Monitor Test of Film Thickness
Wafer Shipping Inspection
Test of Electrical Characteristics, Stress Test
Dicing (CHIP Separation)
CHIP Salection
CHIP Shipping Inspection

Sample Surface Inspection
Bond-Welling and Surface Inspection, Monitor Test of lot un
for Machine Calibration
Bond-Position and Surface Inspection,
Sample Wire Bond Strength Test,
Monitor Test of Sample run for Machine Calibration
Intamal Visual Inspection

Pre-Cap Visual
Inspection

Continued on next page

7-4

Internal Merchant
Inspection

Static RAM Data Book

Quality and Reliability

Quality Control Processes at Fujitsu (Continued)

Sealing or Molding
Aging (After Encapsulation)
Leak Test (Hennetic Package Only)
Fine and Gross leak Tests
External Sampling Visual Inspection
External Sampling Visual Inspection
External Sampling Visual Inspection

External Visual Inspection

External Mechanical Inspection

External Sampling Visual Inspection

Shipping Tests

Test of ACiDC Characteristics and Functions
Hermeticity (Fine and Gross leak Tests). External and Marking Inspection~
Electrical Characteristics Tests. All Sampling Tests

U

Endurance and Environmental Tests

0

Reliability Tests
lot Tests/Periodic Tests
Warehousing

legend:

o

o

c

<>

Production Process
Test/Inspection
Production Process
and Test/Inspection
QC Gate (Sampling)

Note:
The flow sequence may vary slightiy
with indillidual product type.

7-5

III

Quality and ReHabiHty

IDI

7-6

Static RAM Data Book

Section 8
Ordering Information - At a Glance

I

Page
Ih'3
Ih'3
Ih'3
8-t
8-t
~

~

IC Product Marking
IC Ordering Code (Part Number)
IC PllCkage Codes
IC Module Ordering Code (Part Number)
IC Module Package Codes
Wide Temperature IC Ordering Code (Part Number)
Wide Temperature IC Package Codes

8-1

Ordering Information

8-2

Static RAM Data 8oo/c

Ordering Information

Slaffc RAM Dara Book

IC Product Marking

Fujitsu Logo

Z Z - year
Nole:

week number
XX Marking formats may vary, depending on the product. The country of origin eppears on all finished perts.

IC Ordering Code (Part Number)

IL
T
1
MB

XXXXX -1

P

Package Code (See Package Codes below)

Speed Designator (When applicable)

Device Type

Manufacturer Designator
MB
MBM
Nole:

Identifies an IC designed and manufactured by Fuj~su that uSeS a Fuj~su-designated device number.
identifies an IC designed and manufactured by Fujitsu that uSeS a device number designated by the industry
to be the industry standard number.
Please conract your nearest Fujitsu sales office, repRIsentetive, or distributor for exact part number/order information.

IC Package Codes

i·····.

..

·····q~~rhlc··.i

it

Package Type

Package Code

...............

1$

••••••••

Package Type

Package Code

LCC (Leadless Chip Carrier)

TV,CV

LCC (Leadless Chip Carrier)

PV

PGA (Pin Grid Array)

CR

PLCC (Leaded Chip Carrier)

PO

DIP (Side Brazed)1

C

PGA (Pin Grid Array)

PR

DIP (CERDIP)2

Z

DIP (Dual In-line Package)

P,M

Shrink DIP

CSH

Shrink DIP

PSH

Flatpack, Meral Seal

CF

Flatpack

PF

Flatpack, Glass Seal

ZF

Single In-line, straight leads

PS

SOJ (Single Outline Junction)

CJ

Single in-line, zig-zag leads

PSZ,PZ

SOJ (Single Outline Junction)

PJ

2

Side Brazed

,I

~

~

CERDIP

f

~I
8-3

Static RAM Data Book

OrderIng Information

IC Module Ordering Code (Part Number)

II..
T
1
MB

XXXXX -YY pp
Module Code (See Module Codes below)

Speed Designator (When applicable)

Device Type

Manufacturer Designator
MB
MBM
Note:

Identifies an IC designed and manufactured by Fuj~su that uses a Fuj~u-designated device number.
Identifies an IC designed and manufactured by Fuj~u that uses a device number designated by the industry
Ie be the industry standard number.
Please contact your neBrllst Fujitsu sales office, representative, or distribu1Dr for exact part number/order information.

IC Module Package Codes

8-4

Ordering Information

Static RAM Data Book

Wide Temperature Range IC Ordering Codes (Part Number)
MB

XXXXX -yy W SC

ll lB83C_~
Temperature Range Designator·

Speed Designator (When applicable)
Device Type
Manufacturer Designator
MB
·W

Identifies an Ie designed and manufactured by Fuj~su that uses a Fuj~su"designated device number.
Indicates wide temperature range; S98 product specifications for exact temperature information.

Note:

Please contact your Fujitsu sales office for exaC! pan number/order information.

Wide Temperature Range IC Package

8-5

Ordering Information

8-6

Staffa RAM Data Book

Section 9
Sales Information -

I

At a Glance

Page
~

9-7
9-8
9-9
9-11
9-11
9-11
9-12
9-16
9-17
9-18
9-20
9-21
9-22

Introduction to Fujitsu
Integrated Circuits Corporate Headquarters - Worldwide
FMI Sales Offices lor North and South America
FMI Representatives - USA
FMI Representatives - Canada
FMI Representatives-Mexico
FMI Representatives - Puerto Rico
FMI Distributors - USA
FMI Distributors - Canada
FMG Sales Offices lor Europe
FMG Distributors-Europe
FMA Sales Offices for Asia and Australia
FMA Representatives - Asia and Australia
FMA Distributors - Asia and Australia

9-1

Sales Informtltion

9-2

Sta6c RAM Data 800k

Static RAM Data Book

Sal6S Information

Introduction to Fujitsu

Fujitsu Limited
Fujitsu Limited, headquartered near Tokyo, Japan, is the largest
supplier of co""uters in Japan and is among the top ten
companies operating in Japan. Fujitsu Is also one of the world's
largest suppliers of telecommunications equipment and
semiconductor devices.
Established in 1935 as the Communications Division spinoff of
Fuji Electric Company Limited, Fujitsu Limited, in 1985,
celebrated 50 years of service to the world through the development and manufacture of state-of-the-art products in data
processing, telecommunications and semiconductors.
Fujitsu has five plants in key industrial regions in Japan covering
all steps of semiconductor production. Five wholly-owned
Japanese subsidiaries provide additional capacity for production
of advanced semiconductor devices. Two additional facilities
operate in the U.S. and one in Europe to help meet the growing
worldwide demand for Fujitsu semiconductor products.

9-3

Static RAM Data Book

Sa/ss Information

Introduction to Fujitsu (Continued)
Fujitsu Microelectronics, Inc.

Fujitsu Microelectronics, Inc. (FMI), with headquarters in San
Jose, California, was established in 1979 as a wholly-owned
Fujitsu Limited subsidiary for the marketing, sales, and distribution of Fujitsu integrated cirooit and component products. Since
1979, FMI has grown to include one research and development
division, two marketing divisions, two manufacturing divisions
and a subsidiary. FMI offers a complete array of semiconductor
products for its QJstomers.
The Advanced Products Division (APD) is responsible for the
complete product development cycle, from design through
operations support and worldwide marketing and sales. Products
are the result of both internal development and external
relationships, such as joint development agreements, technology
licenses, and joint ventures. The SPARO" RISC processor was
developed by both APD and Sun Microsystems, Inc.
In addition to designing and selling a full line of SPARC
processors and peripheral chips, APD also designed and is
selling the EtherStat'" LAN controller - the first VLSI device to
integrate both StarlANTM and Ethernet® protocols into one
device. The core of APD's EtherStar chip was the result of APD's
cooperative venture with Ungermann-Bass.
The Microwave and Optoelectronics Division (MOD) markets
GaAs, FETs, and FET power amplifiers, lightwave and microwave devices, optical devices, emitters, and SI transistors.
The largest FMI marketing division is the Integrated Cirooits
Division (ICD).
Memory and programmable devices marketed by ICD include the
following:
DRAMs and DRAM Modules
EPROMs
EEPROMs
NOV RAMs
CMOS masked ROMs
CMOS SRAMs and CMOS SRAM Modules
BiCMOS SRAMs
Bipolar PROMs
ECLRAMs
STRAMs (self-timed RAM)
Hi-Rei PROMs and SRAMs
Ultra High-speed ECUECL-TTL Translator Cirooits
Linear ICs and Transistors

Static RAM Data Book

Sales Information

Introduction to Fujitsu (Continued)
ASIC products offered by ICD include the following:
CMOS, ECl, and BiCMOS gate arrays
CMOS standard cells
Design Software Support
Design Software Support
Customer support and customer training for ASIC products are
available through the following FMI design centers:
San Jose
Dallas
Atlanta

Gresham
Chicago
Boston

Microcomputer and communications products offered by ICD
include the following:
4-bitMCUs
8- and 16-bit MPUs
SCSI and controllers
DSPs
Prescalers
PlLs
Memory Cards
FMI's manufacturing divisions are in San Diego, California and
Gresham, Oregon. The San Diego Manufacturing Division
assembles and tests memory devices. In 1988, the Gresham
Manufacturing Division began manufacturing ASIC products and
DRAM memories. This facility, when completed, will have one
million square feet of manufacturing-the largest Fujitsu
manufacturing plant outside Japan.
FMI's subsidiary, Fujitsu Components of America, markets
connectors, keyboards, plasma displays, relays, and hybrid ICs.

Fujitsu Mlkroelektronlk GmbH (European Sales Operation)
Fujitsu Mikroelektronik GmbH (FMG) was established in June,
1980, in Frankfurt, West Germany, and is a wholly-owned
subsidiary of Fujitsu Limited, Tokyo. FMG is the sole representative of the Fujitsu Electronic Device Group in Europe. The wide
range of ICs, lSI memories, microprocessors, and ASIC
products are noted throughout Europe for design excellence and
unmatched reliability. Branch offices are located in Munich,
london, Paris, Stockholm, and Milan.

9-5

Static RAM Data Book

Sales Information

Introduction to Fujitsu (Continued)
Fujitsu Microelectronics Ireland, Ltd. (European Production Operation)
Fujitsu Microelectronics Ireland, Ltd. (FME) was established in
1980, in the suburbs of Dublin, as Fujitsu's European Production
Center for integrated circuits. FME assembles DRAMs,
EPROMs, and other LSI memory products.
Fujitsu Microelectronics, Ltd. (European ASIC Design Operation)
Fujitsu Microelectronics, Ltd., Fujitsu's European VLSI DeSign
Center, opened in October of 1983 in Manchester, England. The
Design Center is equipped with highly sophisticated CAD
systems to ensure fast and reliable processing of input data. An
experienced staff of engineers is available to assist in all phases
of the design process.
Fujitsu Microelectronics Asia PTE Ltd. (Asian/Oceanian Sales Operation)
Fujitsu Microelectronics Asia PTE Ltd. (FMA) opened in August
1986 in Hong Kong as a wholly~wned Fujitsu subsidiary for
sales of electronic devices to Asian and Southwest Pacific
markets.

SPARC'h1 18 a trademark of SI.r1 Miaoaystans. Inc.

Eth....... 10 a "", _ _ 01 XeIox Co!poratlan.

EtherStaiTM Ia a trademark 01 Fujitsu Mboeledronlcs, Inc.

SIarlAN'" II a trademar1< 01 AT&T.

9-6

Static RAM Data Book

Sales Information

Integrated Circuits Corporate Headquarters -

Worldwide

International Corporate Headquarters
FUJITSU LIMITED
Marunouchi Headquarters
6-1, Marunouchi l-<:home
Chiyoda-ku, Tokyo 100
Japan
Tel: (03) 216-3211
Telex: 781-22833
FAX: (03) 213-7174

For integrated circuits marketing information please contact the following:

Headquarters for Japan
FUJITSU LIMITED
Integrated Circuits and Semiconductor Marketing
Furukawa 8ogo Bldg.
6-1, Marunouchi 2--<:home
Chiyoda-ku, Tokyo 100
Japan
Tel: (03) 216-3211
Telex: 781-2224361
FAX: (03) 211-3987

Headquarters for North and South America
FUJITSU MICROELECTRONICS, INC,
Integrated Circuits Division
3545 North First Street
San Jose, CA 95134-1804

USA
Tel: (408) 922-9000
Telex: 91Q-331Hl190
FAX: (408) 43241044

Headquarters for Europe
FUJITSU MIKROELEKTRONIK GmbH
Lyoner Strasse 44-48
Arabella Centra 9. OG
D-6OOO Frankfurt 71
Federal Republic of Germany
Tel: (069) 66320
Telex: 441963
FAX: (069) 6632122

Headquarters for ASia and Australia
FUJITSU MICROELECTRONICS ASIA PTE LIMITED
06-04I06'()7 Plaza by the Park
No. 51 Bras Basah Road
Singapore 0719
Tel: (65) 336-1600
Telex: 55573
FAX: (65) 336-1609

9-7

Static RAM Data Book

Sales Information

Fujitsu Microelectronics, Inc. (FMI) Sales Offices for
North and South America
NORTHERN CALIFORNIA

MASSACHUSETTS (Boston)

NEW YORK (Hauppauge)

Fujitsu Microelectronics, Inc.
10600 N. De Anza Blvd.
Suite 225
Cupertino, CA 95014
Tel: (408) 996-1600
FAX: (408) 725-8746

Fujitsu Microelectronics, Inc.
75 Wells Awnue
SuiteS
Newlon Center, MA 02159-3251
Tel: (617) 964-7080
FAX: (617) 964-3301

601 Veterans Memorial Highway
Suite P
Hauppauge, NY 11788-1054
Tel: (516) 361-6565
FAX: (516) 361-6480

Fujitsu Microelectronics, Inc.

SOUTHERN CALIFORNIA

MINNESOTA (Minneapolis)

OREGON (Portland)

Fujitsu Microelectronics, Inc.
Century Centre
2603 Main Street
Suite 510
Irvine, CA 92714
Tel: (714) 724-8n7
FAX: (714) 724-8778

Fujitsu Microelectronics, Inc.
3460 Washington Drive
Suite 209
Eagan, MN 55122-1303
Tel: (612) 454-Q323
FAX: (612) 454-0601

Fujitsu Microelactronics, Inc.
5285 SW Meadows Road
Suite 222
Lake Oswego, OR 97035-9998
Tel: (503) 684-4545
FAX: (503) 684-4547

NEW JERSEY (Mt. Laurel)

TEXAS (Dallas)

Fujitsu Microelectronics, Inc.
Horizon Corpcrate Center
3000 Atrium Way
Suite 100
MI. Laurel, NJ 08054
Tel: (609) 727-9700
FAX: (609) 727-9797

Fujitsu Microelectronics, Inc.
14785 Preston Road
Suite 670
Dallas, TX 75240
Tel: (214) 233-9394
FAX: (214)366-7917

GEORGIA (Atlanta)
Fujitsu Microelectronics, Inc.
3500 Parkway Lane
Suite 210
Norcross, GA 30092
Tel: (404) 449-8539
FAX: (404) 441-2016

ILLINOIS (Chicago)
Fujitsu Microelectronics, Inc.
One Pierce Place
Suite 910
Itasca, IL 60143-2681
Tel: (708) 250-8580
FAX: (708) 250-8591

9-8

Static RAM Data Book

Sales Information

FMI Representatives - USA
For product information, contact your lJ8arest Representative.

Alabama

Connecticut

Indiana

The Nows Group, Inc.
2905 Westcorp Blvd,
Suite 120
Huntsville, AL 35805
Tel: (205) 534-0044
FAX: (205) 534-{J186

Conntech Sales, Inc.
182 Grand Street
Suite 318
Waterbury, CT 06702
Tel: (203) 754-2823
FAX: (203) 573-0538

Fred Dorsey & Associates
3518 Eden Place
Carmel,IN 46032
Tel: (317) 844-4842
FAX: (317) 844-4843

Arizona

Florida

Aztech Component Sales Inc.
15230 N 75th Street
Suite 1031
Scottsdale, AZ 85260
Tel: (602) 99Hi3oo
FAX: (602) 991-Q563

Samtronic Associates, Inc,
657 Maidand Avenue
Altamonte Springs, FL 3270 1
Tel: (407) 831~33
FAX: (407) 831-2844

Iowa

California
Harvey King, Inc,
6393 Nancy Ridge Drive
San Diego, CA 92121
Tel: (619) 587-9300
FAX: (619) 587-Q507
Infinity Sales, Inc.
4500 Campus Drive
Suite 300
Newport Beach, CA 92660
Tel: (714) 833-Q300
FAX: (714) 833-Q303
Norcomp
3350 Scott Blvd.,
Suite 24
Santa Clara, CA 95054
Tel: (408) 727-7707
FAX: (408) 986-1947
Noroomp
2140 Professional Drive
Suite 200
Roseville, CA 95661
Tel: (916) 782-9070
FAX: (916) 782-9073

Semtronic Associates, Inc,
1467 S. Missouri Avenue
Clearwater, FL 33516
Tel: (813) 461-4675
FAX: (813) 442-2234
Semtronic Associates, Inc.
3471 NW 55th Street
Ft Lauderdale, FL 33309
Tel: (305) 731-2484
FAX: (305) 731-1019

Georgia
The Novus Group, Inc.
6115-A Oakbrock Pkwy
Norcross, GA 30093
Tel: (404) 263-Q32O
FAX: (404) 263-9946

Idaho
Cascade Components
2710 Sunrise Rim Road
Suite 130
Boise, 1083705
Tel: (208) 343-9886
FAX: (208) 343-9887

Illinois
Colorado
Front Range Marketing
3100 Arapahoe Road
Suite 404
Boulder, CO 80303
Tel: (303) 443-4780
FAX: (303) 447-Q371

Beta Technology
1009 Hawthorn Drive
Itasca,IL80143
Tel: (708) 256-9586
FAX: (708) 256-9592

Electromec Sales
1500 2nd Avenue
Suite 205
Cedar Rapids, IA 52403
Tel: (319) 362-6413
FAX: (319) 362-6535

Maryland
Arbotek Associates
102 W, Joppa Road
Towson, MD 21204
Tel: (301)825-Qn5
FAX: (301) 337-2781

Massachusetts
Milt-Bern Associates
2 Mack Road
Wobum, MA 01801
Tel: (617) 932-3311
FAX: (617) 932-Q511

Michigan
Greiner Associates, Inc,
15324 E. Jefferson Avenue
Suite 12
Grosse Point Park, MI 48230
Tel: (313) 499-Q188
FAX: (313) 499-Q665

Minnesota
Electromec Sales
1601 E Highway 13
Suite 200
Burnsville, MN 55337
Tel: (612) 894-8200
FAX: (612)894-9352

9-9

Sales Information

Static RAM Data Book

FMI Representatives - USA (Continued)
New Jersey

North carolina

Technical Marketing, Inc.

BGR Associates
Evesham Commons
525 Route 73
Suite 100
Marlton, NJ 08053
Tel: (609) 983-1020
FAX: (609) 983-1879

The Now. Group, Inc.
102.6 Commonwealth Court
Cary, NC 27511
Tel: (919) 460-ml
FAX: (919)460-6703

Suite 139
Houston, TX 77042
Tel: (713) 783-4497
FAX: (713) 783-5307

Technical Applications & Marketing

Spectrum ESO
3947 Ray Court Road

91 Clinton Road
Suite1D
Fairfield, NJ 07006
Tel: (201) 575--4130
FAX: (20 1) 575--4563

New York
Quality Components
3343 Harlem Road
Buffalo, NY 14225
Tel: (716)837~
FAX: (716) 837-0662
Quality Components
116 Fayette Street
Manlius, NY 13104
Tel: (315) 682-8865
FAX: (315) 682-22n
Quality Components
2318 TItus Ave.
Rochester, NY 14622
Tel: (716) 342-7229
FAX: (716) 342-7227

9-10

Ohio

Morrow, OH 45152
Tel: (513) 899-3260
FAX: (513) 8911-3260
Spectrum ESO
8925 Galloway Trail
Novelty, OH 44072
Tel: (216) 338-522.6
FAX: (216) 336-3214

Oregon
L-8quared Umitad
15234 NW Greenbrier Pkwy

Beaverton, OR 97006
Tel: (503) 629-8555
FAX: (503)645-8196

Texas
Technical Marketing, Inc.
3320 Wiley Post Road
Carrollton, TX 75006
Tel: (214) 367-3601
FAX: (214) 367-3605

2901 W~crest Drive

Technical Marketing, Inc.
1315 Sam Bass Circle
Suite B-3
Round Rock, TX 78681
Tel: (512) 24

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