1990_Hitachi_IC_Memory_Data_Book 1990 Hitachi IC Memory Data Book

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ICMEMORY
DATA BOOK

#M11.1

CS-E410T

When using this document, keep the following in mind:
1.

This document may, wholly or partially, be subject to change without
notice.

2.

All rights are reserved: No one is permitted to reproduce or duplicate, in
any form, the whole or part of this document without Hitachi's permission.

3.

Hitachi will not be held responsible for any damage to the user that may
result from accidents or any other reasons during operation of the user's
unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims
or other problems that may result from applications based on the examples
described herein.
5.

No license is granted by implication or otherwise under any patents or
other rights of any third party or Hitachi, Ltd.

6.

MEDICAL APPLICATIONS: Hitachi's products are not authorized for
use in MEDICAL APPLICATIONS without the written consent of the
appropriate officer of Hitachi's sales company. Such use includes, but is
not limited to, use in life support systems. Buyers of Hitachi's products are
requested to notify the relevant Hitachi sales offices when planning to use
the products in MEDICAL APPLICATIONS.

January 1990

©Copyright 1990, Hitachi America, Ltd.

Printed in U.S.A.

Section

INTRODUCTION

MOS Static RAM

Cache Static RAM and
Fast SRAM Modules

MOS Pseudo Static RAM

Video Memory

MOS Dynamic RAM

MOS Dynamic RAM Module

MOS Mask ROM

MOSPROM
ECLRAM
HITACHI SALES OFFICES

o

SECTION 9, PAGE 1302

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------------------------TABLEOFCONTENTS

TABLE OF CONTENTS
Page

Introduction
QUICK REFERENCE GUIDE

XIII

PACKAGE INFORMATION
RELIABILITY OF HITACHI I C. MEMORIES .. .

13

QUALITY ASSURANCE OF I C MEMORY

28

.. .

OUTLINE OF TESTING METHOD

34

APPLICATION ..

35

Section 1
MOS Static Ram
• HM6116 SERIES
HM6116P-2/3/4
HM6116LP-2/3/4
HM6116FP-2/3/4
HM6116LFP-2/3/4

2,048-word x 8-blt High Speed CMOS Stalic RAM . . ..

64

• HM6116A SERIES
HM6116AP-12/15/20
HM6116ALP-12/15/20
HM6116ASP-12/15/20
HM6116ALSP-12/15/20

2,048-word x 8-bit High Speed Static CMOS RAM ....... . .... .

69

• HM6716 SERIES
HM6716P-25/30

2,048-word x 8-bit High Speed HI-BiCMOS Static RAM (with OE) ..

74

• HM6719 SERIES
HM6719P-25/30

2,048-word x 9-bit High Speed HI-BiCMOS Static RAM (with OE) ...

74

• HM6268 SERIES
HM6268P-25/35/45
HM6268LP-25/35/45

4,096-word x 4-blt High Speed CMOS Static RAM . .... . ..... .

80

• HM6267 SERIES
HM6267P-35/45/55
HM6267LP-35/45/55

16,384-word x 1-blt High Speed CMOS Static RAM .....

87

• HM6264A SERIES
HM6264AP-10/12/15
HM6264ALP-10/12/15
HM6264ALP-10LlI2L115L
HM6264ASP-10/12/15
HM6264ALSP-10/12/15
H M6264ALSP-l OLl12L115L
H M6264AFP-l 0/12/15
HM6264ALFP-10/12/15
H M6264ALFP-10Ll12L115L

8,192-word x 8-blt High Speed CMOS Static RAM .............. .

94

• HM6288 SERIES
H M6288P-25/35
HM6288LP-25/35
H M6288J P-25/35
H M6288LJ P-25/35

16,384-word x 4-blt High Speed CMOS Static RAM ..

103

• HM6788 SERIES
H M6788P-25/30

16,384-word x 4-blt High Speed HI-BICMOS Static RAM ......... .

111

• HM6788H SERIES
HM6788HP-15/20

16,384-word x 4-bit High Speed Hi-BiCMOS Static RAM ......... .

115

• HM6788HA SERIES
HM6788HAP-12/15/20

16,384-word x 4-bit High Speed Static RAM. . . . . . . . . . . . . . ..

. ..

119

• HM6289 SERIES
HM6289JP-25/35
HM6289LJP-25/35

16,384-word x 4-bit High Speed CMOS Static RAM (with OE) ..... .

124

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra POint Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

TABLEOFCONTENTS--------------------------------------------------Section l-MOS Static Ram (continued)

Page

• HM6789 SERIES
HM6789P-25/30
HM6789JP-25/30

16,384-word x 4-bit High Speed Hi-SiCMOS Static RAM (with OE) ..

135

• HM6789H SERIES
HM6789HP-15/20
HM6789HJP-15/20

16,384-word x 4-bit High Speed HI-SiCMOS Static RAM (with OE)

142

• HM6789HA SERIES
HM6789HAP-12/15/20
HM6789HAJP-12/15/20

16,384-word x 4-bit High Speed Static RAM (with OE)

149

• HM6287 SERIES
H M6287P-45/55/70
HM6287LP-45/55/70

65,536-word x l-blt High Speed CMOS Static RAM ..

157

• HM6287H SERIES
H M6287H P-25/35
HM6287HLP-25/35
HM6287HJP-25/35
HM6287HLJP-25/35

65,536-word x l-bit High Speed CMOS Static RAM. . . . .. . .....

164

• HM6787 SERIES
H M6787P-25/30

65,536-word x l-bit High Speed HI-SIC MaS Static RAM . .

173

• HM6787H SERIES
HM6787HP-15/20
HM6787HJP-15/20

65,536-word x l-bit High Speed HI-SiCMOS Static RAM ...

178

• HM6787HA SERIES
HM6787HAP-12/15/20
HM6787HAJP-12/15/20

65,536-word x l-bit High Speed Static RAM ...

183

• HM62256 SERIES

32,768-word x 8-bit High Speed CMOS Static RAM.

189

HM62256P-8/10/12/15
HM62256LP-8/10/12/15

H M62256LP-l0SLl12SLl15SL
H M62256FP-8Tfl0T 112T115T
HM62256LFP-8T/l0T/12T/15T
HM62256LFP-8SLT/l0SLT/12SLT/15SLT
• HM62832/HM62832H
HM62832P-35/45
HM62832LP-35/45
HM62832JP-35/45
H M62832LJ P-35/45
HM62832HP-35/45
HM62832HJP-35/45

32,768-word x 8-bit High Speed CMOS Static RAM

197

• HM6208/HM6208H SERIES
H M6208P-35/45
HM6208HP-25/35
H M6208H LP-25/35
HM6208HJP-25/35
HM6208HLJP-25/35

65,536-word x 4-bit High Speed CMOS Static RAM ...

203

• HM6708 SERIES
H M6708P-20/25
HM6708JP-20/25

65,536-word x 4-blt High Speed HI-SiC MaS Static RAM ...

211

• HM6708A SERIES
H M6708AP-15/20/25
H M6708AJ P-15/20/25

65,536-word x 4-bit High Speed Static RAM ....

217

• HM6709 SERIES
HM6709JP-20/25

65,536-word x 4-bit High Speed Static RAM (with OE) ..

222

• HM6709A SERIES
H M6709AP-15/20/25
HM6709AJP-15/20/25

65,536-word x 4-bit High Speed Static RAM (with OE) ....

229

~HITACHI
ii

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------------------------TABLE OF CONTENTS
Section 1-MOS Static Ram (continued)

Page

• HM6207 SERIES
HM6207P-35/45
HM6207LP-35/45

262,144-word x l-blt High Speed CMOS Static RAM.

236

• HM6207H SERIES
HM6207P-35/45
HM6207HP-25/35
HM6207HLP-25/35
HM6207HJP-25/35
HM6207HLJP-25/35

262,l44-word x l-blt High Speed CMOS Static RAM.. .. .... . ..

243

• HM6707 SERIES
HM6707P-20/25
HM6707JP-20/25

262,144-word x l-blt High Speed HI-BICMOS Static RAM.

250

• HM6707A SERIES
HM6707AP-15/20/25
HM6707AJP-15/20/25

262,144-word x l-blt High Speed Static RAM .....

255

• HM628128 SERIES
HM628128P-7/8/10/12
HM628128LP-7/8/10112
HM628128FP-7/8/10112
HM628128LFP-7/8/10/12

131,072-word

x 8-bit High Speed CMOS Static RAM ............ .

261

• HM624256 SERIES
HM624256P-35/45
HM624256LP-35/45
HM624256JP-35/45
HM624256LJP-35/45

262,l44-word x 4-blt High Speed CMOS Static RAM ........... .

269

• HM624257 SERIES
HM624257JP-35/45
HM624257LJP-35/45

262,144-word x 4-bit High Speed CMOS Static RAM ............ .

275

• HM66204 SERIES
HM66204-12/15
HM66204L-12/15

131,072-word

x 8-bit High Density CMOS Static RAM Module.....

283

• HM63921-20/25/35
HM63921 P-20/25/35

2K x 9-bit CMOS Parallel In-Out FIFO Memory ....

289

• HM63941-25/35/45
HM63941 P-25/35/45

4K

x 9-bit CMOS Parallel In-Out FIFO Memory ..

301

Section 2
Cache Static RAM and Fast SRAM Modules
• HM62A168/HM62A188 SERIES
HM62168CP-25/35/45
HM62188CP-25/35/45

Direct Mapped 8,192-word x 16/18-blt 2-way .................. .
4,096-word x 16/18-bit Static Cache RAM

311

• HM67C932 SERIES
HM67C932CP-20/25

8,192-word

x 9-blt x 4-row Static Cache RAM ................. .

319

• HB66B1616A-25/35
HB66B1616A-25/35

16,384-word x 16-bit High Speed Static RAM Module ........... .

333

• HB66A2568A-25/35
HB66A2568A-25/35

262,144-word x 8-blt High Speed Static RAM Module ........... .

343

• HM644332
HM644332G-25/30

2,048 Entry Tag Memory. . . . .. ........................... .

351

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

iii

TABLEOFCONTENTS--------------------------------------------------Section 3
MOS Pseudo Static RAM

Page

• HM65256B SERIES
HM65256BP-l0/12/15/20
HM65256BLP-l0/12/15/20
HM65256BSP-l0/12/15/20
HM65256BLSP-l0/12/15/20
HM65256BFP-l0T112T/15T120T
HM65256BLFP-l0T/12T/15T/20T

32,768-word x 8-bit High Speed Pseudo Static RAM. . .. . ...... .

369

• HM658128 SERIES
HM658128DP-l0/12/15
HM658128LP-l0/12/15
HM658128DFP-l0/12/15
HM658128LFP-l0/12/15

131,072-word x 8-bit High Speed CMOS Pseudo Static RAM

376

., ,

..'
'

,.

Section 4
Video Memory
• HM63021 SERIES
HM63021 P-28/34/45

2,048-word x 8-bit Line Memory ..

388

• HM53051P
HM53051 P-45/60

262,144-word x 4-bit Frame Memory ..

402

• HM53461 SERIES
HM53461 P-l0/12/15
HM53461 ZP-l0/12/15

65,536-word x 4-bit Multiport CMOS Video RAM.

412

• HM53462 SERIES
HM53462P-l0/12/15
HM53462ZP-l0/12/15

65.536-word x 4-blt Multiport CMOS Video RAM
(with Logic operallOn mode)

425

• HM538122 SERIES
HM538122JP-l0/12/15

131,072-word x 8-bit Multiport CMOS Video RAM .....

444

• HM538123 SERIES
HM538123JP-l0/12/15

131,072-word x 8-bit Multiport CMOS Video RAM .... "

• HM534251 SERIES
HM534251JP-l0/11/12/15
HM534251 ZP-l0/11/12/15

262,144-word x 4-blt Multiport CMOS Video RAM .............. .

469

• HM534252 SERIES
HM534252JP-l0/11/12/15
HM534252ZP-l0111 112/15

262,144-word x 4-bit Multiport CMOS Video RAM ...

516

• HM534253 SERIES
HM534253JP-l0/12/15
HM534253ZP-l0/12/15

262,144-word x 4-bit Multlport CMOS Video RAM ...... .

542

• HM538121JP/ZP-l0/12/15
HM538121 JP-l0/12/15

131,072 x 8-bit Multiport CMOS Video Random Access Memory ..

569

• HM50464 SERIES
HM50464P-12/15/20
HM50464CP-12/15/20

65,536-word x 4-bit Dynamic Random Access Memory .......... .

590

• HM50256 SERIES
HM50256P-12/15/20
HM50256ZP-12/15/20
HM50256CP-12/15/20

262,144-word x I-bit Dynamic Random Access Memory ......... .

598

• HM51256 SERIES
HM51256P-8/10/12/15
HM51256CP-8/10/12/15
HM51256LP-8/10/12/15
HM51256LCP-8/10/12/15
HM51256ZP-8/10/12/15
HM51256LZP-8/10/12/15

262,144-word x I-bit Dynamic Random Access Memory ......... .

606

...

470

Section 5
MOS Dynamic RAM

~HITACHI
iv

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------------------------TABLEOFCONTENTS
Section 5-MOS Dynamic RAM (continued)
• HM51258 SERIES

Page

262,144-word x l-bit Static Column CMOS Dynamic RAM. ... ... .

614

• HM514256 SERIES
HM514256P-8/10/12
HM514256JP-8/10/12
HM514256ZP-S/l0/12

262,144-word x 4-blt CMOS Dynamic RAM . . . . . . . . . . . . . . . . . . . .

623

• HM514256S/HM514256A SERIES
HM514256P-SS/l0S/12S
HM514256JP-SS/l0S/12S
HM514256ZP-8S/10S/12S
HM514256AP-8/10/12
HM514256AJP-S/l0/12
HM514256AZP-8/10112

262,144-word x 4-bit CMOS Dynamic RAM . . . . . . .. ... ... ...

635

• HM514256API/AJPI/AZPI-6I71S/10/12
(EXTENDED TEMPERATURE
RANGE VERSION)
HM514256API-6/7/S/10/12
HM514256AJPI-6/7/S/10/12
HM514256AZPI-6171S/10/12

262,144-word x 4-blt Dynamic Random Access Memory.

651

• HM514256ALP/ALJP/ALZP-S/l0/12
HM514256ALP-S/l0/12
HM514256ALJP-8/10/12
HM514256ALZP-S110/12

262,144-word x 4-bit Dynamic Random Access Memory. ........

667

• HM514256H SERIES
HM514256HP-617
HM514256HJP-6/7
HM514256HZP-617

262,144-word x 4-bit CMOS Dynamic RAM. . . . . . . .. . . . . .. ....

6S2

• HM514258S/HM514258A SERIES
HM514258P-8S/10S/12S
HM51425SJP-SS/l0S/12S
HM51425SZP-SS/l0S/12S
HM51425SAP-S/l0/12
HM51425SAJP-S/l0/12
HM51425SAZP-S/l0/12

262,144-word x 4-bit CMOS Dynamic RAM. . . . . . . . . . . . . . . . . . . .

696

• HM514266AP/AJP/AZP-61718/10/12

262,144-word x 4-bit Dynamic Random Access Memory. .. ......

711

• HM511000S/HM511000A SERIES
HM511000P-SS/l0S/12S
HM511000JP-8S/10S/12S
HM511000ZP-SS/l0S/12S
HM511000AP-S/l0/12
HM511000AJP-8/10/12
HM511000AZP-S/l0112

1,04S,576-word x l-bit CMOS Dynamic RAM. . . . . . ... .... . . .

725

• HM511000ALP/ALJP/ALZP-S/l0/12
HM511000ALP-8/10/12
HM511000ALJP-8110/12
HM511000ALZP-8/10/12

1,04S,576-word x l-bit Dynamic Random Access Memory. . . . . . . .

737

• HM511000H SERIES
HM511000HP-6/7
HM511000HJP-6/7
HM511000HZP-6/7

1,04S,576-word x l-bit CMOS Dynamic RAM...........

751

• HM511001S SERIES
HM511001 P-SSI10S/12S
HM511001JP-SS/l0S/12S
HM511001 ZP-SS/l0S/12S

1,04S,576-word x l-bit CMOS Dynamic RAM. " . . . . . . . . . . . . . . . .

762

HM51258P-8/10/12/15

HM514266AP-6/7/S/10/12
HM514266AJP-6/7/8/10/12
HM514266AZP-6/7/S/10/12

•
Hitachi America, Ltd .•

H~achi

HITACHI

Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

v

TABLEOFCONTENTS--------------------------------------------------Section 5-MOS Dynamic RAM (continued)

Page

• HM511001A SERIES
HM511001 AP-B/l0/12
HM511001 AJP-B/l0/12
HM511001 AZP-B/l0/12

1,048,576-word x 1-bit CMOS Dynamic RAM ..

773

• HM571000JP-35R/40/45
HM571000JP-35R/40/45

1,048,576-word xl-bit (BiCMOS) Memory

785

• HM574256JP-35R/40/45
HM574256JP-35R/40/45

262,144-word x 4-blt (BiCMOS) ........ .

803

• HM511002S/HM511002A
HM511002P-BS/l0S/12S
HM511002JP-BS/l0S/12S
HM511002ZP-BS/l0S/12S
HM511002AP-B/l0/12
HM511002AJP-B/l0/12
HM511002AZP-B/l0/12

1,048,576-word x 1-bit CMOS Dynamic RAM ...... .

816

• HB56A lBA/AT/B-6H/7H/BA/10A/12A
HB56A lBA-6H/7H/BA/l0A/12A
HB56A lBAT-6H/7H/BA/l0A/12A
HB56A lBB-6H/7H/BAI1 OAl12A

1,048,576-word x 8-bit High Density Dynamic RAM Module.

831

• HB56C1BA/AT/B-BA/10A/12A
HB56C1BA-BA/l0A/12A
HB56C1BAT-BA/l0Al12A
HB56C1BB-BA/l0A/12A

1,048,576-word x 8-blt High Density Dynamic RAM Module

837

• HB56A 19A/AT/B-6H/7H/BA/10A/12A
HB56A 19A-6H/7H/BA/l0A/12A
HB56A 19AT-6H/7H/BA/l0A/12A
HB56A 19B-6H/7H/BA/l0A/12A

1,04B,576-word x 9-blt High Density Dynamic RAM Module ..

843

• HB56C19A/AT/B-BA/10A/12A
HB56C19A-BA/l0A/12A
HB56C19AT-BA/l0A/12A
HB56C19B-BA/l0A/12A

1,048,576-word x 9-bit High Density Dynamic RAM Module.. . ...

849

• HM514100JP/ZP-B/l0/12
HM514100JP-B/l0/12
HM514100ZP-B/l0/12

4,194,304-word x 1-bit Dynamic Random Access Memory

855

• HM514100JP/ZP-7
HM514100JP-7
HM514100ZP-7

4,194,304-word x 1-blt Dynamic Random Access Memory.

869

• HM514100LJP/LZP-B/l0/12
HM514100LJP-B/l0/12
HM514100LZP-B/l0/12

4,194,304-word x 1-blt Dynamic Random Access Memory.

883

• HM514400JP/ZP-8/10/12
HM514400JP-8/10/12
HM514400ZP-8/10/12

1,048,576-word x 4-bit Dynamic Random Access Memory

• HM514410JP/ZP-8/10/12
HM514410JP-8/10/12
HM514410ZP-8/10/12

1,048,576-word x 4-bit Dynamic Random Access Memory ..

911

• HM514400LJP/LZP-8/10/12
HM514400LJP-B/l0/12
HM514400LZP-8/10/12

1,04B,576-word x 4-bit Dynamic Random Access Memory ...... .

931

• HB561003 SERIES
HB561003AR/B-12/15

262,144-word x 9-bit Dynamic Random Access Memory Module ...

954

• HB561409 SERIES
HB561409A-10/B-l0

262,144-word x 9-bit Dynamic Random Access Memory Module

958

..

..

897

Section 6
MOS Dynamic RAM Module

~HITACHI
vi

Hitachi America, ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

..

~~------------------------------------------------TABLEOFCONTENTS

Section 6-MOS Dynamic RAM Module (continued)

Page

• HB561008 SERIES
H B561 008AR/B-12/B-15

262,144-word x 8-bIt Dynamic Random Access Memory Module

963

• HB56D25608A/B-6H/7H/8A/10A/12A
H B56D25608A-6H/7H/8A/1 OA/12A
HB56D25608B-6H/7H/8A/10A/12A

262,144-word x 8-blt High Density Dynamic RAM Module.

967

• HB56D25609A/B-85A/10A/12A
HB56D25609A-85A/10A/12A
HB56D25609B-85A110A/12A

262,144-word x 9-bIt High Density Dynamic RAM Module

979

• HB56D25636B-85/10/12

262,144-word x 36-blt High Density Dynamic RAM Module.

991

• HB56D51236B-85/10/12

524,288-word x 36-blt High Density Dynamic RAM Module

1003

• HB56A48A/AT/B-8/10/12
HB56A48A-8/10/12
HB56A48AT-8/10/12
HB56A48B-8/10/12

4,194,304-word x 8-blt High Density Dynamic RAM Module

1015

• HB56A49A/AT/B-8/10/12
HB56A49A-8/10/12
HB56A49AT-8/10/12
HB56A49B-8/10/12

4,194,304-word x 9-blt High Density Dynamic RAM Module.

1027

• HB56D136B-8/10/12

1,048,576-word x 36-blt High Density Dynamic RAM Module

1039

• HB56D236B-8/10/12

2,097,152-word x 36-blt High Density Dynamic RAM Module

1049

• HN623257p, HN623257F
HN623257P
HN623257F

32,768-word x 8-blt CMOS Mask Programmable.
Read Only Memory

1060

• HN623258P, HN623258F
HN623258P
HN623258F

32,768-word x 8-blt CMOS Mask Programmable ROM.

1063

• HN62321/HN62331 SERIES
HN62321P
HN62321BP
HN62331 P
HN62321F
HN62321BF
HN62331 F

131,072-word x 8-blt CMOS Mask Programmable ROM

• HN62331AP/F
HN62331AP
HN62331AF

131,072-word x 8-bIt CMOS Mask Programmable
Read Only Memory

1069

• HN62331 P/F
HN62331P
HN62331F

131,072-word x 8-bIt CMOS Mask Programmable
Read Only Memory

1073

• HN62321 E/HN62331 E SERIES
HN62321EP
HN62332EP
HN62321EF
HN62331EF

131,072-word x 8-blt CMOS Mask Programmable ROM

1077

• HN62321 AlHN62331 A SERIES
HN62321AP
HN62331AP
HN62321AF
HN62331AF

131,072-word x 8-blt CMOS Mask Programmable ROM

1080

• HN62412/HN62422 SERIES
HN62412P
HN62422P
HN62412FP
HN62422FP

131,072-word x 16-bltl262,144-word x 8-blt CMOS
Mask Programmable ROM

1083

Section 7
MOS Mask ROM

.

1066

~HITACHI
Hitachi America, Ltd • Hitachi Plaza' 2000 Sierra Point Pkwy' Brisbane, CA 94005-1819 • (415) 589-8300

vii

TABLEOFCONTENTS------------------------------------------------Page

Section 7-MOS Mask ROM (continued)
• HN62404/HN62424 SERIES
HN62404P
HN62424P
HN62404FP
HN62424FP

262,144-word x 16-bitl524,288-word x 8-bit CMOS ............. .
Mask Programmable ROM

1087

• HN62304B/HN62324B SERIES
HN62304BP
HN62324BP
HN62304BF
HN62324BF

524,288-word x 8-bit CMOS ............................... .
Mask Programmable ROM

1091

• HN62444 SERIES
HN62444P
HN62444FP
HN62444F

262,144-word x 16-bitl524,288-word x 8-bit CMOS ......... .
Mask Programmable Read Only Memory

1095

• HN62414 SERIES
HN62414P-17/20
HN62414FP-17/20
HN62414F-17/20

262,144-word x 16-bitl524,288-word x 8-bit CMOS ............. .
Mask Programmable Read Only Memory

1101

• HN62314B SERIES
HN62314BP-17/20
HN62314BF-17/20

524,288-word x 8-bit CMOS Mask Programmable Read Only Memory

1107

• HN62344B SERIES
HN62344BP
HN62344BF

524,288-word x 8-bit CMOS Mask Programmable Read Only Memory

1111

• HN62408 SERIES
HN62408P
HN62408FP

524,288-word x 16-bitll,048,576-word x 8-bit CMOS ........... .
Mask Programmable ROM

1114

• HN62308B SERIES
HN62308BP
HN62308BF

1,048,576-word x 8-bit CMOS Mask Programmable Read ........ .
Only Memory

1119

• HN66403P SERIES
HN66403P

524,288-word x 16-bitll,048,576-word x 8-bit CMOS ........... .
Mask Programmable Read Only Memory

1123

• HN624016 SERIES
HN624016P
HN624016F

1,048,576-word x 16-bitl2,097,152-word x 8-bit CMOS .......... .
Mask Programmable Read Only Memory

1127

• HN58064 SERIES
HN58064P-25/30

8,192-word x 8-bit Electrically Erasable and Programmable ROM ...

1132

• HN58C65 SERIES
HN58C65P-25
HN58C65FP-25

8,192-word x 8-bit Electrically Erasable and Programmable ...... .
CMOS ROM

1138

• HN58C66 SERIES
HN58C66P-25
HN58C66FP-25

8,192-word x 8-bit CMOS Electrically Erasable and ............. .
Programmable ROM

1147

• HN58C256 SERIES
HN58C256P-15/20
HN58C256FP-15/20

32,768-word x 8-bit Electrically Erasable and Programmable ..... .
CMOS ROM

1156

• HN27C256AG SERIES
HN27C256AG-l0/12/15

32,768-word x 8-bit UV Erasable and Programmable ROM ....... .

1158

• HN27C256HG SERIES
HN27C256HG-70/85

32,768-word x 8-bit CMOS UV Erasable and Programmable ROM ..

1166

• HN27512G SERIES
HN27512G-25/30

65,536-word x 8-blt UV Erasable and Programmable ROM ....... .

1176

• HN27Cl024HG SERIES
HN27Cl024HG-85/10

65,536-word x 16-bit CMOS UV Erasable and Programmable ROM.

1183

Section 8
MOSPROM

•
viii

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------------TABlEOFCONTENTS
Page

Section 8-MOS PROM (continued)
• HN27C101G SERIES
HN27C101 G-17/20/25

131,072-word x 8-blt CMOS UV Erasable and Programmable ROM.

1192

• HN27C301G SERIES
HN27C301 G-17/20/25

131,072-word x 8-bit CMOS UV Erasable and Programmable ROM

1200

• HN27C256FP SERIES

32,768-word x 8-blt CMOS One Time Electrically ...
Programmable ROM

1209

• HN27512P SERIES
HN27512P-25/30

65,536-word x 8-bit One Time Electrically Programmable.
Read Only Memory

1215

• HN27C101P/FP SERIES
HN27C101 P-20/25
H N27C 101 FP-20/25

131,072-word x 8-bit CMOS One Time
Electrically Programmable ROM

1222

• HN27C301 P/FP SERIES
HN27C301 P-20/25
HN27C301 FP-20/25

131,072-word x 8-blt CMOS One Time ..
Electrically Programmable ROM

1229

• HN27C101AG SERIES
CMOS 1Mb EPROM

131,072-word x 8-bit CMOS UV Erasable and Programmable ROM.

1237

• HN27C4096 SERIES
HN27C4096G-10/12/15
HN27C4096CC-10/12/15

262,144-word x 16-bIt CMOS UV Erasable and Programmable ROM

1247

• HM10494 SERIES
HM10494-10/12
HM10494F-10/12

16,384-word x 4-bit Fully Decoded Random Access Memory

1258

• HM10490 SERIES
HM10490-10/12

65,536-word x 1-blt Fully Decoded Random Access Memory ..

1263

• HM10504-10/12

65,536-word x 4-bit Fully Decoded Random Access Memory

1267

• HM10500-15

262,144-word x 1-bit Fully Decoded Random Access Memory

1268

• HM100494 SERIES
HM100494-10/12
HM100494F-10/12

16,384-word x 4-bit Fully Decoded Random Access Memory ..

1273

• HM100490-10/12

65,536-word x 1-bIt Fully Decoded Random Access Memory ... .

1277

• HM100504F-10/12

65,536-word x 4-bit Fully Decoded Random Access Memory .. .

1281

• HM100500 SERIES
HM100500-18
HM100500CG-18
HM100500F-18

262,144-word x 1-blt Fully Decoded Random Access Memory ..

1282

• HM101494 SERIES
HM101494-10/12
HM101494F-10/12

16,384-word x 4-bit Fully Decoded Random Access Memory ..... .

1285

• HM101490-10/12

65,536-word x 1-bit Fully Decoded Random Access Memory

1289

• HM101504F-10/12

65,536-word x 4-bit Fully Decoded Random Access Memory

1293

• HM101500F-15

262,144-word x 1-blt Fu!ly Decoded Random Access Memory ....

1294

Section 9
ECl RAM
...

HITACHI SALES OFFICES. . . . . . . . . . .. . .............. .

1302

@HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy' Brisbane, CA 94005-1819' (415) 589-8300

ix

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

INTRODUCTION
• Ouick
Reference
.to Hitachi I.C. Memories
• Package Information
• Reliability of
Hitachi I.C. Memories
• Quality Assurance of
I.C. Memory
• Outline of Thsting Method
• Application

~HITACHI®

.HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave .• San Jose, CA 95131 • (408) 435-8300

QUICK REFERENCE GUIDE TO HITACHI MEMORIES
• MOSRAM
Mode

Total

Type No.

Process

OrgamzatJon
(word x bII)

~cess

Cycle

Time
(ns)
Max

Time
(ns)
Max

16-2'2
16-4"2
16L"2"2
HM il16L"3"2

~"1"~2_

nM

)11-

Hili
Hili

IV) •

Power
DIssipation
(W)

Package

10

CMOS

2048x8

12
15

,<
2"2
5"2

150
200

~0"2

16k-b r.7.'i:;;:c=----j Bi-CMOS

~n--'NoG-'---'-PFp'Tl-rspzp"T".C-'G----r
CPJ"p-l
M
Ie e

'e e

.e

e

i4

10a/0.175

'••

i4

10tJO.15

•e ee

0.1m/15m

12
15
21

5tJl0m

2048~

24

i4

e

le

•
•
•

Ie
Ie
Ie

0.28

(withllt)

!5
35
~

4096x4

15

0.ltJO.25

~

5tJO.25

31
41
31

CMOS

74

••
••
e

I-----i 20 I-r.:++--t-+-+-+-t-t---:~
~-U~'

M5l425

5'3

2

34

3

45
45

4

60
190
220
260
190
220
260

10
120
150
10
120
15C

120
150
100
120
150
100
1()(
12(
15(
10
1()(
120
150

~'3

65536 x 4
NMOS

___ ii~:;-+------l

200
120

262144 x 1 '12
I-IM~1?1;R1

_R

CMOS

3

'.'.1.
,.,.

3

,.,.

176
88

1110
10
l:iO
10

16k-b

Page

220
260
190
220
260
190
190
220
260
190
190
220
260
190
120
!SO
120
!60
330
220

15

251

85
100
120
150

155
185
210
250

025
02

I..

412

I..

412

,..

425

,..

425

24 ~1tt~_4_+~.-+-+-+-+~4111~2
,..
425

•

569

,.

444

40 1---~-4-+-+-+-+'.~-I--~444_

+5

I.

35m10 55

,.

444
470

I.

470

•
•
•
•
•

I.
I.
I.
I.
I.

469
469
469

•
•

i.
I.

516
542

•
•

I.
I.

469

516

542
!j.

18 ~I~.-+-+-+-+I.~-I---I--~~_
20m10.35

I.
I.
I.
Itt

•
•
•

I.

I.

,.

I.

,.

I.

I.
I.
Ie

~

I.

I.

i9R
106

I.

606

Ie

;98
i98

606
(continued)

~HITACHI
xvi

Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - QUICK REFERENCE GUIDE

• MOSRAM
I~cess Cycle

Mode

Total

Process

Type No

Orgamzabon . ~~. lime
(word x bit)
(ns)
Max

Power

110',,.

"pol,

DissipaMn

IV)

(W)

Package "

~n-"'NoG-r--rpi FP-'-I-"spl zp--'-ICG-I"'--'cpl J.....,...--lPM

Page

f-I

IM512
262144 x 1 f-1,*-C~!O,....,

10m/0.35

12
IS

IMOIl

16

r..

I.

I.

111, 40

I.
I.
I.
I.
i.
I·
I.
I.
I.
I.

I.
I.
I.
Ie
Ie
I.
I.
I.
Ie
Ie

I.
I.
I.
..I.
I.
I.
.-

I.

I.
I.

111: 30
IIIl 75

I.
I.

I.
I.

I.
I.

·-.··
··•
•
·

,..-r.'. ...
I.•• .•

I
1(

IM514

I
1(
120
80
100
12(

5-I:S

160
190
2:!0

10mlO.33

1!10
2:!0

6(

120

71
8(
10!
12(
60

130
160
190
!20
120
140

'H

11/495

,.

10ml0 45

160
190

1(

220

10mlD 375

160

10

1(

12(
6(

Dynamic 1M-b

CMOS

7(
80
100
1048576 x 1 120

110

80

160

10
12

190
20
160

8(

HM511ooG-IOS
HM5111lOO-12S
HM511000A-I0
HM511OO0A-12
IM511000ALP-8
IM511000ALP-I0
IM511000ALP-12
lMO 11UWAUP-8
lMO IlUWAUP-I0
MOll

IVlOII

11-0:

MOil

11-1

IH
IH

511

iO

11/495
11/440

+5

11I31l3

190
!20

DC

gO

8C

20
60

DC

90

11/3113
;9
)3

59
10m/0.35
10m/0375

I:

Ui385
80
100
I:!O

IP_'?

'0
,0

IA-8
IA-I0
IA-12
-ll

I.
I.
I.

171330
1.71275
17/385
17/330
1.71275

11
'20
25
40

10mlO.45

00
20

81

160

101
12(

220

5()
~O

•

•

•

•

IOmfO.35

50

I.

35
35

651

i96

e-

I.

11
11

•

.-.-

.-.-

••
••

•

. -.
•

••

11

.-.
...
· ...•
•

•

•

•
••

••
.••

•

•••

I.
,.

I.
I.

I.
I.

,.

I.

I.

··• .-.

••
••

737

••
•

i2

17
17

.-.-

I..
.
· -. -.
I.

60

11
12(
81
10
81

18

••

6

190

7
81

816
(continued)

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

xvii

QUICK REFERENCE GUIDE - - - - - - - - - - - - - - - - - - - - - - - - - -

• MOSRAM
Mode

Total

Type No

Process

Organization
(word x bit)

I~cess
Time
(ns)
Max

Cycle
Time S,pply
(ns) V"..,.
Max
IV)

Power

Dissipation
(W)

Package .,

~lpm~NO~GP~I~
FPI s~pl~
zprCG~1cP~I~
JPM----j
I_
Ie

1

2A-l0
2A-12
JP-35R

lM-b~~llj
~M
;7A?'i

'_0'

CMOS

Bi-CMOS

11,048,576 (1~1~~1'

lMxl

HM574251 P-4(

HM'i141r
HM51410~10

4,194,304 x 1

HM5141oo-12

40
45
35
4C
45
80

MWIO 144VV- IV
MIVlOI44UU-I

4M-b HM514101-8
HM514101-10
HM5141C ·12

CMOS

MIVIO 14IV£-O
MIVlOI4IV£-lU

HM514102-12

Ie

5V

~--~~~8iCO~15~;CO~
100 180
A 1
12C 21C
~,194,304xl 80 150
100 180
~__-----j~1~20~2~100~
80 150
1,048,576:4 100 180

HB56A19-10S
1048576 x 9

HB56A19-10A
nooo" ,~-,£"

DRAM
Module

HB56C18-10
HB56C18-12
HB56C18AT-8A
HB56C18AT-l0A

1048576x8
CMOS

MOOO" '_0'" - 1£"

HB56C19-8
HB56C19-1O
HB56C19-12
HB56C 19AT-8A
HB56C 19AT-l0A

1048576x9

MOOO" I~"I-I'"

~A_A,

262,144 x 8

~'1-10A

-lUll

1-12A

262,144 x 9

210
180
210
180
210
190
220
560
A80
400
830
190
220
630
540
450
180
160
132
110
94
202
170
144

llm/.385

llm1.~5
11 m/.44

I-

I-

l1m/.44

I_
I-

03
803

I_

816
816
855
855
855

I_
I_
I_

I_
883
I_
883
I_
883
I_
883
r.883
I_
I_
I_
I_

20ml14
20

883
883
883
883

I_
I_
I_
I_
I_
I_
I_

963
963
854
854
958
831
831

~~-4-+-+-+-+~Ie~aIT~_
_ 831

5V
20m/1.6

I_

843

_

843

_

843

20m/1.8

837
837

88/3.08
88/2.6A

88/220'
99/3465

_

849

_

849

_

849

_

96i

I_
I_
I_

967
967
967

22m12.0
9913465
99/2970

99/2475
22/990

221880
221726
22/605
22/517
331
33/94
33/.79

.HITACHI
xviii

:16
:16
i16

Ie
Ie

012/2.42
0.135/2
55
0.135/2.16
60m/18

;~ ~~~
120
100
120
100
120
100
120
80
100
120
80
100
120
80
100
120
60
70
80
100
120
85
100
120

11 ml 495
11 mI 44

llm/.385
0.12/2.42

262144 x 9 150 260
~__~~1~0ICO~18~CO~
100 180
1048576 x 8

-----

r_

Tj mTS5

1m1.385
llm/.495
11 m/.44
11m1.385
11 mI 495

HIR'ifi1nllOSllL1-~'i~-=~
150 260
NMOS 1------+-=-120-t~
21CO-l

HB56A 18-1OS

I-

1;:3~~

14C ISV-5
150
180
210

Page

lW

11 ml 495

__-+__~H~M5144~10~=__12~----~----~1=_20~1~10
HR'ifi11lOSl_1'
262144 x 8 120 110

~

r.

I_

I_

~~~ ~~~

7C
80
1,048,576 (4 100
120

Dynami(

80
85
70
8C
85
150

lOm/0.45

I_
Ie

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

I_
I_

979
979
(continued)

- - - - - - - - - - - - - - - - - - - - - - - - - - - QUICK REFERENCE GUIDE

• MOSRAM
Mode

Total

Type No
I_R~A

85
10
120
85
262,144 x36 100
120
85
524,288x36 1011
120

262,144 x 9

I-lOA
-12A

I HB56D5

-IU
2
6B-1

I HB56M

DRAM
Module

MtlOOM~-IU

lA1?cess
Time
(ns)
Max

Organization
(word x bit)

Process

CMOS

1

4,1

1

4,1

,9

80
100
120

,8

80
100
120
80
100
120
80
100
120

no_"''''~"-,£

I HB56A48-8
I HB56A48-10
4M-b ~6~48:!2

1,045,576
36

I HB56D136-12

2,097,152
x36

~R<;~n?~~_1?

Cycle
Time
(ns)
Max

Supply
Voltage

(VI

202
176
144
160
90
20

Power
DIssipation
(W)

Package "
IpmN'

Page

G P fP SP I ZP I CG ' CP JP

M

•
••
••

33/1
3~.!l~

30

33/.79
126/4.24

252/4.58
252/3.91
911
20
252/3.36
160
99mJ4455
190
99m/3.96
220
99m/4405
5V
160
88m/396
190
88m/3.52
88m/3.08
220
160
126m/5.25
190
126m/4.62
220 5V 126mJ3.99
160 1±5Ok 252m/5.57
252m/4.94
190
220
252m/4.31

•
•
•
•
•
••
•
••
••
•
_.••

72

30

72

979
979
979
991
991
991003
1003
1003
1027
1027
1027
1015
1015
1015
1039
1039
1039
1049
1049
lQ49

• MOSROM
Program

Total
Bit
256k-b

Type No.

Process

I HN623257
I HN623258
I HN6233P

Organlza~on

(word x bit)

Access
Time
(ns)
Max
150
200
120
150
200
120
200
120
150
150
200
150
200
150
200

32768x8

I HN62321
lM-b

2M-b
Mask

4M-b

I HN62321B
I HN62331E'3
I HN62321E
I HN62331A'3
I HN62321A
IHN62422'3
I HN62412
I HN62424'3
I HN62404
I M"OL~L4tl'
I HN62304B

131072x8

CMOS

524288x8
262144 x 16
or 524288x8
512Kx8
512Kx!j
256 x 16

HN62414
I HN62314
HN62444

BM-b

131072 x 16
or 262144 x 8
262144 x 16
or 524288 x 8

~OQl1ZO

Power
Dissipation
(W)

Package "
PION,

Page

G P FP

••
•
••
•• •

-~

28

32
40/44
5+

5,,/01
401

32

200/170
200/170
1QO
100

40
44148
32
40
44/48

200

42/44

o~~~~~68

HN62408'3

Supply
Voltage
(V)

•
••
••
••
••
•• _.
•
• ••
••
•
••
•
•
•
••
•
•

.

! •
,

! •

1060
1063
1069
1066
1077
1077
1077
1069
1080
1083
1083
1087
1087
1091
1091
1101
1101
1107
1095
1095
1114

(continued)

o

HITACHI

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

xix

QUICK REFERENCE GUIDE

• MOSROM
Program

Total
Bit

Type No.

Process

HN62308B
Electrically
Erasable &
Programmable

16M-b

256k-b

256k-b

UV Erasable
& Electrically
Programmable

512k-b

1M-b

256k-b
512k-b
One Time
Electrically
Programmable
1M-b

HN58C65-25
HN58C66-25
HN58C256-20'4
HN27C256A-10'3
HN27C256A-12'3
HN27C256A-15'3
HN27C256H-70
HN27C256H-85
HN27512-25
HN27512-30
HN27C1024H-85
HN27C1024H-10
HN27C101-17
HN27C101-20
HN27C101-25
HN27C301-17
HN27C301-20
HN27C301-25
HN27C256-25T
HN27C256-30T
HN27512-25
HN27512-30
HN27C101-20
HN27C101-25
HN27C301-20
HN27C301-25

8192 x8

CMOS
32768 x 8

NMOS

65536 x 8
65536 x 16

CMOS

131072x8

32768 x 8
NMOS

65536 x 8

131072 x 8
CMOS

HN27C101-AG

128kx 8

HN27C4096

256kx 16

•
xx

Access
Time
(ns)
Max

1Mx8
1Mx8
512Kx 16
1048576 x 16
or 20978152 x 8

HN66403P
HN624016'3

64k-b

Organization
(word x bit)

Supply
Voltage
(V)

Power
Dissipation
rN)

200

Package "
Pin No

G

5,,10.1

42

200
250
250
200
100
120
150
70
85
250
300
85
100
170
200
250
170
200
250
250
300
250
300
200
250
200
250
15/12/10
15/12
12/12110
12115

2m/20m

05,,10.1

28

015
50m/0 2
02

40

05,,10.1

32

+5

o5,,/50m
50m/0 2

32
05",01
40
44

Page
FP

••

32

250

P

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
••
••
••

•
•
•
•
•
•
•
••
•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

•
•
•
•
•
•
•

1119
1123
1127
1138
1147
1156
1158
1158
1158
1166
1166
1176
1176
1183
1183
1192
1192
1192
1200
1200
1200
1209
1209
1215
1215
1222
1222
1229
1229
1237
1237
1247
1247

- - - - - - - - - - - - - - - - - - - - - - - - - - - QUICK REFERENCE GUIDE

• ECLRAM
level

Total
Bit

64k-b
ECl10K
256k-b

64k-b

256k-b
ECL100K

64k-b

Type No
HM10494-1O
HM10494-12
HM10490-10
HM10490-12
HM10504-10
HM10504-12
HM10500-15'3
HM100494-10'4
HM100494-12'4
HM100490-10
HM100490-12
HM100490-15
HM100504F-10
HM100504F-12
HM100500-18'3
HM101494-10
HM101494-12
HM101490-10
HM101490-12
HM101504-10
HM101504-12
HM101500-15'3

Organization
(word x bit)

Output

16384x4
65536-1

Open

65536x4
262144 x 1
16384x4
65536 x 1
65536x4
262144 x 1

Emitter

16384x4

65536 x 1

Access
Time
(ns)
Max

10
12
10
12
10
12
15
10
12
15
20
10
12
18
10
12
10
12
10
12

Supply
Voltage

Power
DIssipation

(V)

(W)

08
-52

57
50
052
065

-45

057
50
05
75

-52

.57

,50

Package "
Pm No

G

F

Page
CG

••
••
22 • •
••
•
28
•
24 •
28 • •
••
••
22 • •
••
•
28
•
24/28 • • •
28 • •
••
22 • •
••
•
•
24

JP

28

•

•
•
•
•
•

1258
1258
1263
1263
1267
1267
1269
1273
1273
1277
1277
1277
1281
1281
1282
1285
1285
1289
1289
1293
1293
1294

Notes) '1 The package codes of G, F and CG and apphed to the package matenal as foIl17NS
G, cerdlp, F, F~t Package, 00, Ceramic leadless Cilp Garner
'2 Maintenance Only This dO\l1ce IS not "",,'ab'e for new apphcabon
·3 Preliminary
'4 Under Development

~HITACHI
Hitachi Amenca, Ltd, • Httachi Plaza • 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300

xxi

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

Package Information

~HITACHI®

• PACKAGE INFORMATION
e Dual-in-line Plastic

Unit: mm (inch) Scale 1/1

eDP-16B

eDP-18B
192(0756)
2032max

~

(OaGOma.)

9/

~~:::::Jll~:~
ill I-!- _ _

~/.m

(0035)

(0051)

~ ~

•

~

22.0(0866)

18 2Z16max to loom.x) 10

~~d

762
/(0300)1

~h~
i ~e \\02~'!:"
o

~ ~
e

254±025
048101
(0100'0010) (0019+0004)

0"~J5'

)
~O\O:~o;

'-rr,....,TT"rTTtT[:n:ln:r'~e - e
I

13(0.051)

_

~l:i

048±01
254±025(0019±OOO4) (0100±0010)

eOP-20N

eOP-18C

2540max
(I OOOma»

2226(0876)

-;:;r~
Ltt-trt""'-c"1E:M:I"V"C'"Ir-.:le

---'.JW

9
(003S)

ul~ = -~ =-i

(0051)

!-lli~2

os.
~~
r~

",e

2S4:t025

(0100 ± 0 010)

-L

048101
(0019' 0004)

~~e.

eOP-22N

eOP-20NA

2708(1066)
21 9Oma•.( I 098max)
12

~~

U8±O I
(0019±0004)

•
2

162
(0300)

254±025
(OIOO±OOIO)

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

--------------------------------------------------------PACKAGEINFORMATION
e Dual-in-line Plastic

Unit: mm (inch) Scale 1/1

eOP-22NB

eOP-24

31 6( I 244)

1"24

27 90max (I 098max)

.t::::;:.:[:U

088(0035)

II~

-I (~~47)

762
(0300)

12

o25~% ~\

to O\O~U~~)

~~~~

-U--

13!

OJ

I 3(0051)

~!!

32 Srr.ax (I 2S0max)

.e

Q48±OI

254±025

(0019±0004)

(0100±0010)

eOP-24A

eOP-24N

r

_~~1) __
31 75madl 250ma,)

c::::: ::jl~l!

10~-l.~
(0043)

1

12

13

(0 OSI)

eOP-24NC

29.88(1 176)
30 48max (I 2QOrnax )

24

13

o

~

I 14(0045)

762
(0300)

~!jil--l~l
~.E'E-~
-

-----L
048±O I

(OOI9±0004)

254±025
(OIOOtOOIO)

,,-

~~

~~

..... .9. 0'"

~~

~ ~
3:X g

IS'

N.e
@HITACHI

Hitachi Amenca, Ltd • Hitachi Plaza. 2000 Sierra POint Pkwy • Bnsbane, CA 94005-1819 • (415) 589-8300

3

PACKAGEINFORMATION-----------------------------------------------------Unit: mm (inch) Scale 1/1

e Dual-in-line Plastic
• DP-28

eOP-28N
360(1417)

:: ::: ::::::::
~[1~ I
-1-1_
I

14

-

I 30(0051)

wmwmwmi
-L
D48±OI

(0019±0004)

~:.

254±025

COg

~.e.

(0100±0010)

eOP-32

•
4

HITACHI

Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

------------------------------------------------------PACKAGEINFORMATION
Unit. mm (inch) Scale 1/1

e Dual-in-line Plastic
eOP-42
528(2019)

53 7m," (2 II.mlx)

~n

.-

22

M

u~

...................................................... ""' ........................ _

~

~(00.1)

21

1524
(0600)

~li
.

09.

254+025
fiilOO+oolO)

on g

~5
:;;~

048+01

~i9+0004)

r.,-

eo'

Applicable ICs
Dp·16B

HM50236P

Dp-18B

IIM50464P Sene,. IIM50465P Sene,

Dp-18C
DP-20N
Dp-20NA
DP-22N
DP-22NB

Sene~.

1I:vI50257P Sene~. HM51236P Sene!., H:\r151256LP

Sene~,

HM3125HP Sene..,

IIM53051P. IIM511000AP Senes. IIM511000SP Senes. IIM511000HP Senes. IIM51100lAP Senes. IIM51l00lSp Sene,.
IIM511002AP Senes, HM511002SP Sene,
IIM6l6811P Senes, I!M6l6811LP Sene" IIM62b8P Senes, IIM6268LP Senes IIM6167P Sene" Wvlbl67LP Senes,
IIM6l671!P Senes, IIM6l67l1Ll' Sene" HM6267P Senes, IIM6267LP Sene,
IIM5l4256P Sene" I!M5l4256AP Sene" I!M:J14256SP Sene" I!M5l425611P Senes, IIM5l4258l1LP Senes,
IIM514258SP Senes
IIM6287P Senes, IIM6287LP Senes
IIM6288P Senes, HM6288LP Sene" IIM6788P Senes, IIM6788l1P Sene" IIM628711P Senes, IIM628711LP Senes,
IIM6787P Sene" IIM678711P Sene,

DP-24

IIM61l6P Senes, IIM61l6LP Senes, IIM61l6Ap Sene" IIM6116ALP Sen.,

DP-24A

IIM5346lP Senes. IIM53462P Senes

DP-24N
DP-24NC

HM6116ASP Series, HM6116ALSp Senes
I!M6716P Senes, HM6719P Sene" IIM6789P Senes, IIM6789l1P Senes, I!M6208P Senes, llM6208LP Senes, IIM6208l1P Sene,.
llM6208I1LP Senes, HM6708P Senes, llM6207P Senes, HM6207LP Senes, HM6207llP Senes, HM6207HLP Senes, HM6707P Sene.
HM6264P Senes, HM6264LP Sene" llM6264LP-L Senes, HM6264AP Senes, HM6264ALP Senes, HM6264ALP-L Senes,

Dp-28

IIM62256P Senes, IIM62256LP Senes, IIM62256LP-L Senes, HM65256AP Senes, HM65256BP Senes, HM65256BLP Senes,
IIN623257p, IIN623258P, IIN6232lP, HN6232lBP, HN62331P, IIN62321EP, IIN6233lEP, HN6232lAP, IIN6233lAP, IIN58064P.
HN58C66P, HN58C256P, IIN27128AP, IIN27256P, HN275l2P

DP-28N
Dp-32

HM6264ASP Senes, HM6264ALSP Senes, I!M6264ALSP-L Senes, IIM65256ASI' Senes, IIM65256BSP Senes,
I1M65256BLSp Senes, HM630211' Senes
HM628l28p Senes, HM628128LP Senes, IIM658128DP Senes, IIM65256ASP Sene" HM65256BSP Senes,
IIN27C101P Senes, IIN27C30lP Senes

DP-40

HN624l2p, IIN62422P, IIN62404P, HN62424P

DI'-42

HN624081', HN6240l6P

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300

5

PACKAGE I N F O R M A T I O N - - - - - - - - - - - - - - - - - - - - - - - - - - - -

e

CERDIP

Unit: mm (inch) Scale 1/1

~

eOG-20N
25 16(0.991)

eOG-22N

.

III

120

r==lJ~

~
(0040)

(0061)

~

"~
-

Hd
~

.

2541025
(OIOO:1'OOIO)

762

~

t.O.8

=~E

~

~0300)

1L

048tOI
(OOI9:t0004)

--

~!~

.. 0 \ \

~!.

~ ~
.e

~2:~~~:c~~)

048±OI
(0 019±0 004)

\0

0"'15'

:::e

2S4±025
(0100±0010)

eOG-24V

eOG-28

3683

t::::B:::JJ
I

---J ~2

14

~

(0052)

--.

.!('~I

1524
(0600)

I

b~!H!F\~
--~
2S~~~~
254 ±O 25
(OIOO±OOIO)

-L-

048±OI
(OOI9±0004)

~g

.

~;;O-IS'

°:;)

0
10..
tOO-o

N--

eOG-28N

~lU
c:::>;

048±OI

254±OZS

(0019±0004)

(OIOO±OOIO)

e

~HITACHI
6

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 • (415) 589-8300

------------------------------------------------------PACKAGEINFORMAT~N

e CERDIP

Unit: mm linch) Scale 1/1

eOG·32

11

32

r~2J

o

1524
10600)

16

eOG·40A

Z S4max
(0 100max)

Applicable ICs
IJG·20N

HM10480·15, HMlOO480·15

IJG·22N

HMI0490·15, HMlO0490 Senes

IJG·24V

HMI0500·15
HN27128AG Senes, HN27256G Senes, HN27C256G Senes, HN27C256AG Senes, HN27C256HG Senes,

IJG·28

HN27512G Senes

DG·28N

HMI0494 Senes, HMI00494 Senes

DG·32

HN27ClOIG Senes, HN27C301G Senes

IJG·4OA

HN27Cl024HG Senes

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005· 1819. (415) 589-8300

7

PACKAGEINFORMAnoN-----------------------------------------------------e Zigzag-in-line Plastic

Unit: mm (Inch) Scale 1/1

eZP-16

eZP-20

..

20 13(0 793)

IT065in.X(0813m..

~~

r'i!!II~ ';,~s
~

8 .......

16

~

~nTmrnmnrnTnm

0'1:01
(OOI9tOOOt)

1117(0050)]

c

~ E -

OlS~U'

(OOI~UUl
~

=L

"'l;!

",r:J~

!Yi?S6YvY'il.J::: ~

eZP-24

eZP-28

I
I

I

3558(1 '01)
36 57max (I .40malC)

-

~mmmmmnmllm~281]
II

~::::

(0 020~g gg~)

!'

Ii

I

1 27(0050) I

n n n n n n n n n n

_U Q Q Q

Q

UQ

U U

3

n

I--t.::l~

U g Q U t~8

Applicable ICs
ZP-16

HM50256ZP Senes, HM50257ZP Senes, HM51256ZP Senes, HM51256LZP Senes

ZI'-20

HM514258SZP Senes, HM511000AZP Senes, HM511000SZP Senes, HM511000HZP Senes, HM511001AZP Senes,

HM514256ZP Senes, HM514256AZP SerieS, HM514256SZP Senes, HM514256HZP Senes, HM514258AZP Senes
HM511001SZP Senes, HM511002AZP Senes, HM511002SZP Series
ZP-24

HM53461ZP Senes, HM53462ZP Senes

ZP-28

HM534251ZP Senes, HM534252ZP Senes, HM534253ZP Senes

*

HITACHI

8

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819. (415) 589-8300

------------------------------------------------------PACKAGEINFORMATION
e Flat Package

Unit mm (inch) Scale 1 Y,

eFP-24D

eFP-28D

1580(0622)

O· -10'

162ImaK(0638maK)

1":.\
~
a;

0H

.n

~~ ~ ~

o 17+g g,
(O-007± 0003)

-

o40~g A~

(0 016~g gg;)

eFP-28DA

1830(0

W

no)

O' - 10'

-v--

0;;;

Oi

~

0

0

0

e

~:2

8

...

+<

=8

~

~1"18'
(0007 ±O DOl)

eFP-44A

172±03(0677±0012)
14 010 551)

~nnnnnl{

"

o ___ 34

~:g
~

1

I;

290(0 114)max

1

o

1(0 004)

(STAND OFF

f=1

0

~o

~ ~ 44

12

N

e E:
~ ~~

~

I

UUUUUUI I

0,!5++ 0 05 111+1015(0 006)MI
(0 0 _0 002)

I

OI5±005

~IL' I

10 006±0 002)

I I,
Ill!

~ Ilf~[ ~Ii

I . II
'JL ~~ _

L~=~:"--....

(0 031)
_________

~

1013 ±005

10_~. IIO~59~~~~~

o43±OI

127±02

(OOI7±0004)

(0050±0008)

._ _ _ 10037±0007)
235maK

______._ _ _ _ _ _ _---'
(0 093max)

~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Bnsbane, CA 94005-1819 • (415) 589-8300

9

PACKAGE I N F O R M A T I O N I - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• Flat Packages (continued)
• FG-24A

• FG-28D

Applicable les
FP-24D
Senes, 1l:vJ6116LFI' Sene,
- - f1l1Vl6116FI'
---- - - - - - - - - - - - - - - - - - -______---c____: - : - : _ _ - - . - - - - - - - - - FP-2BD

1l~16264FI'

Senes, IlM6264LFI' Sene>, 1l\16264LFI'·L Senes, 1l\'16264AFP Senes, HM6261ALFI' Sene,

1l1Vl6264ALFp·L Senes, HN58C6jFP Sene" IIN38C66FI' Senr_'s_,._1l._N_·:,_RC.'.Z_3_6_F_P_S_e_n_es_ _ _ _._ _ _ _ _ _ _ _ _ _ _ _ __
IlM6264FI' Senes, HM6264LFP Senes, IIM6264LFI'·L Sene" ILvlliZ64AFP Senes, HM6264ALFP Senes
FP·28IlA

IIM6264ALFP-L Senes, HM62256FP Senes. JI:v162Z::i6LFP Sene'>, 1J:\i1622:J6SLFP Senes, HM652:)6BFP Senec-"
IllVl63256BLFP Senes, IIN623257F, IIN62:1Z5RF, IlN62:121F, IIN62:11111F, HN62:l31F, llN62321EF, IINb233IEF, HN38C65FI',
IIN58C66FI', HN58C256FP, IlN27C256FP
IIlV1628128FP Senes,

FI'·321l

1l~1628128LFP

Senes, 1I'I165812HllFP Sene" 1I'I1658128LFP Serw" IIN62:l2IAF,

HN62:13IAF, HN623()4HF llN623241lF, IlN27CI()IFI', IIN27C:1()IFI'

---+---------------------------_._--------_._---HN62412FI', IIN62422FP, 1Ir-.i62404FP, IIN62:_24_F_P_,_1I_N~.4_08_F_P_ _ _. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Fp·44A
H;·20D

HMI0150U~·I'

FG-24A

HMIOI5WF-15

FG-28D

HM l0049F Senes

• TSOP Packages
• TFP·32DA

• TFP-32D

8,0(0.315)
32

17

8.0(0.315)

0.20'0.10

O.50!O.10
(0.02o,o.004)
20.0'0.2(0.787<0.008)

0.50'0.10
(0.020'0.004)
14.0:tO.Z
(0.551'0.008)

~HITACHI
10

Hitachi AmerIca, Ltd • Hitachi Plaza' 2000 SIerra Pomt Pkwy' BrIsbane, CA 94005-1819· (415) 589-8300

------------------------------------------------------PP.ACKAGEINFORMAnON
• Leadless Chip Carrier
• CG-28

• CG-22A

• CG-288

• CG-28A

~

I
I

635±02(025±0008)

~i[ I,.,,'" 1~
! I r[jj""i]ij"n
14

g

,

2Z±025

IUH03

N

--t--

0024)

~;'!I

0 00

20

13

n

(0 08l±0 010)

719(0283)

86~:15

21

(0339~~

I UUUUUUII

10

• Flat Package (J-bend Leads)
• CP-20D

• CP-18

I~

~

~~~~
L§2J.,

(0 094~:::)

169(0665)

20 17 21max (0 610max )

I; ~

)

N

o 63mm (0 02Smln )
II

j ~

I

d-

10

074(0029) ~_t~O
______________

IDfOTiO]OO]
(SEATING PlANE:)

~

OO±O 10

[I

mooso!

fI+i

fil :0:
~

...

-

(0017±000')

• CP-280

• CP-24D

(0094~:=

IS 63(0 61S)

16 OOmax

2'

)

o 63mall

o63mm
13

(0 02Smm )

]-!I
; ti
~ :

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra POint Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300

11

PACKAGE INFORMATION - - - - - - - - - - - - - - - - - - - - - - - - - Umt: mm (inch) Scale 1%

• Flat Packages (J-Bend Leads) (continued)

• CP-40D

• CP-32D

• CP-44

Applicable ICs
CG-22A

HM6787CG Senes, HMlO0490CG Sene,

CG-28

HMI0490CG-15

CG-28A

HM2144CG Senes, HMI04ROCG-13 HM 10l5WCG-15

CG-28B

HMI00500CG-18

CP-18

HM50464CP Senes, HM50256CI' Sene., IIM50257CP Senes, HM51256CP Senes, HM51256LCP Sene,
HM514256JP Senes, HM514256AJP, IIM514256SJP Sene,. HM514256HJP Sene" IIM514258AJP Senes, HM514258SJI' Senes,

CP-20D

HM511000AJP Senes, IIM511000SJP Sene" HM5110001!)P Senes, IIM511001AJP Sene" IIM511001SJP Senes,
HM511002AJP Senes, HM511002SJP Senes
HM6288JP Senes, HM6288LJP Senes. HM6289JP Senes, HM6289LJP Senes, IIM6789JP Senes, HM6789HJP Senes, HM6287HJP

CP-24D

Senes, HM6287HLJP Senes, HM6787HJP Senes, HM6208l1JP Senes, HM6208HLJP Senes, HM6708JP Senes, HM6207HJP Senes,
HM6207HLJP Senes, lIM6707JP Senes,

CP-28D

HM624256JP Senes, HM53425IJP Senes. IIM534252JP Senes, IIM534253JP Senes

CP-32D

HM624257JP Senes, HM624257LJP Senes

CP-40D

HM53812IJP Senes, IIM538122JI' Senes, IIM538123JP Senes

CP-44

HM67C932 Senes

CP-52

HM62A168 Senes, HM62A188 Senes

.HITACHI
12

Hitachi Amenca, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy • Bnsbane, CA 94005-1819 • (415) 589-8300

• RELIABILITY OF HITACHI IC MEMORIES
1. STRUCTURE
IC memories are basically classified into bipolar
type and MOS type and utilized effectively by their
characteristics. The characteristic of bipolar memories is high speed but small capacity, instead, MOS
memories have large capacity. There are also differences in circuit design, layout pattern, degree of
integration, and manufacturing process. These
memories have been produced with the standardized
concept of design and inspection all through the

processes of designing, manufacturing and inspection.
IC memories are constituted by the unit patterns
called cells, which are integrated in high density.
The knowhows based on our experience have been
applied in every production stage. In addition, reliability has been ensured using TEG (Test Element
Group) evaluation. Examples of cell circuits of
bipolar and MOS memories are shown in Table 1.

• Table 1 Basic Cell Circuit of IC Memories
Classification

Bipolar memory
(RAM)

Application

control memory

Buffer memory,
of high-speed

NMOS memory
(PROM)

NMOS memory
(Dynamic RAM)

Bipolar memory
(PROM)

Main memory of computer,

Microcomputer
control use

microcomputer memory

computer

For
microcomputer

control

Example of
basic cell
circuit

Dies of IC memories are produced in various packages. In this process of packaging, Hitachi has also
innovated new techniques and ensured to high level.
As packages for IC memories, cerdip (glass-sealed)
packages and plastic packages are currently used.
Also such packages as LCC (Leadless Chip Carrier)
or SOP (Small Outline Package) have been developed for high density packaging. Cerdip packages
sealed hermetically are suitable for equipment requiring high reliability. Plastic packages are widely
applied to many kinds of equipment. Hitachi
plastic packages have been improved the reliability

level as highly as that of the hermetically sealed
packages. Table 2 shows the outlines of the Hitachi
packages.

• Table 2 IC Memory Package Outline
• Cerdip

.16 pin

.18 Pin

.20 Pin

•

.24 Pin

HITACHI

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819' (415) 589-8300

13

Reliability of Hitachi

Ie M e m o r i e s ' - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ __

• Cerdip (continued)

- 28 Pin with lid

- 32 Pin with Ud

- Plastic DIP

-16 Pin

- 18 Pin

- 20 Pin

-24 Pin

-28 Pin

-28 Pin

- Leadless Chip Carrier
.20 Pin

•

22 Pin

.24 Pin

•
-sop
.24 Pin

.28/32 Pin

- PLCC
.18 Pin

-SOJ
• 20/26/28/32 Pin

~HITACHI
14

Hitachi Amenca, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, GA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - R e l i a b i l i t y of Hitachi IC Memories

2. RELIABILITY
Results of reliability tests are listed below.
ty control, there is no difference in reliability
among the various types. And the larger the capac·
ity is, the higher the reliability per bit becomes.

2.1 Reliability Test Data on Bipolar Memories
The reliability test data on the bipolar memories are
shown in Table 3 and 4. Since they are manufac·
tured under the standardized design rules and quali·

• Table 3 Results on Bipolar Memory Reliability Test (1)
HM10480·15
Test item

Test
condition

Hightemperature
(Operating)

Ta=125°C
VEE=-5.2V

High-temp
storage

Ta=200°C

HM2144CG
Total
FailSam- component
pIes
ures
hours

Total
FailSam- component
ures
pIes
hours

Failure
rate*
(l/hr)

Test
condition

340

C.H.
3.4x10'

0

11h
2.7x10-·

Ta=125°C
VEE=-5.2V

120

351

3.51x10'

0

2.6xI0-'

Ta=200°C

120

c.H.
1.2xlO'
1.2x10'

Failure
rate*
(l/hr)

0

11h
7.7x10-·

a

7.7x10-·

• Confidence level 60%

• Table 4 Results on Bipolar Memory Reliability Test (2)
Test item

HM10480-15

Test condition

HM2144CG

Samples

Failure

Samples

160

0

180

Failures
0

0

22

0

Temperature cycling

_55°C to +150°C, 10 cycle

Soldering heat

260°C, 10 seconds

35

Thermal shock

O°C to +lOO°C, 10 cycles

50

0

50

0

Mechanical shock

1500G, a.5ms, Three times each for X,
YandZ

30

0

22

0

Variahle frequency

100 to 200 Hz, 20G, Three times each
for X, Y and Z

40

0

22

0

Constant-acceleration

20000G, 1 minute, each for X, Y and Z

40

0

22

0

2.2 Reliability test data on Hi-BiCMOS memory
Hi-BiCMOS memory is newly designed based on the
latest fine machining technologies (2m ~ 1ml.
which features low electric consumption / high
integrity by CMOS and high speed / high drivability
by bipolar. This device also attains high speed close
to Eel and low electric consumption as CMOS.
Input and output level supports both ECl and TTL.
Reliability test data of HM100490-15 (64k-words x
1-bit) and HM6788P-25 (16k-words x 4-bits) are

listed in table 5 and table 6.
The above shows the sufficient reliability of high
speed Hi-BiCMOS in the normal use with some
limitations considered from its own circuit composition. For further information, see each data
sheet. Besides the caution points with CMOS and
bipolar device, avoid abnormal use as in deformed
or slow wave form which causes malfunction and
latch up.

Table 5 Results on Hi-BiCMOS Memory Reliability Test (1)
-~~

Test item

.

HM100490-l5 (Cerdip)
Failure Test item
Total test
Test
Samples time Failures
rate
condition
High-

HM6788P-25 (Plastic)
Test
condition

test Failures
Samples Test
time

Failure
rate

tempera~

HightemperaTa = 125'C
ture
VEE~4.5V
pulse
operation

380

Hightemp.
storage

330

Ta=200'C

C.R.
3.8x1O'

3.3x1O'

0

0

Ta = 125'C
ture
VCC=5.0V
pulse
operallh
tion
2.4xlO-·
MOIsture 85'C 85%RH
endur5V
ance
3.0xI0-· Pressure 121°C100%RH
cooker

Remarks

*\

I/h
4_8xI0-' foreign
matter

420

c.R.
4.2xlO'

1*\

210

2.lxlO'

0

4.8xI0-·

80

0.16x1O'

0

6.3xI0-'

-

@HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

15

Reliability of Hitachi Ie M e m o r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - Table 6 Results on Hi-BiCMOS Memorv Reliability Test (2)

_55°C - -150°C 100 cycles

180

0

Soldering heat

250°C 10 seconds

22

0

Thermal shock

DoC - 100°C 10 cycles

50

Mechanical shock

1500G, 0.5ms Three times each
for X, Y and Z

Variable frequency

Temperature cycling

1

Samples

Failure

180

0

22

0

0

50

0

22

0

-

-

100 - 200Hz, 20G Three times each
for X, Y and Z

22

0

-

-

20000G, I minute, each
for X, Y and Z

22

0

-

-

~-

-

HM6788P-25 (Plastic)

HMlO0490-15 (Cerdip)
Failure
Samples

Test condition

Test item

Constant acceleration

The life test is performed at high temperature and
high voltage to evaluate the reliability of products
using fewer samples. All failures are caused in
manufacturing process, so we feedback the data into
manufacturing process to improve the quality and
reliability.

2.3
Reliability test data on MOS memories
2.3.1 Reliability test data on MOS DRAM and
SRAM
Table 7 and table 8 shows the reliability test data on
the representative types of 1M DRAM (HM511000/
HM514256), 256k SRAM (HM62256) 1M SRAM
(HM628128FP) .
• Table 7 Reliability Data on 1M DRAM

Test item

Hightemperature
pulse operation

Test
condition

HM511000P/HM514256P
Series (D IP)
Failure
FailSamTotal
rate*
pies test time ures
(l/hr)

HM511000JP/HM514256JP
Series (SOP)
Failure
Total
FailSamrate*
pies total time ures
(l/hr)

125°Cf5.5V

300

0

1.53 xl 0-'

200

4.00xlO'

0

2.30xlO"·

125°C/7V

1252 4.50xlO'

1*

4.48xI0'" 3186

9.34xI0'

0

9.85xI0- 7

200 4.00xlO'

0

2.30xI0-·

200

4.00xlO'

0

2.30xI0-·

150"C/7V

6.00xlO'

Moisture
endurance

85°C 85% RH 420
5.5V

8.40xI0'

0

1.10xI0-·

682

1.36x10·

0

6.74xI0- 7

Pressure
cooker

121°C/IOO%
RH

4.50xlO·

0

2.04xI0-'

200

6.00xI0'

0

1.53xIO"'

150

Remarks

*1
Oxide film
Failure xl

* ConfIdence level 60%

• Table 8. Reliability Data on 256K and 1M SRAM
HM62256FP (SOP)
Test item

Test
condition

Sampies

Total
test time

Failures

Failure
rate*
(l/hr)

HM628128FP (SOP)
Failure
Failrate'
ures
(I/hr)

SamTotal
pies total time

Hightemperature
pulse operation

3088 3.11xIO·

0

8.88xIO- 7 1038

1.04xIO'

0

8.86xI0- 7

125°C/7V

455 4.55xIO'

0

2.02xI0-·

951

5.33xIO·

1*'

3.79xI0-·

150°C/7V

103

1 *'

2.02xI0"'

80

1.60xlO'

0

5.75xI0-·

Moisture
endurance

85°C/85%
RH7V

680 6.80xI0'

0

1.35xIO-·

127

2.54xlO'

0

3.62xIO-·

Pressure
cooker

121°C/IOO%
RH

320 6.40xlO'

1*'

3.16xIO-'

90 2.70xIO·

0

3.4IxI0-'

125°Cf5.5V

1.00xl0'

Remarks

*1
Foreign x 2
*2 Leak x 1

, Confidence level 60%

~HITACHI
16

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - Reliability of Hitachi Ie Memories

2.3.2 Reliability Test Data on EPROM
EPROM has two types; conventional EPROM with
transparent window and one time programmable
ROM (OTPROM) packaged in plastic package. Table

9 shows reliability test data on the representative
EPROM
types
512k
EPROM
(HN27512,
HN27512Pl. 1M EPROM (HN27C101, HN27C301).

• Table 9. Reliability Data on 512K and 1M EPROM
Test
condition

Test item

Hightemperature
operation

HN27512 (Cerdip/Plastic)
Failure
Total
Failrate'
test time ures
(l/hr)

HN27CIOI/HN27C30I
Failure
Failrate*
ures
(l/hr)

Sampies

125°C/5.5V

200

3.72xIO'

0

2.47xI0- 6

180

3.24x1O'

0

2.84xI0- 6

125°C/7V

530

7.95x1O'

0

1.16x10-6

327

6.54x1O'

0

1.41xlO-6

150

7.5x1O'

0

1.23x10-6

Hightemperature
bake

175°C

260

4.91xlO'

0

1.87x10-6

200°C

240

3.72xIO'

250°C

180

1.89xlO'

Moisture
endurance

85°C/85%
RH 5.5V

290

'121°C/IOO%
RH

50

Pressure
cooker

Remarks

SamTotal
pies total time

I"

5.43xI0-

6

130

6.49x1O'

1*'

3.11xI0-6

7*'

4.44xI0-'

110

3.07x1O' 40*'

1.30x40-4

5.22xIO'

0

1.76xlo-6

-

-

-

-

O.IOxIO'

0

9.20xlO-'

-

-

-

-

*1
Data
dissipation x 49

Data of 512K
OTPROM

* Confidence level 60%.

The failure shown in table 9 is due to the data dissipation in memory cells. Getting thermal energy,
electrons in memory cells are activated and go
through the floating gate. In actual usage, however,
it has no problem because this phenomenon dependes on temperature (about 1.OeV of activated
energy) greatly. The moisture resistance of
OTPROM is also satisfactory .

Table 10 shows the example of PROM derating.
When derating, the parameter is generally only the
temperatu re because other operating cond itions are
specified. Especially to lower the junction temperature during mounting is important for stabilizing the
operation relative to access time, refresh time and
other characteristics.

• Table 10 Example of HN27C101/HN27C301 Derating
Factor
Failure criteria
Failure mechanism

Tern perature
Electrical Characteristics,
Function Test
Increase of leak current
and others

10'

10'

j

10'
~

Results:
The result from high temperature baking of PROM
is shown in the right figure.

,.~

10'

I

10'

/

j

10'

10'

/

~>;,>;,
1il

15

f

20

~

$-> So>

""'

~ 25~ ~

P

7 "~
30

35

103jT! ("K- 1 )

Note: Decreasing junction temperature shown in the figure will promise the ~her reliabilitli The junction temperature
can be calculated by a formula: Tj = Ta + 8jaOPd Bja in about 100°C with no air ow and about 60 to
700 CfW with 2.S mls air flow.

~HITACHI
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 • (415) 589-8300

17

Reliability of HitachllC M e m o r l e a - - - - - - - - - - - - - - - - - - - - - - - - - - - 2.3.3 Reliability Data on MASK ROM
Table 9 shows the reliability test data on 2M and
4M bit MASK ROM. MASK ROM is patterned ac-

cording to ROM information in manufacturing
process, so data dissipation isn't occurred in high
temperature like EPROM and EEPROM .

• Table 11. Reliability Data on 2M and 4M MASK ROM
HN62412P (Plastic)
Test
condition

Test item
High-temp.
pulse
operaton

125°C/5.5V
125°C/7V

Moisture
endurance
Pressure
cooker

85°C/85%
RH 5.5V
121°C/
100% RH

•

Sampies

Total
test time

HN62404P (Plastic)

Failure
rate·
(l/hr)

Failures

Sampies

Total
test time

Failures

Failure
rate·
(l/hr)

-

-

-

-

200

4.0xlOs

0

'1:~)l\()"'

120

1.2xlO s

0

7.67xI0-·

300

3.0x1O s

0

3.0xlO··

120

1.2x10 s

0

7.67xI0"

120

1.20x10'

0

7.67xI0"

4S

2.3xI0·

0

4.lxI0- s

45

2.3xI0·

0

4.lxI0- s

--

Remarks

Confidence level 60%.

2.3.4 Reliability Data on MOS Memory (The result
of environment test)
Table 12 shows examples of each environment test
data. They show good results without any failure
even in severe environment.
V TH of MOS transistor is one of the basic process

parameters in MOS memory, which has almost no
change using surface stabilization technology and
clean process. Figure 4 shows the examples of time
changes for 1M DRAM; V DD min. (V min ) and
access time (tRAC) in high temperature pulse test.

• Table 12 Reliability Data on MOS Memories
Test item

Temperature cycling
Temperature cycling
Thermal shock
Soldering heat
Mechanical shock
Variable frequency
Constant-acceleration

Test condition

HM511000P HMS11000JP HM622S6FP HM628128FP
(SOJ)
(SOP)
(SOP)
(DIP)

EPROM
(Cerdip)

Sam- Fail- Sam- Fail- Sam- Fail- Sam- Fail- Sam- Failpies
ure pies ures pies ures pies ures pies ures

-SSoC to 150°C
3755
10 cycle
-5SoC to ISO°C ISO
500 cycle
-65°C to ISO°C
77
15 cycle
260°C,
22
10 seconds
l,500G,O.Sms
100 to 2,OOOHz
20G
6000G
-

0

2786

0

3328

0

710

0

2790

0

0

200

0

482

0

lOS

0

450

0

0

100

0

76

0

77

0

80

0

0

22

0

22

0

22

0

22

0

-

-

-

-

0

-

-

-

-

-

-

38

-

38

0

-

-

-

-

-

-

-

38

0

2.4 Change of Electrical Characteristics on IC
Memory
The degradation of leBO and hFE are the main
factors of degradation in inner cell transistor of
bipolar memory. In actual element designing, how·

-

-

*6,OOOG

ever, it is designed to operate in the range at which
no degradation happen. Therefore no change of
characteristics including access time are observed.
Time dependence in access time for HM10470 are
shown in Fig. 1.

~HITACHI
18

Remarks

Hitachi America, Ltd • Hitachi Plaza· 2000 Sierra POint Pkwy· Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - R e l i a b i l i t y of Hitachi

Ie Memories

Figure 1 Time change in access time for bipolar memory

Example

Example of time change in access time for Bipolar memory

HMI0480-15

Device name
Test condition

To = 125°C, VEE = -5.2V

Failure criteria

tAA = 15ns

Failure mechanism

Surface degration

Test Condition
20

Results:
Access time is stabilized.

2

V,,=-5.2V
Ta=25'C

Maximum
Average
MinImum

Marching Pattern

-~
-

15

<
<

~

10

5

1-

I

a

I

iI

I

I

500

1,000

\

2,000

Time (hr 1

I
Figure 2 Time change in access time for Hi-BiCMOS memory

Example
Device name

HMIOO490

Test condition

To = 125°C, VEE = -4.5V
all bit scanning

Failure criteria

tAA = 15ns

Failure mechanism

Surface degradation

Example of time change in access time for Hi-Bi CMOS memory

Test CollditiOIl

20

2

V•• =-4.5V
Ta=e5'C

~".m",
l,\erage
\llmmum

\larclllng Panern

Results:
Access time is stabilized.

-;n
-5

15

c
c

10

~

5

t

I

a

I

I

1,000

500

T,,,,,,

I

\

2,000

hrl

@HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589·8300

19

Reliability of Hitachi M e m o r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - Figure 3 Time change in VCC min and tAA for Hi-BiCMOS memory

Examples of time change in Vee min and fAA for Hi-Bi CMOS
memory

Example
Device name

HM6788P-25

Test condition

Ta = 125°C, Vee = 5.0V
all bit scanning

Failure criteria

Vee = 4.5V, fAA = 25ns

Failure mechanism

Surface degradation

5

~

"
E

4

~

3

g 2 Test Condition

>

Results:
Both of Vee (min) and fAA are stabilized.

2Maximum

Average
1 Vc"-=5V
Ta-25"C
Minimum
Marching
Pattern
0
0

500

2,000

1,000

Time (he)
'30

Test Condition
Same as above

25

"'"

3

~

20

'15

:::
0

500

2,000

1,000

Time (he)
Figure 4 Time change in V DD min and tRAC for MOS memory

Example of time change in VDD min and tRAe for MOS memory

Example
Device name

HM511000P

Test condition

Ta =125°C, Vee = 7V
all bit scanning

Failure criteria

VDD = 4.5V, AVDD = l.OV

Failure mechanism

Surface degradation

S

4

E

Results:
Access time (tAA) is stabilized and is within the failure
criteria.

3

~

~

~

.~

~ 2 Test Condition
Marching pattern
r.=2s'C
I
N=200pcs

i

Maximum
Average
Minimum

0
0

110

500

Q

1,000
Time (hr)

.

2,000

Test Condition
Same as above

100

]
~
Note:

90
80

Test accuracy is O.2V, 2ns.
10

t t I I

60
0

500

1,000
Time (hr)

2,000

~HITACHI
20

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra POint Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - R e l i a b i l l t y of Hitachi Memories
2.5 Failure Mode Rate
Figure 5 and 6 show examples of failure mode
happened in users' application. Since IC memories
require the finest pattern process technology, the
percentage of failures, such as pinholes, defects on
photoresist and foreign materials, tends to increase.
To eliminate the defects in the manufacturing

Figure 5

Failure Mode Rate of Bipolar Memory

process, Hitachi has improved the process and
performed 100% burn in screening under high tem·
perature. Hitachi has been collecting and checking
customers' process·data and marketing data for
higher reliability of our products. To analyze them
is very helpful for the improvement of designing and
manufacturing.

Figure 6

Failure Mode Rate of MOS Memory

3. Reliability of Semiconductor Devices
3.1. Reliability Characteristics for Semiconductor
Devices
Hitachi semiconductor devices are designed, manu·
factured and inspected so as to achieve a high level
of reliability. Accordingly, system reliability can be
improved by combining highly reliable components
along proper environmental conditions. This
section describes reliability characteristics, failure
types and their mechanisms in terms of devices.
First, semiconductor device characteristics are
examined in light of their reliability.
(1) Semiconductor devices are essentially structure
sensitive as seen in surface phenomenon. Fab·
ricating the device requires precise control of a
large number of process steps.
(2) Device reliability is partly governed by elec·
trode materials and package materials, as well as
by the coordination of these materials with the
device materials.
(3) Devices employ thin·film and fine·processing
techniques for metallization and bonding. Fine
materials and thin film surfaces sometimes
exhibit physically different characteristics from
the bulks.

(4) Semiconductor device technology advances
drastically: Many new devices have been
developed using new processes over a short
period of time. Thus, conventional device reo
liability data cannot be used in some cases.
(5) Semiconductor devices are characterized by
volume production. Therefore, variations
should be an important consideration.
(6) Initial and accidental failures are only con·
sidered to be semiconductor device failures
based on the fact that semiconductor devices
are essentially operable semipermanently.
However, wear failures caused by worn mate·
rials and migration should be also reviewed
when electrode and package materials are not
suited for particular environmental conditions.
(7) Component reliability may depend on device
mounting, conditions for use, and environment.
Device reliability is affected by such factors as
voltage, electric field strength, current density,
temperature, humidity, gas, dust, mechanical
stress, vibration, mechanical shock, and radia·
tion magnetic field strength.

@HITACHI
Hitachi America, Ltd • Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

21

Reliability of Hitachi

Ie M e m o r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - contribute to reliability related fields such as
product design, prediction, test, storage and usage
by adding physics as a basic technology to conven·
tional experimental and statistical approaches.

Iniba] faiJure reglOn
: Declinmg fBllure rates (m< 1 )
Wearout failure regIOn
: Rismg fadure rates (m > 1)

____ ~~I~~~~~!:a~ ____ _
:---------- I

:

Random fadure region
. Constant fadure rates (m = 1)

: m . Welbull dlstnbubon
:
form parameter
I

I

Useful longevity

I

Tune (t)

Figure 7

Typical failure rate curve

Device reliability is generally represented by the
failure rate. 'Failure' means that a device loses
its function, including intermittent degradation
as well as complete destruction.
Generally, the failure rate of electric components and equipment is represented by the
bathtub curve shown in Fig. Z. For semiconductor devices, the configuration parameter of
the Wei bull distribution is smaller than 1, which
means an initial failure type. Such devices
ensure a long lifetime unless extreme environmental stress is applied. Therefore, initial and
accidental failures can become a problem for
semiconductor devices. Semiconductor device
reliability can be physically represented as well
as statistically. Both aspects of failures have
been thoroughly analyzed to establish a high
level of reliability.
3.2 Failure Types and Their Mechanisms
3.2.1 Failure physiCS
Failure physics is, in a broad sense, a basic technology of "physics + engineering". It is used to
examine the physical mechanism of failures in terms
of atoms and molecules to improve device reliability. This physical approach was introduced to the
reliability field with the demand for minimized development cost and period, as technology rapidly
developed and system performance increased, requiring more complex and higher levels of reliabili·
ty. These conditions derived from the development
of solid state physics (semiconductor physics) after
World War II and associated device development.
Failure physics have been employed to:
1) Detect failed devices as soon as possible
2) Establish models and equation used for failure
prediction
3) Evaluate reliability in short periods by acceler·
ated life test
The pu rpose of the fai Iure physics approach is to

3.2.2 Failure types and their mechanism
Device failures are physically discussed in this
section. Semiconductor device failures are basically
categorized as disconnection, short-circuit, de·
terioration and miscellaneous failures. These
failures and their causes are summarized in Table
11. Typical failure mechanisms are reviewed next.
(1) Surface Deterioration
The pn junction has a charge density of 1014
1020 fcm 3 . If charges exceeding the above density
are accumulated on the pn junction surface, partic·
ularly adjacent to a depletion layer, electric
characteristics of the junction tend to be easily
varied. Although the surface of such devices as
planar transistors is generally covered with a Si0 2
film and is in an inactive state, the possibility of
deterioration caused by surface channels still exists.
Surface deterioration depends heavily on appl ied
temperature and voltage and is often handled by the
reaction model.
One example of recent failures is surface deteriora·
tion caused by hot carriers. Hot carriers are
generated when such devices as MOS dynamic
RAMs are operated at a voltage near the minimum
breakdown voltage BVos by raising internal voltage
and when a strong electric field is established near
the MOS device's drain resulting from reduced device geometry from 2 ).1m to 0.8 ).1m. Generated hot
carriers may affect surface boundary characteristics
on a part of the gate oxide film, resulting in de·
gradation of threshold voltage (V TH ) and counter
conductance (gm). Hitachi devices have employed
improved design and process techniques to prevent
these problems. However, as process becomes finer,
surface deterioration may possibly become a serious
problem.
(2) Electrode·related Failures
Electrode·related failures have become increasingly
important as multi·layer wiring has become more
complicated. Noticeable failures include electro·
migration and AI wiring corrosion in plastic sealed
packages.
CD Electromigration
This is a phenomenon in which metal atoms are
moved by a large current of about 106 A/cm 2
supplied to the metal. When ionized atoms collide
with current of about scattering electrons, an
'electron wind' is produced. This wind moves the

~HITACHI
22

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra POint Pkwy.• Brisbane, CA 94005·1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - R e l i a b i l i t y of Hitachi

metal atoms in the opposite direction from the
current flow, which generates voids at a negative
electrode, and hillock and whiskers at an opposite
one. The generated voids increase wiring resistance
and cause excessive currents to flow in some areas,
leading to disconnection. The generated whiskers
may cause shortcircuits in multi·metal line.
@ Multi-metal line related failures
Major failures associated with multi-metal line
include increased leak currents, shortcircuits caused
by a failed dielectric interlayer, and increased
contact metal resistance and disconnection between
metal wirings.
@ AI line corrosion and disconnection
When Plastic encapsu lated devices are subjected to
high-temperatures, high-humidity or a bias-applied
condition, AI electrodes in devices can cause corrosion or disconnection (Fig. 8). Under high-temperature and high-humidity, corrosions are randomly

Ie Memories

scopic volume resistivity of sealed resin. The AI line
corrosion mechanism described above is summarized
in Fig. 9.

Figure 9 Plastic package cross section and AI corrosion
mechanism

95

13S"C 12TC
0

sJ

HOT

6

SO

I

I

70

I

0

II

0
0

Figure 8 Categorized AI corrosion mode

~

2

8

10

Corubbon
I
I
I

0

~

V cc=5.5V

RH=85fb

I
I

5-

generated over the element surface. However, after
an extended period of time, the corrosions have not
significantly increased. Accordingly, this failure is
possibly due to an initial failure associated with
manufacturing. It is also verified that this type of
failure can be generated when the adhesion surface
between an element and resin is separated or when
foreign materials are attached to the element with
human saliva. Under a bias-appllied, high-temperature, high-humidity condition, on the other hand,
corrosions are generated in higher potential areas
while in lower potential areas, grain corrosion
occurs. Once this failure occurs in part of a device,
the device can become worn out in a relatively short
time. This failure proves to depend on the hydro-

I

0

.

O. I
10

Figure 10

.

10

.

10
Test Time (hrs)

.

10

An Example of Moisture Resistance by High
temp. and High humidity and bias

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300

23

Reliability of Hitachi

Ie

Memorles-----------------------

,

10

..L
10'

_L
10'

/

,
~

10'

J

Ii'
10'

u:u
~-E

J0

2.0

~- t-l-'If'
I
II I \I
2.5

~= f=
3.0

3.5

T.............. 1/T (IO'/'K)

Figure 11

Relationship between tempereture and
Time to 1% failure (RH = 85%)

(3) Bonding related failures
Degradation caused by intermetallic formation
Bonding strength degradation and contact resistance
increase are caused by compounds formed in connections between Au wire and AI film or between
Au film and AI wire. These are the most serious
problems in terms of reliability. The compounds
are formed rapidly during bonding and are increased
through thermal treatment. Consequently, Hitachi
products are subjected to a lower-temperature,
shorter-period bonding whenever possible.
® Wire creep
Wire creep is wire neck destruction in an Au ball
along an intergranular system occurring when a
plastic sealed device is subjected to a long-term
thermal cycling test. This failure results from
increased crystal grains due to heat application
when forming a ball at the top of an Au wire, or
from an impurity introducing to the intergranular
system. Bonding under usual conditions with no
loop configuration failures does not cause this
failure unless a severe long-term thermal cycling test
is applied. Accordingly, wire creep is not a problem
in actual usage.
® Chip crack
With the increase in chip size associated with the
increased number of incorporated functions, more
problems have been occurring during assembly, such
as chip cracks during bonding. Bonding methods

 Vcc or Vout < GND for input level
Therefore, circuits should be designed so that no
forward current flows through the input protection
diodes or output parasitic diodes.
@ Soft errors
When O! particles are generated from uranium or
thorium in a package the silicon surface of an LSI
chip, electron-hole pairs are formed which act as
noise to data lines and other floating nodes, causing
temporary soft errors. This phenomenon is shown
in Fig. 14. Only electrons from among the electronhole pairs are only collected to a memory cell. As a
result, the cell changes from a state of 1 to 0, which
is a soft error.
Hitachi devices have been subjected to simulation
and irradiation tests to prevent soft errors. In some
cases, organic material, PIO, is applied to the surface
of the device.

a

Equivalent circuit of charging model

@ Latch up
Latch up is a problem unique to CMOS devices.
This problem is a thyristor phenomenon caused by
a parasitic PNP or NPN transistor formed in the
CMOS configuration. Latch up occurs when an
accidental surge voltage exceeding a maximum
rating, a power supply ripple, an unregulated power
supply and noise is applied, or when a device is
operated from two sources having different set-up
voltages. These cases can cause input or output
current to flow in the opposite direction from usual
flow, which triggers parasitic thyristors. This results
in excessive current flowing between a power supply

Figure 14

Soft error caused bv Ct particles in dynamic
memory

@HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

25

Reliability of Hitachi M e m o r i e s - - - - - - - - - - - - - - - - - - - - - - - - - Table 13. Failure causes and mechanism

Failure related causes

Failure mechanisms

Failure modes

Passivation

Surface oxide film,
Insulating film between
wires

Pin hole, Crack, Uneven
thickness, Contamination,
Surface inversion,
Hot carrier injected

Withstanding voltage
reduced, Short, Leak
current increased,
hFE degraded, Threshold
voltage variation, Noise

Metallization

Interconnection,
Contact, Through hole

Flaw, Void, Mechanical
damage,
Break due to uneven
surface, Non-ohmic
contact, Insufficient
adhesion strength,
Improper thickness,
Electromigra tion,
Corrosion

Open, Short,
Resistance increased

Connection

Wire bonding,
Ball bonding

Bonding runout,
Compounds between metals,
Bonding position mismatch,
Bonding damaged

Open, Short
Resistance increased

Wire lead

Internal connection

Disconnection,

-~~---~~-

Open, Short

Sagging, Short
- -- - - - -

Diffusion, Junction

Junction diffusion,
Isolation

Die bonding

Connection between die
and package

Package sealing

Packaging, Hermetic
Seal, Lead plating,
Hermetic pakage &
plastic package, Filler gas

Crystal defect,
Crystallized impurity,
Photo resist mismatching

---

------

Peeling chip, Crack

Integrity,
moisture ingress,

Impurity gas, High
temperature, Surface
contamination, Lead
rust, Lead bend, break
~----

Foreign matter

Foreign matter in package

Input/output pin

Electrostatistics,
Excessive Voltage, Surge

Disturbance

'" particle
High electric field

-----~--

Short, Leak current
increased

~-

Electron destroyed

."-~---~.---

------

Open, Short, Unstable
operation, Thermal
resistance increased
-- f------Short, Leak current
Increased, Open, Corrosion
disconnection, Soldering
failure

.---------~-

Dirt, Conducting foreign
ma tier, Organic carbide

- - - - - - - - - t-------~------~---------

Withstanding voltage
reduced, Short

Electron hole generated
1-----Surface inversion

Short, Open, Fusing

Soft error
Leak current increased

----

~HITACHI
26

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy • Bnsbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - R e U a b l l i t y of Hitachi Ie Memories
(6) Fine geometry related problems
In response to higher integration requirements for
memories and microcomputers, LSI geometry has
been reduced in the way of 3 IJ.m -+ 2 IJ.m -+ 1.3 IJ.m
-+O.8IJ.m•

However power supply has not been scaled down
used for 5V, only line dimensions have been fined
increasingly. Problems associated with finer geo·
metry are shown in Table 14.

Table 14. Finer geometry reletad problems
Item

Problems

Countermeasure

5V single supply voltage

• Breakdown voltage of gate oxide films
• SiO. defects

Oxide film formation process improved
• Cleaning
• Gettering
• Screening

Horizontal dimension
reduction

• Soft errors by .. particles
• AI reliability reduced
• CMOS latch up
• Mask alignment margin reduced
• Hot carriers

Surface passivation film improved
• Metallization improved
• Design/layout improved
• Process improved

Vertical & horizontal
dimension r~duction

• Higher breakdown voltage not permitted
• Electrostatic discharge resistance reduced

Use of low voltage examined
• Configuration improved
• Protection circuits enhanced

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

27

• QUAUTY ASSURANCE OF IC MEMORY
1. VIEWS ON QUALITY AND
RELIABILITY
Hitachi basic views on quality are to meet individual
users' purpose and their required quality level and
also to maintain the satisfied level for general ap·
plication. Hitachi has made efforts to assure the
standardized reliability of our IC memories in actual
usage. To meet users' requests and to cover expand·
ing application, Hitachi performs the followings;
(1) Establish the reliability in design at the stage of
new product development.
(2) Establish the quality at all steps in manufactur·
ing process.
(3) Intensify the inspection and the assurance of reo
liability of products.
(4) Improve the product quality based on market·
ing data.
Furthermore. to get higher quality and reliability.
we cooperate with our research laboratories.
With the views and methods mentioned above,
Hitachi makes the best efforts to meet the users' reo
quirements.

2. RELIABILITY DESIGN OF
SEMICONDUCTOR DEVICES
2.1 Reliability Target
Establishment of reliability target is important in
manufacturing and marketing as well as function
and price. It is not practical to determine the reo
liability target based on the failure rate under single
common test condition. So, the reliability target is
determined based on many factors such as each
characteristics of equipment, reliability target of
system, derating applied in design, operating condi·
tion and maintenance.
2.2 Reliability Design
Timely study and execution are essential to achieve
the reliability based on reliability targets. The main
items are the design standardization, device design
including process and structural design, design
review and reliability test.
(1) Design Standardization
Design standardization needs establishing design
rules and standardizing parts, material, and
process. When design rules are established on
circuit, cell, and layout design, critical items
about quality and reliability should be ex·
amined. Therefore, in using standardized

•
28

process or material, even newly developed prod·
ucts would have high reliability, with the excep·
tion of special requirement on function.
(2) Device Design
It is important for device design to consider
total balance of process design, structure
design, circuit and layout design. Especially in
case of applying new process or new material,
we study the technology prior to development
of the device in detail.
(3) Reliability Test by Test Site
Test site is sometimes called Test Pattern. It is
useful method for evaluating reliability of
designing and processing ICs with complicated
functions.
1. Purposes of Test Site are as foi,ows;
• Making clear about fundamental failure mode;
• Analysis of relation between failure mode and
manufacturing process condition.
• Analysis of failure mechanism.
• Establishment of QC point in manufacturing.
2. Effects of evaluation by Test Site are as follows;
• Common fundamental failure mode and
failure mechanism in devices can be evaluated.
• Factors dominating failure mode can be
picked up, and compared with the process
having been experienced in field.
• Able to analyze relation between failure
causes and manufacturing factors.
• Easy to run tests.
2.3 Design Review
Design review is a method to confirm systematically
whether or not design satisfies the performance
required including by users, follows the specified
ways, and whether or not the technical items
accumulated in test data and application data are
effectively applied.
In addition, from the standpoint of competition
with other products, the major purpose of design
review is to insure quality and reliability of the
product. In Hitachi, design review is performed
in designing new products and also in changing
products.
The followings are the items to consider at design
review.
(1) Describe the products based on specified design
documents.
(2) Considering the documents from the standpoint
of each participant, plan and execute the sub·
program such as calculation, experiments and

HITACHI

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- - - - - - - - - - - - - - - - - - - - - - - - - - - Quality Assurance of

investigation if unclear matter is found.
(3) Determine the contents and methods of reliability test based on design document and drawing.
(4) Check process ability of manufacturing line to
achieve design goal.
(5) Arrange the preparation for production.
(6) Plan and execute the sub-programs of design
ch~nges proposed by individual specialists, for
tests, experiments and calculation to confirm the
design change.
(7) Refer to the past failure experiences with
similar devices, confirm the prevention against
them, and plan and execute the test program
for confirmation of them.
In Hitachi, these study and decision at design review
are made using the individual check lists according
to its objects.

I

Step

3.1 Activity of Quality Assurance
The following items are the general views of overall
quality assurance in Hitachi;
(1) Problems is solved in each process so that even
the potential failure factors will be removed at
final stage of production.
(2) Feedback of information is made to insure
satisfied level of process ability.
As the result, we assure the reliability.

Purpose

Des ign ReVIew

~pet.lficailim

I

/Il."gn
Trl.tl

11

ProductIOn

MateriaI-., Parts
I\pproval

If-

Characterlstlts of Material and
Parts
Appearance
DimenSion

Heat ReSistance
Mechanical
Electrical
Others

II

Memory

3. QUALITY ASSURANCE SYSTEM OF
SEMICONDUCTOR DEVICES

Contents

TarRt"t

Ie

Characteristics Approval

11---

Electrical
CharaC'terlo;tlcs
Fun('tlOn
V~It.g.

Current
Temperature

Conflrmallon of
Cha rac te nstlcs and
ReliabilIty of MaterIals
and Parts

ConfirmatIOn of Target
Spec. Mamly about
Electrical
Characteristics

O,h.r.
Appearance, DimenSion

II

Qua IIty Approva I (1)

II

Quality Approval (2)

1MProduction
...
.1

jf-

H-

ReliabilIty Test
LIfe Test
Thermal Stress
MOIsture ReSIstance
MechanIcal Stress
Others

ReliabilIty Test

ConfirmatIOn of Quality
and Reliability m Design

Conhrmation of Quality

Process Check same as

and Reliability

Quality Approval (1)

Producllon

In

Mass

Figure 1 Flow Chert of Qualification

~HITACHI
Hitachi Amenca, Ltd • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

29

Quality Assurance of Ie Memory - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ __
3.2 Qualification
To assure the quality and reliability, the qlJalifica·
tion tests are done at each stage of trial production
and mass production based on the reliability design
described in section 2.
The followings are the views on qualification in
Hitachi:
(1) From the standpoint of customers, qualify the
products objectively by a third party.
(2) Consider the failure experiences and data from

customers.
(3) Qualify every change in design and work.
(4) Qualify intensively on parts and materials and
process.
(5) Considering the process ability and factor of
manufacturing fluctuation, establish the control
points in mass production.
Considering the views mentioned above, qualification shown in Fig. 1 is done.

Quality Control

Process

Method

Inspection on Ma te ria I and

---

Parts for Semiconductor

Lot Sampling,
Confi;mation of
Quality Level

Devices
Manufacturing Equipment,

-

Environment. Sub-material.

-

-

Confirmation of
Quality Level

Worker Control

Inner Process

Lot Sampling,

Quality Control

Confirmation of
Qua IIty Leve I

100% InspectIOn on

Testing,

Appearance and Electrical

Inspection

Characteristics
Sampling InspectIOn on
Lot Samphng

Appearance and Electrical
Cha racte rlstlC s

Confirmation of
Rellablhty Test

Quality Level, Lot
Sampling

r-----------,

I

I
I

I

Quality Information.
Claim
Field Experience
General Quahty
Information

I
I

Feedback of
Information

I'-- _ _ _ _ _ _ _ _ _ _ ..J
Figure 2 Flow Chart of Quality Control in Manufacturing Process

30

$

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - Q u a l i t y Assurance of
3.3 Quality and Reliability Control in Mass Produc·
tion
To assure quality in mass production, quality is
controlled functionally by each department, mainly
by manufacturing department and quality assurance
department. The total function flow is shown in
Fig. 2.
3.3.1 Quality Control on Parts and Materials
With the tendency toward higher performance and
higher reliability of devices, quality control of parts
and materials becomes more important. The items
such as crystal, lead frame, fine wire for wire bond·
ing, package and materials required in manufactur·
ing process like mask pattern and chemicals, are all
subject to inspection and control.
Besides qualification of parts and materials stated In
3.2, quality control of parts and materials is defined
in incoming inspection. Incoming inspection IS per·
formed based on its purchase specification, drawing
and mainly sampling test based on MIL·STD·105D.
The other activities for quality assurance are as
follows.
•

Table 1. Quality Control Check Points of Parts
and Material (example)
Material.

Parts

Wafer

ImporUnt
Control Items
Appearance

DimensIOn

Sheet ResiStance
Defect DensIty
Crystal Ax IS

Appearance
Mask

DimensIOn

WlTe for
WlTe
Bonding

lion on Surface
Flatness
Resistance
Defect Numher~

----Defect Numbers, Sc..ratch
DimenSion Level

Resistoratlon
GradatIOn

FlOe

Pomt for Check

Damage and Contam-103-

Appearance

Uniformity of Gradation
Contamination. Scratc..h,
Bend, TWist

DimensIOn
Purify
Elongation RatIO
AppearanceDimenSion

Purity Level
Mechanical Strength
ContaminatIOn, Scratch
Dlmen~lOn Level

Processing

FrJ.me

CeramIC
Pac kage

PlastiC

Accuracy
Plating
Bondahlilty. Solderabihty
Mountmg
Heat Resistance
Character 1st ICS
----,--Appearance
ContamJ031lOn, Scrat(h
DimenSIOn
DlmeonslOn Level
Leak ReSistance
Airtightness
Plating
Bondablilty. Solderablhty
Mountmg
Heat ReSistance
CharacteristiCS
Electrical
Characteristics
MechaOical
Mechanical Strength
Strength
- -;-- -------CompositIOn
Charat tenstlcs of
PlastiC Mdtenal
Eleetr,,:al
CharacteristICs
Thermal
Char de tens tiCS
MoldlOg
Moldmg Perform ante
Performance
Mountmg
Mounting Characterastlcs
CharactenstlCS

Ie

Memory

(1) Technology Meeting with Vendors
(2) Approval and Guidance of Vendors
(3) Analysis and tests of physical chemistry.
The typical check points of parts and materials are
shown in Table 1.
3.3.2 Inner Process Quality Control
To control inner process quality is very significant
for quality assurance of devices. The quality
control of products in every stage of production is
explained below. Fig. 3 shows Inner process quality
control.
(1) Quality Control of Products in Every Stage of
Production
Potential failure factors of devices should be removed in manufacturing process. Therefore, check
points are set up In each process so as not to move
the products with failure factors to the next
process. Especially, for high reliability devices,
manufacturing lines are rigidly selected in order to
control the quality in process. Additionally we perform rigid check per process or per lot, 100%
inspection in proper processes so as to remove
failure factors caused by manufacturing fluctuation,
and screenings depending on high temperature aging
or temperature cycling. Contents of controlling
quality under processing are as follows:
• Control of conditions of equipment and workers
and sam pli ng test of uncompleted produsts.
• Proposal and execution of working improvement.
• Education of workers
• Maintenance and improvement of yield
• Picking up of quality problems and execution of
countermeasures toward them.
• Communication of quality information.
(2) Quality Control of Manufacturing Facilities and
Measuring Equipment
Manufacturing facilities have been developed with
the need of higher devices in performance and the
automated production. It is also important to determine quality and reliability.
In Hitachi, automated manufacturing is promoted
to avoid manufacturing fluctuation, and the opera·
tion of high performance equipment is controlled to
function properly.
As for maintenance inspection for quality control,
daily and periodically inspections are performed
based on specification on every check point.
As for adjustment and maintenance of measuring
equipment, the past data and specifications are
clearly checked to keep and improve quality.

~HITACHI
Hitachi Amenca. Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Bnsbane. CA 94005·1819 • (415) 589.8300

31

Quality Assurance of Ie M e m o r y - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ __
(3) Quality Control of Manufacturing Circumstances and Sub-material.
Quality and reliability of devices are affected
especially by manufacturing process. Therefore, we thoroughly control the manufacturing
circumstances such as temperature, humidity,
dust, and the sub-materials like gas or pure
water used in manufacturing process.

Process

Dust control is essential to realize higher integration and higher reliability of devices. To
maintain and improve the clearness of manufacturing site, we take care buildings, facilities, airconditioning system, materials, clothes and
works. Moreover, we periodically check on
floating dust in the air, fallen dust or dirtiness
on floor.

Control Point

Purpose of Control

Purchase of Mater .. 1
Wafer

Wafer
Surface OXIdatIOn
InspectIOn on Surface
OxidatIOn
Photo Resist

CharacteristiCS, Appearance

OXIdatIOn

Scratch. Removal of Crystal
Defect Wafer
Assurance of Resistance

Appearance. ThIckness of
OXIde Flim

Pmhole. Scratch

DlmenslOn, Appearance

D,mension Level
Check of Photo Res ist
DiffUSIOn Status

Photo
Resist

InspectIOn on Photo Resist
o PQC Level Check
D,ffus,on

Diffusion

Diffus IOn Depth. Sheet
Resistance

Inspec tlOn on Dtffus IOn
OPQC Level Check
Evaporation

In.pectlOn on Evaporation
o PQC Level Check
Wafer InspectIOn

Gate WIdth
Characteristics of Oxide Film
Breakdown Voltage
Evapo-

Thickness of Vapor Flim.

ration

Scratch, ContaminatIOn

Wafer

ThIckness. VTH Characteristics

InspectIOn on Ch,p
Electrical Characteristics
ChIp Scribe
Inspection on Chip
Appearance
o PQC Lot Judgement

Chip

Assembhng

Assembling

Control of Basic Parameters
(VTH. etc) Cleaness of surface,
Prior Check of VtH
Breakdown Voltage Check
Assurance of Standard
ThIckness

Prevention of Crack.
Quality Assurance of Scribe

Electrical CharacterIStICS
Appearance of Ch,p

Frame
Appearance after Chip
Bordmg
Appearance after Wire

o PQC

Bonding
Pull Strength. Camp res IOn
Width. Shear Strength
Appearance after Assembhng

Level Check

Inspection after
Assembling
o PQC Lot Judgement
Package

Sealing

Sealmg

o PQC Leve I Check
Marking
Final Electrical Inspection
OFailure Analysis

Qualtty Check of Chip
Bonding
Quality Check of Wire
Bonding
PreventIOn of Open and
Short

Appearance after Sealing
Outline. Dimension
Ma rk ing Strength

and Dlmens Ion

AnalysIs of Faliures. Faliure
Mode. Mechanism

Feedback of AnalysIs Informatian

Guarantee of Appearance

Appearance InspectIOn
Sampling inspectIon on
Products
ReceiVing
Shipment
Figure 3 Example of Inner Process Quality Control

~HITACHI
32

Hitachi America. Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - Q u a l l t y Assurance of

3.3.3 Final Tests and Reliability Assurance
(1) Final Tests
Lot inspection is done by quality assurance
department for the product passed in 100% test
in final manufacturing process. Though 100%
of passed products is expected, sampling inspection is subjected to prevent mixture of failed
products by mistake.

Ie Memory

The inspection is executed not only to confirm
that the products meet users' requirement, but
to consider potential factors. Our lot inspection is based on MIL-STO-1050.
(2) Reliability Assurance Tests
To assure reliability, the reliability tests are per·
formed periodically, and performed on each
manufacturing lot if user requires.

Failure AnalysIs

Countermeasure

Execution of
Countermeasure

Report

Quality Assurance Dept.

Follow-up and Confirmation
of Countermeasure Execution

Report
L ________________________________

~

Sales Engineering Dept.

Reply

Customer

Figure 4

Proc_ Flow Chart of Coping with Failure to a Customer

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589-8300

33

• OUTUNE OF TESTING METHOD
1. INSPECTION METHOD

2. MARCHING PATTERN

Compared to conventional core memories, IC
memories contain all peripheral circuits, such as the
decoder circuit, write circuit and read circuit. As a
result, assembly and electrical inspection of ICs are
all performed by IC manufacturers. Consequently,
as the electrical inspection of IC memories are
becoming more systematic, conventional IC inspec·
tion facilities are becoming useless. This has led to
the development and introduction of a memory
tester with pattern generator to generate the inspec·
tion pattern of the memory IC at high speed. A
function test for such as TTL gates can be per·
formed even by a simple DC parameter facility.
However, when the address input becomes multiplexed as in 16K, 64K and 256K memory, even the
generation of the function test pattern becomes a
serious problem.
In the memory IC inspection, its quality cannot be
judged by DC test on external pins only, because the
number of the element such as transistor which can
be judged in the DC test is only 1/1000 of all elements. The followings are the address patterns proposed to inspect whether the internal circuits are
functioning correctly.
(1) All "Low", All "High"
(2) Checker Flag
(3) Stripe Pattern
(4) Marching Pattern
(5) Galloping
(6) Waling
(7) Ping-Pong
Those are not all, but only representative ones.
There are the pattern to check the mutual interference of bits and the pattern for the maximum
power dissipation. Among the above mentioned
patterns, those of (1) to (4) are called N pattern,
which can check one sequence of N bit IC memory
with the several times of N patterns at most. Those
of (5) to (7) are called N3 pattern, which need
several times of N2 patterns to check one sequence
of N bit IC memory. Serious problem arises in using
N 2 pattern in a large-capacity memory. For example, inspection of 16K memory with galloping
pattern takes a lot of time - about 30 minutes. (1),
(2) and (3) are rather simple and good methods,
however, they are not perfect to find any failure in
decoder circuits. Marching is the most simple and
necessary pattern to check the function of IC
memories.

The marching pattern, as its name indicates, is a pattern in which "1"s march into all bits of "O"s. For
example, a simple addressing of 16 bit memory is
described below.
(1) Clear all bits ............. See Fig. 1 (a)
(2) Read "0" from Oth address and check that the
read data is "0". Hereafter, "Read" means
"checking and judging data"
(3) Write "1" on Oth address ....... See Fig. 1(b)
(4) Read "0" from 1st address.
(5) Write "1" on 1st address.
(6) Read "0" from nth address.
(7) Write "1" on nth address ...... See Fig. 1 (c)
(8) Repeat (6) to (7) to the last address. Finally,
all data will be "1".
(9) After all data become "1", repeat from (2) to
(8) replacing "0" and "1".
In this method, 5N address patterns are necessary
for the N-bit memory.

•
34

a

o

Figure1

c

b

o

0

o

0

0

0

o

0

0

o

0

Addreaing method of for 16 bit memory in the
Marching pattern

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Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 940OS-1819 • (415) 589-8300

• APPLICATION
1. Static RAM
1.1. Static RAM Memory Cell
The static RAM memory cell consists of flip-flops
organized as 4 NMOS transistors and 2 load resistors
as shown in figure 1-1. The data in the cell can be
retained as long as power is supplied, and read out
without being destroyed.
Word Lme

Vee

Fillure1-1.

Vee

Static RAM Memory Can

1.2.

Data Retention Mode and Battery Back-up
System
The data in RAM is destroyed at power off. However, CMOS static RAM has a data retention mode.
In this mode, power consumption at standby is extremely low and supply voltage can be reduced to
2 V. So, it enables a battery back-up system to
retain data during power failure.
Data Retention Mode: The important point in
designing a battery back-up system is the timing
relation between the memory power supply during
the change (ordinal source'" battery) and the chip
select signal. If the timing for the change is missed,
the data in memory might be destroyed_
Figure 1-2. shows the timing for switching the
power supply. The following explains the technical
terms related to the data retention mode.
Data retenbon mode

V c c - - -___
VD.R~2.0V

OV _ _ _ _ _ _ _ _ _ _Cs(CE)"
_ _ _ _VDrO.2V
___________ _

Fillure 1-2.

Timing for Battary Back-up Application

Data retention mode: The period that the power
supply voltage is lower than the specified operation
voltage. During this period, memory must be kept in
non-select condition (e.g. CS = V OR - 0.2V).

teoR (time for chip select to data retention): The
minimum time needed to change from operating
mode to data retention mode. Normally 0 ns.
tR (Operation recovery time): The minimum time
needed to change from data retention mode to
operating mode. Normally, it is the same as the
cycle time of the memory.
VOR (data retention voltage): The voltage applied in
data retention mode. Normally, the minimum
supply voltage needed to retain memory data is 2 V.
I eeOR (data retention current): The current consumption in data retention mode. It depends on
memory power supply voltage and ambient temperature. It is specified at supply voltage (VOR) =
3.0 V.
Battery Back-up System: battery back-up sequence
is described in the following:
1. External circuit detects failure of system power
supply.
2. External circuit changes RAM to standby mode.
3. External circuit separates RAM from system
power supply.
4. External circuit switches to Back-up power
supply.

Memory Vee

System Vee

]§ s;;
U

..,

Memory

f---4----------

Figura 1-3.

control pm

Example of Battery Back-up System

The control circuit detects the power failure and
cuts off the power after switching memories to
standby mode. On recovery, it confirms power
supply and after some delay, returns memories to
operating mode. The memory control signals
depend on the types of memories used in the
system.
* Using memory with only one CS. NAND signal
between the control signal and chip select signal
should be connected to CS. As the level of CS in
data retention mode must be higher than VOR 0.2V, the power supply for this NAND gate must
either be shared with the memory power supply,
or be pulled up to the memory power supply.
* Using memory with two CS. Basically, the
signals are the same as mentioned above. In
general use, two pins should be used for the
control signal and the chip select signal respec-

~HITACHI
Hitachi America, Ltd • Hitachi Plaza' 2000 Sierra Point Pkwy' Brisbane, CA 94005-1819 • (415) 589-8300

35

Application----------------------------------------

tively. CS, which can intercept current path of
other pins in the input buffers, is for control
signal input of data retention mode.
* Using memory with CS and CS. As CS selects
the chips at high level, it is better to use CS than
CS as control signal input for data retention
mode. As soon as power down is detected,
signals should be brought to low level. So a pullRegulating

up to the memory power supply level is not
needed and circuit organization is simplified.
Figure '-4 shows an example of a battery back-up
system circuit. Hitachi recommends using CMOS
logic for gate G 1 in control circuit and memory
Vcc. The low V CE transistor Q 1 is required to
switch regulating circuit from system power supply
to back-up power supply.

CircUit

+ 5V o-__S_y,_,e,..m_V_'_'-~-h.' ·;tr----~t-..,-

j

i

--l
,

r"l

L___ J
Back-up

CircUits

Figure ,....

Example of Battery Back-up System Circuit

•
36

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

------------------------------------Application
2. Pseudo·Static RAM
2.1 Pseudo·Static RAM Features
A new type of memory, pseudo-static RAM has
been developed providing the advantages of
dynamic RAM (low cost, high density), and static
RAM (easy usage). IC memory consists of memory
cells for data storage, and input/output circuits for
interfacing to the external circuits. PSRAM provides the memory cell and peripheral circuits of
DRAM and the external control circuits, which
includes a part of the refresh control circuits not
provided by dynamic RAM, and interface circuits
similar to that of static RAM, on a chip, as shown in
table 2-1. Address input is not multiplexed and
data input/output is byte-wide like standard static
RAM. With PSRAM x 8 organization, medium
density memory system can be designed easily.
PSRAM provides address refresh, automatic refresh
and self refresh.
Figure 2-1 shows examples of system design using
PSRAM and DRAM. Using PSRAM, the circuits

--

Data
Address

C
P
U

~

1

Status

~

Timer &
Control

Busy

IPSRAM)

Figure 2-1.

System Organization

Memory Array
11T'+IC/CeIl)

Table 2·1. PSRAM Feetures
SRAM

Memory Cell

4 Tr + 2 R

Organization

xl,x4,x8

Address

1 Tr + 1 C

Nor
Necessary

External Circuits

Data

xl,x4

x8

Single Address

Refresh

DRAM

PSRAM

Multiplexed
Address
Column Address

Necessary

Simple<:

:>Complexed

Figure 2-2.

interfacing CPU to DRAM can be drastically
reduced.
Figure 2-2 shows block diagram of pseudo static
RAM.
2.2. 1 Mbit Pseudo-Static RAM Function
Read/Wrlte Cycle: Figure 2-3 and figure 2-4 show
the timing chart for the read/write cycle of 1 Mbit
pseudo-static RAM HM658128_ The HM658128

Block Diagram (PSRAM)

can perform 2 types of access in a read cycle, CE
access (Figure 2-3 (a)) and DE access figure 2-3 (b)).
It writes the data at the rising edge of WE (figure
2-4 (a)) or at the rising edge of CE (figure 2-4 (b)).
The CS" pin should be brought high when the address is latched at the falling edge of ~ in the read/
write cycle. The HM658128 has no U'E" specification at the falling edge of CE as it provides both U'E"
pin and RFS'Ff pin.

ar

cs
Da..

(.) CE

(b)

access

Figure 2-3.

•

DE

access

Reed Cyda

HITACHI

Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

37

A p p l i c a t i o n - - - - - - - - - - - - - - - - - - - - - - - - - - - -_________
CS Standby Mode: The HM658128 enters CS
standby mode for one cycle if CS turns to low
at the falling edge of CE (figure 2-5).

Standby

Address

:: ;;;;;:J IIIIIIII~
Figure 2-5.

CS

CS Standby Mode

D,..
(a) Write at the

riSing

edge of WE

Figure 2-4.

(b) Write at the rlsmg edge of

CE

Write Cycle

Address Refresh: Address refresh mode performs
refresh by access to row address (AO - A8) 0 - 511
sequentially within 8 ms, as shown in figure 2-6 (in

distributed mode). In this mode, CS should be high
at falling edge of CEo

15,us

A9-A16
CS--~~--------~---+----------~---+--------~r---~---

Refresh

R/W

Figure 2-6.

Address Refresh

Automatic Refresh: The HM658128 goes to automatic refresh mode if RFSH falls while CE is high
and it is kept low for more than 180 ns.
It is not required to input the refresh address from

address pins AO - A8, as it is generated internally.
Figure 2-7 shows the timing chart for distributed
refresh. In automatic refresh mode, the timing for
only CE and RFSH are specified.

"
RFSH

18Ons;;;;Refresh<8,us

Figure 2-7.

Self Refresh: Self refresh mode performs refresh at
the internally determined interval. The HM658128
enters the mode when the internal refresh timer is

Automatic Refresh

enabled by keeping CE high and RFSH low for
more than 8 Jl.s (figure 2-8).

~HITACHI
38

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------------------------------------------------------------------------A~ication

Second self refresh current increases at low supply
voltage.

SXl
Figure 2-8.

[d:Y

Self Refresh

Fad

Considerations on Using HM658128: The following
should be considered when using the HM658128.
• Data retention. The HM658128 can retain the
data with a battery (but not for long time). The
HM658128L, low power version, offers typical
self-refresh or standby current of 1001olA.
A 1-Mbyte system (using eight HM658128Ls)
can retain the data for about 1.5 months with
battery of 100 mAh current. Vee = 5 V ± 10%
must be maintained for data retention.
• Power on. Start HM658128 operation by
executing more than eight initial cycles (dummy
cycles) more than 100 tJS after power voltage
reaches 4.5 V - 5.5 V after power on.
• Bypass capacitor. Hitachi recommends inserting
1 bypass capacitor per RAM.
2.3 Pseudo-Static RAM Data Retention
PSRAM with self refresh retains data CE and OE
are fixed for more than defined period. The following explains considerations for PSRAM data retention.
First, PSRAM cannot retain the data at low supply
voltage.
They employ 1 MOS type memory cell as shown in
figure 2-9. The charge is stored on the capacitor C
as memory data. The data 1, written at low supply

Self Refresh Voltqe

Figure 2-10. PSRAM Operating Voltage

PSRAM provides the voltage level detector circuit
to reduce self refresh current. However, it should
be noted that the circuit increases the current with
low supply voltage in self refresh (figure 2-11). Self
refresh current also increases at low temperature
(figure 2-12).

Figure 2-11. Self Refr.h Current ft. Voltage

Spe,
O'c

r",m'''''''''''''1

~
Temperature

Figure 2-12. Self-Ref_h Current vs Temperature
Word Lme

Please use PSRAM within the recommended operation range (Vee more than 4.5 V, temperature more
than O°C) for data retention, especially using a
battery.

Figure 2-9. Memory Cell of PSRAM

voltage, cannot be read as 1 at high supply voltage.
Figure 2-10 indicates the operation voltage for self
refresh and subsequent read of PSRAM. If the data
is read out at more than 5 V of Vee, for example,
after self refresh is performed at Vee = 3.7 V, it is
destroyed.
PSRAM must be used at supply voltage from 4.5V
to 5.5V.

•

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39

Application
3. Video RAM
3.1. Multiport Video RAM
Figure 3-1 shows general idea of video RAM_ Multiport video RAM provides an internal data register
(SAM) with the memory (RAM). Both of them
can be accessed asynchronously. Effective graphic

display memory is realized by using the random
port of the RAM part for graphic processor drawing
and the serial port of the SAM part for CRT display.

RAM

DRAM
Random port

memory cell

Drawing

MultI-port

AddN'SS

Video RAM

Graphic

Processor

Figure 3-1.

Generelldea of Multi-port Video RAM

shows the operation modes of the HM53461.

Figure 3-2 shows the block diagram of the 256kbit multiport video RAM HM53461, and table 3-1

iIT/OE

SI/O

I/O

Senal
port

SC

Figure 3-2.

The

operation modes shown in table 3-1

SOE

Block Diagram of HM53461

are described as follows.

Table 3-1. Operation Modes of HM53461

At the falling edge of RAS
WE
DT/OE
CAS
- - - - t--H
H
H
H
H
L
H
L
H

RAM modes

SOE
"-"

SAM modes
Notes
SIlO direction
1,2,3
Sin/Sout

X
X
X

Temporary write mask data program
Read transfer

Sin/Sout

Read/write

Sout

H

L

L

L

Write transfer

Sin

H
----

L

L

H

X

X

X

Pseudo transfer
CBR refresh

Sin
Sin/Sout

L

Notes: 1.
2.
3.

----

1,2,3
2

1,2

H: High
L: Low
X: Don't Care
Transfer cycle executed previously d~s SIlO direction.
SIlO is in high impedance state with SOE high, even if the direction is ~
The HMS3461 starts write operation if WE is low at the faIling edge of CAS or become low between the faIling
edge of CAS and the rising edge of RAS.

~HITACHI
40

Hitachi America. Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819· (415) 589-8300

----------------------------------AppIlcatlon
Read/Write Operation: Read/write is performed
on the random port in the same sequence as for a
dynamic RAM (figure 3-3). The HM53461 starts
the read operation with WE high and the write
operation at the falling edge of WE.
AO-A7

Read Transfer Operation: In this cycle, the
HM53461 transfers the data of one row in RAM
(1024 bits). which address is specified at the falling
edge of RAS, to SAM (figure 3-5)_ The start address
in SAM can be programmed at the falling edge of
CAS in this cycle_ After data transfer, the serial
port turns to serial read mode at the rising edge of
DT/OE.

AO-A7

DRAM

memory
c:oII

DRAM

SI/OI - SI/04

memory
c:oII

1/01-1/04

Figure 3-3.

R.d/Write Operation

Figure 3-6.

Temporary Write Mask Set and Temporary Masked
Write Operation: The HM53461 provides temporary masked write operation which inhibits to
write data bit-by-bit (write mask) during one RAS
cycle. Temporary write mask set function defines
the bits to be inhibited (figure 3-4). This operation
puts the data on 1/01 - 1/04 into the internal temporary write mask register. When 0 is programmed
to the register, writing to the corresponding bit is
inhibited.
The temporary write mask register is reset at the
rising edge of RAS.

R.d Tr....st. Operation

Write Transfer Operation: In this cycle, the
HM53461 transfers the data in the SAM data register (1024 bits) to one row in RAM, which address
is specified at the falling edge of RAS (figure 3-6).
The start address in SAM can be programmed in this
cycle. After data transfer, serial port turns to serial
write mode.
AO-A7

AO-A7

DRAM

SII01- 51/04

memory

,.11

DRAM
memory

Figure 3-6.

c:oII

Pseudo Transfer Operation: This operation switches
the serial port to serial write mode (figure 3-7). It
does not perform data transfer between RAM and
SAM. SAM start address can be programmed in this
cycle.

1/01-1/04

Figure 3-4.

Write Transfer Operation

Temporery Mlllkad Write Operation

$HITACHI
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41

~Icationl---------------------------------------------------------------------

Serial RaadJWrite Operation: The HM53461 reads!
writes the contents of the SAM data register in serial
at the rising edge of SC (serial clock input) (figure
3-9). The address for serial access is generated by
the internal address pointer, independently of
random port operation. It should be considered
that serial access is restricted in transfer cycles. The
SAM, employing static-type data registers, requires
no refresh.

AO-A7

......do Transfer Operation

Fi.... re 3-7.

/

~

\

CAS-Before-RAS Refresh Operation: The HM53461
performs refresh by using the internal address
counter in this operation (figure 3-8).

I ~umn I [];] ::=-1
~

~

/

Fi.... re 3-9.

\

Serial R.d/Wrlte Operation

The HM53462 is a multiport video RAM, adding
logic operation capability to the advantages of
HM53461 .
Figure 3-10 shows the block diagram. Table 3-2
describes the operation modes.

DRAM
.....ory

cell

Figure 3-8. CAS-Before-RAS Refresh

,--------RAM

I

---I
SAM

'

I
I

DRAM
I/O

Raodom
port

SI/O

.....ory

cell.

,

I

I
I

Senal
port

I

I

I

I

I

_..J

WE-t--------+------+--------------~
SC

SOE

Figure 3-10. Block Diagram of HM53462

•
42

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------Appllcatlon
Table 3-2. Operation Modes of HM53462

At the falling edge of RAS

RAM modes

CAS

DT/OE

WE

SOE

H

H

H

X

Read/write

H

H

L

X

H

L

H

X

H

L

L

L

SAM modes
SI/O direction

Notes

Sin/Sout

1,2,3

Temporary masked write

Sin/Sout

1,2,3

Read transfer

Sout

Write transfer

Sin

2

H

L

L

H

Pseudo transfer

Sin

L

X

X

X

CAS-before-RAS refresh

Sin/Sout

1,2

X

Logic operation program
(CDR Refresh)

Sin/Sout

1,2

X

L

H: High

Notes: 1.

L
L:

Low

X: Don't Care

Transfer cycle previously executed defines SIlO direction.
SIlO is in high impedance with SOE high, even if S.!lQ..direction is Sout.
__
HM53462 writes if WE is low at the falling edge of CAS or becomes low between the falling edge of CAS and the
rising edge of RAS.

2.
3.

Logic Operation Programming: This function
programs a logic operation (figure 3-11). The logic
operation is available until re-programmed or reset.
In logic operation mode, HM53462 performs readmodify-write internally when data is written into
random port. The result of the logic operation
between memory data and written data is put into
the address from which the memory data is transferred.
In the logic operation programming cycle, the mask
register, which differs from the temporary mask register, is also programmed. It is available until reprogrammed.
AO-A7

.

:! illill--~ti . . --=---->-------'+'"
e
8;::;

I I

1'-"

L_"

-lI

g..a

j

8

I

:

DRAM
memory
cell

I
1

I~::~:=:~W;
11
11

I I

1 I
1 I

1 I

1 I

1/01-1/04

(dotted hnes mdlcate wnte m logic operabon mode)

Figure 3-11. Logic Operation Programming

Notes: Notes on using HM53461/HM53462 are as
follows.
• Dummy RAS cycle. Devices should be initialized
by S dummy RAS cycles (minimum) before
access to random port. Refresh cycle can be inserted for initialization. It is recommended that
the system be initialized by dummy RAS cycle in
the automatic reset time of the processor.
• Bypass capacitor. One bypass capacitor should
be inserted between Vee and Vss to each device.
The Vee pin should be connected to the capacitor by the shortest path. A capacitor of several
fJ.F is suitable.
• Negative voltage input. Negative polarity input
level to input pin or I/O pin should be under -1
V. In this range, it has no effect on device
characteristics or RAM/SAM data retention.
• Initialization
of
logic
operation
mode
(HM53462). The logic operation programming
cycle should be executed before access to the
random port to initialize logic operation mode
after power on. At this time, the operation
codes (0101) and all 1 write mask data are recommended.
3.2_ Line Memory
Hitachi has produced a line memory for line buffers
with simple circuits, providing specific functions as
described below.
The line buffer can improve picture quality by
storing 1 horizontal line data. It has following
features.
• Capacity to store 1 horizontal line data
• High-speed operation matching the sampling
speed of PAL TV signal (4 fsc/S fsc) or NTSC TV
signal (4 fsc/S fsc).

OHITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

43

Ap~ication--

_______________________________________________________________

• Separate data inputs/outputs and capability of
serial data inputs and outputs.
The conventional line buffer composed of high
speed static RAMs requires separate input/output
for double buffer organization. It also requires
interleaving for high speed operation, matching
4 fsc/8 fsc, wherefscisthesubcarrierfrequency. In
addition, external circuits are needed for serial
address scan.
The line memory provides all of these functions.
Figure 3-12 shows the standard organization of a
conventional memory buffer and figure 3-13
shows the block diagram of line memory.

Addres.--------\

The Hitachi HM63021 is a 2048-word x 8-bit line
memory storing 2 horizontal lines of data.
It has five different modes for various video graphic
system applications. It realizes high speed opera·
tions for PAL and NTSC TV signals, and dissipates
little power employing 1.3 Jlm CMOS technology
and static·type memory cells.
The features of the HM63021 are described as
follows:
• Five modes for various video graphic system
applications
- Delay line mode
- Alternate 1H/2H delay mode
- TBC (Time·Base Corrector) mode
- Double speed conversion mode
- Time-base compression/expansion mode
• High speed cycle time
HM63021-34: 34 ns min (corresponds to 8 fsc
of NTSC TV signal)
HM63021-28: 28 ns min (corresponds to 8 fsc
of PAL TV signal).
Line memory in the system using digital signal
processing technologies offers following applica·
tions:
1. com b filter
2. double-speed conversion (non·interlace)
3. compression/expansion of graphics (picturein-picture)
4. dropout canceller
5. time-base corrector
6. noise reducer

Address
Control

Figur.3·12. Standard Orllllnization of Conventional
Line Buffer

I----t--~k
Input

Buffer

IH Memory

Output

Buller

D_.~_~_1d__T-

:-'L--I

Figur.3·13. Block Diagram of Line Memory

•
44

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----------------------------------AppIlcation

4. Dynamic RAM
4.1. Dynamic RAM Memory Cen
The dynamic RAM memory cell consists of 1 MOS
transistor and 1 capacitor, as shown in figure 4-1. It
detects the data in the cell (1 or 0) by the charge
stored in capacitor. Dynamic RAM offers higher
densiJ;y than that of static RAM because of fewer
components per chip.
However, Dynamic RAM must rewrite data, called
refresh, in a defined cycle because the charge stored
in the capacitor leaks.

r
FI..... 4-1.

Memory Cell of Dynamic RAM

4.2. Power On Procedure
After turning on power, to set the internal memory
circuitry, hold for more than 100 IJS, then apply
eight or more dummy cycles before operation. The
dummy cycle may be either a normal read/write
cycle or a refresh cycle. When using an internal reo
fresh counter, eight or more CAS before RAS
refresh cycles are required as dummy cycles.

4.3 Address Multiplexing
Dynamic RAMs are used to increase capacity be·
cause of their smaller cell area. In using dynamic
RAMs in systems, however, it is desirable to increase
the memory density by using smaller packages. To
reduce the number of pins and the package size,
address multiplexing is used.
Using a 1-Mbit dynamic RAM, 20-address signals are
necessary to select one of 1.048,576 memory cells.
Address multiplexing allows address signals to be
applied to each address pin. Thus only 10-address
input pins are required to select one of 1048,576
addresses. Multiplexed address inputs are latched
as follows: RAS (Row Address Strobe) selects one
of word lines according to the row address signal,
and one of column decoders is selected by CAS
(column address strobe) following column address
signal. Although two extra signals, RAS and CAS,
are required, the number of address pins is reduced
to half. Figure 4-2 shows the pin arrangement,
address latch waveform, and the block diagram of
address·multiplexed 1-Mbit dynamic RAM. Systems
need an address multiplexer in order to latch the
multiplexed address signals into the device.

AO-A9 Address Inputs
~

Column Address Strobe
Data In
Data Out
Row Address Strobe
ReadfWrite Input
Vee Power (+5V)
Ground
VSS
AO-AS Refresh Address Inputs
Din
Dout
RAS
WE

(b) A_Lotch

(.) Pin Arranpment

n::. .Ciis_~ld......-w-~_I_.::;:.::.:::=_I

E.temol penpberol-+-lntemollllOlllOrl' LSI

I

Row C"Mcwt
Address

A_

Cuewt

eo.....

CoIumn_
(e) BIoek otiqnm 01 Addns. MulbpIeuq

FI..re 4-2

Add.... Multiplexing of Dynamic RAMI

•

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45

Application---------------------------------4.4. Dynamic RAM Function
Figure 4-3 shows the normal function of Dynamic
RAM.
tRC:
tRCD:
tRAC:

Random Read or Write Cycle Time
RAS to CAS Delay Time
Access Time from RAS

tCAC: Access Time from CAS

R:

Address

c:

Row Address
Column Address

Dout

(a)

Read Cycle

CAS
Address

Address

Don

Don
Dout

Hioh Z
(Early Write) (b) Write Cycle

(Delayed Write)

tRWC: Read-Write Cycle Time
Address

Don

DOllt

1f/l111!1/mvv&:
{

}-

(c) Read-Modify-Write Cycle
Figure 4-3 Normal Function of Dynamic RAM

Read Cycle: In the read cycle, a row address is
latched at the falling edge of liAS", and a column
address is latched at the falling edge of "CAS' after
the "RAS"" fall ing edge. If WE" is high, the data is
read out from Dout with the access time of tCAC
(Access time from CAS) or i!RAC (Access time
from RAS).
The tRCD maximum (RAS to CAS delay time) is
specified only to guarantee the specified minimum
values of other timings such as the cycle time,
RAS/CAS pulse width. Therefore, when using these

timings with more than the specified minimum
value, there is no need to limit the tRCD to the
specified maximum value.
Write Cycle: Dynamic RAM provides two write
cycle modes: early write cycle and delayed write
cycle. In the early write cycle, when WE is low,
data is written into Din at the falling edge of CAS_
In delayed write cycle, when WE is high, data is
written into Din at the falling edge of WE after CAS
falling_
Read-Modify-Write Cycle: The read-modify-write

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--------------------------------------Application
cycle is initiated by taking WE high. Data is read
out from Dout at the falling edge of CAS with WE
high. Then, when WE goes low, data is written into
the same address from Din in the same cycle.
The cycle time in the read·modify·write mode
(tRWC) is longer than the cycle time in read/write
mode {tRcl.

When a word line is selected by row address, all data
in the memory cells connected to the selected word
line is transferred to sense amplifiers. One of these
sense amplifiers is selected by the column address,
and its contents are output.
The output of data from other sense amplifiers is
controlled only by the column address.
Access controlled only by column address with the
row address fixed is called high speed access mode.
Table 4·1 compares each mode.
Page Mode: This is the most typical access mode in
dynamic RAM. The column address is switched
synchronized with CAS falling.
Nibble Mode: In a nibble mode dynamic RAM,

4.5 High Speed Access Mode
Dynamic RAM access time is typically longer than
that of static RAMs. To realize higher speed opera·
tion, they have high speed access modes.
The read operation in dynamic RAM is performed
as follows:

Tabla 4·1. ComparilOn of Dynamic RAM High Speed Accea Modes

RAS

Normal

Mode

CAS
Address

Dout

~

R : Row Address

C . Column Address

Page
Mode

Nibble

Mode

Static Column

Mode

,s-J

RAS \

High-Speed

Page Mode

CAS~~
~

Address
Dout

R

C

1

2

3

4

b::>-

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47

Application-----·-------------------------------data from 4 sequential addresses is stored in the
4·bit output latch circuits. Output is provided by
the CAS signal, which controls the latch circuits.
When 4 addresses are accessed sequentially, the row
addresses on and after second bit need not be
selected. Therefore, it facilitates the timing design.
In nibble mode, the operation is limited to 4 ad·
dresses, however, it enables faster access (tNAcI
than that in page mode.
Static Column Mode: In static column mode, the
column address is switched without the synchro·
nized signal by high·speed static RAM technology
in the peripheral circuits.
High Speed Page Mode: This mode is the advanced
mode of static column mode, with CAS providing
the address latch function.

4.6 Refresh
Refresh operation is performed by accessing every
word line within the specified time (refresh cycle).
Table 4·2 compares the following refresh modes in
dynamic RAM.
RAS Only Refresh: In RAS only refresh mode,
refresh can be completed by selecting only row
addresses synchronized with RAS.
CAS Before RAS Refresh: This mode refreshes by
the CAS falling edge before RAS in the period de·
fined by the internal refresh address generator. This
mode simplifies the external address multiplexer.
Hidden Refresh: In hidden refresh, CAS before
RAS refresh is performed while output data is valid.

Tabla ....2. ComparilOn of Dynamic RAM Rafr.h Mod.

Read
R : Row Address
C : Column Addre..

RASOnly
Refresh
Dout Hch Impedance

CAS before
RAS
Refresh

Address

Pffl/ff/zvAUt/l?lZ?

Dw. - - - - - - -

Hidden
Refresh

W

•
48

Don't care

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Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

------------------------------------Appfication
5. EEPROM
5.1. EEPROM Memory Cell
EEPROM is electrically erasable and programmable
ROM, which can be erased or written remotely
while the system is in operation.
The Hitachi EEPROM memory cell is MNOS (Metal
~itride Qxide ~emiconductor) type, as shown in
figure 5·1.
An MNOS memory cell consists of two layers of
oxide film and nitride film. The thickness of oxide
film is about 20 A and that of nitride film is 300 to
500 A. There are traps in the boundary of the
oxide and nitride films to catch electrons. Electrons
move by the tunneling phenomenon between the
substrate and traps.

MNOS memory cell

A5-A13

I/O

ROY/BUSY

@

AO-A4

Figure 5·2.

Poly-

slhcon

N Substrate

Figure 5·1.

MNOS Type Memory Transistor

5.2. 64-kbit CMOS EEPROM Function
Page Write Function: The 64·kbit HN58C65 can
latch 32 bytes (max) and write them in one write
cycle. Writer cycle time is specified as 10 ms (max.).
The effective byte write speed of HN58C65 in page
write mode is:
10 ms/32 bytes = 0.31 ms/byte
Thus it takes only 2.56 seconds to write the whole
HN58C65. Figure 5.2 shows internal operation.
The following describes operation sequence:
1. 32·byte memory cell data at the row address
selected by address pins A5 - A 12 is latched.
2. Latched data at the column address specified by
address pins AO - A4 is altered with write data,
which is put into Din buffer from I/O pins 1/00

-1/07.
The 32 bytes (max) of latched data are altered
by repeating this operation 32 times.
3. 32·bytes memory cell data in the selected row
(1) are erased (All 1).
4. Latched data is written into the selected row (3).
5. CPU acknowledges the completion of write cycle
by the internal timer. The HN58C65 provides
ROY /BUSY and Data polling to indicate the
write completion.

HN58C65 Page Write

Internal Timer: The HN58C65 indicates the
completion of data write to the CPU by using the
internal timer. The HN58C65 enters next cycle as
soon as detecting the completion of write. This
function offers high system throughput as the CPU
can access other devices during write cycle. The
HN58C65 has two functions, ROY/Busy and Data
polling, to indicate the completion of data write.
The ROY /Busy approach indicates the completion
of data write by using pin 1. It is low when the
HN58C65 is in data write operation (Busy) and
turns to high impedance state at the end of data
write (ROY). ROY/Busy pin should be pulled up as
it uses open drain output. The ROY/Busy pins can
be wired·OR when using several HN58C65s.
The Data polling approach, implemented by soft·
ware, indicates the completion of data write
through pin 19 (1/07). While the data write is not
completed, 1/07 shows the inverted data of what
was written in the last cycle. In using this approach,
RDY /Busy pin should be opened or grounded.
The Data polling approach can acknowledge the
completion of data write in an individual HN58C65,
even if several HN58C65s are used in the system.
Data Protection: EEPROM performs data write
with a higher voltage (V pp ) than power supply
voltage (Vee). The HN58C65 internally generates
V pp by a high voltage generator with the combina·
tion of control pins (CE, OE, WE). It supports the
following functions to avoid accidental data write
(data protection).
1. Data protection against the noise on the control
pins (CE, DE, WE) during operation.
2. Data protection against the noise at power-on/
power-off.

.HITACHI
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49

Application---------------------------------6. EPROM/OTPROM
6.1. EPROM Programming
Figure 6·1 shows the sectional structure of an
EPROM memory cell. The upper gate, one of the
gates made of two·layered polycrystalline silicon, is
called the control gate and is connected to a word
line. The lower layer is called the floating gate and
is not connected. This memory cell is programmed
as follows: With substrate and source grounded,
apply high voltage between drain and control gate.
Then, an electric potential incline occurs between
source and drain so that intensity of the electric
field becomes high near the drain. Because of this
electric field, electrons are accelerated and so-called
hot electrons are generated, which jump over the
energy barrier of Si0 2 film. Hot electrons are
pulled by the electric potential of the control gate
and pour into the floating gate. Electrons stored in
the floating gate remain stable, as they fall into a
well surrounded by an energy barrier of Si0 2 film.
Therefore, it is evident that the quality of Si0 2 film
surrounding the floating gate is essential for good
data retention characteristics. To keep data reten·
tion in the 5· or 10·year range, high quality Si0 2
film is needed.
Figure 6-2. shows the fundamental characteristics of
the EPROM transistor. While 10 in a non·pro·
grammed transistor begins to flow with VG of about
1V, the current in a programmed transistor does not
flow until VG rises to 7 V - 10 V. Therefore, if the
voltage of word line applied to the control gate is
about 5 V in readout, the non·programmed memory
transistor will be on, and the programmed one will
be off. This means that the data can be read out by
means of the same structure as NOR·type mask
ROM.
6.2. Erasing EPROM
When shipped, all bits of the EPROM are at logic 1
with all electrons in the floating gate released
(erase). Changing the logic 1 to logic a through the
application of the specified waveform and voltage,
programs the necessary information. The higher the
V pp voltage and the longer the program pulse width
tpw, the more electrons can be programmed in, as
shown in Figure 6·3. If V pp exceeds the rated
value, such as by overshoot, the p·n junction of the
memory may yield to permanent breakdown. To
avoid this, check V pp overshoot of the PROM
programmer. Also, check negative·voltage·induced
noise at other terminals, which can create a parasitic
transistor effect and reduce the yield voltage.

•
50

Hitachi's EPROMs can usually be written and erased
more than 100 times.

=

/Control Got,

5;0,

Sourc.

Figure 6·1.

Err7..,....Z-rZ~7-.,.,r

~

~rzZ7zY

FloaungGate
Dra'n

Cross Section of EPROM Memory Cell

To

I

Non-programmed

Memory cell

~~-----~-----~

~!01vo
VGL+-J
Figure 6·2.

Fundamental Characteristic of EPROM
Memory Cell
Programmlnl Conditions;
Vcc=6.0V.
Vpp=12.5V

10
Program Pu1ae Width t,.w (ms)

Figure 6-3.

Stand.rd Programming Characteristics
of EPROMs

EPROMs are erased by ultraviolet light exposure
through a transparent window on the package.
Electrons in the floating gate get energy from
photons and become hot electrons again with
enough energy to go over the energy barrier of Si0 2

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----------------------------------------------------------------------------Application
film. The hot electrons go through to the control
gate or the substrate and erasure is completed.
Therefore, light with enough energy to get the
electrons over the energy barrier of Si0 2 film is
needed for erasure. Light energy is proportional to
its frequency, and described as E = hv. E means the
energy of light, h is Planck's constant, v is light
frequency. Erasure isn't caused by light over certain
wavelengths, and under certain wavelengths, erasure
does occur. However, erasure time depends upon
the quantity of photons, therefore erasure time
cannot be shortened by shorter wavelength. Figure
6-4 shows the relation between wavelength and
erasure effectiveness. Erasure starts at about 4000
1\, and is saturated at about 3000A..

be removed with a solvent such as alcohol that does
not damage the package.
Figure 6-5 shows EPROM standard erasure characteristics.
6.3. EPROM Data Retention Characteristic
About 2 to 20 x 10- 14 coulomb of electrons are
accumulated in the floating gate when programmed.
However, these electrons dissipate with time. Then
the data may be inverted. The mechanism of
electron dissipation is generally explained as follows.
Data Dissipation by Heat: The electrons at the
floating gate are in a non-equilibrium state, so the
dissipation of electrons by thermal energy is unavoidable. Therefore, the data retention time
depends on temperature. Figure 6-6 shows typical
data retention characteristics. The data retention
time is proportional to the reciprocal of absolute
temperature.

10

,
I

/

I

,

/
10
Wavelength

300 200 150 100

Figu re 6-4.

Erasure Efficiency of EPROM

For erasure, the wavelength and minimum irradiation rate of ultraviolet light must be 2,5371\ and 15
W's/cm 2 respectively. These conditions can be met
by placing the device 2 - 3 cm below a 12,000
W/cm 2 UV lamp for about 20 minutes.
The UV transmittance of the transparent lid
materials is about 70%. However, it is influenced by
contamination or foreign materials on the lid
surface. Contamination or foreign materials should

Stored temperature ('C)

Figure 6-6.

EPROM's Data Rentantion Characteristic

Data Dissipation by Ultraviolet Light: Ultraviolet
rays at a wavelength of not greater than 3,000 40001\ is capable of releasing the electric charge at

::y

.\
\.

\
6
5
4

:/

I\-

I),

V

I">

W . IrradiatIOn (W .

Figure 6-5.

sec/cm~)

W ntmg Charge (relative)

Standard Erasure Characteristics

Figure 6-7.

EPROM's Data Retention Time

~HITACHI
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51

Application-----------------------------------

floating gate of the EPROM with varying efficiencies. Fluorescent light and sunlight contain some
ultraviolet light, and so prolonged exposure to these
lights can cause data corruption as a result of
electric charge dissipation. Figure 6-7 shows the
standard, data retention time under an ultraviolet
eraser, sunlight and fluorescent lighting.
6.4 Optimized High-Speed Programming
With the increase of EPROM density, the time for
programming becomes more important. The
method for high speed programming has been developed and put into practical use according to
each EPROM generation.
Following explains three methods for High-Speed
programming_
(1) First generation ... conventional programming.
This method is employed in the 3 J.tm and 5 J..!m
process products. Programming is performed with
a uniform pulse of 50 ms per byte. Although it is
the advantage that it applies enough pulse to all
bits, it takes much time to program high density
devices.
High performance
(2) Second generation
programming
This method is employed in 2 J..!m process product.
"High Performance programming (figure 6-8) is

GO
END

performed with a base pulse of 1 ms width. It
repeats programming and reading (verifying) until
the data is programmed enough. There are two
good points in this programming.
First, the programming itself is performed with
optimum program time depending on the capability of each memory cell.
Second, after verification, the data is programmed
using three times as long a pulse and assures highreliability data retention.
(3) Third generation ... Fast High Reliability Programming
This method is employed in the 1.3 J.tm process
products. "Fast High-Reliability Programming"
(figure 6-9) is performed with a base pulse of 0.2
ms. It also shortenes a supplement pulse width to
one-third of that of "High Performance Programming". As a result, this method realizes short
programming time,
reduced
to one-tenth
theoretically.
1 M bit EPROM series employ "Page Programming", which programs 32-bit at once (figure
6-10), reducing programming time to a quarter of
"Fast High-Reliability Programming" for 128k x 8
organization and a half for 64k x 16 organization.
Figure 6-11 shows the programming time of above
methods.

FAIL

Figure 6-8. High-Speed Programming
(High Performance Programming)

Figure 6-9. O.2ms High-Speed Programming
(Fast High-Reliability Programming)

@HITACHI
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--------------------------------------------------------------------Ap~ication

I 50ms programmmg

I
I

10

I
I
I

1ms High-speed

programmmg "
I

2M

32k
Address + I-Address

Storage capaclty( x 8 orgamzatlOn)

4M
(bit)

(Note) Actual program time differs according to
the programmer.
Figure 6-11. Shortened Program Time by HighSpeed Programming.

Figura 6-10_ Page-Mode Programming
(Page Programming)

6_5 Device I ndentifier Code
EPROM programming conditions depend on
EPROM manufacturers and device types, confusion
may cause miss operation_ As a countermeasure
some EPROMs provide device identifier code including such information as manufacture and device
type_ Some newly developed commercial EPROM
programmers can set write conditions automatically
by recognizing this code_
Different programming conditions are as follows:
(1) program voltage, (2) program timing, (3) highperformance programming algorithm, (4) pin configuration_ The Hitachi EPROM has a device
identifier code area besides the memory access area,
as shown in figure 6-12_

•

Data access area

1/0 control CII'CUit

¢

Dou'

Figure 6-12. Device Identifier Code

Table 6-1 describes how to use the device identifier
code. Setting A9 at 12 V and A1 - AS, A 10 - A 13
at V IL access the device identifier code area and
1/00 - 1/07 output the programming condition
code with V IL or V IH of AO_

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53

~iCMlon--------------------------------------------------------------------

Tablel6-1. Hitachi EPROM Device Identifier Code

A.
Manufacturer
Code

ROM
code

Hitachi
V/L
HN27128A
HN27256
HN27C256
HN27C256H V/H
HN27C256A
HN27512
HN27CI024H

1/08-1/015

-

-

-

-

-

1/07 1/06 1/05 1/04 1/03 1/02 1/01 1/00
0
0
0
1
0
0
1
1

0
0
0
0
0
0
0
0

0
0
0
1
1
1
0
1

0
0
1
1
1
1
1
1

0
1
0
0
0
0
0
1

1
1
0
0
0
0
1
0

1
1
0
0
0
0
0
1

1
1
0
0
1
1
0
0

Hex Data
07
OD
10
BO
31
31
94
BA

A9: 12V
Al -AB, AIO -AI3: V/L
Al4, AIS: Don't care

6.6 Shielding Label
When using an EPROM in an environment where it
can be exposed to ultraviolet light, Hitachi recommends putting a shielding label on its transparent lid
to absorb ultraviolet light. In choosing a shielding
label, the following points should be carefully
checked.
Adhesiveness (mechanical strength). Avoid
repeated attaching or exposure to dust that may
reduce the adhesive strength. Ultraviolet erasing
and reprogramming are recommended after
stripping off an attached label. (When the need
arises to change a label, it is advisable to put a
new one on over the old one since peeling may
create a static charge.)
Allowable temperature range. Use the shielding
label in an environment whose temperature falls
within the specified allowable temperature range.
Beyond the specified temperature range, the
paste on the label may harden or stick too fast:
When it hardens, the label may come off easily.
When it sticks too fast, the paste may remain on
the window glass after the label has been removed.
Moisture resistance. Use the shielding label in an
environment whose humidity falls within the
specified allowable humidity range.

*

1. Pin contact check

2.

3.

*

4.

*

6.7 EPROM Programmer
The EPROM programmer stores the user's program
in its internal RAM and writes the program in the
EPROM. For this programming, 3 functions at least
are necessary: blank check function prior to programming, programming function, and the verify
function after programming. Figure 6-13 shows the
programming flow chart. Some programmers check
for pin contact failure or the reverse insertion
before the blank check.
The outline of each block is as follows.

5.

In the ROM pin and socket connection test,
checking is normally performed by detecting the
forward current at each EPROM pin. Care is
necessary as this forward biased resistance differs
in products of each company.
Reverse insertion check
This check detects the reverse insertion of the
device, places the equipment in reset mode and
protects the device and equipment.
Blank check
This check is performed before programming. It
checks whether the device is an erased EPROM,
or it preventing EPROM reprogramming. Since
the output data in the erased condition are 1
(high levell. check whether or not data in
EPROM are all 1. It will fail-stop even when one
bit is 0 (low level). Normally, it is designed to
provide warning with a lamp or buzzer.
Programming
The function of programming the data in the
internal RAM of the programmer into EPROM
will fail-stop when programming cannot be done.
The normal flow is as shown in figure 6-14. The
EPROM data will be read out prior to programming and compared with programming data.
If they coincide, programming will be skipped
and if they differ, programming will be performed. Then, the data will be read out again
and compared with the programming data, and if
they coincide, the programmer will progress to
the next address.
Verify
This function checks after programming com·
pletion whether or not the programming is
correct when comparing with the data in the
internal RAM of the programmer. It performs
fail·stop when they do not coincide. Normally,
when it fails, it lights the fail lamp and displays

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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Application

Figura 6·13. Programming
Flow Chart of EPROM
Programmar (11

Figura 6·14. Programming
Flow Chart of EPROM
Program mar (21

the address and data.
6. How to input the program
Table 6·2 shows several methods for inputting
the program data to the internal RAM of the
programmer. Normally, paper tape input and
teletypewriter input are prefered options.
Tabla 6·2. EPROM Data Input
Method

Content

Copy input

Input by copying the master ROM.

Manual input

Input by the keyswitch on the front
panel. Used for correction or
revision of program

Paper tape input

Read the paper tape furnished
from the host system with the
tape reader

Teletypewriter
input

Input with the teletypewriter.
Preparation, correction, and list
preparation of the program can be
made.

6.8 Handling EPROMs
Touched with a charged human body or rubbed
with plastics or dry cloth, the glass window of an
EPROM generates static electricity which causes de·
vice malfunctions. Typical malfunctions are faulty
blanking and write margin setting that give the false
impression that information has been correctly
written in. As already reported at the international
conferences concerning the reliability of LSI chips,
this is due to the prolonged retention of electric
charge (resulting from the static electricity) on the

glass window. Such malfunctions can be eliminated
by neutralizing the charges by irradiating with ultra·
violet rays for a short time. The EPROM should be
reprogrammed after this irradiation since it reduces
the electric charges in the floating gate, too. The
basic countermeasure is to prevent the charging of
the window, which can be achieved by the following
methods as in the prevention of common static
breakdown of ICs.
1. Ground operators who handle the EPROM.
Avoid using things such as gloves that may
generate static electricity.
2. Refrain from rubbing the glass window with
plastic or other materials that may generate static
electricity.
3. Avoid the use of coolant sprays which contain
some ions.
4. Use shielding labels (especially those containing
conductive substances) that can evenly dis·
tribute established charge.
6.9 Ensuring OTPROM Reliability
ROM
One
time electrically programmable
(OTPROM) has two kinds of packages: standard
dual in·line package (DIP) and small outline package
(SOP). It is one time only programmable because it
has no window for ultraviolet light exposure; testing
by programming and erasure cannot be performed
after it is assembled.
So, Hitachi performs screening test for program·
ming, access time, and data retention on wafers at
proving test.
However, rare defects may occur in the assembly
process cannot be completely removed in final test
screening which is only a reading test.
Therefore, Hitachi recommends that users perform
high temperature baking after programming devices
to ensure high reliability.
Detailed conditions and procedures for screening are
shown in figure 6·15. First, program and verify
devices. Then, leave them without bias at 125 to
150°C for 24 to 48 hours.
After that, check read·out function and remove the
chips with data retention failures.
From the results of devices in which the recom·
mended screening test is properly performed, we
confirm that the data retention characteristics of
OTPROMs are equal to general EPROMs.

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

55

Application-----·--------------------------------Programmmg,

'----,r--.....

Readmg-out

' - - - r - _....

Retention

Da..

Wafer Screenmg

Program and
Venfy

by Programmer

Bakmg at

125 to 150'C

for 24 to 48hrs

Recommended
Screening Conditions

Figure 6·15. Screening Flow Chart of OTPROM

•
56

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

-----------------------.-------------- Application
7. MASK ROM PROGRAMMING INSTRUCTION
The writing of the custom program code into mask
ROMs is performed by the CAD system on a largesized computer. ROM code data should conform to
specifications given below, using either paper tape,
EPROM, or magnetic tape. Additional instructions,
such as chip select and customers' part number,
should be given in the "ROM Specification Identification Sheet"
7.1 Specification of EPROM
1. Submit the three sets of the EPROM-stored data.
Specify the address of the EPROM in the case of
two or four EPROMs.
2. The ROM code data is input from the start
address to Final Address in the EPROM.
3. Type of EPROM
HN482764 (8-kword x 8-bit, 2764 Compatible)
HN4827128 (16-kword x 8-bit, 27128 Compatible)
HN27256
(32-kword x 8-bit, 27256 Compatible)
HN27C256 (32-kword x 8-bit, 27C256 Compatible)
7.2 Specification of Magnetic Tape
1. Use the following type of magnetic tape which
can be used by a magnetic tape device compatible with the IBM magnetic tape device.

Figure 7-1.

Ualll
record

Record Start

5 J

5

Record Typ-,-

3

0

0

o

Address Sal'

J
J
J
J

Data

J
J

Data

J
3

Dati

J
3

Check Sum

0
0
0
0

•
••
8

,
•,
J

5
I

The actual load module mode is shown in figure
7-2.

Magnetic Tape Format

Header
record

Byte Count

Length ..... 2,400 feet, 1,200 feet or 600 feet
Width . . . . . . . . . . . . . . . . . . . . . . . 1!2 inch
Channel . . . . . . . . . . . . . . . . . . . 9 channels
Bit density .... 800 BPI or 1,600 BPI (Clearly
state which it is in the "ROM
Specification
Indetification
Sheet".)
2. Use EBCDIC as the use code.
3. Follow the format of the magnetic tape as described below
No leading tape mark
No label
Record size . . . . . . . . . . . . . 80 byte!l record
Block size . . . . . . . . . . . . . 10 records!l block
The end of the file should be indicated by 2
successive tape marks (TM) (figure 7-1).
4. HMCS6800 load module data mode. This mode
is the object mode output from the assembler
HMCS6800.
Divide the 8-bit code into the upper and lower
4-bit codes, and convert each into hexadecimal
notation.
Example: The code 11000110 is as follows
under binary notation.
(Upper 4-bits)
(Low 4-bits) Bit weight
07060504
030201 DO (ROM output
1 0 0
0 1 1 0 equivalence)

6

0000

5 J

S

5

J

S

J

I

I

J

, ,

J
J

I
6

16

J
J

0
J

oJ

J
J
J
J

I
I
0
0

! 100

J
J
J
J

0
0
0
0

0000

48-H

J
J

44-0

J
J

52-R

18 (Check Sum)

End of
fde record

,, , ,
, o,

• •J
•

0

[TI•

I

J

8

~ck

Fe

( Check

Sum I

Sum)

Figure 7·2 . HMCS68000 Load Module Date Format

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy_ • Brisbane, CA 94005-1819 • (415) 589-8300

57

Application-------------------------------------SO indicates the head of the file and S9 indicates the
end of the file. The actual data starts following S1.
This means that the data starts from the address
(hexadecimal) indicated in the address size. The
address of the address size of the data recorder is

compared with the next data recorder address by
counting in increments of 1 byte of the data and
checking whether it is sequential or not. The
printed example of the HMCS6800 load module
mode is as shown in figure 7·3.

Header Record -+ SO 0 BOO 0 0 5 8 204 5584 I 4 D 504 C B 5
Da ta Reco rd

-+ S I I 3 F 0 0 0 7 E F 5 5 8 7 E F 7 8 9 7 E F A A 7 7 E F 9 C 0 7 E F 9 C 4 7 E 2 4

Da ta Record
End of
FdeRecord

-+ S I I 2 F 0 I 0 FA 6 5 7 E FA 8 B 7 E F A A0 7 E F 9 DC 7 E F A 2 4 7 EO 6
-+S9030000FC
Figure 7·3. HMCS6800 Load Module Example

If an address is skipped, enter the skipped address
into the "ROM Specification Identification Sheet"
and the data (00 or FF) entered into the skipped
address.

5. BNPF mode
One word is symbolized by the word start mark
B, the bit content represented by 8 characters of
P and N, and the BNPF slice composed of succes·
sive 10 characters of the work end mark F.
The contents from F of one BNPF slice up to B
of the next BNPF slice are ignored.
(Example) The code of AA (hexadecimal) is
symbolized as shown in figure 7-4.
It is necessary to designate the bit pattern (BNPF
slice) on all ROM addresses. Therefore, the term
of the ROM head address of "ROM Specification
Identification Sheet" always becomes O.
B . . . . . .. Indicates start of 1 word.
N . . . . . . . . . . . . . . . Indicates 1 bit data.
P . . . . . . . . . . . . . . . Indicates 1 bit of 1 data.
F . . . . . . . . . . . . . . . Indicates end of 1 word.

7.3 Specification of Floppy Disk
1. Use the following type of floppy disk (figure
7·5):
Type .... 8 Inch Single Sided and Single Density
Number of Sectors ....... . . . . . . . . .. 26
Number of Tracks. . . . . . . . . . . . . . . . .. 77
Sector 26

I

Sector 01

Sector 03

Track 00
(lndex' Trackl

Figure 7·5.

Floppy Disk Format

2. Use EBCDIC as the use code.
3. Format the floppy disk as described below.
Composition is described in table 7·1.
Record size . . . . . . . . . . . . . 80 byte/1 record
Table 7·1. Floppy Disk Composition
---------

No.

Item
Stand ard Volume La bel

Location
Track

Sector

00

07

00

08 - 26

01- 73

01 - 26

75, 76

01 - 26

00
74

01 - 06
01 - 26

-

2

Standa. rd Head Label

3

Data Area

- - - - - - - - - 1-----

--

4

-------~---"".

Altern al Track
--_..

_-

Spare Track
Figure 7-4.

BNPF Mode Example

--.-------~-

~HITACHI
58

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

------------------------------------Application

Use the sectors as in figure 7·6. Use one sector
for one record, that is, 80 bytes out of 128 bytes

used for one record.
4. Data Mode. See data mode for magnetic tape.
1 Track

Sector 1

Sector 2

Sector 3

Record I

(80 bytes)

Figure 7-6.

Check

Figure 7·7.

Floppy Disk Sector Format

~.

unused

OK

Mask flOM Development Flowchart

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

59

Application
8. INSTRUCTIONS FOR USING MEMORY
DEVICES
8.1 Prevention of Electrostatic Discharge
As semiconductor memory designs are based on a
very fine pattern, they can be subject to malfunction or defects caused by static electricity. Though
the built-in protection circuits assure unaffected reliability in normal use, devices should be handled
according to the following instructions:
1. I n transporting and storing memory devices, put
them in conductive magazine or put all pins of
each device into a conductive mat so that they
are kept at the same potential. Manufacturers
should give enough consideration to packing
when shipping their products.
2. When devices touch a human body in mounting
or inspection, the handler must be grounded. Do
not forget to insert a resistor (1 MQ appro x is
desirable) in series to protect the handles from
electrical shock.
3. Keep the relative ambient humidity at about 50%
in process.
4. For working clothes, cotton is preferrable to
synthetic fabrics.
5. Use a soldering iron operating at low voltage (12
V or 24 V, if possible) with its tip grounded.
6. In transporting the board with memory devices
mounted on it, cover it with conductive sheets.
7. Use conductive sheets of high resistance (about
109 ohm/D) to protect devices from electrostatic
discharge. For, if dropped onto conductive
materials like a metal sheet, devices may deteriorate or even breakdown owing to sudden
discharge of the charge stored on the surface.
8. Never set the system to which memory devices
are applied near anything that generates high
voltage (e.g. CRT Anode electrode, etc.).

8.2 Using CMOS Memories
As shown in figure 8-1, the input of a CMOS
memory is connected to the gate of an inverter consisting of PMOS and NMOS transistors. Figure 8-2
shows the relationship between the input voltage
and current in this inverter. The top and bottom
transistors turn ON and make current flown when
the input voltage becomes intermediate level. Therefore, it is necessary to keep the input voltage below
0.2 V or above Vee - 0.2 V in order to minimize
power consumption. The data sheet specifies the
stand-by current for both the cases of input level
with minimum V 1H and maximum V 1L and that
with 0.2 V or Vee - 0.2 V, and the difference in
value is remarkably great. Some memory devices

are designed to cut off such current flow in standby
mode by the control of input signals, but it depends
on device type. This should be confirmed in data
sheets for each device type.

Figura 8-1.

CMOS Invarter

-E;: 5I1CC~5'OV
~ 4
3

~

11
~
8

2
1

0123456
Input Voltage

Figure 8-2.

Relationship between Input Voltage & Currant
In CMOS Inverter

Another problem particular to CMOS devices is
latch-up. Figure 8-3 shows the cross section of a
CMOS inverter and the structure of a parasitic
bipolar transistor. The equivalent circuit of the
parasitic thyristor is shown in figure 8-4. When
positive DC current or pulse noise is applied (figure
8-4 (a»), TR3 is turned on owing to the bias voltage
generated between base and emitter. And trigger
current flows into GND through R p , the base resistance of TR2. As a result, TR2 becomes conductive and current flows from power supply (V cd
through the base resistance of TR 1 (R N l. which
puts TR 1 into conduction, too. Then, as the base
of TR2 is rebiased by collector current from TR 1,
the closed loop consisting of TR 1 and TR2 reacts.
Thus current flows constantly between power
supply (Vee) and GND even without trigger current
caused by outside noise.
Latch-up can be caused by a negative pulse, too
(figure 8-4 (bb». Most of semiconductor memory
manufacturers are trying to improve latch-up immunity of their products. Hitachi provides enough
guard band by applying diffusion layer around
inputs and outputs, taking care not to connect input
to p+ diffusion layer. Input voltage for 64 kbit

@HITACHI
60

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

--------------------------------------Application
static RAM HM6264A, for example, is specified as
follows:
V 1H max 6.0 V (not depending on Vee!
V 1L min 3.0 V
(pulse width = 50 ns)
-0.3 V (DC level)

Thus almost no consideration for latch·up is required in system design.

Pm

(a)

(b)

Figure 8-3.

Cross Section Structure of CMOS Inverter
Closed Loop

j--Vc;--l

Pm

Vee

P,n

I
I

Rn:
I

I
I

L-H~.rTu:
I
I
I

I

I
Till

I
:
ON L ______ .J

(a) Thynstor Effect by
Positive Voltage

Figure 8-4.

(b) Thynstor Effect by
Negative Voltage

Equivalent Circuit of Parasitic Thyristor

8.3 Noise Prevention
Noise in semiconductor memories is roughly clas·
sified into input signal noise and power supply
noise.
8.3.1 Input Signal Noise
In.put signal noise is caused by overshoot and undershoot. If either of them is out of recommended DC
operating conditions, normal operation is hindered,
and voltage over absolute maximum rating will
break the device. In operating high speed systems,
special care is required to prevent input signal
noise.
The noise can be prevented by inserting a serial resistance of less than 50 ohm into each input or a
terminating resistance into the input line. Actually,
however, input signal noise can be simply reduced by
a stable power supply line, because it is often caused
by unstable reference voltage (GND level).

8.3.2 Power Supply Noise
The power source noise can be classed as lowfrequency noise and high-frequency noise as shown
in figure 8-5. To assure stable memory operation,
the peak-to-peak power supply voltage in the presence of low-or high-frequency noise should be held
below 10 percent of its standard level.
1lIP-~NOIR

NotMorethulIO%alStandan!
Power Supply Vo_

~ftftn,,~L
-f--~:~r

Low-frequenQ'

NOIR

NOI MOft tIwI10% of StMd-rd POwtl'

Supply VollaIt'

Total of Low-1IMi ibah-irequeIIc),
Not Mwe than + 10% of StalIdatd Pewer
Supply Voicue

Figure 8-5.

Power Source Noise

~HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

61

Application-------------------------------------Devices like dynamic RAMs, which operate from
clock signals, or high speed CMOS static RAMs,
through which current flows during transition of
signals, consume high peak current. When a power
supply does not have enough capacity for the peak
current, voltage drops. And if the recovery rate of
the power supply synchronizes with its time con·
stant, it may start oscillating. To reduce the in·
fluence of the peak current, a bypass capacitor of
0.1 - 0.01 JlF should be inserted near the device.
The following points must be considered in design·
ing pattern of the board:
For bypass capacitors, use titanium, ceramic, or
tantalum capacitors which have better high-

*

*

*
*

frequency characteristics.
Bypass capacitors must be applied as near to the
power supply pin of memory devices as possible,
and inductance in the path from Vee pin to V55
pin through the bypass capacitor must be as little
as possible.
The line connected to the power supply on the
board should be as wide as possible.
It is preferrable for the power supply line to be
at right angles to devices selected at the same
time, lest too much peak current should flow
through one power supply line at a time.

Non~preferred

Preferred

CS
Signal

f":~5;:~~~

-Faults1 Bypath Lmes are too
Long
2. Devices Selected at

~~~==~~ S~:~~h:i~
Vee

V~S Vee Vss Vee

Vss

~~~-~

Vee

Vss

~

Data I/O

Figure 8-6.

Data 110

Examples of Power Supply Board Pattern

8.4 Address Input Waveform of Hi-BiCMOS
Memory
Data stored in memory might be destructed in case
that Address Input of the HM6716, HM6719,
HM6787, HM6788 and HM6789 series becomes
floating and sticks at and around threshold voltage.
(e.g. CPU does Address Bus to off state in Figure 1.)
Consequently, the following three methods are recommended so as to preserve malfunction of
memory device.
A: Insert latch as shown in Figure 8-7 lest Address
Input should become floating.
B: Put CS into High while Address Input becomes
floating.
(Dotted line in Figure 8-8)
C: Insert Pull-up Resistor (R) to hold time
constant of R ising Edge wave form of Address
Input pin (tr = R x C) below 150 ns.
Stable operation can be assured if you have already
adopted the above three method (A, B, C), while
if you have any problem, please contact our sales
offices.

Pull-up

Resistor

CPU
Address
Bus

I-r----~-,

.s:;

CS

Input

I

..I

I

Control

Memory

;l I
.. I

L __

I
J

I

L_________________ .J
Figure 8-7

xPt
4

Address - - - - ;
Input

\

_ _ _~

'-_ _ _ __

r------,
CS

/

\

(

Write

\

Floating

Figure 8-8

~HITACHI
62

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

Read

Section 1
MOS Static RAM

.HITACHI®
63

HM6116 Series----Maintenance Only
204B-word x B-bit High Speed CMOS Static RAM
.FEATURES
•
•
•

•
•
•
•
•

HM6116l'Senes

Single 5V Supply
High speed: Fast Access Time
120ns/150ns/200ns (max.)
Low Power Standby and Low Power Operation
100~W (typ.)
Standby:
10~W (typ.) (L-version)
200mW (typ.)
Operation:
175mW (typ.) (L-version)
Completely Static RAM:
No clock or Timing Strobe Required
Directly TTL Compatible: All Input and Output
Pin Out Compatible with Standard 16K EPROM/MASK ROM
Equal Access and Cycle Time
Capability of Battery Back Up Operation (L-version)

(DP-Z4)

HM6116FP Senes

.ORDERING INFORMATION
Type No.

Access Time

HM6116P·2
HM6116P·3
HM6116P·4

120n8
150n8
200n8

HM6116LP·2
HM6116LP·3
HM6116LP·4

120n8
150n8
200n8

HM6116FP·2
HM6116FP·3
HM6114FP·4

120n8
150n8
200n8

HM6116LFp·2
HM6116LFp·3
HM6116LFP·4

120ns
150ns
200n8

Package

600mil24pm
Plastic DIP

24pin Pla8tic SOP
WI' 241))

.PIN ARRANGEMENT
.FUNCTIONAL BLOCK DIAGRAM
----..0
Nemory Matr1x

Vee

---OVss

128 x 128

110,0--.......-1

110. 0----1~_I

WE o---'L.!-±-I
Note' This device is not available
for new application.

~HITACHI
64

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6116 Series
.ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Voltage on An)' Pm Rt"latlve to

V,,,

Storage Temperature

Storage Temperature Under Bias

Power DISSipation

*I

Unit

0.5" to +7 0
o to +70
-55 to +125
-10 to +85
10

T.,.
To,.

Operating Temperature

~Htel

Rating

V,

T....
p,

V

·c
·c
·c
W

3 5\ for pul-.e .... Idth <;. 11111'"

.TRUTH TABLE
OF.
x

CS
H

WE

Mode

x

Not Selected

In.

Ref. Cycle

1/0 Pin

Vee Current

High Z

lUI

Read Cycle 11)-(3)

L

L

H

Read

Icc

Dout

L

H

L

Write

Icc

DIn

W rite Cycle 11)

L

L

L

Write

Icc

DIn

Write Cycle (2)

.RECOMaENDED DC OPERATING CONDITIONS (Ta-O to +70'C)
Item
Supply Voltage

Input Voltage
Note) *1 -3 OV for pul&e

typ

max

Unit

Vee

4.5

5.0

5.5

V

Vs;

0

0

0

V

Vi.

2.2

3.S

6.0

V

V/L

-0.3"

-

0.8

V

Symbol

min

wldth~5nns

.DC AND OPERATING CHARACTERISTICS (Vcc=5V ± 10%. Vss=OV. Ta=O to +70T)
HM6116-Z
Symbol

Test CondItions

Input Leakage Current

JILlJ

Vee = 5.5V, VIN = Vss to V(e

Output Leakage Current

IlLol

Item

Operatmg Power Supply
Current

Icc
[cn"'2

Average Operating Current

Standby Power Supply

Icc,
ISB

CS= VIH or OE= VIH,

V, '0 = Vs; to Vee

[S81

VOL
Output Voltage

VOH

typo,

max

-

-

-

-

Unit

mm

typO'

10

-

-

10

Z03

-

-

Z0 3

10

-

-

10

Z0 3

-

-

Z03

max

-

40

80

-

35

70

-

35 03

70. 3

-

30. 3

60*'

VIH=3.5V, VIL=0.6V,

-

35

-

-

30

Iuo=OmA

30 03

-

-

Z5*'

-

Mm. cycle, duty = 100%

-

40

80

-

35

70

Iuo=OmA

-

35. 3

70 03

-

30. 3

60. 3

-

5

15

-

5

15

4. 3

lZ· 3

-

4. 3

lZ· 3

CS= VIL, Iuo=OmA

CS= VIH

/-lA

/-lA

rnA

rnA

rnA

rnA

IOL=4mA

-

-

04

-

-

-

V

IOL=Z.lmA

-

-

-

-

-

0.4

V

IOH=-l.OmA

Z4

-

-

Z.4

-

-

V

CS~

Current

HM6116·3/ -4

mm

Vee-OZV, OV;;> VIN;;>

O.ZV or VeL - 0 ZV;;> VIN

Z

-

Z·3

50 03

-

Z·3

0.02

O.OZ

Z
50. 3

/-lA

Notes) *1 Vc.c =5V. Ta=2S0C
• 2 Reference Only
.3 ThiS charactenstlcs are guaranteed only for L·verSlon

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

65

HM6116 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

.CAPACITANCE (j=lMHz, Ta=2S'C)
Symbol

Test Conditions

typ

max

Unit

Input Capacitance

C..

v..-OV

3

5

pF

Input/Output Capacitance

ClI'O

\-I",-OV

5

7

pF

Item

Note} This parameter

IS

sampled .nd not 100% tested

.AC CHARACTERISTICS (Vcc =5V±10%, Ta=O

to

+70'C)

eAC TEST CONDITIONS
Input Pulse Levels: 0.8 to 2.4V
Input R,se and Fall T,mes: 10 ns
Input and Output TIming Reference Levels: I.SV
Output Load: lTTL Gate and CL (100pF) (Including scope and jig)

eREAD CYClE
HM6116-2

Item

HM6116-3

HM6116-4

Symbol

UOlt

mon

max

mIn

max

mon

max

Read Cycle Time

he

120

-

150

-

200

-

ns

Address Access Tune

I"

-

120

-

150

-

200

ns

Chip Select Access Time

tACS

-

120

-

150

-

200

ns

Chip Selection to Output In Low Z

teLz

10

-

15

-

15

-

ns

Output Enable to Output Valod

10£

-

80

-

100

-

120

ns

Output Enable to Output in Low Z

tOLZ

10

-

15

-

15

-

ns

Chip Deselectlon to Output on HIgh Z

'CHZ

0

40

0

50

0

60

ns

Chip DIsable to Output on HIgh Z

10HZ

0

40

0

50

0

60

ns

Output Hold from Address Change

10.

10

-

15

-

15

-

ns

eWRITE CYClE
Symbol

HM6116-4

HM6116-3

HM6116-2

Item

mIn

max

mIn

-

150

W rite Cycle Time

Iwe

120

Chip Selection to End of Write

lew

70

Address Valid to End of Wrote

I.w

Address Set Up T,me

lAS

105
20

W rote Pulse Width

Iw,

W rite Recovery Tune

Iw,

Output DIsable to Output on HIgh Z

tOHZ

70
5
0

W rote to Output on HIgh Z

tWHZ

0

40
50

Data to W nte Tune Overlap

low

Data Hold from Write Time

10.

35
5

-

10
0
0
40
10

Output Active from End of Write

low

5

-

10

90

120
20
90

max

min

max

200

50

60

-

120
140
20
120
10
0
0
60
10

ns
ns

-

ns
ns
ns

-

ns

60
60

ns

-

ns

10

.TIMNG WAVEFORM
eREAD CYClE (1)'1)

~HITACHI
66

UnIt

Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

ns
ns
ns

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6116 Series

-READ CYCLE (2)'''''' ( I )

Addnn

oOtU

-READ CYCLE (3)"'(3""

DOIlI

NOTES: 1.
2.
3.
4.

W[ is High for Read Cycle.
Device is continuously selected. ~= VIL'

Address Valid prior 10 or coincident with ~transilion Low.

tm"= VIL'

• WRITE CYCLE(1)

1--------,.,:--------1
AcId,...

'AI
I-___ ,"!.!(l~)_ _~

110.,

I) ••

_ ________ ~L_'·_·--"'~I~~
<1-

•

4XXX

HITACHI

Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300

67

HM6116Series----------------------------------

-WRITE CYCLE(2)'"
Address

Dou.

Din

NOTES:

_________________~r--'
.-----'-D·~~~(~8)~~~
C
l>OO0.2V

2.0

-

-

Vcc~30V,CS"'28V. VlH~2.8V

or OV;; VlN;iO.2V

See Retention Waveform

0
t 11("'2

-

pA

-

ns

-

ns

iRe -= Read Cycle TIme

_ Low Vee Data Retention Waveform

4SV---------

1--_____-"0.,,''-'",R'c.:""""",,,::c"..::M,,,"'o..'- - - - - 1 r------------------------------

------------.

V"

~

_ _ _....J

w-------------------------------------------

.HITACHI
68

V

30

IO.uA max at Ta=O'C to + 40'c' VIL rum:=. -- O.3V

Va _ _ _ _ _ _ _--,

Unit

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

HM6116A Series---Maintenance Only
2048-word x 8-bit High Speed Static CMOS RAM
• FURTURES
• High speed: Fast Access Time 120nsl150ns/200ns (max.)
• Low Power Standby and
Standby:
100~W (typ.)
Low Power Operation
5~W (typ.) (L·version)
Operation: 15mW (typ.) (f = 1 MHz)
10 mW (typ.) (L·version)
• Single 5V Supply and High Density 24 Pin Package
• Completely Static RAM: No clock or Timing Strobe Required
• Directly TTL Compatible: All Input and Output
• Pin Out Compatible with Standard 16K EPROM/MASK ROM
• Equal Access and Cycle Time
• Capability of Battery Back Up Operation (L·version)

HM6116AP Series

---I

)

(Top View)

I/O. -r---t+-t>-+--I

~-b-~=t-t:--------~
WE o---+iDl--i

~----~~~~--~
Note) This device is not available for new application.

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

69

HM6116A S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Vohlle' on Any PIR Relative to Vs.s

V,

Ope rat

Storale Temperalure

T...
T...

Storage Temperature Under Bias

T....

Pown DIssipation

p,

Note)

lA, Temperature

Rating

--0.5"

Unit

+70

V

+70
-55 10 + 125
-10 10 +85

·c

I 0

W

10

o 10

* 1 --35V for pulse wldth;iSOns

·C
·C

.TRUTH TABLE
CS

OF.

WI-:

Mod.

H

x

x

~ol Sf-Ie-tIed

L

L

H

R..d

Icc

Doul

R..d Cyel. 111-131

L

H

L

Wnce

I"

Dan

W nl. Cyel. I II

L

L

L

Write

Icc

D.n

Wnl. Cyel. 121

Iu.

R.I. Cyel.

I/O P,n

Vcr Current

H•• h Z

lUI

.RECOMMENDED DC OPERATING CONDITIONS (To-O to +70"()
Iyp

max

Unlt

Vee

4.5

5.0

5 5

V

Vss

0

0

0

V

3.5

6.0

V

-

0.8

V

Symbol

Item

m.n

Supply Volta ••

v,.

Inpul Volta••

2.2
-03"

V"
Note)

*1

- 3 OV for pulse

wldth~50ns

• DC AND OPERATING CHARACTERISTICS (Vee

= 5V ± 10%,

HM6116A-12
min typO' max

Vss

= OV, Ta =0 to +70°C)

Symbol

Test Condition

Input Leakage
Current

IILII

Vee=5.5V, Vin=VSS
to Vee

-

-

2

-

-

Output Leakage
Current

11£0 1

CS= VIH or OE= VIH,
VI/O= VSS to Vee

-

-

2

-

-

CS= VIL,lJ/o=OrnA
Vin = VIH or VIL

-

Item

---

Icc

Operating Power
Supply Current

Average Opera ling
Current
Standby Power
Supply Current

Output Voltage

Iee2
ISB

CS=VIH

-

ISBl

CS~ Vee-0.2V
OV;::;Vin

-

VOL

IOL =4rnA

-

2.4

VOH

IOH= -I.OrnA

2

-

-

2

fJA

2

-

-

2

fJA

5
4"

15
12*'

-

5
4,2

15
12,2

rnA

-

3

-

2,2

15
12*'

-

6

-

3

6

-

3

6

-

2'2

5*'

-

2*'

5*'

-

45
25
20'2 40'2

-

20
15'2

35
30*2

rnA

4
3"

rnA

0.02
2
1'2 50"

rnA
fJA

5"
60
35
30*2 50'2
1
0.5*'

4
3*'

-

-

5
4"

1
0.5"

-

4
3"

-

2

-

1
0.5"

-

0.02

I"

50"

-

0.4

-

-

0.4

-

-

0.4

V

-

-

2.4

-

-

2.4

-

-

V

OHITACHI
Hitachi America, Ltd.

0

Hitachi Plaza

0

rnA

2
0.02
1*' 50'2

Notes) *1. Vee=5V, Ta=2SoC
*2. This characteristics is guaranteed only for L-version.

70

Unit

-'"--

VIH=Vee, VIL=OV,
CS=VIL'
II/O=OrnA.J=IMHz
min. cycle,II/O-OrnA
duty = 100%

Ieel

HM6116A-20
min typO' max

HM6116A-15
min typO' max

2000 Sierra Point Pkwy.

0

Brisbane, CA 94005-1819

0

(415) 589-8300

-------------------------------------------------------------HM6116AS.IH
.CAPACITANCE (f-lMHz. Ta-2S'C)
Item
Input Capacltanc.

Sylllbo'

Test Cond,tIOns

typ

C..

v..-OV
v,.,-OV

3
5

Input/Output CapacItance

C".

....

UnIt

5

pF

7

pF

Not.) Thll par....eter .1 .. mpled .nd not 100% telted

.AC CHARACTERISTICS (Vcc-SV±IO%. Ta-O to +70'Cl
eAC TEST CONDITIONS
Input Pulse Levels: 0.8 to 2.4V
Input RIse and Fall Times: 10 ns
Input and Output TImIng Reference Levels. 1.SV
Output Load. lTTL Gale and CL • l00pF (,nclud,ng scope and Jlgl

• READ CYCLE
Item
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Selection to Output iIr Low Z
Output Enable to Output Valid
Output Enable to Output in Low Z
Chip Deselection to Output in Hlah Z
Chip Disable to Output in Hi8h Z
Output Hold from Address Change

HM6116A-12

HM6116A-15

HM6116A-20

max

min
200

max

-

min
ISO

max

tRC

min
120

tAA

-

120
120

-

ISO
ISO

-

200
200

Symbol

Unit

-

tACS

-

tCLZ

10

-

10

-

10

tOE

-

S5

-

60

-

10
0
0
IS

-

10
0
0
20

tOLZ
lCHZ
10HZ
tOH

10
0
0
10

40
40

-

SO
SO

-

-

-

70

60
60

-

ns
ns
ns
ns
ns
ns
ns
ns
ns

• WRITE CYCLE
Item
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Set Up Time
Write Pulse Width
Write Recovery Time
Output Disable to Output in Hi8h Z
Write to Output in Hlah Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write

Symbol
twc
tew
tAW
tAS
twp
tWR
10HZ
tWHZ
lDW
tDH
tow

HM6116A-12

HM6116A-15

HM6116A-20

min
120
70
lOS
0
70
0
0
0
35
0
10

min
ISO
90
120
0
80
0

min
200
120
140
0
100
0
0
0
SO
0
10

max

-

-

-

40
35

-

-

0

max

-

SO
40

0
40
0
---10 --

Unit

max

-

60
SO

-

-

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

.TIMING WAVEFeRM
eREAD

eva.E (1)(1)

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

71

HM8118ASWi•• ---------------------------------------------------------------eREAD CYa.E(2)'1)'2''''

eREAD Cya.E (3)'1)"""

NOTES: I. ftis Hiah for Read Cycle.
2. Device is continuously selected, ~= V/L.
3. Address Valid prior to or coincident with ~transition Low.
4. OE". VIL'

eWRITE CYCLE(1)

Address

twp,;:,.ll...:.'_--I

~ut ~~~~~--~--~~--~+----------_________________

~~~~-w----t-DH-~~~+~~~

Din

•
72

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

-------------------------------------------------------------HM8118ASeriM
eWAlTE CYCLE(2)'"
~------------twc-------------i

Address __

-JI~

_____________________ J

Din

NOTES: J. A write occurs during the overlap (t.ll!.f) of a low ~ and a 10w"WE".
2. t IIIR is measured from the earlier of CSor WE" going hiah to the end
of wrile cycle.
3. During this period, 1/0 pins are in the output state so thaI the input
sianals of opposite phase 10 the outpuls must not be applied.
4. If the CS" low transition occurs simultaneously with the WE" low
transitions or .fter the WE transition, outpul remain in a hich impedance state.
S. llI"is continuously low. (Dr .. VIL)
6. Dout is t"e same phase of write data of this write cycle.
7. DO.ll1.is lhe read data of next address.
8. If CS is Low durinc this period, 1/0 pins are in Ihe output state.
1lIen the data input sianals of opposite phase 10 the outputs must
not be applied 10 them .

• LOW Vee DATA RETENTION CHARACTERISTICS

(To-O to +70'C)

This characteristics is guaranteed only for L-version.
he..
Vcc for Dato Retenllon
Data Retenllon Current
ChIp De.elect to Doto RetentIon Til""
Operation Recovery T,me

..
Notes)*110JJAmaxatTa-OCto

t-40C,Vll.lnlO

Symbol

V••

Test Conditions
~~V" -O.ZV

Iccu· 1 Vee-3.0V. CS~2.8V, OV;;; VtN
Ie ..
h

See Retention Waveform

mI.
2.0

0

, .,.2

typ

-

--

U.,t

30

/AA

-

-

-

V

••
.1

-03V

.2 lie = Read Cycle Time

eLow Vee Data Retention Walleform
V" _ _ _ _ _ _ _ _"\ I-_________..!Ilo:!!.!...

!:Ro~
..~
••~
...~IW:!!.c-

_______ I , -_ _ _ _ _ __

tSV---------

C!---...I

w-- ________________________________________ _

$

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

73

HM6716 S e r i e s - - - - Maintenance Only
HM6719 Series
2048-word x 8-bit High Speed Hi-BiCMOS Static RAM (with OE)
2048-word x 9-bit High Speed Hi-BiCMOS Static RAM (with OE)
• Features
• Fast Access Time: 25/30ns (max)
• Low Power Dissipation (DC): 280mW (typ.)
• +5V Single Supply
• Completely Static Memory No Clock or Timing Strobe Required
• Balanced Read and Write Cycle Time
• Fully TTL Compatible Input and Output

• ORDERING INFORMATION
Type No.

Access Time

HM6716p·25
HM6716P-30

25ns
30ns

HM6719P-25
HM6719P-30

25ns
30ns

•

Package

(DP-24NC)

300 mil 24 Pin
Plastic DIP

•

•

A,o---C;C:J
(

Row

)

)

Decoder

Memory Matrix

HM6716

A7
A6
As
A_
A3
A2
Al
Ao

Block Diagram

(

PIN ARRANGEMENT

--<>Vcc
--<>YSS

A!O~-~----'

Vee

As
A9
WE
OE

A,o
CS
lias
1107
1/0 6
vas

VOl
V02

1/0 3

110_

Yss

(Top View)

•

HM6719

vee

A7
A6
As
A_
A3
A2
A,
Ao

• Absolute Maximum Ratings
Item
Terminal Voltage to YSS Pin
Power Dissipation
Operating Temperature Range
Storage Temperature Range

Symbol

VT
PT
Topr
T. tll

Rating
-0.5 to +7.0
1.0
oto +70
-55 to +125

$
74

Unit
Y
W

°c
°c

As
A9
WE

CS
AIO
1109

lias
110 7

110,
110 2

1/06

V03

1105

YSS

110,

(Top View)

HITACHI

Hitachi America, Ltd • Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819' (415) 589-8300

- - - - - - - - - H M 6 7 1 6 . HM6719 Series

• Truth Table
e HM6716

L

WE
Hor L
H
L
L

Mode
Not selected
Read
Write
Write

H

H

Output Disabled

CS
H
L
L
L

OE
Hor L
L

L

H

V cc Current

Pin
HighZ
Dout
Din
Din
High Z

ISB.ISBI
ICC. ICCI
ICC. ICCI
Icc'/CCI
ICc. ICC],

Ref. Cycle

Read Cycle (1) (2) (3)
Write Cycle (1)
Write Cycle (2)
-

eHM6719
WE
Hor L
H
L

CS
H
L
L

Mode

VCC Current

Not selected
Read
Write

ISB'/SBI
ICC'/CCI
ICC'/CCI

- Recommended DC Operating Conditions (Ta
Item
Supply Voltage
Input High Voltage
Input Low Voltage
*)

Symbol

VCC
VSS
VlH
VIL *)

Ref, Cycle

I/O Pin
High Z
Dout
Din

Read Cycle (2) (3)
Write Cycle (2)

=0 to +70°C)

min
4,5

typ

max

Unit

5,0

5,5

V

0.0

0.0

0.0

V

2.2

-

6.0

V

-3.0

-

0.8

V

Pulse Width: 20ns, DC: -0.5V

- DC and Operating Characteristics (Vee
Item

= SV ± 10%. Ta =0 to +70°C)

Symbol

min

typ

Input Leakage Current

IILl I Vcc=5.5V. VIN= Vssto Vee

Test Conditions

-

-

max
2

Unit

Output Leakage Current

Ihol CS=VIH • Vl/O= VSS to Vee

-

2

/J A

Operating Power Supply Current

Icc

120

rnA

Average Operating Current

ICCl

130

rnA

30

rnA

/J A

CS=VIL.II/O=OmA
Min. Cycle, Duty: 100%ljIO=OmA

-

ISB

CS=VIH
CS ~ VCc-0.2V

-

-

ISBI

VIN~0.2Vor VJN~ Vcc-0.2V

-

-

10

rnA

Output Low Voltage

VOL

-

0.4

V

VOH

IOL=4mA
Ioif-lmA

-

Output High Voltage

2.4

-

-

V

Standby Power Supply
Current

-AC Test Conditions
Input pulse levels: Vss t03.0V
Input and Output reference levels: 1.5V
Input rise and fall time: 4ns
Output Load: See Figure

+5V

~

Dout

6200

9100

+5V

~

9100

Dout
30pF*

6200

5pF*

*including

scope and jig

Output Load A

Output Load B
(ICHZ. IWHZ, Icu. lOw. IoU, I(JHz)

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

75

HM6716. HM6719 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Capacitance (Ta = 2S oC.f= 1.0 MHz)
Item
Input Capacitance
I/O Capacitance
Note)

Symbol

Test Conditions

min

typ

max

Unit

CIN

VIN=OV

pF

CliO

-

6

Vl/O=OV

-

8

pF

Unit

Notes

This parameter is sampled and not 100%. tested.

-AC Charac1eristics (Vee SV ± 10%, Ta
.Read Cycle
Item

=0 to +70°C, unless otherwise noted.)
Symbol

HM6716-25
HM6719-25
min

HM6716-30
HM6719-30

max

min

max

Read Cycle Time

tRC

25

-

30

-

ns

-

Address Access Time

tAA

-

25

-

30

ns

Chip Select Access Time

tAcB

-

-

25

-

30

ns

tCLZ

0

-

0

-

ns

*2

tOE

0

20

0

20

ns

*1

Output Enable to Output in Low Z

tOLZ

0

-

0

-

tCHZ

0

10

0

12

ns
ns

*1.*2

Chip Deselection to Output in High Z
Chip Disable to Output in High Z

tOHZ

0

10

0

10

ns

*1.*2

Output Hold from Address Change
Input Voltage Rise/Fall Time

tOH

5

-

5

-

tT

-

150

-

150

ns
ns

*3

Unit

Notes

Chip Selection to Output in Low Z
Output Enable to Output Valid

*2

-

• Write Cycle
Item

Symbol

HM6716-25
HM6719-25
min

HM6716-30
HM6719-30

max

min

max

Write Cycle Time

twc

2S

-

30

-

ns

-

Chip Selection to End of Write

tcw

20

-

25

-

ns

-

Address Setup Time

tAS

0

-

0

-

tAW

20

-

25

-

ns

Address Valid to End of Write

ns

-

Write Pulse Width

twp

20

-

25

-

ns

-

Write Recovery Time

tWR

0

-

0

-

ns

-

Output Disable to Output in High Z

tOHZ

0

10

0

10

ns

*1. *2

Write to Output in High Z

tWHZ

0

10

0

12

ns

*2

Data Valid to End of Write

tDW

15

15

-

ns

tDH

5

5

-

-

Data Hold Time

-

ns

-

Output Active from End of Write

tow

0

-

0

-

ns

*2

Notes) *1. These parameters are for HM6716.
*2. Transition is measured t200mV from steady state voltage with Load(B).
This parameter is sampled and not 100% tested.
*3. If tT becomes more than 150ns, there is possibility of function fail.
Please contact your nearest Hitachi's Sale Dept. regarding specification.

•
76

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 1 6 , HM6719 Series
•

Timing Waveforms
Read Cycle (1)'1

•

- - - - - - - tRC - - - - - - -

....---- tAA ------..M'

•

•

tACS----r-~1

~u

~~~--~~~

Dout--------------------------~

High impedance

•

Read Cycle (2) '1, '2, '4

.-tRC~t

Address

~

.~=======1~==~~-----

-~-H---­

+--~H

Dout

•

Previous Data Valid

Data Valid

Read Cycle (3) '1,'3.'4

cs

~,~

tRC

t~"z+
\

Dout

Data Valid
High impedance

Notes)

*1.
*2.
*3.
*4.

WE is High for Read Cycle.
Device is continuously selected, CS=V,L' _
Address Valid prior to or coincident with CS transition Low.
OE=V,L.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

77

HM8716.HM6719Senn----------------------------------------------------•

Write Cycle (1)

1+------- twc

------.~

Address

1*1

~--twp

~

r-----

High Impedance

Dout~~~-+-+~~~------------------~--------------

$
78

HITACHI

Hitachi America, ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 1 6 . HM6719 Series
• Write Cycle (2)·5
~----------twc---------~

Address

,..------

WE ---t-~~~"'.I...I _ _ -

h

Din----------«~

tDW

tDH J:8

oat: ~>f()O()()(

Notesl -1. A write occurs during the overlap (~I of a low CS and low WE.
-2. tWR is measured from the earlier of CS or WE going high to the end
of write cycle.
-3. During this period, I/O pins ere in the outPut state so that the input
signals of opposite ph_ to the outputs must not be applied.
-4. If the ~ low transition occurs simulteneously with the WE low tran·
sitions or after the WE transition, output remain in a high impedance
state.
-5. ()E is continuously low. (5'EmV'LI.
-6. Dout is the same phase of write data of this write cycle.
-7. Dout is the read data of next address.
-S. If ~ is Low during this period, I/O pins are in the output state.
Then the data input signals of opposite phase to the outputs must
not be appliad to them.

$

HITACHI

Hitachi America, ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy•• Brisbane, CA 94005-1819 • (415) 589-8300

79

HM6268 Series

II

4096-word x 4-bit High 'Speed CMOS Static RAM
-FEATURES
•
•
•

Single 5V Supply and High Density 20 Pin Package.
High Speed: Fast Access Time 25/35/45ns (max.)
Low Power Standby: 100~W typ, 5~W typ (L·version)
Active: 250mW typo
• Completely Static Memory: No Clock or Timing
Strobe Required
• Equal Access and Cycle Times
• Directly TTL Compatible - All Inputs and Outputs
• Capability of Battery Back Up Operation (L-version)

IDP-20N)

J

'--------

.ORDERING INFORMATION
Type No.

25ns
35ns
45ns

HM6268LP-25
HM6268LP-35
HM6268LP-45

25ns
35ns
45ns

.PIN ARRANGEMENT

Package

Access Time

HM6268P·25
HM6268P·35
HM6268P·45

300ml120pm
Plastic DIP

.BLOCK DIAGRAM
-

Vee

Memory Array

64 Row:,
Row Decoder

256 Columns

.ABSOLUTE MAXIMUM RATINGS
Symbol

Rating

VT

-0.5"1 to +7.0

V

Power DISSipatIon

PT

1.0

W

OperatIng Temperature

T.,.

+70

·C

Storage Temperature

T.I,

-55 to +125

Temperature under Bias

T.,..

-10 to +85

·c
·c

Item
Voltag.. on Any Pin Relative to

Note)

*I

Vss

o to

Unit

-3 5V for pulse wldth;;,ilOns

.HITACHI
80

Hitachi America, Ltd_ • Hitachi Plaza' 2000 Sierra Point Pkwy_ • Brisbane, CA 94005-1819 • (415) 589-8300

------------------------------------------------------------HM6288S.~

.TRUTH TABLE
CS

WE

Mode

Vee Current

I/O Pm

Ref Cycle

H

x

Not Selected

ISB.IsB'

H'ghZ

-

L

H

Read

lee

Dout

Read Cycle

L

L

Wnte

lee

Dm

Wnte Cycle

.RECOMMENDED OPERATING CONDITIONS (Ta =0 to +70'C )
Parameter

Symbol

mm

typ

max

UnIt

Vee

45

5.0

5.5

V

IIss

0

0

0

V

Input High (logic 1) Voltage

VIH

2.2

-

6.0

V

Input Low (logic 0) Voltage

V,L

-0.5*'

-

08

V

Supply Voltage

Note) *1 -30V for pulse width:; IOns

• DC AND OPERATING CHARACTERISTICS (Vee = 5V ± 10%, Vss = OV. Ta = 0 to +70°C
Parameter

Symbol

Input Leakage Current

Min.

Typ.'1

Max.

UOlt

IIul

Vee = 5.5V. Von = Vss to Vee

Test ConditIon

-

-

2.0

p.A

2.0

p.A

50'3

90

rnA

Output Low Voltage

VOL

IOL = 8mA

-

Output HIgh Voltage

VOH

IOH = -O.4mA

2.4

Output Leakage Current

IILOI

CS = V IH • V IIO = Vss to Vee

Operatmg Power Supply Current

Icc

CS = V IL • 1110 = OmA. min. cycle

Standby Power Supply Current

ISB

CS = V IH • min. cycle

Standby Power Supply Current (I)

ISBI

CS 2: Vee -0.2V.
OV :S V IN :S 0.2V or Vee - 0.2V :S V IN

15

25

rnA

0.02

2.0

rnA

1'2

50'2

/lA

-

0.4

V

-

V

.. -

Notes) .1 TYPical hmlts are at Vee =S.OV. Ta= +2S"C and specified loadmg
.2 '. hiS characteristics IS guaranteed only for L·verslOn
3 40mA typ for 45ns verSlon

*

.CAPAQTANCE (Ta=2S'C,f=l.OMHz)
Parameter

Symbol

Input Capacitance

C,N

Input/Output CapacItance

Ctlo

Test CondItions

mm

max

Unit

V'N=OV

-

6

pF

Vt/o=OV

-

9

pF

Note ThiS parameter IS sampled and not 100% tested

.AC CHARACTERISTICS (Vcc=5V±10%. Ta=O to +70'C. unless otherwise noted.)
• AC Test Conditions
Input and Output timing reference levels: 1.SV
Input pulse levels: Vss to 3.0V
Output load: See Figure
Input rise and fall times: Sns
Output Load (8)
Output Load (A)

(for

tHZ. tLZ. twz & tOW)

5V

5V

DoUI

Doul

255!l

255Q

5pF"

• Including scope and jig.

•

HITACHI

Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300

81

HM6268 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

eREADCYCLE
HM6268·25

Parameter
Read Cycle TIme

IRc

25

Address Access TIme

IAA

-

Chip Select Access TIme

lACS

Output Hold from Address Change

mH

ChIp SelectIOn to Output in Low Z

fLZ*l

10

ChIp DeselectIOn to Output

•

5

0

/Pu

0

Chip DeselectIOn to Power Down TIme

/PD

Note)

*I

~

--

25

-

blz·'

HIgh Z

35

~

25

ChIp SelectIOn to Power Up Time

10

min

max

mm

10

~

15

0
0

~

25

Unit

max

mm

~

35
35

5

~

-

HM6268·45

HM6268·35

Symbol

~

45

-

ns

-

45

ns

45

ns

5

-

ns

10

-

ns

0

20

ns

0

-

ns

30

ns

~.

~

~

20
~

25

max

-

TransitIOn IS measured ± 200mV from steady state voltage with Load (B)
This parameter IS sampled and not 10046 tested

Timing Waveform of Read Cycle No.1 (1 ),(2)
IRe

Address
I..

10<

Data Valid

Dout

•

Timing Waveform of Read Cycle No. 2(1),(3)

ILl

Dout

High Impedance
/PL'

Vet SUPPlY

-Ie~-----------h------------..
50%

Current

Notes: I. WE is High for Read Cycle.
2. Device is continuously selected, CS = VIL.
3. Address Valid prior to or coincident with CS transition Low.
e WRITE CYCLE
HM6268·25
Parameter

HM6268·35

HM6268·45

Symbol

Unit
mm

max

min

max

mm

max

WrIte Cycle TIme

twc

25

-

35

-

45

-

ns

ChIp SelectIOn to End of Write

it.

20

-

30

-

40

-

ns

Address Valtd to End of Write

tMf

20

ns

~.

30

-

40

-

0

-

0

-

ns

30

--

35

-

ns

0

_.

0

-

ns

20

-

20

_..

ns

Address Setup TIme

lAS

0

--

Write Pulse WIdth

1M'!'

20

----

Write Recovery TIme

IMR

0

-

Data Valid to End of Write

Ivw

12

Data Hold TIme

IvH

0

--

0

--

0

-

ns

Write Enabled 10 Outpul m HIgh Z

twZ*l

0

8

0

10

0

15

ns

Output ActIve from End of WrIte

toft *1

0

--

0

-

0

-

ns

-

Note) lie 1 Transition IS measured ±200mV from steady state voltage with Load (B)
ThiS parameter IS sampled and not 100°'0 tested

•
82

HITACHI

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 8 2 8 8 Series

•

Timing Waveform of Write Cycle No.1 (WE Controlled)

"it ----------_~1.--Addre ..

~~~

1--------"" -------~

.-~~~~~~~

tAil

---..:...--~I_r:_I-----

'"" -----l ,,_____+ ____

Din

*3

Do"!

•

( ( (( ( ( ((

'"Y~

tOil

High Impedance

l ..

~
tUH

Timing Waveform of Write Cycle No.2 (CS Controlled)
'oe
Address

lAw

,.

'I'.

(2)

lew

Don

Dout

High Impedance

(4)

Notes: 1. A write occurs during the overlap of a low CS and a low WE. (twp).
2. tWR is measured from the earlier of CS or Wi> going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs
must not be applied.
4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output
buffers remain in a high impedance state.
S. If CS is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to
the outputs must not be applied to them.
6. Dout is the same phase of write data of this write cycle, if tWR is long enough.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

83

HM6268 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

.LOW Vee DATA RETENTION CHARACTERISTICS (O'C ~ Ta~70'C)
This characteristics guaranteed only for L-version.Parameter

Data Retention Current

VD ,

~;, Vee-O.ZV

IceDIt

v'.;' Vn -O.ZV or
OV:i V,.:iiO.ZV

Chip Deselect to Data Retention Time

tCDIt

Operation Recovery Time

I,

Note<;) *1

,.~-Read

eyrie Time

Test Condlhons

Symbol

Vee for Data Retention

mIn

typ

max

Unit

Z.O

-

-

V

-

30 '2
ZO .J

pA

-

-

ns

0

See retentIOn waveform
t Itt

.1

*2 Vlc -30V
*3 VC l-2 OV

-LOW Vee DATA RETENTION WAVEFORM
DATA RETENTiON MODE

Va - - - - - - -....... 1

.5V---------

___ x,.! _________ _
cs ____...J
ov _____________________________________ - ___ - ---

•
84

HITACHI

Hitachi America, Ltd, • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

ns

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HM6268 Series
SUPPL Y CURRENT VS. AMBIENT
TEMPERATURE

SUPPLY CURRENT VS. SUPPLY
VOLTAGE
1.6

I. 6
TF25'C

Vcc=50V
1.4

1.4

2

~

0

V

./

2

0---

V
.--"

8

- r--- -

8

O.6

O.6

O. 4

5.0

4.75

4.5

o. 4

5.5

5.25

20

80

60

40

Ta

Ambient Temperatare

Supply Voltage Vee (V)

(Oe)

ACCESS TIME VS. LOAD
CAPACITANCE

ACCESS TIME VS. SUPPLY
VOLTAGE
.8

.3
Ta~25'C

1. 2

.6

I~
0

~

j

4

r--

~

O.9

/'

0

•

o.

O. 7

V

.2

r---

./

V

V

./

.8

4.5

4.75

5.0

5.25

O. 6

5.5

200

100

400

300

Load Capacitance CL (pF)

Supply Voltage Vee (V)

SUPPL Y CURRENT VS.
FREQUENCY

ACCESS TIME VS.
AMBIENT TEMPERATURE

T (ns)
I. 3

100

.1

0

33

25

20

Vcc=S.OV

2

11 o.

~

1

°V'"

~

~

~ o. 8

I

V

../

./

V

u o. 7

J

8

20

V

9

~

9

o7 0

./

1.0

40

60

80

O. 6

O. 5

10

•

30

20
Frequency

Ambient Temperature Ta ("C)

f

40

50

(MHz)

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

85

HM6268 Seri.. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INPUT LOW VOLTAGE VS. SUPPLY
VOLTAGE

INPUT HIGH VOLTAGE VS. SUPPLY
VOLTAGE
1.3

1.3

Ta~25'C

To=::.25"C

1.0

1
1

~

0.9

.3

-- --

1

1

~

4.5

4.75

5.0

:!

1.0

Ij

~
0.9

~

5.25

~

0.8

0.7

5.5

4.5

1.6

To = 25·C
Vcc=5V

~

1.4

1.0

J

Ta=25'C
Vcc=5V
1.4

1\

j

\

~

]

5.5

OUTPUT CURRENT VS. OUTPUT
VOLTAGE

1.6

.!

5.25

Supply Voltage Vee (V)

OUTPUT CURRENT VS. OUTPUT
VOLTAGE

I.2

5.0

4.75

Supply Vohage Vee (V)

1e

----- ----

1.1

~

0.8

0.7

1.2

0.8

1

1.

2

~

\

o.6

~

1.0

f

> o.8

\,

!

/

o.6

o.4

.4

0.2

Output Voltage VOH (V)

/

L
V

STANDBY CURRENT VS. AMBIENT
TEMPERATURE

0.6

0.4
Output Voltage

VOl.

(V)

STANDBY CURRENT VS. SUPPLY
VOLTAGE

,

1.4

Vcc=3V

CS~2.8V

1.2

.
.
10-,

j o.8

V
.,,/

V

1 6~

u o.

V
20

1

o.4

40

60

80

/

Ta=25·C

CS= Vcc-O.2V

o. 2

Ambient Temperature Ta ("C)

Supply Voltage Vee (V)

•
86

V

~

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

0.8

HM6267 S e r i e s - - - - - - - 16384-word x 1-bit High Speed CMOS Static RAM
•
•
•

•
•
•

FEATURES
High Speed: Fast Access Time 35/45/55ns (max.)
Low Power Standby and Low Power Operation
Standby: 0.1 mW (typ.)/5/..1W (typ.) (L·version),
Operation: 200mW (typ.)
Single 5V Supply and High Density 20 Pin Package
Completely Static Memory ...... No Clock or Timing Strobe
Required
Equal Access and Cycle Time
Directly TTL Compatible: All Input and Output
Capability of Battery Back Up Operation (L·version)

•

ORDERING INFORMATION

•
•

Type No.

Access Time

HM6267P·35
HM6267P45
HM6267p·55

35ns
45ns
55ns

HM6267LP-35
HM6267LP45
HM6267LP-55

35ns
45ns
55ns

•

(DP-20N)

• PIN ARRANGEMENT

Package

300 mil 20 pin
Plactic DIP

BLOCK DIAGRAM

'"

- - Vee

\,

"
"

- - v"
Kow

Mt'II'I

..

I) j'

,,!'i

,0

I"

o

..!o

III

IICI

o\mblf'nl TemJ)t'ralurt' Tn

SUPPLY CURRENT VS. FREQUENCY

ACCESS TIME VS. LOAD CAPACITANCE

,

I

r.

0

1

q

'1111

?

-

I--- l...---

0

(t)

IlK)

./

X

~

/"

,

10

\0

V

./

V

0"

X

r,

200

HlO

i

400

300

10

INPUT LOW VOLTAGE VS. SUPPLY VOLTAGE

2\

!f1

Frequenc\

f (MH,l

INPUT HIGH VOLTAGE VS. SUPPLY VOLTAGE
3

3

Ta=2S"C

Ta=2S"C
2

2

--

I

f

0

I---I - -

09

0

~

45

I---

8

475

50

52,

II 7
45

55

475

50

525

5.5

Supply VolI~ Vee (VI

Supply VohaR! Vee (V)

•
92

~

9

8

o7

--

.1

1---

:>

j

V

HITACHI

Hitachi America, ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 8 2 8 7 Series

OUTPUT CURRENT VS. OUTPUT VOLTAGE

OUTPUT CURRENT VS. OUTPUT VOLTAGE

6

6

Ta=25t'

1\

4

1
1

I.

1.0

j

1

0

4

\
\
\
\

2

3
J

Vcc=W

8

6

~

12

~

I0

1

V

R

/

6

\

4

/

10

/

r.=m;
Vcc=5V

1/

4

06

0.1

02

Output Vnka,ae

OUIPUI VnltaA'l! VIM (V)

STANDBY CURRENT VS.
AMBIENT TEMPERATURE

I

VIIL

STANDBY CURRENT VS. SUPPLY VOLTAGE

.

"

~rr=3V

CS=2RV

12

.
!
i

/
./

10-<

V

~

OK

!

06

j

/
,
\0"0

0'

20

40

OR

(V)

60

110

,./'

/

V

/

V

7

7

/

Ta==2S"C
Cs=Vcr-02V

2
Suppl'4 VnltaRe \cc (V)

Amblei'll Temperature To (t \

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

93

HM6264A Series--------Maintenance Only
8192-word x 8-bit High Speed CMOS Static RAM
• FEATURES
• low Power Standby

•
•
•
•
•
•
•

HA6264AP Series

Standby:
O.lmW (typ.)
10~W (typ.) l-/ll-version
Operating: 15mW/MHz (typ.)
l00ns/120ns/150ns (max.)

low Power Operation
Fast access Time
Single +5V Supply
Completely Static Memory ..... No clock or Timing Strobe Required
_Equal Access and Cycle Time
Common Data Input and Output, Three State Output
Directly TTL Compatible: All Input and Output
Capability of Battery Back Up Operation (l-/ll-version)

(DP-28)
HM6264ASP Series

• ORDERING INFORMATION
Type No.

Access Time

HM6264AP-I0
HM6264AP-12
HM6264AP-15

lOOns
120ns
150ns

HM6264ALP-I0
HM6264ALP-12
HM6264ALP-15

lOOns
120ns
150ns

HM6264ALP-IOL
HM6264ALP-12L
HM6264ALP-15L

lOOns
120ns
150ns

HM6264ASP·1O
HM6264ASP-12
HM6264ASP·15

lOOns
120ns
150ns

HM6264ALSP·1O
HM6264ALSP-12
HM6264ALSP-15

lOOns
120ns
150ns

HM6264ALSP-10L
HM6264ALSP-12L
HM6264ALSP-15 L

lOOns
120ns
150ns

HM6264AFP-10
HM6264AFP-12
HM6264AFP-15

lOOns
120ns
150ns

HM6 264ALFP-l 0
HM6264ALFP-12
HM6264ALFP-15

lOOns
120ns
150ns

HM6264ALFP-10L
HM6264ALFP-12L
HM6264ALFP-15L

lOOns
120ns
150ns

Package

600 mil 28 pin
Plastic DIP
(DP-28N)
HM6264AFP Series

300 mil 28 pin
Plastic DIP
(FP-28D/DA)

• PIN ARRANGEMENT

28 pin
Plastic SOP
(Note)

Note) T is added to the end of the type no. for a SOP of 3.00 mm (max.)
thickness.

(Top V,ew)

•
94

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 6 4 A Series

• BLOCK DIAGRAM

~:'
A.
A,

<>----t=i:a:==r-,

,,,
"

--oVn

Row
Dttodu

A,

--0

Memorv Matrix
25b x 256

Vs!.

A,

~~----L-----_r------~

(iE

0-------------'

• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Terminal Voltage 1
VT
Power Dissipation
PT
Operating Temperature
Topr
Storage Temperature
TBt,
Storage Temperature (Under 8~ TbiOB
Notes) * 1. With respect to Vss.
*2. -3.0V for pulse width ~ SOns

Rating
-0.5*2 to +7.0

Unit

1.0

W
·C
·C
·C

o to +70
-55 to+12S
-10 to +85

V

• TRUTH TABLE
WE

cs. CS.

OF;

X

H

X

X

X

X

X

H
H
L
L

L
L
L
L

L
H
H
H
H

H
L
H
L

Mode
Not Selected
(Power Down)
Output Disabled
Read
Write

110 Pin
High Z

Vee Current

High Z
High Z
Dout
Din
Din

ISB/SBI
ICC
ICC
ICC
ICC

Note

ISB/SBI

Read Cycle
Write Cycle (I)
Write Cycle (2)

X: H or L

• RECOMMENDED DC OPERATING CONDITIONS (To = 0 III +700q
Ilem
Supply V"1t.I~C
Input

Vn1ta~c

Symb.. l

min

Iyp

max

Vee

s.n

5.5

V/H

4.5
0
2.2

VII.

-0.3*1

VSS

0
..

n
6.0
0.8

Unit
V
V
V
V

Note) *1. -3.0V for pulse width ~ SOns

~HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, GA 94005-1819 • (415) 589-8300

95

HM6264A S e r i e s - - - - - - - - - - - - - - - - - - - - - - · - - - - - - - - - - -

•

DC AND OPERATING CHARACTERISTICS (Vcc
Item

Symbol

= 5V ± 10%, Vss =OV, Ta = 0 to

Test Condition

min

+70°C)
typ*1 max

Unit

ilL/I

Vin=VSSto VCC

-

-

2

p.A

Output Leakage Current

11£0 1

CSI= VIH or CS2=VIL orOE= VIHor WE= V/L.
VI/O=VSSto Vee

-

-

2

p.A

Operating Power Supply Current

ICCDC

CSl=VIL. CS2=V/H. h/o=OmA

-

7

-

30
30

-

Input Leakage Current

Min. cycle, duty=100%, CSI=VIL, CS2=V/H
h/O=OmA
Cycle time - Ip.s, duty - 100%,11/0 = OmA,
CSI ~ 0.2V, CS2 ~ VCC -0.2V
V/H ~ VCC -O.2V, VIL ~ 0.2V

ICCl
Average Operating Current

ICC2

CSI =VIH or CS2=VIL

ISB
Standby Power Supply Current

CSI~VCC-0.2V, CS2~VCc-0.2Vor
OV ~ OS2 ~ 0.2V, OV ~ Vln

ISBI*2

Output Voltage

VOL

IOL=2.lmA

VOH

IOH=-1.0mA

IS

rnA

45*'
55*-

rnA

3

5

rnA

-

I

3

rnA

-

0.02

2

rnA

-

2*' 100*'

-

2.4

50*'

-

0.4

V

-

V

Notes) *1. Typical limits are at VCC=S.OV, Ta=2S oC and specified loading.
*2. VIL min=-O.3V
*3. This characteristics is guaranteed only for L-version.
*4. This characteristics is guaranteed only for LL-version.
*5. For 120ns/1S0ns version.
*6. For lOOns version.

• CAPACITANCE

U = IMHz, To = 25°0

Item
Input Capacllancc
Input/Output Capacitance
Note) This parameter

IS

Symbol Test ('"ndlllOn
Vm = OV
On

Cuo

Vuo

=

OV

typ

max

-

5

-

7

Unll
pF
pF

sampled and not 100% tested.

• AC CHARACTERISTICS (Vee

= 5V±100/0. Ta

=

0 to +70°C)

• AC TEST CONDITIONS
Input Pulse Levels: O.SV 12.4V
Input R.se and Fall Time IOns
Input Tim ing Reference Level: 1.5V
Output Timing Reference Level: O.SV 12.0V
Output Timing Reference Level: HM6264A-l0 1.5V
HM6264A-12/15 0.SV/2.0V
Output Load: lTTL Gate and CL (100pF) (including scope and jig)

.HITACHI
96

p.A

2*4

Hitachi America. Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 6 4 A Series
•

READ CYCLE

HM6264A-10
HM6264A-12
HM6264A-15
Unit
min
max
min
max
min
max
Read Cycle Time
100
120
150
ns
tRC
Address Access Time
100
120
150
ns
tAA
100
120
150
I
CS1
ns
tC01
Chip Selection to Output
100
120
CS2
ns
150
tC02
Output Enable to Output Valid
50
60
ns
70
tOE
10
10
15
ns
CS1
Chip Selection to
tLZ1
Output in Low Z
10
10
15
ns
CS2
tLZ2
Output Enable to Output in Low Z
5
5
5
ns
tOLZ
35
0
0
40
0
50
ns
I csr
Chip Deselection to
tHZ1
Output in High Z
0
35
40
0
0
50
ns
CS2
tHZ2
Output Disable to Output in High Z
40
0
35
0
0
50
ns
tOHZ
Output Hold from Address Change
10
10
10
ns
tOH
..
Notes) 1. tHZ and tOHZ are defined as the time at whIch the outputs achIeve the open CIrcUIt condItIon and are not referred
to output voltage levels.
2. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from
d device to device .
Item

Symbol

I

I
I

I

• READ CYCLE
~-------------------tRC-----------------~

~-------tAA------~

CS1

"\\:\\~~~~\\\\~~-------tCOl-----_!
t-------tLZl------i

Dout------------____________________________

~

~--------tC02'---_+--~

Data Valid
Note) 1. WE is high for Read Cycle

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

97

HM6264A Series-------------------------------•

WRITE CYCLE

Item

Symbol

Write Cycle Time
Chip Selection to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Enable to Output in High Z
Output Active from End of Write

twe
tew
tAS
tAW
twp
tWR
tWHZ
tDW
tDH
tOHZ
tow

HM6264A-10
min
max
100
80
0
80
60
0
0
35
40
0
0
35
5
-

HM6264A-12
min
max
120
85
0
85
70
0
0
40
40
0
0
40
5
-

HM6264A-15
min
max
150
100
0
100
90
0
0
50
50
0
0
50
5
-

• WRITE CYCLE 111 IOE clockl

~------twc------~

CS2

Dout--~~-+~~~~~~~~~~~----~~tD-W--~----tD-H------------Din--------------------------------~

.

~----------~~~

•
98

HITACHI

Hitachi America, ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 6 4 A Series

(OE

• WRITE CYCLE (2)

Low F,x)

twe

/
\.

Address

"

\.

tAW

CSt

\ \\ ,\ \~

tWR [4J

tew [2J

I II /111 ILL

V

[6J
tew [2J

~/I

CS2

II 'III/V

~

,\\\ ,\\\~ill

twp [IJ
tAS [3J

-=x\ \'
I

tOH

J
[5J

tWHZ

tow
[7J

Dout

\

\

\ \

///i////~jjj/i/

[8J

~

\

tDW

tDH

1'-.1 .i":.f..j.
[9J

Din

<1D~

\ \ \ _\\.lSl"-..
'/\LY

NOTES: I) A write occurs during the overlap of a low CSI, a high CS2 and a low WE. A wnte begms at the latest transItion among CSi going low, CS2 going high and WE going low. A write ends at the earliest transition among
CS1 going high, CS2 going low and WE going high, IWp is measured from the beginning of write to the end
of write.
2) lew is measured from the later of CSI going low or CS2 going high to the end of write.
3) I AS is measured from the address valid to the begmning of write.
4) IWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle.
5) During this period, I/O pins are in the output state, therefore the input signals of opposite phase to the outputs
must not be applied.
6) If CS1 goes low simultaneously with WE going low or after WE going low, the outputs remain in high impedance state.
7) Dout is the same phase of the latest wntten data in this write cycle.
8) Dout is the read data of next address.
9) If CSI is low and CS2 IS high during this period, I/O pins are in the output state Therefore, the input signals
of opposite phase to the outputs must not be applied to them.

~HITACHI
Hitachi America, Ltd • Hitachi Plaza' 2000 Sierra Point Pkwy' Brisbane, CA 94005-1819 • (415) 589-8300

99

HM6264A S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

•

LOW Vee DATA RETENTION CHARACTERISTICS (Ta
This characteristics is guaranteed only for L/LL-version.
Symbol

Item

=0 to +70°C)

Test Condition

Vee for Data Retention

VDR

CSlP<'Udt'f

~4

NC

Mt'mnr\

v••

\rrav

(Top View)

1!M i{n",
ji2l .. lum" ..

I;

...

I

01

Pin Description

~~r:fr-r--l:=rL-~::~;;--1==~~
Culumll I 0

...

Pin Name

Function

AO-A13

Address
Input/Output
Chip Select

1/01-1/04
I

o~

CS
WE

"lt11113--L--J

Vee
VSS

•

Write Enable
Power Supply
Ground

HITACHI

Hitachi America, ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

103

HM6288Serie.----------------------------------

.ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Rating

Volt_gf' on Any Pin Relative to Vss

Vr

-O.S"to +7.0

V

Power DIssipation

Pr

1.0

W

Operating Temperature

T.,.

Storage Temperature
Temperature under Bias
~ote

*1

o to

Unit

+70

·C

T~I.

-55to+125

·C

T....

-10 to +85

·C

Vr mm = -2 OV for pulse wldth;;;;;lOns

.TRUTH TABLE
CS

WE

Mode

Vee Current

I/O Pin

H

X

Standby

ISB,IsB'

H'ghZ

L

H

Read

Icc

Dout

Read'Cycie I, 2

L

L

Write

Icc

Din

Write Cycle I, 2

Ref. Cycle
-

.RECOMMENDED DC OPERATING CONDITIONS (Ta=O to +70'C)
Symbol

mm

typ

max

Unit

Vee

4.5

5.0

5.5

V

Vss

0

0

0

V

Input High (logic 1) Voltage

VIH

2.2

-

6.0

V

Input Low (logic 0) Voltage

V/L

-0.5"

-

0.8

V

Parameter
Supply Voltage

Note. *1.

VEL

mm = -2 OV for pulse width;::;';; IOns

.DCANDOPERATINGCHARACTERISTICS (Ta=Oto +70'C, Vcc=5V±lO%, VSS=OV)
Symbol

max

Umt

IILII

Vee=MAX. V/N=Vss to Vee

-

-

20

p.A

Output Leakage Current

IILO I

CS=VIH,VUO= Vss to Vee

-

2.0

p.A

Operating Power Supply Current

Icc

CS= V/L, Iuo=OmA, min. cycle

-

60

120

rnA

CS= VIH, min. cycle

-

15

30

rnA

/581*2

CS ~ Vee - 0.2V

-

0.02

2.0

rnA

1581*3

OV;;;; V/N;;;;0.2V or Vee-0.2V;;;; VrN

-

0.02

0.1

rnA

0.4

V

Parameter

Standby Vee Current

ISH

Standby Vee Current 1

Test Condition

min

Input Leakage Current

typ"

Output Low Voltage

VOL

IOL=8mA

-

-

Output High Voltage

VOH

IOH=-4.0mA

2.4

-

-

V

Test Conditions

min

max

Unit

v..=OV

-

6

pF

VI/O=OV

-

8

pF

Notes.

* 1. TYPical hmlts are at
* 2. P version
* 3. LP version

Vee - S.OV, Ta - + 25 C and specified loadmg

.CAPACITANCE ( Ta=25"C, f
Parameter
Input Capacitance
Input/Output Capacitance

= l.OMHz)
Symbol

G••
Grlo

Note: This parameter IS sampled and not 100% tested

•
104

HITACHI

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 8 Series
.AC CHARACTERISTICS

•

AC Test Conditions
Input pulse levels: OV to 3.0V
Input rise and fall times: 5ns

Input and Output timing reference levels: 1.5V
Output load: See Figure
5V

5V

Dout

Dout

255Q

255Q

30pF'
Output Load (A)

Output Load (8)
(for 1HZ. ILZ. IWZ & tOW)

*Includlng scope & Jig.

•

READ CYCLE
Parameter

Symbol

Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Selection to Output in Low Z
Chip Deselection to Output in High Z
Chip Selection to Power Up Time
Chip Seselection to Power Down Time
*

-~---~

tRC

..

tAA
tACS
tOH
ILZ*
1HZ *
IpU
IpD

HM6288-25
min
max
25
25
25
3
5
12
0
0
25

HM6288-35
max
min
35
35
35
5
5
0
20
0
30
-

Unit
ns
ns
ns
ns
ns
ns
ns
ns

Transition IS measured ± 200m V from steady state voltage with Load (8)
This parameter IS sampled and not 100(./0 tested

eTiming Waveform of Read Cycle No.1 [1] [2]
I"

\/
\.

\

Address

1\
I"

10H

10H

Dout

~XXX)K

ProvlOus

Data Valid

\(M

Data Valid

eTiming Waveform of Read Cycle No.2 [1] [3]

cs

\

/

I,,,
Dout

--------~--H-,.-h-lm-~-d.-n'-.----{~)()K~------D.-~-V-.h-d4_------~)~
Impedance

Ipu

Vee supply

50% \

\.

("urrent

[,.
N()t~

I WE

IS

2 Device

Ihgh for Read Cycle
IS

contmuously self"Cted,

CS= VIL

3 Addres.<; Vahd prtor to or cOlOcldent with CS tranSitIOn Low

•

HITACHI

Hitachi America, Ltd • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-t819 • (4t5) 589-8300

105

HM8288&wiH-------------------------------------------------------------•

WRITE CYCLE

Parameter

Symbol

Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Date Valid to End of Write
Data Hold Time
Write Enabled to Output In High Z
Output Active from End of Write

twe
tew
tAW
tAS
twp
tWR
tDW
tDH
tWZ*
tOW*

HM6288-25
min
max
25
20
20
0
20
0
12
0
0
8
5
-

HM6288-35
min
max
35
30
30
0
30
0
20
0
0
10
5
-

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

• TraRS1tJon IS measured ±200mV from stead)' state voltage With Load (81

ThiS parameter IS sampled and not 100°& tested

• Timing Waveform of Write Cycle No.1 (WE Controlled)
/we

Address

'ew

'AW

'D.
Don

nata

DI

Vahd

DOllt

.HITACHI
106

Hijachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 8 Series
eTiming Waveform of Write Cycle No.2 (CS Controlled)

I.,
Address

I,.
lew

1.,,..1

I.w

Don

Data

High Impedance

Dout

In

Valid

*4

Notes) 1 A write occursdunng the overlap of a low CS and a low WE (IMP)
2 t~ R IS measured from the earher of CS or WE gOing high to the end of wnte cycle
3 DUring this penod, liD pms are In the output state so that the mput signals of oPPOsite phase to the
outputs must not be apphed
4 If the CS low transition occurs simultaneously with the WE low transItion or after the WE
transition. the output buffers remam In a high Impedance state
5 If CS IS low dUring this penod, 110 PinS are In the output state after tow Then the data mput signals
of opposite phase to the outputs must not be apphed to them
6. Dout IS the same phase of write data of this write cycle, If tWR IS long enough

e Low Vee Data Retention Characteristics ( Ta = 0 to

+ 70'C)

(This Characteristics is guaranteed only for L-version.l
Symbol

Parameter

Mm

Typ

Max

UOIt

Vee for data retention

VVR

Z.O

-

-

Data retentIon current

/CCDR

-

-

50"
35"

I1A

tCDR

0

-

-

ns

tR

tRc ll

-

-

ns

V

Test Conditions
CS;;;: Vee-O.ZV
\1,,;;;: Vee - O.ZV or

Chip deselect to data
retention time

OV~

\1"

~O.ZV

See retention waveform

OperatIOn recovery time
NOTE

1 IRe = Read cycle time
2 Vcc=3.0V
3 Va=20V

Low Vcc Data Retention Waveform
v~

________________

Data Retention Mode
~

4.5V--------

-------------------------

---------

cs _____

--J

w- ___________________________________________ _

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

107

HM6288 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SUPPLY CURRENT VS. SUPPLY VOLTAGE

SUPPLY CURRENT VS. AMBIENT TEMPERATURE

1. 6

1.6

Vcc=5 OV

Ta=25'C
14

]

1

]

1.2

~

----

.;:

~

1.0

c.
"

08

"

1. 4

---

u

~

on

0.6

0.4 4.5

V-

1

V--

2

~

""

J

1a

'"' 08

--

j

on

0.6

4.75

50

20

5.5

5.25

1.3

~

§

1.8

1.2

]

1.6

1.1

1

14

1.0

r---

b

j

80

Ta=25'C

~

i

60

ACCESS TIME VS. LOAD CAPACITANCE

ACCESS TIME VS. SUPPLY VOLTAGE

~c

40

AmbIent Temperature Ta (OC)

Supply Voltap;e Vee (V)

]

t--- r--

0.9

--

--

~

~

~

t---

3

1.2

~

1.0

!
~

«

.-- ~

-----

V

0.8

08

475

5.0

5.25

50

5.5

100

150

200

Lo.ad Capacitance CdpF)

Supply Voltage Vee (V)

SUPPLY CURRENT VS. FREQUENCY

ACCESS TIME VS. AMBIENT TEMPERATURE
1.3

100

1. 1

50

33

25

20 T (ns)

Vcc=5.0V
1. 2

1

;;
j"

~

~

1.0

~

l.---

........

-

./

1.a

O. 9

./

O. 8

~

O. 9

O. 7

0.8

0.6

/

V

V

V

~

o. 7 a

20

40

60

10

80

20

30

40

Frequency f (MHz)

Ambient Temperature Ta (OC)

~HITACHI
108

Hitachi Amenca, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

50

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 8 Series
HIGH LEVEL INPUT VOLTAGE VS.
SUPPLY VOLTAGE

LOW LEVEL INPUT VOLTAGE VS.
SUPPLY VOLTAGE
3

1.3

To=25'C

To=25'C
1. 2

12

--

1
1. 0

~

!--

o. 9

1. 1

~

1. 0

o. S
O. 7

4.5

i

0.9

~

0.8

"
5.0

475

525

0.7

5.5

V-

4.5

-- --

OUTPUT CURRENT VS. OUTPUT VOLTAGE(1)

1. 6

To=25'C
Vee =5V

i

To=25'C
Vec=5V

1.4

1. 4

1.2

1. 2

/
V

z

!

u

\

1.0

].
\j

0

~

O.S

3

-So

::i:

0.6

\

1. 0
O.S

\

0.6

1\

V

/

0.2
High Level Output Voltage

~
~

~

1. 0

o. 5~

V

/
/'

]

..~

V

.

II

1.0

~

c
1:

8
]"

O.S
0.6
0.4
0.2

20

40

60

so

O.S

(V)

1

1.2

~

o. 1

0.6
VOL

1.4
Vee=3V
CS=2.SV

]

!
j

0.4

STANDBY CURRENT VS. SUPPLY VOLTAGE

10

u

L

Low Level Output Voltage

(V)

VOH

STANDBY CURRENT VS. AMBIENT TEMPERATURE

~

5.5

OUTPUT CURRENT VS. OUTPUT VOLTAGE(2)

16

]
0

5.25

Supply Voltage Vee (V)

Supply Voltage Vee (V)

1

5.0

4.75

~

o

2

Ambient Temperature Ta (4C)

--

/V
V

/

/

To=25"C
CS=Vee-O.2V

Supply Voltage Vee (V)

.HITACHI
Hitachi America, Lid .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

109

HM6288 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - STANDBY CURRENT VS.INPUT VOLTAGE

10

Ta=25'C
Vcc=5.0V
CS=4.8V

~

1
0

~

6

~
~

4

u

"

.0

~

2

1'\
1\

J

2

~

3

Input Vo1tage

4

Vln

(V)

•
110

HITACHI

Hitachi America, ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

HM6788 Series---- Maintenance Only
16384-word' x 4-bit High Speed Hi-BiCMOS Static RAM
.FEATURES
• Super Fast Access Time: 25/30n5 (max.)
• Low power Operation
Operating: 230mW (typ). Standby: 10mW (typ)
• +5V Single Supply
• Co';'pletely Static Memory No Clock or Timing Strobe required
• Balanced Read and Write Cycle Time
• Fully TTL compatible Input and Output

(Dp·22NBl

• ORDERING INFORMATION
Type No.

Access Time

HM6788p·25

25ns

HM6788P-30

30ns

Package

.PIN ARRANGEMENT

300 mil 22 pin
Plastic DIP

.BLOCK DIAGRAM
A'V--'A<--...J

--OVer

A,'"'--..J~--'

A.........-..J~--...,
A.........

_..J~

--oVss

Memory Matrix
128X512

Row

Asv--, A<--...J Decoder

__...,

A7o---C~::::J
A."--..J~--""

1/01n--,;v=-=·-=~'::-=-=-=-=~-~==::::;co:lo:m:";l!O===::I~--,

.ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Rating

Umt

Terminal Voltage to Vss pin

VT

-0 5to +7.0

V

Power Dissipation

PT

l.0

W

Operating Temperature

Topr

Storage Temperature (with bias)
Storage Temperature

oto +70

·C

T.. ,(bias)

-10to+85

·C

T~t(J

-55to +125

·C

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300

111

HM6788 Seri.. - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
.TRUTH TABLE
CS

WE

Vee Current

Output Pin

H

x

Not selected

IS8.Is8'

HighZ

L

H

Read

Icc. IcC!

Dout

Read Cycle (1) (2)

L

L

Write

Icc. IcC!

Din

Write Cycle (1) (2)

Mode

Ref. Cycle
-

x: H orL

.RECOMMENDED DC OPERATING CONDITIONS (O'C ~ Ta ~ 70'C)
min

typ

max

Vee

4.5

5.0

5.5

V

Vss

0

0

0

V

6.0

V

o.s

V

Symbol

Item
Supply Voltage
Input High Voltage

V,H

2.2

Input Low Voltage

VII.

-0.5*'

-

Unit

Note) *1 -30V with 20ns pulse Width

.DC AND OPERATING CHARACTERISTICS (Vcc=5V± 10%. Ta=O'Cto +70'C)
Symbol

Test Conditions

min

typ

Input Leakage Current

I ILl I

Vee=5.5V. VIN= Vss to Vee

-

-

2

Output Leakage Current

Ihol

CS= VIH. VI/O= Vss to Vee

-

-

2

,..A

Opearating Power Supply Current

Icc

CS= VIL. Ii /0 = OmA

-

SO

rnA

Average Operating Current

Icc,

Min. Cycle. Duty: 100%

rnA

CS= V,H

30

rnA

/S81

CS;;: Vee-O.2V. VI.,:;;O.2Vor V,,<: Vee-O.2V

-

10

rnA

Output Low Voltage

VOL

10/. = SmA

-

120

IS8

-

0.5

V

Output High Voltage

VOH

IOH=-4mA

2.4

-

-

V

Item

Standby Power Supply Current

max

-AC CHARACTERISTICS (Vee = 5V ±10%, Ta = 0 to +70°C, unless otherwise noted)
•

AC Test Conditions
Input pulse levels: Vss to 3.0V
Input rise and fall time: 4ns

Input and Output reference levels: 1.5V
Output Load: See Figure

+5V

255Q

.lncIudi", scope and ii..

Output Load B

(tCHZ. tWHZ. tCLZ. tOW)

Output Load A

eHITACHI
112

Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

Unit
,..A

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 8 8 Series

.READ CYCLE
HM6788·25
Item

HM6788·30

Symbol

Umt
mIn

max

mm

max

Read Cycle Time

IRe

25

-

30

-

ns

Address Access Time

IAA

-

25

-

30

ns

Chip Select Access Time

tACS

-

25

-

30

ns

Chip SelectIOn to Output In Low Z

teLL

2

0

.

0

Chip Deselectlon to Output In High Z

tCHZ* 2

0

10

0

12

ns

5

-

ns

0

-

ns

*

.

ns

Output Hold from Address Change

IOH

5

.-

Chip Selection to Power Up Tlme'l

tPF

0

-

ChIp Deselection to Power Down Tlme'l

IPD

-

20

-

30

ns

tr

-

150

-

150

ns

Input Voltage Rise/Fall Time'3
Notes)

*1

This parameter IS sampled and not 1oo o/Q tested
*2 TranSitIOn IS measured ±200mV form steady .,tate voltage with Load (8) This parameter 1", sampled and not IOGo(, tested
*3 If tl becomes more than 150m" there IS POSSibility of functIOn fall
plcu\c LonWel your

•

nc.tn.~ . . t

Hlt:llhl Sale . . Dept regardmg "'pcclticdtlOn

·1 *2

Timing waveform of Read Cycle No.1'

I"

'""

loU

DuIU

•

Data ValId

PrevIOus data Valid

Timing waveform of Read Cycle No. 2. 1 ,.3

"u

~-------=-------~

Ilu

Data ValId

BULII

High Impedance

Note) *1. WE = V/H
*2. CS= VIL
*3. Address valid prior to or coincident with CS transition Low.

• WRITE CYCLE
HM6788·25
Item

HM6788·30

Symbol

min

max

mIn

max

Umt

Write Cycle Time

Iwe

25

-

30

-

ns

Chip Selection to End of Write

tew

20

-

25

-

ns

Address Setup Time

lAS

0

0

-

ns

Address Valid to End of Wnte

lAW

20

-

25

-

ns

Write Pulse Width

Iwp

20

-

25

-

ns

Write Recovery Time

IWR

0

-

0

-

ns

Write to Output In High Z

tWHZ· 1

0

10

0

12

ns

Data Valid to End of Write

low

15

-

ns

Data Hold Time

IDH

Output Active from End of Wnte

tow

*1

15

*1

-

-

5

-

5

-

n.

0

.-

0

-

ns

TranSitIOn IS measured ±200mV from steady state voltage With Load(B)
This parameter IS sampled and not lOO?o tested

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

113

HM6788 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

•

Timing waveform of Write Cycle No.1 (WE Controlled)

,,,

.1.ddrrss

,,,
tAli'
/lIP *1

'OH

Dout

tDW

IIlgh Impedance

•

IDN

"

Data Vahd

HIgh Impedance

Timing waveform of Write Cycle No.2 (CS Controlled)
'we

Address

,,,

lAw

"P

I llgh 1m ped.nce

Il1gh Impedance

Dout

IDW

Om

IDN

Data V.hd

Notes) * 1. A write occurs during the overlap (tWP) of a low CS and a low WE.
*2. During this period, I/O pins are in the output state so that the input signals of
opposite phase to the outputs must not be applied.
*3. Dout is the same phase of write data of this write cycle.
*4. If the CS low transition occurs after the WE low transition, output remain in a
high impedance state.
*5. If CS is low during this period, I/O pins are in the output state. Then, the data
Input signals of oppoSIte phase to the outputs must not be applied to them.
*6. tWR is measured from the earlier of CS or WE going high to the end of write cycle .
• CAPACITANCE (Ta=2S·C./= I.OMHz)
Item

____________

Input CapaCItance

Input/Output CapaCltance

-------------Note) This parameter

114

IS

sampled and not WOO() tested

+_S_~_:_:_O_I4_----m;"- ~C,lo

_.

--

-;"
-

~ ~_;____~-----~-~n-,d-~-~-~n-s------

-----

8.0
---_.-

VOI"T=OV

~HITACHI

Hitachi America, Ltd • Hitachi Plaza· 2000 Sierra POint Pkwy. Brisbane, CA 94005-1819 • (415) 589-8300

HM6788H S e r i e s - - - - - - 16384-word x 4-bit High Speed Hi-BiCMOS Static RAM
Features
• Super Fast Access Time: 15/20ns (max.)
• Low power Operation
Operating: 280mW (typ)
• +5V Single Supply
• Completely Static Memory No Clock or Timing Strobe required
• Equal Access and Cycle Times
• Fully TTL compatible Input and Output

(DP·22NB)

Ordering Information
Type No.

Pin Arrangement
Package

Access Time

HM6788HP·15

15ns

HM6788Hp·20

20ns

300 mil 22 pin
Plastic DIP

Block Diagram
A.~--~~--~ r-------------~

A,
A.~_J"o<...,

Memory Matrix

A,~_J"o<...,

Vee
--<>
--<>
VSS

128X512

A4~-~:::J
A.~-~:::J

A.

O-:~5==~_r=~~;;:;==~:::;_,
Column 1/0

1101 c>1102 ~.ff.IH)~

1103 <>-1r+HH)~
110. '"'--"'LLULI"-_

(Top View)

WE~==~~4=========~

__

Absolute Maximum Ratings
Item

Symbol

Rating

Unit

Terminal Voltage to Vss pin

VT

-0.5to +7.0

Power Dissipation

Pr

1.0

V
'W

Operating Temperature

Top,

oto +70

·C

Storage Temperature (with bias)

T.,,(bias)

-IOto +85

·C

Storage Temperature

T,t,

-55to +125

'C

Note)

The specitications of this device are subject to change without notice.
Please contact Hitachi's Sales Dept. regarding specifications .

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005· 1819 • (415) 589·8300

115

HM6788H S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Truth Table

CS

Mode

Vee Current

I/O Pin

Not selected

IS8.ls81

HighZ

H

Read

lee.leel

Data Out

Read Cycle (1). (2)

L

Write

Icc. Icc I

Data In

Write Cycle (1). (2)

H

x

L
L

Ref. Cycle

x: H or L

Recommended DC Operating Conditions (O'C;:;; Ta;:;; 70'C)
min

typ

max

Unit

Vee

4.5

5.0

5.5

V

Vss

0

0

0

V

Input HIgh Voltage

V,H

2.2

6.0

V

Input Low Voltage

VII.

-0.5*'

0.8

V

Symbol

Item
Supply Voltage

Note) *1. -3.0V with IOns pulse width.

DC and Operating Characteristics (Vcc=5V ± 10%. Ta=O'C to +70'C)
Symbol

Test Conditions

Input Leakage Current

Item

I ILl I

Vee=5.5V. VIN= Vss to Vee

2

pA

Output Leakage Current

Ihol

CS= V,H. Vdo= Vss to Vee

10

pA

Opearating Power Supply Current

Icc

CS= VII.. [, /o=OmA

100

mA

Average Operating Current

leCl

Min. Cycle. Duty: 100% 11/0 =OmA

120

mA

ISB

CS= V,H

30

mA

IS81

CSo= Vce-O.2V. V, .• :;;O.2V or V"o= Vce-O.2V

10

mA

Output Low Voltage

VOL

Im.=8mA

0.4

V

Output High Voltage

VaH

laH=-4mA

Standby Power Supply Current

AC Characteristics (Vee

typ

min

max

V

2.4

=5V ±10%, T, =0 to +70°C, unless otherwise noted)

• AC Te.t Condition.
Input pulse levels: Vss to 3.0V
Input rise and fall time~ 4ns

Input and Output reference levels: 1.5V
Output Load: See Figure
+5V

+IV

Output
Output

..;= 3OoY'
7
.lncIudI....... Mdil~

Output Load B

(tHZ. tLZ. tWZ. tOW)

Output Load A

•
116

Unit

HITACHI

Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 8 8 H Series
Read Cycle
Item

HM6788H-15

Symbol

min

HM6788H-20

max

min

Unit

Note

max

Read Cycle Time

tRC

Address Access Time

tAA

15

20

ns

Chip Select Access Time

tACS

15

20

ns
ns

1,2

8

ns

1,2

15

Chip Selection to Output in Low Z

tLZ

3

Chip Deselection to Output in High Z

tHZ

0

Output Hold from Address Change

tOH

20

ns

3
6

0

ns

3

Note) *1. This parameter is sampled and not 100% tested.
*2. Transition is measured ±200mV from steady state voltage with specified loading in Load B .

•

Timing waveform of Read Cycle No. 1*1,*2

Address

Data Out

•

Data Valid

Previous Data Valid

Timing waveform of Read Cycle No. 2*1,*3

Data Out

Data Valid

High Impedance

Note) *1. WE = VIB
*2. CS= V/L
*3. Address valid prior to or coincident with CS transition Low.

Write Cycle
Item

Symbol

HM6788H-15
min

max

HM6788H-20
min

Unit

Note
2

max

Write Cycle Time

twc

15

20

ns

Chip Selection to End of Write

tcw

10

15

ns

o

o

Address Setup Time

tAS

Address Valid to End of Write

tAW

10

15

ns

Write Pulse Width

twp

10

15

ns

Write Recovery Time

tWR

ns

ns

o

twz

o

Data Valid to End of Write

tDW

9

10

ns

Data Hold Time

tDH
tow

o
o

ns

Output Active from End of Write

o
o

Write Enable to OU.tput in High Z

6

8

ns

ns

3,4

3,4

Note) 1. IfCS goes high simultaneously with WE high, the output remains in a high impedance state.
2. All Write Cycle timings are referenced from the last valid address to the first transitioning address.
3. Transition is measured ±200mV from steady state voltage with specified loading in Load B.
4. This parameter is sampled and not 100% tested.

~HITACHI
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300

117

HM6788H S.ies------------------------------__________________________________
• Timing waveform of Write Cycle No.1

/WE

Controlled)

Address

Data In

Data Out

•

.=t

Timing waveform of Write Cycle No.2 (CS Controlled)
_ t wc

Address

_ _ _ _ _ _ _ _ _ _ _ _-:-_ __

.

-------

----------~

tAS

tcw - - - + 1 , . - - - - - - twp*1

n\!;: tow -+~IJM

Data In
Data Out

""7r7'~XXr7r7XXr7r7XXr7r7XXnr7'xxnr7'xXL Data Valid M~XX~XX~XX
High Impedance *4

Note)*I. A write occurs during the overlap of a low CS and a low WE. (twp)
*2. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
*3. During this period. I/O pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
*4. If the
low transition occurs simultaneously with the WE low transition or after the
WE transition. the output buffers remain in a high impedance state.
*S. If CS is low during this period. I/O pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.

as

*6. Data Out is the same phase of write data of this write cycle.

Capacitance ( Ta=25'C. f= 1.0MHz)
Item

Symbol

min

typ

max

Conditions

Input Capacitance

CIN

6.0

VIN=OV

Input/Output Capacitance

Cdo

10

VI/O=OV

Note) This parameter is sampled and not l00q,.o tested.

•
118

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM6788HA Series- Preliminary
16384-Word x 4-Bit High Speed Static RAM
• FEATURES
• Super Fast
Access Time ........................ .12/15/20ns (max.)
• + 5V Single Supply
• Low Power Dissipation
(DC) Operating ..........................300mW (typ.)
• Completely Static Memory
No Clock or Timing Strobe Required
• Fully TTL Compatible-All Inputs and Outputs

• PIN ARRANGEMENT

• ORDERING INFORMATION

Type No.

(DP-22NB)

Access Time

Package

12ns
15ns
20ns

300 mil 22 pin

~o----I

AO
Al
A2
A3
A4
As
A6
A7
As
CS

A3o----I

Vss

HM6788HAP-12
HM6788HAP-15
HM6788HAP-20

Plastic DIP

(DP-22NB)

• BLOCK DIAGRAM

Aeo----I

- 0 Vee

-oVss

A7o----I

Aeo----I
As 0----1

Memory Matrix
128 X 512

~o--~~~
1101 o---'-1>~
1102o--#H

Vee

A13
A12
All
Am
Ag
1101
1102
1/03

1104
WE
(Top View)

Column 110

110:1 o---.i+H
1104 o-..-H+H.>-I

cso-t-----.--Cf"""l
WE~=====±~~~

_____~

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

119

HM6788HA Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS
Symbol

Rating

Voltage on Any Pin Relative to V ss

VT

-0.5 to +7.0

V

Power Dissipation

PT

1.0

W

Operating Temperature

Topr
T stg

o to +70

°C

Storage Temperature

-55 to + 125

°C

Temperature Under Bias

Tbias

-10 to +85

°C

Item

Unit

• RECOMMENDED DC OPERATING CONDITIONS (O°C :5 Ta :5 70°C)
Min.
4.5

Typ.

Max.

Unit

5.0

5.5

V

0.0

0.0

0.0

V

Input High (Logic 1) Voltage

Vss
VIH

2.2

-

6.0

V

Input Low (Logic 0) Voltage

V IL

-3.0*

-

0.8

V

Item

Symbol
Vee

Supply Voltage

'Pulse width :5 IOns, DC: -0.5V

• TRUTH TABLE
CS

WE

Mode

Vee Current

I/O Pin

Ref. Cycle

H

X

Not Selected

ISB,IsBI

HighZ

L
L

H

Read
Write

Icc, IcC!

Data Out
Data In

Read Cycle (1), (2)

L

Icc, IcC!

• DC AND OPERATING CHARACTERISTICS (Vee
Item

= O°C to 70°C, Vss = OV)

Test Condition

Min.

Typ.

Max.

Unit

IILlI

= 5.5V, VIN = Vss to Vee
CS = VIH , VI/O = Vss to Vee
CS = V IL , II/O, = OrnA
Min. Cycle Duty: 100% II/O = OrnA
CS = VIH

-

-

2

/LA

10
100

/LA
rnA

-

120

rnA

-

30

rnA

CS ~ Vee - 0.2V
VIN :5 0.2V or V IN

-

-

10

rnA

-

-

0.4

V

-

V

IILOI

Operating Power Supply Current

Icc

Average Operating Current

Ieel
ISB

Standby Power Supply Current (1)

ISBI

Output Low Voltage

VOL
VOH

Output High Voltage

± 10%, Ta

Symbol

Input Leakage Current
Output Leakage Current

Standby Power Supply Current

= 5V

Write Cycle (1), (2)

Vee

IOL
IOH

~

Vee - 0.2V

= 8mA
= -4mA

2.4

• AC TEST CONDITIONS
• Input Pulse Levels: Vss to 3.0V
• Input Timing Reference Levels: 1.5V
• Output Load: See Figure

• Input Rise and Fall Times: 4ns
• Output Reference Levels: 1.5V

+5V

4800

Dout

+5V

Dout

2550

2550

4800
5 pF *

Output Load B
(for tHZ , tLV twz , & tow)

Output Load A
'Including scope and jig capacitance.

.HITACHI
120

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 8 8 H A Series

• CAPACITANCE (Ta

= 2SoC, f = 1.0MHz)
Symbol

Max.

Unit

Input Capacitance

C IN

6.0

pF

VIN = OV

Input/Output Capacitance

CliO

10.0

pF

VIla = OV

Item

NOTE:

Conditions

This parameter is sampled and not 100% tested .

• AC CHARACTERISTICS (Vcc

= SV

± 10%, Ta

= O°C to 70°C, unless otherwise noted.)

• Read Cycle
Item

HM6788HA-12 HM6788HA-IS HM6788HA-20

Symbol

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Notes

Read Cycle Time

tRC

12

-

IS

-

20

-

ns

Address Access Time

tAA

12

ns

12

-

20

tACS
tOH

-

IS

Chip Select Access Time

-

20

ns

-

-

4

-

S

-

4

tLZ

4
3

S

-

ns
ns

1,2

tHZ

0

6

0

6

0

8

ns

1,2

Unit

Notes

Output Hold from Address Change
Chip Selection to Output in Low Z
Chip Deselection to Output in High Z
NOTES:

IS

I. This parameter is sampled and not 100% tested.
2. Transition is measured ±200mV from steady state voltage with specified loading in Load B.

• Write Cycle
Item

HM6788HA-12 HM6788HA-IS HM6788HA-20

Symbol

Min.

Max.

Min.

Max.

Min.

Max.

15

-

20

10

-

IS

-

10
0
10
0
7
0
0
3

-

IS

-

-

Write Cycle Time

twc

12

Chip Selection to End of Write
Address Valid to End of Write

lew
tAW

8

-

8

-

Address Setup Time

tAS
twp

0

-

Write Pulse Width

8

-

Write Recovery Time

tWR

0

-

Data Valid to End of Write

tDW
tDH

6
0

-

Data Hold Time
Write Enable to Output in High Z

twz

0

6

Output Active from End of Write

tow

3

-

NOTES:

-

ns

2

-

ns
ns

-

0

-

ns

-

IS

ns

-

ns

-

ns

-

10

-

6

0

-

ns

0

8

ns

-

3

-

ns

0

-

3,4
3,4

I. If CS goes high simultaneously with WE high, the output remains in a high impedance state.
2. All write cycle timings are referenced from the last valid address to the first transitioning address.
3. Transition is measured ±200mV from steady state voltage with specified loading in Load B.
4. This parameter is sampled and not 100% tested .

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

121

HM6788HA Series - - - - - - - - - - - . - - - - - - - - - - - - - - - - • TIMING WAVEFORM
• Read Cycle (1) (1) (2)

Address
tOH

tOH

Data Out

Previous Data Valid

Data Valid

• Read Cycle (2) (1) (3)

tRC

cs

~

It'

1'0..
tACS
tLZ

tHZ

Data Out
Hig himpede nce

NOTES:

KXXXXX) K

"

Data Valid

./

High
Impedence

1. WE is High for READ cycle.
2. Device is continuously selected, CS = VIL
3. Address valid prior to or coincident with CS transition low.

$
122

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 8 8 H A Series
• Write Cycle (1)

(WE Controlled)

twc

Address
tcw

cs
WE

High Impedance

High Impedance
Data In

tOH(6)

Data Out
• Write Cycle (2) (CS Controlled)
twc

"!.
/

)K

Address

tWR(2)

tAW

K

tAS

I

cs

~

tcw

/'(
twp(1)

WE
tDW

Data In

Data Valid
High Impedance (4)

Data Out
NOTES:

I. A wnte occurs during the overlap of a low CS and a low WE (twp).
2. tWR

IS

measured from the earlier of CS or WE going high to the end of write cycle.

3. During this period, 1/0 pins are in the output state so that the input signals of opposite phase to the outputs must not
be applied.
4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output
buffers remain in a high impedance state.
5. If CS is low during this period, 1/0 pins are in the output state. Then the data input signals of opposite phase to the
outputs must not be applied to them.
6. Dou! is the same phase of write data of this write cycle.

eHITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Pomt Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

123

HM6289 Series - - - - - - - - - 16384-Word x 4·Blt High Speed CMOS Static RAM (with OE)
The Hitachi HM6289 is a high speed 64k static RAM organized
as 16-kword x 4-bit. It realizes high speed access time (25/35/45 ns)
and low power consumption, employing CMOS process technology.
It is most advantageous for the field where high speed and high
density memory is required, such as the cache memory for main
frame or 32-bit MPU.
The HM6289, packaged in a 300-mil SOJ, is available for high
density mounting. Low power version retains the data with battery
back up.

Features
High speed
Access time:
25/35 ns (max)
High density 24-pin SOJ package
Low power
300 mW (typ)
Active mode:
Standby mode:
100 JlW (typ)
Single 5 V supply
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible: All inputs and outputs

Access Time
25ns
35ns
25ns
35ns

AI.

(Top V,ew)

Pin Description
Pin Name
AO-A13
I!01-I!04

Ordering Information
Type No.
HM6289JP-25
HM6289JP-35
HM6289LJP-25
HM6289UP-35

Pin Arrangement

Package
300-mil
24-pin
SOJ
(CP-24D)

CS
OE

WE
Vee
Vss

Function

Address
Input/output
Chip select
Output enable
Write enable
Power supply

Ground

Block Diagram
A2
A3
A4
A5
A6
A7
A8
1/01
1/02
1/03
1/04

~g+:===::t=;~)

tlEO+----+~T""'\

•
124

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 9 Series

Function Table

Note:

CS

OE

WE

H
L
L
L

x

x

L
H
L

H
L
L

Mode
Not selected
Read
Write
Write

I/O pin
High-Z
Dout
Din
Din

Vee Current
IsD,ISDI

Icc
lee
lee

Ref. Cycle
Read cycle (1 H3)
Write cycle (IH2)
Write cycle (3)-(6)

x; HorL

Absolute Maximum Ratings
Item
Voltage on any pin relative to Vss
Power dissipation
Operating temperature range
Storage temperature range
Storage temperature range under bias
Note:

Symbol
Vin

Value
-0.5'1 to +7.0
1.0
to +70
-55 to +125
-10 to +85

Pr

Unit
V
W
°C
°C
°C

o

Top<
To..
Tbiao

*1. Yin min = -2.0 V for pulse width :s; 10 os.

Recommended DC Operating Conditions (Ta = 0 to +70°C)
Symbol
Vee
Vss
Input high (logic 1) voltage
Vrn
Input low (logic 0) voltage
VIL
Item
Supply voltage

Note:

Min
4.5
0
2.2
-0.5'1

Max
5.5
0
6.0
0.8

Typ
5.0
0

Unit
V
V
V
V

*1. VIL min = -2.0 V for pulse width:S; IOns.

DC Characteristics (Ta = 0 to +70°C, Vee = 5 V ± 10%, Vss = 0 V)
Item
Input leakage current

Symbol
IILlI

Min

Typ'l

Max
2.0

Unit

2.0

J.lA

Output leakage current

IILaI

Operating Vee current

lee

60

120

rnA

Standby Vee current
Standby Vee current (1)

IsD
Is81'2
Is81"

15
0.02
0.02

30
2.0
0.1

rnA
rnA
rnA

Output low voltage
Output high voltage

VOL
VOH

0.4

V
V

2.4

Test Conditions
Vee = Max
Yin = OV to Vee
CS = Vrn
VIIO = 0 V to Vee
CS = VIL, 1110 = 0 rnA,
Min. cycle
CS = Vrn, Min. cycle
CS ~ Vee - 0.2 V
OV:s; Yin :s; 0.2 V or
Vee- 0.2 V:s; Yin
IOL=8mA
IOH=-4.0mA

IIA

Notes: *1. Typica1limits are at Vee = 5.0 V, Ta = +25OC and specified loading.
*2. P-version
*3. LP-version

Capacitance (Ta = 25°C, f = IMHz)
Item
Input capacitance
Input/output capacitance
Note:

Symbol
Cin
ClIO

Min

Typ

Max
6
8

Unit
pF
pF

Test Conditions
Yin =0 V
VI/O=OV

This parameter is sampled and not 100% tested.

$HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

125

HM6289 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - -

AC Characteristics (Ta =0 to +70°C, Vee =5 V ± 10%, unless otherwise noted.)
Test Conditions
Input pulse levels:
Input rise and fall times:
Input and output timing reference I~vels:
Output load:

Vssto 3.0 V

5 ns
1.5 V
See figures

Output Load (A)

Output Load (B)

(for IClIZ, Ia..z, 101lZ,
;>+5V
~480!l

Dout

Nole:

0----<..---+

Dout

25sn~F'

~

25S!l

IOU, IWIIZ & lOW)

:8::
5pF*

* Including scope & jig.

Read Cycle
Item

Symbol

Read cycle time
Address access time
Chip select access time
Chip selection to output in low-Z
Output enable to output valid
Output enable to output in low-Z
Chip deselection to output in high-Z
Chis disable to output in high-Z
Output hold from address change
Chip selection to ~wer ~ time
Chip deselection to power down time
Note:

IRC

HM6289-25
Min
Max
25

25
25

1M

tACS
tcLZ"\

5

toB
tou"\

0

tc/IZ"\

0

tollZ"\

0

toll

3
0

12

IPU

20
10

5
0
25

lPD

0
0
0

30

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

*1. Output transition is measured ±200 mV from steady state voltage with Load (B). This parameter is sampled and not 100%
tested.

$
126

12
10

HM6289-35
Min
Max
35
35
35
5
15

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6289 Series

Read Timing Waveform (1) 'I
I"

~ l(
A""_, ---.I
1\

\/
I\,
I ..

0.

,,\\\\\'\

II I II

/

/
I ..

cs

~I\

---!.o!...-

/VI IIII'u. III

~
I,a

Ie.,
I,u
DOl.lt

(&(

H..tIlmpeduce

nita VaRd

\.Vj(\
r\
j

Read Timing Waveform (2) 'I :2:4
I"

~I

A""N"

\V
/1\.

--.I \.
I ..

'M

*Xx)K

Dout

...

D.taVIlIlI

I

>KX

Read Timing Waveform 13)",'3,'4

"a
Dout

Notes: .1.
·2.
·3.
·4.

HiP Impedance

WE is high for read cycle.
Device is continuously selected, CS = Vn...
Address valid prior to or coincident with CS transition low.
OE=Vn...

Write Cycle
Item
Write cycle time
Chip selection to end of write
Address valid to end of write
Address setup time
Write pulse width
Write recovery time
Output disable to output in high-Z'!
Write to output in high-Z'!
Data to write time overlap
Data hold from write time
Output active from end of write'!
Note:

HM6289-25
Min
Max
25
20
20
0
20
0
0
10
0
8
12
0
5

Symbol
twe

tew
tAw

tAS
twP
twR

tOHZ
twHZ

tDw
tDH
tow

HM6289-35
Min
Max
35
30
30
0
30
0
0
10
0
10
20
0
5

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

.1. Output transition is measured ± 200 mV from steady state voltage with Load (B). This parameter is sampled and not 100%
tested.

•

HITACHI

Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

127

HM6289 S e r l e s - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Write Timing Waveform (1) (OE =High, WE =Controlled)

'''''
Addre..

'"

...
Ia.

Don

'"

D... Volid

Hiah 1m.........
Doul

Write Timing Waveform (2) (OE = High, CS = Controlled)

'''''
Addresl

'e.

''''

'"

,..,..1
Ia.

Do.

Dout

nata Valid

Iboh I ...........

.HITACHI
128

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 9 Series

Write Timing Waveform (3) (OE =Clocked, WE

=Controlled)
In

.-.~

\V

---.J\

DE

II I

/~

/ v'

\1\\\\\

I
I"

a

\ \\

\ 1\\
1M

WE

IVI I VII II
IV

I ..

f---!.!!..--

r.... 1

\\\

lou·2

I--huU~

....

\l

r-

H.... lmpedace

.11
I ..

I
D.

(X)l(

'''"---

I.

I
n.. vlhd

JKX)

Write Timing Waveform (4) (OE = Clocked, CS = Controlled)

I"

I ..

I ..

D.

0..,

$

HITACHI

Hitachi Amenca, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

129

HM6289 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Write Timing Waveform (5) (OE =Low, WE =Controlled)
"<
Addreu

Hllh Impedance
001,11

.5

Dm

Write Timing Waveform (6) (OE

=Low, CS = Controlled)
I~

Addreu

HiP. Impedance
001,11

Dm

A write occurs during the overlap of a low CS and a low WE. (tWp)
tWR is measured from the earlier of CS or WE going high to the end of write cycle.
During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffcrs remain
in a high impedance state.
*5. If CS is low during this period, I/O pins are in the output state after tow. Then the data input signals of opposite phase to the
outputs must not be applied to them.
*6. Dout is the same phase of write data of this write cycle, if tWR is long enough.
*7. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain in high
impedance state.

Notes: *1
*2.
*3.
*4.

•
130

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6289 Series

Low Vee Data Retention Characteristics (Ta =0 to +70°C)
This characteristics is guaranteed only for L-version.
Item
Vee for data retention
Data retention current
Chip deselect to data retention time
Operation recovery time
Note:

Symbol
VDR
IccoR

Min
2

tcDR
ta

0
tac·!

Typ

Max

Unit
V

50. 2
35. 3

IlA
ns
ns

Test Conditions
CS ~ Vee- 0.2 V,
Yin ~ Vcc-O.2 Vor
o V ~ Vin~ 0.2 V
See retention waveform

* I. tac =Read cycle time
*2. Vee =3.0 V
*3. Vee =2.0 V

Low Vee Data Retention Waveform

Data Retention Mode

v.., _ _ _ _ _ _-.I
4.5V--------

-------------------------

---------

CS"V..,-O.2V

~---------------------------------------------

•

HITACHI

Hitachi America, ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300

131

HM6289 Series
Supply Current ¥s. Ambient Temperature

Supply Current vs. Supply Voltage

1.6

'"
:.l

1. 6
Vcc=5.0V

To=25'C
1.4

]

~

E

~

1.2

Jl

1.0

~

0.8

8

>-

]: 0.6

----

-----

~

1.4

J

~

c

1.2

Jl

1.0

8~

0.8

t---

- t--- I---

~

§:

0.6



11

,

~

10

}

09

I

0.9

]

0.8

]

0.8

i

07

~
~

0.7

4.5

-------

~

Supply Voltage

1.0

5.25

50

475

1

5.5

~

14

.§

1.2

~

1.0

~

Vee (V)

1

0.8

]

0.6

i

0.4 1

/

\

f

o.

0.4

0.6

~"

/

/

1
:=
.

/

I

10

I
d

0.6

II

iii 0.8
o!l

!

/

40

Ambient TemperabJre

60

80

/

/V

0.4
0.2

o
20

VOL (V)

/

1.2

CIl

o

0.8

Standby Current VI. Supply Voltage

:8'
o. 1

I

I

1.4

I

5.5

/

Low Level Output Voltage

VOH (V)

Vcc=3V
CS=2.8V

1
~

I

0.2

2

10

5

5.25

Vee M

Ta=25'C
Vcc=5V

Standby Current va. Ambient Temperature

1.0

5.0

Output Current VI. Output Voltage (2)

\\

High Level Output Voltage

!

4.75

~

Ta=25'C
Vcc=5V

i

\

4.5

Supply Voltage

Output Current VI. Output Voltage (1)
11.6

----

--

~

2

----

V

Ta=25'C
CS=Vcc -O.2V

6

Supply Voltage Vee (V)

Ta ("C)

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

133

HM6289 S e r l e . - - - - - - - - - - - - - - - - - - - - - - - - - - - Standby Current va. Input Voltage
10

I
!
iii
.!I

8

6

i

4

..,E
!
Ul

2

a

Ta-25"C
Vcc=5.0V
CS=4.8V

1'\
j

1\

~

Input Voltage VIII (V)

•
134

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

HM6789 Series---- Maintenance Only
16384-word x 4-bit High Speed Hi-BiCMOS Static RAM (with OE)
Features
• Super Fast Access Time: . . . . . . . . . . . . . . . 25/30 ns (max)
• Low Power Dissipation (DC) Operating. . . .. 230 mW (typ.)
• +5V Single Supply
• Completely Static Memory
No Clock or Timing Strobe Required
• Balanced Read and Write Cycle Time
• Fully TTL Compatible Input and Output

HM6789P Series

Orderinglnforrnation
Type No.

Package

Access Time

HM6789P-25
HM6789P-30

25ns
30ns

300 mil 24 pin
plastic DIP

HM6789JP-25
HM6789JP-30

25ns
30ns

300 mil 24 pin
Plastic SOJ

A2 cr-----l

(DP-24NC)
HM6789JP Series

- - 0 Vcc

A3cr-----l

- - 0 Vss

A4o---f~

Memory Matn"

AScr-----l

128XS12

A6cr-----\

(CP-24D)

A7o-----\

AScr-----\
1/01 cr--r--I

>-1

Pin Arrangement

Col.... 1/0

1/02 cr-~f+-I

Column Decoder

1/03 cr-..-HH--l
1/04

o-t-++H-f>--1

Absolute Maximum Ratings
Item
Terminal Voltage to

vss Pin

Power Dissipation
Operating Temperature Range
Storage Temperature Range under bias
Storage Temperature Range

Symbol

Rating

VT
PT

-0.5 to +7.0

V

1.0

W

Unit

o to +70

·C

Tstg(bias) -10 to +85

·c
·c

Topr

-55 to+125

Tstg

•

(Top View)

HITACHI

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135

HM6789 Serl..

Recommended DC Operating Conditions (Ta = 0 to +70°C)
Item

Symbol

Supply Voltage

min

typ

max

VCC

4.5

5.0

5.5

V

VSS

0.0

0.0

0.0

V

Unit

Input High Voltage

VIH

2.2

6.0

V

Input Low Voltage

VIL

-0.5*'

0.8

V

Note) * 1. -3.0V for pulse width ~ 20ns.

Function Table
CS

OE

WE"

H

HorL

HorL

L

H

H

L

L

H

L

H

L

L

L

L

Mode

VccCurrent

1/0 Pin

Not selected

ISB,ISBI

HighZ

Output Disabled

ICC,ICCI

HighZ

ICC, IcCl

Dout

ICC, ICCI

Din

Write Cycle (1) (2) (3) (4)

ICC, IcCl

Din

Write Cycle (5) (6)

Read
Write

Ref. Cycle

Read Cycle (1) (2) (3)

DC and Operating Characteristics (VCc=5V±10%, Ta=O to +70°C)
Symbol

Item

min

typ

max

Test Conditions

Unit

= S.SV, VIN = VSS to Vee
CS = VIH or OE =VIH or WE = VIL
VIIO = VSS to Vec
CS = VIL, 11/0 = OmA

Input Leakage Current

(lLlI

2

",A

Output Leakage Current

IILOI

2

",A

Operating Power Supply Current

ICC

100

rnA

Average Operating Current

leCl

120

rnA

Min.Cycle,Duty: 100%,11/0=OmA

VCC

ISB

30

rnA

CS =VIH

ISBI

10

mA

CS~ VCC -0.2V
VIN ~ 0.2V or VIN ~ VCC - 0.2V

0.4

V

10L

V

10H

StandbY Power Supply Current
Output Low Voltage

VOL

Output High Voltage

VOH

2.4

= 8mA
= -4mA

AC Test Conditions
• Input pulse levels . . . . . . . . . . . . . . . . . . . . Vss to 3.0V
• Input and Output reference levels . . . . . . . . . . . . . . 1.5 V
• Input rise and fall time . . . . . . . . . . . . . . . . . . . . . . 4 ns
• Output Load: See Figure

Dout

Dou.
2551l

• iac1udi...
...,.oadjll

0 ..... Lood A

O._LoodB

{!:::::i!:f

•
136

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 8 9 Series
Capacitance (Ta = 25°C,[= 1.0MHz)

Item

----------------.------------------max

Unit

Imput Capacitance

Symbol
ClN

min

typ

6

pF

Test Conditions
VIN ; OV

Input/Output Capacitance

ClIO

8

pF

Vila

---------------------~------------

--------------------------------

;

OV

Note) This parameter is sampled and not 100% tested.
AC Characteristics (V cc=5V±1O%, Ta=O to +70°C, unless otherwise noted.)
Read Cycle

Item

Symbol

HM6789-30

HM6789-25
min

max

min

max

Unit
ns

30

Read Cycle Time

tRC

Address Access Time

tAA

25

30

ns

Chip Select Access Time

tACS

25

30

ns

25

Chip Selection to Output in Low Z

tCLZ"!

0

Output Enable to Output Valid

tOE

0

Output Enable to Output in Low Z

tOLZ"!

0

Chip Deselection to Output in High Z

tCHZ"!

0

Output Hold from Address Change

tOH
tT*2

5

Input Voltage Rise/Fall Time

ns

0
15

15

ns

12

ns

150

ns

0

ns

0
10

0
5

150

ns

Write Cycle

Item

HM6789-25

Symbol

min

max

HM6789-30

min

Unit

max

Write Cycle Time

twc

25

30

ns

Chip Selection to End of Write

tew

20

25

ns

0

ns

ns

Address Setup Time

tAS

0

Address Valid to End of Write

tAW

20

25

Write Pulse Width

twp

20

25

ns

0

ns

Write Recovery Time

tWR

0

Write to Output in High Z

tWHZ"!

0

Data Valid to End of Write

tDW

10

15

Data Hold Time

tDH

5

Output Disable to Output in Hihg Z

tOHZ·!

0

Output Active from End of Write

tOW·!

0

0

12

ns

20

ns

5
10

0

ns

10

0

ns
ns

Notes) * I. Transition is measured ±200mV from steady state voltage with Load (B).
This parameter is sampled and not 100% tested.
*2. IftT becomes more than 150ns, there is possibility of function fail.
Plea,c contact your neare,t Hitachi Sales Dept. regarding specification.

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

137

S~ies----------------------------------------------------------------

HM6789H

Timing Waveform
Read Cyde

11,° 1

Address

Dout

Read Cyde (2,° 1 , "2,"3

I"

Address
108

108

Data Valid

PreVIQVS Data Valid

Dout

Read Cycle (3,"1, °3, °4

cs
tCHZ

leu

Data Vabd

Dout

High Impedance

Notes) *1.
*2.
*3.
*4.

WE= VIH
~= VIL
(ffi = VIL

__
Address valid prior to or coincident with CS transition Low .

•
138

HITACHI

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 8 9 Series
Write Cycle (1) (OE

= H, WE Controlled)

Address

tAW

t ••

D",

t ••

nata Valid

High Impedance
Dout

Write Cycle (2) (OE

= H, CS Controlled)

Address

t ..

tAW

10.

Data Vahd

Din

High Impedance
Dout

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300

139

HM6789

Series--------------------------------------------------------------

Write Cycle (3)

lOE = Clocked, WE Controlled)
t.e

Address

te.

tAW

,.,.*1

Oout
tD.

tDR

HIgh Impedance

High Impedance

Data Vahd

Din

Write Cycle (4) IOE = Clocked, CS Controlled)

t.e

Address

tew

tAW

tD.

Din

nata Valid

Dout

•
140

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 8 9 Series
Write Cycle (5) (OE

=

L, WE Controlled)

I.,
Address

I,.

I,.
High Impedance
DOllt

*5

High Impedance
Data Vahd

Din

High Impedance

Write Cycle (6) (OE = L, CS Controlled)

I.,
Address

I"

f,.

es

I,.
fw*l

WE

Ibsh Impedance

DOllt

to.

IDH

High Impedance

Don

nata V.bd

Notes)*l. A write occurs during the overlap (twp) of a low CS and a low WE.
*2. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs
must not be applied.
*3. Dout is the same phase of write data of this write cycle.
*4. If the CS is low transition occurs after the WE low transition, output remain in a high impedance state.
*5. If CS is low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to
the outputs must not be applied to them.
*6. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain
in high impedance state.

~HITACHI

Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

141

HM6789H S e r i e s - - - - - - 16384-word x 4-bit High Speed Hi-BiCMOS Static RAM (with OE)
Features
• Super Fast Access Time: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15/20 ns (max)
• Low Power Dissipation (DC) Operating 0 0 0 0 0 280 mW (typo)
• +5V Single Supply
• Completely Static Memory
No Clock or Timing Strobe Required
• Balanced Read and Write Cycle Time
• Fully TTL Compatible Input and Output

HM6789HP Series

Ordering Information
Type No.

Access Time

Package

(DP-24NC)

HM6789HP-15
HM6789HP-20

15ns
20ns

300 mil 24 pin
plastic DIP

HM6789HJP-15
HM6789HJP-20

15ns
20ns

300 mil

HM6789HJP Series

24 pm pla'lIc SOl

Block Diagram
A8 0------1

- - 0 Vee

A7 0------1

--OVss

A6o---i
Row

Memory MatriX

Decoder

128 X 512

A50---~~

A4o---i

(CP-24D)

A3 o-----l
A20---t

Pin Arrangement
Column I/O
1/02 o-~ft-i

1/03 o-.,-rt+i
1/04 ~++-I-H

Absolute Maximum Ratings
Item

Symbol

Rating

Terminal Voltage to V SS Pin

VT

-0.5 to +700

V

Power Dissipation

PT

1.0

W

Operating Temperature Range
Storage Temperature Range under bias
Storage Temperature Range

Note)

Topr

(Top View)

oto +70 °c

T.tg(bias) -10 to +85

T.tg

Unit

-55 to+125

°c
°c

The specifications of this device are subject to change without notice.
Please contact Hitachi's Sales Dept. regarding specifications.

~HITACHI
142

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 8 9 H Series
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Item

Symbol

Supply Voltage

min

typ

max

VCC

4.5

5.0

5.5

V

VSS

0.0

0.0

0.0

V

Unit

Input High Voltage

VIH

2.2

6.0

V

Input Low Voltage

VIL

-0.5*·

O.S

V

Note) *i. -3.0V for pulse width

~

IOns.

Function Table
CS

OE

WE

H

Hor L

H orL

L

H

H

L

L

H

L

H

L

L

L

L

Mode
Not selected
Output Disabled
Read
Write

VccCurrent

I/O Pin

ISD.ISDI

High Z

Ref. Cycle

ICC. IccI

High Z

ICC. ICCI

Data Out

ICC. IccI

Data In

ICC. ICCI

Data Out

Read Cycle (1) (2) (3)
Write Cycle (1) (2) (3) (4)
Write Cycle (5) (6)

DC and Operating Characteristics (Vcc =5V± 10%, Ta=O to +70°C)
Unit

Test Conditions

Input Leakage Current

Item

Symbol
IILlI

2

p.A

VCC = 5.5V. VIN = VSS to VCC

Output Leakage Current

IILOI

10

p.A

CS = VIH orM = VlHorWE=VIL.
VIIO VSS to VCC

Operating Power Supply Current

Ice

100

rnA

CS = VIL. 11/0 = OmA

Average Operating Current

ICCI

120

rnA

Min.Cycle.Duty: 100%,II/0=OmA

ISD

30

mA

CS

10

mA

CS~ V cc - 0.2V
VIN ~ 0.2V or VIN ~ VCC - 0.2V

0.4

V

10L

V

10H

min

typ

max

=

Standby Power Supply Current
ISDI
Output Low Voltage

VOL

Output High Voltage

VOH

2.4

= VIH
= SmA
= -4mA

AC Test Conditions
• Input pulse levels . . . . . . . . . . . . . . . . . . . . Vss to 3.0V
• Input and Output reference levels . . . . . . . . . . . . . . 1.5 V
• Input rise and fall time . . . . . . . . . . . . . . . . . . . . . . 4 ns
• Output Load: See Figure
+5V

Output

Output
25511

25511
• inciudilll
leope .nd iii

Output Load A

Output Load B
('CHZ.

'rtHz.

10HZ

IcLZ. 10", tou)

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

143

HM6789H Series

Capacitance (Til = 25°C,[= 1.OMHz)
Item

Symbol

typ

min

max

Test Conditions

Unit

Imput Capacitance

CIN

6

pF

VIN = OV

Input/Output Capacitance

ClIO

10

pF

VIIO = OV

Note) This parameter is sampled and not .00% tested.

AC Characteristics (V cc=5V±10%, Ta=O to +70°C, unless otherwise noted.)
Read Cycle
Item

HM6789H-15

Symbol

min

max

HM6789H-20
min

max

Unit
ns

Read Cycle Time

tRC

Address Access Time

tAA

15

20

ns

Chip Select Access Time

tACS

15

20

ns

Chip Selection to Output in Low Z

tCLZ··

3

Output Enable to Output Valid

tOE

0

Output Enable to Output in Low Z

tOLZ··

3

Chip Deselection to Output in High Z

tCHZ··

0

Output Hold from Address Change

tOH

3

20

15

ns

3
12

0

12

3
6

0

ns
ns

8

3

ns
ns

Write Cycle
Item

HM6789H-15

Symbol

min

max

HM6789H-20
min

Unit

max

Write Cycle Time

twc

15

20

ns

Chip Selection to End of Write

tew

10

15

ns

Address Setup Time

ns

tAS

0

0

Address Valid to End of Write

tAW

10

15

ns

Write Pulse Width

twp

15

ns

Write Recovery Time

tWR

I

ns

Write to Output in High Z

tWHZ··

10
0

6

0

8

ns

Data Valid to·End of Write

tow

9

10

ns

Data Hold Time

tOH

0

0

ns

Output Disable to Output in High Z

tOHZ··

0

Output Active from End of Write

tOW··

0

6

0

8

0

Note) *1. Transition is measured :t200mV from steady state voltage with Load (B).
This parameter is sampled and not 100% tested .

•
144

HITACHI

Hitachi America. Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

ns
ns

-------------------------------------------------------------HM6789H S.iM
Timing Waveform
Reed Cycle (1)'1
loe

Address

OE

Data Out

Reed Cycle (2)'1, '2, '3

he

Address
I ..
I ..

Data Out

D... VUd

PrevIous Data ValId

Reed Cycle (3)'" '3, '4

tRe

leu

DataV.1uI

Data Out

Notes) *1. WE = VIH
*2. CS = VIL
*3. OE- VIL
*4. Address valid prior to or coincident with CS transition Low .

•

HITACHI

Hitachi America. Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819· (415) 589-8300

145

HM6789H

S-ia-------------------------------------------------------------

Write Cyde 111 (OE = H. WE Controlledl

'''''
Address

''''
cs

".
1.,.*1

WE

".
Data In

Dara

'"
v.....

Data Out

Write Cyde (21 (Of - H. CS Controlledl

'"
Address

".

'"
cs

".
WE

'"
Data In

Data Out

Dara Volid

Hilhl..........

•
146

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

----------------------------------------------------------------HM6789H S.iM
Write Cyde (3) IOE = Clocked,WE Controlled)
I.e

Address

OE

CS
I.w

WE

H.... 1m......."

Data Out

I ..

Iligh Impedance

Hlgh Impedance

Data In

Data Vahd

Write Cyde (4) IOE = Clocked, CS Controlled)

lwe

Address

lew

CS

t ..,.*1

WE
'DW

Data In

Da.. Valid

Data Out

$HITACHI
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra POint Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300

147

HM6789H

Series--------------------------------

Write Cycle (51 (OE = L, WE Controlled I

I'e

Address
Ie'

cs

WE

I.,
HOIh Impedance

Data Out

.5

High Impedance

Data In

High Impedance

Da.. V,M

Write Cycle (81 IOf a L, CS Controlledl

Address
I ..

Ie'

cs
t..,.*1

WE

!bob Impedance

Data Out

I.,

I ..

High Impedance

Data In

Data V.lld

Notes)*l. A write occurs during the overlap (twp) of a low CS and a low WE.
*2. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs
must not be applied.
*3. Data Out is the same phase of write data of this write cycle.
*4. If the CS is low transition occurs after the WE low transition, output remain in a high impedance state.
*S. If CS is low during this period, I/O pins are in the output state. Then, the data input signais of opposite phase to
the outputs must not be applied to them.
*6. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain
in high impedance state.

$HITACHI
148

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM6789HA Series - - - - - - - - - - P r e l i m i n a r y
16384-Word x 4-Bit High Speed Static RAM (with OE)
• FEATURES
• Super Fast
Access Time ....................Add. 12/15/20ns (max.)
DE 6/7/8ns (max.)
• Low Power Dissipation
(DC) Operating ..........................300mW (typ.)
• + 5V Single Supply
• Completely Static Memory
No Clock or Timing Strobe Required
• Fully TTL Compatible Input and Output

(DP-24NC)

• ORDERING INFORMATION
Type No.

Access Time

Package

HM6789HAP-12
HM6789HAP-15
HM6789HAP-20

120s
150s
200s

300 mil 24pio
Plastic DIP
(DP-24NC)

HM6789HAJP-12
HM6789HAJP-15
HM6789HAJP-20

120s
150s
200s

300 mil 24 pio
Plastic SOJ
(CP-24D)

• BLOCK DIAGRAM

AaO-----l
A70-----l
Aeo-----l
Aso----l
A40----l
A3 0----1':5;:]

A2

-oVcc
-oVss
Memory Matrix
128 X 512

• PIN ARRANGEMENT

Ao

vee

At

A'3
A12
All
AID
Ag

A2

Aa
A4
A5

o---~==~ :=::C===::::c:~_

IlOto--_--l
11020---'+-1-1
1103 o-_H-+~

(CP-24D)

Column 1/0

1104 o-....,f++~

As

NC

A7
As

1/0,
1/02

CS

1/03

OE

1/04

Vss

WE

(Top View)

_HITACHI
Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane. CA 94005·1819 • (415) 589-8300

149

HM6789HA Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Rating

VT
PT

-0.5 to +7.0

V

1.0

W

Voltage on Any Pin Relative to Vss
Power Dissipation
Operating Temperature Range
Storage Temperature Range (with bias)

o to

-10 to +S5

°C
°C

-55 to + 125

°C

Topr
Tstg(blas)
Tstg

Storage Temperature Range

Unit

+70

• RECOMMENDED DC OPERATING CONDITIONS (O°C :;; Ta :;; 70°C)
Item

Symbol

Min.

Typ.

Max.

Vec

4.5

5.0

5.5

V

Vss

0.0

0.0

0.0

V

Supply Voltage

Unit

Input High Voltage

VIH

2.2

-

6.0

V

Input Low Voltage

VIL*

-3.0

-

O.S

V

'Pulse width -; IOns, DC: -O.5V

• TRUTH TABLE
CS

OE

WE

Mode

Vcc Current

110 Pin

H

HorL

Hor L

Not Selected

HighZ

L
L

H

H

Output Disabled

ISB' ISB!
Icc, ICC!

HighZ

L

H

Read

Icc, IcC!

Data Out

Read Cycle (1) (2) (3)

L

H

L

Icc, Icc!

Data In

Write Cycle (1) (2) (3) (4)

L

L

L

Icc, IcC!

Data In

Write Cycle (5) (6)

Write

Ref. Cycle
-

• DC AND OPERATING CHARACTERISTICS (Vcc = 5V ± 10%, Ta = O°C to 70°C, Vss = OV)
Item

Symbol

Input Leakage Current
Output Leakage Current

Min.

Typ.

Max.

Unit

Ilul

Vcc = 5.5V, VIN = Vss to Vcc

Test Condition

-

-

2

p.A

IILOI

CS = VIH or OE = VIH, WE = V1L
VIIO = Vss to Vcc

-

-

10

p.A

Operating Power Supply Current

Icc

rnA

-

-

100

IcC!

CS = V1L , 1110 , = OmA
Min. Cycle, Duty: 100%,1110 = OrnA

-

Average Operating Current

120

rnA

ISB

CS = VIH

-

-

30

rnA

ISBl

CS ~ Vcc - 0.2V
V IN :;; 0.2V or V IN

-

-

10

rnA

VOL
VOH

-

-

0.4

V

10H = -4mA

-

V

Standby Power Supply Current
Output Low Voltage
Output High Voltage

~

IOL = SrnA

Vcc - 0.2V

2.4

• AC TEST CONDITIONS
• Input Pulse Levels: Vss to 3.0V
• Input and Output Reference Levels: 1.5V
± 200mV from steady level (Output Load 8)

• Input Rise and FaJl Time: 4ns
• Output Load: See Figure
+5V

+5V

DOU~

DOU~ 4800

4800

2550 L j 5 PF'

2550 L j 3 0 pF •

Output Load B
(for tCHz, tCLZ , 10HZ' tOLZ , twz & tow)

Output Load A
*Including scope and jig capacitance.

•
150

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6789HA Series
• TIMING WAVEFORM
• Read Cycle (1) (1)

Address

OE

cs
tCLZ

Data Out

tCHZ

Data Valid

High Impedance

• Read Cycle (2) (1) (2) (3)

RC

)~

)K

Address

tAA

tOH

tOH

Data Out

JOOO K

Previous Data Valid

X

Data Valid

• Read Cycle (3) (1) (3) (4)

tRC

cs

)t

K.
tACS

tCHZ
~

tClZ

Data Out

NOTES:

Highimpedance

rXX)K

Data Valid

"
/

1. WE = VIH
2. CS = VIL
3. OE = VIL
4. Address valid prior to or coincident with CS transition low.

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

151

HM6789HA Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • CAPACITANCE (Ta

= 25°C, f = 1.0MHz)
Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Input Capacitance

CIN

VIN = OV

pF

CliO

VIla = OV

-

6

Input/Output Capacitance

-

10

pF

Item

NOTE:

This parameter is sampled and not 100% tested .

• AC CHARACTERISTICS (Vcc

= 5V

= O°C to 70°C, unless otherwise noted.)

± 10%, Ta

• Read Cycle
Item
Read Cycle Time
Address Access Time

Symbol

HM6789HA-12 HM6789HA-15 HM6789HA-20

tRC
tAA

Chip Select Access Time

tACS

Chip Selection to Output in Low Z

leLz

Notes

Max.

Min.

Max.

Min.

12
-

-

15
-

-

ns

-

-

20

ns

-

12

-

-

20

ns

6
6
-

5

15
15
7
6
-

20

12

5

8
8
-

ns
ns

1,2

ns

1,2

ns

1,2

ns

-

Unit

Notes

Output Enable to Output Valid

toE

3
0

Output Enable to Output in Low Z

toLZ

2

Chip Deselection to Output in High Z

leHZ
tOH

0
4

Output Hold from Address Change

Unit

Min.

0
2
0
4

0
2
0
4

Max.

-

I

• Write Cycle
Item

HM6789HA-12 HM6789HA-15 HM6789HA-20

Symbol

Min.

Max.

Min.

Max.

Min.

Max.

-

15

-

20

-

ns

-

10

-

-

ns

-

0

-

15
0

-

ns

-

-

10

-

15

-

ns

-

6
-

10

-

15

-

ns

0

-

0

-

ns

0
7

ns

0

-

ns

6

I

8

ns

-

3

0
10
0
1
3

8
-

-

6
6
-

-

ns

Write Cycle Time

twc

12

Chip Selection to End of Write
Address Setup Time

lew
tAS

8
0

Address Valid to End of Write
Write Pulse Width

tAW
twp

Write Recovery Time

tWR

Write to Output in High Z

tWHz
tDW

8
8
0
0
6
0
1
3

Data Valid to End of Write
Data Hold Time

tDH

Output Disable to Output in High Z

tOHZ
tow

Output Active from End of Write
NOTES:

ns

I. Transition is measured ± 200mV from steady state voltage with Load B.
2. This parameter is sampled and not 100 % tested .

•
152

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

1,2
1,2
1,2

- - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6789HA Series
• Write Cycle (1)

(OE

= H, WE Controlled)
twe

Address
tew

cs
twp(1)

WE
tow

Data In

tOH

Data Valid
High Impedance

Data Out

• Write Cycle (2)

(OE = H, CS Controlled)
twe

Address
tAS

tew

CS
tAW
twp(1)

WE
tow

Data In

Data Valid
High Impedance

Data Out

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

153

HM6789HA Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • Write Cycle (3)

(OE = Clocked, WE Controlled)
twe

Address

OE
tew

cs
twp(1)

WE
tOLZ(2

High Impedance

Data Out

tDW

Data In

• Write Cycle (4)

tDH

~,m--------_.+.,.....,..High ImpedancE

High Impedance

(OE = Clocked, CS Controlled)
twe

Address

OE
tew

cs
tWA

twp(1)

WE

Data In
High Impedance
Data Out

~HITACHI
154

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6789HA Series
• Write Cycle (5)

(DE = L, WE Controlled)

Address
tew

cs
twp

WE

(1)

(2)

Data Out

High Impedance
tDW

Data In

tow

..---"'-'-'~

----...

tDH

_H.....;ig::..h_l_m..:.p_e_d_an_c_e_ _ _ _ _ _ _-<~r---D-at-a-v-a-li-d---M-..

(S) High

Impedance

OHITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

155

HM6789HA Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Write Cycle (6)

(DE = L, CS Controlled)

twc
Address

cs
twp

(1)

WE
High Impedance

Data Out

tDw

Data In

NOTES:

High Impedance

Data Valid

I. A write occurs dunng the overlap (twp) of a low CS and a low
2. During this period, 110 pins are
be applied.
3. Doul

IS

tDH

10

WE.

the output state so that the input signals of opposite phase to the outputs must not

the same phase of write data of this write cycle.

4. If the CS low transItIon occurs after the WE low transitIOn, output remain in a high impedance state.
5. If CS is low dunng this penod, 110 pins are 10 the output state. Then, the data input signals of opposIte phase to the
outputs must not be apphed to them.
6. If CS low transitIOn occurs simultaneously with the OE high transitIOn or after the OE transition, output remain in
high Impedance state.

~HITACHI
156

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM6287 Series

Maintenance Only

65536-word x '-bit High Speed CMOS Static RAM
• FEATURES
•
•
•

•
•
•
•

High Speed: Fast Access Time 45/55/70ns (max.)
Single 5V Supply and High Density 22 Pin Package
Low Power Standby and Low Power Operation
Standby: 100llW (typ.)/10IlW (typ.) (L-version)
Operation: 300mW (typ.)
Completely Static Memory
No Clock or Timing Strobe Required
Equal Access and Cycle Times
Directly TTL Compatible: All Inputs and Output
Capability of Battery Back Up Operation (L-version)

(DP-22N)

• PIN ARRANGEMENT
• ORDERING INFORMATION
Type No.

Package

Access Time

HM6287P-45
HM6287P-55
HM6287P-70

45ns
55ns
70ns

HM6287LP-45
HM6287LP-55
HM6287LP-70

45ns
SSns
70ns

300 mil 22 pin
Plastic DIP

• BLOCK DIAGRAM
A.

_Vo<

A.
A..

R••

+-- Vss
Me •• r, Arn,

A..

1111(511

A"
A..
A..

D"

es
WE

NOTE: Not for new designs.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy•• Brisbane. CA 94005-1819 • (415) 589-8300

157

HM6287S.IM-------------------------------------------------------------• TRUTH TABLE
CS

WE

Mode

H

X

Not Selected

L

H

Read

L

L

Write

Vee Current

Ref. Cycle

Dout Pin
High Z

-

Icc

Dout

Read Cycle

Icc

High Z

Write Cycle

ISB,lsBl

• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Rating

Unit

Voltage on Any Pin Relative to VSS

VT

-0.5"1 to +7.0

V

Power Dissipation

PT

1.0

W
·C

Operating Temperature

Topr

o to +70

Storage Temperature

Tit.

-55 to +125

·C

Temperature Under Bias

TblOi

-10 to +85

·C

Note) "I. -3.5V for pulse width;;; 20ns

• RECOMMENDED DC OPERATING CONDITIONS (Til = 0 to +70°C)
Item
Supply Voltage

Input Voltage

Unit

Symbol

min

typ

max

Vee

4.5

5.0

5.5

V

VSS

0

0

0

V

VIH

2.2

-

6.0

V

VIL

-0.5"1

-

0.8

V

Note) "1. -3.0V for pulse width ~ 20ns

• DC AND OPERATING CHARACTERISTICS (Vee
Symbol

Item

=SV ± 10%, VSS =OV, Ta =0 to +70°C)

Input Leakage Current

I ILl I

Vee = S.5V, Vln = Vssto Vee

Output Leakage Current
Operating Power Supply Current

Ihol
lee
ISB

CS - VIH, Vout= Vssto Vee
CS = V/L,lout - OmA, min. cycle

Standby Power Supply Current

ISBl
VOL
VOH

Output Voltage

min typ·l max
2.0
-

Test Conditions

-

CS = VIH, min. cycle
CS ~ Vcc-O.2V,
OV ::;; Vin ::;; 0.2V or Vee - 0.2V ;;; Vin
10L = SmA

2.4

IOH= -4.0mA
Notes) ·1. Typical bmits are at Vee = S.OV, Ta - 2S C and specIfied loadtng.

Unit
jlA

-

2.0

jlA

60

100

rnA

30 rnA
10
rnA
0.02 2.0
2.2 100"2 IIA

-

0.4

-

V
V

Q

• 2. This characteristics is guaranteed only for L·version.

• CAPACITANCE (/= IMHz, Til = 2S 0c)
Symbol

Item
Input Capacitance
Output Capacitance

qn
Cout

max

min

typ

V'n =OV

-

-

5

pF

Vout=OV

-

-

7.5

pF

Test Conditions

Note) This parameter is sampled and not 100% tested.

$
158

HITACHI

Hitachi America, Ltd. • Hitachi Plaza" 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

Unit

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 7 Series

• AC CHARACTERISTICS (Vcc = SV ±10%, Ta = 0 to +70°C, unless otherwise noted)
•

AC TEST CONDITIONS
Input Pulse Levels: Vss to 3.0V
Input Rise and Fall Times: 5ns
Input and Output Timing Reference Levels: 1.5V
Output Load: See Figure
Output Load B

Output Load A
5V

:g
5V

'800

'800

.

Doo.o---_p-_-+

D....

* Indudln. scope
•

•

5.F·

2550

3O.F

2550

& JI, upacilance

READ CYCLE
item

Symbol

Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Selection to Output in Low Z
Chip Deselection to Ou tpu t iii High 2:
Chip Selection to Power Up Time
Chip Deselection to Power Down Time

tRC
tAA
tACS
tOH
tLZ
tHZ
tpu
tPD

HM6287-4S
min
max
45
45
45
5
5
30
0
0
40
-

HM6287·SS
min
max
55
55
55
5
5
0
30
0
40
-

HM6287·70
min
max
70
70
70
5
5
30
0
0
40
-

-

-

Unit

Notes

ns
ns
ns
ns
ns
ns
ns
ns

I

2,3,7
2,3,7
7
7

Timing Waveform of Read Cycle No. 1 (4)( 5 )

~~----------------'.(----------------~~

Address

DoUI

~-,,,"--L-'flH
Dala Valid

• Timing Waveform of Read Cycle No.

2(4)(6)

Dout

~

Vee supply c:.c•• - - • current

---------------------------

'~"-l-_

50'1'1

ISH

Notes:

I. All Read Cycle timings are referenced from last valid address to the fust transitioning address.
2. At any given temperature and voltage condition, fHZ max. is less than fLZ min. both for a given device
and from device to device.
3. Transition IS measured ±500 mV from steady state voltage with specified loadmg m Load B.
4. WE is high for READ Cycle.
S. Device is continuously selected, whIle CS = VIL.
6. Address valid pnor to or coincident WIth CS transitIOn low.
7. This parameter is sampled and not 100% tested.

~HITACHI
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159

HM6287 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• WRITE CYCLE
Symbol

Item
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enabled to Output in High Z
Output Active from End of Write

twe
lew
tAW
tAS
twp
tWR
tDW
IDH
IWZ
tow

HM628745
min
max
45
40
40
0
25
0
25
0
0
25
0
-

HM6287-55
max
min
55
50
50
0
35
0
25
0
0
25
0

HM6287-70
min
max
70
55
55
0
40
0
30
0
30
0
0

Unit

Notes

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

2

• Timing Waveform of Write Cycle No.1 (WE Controlled)
III(

Address

~

- 1\
1---"'_
WE

..".

,

"tI·~

\\ \

.C

Don

Dout

IJI1

IData

. t::!

-

In

1---"'fJH

ValidX'

,

\---tlJII

f-'"~

High Impedance

Data Undefined

• Timing Waveform of Write Cycle No.1 (CS Controlled)

,.,

I'

tAil

t"3

1

".

1

_I.,

!---'."-

.L
l

Din

.1'0"

lJI'

Data m Vahd

*-

l-----tllL

Dout

Notes) 1.
2.
3.
4.

Data Undefined

If CS goes high Simultaneously with WE high, the output remains in a high impedance state.
All Write Cycle timings are referenced from the last valid address to the first transitioning address.
Transition is measured ±500mV from steady state voltage with specified loading in Load B.
This parameter is sampled and not 100% tested .

•
160

High Impedance

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

3,4
3,4

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 7 Series

• LOW Vee DATA RETENTION CHARACTERISTICS (Ta

= 0 to +70°C)

This characteristics is guaranteed only for L-version.
Parameter

Vcc for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Note) *1. tRC - Read Cycle Time
*2. Vee = 3.0V

•

Symbol

Test Condition

VDR
ICCDR
teDR
tR

CS~ vee-Nv'
V{p ~ Vee-.
or
o S-Vin S; 0.2V

typo

max.

-

-

Umt
V

-

I

50.2

/loA

0

-

-

ns
ns

min.
2.0

See retention waveform

tRC· 1

-

LOW Vee DATA RETENTION WAVEFORM
Data Retention Mode

\.1

Vee _ _ _ _ _ _ _

45V---------

--- -- ---- -- - -- - - -- - - - - ---

CSii=Vcc-O 2V

Cs _ _ _ _..1

w ____________________________________________ _

SUPPLY CURRENT vs. SUPPLY VOLTAGE

SUPPLY CURRENT vs. AMBIENT TEMPERATURE
6

I.6

Vcc=5.0V

Ta=25°C
1.4

•

I.

2

8

~
~

~

]

~

1 Or--1.

6

0.

4.5

r-- ~

8

6

•

1.2

4.75

5.0

5.25

•

O•

5.5

20

40

60

80

Ambient Temperature To ("C)

Supply Voltage Vee (V)

•

HITACHI

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161

HM6287 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ACCESS TIME vs. AMBIENT TEMPERATURE

ACCESS TIME vs. SUPPLY VOLTAGE

13

1.3
Ta~25·C

Vcc=5.0V

1. 2

1.2

1
1

1. 1

~

1.0

~

O.9

:---

~
j

~

...,

1

11

J

10

~

0.9

r--

j

j

08

45

5.25

,../
~

0.8

07

5.0

4.75

V

~

---- -

7

..,../

5.5

o

STANDBY CURRENT
SUPPLY VOLTAGE

STANDBY CURRENT vs.
AMBIENT TEMPERATURE

14

j

O.8

]

f

o. 6
O.

--

/

V

4~

/

80

Ambient Temperature Ta ("C)

VS.

2

60

40

20

Supply Voltage Vee (V)

10

/

/

Vcc=3V
Cs~2.8V

1

.Ta=2S"C
V,e-0.2V

CSi

,/

'/

,/'

/

,

o. 2

SUPPLY CURRENT
FREQUENCY

60

40

20

AmbIent Temperature Ta (Oe)

Supply Voltage Vee (V)

STANDBY CURRENT vs.
INPUT VOLTAGE

¥s.

T(ns)

200

1.1

100

50

66

40

10
Ta=2S·C

I

~o'

~

1.0

Vcc =5.0V

--

/

0.9

]

o.6
o. 5

\

/

7

en

/'

/"

.!! o.8

1 o.

Cs~4.8V

/'

/

2

10

15

20

25

Frequency j (MHz)

0

\

""

i'....

Input Voltage VltdV)

~HITACHI
162

Hitachi America, Ltd • Hitachi Plaza' 2000 Sierra POint Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300

80

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 7 Series
INPUT LOW VOLTAGE
SUPPLY VOLTAGE

INPUT HIGH VOLTAGE
SUPPLY VOLTAGE

VS.

VI.

1.3

1.3

T.~25"C

T.~25·C

I. 2

1.2

1

1

-------

1.0

1
j

:s:

!

0.9

0.8

O. 7

4.5

4.75

50

~

I----

1.

:!
~

1.

0

>
oj o.
:<:

J--- V-

1 o.

5.25

1

8

O.7

5.5

---

~

4.5

5.0

4.75

5.25

5.5

Supply Voltage Vcc (V)

Supply Volta8e Vee (V)

OUTPUT HIGH CURRENT VI.
OUTPUT HIGH VOLTAGE

OUTPUT LOW CURRENT VI.
OUTPUT LOW VOLTAGE
I.6

3.0

Ta=2SoC

'i
~

2.5

~

2.0

~

I.5

<3

~

I. 0

!

o. 5
0

Vcc=5V

\

\
i\

\

'i

I. 4

1
3

1.2

I

I.

0

u

\

j

!

\

0.8

o.6

o.4

Output High Voltage VOH (V)

/

/

/
V

.1

Ta=2S"C

Vcc=5V

V
0.2

0.4

Output Low Voltage

0.6
VOL

0.8

(V)

~HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300

163

HM6287H Series
65536-Word x 1-Bit High Speed CMOS Static RAM
The Hitachi HM6287H is a high speed 64K static RAM organized
as 64-kword x 1-bit. It realizes high speed access time (25/35 ns) and
low power consumption, employing CMOS process technology and
high speed circuit designing technology. It is most advantageous for
the field where high speed and high density memory is required,
such as the cache memory for main frame or 32-bit MPU. The
HM6287H packaged in a 300-mil plastic DIP and SOJ, is available
for high density mounting.
Low power version retains the data with battery back up.

HM6287HP Series

(DP-22NB)
HM6287HJP Series

Features
• Single 5 V supply and high density 22-pin DIP and 24-pin SOJ
• High speed:
Fast access time 25/35 ns (max)
• Low power
Operation: 300 mW (typ)
Standby:
100 IlW (typ)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Directly TIL compatible: All inputs and outputs

Pin Arrangement

Pin Description
HM6287HJP Series

HM6287HP Series

AO
Al
A2
A3
A4
A5

vee

A15
A14
A13
A12
All
Ala

A6
A7
Dout

A9
AS
Din

WE

AO
Al
A2
A3

vee

A15
A14
A13
A12
NC
All
Ala

A4

A5
NC
A6

A9
AS
Din

A7
Dout

WE

cs

Vss

(CP-24D)

V .. '-'-_ _- '

Pin Name
AO-A15
Din
Dout
CS
WE
Vee
Vss

Function
Address
Input
Output
Chip select
Write enable
Power supply
Ground

CS

(Top View)

(Top View)

Ordering Information
Type No.
HM6287HP-25
HM6287HP-35
HM6287HLP-25
HM6287HLP-35
HM6287HJP-25
HM6287HJP-35
HM6287HUP-25
HM6287HLJP-35

Access Time
25 ns
35 ns
25 ns
35ns
25 ns
35 ns
25 ns
35 ns

Package
300-mil
22-pin
plastic DIP
(DP-22NB)
300-mil
24-pinSOJ
(CP-24D)

~HITACHI
164

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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 7 H Series

Block diagram
AO
-Vee
A2

-Vss

A3

Row

Memory Array

Oecoder

128X512

A4
A5
A6

Din

--1':>--+--1

Dout

Function Table
CS
H

WE

L
L

H

Note:

x
L

Mode
Standby
Read
Write

Vee Current
ISB,IsBI

Icc
Icc

Ref. Cycle

DoutPin
High-Z
Dout
High-Z

Read cycle 1, 2
Write cycle 1, 2

x: H orL

Absolute Maximum Ratings
Item
Voltage on any pin relative to V ss
Power dissipation
Operating temperature
Storage temperature
Storage temperature under bias
Note: *1. VTmin =-2.0 V for pulse width!> IOns

Symbol
VT

PT
Topr
Tstg
Tbias

Unit
V
W

Value

-0.5"1 to +7.0
1.0
o to +70
-55 to +125
-10 to +85

·C
·C
·C

Recommended DC Operating Conditions (Ta =0 to + 70°C)
Item
Supply voltage
Input high (logic 1) voltage
Input low (logic 0) voltage
Note:

Symbol
Vee
Vss
Vm
VIL

Min

4.5
0
2.2
-0.5"1

Typ

Max

5.0
0

5.5
0
6.0
0.8

Unit
V
V
V
V

*1. VIL min = -2.0 V for pulse width!> IOns

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Bnsbane, CA 94005-1819 • (415) 589-8300

165

HM6287H Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

DC Characteristics (Ta =0 to +70°C, Vee =5 V ± 10%, Vss =0 V)
Item
Input leakage current

Typ"

Min

Symbol
I lui

Max
2.0

Unit

2.0

JlA

Output leakage current

Ih.o I

Operating Vee current

Ice

60

120

rnA

Standby Vee current

Iso

15
0.02

30
2.0

rnA
rnA

Standby Vee current (1)

Iso,
0.02'2

0.1'2

Output low voltage
Output high voltage

VOL
VOII
.-----~

--.-~------------

-_.

2.4

---- --- _. ---

Notes: *1. Typical limits are at Vee =5.0 V, Ta

---------~~-

rnA
V
V

--------------

0.4

---

Tcst Conditions
Vee = Max
Yin = Vss to Vee
CS = VDI
VI/O = Vss to Vee
CS = VIL
lout = 0 rnA, min cycle
CS = VOl, min cycl:. ___
CS ~ Vee - 0.2 V
oV s Yin S 0.2V or
Vee-O.2 Vs Yin
- -- -- - -----_. ---101. = 8 rnA
---_._-----1011 = -4.0 mA

JlA

---

=25°C and specifIed loading.

*2. This characteristics is guaranteed only for

L-vcr~lOn.

Capacitance ( Ta = 25°C, f = ).0 MHz )"
Item
Input capacitance
Output capacitance
Note:

Symbol
Cin
Cout

Max

Min

6
8

- -U-nh
pF
pF

TcstCo~ldili(ms----·

Yin = 0 V
Vout=OV

-------~---~-----

.1. This parameter is sampled and not 100% tested.

AC Characteristics (Ta =0 to +70°C, Vee = 5 V ± 10%, unless otherwise noted. )
Test Conditions
• Input pulse levels: Vss to 3.0V
• Input rise and fall times: 5 ns
Output Load (A)

00"

d
2"0

Note:

• Input and Output timing reference levels: 1.5 V
Output load: See figures
Output Load (El

(for

til?, 11.7., tWI.

& tow)

'"OO

-I'O'f.

Including scope & jig

.HITACHI
166

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

.~----

HM6287H Series

Read Cycle
Symbol

Item
Read cycle time
Address access time
Chip select access time
Output hold from address change
Chip selection to output in low-Z
Chip deselection to output in high-Z
Chip selection to power up time
Chip deselection to power down time

IRc

tAA
lACS

tOH
ILZ'!
tHz'!
lPu

tI'D

HM6287H-25
Max
Min
25
25
25
3
5
0
12
0
25

HM6287H-35
Min
Max
35
35
35
5
5
20
0
0
30

Unit
ns
ns
ns
ns
ns
ns
ns
ns

Read Timing Waveform (1) '2,'3,'5

..
Addreu

.,
Doul

I"

to •

PreviOUS
Dal&

Valid

0,11 Valid

Read Timing Waveform (2)'2. '4

"e
I.cs

'v
Doul

Vee S\lPPI, Currenl

ke
- - - - - - - - - -

-Jr-------------------,rso..

~h-.------------r
Notes: *1.
*2,
*3.
*4.

Transition is measured ±200 mV from steady state voltage with Load (B). This parameter is sampled and not 100 % tested.
WE is high for read cycle.
Device is continuously selected, CS = VIL.
Address valid priorto or coincident with CS transition low.
*5, AU read cycle timing are referenced from last valid address to the first transitioning address.

~HITACHI
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167

HM6287H Series

WrHeCycle
Item
Write cycle time
Chip selection to end of write
Address valid to end of write
Address setup time
Write pulse width
Write recovery time
Data valid to end of write
Data hold time
Write enabled to output in high-Z
Output active from end of write

HM6287H-25
Max
Min
25
20
20
0
20
0
15
0
0
8
5

Symbol
twe

tcw

tAw
tAs
twp
twR

tow
toH
twz')

tow')

HM6287H-35
Min
Max
35
30
30
0
30
0
20
0
0
10
5

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Write Timing Waveform (1) (WE controlled)

Address

tDW

Data .n
Valid

Din

twz
Oaut

High Impedance

~HITACHI
168

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6287H Series

Write Timing Waveform (2) (CS Controlled)
twe
Address

tew

Din

High Impedance"

Dout

Notes: .1.
·2.
·3.
·4.

Transition is measured ±200 mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested.
A write occurs during the overlap of a low CS and a low WE. (tWP)
twa is measured from the earlier of CS or WE going high to the end of write cycle.
IT the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain
in a high impedance state.
·5. Dout is the same phase of write data of this write cycle, if twa is long enough.

Low Vee Data Retention Characteristics ( Ta = 0 to +70°C)
(This specification is guaranteed only for L-version.)

Item
Vee for data retention
Data retention current
Chip deselect to data retention time
Operation recovery time

Symbol
VOR
IcCOR

Min
2.0

tCOR

Typ

0

IR

IRC'!

Max

Unit
V

50'2
35'3

flA
ns
ns

Test Condition
TI~ Vcc- 0.2 V
Yin ~ Vcc-O.2 Vor
oV ::; Yin ::; 0.2 V
See retention waveform

=
=

Notes: .1. lac Read cycle time
·2. Vee 3.0 V
·3. Vee = 2.0 V

Low Vee Data Retention Timing Waveform
Data Retention Mode
Vee

V. R
CS;S:V. R -O.2V

OV

----------------------------------•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

169

HM8287HSer.s----------------------------------------------------Supply Current vs. Supply Voltage

Supply Current vs. Ambient Temperature
1.6

1.6

j

Ta=25'C

:ti'
~

1.4

;.;

:.;

E 1.2
~
]

1.0

~

08

~

B:

0.6

-----

----- -----

Vce=5.0V
1.4

E 1.2
~u

~

..!:l

!

U
>.

1

='

1.0

t--- r--

0.8
06


II)

~

1.0

~

'0
:>

0.9

.s
_

O.S

!

0.7

'"
:.;

i!l

i----""

~

Ta=25'C

~

1. 2

?._

1. 1

1. 2

§

b

'" 1.

Ta=25'C

;;
:>

~ 1. 0

5

~

O•9

.<::

~

---

~

~

.~

::c
::;

O.S

.s4.5

4.75

5.0

5.25

5.5

4.75

5.0

5.25

5.5

Supply Voltage Vee (V)

Supply Voltage Vee (V)

Output Current va. Output Voltage (1)

Output Current vs. Output Voltage (2)
~

1.6

]

Ta=25'C
Vcc=5V

i!l

1.4

1\
\

~

~

1.2

.9
i:

1.0

~

O.S

~
U

\

j

3

~ 0.6

8
4

'"
i!l

V

~

1.2

j

E
1.0
0

iii O.S

~

!

U

0.6
0.4

.g ,
3

CI)

40

0.6

b

5~

60

SO

Ambient Temperature Ta (0C)
.J

0.4

1.4

Vcc=3V
CS=2.SV

20

0.2

O.S

Standby Current va. Supply Voltage

10

1

/

i

~

Output Low Voltage VOL (V)

Standby Current va. Ambient Temperature

/

V

0.4 0

Output High Voltage VOH (V)

/

L

J

\
2

Ta=25'C
Vcc=5V

., 1.4

,

E
~ 1.2

1.6

0.2

--

V

L

/

/

/

/

Ta=25'C
._
cs=rcc -0.2V

345

Supply Voltage Vee (V)

~HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

171

HM6287H Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Standby Current

va, Input Voltage

a
To ='25'(;
Vcc=5.0V
CS=4.8V _

8

II

)

\

~
2

~

3

4

5

Input Voltage Vin (V)

.HITACHI
172

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM6787 Series

Maintenance Only

65536-word x 1-bit High Speed Hi-BiCMOS Static RAM
HM6787P Series

• FEATURES
•
•
•
•
•
•
•
•

Super Fast Access Time: 25ns/30ns (max.)
Low Power Dissipation (DC):
Operating l80mW (typ)
High Driving Capability: IOL l6mA
+5V Single Supply
Completely Static Memory
No Clock or Timing Strobe Required
Balanced Read and Write Cycle Time
Fully TTL Compatible Input and Output
Skinny 22·pin Plastic Dip (300 mil) and 22·pin Chip Carrier

(DP·22NB)

• ORDERING INFORMATION
Type No.

Access Time

HM6787p·2S
HM6787P·30

2Sns
30ns

Package
300 mil 22 pin
Plastic DIP

• PIN ARRANGEMENT
•

HM6787P Series

• BLOCK DIAGRAM
---() Vee
---0

VS5

Memory Matrix

128X512

j
~~

WE~

-0

~"~'/O

Dout

A6A7A8A2A3A4A5AOAl

(Top View)

.ABSOLUTE MAXIMUM RATINGS
Item
Terminal Voltage to Vss Pin
Power Dissipation
Operating Temperature Range
Storage Temperature Range

Symbol
VT
PT
Top,
Tstg

Rating

-0.5 to +7.0
1.0

o to +70
-55 to +125

•

Unit
V
W

'c
'c

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

173

HM6787

Series----------------------------------

• TRUTH TABLE
CS

WE

Mode

H

X

Not Selected

Output Pin

L

H

Read

Icc

Dout

L

L

Write

Icc

High Z

Vee Current

High Z

ISB.ISBl

• RECOMMENDED DC OPERATING CONDITIONS (O°C ~ Ta ~ 70°C)
Item
Supply Voltage
Input High Voltage
Input Low Voltage
Note)

* 1.

min.

typo

max.

Vee

4.5

5.0

5.5

V

VSS

0

0

0

V

6.0

V

0.8

V

Symbol

VlH

2.2

VIL

-0.5'1

-

Unit

-3.0V for pulse width ~ 20ns .

• DC AND OPERATING CHARACTERISTICS (Vcc = 5V±1Q%, To =O°C to +70°C)
Item

Symbol

Test Conditions

Input Leakage Current

IhII

Vee =5.5V, VIN = Vss to Vee

Output Leakage Current

I/LOI

CS= VIH , VOUT= Vssto Vee

Operating Power Supply Current

IcC

CS= VIL,IOUrOmA

ISB

CS= VIH
CS~ Vee -0.2V

Standby Power Supply Current
ISBl

min.

typo

-

-

2

IlA

100
40

rnA
rnA

-

-

20

rnA

-

0.5

V

-

V

VIN~0.2Vor VIN~Vee-0.2V

Output Low Voltage

VOL

Jo L = 16mA

-

Output High Voltage

VOH

IOH=-4mA

2.4

TEST CONDITIONS
• AC
Input pulse levels:
to 3.0V

Out put Load A

Vss

(for

1HZ, ILZ, IWZ

480 Q
480 Q

Dout
Dout
3OpF*
255 Q

5pF*

• Including scope and jig.

~HITACHI
174

IlA

& tow)

+5V

255 Q

Unit

2

Output Load B

+5V

Input rise and fall times: 4ns
Input timing reference levels: 1.5V
Output reference levels: 1.5V
Output load: See Figure

max.

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300

---------------------------------------------------------------HM6787SeriH
• CAPACITANCE (Ta

=25°C.I= 1.0MHz)

Item
Input Capacitance
Output Capacitance

Symbol

max

Unit

Conditions

CIN

5.0

pF

VIN = OV

7.0

pF

VOUT=OV

COUT

Note) This parameter is sampled and not 100% tested.

• AC CHARACTERISTICS (VCC = 5V±IO%, Ta =O°C to 70°C, unless otherwise noted.)
•

READ CYCLE
Item
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Selection to Output in Low Z
Chip Deselection to Output in High Z
Chip Selection to Power Up Time
Chip Deselection to Power Down Time
Input Voltage Rise/Fall Time

HM6787-25
min
max
25
25
25
5
5
15
0
0
25
150

Symbol

tRC
tAA
tACS
tOH
tLZ
tHZ
tpu
tPD
tT

HM6787-30
min
max
30
30
30
5
5
15
0
0
-

-

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

30
150

Notes

1,2
1,2
2
2
3

Notes) 1. Transition is measured ±200m V from steady state voltage with specified loading in Load B.
2. This parameter is sampled and not 100% tested.
3. If tT becomes more than 150ns, there is possibility of function fail.
Please contact your nearest Hitachi's Sale Dept. regarding specification.

•

WRITE CYCLE
Item
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write

Note: 1.
2.
3.
4.

Symbol

twc
tcw
tAW
tAS
twp
tWR
tDW
tDH
twz
tow

HM6787-2S
min.
max.

2S

-

20
20
0
20

-

-

-

S

-

20
0
0
0

15

-

HM6787-30
min.
max.
30
25
25
0
25
5
25
0
0
15
0
-

Unit

Notes

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

2

3,4
3,4

If CS goes high simultaneously with WE high, the output remains in a high impedance state.
All Write Cycle timings are referenced from the last valid address to the first transitloning address.
Transition is measured ±200mV from steady state voltage with specified loading in Load B.
This parameter is sampled and not 100% tested.

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

175

HM8787SeriM------------------------------------------------____________

• TIMING WAVEFORM OF READ CYCLE NO. 11 ). 2)

IRe

Address

IAA
IOH

Dati Out

Previous Data Valid

Data Valid

• TIMING WAVEFORM OF READ CYCLE NO. 21 ).3)

IRe

lACS

!LZ

Dati Out

High Impedance
Data Valid

IPlJ

Vee Supply

Current

Note: 1. WE Is high and CS is low for READ cycle.
2. Addresses valid prior to or coincident with CS transition low.
3. Transition Is measured ± 200mV from steady state voltage with specified loading in Load B.

•
176

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 8 7 8 7 Series

•

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)
twe

Address

lew

tAW
!AS
twp

tow
Data In

Data In Val id
!wZ

Data Out

Data Undefined

HIgh Impedance

Note: 1. Transition is measured ±200mV from steady state voltage with specified loading in Load B.

•

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED)
Iwe

Address

~

j

j~
!AS
!ew

'i

,I
lAW

!WR
!wP

1//////

\. \. \. \. \. \. '~

tOH

tow

'W

Data In

Data In Valid

j\,

)\.

IWZ

Data Out

,

Data Undefined

High Impedance

Note: 1. Transition is measured ±200mV from steady state voltage with specified loading in Load B.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589-8300

177

HM6787H S e r i e s - - - - - - 65536-word x 1-bit High Speed Hi-BiCMOS Static RAM
Features
• Super Fast Access Time: 15n5/20n5 (max.)
• Low Power Dissipation (DC):
Operating 210mW (typ)
• +5V Single Supply
• Completely Static Memory
No Clock or Timing Strobe Required
• Balanced Read and Write Cycle Time
• Fully TTL Compatible Input and Output

HM6787HP Series

(DP-22NB)

Ordering Information
HM6787H1P Series
Type No.

Access Time

Package

HM6787HP-15
HM6787HP-20

15ns
20ns

300 mil 22 pin
Plastic DIP

HM6787H1P-15
HM6787H1P-20

15ns
20ns

300 mil 24 pin
Plastic SOl

L

Block Diagram
Vee

A,
A,
A,
As
A,
A,
A,

--0
--0

Row

Vss

Memory Matrix

,

(CP-240)
----------------~

128x512

Dout

Pin Arrangement
HM6787HP Series

HM6787HJP Series
AO
Al
A2

AlS

A3

Al3

A4

Al2

Vee

Al4

AS

NC

NC

All

A6

Ala

A7

A9

Dout
WE

A8

Vss

CS

Din

(Top View)

Note)

The specifications of this device
are subject to change without
notice.
Please contact Hitachi's Sales
Dept. regarding specifications.

~HITACHI
178

Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

----------------------------------------------------------------HM6787H

S.i~

Absolute Maximum Ratings
Symbol

Item
Terminal Voltage to Y88 Pin
Power Dissipation
Opera tin. Temperature Range
Storage Temperature Range

YT
PT
Top,
Tstg

Temperature under Bias

TbllJl

Rating
-o.S to +7.0
1.0
o to +70
-SS to +12S
-10 to +SS

Unit
V
W
·C
·C
·C

Function Table
CS

WE

Mode

H

X

Not Selected

L

H

Read

L

L

Write

Output Pin

YccCurrent

High Z
ICC,lCCl

Dout

Icc,lCCl

High Z

Recommended DC Operating Conditions (OOe ~ Ta ~ 70°C)
Item
Supply Voltage

min.

typo

max.

Vcc

4.S

S.O

S.S

V

Vss

0

0

0

V

Symbol

Unit

Input High Voltage

VIH

2.2

6.0

V

Input Low Voltage

VIL

-O.S*1

O.S

V

Note) .1. -3.0V for pulse width ~ IOns.

DC and Operating Characteristics (Vee =SV±lO%, Ta
Item

Symbol

Input Leakage Current
Output Leakage Current
Operating Power Supply Current

Icc

Average Operating Current

typo

min.

=oOe to +70°C)
max.

Test Conditions

Unit

11£11

2

"A

Vcc=S.SV, VJN= VSS to Vee

Ihol

10

CS = VIH , VOUT= YSS to Yee

100

"A
rnA

ICCl

120

rnA

Min. Cycle, Duty: 100%

ISB

30

rnA

CS= VIH

ISB1

10

rnA

Output Low Voltage

VOL

0.4

V

10L= SmA

Output High Voltage

VOH

V

IOH"'-4mA

CS= VIL , IOUT=OmA

IOUT=OmA

CS~ VCC -0.2V

Standby Power Supply Current

2.4

•

VIN:!!0.2Vor VIN~Ycc-0.2V

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

179

HM6787H 8«i88---------------------------------------------------------------AC Test Conditions

Oul pul Load A

Input pulse levels: Vss to 3.0V
Input rise and fall times: 4ns
Input timing reference levels: 1.5V
Output reference levels: 1.5V
Output load: See Figure

Oul put Load B

+5V

(for

1HZ. ILZ. IWZ

&

lOW)

+5V
4800

4800

DoUlo--....- -..

2550

30ph

Doulo--....- -...

2550

• Including lOop. and ilg.

Capacitance (Ta = 2S o C,f= l.OMHz)
Conditions

Symbol

max.

Unit

Input Capacitance

CIN

6.0

pF

VIN= OV

Output Capacitance

COUT

10.0

pF

VOUT=OV

Item

Note) This parameter is sampled and not 100% tested.

AC Characteristics (VCC = SVtlO%, Ta = O°C to 70°C, unless otherwise noted.)
Read Cycle
Item
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Selection to Output in Low Z
Chip Deselection to Output in High Z

Symbol

tRC
tAA
tACS
tOH
tLZ
tHZ

HM6787H-15
max.
min.
15
15
15
3
3
0
6

HM6787H-20
min.
max.
20
20
20
3
3
8
0

".

Unit

Notes

ns
os

ns
ns
ns
ns

1,2
1,2

Note: 1. This parameter is sampled and 100% tested.
2. Transition is measured t200mV from steady state voltage with specified loading in Load B.

Write Cycle
Item
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in Hish Z
Output Active from End of Write

HM6787H-15
max.
min.
15
10
10
0
10
3
12
0
0
6

Symbol

twc
tcw
tAW
tAS
twp
tWR
tDW
tDH
twz
tow

0

HM6787H-20
min.
max.
20
15
15
0
15
3
15
0
0
8
0

Unit

Notes

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

2

Note: 1. If~ goes hish simultaneously with WE high, the output remains in a high impedance state.
2. AU Write Cycle timings are referenced from the last valid address to the first transitloning address.
3. Transition is measured t200mV from steady state voltage with specified loading in Load B.
4. This parameter is sampled and not 100% tested.

•
180

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

3,4
3,4

----------------------------------------------------------------HM6787H S.ies
Timing Waveform of Read Cycle No. 11 ).

2)

IRC

Address

IAA
IOH

Data Out

Data Valid

Pr.. ious Data Valid

Timing Waveform of Read Cycle No. 2 1 ).

3)

~---------------------------------------------------------------------------~

IRC

lACS

ILZ

D.ta Out

Hip Impedance

Hi Ih Impedance

Data Valid

Note: I. WE il hlah and CS illow for READ cycle.
2. Addresses valid prior to or coincident with CS transition low.
3. Transition is measured t200mV from steady state voltage with specified loading in Load B.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819· (415) 589-8300

181

HM6787H

Swies----------------------------------------------------------------

Timing Waveform of Write Cycle No.1 (WE Controlled)
Iwe

Addr ...

lew

lAW
lAS
Iwp

low

Data In

Data In Valid
IWl

Data Out

Data Undefined

High Impedance

Note: I. Transition is measured ±200mV from steady state voltage with specified loading in Load B.

Timing Waveform of Write Cycle No.2 (CS Controlled)
Iwe

Address

-

)(

)~
lAS
lew

~

}
lAW

IWR
Iwp

1// / / /

\. \. \. \. \. \. ~\.
low

'.'l

Data In

)\.

IOH

Data In Valid

~~
)1\.

IWl

Data Out

Data Undefined
High Impedance

Note: 1. Transition is measured :t200mV from steady state voltage with specified loading in Load B.

_HITACHI
182

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589-8300

HM6787HA Series- Preliminary
65536-Word x 1-Bit High Speed Static RAM
• FEATURES
• Super Fast
Access Time ........................ .12/15/20ns (max.)
• Low Power Dissipation
(DC) Operating ..........................300mW (typ.)
• + 5V Single Supply
• Completely Static Memory
No Clock or Timing Strobe Required
• Fully TTL Compatible Input and Output

(DP-22NB)

• ORDERING INFORMATION
Access Time

Package

HM6787HAP-12
HM6787HAP-15
HM6787HAP-20

Type No.

l2ns
l5ns
20ns

300 mil 22 pin
Plastic DIP
(DP-22NB)

HM6787HAJP-12
HM6787HAJP-15
HM6787HAJP-20

l2ns
l5ns
20ns

300 mil 24 pin
Plastic SOJ
(CP-24D)

• BLOCK DIAGRAM

A80---.,::;.:~J

A70----t:i:l

Aso----D:l
AS 0 - - - " : : ; '

(CP-24D)

• PIN ARRANGEMENT
HM6787HAP Series

Ao
A1
A2
A3
A4
As

Vee

A11
A10
Ag
As

Row

Memory Matrix

NC

Decoder

256x1024

Ae
A7

A40---.,::;.'--J
A3o---~::J

A2o---~CL_---.J

A1S
A14
A13
A12
NC

Dout
L--..,-_ _ _ _ _- , - - '

WE

Din

Vss

CS
(Top View)
HM6787HAJP Series

vee

Ao
A1
A2
A3
A4
As

A1S
A14
A13
A12
NC

A11
A10
Ag
As

NC

Ae
A7
Dout
WE

Drn

Vss

CS
(Top View)

o

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

183

HM6787HA Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS
Symbol

Rating

Voltage on Any Pin Relative to V SS

VT

-0.5 to +7.0

V

Power Dissipation
Operating Temperature Range

PT

1.0

o to +70

Storage Temperature Range

Top,
Tstg

W
°C

-55 to + 125

°C

Temperature Under Bias

Tbias

-10 to +S5

°C

Item

• RECOMMENDED DC OPERATING CONDITIONS (O°C
Item

s Ta

Unit

S 70°C)

Symbol

Min.

Typ.

Max.

Unit

Vee

4.5

5.0

5.5

V

0.0

0.0

V

Input High Voltage

Vss
VIH

0.0

-

6.0

V

Input Low Voltage

V IL

2.2
-3.0·

-

O.S

V

Supply Voltage

·Pulse width" IOns, DC: -0.5V

• TRUTH TABLE
CS

WE

Mode

Vee Current

Output Pin

H

X

Not Selected

ISB,IsB!

L

H

Read

Icc, ICC!

HighZ
Data Out

L

L

Write

Icc, IcC!

High Z

• DC AND OPERATING CHARACTERISTICS (Vce = 5V ± 10%, Ta
Item

= O°C to 70°C, Vss = OV)

Symbol

Test Condition

Min.

Typ.

Max.

Unit

Input Leakage Current

Ilui

2

p.A

IILOI

-

-

Output Leakage Current

-

10

p.A

Operating Power Supply Current

Icc

-

rnA

Icc!

120

rnA

-

-

100

Average Operating Current

= 5.5V, VIN = Vss to Vec
CS = VIH , VOUT = Vss to Vce
CS = V1L , lOUT = OrnA
Min. Cycle Duty: 100%, lOUT = OrnA
CS = VIH

30

rnA

-

-

10

rnA

-

-

0.4

V

-

V

ISB
Standby Power Supply Current
ISBl
Output Low Voltage

VOL
VOH

Output High Voltage

Vee

CS 2! Vee - 0.2V
V IN s 0.2Vor VIN 2! Vee - 0.2V
IOL
IOH

= SmA
= -4mA

-

2.4

• AC TEST CONDITIONS
• Input Pulse Levels: Vss to 3.0V
• Input Timing Reference Levels: 1.5V
• Output Load: See Figure

• Input Rise and Fall Times: 4ns
• Output Reference Levels: 1.5V

+5V

+5V

4800

Dout

4800

Dout

2550

2550

5 pF *

Output Load B

(for tHZ , tLZ , twz & low)

Output Load A
'Including scope and jig capacitance.

•
184

HITACHI

Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005·1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6787HA Series
• CAPACITANCE (Ta

= 25°C, f = 1.0MHz)

Item

Symbol

Max.

Unit

C IN

6.0

pF

V IN

C OUT

10.0

pF

VOUT

Input Capacitance
Output Capacitance
NOTE:

Conditions

= OV
= OV

This parameter is sampled and not 100% tested .

• AC CHARACTERISTICS (Vcc = 5V ± 10%, Ta to O°C to 70°C, unless otherwise noted.)
• Read Cycle
Item
Read Cycle Time

Symbol

HM6787HA-12 HM6787HA-15 HM6787HA-20
Min.

Max.

Min.

Unit

Notes

20

-

ns

-

-

20

ns

-

20

ns

-

4

-

ns

-

5

-

-

ns

1,2

6

0

6

4
5
0

8

ns

1,2

Unit

Notes

tAA

12

15
-

Chip Select Access Time

tACS

-

12

-

Output Hold from Address Change

tOH

-

Chip Selection to Output in Low Z

tLz

4
3

Chip Deselection to Output in High Z

tHZ

0

NOTES:

Max.

IS
IS
-

-

tRC

Min.

-

12
-

Address Access Time

Max.

1. This parameter is sampled and not 100% tested.
2. Transition is measured ±2oomV from steady state voltage with specified loading in Load B.

• Write Cycle
Item

Symbol

HM6787HA-12 HM6787HA-15 HM6787HA-20
Min.

Max.

Min.

Max.

Min.

Max.

Write Cycle Time

twc

12

-

15

-

20

-

ns

2

Chip Selection to End of Write

lew
tAW

8

-

10

-

-

-

10

-

-

ns
ns

-

8

15
15

-

0

-

ns

-

8

-

10

-

0

Write Pulse Width

tAS
twp

0

15

-

ns

-

Write Recovery Time

tWR

0

0

-

0

-

ns

-

Data Valid to End of Write
Data Hold Time

tDW

7

8

-

10

-

0

0

-

0

Write Enable to Output in High Z

twz

0

0

6

0

8

ns
ns

-

tDH

ns

Output Active from End of Write

tow

3

6
-

3

-

3

-

3,4
3,4

Address Valid to End of Write
Address Setup Time

NOTES:

ns

-

-

I. If CS goes high simultaneously with WE high, the output remains in a high impedance state.
2. All write cycle timings are referenced from the last valid address to the first transitioning address.
3. Transition is measured ± 200m V from steady state voltage with specified loading in Load B.
4. This parameter is sampled and not 100% tested .

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

185

HM6787HA Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORM
• Read Cycle (1) (1) (2)

Address
tOH

Data Out

Data Valid

Previous Data Valid

• Read Cycle (2) (1) (3)

tRC

cs

~

"

//
tACS
tLZ

tHZ

Data Out
High Impedence

C'IXIXIJK

Data Valid

"/
High

Impedence

NOTES:

I. WE is high and CS is low for READ cycle.
2. Addresses valid prior to or coincident with CS transition low.
3. Transition is measured ±200mV from steady state voltage with specified loading in Load B.

$
186

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6787HA Series
• Write Cycle (1) (WE Controlled)

twc

)K

Address

)
tew

"-""-"-"--~ ~

~

cs

/

"

.,~////////////~
tAW
tAS

tWA
twp

WE

/~

~~ ~

tOH

tow
Data In

I
Data Out

NOTE:

Data In Valid
twz

"I

Data Undefined

I

)/

"

tow

1.1

/1 Hi himpe dane 1'\
e
9

I. Transition is measured ±200mV from steady state voltage with specified loading in Load B.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

187

HM6787HASenes---------------------------------------------------• WrHe Cycle (2) (CS Controlled)
twc
Address
tcw

cs

twp

WE
tow

Data In Valid
twz

Data In
Data Out

NOTE:

~)to------------High Impedance

Data Undefined
----------------'

I. Transition is measured :l:200mV from steady state voltage with specified loading in Load B.

•
188

HITACHI

Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM62256 S e r i e s - - - - - - - 32768-word x 8-bit High Speed CMOS Static RAM
• FEATURES
•
•

•
•
•
•

High Speed: Fast Access Time 85/1oo/120/150n5 (max.)
Low Power Standby and Low Power Operation;
Standby: 200~W (typ)/10~W (typ) (L-version),
Operation: 40mW (typ.) (f= 1MHz)
Single 5V Supply
Completely Static RAM: No clock or Timing Strobe Required
Equal Access and Cycle Time
Common Data Input and Output, Three-state Output
Directly TTL Compatible: All Input and Output
Capability of Battery Back Up Operation (L-/L-SL version)

•

ORDERING INFORMATION

•
•

Type No.

Access Time

HM62256P-8
HM62256P-IO
HM62256P-12
HM62256P-15

85ns
lOOns
120ns
lS0ns

HM622S6LP-8
HM622S6LP-IO
HM622S6LP-12
HM62256LP-15

8Sns
lOOns
120ns
150ns

HM62256LP-10SL
HM622S6LP-12SL
HM622S6LP-1SSL

lOOns
120ns
lS0ns

HM622S6FP-8T
HM62256FP-10T
HM622S6FP-12T
HM622S6FP-15T

8Sns
lOOns
120ns
150ns

HM622S6LFP-8T
HM62256LFP-10T
HM622S6LFP-12T
HM622S6LFP-IST

8Sns
lOOns
120ns
lS0ns

HM62256LFP-10SLT
HM622S6LFP-12SLT
HM62256LFP-1SSLT

lOOns
120ns
150ns

HM62256P Series

(DP-28)
HM62256FP Series

Package

600mi128pin
Plastic DIP

(FP-28DA)

• PIN ARRANGEMENT

28 pin
Plastic SOP

• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Rating

Unit

VT

-

-

-

ns

-

ns

p.A

Note) *1. tRC =Read Cycle Time
*2. This characteristic is guaranteed only for L-version, 20p.A max. at T" = 0 to 40·C.
*3. This characteristic is guaranteed only for L-SL version, 3p.A max. at T" = 0 to 40·C.

•

Low Vee Deta Retantion Waveform

DATA RETENTION MODE

Vee

2.2V-----VDR

cs~

CS-_J
Note)

VDR~2.0V

Vee-O.2V

OV------------------------------------------------------------

In Data Retention Mode, CS" controls the Address,WE, M, and Din Buffers. Yin for these inputs can be in
high impedance state in data retention mode.

_HITACHI
Hitachi America, Ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

193

HM82258 Seri.. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SUPPLY CURRENT vs. AMBI ENT TEMPERATURE 111

SUPPLY CURRENT vs. SUPPL Y VOLTAGE 111

1. 6

1.6

Ta=25"C

1
~

Vcc =5.o.V
4

1.4

L

1.2

~

0.

8

V LV

2

L

-

o.r----

8

o..6

r--- t--

o.. 6

0..4 4.50.

4.75

o.. 4 0.

550

5.25

5.00

20.

40.

SUPPLY CURRENT vs. SUPPL Y VOLTAGE (21

SUPPLY CURRENT vs. AMBIENT TEMPERATURE (21
1.3

1.6

Vcc =5.o.V

Ta=25'C

2

j
-"

j

80

60

Ambient Temperature Ta (·C J

Supply Voltage Vee (V)

1.0.

0. .8~

~

V-

----

1

~

]
i

'"

.6

4
0. 4.50

4.75

5.00

5.50

5.25

-

1. 0.

0..9

0..8

0. 7 0.

Supply Voltale Vee (V)

SUPPLY CURRENT vs. SUPPLY VOLTAGE 131

60
20.
40.
Ambient Temperature To (·C)

SUPPLY CURRENT VI. AMBIENT TEMPERATURE (31

1.6

1. 3

Ta=25"C

Vcc=5.0V

2

1.4

1
"li
~

1. 2

~
G

~

!

u

j

1.0.

0.

81""""'"

L

~

~

V

L

1

0.1---

9

--

-

0..8

0.6

0..4 4.50

4.75

5.00

5.25

5.50

0. 7

Supply Voltase Vee (V)

•
194

80

60
20
40.
Ambient Temperature To ("C)

HITACHI

Hitachi America, ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

80

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 2 5 6 Series
ACCESS TIME VI. SUPPLY VOLTAGE

ACCESS TIME

VI.

AMBIENT TEMPERATURE

1.3

1.3

Ta- 25"C

Vee = S.OV

1.2

1.2

...

,.§

-E

--- ---r---..

1.1

r---..

1.0

;:
~

I

0.9

-<

0

4.50

5.25

5.00

4.75

Supply Voltage V«

STANDBY CURRENT

VI.

O.7

5.50

20

IV)

SUPPLY VOLTAGE

/

STANDBY CURRENT

8

/

6

AMBIENT TEMPERATURE

4

~

V

/

1
z

I

.

V

/

L
V'

,

JO"

SUPPLY CURRENT

o

VI.

20

40

60

To.

Ambient Temperature

FREQUENCY {READ)

SUPPLY CURRENT

VI.

80

(T)

FREQUENCY {WRITE)

1. 2

1. 2

15On,

i2On,

1. 0

/'

j o. 6
o. 4

~

]

~

/

V

Z

J

TF25"C
Vee

=

10

1 o.

/'

/

\50., IkOn,

l06ns 85ns

V
./

8

'" o. 2

V

V

TF25'C

Supply V oltage Vee (V)

1 o.

-=s.ov

11

o.2 2

~
c3

VI.

80

Vee

II

0

~

60

To. ('C)

0

2

]

40

Ambient Temperature

1. 4

O.

V

/
V'

/

O. 8

0.8

07

L

O.9

j

/'

8

/

o. 6

/

c

5.0V

~

<3 o. 4
.2

V

10

Ta=2S'C

/V
10

12

Frequency f (MHz)

Frequency

•

V
Vee =S.OV

0

0

L

lo6ns 85ns

J

12

(MHz)

HITACHI

Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

195

HM62256 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INPUT LOW VOLTAGEvs.SUPPLY VOLTAGE

INPUT HIGH VOLTAGE VS.
SUPPL Y VOLT AG E

13

1. 3

Ta 2S'C
]

12

~
Z

.

1. 1

;;

10

E

~

"0

;,...

O,g

j

Ta

-- -r--

1

~

1
;
~

O. 7450

475

5.00

1

I

09

V--

4.50

VI

OUTPUT CURRENT
OUTPUT VOLTAGE

% 1.4

4

\

8

2

\

O. 6

C 1.0
~

Ta::,2S'C
V(c S,QV

o
j

\

o.8

~

6 o.6

\

o. 4

O. 4
Output High Voltage

ACCESS TIME

VI.

V(IH

525

550

VI.

J

\

~

o

5.00

OUTPUT CURRENT
OUTPUT VOLTAGE

VI.

1. 6

0

475

Supply Voltafl:(' Vu . \'

1.6

1. 2

-----

08

0.7

5.50

5.25

Supply Voltage Vee

1.0

:i:

8

1
z

J
02

/

/

/

/
Ta- 2S'C
Vcc --5.0V

0.4

0.6

Output Low Voltage VOl i V

(V)

I

LOAD CAPACITANCE

1.8

1.6

]

1
z

------

1.4

0

8

O.6

100

200

300

.--::-::

500

400

Load Capacitance C L (pF)

•
196

25'C

2

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

0.8

HM62832/HM62832H
8-Bit CMOS Static RAM
32768-WORD x a·BIT HIGH SPEED CMOS ST~TIC RAM
• FEATURES
• High speed: Fast Access time 25/35/45 ns (max.)

HM82832-Low power
Standby: 10 p.W (typical) (L-version)
Active: 300 mW (typical)

HM82832H-Low power

(DP-28NA)

Standby: 300 mW (typical)
Active: 30 p.W (typical) (L-version)
• Single 5V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output-Three stage output
• Direc1ly TTL compatible-All inputs and outputs

(CP-28DN)

• ORDERING INFORMATION
Part No.

Access

PIN ARRANGEMENT
Package
Top View

HM62832P-35
HM62832P-45

35 ns
45 ns

HM62832LP-35
HM62832LP-45

35 ns
45 ns

HM62832JP-35
HM62832JP-45

35 ns
45 ns

HM62832UP-35
HM62832UP-45

35 ns
45 ns

HM62832HP-25
HM62832HP-35
HM62832HP-45

25 ns
35 ns
45 ns

300 mil 28-pin
Plastic DIP
(DP-28NA)

HM62832HJP-25
HM62832HJP-35
HM62832HJP-45

25 ns
35 ns
45 ns

300 mil 28-pin
Plastic SOl
(CP-28DN)

300 mil 28-pin
Plastic DIP

300 mil 28-pin
Plastic SOl

A14

Vee

A12

WE

A7
A6

A'3

As

Ag

A4
A3
A2

All

AI

CS

AI)

1/07

1100
110,
1102

1106
1/05
1104
1103

As

OE

A10

VSS

• PIN DESCRIPTION
Pin Name
Ao-A'4

•

Function
Address

1100 -1/07

Input/Output

CS

Chip Select

WE

Write Enable

OE

Output Enable

Vee

Power Supply

Vss

Ground

HITACHI

Hitachi America, Ltd .• H~achi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

197

HM628321HM62832H - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• BLOCK DIAGRAM

Memory Array

A12
A14
All
A13

I

A9
All

I Address
Buffer

Row
Decoder

X

AS
All
A7

5l2X5l2

VOO - - - - - - I

Column 110

1107

WE
OE

AD Al A2 A3 Al0 A3 A4

CS

• ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Voltage on any Pm Relative to VSS

Item

VT

-0.5*1 to + 7.0

V

Power Dissipation

PT

1.0

W

Unit

Operating Temperature

Topr

o to +70

°C

Storage Temperature

T~tg

-55 to +125

°C

Storage Temperature Under Bias

Tblas

-10 to +85

°C

NOTE:

1 -2 S V for pulse Width

~

10 n~

• FUNCTION TABLE
CS

OE

WE

Mode

Vee Current

1/0 Pm

H

X

X

• Not Selected

ISB.IsBI

HigbZ

L

L

H

Read

Icc

D out

Read Cycle(l) 10 (3)

L

H

L

Icc

Dm

Wnte Cycle(1)

L

L

L

Icc

Dm

Write Cycle(2)

NOTE:

Write

I X HorL

•
198

Ref. Cycle

HITACHI

Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

---------------------------------------------------------------HM6~~HM6~2H

• DC CHARACTERISTICS for HM62832 (TA = 0 to +70·C, Vee = 5V ± 10%, Vss = OV)
Symbol

Min.

Typ.*1

Max.

Unit

Input Leakage Current

Ilul

-

-

10

p.A

Yin = Vss 10 Vee

Output Leakage Current

IILOI

-

-

10

p.A

CS = VlHorOE = VIH
or WE = VIL '
VI/O=VSSIOVcc

Average Operating Power
Supply Current

Icc

-

60

120

mA

Min. cycle, duty
CS = VIL,
luo=OmA

IS8

-

15

30

mA

CS = VIH

1881

-

2

100

p.A

oV :s Yin :s 0.2 V,

Parameter

Test Conditions

CS

Standby VCC Current

~

OrVin,
Output \bltage
NOTE:

VOL

-

VOH

2.4

-

= 100%,

Vcc - 0.2V,
~

L-version

V",,-0.2V

0.4

V

IoL=8mA

-

V

IoH =-4mA

I Typoc:alvalues an: II Vee = 5.0 V. TA = +2S·C and spe<:ifoed loadon,.

• DC CHARACTERISTICS for HM62832H (TA = 0 to + 70·C, Vee = 5V

:i:

10%, Vss = OV)

Symbol

Min.

Typ.*1

Max.

Unit

Input Leakage Current

lIul

-

-

2

p.A

Von = Vss 10 Vcc

Output Leakage Current

IILOI

-

-

2

,.A

CS = VIHorOE = VIH
or WE = VIL,
Vl/o=Vss lOVee

Operating Power Supply Current

Icc

-

60

120

mA

Min. cycle, duty
CS = VIL,
luo=OmA

Standby Power Supply Current

IS8

-

15

30

mA

CS = VIH

-

0.02

2

mA

Cs l!:

-

0.006

0.1

mA

Parameter

Standby Power Supply Current

Output \bltage
NOTE:

Note

1881

Test Conditions

= 100%,

Vee - 0.2V,

o V :s V.. :s 0.2 V,
or V..,

~

L-version

VIX - 0.2 V

VOL

-

-

0.4

V

IoL=8mA

VOH

2.4

-

-

V

10H =-4mA

I TypICal values are at Vee - S 0 V, TA =

Note

+2SoC and specified loacbng.

• CAPACITANCE (Ta = 25·C, f = IMHz)
Parameter

Symbol

Min.

Typ.

Max.

Unit

Input Capacitance

Con

-

-

6

pF

V.. =OV

Input/Output Capacitance

CliO

-

-

\0

pF

Vila =OV

NOTE:

Test Conditions

I. This parameter is sampled and not 100" tested.

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

199

HM62832/HM62832H - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• AC CHARACTERISTICS (Ta = 0 to +70°C, Vee = 5 V ± 10%, unless otherwise noted.)
Test Conditions
• Input and output timing reference levels: 1.5 V
• Output load: See Figures

• Input pulse levels: 0.0 V to 3.0 V
• Input rise and fall times: 5 ns

Output Load (8)

Output Load (A)

(for telz, toLZ' tcHZ, t OHZ' tWHZ

+5V

NOTE:

tow)

+5~80

~

n=i

Dout

255

&

Dout

480pF *
30

255

5 pF'

"Includmg scope & Jig

• Read Cycle
HM62832-35
HM62832H-35

HM62832H-25
Parameter

Symbol
Mm.

Max.

Mm.

HM62832-45
HM62832H-45

Max.

Min.

Unit

Max.

Read Cycle Time

tRC

25

-

35

-

45

-

ns

Address Access Time

tAA

-

25

-

35

-

45

ns

Chip Select Access Time

tACS

-

25

-

35

-

45

ns

tOE

-

12

-

15

-

20

ns

Output Hold From Address Change

tOH

5

-

5

-

5

-

ns

Chip Selection to Output m Low-Z

tCLZ

5

-

5

-

5

-

ns

Output Enable to Output m Low-Z

toLZ

0

-

0

-

0

-

ns

Chip Deselectlon to Output in Hlgh-Z

tCHZ

0

12

0

15

0

15

ns

Output Disable to Output in High-Z

tOHZ

0

12

0

15

0

15

ns

Output Enable to Output Vahd

Read Cycle Timing (2) "1, "2, "4

Read Cycle Timing (1)"1

Address

~~=====~

Read Cycle Timing (3) "1, "3, "4

-)~~::;--{I-----"~"'----1
Dout~~---D-~-av-al-td-----~

cs
Dout

NOTES:

*1 WE

IS

*2 Device

high for read cycle
IS

contmuously selected.

CS ==

VIL

*3 Address should be valid prior to or cOinCident with
*4

OE =

VTL

~HITACHI
200

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300

CS tranSition low

------------------------------------------------------------------HM6283~HM62832H

• Write Cycle
HM62832H-25
Item

Symbol

HM62832-35
HM62832H-35

HM62832-45
HM62832H-45

Unit

Min.

Max.

Min.

Max.

Min.

Max.

-

ns

ns

Write Cycle Time

twe

25

-

35

-

45

Chip Selection to End of Write

lew

20

-

30

-

40

Address Valid to End of Write

tAW

20

-

30

40

Address Setup Time

tAS.

0

-

0

-

Write Pulse Width

twp

15

-

25

tWR

0

-

20

Write Recovery Time

0

-

0

-

Write to Output in High-Z

tWHz

0

15

0

15

0

20

ns

Data to Write Time Overlap

tow

12

15

tOH

0

-

ns

0

-

20

0

-

10HZ

0

12

0

15

0

20

ns

tow

5

-

5

-

5

-

ns

Data Hold from Write Time
Output Disable to Output in High-Z
Output Active From End of Write

0

ns
ns

ns
ns

ns

Write Cycle Timing (1) (OE Clock)
Address

)I(

0

0.""

....

l'-~

~

~
,"\..."\..."\..."\..."\..."'l////~

'"

"1.."\...,"\...'1\.

~

Dou.

)l(XX

)K

Din

Write Cycle Timing (2) (OE Low Fixed)
Address
lew

twR 2

.....
Dou.
D.n
NOTES:

*1 A wrue occurs durmg tbe overlap (twp) of a low CS and a low WE
*2. IWR IS measured from the earher of Cs or WE gomg high to the end of wnte cycle

*3 Durmg thiS penod. I/O pms are

In

the output state The mput signals out of phase must not be apphed

*4 lfthe Cs low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remam

*5.

5E IS contmuously low (OE =

*6. Doul IS

In

In

a high Impedance state

Vll)

the same phase of wntten data of thiS Write cycle

*7 D0lI1 is the read data of next address
*8

IfCS IS low dunng this period, 110 pans are m the output state

The mput signals out of phase must not be applied to 110 pins.

·9. WE must be high during all address tranSItions except when deVice IS deselected With CS

~HITACHI
Hitachi America, Ltd. • Hilachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

201

HM62832/HM62832H - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• Low Vee Data Retention Characteristics (TA = 0 to +70°C)
This characteristics is guaranteed only for L-version
Parameter

Symbol

Min.

Typ.

Max.

Unit

Vee for Data Retention

VOR

2.0

-

-

V

Data Retention Current

IeeoR

-

I

50'2

p.A

!cOR

0

-

-

ns

IRe

IRe 'I

-

-

ns

Chip Deselect to Data Retention Time
Operation Recovery Time
NOTES:

Test Conditions

CS '" Vee - 0.2 V,
Vin ' " Vee-0.2Vor
o V " Vin " 0.2 V

"'I tRe = read cycle time
*2 Vee == 30V

Low Vee Data Retention Timing Waveform
Data retention mode

V~45V----:ff--~~---------------~------'" ::::: ::::_ ~===============I=--f:==~=====:

OS ~R

___________e~~'i:Q._=~2y_________________ _

• PACKAGE DIMENSIONS Unit: mm (inch)
HM62832HP Series
(DP-28NA)
HM62832P/HP

HM62832HJP Series
(CP-28DN)
HM62832JP/HJP

4:;::<:
~!j
~~ !r!--"!i
1_- '

~--#--

048±O f
(OOI9±OOO4,

ZSH025

"'" ...

~

s

(OIOO±OOlO)

~HITACHI
202

HitachI America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300

HM6208/HM6208H Series
4-Bit CMOS Static RAM
65536-Word x 4-BIt High Speed CMOS Static RAM
The Hitachi HM6208 and HM6208H are high speed 256k static
RAMS organized as 64k-word x 4 bit. They realize high speed
access time (25/35/45 ns) and low power consumption, employing
CMOS process technology and high speed circuit designing
technology. It is most advantageous wherever high speed and high
density memory is required, such as the cache memory for main
frame or 32-bit MPU.
The HM6208 and HM6208H are packaged in the industry
standard 300-mil, 24 pin, plastic DIP. The HM6208H is also
available in a 300-mil, 24 pin, plastic SOJ package for high density
mounting. The low power versions are ideal for battery backed
systems.

(DP-24NC)

Features
• Single 5 V supply and high density 24-pin package
• High speed:
Access time 25/35/45 ns (max.)
• Low power
300 mW (typ.)
Active:
Standby:
100 JLW (typ.)
30 JLW (typ.) (L-version)
• Completely static operation requires
No clock or timing strobe
• Access and cycle times are equivalent
• All inputs and outputs TTL compatible
• Capability of battery back up operation (L-verslon)

(CP-24D)

Pin Arrangement

AO

U

1

Ordering Information

AI4

Access Time
35 ns
45 ns
35 ns
45 ns
25 ns
35 ns
25 ns
35 ns
25 ns
35 ns
25 ns
35 ns

Type No.
HM6208P-35
HM6208P-45
HM6208LP-35
HM6208LP-45
HM6208HP-25
HM6208HP-35
HM6208HLP-25
HM6208HLP-35
HM6208HJP-25
HM6208HJP-35
HM6208HUP-25
HM6208HUP-35

Vee
AI5

Package

300-md
24-pin
plastic DIP
(DP-24NC)

300-md
24-pin
plastic SOJ
(CP-24D)

(fop View)

Pin Description
Pin Name
AO-AI5

Function
Address

1/01- 1/04

Input/Output
Chip select
Write enable

CS
WE
Vee

Power supply

Vss

Ground

$

HITACHI

Hitachi America, Ltd. • Hitachi Plm • 2000 Sierra Point Pkwy. • 8risbane, CA 94005-1819 • (415) 589-8300

203

HM6208/HM6208H Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Block Diagram
AI4~~==r-----~~------------_.
-Vee

AI50--D=~

AO
Al

--v,.

e>-Dc:::::::I
G-Dc:::::::I

Row

Memory Array

Decoder

A2 o--D=~
A30--o=:::1

256 x 1,024

A4 O--D=::::l

A5

o---1~==L

__J
Input

Da..
Control

C5

WE

Function Table

CS

WE

H
L
L

X

Note:

H
L

Mode
Not selected
Read
Write

Vee Current
ISB,ISR!
Icc
Icc

I/O Pin
High-Z
Dout
Din

Ref. Cycle
Read cycle
Write cycle

x means don't care.

Absolute Maximum Ratings
Item
Voltage on any pin relative to Vss
Power dissipation

Symbol
Vin
PT

Value
-0.5'! to +7.0
1.0
o to +70
_~~~-a-t-in~g~t-em~pe~r-a-ru-r~e-r-an~g~e----------.To~
Storage temperarure range
Tstg
-55 to +125
-10_to_+85
~-S-to-r...:ag"'-e-te-m-'p-e-ra-n-!-re-r-a-n"ge-un-d-c-r-b-i_as_ _ _ _ _ Tbias._ _ _ _ _ _ _
_ __
Note: .\'
Vin min = -2.5 V for pulse width S \0 ns.

Unit
V
W
°C
°C
°C

~HITACHI
204

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6208/HM6208H Series

Recommended DC Operating Conditions (Ta = 0 to +70°C)
Item
Supply voltage
Input high (logic \) voltage
Input low (logic 0) voltage
Note:

•

Min
4.5
0

Symbol
Vee
Vss
VIH
VIL

--------

Max
5.5
0
6.0
0.8

Typ
5.0
0

2.2
_0.5'1

Unit
V
V
V
V

"I. VIL mm = -2.0 V for pulse WIdth S 10 os .

DC Characteristics

(Ta

= 0 (0 + 70'C, VCC = 5 V

Input Leakage Current
Output Leakage Current

± 10%. V ss

Min

Symbol

Item

= 0 V)
Mdx

Typ"

Tc.." Condition-.

UnIt

III

-

-

20

~A

lLO

-

-

100

~A

Vce = Max
Yin = v~\ to Vec
CS = V IH

--

V I/O = V..,.., to VeT

0 mA.
Min Cycle, Duty = 100%
- - - - ---

CS = V IL . 1110 =

Operating Power Supply Current

Icc

-

60

100

mA

Standby Power Supply Current

ISB

-

15

30

mA

Standby Power Supply Current "H" VCP"lon

ISB

-

20

40

rnA

Standby Power Supply Current

ISSl

-

20

2000

~A

Standby Power Supply Current L- Vcn.,lon

I sBr

-

6

100

~A

Output Low Voltage

VOL

--

-

04

V

10L = 8 rnA

Output High Voltage

VOH

24

-

-

V

IOH = -4 0 mA

Note

*1

Typlcallmllt~

arc at Vee

= 50 V, T" =

+25°C and

~pcClrlcd

Cs

= V 1H . Mm Cycle

CS '" Vec - 0 2 V
:s: Vm :s 0 2 V or

oV

Vm~V(C-02V

loading

Capacitance (Ta =25°C. f = 1MHz)'1
Symbol
Cin
ClIO

Item
Input capacitance
Input/output capacitance
Note:

Test Conditions
Vin=O V
vvo =-O:c-V:c:-----

Min

*1. This parametens sampled and not 100% tested.

AC Characteristics (Ta = 0 to +70°C. Vee = 5 V ± 10%. unless otherwise noted.)
Test Conditions
Input and output timing reference levels: 1.5 V
Output load: See Figures

Input pulse levels: Vss to 3.0 V
Input rise and fall times: 5 ns

Output Load CA)

Output Load (B)
(for 0/7" tLZ, twz & tow)

>IV

Do.,

~
2550

Note:

* Including scope &

..oo

Do.,
lOpY.

~
2550

..oo

5pF.

Jig.

•

HITACHI

Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

205

HM6208/HM6208H Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Read Cycle

HM6208-35
HM6208H-35

HM6208H-25

Symbol

Item

Min.

Max.

Min.

HM6208-45

Max.

Min.

Unit

Max.

Read Cycle Time

tRC

25

-

35

-

45

-

ns

Address Access Time

tAA

-

25

35

ns

tACS

-

25

-

45

Chip Select Access Time

-

45

ns

Output Hold From Address Change

toH

5

5

5

5

5

-

ns

tLZ"

-

5

Chip Selection to Output in Low-Z

-

Chip Deselection to Output in High-Z

tHZ"

0

12

0

20

0

20

ns

Chip Selection to Power Up Time

tpu

0

-

0

-

0

-

ns

Chip Deselection to Power Down Time

tpD

-

15

-

25

-

30

ns

Note:

35

*1 Transition is measured ±200 mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested.

Read Timing Waveform (1) '1,'2
t"

Address

t ••

Data V.ltd

D..,

Read Timing Waveform (2) '1,'3

1\

D..,

L
----+--------

"

____

2 ~4 '025
(0100' 0010)

~~t

00

9

fE\

~" O.~

:1 e

~,~

,

060(0 024)

~

-ll.--

(OO\O-~\U~)

I)

[qo

1010004)

S(ATING PLANE I

"

JL-

o 43:tO
o OI1±O

]~r::; m~
; +1 +1

,

o l,)~'!.~~

_

-I .. r(O 081~~ ::~)

p

762
(0300)

I

•
210

.. lO~~ :~
IS&3(o6IS)

13(0 051)

I :;

,

10

14(0 0291

"

Or

~I~

"- ~wJ~~

004'

HITACHI

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM6708 S e r i e s - - - - - - - 65536·word x 4·bit High Speed Hi·BiCMOS Static RAM
Features

•
•
•
•
•
•

HM6708P

Super Fast Access Time: 20/25ns (max.)
Low Power Dissipation
Operating: 350mW (tyP.) (f = 50MHz)
+5V Single Supply
Completely Static Memory
No Clock or Timing Strobe Required
Balanced Read and Write Cycle Time
Fully TTL Compatible Input and Output
(DP·24NC)
HM6708JP

Ordering Information
Access Time

Package

HM6708p·20
HM6708p·25

Type No.

20ns
25ns

300mil24 pin
Plastic DIP

HM6708JP-20
HM6708JP·25

20ns
25ns

300 mil
24 pin SOJ

(CP-24D)

Block Diagram

Vee

Ao
Al

Pin Arrangement

---0

A2
A3 ~--, ..-L.1

A4

Memory Matrix

Vss

Vee

256X 1024

A is

As

Ag

AI4

Alo <>---1:::0

AI3

110 1 ~~~~==~ ~==C=o=lu=m=n=I/=O==c'..-1102
1103

AI2

AII
AIO

110 1
1102
1103
110 4
WE

1/04

(Top View)

Note}

The specifications of this device are subject to change without notice.
Please contact Hitachi's Sales Dept. regarding specifications.

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

211

HM6708 Sari..

Absolute Maximum Ratings
Item

Symbol

Terminal Voltage to Vss Pin

Rating

Unit

VT

-0.5 to +7.0

Power Dissipation

PT

1.0

W

Operating Temperature Range

Topr

o to +70

·C

Storage Temperature Range (with bias) T.t,(blu)
Storage Temperature Range

T,t,

V

-10 to +S5

·C

-55 to +125

·C

Recommended DC Operating Conditions (Ta = 0 to +70°C)
Symbol

Item
Supply Voltage

Input Voltage
Note)

min.

typo

max.

Unit

Vee

4.5

5.0

5.5

V

VSS

0

0

0

V

VIH

2.2

6.0

V

VIL

-0.5*1

O.S

V

*1. -3.0 V for pulse width 20ns.

Function Tabla
~

WE

H

X

L
L

Mode

I/O Pin

Vee Current

Ref. Cycle

Not selected

ISB.lsBI

HlghZ

H

Read

lee.leCI

Data OIt

Read Cycle

L

Write

Icc.ICCI

Data In

Write Cycle

DC and Oparatlng Charactart.tlcs (Vee = 5 V ±10%, Ta = 0 to +70°C)
Item
Input Leakage Current

Symbol

min.

typo

IILlI

max.

Unit

Test Conditions

2

pi.

VCC= 5.5V. VIN= Vssto Vee

~. VIH. VI/O = Vssto VCC

Output Leakage Current

11£0 1

10

pi.

Operating Power Supply Current

Icc

100

mA

CS • VIL.II/O = 0 mA

Average Operating Current

IcC!

120

mA

Min. Cycle. Duty: 100%.11/0=OmA

ISB

30

mA

CS· VIlI. VIN= VIlIor VIL

ISBI

10

mA

~~ Vcc-0.2V
VIN ~ 0.2 Vor VIN ~ Vcc-0.2V

V

10L· SmA

V

10H- -4 mA

Standby Power Supply Current
Output Low Voltage

VOL

Output High Voltage

VOH

0.4
2.4

•
212

HITACHI

Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 0 8 Series
Capacitance (Ta

=2SoC,f= 1 MHz)
Symbol

Item
Input Capacitance
Input/O utput Capacitance
Note)

max.

Unit

6.0

pF

VIN= 0 V

10.0

pF

VI/O=OV

Test Conditions

This parameter is sampled and not 100% tested_

AC Characteristics (Vee = S v ±lO%, Ta = 0 to +70°C, unless otherwise noted)
AC Test Conditions
•
•
•
•
•

Input pulse levels: Vss to 3.0 V
Input timing reference levels: 1.5 V
Output Load: See Figure
Input rise and fall times: 4 ns
Output reference levels: 1.5 V

Output

Output
255\2

255\2

Output Load A

• ineludin.
ICOpe and ii,

Output Load B
(for tHZ, tLZ, twz, & tow)

Read Cycle
Item
Read Cycle Time

Symbol
tRC

HM6708-20
min.
max.
20

HM6708-2S
min.
max.
2S

Unit

Notes

ns

Address Access Time
Chip Select Access Time
Output Hold from Address Change

tOH

5

5

ns

Chip Selection to Output in Low Z

tLz

0

0

ns

1,2

Chip Deselection to Output
in High Z

tHZ

0

ns

1,2

Note)

tAA

20

2S

tACS

20

2S

8

0

10

ns
ns

1. This parameter is sampled and not 100% tested.
2. Transition is measured ±200 mV from steady state voltage with specified loading in Load B.

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

213

HM6708Series------------------------------------------------------------

1 + - - - - - - tRC

----------+~I

Address

nata Out

------~-H~~----na-ta-Va-lid-~-H-~*==
1+------- tRC

..

--------i~ 1

1+----tACS----~~~1

Data Out

nata Valid

High Impedance

Notes) -I. ft Is High for Read cycle.
-2. Device is continuously selected, ~ =VII.-3. Address valid prior to or coincident with CS transition low.

Write Cycle
Item

Symbol

HM6708·20
min.
max.

HM6708·25
max.
min.

Unit

Notes
2

twe

20

25

Chip Selection to End of Write

tew

15

20

ns
ns

Address Valid to End of Write

tAW

15

20

ns

Address Setup Time

tAB

0

0

ns

Write Pulse Width

twp

15

20

ns

Write Recovery Time

tWit

3

3

ns

Data Valid to End of Write

tDW

12

15

ns

Data Hold Time

tDH

0

0

Write Enable to Output in High Z

twz

0

Output Active from End of Write

tow

0

Write Cycle Time

8

0

ns
10

0

ns

3,4

ns

3,4

Note) 1. If ~ goes high simultaneously with WE high, the output remains in a high impedance state.
2. All Write Cycie timings are referenced from the last valid address to the first transitioning address.
3. Transition is measured :t200 mV from steady state voltage with specified loading in Load B.
4. This parameter is sampled and not 100% tested •

•
214

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1B19 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6708 Series
Write Cycle-1 (WE Controlled)

1....- - - - - - -

twc - - - - - - - - - + 1

Address

Data In

High Impedance

Data Out

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

215

HM6708 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Write Cycle-2 ICS Controlled)

=t• -----------tA-W--::::::::::::~~-I~--tW--R-*--2~---------­
~twc-;k

Address

tAS~
- - - - - - - - - - ' " \ 1-4---

Data In

Data Out

Note)

tcw

-----l~~1

\7\1-;- tow -+"~11\7

--,r""7'\XXXXr-7r"1XXr-7r"7Xr-7r"1XXr"'7r7XXM
r7r7

Data Valid

M~XX~XX~XX

High Impedance *4

*1. A write occurs during the overlap of a low CS and a low WE. (twp)
*2. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
*3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs
must not be applied.
*4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the
output buffers remain in a high impedance state.
*5. If CS is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase
to the outputs must not be applied to them.
06. Output is the same phase of write data of this write cycle.

~HITACHI
216

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300

HM6708A

SerieS-Product Preview - - - - - - - - - -

65536-Word x 4-Bit High Speed Static RAM
• FEATURES
• Super Fast
Access Time ........................ 15/20/25ns (max.)
• Low Power Dissipation ...................... AOOmW (typ.)
• + 5V Single Supply
• Completely Static Memory
No Clock or Timing Strobe Required
• Fully TTL Compatible Input and Output

(DP-24NC)

• ORDERING INFORMATION
Type No.

Access Time

Package

HM6708AP-15
HM6708AP-20
HM6708AP-25

15ns
20ns
25ns

300 mi124 pin
Plastic DIP
(DP-24NC)

HM6708AJP-15
HM6708AJP-20
HM6708AJP-25

15ns
20ns
25ns

300 mil 24 pin
Plastic SOJ
(CP-24D)

(CP-24D)

• PIN ARRANGEMENT
• BLOCK DIAGRAM

Ao

A20-----I
A3 o----C::w

A4 o----C::w

A7 0----1~::w
As 0----1~::w
Ag 0----1~::w
As 0----1~::w
As

---0 Vee

A1

-oVss

A2

Memory Matrix
256 X 1024

A4
A5

o---~==~ :=::C==========~

110 1 0---.......-1

A3

Column I/O

1102 o--.-H-l~-1

A6
A7

As
As

o-~~-H~>--l

CS

1/04 o---.1H-tH>--l

Vss

1/03

'-----'

(Top View)

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra POint Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

217

HM6708A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS

Item
Terminal Voltage to Vss Pin
Power Dissipation
Operating Temperature Range
Storage Temperature Range (with bias)
Storage Temperature Range

Symbol
VT
PT

Rating
-0.5 to +7.0
1.0
Oto +70
-10 to +S5
-55 to +125

Toor

TSI2(bias)
TSl2

Unit
V
W
°C
°C
°C

• RECOMMENDED DC OPERATING CONDITIONS (O°C :s T. :s 70°C)

Item

Symbol
Vee
Vss
V1H
V1L

Supply Voltage
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
·Pulse width s I5ns. DC: -O.5V

Min.
4.5
0.0
2.2
-3.0·

Typ.
5.0
0.0

Max.
5.5
0.0
Vee + 0.5
O.S

-

-

Unit
V
V
V
V

• TRUTH TABLE

CS
H
L
L

WE
X
H
L

Mode
Not Selected
Read
Write

Vee Current
ISB.IsB!
Icc. IcC!
Icc. Icc!

110 Pin
HighZ
Data Out
Data In

Ref. Cycle

Read Cycle (1) (2)
Write Cycle (1) (2)

• DC AND OPERATING CHARACTERISTICS (Vee = 5V :I: 10%, T. = O°C to 70°C. Vss = OV)

Item
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Average Operating Current

Symbol

ISB!

Test Condition
Vee = 5.5V, VIN = Vss to Vee
CS = VIH, VI/O = Vss to Vee
CS = V1L , 1110 = OrnA
Min. Cycle, Duty: 100%,1110 = OrnA
CS = V1H , VIN = VIH or V1L
CS ;:: Vee - 0.2V
VIN :s 0.2V or VIN ;:: Vee - 0.2V

VOL
VOH

IOL = SmA
IOH = -4mA

IILlI
IILOI
Icc
IcC!
ISB

Standby Power Supply Current
Output Low Voltage
Output High Voltage

Min.

Typ.

-

-

Unit

-

Max.
2
10
100
120
30

-

-

10

rnA

2.4

-

0.4

V
V

-

• AC TEST CONDITIONS

• Input Pulse Levels: Vss to 3.0V
• Input Timing Reference Levels: 1.5V
• Output Reference Levels: 1.5V

• Input Rise and Fall Times: 4ns
• Output Load: See Figure

+5V

+5V

Dout

4800

Dout

2550

2550

4800
5 pF *

Output Load B
(for t Hz , tLZ ' twz &

Output Load A

low)

*Including scope and Jig capacItance.

•
218

HITACHI

Hitachi Amenca, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

-

p,A

/LA
rnA
rnA
rnA

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6708A Series
• CAPACITANCE (Ta = 25°C, f = 1.0MHz)
Symbol

Test Conditions

Max.

Unit

Input Capacitance

Item

C 1N

6.0

pF

Output Capacitance

CliO

= OV
VIla = OV

10.0

pF

NOTE:

V IN

ThIS parameter is sampled and not 100 % tested .

• AC CHARACTERISTICS (Vcc = 5V ± 10%, Ta = O°C to 70°C, unless otherwise noted.)
• Read Cycle
Item
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Selection to Output in Low Z

HM6708A-15

HM6708A-20

HM6708A-25

Min.

Max.

Min.

Max.

Min.

tRC

15

-

20

-

25

-

ns

-

tAA

-

15

-

20

-

25

ns

-

tACS

-

15

-

20

25

ns

-

toH
tLZ

3
3

-

3
3

-

3
3

-

ns

-

-

ns

1,2

ns

1,2

Unit

Notes

Symbol

-

-

Max.

Unit

Chip Deselection to Output in High Z
NOTES:

0
6
0
8
0
10
tHZ
I. This parameter is sampled and not 100% tested.
2. TransitIOn is measured ±200mV from steady state voltage with specified loading in Load B.

Notes

• Write Cycle
HM6708A-15

HM6708A-20

HM6708A-25

Min.

Max.

Min.

Min.

Max.

twc

15

-

20

-

25

-

ns

-

15

-

20

-

ns

-

Address Valid to End of Write

lew
tAW

10
10

-

15

-

20

-

ns

-

Address Setup Time

tAS

0

-

0

-

0

-

ns

-

Write Pulse Width

twp

10

-

15

-

20

-

ns

-

Write Recovery Time

tWR

0

-

0

-

0

-

ns

-

Data Valid to End of Write

tDW

9

-

12

-

15

-

ns

-

Data Hold Time

tDH

0

-

0

-

0

-

ns

Write Enable to Output in High Z

twz

0

6

0

8

0

10

ns

2, 3

ns

2, 3

Item
Write Cycle Time
Chip Selection to End of Write

Symbol

Max.

0
0
0
tow
I. All write cycle timmgs are referenced from the last valId address to the first transitionmg address.
2. TransitIon is measured ±200mV from steady state voltage with specified loading in Load B.
3 This parameter IS sampled and not 100% tested.

Output Active from End of Write
NOTES:

1

-

~HITACHI
Hitachi America, Ltd • Hitachi Plaza· 2000 Sierra Point Pkwy.• Bnsbane,_ CA 94005-1819 • (415) 589-8300

219

HM6708A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORM

• Read Cycle (1) (1)(2)

Address
tOH
tOH

Data Out

Previous Data Valid

• Read Cycle (2)

Data Valid

(1) (3)

tRC

cs

/

'-'"'

tACS
tLZ

Data Out

Hi9 him pedan ce

·V.XX'V
I"
./1'\.

~

tHZ
Data Valid

,
/

Hi 9h
Impedance

NOTES:

I. WE is High for READ cycle.
2. Device is continuously selected, CS =

VIL.

3. Address valid prior to or coincident with CS transition low.

~HITACHI
220

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6708A Series
• Write Cycle (1)

(WE Controlled)
twe

Address
tew

cs
twp(1)

WE

Din
High Impedance

Dout

• Write Cycle (2)

(CS Controlled)
twe

Address
tew

cs
WE
tow

Data In

Data Valid
High Impedance (2)

Dout
NOTES:

I. A write occurs during the overlap of a low CS and a low WE (twp).

2. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not
be applied.
4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output
buffers remain in a high impedance state.
5. If CS is low during this period, I/O pins are in the output state. Then the data mput signals of opposite phase to the
outputs must not be applied to them.
6. Output data is the same phase of write data of this write cycle.

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

221

HM6709

SerieS-Preliminary

65536·Word x 4·Bit High Speed Static RAM (with OE)
• FEATURES
• Super Fast
Access Time .......................... .20/25ns (max.)
• Fast OE
Access Time ............................. 10ns (max.)
• Low Power Dissipation .......................350mW (typ.)
• + 5V Single Supply
• Completely Static Memory
No Clock or Timing Strobe Required
• Balanced Read and Write Cycle Time
• Fully TTL Compatible Input and Output
• 300 mil 28 pin SOJ
• ORDERING INFORMATION
Type No.

(CP-28DN)
• PIN ARRANGEMENT

NC

Access Time

Package

Ao

20ns
25ns

300 mil 28 pin
Plastic SOJ
(CP-28DN)

Al
A2

HM6709JP-20
HM6709JP-25

A3
A4

• BLOCK DIAGRAM
As 0----1
Alo----I
A20----I
A30----I
A40----i
As 0----1
Ag o - - - - i

As
Aa
A7

As
Memory Matrix
256 X 1024

Ag

CS
OE

VSS

AlOo---~~===!
1/0 1 0--_-1.:>-1

Column 1/0

(Top View)

1/020---.+H
1I030-_++H
1/04

o--'++H-I~-I
L...-_--'

~HITACHI
222

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6709 Series
• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Rating

VT

-0.5 to +7.0

V

PT

1.0

W
°C

Terminal Voltage to Vss Pin
Power Dissipation
Operating Temperature Range

o to

Topr

Storage Temperature Range (with bias)

Tstg(b,as)
T stg

Storage Temperature Range

Unit

+70

-10 to +85

°C

-55 to + 125

°C

• RECOMMENDED DC OPERATING CONDITIONS (O°C :5 Ta :5 70°C)
Symbol

Min.

Typ.

Max.

Vcc

4.5

5.0

5.5

V

0.0

0.0

0.0

V

Input High Voltage

Vss
VIH

2.2

-

6.0

V

Input Low Voltage

VIL*

-3.0

-

0.8

V

Item
Supply Voltage

Unit

'Pulse width: 20ns, DC: -0.5V

• TRUTH TABLE
CS

OE

WE

Mode

Vcc Current

110 Pin

Ref. Cycle

H

H or L

H or L

Not Selected

ISB,IsBI

High Z

-

L

H

H

Output Disabled

Icc, IcC!

High Z

L

L

H

Read

Icc, Icci

Data Out

Read Cycle (1) (2) (3)

L

H

L

Icc, Icc I

Data In

Write Cycle (I) (2) (3) (4)

L

L

L

Icc, Icci

Data In

Write Cycle (5) (6)

Write

-

• DC AND OPERATING CHARACTERISTICS (Vcc = 5V ± 10%, Ta = O°C to 70°C)
Item

Symbol

Typ.

Max.

Unit

IIul

Vcc = 5.5V, VIN = Vss to Vcc

-

-

2

p.A

Output Leakage Current

IILOI

CS = VIH or OE = VIH , WE = VIL
Vila = Vss to Vcc

-

-

10

p.A

Operating Power Supply Current

Icc

-

-

100

rnA

Icci

CS = VIL , 1110 = OmA
Min. Cycle, Duty: 100%,1110 = OmA

-

-

120

rnA

ISB

CS = VIH , VIN = VIH or V IL

-

-

30

rnA

ISBI

CS ~ Vcc - 0.2V
V IN :5 0.2V or VIN

-

-

10

rnA

-

-

0.4

V

Input Leakage Current

Average Operating Current
Standby Power Supply Current
Output Low Voltage

VOL
VOH

Output High Voltage

Test Condition

~

IOL = 8mA
IOH = -4mA

Min.

Vcc - 0.2V

2.4

-

-

V

• AC TEST CONDITIONS
• Input Pulse Levels: Vss to 3.0V
• Input and Output Reference Levels: 1.5V

• Input Rise and Fall Time: 4ns
• Output Load: See Figure
+5 V

+5V

DOU~

DOU~ 4800
2550

4800

2550~5PF'

~30PF'

Output Load B
(for tHz, tLZ' tOHZ' IoLz, twz & tow)

Output Load A
'Including scope and jig capacitance.

o

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

223

HM6709 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• CAPACITANCE (Ta

= 25°C, f = 1.0MHz)

Item

Symbol

Test Conditions

C IN

= OV
Vila = OV

Input Capacitance
Input/Output Capacitance
NOTE:

CliO

Typ.

Max.

Unit

-

-

6

pF

-

-

10

pF

Min.

V IN

This parameter is sampled and not 100% tested .

• AC CHARACTERISTICS (Vcc

= 5V

± 10%, Ta

= O°C to 70°C, unless otherwise noted.)

• Read Cycle
Item

Symbol

HM6709JP·20

HM6709JP·25

Min.

Max.

Min.

Max.

Unit

Notes

tRC

20

-

25

-

ns

-

Address Access Time

tAA

20

ns

tACS

20

-

25

Chip Select Access Time

-

25

ns

-

Chip Selection to Output in Low Z

tLZ

0

-

0

-

ns

1,2

Output Enable to Output Valid

tOE

0

10

0

10

ns

Output Enable to Output in Low Z

toLZ
tHZ

0

0

-

ns

1,2

0

10

ns

1,2

toH

5

8
-

5

-

ns

-

Unit

Notes

Read Cycle Time

Chip Deselection to Output in High Z
Output Hold from Address Change
NOTES:

0

-

I. This parameter is sampled and not 100% tested.
2. Transition is measured ±200mV from steady state voltage with specified loading is Load B.

• Write Cycle
Item

Symbol

HM6709JP·20

HM6709JP·25

Min.

Max.

Min.

Max.

ns

I

ns

-

ns

-

ns

-

Write Cycle Time

twc

20

-

25

Chip Selection to End of Write

tcw

15

20

Address Setup Time

tAS

0

20

-

Write Pulse Width

tAW
twp

15

-

15

-

20

-

ns

-

Write Recovery Time

tWR

3

-

3

-

ns

-

Address Valid to End of Write

0

Write to Output in High Z

twz

0

8

0

10

ns

2,3

Data Valid to End of Write

tDW

12

-

15

-

ns

Data Hold Time

tDH

0

-

0

-

ns

-

Output Disable to Output in High Z

tOHZ

0

8

0

10

ns

2, 3

Output Active from End of Write

tow

0

-

0

-

ns

2,3

NOTES:

1. All write cycle timings are referenced from the last valid address to the first transitioning address.
2. This parameter is sampled and not 100% tested.
3. Transition is measured ±200mV from steady state voltage with specified loading in Load B.

~HITACHI
224

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 0 9 Series
• TIMING WAVEFORM

• Read Cycle (1)

(1)

Address

OE

cs
tCll

Data Out

Data Valid

High Impedance

• Read Cycle (2)

(1)(2) (3)

)(

Address

)(
tAA

tOH

tOH

Data Out

• Read Cycle (3)

\ X

Data Valid

(1) (3) (4)

tRC

cs

""

Data Out

NOTES:

XXX) K

Previous Data Valid

/E
tCll

High Impedance

1. WE
2. CS

=
=

tCHl

tACS

KX>OK.

Data Valid

"-

/

VlH

VIL

3. OE = VIL

4. Address valid prior to or coincident with CS transition low.

~HITACHI
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

225

HM6709 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Write Cycle (1)

(OE = H, WE Controlled)
twe

Address
tew

cs
twp(1)

WE
tow

tOH

Data Valid

Data In
High Impedance

Data Out

• Write Cycle (2)

(OE = H, CS Controlled)
twe

Address
tew

cs
twp(1)

WE
tow

Data In

Data Valid
High Impedance

Data Out

@HITACHI
226

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6709 Series
• Write Cycle (3)

(OE = Clocked, WE Controlled)
IWC

Address

OE
tcw

cs
twp(1)

WE

High Impedance

Data Out

tDW

Data In

High Impedance

~~----------------~~

High Impedance

• Write Cycle (4)

tDH

(OE = Clocked, CS Controlled)

twc

Address

OE
tcw

cs
tWR

twp(1)

WE

Data In
Data Out

~HITACHI
Hitachi America, Ltd • Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

227

HM6709 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• Write Cycle (5)

(DE = L, WE Controlled)

Address

cs
twp

WE

(1)

(2)

High Impedance

Data Out

tow

Data In

High Impedance

• Write Cycle (6)

tow

~~-)Ooj --~

tOH

.m-....-------....-l-. (5) High Impedance
Data Valid

(DE = L, CS Controlled)

twc
Address

cs
twp

(1)

WE
High Impedance

Data Out

tow

Data In

NOTES:

High Impedance

tOH

Data Valid

I. A write occurs during the overlap (twp) of a low CS and a low WE.

2. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not
be applied.
3. Output data is the same phase of write data of this write cycle.
4. If the CS is low transition occurs after the WE low transition, output remain m a high impedance state.
5. If CS is low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the
outputs must not be applied to them.
6. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain in
high impedance state.

~HITACHI
228

Hitachi A;nerica, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM6709A Series-Product Preview
65536-Word x 4-Bit High Speed Static RAM (with OE)
• FEATURES

• Super Fast
Access Time ....................... .15/20/25ns (max.)
• Fast OE
Access Time ......................... .8/10/10ns (max.)
• Low Power Dissipation ...................... .400mW (typ.)
• + 5V Single Supply
• Completely Static Memory
No Clock or Timing Strobe Required
• Fully TTL Compatible Input and Output

(DP-28N)

• ORDERING INFORMATION
Access Time

Package

HM6709AP-15
HM6709AP-20
HM6709AP-25

Type No.

15ns
20ns
25ns

300 mil 28 pin
Plastic DIP
(DP-28N)

HM6709AJP-15
HM6709AJP-20
HM6709AJP-25

15ns
20ns
25ns

300 mil 28 pin
Plastic SOJ
(CP-28DN)

• BLOCK DIAGRAM

A20----l
A30----l
A4 0----I
A7 0----I
As 0----1
As 0----1
As 0----1
As o----l
1/0 1 0---.-1
1/020---.+H
1/03 o-_>++H
1/04 o--,f-H+C>

-OO

High Impedance

Data Valid

1. WE = VIH
2. CS = VIL.
3. OE

= VIL.

4. Address valid prior to or coincident with CS transition low.

•
232

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005· 1819 • (415) 589·8300

)

~

HM6709A Series
• Write Cycle (1)

(OE

= H, WE Controlled)
twe

Address
tew

CS
tAW
twp(1)

WE
tDW

Data In

tDH

Data Valid
High Impedance

Data Out
• Write Cycle (2)

(OE

= H, CS Controlled)
twe

Address
tAs

tew

CS
tAW
twp(1)

WE
tDW

Data In
High Impedance

Data Out

~HITACHI
Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

233

HM6709A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Write Cycle (3)

(DE

= Clocked, WE Controlled)
twe

Address

OE
tew

cs
twp(1)

WE
tOLZ(2

High Impedance

Data Out

tDW

Data In

High Impedance

• Write Cycle (4)

(DE

tDH

~,.-h---------~~High Impedanc.

= Clocked, CS Controlled)
twe

Address

OE
tew

cs
tWR

twp(1)

WE

Data In
High Impedance

Data Out

~HITACHI
234

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6709A Series
• Write Cycle (5)

(OE

= L, WE Controlled)

Address

cs
twp

WE

(1)

High Impedance

Data Out

tow

Data In

High Impedance

• Write Cycle (6)

(OE

tow
(3)

tOH
(5)

Data Valid

High Impedance

= L, CS Controlled)

Address

cs
twp

(1)

WE
High Impedance

Data Out

tow

Data In

NOTES:

High Impedance

tOH

Data Valid

I. A write occurs during the overlap (twp) of a low CS and a low WE.

2. During this period, 110 pins are in the output state so that the input signals of opposite phase to the outputs must not
be applied.
3. Output data is the same phase of write data of this write cycle.
4. If the CS is low transition occurs after the WE low transition, output remain in a high impedance state.
S. If CS is low during this period. 110 pins are in the output state. Then. the data input signals of opposite phase to the
outputs must not be applied to them.
6. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain in
high impedance state.

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

235

HM6207 S e r i e s - - - - - - - - - 262144-word x 1-bit High Speed CMOS Static RAM
The Hitachi HM6207 is a high speed 256k static RAM organized as 256-kword x 1-bit. It realizes high speed access time
(35/45 ns) and low power consumption, employing CMOS
process technology and high speed circuit designing technology.
It is most advantageous for the field where high speed and high
density memory is required, such as the cache memory for main
frame or 32-bit MPU. The HM6207, packaged in a 300 mil
plastic DIP, is available for high density mounting.
Low power version retains the data with battery back up.

Features
• High Speed: Fast Access Time 35/45 ns (max.)
• Low Power
Standby: 100 IJ,W (typ.)/30 IJ,W (typ.) (L-version)
Operation: 300 mW (typ.)
• Single 5V Supply and High Density 24 Pin Package
• Completely Static Memory:
No Clock or Timing Strobe Required
• Equal Access and Cycle Time
• Directly TTL Compatible: All Inputs and Outputs
• Capability of Battery Back Up Operation (L·version)

(DP-24NC)

Pin Arrangement

Ordering Information
Type No.

Package

Access Time

HM6207P-35
HM6207P-45

35 ns
45 ns

HM6207LP-35
HM6207LP-45

35 ns
45 ns

300-mil 24-pin Plastic DIP

Absolute Maximum Ratings
Symbol
Item
Voltage on Any Pin Relative to VSS
Power Dissipation
Topr
Operating Temperature
Tstg
Storage Temperature
Storage Temperature under bias
Tbias
Note)·1. -2.SV for pulse width;:; IOns.

(Top View)
Rating
-0.5.1 to +7.0
1.0
o to +70
-55 to +125
-10 to +85

•
236

Unit
V
W

°c
°c
°c

Pin Description
Pin Name
AO - A17
Din
Dout
_ _ CS ____
WE
Vee
Vss

Function
Address
Data Input
Data Output
9tip Select
Write Enable
Power Supply
Ground

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 0 7 Series

Block Diagram
AI5
AI6
AI7

-Vee
Memory Array
256 X 1,024

AO

_ V..

Al

A2
A3

A4

Dm--{~-1--~

. -......r - 00• 1

Function Table
Mode
CS
WE
NOT SELECTED
H
X
H
READ
L
L
WRITE
L
Note) X means don't care.

Vee Current
ISB,ISBI
Ice
lee

Recommended DC Operating Conditions (Ta
Parameter

Symbol

Vee
Supply Voltage
VSS
Input High (logic 1) Voltage
VIH
Input Low (logic 0) Voltage
VIL
Note) .1. -2.0V for pulse width;:;; 10 ns

Dout Pin
HIGH-Z
Dout
HIGH-Z

Symbol

READ CYCLE
WRITE CYCLE

=0 to +70°C)
min
4.5
0
2.2
-0.5.1

typ

min

max
5.5
0
6.0
0.8

5.0
0

DC and Operating Characteristics (Ta = 0 to +70°C, Vee
Parameter

Ref. Cycle

Unit
V
V
V
V

=SV ± 10%, Vss =OV)
typ·1

max

Unit

Input Leakage Current

tILlI

2.0

pA

Output Leakage Current

IILOI

10.0

pA

60

100

rnA

15

30

rnA

Operating Power Supply Current

lee

Standby Power Supply Current

ISB

Standby Power Supply Current (1)

ISBI

0.02
0.006.2

2.0
0.1 *2

Output Low Voltage
0.4
VOL
Output High Voltage
2.4
VOH
Note) .1. Typical limits are at Vee = S.OV, Ta = 2S·C and specified loading.
·2. This characteristics is guaranteed only for L-version.

Test Condition
Vee = MAX.
VIN = VSS to Vee
CS= VIH
Vout = VSS to Vee
CS= VIL
lout =Om A, min. cycle
CS = VIH, min. cycle
CS} Vee-O.2V,

rnA

OV~ VIN ;:;; 0.2V or
VIN ~Vee-0.2V

V
V

IoL- 8mA
IOH = -4.0mA

.HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

237

HM6207 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Capacitance (Ta = 25°C,/= 1.0MHz)
Symbol
. Parameter
Min
Input Capacitance
Cin
Output Capacitance
Cout
Note) This parameter is sampled and not 100% tested.

Typ

Unit
pF
pF

Max
6.0
10

Conditions
Yin = OV
Vout- OV

------------~-----------~-

AC Characteristics (Ta= 0 to +70°C, Vee= 5V ± 10%, unless otherwise noted.)
AC Test Conditions
• Input pulse levels: Vss to 3.0V
• Input rise and fall times: 5ns

• Input and Output timing reference levels: 1.5V
• Output load: See Figures .
Output Load (B)

Output Load (A)

(for

+5V

1HZ.

&
+5V

t LZ• twz

tow)

480
Dout

0---.----.
255

Dout

3OpF*

Q

Q

0---.---..
255

Q

*Including scope & jig.
Read Cycle
Parameter

Symbol

Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Selection to Output in Low Z
Chip Deselection to Output in High Z
Chip Selection to Power Up Time
Chip Deselection to Power Down Time

tRC
tAA
tACS
tOH
tLZ
tHZ
tpu
tPD

HM6207-35
min
max
35
35
35
5
5
0
30
0
30

HM6207-45
min
max
45
45

Unit
ns
ns
ns
ns
ns
ns
ns
ns

46

5
5
0
0

30
40

Notes
*1

*2,*3,*7
*2,*3,*7
*7
*7

Timing Waveform of Read Cycle No. 1.4 ,.5

Address

'0.

'0'
Data Valid

Dout

~HITACHI
238

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, GA 94005-1819 • (415) 589-8300

-----------------------------------------------------------------HM8207S.ies
Timing Waveform of Read Cycle No. 2"4,·6

cs _______"'"\

J-~-------------'.!!~

'HZ

I"

Dout ---------f----------------~

Data Valid

H.""

Hitch Impt"danct'

Impt"dan('('
IpD

Vee

supply

current

Notes) .1. AIJ Read Cycle timings are referenced from last valid address to the first transitioning address.
·2. At any given temperature and voltage condition, tHZ max. is less than tLZ min. both for a given device and from
device to device.
·3. Transition is measured ±200mV from steady state voltage with specified loading in Load B.
·4. WE is high for READ Cycle.
·5. Device is continuously selected, while CS = V/L.
·6. Addresses valid prior to or coincident with CS" transition low.
·7. This parameter is sampled and not 100% tested.
Write Cycle
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write

Symbol

twe
tew
tAW
tAS
twp
tWR
tDW
tDH
twz
tow

HM6207-35
min
max
35
30
30
0
25
3
20
0
0
0

•

20

HM6207-45
min
max
45
40
40
0
25
3
20
0
0
0

25

Unit

Notes

ns

*2

ns
ns
ns
ns
ns
ns
ns
ns
ns

*3, *4
*3,*4

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

239

HM6207 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Timing Wa\'eform of Write Cycle No.1 (m Controlled)
t.e

------------- ----

"

Address

/\
__t_ew_ _ _ _ _ _ _

I
cs

\\\\ \\\
.

~

_____

I

-~-~------~---

--~\

_----.J..~---_

.\\I\"

\"

/

~--V
t ••

t.w

I-

V
I\"

Om

/////i//////

Data

In

l(

Valid

I\"
to.

~

V

Dout

I

\

High Impedance

Timing Waveform of Write Cycle No. 2 (~ Controlled)

twe

Address

\V

\V
11\

/\"
te.

tAS

l

/

V

t..
two
top

VIIIIIIII/i/;

\\\\\\\\\\\\\\\\

to.

t.w

\/
I

Om

Data m Valid

\V

/'\

~
Dout

Notes) '1.
'2.
'3.
'4.

/

Data Undefmed

HlIh Impedance

If CS goes high simultaneously with WI;: high, the output remains in a high impedance states.
All Write Cycle timings are referenced from the last valid address to the first transitioning address.
Transition is measured ±200mV from steady state voltage with specified loading in Load B.
This parameter is sampled and not 100% tested .

•
240

/

HITACHI

Hitachi America, ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 0 7 Series
Low Vee Data Retention Characteristics (Ta = 0 to +70°C)
(This characteristics is guaranteed only for L-version)

._--

----------

Chip Deselect to Data Retention Time
-----Operation Recovery Time

Test ConditIOn
min _ _--"""-'--_~="___~=_""""'c_;_;--~~~
typo
max.
Urnt
_ _ _ _S-:yc:-m_b_o_l_----'-'=
CS ~ VCC - 0.2V
VDR
2.0
V
V{r~ Vc«- 0.2\! or
50"2
ICCDR
2
IJA
o -Vin-0.2V
tc
DR
0
ns
See
retention
----=-=--'-'-------.,,.------waveform
tRC"!
tR
ns

Note) "1.

"2. V CC= 3_0V

Parameter
V CC for Data Retention
Data Retention Current

IRC = Read Cycle Time

Low Vee Data Retention Waveform

Data Rett'ntlOn Mode

vcc - - - - - - -.....
4.5V---------

cs ~ Vcc-O.2V
c s - -_ _-'
w ________________________________________ _

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

241

•
242

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

HM6207/HM6207H Series
1-Bit CMOS Static RAM
262l44-Word x l-Bit High Speed CMOS Static RAM
The Hitachi HM6207 and HM6207H are high speed 256k
static RAMs organized as 256-kword x I-bit. They realize high
speed access time (25/35/45ns) and low power consumption,
employing CMOS process technology and high speed circuit
design technology. It is most advantageous wherever high
speed and high density memory is reqUired.
The HM6207 and HM6207H are packaged In the Industry
standard 300-mll, 24-pln plastiC DIP The HM6207H IS also
available In a 300-mll, 25-pln plastiC SOJ package for high
density mounting The low power versions are Ideal for battery
backed systems.
(DP':!-1-NC)

Features
• Single 5 V supply and high density 24-pln package
• High speed
Access time: 25/35/45 ns (max)
• Low power
300 mW (typ)
Active.
100 I'W (typ)
Standby:
30 I'W (typ ) (L-verslon)
• Completely static memory requires
No clock or timing strobe reqUires
• Equal access and cycle time
• All Inputs and outputs TTL compatible
• Capability of battery back up operation (L-verslon)

,
(CP-2..J.D)

Pin Arrangement

Ordering Information
Type No
HM6207P-35
HM6207P-45
HM6207HP-25
HM6207HP-35
HM6207HLP-25
HM6207HLP-35
HM6207H1P-25
HM6207H1P-35
HM6207HLJP-25
HM6207HLJP-35

Package
35 n,
45
25
35 ns
25
35 I"

n,
n,
n,

35 ns
25 n,
35ns

300-mll
24-pm
plastIc DIP
(DP-24NC)
300-11111
24-pm
plastiC SOl
_~P~ _ _

Pin Description
-------,-

Pm Nam---=-e_ _ _FuncllOn
AD - Al7
Address

Om
_Data InE"_t_____ _
. Dout______ _ Dataollt!"'.' __ _
CS

ChlP--,-C!cct

WE----- Wnte enable
Vee

Vss

_~uwcr Sl_lppl~

Ground

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra POint Pkwy· Brisbane, CA 94005-1819 • (415) 589-8300

243

HM6207/HM6207H S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Block Diagram

AI5
AI6
AI7

-Vee

Melllory Arrll)'
256X 1,024

AO

...._Vs..

AI

A2
A3
A4

DID--C::r-~--I

Function Table
TI
WE
H

x

L
L

H

Note:

L

Mode
Not selccted
Read
Write

Dou!

Vee Currenl

I/O Pin

Ref, Cycle

IS8, isOI
Icc
Icc

Hlgh-Z
Dout
High-Z

Read cycle
Write cycle

x means don't care.

Absolute Maximum Ratings
Symbol
Vin

Item
Voltage on any pin relative to Vss
Power dissipation

1.0

Operating temperature range
Storage temperature range
Storage temperature range under bias

Note: *1.

Yin min = -2.5 V for pulse widlh

Value
_0.5'1 to +7,0

Topr
Tstg
Tbias
~

oto +70
-55 to +125
-10 to +85

Unit
V
W
·C
·C
·C

10 ns.

~HITACHI
244

Hitachi America, ltd, • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 0 7 / H M 6 2 0 7 H Series

Recommended DC Operating Conditions (Ta = 0 to +70°C)
Item

Symbol
Vee
Supply voltage
Vss
Input high (logic 1) voltage
VDf
Input low (logic 0) voltage
VIL
Note: *1. VIL min =-2.0 V for pulse width :s; 10 ns.

Min
4.5
0

v
V
V
V

6.0
0.8

-0.5"

Symbol

Unit

o

2.2

• DC Characteristics (Ta = 0 to +70°C, vee = 5 V
Item

Max
5.5

Typ
5.0
0

± 10%,

vss = 0 V)

Min

Typ '.

Max

Input Leakage Current

IIul

-

-

20

~A

Ou.put Leakage Current

IILOI

-

-

100

~A

OpcrallOg Power Supply Current

Icc

-

60

100

rnA

I,.

-

15

30

rnA

Is.

-

20

40

mA

Is••

-

20

2000

~A

I,.t

-

6

100

~A

Standby Power Supply Current
Standby Power Supply Current

I . H" VCI"\lon

Standby Power Supply Current (I)
Standby Power Supply Current (I)

J

L-Vcr"on

Tc ...t Condition...

Umt

Vec = Max
Vm = Vss to Vee
CS = VtH
V110 = VS'i to Vee

CS = VtL . 1110 = 0 rnA.
Min Cycle. Duty = 100%

CS

= VIH • Min Cycle

CS"V ec -02V

o V :s

Vm S 02 V or
Vm ~ Vee - 0 2V

QUlPUI Low Voltage

VOL

-

-

04

V

i OL=8mA

Output H.gh Vohage

VOH

24

-

-

V

IOH = -40mA

Note

*1 Typical hnllt ... arc at Vee = 50 V. T.. = +25°C and

!lPCClflCd

loadmg

Capacitance (Ta = 25°C, f = 1MHz)"'
Item
Input capacitance
Output capacitance
Note:

Symbol
Cin
Cout

Min

Max

Unit

6
10

pF
pF

Test Conditions
Vin=OV
V••t=OV

*1. This parameter is sampled and not 100% tested.

AC Characteristics (Ta = 0 to +70°C, Vee = 5 V ± 10%, unless otherwise noted.)
Test Conditions
• Input pulse levels: Vss to 3.0 V
Input and output timing reference levels: 1.5 V
Output load: See Figures
• Input rise and fall times: 5 ns
Output Load (A)

Output Load (B)
(for 1HZ, tLZ,

+5V

....

tow)

+5V

~ .F.
....

....

~
255D

255g

Note:

lWZ &

....
Spr.

* Including scope & jig.

•

HITACHI

Hitachi America. Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

245

HM6207/HM6207H Senes - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Read Cycle
Item

Mm.
Read Cycle TIme
Address Access Time

HM6207-35
HM6207H-35

HM6207H-25

Symbol

Max.

Mm.

HM6207-45

Max.

Min.

Unit

Max.

tRC

25

-

35

-

45

-

ns

tAA

-

25

-

35

-

45

ns

25

-

35

-

45

ns

5

5
5

-

ns

5

-

tACS

-

Output Hold From Address Change

toH

5

ChIp Selection to Output m Low-Z

tLZ' 1

5

-

Chip Deselection to Output in Hlgh-Z

tHZ' 1

0

12

0

20

0

30

ns

ChIp Selection to Power Up TIme

tpu

0

-

0

-

0

-

ns

Chip Deselectlon to Power Down TIme

tpD

-

15

-

25

-

40

ns

Chip Select Access Time

Note

*1 TranMtlon .. mea.ured ±200 mY from ;teady ;tate voltage wIth Load (B) Th .. parameter .. ;ampled and not 100% tested

Read Timing Waveform (1)

'I. '2

I"

Address

~

----.I

I ..
10.

10.

Dout

Data Invahd

I

IK&

Da'" Valid

1,\

Read Timing Waveform (2) 'I. '3

cs - - -....

I"
~----~~----~.---~=--~-----

-- - ---- - - - 11,.------

I
I

tu

Dout

1/,-------.,.\ , - - - - - - - t - - -......
Data Invalid
I
nata Vahd
If---

----+--------{

'--------t---;---tlm.p~:('l'

High ImpedancI!

Vee supply

---------------+~----------------------~---....+

.../,if

_lc_,_______

50""

Notes: '1. "WEis high for read cyde.
'2. Device is continuously selected, CS =VIL.
'3. Address vahd prior to or coincident with CS tranSition low.

$HITACHI
246

Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

ns

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6207/HM6207H Series

• Write Cycle
HM6207-35
HM6207H-35

HM6207H-25

Symbol

Item

HM6207-45

Mm

Max

Mm

Max

Mm.

Max.

Unll

Write Cycle Time

twe

25

-

35

-

45

-

n,

Chip SelectIOn to End of Wnte

tew

20

-

30

-

40

-

n,

Addre" Valid to End of Write

tAw

20

-

30

-

40

-

n,

Addre" Setup Time

tAs

0

-

0

-

0

-

ns

twp

20

-

~

-

35

-

ns
ns

I

Wnte Pube Width

I "H" Vcn~lon

30

Wntc Recovery Tmlc

tWR

3

-

3

-

3

-

Data Valid to End of Wnte

tDw

15

-

20

-

20

-

ns

Data Hold Time

tDH

0

-

0

-

0

-

ns

Wnte Enabled to Output m Hlgh-Z

twz 'I

0

8

0

10

0

15

ns

Output Active From End of Write

tow 'I

0

-

0

-

0

-

Note

*I

Tran~ltlon 1~ mea~ured

±200 mY from high Impedance voltage with Load (B)

Thl~

parameter

I~ ~arnplcd

and not 100%

ns
tc~tcd

Write Timing Waveform (1) (WE Controlled)

.-------~~------~~~--------~---------------------------------------~

twe

---~-

Address

cs

~V

----./""

/\.

\\\'\I\\t.
t"

--~~--

-~---

t ..

----V///~1/////
1-----'--"----

I

t.,

I
WE

----

\ \ 1'\

./
-~~------ ~

\JI
A

Data Vahd

\.

tow

I---'"'-Dout
High Impedance

/
\.

@HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

247

HM6207/HM6207H Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Write Timing Waveform (2) (CS Conlrolled)
------~~.----"------ .. . ! . ! " £ ' - - - - - - - - - - - - _ 1

Address

----~----.--

cs
--~---~---- ~-----

------_._- -~-~WE

Dm

Data Vahd

I.'~
Dout

-----------«

D... l',d,fm,d
.

Notes:

*1. A wnte occurs dunng the overlap of a low CS and a Jow WE.
*2. tWR is measured from the eaTHer of CS or WE going high to the end of wnte cycle.
*3. If the CS low transition occurs simultaneously with the WE low transtUon or after the WE transition, the output buffers remain
in a high Impedance state.
*4. Dout is the same phase of wnte data of this write cycle, If tWR is long enough .

•
248

r-- - - - - - - - - - - - - - - - - - - HllJh Impedancl'

HITACHI

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6207/HM6207H Series

Low Vee Data Retention Characteristics (Ta = 0 to +70'C)
These characteristics are guaranteed only for L-version.
-----TtCn1-~~-~: ~~

-

s)'~l)ol---ivEn-~-f)'LMax_~i~_

Data retention current

Notes

_____~0·2

IcCOR

------ - - - - - - - - - - - - - "

Chip deselect to data retention time
Operation recovery I1me

v

20

VDR

tCDR

o
tHe "1

~A ___ _

ns
ns

Test Condi tions

CS

~Vcc-0.2

V.

Vm~Vcc-0.2Vor

o V ~ Yin ~ 0.2 V

----------

*1. tRc;:: read cycle tIme
*2 Vcc=30V.

Low Vee Data Retention Timing Waveform

-------

v,'--_ _ _ ______
45V---------

Data retention mode
--------------------------

---------

Cs---~
~-----------------------------------------

• PACKAGE DIMENSIONS Unit: mm (inch)
HM6207P/HM6207HP Sene,
WP-24NC)

I
,

~

I

298'(1176)
30 48m,,,"OOm,"

124

HM6207HJP Senes
(CP·24D)

13

,[::::::;}]!~I

--I+--

11

I 14(0045)

13(0 051)

WiViAAANffl sf ;H
c

1.

048<01
(0019

+

0004)

~5
(OICOtOQIO)

~~S ~Ig
~f~

N.9

@HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

249

HM6707 S e r i e s - - - - - - - 262144-word x 1-bit High Speed Hi·BiCMOS Static RAM
Features
• Super Fast Access Time: 20/25ns (max.)
• Low Power Dissipation
Operating: 350mW (typ.) (f = 50MHz)
•
•
•
•

HM6707P

+5V Single Supply
Completely Static Memory
No Clock or Timing Strobe Required
Balanced Read and Write Cycle Time
Fully TTL Compatible Input and Output

(DP-24NC)
HM6707JP

Ordering Information
Type No.

Access Time

HM6707p·20

20ns

HM6707p·25

25ns

HM6707JP·20

20ns

HM6 707 JP-25

25ns

Package
300mil 24 pin
Plastic DIP
300 mil
24 pin SOJ
(CP-24D)

Block Diagram

Vee

Ao
AlO---i:A::J
A2 ~---'.-<-1
A3~--r~'

Pin Arrangement

--0
--0

Row

Memory Matrix

Vss

Vee

Ao
AI

AI7

As~--.",,--,

A2

AI6

A9

A3

AI5

A4

Au

As

AI3
A12
All

A4

Decoder

256XI024

AIO ~---'r';~-'L-_ _-'

Din

As
A7

AIO

As
Dout

~<>--=~~
WEo-

As

WE

Din

VSS

CS
(Top View)

Note)

The specifications of this device are subject to change without notice.
Please contact Hitachi's Sales Dept. regarding specifications.

~HITACHI
250

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra POint Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 0 7 Series

Absolute Maximum Ratings
Symbol

Item

Rating

Power Dissipation
Operating Temperature Range

Unit

-0.5 to +7.0

Terminal Voltage to Vss Pin
Topr

W

o to +70

°c
°c
°c

Storage Temperature Range (with bias) TstR(bias)

-10 to +85

Storage Temperature Range

-55 to +125

Tstg

Recommended DC Operating Conditions (Ta
Item

V

1.0

=0 to +70°C)

Symbol

min.

typo

max.

Unit

Vcc

4.5

5.0

5.5

V

Vss

0

0

0

V

V1H

2.2

6.0

V

VIL

-0.5*'

0.8

V

Supply Voltage
Input Voltage
Note) *1 : -3.0 V for pulse width 20ns.

Function Table
CS

WE

H

X

Not selected

ISB,lSBl

High Z

L

H

Read

ICC.ICCl

Dout

L

L

Write

Icc.ICCl

High Z

Mode

DC and Operating Characteristics (Vee
Item

Symbol

Input Leakage Current

IILl I

Output Leakage Current

IILO I

Output Pin

V cc Current

=5 V ±1O%, Ta =0 to +70°C)
min.

typo

max.

Unit

Test Conditions

2

/loA

V C9 =5.5V, V/N=VSS to Vce

10

/loA

CS = V1H, VOUT= VSS to Vec
CS = V/L,IOUT=OmA

Opera ting Power Su pply Current

Icc

100

rnA

Average Operating Current

ICCl

120

rnA

Min. Cycle, Duty: 100%,IOUT=OmA

ISB

30

rnA

CS = VIH, VIN- VIHor V/L

ISBl

10

rnA

CS ~ Vce-0.2 V
V/N;£0.2Vor V/N~ Vec-0.2V

Standby Power Supply Current
Output Low Voltage

VOL

Output High Voltage

VOH

0.4
2.4

V

IOL = 8 rnA

V

10H = -4 rnA

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

251

HM6707 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Capacitance

(Ta = 2S o C,f= 1 MHz)
Symbol

Item
Input Capacitance
Output Capacitance

COUT

max.

Unit

6.0

pF

Test Conditions
V/N = OV

10.0

pF

VOUT=OV

Note) This parameter is sampled and not 100% tested.

AC Characteristics (VCC

=SV±lO%, Ta =0 to +70°C, unless otherwise noted)

AC Test Conditions

•
•
•
•
•

Input pulse levels: VSS to 3.0 V
Input timing reference levels: 1.5 V
Output Load: See Figure
Input rise and fall times: 4 ns
Output reference levels: 1.5 V

480.0

Dout

480.0

Dout

255.0

255.0

30pF*

5pF*

*including

scope and jig

Output L08d B

Output Load A

(for tHZ, tLZ, twz & tow)

Read Cycle
Item

Symbol

HM6707-20
max.
min.

HM6707-25
min.
max.

Unit

Read Cycle Time

tRC

Address Access Time

tAA

20

25

ns

Chip Select Access Time

tACS

20

25

ns

25

20

Notes

ns

Output Hold from Address Change

tOH

5

5

ns

Chip Selection to Output in Low Z

tLZ

5

5

ns

1,2

Chip Deselection to Output
in High Z

tHZ

0

ns

1.2

Note)

15

0

15

1. This parameter is sampled and not 100% tested.
2. Transition is measured ±200 mV from steady state voltage with specified loading in Load B.

~HITACHI
252

Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 0 7 Series
Read Cyele-1*!

I - - - - - - - tRC --------1~~,

I~..

Address

,. .t----- tAA -----I~~I
+-toH
Data Out

~

Previous Data Valid

Data Valid

Read Cycle-2*2

~------ tRC -------~

..

tACS--'

+- tu"3...
High Impedance

Data Out

Data Valid

Notes) *1. WE is high and CS"is low for Read cycle .
• 2. Addresses valid prior to or coincident with CS transition low .
• 3. Transition is measured ±200 mV from steady state voltage with specified loading in Load B.
Write Cycle
Item

HM6707-20
min.
max.

Symbol

HM6707-2S
min.
max.

Unit

Notes

2

Write Cycle Time

twe

20

2S

ns

Chip Selection to End of Write

tew

IS

20

ns

Address Valid to End of Write

tAW

IS

20

ns

Address Setup Time

tAS

0

0

ns

Write Pulse Width

twp

IS

20

ns

Write Recovery Time

tWR

3

3

ns

Data Valid to End of Write

tDW

IS

20

ns

Data Hold Time

tDH

0

0

Write Enable to Output in High Z

twz

0

Output Active from End of Write

tow

0

Note)

1.
2.
3.
4.

IS

0
0

ns
IS

ns

3,4

ns

3,4

If CS goes high simultaneously with WE high, the output remains in a high impedance state.
All Write Cycle timings are referenced from the last valid address to the first transitioning address.
Transition is measured ±200 mV from steady state voltage with specified loading in Load B.
This parameter is sampled and not 100% tested .

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

253

- - - - - -----------

-

HM6707 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Write Cycle-1 (WE Controlled)

I~-------twc --------~.~I

Address
~~~~

1+---- tew -----.1

~--r_~--~~~~

1..... . - - - - - - tAW -----------+1

tow -+~tOH.
Data In Valid

Data In

*1

.. tow --+
~-------

Data Out

Data Undefined

High Impedance

Note) *1. TransItion is measured ±200 mV from steady state voltage with specified loading in Load B.

Write Cycle-2 (CS Controlled)

.
Address

•,

twc

~

I~

~\

.. tAS.

..

•-/'

tew

~ ....

1

1\

...

• f- tWR

tAW

+ - - twp -----..

\\\\\\\- \'
Data In

Data In Valid
~

Data Out

Data Undefined

If/////

7
tow

I
'":1\

-I

*1

twz

.~~
~II

11\

~

*2

High Impedance

Note) *1. Transition is measured ±200 mV from steady state voltage with specIfied loading in Load B.
*2. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition. the output
buffer remains in a high impedance state.

~HITACHI
254

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM6707A Series- Product Preview - - - - - - - - - 262144·Word x 1·Bit High Speed Static RAM
• FEATURES
• Super Fast
Access Time ........................ 15/20/25ns (max.)
• Low Power Dissipation ...................... .400mW (typ.)
• + 5V Single Supply
• Completely Static Memory
No Clock or Timing Strobe Required
• Fully TTL Compatible Input and Output

(DP-24NC)

• ORDERING INFORMATION
Access Time

Package

HM6707AP-15
HM6707AP-20
HM6707AP-25

15ns
20ns
25ns

300 mil 24 pin
Plastic DIP
(DP-24NC)

HM6707AJP-15
HM6707 AJP-20
HM6707 AJP-25

15ns
20ns
25ns

300 mil 24 pin
Plastic SOJ
(CP-24D)

Type No.

(CP-24D)
• PIN ARRANGEMENT

• BLOCK DIAGRAM

A20----I:;;.

--0

A30---~::J

Vee

- - 0 VS3

A40----I
A70----I
A80---~::J

Row

Memory Matrix

Decoder

2S6x1024

Ago----I:;;.
AS 0----1:;;'
A60---~j

Din o-_ _ _-t>____r-'----------'--l-t>--,oD,OU1

Ao

Vee

Al

A17

A2

A16

A3

A15

A4

A14

A5

A13

A6

A12

A7

All

As

AlO

Dout

Ag

WE
VSS

Din

CS
(Top View)

cs~===='~~:J

WEC>

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra POint Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

255

HM6707A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS
Unit

Symbol

Rating

Terminal Voltage to V ss Pin
Power Dissipation

VT

-0.5 to +7.0

V

PT

1.0

W

Operating Temperature Range
Storage Temperature Range (with bias)

Topr

o to +70
-10 to +S5

°C

-55 to + 125

°C

Item

Tstg(bias)
T stg

Storage Temperature Range

°C

• RECOMMENDED DC OPERATING CONDITIONS (DOC ::;; Ta ::;; 70°C)
Item

Symbol

Min.

Typ.

Max.

Unit

Vee

4.5

5.0

5.5

V

Vss
V/H
V1L

0.0

0.0

0.0

V

2.2

-

Vee + 0.5
O.S

V

Supply Voltage
Input High Voltage
Input Low Voltage

-3.0*

V

*Pulse width: 15ns, DC: -O.5V

• TRUTH TABLE
Output Pin

CS

WE

Mode

H

X

Not Selected

ISB,lsB!

HighZ

L

H

Read

Icc, Icc!

L

L

Write

Icc, IcC!

Data Out
HighZ

Vee Current

• DC AND OPERATING CHARACTERISTICS (Vee
Item

= 5V

± 10%, Ta

= DOC to 70°C, Vss = OV)
Unit
p.A

100

rnA

Input Leakage Current

Ilui

-

-

Output Leakage Current

IILOI

-

Operating Power Supply Current

Icc

Average Operating Current

IcC!

= 5.5V, VIN = Vss to Vee
CS = V/H, VOUT = Vss to Vee
CS = V1L , lOUT = OmA
Min. Cycle, Duty: 100%, lOUT = OrnA

-

-

120

rnA

ISB

CS = V1H , VIN = V/H or V1L

-

-

30

rnA

ISB!

CS ;;" Vee - 0.2V
VIN ::;; 0.2V or VIN ;;" Vee - 0.2V

-

-

10

rnA

-

-

0.4

V

2.4

-

-

V

Output Low Voltage

VOL
VOH

Output High Voltage

Vee

IOL = SrnA
IOH

= -4rnA

-

Typ.

2
10

Test Condition

Standby Power Supply Current

Min.

Max.

Symbol

• AC TEST CONDITIONS
• Input Pulse Levels: Vss to 3.0V
• Input Timing Reference Levels: 1.5V
• Output Reference Levels: 1.5V

• Input Rise and Fall Times: 4ns
• Output Load: See Figure

+5V

+5V

4800

Dout

Dout

2550

2550

4800
5 pF

*

Output Load B
(for t HZ , tLZ , twz & tOW)

Output Load A
*Including scope and jig capacitance.

~HITACHI
256

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

p.A

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6707A Series
• CAPACITANCE (Ta = 25°C, f = 1.0MHz)
Item

Symbol

Test Conditions

Max.

Unit

C IN

V IN = OV

6.0

pF

COUT

VOUT = OV

10.0

pF

Input Capacitance
Output Capacitance
NOTE:

This parameter is sampled and not 100% tested .

• AC CHARACTERISTICS (Vcc = 5V ± 10%, Ta = O°C to 70°C, unless otherwise noted.)
• Read Cycle
Item

Symbol

HM6707A-15

HM6707A-20

HM6707A-25

Min.

Min.

Max.

Min.

Max.

Max.

Unit

Notes

Read Cycle Time

tRC

15

-

20

-

25

-

ns

Address Access Time

tAA

-

15

-

20

-

25

ns

-

Chip Select Access Time

tACS

15

ns

-

tOH

-

ns

-

tLz

3
3

25

Chip Selection to Output in Low Z

3
3

20

Output Hold from Address Change

3
3

ns

1,2

ns

1,2

Unit

Notes

ns

-

-

-

Chip Deselection to Output in High Z
NOTES:

0
6
0
8
0
10
tHZ
I. This parameter is sampled and not 100% tested.
2. Transition is measured ±2oomV from steady state voltage with specified loading in Load B.

-

• Write Cycle
Item

Symbol

HM6707A-15

HM6707A-20

HM6707A-25

Min.

Max.

Min.

Max.

Min.

Max.

twc

15

-

20

-

25

Chip Selection to End of Write

tcw

10

-

15

-

20

Address Valid to End of Write

tAW

10

-

15

-

20

Address Setup Time

tAs

0

-

0

-

0

Write Pulse Width

twp

10

-

15

-

20

-

Write Recovery Time

tWR

0

-

0

-

0

-

Data Valid to End of Write

tDw

9

-

12

-

15

-

ns

Data Hold Time

tDH

0

-

0

-

0

-

ns

I
-

Write Enable to Output in High Z

twz

0

6

0

8

0

10

ns

2,3

0

-

0

-

0

-

ns

2,3

Write Cycle Time

Output Active from End of Write
NOTES:

tow
I. All write cycle timings are referenced from the last valid address to the first transitioning address.
2. Transition is measured ± 200mV from steady state voltage with specified loading in Load B.
3. This parameter is sampled and not 100% tested.

ns
ns
ns
ns
ns

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

257

HM6707A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORM
• Read Cycle (1)

(1)

Address
tOH

Data Out

Data Valid

Previous Data Valid

• Read Cycle (2) (2)
RC

cs

~I\.

.i

V

tAcs
tlZ(3)

tHZ(3)

Data Out
High Impedence

NOTES:

K200000 K

Data Valid

/

1. WE is high and CS IS low for READ cycle.
2. Addresses valid prior to or coincIdent with CS transitIOn low.
3. TransitIOn is measured ± 200mV from steady state voltage wIth specified loading In Load B.

.HITACHI
258

"

High
Impedence

Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra POint Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 0 7 A Series
• Write Cycle (1) (WE Controlled)

twe

)(

Address

)(
tew

cs

'"'"'"'"'"~

~

"l~////////////h
tAW
tAS

tWR
twp

WE

~

~~

/

tOH

tow

)

Data In

L
Data Out

NOTES:

Data In Valid
twz
_I

'"

Data Undefined

m.12)

) t'

"

tow

/1 Hgh
i Impedance

V

"

I. Transition is measured ±200mV from steady state voltage with specified loading in Load B.
2. If CS goes high simultaneously with WE high, the output remains in a high impedance state .

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

259

HM6707A Series
• Write Cycle (2)

(CS Controlled)
twc

Address
tcw

CS
tAW
twp

WE
tDW
Data In Valid

Data In
twz

Data Out

NOTES:

Data Undefined

~

High Impedance

I. Transition is measured ± 200m V from steady state voltage with specified loading in Load B.

.HITACHI
260

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM628128 S e r i e s - - - - - - - - - 131072·Word x 8·Bit High Speed CMOS Static RAM
The Hitachi HM628128 is a CMOS static RAM organized 128kword x 8-bit. It realizes higher density, higher performance and low
power consumption by employing 0.8 11m Hi-CMOS process
technology.
It offers low power standby power dissipation; therefore, it is
suitable for battery back-up systems. The device, packaged in a 525
mil SOP (460-mil body SOP) or a 600-mil plastic DIP, is available for
high density mounting.

Features
•

•
•
•
•
•
•

High speed: Fast access time 70/85/100/120 ns (max.)
Low power
Standby: 10 I1W (typ) (L-version)
Operation: 75 mW (typ)
Single 5 V supply
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Common data input and output: Three state output
Directly TTL compatible: All inputs and outputs
Capability of battery back up operation (L-version)
2 chip selection for battery back up

Ordering Information
Type No.
HM628128P-7
HM628128P-8
HM628128P-10
HM628128P-12
HM628128LP-7
HM628128LP-8
HM628128LP-10
HM628128LP-12
HM628128FP-7
HM628128FP-8
HM628128FP-10
HM628128FP-12
HM628128LFP-7
HM628128LFP-8
HM628128LFP-10
HM628128LFP-12
Note:

HM628128P Series

~______ ~(D~P~-3~2)~~__ _

HM628128FP Series

(FP-32D)

Pin Arrangement
Access Time
70ns
85 ns
100 ns
120ns
70 ns
85 ns
100 ns
120ns
70ns
85 ns
lOOns
120ns
70ns
85 ns
lOOns
120ns

Package
NC

600 mil 32-pin
plastic DIP
(DP-32)

Vee

A16

31

A14
A12

WE

4

A7
A6

A13
6

A8

A5

A9

A4
A3

The specifications of this device are subject to change without notice.
Please contact your nearcst Hitachi's Salcs Dept. regarding
specifications.

A11

bE

9
10

Al0

Al

11

CS[

AO

12

1/07

1/00

13

1/06

1/01

14

1/05

1/02

15

1/04

V"

16

1/03

A2

525 mil 32-pin
plastic SOP
(FP-32D)

~15

CS2

(Top View)

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

261

HM628128 Series

Pin Description
Function
Address
Input/output
Chip select 1
Chip select 2
Write enable
Output enable
No connection
Power supply
Ground

Pin Name
AO-Al6

UOO - 1/07
CSl
CS2
WE
OE
NC
Vee
VSS

Block Diagram
A13
A15
A16

':--H~==f-I
---0

Row

Memory MatrIX

Decoder

1/00

o---t+-Q----IH

1/07

o-1'-H--D---IH

Vee

512X2.04B

C510-----1
Read/Wnte Control
WE

0--

OE 0 ' - -_ _ _ _ _ _--'

Function Table
WE

x
x
H
H

L
L
Note:

CSl
H

CS2

OE

x

x

x

L
H
H
H
H

X

L
L
L
L

H
L
H
L

Mode
Not selected
Output disable
Read
Write

DoutPin
High-Z
High-Z
High-Z
Dout
Din
Din

Ref. Cycle

Read cycle
Write cycle (1)
Write £}'cle (2)

x: H orL

•
262

Vee Current
ISB, ISBI
ISB,IsB!
Ice
Icc
Ice
Ice

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM628128 Series

Absolute Maximum Ratings
Item
Voltage on any pin relative to Vss
Power dissipation
Operating temperature
Storage temperature
Storage temperature under bias
Note:

Symbol

Value
-0.5"' to +7.0

Unit

1.0

w

Topr
Tstg
Tbias

V

Oto +70
-55 to +125
-10 to +85

*\. -3.0 V for pulse half-width ::; 30 ns

Recommended DC Operating Conditions ( Ta = 0 to + 70°C)
Item
Supply voltage
Input high (logic I) voltage
Input low (logic 0) voltage
Note:

Symbol
Vee
Vss
VIH
VIL

Min
4.5
0
2.2

Typ
5.0
0

Max
5.5
0
6.0
0.8

-0.3"'

Unit
V
V
V
V

Note

*\. -3.0 V for pulse half-width ::; 30 ns

DC Characteristics ( Ta = 0 to +70°C, Vee = 5 V ± 10%, VSS = 0 V)
Item
Input leakage current

Typ" ,

Max
2

Unit

Ilul

Output leakage current

IILOI

2

IlA

Operating power supply current: DC

Icc

15

30

rnA

Icc,

45

70

rnA

IcC2

15

30

rnA

3

rnA

0.02

2

rnA

"2"2

100"2

IlA

Symbol Min

IlA

Operating power supply current

Standby power supply current: DC

ISB

Standby power supply current (1): DC

Isu!

Output low voltage
Output high voltage

VOL
VOH

Test Conditions
Yin = Vss to Vee
CS1 = VlllOr CS2 = VlLor
OE= VllI or WE = VIL,
VI/o= Vss to Vee
CS1= VIl" CS2 = VOl,
others = Vul/V IL
11/0= ornA
Min cycle, duty = 100%,
CS1 = VIL, CS2 = VIII,
others = VUI/VIL
11/0 = ornA
Cycle tirne = 1 115,
duty = 100%, Iva = 0 rnA
CS1 ::; 0.2 V, CS2 ?Vee- 0.2 V
Vlll?Vee-0.2V, VIl,::;O.2V
CS1 = VllI, CS2 = Vlli
or CS2 = VIL
Vin? 0 V
CS1?Vec-0.2V,
CS2? Vee- 0.2 V or
OV::;CS2::;O,2 V

"--------~-----

0.4
2.4

V
V

10L = 2,1 rnA
1011 = -LO rnA

-------

Notes: *\. Typical values are at Vee = 5,0 V, Ta = +25°e and specified loading.
*2. This characteristics is guaranteed only for L-version.

@HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra POint Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

263

HM628128 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

capacitance ( Ta =25°C, f =1.0 MHz)
Item
Inpul'capacitance
Input/output capacitance
Note:

Symbol
Cin
ClIO

Typ

Min

Max

Unit

8
10

pF
pF

Test Conditions
Yin =OV

This parameteris sampled and not 100% tested.

AC Characteristics (Ta =0 to +70°C, Vee =5 V ± 10%, unless otherwise noted)
Test Conditions
• Input pulse levels: 0.8 V :0 2.4 V
• Input rise and fall times: 5 ns

•
•

Input and output timing reference levels: 1.5 V
Output load: 1 TTL Gate and CL (100pF)
(Including scope & jig)

Read Cycle
Item

Symbol

Read cycle time
Address access time
Chip selection (CSt)
to output valid
Chip selection (CS2)
10 output valid
Output enable (DE)
to output valid
Chip selection (CS1)
to output in low-Z
Chip selection (CS2)
10 output in low-Z
Output enable (OE)
10 output in low-Z
Chip deselection (CS1)
to output in high-Z
Chip deselection (CS2)
to output in high-Z
Output disable (OE)
to output in high-Z
Output hold from
address change

IRe

lAA
teo!

HM628128-7 HM628128-8 HM628128-10 HM628128-12
Min Max
Min Max
Min
Max Min Max
70
100
120
85
70
85
100
120
70
100
120
85

Note

ns
ns
ns

teo2

70

85

100

120

ns

IoE

35

45

50

60

ns

lLZl

10

10

10

10

ns

"I .• 2.·3

lLZ2

10

10

10

10

ns

·1, "'2, "3

t0l2

5

5

5

5

ns

·1. "'2.-3

blZl

0

25

0

30

0

35

0

45

ns

·1. -2, '3

blZ2

0

25

0

30

0

35

0

45

ns

.'. ·2. "'3

10HZ

0

25

0

30

0

35

0

45

ns

*1. "'2, *3

loll

10

10

•
264

Unit

10

10

ns

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300

- - - - - - - - - - - - - - - . - - - - - - - - - - - - - - - HM628128 Series

Read Timing Waveform'4
.c

-:r-

"/

Address

t ..

teol

\""-""-\\\\1'-I

'/

t HZ1

tC02

CS2

IILLI

tlll

/llllf

.\ r\\\'\'\ l'\

tll2

tOE

\\\\\\\\\\\i

tHZ2

tOLl

'/ V//// /

I

tOHZ

Dout

---l--t:::r---=:--::::-----'-I----,

1/02 <>---ttft?--l
1/03 o-t++H>--l
1/04 ~H+H>--l

• FUNCTION TABLE

NOTE:

CS

OE

WE

Mode

Vcc Current

110 Pm

H

X

X

Not Selected

ISB,ISBI

High-Z

Ref. Cycle

-

L

L

H

Read

Icc

Dout

Read Cyele(1)-(3)

L

H

L

Write

Icc

Don

Write Cyele( I)

L

L

L

Write

Icc

Don

Write Cyele(2)

X HorL

• ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Voltage on any Pm RelatIve to VSS

VT

-0.5'1 to + 7.0

V

Power DissipatIOn

PT

1.0

W

'C

Item

Unit

Operating Temperature Range

Topr

oto +70

Storage Temperature Range

T stg

-55 to + 125

'C

Storage Temperature Range Under Bias

T b,as

-10 to +85

'C

NOTE:

*1 V T mm

= -20 V

for pulse width S 10 ns

~HITACHI
270

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 4 2 5 6 Series

• RECOMMENDED DC OPERATING CONDITIONS (T. = 0 to + 70°C)
Item

Symbol

Min.

Typ.

Max.

Vee

4.5

5.0

5.5

V

Vss

0

0

0

V

Supply Voltage

Unit

Input High (Logic I) Voltage

VIH

2.2

-

6.0

V

Input Low (Logic 0) Voltage

VIL

-0.5'1

-

0.8

V

NOTE:

·1 V1L mm =-20VforpulsewKlth:s IOns

• DC CHARACTERISTICS (T. = 0 to +70°C, Vee = 5 V ± 10%, Vss = 0 V)
Symbol

Min.

Typ.'1

Max.

Unit

Input Leakage Current

Ilul

-

-

2.0

p.A

Vee = max.
Y,n = Vss to Vee

Output Leakage Current

IILOI

-

-

2.0

p.A

CS = VIH
VOU! = Vss to Vee

Operating Power Supply Current

lee

-

70

120

rnA

CS = VIL , loul = 0 rnA,
min. cycle

Standby Power Supply Current

IS8

-

30

60

rnA

CS = VIH, min. cycle

IS81'2

-

0.02

IS81 '3

-

-

2.0
0.2

rnA
rnA

oV :S Von :s 0.2 V or

Output Low Voltage

VOL

-

-

0.4

V

IOL=SmA

Output High Voltage

VOH

2.4

-

-

V

IOH = -4.0mA

Item

Standby Power Supply Current (I)

Test Conditions

CS 2: Vee -0.2 V
V,n 2: Vee - 0.2V

NOTES:

*1 TypICal hmltsare aI Vee = 5 0 V, T.. = 25°C amd specified loading
"'2 JP-ver510n
·3 UP-version

• CAPACITANCE (T.

= 25°C, f = IMHz)
Symbol

Mm.

Max.

Unit

Input Capacitance

Con

6

pF

Von =OV

Input/Output Capacitance

CYO

-

11

pF

VI/O = OV

Item

NOTE:

Test Conditions

I ThiS parameter IS sampled and not 100% tested

• AC CHARACTERISTICS (T.
Test Conditions

= 0 to +70°C, Vee = 5 V ±

10%, unless otherwise noted.)

• Input and output timing reference levels: 1.5 V
• Output load: See Figures

• Input pulse levels: Vss to 3.0 V
• Input rise and fall times: 5 ns
Output Load (A)

Output Load (B)
(for IcHZ.IcLZ' tWHZ &

+5V

!ow)

+5V

48012
Dout

0---+,---+
25512

NOTE:

48012
Dout

30pF'

0--;---+
255!2

5pF'

*.ncluchng scope &. JIB

$

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

271

HM624256 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• Read Cycle
Item

HM624256-35

Symbol

Min.

HM624256-45

Max.

Min.

Max.

Unit

Read Cycle Time

tRC

35

-

45

-

Address Access TIme

IAA

-

35

45

ns

Chip Select Access TIme

tACS

-

35

-

45

ns

IeLZ')

ChIp SelecllOn to Output In Low-Z

ns

10

-

10

-

ns

IS

-

23

ns
ns

IoE

-

Output Enable to Output in Low-Z

10LZ ')

0

-

0

-

Chip Deselection to Output In High-Z

IeHZ ')

0

20

0

20

ns

ChIp Disable to Output in High-Z

10HZ')

0

10

0

l5

ns

Output Hold From Address Change

IoH

5

-

5

tpu

0

-

0

-

ns

ChIp Selection to Power Up Time
ChIp Deselectlon to Power Down Time

tpo

-

30

-

30

ns

Output Enable to Output Valid

Read Timing Waveform (1) '1, '2
t.e
Address

OE

tOLZ

Dout

Read Timing Waveform (2) '1, '2, '3, '5
I.e
Address
tOM

to.
Dout

$HITACHI
272

Hitachi America, Ltd .• Hitachi PIa2a • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

ns

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 4 2 5 6 Series

Read Timing Waveform (3) *1, *2, *4, *5

NOTES:

'" I Transition

IS

--9

_l~ICLZ-.&xx-~----

Doul

measured

±

200 mv from steady scate voltage with Load (B) This parameter IS sampled and not 100% tested

"'2 WE IS high for read cycle

"'3 Device

IS

conltnuously selected, CS = VIL

*4 Address valid prior to or cOincident wllh
"'5

DE =

CS tmnsllton low

VIL

• Write Cycle
Symbol

Item

HM624256-35

HM624256-45

Unil

Min.

Max.

Min.

Max

os

Write Cycle Time

Iwe

35

lew

30

-

45

Chip Selection to End of Write

-

40

-

0

-

ns

35

ns

3

-

40

ns

tAW

30

Address Setop TIme

tAS

0

Wnte Pulse Width

twp

30

Wnte Recovery Time

tWR

3

-

Output Disable to Output in High-Z*1

10HZ

0

10

0

15

ns

Write to Output in High-Z*1

tWHZ

0

10

0

15

ns

Data to Write Time Overlap

tDW

20

25

-

ns

Data Hold From Write Time

tDH

0

-

0

-

ns

Output Active From End ofWrite*1

tv.v

0

-

0

-

ns

Address Valid to End of Write

NOTE:

1 TranSibon IS measured

::I::

ns

ns

200 mV from steady state voltage With l.Dad (8)

TIus parameter IS sampled and not 100% tested

Write Timing Waveform (1)
Address

Icw

Dou!
IDW

IDK

DIn

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

273

HM624256Series----------------------------Write Timing Waveform (2) ·6

Address
tew

t WP .,

tow
Dout

laH·'

tDW

Din

NOTES:

*1 TransitIOn

IS

measured ::1:200 mV from high

Impedance

vollage with Load (B) This parameter IS sampled and not 100% teSled

*2 A Write occurs dunng the overlap (twp) of a law CS and a low WE
*3 tWR IS measured from the earher of CS or WE gomg high to the end of wnte cycle
*4 Durmg this penod, I/O pms are m the output state so that the mput signals of the OPPOSite phase to the outputs must not be apphed
*5 If the CS low transition occurs simultaneously With the WE low translbons or after the WE transition, output remam
*6

OE IS contmuously low (00

In

a high Impedance state

= VIL)

*7 DoUT IS the same phase of wnte data of this wnte cycle
*8 DaUT

IS

the read data of next address

*9 If CS IS low dunng Ihls penod. 110 pms are the output state Then the data Input signals of OPPOSite phase to the outputs must not be apphed to them

(OP-28C)

(CP-280)

D

(0 094~~ ~~)

18 17

I8S4 (07Jlmn

3410(1366)
3S 56maK(1 AOOmax)

I

I~

II t:~~114

o 63(0025)MN

~I

~~~O~

~(OOO4)

(SEATING PLANE)

•
274

y,

EJ1I0'""'0S0)1""

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM624257 Series
4-Bit CMOS Static RAM

Under Development

HM624257 SERIES
262144-WORD x 4-81T HIGH SPEED CMOS STATIC RAM
The Hitachi HM624257 is a high speed 1M static RAM
organized as 256-kword x 4-bit. It realizes high speed access
time (35/45 ns) and low power consumption, employing the
advanced CMOS process technology and high speed circuit
designing technology. It is most advantageous for the field where
high speed and high density memory is required, such as the
cache memory for main frame or 32-bit MPU.
The HM624257, packaged In a 400-mil plastic SOJ IS available
for high density mounting.

,

• FEATURES
• Single 5 V supply and high density 32-pin package (SOJ)
• High speed: Access time 35/45 ns (max.)
• Low power dissipation
Active mode: 350 mW (typ.)
Standby: 100 p.W (typ.)
• Completely static memory:
No clock or timing strobe required
• Equal access and cycle time

(CP-32D)

• Directly TIL compatible: A" inputs and outputs

• ORDERING INFORMATION
PIN ARRANGEMENT
Type No.

Access Time

Package

35 ns
45 ns

400 mil
32-pin
Plastic SO]
(CP-32D)

HM624257JP-35
HM624257JP-45
HM624257UP-35
HM624257UP-45

35 ns
45 ns

Top View

• PIN DESCRIPTION
Pin Name

Function

NC

Vee

Ao

A17

Al

A16

A2

A1S

A3
A4

A14

As

A12

A13

Ao-AI7

Address

A6

All

11-4
11-04

Data Input

A7

NC

CS

Chip Select

Data Output

WE

Write Enable

Vee

Power Supply

Vss

Ground

As

11

Ag

12

Al0

01

14

02

13

03

CS

04

Vss

WE

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

275

HM624257 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • BLOCK DIAGRAM
AO

Al
A2

_Vee

AJ

-Vss
Memory Arrray

A4

256X 1,024

A5

AS

A7
A8

01

04

cs
wE~-1~~------------------------------------~

• ABSOLUTE MAXIMUM RATINGS
Item

UOIt

Symbol

Value

Voltage on any Pin Relative to VSS

VIn

_0.5" to + 7.0

V

Power DissipatIon

PT

10

W

o to

·C

+70

Operating Temperature Range

Topr

Storage Temperature Range

T stg

-55 to + 125

·C

Storage Temperature Range Under Bias

T b1m•

-10 to +85

·C

*1 V

NOTE:

In

mm = -2 0 V for pulse width :5 10 ns

• FUNCTION TABLE
CS

WE

Mode

Vee Current

Dout Pin

H

X

Not Selected

IS8 , IS81

High-Z

-

L

H

Read

Icc

Dout

Read Cycle(' )-(2)

L

Write

Icc

High-Z

Write Cycle(1 H2)

L
NOTE:

x

Ref. Cycle

H or L

.HITACHI
276

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - HM624257 Series
• RECOMMENDED DC OPERATING CONDITIONS (T. = 0 to + 70°C)
Item

Symbol

Min.

Typ.

Max.

Vee

4.5

5.0

5.5

V

Vss

0

0

0

V

Supply Voltage

Umt

Input High (Logic I) Voltage

V IH

2.2

-

6.0

V

Input Low (Logic 0) Voltage

V IL

-0.5'1

-

0.8

V

NOTE:

*1 V1L mm == -20 V for pulse width

~

10 ns

• DC CHARACTERISTICS (T. = 0 to +70°C, Vee = 5 V ± 10%, Vss = 0 V)
Symbol

Min.

Typ.'1

Max.

Umt

Input Leakage Current

IILlI

-

-

2.0

p.A

Vee = max.
VIR = Vss to Vee

Output Leakage Current

IILOI

-

-

10.0

p.A

CS = V IH
VIIO = Vss to Vee

Operatmg Power Supply Current

Icc

-

70

120

rnA

CS = V IL , 11/0 = 0 rnA,
mm. cycle

Standby Power Supply Current

ISH

-

30

60

rnA

CS = V lH , mm. cycle

Standby Power Supply Current (I)

Isol

-

0.02

2.0

rnA

Item

Test Conditions

CS;;,Vee -0.2V
:s VIR :s 0.2 V or
VIR ;;, Vee - 0.2V

oV

Output Low Voltage

VOL

-

-

0.4

V

IoL = 8 rnA

Output High Voltage

VOH

2.4

-

-

V

IoH = -4.0 rnA

NOTE:

1 Typical hmll'i are at Vee = 5 0 V. T.

=

+2SoC and specified loadmg

• CAPACITANCE (T. = 25°C, f = IMHz)
Symbol

Min.

Max.

Unit

Input Capacitance

Item

C IR

-

6

pF

VIR =OV

Output Capacitance

Cout

-

II

pF

VOU! = OV

NOTE:

Test Conditions

I This parameter IS sampled and not 100% tested

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

2n

HM624257 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • AC CHARACTERISTICS (Ta = 0 to +70°C, Vee = 5 V ± 10%, unless otherwise noted.)

Test Conditions
• Input and output timing reference levels: 1.5 V
• Output load: See Figures

• Input pulse levels: Vss to 3.0 V
• Input rise and fall times: 5 ns
Output Load (A)

Output Load (B)
(for tCHZ' tClZ' tWHZ &

5V

tow)

5V
4800
4800

Dout

255Q

~

Dou!

30pF-

255Q

~i>

5pF·

7/7NOTE:

7/7"

*Includmg scope & Jig

• Read Cycle
HM624257-35
Item

HM624257-45

Symbol

VOlt
Mm.

Max.

Min.

Max.

Read Cycle Time

tRC

35

-

45

-

ns

Address Access Time

tM

-

35

-

4S

ns

ChIp Select Access TIme

tAcs

-

35

Output Hold From Address Change

IoH

S

5

45

ns

-

ns

ChIp Selection to Output in Low-Z

tLZ 'I

S

-

5

-

ns

ChIp DeselectlOn to Output in Hlgh-Z

tHZ 'I

0

20

0

20

ns

Chip Selection to Power Vp Time

tpu

0

-

0

-

ns

ChIp Deselecllon to Power Down TIme

tpD

-

-

30

ns

NOTE:

I Tran.. \tIon I~ mea~urcd ± 200 mV from ..teady voltage With Load (B)
Th.\ parameter .'> ~ampled and not 100% te .. ted

•
278

HITACHI

Hitachi America, ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - HM624257 Series
Read Timing Waveform (1)

'1, '2
I"

Address

10H

Dout

Data Vahd

Read Timing Waveform (2) '1, '3

"e
I"
I"

Data V.lid
Doul
High Impedance

High Impedance

Vee supply

---------------+r------------------------~--~
Icc

50%

currC'nt
NOTES:

*I

WE IS high for read cycle

*2 Device

IS

contmuously selected. CS = VIL

*3 Address vahd pnor to or comcldent With

CS transition low

• Write Cycle
HM624257-35
Item

Symbol

HM624257-45
Unit

Mm.

Max.

Min.

Max.

twe

35

-

45

lew

30

-

40

-

ns

Chip Selection to End of Write
Address Valid to End of Write

tAW

30

-

40

-

ns
ns

Write Cycle Time

ns

Address Setup Time

tAS

0

-

0

-

Wnte Pulse Width

twp

30

-

35

-

ns

Write Recovery Time

tWR

3

3

tDW

20

-

ns

Data Valid to End of Write

-

Data Hold Time

tDH

3

-

3

-

ns

Write Enabled to Output in Hlgh-Z

twz 'I

0

15

0

20

ns

Output Active From End of Wnte

!ow'1

5

-

5

-

ns

NOTE:

I TranSition IS measured
This parameter

IS

ns

*' 200 m V from steady state voltage With Load (8)

sampled and not 100% tested

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

279

HM624257 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - Write Timing Waveform (1) (WE Controlled)

Address

cs

WE

Dm

Duut

Write Timing Waveform (2) (CS Controlled)
lwe

Address

I..

Iwn"J

lew

WE

I,.
Data

Dm

In

Valid

Duu!

NOTES:

*I

A wrlle occur~ dUring the overlap of a low

CS and a low WE

*2 tWR I~ mea~ured from the earlier of CS or WE gomg high to the end of write cycle
*3 If the

CS low tramilion occurs Slmult.l.neou~ly

with the WE low trdn<;ltlOnl> or after the WE trao!>ltlOn, output buffer., remain

In

a high Impedance "tate

*4 DOUT 1<; the ,>arne pha<;e of write data of Ihl'> write cycle

$
280

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - HM624257 Series

• Low Vee Data Retention Characteristics (T. = 0 to

+70·C)

Symbol

Min

Typ.

Max.

Unit

Vee for Data Retention

VDR

2

-

-

V

Data Retention Current

icCDR

-

2

100'1

/lA

!cDR

0

-

tR

5

-

ns

-

ms

Item

Chip Deselect to Data Retention Time
Operation Recovery Time
NOTE:

lest Conditions
Cs'",Vcc -0.2V,
Von '" Vcc-0.2Vor
V :S VIn :S 0.2 V

o

'I Vcc=30V

Low Vee Data Retention Timing Waveform
vu-------~
4.5V--------

cs _____J

w ____________________________________________ _

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

281

HM624257 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - (CP-32D)

(0 094~~ ~?l)

2071(0815)

2108(0830)ma.

o 63(0

32

025)MIN

::;~~9~J\i!~J\i!iroJWOOQ~1~

50,0(0004 1

,SEATiNG Pl.AN[\

----U.--

o 43±O 10
.0 OI7±O 0041

uJ.L:'

~

3 S±D 26

-&~!_~ o~o))

.HITACHI
282

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM66204 Series---

Maintenance Only

131072-word x 8-bit High Density CMOS Static RAM Module
The HM66204 is a high density 1 M-bit static RAM module
consisted of 4 pieces of HM62256FP/LFP products (SOP type
256k static RAM) and a HD74HC138FP equivalent product (SOP
type CMOS decoder logic).
An outline of the HM66204 is the standard 600 mil width 32
pin dual-in-line package. Its pin arrangement is completely compatible with 1 M-bit monolithic static RAM.
The HM66204 offers the features of low power and high speed
by using high speed CMOS devices. And, the HM66204 makes
high density mounting possible with no surface mount technology.
These features make the HM66204 ideally suited for high
density compacted memory systems.

(DM-32A)

Pin Arrangement
Features
• High density 32 pin DIP
Mounting 4 pcs. of 256k static RAM (SOP; HM62256FPI
LFP) and CMOS decoder logic (SOP; HD74HC138FP
equivalent)
• Pin compatible with 1 M monolithic static RAM
•
•
•
•

•
•

High speed
- Fast access time 120 ns/150 ns (maximum)
Equal access and cycle time
Completely static RAM
- No clock or timing strobe required
Low power standby and low power operation
- Standby
40 jJ.W (typical) (L-version)
- Operation
50 mW(typical) (f = 1 MHz)
Common data input and output, three state outputs
Capable of battery backup operation (L-version)

Ordering Information
Part No.

Access Time

Package

Pin Description

120 ns
HM66204-12
HM66204-15
150 ns
- - - - - - - - - - - - - - 600-mil 32-pin DIP
HM66204L-12
120 ns
150 ns
HM66204L-15

Absolute Maximum Ratings
Symbol
Item
Voltage on any pin relative to Vss
VT
Topr
Operating temperature range
Tstg
Storage temperature range
Storage temperature range under bias
Tbias
Power dissipation
PT

Rating
-0.5 to +7.0
o to +70
-55 to +125
-10 to +85
1.0

Pin Name

Unit
V

°c
°c
°c

AO- A16
1/01 - 1/08
CS
OE
WE

Vee

Vss
NC

Function
Address
Input/Output
Chip Select
Output Enable
Write Enable
Power Supply
Ground
No Connection

W

~HITACHI
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283

HM66204 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Block Diagram
AO

1/01

*1 RAM :-';o]-\Jo4 IIM62256FI'I.f
wd"r H1J74H( 1381- P ur

*

I" '>t.lUllalenl

Mode Selection
Mode
Not selected (Power down)
Read
Write

CS
H
L
L
L

WE

OE

I/O

X

X

High-Z

H
L
L

L
H
L

Dout
Din
Din

Current
ISB,ISBI
ICC
ICC
ICC

Note
Read cycle (1) - (3)
Write cycle (1)
Write cycle (2)

Note) X = Don't care (H or L)
Electrical Characteristics
Recommended DC Operating Conditions (Ta =_0_t_o_+_7_0_0_C-'-)__________________________
Symbol
Min
Parameter
Typ
Max
Unit
Notes
Supply voltage

Vee
Vss

Input high (logic I) Voltage
Input low (logic 0) Voltage

4.5
0
3.85*'
2.2

5.0
0

-0.5

5.5
0
6.0
6.0
0.8

V
V
V
V
V

A15, A16, CS
Others except A15, A16, CS

Note) *1. VIH min is determined by Vee x 0.7.
DC Characteristics (Ta = 0 to +70°C, VCC = 5V ± 10%, VSS = OV)
Parameter
Symbol Min Typ'l
Input leakage current

Output leakage current

IIUI

Max
8
2

Unit

Test Conditions

/JA
/JA

Vln = Vssto Vee
Vtn - Vss to 3.5V

8

/JA

CS = V/H or OE = V/H
VI/O= Vssto Vee

2

/J A

IILOI

cs = V/H or OE = V/H
VI/O= VSS to 3.5V

ICC

10

25

rnA

CS= VIL
11/0 = OmA

Average operating power supply
current (I)

ICCI

37
35

80
80

rnA

MIN. cycle duty = 100%
11/0 - OmA

Average operating power supply
current (2)

lee2

10

15

rnA

CS = VIL, VlH = Vec
VIL = OV, 11/0 = OmA
f= IMHz

Standby power supply current: DC

ISB

2

12

rnA

8

400

/JA

Operating power supply current: DC

Standby power supply current
(1): DC
Output low voltage .
Output high voltage
Note) 'I. Typical values are at Vee

ISBI

0.16
8
rnA
V
VOL
0.4
2.4
V
VOH
=5.0V, Ta= +2Soe and specified loading .

•
284

Notes

-12
-15

CS = VlH
CS ~ Vee-0.2V
HM66204L
AI5 ·A16 ~ Vee - 0.2V Series
or OV :::;; A15· AI6 :::;; 0.2V
IOL = 2.1 rnA
IOH = -1.0 rnA

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 6 2 0 4 Series
Capacitance (Ta = 25°C, f = I MHz)

-- - - - - - -

-- - - --- - - - - - - - - - - - - -

Parameter

Inpu-'-ca-pa-citanc~

Input/outPut capacitance

Symbol
Cin

Min

Typ

CliO

Max
45

Unit
pF

Test Conditions
Yin = OV

50

pF

VIIO - OV

~~~~~--~~~------~~~--------~---------­

Note) This parameter is sampled and not 100% tested.

AC Characteristics (Ta = 0 to +70°C, VCC = 5V ± 10%, unless otherwise noted)
AC Test Conditions
• Input pulse levels:
O.BV to 4.0V ... CS, A15, A16
O.BV to 2.4V ... Other pin except
A15, A16

• Input rise and fall times: 5 ns
• Input and output timing reference level: 1.5V
• Output load: 1 TTL Gate and C L (100pF)
(Including scope & jig)

CS",

Read Cycle
HM66204-12
HM66204-15
Unit
max
min
min
max
Read cycle time
120
150
ns
tRC
120
150
ns
Address access time
tAA
-------120
150
ns
Chip select access time
tACS
ns__
60
70 _ _ _ _
Output enable to output valid_ _ _ _ _ _tOE
--=--='--___---:--:,---_______
-:--=-_ _ _ _
Output hold from address change
10
10
ns
tOH
10
Chip selection to output in low Z
10
ns
tCLZ
5
ns
5
tOLZ
Output e_~~ble to out~ut!_'!.low Z
ns
Chip deselection to output in high Z
40
0
50
0
tCHZ
ns
Output disable to output in high Z
40
0
SO
0
tOHZ
Symbol

Parameter

Read Cycle Timing No.1 ·1
IRC

Address
IAA

IDE
IOLZ

I-----IACS

--+---i

ICLZ

Dout

Read Cycle Timing No. 2. 1 ,.2,,4
IRC

Address
IOH

IAA

IOH

Dout

Data Valid

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

285

HM66204

Series----------------------------------

Read Cycle Timing No. 3.1 • ·3, "4

IC//Z
/CLZ

Dout

Data Vahd

Notes) *1. WE is high for read cycle.
·2. Device is continuously selected, ES = VIL.
·3. Address should be valid prior to or coincident with CS transition low.
*4. Cffi= VIL.

Write Cycle
Parameter

Symbol

Write cycle time
Chip selection to end of write
Address valid to end of write
----_.
Address setup time
Write pulse width
Write recovery time
Write to output in high Z
Data to write time overlap
Data hold from write time
Output disable to output in high Z
Output active from end of write

Write Cycle Timing No.1

HM66204·12
min
max
120
100
100
0
90
5
0
40
50

HM66204-15
min
max
150
120
120
0
110
5

------"

twc
tcw
tAW
tAS
twp
tWR
tWHZ
tow

0
0
5

tOH
tOHZ
tow

0
60
0
0
5

40

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

50

50

(Of Clock)

we

) V--

Address
)

t--tWR*~

LL/'

\\1\ t---tAS1\\\ \ " \
tOHZ*3
Dout

Din

~

lew

I

///////

tAw

\ \ \ \\,

twp *1

\\\\\\\\\\

//////////

tDW
/

\. \. 1\

tDH

XX

~HITACHI
286

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 6 2 0 4 Series
Write Cycle Timing No. 2*5 (CE Low Fixed)

lwe

Address
lew

lAW

lwp*

WE

1

IOH

low
Dout
IDW

tDH

Din

Notes) *1. A write occurs during the overlap (twp) of a low CS and a low WE.
*2. tWR is measured from the earlier of CS or WE: going high to the end of write cycle.
*3. During this period, 1/0 pins are in the output state.
The input signals of opposite phase to the outputs must not be applied.
*4. If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition,
outputs remain in a high impedance state.
*5. OE is continuously low. (OE = VIL>
*6. Dout should be held in phase of the written data during this write cycle.
*7. D out is the read data of next address.
*S. If CS is low during this period, 1/0 pins are in the output state. The input signals which are opposite to the
output level should not be applied to 1/0 pins.

Low Vee Data Retention Characteristics (Ta =O°C to +70°C)
Data retention characteristics is guaranteed only for L version.
Parameter

Symbol

Vee for data retention

Min

Typ

Max

2.0

Da ta retention current

ICCDR

Chip deselect to data retention time

tCDR

200

o

Operation recovery time

Unit

Test Conditions

v

CS L Vcc-o.2V
Al5, Al6 L VCC-0.2V
or Al5, Al6 ~ 0.2V

/JA

VCC= 3.0V, CS L 2.SV
Al5 •Al6 2'. 2.SV or
OV ;£ A15· Al6 ;£ 0.2V

ns
ns

See retention waveform

Note) *\. tRC = Read Cycle Time.

Low Vee Data Retention Waveform
Vee

VDR0/;2.0V

cs;;;: l'ec-O.2V
ov --- --------------------------------------------------------•

HITACHI

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287

HM66204 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Package Dimensions; Unit: mm (inch)

47.50(1.870 )
C48.26max. (1.900max.))

2.54(0.100)
_+----+-.,:;4.""70(0.185)
C5.08max. (O']'OOmax.»)

1.02(0.040)
0.35-0.59
(0.014-0.023)

I~~HI\

q

~

'/

'A"
'tl

IY
!.J

"
0.20-0.36
(0.008-0.014)
15.24(0.600)

•
288

~

- 0 - -15-

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

HM63921-20/25/35 -

Product Preview - - - - - - - -

2K x 9-Bit CMOS Parallel In-Out FIFO Memory
• DESCRIPTION
The HM63921 is a First-In, First-Out memory that utilizes a high
performance static RAM array with internal algorithm that controls,
monitors and declares status of the memory by empty flag, full flag
and half-full flag, to prevent data overflow or underflow.
Expansion logic warrants unlimited expansion capability in width
and depth. Both read and write are independent from each other and
their corresponding pointers are designed to select the proper locations out of the entire array serially without address information to
load or unload data.
Data is toggled in and out of the device through the use of the write
enable (W) and read enable (A) pins. The device has a read/write
cycle time of 30/35/45ns. Organization of HM63921 provides a 9-bit
data bus. the ninth bit could be used for control or parity for error
checking at the option of the user. The HM63941 is fabricated using
the Hitachi CMOS 1.3micron technology. The device is available
in DIP.
•
•
•
•
•
•
•
•
•
•
•

FEATURES
First-In, First-Out Dual Port Memory
2k x 9 Organization
Low-Power CMOS 1.3micron Technology
Asynchronous and Simultaneous Read and Write
Fully Expandable in Depth and/or Width
Single 5V (± 10oAl) Power Supply
Empty and Full Warning Flags
Half-Full Flag
Access Time .................................20/25/35ns
Package ................. 300-mil 28-pin Plastic DIP Package

(DP-28NA)
• PIN ARRANGEMENT

W

Vee

D8
D3
D2
D1
Do

D4
D5
D6
D7

FURT
RS
EF
XO/HF

Xi
FF
00
01
02
03
08

07
06
05
04

R

Vss
• ORDERING INFORMATION
Type Name

Access Time

Package

HM63921P-20
HM63921P-25
HM63921P-35

20ns
25ns
35ns

300-mil 28-pin
Plastic DIP
(DP-28NA)

$

tTop View)
• PIN DESCRIPTION
Pin Name

Function

DO-Dg

Data Inputs

RS

Reset

W

Write Enable

R

Read Enable

FL

First Load

RT

Retransmit

XI

Expansion-In

XO

Expansion-Out

HF

Half-Full Flag

FF

Full Flag

EF

Empty Flag

Qo-Qg

Data Outputs

HITACHI

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289

HM63921-20/25/35 - - - - - - - - - - - - - - - - - - - - - - - - - -

• BLOCK DIAGRAM

00 01 02 03 D4 0506 0708

W

Write
Pointer

Row
Decode

Memory Array
2048 X 9

Row

Read

Decode

Pointer

Column Decoder

co 01 Q2 Q3 Q4 05 06 07 08

•
290

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - HM63921·20/25/35
• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Rating

Terminal Voltage( l)

VT

-0.5(2) to +7.0

V

Power Dissipation

PT

1.0

W

Operating Temperature

Top,

Storage Temperature

Ts~
T blas

Storage Temperature Under Bias
NOTES:

o to

Unit

°C

+70

-55 to + 125

°C

-10 to +S5

°C

I. Relative to Vss.

2. -3.5V for pulse WIdth :s IOns.
• Recommended DC Operating Conditions (T. = 0 to +70°C)
Parameter

Symbol

Min.

Typ.

Max.

Unit

Vee

4.5

5.0

5.5

V

Vss
V IH

0

0

0

V

2.2
-0.5(1)

-

6.0

V

O.S

V

Supply Voltage
Input Voltage
NOTE:

V1L

I. -3.0V for pulse width

:S

IOns.

• DC CHARACTERISTICS (T. = O°C to +70°C, Vee = 5V ± 10%)
Parameter

Symbol

Test Conditions

Min.

= 5.5V, Vm = OV - Vee
= V1H , VOUI = OV - Vee

Input Leakage Current

IILlI

Vee

-

Output Leakage Current

IIwl

R

-20

Operating Power Supply Current

Average Operating Current

Icel

-25
-35

= W = RS = FLIRT = V1H

ISBl

R

All inputs

Output High Voltage

ISB2
VOH

Output Low Voltage

VOL

Standby Power Supply Current

~

-

Vee -0.2Vor::;; Vee

= -4mA
IOL = SrnA

2.4

IoH

-

Typ.

Max.

Unit

-

2

p.A

2

p.A

-

120

rnA

110

rnA

-

100

rnA

10

rnA

-

I

rnA

-

-

V

0.4

V

• CAPACITANCE (T. = 25°C, f = lMHz)
Symbol

Test Conditions

Typ.

Max.

Input Capacitance

Parameter

Cm

Vm = OV

-

6

pF

Output Capacitance

COUI

VOUI = OV

-

10

pF

NOTE:

Unit

1. This parameter is sampled and not 100 % tested.

• AC CHARACTERISTICS (Ta

= O°C to 70°C, Vee = 5

± 10%)

• Test Conditions
• Input Pulse Levels: Vss to 3.0V
• Input and Output Timing Reference Level: 1.5V

• Input Rise and Fall Times: 5ns
• Output Load: See Figure

+5V

DOU~ 480n
255n L j 3 0 pF •
Output Load
*Inc1uding scope and jig.

•

HITACHI

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291

HM63921·20/25/35 - - - - - - - - - - - - - - - - - - - - - - - - - - -

• Read Cycle
Parameter
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
Read Low to DB Low Z
Read High to DB High Z
Data Valid from Read High
Read Pulse Width After Empty Flag High
Write High to DB Low Z
(Read Data Flow Through Mode)
NOTE:

Symbol
tRC
tA
tRR
tRPW
tRLZ(1)
tRHz(1)
toH
tRPE
tWLZ(1)

HM63921-20
Min.
Max.
30
20
10
20
5
15
3
20
3

-

HM63921-25
Min. Max.
35
25
10
25
5
15
3
25
3

-

HM63921-35
Min. Max.
45
35
10
35
5
20
3
35
3

-

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

I. tRLZ, tRHZ and tWLZ are sampled and not 100% tested.

• Write Cycle
Parameter

Symbol

Write Cycle Time

twc

Write Recovery Time

HM63921-20
Min.
Max.
30
-

-

10
25

-

15

0

-

0

-

20

-

25

-

10

tWR
twpw

20

tDS

10

Data Hold Time

tDH

Effective Write Pulse Width After
Full Flag High

tWPF

Write Pulse Width
Data Setup Time

HM63921-25
Min.
Max.
35
-

HM63921-35
Max.
Min.
45
10

Unit
ns
ns

35
20

-

ns

-

ns

5

-

ns

35

-

ns

• Reset Cycle
Parameter

Symbol

Reset Cycle Time

tRSC
tRs

Reset Pulse Width

HM63921-20
Min.
Max.
30
20

Reset Setup Time

tRsS

0

-

Reset Recovery Time

tRSR

10

-

HM63921-25
Min. Max.
35
25
0
10

-

HM63921-35
Min. Max.
45
35

Unit
ns
ns

0

-

ns

10

-

ns

• Retransmit Cycle
Parameter

Symbol

Retransmit Cycle Time

tRTC
tRT

Retransmit Pulse Width
Retransmit Setup Time

tRTS
tRTR

Retransmit Recovery Time

•
292

HM63921-20
Min.
Max.
30
20

-

0
10

-

-

HM63921-25
Min. Max.
35
20
0

-

10

-

HM63921-35
Min. Max.
45
-

Unit
ns

35

-

ns

0

-

10

-

ns
ns

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - HM63921-20/25/35

• Flag Timing
Parameter
Reset to Empty Flag Low

Symbol

HM63921-20

HM63921-25

HM63921-35

Min.

Min.

Max.

Min.

Max.

Max.

Unit

tEFL

-

20

-

25

-

35

ns

Reset to Full Flag High

tFFH

-

20

-

25

-

35

ns

Reset to Half-Full Flag High

tHFH

-

30

-

35

-

45

ns

Read Low to Empty Flag Low

tREF

-

20

-

25

-

35

ns

Read High to Full Flag High

tRFF

-

20

-

25

-

35

ns

Write High to Empty Flag High

tWEF

-

20

-

25

-

35

ns

Write Low to Full Flag Low

tWFF

-

20

-

25

-

35

ns

Write Low to Half-Full Flag Low

tWHF

-

30

-

35

-

45

ns

Read High to Half-Full Flag High

tRHF

-

30

-

35

-

45

ns

• Expansion Timing
Parameter
Expansion in Setup to Write or Read
Expansion in Recovery Time
Expansion in Pulse Width

HM63921-20

HM63921-25

HM63921-35

Min.

Max.

Min.

Max.

Min.

tEFL

-

15

-

20

-

30

ns

tRFF

-

15

-

20

-

30

ns

-

10

-

10

-

ns

Symbol

Max.

Unit

tWHF

10

Expansion Out High Delay From Clock

tREF

10

-

10

-

10

-

ns

Expansion Out Low Delay From Clock

tRFF

10

-

10

-

15

-

ns

~HITACHI
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293

HM63921-20/25/35 - - - - - - - - - - - - - - - - - - - - - - - - - - SIGNAL DESCRIPTIONS

tions, until one or more write operations are completed, or FIFO is set to retransmit.

Inputs
• Reset (RS)
The device is reset whenever RS input is taken to
low state, for minimum reset pulse width. When
device is reset, both read and write pointers are
set to the first location. A reset cycl~ is required
after power on. Both read enable (R) and write
enable (Vii) inputs must be in the high state dur.!!!g
reset. Empty!@g (EF) will go low and full flag (FF)
and half-full (HF) will go high during reset cycle.
• Write enable (Vii)
_
Write cycle is initiated at the falling edge of W, if
the full flag (FF) is not set, provided that data setup and hold time requirements relative to the rising edge of (Vii) are met. Data is stored in the device sequentially and independently of any simultaneous read operation. To inhibit further write operations and prevent internal data overflow full
flag (FF) will go low.
• Read enable (Fi)
_
Read cycle is initiated at the falling edge of R, if
the empty flag (EF) is not set. Data is accessed on
a first-in, first-out basis independently of simultaneous write operation. As read enable (Fi) goes
high, all outputs will return to high impedance
state, till next read operation. After the last data
has been read from the FIFO, the empty flag (EF)
will go low, preventing further read operations with
0..!ili'ut kept in high impedance state. Empty flag
(EF) will go high during a valid write cycle (twEF),
thereafter a valid read can start.
• First load/retransmit (FLIRT)
For depth expansion mode, this pin is grounded to
indicate that it is the first device, while this pin of
the rest of devices should connect to Vee for correct operation. In single device mode, this pin resets the read pointer to the beginning of the FIFO
memory, therefore data can be reread from the
beginning. Both R and Vii should be kept high
while RT is taken low.
• Expansion-in (Xi)
For single device mode expansion-in (Xi) is
grounded. For depth expansIOn mode,
expansion-in @ should be connected to
expansion-out (XO) of previous device.
• Data In (Do to Os)
Data inputs for 9-bit wide data.

• Expansion-out (XO)/Half-full flag (HF)
This output has dual functionality depending how
it is used. In de..e!!.l expansion configuration
expansion-out (XO) is connected to next
expansion-in (Xi). The expansion-out (XO) of the
last FIFO is connected to the expansion-in (Xi) of
the first FIFO. In this way the first FIFO indicates
the next FIFO that it will receive the next data. In
like manner, any FIFO which becomes full will indicate the next FIFO that it will receive the next data.
The second function of this output is in stand
alone and/or parallel expansion configurations to
indicate the system user that the FIFO is almost
full.
• Data outputs (0 0 to as)
Data outputs for 9-bit wide data. Th~se outputs
are in high impedance state when R is in high
state.
VARIOUS OPERATIONS MODE
_
• Single device mode
If only one FIFO is used, the expansion-in (XI) pin
should be grounded.
• Width expansion mode
Width expansion by 9-bit increments may be
achieved when separately paralleling the data inputs and the data outputs. In this configuration
any flags of any device may be used. To avoid
output contention of the flags for short periods of
time, the flag outputs should not be wired together.
• Depth expansion mode
Multiple of FIFOs could provide multiple of 2k x 9
as (N) x (2k) by 9-bits wide, where N is the number of FIFOs connected in depth expansion
mode.
The following arrangement must be provided.

1. First load (FL) of the first FIFO should be connected to ground.
2. All other (FL) should be connected to Vee.
3. Connect the expansion-out (XO) of each FIFO
to e~nsion-in (Xi) of the...!!ext FIFO serially
and XO of the last FIFO to XI of the first FIFO.

4. Connect all the empty flag (EF) t.Qgether to OR
gate and connect all the full flag (FF) together to
OR gate to obtain two separate valid empty flag
(EF) and full flag (FF) outputs.

Outputs
• Full Flag (FF)
The full flag (FF) will go low when FIFO is full,
inhibiting further write operations until one or
more read operations are completed or the FIFO
is reset.

5. (RT) and (AF) will not be available in this mode.
• Compound expansion mode
Combination of width and depth expansion
modes will provide larger FIFO arrays.

• Empty flag (EF)
The empty flag (EF) will go low when the FIFO
becomes empty, inhibiting further read opera·

~HITACHI
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- - - - - - - - - - - - - - - - - - - - - - - - - - - HM63921-20/25/35
• TIMING WAVEFORM

• Read Cycle

tRPw

00-08

Data out valid

Data out valid

• Write Cycle

twe
twpw

W

~

)

'"

twpw

tWR

tos

V

~

tOH

:< Data in valid;-

Do-D8

/IL

1'\
los

tOH

KData in valid)

• Reset Cycle

tRse

R,W

tRSR

EF

FF

XO/HF
NOTES:

1.

W = R = VIH during reset.

2.

tRSC

=

tRST. tRSR·

.HITACHI
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295

HM63921-20/25/35 - - - - - - - - - - - - - - - - - - - - - - - - - - -

• Retransmit Cycle
tRTe
tRT

FURT

'\

./

V

tRTS

~

R,W

'!>K

/f

tRTR

• Full-Flag Cycle (From Last Write to First Read)

Last write

Additional reads

First Read

First Read

~

R
W

FF

• Empty-Flag Cycle

(From Last Read to First Write)
Last Read

First Read

First Read

W

R

EF

00-08

@HITACHI
296

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- - - - - - - - - - - - - - - - - - - - - - - - - - - HM63921-20/25/35

• Half-Full Flag Cycle

Write=Read+ 1023

,

Write=Read+ 1023

Write=Read+ 1024

I"..
tRHF

~

tWHF

"'~

/

V

• Read Data Flow Through Mode

Do-D8

w

EF

00-08

•

HITACHI

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297

HM63921-20/25/35 - - - - - - - - - - - - - - - - - - - - - - - - - - -

• Write Data Flow Through Mode

FF

Data in valid

00-08

00-08

• Expansion Out Cycle 1

Read from last

~~PhYSical address

~

-l~J
tXOL

txoH

@HITACHI
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- - - - - - - - - - - - - - - - - - - - - - - - - - - - HM63921-20/25/35

• Expansion Out Cycle 2

(Read Data Flow Through Mode)
Write to last physical address

------------------------~

• Expansion Out Cycle 3

,----------------------

(Write Data Flow Through Mode)
Read from last physical address

------------------------~

~---------------------

w
FF

~HITACHI
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299

HM63921-20/25/35 - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• Expansion In Cycle

tXI

tXIR

tXOL

w
tXIS

Read from first
physical address

~HITACHI
300

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HM63941-25/35/45 -

Preliminary

4K x 9-Bit CMOS Parallel In-Out FIFO Memory
• DESCRIPTION

The HM63941 is a First-In, First-Out memory that utilizes a high
performance static RAM array with internal algorithm that controls,
monitors and declares status of the memory by empty flag, full flag
and almost-full flag, to prevent data overflow or underflow.
Expansion logic warrants unlimited expansion capability in width
and depth. Both read and write are independent from each other and
their corresponding pointers are designed to select the proper locations out of the entire array serially without address information to
load or unload data.
Data is toggled in and out olthe device through the use of the write
enable (W) and read enable (Fi) pins. The device has a read/write
cycle time of 35/45/60ns. Organization of HM63941 provides a 9-bit
data bus. the ninth bit could be used for control or parity for error
checking at the option of the user. The HM63941 is fabricated using
the Hitachi CMOS 1.3micron technology. The device is available
in DIP.
•
•
•
•
•
•
•
•
•
•
•

FEATURES
First-In, First-Out Dual Port Memory
4k x 9 Organization
Low-Power CMOS 1.3micron Technology
Asynchronous and Simultaneous Read and Write
Fully Expandable in Depth and/or Width
Single 5V (± 10%) Power Supply
Empty and Full Warning Flags
Almost-Full Flag
Access Time .................................25/35/45ns
Package ..............................28-pin DIP Package

(DP-28NA)
• PIN ARRANGEMENT

W
Ds
D3
D2
D1
Do

Vee
D4
D5
D6
D7
FLIRT

X1

RS

FF

EF

Qo
Q1
02
03
Os
VSS

Q7
06
05
04

XO/AF

R

• ORDERING INFORMATION

Type Name

Access Time

Package

HM6394I P-25
HM63941P-35
HM63941P-45

25ns
35ns
45ns

28-pin Plastic DIP

(Top View)
• PIN DESCRIPTION

Pin Name

Function

Do-Ds

Data inputs

RS

Reset

W

Write enable

R

Read enable

FL

First load

RT

Retransmit

XI

Expansion-in

XO

Expansion-out

AF

Almost-full flag

FF

Full flag

EF

Empty flag

Qo-Qs

Data outputs

~HITACHI
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301

HM63941-25/35/45 - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS
Symbol
VT

Rating
-0.5(2) to + 7.0

Unit

Terminal Voltage(1)

Item
Power Dissipation

PT

1.0

Operating Temperature
Storage Temperature

Top,
T stg

W
°C

-55 to + 125

°C

Storage Temperature Under Bias

Tb,as

-10 to +S5

°C

NOTES:

o to

V

+70

I. Relative to Vss.

2. -3.5V for pulse width:;; IOns.

• ELECTRICAL CHARACTERISTICS

• Recommended DC Operating Conditions (Ta = 0 to + 70°C)
Parameter

Symbol

Min.

Typ.

Max.

Unit

Vee

4.5

5.0

5.5

V

Vss
V IH

0
2.0
-0.5(1)

0

0

Supply Voltage
Input Voltage
NOTE:

V 1L

-

6.0

V
V

-

O.S

V

I. -3.0V for pulse width:;; IOns.

• DC CHARACTERISTICS (Ta = O°C to +70°C, Vee = 5V ± 10%)
Max.

Unit

Input Leakage Current

Ilui

Vee = 5.5V, Vm = OV - Vee

-

-

2

I'A

Output Leakage Current

IILOI

R = VIH , Vout = OV - Vee
Average Operating Current

-

-

2
SO

I'A
rnA

R = W = RS = FLIRT = V IH
All Inputs", Vee - 0.2V or s Vee

-

10

rnA

I

rnA

Output Low Voltage

VOL

IOL = SmA

2.4
-

-

Output High Voltage

Iee2
ISB
VOH

Parameter

Operating Power Supply Current
Standby Power Supply Current

Test Conditions

Symbol

Ieel

IOH = -4mA

Min.

-

Typ.

-

-

0.4

-

V
V

• CAPACITANCE (Ta = 25°C, f = IMHz)
Symbol

Test Conditions

Typ.

Max.

Unit

Input Capacitance

Cm

pF

C out

-

TBD

Output Capacitance

= OV
VOUI = OV

TBD

pF

Parameter

Vm

• AC CHARACTERISTICS (Ta = O°C to 70°C, Vee = 5 ± 10%)

• Test Conditions
• Input Pulse Levels: Vss to 3.0V
• Input and Output Timing Reference Level: 1.5V

• Input Rise and Fall Times: 5 ns
• Output Load: See Figure

+5V
4800

Dout

2550

L

30pF*

h7
Output Load
*Including scope and jig.

~HITACHI
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- - - - - - - - - - - - - - - - - - - - - - - - - - - HM63941-25/35/45
• Read Cycle

Parameter
Read Cycle Time
Access Time

Symbol
tRc
tA

HM63941-25

HM63941-35

HM63941-45

Min.
35

Max.
-

Min.
45

Max.
-

Min.
60

-

-

25

-

35

-

45

Max.

Unit
ns
ns

tRR

10

-

15

25

35

-

45

-

ns

tRPw

-

10

Read Pulse Width
Read Low to DB Low Z

tRLZ

5

-

5

-

10

-

ns

Read High to DB High Z

tRHZ

-

15

20

ns

toH

5

-

5

25

Data Valid from Read High

5

-

ns

Read Recovery Time

-

ns

• Write Cycle
Parameter
Write Cycle Time

Symbol

HM63941-25

HM63941-35

HM63941-45

Unit

Min.

Max.

Min.

Max.

Min.

Max.

twc

35

-

45

-

60

-

ns

-

10

-

15

-

ns

tWR

10

Write Pulse Width

twpw

20

-

35

-

45

-

ns

Data Setup Time

tDS

15

-

20

-

25

-

ns

Data Hold Time

tDH

0

-

0

-

5

-

ns

Write Recovery Time

• Reset Cycle
Parameter

Symbol

HM63941-25
Max.

Min.

Max.

35

45

-

Reset Pulse Width

tRSC
tRS

25

-

Reset Recovery Time

tRSR

10

-

Reset Cycle Time

HM63941-35

Min.

35
10

-

HM63941-45

Unit

Min.

Max.

60

-

ns

45
15

-

ns

-

ns

• Retransmit Cycle
Parameter

Symbol

HM63941-25

HM63941-35

Min.

Max.

Min.

35

Max.

HM63941-45
Min.

Max.

Unit

tRTC
tRT

-

60

-

ns

20

-

45

Retransmit Pulse Width

35

-

45

-

ns

Retransmit Recovery Time

tRTR

10

-

10

-

15

-

ns

Retransmit Cycle Time

• Flag Timing
Parameter

Symbol

HM63941-25
Min.

HM63941-35

HM63941-45

Max.

Min.

Max.

Min.

Reset to Empty Flag Low

tEFL

-

30

-

45

Read Low to Empty Flag Low

tREF

-

25

-

35

-

Read High to Full Flag High

tRFF

-

25

-

35

Write High to Empty Flag High

tWEF

-

25

-

Write Low to Full Flag Low

tWFF

-

25

-

Write Low to Almost-Full Low

tWAF

-

30

Read High to Almost-Full High

tRAF

-

30

Max.

Unit

60

ns

-

45
45

ns
ns

35

-

45

ns

35

-

45

ns

-

40

-

55

ns

-

40

-

55

ns

~HITACHI
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303

HM63941-25/35/45 - - - - - - - - - - - - - - - - - - - - - - - - - - SIGNAL DESCRIPTIONS
Inputs

• Aeset (AS)
The device is reset whenever AS input is taken to
low state, for minimum reset pulse width. When
device is reset, both read and write pointers are
set to the first location. A reset cycl~ is required
after power on. Both read enable (A) and write
enable (W) inputs must be in the high state durl!:!9
reset. Empty fla9.iEF) will go low and full flag (FF)
and almost-full (AF) will go high during reset cycle.
• Write enable (W)
_
Write cycle is initiated at the falling edge of W, if
the full flag (FF) is not set, provided that data setup and hold time requirements relative to the rising edge of 0N) are met. Data is stored in the device sequentially and independently of any simultaneous read operation. To inhibit further write operations and prevent internal data overflow full
flag (FF) will go low.
• Aead enable (Fi)
_
Aead cycle is initiated at the falling edge of A, if
the empty flag (EF) is not set. Data is accessed on
a first-in, first-out basis independently of simultaneous write operation. As read enable (Fi) goes
high, all outputs will return to high impedance
state, till next read operation. After the last data
has been read from the FIFO, the empty flag (EF)
will go low, preventing further read operations with
~ut kept in high impedance state. Empty flag
(EF) will go high during a valid write cycle (twEF),
thereafter a valid read can start.
• First load/retransmit (FLlAT)
For depth expansion mode, this pin is grounded to
indicate that it is the first device, while this pin of
the rest of devices should connect to Vee for correct operation. In single device mode, this pin resets the read pointer to the beginning of the FIFO
memory, therefore data can be reread from the
beginning. Both Rand W should be kept high
while AT is taken low.
• Expansion-in (Xi)
For single device mode expansi~n-in (Xi) is
grounded. For depth expansion mode,
expansion-in QQ) should be connected to
expansion-out (XO) of previous device.
• Data In (Do to Os)
Data inputs for 9-bit wide data.
Outputs

• Full Flag (FF)
The full flag (FF) will go low when FIFO is full,
inhibiting further write operations until one or
more read operations are completed or the FIFO
is reset.

tions, until one or more write operations are completed, or FIFO is set to retransmit.
• Expansion-out (XO)/Almost-full flag (AF)
This output has dual functionality depending how
it is used. In de.E!!:l expansion configuration
expansion-out (XO) is connected to next
expansion-in (Xi). The expansion-out (XO) ~the
last FIFO is connected to the expansion-in (XI) of
the first FIFO. In this way the first FIFO indicates
the next FIFO that it will receive the next data. In
like manner, any FIFO which becomes full will indicate the next FIFO that it will receive the next data.
The second function of this output is in stand
alone and/or parallel expansion configurations to
indicate the system user that the FIFO is almost
full.
• Data outputs (0 0 to as)
Data outputs for 9-bit wide data. Th~se outputs
are in high impedance state when A is in high
state.
VARIOUS OPERATIONS MODE

• Single device mode
_
If only one FIFO is used, the expansion-in (XI) pin
should be grounded.
• Width expansion mode
Width expansion by 9-bit increments may be
achieved when separately paralleling the data inputs and the data outputs. In this configuration
any flags of any device may be used. To avoid
output contention of the flags for short periods of
time, the flag outputs should not be wired together.
• Depth expansion mode
Multiple of FIFOs could provide multiple of 4k x 9
as (N) x (4k) by 9-bits wide, where N is the number of FIFOs connected in depth expansion
mode.
The following arrangement must be provided.
1. First load (FL) of the first FIFO should be connected to ground.
2. All other (FL) should be connected to Vee.
3. Connect the expansion-out (XO) of each FIFO
to e~nsion-in (Xi) of the.l!ext FIFO serially
and XO of the last FIFO to XI of the first FIFO.
4. Connect all the empty flag (EF) lE,gether to OR
gate and connect all the full flag (FF) together to
OA gate to obtain two separate valid empty flag
(EF) and full flag (FF) outputs.
5. (RT) and (AF) will not be available in this mode.
• Compound expansion mode
Combination of width and depth expansion
modes will provide larger FIFO arrays.

• Empty flag (EF)
The empty flag (EF) will go low when the FIFO
becomes empty, inhibiting further read opera-

~HITACHI
304

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - HM63941·25/35/45

• TIMING WAVEFORM
• Read Cycle

00-08

Data out valid

Data out valid

• Write Cycle

twc
twpw

tWR

w
./

I'\.

tos

jI(

tOH

"-I"

:<: Data in valid)

00-08

( Data in valid)

• Reset Cycle

~,
" ' - _ _ _J /

w
tEFL
EF

NOTES:

I.

Vi

2.

tRSC = tRST, tRSR.

=

R=

VIH during reset.

.HITACHI
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305

HM63941-25/35/45 - - - - - - - - - - - - - - - - - - - - - - - - - - • Retransmit Cycle

FURT

• Full-Flag Cycle

(From Last Write to First Read)

Last write

First Read

First Read

R

w
FF

• Full-Flag Cycle

(Effective Write Pulse Width After FF High)

FF
W

@HITACHI
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- - - - - - - - - - - - - - - - - - - - - - - - - - - HM63941-25/35/45

• Empty-Flag Cycle

(From Last Write to First Read)
First Read

First Write

Last Read

Data Out

• Empty-Flag Cycle (Effective Read Pulse Width After EF High)

EF

• Almost-Full Flag Cycle
Write=Read+4079

Write=Read+4080

Write=Read+4079

"\ I\..
I~RAF.

;V
tWAF

AF

~I\.

./

•

/

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

307

~HITACHI
308

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Section 2
Cache Static RAM
and
Fast SRAM Modules

.HITACHI@
309

~HITACHI
310

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300

HM62A 168/HM62A188 SerieS-Preliminary
• PIN-OUT

Direct Mapped 8,192-Word x 16/18-Bit
2-Way 4,096-Word x 16/18-Bit Static Cache RAM
• DESCRIPTION
The Hitachi HM62A168/HM62A188 is a high speed 128/144-kbit
static cache RAM organized as 2-way set associative 4k x 16/18 or
direct mapped 8k x 16/18. By using two HM62A 168/HM62A 188 with
Intel's 82385 cache controller a high performance 80386 system can
be achieved.
The HM62A 168/HM62A 188, packaged in a 52-pin PLCC is available for high density mounting.
• FEATURES
• Meets INTEL 82385 cache memory controller
• High Speed
Access Time ....................... .25/35/45ns (max.)
• Address Latch
• Pin Programmable for 8k x 16118 or 2-Way 4k x 16/18

(CP-52)
• PIN DESCRIPTION

• ORDERING INFORMATION
Type No.

Access

Package

HM62168CP-25
HM62168CP-35
HM62168CP-45

25ns
35ns
45ns

52-pin PLCC

HM62188CP-25
HM62188CP-35
HM62188CP-45

25ns
35ns
45ns

52-pin PLCC

• BLOCK DIAGRAM
Topology lWo-Way Set Associative (MODE

= Logic Low)

Pm Name

FunctIOn

CALEN

Cache Address
Latch Enable

MOOE

Mode Select

Ao to A\2

Address

CSo, CSt

Cache ChIp Select

COEA,COEB

Cache Output Enable

CWEA,CWEB

Cache WrIte Enahle

0 0 to 0'5

Oata Input/Output

CE

Cache Chip Enable

NC/OPo,OP,

No connectIOn
Parity Input/Output

Way A

COEA - - - - - ; 4k, 8/9

4kx 819

• PIN ARRANGEMENT

CWEA - - - - - - - l

AI A2 M A4 AS AS ~ CALENA1 II. Nl AI0All
AD

)

DO to D151and OPO, DP1

All-L---.Jn

AI 6 5 4

3 2

1 52 51 50 49 48 41

8

U

10
11

42

00Eii - - - - - + I

41

CWEii - - - - - + I 4k, 8/9

Ce - - - - '

4kx8/9

40

Way B

15

30

~==========~------~

16

38

11

31

19
20

Topology Direct Map (MODE = Logic Low)
COEA

Va:; VccCSO

00Eii -'-----1
6\WA - . - - - - - ;

em V.V.COEA

l:WED

CS;

mil

Vee Vee

MOllE

(Top View)

CWEii
A12
AD

~

DO 10 0151and OPO. OPI

All

CALEN

Ce------o---f----'

~=============~---~
CSI

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra POint Pkwy. Brisbane, CA 94005-1819. (415) 589-8300

311

HM62A168/HM62A188 Series - - - - - - - - - - - - - - - - - - - - - - - - • FUNCTION TABLE
• Two-Way Mode (Mode = High) 2-4K x 16/18
110 Pin

Input Signal
CWEA CWEB

CE
H

CS o
X

CS I
X

COEA
X

COEB
X

X

X

H

H

X

X

X

L

L

H

L

H

H

H

L

L

H

H

L

H

L

L
L

L
H

H
L

H

L

H
H

H

H

L

L

L

L

H

H

H

Function

Do-D7/DPo

Ds-D'5IDP ,

X

High-Z

High-Z

X

High-Z

High-Z

Disabled

Output

High-Z

Read Way A

H

Output

High-Z

Read Way B

H

High-Z

Read Way A

High-Z

Output
Output

Output

Output

Read Way A

Output
High-Z

Write Way A

Disabled

Read Way B

L

L

L

H

L

H

H

Output

L

L

H

X

X

L

H

Input

L

L
H

H
L

X
X

X
X

H

L

L

L

H

Input
High-Z

L

H

L

X

X

H

L

High-Z

Input

Write Way B

L

L

L

X

X

L

H

Input

Input

Write Way A

Read Way B

High-Z

Write Way B

Input

Write Way A

L

L

L

X

X

H

L

Input

Input

Write Way B

L

L

H

L

Input
High-Z

Write Way A & B

L

L
L

High-Z

H

X
X

L

L

X
X

Input

Write Way A & B

L

L

L

X

X

L

L

Input

Input

Write Way A & B

• Direct Mode (Mode = Low) 8K x 16/18
Input Signal
CE

CSo

CS,

COEA

COEB

CWEA

CWEB

110 Pin
D g-D I5 IDP I

Function

H

X

X

X

X

X

X

Do-D7IDPo
High-Z

High-Z

Disabled

X

H

H

X

X

X

X

High-Z

High-Z

Disabled

X

X

X

H

H

X

X

High-Z

High-Z

Disabled

L
L

L
H

H
L

L
L

L
L

H
H

H

High-Z

H

Output
High-Z

Output

Read Do to 0 7
Read 0 8 to DIS

L

L

L

L

L

H

H

Output

L

L

H

X

X

L

L

Input

Output
High-Z

Read Do to 0 IS
Write Do to 0 7

L

H

L

X

X

L

L

High-Z

Input

Write Os to D,s

L

L

L

X

X

L

L

Input

Input

Write Do to DIS

• ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Power Dissipation

Vm
PT

Operating Temperature Range

Topr

Storage Temperature Range

T st•
T btas

-0.5(1) to +7.0
1.2
o to +70
-55 to + 125
-10 to +85

Item
Voltage on Any Pin Relative to Vss

Storage Temperature Range Under Bias
NOTE:

1. Vm min. = -2.5V for pulse width :s; IOns .

•
312

Unit

HITACHI

Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819' (415) 589-8300

V
W
°C
°C
°C

- - - - - - - - - - - - - - - - - - - - - - - - - HM62A168/HM62A188 Series
• RECOMMENDED DC OPERATING CONDITIONS (T. = 0 to 70°C)
Parameter

Symbol

Min.

Typ.

Max.

Unit

Vee

4.S

S.O

5.S

V

0

V

+ 0.3

V

Input Low (Logic 0) Voltage

V1L

0
2.2
-0.3(1)

0

Input High (Logic 1) Voltage

Vss
VIH

Supply Voltage

NOTE:

-

Vee

-

0.8

V

1. VIL min. = -2.0V for pulse width s IOns.

• DC CHARACTERISTICS (T. = 0 to 70°C, Vee = SV ± 10%, V ss = OV)
Min.

Typ.

tOH

Ooull
OPO,OP1

)00K

Data Valid

tCE

~HITACHI
314

Unit

Max.

3
3
2
8
4
5

Output Hold from Address Change
Chip Select to Output Low-Z

(CWE

Max.

25

tOE

• Read Timing Waveform (1)

Min.

tRC

Output Enable to Output Valid

Address Latch Enable Pulse Width

Max.

HM62168-45
HM62188-45

tAA
tA12
tcs, tCE

Chip Select Access Time

HM62168-35
HM62188-35

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300

ns
ns
ns
ns
ns
ns

- - - - - - - - - - - - - - - - - - - - - - - - - HM62A168/HM62A188 Series
• Read Timing Waveform (2)

(CWE = High, COE = Low, CS = Low)

tCE

/

'\.

/

GALEN

tASL

tAHL

/
tRC

)K

Address AD-A 11 Valid

AO-A11

tM

)K

A12

A12 Valid
tA12

tOH

)00 (

Doutl
DPO, DP1

Data Valid

tCE

• Read Timing Waveform (3)

(CWE = High)
tCALEN

GALEN

~"

/
tASL

/
tAHL

"

tRC

Address

)(

"

) "-

External Address Valid
tM
tA12

GS,GE

/'f'

r\.

tHZ

tcs
tCE
tLZ

l'\.

./
tOLZ

Doutl
DPO, DP1

p(

It"
tOHZ
Data Valid

"-

/

tOE

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

315

HM62A168/HM62A188 Series - - - - - - - - - - - - - - - - - - - - - - - - • Write Cycle
Parameter

Symbol

HM62168-25
HM62188-25

HM62168-35
HM62188-35

HM62168-45
HM62188-45

Unit

Min.

Max.

Min.

Max.

Min.

35

45

-

ns

40

-

ns

25

-

40

-

ns
ns

Max.

Write Cycle Time

twc

25

Address Valid to End of Write

tAw

18

tA12W

18

-

Chip Select to End of Write

tcw

18

-

25

-

30

Data Valid to End of Write

tDW

10

10

-

15

tDH

0

0

-

0

-

ns

tWHZ

3
25

15

-

20

ns

tWLz
twp

3
18

15
-

-

-

3

-

ns

-

30

-

ns

tcp

18

-

25

-

30

-

ns

Address Setup Time

tAS

0

-

0

-

ns

tWR

0

0

-

2

-

ns

8

10
6

10

Address Hold to Latch Low

tAHL

5

-

5

-

5

-

ns

4

-

15

Address Setup to Latch Low

tcALEN
tASL

-

0

Write Recovery Time

A 12 Valid to End of Write

Data Hold from End of Write
Write Enable Active to High-Z
Write Enable Inactive to Low-Z
Write Pulse Width
CE Pulse Width During Chip Enable
Controlled Write

Address Latch Enable Pulse Width

25

~HITACHI
316

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

ns

ns
ns

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HM62A168/HM62A188 Series
• Write Timing Waveform (1)

(CDE = High, WE Controlled)

tCALEN

CALEN
twc

Address

External Address Valid

Din!
DPO,DP1

Data Valid

•

HITACHI

Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy • Bnsbane, CA 94005-1819 • (415) 589-8300

317

HM62A168/HM62A188 Series - - - - - - - - - - - - - - - - - - - - - - - - • Write Timing Waveform (2)

(COE = High, CE Controlled)

tCALEN

CALEN
twc

Address

External Address Valid
tWR

tcp

Din!

DPO, DP1

•
318

HITACHI

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy • Brisbane. CA 94005-1819 • (415) 589-8300

HM67C932

SerieS-Preliminary

8,192-Word x 9-Bit x 4-Row Static Cache RAM
• DESCRIPTION
The Hitachi HM67C932 is a high speed 288-kbit static cache RAM
organized as 4-way set associative 8k x 9 or direct mapped 32k x 9
with 4-row selector for burst mode. By using HM67C932 with high
speed standard microprocessors a high performance computer system can be achieved.
The HM67C932, packaged in a 44-pin PLCC is available for high
density mounting.
•
•
•
•
•
•
•
•
•

FEATURES
For High Speed Standard Microprocessors
High Speed Access Capability with Lower 2-address by Selector
Pipeline Access Capability with On Chip Address and Row Latches
(Edge Trigger Type Row Latch)'
On Chip Parity Generator and Checker
Organization .................288-kbit (8-kw x 9 bit x 4 row)
Drivability for Heavy Load (C L = 100 pF) &.
PLCC 44-pin
TTL 1/0

(CP-44)

• PIN ARRANGEMENT
A3 M AS MALEVssVcc A7

At,

M 10

'For cache RAM with transparent row latch, request data sheet HM678932.

• ORDERING INFORMATION
Type No.

Access Time

Package

HM67C932CP-20
HM67C932CP-25

20ns
25ns

44-pin PLCC
(Top View)

• MAIN CHARACTERISTICS
Item
Address Access Time (max.)
Access
Time

• PIN DESCRIPTION
Spec.
20/25ns

Row Select Access Time (max.)

10113ns

OE Access Time (max.)

10ll3ns

Cycle Time (min.)
Power Dissipation (typ.)

Remarks
CL = lOOpF&

25/30ns

Clock Frequency
33 - 40 MHz

0.8W

Vcc = 5.0V
tCYC = 60ns

Pin Name

Function

ALE

Address Latch Enable

Ao-AI2

Address

RLE

Row Latch Enable
(Edge Trigger)

Ro-RI

Row

I/Oo-I10 7

Data InputlOutput

1/08

Data InputlOutput
(Even Parity)

CS

Chip Select

WE

Write Enable

OE

Output Enable

PC

Parity Control

PError

Parity Error Output
(Open Drain)

Vcc

Power

Vss

Ground

VCCQ

Power
(For Output Transistors)

VSSQ

Ground
(For Output Transistors)

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

319

HM67C932 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • BLOCK DIAGRAM

Dout
Selector

Address
WE
Dout

8k word X 9 bit

WE - - - + I

Ro.1

RLE
• Edge Trigger

pc------------------------------------~

CS---I.~

&.. •• Open drain

• FUNCTION TABLE
• Truth Table
CS OE WE
H X X
L H H
L L H
L H L
L L L
L H L
L L L
NOTE:

PC
X
X
X
L
L
H
H

Mode
Not Selected
Output Disabled
Read
Write
Write
Write (Parity Generate)
Write (Parity Generate)

Vcc Current
ISB,IsBI
Icc, Icci
Icc, Icc!
Icc, Icc!
Icc, Icc!
Icc, Icc!
Icc, IcC!

1/0 Pin
HighZ
High Z
DOllt
Din
Dm
Din(l)
Din(l)

PError Pin
HighZ
HighZ
High Z or L (Error)
HighZ
High Z
HighZ
High Z

Ref. Cycle

Read Cycle No.1, 2
Write Cycle No. 1-5
Write Cycle No.6, 7
Write Cycle No.1

1. DI8 input is ignored and generated as parity bit from DIO to Dn.

• Input Latch Table
• Row Latch

• Address Latch
ALE
H
L

Mode
Load
Hold

Latch Output
Address Input
Previous Address

RLE

t
HorL

Mode
Load
Hold

Latch Output
Row Input
Previous Row

~HITACHI
320

Hitachi America. Ltd • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - HM67C932 Series
• ABSOLUTE MAXIMUM RATINGS
Symbol

Rating

Unit

Voltage on Any Pin Relative to Vss

Item

VT

-0.5 to +7.0

Operating Temperature Range

Topr

V
DC

Storage Temperature Range (With Bias)

o to

TS!2(b••s)

+70
-10 to +S5

TS!2

-55 to + 125

Storage Temperature Range

DC
DC

• RECOMMENDED DC OPERATING CONDITIONS (T. = 0 to + 70DC)
Item

Symbol

Min.

Typ.

Vee

4.5

5.0

Vss
VIH
V1L

0

0

0

V

2.2
-0.5(1)

-

Vee + 0.5
0.8

V

= 5V

= 0 to

Supply Voltage
Input Voltage

NOTE:

Max.
5.5

Unit
V

V

I. -3.0V for pulse width S 2Ons.

• DC AND OPERATING CHARACTERISTICS (Vee
Item

± 10%, Ta

+70 DC, VSS = OV)

Symbol

Test Conditions

Min.

Max.

Unit

Input Leakage Current

ILl

-

-

2

pA

Output Leakage Current

ILO

-

-

10

p.A

Operating Power Supply Current

Icc
Icc I

-

-

TBD

mA

-

-

TBD

rnA

ISB

= Vss to Vee
CS = VIH or OE = VIH or
WE = V1L, VIIO = Vss to Vee
CS = V1L, 1110 = OmA
Min. Cycle, Duty: 100%, 1110 = OmA
CS = VIH

-

TBD

rnA

ISBI

CS o(

Dout

)V-

Data Valid

• Timing Waveform of Read Cycle (2) (1) (3)

RC

cs

/~

".\K

tHZ

tACS
tCll

vXX~V
r-.
/'1\..

Dout

~

Vccsupply
current

............................................................
Icc

"'

/
tpD

150%

50%~

158

NOTES:

1. WE is high for read cycle.
2. Device IS continuously selected, CS = VIL.
3. Address vabd prior to or coincident with CS transition low.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

347

HB66A2568A-25/35 - - - - - - - - - - - - - - - - - - - - - - - - - -

• Write Cycle
Parameter

Symbol

HB66A2568A-25

HB66A2568A-35

Min.

Max.

Min.

Max.

35

-

ns

-

ns

-

ns

10
-

ns

Write Cycle Time

twc

25

Chip Selection to End of Write
Address Valid to End of Write

lew
tAw

20
20

Write Pulse Width

tAS
twp

0

-

20

-

30

Write Recovery Time

tWR

3

3

Data Valid to End of Write

tDW

15

20

0

Write Enabled to Output in High-Z

tDH
twz(l)

-

0

8

0

Output Active from End of Write

tow(2)

0

-

0

Address Setup Time

Data Hold Time

NOTE:

30
30
0

0

I. Transition is measured ± 200mV from high impedance voltage with Load (B).

This parameter is sampled and not 100 % tested .

•
348

HITACHI

Hitachi America, ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

Unit

ns

ns
ns
ns
ns
ns

- - - - - - - - - - - - - - - - - - - - - - - - - - - - HB66A2568A·25/35
• Timing Waveform of Write Cycle (1)

(WE Controlled)
lWC

Address

CS1,2

WE

Din

Dout

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

349

HB66A2568A-25/35 - - - - - - - - - - - - - - - - - - - - - - - - - - • Timing Waveform of Write Cycle (2)

(CS Controlled)

twe

Address
tew

CS1,2
twp·1

WE
tDW

Din
Dout

NOTES:

Data in valid
High Impedance

·3

1. A write occurs during the overlap of a low CS and a low WE.
2. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
3. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output
buffers remain in a high impedance state.
4. Dou! is the same phase of write data of this write cycle, if tWR is long enough.

~HITACHI
350

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM644332
2K Entry TAG Memory for Cache Sub System

The HM644332 TAGM IS a 2048·entry tag memory
fabncated with CMOS technology It supports
compact cache systems wIth 2·way or 4·way set

assocIativity and a hIgh level of performance for
32·blt mIcroprocessor systems, when used to·
gether wIth fast static RAMs as data RAMs

Features
• TIL-<:ompatlble Inputs and outputs

• Programmable orgamzation. 512-entry x 4-way or
1024-entry x 2-way

• LRU (least recently used) replacement algOrIthm
• Memory organization. 512 words x 98 bits
98 bIts = (20 tag bIts + 1 parity bit + 2 validity bits) x
4 ways + 6 LRU bits

• Purge functions (all purge and partial purge)
• Internal parity generator/checker

• Fast access time: 25 /30 ns max from address ip puts,
18 ns max from tag data inputs

• 64-pin pin-grid-array

• Single + 5 V supply

Ordering Information
AccesaTlme
Part No.

From Addresa

From Tag Data

Package

HM644332G-25

25 ns

18 ns

64-pin PGA

HM644332G·30

30 ns

18 ns

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300

351

HM644332

Pin Arrangement
(9)00000000(9)
19
v a
00
0
00
000
0
0
S1
34 55
sa 29
52 53
'8 51
00
00
.. 30
11 so
00
00
16
60 3'
00
00
Bottom view
6' 32
's
00
00
82 33
" "
00
00
63 34
'3
00
00
80
.ss
64 35
00000000
11
"
a
~
~
B M ~ ~
(9)008 1 00000(9)
,
6
S
3
2
~

~

~

~

~

~

.

~

.
.
.

10

•

&

•

Function

Pin No.

Function

Pin No.

Function

N.C.

23

A4

45

TD6

MHIT

24

As

46

TOg

3

HITolREPo

25

A7

47

Vee

4

HITiREP2

26

Ag

48

TD'3

5

HIT3/REP3

27

N.C.

49

TD,s

6

TDo

28

N.C.

50

TD17

7

T02

29

PINV

51

TD,g

8

EXTH

30

SBlK

52

Ao

9

MHENBl

31

SB,

53

A2

10

N.C.

32

INH

54

Vss

11

T07

33

INVl

55

A6

12

TOs

34

SET

56

As

13

TD,o

35

H/R

57

PURGE

TD"

36

HIT

58

MODE

15

TD'2

37

HColRCo

59

VINV

16

SBo

Pin No.

2

14

TD'4

38

HC,IRC,

60

17

TD'6

39

HIT,IREP,

61

Vee

18

TD,s

40

Vss

62

WRITE

19

N.C.

41

TD,

63

RLATCH

20

N.C.

42

TD3

64

PERR

21

A,

43

TD4

22

~

44

TDs

.HITACHI
352

Hitachi America, ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

HM644332

Pin Description
110

Symbol

Pin Name

Pin No.

Function

MODE

Mode

58

Mode selection
MODE ~ H: 512-entry x 4-way
MODE = L: 1024-entry x 2-way

AO-Ag

Address

52, 21, 53, 22, 23,
24, 55, 25, 56, 26

Address Inputs: Ag is not used lor 4-way; fix
it to H or L

TD O-TD '9

Tag Data

6, 41, 7, 42-45,
11,12,46,13,14,
15,48,16,49,17,
50,18,51

Tag information

PURGE

Purge

57

All purge is done when PURGE

INVL

Invalidate

33

Partial purge: V bit of specified address is
forced to 0 (L)

SBLK

Way Select Enable

30

Enables external way selection in replacement and invalidation cycles

SBo' SB,

External Way Address 60, 31

=L

External way address input: Enabled when
SBLK = H

WRITE

Wnte

62

Enables write

SET

Set

34

Timing pulse
Read cycle: Updates LRU
Wnte cycle: Stores tag, sets V bits to H,
and updates LRU
Partial purge cycle: Shifts LRU and sets
V bits to L

INH

Inhibit

32

Inhibits all functions except all purge

HIR

HitiReplace Selection 35

RLATCH

Replace Latch

63

Latch control for replace information

PINV

Parity Inversion

29

Used for testing only

Output selection
HIR = H: Hit information
HIR = L: Replace information

VINV

Validity Inversion

59

Used for testing only

MHENBL

MHIT Enable

9

Enables MHIT output

EXTH

External Hit Control

8

HIT

Hit

36

HCo/RCo
HC,tRC,

Hit/Replace Code

37,38

Forces MHIT output to L

a
a

Hit output: NOR of HITo to HIT3
Coded output of hit or replace Information

HITo'REPo- HitiReplace
HIT3/REP3

3,39,
4,5

a

Uncoded output of hit or replace information

PERR

Parity Error

64

0

Indicates parity error

MHIT

Modified Hit

2

a

Hit output modified by MHENBL and EXTH

Vce

Power

47,61

Connects to + 5V power supply

Vss

Ground

40,54

Connects to ground

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

353

HM644332----------------------------------------------------------Block Diagrams
Internal Blocks

Entry

ff-

r---

0

u...

-

0
0
0

.

Address
buffer
and
decoder

0
0
0
0
0
0

-~

.

0
0

o
0

j.-u..

'r--v'

Memory cells
512 entries
x 23 bits
x 4 ways

Parity
data

~

Replace information
Tag
data

D

C?0

Hit informatiL
Tag
data
buffer

rf---

,
'I
Sense out

J.

Parity
checker

Comparators

0

~

y-

rr=-

Parity
generator

0

~

--.;

0-

0

PURGE

--Vss

Memory cell
512 entries
x 6 bhs

f--

-J..,

0

ro

i>'

90

Purge
buffer

I

Replace information

~~

~
LRU
logic

TL-

New LRU data

0
0
0

6-

MPXand
output control

J.. o~ ...... ob
Hit/replace
information

Output control

b
Panty error

.HITACHI
354

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

-------------------------------HM644332

Output Control Block

MHENBL

EXTH

MHIT

Cell

I-------~HIT

88

.-------0 HITa/REPa
,..-----~

HIT,tREP1

,..------- VCC-0.2V, OE> VCC-0.2V

-

-

-

-

0.05

0.1

rnA

ICC2
Operating Power Supply
Current in Self Refresh Mode ICC3

CE: V/H, OE : V/L

-

1

2

-

0.6

1

rnA

CE;:: VCC-0.2V, OE~0.2V

-

-

-

-

50

100

I'A

Inpu t Leakage
Current

ILl

VCC- 5.5V
Vln: VSS to VCC

-10

-

10

-10

-

10

I'A

Output Leakage
Current

1£0

OE: V/H
VIIO: VSS to VCC

-10

-

10

-10

-

10

I'A

VOL

IOL: 2.1 rnA

-

-

0.4

-

-

0.4

V

VOH

IOH- -I rnA

2.4

-

-

2.4

-

-

V

Output Voltage

• CAPACITANCE
Item

Symbol

Test Conditions

typo

max.

Input Capacitance

Cin

Vin: OV

-

5

pF

Input/Output Capacitance

C'io

VI/a: OV

-

7

pF

Unit

Note) ThIS Parameter IS sampled and not 100% tested.

• AC CHARACTERISTICS (Ta = 0 to +70°C, Vee = 5V ±10%)
• AC Test Conditions
Input Pulse Levels. . . . . . . .
. ..... 2.4V, O.4V
Input Rise and Fall Times
. . . . . . . . . . . 5ns
Timing Measurement Level
. . . . . . . . . . . . 2.2V, O.BV
Reference Level ........... V OH = 2.0V, VOL = O.BV
Output Load . . . . . . . . . . . . . . . . . . 1 TTL and 100pF (including scope and jig)
Item

Symbol

HM65256B·IO

min.

max.

Random Read or Write Cycle Time tRC
Static Column Mode Read or Write
tRse
Cycle

160

-

55

-

Chip Enable Access Time

tCEA

Address Access Time

tAA

-

Output Enable Access Time

Chip Enable Precharge Time

tOEA
tCHZ
tCLZ
tOLZ
tOHZ
tCE
tp

Address Set·up Time
Row Address Hold Time
Column Address Hold Time

Chip Disable to Output in High Z
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Output Disable to Output in High Z
Chip Enable Pulse Width

100
50

-

40

-

25
30

-

10

-

-

25

lOOn

4m

50

-

tAS
tRAH

0
20
100

Read Command Hold Time

tCAH
tRCS
tRCH

Outpu t Enable Hold Time

tOHC

0

Output Enable to Chip Enable Delay
Time

tOCD

0

Read Command Set·up Time

0
0

HM65256B-12
min.

max.

190

-

65

-

HM65256B·15
min.
max.
235

-

80

-

HM65256B-20

-

-

105

-

ns

150

-

200

ns

100

ns

75

ns

35

ns
ns

120
60

-

75

-

50

-

60

-

30

-

30

-

10

-

-

35
10
25

120n

4m

60

-

-

0

-

20

-

120

-

0

-

-

30

150n

4m

40

-

10

-

200n

-

100

-

0

-

25

30

150
0

-

0
0

-

0

0

-

-

0

-

0

-

0

s

-

ns

-

ns
ns

0
0

-

ns

-

ns

tOH

5

-

5

-

5

-

10

twp

25

-

25

30

-

35

Chip Enable to End of Write

tcw

100

-

120

Column Address Set·up Time

tASW

0

-

0

-

0

ns

4m

ns

Write Command Pulse Width

-

ns

-

200
0

Output Hold Time from Column
Address

150

ns

35

75

0

Unit

310

-

25

max.

min.

200

-

ns
ns
ns

ns
ns

-

ns
0
(to be contmued)

@HITACHI
Hitachi America, Ltd • Hitachi Plaza' 2000 Sierra POint Pkwy' Brisbane, CA 94005·1819 • (415) 589·8300

371

HM65256B S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Symbol

Item

HM65256B·I0

min.

Column Address Hold Time after Write IAHW
Data Valid to End of Write
IDW
Data In Hold Time for Write
Output Active from End of Write

0
20

IDH

0

lOW

5

Write to Output in High Z
Transition Time (Rise and Fall)

IT

Refresh Command Delay Time

IRFD

max.

20
0
5

-

50

HM65256B·15

min.

-

0

25
3
50

max.

min.

-

-

IWHZ

HM65256B·12

25
3
60

max.

min.

0

-

0

25

-

30

0
5

-

0

-

50

HM65256B·20

-

3
75

5
30

-

50

3
100

max.

Unit

-

ns

-

ns

ns

-

ns

35
50

ns

-

ns
ns

Refresh Precharge Time

IFP

30

-

30

-

30

-

30

-

ns

Refresh Command Pulse Width for
Automatic Refresh

IFAP

80

10000

80

10000

80

10000

80

10000

ns

Automatic Refresh Cycle Time

IFe

160

-

190

235

190

-

235

-

ns

10000

-

310

10000

-

Refresh Command Pulse Width for Self
IFAS
Refresh

10000

Refresh Reset Time for Self Refresh

IFRS

160

Refresh Period

IREF

-

4

-

4

-

10000
310
4

-

ns
ns
4

ms

Notes:
(I) 'CHZ, '0HZ and tWHZ are defined as the time at which the output achieves the open circuit conditions.
tCLZ' tOLZ and lOW are sampled under the condition of tT=5ns, and not 100% tested
(3) A write occurs during the overlap of a low CE and low WE.
(4) If CE goes low simultaneously with WE going low or after WE going low, the outputs remam in high impedance state
(5) If input signals of opposite phase to the outputs are applied in write cycle, OE or WE must disable output buffers
prior to applymg data to the device and data mputs must be floating prior to OE or WE turning on output buffers
(6) V m (min) and V IL (max) are reference levels for measuring timing of input signals. Also, transitIOn times are meas·
ured between Vm and VIL'
(7) An initial pause of 1 OO"S is required after power·up followed by a minimum of 8 initialization cycles .

(2)

• TIMING WAVEFORMS
•

Read Cycle No.1 ICE controlled)
tH(

CE-----J

Address

Ao-A7

Address

A8-AII~UL~3 ~~4_------------------------------------_f~~~~~~~~~~

leu
Dout----------------------------~

"'-Jij:...ll..JL.¥

Valid

Data Out

~HITACHI
372

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 5 2 5 6 B Series
•

Read Cycl. No.2 (OE controlled I
IH(

CE-----..I

Address
Ao-A, ~~~ ~TT-~~~~~~~~~~~~~~~~~~~~~~~~~~
Address

A.-AI4~-L~J~_4~-------------------------------------------r--~ ~-L~~~

WE

I(/./.

Dout----------------------------~

•

Writ. Cycl. No.1 (OE Clockl
IRe
tCF.

CE-------i

Address
Ao-A7
leAH

Address
AH-AII
tANM

WE-----+------.. I----""----Ilr---------tl---

tCH~

•

HITACHI

Hitachi Amenca, Ltd • Hitachi Plaza. 2000 Sierra POint Pkwy.• Brisbane, CA 94005·1819 • (415) 589-8300

373

HM65256BSeries------------------------------------------------------------•

Writ. Cycle No.2 IOE low fixl
IR<
ICE

CE-----.11

Addressnt'X"'-~iI=====================+1~
__________________________________________
A.-A,,~LX~~-4

_H_f~~u-

OE----+----------+------------H-------

tllHZ

Dout---------=~--~~~~~~~~~~~-----------------------

• Static Column Mode Read Cycle

CE
lAS

Address

Ao-A7

Address
A8-A14

WE
OE
Dout

~HITACHI
374

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 5 2 5 6 8 Series
• Static Column Mode Write Cycle

CE

Address
AS-AI4

Dou!

•

--------~==::~~~~~--~-------i~~~~~~~--------

Automatic Refresh Cycle

CE-----------J

~-~I~R~F~D-~~----I~f~·C----~~-~IF~C~-~ ~____________
IFP

•

IFAP

Self Refresh Cycle

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra POint Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

375

131072-word x 8-bit High Speed CMOS Pseudo Static RAM
The Hitachi HM658128 is a pseudo-static RAM organized as
131,072-word x 8-bit_ HM658128 realizes low power consumption and high speed access time by employing 1_3~m CMOS
process technology_
The HM658128 supports 3 refresh functions: Address Refresh,
Auto Refresh and Self Refresh_ Low power version dissipates
only 0_5mW (typ.) in Self Refresh Mode and retains the data with
battery backup for short time_ Self Refresh Mode is guaranteed
only for L-version_
The HM658128 is pin-compatible with 256k-bit PSRAM and
static RAM_

11
HM658128P Series

(DP-32)
HM658128FP Series

• FEATURES
•
•

Single 5V (±10%)
High Speed
o Access Time
CE Access Ti me ___ 100/120/150ns
o Cycle Time
Random Read/Write Cycle Time _.. 180/210/250ns
• Low Power ... 200mW typo (Active)
0.5mW (standby)
• All inputs and outputs TTL compatible
• Non Multiplexed Address
• 512 Refresh Cycles (8ms)
• Refresh Functions
Address Refresh
Automatic Refresh
Self Refresh (Only for L-version)

•

(FP-32D)

• PIN ARRANGEMENT

ORDERING INFORMATION
Type No.
HM658128DP-10
HM658128DP-12
HM658128DP-15
HM658128LP-1O
HM658128LP-12
HM658128LP-15
HM658128DFP-10
HM658128DFP-12
HM658128DFP-15
HM658128LFP-10
HM658128LFP-12
HM658128LFP-15

Access Time
lOOns
120ns
150ns
lOOns
120ns
150ns
lOOns
120ns
150ns
lOOns
120ns
150ns

Package

600 mil 32 pin
Plastic DIP

32 pin Plastic
SOP

(Top View)

• PIN DESCRIPTION
Symbol
AO - A16

Address Inputs

I/O - 1/07

Data Input/Output

RFSH
CE

~HITACHI
376

Pin Name

Refresh
Chip Enable

OE

Output Enable

WE

Write Enable

CS

Chip Select

Vee
VSS

Power Supply
Ground

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 5 8 1 2 8 Series

•

BLOCK DIAGRAM
A.

~

r--

··
··
··

A. 0-

[(10

i'()7

r--

Addr~"

Row

M~M()R'r

MATRIX

La1ch

D!'<:oder

151t><256!xll

(umrol

-ce-

'---

r--

o-~

t---

(olumn 1'0

Inpui

Oala
("mrnl

"L-

Column Deem!.r

'-Addre,s Latch Control

~ --:---:--:--:-~,
~

A"
/1

r

A.

I

r~

rE

rs

Refresh
Control

I

OE
WE

L

I
T'm,ng

Pul~

Ge .... ra!Or

Read "me Control

• TRUTH TABLE
CS at CE going Low
CE
RFSH
X
L
H
L
H
X
H
X
L
L
X
L
H
X
L
H
X
H
Note) *1. Self refresh IS guaranteed only for L-version .

OE
L
X
H
X
X
X

WE
H
L
H
X
X
X

I/O Pin
LowZ
High Z
HighZ
High Z
HighZ
HighZ

Mode
Read
Write

CS Standby
Refresh*'
Standby

• ABSOLUTE MAXIMUM RATINGS
Item
Terminal Voltage with Respect to V ss
Power Dissipation
Operating Temperature
Storage Temperature
Storage Temperature Under Bias

•

Topr
T. t,_
Tbias

RECOMMENDED DC OPERATING CONDITIONS (To
Item
Supply Voltage
Input Voltage
Note) *1.

Rating
-1.0 to +7.0
1.0
o to +70
-55 to +125
-10 to +85

Symbol
VT
PT

Symbol

VIL min = -3.0V for pulse width

~

°c
°c
°c

=0 to +70°C)

min.
4.5
0
2.2
-0.5*'

Vee
Vss
VIH
VIL

Unit
V
W

typo
5.0
0

-

max.
5.5
0
6.0
0.8

Unit
V
V
V
V

IOns .

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

377

HM~128SeriH------------------

•

___________________________________________

DC CHARACTERISTICS (Ta = 0 to +70°C, V cc = SV ± 10%)
Parameter

Symbol

Operating Power
Supply Current
Standby Power
Supply Current
Standby Power
Supply Current

Test Condition

ICCI

ISB2
ICC2
Iccs

Input Leakage Current

ILl

Output Leakage Current

ho

VCC=5.5V
Vln = Vssto VCC
OE= VIH
VIla = Vss to Vcc
10L- 2.1mA
10H= -lmA

VOL
VOH
Note) °1. This characteristics is guaranteed only for L-version.
Output Voltage

• CAPACITANCE (Ta

typo

max.

Unit

-

40

75

rnA

-

1

2

rnA

-

100

200

IJ.A

-

1

2

rnA

-

100

200

IJ.A

-10

-

10

IJ.A

-10

-

10

IJ.A

-

-

0.4

V
V

CE = VIH
RFSH = VIH
CE~ Vcc -0.2V
RFSH ~ Vcc -0.2V
rn= VIH
RFSH = VIL
rn~ Vcc -0.2V
RFSHS:0.2V

ISBI

Operating Power
Supply Current in Self Refresh Mode*l

min.

hlo=O
tcyc = min.

2.4

-

= 2S o C,[= IMHz)

Item
Input Capacitance
Input/Output Capacitance

Symbol

Test Condition

typo

Vin -OV
VI/a =OV

-

Cin
CliO

max.
S
10

-

Unit
pF
pF

Note) This Parameter is sampled and not 100% tested .

• AC CHARACTERISTICS (Ta = 0 to +70°C, VCC = SV ± 10%)
• AC Test Conditions
Input Pulse Levels
........... 2.4V.0.4V
Input Rise and Fall Times ........... 5ns
Timing Measurement Level ........... 2.2V.O.SV
Reference Level ................... VO H = 2.0V. VOL = O.SV
Output Load
. . . . . . . . . . . . . . . . . .. 1 TTL and 100pF (including scope and jig)

Item

c,S-S,z.8-8

Random Read or Write Cycle Time
Random Read Modify Write Cycle Time
Chip Enable Access Time
Output Enable Access Time
Chip Disable to Output in High Z
Chip Enable to Output in Low Z
Output Disable to Output in HighZ
Output Enable to Output in Low Z
Chip Enable Pulse Width
Chip Enable Precharge Time
Address Set-up Time
Address Hold Time
Read Command Set-up Time

4.0

-

HM65S12S-10
min.
max.
ISO
tRC
240
tRWC
100
tCEA
30
tOEA
30
tCHZ
30
tCLZ
25
tOHZ
5
tOLZ
lOOn
11J.
tCE

Symbol

tp
tAS
tAH
tRCS

I~~
0
30
0

Read Command Hold Time
RFSH Hold Time

tRHC

0
15

Refresh Command Delay Time (Standby Mode)

tRCD

-

tRCH

-

HM65S12S-12
min.
max.
210
2S0
120
40
35
35
30
5
120n
11J.

b~
0
35
0
0
15

-

-

5

-

-

HM65S12S-15
min.
max.
250
330
150
50
40
40
35
5
150n
11J.

70'tCI
0
40
0
0
15

-

-

5

-

-

-

5

Unit
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
ns
ns
ns
ns
ns

(to be continued)

~HITACHI
378

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 5 8 1 2 8 Series
Item

b~·z8-& Symbol

Chip Select Set-up Time
Chip Select Hold Time
Write Command Pulse Width
30
Chip Enable to End of Write
Data In to End of Write
Data In Hold Time for Write
Output Active from End of Write
Write to Ou tpu t in High Z
Transition Time (Rise and Fall)
Refresh Command Delay Time
~,.?
Refresh Precharge Time
Refresh Command Pulse Width for Automatic
Refresh
Automatic Refresh Cycle Time
Refresh Command Pulse Width for Self Refresh
Refresh Reset Time for Self Refresh
Refresh Reset Time for Automatic Refresh
Refresh Period (512 cycles)

tess
tesH
twp
tew
tDW
tDH
tow
tWHZ
tT
tRFD
tFP
tFAP
tFe
tFAS*9
tRFS*9

HM65S12S-10
min.
max.
0
30
30
100
25
0
5
25
50
3
70
-

,c4f(
SOn
ISO
S'
ISO
0

tRFA
tREF

-

-

HM65S12S-12
min.
max.
0
35
35
120
30
0
5
30
3
50
SO

<.QW(
S"

-

S

-

SOn
210
S
210
0

-

HM65S12S-15
min.
max.
0
40
40
150
35
0
5
35
3
50
90
-

}o.M
SOn

S"

-

S

-

250
S
250
0
-

S"

nit
ns
ns
ns
ns
ns
ns
ns

ns
ns
ns
ns
s

-

ns

-

ItS

-

ns

-

ns
ns

S

Notes:
(1) tCHZ, tOHZ and tWHZ are defined as the time at which

the output achieves the open circuit conditions under
the condition of tr = 5ns and not 100% tested.
(2)tCHZ, tCLZ, tOHZ. tOLZ. tWHZ and tow are sampled
under the condition oftr = 5ns and not 100% tested.
(3) A write occurs during the overlap of a low c.E..and a
low WE~Write end is defined at the earlier of WE going
high or CE going high.
(4) If CE~es low simultaneously with WE going low or
after WE going low. the outputs remain in high impedance state.
(5) If input signals of opposite phase to the outputs are

applied in write cycle, OE or WE must disable output
buffers prior to applying data to-1.he device and data
inputs must be floating prior to OE or WE turning on
output buffers.
(6) VIH (min) and VI!- (max) are reference levels for
measuring timing 0 mput signals. Also, transition times
are measured between V IH and V I.{.'
(7) An initial pause of 100!,s is requlIed after power-up
followed by a minimum of S initialization cycles.
(S) After Self Refresh, Auto Refresh should be started within l5!,s. (only for L-version)
(9) This characteristics is guaranteed only for L-version .

• TIMING WAVEFORMS
•

Read Cycle

cs

Address
Ao-A16

Dout

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy' Brisbane, CA 94005-1819 • (415) 589-8300

379

HM658128 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

•

Write Cycle-1 IOE Clock)

cs

Address

Ao"-AI6

Dout

Write Cycle-2 (OE Low Fix)

cs

Address
Ao-AI6

0"

DOllt

.HITACHI
380

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 5 8 1 2 8 Series
•

Read Modify Write Cycle

CS

Address

An-A'6

RFSH

Dm

Dout

•

Automatic Refresh Cycle

•

Self Refresh Cycle

IT

Note)

•

Self refresh is guaranteed only for L-version.

CS Standby Mode

,,

2-

cs

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

381

HM658128 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SUPPLY CURRENT VS. SUPPLY VOLTAGE ( 1 )

SUPPLY CURRENT VS. AM81ENT TEMPERATURE (1 )

1.3

1.3

To = 25'(;

Vee =5 OV

1.2

]

/

1

1.1

-

1.0

z

>- 09

8:
Ul

"

- r---

]
i

.,./

V

- r-- r-

1.0

0.9

en

O.S
07

1.2

§
z 11

/

V

~
u

"

]

os
4.50

4.75

5.00

5.25

5.50

20

Supply Voltage Vee (V)

40

SUPPLY CURRENT VS. SUPPLY VOLTAGE(2)

SUPPLY CURRENT VS. AM81ENT TEMPERATURE (2)

6

1. 3

To = 25'(;

1§

Vee=5.0V

]

1. 4

/

z 1. 2

~

/

1. 0

Sv V

u

>-

O. 44.50

1. 2

"z§

1. 1

-

1. 0

~

~ b,
~

u

8: o.
"
o. 6
Ul

>-

9

0.

""

J'--..,
............

Ul

5.00

4.75

5.25

o. S
o. 7 0

5.50

Ambient Temperature Ta

SUPPLY CURRENT VS. SUPPLY VOLTAGE(3)

1.6
To =25'(;

Vee=5.0V

:0 1.4

~

z§ 1.2
0

~

~

~

V

.......-

]

1.4

~

1.

z

]
>-

2~

1. 0

~

O. S

~

8:
J:

o. 6

~

O. 6

4.75

5.00

5.25

5.50

O. 4 0

Supply Voltage Vee (V)

20

40

~

60

Ambient Temperature Ta

eel

~HITACHI
382

so

eel

SUPPLY CURRENT VS. AM81ENT TEMPERATURE (3)

1. 6

O. 4 4.50

i"-

60

40

20

Supply Voltage Vee (V)

Sv

so

60

Ambient Temperature Ta ('C)

Hitachi America, Ltd • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

so

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM658128 Series
ACCESS TIME VS. SUPPLY VOLTAGE

ACCESS TIME VS. AMBIENT TEMPERATURE

1.3

1.3

Vee =5.0V

Ta=25"C
1.2

]
~
z

11---_

----- -----I----

10

E

b

~

0.9

~

~

11

i5

-E

1.0

b

0.9

]

~

V

V

V

os

O.S
0.7 4.50,

4.75

5.00
Supply Voltage

0.7

5.50

5.25
Vl(

o

20

40

60

STANDBY CURRENT VS. SUPPLY VOLTAGE(l)

STANDBY CURRENT VS. AMBIENT TEMPERATURE (1)

1.6

1.6
Ta=25"C

~§

1.4

z 1.2

~

8
]"
~

1.0
O.S
0.6
0.4

V

V
4.5

V

Vee=5.0V
1.4

V

1.2
1.0

]

O. S

~

a
50

4.75

0.4

o

1.6

Ta=25"C

Vee=5.0V

1.4

~

1.0

~

/v

~

/'

-o§

z
_

8 o.Sv V
-a
@

U

0.

"

0.6
0.4
4.5

1.4
1.2
1.0

t--- "-

1
1

./

if>

so

60

STANDBY CURRENT VS. AMBIENT TEMPERATURE(2)

1.6

1.2

40

20

Ambient Temperature Ta ("C)

STANDBY CURRENT VS. SUPPLY VOLTAGE(2)

~
z

-r--r---

0.6

5.5

5.25

--

Supply Voltage Vee (V)

1

80

Ambient Temperature Ta ZOe)

(V)

O.S

-....;..

I---I---

0.6

4.75

5.0

5.25

5.5

0.4

Supply Voltage VeL (V)

o

20

40

60

so

Ambient Temperature Ta ('C)

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

383

HM658128 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LOW LEVEL INPUT VOLTAGE VS. SUPPLY VOLTAGE

]

1.3

]

HIGH LEVEL INPUT VOLTAGE VS. SUPPLY VOLTAGE

1.3

-;;;

Ta=25"C

§

Ta=25"C

1.2

3

1.2

x 1. 1

;;:

~

1.1

..

~

3

-

~

>1l,

1.0

2
"0

:~

0.9

]

0.8

~

:...---- ~

f.----

1l,
;'I

'0

:-

1.0

1 0.9
]

-So

;;:

0.8

-----------

~

j

O. 7
4.50

5.00

4.75

5.25

0.7

5.50

4.50

HIGH LEVEL OUTPUT CURRENT VS. OUTPUT VOLTAGE

~
\3
z

1.4
1.2

c

~

1.0

u

g

"

0.8

0

]

~

:I:

0.6

1.6

1\

\
\
\
\
\

HIgh Level Output Voltage

/

Ta=25"C
Vcc =5.0V

0
8

/
0.2
VOH

(V)

I

/

/

/
Ta=25"C
Vcc=5.0V

0.4

0.6

Low Level Output Voltage V OJ (V)

~HITACHI
384

5.50

LOW LEVEL OUTPUT CURRENT VS. OUTPUT VOLTAGE

1.6

]

5.25

5.00

4.75

Supply Voltage Vee (V)

Supply Voltage Vee (V)

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

0.8

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HM658128 Series

ACCESS TIME VS. LOAD CAPACITANCE
1.8

1l

1.6

1
3

1. 4

"

Z

a
8
O. 6

100

--

~

ZOO

>--

300

-

~

400

500

Lead Capac1tance Cd pF)

~HITACHI
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

385

~HITACHI
386

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

Section 4
Video Memory

~HITACHI®
387

HM63021 S e r i e s - - - - - - - 2048-word x 8-bit Line Memory

HM63021 is a 2048-word x 8-bit static Serial Access Memory
(SAM) with separate data inputs and outputs. Since it has an
internal address counter, no external address signal is required
and internal addresses are scanned serially. Using five different
address scan modes, it is applicable to FIFO memories, doublespeed conversions, 1 H delay lines and 1 H/2H delay lines for
digital TV signals. Its minimum cycle times are 28 ns and 34 ns
each corresponding to 8 fsc of PAL TV signals and NTSC TV
signals. All inputs and outputs are TTL-compartiable. This device
is packaged in a 300-mil dual-in-line plastic package.
(DP-28N)

Features
• Five modes for various applications
• Corresponds to Digital TV system with 4 fsc sampling
(PAL, NTSC)
• Decoder signal output pin; Fewer external circuits
• Asynchronous ReadlWrite operation;
Separate address counters for Read/Write
No Address Input required
• High Speed; Cycle Time 28/34/45 ns (min)
• Completely Static Memory; No refresh required
• 8-bit SAM with separate I/O
• Low Power; 250 mW typo Active
• Single 5 V supply
• TTL compatible

Ordering Information
Cycle
Time

Type No.

HM63021P-28 28 ns
HM63021P-34 34 ns
HM63021P-45 45 ns

Package
300-mil 28-pin
Plastic DIP

Pin Arrangement

D

I

IH/2H

I

THC

I

DSC

I

THCE

MODEl

1
RES i

CLK

RCLK
RRES
DInO

Dml
Dm2
Dm3

Dm4

DECI

I WDEC I

!dQ~~
~
Cootml

O~
4

~
25

~
~

~

C!~

Dm7

~

WE

12

HlghZ

V"

24

~ j
~

Dm6

OmS

THCE

Modes

~

G:=

l!

!

n

Wnte
Control

~

I

DSC

I

I

IH/2H

LRDEC J

DEC2

THC

I

D

V"

MODE2
MODE3
OE
DoutO
DoutI
Dout2

tm

Dout3

19

DoutS

1=

~
17

Dout6

16

WRES

I

I

DEC3

~

WCLK

I WT I

DEC4

~

I::::

Dout4

Dout7

DS

(Top View)

~HITACHI
388

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 3 0 2 1 Series

Pin Description
Pin No.

Pin Name

1

MODEl

2

RCLK/CLK

3

RRES/RES

4·11
12

Functions
Mode Input 1 (All Modes)
Read Clock Input (TBCE, DSC, TBC)
Clock Input (lHl2H, D)
Read Reset Input (TBCE, DSC, TBC)
Reset Input (l H/2H, D)
Data Inputs (All Modes)
Write Enable Input (AU Modes)

DinO-Din7
WE

13

High Z/WDEC/DECI

14

VSS

15

WCLK/WT /DEC4

16

WRES/DS/DEC3

17·24
25

Dout 0 - Dout 7
OE

26

MODE3/RDEC/DEC2

27
28

MODE2

High Impedance (TBCE, DSC)
Write Decode Pulse Output (TBC)
Decode Pulse Output 1 (lH/2H, D)
Ground (AU Modes)
Write Clock Input (TBCE, DSC, TBC)
Write Timing Input (l H/2H)
Decode Pulse Output 4 (D)
Write Reset Input (TBCE, DSC, TBC)
Delay Select Input (l HI 2H)
Decode Pulse Output 3 (D)
Data Outputs (All Modes)
Outpl4t Enable Input (All Modes)
Mode Input 3 (TBCE)
Read Decode Pulse Output (TBC)
Decode Pulse Output 2 (lH/2H, D)
Mode Input 2 (All Modes)
Power Supply (+SV) (All Modes)

Vee

Mode Table
Mode Signals
Mode
MODEl
MODE2
MODE3
H
H
H
Time base compression/expansion (TBCE)
H
H
L
Double speed conversion (DSC)
·1
H
L
Time base correction (TBC)
°1
L
H
1H/2H delay (lH/2H)
°1
L
L
Delay line (D)
Note) 01. Decoder Output Signal (~ImCl)

Application Example
Picture in Picture
Non interlace
Time Base Corrector
Vertical fJIter
Delay line

Absolute Maximum Ratings
Parameter
Voltage on Any Pin relative to V ss

Symbol

Power Dissipation
Operating Temperature
Storage Temperature

Topr

Storage Temperature under bias

Tbias

Tstg

Rating
-0.5°1 to +7.0
1.0
oto +70
-55 to +125
-10 to +85

Unit
V
W
·C
·C
·C

Note) 01. -3.SV for pulse width ~ 10 ns

Hitachi America, Ltd.

• HITACHI
° Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

389

HM83021S.I•• ---------------------------------------------------------------Block Diagram

Vee

Vss

I

I

DInO

WE

~I
~
.---------d

WE

Input
Latch

Latch

Write Address

Con...1

I

WDEC _ _--+_+-("'204=7'-1)

r-

Address

Decoder
IL...----'

DID7

I

r......-..

Write Column Decoder

(Wnte Stop)

iiiiES/RES
WCLKIWT
WRES/DS

Tlmlrlll:
Control
LOB'c
Reid

Write

MODEl

R.w

R.w

Decoder

Decoder

MODE2
MODE3

Read Column SwItCh

Address
Decoder

Read Column Decoder

(2047)

RDEC

(900.1810)

iiffi

(909.1819)

DEC2

1-'<.:;11::.34:;}_____ iiEC3
1-'<.:;11.:;25;.:..}----DEC4

H

Read Address
Control

Output Latch

DootO

I

Dout7

I

-.l
OE

Recommended DC Operating Conditions (To = 0 to +70°C)
Parameter
Symbol
min
typ
max
Unit
4.5
5.0
5.5
V
Vee
Supply Voltage
0
o
0
V
VSS
2.4
VIH
V
6.0
Input Voltage
-0.5"1
VIL
0.8
V
Note) '1. -3.0V for pulse width ~ 10 ns.

~HITACHI
390

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy' Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM63021 Series
DC and Operating Characteristics (Ta= 0 to +70°C, Vee = SV ± 10%, Vss = OV)
Parameter

Symbol

min

typO!

max

Unit

Test Condition

Input Leakage Current

IIUI

10

/,A

Ve e =5.5V
Yin = VSS to Vee

Output Leakage Current

IILOI

10

/'A

Of= VIH
Vout = VSS to Vee

Operating Power Supply Current

lee

90

rnA

50

0.4

VOL
Output Voltage
V OH

V

Min. cycle, lout = 0 rnA
10L = 8 rnA *2, Dout 0 to Dout 7,

DEC Output pin

2.4

V

IOH = -4 rnA, Dout 0 to Dout 7
pin

2.4

V

IOH = -I rnA, DEC Output pin

----------------------------~----------------~~--Notes) *1. Typical values are at Vee = 5V, Ta = 25°e and for reference only.

*2. IOL = 6mA for 45ns version.

Capacitance (Ta

= 2SoC,f= 1.0 MHz)

_ _ _ _ _-'P:.:a::r.=am::....e.:.tec:r_ _ _ _ _-"S"y-"m"'b::..0c:l'---_ _ _:::m:::i:::n_ _ _-=:t__
yp~_ _---=:m:.:-a=x'-_ _--'U=n=i=t____Conditions
Input Capacitance
Cin
6
pF
Yin = OV
Output Capacitance "2
Cout
9
pF
Vout = OV
Notes) *1. This parameter is sampled and not 100% tested.
*2. 13, 15 - 24, 26 pin

AC Characteristics (Vee = SV ± 10%, Ta = 0 to + 70° C, unless otherwise noted.)
• AC Test Conditions
I nput and Output timing reference levels: 1.5V
Input pulse levels: Vss to 3V
I nput rise and fall times: 5 ns
HM63021·28/34

Dout Output Load (A)

Dout Output Load (8)
(toLZ. 10HZ)

DEC Output Load

5100

DEC

48011

0--....,.---...
395Q

Dout 0--"""1>---~

30pF *1

4800

Dout

*1
30pF

255Q

0 - - -.....- -...
*1
5pF

255Q

* 1 Including scope and Jig.
HM63021-45
Dou! Oulpul Load (8)
DEC Output Load

(tOLZ, tOHZ)

Dout Oulpul Load (A)

+5V

+5V

+5V

Dout

DoutO-,....-....

DEC ( } - - . - -....
3()PF~1

294Q

01

0--..--...

30pF*1

Includmg scope and Jig

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra POint Pkwy • Brisbane, CA 94005·1819 • (415) 589·8300

391

HM63021 Series
Read Cycle
Symbol

Parameter
Read Cycle Time
Read Clock Width
Access Time
(fall)
Decode Output Access Time
(rise)
Output Hold Time
(fall)
Decode Output Hold Time
(rise)
Output Enable Access Time
Output Disable to Output in High Z
Output Enable to Output in Low Z

tRC
tRWL
tRWH
tAC
tDAl
tDA2
tOH
tDOHl
tDOH2
tOE
tOHZ
tOLZ

HM63021-28
min
max
28

HM63021-34
min
max
34

10
10

10
10
20
20
40

15
15
25
25
50

5
5
5
0
5

HM63021-45
min
max
45

5
5
5
20
15

0
5

30
30
60
5
5
5

25
20

0
5

30
25

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Write Cycle
Parameter

Symbol

Write Cycle Time

twc
tWC(lH/2H Mode)

Write Clock Width

tWWL
tWWH

Input Data Setup Time
Input Data Hold Time
WE Setup Time
WE Hold Time
WT Setup Time
WT Hold Time

tvs
tDH
tWESL
tWESH
tWEHL
tWEHH
tWTSL
tWTSH
tWTHL
tWTHH

HM63021-28
min
max
28
56
10
10
5
5
5
5
5
5
5
5
5
5

HM63021-34
min
max
34
68
10

HM63021-28
max
min
8
5
8
5

HM63021-34
min
max
9
5

10
5
5
5
5
5
5
5
5
5
5

HM63021-45
min
max
45
90
15
15
7
7
7
7
7
7
7
7
7
7

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Reset Cycle
Parameter
Reset Setup Time
Reset Hold Time
Clock Setup Time Before Reset
Clock Hold Time Before Reset

Symbol

tRES
tREH
tREPS
tREPH

7

10
7

•

ns
ns
ns
ns

Double-Speed Conversion Mode
This mode turns HM63021 into a 1024-word x

~HITACHI
392

Unit

reset to address O. A write-inhibit function of
HM63021 stops writing automatically after the
data has been written into all addresses 0 to
2047. The write-inhibit function is released by
reset using WRES, and the HM63021 restarts
writing into address O.

Mode Description

• Time Base Compression/Expansion Mode
This mode turns HM63021 into a 2048-word x 8bit FIFO memory with asynchronous input/
output. The HM63021 provides 2 clocks
(RCLK, WCLK) and 2 resets (RRES, WRES),
one each for read and write. The internal address
counters increment by 1 address clock and are

9
5

HM63021-45
max
10

min

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - . - - - - - - - - - - - - - - - - HM63021 Series

8-bit x 2 memory with asynchronous input/
output. It is used for generating non· interlaced
TV signals. When the original signal and the
interpolated signal (1 field delay) of interlaced
signals are input to the HM63021, multiplexed
per dot, it outputs non-interlaced signals for each
line. 8 fsc should be input to RCLK and WCLK.
A standard H synchronizing signal and a noninterlace H synchronizing signal are input to
ii"lRE"S" and tfFfE"S" respectively. A write-inhibit
function is provided in this mode, making it
applicable to PAL TV, where extra data
(1135-1024 = 111 bits) is ignored.
•

TBC Mode
This mode turns HM63021 into 2048-word x
8-bit FIFO memory with asynchronous input/
output. The HM63021 provides 2 clocks
(lfcLR, WCIK) and 2 resets (Fi'RB, Wif£"S").
one each for read and write. The internal address
counters increment by 1 address at each clock
and are reset to address O. The internal address
counters return to address 0 after they reach
address 2047. The HM{)3021 outputs a write
decode pulse from
synchronizing it with
address 2047 in the write address counter, and
read a decode pulse from RDEC, synchronizing
with address 2047 in the read address counter.
Using these pulses, the memory area can be extended easily (multiple-HM63021s can be used
with ease).

of RES. Since the HM63021 outputs a 901
decode pulse (DEC1) and a 910 decode pulse
(DEC2). connecting ~ to RES, for example,
outputs 1 H- and 2H- delayed signals alternately
at a 8- fsc cycle when the original signal is input
at a 4- fsc cycle. A write-inhibit function is provided in this mode, making it applicable to PAL
TV, where extra data (1135-1024 = 111 bits) is
ignored.
•

Notes on Using HM63021
•

Hitachi recommends that pin 13 (high impedance) should be fixed by pulling up or down
with a resistor (of several kil) in TBC or DSC
mode.

•

Hitachi recommends that the mode signal input
pins and DS pin should be fixed by pulling them
up or down with a resistor (of several kill.

•

Data integrity cannot be guaranteed when mode
is changed during operation.

wr>rr.

•

1 H/2H Delay Mode
This mode turns HM63021 into a 1024-word x
8-bit x 2 delay line with synchronous input/
output. Delay time is defined by the reset period

Delay Line Mode
This mode turns HM63021 into a 2048-word x
8-bit delay line with synchronous input/output.
Delay time (3 to 2048 bits) is defined by the
reset period of RES. The delay is 2048 bits
when RES is fixed High. Signals delayed by 910
bits to 1135 bits for example, can be easily obtained without external circuits by just connecting selected decoded pulses on DECl - DEC4 to
RES.

• When a read address coincides with a write
address in TBCE, TBC or DSC mode, the data is
written correctly but it is not always read
correctly.

(1) Read after Write (3 bits delay)
WLCK

t~twcmln

RCLK

(2) Write after Read (2048 bits delay)
WCLK

I ~Ons

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

393

HM63021

Serle8--------------------------------

• At power on, the output of the address counter
is not defined. Therefore, operations before the
system is reset cannot be guaranteed, and decode
signal output is not defined until after the first
reset cycle.
• The decode signal is latched by a decode output
latch circuit at the previous address of the internal counter address and is output synchronized with the ne~t address. For example, WDEC
in TBC mode is latched at write address 2046
and is output at write address 2047. If a write
reset is performed on address 2047 at this time,

•

Hitachi recommends that tm (time between
mode set and the first cycle (Pre-reset)) should

the write address becomes 0 and WDEC is output.
The same operation is performed in other modes.
•

In the reset cycle, the input levels of WRES;
R RES, "FfES are raised to satisfy t R E H. and are
fixed high until tREPH in the next pre-reset cycle
is satisfied. The rise timings of the reset signals
(RES; ~. RRES) are optionals provided that
the tREPS specification is satisfied. The timings
at which RES, WRES, and RRES fall after prereset are also optional, provided that the t R EPH
and t R ES specifications are satisfied.

be kept for 2 cycle time (56ns / 68ns / 90ns) or
more while the power supply is on.

(1) TBCE, TBC, DSC and Delay Line Mode

~
~
mode

WCLt
(CLK)
WRES
(RES)

--~~TTTTr=~7777T=~
~~r.rtTTrrTTTTTTTT7777V----'

Vahd

~HITACHI
394

Hitachi America, Ltd • Hitachi Plaza· 2000 Sierra POint Pkwy· Brisbane, CA 94005-1819· (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 3 0 2 1 Series

(2) 1 H / 2H Delay Mode

~
~
mod,. DS

~
~

.Di.=='1'--~=-----+--------+--------_+-

Note

Whf'n mode pms are fixed with Vee. GND m mode set
while the power supply

IS

on, tm spec

If>

not needed

Decode Signal
When internal address counter reaches the specified address as shown below, decode outputs become low.
Mode
TBC

Pin
No.
13
26

Pin
Name
WDEC
RDEC

Internal Address
counter
Write 2047
Read 2047

Timing of the
Output Signal
After Write 2047
Output of 2046

13

DEC!

Read 900 (2H)

Output of 900 (l H)

26

DEC2

Read 909 (2H)

Output of 909 (lH)

lH/2H

Operation
Completion of Writing on all bits is detected.
Completion of Reading from all bits is detected.
By inputting this signal to pin #3, 901/1802-bit
delay output is obtained.
By inputting this signal to pin #3, 910/1820-bit
delay output is obtained.

By inputting this signal to pin #3, 90 I-bit delay
output is obtained.
DECI
13
By inputting this signal to pin #3 after the
Read 1810
Output of 1809
frequency of DECI is devided into two, 1811-bit
delay output is obtained.
By inputting this signal to pin #3, 91 O-bit delay
Read 909
Output of 908
output is obtained.
Delay
DEC2
26
By inputting this signal to pin #3 after the
line
frequency of DEC2 is devided into two, 1820-bit
Read 1819
Output of 1818
delay output is obtained.
By inputting this signal to pin #3, 1135-bit delay
16
DEC3
Read 1134
Output of 1133
output is obtained.
By inputting this signal to pin #3, 1126-bit delay
DEC4
Read 1125
15
Output of 1124
output is obtained.
Note) When counter is reset by Reset Signal (RRES, RES, ~,address becomes O.
Read 900

Output of 899

Write-inhibit Function
When internal address counter is as follows, writing is inhibited automatically for the next cycle. The write·
inhibit function is cancelled by reset through WRES or RES.
Write-inhibit Function
(internal counter address)
Write-inhibit after address 2047
TBCE
Write-inhibit after address 1023 x 2
DSC
No function
TBC
Write-inhibit after address 1023
IH/2H
No function
D
Note) When address counter is reset by W"RES or RES, address becomes O.
Mode

~HITACHI
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

395

HM63021 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Read Reset Cycle (TBCE, TBC Modes)

Notes) "I. The read address counter I. reset at the first falllns edse of ~ after IfI{!!I f~~Eseetlng the specifications
of tREPS and tREPH. and It is not reset at the next falling edge of R'el:'X even If
Is kept low.
When tRES. tREH. tREPS. and tREPH cannot meet the specifications. the relet operation Is not Iluaranteed.
"2. Output Is from the read addre.. of the previoul cycle.
"3. When DB Is fixed high. the data at the read addreu counter Is reset after the data of address 2047 Is output.
and the same operation restarts.

Write Re.et Cycle (TBCE, TBC Mode.)

WCLK

Din

WE

Note)

The write address counter Is reset at the first falling edge of WCI:K after WRES falls. meeting the specifications of
tREPS and tREPH. and it is not reset at the next failing edge of~ even if WIrn'S" is kept low.
When tRES. tREH. tREPS. and tREPH cannot meet the specifications, the reset operation is not guaranteed .

•
396

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 3 0 2 1 Series
Reset Cycle (OSC Mode)

D,.

RCLK

*2. *~.

RRES

*4

-r~-M",I

i'A--f-£.L.'fL../'-LJ.¥-1

Dout

Reset Timmg 1

Reset Tlmmg 2

Notes) *1. The write address counter is reset at the first falling edge of WCLR after WRES falls, meeting the specifications
of tREPS and tREPH. and is not reset at the next falling edge of WCLK even if WP:ES" is kept low.
When tRES. tREH. tREPS. and tREPH cannot meet the specifications. the reset operation is not guaranteed.
*2. The read address counter is reset at the first falling edge of ~ after R1(ES falls. meeting the specifications
of tREPS and tREPH. and it is not reset at the next falling edge of 1>:CLK even if RRES is kept low.
When tRES. tREH. tREPS anr!!REPH cannot meet the specifications. reset operation is not guaranteed.
*3. When tREPH. tRES tREH (~to WCLK). or tREPS. tREPH, tRES, tREH (PRES to RCLK) cannot meet
the specifications. the output of video signal A is not guaranteed. (Reset Timing I).
*4. When tREfS (WRES to RCLK). or tRES, tREH, tREPS, tREPH (PRES to RCLK) cannot meet the specifications. the Interpolation signal B is not guaranteed. (Reset Timing II).

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

397

HM63021 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Reset Cycle (lH/2H Mode)

CI.i
(SI•• )

*1

WT
(41,,)

_*2

RES

*I.U
Din

(n-2)

U

Oout

WE

DS

u

\

~----....\
I ,----~

/

\

(Hllh) or (Low)

Notes) "I. WT'ls the Input durlllJ_half cycle of c:!t'K. meetins the ~cificatlons of tWTSL. tWTHL. tWTSH.and tWTHH'
Data Is written when WT Is low. Reset I. possible when WT Is high.
·2. Read address counter Is reset at the first fa11lns edge of ~ after ltV ~ meeting the specifications of
tREPS and tREPH. and it Is not reset at the next failing edge of erR' even if RES is kept low.
When tRES. tREH, tREPS, and tREPH cannot meet the specifications, the reset operation Is not guaranteed.
·3. When DS Is fixed high, 1H output data is delayed by n bits and 2H output data is delayed by 2n bits where 2n
is the reset cycle of 1tU,
When DS is fixed low, 1H output data Is delayed by n-5 bits and 2H output data is delayed by 2n-5 bits .

•
398

HITACHI

Hitachi America. Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 3 0 2 1 Series
Reset Cycle (0 Mode)

WE

Dm

Dout

Note)

*1. The read address counter is reset at the first falling edge of CLK after RES falls. meeting the specifications of
tREPS and tREPH. and it is not reset at the next falling edge of ELf{ even if 'RES is kept low.
When tRES. tREH. tREPS. and tREPH cannot meet the specifications. the reset operation is not guaranteed.

Write Enable (TBCE, OSC, TBC, 0 Modes)

D,.
Notes) *1. When tWEHL. tWESH. tWEHH. and tWESL cannot meet this specifications. the write enable operation is not
guaranteed.
*2. In the delay line mode. CLK takes the place of WCLK.

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

399

HM63021 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Write Enable (lH/2H Mode)

eLK
(Sfsc)

WT

(4r,c)

Din

Note)

"I. When tWTSL. tWTHL. tWEHL. and tWEHH cannot meet the specifications, the write enable operation Is not
guaranteed.

Decode Output (TBC. D Modes)

Notes) "I. In TBC$D~~ WCLK or RCLK takes theml~ce of CLK.

*2.

~Is

or~ln

'i'll'I!,

~,

2,

~ or~

in D mode.

Decode OutPut (1H/2H Model

Note)

*1. When tWTSL, tWTHL. tWTSH, and tWTHH cannot meet the specifications. the decode output operation is not
guaranteed.

~HITACHI
400

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 3 0 2 1 Series
Output Enable (All Modes)

~

--------.!.~-"""'
Dout*J.

H,lhZ

~

IIlm
8 -------

____D_.~_V_u_,d_ _ _ __'~}---~~~-+-~,~~---D.-~-V-u-,d---

Note) *1. Transition of tOHZ and tWLZ is measured ±200 mV from steady state voltage with Output Load B.
This parameter is sampled and not 100% tested.

~HITACHI
Hitachi America, Ltd • Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

401

HM53051P*
• An Application Note is available for this device, contact your local Hitachi representative.
262144-word X 4-bit Frame Memory
HM53051 P is a 262,144-word x 4-bit frame memory, using the
most advanced 1.3t.Lm CMOS processes. It performs serial access
by an internal address generator.
It offers a high-speed cycle time of 45ns or 60ns (min). As
input data and output data can be written or read in any cycle,
synchronized with a system clock, and the delay between data
read/write operations is freely settable. Y/C separation and
frozen pictures can be realized easily in 4fsc NTSC digital TV or
VCR systems. Also, it enables random access in 32-word x'l-bit
data block. With this function, picture in picture or a multiplexed picture can be displayed with ease.
Features
• 262,144-word x 4-bit serial access memory
• Organized with dual ports
Serial input
x 4-bit
x 4-bit
Serial output
• High Speed
Read/Write Cycle Time: 45ns/60ns (min)
Access Time: 35ns/4Ons (max)
• Semi-synchronous Read/Write Cycle
• Low Power
Active: 200mW (typ)
• Random Access in 32-word x 4-bit blocks
• External Refresh Control is unnecessary
Ordering Information
Type No.

Cycle Time
45ns
60ns

HM53051P-45
HM53051P-60

Package
300 mil 18-pin
Plastic DIP

Block Diagram

SAD

Memory Array

262,144 X4

(DP-18BJ

Pin Arrangement
Dout2
Dout3

Doutl
OoutO

TAS

Dm3
Dm2

~-<-

_ _ _ _.J--- Dml

(Top View)

Pin Description
Pin Name
Din
Dout
OE
TAS
CLK
CGW
CGR
SAD
SAS
WE

Function
Data Input
Data Output
Output Enable
Transfer Address Strobe
System Clock
Clock Gate (Write)
Clock Gate (Read)
Serial Address
Serial Address Strobe
Write Enable

Read/Write/Refresh
Control
&
Tlmmg Generator

DoutO

Dout2
Doutt
Dout3

DmO
Dm2 WE
Dlnl
Dm3

@HITACHI
402

Hitachi America, Ltd • Hitachi Plaza· 2000 Sierra POint Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

-----------------------------------------------------------------HM53051P
Functional Description
Serial access memory with I/O separated
Read cycle and write cycle of HM53051 can be
operated independently synchronized with a system
clock. It realizes time compression or expansion for
picture in picture in digital TV. for example.

• Write cycle by CGW
Write data are taken in at the falling edge of the
system clock ClK when CGW is low. If CGW is
high. HM53051 does not enter write cycle (cycle
time is defined by system clock cycle time). Time
is compressed easily with CGW.

eLK

Dn

Dm

)@(

xxxxxxxxx

Dn+1

• Read Cycle by CGR
Read data is output at the falling edge of the system
clock CD< when C"G"R is low. If ~ is high.
HM53051 does not enter read cycle (cycle time is

Dn+2

X XXXXXXX

defined by system clock time). Time is expanded
is realized easily with ml1.

eLK

D.

Doul

>®<

XXX

Dn+1

Dn+2

Random Access
The HM53051 is also capable of random access by
serial address input. SAD. Random access by the
unit of 32-word x 4-bit is performed. when TAS is
low after read address (ARO - AR12). write address
(AWO - AW12) and mode setting flags. RF (Read
SAS

Dn+3

Flag). WF (Write Flag) and I'i.W (Mode Flag) are read
into by SAD with synchronous MS. In order to
output data continuously. the address specified by
SAO increments automatically.

---

Mode Programming
Operation mode in HM53051 is programmed by the combination of SAD 5-bit.

MY

WF

RJf

0
0
0
0

0
0

0
1

0
0
0

0
1

0

Note)

AWO
x

ARO
x

x
x
x
x
x
x

x
x
x
x
x
x
1

0
0

0

1

0

1

Mode
Write/read address asynchronous transfer
Write address asynchronous transfer
Read address asynchronous transfer
Write/read address synchronous transfer
Write address synchronous transfer
Read address synchronous transfer
System reset
Inhibit

x means Don't care.

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300

403

HM53051P------------------------------------------------------_________
ReadJWrite Address Asynchronous Transfer Mode
• Read address asynchronous transfer mode
(1) Read address asynchronous transfer mode (1) (CGR: Low)
---,1

Dout

Note)

r-1

L-...J

CLK

r-----'L-.J
31 r-1 32 r-1 33 r-----' 63 r-1 64 r-1 65 r L-I L-I
L-I L-.J L-I

2 r-1 3

L-...J

L-...J

~------ _ _.....~2--- D3~

.1.

.1.

AddAR

AddAR+l

The data block at read address AR, specified by SAD, is output starting from the 32-nd system clock after the
ofTAS.

(2) Read address asynchronous transfer mode (2) (CGR: High)
2

3

CLK

LJl..JLJ-----

TAS

'---J
_ _.....~~~D~I_~~

Dou!

I.

Add AR

Notes) *1. The data block at read address AR, specified by SAD, is output starting from the 32-nd system clock after
the falling of TAS".
*2. If roR is turned to low after 33-rd clock from the falling edge of TAS, the data at read address AR (D2, D3,
D4 ...) is output with synchronous crK while CGR" is low.

• Write address asynchronous transfer mode
(1) Write address asynchronous transfer mode (1) (CGW: Low)
CLK

Din

1
2
3
31
32
33
63
64
65
~-----~-----~

~ - - - - - .J"n.;;=-/v'-";..:;....IV"-"'D-"2_--~
Add AW+l

AddAW

Note)

Add AW+2

The data block at write address AW, specified by SAD, is taken in starting from the 1-st clock after the falling edge
of'fAS.

(2) Write address asynchronous transfer mode (2) (CGW; High)
---, 1 r-1 2 r-1 3

CLK

L-I

L-..J

r- ___ _

31

32

L-I

lL-J-----------------------------------------Din

-----AddAW

Note)

If"CGW is turned to low after falling ofTAS":the data block at write address AW is taken in with synchronous eLK.

~HITACHI
404

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

-----------------------------------------------------------------HM53051P
ReadJWrite Address Synchronous Transfer Mode
• Read address synchronous transfer mode
1 ";n";32

5
63
64
65
66
~s--u-ssL..J1.....JLJLJ\~
1

eLK

2

n

31

32

33

34

II~)S

,GR

Dou!

Note)

IS

-----ll----SJ----------IS---------

~)~~~\~
~
AddARN-I
AddARN+1
I
AR

When TAS turns to low, the data block at read address AR, specified by SAD, is output after the data block at the
present read address ARN, and the next address ARN+ 1 is put out.

• Write address synchronous transfer mode
----, 1

2 HI---.

LJ·

n

.----!' + ~~ 31 ,..--, 32 ,..--, 33 ,..--,1 ~~ 32

L.J

LJ ..

L.J

L.J

LJ

LJ

TAS

~~.~\-----------------

CGW

'},

DIn

'fI:Etlf:K)\~)_
•

Note)

r---1

LJ

eLK

Add AW

I

Add AW+l

When TAS turns to low, the data block being written is taken into write address AW.

System Reset Mode
System reset mode is the same as read/write address asynchronous transfer mode except that read/write
address are reset to O.
• System reset by SAD
Note)

System reset mode starts when MF, WF, RF, AWO, and ARO are all high.

• System reset by

SAS and TAS

-u-Ln
L.J
L.J

~System reset mode

Note)

•

System reset mode starts when both SAS and T AS are low at the falling edge of the eLK.

1 field delay

Note)

Field-delayed data is output, when CGR and CGW tum to high before the system reset at the beginning of every
field, and turn to low simultaneously after the 33rd clock from the system reset.

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300

405

HM53051P----------------------------------------------------------------Notes on Using HM53051

•

Input/output data of 32 words is not written or
read in read/write address asynchronous transfer
mode or during system reset. The data is written
or read out in blocks of 32-word x 4-bit. Input
data of less than 32 words is not written in write
address asynchronous transfer mode or during
system reset. When asynchronous read address
transfer mode or system reset mode is activated,
output from the current data block will
continue. When output data from the current
data block is finished, the next data block is not
read out if it has less than 32 words.

•

Input data is not read out immediately. The data
(32 word x 4-bit) is written into the memory
array in the next 32 cycles after it is taken in.
The data can be read out only after writing to
the memory array is completed. If read address
transfer mode is programmed after the 33 word
clock from on input data block, new data can be
read out. If this mode is programmed before the
33 word clock, new data or old data is output.

(1) Read/write address asynchronous transfer mode

eLK

32

32

32

32

cycle

I
(W flte Address

I
Dm

Dout

(Read Address

ANI

AN)

I

I

1
Om of
Address AN

Wntlng on
Address AN

Reading from
Address AN

Dout of
Address AN

(2) Read/write address synchronous transfer mode

eLK
cycle

I

I 2 I 3 1 .. . 1 32

I

1 2 1 3 1 . . . I 32

I

J

21

31 . . . 1 32 1 I

1 2 1 3 1 . . . I 32 I

1

(Read Address

( W flte Addrf'ss

ANI

ANI

Dm
Om of
Address AN

Writing on

Address AN

Dout

Dout of

Address AR

Readmg from Address AN
_/_ Dout of Address ART 1

.1_

~HITACHI
406

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

Dout of
Address

AN

-------------------------------------------------------------------HM53051P
•

Mode programming
Do not reprogram read address transfer mode
before a read operation of the previous read
address transfer mode or system reset mode is
completed. If it is reprogrammed during a read
operation, address becomes inval id, and the
device may malfunction.

Do not reprogram write address transfer mode or
system reset mode before a write operation of
the previous write address transfer mode or
system reset mode is completed. If it is reprogrammed during a write operation, address
become invalid, and the device may malfunction.

(1) Read address asynchronous transfer mode
eLK

1

cycle

I I I .. I
3

2

32

1

I

I I
2

3J

1

•

1l2J 3

32

l·

j

32

I

I

TAS
(Read Address AN)

(Read Address AM)

Daut

Dout of
Address AM

Rf'acimg from

Readmg from

Address AM

Address AN

Dout of

Addre!>s AN

(2) Read address synchronous transfer mode
eLK

1

cycle

.I

I I I
2

3

32

I I I. I

1

2

3

1

32

I I I .I
2

3

32

I I

1

2

I

I
(Read Address AN)

(Read Address AM)

Dout
Readmg from

Dout of
AJdres:" AN

Address AN

Readmg from
Addre<;s AM

·1·

(3) Write address asynchronous transfer mode
eLK
cycle

1

-TAS

I I I .. I
2

3

32

1

I J 1 .1 I I I I . . I
2

3

32

1

2

3

32

I

W

(Wnte

Addre~s

(WrIte Address

AN)

A~fi

Om

Om of
Address AN

Wrltmg on

Address AN

Om of
Address AM

~HITACHI
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

407

HM53051P----------------------------------------------------------------(4) Write address synchronous transfer mode

112 1

1 ... 1 32

3

11

2

1 3 1 . " 1 32

cycle

11

1

2

1",1

3

I
(W nte Address AN)

32

LJ
(WrIte Address AM)

Dm

Om of

•

Om of

Wrltmg on
Address AN

Address AN

Address AM

32 elK initialization cycles or more are reo
quired.

Addresses must be set by read and write address
asynchronous transfer or system reset 100MS
after power on. Before an address can be set,

Absolute Maximum Ratings
Symbol

Parameter

Rating

Voltage on Any Pin Relative to Vss
Power Dissipation

Unit

-1.0 to +7.0

V

1.0

Operating Temperature

Topr

o to +70

W
·C

Storage Temperature

Tstg

-55 to +125

·C

Storage Temperature (under bias)

Tbias

-10 to +85

·C

Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter

Symbol

Supply Voltage
Input Voltage

min

typ

max

Vee

4.5

5.0

5.5

V

VSS

0

0

0

V

Unit

VIH

2.7

6.5

V

VIL

_0.5*'

0.8

V

Note) * 1. -3.0V for pulse width ;£ IOns.

DC and Operating Characteristics (Ta = 0 to +70°C, Vee

Test Conditions

Symbol

Parameter
Operating Power Supply Current

= 5V ± 10%, V ss = OV)
min

Min. cycle,
lout = 0 mA

lee

typ

max

Unit

40

60

mA

Input Leakage Current

Vee = 5.5 V
Yin = VSS to Vee

-10

10

"A

Output Leakage Current

OE=VIH
Vout = VSS to Vee

-10

10

"A

0.4

V

IOL =4.2 mA

Output Voltage

IOH = -2 mA,

Capacitance (Ta =25°C, f
Parameter

V

2.4

= 1.0 MHz)
Symbol

Test Conditions

min

typ

max

Unit
pF
pF

Input Capacitance

Cin

Vin= OV

5

Output Capacitance

Cout

Vout=OV

7

Note)

This parameter is sampled and not 100% tested.

~HITACHI
408

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

HM53051P

AC Characteristics (Vee = 5 V ± 10%, Ta =0 to +70°C)
AC Test Conditions
Input and output timing reference levels: 1.5 V
Input pulse levels: Vss to 3 V
Input rise and fall times: 5 ns
• Output Load: 2 TTL + 50 pF
(Including scope and jig)

•
•

•

Parameter

Symbol

System Clock Cycle Time

CI:K Pulse Width
Access Time from CI:K
Output Hold Time
Output Enable Access Time
Output Enable to Output in Low Z
Output Disable to Output in High Z
CGR Setup Time
CGKHoid Time
CGW Setup Time
CGW Hold Time
Write Command Setup Time
Write Command Hold Time
Data Input Setup Time
Data Input Hold Time
SAS Cycle Time
SAS Pulse Width
Serial Address Setup Time
Serial Address Hold Time
SAS Setup Time during Mode Programming
SAS Hold Time during Mode Programming
..
TAS Setup Time
T AS Hold Time
SAS Setup Time during System Reset by SAS/T AS
SAS Hold Time during System Reset by SAS/T AS
.-~-.--.-

tcc
tCL
tCH
tAC
tOH
tOEA
tOLZ
tOHZ
tGRS
tGRH
tGWS
tGWH
twcs
tWCH
tDS
tDH
tsc
tSL
tSH
tSAS
tSAH
tSSH
tSHH
tTS
tTH
tSSL
tSHL

-------~-.-.

HM53051-45
max
45
300
15
15
35
5
25
5
0
20
15
5
15
5
15
5
15
5
45
15
15
15
5
15
5
15
5
15
5

min

HM53051-60
max
60
300
15
15
40
8
30
5
20
0
15

min

15
5
15
5
15
5
60
15
15
15
5
15
5
15
5
15
5

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

~HITACHI
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 • (415) 589-8300

409

HM53051P----------------------------------------------------------------Read/Write Cycle

CLK

Don

CGR

DE

Low

to.
Dout

Notes) *1. Write Cycle starts when CGW is low and WE is low. Data are not written when WE is high.
Time-compression mode is realized by controlling CGW.
*2. Read cycle starts when CGR is low. Time-expansion mode is realized by controlling CGR.
Read Cycle (OE control)

CLK

CGR

loLZ

Dout

Notes) *1. tOHZ is

defi.~ed

by the time at which the output achieves the open circuit condition.

*2. tOLZ and tOHZ are sampled and not 100% tested.

~HITACHI
410

Hitachi America, Ltd • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589-8300

-----------------------------------------------------------------HM53051P
Mode Selection

SAS

SAD

TAS

Note)

SAS operates asynchronously with CIK: When TAS is low at the falling edge of the CI:K, the address transfer cycle
starts. SAS should be high during the address transfer cycle.

SAs, TAS Reset Mode

elK

SAS

TAS

Note)

The mode which was selected by SAD before SAs- and TAS reset, if SAS and TAS are reset, should be changed
because SAD is newly taken into by SAS. The mode should be reselected by SAD after SAS and TAS reset.

@HITACHI
Hitachi Amenca, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300

411

HM53461 S e r i e s - - - - - - - 65,536-word x 4-bit Multiport CMOS Video RAM
The HM53461 is a 262, 144·bit multi port memory equipped
with a 64k·word x 4-bit Dynamic RAM port and a 256·word x 4·
bit Serial Access Memory (SAM) port. The SAM port is con·
nected to an internal 1,024·bit data register through a 256·word x
4·bit serial read or write access control. I n the read transfer
cycle, the memory cell data is transferred from a selected word
line of the RAM port to the data register. The RAM port has a
write mask capability in addition to the conventional operation
mode. Write bit selection out of 4 data bit can be achieved.
Utilizing the Hitachi 2J.lm CMOS process, fast serial access
operation and low power dissipation are realized. All inputs and
outputs, including clocks, are TTL compatible.

HM53461P Series

(DP·24A)
HM5 3461 ZP Series

• FEATURES
•
•
•
•

•
•

Multiport organization
(RAM; 64k·word x 4·bit and SAM; 256 word x 4·bit)
Double layer polysilicon/polyicide n·well CMOS process
Single 5V (±10%)
Low power Active RAM; 380mW max.
SAM; 220mW max.
Standby
40mW max.
Access Time
RAM; 100ns/120ns/150ns
SAM; 40ns/40ns/60ns

(ZP·24)

Cycle Time

Random read or write cycle time (RAM)
190ns/220ns/260ns
Serial read or write cycle time (SAM)
40ns/40ns/60ns
• TTL compatible
• 256 refresh cycles ..... 4ms
• Refresh function
R AS - only refresh
CAS - before - RAS refresh
Hidden refresh
• Data transfer operation (RAM~SAM)
• Fast serial access operation asynchronized with RAM port
except data transfer cycle
• Real time read transfer capability
• Write mask mode capability

INFORMATION
• ORDERING
Type No.

Access Time

Package

HM53461p·IO
HM53461p·12
HM53461p·15

lOOns
120ns
150ns

400 mil 24·pin
Plastic DIP

HM53461Zp·1O
HM53461ZP·12
HM53461ZP·15

lOOns
l20ns
150ns

24·pin Plastic ZIP

-- ---,.. ----- ._-------

~HITACHI
412

Hitachi America, Ltd • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005· 1819 • (415) 589·8300

------

------- - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 5 3 4 6 1 Series

• PIN ARRANGEMENT
•

•
•

HM53461 P Series

SI/O,
Sl/O,

liD,
I/o,

HM53461ZP Series

1/04
SI/03
Vss

1/03
SOE
SI/04
SC

9 SI/02
n 1/01
13 WE
15 A6
17 A4

PIN DESCRIPTION
Pin Name
AO - A7

Function
Address Inputs

1/01 - 1/04

RAM Port Data Input/Output

SI/O 1 - SI/04

SAM Port Data Input/Output

RAS

Row Address Strobe

CAS

Column Address Strobe

SC

Serial Clock

WE

Write Enable

19A7

DT/OE

21 A2
23AO

SOE

SAM Port Enable

Vee
VSS

Power Supply

(Bottom View)

Data Transfer/Output Enable

Ground

(fop View)

• BLOCK DIAGRAM

.HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 • (415) 589-8300

413

HM53461 Series - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
.ABSOLUTE MAXIMUM RATINGS
Voltage on any pin relative to Vss .............. -1V to +7V
Power supply voltage relative to V ss .......... -O.5V to +7V
Operating temperature, Ta (Ambient) .......... oDe to +70o e
Storage temperature ................... -55°C to +125°e
Short circuit output current ..................... 50mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
• RECOMMENDED DC OPERATING CONDITIONS (Ta=O to +70°C)
typo
5.0

V/H

min.
4.5
2.4

VIL

_0.5*'

-

Symbol

Parameter
Supply voltage
Input High voltage
Input Low voltage

Vee

-

max.

Unit
V
V
V

5.5
6.5
0.8

Notes: 1. All voltages referenced to V ss.
2. -3.0V for pulse width;£ IOns.

•

DC ElECTRICAL CHARACTERISTICS (Ta
Symbol

RAM PORT

=0 to +70vC, VCC = SV ±IO%, VSS =OV)

SAM PORT
Standby Active

HM53461
-10

HM53461
-12

HM53461
-15

Unit

60

50

rnA

100
7
40
50
90
40
80

rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
mA
rnA

Operating current RAS, CAS cycling
IRC= min.

ICC)

0

X

70

ICC7

X

0

Standby current RAS, CAS = VIH

lCC2

0

X

110
7

lccs

X

0

RAS only refresh curren t
CAS = VIH' RAS cycling IRC = min.

lCC3

0

X

lCC9

X

0

~mode

lCC4

0

X

lCCIO
Iccs

X

0

0

X

100
50
90
60

lCCII

X

0

100

90

80
7
30
40
70
35
65
40
70

75
115

65
105

55
85

current RAS = VILo
A cycling IpC E min.

CDR refresh current RAS cycling
IRC= min.
Data transfer curren t
RAS, CAS cycling IRC = min.

lCC6

0

X

ICCJ2

X

0

min.
-10
-10
2.4

max.
10
10

-

0.4

Symbol

Parameter
Input leakage
Output leakage
Output high voltage/OH=-2mA
Output low voltage IOL =4.2mA

ILl
ILO
VOH
VOL

-

40
60

SO

Unit
",A
",A
V
V

• INPUT/OUTPUT CAPACITANCE
Parameter
Address
Clocks
I/O, SI/O

414

Symbol

typo

max.

CIl
CI2
CliO

-

5
5
7

-

-

Unit
pF
pF
pF

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 5 3 4 6 1 Series

• ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING
CONDITIONS (To =0 to +70°C, VCC=5V±1O%, VSs=OV)1l·101.111
Parameter
Random Read or Write Cycle Time
Read-Modify-Write Cycle Time
Page !dode Cycle Time
Access Time from RAS
Access Time from CAS
Output Buffer Turn Off Delay referenced to CAS
Transition Time (Rise and Fall)
RAS Precharge Time
RAS Pulse Width
CAS Pulse Width
RAS to CAS Delay Time
RAS Hold Time
CAS Hold Time
CAS to RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
Write Command Setup Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Da ta-in Setup Time
Data-in Hold Time
Read Command Setup Time
Read Command Hold Time
Read Command Hold Time referenced to RAS
Refresh Period
RAS Pulse Width (Read-Mbdify-Write Cycle)
CAS to WE Delay
CAS Setup time (CAS-before-RAS refresh)

Symbol
tRC
tRwC
tpc
tRAC
tCAC
tOFFl
tT
tRP
tRAS
tCAS
tRcD
tRSH
tCSH
tCRP
tASR
tRAH
tASC
tCAH
twcs
tWCH
twp
tRWL
tCWL
tDS
tDH
tRCS
tRCH
tRRH
tREF
tRws
tCWD
tCSR

CAS Hold Time (CAS-before-RAS refresh)
tCHR
RAS Precharge to CAS Hold Time
t~pc
CAS Precharge Time
tcp
Access Time from OE
tOAC
Output Buffer Turn-off Delay referenced to OE tOFF2
OE to Data-in Delay Time
tODD
OE Hold Time referenced to WE
tOEH
Data-in to CAS Delay Time
tDZC
Data-in to OE Delay Time
tDZO
OE to RAS Delay Time
tORD
Serial Clock Cycle Time
tscc
Access Time from SC
tSCA
Access Time from SOE
tSEA
SC Pulse Width
tsc

HM53461-10

HM53461-12

HM53461-15

min.

max.

max.

min.

max.

190
260
70

-

min.
220
300
85

-

260
355
105

-

-

-

0
3
80
100
50
25
50
100
10
0
15
0
20
0
25
15
35
35
0
25
0
0
10

170
85
10
20
10
10

100
50
25
50

120

-

-

60
30
50

-

0
3

-

-

0
25
0
0
10

10000
10000
50

-

-

-

4
10000

-

-

-

-

-

90
120
60
25
60
120
10
0
15
0
20
0
25
20
40
40

-

-

200
100
10
25
10
15

0
3

-

100
150
75
30
75
150
10
0
20
0
25
0
30
25
45
45

-

0
30
0
0
10

-

10000
10000
60
-

-

-

4
10000

-

10
30
10
20

-

ns

-

150
75
40
50

10000
10000
75

-

-

-

245
125

4
10000

-

-

-

30

-

0
2S
10
0
0

2S

0
30
15
0
0
40
40

-

-

40
30

-

60
40

10

-

10

-

3S

-

40

-

-

40
2S

10

-

35
30

-

-

-

-

0
40
20
0
0
45
60

Unit Note

40
40

-

-

-

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

2, 3
3,4
5
6

7

8

9
8,9

8

10
10

(to be continued)

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

415

HMS3461 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --

Parameter
SC Precharge Width
Serial Data-out Hold Time after SC High
Serial Output Buffer Turn-off Delay from SOE
Serial Data-in Setup Time
Serial Data-in Hold Time
DT to RAS Setup Time
DTto RAS Hold Time(Read Transfer Cycle)
DT to RAS Hold Time
DT to CAS Hold Time
Last SC to DT Delay Time
First SC to DT Hold Time
DT to RAS Delay Time
WE to RAS Setup Time
WE to RAS Hold Time
I/O to RAS Setup Time
I/O to RAS Hold Time
Serial Output Buffer Turn-off Delay from RAS
SC to RAS Setup Time
RAS to SC Delay Time
Serial Data Input Delay Time from RAS
Serial Data Input to DT Delay Time
SOE to RAS Setup Time
SOE to RAS Hold Time
Serial Write Enable Setup Time
Serial Write Enable Hold Time
Serial Write Disable Setup Time
Serial Write Disable Hold Time
DT to Sout in Low-Z Delay Time

Symbol
ISCp
ISOH
ISEZ
ISIS
ISIH
IDTS
IRDH
IDTH
ICDH
ISDD
ISDH
IDTR
IWS
IWH
IMS
IMH
ISRZ
ISRS
ISRD
ISID
ISZD
IES
IEH
ISWS
ISWH
ISWIS
ISWIH
IDLZ

Notes)
1. AC measurements assume tT=Sns.
2.Assumes that IRCD~IRCD(max). If IRCD is greater
than the maximum recommended value shown in this
table, I RAC exceeds the value shown.
3. Measured with a load circuit equivalent to 2TTL loads
and 100pF.
4. Assumes that I RCD~I RCD(max).
S. tOFF(max) defines the time at which the output
achieves the open circuit condition and is not referenced
to output voltage levels.
6. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are
measured between VIH and VIL'
7.0peration with the IRCD(max) limit insures that IRAC
(max) can be met, IRCD(max) is specified as a reference
point only, if IReD is greater than the specified tReD
(max) limit, then access time is controUed exclusively be

HM53461-10
max.
min.
10
10
0
0
15
0
80
15
20
5
2S
10
0
15
0
15
10
30
25
50
0
0
15
0
35
0
35
5

25

-

-

-

-

-

50

-

-

HM53461-12
max.
min.
10
10
0
0
20
0
90
15
30
S
2S
10
0
15
0
15
10
40
30
60
0
0
15
0
35

2S

-

HM53461-15
max.
min.
10
10
0
0

-

2S

-

0
110

-

60

-

-

20
4S
10
30
10
0
20
0
20
10
45
35
75
0
0
20
0
55

0
3S

-

-

0
55

10

-

10

30

-

-

75

-

-

-

-

Unit Note
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

and I CWD are not restrictive operating parameters.
They are included in the data sheet as electrical characteristics only: if twcs~ twcs(min), the cycle is an early
write cycle and the data out pin will remain open circuit
(high impedance) throughout the entire cycle; if t CWD
~lcWD(min), the cycle is a read/write and the data
output will contain data read from the selected ceU; if
neither of the above sets of conditions is satisfied, the
condition of the data out (at access time) is indeterminate.
9. These parameters are referenced to CAS leading edge in
early write cycle and to WE leading edge in delayed
write or read-modify-write cycles.
10.Measured with a load circuit equivalent to 2TTL and
50pF.
l1.An L'litial pause of 1001'S is required after power-up.
Then execute at least 8 initialization cycles.
8.twcs

ICAC.

~HITACHI
416

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 5 3 4 6 1 Series

• WAVE FORMS
• READ CYCLE

IRC

CAS --~-----....

Address

(Output)
1/0

---H-----1--~:c;{.-.J~:..r_..r

1/0

(Input) "'""'...."'1~................"[

E2".a Do not care
• EARLY WRITE CYCLE

IRC

CAS----~+_--------~

Addre••

1/0
(Input)

I/O
(Output)

mDo not care
Note)

*1. When WE is "R" level, the all data on the I/O can be written into the cell.

__
When WE is "L" level, the data on the I/O are not written except for when I/O is 'high' at the falling eclp of RAS.

~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

417

HM53461

Series----------------------------------

• DELAYED WRITE CYCLE
tRe

Address

1/0
(Input)

High-Z

1/0
(Output)

1m Do not care
Note)

* 1. When WE is "H" level, all the data on I/O 1-1/04 can be written into the memory cell.
When WE is "L" level, the data on I/Os are not written exept for when I/O="H" at the falling edge of RAS .

• READ MODIFY WRITE CYCLE

Address

1/0
(Input)

I/O
(Output)

IZZ2I Do not care
Note)

* 1. When WE

is "H" level, all the data on 1/01-1/04 can be written into the memory cell.
__
When WE is "L"level, the data on I/Os are not written except for when I/O="H" at the falling edge of RAS.

~HITACHI
418

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

-------------------------------------------------------------HM53461SeriH
• PAGE MODE READ CYCLE

Address

I/O
(Output)--+il--+--fl'---'=_-'r

I/O
(Input)

IZZ2I 00 not care
• PAGE MODE WRITE CYCLE (Early Write)

Adre ••

I/O
(Input)

I/O
(Output)

m 00 not care
Note)

* 1. When WE is "H" level, all the data on 1/0-1/04 can be written into the memory cell.
When WE is "L" level, the data on I/Os are not written except for when I/O="H" at the falling edge of RAS .

•

HITACHI

Hitachi America, Ltd • Hitachi Plaza • 2000 Sierra POint Pkwy.• Brisbane, CA 94005-1819-. (415) 589-8300

419

HM53461

Series----------------------------------

• PAGE MODE WRITE CYCLE (Delayed Write)

Address

1'0
(Input)

I/O
(Output)

IZZ2I Do not care
Note) *1. When WE is "H" level, all the data on 1/0-1/04 can be written into the memory cell.
When WE is "L"level, the data on 1/0s are not written except for when 1/0="H" at the falling edge of RAS .
• RAS-ONL Y REFRESH CYCLE
IRe

RAS ----~ ~_ _ _~~______~ ~~------------~

Address

I/O
(Output)

I/O

(Input)

IZZl Do not care
~HITACHI
420

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - H M 5 3 4 6 1 Series

• CAS-BEFORE-RAS REFRESH
t.e

Address

WE

/j//////////////////7//////!/fl//fl/,

V/II///I////I/I////////lfl/1TIIIf/I

I/O
(Output)

DT/OE

/f//////1//1//////II1II/1//111///It
IZZiJ Do not care

• HIDDEN REFRESH CYCLE
IRe

tR'

RAS - - ' " ' \ I 1 - _ - - = = - _ - 1

Address

WE

I/O
(Output)

I/O
(Input)

IZZl Do not care

--~

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

421

HM53461

Series-----------------------------------------------------------------

• READ TRANSFER CYCLE (1,*1,*2
IRe

HAS

lRA~

Address

110

(Output)
I/O

(I nput) .J..1.J.-'r"f-L1.J.'"'-'L.L,Lj'"'-1.J.,Ljt..L"rl-'-4.l.,.L.j'+~f_'-'-.....J...jL..£......

SC
SI/O
(Output)
Note

SI/O
(Input) - - - - - - - - - - . . . : : . - - - - - - - - - - - - -

.1) In the case that the previous data transfer cycle was read transfer.

IlZ2I

Do not care
.2) Assume that SOE is "L" level.
.3) CAS and SAM start address need not be supplied every cycle, only when it is desired to change to a new SAM start address .

• READ TRANSFER CYCLE (2,*1,*2
I",

HAS

CAS

Address

WE
I/O
(Output)
I/O
(Input)
DT/OE
SC

SI/O
(Output)

IZZ2I Do not care

~ Inhibit rising transient
Note)
.1) In the case that the previous data transfer cycle was write transfer or pseudo transfer.
02) Assume that SOE is "L" level,
.3) CAS and SAM start address need not be supplied every cycle, only when it is desired to change to a new SAM start address.

SI/O
(Input)

~HITACHI
422

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra POint Pkwy' Brisbane, CA 94005-1819. (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 5 3 4 6 1 Series

• PSEUDO TRANSFER CYCLE

Address

SC
SIlO

(Input)

--t--t---=':""""---t;/

l"-~.L..L..I...I.-'-'~

IZZ2I Do not care
~

SI/O

Note) *1. (Output) ---.1\

Inhibit rising transient

"\,4.."j"'...I..'-f

CAS and SAM start address need not be supplied every cycle, only when it is desired to change to a new SAM start address .

• WRITE TRANSFER CYCLE
INc

Address

SC

SIlO
(Input)

mDonotcare
SIiO

High-Z

(Output) - - - - - - - - - - - - - " - - - - - - - - - - - - - -

m Inhibit rising transient

Note) *1.
CAS and SAM start Address need not be supplied every cycle, only when it is desired to change to a new SAM start Address.

~HITACHI
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

423

Serie8-----------------------------------------------------------------

HM53461

• SERIAL READ CYCLE

50E - - - - - - - '

5C

5{'0
(Output)

I2'ZJ Do not care
• SERIAL WRITE CYCLE

50E

----------:-----1

SC

51/0
(Input)

---""
~Donotcare

~HITACHI
424

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM53462 S e r i e s - - - - - - 65,536-word x 4 bits Multipart CMOS Video RAM (with Logic operation mode)
The HM53462 is a 262, 144 bit multipart memory equipped
with a 64k-word x 4 bit Dynamic RAM port and a 256-word x
4-bit Serial Access Memory (SAM) port. The SAM port is connected to an internal 1,024-bit data register through a 256-word
x 4-bit serial read or write access control. In the read transfer
cycle, the memory cell data is transferred from a selected word
line of the RAM port to the data register. The RAM port has a
write mask capability in addition to the conventional operation
mode. Write bit selection out of 4 data bit can be achieved.
RAM port has another new function, logic operation capability.
By this function logic operation between memory data and input
data can be done in one cycle. Utilizing the Hitachi 2~m CMOS
process, fast serial access operation and low power dissipation are
realized. All inputs and outputs, including clocks, are TTL
compatible.

HM53462P Series

(DP-24A)
HM53462ZP Seires

• FEATURES
•
•
•
•

•

Multiport organization
(RAM; 64k-word x 4 bit and SAM; 256-word x 4 bit)
Double layer polysilicon/polyicide n-well CMOS process
Single 5V (±10%)
RAM; 380 mW max.
Low powr Active
SAM; 220 mW max.
Standby
40 mW max.
Access Time RAM; 100ns/120ns/150ns
SAM; 40ns/40ns/60ns

(ZP-24)

•

Cycle Time Random read or write cycle time (RAM)
190ns/220ns/260ns
Serial read or write cycle time (SAM)
40ns/40ns/60ns
• TTL compatible
• 256 refresh cycles .. 4ms
• Refresh function
RAS - only refresh
CAS - before - RAS refresh
Hidden refresh
• Bidirectional data transfer operation (RAM ~ SAM)
• Fast serial access operation asynchronized with RAM port except data transfer cycle
• Real time read transfer capability
• Write mask mode capability
• Logic operation capability between Din and Dout
• SAM organization can be changed to 1024 x 1

• ORDERING INFORMATION
Type No.

Access Time

Package

HM53462P-10
HM53462P-12
HM53462P-15

lOOns
l20ns
l50ns

400 mil 24 pin Plastic
DIP

HM53462ZP-10
HM53462ZP-12
HM53462ZP-15

lOOns
l20ns
l50ns

24 pin Plastic ZIP

~HITACHI
Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra-Point Pkwy_ • Brisbane. CA 94005-1819. (415) 589-8300

425

HM 53462 Series

• PIN ARRANGEMENT

•

HM53462P Series
SC

v"
SI/O.

51/0,

•

•

HM53462ZP Series

1/03

104
SI;03

SOE
SI/04

SC

SIlO,

9 SI/02

11 1/01
I/O,

I/O.

I/o,

I/O,

13
15
17
19
21
23

WE

A6

Al

AI

Az

AI

A,

r((

A7

WE
A6
A4
A7
A2
AO

PIN DESCRIPTION
Pin Name
AO - A7
1/01 - 1/04
SI/Ol - SI/04
RAS
CAS
SC
WE
DT/OE
SOE

Vee
VSS

Function
Address Inputs
RAM Port Data Input/Output
SAM Port Data Input/Output
Row Address Strobe
Column Address Strobe
Serial Clock
Write Enable
Data Transfer/Output Enable
SAM Port Enable
Power Supply
Ground

(Bottom View)

(Top View)

• BLOCK DIAGRAM

Dout

Memory Array

(256X256)

Are

In

High- Z State.

BY 4 Mode 256X4
(Normal Mode)

~HITACHI
426

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra POint Pkwy. Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 5 3 4 6 2 Series

• ABSOLUTE MAXIMUM RATINGS

Voltage on any pin relative to V55 . . . . . . . . . . .. -1 V to +7V
Power supply voltage relative to V55 . . . . . . . . . . -O.SV to +7V
Operating temperature, Ta (Ambient) . . . . . . . . . oOe to +70 0e
Storage temperature . . . . . . . . . . . . . . . . . . _55° e to +125° e
Short circuit output current . . . . . . . . . . . . . . . . . . . . SOmA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

• INPUT/OUTPUT CAPACITANCE
Parameter
Address
Oocks
I/O. SIlO

Symbol
CI I
CIt

typo

CliO

-

-

-

max.
5
5

7

Unit
pF
pF
pF

RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 to +70°C)
Symbol

Parameter
Supply voltage
Input High voltage
Input Low voltage

VCC
VIH
V/L

min.
4.5
2.4

typo

max.

5.0

_0.5*'

-

5.5
6.5
0.8

-

Unit
V
V
V

ss.

Notes) 1. All voltages referenced to V
2. -3.0V for pulse width ;£ IOns.

• DC ELECTRICAL CHARACTERISTICS (Ta
Symbol

RAM PORT

=0 to +70°C, Vee =SV ± 10%, Vss =OV)

SAM PORT
Standby Active
0

-10

HM53462
-12

HM53462
-15

Unit

X

70

60

50

rnA

80
7

50
90
60
100

100
7
40
50
90
40
80
50
90

35
65
40
70

rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
mA

75
115

65
105

55
85

rnA
rnA

HM53462

Operating current RAS, CAS cycling
tRC= min.

ICCI
ICC7

X

0

110

Standby current RAS, CAS = VIH

ICC2

0

X

Iccs
ICC3
ICC9
ICC4
IcclO
Iccs
ICCl1
ICC6

X

0

0

X

7
40
60
100

RAS only refresh curren t
CAS = VIH.RAScyclingtRC=min.
~ mode

current RAS
CAS cycling tpc E min.

=VIL'

eBR refresh current RAS cycling
tRC=min.
Data transfer current
RAS, CAS cycling tRC =min.
Parameter
Inpu t leakage
Ou tpu t leakage
Output high voltage IOH a - 2 mA
Output low voltage IOL = 4.2 rnA

X

0

0

X

X

0

0

X

X

0

0

X

X

0

Symbol

min.

ILl

-10

ho

-10
2.4

max.
10
10

ICC12

VOH
VOL

-

•

0.4

30
40
70

Unit
,..A
,..A
V
V

HITACHI

Hitachi America, Ltd • Hitachi Plaza· 2000 Sierra Point Pkwy· Brisbane, CA 94005-1819 • (415) 589-8300

427

HM53462 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING
CONDITIONS (Ta =0 to +70°C, Vee =5V ± 10%, Vss =OV)IJ,IO),11)
Parameter

Symbol

HM53462
-10
min.
max.

HM53462
-12
min.
max.

HM53462
-15
min.
max.

Unit

Note

Random Read or Write Cycle Time
Read-Modify-Write Cycle Time
Page Mode Cycle Time

tRC

190

-

220

-

260

-

tRWC
tpc

260

-

300

355

-

70

-

85

-

105

-

Access Time from RAS

tRAC

100

-

120

-

150

ns

2,3

Access Time from CAS

tCAC

-

50

-

60

-

75

ns

3,4

Out~Buffer

Turn Off Delay referenced

to CAS
Transition Time (Rise and Fall)

ns
ns
ns

tOFFI

0

25

0

30

0

40

ns

5

tT

3

50

3

50

3

50

ns

6

tRP

80

-

90

-

100

-

ns

RAS Pulse Width
CAS Pulse Width

tRAS

100

120

10000

ns

SO

60

10000
10000

150

tCAS

10000
10000

75

RAS to CAS Delay Time
RAS Hold Time

tRCD

25

50

25

60

30

10000
75

ns
ns

tRSH

50

tCSH

100

ns
ns

RAS Precharge Time

75

-

150

-

10

-

10

-

0

-

ns

0

CAS Hold Time
CAS to RAS Precharge Time
Row Address Setup Time

tCRP

10

tASR

0

-

Row Address Hold Time

tRAH

15

-

15

-

20

-

tASC

0

-

0

-

0

-

ns
ns

20

-

25

-

ns

0

-

0

25

-

30

20
40

-

25
45

Column Address Setup Time
Column Address Hold Time
-Wnte Command Setup Time
Wnte Command Hold Time

- -

Write Command Pulse Width
Wnte Command to RAS Lead Time
Write Command to CAS Lead Time

----

Data-in Setup Time
Data·in Hold Time
Read Command Setup Time
Read Command Hold Time
Read Command Hold Time referenced
to RAS
Refresh Period
RAS Pulse Width
(Read-Modify-Write Cycle)
CAS to WE Delay
CAS Setup Time
(CAS - before - RAS refresh)
CAS Hold Time
(CAS - before - RAS refresh)
RAS Precharge to CAS Hold Time
CAS Precharge Time
Access Time from OE
out~

Buffer Turn·off Delay referenced
to
OE to Data·in Delay Time

tCAH

20

twcs

0

tWCH
twp

25

tRWL

15
35

tCWL

35

tDS

0

tDH

25

60
120

-

ns

-

ns

-

ns
ns
ns

40

-

0

-

0

ns

9

-

-

25

30

-

0

ns
ns

8,9

0

-

0

-

0

-

ns

10

-

10

-

ns

45

tRCS

0
0

tRRH

10

tREF

-

tRWS

170

10000

200

10000

245

tCWD

85

-

100

-

125

-

ns

tCSR

10

-

10

-

10

-

ns

tCHR

20

-

25

-

30

-

ns

tRPC

10

-

10

-

ns

10

-

10

tcp

15

-

20

40

ns
ns

40

ns

tOAC

-

30

-

0

tODD

25

OE Hold Time referenced to WE

tOEH

10

Data·in to CAS Delay Tim~
Data·in to OE Delay Time
OE to RAS Delay Time

tDZC
tDZO

0
0

-

tORD

35

-

4

-

25

tOFF2

8

ns

tRCH

4

7

35
30

0

-

15
0

-

0
0

40

-

ns

0
40

0

ms

-

-

30

4

10000

20

45

-

-

8

ns
ns
ns
ns
-

ns
(to be continued)

$
428

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M S 3 4 6 2 Series
Parameter

HM53462
-10

Symbol

min.

max.

HM53462
-12
min.

HM53462
-15

min.

max.

Unit

Serial Cloc k Cycle Time

tscc

40

-

40

-

60

-

ns

Access Time from SC

tSCA

40

-

40

-

60

Access Time from SOE

tSEA

-

25

-

30

-

40

ns
ns

tsc

10

-

10

-

10
10

-

ns
ns

10

-

ns
ns

SC Pulse Width
SC Precharge Width

,

tscp

10

-

10

-

Serial Data-out Hold Time after SC High
Serial Output Buffer Turn-off Delay
from SOE
Serial Data-in Setup Time

tSOH

10

-

10

-

tSEZ

0

25

0

25

0

30

tSIS

0

-

0

0

-

ns

Serial Data-in Hold Time
DT to RAS Setup Time

tSIH

15

20

25

0

0

-

ns

tDTS

-

-

DT to RAS Hold Time
(Read Transfer Cycle)

tRDH

80

-

90

-

110

-

ns

rDTH

15

-

15

-

20

-

tCDH

20

-

-

45

-

tSDD
rSDH

5
25
10

10

-

10
30

tDTR

0

-

30
5

ns
ns

0

-

rWH

15

-

15

-

rMS

0

-

0

-

15

-

15

-

DT to RAS Hold Time
DT to CAS Hold Time
Last SC to DT Delay Time
First SC to DT Hold Time
DT to RAS Delay Time
WE to RAS Setup Time
WE to RAS Hold Time

rJII§~l

--c-----'-

1/0 to RAS Setup Time
1/0 to RAS Hold Time
Serial Output Buffer Turn off Delay
from RAS
SC to RAS Setup Time
RAS to SC Delay Time
---

..

--~

rMH
-

SOE to RAS Setup Time
SOE to RAS Hold Time
Serial Write Enable Setup Time

,

!

I

-

10
0

-

20
0

-

20

-

60

10

75

ns

-

45

-

25

-

30

35

-

rSID

SO

-

60

75

-

tSZD

0

-

0

-

ns
ns

0

-

0

0

-

0

-

15

-

15

-

20

-

~EL.. tEH

-------

ns
ns
ns
ns
ns
ns
-- - - - - ns

10

I

10

-

40

~
30

10

ns

50

- - I-tSRS
rSRD
--_.-

--------

0

-

rSRZ

Serial Data Input Delay Time from RAS
Serial Data Input to DT Delay Time

I

25

I

Note

max.

.-

rSWS

0

-

0

-

0

-

Serial Write Enable Hold Time

tSWH

35

-

35

-

55

Serial Write Disable Setup Time

rSWIS

0

-

0

-

0

Serial Write Disable Hold Time

rSWIH

35

-

35

55

DT to Sout in Low-Z Delay Time

tDLZ

5

-

10

-

-

10

ns
ns

-

_.

----

ns
ns
ns
ns
ns
ns
ns

Notes)

1. AC measurements assume tT =5ns.
2. Assumes that tRCD ~ tRCD (max). If rRCD IS greater
than the maximum recommended value shown In this
table, rRACexceeds the value shown.
3. Measured with a load circuit equivalent to 2TTL loads
and 100 pF.
4. Assumes that tRCD ~ rRCD (max).
5. tOFF (max) defines the time at which the output
achieves the open circuit condition and IS not referenced to output voltage levels.
6. vIH (min) and V/L (max) are reference levels for
measuring timing of input signals. Also, transition
times are measured between V IH and V IL'
7. Operation with the rRCD (max) limit insures that
tRAC (max) can be met, tRCD (max) is specified as a
reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled
exclusively be tCAC'
8. twcs and tcwD are not restrictive operating para-

meters. They are included in the data sheet as electrical charactenstics only: if rWCS f; twcs (min), the
cycle is an early write cycle and the data out pin will
remain open circuit (high impedance) throughout the
entire cycle; if tCWD f; tCWD (mIn), the cycle is a
read/write and the data output will contain data read
from the selected cell; if neither of the above sets of
conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
9. These parameters are referenced to CAS leading edge
in early wnte cycle and to WE leading edge in delayed
write or read-modify-write cycles.
10. Measured with a load circuit equivalent to 2TTL and
50 pF.
11. After power-up, pause for more than 100"s and
execute at least 8 initialization cycles. Then execute
at least one logic reset cycle including write mask
reset (on the falling edge of RAS, WE = "Low" and
1/01 - I/O = "High"), and execute one or more transport cycle for initiation of SAM port.

~HITACHI
Hitachi America, Ltd • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

429

HM53462

Serie8----------------------------------

• WAVE FORMS
•

tH<

RAS

READ CYCLE

Address

(Output)
1/0

-----Irt-----------~------~~~--~~~~~

110
(Input)

•

:...I:;."t.~4~""'''-~

rza Do not care

EARLY WRITE CYCLE

CAS------~--------------~

Address

WE

10
(Input)

10
(Output)

I2Za Do not care
Note) *1. When WE is "H" level, the all data on the I/O can be written into the cell. When WE
is "L" level, the data on the I/O are not written except for when I/O is "H"level at
the falling edge of RAS.

~HITACHI
430

Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra POint Pkwy. Brisbane, CA 94005·1819 • (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM53462 Series

• DELAYED WRITE CYCLE
IRe

Address

110
(Input)

I/O
High-Z
(Output)--------------,;;...----------------

1m

Do not care
Note) *1. When WE is "H"level, all the data on 1/01-1/04 can be written into the memory celL
When WE is "L" level, the data on I/Os are not written except for when I/O • "H" at the falling edge of
RAS.

•

READ MODIFY WRITE CYCLE

Address

1/0
(Input)

1'0
(Output)

IZZ2I

Do not care
Note) *1. When WE is "H" level, all the data on I/O I -1/04 can be written into the memory cell.
When WE is "L" level, the data on I/Os are not written except for when I/O· "H" at the falling edge of
RAS.

~HITACHI
Hitachi America, Ltd • Hitachi Plaza· 2000 Sierra Pomt Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

431

HM53462

•

Series----------------------------------

PAGE MODE READ CYCLE

Address

I/O
(Output)

I/O
(Input)

•

PAGE MODE WRITE CYCLE (Early Write)

CAS

--++-';;;;';-L

Adress

I/O
(Input)

I/O
(Output)

mDonot care
Note) *1. When WE is "H" level, all the data on 1/01-1/04 can be written into the memory cell.
When WE is "L" level, the data on I/Os are not written except for when I/O = "H" at the falling edge of
RAS.

~HITACHI
432

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HM53462 Series

•

PAGE MODE WRITE CYCLE (Delayed Write)

Address

1'0
(Input)

10
10utput)

IZZ2I Do not care
Note)

* I. When WE is "H" level, all the data on I/O 1-1/04 can be written into the memory cell.
When WE is "1." level, the data on I/Os are not written except for when I/O = "H" at the falling edge of
RAS .

•

RAS-ON L Y REFRESH CYCLE
tH,

Address

I/O
(Output)

IZn Do not care

~HITACHI
Hitachi America, Ltd • Hitachi Plaza' 2000 Sierra POint Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300

433

HM53462 S e r i e s - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ __

• ~-BEFORE-~ REFRESH CYCLE
IRe

tRP

I/O
(INPUT)

7

I/O
HIGH-Z
(OUTPUT)-------------.;,;;;.;;..;.;..;;;,...----------

DTIOE

zmz7l/l//l/Ollllll7lZZOlllO
FllA

•

Do not care

HIDDEN REFRESH CYCLE
IX(

IHe
IH".,

RAS - - - " -

Address

tORD

VALID

1'0
(Output)

110
(Input)

Dour

High-Z

rn

Do not care

.HITACHI
434

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 5 3 4 6 2 Series

• READ TRANSFER CYCLE (11- 1 ,-2

IH(

RAS

Address

I/O
(Output)

110
(Jnput)

-4.1.J.~f-LI.J..L..l[..LL.I.....L..I.J.L.I.....L..~....L..I.J..L..l~t.l::L.I.....L..'""L.I.....L..'-

SC
51/0
(Output)

SI/O

(lnput)----------....;.;,=...;;;,.------------

IZZlI

NOTE *1) In the case that the previous data transfer cycle was read transfer.
Do not care
*2) Assume that SOE is "Low".
*3) CAS and SAM start Address need not be supplied every cycle, only when it is desired to change to a new SAM

start Address .

• READ TRANSFER CYCLE (21- 1,-2
IN ,-.

'H'

Address

I/O
(Qutput)

I/O
(Input)

51/0
(Output;

..t..1.L£f-~.I..I..u.. .'"'-I.LI.L.I..I..I..I.LIi,t,J..u..u.i.LJt.,I,'u..'"'-I..L.I..L.LLI.LL.

1t:G.~~------_:_j-~(1u.'J.l)

IZZ2I Do not care

m Inhibit nsing transient

SIlO
(Input)

NOTE *1) In the case that the previous data transfer cycle was read transfer.

__
*2) Assume that SOE is "Low"
*3) t;,\S and SAM start Address need not be supplied every cycle, only when it is desired to change to a new SAM
start Address.

•

HITACHI

Hitachi America. Ltd. - Hitachi Plaza - 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

435

HM53462 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• PSEUDO TRANSFER CYCLE
I"

Address

5C
510

(Input) --+-+---:----~:y

l\L-.L..L..L...I....l...I:....c...L...U

IlZ2I Do no t care

m Inhibit rising transient

51'0
(Output)

*1) CAS and SAM start address need not be supplied every cycle, only when it is desired to change to a new SAM
start address .
• WRITE TRANSFER CYCLE
IRe

RAS

CAS

Address

WE

DT/OE

SOE

SC

SilO
(Input)
SIlO
(Output)

U2!Donotcare

High-Z

m

Inhibit rising transient

*1) CAS and SAM start address need not be supplied every cycle, only when it is desired to change to a new SAM
start address.

~HITACHI
436

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 5 3 4 6 2 Series

• SERIAL READ CYCLE

SOE _ _ _ _ _ _J

SC

SIO
(Output I

IZZiJ Do not care
• SERIAL WRITE CYCLE

SOE - - - - - - - - - - - - ' \

SC

SI/O
(Input)

----'

UL1 Do not care
•

ELECTRICAL AC CHARACTERISTICS (Logic operation mode)
Parameter

Write cycle time
RAS pulse width in write cycle
CAS pulse width in write cycle
CAS" hold time in write cycle
RAg hold time in write cycle
Page mode cycle time (Write cycle)
CAS""hold time
(Logic operation set/reset cycle)
CAS hold time from RAg precharge
(x4 .... xl set cycle)

HM53462-10
min.
max.
230
140
10000
80
10000
140
80
100

Symbol
tFRC
tRFS
tCFS
tFCSH
tFRSH
tFPC

HM53462-12
min.
max.
265
165
10000
95
10000
165
95
120

HM53462-15
min.
max.
310
200
10000
105
10000
200
105
135
-

Unit
ns
ns
ns
ns
ns
ns

tFCHR

90

-

100

-

120

-

ns

tPSCH

10

-

10

-

10

-

ns

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brtsbane, CA 94005·1819 • (415) 589-8300

437

HM53462 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

•

•

LOGIC CODE (FCO- 3 are AXO- AX3 in Logic Operation Set Cycle)
FC3

FC2

FCI

FCO

0
0
0
0
0
0
0
0
I
I
I
I
I
I
I
I

0
0
0
0
I
I
I
I
0
0
0
0
I
I
I
I

0
0
I
I
0
0
I
I
0
0
I
I
0
0
I
I

0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I

LOGIC
Write Data
Zero
0
Di'Mi
ANDl
AND2
Di'Mi
X4 -+XI
AND3
Di 'Mi
Di
THROUGH
DI . Mi + Di . Mi
EOR
Symbol

ORI
NOR
ENOR
INVI
OR2
INV2
OR3
NAND
I

Di+Mi
Dl'Mi
Di . Mi + Di ' Mi
Di
Di+ Mi
Mi
Di+ Mi
Di+Mi
ONE

-+

SAM organization changes to 1024 x I

-+

Logic operation mode reset

Di
Mi

: External Data-in
: The data of the memory ceU

LOGIC OPERATION SET/RESET CYCLE (With CAS before RAS refresh)
IRP

IRe

Address

I/O

(Input)

.L...I....J...J..J

HIGH'Z

I/O
(Output)

DT/OE

7//IOllI7lIOI//Z7II7IIOOZOZ
/11Za

Do not care

*1) Logic code AO-A3 (A4-A7: don't care)
*2) Write mask data

~HITACHI
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HItachi America, Ltd .• Hitachi Plaza. 2000 SIerra Point Pkwy· Brisbane, CA 94005·1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 5 3 4 6 2 Series

• LOGIC OPERATION MODE
•

inn

EARLY WRITE CYCLE

tfRSH

tHU)

tresH

Address

I/O
(Input)

I/O
(Output) _____~+--------------------------------------------

Note) * 1. When WE is 'high', the all data on the I/O can be written into the cell.
When WE is 'low', the data on the I/O are not written except for when I/O is 'high'
at the falling edge of RAS .

•

DELAYED WRITE CYCLE

1--_________-=1'-' ":.::."_ _ _ _ _ _ _ _ _ _---1

lfH~H

tHC/)

CAS

rIllA Do not care

IA>"

Address

WE

I/O
(Input)

1i0

VALID DATA IN

HIGH~

Z

(Output)

NOTE I) When WE is "H" level, all the data on 1/01-4 can be written into the memory cell.
~ Do not care
When WE is "L" level, the data on I/Os are not written except for when I/O ="H" at the falling edge of RAS.

~HITACHI
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra POint Pkwy • Brisbane, CA 94005-1819 • (415) 589·8300

439

HM53462 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

•

PAGE MODE WRITE CYCLE (Delayed Write)

Address

[ 0
(Input)

10
(Output)

Note) *1. When WE is 'high', the all data on the I/O can be written into the cell.
When WE is 'low', the data on the I/O are not written except for when I/O is 'high'
at the falling edge of RAS.

•

rn Do not care

PAGE MODE WRITE CYCLE (Early Write)

Address

I/O
(Input)

I/O
(Output) ____

Note)

~+_----------------------~~~-------------------------------

* 1. When WE is 'high', the all data on the I/O can be written into the cell.

IlZlI Do not care

When WE is 'low', the data on the I/O are not written except for when I/O is 'high'
at the falling edge of RAS.

~HITACHI
440

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 5 3 4 6 2 Series

• DESCRIPTION
1. LOGIC OPERATION MODE

HM53462 has an internal logic operation unit
which makes a process of graphics simple. The logic
is determined in "Logic operation set/reset cycle",
and the operation is executed in every write cycle
succeeding to the logic operatIOn set/reset cycle. In
this mode the internal read-modify-write operation
is executed and the cell data is converted into the
new data given by the logic operation between Din
and the old cell data.
2. LOGIC OPERATION SET/RESET CYCLE

A logic operation set/reset cycle is performed by
bringing CAS and WE low when RAS falls (Fig. 1).
The logic code and the bits to be masked are datermined respectively by AxO-3 state and I/O 1-4 state
at the falling edge of RAS. Furthermore, in this
cycle CAS - before - RAS refresh operation is executed, too. In the case of executing the conventional CAS" - before - RAS refresh operation, WF
must be high when RAS falls.
2.1. Logic code

The logic code is shown in Table 1.

CAS

is turned on, at least one logic reset cycle including
write mask reset is required to initialize logic code.
If the lOgic code is (Ax3, Ax2, Axl, AxO) = (0, 0,1,
1), the SAM organization is changed converter (Fig.
2). In the case that the SAM organization is
changed to 1,024 xl, one data transfer cycle is
needed to initialie the SAM selector.
Once the SAM organization is changed to 1024 x 1,
this code is maintained unless power is turned off.
2.2. Write mask

HM53462 has two kinds of mask registers (register
1, 2). The register I is set by bringing WE low at
the falIing edge of RAS during the write cycle, and
the mask data is available only in this cycle. The
register 2 is set by level of I/O In the logiC operation
set/reset cycle, and the mask data is available until
the next logic operation set/reset cycle. If the register I is set during the current logic operation
mode, the mask data of the register 1 is preferred
(that of the register 2 is ignored) and the logic becomes "THROUGH" only in this cycle (Fig. 3).

When power

"L"

Addros

WE
DT/OE

110

IlZZI Do not care
Fig. 1 LOGIC OPERATION SET/RESET CYCLE

.HITACHI
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra POint Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300

441

HM53462S.ies----------------------------------------------------------------Tabla 1. LOGIC CODE (FCO - FC3 are AXO - AX3 in Logic Operation Set Cycle)
FC3

FC2

FCI

FCO

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
I
0
1
0
1
0
1
0
1
0
1
0
1
0
1

LOGIC
Write Data
Zero
0
Di'Mi
ANDI
AND2
Di 'Mi
X4 ~Xl
AND3
Di'Mi
THROUGH
Di
Di • Mi + Di . Mi
EOR
Di+ Mi
ORI
Di 'Mi
NOR
Di . Mi + or· WI
ENOR
INVI
Di
OR2
Di+ Mi
INV2
Mi
OR3
Di+ Mi
Di+Mi
NAND
1
ONE
Symbol

-

~

SAM organiza:!t)n changes to 1024 x 1

~

Logic operation mode reset

Di
Mi

: External Data-in
: The data of the memory 0811

Fig. 2 THE SHIFT WAY OF SAM DATA

SAM Data Register

Senal I/O
l+l

;e
j
L -________________

f

~
i ~
1

a

b

~~ g_;~:_c~~
__

~____________~~~j~d~
1)

By 4 mode (SAM organization: 256 x 4)

,;:,----S
SI02

X

SI03

X
X

SI04

hu

I~

\

I

\

x:::::
x:=

---~

d

X
X
X

g

x::::

x:=

.HITACHI
442

Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM53462 Series
2) By 1 mode (SAM organization: 1024 x 1)

SII:~

~__ A\. ....

r\

I

r::::---\

SI/02 _ _ _ _ _ _ _ _ _ _ _ _....;.;H;::lg;;.h·..:;Z;..__ _ _ _ _ _ _ _ _ _ __
SI/03 _ _ _ _ _ _ _ _ _ _ _ _ _....;.;H.:::'g~h·..:;Z;..__ _ _ _ _ _ _ _ _ _ ___
SI/04 ___________________________H_';;.gh__
Z ___________________________

Fig. 3 EXAMPLE OF LOGIC OPERATION MODE

RAS

LogiC operation
set/reset cycle

Write cycle

r

I

--.
"L"

CAS
WE

I

1/01

\

"L"

"H" \
"O"Wnte

Masked

1/03
1/04

I

"1"Wnte

Logic

Mask reg.2 IS set
J 02,3 .M asked
Assume that the
logiC IS set to

"AND!".

r~

AND!

I
Masked I

Masked

1/02

r

/'"

r~

"H"

"L"

~

W nte cycle

W nte cycle

Write cycle

"H" \

'\

"1"Wnte

"1"Wnte

Masked

"O"Wnte

Masked

Masked

"O"Wflte

THROUGH

r~

,-':";;:\

AND!

" O"Wnte
Masked

I

Masked
"1"Write
AND!

Mask reg.1 is set,
and valid only In
this cycle
J Ol.4:M asked

@HITACHI
Hitachi America, Ltd • Hitachi Plaza' 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300

443

HM538122 Series -

Preliminary

131072-Word x a-Bit Multiport CMOS Video RAM
The HM538122 is a 1-Mbit multiport video RAM equipped with a
128-kword x 8-bit dynamic RAM and a 256-word x 8-bit SAM (serial
access memory).
Its RAM and SAM operate independently and asynchronously. It
can transfer data between RAM and SAM and has a write mask
function.
It also provides logic operation mode to simplify its operation. In
this mode, logic operation between memory data and input data can
be executed by using internal logic-arithmetic unit.

Pin Arrangement
sc

Vss 1

SI/OO

SI/07

SI/01

SI/06

SI/02

SI/05
SI/04

SI/03

BT/OE

SE

1/00

1/07

1/01

1/06

Features

1/02

1/05

•

1/03

1/04

Multiport organization
Asynchronous and simultaneous operation of RAM and SAM
capability
RAM: 128-kword x 8-bit and SAM: 256-word x 8-bit
• Access time
RAM: 100 ns/120 ns/150 ns max
SAM: 30 ns/40 ns/50 ns max
RAM: 190 ns/220 ns/260 ns min
• Cycle time
SAM: 30 ns/40 ns/60 ns min
•

•
•
•
•
•
•

•

Vss 2

WE

Ordering Information
Type No.

Access Time

HM538122JP-I0
HM538122JP-12
HMS38122JP-15

100 ns
120ns
150 ns

Package

400-mil
40-pin
Plastic sm (CP-4OD)

NC

RAS

CAS

NC

NC

A8

AO
Al

A6

Low power
Active

RAM: 385 mW max
SAM: 275 mW max
Standby
40 mW max
High-speed page mode capability
Logic operation mode capability
2 types of mask write mode capability
Bidirectional data transfer cycle between RAM and SAM capability
Real time read transfer capability
3 variations of refresh (8 ms/512 cycles)
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
TIL compatible

NC

NC

AS

18

A4

19

22

A3

Vcc 2 20

21

A7

A2

(Top View)

Pin Description
Pin Name
AD-A8
I/O-I/07
SI/OOSII07
RAS
CAS
WE
DT/OE
SC
SE
Vee
Vss
NC

Function
Address inputs
RAM port data inputs/
outputs
SAM port data inputs/
outputs
Row adress strobe
Column address strobe
Write enable
Data transfer/Output
enable
Serial clock
SAM port enable
Power supply
Ground
No connection

This document contains infonnationon a new product. Specifications and infonnation
contained herein are subject to change without notice.

•
444

HITACHI

Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM538122 Series

Block Diagram

RAM

255

SAM

255

Dout

Pomter

Din

c

Memory
Array

E

"
"0
u

..,

~
ex:

'"

..

~

rnJj

Q)

ex:

"'

'*'
E

Cl